Revert "Revert "VIXL Release 1.13""

This reverts commit 4b3aae88b0dd15a6b999b4c3f7f683fa0aafa631, picks up fixes
from upstream VIXL
- ba1832c Fix the Android.mk.template.
- 838e379 Add a .gitreview for Linaro's server.
- 85a01e7 Fix for undefined uint64_t to int64_t conversion.
and regenerates Android.mk.

Change-Id: Ib3e8b34992b49ce80daf5e37d6634fc24ef047b9
diff --git a/.clang-format b/.clang-format
new file mode 100644
index 0000000..30ef2f6
--- /dev/null
+++ b/.clang-format
@@ -0,0 +1,39 @@
+# Copyright 2016, ARM Limited
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+#   * Redistributions of source code must retain the above copyright notice,
+#     this list of conditions and the following disclaimer.
+#   * Redistributions in binary form must reproduce the above copyright notice,
+#     this list of conditions and the following disclaimer in the documentation
+#     and/or other materials provided with the distribution.
+#   * Neither the name of ARM Limited nor the names of its contributors may be
+#     used to endorse or promote products derived from this software without
+#     specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
+# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+BasedOnStyle: Google
+
+# We keep two empty lines between functions in `.cc` files.
+MaxEmptyLinesToKeep: 2
+
+# Either fit all arguments on the same line, or have one per line.
+# Ideally we would like to allow grouping them when it makes sense. But
+# `clang-format` cannot know what 'makes sense'.
+BinPackArguments: false
+BinPackParameters: false
+
+PenaltyBreakBeforeFirstCallParameter: 500
+PenaltyBreakString: 100
diff --git a/.gitreview b/.gitreview
new file mode 100644
index 0000000..fcf1872
--- /dev/null
+++ b/.gitreview
@@ -0,0 +1,4 @@
+[gerrit]
+host=review.linaro.org
+port=29418
+project=arm/vixl
diff --git a/Android.mk b/Android.mk
index 7b5b6fc..ddcd16e 100644
--- a/Android.mk
+++ b/Android.mk
@@ -83,6 +83,7 @@
   test/test-invalset.cc \
   test/test-runner.cc \
   test/test-simulator-a64.cc \
+  test/test-trace-a64.cc \
   test/test-utils-a64.cc
 
 vixl_cpp_flags := \
@@ -239,6 +240,6 @@
 .PHONY: run-vixl-tests
 run-vixl-tests: vixl-test-runner
 	$(vixl_root)/third_party/android/check_top_level_android_mk.sh
-	$(HOST_OUT)/bin/vixl-test-runner --run_all
-	$(HOST_OUT)/bin/vixl-test-runner --run_all --debugger
+	cd $(vixl_root) && $(ANDROID_BUILD_TOP)/$(HOST_OUT)/bin/vixl-test-runner --run_all
+	cd $(vixl_root) && $(ANDROID_BUILD_TOP)/$(HOST_OUT)/bin/vixl-test-runner --run_all --debugger
 	@echo vixl tests PASSED
diff --git a/CPPLINT.cfg b/CPPLINT.cfg
index 723623b..3f17726 100644
--- a/CPPLINT.cfg
+++ b/CPPLINT.cfg
@@ -34,20 +34,6 @@
 filter=+runtime/string
 filter=+runtime/virtual
 filter=+runtime/vlog
-filter=+whitespace/blank_line
-filter=+whitespace/braces
-filter=+whitespace/comma
-filter=+whitespace/comments
-filter=+whitespace/end_of_line
-filter=+whitespace/ending_newline
-filter=+whitespace/indent
-filter=+whitespace/labels
-filter=+whitespace/line_length
-filter=+whitespace/newline
-filter=+whitespace/operators
-filter=+whitespace/parens
-filter=+whitespace/tab
-filter=+whitespace/todo
 # cpplint.py enables these filters in reversed order.
 filter=-
 linelength=80
diff --git a/README.md b/README.md
index 46042d7..17b81a2 100644
--- a/README.md
+++ b/README.md
@@ -1,4 +1,4 @@
-VIXL: AArch64 Runtime Code Generation Library Version 1.12
+VIXL: AArch64 Runtime Code Generation Library Version 1.13
 ==========================================================
 
 Contents:
@@ -49,10 +49,12 @@
 been tested using GCC on AArch64 Debian, GCC and Clang on amd64 Ubuntu
 systems.
 
-To run the linter stage of the tests, the following software is also required:
+To run the linter and code formatting stages of the tests, the following
+software is also required:
 
  1. Git
  2. [Google's `cpplint.py`][cpplint]
+ 3. clang-format-3.6
 
 Refer to the 'Usage' section for details.
 
@@ -77,6 +79,11 @@
 floating-point operations which do not work correctly, and a number of tests
 fail as a result.
 
+VIXL may not build using Clang 3.7, due to a compiler warning. A workaround is
+to disable conversion of warnings to errors, or to delete the offending
+`return` statement reported and rebuild. This problem will be fixed in the next
+release.
+
 Debug Builds
 ------------
 
@@ -144,27 +151,13 @@
 `--nolint`. This removes the dependency on `cpplint.py` and Git. The `--nolint`
 option is implied if the VIXL project is a snapshot (with no `.git` directory).
 
+Additionally, `tools/test.py` tests code formatting using `clang-format-3.6`.
+If you don't have `clang-format-3.6`, disable the test using the
+`--noclang-format` option.
 
-Building and Running the Benchmarks
------------------------------------
-
-There are three very basic benchmarks provided with VIXL:
-
- 1. bench-dataop, emitting adds
- 2. bench-branch, emitting branches
- 3. bench-branch-link, emitting branch-links
-
-Build these benchmarks using `scons bench-dataop`, `scons bench-branch` and
-`scons bench-branch-link`. This will produce binaries called
-`bench-dataop_sim`, `bench-branch_sim` and `bench-branch-link_sim`. Run these
-with an iteration count argument, for example `./bench-dataop_sim 10000000`. The
-benchmarks do not report a result; time them using the UNIX `time` command.
-
-Build the benchmarks natively for execution on an AArch64 target using `scons
-<benchmark name> simulator=off`. This will produce binaries called
-`bench-dataop`, `bench-branch` and `bench-branch-link`. Run and time these in
-the same way as the simulator versions.
-
+Also note that the tests for the tracing features depend upon external `diff`
+and `sed` tools. If these tools are not available in `PATH`, these tests will
+fail.
 
 Getting Started
 ---------------
@@ -174,7 +167,6 @@
 build all the examples with `scons examples` from the root directory, or use
 `scons --help` to get a detailed list of available build targets.
 
-
 Using VIXL
 ----------
 
diff --git a/SConstruct b/SConstruct
index d1ffa81..13c2db0 100644
--- a/SConstruct
+++ b/SConstruct
@@ -215,13 +215,17 @@
   #   http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57045
   # The bug does not seem to appear in GCC 4.7, or in debug builds with GCC 4.8.
   if env['mode'] == 'release':
-    process = subprocess.Popen(env['CXX'] + ' --version | grep "g++.*4\.8"',
+    process = subprocess.Popen(env['CXX'] + ' --version 2>&1 | grep "g++.*4\.8"',
                                shell = True,
                                stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
-    stdout, stderr = process.communicate()
+    stdout, unused = process.communicate()
     using_gcc48 = stdout != ''
     if using_gcc48:
       env.Append(CPPFLAGS = ['-Wno-maybe-uninitialized'])
+  # On OSX, compilers complain about `long long` being a C++11 extension when no
+  # standard is passed.
+  if 'std' not in env or env['std'] == 'c++98':
+    env.Append(CPPFLAGS = ['-Wno-c++11-long-long'])
 
 
 def ConfigureEnvironment(env):
diff --git a/benchmarks/bench-branch-link-masm.cc b/benchmarks/bench-branch-link-masm.cc
index 115f402..77e92c9 100644
--- a/benchmarks/bench-branch-link-masm.cc
+++ b/benchmarks/bench-branch-link-masm.cc
@@ -37,8 +37,12 @@
   int iterations = 0;
 
   switch (argc) {
-    case 1: iterations = kDefaultIterationsCount; break;
-    case 2: iterations = atoi(argv[1]); break;
+    case 1:
+      iterations = kDefaultIterationsCount;
+      break;
+    case 2:
+      iterations = atoi(argv[1]);
+      break;
     default:
       printf("Usage: %s [#iterations]\n", argv[0]);
       exit(1);
diff --git a/benchmarks/bench-branch-link.cc b/benchmarks/bench-branch-link.cc
index b18cd8b..6174e39 100644
--- a/benchmarks/bench-branch-link.cc
+++ b/benchmarks/bench-branch-link.cc
@@ -38,8 +38,12 @@
   int instructions = 0;
 
   switch (argc) {
-    case 1: instructions = kDefaultInstructionCount; break;
-    case 2: instructions = atoi(argv[1]); break;
+    case 1:
+      instructions = kDefaultInstructionCount;
+      break;
+    case 2:
+      instructions = atoi(argv[1]);
+      break;
     default:
       printf("Usage: %s [#instructions]\n", argv[0]);
       exit(1);
@@ -48,7 +52,7 @@
   MacroAssembler masm(instructions * kInstructionSize);
   InstructionAccurateScope scope(&masm, instructions);
 
-  #define __ masm.
+#define __ masm.
 
   Label target;
   for (int i = 0; i < instructions; i++) {
diff --git a/benchmarks/bench-branch-masm.cc b/benchmarks/bench-branch-masm.cc
index 23cbd1e..ecc1324 100644
--- a/benchmarks/bench-branch-masm.cc
+++ b/benchmarks/bench-branch-masm.cc
@@ -41,8 +41,12 @@
   int iterations = 0;
 
   switch (argc) {
-    case 1: iterations = kDefaultIterationCount; break;
-    case 2: iterations = atoi(argv[1]); break;
+    case 1:
+      iterations = kDefaultIterationCount;
+      break;
+    case 2:
+      iterations = atoi(argv[1]);
+      break;
     default:
       printf("Usage: %s [#iterations]\n", argv[0]);
       exit(1);
diff --git a/benchmarks/bench-branch.cc b/benchmarks/bench-branch.cc
index 706ecfd..a05ea7b 100644
--- a/benchmarks/bench-branch.cc
+++ b/benchmarks/bench-branch.cc
@@ -41,8 +41,12 @@
   int instructions = 0;
 
   switch (argc) {
-    case 1: instructions = kDefaultInstructionCount; break;
-    case 2: instructions = atoi(argv[1]); break;
+    case 1:
+      instructions = kDefaultInstructionCount;
+      break;
+    case 2:
+      instructions = atoi(argv[1]);
+      break;
     default:
       printf("Usage: %s [#instructions]\n", argv[0]);
       exit(1);
@@ -52,7 +56,7 @@
   const int buffer_instruction_count = buffer_size / kInstructionSize;
   MacroAssembler masm(buffer_size);
 
-  #define __ masm.
+#define __ masm.
   // We emit a branch to the next instruction.
 
   int rounds = instructions / buffer_instruction_count;
diff --git a/benchmarks/bench-dataop.cc b/benchmarks/bench-dataop.cc
index cf9faed..32b5b2c 100644
--- a/benchmarks/bench-dataop.cc
+++ b/benchmarks/bench-dataop.cc
@@ -41,8 +41,12 @@
   unsigned instructions = 0;
 
   switch (argc) {
-    case 1: instructions = kDefaultInstructionCount; break;
-    case 2: instructions = atoi(argv[1]); break;
+    case 1:
+      instructions = kDefaultInstructionCount;
+      break;
+    case 2:
+      instructions = atoi(argv[1]);
+      break;
     default:
       printf("Usage: %s [#instructions]\n", argv[0]);
       exit(1);
@@ -52,7 +56,7 @@
   const unsigned buffer_instruction_count = buffer_size / kInstructionSize;
   MacroAssembler masm(buffer_size);
 
-  #define __ masm.
+#define __ masm.
 
   unsigned rounds = instructions / buffer_instruction_count;
   for (unsigned i = 0; i < rounds; ++i) {
diff --git a/doc/changelog.md b/doc/changelog.md
index f053e19..70d0755 100644
--- a/doc/changelog.md
+++ b/doc/changelog.md
@@ -1,6 +1,12 @@
 VIXL Change Log
 ===============
 
+* 1.13
+    + Improve code formatting and add tests using clang-format.
+    + Fix bugs in disassembly of unallocated instruction encodings.
+    + Fix some execution trace bugs, and add tests.
+    + Other small bug fixes and improvements.
+
 * 1.12
     + Bug fixes for toolchain compatibility.
 
diff --git a/doc/supported-instructions.md b/doc/supported-instructions.md
index 2b5b4d8..b9d2e62 100644
--- a/doc/supported-instructions.md
+++ b/doc/supported-instructions.md
@@ -49,28 +49,28 @@
 
 Calculate the address of a PC offset.
 
-    void adr(const Register& rd, int imm21)
+    void adr(const Register& xd, int imm21)
 
 
 ### ADR ###
 
 Calculate the address of a label.
 
-    void adr(const Register& rd, Label* label)
+    void adr(const Register& xd, Label* label)
 
 
 ### ADRP ###
 
 Calculate the page address of a PC offset.
 
-    void adrp(const Register& rd, int imm21)
+    void adrp(const Register& xd, int imm21)
 
 
 ### ADRP ###
 
 Calculate the page address of a label.
 
-    void adrp(const Register& rd, Label* label)
+    void adrp(const Register& xd, Label* label)
 
 
 ### AND ###
@@ -324,72 +324,72 @@
 
 CRC-32 checksum from byte.
 
-    void crc32b(const Register& rd,
-                const Register& rn,
-                const Register& rm)
+    void crc32b(const Register& wd,
+                const Register& wn,
+                const Register& wm)
 
 
 ### CRC32CB ###
 
 CRC-32 C checksum from byte.
 
-    void crc32cb(const Register& rd,
-                 const Register& rn,
-                 const Register& rm)
+    void crc32cb(const Register& wd,
+                 const Register& wn,
+                 const Register& wm)
 
 
 ### CRC32CH ###
 
 CRC-32 C checksum from half-word.
 
-    void crc32ch(const Register& rd,
-                 const Register& rn,
-                 const Register& rm)
+    void crc32ch(const Register& wd,
+                 const Register& wn,
+                 const Register& wm)
 
 
 ### CRC32CW ###
 
 CRC-32 C checksum from word.
 
-    void crc32cw(const Register& rd,
-                 const Register& rn,
-                 const Register& rm)
+    void crc32cw(const Register& wd,
+                 const Register& wn,
+                 const Register& wm)
 
 
 ### CRC32CX ###
 
 CRC-32C checksum from double word.
 
-    void crc32cx(const Register& rd,
-                 const Register& rn,
-                 const Register& rm)
+    void crc32cx(const Register& wd,
+                 const Register& wn,
+                 const Register& xm)
 
 
 ### CRC32H ###
 
 CRC-32 checksum from half-word.
 
-    void crc32h(const Register& rd,
-                const Register& rn,
-                const Register& rm)
+    void crc32h(const Register& wd,
+                const Register& wn,
+                const Register& wm)
 
 
 ### CRC32W ###
 
 CRC-32 checksum from word.
 
-    void crc32w(const Register& rd,
-                const Register& rn,
-                const Register& rm)
+    void crc32w(const Register& wd,
+                const Register& wn,
+                const Register& wm)
 
 
 ### CRC32X ###
 
 CRC-32 checksum from double word.
 
-    void crc32x(const Register& rd,
-                const Register& rn,
-                const Register& rm)
+    void crc32x(const Register& wd,
+                const Register& wn,
+                const Register& xm)
 
 
 ### CSEL ###
@@ -588,7 +588,7 @@
 
 Load word pair with sign extension.
 
-    void ldpsw(const Register& rt, const Register& rt2, const MemOperand& src)
+    void ldpsw(const Register& xt, const Register& xt2, const MemOperand& src)
 
 
 ### LDR ###
@@ -649,21 +649,21 @@
 
 Load word with sign extension from literal pool.
 
-    void ldrsw(const Register& rt, RawLiteral* literal)
+    void ldrsw(const Register& xt, RawLiteral* literal)
 
 
 ### LDRSW ###
 
 Load word with sign extension from pc + imm19 << 2.
 
-    void ldrsw(const Register& rt, int imm19)
+    void ldrsw(const Register& xt, int imm19)
 
 
 ### LDRSW ###
 
 Load word with sign extension.
 
-    void ldrsw(const Register& rt, const MemOperand& src,
+    void ldrsw(const Register& xt, const MemOperand& src,
                LoadStoreScalingOption option = PreferScaledOffset)
 
 
@@ -711,7 +711,7 @@
 
 Load word with sign extension.
 
-    void ldursw(const Register& rt, const MemOperand& src,
+    void ldursw(const Register& xt, const MemOperand& src,
                 LoadStoreScalingOption option = PreferUnscaledOffset)
 
 
@@ -820,14 +820,14 @@
 
 Move to register from system register.
 
-    void mrs(const Register& rt, SystemRegister sysreg)
+    void mrs(const Register& xt, SystemRegister sysreg)
 
 
 ### MSR ###
 
 Move from register to system register.
 
-    void msr(SystemRegister sysreg, const Register& rt)
+    void msr(SystemRegister sysreg, const Register& xt)
 
 
 ### MSUB ###
@@ -969,7 +969,7 @@
 
 Reverse bytes in 32-bit words.
 
-    void rev32(const Register& rd, const Register& rn)
+    void rev32(const Register& xd, const Register& xn)
 
 
 ### ROR ###
@@ -1045,20 +1045,20 @@
 
 Signed long multiply and accumulate: 32 x 32 + 64 -> 64-bit.
 
-    void smaddl(const Register& rd,
-                const Register& rn,
-                const Register& rm,
-                const Register& ra)
+    void smaddl(const Register& xd,
+                const Register& wn,
+                const Register& wm,
+                const Register& xa)
 
 
 ### SMSUBL ###
 
 Signed long multiply and subtract: 64 - (32 x 32) -> 64-bit.
 
-    void smsubl(const Register& rd,
-                const Register& rn,
-                const Register& rm,
-                const Register& ra)
+    void smsubl(const Register& xd,
+                const Register& wn,
+                const Register& wm,
+                const Register& xa)
 
 
 ### SMULH ###
@@ -1072,7 +1072,7 @@
 
 Signed long multiply: 32 x 32 -> 64-bit.
 
-    void smull(const Register& rd, const Register& rn, const Register& rm)
+    void smull(const Register& xd, const Register& wn, const Register& wm)
 
 
 ### STLR ###
@@ -1272,14 +1272,14 @@
 
 System instruction with pre-encoded op (op1:crn:crm:op2).
 
-    void sys(int op, const Register& rt = xzr)
+    void sys(int op, const Register& xt = xzr)
 
 
 ### SYS ###
 
 System instruction.
 
-    void sys(int op1, int crn, int crm, int op2, const Register& rt = xzr)
+    void sys(int op1, int crn, int crm, int op2, const Register& xt = xzr)
 
 
 ### TBNZ ###
@@ -1358,20 +1358,20 @@
 
 Unsigned long multiply and accumulate: 32 x 32 + 64 -> 64-bit.
 
-    void umaddl(const Register& rd,
-                const Register& rn,
-                const Register& rm,
-                const Register& ra)
+    void umaddl(const Register& xd,
+                const Register& wn,
+                const Register& wm,
+                const Register& xa)
 
 
 ### UMSUBL ###
 
 Unsigned long multiply and subtract: 64 - (32 x 32) -> 64-bit.
 
-    void umsubl(const Register& rd,
-                const Register& rn,
-                const Register& rm,
-                const Register& ra)
+    void umsubl(const Register& xd,
+                const Register& wn,
+                const Register& wm,
+                const Register& xa)
 
 
 ### UMULH ###
@@ -1387,9 +1387,9 @@
 
 Unsigned long multiply: 32 x 32 -> 64-bit.
 
-    void umull(const Register& rd,
-               const Register& rn,
-               const Register& rm)
+    void umull(const Register& xd,
+               const Register& wn,
+               const Register& wm)
 
 
 ### UXTB ###
diff --git a/examples/abs.cc b/examples/abs.cc
index 634c375..39b352b 100644
--- a/examples/abs.cc
+++ b/examples/abs.cc
@@ -61,7 +61,7 @@
   int64_t input_value = -42;
   simulator.set_xreg(0, input_value);
   simulator.RunFrom(masm.GetLabelAddress<Instruction*>(&abs));
-  printf("abs(%ld) = %ld\n", input_value, simulator.xreg(0));
+  printf("abs(%" PRId64 ") = %" PRId64 "\n", input_value, simulator.xreg(0));
 
   return 0;
 }
diff --git a/examples/add2-vectors.cc b/examples/add2-vectors.cc
index 4992708..820070a 100644
--- a/examples/add2-vectors.cc
+++ b/examples/add2-vectors.cc
@@ -82,7 +82,7 @@
 }
 
 
-void PrintVector(const uint8_t *vec, unsigned num) {
+void PrintVector(const uint8_t* vec, unsigned num) {
   unsigned i;
   printf("( ");
   if (num > 0) {
@@ -108,14 +108,14 @@
   masm.FinalizeCode();
 
   // Initialize input data for the example function.
-  uint8_t vecA[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
-                    0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
-                    16, 17, 18, 19, 20};
-  uint8_t vecB[] = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
-                    30, 31,
-                    16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
-                    30, 31,
-                    32, 33, 34, 35, 36};
+  // clang-format: off
+  uint8_t vecA[] = {0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12,
+                    13, 14, 15, 0,  1,  2,  3,  4,  5,  6,  7,  8,  9,
+                    10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20};
+  uint8_t vecB[] = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28,
+                    29, 30, 31, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
+                    26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36};
+  // clang-format on
   uint8_t vecC[ARRAY_SIZE(vecA)];
 
   // Check whether the number of elements in both vectors match.
diff --git a/examples/add3-double.cc b/examples/add3-double.cc
index f14947f..3bac582 100644
--- a/examples/add3-double.cc
+++ b/examples/add3-double.cc
@@ -35,8 +35,8 @@
   //    x -> d0
   //    y -> d1
   //    z -> d2
-  __ Fadd(d0, d0, d1);    // d0 <- x + y
-  __ Fadd(d0, d0, d2);    // d0 <- d0 + z
+  __ Fadd(d0, d0, d1);  // d0 <- x + y
+  __ Fadd(d0, d0, d2);  // d0 <- d0 + z
 
   // The return value is already in d0.
   __ Ret();
diff --git a/examples/add4-double.cc b/examples/add4-double.cc
index ac25964..5f637ad 100644
--- a/examples/add4-double.cc
+++ b/examples/add4-double.cc
@@ -76,7 +76,10 @@
   simulator.set_xreg(1, c);
   simulator.set_dreg(1, d);
   simulator.RunFrom(masm.GetLabelAddress<Instruction*>(&add4_double));
-  printf("%ld + %f + %ld + %f = %f\n", a, b, c, d, simulator.dreg(0));
+  // clang-format off
+  printf("%" PRIu64 " + %f + %" PRIu64 " + %f = %f\n",
+         a, b, c, d, simulator.dreg(0));
+  // clang-format on
 
   return 0;
 }
diff --git a/examples/check-bounds.cc b/examples/check-bounds.cc
index 635918e..bf43780 100644
--- a/examples/check-bounds.cc
+++ b/examples/check-bounds.cc
@@ -59,16 +59,21 @@
 
 #ifndef TEST_EXAMPLES
 #ifdef VIXL_INCLUDE_SIMULATOR
-void run_function(Simulator *simulator, Instruction * function,
-                  uint64_t value, uint64_t low, uint64_t high) {
+void run_function(Simulator* simulator,
+                  Instruction* function,
+                  uint64_t value,
+                  uint64_t low,
+                  uint64_t high) {
   simulator->set_xreg(0, value);
   simulator->set_xreg(1, low);
   simulator->set_xreg(2, high);
 
   simulator->RunFrom(function);
-  printf("%ld %s between %ld and %ld\n", value,
+  printf("%" PRIu64 " %s between %" PRIu64 " and %" PRIu64 "\n",
+         value,
          simulator->xreg(0) ? "is" : "is not",
-         low, high);
+         low,
+         high);
 
   simulator->ResetState();
 }
@@ -87,7 +92,7 @@
   masm.FinalizeCode();
 
   // Run the example function.
-  Instruction * function = masm.GetLabelAddress<Instruction*>(&check_bounds);
+  Instruction* function = masm.GetLabelAddress<Instruction*>(&check_bounds);
   run_function(&simulator, function, 546, 50, 1000);
   run_function(&simulator, function, 62, 100, 200);
   run_function(&simulator, function, 200, 100, 200);
diff --git a/examples/crc-checksums.cc b/examples/crc-checksums.cc
index 4fc9556..979d9a6 100644
--- a/examples/crc-checksums.cc
+++ b/examples/crc-checksums.cc
@@ -43,8 +43,8 @@
   // Move input array to temp register so we can re-use w0 as return register.
   __ Mov(x2, x0);
 
-  // Initial remainder for the checksum.  If length=0, then this value will
-  // be returned.
+  // Initial remainder for the checksum. If length=0, then this value will be
+  // returned.
   __ Mov(w0, 0xffffffff);
 
   // Loop for iterating through the array, starting at msg[0].
@@ -66,7 +66,7 @@
 
 #ifndef TEST_EXAMPLES
 
-void runExample(const char *msg) {
+void runExample(const char* msg) {
   // Create and initialize the assembler and the simulator.
   byte assm_buf[BUF_SIZE];
   MacroAssembler masm(assm_buf, BUF_SIZE);
diff --git a/examples/custom-disassembler.cc b/examples/custom-disassembler.cc
index 2663c6f..2187750 100644
--- a/examples/custom-disassembler.cc
+++ b/examples/custom-disassembler.cc
@@ -33,9 +33,8 @@
 
 
 // We override this method to specify how register names should be disassembled.
-void CustomDisassembler::AppendRegisterNameToOutput(
-    const Instruction* instr,
-    const CPURegister& reg) {
+void CustomDisassembler::AppendRegisterNameToOutput(const Instruction* instr,
+                                                    const CPURegister& reg) {
   USE(instr);
   if (reg.IsRegister()) {
     switch (reg.code()) {
@@ -170,11 +169,12 @@
     decoder.Decode(instr);
     printf("\n");
     printf("VIXL disasm\t %p:\t%s\n",
-           reinterpret_cast<void*>(instr), disasm.GetOutput());
+           reinterpret_cast<void*>(instr),
+           disasm.GetOutput());
     int64_t rel_addr =
         custom_disasm.CodeRelativeAddress(reinterpret_cast<void*>(instr));
     char rel_addr_sign_char = rel_addr < 0 ? '-' : ' ';
-    rel_addr = labs(rel_addr);
+    rel_addr = std::abs(rel_addr);
     printf("custom disasm\t%c0x%" PRIx64 ":\t%s\n",
            rel_addr_sign_char,
            rel_addr,
diff --git a/examples/custom-disassembler.h b/examples/custom-disassembler.h
index 4fcc693..4ea1da7 100644
--- a/examples/custom-disassembler.h
+++ b/examples/custom-disassembler.h
@@ -37,10 +37,10 @@
 // - Add comments to some add/sub instructions.
 // - Use aliases for register names.
 // - Add descriptions for code addresses.
-class CustomDisassembler: public Disassembler {
+class CustomDisassembler : public Disassembler {
  public:
-  CustomDisassembler() : Disassembler() { }
-  virtual ~CustomDisassembler() { }
+  CustomDisassembler() : Disassembler() {}
+  virtual ~CustomDisassembler() {}
 
   virtual void VisitAddSubShifted(const Instruction* instr);
 
diff --git a/examples/examples.h b/examples/examples.h
index 8221011..c52ae99 100644
--- a/examples/examples.h
+++ b/examples/examples.h
@@ -25,7 +25,7 @@
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 #ifndef VIXL_EXAMPLE_EXAMPLES_H_
-# define VIXL_EXAMPLE_EXAMPLES_H_
+#define VIXL_EXAMPLE_EXAMPLES_H_
 
 #include "vixl/a64/simulator-a64.h"
 #include "vixl/a64/debugger-a64.h"
@@ -113,7 +113,7 @@
 //   uint64_t demo_function(uint64_t x)
 //
 // This is the example used in doc/getting-started.txt
-void GenerateDemoFunction(MacroAssembler *masm);
+void GenerateDemoFunction(MacroAssembler* masm);
 
 // This function generates and runs code that uses literals to sum the `a` and
 // `b` inputs.
diff --git a/examples/factorial-rec.cc b/examples/factorial-rec.cc
index 5d1e5df..d69e83a 100644
--- a/examples/factorial-rec.cc
+++ b/examples/factorial-rec.cc
@@ -43,7 +43,7 @@
   __ Mov(x1, x0);
   __ Sub(x0, x0, 1);
   __ Push(x1, lr);
-  __ Bl(&entry);    // Recursive call factorial_rec(n - 1).
+  __ Bl(&entry);  // Recursive call factorial_rec(n - 1).
   __ Pop(lr, x1);
   __ Mul(x0, x0, x1);
   __ Ret();
@@ -73,7 +73,9 @@
   uint64_t input_val = 16;
   simulator.set_xreg(0, input_val);
   simulator.RunFrom(masm.GetLabelAddress<Instruction*>(&factorial_rec));
-  printf("factorial(%ld) = %ld\n", input_val, simulator.xreg(0));
+  printf("factorial(%" PRIu64 ") = %" PRId64 "\n",
+         input_val,
+         simulator.xreg(0));
 
   return 0;
 }
diff --git a/examples/factorial.cc b/examples/factorial.cc
index 9df65f1..9ad47b2 100644
--- a/examples/factorial.cc
+++ b/examples/factorial.cc
@@ -37,7 +37,7 @@
   Label loop, end;
 
   __ Mov(x1, x0);
-  __ Mov(x0, 1);     // Use x0 as the accumulator.
+  __ Mov(x0, 1);  // Use x0 as the accumulator.
 
   __ Cbz(x1, &end);  // Nothing to do if the input is null.
 
@@ -71,7 +71,9 @@
   uint64_t input_val = 16;
   simulator.set_xreg(0, input_val);
   simulator.RunFrom(masm.GetLabelAddress<Instruction*>(&factorial));
-  printf("factorial(%ld) = %ld\n", input_val, simulator.xreg(0));
+  printf("factorial(%" PRIu64 ") = %" PRId64 "\n",
+         input_val,
+         simulator.xreg(0));
 
   return 0;
 }
diff --git a/examples/getting-started.cc b/examples/getting-started.cc
index 6cd8bba..38f2924 100644
--- a/examples/getting-started.cc
+++ b/examples/getting-started.cc
@@ -54,7 +54,7 @@
   masm.FinalizeCode();
 
   simulator.set_xreg(0, 0x8899aabbccddeeff);
-  simulator.RunFrom(masm.GetLabelAddress<Instruction*>(&demo_function));
+  simulator.RunFrom(masm.GetLabelAddress<Instruction *>(&demo_function));
   printf("x0 = %" PRIx64 "\n", simulator.xreg(0));
 
   return 0;
diff --git a/examples/literal.cc b/examples/literal.cc
index 02de7ef..49f4966 100644
--- a/examples/literal.cc
+++ b/examples/literal.cc
@@ -70,7 +70,7 @@
 
   // Run the code.
   simulator.RunFrom(masm.GetLabelAddress<Instruction*>(&start));
-  printf("111 + 222 = %ld\n", simulator.xreg(0));
+  printf("111 + 222 = %" PRId64 "\n", simulator.xreg(0));
 
   // Now let's modify the values of the literals.
   automatically_placed_literal.UpdateValue(a, code);
diff --git a/examples/neon-matrix-multiply.cc b/examples/neon-matrix-multiply.cc
index 2619339..9e66a0f 100644
--- a/examples/neon-matrix-multiply.cc
+++ b/examples/neon-matrix-multiply.cc
@@ -124,15 +124,39 @@
   //   float mat1[kLength] = { 1.0f, 52.03f, 4.43f, ... };
   // However, the following way better shows the "column-major" arrangement.
 
-  mat1[0] =   1.0f; mat1[4] =   2.0f; mat1[ 8] =   3.0f; mat1[12] =   4.0f;
-  mat1[1] = 52.03f; mat1[5] = 12.24f; mat1[ 9] = 53.56f; mat1[13] = 22.22f;
-  mat1[2] =  4.43f; mat1[6] =  5.00f; mat1[10] =  7.00f; mat1[14] =  3.11f;
-  mat1[3] = 43.47f; mat1[7] = 10.97f; mat1[11] = 37.78f; mat1[15] = 90.91f;
+  mat1[0] = 1.0f;
+  mat1[4] = 2.0f;
+  mat1[8] = 3.0f;
+  mat1[12] = 4.0f;
+  mat1[1] = 52.03f;
+  mat1[5] = 12.24f;
+  mat1[9] = 53.56f;
+  mat1[13] = 22.22f;
+  mat1[2] = 4.43f;
+  mat1[6] = 5.00f;
+  mat1[10] = 7.00f;
+  mat1[14] = 3.11f;
+  mat1[3] = 43.47f;
+  mat1[7] = 10.97f;
+  mat1[11] = 37.78f;
+  mat1[15] = 90.91f;
 
-  mat2[0] =   1.0f; mat2[4] = 11.24f; mat2[ 8] = 21.00f; mat2[12] = 21.31f;
-  mat2[1] =   2.0f; mat2[5] =  2.24f; mat2[ 9] =  8.56f; mat2[13] = 52.03f;
-  mat2[2] =   3.0f; mat2[6] = 51.00f; mat2[10] = 21.00f; mat2[14] = 33.11f;
-  mat2[3] =   4.0f; mat2[7] =  0.00f; mat2[11] = 84.00f; mat2[15] =  1.97f;
+  mat2[0] = 1.0f;
+  mat2[4] = 11.24f;
+  mat2[8] = 21.00f;
+  mat2[12] = 21.31f;
+  mat2[1] = 2.0f;
+  mat2[5] = 2.24f;
+  mat2[9] = 8.56f;
+  mat2[13] = 52.03f;
+  mat2[2] = 3.0f;
+  mat2[6] = 51.00f;
+  mat2[10] = 21.00f;
+  mat2[14] = 33.11f;
+  mat2[3] = 4.0f;
+  mat2[7] = 0.00f;
+  mat2[11] = 84.00f;
+  mat2[15] = 1.97f;
 
   simulator.ResetState();
   simulator.set_xreg(0, reinterpret_cast<uintptr_t>(output));
@@ -142,20 +166,32 @@
 
   // Print the 4x4 output matrix along with both 4x4 input matrices.
   for (int i = 0; i < kRowSize; i++) {
-    printf("| %8.2f %8.2f %8.2f %8.2f |   "
-           "| %8.2f %8.2f %8.2f %8.2f |       "
-           "| %8.2f %8.2f %8.2f %8.2f |\n",
-             mat1[i],   mat1[4+i],   mat1[8+i],   mat1[12+i],
-             mat2[i],   mat2[4+i],   mat2[8+i],   mat2[12+i],
-           output[i], output[4+i], output[8+i], output[12+i]);
+    printf(
+        "| %8.2f %8.2f %8.2f %8.2f |   "
+        "| %8.2f %8.2f %8.2f %8.2f |       "
+        "| %8.2f %8.2f %8.2f %8.2f |\n",
+        mat1[i],
+        mat1[4 + i],
+        mat1[8 + i],
+        mat1[12 + i],
+        mat2[i],
+        mat2[4 + i],
+        mat2[8 + i],
+        mat2[12 + i],
+        output[i],
+        output[4 + i],
+        output[8 + i],
+        output[12 + i]);
     if (i == 0 || i == 2) {
-      printf("|                                     |   "
-             "|                                     |       "
-             "|                                     |\n");
+      printf(
+          "|                                     |   "
+          "|                                     |       "
+          "|                                     |\n");
     } else if (i == 1) {
-      printf("|                                     | x "
-             "|                                     |   =   "
-             "|                                     |\n");
+      printf(
+          "|                                     | x "
+          "|                                     |   =   "
+          "|                                     |\n");
     }
   }
 
diff --git a/examples/non-const-visitor.cc b/examples/non-const-visitor.cc
index a616f12..b11025c 100644
--- a/examples/non-const-visitor.cc
+++ b/examples/non-const-visitor.cc
@@ -53,7 +53,7 @@
   simulator.set_xreg(1, b);
   simulator.RunFrom(start_instr);
   int64_t res = simulator.xreg(0);
-  printf("foo(%" PRId64", %" PRId64") = %" PRId64"\n", a, b, res);
+  printf("foo(%" PRId64 ", %" PRId64 ") = %" PRId64 "\n", a, b, res);
 
   return res;
 #else
diff --git a/examples/non-const-visitor.h b/examples/non-const-visitor.h
index 7d8d08b..c54fd0c 100644
--- a/examples/non-const-visitor.h
+++ b/examples/non-const-visitor.h
@@ -53,76 +53,76 @@
     mutable_instr->SetInstructionBits(instr_bits);
   }
 
-  // Define the remaining visitors to do nothing.
-#define UNUSED_VISITOR_LIST(V)      \
-  V(PCRelAddressing)                \
-  V(AddSubImmediate)                \
-  V(LogicalImmediate)               \
-  V(MoveWideImmediate)              \
-  V(Bitfield)                       \
-  V(Extract)                        \
-  V(UnconditionalBranch)            \
-  V(UnconditionalBranchToRegister)  \
-  V(CompareBranch)                  \
-  V(TestBranch)                     \
-  V(ConditionalBranch)              \
-  V(System)                         \
-  V(Exception)                      \
-  V(LoadStorePairPostIndex)         \
-  V(LoadStorePairOffset)            \
-  V(LoadStorePairPreIndex)          \
-  V(LoadStorePairNonTemporal)       \
-  V(LoadLiteral)                    \
-  V(LoadStoreUnscaledOffset)        \
-  V(LoadStorePostIndex)             \
-  V(LoadStorePreIndex)              \
-  V(LoadStoreRegisterOffset)        \
-  V(LoadStoreUnsignedOffset)        \
-  V(LoadStoreExclusive)             \
-  V(LogicalShifted)                 \
-  V(AddSubExtended)                 \
-  V(AddSubWithCarry)                \
-  V(ConditionalCompareRegister)     \
-  V(ConditionalCompareImmediate)    \
-  V(ConditionalSelect)              \
-  V(DataProcessing1Source)          \
-  V(DataProcessing2Source)          \
-  V(DataProcessing3Source)          \
-  V(FPCompare)                      \
-  V(FPConditionalCompare)           \
-  V(FPConditionalSelect)            \
-  V(FPImmediate)                    \
-  V(FPDataProcessing1Source)        \
-  V(FPDataProcessing2Source)        \
-  V(FPDataProcessing3Source)        \
-  V(FPIntegerConvert)               \
-  V(FPFixedPointConvert)            \
-  V(Crypto2RegSHA)                  \
-  V(Crypto3RegSHA)                  \
-  V(CryptoAES)                      \
-  V(NEON2RegMisc)                   \
-  V(NEON3Different)                 \
-  V(NEON3Same)                      \
-  V(NEONAcrossLanes)                \
-  V(NEONByIndexedElement)           \
-  V(NEONCopy)                       \
-  V(NEONExtract)                    \
-  V(NEONLoadStoreMultiStruct)       \
+// Define the remaining visitors to do nothing.
+#define UNUSED_VISITOR_LIST(V)          \
+  V(PCRelAddressing)                    \
+  V(AddSubImmediate)                    \
+  V(LogicalImmediate)                   \
+  V(MoveWideImmediate)                  \
+  V(Bitfield)                           \
+  V(Extract)                            \
+  V(UnconditionalBranch)                \
+  V(UnconditionalBranchToRegister)      \
+  V(CompareBranch)                      \
+  V(TestBranch)                         \
+  V(ConditionalBranch)                  \
+  V(System)                             \
+  V(Exception)                          \
+  V(LoadStorePairPostIndex)             \
+  V(LoadStorePairOffset)                \
+  V(LoadStorePairPreIndex)              \
+  V(LoadStorePairNonTemporal)           \
+  V(LoadLiteral)                        \
+  V(LoadStoreUnscaledOffset)            \
+  V(LoadStorePostIndex)                 \
+  V(LoadStorePreIndex)                  \
+  V(LoadStoreRegisterOffset)            \
+  V(LoadStoreUnsignedOffset)            \
+  V(LoadStoreExclusive)                 \
+  V(LogicalShifted)                     \
+  V(AddSubExtended)                     \
+  V(AddSubWithCarry)                    \
+  V(ConditionalCompareRegister)         \
+  V(ConditionalCompareImmediate)        \
+  V(ConditionalSelect)                  \
+  V(DataProcessing1Source)              \
+  V(DataProcessing2Source)              \
+  V(DataProcessing3Source)              \
+  V(FPCompare)                          \
+  V(FPConditionalCompare)               \
+  V(FPConditionalSelect)                \
+  V(FPImmediate)                        \
+  V(FPDataProcessing1Source)            \
+  V(FPDataProcessing2Source)            \
+  V(FPDataProcessing3Source)            \
+  V(FPIntegerConvert)                   \
+  V(FPFixedPointConvert)                \
+  V(Crypto2RegSHA)                      \
+  V(Crypto3RegSHA)                      \
+  V(CryptoAES)                          \
+  V(NEON2RegMisc)                       \
+  V(NEON3Different)                     \
+  V(NEON3Same)                          \
+  V(NEONAcrossLanes)                    \
+  V(NEONByIndexedElement)               \
+  V(NEONCopy)                           \
+  V(NEONExtract)                        \
+  V(NEONLoadStoreMultiStruct)           \
   V(NEONLoadStoreMultiStructPostIndex)  \
-  V(NEONLoadStoreSingleStruct)      \
+  V(NEONLoadStoreSingleStruct)          \
   V(NEONLoadStoreSingleStructPostIndex) \
-  V(NEONModifiedImmediate)          \
-  V(NEONScalar2RegMisc)             \
-  V(NEONScalar3Diff)                \
-  V(NEONScalar3Same)                \
-  V(NEONScalarByIndexedElement)     \
-  V(NEONScalarCopy)                 \
-  V(NEONScalarPairwise)             \
-  V(NEONScalarShiftImmediate)       \
-  V(NEONShiftImmediate)             \
-  V(NEONTable)                      \
-  V(NEONPerm)                       \
-  V(Unallocated)                    \
+  V(NEONModifiedImmediate)              \
+  V(NEONScalar2RegMisc)                 \
+  V(NEONScalar3Diff)                    \
+  V(NEONScalar3Same)                    \
+  V(NEONScalarByIndexedElement)         \
+  V(NEONScalarCopy)                     \
+  V(NEONScalarPairwise)                 \
+  V(NEONScalarShiftImmediate)           \
+  V(NEONShiftImmediate)                 \
+  V(NEONTable)                          \
+  V(NEONPerm)                           \
+  V(Unallocated)                        \
   V(Unimplemented)
 #define DEFINE_UNUSED_VISITOR(Name)                                  \
   virtual void Visit##Name(const Instruction* i) {                   \
diff --git a/examples/sum-array.cc b/examples/sum-array.cc
index 8803962..299a550 100644
--- a/examples/sum-array.cc
+++ b/examples/sum-array.cc
@@ -74,7 +74,7 @@
   masm.FinalizeCode();
 
   // Run the example function.
-  uint8_t data[] = { 2, 45, 63, 7, 245, 38 };
+  uint8_t data[] = {2, 45, 63, 7, 245, 38};
   uintptr_t data_addr = reinterpret_cast<uintptr_t>(data);
   simulator.set_xreg(0, data_addr);
   simulator.set_xreg(1, ARRAY_SIZE(data));
diff --git a/examples/swap-int32.cc b/examples/swap-int32.cc
index 0ea2435..1b58a72 100644
--- a/examples/swap-int32.cc
+++ b/examples/swap-int32.cc
@@ -79,17 +79,21 @@
   simulator.set_wreg(0, 0x11111111);
   simulator.set_wreg(1, 0x22222222);
 
+  // clang-format off
   printf("Before swap_int32:\n"
          "x0 = 0x%" PRIx32 "\n"
          "x1 = 0x%" PRIx32 "\n",
          simulator.wreg(0), simulator.wreg(1));
+  // clang-format on
 
   simulator.RunFrom(masm.GetLabelAddress<Instruction*>(&swap_int32));
 
+  // clang-format off
   printf("After swap_int32:\n"
          "x0 = 0x%" PRIx32 "\n"
          "x1 = 0x%" PRIx32 "\n",
          simulator.wreg(0), simulator.wreg(1));
+  // clang-format on
 
   return 0;
 }
diff --git a/examples/swap4.cc b/examples/swap4.cc
index 808b148..4c48717 100644
--- a/examples/swap4.cc
+++ b/examples/swap4.cc
@@ -67,6 +67,7 @@
   simulator.set_xreg(2, 0x3333333333333333);
   simulator.set_xreg(3, 0x4444444444444444);
 
+  // clang-format off
   printf("Before swap4:\n"
          "x0 = 0x%" PRIx64 "\n"
          "x1 = 0x%" PRIx64 "\n"
@@ -74,9 +75,11 @@
          "x3 = 0x%" PRIx64 "\n",
          simulator.xreg(0), simulator.xreg(1),
          simulator.xreg(2), simulator.xreg(3));
+  // clang-format on
 
   simulator.RunFrom(masm.GetLabelAddress<Instruction*>(&swap4));
 
+  // clang-format off
   printf("After swap4:\n"
          "x0 = 0x%" PRIx64 "\n"
          "x1 = 0x%" PRIx64 "\n"
@@ -84,6 +87,7 @@
          "x3 = 0x%" PRIx64 "\n",
          simulator.xreg(0), simulator.xreg(1),
          simulator.xreg(2), simulator.xreg(3));
+  // clang-format on
 
   return 0;
 }
diff --git a/src/vixl/a64/assembler-a64.cc b/src/vixl/a64/assembler-a64.cc
index 59f8ffc..5227460 100644
--- a/src/vixl/a64/assembler-a64.cc
+++ b/src/vixl/a64/assembler-a64.cc
@@ -57,8 +57,7 @@
 
 
 bool CPURegList::IsValid() const {
-  if ((type_ == CPURegister::kRegister) ||
-      (type_ == CPURegister::kVRegister)) {
+  if ((type_ == CPURegister::kRegister) || (type_ == CPURegister::kVRegister)) {
     bool is_valid = true;
     // Try to create a CPURegister for each element in the list.
     for (int i = 0; i < kRegListSizeInBits; i++) {
@@ -155,51 +154,35 @@
 
 // Registers.
 #define WREG(n) w##n,
-const Register Register::wregisters[] = {
-REGISTER_CODE_LIST(WREG)
-};
+const Register Register::wregisters[] = {REGISTER_CODE_LIST(WREG)};
 #undef WREG
 
 #define XREG(n) x##n,
-const Register Register::xregisters[] = {
-REGISTER_CODE_LIST(XREG)
-};
+const Register Register::xregisters[] = {REGISTER_CODE_LIST(XREG)};
 #undef XREG
 
 #define BREG(n) b##n,
-const VRegister VRegister::bregisters[] = {
-REGISTER_CODE_LIST(BREG)
-};
+const VRegister VRegister::bregisters[] = {REGISTER_CODE_LIST(BREG)};
 #undef BREG
 
 #define HREG(n) h##n,
-const VRegister VRegister::hregisters[] = {
-REGISTER_CODE_LIST(HREG)
-};
+const VRegister VRegister::hregisters[] = {REGISTER_CODE_LIST(HREG)};
 #undef HREG
 
 #define SREG(n) s##n,
-const VRegister VRegister::sregisters[] = {
-REGISTER_CODE_LIST(SREG)
-};
+const VRegister VRegister::sregisters[] = {REGISTER_CODE_LIST(SREG)};
 #undef SREG
 
 #define DREG(n) d##n,
-const VRegister VRegister::dregisters[] = {
-REGISTER_CODE_LIST(DREG)
-};
+const VRegister VRegister::dregisters[] = {REGISTER_CODE_LIST(DREG)};
 #undef DREG
 
 #define QREG(n) q##n,
-const VRegister VRegister::qregisters[] = {
-REGISTER_CODE_LIST(QREG)
-};
+const VRegister VRegister::qregisters[] = {REGISTER_CODE_LIST(QREG)};
 #undef QREG
 
 #define VREG(n) v##n,
-const VRegister VRegister::vregisters[] = {
-REGISTER_CODE_LIST(VREG)
-};
+const VRegister VRegister::vregisters[] = {REGISTER_CODE_LIST(VREG)};
 #undef VREG
 
 
@@ -342,8 +325,17 @@
 }
 
 
-bool Operand::IsImmediate() const {
-  return reg_.Is(NoReg);
+bool Operand::IsImmediate() const { return reg_.Is(NoReg); }
+
+
+bool Operand::IsPlainRegister() const {
+  return reg_.IsValid() &&
+         (((shift_ == NO_SHIFT) && (extend_ == NO_EXTEND)) ||
+          // No-op shifts.
+          ((shift_ != NO_SHIFT) && (shift_amount_ == 0)) ||
+          // No-op extend operations.
+          ((extend_ == UXTX) || (extend_ == SXTX) ||
+           (reg_.IsW() && ((extend_ == UXTW) || (extend_ == SXTW)))));
 }
 
 
@@ -375,7 +367,7 @@
 
 // MemOperand
 MemOperand::MemOperand(Register base, int64_t offset, AddrMode addrmode)
-  : base_(base), regoffset_(NoReg), offset_(offset), addrmode_(addrmode) {
+    : base_(base), regoffset_(NoReg), offset_(offset), addrmode_(addrmode) {
   VIXL_ASSERT(base.Is64Bits() && !base.IsZero());
 }
 
@@ -384,8 +376,13 @@
                        Register regoffset,
                        Extend extend,
                        unsigned shift_amount)
-  : base_(base), regoffset_(regoffset), offset_(0), addrmode_(Offset),
-    shift_(NO_SHIFT), extend_(extend), shift_amount_(shift_amount) {
+    : base_(base),
+      regoffset_(regoffset),
+      offset_(0),
+      addrmode_(Offset),
+      shift_(NO_SHIFT),
+      extend_(extend),
+      shift_amount_(shift_amount) {
   VIXL_ASSERT(base.Is64Bits() && !base.IsZero());
   VIXL_ASSERT(!regoffset.IsSP());
   VIXL_ASSERT((extend == UXTW) || (extend == SXTW) || (extend == SXTX));
@@ -399,8 +396,13 @@
                        Register regoffset,
                        Shift shift,
                        unsigned shift_amount)
-  : base_(base), regoffset_(regoffset), offset_(0), addrmode_(Offset),
-    shift_(shift), extend_(NO_EXTEND), shift_amount_(shift_amount) {
+    : base_(base),
+      regoffset_(regoffset),
+      offset_(0),
+      addrmode_(Offset),
+      shift_(shift),
+      extend_(NO_EXTEND),
+      shift_amount_(shift_amount) {
   VIXL_ASSERT(base.Is64Bits() && !base.IsZero());
   VIXL_ASSERT(regoffset.Is64Bits() && !regoffset.IsSP());
   VIXL_ASSERT(shift == LSL);
@@ -408,7 +410,7 @@
 
 
 MemOperand::MemOperand(Register base, const Operand& offset, AddrMode addrmode)
-  : base_(base), regoffset_(NoReg), addrmode_(addrmode) {
+    : base_(base), regoffset_(NoReg), addrmode_(addrmode) {
   VIXL_ASSERT(base.Is64Bits() && !base.IsZero());
 
   if (offset.IsImmediate()) {
@@ -455,14 +457,10 @@
 }
 
 
-bool MemOperand::IsPreIndex() const {
-  return addrmode_ == PreIndex;
-}
+bool MemOperand::IsPreIndex() const { return addrmode_ == PreIndex; }
 
 
-bool MemOperand::IsPostIndex() const {
-  return addrmode_ == PostIndex;
-}
+bool MemOperand::IsPostIndex() const { return addrmode_ == PostIndex; }
 
 
 void MemOperand::AddOffset(int64_t offset) {
@@ -488,7 +486,8 @@
 
 
 // Assembler
-Assembler::Assembler(byte* buffer, size_t capacity,
+Assembler::Assembler(byte* buffer,
+                     size_t capacity,
                      PositionIndependentCodeOption pic)
     : pic_(pic) {
 #ifdef VIXL_DEBUG
@@ -513,14 +512,10 @@
 }
 
 
-void Assembler::Reset() {
-  buffer_->Reset();
-}
+void Assembler::Reset() { buffer_->Reset(); }
 
 
-void Assembler::FinalizeCode() {
-  buffer_->SetClean();
-}
+void Assembler::FinalizeCode() { buffer_->SetClean(); }
 
 
 void Assembler::bind(Label* label) {
@@ -553,8 +548,7 @@
 
   if (label->IsBound()) {
     uintptr_t pc_offset = GetCursorAddress<uintptr_t>() >> element_shift;
-    uintptr_t label_offset =
-        GetLabelAddress<uintptr_t>(label) >> element_shift;
+    uintptr_t label_offset = GetLabelAddress<uintptr_t>(label) >> element_shift;
     return label_offset - pc_offset;
   } else {
     label->AddLink(buffer_->CursorOffset());
@@ -603,8 +597,12 @@
   literal->set_offset(CursorOffset());
   // Copy the data into the pool.
   switch (literal->size()) {
-    case kSRegSizeInBytes: dc32(literal->raw_value32()); break;
-    case kDRegSizeInBytes: dc64(literal->raw_value64()); break;
+    case kSRegSizeInBytes:
+      dc32(literal->raw_value32());
+      break;
+    case kDRegSizeInBytes:
+      dc64(literal->raw_value64());
+      break;
     default:
       VIXL_ASSERT(literal->size() == kQRegSizeInBytes);
       dc64(literal->raw_value128_low64());
@@ -661,9 +659,7 @@
 }
 
 
-void Assembler::b(int imm26) {
-  Emit(B | ImmUncondBranch(imm26));
-}
+void Assembler::b(int imm26) { Emit(B | ImmUncondBranch(imm26)); }
 
 
 void Assembler::b(int imm19, Condition cond) {
@@ -685,9 +681,7 @@
 }
 
 
-void Assembler::bl(int imm26) {
-  Emit(BL | ImmUncondBranch(imm26));
-}
+void Assembler::bl(int imm26) { Emit(BL | ImmUncondBranch(imm26)); }
 
 
 void Assembler::bl(Label* label) {
@@ -697,28 +691,24 @@
 }
 
 
-void Assembler::cbz(const Register& rt,
-                    int imm19) {
+void Assembler::cbz(const Register& rt, int imm19) {
   Emit(SF(rt) | CBZ | ImmCmpBranch(imm19) | Rt(rt));
 }
 
 
-void Assembler::cbz(const Register& rt,
-                    Label* label) {
+void Assembler::cbz(const Register& rt, Label* label) {
   int64_t offset = LinkAndGetInstructionOffsetTo(label);
   VIXL_ASSERT(Instruction::IsValidImmPCOffset(CompareBranchType, offset));
   cbz(rt, static_cast<int>(offset));
 }
 
 
-void Assembler::cbnz(const Register& rt,
-                     int imm19) {
+void Assembler::cbnz(const Register& rt, int imm19) {
   Emit(SF(rt) | CBNZ | ImmCmpBranch(imm19) | Rt(rt));
 }
 
 
-void Assembler::cbnz(const Register& rt,
-                     Label* label) {
+void Assembler::cbnz(const Register& rt, Label* label) {
   int64_t offset = LinkAndGetInstructionOffsetTo(label);
   VIXL_ASSERT(Instruction::IsValidImmPCOffset(CompareBranchType, offset));
   cbnz(rt, static_cast<int>(offset));
@@ -834,60 +824,52 @@
 }
 
 
-void Assembler::tbz(const Register& rt,
-                    unsigned bit_pos,
-                    int imm14) {
+void Assembler::tbz(const Register& rt, unsigned bit_pos, int imm14) {
   VIXL_ASSERT(rt.Is64Bits() || (rt.Is32Bits() && (bit_pos < kWRegSize)));
   Emit(TBZ | ImmTestBranchBit(bit_pos) | ImmTestBranch(imm14) | Rt(rt));
 }
 
 
-void Assembler::tbz(const Register& rt,
-                    unsigned bit_pos,
-                    Label* label) {
+void Assembler::tbz(const Register& rt, unsigned bit_pos, Label* label) {
   ptrdiff_t offset = LinkAndGetInstructionOffsetTo(label);
   VIXL_ASSERT(Instruction::IsValidImmPCOffset(TestBranchType, offset));
   tbz(rt, bit_pos, static_cast<int>(offset));
 }
 
 
-void Assembler::tbnz(const Register& rt,
-                     unsigned bit_pos,
-                     int imm14) {
+void Assembler::tbnz(const Register& rt, unsigned bit_pos, int imm14) {
   VIXL_ASSERT(rt.Is64Bits() || (rt.Is32Bits() && (bit_pos < kWRegSize)));
   Emit(TBNZ | ImmTestBranchBit(bit_pos) | ImmTestBranch(imm14) | Rt(rt));
 }
 
 
-void Assembler::tbnz(const Register& rt,
-                     unsigned bit_pos,
-                     Label* label) {
+void Assembler::tbnz(const Register& rt, unsigned bit_pos, Label* label) {
   ptrdiff_t offset = LinkAndGetInstructionOffsetTo(label);
   VIXL_ASSERT(Instruction::IsValidImmPCOffset(TestBranchType, offset));
   tbnz(rt, bit_pos, static_cast<int>(offset));
 }
 
 
-void Assembler::adr(const Register& rd, int imm21) {
-  VIXL_ASSERT(rd.Is64Bits());
-  Emit(ADR | ImmPCRelAddress(imm21) | Rd(rd));
+void Assembler::adr(const Register& xd, int imm21) {
+  VIXL_ASSERT(xd.Is64Bits());
+  Emit(ADR | ImmPCRelAddress(imm21) | Rd(xd));
 }
 
 
-void Assembler::adr(const Register& rd, Label* label) {
-  adr(rd, static_cast<int>(LinkAndGetByteOffsetTo(label)));
+void Assembler::adr(const Register& xd, Label* label) {
+  adr(xd, static_cast<int>(LinkAndGetByteOffsetTo(label)));
 }
 
 
-void Assembler::adrp(const Register& rd, int imm21) {
-  VIXL_ASSERT(rd.Is64Bits());
-  Emit(ADRP | ImmPCRelAddress(imm21) | Rd(rd));
+void Assembler::adrp(const Register& xd, int imm21) {
+  VIXL_ASSERT(xd.Is64Bits());
+  Emit(ADRP | ImmPCRelAddress(imm21) | Rd(xd));
 }
 
 
-void Assembler::adrp(const Register& rd, Label* label) {
+void Assembler::adrp(const Register& xd, Label* label) {
   VIXL_ASSERT(AllowPageOffsetDependentCode());
-  adrp(rd, static_cast<int>(LinkAndGetPageOffsetTo(label)));
+  adrp(xd, static_cast<int>(LinkAndGetPageOffsetTo(label)));
 }
 
 
@@ -905,8 +887,7 @@
 }
 
 
-void Assembler::cmn(const Register& rn,
-                    const Operand& operand) {
+void Assembler::cmn(const Register& rn, const Operand& operand) {
   Register zr = AppropriateZeroRegFor(rn);
   adds(zr, rn, operand);
 }
@@ -999,8 +980,7 @@
 }
 
 
-void Assembler::tst(const Register& rn,
-                    const Operand& operand) {
+void Assembler::tst(const Register& rn, const Operand& operand) {
   ands(AppropriateZeroRegFor(rn), rn, operand);
 }
 
@@ -1090,8 +1070,8 @@
                     unsigned imms) {
   VIXL_ASSERT(rd.size() == rn.size());
   Instr N = SF(rd) >> (kSFOffset - kBitfieldNOffset);
-  Emit(SF(rd) | BFM | N |
-       ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd));
+  Emit(SF(rd) | BFM | N | ImmR(immr, rd.size()) | ImmS(imms, rn.size()) |
+       Rn(rn) | Rd(rd));
 }
 
 
@@ -1101,8 +1081,8 @@
                      unsigned imms) {
   VIXL_ASSERT(rd.Is64Bits() || rn.Is32Bits());
   Instr N = SF(rd) >> (kSFOffset - kBitfieldNOffset);
-  Emit(SF(rd) | SBFM | N |
-       ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd));
+  Emit(SF(rd) | SBFM | N | ImmR(immr, rd.size()) | ImmS(imms, rn.size()) |
+       Rn(rn) | Rd(rd));
 }
 
 
@@ -1112,8 +1092,8 @@
                      unsigned imms) {
   VIXL_ASSERT(rd.size() == rn.size());
   Instr N = SF(rd) >> (kSFOffset - kBitfieldNOffset);
-  Emit(SF(rd) | UBFM | N |
-       ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd));
+  Emit(SF(rd) | UBFM | N | ImmR(immr, rd.size()) | ImmS(imms, rn.size()) |
+       Rn(rn) | Rd(rd));
 }
 
 
@@ -1160,33 +1140,33 @@
 }
 
 
-void Assembler::cset(const Register &rd, Condition cond) {
+void Assembler::cset(const Register& rd, Condition cond) {
   VIXL_ASSERT((cond != al) && (cond != nv));
   Register zr = AppropriateZeroRegFor(rd);
   csinc(rd, zr, zr, InvertCondition(cond));
 }
 
 
-void Assembler::csetm(const Register &rd, Condition cond) {
+void Assembler::csetm(const Register& rd, Condition cond) {
   VIXL_ASSERT((cond != al) && (cond != nv));
   Register zr = AppropriateZeroRegFor(rd);
   csinv(rd, zr, zr, InvertCondition(cond));
 }
 
 
-void Assembler::cinc(const Register &rd, const Register &rn, Condition cond) {
+void Assembler::cinc(const Register& rd, const Register& rn, Condition cond) {
   VIXL_ASSERT((cond != al) && (cond != nv));
   csinc(rd, rn, rn, InvertCondition(cond));
 }
 
 
-void Assembler::cinv(const Register &rd, const Register &rn, Condition cond) {
+void Assembler::cinv(const Register& rd, const Register& rn, Condition cond) {
   VIXL_ASSERT((cond != al) && (cond != nv));
   csinv(rd, rn, rn, InvertCondition(cond));
 }
 
 
-void Assembler::cneg(const Register &rd, const Register &rn, Condition cond) {
+void Assembler::cneg(const Register& rd, const Register& rn, Condition cond) {
   VIXL_ASSERT((cond != al) && (cond != nv));
   csneg(rd, rn, rn, InvertCondition(cond));
 }
@@ -1220,75 +1200,75 @@
 
 
 void Assembler::DataProcessing3Source(const Register& rd,
-                     const Register& rn,
-                     const Register& rm,
-                     const Register& ra,
-                     DataProcessing3SourceOp op) {
+                                      const Register& rn,
+                                      const Register& rm,
+                                      const Register& ra,
+                                      DataProcessing3SourceOp op) {
   Emit(SF(rd) | op | Rm(rm) | Ra(ra) | Rn(rn) | Rd(rd));
 }
 
 
-void Assembler::crc32b(const Register& rd,
-                       const Register& rn,
-                       const Register& rm) {
-  VIXL_ASSERT(rd.Is32Bits() && rn.Is32Bits() && rm.Is32Bits());
-  Emit(SF(rm) | Rm(rm) | CRC32B | Rn(rn) | Rd(rd));
+void Assembler::crc32b(const Register& wd,
+                       const Register& wn,
+                       const Register& wm) {
+  VIXL_ASSERT(wd.Is32Bits() && wn.Is32Bits() && wm.Is32Bits());
+  Emit(SF(wm) | Rm(wm) | CRC32B | Rn(wn) | Rd(wd));
 }
 
 
-void Assembler::crc32h(const Register& rd,
-                       const Register& rn,
-                       const Register& rm) {
-  VIXL_ASSERT(rd.Is32Bits() && rn.Is32Bits() && rm.Is32Bits());
-  Emit(SF(rm) | Rm(rm) | CRC32H | Rn(rn) | Rd(rd));
+void Assembler::crc32h(const Register& wd,
+                       const Register& wn,
+                       const Register& wm) {
+  VIXL_ASSERT(wd.Is32Bits() && wn.Is32Bits() && wm.Is32Bits());
+  Emit(SF(wm) | Rm(wm) | CRC32H | Rn(wn) | Rd(wd));
 }
 
 
-void Assembler::crc32w(const Register& rd,
-                       const Register& rn,
-                       const Register& rm) {
-  VIXL_ASSERT(rd.Is32Bits() && rn.Is32Bits() && rm.Is32Bits());
-  Emit(SF(rm) | Rm(rm) | CRC32W | Rn(rn) | Rd(rd));
+void Assembler::crc32w(const Register& wd,
+                       const Register& wn,
+                       const Register& wm) {
+  VIXL_ASSERT(wd.Is32Bits() && wn.Is32Bits() && wm.Is32Bits());
+  Emit(SF(wm) | Rm(wm) | CRC32W | Rn(wn) | Rd(wd));
 }
 
 
-void Assembler::crc32x(const Register& rd,
-                       const Register& rn,
-                       const Register& rm) {
-  VIXL_ASSERT(rd.Is32Bits() && rn.Is32Bits() && rm.Is64Bits());
-  Emit(SF(rm) | Rm(rm) | CRC32X | Rn(rn) | Rd(rd));
+void Assembler::crc32x(const Register& wd,
+                       const Register& wn,
+                       const Register& xm) {
+  VIXL_ASSERT(wd.Is32Bits() && wn.Is32Bits() && xm.Is64Bits());
+  Emit(SF(xm) | Rm(xm) | CRC32X | Rn(wn) | Rd(wd));
 }
 
 
-void Assembler::crc32cb(const Register& rd,
-                        const Register& rn,
-                        const Register& rm) {
-  VIXL_ASSERT(rd.Is32Bits() && rn.Is32Bits() && rm.Is32Bits());
-  Emit(SF(rm) | Rm(rm) | CRC32CB | Rn(rn) | Rd(rd));
+void Assembler::crc32cb(const Register& wd,
+                        const Register& wn,
+                        const Register& wm) {
+  VIXL_ASSERT(wd.Is32Bits() && wn.Is32Bits() && wm.Is32Bits());
+  Emit(SF(wm) | Rm(wm) | CRC32CB | Rn(wn) | Rd(wd));
 }
 
 
-void Assembler::crc32ch(const Register& rd,
-                        const Register& rn,
-                        const Register& rm) {
-  VIXL_ASSERT(rd.Is32Bits() && rn.Is32Bits() && rm.Is32Bits());
-  Emit(SF(rm) | Rm(rm) | CRC32CH | Rn(rn) | Rd(rd));
+void Assembler::crc32ch(const Register& wd,
+                        const Register& wn,
+                        const Register& wm) {
+  VIXL_ASSERT(wd.Is32Bits() && wn.Is32Bits() && wm.Is32Bits());
+  Emit(SF(wm) | Rm(wm) | CRC32CH | Rn(wn) | Rd(wd));
 }
 
 
-void Assembler::crc32cw(const Register& rd,
-                        const Register& rn,
-                        const Register& rm) {
-  VIXL_ASSERT(rd.Is32Bits() && rn.Is32Bits() && rm.Is32Bits());
-  Emit(SF(rm) | Rm(rm) | CRC32CW | Rn(rn) | Rd(rd));
+void Assembler::crc32cw(const Register& wd,
+                        const Register& wn,
+                        const Register& wm) {
+  VIXL_ASSERT(wd.Is32Bits() && wn.Is32Bits() && wm.Is32Bits());
+  Emit(SF(wm) | Rm(wm) | CRC32CW | Rn(wn) | Rd(wd));
 }
 
 
-void Assembler::crc32cx(const Register& rd,
-                        const Register& rn,
-                        const Register& rm) {
-  VIXL_ASSERT(rd.Is32Bits() && rn.Is32Bits() && rm.Is64Bits());
-  Emit(SF(rm) | Rm(rm) | CRC32CX | Rn(rn) | Rd(rd));
+void Assembler::crc32cx(const Register& wd,
+                        const Register& wn,
+                        const Register& xm) {
+  VIXL_ASSERT(wd.Is32Bits() && wn.Is32Bits() && xm.Is64Bits());
+  Emit(SF(xm) | Rm(xm) | CRC32CX | Rn(wn) | Rd(wd));
 }
 
 
@@ -1324,52 +1304,52 @@
 }
 
 
-void Assembler::umaddl(const Register& rd,
-                       const Register& rn,
-                       const Register& rm,
-                       const Register& ra) {
-  VIXL_ASSERT(rd.Is64Bits() && ra.Is64Bits());
-  VIXL_ASSERT(rn.Is32Bits() && rm.Is32Bits());
-  DataProcessing3Source(rd, rn, rm, ra, UMADDL_x);
+void Assembler::umaddl(const Register& xd,
+                       const Register& wn,
+                       const Register& wm,
+                       const Register& xa) {
+  VIXL_ASSERT(xd.Is64Bits() && xa.Is64Bits());
+  VIXL_ASSERT(wn.Is32Bits() && wm.Is32Bits());
+  DataProcessing3Source(xd, wn, wm, xa, UMADDL_x);
 }
 
 
-void Assembler::smaddl(const Register& rd,
-                       const Register& rn,
-                       const Register& rm,
-                       const Register& ra) {
-  VIXL_ASSERT(rd.Is64Bits() && ra.Is64Bits());
-  VIXL_ASSERT(rn.Is32Bits() && rm.Is32Bits());
-  DataProcessing3Source(rd, rn, rm, ra, SMADDL_x);
+void Assembler::smaddl(const Register& xd,
+                       const Register& wn,
+                       const Register& wm,
+                       const Register& xa) {
+  VIXL_ASSERT(xd.Is64Bits() && xa.Is64Bits());
+  VIXL_ASSERT(wn.Is32Bits() && wm.Is32Bits());
+  DataProcessing3Source(xd, wn, wm, xa, SMADDL_x);
 }
 
 
-void Assembler::umsubl(const Register& rd,
-                       const Register& rn,
-                       const Register& rm,
-                       const Register& ra) {
-  VIXL_ASSERT(rd.Is64Bits() && ra.Is64Bits());
-  VIXL_ASSERT(rn.Is32Bits() && rm.Is32Bits());
-  DataProcessing3Source(rd, rn, rm, ra, UMSUBL_x);
+void Assembler::umsubl(const Register& xd,
+                       const Register& wn,
+                       const Register& wm,
+                       const Register& xa) {
+  VIXL_ASSERT(xd.Is64Bits() && xa.Is64Bits());
+  VIXL_ASSERT(wn.Is32Bits() && wm.Is32Bits());
+  DataProcessing3Source(xd, wn, wm, xa, UMSUBL_x);
 }
 
 
-void Assembler::smsubl(const Register& rd,
-                       const Register& rn,
-                       const Register& rm,
-                       const Register& ra) {
-  VIXL_ASSERT(rd.Is64Bits() && ra.Is64Bits());
-  VIXL_ASSERT(rn.Is32Bits() && rm.Is32Bits());
-  DataProcessing3Source(rd, rn, rm, ra, SMSUBL_x);
+void Assembler::smsubl(const Register& xd,
+                       const Register& wn,
+                       const Register& wm,
+                       const Register& xa) {
+  VIXL_ASSERT(xd.Is64Bits() && xa.Is64Bits());
+  VIXL_ASSERT(wn.Is32Bits() && wm.Is32Bits());
+  DataProcessing3Source(xd, wn, wm, xa, SMSUBL_x);
 }
 
 
-void Assembler::smull(const Register& rd,
-                      const Register& rn,
-                      const Register& rm) {
-  VIXL_ASSERT(rd.Is64Bits());
-  VIXL_ASSERT(rn.Is32Bits() && rm.Is32Bits());
-  DataProcessing3Source(rd, rn, rm, xzr, SMADDL_x);
+void Assembler::smull(const Register& xd,
+                      const Register& wn,
+                      const Register& wm) {
+  VIXL_ASSERT(xd.Is64Bits());
+  VIXL_ASSERT(wn.Is32Bits() && wm.Is32Bits());
+  DataProcessing3Source(xd, wn, wm, xzr, SMADDL_x);
 }
 
 
@@ -1407,39 +1387,33 @@
 }
 
 
-void Assembler::rbit(const Register& rd,
-                     const Register& rn) {
+void Assembler::rbit(const Register& rd, const Register& rn) {
   DataProcessing1Source(rd, rn, RBIT);
 }
 
 
-void Assembler::rev16(const Register& rd,
-                      const Register& rn) {
+void Assembler::rev16(const Register& rd, const Register& rn) {
   DataProcessing1Source(rd, rn, REV16);
 }
 
 
-void Assembler::rev32(const Register& rd,
-                      const Register& rn) {
-  VIXL_ASSERT(rd.Is64Bits());
-  DataProcessing1Source(rd, rn, REV);
+void Assembler::rev32(const Register& xd, const Register& xn) {
+  VIXL_ASSERT(xd.Is64Bits());
+  DataProcessing1Source(xd, xn, REV);
 }
 
 
-void Assembler::rev(const Register& rd,
-                    const Register& rn) {
+void Assembler::rev(const Register& rd, const Register& rn) {
   DataProcessing1Source(rd, rn, rd.Is64Bits() ? REV_x : REV_w);
 }
 
 
-void Assembler::clz(const Register& rd,
-                    const Register& rn) {
+void Assembler::clz(const Register& rd, const Register& rn) {
   DataProcessing1Source(rd, rn, CLZ);
 }
 
 
-void Assembler::cls(const Register& rd,
-                    const Register& rn) {
+void Assembler::cls(const Register& rd, const Register& rn) {
   DataProcessing1Source(rd, rn, CLS);
 }
 
@@ -1458,11 +1432,11 @@
 }
 
 
-void Assembler::ldpsw(const Register& rt,
-                      const Register& rt2,
+void Assembler::ldpsw(const Register& xt,
+                      const Register& xt2,
                       const MemOperand& src) {
-  VIXL_ASSERT(rt.Is64Bits());
-  LoadStorePair(rt, rt2, src, LDPSW_x);
+  VIXL_ASSERT(xt.Is64Bits() && xt2.Is64Bits());
+  LoadStorePair(xt, xt2, src, LDPSW_x);
 }
 
 
@@ -1498,16 +1472,14 @@
 void Assembler::ldnp(const CPURegister& rt,
                      const CPURegister& rt2,
                      const MemOperand& src) {
-  LoadStorePairNonTemporal(rt, rt2, src,
-                           LoadPairNonTemporalOpFor(rt, rt2));
+  LoadStorePairNonTemporal(rt, rt2, src, LoadPairNonTemporalOpFor(rt, rt2));
 }
 
 
 void Assembler::stnp(const CPURegister& rt,
                      const CPURegister& rt2,
                      const MemOperand& dst) {
-  LoadStorePairNonTemporal(rt, rt2, dst,
-                           StorePairNonTemporalOpFor(rt, rt2));
+  LoadStorePairNonTemporal(rt, rt2, dst, StorePairNonTemporalOpFor(rt, rt2));
 }
 
 
@@ -1519,8 +1491,8 @@
   VIXL_ASSERT(AreSameSizeAndType(rt, rt2));
   VIXL_ASSERT(addr.IsImmediateOffset());
 
-  unsigned size = CalcLSPairDataSize(
-    static_cast<LoadStorePairOp>(op & LoadStorePairMask));
+  unsigned size =
+      CalcLSPairDataSize(static_cast<LoadStorePairOp>(op & LoadStorePairMask));
   VIXL_ASSERT(IsImmLSPair(addr.offset(), size));
   int offset = static_cast<int>(addr.offset());
   Emit(op | Rt(rt) | Rt2(rt2) | RnSP(addr.base()) | ImmLSPair(offset, size));
@@ -1528,7 +1500,8 @@
 
 
 // Memory instructions.
-void Assembler::ldrb(const Register& rt, const MemOperand& src,
+void Assembler::ldrb(const Register& rt,
+                     const MemOperand& src,
                      LoadStoreScalingOption option) {
   VIXL_ASSERT(option != RequireUnscaledOffset);
   VIXL_ASSERT(option != PreferUnscaledOffset);
@@ -1536,7 +1509,8 @@
 }
 
 
-void Assembler::strb(const Register& rt, const MemOperand& dst,
+void Assembler::strb(const Register& rt,
+                     const MemOperand& dst,
                      LoadStoreScalingOption option) {
   VIXL_ASSERT(option != RequireUnscaledOffset);
   VIXL_ASSERT(option != PreferUnscaledOffset);
@@ -1544,7 +1518,8 @@
 }
 
 
-void Assembler::ldrsb(const Register& rt, const MemOperand& src,
+void Assembler::ldrsb(const Register& rt,
+                      const MemOperand& src,
                       LoadStoreScalingOption option) {
   VIXL_ASSERT(option != RequireUnscaledOffset);
   VIXL_ASSERT(option != PreferUnscaledOffset);
@@ -1552,7 +1527,8 @@
 }
 
 
-void Assembler::ldrh(const Register& rt, const MemOperand& src,
+void Assembler::ldrh(const Register& rt,
+                     const MemOperand& src,
                      LoadStoreScalingOption option) {
   VIXL_ASSERT(option != RequireUnscaledOffset);
   VIXL_ASSERT(option != PreferUnscaledOffset);
@@ -1560,7 +1536,8 @@
 }
 
 
-void Assembler::strh(const Register& rt, const MemOperand& dst,
+void Assembler::strh(const Register& rt,
+                     const MemOperand& dst,
                      LoadStoreScalingOption option) {
   VIXL_ASSERT(option != RequireUnscaledOffset);
   VIXL_ASSERT(option != PreferUnscaledOffset);
@@ -1568,7 +1545,8 @@
 }
 
 
-void Assembler::ldrsh(const Register& rt, const MemOperand& src,
+void Assembler::ldrsh(const Register& rt,
+                      const MemOperand& src,
                       LoadStoreScalingOption option) {
   VIXL_ASSERT(option != RequireUnscaledOffset);
   VIXL_ASSERT(option != PreferUnscaledOffset);
@@ -1576,7 +1554,8 @@
 }
 
 
-void Assembler::ldr(const CPURegister& rt, const MemOperand& src,
+void Assembler::ldr(const CPURegister& rt,
+                    const MemOperand& src,
                     LoadStoreScalingOption option) {
   VIXL_ASSERT(option != RequireUnscaledOffset);
   VIXL_ASSERT(option != PreferUnscaledOffset);
@@ -1584,7 +1563,8 @@
 }
 
 
-void Assembler::str(const CPURegister& rt, const MemOperand& dst,
+void Assembler::str(const CPURegister& rt,
+                    const MemOperand& dst,
                     LoadStoreScalingOption option) {
   VIXL_ASSERT(option != RequireUnscaledOffset);
   VIXL_ASSERT(option != PreferUnscaledOffset);
@@ -1592,16 +1572,18 @@
 }
 
 
-void Assembler::ldrsw(const Register& rt, const MemOperand& src,
+void Assembler::ldrsw(const Register& xt,
+                      const MemOperand& src,
                       LoadStoreScalingOption option) {
-  VIXL_ASSERT(rt.Is64Bits());
+  VIXL_ASSERT(xt.Is64Bits());
   VIXL_ASSERT(option != RequireUnscaledOffset);
   VIXL_ASSERT(option != PreferUnscaledOffset);
-  LoadStore(rt, src, LDRSW_x, option);
+  LoadStore(xt, src, LDRSW_x, option);
 }
 
 
-void Assembler::ldurb(const Register& rt, const MemOperand& src,
+void Assembler::ldurb(const Register& rt,
+                      const MemOperand& src,
                       LoadStoreScalingOption option) {
   VIXL_ASSERT(option != RequireScaledOffset);
   VIXL_ASSERT(option != PreferScaledOffset);
@@ -1609,7 +1591,8 @@
 }
 
 
-void Assembler::sturb(const Register& rt, const MemOperand& dst,
+void Assembler::sturb(const Register& rt,
+                      const MemOperand& dst,
                       LoadStoreScalingOption option) {
   VIXL_ASSERT(option != RequireScaledOffset);
   VIXL_ASSERT(option != PreferScaledOffset);
@@ -1617,7 +1600,8 @@
 }
 
 
-void Assembler::ldursb(const Register& rt, const MemOperand& src,
+void Assembler::ldursb(const Register& rt,
+                       const MemOperand& src,
                        LoadStoreScalingOption option) {
   VIXL_ASSERT(option != RequireScaledOffset);
   VIXL_ASSERT(option != PreferScaledOffset);
@@ -1625,7 +1609,8 @@
 }
 
 
-void Assembler::ldurh(const Register& rt, const MemOperand& src,
+void Assembler::ldurh(const Register& rt,
+                      const MemOperand& src,
                       LoadStoreScalingOption option) {
   VIXL_ASSERT(option != RequireScaledOffset);
   VIXL_ASSERT(option != PreferScaledOffset);
@@ -1633,7 +1618,8 @@
 }
 
 
-void Assembler::sturh(const Register& rt, const MemOperand& dst,
+void Assembler::sturh(const Register& rt,
+                      const MemOperand& dst,
                       LoadStoreScalingOption option) {
   VIXL_ASSERT(option != RequireScaledOffset);
   VIXL_ASSERT(option != PreferScaledOffset);
@@ -1641,7 +1627,8 @@
 }
 
 
-void Assembler::ldursh(const Register& rt, const MemOperand& src,
+void Assembler::ldursh(const Register& rt,
+                       const MemOperand& src,
                        LoadStoreScalingOption option) {
   VIXL_ASSERT(option != RequireScaledOffset);
   VIXL_ASSERT(option != PreferScaledOffset);
@@ -1649,7 +1636,8 @@
 }
 
 
-void Assembler::ldur(const CPURegister& rt, const MemOperand& src,
+void Assembler::ldur(const CPURegister& rt,
+                     const MemOperand& src,
                      LoadStoreScalingOption option) {
   VIXL_ASSERT(option != RequireScaledOffset);
   VIXL_ASSERT(option != PreferScaledOffset);
@@ -1657,7 +1645,8 @@
 }
 
 
-void Assembler::stur(const CPURegister& rt, const MemOperand& dst,
+void Assembler::stur(const CPURegister& rt,
+                     const MemOperand& dst,
                      LoadStoreScalingOption option) {
   VIXL_ASSERT(option != RequireScaledOffset);
   VIXL_ASSERT(option != PreferScaledOffset);
@@ -1665,19 +1654,20 @@
 }
 
 
-void Assembler::ldursw(const Register& rt, const MemOperand& src,
+void Assembler::ldursw(const Register& xt,
+                       const MemOperand& src,
                        LoadStoreScalingOption option) {
-  VIXL_ASSERT(rt.Is64Bits());
+  VIXL_ASSERT(xt.Is64Bits());
   VIXL_ASSERT(option != RequireScaledOffset);
   VIXL_ASSERT(option != PreferScaledOffset);
-  LoadStore(rt, src, LDRSW_x, option);
+  LoadStore(xt, src, LDRSW_x, option);
 }
 
 
-void Assembler::ldrsw(const Register& rt, RawLiteral* literal) {
-  VIXL_ASSERT(rt.Is64Bits());
+void Assembler::ldrsw(const Register& xt, RawLiteral* literal) {
+  VIXL_ASSERT(xt.Is64Bits());
   VIXL_ASSERT(literal->size() == kWRegSizeInBytes);
-  ldrsw(rt, static_cast<int>(LinkAndGetWordOffsetTo(literal)));
+  ldrsw(xt, static_cast<int>(LinkAndGetWordOffsetTo(literal)));
 }
 
 
@@ -1729,22 +1719,19 @@
 }
 
 
-void Assembler::ldxrb(const Register& rt,
-                      const MemOperand& src) {
+void Assembler::ldxrb(const Register& rt, const MemOperand& src) {
   VIXL_ASSERT(src.IsImmediateOffset() && (src.offset() == 0));
   Emit(LDXRB_w | Rs_mask | Rt(rt) | Rt2_mask | RnSP(src.base()));
 }
 
 
-void Assembler::ldxrh(const Register& rt,
-                      const MemOperand& src) {
+void Assembler::ldxrh(const Register& rt, const MemOperand& src) {
   VIXL_ASSERT(src.IsImmediateOffset() && (src.offset() == 0));
   Emit(LDXRH_w | Rs_mask | Rt(rt) | Rt2_mask | RnSP(src.base()));
 }
 
 
-void Assembler::ldxr(const Register& rt,
-                     const MemOperand& src) {
+void Assembler::ldxr(const Register& rt, const MemOperand& src) {
   VIXL_ASSERT(src.IsImmediateOffset() && (src.offset() == 0));
   LoadStoreExclusive op = rt.Is64Bits() ? LDXR_x : LDXR_w;
   Emit(op | Rs_mask | Rt(rt) | Rt2_mask | RnSP(src.base()));
@@ -1797,22 +1784,19 @@
 }
 
 
-void Assembler::ldaxrb(const Register& rt,
-                       const MemOperand& src) {
+void Assembler::ldaxrb(const Register& rt, const MemOperand& src) {
   VIXL_ASSERT(src.IsImmediateOffset() && (src.offset() == 0));
   Emit(LDAXRB_w | Rs_mask | Rt(rt) | Rt2_mask | RnSP(src.base()));
 }
 
 
-void Assembler::ldaxrh(const Register& rt,
-                       const MemOperand& src) {
+void Assembler::ldaxrh(const Register& rt, const MemOperand& src) {
   VIXL_ASSERT(src.IsImmediateOffset() && (src.offset() == 0));
   Emit(LDAXRH_w | Rs_mask | Rt(rt) | Rt2_mask | RnSP(src.base()));
 }
 
 
-void Assembler::ldaxr(const Register& rt,
-                      const MemOperand& src) {
+void Assembler::ldaxr(const Register& rt, const MemOperand& src) {
   VIXL_ASSERT(src.IsImmediateOffset() && (src.offset() == 0));
   LoadStoreExclusive op = rt.Is64Bits() ? LDAXR_x : LDAXR_w;
   Emit(op | Rs_mask | Rt(rt) | Rt2_mask | RnSP(src.base()));
@@ -1840,51 +1824,46 @@
 }
 
 
-void Assembler::stlrb(const Register& rt,
-                      const MemOperand& dst) {
+void Assembler::stlrb(const Register& rt, const MemOperand& dst) {
   VIXL_ASSERT(dst.IsImmediateOffset() && (dst.offset() == 0));
   Emit(STLRB_w | Rs_mask | Rt(rt) | Rt2_mask | RnSP(dst.base()));
 }
 
 
-void Assembler::stlrh(const Register& rt,
-                      const MemOperand& dst) {
+void Assembler::stlrh(const Register& rt, const MemOperand& dst) {
   VIXL_ASSERT(dst.IsImmediateOffset() && (dst.offset() == 0));
   Emit(STLRH_w | Rs_mask | Rt(rt) | Rt2_mask | RnSP(dst.base()));
 }
 
 
-void Assembler::stlr(const Register& rt,
-                     const MemOperand& dst) {
+void Assembler::stlr(const Register& rt, const MemOperand& dst) {
   VIXL_ASSERT(dst.IsImmediateOffset() && (dst.offset() == 0));
   LoadStoreExclusive op = rt.Is64Bits() ? STLR_x : STLR_w;
   Emit(op | Rs_mask | Rt(rt) | Rt2_mask | RnSP(dst.base()));
 }
 
 
-void Assembler::ldarb(const Register& rt,
-                      const MemOperand& src) {
+void Assembler::ldarb(const Register& rt, const MemOperand& src) {
   VIXL_ASSERT(src.IsImmediateOffset() && (src.offset() == 0));
   Emit(LDARB_w | Rs_mask | Rt(rt) | Rt2_mask | RnSP(src.base()));
 }
 
 
-void Assembler::ldarh(const Register& rt,
-                      const MemOperand& src) {
+void Assembler::ldarh(const Register& rt, const MemOperand& src) {
   VIXL_ASSERT(src.IsImmediateOffset() && (src.offset() == 0));
   Emit(LDARH_w | Rs_mask | Rt(rt) | Rt2_mask | RnSP(src.base()));
 }
 
 
-void Assembler::ldar(const Register& rt,
-                     const MemOperand& src) {
+void Assembler::ldar(const Register& rt, const MemOperand& src) {
   VIXL_ASSERT(src.IsImmediateOffset() && (src.offset() == 0));
   LoadStoreExclusive op = rt.Is64Bits() ? LDAR_x : LDAR_w;
   Emit(op | Rs_mask | Rt(rt) | Rt2_mask | RnSP(src.base()));
 }
 
 
-void Assembler::prfm(PrefetchOperation op, const MemOperand& address,
+void Assembler::prfm(PrefetchOperation op,
+                     const MemOperand& address,
                      LoadStoreScalingOption option) {
   VIXL_ASSERT(option != RequireUnscaledOffset);
   VIXL_ASSERT(option != PreferUnscaledOffset);
@@ -1892,7 +1871,8 @@
 }
 
 
-void Assembler::prfum(PrefetchOperation op, const MemOperand& address,
+void Assembler::prfum(PrefetchOperation op,
+                      const MemOperand& address,
                       LoadStoreScalingOption option) {
   VIXL_ASSERT(option != RequireScaledOffset);
   VIXL_ASSERT(option != PreferScaledOffset);
@@ -1905,13 +1885,15 @@
 }
 
 
-void Assembler::sys(int op1, int crn, int crm, int op2, const Register& rt) {
-  Emit(SYS | ImmSysOp1(op1) | CRn(crn) | CRm(crm) | ImmSysOp2(op2) | Rt(rt));
+void Assembler::sys(int op1, int crn, int crm, int op2, const Register& xt) {
+  VIXL_ASSERT(xt.Is64Bits());
+  Emit(SYS | ImmSysOp1(op1) | CRn(crn) | CRm(crm) | ImmSysOp2(op2) | Rt(xt));
 }
 
 
-void Assembler::sys(int op, const Register& rt) {
-  Emit(SYS | SysOp(op) | Rt(rt));
+void Assembler::sys(int op, const Register& xt) {
+  VIXL_ASSERT(xt.Is64Bits());
+  Emit(SYS | SysOp(op) | Rt(xt));
 }
 
 
@@ -1927,9 +1909,7 @@
 }
 
 
-void Assembler::hint(SystemHint code) {
-  Emit(HINT | ImmHint(code) | Rt(xzr));
-}
+void Assembler::hint(SystemHint code) { Emit(HINT | ImmHint(code) | Rt(xzr)); }
 
 
 // NEON structure loads and stores.
@@ -1938,8 +1918,8 @@
 
   if (addr.IsPostIndex()) {
     VIXL_STATIC_ASSERT(NEONLoadStoreMultiStructPostIndex ==
-        static_cast<NEONLoadStoreMultiStructPostIndexOp>(
-            NEONLoadStoreSingleStructPostIndex));
+                       static_cast<NEONLoadStoreMultiStructPostIndexOp>(
+                           NEONLoadStoreSingleStructPostIndex));
 
     addr_field |= NEONLoadStoreMultiStructPostIndex;
     if (addr.offset() == 0) {
@@ -1969,11 +1949,13 @@
     switch (op) {
       case NEON_LD1_1v:
       case NEON_ST1_1v:
-        offset *= 1; break;
+        offset *= 1;
+        break;
       case NEONLoadStoreSingleStructLoad1:
       case NEONLoadStoreSingleStructStore1:
       case NEON_LD1R:
-        offset = (offset / vt.lanes()) * 1; break;
+        offset = (offset / vt.lanes()) * 1;
+        break;
 
       case NEON_LD1_2v:
       case NEON_ST1_2v:
@@ -1984,32 +1966,36 @@
       case NEONLoadStoreSingleStructLoad2:
       case NEONLoadStoreSingleStructStore2:
       case NEON_LD2R:
-        offset = (offset / vt.lanes()) * 2; break;
+        offset = (offset / vt.lanes()) * 2;
+        break;
 
       case NEON_LD1_3v:
       case NEON_ST1_3v:
       case NEON_LD3:
       case NEON_ST3:
-        offset *= 3; break;
+        offset *= 3;
+        break;
       case NEONLoadStoreSingleStructLoad3:
       case NEONLoadStoreSingleStructStore3:
       case NEON_LD3R:
-        offset = (offset / vt.lanes()) * 3; break;
+        offset = (offset / vt.lanes()) * 3;
+        break;
 
       case NEON_LD1_4v:
       case NEON_ST1_4v:
       case NEON_LD4:
       case NEON_ST4:
-        offset *= 4; break;
+        offset *= 4;
+        break;
       case NEONLoadStoreSingleStructLoad4:
       case NEONLoadStoreSingleStructStore4:
       case NEON_LD4R:
-        offset = (offset / vt.lanes()) * 4; break;
+        offset = (offset / vt.lanes()) * 4;
+        break;
       default:
         VIXL_UNREACHABLE();
     }
-    VIXL_ASSERT(!addr.regoffset().Is(NoReg) ||
-                addr.offset() == offset);
+    VIXL_ASSERT(!addr.regoffset().Is(NoReg) || addr.offset() == offset);
   }
 #else
   USE(vt, addr, op);
@@ -2026,15 +2012,14 @@
 
 
 void Assembler::LoadStoreStructSingleAllLanes(const VRegister& vt,
-                                      const MemOperand& addr,
-                                      NEONLoadStoreSingleStructOp op) {
+                                              const MemOperand& addr,
+                                              NEONLoadStoreSingleStructOp op) {
   LoadStoreStructVerify(vt, addr, op);
   Emit(op | LoadStoreStructAddrModeField(addr) | LSVFormat(vt) | Rt(vt));
 }
 
 
-void Assembler::ld1(const VRegister& vt,
-                    const MemOperand& src) {
+void Assembler::ld1(const VRegister& vt, const MemOperand& src) {
   LoadStoreStruct(vt, src, NEON_LD1_1v);
 }
 
@@ -2127,9 +2112,9 @@
 
 
 void Assembler::ld3r(const VRegister& vt,
-                    const VRegister& vt2,
-                    const VRegister& vt3,
-                    const MemOperand& src) {
+                     const VRegister& vt2,
+                     const VRegister& vt3,
+                     const MemOperand& src) {
   USE(vt2, vt3);
   VIXL_ASSERT(AreSameFormat(vt, vt2, vt3));
   VIXL_ASSERT(AreConsecutive(vt, vt2, vt3));
@@ -2163,10 +2148,10 @@
 
 
 void Assembler::ld4r(const VRegister& vt,
-                    const VRegister& vt2,
-                    const VRegister& vt3,
-                    const VRegister& vt4,
-                    const MemOperand& src) {
+                     const VRegister& vt2,
+                     const VRegister& vt3,
+                     const VRegister& vt4,
+                     const MemOperand& src) {
   USE(vt2, vt3, vt4);
   VIXL_ASSERT(AreSameFormat(vt, vt2, vt3, vt4));
   VIXL_ASSERT(AreConsecutive(vt, vt2, vt3, vt4));
@@ -2174,8 +2159,7 @@
 }
 
 
-void Assembler::st1(const VRegister& vt,
-                    const MemOperand& src) {
+void Assembler::st1(const VRegister& vt, const MemOperand& src) {
   LoadStoreStruct(vt, src, NEON_ST1_1v);
 }
 
@@ -2304,9 +2288,15 @@
 
   Instr instr = op;
   switch (lane_size) {
-    case 1: instr |= NEONLoadStoreSingle_b; break;
-    case 2: instr |= NEONLoadStoreSingle_h; break;
-    case 4: instr |= NEONLoadStoreSingle_s; break;
+    case 1:
+      instr |= NEONLoadStoreSingle_b;
+      break;
+    case 2:
+      instr |= NEONLoadStoreSingle_h;
+      break;
+    case 4:
+      instr |= NEONLoadStoreSingle_s;
+      break;
     default:
       VIXL_ASSERT(lane_size == 8);
       instr |= NEONLoadStoreSingle_d;
@@ -2316,22 +2306,17 @@
 }
 
 
-void Assembler::ld1(const VRegister& vt,
-                    int lane,
-                    const MemOperand& src) {
+void Assembler::ld1(const VRegister& vt, int lane, const MemOperand& src) {
   LoadStoreStructSingle(vt, lane, src, NEONLoadStoreSingleStructLoad1);
 }
 
 
-void Assembler::ld1r(const VRegister& vt,
-                     const MemOperand& src) {
+void Assembler::ld1r(const VRegister& vt, const MemOperand& src) {
   LoadStoreStructSingleAllLanes(vt, src, NEON_LD1R);
 }
 
 
-void Assembler::st1(const VRegister& vt,
-                    int lane,
-                    const MemOperand& dst) {
+void Assembler::st1(const VRegister& vt, int lane, const MemOperand& dst) {
   LoadStoreStructSingle(vt, lane, dst, NEONLoadStoreSingleStructStore1);
 }
 
@@ -2341,14 +2326,10 @@
                                 const VRegister& vm,
                                 NEON3DifferentOp vop) {
   VIXL_ASSERT(AreSameFormat(vn, vm));
-  VIXL_ASSERT((vn.Is1H() && vd.Is1S()) ||
-              (vn.Is1S() && vd.Is1D()) ||
-              (vn.Is8B() && vd.Is8H()) ||
-              (vn.Is4H() && vd.Is4S()) ||
-              (vn.Is2S() && vd.Is2D()) ||
-              (vn.Is16B() && vd.Is8H())||
-              (vn.Is8H() && vd.Is4S()) ||
-              (vn.Is4S() && vd.Is2D()));
+  VIXL_ASSERT((vn.Is1H() && vd.Is1S()) || (vn.Is1S() && vd.Is1D()) ||
+              (vn.Is8B() && vd.Is8H()) || (vn.Is4H() && vd.Is4S()) ||
+              (vn.Is2S() && vd.Is2D()) || (vn.Is16B() && vd.Is8H()) ||
+              (vn.Is8H() && vd.Is4S()) || (vn.Is4S() && vd.Is2D()));
   Instr format, op = vop;
   if (vd.IsScalar()) {
     op |= NEON_Q | NEONScalar;
@@ -2365,12 +2346,9 @@
                                 const VRegister& vm,
                                 NEON3DifferentOp vop) {
   VIXL_ASSERT(AreSameFormat(vd, vn));
-  VIXL_ASSERT((vm.Is8B() && vd.Is8H()) ||
-              (vm.Is4H() && vd.Is4S()) ||
-              (vm.Is2S() && vd.Is2D()) ||
-              (vm.Is16B() && vd.Is8H())||
-              (vm.Is8H() && vd.Is4S()) ||
-              (vm.Is4S() && vd.Is2D()));
+  VIXL_ASSERT((vm.Is8B() && vd.Is8H()) || (vm.Is4H() && vd.Is4S()) ||
+              (vm.Is2S() && vd.Is2D()) || (vm.Is16B() && vd.Is8H()) ||
+              (vm.Is8H() && vd.Is4S()) || (vm.Is4S() && vd.Is2D()));
   Emit(VFormat(vm) | vop | Rm(vm) | Rn(vn) | Rd(vd));
 }
 
@@ -2380,16 +2358,14 @@
                                  const VRegister& vm,
                                  NEON3DifferentOp vop) {
   VIXL_ASSERT(AreSameFormat(vm, vn));
-  VIXL_ASSERT((vd.Is8B() && vn.Is8H()) ||
-              (vd.Is4H() && vn.Is4S()) ||
-              (vd.Is2S() && vn.Is2D()) ||
-              (vd.Is16B() && vn.Is8H())||
-              (vd.Is8H() && vn.Is4S()) ||
-              (vd.Is4S() && vn.Is2D()));
+  VIXL_ASSERT((vd.Is8B() && vn.Is8H()) || (vd.Is4H() && vn.Is4S()) ||
+              (vd.Is2S() && vn.Is2D()) || (vd.Is16B() && vn.Is8H()) ||
+              (vd.Is8H() && vn.Is4S()) || (vd.Is4S() && vn.Is2D()));
   Emit(VFormat(vd) | vop | Rm(vm) | Rn(vn) | Rd(vd));
 }
 
 
+// clang-format off
 #define NEON_3DIFF_LONG_LIST(V) \
   V(pmull,  NEON_PMULL,  vn.IsVector() && vn.Is8B())                           \
   V(pmull2, NEON_PMULL2, vn.IsVector() && vn.Is16B())                          \
@@ -2427,6 +2403,7 @@
   V(sqdmlsl2, NEON_SQDMLSL2, vn.Is1H() || vn.Is1S() || vn.Is8H() || vn.Is4S()) \
   V(sqdmull,  NEON_SQDMULL,  vn.Is1H() || vn.Is1S() || vn.Is4H() || vn.Is2S()) \
   V(sqdmull2, NEON_SQDMULL2, vn.Is1H() || vn.Is1S() || vn.Is8H() || vn.Is4S()) \
+// clang-format on
 
 
 #define DEFINE_ASM_FUNC(FN, OP, AS)        \
@@ -2439,6 +2416,7 @@
 NEON_3DIFF_LONG_LIST(DEFINE_ASM_FUNC)
 #undef DEFINE_ASM_FUNC
 
+// clang-format off
 #define NEON_3DIFF_HN_LIST(V)         \
   V(addhn,   NEON_ADDHN,   vd.IsD())  \
   V(addhn2,  NEON_ADDHN2,  vd.IsQ())  \
@@ -2448,14 +2426,15 @@
   V(subhn2,  NEON_SUBHN2,  vd.IsQ())  \
   V(rsubhn,  NEON_RSUBHN,  vd.IsD())  \
   V(rsubhn2, NEON_RSUBHN2, vd.IsQ())
+// clang-format on
 
-#define DEFINE_ASM_FUNC(FN, OP, AS)        \
-void Assembler::FN(const VRegister& vd,    \
-                   const VRegister& vn,    \
-                   const VRegister& vm) {  \
-  VIXL_ASSERT(AS);                         \
-  NEON3DifferentHN(vd, vn, vm, OP);        \
-}
+#define DEFINE_ASM_FUNC(FN, OP, AS)         \
+  void Assembler::FN(const VRegister& vd,   \
+                     const VRegister& vn,   \
+                     const VRegister& vm) { \
+    VIXL_ASSERT(AS);                        \
+    NEON3DifferentHN(vd, vn, vm, OP);       \
+  }
 NEON_3DIFF_HN_LIST(DEFINE_ASM_FUNC)
 #undef DEFINE_ASM_FUNC
 
@@ -2540,21 +2519,19 @@
 }
 
 
-void Assembler::mrs(const Register& rt, SystemRegister sysreg) {
-  VIXL_ASSERT(rt.Is64Bits());
-  Emit(MRS | ImmSystemRegister(sysreg) | Rt(rt));
+void Assembler::mrs(const Register& xt, SystemRegister sysreg) {
+  VIXL_ASSERT(xt.Is64Bits());
+  Emit(MRS | ImmSystemRegister(sysreg) | Rt(xt));
 }
 
 
-void Assembler::msr(SystemRegister sysreg, const Register& rt) {
-  VIXL_ASSERT(rt.Is64Bits());
-  Emit(MSR | Rt(rt) | ImmSystemRegister(sysreg));
+void Assembler::msr(SystemRegister sysreg, const Register& xt) {
+  VIXL_ASSERT(xt.Is64Bits());
+  Emit(MSR | Rt(xt) | ImmSystemRegister(sysreg));
 }
 
 
-void Assembler::clrex(int imm4) {
-  Emit(CLREX | CRm(imm4));
-}
+void Assembler::clrex(int imm4) { Emit(CLREX | CRm(imm4)); }
 
 
 void Assembler::dmb(BarrierDomain domain, BarrierType type) {
@@ -2593,7 +2570,7 @@
   } else {
     VIXL_ASSERT(vd.Is2S() | vd.Is4S());
     Instr op = NEONModifiedImmediate_MOVI;
-    Instr q = vd.Is4S() ?  NEON_Q : 0;
+    Instr q = vd.Is4S() ? NEON_Q : 0;
     uint32_t encoded_imm = FP32ToImm8(imm);
     Emit(q | op | ImmNEONabcdefgh(encoded_imm) | NEONCmode(0xf) | Rd(vd));
   }
@@ -2702,26 +2679,22 @@
 }
 
 
-void Assembler::fcmp(const VRegister& vn,
-                     const VRegister& vm) {
+void Assembler::fcmp(const VRegister& vn, const VRegister& vm) {
   FPCompareMacro(vn, vm, DisableTrap);
 }
 
 
-void Assembler::fcmpe(const VRegister& vn,
-                      const VRegister& vm) {
+void Assembler::fcmpe(const VRegister& vn, const VRegister& vm) {
   FPCompareMacro(vn, vm, EnableTrap);
 }
 
 
-void Assembler::fcmp(const VRegister& vn,
-                     double value) {
+void Assembler::fcmp(const VRegister& vn, double value) {
   FPCompareMacro(vn, value, DisableTrap);
 }
 
 
-void Assembler::fcmpe(const VRegister& vn,
-                      double value) {
+void Assembler::fcmpe(const VRegister& vn, double value) {
   FPCompareMacro(vn, value, EnableTrap);
 }
 
@@ -2781,8 +2754,7 @@
 }
 
 
-void Assembler::fcvt(const VRegister& vd,
-                     const VRegister& vn) {
+void Assembler::fcvt(const VRegister& vd, const VRegister& vn) {
   FPDataProcessing1SourceOp op;
   if (vd.Is1D()) {
     VIXL_ASSERT(vn.Is1S() || vn.Is1H());
@@ -2799,44 +2771,35 @@
 }
 
 
-void Assembler::fcvtl(const VRegister& vd,
-                      const VRegister& vn) {
-  VIXL_ASSERT((vd.Is4S() && vn.Is4H()) ||
-              (vd.Is2D() && vn.Is2S()));
+void Assembler::fcvtl(const VRegister& vd, const VRegister& vn) {
+  VIXL_ASSERT((vd.Is4S() && vn.Is4H()) || (vd.Is2D() && vn.Is2S()));
   Instr format = vd.Is2D() ? (1 << NEONSize_offset) : 0;
   Emit(format | NEON_FCVTL | Rn(vn) | Rd(vd));
 }
 
 
-void Assembler::fcvtl2(const VRegister& vd,
-                       const VRegister& vn) {
-  VIXL_ASSERT((vd.Is4S() && vn.Is8H()) ||
-              (vd.Is2D() && vn.Is4S()));
+void Assembler::fcvtl2(const VRegister& vd, const VRegister& vn) {
+  VIXL_ASSERT((vd.Is4S() && vn.Is8H()) || (vd.Is2D() && vn.Is4S()));
   Instr format = vd.Is2D() ? (1 << NEONSize_offset) : 0;
   Emit(NEON_Q | format | NEON_FCVTL | Rn(vn) | Rd(vd));
 }
 
 
-void Assembler::fcvtn(const VRegister& vd,
-                      const VRegister& vn) {
-  VIXL_ASSERT((vn.Is4S() && vd.Is4H()) ||
-              (vn.Is2D() && vd.Is2S()));
+void Assembler::fcvtn(const VRegister& vd, const VRegister& vn) {
+  VIXL_ASSERT((vn.Is4S() && vd.Is4H()) || (vn.Is2D() && vd.Is2S()));
   Instr format = vn.Is2D() ? (1 << NEONSize_offset) : 0;
   Emit(format | NEON_FCVTN | Rn(vn) | Rd(vd));
 }
 
 
-void Assembler::fcvtn2(const VRegister& vd,
-                       const VRegister& vn) {
-  VIXL_ASSERT((vn.Is4S() && vd.Is8H()) ||
-              (vn.Is2D() && vd.Is4S()));
+void Assembler::fcvtn2(const VRegister& vd, const VRegister& vn) {
+  VIXL_ASSERT((vn.Is4S() && vd.Is8H()) || (vn.Is2D() && vd.Is4S()));
   Instr format = vn.Is2D() ? (1 << NEONSize_offset) : 0;
   Emit(NEON_Q | format | NEON_FCVTN | Rn(vn) | Rd(vd));
 }
 
 
-void Assembler::fcvtxn(const VRegister& vd,
-                       const VRegister& vn) {
+void Assembler::fcvtxn(const VRegister& vd, const VRegister& vn) {
   Instr format = 1 << NEONSize_offset;
   if (vd.IsScalar()) {
     VIXL_ASSERT(vd.Is1S() && vn.Is1D());
@@ -2848,40 +2811,35 @@
 }
 
 
-void Assembler::fcvtxn2(const VRegister& vd,
-                        const VRegister& vn) {
+void Assembler::fcvtxn2(const VRegister& vd, const VRegister& vn) {
   VIXL_ASSERT(vd.Is4S() && vn.Is2D());
   Instr format = 1 << NEONSize_offset;
   Emit(NEON_Q | format | NEON_FCVTXN | Rn(vn) | Rd(vd));
 }
 
 
-#define NEON_FP2REGMISC_FCVT_LIST(V)  \
-  V(fcvtnu, NEON_FCVTNU, FCVTNU)      \
-  V(fcvtns, NEON_FCVTNS, FCVTNS)      \
-  V(fcvtpu, NEON_FCVTPU, FCVTPU)      \
-  V(fcvtps, NEON_FCVTPS, FCVTPS)      \
-  V(fcvtmu, NEON_FCVTMU, FCVTMU)      \
-  V(fcvtms, NEON_FCVTMS, FCVTMS)      \
-  V(fcvtau, NEON_FCVTAU, FCVTAU)      \
+#define NEON_FP2REGMISC_FCVT_LIST(V) \
+  V(fcvtnu, NEON_FCVTNU, FCVTNU)     \
+  V(fcvtns, NEON_FCVTNS, FCVTNS)     \
+  V(fcvtpu, NEON_FCVTPU, FCVTPU)     \
+  V(fcvtps, NEON_FCVTPS, FCVTPS)     \
+  V(fcvtmu, NEON_FCVTMU, FCVTMU)     \
+  V(fcvtms, NEON_FCVTMS, FCVTMS)     \
+  V(fcvtau, NEON_FCVTAU, FCVTAU)     \
   V(fcvtas, NEON_FCVTAS, FCVTAS)
 
-#define DEFINE_ASM_FUNCS(FN, VEC_OP, SCA_OP)  \
-void Assembler::FN(const Register& rd,        \
-                   const VRegister& vn) {     \
-  NEONFPConvertToInt(rd, vn, SCA_OP);         \
-}                                             \
-void Assembler::FN(const VRegister& vd,       \
-                   const VRegister& vn) {     \
-  NEONFPConvertToInt(vd, vn, VEC_OP);         \
-}
+#define DEFINE_ASM_FUNCS(FN, VEC_OP, SCA_OP)                     \
+  void Assembler::FN(const Register& rd, const VRegister& vn) {  \
+    NEONFPConvertToInt(rd, vn, SCA_OP);                          \
+  }                                                              \
+  void Assembler::FN(const VRegister& vd, const VRegister& vn) { \
+    NEONFPConvertToInt(vd, vn, VEC_OP);                          \
+  }
 NEON_FP2REGMISC_FCVT_LIST(DEFINE_ASM_FUNCS)
 #undef DEFINE_ASM_FUNCS
 
 
-void Assembler::fcvtzs(const Register& rd,
-                       const VRegister& vn,
-                       int fbits) {
+void Assembler::fcvtzs(const Register& rd, const VRegister& vn, int fbits) {
   VIXL_ASSERT(vn.Is1S() || vn.Is1D());
   VIXL_ASSERT((fbits >= 0) && (fbits <= rd.SizeInBits()));
   if (fbits == 0) {
@@ -2893,9 +2851,7 @@
 }
 
 
-void Assembler::fcvtzs(const VRegister& vd,
-                       const VRegister& vn,
-                       int fbits) {
+void Assembler::fcvtzs(const VRegister& vd, const VRegister& vn, int fbits) {
   VIXL_ASSERT(fbits >= 0);
   if (fbits == 0) {
     NEONFP2RegMisc(vd, vn, NEON_FCVTZS);
@@ -2906,9 +2862,7 @@
 }
 
 
-void Assembler::fcvtzu(const Register& rd,
-                       const VRegister& vn,
-                       int fbits) {
+void Assembler::fcvtzu(const Register& rd, const VRegister& vn, int fbits) {
   VIXL_ASSERT(vn.Is1S() || vn.Is1D());
   VIXL_ASSERT((fbits >= 0) && (fbits <= rd.SizeInBits()));
   if (fbits == 0) {
@@ -2920,9 +2874,7 @@
 }
 
 
-void Assembler::fcvtzu(const VRegister& vd,
-                       const VRegister& vn,
-                       int fbits) {
+void Assembler::fcvtzu(const VRegister& vd, const VRegister& vn, int fbits) {
   VIXL_ASSERT(fbits >= 0);
   if (fbits == 0) {
     NEONFP2RegMisc(vd, vn, NEON_FCVTZU);
@@ -2932,9 +2884,7 @@
   }
 }
 
-void Assembler::ucvtf(const VRegister& vd,
-                      const VRegister& vn,
-                      int fbits) {
+void Assembler::ucvtf(const VRegister& vd, const VRegister& vn, int fbits) {
   VIXL_ASSERT(fbits >= 0);
   if (fbits == 0) {
     NEONFP2RegMisc(vd, vn, NEON_UCVTF);
@@ -2944,9 +2894,7 @@
   }
 }
 
-void Assembler::scvtf(const VRegister& vd,
-                      const VRegister& vn,
-                      int fbits) {
+void Assembler::scvtf(const VRegister& vd, const VRegister& vn, int fbits) {
   VIXL_ASSERT(fbits >= 0);
   if (fbits == 0) {
     NEONFP2RegMisc(vd, vn, NEON_SCVTF);
@@ -2957,9 +2905,7 @@
 }
 
 
-void Assembler::scvtf(const VRegister& vd,
-                      const Register& rn,
-                      int fbits) {
+void Assembler::scvtf(const VRegister& vd, const Register& rn, int fbits) {
   VIXL_ASSERT(vd.Is1S() || vd.Is1D());
   VIXL_ASSERT(fbits >= 0);
   if (fbits == 0) {
@@ -2971,9 +2917,7 @@
 }
 
 
-void Assembler::ucvtf(const VRegister& vd,
-                      const Register& rn,
-                      int fbits) {
+void Assembler::ucvtf(const VRegister& vd, const Register& rn, int fbits) {
   VIXL_ASSERT(vd.Is1S() || vd.Is1D());
   VIXL_ASSERT(fbits >= 0);
   if (fbits == 0) {
@@ -3013,6 +2957,7 @@
 }
 
 
+// clang-format off
 #define NEON_FP2REGMISC_LIST(V)                 \
   V(fabs,    NEON_FABS,    FABS)                \
   V(fneg,    NEON_FNEG,    FNEG)                \
@@ -3026,21 +2971,21 @@
   V(frinti,  NEON_FRINTI,  FRINTI)              \
   V(frsqrte, NEON_FRSQRTE, NEON_FRSQRTE_scalar) \
   V(frecpe,  NEON_FRECPE,  NEON_FRECPE_scalar )
+// clang-format on
 
 
-#define DEFINE_ASM_FUNC(FN, VEC_OP, SCA_OP)            \
-void Assembler::FN(const VRegister& vd,                \
-                   const VRegister& vn) {              \
-  Instr op;                                            \
-  if (vd.IsScalar()) {                                 \
-    VIXL_ASSERT(vd.Is1S() || vd.Is1D());               \
-    op = SCA_OP;                                       \
-  } else {                                             \
-    VIXL_ASSERT(vd.Is2S() || vd.Is2D() || vd.Is4S());  \
-    op = VEC_OP;                                       \
-  }                                                    \
-  NEONFP2RegMisc(vd, vn, op);                          \
-}
+#define DEFINE_ASM_FUNC(FN, VEC_OP, SCA_OP)                      \
+  void Assembler::FN(const VRegister& vd, const VRegister& vn) { \
+    Instr op;                                                    \
+    if (vd.IsScalar()) {                                         \
+      VIXL_ASSERT(vd.Is1S() || vd.Is1D());                       \
+      op = SCA_OP;                                               \
+    } else {                                                     \
+      VIXL_ASSERT(vd.Is2S() || vd.Is2D() || vd.Is4S());          \
+      op = VEC_OP;                                               \
+    }                                                            \
+    NEONFP2RegMisc(vd, vn, op);                                  \
+  }
 NEON_FP2REGMISC_LIST(DEFINE_ASM_FUNC)
 #undef DEFINE_ASM_FUNC
 
@@ -3073,49 +3018,37 @@
 }
 
 
-void Assembler::cmeq(const VRegister& vd,
-                     const VRegister& vn,
-                     int value) {
+void Assembler::cmeq(const VRegister& vd, const VRegister& vn, int value) {
   VIXL_ASSERT(vd.IsVector() || vd.Is1D());
   NEON2RegMisc(vd, vn, NEON_CMEQ_zero, value);
 }
 
 
-void Assembler::cmge(const VRegister& vd,
-                     const VRegister& vn,
-                     int value) {
+void Assembler::cmge(const VRegister& vd, const VRegister& vn, int value) {
   VIXL_ASSERT(vd.IsVector() || vd.Is1D());
   NEON2RegMisc(vd, vn, NEON_CMGE_zero, value);
 }
 
 
-void Assembler::cmgt(const VRegister& vd,
-                     const VRegister& vn,
-                     int value) {
+void Assembler::cmgt(const VRegister& vd, const VRegister& vn, int value) {
   VIXL_ASSERT(vd.IsVector() || vd.Is1D());
   NEON2RegMisc(vd, vn, NEON_CMGT_zero, value);
 }
 
 
-void Assembler::cmle(const VRegister& vd,
-                     const VRegister& vn,
-                     int value) {
+void Assembler::cmle(const VRegister& vd, const VRegister& vn, int value) {
   VIXL_ASSERT(vd.IsVector() || vd.Is1D());
   NEON2RegMisc(vd, vn, NEON_CMLE_zero, value);
 }
 
 
-void Assembler::cmlt(const VRegister& vd,
-                     const VRegister& vn,
-                     int value) {
+void Assembler::cmlt(const VRegister& vd, const VRegister& vn, int value) {
   VIXL_ASSERT(vd.IsVector() || vd.Is1D());
   NEON2RegMisc(vd, vn, NEON_CMLT_zero, value);
 }
 
 
-void Assembler::shll(const VRegister& vd,
-                     const VRegister& vn,
-                     int shift) {
+void Assembler::shll(const VRegister& vd, const VRegister& vn, int shift) {
   VIXL_ASSERT((vd.Is8H() && vn.Is8B() && shift == 8) ||
               (vd.Is4S() && vn.Is4H() && shift == 16) ||
               (vd.Is2D() && vn.Is2S() && shift == 32));
@@ -3124,9 +3057,7 @@
 }
 
 
-void Assembler::shll2(const VRegister& vd,
-                      const VRegister& vn,
-                      int shift) {
+void Assembler::shll2(const VRegister& vd, const VRegister& vn, int shift) {
   USE(shift);
   VIXL_ASSERT((vd.Is8H() && vn.Is16B() && shift == 8) ||
               (vd.Is4S() && vn.Is8H() && shift == 16) ||
@@ -3155,43 +3086,32 @@
 }
 
 
-void Assembler::fcmeq(const VRegister& vd,
-                      const VRegister& vn,
-                      double value) {
+void Assembler::fcmeq(const VRegister& vd, const VRegister& vn, double value) {
   NEONFP2RegMisc(vd, vn, NEON_FCMEQ_zero, value);
 }
 
 
-void Assembler::fcmge(const VRegister& vd,
-                      const VRegister& vn,
-                      double value) {
+void Assembler::fcmge(const VRegister& vd, const VRegister& vn, double value) {
   NEONFP2RegMisc(vd, vn, NEON_FCMGE_zero, value);
 }
 
 
-void Assembler::fcmgt(const VRegister& vd,
-                      const VRegister& vn,
-                      double value) {
+void Assembler::fcmgt(const VRegister& vd, const VRegister& vn, double value) {
   NEONFP2RegMisc(vd, vn, NEON_FCMGT_zero, value);
 }
 
 
-void Assembler::fcmle(const VRegister& vd,
-                      const VRegister& vn,
-                      double value) {
+void Assembler::fcmle(const VRegister& vd, const VRegister& vn, double value) {
   NEONFP2RegMisc(vd, vn, NEON_FCMLE_zero, value);
 }
 
 
-void Assembler::fcmlt(const VRegister& vd,
-                      const VRegister& vn,
-                      double value) {
+void Assembler::fcmlt(const VRegister& vd, const VRegister& vn, double value) {
   NEONFP2RegMisc(vd, vn, NEON_FCMLT_zero, value);
 }
 
 
-void Assembler::frecpx(const VRegister& vd,
-                       const VRegister& vn) {
+void Assembler::frecpx(const VRegister& vd, const VRegister& vn) {
   VIXL_ASSERT(vd.IsScalar());
   VIXL_ASSERT(AreSameFormat(vd, vn));
   VIXL_ASSERT(vd.Is1S() || vd.Is1D());
@@ -3199,6 +3119,7 @@
 }
 
 
+// clang-format off
 #define NEON_3SAME_LIST(V) \
   V(add,      NEON_ADD,      vd.IsVector() || vd.Is1D())            \
   V(addp,     NEON_ADDP,     vd.IsVector() || vd.Is1D())            \
@@ -3253,18 +3174,20 @@
   V(uqshl,    NEON_UQSHL,    true)                                  \
   V(sqrshl,   NEON_SQRSHL,   true)                                  \
   V(uqrshl,   NEON_UQRSHL,   true)
+// clang-format on
 
-#define DEFINE_ASM_FUNC(FN, OP, AS)        \
-void Assembler::FN(const VRegister& vd,    \
-                   const VRegister& vn,    \
-                   const VRegister& vm) {  \
-  VIXL_ASSERT(AS);                         \
-  NEON3Same(vd, vn, vm, OP);               \
-}
+#define DEFINE_ASM_FUNC(FN, OP, AS)         \
+  void Assembler::FN(const VRegister& vd,   \
+                     const VRegister& vn,   \
+                     const VRegister& vm) { \
+    VIXL_ASSERT(AS);                        \
+    NEON3Same(vd, vn, vm, OP);              \
+  }
 NEON_3SAME_LIST(DEFINE_ASM_FUNC)
 #undef DEFINE_ASM_FUNC
 
 
+// clang-format off
 #define NEON_FP3SAME_OP_LIST(V)                  \
   V(fadd,    NEON_FADD,    FADD)                 \
   V(fsub,    NEON_FSUB,    FSUB)                 \
@@ -3290,83 +3213,69 @@
   V(fminp,   NEON_FMINP,   0)                    \
   V(fmaxnmp, NEON_FMAXNMP, 0)                    \
   V(fminnmp, NEON_FMINNMP, 0)
+// clang-format on
 
-#define DEFINE_ASM_FUNC(FN, VEC_OP, SCA_OP)            \
-void Assembler::FN(const VRegister& vd,                \
-                   const VRegister& vn,                \
-                   const VRegister& vm) {              \
-  Instr op;                                            \
-  if ((SCA_OP != 0) && vd.IsScalar()) {                \
-    VIXL_ASSERT(vd.Is1S() || vd.Is1D());               \
-    op = SCA_OP;                                       \
-  } else {                                             \
-    VIXL_ASSERT(vd.IsVector());                        \
-    VIXL_ASSERT(vd.Is2S() || vd.Is2D() || vd.Is4S());  \
-    op = VEC_OP;                                       \
-  }                                                    \
-  NEONFP3Same(vd, vn, vm, op);                         \
-}
+#define DEFINE_ASM_FUNC(FN, VEC_OP, SCA_OP)             \
+  void Assembler::FN(const VRegister& vd,               \
+                     const VRegister& vn,               \
+                     const VRegister& vm) {             \
+    Instr op;                                           \
+    if ((SCA_OP != 0) && vd.IsScalar()) {               \
+      VIXL_ASSERT(vd.Is1S() || vd.Is1D());              \
+      op = SCA_OP;                                      \
+    } else {                                            \
+      VIXL_ASSERT(vd.IsVector());                       \
+      VIXL_ASSERT(vd.Is2S() || vd.Is2D() || vd.Is4S()); \
+      op = VEC_OP;                                      \
+    }                                                   \
+    NEONFP3Same(vd, vn, vm, op);                        \
+  }
 NEON_FP3SAME_OP_LIST(DEFINE_ASM_FUNC)
 #undef DEFINE_ASM_FUNC
 
 
-void Assembler::addp(const VRegister& vd,
-                     const VRegister& vn) {
+void Assembler::addp(const VRegister& vd, const VRegister& vn) {
   VIXL_ASSERT((vd.Is1D() && vn.Is2D()));
   Emit(SFormat(vd) | NEON_ADDP_scalar | Rn(vn) | Rd(vd));
 }
 
 
-void Assembler::faddp(const VRegister& vd,
-                      const VRegister& vn) {
-  VIXL_ASSERT((vd.Is1S() && vn.Is2S()) ||
-              (vd.Is1D() && vn.Is2D()));
+void Assembler::faddp(const VRegister& vd, const VRegister& vn) {
+  VIXL_ASSERT((vd.Is1S() && vn.Is2S()) || (vd.Is1D() && vn.Is2D()));
   Emit(FPFormat(vd) | NEON_FADDP_scalar | Rn(vn) | Rd(vd));
 }
 
 
-void Assembler::fmaxp(const VRegister& vd,
-                      const VRegister& vn) {
-  VIXL_ASSERT((vd.Is1S() && vn.Is2S()) ||
-              (vd.Is1D() && vn.Is2D()));
+void Assembler::fmaxp(const VRegister& vd, const VRegister& vn) {
+  VIXL_ASSERT((vd.Is1S() && vn.Is2S()) || (vd.Is1D() && vn.Is2D()));
   Emit(FPFormat(vd) | NEON_FMAXP_scalar | Rn(vn) | Rd(vd));
 }
 
 
-void Assembler::fminp(const VRegister& vd,
-                      const VRegister& vn) {
-  VIXL_ASSERT((vd.Is1S() && vn.Is2S()) ||
-              (vd.Is1D() && vn.Is2D()));
+void Assembler::fminp(const VRegister& vd, const VRegister& vn) {
+  VIXL_ASSERT((vd.Is1S() && vn.Is2S()) || (vd.Is1D() && vn.Is2D()));
   Emit(FPFormat(vd) | NEON_FMINP_scalar | Rn(vn) | Rd(vd));
 }
 
 
-void Assembler::fmaxnmp(const VRegister& vd,
-                        const VRegister& vn) {
-  VIXL_ASSERT((vd.Is1S() && vn.Is2S()) ||
-              (vd.Is1D() && vn.Is2D()));
+void Assembler::fmaxnmp(const VRegister& vd, const VRegister& vn) {
+  VIXL_ASSERT((vd.Is1S() && vn.Is2S()) || (vd.Is1D() && vn.Is2D()));
   Emit(FPFormat(vd) | NEON_FMAXNMP_scalar | Rn(vn) | Rd(vd));
 }
 
 
-void Assembler::fminnmp(const VRegister& vd,
-                        const VRegister& vn) {
-  VIXL_ASSERT((vd.Is1S() && vn.Is2S()) ||
-              (vd.Is1D() && vn.Is2D()));
+void Assembler::fminnmp(const VRegister& vd, const VRegister& vn) {
+  VIXL_ASSERT((vd.Is1S() && vn.Is2S()) || (vd.Is1D() && vn.Is2D()));
   Emit(FPFormat(vd) | NEON_FMINNMP_scalar | Rn(vn) | Rd(vd));
 }
 
 
-void Assembler::orr(const VRegister& vd,
-                    const int imm8,
-                    const int left_shift) {
-  NEONModifiedImmShiftLsl(vd, imm8, left_shift,
-                          NEONModifiedImmediate_ORR);
+void Assembler::orr(const VRegister& vd, const int imm8, const int left_shift) {
+  NEONModifiedImmShiftLsl(vd, imm8, left_shift, NEONModifiedImmediate_ORR);
 }
 
 
-void Assembler::mov(const VRegister& vd,
-                    const VRegister& vn) {
+void Assembler::mov(const VRegister& vd, const VRegister& vn) {
   VIXL_ASSERT(AreSameFormat(vd, vn));
   if (vd.IsD()) {
     orr(vd.V8B(), vn.V8B(), vn.V8B());
@@ -3377,11 +3286,8 @@
 }
 
 
-void Assembler::bic(const VRegister& vd,
-                    const int imm8,
-                    const int left_shift) {
-  NEONModifiedImmShiftLsl(vd, imm8, left_shift,
-                          NEONModifiedImmediate_BIC);
+void Assembler::bic(const VRegister& vd, const int imm8, const int left_shift) {
+  NEONModifiedImmShiftLsl(vd, imm8, left_shift, NEONModifiedImmediate_BIC);
 }
 
 
@@ -3405,18 +3311,21 @@
          ImmNEONabcdefgh(imm8) | NEONCmode(0xe) | Rd(vd));
   } else if (shift == LSL) {
     VIXL_ASSERT(is_uint8(imm));
-    NEONModifiedImmShiftLsl(vd, static_cast<int>(imm), shift_amount,
+    NEONModifiedImmShiftLsl(vd,
+                            static_cast<int>(imm),
+                            shift_amount,
                             NEONModifiedImmediate_MOVI);
   } else {
     VIXL_ASSERT(is_uint8(imm));
-    NEONModifiedImmShiftMsl(vd, static_cast<int>(imm), shift_amount,
+    NEONModifiedImmShiftMsl(vd,
+                            static_cast<int>(imm),
+                            shift_amount,
                             NEONModifiedImmediate_MOVI);
   }
 }
 
 
-void Assembler::mvn(const VRegister& vd,
-                    const VRegister& vn) {
+void Assembler::mvn(const VRegister& vd, const VRegister& vn) {
   VIXL_ASSERT(AreSameFormat(vd, vn));
   if (vd.IsD()) {
     not_(vd.V8B(), vn.V8B());
@@ -3433,11 +3342,9 @@
                      const int shift_amount) {
   VIXL_ASSERT((shift == LSL) || (shift == MSL));
   if (shift == LSL) {
-    NEONModifiedImmShiftLsl(vd, imm8, shift_amount,
-                            NEONModifiedImmediate_MVNI);
+    NEONModifiedImmShiftLsl(vd, imm8, shift_amount, NEONModifiedImmediate_MVNI);
   } else {
-    NEONModifiedImmShiftMsl(vd, imm8, shift_amount,
-                            NEONModifiedImmediate_MVNI);
+    NEONModifiedImmShiftMsl(vd, imm8, shift_amount, NEONModifiedImmediate_MVNI);
   }
 }
 
@@ -3448,13 +3355,10 @@
                                 int vm_index,
                                 NEONByIndexedElementOp vop) {
   VIXL_ASSERT(AreSameFormat(vd, vn));
-  VIXL_ASSERT((vd.Is2S() && vm.Is1S()) ||
-              (vd.Is4S() && vm.Is1S()) ||
-              (vd.Is1S() && vm.Is1S()) ||
-              (vd.Is2D() && vm.Is1D()) ||
+  VIXL_ASSERT((vd.Is2S() && vm.Is1S()) || (vd.Is4S() && vm.Is1S()) ||
+              (vd.Is1S() && vm.Is1S()) || (vd.Is2D() && vm.Is1D()) ||
               (vd.Is1D() && vm.Is1D()));
-  VIXL_ASSERT((vm.Is1S() && (vm_index < 4)) ||
-              (vm.Is1D() && (vm_index < 2)));
+  VIXL_ASSERT((vm.Is1S() && (vm_index < 4)) || (vm.Is1D() && (vm_index < 2)));
 
   Instr op = vop;
   int index_num_bits = vm.Is1S() ? 2 : 1;
@@ -3462,8 +3366,8 @@
     op |= NEON_Q | NEONScalar;
   }
 
-  Emit(FPFormat(vd) | op | ImmNEONHLM(vm_index, index_num_bits) |
-       Rm(vm) | Rn(vn) | Rd(vd));
+  Emit(FPFormat(vd) | op | ImmNEONHLM(vm_index, index_num_bits) | Rm(vm) |
+       Rn(vn) | Rd(vd));
 }
 
 
@@ -3473,12 +3377,9 @@
                               int vm_index,
                               NEONByIndexedElementOp vop) {
   VIXL_ASSERT(AreSameFormat(vd, vn));
-  VIXL_ASSERT((vd.Is4H() && vm.Is1H()) ||
-              (vd.Is8H() && vm.Is1H()) ||
-              (vd.Is1H() && vm.Is1H()) ||
-              (vd.Is2S() && vm.Is1S()) ||
-              (vd.Is4S() && vm.Is1S()) ||
-              (vd.Is1S() && vm.Is1S()));
+  VIXL_ASSERT((vd.Is4H() && vm.Is1H()) || (vd.Is8H() && vm.Is1H()) ||
+              (vd.Is1H() && vm.Is1H()) || (vd.Is2S() && vm.Is1S()) ||
+              (vd.Is4S() && vm.Is1S()) || (vd.Is1S() && vm.Is1S()));
   VIXL_ASSERT((vm.Is1H() && (vm.code() < 16) && (vm_index < 8)) ||
               (vm.Is1S() && (vm_index < 4)));
 
@@ -3490,8 +3391,8 @@
   } else {
     format = VFormat(vn);
   }
-  Emit(format | op | ImmNEONHLM(vm_index, index_num_bits) |
-       Rm(vm) | Rn(vn) | Rd(vd));
+  Emit(format | op | ImmNEONHLM(vm_index, index_num_bits) | Rm(vm) | Rn(vn) |
+       Rd(vd));
 }
 
 
@@ -3518,49 +3419,54 @@
   } else {
     format = VFormat(vn);
   }
-  Emit(format | op | ImmNEONHLM(vm_index, index_num_bits) |
-       Rm(vm) | Rn(vn) | Rd(vd));
+  Emit(format | op | ImmNEONHLM(vm_index, index_num_bits) | Rm(vm) | Rn(vn) |
+       Rd(vd));
 }
 
 
+// clang-format off
 #define NEON_BYELEMENT_LIST(V)                         \
   V(mul,      NEON_MUL_byelement,      vn.IsVector())  \
   V(mla,      NEON_MLA_byelement,      vn.IsVector())  \
   V(mls,      NEON_MLS_byelement,      vn.IsVector())  \
   V(sqdmulh,  NEON_SQDMULH_byelement,  true)           \
   V(sqrdmulh, NEON_SQRDMULH_byelement, true)
+// clang-format on
 
 
-#define DEFINE_ASM_FUNC(FN, OP, AS)        \
-void Assembler::FN(const VRegister& vd,    \
-                   const VRegister& vn,    \
-                   const VRegister& vm,    \
-                   int vm_index) {         \
-  VIXL_ASSERT(AS);                         \
-  NEONByElement(vd, vn, vm, vm_index, OP); \
-}
+#define DEFINE_ASM_FUNC(FN, OP, AS)          \
+  void Assembler::FN(const VRegister& vd,    \
+                     const VRegister& vn,    \
+                     const VRegister& vm,    \
+                     int vm_index) {         \
+    VIXL_ASSERT(AS);                         \
+    NEONByElement(vd, vn, vm, vm_index, OP); \
+  }
 NEON_BYELEMENT_LIST(DEFINE_ASM_FUNC)
 #undef DEFINE_ASM_FUNC
 
 
+// clang-format off
 #define NEON_FPBYELEMENT_LIST(V) \
   V(fmul,  NEON_FMUL_byelement)  \
   V(fmla,  NEON_FMLA_byelement)  \
   V(fmls,  NEON_FMLS_byelement)  \
   V(fmulx, NEON_FMULX_byelement)
+// clang-format on
 
 
-#define DEFINE_ASM_FUNC(FN, OP)              \
-void Assembler::FN(const VRegister& vd,      \
-                   const VRegister& vn,      \
-                   const VRegister& vm,      \
-                   int vm_index) {           \
-  NEONFPByElement(vd, vn, vm, vm_index, OP); \
-}
+#define DEFINE_ASM_FUNC(FN, OP)                \
+  void Assembler::FN(const VRegister& vd,      \
+                     const VRegister& vn,      \
+                     const VRegister& vm,      \
+                     int vm_index) {           \
+    NEONFPByElement(vd, vn, vm, vm_index, OP); \
+  }
 NEON_FPBYELEMENT_LIST(DEFINE_ASM_FUNC)
 #undef DEFINE_ASM_FUNC
 
 
+// clang-format off
 #define NEON_BYELEMENT_LONG_LIST(V)                               \
   V(sqdmull,  NEON_SQDMULL_byelement, vn.IsScalar() || vn.IsD())  \
   V(sqdmull2, NEON_SQDMULL_byelement, vn.IsVector() && vn.IsQ())  \
@@ -3580,54 +3486,49 @@
   V(smlsl2,   NEON_SMLSL_byelement,   vn.IsVector() && vn.IsQ())  \
   V(umlsl,    NEON_UMLSL_byelement,   vn.IsVector() && vn.IsD())  \
   V(umlsl2,   NEON_UMLSL_byelement,   vn.IsVector() && vn.IsQ())
+// clang-format on
 
 
-#define DEFINE_ASM_FUNC(FN, OP, AS)         \
-void Assembler::FN(const VRegister& vd,     \
-                   const VRegister& vn,     \
-                   const VRegister& vm,     \
-                   int vm_index) {          \
-  VIXL_ASSERT(AS);                          \
-  NEONByElementL(vd, vn, vm, vm_index, OP); \
-}
+#define DEFINE_ASM_FUNC(FN, OP, AS)           \
+  void Assembler::FN(const VRegister& vd,     \
+                     const VRegister& vn,     \
+                     const VRegister& vm,     \
+                     int vm_index) {          \
+    VIXL_ASSERT(AS);                          \
+    NEONByElementL(vd, vn, vm, vm_index, OP); \
+  }
 NEON_BYELEMENT_LONG_LIST(DEFINE_ASM_FUNC)
 #undef DEFINE_ASM_FUNC
 
 
-void Assembler::suqadd(const VRegister& vd,
-                       const VRegister& vn) {
+void Assembler::suqadd(const VRegister& vd, const VRegister& vn) {
   NEON2RegMisc(vd, vn, NEON_SUQADD);
 }
 
 
-void Assembler::usqadd(const VRegister& vd,
-                       const VRegister& vn) {
+void Assembler::usqadd(const VRegister& vd, const VRegister& vn) {
   NEON2RegMisc(vd, vn, NEON_USQADD);
 }
 
 
-void Assembler::abs(const VRegister& vd,
-                    const VRegister& vn) {
+void Assembler::abs(const VRegister& vd, const VRegister& vn) {
   VIXL_ASSERT(vd.IsVector() || vd.Is1D());
   NEON2RegMisc(vd, vn, NEON_ABS);
 }
 
 
-void Assembler::sqabs(const VRegister& vd,
-                      const VRegister& vn) {
+void Assembler::sqabs(const VRegister& vd, const VRegister& vn) {
   NEON2RegMisc(vd, vn, NEON_SQABS);
 }
 
 
-void Assembler::neg(const VRegister& vd,
-                    const VRegister& vn) {
+void Assembler::neg(const VRegister& vd, const VRegister& vn) {
   VIXL_ASSERT(vd.IsVector() || vd.Is1D());
   NEON2RegMisc(vd, vn, NEON_NEG);
 }
 
 
-void Assembler::sqneg(const VRegister& vd,
-                      const VRegister& vn) {
+void Assembler::sqneg(const VRegister& vd, const VRegister& vn) {
   NEON2RegMisc(vd, vn, NEON_SQNEG);
 }
 
@@ -3637,91 +3538,77 @@
                         NEON2RegMiscOp vop) {
   Instr format, op = vop;
   if (vd.IsScalar()) {
-    VIXL_ASSERT((vd.Is1B() && vn.Is1H()) ||
-                (vd.Is1H() && vn.Is1S()) ||
+    VIXL_ASSERT((vd.Is1B() && vn.Is1H()) || (vd.Is1H() && vn.Is1S()) ||
                 (vd.Is1S() && vn.Is1D()));
     op |= NEON_Q | NEONScalar;
     format = SFormat(vd);
   } else {
-    VIXL_ASSERT((vd.Is8B() && vn.Is8H())  ||
-                (vd.Is4H() && vn.Is4S())  ||
-                (vd.Is2S() && vn.Is2D())  ||
-                (vd.Is16B() && vn.Is8H()) ||
-                (vd.Is8H() && vn.Is4S())  ||
-                (vd.Is4S() && vn.Is2D()));
+    VIXL_ASSERT((vd.Is8B() && vn.Is8H()) || (vd.Is4H() && vn.Is4S()) ||
+                (vd.Is2S() && vn.Is2D()) || (vd.Is16B() && vn.Is8H()) ||
+                (vd.Is8H() && vn.Is4S()) || (vd.Is4S() && vn.Is2D()));
     format = VFormat(vd);
   }
   Emit(format | op | Rn(vn) | Rd(vd));
 }
 
 
-void Assembler::xtn(const VRegister& vd,
-                    const VRegister& vn) {
+void Assembler::xtn(const VRegister& vd, const VRegister& vn) {
   VIXL_ASSERT(vd.IsVector() && vd.IsD());
   NEONXtn(vd, vn, NEON_XTN);
 }
 
 
-void Assembler::xtn2(const VRegister& vd,
-                     const VRegister& vn) {
+void Assembler::xtn2(const VRegister& vd, const VRegister& vn) {
   VIXL_ASSERT(vd.IsVector() && vd.IsQ());
   NEONXtn(vd, vn, NEON_XTN);
 }
 
 
-void Assembler::sqxtn(const VRegister& vd,
-                      const VRegister& vn) {
+void Assembler::sqxtn(const VRegister& vd, const VRegister& vn) {
   VIXL_ASSERT(vd.IsScalar() || vd.IsD());
   NEONXtn(vd, vn, NEON_SQXTN);
 }
 
 
-void Assembler::sqxtn2(const VRegister& vd,
-                       const VRegister& vn) {
+void Assembler::sqxtn2(const VRegister& vd, const VRegister& vn) {
   VIXL_ASSERT(vd.IsVector() && vd.IsQ());
   NEONXtn(vd, vn, NEON_SQXTN);
 }
 
 
-void Assembler::sqxtun(const VRegister& vd,
-                       const VRegister& vn) {
+void Assembler::sqxtun(const VRegister& vd, const VRegister& vn) {
   VIXL_ASSERT(vd.IsScalar() || vd.IsD());
   NEONXtn(vd, vn, NEON_SQXTUN);
 }
 
 
-void Assembler::sqxtun2(const VRegister& vd,
-                        const VRegister& vn) {
+void Assembler::sqxtun2(const VRegister& vd, const VRegister& vn) {
   VIXL_ASSERT(vd.IsVector() && vd.IsQ());
   NEONXtn(vd, vn, NEON_SQXTUN);
 }
 
 
-void Assembler::uqxtn(const VRegister& vd,
-                      const VRegister& vn) {
+void Assembler::uqxtn(const VRegister& vd, const VRegister& vn) {
   VIXL_ASSERT(vd.IsScalar() || vd.IsD());
   NEONXtn(vd, vn, NEON_UQXTN);
 }
 
 
-void Assembler::uqxtn2(const VRegister& vd,
-                       const VRegister& vn) {
+void Assembler::uqxtn2(const VRegister& vd, const VRegister& vn) {
   VIXL_ASSERT(vd.IsVector() && vd.IsQ());
   NEONXtn(vd, vn, NEON_UQXTN);
 }
 
 
 // NEON NOT and RBIT are distinguised by bit 22, the bottom bit of "size".
-void Assembler::not_(const VRegister& vd,
-                     const VRegister& vn) {
+void Assembler::not_(const VRegister& vd, const VRegister& vn) {
   VIXL_ASSERT(AreSameFormat(vd, vn));
   VIXL_ASSERT(vd.Is8B() || vd.Is16B());
   Emit(VFormat(vd) | NEON_RBIT_NOT | Rn(vn) | Rd(vd));
 }
 
 
-void Assembler::rbit(const VRegister& vd,
-                     const VRegister& vn) {
+void Assembler::rbit(const VRegister& vd, const VRegister& vn) {
   VIXL_ASSERT(AreSameFormat(vd, vn));
   VIXL_ASSERT(vd.Is8B() || vd.Is16B());
   Emit(VFormat(vn) | (1 << NEONSize_offset) | NEON_RBIT_NOT | Rn(vn) | Rd(vd));
@@ -3739,9 +3626,7 @@
 }
 
 
-void Assembler::dup(const VRegister& vd,
-                    const VRegister& vn,
-                    int vn_index) {
+void Assembler::dup(const VRegister& vd, const VRegister& vn, int vn_index) {
   Instr q, scalar;
 
   // We support vn arguments of the form vn.VxT() or vn.T(), where x is the
@@ -3749,9 +3634,15 @@
   int lane_size = vn.LaneSizeInBytes();
   NEONFormatField format;
   switch (lane_size) {
-    case 1: format = NEON_16B; break;
-    case 2: format = NEON_8H;  break;
-    case 4: format = NEON_4S;  break;
+    case 1:
+      format = NEON_16B;
+      break;
+    case 2:
+      format = NEON_8H;
+      break;
+    case 4:
+      format = NEON_4S;
+      break;
     default:
       VIXL_ASSERT(lane_size == 8);
       format = NEON_2D;
@@ -3766,14 +3657,12 @@
     q = vd.IsD() ? 0 : NEON_Q;
     scalar = 0;
   }
-  Emit(q | scalar | NEON_DUP_ELEMENT |
-       ImmNEON5(format, vn_index) | Rn(vn) | Rd(vd));
+  Emit(q | scalar | NEON_DUP_ELEMENT | ImmNEON5(format, vn_index) | Rn(vn) |
+       Rd(vd));
 }
 
 
-void Assembler::mov(const VRegister& vd,
-                    const VRegister& vn,
-                    int vn_index) {
+void Assembler::mov(const VRegister& vd, const VRegister& vn, int vn_index) {
   VIXL_ASSERT(vn.IsScalar());
   dup(vd, vn, vn_index);
 }
@@ -3797,19 +3686,27 @@
   int lane_size = vd.LaneSizeInBytes();
   NEONFormatField format;
   switch (lane_size) {
-    case 1: format = NEON_16B; break;
-    case 2: format = NEON_8H;  break;
-    case 4: format = NEON_4S;  break;
+    case 1:
+      format = NEON_16B;
+      break;
+    case 2:
+      format = NEON_8H;
+      break;
+    case 4:
+      format = NEON_4S;
+      break;
     default:
       VIXL_ASSERT(lane_size == 8);
       format = NEON_2D;
       break;
   }
 
-  VIXL_ASSERT((0 <= vd_index) &&
-          (vd_index < LaneCountFromFormat(static_cast<VectorFormat>(format))));
-  VIXL_ASSERT((0 <= vn_index) &&
-          (vn_index < LaneCountFromFormat(static_cast<VectorFormat>(format))));
+  VIXL_ASSERT(
+      (0 <= vd_index) &&
+      (vd_index < LaneCountFromFormat(static_cast<VectorFormat>(format))));
+  VIXL_ASSERT(
+      (0 <= vn_index) &&
+      (vn_index < LaneCountFromFormat(static_cast<VectorFormat>(format))));
   Emit(NEON_INS_ELEMENT | ImmNEON5(format, vd_index) |
        ImmNEON4(format, vn_index) | Rn(vn) | Rd(vd));
 }
@@ -3823,17 +3720,24 @@
 }
 
 
-void Assembler::ins(const VRegister& vd,
-                    int vd_index,
-                    const Register& rn) {
+void Assembler::ins(const VRegister& vd, int vd_index, const Register& rn) {
   // We support vd arguments of the form vd.VxT() or vd.T(), where x is the
   // number of lanes, and T is b, h, s or d.
   int lane_size = vd.LaneSizeInBytes();
   NEONFormatField format;
   switch (lane_size) {
-    case 1: format = NEON_16B; VIXL_ASSERT(rn.IsW()); break;
-    case 2: format = NEON_8H;  VIXL_ASSERT(rn.IsW()); break;
-    case 4: format = NEON_4S;  VIXL_ASSERT(rn.IsW()); break;
+    case 1:
+      format = NEON_16B;
+      VIXL_ASSERT(rn.IsW());
+      break;
+    case 2:
+      format = NEON_8H;
+      VIXL_ASSERT(rn.IsW());
+      break;
+    case 4:
+      format = NEON_4S;
+      VIXL_ASSERT(rn.IsW());
+      break;
     default:
       VIXL_ASSERT(lane_size == 8);
       VIXL_ASSERT(rn.IsX());
@@ -3841,31 +3745,37 @@
       break;
   }
 
-  VIXL_ASSERT((0 <= vd_index) &&
-          (vd_index < LaneCountFromFormat(static_cast<VectorFormat>(format))));
+  VIXL_ASSERT(
+      (0 <= vd_index) &&
+      (vd_index < LaneCountFromFormat(static_cast<VectorFormat>(format))));
   Emit(NEON_INS_GENERAL | ImmNEON5(format, vd_index) | Rn(rn) | Rd(vd));
 }
 
 
-void Assembler::mov(const VRegister& vd,
-                    int vd_index,
-                    const Register& rn) {
+void Assembler::mov(const VRegister& vd, int vd_index, const Register& rn) {
   ins(vd, vd_index, rn);
 }
 
 
-void Assembler::umov(const Register& rd,
-                     const VRegister& vn,
-                     int vn_index) {
+void Assembler::umov(const Register& rd, const VRegister& vn, int vn_index) {
   // We support vd arguments of the form vd.VxT() or vd.T(), where x is the
   // number of lanes, and T is b, h, s or d.
   int lane_size = vn.LaneSizeInBytes();
   NEONFormatField format;
   Instr q = 0;
   switch (lane_size) {
-    case 1: format = NEON_16B; VIXL_ASSERT(rd.IsW()); break;
-    case 2: format = NEON_8H;  VIXL_ASSERT(rd.IsW()); break;
-    case 4: format = NEON_4S;  VIXL_ASSERT(rd.IsW()); break;
+    case 1:
+      format = NEON_16B;
+      VIXL_ASSERT(rd.IsW());
+      break;
+    case 2:
+      format = NEON_8H;
+      VIXL_ASSERT(rd.IsW());
+      break;
+    case 4:
+      format = NEON_4S;
+      VIXL_ASSERT(rd.IsW());
+      break;
     default:
       VIXL_ASSERT(lane_size == 8);
       VIXL_ASSERT(rd.IsX());
@@ -3874,23 +3784,20 @@
       break;
   }
 
-  VIXL_ASSERT((0 <= vn_index) &&
-          (vn_index < LaneCountFromFormat(static_cast<VectorFormat>(format))));
+  VIXL_ASSERT(
+      (0 <= vn_index) &&
+      (vn_index < LaneCountFromFormat(static_cast<VectorFormat>(format))));
   Emit(q | NEON_UMOV | ImmNEON5(format, vn_index) | Rn(vn) | Rd(rd));
 }
 
 
-void Assembler::mov(const Register& rd,
-                    const VRegister& vn,
-                    int vn_index) {
+void Assembler::mov(const Register& rd, const VRegister& vn, int vn_index) {
   VIXL_ASSERT(vn.SizeInBytes() >= 4);
   umov(rd, vn, vn_index);
 }
 
 
-void Assembler::smov(const Register& rd,
-                     const VRegister& vn,
-                     int vn_index) {
+void Assembler::smov(const Register& rd, const VRegister& vn, int vn_index) {
   // We support vd arguments of the form vd.VxT() or vd.T(), where x is the
   // number of lanes, and T is b, h, s.
   int lane_size = vn.LaneSizeInBytes();
@@ -3898,8 +3805,12 @@
   Instr q = 0;
   VIXL_ASSERT(lane_size != 8);
   switch (lane_size) {
-    case 1: format = NEON_16B; break;
-    case 2: format = NEON_8H;  break;
+    case 1:
+      format = NEON_16B;
+      break;
+    case 2:
+      format = NEON_8H;
+      break;
     default:
       VIXL_ASSERT(lane_size == 4);
       VIXL_ASSERT(rd.IsX());
@@ -3907,70 +3818,63 @@
       break;
   }
   q = rd.IsW() ? 0 : NEON_Q;
-  VIXL_ASSERT((0 <= vn_index) &&
-          (vn_index < LaneCountFromFormat(static_cast<VectorFormat>(format))));
+  VIXL_ASSERT(
+      (0 <= vn_index) &&
+      (vn_index < LaneCountFromFormat(static_cast<VectorFormat>(format))));
   Emit(q | NEON_SMOV | ImmNEON5(format, vn_index) | Rn(vn) | Rd(rd));
 }
 
 
-void Assembler::cls(const VRegister& vd,
-                    const VRegister& vn) {
+void Assembler::cls(const VRegister& vd, const VRegister& vn) {
   VIXL_ASSERT(AreSameFormat(vd, vn));
   VIXL_ASSERT(!vd.Is1D() && !vd.Is2D());
   Emit(VFormat(vn) | NEON_CLS | Rn(vn) | Rd(vd));
 }
 
 
-void Assembler::clz(const VRegister& vd,
-                    const VRegister& vn) {
+void Assembler::clz(const VRegister& vd, const VRegister& vn) {
   VIXL_ASSERT(AreSameFormat(vd, vn));
   VIXL_ASSERT(!vd.Is1D() && !vd.Is2D());
   Emit(VFormat(vn) | NEON_CLZ | Rn(vn) | Rd(vd));
 }
 
 
-void Assembler::cnt(const VRegister& vd,
-                    const VRegister& vn) {
+void Assembler::cnt(const VRegister& vd, const VRegister& vn) {
   VIXL_ASSERT(AreSameFormat(vd, vn));
   VIXL_ASSERT(vd.Is8B() || vd.Is16B());
   Emit(VFormat(vn) | NEON_CNT | Rn(vn) | Rd(vd));
 }
 
 
-void Assembler::rev16(const VRegister& vd,
-                      const VRegister& vn) {
+void Assembler::rev16(const VRegister& vd, const VRegister& vn) {
   VIXL_ASSERT(AreSameFormat(vd, vn));
   VIXL_ASSERT(vd.Is8B() || vd.Is16B());
   Emit(VFormat(vn) | NEON_REV16 | Rn(vn) | Rd(vd));
 }
 
 
-void Assembler::rev32(const VRegister& vd,
-                      const VRegister& vn) {
+void Assembler::rev32(const VRegister& vd, const VRegister& vn) {
   VIXL_ASSERT(AreSameFormat(vd, vn));
   VIXL_ASSERT(vd.Is8B() || vd.Is16B() || vd.Is4H() || vd.Is8H());
   Emit(VFormat(vn) | NEON_REV32 | Rn(vn) | Rd(vd));
 }
 
 
-void Assembler::rev64(const VRegister& vd,
-                      const VRegister& vn) {
+void Assembler::rev64(const VRegister& vd, const VRegister& vn) {
   VIXL_ASSERT(AreSameFormat(vd, vn));
   VIXL_ASSERT(!vd.Is1D() && !vd.Is2D());
   Emit(VFormat(vn) | NEON_REV64 | Rn(vn) | Rd(vd));
 }
 
 
-void Assembler::ursqrte(const VRegister& vd,
-                        const VRegister& vn) {
+void Assembler::ursqrte(const VRegister& vd, const VRegister& vn) {
   VIXL_ASSERT(AreSameFormat(vd, vn));
   VIXL_ASSERT(vd.Is2S() || vd.Is4S());
   Emit(VFormat(vn) | NEON_URSQRTE | Rn(vn) | Rd(vd));
 }
 
 
-void Assembler::urecpe(const VRegister& vd,
-                       const VRegister& vn) {
+void Assembler::urecpe(const VRegister& vd, const VRegister& vn) {
   VIXL_ASSERT(AreSameFormat(vd, vn));
   VIXL_ASSERT(vd.Is2S() || vd.Is4S());
   Emit(VFormat(vn) | NEON_URECPE | Rn(vn) | Rd(vd));
@@ -3980,41 +3884,32 @@
 void Assembler::NEONAddlp(const VRegister& vd,
                           const VRegister& vn,
                           NEON2RegMiscOp op) {
-  VIXL_ASSERT((op == NEON_SADDLP) ||
-              (op == NEON_UADDLP) ||
-              (op == NEON_SADALP) ||
-              (op == NEON_UADALP));
+  VIXL_ASSERT((op == NEON_SADDLP) || (op == NEON_UADDLP) ||
+              (op == NEON_SADALP) || (op == NEON_UADALP));
 
-  VIXL_ASSERT((vn.Is8B() && vd.Is4H()) ||
-              (vn.Is4H() && vd.Is2S()) ||
-              (vn.Is2S() && vd.Is1D()) ||
-              (vn.Is16B() && vd.Is8H())||
-              (vn.Is8H() && vd.Is4S()) ||
-              (vn.Is4S() && vd.Is2D()));
+  VIXL_ASSERT((vn.Is8B() && vd.Is4H()) || (vn.Is4H() && vd.Is2S()) ||
+              (vn.Is2S() && vd.Is1D()) || (vn.Is16B() && vd.Is8H()) ||
+              (vn.Is8H() && vd.Is4S()) || (vn.Is4S() && vd.Is2D()));
   Emit(VFormat(vn) | op | Rn(vn) | Rd(vd));
 }
 
 
-void Assembler::saddlp(const VRegister& vd,
-                       const VRegister& vn) {
+void Assembler::saddlp(const VRegister& vd, const VRegister& vn) {
   NEONAddlp(vd, vn, NEON_SADDLP);
 }
 
 
-void Assembler::uaddlp(const VRegister& vd,
-                       const VRegister& vn) {
+void Assembler::uaddlp(const VRegister& vd, const VRegister& vn) {
   NEONAddlp(vd, vn, NEON_UADDLP);
 }
 
 
-void Assembler::sadalp(const VRegister& vd,
-                       const VRegister& vn) {
+void Assembler::sadalp(const VRegister& vd, const VRegister& vn) {
   NEONAddlp(vd, vn, NEON_SADALP);
 }
 
 
-void Assembler::uadalp(const VRegister& vd,
-                       const VRegister& vn) {
+void Assembler::uadalp(const VRegister& vd, const VRegister& vn) {
   NEONAddlp(vd, vn, NEON_UADALP);
 }
 
@@ -4022,23 +3917,19 @@
 void Assembler::NEONAcrossLanesL(const VRegister& vd,
                                  const VRegister& vn,
                                  NEONAcrossLanesOp op) {
-  VIXL_ASSERT((vn.Is8B()  && vd.Is1H()) ||
-              (vn.Is16B() && vd.Is1H()) ||
-              (vn.Is4H()  && vd.Is1S()) ||
-              (vn.Is8H()  && vd.Is1S()) ||
-              (vn.Is4S()  && vd.Is1D()));
+  VIXL_ASSERT((vn.Is8B() && vd.Is1H()) || (vn.Is16B() && vd.Is1H()) ||
+              (vn.Is4H() && vd.Is1S()) || (vn.Is8H() && vd.Is1S()) ||
+              (vn.Is4S() && vd.Is1D()));
   Emit(VFormat(vn) | op | Rn(vn) | Rd(vd));
 }
 
 
-void Assembler::saddlv(const VRegister& vd,
-                       const VRegister& vn) {
+void Assembler::saddlv(const VRegister& vd, const VRegister& vn) {
   NEONAcrossLanesL(vd, vn, NEON_SADDLV);
 }
 
 
-void Assembler::uaddlv(const VRegister& vd,
-                       const VRegister& vn) {
+void Assembler::uaddlv(const VRegister& vd, const VRegister& vn) {
   NEONAcrossLanesL(vd, vn, NEON_UADDLV);
 }
 
@@ -4046,11 +3937,9 @@
 void Assembler::NEONAcrossLanes(const VRegister& vd,
                                 const VRegister& vn,
                                 NEONAcrossLanesOp op) {
-  VIXL_ASSERT((vn.Is8B()  && vd.Is1B()) ||
-              (vn.Is16B() && vd.Is1B()) ||
-              (vn.Is4H()  && vd.Is1H()) ||
-              (vn.Is8H()  && vd.Is1H()) ||
-              (vn.Is4S()  && vd.Is1S()));
+  VIXL_ASSERT((vn.Is8B() && vd.Is1B()) || (vn.Is16B() && vd.Is1B()) ||
+              (vn.Is4H() && vd.Is1H()) || (vn.Is8H() && vd.Is1H()) ||
+              (vn.Is4S() && vd.Is1S()));
   if ((op & NEONAcrossLanesFPFMask) == NEONAcrossLanesFPFixed) {
     Emit(FPFormat(vn) | op | Rn(vn) | Rd(vd));
   } else {
@@ -4059,24 +3948,23 @@
 }
 
 
-#define NEON_ACROSSLANES_LIST(V) \
-  V(fmaxv,   NEON_FMAXV,   vd.Is1S()) \
-  V(fminv,   NEON_FMINV,   vd.Is1S()) \
+#define NEON_ACROSSLANES_LIST(V)      \
+  V(fmaxv, NEON_FMAXV, vd.Is1S())     \
+  V(fminv, NEON_FMINV, vd.Is1S())     \
   V(fmaxnmv, NEON_FMAXNMV, vd.Is1S()) \
   V(fminnmv, NEON_FMINNMV, vd.Is1S()) \
-  V(addv,    NEON_ADDV,    true)      \
-  V(smaxv,   NEON_SMAXV,   true)      \
-  V(sminv,   NEON_SMINV,   true)      \
-  V(umaxv,   NEON_UMAXV,   true)      \
-  V(uminv,   NEON_UMINV,   true)
+  V(addv, NEON_ADDV, true)            \
+  V(smaxv, NEON_SMAXV, true)          \
+  V(sminv, NEON_SMINV, true)          \
+  V(umaxv, NEON_UMAXV, true)          \
+  V(uminv, NEON_UMINV, true)
 
 
-#define DEFINE_ASM_FUNC(FN, OP, AS)        \
-void Assembler::FN(const VRegister& vd,    \
-                   const VRegister& vn) {  \
-  VIXL_ASSERT(AS);                         \
-  NEONAcrossLanes(vd, vn, OP);             \
-}
+#define DEFINE_ASM_FUNC(FN, OP, AS)                              \
+  void Assembler::FN(const VRegister& vd, const VRegister& vn) { \
+    VIXL_ASSERT(AS);                                             \
+    NEONAcrossLanes(vd, vn, OP);                                 \
+  }
 NEON_ACROSSLANES_LIST(DEFINE_ASM_FUNC)
 #undef DEFINE_ASM_FUNC
 
@@ -4178,12 +4066,9 @@
   VIXL_ASSERT((shift >= 0) && (shift < laneSizeInBits));
   int immh_immb = (laneSizeInBits + shift) << 16;
 
-  VIXL_ASSERT((vn.Is8B() && vd.Is8H()) ||
-              (vn.Is4H() && vd.Is4S()) ||
-              (vn.Is2S() && vd.Is2D()) ||
-              (vn.Is16B() && vd.Is8H())||
-              (vn.Is8H() && vd.Is4S()) ||
-              (vn.Is4S() && vd.Is2D()));
+  VIXL_ASSERT((vn.Is8B() && vd.Is8H()) || (vn.Is4H() && vd.Is4S()) ||
+              (vn.Is2S() && vd.Is2D()) || (vn.Is16B() && vd.Is8H()) ||
+              (vn.Is8H() && vd.Is4S()) || (vn.Is4S() && vd.Is2D()));
   Instr q;
   q = vn.IsD() ? 0 : NEON_Q;
   Emit(q | op | immh_immb | Rn(vn) | Rd(vd));
@@ -4200,18 +4085,14 @@
   int immh_immb = (2 * laneSizeInBits - shift) << 16;
 
   if (vn.IsScalar()) {
-    VIXL_ASSERT((vd.Is1B() && vn.Is1H()) ||
-                (vd.Is1H() && vn.Is1S()) ||
+    VIXL_ASSERT((vd.Is1B() && vn.Is1H()) || (vd.Is1H() && vn.Is1S()) ||
                 (vd.Is1S() && vn.Is1D()));
     q = NEON_Q;
     scalar = NEONScalar;
   } else {
-    VIXL_ASSERT((vd.Is8B() && vn.Is8H()) ||
-                (vd.Is4H() && vn.Is4S()) ||
-                (vd.Is2S() && vn.Is2D()) ||
-                (vd.Is16B() && vn.Is8H())||
-                (vd.Is8H() && vn.Is4S()) ||
-                (vd.Is4S() && vn.Is2D()));
+    VIXL_ASSERT((vd.Is8B() && vn.Is8H()) || (vd.Is4H() && vn.Is4S()) ||
+                (vd.Is2S() && vn.Is2D()) || (vd.Is16B() && vn.Is8H()) ||
+                (vd.Is8H() && vn.Is4S()) || (vd.Is4S() && vn.Is2D()));
     scalar = 0;
     q = vd.IsD() ? 0 : NEON_Q;
   }
@@ -4219,294 +4100,222 @@
 }
 
 
-void Assembler::shl(const VRegister& vd,
-                    const VRegister& vn,
-                    int shift) {
+void Assembler::shl(const VRegister& vd, const VRegister& vn, int shift) {
   VIXL_ASSERT(vd.IsVector() || vd.Is1D());
   NEONShiftLeftImmediate(vd, vn, shift, NEON_SHL);
 }
 
 
-void Assembler::sli(const VRegister& vd,
-                    const VRegister& vn,
-                    int shift) {
+void Assembler::sli(const VRegister& vd, const VRegister& vn, int shift) {
   VIXL_ASSERT(vd.IsVector() || vd.Is1D());
   NEONShiftLeftImmediate(vd, vn, shift, NEON_SLI);
 }
 
 
-void Assembler::sqshl(const VRegister& vd,
-                      const VRegister& vn,
-                      int shift) {
+void Assembler::sqshl(const VRegister& vd, const VRegister& vn, int shift) {
   NEONShiftLeftImmediate(vd, vn, shift, NEON_SQSHL_imm);
 }
 
 
-void Assembler::sqshlu(const VRegister& vd,
-                       const VRegister& vn,
-                       int shift) {
+void Assembler::sqshlu(const VRegister& vd, const VRegister& vn, int shift) {
   NEONShiftLeftImmediate(vd, vn, shift, NEON_SQSHLU);
 }
 
 
-void Assembler::uqshl(const VRegister& vd,
-                      const VRegister& vn,
-                      int shift) {
+void Assembler::uqshl(const VRegister& vd, const VRegister& vn, int shift) {
   NEONShiftLeftImmediate(vd, vn, shift, NEON_UQSHL_imm);
 }
 
 
-void Assembler::sshll(const VRegister& vd,
-                      const VRegister& vn,
-                      int shift) {
+void Assembler::sshll(const VRegister& vd, const VRegister& vn, int shift) {
   VIXL_ASSERT(vn.IsD());
   NEONShiftImmediateL(vd, vn, shift, NEON_SSHLL);
 }
 
 
-void Assembler::sshll2(const VRegister& vd,
-                       const VRegister& vn,
-                       int shift) {
+void Assembler::sshll2(const VRegister& vd, const VRegister& vn, int shift) {
   VIXL_ASSERT(vn.IsQ());
   NEONShiftImmediateL(vd, vn, shift, NEON_SSHLL);
 }
 
 
-void Assembler::sxtl(const VRegister& vd,
-                     const VRegister& vn) {
+void Assembler::sxtl(const VRegister& vd, const VRegister& vn) {
   sshll(vd, vn, 0);
 }
 
 
-void Assembler::sxtl2(const VRegister& vd,
-                      const VRegister& vn) {
+void Assembler::sxtl2(const VRegister& vd, const VRegister& vn) {
   sshll2(vd, vn, 0);
 }
 
 
-void Assembler::ushll(const VRegister& vd,
-                      const VRegister& vn,
-                      int shift) {
+void Assembler::ushll(const VRegister& vd, const VRegister& vn, int shift) {
   VIXL_ASSERT(vn.IsD());
   NEONShiftImmediateL(vd, vn, shift, NEON_USHLL);
 }
 
 
-void Assembler::ushll2(const VRegister& vd,
-                       const VRegister& vn,
-                       int shift) {
+void Assembler::ushll2(const VRegister& vd, const VRegister& vn, int shift) {
   VIXL_ASSERT(vn.IsQ());
   NEONShiftImmediateL(vd, vn, shift, NEON_USHLL);
 }
 
 
-void Assembler::uxtl(const VRegister& vd,
-                     const VRegister& vn) {
+void Assembler::uxtl(const VRegister& vd, const VRegister& vn) {
   ushll(vd, vn, 0);
 }
 
 
-void Assembler::uxtl2(const VRegister& vd,
-                      const VRegister& vn) {
+void Assembler::uxtl2(const VRegister& vd, const VRegister& vn) {
   ushll2(vd, vn, 0);
 }
 
 
-void Assembler::sri(const VRegister& vd,
-                    const VRegister& vn,
-                    int shift) {
+void Assembler::sri(const VRegister& vd, const VRegister& vn, int shift) {
   VIXL_ASSERT(vd.IsVector() || vd.Is1D());
   NEONShiftRightImmediate(vd, vn, shift, NEON_SRI);
 }
 
 
-void Assembler::sshr(const VRegister& vd,
-                     const VRegister& vn,
-                     int shift) {
+void Assembler::sshr(const VRegister& vd, const VRegister& vn, int shift) {
   VIXL_ASSERT(vd.IsVector() || vd.Is1D());
   NEONShiftRightImmediate(vd, vn, shift, NEON_SSHR);
 }
 
 
-void Assembler::ushr(const VRegister& vd,
-                     const VRegister& vn,
-                     int shift) {
+void Assembler::ushr(const VRegister& vd, const VRegister& vn, int shift) {
   VIXL_ASSERT(vd.IsVector() || vd.Is1D());
   NEONShiftRightImmediate(vd, vn, shift, NEON_USHR);
 }
 
 
-void Assembler::srshr(const VRegister& vd,
-                      const VRegister& vn,
-                      int shift) {
+void Assembler::srshr(const VRegister& vd, const VRegister& vn, int shift) {
   VIXL_ASSERT(vd.IsVector() || vd.Is1D());
   NEONShiftRightImmediate(vd, vn, shift, NEON_SRSHR);
 }
 
 
-void Assembler::urshr(const VRegister& vd,
-                      const VRegister& vn,
-                      int shift) {
+void Assembler::urshr(const VRegister& vd, const VRegister& vn, int shift) {
   VIXL_ASSERT(vd.IsVector() || vd.Is1D());
   NEONShiftRightImmediate(vd, vn, shift, NEON_URSHR);
 }
 
 
-void Assembler::ssra(const VRegister& vd,
-                     const VRegister& vn,
-                     int shift) {
+void Assembler::ssra(const VRegister& vd, const VRegister& vn, int shift) {
   VIXL_ASSERT(vd.IsVector() || vd.Is1D());
   NEONShiftRightImmediate(vd, vn, shift, NEON_SSRA);
 }
 
 
-void Assembler::usra(const VRegister& vd,
-                     const VRegister& vn,
-                     int shift) {
+void Assembler::usra(const VRegister& vd, const VRegister& vn, int shift) {
   VIXL_ASSERT(vd.IsVector() || vd.Is1D());
   NEONShiftRightImmediate(vd, vn, shift, NEON_USRA);
 }
 
 
-void Assembler::srsra(const VRegister& vd,
-                      const VRegister& vn,
-                      int shift) {
+void Assembler::srsra(const VRegister& vd, const VRegister& vn, int shift) {
   VIXL_ASSERT(vd.IsVector() || vd.Is1D());
   NEONShiftRightImmediate(vd, vn, shift, NEON_SRSRA);
 }
 
 
-void Assembler::ursra(const VRegister& vd,
-                      const VRegister& vn,
-                      int shift) {
+void Assembler::ursra(const VRegister& vd, const VRegister& vn, int shift) {
   VIXL_ASSERT(vd.IsVector() || vd.Is1D());
   NEONShiftRightImmediate(vd, vn, shift, NEON_URSRA);
 }
 
 
-void Assembler::shrn(const VRegister& vd,
-                     const VRegister& vn,
-                     int shift) {
+void Assembler::shrn(const VRegister& vd, const VRegister& vn, int shift) {
   VIXL_ASSERT(vn.IsVector() && vd.IsD());
   NEONShiftImmediateN(vd, vn, shift, NEON_SHRN);
 }
 
 
-void Assembler::shrn2(const VRegister& vd,
-                      const VRegister& vn,
-                      int shift) {
+void Assembler::shrn2(const VRegister& vd, const VRegister& vn, int shift) {
   VIXL_ASSERT(vn.IsVector() && vd.IsQ());
   NEONShiftImmediateN(vd, vn, shift, NEON_SHRN);
 }
 
 
-void Assembler::rshrn(const VRegister& vd,
-                      const VRegister& vn,
-                      int shift) {
+void Assembler::rshrn(const VRegister& vd, const VRegister& vn, int shift) {
   VIXL_ASSERT(vn.IsVector() && vd.IsD());
   NEONShiftImmediateN(vd, vn, shift, NEON_RSHRN);
 }
 
 
-void Assembler::rshrn2(const VRegister& vd,
-                       const VRegister& vn,
-                       int shift) {
+void Assembler::rshrn2(const VRegister& vd, const VRegister& vn, int shift) {
   VIXL_ASSERT(vn.IsVector() && vd.IsQ());
   NEONShiftImmediateN(vd, vn, shift, NEON_RSHRN);
 }
 
 
-void Assembler::sqshrn(const VRegister& vd,
-                       const VRegister& vn,
-                       int shift) {
+void Assembler::sqshrn(const VRegister& vd, const VRegister& vn, int shift) {
   VIXL_ASSERT(vd.IsD() || (vn.IsScalar() && vd.IsScalar()));
   NEONShiftImmediateN(vd, vn, shift, NEON_SQSHRN);
 }
 
 
-void Assembler::sqshrn2(const VRegister& vd,
-                        const VRegister& vn,
-                        int shift) {
+void Assembler::sqshrn2(const VRegister& vd, const VRegister& vn, int shift) {
   VIXL_ASSERT(vn.IsVector() && vd.IsQ());
   NEONShiftImmediateN(vd, vn, shift, NEON_SQSHRN);
 }
 
 
-void Assembler::sqrshrn(const VRegister& vd,
-                        const VRegister& vn,
-                        int shift) {
+void Assembler::sqrshrn(const VRegister& vd, const VRegister& vn, int shift) {
   VIXL_ASSERT(vd.IsD() || (vn.IsScalar() && vd.IsScalar()));
   NEONShiftImmediateN(vd, vn, shift, NEON_SQRSHRN);
 }
 
 
-void Assembler::sqrshrn2(const VRegister& vd,
-                         const VRegister& vn,
-                         int shift) {
+void Assembler::sqrshrn2(const VRegister& vd, const VRegister& vn, int shift) {
   VIXL_ASSERT(vn.IsVector() && vd.IsQ());
   NEONShiftImmediateN(vd, vn, shift, NEON_SQRSHRN);
 }
 
 
-void Assembler::sqshrun(const VRegister& vd,
-                        const VRegister& vn,
-                        int shift) {
+void Assembler::sqshrun(const VRegister& vd, const VRegister& vn, int shift) {
   VIXL_ASSERT(vd.IsD() || (vn.IsScalar() && vd.IsScalar()));
   NEONShiftImmediateN(vd, vn, shift, NEON_SQSHRUN);
 }
 
 
-void Assembler::sqshrun2(const VRegister& vd,
-                         const VRegister& vn,
-                         int shift) {
+void Assembler::sqshrun2(const VRegister& vd, const VRegister& vn, int shift) {
   VIXL_ASSERT(vn.IsVector() && vd.IsQ());
   NEONShiftImmediateN(vd, vn, shift, NEON_SQSHRUN);
 }
 
 
-void Assembler::sqrshrun(const VRegister& vd,
-                         const VRegister& vn,
-                         int shift) {
+void Assembler::sqrshrun(const VRegister& vd, const VRegister& vn, int shift) {
   VIXL_ASSERT(vd.IsD() || (vn.IsScalar() && vd.IsScalar()));
   NEONShiftImmediateN(vd, vn, shift, NEON_SQRSHRUN);
 }
 
 
-void Assembler::sqrshrun2(const VRegister& vd,
-                          const VRegister& vn,
-                          int shift) {
+void Assembler::sqrshrun2(const VRegister& vd, const VRegister& vn, int shift) {
   VIXL_ASSERT(vn.IsVector() && vd.IsQ());
   NEONShiftImmediateN(vd, vn, shift, NEON_SQRSHRUN);
 }
 
 
-void Assembler::uqshrn(const VRegister& vd,
-                       const VRegister& vn,
-                       int shift) {
+void Assembler::uqshrn(const VRegister& vd, const VRegister& vn, int shift) {
   VIXL_ASSERT(vd.IsD() || (vn.IsScalar() && vd.IsScalar()));
   NEONShiftImmediateN(vd, vn, shift, NEON_UQSHRN);
 }
 
 
-void Assembler::uqshrn2(const VRegister& vd,
-                        const VRegister& vn,
-                        int shift) {
+void Assembler::uqshrn2(const VRegister& vd, const VRegister& vn, int shift) {
   VIXL_ASSERT(vn.IsVector() && vd.IsQ());
   NEONShiftImmediateN(vd, vn, shift, NEON_UQSHRN);
 }
 
 
-void Assembler::uqrshrn(const VRegister& vd,
-                        const VRegister& vn,
-                        int shift) {
+void Assembler::uqrshrn(const VRegister& vd, const VRegister& vn, int shift) {
   VIXL_ASSERT(vd.IsD() || (vn.IsScalar() && vd.IsScalar()));
   NEONShiftImmediateN(vd, vn, shift, NEON_UQRSHRN);
 }
 
 
-void Assembler::uqrshrn2(const VRegister& vd,
-                         const VRegister& vn,
-                         int shift) {
+void Assembler::uqrshrn2(const VRegister& vd, const VRegister& vn, int shift) {
   VIXL_ASSERT(vn.IsVector() && vd.IsQ());
   NEONShiftImmediateN(vd, vn, shift, NEON_UQRSHRN);
 }
@@ -4531,9 +4340,7 @@
 }
 
 
-Instr Assembler::ImmFP32(float imm) {
-  return FP32ToImm8(imm) << ImmFP_offset;
-}
+Instr Assembler::ImmFP32(float imm) { return FP32ToImm8(imm) << ImmFP_offset; }
 
 
 uint32_t Assembler::FP64ToImm8(double imm) {
@@ -4552,9 +4359,7 @@
 }
 
 
-Instr Assembler::ImmFP64(double imm) {
-  return FP64ToImm8(imm) << ImmFP_offset;
-}
+Instr Assembler::ImmFP64(double imm) { return FP64ToImm8(imm) << ImmFP_offset; }
 
 
 // Code generation helpers.
@@ -4573,8 +4378,8 @@
 
   if (shift >= 0) {
     // Explicit shift specified.
-    VIXL_ASSERT((shift == 0) || (shift == 16) ||
-                (shift == 32) || (shift == 48));
+    VIXL_ASSERT((shift == 0) || (shift == 16) || (shift == 32) ||
+                (shift == 48));
     VIXL_ASSERT(rd.Is64Bits() || (shift == 0) || (shift == 16));
     shift /= 16;
   } else {
@@ -4599,8 +4404,8 @@
 
   VIXL_ASSERT(is_uint16(imm));
 
-  Emit(SF(rd) | MoveWideImmediateFixed | mov_op |
-       Rd(rd) | ImmMoveWide(imm) | ShiftMoveWide(shift));
+  Emit(SF(rd) | MoveWideImmediateFixed | mov_op | Rd(rd) | ImmMoveWide(imm) |
+       ShiftMoveWide(shift));
 }
 
 
@@ -4629,7 +4434,10 @@
     // extended register mode, and emit an add/sub extended instruction.
     if (rn.IsSP() || rd.IsSP()) {
       VIXL_ASSERT(!(rd.IsSP() && (S == SetFlags)));
-      DataProcExtendedRegister(rd, rn, operand.ToExtendedRegister(), S,
+      DataProcExtendedRegister(rd,
+                               rn,
+                               operand.ToExtendedRegister(),
+                               S,
                                AddSubExtendedFixed | op);
     } else {
       DataProcShiftedRegister(rd, rn, operand, S, AddSubShiftedFixed | op);
@@ -4665,9 +4473,7 @@
 }
 
 
-void Assembler::svc(int code) {
-  Emit(SVC | ImmException(code));
-}
+void Assembler::svc(int code) { Emit(SVC | ImmException(code)); }
 
 
 // TODO(all): The third parameter should be passed by reference but gcc 4.8.2
@@ -4732,7 +4538,7 @@
     int64_t immediate = operand.immediate();
     VIXL_ASSERT(IsImmConditionalCompare(immediate));
     ccmpop = ConditionalCompareImmediateFixed | op |
-        ImmCondCmp(static_cast<unsigned>(immediate));
+             ImmCondCmp(static_cast<unsigned>(immediate));
   } else {
     VIXL_ASSERT(operand.IsShiftedRegister() && (operand.shift_amount() == 0));
     ccmpop = ConditionalCompareRegisterFixed | op | Rm(operand.reg());
@@ -4772,10 +4578,10 @@
                                         const int imm8,
                                         const int left_shift,
                                         NEONModifiedImmediateOp op) {
-  VIXL_ASSERT(vd.Is8B() || vd.Is16B() || vd.Is4H() || vd.Is8H() ||
-              vd.Is2S() || vd.Is4S());
-  VIXL_ASSERT((left_shift == 0) || (left_shift == 8) ||
-              (left_shift == 16) || (left_shift == 24));
+  VIXL_ASSERT(vd.Is8B() || vd.Is16B() || vd.Is4H() || vd.Is8H() || vd.Is2S() ||
+              vd.Is4S());
+  VIXL_ASSERT((left_shift == 0) || (left_shift == 8) || (left_shift == 16) ||
+              (left_shift == 24));
   VIXL_ASSERT(is_uint8(imm8));
 
   int cmode_1, cmode_2, cmode_3;
@@ -4858,10 +4664,14 @@
     switch (extend) {
       case UXTB:
       case UXTH:
-      case UXTW: ubfm(rd, rn_, non_shift_bits, high_bit); break;
+      case UXTW:
+        ubfm(rd, rn_, non_shift_bits, high_bit);
+        break;
       case SXTB:
       case SXTH:
-      case SXTW: sbfm(rd, rn_, non_shift_bits, high_bit); break;
+      case SXTW:
+        sbfm(rd, rn_, non_shift_bits, high_bit);
+        break;
       case UXTX:
       case SXTX: {
         VIXL_ASSERT(rn.size() == kXRegSize);
@@ -4869,7 +4679,8 @@
         lsl(rd, rn_, left_shift);
         break;
       }
-      default: VIXL_UNREACHABLE();
+      default:
+        VIXL_UNREACHABLE();
     }
   } else {
     // No need to extend as the extended bits would be shifted away.
@@ -4884,11 +4695,11 @@
                                         FlagsUpdate S,
                                         Instr op) {
   VIXL_ASSERT(operand.IsShiftedRegister());
-  VIXL_ASSERT(rn.Is64Bits() || (rn.Is32Bits() &&
-              is_uint5(operand.shift_amount())));
-  Emit(SF(rd) | op | Flags(S) |
-       ShiftDP(operand.shift()) | ImmDPShift(operand.shift_amount()) |
-       Rm(operand.reg()) | Rn(rn) | Rd(rd));
+  VIXL_ASSERT(rn.Is64Bits() ||
+              (rn.Is32Bits() && is_uint5(operand.shift_amount())));
+  Emit(SF(rd) | op | Flags(S) | ShiftDP(operand.shift()) |
+       ImmDPShift(operand.shift_amount()) | Rm(operand.reg()) | Rn(rn) |
+       Rd(rd));
 }
 
 
@@ -4911,25 +4722,25 @@
   int64_t offset = addr.offset();
 
   if (addr.IsImmediateOffset()) {
-    bool prefer_unscaled = (option == PreferUnscaledOffset) ||
-                           (option == RequireUnscaledOffset);
+    bool prefer_unscaled =
+        (option == PreferUnscaledOffset) || (option == RequireUnscaledOffset);
     if (prefer_unscaled && IsImmLSUnscaled(offset)) {
       // Use the unscaled addressing mode.
       return base | LoadStoreUnscaledOffsetFixed |
-          ImmLS(static_cast<int>(offset));
+             ImmLS(static_cast<int>(offset));
     }
 
     if ((option != RequireUnscaledOffset) &&
         IsImmLSScaled(offset, access_size)) {
       // Use the scaled addressing mode.
       return base | LoadStoreUnsignedOffsetFixed |
-          ImmLSUnsigned(static_cast<int>(offset) >> access_size);
+             ImmLSUnsigned(static_cast<int>(offset) >> access_size);
     }
 
     if ((option != RequireScaledOffset) && IsImmLSUnscaled(offset)) {
       // Use the unscaled addressing mode.
       return base | LoadStoreUnscaledOffsetFixed |
-          ImmLS(static_cast<int>(offset));
+             ImmLS(static_cast<int>(offset));
     }
   }
 
@@ -4952,7 +4763,7 @@
     // access size.
     VIXL_ASSERT((shift_amount == 0) || (shift_amount == access_size));
     return base | LoadStoreRegisterOffsetFixed | Rm(addr.regoffset()) |
-        ExtendMode(ext) | ImmShiftLS((shift_amount > 0) ? 1 : 0);
+           ExtendMode(ext) | ImmShiftLS((shift_amount > 0) ? 1 : 0);
   }
 
   if (addr.IsPreIndex() && IsImmLSUnscaled(offset)) {
@@ -5063,9 +4874,7 @@
 }
 
 
-bool Assembler::IsImmLSUnscaled(int64_t offset) {
-  return is_int9(offset);
-}
+bool Assembler::IsImmLSUnscaled(int64_t offset) { return is_int9(offset); }
 
 
 // The movn instruction can generate immediates containing an arbitrary 16-bit
@@ -5227,12 +5036,12 @@
   // (1 + 2^d + 2^(2d) + ...), i.e. 0x0001000100010001 or similar. These can
   // be derived using a table lookup on CLZ(d).
   static const uint64_t multipliers[] = {
-    0x0000000000000001UL,
-    0x0000000100000001UL,
-    0x0001000100010001UL,
-    0x0101010101010101UL,
-    0x1111111111111111UL,
-    0x5555555555555555UL,
+      0x0000000000000001UL,
+      0x0000000100000001UL,
+      0x0001000100010001UL,
+      0x0101010101010101UL,
+      0x1111111111111111UL,
+      0x5555555555555555UL,
   };
   uint64_t multiplier = multipliers[CountLeadingZeros(d, kXRegSize) - 57];
   uint64_t candidate = (b - a) * multiplier;
@@ -5296,10 +5105,14 @@
   } else {
     VIXL_ASSERT(rt.IsVRegister());
     switch (rt.SizeInBits()) {
-      case kBRegSize: return LDR_b;
-      case kHRegSize: return LDR_h;
-      case kSRegSize: return LDR_s;
-      case kDRegSize: return LDR_d;
+      case kBRegSize:
+        return LDR_b;
+      case kHRegSize:
+        return LDR_h;
+      case kSRegSize:
+        return LDR_s;
+      case kDRegSize:
+        return LDR_d;
       default:
         VIXL_ASSERT(rt.IsQ());
         return LDR_q;
@@ -5315,10 +5128,14 @@
   } else {
     VIXL_ASSERT(rt.IsVRegister());
     switch (rt.SizeInBits()) {
-      case kBRegSize: return STR_b;
-      case kHRegSize: return STR_h;
-      case kSRegSize: return STR_s;
-      case kDRegSize: return STR_d;
+      case kBRegSize:
+        return STR_b;
+      case kHRegSize:
+        return STR_h;
+      case kSRegSize:
+        return STR_s;
+      case kDRegSize:
+        return STR_d;
       default:
         VIXL_ASSERT(rt.IsQ());
         return STR_q;
@@ -5328,7 +5145,7 @@
 
 
 LoadStorePairOp Assembler::StorePairOpFor(const CPURegister& rt,
-    const CPURegister& rt2) {
+                                          const CPURegister& rt2) {
   VIXL_ASSERT(AreSameSizeAndType(rt, rt2));
   USE(rt2);
   if (rt.IsRegister()) {
@@ -5336,8 +5153,10 @@
   } else {
     VIXL_ASSERT(rt.IsVRegister());
     switch (rt.SizeInBytes()) {
-      case kSRegSizeInBytes: return STP_s;
-      case kDRegSizeInBytes: return STP_d;
+      case kSRegSizeInBytes:
+        return STP_s;
+      case kDRegSizeInBytes:
+        return STP_d;
       default:
         VIXL_ASSERT(rt.IsQ());
         return STP_q;
@@ -5363,8 +5182,10 @@
   } else {
     VIXL_ASSERT(rt.IsVRegister());
     switch (rt.SizeInBytes()) {
-      case kSRegSizeInBytes: return STNP_s;
-      case kDRegSizeInBytes: return STNP_d;
+      case kSRegSizeInBytes:
+        return STNP_s;
+      case kDRegSizeInBytes:
+        return STNP_d;
       default:
         VIXL_ASSERT(rt.IsQ());
         return STNP_q;
@@ -5387,8 +5208,10 @@
   } else {
     VIXL_ASSERT(rt.IsVRegister());
     switch (rt.SizeInBytes()) {
-      case kSRegSizeInBytes: return LDR_s_lit;
-      case kDRegSizeInBytes: return LDR_d_lit;
+      case kSRegSizeInBytes:
+        return LDR_s_lit;
+      case kDRegSizeInBytes:
+        return LDR_d_lit;
       default:
         VIXL_ASSERT(rt.IsQ());
         return LDR_q_lit;
@@ -5397,10 +5220,14 @@
 }
 
 
-bool AreAliased(const CPURegister& reg1, const CPURegister& reg2,
-                const CPURegister& reg3, const CPURegister& reg4,
-                const CPURegister& reg5, const CPURegister& reg6,
-                const CPURegister& reg7, const CPURegister& reg8) {
+bool AreAliased(const CPURegister& reg1,
+                const CPURegister& reg2,
+                const CPURegister& reg3,
+                const CPURegister& reg4,
+                const CPURegister& reg5,
+                const CPURegister& reg6,
+                const CPURegister& reg7,
+                const CPURegister& reg8) {
   int number_of_valid_regs = 0;
   int number_of_valid_fpregs = 0;
 
@@ -5432,10 +5259,14 @@
 }
 
 
-bool AreSameSizeAndType(const CPURegister& reg1, const CPURegister& reg2,
-                        const CPURegister& reg3, const CPURegister& reg4,
-                        const CPURegister& reg5, const CPURegister& reg6,
-                        const CPURegister& reg7, const CPURegister& reg8) {
+bool AreSameSizeAndType(const CPURegister& reg1,
+                        const CPURegister& reg2,
+                        const CPURegister& reg3,
+                        const CPURegister& reg4,
+                        const CPURegister& reg5,
+                        const CPURegister& reg6,
+                        const CPURegister& reg7,
+                        const CPURegister& reg8) {
   VIXL_ASSERT(reg1.IsValid());
   bool match = true;
   match &= !reg2.IsValid() || reg2.IsSameSizeAndType(reg1);
@@ -5449,8 +5280,10 @@
 }
 
 
-bool AreSameFormat(const VRegister& reg1, const VRegister& reg2,
-                   const VRegister& reg3, const VRegister& reg4) {
+bool AreSameFormat(const VRegister& reg1,
+                   const VRegister& reg2,
+                   const VRegister& reg3,
+                   const VRegister& reg4) {
   VIXL_ASSERT(reg1.IsValid());
   bool match = true;
   match &= !reg2.IsValid() || reg2.IsSameFormat(reg1);
@@ -5460,8 +5293,10 @@
 }
 
 
-bool AreConsecutive(const VRegister& reg1, const VRegister& reg2,
-                    const VRegister& reg3, const VRegister& reg4) {
+bool AreConsecutive(const VRegister& reg1,
+                    const VRegister& reg2,
+                    const VRegister& reg3,
+                    const VRegister& reg4) {
   VIXL_ASSERT(reg1.IsValid());
   bool match = true;
   match &= !reg2.IsValid() ||
diff --git a/src/vixl/a64/assembler-a64.h b/src/vixl/a64/assembler-a64.h
index fda5ccc..10d0f14 100644
--- a/src/vixl/a64/assembler-a64.h
+++ b/src/vixl/a64/assembler-a64.h
@@ -139,16 +139,14 @@
   }
 
   bool IsValidRegister() const {
-    return IsRegister() &&
-           ((size_ == kWRegSize) || (size_ == kXRegSize)) &&
+    return IsRegister() && ((size_ == kWRegSize) || (size_ == kXRegSize)) &&
            ((code_ < kNumberOfRegisters) || (code_ == kSPRegInternalCode));
   }
 
   bool IsValidVRegister() const {
-    return IsVRegister() &&
-           ((size_ == kBRegSize) || (size_ == kHRegSize) ||
-            (size_ == kSRegSize) || (size_ == kDRegSize) ||
-            (size_ == kQRegSize)) &&
+    return IsVRegister() && ((size_ == kBRegSize) || (size_ == kHRegSize) ||
+                             (size_ == kSRegSize) || (size_ == kDRegSize) ||
+                             (size_ == kQRegSize)) &&
            (code_ < kNumberOfVRegisters);
   }
 
@@ -184,17 +182,11 @@
     return IsRegister() && (code_ == kSPRegInternalCode);
   }
 
-  bool IsRegister() const {
-    return type_ == kRegister;
-  }
+  bool IsRegister() const { return type_ == kRegister; }
 
-  bool IsVRegister() const {
-    return type_ == kVRegister;
-  }
+  bool IsVRegister() const { return type_ == kVRegister; }
 
-  bool IsFPRegister() const {
-    return IsS() || IsD();
-  }
+  bool IsFPRegister() const { return IsS() || IsD(); }
 
   bool IsW() const { return IsValidRegister() && Is32Bits(); }
   bool IsX() const { return IsValidRegister() && Is64Bits(); }
@@ -231,9 +223,7 @@
   RegisterType type_;
 
  private:
-  bool IsValidOrNone() const {
-    return IsValid() || IsNone();
-  }
+  bool IsValidOrNone() const { return IsValid() || IsNone(); }
 };
 
 
@@ -244,8 +234,7 @@
       : CPURegister(other.code(), other.size(), other.type()) {
     VIXL_ASSERT(IsValidRegister());
   }
-  Register(unsigned code, unsigned size)
-      : CPURegister(code, size, kRegister) {}
+  Register(unsigned code, unsigned size) : CPURegister(code, size, kRegister) {}
 
   bool IsValid() const {
     VIXL_ASSERT(IsRegister() || IsNone());
@@ -330,29 +319,19 @@
   bool IsLaneSizeS() const { return LaneSizeInBits() == kSRegSize; }
   bool IsLaneSizeD() const { return LaneSizeInBits() == kDRegSize; }
 
-  int lanes() const {
-    return lanes_;
-  }
+  int lanes() const { return lanes_; }
 
-  bool IsScalar() const {
-    return lanes_ == 1;
-  }
+  bool IsScalar() const { return lanes_ == 1; }
 
-  bool IsVector() const {
-    return lanes_ > 1;
-  }
+  bool IsVector() const { return lanes_ > 1; }
 
   bool IsSameFormat(const VRegister& other) const {
     return (size_ == other.size_) && (lanes_ == other.lanes_);
   }
 
-  unsigned LaneSizeInBytes() const {
-    return SizeInBytes() / lanes_;
-  }
+  unsigned LaneSizeInBytes() const { return SizeInBytes() / lanes_; }
 
-  unsigned LaneSizeInBits() const {
-    return LaneSizeInBytes() * 8;
-  }
+  unsigned LaneSizeInBits() const { return LaneSizeInBytes() * 8; }
 
  private:
   static const VRegister bregisters[];
@@ -377,22 +356,22 @@
 const CPURegister NoCPUReg;
 
 
-#define DEFINE_REGISTERS(N)  \
-const Register w##N(N, kWRegSize);  \
-const Register x##N(N, kXRegSize);
+#define DEFINE_REGISTERS(N)          \
+  const Register w##N(N, kWRegSize); \
+  const Register x##N(N, kXRegSize);
 REGISTER_CODE_LIST(DEFINE_REGISTERS)
 #undef DEFINE_REGISTERS
 const Register wsp(kSPRegInternalCode, kWRegSize);
 const Register sp(kSPRegInternalCode, kXRegSize);
 
 
-#define DEFINE_VREGISTERS(N)  \
-const VRegister b##N(N, kBRegSize);  \
-const VRegister h##N(N, kHRegSize);  \
-const VRegister s##N(N, kSRegSize);  \
-const VRegister d##N(N, kDRegSize);  \
-const VRegister q##N(N, kQRegSize);  \
-const VRegister v##N(N, kQRegSize);
+#define DEFINE_VREGISTERS(N)          \
+  const VRegister b##N(N, kBRegSize); \
+  const VRegister h##N(N, kHRegSize); \
+  const VRegister s##N(N, kSRegSize); \
+  const VRegister d##N(N, kDRegSize); \
+  const VRegister q##N(N, kQRegSize); \
+  const VRegister v##N(N, kQRegSize);
 REGISTER_CODE_LIST(DEFINE_VREGISTERS)
 #undef DEFINE_VREGISTERS
 
@@ -458,7 +437,8 @@
                       CPURegister reg3 = NoCPUReg,
                       CPURegister reg4 = NoCPUReg)
       : list_(reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit()),
-        size_(reg1.size()), type_(reg1.type()) {
+        size_(reg1.size()),
+        type_(reg1.type()) {
     VIXL_ASSERT(AreSameSizeAndType(reg1, reg2, reg3, reg4));
     VIXL_ASSERT(IsValid());
   }
@@ -468,13 +448,15 @@
     VIXL_ASSERT(IsValid());
   }
 
-  CPURegList(CPURegister::RegisterType type, unsigned size,
-             unsigned first_reg, unsigned last_reg)
+  CPURegList(CPURegister::RegisterType type,
+             unsigned size,
+             unsigned first_reg,
+             unsigned last_reg)
       : size_(size), type_(type) {
-    VIXL_ASSERT(((type == CPURegister::kRegister) &&
-                 (last_reg < kNumberOfRegisters)) ||
-                ((type == CPURegister::kVRegister) &&
-                 (last_reg < kNumberOfVRegisters)));
+    VIXL_ASSERT(
+        ((type == CPURegister::kRegister) && (last_reg < kNumberOfRegisters)) ||
+        ((type == CPURegister::kVRegister) &&
+         (last_reg < kNumberOfVRegisters)));
     VIXL_ASSERT(last_reg >= first_reg);
     list_ = (UINT64_C(1) << (last_reg + 1)) - 1;
     list_ &= ~((UINT64_C(1) << first_reg) - 1);
@@ -653,7 +635,7 @@
   // where <immediate> is int64_t.
   // This is allowed to be an implicit constructor because Operand is
   // a wrapper class that doesn't normally perform any type conversion.
-  Operand(int64_t immediate = 0);           // NOLINT(runtime/explicit)
+  Operand(int64_t immediate = 0);  // NOLINT(runtime/explicit)
 
   // rm, {<shift> #<shift_amount>}
   // where <shift> is one of {LSL, LSR, ASR, ROR}.
@@ -662,7 +644,7 @@
   // a wrapper class that doesn't normally perform any type conversion.
   Operand(Register reg,
           Shift shift = LSL,
-          unsigned shift_amount = 0);   // NOLINT(runtime/explicit)
+          unsigned shift_amount = 0);  // NOLINT(runtime/explicit)
 
   // rm, {<extend> {#<shift_amount>}}
   // where <extend> is one of {UXTB, UXTH, UXTW, UXTX, SXTB, SXTH, SXTW, SXTX}.
@@ -670,6 +652,7 @@
   explicit Operand(Register reg, Extend extend, unsigned shift_amount = 0);
 
   bool IsImmediate() const;
+  bool IsPlainRegister() const;
   bool IsShiftedRegister() const;
   bool IsExtendedRegister() const;
   bool IsZero() const;
@@ -683,6 +666,8 @@
     return immediate_;
   }
 
+  int64_t GetEquivalentImmediate() const { return IsZero() ? 0 : immediate(); }
+
   Register reg() const {
     VIXL_ASSERT(IsShiftedRegister() || IsExtendedRegister());
     return reg_;
@@ -726,9 +711,7 @@
              Register regoffset,
              Extend extend,
              unsigned shift_amount = 0);
-  MemOperand(Register base,
-             const Operand& offset,
-             AddrMode addrmode = Offset);
+  MemOperand(Register base, const Operand& offset, AddrMode addrmode = Offset);
 
   const Register& base() const { return base_; }
   const Register& regoffset() const { return regoffset_; }
@@ -796,6 +779,10 @@
    public:
     explicit LabelLinksIterator(Label* label)
         : LabelLinksIteratorBase(&label->links_) {}
+
+    // TODO: Remove these and use the STL-like interface instead.
+    using LabelLinksIteratorBase::Advance;
+    using LabelLinksIteratorBase::Current;
   };
 
   void Bind(ptrdiff_t location) {
@@ -811,13 +798,9 @@
     links_.insert(instruction);
   }
 
-  void DeleteLink(ptrdiff_t instruction) {
-    links_.erase(instruction);
-  }
+  void DeleteLink(ptrdiff_t instruction) { links_.erase(instruction); }
 
-  void ClearAllLinks() {
-    links_.clear();
-  }
+  void ClearAllLinks() { links_.clear(); }
 
   // TODO: The comment below considers average case complexity for our
   // usual use-cases. The elements of interest are:
@@ -851,10 +834,15 @@
 
   static const ptrdiff_t kLocationUnbound = -1;
 
-  // It is not safe to copy labels, so disable the copy constructor and operator
-  // by declaring them private (without an implementation).
+// It is not safe to copy labels, so disable the copy constructor and operator
+// by declaring them private (without an implementation).
+#if __cplusplus >= 201103L
+  Label(const Label&) = delete;
+  void operator=(const Label&) = delete;
+#else
   Label(const Label&);
   void operator=(const Label&);
+#endif
 
   // The Assembler class is responsible for binding and linking labels, since
   // the stored offsets need to be consistent with the Assembler's buffer.
@@ -867,21 +855,17 @@
 
 
 // Required InvalSet template specialisations.
-#define INVAL_SET_TEMPLATE_PARAMETERS \
-    ptrdiff_t,                        \
-    Label::kNPreallocatedLinks,       \
-    ptrdiff_t,                        \
-    Label::kInvalidLinkKey,           \
-    Label::kReclaimFrom,              \
-    Label::kReclaimFactor
-template<>
-inline ptrdiff_t InvalSet<INVAL_SET_TEMPLATE_PARAMETERS>::Key(
+#define INVAL_SET_TEMPLATE_PARAMETERS                                       \
+  ptrdiff_t, Label::kNPreallocatedLinks, ptrdiff_t, Label::kInvalidLinkKey, \
+      Label::kReclaimFrom, Label::kReclaimFactor
+template <>
+inline ptrdiff_t InvalSet<INVAL_SET_TEMPLATE_PARAMETERS>::GetKey(
     const ptrdiff_t& element) {
   return element;
 }
-template<>
-inline void InvalSet<INVAL_SET_TEMPLATE_PARAMETERS>::SetKey(
-              ptrdiff_t* element, ptrdiff_t key) {
+template <>
+inline void InvalSet<INVAL_SET_TEMPLATE_PARAMETERS>::SetKey(ptrdiff_t* element,
+                                                            ptrdiff_t key) {
   *element = key;
 }
 #undef INVAL_SET_TEMPLATE_PARAMETERS
@@ -924,8 +908,7 @@
   size_t size() {
     VIXL_STATIC_ASSERT(kDRegSizeInBytes == kXRegSizeInBytes);
     VIXL_STATIC_ASSERT(kSRegSizeInBytes == kWRegSizeInBytes);
-    VIXL_ASSERT((size_ == kXRegSizeInBytes) ||
-                (size_ == kWRegSizeInBytes) ||
+    VIXL_ASSERT((size_ == kXRegSizeInBytes) || (size_ == kWRegSizeInBytes) ||
                 (size_ == kQRegSizeInBytes));
     return size_;
   }
@@ -951,9 +934,7 @@
   bool IsUsed() { return offset_ < 0; }
   bool IsPlaced() { return offset_ > 0; }
 
-  LiteralPool* GetLiteralPool() const {
-    return literal_pool_;
-  }
+  LiteralPool* GetLiteralPool() const { return literal_pool_; }
 
   ptrdiff_t offset() {
     VIXL_ASSERT(IsPlaced());
@@ -1003,7 +984,8 @@
     UpdateValue(value);
   }
 
-  Literal(T high64, T low64,
+  Literal(T high64,
+          T low64,
           LiteralPool* literal_pool = NULL,
           RawLiteral::DeletionPolicy ownership = kManuallyDeleted)
       : RawLiteral(kQRegSizeInBytes, literal_pool, ownership) {
@@ -1017,7 +999,7 @@
   // the pool.
   // If the literal has already been placed in a literal pool, the address of
   // the start of the code buffer must be provided, as the literal only knows it
-  // offset from there.  This also allows patching the value after the code has
+  // offset from there. This also allows patching the value after the code has
   // been moved in memory.
   void UpdateValue(T new_value, uint8_t* code_buffer = NULL) {
     VIXL_ASSERT(sizeof(new_value) == size_);
@@ -1106,7 +1088,8 @@
  public:
   Assembler(size_t capacity,
             PositionIndependentCodeOption pic = PositionIndependentCode);
-  Assembler(byte* buffer, size_t capacity,
+  Assembler(byte* buffer,
+            size_t capacity,
             PositionIndependentCodeOption pic = PositionIndependentCode);
 
   // The destructor asserts that one of the following is true:
@@ -1135,9 +1118,7 @@
   // Place a literal at the current PC.
   void place(RawLiteral* literal);
 
-  ptrdiff_t CursorOffset() const {
-    return buffer_->CursorOffset();
-  }
+  ptrdiff_t CursorOffset() const { return buffer_->CursorOffset(); }
 
   ptrdiff_t BufferEndOffset() const {
     return static_cast<ptrdiff_t>(buffer_->capacity());
@@ -1152,7 +1133,7 @@
 
   // Return the address of a bound label.
   template <typename T>
-  T GetLabelAddress(const Label * label) const {
+  T GetLabelAddress(const Label* label) const {
     VIXL_ASSERT(label->IsBound());
     VIXL_STATIC_ASSERT(sizeof(T) >= sizeof(uintptr_t));
     return GetOffsetAddress<T>(label->location());
@@ -1227,9 +1208,7 @@
   void cbnz(const Register& rt, int imm19);
 
   // Table lookup from one register.
-  void tbl(const VRegister& vd,
-           const VRegister& vn,
-           const VRegister& vm);
+  void tbl(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Table lookup from two registers.
   void tbl(const VRegister& vd,
@@ -1253,9 +1232,7 @@
            const VRegister& vm);
 
   // Table lookup extension from one register.
-  void tbx(const VRegister& vd,
-           const VRegister& vn,
-           const VRegister& vm);
+  void tbx(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Table lookup extension from two registers.
   void tbx(const VRegister& vd,
@@ -1295,103 +1272,75 @@
   // unscaled (i.e. the result can be unaligned).
 
   // Calculate the address of a label.
-  void adr(const Register& rd, Label* label);
+  void adr(const Register& xd, Label* label);
 
   // Calculate the address of a PC offset.
-  void adr(const Register& rd, int imm21);
+  void adr(const Register& xd, int imm21);
 
   // Calculate the page address of a label.
-  void adrp(const Register& rd, Label* label);
+  void adrp(const Register& xd, Label* label);
 
   // Calculate the page address of a PC offset.
-  void adrp(const Register& rd, int imm21);
+  void adrp(const Register& xd, int imm21);
 
   // Data Processing instructions.
   // Add.
-  void add(const Register& rd,
-           const Register& rn,
-           const Operand& operand);
+  void add(const Register& rd, const Register& rn, const Operand& operand);
 
   // Add and update status flags.
-  void adds(const Register& rd,
-            const Register& rn,
-            const Operand& operand);
+  void adds(const Register& rd, const Register& rn, const Operand& operand);
 
   // Compare negative.
   void cmn(const Register& rn, const Operand& operand);
 
   // Subtract.
-  void sub(const Register& rd,
-           const Register& rn,
-           const Operand& operand);
+  void sub(const Register& rd, const Register& rn, const Operand& operand);
 
   // Subtract and update status flags.
-  void subs(const Register& rd,
-            const Register& rn,
-            const Operand& operand);
+  void subs(const Register& rd, const Register& rn, const Operand& operand);
 
   // Compare.
   void cmp(const Register& rn, const Operand& operand);
 
   // Negate.
-  void neg(const Register& rd,
-           const Operand& operand);
+  void neg(const Register& rd, const Operand& operand);
 
   // Negate and update status flags.
-  void negs(const Register& rd,
-            const Operand& operand);
+  void negs(const Register& rd, const Operand& operand);
 
   // Add with carry bit.
-  void adc(const Register& rd,
-           const Register& rn,
-           const Operand& operand);
+  void adc(const Register& rd, const Register& rn, const Operand& operand);
 
   // Add with carry bit and update status flags.
-  void adcs(const Register& rd,
-            const Register& rn,
-            const Operand& operand);
+  void adcs(const Register& rd, const Register& rn, const Operand& operand);
 
   // Subtract with carry bit.
-  void sbc(const Register& rd,
-           const Register& rn,
-           const Operand& operand);
+  void sbc(const Register& rd, const Register& rn, const Operand& operand);
 
   // Subtract with carry bit and update status flags.
-  void sbcs(const Register& rd,
-            const Register& rn,
-            const Operand& operand);
+  void sbcs(const Register& rd, const Register& rn, const Operand& operand);
 
   // Negate with carry bit.
-  void ngc(const Register& rd,
-           const Operand& operand);
+  void ngc(const Register& rd, const Operand& operand);
 
   // Negate with carry bit and update status flags.
-  void ngcs(const Register& rd,
-            const Operand& operand);
+  void ngcs(const Register& rd, const Operand& operand);
 
   // Logical instructions.
   // Bitwise and (A & B).
-  void and_(const Register& rd,
-            const Register& rn,
-            const Operand& operand);
+  void and_(const Register& rd, const Register& rn, const Operand& operand);
 
   // Bitwise and (A & B) and update status flags.
-  void ands(const Register& rd,
-            const Register& rn,
-            const Operand& operand);
+  void ands(const Register& rd, const Register& rn, const Operand& operand);
 
   // Bit test and set flags.
   void tst(const Register& rn, const Operand& operand);
 
   // Bit clear (A & ~B).
-  void bic(const Register& rd,
-           const Register& rn,
-           const Operand& operand);
+  void bic(const Register& rd, const Register& rn, const Operand& operand);
 
   // Bit clear (A & ~B) and update status flags.
-  void bics(const Register& rd,
-            const Register& rn,
-            const Operand& operand);
+  void bics(const Register& rd, const Register& rn, const Operand& operand);
 
   // Bitwise or (A | B).
   void orr(const Register& rd, const Register& rn, const Operand& operand);
@@ -1485,19 +1434,13 @@
   }
 
   // Signed extend byte.
-  void sxtb(const Register& rd, const Register& rn) {
-    sbfm(rd, rn, 0, 7);
-  }
+  void sxtb(const Register& rd, const Register& rn) { sbfm(rd, rn, 0, 7); }
 
   // Signed extend halfword.
-  void sxth(const Register& rd, const Register& rn) {
-    sbfm(rd, rn, 0, 15);
-  }
+  void sxth(const Register& rd, const Register& rn) { sbfm(rd, rn, 0, 15); }
 
   // Signed extend word.
-  void sxtw(const Register& rd, const Register& rn) {
-    sbfm(rd, rn, 0, 31);
-  }
+  void sxtw(const Register& rd, const Register& rn) { sbfm(rd, rn, 0, 31); }
 
   // Ubfm aliases.
   // Logical shift left.
@@ -1534,19 +1477,13 @@
   }
 
   // Unsigned extend byte.
-  void uxtb(const Register& rd, const Register& rn) {
-    ubfm(rd, rn, 0, 7);
-  }
+  void uxtb(const Register& rd, const Register& rn) { ubfm(rd, rn, 0, 7); }
 
   // Unsigned extend halfword.
-  void uxth(const Register& rd, const Register& rn) {
-    ubfm(rd, rn, 0, 15);
-  }
+  void uxth(const Register& rd, const Register& rn) { ubfm(rd, rn, 0, 15); }
 
   // Unsigned extend word.
-  void uxtw(const Register& rd, const Register& rn) {
-    ubfm(rd, rn, 0, 31);
-  }
+  void uxtw(const Register& rd, const Register& rn) { ubfm(rd, rn, 0, 31); }
 
   // Extract.
   void extr(const Register& rd,
@@ -1612,44 +1549,28 @@
             Condition cond);
 
   // CRC-32 checksum from byte.
-  void crc32b(const Register& rd,
-              const Register& rn,
-              const Register& rm);
+  void crc32b(const Register& wd, const Register& wn, const Register& wm);
 
   // CRC-32 checksum from half-word.
-  void crc32h(const Register& rd,
-              const Register& rn,
-              const Register& rm);
+  void crc32h(const Register& wd, const Register& wn, const Register& wm);
 
   // CRC-32 checksum from word.
-  void crc32w(const Register& rd,
-              const Register& rn,
-              const Register& rm);
+  void crc32w(const Register& wd, const Register& wn, const Register& wm);
 
   // CRC-32 checksum from double word.
-  void crc32x(const Register& rd,
-              const Register& rn,
-              const Register& rm);
+  void crc32x(const Register& wd, const Register& wn, const Register& xm);
 
   // CRC-32 C checksum from byte.
-  void crc32cb(const Register& rd,
-               const Register& rn,
-               const Register& rm);
+  void crc32cb(const Register& wd, const Register& wn, const Register& wm);
 
   // CRC-32 C checksum from half-word.
-  void crc32ch(const Register& rd,
-               const Register& rn,
-               const Register& rm);
+  void crc32ch(const Register& wd, const Register& wn, const Register& wm);
 
   // CRC-32 C checksum from word.
-  void crc32cw(const Register& rd,
-               const Register& rn,
-               const Register& rm);
+  void crc32cw(const Register& wd, const Register& wn, const Register& wm);
 
   // CRC-32C checksum from double word.
-  void crc32cx(const Register& rd,
-               const Register& rn,
-               const Register& rm);
+  void crc32cx(const Register& wd, const Register& wn, const Register& xm);
 
   // Multiply.
   void mul(const Register& rd, const Register& rn, const Register& rm);
@@ -1658,7 +1579,7 @@
   void mneg(const Register& rd, const Register& rn, const Register& rm);
 
   // Signed long multiply: 32 x 32 -> 64-bit.
-  void smull(const Register& rd, const Register& rn, const Register& rm);
+  void smull(const Register& xd, const Register& wn, const Register& wm);
 
   // Signed multiply high: 64 x 64 -> 64-bit <127:64>.
   void smulh(const Register& xd, const Register& xn, const Register& xm);
@@ -1676,40 +1597,36 @@
             const Register& ra);
 
   // Signed long multiply and accumulate: 32 x 32 + 64 -> 64-bit.
-  void smaddl(const Register& rd,
-              const Register& rn,
-              const Register& rm,
-              const Register& ra);
+  void smaddl(const Register& xd,
+              const Register& wn,
+              const Register& wm,
+              const Register& xa);
 
   // Unsigned long multiply and accumulate: 32 x 32 + 64 -> 64-bit.
-  void umaddl(const Register& rd,
-              const Register& rn,
-              const Register& rm,
-              const Register& ra);
+  void umaddl(const Register& xd,
+              const Register& wn,
+              const Register& wm,
+              const Register& xa);
 
   // Unsigned long multiply: 32 x 32 -> 64-bit.
-  void umull(const Register& rd,
-             const Register& rn,
-             const Register& rm) {
-    umaddl(rd, rn, rm, xzr);
+  void umull(const Register& xd, const Register& wn, const Register& wm) {
+    umaddl(xd, wn, wm, xzr);
   }
 
   // Unsigned multiply high: 64 x 64 -> 64-bit <127:64>.
-  void umulh(const Register& xd,
-             const Register& xn,
-             const Register& xm);
+  void umulh(const Register& xd, const Register& xn, const Register& xm);
 
   // Signed long multiply and subtract: 64 - (32 x 32) -> 64-bit.
-  void smsubl(const Register& rd,
-              const Register& rn,
-              const Register& rm,
-              const Register& ra);
+  void smsubl(const Register& xd,
+              const Register& wn,
+              const Register& wm,
+              const Register& xa);
 
   // Unsigned long multiply and subtract: 64 - (32 x 32) -> 64-bit.
-  void umsubl(const Register& rd,
-              const Register& rn,
-              const Register& rm,
-              const Register& ra);
+  void umsubl(const Register& xd,
+              const Register& wn,
+              const Register& wm,
+              const Register& xa);
 
   // Signed integer divide.
   void sdiv(const Register& rd, const Register& rn, const Register& rm);
@@ -1724,7 +1641,7 @@
   void rev16(const Register& rd, const Register& rn);
 
   // Reverse bytes in 32-bit words.
-  void rev32(const Register& rd, const Register& rn);
+  void rev32(const Register& xd, const Register& xn);
 
   // Reverse bytes.
   void rev(const Register& rd, const Register& rn);
@@ -1737,107 +1654,129 @@
 
   // Memory instructions.
   // Load integer or FP register.
-  void ldr(const CPURegister& rt, const MemOperand& src,
+  void ldr(const CPURegister& rt,
+           const MemOperand& src,
            LoadStoreScalingOption option = PreferScaledOffset);
 
   // Store integer or FP register.
-  void str(const CPURegister& rt, const MemOperand& dst,
+  void str(const CPURegister& rt,
+           const MemOperand& dst,
            LoadStoreScalingOption option = PreferScaledOffset);
 
   // Load word with sign extension.
-  void ldrsw(const Register& rt, const MemOperand& src,
+  void ldrsw(const Register& xt,
+             const MemOperand& src,
              LoadStoreScalingOption option = PreferScaledOffset);
 
   // Load byte.
-  void ldrb(const Register& rt, const MemOperand& src,
+  void ldrb(const Register& rt,
+            const MemOperand& src,
             LoadStoreScalingOption option = PreferScaledOffset);
 
   // Store byte.
-  void strb(const Register& rt, const MemOperand& dst,
+  void strb(const Register& rt,
+            const MemOperand& dst,
             LoadStoreScalingOption option = PreferScaledOffset);
 
   // Load byte with sign extension.
-  void ldrsb(const Register& rt, const MemOperand& src,
+  void ldrsb(const Register& rt,
+             const MemOperand& src,
              LoadStoreScalingOption option = PreferScaledOffset);
 
   // Load half-word.
-  void ldrh(const Register& rt, const MemOperand& src,
+  void ldrh(const Register& rt,
+            const MemOperand& src,
             LoadStoreScalingOption option = PreferScaledOffset);
 
   // Store half-word.
-  void strh(const Register& rt, const MemOperand& dst,
+  void strh(const Register& rt,
+            const MemOperand& dst,
             LoadStoreScalingOption option = PreferScaledOffset);
 
   // Load half-word with sign extension.
-  void ldrsh(const Register& rt, const MemOperand& src,
+  void ldrsh(const Register& rt,
+             const MemOperand& src,
              LoadStoreScalingOption option = PreferScaledOffset);
 
   // Load integer or FP register (with unscaled offset).
-  void ldur(const CPURegister& rt, const MemOperand& src,
+  void ldur(const CPURegister& rt,
+            const MemOperand& src,
             LoadStoreScalingOption option = PreferUnscaledOffset);
 
   // Store integer or FP register (with unscaled offset).
-  void stur(const CPURegister& rt, const MemOperand& src,
+  void stur(const CPURegister& rt,
+            const MemOperand& src,
             LoadStoreScalingOption option = PreferUnscaledOffset);
 
   // Load word with sign extension.
-  void ldursw(const Register& rt, const MemOperand& src,
+  void ldursw(const Register& xt,
+              const MemOperand& src,
               LoadStoreScalingOption option = PreferUnscaledOffset);
 
   // Load byte (with unscaled offset).
-  void ldurb(const Register& rt, const MemOperand& src,
+  void ldurb(const Register& rt,
+             const MemOperand& src,
              LoadStoreScalingOption option = PreferUnscaledOffset);
 
   // Store byte (with unscaled offset).
-  void sturb(const Register& rt, const MemOperand& dst,
+  void sturb(const Register& rt,
+             const MemOperand& dst,
              LoadStoreScalingOption option = PreferUnscaledOffset);
 
   // Load byte with sign extension (and unscaled offset).
-  void ldursb(const Register& rt, const MemOperand& src,
+  void ldursb(const Register& rt,
+              const MemOperand& src,
               LoadStoreScalingOption option = PreferUnscaledOffset);
 
   // Load half-word (with unscaled offset).
-  void ldurh(const Register& rt, const MemOperand& src,
+  void ldurh(const Register& rt,
+             const MemOperand& src,
              LoadStoreScalingOption option = PreferUnscaledOffset);
 
   // Store half-word (with unscaled offset).
-  void sturh(const Register& rt, const MemOperand& dst,
+  void sturh(const Register& rt,
+             const MemOperand& dst,
              LoadStoreScalingOption option = PreferUnscaledOffset);
 
   // Load half-word with sign extension (and unscaled offset).
-  void ldursh(const Register& rt, const MemOperand& src,
+  void ldursh(const Register& rt,
+              const MemOperand& src,
               LoadStoreScalingOption option = PreferUnscaledOffset);
 
   // Load integer or FP register pair.
-  void ldp(const CPURegister& rt, const CPURegister& rt2,
+  void ldp(const CPURegister& rt,
+           const CPURegister& rt2,
            const MemOperand& src);
 
   // Store integer or FP register pair.
-  void stp(const CPURegister& rt, const CPURegister& rt2,
+  void stp(const CPURegister& rt,
+           const CPURegister& rt2,
            const MemOperand& dst);
 
   // Load word pair with sign extension.
-  void ldpsw(const Register& rt, const Register& rt2, const MemOperand& src);
+  void ldpsw(const Register& xt, const Register& xt2, const MemOperand& src);
 
   // Load integer or FP register pair, non-temporal.
-  void ldnp(const CPURegister& rt, const CPURegister& rt2,
+  void ldnp(const CPURegister& rt,
+            const CPURegister& rt2,
             const MemOperand& src);
 
   // Store integer or FP register pair, non-temporal.
-  void stnp(const CPURegister& rt, const CPURegister& rt2,
+  void stnp(const CPURegister& rt,
+            const CPURegister& rt2,
             const MemOperand& dst);
 
   // Load integer or FP register from literal pool.
   void ldr(const CPURegister& rt, RawLiteral* literal);
 
   // Load word with sign extension from literal pool.
-  void ldrsw(const Register& rt, RawLiteral* literal);
+  void ldrsw(const Register& xt, RawLiteral* literal);
 
   // Load integer or FP register from pc + imm19 << 2.
   void ldr(const CPURegister& rt, int imm19);
 
   // Load word with sign extension from pc + imm19 << 2.
-  void ldrsw(const Register& rt, int imm19);
+  void ldrsw(const Register& xt, int imm19);
 
   // Store exclusive byte.
   void stxrb(const Register& rs, const Register& rt, const MemOperand& dst);
@@ -1912,11 +1851,13 @@
   void ldar(const Register& rt, const MemOperand& src);
 
   // Prefetch memory.
-  void prfm(PrefetchOperation op, const MemOperand& addr,
+  void prfm(PrefetchOperation op,
+            const MemOperand& addr,
             LoadStoreScalingOption option = PreferScaledOffset);
 
   // Prefetch memory (with unscaled offset).
-  void prfum(PrefetchOperation op, const MemOperand& addr,
+  void prfum(PrefetchOperation op,
+             const MemOperand& addr,
              LoadStoreScalingOption option = PreferUnscaledOffset);
 
   // Prefetch memory in the literal pool.
@@ -1968,16 +1909,16 @@
 
   // System instructions.
   // Move to register from system register.
-  void mrs(const Register& rt, SystemRegister sysreg);
+  void mrs(const Register& xt, SystemRegister sysreg);
 
   // Move from register to system register.
-  void msr(SystemRegister sysreg, const Register& rt);
+  void msr(SystemRegister sysreg, const Register& xt);
 
   // System instruction.
-  void sys(int op1, int crn, int crm, int op2, const Register& rt = xzr);
+  void sys(int op1, int crn, int crm, int op2, const Register& xt = xzr);
 
   // System instruction with pre-encoded op (op1:crn:crm:op2).
-  void sys(int op, const Register& rt = xzr);
+  void sys(int op, const Register& xt = xzr);
 
   // System data cache operation.
   void dc(DataCacheOp op, const Register& rt);
@@ -2002,9 +1943,7 @@
 
   // Alias for system instructions.
   // No-op.
-  void nop() {
-    hint(NOP);
-  }
+  void nop() { hint(NOP); }
 
   // FP and NEON instructions.
   // Move double precision immediate to FP register.
@@ -2062,13 +2001,10 @@
               const VRegister& va);
 
   // FP multiply-negate scalar.
-  void fnmul(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void fnmul(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // FP reciprocal exponent scalar.
-  void frecpx(const VRegister& vd,
-              const VRegister& vn);
+  void frecpx(const VRegister& vd, const VRegister& vn);
 
   // FP divide.
   void fdiv(const VRegister& vd, const VRegister& fn, const VRegister& vm);
@@ -2115,9 +2051,7 @@
   // FP round to integer, towards zero.
   void frintz(const VRegister& vd, const VRegister& vn);
 
-  void FPCompareMacro(const VRegister& vn,
-                      double value,
-                      FPTrapFlags trap);
+  void FPCompareMacro(const VRegister& vn, double value, FPTrapFlags trap);
 
   void FPCompareMacro(const VRegister& vn,
                       const VRegister& vm,
@@ -2160,12 +2094,8 @@
              Condition cond);
 
   // Common FP Convert functions.
-  void NEONFPConvertToInt(const Register& rd,
-                          const VRegister& vn,
-                          Instr op);
-  void NEONFPConvertToInt(const VRegister& vd,
-                          const VRegister& vn,
-                          Instr op);
+  void NEONFPConvertToInt(const Register& rd, const VRegister& vn, Instr op);
+  void NEONFPConvertToInt(const VRegister& vd, const VRegister& vn, Instr op);
 
   // FP convert between precisions.
   void fcvt(const VRegister& vd, const VRegister& vn);
@@ -2261,108 +2191,67 @@
   void ucvtf(const VRegister& fd, const VRegister& vn, int fbits = 0);
 
   // Unsigned absolute difference.
-  void uabd(const VRegister& vd,
-            const VRegister& vn,
-            const VRegister& vm);
+  void uabd(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed absolute difference.
-  void sabd(const VRegister& vd,
-            const VRegister& vn,
-            const VRegister& vm);
+  void sabd(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Unsigned absolute difference and accumulate.
-  void uaba(const VRegister& vd,
-            const VRegister& vn,
-            const VRegister& vm);
+  void uaba(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed absolute difference and accumulate.
-  void saba(const VRegister& vd,
-            const VRegister& vn,
-            const VRegister& vm);
+  void saba(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Add.
-  void add(const VRegister& vd,
-           const VRegister& vn,
-           const VRegister& vm);
+  void add(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Subtract.
-  void sub(const VRegister& vd,
-           const VRegister& vn,
-           const VRegister& vm);
+  void sub(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Unsigned halving add.
-  void uhadd(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void uhadd(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed halving add.
-  void shadd(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void shadd(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Unsigned rounding halving add.
-  void urhadd(const VRegister& vd,
-              const VRegister& vn,
-              const VRegister& vm);
+  void urhadd(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed rounding halving add.
-  void srhadd(const VRegister& vd,
-              const VRegister& vn,
-              const VRegister& vm);
+  void srhadd(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Unsigned halving sub.
-  void uhsub(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void uhsub(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed halving sub.
-  void shsub(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void shsub(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Unsigned saturating add.
-  void uqadd(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void uqadd(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed saturating add.
-  void sqadd(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void sqadd(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Unsigned saturating subtract.
-  void uqsub(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void uqsub(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed saturating subtract.
-  void sqsub(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void sqsub(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Add pairwise.
-  void addp(const VRegister& vd,
-            const VRegister& vn,
-            const VRegister& vm);
+  void addp(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Add pair of elements scalar.
-  void addp(const VRegister& vd,
-            const VRegister& vn);
+  void addp(const VRegister& vd, const VRegister& vn);
 
   // Multiply-add to accumulator.
-  void mla(const VRegister& vd,
-           const VRegister& vn,
-           const VRegister& vm);
+  void mla(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Multiply-subtract to accumulator.
-  void mls(const VRegister& vd,
-           const VRegister& vn,
-           const VRegister& vm);
+  void mls(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Multiply.
-  void mul(const VRegister& vd,
-           const VRegister& vn,
-           const VRegister& vm);
+  void mul(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Multiply by scalar element.
   void mul(const VRegister& vd,
@@ -2491,158 +2380,97 @@
                 int vm_index);
 
   // Compare equal.
-  void cmeq(const VRegister& vd,
-            const VRegister& vn,
-            const VRegister& vm);
+  void cmeq(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Compare signed greater than or equal.
-  void cmge(const VRegister& vd,
-            const VRegister& vn,
-            const VRegister& vm);
+  void cmge(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Compare signed greater than.
-  void cmgt(const VRegister& vd,
-            const VRegister& vn,
-            const VRegister& vm);
+  void cmgt(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Compare unsigned higher.
-  void cmhi(const VRegister& vd,
-            const VRegister& vn,
-            const VRegister& vm);
+  void cmhi(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Compare unsigned higher or same.
-  void cmhs(const VRegister& vd,
-            const VRegister& vn,
-            const VRegister& vm);
+  void cmhs(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Compare bitwise test bits nonzero.
-  void cmtst(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void cmtst(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Compare bitwise to zero.
-  void cmeq(const VRegister& vd,
-            const VRegister& vn,
-            int value);
+  void cmeq(const VRegister& vd, const VRegister& vn, int value);
 
   // Compare signed greater than or equal to zero.
-  void cmge(const VRegister& vd,
-            const VRegister& vn,
-            int value);
+  void cmge(const VRegister& vd, const VRegister& vn, int value);
 
   // Compare signed greater than zero.
-  void cmgt(const VRegister& vd,
-            const VRegister& vn,
-            int value);
+  void cmgt(const VRegister& vd, const VRegister& vn, int value);
 
   // Compare signed less than or equal to zero.
-  void cmle(const VRegister& vd,
-            const VRegister& vn,
-            int value);
+  void cmle(const VRegister& vd, const VRegister& vn, int value);
 
   // Compare signed less than zero.
-  void cmlt(const VRegister& vd,
-            const VRegister& vn,
-            int value);
+  void cmlt(const VRegister& vd, const VRegister& vn, int value);
 
   // Signed shift left by register.
-  void sshl(const VRegister& vd,
-            const VRegister& vn,
-            const VRegister& vm);
+  void sshl(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Unsigned shift left by register.
-  void ushl(const VRegister& vd,
-            const VRegister& vn,
-            const VRegister& vm);
+  void ushl(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed saturating shift left by register.
-  void sqshl(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void sqshl(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Unsigned saturating shift left by register.
-  void uqshl(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void uqshl(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed rounding shift left by register.
-  void srshl(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void srshl(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Unsigned rounding shift left by register.
-  void urshl(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void urshl(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed saturating rounding shift left by register.
-  void sqrshl(const VRegister& vd,
-              const VRegister& vn,
-              const VRegister& vm);
+  void sqrshl(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Unsigned saturating rounding shift left by register.
-  void uqrshl(const VRegister& vd,
-              const VRegister& vn,
-              const VRegister& vm);
+  void uqrshl(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Bitwise and.
-  void and_(const VRegister& vd,
-            const VRegister& vn,
-            const VRegister& vm);
+  void and_(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Bitwise or.
-  void orr(const VRegister& vd,
-           const VRegister& vn,
-           const VRegister& vm);
+  void orr(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Bitwise or immediate.
-  void orr(const VRegister& vd,
-           const int imm8,
-           const int left_shift = 0);
+  void orr(const VRegister& vd, const int imm8, const int left_shift = 0);
 
   // Move register to register.
-  void mov(const VRegister& vd,
-           const VRegister& vn);
+  void mov(const VRegister& vd, const VRegister& vn);
 
   // Bitwise orn.
-  void orn(const VRegister& vd,
-           const VRegister& vn,
-           const VRegister& vm);
+  void orn(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Bitwise eor.
-  void eor(const VRegister& vd,
-           const VRegister& vn,
-           const VRegister& vm);
+  void eor(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Bit clear immediate.
-  void bic(const VRegister& vd,
-           const int imm8,
-           const int left_shift = 0);
+  void bic(const VRegister& vd, const int imm8, const int left_shift = 0);
 
   // Bit clear.
-  void bic(const VRegister& vd,
-           const VRegister& vn,
-           const VRegister& vm);
+  void bic(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Bitwise insert if false.
-  void bif(const VRegister& vd,
-           const VRegister& vn,
-           const VRegister& vm);
+  void bif(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Bitwise insert if true.
-  void bit(const VRegister& vd,
-           const VRegister& vn,
-           const VRegister& vm);
+  void bit(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Bitwise select.
-  void bsl(const VRegister& vd,
-           const VRegister& vn,
-           const VRegister& vm);
+  void bsl(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Polynomial multiply.
-  void pmul(const VRegister& vd,
-            const VRegister& vn,
-            const VRegister& vm);
+  void pmul(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Vector move immediate.
   void movi(const VRegister& vd,
@@ -2651,8 +2479,7 @@
             const int shift_amount = 0);
 
   // Bitwise not.
-  void mvn(const VRegister& vd,
-           const VRegister& vn);
+  void mvn(const VRegister& vd, const VRegister& vn);
 
   // Vector move inverted immediate.
   void mvni(const VRegister& vd,
@@ -2661,64 +2488,49 @@
             const int shift_amount = 0);
 
   // Signed saturating accumulate of unsigned value.
-  void suqadd(const VRegister& vd,
-              const VRegister& vn);
+  void suqadd(const VRegister& vd, const VRegister& vn);
 
   // Unsigned saturating accumulate of signed value.
-  void usqadd(const VRegister& vd,
-              const VRegister& vn);
+  void usqadd(const VRegister& vd, const VRegister& vn);
 
   // Absolute value.
-  void abs(const VRegister& vd,
-           const VRegister& vn);
+  void abs(const VRegister& vd, const VRegister& vn);
 
   // Signed saturating absolute value.
-  void sqabs(const VRegister& vd,
-             const VRegister& vn);
+  void sqabs(const VRegister& vd, const VRegister& vn);
 
   // Negate.
-  void neg(const VRegister& vd,
-           const VRegister& vn);
+  void neg(const VRegister& vd, const VRegister& vn);
 
   // Signed saturating negate.
-  void sqneg(const VRegister& vd,
-             const VRegister& vn);
+  void sqneg(const VRegister& vd, const VRegister& vn);
 
   // Bitwise not.
-  void not_(const VRegister& vd,
-            const VRegister& vn);
+  void not_(const VRegister& vd, const VRegister& vn);
 
   // Extract narrow.
-  void xtn(const VRegister& vd,
-           const VRegister& vn);
+  void xtn(const VRegister& vd, const VRegister& vn);
 
   // Extract narrow (second part).
-  void xtn2(const VRegister& vd,
-            const VRegister& vn);
+  void xtn2(const VRegister& vd, const VRegister& vn);
 
   // Signed saturating extract narrow.
-  void sqxtn(const VRegister& vd,
-             const VRegister& vn);
+  void sqxtn(const VRegister& vd, const VRegister& vn);
 
   // Signed saturating extract narrow (second part).
-  void sqxtn2(const VRegister& vd,
-              const VRegister& vn);
+  void sqxtn2(const VRegister& vd, const VRegister& vn);
 
   // Unsigned saturating extract narrow.
-  void uqxtn(const VRegister& vd,
-             const VRegister& vn);
+  void uqxtn(const VRegister& vd, const VRegister& vn);
 
   // Unsigned saturating extract narrow (second part).
-  void uqxtn2(const VRegister& vd,
-              const VRegister& vn);
+  void uqxtn2(const VRegister& vd, const VRegister& vn);
 
   // Signed saturating extract unsigned narrow.
-  void sqxtun(const VRegister& vd,
-              const VRegister& vn);
+  void sqxtun(const VRegister& vd, const VRegister& vn);
 
   // Signed saturating extract unsigned narrow (second part).
-  void sqxtun2(const VRegister& vd,
-               const VRegister& vn);
+  void sqxtun2(const VRegister& vd, const VRegister& vn);
 
   // Extract vector from pair of vectors.
   void ext(const VRegister& vd,
@@ -2727,18 +2539,13 @@
            int index);
 
   // Duplicate vector element to vector or scalar.
-  void dup(const VRegister& vd,
-           const VRegister& vn,
-           int vn_index);
+  void dup(const VRegister& vd, const VRegister& vn, int vn_index);
 
   // Move vector element to scalar.
-  void mov(const VRegister& vd,
-           const VRegister& vn,
-           int vn_index);
+  void mov(const VRegister& vd, const VRegister& vn, int vn_index);
 
   // Duplicate general-purpose register to vector.
-  void dup(const VRegister& vd,
-           const Register& rn);
+  void dup(const VRegister& vd, const Register& rn);
 
   // Insert vector element from another vector element.
   void ins(const VRegister& vd,
@@ -2753,38 +2560,25 @@
            int vn_index);
 
   // Insert vector element from general-purpose register.
-  void ins(const VRegister& vd,
-           int vd_index,
-           const Register& rn);
+  void ins(const VRegister& vd, int vd_index, const Register& rn);
 
   // Move general-purpose register to a vector element.
-  void mov(const VRegister& vd,
-           int vd_index,
-           const Register& rn);
+  void mov(const VRegister& vd, int vd_index, const Register& rn);
 
   // Unsigned move vector element to general-purpose register.
-  void umov(const Register& rd,
-            const VRegister& vn,
-            int vn_index);
+  void umov(const Register& rd, const VRegister& vn, int vn_index);
 
   // Move vector element to general-purpose register.
-  void mov(const Register& rd,
-           const VRegister& vn,
-           int vn_index);
+  void mov(const Register& rd, const VRegister& vn, int vn_index);
 
   // Signed move vector element to general-purpose register.
-  void smov(const Register& rd,
-            const VRegister& vn,
-            int vn_index);
+  void smov(const Register& rd, const VRegister& vn, int vn_index);
 
   // One-element structure load to one register.
-  void ld1(const VRegister& vt,
-           const MemOperand& src);
+  void ld1(const VRegister& vt, const MemOperand& src);
 
   // One-element structure load to two registers.
-  void ld1(const VRegister& vt,
-           const VRegister& vt2,
-           const MemOperand& src);
+  void ld1(const VRegister& vt, const VRegister& vt2, const MemOperand& src);
 
   // One-element structure load to three registers.
   void ld1(const VRegister& vt,
@@ -2800,18 +2594,13 @@
            const MemOperand& src);
 
   // One-element single structure load to one lane.
-  void ld1(const VRegister& vt,
-           int lane,
-           const MemOperand& src);
+  void ld1(const VRegister& vt, int lane, const MemOperand& src);
 
   // One-element single structure load to all lanes.
-  void ld1r(const VRegister& vt,
-            const MemOperand& src);
+  void ld1r(const VRegister& vt, const MemOperand& src);
 
   // Two-element structure load.
-  void ld2(const VRegister& vt,
-           const VRegister& vt2,
-           const MemOperand& src);
+  void ld2(const VRegister& vt, const VRegister& vt2, const MemOperand& src);
 
   // Two-element single structure load to one lane.
   void ld2(const VRegister& vt,
@@ -2820,9 +2609,7 @@
            const MemOperand& src);
 
   // Two-element single structure load to all lanes.
-  void ld2r(const VRegister& vt,
-            const VRegister& vt2,
-            const MemOperand& src);
+  void ld2r(const VRegister& vt, const VRegister& vt2, const MemOperand& src);
 
   // Three-element structure load.
   void ld3(const VRegister& vt,
@@ -2866,197 +2653,136 @@
             const MemOperand& src);
 
   // Count leading sign bits.
-  void cls(const VRegister& vd,
-           const VRegister& vn);
+  void cls(const VRegister& vd, const VRegister& vn);
 
   // Count leading zero bits (vector).
-  void clz(const VRegister& vd,
-           const VRegister& vn);
+  void clz(const VRegister& vd, const VRegister& vn);
 
   // Population count per byte.
-  void cnt(const VRegister& vd,
-           const VRegister& vn);
+  void cnt(const VRegister& vd, const VRegister& vn);
 
   // Reverse bit order.
-  void rbit(const VRegister& vd,
-            const VRegister& vn);
+  void rbit(const VRegister& vd, const VRegister& vn);
 
   // Reverse elements in 16-bit halfwords.
-  void rev16(const VRegister& vd,
-             const VRegister& vn);
+  void rev16(const VRegister& vd, const VRegister& vn);
 
   // Reverse elements in 32-bit words.
-  void rev32(const VRegister& vd,
-             const VRegister& vn);
+  void rev32(const VRegister& vd, const VRegister& vn);
 
   // Reverse elements in 64-bit doublewords.
-  void rev64(const VRegister& vd,
-             const VRegister& vn);
+  void rev64(const VRegister& vd, const VRegister& vn);
 
   // Unsigned reciprocal square root estimate.
-  void ursqrte(const VRegister& vd,
-               const VRegister& vn);
+  void ursqrte(const VRegister& vd, const VRegister& vn);
 
   // Unsigned reciprocal estimate.
-  void urecpe(const VRegister& vd,
-              const VRegister& vn);
+  void urecpe(const VRegister& vd, const VRegister& vn);
 
   // Signed pairwise long add.
-  void saddlp(const VRegister& vd,
-              const VRegister& vn);
+  void saddlp(const VRegister& vd, const VRegister& vn);
 
   // Unsigned pairwise long add.
-  void uaddlp(const VRegister& vd,
-              const VRegister& vn);
+  void uaddlp(const VRegister& vd, const VRegister& vn);
 
   // Signed pairwise long add and accumulate.
-  void sadalp(const VRegister& vd,
-              const VRegister& vn);
+  void sadalp(const VRegister& vd, const VRegister& vn);
 
   // Unsigned pairwise long add and accumulate.
-  void uadalp(const VRegister& vd,
-              const VRegister& vn);
+  void uadalp(const VRegister& vd, const VRegister& vn);
 
   // Shift left by immediate.
-  void shl(const VRegister& vd,
-           const VRegister& vn,
-           int shift);
+  void shl(const VRegister& vd, const VRegister& vn, int shift);
 
   // Signed saturating shift left by immediate.
-  void sqshl(const VRegister& vd,
-             const VRegister& vn,
-             int shift);
+  void sqshl(const VRegister& vd, const VRegister& vn, int shift);
 
   // Signed saturating shift left unsigned by immediate.
-  void sqshlu(const VRegister& vd,
-              const VRegister& vn,
-              int shift);
+  void sqshlu(const VRegister& vd, const VRegister& vn, int shift);
 
   // Unsigned saturating shift left by immediate.
-  void uqshl(const VRegister& vd,
-             const VRegister& vn,
-             int shift);
+  void uqshl(const VRegister& vd, const VRegister& vn, int shift);
 
   // Signed shift left long by immediate.
-  void sshll(const VRegister& vd,
-             const VRegister& vn,
-             int shift);
+  void sshll(const VRegister& vd, const VRegister& vn, int shift);
 
   // Signed shift left long by immediate (second part).
-  void sshll2(const VRegister& vd,
-              const VRegister& vn,
-              int shift);
+  void sshll2(const VRegister& vd, const VRegister& vn, int shift);
 
   // Signed extend long.
-  void sxtl(const VRegister& vd,
-            const VRegister& vn);
+  void sxtl(const VRegister& vd, const VRegister& vn);
 
   // Signed extend long (second part).
-  void sxtl2(const VRegister& vd,
-             const VRegister& vn);
+  void sxtl2(const VRegister& vd, const VRegister& vn);
 
   // Unsigned shift left long by immediate.
-  void ushll(const VRegister& vd,
-             const VRegister& vn,
-             int shift);
+  void ushll(const VRegister& vd, const VRegister& vn, int shift);
 
   // Unsigned shift left long by immediate (second part).
-  void ushll2(const VRegister& vd,
-              const VRegister& vn,
-              int shift);
+  void ushll2(const VRegister& vd, const VRegister& vn, int shift);
 
   // Shift left long by element size.
-  void shll(const VRegister& vd,
-            const VRegister& vn,
-            int shift);
+  void shll(const VRegister& vd, const VRegister& vn, int shift);
 
   // Shift left long by element size (second part).
-  void shll2(const VRegister& vd,
-             const VRegister& vn,
-             int shift);
+  void shll2(const VRegister& vd, const VRegister& vn, int shift);
 
   // Unsigned extend long.
-  void uxtl(const VRegister& vd,
-            const VRegister& vn);
+  void uxtl(const VRegister& vd, const VRegister& vn);
 
   // Unsigned extend long (second part).
-  void uxtl2(const VRegister& vd,
-             const VRegister& vn);
+  void uxtl2(const VRegister& vd, const VRegister& vn);
 
   // Shift left by immediate and insert.
-  void sli(const VRegister& vd,
-           const VRegister& vn,
-           int shift);
+  void sli(const VRegister& vd, const VRegister& vn, int shift);
 
   // Shift right by immediate and insert.
-  void sri(const VRegister& vd,
-           const VRegister& vn,
-           int shift);
+  void sri(const VRegister& vd, const VRegister& vn, int shift);
 
   // Signed maximum.
-  void smax(const VRegister& vd,
-            const VRegister& vn,
-            const VRegister& vm);
+  void smax(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed pairwise maximum.
-  void smaxp(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void smaxp(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Add across vector.
-  void addv(const VRegister& vd,
-            const VRegister& vn);
+  void addv(const VRegister& vd, const VRegister& vn);
 
   // Signed add long across vector.
-  void saddlv(const VRegister& vd,
-              const VRegister& vn);
+  void saddlv(const VRegister& vd, const VRegister& vn);
 
   // Unsigned add long across vector.
-  void uaddlv(const VRegister& vd,
-              const VRegister& vn);
+  void uaddlv(const VRegister& vd, const VRegister& vn);
 
   // FP maximum number across vector.
-  void fmaxnmv(const VRegister& vd,
-               const VRegister& vn);
+  void fmaxnmv(const VRegister& vd, const VRegister& vn);
 
   // FP maximum across vector.
-  void fmaxv(const VRegister& vd,
-             const VRegister& vn);
+  void fmaxv(const VRegister& vd, const VRegister& vn);
 
   // FP minimum number across vector.
-  void fminnmv(const VRegister& vd,
-               const VRegister& vn);
+  void fminnmv(const VRegister& vd, const VRegister& vn);
 
   // FP minimum across vector.
-  void fminv(const VRegister& vd,
-             const VRegister& vn);
+  void fminv(const VRegister& vd, const VRegister& vn);
 
   // Signed maximum across vector.
-  void smaxv(const VRegister& vd,
-             const VRegister& vn);
+  void smaxv(const VRegister& vd, const VRegister& vn);
 
   // Signed minimum.
-  void smin(const VRegister& vd,
-            const VRegister& vn,
-            const VRegister& vm);
+  void smin(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed minimum pairwise.
-  void sminp(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void sminp(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed minimum across vector.
-  void sminv(const VRegister& vd,
-             const VRegister& vn);
+  void sminv(const VRegister& vd, const VRegister& vn);
 
   // One-element structure store from one register.
-  void st1(const VRegister& vt,
-           const MemOperand& src);
+  void st1(const VRegister& vt, const MemOperand& src);
 
   // One-element structure store from two registers.
-  void st1(const VRegister& vt,
-           const VRegister& vt2,
-           const MemOperand& src);
+  void st1(const VRegister& vt, const VRegister& vt2, const MemOperand& src);
 
   // One-element structure store from three registers.
   void st1(const VRegister& vt,
@@ -3072,14 +2798,10 @@
            const MemOperand& src);
 
   // One-element single structure store from one lane.
-  void st1(const VRegister& vt,
-           int lane,
-           const MemOperand& src);
+  void st1(const VRegister& vt, int lane, const MemOperand& src);
 
   // Two-element structure store from two registers.
-  void st2(const VRegister& vt,
-           const VRegister& vt2,
-           const MemOperand& src);
+  void st2(const VRegister& vt, const VRegister& vt2, const MemOperand& src);
 
   // Two-element single structure store from two lanes.
   void st2(const VRegister& vt,
@@ -3116,420 +2838,256 @@
            const MemOperand& src);
 
   // Unsigned add long.
-  void uaddl(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void uaddl(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Unsigned add long (second part).
-  void uaddl2(const VRegister& vd,
-              const VRegister& vn,
-              const VRegister& vm);
+  void uaddl2(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Unsigned add wide.
-  void uaddw(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void uaddw(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Unsigned add wide (second part).
-  void uaddw2(const VRegister& vd,
-              const VRegister& vn,
-              const VRegister& vm);
+  void uaddw2(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed add long.
-  void saddl(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void saddl(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed add long (second part).
-  void saddl2(const VRegister& vd,
-              const VRegister& vn,
-              const VRegister& vm);
+  void saddl2(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed add wide.
-  void saddw(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void saddw(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed add wide (second part).
-  void saddw2(const VRegister& vd,
-              const VRegister& vn,
-              const VRegister& vm);
+  void saddw2(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Unsigned subtract long.
-  void usubl(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void usubl(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Unsigned subtract long (second part).
-  void usubl2(const VRegister& vd,
-              const VRegister& vn,
-              const VRegister& vm);
+  void usubl2(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Unsigned subtract wide.
-  void usubw(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void usubw(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Unsigned subtract wide (second part).
-  void usubw2(const VRegister& vd,
-              const VRegister& vn,
-              const VRegister& vm);
+  void usubw2(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed subtract long.
-  void ssubl(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void ssubl(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed subtract long (second part).
-  void ssubl2(const VRegister& vd,
-              const VRegister& vn,
-              const VRegister& vm);
+  void ssubl2(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed integer subtract wide.
-  void ssubw(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void ssubw(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed integer subtract wide (second part).
-  void ssubw2(const VRegister& vd,
-              const VRegister& vn,
-              const VRegister& vm);
+  void ssubw2(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Unsigned maximum.
-  void umax(const VRegister& vd,
-            const VRegister& vn,
-            const VRegister& vm);
+  void umax(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Unsigned pairwise maximum.
-  void umaxp(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void umaxp(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Unsigned maximum across vector.
-  void umaxv(const VRegister& vd,
-             const VRegister& vn);
+  void umaxv(const VRegister& vd, const VRegister& vn);
 
   // Unsigned minimum.
-  void umin(const VRegister& vd,
-            const VRegister& vn,
-            const VRegister& vm);
+  void umin(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Unsigned pairwise minimum.
-  void uminp(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void uminp(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Unsigned minimum across vector.
-  void uminv(const VRegister& vd,
-             const VRegister& vn);
+  void uminv(const VRegister& vd, const VRegister& vn);
 
   // Transpose vectors (primary).
-  void trn1(const VRegister& vd,
-            const VRegister& vn,
-            const VRegister& vm);
+  void trn1(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Transpose vectors (secondary).
-  void trn2(const VRegister& vd,
-            const VRegister& vn,
-            const VRegister& vm);
+  void trn2(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Unzip vectors (primary).
-  void uzp1(const VRegister& vd,
-            const VRegister& vn,
-            const VRegister& vm);
+  void uzp1(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Unzip vectors (secondary).
-  void uzp2(const VRegister& vd,
-            const VRegister& vn,
-            const VRegister& vm);
+  void uzp2(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Zip vectors (primary).
-  void zip1(const VRegister& vd,
-            const VRegister& vn,
-            const VRegister& vm);
+  void zip1(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Zip vectors (secondary).
-  void zip2(const VRegister& vd,
-            const VRegister& vn,
-            const VRegister& vm);
+  void zip2(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed shift right by immediate.
-  void sshr(const VRegister& vd,
-            const VRegister& vn,
-            int shift);
+  void sshr(const VRegister& vd, const VRegister& vn, int shift);
 
   // Unsigned shift right by immediate.
-  void ushr(const VRegister& vd,
-            const VRegister& vn,
-            int shift);
+  void ushr(const VRegister& vd, const VRegister& vn, int shift);
 
   // Signed rounding shift right by immediate.
-  void srshr(const VRegister& vd,
-             const VRegister& vn,
-             int shift);
+  void srshr(const VRegister& vd, const VRegister& vn, int shift);
 
   // Unsigned rounding shift right by immediate.
-  void urshr(const VRegister& vd,
-             const VRegister& vn,
-             int shift);
+  void urshr(const VRegister& vd, const VRegister& vn, int shift);
 
   // Signed shift right by immediate and accumulate.
-  void ssra(const VRegister& vd,
-            const VRegister& vn,
-            int shift);
+  void ssra(const VRegister& vd, const VRegister& vn, int shift);
 
   // Unsigned shift right by immediate and accumulate.
-  void usra(const VRegister& vd,
-            const VRegister& vn,
-            int shift);
+  void usra(const VRegister& vd, const VRegister& vn, int shift);
 
   // Signed rounding shift right by immediate and accumulate.
-  void srsra(const VRegister& vd,
-             const VRegister& vn,
-             int shift);
+  void srsra(const VRegister& vd, const VRegister& vn, int shift);
 
   // Unsigned rounding shift right by immediate and accumulate.
-  void ursra(const VRegister& vd,
-             const VRegister& vn,
-             int shift);
+  void ursra(const VRegister& vd, const VRegister& vn, int shift);
 
   // Shift right narrow by immediate.
-  void shrn(const VRegister& vd,
-            const VRegister& vn,
-            int shift);
+  void shrn(const VRegister& vd, const VRegister& vn, int shift);
 
   // Shift right narrow by immediate (second part).
-  void shrn2(const VRegister& vd,
-             const VRegister& vn,
-             int shift);
+  void shrn2(const VRegister& vd, const VRegister& vn, int shift);
 
   // Rounding shift right narrow by immediate.
-  void rshrn(const VRegister& vd,
-             const VRegister& vn,
-             int shift);
+  void rshrn(const VRegister& vd, const VRegister& vn, int shift);
 
   // Rounding shift right narrow by immediate (second part).
-  void rshrn2(const VRegister& vd,
-              const VRegister& vn,
-              int shift);
+  void rshrn2(const VRegister& vd, const VRegister& vn, int shift);
 
   // Unsigned saturating shift right narrow by immediate.
-  void uqshrn(const VRegister& vd,
-              const VRegister& vn,
-              int shift);
+  void uqshrn(const VRegister& vd, const VRegister& vn, int shift);
 
   // Unsigned saturating shift right narrow by immediate (second part).
-  void uqshrn2(const VRegister& vd,
-               const VRegister& vn,
-               int shift);
+  void uqshrn2(const VRegister& vd, const VRegister& vn, int shift);
 
   // Unsigned saturating rounding shift right narrow by immediate.
-  void uqrshrn(const VRegister& vd,
-               const VRegister& vn,
-               int shift);
+  void uqrshrn(const VRegister& vd, const VRegister& vn, int shift);
 
   // Unsigned saturating rounding shift right narrow by immediate (second part).
-  void uqrshrn2(const VRegister& vd,
-                const VRegister& vn,
-                int shift);
+  void uqrshrn2(const VRegister& vd, const VRegister& vn, int shift);
 
   // Signed saturating shift right narrow by immediate.
-  void sqshrn(const VRegister& vd,
-              const VRegister& vn,
-              int shift);
+  void sqshrn(const VRegister& vd, const VRegister& vn, int shift);
 
   // Signed saturating shift right narrow by immediate (second part).
-  void sqshrn2(const VRegister& vd,
-               const VRegister& vn,
-               int shift);
+  void sqshrn2(const VRegister& vd, const VRegister& vn, int shift);
 
   // Signed saturating rounded shift right narrow by immediate.
-  void sqrshrn(const VRegister& vd,
-               const VRegister& vn,
-               int shift);
+  void sqrshrn(const VRegister& vd, const VRegister& vn, int shift);
 
   // Signed saturating rounded shift right narrow by immediate (second part).
-  void sqrshrn2(const VRegister& vd,
-                const VRegister& vn,
-                int shift);
+  void sqrshrn2(const VRegister& vd, const VRegister& vn, int shift);
 
   // Signed saturating shift right unsigned narrow by immediate.
-  void sqshrun(const VRegister& vd,
-               const VRegister& vn,
-               int shift);
+  void sqshrun(const VRegister& vd, const VRegister& vn, int shift);
 
   // Signed saturating shift right unsigned narrow by immediate (second part).
-  void sqshrun2(const VRegister& vd,
-                const VRegister& vn,
-                int shift);
+  void sqshrun2(const VRegister& vd, const VRegister& vn, int shift);
 
   // Signed sat rounded shift right unsigned narrow by immediate.
-  void sqrshrun(const VRegister& vd,
-                const VRegister& vn,
-                int shift);
+  void sqrshrun(const VRegister& vd, const VRegister& vn, int shift);
 
   // Signed sat rounded shift right unsigned narrow by immediate (second part).
-  void sqrshrun2(const VRegister& vd,
-                 const VRegister& vn,
-                 int shift);
+  void sqrshrun2(const VRegister& vd, const VRegister& vn, int shift);
 
   // FP reciprocal step.
-  void frecps(const VRegister& vd,
-              const VRegister& vn,
-              const VRegister& vm);
+  void frecps(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // FP reciprocal estimate.
-  void frecpe(const VRegister& vd,
-              const VRegister& vn);
+  void frecpe(const VRegister& vd, const VRegister& vn);
 
   // FP reciprocal square root estimate.
-  void frsqrte(const VRegister& vd,
-               const VRegister& vn);
+  void frsqrte(const VRegister& vd, const VRegister& vn);
 
   // FP reciprocal square root step.
-  void frsqrts(const VRegister& vd,
-               const VRegister& vn,
-               const VRegister& vm);
+  void frsqrts(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed absolute difference and accumulate long.
-  void sabal(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void sabal(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed absolute difference and accumulate long (second part).
-  void sabal2(const VRegister& vd,
-              const VRegister& vn,
-              const VRegister& vm);
+  void sabal2(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Unsigned absolute difference and accumulate long.
-  void uabal(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void uabal(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Unsigned absolute difference and accumulate long (second part).
-  void uabal2(const VRegister& vd,
-              const VRegister& vn,
-              const VRegister& vm);
+  void uabal2(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed absolute difference long.
-  void sabdl(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void sabdl(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed absolute difference long (second part).
-  void sabdl2(const VRegister& vd,
-              const VRegister& vn,
-              const VRegister& vm);
+  void sabdl2(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Unsigned absolute difference long.
-  void uabdl(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void uabdl(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Unsigned absolute difference long (second part).
-  void uabdl2(const VRegister& vd,
-              const VRegister& vn,
-              const VRegister& vm);
+  void uabdl2(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Polynomial multiply long.
-  void pmull(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void pmull(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Polynomial multiply long (second part).
-  void pmull2(const VRegister& vd,
-              const VRegister& vn,
-              const VRegister& vm);
+  void pmull2(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed long multiply-add.
-  void smlal(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void smlal(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed long multiply-add (second part).
-  void smlal2(const VRegister& vd,
-              const VRegister& vn,
-              const VRegister& vm);
+  void smlal2(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Unsigned long multiply-add.
-  void umlal(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void umlal(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Unsigned long multiply-add (second part).
-  void umlal2(const VRegister& vd,
-              const VRegister& vn,
-              const VRegister& vm);
+  void umlal2(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed long multiply-sub.
-  void smlsl(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void smlsl(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed long multiply-sub (second part).
-  void smlsl2(const VRegister& vd,
-              const VRegister& vn,
-              const VRegister& vm);
+  void smlsl2(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Unsigned long multiply-sub.
-  void umlsl(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void umlsl(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Unsigned long multiply-sub (second part).
-  void umlsl2(const VRegister& vd,
-              const VRegister& vn,
-              const VRegister& vm);
+  void umlsl2(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed long multiply.
-  void smull(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void smull(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed long multiply (second part).
-  void smull2(const VRegister& vd,
-              const VRegister& vn,
-              const VRegister& vm);
+  void smull2(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed saturating doubling long multiply-add.
-  void sqdmlal(const VRegister& vd,
-               const VRegister& vn,
-               const VRegister& vm);
+  void sqdmlal(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed saturating doubling long multiply-add (second part).
-  void sqdmlal2(const VRegister& vd,
-                const VRegister& vn,
-                const VRegister& vm);
+  void sqdmlal2(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed saturating doubling long multiply-subtract.
-  void sqdmlsl(const VRegister& vd,
-               const VRegister& vn,
-               const VRegister& vm);
+  void sqdmlsl(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed saturating doubling long multiply-subtract (second part).
-  void sqdmlsl2(const VRegister& vd,
-                const VRegister& vn,
-                const VRegister& vm);
+  void sqdmlsl2(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed saturating doubling long multiply.
-  void sqdmull(const VRegister& vd,
-               const VRegister& vn,
-               const VRegister& vm);
+  void sqdmull(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed saturating doubling long multiply (second part).
-  void sqdmull2(const VRegister& vd,
-                const VRegister& vn,
-                const VRegister& vm);
+  void sqdmull2(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed saturating doubling multiply returning high half.
-  void sqdmulh(const VRegister& vd,
-               const VRegister& vn,
-               const VRegister& vm);
+  void sqdmulh(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed saturating rounding doubling multiply returning high half.
-  void sqrdmulh(const VRegister& vd,
-                const VRegister& vn,
-                const VRegister& vm);
+  void sqrdmulh(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Signed saturating doubling multiply element returning high half.
   void sqdmulh(const VRegister& vd,
@@ -3544,79 +3102,49 @@
                 int vm_index);
 
   // Unsigned long multiply long.
-  void umull(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void umull(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Unsigned long multiply (second part).
-  void umull2(const VRegister& vd,
-              const VRegister& vn,
-              const VRegister& vm);
+  void umull2(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Add narrow returning high half.
-  void addhn(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void addhn(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Add narrow returning high half (second part).
-  void addhn2(const VRegister& vd,
-              const VRegister& vn,
-              const VRegister& vm);
+  void addhn2(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Rounding add narrow returning high half.
-  void raddhn(const VRegister& vd,
-              const VRegister& vn,
-              const VRegister& vm);
+  void raddhn(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Rounding add narrow returning high half (second part).
-  void raddhn2(const VRegister& vd,
-               const VRegister& vn,
-               const VRegister& vm);
+  void raddhn2(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Subtract narrow returning high half.
-  void subhn(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void subhn(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Subtract narrow returning high half (second part).
-  void subhn2(const VRegister& vd,
-              const VRegister& vn,
-              const VRegister& vm);
+  void subhn2(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Rounding subtract narrow returning high half.
-  void rsubhn(const VRegister& vd,
-              const VRegister& vn,
-              const VRegister& vm);
+  void rsubhn(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // Rounding subtract narrow returning high half (second part).
-  void rsubhn2(const VRegister& vd,
-               const VRegister& vn,
-               const VRegister& vm);
+  void rsubhn2(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // FP vector multiply accumulate.
-  void fmla(const VRegister& vd,
-            const VRegister& vn,
-            const VRegister& vm);
+  void fmla(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // FP vector multiply subtract.
-  void fmls(const VRegister& vd,
-            const VRegister& vn,
-            const VRegister& vm);
+  void fmls(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // FP vector multiply extended.
-  void fmulx(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void fmulx(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // FP absolute greater than or equal.
-  void facge(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void facge(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // FP absolute greater than.
-  void facgt(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void facgt(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // FP multiply by element.
   void fmul(const VRegister& vd,
@@ -3643,94 +3171,61 @@
              int vm_index);
 
   // FP compare equal.
-  void fcmeq(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void fcmeq(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // FP greater than.
-  void fcmgt(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void fcmgt(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // FP greater than or equal.
-  void fcmge(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void fcmge(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // FP compare equal to zero.
-  void fcmeq(const VRegister& vd,
-             const VRegister& vn,
-             double imm);
+  void fcmeq(const VRegister& vd, const VRegister& vn, double imm);
 
   // FP greater than zero.
-  void fcmgt(const VRegister& vd,
-             const VRegister& vn,
-             double imm);
+  void fcmgt(const VRegister& vd, const VRegister& vn, double imm);
 
   // FP greater than or equal to zero.
-  void fcmge(const VRegister& vd,
-             const VRegister& vn,
-             double imm);
+  void fcmge(const VRegister& vd, const VRegister& vn, double imm);
 
   // FP less than or equal to zero.
-  void fcmle(const VRegister& vd,
-             const VRegister& vn,
-             double imm);
+  void fcmle(const VRegister& vd, const VRegister& vn, double imm);
 
   // FP less than to zero.
-  void fcmlt(const VRegister& vd,
-             const VRegister& vn,
-             double imm);
+  void fcmlt(const VRegister& vd, const VRegister& vn, double imm);
 
   // FP absolute difference.
-  void fabd(const VRegister& vd,
-            const VRegister& vn,
-            const VRegister& vm);
+  void fabd(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // FP pairwise add vector.
-  void faddp(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void faddp(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // FP pairwise add scalar.
-  void faddp(const VRegister& vd,
-             const VRegister& vn);
+  void faddp(const VRegister& vd, const VRegister& vn);
 
   // FP pairwise maximum vector.
-  void fmaxp(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void fmaxp(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // FP pairwise maximum scalar.
-  void fmaxp(const VRegister& vd,
-             const VRegister& vn);
+  void fmaxp(const VRegister& vd, const VRegister& vn);
 
   // FP pairwise minimum vector.
-  void fminp(const VRegister& vd,
-             const VRegister& vn,
-             const VRegister& vm);
+  void fminp(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // FP pairwise minimum scalar.
-  void fminp(const VRegister& vd,
-             const VRegister& vn);
+  void fminp(const VRegister& vd, const VRegister& vn);
 
   // FP pairwise maximum number vector.
-  void fmaxnmp(const VRegister& vd,
-               const VRegister& vn,
-               const VRegister& vm);
+  void fmaxnmp(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // FP pairwise maximum number scalar.
-  void fmaxnmp(const VRegister& vd,
-               const VRegister& vn);
+  void fmaxnmp(const VRegister& vd, const VRegister& vn);
 
   // FP pairwise minimum number vector.
-  void fminnmp(const VRegister& vd,
-               const VRegister& vn,
-               const VRegister& vm);
+  void fminnmp(const VRegister& vd, const VRegister& vn, const VRegister& vm);
 
   // FP pairwise minimum number scalar.
-  void fminnmp(const VRegister& vd,
-               const VRegister& vn);
+  void fminnmp(const VRegister& vd, const VRegister& vn);
 
   // Emit generic instructions.
   // Emit raw instructions into the instruction stream.
@@ -3751,7 +3246,7 @@
   // Copy a string into the instruction stream, including the terminating NULL
   // character. The instruction pointer is then aligned correctly for
   // subsequent instructions.
-  void EmitString(const char * string) {
+  void EmitString(const char* string) {
     VIXL_ASSERT(string != NULL);
     VIXL_ASSERT(buffer_monitor_ > 0);
 
@@ -3826,9 +3321,7 @@
     return 0;
   }
 
-  static Instr Cond(Condition cond) {
-    return cond << Condition_offset;
-  }
+  static Instr Cond(Condition cond) { return cond << Condition_offset; }
 
   // PC-relative address encoding.
   static Instr ImmPCRelAddress(int imm21) {
@@ -3872,7 +3365,7 @@
 
   // Data Processing encoding.
   static Instr SF(Register rd) {
-      return rd.Is64Bits() ? SixtyFourBits : ThirtyTwoBits;
+    return rd.Is64Bits() ? SixtyFourBits : ThirtyTwoBits;
   }
 
   static Instr ImmAddSub(int imm) {
@@ -3887,14 +3380,14 @@
 
   static Instr ImmS(unsigned imms, unsigned reg_size) {
     VIXL_ASSERT(((reg_size == kXRegSize) && is_uint6(imms)) ||
-           ((reg_size == kWRegSize) && is_uint5(imms)));
+                ((reg_size == kWRegSize) && is_uint5(imms)));
     USE(reg_size);
     return imms << ImmS_offset;
   }
 
   static Instr ImmR(unsigned immr, unsigned reg_size) {
     VIXL_ASSERT(((reg_size == kXRegSize) && is_uint6(immr)) ||
-           ((reg_size == kWRegSize) && is_uint5(immr)));
+                ((reg_size == kWRegSize) && is_uint5(immr)));
     USE(reg_size);
     VIXL_ASSERT(is_uint6(immr));
     return immr << ImmR_offset;
@@ -3911,7 +3404,7 @@
   static Instr ImmRotate(unsigned immr, unsigned reg_size) {
     VIXL_ASSERT((reg_size == kWRegSize) || (reg_size == kXRegSize));
     VIXL_ASSERT(((reg_size == kXRegSize) && is_uint6(immr)) ||
-           ((reg_size == kWRegSize) && is_uint5(immr)));
+                ((reg_size == kWRegSize) && is_uint5(immr)));
     USE(reg_size);
     return immr << ImmRotate_offset;
   }
@@ -3938,9 +3431,7 @@
     return amount << ImmDPShift_offset;
   }
 
-  static Instr ExtendMode(Extend extend) {
-    return extend << ExtendMode_offset;
-  }
+  static Instr ExtendMode(Extend extend) { return extend << ExtendMode_offset; }
 
   static Instr ImmExtendShift(unsigned left_shift) {
     VIXL_ASSERT(left_shift <= 4);
@@ -4050,9 +3541,7 @@
   static Instr ImmFP64(double imm);
 
   // FP register type.
-  static Instr FPType(FPRegister fd) {
-    return fd.Is64Bits() ? FP64 : FP32;
-  }
+  static Instr FPType(FPRegister fd) { return fd.Is64Bits() ? FP64 : FP32; }
 
   static Instr FPScale(unsigned scale) {
     VIXL_ASSERT(is_uint6(scale));
@@ -4079,19 +3568,28 @@
   static Instr VFormat(VRegister vd) {
     if (vd.Is64Bits()) {
       switch (vd.lanes()) {
-        case 2: return NEON_2S;
-        case 4: return NEON_4H;
-        case 8: return NEON_8B;
-        default: return 0xffffffff;
+        case 2:
+          return NEON_2S;
+        case 4:
+          return NEON_4H;
+        case 8:
+          return NEON_8B;
+        default:
+          return 0xffffffff;
       }
     } else {
       VIXL_ASSERT(vd.Is128Bits());
       switch (vd.lanes()) {
-        case 2: return NEON_2D;
-        case 4: return NEON_4S;
-        case 8: return NEON_8H;
-        case 16: return NEON_16B;
-        default: return 0xffffffff;
+        case 2:
+          return NEON_2D;
+        case 4:
+          return NEON_4S;
+        case 8:
+          return NEON_8H;
+        case 16:
+          return NEON_16B;
+        default:
+          return 0xffffffff;
       }
     }
   }
@@ -4120,20 +3618,30 @@
   static Instr LSVFormat(VRegister vd) {
     if (vd.Is64Bits()) {
       switch (vd.lanes()) {
-        case 1: return LS_NEON_1D;
-        case 2: return LS_NEON_2S;
-        case 4: return LS_NEON_4H;
-        case 8: return LS_NEON_8B;
-        default: return 0xffffffff;
+        case 1:
+          return LS_NEON_1D;
+        case 2:
+          return LS_NEON_2S;
+        case 4:
+          return LS_NEON_4H;
+        case 8:
+          return LS_NEON_8B;
+        default:
+          return 0xffffffff;
       }
     } else {
       VIXL_ASSERT(vd.Is128Bits());
       switch (vd.lanes()) {
-        case 2: return LS_NEON_2D;
-        case 4: return LS_NEON_4S;
-        case 8: return LS_NEON_8H;
-        case 16: return LS_NEON_16B;
-        default: return 0xffffffff;
+        case 2:
+          return LS_NEON_2D;
+        case 4:
+          return LS_NEON_4S;
+        case 8:
+          return LS_NEON_8H;
+        case 16:
+          return LS_NEON_16B;
+        default:
+          return 0xffffffff;
       }
     }
   }
@@ -4142,11 +3650,16 @@
   static Instr SFormat(VRegister vd) {
     VIXL_ASSERT(vd.lanes() == 1);
     switch (vd.SizeInBytes()) {
-      case 1: return NEON_B;
-      case 2: return NEON_H;
-      case 4: return NEON_S;
-      case 8: return NEON_D;
-      default: return 0xffffffff;
+      case 1:
+        return NEON_B;
+      case 2:
+        return NEON_H;
+      case 4:
+        return NEON_S;
+      case 8:
+        return NEON_D;
+      default:
+        return 0xffffffff;
     }
   }
 
@@ -4154,19 +3667,19 @@
     int h, l, m;
     if (num_bits == 3) {
       VIXL_ASSERT(is_uint3(index));
-      h  = (index >> 2) & 1;
-      l  = (index >> 1) & 1;
-      m  = (index >> 0) & 1;
+      h = (index >> 2) & 1;
+      l = (index >> 1) & 1;
+      m = (index >> 0) & 1;
     } else if (num_bits == 2) {
       VIXL_ASSERT(is_uint2(index));
-      h  = (index >> 1) & 1;
-      l  = (index >> 0) & 1;
-      m  = 0;
+      h = (index >> 1) & 1;
+      l = (index >> 0) & 1;
+      m = 0;
     } else {
       VIXL_ASSERT(is_uint1(index) && (num_bits == 1));
-      h  = (index >> 0) & 1;
-      l  = 0;
-      m  = 0;
+      h = (index >> 0) & 1;
+      l = 0;
+      m = 0;
     }
     return (h << NEONH_offset) | (l << NEONL_offset) | (m << NEONM_offset);
   }
@@ -4193,7 +3706,7 @@
   static Instr ImmNEONabcdefgh(int imm8) {
     VIXL_ASSERT(is_uint8(imm8));
     Instr instr;
-    instr  = ((imm8 >> 5) & 7) << ImmNEONabc_offset;
+    instr = ((imm8 >> 5) & 7) << ImmNEONabc_offset;
     instr |= (imm8 & 0x1f) << ImmNEONdefgh_offset;
     return instr;
   }
@@ -4214,9 +3727,7 @@
     return buffer_->OffsetFrom(label->location());
   }
 
-  size_t SizeOfCodeGenerated() const {
-    return buffer_->CursorOffset();
-  }
+  size_t SizeOfCodeGenerated() const { return buffer_->CursorOffset(); }
 
   size_t BufferCapacity() const { return buffer_->capacity(); }
 
@@ -4229,7 +3740,7 @@
       do {
         // TODO(all): refine.
         capacity *= 2;
-      } while ((capacity - size) <  amount);
+      } while ((capacity - size) < amount);
       buffer_->Grow(capacity);
     }
   }
@@ -4246,9 +3757,7 @@
   }
 #endif
 
-  PositionIndependentCodeOption pic() const {
-    return pic_;
-  }
+  PositionIndependentCodeOption pic() const { return pic_; }
 
   bool AllowPageOffsetDependentCode() const {
     return (pic() == PageOffsetDependentCode) ||
@@ -4349,9 +3858,9 @@
   static LoadStorePairOp StorePairOpFor(const CPURegister& rt,
                                         const CPURegister& rt2);
   static LoadStorePairNonTemporalOp LoadPairNonTemporalOpFor(
-    const CPURegister& rt, const CPURegister& rt2);
+      const CPURegister& rt, const CPURegister& rt2);
   static LoadStorePairNonTemporalOp StorePairNonTemporalOpFor(
-    const CPURegister& rt, const CPURegister& rt2);
+      const CPURegister& rt, const CPURegister& rt2);
   static LoadLiteralOp LoadLiteralOpFor(const CPURegister& rt);
 
 
@@ -4414,9 +3923,7 @@
                                const int imm8,
                                const int shift_amount,
                                NEONModifiedImmediateOp op);
-  void NEONFP2Same(const VRegister& vd,
-                   const VRegister& vn,
-                   Instr vop);
+  void NEONFP2Same(const VRegister& vd, const VRegister& vn, Instr vop);
   void NEON3Same(const VRegister& vd,
                  const VRegister& vn,
                  const VRegister& vm,
@@ -4445,12 +3952,8 @@
                     const VRegister& vn,
                     NEON2RegMiscOp vop,
                     int value = 0);
-  void NEONFP2RegMisc(const VRegister& vd,
-                      const VRegister& vn,
-                      Instr op);
-  void NEONAddlp(const VRegister& vd,
-                 const VRegister& vn,
-                 NEON2RegMiscOp op);
+  void NEONFP2RegMisc(const VRegister& vd, const VRegister& vn, Instr op);
+  void NEONAddlp(const VRegister& vd, const VRegister& vn, NEON2RegMiscOp op);
   void NEONPerm(const VRegister& vd,
                 const VRegister& vn,
                 const VRegister& vm,
@@ -4490,9 +3993,7 @@
                            const VRegister& vn,
                            int shift,
                            NEONShiftImmediateOp op);
-  void NEONXtn(const VRegister& vd,
-               const VRegister& vn,
-               NEON2RegMiscOp vop);
+  void NEONXtn(const VRegister& vd, const VRegister& vn, NEON2RegMiscOp vop);
 
   Instr LoadStoreStructAddrModeField(const MemOperand& addr);
 
@@ -4505,9 +4006,9 @@
   // Link the current (not-yet-emitted) instruction to the specified label, then
   // return an offset to be encoded in the instruction. If the label is not yet
   // bound, an offset of 0 is returned.
-  ptrdiff_t LinkAndGetByteOffsetTo(Label * label);
-  ptrdiff_t LinkAndGetInstructionOffsetTo(Label * label);
-  ptrdiff_t LinkAndGetPageOffsetTo(Label * label);
+  ptrdiff_t LinkAndGetByteOffsetTo(Label* label);
+  ptrdiff_t LinkAndGetInstructionOffsetTo(Label* label);
+  ptrdiff_t LinkAndGetPageOffsetTo(Label* label);
 
   // A common implementation for the LinkAndGet<Type>OffsetTo helpers.
   template <int element_shift>
@@ -4542,10 +4043,7 @@
  public:
   // Tell whether or not the scope needs to ensure the associated CodeBuffer
   // has enough space for the requested size.
-  enum CheckPolicy {
-    kNoCheck,
-    kCheck
-  };
+  enum CheckPolicy { kNoCheck, kCheck };
 
   // Tell whether or not the scope should assert the amount of code emitted
   // within the scope is consistent with the requested amount.
@@ -4584,7 +4082,8 @@
 #ifdef VIXL_DEBUG
     assm_->ReleaseBuffer();
     switch (assert_policy_) {
-      case kNoAssert: break;
+      case kNoAssert:
+        break;
       case kExactSize:
         VIXL_ASSERT(assm_->SizeOfCodeGeneratedSince(&start_) == size_);
         break;
diff --git a/src/vixl/a64/constants-a64.h b/src/vixl/a64/constants-a64.h
index 2caa73a..94cabad 100644
--- a/src/vixl/a64/constants-a64.h
+++ b/src/vixl/a64/constants-a64.h
@@ -39,151 +39,153 @@
 const int kNumberOfCalleeSavedFPRegisters = 8;
 const int kFirstCalleeSavedFPRegisterIndex = 8;
 
+// clang-format off
 #define REGISTER_CODE_LIST(R)                                                  \
 R(0)  R(1)  R(2)  R(3)  R(4)  R(5)  R(6)  R(7)                                 \
 R(8)  R(9)  R(10) R(11) R(12) R(13) R(14) R(15)                                \
 R(16) R(17) R(18) R(19) R(20) R(21) R(22) R(23)                                \
 R(24) R(25) R(26) R(27) R(28) R(29) R(30) R(31)
+// clang-format on
 
-#define INSTRUCTION_FIELDS_LIST(V_)                                            \
-/* Register fields */                                                          \
-V_(Rd, 4, 0, Bits)                        /* Destination register.        */   \
-V_(Rn, 9, 5, Bits)                        /* First source register.       */   \
-V_(Rm, 20, 16, Bits)                      /* Second source register.      */   \
-V_(Ra, 14, 10, Bits)                      /* Third source register.       */   \
-V_(Rt, 4, 0, Bits)                        /* Load/store register.         */   \
-V_(Rt2, 14, 10, Bits)                     /* Load/store second register.  */   \
-V_(Rs, 20, 16, Bits)                      /* Exclusive access status.     */   \
-                                                                               \
-/* Common bits */                                                              \
-V_(SixtyFourBits, 31, 31, Bits)                                                \
-V_(FlagsUpdate, 29, 29, Bits)                                                  \
-                                                                               \
-/* PC relative addressing */                                                   \
-V_(ImmPCRelHi, 23, 5, SignedBits)                                              \
-V_(ImmPCRelLo, 30, 29, Bits)                                                   \
-                                                                               \
-/* Add/subtract/logical shift register */                                      \
-V_(ShiftDP, 23, 22, Bits)                                                      \
-V_(ImmDPShift, 15, 10, Bits)                                                   \
-                                                                               \
-/* Add/subtract immediate */                                                   \
-V_(ImmAddSub, 21, 10, Bits)                                                    \
-V_(ShiftAddSub, 23, 22, Bits)                                                  \
-                                                                               \
-/* Add/substract extend */                                                     \
-V_(ImmExtendShift, 12, 10, Bits)                                               \
-V_(ExtendMode, 15, 13, Bits)                                                   \
-                                                                               \
-/* Move wide */                                                                \
-V_(ImmMoveWide, 20, 5, Bits)                                                   \
-V_(ShiftMoveWide, 22, 21, Bits)                                                \
-                                                                               \
-/* Logical immediate, bitfield and extract */                                  \
-V_(BitN, 22, 22, Bits)                                                         \
-V_(ImmRotate, 21, 16, Bits)                                                    \
-V_(ImmSetBits, 15, 10, Bits)                                                   \
-V_(ImmR, 21, 16, Bits)                                                         \
-V_(ImmS, 15, 10, Bits)                                                         \
-                                                                               \
-/* Test and branch immediate */                                                \
-V_(ImmTestBranch, 18, 5, SignedBits)                                           \
-V_(ImmTestBranchBit40, 23, 19, Bits)                                           \
-V_(ImmTestBranchBit5, 31, 31, Bits)                                            \
-                                                                               \
-/* Conditionals */                                                             \
-V_(Condition, 15, 12, Bits)                                                    \
-V_(ConditionBranch, 3, 0, Bits)                                                \
-V_(Nzcv, 3, 0, Bits)                                                           \
-V_(ImmCondCmp, 20, 16, Bits)                                                   \
-V_(ImmCondBranch, 23, 5, SignedBits)                                           \
-                                                                               \
-/* Floating point */                                                           \
-V_(FPType, 23, 22, Bits)                                                       \
-V_(ImmFP, 20, 13, Bits)                                                        \
-V_(FPScale, 15, 10, Bits)                                                      \
-                                                                               \
-/* Load Store */                                                               \
-V_(ImmLS, 20, 12, SignedBits)                                                  \
-V_(ImmLSUnsigned, 21, 10, Bits)                                                \
-V_(ImmLSPair, 21, 15, SignedBits)                                              \
-V_(ImmShiftLS, 12, 12, Bits)                                                   \
-V_(LSOpc, 23, 22, Bits)                                                        \
-V_(LSVector, 26, 26, Bits)                                                     \
-V_(LSSize, 31, 30, Bits)                                                       \
-V_(ImmPrefetchOperation, 4, 0, Bits)                                           \
-V_(PrefetchHint, 4, 3, Bits)                                                   \
-V_(PrefetchTarget, 2, 1, Bits)                                                 \
-V_(PrefetchStream, 0, 0, Bits)                                                 \
-                                                                               \
-/* Other immediates */                                                         \
-V_(ImmUncondBranch, 25, 0, SignedBits)                                         \
-V_(ImmCmpBranch, 23, 5, SignedBits)                                            \
-V_(ImmLLiteral, 23, 5, SignedBits)                                             \
-V_(ImmException, 20, 5, Bits)                                                  \
-V_(ImmHint, 11, 5, Bits)                                                       \
-V_(ImmBarrierDomain, 11, 10, Bits)                                             \
-V_(ImmBarrierType, 9, 8, Bits)                                                 \
-                                                                               \
-/* System (MRS, MSR, SYS) */                                                   \
-V_(ImmSystemRegister, 19, 5, Bits)                                             \
-V_(SysO0, 19, 19, Bits)                                                        \
-V_(SysOp, 18, 5, Bits)                                                         \
-V_(SysOp1, 18, 16, Bits)                                                       \
-V_(SysOp2, 7, 5, Bits)                                                         \
-V_(CRn, 15, 12, Bits)                                                          \
-V_(CRm, 11, 8, Bits)                                                           \
-                                                                               \
-/* Load-/store-exclusive */                                                    \
-V_(LdStXLoad, 22, 22, Bits)                                                    \
-V_(LdStXNotExclusive, 23, 23, Bits)                                            \
-V_(LdStXAcquireRelease, 15, 15, Bits)                                          \
-V_(LdStXSizeLog2, 31, 30, Bits)                                                \
-V_(LdStXPair, 21, 21, Bits)                                                    \
-                                                                               \
-/* NEON generic fields */                                                      \
-V_(NEONQ, 30, 30, Bits)                                                        \
-V_(NEONSize, 23, 22, Bits)                                                     \
-V_(NEONLSSize, 11, 10, Bits)                                                   \
-V_(NEONS, 12, 12, Bits)                                                        \
-V_(NEONL, 21, 21, Bits)                                                        \
-V_(NEONM, 20, 20, Bits)                                                        \
-V_(NEONH, 11, 11, Bits)                                                        \
-V_(ImmNEONExt, 14, 11, Bits)                                                   \
-V_(ImmNEON5, 20, 16, Bits)                                                     \
-V_(ImmNEON4, 14, 11, Bits)                                                     \
-                                                                               \
-/* NEON Modified Immediate fields */                                           \
-V_(ImmNEONabc, 18, 16, Bits)                                                   \
-V_(ImmNEONdefgh, 9, 5, Bits)                                                   \
-V_(NEONModImmOp, 29, 29, Bits)                                                 \
-V_(NEONCmode, 15, 12, Bits)                                                    \
-                                                                               \
-/* NEON Shift Immediate fields */                                              \
-V_(ImmNEONImmhImmb, 22, 16, Bits)                                              \
-V_(ImmNEONImmh, 22, 19, Bits)                                                  \
-V_(ImmNEONImmb, 18, 16, Bits)
+#define INSTRUCTION_FIELDS_LIST(V_)                        \
+  /* Register fields */                                    \
+  V_(Rd, 4, 0, Bits)    /* Destination register.        */ \
+  V_(Rn, 9, 5, Bits)    /* First source register.       */ \
+  V_(Rm, 20, 16, Bits)  /* Second source register.      */ \
+  V_(Ra, 14, 10, Bits)  /* Third source register.       */ \
+  V_(Rt, 4, 0, Bits)    /* Load/store register.         */ \
+  V_(Rt2, 14, 10, Bits) /* Load/store second register.  */ \
+  V_(Rs, 20, 16, Bits)  /* Exclusive access status.     */  \
+                                                           \
+  /* Common bits */                                        \
+  V_(SixtyFourBits, 31, 31, Bits)                          \
+  V_(FlagsUpdate, 29, 29, Bits)                            \
+                                                           \
+  /* PC relative addressing */                             \
+  V_(ImmPCRelHi, 23, 5, SignedBits)                        \
+  V_(ImmPCRelLo, 30, 29, Bits)                             \
+                                                           \
+  /* Add/subtract/logical shift register */                \
+  V_(ShiftDP, 23, 22, Bits)                                \
+  V_(ImmDPShift, 15, 10, Bits)                             \
+                                                           \
+  /* Add/subtract immediate */                             \
+  V_(ImmAddSub, 21, 10, Bits)                              \
+  V_(ShiftAddSub, 23, 22, Bits)                            \
+                                                           \
+  /* Add/substract extend */                               \
+  V_(ImmExtendShift, 12, 10, Bits)                         \
+  V_(ExtendMode, 15, 13, Bits)                             \
+                                                           \
+  /* Move wide */                                          \
+  V_(ImmMoveWide, 20, 5, Bits)                             \
+  V_(ShiftMoveWide, 22, 21, Bits)                          \
+                                                           \
+  /* Logical immediate, bitfield and extract */            \
+  V_(BitN, 22, 22, Bits)                                   \
+  V_(ImmRotate, 21, 16, Bits)                              \
+  V_(ImmSetBits, 15, 10, Bits)                             \
+  V_(ImmR, 21, 16, Bits)                                   \
+  V_(ImmS, 15, 10, Bits)                                   \
+                                                           \
+  /* Test and branch immediate */                          \
+  V_(ImmTestBranch, 18, 5, SignedBits)                     \
+  V_(ImmTestBranchBit40, 23, 19, Bits)                     \
+  V_(ImmTestBranchBit5, 31, 31, Bits)                      \
+                                                           \
+  /* Conditionals */                                       \
+  V_(Condition, 15, 12, Bits)                              \
+  V_(ConditionBranch, 3, 0, Bits)                          \
+  V_(Nzcv, 3, 0, Bits)                                     \
+  V_(ImmCondCmp, 20, 16, Bits)                             \
+  V_(ImmCondBranch, 23, 5, SignedBits)                     \
+                                                           \
+  /* Floating point */                                     \
+  V_(FPType, 23, 22, Bits)                                 \
+  V_(ImmFP, 20, 13, Bits)                                  \
+  V_(FPScale, 15, 10, Bits)                                \
+                                                           \
+  /* Load Store */                                         \
+  V_(ImmLS, 20, 12, SignedBits)                            \
+  V_(ImmLSUnsigned, 21, 10, Bits)                          \
+  V_(ImmLSPair, 21, 15, SignedBits)                        \
+  V_(ImmShiftLS, 12, 12, Bits)                             \
+  V_(LSOpc, 23, 22, Bits)                                  \
+  V_(LSVector, 26, 26, Bits)                               \
+  V_(LSSize, 31, 30, Bits)                                 \
+  V_(ImmPrefetchOperation, 4, 0, Bits)                     \
+  V_(PrefetchHint, 4, 3, Bits)                             \
+  V_(PrefetchTarget, 2, 1, Bits)                           \
+  V_(PrefetchStream, 0, 0, Bits)                           \
+                                                           \
+  /* Other immediates */                                   \
+  V_(ImmUncondBranch, 25, 0, SignedBits)                   \
+  V_(ImmCmpBranch, 23, 5, SignedBits)                      \
+  V_(ImmLLiteral, 23, 5, SignedBits)                       \
+  V_(ImmException, 20, 5, Bits)                            \
+  V_(ImmHint, 11, 5, Bits)                                 \
+  V_(ImmBarrierDomain, 11, 10, Bits)                       \
+  V_(ImmBarrierType, 9, 8, Bits)                           \
+                                                           \
+  /* System (MRS, MSR, SYS) */                             \
+  V_(ImmSystemRegister, 19, 5, Bits)                       \
+  V_(SysO0, 19, 19, Bits)                                  \
+  V_(SysOp, 18, 5, Bits)                                   \
+  V_(SysOp1, 18, 16, Bits)                                 \
+  V_(SysOp2, 7, 5, Bits)                                   \
+  V_(CRn, 15, 12, Bits)                                    \
+  V_(CRm, 11, 8, Bits)                                     \
+                                                           \
+  /* Load-/store-exclusive */                              \
+  V_(LdStXLoad, 22, 22, Bits)                              \
+  V_(LdStXNotExclusive, 23, 23, Bits)                      \
+  V_(LdStXAcquireRelease, 15, 15, Bits)                    \
+  V_(LdStXSizeLog2, 31, 30, Bits)                          \
+  V_(LdStXPair, 21, 21, Bits)                              \
+                                                           \
+  /* NEON generic fields */                                \
+  V_(NEONQ, 30, 30, Bits)                                  \
+  V_(NEONSize, 23, 22, Bits)                               \
+  V_(NEONLSSize, 11, 10, Bits)                             \
+  V_(NEONS, 12, 12, Bits)                                  \
+  V_(NEONL, 21, 21, Bits)                                  \
+  V_(NEONM, 20, 20, Bits)                                  \
+  V_(NEONH, 11, 11, Bits)                                  \
+  V_(ImmNEONExt, 14, 11, Bits)                             \
+  V_(ImmNEON5, 20, 16, Bits)                               \
+  V_(ImmNEON4, 14, 11, Bits)                               \
+                                                           \
+  /* NEON Modified Immediate fields */                     \
+  V_(ImmNEONabc, 18, 16, Bits)                             \
+  V_(ImmNEONdefgh, 9, 5, Bits)                             \
+  V_(NEONModImmOp, 29, 29, Bits)                           \
+  V_(NEONCmode, 15, 12, Bits)                              \
+                                                           \
+  /* NEON Shift Immediate fields */                        \
+  V_(ImmNEONImmhImmb, 22, 16, Bits)                        \
+  V_(ImmNEONImmh, 22, 19, Bits)                            \
+  V_(ImmNEONImmb, 18, 16, Bits)
 
-#define SYSTEM_REGISTER_FIELDS_LIST(V_, M_)                                    \
-/* NZCV */                                                                     \
-V_(Flags, 31, 28, Bits)                                                        \
-V_(N, 31, 31, Bits)                                                            \
-V_(Z, 30, 30, Bits)                                                            \
-V_(C, 29, 29, Bits)                                                            \
-V_(V, 28, 28, Bits)                                                            \
-M_(NZCV, Flags_mask)                                                           \
-/* FPCR */                                                                     \
-V_(AHP, 26, 26, Bits)                                                          \
-V_(DN, 25, 25, Bits)                                                           \
-V_(FZ, 24, 24, Bits)                                                           \
-V_(RMode, 23, 22, Bits)                                                        \
-M_(FPCR, AHP_mask | DN_mask | FZ_mask | RMode_mask)
+#define SYSTEM_REGISTER_FIELDS_LIST(V_, M_) \
+  /* NZCV */                                \
+  V_(Flags, 31, 28, Bits)                   \
+  V_(N, 31, 31, Bits)                       \
+  V_(Z, 30, 30, Bits)                       \
+  V_(C, 29, 29, Bits)                       \
+  V_(V, 28, 28, Bits)                       \
+  M_(NZCV, Flags_mask)                      \
+  /* FPCR */                                \
+  V_(AHP, 26, 26, Bits)                     \
+  V_(DN, 25, 25, Bits)                      \
+  V_(FZ, 24, 24, Bits)                      \
+  V_(RMode, 23, 22, Bits)                   \
+  M_(FPCR, AHP_mask | DN_mask | FZ_mask | RMode_mask)
 
 // Fields offsets.
-#define DECLARE_FIELDS_OFFSETS(Name, HighBit, LowBit, X)                       \
-const int Name##_offset = LowBit;                                              \
-const int Name##_width = HighBit - LowBit + 1;                                 \
-const uint32_t Name##_mask = ((1 << Name##_width) - 1) << LowBit;
+#define DECLARE_FIELDS_OFFSETS(Name, HighBit, LowBit, X) \
+  const int Name##_offset = LowBit;                      \
+  const int Name##_width = HighBit - LowBit + 1;         \
+  const uint32_t Name##_mask = ((1 << Name##_width) - 1) << LowBit;
 #define NOTHING(A, B)
 INSTRUCTION_FIELDS_LIST(DECLARE_FIELDS_OFFSETS)
 SYSTEM_REGISTER_FIELDS_LIST(DECLARE_FIELDS_OFFSETS, NOTHING)
@@ -194,6 +196,10 @@
 // from ImmPCRelLo and ImmPCRelHi.
 const int ImmPCRel_mask = ImmPCRelLo_mask | ImmPCRelHi_mask;
 
+// Disable `clang-format` for the `enum`s below. We care about the manual
+// formatting that `clang-format` would destroy.
+// clang-format off
+
 // Condition codes.
 enum Condition {
   eq = 0,   // Z set            Equal.
@@ -1434,8 +1440,8 @@
 enum NEON3SameOp {
   NEON3SameFixed = 0x0E200400,
   NEON3SameFMask = 0x9F200400,
-  NEON3SameMask = 0xBF20FC00,
-  NEON3SameUBit = 0x20000000,
+  NEON3SameMask =  0xBF20FC00,
+  NEON3SameUBit =  0x20000000,
   NEON_ADD    = NEON3SameFixed | 0x00008000,
   NEON_ADDP   = NEON3SameFixed | 0x0000B800,
   NEON_SHADD  = NEON3SameFixed | 0x00000000,
@@ -1661,7 +1667,7 @@
 enum NEONExtractOp {
   NEONExtractFixed = 0x2E000000,
   NEONExtractFMask = 0xBF208400,
-  NEONExtractMask = 0xBFE08400,
+  NEONExtractMask =  0xBFE08400,
   NEON_EXT = NEONExtractFixed | 0x00000000
 };
 
@@ -1806,7 +1812,7 @@
   NEONLoadStoreSingleStructPostIndexFixed = 0x0D800000,
   NEONLoadStoreSingleStructPostIndexFMask = 0xBF800000,
   NEONLoadStoreSingleStructPostIndexMask  = 0xBFE0E000,
-  NEONLoadStoreSingleStructPostIndex = 0x00800000,
+  NEONLoadStoreSingleStructPostIndex =      0x00800000,
   NEON_LD1_b_post = NEON_LD1_b | NEONLoadStoreSingleStructPostIndex,
   NEON_LD1_h_post = NEON_LD1_h | NEONLoadStoreSingleStructPostIndex,
   NEON_LD1_s_post = NEON_LD1_s | NEONLoadStoreSingleStructPostIndex,
@@ -2073,28 +2079,28 @@
   NEONScalarShiftImmediateFixed = 0x5F000400,
   NEONScalarShiftImmediateFMask = 0xDF800400,
   NEONScalarShiftImmediateMask  = 0xFF80FC00,
-  NEON_SHL_scalar  = NEON_Q | NEONScalar | NEON_SHL,
-  NEON_SLI_scalar  = NEON_Q | NEONScalar | NEON_SLI,
-  NEON_SRI_scalar  = NEON_Q | NEONScalar | NEON_SRI,
-  NEON_SSHR_scalar = NEON_Q | NEONScalar | NEON_SSHR,
-  NEON_USHR_scalar = NEON_Q | NEONScalar | NEON_USHR,
-  NEON_SRSHR_scalar = NEON_Q | NEONScalar | NEON_SRSHR,
-  NEON_URSHR_scalar = NEON_Q | NEONScalar | NEON_URSHR,
-  NEON_SSRA_scalar = NEON_Q | NEONScalar | NEON_SSRA,
-  NEON_USRA_scalar = NEON_Q | NEONScalar | NEON_USRA,
-  NEON_SRSRA_scalar = NEON_Q | NEONScalar | NEON_SRSRA,
-  NEON_URSRA_scalar = NEON_Q | NEONScalar | NEON_URSRA,
-  NEON_UQSHRN_scalar = NEON_Q | NEONScalar | NEON_UQSHRN,
-  NEON_UQRSHRN_scalar = NEON_Q | NEONScalar | NEON_UQRSHRN,
-  NEON_SQSHRN_scalar = NEON_Q | NEONScalar | NEON_SQSHRN,
-  NEON_SQRSHRN_scalar = NEON_Q | NEONScalar | NEON_SQRSHRN,
-  NEON_SQSHRUN_scalar = NEON_Q | NEONScalar | NEON_SQSHRUN,
-  NEON_SQRSHRUN_scalar = NEON_Q | NEONScalar | NEON_SQRSHRUN,
-  NEON_SQSHLU_scalar = NEON_Q | NEONScalar | NEON_SQSHLU,
+  NEON_SHL_scalar  =       NEON_Q | NEONScalar | NEON_SHL,
+  NEON_SLI_scalar  =       NEON_Q | NEONScalar | NEON_SLI,
+  NEON_SRI_scalar  =       NEON_Q | NEONScalar | NEON_SRI,
+  NEON_SSHR_scalar =       NEON_Q | NEONScalar | NEON_SSHR,
+  NEON_USHR_scalar =       NEON_Q | NEONScalar | NEON_USHR,
+  NEON_SRSHR_scalar =      NEON_Q | NEONScalar | NEON_SRSHR,
+  NEON_URSHR_scalar =      NEON_Q | NEONScalar | NEON_URSHR,
+  NEON_SSRA_scalar =       NEON_Q | NEONScalar | NEON_SSRA,
+  NEON_USRA_scalar =       NEON_Q | NEONScalar | NEON_USRA,
+  NEON_SRSRA_scalar =      NEON_Q | NEONScalar | NEON_SRSRA,
+  NEON_URSRA_scalar =      NEON_Q | NEONScalar | NEON_URSRA,
+  NEON_UQSHRN_scalar =     NEON_Q | NEONScalar | NEON_UQSHRN,
+  NEON_UQRSHRN_scalar =    NEON_Q | NEONScalar | NEON_UQRSHRN,
+  NEON_SQSHRN_scalar =     NEON_Q | NEONScalar | NEON_SQSHRN,
+  NEON_SQRSHRN_scalar =    NEON_Q | NEONScalar | NEON_SQRSHRN,
+  NEON_SQSHRUN_scalar =    NEON_Q | NEONScalar | NEON_SQSHRUN,
+  NEON_SQRSHRUN_scalar =   NEON_Q | NEONScalar | NEON_SQRSHRUN,
+  NEON_SQSHLU_scalar =     NEON_Q | NEONScalar | NEON_SQSHLU,
   NEON_SQSHL_imm_scalar  = NEON_Q | NEONScalar | NEON_SQSHL_imm,
   NEON_UQSHL_imm_scalar  = NEON_Q | NEONScalar | NEON_UQSHL_imm,
-  NEON_SCVTF_imm_scalar = NEON_Q | NEONScalar | NEON_SCVTF_imm,
-  NEON_UCVTF_imm_scalar = NEON_Q | NEONScalar | NEON_UCVTF_imm,
+  NEON_SCVTF_imm_scalar =  NEON_Q | NEONScalar | NEON_SCVTF_imm,
+  NEON_UCVTF_imm_scalar =  NEON_Q | NEONScalar | NEON_UCVTF_imm,
   NEON_FCVTZS_imm_scalar = NEON_Q | NEONScalar | NEON_FCVTZS_imm,
   NEON_FCVTZU_imm_scalar = NEON_Q | NEONScalar | NEON_FCVTZU_imm
 };
@@ -2111,6 +2117,9 @@
   UnallocatedFMask = 0x00000000
 };
 
+// Re-enable `clang-format` after the `enum`s.
+// clang-format on
+
 }  // namespace vixl
 
 #endif  // VIXL_A64_CONSTANTS_A64_H_
diff --git a/src/vixl/a64/cpu-a64.cc b/src/vixl/a64/cpu-a64.cc
index bc905d1..4fb7de9 100644
--- a/src/vixl/a64/cpu-a64.cc
+++ b/src/vixl/a64/cpu-a64.cc
@@ -61,8 +61,8 @@
 #ifdef __aarch64__
   uint64_t cache_type_register;
   // Copy the content of the cache type register to a core register.
-  __asm__ __volatile__ ("mrs %[ctr], ctr_el0"  // NOLINT
-                        : [ctr] "=r" (cache_type_register));
+  __asm__ __volatile__("mrs %[ctr], ctr_el0"  // NOLINT
+                       : [ctr] "=r"(cache_type_register));
   VIXL_ASSERT(is_uint32(cache_type_register));
   return cache_type_register;
 #else
@@ -101,65 +101,70 @@
   uintptr_t end = start + length;
 
   do {
-    __asm__ __volatile__ (
-      // Clean each line of the D cache containing the target data.
-      //
-      // dc       : Data Cache maintenance
-      //     c    : Clean
-      //      va  : by (Virtual) Address
-      //        u : to the point of Unification
-      // The point of unification for a processor is the point by which the
-      // instruction and data caches are guaranteed to see the same copy of a
-      // memory location. See ARM DDI 0406B page B2-12 for more information.
-      "   dc    cvau, %[dline]\n"
-      :
-      : [dline] "r" (dline)
-      // This code does not write to memory, but the "memory" dependency
-      // prevents GCC from reordering the code.
-      : "memory");
+    __asm__ __volatile__(
+        // Clean each line of the D cache containing the target data.
+        //
+        // dc       : Data Cache maintenance
+        //     c    : Clean
+        //      va  : by (Virtual) Address
+        //        u : to the point of Unification
+        // The point of unification for a processor is the point by which the
+        // instruction and data caches are guaranteed to see the same copy of a
+        // memory location. See ARM DDI 0406B page B2-12 for more information.
+        "   dc    cvau, %[dline]\n"
+        :
+        : [dline] "r"(dline)
+        // This code does not write to memory, but the "memory" dependency
+        // prevents GCC from reordering the code.
+        : "memory");
     dline += dsize;
   } while (dline < end);
 
-  __asm__ __volatile__ (
-    // Make sure that the data cache operations (above) complete before the
-    // instruction cache operations (below).
-    //
-    // dsb      : Data Synchronisation Barrier
-    //      ish : Inner SHareable domain
-    //
-    // The point of unification for an Inner Shareable shareability domain is
-    // the point by which the instruction and data caches of all the processors
-    // in that Inner Shareable shareability domain are guaranteed to see the
-    // same copy of a memory location.  See ARM DDI 0406B page B2-12 for more
-    // information.
-    "   dsb   ish\n"
-    : : : "memory");
+  __asm__ __volatile__(
+      // Make sure that the data cache operations (above) complete before the
+      // instruction cache operations (below).
+      //
+      // dsb      : Data Synchronisation Barrier
+      //      ish : Inner SHareable domain
+      //
+      // The point of unification for an Inner Shareable shareability domain is
+      // the point by which the instruction and data caches of all the
+      // processors
+      // in that Inner Shareable shareability domain are guaranteed to see the
+      // same copy of a memory location. See ARM DDI 0406B page B2-12 for more
+      // information.
+      "   dsb   ish\n"
+      :
+      :
+      : "memory");
 
   do {
-    __asm__ __volatile__ (
-      // Invalidate each line of the I cache containing the target data.
-      //
-      // ic      : Instruction Cache maintenance
-      //    i    : Invalidate
-      //     va  : by Address
-      //       u : to the point of Unification
-      "   ic   ivau, %[iline]\n"
-      :
-      : [iline] "r" (iline)
-      : "memory");
+    __asm__ __volatile__(
+        // Invalidate each line of the I cache containing the target data.
+        //
+        // ic      : Instruction Cache maintenance
+        //    i    : Invalidate
+        //     va  : by Address
+        //       u : to the point of Unification
+        "   ic   ivau, %[iline]\n"
+        :
+        : [iline] "r"(iline)
+        : "memory");
     iline += isize;
   } while (iline < end);
 
-  __asm__ __volatile__ (
-    // Make sure that the instruction cache operations (above) take effect
-    // before the isb (below).
-    "   dsb  ish\n"
+  __asm__ __volatile__(
+      // Make sure that the instruction cache operations (above) take effect
+      // before the isb (below).
+      "   dsb  ish\n"
 
-    // Ensure that any instructions already in the pipeline are discarded and
-    // reloaded from the new data.
-    // isb : Instruction Synchronisation Barrier
-    "   isb\n"
-    : : : "memory");
+      // Ensure that any instructions already in the pipeline are discarded and
+      // reloaded from the new data.
+      // isb : Instruction Synchronisation Barrier
+      "   isb\n"
+      :
+      :
+      : "memory");
 #else
   // If the host isn't AArch64, we must be using the simulator, so this function
   // doesn't have to do anything.
diff --git a/src/vixl/a64/debugger-a64.cc b/src/vixl/a64/debugger-a64.cc
index 359e51b..970b5d3 100644
--- a/src/vixl/a64/debugger-a64.cc
+++ b/src/vixl/a64/debugger-a64.cc
@@ -31,13 +31,13 @@
 namespace vixl {
 
 // List of commands supported by the debugger.
-#define DEBUG_COMMAND_LIST(C)  \
-C(HelpCommand)                 \
-C(ContinueCommand)             \
-C(StepCommand)                 \
-C(DisasmCommand)               \
-C(PrintCommand)                \
-C(ExamineCommand)
+#define DEBUG_COMMAND_LIST(C) \
+  C(HelpCommand)              \
+  C(ContinueCommand)          \
+  C(StepCommand)              \
+  C(DisasmCommand)            \
+  C(PrintCommand)             \
+  C(ExamineCommand)
 
 // Debugger command lines are broken up in token of different type to make
 // processing easier later on.
@@ -62,7 +62,8 @@
 };
 
 // Tokens often hold one value.
-template<typename T> class ValueToken : public Token {
+template <typename T>
+class ValueToken : public Token {
  public:
   explicit ValueToken(T value) : value_(value) {}
   ValueToken() {}
@@ -88,7 +89,7 @@
   virtual bool IsRegister() const { return true; }
   virtual bool CanAddressMemory() const { return value().Is64Bits(); }
   virtual uint8_t* ToAddress(Debugger* debugger) const;
-  virtual void Print(FILE* out = stdout) const ;
+  virtual void Print(FILE* out = stdout) const;
   const char* Name() const;
 
   static Token* Tokenize(const char* arg);
@@ -111,7 +112,7 @@
       : ValueToken<const FPRegister>(fpreg) {}
 
   virtual bool IsFPRegister() const { return true; }
-  virtual void Print(FILE* out = stdout) const ;
+  virtual void Print(FILE* out = stdout) const;
 
   static Token* Tokenize(const char* arg);
   static FPRegisterToken* Cast(Token* tok) {
@@ -153,7 +154,7 @@
   virtual bool IsAddress() const { return true; }
   virtual bool CanAddressMemory() const { return true; }
   virtual uint8_t* ToAddress(Debugger* debugger) const;
-  virtual void Print(FILE* out = stdout) const ;
+  virtual void Print(FILE* out = stdout) const;
 
   static Token* Tokenize(const char* arg);
   static AddressToken* Cast(Token* tok) {
@@ -212,7 +213,8 @@
 };
 
 
-template<typename T> class Format : public FormatToken {
+template <typename T>
+class Format : public FormatToken {
  public:
   Format(const char* fmt, char type_code) : fmt_(fmt), type_code_(type_code) {}
 
@@ -263,7 +265,7 @@
   const char* name() { return name_->value(); }
   // Run the command on the given debugger. The command returns true if
   // execution should move to the next instruction.
-  virtual bool Run(Debugger * debugger) = 0;
+  virtual bool Run(Debugger* debugger) = 0;
   virtual void Print(FILE* out = stdout);
 
   static bool Match(const char* name, const char** aliases);
@@ -419,121 +421,116 @@
   const char* cause_;
 };
 
-const char* HelpCommand::kAliases[] = { "help", NULL };
+const char* HelpCommand::kAliases[] = {"help", NULL};
 const char* HelpCommand::kArguments = NULL;
 const char* HelpCommand::kHelp = "  Print this help.";
 
-const char* ContinueCommand::kAliases[] = { "continue", "c", NULL };
+const char* ContinueCommand::kAliases[] = {"continue", "c", NULL};
 const char* ContinueCommand::kArguments = NULL;
 const char* ContinueCommand::kHelp = "  Resume execution.";
 
-const char* StepCommand::kAliases[] = { "stepi", "si", NULL };
+const char* StepCommand::kAliases[] = {"stepi", "si", NULL};
 const char* StepCommand::kArguments = "[n = 1]";
 const char* StepCommand::kHelp = "  Execute n next instruction(s).";
 
-const char* DisasmCommand::kAliases[] = { "disasm", "di", NULL };
+const char* DisasmCommand::kAliases[] = {"disasm", "di", NULL};
 const char* DisasmCommand::kArguments = "[n = 10]";
 const char* DisasmCommand::kHelp =
-  "  Disassemble n instruction(s) at pc.\n"
-  "  This command is equivalent to x pc.i [n = 10]."
-;
+    "  Disassemble n instruction(s) at pc.\n"
+    "  This command is equivalent to x pc.i [n = 10].";
 
-const char* PrintCommand::kAliases[] = { "print", "p", NULL };
-const char* PrintCommand::kArguments =  "<entity>[.format]";
+const char* PrintCommand::kAliases[] = {"print", "p", NULL};
+const char* PrintCommand::kArguments = "<entity>[.format]";
 const char* PrintCommand::kHelp =
-  "  Print the given entity according to the given format.\n"
-  "  The format parameter only affects individual registers; it is ignored\n"
-  "  for other entities.\n"
-  "  <entity> can be one of the following:\n"
-  "   * A register name (such as x0, s1, ...).\n"
-  "   * 'regs', to print all integer (W and X) registers.\n"
-  "   * 'fpregs' to print all floating-point (S and D) registers.\n"
-  "   * 'sysregs' to print all system registers (including NZCV).\n"
-  "   * 'pc' to print the current program counter.\n"
-;
+    "  Print the given entity according to the given format.\n"
+    "  The format parameter only affects individual registers; it is ignored\n"
+    "  for other entities.\n"
+    "  <entity> can be one of the following:\n"
+    "   * A register name (such as x0, s1, ...).\n"
+    "   * 'regs', to print all integer (W and X) registers.\n"
+    "   * 'fpregs' to print all floating-point (S and D) registers.\n"
+    "   * 'sysregs' to print all system registers (including NZCV).\n"
+    "   * 'pc' to print the current program counter.\n";
 
-const char* ExamineCommand::kAliases[] = { "m", "mem", "x", NULL };
+const char* ExamineCommand::kAliases[] = {"m", "mem", "x", NULL};
 const char* ExamineCommand::kArguments = "<addr>[.format] [n = 10]";
 const char* ExamineCommand::kHelp =
-  "  Examine memory. Print n items of memory at address <addr> according to\n"
-  "  the given [.format].\n"
-  "  Addr can be an immediate address, a register name or pc.\n"
-  "  Format is made of a type letter: 'x' (hexadecimal), 's' (signed), 'u'\n"
-  "  (unsigned), 'f' (floating point), i (instruction) and a size in bits\n"
-  "  when appropriate (8, 16, 32, 64)\n"
-  "  E.g 'x sp.x64' will print 10 64-bit words from the stack in\n"
-  "  hexadecimal format."
-;
+    "  Examine memory. Print n items of memory at address <addr> according to\n"
+    "  the given [.format].\n"
+    "  Addr can be an immediate address, a register name or pc.\n"
+    "  Format is made of a type letter: 'x' (hexadecimal), 's' (signed), 'u'\n"
+    "  (unsigned), 'f' (floating point), i (instruction) and a size in bits\n"
+    "  when appropriate (8, 16, 32, 64)\n"
+    "  E.g 'x sp.x64' will print 10 64-bit words from the stack in\n"
+    "  hexadecimal format.";
 
-const char* RegisterToken::kXAliases[kNumberOfRegisters][kMaxAliasNumber] = {
-  { "x0", NULL },
-  { "x1", NULL },
-  { "x2", NULL },
-  { "x3", NULL },
-  { "x4", NULL },
-  { "x5", NULL },
-  { "x6", NULL },
-  { "x7", NULL },
-  { "x8", NULL },
-  { "x9", NULL },
-  { "x10", NULL },
-  { "x11", NULL },
-  { "x12", NULL },
-  { "x13", NULL },
-  { "x14", NULL },
-  { "x15", NULL },
-  { "ip0", "x16", NULL },
-  { "ip1", "x17", NULL },
-  { "x18", "pr", NULL },
-  { "x19", NULL },
-  { "x20", NULL },
-  { "x21", NULL },
-  { "x22", NULL },
-  { "x23", NULL },
-  { "x24", NULL },
-  { "x25", NULL },
-  { "x26", NULL },
-  { "x27", NULL },
-  { "x28", NULL },
-  { "fp", "x29", NULL },
-  { "lr", "x30", NULL },
-  { "sp", NULL}
-};
+const char* RegisterToken::kXAliases[kNumberOfRegisters][kMaxAliasNumber] =
+    {{"x0", NULL},
+     {"x1", NULL},
+     {"x2", NULL},
+     {"x3", NULL},
+     {"x4", NULL},
+     {"x5", NULL},
+     {"x6", NULL},
+     {"x7", NULL},
+     {"x8", NULL},
+     {"x9", NULL},
+     {"x10", NULL},
+     {"x11", NULL},
+     {"x12", NULL},
+     {"x13", NULL},
+     {"x14", NULL},
+     {"x15", NULL},
+     {"ip0", "x16", NULL},
+     {"ip1", "x17", NULL},
+     {"x18", "pr", NULL},
+     {"x19", NULL},
+     {"x20", NULL},
+     {"x21", NULL},
+     {"x22", NULL},
+     {"x23", NULL},
+     {"x24", NULL},
+     {"x25", NULL},
+     {"x26", NULL},
+     {"x27", NULL},
+     {"x28", NULL},
+     {"fp", "x29", NULL},
+     {"lr", "x30", NULL},
+     {"sp", NULL}};
 
-const char* RegisterToken::kWAliases[kNumberOfRegisters][kMaxAliasNumber] = {
-  { "w0", NULL },
-  { "w1", NULL },
-  { "w2", NULL },
-  { "w3", NULL },
-  { "w4", NULL },
-  { "w5", NULL },
-  { "w6", NULL },
-  { "w7", NULL },
-  { "w8", NULL },
-  { "w9", NULL },
-  { "w10", NULL },
-  { "w11", NULL },
-  { "w12", NULL },
-  { "w13", NULL },
-  { "w14", NULL },
-  { "w15", NULL },
-  { "w16", NULL },
-  { "w17", NULL },
-  { "w18", NULL },
-  { "w19", NULL },
-  { "w20", NULL },
-  { "w21", NULL },
-  { "w22", NULL },
-  { "w23", NULL },
-  { "w24", NULL },
-  { "w25", NULL },
-  { "w26", NULL },
-  { "w27", NULL },
-  { "w28", NULL },
-  { "w29", NULL },
-  { "w30", NULL },
-  { "wsp", NULL }
-};
+const char* RegisterToken::kWAliases[kNumberOfRegisters][kMaxAliasNumber] =
+    {{"w0", NULL},
+     {"w1", NULL},
+     {"w2", NULL},
+     {"w3", NULL},
+     {"w4", NULL},
+     {"w5", NULL},
+     {"w6", NULL},
+     {"w7", NULL},
+     {"w8", NULL},
+     {"w9", NULL},
+     {"w10", NULL},
+     {"w11", NULL},
+     {"w12", NULL},
+     {"w13", NULL},
+     {"w14", NULL},
+     {"w15", NULL},
+     {"w16", NULL},
+     {"w17", NULL},
+     {"w18", NULL},
+     {"w19", NULL},
+     {"w20", NULL},
+     {"w21", NULL},
+     {"w22", NULL},
+     {"w23", NULL},
+     {"w24", NULL},
+     {"w25", NULL},
+     {"w26", NULL},
+     {"w27", NULL},
+     {"w28", NULL},
+     {"w29", NULL},
+     {"w30", NULL},
+     {"wsp", NULL}};
 
 
 Debugger::Debugger(Decoder* decoder, FILE* stream)
@@ -554,11 +551,13 @@
 
 
 void Debugger::Run() {
-  pc_modified_ = false;
+  // Flush any written registers before executing anything, so that
+  // manually-set registers are logged _before_ the first instruction.
+  LogAllWrittenRegisters();
+
   while (pc_ != kEndOfSimAddress) {
     if (pending_request()) RunDebuggerShell();
     ExecuteInstruction();
-    LogAllWrittenRegisters();
   }
 }
 
@@ -575,8 +574,7 @@
   }
   const Instruction* to = from + count * kInstructionSize;
 
-  for (const Instruction* current = from;
-       current < to;
+  for (const Instruction* current = from; current < to;
        current = current->NextInstruction()) {
     printer_->Decode(current);
   }
@@ -600,7 +598,7 @@
 
   for (const uint8_t* current = from; current < to; current += size) {
     if (((current - from) % 8) == 0) {
-      printf("\n%p: ", current);
+      printf("\n%p: ", reinterpret_cast<const void*>(current));
     }
 
     uint64_t data = Memory::Read<uint64_t>(current);
@@ -618,8 +616,8 @@
   const uint64_t format_size = format->SizeOf() * 8;
   const uint64_t count = reg_size / format_size;
   const uint64_t mask = 0xffffffffffffffff >> (64 - format_size);
-  const uint64_t reg_value = reg<uint64_t>(target_reg.code(),
-                                           Reg31IsStackPointer);
+  const uint64_t reg_value =
+      reg<uint64_t>(target_reg.code(), Reg31IsStackPointer);
   VIXL_ASSERT(count > 0);
 
   printf("%s = ", name);
@@ -665,7 +663,8 @@
       return;
     case HLT:
       VIXL_FALLTHROUGH();
-    default: Simulator::VisitException(instr);
+    default:
+      Simulator::VisitException(instr);
   }
 }
 
@@ -917,7 +916,8 @@
         case 'd':
           fpreg = VRegister::DRegFromCode(static_cast<unsigned>(code));
           break;
-        default: VIXL_UNREACHABLE();
+        default:
+          VIXL_UNREACHABLE();
       }
 
       return new FPRegisterToken(fpreg);
@@ -965,7 +965,7 @@
 
 
 void AddressToken::Print(FILE* out) const {
-  fprintf(out, "[Address %p]", value());
+  fprintf(out, "[Address %p]", reinterpret_cast<const void*>(value()));
 }
 
 
@@ -1011,7 +1011,8 @@
     case 'i':
       if (length == 1) return new Format<uint32_t>("%08" PRIx32, 'i');
       VIXL_FALLTHROUGH();
-    default: return NULL;
+    default:
+      return NULL;
   }
 
   char* endptr = NULL;
@@ -1036,33 +1037,51 @@
   switch (arg[0]) {
     case 'x':
       switch (count) {
-        case 8: return new Format<uint8_t>("%02" PRIx8, 'x');
-        case 16: return new Format<uint16_t>("%04" PRIx16, 'x');
-        case 32: return new Format<uint32_t>("%08" PRIx32, 'x');
-        case 64: return new Format<uint64_t>("%016" PRIx64, 'x');
-        default: return NULL;
+        case 8:
+          return new Format<uint8_t>("%02" PRIx8, 'x');
+        case 16:
+          return new Format<uint16_t>("%04" PRIx16, 'x');
+        case 32:
+          return new Format<uint32_t>("%08" PRIx32, 'x');
+        case 64:
+          return new Format<uint64_t>("%016" PRIx64, 'x');
+        default:
+          return NULL;
       }
     case 's':
       switch (count) {
-        case 8: return new Format<int8_t>("%4" PRId8, 's');
-        case 16: return new Format<int16_t>("%6" PRId16, 's');
-        case 32: return new Format<int32_t>("%11" PRId32, 's');
-        case 64: return new Format<int64_t>("%20" PRId64, 's');
-        default: return NULL;
+        case 8:
+          return new Format<int8_t>("%4" PRId8, 's');
+        case 16:
+          return new Format<int16_t>("%6" PRId16, 's');
+        case 32:
+          return new Format<int32_t>("%11" PRId32, 's');
+        case 64:
+          return new Format<int64_t>("%20" PRId64, 's');
+        default:
+          return NULL;
       }
     case 'u':
       switch (count) {
-        case 8: return new Format<uint8_t>("%3" PRIu8, 'u');
-        case 16: return new Format<uint16_t>("%5" PRIu16, 'u');
-        case 32: return new Format<uint32_t>("%10" PRIu32, 'u');
-        case 64: return new Format<uint64_t>("%20" PRIu64, 'u');
-        default: return NULL;
+        case 8:
+          return new Format<uint8_t>("%3" PRIu8, 'u');
+        case 16:
+          return new Format<uint16_t>("%5" PRIu16, 'u');
+        case 32:
+          return new Format<uint32_t>("%10" PRIu32, 'u');
+        case 64:
+          return new Format<uint64_t>("%20" PRIu64, 'u');
+        default:
+          return NULL;
       }
     case 'f':
       switch (count) {
-        case 32: return new Format<float>("%13g", 'f');
-        case 64: return new Format<double>("%13g", 'f');
-        default: return NULL;
+        case 32:
+          return new Format<float>("%13g", 'f');
+        case 64:
+          return new Format<double>("%13g", 'f');
+        default:
+          return NULL;
       }
     default:
       VIXL_UNREACHABLE();
@@ -1071,7 +1090,7 @@
 }
 
 
-template<typename T>
+template <typename T>
 void Format<T>::Print(FILE* out) const {
   unsigned size = sizeof(T) * 8;
   fprintf(out, "[Format %c%u - %s]", type_code_, size, fmt_);
@@ -1083,15 +1102,13 @@
 }
 
 
-void DebugCommand::Print(FILE* out) {
-  fprintf(out, "%s", name());
-}
+void DebugCommand::Print(FILE* out) { fprintf(out, "%s", name()); }
 
 
 bool DebugCommand::Match(const char* name, const char** aliases) {
   for (const char** current = aliases; *current != NULL; current++) {
     if (strcmp(name, *current) == 0) {
-       return true;
+      return true;
     }
   }
 
@@ -1102,8 +1119,7 @@
 DebugCommand* DebugCommand::Parse(char* line) {
   std::vector<Token*> args;
 
-  for (char* chunk = strtok(line, " \t");
-       chunk != NULL;
+  for (char* chunk = strtok(line, " \t"); chunk != NULL;
        chunk = strtok(NULL, " \t")) {
     char* dot = strchr(chunk, '.');
     if (dot != NULL) {
@@ -1132,12 +1148,12 @@
   }
 
   const char* name = IdentifierToken::Cast(args[0])->value();
-  #define RETURN_IF_MATCH(Command)       \
-  if (Match(name, Command::kAliases)) {  \
-    return Command::Build(args);         \
+#define RETURN_IF_MATCH(Command)        \
+  if (Match(name, Command::kAliases)) { \
+    return Command::Build(args);        \
   }
   DEBUG_COMMAND_LIST(RETURN_IF_MATCH);
-  #undef RETURN_IF_MATCH
+#undef RETURN_IF_MATCH
 
   return new UnknownCommand(args);
 }
@@ -1165,12 +1181,12 @@
   VIXL_ASSERT(debugger->IsDebuggerRunning());
   USE(debugger);
 
-  #define PRINT_HELP(Command)                     \
-    DebugCommand::PrintHelp(Command::kAliases,    \
-                            Command::kArguments,  \
-                            Command::kHelp);
+#define PRINT_HELP(Command)                    \
+  DebugCommand::PrintHelp(Command::kAliases,   \
+                          Command::kArguments, \
+                          Command::kHelp);
   DEBUG_COMMAND_LIST(PRINT_HELP);
-  #undef PRINT_HELP
+#undef PRINT_HELP
   printf("\n----\n\n");
 
   return false;
@@ -1331,8 +1347,7 @@
   }
 
   Token* target = args[1];
-  if (!target->IsRegister() &&
-      !target->IsFPRegister() &&
+  if (!target->IsRegister() && !target->IsFPRegister() &&
       !target->IsIdentifier()) {
     return new InvalidCommand(args, 1, "expects reg or identifier");
   }
@@ -1353,23 +1368,34 @@
     case 2: {
       if (target->IsRegister()) {
         switch (target_size) {
-          case 4: format = new Format<uint32_t>("%08" PRIx32, 'x'); break;
-          case 8: format = new Format<uint64_t>("%016" PRIx64, 'x'); break;
-          default: VIXL_UNREACHABLE();
+          case 4:
+            format = new Format<uint32_t>("%08" PRIx32, 'x');
+            break;
+          case 8:
+            format = new Format<uint64_t>("%016" PRIx64, 'x');
+            break;
+          default:
+            VIXL_UNREACHABLE();
         }
       } else if (target->IsFPRegister()) {
         switch (target_size) {
-          case 4: format = new Format<float>("%8g", 'f'); break;
-          case 8: format = new Format<double>("%8g", 'f'); break;
-          default: VIXL_UNREACHABLE();
+          case 4:
+            format = new Format<float>("%8g", 'f');
+            break;
+          case 8:
+            format = new Format<double>("%8g", 'f');
+            break;
+          default:
+            VIXL_UNREACHABLE();
         }
       }
       break;
     }
     case 3: {
       if (target->IsIdentifier()) {
-        return new InvalidCommand(args, 2,
-            "format is only allowed with registers");
+        return new InvalidCommand(args,
+                                  2,
+                                  "format is only allowed with registers");
       }
 
       Token* second = args[2];
@@ -1396,7 +1422,7 @@
   VIXL_ASSERT(debugger->IsDebuggerRunning());
 
   uint8_t* address = target()->ToAddress(debugger);
-  int64_t  amount = count()->value();
+  int64_t amount = count()->value();
   if (format()->type_code() == 'i') {
     debugger->PrintInstructions(address, amount);
   } else {
diff --git a/src/vixl/a64/debugger-a64.h b/src/vixl/a64/debugger-a64.h
index 16394f1..1ab8034 100644
--- a/src/vixl/a64/debugger-a64.h
+++ b/src/vixl/a64/debugger-a64.h
@@ -45,7 +45,7 @@
 enum DebugParameters {
   DBG_INACTIVE = 0,
   DBG_ACTIVE = 1 << 0,  // The debugger is active.
-  DBG_BREAK  = 1 << 1   // The debugger is at a breakpoint.
+  DBG_BREAK = 1 << 1    // The debugger is at a breakpoint.
 };
 
 // Forward declarations.
@@ -81,9 +81,7 @@
   }
 
   bool pending_request() const { return pending_request_; }
-  void update_pending_request() {
-    pending_request_ = IsDebuggerRunning();
-  }
+  void update_pending_request() { pending_request_ = IsDebuggerRunning(); }
 
   void PrintInstructions(const void* address, int64_t count = 1);
   void PrintMemory(const uint8_t* address,
diff --git a/src/vixl/a64/decoder-a64.cc b/src/vixl/a64/decoder-a64.cc
index 5ba2d3c..307b427 100644
--- a/src/vixl/a64/decoder-a64.cc
+++ b/src/vixl/a64/decoder-a64.cc
@@ -30,16 +30,20 @@
 
 namespace vixl {
 
-void Decoder::DecodeInstruction(const Instruction *instr) {
+void Decoder::DecodeInstruction(const Instruction* instr) {
   if (instr->Bits(28, 27) == 0) {
     VisitUnallocated(instr);
   } else {
     switch (instr->Bits(27, 24)) {
       // 0:   PC relative addressing.
-      case 0x0: DecodePCRelAddressing(instr); break;
+      case 0x0:
+        DecodePCRelAddressing(instr);
+        break;
 
       // 1:   Add/sub immediate.
-      case 0x1: DecodeAddSubImmediate(instr); break;
+      case 0x1:
+        DecodeAddSubImmediate(instr);
+        break;
 
       // A:   Logical shifted register.
       //      Add/sub with carry.
@@ -52,15 +56,21 @@
       //      Add/sub extended register.
       //      Data processing 3 source.
       case 0xA:
-      case 0xB: DecodeDataProcessing(instr); break;
+      case 0xB:
+        DecodeDataProcessing(instr);
+        break;
 
       // 2:   Logical immediate.
       //      Move wide immediate.
-      case 0x2: DecodeLogical(instr); break;
+      case 0x2:
+        DecodeLogical(instr);
+        break;
 
       // 3:   Bitfield.
       //      Extract.
-      case 0x3: DecodeBitfieldExtract(instr); break;
+      case 0x3:
+        DecodeBitfieldExtract(instr);
+        break;
 
       // 4:   Unconditional branch immediate.
       //      Exception generation.
@@ -73,7 +83,9 @@
       case 0x4:
       case 0x5:
       case 0x6:
-      case 0x7: DecodeBranchSystemException(instr); break;
+      case 0x7:
+        DecodeBranchSystemException(instr);
+        break;
 
       // 8,9: Load/store register pair post-index.
       //      Load register literal.
@@ -89,7 +101,9 @@
       case 0x8:
       case 0x9:
       case 0xC:
-      case 0xD: DecodeLoadStore(instr); break;
+      case 0xD:
+        DecodeLoadStore(instr);
+        break;
 
       // E:   FP fixed point conversion.
       //      FP integer conversion.
@@ -103,7 +117,9 @@
       // F:   FP data processing 3 source.
       //      Advanced SIMD.
       case 0xE:
-      case 0xF: DecodeFP(instr); break;
+      case 0xF:
+        DecodeFP(instr);
+        break;
     }
   }
 }
@@ -166,10 +182,8 @@
 
 
 void Decoder::DecodeBranchSystemException(const Instruction* instr) {
-  VIXL_ASSERT((instr->Bits(27, 24) == 0x4) ||
-              (instr->Bits(27, 24) == 0x5) ||
-              (instr->Bits(27, 24) == 0x6) ||
-              (instr->Bits(27, 24) == 0x7) );
+  VIXL_ASSERT((instr->Bits(27, 24) == 0x4) || (instr->Bits(27, 24) == 0x5) ||
+              (instr->Bits(27, 24) == 0x6) || (instr->Bits(27, 24) == 0x7));
 
   switch (instr->Bits(31, 29)) {
     case 0:
@@ -244,12 +258,9 @@
           }
         }
       } else {
-        if ((instr->Bit(24) == 0x1) ||
-            (instr->Bits(20, 16) != 0x1F) ||
-            (instr->Bits(15, 10) != 0) ||
-            (instr->Bits(4, 0) != 0) ||
-            (instr->Bits(24, 21) == 0x3) ||
-            (instr->Bits(24, 22) == 0x3)) {
+        if ((instr->Bit(24) == 0x1) || (instr->Bits(20, 16) != 0x1F) ||
+            (instr->Bits(15, 10) != 0) || (instr->Bits(4, 0) != 0) ||
+            (instr->Bits(24, 21) == 0x3) || (instr->Bits(24, 22) == 0x3)) {
           VisitUnallocated(instr);
         } else {
           VisitUnconditionalBranchToRegister(instr);
@@ -267,10 +278,8 @@
 
 
 void Decoder::DecodeLoadStore(const Instruction* instr) {
-  VIXL_ASSERT((instr->Bits(27, 24) == 0x8) ||
-              (instr->Bits(27, 24) == 0x9) ||
-              (instr->Bits(27, 24) == 0xC) ||
-              (instr->Bits(27, 24) == 0xD) );
+  VIXL_ASSERT((instr->Bits(27, 24) == 0x8) || (instr->Bits(27, 24) == 0x9) ||
+              (instr->Bits(27, 24) == 0xC) || (instr->Bits(27, 24) == 0xD));
   // TODO(all): rearrange the tree to integrate this branch.
   if ((instr->Bit(28) == 0) && (instr->Bit(29) == 0) && (instr->Bit(26) == 1)) {
     DecodeNEONLoadStore(instr);
@@ -444,8 +453,7 @@
 
 
 void Decoder::DecodeDataProcessing(const Instruction* instr) {
-  VIXL_ASSERT((instr->Bits(27, 24) == 0xA) ||
-              (instr->Bits(27, 24) == 0xB));
+  VIXL_ASSERT((instr->Bits(27, 24) == 0xA) || (instr->Bits(27, 24) == 0xB));
 
   if (instr->Bit(24) == 0) {
     if (instr->Bit(28) == 0) {
@@ -465,8 +473,7 @@
           break;
         }
         case 2: {
-          if ((instr->Bit(29) == 0) ||
-              (instr->Mask(0x00000410) != 0)) {
+          if ((instr->Bit(29) == 0) || (instr->Mask(0x00000410) != 0)) {
             VisitUnallocated(instr);
           } else {
             if (instr->Bit(11) == 0) {
@@ -491,8 +498,7 @@
             VIXL_FALLTHROUGH();
           } else {
             if (instr->Bit(30) == 0) {
-              if ((instr->Bit(15) == 0x1) ||
-                  (instr->Bits(15, 11) == 0) ||
+              if ((instr->Bit(15) == 0x1) || (instr->Bits(15, 11) == 0) ||
                   (instr->Bits(15, 12) == 0x1) ||
                   (instr->Bits(15, 12) == 0x3) ||
                   (instr->Bits(15, 13) == 0x3) ||
@@ -504,8 +510,7 @@
                 VisitDataProcessing2Source(instr);
               }
             } else {
-              if ((instr->Bit(13) == 1) ||
-                  (instr->Bits(20, 16) != 0) ||
+              if ((instr->Bit(13) == 1) || (instr->Bits(20, 16) != 0) ||
                   (instr->Bits(15, 14) != 0) ||
                   (instr->Mask(0xA01FFC00) == 0x00000C00) ||
                   (instr->Mask(0x201FF800) == 0x00001800)) {
@@ -520,12 +525,14 @@
         case 1:
         case 3:
         case 5:
-        case 7: VisitUnallocated(instr); break;
+        case 7:
+          VisitUnallocated(instr);
+          break;
       }
     }
   } else {
     if (instr->Bit(28) == 0) {
-     if (instr->Bit(21) == 0) {
+      if (instr->Bit(21) == 0) {
         if ((instr->Bits(23, 22) == 0x3) ||
             (instr->Mask(0x80008000) == 0x00008000)) {
           VisitUnallocated(instr);
@@ -542,8 +549,7 @@
         }
       }
     } else {
-      if ((instr->Bit(30) == 0x1) ||
-          (instr->Bits(30, 29) == 0x1) ||
+      if ((instr->Bit(30) == 0x1) || (instr->Bits(30, 29) == 0x1) ||
           (instr->Mask(0xE0600000) == 0x00200000) ||
           (instr->Mask(0xE0608000) == 0x00400000) ||
           (instr->Mask(0x60608000) == 0x00408000) ||
@@ -560,8 +566,7 @@
 
 
 void Decoder::DecodeFP(const Instruction* instr) {
-  VIXL_ASSERT((instr->Bits(27, 24) == 0xE) ||
-              (instr->Bits(27, 24) == 0xF));
+  VIXL_ASSERT((instr->Bits(27, 24) == 0xE) || (instr->Bits(27, 24) == 0xF));
   if (instr->Bit(28) == 0) {
     DecodeNEONVectorDataProcessing(instr);
   } else {
@@ -573,8 +578,7 @@
       if (instr->Bit(29) == 0) {
         if (instr->Bit(24) == 0) {
           if (instr->Bit(21) == 0) {
-            if ((instr->Bit(23) == 1) ||
-                (instr->Bit(18) == 1) ||
+            if ((instr->Bit(23) == 1) || (instr->Bit(18) == 1) ||
                 (instr->Mask(0x80008000) == 0x00000000) ||
                 (instr->Mask(0x000E0000) == 0x00000000) ||
                 (instr->Mask(0x000E0000) == 0x000A0000) ||
@@ -626,8 +630,7 @@
                 VisitFPDataProcessing1Source(instr);
               }
             } else if (instr->Bits(13, 10) == 8) {
-              if ((instr->Bits(15, 14) != 0) ||
-                  (instr->Bits(2, 0) != 0) ||
+              if ((instr->Bits(15, 14) != 0) || (instr->Bits(2, 0) != 0) ||
                   (instr->Mask(0x80800000) != 0x00000000)) {
                 VisitUnallocated(instr);
               } else {
@@ -663,7 +666,8 @@
                     VisitFPConditionalSelect(instr);
                     break;
                   }
-                  default: VIXL_UNREACHABLE();
+                  default:
+                    VIXL_UNREACHABLE();
                 }
               }
             }
@@ -864,13 +868,13 @@
 }
 
 
-#define DEFINE_VISITOR_CALLERS(A)                                              \
-  void Decoder::Visit##A(const Instruction *instr) {                           \
-    VIXL_ASSERT(instr->Mask(A##FMask) == A##Fixed);                            \
-    std::list<DecoderVisitor*>::iterator it;                                   \
-    for (it = visitors_.begin(); it != visitors_.end(); it++) {                \
-      (*it)->Visit##A(instr);                                                  \
-    }                                                                          \
+#define DEFINE_VISITOR_CALLERS(A)                               \
+  void Decoder::Visit##A(const Instruction* instr) {            \
+    VIXL_ASSERT(instr->Mask(A##FMask) == A##Fixed);             \
+    std::list<DecoderVisitor*>::iterator it;                    \
+    for (it = visitors_.begin(); it != visitors_.end(); it++) { \
+      (*it)->Visit##A(instr);                                   \
+    }                                                           \
   }
 VISITOR_LIST(DEFINE_VISITOR_CALLERS)
 #undef DEFINE_VISITOR_CALLERS
diff --git a/src/vixl/a64/decoder-a64.h b/src/vixl/a64/decoder-a64.h
index b3f04f6..a0715b2 100644
--- a/src/vixl/a64/decoder-a64.h
+++ b/src/vixl/a64/decoder-a64.h
@@ -35,83 +35,83 @@
 
 // List macro containing all visitors needed by the decoder class.
 
-#define VISITOR_LIST_THAT_RETURN(V) \
-  V(PCRelAddressing)                \
-  V(AddSubImmediate)                \
-  V(LogicalImmediate)               \
-  V(MoveWideImmediate)              \
-  V(Bitfield)                       \
-  V(Extract)                        \
-  V(UnconditionalBranch)            \
-  V(UnconditionalBranchToRegister)  \
-  V(CompareBranch)                  \
-  V(TestBranch)                     \
-  V(ConditionalBranch)              \
-  V(System)                         \
-  V(Exception)                      \
-  V(LoadStorePairPostIndex)         \
-  V(LoadStorePairOffset)            \
-  V(LoadStorePairPreIndex)          \
-  V(LoadStorePairNonTemporal)       \
-  V(LoadLiteral)                    \
-  V(LoadStoreUnscaledOffset)        \
-  V(LoadStorePostIndex)             \
-  V(LoadStorePreIndex)              \
-  V(LoadStoreRegisterOffset)        \
-  V(LoadStoreUnsignedOffset)        \
-  V(LoadStoreExclusive)             \
-  V(LogicalShifted)                 \
-  V(AddSubShifted)                  \
-  V(AddSubExtended)                 \
-  V(AddSubWithCarry)                \
-  V(ConditionalCompareRegister)     \
-  V(ConditionalCompareImmediate)    \
-  V(ConditionalSelect)              \
-  V(DataProcessing1Source)          \
-  V(DataProcessing2Source)          \
-  V(DataProcessing3Source)          \
-  V(FPCompare)                      \
-  V(FPConditionalCompare)           \
-  V(FPConditionalSelect)            \
-  V(FPImmediate)                    \
-  V(FPDataProcessing1Source)        \
-  V(FPDataProcessing2Source)        \
-  V(FPDataProcessing3Source)        \
-  V(FPIntegerConvert)               \
-  V(FPFixedPointConvert)            \
-  V(Crypto2RegSHA)                  \
-  V(Crypto3RegSHA)                  \
-  V(CryptoAES)                      \
-  V(NEON2RegMisc)                   \
-  V(NEON3Different)                 \
-  V(NEON3Same)                      \
-  V(NEONAcrossLanes)                \
-  V(NEONByIndexedElement)           \
-  V(NEONCopy)                       \
-  V(NEONExtract)                    \
-  V(NEONLoadStoreMultiStruct)       \
+#define VISITOR_LIST_THAT_RETURN(V)     \
+  V(PCRelAddressing)                    \
+  V(AddSubImmediate)                    \
+  V(LogicalImmediate)                   \
+  V(MoveWideImmediate)                  \
+  V(Bitfield)                           \
+  V(Extract)                            \
+  V(UnconditionalBranch)                \
+  V(UnconditionalBranchToRegister)      \
+  V(CompareBranch)                      \
+  V(TestBranch)                         \
+  V(ConditionalBranch)                  \
+  V(System)                             \
+  V(Exception)                          \
+  V(LoadStorePairPostIndex)             \
+  V(LoadStorePairOffset)                \
+  V(LoadStorePairPreIndex)              \
+  V(LoadStorePairNonTemporal)           \
+  V(LoadLiteral)                        \
+  V(LoadStoreUnscaledOffset)            \
+  V(LoadStorePostIndex)                 \
+  V(LoadStorePreIndex)                  \
+  V(LoadStoreRegisterOffset)            \
+  V(LoadStoreUnsignedOffset)            \
+  V(LoadStoreExclusive)                 \
+  V(LogicalShifted)                     \
+  V(AddSubShifted)                      \
+  V(AddSubExtended)                     \
+  V(AddSubWithCarry)                    \
+  V(ConditionalCompareRegister)         \
+  V(ConditionalCompareImmediate)        \
+  V(ConditionalSelect)                  \
+  V(DataProcessing1Source)              \
+  V(DataProcessing2Source)              \
+  V(DataProcessing3Source)              \
+  V(FPCompare)                          \
+  V(FPConditionalCompare)               \
+  V(FPConditionalSelect)                \
+  V(FPImmediate)                        \
+  V(FPDataProcessing1Source)            \
+  V(FPDataProcessing2Source)            \
+  V(FPDataProcessing3Source)            \
+  V(FPIntegerConvert)                   \
+  V(FPFixedPointConvert)                \
+  V(Crypto2RegSHA)                      \
+  V(Crypto3RegSHA)                      \
+  V(CryptoAES)                          \
+  V(NEON2RegMisc)                       \
+  V(NEON3Different)                     \
+  V(NEON3Same)                          \
+  V(NEONAcrossLanes)                    \
+  V(NEONByIndexedElement)               \
+  V(NEONCopy)                           \
+  V(NEONExtract)                        \
+  V(NEONLoadStoreMultiStruct)           \
   V(NEONLoadStoreMultiStructPostIndex)  \
-  V(NEONLoadStoreSingleStruct)      \
+  V(NEONLoadStoreSingleStruct)          \
   V(NEONLoadStoreSingleStructPostIndex) \
-  V(NEONModifiedImmediate)          \
-  V(NEONScalar2RegMisc)             \
-  V(NEONScalar3Diff)                \
-  V(NEONScalar3Same)                \
-  V(NEONScalarByIndexedElement)     \
-  V(NEONScalarCopy)                 \
-  V(NEONScalarPairwise)             \
-  V(NEONScalarShiftImmediate)       \
-  V(NEONShiftImmediate)             \
-  V(NEONTable)                      \
-  V(NEONPerm)                       \
+  V(NEONModifiedImmediate)              \
+  V(NEONScalar2RegMisc)                 \
+  V(NEONScalar3Diff)                    \
+  V(NEONScalar3Same)                    \
+  V(NEONScalarByIndexedElement)         \
+  V(NEONScalarCopy)                     \
+  V(NEONScalarPairwise)                 \
+  V(NEONScalarShiftImmediate)           \
+  V(NEONShiftImmediate)                 \
+  V(NEONTable)                          \
+  V(NEONPerm)
 
-#define VISITOR_LIST_THAT_DONT_RETURN(V)  \
-  V(Unallocated)                          \
-  V(Unimplemented)                        \
+#define VISITOR_LIST_THAT_DONT_RETURN(V) \
+  V(Unallocated)                         \
+  V(Unimplemented)
 
-#define VISITOR_LIST(V)             \
-  VISITOR_LIST_THAT_RETURN(V)       \
-  VISITOR_LIST_THAT_DONT_RETURN(V)  \
+#define VISITOR_LIST(V)       \
+  VISITOR_LIST_THAT_RETURN(V) \
+  VISITOR_LIST_THAT_DONT_RETURN(V)
 
 namespace vixl {
 
@@ -119,18 +119,15 @@
 // must provide implementations for all of these functions.
 class DecoderVisitor {
  public:
-  enum VisitorConstness {
-    kConstVisitor,
-    kNonConstVisitor
-  };
+  enum VisitorConstness { kConstVisitor, kNonConstVisitor };
   explicit DecoderVisitor(VisitorConstness constness = kConstVisitor)
       : constness_(constness) {}
 
   virtual ~DecoderVisitor() {}
 
-  #define DECLARE(A) virtual void Visit##A(const Instruction* instr) = 0;
+#define DECLARE(A) virtual void Visit##A(const Instruction* instr) = 0;
   VISITOR_LIST(DECLARE)
-  #undef DECLARE
+#undef DECLARE
 
   bool IsConstVisitor() const { return constness_ == kConstVisitor; }
   Instruction* MutableInstruction(const Instruction* instr) {
@@ -198,9 +195,9 @@
   // of visitors stored by the decoder.
   void RemoveVisitor(DecoderVisitor* visitor);
 
-  #define DECLARE(A) void Visit##A(const Instruction* instr);
+#define DECLARE(A) void Visit##A(const Instruction* instr);
   VISITOR_LIST(DECLARE)
-  #undef DECLARE
+#undef DECLARE
 
 
   std::list<DecoderVisitor*>* visitors() { return &visitors_; }
diff --git a/src/vixl/a64/disasm-a64.cc b/src/vixl/a64/disasm-a64.cc
index 20caba4..713927c 100644
--- a/src/vixl/a64/disasm-a64.cc
+++ b/src/vixl/a64/disasm-a64.cc
@@ -31,14 +31,14 @@
 
 Disassembler::Disassembler() {
   buffer_size_ = 256;
-  buffer_ = reinterpret_cast<char*>(malloc(buffer_size_));
+  buffer_ = reinterpret_cast<char *>(malloc(buffer_size_));
   buffer_pos_ = 0;
   own_buffer_ = true;
   code_address_offset_ = 0;
 }
 
 
-Disassembler::Disassembler(char* text_buffer, int buffer_size) {
+Disassembler::Disassembler(char *text_buffer, int buffer_size) {
   buffer_size_ = buffer_size;
   buffer_ = text_buffer;
   buffer_pos_ = 0;
@@ -54,15 +54,14 @@
 }
 
 
-char* Disassembler::GetOutput() {
-  return buffer_;
-}
+char *Disassembler::GetOutput() { return buffer_; }
 
 
-void Disassembler::VisitAddSubImmediate(const Instruction* instr) {
+void Disassembler::VisitAddSubImmediate(const Instruction *instr) {
   bool rd_is_zr = RdIsZROrSP(instr);
-  bool stack_op = (rd_is_zr || RnIsZROrSP(instr)) &&
-                  (instr->ImmAddSub() == 0) ? true : false;
+  bool stack_op = (rd_is_zr || RnIsZROrSP(instr)) && (instr->ImmAddSub() == 0)
+                      ? true
+                      : false;
   const char *mnemonic = "";
   const char *form = "'Rds, 'Rns, 'IAddSub";
   const char *form_cmp = "'Rns, 'IAddSub";
@@ -88,7 +87,9 @@
       break;
     }
     case SUB_w_imm:
-    case SUB_x_imm: mnemonic = "sub"; break;
+    case SUB_x_imm:
+      mnemonic = "sub";
+      break;
     case SUBS_w_imm:
     case SUBS_x_imm: {
       mnemonic = "subs";
@@ -98,13 +99,14 @@
       }
       break;
     }
-    default: VIXL_UNREACHABLE();
+    default:
+      VIXL_UNREACHABLE();
   }
   Format(instr, mnemonic, form);
 }
 
 
-void Disassembler::VisitAddSubShifted(const Instruction* instr) {
+void Disassembler::VisitAddSubShifted(const Instruction *instr) {
   bool rd_is_zr = RdIsZROrSP(instr);
   bool rn_is_zr = RnIsZROrSP(instr);
   const char *mnemonic = "";
@@ -114,7 +116,9 @@
 
   switch (instr->Mask(AddSubShiftedMask)) {
     case ADD_w_shift:
-    case ADD_x_shift: mnemonic = "add"; break;
+    case ADD_x_shift:
+      mnemonic = "add";
+      break;
     case ADDS_w_shift:
     case ADDS_x_shift: {
       mnemonic = "adds";
@@ -145,24 +149,27 @@
       }
       break;
     }
-    default: VIXL_UNREACHABLE();
+    default:
+      VIXL_UNREACHABLE();
   }
   Format(instr, mnemonic, form);
 }
 
 
-void Disassembler::VisitAddSubExtended(const Instruction* instr) {
+void Disassembler::VisitAddSubExtended(const Instruction *instr) {
   bool rd_is_zr = RdIsZROrSP(instr);
   const char *mnemonic = "";
   Extend mode = static_cast<Extend>(instr->ExtendMode());
-  const char *form = ((mode == UXTX) || (mode == SXTX)) ?
-                     "'Rds, 'Rns, 'Xm'Ext" : "'Rds, 'Rns, 'Wm'Ext";
-  const char *form_cmp = ((mode == UXTX) || (mode == SXTX)) ?
-                         "'Rns, 'Xm'Ext" : "'Rns, 'Wm'Ext";
+  const char *form = ((mode == UXTX) || (mode == SXTX)) ? "'Rds, 'Rns, 'Xm'Ext"
+                                                        : "'Rds, 'Rns, 'Wm'Ext";
+  const char *form_cmp =
+      ((mode == UXTX) || (mode == SXTX)) ? "'Rns, 'Xm'Ext" : "'Rns, 'Wm'Ext";
 
   switch (instr->Mask(AddSubExtendedMask)) {
     case ADD_w_ext:
-    case ADD_x_ext: mnemonic = "add"; break;
+    case ADD_x_ext:
+      mnemonic = "add";
+      break;
     case ADDS_w_ext:
     case ADDS_x_ext: {
       mnemonic = "adds";
@@ -173,7 +180,9 @@
       break;
     }
     case SUB_w_ext:
-    case SUB_x_ext: mnemonic = "sub"; break;
+    case SUB_x_ext:
+      mnemonic = "sub";
+      break;
     case SUBS_w_ext:
     case SUBS_x_ext: {
       mnemonic = "subs";
@@ -183,13 +192,14 @@
       }
       break;
     }
-    default: VIXL_UNREACHABLE();
+    default:
+      VIXL_UNREACHABLE();
   }
   Format(instr, mnemonic, form);
 }
 
 
-void Disassembler::VisitAddSubWithCarry(const Instruction* instr) {
+void Disassembler::VisitAddSubWithCarry(const Instruction *instr) {
   bool rn_is_zr = RnIsZROrSP(instr);
   const char *mnemonic = "";
   const char *form = "'Rd, 'Rn, 'Rm";
@@ -197,9 +207,13 @@
 
   switch (instr->Mask(AddSubWithCarryMask)) {
     case ADC_w:
-    case ADC_x: mnemonic = "adc"; break;
+    case ADC_x:
+      mnemonic = "adc";
+      break;
     case ADCS_w:
-    case ADCS_x: mnemonic = "adcs"; break;
+    case ADCS_x:
+      mnemonic = "adcs";
+      break;
     case SBC_w:
     case SBC_x: {
       mnemonic = "sbc";
@@ -218,13 +232,14 @@
       }
       break;
     }
-    default: VIXL_UNREACHABLE();
+    default:
+      VIXL_UNREACHABLE();
   }
   Format(instr, mnemonic, form);
 }
 
 
-void Disassembler::VisitLogicalImmediate(const Instruction* instr) {
+void Disassembler::VisitLogicalImmediate(const Instruction *instr) {
   bool rd_is_zr = RdIsZROrSP(instr);
   bool rn_is_zr = RnIsZROrSP(instr);
   const char *mnemonic = "";
@@ -238,12 +253,13 @@
 
   switch (instr->Mask(LogicalImmediateMask)) {
     case AND_w_imm:
-    case AND_x_imm: mnemonic = "and"; break;
+    case AND_x_imm:
+      mnemonic = "and";
+      break;
     case ORR_w_imm:
     case ORR_x_imm: {
       mnemonic = "orr";
-      unsigned reg_size = (instr->SixtyFourBits() == 1) ? kXRegSize
-                                                        : kWRegSize;
+      unsigned reg_size = (instr->SixtyFourBits() == 1) ? kXRegSize : kWRegSize;
       if (rn_is_zr && !IsMovzMovnImm(reg_size, instr->ImmLogical())) {
         mnemonic = "mov";
         form = "'Rds, 'ITri";
@@ -251,7 +267,9 @@
       break;
     }
     case EOR_w_imm:
-    case EOR_x_imm: mnemonic = "eor"; break;
+    case EOR_x_imm:
+      mnemonic = "eor";
+      break;
     case ANDS_w_imm:
     case ANDS_x_imm: {
       mnemonic = "ands";
@@ -261,7 +279,8 @@
       }
       break;
     }
-    default: VIXL_UNREACHABLE();
+    default:
+      VIXL_UNREACHABLE();
   }
   Format(instr, mnemonic, form);
 }
@@ -287,16 +306,15 @@
        ((~value & UINT64_C(0x0000ffffffffffff)) == 0))) {
     return true;
   }
-  if ((reg_size == kWRegSize) &&
-      (((value & 0xffff0000) == 0xffff0000) ||
-       ((value & 0x0000ffff) == 0x0000ffff))) {
+  if ((reg_size == kWRegSize) && (((value & 0xffff0000) == 0xffff0000) ||
+                                  ((value & 0x0000ffff) == 0x0000ffff))) {
     return true;
   }
   return false;
 }
 
 
-void Disassembler::VisitLogicalShifted(const Instruction* instr) {
+void Disassembler::VisitLogicalShifted(const Instruction *instr) {
   bool rd_is_zr = RdIsZROrSP(instr);
   bool rn_is_zr = RnIsZROrSP(instr);
   const char *mnemonic = "";
@@ -304,15 +322,25 @@
 
   switch (instr->Mask(LogicalShiftedMask)) {
     case AND_w:
-    case AND_x: mnemonic = "and"; break;
+    case AND_x:
+      mnemonic = "and";
+      break;
     case BIC_w:
-    case BIC_x: mnemonic = "bic"; break;
+    case BIC_x:
+      mnemonic = "bic";
+      break;
     case EOR_w:
-    case EOR_x: mnemonic = "eor"; break;
+    case EOR_x:
+      mnemonic = "eor";
+      break;
     case EON_w:
-    case EON_x: mnemonic = "eon"; break;
+    case EON_x:
+      mnemonic = "eon";
+      break;
     case BICS_w:
-    case BICS_x: mnemonic = "bics"; break;
+    case BICS_x:
+      mnemonic = "bics";
+      break;
     case ANDS_w:
     case ANDS_x: {
       mnemonic = "ands";
@@ -340,44 +368,55 @@
       }
       break;
     }
-    default: VIXL_UNREACHABLE();
+    default:
+      VIXL_UNREACHABLE();
   }
 
   Format(instr, mnemonic, form);
 }
 
 
-void Disassembler::VisitConditionalCompareRegister(const Instruction* instr) {
+void Disassembler::VisitConditionalCompareRegister(const Instruction *instr) {
   const char *mnemonic = "";
   const char *form = "'Rn, 'Rm, 'INzcv, 'Cond";
 
   switch (instr->Mask(ConditionalCompareRegisterMask)) {
     case CCMN_w:
-    case CCMN_x: mnemonic = "ccmn"; break;
+    case CCMN_x:
+      mnemonic = "ccmn";
+      break;
     case CCMP_w:
-    case CCMP_x: mnemonic = "ccmp"; break;
-    default: VIXL_UNREACHABLE();
+    case CCMP_x:
+      mnemonic = "ccmp";
+      break;
+    default:
+      VIXL_UNREACHABLE();
   }
   Format(instr, mnemonic, form);
 }
 
 
-void Disassembler::VisitConditionalCompareImmediate(const Instruction* instr) {
+void Disassembler::VisitConditionalCompareImmediate(const Instruction *instr) {
   const char *mnemonic = "";
   const char *form = "'Rn, 'IP, 'INzcv, 'Cond";
 
   switch (instr->Mask(ConditionalCompareImmediateMask)) {
     case CCMN_w_imm:
-    case CCMN_x_imm: mnemonic = "ccmn"; break;
+    case CCMN_x_imm:
+      mnemonic = "ccmn";
+      break;
     case CCMP_w_imm:
-    case CCMP_x_imm: mnemonic = "ccmp"; break;
-    default: VIXL_UNREACHABLE();
+    case CCMP_x_imm:
+      mnemonic = "ccmp";
+      break;
+    default:
+      VIXL_UNREACHABLE();
   }
   Format(instr, mnemonic, form);
 }
 
 
-void Disassembler::VisitConditionalSelect(const Instruction* instr) {
+void Disassembler::VisitConditionalSelect(const Instruction *instr) {
   bool rnm_is_zr = (RnIsZROrSP(instr) && RmIsZROrSP(instr));
   bool rn_is_rm = (instr->Rn() == instr->Rm());
   const char *mnemonic = "";
@@ -390,7 +429,9 @@
 
   switch (instr->Mask(ConditionalSelectMask)) {
     case CSEL_w:
-    case CSEL_x: mnemonic = "csel"; break;
+    case CSEL_x:
+      mnemonic = "csel";
+      break;
     case CSINC_w:
     case CSINC_x: {
       mnemonic = "csinc";
@@ -424,17 +465,18 @@
       }
       break;
     }
-    default: VIXL_UNREACHABLE();
+    default:
+      VIXL_UNREACHABLE();
   }
   Format(instr, mnemonic, form);
 }
 
 
-void Disassembler::VisitBitfield(const Instruction* instr) {
+void Disassembler::VisitBitfield(const Instruction *instr) {
   unsigned s = instr->ImmS();
   unsigned r = instr->ImmR();
   unsigned rd_size_minus_1 =
-    ((instr->SixtyFourBits() == 1) ? kXRegSize : kWRegSize) - 1;
+      ((instr->SixtyFourBits() == 1) ? kXRegSize : kWRegSize) - 1;
   const char *mnemonic = "";
   const char *form = "";
   const char *form_shift_right = "'Rd, 'Rn, 'IBr";
@@ -508,7 +550,7 @@
 }
 
 
-void Disassembler::VisitExtract(const Instruction* instr) {
+void Disassembler::VisitExtract(const Instruction *instr) {
   const char *mnemonic = "";
   const char *form = "'Rd, 'Rn, 'Rm, 'IExtract";
 
@@ -523,37 +565,50 @@
       }
       break;
     }
-    default: VIXL_UNREACHABLE();
+    default:
+      VIXL_UNREACHABLE();
   }
   Format(instr, mnemonic, form);
 }
 
 
-void Disassembler::VisitPCRelAddressing(const Instruction* instr) {
+void Disassembler::VisitPCRelAddressing(const Instruction *instr) {
   switch (instr->Mask(PCRelAddressingMask)) {
-    case ADR: Format(instr, "adr", "'Xd, 'AddrPCRelByte"); break;
-    case ADRP: Format(instr, "adrp", "'Xd, 'AddrPCRelPage"); break;
-    default: Format(instr, "unimplemented", "(PCRelAddressing)");
+    case ADR:
+      Format(instr, "adr", "'Xd, 'AddrPCRelByte");
+      break;
+    case ADRP:
+      Format(instr, "adrp", "'Xd, 'AddrPCRelPage");
+      break;
+    default:
+      Format(instr, "unimplemented", "(PCRelAddressing)");
   }
 }
 
 
-void Disassembler::VisitConditionalBranch(const Instruction* instr) {
+void Disassembler::VisitConditionalBranch(const Instruction *instr) {
   switch (instr->Mask(ConditionalBranchMask)) {
-    case B_cond: Format(instr, "b.'CBrn", "'TImmCond"); break;
-    default: VIXL_UNREACHABLE();
+    case B_cond:
+      Format(instr, "b.'CBrn", "'TImmCond");
+      break;
+    default:
+      VIXL_UNREACHABLE();
   }
 }
 
 
 void Disassembler::VisitUnconditionalBranchToRegister(
-    const Instruction* instr) {
+    const Instruction *instr) {
   const char *mnemonic = "unimplemented";
   const char *form = "'Xn";
 
   switch (instr->Mask(UnconditionalBranchToRegisterMask)) {
-    case BR: mnemonic = "br"; break;
-    case BLR: mnemonic = "blr"; break;
+    case BR:
+      mnemonic = "br";
+      break;
+    case BLR:
+      mnemonic = "blr";
+      break;
     case RET: {
       mnemonic = "ret";
       if (instr->Rn() == kLinkRegCode) {
@@ -561,77 +616,109 @@
       }
       break;
     }
-    default: form = "(UnconditionalBranchToRegister)";
+    default:
+      form = "(UnconditionalBranchToRegister)";
   }
   Format(instr, mnemonic, form);
 }
 
 
-void Disassembler::VisitUnconditionalBranch(const Instruction* instr) {
+void Disassembler::VisitUnconditionalBranch(const Instruction *instr) {
   const char *mnemonic = "";
   const char *form = "'TImmUncn";
 
   switch (instr->Mask(UnconditionalBranchMask)) {
-    case B: mnemonic = "b"; break;
-    case BL: mnemonic = "bl"; break;
-    default: VIXL_UNREACHABLE();
+    case B:
+      mnemonic = "b";
+      break;
+    case BL:
+      mnemonic = "bl";
+      break;
+    default:
+      VIXL_UNREACHABLE();
   }
   Format(instr, mnemonic, form);
 }
 
 
-void Disassembler::VisitDataProcessing1Source(const Instruction* instr) {
+void Disassembler::VisitDataProcessing1Source(const Instruction *instr) {
   const char *mnemonic = "";
   const char *form = "'Rd, 'Rn";
 
   switch (instr->Mask(DataProcessing1SourceMask)) {
-    #define FORMAT(A, B)  \
-    case A##_w:           \
-    case A##_x: mnemonic = B; break;
+#define FORMAT(A, B) \
+  case A##_w:        \
+  case A##_x:        \
+    mnemonic = B;    \
+    break;
     FORMAT(RBIT, "rbit");
     FORMAT(REV16, "rev16");
     FORMAT(REV, "rev");
     FORMAT(CLZ, "clz");
     FORMAT(CLS, "cls");
-    #undef FORMAT
-    case REV32_x: mnemonic = "rev32"; break;
-    default: VIXL_UNREACHABLE();
+#undef FORMAT
+    case REV32_x:
+      mnemonic = "rev32";
+      break;
+    default:
+      VIXL_UNREACHABLE();
   }
   Format(instr, mnemonic, form);
 }
 
 
-void Disassembler::VisitDataProcessing2Source(const Instruction* instr) {
+void Disassembler::VisitDataProcessing2Source(const Instruction *instr) {
   const char *mnemonic = "unimplemented";
   const char *form = "'Rd, 'Rn, 'Rm";
   const char *form_wwx = "'Wd, 'Wn, 'Xm";
 
   switch (instr->Mask(DataProcessing2SourceMask)) {
-    #define FORMAT(A, B)  \
-    case A##_w:           \
-    case A##_x: mnemonic = B; break;
+#define FORMAT(A, B) \
+  case A##_w:        \
+  case A##_x:        \
+    mnemonic = B;    \
+    break;
     FORMAT(UDIV, "udiv");
     FORMAT(SDIV, "sdiv");
     FORMAT(LSLV, "lsl");
     FORMAT(LSRV, "lsr");
     FORMAT(ASRV, "asr");
     FORMAT(RORV, "ror");
-    #undef FORMAT
-    case CRC32B: mnemonic = "crc32b"; break;
-    case CRC32H: mnemonic = "crc32h"; break;
-    case CRC32W: mnemonic = "crc32w"; break;
-    case CRC32X: mnemonic = "crc32x"; form = form_wwx; break;
-    case CRC32CB: mnemonic = "crc32cb"; break;
-    case CRC32CH: mnemonic = "crc32ch"; break;
-    case CRC32CW: mnemonic = "crc32cw"; break;
-    case CRC32CX: mnemonic = "crc32cx"; form = form_wwx; break;
-    default: form = "(DataProcessing2Source)";
+#undef FORMAT
+    case CRC32B:
+      mnemonic = "crc32b";
+      break;
+    case CRC32H:
+      mnemonic = "crc32h";
+      break;
+    case CRC32W:
+      mnemonic = "crc32w";
+      break;
+    case CRC32X:
+      mnemonic = "crc32x";
+      form = form_wwx;
+      break;
+    case CRC32CB:
+      mnemonic = "crc32cb";
+      break;
+    case CRC32CH:
+      mnemonic = "crc32ch";
+      break;
+    case CRC32CW:
+      mnemonic = "crc32cw";
+      break;
+    case CRC32CX:
+      mnemonic = "crc32cx";
+      form = form_wwx;
+      break;
+    default:
+      form = "(DataProcessing2Source)";
   }
   Format(instr, mnemonic, form);
 }
 
 
-void Disassembler::VisitDataProcessing3Source(const Instruction* instr) {
+void Disassembler::VisitDataProcessing3Source(const Instruction *instr) {
   bool ra_is_zr = RaIsZROrSP(instr);
   const char *mnemonic = "";
   const char *form = "'Xd, 'Wn, 'Wm, 'Xa";
@@ -703,28 +790,34 @@
       form = form_xxx;
       break;
     }
-    default: VIXL_UNREACHABLE();
+    default:
+      VIXL_UNREACHABLE();
   }
   Format(instr, mnemonic, form);
 }
 
 
-void Disassembler::VisitCompareBranch(const Instruction* instr) {
+void Disassembler::VisitCompareBranch(const Instruction *instr) {
   const char *mnemonic = "";
   const char *form = "'Rt, 'TImmCmpa";
 
   switch (instr->Mask(CompareBranchMask)) {
     case CBZ_w:
-    case CBZ_x: mnemonic = "cbz"; break;
+    case CBZ_x:
+      mnemonic = "cbz";
+      break;
     case CBNZ_w:
-    case CBNZ_x: mnemonic = "cbnz"; break;
-    default: VIXL_UNREACHABLE();
+    case CBNZ_x:
+      mnemonic = "cbnz";
+      break;
+    default:
+      VIXL_UNREACHABLE();
   }
   Format(instr, mnemonic, form);
 }
 
 
-void Disassembler::VisitTestBranch(const Instruction* instr) {
+void Disassembler::VisitTestBranch(const Instruction *instr) {
   const char *mnemonic = "";
   // If the top bit of the immediate is clear, the tested register is
   // disassembled as Wt, otherwise Xt. As the top bit of the immediate is
@@ -733,15 +826,20 @@
   const char *form = "'Rt, 'IS, 'TImmTest";
 
   switch (instr->Mask(TestBranchMask)) {
-    case TBZ: mnemonic = "tbz"; break;
-    case TBNZ: mnemonic = "tbnz"; break;
-    default: VIXL_UNREACHABLE();
+    case TBZ:
+      mnemonic = "tbz";
+      break;
+    case TBNZ:
+      mnemonic = "tbnz";
+      break;
+    default:
+      VIXL_UNREACHABLE();
   }
   Format(instr, mnemonic, form);
 }
 
 
-void Disassembler::VisitMoveWideImmediate(const Instruction* instr) {
+void Disassembler::VisitMoveWideImmediate(const Instruction *instr) {
   const char *mnemonic = "";
   const char *form = "'Rd, 'IMoveImm";
 
@@ -770,97 +868,117 @@
         mnemonic = "movz";
       break;
     case MOVK_w:
-    case MOVK_x: mnemonic = "movk"; form = "'Rd, 'IMoveLSL"; break;
-    default: VIXL_UNREACHABLE();
+    case MOVK_x:
+      mnemonic = "movk";
+      form = "'Rd, 'IMoveLSL";
+      break;
+    default:
+      VIXL_UNREACHABLE();
   }
   Format(instr, mnemonic, form);
 }
 
 
-#define LOAD_STORE_LIST(V)    \
-  V(STRB_w, "strb", "'Wt")    \
-  V(STRH_w, "strh", "'Wt")    \
-  V(STR_w, "str", "'Wt")      \
-  V(STR_x, "str", "'Xt")      \
-  V(LDRB_w, "ldrb", "'Wt")    \
-  V(LDRH_w, "ldrh", "'Wt")    \
-  V(LDR_w, "ldr", "'Wt")      \
-  V(LDR_x, "ldr", "'Xt")      \
-  V(LDRSB_x, "ldrsb", "'Xt")  \
-  V(LDRSH_x, "ldrsh", "'Xt")  \
-  V(LDRSW_x, "ldrsw", "'Xt")  \
-  V(LDRSB_w, "ldrsb", "'Wt")  \
-  V(LDRSH_w, "ldrsh", "'Wt")  \
-  V(STR_b, "str", "'Bt")      \
-  V(STR_h, "str", "'Ht")      \
-  V(STR_s, "str", "'St")      \
-  V(STR_d, "str", "'Dt")      \
-  V(LDR_b, "ldr", "'Bt")      \
-  V(LDR_h, "ldr", "'Ht")      \
-  V(LDR_s, "ldr", "'St")      \
-  V(LDR_d, "ldr", "'Dt")      \
-  V(STR_q, "str", "'Qt")      \
+#define LOAD_STORE_LIST(V)   \
+  V(STRB_w, "strb", "'Wt")   \
+  V(STRH_w, "strh", "'Wt")   \
+  V(STR_w, "str", "'Wt")     \
+  V(STR_x, "str", "'Xt")     \
+  V(LDRB_w, "ldrb", "'Wt")   \
+  V(LDRH_w, "ldrh", "'Wt")   \
+  V(LDR_w, "ldr", "'Wt")     \
+  V(LDR_x, "ldr", "'Xt")     \
+  V(LDRSB_x, "ldrsb", "'Xt") \
+  V(LDRSH_x, "ldrsh", "'Xt") \
+  V(LDRSW_x, "ldrsw", "'Xt") \
+  V(LDRSB_w, "ldrsb", "'Wt") \
+  V(LDRSH_w, "ldrsh", "'Wt") \
+  V(STR_b, "str", "'Bt")     \
+  V(STR_h, "str", "'Ht")     \
+  V(STR_s, "str", "'St")     \
+  V(STR_d, "str", "'Dt")     \
+  V(LDR_b, "ldr", "'Bt")     \
+  V(LDR_h, "ldr", "'Ht")     \
+  V(LDR_s, "ldr", "'St")     \
+  V(LDR_d, "ldr", "'Dt")     \
+  V(STR_q, "str", "'Qt")     \
   V(LDR_q, "ldr", "'Qt")
 
-void Disassembler::VisitLoadStorePreIndex(const Instruction* instr) {
+void Disassembler::VisitLoadStorePreIndex(const Instruction *instr) {
   const char *mnemonic = "unimplemented";
   const char *form = "(LoadStorePreIndex)";
 
   switch (instr->Mask(LoadStorePreIndexMask)) {
-    #define LS_PREINDEX(A, B, C) \
-    case A##_pre: mnemonic = B; form = C ", ['Xns'ILS]!"; break;
+#define LS_PREINDEX(A, B, C)  \
+  case A##_pre:               \
+    mnemonic = B;             \
+    form = C ", ['Xns'ILS]!"; \
+    break;
     LOAD_STORE_LIST(LS_PREINDEX)
-    #undef LS_PREINDEX
+#undef LS_PREINDEX
   }
   Format(instr, mnemonic, form);
 }
 
 
-void Disassembler::VisitLoadStorePostIndex(const Instruction* instr) {
+void Disassembler::VisitLoadStorePostIndex(const Instruction *instr) {
   const char *mnemonic = "unimplemented";
   const char *form = "(LoadStorePostIndex)";
 
   switch (instr->Mask(LoadStorePostIndexMask)) {
-    #define LS_POSTINDEX(A, B, C) \
-    case A##_post: mnemonic = B; form = C ", ['Xns]'ILS"; break;
+#define LS_POSTINDEX(A, B, C) \
+  case A##_post:              \
+    mnemonic = B;             \
+    form = C ", ['Xns]'ILS";  \
+    break;
     LOAD_STORE_LIST(LS_POSTINDEX)
-    #undef LS_POSTINDEX
+#undef LS_POSTINDEX
   }
   Format(instr, mnemonic, form);
 }
 
 
-void Disassembler::VisitLoadStoreUnsignedOffset(const Instruction* instr) {
+void Disassembler::VisitLoadStoreUnsignedOffset(const Instruction *instr) {
   const char *mnemonic = "unimplemented";
   const char *form = "(LoadStoreUnsignedOffset)";
 
   switch (instr->Mask(LoadStoreUnsignedOffsetMask)) {
-    #define LS_UNSIGNEDOFFSET(A, B, C) \
-    case A##_unsigned: mnemonic = B; form = C ", ['Xns'ILU]"; break;
+#define LS_UNSIGNEDOFFSET(A, B, C) \
+  case A##_unsigned:               \
+    mnemonic = B;                  \
+    form = C ", ['Xns'ILU]";       \
+    break;
     LOAD_STORE_LIST(LS_UNSIGNEDOFFSET)
-    #undef LS_UNSIGNEDOFFSET
-    case PRFM_unsigned: mnemonic = "prfm"; form = "'PrefOp, ['Xns'ILU]";
+#undef LS_UNSIGNEDOFFSET
+    case PRFM_unsigned:
+      mnemonic = "prfm";
+      form = "'PrefOp, ['Xns'ILU]";
   }
   Format(instr, mnemonic, form);
 }
 
 
-void Disassembler::VisitLoadStoreRegisterOffset(const Instruction* instr) {
+void Disassembler::VisitLoadStoreRegisterOffset(const Instruction *instr) {
   const char *mnemonic = "unimplemented";
   const char *form = "(LoadStoreRegisterOffset)";
 
   switch (instr->Mask(LoadStoreRegisterOffsetMask)) {
-    #define LS_REGISTEROFFSET(A, B, C) \
-    case A##_reg: mnemonic = B; form = C ", ['Xns, 'Offsetreg]"; break;
+#define LS_REGISTEROFFSET(A, B, C)   \
+  case A##_reg:                      \
+    mnemonic = B;                    \
+    form = C ", ['Xns, 'Offsetreg]"; \
+    break;
     LOAD_STORE_LIST(LS_REGISTEROFFSET)
-    #undef LS_REGISTEROFFSET
-    case PRFM_reg: mnemonic = "prfm"; form = "'PrefOp, ['Xns, 'Offsetreg]";
+#undef LS_REGISTEROFFSET
+    case PRFM_reg:
+      mnemonic = "prfm";
+      form = "'PrefOp, ['Xns, 'Offsetreg]";
   }
   Format(instr, mnemonic, form);
 }
 
 
-void Disassembler::VisitLoadStoreUnscaledOffset(const Instruction* instr) {
+void Disassembler::VisitLoadStoreUnscaledOffset(const Instruction *instr) {
   const char *mnemonic = "unimplemented";
   const char *form = "'Wt, ['Xns'ILS]";
   const char *form_x = "'Xt, ['Xns'ILS]";
@@ -872,46 +990,119 @@
   const char *form_prefetch = "'PrefOp, ['Xns'ILS]";
 
   switch (instr->Mask(LoadStoreUnscaledOffsetMask)) {
-    case STURB_w:  mnemonic = "sturb"; break;
-    case STURH_w:  mnemonic = "sturh"; break;
-    case STUR_w:   mnemonic = "stur"; break;
-    case STUR_x:   mnemonic = "stur"; form = form_x; break;
-    case STUR_b:   mnemonic = "stur"; form = form_b; break;
-    case STUR_h:   mnemonic = "stur"; form = form_h; break;
-    case STUR_s:   mnemonic = "stur"; form = form_s; break;
-    case STUR_d:   mnemonic = "stur"; form = form_d; break;
-    case STUR_q:   mnemonic = "stur"; form = form_q; break;
-    case LDURB_w:  mnemonic = "ldurb"; break;
-    case LDURH_w:  mnemonic = "ldurh"; break;
-    case LDUR_w:   mnemonic = "ldur"; break;
-    case LDUR_x:   mnemonic = "ldur"; form = form_x; break;
-    case LDUR_b:   mnemonic = "ldur"; form = form_b; break;
-    case LDUR_h:   mnemonic = "ldur"; form = form_h; break;
-    case LDUR_s:   mnemonic = "ldur"; form = form_s; break;
-    case LDUR_d:   mnemonic = "ldur"; form = form_d; break;
-    case LDUR_q:   mnemonic = "ldur"; form = form_q; break;
-    case LDURSB_x: form = form_x; VIXL_FALLTHROUGH();
-    case LDURSB_w: mnemonic = "ldursb"; break;
-    case LDURSH_x: form = form_x; VIXL_FALLTHROUGH();
-    case LDURSH_w: mnemonic = "ldursh"; break;
-    case LDURSW_x: mnemonic = "ldursw"; form = form_x; break;
-    case PRFUM:    mnemonic = "prfum"; form = form_prefetch; break;
-    default: form = "(LoadStoreUnscaledOffset)";
+    case STURB_w:
+      mnemonic = "sturb";
+      break;
+    case STURH_w:
+      mnemonic = "sturh";
+      break;
+    case STUR_w:
+      mnemonic = "stur";
+      break;
+    case STUR_x:
+      mnemonic = "stur";
+      form = form_x;
+      break;
+    case STUR_b:
+      mnemonic = "stur";
+      form = form_b;
+      break;
+    case STUR_h:
+      mnemonic = "stur";
+      form = form_h;
+      break;
+    case STUR_s:
+      mnemonic = "stur";
+      form = form_s;
+      break;
+    case STUR_d:
+      mnemonic = "stur";
+      form = form_d;
+      break;
+    case STUR_q:
+      mnemonic = "stur";
+      form = form_q;
+      break;
+    case LDURB_w:
+      mnemonic = "ldurb";
+      break;
+    case LDURH_w:
+      mnemonic = "ldurh";
+      break;
+    case LDUR_w:
+      mnemonic = "ldur";
+      break;
+    case LDUR_x:
+      mnemonic = "ldur";
+      form = form_x;
+      break;
+    case LDUR_b:
+      mnemonic = "ldur";
+      form = form_b;
+      break;
+    case LDUR_h:
+      mnemonic = "ldur";
+      form = form_h;
+      break;
+    case LDUR_s:
+      mnemonic = "ldur";
+      form = form_s;
+      break;
+    case LDUR_d:
+      mnemonic = "ldur";
+      form = form_d;
+      break;
+    case LDUR_q:
+      mnemonic = "ldur";
+      form = form_q;
+      break;
+    case LDURSB_x:
+      form = form_x;
+      VIXL_FALLTHROUGH();
+    case LDURSB_w:
+      mnemonic = "ldursb";
+      break;
+    case LDURSH_x:
+      form = form_x;
+      VIXL_FALLTHROUGH();
+    case LDURSH_w:
+      mnemonic = "ldursh";
+      break;
+    case LDURSW_x:
+      mnemonic = "ldursw";
+      form = form_x;
+      break;
+    case PRFUM:
+      mnemonic = "prfum";
+      form = form_prefetch;
+      break;
+    default:
+      form = "(LoadStoreUnscaledOffset)";
   }
   Format(instr, mnemonic, form);
 }
 
 
-void Disassembler::VisitLoadLiteral(const Instruction* instr) {
+void Disassembler::VisitLoadLiteral(const Instruction *instr) {
   const char *mnemonic = "ldr";
   const char *form = "(LoadLiteral)";
 
   switch (instr->Mask(LoadLiteralMask)) {
-    case LDR_w_lit: form = "'Wt, 'ILLiteral 'LValue"; break;
-    case LDR_x_lit: form = "'Xt, 'ILLiteral 'LValue"; break;
-    case LDR_s_lit: form = "'St, 'ILLiteral 'LValue"; break;
-    case LDR_d_lit: form = "'Dt, 'ILLiteral 'LValue"; break;
-    case LDR_q_lit: form = "'Qt, 'ILLiteral 'LValue"; break;
+    case LDR_w_lit:
+      form = "'Wt, 'ILLiteral 'LValue";
+      break;
+    case LDR_x_lit:
+      form = "'Xt, 'ILLiteral 'LValue";
+      break;
+    case LDR_s_lit:
+      form = "'St, 'ILLiteral 'LValue";
+      break;
+    case LDR_d_lit:
+      form = "'Dt, 'ILLiteral 'LValue";
+      break;
+    case LDR_q_lit:
+      form = "'Qt, 'ILLiteral 'LValue";
+      break;
     case LDRSW_x_lit: {
       mnemonic = "ldrsw";
       form = "'Xt, 'ILLiteral 'LValue";
@@ -922,7 +1113,8 @@
       form = "'PrefOp, 'ILLiteral 'LValue";
       break;
     }
-    default: mnemonic = "unimplemented";
+    default:
+      mnemonic = "unimplemented";
   }
   Format(instr, mnemonic, form);
 }
@@ -941,168 +1133,324 @@
   V(LDP_q, "ldp", "'Qt, 'Qt2", "4")     \
   V(STP_q, "stp", "'Qt, 'Qt2", "4")
 
-void Disassembler::VisitLoadStorePairPostIndex(const Instruction* instr) {
+void Disassembler::VisitLoadStorePairPostIndex(const Instruction *instr) {
   const char *mnemonic = "unimplemented";
   const char *form = "(LoadStorePairPostIndex)";
 
   switch (instr->Mask(LoadStorePairPostIndexMask)) {
-    #define LSP_POSTINDEX(A, B, C, D) \
-    case A##_post: mnemonic = B; form = C ", ['Xns]'ILP" D; break;
+#define LSP_POSTINDEX(A, B, C, D) \
+  case A##_post:                  \
+    mnemonic = B;                 \
+    form = C ", ['Xns]'ILP" D;    \
+    break;
     LOAD_STORE_PAIR_LIST(LSP_POSTINDEX)
-    #undef LSP_POSTINDEX
+#undef LSP_POSTINDEX
   }
   Format(instr, mnemonic, form);
 }
 
 
-void Disassembler::VisitLoadStorePairPreIndex(const Instruction* instr) {
+void Disassembler::VisitLoadStorePairPreIndex(const Instruction *instr) {
   const char *mnemonic = "unimplemented";
   const char *form = "(LoadStorePairPreIndex)";
 
   switch (instr->Mask(LoadStorePairPreIndexMask)) {
-    #define LSP_PREINDEX(A, B, C, D) \
-    case A##_pre: mnemonic = B; form = C ", ['Xns'ILP" D "]!"; break;
+#define LSP_PREINDEX(A, B, C, D)   \
+  case A##_pre:                    \
+    mnemonic = B;                  \
+    form = C ", ['Xns'ILP" D "]!"; \
+    break;
     LOAD_STORE_PAIR_LIST(LSP_PREINDEX)
-    #undef LSP_PREINDEX
+#undef LSP_PREINDEX
   }
   Format(instr, mnemonic, form);
 }
 
 
-void Disassembler::VisitLoadStorePairOffset(const Instruction* instr) {
+void Disassembler::VisitLoadStorePairOffset(const Instruction *instr) {
   const char *mnemonic = "unimplemented";
   const char *form = "(LoadStorePairOffset)";
 
   switch (instr->Mask(LoadStorePairOffsetMask)) {
-    #define LSP_OFFSET(A, B, C, D) \
-    case A##_off: mnemonic = B; form = C ", ['Xns'ILP" D "]"; break;
+#define LSP_OFFSET(A, B, C, D)    \
+  case A##_off:                   \
+    mnemonic = B;                 \
+    form = C ", ['Xns'ILP" D "]"; \
+    break;
     LOAD_STORE_PAIR_LIST(LSP_OFFSET)
-    #undef LSP_OFFSET
+#undef LSP_OFFSET
   }
   Format(instr, mnemonic, form);
 }
 
 
-void Disassembler::VisitLoadStorePairNonTemporal(const Instruction* instr) {
+void Disassembler::VisitLoadStorePairNonTemporal(const Instruction *instr) {
   const char *mnemonic = "unimplemented";
   const char *form;
 
   switch (instr->Mask(LoadStorePairNonTemporalMask)) {
-    case STNP_w: mnemonic = "stnp"; form = "'Wt, 'Wt2, ['Xns'ILP2]"; break;
-    case LDNP_w: mnemonic = "ldnp"; form = "'Wt, 'Wt2, ['Xns'ILP2]"; break;
-    case STNP_x: mnemonic = "stnp"; form = "'Xt, 'Xt2, ['Xns'ILP3]"; break;
-    case LDNP_x: mnemonic = "ldnp"; form = "'Xt, 'Xt2, ['Xns'ILP3]"; break;
-    case STNP_s: mnemonic = "stnp"; form = "'St, 'St2, ['Xns'ILP2]"; break;
-    case LDNP_s: mnemonic = "ldnp"; form = "'St, 'St2, ['Xns'ILP2]"; break;
-    case STNP_d: mnemonic = "stnp"; form = "'Dt, 'Dt2, ['Xns'ILP3]"; break;
-    case LDNP_d: mnemonic = "ldnp"; form = "'Dt, 'Dt2, ['Xns'ILP3]"; break;
-    case STNP_q: mnemonic = "stnp"; form = "'Qt, 'Qt2, ['Xns'ILP4]"; break;
-    case LDNP_q: mnemonic = "ldnp"; form = "'Qt, 'Qt2, ['Xns'ILP4]"; break;
-    default: form = "(LoadStorePairNonTemporal)";
+    case STNP_w:
+      mnemonic = "stnp";
+      form = "'Wt, 'Wt2, ['Xns'ILP2]";
+      break;
+    case LDNP_w:
+      mnemonic = "ldnp";
+      form = "'Wt, 'Wt2, ['Xns'ILP2]";
+      break;
+    case STNP_x:
+      mnemonic = "stnp";
+      form = "'Xt, 'Xt2, ['Xns'ILP3]";
+      break;
+    case LDNP_x:
+      mnemonic = "ldnp";
+      form = "'Xt, 'Xt2, ['Xns'ILP3]";
+      break;
+    case STNP_s:
+      mnemonic = "stnp";
+      form = "'St, 'St2, ['Xns'ILP2]";
+      break;
+    case LDNP_s:
+      mnemonic = "ldnp";
+      form = "'St, 'St2, ['Xns'ILP2]";
+      break;
+    case STNP_d:
+      mnemonic = "stnp";
+      form = "'Dt, 'Dt2, ['Xns'ILP3]";
+      break;
+    case LDNP_d:
+      mnemonic = "ldnp";
+      form = "'Dt, 'Dt2, ['Xns'ILP3]";
+      break;
+    case STNP_q:
+      mnemonic = "stnp";
+      form = "'Qt, 'Qt2, ['Xns'ILP4]";
+      break;
+    case LDNP_q:
+      mnemonic = "ldnp";
+      form = "'Qt, 'Qt2, ['Xns'ILP4]";
+      break;
+    default:
+      form = "(LoadStorePairNonTemporal)";
   }
   Format(instr, mnemonic, form);
 }
 
 
-void Disassembler::VisitLoadStoreExclusive(const Instruction* instr) {
+void Disassembler::VisitLoadStoreExclusive(const Instruction *instr) {
   const char *mnemonic = "unimplemented";
   const char *form;
 
   switch (instr->Mask(LoadStoreExclusiveMask)) {
-    case STXRB_w: mnemonic = "stxrb"; form = "'Ws, 'Wt, ['Xns]"; break;
-    case STXRH_w: mnemonic = "stxrh"; form = "'Ws, 'Wt, ['Xns]"; break;
-    case STXR_w: mnemonic = "stxr"; form = "'Ws, 'Wt, ['Xns]"; break;
-    case STXR_x: mnemonic = "stxr"; form = "'Ws, 'Xt, ['Xns]"; break;
-    case LDXRB_w: mnemonic = "ldxrb"; form = "'Wt, ['Xns]"; break;
-    case LDXRH_w: mnemonic = "ldxrh"; form = "'Wt, ['Xns]"; break;
-    case LDXR_w: mnemonic = "ldxr"; form = "'Wt, ['Xns]"; break;
-    case LDXR_x: mnemonic = "ldxr"; form = "'Xt, ['Xns]"; break;
-    case STXP_w: mnemonic = "stxp"; form = "'Ws, 'Wt, 'Wt2, ['Xns]"; break;
-    case STXP_x: mnemonic = "stxp"; form = "'Ws, 'Xt, 'Xt2, ['Xns]"; break;
-    case LDXP_w: mnemonic = "ldxp"; form = "'Wt, 'Wt2, ['Xns]"; break;
-    case LDXP_x: mnemonic = "ldxp"; form = "'Xt, 'Xt2, ['Xns]"; break;
-    case STLXRB_w: mnemonic = "stlxrb"; form = "'Ws, 'Wt, ['Xns]"; break;
-    case STLXRH_w: mnemonic = "stlxrh"; form = "'Ws, 'Wt, ['Xns]"; break;
-    case STLXR_w: mnemonic = "stlxr"; form = "'Ws, 'Wt, ['Xns]"; break;
-    case STLXR_x: mnemonic = "stlxr"; form = "'Ws, 'Xt, ['Xns]"; break;
-    case LDAXRB_w: mnemonic = "ldaxrb"; form = "'Wt, ['Xns]"; break;
-    case LDAXRH_w: mnemonic = "ldaxrh"; form = "'Wt, ['Xns]"; break;
-    case LDAXR_w: mnemonic = "ldaxr"; form = "'Wt, ['Xns]"; break;
-    case LDAXR_x: mnemonic = "ldaxr"; form = "'Xt, ['Xns]"; break;
-    case STLXP_w: mnemonic = "stlxp"; form = "'Ws, 'Wt, 'Wt2, ['Xns]"; break;
-    case STLXP_x: mnemonic = "stlxp"; form = "'Ws, 'Xt, 'Xt2, ['Xns]"; break;
-    case LDAXP_w: mnemonic = "ldaxp"; form = "'Wt, 'Wt2, ['Xns]"; break;
-    case LDAXP_x: mnemonic = "ldaxp"; form = "'Xt, 'Xt2, ['Xns]"; break;
-    case STLRB_w: mnemonic = "stlrb"; form = "'Wt, ['Xns]"; break;
-    case STLRH_w: mnemonic = "stlrh"; form = "'Wt, ['Xns]"; break;
-    case STLR_w: mnemonic = "stlr"; form = "'Wt, ['Xns]"; break;
-    case STLR_x: mnemonic = "stlr"; form = "'Xt, ['Xns]"; break;
-    case LDARB_w: mnemonic = "ldarb"; form = "'Wt, ['Xns]"; break;
-    case LDARH_w: mnemonic = "ldarh"; form = "'Wt, ['Xns]"; break;
-    case LDAR_w: mnemonic = "ldar"; form = "'Wt, ['Xns]"; break;
-    case LDAR_x: mnemonic = "ldar"; form = "'Xt, ['Xns]"; break;
-    default: form = "(LoadStoreExclusive)";
+    case STXRB_w:
+      mnemonic = "stxrb";
+      form = "'Ws, 'Wt, ['Xns]";
+      break;
+    case STXRH_w:
+      mnemonic = "stxrh";
+      form = "'Ws, 'Wt, ['Xns]";
+      break;
+    case STXR_w:
+      mnemonic = "stxr";
+      form = "'Ws, 'Wt, ['Xns]";
+      break;
+    case STXR_x:
+      mnemonic = "stxr";
+      form = "'Ws, 'Xt, ['Xns]";
+      break;
+    case LDXRB_w:
+      mnemonic = "ldxrb";
+      form = "'Wt, ['Xns]";
+      break;
+    case LDXRH_w:
+      mnemonic = "ldxrh";
+      form = "'Wt, ['Xns]";
+      break;
+    case LDXR_w:
+      mnemonic = "ldxr";
+      form = "'Wt, ['Xns]";
+      break;
+    case LDXR_x:
+      mnemonic = "ldxr";
+      form = "'Xt, ['Xns]";
+      break;
+    case STXP_w:
+      mnemonic = "stxp";
+      form = "'Ws, 'Wt, 'Wt2, ['Xns]";
+      break;
+    case STXP_x:
+      mnemonic = "stxp";
+      form = "'Ws, 'Xt, 'Xt2, ['Xns]";
+      break;
+    case LDXP_w:
+      mnemonic = "ldxp";
+      form = "'Wt, 'Wt2, ['Xns]";
+      break;
+    case LDXP_x:
+      mnemonic = "ldxp";
+      form = "'Xt, 'Xt2, ['Xns]";
+      break;
+    case STLXRB_w:
+      mnemonic = "stlxrb";
+      form = "'Ws, 'Wt, ['Xns]";
+      break;
+    case STLXRH_w:
+      mnemonic = "stlxrh";
+      form = "'Ws, 'Wt, ['Xns]";
+      break;
+    case STLXR_w:
+      mnemonic = "stlxr";
+      form = "'Ws, 'Wt, ['Xns]";
+      break;
+    case STLXR_x:
+      mnemonic = "stlxr";
+      form = "'Ws, 'Xt, ['Xns]";
+      break;
+    case LDAXRB_w:
+      mnemonic = "ldaxrb";
+      form = "'Wt, ['Xns]";
+      break;
+    case LDAXRH_w:
+      mnemonic = "ldaxrh";
+      form = "'Wt, ['Xns]";
+      break;
+    case LDAXR_w:
+      mnemonic = "ldaxr";
+      form = "'Wt, ['Xns]";
+      break;
+    case LDAXR_x:
+      mnemonic = "ldaxr";
+      form = "'Xt, ['Xns]";
+      break;
+    case STLXP_w:
+      mnemonic = "stlxp";
+      form = "'Ws, 'Wt, 'Wt2, ['Xns]";
+      break;
+    case STLXP_x:
+      mnemonic = "stlxp";
+      form = "'Ws, 'Xt, 'Xt2, ['Xns]";
+      break;
+    case LDAXP_w:
+      mnemonic = "ldaxp";
+      form = "'Wt, 'Wt2, ['Xns]";
+      break;
+    case LDAXP_x:
+      mnemonic = "ldaxp";
+      form = "'Xt, 'Xt2, ['Xns]";
+      break;
+    case STLRB_w:
+      mnemonic = "stlrb";
+      form = "'Wt, ['Xns]";
+      break;
+    case STLRH_w:
+      mnemonic = "stlrh";
+      form = "'Wt, ['Xns]";
+      break;
+    case STLR_w:
+      mnemonic = "stlr";
+      form = "'Wt, ['Xns]";
+      break;
+    case STLR_x:
+      mnemonic = "stlr";
+      form = "'Xt, ['Xns]";
+      break;
+    case LDARB_w:
+      mnemonic = "ldarb";
+      form = "'Wt, ['Xns]";
+      break;
+    case LDARH_w:
+      mnemonic = "ldarh";
+      form = "'Wt, ['Xns]";
+      break;
+    case LDAR_w:
+      mnemonic = "ldar";
+      form = "'Wt, ['Xns]";
+      break;
+    case LDAR_x:
+      mnemonic = "ldar";
+      form = "'Xt, ['Xns]";
+      break;
+    default:
+      form = "(LoadStoreExclusive)";
   }
   Format(instr, mnemonic, form);
 }
 
 
-void Disassembler::VisitFPCompare(const Instruction* instr) {
+void Disassembler::VisitFPCompare(const Instruction *instr) {
   const char *mnemonic = "unimplemented";
   const char *form = "'Fn, 'Fm";
   const char *form_zero = "'Fn, #0.0";
 
   switch (instr->Mask(FPCompareMask)) {
     case FCMP_s_zero:
-    case FCMP_d_zero: form = form_zero; VIXL_FALLTHROUGH();
+    case FCMP_d_zero:
+      form = form_zero;
+      VIXL_FALLTHROUGH();
     case FCMP_s:
-    case FCMP_d: mnemonic = "fcmp"; break;
+    case FCMP_d:
+      mnemonic = "fcmp";
+      break;
     case FCMPE_s_zero:
-    case FCMPE_d_zero: form = form_zero; VIXL_FALLTHROUGH();
+    case FCMPE_d_zero:
+      form = form_zero;
+      VIXL_FALLTHROUGH();
     case FCMPE_s:
-    case FCMPE_d: mnemonic = "fcmpe"; break;
-    default: form = "(FPCompare)";
+    case FCMPE_d:
+      mnemonic = "fcmpe";
+      break;
+    default:
+      form = "(FPCompare)";
   }
   Format(instr, mnemonic, form);
 }
 
 
-void Disassembler::VisitFPConditionalCompare(const Instruction* instr) {
+void Disassembler::VisitFPConditionalCompare(const Instruction *instr) {
   const char *mnemonic = "unmplemented";
   const char *form = "'Fn, 'Fm, 'INzcv, 'Cond";
 
   switch (instr->Mask(FPConditionalCompareMask)) {
     case FCCMP_s:
-    case FCCMP_d: mnemonic = "fccmp"; break;
+    case FCCMP_d:
+      mnemonic = "fccmp";
+      break;
     case FCCMPE_s:
-    case FCCMPE_d: mnemonic = "fccmpe"; break;
-    default: form = "(FPConditionalCompare)";
+    case FCCMPE_d:
+      mnemonic = "fccmpe";
+      break;
+    default:
+      form = "(FPConditionalCompare)";
   }
   Format(instr, mnemonic, form);
 }
 
 
-void Disassembler::VisitFPConditionalSelect(const Instruction* instr) {
+void Disassembler::VisitFPConditionalSelect(const Instruction *instr) {
   const char *mnemonic = "";
   const char *form = "'Fd, 'Fn, 'Fm, 'Cond";
 
   switch (instr->Mask(FPConditionalSelectMask)) {
     case FCSEL_s:
-    case FCSEL_d: mnemonic = "fcsel"; break;
-    default: VIXL_UNREACHABLE();
+    case FCSEL_d:
+      mnemonic = "fcsel";
+      break;
+    default:
+      VIXL_UNREACHABLE();
   }
   Format(instr, mnemonic, form);
 }
 
 
-void Disassembler::VisitFPDataProcessing1Source(const Instruction* instr) {
+void Disassembler::VisitFPDataProcessing1Source(const Instruction *instr) {
   const char *mnemonic = "unimplemented";
   const char *form = "'Fd, 'Fn";
 
   switch (instr->Mask(FPDataProcessing1SourceMask)) {
-    #define FORMAT(A, B)  \
-    case A##_s:           \
-    case A##_d: mnemonic = B; break;
+#define FORMAT(A, B) \
+  case A##_s:        \
+  case A##_d:        \
+    mnemonic = B;    \
+    break;
     FORMAT(FMOV, "fmov");
     FORMAT(FABS, "fabs");
     FORMAT(FNEG, "fneg");
@@ -1114,27 +1462,48 @@
     FORMAT(FRINTA, "frinta");
     FORMAT(FRINTX, "frintx");
     FORMAT(FRINTI, "frinti");
-    #undef FORMAT
-    case FCVT_ds: mnemonic = "fcvt"; form = "'Dd, 'Sn"; break;
-    case FCVT_sd: mnemonic = "fcvt"; form = "'Sd, 'Dn"; break;
-    case FCVT_hs: mnemonic = "fcvt"; form = "'Hd, 'Sn"; break;
-    case FCVT_sh: mnemonic = "fcvt"; form = "'Sd, 'Hn"; break;
-    case FCVT_dh: mnemonic = "fcvt"; form = "'Dd, 'Hn"; break;
-    case FCVT_hd: mnemonic = "fcvt"; form = "'Hd, 'Dn"; break;
-    default: form = "(FPDataProcessing1Source)";
+#undef FORMAT
+    case FCVT_ds:
+      mnemonic = "fcvt";
+      form = "'Dd, 'Sn";
+      break;
+    case FCVT_sd:
+      mnemonic = "fcvt";
+      form = "'Sd, 'Dn";
+      break;
+    case FCVT_hs:
+      mnemonic = "fcvt";
+      form = "'Hd, 'Sn";
+      break;
+    case FCVT_sh:
+      mnemonic = "fcvt";
+      form = "'Sd, 'Hn";
+      break;
+    case FCVT_dh:
+      mnemonic = "fcvt";
+      form = "'Dd, 'Hn";
+      break;
+    case FCVT_hd:
+      mnemonic = "fcvt";
+      form = "'Hd, 'Dn";
+      break;
+    default:
+      form = "(FPDataProcessing1Source)";
   }
   Format(instr, mnemonic, form);
 }
 
 
-void Disassembler::VisitFPDataProcessing2Source(const Instruction* instr) {
+void Disassembler::VisitFPDataProcessing2Source(const Instruction *instr) {
   const char *mnemonic = "";
   const char *form = "'Fd, 'Fn, 'Fm";
 
   switch (instr->Mask(FPDataProcessing2SourceMask)) {
-    #define FORMAT(A, B)  \
-    case A##_s:           \
-    case A##_d: mnemonic = B; break;
+#define FORMAT(A, B) \
+  case A##_s:        \
+  case A##_d:        \
+    mnemonic = B;    \
+    break;
     FORMAT(FMUL, "fmul");
     FORMAT(FDIV, "fdiv");
     FORMAT(FADD, "fadd");
@@ -1144,46 +1513,57 @@
     FORMAT(FMAXNM, "fmaxnm");
     FORMAT(FMINNM, "fminnm");
     FORMAT(FNMUL, "fnmul");
-    #undef FORMAT
-    default: VIXL_UNREACHABLE();
+#undef FORMAT
+    default:
+      VIXL_UNREACHABLE();
   }
   Format(instr, mnemonic, form);
 }
 
 
-void Disassembler::VisitFPDataProcessing3Source(const Instruction* instr) {
+void Disassembler::VisitFPDataProcessing3Source(const Instruction *instr) {
   const char *mnemonic = "";
   const char *form = "'Fd, 'Fn, 'Fm, 'Fa";
 
   switch (instr->Mask(FPDataProcessing3SourceMask)) {
-    #define FORMAT(A, B)  \
-    case A##_s:           \
-    case A##_d: mnemonic = B; break;
+#define FORMAT(A, B) \
+  case A##_s:        \
+  case A##_d:        \
+    mnemonic = B;    \
+    break;
     FORMAT(FMADD, "fmadd");
     FORMAT(FMSUB, "fmsub");
     FORMAT(FNMADD, "fnmadd");
     FORMAT(FNMSUB, "fnmsub");
-    #undef FORMAT
-    default: VIXL_UNREACHABLE();
+#undef FORMAT
+    default:
+      VIXL_UNREACHABLE();
   }
   Format(instr, mnemonic, form);
 }
 
 
-void Disassembler::VisitFPImmediate(const Instruction* instr) {
+void Disassembler::VisitFPImmediate(const Instruction *instr) {
   const char *mnemonic = "";
   const char *form = "(FPImmediate)";
 
   switch (instr->Mask(FPImmediateMask)) {
-    case FMOV_s_imm: mnemonic = "fmov"; form = "'Sd, 'IFPSingle"; break;
-    case FMOV_d_imm: mnemonic = "fmov"; form = "'Dd, 'IFPDouble"; break;
-    default: VIXL_UNREACHABLE();
+    case FMOV_s_imm:
+      mnemonic = "fmov";
+      form = "'Sd, 'IFPSingle";
+      break;
+    case FMOV_d_imm:
+      mnemonic = "fmov";
+      form = "'Dd, 'IFPDouble";
+      break;
+    default:
+      VIXL_UNREACHABLE();
   }
   Format(instr, mnemonic, form);
 }
 
 
-void Disassembler::VisitFPIntegerConvert(const Instruction* instr) {
+void Disassembler::VisitFPIntegerConvert(const Instruction *instr) {
   const char *mnemonic = "unimplemented";
   const char *form = "(FPIntegerConvert)";
   const char *form_rf = "'Rd, 'Fn";
@@ -1191,65 +1571,113 @@
 
   switch (instr->Mask(FPIntegerConvertMask)) {
     case FMOV_ws:
-    case FMOV_xd: mnemonic = "fmov"; form = form_rf; break;
+    case FMOV_xd:
+      mnemonic = "fmov";
+      form = form_rf;
+      break;
     case FMOV_sw:
-    case FMOV_dx: mnemonic = "fmov"; form = form_fr; break;
-    case FMOV_d1_x: mnemonic = "fmov"; form = "'Vd.D[1], 'Rn"; break;
-    case FMOV_x_d1: mnemonic = "fmov"; form = "'Rd, 'Vn.D[1]"; break;
+    case FMOV_dx:
+      mnemonic = "fmov";
+      form = form_fr;
+      break;
+    case FMOV_d1_x:
+      mnemonic = "fmov";
+      form = "'Vd.D[1], 'Rn";
+      break;
+    case FMOV_x_d1:
+      mnemonic = "fmov";
+      form = "'Rd, 'Vn.D[1]";
+      break;
     case FCVTAS_ws:
     case FCVTAS_xs:
     case FCVTAS_wd:
-    case FCVTAS_xd: mnemonic = "fcvtas"; form = form_rf; break;
+    case FCVTAS_xd:
+      mnemonic = "fcvtas";
+      form = form_rf;
+      break;
     case FCVTAU_ws:
     case FCVTAU_xs:
     case FCVTAU_wd:
-    case FCVTAU_xd: mnemonic = "fcvtau"; form = form_rf; break;
+    case FCVTAU_xd:
+      mnemonic = "fcvtau";
+      form = form_rf;
+      break;
     case FCVTMS_ws:
     case FCVTMS_xs:
     case FCVTMS_wd:
-    case FCVTMS_xd: mnemonic = "fcvtms"; form = form_rf; break;
+    case FCVTMS_xd:
+      mnemonic = "fcvtms";
+      form = form_rf;
+      break;
     case FCVTMU_ws:
     case FCVTMU_xs:
     case FCVTMU_wd:
-    case FCVTMU_xd: mnemonic = "fcvtmu"; form = form_rf; break;
+    case FCVTMU_xd:
+      mnemonic = "fcvtmu";
+      form = form_rf;
+      break;
     case FCVTNS_ws:
     case FCVTNS_xs:
     case FCVTNS_wd:
-    case FCVTNS_xd: mnemonic = "fcvtns"; form = form_rf; break;
+    case FCVTNS_xd:
+      mnemonic = "fcvtns";
+      form = form_rf;
+      break;
     case FCVTNU_ws:
     case FCVTNU_xs:
     case FCVTNU_wd:
-    case FCVTNU_xd: mnemonic = "fcvtnu"; form = form_rf; break;
+    case FCVTNU_xd:
+      mnemonic = "fcvtnu";
+      form = form_rf;
+      break;
     case FCVTZU_xd:
     case FCVTZU_ws:
     case FCVTZU_wd:
-    case FCVTZU_xs: mnemonic = "fcvtzu"; form = form_rf; break;
+    case FCVTZU_xs:
+      mnemonic = "fcvtzu";
+      form = form_rf;
+      break;
     case FCVTZS_xd:
     case FCVTZS_wd:
     case FCVTZS_xs:
-    case FCVTZS_ws: mnemonic = "fcvtzs"; form = form_rf; break;
+    case FCVTZS_ws:
+      mnemonic = "fcvtzs";
+      form = form_rf;
+      break;
     case FCVTPU_xd:
     case FCVTPU_ws:
     case FCVTPU_wd:
-    case FCVTPU_xs: mnemonic = "fcvtpu"; form = form_rf; break;
+    case FCVTPU_xs:
+      mnemonic = "fcvtpu";
+      form = form_rf;
+      break;
     case FCVTPS_xd:
     case FCVTPS_wd:
     case FCVTPS_xs:
-    case FCVTPS_ws: mnemonic = "fcvtps"; form = form_rf; break;
+    case FCVTPS_ws:
+      mnemonic = "fcvtps";
+      form = form_rf;
+      break;
     case SCVTF_sw:
     case SCVTF_sx:
     case SCVTF_dw:
-    case SCVTF_dx: mnemonic = "scvtf"; form = form_fr; break;
+    case SCVTF_dx:
+      mnemonic = "scvtf";
+      form = form_fr;
+      break;
     case UCVTF_sw:
     case UCVTF_sx:
     case UCVTF_dw:
-    case UCVTF_dx: mnemonic = "ucvtf"; form = form_fr; break;
+    case UCVTF_dx:
+      mnemonic = "ucvtf";
+      form = form_fr;
+      break;
   }
   Format(instr, mnemonic, form);
 }
 
 
-void Disassembler::VisitFPFixedPointConvert(const Instruction* instr) {
+void Disassembler::VisitFPFixedPointConvert(const Instruction *instr) {
   const char *mnemonic = "";
   const char *form = "'Rd, 'Fn, 'IFPFBits";
   const char *form_fr = "'Fd, 'Rn, 'IFPFBits";
@@ -1258,26 +1686,37 @@
     case FCVTZS_ws_fixed:
     case FCVTZS_xs_fixed:
     case FCVTZS_wd_fixed:
-    case FCVTZS_xd_fixed: mnemonic = "fcvtzs"; break;
+    case FCVTZS_xd_fixed:
+      mnemonic = "fcvtzs";
+      break;
     case FCVTZU_ws_fixed:
     case FCVTZU_xs_fixed:
     case FCVTZU_wd_fixed:
-    case FCVTZU_xd_fixed: mnemonic = "fcvtzu"; break;
+    case FCVTZU_xd_fixed:
+      mnemonic = "fcvtzu";
+      break;
     case SCVTF_sw_fixed:
     case SCVTF_sx_fixed:
     case SCVTF_dw_fixed:
-    case SCVTF_dx_fixed: mnemonic = "scvtf"; form = form_fr; break;
+    case SCVTF_dx_fixed:
+      mnemonic = "scvtf";
+      form = form_fr;
+      break;
     case UCVTF_sw_fixed:
     case UCVTF_sx_fixed:
     case UCVTF_dw_fixed:
-    case UCVTF_dx_fixed: mnemonic = "ucvtf"; form = form_fr; break;
-    default: VIXL_UNREACHABLE();
+    case UCVTF_dx_fixed:
+      mnemonic = "ucvtf";
+      form = form_fr;
+      break;
+    default:
+      VIXL_UNREACHABLE();
   }
   Format(instr, mnemonic, form);
 }
 
 
-void Disassembler::VisitSystem(const Instruction* instr) {
+void Disassembler::VisitSystem(const Instruction *instr) {
   // Some system instructions hijack their Op and Cp fields to represent a
   // range of immediates instead of indicating a different instruction. This
   // makes the decoding tricky.
@@ -1297,18 +1736,30 @@
       case MRS: {
         mnemonic = "mrs";
         switch (instr->ImmSystemRegister()) {
-          case NZCV: form = "'Xt, nzcv"; break;
-          case FPCR: form = "'Xt, fpcr"; break;
-          default: form = "'Xt, (unknown)"; break;
+          case NZCV:
+            form = "'Xt, nzcv";
+            break;
+          case FPCR:
+            form = "'Xt, fpcr";
+            break;
+          default:
+            form = "'Xt, (unknown)";
+            break;
         }
         break;
       }
       case MSR: {
         mnemonic = "msr";
         switch (instr->ImmSystemRegister()) {
-          case NZCV: form = "nzcv, 'Xt"; break;
-          case FPCR: form = "fpcr, 'Xt"; break;
-          default: form = "(unknown), 'Xt"; break;
+          case NZCV:
+            form = "nzcv, 'Xt";
+            break;
+          case FPCR:
+            form = "fpcr, 'Xt";
+            break;
+          default:
+            form = "(unknown), 'Xt";
+            break;
         }
         break;
       }
@@ -1369,72 +1820,94 @@
           form = "'G1, 'Kn, 'Km, 'G2, 'Xt";
         }
         break;
-      }
+    }
   }
   Format(instr, mnemonic, form);
 }
 
 
-void Disassembler::VisitException(const Instruction* instr) {
+void Disassembler::VisitException(const Instruction *instr) {
   const char *mnemonic = "unimplemented";
   const char *form = "'IDebug";
 
   switch (instr->Mask(ExceptionMask)) {
-    case HLT: mnemonic = "hlt"; break;
-    case BRK: mnemonic = "brk"; break;
-    case SVC: mnemonic = "svc"; break;
-    case HVC: mnemonic = "hvc"; break;
-    case SMC: mnemonic = "smc"; break;
-    case DCPS1: mnemonic = "dcps1"; form = "{'IDebug}"; break;
-    case DCPS2: mnemonic = "dcps2"; form = "{'IDebug}"; break;
-    case DCPS3: mnemonic = "dcps3"; form = "{'IDebug}"; break;
-    default: form = "(Exception)";
+    case HLT:
+      mnemonic = "hlt";
+      break;
+    case BRK:
+      mnemonic = "brk";
+      break;
+    case SVC:
+      mnemonic = "svc";
+      break;
+    case HVC:
+      mnemonic = "hvc";
+      break;
+    case SMC:
+      mnemonic = "smc";
+      break;
+    case DCPS1:
+      mnemonic = "dcps1";
+      form = "{'IDebug}";
+      break;
+    case DCPS2:
+      mnemonic = "dcps2";
+      form = "{'IDebug}";
+      break;
+    case DCPS3:
+      mnemonic = "dcps3";
+      form = "{'IDebug}";
+      break;
+    default:
+      form = "(Exception)";
   }
   Format(instr, mnemonic, form);
 }
 
 
-void Disassembler::VisitCrypto2RegSHA(const Instruction* instr) {
+void Disassembler::VisitCrypto2RegSHA(const Instruction *instr) {
   VisitUnimplemented(instr);
 }
 
 
-void Disassembler::VisitCrypto3RegSHA(const Instruction* instr) {
+void Disassembler::VisitCrypto3RegSHA(const Instruction *instr) {
   VisitUnimplemented(instr);
 }
 
 
-void Disassembler::VisitCryptoAES(const Instruction* instr) {
+void Disassembler::VisitCryptoAES(const Instruction *instr) {
   VisitUnimplemented(instr);
 }
 
 
-void Disassembler::VisitNEON2RegMisc(const Instruction* instr) {
-  const char *mnemonic       = "unimplemented";
-  const char *form           = "'Vd.%s, 'Vn.%s";
-  const char *form_cmp_zero  = "'Vd.%s, 'Vn.%s, #0";
+void Disassembler::VisitNEON2RegMisc(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'Vd.%s, 'Vn.%s";
+  const char *form_cmp_zero = "'Vd.%s, 'Vn.%s, #0";
   const char *form_fcmp_zero = "'Vd.%s, 'Vn.%s, #0.0";
   NEONFormatDecoder nfd(instr);
 
-  static const NEONFormatMap map_lp_ta = {
-    {23, 22, 30}, {NF_4H, NF_8H, NF_2S, NF_4S, NF_1D, NF_2D}
-  };
+  static const NEONFormatMap map_lp_ta =
+      {{23, 22, 30}, {NF_4H, NF_8H, NF_2S, NF_4S, NF_1D, NF_2D}};
 
-  static const NEONFormatMap map_cvt_ta = {
-    {22}, {NF_4S, NF_2D}
-  };
+  static const NEONFormatMap map_cvt_ta = {{22}, {NF_4S, NF_2D}};
 
-  static const NEONFormatMap map_cvt_tb = {
-    {22, 30}, {NF_4H, NF_8H, NF_2S, NF_4S}
-  };
+  static const NEONFormatMap map_cvt_tb = {{22, 30},
+                                           {NF_4H, NF_8H, NF_2S, NF_4S}};
 
   if (instr->Mask(NEON2RegMiscOpcode) <= NEON_NEG_opcode) {
     // These instructions all use a two bit size field, except NOT and RBIT,
     // which use the field to encode the operation.
     switch (instr->Mask(NEON2RegMiscMask)) {
-      case NEON_REV64:     mnemonic = "rev64"; break;
-      case NEON_REV32:     mnemonic = "rev32"; break;
-      case NEON_REV16:     mnemonic = "rev16"; break;
+      case NEON_REV64:
+        mnemonic = "rev64";
+        break;
+      case NEON_REV32:
+        mnemonic = "rev32";
+        break;
+      case NEON_REV16:
+        mnemonic = "rev16";
+        break;
       case NEON_SADDLP:
         mnemonic = "saddlp";
         nfd.SetFormatMap(0, &map_lp_ta);
@@ -1443,11 +1916,21 @@
         mnemonic = "uaddlp";
         nfd.SetFormatMap(0, &map_lp_ta);
         break;
-      case NEON_SUQADD:    mnemonic = "suqadd"; break;
-      case NEON_USQADD:    mnemonic = "usqadd"; break;
-      case NEON_CLS:       mnemonic = "cls"; break;
-      case NEON_CLZ:       mnemonic = "clz"; break;
-      case NEON_CNT:       mnemonic = "cnt"; break;
+      case NEON_SUQADD:
+        mnemonic = "suqadd";
+        break;
+      case NEON_USQADD:
+        mnemonic = "usqadd";
+        break;
+      case NEON_CLS:
+        mnemonic = "cls";
+        break;
+      case NEON_CLZ:
+        mnemonic = "clz";
+        break;
+      case NEON_CNT:
+        mnemonic = "cnt";
+        break;
       case NEON_SADALP:
         mnemonic = "sadalp";
         nfd.SetFormatMap(0, &map_lp_ta);
@@ -1456,20 +1939,48 @@
         mnemonic = "uadalp";
         nfd.SetFormatMap(0, &map_lp_ta);
         break;
-      case NEON_SQABS:     mnemonic = "sqabs"; break;
-      case NEON_SQNEG:     mnemonic = "sqneg"; break;
-      case NEON_CMGT_zero: mnemonic = "cmgt"; form = form_cmp_zero; break;
-      case NEON_CMGE_zero: mnemonic = "cmge"; form = form_cmp_zero; break;
-      case NEON_CMEQ_zero: mnemonic = "cmeq"; form = form_cmp_zero; break;
-      case NEON_CMLE_zero: mnemonic = "cmle"; form = form_cmp_zero; break;
-      case NEON_CMLT_zero: mnemonic = "cmlt"; form = form_cmp_zero; break;
-      case NEON_ABS:       mnemonic = "abs"; break;
-      case NEON_NEG:       mnemonic = "neg"; break;
+      case NEON_SQABS:
+        mnemonic = "sqabs";
+        break;
+      case NEON_SQNEG:
+        mnemonic = "sqneg";
+        break;
+      case NEON_CMGT_zero:
+        mnemonic = "cmgt";
+        form = form_cmp_zero;
+        break;
+      case NEON_CMGE_zero:
+        mnemonic = "cmge";
+        form = form_cmp_zero;
+        break;
+      case NEON_CMEQ_zero:
+        mnemonic = "cmeq";
+        form = form_cmp_zero;
+        break;
+      case NEON_CMLE_zero:
+        mnemonic = "cmle";
+        form = form_cmp_zero;
+        break;
+      case NEON_CMLT_zero:
+        mnemonic = "cmlt";
+        form = form_cmp_zero;
+        break;
+      case NEON_ABS:
+        mnemonic = "abs";
+        break;
+      case NEON_NEG:
+        mnemonic = "neg";
+        break;
       case NEON_RBIT_NOT:
         switch (instr->FPType()) {
-          case 0: mnemonic = "mvn"; break;
-          case 1: mnemonic = "rbit"; break;
-          default: form = "(NEON2RegMisc)";
+          case 0:
+            mnemonic = "mvn";
+            break;
+          case 1:
+            mnemonic = "rbit";
+            break;
+          default:
+            form = "(NEON2RegMisc)";
         }
         nfd.SetFormatMaps(nfd.LogicalFormatMap());
         break;
@@ -1479,8 +1990,12 @@
     // SHLL, SQXTN and UQXTN, which use a two bit size field.
     nfd.SetFormatMaps(nfd.FPFormatMap());
     switch (instr->Mask(NEON2RegMiscFPMask)) {
-      case NEON_FABS:   mnemonic = "fabs"; break;
-      case NEON_FNEG:   mnemonic = "fneg"; break;
+      case NEON_FABS:
+        mnemonic = "fabs";
+        break;
+      case NEON_FNEG:
+        mnemonic = "fneg";
+        break;
       case NEON_FCVTN:
         mnemonic = instr->Mask(NEON_Q) ? "fcvtn2" : "fcvtn";
         nfd.SetFormatMap(0, &map_cvt_tb);
@@ -1496,35 +2011,98 @@
         nfd.SetFormatMap(0, &map_cvt_ta);
         nfd.SetFormatMap(1, &map_cvt_tb);
         break;
-      case NEON_FRINTN: mnemonic = "frintn"; break;
-      case NEON_FRINTA: mnemonic = "frinta"; break;
-      case NEON_FRINTP: mnemonic = "frintp"; break;
-      case NEON_FRINTM: mnemonic = "frintm"; break;
-      case NEON_FRINTX: mnemonic = "frintx"; break;
-      case NEON_FRINTZ: mnemonic = "frintz"; break;
-      case NEON_FRINTI: mnemonic = "frinti"; break;
-      case NEON_FCVTNS: mnemonic = "fcvtns"; break;
-      case NEON_FCVTNU: mnemonic = "fcvtnu"; break;
-      case NEON_FCVTPS: mnemonic = "fcvtps"; break;
-      case NEON_FCVTPU: mnemonic = "fcvtpu"; break;
-      case NEON_FCVTMS: mnemonic = "fcvtms"; break;
-      case NEON_FCVTMU: mnemonic = "fcvtmu"; break;
-      case NEON_FCVTZS: mnemonic = "fcvtzs"; break;
-      case NEON_FCVTZU: mnemonic = "fcvtzu"; break;
-      case NEON_FCVTAS: mnemonic = "fcvtas"; break;
-      case NEON_FCVTAU: mnemonic = "fcvtau"; break;
-      case NEON_FSQRT:  mnemonic = "fsqrt"; break;
-      case NEON_SCVTF:  mnemonic = "scvtf"; break;
-      case NEON_UCVTF:  mnemonic = "ucvtf"; break;
-      case NEON_URSQRTE: mnemonic = "ursqrte"; break;
-      case NEON_URECPE:  mnemonic = "urecpe";  break;
-      case NEON_FRSQRTE: mnemonic = "frsqrte"; break;
-      case NEON_FRECPE:  mnemonic = "frecpe";  break;
-      case NEON_FCMGT_zero: mnemonic = "fcmgt"; form = form_fcmp_zero; break;
-      case NEON_FCMGE_zero: mnemonic = "fcmge"; form = form_fcmp_zero; break;
-      case NEON_FCMEQ_zero: mnemonic = "fcmeq"; form = form_fcmp_zero; break;
-      case NEON_FCMLE_zero: mnemonic = "fcmle"; form = form_fcmp_zero; break;
-      case NEON_FCMLT_zero: mnemonic = "fcmlt"; form = form_fcmp_zero; break;
+      case NEON_FRINTN:
+        mnemonic = "frintn";
+        break;
+      case NEON_FRINTA:
+        mnemonic = "frinta";
+        break;
+      case NEON_FRINTP:
+        mnemonic = "frintp";
+        break;
+      case NEON_FRINTM:
+        mnemonic = "frintm";
+        break;
+      case NEON_FRINTX:
+        mnemonic = "frintx";
+        break;
+      case NEON_FRINTZ:
+        mnemonic = "frintz";
+        break;
+      case NEON_FRINTI:
+        mnemonic = "frinti";
+        break;
+      case NEON_FCVTNS:
+        mnemonic = "fcvtns";
+        break;
+      case NEON_FCVTNU:
+        mnemonic = "fcvtnu";
+        break;
+      case NEON_FCVTPS:
+        mnemonic = "fcvtps";
+        break;
+      case NEON_FCVTPU:
+        mnemonic = "fcvtpu";
+        break;
+      case NEON_FCVTMS:
+        mnemonic = "fcvtms";
+        break;
+      case NEON_FCVTMU:
+        mnemonic = "fcvtmu";
+        break;
+      case NEON_FCVTZS:
+        mnemonic = "fcvtzs";
+        break;
+      case NEON_FCVTZU:
+        mnemonic = "fcvtzu";
+        break;
+      case NEON_FCVTAS:
+        mnemonic = "fcvtas";
+        break;
+      case NEON_FCVTAU:
+        mnemonic = "fcvtau";
+        break;
+      case NEON_FSQRT:
+        mnemonic = "fsqrt";
+        break;
+      case NEON_SCVTF:
+        mnemonic = "scvtf";
+        break;
+      case NEON_UCVTF:
+        mnemonic = "ucvtf";
+        break;
+      case NEON_URSQRTE:
+        mnemonic = "ursqrte";
+        break;
+      case NEON_URECPE:
+        mnemonic = "urecpe";
+        break;
+      case NEON_FRSQRTE:
+        mnemonic = "frsqrte";
+        break;
+      case NEON_FRECPE:
+        mnemonic = "frecpe";
+        break;
+      case NEON_FCMGT_zero:
+        mnemonic = "fcmgt";
+        form = form_fcmp_zero;
+        break;
+      case NEON_FCMGE_zero:
+        mnemonic = "fcmge";
+        form = form_fcmp_zero;
+        break;
+      case NEON_FCMEQ_zero:
+        mnemonic = "fcmeq";
+        form = form_fcmp_zero;
+        break;
+      case NEON_FCMLE_zero:
+        mnemonic = "fcmle";
+        form = form_fcmp_zero;
+        break;
+      case NEON_FCMLT_zero:
+        mnemonic = "fcmlt";
+        form = form_fcmp_zero;
+        break;
       default:
         if ((NEON_XTN_opcode <= instr->Mask(NEON2RegMiscOpcode)) &&
             (instr->Mask(NEON2RegMiscOpcode) <= NEON_UQXTN_opcode)) {
@@ -1532,19 +2110,35 @@
           nfd.SetFormatMap(1, nfd.LongIntegerFormatMap());
 
           switch (instr->Mask(NEON2RegMiscMask)) {
-            case NEON_XTN:    mnemonic = "xtn"; break;
-            case NEON_SQXTN:  mnemonic = "sqxtn"; break;
-            case NEON_UQXTN:  mnemonic = "uqxtn"; break;
-            case NEON_SQXTUN: mnemonic = "sqxtun"; break;
+            case NEON_XTN:
+              mnemonic = "xtn";
+              break;
+            case NEON_SQXTN:
+              mnemonic = "sqxtn";
+              break;
+            case NEON_UQXTN:
+              mnemonic = "uqxtn";
+              break;
+            case NEON_SQXTUN:
+              mnemonic = "sqxtun";
+              break;
             case NEON_SHLL:
               mnemonic = "shll";
               nfd.SetFormatMap(0, nfd.LongIntegerFormatMap());
               nfd.SetFormatMap(1, nfd.IntegerFormatMap());
               switch (instr->NEONSize()) {
-                case 0: form = "'Vd.%s, 'Vn.%s, #8"; break;
-                case 1: form = "'Vd.%s, 'Vn.%s, #16"; break;
-                case 2: form = "'Vd.%s, 'Vn.%s, #32"; break;
-                default: form = "(NEON2RegMisc)";
+                case 0:
+                  form = "'Vd.%s, 'Vn.%s, #8";
+                  break;
+                case 1:
+                  form = "'Vd.%s, 'Vn.%s, #16";
+                  break;
+                case 2:
+                  form = "'Vd.%s, 'Vn.%s, #32";
+                  break;
+                default:
+                  Format(instr, "unallocated", "(NEON2RegMisc)");
+                  return;
               }
           }
           Format(instr, nfd.Mnemonic(mnemonic), nfd.Substitute(form));
@@ -1558,14 +2152,16 @@
 }
 
 
-void Disassembler::VisitNEON3Same(const Instruction* instr) {
+void Disassembler::VisitNEON3Same(const Instruction *instr) {
   const char *mnemonic = "unimplemented";
   const char *form = "'Vd.%s, 'Vn.%s, 'Vm.%s";
   NEONFormatDecoder nfd(instr);
 
   if (instr->Mask(NEON3SameLogicalFMask) == NEON3SameLogicalFixed) {
     switch (instr->Mask(NEON3SameLogicalMask)) {
-      case NEON_AND: mnemonic = "and"; break;
+      case NEON_AND:
+        mnemonic = "and";
+        break;
       case NEON_ORR:
         mnemonic = "orr";
         if (instr->Rm() == instr->Rn()) {
@@ -1573,54 +2169,68 @@
           form = "'Vd.%s, 'Vn.%s";
         }
         break;
-      case NEON_ORN: mnemonic = "orn"; break;
-      case NEON_EOR: mnemonic = "eor"; break;
-      case NEON_BIC: mnemonic = "bic"; break;
-      case NEON_BIF: mnemonic = "bif"; break;
-      case NEON_BIT: mnemonic = "bit"; break;
-      case NEON_BSL: mnemonic = "bsl"; break;
-      default: form = "(NEON3Same)";
+      case NEON_ORN:
+        mnemonic = "orn";
+        break;
+      case NEON_EOR:
+        mnemonic = "eor";
+        break;
+      case NEON_BIC:
+        mnemonic = "bic";
+        break;
+      case NEON_BIF:
+        mnemonic = "bif";
+        break;
+      case NEON_BIT:
+        mnemonic = "bit";
+        break;
+      case NEON_BSL:
+        mnemonic = "bsl";
+        break;
+      default:
+        form = "(NEON3Same)";
     }
     nfd.SetFormatMaps(nfd.LogicalFormatMap());
   } else {
-    static const char *mnemonics[] = {
-        "shadd", "uhadd", "shadd", "uhadd",
-        "sqadd", "uqadd", "sqadd", "uqadd",
-        "srhadd", "urhadd", "srhadd", "urhadd",
-        NULL, NULL, NULL, NULL,  // Handled by logical cases above.
-        "shsub", "uhsub", "shsub", "uhsub",
-        "sqsub", "uqsub", "sqsub", "uqsub",
-        "cmgt", "cmhi", "cmgt", "cmhi",
-        "cmge", "cmhs", "cmge", "cmhs",
-        "sshl", "ushl", "sshl", "ushl",
-        "sqshl", "uqshl", "sqshl", "uqshl",
-        "srshl", "urshl", "srshl", "urshl",
-        "sqrshl", "uqrshl", "sqrshl", "uqrshl",
-        "smax", "umax", "smax", "umax",
-        "smin", "umin", "smin", "umin",
-        "sabd", "uabd", "sabd", "uabd",
-        "saba", "uaba", "saba", "uaba",
-        "add", "sub", "add", "sub",
-        "cmtst", "cmeq", "cmtst", "cmeq",
-        "mla", "mls", "mla", "mls",
-        "mul", "pmul", "mul", "pmul",
-        "smaxp", "umaxp", "smaxp", "umaxp",
-        "sminp", "uminp", "sminp", "uminp",
-        "sqdmulh", "sqrdmulh", "sqdmulh", "sqrdmulh",
-        "addp", "unallocated", "addp", "unallocated",
-        "fmaxnm", "fmaxnmp", "fminnm", "fminnmp",
-        "fmla", "unallocated", "fmls", "unallocated",
-        "fadd", "faddp", "fsub", "fabd",
-        "fmulx", "fmul", "unallocated", "unallocated",
-        "fcmeq", "fcmge", "unallocated", "fcmgt",
-        "unallocated", "facge", "unallocated", "facgt",
-        "fmax", "fmaxp", "fmin", "fminp",
-        "frecps", "fdiv", "frsqrts", "unallocated"};
+    static const char *mnemonics[] =
+        {"shadd",       "uhadd",       "shadd",       "uhadd",
+         "sqadd",       "uqadd",       "sqadd",       "uqadd",
+         "srhadd",      "urhadd",      "srhadd",      "urhadd",
+         // Handled by logical cases above.
+         NULL,          NULL,          NULL,          NULL,
+         "shsub",       "uhsub",       "shsub",       "uhsub",
+         "sqsub",       "uqsub",       "sqsub",       "uqsub",
+         "cmgt",        "cmhi",        "cmgt",        "cmhi",
+         "cmge",        "cmhs",        "cmge",        "cmhs",
+         "sshl",        "ushl",        "sshl",        "ushl",
+         "sqshl",       "uqshl",       "sqshl",       "uqshl",
+         "srshl",       "urshl",       "srshl",       "urshl",
+         "sqrshl",      "uqrshl",      "sqrshl",      "uqrshl",
+         "smax",        "umax",        "smax",        "umax",
+         "smin",        "umin",        "smin",        "umin",
+         "sabd",        "uabd",        "sabd",        "uabd",
+         "saba",        "uaba",        "saba",        "uaba",
+         "add",         "sub",         "add",         "sub",
+         "cmtst",       "cmeq",        "cmtst",       "cmeq",
+         "mla",         "mls",         "mla",         "mls",
+         "mul",         "pmul",        "mul",         "pmul",
+         "smaxp",       "umaxp",       "smaxp",       "umaxp",
+         "sminp",       "uminp",       "sminp",       "uminp",
+         "sqdmulh",     "sqrdmulh",    "sqdmulh",     "sqrdmulh",
+         "addp",        "unallocated", "addp",        "unallocated",
+         "fmaxnm",      "fmaxnmp",     "fminnm",      "fminnmp",
+         "fmla",        "unallocated", "fmls",        "unallocated",
+         "fadd",        "faddp",       "fsub",        "fabd",
+         "fmulx",       "fmul",        "unallocated", "unallocated",
+         "fcmeq",       "fcmge",       "unallocated", "fcmgt",
+         "unallocated", "facge",       "unallocated", "facgt",
+         "fmax",        "fmaxp",       "fmin",        "fminp",
+         "frecps",      "fdiv",        "frsqrts",     "unallocated"};
 
     // Operation is determined by the opcode bits (15-11), the top bit of
     // size (23) and the U bit (29).
-    unsigned index = (instr->Bits(15, 11) << 2) | (instr->Bit(23) << 1) |
-                     instr->Bit(29);
+    unsigned index =
+        (instr->Bits(15, 11) << 2) | (instr->Bit(23) << 1) | instr->Bit(29);
     VIXL_ASSERT(index < (sizeof(mnemonics) / sizeof(mnemonics[0])));
     mnemonic = mnemonics[index];
     // Assert that index is not one of the previously handled logical
@@ -1635,7 +2245,7 @@
 }
 
 
-void Disassembler::VisitNEON3Different(const Instruction* instr) {
+void Disassembler::VisitNEON3Different(const Instruction *instr) {
   const char *mnemonic = "unimplemented";
   const char *form = "'Vd.%s, 'Vn.%s, 'Vm.%s";
 
@@ -1644,24 +2254,60 @@
 
   // Ignore the Q bit. Appending a "2" suffix is handled later.
   switch (instr->Mask(NEON3DifferentMask) & ~NEON_Q) {
-    case NEON_PMULL:    mnemonic = "pmull";   break;
-    case NEON_SABAL:    mnemonic = "sabal";   break;
-    case NEON_SABDL:    mnemonic = "sabdl";   break;
-    case NEON_SADDL:    mnemonic = "saddl";   break;
-    case NEON_SMLAL:    mnemonic = "smlal";   break;
-    case NEON_SMLSL:    mnemonic = "smlsl";   break;
-    case NEON_SMULL:    mnemonic = "smull";   break;
-    case NEON_SSUBL:    mnemonic = "ssubl";   break;
-    case NEON_SQDMLAL:  mnemonic = "sqdmlal"; break;
-    case NEON_SQDMLSL:  mnemonic = "sqdmlsl"; break;
-    case NEON_SQDMULL:  mnemonic = "sqdmull"; break;
-    case NEON_UABAL:    mnemonic = "uabal";   break;
-    case NEON_UABDL:    mnemonic = "uabdl";   break;
-    case NEON_UADDL:    mnemonic = "uaddl";   break;
-    case NEON_UMLAL:    mnemonic = "umlal";   break;
-    case NEON_UMLSL:    mnemonic = "umlsl";   break;
-    case NEON_UMULL:    mnemonic = "umull";   break;
-    case NEON_USUBL:    mnemonic = "usubl";   break;
+    case NEON_PMULL:
+      mnemonic = "pmull";
+      break;
+    case NEON_SABAL:
+      mnemonic = "sabal";
+      break;
+    case NEON_SABDL:
+      mnemonic = "sabdl";
+      break;
+    case NEON_SADDL:
+      mnemonic = "saddl";
+      break;
+    case NEON_SMLAL:
+      mnemonic = "smlal";
+      break;
+    case NEON_SMLSL:
+      mnemonic = "smlsl";
+      break;
+    case NEON_SMULL:
+      mnemonic = "smull";
+      break;
+    case NEON_SSUBL:
+      mnemonic = "ssubl";
+      break;
+    case NEON_SQDMLAL:
+      mnemonic = "sqdmlal";
+      break;
+    case NEON_SQDMLSL:
+      mnemonic = "sqdmlsl";
+      break;
+    case NEON_SQDMULL:
+      mnemonic = "sqdmull";
+      break;
+    case NEON_UABAL:
+      mnemonic = "uabal";
+      break;
+    case NEON_UABDL:
+      mnemonic = "uabdl";
+      break;
+    case NEON_UADDL:
+      mnemonic = "uaddl";
+      break;
+    case NEON_UMLAL:
+      mnemonic = "umlal";
+      break;
+    case NEON_UMLSL:
+      mnemonic = "umlsl";
+      break;
+    case NEON_UMULL:
+      mnemonic = "umull";
+      break;
+    case NEON_USUBL:
+      mnemonic = "usubl";
+      break;
     case NEON_SADDW:
       mnemonic = "saddw";
       nfd.SetFormatMap(1, nfd.LongIntegerFormatMap());
@@ -1698,36 +2344,58 @@
       nfd.SetFormatMaps(nfd.LongIntegerFormatMap());
       nfd.SetFormatMap(0, nfd.IntegerFormatMap());
       break;
-    default: form = "(NEON3Different)";
+    default:
+      form = "(NEON3Different)";
   }
   Format(instr, nfd.Mnemonic(mnemonic), nfd.Substitute(form));
 }
 
 
-void Disassembler::VisitNEONAcrossLanes(const Instruction* instr) {
+void Disassembler::VisitNEONAcrossLanes(const Instruction *instr) {
   const char *mnemonic = "unimplemented";
   const char *form = "%sd, 'Vn.%s";
 
-  NEONFormatDecoder nfd(instr, NEONFormatDecoder::ScalarFormatMap(),
-                               NEONFormatDecoder::IntegerFormatMap());
+  NEONFormatDecoder nfd(instr,
+                        NEONFormatDecoder::ScalarFormatMap(),
+                        NEONFormatDecoder::IntegerFormatMap());
 
   if (instr->Mask(NEONAcrossLanesFPFMask) == NEONAcrossLanesFPFixed) {
     nfd.SetFormatMap(0, nfd.FPScalarFormatMap());
     nfd.SetFormatMap(1, nfd.FPFormatMap());
     switch (instr->Mask(NEONAcrossLanesFPMask)) {
-      case NEON_FMAXV: mnemonic = "fmaxv"; break;
-      case NEON_FMINV: mnemonic = "fminv"; break;
-      case NEON_FMAXNMV: mnemonic = "fmaxnmv"; break;
-      case NEON_FMINNMV: mnemonic = "fminnmv"; break;
-      default: form = "(NEONAcrossLanes)"; break;
+      case NEON_FMAXV:
+        mnemonic = "fmaxv";
+        break;
+      case NEON_FMINV:
+        mnemonic = "fminv";
+        break;
+      case NEON_FMAXNMV:
+        mnemonic = "fmaxnmv";
+        break;
+      case NEON_FMINNMV:
+        mnemonic = "fminnmv";
+        break;
+      default:
+        form = "(NEONAcrossLanes)";
+        break;
     }
   } else if (instr->Mask(NEONAcrossLanesFMask) == NEONAcrossLanesFixed) {
     switch (instr->Mask(NEONAcrossLanesMask)) {
-      case NEON_ADDV:  mnemonic = "addv"; break;
-      case NEON_SMAXV: mnemonic = "smaxv"; break;
-      case NEON_SMINV: mnemonic = "sminv"; break;
-      case NEON_UMAXV: mnemonic = "umaxv"; break;
-      case NEON_UMINV: mnemonic = "uminv"; break;
+      case NEON_ADDV:
+        mnemonic = "addv";
+        break;
+      case NEON_SMAXV:
+        mnemonic = "smaxv";
+        break;
+      case NEON_SMINV:
+        mnemonic = "sminv";
+        break;
+      case NEON_UMAXV:
+        mnemonic = "umaxv";
+        break;
+      case NEON_UMINV:
+        mnemonic = "uminv";
+        break;
       case NEON_SADDLV:
         mnemonic = "saddlv";
         nfd.SetFormatMap(0, nfd.LongScalarFormatMap());
@@ -1736,49 +2404,102 @@
         mnemonic = "uaddlv";
         nfd.SetFormatMap(0, nfd.LongScalarFormatMap());
         break;
-      default: form = "(NEONAcrossLanes)"; break;
+      default:
+        form = "(NEONAcrossLanes)";
+        break;
     }
   }
-  Format(instr, mnemonic, nfd.Substitute(form,
-      NEONFormatDecoder::kPlaceholder, NEONFormatDecoder::kFormat));
+  Format(instr,
+         mnemonic,
+         nfd.Substitute(form,
+                        NEONFormatDecoder::kPlaceholder,
+                        NEONFormatDecoder::kFormat));
 }
 
 
-void Disassembler::VisitNEONByIndexedElement(const Instruction* instr) {
+void Disassembler::VisitNEONByIndexedElement(const Instruction *instr) {
   const char *mnemonic = "unimplemented";
   bool l_instr = false;
   bool fp_instr = false;
 
   const char *form = "'Vd.%s, 'Vn.%s, 'Ve.%s['IVByElemIndex]";
 
-  static const NEONFormatMap map_ta = {
-    {23, 22}, {NF_UNDEF, NF_4S, NF_2D}
-  };
-  NEONFormatDecoder nfd(instr, &map_ta,
+  static const NEONFormatMap map_ta = {{23, 22}, {NF_UNDEF, NF_4S, NF_2D}};
+  NEONFormatDecoder nfd(instr,
+                        &map_ta,
                         NEONFormatDecoder::IntegerFormatMap(),
                         NEONFormatDecoder::ScalarFormatMap());
 
   switch (instr->Mask(NEONByIndexedElementMask)) {
-    case NEON_SMULL_byelement:    mnemonic = "smull"; l_instr = true; break;
-    case NEON_UMULL_byelement:    mnemonic = "umull"; l_instr = true; break;
-    case NEON_SMLAL_byelement:    mnemonic = "smlal"; l_instr = true; break;
-    case NEON_UMLAL_byelement:    mnemonic = "umlal"; l_instr = true; break;
-    case NEON_SMLSL_byelement:    mnemonic = "smlsl"; l_instr = true; break;
-    case NEON_UMLSL_byelement:    mnemonic = "umlsl"; l_instr = true; break;
-    case NEON_SQDMULL_byelement:  mnemonic = "sqdmull"; l_instr = true; break;
-    case NEON_SQDMLAL_byelement:  mnemonic = "sqdmlal"; l_instr = true; break;
-    case NEON_SQDMLSL_byelement:  mnemonic = "sqdmlsl"; l_instr = true; break;
-    case NEON_MUL_byelement:      mnemonic = "mul"; break;
-    case NEON_MLA_byelement:      mnemonic = "mla"; break;
-    case NEON_MLS_byelement:      mnemonic = "mls"; break;
-    case NEON_SQDMULH_byelement:  mnemonic = "sqdmulh";  break;
-    case NEON_SQRDMULH_byelement: mnemonic = "sqrdmulh"; break;
+    case NEON_SMULL_byelement:
+      mnemonic = "smull";
+      l_instr = true;
+      break;
+    case NEON_UMULL_byelement:
+      mnemonic = "umull";
+      l_instr = true;
+      break;
+    case NEON_SMLAL_byelement:
+      mnemonic = "smlal";
+      l_instr = true;
+      break;
+    case NEON_UMLAL_byelement:
+      mnemonic = "umlal";
+      l_instr = true;
+      break;
+    case NEON_SMLSL_byelement:
+      mnemonic = "smlsl";
+      l_instr = true;
+      break;
+    case NEON_UMLSL_byelement:
+      mnemonic = "umlsl";
+      l_instr = true;
+      break;
+    case NEON_SQDMULL_byelement:
+      mnemonic = "sqdmull";
+      l_instr = true;
+      break;
+    case NEON_SQDMLAL_byelement:
+      mnemonic = "sqdmlal";
+      l_instr = true;
+      break;
+    case NEON_SQDMLSL_byelement:
+      mnemonic = "sqdmlsl";
+      l_instr = true;
+      break;
+    case NEON_MUL_byelement:
+      mnemonic = "mul";
+      break;
+    case NEON_MLA_byelement:
+      mnemonic = "mla";
+      break;
+    case NEON_MLS_byelement:
+      mnemonic = "mls";
+      break;
+    case NEON_SQDMULH_byelement:
+      mnemonic = "sqdmulh";
+      break;
+    case NEON_SQRDMULH_byelement:
+      mnemonic = "sqrdmulh";
+      break;
     default:
       switch (instr->Mask(NEONByIndexedElementFPMask)) {
-        case NEON_FMUL_byelement:  mnemonic = "fmul";  fp_instr = true; break;
-        case NEON_FMLA_byelement:  mnemonic = "fmla";  fp_instr = true; break;
-        case NEON_FMLS_byelement:  mnemonic = "fmls";  fp_instr = true; break;
-        case NEON_FMULX_byelement: mnemonic = "fmulx"; fp_instr = true; break;
+        case NEON_FMUL_byelement:
+          mnemonic = "fmul";
+          fp_instr = true;
+          break;
+        case NEON_FMLA_byelement:
+          mnemonic = "fmla";
+          fp_instr = true;
+          break;
+        case NEON_FMLS_byelement:
+          mnemonic = "fmls";
+          fp_instr = true;
+          break;
+        case NEON_FMULX_byelement:
+          mnemonic = "fmulx";
+          fp_instr = true;
+          break;
       }
   }
 
@@ -1794,12 +2515,13 @@
 }
 
 
-void Disassembler::VisitNEONCopy(const Instruction* instr) {
+void Disassembler::VisitNEONCopy(const Instruction *instr) {
   const char *mnemonic = "unimplemented";
   const char *form = "(NEONCopy)";
 
-  NEONFormatDecoder nfd(instr, NEONFormatDecoder::TriangularFormatMap(),
-                               NEONFormatDecoder::TriangularScalarFormatMap());
+  NEONFormatDecoder nfd(instr,
+                        NEONFormatDecoder::TriangularFormatMap(),
+                        NEONFormatDecoder::TriangularScalarFormatMap());
 
   if (instr->Mask(NEONCopyInsElementMask) == NEON_INS_ELEMENT) {
     mnemonic = "mov";
@@ -1844,7 +2566,7 @@
 }
 
 
-void Disassembler::VisitNEONExtract(const Instruction* instr) {
+void Disassembler::VisitNEONExtract(const Instruction *instr) {
   const char *mnemonic = "unimplemented";
   const char *form = "(NEONExtract)";
   NEONFormatDecoder nfd(instr, NEONFormatDecoder::LogicalFormatMap());
@@ -1856,9 +2578,9 @@
 }
 
 
-void Disassembler::VisitNEONLoadStoreMultiStruct(const Instruction* instr) {
-  const char *mnemonic = "unimplemented";
-  const char *form = "(NEONLoadStoreMultiStruct)";
+void Disassembler::VisitNEONLoadStoreMultiStruct(const Instruction *instr) {
+  const char *mnemonic = NULL;
+  const char *form = NULL;
   const char *form_1v = "{'Vt.%1$s}, ['Xns]";
   const char *form_2v = "{'Vt.%1$s, 'Vt2.%1$s}, ['Xns]";
   const char *form_3v = "{'Vt.%1$s, 'Vt2.%1$s, 'Vt3.%1$s}, ['Xns]";
@@ -1866,21 +2588,87 @@
   NEONFormatDecoder nfd(instr, NEONFormatDecoder::LoadStoreFormatMap());
 
   switch (instr->Mask(NEONLoadStoreMultiStructMask)) {
-    case NEON_LD1_1v: mnemonic = "ld1"; form = form_1v; break;
-    case NEON_LD1_2v: mnemonic = "ld1"; form = form_2v; break;
-    case NEON_LD1_3v: mnemonic = "ld1"; form = form_3v; break;
-    case NEON_LD1_4v: mnemonic = "ld1"; form = form_4v; break;
-    case NEON_LD2: mnemonic = "ld2"; form = form_2v; break;
-    case NEON_LD3: mnemonic = "ld3"; form = form_3v; break;
-    case NEON_LD4: mnemonic = "ld4"; form = form_4v; break;
-    case NEON_ST1_1v: mnemonic = "st1"; form = form_1v; break;
-    case NEON_ST1_2v: mnemonic = "st1"; form = form_2v; break;
-    case NEON_ST1_3v: mnemonic = "st1"; form = form_3v; break;
-    case NEON_ST1_4v: mnemonic = "st1"; form = form_4v; break;
-    case NEON_ST2: mnemonic = "st2"; form = form_2v; break;
-    case NEON_ST3: mnemonic = "st3"; form = form_3v; break;
-    case NEON_ST4: mnemonic = "st4"; form = form_4v; break;
-    default: break;
+    case NEON_LD1_1v:
+      mnemonic = "ld1";
+      form = form_1v;
+      break;
+    case NEON_LD1_2v:
+      mnemonic = "ld1";
+      form = form_2v;
+      break;
+    case NEON_LD1_3v:
+      mnemonic = "ld1";
+      form = form_3v;
+      break;
+    case NEON_LD1_4v:
+      mnemonic = "ld1";
+      form = form_4v;
+      break;
+    case NEON_LD2:
+      mnemonic = "ld2";
+      form = form_2v;
+      break;
+    case NEON_LD3:
+      mnemonic = "ld3";
+      form = form_3v;
+      break;
+    case NEON_LD4:
+      mnemonic = "ld4";
+      form = form_4v;
+      break;
+    case NEON_ST1_1v:
+      mnemonic = "st1";
+      form = form_1v;
+      break;
+    case NEON_ST1_2v:
+      mnemonic = "st1";
+      form = form_2v;
+      break;
+    case NEON_ST1_3v:
+      mnemonic = "st1";
+      form = form_3v;
+      break;
+    case NEON_ST1_4v:
+      mnemonic = "st1";
+      form = form_4v;
+      break;
+    case NEON_ST2:
+      mnemonic = "st2";
+      form = form_2v;
+      break;
+    case NEON_ST3:
+      mnemonic = "st3";
+      form = form_3v;
+      break;
+    case NEON_ST4:
+      mnemonic = "st4";
+      form = form_4v;
+      break;
+    default:
+      break;
+  }
+
+  // Work out unallocated encodings.
+  bool allocated = (mnemonic != NULL);
+  switch (instr->Mask(NEONLoadStoreMultiStructMask)) {
+    case NEON_LD2:
+    case NEON_LD3:
+    case NEON_LD4:
+    case NEON_ST2:
+    case NEON_ST3:
+    case NEON_ST4:
+      // LD[2-4] and ST[2-4] cannot use .1d format.
+      allocated = (instr->NEONQ() != 0) || (instr->NEONLSSize() != 3);
+      break;
+    default:
+      break;
+  }
+  if (allocated) {
+    VIXL_ASSERT(mnemonic != NULL);
+    VIXL_ASSERT(form != NULL);
+  } else {
+    mnemonic = "unallocated";
+    form = "(NEONLoadStoreMultiStruct)";
   }
 
   Format(instr, mnemonic, nfd.Substitute(form));
@@ -1888,9 +2676,9 @@
 
 
 void Disassembler::VisitNEONLoadStoreMultiStructPostIndex(
-    const Instruction* instr) {
-  const char *mnemonic = "unimplemented";
-  const char *form = "(NEONLoadStoreMultiStructPostIndex)";
+    const Instruction *instr) {
+  const char *mnemonic = NULL;
+  const char *form = NULL;
   const char *form_1v = "{'Vt.%1$s}, ['Xns], 'Xmr1";
   const char *form_2v = "{'Vt.%1$s, 'Vt2.%1$s}, ['Xns], 'Xmr2";
   const char *form_3v = "{'Vt.%1$s, 'Vt2.%1$s, 'Vt3.%1$s}, ['Xns], 'Xmr3";
@@ -1899,30 +2687,96 @@
   NEONFormatDecoder nfd(instr, NEONFormatDecoder::LoadStoreFormatMap());
 
   switch (instr->Mask(NEONLoadStoreMultiStructPostIndexMask)) {
-    case NEON_LD1_1v_post: mnemonic = "ld1"; form = form_1v; break;
-    case NEON_LD1_2v_post: mnemonic = "ld1"; form = form_2v; break;
-    case NEON_LD1_3v_post: mnemonic = "ld1"; form = form_3v; break;
-    case NEON_LD1_4v_post: mnemonic = "ld1"; form = form_4v; break;
-    case NEON_LD2_post: mnemonic = "ld2"; form = form_2v; break;
-    case NEON_LD3_post: mnemonic = "ld3"; form = form_3v; break;
-    case NEON_LD4_post: mnemonic = "ld4"; form = form_4v; break;
-    case NEON_ST1_1v_post: mnemonic = "st1"; form = form_1v; break;
-    case NEON_ST1_2v_post: mnemonic = "st1"; form = form_2v; break;
-    case NEON_ST1_3v_post: mnemonic = "st1"; form = form_3v; break;
-    case NEON_ST1_4v_post: mnemonic = "st1"; form = form_4v; break;
-    case NEON_ST2_post: mnemonic = "st2"; form = form_2v; break;
-    case NEON_ST3_post: mnemonic = "st3"; form = form_3v; break;
-    case NEON_ST4_post: mnemonic = "st4"; form = form_4v; break;
-    default: break;
+    case NEON_LD1_1v_post:
+      mnemonic = "ld1";
+      form = form_1v;
+      break;
+    case NEON_LD1_2v_post:
+      mnemonic = "ld1";
+      form = form_2v;
+      break;
+    case NEON_LD1_3v_post:
+      mnemonic = "ld1";
+      form = form_3v;
+      break;
+    case NEON_LD1_4v_post:
+      mnemonic = "ld1";
+      form = form_4v;
+      break;
+    case NEON_LD2_post:
+      mnemonic = "ld2";
+      form = form_2v;
+      break;
+    case NEON_LD3_post:
+      mnemonic = "ld3";
+      form = form_3v;
+      break;
+    case NEON_LD4_post:
+      mnemonic = "ld4";
+      form = form_4v;
+      break;
+    case NEON_ST1_1v_post:
+      mnemonic = "st1";
+      form = form_1v;
+      break;
+    case NEON_ST1_2v_post:
+      mnemonic = "st1";
+      form = form_2v;
+      break;
+    case NEON_ST1_3v_post:
+      mnemonic = "st1";
+      form = form_3v;
+      break;
+    case NEON_ST1_4v_post:
+      mnemonic = "st1";
+      form = form_4v;
+      break;
+    case NEON_ST2_post:
+      mnemonic = "st2";
+      form = form_2v;
+      break;
+    case NEON_ST3_post:
+      mnemonic = "st3";
+      form = form_3v;
+      break;
+    case NEON_ST4_post:
+      mnemonic = "st4";
+      form = form_4v;
+      break;
+    default:
+      break;
+  }
+
+  // Work out unallocated encodings.
+  bool allocated = (mnemonic != NULL);
+  switch (instr->Mask(NEONLoadStoreMultiStructPostIndexMask)) {
+    case NEON_LD2_post:
+    case NEON_LD3_post:
+    case NEON_LD4_post:
+    case NEON_ST2_post:
+    case NEON_ST3_post:
+    case NEON_ST4_post:
+      // LD[2-4] and ST[2-4] cannot use .1d format.
+      allocated = (instr->NEONQ() != 0) || (instr->NEONLSSize() != 3);
+      break;
+    default:
+      break;
+  }
+  if (allocated) {
+    VIXL_ASSERT(mnemonic != NULL);
+    VIXL_ASSERT(form != NULL);
+  } else {
+    mnemonic = "unallocated";
+    form = "(NEONLoadStoreMultiStructPostIndex)";
   }
 
   Format(instr, mnemonic, nfd.Substitute(form));
 }
 
 
-void Disassembler::VisitNEONLoadStoreSingleStruct(const Instruction* instr) {
-  const char *mnemonic = "unimplemented";
-  const char *form = "(NEONLoadStoreSingleStruct)";
+void Disassembler::VisitNEONLoadStoreSingleStruct(const Instruction *instr) {
+  const char *mnemonic = NULL;
+  const char *form = NULL;
 
   const char *form_1b = "{'Vt.b}['IVLSLane0], ['Xns]";
   const char *form_1h = "{'Vt.h}['IVLSLane1], ['Xns]";
@@ -1931,15 +2785,27 @@
   NEONFormatDecoder nfd(instr, NEONFormatDecoder::LoadStoreFormatMap());
 
   switch (instr->Mask(NEONLoadStoreSingleStructMask)) {
-    case NEON_LD1_b: mnemonic = "ld1"; form = form_1b; break;
-    case NEON_LD1_h: mnemonic = "ld1"; form = form_1h; break;
+    case NEON_LD1_b:
+      mnemonic = "ld1";
+      form = form_1b;
+      break;
+    case NEON_LD1_h:
+      mnemonic = "ld1";
+      form = form_1h;
+      break;
     case NEON_LD1_s:
       mnemonic = "ld1";
       VIXL_STATIC_ASSERT((NEON_LD1_s | (1 << NEONLSSize_offset)) == NEON_LD1_d);
       form = ((instr->NEONLSSize() & 1) == 0) ? form_1s : form_1d;
       break;
-    case NEON_ST1_b: mnemonic = "st1"; form = form_1b; break;
-    case NEON_ST1_h: mnemonic = "st1"; form = form_1h; break;
+    case NEON_ST1_b:
+      mnemonic = "st1";
+      form = form_1b;
+      break;
+    case NEON_ST1_h:
+      mnemonic = "st1";
+      form = form_1h;
+      break;
     case NEON_ST1_s:
       mnemonic = "st1";
       VIXL_STATIC_ASSERT((NEON_ST1_s | (1 << NEONLSSize_offset)) == NEON_ST1_d);
@@ -1964,10 +2830,11 @@
       VIXL_STATIC_ASSERT((NEON_ST2_s | (1 << NEONLSSize_offset)) == NEON_ST2_d);
       VIXL_STATIC_ASSERT((NEON_LD2_s | (1 << NEONLSSize_offset)) == NEON_LD2_d);
       mnemonic = (instr->LdStXLoad() == 1) ? "ld2" : "st2";
-      if ((instr->NEONLSSize() & 1) == 0)
+      if ((instr->NEONLSSize() & 1) == 0) {
         form = "{'Vt.s, 'Vt2.s}['IVLSLane2], ['Xns]";
-      else
+      } else {
         form = "{'Vt.d, 'Vt2.d}['IVLSLane3], ['Xns]";
+      }
       break;
     case NEON_LD2R:
       mnemonic = "ld2r";
@@ -1986,17 +2853,18 @@
     case NEON_LD3_s:
     case NEON_ST3_s:
       mnemonic = (instr->LdStXLoad() == 1) ? "ld3" : "st3";
-      if ((instr->NEONLSSize() & 1) == 0)
+      if ((instr->NEONLSSize() & 1) == 0) {
         form = "{'Vt.s, 'Vt2.s, 'Vt3.s}['IVLSLane2], ['Xns]";
-      else
+      } else {
         form = "{'Vt.d, 'Vt2.d, 'Vt3.d}['IVLSLane3], ['Xns]";
+      }
       break;
     case NEON_LD3R:
       mnemonic = "ld3r";
       form = "{'Vt.%s, 'Vt2.%s, 'Vt3.%s}, ['Xns]";
       break;
     case NEON_LD4_b:
-     case NEON_ST4_b:
+    case NEON_ST4_b:
       mnemonic = (instr->LdStXLoad() == 1) ? "ld4" : "st4";
       form = "{'Vt.b, 'Vt2.b, 'Vt3.b, 'Vt4.b}['IVLSLane0], ['Xns]";
       break;
@@ -2010,16 +2878,62 @@
       VIXL_STATIC_ASSERT((NEON_LD4_s | (1 << NEONLSSize_offset)) == NEON_LD4_d);
       VIXL_STATIC_ASSERT((NEON_ST4_s | (1 << NEONLSSize_offset)) == NEON_ST4_d);
       mnemonic = (instr->LdStXLoad() == 1) ? "ld4" : "st4";
-      if ((instr->NEONLSSize() & 1) == 0)
+      if ((instr->NEONLSSize() & 1) == 0) {
         form = "{'Vt.s, 'Vt2.s, 'Vt3.s, 'Vt4.s}['IVLSLane2], ['Xns]";
-      else
+      } else {
         form = "{'Vt.d, 'Vt2.d, 'Vt3.d, 'Vt4.d}['IVLSLane3], ['Xns]";
+      }
       break;
     case NEON_LD4R:
       mnemonic = "ld4r";
       form = "{'Vt.%1$s, 'Vt2.%1$s, 'Vt3.%1$s, 'Vt4.%1$s}, ['Xns]";
       break;
-    default: break;
+    default:
+      break;
+  }
+
+  // Work out unallocated encodings.
+  bool allocated = (mnemonic != NULL);
+  switch (instr->Mask(NEONLoadStoreSingleStructMask)) {
+    case NEON_LD1_h:
+    case NEON_LD2_h:
+    case NEON_LD3_h:
+    case NEON_LD4_h:
+    case NEON_ST1_h:
+    case NEON_ST2_h:
+    case NEON_ST3_h:
+    case NEON_ST4_h:
+      VIXL_ASSERT(allocated);
+      allocated = ((instr->NEONLSSize() & 1) == 0);
+      break;
+    case NEON_LD1_s:
+    case NEON_LD2_s:
+    case NEON_LD3_s:
+    case NEON_LD4_s:
+    case NEON_ST1_s:
+    case NEON_ST2_s:
+    case NEON_ST3_s:
+    case NEON_ST4_s:
+      VIXL_ASSERT(allocated);
+      allocated = (instr->NEONLSSize() <= 1) &&
+                  ((instr->NEONLSSize() == 0) || (instr->NEONS() == 0));
+      break;
+    case NEON_LD1R:
+    case NEON_LD2R:
+    case NEON_LD3R:
+    case NEON_LD4R:
+      VIXL_ASSERT(allocated);
+      allocated = (instr->NEONS() == 0);
+      break;
+    default:
+      break;
+  }
+  if (allocated) {
+    VIXL_ASSERT(mnemonic != NULL);
+    VIXL_ASSERT(form != NULL);
+  } else {
+    mnemonic = "unallocated";
+    form = "(NEONLoadStoreSingleStruct)";
   }
 
   Format(instr, mnemonic, nfd.Substitute(form));
@@ -2027,9 +2941,9 @@
 
 
 void Disassembler::VisitNEONLoadStoreSingleStructPostIndex(
-    const Instruction* instr) {
-  const char *mnemonic = "unimplemented";
-  const char *form = "(NEONLoadStoreSingleStructPostIndex)";
+    const Instruction *instr) {
+  const char *mnemonic = NULL;
+  const char *form = NULL;
 
   const char *form_1b = "{'Vt.b}['IVLSLane0], ['Xns], 'Xmb1";
   const char *form_1h = "{'Vt.h}['IVLSLane1], ['Xns], 'Xmb2";
@@ -2038,15 +2952,27 @@
   NEONFormatDecoder nfd(instr, NEONFormatDecoder::LoadStoreFormatMap());
 
   switch (instr->Mask(NEONLoadStoreSingleStructPostIndexMask)) {
-    case NEON_LD1_b_post: mnemonic = "ld1"; form = form_1b; break;
-    case NEON_LD1_h_post: mnemonic = "ld1"; form = form_1h; break;
+    case NEON_LD1_b_post:
+      mnemonic = "ld1";
+      form = form_1b;
+      break;
+    case NEON_LD1_h_post:
+      mnemonic = "ld1";
+      form = form_1h;
+      break;
     case NEON_LD1_s_post:
       mnemonic = "ld1";
       VIXL_STATIC_ASSERT((NEON_LD1_s | (1 << NEONLSSize_offset)) == NEON_LD1_d);
       form = ((instr->NEONLSSize() & 1) == 0) ? form_1s : form_1d;
       break;
-    case NEON_ST1_b_post: mnemonic = "st1"; form = form_1b; break;
-    case NEON_ST1_h_post: mnemonic = "st1"; form = form_1h; break;
+    case NEON_ST1_b_post:
+      mnemonic = "st1";
+      form = form_1b;
+      break;
+    case NEON_ST1_h_post:
+      mnemonic = "st1";
+      form = form_1h;
+      break;
     case NEON_ST1_s_post:
       mnemonic = "st1";
       VIXL_STATIC_ASSERT((NEON_ST1_s | (1 << NEONLSSize_offset)) == NEON_ST1_d);
@@ -2094,7 +3020,7 @@
       if ((instr->NEONLSSize() & 1) == 0)
         form = "{'Vt.s, 'Vt2.s, 'Vt3.s}['IVLSLane2], ['Xns], 'Xmb12";
       else
-        form = "{'Vt.d, 'Vt2.d, 'Vt3.d}['IVLSLane3], ['Xns], 'Xmr3";
+        form = "{'Vt.d, 'Vt2.d, 'Vt3.d}['IVLSLane3], ['Xns], 'Xmb24";
       break;
     case NEON_LD3R_post:
       mnemonic = "ld3r";
@@ -2122,18 +3048,63 @@
       mnemonic = "ld4r";
       form = "{'Vt.%1$s, 'Vt2.%1$s, 'Vt3.%1$s, 'Vt4.%1$s}, ['Xns], 'Xmz4";
       break;
-    default: break;
+    default:
+      break;
+  }
+
+  // Work out unallocated encodings.
+  bool allocated = (mnemonic != NULL);
+  switch (instr->Mask(NEONLoadStoreSingleStructPostIndexMask)) {
+    case NEON_LD1_h_post:
+    case NEON_LD2_h_post:
+    case NEON_LD3_h_post:
+    case NEON_LD4_h_post:
+    case NEON_ST1_h_post:
+    case NEON_ST2_h_post:
+    case NEON_ST3_h_post:
+    case NEON_ST4_h_post:
+      VIXL_ASSERT(allocated);
+      allocated = ((instr->NEONLSSize() & 1) == 0);
+      break;
+    case NEON_LD1_s_post:
+    case NEON_LD2_s_post:
+    case NEON_LD3_s_post:
+    case NEON_LD4_s_post:
+    case NEON_ST1_s_post:
+    case NEON_ST2_s_post:
+    case NEON_ST3_s_post:
+    case NEON_ST4_s_post:
+      VIXL_ASSERT(allocated);
+      allocated = (instr->NEONLSSize() <= 1) &&
+                  ((instr->NEONLSSize() == 0) || (instr->NEONS() == 0));
+      break;
+    case NEON_LD1R_post:
+    case NEON_LD2R_post:
+    case NEON_LD3R_post:
+    case NEON_LD4R_post:
+      VIXL_ASSERT(allocated);
+      allocated = (instr->NEONS() == 0);
+      break;
+    default:
+      break;
+  }
+  if (allocated) {
+    VIXL_ASSERT(mnemonic != NULL);
+    VIXL_ASSERT(form != NULL);
+  } else {
+    mnemonic = "unallocated";
+    form = "(NEONLoadStoreSingleStructPostIndex)";
   }
 
   Format(instr, mnemonic, nfd.Substitute(form));
 }
 
 
-void Disassembler::VisitNEONModifiedImmediate(const Instruction* instr) {
+void Disassembler::VisitNEONModifiedImmediate(const Instruction *instr) {
   const char *mnemonic = "unimplemented";
   const char *form = "'Vt.%s, 'IVMIImm8, lsl 'IVMIShiftAmt1";
 
-  int cmode   = instr->NEONCmode();
+  int cmode = instr->NEONCmode();
   int cmode_3 = (cmode >> 3) & 1;
   int cmode_2 = (cmode >> 2) & 1;
   int cmode_1 = (cmode >> 1) & 1;
@@ -2141,9 +3112,9 @@
   int q = instr->NEONQ();
   int op = instr->NEONModImmOp();
 
-  static const NEONFormatMap map_b = { {30}, {NF_8B, NF_16B} };
-  static const NEONFormatMap map_h = { {30}, {NF_4H, NF_8H} };
-  static const NEONFormatMap map_s = { {30}, {NF_2S, NF_4S} };
+  static const NEONFormatMap map_b = {{30}, {NF_8B, NF_16B}};
+  static const NEONFormatMap map_h = {{30}, {NF_4H, NF_8H}};
+  static const NEONFormatMap map_s = {{30}, {NF_2S, NF_4S}};
   NEONFormatDecoder nfd(instr, &map_b);
 
   if (cmode_3 == 0) {
@@ -2166,7 +3137,7 @@
         mnemonic = (op == 1) ? "mvni" : "movi";
         form = "'Vt.%s, 'IVMIImm8, msl 'IVMIShiftAmt2";
         nfd.SetFormatMap(0, &map_s);
-      } else {   // cmode<1> == '1'.
+      } else {  // cmode<1> == '1'.
         if (cmode_0 == 0) {
           mnemonic = "movi";
           if (op == 0) {
@@ -2177,11 +3148,14 @@
         } else {  // cmode<0> == '1'
           mnemonic = "fmov";
           if (op == 0) {
-            form  = "'Vt.%s, 'IVMIImmFPSingle";
+            form = "'Vt.%s, 'IVMIImmFPSingle";
             nfd.SetFormatMap(0, &map_s);
           } else {
             if (q == 1) {
               form = "'Vt.2d, 'IVMIImmFPDouble";
+            } else {
+              mnemonic = "unallocated";
+              form = "(NEONModifiedImmediate)";
             }
           }
         }
@@ -2192,10 +3166,10 @@
 }
 
 
-void Disassembler::VisitNEONScalar2RegMisc(const Instruction* instr) {
+void Disassembler::VisitNEONScalar2RegMisc(const Instruction *instr) {
   const char *mnemonic = "unimplemented";
-  const char *form     = "%sd, %sn";
-  const char *form_0   = "%sd, %sn, #0";
+  const char *form = "%sd, %sn";
+  const char *form_0 = "%sd, %sn, #0";
   const char *form_fp0 = "%sd, %sn, #0.0";
 
   NEONFormatDecoder nfd(instr, NEONFormatDecoder::ScalarFormatMap());
@@ -2204,44 +3178,117 @@
     // These instructions all use a two bit size field, except NOT and RBIT,
     // which use the field to encode the operation.
     switch (instr->Mask(NEONScalar2RegMiscMask)) {
-      case NEON_CMGT_zero_scalar: mnemonic = "cmgt"; form = form_0; break;
-      case NEON_CMGE_zero_scalar: mnemonic = "cmge"; form = form_0; break;
-      case NEON_CMLE_zero_scalar: mnemonic = "cmle"; form = form_0; break;
-      case NEON_CMLT_zero_scalar: mnemonic = "cmlt"; form = form_0; break;
-      case NEON_CMEQ_zero_scalar: mnemonic = "cmeq"; form = form_0; break;
-      case NEON_NEG_scalar:       mnemonic = "neg";   break;
-      case NEON_SQNEG_scalar:     mnemonic = "sqneg"; break;
-      case NEON_ABS_scalar:       mnemonic = "abs";   break;
-      case NEON_SQABS_scalar:     mnemonic = "sqabs"; break;
-      case NEON_SUQADD_scalar:    mnemonic = "suqadd"; break;
-      case NEON_USQADD_scalar:    mnemonic = "usqadd"; break;
-      default: form = "(NEONScalar2RegMisc)";
+      case NEON_CMGT_zero_scalar:
+        mnemonic = "cmgt";
+        form = form_0;
+        break;
+      case NEON_CMGE_zero_scalar:
+        mnemonic = "cmge";
+        form = form_0;
+        break;
+      case NEON_CMLE_zero_scalar:
+        mnemonic = "cmle";
+        form = form_0;
+        break;
+      case NEON_CMLT_zero_scalar:
+        mnemonic = "cmlt";
+        form = form_0;
+        break;
+      case NEON_CMEQ_zero_scalar:
+        mnemonic = "cmeq";
+        form = form_0;
+        break;
+      case NEON_NEG_scalar:
+        mnemonic = "neg";
+        break;
+      case NEON_SQNEG_scalar:
+        mnemonic = "sqneg";
+        break;
+      case NEON_ABS_scalar:
+        mnemonic = "abs";
+        break;
+      case NEON_SQABS_scalar:
+        mnemonic = "sqabs";
+        break;
+      case NEON_SUQADD_scalar:
+        mnemonic = "suqadd";
+        break;
+      case NEON_USQADD_scalar:
+        mnemonic = "usqadd";
+        break;
+      default:
+        form = "(NEONScalar2RegMisc)";
     }
   } else {
     // These instructions all use a one bit size field, except SQXTUN, SQXTN
     // and UQXTN, which use a two bit size field.
     nfd.SetFormatMaps(nfd.FPScalarFormatMap());
     switch (instr->Mask(NEONScalar2RegMiscFPMask)) {
-      case NEON_FRSQRTE_scalar:    mnemonic = "frsqrte"; break;
-      case NEON_FRECPE_scalar:     mnemonic = "frecpe";  break;
-      case NEON_SCVTF_scalar:      mnemonic = "scvtf"; break;
-      case NEON_UCVTF_scalar:      mnemonic = "ucvtf"; break;
-      case NEON_FCMGT_zero_scalar: mnemonic = "fcmgt"; form = form_fp0; break;
-      case NEON_FCMGE_zero_scalar: mnemonic = "fcmge"; form = form_fp0; break;
-      case NEON_FCMLE_zero_scalar: mnemonic = "fcmle"; form = form_fp0; break;
-      case NEON_FCMLT_zero_scalar: mnemonic = "fcmlt"; form = form_fp0; break;
-      case NEON_FCMEQ_zero_scalar: mnemonic = "fcmeq"; form = form_fp0; break;
-      case NEON_FRECPX_scalar:     mnemonic = "frecpx"; break;
-      case NEON_FCVTNS_scalar:     mnemonic = "fcvtns"; break;
-      case NEON_FCVTNU_scalar:     mnemonic = "fcvtnu"; break;
-      case NEON_FCVTPS_scalar:     mnemonic = "fcvtps"; break;
-      case NEON_FCVTPU_scalar:     mnemonic = "fcvtpu"; break;
-      case NEON_FCVTMS_scalar:     mnemonic = "fcvtms"; break;
-      case NEON_FCVTMU_scalar:     mnemonic = "fcvtmu"; break;
-      case NEON_FCVTZS_scalar:     mnemonic = "fcvtzs"; break;
-      case NEON_FCVTZU_scalar:     mnemonic = "fcvtzu"; break;
-      case NEON_FCVTAS_scalar:     mnemonic = "fcvtas"; break;
-      case NEON_FCVTAU_scalar:     mnemonic = "fcvtau"; break;
+      case NEON_FRSQRTE_scalar:
+        mnemonic = "frsqrte";
+        break;
+      case NEON_FRECPE_scalar:
+        mnemonic = "frecpe";
+        break;
+      case NEON_SCVTF_scalar:
+        mnemonic = "scvtf";
+        break;
+      case NEON_UCVTF_scalar:
+        mnemonic = "ucvtf";
+        break;
+      case NEON_FCMGT_zero_scalar:
+        mnemonic = "fcmgt";
+        form = form_fp0;
+        break;
+      case NEON_FCMGE_zero_scalar:
+        mnemonic = "fcmge";
+        form = form_fp0;
+        break;
+      case NEON_FCMLE_zero_scalar:
+        mnemonic = "fcmle";
+        form = form_fp0;
+        break;
+      case NEON_FCMLT_zero_scalar:
+        mnemonic = "fcmlt";
+        form = form_fp0;
+        break;
+      case NEON_FCMEQ_zero_scalar:
+        mnemonic = "fcmeq";
+        form = form_fp0;
+        break;
+      case NEON_FRECPX_scalar:
+        mnemonic = "frecpx";
+        break;
+      case NEON_FCVTNS_scalar:
+        mnemonic = "fcvtns";
+        break;
+      case NEON_FCVTNU_scalar:
+        mnemonic = "fcvtnu";
+        break;
+      case NEON_FCVTPS_scalar:
+        mnemonic = "fcvtps";
+        break;
+      case NEON_FCVTPU_scalar:
+        mnemonic = "fcvtpu";
+        break;
+      case NEON_FCVTMS_scalar:
+        mnemonic = "fcvtms";
+        break;
+      case NEON_FCVTMU_scalar:
+        mnemonic = "fcvtmu";
+        break;
+      case NEON_FCVTZS_scalar:
+        mnemonic = "fcvtzs";
+        break;
+      case NEON_FCVTZU_scalar:
+        mnemonic = "fcvtzu";
+        break;
+      case NEON_FCVTAS_scalar:
+        mnemonic = "fcvtas";
+        break;
+      case NEON_FCVTAU_scalar:
+        mnemonic = "fcvtau";
+        break;
       case NEON_FCVTXN_scalar:
         nfd.SetFormatMap(0, nfd.LongScalarFormatMap());
         mnemonic = "fcvtxn";
@@ -2250,10 +3297,17 @@
         nfd.SetFormatMap(0, nfd.ScalarFormatMap());
         nfd.SetFormatMap(1, nfd.LongScalarFormatMap());
         switch (instr->Mask(NEONScalar2RegMiscMask)) {
-          case NEON_SQXTN_scalar:  mnemonic = "sqxtn"; break;
-          case NEON_UQXTN_scalar:  mnemonic = "uqxtn"; break;
-          case NEON_SQXTUN_scalar: mnemonic = "sqxtun"; break;
-          default: form = "(NEONScalar2RegMisc)";
+          case NEON_SQXTN_scalar:
+            mnemonic = "sqxtn";
+            break;
+          case NEON_UQXTN_scalar:
+            mnemonic = "uqxtn";
+            break;
+          case NEON_SQXTUN_scalar:
+            mnemonic = "sqxtun";
+            break;
+          default:
+            form = "(NEONScalar2RegMisc)";
         }
     }
   }
@@ -2261,23 +3315,31 @@
 }
 
 
-void Disassembler::VisitNEONScalar3Diff(const Instruction* instr) {
+void Disassembler::VisitNEONScalar3Diff(const Instruction *instr) {
   const char *mnemonic = "unimplemented";
   const char *form = "%sd, %sn, %sm";
-  NEONFormatDecoder nfd(instr, NEONFormatDecoder::LongScalarFormatMap(),
-                               NEONFormatDecoder::ScalarFormatMap());
+  NEONFormatDecoder nfd(instr,
+                        NEONFormatDecoder::LongScalarFormatMap(),
+                        NEONFormatDecoder::ScalarFormatMap());
 
   switch (instr->Mask(NEONScalar3DiffMask)) {
-    case NEON_SQDMLAL_scalar  : mnemonic = "sqdmlal"; break;
-    case NEON_SQDMLSL_scalar  : mnemonic = "sqdmlsl"; break;
-    case NEON_SQDMULL_scalar  : mnemonic = "sqdmull"; break;
-    default: form = "(NEONScalar3Diff)";
+    case NEON_SQDMLAL_scalar:
+      mnemonic = "sqdmlal";
+      break;
+    case NEON_SQDMLSL_scalar:
+      mnemonic = "sqdmlsl";
+      break;
+    case NEON_SQDMULL_scalar:
+      mnemonic = "sqdmull";
+      break;
+    default:
+      form = "(NEONScalar3Diff)";
   }
   Format(instr, mnemonic, nfd.SubstitutePlaceholders(form));
 }
 
 
-void Disassembler::VisitNEONScalar3Same(const Instruction* instr) {
+void Disassembler::VisitNEONScalar3Same(const Instruction *instr) {
   const char *mnemonic = "unimplemented";
   const char *form = "%sd, %sn, %sm";
   NEONFormatDecoder nfd(instr, NEONFormatDecoder::ScalarFormatMap());
@@ -2285,49 +3347,113 @@
   if (instr->Mask(NEONScalar3SameFPFMask) == NEONScalar3SameFPFixed) {
     nfd.SetFormatMaps(nfd.FPScalarFormatMap());
     switch (instr->Mask(NEONScalar3SameFPMask)) {
-      case NEON_FACGE_scalar:   mnemonic = "facge"; break;
-      case NEON_FACGT_scalar:   mnemonic = "facgt"; break;
-      case NEON_FCMEQ_scalar:   mnemonic = "fcmeq"; break;
-      case NEON_FCMGE_scalar:   mnemonic = "fcmge"; break;
-      case NEON_FCMGT_scalar:   mnemonic = "fcmgt"; break;
-      case NEON_FMULX_scalar:   mnemonic = "fmulx"; break;
-      case NEON_FRECPS_scalar:  mnemonic = "frecps"; break;
-      case NEON_FRSQRTS_scalar: mnemonic = "frsqrts"; break;
-      case NEON_FABD_scalar:    mnemonic = "fabd"; break;
-      default: form = "(NEONScalar3Same)";
+      case NEON_FACGE_scalar:
+        mnemonic = "facge";
+        break;
+      case NEON_FACGT_scalar:
+        mnemonic = "facgt";
+        break;
+      case NEON_FCMEQ_scalar:
+        mnemonic = "fcmeq";
+        break;
+      case NEON_FCMGE_scalar:
+        mnemonic = "fcmge";
+        break;
+      case NEON_FCMGT_scalar:
+        mnemonic = "fcmgt";
+        break;
+      case NEON_FMULX_scalar:
+        mnemonic = "fmulx";
+        break;
+      case NEON_FRECPS_scalar:
+        mnemonic = "frecps";
+        break;
+      case NEON_FRSQRTS_scalar:
+        mnemonic = "frsqrts";
+        break;
+      case NEON_FABD_scalar:
+        mnemonic = "fabd";
+        break;
+      default:
+        form = "(NEONScalar3Same)";
     }
   } else {
     switch (instr->Mask(NEONScalar3SameMask)) {
-      case NEON_ADD_scalar:    mnemonic = "add";    break;
-      case NEON_SUB_scalar:    mnemonic = "sub";    break;
-      case NEON_CMEQ_scalar:   mnemonic = "cmeq";   break;
-      case NEON_CMGE_scalar:   mnemonic = "cmge";   break;
-      case NEON_CMGT_scalar:   mnemonic = "cmgt";   break;
-      case NEON_CMHI_scalar:   mnemonic = "cmhi";   break;
-      case NEON_CMHS_scalar:   mnemonic = "cmhs";   break;
-      case NEON_CMTST_scalar:  mnemonic = "cmtst";  break;
-      case NEON_UQADD_scalar:  mnemonic = "uqadd";  break;
-      case NEON_SQADD_scalar:  mnemonic = "sqadd";  break;
-      case NEON_UQSUB_scalar:  mnemonic = "uqsub";  break;
-      case NEON_SQSUB_scalar:  mnemonic = "sqsub";  break;
-      case NEON_USHL_scalar:   mnemonic = "ushl";   break;
-      case NEON_SSHL_scalar:   mnemonic = "sshl";   break;
-      case NEON_UQSHL_scalar:  mnemonic = "uqshl";  break;
-      case NEON_SQSHL_scalar:  mnemonic = "sqshl";  break;
-      case NEON_URSHL_scalar:  mnemonic = "urshl";  break;
-      case NEON_SRSHL_scalar:  mnemonic = "srshl";  break;
-      case NEON_UQRSHL_scalar: mnemonic = "uqrshl"; break;
-      case NEON_SQRSHL_scalar: mnemonic = "sqrshl"; break;
-      case NEON_SQDMULH_scalar:  mnemonic = "sqdmulh";  break;
-      case NEON_SQRDMULH_scalar: mnemonic = "sqrdmulh"; break;
-      default: form = "(NEONScalar3Same)";
+      case NEON_ADD_scalar:
+        mnemonic = "add";
+        break;
+      case NEON_SUB_scalar:
+        mnemonic = "sub";
+        break;
+      case NEON_CMEQ_scalar:
+        mnemonic = "cmeq";
+        break;
+      case NEON_CMGE_scalar:
+        mnemonic = "cmge";
+        break;
+      case NEON_CMGT_scalar:
+        mnemonic = "cmgt";
+        break;
+      case NEON_CMHI_scalar:
+        mnemonic = "cmhi";
+        break;
+      case NEON_CMHS_scalar:
+        mnemonic = "cmhs";
+        break;
+      case NEON_CMTST_scalar:
+        mnemonic = "cmtst";
+        break;
+      case NEON_UQADD_scalar:
+        mnemonic = "uqadd";
+        break;
+      case NEON_SQADD_scalar:
+        mnemonic = "sqadd";
+        break;
+      case NEON_UQSUB_scalar:
+        mnemonic = "uqsub";
+        break;
+      case NEON_SQSUB_scalar:
+        mnemonic = "sqsub";
+        break;
+      case NEON_USHL_scalar:
+        mnemonic = "ushl";
+        break;
+      case NEON_SSHL_scalar:
+        mnemonic = "sshl";
+        break;
+      case NEON_UQSHL_scalar:
+        mnemonic = "uqshl";
+        break;
+      case NEON_SQSHL_scalar:
+        mnemonic = "sqshl";
+        break;
+      case NEON_URSHL_scalar:
+        mnemonic = "urshl";
+        break;
+      case NEON_SRSHL_scalar:
+        mnemonic = "srshl";
+        break;
+      case NEON_UQRSHL_scalar:
+        mnemonic = "uqrshl";
+        break;
+      case NEON_SQRSHL_scalar:
+        mnemonic = "sqrshl";
+        break;
+      case NEON_SQDMULH_scalar:
+        mnemonic = "sqdmulh";
+        break;
+      case NEON_SQRDMULH_scalar:
+        mnemonic = "sqrdmulh";
+        break;
+      default:
+        form = "(NEONScalar3Same)";
     }
   }
   Format(instr, mnemonic, nfd.SubstitutePlaceholders(form));
 }
 
 
-void Disassembler::VisitNEONScalarByIndexedElement(const Instruction* instr) {
+void Disassembler::VisitNEONScalarByIndexedElement(const Instruction *instr) {
   const char *mnemonic = "unimplemented";
   const char *form = "%sd, %sn, 'Ve.%s['IVByElemIndex]";
   NEONFormatDecoder nfd(instr, NEONFormatDecoder::ScalarFormatMap());
@@ -2355,11 +3481,20 @@
     default:
       nfd.SetFormatMap(0, nfd.FPScalarFormatMap());
       switch (instr->Mask(NEONScalarByIndexedElementFPMask)) {
-        case NEON_FMUL_byelement_scalar: mnemonic = "fmul"; break;
-        case NEON_FMLA_byelement_scalar: mnemonic = "fmla"; break;
-        case NEON_FMLS_byelement_scalar: mnemonic = "fmls"; break;
-        case NEON_FMULX_byelement_scalar: mnemonic = "fmulx"; break;
-        default: form = "(NEONScalarByIndexedElement)";
+        case NEON_FMUL_byelement_scalar:
+          mnemonic = "fmul";
+          break;
+        case NEON_FMLA_byelement_scalar:
+          mnemonic = "fmla";
+          break;
+        case NEON_FMLS_byelement_scalar:
+          mnemonic = "fmls";
+          break;
+        case NEON_FMULX_byelement_scalar:
+          mnemonic = "fmulx";
+          break;
+        default:
+          form = "(NEONScalarByIndexedElement)";
       }
   }
 
@@ -2367,12 +3502,13 @@
     nfd.SetFormatMap(0, nfd.LongScalarFormatMap());
   }
 
-  Format(instr, mnemonic, nfd.Substitute(
-    form, nfd.kPlaceholder, nfd.kPlaceholder, nfd.kFormat));
+  Format(instr,
+         mnemonic,
+         nfd.Substitute(form, nfd.kPlaceholder, nfd.kPlaceholder, nfd.kFormat));
 }
 
 
-void Disassembler::VisitNEONScalarCopy(const Instruction* instr) {
+void Disassembler::VisitNEONScalarCopy(const Instruction *instr) {
   const char *mnemonic = "unimplemented";
   const char *form = "(NEONScalarCopy)";
 
@@ -2387,62 +3523,129 @@
 }
 
 
-void Disassembler::VisitNEONScalarPairwise(const Instruction* instr) {
+void Disassembler::VisitNEONScalarPairwise(const Instruction *instr) {
   const char *mnemonic = "unimplemented";
   const char *form = "%sd, 'Vn.%s";
-  NEONFormatMap map = { {22}, {NF_2S, NF_2D} };
+  NEONFormatMap map = {{22}, {NF_2S, NF_2D}};
   NEONFormatDecoder nfd(instr, NEONFormatDecoder::FPScalarFormatMap(), &map);
 
   switch (instr->Mask(NEONScalarPairwiseMask)) {
-    case NEON_ADDP_scalar:    mnemonic = "addp"; break;
-    case NEON_FADDP_scalar:   mnemonic = "faddp"; break;
-    case NEON_FMAXP_scalar:   mnemonic = "fmaxp"; break;
-    case NEON_FMAXNMP_scalar: mnemonic = "fmaxnmp"; break;
-    case NEON_FMINP_scalar:   mnemonic = "fminp"; break;
-    case NEON_FMINNMP_scalar: mnemonic = "fminnmp"; break;
-    default: form = "(NEONScalarPairwise)";
+    case NEON_ADDP_scalar:
+      mnemonic = "addp";
+      break;
+    case NEON_FADDP_scalar:
+      mnemonic = "faddp";
+      break;
+    case NEON_FMAXP_scalar:
+      mnemonic = "fmaxp";
+      break;
+    case NEON_FMAXNMP_scalar:
+      mnemonic = "fmaxnmp";
+      break;
+    case NEON_FMINP_scalar:
+      mnemonic = "fminp";
+      break;
+    case NEON_FMINNMP_scalar:
+      mnemonic = "fminnmp";
+      break;
+    default:
+      form = "(NEONScalarPairwise)";
   }
-  Format(instr, mnemonic, nfd.Substitute(form,
-      NEONFormatDecoder::kPlaceholder, NEONFormatDecoder::kFormat));
+  Format(instr,
+         mnemonic,
+         nfd.Substitute(form,
+                        NEONFormatDecoder::kPlaceholder,
+                        NEONFormatDecoder::kFormat));
 }
 
 
-void Disassembler::VisitNEONScalarShiftImmediate(const Instruction* instr) {
+void Disassembler::VisitNEONScalarShiftImmediate(const Instruction *instr) {
   const char *mnemonic = "unimplemented";
-  const char *form   = "%sd, %sn, 'Is1";
+  const char *form = "%sd, %sn, 'Is1";
   const char *form_2 = "%sd, %sn, 'Is2";
 
-  static const NEONFormatMap map_shift = {
-    {22, 21, 20, 19},
-    {NF_UNDEF, NF_B, NF_H, NF_H, NF_S, NF_S, NF_S, NF_S,
-     NF_D,     NF_D, NF_D, NF_D, NF_D, NF_D, NF_D, NF_D}
-  };
-  static const NEONFormatMap map_shift_narrow = {
-    {21, 20, 19},
-    {NF_UNDEF, NF_H, NF_S, NF_S, NF_D, NF_D, NF_D, NF_D}
-  };
+  static const NEONFormatMap map_shift = {{22, 21, 20, 19},
+                                          {NF_UNDEF,
+                                           NF_B,
+                                           NF_H,
+                                           NF_H,
+                                           NF_S,
+                                           NF_S,
+                                           NF_S,
+                                           NF_S,
+                                           NF_D,
+                                           NF_D,
+                                           NF_D,
+                                           NF_D,
+                                           NF_D,
+                                           NF_D,
+                                           NF_D,
+                                           NF_D}};
+  static const NEONFormatMap map_shift_narrow =
+      {{21, 20, 19}, {NF_UNDEF, NF_H, NF_S, NF_S, NF_D, NF_D, NF_D, NF_D}};
   NEONFormatDecoder nfd(instr, &map_shift);
 
   if (instr->ImmNEONImmh()) {  // immh has to be non-zero.
     switch (instr->Mask(NEONScalarShiftImmediateMask)) {
-      case NEON_FCVTZU_imm_scalar: mnemonic = "fcvtzu";    break;
-      case NEON_FCVTZS_imm_scalar: mnemonic = "fcvtzs";   break;
-      case NEON_SCVTF_imm_scalar: mnemonic = "scvtf";    break;
-      case NEON_UCVTF_imm_scalar: mnemonic = "ucvtf";   break;
-      case NEON_SRI_scalar:       mnemonic = "sri";    break;
-      case NEON_SSHR_scalar:      mnemonic = "sshr";   break;
-      case NEON_USHR_scalar:      mnemonic = "ushr";   break;
-      case NEON_SRSHR_scalar:     mnemonic = "srshr";  break;
-      case NEON_URSHR_scalar:     mnemonic = "urshr";  break;
-      case NEON_SSRA_scalar:      mnemonic = "ssra";   break;
-      case NEON_USRA_scalar:      mnemonic = "usra";   break;
-      case NEON_SRSRA_scalar:     mnemonic = "srsra";  break;
-      case NEON_URSRA_scalar:     mnemonic = "ursra";  break;
-      case NEON_SHL_scalar:       mnemonic = "shl";    form = form_2; break;
-      case NEON_SLI_scalar:       mnemonic = "sli";    form = form_2; break;
-      case NEON_SQSHLU_scalar:    mnemonic = "sqshlu"; form = form_2; break;
-      case NEON_SQSHL_imm_scalar: mnemonic = "sqshl";  form = form_2; break;
-      case NEON_UQSHL_imm_scalar: mnemonic = "uqshl";  form = form_2; break;
+      case NEON_FCVTZU_imm_scalar:
+        mnemonic = "fcvtzu";
+        break;
+      case NEON_FCVTZS_imm_scalar:
+        mnemonic = "fcvtzs";
+        break;
+      case NEON_SCVTF_imm_scalar:
+        mnemonic = "scvtf";
+        break;
+      case NEON_UCVTF_imm_scalar:
+        mnemonic = "ucvtf";
+        break;
+      case NEON_SRI_scalar:
+        mnemonic = "sri";
+        break;
+      case NEON_SSHR_scalar:
+        mnemonic = "sshr";
+        break;
+      case NEON_USHR_scalar:
+        mnemonic = "ushr";
+        break;
+      case NEON_SRSHR_scalar:
+        mnemonic = "srshr";
+        break;
+      case NEON_URSHR_scalar:
+        mnemonic = "urshr";
+        break;
+      case NEON_SSRA_scalar:
+        mnemonic = "ssra";
+        break;
+      case NEON_USRA_scalar:
+        mnemonic = "usra";
+        break;
+      case NEON_SRSRA_scalar:
+        mnemonic = "srsra";
+        break;
+      case NEON_URSRA_scalar:
+        mnemonic = "ursra";
+        break;
+      case NEON_SHL_scalar:
+        mnemonic = "shl";
+        form = form_2;
+        break;
+      case NEON_SLI_scalar:
+        mnemonic = "sli";
+        form = form_2;
+        break;
+      case NEON_SQSHLU_scalar:
+        mnemonic = "sqshlu";
+        form = form_2;
+        break;
+      case NEON_SQSHL_imm_scalar:
+        mnemonic = "sqshl";
+        form = form_2;
+        break;
+      case NEON_UQSHL_imm_scalar:
+        mnemonic = "uqshl";
+        form = form_2;
+        break;
       case NEON_UQSHRN_scalar:
         mnemonic = "uqshrn";
         nfd.SetFormatMap(1, &map_shift_narrow);
@@ -2477,50 +3680,116 @@
 }
 
 
-void Disassembler::VisitNEONShiftImmediate(const Instruction* instr) {
+void Disassembler::VisitNEONShiftImmediate(const Instruction *instr) {
   const char *mnemonic = "unimplemented";
-  const char *form         = "'Vd.%s, 'Vn.%s, 'Is1";
+  const char *form = "'Vd.%s, 'Vn.%s, 'Is1";
   const char *form_shift_2 = "'Vd.%s, 'Vn.%s, 'Is2";
-  const char *form_xtl     = "'Vd.%s, 'Vn.%s";
+  const char *form_xtl = "'Vd.%s, 'Vn.%s";
 
   // 0001->8H, 001x->4S, 01xx->2D, all others undefined.
-  static const NEONFormatMap map_shift_ta = {
-    {22, 21, 20, 19},
-    {NF_UNDEF, NF_8H, NF_4S, NF_4S, NF_2D, NF_2D, NF_2D, NF_2D}
-  };
+  static const NEONFormatMap map_shift_ta =
+      {{22, 21, 20, 19},
+       {NF_UNDEF, NF_8H, NF_4S, NF_4S, NF_2D, NF_2D, NF_2D, NF_2D}};
 
   // 00010->8B, 00011->16B, 001x0->4H, 001x1->8H,
   // 01xx0->2S, 01xx1->4S, 1xxx1->2D, all others undefined.
-  static const NEONFormatMap map_shift_tb = {
-    {22, 21, 20, 19, 30},
-    {NF_UNDEF, NF_UNDEF, NF_8B,    NF_16B, NF_4H,    NF_8H, NF_4H,    NF_8H,
-     NF_2S,    NF_4S,    NF_2S,    NF_4S,  NF_2S,    NF_4S, NF_2S,    NF_4S,
-     NF_UNDEF, NF_2D,    NF_UNDEF, NF_2D,  NF_UNDEF, NF_2D, NF_UNDEF, NF_2D,
-     NF_UNDEF, NF_2D,    NF_UNDEF, NF_2D,  NF_UNDEF, NF_2D, NF_UNDEF, NF_2D}
-  };
+  static const NEONFormatMap map_shift_tb = {{22, 21, 20, 19, 30},
+                                             {NF_UNDEF,
+                                              NF_UNDEF,
+                                              NF_8B,
+                                              NF_16B,
+                                              NF_4H,
+                                              NF_8H,
+                                              NF_4H,
+                                              NF_8H,
+                                              NF_2S,
+                                              NF_4S,
+                                              NF_2S,
+                                              NF_4S,
+                                              NF_2S,
+                                              NF_4S,
+                                              NF_2S,
+                                              NF_4S,
+                                              NF_UNDEF,
+                                              NF_2D,
+                                              NF_UNDEF,
+                                              NF_2D,
+                                              NF_UNDEF,
+                                              NF_2D,
+                                              NF_UNDEF,
+                                              NF_2D,
+                                              NF_UNDEF,
+                                              NF_2D,
+                                              NF_UNDEF,
+                                              NF_2D,
+                                              NF_UNDEF,
+                                              NF_2D,
+                                              NF_UNDEF,
+                                              NF_2D}};
 
   NEONFormatDecoder nfd(instr, &map_shift_tb);
 
   if (instr->ImmNEONImmh()) {  // immh has to be non-zero.
     switch (instr->Mask(NEONShiftImmediateMask)) {
-      case NEON_SQSHLU:     mnemonic = "sqshlu"; form = form_shift_2; break;
-      case NEON_SQSHL_imm:  mnemonic = "sqshl";  form = form_shift_2; break;
-      case NEON_UQSHL_imm:  mnemonic = "uqshl";  form = form_shift_2; break;
-      case NEON_SHL:        mnemonic = "shl";    form = form_shift_2; break;
-      case NEON_SLI:        mnemonic = "sli";    form = form_shift_2; break;
-      case NEON_SCVTF_imm:  mnemonic = "scvtf";  break;
-      case NEON_UCVTF_imm:  mnemonic = "ucvtf";  break;
-      case NEON_FCVTZU_imm: mnemonic = "fcvtzu"; break;
-      case NEON_FCVTZS_imm: mnemonic = "fcvtzs"; break;
-      case NEON_SRI:        mnemonic = "sri";    break;
-      case NEON_SSHR:       mnemonic = "sshr";   break;
-      case NEON_USHR:       mnemonic = "ushr";   break;
-      case NEON_SRSHR:      mnemonic = "srshr";  break;
-      case NEON_URSHR:      mnemonic = "urshr";  break;
-      case NEON_SSRA:       mnemonic = "ssra";   break;
-      case NEON_USRA:       mnemonic = "usra";   break;
-      case NEON_SRSRA:      mnemonic = "srsra";  break;
-      case NEON_URSRA:      mnemonic = "ursra";  break;
+      case NEON_SQSHLU:
+        mnemonic = "sqshlu";
+        form = form_shift_2;
+        break;
+      case NEON_SQSHL_imm:
+        mnemonic = "sqshl";
+        form = form_shift_2;
+        break;
+      case NEON_UQSHL_imm:
+        mnemonic = "uqshl";
+        form = form_shift_2;
+        break;
+      case NEON_SHL:
+        mnemonic = "shl";
+        form = form_shift_2;
+        break;
+      case NEON_SLI:
+        mnemonic = "sli";
+        form = form_shift_2;
+        break;
+      case NEON_SCVTF_imm:
+        mnemonic = "scvtf";
+        break;
+      case NEON_UCVTF_imm:
+        mnemonic = "ucvtf";
+        break;
+      case NEON_FCVTZU_imm:
+        mnemonic = "fcvtzu";
+        break;
+      case NEON_FCVTZS_imm:
+        mnemonic = "fcvtzs";
+        break;
+      case NEON_SRI:
+        mnemonic = "sri";
+        break;
+      case NEON_SSHR:
+        mnemonic = "sshr";
+        break;
+      case NEON_USHR:
+        mnemonic = "ushr";
+        break;
+      case NEON_SRSHR:
+        mnemonic = "srshr";
+        break;
+      case NEON_URSHR:
+        mnemonic = "urshr";
+        break;
+      case NEON_SSRA:
+        mnemonic = "ssra";
+        break;
+      case NEON_USRA:
+        mnemonic = "usra";
+        break;
+      case NEON_SRSRA:
+        mnemonic = "srsra";
+        break;
+      case NEON_URSRA:
+        mnemonic = "ursra";
+        break;
       case NEON_SHRN:
         mnemonic = instr->Mask(NEON_Q) ? "shrn2" : "shrn";
         nfd.SetFormatMap(1, &map_shift_ta);
@@ -2575,7 +3844,8 @@
           mnemonic = instr->Mask(NEON_Q) ? "ushll2" : "ushll";
         }
         break;
-      default: form = "(NEONShiftImmediate)";
+      default:
+        form = "(NEONShiftImmediate)";
     }
   } else {
     form = "(NEONShiftImmediate)";
@@ -2584,7 +3854,7 @@
 }
 
 
-void Disassembler::VisitNEONTable(const Instruction* instr) {
+void Disassembler::VisitNEONTable(const Instruction *instr) {
   const char *mnemonic = "unimplemented";
   const char *form = "(NEONTable)";
   const char form_1v[] = "'Vd.%%s, {'Vn.16b}, 'Vm.%%s";
@@ -2592,24 +3862,51 @@
   const char form_3v[] = "'Vd.%%s, {'Vn.16b, v%d.16b, v%d.16b}, 'Vm.%%s";
   const char form_4v[] =
       "'Vd.%%s, {'Vn.16b, v%d.16b, v%d.16b, v%d.16b}, 'Vm.%%s";
-  static const NEONFormatMap map_b = { {30}, {NF_8B, NF_16B} };
+  static const NEONFormatMap map_b = {{30}, {NF_8B, NF_16B}};
   NEONFormatDecoder nfd(instr, &map_b);
 
   switch (instr->Mask(NEONTableMask)) {
-    case NEON_TBL_1v: mnemonic = "tbl"; form = form_1v; break;
-    case NEON_TBL_2v: mnemonic = "tbl"; form = form_2v; break;
-    case NEON_TBL_3v: mnemonic = "tbl"; form = form_3v; break;
-    case NEON_TBL_4v: mnemonic = "tbl"; form = form_4v; break;
-    case NEON_TBX_1v: mnemonic = "tbx"; form = form_1v; break;
-    case NEON_TBX_2v: mnemonic = "tbx"; form = form_2v; break;
-    case NEON_TBX_3v: mnemonic = "tbx"; form = form_3v; break;
-    case NEON_TBX_4v: mnemonic = "tbx"; form = form_4v; break;
-    default: break;
+    case NEON_TBL_1v:
+      mnemonic = "tbl";
+      form = form_1v;
+      break;
+    case NEON_TBL_2v:
+      mnemonic = "tbl";
+      form = form_2v;
+      break;
+    case NEON_TBL_3v:
+      mnemonic = "tbl";
+      form = form_3v;
+      break;
+    case NEON_TBL_4v:
+      mnemonic = "tbl";
+      form = form_4v;
+      break;
+    case NEON_TBX_1v:
+      mnemonic = "tbx";
+      form = form_1v;
+      break;
+    case NEON_TBX_2v:
+      mnemonic = "tbx";
+      form = form_2v;
+      break;
+    case NEON_TBX_3v:
+      mnemonic = "tbx";
+      form = form_3v;
+      break;
+    case NEON_TBX_4v:
+      mnemonic = "tbx";
+      form = form_4v;
+      break;
+    default:
+      break;
   }
 
   char re_form[sizeof(form_4v) + 6];
   int reg_num = instr->Rn();
-  snprintf(re_form, sizeof(re_form), form,
+  snprintf(re_form,
+           sizeof(re_form),
+           form,
            (reg_num + 1) % kNumberOfVRegisters,
            (reg_num + 2) % kNumberOfVRegisters,
            (reg_num + 3) % kNumberOfVRegisters);
@@ -2618,41 +3915,54 @@
 }
 
 
-void Disassembler::VisitNEONPerm(const Instruction* instr) {
+void Disassembler::VisitNEONPerm(const Instruction *instr) {
   const char *mnemonic = "unimplemented";
   const char *form = "'Vd.%s, 'Vn.%s, 'Vm.%s";
   NEONFormatDecoder nfd(instr);
 
   switch (instr->Mask(NEONPermMask)) {
-    case NEON_TRN1: mnemonic = "trn1";   break;
-    case NEON_TRN2: mnemonic = "trn2";  break;
-    case NEON_UZP1: mnemonic = "uzp1"; break;
-    case NEON_UZP2: mnemonic = "uzp2";  break;
-    case NEON_ZIP1: mnemonic = "zip1"; break;
-    case NEON_ZIP2: mnemonic = "zip2"; break;
-    default: form = "(NEONPerm)";
+    case NEON_TRN1:
+      mnemonic = "trn1";
+      break;
+    case NEON_TRN2:
+      mnemonic = "trn2";
+      break;
+    case NEON_UZP1:
+      mnemonic = "uzp1";
+      break;
+    case NEON_UZP2:
+      mnemonic = "uzp2";
+      break;
+    case NEON_ZIP1:
+      mnemonic = "zip1";
+      break;
+    case NEON_ZIP2:
+      mnemonic = "zip2";
+      break;
+    default:
+      form = "(NEONPerm)";
   }
   Format(instr, mnemonic, nfd.Substitute(form));
 }
 
 
-void Disassembler::VisitUnimplemented(const Instruction* instr) {
+void Disassembler::VisitUnimplemented(const Instruction *instr) {
   Format(instr, "unimplemented", "(Unimplemented)");
 }
 
 
-void Disassembler::VisitUnallocated(const Instruction* instr) {
+void Disassembler::VisitUnallocated(const Instruction *instr) {
   Format(instr, "unallocated", "(Unallocated)");
 }
 
 
-void Disassembler::ProcessOutput(const Instruction* /*instr*/) {
+void Disassembler::ProcessOutput(const Instruction * /*instr*/) {
   // The base disasm does nothing more than disassembling into a buffer.
 }
 
 
-void Disassembler::AppendRegisterNameToOutput(const Instruction* instr,
-                                              const CPURegister& reg) {
+void Disassembler::AppendRegisterNameToOutput(const Instruction *instr,
+                                              const CPURegister &reg) {
   USE(instr);
   VIXL_ASSERT(reg.IsValid());
   char reg_char;
@@ -2662,10 +3972,18 @@
   } else {
     VIXL_ASSERT(reg.IsVRegister());
     switch (reg.SizeInBits()) {
-      case kBRegSize: reg_char = 'b'; break;
-      case kHRegSize: reg_char = 'h'; break;
-      case kSRegSize: reg_char = 's'; break;
-      case kDRegSize: reg_char = 'd'; break;
+      case kBRegSize:
+        reg_char = 'b';
+        break;
+      case kHRegSize:
+        reg_char = 'h';
+        break;
+      case kSRegSize:
+        reg_char = 's';
+        break;
+      case kDRegSize:
+        reg_char = 'd';
+        break;
       default:
         VIXL_ASSERT(reg.Is128Bits());
         reg_char = 'q';
@@ -2685,35 +4003,40 @@
 }
 
 
-void Disassembler::AppendPCRelativeOffsetToOutput(const Instruction* instr,
+void Disassembler::AppendPCRelativeOffsetToOutput(const Instruction *instr,
                                                   int64_t offset) {
   USE(instr);
-  char sign = (offset < 0) ? '-' : '+';
-  AppendToOutput("#%c0x%" PRIx64, sign, std::abs(offset));
+  if (offset < 0) {
+    // Cast to uint64_t so that INT64_MIN is handled in a well-defined way.
+    uint64_t abs_offset = -static_cast<uint64_t>(offset);
+    AppendToOutput("#-0x%" PRIx64, abs_offset);
+  } else {
+    AppendToOutput("#+0x%" PRIx64, offset);
+  }
 }
 
 
-void Disassembler::AppendAddressToOutput(const Instruction* instr,
-                                         const void* addr) {
+void Disassembler::AppendAddressToOutput(const Instruction *instr,
+                                         const void *addr) {
   USE(instr);
   AppendToOutput("(addr 0x%" PRIxPTR ")", reinterpret_cast<uintptr_t>(addr));
 }
 
 
-void Disassembler::AppendCodeAddressToOutput(const Instruction* instr,
-                                             const void* addr) {
+void Disassembler::AppendCodeAddressToOutput(const Instruction *instr,
+                                             const void *addr) {
   AppendAddressToOutput(instr, addr);
 }
 
 
-void Disassembler::AppendDataAddressToOutput(const Instruction* instr,
-                                             const void* addr) {
+void Disassembler::AppendDataAddressToOutput(const Instruction *instr,
+                                             const void *addr) {
   AppendAddressToOutput(instr, addr);
 }
 
 
-void Disassembler::AppendCodeRelativeAddressToOutput(const Instruction* instr,
-                                                     const void* addr) {
+void Disassembler::AppendCodeRelativeAddressToOutput(const Instruction *instr,
+                                                     const void *addr) {
   USE(instr);
   int64_t rel_addr = CodeRelativeAddress(addr);
   if (rel_addr >= 0) {
@@ -2725,29 +4048,30 @@
 
 
 void Disassembler::AppendCodeRelativeCodeAddressToOutput(
-    const Instruction* instr, const void* addr) {
+    const Instruction *instr, const void *addr) {
   AppendCodeRelativeAddressToOutput(instr, addr);
 }
 
 
 void Disassembler::AppendCodeRelativeDataAddressToOutput(
-    const Instruction* instr, const void* addr) {
+    const Instruction *instr, const void *addr) {
   AppendCodeRelativeAddressToOutput(instr, addr);
 }
 
 
 void Disassembler::MapCodeAddress(int64_t base_address,
-                                  const Instruction* instr_address) {
-  set_code_address_offset(
-      base_address - reinterpret_cast<intptr_t>(instr_address));
+                                  const Instruction *instr_address) {
+  set_code_address_offset(base_address -
+                          reinterpret_cast<intptr_t>(instr_address));
 }
-int64_t Disassembler::CodeRelativeAddress(const void* addr) {
+int64_t Disassembler::CodeRelativeAddress(const void *addr) {
   return reinterpret_cast<intptr_t>(addr) + code_address_offset();
 }
 
 
-void Disassembler::Format(const Instruction* instr, const char* mnemonic,
-                          const char* format) {
+void Disassembler::Format(const Instruction *instr,
+                          const char *mnemonic,
+                          const char *format) {
   VIXL_ASSERT(mnemonic != NULL);
   ResetOutput();
   Substitute(instr, mnemonic);
@@ -2762,7 +4086,7 @@
 }
 
 
-void Disassembler::Substitute(const Instruction* instr, const char* string) {
+void Disassembler::Substitute(const Instruction *instr, const char *string) {
   char chr = *string++;
   while (chr != '\0') {
     if (chr == '\'') {
@@ -2776,8 +4100,8 @@
 }
 
 
-int Disassembler::SubstituteField(const Instruction* instr,
-                                  const char* format) {
+int Disassembler::SubstituteField(const Instruction *instr,
+                                  const char *format) {
   switch (format[0]) {
     // NB. The remaining substitution prefix characters are: GJKUZ.
     case 'R':  // Register. X or W, selected by sf bit.
@@ -2789,19 +4113,32 @@
     case 'H':
     case 'S':
     case 'D':
-    case 'Q': return SubstituteRegisterField(instr, format);
-    case 'I': return SubstituteImmediateField(instr, format);
-    case 'L': return SubstituteLiteralField(instr, format);
-    case 'N': return SubstituteShiftField(instr, format);
-    case 'P': return SubstitutePrefetchField(instr, format);
-    case 'C': return SubstituteConditionField(instr, format);
-    case 'E': return SubstituteExtendField(instr, format);
-    case 'A': return SubstitutePCRelAddressField(instr, format);
-    case 'T': return SubstituteBranchTargetField(instr, format);
-    case 'O': return SubstituteLSRegOffsetField(instr, format);
-    case 'M': return SubstituteBarrierField(instr, format);
-    case 'K': return SubstituteCrField(instr, format);
-    case 'G': return SubstituteSysOpField(instr, format);
+    case 'Q':
+      return SubstituteRegisterField(instr, format);
+    case 'I':
+      return SubstituteImmediateField(instr, format);
+    case 'L':
+      return SubstituteLiteralField(instr, format);
+    case 'N':
+      return SubstituteShiftField(instr, format);
+    case 'P':
+      return SubstitutePrefetchField(instr, format);
+    case 'C':
+      return SubstituteConditionField(instr, format);
+    case 'E':
+      return SubstituteExtendField(instr, format);
+    case 'A':
+      return SubstitutePCRelAddressField(instr, format);
+    case 'T':
+      return SubstituteBranchTargetField(instr, format);
+    case 'O':
+      return SubstituteLSRegOffsetField(instr, format);
+    case 'M':
+      return SubstituteBarrierField(instr, format);
+    case 'K':
+      return SubstituteCrField(instr, format);
+    case 'G':
+      return SubstituteSysOpField(instr, format);
     default: {
       VIXL_UNREACHABLE();
       return 1;
@@ -2810,8 +4147,8 @@
 }
 
 
-int Disassembler::SubstituteRegisterField(const Instruction* instr,
-                                          const char* format) {
+int Disassembler::SubstituteRegisterField(const Instruction *instr,
+                                          const char *format) {
   char reg_prefix = format[0];
   unsigned reg_num = 0;
   unsigned field_len = 2;
@@ -2824,18 +4161,20 @@
         field_len = 3;
       }
       break;
-    case 'n': reg_num = instr->Rn(); break;
+    case 'n':
+      reg_num = instr->Rn();
+      break;
     case 'm':
       reg_num = instr->Rm();
       switch (format[2]) {
-          // Handle registers tagged with b (bytes), z (instruction), or
-          // r (registers), used for address updates in
-          // NEON load/store instructions.
+        // Handle registers tagged with b (bytes), z (instruction), or
+        // r (registers), used for address updates in
+        // NEON load/store instructions.
         case 'r':
         case 'b':
         case 'z': {
           field_len = 3;
-          char* eimm;
+          char *eimm;
           int imm = static_cast<int>(strtol(&format[3], &eimm, 10));
           field_len += eimm - &format[3];
           if (reg_num == 31) {
@@ -2844,8 +4183,8 @@
                 imm *= (1 << instr->NEONLSSize());
                 break;
               case 'r':
-                imm *= (instr->NEONQ() == 0) ? kDRegSizeInBytes
-                                             : kQRegSizeInBytes;
+                imm *=
+                    (instr->NEONQ() == 0) ? kDRegSizeInBytes : kQRegSizeInBytes;
                 break;
               case 'b':
                 break;
@@ -2862,8 +4201,12 @@
       // by-element instructions.
       reg_num = (instr->Rm() & 0xf);
       break;
-    case 'a': reg_num = instr->Ra(); break;
-    case 's': reg_num = instr->Rs(); break;
+    case 'a':
+      reg_num = instr->Ra();
+      break;
+    case 's':
+      reg_num = instr->Rs();
+      break;
     case 't':
       reg_num = instr->Rt();
       if (format[0] == 'V') {
@@ -2874,13 +4217,14 @@
         }
       } else {
         if (format[2] == '2') {
-        // Handle register specifier Rt2.
+          // Handle register specifier Rt2.
           reg_num = instr->Rt2();
           field_len = 3;
         }
       }
       break;
-    default: VIXL_UNREACHABLE();
+    default:
+      VIXL_UNREACHABLE();
   }
 
   // Increase field length for registers tagged as stack.
@@ -2899,19 +4243,33 @@
 
   switch (reg_prefix) {
     case 'W':
-      reg_type = CPURegister::kRegister; reg_size = kWRegSize; break;
+      reg_type = CPURegister::kRegister;
+      reg_size = kWRegSize;
+      break;
     case 'X':
-      reg_type = CPURegister::kRegister; reg_size = kXRegSize; break;
+      reg_type = CPURegister::kRegister;
+      reg_size = kXRegSize;
+      break;
     case 'B':
-      reg_type = CPURegister::kVRegister; reg_size = kBRegSize; break;
+      reg_type = CPURegister::kVRegister;
+      reg_size = kBRegSize;
+      break;
     case 'H':
-      reg_type = CPURegister::kVRegister; reg_size = kHRegSize; break;
+      reg_type = CPURegister::kVRegister;
+      reg_size = kHRegSize;
+      break;
     case 'S':
-      reg_type = CPURegister::kVRegister; reg_size = kSRegSize; break;
+      reg_type = CPURegister::kVRegister;
+      reg_size = kSRegSize;
+      break;
     case 'D':
-      reg_type = CPURegister::kVRegister; reg_size = kDRegSize; break;
+      reg_type = CPURegister::kVRegister;
+      reg_size = kDRegSize;
+      break;
     case 'Q':
-      reg_type = CPURegister::kVRegister; reg_size = kQRegSize; break;
+      reg_type = CPURegister::kVRegister;
+      reg_size = kQRegSize;
+      break;
     case 'V':
       AppendToOutput("v%d", reg_num);
       return field_len;
@@ -2919,8 +4277,8 @@
       VIXL_UNREACHABLE();
   }
 
-  if ((reg_type == CPURegister::kRegister) &&
-      (reg_num == kZeroRegCode) && (format[2] == 's')) {
+  if ((reg_type == CPURegister::kRegister) && (reg_num == kZeroRegCode) &&
+      (format[2] == 's')) {
     reg_num = kSPRegInternalCode;
   }
 
@@ -2930,8 +4288,8 @@
 }
 
 
-int Disassembler::SubstituteImmediateField(const Instruction* instr,
-                                           const char* format) {
+int Disassembler::SubstituteImmediateField(const Instruction *instr,
+                                           const char *format) {
   VIXL_ASSERT(format[0] == 'I');
 
   switch (format[1]) {
@@ -2943,12 +4301,10 @@
         }
       } else {
         VIXL_ASSERT((format[5] == 'I') || (format[5] == 'N'));
-        uint64_t imm = static_cast<uint64_t>(instr->ImmMoveWide()) <<
-            (16 * instr->ShiftMoveWide());
-        if (format[5] == 'N')
-          imm = ~imm;
-        if (!instr->SixtyFourBits())
-          imm &= UINT64_C(0xffffffff);
+        uint64_t imm = static_cast<uint64_t>(instr->ImmMoveWide())
+                       << (16 * instr->ShiftMoveWide());
+        if (format[5] == 'N') imm = ~imm;
+        if (!instr->SixtyFourBits()) imm &= UINT64_C(0xffffffff);
         AppendToOutput("#0x%" PRIx64, imm);
       }
       return 8;
@@ -2994,12 +4350,13 @@
       AppendToOutput("#0x%" PRIx64 " (%" PRId64 ")", imm, imm);
       return 7;
     }
-    case 'F': {  // IFPSingle, IFPDouble or IFPFBits.
+    case 'F': {                // IFPSingle, IFPDouble or IFPFBits.
       if (format[3] == 'F') {  // IFPFbits.
         AppendToOutput("#%" PRId32, 64 - instr->FPScale());
         return 8;
       } else {
-        AppendToOutput("#0x%" PRIx32 " (%.4f)", instr->ImmFP(),
+        AppendToOutput("#0x%" PRIx32 " (%.4f)",
+                       instr->ImmFP(),
                        format[3] == 'S' ? instr->ImmFP32() : instr->ImmFP64());
         return 9;
       }
@@ -3010,10 +4367,11 @@
     }
     case 'N': {  // INzcv.
       int nzcv = (instr->Nzcv() << Flags_offset);
-      AppendToOutput("#%c%c%c%c", ((nzcv & NFlag) == 0) ? 'n' : 'N',
-                                  ((nzcv & ZFlag) == 0) ? 'z' : 'Z',
-                                  ((nzcv & CFlag) == 0) ? 'c' : 'C',
-                                  ((nzcv & VFlag) == 0) ? 'v' : 'V');
+      AppendToOutput("#%c%c%c%c",
+                     ((nzcv & NFlag) == 0) ? 'n' : 'N',
+                     ((nzcv & ZFlag) == 0) ? 'z' : 'Z',
+                     ((nzcv & CFlag) == 0) ? 'c' : 'C',
+                     ((nzcv & VFlag) == 0) ? 'v' : 'V');
       return 5;
     }
     case 'P': {  // IP - Conditional compare.
@@ -3028,8 +4386,9 @@
       return 8;
     }
     case 'S': {  // IS - Test and branch bit.
-      AppendToOutput("#%" PRId32, (instr->ImmTestBranchBit5() << 5) |
-                                  instr->ImmTestBranchBit40());
+      AppendToOutput("#%" PRId32,
+                     (instr->ImmTestBranchBit5() << 5) |
+                         instr->ImmTestBranchBit40());
       return 2;
     }
     case 's': {  // Is - Shift (immediate).
@@ -3081,8 +4440,8 @@
             if (strncmp(format, "IVInsIndex1", strlen("IVInsIndex1")) == 0) {
               AppendToOutput("%d", rd_index);
               return strlen("IVInsIndex1");
-            } else if (strncmp(format, "IVInsIndex2",
-                       strlen("IVInsIndex2")) == 0) {
+            } else if (strncmp(format, "IVInsIndex2", strlen("IVInsIndex2")) ==
+                       0) {
               AppendToOutput("%d", rn_index);
               return strlen("IVInsIndex2");
             } else {
@@ -3097,16 +4456,17 @@
           return 9;
         }
         case 'M': {  // Modified Immediate cases.
-          if (strncmp(format,
-                      "IVMIImmFPSingle",
-                      strlen("IVMIImmFPSingle")) == 0) {
-            AppendToOutput("#0x%" PRIx32 " (%.4f)", instr->ImmNEONabcdefgh(),
+          if (strncmp(format, "IVMIImmFPSingle", strlen("IVMIImmFPSingle")) ==
+              0) {
+            AppendToOutput("#0x%" PRIx32 " (%.4f)",
+                           instr->ImmNEONabcdefgh(),
                            instr->ImmNEONFP32());
             return strlen("IVMIImmFPSingle");
           } else if (strncmp(format,
                              "IVMIImmFPDouble",
                              strlen("IVMIImmFPDouble")) == 0) {
-            AppendToOutput("#0x%" PRIx32 " (%.4f)", instr->ImmNEONabcdefgh(),
+            AppendToOutput("#0x%" PRIx32 " (%.4f)",
+                           instr->ImmNEONabcdefgh(),
                            instr->ImmNEONFP64());
             return strlen("IVMIImmFPDouble");
           } else if (strncmp(format, "IVMIImm8", strlen("IVMIImm8")) == 0) {
@@ -3123,13 +4483,15 @@
             }
             AppendToOutput("#0x%" PRIx64, imm);
             return strlen("IVMIImm");
-          } else if (strncmp(format, "IVMIShiftAmt1",
+          } else if (strncmp(format,
+                             "IVMIShiftAmt1",
                              strlen("IVMIShiftAmt1")) == 0) {
             int cmode = instr->NEONCmode();
             int shift_amount = 8 * ((cmode >> 1) & 3);
             AppendToOutput("#%d", shift_amount);
             return strlen("IVMIShiftAmt1");
-          } else if (strncmp(format, "IVMIShiftAmt2",
+          } else if (strncmp(format,
+                             "IVMIShiftAmt2",
                              strlen("IVMIShiftAmt2")) == 0) {
             int cmode = instr->NEONCmode();
             int shift_amount = 8 << (cmode & 1);
@@ -3158,8 +4520,8 @@
 }
 
 
-int Disassembler::SubstituteBitfieldImmediateField(const Instruction* instr,
-                                                   const char* format) {
+int Disassembler::SubstituteBitfieldImmediateField(const Instruction *instr,
+                                                   const char *format) {
   VIXL_ASSERT((format[0] == 'I') && (format[1] == 'B'));
   unsigned r = instr->ImmR();
   unsigned s = instr->ImmS();
@@ -3193,12 +4555,12 @@
 }
 
 
-int Disassembler::SubstituteLiteralField(const Instruction* instr,
-                                         const char* format) {
+int Disassembler::SubstituteLiteralField(const Instruction *instr,
+                                         const char *format) {
   VIXL_ASSERT(strncmp(format, "LValue", 6) == 0);
   USE(format);
 
-  const void * address = instr->LiteralAddress<const void *>();
+  const void *address = instr->LiteralAddress<const void *>();
   switch (instr->Mask(LoadLiteralMask)) {
     case LDR_w_lit:
     case LDR_x_lit:
@@ -3211,14 +4573,14 @@
     case PRFM_lit: {
       // Use the prefetch hint to decide how to print the address.
       switch (instr->PrefetchHint()) {
-        case 0x0:     // PLD: prefetch for load.
-        case 0x2:     // PST: prepare for store.
+        case 0x0:  // PLD: prefetch for load.
+        case 0x2:  // PST: prepare for store.
           AppendCodeRelativeDataAddressToOutput(instr, address);
           break;
-        case 0x1:     // PLI: preload instructions.
+        case 0x1:  // PLI: preload instructions.
           AppendCodeRelativeCodeAddressToOutput(instr, address);
           break;
-        case 0x3:     // Unallocated hint.
+        case 0x3:  // Unallocated hint.
           AppendCodeRelativeAddressToOutput(instr, address);
           break;
       }
@@ -3232,8 +4594,8 @@
 }
 
 
-int Disassembler::SubstituteShiftField(const Instruction* instr,
-                                       const char* format) {
+int Disassembler::SubstituteShiftField(const Instruction *instr,
+                                       const char *format) {
   VIXL_ASSERT(format[0] == 'N');
   VIXL_ASSERT(instr->ShiftDP() <= 0x3);
 
@@ -3244,8 +4606,9 @@
     }
     case 'L': {  // HLo.
       if (instr->ImmDPShift() != 0) {
-        const char* shift_type[] = {"lsl", "lsr", "asr", "ror"};
-        AppendToOutput(", %s #%" PRId32, shift_type[instr->ShiftDP()],
+        const char *shift_type[] = {"lsl", "lsr", "asr", "ror"};
+        AppendToOutput(", %s #%" PRId32,
+                       shift_type[instr->ShiftDP()],
                        instr->ImmDPShift());
       }
       return 3;
@@ -3257,45 +4620,60 @@
 }
 
 
-int Disassembler::SubstituteConditionField(const Instruction* instr,
-                                           const char* format) {
+int Disassembler::SubstituteConditionField(const Instruction *instr,
+                                           const char *format) {
   VIXL_ASSERT(format[0] == 'C');
-  const char* condition_code[] = { "eq", "ne", "hs", "lo",
-                                   "mi", "pl", "vs", "vc",
-                                   "hi", "ls", "ge", "lt",
-                                   "gt", "le", "al", "nv" };
+  const char *condition_code[] = {"eq",
+                                  "ne",
+                                  "hs",
+                                  "lo",
+                                  "mi",
+                                  "pl",
+                                  "vs",
+                                  "vc",
+                                  "hi",
+                                  "ls",
+                                  "ge",
+                                  "lt",
+                                  "gt",
+                                  "le",
+                                  "al",
+                                  "nv"};
   int cond;
   switch (format[1]) {
-    case 'B': cond = instr->ConditionBranch(); break;
+    case 'B':
+      cond = instr->ConditionBranch();
+      break;
     case 'I': {
       cond = InvertCondition(static_cast<Condition>(instr->Condition()));
       break;
     }
-    default: cond = instr->Condition();
+    default:
+      cond = instr->Condition();
   }
   AppendToOutput("%s", condition_code[cond]);
   return 4;
 }
 
 
-int Disassembler::SubstitutePCRelAddressField(const Instruction* instr,
-                                              const char* format) {
-  VIXL_ASSERT((strcmp(format, "AddrPCRelByte") == 0) ||   // Used by `adr`.
-              (strcmp(format, "AddrPCRelPage") == 0));    // Used by `adrp`.
+int Disassembler::SubstitutePCRelAddressField(const Instruction *instr,
+                                              const char *format) {
+  VIXL_ASSERT((strcmp(format, "AddrPCRelByte") == 0) ||  // Used by `adr`.
+              (strcmp(format, "AddrPCRelPage") == 0));   // Used by `adrp`.
 
   int64_t offset = instr->ImmPCRel();
 
   // Compute the target address based on the effective address (after applying
   // code_address_offset). This is required for correct behaviour of adrp.
-  const Instruction* base = instr + code_address_offset();
+  const Instruction *base = instr + code_address_offset();
   if (format[9] == 'P') {
     offset *= kPageSize;
     base = AlignDown(base, kPageSize);
   }
   // Strip code_address_offset before printing, so we can use the
   // semantically-correct AppendCodeRelativeAddressToOutput.
-  const void* target =
-      reinterpret_cast<const void*>(base + offset - code_address_offset());
+  const void *target =
+      reinterpret_cast<const void *>(base + offset - code_address_offset());
 
   AppendPCRelativeOffsetToOutput(instr, offset);
   AppendToOutput(" ");
@@ -3304,24 +4682,33 @@
 }
 
 
-int Disassembler::SubstituteBranchTargetField(const Instruction* instr,
-                                              const char* format) {
+int Disassembler::SubstituteBranchTargetField(const Instruction *instr,
+                                              const char *format) {
   VIXL_ASSERT(strncmp(format, "TImm", 4) == 0);
 
   int64_t offset = 0;
   switch (format[5]) {
     // BImmUncn - unconditional branch immediate.
-    case 'n': offset = instr->ImmUncondBranch(); break;
+    case 'n':
+      offset = instr->ImmUncondBranch();
+      break;
     // BImmCond - conditional branch immediate.
-    case 'o': offset = instr->ImmCondBranch(); break;
+    case 'o':
+      offset = instr->ImmCondBranch();
+      break;
     // BImmCmpa - compare and branch immediate.
-    case 'm': offset = instr->ImmCmpBranch(); break;
+    case 'm':
+      offset = instr->ImmCmpBranch();
+      break;
     // BImmTest - test and branch immediate.
-    case 'e': offset = instr->ImmTestBranch(); break;
-    default: VIXL_UNIMPLEMENTED();
+    case 'e':
+      offset = instr->ImmTestBranch();
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
   }
   offset <<= kInstructionSizeLog2;
-  const void* target_address = reinterpret_cast<const void*>(instr + offset);
+  const void *target_address = reinterpret_cast<const void *>(instr + offset);
   VIXL_STATIC_ASSERT(sizeof(*instr) == 1);
 
   AppendPCRelativeOffsetToOutput(instr, offset);
@@ -3332,14 +4719,14 @@
 }
 
 
-int Disassembler::SubstituteExtendField(const Instruction* instr,
-                                        const char* format) {
+int Disassembler::SubstituteExtendField(const Instruction *instr,
+                                        const char *format) {
   VIXL_ASSERT(strncmp(format, "Ext", 3) == 0);
   VIXL_ASSERT(instr->ExtendMode() <= 7);
   USE(format);
 
-  const char* extend_mode[] = { "uxtb", "uxth", "uxtw", "uxtx",
-                                "sxtb", "sxth", "sxtw", "sxtx" };
+  const char *extend_mode[] =
+      {"uxtb", "uxth", "uxtw", "uxtx", "sxtb", "sxth", "sxtw", "sxtx"};
 
   // If rd or rn is SP, uxtw on 32-bit registers and uxtx on 64-bit
   // registers becomes lsl.
@@ -3359,11 +4746,17 @@
 }
 
 
-int Disassembler::SubstituteLSRegOffsetField(const Instruction* instr,
-                                             const char* format) {
+int Disassembler::SubstituteLSRegOffsetField(const Instruction *instr,
+                                             const char *format) {
   VIXL_ASSERT(strncmp(format, "Offsetreg", 9) == 0);
-  const char* extend_mode[] = { "undefined", "undefined", "uxtw", "lsl",
-                                "undefined", "undefined", "sxtw", "sxtx" };
+  const char *extend_mode[] = {"undefined",
+                               "undefined",
+                               "uxtw",
+                               "lsl",
+                               "undefined",
+                               "undefined",
+                               "sxtw",
+                               "sxtx"};
   USE(format);
 
   unsigned shift = instr->ImmShiftLS();
@@ -3388,13 +4781,13 @@
 }
 
 
-int Disassembler::SubstitutePrefetchField(const Instruction* instr,
-                                          const char* format) {
+int Disassembler::SubstitutePrefetchField(const Instruction *instr,
+                                          const char *format) {
   VIXL_ASSERT(format[0] == 'P');
   USE(format);
 
-  static const char* hints[] = {"ld", "li", "st"};
-  static const char* stream_options[] = {"keep", "strm"};
+  static const char *hints[] = {"ld", "li", "st"};
+  static const char *stream_options[] = {"keep", "strm"};
 
   unsigned hint = instr->PrefetchHint();
   unsigned target = instr->PrefetchTarget() + 1;
@@ -3416,17 +4809,15 @@
   return 6;
 }
 
-int Disassembler::SubstituteBarrierField(const Instruction* instr,
-                                         const char* format) {
+int Disassembler::SubstituteBarrierField(const Instruction *instr,
+                                         const char *format) {
   VIXL_ASSERT(format[0] == 'M');
   USE(format);
 
-  static const char* options[4][4] = {
-    { "sy (0b0000)", "oshld", "oshst", "osh" },
-    { "sy (0b0100)", "nshld", "nshst", "nsh" },
-    { "sy (0b1000)", "ishld", "ishst", "ish" },
-    { "sy (0b1100)", "ld", "st", "sy" }
-  };
+  static const char *options[4][4] = {{"sy (0b0000)", "oshld", "oshst", "osh"},
+                                      {"sy (0b0100)", "nshld", "nshst", "nsh"},
+                                      {"sy (0b1000)", "ishld", "ishst", "ish"},
+                                      {"sy (0b1100)", "ld", "st", "sy"}};
   int domain = instr->ImmBarrierDomain();
   int type = instr->ImmBarrierType();
 
@@ -3434,13 +4825,17 @@
   return 1;
 }
 
-int Disassembler::SubstituteSysOpField(const Instruction* instr,
-                                       const char* format) {
+int Disassembler::SubstituteSysOpField(const Instruction *instr,
+                                       const char *format) {
   VIXL_ASSERT(format[0] == 'G');
   int op = -1;
   switch (format[1]) {
-    case '1': op = instr->SysOp1(); break;
-    case '2': op = instr->SysOp2(); break;
+    case '1':
+      op = instr->SysOp1();
+      break;
+    case '2':
+      op = instr->SysOp2();
+      break;
     default:
       VIXL_UNREACHABLE();
   }
@@ -3448,13 +4843,17 @@
   return 2;
 }
 
-int Disassembler::SubstituteCrField(const Instruction* instr,
-                                    const char* format) {
+int Disassembler::SubstituteCrField(const Instruction *instr,
+                                    const char *format) {
   VIXL_ASSERT(format[0] == 'K');
   int cr = -1;
   switch (format[1]) {
-    case 'n': cr = instr->CRn(); break;
-    case 'm': cr = instr->CRm(); break;
+    case 'n':
+      cr = instr->CRn();
+      break;
+    case 'm':
+      cr = instr->CRm();
+      break;
     default:
       VIXL_UNREACHABLE();
   }
@@ -3468,17 +4867,20 @@
 }
 
 
-void Disassembler::AppendToOutput(const char* format, ...) {
+void Disassembler::AppendToOutput(const char *format, ...) {
   va_list args;
   va_start(args, format);
-  buffer_pos_ += vsnprintf(&buffer_[buffer_pos_], buffer_size_ - buffer_pos_,
-          format, args);
+  buffer_pos_ += vsnprintf(&buffer_[buffer_pos_],
+                           buffer_size_ - buffer_pos_,
+                           format,
+                           args);
   va_end(args);
 }
 
 
-void PrintDisassembler::ProcessOutput(const Instruction* instr) {
-  fprintf(stream_, "0x%016" PRIx64 "  %08" PRIx32 "\t\t%s\n",
+void PrintDisassembler::ProcessOutput(const Instruction *instr) {
+  fprintf(stream_,
+          "0x%016" PRIx64 "  %08" PRIx32 "\t\t%s\n",
           reinterpret_cast<uint64_t>(instr),
           instr->InstructionBits(),
           GetOutput());
diff --git a/src/vixl/a64/disasm-a64.h b/src/vixl/a64/disasm-a64.h
index 930df6e..c9be040 100644
--- a/src/vixl/a64/disasm-a64.h
+++ b/src/vixl/a64/disasm-a64.h
@@ -35,22 +35,22 @@
 
 namespace vixl {
 
-class Disassembler: public DecoderVisitor {
+class Disassembler : public DecoderVisitor {
  public:
   Disassembler();
   Disassembler(char* text_buffer, int buffer_size);
   virtual ~Disassembler();
   char* GetOutput();
 
-  // Declare all Visitor functions.
-  #define DECLARE(A) virtual void Visit##A(const Instruction* instr);
+// Declare all Visitor functions.
+#define DECLARE(A) virtual void Visit##A(const Instruction* instr);
   VISITOR_LIST(DECLARE)
-  #undef DECLARE
+#undef DECLARE
 
  protected:
   virtual void ProcessOutput(const Instruction* instr);
 
-  // Default output functions.  The functions below implement a default way of
+  // Default output functions. The functions below implement a default way of
   // printing elements in the disassembly. A sub-class can override these to
   // customize the disassembly output.
 
@@ -106,15 +106,16 @@
   int64_t CodeRelativeAddress(const void* instr);
 
  private:
-  void Format(
-      const Instruction* instr, const char* mnemonic, const char* format);
+  void Format(const Instruction* instr,
+              const char* mnemonic,
+              const char* format);
   void Substitute(const Instruction* instr, const char* string);
   int SubstituteField(const Instruction* instr, const char* format);
   int SubstituteRegisterField(const Instruction* instr, const char* format);
   int SubstituteImmediateField(const Instruction* instr, const char* format);
   int SubstituteLiteralField(const Instruction* instr, const char* format);
-  int SubstituteBitfieldImmediateField(
-      const Instruction* instr, const char* format);
+  int SubstituteBitfieldImmediateField(const Instruction* instr,
+                                       const char* format);
   int SubstituteShiftField(const Instruction* instr, const char* format);
   int SubstituteExtendField(const Instruction* instr, const char* format);
   int SubstituteConditionField(const Instruction* instr, const char* format);
@@ -162,15 +163,15 @@
 };
 
 
-class PrintDisassembler: public Disassembler {
+class PrintDisassembler : public Disassembler {
  public:
-  explicit PrintDisassembler(FILE* stream) : stream_(stream) { }
+  explicit PrintDisassembler(FILE* stream) : stream_(stream) {}
 
  protected:
   virtual void ProcessOutput(const Instruction* instr);
 
  private:
-  FILE *stream_;
+  FILE* stream_;
 };
 }  // namespace vixl
 
diff --git a/src/vixl/a64/instructions-a64.cc b/src/vixl/a64/instructions-a64.cc
index 33992f8..c4915bf 100644
--- a/src/vixl/a64/instructions-a64.cc
+++ b/src/vixl/a64/instructions-a64.cc
@@ -52,8 +52,8 @@
                             unsigned int width) {
   VIXL_ASSERT(width <= 64);
   rotate &= 63;
-  return ((value & ((UINT64_C(1) << rotate) - 1)) <<
-          (width - rotate)) | (value >> rotate);
+  return ((value & ((UINT64_C(1) << rotate) - 1)) << (width - rotate)) |
+         (value >> rotate);
 }
 
 
@@ -94,8 +94,10 @@
       case LDR_h:
       case LDR_s:
       case LDR_d:
-      case LDR_q: return true;
-      default: return false;
+      case LDR_q:
+        return true;
+      default:
+        return false;
     }
   }
 }
@@ -119,8 +121,10 @@
       case STR_h:
       case STR_s:
       case STR_d:
-      case STR_q: return true;
-      default: return false;
+      case STR_q:
+        return true;
+      default:
+        return false;
     }
   }
 }
@@ -199,9 +203,7 @@
 }
 
 
-float Instruction::ImmFP32() const {
-  return Imm8ToFP32(ImmFP());
-}
+float Instruction::ImmFP32() const { return Imm8ToFP32(ImmFP()); }
 
 
 double Instruction::Imm8ToFP64(uint32_t imm8) {
@@ -219,14 +221,10 @@
 }
 
 
-double Instruction::ImmFP64() const {
-  return Imm8ToFP64(ImmFP());
-}
+double Instruction::ImmFP64() const { return Imm8ToFP64(ImmFP()); }
 
 
-float Instruction::ImmNEONFP32() const {
-  return Imm8ToFP32(ImmNEONabcdefgh());
-}
+float Instruction::ImmNEONFP32() const { return Imm8ToFP32(ImmNEONabcdefgh()); }
 
 
 double Instruction::ImmNEONFP64() const {
@@ -253,12 +251,15 @@
   VIXL_STATIC_ASSERT(kWRegSizeInBytes == kSRegSizeInBytes);
   switch (op) {
     case STP_q:
-    case LDP_q: return kQRegSizeInBytesLog2;
+    case LDP_q:
+      return kQRegSizeInBytesLog2;
     case STP_x:
     case LDP_x:
     case STP_d:
-    case LDP_d: return kXRegSizeInBytesLog2;
-    default: return kWRegSizeInBytesLog2;
+    case LDP_d:
+      return kXRegSizeInBytesLog2;
+    default:
+      return kWRegSizeInBytesLog2;
   }
 }
 
@@ -293,7 +294,7 @@
 
 
 const Instruction* Instruction::ImmPCOffsetTarget() const {
-  const Instruction * base = this;
+  const Instruction* base = this;
   ptrdiff_t offset;
   if (IsPCRelAddressing()) {
     // ADR and ADRP.
@@ -316,11 +317,16 @@
 
 int Instruction::ImmBranch() const {
   switch (BranchType()) {
-    case CondBranchType: return ImmCondBranch();
-    case UncondBranchType: return ImmUncondBranch();
-    case CompareBranchType: return ImmCmpBranch();
-    case TestBranchType: return ImmTestBranch();
-    default: VIXL_UNREACHABLE();
+    case CondBranchType:
+      return ImmCondBranch();
+    case UncondBranchType:
+      return ImmUncondBranch();
+    case CompareBranchType:
+      return ImmCmpBranch();
+    case TestBranchType:
+      return ImmTestBranch();
+    default:
+      VIXL_UNREACHABLE();
   }
   return 0;
 }
@@ -377,7 +383,8 @@
       imm_mask = ImmTestBranch_mask;
       break;
     }
-    default: VIXL_UNREACHABLE();
+    default:
+      VIXL_UNREACHABLE();
   }
   SetInstructionBits(Mask(~imm_mask) | branch_imm);
 }
@@ -397,13 +404,21 @@
   VIXL_ASSERT(vform == kFormat8H || vform == kFormat4S || vform == kFormat2D ||
               vform == kFormatH || vform == kFormatS || vform == kFormatD);
   switch (vform) {
-    case kFormat8H: return kFormat8B;
-    case kFormat4S: return kFormat4H;
-    case kFormat2D: return kFormat2S;
-    case kFormatH:  return kFormatB;
-    case kFormatS:  return kFormatH;
-    case kFormatD:  return kFormatS;
-    default: VIXL_UNREACHABLE(); return kFormatUndefined;
+    case kFormat8H:
+      return kFormat8B;
+    case kFormat4S:
+      return kFormat4H;
+    case kFormat2D:
+      return kFormat2S;
+    case kFormatH:
+      return kFormatB;
+    case kFormatS:
+      return kFormatH;
+    case kFormatD:
+      return kFormatS;
+    default:
+      VIXL_UNREACHABLE();
+      return kFormatUndefined;
   }
 }
 
@@ -412,13 +427,21 @@
   VIXL_ASSERT(vform == kFormat8B || vform == kFormat4H || vform == kFormat2S ||
               vform == kFormatB || vform == kFormatH || vform == kFormatS);
   switch (vform) {
-    case kFormat8B: return kFormat8H;
-    case kFormat4H: return kFormat4S;
-    case kFormat2S: return kFormat2D;
-    case kFormatB:  return kFormatH;
-    case kFormatH:  return kFormatS;
-    case kFormatS:  return kFormatD;
-    default: VIXL_UNREACHABLE(); return kFormatUndefined;
+    case kFormat8B:
+      return kFormat8H;
+    case kFormat4H:
+      return kFormat4S;
+    case kFormat2S:
+      return kFormat2D;
+    case kFormatB:
+      return kFormatH;
+    case kFormatH:
+      return kFormatS;
+    case kFormatS:
+      return kFormatD;
+    default:
+      VIXL_UNREACHABLE();
+      return kFormatUndefined;
   }
 }
 
@@ -427,39 +450,58 @@
   switch (vform) {
     case kFormatB:
     case kFormat8B:
-    case kFormat16B: return kFormat16B;
+    case kFormat16B:
+      return kFormat16B;
     case kFormatH:
     case kFormat4H:
-    case kFormat8H:  return kFormat8H;
+    case kFormat8H:
+      return kFormat8H;
     case kFormatS:
     case kFormat2S:
-    case kFormat4S:  return kFormat4S;
+    case kFormat4S:
+      return kFormat4S;
     case kFormatD:
     case kFormat1D:
-    case kFormat2D:  return kFormat2D;
-    default: VIXL_UNREACHABLE(); return kFormatUndefined;
+    case kFormat2D:
+      return kFormat2D;
+    default:
+      VIXL_UNREACHABLE();
+      return kFormatUndefined;
   }
 }
 
 VectorFormat VectorFormatHalfWidthDoubleLanes(const VectorFormat vform) {
   switch (vform) {
-    case kFormat4H: return kFormat8B;
-    case kFormat8H: return kFormat16B;
-    case kFormat2S: return kFormat4H;
-    case kFormat4S: return kFormat8H;
-    case kFormat1D: return kFormat2S;
-    case kFormat2D: return kFormat4S;
-    default: VIXL_UNREACHABLE(); return kFormatUndefined;
+    case kFormat4H:
+      return kFormat8B;
+    case kFormat8H:
+      return kFormat16B;
+    case kFormat2S:
+      return kFormat4H;
+    case kFormat4S:
+      return kFormat8H;
+    case kFormat1D:
+      return kFormat2S;
+    case kFormat2D:
+      return kFormat4S;
+    default:
+      VIXL_UNREACHABLE();
+      return kFormatUndefined;
   }
 }
 
 VectorFormat VectorFormatDoubleLanes(const VectorFormat vform) {
   VIXL_ASSERT(vform == kFormat8B || vform == kFormat4H || vform == kFormat2S);
   switch (vform) {
-    case kFormat8B: return kFormat16B;
-    case kFormat4H: return kFormat8H;
-    case kFormat2S: return kFormat4S;
-    default: VIXL_UNREACHABLE(); return kFormatUndefined;
+    case kFormat8B:
+      return kFormat16B;
+    case kFormat4H:
+      return kFormat8H;
+    case kFormat2S:
+      return kFormat4S;
+    default:
+      VIXL_UNREACHABLE();
+      return kFormatUndefined;
   }
 }
 
@@ -467,21 +509,32 @@
 VectorFormat VectorFormatHalfLanes(const VectorFormat vform) {
   VIXL_ASSERT(vform == kFormat16B || vform == kFormat8H || vform == kFormat4S);
   switch (vform) {
-    case kFormat16B: return kFormat8B;
-    case kFormat8H: return kFormat4H;
-    case kFormat4S: return kFormat2S;
-    default: VIXL_UNREACHABLE(); return kFormatUndefined;
+    case kFormat16B:
+      return kFormat8B;
+    case kFormat8H:
+      return kFormat4H;
+    case kFormat4S:
+      return kFormat2S;
+    default:
+      VIXL_UNREACHABLE();
+      return kFormatUndefined;
   }
 }
 
 
 VectorFormat ScalarFormatFromLaneSize(int laneSize) {
   switch (laneSize) {
-    case 8:  return kFormatB;
-    case 16: return kFormatH;
-    case 32: return kFormatS;
-    case 64: return kFormatD;
-    default: VIXL_UNREACHABLE(); return kFormatUndefined;
+    case 8:
+      return kFormatB;
+    case 16:
+      return kFormatH;
+    case 32:
+      return kFormatS;
+    case 64:
+      return kFormatD;
+    default:
+      VIXL_UNREACHABLE();
+      return kFormatUndefined;
   }
 }
 
@@ -489,15 +542,21 @@
 unsigned RegisterSizeInBitsFromFormat(VectorFormat vform) {
   VIXL_ASSERT(vform != kFormatUndefined);
   switch (vform) {
-    case kFormatB: return kBRegSize;
-    case kFormatH: return kHRegSize;
-    case kFormatS: return kSRegSize;
-    case kFormatD: return kDRegSize;
+    case kFormatB:
+      return kBRegSize;
+    case kFormatH:
+      return kHRegSize;
+    case kFormatS:
+      return kSRegSize;
+    case kFormatD:
+      return kDRegSize;
     case kFormat8B:
     case kFormat4H:
     case kFormat2S:
-    case kFormat1D: return kDRegSize;
-    default: return kQRegSize;
+    case kFormat1D:
+      return kDRegSize;
+    default:
+      return kQRegSize;
   }
 }
 
@@ -512,17 +571,23 @@
   switch (vform) {
     case kFormatB:
     case kFormat8B:
-    case kFormat16B: return 8;
+    case kFormat16B:
+      return 8;
     case kFormatH:
     case kFormat4H:
-    case kFormat8H: return 16;
+    case kFormat8H:
+      return 16;
     case kFormatS:
     case kFormat2S:
-    case kFormat4S: return 32;
+    case kFormat4S:
+      return 32;
     case kFormatD:
     case kFormat1D:
-    case kFormat2D: return 64;
-    default: VIXL_UNREACHABLE(); return 0;
+    case kFormat2D:
+      return 64;
+    default:
+      VIXL_UNREACHABLE();
+      return 0;
   }
 }
 
@@ -537,17 +602,23 @@
   switch (vform) {
     case kFormatB:
     case kFormat8B:
-    case kFormat16B: return 0;
+    case kFormat16B:
+      return 0;
     case kFormatH:
     case kFormat4H:
-    case kFormat8H: return 1;
+    case kFormat8H:
+      return 1;
     case kFormatS:
     case kFormat2S:
-    case kFormat4S: return 2;
+    case kFormat4S:
+      return 2;
     case kFormatD:
     case kFormat1D:
-    case kFormat2D: return 3;
-    default: VIXL_UNREACHABLE(); return 0;
+    case kFormat2D:
+      return 3;
+    default:
+      VIXL_UNREACHABLE();
+      return 0;
   }
 }
 
@@ -555,19 +626,26 @@
 int LaneCountFromFormat(VectorFormat vform) {
   VIXL_ASSERT(vform != kFormatUndefined);
   switch (vform) {
-    case kFormat16B: return 16;
+    case kFormat16B:
+      return 16;
     case kFormat8B:
-    case kFormat8H: return 8;
+    case kFormat8H:
+      return 8;
     case kFormat4H:
-    case kFormat4S: return 4;
+    case kFormat4S:
+      return 4;
     case kFormat2S:
-    case kFormat2D: return 2;
+    case kFormat2D:
+      return 2;
     case kFormat1D:
     case kFormatB:
     case kFormatH:
     case kFormatS:
-    case kFormatD: return 1;
-    default: VIXL_UNREACHABLE(); return 0;
+    case kFormatD:
+      return 1;
+    default:
+      VIXL_UNREACHABLE();
+      return 0;
   }
 }
 
@@ -577,17 +655,23 @@
   switch (vform) {
     case kFormatB:
     case kFormat8B:
-    case kFormat16B: return 16;
+    case kFormat16B:
+      return 16;
     case kFormatH:
     case kFormat4H:
-    case kFormat8H: return 8;
+    case kFormat8H:
+      return 8;
     case kFormatS:
     case kFormat2S:
-    case kFormat4S: return 4;
+    case kFormat4S:
+      return 4;
     case kFormatD:
     case kFormat1D:
-    case kFormat2D: return 2;
-    default: VIXL_UNREACHABLE(); return 0;
+    case kFormat2D:
+      return 2;
+    default:
+      VIXL_UNREACHABLE();
+      return 0;
   }
 }
 
@@ -599,8 +683,10 @@
     case kFormatB:
     case kFormatH:
     case kFormatS:
-    case kFormatD: return false;
-    default: return true;
+    case kFormatD:
+      return false;
+    default:
+      return true;
   }
 }
 
@@ -619,4 +705,3 @@
   return UINT64_MAX >> (64 - LaneSizeInBitsFromFormat(vform));
 }
 }  // namespace vixl
-
diff --git a/src/vixl/a64/instructions-a64.h b/src/vixl/a64/instructions-a64.h
index 7e0dbae..786c02d 100644
--- a/src/vixl/a64/instructions-a64.h
+++ b/src/vixl/a64/instructions-a64.h
@@ -98,8 +98,8 @@
 
 const unsigned kAddressTagOffset = 56;
 const unsigned kAddressTagWidth = 8;
-const uint64_t kAddressTagMask =
-    ((UINT64_C(1) << kAddressTagWidth) - 1) << kAddressTagOffset;
+const uint64_t kAddressTagMask = ((UINT64_C(1) << kAddressTagWidth) - 1)
+                                 << kAddressTagOffset;
 VIXL_STATIC_ASSERT(kAddressTagMask == UINT64_C(0xff00000000000000));
 
 // AArch64 floating-point specifics. These match IEEE-754.
@@ -128,17 +128,13 @@
 
 enum ImmBranchType {
   UnknownBranchType = 0,
-  CondBranchType    = 1,
-  UncondBranchType  = 2,
+  CondBranchType = 1,
+  UncondBranchType = 2,
   CompareBranchType = 3,
-  TestBranchType    = 4
+  TestBranchType = 4
 };
 
-enum AddrMode {
-  Offset,
-  PreIndex,
-  PostIndex
-};
+enum AddrMode { Offset, PreIndex, PostIndex };
 
 enum FPRounding {
   // The first four values are encodable directly by FPCR<RMode>.
@@ -153,10 +149,7 @@
   FPRoundOdd
 };
 
-enum Reg31Mode {
-  Reg31IsStackPointer,
-  Reg31IsZeroRegister
-};
+enum Reg31Mode { Reg31IsStackPointer, Reg31IsZeroRegister };
 
 // Instructions. ---------------------------------------------------------------
 
@@ -170,9 +163,7 @@
     *(reinterpret_cast<Instr*>(this)) = new_instr;
   }
 
-  int Bit(int pos) const {
-    return (InstructionBits() >> pos) & 1;
-  }
+  int Bit(int pos) const { return (InstructionBits() >> pos) & 1; }
 
   uint32_t Bits(int msb, int lsb) const {
     return unsigned_bitextract_32(msb, lsb, InstructionBits());
@@ -183,14 +174,12 @@
     return signed_bitextract_32(msb, lsb, bits);
   }
 
-  Instr Mask(uint32_t mask) const {
-    return InstructionBits() & mask;
-  }
+  Instr Mask(uint32_t mask) const { return InstructionBits() & mask; }
 
-  #define DEFINE_GETTER(Name, HighBit, LowBit, Func)             \
+#define DEFINE_GETTER(Name, HighBit, LowBit, Func) \
   int32_t Name() const { return Func(HighBit, LowBit); }
   INSTRUCTION_FIELDS_LIST(DEFINE_GETTER)
-  #undef DEFINE_GETTER
+#undef DEFINE_GETTER
 
   // ImmPCRel is a compound field (not present in INSTRUCTION_FIELDS_LIST),
   // formed from ImmPCRelLo and ImmPCRelHi.
@@ -238,13 +227,9 @@
     return Mask(CompareBranchFMask) == CompareBranchFixed;
   }
 
-  bool IsTestBranch() const {
-    return Mask(TestBranchFMask) == TestBranchFixed;
-  }
+  bool IsTestBranch() const { return Mask(TestBranchFMask) == TestBranchFixed; }
 
-  bool IsImmBranch() const {
-    return BranchType() != UnknownBranchType;
-  }
+  bool IsImmBranch() const { return BranchType() != UnknownBranchType; }
 
   bool IsPCRelAddressing() const {
     return Mask(PCRelAddressingFMask) == PCRelAddressingFixed;
@@ -390,28 +375,24 @@
     return literal;
   }
 
-  float LiteralFP32() const {
-    return rawbits_to_float(Literal32());
-  }
+  float LiteralFP32() const { return rawbits_to_float(Literal32()); }
 
-  double LiteralFP64() const {
-    return rawbits_to_double(Literal64());
-  }
+  double LiteralFP64() const { return rawbits_to_double(Literal64()); }
 
-  const Instruction* NextInstruction() const {
-    return this + kInstructionSize;
-  }
+  const Instruction* NextInstruction() const { return this + kInstructionSize; }
 
   const Instruction* InstructionAtOffset(int64_t offset) const {
     VIXL_ASSERT(IsWordAligned(this + offset));
     return this + offset;
   }
 
-  template<typename T> static Instruction* Cast(T src) {
+  template <typename T>
+  static Instruction* Cast(T src) {
     return reinterpret_cast<Instruction*>(src);
   }
 
-  template<typename T> static const Instruction* CastConst(T src) {
+  template <typename T>
+  static const Instruction* CastConst(T src) {
     return reinterpret_cast<const Instruction*>(src);
   }
 
@@ -429,14 +410,14 @@
 // Functions for handling NEON vector format information.
 enum VectorFormat {
   kFormatUndefined = 0xffffffff,
-  kFormat8B  = NEON_8B,
+  kFormat8B = NEON_8B,
   kFormat16B = NEON_16B,
-  kFormat4H  = NEON_4H,
-  kFormat8H  = NEON_8H,
-  kFormat2S  = NEON_2S,
-  kFormat4S  = NEON_4S,
-  kFormat1D  = NEON_1D,
-  kFormat2D  = NEON_2D,
+  kFormat4H = NEON_4H,
+  kFormat8H = NEON_8H,
+  kFormat2S = NEON_2S,
+  kFormat4S = NEON_4S,
+  kFormat1D = NEON_1D,
+  kFormat2D = NEON_2D,
 
   // Scalar formats. We add the scalar bit to distinguish between scalar and
   // vector enumerations; the bit is always set in the encoding of scalar ops
@@ -470,6 +451,7 @@
 uint64_t MaxUintFromFormat(VectorFormat vform);
 
 
+// clang-format off
 enum NEONFormat {
   NF_UNDEF = 0,
   NF_8B    = 1,
@@ -485,6 +467,7 @@
   NF_S     = 11,
   NF_D     = 12
 };
+// clang-format on
 
 static const unsigned kNEONFormatMaxBits = 6;
 
@@ -498,10 +481,7 @@
 
 class NEONFormatDecoder {
  public:
-  enum SubstitutionMode {
-    kPlaceholder,
-    kFormat
-  };
+  enum SubstitutionMode { kPlaceholder, kFormat };
 
   // Construct a format decoder with increasingly specific format maps for each
   // subsitution. If no format map is specified, the default is the integer
@@ -510,8 +490,7 @@
     instrbits_ = instr->InstructionBits();
     SetFormatMaps(IntegerFormatMap());
   }
-  NEONFormatDecoder(const Instruction* instr,
-                    const NEONFormatMap* format) {
+  NEONFormatDecoder(const Instruction* instr, const NEONFormatMap* format) {
     instrbits_ = instr->InstructionBits();
     SetFormatMaps(format);
   }
@@ -556,7 +535,9 @@
                          SubstitutionMode mode0 = kFormat,
                          SubstitutionMode mode1 = kFormat,
                          SubstitutionMode mode2 = kFormat) {
-    snprintf(form_buffer_, sizeof(form_buffer_), string,
+    snprintf(form_buffer_,
+             sizeof(form_buffer_),
+             string,
              GetSubstitute(0, mode0),
              GetSubstitute(1, mode1),
              GetSubstitute(2, mode2));
@@ -577,12 +558,19 @@
   }
 
   VectorFormat GetVectorFormat(const NEONFormatMap* format_map) {
-    static const VectorFormat vform[] = {
-      kFormatUndefined,
-      kFormat8B, kFormat16B, kFormat4H, kFormat8H,
-      kFormat2S, kFormat4S, kFormat1D, kFormat2D,
-      kFormatB, kFormatH, kFormatS, kFormatD
-    };
+    static const VectorFormat vform[] = {kFormatUndefined,
+                                         kFormat8B,
+                                         kFormat16B,
+                                         kFormat4H,
+                                         kFormat8H,
+                                         kFormat2S,
+                                         kFormat4S,
+                                         kFormat1D,
+                                         kFormat2D,
+                                         kFormatB,
+                                         kFormatH,
+                                         kFormatS,
+                                         kFormatD};
     VIXL_ASSERT(GetNEONFormat(format_map) < (sizeof(vform) / sizeof(vform[0])));
     return vform[GetNEONFormat(format_map)];
   }
@@ -592,10 +580,9 @@
   // The integer format map uses three bits (Q, size<1:0>) to encode the
   // "standard" set of NEON integer vector formats.
   static const NEONFormatMap* IntegerFormatMap() {
-    static const NEONFormatMap map = {
-      {23, 22, 30},
-      {NF_8B, NF_16B, NF_4H, NF_8H, NF_2S, NF_4S, NF_UNDEF, NF_2D}
-    };
+    static const NEONFormatMap map =
+        {{23, 22, 30},
+         {NF_8B, NF_16B, NF_4H, NF_8H, NF_2S, NF_4S, NF_UNDEF, NF_2D}};
     return &map;
   }
 
@@ -603,9 +590,7 @@
   // long set of NEON integer vector formats. These are used in narrow, wide
   // and long operations.
   static const NEONFormatMap* LongIntegerFormatMap() {
-    static const NEONFormatMap map = {
-      {23, 22}, {NF_8H, NF_4S, NF_2D}
-    };
+    static const NEONFormatMap map = {{23, 22}, {NF_8H, NF_4S, NF_2D}};
     return &map;
   }
 
@@ -614,28 +599,24 @@
   static const NEONFormatMap* FPFormatMap() {
     // The FP format map assumes two bits (Q, size<0>) are used to encode the
     // NEON FP vector formats: NF_2S, NF_4S, NF_2D.
-    static const NEONFormatMap map = {
-      {22, 30}, {NF_2S, NF_4S, NF_UNDEF, NF_2D}
-    };
+    static const NEONFormatMap map = {{22, 30},
+                                      {NF_2S, NF_4S, NF_UNDEF, NF_2D}};
     return &map;
   }
 
   // The load/store format map uses three bits (Q, 11, 10) to encode the
   // set of NEON vector formats.
   static const NEONFormatMap* LoadStoreFormatMap() {
-    static const NEONFormatMap map = {
-      {11, 10, 30},
-      {NF_8B, NF_16B, NF_4H, NF_8H, NF_2S, NF_4S, NF_1D, NF_2D}
-    };
+    static const NEONFormatMap map =
+        {{11, 10, 30},
+         {NF_8B, NF_16B, NF_4H, NF_8H, NF_2S, NF_4S, NF_1D, NF_2D}};
     return &map;
   }
 
   // The logical format map uses one bit (Q) to encode the NEON vector format:
   // NF_8B, NF_16B.
   static const NEONFormatMap* LogicalFormatMap() {
-    static const NEONFormatMap map = {
-      {30}, {NF_8B, NF_16B}
-    };
+    static const NEONFormatMap map = {{30}, {NF_8B, NF_16B}};
     return &map;
   }
 
@@ -644,40 +625,60 @@
   // xxx10->8B, xxx11->16B, xx100->4H, xx101->8H
   // x1000->2S, x1001->4S,  10001->2D, all others undefined.
   static const NEONFormatMap* TriangularFormatMap() {
-    static const NEONFormatMap map = {
-      {19, 18, 17, 16, 30},
-      {NF_UNDEF, NF_UNDEF, NF_8B, NF_16B, NF_4H, NF_8H, NF_8B, NF_16B, NF_2S,
-       NF_4S, NF_8B, NF_16B, NF_4H, NF_8H, NF_8B, NF_16B, NF_UNDEF, NF_2D,
-       NF_8B, NF_16B, NF_4H, NF_8H, NF_8B, NF_16B, NF_2S, NF_4S, NF_8B, NF_16B,
-       NF_4H, NF_8H, NF_8B, NF_16B}
-    };
+    static const NEONFormatMap map = {{19, 18, 17, 16, 30},
+                                      {NF_UNDEF,
+                                       NF_UNDEF,
+                                       NF_8B,
+                                       NF_16B,
+                                       NF_4H,
+                                       NF_8H,
+                                       NF_8B,
+                                       NF_16B,
+                                       NF_2S,
+                                       NF_4S,
+                                       NF_8B,
+                                       NF_16B,
+                                       NF_4H,
+                                       NF_8H,
+                                       NF_8B,
+                                       NF_16B,
+                                       NF_UNDEF,
+                                       NF_2D,
+                                       NF_8B,
+                                       NF_16B,
+                                       NF_4H,
+                                       NF_8H,
+                                       NF_8B,
+                                       NF_16B,
+                                       NF_2S,
+                                       NF_4S,
+                                       NF_8B,
+                                       NF_16B,
+                                       NF_4H,
+                                       NF_8H,
+                                       NF_8B,
+                                       NF_16B}};
     return &map;
   }
 
   // The scalar format map uses two bits (size<1:0>) to encode the NEON scalar
   // formats: NF_B, NF_H, NF_S, NF_D.
   static const NEONFormatMap* ScalarFormatMap() {
-    static const NEONFormatMap map = {
-      {23, 22}, {NF_B, NF_H, NF_S, NF_D}
-    };
+    static const NEONFormatMap map = {{23, 22}, {NF_B, NF_H, NF_S, NF_D}};
     return &map;
   }
 
   // The long scalar format map uses two bits (size<1:0>) to encode the longer
   // NEON scalar formats: NF_H, NF_S, NF_D.
   static const NEONFormatMap* LongScalarFormatMap() {
-    static const NEONFormatMap map = {
-      {23, 22}, {NF_H, NF_S, NF_D}
-    };
+    static const NEONFormatMap map = {{23, 22}, {NF_H, NF_S, NF_D}};
     return &map;
   }
 
   // The FP scalar format map assumes one bit (size<0>) is used to encode the
   // NEON FP scalar formats: NF_S, NF_D.
   static const NEONFormatMap* FPScalarFormatMap() {
-    static const NEONFormatMap map = {
-      {22}, {NF_S, NF_D}
-    };
+    static const NEONFormatMap map = {{22}, {NF_S, NF_D}};
     return &map;
   }
 
@@ -685,11 +686,23 @@
   // the NEON FP scalar formats:
   // xxx1->B, xx10->H, x100->S, 1000->D, all others undefined.
   static const NEONFormatMap* TriangularScalarFormatMap() {
-    static const NEONFormatMap map = {
-      {19, 18, 17, 16},
-      {NF_UNDEF, NF_B, NF_H, NF_B, NF_S, NF_B, NF_H, NF_B,
-       NF_D,     NF_B, NF_H, NF_B, NF_S, NF_B, NF_H, NF_B}
-    };
+    static const NEONFormatMap map = {{19, 18, 17, 16},
+                                      {NF_UNDEF,
+                                       NF_B,
+                                       NF_H,
+                                       NF_B,
+                                       NF_S,
+                                       NF_B,
+                                       NF_H,
+                                       NF_B,
+                                       NF_D,
+                                       NF_B,
+                                       NF_H,
+                                       NF_B,
+                                       NF_S,
+                                       NF_B,
+                                       NF_H,
+                                       NF_B}};
     return &map;
   }
 
@@ -712,26 +725,29 @@
 
   // Convert a NEONFormat into a string.
   static const char* NEONFormatAsString(NEONFormat format) {
+    // clang-format off
     static const char* formats[] = {
       "undefined",
       "8b", "16b", "4h", "8h", "2s", "4s", "1d", "2d",
       "b", "h", "s", "d"
     };
+    // clang-format on
     VIXL_ASSERT(format < (sizeof(formats) / sizeof(formats[0])));
     return formats[format];
   }
 
   // Convert a NEONFormat into a register placeholder string.
   static const char* NEONFormatAsPlaceholder(NEONFormat format) {
-    VIXL_ASSERT((format == NF_B) || (format == NF_H) ||
-                (format == NF_S) || (format == NF_D) ||
-                (format == NF_UNDEF));
+    VIXL_ASSERT((format == NF_B) || (format == NF_H) || (format == NF_S) ||
+                (format == NF_D) || (format == NF_UNDEF));
+    // clang-format off
     static const char* formats[] = {
       "undefined",
       "undefined", "undefined", "undefined", "undefined",
       "undefined", "undefined", "undefined", "undefined",
       "'B", "'H", "'S", "'D"
     };
+    // clang-format on
     return formats[format];
   }
 
diff --git a/src/vixl/a64/instrument-a64.cc b/src/vixl/a64/instrument-a64.cc
index 7de1255..92b7063 100644
--- a/src/vixl/a64/instrument-a64.cc
+++ b/src/vixl/a64/instrument-a64.cc
@@ -35,19 +35,13 @@
 }
 
 
-void Counter::Enable() {
-  enabled_ = true;
-}
+void Counter::Enable() { enabled_ = true; }
 
 
-void Counter::Disable() {
-  enabled_ = false;
-}
+void Counter::Disable() { enabled_ = false; }
 
 
-bool Counter::IsEnabled() {
-  return enabled_;
-}
+bool Counter::IsEnabled() { return enabled_; }
 
 
 void Counter::Increment() {
@@ -67,14 +61,10 @@
 }
 
 
-const char* Counter::name() {
-  return name_;
-}
+const char* Counter::name() { return name_; }
 
 
-CounterType Counter::type() {
-  return type_;
-}
+CounterType Counter::type() { return type_; }
 
 
 struct CounterDescriptor {
@@ -83,42 +73,40 @@
 };
 
 
-static const CounterDescriptor kCounterList[] = {
-  {"Instruction", Cumulative},
+static const CounterDescriptor kCounterList[] = {{"Instruction", Cumulative},
 
-  {"Move Immediate", Gauge},
-  {"Add/Sub DP", Gauge},
-  {"Logical DP", Gauge},
-  {"Other Int DP", Gauge},
-  {"FP DP", Gauge},
+                                                 {"Move Immediate", Gauge},
+                                                 {"Add/Sub DP", Gauge},
+                                                 {"Logical DP", Gauge},
+                                                 {"Other Int DP", Gauge},
+                                                 {"FP DP", Gauge},
 
-  {"Conditional Select", Gauge},
-  {"Conditional Compare", Gauge},
+                                                 {"Conditional Select", Gauge},
+                                                 {"Conditional Compare", Gauge},
 
-  {"Unconditional Branch", Gauge},
-  {"Compare and Branch", Gauge},
-  {"Test and Branch", Gauge},
-  {"Conditional Branch", Gauge},
+                                                 {"Unconditional Branch",
+                                                  Gauge},
+                                                 {"Compare and Branch", Gauge},
+                                                 {"Test and Branch", Gauge},
+                                                 {"Conditional Branch", Gauge},
 
-  {"Load Integer", Gauge},
-  {"Load FP", Gauge},
-  {"Load Pair", Gauge},
-  {"Load Literal", Gauge},
+                                                 {"Load Integer", Gauge},
+                                                 {"Load FP", Gauge},
+                                                 {"Load Pair", Gauge},
+                                                 {"Load Literal", Gauge},
 
-  {"Store Integer", Gauge},
-  {"Store FP", Gauge},
-  {"Store Pair", Gauge},
+                                                 {"Store Integer", Gauge},
+                                                 {"Store FP", Gauge},
+                                                 {"Store Pair", Gauge},
 
-  {"PC Addressing", Gauge},
-  {"Other", Gauge},
-  {"NEON", Gauge},
-  {"Crypto", Gauge}
-};
+                                                 {"PC Addressing", Gauge},
+                                                 {"Other", Gauge},
+                                                 {"NEON", Gauge},
+                                                 {"Crypto", Gauge}};
 
 
 Instrument::Instrument(const char* datafile, uint64_t sample_period)
     : output_stream_(stdout), sample_period_(sample_period) {
-
   // Set up the output stream. If datafile is non-NULL, use that file. If it
   // can't be opened, or datafile is NULL, use stdout.
   if (datafile != NULL) {
@@ -130,7 +118,7 @@
   }
 
   static const int num_counters =
-    sizeof(kCounterList) / sizeof(CounterDescriptor);
+      sizeof(kCounterList) / sizeof(CounterDescriptor);
 
   // Dump an instrumentation description comment at the top of the file.
   fprintf(output_stream_, "# counters=%d\n", num_counters);
@@ -169,8 +157,8 @@
   VIXL_ASSERT(counter->type() == Cumulative);
   counter->Increment();
 
-  if ((sample_period_ != 0) && counter->IsEnabled()
-      && (counter->count() % sample_period_) == 0) {
+  if ((sample_period_ != 0) && counter->IsEnabled() &&
+      (counter->count() % sample_period_) == 0) {
     DumpCounters();
   }
 }
@@ -202,9 +190,14 @@
 
 void Instrument::HandleInstrumentationEvent(unsigned event) {
   switch (event) {
-    case InstrumentStateEnable: Enable(); break;
-    case InstrumentStateDisable: Disable(); break;
-    default: DumpEventMarker(event);
+    case InstrumentStateEnable:
+      Enable();
+      break;
+    case InstrumentStateDisable:
+      Disable();
+      break;
+    default:
+      DumpEventMarker(event);
   }
 }
 
@@ -214,8 +207,11 @@
   // line.
   static Counter* counter = GetCounter("Instruction");
 
-  fprintf(output_stream_, "# %c%c @ %" PRId64 "\n", marker & 0xff,
-          (marker >> 8) & 0xff, counter->count());
+  fprintf(output_stream_,
+          "# %c%c @ %" PRId64 "\n",
+          marker & 0xff,
+          (marker >> 8) & 0xff,
+          counter->count());
 }
 
 
@@ -231,7 +227,7 @@
   // A Counter by that name does not exist: print an error message to stderr
   // and the output file, and exit.
   static const char* error_message =
-    "# Error: Unknown counter \"%s\". Exiting.\n";
+      "# Error: Unknown counter \"%s\". Exiting.\n";
   fprintf(stderr, error_message, name);
   fprintf(output_stream_, error_message, name);
   exit(1);
@@ -426,10 +422,14 @@
     case STRH_w:
     case STR_w:
       VIXL_FALLTHROUGH();
-    case STR_x:     store_int_counter->Increment(); break;
+    case STR_x:
+      store_int_counter->Increment();
+      break;
     case STR_s:
       VIXL_FALLTHROUGH();
-    case STR_d:     store_fp_counter->Increment(); break;
+    case STR_d:
+      store_fp_counter->Increment();
+      break;
     case LDRB_w:
     case LDRH_w:
     case LDR_w:
@@ -439,10 +439,14 @@
     case LDRSW_x:
     case LDRSB_w:
       VIXL_FALLTHROUGH();
-    case LDRSH_w:   load_int_counter->Increment(); break;
+    case LDRSH_w:
+      load_int_counter->Increment();
+      break;
     case LDR_s:
       VIXL_FALLTHROUGH();
-    case LDR_d:     load_fp_counter->Increment(); break;
+    case LDR_d:
+      load_fp_counter->Increment();
+      break;
   }
 }
 
diff --git a/src/vixl/a64/instrument-a64.h b/src/vixl/a64/instrument-a64.h
index e1da5b3..b6bbccb 100644
--- a/src/vixl/a64/instrument-a64.h
+++ b/src/vixl/a64/instrument-a64.h
@@ -39,10 +39,7 @@
 const uint64_t kDefaultInstrumentationSamplingPeriod = 1 << 22;
 
 
-enum InstrumentState {
-  InstrumentStateDisable = 0,
-  InstrumentStateEnable = 1
-};
+enum InstrumentState { InstrumentStateDisable = 0, InstrumentStateEnable = 1 };
 
 
 enum CounterType {
@@ -71,19 +68,20 @@
 };
 
 
-class Instrument: public DecoderVisitor {
+class Instrument : public DecoderVisitor {
  public:
-  explicit Instrument(const char* datafile = NULL,
-    uint64_t sample_period = kDefaultInstrumentationSamplingPeriod);
+  explicit Instrument(
+      const char* datafile = NULL,
+      uint64_t sample_period = kDefaultInstrumentationSamplingPeriod);
   ~Instrument();
 
   void Enable();
   void Disable();
 
-  // Declare all Visitor functions.
-  #define DECLARE(A) void Visit##A(const Instruction* instr);
+// Declare all Visitor functions.
+#define DECLARE(A) void Visit##A(const Instruction* instr);
   VISITOR_LIST(DECLARE)
-  #undef DECLARE
+#undef DECLARE
 
  private:
   void Update();
@@ -98,7 +96,7 @@
 
   std::list<Counter*> counters_;
 
-  FILE *output_stream_;
+  FILE* output_stream_;
 
   // Counter information is dumped every sample_period_ instructions decoded.
   // For a sample_period_ = 0 a final counter value is only produced when the
diff --git a/src/vixl/a64/logic-a64.cc b/src/vixl/a64/logic-a64.cc
index 3bccb6e..d8d588a 100644
--- a/src/vixl/a64/logic-a64.cc
+++ b/src/vixl/a64/logic-a64.cc
@@ -31,18 +31,22 @@
 
 namespace vixl {
 
-template<> double Simulator::FPDefaultNaN<double>() {
+template <>
+double Simulator::FPDefaultNaN<double>() {
   return kFP64DefaultNaN;
 }
 
 
-template<> float Simulator::FPDefaultNaN<float>() {
+template <>
+float Simulator::FPDefaultNaN<float>() {
   return kFP32DefaultNaN;
 }
 
 // See FPRound for a description of this function.
-static inline double FPRoundToDouble(int64_t sign, int64_t exponent,
-                                     uint64_t mantissa, FPRounding round_mode) {
+static inline double FPRoundToDouble(int64_t sign,
+                                     int64_t exponent,
+                                     uint64_t mantissa,
+                                     FPRounding round_mode) {
   int64_t bits =
       FPRound<int64_t, kDoubleExponentBits, kDoubleMantissaBits>(sign,
                                                                  exponent,
@@ -53,8 +57,10 @@
 
 
 // See FPRound for a description of this function.
-static inline float FPRoundToFloat(int64_t sign, int64_t exponent,
-                                   uint64_t mantissa, FPRounding round_mode) {
+static inline float FPRoundToFloat(int64_t sign,
+                                   int64_t exponent,
+                                   uint64_t mantissa,
+                                   FPRounding round_mode) {
   int32_t bits =
       FPRound<int32_t, kFloatExponentBits, kFloatMantissaBits>(sign,
                                                                exponent,
@@ -69,8 +75,9 @@
                                        int64_t exponent,
                                        uint64_t mantissa,
                                        FPRounding round_mode) {
-  return FPRound<float16, kFloat16ExponentBits, kFloat16MantissaBits>(
-      sign, exponent, mantissa, round_mode);
+  return FPRound<float16,
+                 kFloat16ExponentBits,
+                 kFloat16MantissaBits>(sign, exponent, mantissa, round_mode);
 }
 
 
@@ -144,7 +151,7 @@
       uint64_t sign = raw >> 31;
       uint64_t exponent = (1 << 11) - 1;
       uint64_t payload = unsigned_bitextract_64(21, 0, raw);
-      payload <<= (52 - 23);  // The unused low-order bits should be 0.
+      payload <<= (52 - 23);           // The unused low-order bits should be 0.
       payload |= (UINT64_C(1) << 51);  // Force a quiet NaN.
 
       return rawbits_to_double((sign << 63) | (exponent << 52) | payload);
@@ -168,11 +175,12 @@
 
 float Simulator::FPToFloat(float16 value) {
   uint32_t sign = value >> 15;
-  uint32_t exponent = unsigned_bitextract_32(
-      kFloat16MantissaBits + kFloat16ExponentBits - 1, kFloat16MantissaBits,
-      value);
-  uint32_t mantissa = unsigned_bitextract_32(
-      kFloat16MantissaBits - 1, 0, value);
+  uint32_t exponent =
+      unsigned_bitextract_32(kFloat16MantissaBits + kFloat16ExponentBits - 1,
+                             kFloat16MantissaBits,
+                             value);
+  uint32_t mantissa =
+      unsigned_bitextract_32(kFloat16MantissaBits - 1, 0, value);
 
   switch (float16classify(value)) {
     case FP_ZERO:
@@ -221,10 +229,10 @@
       exponent += (-15 + 127);
       break;
 
-    default: VIXL_UNREACHABLE();
+    default:
+      VIXL_UNREACHABLE();
   }
-  return rawbits_to_float((sign << 31) |
-                          (exponent << kFloatMantissaBits) |
+  return rawbits_to_float((sign << 31) | (exponent << kFloatMantissaBits) |
                           mantissa);
 }
 
@@ -250,8 +258,8 @@
       //  - The sign is propagated.
       //  - The payload (mantissa) is transferred as much as possible, except
       //    that the top bit is forced to '1', making the result a quiet NaN.
-      float16 result = (sign == 0) ? kFP16PositiveInfinity
-                                   : kFP16NegativeInfinity;
+      float16 result =
+          (sign == 0) ? kFP16PositiveInfinity : kFP16NegativeInfinity;
       result |= mantissa >> (kFloatMantissaBits - kFloat16MantissaBits);
       result |= (1 << 9);  // Force a quiet NaN;
       return result;
@@ -300,8 +308,8 @@
       //  - The sign is propagated.
       //  - The payload (mantissa) is transferred as much as possible, except
       //    that the top bit is forced to '1', making the result a quiet NaN.
-      float16 result = (sign == 0) ? kFP16PositiveInfinity
-                                   : kFP16NegativeInfinity;
+      float16 result =
+          (sign == 0) ? kFP16PositiveInfinity : kFP16NegativeInfinity;
       result |= mantissa >> (kDoubleMantissaBits - kFloat16MantissaBits);
       result |= (1 << 9);  // Force a quiet NaN;
       return result;
@@ -351,7 +359,7 @@
       uint32_t exponent = (1 << 8) - 1;
       uint32_t payload =
           static_cast<uint32_t>(unsigned_bitextract_64(50, 52 - 23, raw));
-      payload |= (1 << 22);   // Force a quiet NaN.
+      payload |= (1 << 22);  // Force a quiet NaN.
 
       return rawbits_to_float((sign << 31) | (exponent << 23) | payload);
     }
@@ -387,9 +395,7 @@
 }
 
 
-void Simulator::ld1(VectorFormat vform,
-                    LogicVRegister dst,
-                    uint64_t addr) {
+void Simulator::ld1(VectorFormat vform, LogicVRegister dst, uint64_t addr) {
   dst.ClearForWrite(vform);
   for (int i = 0; i < LaneCountFromFormat(vform); i++) {
     dst.ReadUintFromMem(vform, i, addr);
@@ -406,9 +412,7 @@
 }
 
 
-void Simulator::ld1r(VectorFormat vform,
-                     LogicVRegister dst,
-                     uint64_t addr) {
+void Simulator::ld1r(VectorFormat vform, LogicVRegister dst, uint64_t addr) {
   dst.ClearForWrite(vform);
   for (int i = 0; i < LaneCountFromFormat(vform); i++) {
     dst.ReadUintFromMem(vform, i, addr);
@@ -587,9 +591,7 @@
 }
 
 
-void Simulator::st1(VectorFormat vform,
-                    LogicVRegister src,
-                    uint64_t addr) {
+void Simulator::st1(VectorFormat vform, LogicVRegister src, uint64_t addr) {
   for (int i = 0; i < LaneCountFromFormat(vform); i++) {
     src.WriteUintToMem(vform, i, addr);
     addr += LaneSizeInBytesFromFormat(vform);
@@ -708,20 +710,36 @@
                               Condition cond) {
   dst.ClearForWrite(vform);
   for (int i = 0; i < LaneCountFromFormat(vform); i++) {
-    int64_t  sa = src1.Int(vform, i);
-    int64_t  sb = src2.Int(vform, i);
+    int64_t sa = src1.Int(vform, i);
+    int64_t sb = src2.Int(vform, i);
     uint64_t ua = src1.Uint(vform, i);
     uint64_t ub = src2.Uint(vform, i);
     bool result = false;
     switch (cond) {
-      case eq: result = (ua == ub); break;
-      case ge: result = (sa >= sb); break;
-      case gt: result = (sa > sb) ; break;
-      case hi: result = (ua > ub) ; break;
-      case hs: result = (ua >= ub); break;
-      case lt: result = (sa < sb) ; break;
-      case le: result = (sa <= sb); break;
-      default: VIXL_UNREACHABLE(); break;
+      case eq:
+        result = (ua == ub);
+        break;
+      case ge:
+        result = (sa >= sb);
+        break;
+      case gt:
+        result = (sa > sb);
+        break;
+      case hi:
+        result = (ua > ub);
+        break;
+      case hs:
+        result = (ua >= ub);
+        break;
+      case lt:
+        result = (sa < sb);
+        break;
+      case le:
+        result = (sa <= sb);
+        break;
+      default:
+        VIXL_UNREACHABLE();
+        break;
     }
     dst.SetUint(vform, i, result ? MaxUintFromFormat(vform) : 0);
   }
@@ -871,19 +889,19 @@
                                 int index) {
   SimVRegister temp;
   VectorFormat indexform =
-               VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform));
+      VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform));
   return smull(vform, dst, src1, dup_element(indexform, temp, src2, index));
 }
 
 
 LogicVRegister Simulator::smull2(VectorFormat vform,
-                                LogicVRegister dst,
-                                const LogicVRegister& src1,
-                                const LogicVRegister& src2,
-                                int index) {
+                                 LogicVRegister dst,
+                                 const LogicVRegister& src1,
+                                 const LogicVRegister& src2,
+                                 int index) {
   SimVRegister temp;
   VectorFormat indexform =
-               VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform));
+      VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform));
   return smull2(vform, dst, src1, dup_element(indexform, temp, src2, index));
 }
 
@@ -895,19 +913,19 @@
                                 int index) {
   SimVRegister temp;
   VectorFormat indexform =
-               VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform));
+      VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform));
   return umull(vform, dst, src1, dup_element(indexform, temp, src2, index));
 }
 
 
 LogicVRegister Simulator::umull2(VectorFormat vform,
-                                LogicVRegister dst,
-                                const LogicVRegister& src1,
-                                const LogicVRegister& src2,
-                                int index) {
+                                 LogicVRegister dst,
+                                 const LogicVRegister& src1,
+                                 const LogicVRegister& src2,
+                                 int index) {
   SimVRegister temp;
   VectorFormat indexform =
-               VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform));
+      VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform));
   return umull2(vform, dst, src1, dup_element(indexform, temp, src2, index));
 }
 
@@ -919,19 +937,19 @@
                                 int index) {
   SimVRegister temp;
   VectorFormat indexform =
-               VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform));
+      VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform));
   return smlal(vform, dst, src1, dup_element(indexform, temp, src2, index));
 }
 
 
 LogicVRegister Simulator::smlal2(VectorFormat vform,
-                                LogicVRegister dst,
-                                const LogicVRegister& src1,
-                                const LogicVRegister& src2,
-                                int index) {
+                                 LogicVRegister dst,
+                                 const LogicVRegister& src1,
+                                 const LogicVRegister& src2,
+                                 int index) {
   SimVRegister temp;
   VectorFormat indexform =
-               VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform));
+      VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform));
   return smlal2(vform, dst, src1, dup_element(indexform, temp, src2, index));
 }
 
@@ -943,19 +961,19 @@
                                 int index) {
   SimVRegister temp;
   VectorFormat indexform =
-               VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform));
+      VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform));
   return umlal(vform, dst, src1, dup_element(indexform, temp, src2, index));
 }
 
 
 LogicVRegister Simulator::umlal2(VectorFormat vform,
-                                LogicVRegister dst,
-                                const LogicVRegister& src1,
-                                const LogicVRegister& src2,
-                                int index) {
+                                 LogicVRegister dst,
+                                 const LogicVRegister& src1,
+                                 const LogicVRegister& src2,
+                                 int index) {
   SimVRegister temp;
   VectorFormat indexform =
-               VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform));
+      VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform));
   return umlal2(vform, dst, src1, dup_element(indexform, temp, src2, index));
 }
 
@@ -967,19 +985,19 @@
                                 int index) {
   SimVRegister temp;
   VectorFormat indexform =
-               VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform));
+      VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform));
   return smlsl(vform, dst, src1, dup_element(indexform, temp, src2, index));
 }
 
 
 LogicVRegister Simulator::smlsl2(VectorFormat vform,
-                                LogicVRegister dst,
-                                const LogicVRegister& src1,
-                                const LogicVRegister& src2,
-                                int index) {
+                                 LogicVRegister dst,
+                                 const LogicVRegister& src1,
+                                 const LogicVRegister& src2,
+                                 int index) {
   SimVRegister temp;
   VectorFormat indexform =
-               VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform));
+      VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform));
   return smlsl2(vform, dst, src1, dup_element(indexform, temp, src2, index));
 }
 
@@ -991,19 +1009,19 @@
                                 int index) {
   SimVRegister temp;
   VectorFormat indexform =
-               VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform));
+      VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform));
   return umlsl(vform, dst, src1, dup_element(indexform, temp, src2, index));
 }
 
 
 LogicVRegister Simulator::umlsl2(VectorFormat vform,
-                                LogicVRegister dst,
-                                const LogicVRegister& src1,
-                                const LogicVRegister& src2,
-                                int index) {
+                                 LogicVRegister dst,
+                                 const LogicVRegister& src1,
+                                 const LogicVRegister& src2,
+                                 int index) {
   SimVRegister temp;
   VectorFormat indexform =
-               VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform));
+      VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform));
   return umlsl2(vform, dst, src1, dup_element(indexform, temp, src2, index));
 }
 
@@ -1021,10 +1039,10 @@
 
 
 LogicVRegister Simulator::sqdmull2(VectorFormat vform,
-                                  LogicVRegister dst,
-                                  const LogicVRegister& src1,
-                                  const LogicVRegister& src2,
-                                  int index) {
+                                   LogicVRegister dst,
+                                   const LogicVRegister& src1,
+                                   const LogicVRegister& src2,
+                                   int index) {
   SimVRegister temp;
   VectorFormat indexform =
       VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform));
@@ -1045,10 +1063,10 @@
 
 
 LogicVRegister Simulator::sqdmlal2(VectorFormat vform,
-                                  LogicVRegister dst,
-                                  const LogicVRegister& src1,
-                                  const LogicVRegister& src2,
-                                  int index) {
+                                   LogicVRegister dst,
+                                   const LogicVRegister& src1,
+                                   const LogicVRegister& src2,
+                                   int index) {
   SimVRegister temp;
   VectorFormat indexform =
       VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform));
@@ -1069,10 +1087,10 @@
 
 
 LogicVRegister Simulator::sqdmlsl2(VectorFormat vform,
-                                  LogicVRegister dst,
-                                  const LogicVRegister& src1,
-                                  const LogicVRegister& src2,
-                                  int index) {
+                                   LogicVRegister dst,
+                                   const LogicVRegister& src1,
+                                   const LogicVRegister& src2,
+                                   int index) {
   SimVRegister temp;
   VectorFormat indexform =
       VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform));
@@ -1092,10 +1110,10 @@
 
 
 LogicVRegister Simulator::sqrdmulh(VectorFormat vform,
-                                  LogicVRegister dst,
-                                  const LogicVRegister& src1,
-                                  const LogicVRegister& src2,
-                                  int index) {
+                                   LogicVRegister dst,
+                                   const LogicVRegister& src1,
+                                   const LogicVRegister& src2,
+                                   int index) {
   SimVRegister temp;
   VectorFormat indexform = VectorFormatFillQ(vform);
   return sqrdmulh(vform, dst, src1, dup_element(indexform, temp, src2, index));
@@ -1120,7 +1138,8 @@
                                const LogicVRegister& src2) {
   dst.ClearForWrite(vform);
   for (int i = 0; i < LaneCountFromFormat(vform); i++) {
-    dst.SetUint(vform, i,
+    dst.SetUint(vform,
+                i,
                 PolynomialMult(src1.Uint(vform, i), src2.Uint(vform, i)));
   }
   return dst;
@@ -1128,29 +1147,33 @@
 
 
 LogicVRegister Simulator::pmull(VectorFormat vform,
-                               LogicVRegister dst,
-                               const LogicVRegister& src1,
-                               const LogicVRegister& src2) {
+                                LogicVRegister dst,
+                                const LogicVRegister& src1,
+                                const LogicVRegister& src2) {
   VectorFormat vform_src = VectorFormatHalfWidth(vform);
   dst.ClearForWrite(vform);
   for (int i = 0; i < LaneCountFromFormat(vform); i++) {
-    dst.SetUint(vform, i, PolynomialMult(src1.Uint(vform_src, i),
-                                         src2.Uint(vform_src, i)));
+    dst.SetUint(vform,
+                i,
+                PolynomialMult(src1.Uint(vform_src, i),
+                               src2.Uint(vform_src, i)));
   }
   return dst;
 }
 
 
 LogicVRegister Simulator::pmull2(VectorFormat vform,
-                                LogicVRegister dst,
-                                const LogicVRegister& src1,
-                                const LogicVRegister& src2) {
+                                 LogicVRegister dst,
+                                 const LogicVRegister& src1,
+                                 const LogicVRegister& src2) {
   VectorFormat vform_src = VectorFormatHalfWidthDoubleLanes(vform);
   dst.ClearForWrite(vform);
   int lane_count = LaneCountFromFormat(vform);
   for (int i = 0; i < lane_count; i++) {
-    dst.SetUint(vform, i, PolynomialMult(src1.Uint(vform_src, lane_count + i),
-                                         src2.Uint(vform_src, lane_count + i)));
+    dst.SetUint(vform,
+                i,
+                PolynomialMult(src1.Uint(vform_src, lane_count + i),
+                               src2.Uint(vform_src, lane_count + i)));
   }
   return dst;
 }
@@ -1402,8 +1425,8 @@
 LogicVRegister Simulator::addv(VectorFormat vform,
                                LogicVRegister dst,
                                const LogicVRegister& src) {
-  VectorFormat vform_dst
-    = ScalarFormatFromLaneSize(LaneSizeInBitsFromFormat(vform));
+  VectorFormat vform_dst =
+      ScalarFormatFromLaneSize(LaneSizeInBitsFromFormat(vform));
 
 
   int64_t dst_val = 0;
@@ -1420,8 +1443,8 @@
 LogicVRegister Simulator::saddlv(VectorFormat vform,
                                  LogicVRegister dst,
                                  const LogicVRegister& src) {
-  VectorFormat vform_dst
-    = ScalarFormatFromLaneSize(LaneSizeInBitsFromFormat(vform) * 2);
+  VectorFormat vform_dst =
+      ScalarFormatFromLaneSize(LaneSizeInBitsFromFormat(vform) * 2);
 
   int64_t dst_val = 0;
   for (int i = 0; i < LaneCountFromFormat(vform); i++) {
@@ -1437,8 +1460,8 @@
 LogicVRegister Simulator::uaddlv(VectorFormat vform,
                                  LogicVRegister dst,
                                  const LogicVRegister& src) {
-  VectorFormat vform_dst
-    = ScalarFormatFromLaneSize(LaneSizeInBitsFromFormat(vform) * 2);
+  VectorFormat vform_dst =
+      ScalarFormatFromLaneSize(LaneSizeInBitsFromFormat(vform) * 2);
 
   uint64_t dst_val = 0;
   for (int i = 0; i < LaneCountFromFormat(vform); i++) {
@@ -1819,7 +1842,7 @@
                               LogicVRegister dst,
                               const LogicVRegister& src) {
   uint64_t result[16];
-  int laneSizeInBits  = LaneSizeInBitsFromFormat(vform);
+  int laneSizeInBits = LaneSizeInBitsFromFormat(vform);
   int laneCount = LaneCountFromFormat(vform);
   for (int i = 0; i < laneCount; i++) {
     result[i] = CountLeadingSignBits(src.Int(vform, i), laneSizeInBits);
@@ -1837,7 +1860,7 @@
                               LogicVRegister dst,
                               const LogicVRegister& src) {
   uint64_t result[16];
-  int laneSizeInBits  = LaneSizeInBitsFromFormat(vform);
+  int laneSizeInBits = LaneSizeInBitsFromFormat(vform);
   int laneCount = LaneCountFromFormat(vform);
   for (int i = 0; i < laneCount; i++) {
     result[i] = CountLeadingZeros(src.Uint(vform, i), laneSizeInBits);
@@ -1855,7 +1878,7 @@
                               LogicVRegister dst,
                               const LogicVRegister& src) {
   uint64_t result[16];
-  int laneSizeInBits  = LaneSizeInBitsFromFormat(vform);
+  int laneSizeInBits = LaneSizeInBitsFromFormat(vform);
   int laneCount = LaneCountFromFormat(vform);
   for (int i = 0; i < laneCount; i++) {
     uint64_t value = src.Uint(vform, i);
@@ -1884,8 +1907,7 @@
     int64_t lj_src_val = src1.IntLeftJustified(vform, i);
 
     // Set signed saturation state.
-    if ((shift_val > CountLeadingSignBits(lj_src_val)) &&
-        (lj_src_val != 0)) {
+    if ((shift_val > CountLeadingSignBits(lj_src_val)) && (lj_src_val != 0)) {
       dst.SetSignedSat(i, lj_src_val >= 0);
     }
 
@@ -1980,9 +2002,9 @@
                                  const LogicVRegister& src) {
   dst.ClearForWrite(vform);
   for (int i = 0; i < LaneCountFromFormat(vform); i++) {
-    int64_t  sa = dst.IntLeftJustified(vform, i);
+    int64_t sa = dst.IntLeftJustified(vform, i);
     uint64_t ub = src.UintLeftJustified(vform, i);
-    int64_t  sr = sa + ub;
+    int64_t sr = sa + ub;
 
     if (sr < sa) {  // Test for signed positive saturation.
       dst.SetInt(vform, i, MaxIntFromFormat(vform));
@@ -1999,14 +2021,14 @@
                                  const LogicVRegister& src) {
   dst.ClearForWrite(vform);
   for (int i = 0; i < LaneCountFromFormat(vform); i++) {
-    uint64_t  ua = dst.UintLeftJustified(vform, i);
-    int64_t   sb = src.IntLeftJustified(vform, i);
-    uint64_t  ur = ua + sb;
+    uint64_t ua = dst.UintLeftJustified(vform, i);
+    int64_t sb = src.IntLeftJustified(vform, i);
+    uint64_t ur = ua + sb;
 
     if ((sb > 0) && (ur <= ua)) {
       dst.SetUint(vform, i, MaxUintFromFormat(vform));  // Positive saturation.
     } else if ((sb < 0) && (ur >= ua)) {
-      dst.SetUint(vform, i, 0);                         // Negative saturation.
+      dst.SetUint(vform, i, 0);  // Negative saturation.
     } else {
       dst.SetUint(vform, i, dst.Uint(vform, i) + src.Int(vform, i));
     }
@@ -2042,20 +2064,48 @@
                                         bool srcIsSigned) {
   bool upperhalf = false;
   VectorFormat srcform = kFormatUndefined;
-  int64_t  ssrc[8];
+  int64_t ssrc[8];
   uint64_t usrc[8];
 
   switch (dstform) {
-    case kFormat8B : upperhalf = false; srcform = kFormat8H; break;
-    case kFormat16B: upperhalf = true;  srcform = kFormat8H; break;
-    case kFormat4H : upperhalf = false; srcform = kFormat4S; break;
-    case kFormat8H : upperhalf = true;  srcform = kFormat4S; break;
-    case kFormat2S : upperhalf = false; srcform = kFormat2D; break;
-    case kFormat4S : upperhalf = true;  srcform = kFormat2D; break;
-    case kFormatB  : upperhalf = false; srcform = kFormatH;  break;
-    case kFormatH  : upperhalf = false; srcform = kFormatS;  break;
-    case kFormatS  : upperhalf = false; srcform = kFormatD;  break;
-    default:VIXL_UNIMPLEMENTED();
+    case kFormat8B:
+      upperhalf = false;
+      srcform = kFormat8H;
+      break;
+    case kFormat16B:
+      upperhalf = true;
+      srcform = kFormat8H;
+      break;
+    case kFormat4H:
+      upperhalf = false;
+      srcform = kFormat4S;
+      break;
+    case kFormat8H:
+      upperhalf = true;
+      srcform = kFormat4S;
+      break;
+    case kFormat2S:
+      upperhalf = false;
+      srcform = kFormat2D;
+      break;
+    case kFormat4S:
+      upperhalf = true;
+      srcform = kFormat2D;
+      break;
+    case kFormatB:
+      upperhalf = false;
+      srcform = kFormatH;
+      break;
+    case kFormatH:
+      upperhalf = false;
+      srcform = kFormatS;
+      break;
+    case kFormatS:
+      upperhalf = false;
+      srcform = kFormatD;
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
   }
 
   for (int i = 0; i < LaneCountFromFormat(srcform); i++) {
@@ -2198,7 +2248,7 @@
                                const LogicVRegister& src) {
   uint64_t result[16];
   int laneCount = LaneCountFromFormat(vform);
-  int laneSizeInBits  = LaneSizeInBitsFromFormat(vform);
+  int laneSizeInBits = LaneSizeInBitsFromFormat(vform);
   uint64_t reversed_value;
   uint64_t value;
   for (int i = 0; i < laneCount; i++) {
@@ -2226,7 +2276,7 @@
   uint64_t result[16];
   int laneCount = LaneCountFromFormat(vform);
   int laneSize = LaneSizeInBytesFromFormat(vform);
-  int lanesPerLoop =  revSize / laneSize;
+  int lanesPerLoop = revSize / laneSize;
   for (int i = 0; i < laneCount; i += lanesPerLoop) {
     for (int j = 0; j < lanesPerLoop; j++) {
       result[i + lanesPerLoop - 1 - j] = src.Uint(vform, i + j);
@@ -2262,13 +2312,13 @@
 
 
 LogicVRegister Simulator::addlp(VectorFormat vform,
-                                 LogicVRegister dst,
-                                 const LogicVRegister& src,
-                                 bool is_signed,
-                                 bool do_accumulate) {
+                                LogicVRegister dst,
+                                const LogicVRegister& src,
+                                bool is_signed,
+                                bool do_accumulate) {
   VectorFormat vformsrc = VectorFormatHalfWidthDoubleLanes(vform);
 
-  int64_t  sr[16];
+  int64_t sr[16];
   uint64_t ur[16];
 
   int laneCount = LaneCountFromFormat(vform);
@@ -2544,8 +2594,8 @@
                               LogicVRegister dst,
                               const LogicVRegister& tab,
                               const LogicVRegister& ind) {
-    movi(vform, dst, 0);
-    return tbx(vform, dst, tab, ind);
+  movi(vform, dst, 0);
+  return tbx(vform, dst, tab, ind);
 }
 
 
@@ -2554,8 +2604,8 @@
                               const LogicVRegister& tab,
                               const LogicVRegister& tab2,
                               const LogicVRegister& ind) {
-    movi(vform, dst, 0);
-    return tbx(vform, dst, tab, tab2, ind);
+  movi(vform, dst, 0);
+  return tbx(vform, dst, tab, tab2, ind);
 }
 
 
@@ -2565,8 +2615,8 @@
                               const LogicVRegister& tab2,
                               const LogicVRegister& tab3,
                               const LogicVRegister& ind) {
-    movi(vform, dst, 0);
-    return tbx(vform, dst, tab, tab2, tab3, ind);
+  movi(vform, dst, 0);
+  return tbx(vform, dst, tab, tab2, tab3, ind);
 }
 
 
@@ -2577,8 +2627,8 @@
                               const LogicVRegister& tab3,
                               const LogicVRegister& tab4,
                               const LogicVRegister& ind) {
-    movi(vform, dst, 0);
-    return tbx(vform, dst, tab, tab2, tab3, tab4, ind);
+  movi(vform, dst, 0);
+  return tbx(vform, dst, tab, tab2, tab3, tab4, ind);
 }
 
 
@@ -2590,7 +2640,9 @@
   for (int i = 0; i < LaneCountFromFormat(vform); i++) {
     uint64_t j = ind.Uint(vform, i);
     switch (j >> 4) {
-      case 0: dst.SetUint(vform, i, tab.Uint(kFormat16B, j & 15)); break;
+      case 0:
+        dst.SetUint(vform, i, tab.Uint(kFormat16B, j & 15));
+        break;
     }
   }
   return dst;
@@ -2606,8 +2658,12 @@
   for (int i = 0; i < LaneCountFromFormat(vform); i++) {
     uint64_t j = ind.Uint(vform, i);
     switch (j >> 4) {
-      case 0: dst.SetUint(vform, i, tab.Uint(kFormat16B, j & 15)); break;
-      case 1: dst.SetUint(vform, i, tab2.Uint(kFormat16B, j & 15)); break;
+      case 0:
+        dst.SetUint(vform, i, tab.Uint(kFormat16B, j & 15));
+        break;
+      case 1:
+        dst.SetUint(vform, i, tab2.Uint(kFormat16B, j & 15));
+        break;
     }
   }
   return dst;
@@ -2624,9 +2680,15 @@
   for (int i = 0; i < LaneCountFromFormat(vform); i++) {
     uint64_t j = ind.Uint(vform, i);
     switch (j >> 4) {
-      case 0: dst.SetUint(vform, i, tab.Uint(kFormat16B, j & 15)); break;
-      case 1: dst.SetUint(vform, i, tab2.Uint(kFormat16B, j & 15)); break;
-      case 2: dst.SetUint(vform, i, tab3.Uint(kFormat16B, j & 15)); break;
+      case 0:
+        dst.SetUint(vform, i, tab.Uint(kFormat16B, j & 15));
+        break;
+      case 1:
+        dst.SetUint(vform, i, tab2.Uint(kFormat16B, j & 15));
+        break;
+      case 2:
+        dst.SetUint(vform, i, tab3.Uint(kFormat16B, j & 15));
+        break;
     }
   }
   return dst;
@@ -2644,10 +2706,18 @@
   for (int i = 0; i < LaneCountFromFormat(vform); i++) {
     uint64_t j = ind.Uint(vform, i);
     switch (j >> 4) {
-      case 0: dst.SetUint(vform, i, tab.Uint(kFormat16B, j & 15)); break;
-      case 1: dst.SetUint(vform, i, tab2.Uint(kFormat16B, j & 15)); break;
-      case 2: dst.SetUint(vform, i, tab3.Uint(kFormat16B, j & 15)); break;
-      case 3: dst.SetUint(vform, i, tab4.Uint(kFormat16B, j & 15)); break;
+      case 0:
+        dst.SetUint(vform, i, tab.Uint(kFormat16B, j & 15));
+        break;
+      case 1:
+        dst.SetUint(vform, i, tab2.Uint(kFormat16B, j & 15));
+        break;
+      case 2:
+        dst.SetUint(vform, i, tab3.Uint(kFormat16B, j & 15));
+        break;
+      case 3:
+        dst.SetUint(vform, i, tab4.Uint(kFormat16B, j & 15));
+        break;
     }
   }
   return dst;
@@ -3217,9 +3287,9 @@
 
 
 LogicVRegister Simulator::sqdmlal2(VectorFormat vform,
-                                  LogicVRegister dst,
-                                  const LogicVRegister& src1,
-                                  const LogicVRegister& src2) {
+                                   LogicVRegister dst,
+                                   const LogicVRegister& src1,
+                                   const LogicVRegister& src2) {
   SimVRegister temp;
   LogicVRegister product = sqdmull2(vform, temp, src1, src2);
   return add(vform, dst, dst, product).SignedSaturate(vform);
@@ -3237,9 +3307,9 @@
 
 
 LogicVRegister Simulator::sqdmlsl2(VectorFormat vform,
-                                  LogicVRegister dst,
-                                  const LogicVRegister& src1,
-                                  const LogicVRegister& src2) {
+                                   LogicVRegister dst,
+                                   const LogicVRegister& src1,
+                                   const LogicVRegister& src2) {
   SimVRegister temp;
   LogicVRegister product = sqdmull2(vform, temp, src1, src2);
   return sub(vform, dst, dst, product).SignedSaturate(vform);
@@ -3257,9 +3327,9 @@
 
 
 LogicVRegister Simulator::sqdmull2(VectorFormat vform,
-                                  LogicVRegister dst,
-                                  const LogicVRegister& src1,
-                                  const LogicVRegister& src2) {
+                                   LogicVRegister dst,
+                                   const LogicVRegister& src1,
+                                   const LogicVRegister& src2) {
   SimVRegister temp;
   LogicVRegister product = smull2(vform, temp, src1, src2);
   return add(vform, dst, product, product).SignedSaturate(vform);
@@ -3400,7 +3470,7 @@
   int laneCount = LaneCountFromFormat(vform);
   int pairs = laneCount / 2;
   for (int i = 0; i < pairs; ++i) {
-    result[2 * i]       = src1.Uint(vform, 2 * i);
+    result[2 * i] = src1.Uint(vform, 2 * i);
     result[(2 * i) + 1] = src2.Uint(vform, 2 * i);
   }
 
@@ -3420,7 +3490,7 @@
   int laneCount = LaneCountFromFormat(vform);
   int pairs = laneCount / 2;
   for (int i = 0; i < pairs; ++i) {
-    result[2 * i]       = src1.Uint(vform, (2 * i) + 1);
+    result[2 * i] = src1.Uint(vform, (2 * i) + 1);
     result[(2 * i) + 1] = src2.Uint(vform, (2 * i) + 1);
   }
 
@@ -3440,7 +3510,7 @@
   int laneCount = LaneCountFromFormat(vform);
   int pairs = laneCount / 2;
   for (int i = 0; i < pairs; ++i) {
-    result[2 * i]       = src1.Uint(vform, i);
+    result[2 * i] = src1.Uint(vform, i);
     result[(2 * i) + 1] = src2.Uint(vform, i);
   }
 
@@ -3460,7 +3530,7 @@
   int laneCount = LaneCountFromFormat(vform);
   int pairs = laneCount / 2;
   for (int i = 0; i < pairs; ++i) {
-    result[2 * i]       = src1.Uint(vform, pairs + i);
+    result[2 * i] = src1.Uint(vform, pairs + i);
     result[(2 * i) + 1] = src2.Uint(vform, pairs + i);
   }
 
@@ -3479,7 +3549,7 @@
   uint64_t result[32];
   int laneCount = LaneCountFromFormat(vform);
   for (int i = 0; i < laneCount; ++i) {
-    result[i]             = src1.Uint(vform, i);
+    result[i] = src1.Uint(vform, i);
     result[laneCount + i] = src2.Uint(vform, i);
   }
 
@@ -3498,13 +3568,13 @@
   uint64_t result[32];
   int laneCount = LaneCountFromFormat(vform);
   for (int i = 0; i < laneCount; ++i) {
-    result[i]             = src1.Uint(vform, i);
+    result[i] = src1.Uint(vform, i);
     result[laneCount + i] = src2.Uint(vform, i);
   }
 
   dst.ClearForWrite(vform);
   for (int i = 0; i < laneCount; ++i) {
-    dst.SetUint(vform, i, result[ (2 * i) + 1]);
+    dst.SetUint(vform, i, result[(2 * i) + 1]);
   }
   return dst;
 }
@@ -3558,7 +3628,7 @@
 }
 
 
-template<typename T>
+template <typename T>
 T Simulator::FPMulx(T op1, T op2) {
   if ((std::isinf(op1) && (op2 == 0.0)) || (std::isinf(op2) && (op1 == 0.0))) {
     // inf * 0.0 returns +/-2.0.
@@ -3569,7 +3639,7 @@
 }
 
 
-template<typename T>
+template <typename T>
 T Simulator::FPMulAdd(T a, T op1, T op2) {
   T result = FPProcessNaNs3(a, op1, op2);
 
@@ -3652,8 +3722,7 @@
   T result = FPProcessNaNs(a, b);
   if (std::isnan(result)) return result;
 
-  if ((a == 0.0) && (b == 0.0) &&
-      (copysign(1.0, a) != copysign(1.0, b))) {
+  if ((a == 0.0) && (b == 0.0) && (copysign(1.0, a) != copysign(1.0, b))) {
     // a and b are zero, and the sign differs: return +0.0.
     return 0.0;
   } else {
@@ -3680,8 +3749,7 @@
   T result = FPProcessNaNs(a, b);
   if (std::isnan(result)) return result;
 
-  if ((a == 0.0) && (b == 0.0) &&
-      (copysign(1.0, a) != copysign(1.0, b))) {
+  if ((a == 0.0) && (b == 0.0) && (copysign(1.0, a) != copysign(1.0, b))) {
     // a and b are zero, and the sign differs: return -0.0.
     return -0.0;
   } else {
@@ -3706,8 +3774,8 @@
 template <typename T>
 T Simulator::FPRecipStepFused(T op1, T op2) {
   const T two = 2.0;
-  if ((std::isinf(op1) && (op2 == 0.0))
-      || ((op1 == 0.0) && (std::isinf(op2)))) {
+  if ((std::isinf(op1) && (op2 == 0.0)) ||
+      ((op1 == 0.0) && (std::isinf(op2)))) {
     return two;
   } else if (std::isinf(op1) || std::isinf(op2)) {
     // Return +inf if signs match, otherwise -inf.
@@ -3724,8 +3792,8 @@
   const T one_point_five = 1.5;
   const T two = 2.0;
 
-  if ((std::isinf(op1) && (op2 == 0.0))
-      || ((op1 == 0.0) && (std::isinf(op2)))) {
+  if ((std::isinf(op1) && (op2 == 0.0)) ||
+      ((op1 == 0.0) && (std::isinf(op2)))) {
     return one_point_five;
   } else if (std::isinf(op1) || std::isinf(op2)) {
     // Return +inf if signs match, otherwise -inf.
@@ -3778,10 +3846,10 @@
       if ((-0.5 <= value) && (value < 0.0)) {
         int_result = -0.0;
 
-      // If the error is greater than 0.5, or is equal to 0.5 and the integer
-      // result is odd, round up.
+        // If the error is greater than 0.5, or is equal to 0.5 and the integer
+        // result is odd, round up.
       } else if ((error > 0.5) ||
-          ((error == 0.5) && (std::fmod(int_result, 2) != 0))) {
+                 ((error == 0.5) && (std::fmod(int_result, 2) != 0))) {
         int_result++;
       }
       break;
@@ -3790,7 +3858,7 @@
       // If value>0 then we take floor(value)
       // otherwise, ceil(value).
       if (value < 0) {
-         int_result = ceil(value);
+        int_result = ceil(value);
       }
       break;
     }
@@ -3804,13 +3872,14 @@
       if ((-1.0 < value) && (value < 0.0)) {
         int_result = -0.0;
 
-      // If the error is non-zero, round up.
+        // If the error is non-zero, round up.
       } else if (error > 0.0) {
         int_result++;
       }
       break;
     }
-    default: VIXL_UNIMPLEMENTED();
+    default:
+      VIXL_UNIMPLEMENTED();
   }
   return int_result;
 }
@@ -3861,41 +3930,41 @@
 
 
 #define DEFINE_NEON_FP_VECTOR_OP(FN, OP, PROCNAN)                \
-template <typename T>                                            \
-LogicVRegister Simulator::FN(VectorFormat vform,                 \
-                             LogicVRegister dst,                 \
-                             const LogicVRegister& src1,         \
-                             const LogicVRegister& src2) {       \
-  dst.ClearForWrite(vform);                                      \
-  for (int i = 0; i < LaneCountFromFormat(vform); i++) {         \
-    T op1 = src1.Float<T>(i);                                    \
-    T op2 = src2.Float<T>(i);                                    \
-    T result;                                                    \
-    if (PROCNAN) {                                               \
-      result = FPProcessNaNs(op1, op2);                          \
-      if (!std::isnan(result)) {                                      \
+  template <typename T>                                          \
+  LogicVRegister Simulator::FN(VectorFormat vform,               \
+                               LogicVRegister dst,               \
+                               const LogicVRegister& src1,       \
+                               const LogicVRegister& src2) {     \
+    dst.ClearForWrite(vform);                                    \
+    for (int i = 0; i < LaneCountFromFormat(vform); i++) {       \
+      T op1 = src1.Float<T>(i);                                  \
+      T op2 = src2.Float<T>(i);                                  \
+      T result;                                                  \
+      if (PROCNAN) {                                             \
+        result = FPProcessNaNs(op1, op2);                        \
+        if (!std::isnan(result)) {                               \
+          result = OP(op1, op2);                                 \
+        }                                                        \
+      } else {                                                   \
         result = OP(op1, op2);                                   \
       }                                                          \
-    } else {                                                     \
-      result = OP(op1, op2);                                     \
+      dst.SetFloat(i, result);                                   \
     }                                                            \
-    dst.SetFloat(i, result);                                     \
+    return dst;                                                  \
   }                                                              \
-  return dst;                                                    \
-}                                                                \
                                                                  \
-LogicVRegister Simulator::FN(VectorFormat vform,                 \
-                             LogicVRegister dst,                 \
-                             const LogicVRegister& src1,         \
-                             const LogicVRegister& src2) {       \
-  if (LaneSizeInBitsFromFormat(vform) == kSRegSize) {            \
-    FN<float>(vform, dst, src1, src2);                           \
-  } else {                                                       \
-    VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize);   \
-    FN<double>(vform, dst, src1, src2);                          \
-  }                                                              \
-  return dst;                                                    \
-}
+  LogicVRegister Simulator::FN(VectorFormat vform,               \
+                               LogicVRegister dst,               \
+                               const LogicVRegister& src1,       \
+                               const LogicVRegister& src2) {     \
+    if (LaneSizeInBitsFromFormat(vform) == kSRegSize) {          \
+      FN<float>(vform, dst, src1, src2);                         \
+    } else {                                                     \
+      VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize); \
+      FN<double>(vform, dst, src1, src2);                        \
+    }                                                            \
+    return dst;                                                  \
+  }
 NEON_FP3SAME_LIST(DEFINE_NEON_FP_VECTOR_OP)
 #undef DEFINE_NEON_FP_VECTOR_OP
 
@@ -3984,12 +4053,24 @@
     T nan_result = FPProcessNaNs(op1, op2);
     if (!std::isnan(nan_result)) {
       switch (cond) {
-        case eq: result = (op1 == op2); break;
-        case ge: result = (op1 >= op2); break;
-        case gt: result = (op1 > op2) ; break;
-        case le: result = (op1 <= op2); break;
-        case lt: result = (op1 < op2) ; break;
-        default: VIXL_UNREACHABLE(); break;
+        case eq:
+          result = (op1 == op2);
+          break;
+        case ge:
+          result = (op1 >= op2);
+          break;
+        case gt:
+          result = (op1 > op2);
+          break;
+        case le:
+          result = (op1 <= op2);
+          break;
+        case lt:
+          result = (op1 < op2);
+          break;
+        default:
+          VIXL_UNREACHABLE();
+          break;
       }
     }
     dst.SetUint(vform, i, result ? MaxUintFromFormat(vform) : 0);
@@ -4023,8 +4104,8 @@
     fcmp<float>(vform, dst, src, zero_reg, cond);
   } else {
     VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize);
-    LogicVRegister zero_reg = dup_immediate(vform, temp,
-                                            double_to_rawbits(0.0));
+    LogicVRegister zero_reg =
+        dup_immediate(vform, temp, double_to_rawbits(0.0));
     fcmp<double>(vform, dst, src, zero_reg, cond);
   }
   return dst;
@@ -4200,32 +4281,32 @@
 }
 
 
-#define DEFINE_NEON_FP_PAIR_OP(FNP, FN, OP)                          \
-LogicVRegister Simulator::FNP(VectorFormat vform,                    \
-                              LogicVRegister dst,                    \
-                              const LogicVRegister& src1,            \
-                              const LogicVRegister& src2) {          \
-  SimVRegister temp1, temp2;                                         \
-  uzp1(vform, temp1, src1, src2);                                    \
-  uzp2(vform, temp2, src1, src2);                                    \
-  FN(vform, dst, temp1, temp2);                                      \
-  return dst;                                                        \
-}                                                                    \
-                                                                     \
-LogicVRegister Simulator::FNP(VectorFormat vform,                    \
-                              LogicVRegister dst,                    \
-                              const LogicVRegister& src) {           \
-  if (vform == kFormatS) {                                           \
-    float result = OP(src.Float<float>(0), src.Float<float>(1));     \
-    dst.SetFloat(0, result);                                         \
-  } else {                                                           \
-    VIXL_ASSERT(vform == kFormatD);                                  \
-    double result = OP(src.Float<double>(0), src.Float<double>(1));  \
-    dst.SetFloat(0, result);                                         \
-  }                                                                  \
-  dst.ClearForWrite(vform);                                          \
-  return dst;                                                        \
-}
+#define DEFINE_NEON_FP_PAIR_OP(FNP, FN, OP)                           \
+  LogicVRegister Simulator::FNP(VectorFormat vform,                   \
+                                LogicVRegister dst,                   \
+                                const LogicVRegister& src1,           \
+                                const LogicVRegister& src2) {         \
+    SimVRegister temp1, temp2;                                        \
+    uzp1(vform, temp1, src1, src2);                                   \
+    uzp2(vform, temp2, src1, src2);                                   \
+    FN(vform, dst, temp1, temp2);                                     \
+    return dst;                                                       \
+  }                                                                   \
+                                                                      \
+  LogicVRegister Simulator::FNP(VectorFormat vform,                   \
+                                LogicVRegister dst,                   \
+                                const LogicVRegister& src) {          \
+    if (vform == kFormatS) {                                          \
+      float result = OP(src.Float<float>(0), src.Float<float>(1));    \
+      dst.SetFloat(0, result);                                        \
+    } else {                                                          \
+      VIXL_ASSERT(vform == kFormatD);                                 \
+      double result = OP(src.Float<double>(0), src.Float<double>(1)); \
+      dst.SetFloat(0, result);                                        \
+    }                                                                 \
+    dst.ClearForWrite(vform);                                         \
+    return dst;                                                       \
+  }
 NEON_FPPAIRWISE_LIST(DEFINE_NEON_FP_PAIR_OP)
 #undef DEFINE_NEON_FP_PAIR_OP
 
@@ -4260,8 +4341,8 @@
 
 
 LogicVRegister Simulator::fmaxnmv(VectorFormat vform,
-                                 LogicVRegister dst,
-                                 const LogicVRegister& src) {
+                                  LogicVRegister dst,
+                                  const LogicVRegister& src) {
   return fminmaxv(vform, dst, src, &Simulator::FPMaxNM);
 }
 
@@ -4528,7 +4609,7 @@
   if (a < 0.5) {
     q0 = static_cast<int>(a * 512.0);
     r = 1.0 / sqrt((static_cast<double>(q0) + 0.5) / 512.0);
-  } else  {
+  } else {
     q1 = static_cast<int>(a * 256.0);
     r = 1.0 / sqrt((static_cast<double>(q1) + 0.5) / 256.0);
   }
@@ -4646,11 +4727,20 @@
               (std::fabs(op) < std::pow(2.0, -1024.0)))) {
     bool overflow_to_inf = false;
     switch (rounding) {
-      case FPTieEven: overflow_to_inf = true; break;
-      case FPPositiveInfinity: overflow_to_inf = (sign == 0); break;
-      case FPNegativeInfinity: overflow_to_inf = (sign == 1); break;
-      case FPZero: overflow_to_inf = false; break;
-      default: break;
+      case FPTieEven:
+        overflow_to_inf = true;
+        break;
+      case FPPositiveInfinity:
+        overflow_to_inf = (sign == 0);
+        break;
+      case FPNegativeInfinity:
+        overflow_to_inf = (sign == 1);
+        break;
+      case FPZero:
+        overflow_to_inf = false;
+        break;
+      default:
+        break;
     }
     FPProcessException();  // FPExc_Overflow and FPExc_Inexact.
     if (overflow_to_inf) {
@@ -4691,7 +4781,7 @@
     double scaled = double_pack(0, 1022, Bits(fraction, 51, 44) << 44);
 
     if (sizeof(T) == sizeof(float)) {  // NOLINT(runtime/sizeof)
-      result_exp = (253 - exp);  // In range 253-254 = -1 to 253+1 = 254.
+      result_exp = (253 - exp);        // In range 253-254 = -1 to 253+1 = 254.
     } else {
       result_exp = (2045 - exp);  // In range 2045-2046 = -1 to 2045+1 = 2046.
     }
@@ -4800,7 +4890,7 @@
     T op = src.Float<T>(i);
     T result;
     if (std::isnan(op)) {
-       result = FPProcessNaN(op);
+      result = FPProcessNaN(op);
     } else {
       int exp;
       uint32_t sign;
diff --git a/src/vixl/a64/macro-assembler-a64.cc b/src/vixl/a64/macro-assembler-a64.cc
index 44f0f0d..3fa2d99 100644
--- a/src/vixl/a64/macro-assembler-a64.cc
+++ b/src/vixl/a64/macro-assembler-a64.cc
@@ -46,9 +46,10 @@
 
 
 LiteralPool::LiteralPool(MacroAssembler* masm)
-    : Pool(masm), size_(0), first_use_(-1),
-      recommended_checkpoint_(kNoCheckpointRequired) {
-}
+    : Pool(masm),
+      size_(0),
+      first_use_(-1),
+      recommended_checkpoint_(kNoCheckpointRequired) {}
 
 
 LiteralPool::~LiteralPool() {
@@ -264,6 +265,12 @@
 
 EmissionCheckScope::EmissionCheckScope(MacroAssembler* masm, size_t size)
     : masm_(masm) {
+  if (masm_ == NULL) {
+    // Nothing to do.
+    // We may reach this point in a context of conditional code generation. See
+    // `MacroAssembler::MoveImmediateHelper()` for an example.
+    return;
+  }
   masm_->EnsureEmitFor(size);
   masm_->BlockPools();
 #ifdef VIXL_DEBUG
@@ -275,6 +282,10 @@
 
 
 EmissionCheckScope::~EmissionCheckScope() {
+  if (masm_ == NULL) {
+    // Nothing to do.
+    return;
+  }
 #ifdef VIXL_DEBUG
   masm_->ReleaseBuffer();
   VIXL_ASSERT(masm_->SizeOfCodeGeneratedSince(&start_) <= size_);
@@ -300,7 +311,7 @@
 }
 
 
-MacroAssembler::MacroAssembler(byte * buffer,
+MacroAssembler::MacroAssembler(byte* buffer,
                                size_t capacity,
                                PositionIndependentCodeOption pic)
     : Assembler(buffer, capacity, pic),
@@ -318,8 +329,7 @@
 }
 
 
-MacroAssembler::~MacroAssembler() {
-}
+MacroAssembler::~MacroAssembler() {}
 
 
 void MacroAssembler::Reset() {
@@ -357,7 +367,7 @@
 
 
 int MacroAssembler::MoveImmediateHelper(MacroAssembler* masm,
-                                        const Register &rd,
+                                        const Register& rd,
                                         uint64_t imm) {
   bool emit_code = (masm != NULL);
   VIXL_ASSERT(is_uint32(imm) || is_int32(imm) || rd.Is64Bits());
@@ -417,7 +427,7 @@
     // halfword, and movk for subsequent halfwords.
     VIXL_ASSERT((reg_size % 16) == 0);
     bool first_mov_done = false;
-    for (unsigned i = 0; i < (temp.size() / 16); i++) {
+    for (unsigned i = 0; i < (reg_size / 16); i++) {
       uint64_t imm16 = (imm >> (16 * i)) & 0xffff;
       if (imm16 != ignored_halfword) {
         if (!first_mov_done) {
@@ -475,8 +485,12 @@
     // Immediate can be represented in a logical orr instruction.
     VIXL_ASSERT(!dst.IsZero());
     if (emit_code) {
-      masm->LogicalImmediate(
-          dst, AppropriateZeroRegFor(dst), n, imm_s, imm_r, ORR);
+      masm->LogicalImmediate(dst,
+                             AppropriateZeroRegFor(dst),
+                             n,
+                             imm_s,
+                             imm_r,
+                             ORR);
     }
     return true;
   }
@@ -491,12 +505,23 @@
     B(static_cast<Condition>(type), label);
   } else {
     switch (type) {
-      case always:        B(label);              break;
-      case never:         break;
-      case reg_zero:      Cbz(reg, label);       break;
-      case reg_not_zero:  Cbnz(reg, label);      break;
-      case reg_bit_clear: Tbz(reg, bit, label);  break;
-      case reg_bit_set:   Tbnz(reg, bit, label); break;
+      case always:
+        B(label);
+        break;
+      case never:
+        break;
+      case reg_zero:
+        Cbz(reg, label);
+        break;
+      case reg_not_zero:
+        Cbnz(reg, label);
+        break;
+      case reg_bit_clear:
+        Tbz(reg, bit, label);
+        break;
+      case reg_bit_set:
+        Tbnz(reg, bit, label);
+        break;
       default:
         VIXL_UNREACHABLE();
     }
@@ -646,8 +671,7 @@
 }
 
 
-void MacroAssembler::Tst(const Register& rn,
-                         const Operand& operand) {
+void MacroAssembler::Tst(const Register& rn, const Operand& operand) {
   VIXL_ASSERT(allow_macro_instructions_);
   Ands(AppropriateZeroRegFor(rn), rn, operand);
 }
@@ -795,11 +819,13 @@
     // same modes here.
     VIXL_ASSERT(operand.shift_amount() <= 4);
     VIXL_ASSERT(operand.reg().Is64Bits() ||
-           ((operand.extend() != UXTX) && (operand.extend() != SXTX)));
+                ((operand.extend() != UXTX) && (operand.extend() != SXTX)));
 
     temps.Exclude(operand.reg());
     Register temp = temps.AcquireSameSizeAs(rn);
-    EmitExtendShift(temp, operand.reg(), operand.extend(),
+    EmitExtendShift(temp,
+                    operand.reg(),
+                    operand.extend(),
                     operand.shift_amount());
     Logical(rd, rn, Operand(temp), op);
   } else {
@@ -828,7 +854,9 @@
   } else if (operand.IsExtendedRegister()) {
     // Emit an extend instruction if moving an extended register. This handles
     // extend with post-shift operations, too.
-    EmitExtendShift(rd, operand.reg(), operand.extend(),
+    EmitExtendShift(rd,
+                    operand.reg(),
+                    operand.extend(),
                     operand.shift_amount());
   } else {
     // Otherwise, emit a register move only if the registers are distinct, or
@@ -840,8 +868,8 @@
     // this case, the instruction is discarded.
     //
     // If the sp is an operand, add #0 is emitted, otherwise, orr #0.
-    if (!rd.Is(operand.reg()) || (rd.Is32Bits() &&
-                                  (discard_mode == kDontDiscardForSameWReg))) {
+    if (!rd.Is(operand.reg()) ||
+        (rd.Is32Bits() && (discard_mode == kDontDiscardForSameWReg))) {
       mov(rd, operand.reg());
     }
   }
@@ -1011,9 +1039,7 @@
 }
 
 
-void MacroAssembler::Movi(const VRegister& vd,
-                          uint64_t hi,
-                          uint64_t lo) {
+void MacroAssembler::Movi(const VRegister& vd, uint64_t hi, uint64_t lo) {
   // TODO: Move 128-bit values in a more efficient way.
   VIXL_ASSERT(vd.Is128Bits());
   UseScratchRegisterScope temps(this);
@@ -1039,7 +1065,9 @@
     // Emit two instructions for the extend case. This differs from Mov, as
     // the extend and invert can't be achieved in one instruction.
     Register temp = temps.AcquireSameSizeAs(rd);
-    EmitExtendShift(temp, operand.reg(), operand.extend(),
+    EmitExtendShift(temp,
+                    operand.reg(),
+                    operand.extend(),
                     operand.shift_amount());
     mvn(rd, Operand(temp));
   } else {
@@ -1109,45 +1137,198 @@
 }
 
 
-void MacroAssembler::Csel(const Register& rd,
-                          const Register& rn,
-                          const Operand& operand,
-                          Condition cond) {
-  VIXL_ASSERT(allow_macro_instructions_);
-  VIXL_ASSERT(!rd.IsZero());
-  VIXL_ASSERT(!rn.IsZero());
-  VIXL_ASSERT((cond != al) && (cond != nv));
-  // The worst case for size is csel immediate:
-  //  * up to 4 instructions to materialise the constant
-  //  * 1 instruction for csel
-  MacroEmissionCheckScope guard(this);
+void MacroAssembler::CselHelper(MacroAssembler* masm,
+                                const Register& rd,
+                                Operand left,
+                                Operand right,
+                                Condition cond,
+                                bool* should_synthesise_left,
+                                bool* should_synthesise_right) {
+  bool emit_code = (masm != NULL);
 
-  if (operand.IsImmediate()) {
-    // Immediate argument. Handle special cases of 0, 1 and -1 using zero
-    // register.
-    int64_t imm = operand.immediate();
-    Register zr = AppropriateZeroRegFor(rn);
-    if (imm == 0) {
-      csel(rd, rn, zr, cond);
-    } else if (imm == 1) {
-      csinc(rd, rn, zr, cond);
-    } else if (imm == -1) {
-      csinv(rd, rn, zr, cond);
-    } else {
-      UseScratchRegisterScope temps(this);
-      Register temp = temps.AcquireSameSizeAs(rn);
-      Mov(temp, operand.immediate());
-      csel(rd, rn, temp, cond);
+  VIXL_ASSERT(!emit_code || masm->allow_macro_instructions_);
+  VIXL_ASSERT((cond != al) && (cond != nv));
+  VIXL_ASSERT(!rd.IsZero() && !rd.IsSP());
+  VIXL_ASSERT(left.IsImmediate() || !left.reg().IsSP());
+  VIXL_ASSERT(right.IsImmediate() || !right.reg().IsSP());
+
+  if (should_synthesise_left != NULL) *should_synthesise_left = false;
+  if (should_synthesise_right != NULL) *should_synthesise_right = false;
+
+  // The worst case for size occurs when the inputs are two non encodable
+  // constants:
+  //  * up to 4 instructions to materialise the left constant
+  //  * up to 4 instructions to materialise the right constant
+  //  * 1 instruction for csel
+  EmissionCheckScope guard(masm, 9 * kInstructionSize);
+  UseScratchRegisterScope temps;
+  if (masm != NULL) {
+    temps.Open(masm);
+  }
+
+  // Try to handle cases where both inputs are immediates.
+  bool left_is_immediate = left.IsImmediate() || left.IsZero();
+  bool right_is_immediate = right.IsImmediate() || right.IsZero();
+  if (left_is_immediate && right_is_immediate &&
+      CselSubHelperTwoImmediates(masm,
+                                 rd,
+                                 left.GetEquivalentImmediate(),
+                                 right.GetEquivalentImmediate(),
+                                 cond,
+                                 should_synthesise_left,
+                                 should_synthesise_right)) {
+    return;
+  }
+
+  // Handle cases where one of the two inputs is -1, 0, or 1.
+  bool left_is_small_immediate =
+      left_is_immediate && ((-1 <= left.GetEquivalentImmediate()) &&
+                            (left.GetEquivalentImmediate() <= 1));
+  bool right_is_small_immediate =
+      right_is_immediate && ((-1 <= right.GetEquivalentImmediate()) &&
+                             (right.GetEquivalentImmediate() <= 1));
+  if (right_is_small_immediate || left_is_small_immediate) {
+    bool swapped_inputs = false;
+    if (!right_is_small_immediate) {
+      std::swap(left, right);
+      cond = InvertCondition(cond);
+      swapped_inputs = true;
     }
-  } else if (operand.IsShiftedRegister() && (operand.shift_amount() == 0)) {
-    // Unshifted register argument.
-    csel(rd, rn, operand.reg(), cond);
+    CselSubHelperRightSmallImmediate(masm,
+                                     &temps,
+                                     rd,
+                                     left,
+                                     right,
+                                     cond,
+                                     swapped_inputs ? should_synthesise_right
+                                                    : should_synthesise_left);
+    return;
+  }
+
+  // Otherwise both inputs need to be available in registers. Synthesise them
+  // if necessary and emit the `csel`.
+  if (!left.IsPlainRegister()) {
+    if (emit_code) {
+      Register temp = temps.AcquireSameSizeAs(rd);
+      masm->Mov(temp, left);
+      left = temp;
+    }
+    if (should_synthesise_left != NULL) *should_synthesise_left = true;
+  }
+  if (!right.IsPlainRegister()) {
+    if (emit_code) {
+      Register temp = temps.AcquireSameSizeAs(rd);
+      masm->Mov(temp, right);
+      right = temp;
+    }
+    if (should_synthesise_right != NULL) *should_synthesise_right = true;
+  }
+  if (emit_code) {
+    VIXL_ASSERT(left.IsPlainRegister() && right.IsPlainRegister());
+    if (left.reg().Is(right.reg())) {
+      masm->Mov(rd, left.reg());
+    } else {
+      masm->csel(rd, left.reg(), right.reg(), cond);
+    }
+  }
+}
+
+
+bool MacroAssembler::CselSubHelperTwoImmediates(MacroAssembler* masm,
+                                                const Register& rd,
+                                                int64_t left,
+                                                int64_t right,
+                                                Condition cond,
+                                                bool* should_synthesise_left,
+                                                bool* should_synthesise_right) {
+  bool emit_code = (masm != NULL);
+  if (should_synthesise_left != NULL) *should_synthesise_left = false;
+  if (should_synthesise_right != NULL) *should_synthesise_right = false;
+
+  if (left == right) {
+    if (emit_code) masm->Mov(rd, left);
+    return true;
+  } else if (left == -right) {
+    if (should_synthesise_right != NULL) *should_synthesise_right = true;
+    if (emit_code) {
+      masm->Mov(rd, right);
+      masm->Cneg(rd, rd, cond);
+    }
+    return true;
+  }
+
+  if (CselSubHelperTwoOrderedImmediates(masm, rd, left, right, cond)) {
+    return true;
   } else {
-    // All other arguments.
-    UseScratchRegisterScope temps(this);
-    Register temp = temps.AcquireSameSizeAs(rn);
-    Mov(temp, operand);
-    csel(rd, rn, temp, cond);
+    std::swap(left, right);
+    if (CselSubHelperTwoOrderedImmediates(masm,
+                                          rd,
+                                          left,
+                                          right,
+                                          InvertCondition(cond))) {
+      return true;
+    }
+  }
+
+  // TODO: Handle more situations. For example handle `csel rd, #5, #6, cond`
+  // with `cinc`.
+  return false;
+}
+
+
+bool MacroAssembler::CselSubHelperTwoOrderedImmediates(MacroAssembler* masm,
+                                                       const Register& rd,
+                                                       int64_t left,
+                                                       int64_t right,
+                                                       Condition cond) {
+  bool emit_code = (masm != NULL);
+
+  if ((left == 0) && (right == 1)) {
+    if (emit_code) masm->cset(rd, cond);
+    return true;
+  } else if ((left == 0) && (right == -1)) {
+    Register zr = AppropriateZeroRegFor(rd);
+    if (emit_code) masm->csinv(rd, zr, zr, InvertCondition(cond));
+    return true;
+  }
+  return false;
+}
+
+
+void MacroAssembler::CselSubHelperRightSmallImmediate(
+    MacroAssembler* masm,
+    UseScratchRegisterScope* temps,
+    const Register& rd,
+    const Operand& left,
+    const Operand& right,
+    Condition cond,
+    bool* should_synthesise_left) {
+  bool emit_code = (masm != NULL);
+  VIXL_ASSERT((right.IsImmediate() || right.IsZero()) &&
+              (-1 <= right.GetEquivalentImmediate()) &&
+              (right.GetEquivalentImmediate() <= 1));
+  Register left_register;
+
+  if (left.IsPlainRegister()) {
+    left_register = left.reg();
+  } else {
+    if (emit_code) {
+      left_register = temps->AcquireSameSizeAs(rd);
+      masm->Mov(left_register, left);
+    }
+    if (should_synthesise_left != NULL) *should_synthesise_left = true;
+  }
+  if (emit_code) {
+    int64_t imm = right.GetEquivalentImmediate();
+    Register zr = AppropriateZeroRegFor(rd);
+    if (imm == 0) {
+      masm->csel(rd, left_register, zr, cond);
+    } else if (imm == 1) {
+      masm->csinc(rd, left_register, zr, cond);
+    } else {
+      VIXL_ASSERT(imm == -1);
+      masm->csinv(rd, left_register, zr, cond);
+    }
   }
 }
 
@@ -1206,7 +1387,8 @@
 }
 
 
-void MacroAssembler::Fcmp(const FPRegister& fn, double value,
+void MacroAssembler::Fcmp(const FPRegister& fn,
+                          double value,
                           FPTrapFlags trap) {
   VIXL_ASSERT(allow_macro_instructions_);
   // The worst case for size is:
@@ -1293,9 +1475,7 @@
 }
 
 
-
-void MacroAssembler::Neg(const Register& rd,
-                         const Operand& operand) {
+void MacroAssembler::Neg(const Register& rd, const Operand& operand) {
   VIXL_ASSERT(allow_macro_instructions_);
   if (operand.IsImmediate()) {
     Mov(rd, -operand.immediate());
@@ -1305,8 +1485,7 @@
 }
 
 
-void MacroAssembler::Negs(const Register& rd,
-                          const Operand& operand) {
+void MacroAssembler::Negs(const Register& rd, const Operand& operand) {
   VIXL_ASSERT(allow_macro_instructions_);
   Subs(rd, AppropriateZeroRegFor(rd), operand);
 }
@@ -1391,7 +1570,7 @@
   }
 
   if ((operand.IsImmediate() && !IsImmAddSub(operand.immediate())) ||
-      (rn.IsZero() && !operand.IsShiftedRegister())                ||
+      (rn.IsZero() && !operand.IsShiftedRegister()) ||
       (operand.IsShiftedRegister() && (operand.shift() == ROR))) {
     UseScratchRegisterScope temps(this);
     Register temp = temps.AcquireSameSizeAs(rn);
@@ -1441,16 +1620,14 @@
 }
 
 
-void MacroAssembler::Ngc(const Register& rd,
-                         const Operand& operand) {
+void MacroAssembler::Ngc(const Register& rd, const Operand& operand) {
   VIXL_ASSERT(allow_macro_instructions_);
   Register zr = AppropriateZeroRegFor(rd);
   Sbc(rd, zr, operand);
 }
 
 
-void MacroAssembler::Ngcs(const Register& rd,
-                         const Operand& operand) {
+void MacroAssembler::Ngcs(const Register& rd, const Operand& operand) {
   VIXL_ASSERT(allow_macro_instructions_);
   Register zr = AppropriateZeroRegFor(rd);
   Sbcs(rd, zr, operand);
@@ -1480,7 +1657,7 @@
     VIXL_ASSERT(operand.reg().size() == rd.size());
     VIXL_ASSERT(operand.shift() != ROR);
     VIXL_ASSERT(is_uintn(rd.size() == kXRegSize ? kXRegSizeLog2 : kWRegSizeLog2,
-                    operand.shift_amount()));
+                         operand.shift_amount()));
     temps.Exclude(operand.reg());
     Register temp = temps.AcquireSameSizeAs(rn);
     EmitShift(temp, operand.reg(), operand.shift(), operand.shift_amount());
@@ -1492,10 +1669,12 @@
     // same modes.
     VIXL_ASSERT(operand.shift_amount() <= 4);
     VIXL_ASSERT(operand.reg().Is64Bits() ||
-           ((operand.extend() != UXTX) && (operand.extend() != SXTX)));
+                ((operand.extend() != UXTX) && (operand.extend() != SXTX)));
     temps.Exclude(operand.reg());
     Register temp = temps.AcquireSameSizeAs(rn);
-    EmitExtendShift(temp, operand.reg(), operand.extend(),
+    EmitExtendShift(temp,
+                    operand.reg(),
+                    operand.extend(),
                     operand.shift_amount());
     AddSubWithCarry(rd, rn, Operand(temp), S, op);
   } else {
@@ -1505,11 +1684,11 @@
 }
 
 
-#define DEFINE_FUNCTION(FN, REGTYPE, REG, OP)                         \
-void MacroAssembler::FN(const REGTYPE REG, const MemOperand& addr) {  \
-  VIXL_ASSERT(allow_macro_instructions_);                             \
-  LoadStoreMacro(REG, addr, OP);                                      \
-}
+#define DEFINE_FUNCTION(FN, REGTYPE, REG, OP)                          \
+  void MacroAssembler::FN(const REGTYPE REG, const MemOperand& addr) { \
+    VIXL_ASSERT(allow_macro_instructions_);                            \
+    LoadStoreMacro(REG, addr, OP);                                     \
+  }
 LS_MACRO_LIST(DEFINE_FUNCTION)
 #undef DEFINE_FUNCTION
 
@@ -1552,13 +1731,13 @@
 }
 
 
-#define DEFINE_FUNCTION(FN, REGTYPE, REG, REG2, OP)  \
-void MacroAssembler::FN(const REGTYPE REG,           \
-                        const REGTYPE REG2,          \
-                        const MemOperand& addr) {    \
-  VIXL_ASSERT(allow_macro_instructions_);            \
-  LoadStorePairMacro(REG, REG2, addr, OP);           \
-}
+#define DEFINE_FUNCTION(FN, REGTYPE, REG, REG2, OP) \
+  void MacroAssembler::FN(const REGTYPE REG,        \
+                          const REGTYPE REG2,       \
+                          const MemOperand& addr) { \
+    VIXL_ASSERT(allow_macro_instructions_);         \
+    LoadStorePairMacro(REG, REG2, addr, OP);        \
+  }
 LSPAIR_MACRO_LIST(DEFINE_FUNCTION)
 #undef DEFINE_FUNCTION
 
@@ -1628,8 +1807,10 @@
 }
 
 
-void MacroAssembler::Push(const CPURegister& src0, const CPURegister& src1,
-                          const CPURegister& src2, const CPURegister& src3) {
+void MacroAssembler::Push(const CPURegister& src0,
+                          const CPURegister& src1,
+                          const CPURegister& src2,
+                          const CPURegister& src3) {
   VIXL_ASSERT(allow_macro_instructions_);
   VIXL_ASSERT(AreSameSizeAndType(src0, src1, src2, src3));
   VIXL_ASSERT(src0.IsValid());
@@ -1642,8 +1823,10 @@
 }
 
 
-void MacroAssembler::Pop(const CPURegister& dst0, const CPURegister& dst1,
-                         const CPURegister& dst2, const CPURegister& dst3) {
+void MacroAssembler::Pop(const CPURegister& dst0,
+                         const CPURegister& dst1,
+                         const CPURegister& dst2,
+                         const CPURegister& dst3) {
   // It is not valid to pop into the same register more than once in one
   // instruction, not even into the zero register.
   VIXL_ASSERT(allow_macro_instructions_);
@@ -1749,14 +1932,16 @@
 }
 
 
-void MacroAssembler::PushHelper(int count, int size,
+void MacroAssembler::PushHelper(int count,
+                                int size,
                                 const CPURegister& src0,
                                 const CPURegister& src1,
                                 const CPURegister& src2,
                                 const CPURegister& src3) {
   // Ensure that we don't unintentionally modify scratch or debug registers.
   // Worst case for size is 2 stp.
-  InstructionAccurateScope scope(this, 2,
+  InstructionAccurateScope scope(this,
+                                 2,
                                  InstructionAccurateScope::kMaximumSize);
 
   VIXL_ASSERT(AreSameSizeAndType(src0, src1, src2, src3));
@@ -1791,14 +1976,16 @@
 }
 
 
-void MacroAssembler::PopHelper(int count, int size,
+void MacroAssembler::PopHelper(int count,
+                               int size,
                                const CPURegister& dst0,
                                const CPURegister& dst1,
                                const CPURegister& dst2,
                                const CPURegister& dst3) {
   // Ensure that we don't unintentionally modify scratch or debug registers.
   // Worst case for size is 2 ldp.
-  InstructionAccurateScope scope(this, 2,
+  InstructionAccurateScope scope(this,
+                                 2,
                                  InstructionAccurateScope::kMaximumSize);
 
   VIXL_ASSERT(AreSameSizeAndType(dst0, dst1, dst2, dst3));
@@ -1990,9 +2177,7 @@
 
   UseScratchRegisterScope temps(this);
 
-  MemOperand loc = BaseMemOperandForLoadStoreCPURegList(registers,
-                                                        mem,
-                                                        &temps);
+  MemOperand loc = BaseMemOperandForLoadStoreCPURegList(registers, mem, &temps);
 
   while (registers.Count() >= 2) {
     const CPURegister& dst0 = registers.PopLowestIndex();
@@ -2057,7 +2242,7 @@
 
 // This is the main Printf implementation. All callee-saved registers are
 // preserved, but NZCV and the caller-saved registers may be clobbered.
-void MacroAssembler::PrintfNoPreserve(const char * format,
+void MacroAssembler::PrintfNoPreserve(const char* format,
                                       const CPURegister& arg0,
                                       const CPURegister& arg1,
                                       const CPURegister& arg2,
@@ -2167,9 +2352,9 @@
     //   strlen(format) + 1 (includes null termination)
     //   padding to next instruction
     //   unreachable
-    EmissionCheckScope guard(
-        this,
-        AlignUp(strlen(format) + 1, kInstructionSize) + 2 * kInstructionSize);
+    EmissionCheckScope guard(this,
+                             AlignUp(strlen(format) + 1, kInstructionSize) +
+                                 2 * kInstructionSize);
     Label after_data;
     B(&after_data);
     Bind(&format_address);
@@ -2190,7 +2375,7 @@
   if (allow_simulator_instructions_) {
     InstructionAccurateScope scope(this, kPrintfLength / kInstructionSize);
     hlt(kPrintfOpcode);
-    dc32(arg_count);          // kPrintfArgCountOffset
+    dc32(arg_count);  // kPrintfArgCountOffset
 
     // Determine the argument pattern.
     uint32_t arg_pattern_list = 0;
@@ -2205,7 +2390,7 @@
       VIXL_ASSERT(arg_pattern < (1 << kPrintfArgPatternBits));
       arg_pattern_list |= (arg_pattern << (kPrintfArgPatternBits * i));
     }
-    dc32(arg_pattern_list);   // kPrintfArgPatternListOffset
+    dc32(arg_pattern_list);  // kPrintfArgPatternListOffset
   } else {
     Register tmp = temps.AcquireX();
     Mov(tmp, reinterpret_cast<uintptr_t>(printf));
@@ -2214,7 +2399,7 @@
 }
 
 
-void MacroAssembler::Printf(const char * format,
+void MacroAssembler::Printf(const char* format,
                             CPURegister arg0,
                             CPURegister arg1,
                             CPURegister arg2,
@@ -2238,7 +2423,8 @@
   PushCPURegList(kCallerSaved);
   PushCPURegList(kCallerSavedV);
 
-  { UseScratchRegisterScope temps(this);
+  {
+    UseScratchRegisterScope temps(this);
     // We can use caller-saved registers as scratch values (except for argN).
     temps.Include(kCallerSaved);
     temps.Include(kCallerSavedV);
@@ -2255,7 +2441,8 @@
       // Allocate a register to hold the original stack pointer value, to pass
       // to PrintfNoPreserve as an argument.
       Register arg_sp = temps.AcquireX();
-      Add(arg_sp, StackPointer(),
+      Add(arg_sp,
+          StackPointer(),
           kCallerSaved.TotalSizeInBytes() + kCallerSavedV.TotalSizeInBytes());
       if (arg0_sp) arg0 = Register(arg_sp.code(), arg0.size());
       if (arg1_sp) arg1 = Register(arg_sp.code(), arg1.size());
@@ -2361,6 +2548,7 @@
 
 void UseScratchRegisterScope::Open(MacroAssembler* masm) {
   VIXL_ASSERT(!initialised_);
+  VIXL_ASSERT(masm != NULL);
   available_ = masm->TmpList();
   availablefp_ = masm->FPTmpList();
   old_available_ = available_->list();
@@ -2397,16 +2585,16 @@
 
 // This allows deferred (and optional) initialisation of the scope.
 UseScratchRegisterScope::UseScratchRegisterScope()
-    : available_(NULL), availablefp_(NULL),
-      old_available_(0), old_availablefp_(0) {
+    : available_(NULL),
+      availablefp_(NULL),
+      old_available_(0),
+      old_availablefp_(0) {
 #ifdef VIXL_DEBUG
   initialised_ = false;
 #endif
 }
 
-UseScratchRegisterScope::~UseScratchRegisterScope() {
-  Close();
-}
+UseScratchRegisterScope::~UseScratchRegisterScope() { Close(); }
 
 
 bool UseScratchRegisterScope::IsAvailable(const CPURegister& reg) const {
diff --git a/src/vixl/a64/macro-assembler-a64.h b/src/vixl/a64/macro-assembler-a64.h
index c635af2..dea7781 100644
--- a/src/vixl/a64/macro-assembler-a64.h
+++ b/src/vixl/a64/macro-assembler-a64.h
@@ -37,21 +37,21 @@
 #include "vixl/a64/simulator-constants-a64.h"
 
 
-#define LS_MACRO_LIST(V)                                      \
-  V(Ldrb, Register&, rt, LDRB_w)                              \
-  V(Strb, Register&, rt, STRB_w)                              \
-  V(Ldrsb, Register&, rt, rt.Is64Bits() ? LDRSB_x : LDRSB_w)  \
-  V(Ldrh, Register&, rt, LDRH_w)                              \
-  V(Strh, Register&, rt, STRH_w)                              \
-  V(Ldrsh, Register&, rt, rt.Is64Bits() ? LDRSH_x : LDRSH_w)  \
-  V(Ldr, CPURegister&, rt, LoadOpFor(rt))                     \
-  V(Str, CPURegister&, rt, StoreOpFor(rt))                    \
+#define LS_MACRO_LIST(V)                                     \
+  V(Ldrb, Register&, rt, LDRB_w)                             \
+  V(Strb, Register&, rt, STRB_w)                             \
+  V(Ldrsb, Register&, rt, rt.Is64Bits() ? LDRSB_x : LDRSB_w) \
+  V(Ldrh, Register&, rt, LDRH_w)                             \
+  V(Strh, Register&, rt, STRH_w)                             \
+  V(Ldrsh, Register&, rt, rt.Is64Bits() ? LDRSH_x : LDRSH_w) \
+  V(Ldr, CPURegister&, rt, LoadOpFor(rt))                    \
+  V(Str, CPURegister&, rt, StoreOpFor(rt))                   \
   V(Ldrsw, Register&, rt, LDRSW_x)
 
 
-#define LSPAIR_MACRO_LIST(V)                              \
-  V(Ldp, CPURegister&, rt, rt2, LoadPairOpFor(rt, rt2))   \
-  V(Stp, CPURegister&, rt, rt2, StorePairOpFor(rt, rt2))  \
+#define LSPAIR_MACRO_LIST(V)                             \
+  V(Ldp, CPURegister&, rt, rt2, LoadPairOpFor(rt, rt2))  \
+  V(Stp, CPURegister&, rt, rt2, StorePairOpFor(rt, rt2)) \
   V(Ldpsw, CPURegister&, rt, rt2, LDPSW_x)
 
 namespace vixl {
@@ -81,10 +81,7 @@
   void SetNextCheckpoint(ptrdiff_t checkpoint);
   ptrdiff_t checkpoint() const { return checkpoint_; }
 
-  enum EmitOption {
-    kBranchRequired,
-    kNoBranchRequired
-  };
+  enum EmitOption { kBranchRequired, kNoBranchRequired };
 
  protected:
   // Next buffer offset at which a check is required for this pool.
@@ -169,8 +166,10 @@
   class BranchInfo {
    public:
     BranchInfo()
-        : max_reachable_pc_(0), pc_offset_(0),
-          label_(NULL), branch_type_(UnknownBranchType) {}
+        : max_reachable_pc_(0),
+          pc_offset_(0),
+          label_(NULL),
+          branch_type_(UnknownBranchType) {}
     BranchInfo(ptrdiff_t offset, Label* label, ImmBranchType branch_type)
         : pc_offset_(offset), label_(label), branch_type_(branch_type) {
       max_reachable_pc_ =
@@ -247,17 +246,15 @@
   // over the pool.
   static const int kPoolNonVeneerCodeSize = 1 * kInstructionSize;
 
-  void UpdateNextCheckPoint() {
-    SetNextCheckpoint(NextCheckPoint());
-  }
+  void UpdateNextCheckPoint() { SetNextCheckpoint(NextCheckPoint()); }
 
   int NumberOfPotentialVeneers() const {
     return static_cast<int>(unresolved_branches_.size());
   }
 
   size_t MaxSize() const {
-    return
-        kPoolNonVeneerCodeSize + unresolved_branches_.size() * kVeneerCodeSize;
+    return kPoolNonVeneerCodeSize +
+           unresolved_branches_.size() * kVeneerCodeSize;
   }
 
   size_t OtherPoolsMaxSize() const;
@@ -284,7 +281,7 @@
       if (empty()) {
         return kInvalidOffset;
       }
-      return min_element_key();
+      return GetMinElementKey();
     }
   };
 
@@ -293,6 +290,10 @@
     BranchInfoTypedSetIterator() : BranchInfoTypedSetIterBase(NULL) {}
     explicit BranchInfoTypedSetIterator(BranchInfoTypedSet* typed_set)
         : BranchInfoTypedSetIterBase(typed_set) {}
+
+    // TODO: Remove these and use the STL-like interface instead.
+    using BranchInfoTypedSetIterBase::Advance;
+    using BranchInfoTypedSetIterBase::Current;
   };
 
   class BranchInfoSet {
@@ -386,7 +387,7 @@
    public:
     explicit BranchInfoSetIterator(BranchInfoSet* set) : set_(set) {
       for (int i = 0; i < BranchInfoSet::kNumberOfTrackedBranchTypes; i++) {
-        new(&sub_iterator_[i])
+        new (&sub_iterator_[i])
             BranchInfoTypedSetIterator(&(set_->typed_set_[i]));
       }
     }
@@ -459,24 +460,26 @@
 
 
 // Required InvalSet template specialisations.
-template<>
-inline ptrdiff_t InvalSet<VeneerPool::BranchInfo,
-                          VeneerPool::kNPreallocatedInfos,
-                          ptrdiff_t,
-                          VeneerPool::kInvalidOffset,
-                          VeneerPool::kReclaimFrom,
-                          VeneerPool::kReclaimFactor>::Key(
-                              const VeneerPool::BranchInfo& branch_info) {
+template <>
+inline ptrdiff_t
+InvalSet<VeneerPool::BranchInfo,
+         VeneerPool::kNPreallocatedInfos,
+         ptrdiff_t,
+         VeneerPool::kInvalidOffset,
+         VeneerPool::kReclaimFrom,
+         VeneerPool::kReclaimFactor>::GetKey(const VeneerPool::BranchInfo&
+                                                 branch_info) {
   return branch_info.max_reachable_pc_;
 }
-template<>
+template <>
 inline void InvalSet<VeneerPool::BranchInfo,
                      VeneerPool::kNPreallocatedInfos,
                      ptrdiff_t,
                      VeneerPool::kInvalidOffset,
                      VeneerPool::kReclaimFrom,
-                     VeneerPool::kReclaimFactor>::SetKey(
-                         VeneerPool::BranchInfo* branch_info, ptrdiff_t key) {
+                     VeneerPool::kReclaimFactor>::SetKey(VeneerPool::BranchInfo*
+                                                             branch_info,
+                                                         ptrdiff_t key) {
   branch_info->max_reachable_pc_ = key;
 }
 
@@ -547,11 +550,14 @@
   // 'always' is used to generate unconditional branches.
   // 'never' is used to not generate a branch (generally as the inverse
   // branch type of 'always).
-  always, never,
+  always,
+  never,
   // cbz and cbnz
-  reg_zero, reg_not_zero,
+  reg_zero,
+  reg_not_zero,
   // tbz and tbnz
-  reg_bit_clear, reg_bit_set,
+  reg_bit_clear,
+  reg_bit_set,
 
   // Aliases.
   kBranchTypeFirstCondition = eq,
@@ -568,7 +574,8 @@
  public:
   MacroAssembler(size_t capacity,
                  PositionIndependentCodeOption pic = PositionIndependentCode);
-  MacroAssembler(byte * buffer, size_t capacity,
+  MacroAssembler(byte* buffer,
+                 size_t capacity,
                  PositionIndependentCodeOption pic = PositionIndependentCode);
   ~MacroAssembler();
 
@@ -595,7 +602,7 @@
   // a constant using the literal pool instead of using multiple 'mov immediate'
   // instructions.
   static int MoveImmediateHelper(MacroAssembler* masm,
-                                 const Register &rd,
+                                 const Register& rd,
                                  uint64_t imm);
   static bool OneInstrMoveImmediateHelper(MacroAssembler* masm,
                                           const Register& dst,
@@ -603,30 +610,14 @@
 
 
   // Logical macros.
-  void And(const Register& rd,
-           const Register& rn,
-           const Operand& operand);
-  void Ands(const Register& rd,
-            const Register& rn,
-            const Operand& operand);
-  void Bic(const Register& rd,
-           const Register& rn,
-           const Operand& operand);
-  void Bics(const Register& rd,
-            const Register& rn,
-            const Operand& operand);
-  void Orr(const Register& rd,
-           const Register& rn,
-           const Operand& operand);
-  void Orn(const Register& rd,
-           const Register& rn,
-           const Operand& operand);
-  void Eor(const Register& rd,
-           const Register& rn,
-           const Operand& operand);
-  void Eon(const Register& rd,
-           const Register& rn,
-           const Operand& operand);
+  void And(const Register& rd, const Register& rn, const Operand& operand);
+  void Ands(const Register& rd, const Register& rn, const Operand& operand);
+  void Bic(const Register& rd, const Register& rn, const Operand& operand);
+  void Bics(const Register& rd, const Register& rn, const Operand& operand);
+  void Orr(const Register& rd, const Register& rn, const Operand& operand);
+  void Orn(const Register& rd, const Register& rn, const Operand& operand);
+  void Eor(const Register& rd, const Register& rn, const Operand& operand);
+  void Eon(const Register& rd, const Register& rn, const Operand& operand);
   void Tst(const Register& rn, const Operand& operand);
   void LogicalMacro(const Register& rd,
                     const Register& rn,
@@ -638,22 +629,16 @@
            const Register& rn,
            const Operand& operand,
            FlagsUpdate S = LeaveFlags);
-  void Adds(const Register& rd,
-            const Register& rn,
-            const Operand& operand);
+  void Adds(const Register& rd, const Register& rn, const Operand& operand);
   void Sub(const Register& rd,
            const Register& rn,
            const Operand& operand,
            FlagsUpdate S = LeaveFlags);
-  void Subs(const Register& rd,
-            const Register& rn,
-            const Operand& operand);
+  void Subs(const Register& rd, const Register& rn, const Operand& operand);
   void Cmn(const Register& rn, const Operand& operand);
   void Cmp(const Register& rn, const Operand& operand);
-  void Neg(const Register& rd,
-           const Operand& operand);
-  void Negs(const Register& rd,
-            const Operand& operand);
+  void Neg(const Register& rd, const Operand& operand);
+  void Negs(const Register& rd, const Operand& operand);
 
   void AddSubMacro(const Register& rd,
                    const Register& rn,
@@ -662,22 +647,12 @@
                    AddSubOp op);
 
   // Add/sub with carry macros.
-  void Adc(const Register& rd,
-           const Register& rn,
-           const Operand& operand);
-  void Adcs(const Register& rd,
-            const Register& rn,
-            const Operand& operand);
-  void Sbc(const Register& rd,
-           const Register& rn,
-           const Operand& operand);
-  void Sbcs(const Register& rd,
-            const Register& rn,
-            const Operand& operand);
-  void Ngc(const Register& rd,
-           const Operand& operand);
-  void Ngcs(const Register& rd,
-            const Operand& operand);
+  void Adc(const Register& rd, const Register& rn, const Operand& operand);
+  void Adcs(const Register& rd, const Register& rn, const Operand& operand);
+  void Sbc(const Register& rd, const Register& rn, const Operand& operand);
+  void Sbcs(const Register& rd, const Register& rn, const Operand& operand);
+  void Ngc(const Register& rd, const Operand& operand);
+  void Ngcs(const Register& rd, const Operand& operand);
   void AddSubWithCarryMacro(const Register& rd,
                             const Register& rn,
                             const Operand& operand,
@@ -723,12 +698,32 @@
                                StatusFlags nzcv,
                                Condition cond,
                                ConditionalCompareOp op);
-  void Csel(const Register& rd,
-            const Register& rn,
-            const Operand& operand,
-            Condition cond);
 
-  // Load/store macros.
+  // On return, the boolean values pointed to will indicate whether `left` and
+  // `right` should be synthesised in a temporary register.
+  static void GetCselSynthesisInformation(const Register& rd,
+                                          const Operand& left,
+                                          const Operand& right,
+                                          bool* should_synthesise_left,
+                                          bool* should_synthesise_right) {
+    // Note that the helper does not need to look at the condition.
+    CselHelper(NULL,
+               rd,
+               left,
+               right,
+               eq,
+               should_synthesise_left,
+               should_synthesise_right);
+  }
+
+  void Csel(const Register& rd,
+            const Operand& left,
+            const Operand& right,
+            Condition cond) {
+    CselHelper(this, rd, left, right, cond);
+  }
+
+// Load/store macros.
 #define DECLARE_FUNCTION(FN, REGTYPE, REG, OP) \
   void FN(const REGTYPE REG, const MemOperand& addr);
   LS_MACRO_LIST(DECLARE_FUNCTION)
@@ -776,10 +771,14 @@
   //
   // Other than the registers passed into Pop, the stack pointer and (possibly)
   // the system stack pointer, these methods do not modify any other registers.
-  void Push(const CPURegister& src0, const CPURegister& src1 = NoReg,
-            const CPURegister& src2 = NoReg, const CPURegister& src3 = NoReg);
-  void Pop(const CPURegister& dst0, const CPURegister& dst1 = NoReg,
-           const CPURegister& dst2 = NoReg, const CPURegister& dst3 = NoReg);
+  void Push(const CPURegister& src0,
+            const CPURegister& src1 = NoReg,
+            const CPURegister& src2 = NoReg,
+            const CPURegister& src3 = NoReg);
+  void Pop(const CPURegister& dst0,
+           const CPURegister& dst1 = NoReg,
+           const CPURegister& dst2 = NoReg,
+           const CPURegister& dst3 = NoReg);
 
   // Alternative forms of Push and Pop, taking a RegList or CPURegList that
   // specifies the registers that are to be pushed or popped. Higher-numbered
@@ -794,26 +793,21 @@
   void PushCPURegList(CPURegList registers);
   void PopCPURegList(CPURegList registers);
 
-  void PushSizeRegList(RegList registers, unsigned reg_size,
+  void PushSizeRegList(
+      RegList registers,
+      unsigned reg_size,
       CPURegister::RegisterType type = CPURegister::kRegister) {
     PushCPURegList(CPURegList(type, reg_size, registers));
   }
-  void PopSizeRegList(RegList registers, unsigned reg_size,
-      CPURegister::RegisterType type = CPURegister::kRegister) {
+  void PopSizeRegList(RegList registers,
+                      unsigned reg_size,
+                      CPURegister::RegisterType type = CPURegister::kRegister) {
     PopCPURegList(CPURegList(type, reg_size, registers));
   }
-  void PushXRegList(RegList regs) {
-    PushSizeRegList(regs, kXRegSize);
-  }
-  void PopXRegList(RegList regs) {
-    PopSizeRegList(regs, kXRegSize);
-  }
-  void PushWRegList(RegList regs) {
-    PushSizeRegList(regs, kWRegSize);
-  }
-  void PopWRegList(RegList regs) {
-    PopSizeRegList(regs, kWRegSize);
-  }
+  void PushXRegList(RegList regs) { PushSizeRegList(regs, kXRegSize); }
+  void PopXRegList(RegList regs) { PopSizeRegList(regs, kXRegSize); }
+  void PushWRegList(RegList regs) { PushSizeRegList(regs, kWRegSize); }
+  void PopWRegList(RegList regs) { PopSizeRegList(regs, kWRegSize); }
   void PushDRegList(RegList regs) {
     PushSizeRegList(regs, kDRegSize, CPURegister::kVRegister);
   }
@@ -858,11 +852,17 @@
     StoreCPURegList(registers, MemOperand(StackPointer(), offset));
   }
 
-  void PeekSizeRegList(RegList registers, int64_t offset, unsigned reg_size,
+  void PeekSizeRegList(
+      RegList registers,
+      int64_t offset,
+      unsigned reg_size,
       CPURegister::RegisterType type = CPURegister::kRegister) {
     PeekCPURegList(CPURegList(type, reg_size, registers), offset);
   }
-  void PokeSizeRegList(RegList registers, int64_t offset, unsigned reg_size,
+  void PokeSizeRegList(
+      RegList registers,
+      int64_t offset,
+      unsigned reg_size,
       CPURegister::RegisterType type = CPURegister::kRegister) {
     PokeCPURegList(CPURegList(type, reg_size, registers), offset);
   }
@@ -955,9 +955,9 @@
   }
 
   // Branch type inversion relies on these relations.
-  VIXL_STATIC_ASSERT((reg_zero      == (reg_not_zero ^ 1)) &&
+  VIXL_STATIC_ASSERT((reg_zero == (reg_not_zero ^ 1)) &&
                      (reg_bit_clear == (reg_bit_set ^ 1)) &&
-                     (always        == (never ^ 1)));
+                     (always == (never ^ 1)));
 
   BranchType InvertBranchType(BranchType type) {
     if (kBranchTypeFirstCondition <= type && type <= kBranchTypeLastCondition) {
@@ -972,9 +972,7 @@
 
   void B(Label* label);
   void B(Label* label, Condition cond);
-  void B(Condition cond, Label* label) {
-    B(label, cond);
-  }
+  void B(Condition cond, Label* label) { B(label, cond); }
   void Bfm(const Register& rd,
            const Register& rn,
            unsigned immr,
@@ -1162,14 +1160,14 @@
               Condition cond) {
     Fccmp(vn, vm, nzcv, cond, EnableTrap);
   }
-  void Fcmp(const VRegister& vn, const VRegister& vm,
+  void Fcmp(const VRegister& vn,
+            const VRegister& vm,
             FPTrapFlags trap = DisableTrap) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     FPCompareMacro(vn, vm, trap);
   }
-  void Fcmp(const VRegister& vn, double value,
-            FPTrapFlags trap = DisableTrap);
+  void Fcmp(const VRegister& vn, double value, FPTrapFlags trap = DisableTrap);
   void Fcmpe(const VRegister& vn, double value);
   void Fcmpe(const VRegister& vn, const VRegister& vm) {
     Fcmp(vn, vm, EnableTrap);
@@ -1288,9 +1286,7 @@
     SingleEmissionCheckScope guard(this);
     fmax(vd, vn, vm);
   }
-  void Fmaxnm(const VRegister& vd,
-              const VRegister& vn,
-              const VRegister& vm) {
+  void Fmaxnm(const VRegister& vd, const VRegister& vn, const VRegister& vm) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     fmaxnm(vd, vn, vm);
@@ -1300,9 +1296,7 @@
     SingleEmissionCheckScope guard(this);
     fmin(vd, vn, vm);
   }
-  void Fminnm(const VRegister& vd,
-              const VRegister& vn,
-              const VRegister& vm) {
+  void Fminnm(const VRegister& vd, const VRegister& vn, const VRegister& vm) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     fminnm(vd, vn, vm);
@@ -1342,7 +1336,7 @@
   void Fmov(VRegister vd, double imm);
   void Fmov(VRegister vd, float imm);
   // Provide a template to allow other types to be converted automatically.
-  template<typename T>
+  template <typename T>
   void Fmov(VRegister vd, T imm) {
     VIXL_ASSERT(allow_macro_instructions_);
     Fmov(vd, static_cast<double>(imm));
@@ -1358,8 +1352,7 @@
     SingleEmissionCheckScope guard(this);
     fmul(vd, vn, vm);
   }
-  void Fnmul(const VRegister& vd, const VRegister& vn,
-             const VRegister& vm) {
+  void Fnmul(const VRegister& vd, const VRegister& vn, const VRegister& vm) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     fnmul(vd, vn, vm);
@@ -1497,9 +1490,11 @@
     VIXL_ASSERT(allow_macro_instructions_);
     VIXL_ASSERT(vt.IsQ());
     SingleEmissionCheckScope guard(this);
-    ldr(vt, new Literal<uint64_t>(high64, low64,
-                                  &literal_pool_,
-                                  RawLiteral::kDeletedOnPlacementByPool));
+    ldr(vt,
+        new Literal<uint64_t>(high64,
+                              low64,
+                              &literal_pool_,
+                              RawLiteral::kDeletedOnPlacementByPool));
   }
   void Ldr(const Register& rt, uint64_t imm) {
     VIXL_ASSERT(allow_macro_instructions_);
@@ -1917,9 +1912,7 @@
     SingleEmissionCheckScope guard(this);
     sxtw(rd, rn);
   }
-  void Tbl(const VRegister& vd,
-           const VRegister& vn,
-           const VRegister& vm) {
+  void Tbl(const VRegister& vd, const VRegister& vn, const VRegister& vm) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     tbl(vd, vn, vm);
@@ -1951,9 +1944,7 @@
     SingleEmissionCheckScope guard(this);
     tbl(vd, vn, vn2, vn3, vn4, vm);
   }
-  void Tbx(const VRegister& vd,
-           const VRegister& vn,
-           const VRegister& vm) {
+  void Tbx(const VRegister& vd, const VRegister& vn, const VRegister& vm) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     tbx(vd, vn, vm);
@@ -2043,9 +2034,7 @@
     SingleEmissionCheckScope guard(this);
     umaddl(rd, rn, rm, ra);
   }
-  void Umull(const Register& rd,
-             const Register& rn,
-             const Register& rm) {
+  void Umull(const Register& rd, const Register& rn, const Register& rm) {
     VIXL_ASSERT(allow_macro_instructions_);
     VIXL_ASSERT(!rd.IsZero());
     VIXL_ASSERT(!rn.IsZero());
@@ -2106,394 +2095,371 @@
     uxtw(rd, rn);
   }
 
-  // NEON 3 vector register instructions.
-  #define NEON_3VREG_MACRO_LIST(V) \
-    V(add, Add)                    \
-    V(addhn, Addhn)                \
-    V(addhn2, Addhn2)              \
-    V(addp, Addp)                  \
-    V(and_, And)                   \
-    V(bic, Bic)                    \
-    V(bif, Bif)                    \
-    V(bit, Bit)                    \
-    V(bsl, Bsl)                    \
-    V(cmeq, Cmeq)                  \
-    V(cmge, Cmge)                  \
-    V(cmgt, Cmgt)                  \
-    V(cmhi, Cmhi)                  \
-    V(cmhs, Cmhs)                  \
-    V(cmtst, Cmtst)                \
-    V(eor, Eor)                    \
-    V(fabd, Fabd)                  \
-    V(facge, Facge)                \
-    V(facgt, Facgt)                \
-    V(faddp, Faddp)                \
-    V(fcmeq, Fcmeq)                \
-    V(fcmge, Fcmge)                \
-    V(fcmgt, Fcmgt)                \
-    V(fmaxnmp, Fmaxnmp)            \
-    V(fmaxp, Fmaxp)                \
-    V(fminnmp, Fminnmp)            \
-    V(fminp, Fminp)                \
-    V(fmla, Fmla)                  \
-    V(fmls, Fmls)                  \
-    V(fmulx, Fmulx)                \
-    V(frecps, Frecps)              \
-    V(frsqrts, Frsqrts)            \
-    V(mla, Mla)                    \
-    V(mls, Mls)                    \
-    V(mul, Mul)                    \
-    V(orn, Orn)                    \
-    V(orr, Orr)                    \
-    V(pmul, Pmul)                  \
-    V(pmull, Pmull)                \
-    V(pmull2, Pmull2)              \
-    V(raddhn, Raddhn)              \
-    V(raddhn2, Raddhn2)            \
-    V(rsubhn, Rsubhn)              \
-    V(rsubhn2, Rsubhn2)            \
-    V(saba, Saba)                  \
-    V(sabal, Sabal)                \
-    V(sabal2, Sabal2)              \
-    V(sabd, Sabd)                  \
-    V(sabdl, Sabdl)                \
-    V(sabdl2, Sabdl2)              \
-    V(saddl, Saddl)                \
-    V(saddl2, Saddl2)              \
-    V(saddw, Saddw)                \
-    V(saddw2, Saddw2)              \
-    V(shadd, Shadd)                \
-    V(shsub, Shsub)                \
-    V(smax, Smax)                  \
-    V(smaxp, Smaxp)                \
-    V(smin, Smin)                  \
-    V(sminp, Sminp)                \
-    V(smlal, Smlal)                \
-    V(smlal2, Smlal2)              \
-    V(smlsl, Smlsl)                \
-    V(smlsl2, Smlsl2)              \
-    V(smull, Smull)                \
-    V(smull2, Smull2)              \
-    V(sqadd, Sqadd)                \
-    V(sqdmlal, Sqdmlal)            \
-    V(sqdmlal2, Sqdmlal2)          \
-    V(sqdmlsl, Sqdmlsl)            \
-    V(sqdmlsl2, Sqdmlsl2)          \
-    V(sqdmulh, Sqdmulh)            \
-    V(sqdmull, Sqdmull)            \
-    V(sqdmull2, Sqdmull2)          \
-    V(sqrdmulh, Sqrdmulh)          \
-    V(sqrshl, Sqrshl)              \
-    V(sqshl, Sqshl)                \
-    V(sqsub, Sqsub)                \
-    V(srhadd, Srhadd)              \
-    V(srshl, Srshl)                \
-    V(sshl, Sshl)                  \
-    V(ssubl, Ssubl)                \
-    V(ssubl2, Ssubl2)              \
-    V(ssubw, Ssubw)                \
-    V(ssubw2, Ssubw2)              \
-    V(sub, Sub)                    \
-    V(subhn, Subhn)                \
-    V(subhn2, Subhn2)              \
-    V(trn1, Trn1)                  \
-    V(trn2, Trn2)                  \
-    V(uaba, Uaba)                  \
-    V(uabal, Uabal)                \
-    V(uabal2, Uabal2)              \
-    V(uabd, Uabd)                  \
-    V(uabdl, Uabdl)                \
-    V(uabdl2, Uabdl2)              \
-    V(uaddl, Uaddl)                \
-    V(uaddl2, Uaddl2)              \
-    V(uaddw, Uaddw)                \
-    V(uaddw2, Uaddw2)              \
-    V(uhadd, Uhadd)                \
-    V(uhsub, Uhsub)                \
-    V(umax, Umax)                  \
-    V(umaxp, Umaxp)                \
-    V(umin, Umin)                  \
-    V(uminp, Uminp)                \
-    V(umlal, Umlal)                \
-    V(umlal2, Umlal2)              \
-    V(umlsl, Umlsl)                \
-    V(umlsl2, Umlsl2)              \
-    V(umull, Umull)                \
-    V(umull2, Umull2)              \
-    V(uqadd, Uqadd)                \
-    V(uqrshl, Uqrshl)              \
-    V(uqshl, Uqshl)                \
-    V(uqsub, Uqsub)                \
-    V(urhadd, Urhadd)              \
-    V(urshl, Urshl)                \
-    V(ushl, Ushl)                  \
-    V(usubl, Usubl)                \
-    V(usubl2, Usubl2)              \
-    V(usubw, Usubw)                \
-    V(usubw2, Usubw2)              \
-    V(uzp1, Uzp1)                  \
-    V(uzp2, Uzp2)                  \
-    V(zip1, Zip1)                  \
-    V(zip2, Zip2)
+// NEON 3 vector register instructions.
+#define NEON_3VREG_MACRO_LIST(V) \
+  V(add, Add)                    \
+  V(addhn, Addhn)                \
+  V(addhn2, Addhn2)              \
+  V(addp, Addp)                  \
+  V(and_, And)                   \
+  V(bic, Bic)                    \
+  V(bif, Bif)                    \
+  V(bit, Bit)                    \
+  V(bsl, Bsl)                    \
+  V(cmeq, Cmeq)                  \
+  V(cmge, Cmge)                  \
+  V(cmgt, Cmgt)                  \
+  V(cmhi, Cmhi)                  \
+  V(cmhs, Cmhs)                  \
+  V(cmtst, Cmtst)                \
+  V(eor, Eor)                    \
+  V(fabd, Fabd)                  \
+  V(facge, Facge)                \
+  V(facgt, Facgt)                \
+  V(faddp, Faddp)                \
+  V(fcmeq, Fcmeq)                \
+  V(fcmge, Fcmge)                \
+  V(fcmgt, Fcmgt)                \
+  V(fmaxnmp, Fmaxnmp)            \
+  V(fmaxp, Fmaxp)                \
+  V(fminnmp, Fminnmp)            \
+  V(fminp, Fminp)                \
+  V(fmla, Fmla)                  \
+  V(fmls, Fmls)                  \
+  V(fmulx, Fmulx)                \
+  V(frecps, Frecps)              \
+  V(frsqrts, Frsqrts)            \
+  V(mla, Mla)                    \
+  V(mls, Mls)                    \
+  V(mul, Mul)                    \
+  V(orn, Orn)                    \
+  V(orr, Orr)                    \
+  V(pmul, Pmul)                  \
+  V(pmull, Pmull)                \
+  V(pmull2, Pmull2)              \
+  V(raddhn, Raddhn)              \
+  V(raddhn2, Raddhn2)            \
+  V(rsubhn, Rsubhn)              \
+  V(rsubhn2, Rsubhn2)            \
+  V(saba, Saba)                  \
+  V(sabal, Sabal)                \
+  V(sabal2, Sabal2)              \
+  V(sabd, Sabd)                  \
+  V(sabdl, Sabdl)                \
+  V(sabdl2, Sabdl2)              \
+  V(saddl, Saddl)                \
+  V(saddl2, Saddl2)              \
+  V(saddw, Saddw)                \
+  V(saddw2, Saddw2)              \
+  V(shadd, Shadd)                \
+  V(shsub, Shsub)                \
+  V(smax, Smax)                  \
+  V(smaxp, Smaxp)                \
+  V(smin, Smin)                  \
+  V(sminp, Sminp)                \
+  V(smlal, Smlal)                \
+  V(smlal2, Smlal2)              \
+  V(smlsl, Smlsl)                \
+  V(smlsl2, Smlsl2)              \
+  V(smull, Smull)                \
+  V(smull2, Smull2)              \
+  V(sqadd, Sqadd)                \
+  V(sqdmlal, Sqdmlal)            \
+  V(sqdmlal2, Sqdmlal2)          \
+  V(sqdmlsl, Sqdmlsl)            \
+  V(sqdmlsl2, Sqdmlsl2)          \
+  V(sqdmulh, Sqdmulh)            \
+  V(sqdmull, Sqdmull)            \
+  V(sqdmull2, Sqdmull2)          \
+  V(sqrdmulh, Sqrdmulh)          \
+  V(sqrshl, Sqrshl)              \
+  V(sqshl, Sqshl)                \
+  V(sqsub, Sqsub)                \
+  V(srhadd, Srhadd)              \
+  V(srshl, Srshl)                \
+  V(sshl, Sshl)                  \
+  V(ssubl, Ssubl)                \
+  V(ssubl2, Ssubl2)              \
+  V(ssubw, Ssubw)                \
+  V(ssubw2, Ssubw2)              \
+  V(sub, Sub)                    \
+  V(subhn, Subhn)                \
+  V(subhn2, Subhn2)              \
+  V(trn1, Trn1)                  \
+  V(trn2, Trn2)                  \
+  V(uaba, Uaba)                  \
+  V(uabal, Uabal)                \
+  V(uabal2, Uabal2)              \
+  V(uabd, Uabd)                  \
+  V(uabdl, Uabdl)                \
+  V(uabdl2, Uabdl2)              \
+  V(uaddl, Uaddl)                \
+  V(uaddl2, Uaddl2)              \
+  V(uaddw, Uaddw)                \
+  V(uaddw2, Uaddw2)              \
+  V(uhadd, Uhadd)                \
+  V(uhsub, Uhsub)                \
+  V(umax, Umax)                  \
+  V(umaxp, Umaxp)                \
+  V(umin, Umin)                  \
+  V(uminp, Uminp)                \
+  V(umlal, Umlal)                \
+  V(umlal2, Umlal2)              \
+  V(umlsl, Umlsl)                \
+  V(umlsl2, Umlsl2)              \
+  V(umull, Umull)                \
+  V(umull2, Umull2)              \
+  V(uqadd, Uqadd)                \
+  V(uqrshl, Uqrshl)              \
+  V(uqshl, Uqshl)                \
+  V(uqsub, Uqsub)                \
+  V(urhadd, Urhadd)              \
+  V(urshl, Urshl)                \
+  V(ushl, Ushl)                  \
+  V(usubl, Usubl)                \
+  V(usubl2, Usubl2)              \
+  V(usubw, Usubw)                \
+  V(usubw2, Usubw2)              \
+  V(uzp1, Uzp1)                  \
+  V(uzp2, Uzp2)                  \
+  V(zip1, Zip1)                  \
+  V(zip2, Zip2)
 
-  #define DEFINE_MACRO_ASM_FUNC(ASM, MASM)   \
-  void MASM(const VRegister& vd,             \
-            const VRegister& vn,             \
-            const VRegister& vm) {           \
-    VIXL_ASSERT(allow_macro_instructions_);  \
-    SingleEmissionCheckScope guard(this);    \
-    ASM(vd, vn, vm);                         \
+#define DEFINE_MACRO_ASM_FUNC(ASM, MASM)                                     \
+  void MASM(const VRegister& vd, const VRegister& vn, const VRegister& vm) { \
+    VIXL_ASSERT(allow_macro_instructions_);                                  \
+    SingleEmissionCheckScope guard(this);                                    \
+    ASM(vd, vn, vm);                                                         \
   }
   NEON_3VREG_MACRO_LIST(DEFINE_MACRO_ASM_FUNC)
-  #undef DEFINE_MACRO_ASM_FUNC
+#undef DEFINE_MACRO_ASM_FUNC
 
-  // NEON 2 vector register instructions.
-  #define NEON_2VREG_MACRO_LIST(V) \
-    V(abs,     Abs)                \
-    V(addp,    Addp)               \
-    V(addv,    Addv)               \
-    V(cls,     Cls)                \
-    V(clz,     Clz)                \
-    V(cnt,     Cnt)                \
-    V(fabs,    Fabs)               \
-    V(faddp,   Faddp)              \
-    V(fcvtas,  Fcvtas)             \
-    V(fcvtau,  Fcvtau)             \
-    V(fcvtms,  Fcvtms)             \
-    V(fcvtmu,  Fcvtmu)             \
-    V(fcvtns,  Fcvtns)             \
-    V(fcvtnu,  Fcvtnu)             \
-    V(fcvtps,  Fcvtps)             \
-    V(fcvtpu,  Fcvtpu)             \
-    V(fmaxnmp, Fmaxnmp)            \
-    V(fmaxnmv, Fmaxnmv)            \
-    V(fmaxp,   Fmaxp)              \
-    V(fmaxv,   Fmaxv)              \
-    V(fminnmp, Fminnmp)            \
-    V(fminnmv, Fminnmv)            \
-    V(fminp,   Fminp)              \
-    V(fminv,   Fminv)              \
-    V(fneg,    Fneg)               \
-    V(frecpe,  Frecpe)             \
-    V(frecpx,  Frecpx)             \
-    V(frinta,  Frinta)             \
-    V(frinti,  Frinti)             \
-    V(frintm,  Frintm)             \
-    V(frintn,  Frintn)             \
-    V(frintp,  Frintp)             \
-    V(frintx,  Frintx)             \
-    V(frintz,  Frintz)             \
-    V(frsqrte, Frsqrte)            \
-    V(fsqrt,   Fsqrt)              \
-    V(mov,     Mov)                \
-    V(mvn,     Mvn)                \
-    V(neg,     Neg)                \
-    V(not_,    Not)                \
-    V(rbit,    Rbit)               \
-    V(rev16,   Rev16)              \
-    V(rev32,   Rev32)              \
-    V(rev64,   Rev64)              \
-    V(sadalp,  Sadalp)             \
-    V(saddlp,  Saddlp)             \
-    V(saddlv,  Saddlv)             \
-    V(smaxv,   Smaxv)              \
-    V(sminv,   Sminv)              \
-    V(sqabs,   Sqabs)              \
-    V(sqneg,   Sqneg)              \
-    V(sqxtn,   Sqxtn)              \
-    V(sqxtn2,  Sqxtn2)             \
-    V(sqxtun,  Sqxtun)             \
-    V(sqxtun2, Sqxtun2)            \
-    V(suqadd,  Suqadd)             \
-    V(sxtl,    Sxtl)               \
-    V(sxtl2,   Sxtl2)              \
-    V(uadalp,  Uadalp)             \
-    V(uaddlp,  Uaddlp)             \
-    V(uaddlv,  Uaddlv)             \
-    V(umaxv,   Umaxv)              \
-    V(uminv,   Uminv)              \
-    V(uqxtn,   Uqxtn)              \
-    V(uqxtn2,  Uqxtn2)             \
-    V(urecpe,  Urecpe)             \
-    V(ursqrte, Ursqrte)            \
-    V(usqadd,  Usqadd)             \
-    V(uxtl,    Uxtl)               \
-    V(uxtl2,   Uxtl2)              \
-    V(xtn,     Xtn)                \
-    V(xtn2,    Xtn2)
+// NEON 2 vector register instructions.
+#define NEON_2VREG_MACRO_LIST(V) \
+  V(abs, Abs)                    \
+  V(addp, Addp)                  \
+  V(addv, Addv)                  \
+  V(cls, Cls)                    \
+  V(clz, Clz)                    \
+  V(cnt, Cnt)                    \
+  V(fabs, Fabs)                  \
+  V(faddp, Faddp)                \
+  V(fcvtas, Fcvtas)              \
+  V(fcvtau, Fcvtau)              \
+  V(fcvtms, Fcvtms)              \
+  V(fcvtmu, Fcvtmu)              \
+  V(fcvtns, Fcvtns)              \
+  V(fcvtnu, Fcvtnu)              \
+  V(fcvtps, Fcvtps)              \
+  V(fcvtpu, Fcvtpu)              \
+  V(fmaxnmp, Fmaxnmp)            \
+  V(fmaxnmv, Fmaxnmv)            \
+  V(fmaxp, Fmaxp)                \
+  V(fmaxv, Fmaxv)                \
+  V(fminnmp, Fminnmp)            \
+  V(fminnmv, Fminnmv)            \
+  V(fminp, Fminp)                \
+  V(fminv, Fminv)                \
+  V(fneg, Fneg)                  \
+  V(frecpe, Frecpe)              \
+  V(frecpx, Frecpx)              \
+  V(frinta, Frinta)              \
+  V(frinti, Frinti)              \
+  V(frintm, Frintm)              \
+  V(frintn, Frintn)              \
+  V(frintp, Frintp)              \
+  V(frintx, Frintx)              \
+  V(frintz, Frintz)              \
+  V(frsqrte, Frsqrte)            \
+  V(fsqrt, Fsqrt)                \
+  V(mov, Mov)                    \
+  V(mvn, Mvn)                    \
+  V(neg, Neg)                    \
+  V(not_, Not)                   \
+  V(rbit, Rbit)                  \
+  V(rev16, Rev16)                \
+  V(rev32, Rev32)                \
+  V(rev64, Rev64)                \
+  V(sadalp, Sadalp)              \
+  V(saddlp, Saddlp)              \
+  V(saddlv, Saddlv)              \
+  V(smaxv, Smaxv)                \
+  V(sminv, Sminv)                \
+  V(sqabs, Sqabs)                \
+  V(sqneg, Sqneg)                \
+  V(sqxtn, Sqxtn)                \
+  V(sqxtn2, Sqxtn2)              \
+  V(sqxtun, Sqxtun)              \
+  V(sqxtun2, Sqxtun2)            \
+  V(suqadd, Suqadd)              \
+  V(sxtl, Sxtl)                  \
+  V(sxtl2, Sxtl2)                \
+  V(uadalp, Uadalp)              \
+  V(uaddlp, Uaddlp)              \
+  V(uaddlv, Uaddlv)              \
+  V(umaxv, Umaxv)                \
+  V(uminv, Uminv)                \
+  V(uqxtn, Uqxtn)                \
+  V(uqxtn2, Uqxtn2)              \
+  V(urecpe, Urecpe)              \
+  V(ursqrte, Ursqrte)            \
+  V(usqadd, Usqadd)              \
+  V(uxtl, Uxtl)                  \
+  V(uxtl2, Uxtl2)                \
+  V(xtn, Xtn)                    \
+  V(xtn2, Xtn2)
 
-  #define DEFINE_MACRO_ASM_FUNC(ASM, MASM)   \
-  void MASM(const VRegister& vd,             \
-            const VRegister& vn) {           \
-    VIXL_ASSERT(allow_macro_instructions_);  \
-    SingleEmissionCheckScope guard(this);    \
-    ASM(vd, vn);                             \
+#define DEFINE_MACRO_ASM_FUNC(ASM, MASM)                \
+  void MASM(const VRegister& vd, const VRegister& vn) { \
+    VIXL_ASSERT(allow_macro_instructions_);             \
+    SingleEmissionCheckScope guard(this);               \
+    ASM(vd, vn);                                        \
   }
   NEON_2VREG_MACRO_LIST(DEFINE_MACRO_ASM_FUNC)
-  #undef DEFINE_MACRO_ASM_FUNC
+#undef DEFINE_MACRO_ASM_FUNC
 
-  // NEON 2 vector register with immediate instructions.
-  #define NEON_2VREG_FPIMM_MACRO_LIST(V) \
-    V(fcmeq, Fcmeq)                      \
-    V(fcmge, Fcmge)                      \
-    V(fcmgt, Fcmgt)                      \
-    V(fcmle, Fcmle)                      \
-    V(fcmlt, Fcmlt)
+// NEON 2 vector register with immediate instructions.
+#define NEON_2VREG_FPIMM_MACRO_LIST(V) \
+  V(fcmeq, Fcmeq)                      \
+  V(fcmge, Fcmge)                      \
+  V(fcmgt, Fcmgt)                      \
+  V(fcmle, Fcmle)                      \
+  V(fcmlt, Fcmlt)
 
-  #define DEFINE_MACRO_ASM_FUNC(ASM, MASM)   \
-  void MASM(const VRegister& vd,             \
-            const VRegister& vn,             \
-            double imm) {                    \
-    VIXL_ASSERT(allow_macro_instructions_);  \
-    SingleEmissionCheckScope guard(this);    \
-    ASM(vd, vn, imm);                        \
+#define DEFINE_MACRO_ASM_FUNC(ASM, MASM)                            \
+  void MASM(const VRegister& vd, const VRegister& vn, double imm) { \
+    VIXL_ASSERT(allow_macro_instructions_);                         \
+    SingleEmissionCheckScope guard(this);                           \
+    ASM(vd, vn, imm);                                               \
   }
   NEON_2VREG_FPIMM_MACRO_LIST(DEFINE_MACRO_ASM_FUNC)
-  #undef DEFINE_MACRO_ASM_FUNC
+#undef DEFINE_MACRO_ASM_FUNC
 
-  // NEON by element instructions.
-  #define NEON_BYELEMENT_MACRO_LIST(V) \
-    V(fmul, Fmul)                      \
-    V(fmla, Fmla)                      \
-    V(fmls, Fmls)                      \
-    V(fmulx, Fmulx)                    \
-    V(mul, Mul)                        \
-    V(mla, Mla)                        \
-    V(mls, Mls)                        \
-    V(sqdmulh, Sqdmulh)                \
-    V(sqrdmulh, Sqrdmulh)              \
-    V(sqdmull,  Sqdmull)               \
-    V(sqdmull2, Sqdmull2)              \
-    V(sqdmlal,  Sqdmlal)               \
-    V(sqdmlal2, Sqdmlal2)              \
-    V(sqdmlsl,  Sqdmlsl)               \
-    V(sqdmlsl2, Sqdmlsl2)              \
-    V(smull,  Smull)                   \
-    V(smull2, Smull2)                  \
-    V(smlal,  Smlal)                   \
-    V(smlal2, Smlal2)                  \
-    V(smlsl,  Smlsl)                   \
-    V(smlsl2, Smlsl2)                  \
-    V(umull,  Umull)                   \
-    V(umull2, Umull2)                  \
-    V(umlal,  Umlal)                   \
-    V(umlal2, Umlal2)                  \
-    V(umlsl,  Umlsl)                   \
-    V(umlsl2, Umlsl2)
+// NEON by element instructions.
+#define NEON_BYELEMENT_MACRO_LIST(V) \
+  V(fmul, Fmul)                      \
+  V(fmla, Fmla)                      \
+  V(fmls, Fmls)                      \
+  V(fmulx, Fmulx)                    \
+  V(mul, Mul)                        \
+  V(mla, Mla)                        \
+  V(mls, Mls)                        \
+  V(sqdmulh, Sqdmulh)                \
+  V(sqrdmulh, Sqrdmulh)              \
+  V(sqdmull, Sqdmull)                \
+  V(sqdmull2, Sqdmull2)              \
+  V(sqdmlal, Sqdmlal)                \
+  V(sqdmlal2, Sqdmlal2)              \
+  V(sqdmlsl, Sqdmlsl)                \
+  V(sqdmlsl2, Sqdmlsl2)              \
+  V(smull, Smull)                    \
+  V(smull2, Smull2)                  \
+  V(smlal, Smlal)                    \
+  V(smlal2, Smlal2)                  \
+  V(smlsl, Smlsl)                    \
+  V(smlsl2, Smlsl2)                  \
+  V(umull, Umull)                    \
+  V(umull2, Umull2)                  \
+  V(umlal, Umlal)                    \
+  V(umlal2, Umlal2)                  \
+  V(umlsl, Umlsl)                    \
+  V(umlsl2, Umlsl2)
 
-  #define DEFINE_MACRO_ASM_FUNC(ASM, MASM)   \
-  void MASM(const VRegister& vd,             \
-            const VRegister& vn,             \
-            const VRegister& vm,             \
-            int vm_index                     \
-            ) {                              \
-    VIXL_ASSERT(allow_macro_instructions_);  \
-    SingleEmissionCheckScope guard(this);    \
-    ASM(vd, vn, vm, vm_index);               \
+#define DEFINE_MACRO_ASM_FUNC(ASM, MASM)    \
+  void MASM(const VRegister& vd,            \
+            const VRegister& vn,            \
+            const VRegister& vm,            \
+            int vm_index) {                 \
+    VIXL_ASSERT(allow_macro_instructions_); \
+    SingleEmissionCheckScope guard(this);   \
+    ASM(vd, vn, vm, vm_index);              \
   }
   NEON_BYELEMENT_MACRO_LIST(DEFINE_MACRO_ASM_FUNC)
-  #undef DEFINE_MACRO_ASM_FUNC
+#undef DEFINE_MACRO_ASM_FUNC
 
-  #define NEON_2VREG_SHIFT_MACRO_LIST(V) \
-    V(rshrn,     Rshrn)                  \
-    V(rshrn2,    Rshrn2)                 \
-    V(shl,       Shl)                    \
-    V(shll,      Shll)                   \
-    V(shll2,     Shll2)                  \
-    V(shrn,      Shrn)                   \
-    V(shrn2,     Shrn2)                  \
-    V(sli,       Sli)                    \
-    V(sqrshrn,   Sqrshrn)                \
-    V(sqrshrn2,  Sqrshrn2)               \
-    V(sqrshrun,  Sqrshrun)               \
-    V(sqrshrun2, Sqrshrun2)              \
-    V(sqshl,     Sqshl)                  \
-    V(sqshlu,    Sqshlu)                 \
-    V(sqshrn,    Sqshrn)                 \
-    V(sqshrn2,   Sqshrn2)                \
-    V(sqshrun,   Sqshrun)                \
-    V(sqshrun2,  Sqshrun2)               \
-    V(sri,       Sri)                    \
-    V(srshr,     Srshr)                  \
-    V(srsra,     Srsra)                  \
-    V(sshll,     Sshll)                  \
-    V(sshll2,    Sshll2)                 \
-    V(sshr,      Sshr)                   \
-    V(ssra,      Ssra)                   \
-    V(uqrshrn,   Uqrshrn)                \
-    V(uqrshrn2,  Uqrshrn2)               \
-    V(uqshl,     Uqshl)                  \
-    V(uqshrn,    Uqshrn)                 \
-    V(uqshrn2,   Uqshrn2)                \
-    V(urshr,     Urshr)                  \
-    V(ursra,     Ursra)                  \
-    V(ushll,     Ushll)                  \
-    V(ushll2,    Ushll2)                 \
-    V(ushr,      Ushr)                   \
-    V(usra,      Usra)                   \
+#define NEON_2VREG_SHIFT_MACRO_LIST(V) \
+  V(rshrn, Rshrn)                      \
+  V(rshrn2, Rshrn2)                    \
+  V(shl, Shl)                          \
+  V(shll, Shll)                        \
+  V(shll2, Shll2)                      \
+  V(shrn, Shrn)                        \
+  V(shrn2, Shrn2)                      \
+  V(sli, Sli)                          \
+  V(sqrshrn, Sqrshrn)                  \
+  V(sqrshrn2, Sqrshrn2)                \
+  V(sqrshrun, Sqrshrun)                \
+  V(sqrshrun2, Sqrshrun2)              \
+  V(sqshl, Sqshl)                      \
+  V(sqshlu, Sqshlu)                    \
+  V(sqshrn, Sqshrn)                    \
+  V(sqshrn2, Sqshrn2)                  \
+  V(sqshrun, Sqshrun)                  \
+  V(sqshrun2, Sqshrun2)                \
+  V(sri, Sri)                          \
+  V(srshr, Srshr)                      \
+  V(srsra, Srsra)                      \
+  V(sshll, Sshll)                      \
+  V(sshll2, Sshll2)                    \
+  V(sshr, Sshr)                        \
+  V(ssra, Ssra)                        \
+  V(uqrshrn, Uqrshrn)                  \
+  V(uqrshrn2, Uqrshrn2)                \
+  V(uqshl, Uqshl)                      \
+  V(uqshrn, Uqshrn)                    \
+  V(uqshrn2, Uqshrn2)                  \
+  V(urshr, Urshr)                      \
+  V(ursra, Ursra)                      \
+  V(ushll, Ushll)                      \
+  V(ushll2, Ushll2)                    \
+  V(ushr, Ushr)                        \
+  V(usra, Usra)
 
-  #define DEFINE_MACRO_ASM_FUNC(ASM, MASM)   \
-  void MASM(const VRegister& vd,             \
-            const VRegister& vn,             \
-            int shift) {                     \
-    VIXL_ASSERT(allow_macro_instructions_);  \
-    SingleEmissionCheckScope guard(this);    \
-    ASM(vd, vn, shift);                      \
+#define DEFINE_MACRO_ASM_FUNC(ASM, MASM)                           \
+  void MASM(const VRegister& vd, const VRegister& vn, int shift) { \
+    VIXL_ASSERT(allow_macro_instructions_);                        \
+    SingleEmissionCheckScope guard(this);                          \
+    ASM(vd, vn, shift);                                            \
   }
   NEON_2VREG_SHIFT_MACRO_LIST(DEFINE_MACRO_ASM_FUNC)
-  #undef DEFINE_MACRO_ASM_FUNC
+#undef DEFINE_MACRO_ASM_FUNC
 
-  void Bic(const VRegister& vd,
-           const int imm8,
-           const int left_shift = 0) {
+  void Bic(const VRegister& vd, const int imm8, const int left_shift = 0) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     bic(vd, imm8, left_shift);
   }
-  void Cmeq(const VRegister& vd,
-            const VRegister& vn,
-            int imm) {
+  void Cmeq(const VRegister& vd, const VRegister& vn, int imm) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     cmeq(vd, vn, imm);
   }
-  void Cmge(const VRegister& vd,
-            const VRegister& vn,
-            int imm) {
+  void Cmge(const VRegister& vd, const VRegister& vn, int imm) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     cmge(vd, vn, imm);
   }
-  void Cmgt(const VRegister& vd,
-            const VRegister& vn,
-            int imm) {
+  void Cmgt(const VRegister& vd, const VRegister& vn, int imm) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     cmgt(vd, vn, imm);
   }
-  void Cmle(const VRegister& vd,
-            const VRegister& vn,
-            int imm) {
+  void Cmle(const VRegister& vd, const VRegister& vn, int imm) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     cmle(vd, vn, imm);
   }
-  void Cmlt(const VRegister& vd,
-            const VRegister& vn,
-            int imm) {
+  void Cmlt(const VRegister& vd, const VRegister& vn, int imm) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     cmlt(vd, vn, imm);
   }
-  void Dup(const VRegister& vd,
-           const VRegister& vn,
-           int index) {
+  void Dup(const VRegister& vd, const VRegister& vn, int index) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     dup(vd, vn, index);
   }
-  void Dup(const VRegister& vd,
-           const Register& rn) {
+  void Dup(const VRegister& vd, const Register& rn) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     dup(vd, rn);
@@ -2514,22 +2480,17 @@
     SingleEmissionCheckScope guard(this);
     ins(vd, vd_index, vn, vn_index);
   }
-  void Ins(const VRegister& vd,
-           int vd_index,
-           const Register& rn) {
+  void Ins(const VRegister& vd, int vd_index, const Register& rn) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     ins(vd, vd_index, rn);
   }
-  void Ld1(const VRegister& vt,
-           const MemOperand& src) {
+  void Ld1(const VRegister& vt, const MemOperand& src) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     ld1(vt, src);
   }
-  void Ld1(const VRegister& vt,
-           const VRegister& vt2,
-           const MemOperand& src) {
+  void Ld1(const VRegister& vt, const VRegister& vt2, const MemOperand& src) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     ld1(vt, vt2, src);
@@ -2551,22 +2512,17 @@
     SingleEmissionCheckScope guard(this);
     ld1(vt, vt2, vt3, vt4, src);
   }
-  void Ld1(const VRegister& vt,
-           int lane,
-           const MemOperand& src) {
+  void Ld1(const VRegister& vt, int lane, const MemOperand& src) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     ld1(vt, lane, src);
   }
-  void Ld1r(const VRegister& vt,
-            const MemOperand& src) {
+  void Ld1r(const VRegister& vt, const MemOperand& src) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     ld1r(vt, src);
   }
-  void Ld2(const VRegister& vt,
-           const VRegister& vt2,
-           const MemOperand& src) {
+  void Ld2(const VRegister& vt, const VRegister& vt2, const MemOperand& src) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     ld2(vt, vt2, src);
@@ -2579,9 +2535,7 @@
     SingleEmissionCheckScope guard(this);
     ld2(vt, vt2, lane, src);
   }
-  void Ld2r(const VRegister& vt,
-            const VRegister& vt2,
-            const MemOperand& src) {
+  void Ld2r(const VRegister& vt, const VRegister& vt2, const MemOperand& src) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     ld2r(vt, vt2, src);
@@ -2606,7 +2560,7 @@
   void Ld3r(const VRegister& vt,
             const VRegister& vt2,
             const VRegister& vt3,
-           const MemOperand& src) {
+            const MemOperand& src) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     ld3r(vt, vt2, vt3, src);
@@ -2634,7 +2588,7 @@
             const VRegister& vt2,
             const VRegister& vt3,
             const VRegister& vt4,
-           const MemOperand& src) {
+            const MemOperand& src) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     ld4r(vt, vt2, vt3, vt4, src);
@@ -2647,23 +2601,17 @@
     SingleEmissionCheckScope guard(this);
     mov(vd, vd_index, vn, vn_index);
   }
-  void Mov(const VRegister& vd,
-           const VRegister& vn,
-           int index) {
+  void Mov(const VRegister& vd, const VRegister& vn, int index) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     mov(vd, vn, index);
   }
-  void Mov(const VRegister& vd,
-           int vd_index,
-           const Register& rn) {
+  void Mov(const VRegister& vd, int vd_index, const Register& rn) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     mov(vd, vd_index, rn);
   }
-  void Mov(const Register& rd,
-           const VRegister& vn,
-           int vn_index) {
+  void Mov(const Register& rd, const VRegister& vn, int vn_index) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     mov(rd, vn, vn_index);
@@ -2681,50 +2629,37 @@
     SingleEmissionCheckScope guard(this);
     mvni(vd, imm8, shift, shift_amount);
   }
-  void Orr(const VRegister& vd,
-           const int imm8,
-           const int left_shift = 0) {
+  void Orr(const VRegister& vd, const int imm8, const int left_shift = 0) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     orr(vd, imm8, left_shift);
   }
-  void Scvtf(const VRegister& vd,
-             const VRegister& vn,
-             int fbits = 0) {
+  void Scvtf(const VRegister& vd, const VRegister& vn, int fbits = 0) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     scvtf(vd, vn, fbits);
   }
-  void Ucvtf(const VRegister& vd,
-             const VRegister& vn,
-             int fbits = 0) {
+  void Ucvtf(const VRegister& vd, const VRegister& vn, int fbits = 0) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     ucvtf(vd, vn, fbits);
   }
-  void Fcvtzs(const VRegister& vd,
-              const VRegister& vn,
-              int fbits = 0) {
+  void Fcvtzs(const VRegister& vd, const VRegister& vn, int fbits = 0) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     fcvtzs(vd, vn, fbits);
   }
-  void Fcvtzu(const VRegister& vd,
-              const VRegister& vn,
-              int fbits = 0) {
+  void Fcvtzu(const VRegister& vd, const VRegister& vn, int fbits = 0) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     fcvtzu(vd, vn, fbits);
   }
-  void St1(const VRegister& vt,
-           const MemOperand& dst) {
+  void St1(const VRegister& vt, const MemOperand& dst) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     st1(vt, dst);
   }
-  void St1(const VRegister& vt,
-           const VRegister& vt2,
-           const MemOperand& dst) {
+  void St1(const VRegister& vt, const VRegister& vt2, const MemOperand& dst) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     st1(vt, vt2, dst);
@@ -2746,16 +2681,12 @@
     SingleEmissionCheckScope guard(this);
     st1(vt, vt2, vt3, vt4, dst);
   }
-  void St1(const VRegister& vt,
-           int lane,
-           const MemOperand& dst) {
+  void St1(const VRegister& vt, int lane, const MemOperand& dst) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     st1(vt, lane, dst);
   }
-  void St2(const VRegister& vt,
-           const VRegister& vt2,
-           const MemOperand& dst) {
+  void St2(const VRegister& vt, const VRegister& vt2, const MemOperand& dst) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     st2(vt, vt2, dst);
@@ -2804,87 +2735,68 @@
     SingleEmissionCheckScope guard(this);
     st4(vt, vt2, vt3, vt4, lane, dst);
   }
-  void Smov(const Register& rd,
-            const VRegister& vn,
-            int vn_index) {
+  void Smov(const Register& rd, const VRegister& vn, int vn_index) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     smov(rd, vn, vn_index);
   }
-  void Umov(const Register& rd,
-            const VRegister& vn,
-            int vn_index) {
+  void Umov(const Register& rd, const VRegister& vn, int vn_index) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     umov(rd, vn, vn_index);
   }
-  void Crc32b(const Register& rd,
-              const Register& rn,
-              const Register& rm) {
+  void Crc32b(const Register& rd, const Register& rn, const Register& rm) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     crc32b(rd, rn, rm);
   }
-  void Crc32h(const Register& rd,
-              const Register& rn,
-              const Register& rm) {
+  void Crc32h(const Register& rd, const Register& rn, const Register& rm) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     crc32h(rd, rn, rm);
   }
-  void Crc32w(const Register& rd,
-              const Register& rn,
-              const Register& rm) {
+  void Crc32w(const Register& rd, const Register& rn, const Register& rm) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     crc32w(rd, rn, rm);
   }
-  void Crc32x(const Register& rd,
-              const Register& rn,
-              const Register& rm) {
+  void Crc32x(const Register& rd, const Register& rn, const Register& rm) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     crc32x(rd, rn, rm);
   }
-  void Crc32cb(const Register& rd,
-               const Register& rn,
-               const Register& rm) {
+  void Crc32cb(const Register& rd, const Register& rn, const Register& rm) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     crc32cb(rd, rn, rm);
   }
-  void Crc32ch(const Register& rd,
-               const Register& rn,
-               const Register& rm) {
+  void Crc32ch(const Register& rd, const Register& rn, const Register& rm) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     crc32ch(rd, rn, rm);
   }
-  void Crc32cw(const Register& rd,
-               const Register& rn,
-               const Register& rm) {
+  void Crc32cw(const Register& rd, const Register& rn, const Register& rm) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     crc32cw(rd, rn, rm);
   }
-  void Crc32cx(const Register& rd,
-               const Register& rn,
-               const Register& rm) {
+  void Crc32cx(const Register& rd, const Register& rn, const Register& rm) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
     crc32cx(rd, rn, rm);
   }
 
-  template<typename T>
+  template <typename T>
   Literal<T>* CreateLiteralDestroyedWithPool(T value) {
     return new Literal<T>(value,
                           &literal_pool_,
                           RawLiteral::kDeletedOnPoolDestruction);
   }
 
-  template<typename T>
+  template <typename T>
   Literal<T>* CreateLiteralDestroyedWithPool(T high64, T low64) {
-    return new Literal<T>(high64, low64,
+    return new Literal<T>(high64,
+                          low64,
                           &literal_pool_,
                           RawLiteral::kDeletedOnPoolDestruction);
   }
@@ -2909,9 +2821,7 @@
     allow_macro_instructions_ = value;
   }
 
-  bool AllowMacroInstructions() const {
-    return allow_macro_instructions_;
-  }
+  bool AllowMacroInstructions() const { return allow_macro_instructions_; }
 #endif
 
   void SetAllowSimulatorInstructions(bool value) {
@@ -2939,17 +2849,11 @@
     ReleaseVeneerPool();
   }
 
-  size_t LiteralPoolSize() const {
-    return literal_pool_.Size();
-  }
+  size_t LiteralPoolSize() const { return literal_pool_.Size(); }
 
-  size_t LiteralPoolMaxSize() const {
-    return literal_pool_.MaxSize();
-  }
+  size_t LiteralPoolMaxSize() const { return literal_pool_.MaxSize(); }
 
-  size_t VeneerPoolMaxSize() const {
-    return veneer_pool_.MaxSize();
-  }
+  size_t VeneerPoolMaxSize() const { return veneer_pool_.MaxSize(); }
 
   // The number of unresolved branches that may require a veneer.
   int NumberOfPotentialVeneers() const {
@@ -2957,8 +2861,8 @@
   }
 
   ptrdiff_t NextCheckPoint() {
-    ptrdiff_t next_checkpoint_for_pools = std::min(literal_pool_.checkpoint(),
-                                                   veneer_pool_.checkpoint());
+    ptrdiff_t next_checkpoint_for_pools =
+        std::min(literal_pool_.checkpoint(), veneer_pool_.checkpoint());
     return std::min(next_checkpoint_for_pools, BufferEndOffset());
   }
 
@@ -2987,9 +2891,7 @@
   }
 
   // Return the current stack pointer, as set by SetStackPointer.
-  const Register& StackPointer() const {
-    return sp_;
-  }
+  const Register& StackPointer() const { return sp_; }
 
   CPURegList* TmpList() { return &tmp_list_; }
   CPURegList* FPTmpList() { return &fptmp_list_; }
@@ -3014,7 +2916,7 @@
   // a problem, preserve the important registers manually and then call
   // PrintfNoPreserve. Callee-saved registers are not used by Printf, and are
   // implicitly preserved.
-  void Printf(const char * format,
+  void Printf(const char* format,
               CPURegister arg0 = NoCPUReg,
               CPURegister arg1 = NoCPUReg,
               CPURegister arg2 = NoCPUReg,
@@ -3023,7 +2925,7 @@
   // Like Printf, but don't preserve any caller-saved registers, not even 'lr'.
   //
   // The return code from the system printf call will be returned in x0.
-  void PrintfNoPreserve(const char * format,
+  void PrintfNoPreserve(const char* format,
                         const CPURegister& arg0 = NoCPUReg,
                         const CPURegister& arg1 = NoCPUReg,
                         const CPURegister& arg2 = NoCPUReg,
@@ -3059,9 +2961,49 @@
   // the output data.
   void AnnotateInstrumentation(const char* marker_name);
 
-  LiteralPool* GetLiteralPool() {
-    return &literal_pool_;
-  }
+  LiteralPool* GetLiteralPool() { return &literal_pool_; }
+
+ protected:
+  // Helper used to query information about code generation and to generate
+  // code for `csel`.
+  // Here and for the related helpers below:
+  // - Code is generated when `masm` is not `NULL`.
+  // - On return and when set, `should_synthesise_left` and
+  //   `should_synthesise_right` will indicate whether `left` and `right`
+  //   should be synthesized in a temporary register.
+  static void CselHelper(MacroAssembler* masm,
+                         const Register& rd,
+                         Operand left,
+                         Operand right,
+                         Condition cond,
+                         bool* should_synthesise_left = NULL,
+                         bool* should_synthesise_right = NULL);
+
+  // The helper returns `true` if it can handle the specified arguments.
+  // Also see comments for `CselHelper()`.
+  static bool CselSubHelperTwoImmediates(MacroAssembler* masm,
+                                         const Register& rd,
+                                         int64_t left,
+                                         int64_t right,
+                                         Condition cond,
+                                         bool* should_synthesise_left,
+                                         bool* should_synthesise_right);
+
+  // See comments for `CselHelper()`.
+  static bool CselSubHelperTwoOrderedImmediates(MacroAssembler* masm,
+                                                const Register& rd,
+                                                int64_t left,
+                                                int64_t right,
+                                                Condition cond);
+
+  // See comments for `CselHelper()`.
+  static void CselSubHelperRightSmallImmediate(MacroAssembler* masm,
+                                               UseScratchRegisterScope* temps,
+                                               const Register& rd,
+                                               const Operand& left,
+                                               const Operand& right,
+                                               Condition cond,
+                                               bool* should_synthesise_left);
 
  private:
   // The actual Push and Pop implementations. These don't generate any code
@@ -3070,12 +3012,18 @@
   // registers.
   //
   // Note that size is per register, and is specified in bytes.
-  void PushHelper(int count, int size,
-                  const CPURegister& src0, const CPURegister& src1,
-                  const CPURegister& src2, const CPURegister& src3);
-  void PopHelper(int count, int size,
-                 const CPURegister& dst0, const CPURegister& dst1,
-                 const CPURegister& dst2, const CPURegister& dst3);
+  void PushHelper(int count,
+                  int size,
+                  const CPURegister& src0,
+                  const CPURegister& src1,
+                  const CPURegister& src2,
+                  const CPURegister& src3);
+  void PopHelper(int count,
+                 int size,
+                 const CPURegister& dst0,
+                 const CPURegister& dst1,
+                 const CPURegister& dst2,
+                 const CPURegister& dst3);
 
   void Movi16bitHelper(const VRegister& vd, uint64_t imm);
   void Movi32bitHelper(const VRegister& vd, uint64_t imm);
@@ -3088,10 +3036,7 @@
   void PrepareForPop(int count, int size);
 
   // The actual implementation of load and store operations for CPURegList.
-  enum LoadStoreCPURegListAction {
-    kLoad,
-    kStore
-  };
+  enum LoadStoreCPURegListAction { kLoad, kStore };
   void LoadStoreCPURegListHelper(LoadStoreCPURegListAction operation,
                                  CPURegList registers,
                                  const MemOperand& mem);
@@ -3162,10 +3107,7 @@
   InstructionAccurateScope(MacroAssembler* masm,
                            int64_t count,
                            AssertPolicy policy = kExactSize)
-      : CodeBufferCheckScope(masm,
-                             (count * kInstructionSize),
-                             kCheck,
-                             policy) {
+      : CodeBufferCheckScope(masm, (count * kInstructionSize), kCheck, policy) {
     VIXL_ASSERT(policy != kNoAssert);
 #ifdef VIXL_DEBUG
     old_allow_macro_instructions_ = masm->AllowMacroInstructions();
@@ -3193,9 +3135,7 @@
     masm_->BlockLiteralPool();
   }
 
-  ~BlockLiteralPoolScope() {
-    masm_->ReleaseLiteralPool();
-  }
+  ~BlockLiteralPoolScope() { masm_->ReleaseLiteralPool(); }
 
  private:
   MacroAssembler* masm_;
@@ -3208,9 +3148,7 @@
     masm_->BlockVeneerPool();
   }
 
-  ~BlockVeneerPoolScope() {
-    masm_->ReleaseVeneerPool();
-  }
+  ~BlockVeneerPoolScope() { masm_->ReleaseVeneerPool(); }
 
  private:
   MacroAssembler* masm_;
@@ -3223,9 +3161,7 @@
     masm_->BlockPools();
   }
 
-  ~BlockPoolsScope() {
-    masm_->ReleasePools();
-  }
+  ~BlockPoolsScope() { masm_->ReleasePools(); }
 
  private:
   MacroAssembler* masm_;
@@ -3241,12 +3177,12 @@
 // original state, even if the lists were modified by some other means.
 class UseScratchRegisterScope {
  public:
-  // This constructor implicitly calls the `Open` function to initialise the
-  // scope, so it is ready to use immediately after it has been constructed.
+  // This constructor implicitly calls `Open` to initialise the scope (`masm`
+  // must not be `NULL`), so it is ready to use immediately after it has been
+  // constructed.
   explicit UseScratchRegisterScope(MacroAssembler* masm);
-  // This constructor allows deferred and optional initialisation of the scope.
-  // The user is required to explicitly call the `Open` function before using
-  // the scope.
+  // This constructor does not implicitly initialise the scope. Instead,the user
+  // is required to explicitly call the `Open` function before using the scope.
   UseScratchRegisterScope();
   // This function performs the actual initialisation work.
   void Open(MacroAssembler* masm);
@@ -3318,22 +3254,19 @@
 
   static void ReleaseByCode(CPURegList* available, int code);
 
-  static void ReleaseByRegList(CPURegList* available,
-                               RegList regs);
+  static void ReleaseByRegList(CPURegList* available, RegList regs);
 
-  static void IncludeByRegList(CPURegList* available,
-                               RegList exclude);
+  static void IncludeByRegList(CPURegList* available, RegList exclude);
 
-  static void ExcludeByRegList(CPURegList* available,
-                               RegList exclude);
+  static void ExcludeByRegList(CPURegList* available, RegList exclude);
 
   // Available scratch registers.
-  CPURegList* available_;     // kRegister
-  CPURegList* availablefp_;   // kVRegister
+  CPURegList* available_;    // kRegister
+  CPURegList* availablefp_;  // kVRegister
 
   // The state of the available lists at the start of this scope.
-  RegList old_available_;     // kRegister
-  RegList old_availablefp_;   // kVRegister
+  RegList old_available_;    // kRegister
+  RegList old_availablefp_;  // kVRegister
 #ifdef VIXL_DEBUG
   bool initialised_;
 #endif
diff --git a/src/vixl/a64/simulator-a64.cc b/src/vixl/a64/simulator-a64.cc
index 69a664b..23da099 100644
--- a/src/vixl/a64/simulator-a64.cc
+++ b/src/vixl/a64/simulator-a64.cc
@@ -82,7 +82,7 @@
   stack_limit_ = stack_ + stack_protection_size_;
   // Configure the starting stack pointer.
   //  - Find the top of the stack.
-  byte * tos = stack_ + stack_size_;
+  byte* tos = stack_ + stack_size_;
   //  - There's a protection region at both ends of the stack.
   tos -= stack_protection_size_;
   //  - The stack pointer must be 16-byte aligned.
@@ -134,10 +134,12 @@
 
 
 void Simulator::Run() {
-  pc_modified_ = false;
+  // Flush any written registers before executing anything, so that
+  // manually-set registers are logged _before_ the first instruction.
+  LogAllWrittenRegisters();
+
   while (pc_ != kEndOfSimAddress) {
     ExecuteInstruction();
-    LogAllWrittenRegisters();
   }
 }
 
@@ -148,36 +150,40 @@
 }
 
 
-const char* Simulator::xreg_names[] = {
-"x0",  "x1",  "x2",  "x3",  "x4",  "x5",  "x6",  "x7",
-"x8",  "x9",  "x10", "x11", "x12", "x13", "x14", "x15",
-"x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
-"x24", "x25", "x26", "x27", "x28", "x29", "lr",  "xzr", "sp"};
+const char* Simulator::xreg_names[] = {"x0",  "x1",  "x2",  "x3",  "x4",  "x5",
+                                       "x6",  "x7",  "x8",  "x9",  "x10", "x11",
+                                       "x12", "x13", "x14", "x15", "x16", "x17",
+                                       "x18", "x19", "x20", "x21", "x22", "x23",
+                                       "x24", "x25", "x26", "x27", "x28", "x29",
+                                       "lr",  "xzr", "sp"};
 
-const char* Simulator::wreg_names[] = {
-"w0",  "w1",  "w2",  "w3",  "w4",  "w5",  "w6",  "w7",
-"w8",  "w9",  "w10", "w11", "w12", "w13", "w14", "w15",
-"w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23",
-"w24", "w25", "w26", "w27", "w28", "w29", "w30", "wzr", "wsp"};
+const char* Simulator::wreg_names[] = {"w0",  "w1",  "w2",  "w3",  "w4",  "w5",
+                                       "w6",  "w7",  "w8",  "w9",  "w10", "w11",
+                                       "w12", "w13", "w14", "w15", "w16", "w17",
+                                       "w18", "w19", "w20", "w21", "w22", "w23",
+                                       "w24", "w25", "w26", "w27", "w28", "w29",
+                                       "w30", "wzr", "wsp"};
 
-const char* Simulator::sreg_names[] = {
-"s0",  "s1",  "s2",  "s3",  "s4",  "s5",  "s6",  "s7",
-"s8",  "s9",  "s10", "s11", "s12", "s13", "s14", "s15",
-"s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
-"s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31"};
+const char* Simulator::sreg_names[] = {"s0",  "s1",  "s2",  "s3",  "s4",  "s5",
+                                       "s6",  "s7",  "s8",  "s9",  "s10", "s11",
+                                       "s12", "s13", "s14", "s15", "s16", "s17",
+                                       "s18", "s19", "s20", "s21", "s22", "s23",
+                                       "s24", "s25", "s26", "s27", "s28", "s29",
+                                       "s30", "s31"};
 
-const char* Simulator::dreg_names[] = {
-"d0",  "d1",  "d2",  "d3",  "d4",  "d5",  "d6",  "d7",
-"d8",  "d9",  "d10", "d11", "d12", "d13", "d14", "d15",
-"d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
-"d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31"};
+const char* Simulator::dreg_names[] = {"d0",  "d1",  "d2",  "d3",  "d4",  "d5",
+                                       "d6",  "d7",  "d8",  "d9",  "d10", "d11",
+                                       "d12", "d13", "d14", "d15", "d16", "d17",
+                                       "d18", "d19", "d20", "d21", "d22", "d23",
+                                       "d24", "d25", "d26", "d27", "d28", "d29",
+                                       "d30", "d31"};
 
-const char* Simulator::vreg_names[] = {
-"v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",
-"v8",  "v9",  "v10", "v11", "v12", "v13", "v14", "v15",
-"v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
-"v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"};
-
+const char* Simulator::vreg_names[] = {"v0",  "v1",  "v2",  "v3",  "v4",  "v5",
+                                       "v6",  "v7",  "v8",  "v9",  "v10", "v11",
+                                       "v12", "v13", "v14", "v15", "v16", "v17",
+                                       "v18", "v19", "v20", "v21", "v22", "v23",
+                                       "v24", "v25", "v26", "v27", "v28", "v29",
+                                       "v30", "v31"};
 
 
 const char* Simulator::WRegNameForCode(unsigned code, Reg31Mode mode) {
@@ -218,31 +224,31 @@
 }
 
 
-#define COLOUR(colour_code)       "\033[0;" colour_code "m"
-#define COLOUR_BOLD(colour_code)  "\033[1;" colour_code "m"
-#define NORMAL  ""
-#define GREY    "30"
-#define RED     "31"
-#define GREEN   "32"
-#define YELLOW  "33"
-#define BLUE    "34"
+#define COLOUR(colour_code) "\033[0;" colour_code "m"
+#define COLOUR_BOLD(colour_code) "\033[1;" colour_code "m"
+#define NORMAL ""
+#define GREY "30"
+#define RED "31"
+#define GREEN "32"
+#define YELLOW "33"
+#define BLUE "34"
 #define MAGENTA "35"
-#define CYAN    "36"
-#define WHITE   "37"
+#define CYAN "36"
+#define WHITE "37"
 void Simulator::set_coloured_trace(bool value) {
   coloured_trace_ = value;
 
-  clr_normal          = value ? COLOUR(NORMAL)        : "";
-  clr_flag_name       = value ? COLOUR_BOLD(WHITE)    : "";
-  clr_flag_value      = value ? COLOUR(NORMAL)        : "";
-  clr_reg_name        = value ? COLOUR_BOLD(CYAN)     : "";
-  clr_reg_value       = value ? COLOUR(CYAN)          : "";
-  clr_vreg_name       = value ? COLOUR_BOLD(MAGENTA)  : "";
-  clr_vreg_value      = value ? COLOUR(MAGENTA)       : "";
-  clr_memory_address  = value ? COLOUR_BOLD(BLUE)     : "";
-  clr_warning         = value ? COLOUR_BOLD(YELLOW)   : "";
-  clr_warning_message = value ? COLOUR(YELLOW)        : "";
-  clr_printf          = value ? COLOUR(GREEN)         : "";
+  clr_normal = value ? COLOUR(NORMAL) : "";
+  clr_flag_name = value ? COLOUR_BOLD(WHITE) : "";
+  clr_flag_value = value ? COLOUR(NORMAL) : "";
+  clr_reg_name = value ? COLOUR_BOLD(CYAN) : "";
+  clr_reg_value = value ? COLOUR(CYAN) : "";
+  clr_vreg_name = value ? COLOUR_BOLD(MAGENTA) : "";
+  clr_vreg_value = value ? COLOUR(MAGENTA) : "";
+  clr_memory_address = value ? COLOUR_BOLD(BLUE) : "";
+  clr_warning = value ? COLOUR_BOLD(YELLOW) : "";
+  clr_warning_message = value ? COLOUR(YELLOW) : "";
+  clr_printf = value ? COLOUR(GREEN) : "";
 }
 
 
@@ -337,8 +343,7 @@
         value &= kWRegMask;
       }
       return (static_cast<uint64_t>(value) >> amount) |
-             ((value & ((INT64_C(1) << amount) - 1)) <<
-              (reg_size - amount));
+             ((value & ((INT64_C(1) << amount) - 1)) << (reg_size - amount));
     }
     default:
       VIXL_UNIMPLEMENTED();
@@ -414,19 +419,37 @@
   uint32_t format = 0;
   if (reg_size != lane_size) {
     switch (reg_size) {
-      default: VIXL_UNREACHABLE(); break;
-      case kQRegSizeInBytes: format = kPrintRegAsQVector; break;
-      case kDRegSizeInBytes: format = kPrintRegAsDVector; break;
+      default:
+        VIXL_UNREACHABLE();
+        break;
+      case kQRegSizeInBytes:
+        format = kPrintRegAsQVector;
+        break;
+      case kDRegSizeInBytes:
+        format = kPrintRegAsDVector;
+        break;
     }
   }
 
   switch (lane_size) {
-    default: VIXL_UNREACHABLE(); break;
-    case kQRegSizeInBytes: format |= kPrintReg1Q; break;
-    case kDRegSizeInBytes: format |= kPrintReg1D; break;
-    case kSRegSizeInBytes: format |= kPrintReg1S; break;
-    case kHRegSizeInBytes: format |= kPrintReg1H; break;
-    case kBRegSizeInBytes: format |= kPrintReg1B; break;
+    default:
+      VIXL_UNREACHABLE();
+      break;
+    case kQRegSizeInBytes:
+      format |= kPrintReg1Q;
+      break;
+    case kDRegSizeInBytes:
+      format |= kPrintReg1D;
+      break;
+    case kSRegSizeInBytes:
+      format |= kPrintReg1S;
+      break;
+    case kHRegSizeInBytes:
+      format |= kPrintReg1H;
+      break;
+    case kBRegSizeInBytes:
+      format |= kPrintReg1B;
+      break;
   }
   // These sizes would be duplicate case labels.
   VIXL_STATIC_ASSERT(kXRegSizeInBytes == kDRegSizeInBytes);
@@ -441,15 +464,57 @@
 Simulator::PrintRegisterFormat Simulator::GetPrintRegisterFormat(
     VectorFormat vform) {
   switch (vform) {
-    default: VIXL_UNREACHABLE(); return kPrintReg16B;
-    case kFormat16B: return kPrintReg16B;
-    case kFormat8B: return kPrintReg8B;
-    case kFormat8H: return kPrintReg8H;
-    case kFormat4H: return kPrintReg4H;
-    case kFormat4S: return kPrintReg4S;
-    case kFormat2S: return kPrintReg2S;
-    case kFormat2D: return kPrintReg2D;
-    case kFormat1D: return kPrintReg1D;
+    default:
+      VIXL_UNREACHABLE();
+      return kPrintReg16B;
+    case kFormat16B:
+      return kPrintReg16B;
+    case kFormat8B:
+      return kPrintReg8B;
+    case kFormat8H:
+      return kPrintReg8H;
+    case kFormat4H:
+      return kPrintReg4H;
+    case kFormat4S:
+      return kPrintReg4S;
+    case kFormat2S:
+      return kPrintReg2S;
+    case kFormat2D:
+      return kPrintReg2D;
+    case kFormat1D:
+      return kPrintReg1D;
+
+    case kFormatB:
+      return kPrintReg1B;
+    case kFormatH:
+      return kPrintReg1H;
+    case kFormatS:
+      return kPrintReg1S;
+    case kFormatD:
+      return kPrintReg1D;
+  }
+}
+
+
+Simulator::PrintRegisterFormat Simulator::GetPrintRegisterFormatFP(
+    VectorFormat vform) {
+  switch (vform) {
+    default:
+      VIXL_UNREACHABLE();
+      return kPrintReg16B;
+    case kFormat4S:
+      return kPrintReg4SFP;
+    case kFormat2S:
+      return kPrintReg2SFP;
+    case kFormat2D:
+      return kPrintReg2DFP;
+    case kFormat1D:
+      return kPrintReg1DFP;
+
+    case kFormatS:
+      return kPrintReg1SFP;
+    case kFormatD:
+      return kPrintReg1DFP;
   }
 }
 
@@ -502,7 +567,8 @@
 //
 // No newline is printed. This allows the caller to print more details (such as
 // a memory access annotation).
-void Simulator::PrintRegisterRawHelper(unsigned code, Reg31Mode r31mode,
+void Simulator::PrintRegisterRawHelper(unsigned code,
+                                       Reg31Mode r31mode,
                                        int size_in_bytes) {
   // The template for all supported sizes.
   //   "# x{code}: 0xffeeddccbbaa9988"
@@ -511,11 +577,15 @@
   //   "# w{code}<7:0>:          0x88"
   unsigned padding_chars = (kXRegSizeInBytes - size_in_bytes) * 2;
 
-  const char * name = "";
-  const char * suffix = "";
+  const char* name = "";
+  const char* suffix = "";
   switch (size_in_bytes) {
-    case kXRegSizeInBytes: name = XRegNameForCode(code, r31mode); break;
-    case kWRegSizeInBytes: name = WRegNameForCode(code, r31mode); break;
+    case kXRegSizeInBytes:
+      name = XRegNameForCode(code, r31mode);
+      break;
+    case kWRegSizeInBytes:
+      name = WRegNameForCode(code, r31mode);
+      break;
     case 2:
       name = WRegNameForCode(code, r31mode);
       suffix = "<15:0>";
@@ -543,8 +613,12 @@
   VIXL_STATIC_ASSERT(sizeof(bits) == kXRegSizeInBytes);
 
   int chars = size_in_bytes * 2;
-  fprintf(stream_, "%s0x%0*" PRIx64 "%s",
-          clr_reg_value, chars, bits, clr_normal);
+  fprintf(stream_,
+          "%s0x%0*" PRIx64 "%s",
+          clr_reg_value,
+          chars,
+          bits,
+          clr_normal);
 }
 
 
@@ -578,8 +652,11 @@
   //   "# v{code}: 0xffeeddccbbaa99887766554433221100".
   // An example with bytes=4 and lsb=8:
   //   "# v{code}:         0xbbaa9988                ".
-  fprintf(stream_, "# %s%5s: %s",
-          clr_vreg_name, VRegNameForCode(code), clr_vreg_value);
+  fprintf(stream_,
+          "# %s%5s: %s",
+          clr_vreg_name,
+          VRegNameForCode(code),
+          clr_vreg_value);
 
   int msb = lsb + bytes - 1;
   int byte = kQRegSizeInBytes - 1;
@@ -632,9 +709,9 @@
   // For vector types, "..." is used to represent one or more omitted lanes.
   //   " (..., {value}, {value}, ...)"
   if ((lane_count == 1) && (rightmost_lane == 0)) {
-    const char * name =
-        (lane_size_in_bytes == kSRegSizeInBytes) ? SRegNameForCode(code)
-                                                 : DRegNameForCode(code);
+    const char* name = (lane_size_in_bytes == kSRegSizeInBytes)
+                           ? SRegNameForCode(code)
+                           : DRegNameForCode(code);
     fprintf(stream_, " (%s%s: ", clr_vreg_name, name);
   } else {
     if (msb < (kQRegSizeInBytes - 1)) {
@@ -645,12 +722,12 @@
   }
 
   // Print the list of values.
-  const char * separator = "";
+  const char* separator = "";
   int leftmost_lane = rightmost_lane + lane_count - 1;
   for (int lane = leftmost_lane; lane >= rightmost_lane; lane--) {
-    double value =
-        (lane_size_in_bytes == kSRegSizeInBytes) ? vreg(code).Get<float>(lane)
-                                                 : vreg(code).Get<double>(lane);
+    double value = (lane_size_in_bytes == kSRegSizeInBytes)
+                       ? vreg(code).Get<float>(lane)
+                       : vreg(code).Get<double>(lane);
     fprintf(stream_, "%s%s%#g%s", separator, clr_vreg_value, value, clr_normal);
     separator = ", ";
   }
@@ -699,23 +776,30 @@
 void Simulator::PrintSystemRegister(SystemRegister id) {
   switch (id) {
     case NZCV:
-      fprintf(stream_, "# %sNZCV: %sN:%d Z:%d C:%d V:%d%s\n",
-              clr_flag_name, clr_flag_value,
-              nzcv().N(), nzcv().Z(), nzcv().C(), nzcv().V(),
+      fprintf(stream_,
+              "# %sNZCV: %sN:%d Z:%d C:%d V:%d%s\n",
+              clr_flag_name,
+              clr_flag_value,
+              nzcv().N(),
+              nzcv().Z(),
+              nzcv().C(),
+              nzcv().V(),
               clr_normal);
       break;
     case FPCR: {
-      static const char * rmode[] = {
-        "0b00 (Round to Nearest)",
-        "0b01 (Round towards Plus Infinity)",
-        "0b10 (Round towards Minus Infinity)",
-        "0b11 (Round towards Zero)"
-      };
+      static const char* rmode[] = {"0b00 (Round to Nearest)",
+                                    "0b01 (Round towards Plus Infinity)",
+                                    "0b10 (Round towards Minus Infinity)",
+                                    "0b11 (Round towards Zero)"};
       VIXL_ASSERT(fpcr().RMode() < (sizeof(rmode) / sizeof(rmode[0])));
       fprintf(stream_,
               "# %sFPCR: %sAHP:%d DN:%d FZ:%d RMode:%s%s\n",
-              clr_flag_name, clr_flag_value,
-              fpcr().AHP(), fpcr().DN(), fpcr().FZ(), rmode[fpcr().RMode()],
+              clr_flag_name,
+              clr_flag_value,
+              fpcr().AHP(),
+              fpcr().DN(),
+              fpcr().FZ(),
+              rmode[fpcr().RMode()],
               clr_normal);
       break;
     }
@@ -734,8 +818,11 @@
 
   // The template is "# {reg}: 0x{value} <- {address}".
   PrintRegisterRawHelper(reg_code, Reg31IsZeroRegister);
-  fprintf(stream_, " <- %s0x%016" PRIxPTR "%s\n",
-          clr_memory_address, address, clr_normal);
+  fprintf(stream_,
+          " <- %s0x%016" PRIxPTR "%s\n",
+          clr_memory_address,
+          address,
+          clr_normal);
 }
 
 
@@ -748,11 +835,16 @@
   // The template is "# v{code}: 0x{rawbits} <- address".
   PrintVRegisterRawHelper(reg_code);
   if (format & kPrintRegAsFP) {
-    PrintVRegisterFPHelper(reg_code, GetPrintRegLaneSizeInBytes(format),
-                           GetPrintRegLaneCount(format), lane);
+    PrintVRegisterFPHelper(reg_code,
+                           GetPrintRegLaneSizeInBytes(format),
+                           GetPrintRegLaneCount(format),
+                           lane);
   }
-  fprintf(stream_, " <- %s0x%016" PRIxPTR "%s\n",
-          clr_memory_address, address, clr_normal);
+  fprintf(stream_,
+          " <- %s0x%016" PRIxPTR "%s\n",
+          clr_memory_address,
+          address,
+          clr_normal);
 }
 
 
@@ -763,10 +855,14 @@
 
   // The template is "# v{code}: 0x{value} -> {address}". To keep the trace tidy
   // and readable, the value is aligned with the values in the register trace.
-  PrintRegisterRawHelper(reg_code, Reg31IsZeroRegister,
+  PrintRegisterRawHelper(reg_code,
+                         Reg31IsZeroRegister,
                          GetPrintRegSizeInBytes(format));
-  fprintf(stream_, " -> %s0x%016" PRIxPTR "%s\n",
-          clr_memory_address, address, clr_normal);
+  fprintf(stream_,
+          " -> %s0x%016" PRIxPTR "%s\n",
+          clr_memory_address,
+          address,
+          clr_normal);
 }
 
 
@@ -789,8 +885,11 @@
   if (format & kPrintRegAsFP) {
     PrintVRegisterFPHelper(reg_code, lane_size, lane_count, lane);
   }
-  fprintf(stream_, " -> %s0x%016" PRIxPTR "%s\n",
-          clr_memory_address, address, clr_normal);
+  fprintf(stream_,
+          " -> %s0x%016" PRIxPTR "%s\n",
+          clr_memory_address,
+          address,
+          clr_normal);
 }
 
 
@@ -798,14 +897,16 @@
 
 void Simulator::VisitUnimplemented(const Instruction* instr) {
   printf("Unimplemented instruction at %p: 0x%08" PRIx32 "\n",
-         reinterpret_cast<const void*>(instr), instr->InstructionBits());
+         reinterpret_cast<const void*>(instr),
+         instr->InstructionBits());
   VIXL_UNIMPLEMENTED();
 }
 
 
 void Simulator::VisitUnallocated(const Instruction* instr) {
   printf("Unallocated instruction at %p: 0x%08" PRIx32 "\n",
-         reinterpret_cast<const void*>(instr), instr->InstructionBits());
+         reinterpret_cast<const void*>(instr),
+         instr->InstructionBits());
   VIXL_UNIMPLEMENTED();
 }
 
@@ -826,7 +927,8 @@
     case B:
       set_pc(instr->ImmPCOffsetTarget());
       break;
-    default: VIXL_UNREACHABLE();
+    default:
+      VIXL_UNREACHABLE();
   }
 }
 
@@ -847,21 +949,29 @@
       set_lr(instr->NextInstruction());
       VIXL_FALLTHROUGH();
     case BR:
-    case RET: set_pc(target); break;
-    default: VIXL_UNREACHABLE();
+    case RET:
+      set_pc(target);
+      break;
+    default:
+      VIXL_UNREACHABLE();
   }
 }
 
 
 void Simulator::VisitTestBranch(const Instruction* instr) {
-  unsigned bit_pos = (instr->ImmTestBranchBit5() << 5) |
-                     instr->ImmTestBranchBit40();
+  unsigned bit_pos =
+      (instr->ImmTestBranchBit5() << 5) | instr->ImmTestBranchBit40();
   bool bit_zero = ((xreg(instr->Rt()) >> bit_pos) & 1) == 0;
   bool take_branch = false;
   switch (instr->Mask(TestBranchMask)) {
-    case TBZ: take_branch = bit_zero; break;
-    case TBNZ: take_branch = !bit_zero; break;
-    default: VIXL_UNIMPLEMENTED();
+    case TBZ:
+      take_branch = bit_zero;
+      break;
+    case TBNZ:
+      take_branch = !bit_zero;
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
   }
   if (take_branch) {
     set_pc(instr->ImmPCOffsetTarget());
@@ -873,11 +983,20 @@
   unsigned rt = instr->Rt();
   bool take_branch = false;
   switch (instr->Mask(CompareBranchMask)) {
-    case CBZ_w: take_branch = (wreg(rt) == 0); break;
-    case CBZ_x: take_branch = (xreg(rt) == 0); break;
-    case CBNZ_w: take_branch = (wreg(rt) != 0); break;
-    case CBNZ_x: take_branch = (xreg(rt) != 0); break;
-    default: VIXL_UNIMPLEMENTED();
+    case CBZ_w:
+      take_branch = (wreg(rt) == 0);
+      break;
+    case CBZ_x:
+      take_branch = (xreg(rt) == 0);
+      break;
+    case CBNZ_w:
+      take_branch = (wreg(rt) != 0);
+      break;
+    case CBNZ_x:
+      take_branch = (xreg(rt) != 0);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
   }
   if (take_branch) {
     set_pc(instr->ImmPCOffsetTarget());
@@ -909,7 +1028,8 @@
                              1);
       break;
     }
-    default: VIXL_UNREACHABLE();
+    default:
+      VIXL_UNREACHABLE();
   }
 
   set_reg(reg_size, instr->Rd(), new_val, LogRegWrites, instr->RdMode());
@@ -965,7 +1085,9 @@
   unsigned reg_size = instr->SixtyFourBits() ? kXRegSize : kWRegSize;
   Shift shift_type = static_cast<Shift>(instr->ShiftDP());
   unsigned shift_amount = instr->ImmDPShift();
-  int64_t op2 = ShiftOperand(reg_size, reg(reg_size, instr->Rm()), shift_type,
+  int64_t op2 = ShiftOperand(reg_size,
+                             reg(reg_size, instr->Rm()),
+                             shift_type,
                              shift_amount);
   if (instr->Mask(NOT) == NOT) {
     op2 = ~op2;
@@ -988,10 +1110,18 @@
   // Switch on the logical operation, stripping out the NOT bit, as it has a
   // different meaning for logical immediate instructions.
   switch (instr->Mask(LogicalOpMask & ~NOT)) {
-    case ANDS: update_flags = true; VIXL_FALLTHROUGH();
-    case AND: result = op1 & op2; break;
-    case ORR: result = op1 | op2; break;
-    case EOR: result = op1 ^ op2; break;
+    case ANDS:
+      update_flags = true;
+      VIXL_FALLTHROUGH();
+    case AND:
+      result = op1 & op2;
+      break;
+    case ORR:
+      result = op1 | op2;
+      break;
+    case EOR:
+      result = op1 ^ op2;
+      break;
     default:
       VIXL_UNIMPLEMENTED();
   }
@@ -1067,13 +1197,11 @@
   VIXL_ASSERT((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX));
   unsigned shift_amount = instr->ImmShiftLS() * instr->SizeLS();
 
-  int64_t offset = ExtendValue(kXRegSize, xreg(instr->Rm()), ext,
-                               shift_amount);
+  int64_t offset = ExtendValue(kXRegSize, xreg(instr->Rm()), ext, shift_amount);
   LoadStoreHelper(instr, offset, Offset);
 }
 
 
-
 void Simulator::LoadStoreHelper(const Instruction* instr,
                                 int64_t offset,
                                 AddrMode addrmode) {
@@ -1083,48 +1211,82 @@
   LoadStoreOp op = static_cast<LoadStoreOp>(instr->Mask(LoadStoreMask));
   switch (op) {
     case LDRB_w:
-      set_wreg(srcdst, Memory::Read<uint8_t>(address), NoRegLog); break;
+      set_wreg(srcdst, Memory::Read<uint8_t>(address), NoRegLog);
+      break;
     case LDRH_w:
-      set_wreg(srcdst, Memory::Read<uint16_t>(address), NoRegLog); break;
+      set_wreg(srcdst, Memory::Read<uint16_t>(address), NoRegLog);
+      break;
     case LDR_w:
-      set_wreg(srcdst, Memory::Read<uint32_t>(address), NoRegLog); break;
+      set_wreg(srcdst, Memory::Read<uint32_t>(address), NoRegLog);
+      break;
     case LDR_x:
-      set_xreg(srcdst, Memory::Read<uint64_t>(address), NoRegLog); break;
+      set_xreg(srcdst, Memory::Read<uint64_t>(address), NoRegLog);
+      break;
     case LDRSB_w:
-      set_wreg(srcdst, Memory::Read<int8_t>(address), NoRegLog); break;
+      set_wreg(srcdst, Memory::Read<int8_t>(address), NoRegLog);
+      break;
     case LDRSH_w:
-      set_wreg(srcdst, Memory::Read<int16_t>(address), NoRegLog); break;
+      set_wreg(srcdst, Memory::Read<int16_t>(address), NoRegLog);
+      break;
     case LDRSB_x:
-      set_xreg(srcdst, Memory::Read<int8_t>(address), NoRegLog); break;
+      set_xreg(srcdst, Memory::Read<int8_t>(address), NoRegLog);
+      break;
     case LDRSH_x:
-      set_xreg(srcdst, Memory::Read<int16_t>(address), NoRegLog); break;
+      set_xreg(srcdst, Memory::Read<int16_t>(address), NoRegLog);
+      break;
     case LDRSW_x:
-      set_xreg(srcdst, Memory::Read<int32_t>(address), NoRegLog); break;
+      set_xreg(srcdst, Memory::Read<int32_t>(address), NoRegLog);
+      break;
     case LDR_b:
-      set_breg(srcdst, Memory::Read<uint8_t>(address), NoRegLog); break;
+      set_breg(srcdst, Memory::Read<uint8_t>(address), NoRegLog);
+      break;
     case LDR_h:
-      set_hreg(srcdst, Memory::Read<uint16_t>(address), NoRegLog); break;
+      set_hreg(srcdst, Memory::Read<uint16_t>(address), NoRegLog);
+      break;
     case LDR_s:
-      set_sreg(srcdst, Memory::Read<float>(address), NoRegLog); break;
+      set_sreg(srcdst, Memory::Read<float>(address), NoRegLog);
+      break;
     case LDR_d:
-      set_dreg(srcdst, Memory::Read<double>(address), NoRegLog); break;
+      set_dreg(srcdst, Memory::Read<double>(address), NoRegLog);
+      break;
     case LDR_q:
-      set_qreg(srcdst, Memory::Read<qreg_t>(address), NoRegLog); break;
+      set_qreg(srcdst, Memory::Read<qreg_t>(address), NoRegLog);
+      break;
 
-    case STRB_w:  Memory::Write<uint8_t>(address, wreg(srcdst)); break;
-    case STRH_w:  Memory::Write<uint16_t>(address, wreg(srcdst)); break;
-    case STR_w:   Memory::Write<uint32_t>(address, wreg(srcdst)); break;
-    case STR_x:   Memory::Write<uint64_t>(address, xreg(srcdst)); break;
-    case STR_b:   Memory::Write<uint8_t>(address, breg(srcdst)); break;
-    case STR_h:   Memory::Write<uint16_t>(address, hreg(srcdst)); break;
-    case STR_s:   Memory::Write<float>(address, sreg(srcdst)); break;
-    case STR_d:   Memory::Write<double>(address, dreg(srcdst)); break;
-    case STR_q:   Memory::Write<qreg_t>(address, qreg(srcdst)); break;
+    case STRB_w:
+      Memory::Write<uint8_t>(address, wreg(srcdst));
+      break;
+    case STRH_w:
+      Memory::Write<uint16_t>(address, wreg(srcdst));
+      break;
+    case STR_w:
+      Memory::Write<uint32_t>(address, wreg(srcdst));
+      break;
+    case STR_x:
+      Memory::Write<uint64_t>(address, xreg(srcdst));
+      break;
+    case STR_b:
+      Memory::Write<uint8_t>(address, breg(srcdst));
+      break;
+    case STR_h:
+      Memory::Write<uint16_t>(address, hreg(srcdst));
+      break;
+    case STR_s:
+      Memory::Write<float>(address, sreg(srcdst));
+      break;
+    case STR_d:
+      Memory::Write<double>(address, dreg(srcdst));
+      break;
+    case STR_q:
+      Memory::Write<qreg_t>(address, qreg(srcdst));
+      break;
 
     // Ignore prfm hint instructions.
-    case PRFM: break;
+    case PRFM:
+      break;
 
-    default: VIXL_UNIMPLEMENTED();
+    default:
+      VIXL_UNIMPLEMENTED();
   }
 
   unsigned access_size = 1 << instr->SizeLS();
@@ -1136,7 +1298,7 @@
     } else {
       LogRead(address, srcdst, GetPrintRegisterFormatForSize(access_size));
     }
-  } else {
+  } else if (instr->IsStore()) {
     if ((op == STR_s) || (op == STR_d)) {
       LogVWrite(address, srcdst, GetPrintRegisterFormatForSizeFP(access_size));
     } else if ((op == STR_b) || (op == STR_h) || (op == STR_q)) {
@@ -1144,6 +1306,8 @@
     } else {
       LogWrite(address, srcdst, GetPrintRegisterFormatForSize(access_size));
     }
+  } else {
+    VIXL_ASSERT(op == PRFM);
   }
 
   local_monitor_.MaybeClear();
@@ -1180,7 +1344,7 @@
   uintptr_t address2 = address + element_size;
 
   LoadStorePairOp op =
-    static_cast<LoadStorePairOp>(instr->Mask(LoadStorePairMask));
+      static_cast<LoadStorePairOp>(instr->Mask(LoadStorePairMask));
 
   // 'rt' and 'rt2' can only be aliased for stores.
   VIXL_ASSERT(((op & LoadStorePairLBit) == 0) || (rt != rt2));
@@ -1243,7 +1407,8 @@
       Memory::Write<qreg_t>(address2, qreg(rt2));
       break;
     }
-    default: VIXL_UNREACHABLE();
+    default:
+      VIXL_UNREACHABLE();
   }
 
   // Print a detailed trace (including the memory address) instead of the basic
@@ -1278,11 +1443,13 @@
 
 void Simulator::PrintExclusiveAccessWarning() {
   if (print_exclusive_access_warning_) {
-    fprintf(
-        stderr,
-        "%sWARNING:%s VIXL simulator support for load-/store-/clear-exclusive "
-        "instructions is limited. Refer to the README for details.%s\n",
-        clr_warning, clr_warning_message, clr_normal);
+    fprintf(stderr,
+            "%sWARNING:%s VIXL simulator support for "
+            "load-/store-/clear-exclusive "
+            "instructions is limited. Refer to the README for details.%s\n",
+            clr_warning,
+            clr_warning_message,
+            clr_normal);
     print_exclusive_access_warning_ = false;
   }
 }
@@ -1374,7 +1541,8 @@
 
     LogRead(address, rt, GetPrintRegisterFormatForSize(element_size));
     if (is_pair) {
-      LogRead(address + element_size, rt2,
+      LogRead(address + element_size,
+              rt2,
               GetPrintRegisterFormatForSize(element_size));
     }
   } else {
@@ -1434,7 +1602,8 @@
 
       LogWrite(address, rt, GetPrintRegisterFormatForSize(element_size));
       if (is_pair) {
-        LogWrite(address + element_size, rt2,
+        LogWrite(address + element_size,
+                 rt2,
                  GetPrintRegisterFormatForSize(element_size));
       }
     }
@@ -1478,9 +1647,11 @@
       break;
 
     // Ignore prfm hint instructions.
-    case PRFM_lit: break;
+    case PRFM_lit:
+      break;
 
-    default: VIXL_UNREACHABLE();
+    default:
+      VIXL_UNREACHABLE();
   }
 
   local_monitor_.MaybeClear();
@@ -1521,7 +1692,7 @@
 
 void Simulator::VisitMoveWideImmediate(const Instruction* instr) {
   MoveWideImmediateOp mov_op =
-    static_cast<MoveWideImmediateOp>(instr->Mask(MoveWideImmediateMask));
+      static_cast<MoveWideImmediateOp>(instr->Mask(MoveWideImmediateMask));
   int64_t new_xn_val = 0;
 
   bool is_64_bits = instr->SixtyFourBits() == 1;
@@ -1536,22 +1707,20 @@
   switch (mov_op) {
     case MOVN_w:
     case MOVN_x: {
-        new_xn_val = ~shifted_imm16;
-        if (!is_64_bits) new_xn_val &= kWRegMask;
+      new_xn_val = ~shifted_imm16;
+      if (!is_64_bits) new_xn_val &= kWRegMask;
       break;
     }
     case MOVK_w:
     case MOVK_x: {
-        unsigned reg_code = instr->Rd();
-        int64_t prev_xn_val = is_64_bits ? xreg(reg_code)
-                                         : wreg(reg_code);
-        new_xn_val =
-            (prev_xn_val & ~(INT64_C(0xffff) << shift)) | shifted_imm16;
+      unsigned reg_code = instr->Rd();
+      int64_t prev_xn_val = is_64_bits ? xreg(reg_code) : wreg(reg_code);
+      new_xn_val = (prev_xn_val & ~(INT64_C(0xffff) << shift)) | shifted_imm16;
       break;
     }
     case MOVZ_w:
     case MOVZ_x: {
-        new_xn_val = shifted_imm16;
+      new_xn_val = shifted_imm16;
       break;
     }
     default:
@@ -1570,14 +1739,22 @@
     new_val = xreg(instr->Rm());
     switch (instr->Mask(ConditionalSelectMask)) {
       case CSEL_w:
-      case CSEL_x: break;
+      case CSEL_x:
+        break;
       case CSINC_w:
-      case CSINC_x: new_val++; break;
+      case CSINC_x:
+        new_val++;
+        break;
       case CSINV_w:
-      case CSINV_x: new_val = ~new_val; break;
+      case CSINV_x:
+        new_val = ~new_val;
+        break;
       case CSNEG_w:
-      case CSNEG_x: new_val = -new_val; break;
-      default: VIXL_UNIMPLEMENTED();
+      case CSNEG_x:
+        new_val = -new_val;
+        break;
+      default:
+        VIXL_UNIMPLEMENTED();
     }
   }
   unsigned reg_size = instr->SixtyFourBits() ? kXRegSize : kWRegSize;
@@ -1590,15 +1767,33 @@
   unsigned src = instr->Rn();
 
   switch (instr->Mask(DataProcessing1SourceMask)) {
-    case RBIT_w: set_wreg(dst, ReverseBits(wreg(src))); break;
-    case RBIT_x: set_xreg(dst, ReverseBits(xreg(src))); break;
-    case REV16_w: set_wreg(dst, ReverseBytes(wreg(src), 1)); break;
-    case REV16_x: set_xreg(dst, ReverseBytes(xreg(src), 1)); break;
-    case REV_w: set_wreg(dst, ReverseBytes(wreg(src), 2)); break;
-    case REV32_x: set_xreg(dst, ReverseBytes(xreg(src), 2)); break;
-    case REV_x: set_xreg(dst, ReverseBytes(xreg(src), 3)); break;
-    case CLZ_w: set_wreg(dst, CountLeadingZeros(wreg(src))); break;
-    case CLZ_x: set_xreg(dst, CountLeadingZeros(xreg(src))); break;
+    case RBIT_w:
+      set_wreg(dst, ReverseBits(wreg(src)));
+      break;
+    case RBIT_x:
+      set_xreg(dst, ReverseBits(xreg(src)));
+      break;
+    case REV16_w:
+      set_wreg(dst, ReverseBytes(wreg(src), 1));
+      break;
+    case REV16_x:
+      set_xreg(dst, ReverseBytes(xreg(src), 1));
+      break;
+    case REV_w:
+      set_wreg(dst, ReverseBytes(wreg(src), 2));
+      break;
+    case REV32_x:
+      set_xreg(dst, ReverseBytes(xreg(src), 2));
+      break;
+    case REV_x:
+      set_xreg(dst, ReverseBytes(xreg(src), 3));
+      break;
+    case CLZ_w:
+      set_wreg(dst, CountLeadingZeros(wreg(src)));
+      break;
+    case CLZ_x:
+      set_xreg(dst, CountLeadingZeros(xreg(src)));
+      break;
     case CLS_w: {
       set_wreg(dst, CountLeadingSignBits(wreg(src)));
       break;
@@ -1607,7 +1802,8 @@
       set_xreg(dst, CountLeadingSignBits(xreg(src)));
       break;
     }
-    default: VIXL_UNIMPLEMENTED();
+    default:
+      VIXL_UNIMPLEMENTED();
   }
 }
 
@@ -1698,16 +1894,24 @@
       break;
     }
     case LSLV_w:
-    case LSLV_x: shift_op = LSL; break;
+    case LSLV_x:
+      shift_op = LSL;
+      break;
     case LSRV_w:
-    case LSRV_x: shift_op = LSR; break;
+    case LSRV_x:
+      shift_op = LSR;
+      break;
     case ASRV_w:
-    case ASRV_x: shift_op = ASR; break;
+    case ASRV_x:
+      shift_op = ASR;
+      break;
     case RORV_w:
-    case RORV_x: shift_op = ROR; break;
+    case RORV_x:
+      shift_op = ROR;
+      break;
     case CRC32B: {
       uint32_t acc = reg<uint32_t>(instr->Rn());
-      uint8_t  val = reg<uint8_t>(instr->Rm());
+      uint8_t val = reg<uint8_t>(instr->Rm());
       result = Crc32Checksum(acc, val, CRC32_POLY);
       break;
     }
@@ -1732,7 +1936,7 @@
     }
     case CRC32CB: {
       uint32_t acc = reg<uint32_t>(instr->Rn());
-      uint8_t  val = reg<uint8_t>(instr->Rm());
+      uint8_t val = reg<uint8_t>(instr->Rm());
       result = Crc32Checksum(acc, val, CRC32C_POLY);
       break;
     }
@@ -1755,7 +1959,8 @@
       reg_size = kWRegSize;
       break;
     }
-    default: VIXL_UNIMPLEMENTED();
+    default:
+      VIXL_UNIMPLEMENTED();
   }
 
   if (shift_op != NO_SHIFT) {
@@ -1763,8 +1968,8 @@
     // register.
     int mask = (instr->SixtyFourBits() == 1) ? 0x3f : 0x1f;
     unsigned shift = wreg(instr->Rm()) & mask;
-    result = ShiftOperand(reg_size, reg(reg_size, instr->Rn()), shift_op,
-                          shift);
+    result =
+        ShiftOperand(reg_size, reg(reg_size, instr->Rn()), shift_op, shift);
   }
   set_reg(reg_size, instr->Rd(), result);
 }
@@ -1799,7 +2004,7 @@
 void Simulator::VisitDataProcessing3Source(const Instruction* instr) {
   unsigned reg_size = instr->SixtyFourBits() ? kXRegSize : kWRegSize;
 
-  int64_t result = 0;
+  uint64_t result = 0;
   // Extract and sign- or zero-extend 32-bit arguments for widening operations.
   uint64_t rn_u32 = reg<uint32_t>(instr->Rn());
   uint64_t rm_u32 = reg<uint32_t>(instr->Rm());
@@ -1814,18 +2019,27 @@
     case MSUB_x:
       result = xreg(instr->Ra()) - (xreg(instr->Rn()) * xreg(instr->Rm()));
       break;
-    case SMADDL_x: result = xreg(instr->Ra()) + (rn_s32 * rm_s32); break;
-    case SMSUBL_x: result = xreg(instr->Ra()) - (rn_s32 * rm_s32); break;
-    case UMADDL_x: result = xreg(instr->Ra()) + (rn_u32 * rm_u32); break;
-    case UMSUBL_x: result = xreg(instr->Ra()) - (rn_u32 * rm_u32); break;
+    case SMADDL_x:
+      result = xreg(instr->Ra()) + (rn_s32 * rm_s32);
+      break;
+    case SMSUBL_x:
+      result = xreg(instr->Ra()) - (rn_s32 * rm_s32);
+      break;
+    case UMADDL_x:
+      result = xreg(instr->Ra()) + (rn_u32 * rm_u32);
+      break;
+    case UMSUBL_x:
+      result = xreg(instr->Ra()) - (rn_u32 * rm_u32);
+      break;
     case UMULH_x:
-      result = MultiplyHigh(reg<uint64_t>(instr->Rn()),
-                            reg<uint64_t>(instr->Rm()));
+      result =
+          MultiplyHigh(reg<uint64_t>(instr->Rn()), reg<uint64_t>(instr->Rm()));
       break;
     case SMULH_x:
       result = MultiplyHigh(xreg(instr->Rn()), xreg(instr->Rm()));
       break;
-    default: VIXL_UNIMPLEMENTED();
+    default:
+      VIXL_UNIMPLEMENTED();
   }
   set_reg(reg_size, instr->Rd(), result);
 }
@@ -1839,8 +2053,7 @@
   int64_t diff = S - R;
   int64_t mask;
   if (diff >= 0) {
-    mask = (diff < (reg_size - 1)) ? (INT64_C(1) << (diff + 1)) - 1
-                                   : reg_mask;
+    mask = (diff < (reg_size - 1)) ? (INT64_C(1) << (diff + 1)) - 1 : reg_mask;
   } else {
     mask = (INT64_C(1) << (S + 1)) - 1;
     mask = (static_cast<uint64_t>(mask) >> R) | (mask << (reg_size - R));
@@ -1886,11 +2099,10 @@
 
 void Simulator::VisitExtract(const Instruction* instr) {
   unsigned lsb = instr->ImmS();
-  unsigned reg_size = (instr->SixtyFourBits() == 1) ? kXRegSize
-                                                    : kWRegSize;
+  unsigned reg_size = (instr->SixtyFourBits() == 1) ? kXRegSize : kWRegSize;
   uint64_t low_res = static_cast<uint64_t>(reg(reg_size, instr->Rm())) >> lsb;
-  uint64_t high_res =
-      (lsb == 0) ? 0 : reg(reg_size, instr->Rn()) << (reg_size - lsb);
+  uint64_t high_res = (lsb == 0) ? 0 : reg(reg_size, instr->Rn())
+                                           << (reg_size - lsb);
   set_reg(reg_size, instr->Rd(), low_res | high_res);
 }
 
@@ -1900,9 +2112,14 @@
 
   unsigned dest = instr->Rd();
   switch (instr->Mask(FPImmediateMask)) {
-    case FMOV_s_imm: set_sreg(dest, instr->ImmFP32()); break;
-    case FMOV_d_imm: set_dreg(dest, instr->ImmFP64()); break;
-    default: VIXL_UNREACHABLE();
+    case FMOV_s_imm:
+      set_sreg(dest, instr->ImmFP32());
+      break;
+    case FMOV_d_imm:
+      set_dreg(dest, instr->ImmFP64());
+      break;
+    default:
+      VIXL_UNREACHABLE();
   }
 }
 
@@ -1916,14 +2133,30 @@
   FPRounding round = RMode();
 
   switch (instr->Mask(FPIntegerConvertMask)) {
-    case FCVTAS_ws: set_wreg(dst, FPToInt32(sreg(src), FPTieAway)); break;
-    case FCVTAS_xs: set_xreg(dst, FPToInt64(sreg(src), FPTieAway)); break;
-    case FCVTAS_wd: set_wreg(dst, FPToInt32(dreg(src), FPTieAway)); break;
-    case FCVTAS_xd: set_xreg(dst, FPToInt64(dreg(src), FPTieAway)); break;
-    case FCVTAU_ws: set_wreg(dst, FPToUInt32(sreg(src), FPTieAway)); break;
-    case FCVTAU_xs: set_xreg(dst, FPToUInt64(sreg(src), FPTieAway)); break;
-    case FCVTAU_wd: set_wreg(dst, FPToUInt32(dreg(src), FPTieAway)); break;
-    case FCVTAU_xd: set_xreg(dst, FPToUInt64(dreg(src), FPTieAway)); break;
+    case FCVTAS_ws:
+      set_wreg(dst, FPToInt32(sreg(src), FPTieAway));
+      break;
+    case FCVTAS_xs:
+      set_xreg(dst, FPToInt64(sreg(src), FPTieAway));
+      break;
+    case FCVTAS_wd:
+      set_wreg(dst, FPToInt32(dreg(src), FPTieAway));
+      break;
+    case FCVTAS_xd:
+      set_xreg(dst, FPToInt64(dreg(src), FPTieAway));
+      break;
+    case FCVTAU_ws:
+      set_wreg(dst, FPToUInt32(sreg(src), FPTieAway));
+      break;
+    case FCVTAU_xs:
+      set_xreg(dst, FPToUInt64(sreg(src), FPTieAway));
+      break;
+    case FCVTAU_wd:
+      set_wreg(dst, FPToUInt32(dreg(src), FPTieAway));
+      break;
+    case FCVTAU_xd:
+      set_xreg(dst, FPToUInt64(dreg(src), FPTieAway));
+      break;
     case FCVTMS_ws:
       set_wreg(dst, FPToInt32(sreg(src), FPNegativeInfinity));
       break;
@@ -1972,26 +2205,66 @@
     case FCVTPU_xd:
       set_xreg(dst, FPToUInt64(dreg(src), FPPositiveInfinity));
       break;
-    case FCVTNS_ws: set_wreg(dst, FPToInt32(sreg(src), FPTieEven)); break;
-    case FCVTNS_xs: set_xreg(dst, FPToInt64(sreg(src), FPTieEven)); break;
-    case FCVTNS_wd: set_wreg(dst, FPToInt32(dreg(src), FPTieEven)); break;
-    case FCVTNS_xd: set_xreg(dst, FPToInt64(dreg(src), FPTieEven)); break;
-    case FCVTNU_ws: set_wreg(dst, FPToUInt32(sreg(src), FPTieEven)); break;
-    case FCVTNU_xs: set_xreg(dst, FPToUInt64(sreg(src), FPTieEven)); break;
-    case FCVTNU_wd: set_wreg(dst, FPToUInt32(dreg(src), FPTieEven)); break;
-    case FCVTNU_xd: set_xreg(dst, FPToUInt64(dreg(src), FPTieEven)); break;
-    case FCVTZS_ws: set_wreg(dst, FPToInt32(sreg(src), FPZero)); break;
-    case FCVTZS_xs: set_xreg(dst, FPToInt64(sreg(src), FPZero)); break;
-    case FCVTZS_wd: set_wreg(dst, FPToInt32(dreg(src), FPZero)); break;
-    case FCVTZS_xd: set_xreg(dst, FPToInt64(dreg(src), FPZero)); break;
-    case FCVTZU_ws: set_wreg(dst, FPToUInt32(sreg(src), FPZero)); break;
-    case FCVTZU_xs: set_xreg(dst, FPToUInt64(sreg(src), FPZero)); break;
-    case FCVTZU_wd: set_wreg(dst, FPToUInt32(dreg(src), FPZero)); break;
-    case FCVTZU_xd: set_xreg(dst, FPToUInt64(dreg(src), FPZero)); break;
-    case FMOV_ws: set_wreg(dst, sreg_bits(src)); break;
-    case FMOV_xd: set_xreg(dst, dreg_bits(src)); break;
-    case FMOV_sw: set_sreg_bits(dst, wreg(src)); break;
-    case FMOV_dx: set_dreg_bits(dst, xreg(src)); break;
+    case FCVTNS_ws:
+      set_wreg(dst, FPToInt32(sreg(src), FPTieEven));
+      break;
+    case FCVTNS_xs:
+      set_xreg(dst, FPToInt64(sreg(src), FPTieEven));
+      break;
+    case FCVTNS_wd:
+      set_wreg(dst, FPToInt32(dreg(src), FPTieEven));
+      break;
+    case FCVTNS_xd:
+      set_xreg(dst, FPToInt64(dreg(src), FPTieEven));
+      break;
+    case FCVTNU_ws:
+      set_wreg(dst, FPToUInt32(sreg(src), FPTieEven));
+      break;
+    case FCVTNU_xs:
+      set_xreg(dst, FPToUInt64(sreg(src), FPTieEven));
+      break;
+    case FCVTNU_wd:
+      set_wreg(dst, FPToUInt32(dreg(src), FPTieEven));
+      break;
+    case FCVTNU_xd:
+      set_xreg(dst, FPToUInt64(dreg(src), FPTieEven));
+      break;
+    case FCVTZS_ws:
+      set_wreg(dst, FPToInt32(sreg(src), FPZero));
+      break;
+    case FCVTZS_xs:
+      set_xreg(dst, FPToInt64(sreg(src), FPZero));
+      break;
+    case FCVTZS_wd:
+      set_wreg(dst, FPToInt32(dreg(src), FPZero));
+      break;
+    case FCVTZS_xd:
+      set_xreg(dst, FPToInt64(dreg(src), FPZero));
+      break;
+    case FCVTZU_ws:
+      set_wreg(dst, FPToUInt32(sreg(src), FPZero));
+      break;
+    case FCVTZU_xs:
+      set_xreg(dst, FPToUInt64(sreg(src), FPZero));
+      break;
+    case FCVTZU_wd:
+      set_wreg(dst, FPToUInt32(dreg(src), FPZero));
+      break;
+    case FCVTZU_xd:
+      set_xreg(dst, FPToUInt64(dreg(src), FPZero));
+      break;
+    case FMOV_ws:
+      set_wreg(dst, sreg_bits(src));
+      break;
+    case FMOV_xd:
+      set_xreg(dst, dreg_bits(src));
+      break;
+    case FMOV_sw:
+      set_sreg_bits(dst, wreg(src));
+      break;
+    case FMOV_dx:
+      set_dreg_bits(dst, xreg(src));
+      break;
     case FMOV_d1_x:
       LogicVRegister(vreg(dst)).SetUint(kFormatD, 1, xreg(src));
       break;
@@ -2001,22 +2274,35 @@
 
     // A 32-bit input can be handled in the same way as a 64-bit input, since
     // the sign- or zero-extension will not affect the conversion.
-    case SCVTF_dx: set_dreg(dst, FixedToDouble(xreg(src), 0, round)); break;
-    case SCVTF_dw: set_dreg(dst, FixedToDouble(wreg(src), 0, round)); break;
-    case UCVTF_dx: set_dreg(dst, UFixedToDouble(xreg(src), 0, round)); break;
+    case SCVTF_dx:
+      set_dreg(dst, FixedToDouble(xreg(src), 0, round));
+      break;
+    case SCVTF_dw:
+      set_dreg(dst, FixedToDouble(wreg(src), 0, round));
+      break;
+    case UCVTF_dx:
+      set_dreg(dst, UFixedToDouble(xreg(src), 0, round));
+      break;
     case UCVTF_dw: {
       set_dreg(dst, UFixedToDouble(static_cast<uint32_t>(wreg(src)), 0, round));
       break;
     }
-    case SCVTF_sx: set_sreg(dst, FixedToFloat(xreg(src), 0, round)); break;
-    case SCVTF_sw: set_sreg(dst, FixedToFloat(wreg(src), 0, round)); break;
-    case UCVTF_sx: set_sreg(dst, UFixedToFloat(xreg(src), 0, round)); break;
+    case SCVTF_sx:
+      set_sreg(dst, FixedToFloat(xreg(src), 0, round));
+      break;
+    case SCVTF_sw:
+      set_sreg(dst, FixedToFloat(wreg(src), 0, round));
+      break;
+    case UCVTF_sx:
+      set_sreg(dst, UFixedToFloat(xreg(src), 0, round));
+      break;
     case UCVTF_sw: {
       set_sreg(dst, UFixedToFloat(static_cast<uint32_t>(wreg(src)), 0, round));
       break;
     }
 
-    default: VIXL_UNREACHABLE();
+    default:
+      VIXL_UNREACHABLE();
   }
 }
 
@@ -2085,7 +2371,8 @@
     case FCVTZU_ws_fixed:
       set_wreg(dst, FPToUInt32(sreg(src) * std::pow(2.0f, fbits), FPZero));
       break;
-    default: VIXL_UNREACHABLE();
+    default:
+      VIXL_UNREACHABLE();
   }
 }
 
@@ -2095,15 +2382,32 @@
 
   FPTrapFlags trap = DisableTrap;
   switch (instr->Mask(FPCompareMask)) {
-    case FCMPE_s: trap = EnableTrap; VIXL_FALLTHROUGH();
-    case FCMP_s: FPCompare(sreg(instr->Rn()), sreg(instr->Rm()), trap); break;
-    case FCMPE_d: trap = EnableTrap; VIXL_FALLTHROUGH();
-    case FCMP_d: FPCompare(dreg(instr->Rn()), dreg(instr->Rm()), trap); break;
-    case FCMPE_s_zero: trap = EnableTrap; VIXL_FALLTHROUGH();
-    case FCMP_s_zero: FPCompare(sreg(instr->Rn()), 0.0f, trap); break;
-    case FCMPE_d_zero: trap = EnableTrap; VIXL_FALLTHROUGH();
-    case FCMP_d_zero: FPCompare(dreg(instr->Rn()), 0.0, trap); break;
-    default: VIXL_UNIMPLEMENTED();
+    case FCMPE_s:
+      trap = EnableTrap;
+      VIXL_FALLTHROUGH();
+    case FCMP_s:
+      FPCompare(sreg(instr->Rn()), sreg(instr->Rm()), trap);
+      break;
+    case FCMPE_d:
+      trap = EnableTrap;
+      VIXL_FALLTHROUGH();
+    case FCMP_d:
+      FPCompare(dreg(instr->Rn()), dreg(instr->Rm()), trap);
+      break;
+    case FCMPE_s_zero:
+      trap = EnableTrap;
+      VIXL_FALLTHROUGH();
+    case FCMP_s_zero:
+      FPCompare(sreg(instr->Rn()), 0.0f, trap);
+      break;
+    case FCMPE_d_zero:
+      trap = EnableTrap;
+      VIXL_FALLTHROUGH();
+    case FCMP_d_zero:
+      FPCompare(dreg(instr->Rn()), 0.0, trap);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
   }
 }
 
@@ -2113,7 +2417,8 @@
 
   FPTrapFlags trap = DisableTrap;
   switch (instr->Mask(FPConditionalCompareMask)) {
-    case FCCMPE_s: trap = EnableTrap;
+    case FCCMPE_s:
+      trap = EnableTrap;
       VIXL_FALLTHROUGH();
     case FCCMP_s:
       if (ConditionPassed(instr->Condition())) {
@@ -2123,7 +2428,8 @@
         LogSystemRegister(NZCV);
       }
       break;
-    case FCCMPE_d: trap = EnableTrap;
+    case FCCMPE_d:
+      trap = EnableTrap;
       VIXL_FALLTHROUGH();
     case FCCMP_d:
       if (ConditionPassed(instr->Condition())) {
@@ -2133,7 +2439,8 @@
         LogSystemRegister(NZCV);
       }
       break;
-    default: VIXL_UNIMPLEMENTED();
+    default:
+      VIXL_UNIMPLEMENTED();
   }
 }
 
@@ -2149,9 +2456,14 @@
   }
 
   switch (instr->Mask(FPConditionalSelectMask)) {
-    case FCSEL_s: set_sreg(instr->Rd(), sreg(selected)); break;
-    case FCSEL_d: set_dreg(instr->Rd(), dreg(selected)); break;
-    default: VIXL_UNIMPLEMENTED();
+    case FCSEL_s:
+      set_sreg(instr->Rd(), sreg(selected));
+      break;
+    case FCSEL_d:
+      set_dreg(instr->Rd(), dreg(selected));
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
   }
 }
 
@@ -2169,39 +2481,83 @@
   unsigned fn = instr->Rn();
 
   switch (instr->Mask(FPDataProcessing1SourceMask)) {
-    case FMOV_s: set_sreg(fd, sreg(fn)); return;
-    case FMOV_d: set_dreg(fd, dreg(fn)); return;
-    case FABS_s: fabs_(kFormatS, vreg(fd), vreg(fn)); return;
-    case FABS_d: fabs_(kFormatD, vreg(fd), vreg(fn)); return;
-    case FNEG_s: fneg(kFormatS, vreg(fd), vreg(fn)); return;
-    case FNEG_d: fneg(kFormatD, vreg(fd), vreg(fn)); return;
-    case FCVT_ds: set_dreg(fd, FPToDouble(sreg(fn))); return;
-    case FCVT_sd: set_sreg(fd, FPToFloat(dreg(fn), FPTieEven)); return;
-    case FCVT_hs: set_hreg(fd, FPToFloat16(sreg(fn), FPTieEven)); return;
-    case FCVT_sh: set_sreg(fd, FPToFloat(hreg(fn))); return;
-    case FCVT_dh: set_dreg(fd, FPToDouble(FPToFloat(hreg(fn)))); return;
-    case FCVT_hd: set_hreg(fd, FPToFloat16(dreg(fn), FPTieEven)); return;
+    case FMOV_s:
+      set_sreg(fd, sreg(fn));
+      return;
+    case FMOV_d:
+      set_dreg(fd, dreg(fn));
+      return;
+    case FABS_s:
+    case FABS_d:
+      fabs_(vform, vreg(fd), vreg(fn));
+      // Explicitly log the register update whilst we have type information.
+      LogVRegister(fd, GetPrintRegisterFormatFP(vform));
+      return;
+    case FNEG_s:
+    case FNEG_d:
+      fneg(vform, vreg(fd), vreg(fn));
+      // Explicitly log the register update whilst we have type information.
+      LogVRegister(fd, GetPrintRegisterFormatFP(vform));
+      return;
+    case FCVT_ds:
+      set_dreg(fd, FPToDouble(sreg(fn)));
+      return;
+    case FCVT_sd:
+      set_sreg(fd, FPToFloat(dreg(fn), FPTieEven));
+      return;
+    case FCVT_hs:
+      set_hreg(fd, FPToFloat16(sreg(fn), FPTieEven));
+      return;
+    case FCVT_sh:
+      set_sreg(fd, FPToFloat(hreg(fn)));
+      return;
+    case FCVT_dh:
+      set_dreg(fd, FPToDouble(FPToFloat(hreg(fn))));
+      return;
+    case FCVT_hd:
+      set_hreg(fd, FPToFloat16(dreg(fn), FPTieEven));
+      return;
     case FSQRT_s:
-    case FSQRT_d: fsqrt(vform, rd, rn); return;
+    case FSQRT_d:
+      fsqrt(vform, rd, rn);
+      // Explicitly log the register update whilst we have type information.
+      LogVRegister(fd, GetPrintRegisterFormatFP(vform));
+      return;
     case FRINTI_s:
-    case FRINTI_d: break;  // Use FPCR rounding mode.
+    case FRINTI_d:
+      break;  // Use FPCR rounding mode.
     case FRINTX_s:
-    case FRINTX_d: inexact_exception = true; break;
+    case FRINTX_d:
+      inexact_exception = true;
+      break;
     case FRINTA_s:
-    case FRINTA_d: fpcr_rounding = FPTieAway; break;
+    case FRINTA_d:
+      fpcr_rounding = FPTieAway;
+      break;
     case FRINTM_s:
-    case FRINTM_d: fpcr_rounding = FPNegativeInfinity; break;
+    case FRINTM_d:
+      fpcr_rounding = FPNegativeInfinity;
+      break;
     case FRINTN_s:
-    case FRINTN_d: fpcr_rounding = FPTieEven; break;
+    case FRINTN_d:
+      fpcr_rounding = FPTieEven;
+      break;
     case FRINTP_s:
-    case FRINTP_d: fpcr_rounding = FPPositiveInfinity; break;
+    case FRINTP_d:
+      fpcr_rounding = FPPositiveInfinity;
+      break;
     case FRINTZ_s:
-    case FRINTZ_d: fpcr_rounding = FPZero; break;
-    default: VIXL_UNIMPLEMENTED();
+    case FRINTZ_d:
+      fpcr_rounding = FPZero;
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
   }
 
   // Only FRINT* instructions fall through the switch above.
   frint(vform, rd, rn, fpcr_rounding, inexact_exception);
+  // Explicitly log the register update whilst we have type information.
+  LogVRegister(fd, GetPrintRegisterFormatFP(vform));
 }
 
 
@@ -2215,26 +2571,46 @@
 
   switch (instr->Mask(FPDataProcessing2SourceMask)) {
     case FADD_s:
-    case FADD_d: fadd(vform, rd, rn, rm); break;
+    case FADD_d:
+      fadd(vform, rd, rn, rm);
+      break;
     case FSUB_s:
-    case FSUB_d: fsub(vform, rd, rn, rm); break;
+    case FSUB_d:
+      fsub(vform, rd, rn, rm);
+      break;
     case FMUL_s:
-    case FMUL_d: fmul(vform, rd, rn, rm); break;
+    case FMUL_d:
+      fmul(vform, rd, rn, rm);
+      break;
     case FNMUL_s:
-    case FNMUL_d: fnmul(vform, rd, rn, rm); break;
+    case FNMUL_d:
+      fnmul(vform, rd, rn, rm);
+      break;
     case FDIV_s:
-    case FDIV_d: fdiv(vform, rd, rn, rm); break;
+    case FDIV_d:
+      fdiv(vform, rd, rn, rm);
+      break;
     case FMAX_s:
-    case FMAX_d: fmax(vform, rd, rn, rm); break;
+    case FMAX_d:
+      fmax(vform, rd, rn, rm);
+      break;
     case FMIN_s:
-    case FMIN_d: fmin(vform, rd, rn, rm); break;
+    case FMIN_d:
+      fmin(vform, rd, rn, rm);
+      break;
     case FMAXNM_s:
-    case FMAXNM_d: fmaxnm(vform, rd, rn, rm); break;
+    case FMAXNM_d:
+      fmaxnm(vform, rd, rn, rm);
+      break;
     case FMINNM_s:
-    case FMINNM_d: fminnm(vform, rd, rn, rm); break;
+    case FMINNM_d:
+      fminnm(vform, rd, rn, rm);
+      break;
     default:
       VIXL_UNREACHABLE();
   }
+  // Explicitly log the register update whilst we have type information.
+  LogVRegister(instr->Rd(), GetPrintRegisterFormatFP(vform));
 }
 
 
@@ -2248,10 +2624,18 @@
 
   switch (instr->Mask(FPDataProcessing3SourceMask)) {
     // fd = fa +/- (fn * fm)
-    case FMADD_s: set_sreg(fd, FPMulAdd(sreg(fa), sreg(fn), sreg(fm))); break;
-    case FMSUB_s: set_sreg(fd, FPMulAdd(sreg(fa), -sreg(fn), sreg(fm))); break;
-    case FMADD_d: set_dreg(fd, FPMulAdd(dreg(fa), dreg(fn), dreg(fm))); break;
-    case FMSUB_d: set_dreg(fd, FPMulAdd(dreg(fa), -dreg(fn), dreg(fm))); break;
+    case FMADD_s:
+      set_sreg(fd, FPMulAdd(sreg(fa), sreg(fn), sreg(fm)));
+      break;
+    case FMSUB_s:
+      set_sreg(fd, FPMulAdd(sreg(fa), -sreg(fn), sreg(fm)));
+      break;
+    case FMADD_d:
+      set_dreg(fd, FPMulAdd(dreg(fa), dreg(fn), dreg(fm)));
+      break;
+    case FMSUB_d:
+      set_dreg(fd, FPMulAdd(dreg(fa), -dreg(fn), dreg(fm)));
+      break;
     // Negated variants of the above.
     case FNMADD_s:
       set_sreg(fd, FPMulAdd(-sreg(fa), -sreg(fn), sreg(fm)));
@@ -2265,7 +2649,8 @@
     case FNMSUB_d:
       set_dreg(fd, FPMulAdd(-dreg(fa), dreg(fn), dreg(fm)));
       break;
-    default: VIXL_UNIMPLEMENTED();
+    default:
+      VIXL_UNIMPLEMENTED();
   }
 }
 
@@ -2330,9 +2715,14 @@
     switch (instr->Mask(SystemSysRegMask)) {
       case MRS: {
         switch (instr->ImmSystemRegister()) {
-          case NZCV: set_xreg(instr->Rt(), nzcv().RawValue()); break;
-          case FPCR: set_xreg(instr->Rt(), fpcr().RawValue()); break;
-          default: VIXL_UNIMPLEMENTED();
+          case NZCV:
+            set_xreg(instr->Rt(), nzcv().RawValue());
+            break;
+          case FPCR:
+            set_xreg(instr->Rt(), fpcr().RawValue());
+            break;
+          default:
+            VIXL_UNIMPLEMENTED();
         }
         break;
       }
@@ -2346,7 +2736,8 @@
             fpcr().SetRawValue(wreg(instr->Rt()));
             LogSystemRegister(FPCR);
             break;
-          default: VIXL_UNIMPLEMENTED();
+          default:
+            VIXL_UNIMPLEMENTED();
         }
         break;
       }
@@ -2354,15 +2745,20 @@
   } else if (instr->Mask(SystemHintFMask) == SystemHintFixed) {
     VIXL_ASSERT(instr->Mask(SystemHintMask) == HINT);
     switch (instr->ImmHint()) {
-      case NOP: break;
-      default: VIXL_UNIMPLEMENTED();
+      case NOP:
+        break;
+      default:
+        VIXL_UNIMPLEMENTED();
     }
   } else if (instr->Mask(MemBarrierFMask) == MemBarrierFixed) {
     __sync_synchronize();
   } else if ((instr->Mask(SystemSysFMask) == SystemSysFixed)) {
     switch (instr->Mask(SystemSysMask)) {
-      case SYS: SysOp_W(instr->SysOp(), xreg(instr->Rt())); break;
-      default: VIXL_UNIMPLEMENTED();
+      case SYS:
+        SysOp_W(instr->SysOp(), xreg(instr->Rt()));
+        break;
+      default:
+        VIXL_UNIMPLEMENTED();
     }
   } else {
     VIXL_UNIMPLEMENTED();
@@ -2418,19 +2814,15 @@
   NEONFormatDecoder nfd(instr);
   VectorFormat vf = nfd.GetVectorFormat();
 
-  static const NEONFormatMap map_lp = {
-    {23, 22, 30}, {NF_4H, NF_8H, NF_2S, NF_4S, NF_1D, NF_2D}
-  };
+  static const NEONFormatMap map_lp =
+      {{23, 22, 30}, {NF_4H, NF_8H, NF_2S, NF_4S, NF_1D, NF_2D}};
   VectorFormat vf_lp = nfd.GetVectorFormat(&map_lp);
 
-  static const NEONFormatMap map_fcvtl = {
-    {22}, {NF_4S, NF_2D}
-  };
+  static const NEONFormatMap map_fcvtl = {{22}, {NF_4S, NF_2D}};
   VectorFormat vf_fcvtl = nfd.GetVectorFormat(&map_fcvtl);
 
-  static const NEONFormatMap map_fcvtn = {
-    {22, 30}, {NF_4H, NF_8H, NF_2S, NF_4S}
-  };
+  static const NEONFormatMap map_fcvtn = {{22, 30},
+                                          {NF_4H, NF_8H, NF_2S, NF_4S}};
   VectorFormat vf_fcvtn = nfd.GetVectorFormat(&map_fcvtn);
 
   SimVRegister& rd = vreg(instr->Rd());
@@ -2440,32 +2832,79 @@
     // These instructions all use a two bit size field, except NOT and RBIT,
     // which use the field to encode the operation.
     switch (instr->Mask(NEON2RegMiscMask)) {
-      case NEON_REV64:     rev64(vf, rd, rn); break;
-      case NEON_REV32:     rev32(vf, rd, rn); break;
-      case NEON_REV16:     rev16(vf, rd, rn); break;
-      case NEON_SUQADD:    suqadd(vf, rd, rn); break;
-      case NEON_USQADD:    usqadd(vf, rd, rn); break;
-      case NEON_CLS:       cls(vf, rd, rn); break;
-      case NEON_CLZ:       clz(vf, rd, rn); break;
-      case NEON_CNT:       cnt(vf, rd, rn); break;
-      case NEON_SQABS:     abs(vf, rd, rn).SignedSaturate(vf); break;
-      case NEON_SQNEG:     neg(vf, rd, rn).SignedSaturate(vf); break;
-      case NEON_CMGT_zero: cmp(vf, rd, rn, 0, gt); break;
-      case NEON_CMGE_zero: cmp(vf, rd, rn, 0, ge); break;
-      case NEON_CMEQ_zero: cmp(vf, rd, rn, 0, eq); break;
-      case NEON_CMLE_zero: cmp(vf, rd, rn, 0, le); break;
-      case NEON_CMLT_zero: cmp(vf, rd, rn, 0, lt); break;
-      case NEON_ABS:       abs(vf, rd, rn); break;
-      case NEON_NEG:       neg(vf, rd, rn); break;
-      case NEON_SADDLP:    saddlp(vf_lp, rd, rn); break;
-      case NEON_UADDLP:    uaddlp(vf_lp, rd, rn); break;
-      case NEON_SADALP:    sadalp(vf_lp, rd, rn); break;
-      case NEON_UADALP:    uadalp(vf_lp, rd, rn); break;
+      case NEON_REV64:
+        rev64(vf, rd, rn);
+        break;
+      case NEON_REV32:
+        rev32(vf, rd, rn);
+        break;
+      case NEON_REV16:
+        rev16(vf, rd, rn);
+        break;
+      case NEON_SUQADD:
+        suqadd(vf, rd, rn);
+        break;
+      case NEON_USQADD:
+        usqadd(vf, rd, rn);
+        break;
+      case NEON_CLS:
+        cls(vf, rd, rn);
+        break;
+      case NEON_CLZ:
+        clz(vf, rd, rn);
+        break;
+      case NEON_CNT:
+        cnt(vf, rd, rn);
+        break;
+      case NEON_SQABS:
+        abs(vf, rd, rn).SignedSaturate(vf);
+        break;
+      case NEON_SQNEG:
+        neg(vf, rd, rn).SignedSaturate(vf);
+        break;
+      case NEON_CMGT_zero:
+        cmp(vf, rd, rn, 0, gt);
+        break;
+      case NEON_CMGE_zero:
+        cmp(vf, rd, rn, 0, ge);
+        break;
+      case NEON_CMEQ_zero:
+        cmp(vf, rd, rn, 0, eq);
+        break;
+      case NEON_CMLE_zero:
+        cmp(vf, rd, rn, 0, le);
+        break;
+      case NEON_CMLT_zero:
+        cmp(vf, rd, rn, 0, lt);
+        break;
+      case NEON_ABS:
+        abs(vf, rd, rn);
+        break;
+      case NEON_NEG:
+        neg(vf, rd, rn);
+        break;
+      case NEON_SADDLP:
+        saddlp(vf_lp, rd, rn);
+        break;
+      case NEON_UADDLP:
+        uaddlp(vf_lp, rd, rn);
+        break;
+      case NEON_SADALP:
+        sadalp(vf_lp, rd, rn);
+        break;
+      case NEON_UADALP:
+        uadalp(vf_lp, rd, rn);
+        break;
       case NEON_RBIT_NOT:
         vf = nfd.GetVectorFormat(nfd.LogicalFormatMap());
         switch (instr->FPType()) {
-          case 0: not_(vf, rd, rn); break;
-          case 1: rbit(vf, rd, rn);; break;
+          case 0:
+            not_(vf, rd, rn);
+            break;
+          case 1:
+            rbit(vf, rd, rn);
+            ;
+            break;
           default:
             VIXL_UNIMPLEMENTED();
         }
@@ -2479,9 +2918,15 @@
     // These instructions all use a one bit size field, except XTN, SQXTUN,
     // SHLL, SQXTN and UQXTN, which use a two bit size field.
     switch (instr->Mask(NEON2RegMiscFPMask)) {
-      case NEON_FABS:   fabs_(fpf, rd, rn); return;
-      case NEON_FNEG:   fneg(fpf, rd, rn); return;
-      case NEON_FSQRT:  fsqrt(fpf, rd, rn); return;
+      case NEON_FABS:
+        fabs_(fpf, rd, rn);
+        return;
+      case NEON_FNEG:
+        fneg(fpf, rd, rn);
+        return;
+      case NEON_FSQRT:
+        fsqrt(fpf, rd, rn);
+        return;
       case NEON_FCVTL:
         if (instr->Mask(NEON_Q)) {
           fcvtl2(vf_fcvtl, rd, rn);
@@ -2506,43 +2951,106 @@
 
       // The following instructions break from the switch statement, rather
       // than return.
-      case NEON_FRINTI:     break;  // Use FPCR rounding mode.
-      case NEON_FRINTX:     inexact_exception = true; break;
-      case NEON_FRINTA:     fpcr_rounding = FPTieAway; break;
-      case NEON_FRINTM:     fpcr_rounding = FPNegativeInfinity; break;
-      case NEON_FRINTN:     fpcr_rounding = FPTieEven; break;
-      case NEON_FRINTP:     fpcr_rounding = FPPositiveInfinity; break;
-      case NEON_FRINTZ:     fpcr_rounding = FPZero; break;
+      case NEON_FRINTI:
+        break;  // Use FPCR rounding mode.
+      case NEON_FRINTX:
+        inexact_exception = true;
+        break;
+      case NEON_FRINTA:
+        fpcr_rounding = FPTieAway;
+        break;
+      case NEON_FRINTM:
+        fpcr_rounding = FPNegativeInfinity;
+        break;
+      case NEON_FRINTN:
+        fpcr_rounding = FPTieEven;
+        break;
+      case NEON_FRINTP:
+        fpcr_rounding = FPPositiveInfinity;
+        break;
+      case NEON_FRINTZ:
+        fpcr_rounding = FPZero;
+        break;
 
-      case NEON_FCVTNS:     fcvts(fpf, rd, rn, FPTieEven); return;
-      case NEON_FCVTNU:     fcvtu(fpf, rd, rn, FPTieEven); return;
-      case NEON_FCVTPS:     fcvts(fpf, rd, rn, FPPositiveInfinity); return;
-      case NEON_FCVTPU:     fcvtu(fpf, rd, rn, FPPositiveInfinity); return;
-      case NEON_FCVTMS:     fcvts(fpf, rd, rn, FPNegativeInfinity); return;
-      case NEON_FCVTMU:     fcvtu(fpf, rd, rn, FPNegativeInfinity); return;
-      case NEON_FCVTZS:     fcvts(fpf, rd, rn, FPZero); return;
-      case NEON_FCVTZU:     fcvtu(fpf, rd, rn, FPZero); return;
-      case NEON_FCVTAS:     fcvts(fpf, rd, rn, FPTieAway); return;
-      case NEON_FCVTAU:     fcvtu(fpf, rd, rn, FPTieAway); return;
-      case NEON_SCVTF:      scvtf(fpf, rd, rn, 0, fpcr_rounding); return;
-      case NEON_UCVTF:      ucvtf(fpf, rd, rn, 0, fpcr_rounding); return;
-      case NEON_URSQRTE:    ursqrte(fpf, rd, rn); return;
-      case NEON_URECPE:     urecpe(fpf, rd, rn); return;
-      case NEON_FRSQRTE:    frsqrte(fpf, rd, rn); return;
-      case NEON_FRECPE:     frecpe(fpf, rd, rn, fpcr_rounding); return;
-      case NEON_FCMGT_zero: fcmp_zero(fpf, rd, rn, gt); return;
-      case NEON_FCMGE_zero: fcmp_zero(fpf, rd, rn, ge); return;
-      case NEON_FCMEQ_zero: fcmp_zero(fpf, rd, rn, eq); return;
-      case NEON_FCMLE_zero: fcmp_zero(fpf, rd, rn, le); return;
-      case NEON_FCMLT_zero: fcmp_zero(fpf, rd, rn, lt); return;
+      case NEON_FCVTNS:
+        fcvts(fpf, rd, rn, FPTieEven);
+        return;
+      case NEON_FCVTNU:
+        fcvtu(fpf, rd, rn, FPTieEven);
+        return;
+      case NEON_FCVTPS:
+        fcvts(fpf, rd, rn, FPPositiveInfinity);
+        return;
+      case NEON_FCVTPU:
+        fcvtu(fpf, rd, rn, FPPositiveInfinity);
+        return;
+      case NEON_FCVTMS:
+        fcvts(fpf, rd, rn, FPNegativeInfinity);
+        return;
+      case NEON_FCVTMU:
+        fcvtu(fpf, rd, rn, FPNegativeInfinity);
+        return;
+      case NEON_FCVTZS:
+        fcvts(fpf, rd, rn, FPZero);
+        return;
+      case NEON_FCVTZU:
+        fcvtu(fpf, rd, rn, FPZero);
+        return;
+      case NEON_FCVTAS:
+        fcvts(fpf, rd, rn, FPTieAway);
+        return;
+      case NEON_FCVTAU:
+        fcvtu(fpf, rd, rn, FPTieAway);
+        return;
+      case NEON_SCVTF:
+        scvtf(fpf, rd, rn, 0, fpcr_rounding);
+        return;
+      case NEON_UCVTF:
+        ucvtf(fpf, rd, rn, 0, fpcr_rounding);
+        return;
+      case NEON_URSQRTE:
+        ursqrte(fpf, rd, rn);
+        return;
+      case NEON_URECPE:
+        urecpe(fpf, rd, rn);
+        return;
+      case NEON_FRSQRTE:
+        frsqrte(fpf, rd, rn);
+        return;
+      case NEON_FRECPE:
+        frecpe(fpf, rd, rn, fpcr_rounding);
+        return;
+      case NEON_FCMGT_zero:
+        fcmp_zero(fpf, rd, rn, gt);
+        return;
+      case NEON_FCMGE_zero:
+        fcmp_zero(fpf, rd, rn, ge);
+        return;
+      case NEON_FCMEQ_zero:
+        fcmp_zero(fpf, rd, rn, eq);
+        return;
+      case NEON_FCMLE_zero:
+        fcmp_zero(fpf, rd, rn, le);
+        return;
+      case NEON_FCMLT_zero:
+        fcmp_zero(fpf, rd, rn, lt);
+        return;
       default:
         if ((NEON_XTN_opcode <= instr->Mask(NEON2RegMiscOpcode)) &&
             (instr->Mask(NEON2RegMiscOpcode) <= NEON_UQXTN_opcode)) {
           switch (instr->Mask(NEON2RegMiscMask)) {
-            case NEON_XTN: xtn(vf, rd, rn); return;
-            case NEON_SQXTN: sqxtn(vf, rd, rn); return;
-            case NEON_UQXTN: uqxtn(vf, rd, rn); return;
-            case NEON_SQXTUN: sqxtun(vf, rd, rn); return;
+            case NEON_XTN:
+              xtn(vf, rd, rn);
+              return;
+            case NEON_SQXTN:
+              sqxtn(vf, rd, rn);
+              return;
+            case NEON_UQXTN:
+              uqxtn(vf, rd, rn);
+              return;
+            case NEON_SQXTUN:
+              sqxtun(vf, rd, rn);
+              return;
             case NEON_SHLL:
               vf = nfd.GetVectorFormat(nfd.LongIntegerFormatMap());
               if (instr->Mask(NEON_Q)) {
@@ -2574,87 +3082,225 @@
   if (instr->Mask(NEON3SameLogicalFMask) == NEON3SameLogicalFixed) {
     VectorFormat vf = nfd.GetVectorFormat(nfd.LogicalFormatMap());
     switch (instr->Mask(NEON3SameLogicalMask)) {
-      case NEON_AND: and_(vf, rd, rn, rm); break;
-      case NEON_ORR: orr(vf, rd, rn, rm); break;
-      case NEON_ORN: orn(vf, rd, rn, rm); break;
-      case NEON_EOR: eor(vf, rd, rn, rm); break;
-      case NEON_BIC: bic(vf, rd, rn, rm); break;
-      case NEON_BIF: bif(vf, rd, rn, rm); break;
-      case NEON_BIT: bit(vf, rd, rn, rm); break;
-      case NEON_BSL: bsl(vf, rd, rn, rm); break;
+      case NEON_AND:
+        and_(vf, rd, rn, rm);
+        break;
+      case NEON_ORR:
+        orr(vf, rd, rn, rm);
+        break;
+      case NEON_ORN:
+        orn(vf, rd, rn, rm);
+        break;
+      case NEON_EOR:
+        eor(vf, rd, rn, rm);
+        break;
+      case NEON_BIC:
+        bic(vf, rd, rn, rm);
+        break;
+      case NEON_BIF:
+        bif(vf, rd, rn, rm);
+        break;
+      case NEON_BIT:
+        bit(vf, rd, rn, rm);
+        break;
+      case NEON_BSL:
+        bsl(vf, rd, rn, rm);
+        break;
       default:
         VIXL_UNIMPLEMENTED();
     }
   } else if (instr->Mask(NEON3SameFPFMask) == NEON3SameFPFixed) {
     VectorFormat vf = nfd.GetVectorFormat(nfd.FPFormatMap());
     switch (instr->Mask(NEON3SameFPMask)) {
-      case NEON_FADD:    fadd(vf, rd, rn, rm); break;
-      case NEON_FSUB:    fsub(vf, rd, rn, rm); break;
-      case NEON_FMUL:    fmul(vf, rd, rn, rm); break;
-      case NEON_FDIV:    fdiv(vf, rd, rn, rm); break;
-      case NEON_FMAX:    fmax(vf, rd, rn, rm); break;
-      case NEON_FMIN:    fmin(vf, rd, rn, rm); break;
-      case NEON_FMAXNM:  fmaxnm(vf, rd, rn, rm); break;
-      case NEON_FMINNM:  fminnm(vf, rd, rn, rm); break;
-      case NEON_FMLA:    fmla(vf, rd, rn, rm); break;
-      case NEON_FMLS:    fmls(vf, rd, rn, rm); break;
-      case NEON_FMULX:   fmulx(vf, rd, rn, rm); break;
-      case NEON_FACGE:   fabscmp(vf, rd, rn, rm, ge); break;
-      case NEON_FACGT:   fabscmp(vf, rd, rn, rm, gt); break;
-      case NEON_FCMEQ:   fcmp(vf, rd, rn, rm, eq); break;
-      case NEON_FCMGE:   fcmp(vf, rd, rn, rm, ge); break;
-      case NEON_FCMGT:   fcmp(vf, rd, rn, rm, gt); break;
-      case NEON_FRECPS:  frecps(vf, rd, rn, rm); break;
-      case NEON_FRSQRTS: frsqrts(vf, rd, rn, rm); break;
-      case NEON_FABD:    fabd(vf, rd, rn, rm); break;
-      case NEON_FADDP:   faddp(vf, rd, rn, rm); break;
-      case NEON_FMAXP:   fmaxp(vf, rd, rn, rm); break;
-      case NEON_FMAXNMP: fmaxnmp(vf, rd, rn, rm); break;
-      case NEON_FMINP:   fminp(vf, rd, rn, rm); break;
-      case NEON_FMINNMP: fminnmp(vf, rd, rn, rm); break;
+      case NEON_FADD:
+        fadd(vf, rd, rn, rm);
+        break;
+      case NEON_FSUB:
+        fsub(vf, rd, rn, rm);
+        break;
+      case NEON_FMUL:
+        fmul(vf, rd, rn, rm);
+        break;
+      case NEON_FDIV:
+        fdiv(vf, rd, rn, rm);
+        break;
+      case NEON_FMAX:
+        fmax(vf, rd, rn, rm);
+        break;
+      case NEON_FMIN:
+        fmin(vf, rd, rn, rm);
+        break;
+      case NEON_FMAXNM:
+        fmaxnm(vf, rd, rn, rm);
+        break;
+      case NEON_FMINNM:
+        fminnm(vf, rd, rn, rm);
+        break;
+      case NEON_FMLA:
+        fmla(vf, rd, rn, rm);
+        break;
+      case NEON_FMLS:
+        fmls(vf, rd, rn, rm);
+        break;
+      case NEON_FMULX:
+        fmulx(vf, rd, rn, rm);
+        break;
+      case NEON_FACGE:
+        fabscmp(vf, rd, rn, rm, ge);
+        break;
+      case NEON_FACGT:
+        fabscmp(vf, rd, rn, rm, gt);
+        break;
+      case NEON_FCMEQ:
+        fcmp(vf, rd, rn, rm, eq);
+        break;
+      case NEON_FCMGE:
+        fcmp(vf, rd, rn, rm, ge);
+        break;
+      case NEON_FCMGT:
+        fcmp(vf, rd, rn, rm, gt);
+        break;
+      case NEON_FRECPS:
+        frecps(vf, rd, rn, rm);
+        break;
+      case NEON_FRSQRTS:
+        frsqrts(vf, rd, rn, rm);
+        break;
+      case NEON_FABD:
+        fabd(vf, rd, rn, rm);
+        break;
+      case NEON_FADDP:
+        faddp(vf, rd, rn, rm);
+        break;
+      case NEON_FMAXP:
+        fmaxp(vf, rd, rn, rm);
+        break;
+      case NEON_FMAXNMP:
+        fmaxnmp(vf, rd, rn, rm);
+        break;
+      case NEON_FMINP:
+        fminp(vf, rd, rn, rm);
+        break;
+      case NEON_FMINNMP:
+        fminnmp(vf, rd, rn, rm);
+        break;
       default:
         VIXL_UNIMPLEMENTED();
     }
   } else {
     VectorFormat vf = nfd.GetVectorFormat();
     switch (instr->Mask(NEON3SameMask)) {
-      case NEON_ADD:   add(vf, rd, rn, rm);  break;
-      case NEON_ADDP:  addp(vf, rd, rn, rm); break;
-      case NEON_CMEQ:  cmp(vf, rd, rn, rm, eq); break;
-      case NEON_CMGE:  cmp(vf, rd, rn, rm, ge); break;
-      case NEON_CMGT:  cmp(vf, rd, rn, rm, gt); break;
-      case NEON_CMHI:  cmp(vf, rd, rn, rm, hi); break;
-      case NEON_CMHS:  cmp(vf, rd, rn, rm, hs); break;
-      case NEON_CMTST: cmptst(vf, rd, rn, rm); break;
-      case NEON_MLS:   mls(vf, rd, rn, rm); break;
-      case NEON_MLA:   mla(vf, rd, rn, rm); break;
-      case NEON_MUL:   mul(vf, rd, rn, rm); break;
-      case NEON_PMUL:  pmul(vf, rd, rn, rm); break;
-      case NEON_SMAX:  smax(vf, rd, rn, rm); break;
-      case NEON_SMAXP: smaxp(vf, rd, rn, rm); break;
-      case NEON_SMIN:  smin(vf, rd, rn, rm); break;
-      case NEON_SMINP: sminp(vf, rd, rn, rm); break;
-      case NEON_SUB:   sub(vf, rd, rn, rm);  break;
-      case NEON_UMAX:  umax(vf, rd, rn, rm); break;
-      case NEON_UMAXP: umaxp(vf, rd, rn, rm); break;
-      case NEON_UMIN:  umin(vf, rd, rn, rm); break;
-      case NEON_UMINP: uminp(vf, rd, rn, rm); break;
-      case NEON_SSHL:  sshl(vf, rd, rn, rm); break;
-      case NEON_USHL:  ushl(vf, rd, rn, rm); break;
-      case NEON_SABD:  absdiff(vf, rd, rn, rm, true); break;
-      case NEON_UABD:  absdiff(vf, rd, rn, rm, false); break;
-      case NEON_SABA:  saba(vf, rd, rn, rm); break;
-      case NEON_UABA:  uaba(vf, rd, rn, rm); break;
-      case NEON_UQADD: add(vf, rd, rn, rm).UnsignedSaturate(vf); break;
-      case NEON_SQADD: add(vf, rd, rn, rm).SignedSaturate(vf); break;
-      case NEON_UQSUB: sub(vf, rd, rn, rm).UnsignedSaturate(vf); break;
-      case NEON_SQSUB: sub(vf, rd, rn, rm).SignedSaturate(vf); break;
-      case NEON_SQDMULH:  sqdmulh(vf, rd, rn, rm); break;
-      case NEON_SQRDMULH: sqrdmulh(vf, rd, rn, rm); break;
-      case NEON_UQSHL: ushl(vf, rd, rn, rm).UnsignedSaturate(vf); break;
-      case NEON_SQSHL: sshl(vf, rd, rn, rm).SignedSaturate(vf); break;
-      case NEON_URSHL: ushl(vf, rd, rn, rm).Round(vf); break;
-      case NEON_SRSHL: sshl(vf, rd, rn, rm).Round(vf); break;
+      case NEON_ADD:
+        add(vf, rd, rn, rm);
+        break;
+      case NEON_ADDP:
+        addp(vf, rd, rn, rm);
+        break;
+      case NEON_CMEQ:
+        cmp(vf, rd, rn, rm, eq);
+        break;
+      case NEON_CMGE:
+        cmp(vf, rd, rn, rm, ge);
+        break;
+      case NEON_CMGT:
+        cmp(vf, rd, rn, rm, gt);
+        break;
+      case NEON_CMHI:
+        cmp(vf, rd, rn, rm, hi);
+        break;
+      case NEON_CMHS:
+        cmp(vf, rd, rn, rm, hs);
+        break;
+      case NEON_CMTST:
+        cmptst(vf, rd, rn, rm);
+        break;
+      case NEON_MLS:
+        mls(vf, rd, rn, rm);
+        break;
+      case NEON_MLA:
+        mla(vf, rd, rn, rm);
+        break;
+      case NEON_MUL:
+        mul(vf, rd, rn, rm);
+        break;
+      case NEON_PMUL:
+        pmul(vf, rd, rn, rm);
+        break;
+      case NEON_SMAX:
+        smax(vf, rd, rn, rm);
+        break;
+      case NEON_SMAXP:
+        smaxp(vf, rd, rn, rm);
+        break;
+      case NEON_SMIN:
+        smin(vf, rd, rn, rm);
+        break;
+      case NEON_SMINP:
+        sminp(vf, rd, rn, rm);
+        break;
+      case NEON_SUB:
+        sub(vf, rd, rn, rm);
+        break;
+      case NEON_UMAX:
+        umax(vf, rd, rn, rm);
+        break;
+      case NEON_UMAXP:
+        umaxp(vf, rd, rn, rm);
+        break;
+      case NEON_UMIN:
+        umin(vf, rd, rn, rm);
+        break;
+      case NEON_UMINP:
+        uminp(vf, rd, rn, rm);
+        break;
+      case NEON_SSHL:
+        sshl(vf, rd, rn, rm);
+        break;
+      case NEON_USHL:
+        ushl(vf, rd, rn, rm);
+        break;
+      case NEON_SABD:
+        absdiff(vf, rd, rn, rm, true);
+        break;
+      case NEON_UABD:
+        absdiff(vf, rd, rn, rm, false);
+        break;
+      case NEON_SABA:
+        saba(vf, rd, rn, rm);
+        break;
+      case NEON_UABA:
+        uaba(vf, rd, rn, rm);
+        break;
+      case NEON_UQADD:
+        add(vf, rd, rn, rm).UnsignedSaturate(vf);
+        break;
+      case NEON_SQADD:
+        add(vf, rd, rn, rm).SignedSaturate(vf);
+        break;
+      case NEON_UQSUB:
+        sub(vf, rd, rn, rm).UnsignedSaturate(vf);
+        break;
+      case NEON_SQSUB:
+        sub(vf, rd, rn, rm).SignedSaturate(vf);
+        break;
+      case NEON_SQDMULH:
+        sqdmulh(vf, rd, rn, rm);
+        break;
+      case NEON_SQRDMULH:
+        sqrdmulh(vf, rd, rn, rm);
+        break;
+      case NEON_UQSHL:
+        ushl(vf, rd, rn, rm).UnsignedSaturate(vf);
+        break;
+      case NEON_SQSHL:
+        sshl(vf, rd, rn, rm).SignedSaturate(vf);
+        break;
+      case NEON_URSHL:
+        ushl(vf, rd, rn, rm).Round(vf);
+        break;
+      case NEON_SRSHL:
+        sshl(vf, rd, rn, rm).Round(vf);
+        break;
       case NEON_UQRSHL:
         ushl(vf, rd, rn, rm).Round(vf).UnsignedSaturate(vf);
         break;
@@ -2696,58 +3342,162 @@
   SimVRegister& rm = vreg(instr->Rm());
 
   switch (instr->Mask(NEON3DifferentMask)) {
-    case NEON_PMULL:    pmull(vf_l, rd, rn, rm); break;
-    case NEON_PMULL2:   pmull2(vf_l, rd, rn, rm); break;
-    case NEON_UADDL:    uaddl(vf_l, rd, rn, rm); break;
-    case NEON_UADDL2:   uaddl2(vf_l, rd, rn, rm); break;
-    case NEON_SADDL:    saddl(vf_l, rd, rn, rm); break;
-    case NEON_SADDL2:   saddl2(vf_l, rd, rn, rm); break;
-    case NEON_USUBL:    usubl(vf_l, rd, rn, rm); break;
-    case NEON_USUBL2:   usubl2(vf_l, rd, rn, rm); break;
-    case NEON_SSUBL:    ssubl(vf_l, rd, rn, rm); break;
-    case NEON_SSUBL2:   ssubl2(vf_l, rd, rn, rm); break;
-    case NEON_SABAL:    sabal(vf_l, rd, rn, rm); break;
-    case NEON_SABAL2:   sabal2(vf_l, rd, rn, rm); break;
-    case NEON_UABAL:    uabal(vf_l, rd, rn, rm); break;
-    case NEON_UABAL2:   uabal2(vf_l, rd, rn, rm); break;
-    case NEON_SABDL:    sabdl(vf_l, rd, rn, rm); break;
-    case NEON_SABDL2:   sabdl2(vf_l, rd, rn, rm); break;
-    case NEON_UABDL:    uabdl(vf_l, rd, rn, rm); break;
-    case NEON_UABDL2:   uabdl2(vf_l, rd, rn, rm); break;
-    case NEON_SMLAL:    smlal(vf_l, rd, rn, rm); break;
-    case NEON_SMLAL2:   smlal2(vf_l, rd, rn, rm); break;
-    case NEON_UMLAL:    umlal(vf_l, rd, rn, rm); break;
-    case NEON_UMLAL2:   umlal2(vf_l, rd, rn, rm); break;
-    case NEON_SMLSL:    smlsl(vf_l, rd, rn, rm); break;
-    case NEON_SMLSL2:   smlsl2(vf_l, rd, rn, rm); break;
-    case NEON_UMLSL:    umlsl(vf_l, rd, rn, rm); break;
-    case NEON_UMLSL2:   umlsl2(vf_l, rd, rn, rm); break;
-    case NEON_SMULL:    smull(vf_l, rd, rn, rm); break;
-    case NEON_SMULL2:   smull2(vf_l, rd, rn, rm); break;
-    case NEON_UMULL:    umull(vf_l, rd, rn, rm); break;
-    case NEON_UMULL2:   umull2(vf_l, rd, rn, rm); break;
-    case NEON_SQDMLAL:  sqdmlal(vf_l, rd, rn, rm); break;
-    case NEON_SQDMLAL2: sqdmlal2(vf_l, rd, rn, rm); break;
-    case NEON_SQDMLSL:  sqdmlsl(vf_l, rd, rn, rm); break;
-    case NEON_SQDMLSL2: sqdmlsl2(vf_l, rd, rn, rm); break;
-    case NEON_SQDMULL:  sqdmull(vf_l, rd, rn, rm); break;
-    case NEON_SQDMULL2: sqdmull2(vf_l, rd, rn, rm); break;
-    case NEON_UADDW:    uaddw(vf_l, rd, rn, rm); break;
-    case NEON_UADDW2:   uaddw2(vf_l, rd, rn, rm); break;
-    case NEON_SADDW:    saddw(vf_l, rd, rn, rm); break;
-    case NEON_SADDW2:   saddw2(vf_l, rd, rn, rm); break;
-    case NEON_USUBW:    usubw(vf_l, rd, rn, rm); break;
-    case NEON_USUBW2:   usubw2(vf_l, rd, rn, rm); break;
-    case NEON_SSUBW:    ssubw(vf_l, rd, rn, rm); break;
-    case NEON_SSUBW2:   ssubw2(vf_l, rd, rn, rm); break;
-    case NEON_ADDHN:    addhn(vf, rd, rn, rm); break;
-    case NEON_ADDHN2:   addhn2(vf, rd, rn, rm); break;
-    case NEON_RADDHN:   raddhn(vf, rd, rn, rm); break;
-    case NEON_RADDHN2:  raddhn2(vf, rd, rn, rm); break;
-    case NEON_SUBHN:    subhn(vf, rd, rn, rm); break;
-    case NEON_SUBHN2:   subhn2(vf, rd, rn, rm); break;
-    case NEON_RSUBHN:   rsubhn(vf, rd, rn, rm); break;
-    case NEON_RSUBHN2:  rsubhn2(vf, rd, rn, rm); break;
+    case NEON_PMULL:
+      pmull(vf_l, rd, rn, rm);
+      break;
+    case NEON_PMULL2:
+      pmull2(vf_l, rd, rn, rm);
+      break;
+    case NEON_UADDL:
+      uaddl(vf_l, rd, rn, rm);
+      break;
+    case NEON_UADDL2:
+      uaddl2(vf_l, rd, rn, rm);
+      break;
+    case NEON_SADDL:
+      saddl(vf_l, rd, rn, rm);
+      break;
+    case NEON_SADDL2:
+      saddl2(vf_l, rd, rn, rm);
+      break;
+    case NEON_USUBL:
+      usubl(vf_l, rd, rn, rm);
+      break;
+    case NEON_USUBL2:
+      usubl2(vf_l, rd, rn, rm);
+      break;
+    case NEON_SSUBL:
+      ssubl(vf_l, rd, rn, rm);
+      break;
+    case NEON_SSUBL2:
+      ssubl2(vf_l, rd, rn, rm);
+      break;
+    case NEON_SABAL:
+      sabal(vf_l, rd, rn, rm);
+      break;
+    case NEON_SABAL2:
+      sabal2(vf_l, rd, rn, rm);
+      break;
+    case NEON_UABAL:
+      uabal(vf_l, rd, rn, rm);
+      break;
+    case NEON_UABAL2:
+      uabal2(vf_l, rd, rn, rm);
+      break;
+    case NEON_SABDL:
+      sabdl(vf_l, rd, rn, rm);
+      break;
+    case NEON_SABDL2:
+      sabdl2(vf_l, rd, rn, rm);
+      break;
+    case NEON_UABDL:
+      uabdl(vf_l, rd, rn, rm);
+      break;
+    case NEON_UABDL2:
+      uabdl2(vf_l, rd, rn, rm);
+      break;
+    case NEON_SMLAL:
+      smlal(vf_l, rd, rn, rm);
+      break;
+    case NEON_SMLAL2:
+      smlal2(vf_l, rd, rn, rm);
+      break;
+    case NEON_UMLAL:
+      umlal(vf_l, rd, rn, rm);
+      break;
+    case NEON_UMLAL2:
+      umlal2(vf_l, rd, rn, rm);
+      break;
+    case NEON_SMLSL:
+      smlsl(vf_l, rd, rn, rm);
+      break;
+    case NEON_SMLSL2:
+      smlsl2(vf_l, rd, rn, rm);
+      break;
+    case NEON_UMLSL:
+      umlsl(vf_l, rd, rn, rm);
+      break;
+    case NEON_UMLSL2:
+      umlsl2(vf_l, rd, rn, rm);
+      break;
+    case NEON_SMULL:
+      smull(vf_l, rd, rn, rm);
+      break;
+    case NEON_SMULL2:
+      smull2(vf_l, rd, rn, rm);
+      break;
+    case NEON_UMULL:
+      umull(vf_l, rd, rn, rm);
+      break;
+    case NEON_UMULL2:
+      umull2(vf_l, rd, rn, rm);
+      break;
+    case NEON_SQDMLAL:
+      sqdmlal(vf_l, rd, rn, rm);
+      break;
+    case NEON_SQDMLAL2:
+      sqdmlal2(vf_l, rd, rn, rm);
+      break;
+    case NEON_SQDMLSL:
+      sqdmlsl(vf_l, rd, rn, rm);
+      break;
+    case NEON_SQDMLSL2:
+      sqdmlsl2(vf_l, rd, rn, rm);
+      break;
+    case NEON_SQDMULL:
+      sqdmull(vf_l, rd, rn, rm);
+      break;
+    case NEON_SQDMULL2:
+      sqdmull2(vf_l, rd, rn, rm);
+      break;
+    case NEON_UADDW:
+      uaddw(vf_l, rd, rn, rm);
+      break;
+    case NEON_UADDW2:
+      uaddw2(vf_l, rd, rn, rm);
+      break;
+    case NEON_SADDW:
+      saddw(vf_l, rd, rn, rm);
+      break;
+    case NEON_SADDW2:
+      saddw2(vf_l, rd, rn, rm);
+      break;
+    case NEON_USUBW:
+      usubw(vf_l, rd, rn, rm);
+      break;
+    case NEON_USUBW2:
+      usubw2(vf_l, rd, rn, rm);
+      break;
+    case NEON_SSUBW:
+      ssubw(vf_l, rd, rn, rm);
+      break;
+    case NEON_SSUBW2:
+      ssubw2(vf_l, rd, rn, rm);
+      break;
+    case NEON_ADDHN:
+      addhn(vf, rd, rn, rm);
+      break;
+    case NEON_ADDHN2:
+      addhn2(vf, rd, rn, rm);
+      break;
+    case NEON_RADDHN:
+      raddhn(vf, rd, rn, rm);
+      break;
+    case NEON_RADDHN2:
+      raddhn2(vf, rd, rn, rm);
+      break;
+    case NEON_SUBHN:
+      subhn(vf, rd, rn, rm);
+      break;
+    case NEON_SUBHN2:
+      subhn2(vf, rd, rn, rm);
+      break;
+    case NEON_RSUBHN:
+      rsubhn(vf, rd, rn, rm);
+      break;
+    case NEON_RSUBHN2:
+      rsubhn2(vf, rd, rn, rm);
+      break;
     default:
       VIXL_UNIMPLEMENTED();
   }
@@ -2765,10 +3515,18 @@
     VectorFormat vf = nfd.GetVectorFormat(nfd.FPFormatMap());
 
     switch (instr->Mask(NEONAcrossLanesFPMask)) {
-      case NEON_FMAXV: fmaxv(vf, rd, rn); break;
-      case NEON_FMINV: fminv(vf, rd, rn); break;
-      case NEON_FMAXNMV: fmaxnmv(vf, rd, rn); break;
-      case NEON_FMINNMV: fminnmv(vf, rd, rn); break;
+      case NEON_FMAXV:
+        fmaxv(vf, rd, rn);
+        break;
+      case NEON_FMINV:
+        fminv(vf, rd, rn);
+        break;
+      case NEON_FMAXNMV:
+        fmaxnmv(vf, rd, rn);
+        break;
+      case NEON_FMINNMV:
+        fminnmv(vf, rd, rn);
+        break;
       default:
         VIXL_UNIMPLEMENTED();
     }
@@ -2776,13 +3534,27 @@
     VectorFormat vf = nfd.GetVectorFormat();
 
     switch (instr->Mask(NEONAcrossLanesMask)) {
-      case NEON_ADDV:   addv(vf, rd, rn); break;
-      case NEON_SMAXV:  smaxv(vf, rd, rn); break;
-      case NEON_SMINV:  sminv(vf, rd, rn); break;
-      case NEON_UMAXV:  umaxv(vf, rd, rn); break;
-      case NEON_UMINV:  uminv(vf, rd, rn); break;
-      case NEON_SADDLV: saddlv(vf, rd, rn); break;
-      case NEON_UADDLV: uaddlv(vf, rd, rn); break;
+      case NEON_ADDV:
+        addv(vf, rd, rn);
+        break;
+      case NEON_SMAXV:
+        smaxv(vf, rd, rn);
+        break;
+      case NEON_SMINV:
+        sminv(vf, rd, rn);
+        break;
+      case NEON_UMAXV:
+        umaxv(vf, rd, rn);
+        break;
+      case NEON_UMINV:
+        uminv(vf, rd, rn);
+        break;
+      case NEON_SADDLV:
+        saddlv(vf, rd, rn);
+        break;
+      case NEON_UADDLV:
+        uaddlv(vf, rd, rn);
+        break;
       default:
         VIXL_UNIMPLEMENTED();
     }
@@ -2808,11 +3580,26 @@
   }
 
   switch (instr->Mask(NEONByIndexedElementMask)) {
-    case NEON_MUL_byelement: Op = &Simulator::mul; vf = vf_r; break;
-    case NEON_MLA_byelement: Op = &Simulator::mla; vf = vf_r; break;
-    case NEON_MLS_byelement: Op = &Simulator::mls; vf = vf_r; break;
-    case NEON_SQDMULH_byelement: Op = &Simulator::sqdmulh; vf = vf_r; break;
-    case NEON_SQRDMULH_byelement: Op = &Simulator::sqrdmulh; vf = vf_r; break;
+    case NEON_MUL_byelement:
+      Op = &Simulator::mul;
+      vf = vf_r;
+      break;
+    case NEON_MLA_byelement:
+      Op = &Simulator::mla;
+      vf = vf_r;
+      break;
+    case NEON_MLS_byelement:
+      Op = &Simulator::mls;
+      vf = vf_r;
+      break;
+    case NEON_SQDMULH_byelement:
+      Op = &Simulator::sqdmulh;
+      vf = vf_r;
+      break;
+    case NEON_SQRDMULH_byelement:
+      Op = &Simulator::sqrdmulh;
+      vf = vf_r;
+      break;
     case NEON_SMULL_byelement:
       if (instr->Mask(NEON_Q)) {
         Op = &Simulator::smull2;
@@ -2885,11 +3672,20 @@
       vf = nfd.GetVectorFormat(nfd.FPFormatMap());
 
       switch (instr->Mask(NEONByIndexedElementFPMask)) {
-        case NEON_FMUL_byelement: Op = &Simulator::fmul; break;
-        case NEON_FMLA_byelement: Op = &Simulator::fmla; break;
-        case NEON_FMLS_byelement: Op = &Simulator::fmls; break;
-        case NEON_FMULX_byelement: Op = &Simulator::fmulx; break;
-        default: VIXL_UNIMPLEMENTED();
+        case NEON_FMUL_byelement:
+          Op = &Simulator::fmul;
+          break;
+        case NEON_FMLA_byelement:
+          Op = &Simulator::fmla;
+          break;
+        case NEON_FMLS_byelement:
+          Op = &Simulator::fmls;
+          break;
+        case NEON_FMULX_byelement:
+          Op = &Simulator::fmulx;
+          break;
+        default:
+          VIXL_UNIMPLEMENTED();
       }
   }
 
@@ -2979,27 +3775,38 @@
   // and PostIndex addressing.
   switch (instr->Mask(NEONLoadStoreMultiStructPostIndexMask)) {
     case NEON_LD1_4v:
-    case NEON_LD1_4v_post: ld1(vf, vreg(reg[3]), addr[3]); count++;
+    case NEON_LD1_4v_post:
+      ld1(vf, vreg(reg[3]), addr[3]);
+      count++;
       VIXL_FALLTHROUGH();
     case NEON_LD1_3v:
-    case NEON_LD1_3v_post: ld1(vf, vreg(reg[2]), addr[2]); count++;
+    case NEON_LD1_3v_post:
+      ld1(vf, vreg(reg[2]), addr[2]);
+      count++;
       VIXL_FALLTHROUGH();
     case NEON_LD1_2v:
-    case NEON_LD1_2v_post: ld1(vf, vreg(reg[1]), addr[1]); count++;
+    case NEON_LD1_2v_post:
+      ld1(vf, vreg(reg[1]), addr[1]);
+      count++;
       VIXL_FALLTHROUGH();
     case NEON_LD1_1v:
     case NEON_LD1_1v_post:
       ld1(vf, vreg(reg[0]), addr[0]);
-      log_read = true;
       break;
     case NEON_ST1_4v:
-    case NEON_ST1_4v_post: st1(vf, vreg(reg[3]), addr[3]); count++;
+    case NEON_ST1_4v_post:
+      st1(vf, vreg(reg[3]), addr[3]);
+      count++;
       VIXL_FALLTHROUGH();
     case NEON_ST1_3v:
-    case NEON_ST1_3v_post: st1(vf, vreg(reg[2]), addr[2]); count++;
+    case NEON_ST1_3v_post:
+      st1(vf, vreg(reg[2]), addr[2]);
+      count++;
       VIXL_FALLTHROUGH();
     case NEON_ST1_2v:
-    case NEON_ST1_2v_post: st1(vf, vreg(reg[1]), addr[1]); count++;
+    case NEON_ST1_2v_post:
+      st1(vf, vreg(reg[1]), addr[1]);
+      count++;
       VIXL_FALLTHROUGH();
     case NEON_ST1_1v:
     case NEON_ST1_1v_post:
@@ -3028,17 +3835,16 @@
       break;
     case NEON_ST4:
     case NEON_ST4_post:
-      st4(vf, vreg(reg[0]), vreg(reg[1]), vreg(reg[2]), vreg(reg[3]),
-          addr[0]);
+      st4(vf, vreg(reg[0]), vreg(reg[1]), vreg(reg[2]), vreg(reg[3]), addr[0]);
       count = 4;
       break;
     case NEON_LD4_post:
     case NEON_LD4:
-      ld4(vf, vreg(reg[0]), vreg(reg[1]), vreg(reg[2]), vreg(reg[3]),
-          addr[0]);
+      ld4(vf, vreg(reg[0]), vreg(reg[1]), vreg(reg[2]), vreg(reg[3]), addr[0]);
       count = 4;
       break;
-    default: VIXL_UNIMPLEMENTED();
+    default:
+      VIXL_UNIMPLEMENTED();
   }
 
   // Explicitly log the register update whilst we have type information.
@@ -3058,8 +3864,8 @@
     int rm = instr->Rm();
     // The immediate post index addressing mode is indicated by rm = 31.
     // The immediate is implied by the number of vector registers used.
-    addr_base += (rm == 31) ? RegisterSizeInBytesFromFormat(vf) * count
-                            : xreg(rm);
+    addr_base +=
+        (rm == 31) ? RegisterSizeInBytesFromFormat(vf) * count : xreg(rm);
     set_xreg(instr->Rn(), addr_base);
   } else {
     VIXL_ASSERT(addr_mode == Offset);
@@ -3106,7 +3912,8 @@
     case NEON_LD3_b:
     case NEON_LD3_b_post:
     case NEON_LD4_b:
-    case NEON_LD4_b_post: do_load = true;
+    case NEON_LD4_b_post:
+      do_load = true;
       VIXL_FALLTHROUGH();
     case NEON_ST1_b:
     case NEON_ST1_b_post:
@@ -3115,7 +3922,8 @@
     case NEON_ST3_b:
     case NEON_ST3_b_post:
     case NEON_ST4_b:
-    case NEON_ST4_b_post: break;
+    case NEON_ST4_b_post:
+      break;
 
     case NEON_LD1_h:
     case NEON_LD1_h_post:
@@ -3124,7 +3932,8 @@
     case NEON_LD3_h:
     case NEON_LD3_h_post:
     case NEON_LD4_h:
-    case NEON_LD4_h_post: do_load = true;
+    case NEON_LD4_h_post:
+      do_load = true;
       VIXL_FALLTHROUGH();
     case NEON_ST1_h:
     case NEON_ST1_h_post:
@@ -3133,7 +3942,9 @@
     case NEON_ST3_h:
     case NEON_ST3_h_post:
     case NEON_ST4_h:
-    case NEON_ST4_h_post: vf = kFormat8H; break;
+    case NEON_ST4_h_post:
+      vf = kFormat8H;
+      break;
     case NEON_LD1_s:
     case NEON_LD1_s_post:
     case NEON_LD2_s:
@@ -3141,7 +3952,8 @@
     case NEON_LD3_s:
     case NEON_LD3_s_post:
     case NEON_LD4_s:
-    case NEON_LD4_s_post: do_load = true;
+    case NEON_LD4_s_post:
+      do_load = true;
       VIXL_FALLTHROUGH();
     case NEON_ST1_s:
     case NEON_ST1_s_post:
@@ -3152,11 +3964,11 @@
     case NEON_ST4_s:
     case NEON_ST4_s_post: {
       VIXL_STATIC_ASSERT((NEON_LD1_s | (1 << NEONLSSize_offset)) == NEON_LD1_d);
-      VIXL_STATIC_ASSERT(
-          (NEON_LD1_s_post | (1 << NEONLSSize_offset)) == NEON_LD1_d_post);
+      VIXL_STATIC_ASSERT((NEON_LD1_s_post | (1 << NEONLSSize_offset)) ==
+                         NEON_LD1_d_post);
       VIXL_STATIC_ASSERT((NEON_ST1_s | (1 << NEONLSSize_offset)) == NEON_ST1_d);
-      VIXL_STATIC_ASSERT(
-          (NEON_ST1_s_post | (1 << NEONLSSize_offset)) == NEON_ST1_d_post);
+      VIXL_STATIC_ASSERT((NEON_ST1_s_post | (1 << NEONLSSize_offset)) ==
+                         NEON_ST1_d_post);
       vf = ((instr->NEONLSSize() & 1) == 0) ? kFormat4S : kFormat2D;
       break;
     }
@@ -3198,7 +4010,8 @@
       do_load = true;
       break;
     }
-    default: VIXL_UNIMPLEMENTED();
+    default:
+      VIXL_UNIMPLEMENTED();
   }
 
   PrintRegisterFormat print_format =
@@ -3267,7 +4080,8 @@
         LogVWrite(addr + (3 * esize), rt4, print_format, lane);
       }
       break;
-    default: VIXL_UNIMPLEMENTED();
+    default:
+      VIXL_UNIMPLEMENTED();
   }
 
   if (addr_mode == PostIndex) {
@@ -3299,7 +4113,7 @@
   int cmode_0 = cmode & 1;
   int q = instr->NEONQ();
   int op_bit = instr->NEONModImmOp();
-  uint64_t imm8  = instr->ImmNEONabcdefgh();
+  uint64_t imm8 = instr->ImmNEONabcdefgh();
 
   // Find the format and immediate value
   uint64_t imm = 0;
@@ -3320,7 +4134,7 @@
     case 0x6:
       vform = (q == 1) ? kFormat4S : kFormat2S;
       if (cmode_0 == 0) {
-        imm = imm8 << 8  | 0x000000ff;
+        imm = imm8 << 8 | 0x000000ff;
       } else {
         imm = imm8 << 16 | 0x0000ffff;
       }
@@ -3350,7 +4164,9 @@
         }
       }
       break;
-    default: VIXL_UNREACHABLE(); break;
+    default:
+      VIXL_UNREACHABLE();
+      break;
   }
 
   // Find the operation
@@ -3369,15 +4185,15 @@
         op = op_bit ? NEONModifiedImmediate_BIC : NEONModifiedImmediate_ORR;
       }
     } else {  // cmode<2> == '1'
-       if (cmode_1 == 0) {
-         op = op_bit ? NEONModifiedImmediate_MVNI : NEONModifiedImmediate_MOVI;
-       } else {  // cmode<1> == '1'
-         if (cmode_0 == 0) {
-           op = NEONModifiedImmediate_MOVI;
-         } else {  // cmode<0> == '1'
-           op = NEONModifiedImmediate_MOVI;
-         }
-       }
+      if (cmode_1 == 0) {
+        op = op_bit ? NEONModifiedImmediate_MVNI : NEONModifiedImmediate_MOVI;
+      } else {  // cmode<1> == '1'
+        if (cmode_0 == 0) {
+          op = NEONModifiedImmediate_MOVI;
+        } else {  // cmode<0> == '1'
+          op = NEONModifiedImmediate_MOVI;
+        }
+      }
     }
   }
 
@@ -3386,7 +4202,7 @@
     orr(vform, rd, rd, imm);
   } else if (op == NEONModifiedImmediate_BIC) {
     bic(vform, rd, rd, imm);
-  } else  if (op == NEONModifiedImmediate_MOVI) {
+  } else if (op == NEONModifiedImmediate_MOVI) {
     movi(vform, rd, imm);
   } else if (op == NEONModifiedImmediate_MVNI) {
     mvni(vform, rd, imm);
@@ -3407,18 +4223,42 @@
     // These instructions all use a two bit size field, except NOT and RBIT,
     // which use the field to encode the operation.
     switch (instr->Mask(NEONScalar2RegMiscMask)) {
-      case NEON_CMEQ_zero_scalar: cmp(vf, rd, rn, 0, eq); break;
-      case NEON_CMGE_zero_scalar: cmp(vf, rd, rn, 0, ge); break;
-      case NEON_CMGT_zero_scalar: cmp(vf, rd, rn, 0, gt); break;
-      case NEON_CMLT_zero_scalar: cmp(vf, rd, rn, 0, lt); break;
-      case NEON_CMLE_zero_scalar: cmp(vf, rd, rn, 0, le); break;
-      case NEON_ABS_scalar:       abs(vf, rd, rn); break;
-      case NEON_SQABS_scalar:     abs(vf, rd, rn).SignedSaturate(vf); break;
-      case NEON_NEG_scalar:       neg(vf, rd, rn); break;
-      case NEON_SQNEG_scalar:     neg(vf, rd, rn).SignedSaturate(vf); break;
-      case NEON_SUQADD_scalar:    suqadd(vf, rd, rn); break;
-      case NEON_USQADD_scalar:    usqadd(vf, rd, rn); break;
-      default: VIXL_UNIMPLEMENTED(); break;
+      case NEON_CMEQ_zero_scalar:
+        cmp(vf, rd, rn, 0, eq);
+        break;
+      case NEON_CMGE_zero_scalar:
+        cmp(vf, rd, rn, 0, ge);
+        break;
+      case NEON_CMGT_zero_scalar:
+        cmp(vf, rd, rn, 0, gt);
+        break;
+      case NEON_CMLT_zero_scalar:
+        cmp(vf, rd, rn, 0, lt);
+        break;
+      case NEON_CMLE_zero_scalar:
+        cmp(vf, rd, rn, 0, le);
+        break;
+      case NEON_ABS_scalar:
+        abs(vf, rd, rn);
+        break;
+      case NEON_SQABS_scalar:
+        abs(vf, rd, rn).SignedSaturate(vf);
+        break;
+      case NEON_NEG_scalar:
+        neg(vf, rd, rn);
+        break;
+      case NEON_SQNEG_scalar:
+        neg(vf, rd, rn).SignedSaturate(vf);
+        break;
+      case NEON_SUQADD_scalar:
+        suqadd(vf, rd, rn);
+        break;
+      case NEON_USQADD_scalar:
+        usqadd(vf, rd, rn);
+        break;
+      default:
+        VIXL_UNIMPLEMENTED();
+        break;
     }
   } else {
     VectorFormat fpf = nfd.GetVectorFormat(nfd.FPScalarFormatMap());
@@ -3427,26 +4267,66 @@
     // These instructions all use a one bit size field, except SQXTUN, SQXTN
     // and UQXTN, which use a two bit size field.
     switch (instr->Mask(NEONScalar2RegMiscFPMask)) {
-      case NEON_FRECPE_scalar:     frecpe(fpf, rd, rn, fpcr_rounding); break;
-      case NEON_FRECPX_scalar:     frecpx(fpf, rd, rn); break;
-      case NEON_FRSQRTE_scalar:    frsqrte(fpf, rd, rn); break;
-      case NEON_FCMGT_zero_scalar: fcmp_zero(fpf, rd, rn, gt); break;
-      case NEON_FCMGE_zero_scalar: fcmp_zero(fpf, rd, rn, ge); break;
-      case NEON_FCMEQ_zero_scalar: fcmp_zero(fpf, rd, rn, eq); break;
-      case NEON_FCMLE_zero_scalar: fcmp_zero(fpf, rd, rn, le); break;
-      case NEON_FCMLT_zero_scalar: fcmp_zero(fpf, rd, rn, lt); break;
-      case NEON_SCVTF_scalar:      scvtf(fpf, rd, rn, 0, fpcr_rounding); break;
-      case NEON_UCVTF_scalar:      ucvtf(fpf, rd, rn, 0, fpcr_rounding); break;
-      case NEON_FCVTNS_scalar: fcvts(fpf, rd, rn, FPTieEven); break;
-      case NEON_FCVTNU_scalar: fcvtu(fpf, rd, rn, FPTieEven); break;
-      case NEON_FCVTPS_scalar: fcvts(fpf, rd, rn, FPPositiveInfinity); break;
-      case NEON_FCVTPU_scalar: fcvtu(fpf, rd, rn, FPPositiveInfinity); break;
-      case NEON_FCVTMS_scalar: fcvts(fpf, rd, rn, FPNegativeInfinity); break;
-      case NEON_FCVTMU_scalar: fcvtu(fpf, rd, rn, FPNegativeInfinity); break;
-      case NEON_FCVTZS_scalar: fcvts(fpf, rd, rn, FPZero); break;
-      case NEON_FCVTZU_scalar: fcvtu(fpf, rd, rn, FPZero); break;
-      case NEON_FCVTAS_scalar: fcvts(fpf, rd, rn, FPTieAway); break;
-      case NEON_FCVTAU_scalar: fcvtu(fpf, rd, rn, FPTieAway); break;
+      case NEON_FRECPE_scalar:
+        frecpe(fpf, rd, rn, fpcr_rounding);
+        break;
+      case NEON_FRECPX_scalar:
+        frecpx(fpf, rd, rn);
+        break;
+      case NEON_FRSQRTE_scalar:
+        frsqrte(fpf, rd, rn);
+        break;
+      case NEON_FCMGT_zero_scalar:
+        fcmp_zero(fpf, rd, rn, gt);
+        break;
+      case NEON_FCMGE_zero_scalar:
+        fcmp_zero(fpf, rd, rn, ge);
+        break;
+      case NEON_FCMEQ_zero_scalar:
+        fcmp_zero(fpf, rd, rn, eq);
+        break;
+      case NEON_FCMLE_zero_scalar:
+        fcmp_zero(fpf, rd, rn, le);
+        break;
+      case NEON_FCMLT_zero_scalar:
+        fcmp_zero(fpf, rd, rn, lt);
+        break;
+      case NEON_SCVTF_scalar:
+        scvtf(fpf, rd, rn, 0, fpcr_rounding);
+        break;
+      case NEON_UCVTF_scalar:
+        ucvtf(fpf, rd, rn, 0, fpcr_rounding);
+        break;
+      case NEON_FCVTNS_scalar:
+        fcvts(fpf, rd, rn, FPTieEven);
+        break;
+      case NEON_FCVTNU_scalar:
+        fcvtu(fpf, rd, rn, FPTieEven);
+        break;
+      case NEON_FCVTPS_scalar:
+        fcvts(fpf, rd, rn, FPPositiveInfinity);
+        break;
+      case NEON_FCVTPU_scalar:
+        fcvtu(fpf, rd, rn, FPPositiveInfinity);
+        break;
+      case NEON_FCVTMS_scalar:
+        fcvts(fpf, rd, rn, FPNegativeInfinity);
+        break;
+      case NEON_FCVTMU_scalar:
+        fcvtu(fpf, rd, rn, FPNegativeInfinity);
+        break;
+      case NEON_FCVTZS_scalar:
+        fcvts(fpf, rd, rn, FPZero);
+        break;
+      case NEON_FCVTZU_scalar:
+        fcvtu(fpf, rd, rn, FPZero);
+        break;
+      case NEON_FCVTAS_scalar:
+        fcvts(fpf, rd, rn, FPTieAway);
+        break;
+      case NEON_FCVTAU_scalar:
+        fcvtu(fpf, rd, rn, FPTieAway);
+        break;
       case NEON_FCVTXN_scalar:
         // Unlike all of the other FP instructions above, fcvtxn encodes dest
         // size S as size<0>=1. There's only one case, so we ignore the form.
@@ -3455,9 +4335,15 @@
         break;
       default:
         switch (instr->Mask(NEONScalar2RegMiscMask)) {
-          case NEON_SQXTN_scalar:  sqxtn(vf, rd, rn); break;
-          case NEON_UQXTN_scalar:  uqxtn(vf, rd, rn); break;
-          case NEON_SQXTUN_scalar: sqxtun(vf, rd, rn); break;
+          case NEON_SQXTN_scalar:
+            sqxtn(vf, rd, rn);
+            break;
+          case NEON_UQXTN_scalar:
+            uqxtn(vf, rd, rn);
+            break;
+          case NEON_SQXTUN_scalar:
+            sqxtun(vf, rd, rn);
+            break;
           default:
             VIXL_UNIMPLEMENTED();
         }
@@ -3474,9 +4360,15 @@
   SimVRegister& rn = vreg(instr->Rn());
   SimVRegister& rm = vreg(instr->Rm());
   switch (instr->Mask(NEONScalar3DiffMask)) {
-    case NEON_SQDMLAL_scalar: sqdmlal(vf, rd, rn, rm); break;
-    case NEON_SQDMLSL_scalar: sqdmlsl(vf, rd, rn, rm); break;
-    case NEON_SQDMULL_scalar: sqdmull(vf, rd, rn, rm); break;
+    case NEON_SQDMLAL_scalar:
+      sqdmlal(vf, rd, rn, rm);
+      break;
+    case NEON_SQDMLSL_scalar:
+      sqdmlsl(vf, rd, rn, rm);
+      break;
+    case NEON_SQDMULL_scalar:
+      sqdmull(vf, rd, rn, rm);
+      break;
     default:
       VIXL_UNIMPLEMENTED();
   }
@@ -3494,32 +4386,74 @@
   if (instr->Mask(NEONScalar3SameFPFMask) == NEONScalar3SameFPFixed) {
     vf = nfd.GetVectorFormat(nfd.FPScalarFormatMap());
     switch (instr->Mask(NEONScalar3SameFPMask)) {
-      case NEON_FMULX_scalar:   fmulx(vf, rd, rn, rm); break;
-      case NEON_FACGE_scalar:   fabscmp(vf, rd, rn, rm, ge); break;
-      case NEON_FACGT_scalar:   fabscmp(vf, rd, rn, rm, gt); break;
-      case NEON_FCMEQ_scalar:   fcmp(vf, rd, rn, rm, eq); break;
-      case NEON_FCMGE_scalar:   fcmp(vf, rd, rn, rm, ge); break;
-      case NEON_FCMGT_scalar:   fcmp(vf, rd, rn, rm, gt); break;
-      case NEON_FRECPS_scalar:  frecps(vf, rd, rn, rm); break;
-      case NEON_FRSQRTS_scalar: frsqrts(vf, rd, rn, rm); break;
-      case NEON_FABD_scalar:    fabd(vf, rd, rn, rm); break;
+      case NEON_FMULX_scalar:
+        fmulx(vf, rd, rn, rm);
+        break;
+      case NEON_FACGE_scalar:
+        fabscmp(vf, rd, rn, rm, ge);
+        break;
+      case NEON_FACGT_scalar:
+        fabscmp(vf, rd, rn, rm, gt);
+        break;
+      case NEON_FCMEQ_scalar:
+        fcmp(vf, rd, rn, rm, eq);
+        break;
+      case NEON_FCMGE_scalar:
+        fcmp(vf, rd, rn, rm, ge);
+        break;
+      case NEON_FCMGT_scalar:
+        fcmp(vf, rd, rn, rm, gt);
+        break;
+      case NEON_FRECPS_scalar:
+        frecps(vf, rd, rn, rm);
+        break;
+      case NEON_FRSQRTS_scalar:
+        frsqrts(vf, rd, rn, rm);
+        break;
+      case NEON_FABD_scalar:
+        fabd(vf, rd, rn, rm);
+        break;
       default:
         VIXL_UNIMPLEMENTED();
     }
   } else {
     switch (instr->Mask(NEONScalar3SameMask)) {
-      case NEON_ADD_scalar:      add(vf, rd, rn, rm); break;
-      case NEON_SUB_scalar:      sub(vf, rd, rn, rm); break;
-      case NEON_CMEQ_scalar:     cmp(vf, rd, rn, rm, eq); break;
-      case NEON_CMGE_scalar:     cmp(vf, rd, rn, rm, ge); break;
-      case NEON_CMGT_scalar:     cmp(vf, rd, rn, rm, gt); break;
-      case NEON_CMHI_scalar:     cmp(vf, rd, rn, rm, hi); break;
-      case NEON_CMHS_scalar:     cmp(vf, rd, rn, rm, hs); break;
-      case NEON_CMTST_scalar:    cmptst(vf, rd, rn, rm); break;
-      case NEON_USHL_scalar:     ushl(vf, rd, rn, rm); break;
-      case NEON_SSHL_scalar:     sshl(vf, rd, rn, rm); break;
-      case NEON_SQDMULH_scalar:  sqdmulh(vf, rd, rn, rm); break;
-      case NEON_SQRDMULH_scalar: sqrdmulh(vf, rd, rn, rm); break;
+      case NEON_ADD_scalar:
+        add(vf, rd, rn, rm);
+        break;
+      case NEON_SUB_scalar:
+        sub(vf, rd, rn, rm);
+        break;
+      case NEON_CMEQ_scalar:
+        cmp(vf, rd, rn, rm, eq);
+        break;
+      case NEON_CMGE_scalar:
+        cmp(vf, rd, rn, rm, ge);
+        break;
+      case NEON_CMGT_scalar:
+        cmp(vf, rd, rn, rm, gt);
+        break;
+      case NEON_CMHI_scalar:
+        cmp(vf, rd, rn, rm, hi);
+        break;
+      case NEON_CMHS_scalar:
+        cmp(vf, rd, rn, rm, hs);
+        break;
+      case NEON_CMTST_scalar:
+        cmptst(vf, rd, rn, rm);
+        break;
+      case NEON_USHL_scalar:
+        ushl(vf, rd, rn, rm);
+        break;
+      case NEON_SSHL_scalar:
+        sshl(vf, rd, rn, rm);
+        break;
+      case NEON_SQDMULH_scalar:
+        sqdmulh(vf, rd, rn, rm);
+        break;
+      case NEON_SQRDMULH_scalar:
+        sqrdmulh(vf, rd, rn, rm);
+        break;
       case NEON_UQADD_scalar:
         add(vf, rd, rn, rm).UnsignedSaturate(vf);
         break;
@@ -3574,9 +4508,15 @@
   }
 
   switch (instr->Mask(NEONScalarByIndexedElementMask)) {
-    case NEON_SQDMULL_byelement_scalar: Op = &Simulator::sqdmull; break;
-    case NEON_SQDMLAL_byelement_scalar: Op = &Simulator::sqdmlal; break;
-    case NEON_SQDMLSL_byelement_scalar: Op = &Simulator::sqdmlsl; break;
+    case NEON_SQDMULL_byelement_scalar:
+      Op = &Simulator::sqdmull;
+      break;
+    case NEON_SQDMLAL_byelement_scalar:
+      Op = &Simulator::sqdmlal;
+      break;
+    case NEON_SQDMLSL_byelement_scalar:
+      Op = &Simulator::sqdmlsl;
+      break;
     case NEON_SQDMULH_byelement_scalar:
       Op = &Simulator::sqdmulh;
       vf = vf_r;
@@ -3592,11 +4532,20 @@
         index = (index << 1) | instr->NEONL();
       }
       switch (instr->Mask(NEONScalarByIndexedElementFPMask)) {
-        case NEON_FMUL_byelement_scalar: Op = &Simulator::fmul; break;
-        case NEON_FMLA_byelement_scalar: Op = &Simulator::fmla; break;
-        case NEON_FMLS_byelement_scalar: Op = &Simulator::fmls; break;
-        case NEON_FMULX_byelement_scalar: Op = &Simulator::fmulx; break;
-        default: VIXL_UNIMPLEMENTED();
+        case NEON_FMUL_byelement_scalar:
+          Op = &Simulator::fmul;
+          break;
+        case NEON_FMLA_byelement_scalar:
+          Op = &Simulator::fmla;
+          break;
+        case NEON_FMLS_byelement_scalar:
+          Op = &Simulator::fmls;
+          break;
+        case NEON_FMULX_byelement_scalar:
+          Op = &Simulator::fmulx;
+          break;
+        default:
+          VIXL_UNIMPLEMENTED();
       }
   }
 
@@ -3629,12 +4578,24 @@
   SimVRegister& rd = vreg(instr->Rd());
   SimVRegister& rn = vreg(instr->Rn());
   switch (instr->Mask(NEONScalarPairwiseMask)) {
-    case NEON_ADDP_scalar:    addp(vf, rd, rn); break;
-    case NEON_FADDP_scalar:   faddp(vf, rd, rn); break;
-    case NEON_FMAXP_scalar:   fmaxp(vf, rd, rn); break;
-    case NEON_FMAXNMP_scalar: fmaxnmp(vf, rd, rn); break;
-    case NEON_FMINP_scalar:   fminp(vf, rd, rn); break;
-    case NEON_FMINNMP_scalar: fminnmp(vf, rd, rn); break;
+    case NEON_ADDP_scalar:
+      addp(vf, rd, rn);
+      break;
+    case NEON_FADDP_scalar:
+      faddp(vf, rd, rn);
+      break;
+    case NEON_FMAXP_scalar:
+      fmaxp(vf, rd, rn);
+      break;
+    case NEON_FMAXNMP_scalar:
+      fmaxnmp(vf, rd, rn);
+      break;
+    case NEON_FMINP_scalar:
+      fminp(vf, rd, rn);
+      break;
+    case NEON_FMINNMP_scalar:
+      fminnmp(vf, rd, rn);
+      break;
     default:
       VIXL_UNIMPLEMENTED();
   }
@@ -3646,11 +4607,23 @@
   SimVRegister& rn = vreg(instr->Rn());
   FPRounding fpcr_rounding = static_cast<FPRounding>(fpcr().RMode());
 
-  static const NEONFormatMap map = {
-    {22, 21, 20, 19},
-    {NF_UNDEF, NF_B, NF_H, NF_H, NF_S, NF_S, NF_S, NF_S,
-     NF_D,     NF_D, NF_D, NF_D, NF_D, NF_D, NF_D, NF_D}
-  };
+  static const NEONFormatMap map = {{22, 21, 20, 19},
+                                    {NF_UNDEF,
+                                     NF_B,
+                                     NF_H,
+                                     NF_H,
+                                     NF_S,
+                                     NF_S,
+                                     NF_S,
+                                     NF_S,
+                                     NF_D,
+                                     NF_D,
+                                     NF_D,
+                                     NF_D,
+                                     NF_D,
+                                     NF_D,
+                                     NF_D,
+                                     NF_D}};
   NEONFormatDecoder nfd(instr, &map);
   VectorFormat vf = nfd.GetVectorFormat();
 
@@ -3659,28 +4632,72 @@
   int right_shift = (16 << highestSetBit) - immhimmb;
   int left_shift = immhimmb - (8 << highestSetBit);
   switch (instr->Mask(NEONScalarShiftImmediateMask)) {
-    case NEON_SHL_scalar:       shl(vf, rd, rn, left_shift); break;
-    case NEON_SLI_scalar:       sli(vf, rd, rn, left_shift); break;
-    case NEON_SQSHL_imm_scalar: sqshl(vf, rd, rn, left_shift); break;
-    case NEON_UQSHL_imm_scalar: uqshl(vf, rd, rn, left_shift); break;
-    case NEON_SQSHLU_scalar:    sqshlu(vf, rd, rn, left_shift); break;
-    case NEON_SRI_scalar:       sri(vf, rd, rn, right_shift); break;
-    case NEON_SSHR_scalar:      sshr(vf, rd, rn, right_shift); break;
-    case NEON_USHR_scalar:      ushr(vf, rd, rn, right_shift); break;
-    case NEON_SRSHR_scalar:     sshr(vf, rd, rn, right_shift).Round(vf); break;
-    case NEON_URSHR_scalar:     ushr(vf, rd, rn, right_shift).Round(vf); break;
-    case NEON_SSRA_scalar:      ssra(vf, rd, rn, right_shift); break;
-    case NEON_USRA_scalar:      usra(vf, rd, rn, right_shift); break;
-    case NEON_SRSRA_scalar:     srsra(vf, rd, rn, right_shift); break;
-    case NEON_URSRA_scalar:     ursra(vf, rd, rn, right_shift); break;
-    case NEON_UQSHRN_scalar:    uqshrn(vf, rd, rn, right_shift); break;
-    case NEON_UQRSHRN_scalar:   uqrshrn(vf, rd, rn, right_shift); break;
-    case NEON_SQSHRN_scalar:    sqshrn(vf, rd, rn, right_shift); break;
-    case NEON_SQRSHRN_scalar:   sqrshrn(vf, rd, rn, right_shift); break;
-    case NEON_SQSHRUN_scalar:   sqshrun(vf, rd, rn, right_shift); break;
-    case NEON_SQRSHRUN_scalar:  sqrshrun(vf, rd, rn, right_shift); break;
-    case NEON_FCVTZS_imm_scalar: fcvts(vf, rd, rn, FPZero, right_shift); break;
-    case NEON_FCVTZU_imm_scalar: fcvtu(vf, rd, rn, FPZero, right_shift); break;
+    case NEON_SHL_scalar:
+      shl(vf, rd, rn, left_shift);
+      break;
+    case NEON_SLI_scalar:
+      sli(vf, rd, rn, left_shift);
+      break;
+    case NEON_SQSHL_imm_scalar:
+      sqshl(vf, rd, rn, left_shift);
+      break;
+    case NEON_UQSHL_imm_scalar:
+      uqshl(vf, rd, rn, left_shift);
+      break;
+    case NEON_SQSHLU_scalar:
+      sqshlu(vf, rd, rn, left_shift);
+      break;
+    case NEON_SRI_scalar:
+      sri(vf, rd, rn, right_shift);
+      break;
+    case NEON_SSHR_scalar:
+      sshr(vf, rd, rn, right_shift);
+      break;
+    case NEON_USHR_scalar:
+      ushr(vf, rd, rn, right_shift);
+      break;
+    case NEON_SRSHR_scalar:
+      sshr(vf, rd, rn, right_shift).Round(vf);
+      break;
+    case NEON_URSHR_scalar:
+      ushr(vf, rd, rn, right_shift).Round(vf);
+      break;
+    case NEON_SSRA_scalar:
+      ssra(vf, rd, rn, right_shift);
+      break;
+    case NEON_USRA_scalar:
+      usra(vf, rd, rn, right_shift);
+      break;
+    case NEON_SRSRA_scalar:
+      srsra(vf, rd, rn, right_shift);
+      break;
+    case NEON_URSRA_scalar:
+      ursra(vf, rd, rn, right_shift);
+      break;
+    case NEON_UQSHRN_scalar:
+      uqshrn(vf, rd, rn, right_shift);
+      break;
+    case NEON_UQRSHRN_scalar:
+      uqrshrn(vf, rd, rn, right_shift);
+      break;
+    case NEON_SQSHRN_scalar:
+      sqshrn(vf, rd, rn, right_shift);
+      break;
+    case NEON_SQRSHRN_scalar:
+      sqrshrn(vf, rd, rn, right_shift);
+      break;
+    case NEON_SQSHRUN_scalar:
+      sqshrun(vf, rd, rn, right_shift);
+      break;
+    case NEON_SQRSHRUN_scalar:
+      sqrshrun(vf, rd, rn, right_shift);
+      break;
+    case NEON_FCVTZS_imm_scalar:
+      fcvts(vf, rd, rn, FPZero, right_shift);
+      break;
+    case NEON_FCVTZU_imm_scalar:
+      fcvtu(vf, rd, rn, FPZero, right_shift);
+      break;
     case NEON_SCVTF_imm_scalar:
       scvtf(vf, rd, rn, right_shift, fpcr_rounding);
       break;
@@ -3700,21 +4717,46 @@
 
   // 00010->8B, 00011->16B, 001x0->4H, 001x1->8H,
   // 01xx0->2S, 01xx1->4S, 1xxx1->2D, all others undefined.
-  static const NEONFormatMap map = {
-    {22, 21, 20, 19, 30},
-    {NF_UNDEF, NF_UNDEF, NF_8B,    NF_16B, NF_4H,    NF_8H, NF_4H,    NF_8H,
-     NF_2S,    NF_4S,    NF_2S,    NF_4S,  NF_2S,    NF_4S, NF_2S,    NF_4S,
-     NF_UNDEF, NF_2D,    NF_UNDEF, NF_2D,  NF_UNDEF, NF_2D, NF_UNDEF, NF_2D,
-     NF_UNDEF, NF_2D,    NF_UNDEF, NF_2D,  NF_UNDEF, NF_2D, NF_UNDEF, NF_2D}
-  };
+  static const NEONFormatMap map = {{22, 21, 20, 19, 30},
+                                    {NF_UNDEF,
+                                     NF_UNDEF,
+                                     NF_8B,
+                                     NF_16B,
+                                     NF_4H,
+                                     NF_8H,
+                                     NF_4H,
+                                     NF_8H,
+                                     NF_2S,
+                                     NF_4S,
+                                     NF_2S,
+                                     NF_4S,
+                                     NF_2S,
+                                     NF_4S,
+                                     NF_2S,
+                                     NF_4S,
+                                     NF_UNDEF,
+                                     NF_2D,
+                                     NF_UNDEF,
+                                     NF_2D,
+                                     NF_UNDEF,
+                                     NF_2D,
+                                     NF_UNDEF,
+                                     NF_2D,
+                                     NF_UNDEF,
+                                     NF_2D,
+                                     NF_UNDEF,
+                                     NF_2D,
+                                     NF_UNDEF,
+                                     NF_2D,
+                                     NF_UNDEF,
+                                     NF_2D}};
   NEONFormatDecoder nfd(instr, &map);
   VectorFormat vf = nfd.GetVectorFormat();
 
   // 0001->8H, 001x->4S, 01xx->2D, all others undefined.
-  static const NEONFormatMap map_l = {
-    {22, 21, 20, 19},
-    {NF_UNDEF, NF_8H, NF_4S, NF_4S, NF_2D, NF_2D, NF_2D, NF_2D}
-  };
+  static const NEONFormatMap map_l =
+      {{22, 21, 20, 19},
+       {NF_UNDEF, NF_8H, NF_4S, NF_4S, NF_2D, NF_2D, NF_2D, NF_2D}};
   VectorFormat vf_l = nfd.GetVectorFormat(&map_l);
 
   int highestSetBit = HighestSetBitPosition(instr->ImmNEONImmh());
@@ -3723,24 +4765,60 @@
   int left_shift = immhimmb - (8 << highestSetBit);
 
   switch (instr->Mask(NEONShiftImmediateMask)) {
-    case NEON_SHL:    shl(vf, rd, rn, left_shift); break;
-    case NEON_SLI:    sli(vf, rd, rn, left_shift); break;
-    case NEON_SQSHLU: sqshlu(vf, rd, rn, left_shift); break;
-    case NEON_SRI:    sri(vf, rd, rn, right_shift); break;
-    case NEON_SSHR:   sshr(vf, rd, rn, right_shift); break;
-    case NEON_USHR:   ushr(vf, rd, rn, right_shift); break;
-    case NEON_SRSHR:  sshr(vf, rd, rn, right_shift).Round(vf); break;
-    case NEON_URSHR:  ushr(vf, rd, rn, right_shift).Round(vf); break;
-    case NEON_SSRA:   ssra(vf, rd, rn, right_shift); break;
-    case NEON_USRA:   usra(vf, rd, rn, right_shift); break;
-    case NEON_SRSRA:  srsra(vf, rd, rn, right_shift); break;
-    case NEON_URSRA:  ursra(vf, rd, rn, right_shift); break;
-    case NEON_SQSHL_imm: sqshl(vf, rd, rn, left_shift); break;
-    case NEON_UQSHL_imm: uqshl(vf, rd, rn, left_shift); break;
-    case NEON_SCVTF_imm: scvtf(vf, rd, rn, right_shift, fpcr_rounding); break;
-    case NEON_UCVTF_imm: ucvtf(vf, rd, rn, right_shift, fpcr_rounding); break;
-    case NEON_FCVTZS_imm: fcvts(vf, rd, rn, FPZero, right_shift); break;
-    case NEON_FCVTZU_imm: fcvtu(vf, rd, rn, FPZero, right_shift); break;
+    case NEON_SHL:
+      shl(vf, rd, rn, left_shift);
+      break;
+    case NEON_SLI:
+      sli(vf, rd, rn, left_shift);
+      break;
+    case NEON_SQSHLU:
+      sqshlu(vf, rd, rn, left_shift);
+      break;
+    case NEON_SRI:
+      sri(vf, rd, rn, right_shift);
+      break;
+    case NEON_SSHR:
+      sshr(vf, rd, rn, right_shift);
+      break;
+    case NEON_USHR:
+      ushr(vf, rd, rn, right_shift);
+      break;
+    case NEON_SRSHR:
+      sshr(vf, rd, rn, right_shift).Round(vf);
+      break;
+    case NEON_URSHR:
+      ushr(vf, rd, rn, right_shift).Round(vf);
+      break;
+    case NEON_SSRA:
+      ssra(vf, rd, rn, right_shift);
+      break;
+    case NEON_USRA:
+      usra(vf, rd, rn, right_shift);
+      break;
+    case NEON_SRSRA:
+      srsra(vf, rd, rn, right_shift);
+      break;
+    case NEON_URSRA:
+      ursra(vf, rd, rn, right_shift);
+      break;
+    case NEON_SQSHL_imm:
+      sqshl(vf, rd, rn, left_shift);
+      break;
+    case NEON_UQSHL_imm:
+      uqshl(vf, rd, rn, left_shift);
+      break;
+    case NEON_SCVTF_imm:
+      scvtf(vf, rd, rn, right_shift, fpcr_rounding);
+      break;
+    case NEON_UCVTF_imm:
+      ucvtf(vf, rd, rn, right_shift, fpcr_rounding);
+      break;
+    case NEON_FCVTZS_imm:
+      fcvts(vf, rd, rn, FPZero, right_shift);
+      break;
+    case NEON_FCVTZU_imm:
+      fcvtu(vf, rd, rn, FPZero, right_shift);
+      break;
     case NEON_SSHLL:
       vf = vf_l;
       if (instr->Mask(NEON_Q)) {
@@ -3831,14 +4909,30 @@
   SimVRegister& rm = vreg(instr->Rm());
 
   switch (instr->Mask(NEONTableMask)) {
-    case NEON_TBL_1v: tbl(vf, rd, rn, rm); break;
-    case NEON_TBL_2v: tbl(vf, rd, rn, rn2, rm); break;
-    case NEON_TBL_3v: tbl(vf, rd, rn, rn2, rn3, rm); break;
-    case NEON_TBL_4v: tbl(vf, rd, rn, rn2, rn3, rn4, rm); break;
-    case NEON_TBX_1v: tbx(vf, rd, rn, rm); break;
-    case NEON_TBX_2v: tbx(vf, rd, rn, rn2, rm); break;
-    case NEON_TBX_3v: tbx(vf, rd, rn, rn2, rn3, rm); break;
-    case NEON_TBX_4v: tbx(vf, rd, rn, rn2, rn3, rn4, rm); break;
+    case NEON_TBL_1v:
+      tbl(vf, rd, rn, rm);
+      break;
+    case NEON_TBL_2v:
+      tbl(vf, rd, rn, rn2, rm);
+      break;
+    case NEON_TBL_3v:
+      tbl(vf, rd, rn, rn2, rn3, rm);
+      break;
+    case NEON_TBL_4v:
+      tbl(vf, rd, rn, rn2, rn3, rn4, rm);
+      break;
+    case NEON_TBX_1v:
+      tbx(vf, rd, rn, rm);
+      break;
+    case NEON_TBX_2v:
+      tbx(vf, rd, rn, rn2, rm);
+      break;
+    case NEON_TBX_3v:
+      tbx(vf, rd, rn, rn2, rn3, rm);
+      break;
+    case NEON_TBX_4v:
+      tbx(vf, rd, rn, rn2, rn3, rn4, rm);
+      break;
     default:
       VIXL_UNIMPLEMENTED();
   }
@@ -3854,12 +4948,24 @@
   SimVRegister& rm = vreg(instr->Rm());
 
   switch (instr->Mask(NEONPermMask)) {
-    case NEON_TRN1: trn1(vf, rd, rn, rm); break;
-    case NEON_TRN2: trn2(vf, rd, rn, rm); break;
-    case NEON_UZP1: uzp1(vf, rd, rn, rm); break;
-    case NEON_UZP2: uzp2(vf, rd, rn, rm); break;
-    case NEON_ZIP1: zip1(vf, rd, rn, rm); break;
-    case NEON_ZIP2: zip2(vf, rd, rn, rm); break;
+    case NEON_TRN1:
+      trn1(vf, rd, rn, rm);
+      break;
+    case NEON_TRN2:
+      trn2(vf, rd, rn, rm);
+      break;
+    case NEON_UZP1:
+      uzp1(vf, rd, rn, rm);
+      break;
+    case NEON_UZP2:
+      uzp2(vf, rd, rn, rm);
+      break;
+    case NEON_ZIP1:
+      zip1(vf, rd, rn, rm);
+      break;
+    case NEON_ZIP2:
+      zip2(vf, rd, rn, rm);
+      break;
     default:
       VIXL_UNIMPLEMENTED();
   }
@@ -3870,7 +4976,8 @@
   VIXL_ASSERT((instr->Mask(ExceptionMask) == HLT) &&
               (instr->ImmException() == kUnreachableOpcode));
 
-  fprintf(stream_, "Hit UNREACHABLE marker at pc=%p.\n",
+  fprintf(stream_,
+          "Hit UNREACHABLE marker at pc=%p.\n",
           reinterpret_cast<const void*>(instr));
   abort();
 }
@@ -3932,9 +5039,7 @@
   uint32_t arg_count;
   uint32_t arg_pattern_list;
   VIXL_STATIC_ASSERT(sizeof(*instr) == 1);
-  memcpy(&arg_count,
-         instr + kPrintfArgCountOffset,
-         sizeof(arg_count));
+  memcpy(&arg_count, instr + kPrintfArgCountOffset, sizeof(arg_count));
   memcpy(&arg_pattern_list,
          instr + kPrintfArgPatternListOffset,
          sizeof(arg_pattern_list));
@@ -3951,17 +5056,17 @@
   // Allocate space for the format string. We take a copy, so we can modify it.
   // Leave enough space for one extra character per expected argument (plus the
   // '\0' termination).
-  const char * format_base = reg<const char *>(0);
+  const char* format_base = reg<const char*>(0);
   VIXL_ASSERT(format_base != NULL);
   size_t length = strlen(format_base) + 1;
-  char * const format = new char[length + arg_count];
+  char* const format = new char[length + arg_count];
 
   // A list of chunks, each with exactly one format placeholder.
-  const char * chunks[kPrintfMaxArgCount];
+  const char* chunks[kPrintfMaxArgCount];
 
   // Copy the format string and search for format placeholders.
   uint32_t placeholder_count = 0;
-  char * format_scratch = format;
+  char* format_scratch = format;
   for (size_t i = 0; i < length; i++) {
     if (format_base[i] != '%') {
       *format_scratch++ = format_base[i];
@@ -3994,8 +5099,8 @@
   // Because '\0' is inserted before each placeholder, the first string in
   // 'format' contains no format placeholders and should be printed literally.
   int result = printf("%s", format);
-  int pcs_r = 1;      // Start at x1. x0 holds the format string.
-  int pcs_f = 0;      // Start at d0.
+  int pcs_r = 1;  // Start at x1. x0 holds the format string.
+  int pcs_f = 0;  // Start at d0.
   if (result >= 0) {
     for (uint32_t i = 0; i < placeholder_count; i++) {
       int part_result = -1;
@@ -4003,10 +5108,17 @@
       uint32_t arg_pattern = arg_pattern_list >> (i * kPrintfArgPatternBits);
       arg_pattern &= (1 << kPrintfArgPatternBits) - 1;
       switch (arg_pattern) {
-        case kPrintfArgW: part_result = printf(chunks[i], wreg(pcs_r++)); break;
-        case kPrintfArgX: part_result = printf(chunks[i], xreg(pcs_r++)); break;
-        case kPrintfArgD: part_result = printf(chunks[i], dreg(pcs_f++)); break;
-        default: VIXL_UNREACHABLE();
+        case kPrintfArgW:
+          part_result = printf(chunks[i], wreg(pcs_r++));
+          break;
+        case kPrintfArgX:
+          part_result = printf(chunks[i], xreg(pcs_r++));
+          break;
+        case kPrintfArgD:
+          part_result = printf(chunks[i], dreg(pcs_f++));
+          break;
+        default:
+          VIXL_UNREACHABLE();
       }
 
       if (part_result < 0) {
diff --git a/src/vixl/a64/simulator-a64.h b/src/vixl/a64/simulator-a64.h
index 8eb1ea9..c484fe1 100644
--- a/src/vixl/a64/simulator-a64.h
+++ b/src/vixl/a64/simulator-a64.h
@@ -53,8 +53,10 @@
 // Callers should use FPRoundToFloat or FPRoundToDouble directly, rather than
 // calling a templated FPRound.
 template <class T, int ebits, int mbits>
-T FPRound(int64_t sign, int64_t exponent, uint64_t mantissa,
-                 FPRounding round_mode) {
+T FPRound(int64_t sign,
+          int64_t exponent,
+          uint64_t mantissa,
+          FPRounding round_mode) {
   VIXL_ASSERT((sign == 0) || (sign == 1));
 
   // Only FPTieEven and FPRoundOdd rounding modes are implemented.
@@ -191,14 +193,14 @@
       // We have to shift the mantissa to the right. Some precision is lost, so
       // we need to apply rounding.
       uint64_t onebit_mantissa = (mantissa >> (shift)) & 1;
-      uint64_t halfbit_mantissa = (mantissa >> (shift-1)) & 1;
+      uint64_t halfbit_mantissa = (mantissa >> (shift - 1)) & 1;
       uint64_t adjustment = (halfbit_mantissa & ~onebit_mantissa);
       uint64_t adjusted = mantissa - adjustment;
-      T halfbit_adjusted = (adjusted >> (shift-1)) & 1;
+      T halfbit_adjusted = (adjusted >> (shift - 1)) & 1;
 
-      T result = static_cast<T>((sign << sign_offset) |
-                                (exponent << exponent_offset) |
-                                ((mantissa >> shift) << mantissa_offset));
+      T result =
+          static_cast<T>((sign << sign_offset) | (exponent << exponent_offset) |
+                         ((mantissa >> shift) << mantissa_offset));
 
       // A very large mantissa can overflow during rounding. If this happens,
       // the exponent should be incremented and the mantissa set to 1.0
@@ -251,7 +253,7 @@
     VIXL_ASSERT((sizeof(value) == 1) || (sizeof(value) == 2) ||
                 (sizeof(value) == 4) || (sizeof(value) == 8) ||
                 (sizeof(value) == 16));
-    memcpy(&value, reinterpret_cast<const char *>(address), sizeof(value));
+    memcpy(&value, reinterpret_cast<const char*>(address), sizeof(value));
     return value;
   }
 
@@ -261,18 +263,18 @@
     VIXL_ASSERT((sizeof(value) == 1) || (sizeof(value) == 2) ||
                 (sizeof(value) == 4) || (sizeof(value) == 8) ||
                 (sizeof(value) == 16));
-    memcpy(reinterpret_cast<char *>(address), &value, sizeof(value));
+    memcpy(reinterpret_cast<char*>(address), &value, sizeof(value));
   }
 };
 
 // Represent a register (r0-r31, v0-v31).
-template<int kSizeInBytes>
+template <int kSizeInBytes>
 class SimRegisterBase {
  public:
   SimRegisterBase() : written_since_last_log_(false) {}
 
   // Write the specified value. The value is zero-extended if necessary.
-  template<typename T>
+  template <typename T>
   void Set(T new_value) {
     VIXL_STATIC_ASSERT(sizeof(new_value) <= kSizeInBytes);
     if (sizeof(new_value) < kSizeInBytes) {
@@ -287,17 +289,17 @@
   // unchanged. The lane parameter indicates where in the register the value
   // should be inserted, in the range [ 0, sizeof(value_) / sizeof(T) ), where
   // 0 represents the least significant bits.
-  template<typename T>
+  template <typename T>
   void Insert(int lane, T new_value) {
     VIXL_ASSERT(lane >= 0);
-    VIXL_ASSERT((sizeof(new_value) +
-                 (lane * sizeof(new_value))) <= kSizeInBytes);
+    VIXL_ASSERT((sizeof(new_value) + (lane * sizeof(new_value))) <=
+                kSizeInBytes);
     memcpy(&value_[lane * sizeof(new_value)], &new_value, sizeof(new_value));
     NotifyRegisterWrite();
   }
 
   // Read the value as the specified type. The value is truncated if necessary.
-  template<typename T>
+  template <typename T>
   T Get(int lane = 0) const {
     T result;
     VIXL_ASSERT(lane >= 0);
@@ -309,13 +311,9 @@
   // TODO: Make this return a map of updated bytes, so that we can highlight
   // updated lanes for load-and-insert. (That never happens for scalar code, but
   // NEON has some instructions that can update individual lanes.)
-  bool WrittenSinceLastLog() const {
-    return written_since_last_log_;
-  }
+  bool WrittenSinceLastLog() const { return written_since_last_log_; }
 
-  void NotifyRegisterLogged() {
-    written_since_last_log_ = false;
-  }
+  void NotifyRegisterLogged() { written_since_last_log_ = false; }
 
  protected:
   uint8_t value_[kSizeInBytes];
@@ -323,12 +321,10 @@
   // Helpers to aid with register tracing.
   bool written_since_last_log_;
 
-  void NotifyRegisterWrite() {
-    written_since_last_log_ = true;
-  }
+  void NotifyRegisterWrite() { written_since_last_log_ = true; }
 };
-typedef SimRegisterBase<kXRegSizeInBytes> SimRegister;      // r0-r31
-typedef SimRegisterBase<kQRegSizeInBytes> SimVRegister;     // v0-v31
+typedef SimRegisterBase<kXRegSizeInBytes> SimRegister;   // r0-r31
+typedef SimRegisterBase<kQRegSizeInBytes> SimVRegister;  // v0-v31
 
 // Representation of a vector register, with typed getters and setters for lanes
 // and additional information to represent lane state.
@@ -347,11 +343,21 @@
   int64_t Int(VectorFormat vform, int index) const {
     int64_t element;
     switch (LaneSizeInBitsFromFormat(vform)) {
-      case 8: element = register_.Get<int8_t>(index); break;
-      case 16: element = register_.Get<int16_t>(index); break;
-      case 32: element = register_.Get<int32_t>(index); break;
-      case 64: element = register_.Get<int64_t>(index); break;
-      default: VIXL_UNREACHABLE(); return 0;
+      case 8:
+        element = register_.Get<int8_t>(index);
+        break;
+      case 16:
+        element = register_.Get<int16_t>(index);
+        break;
+      case 32:
+        element = register_.Get<int32_t>(index);
+        break;
+      case 64:
+        element = register_.Get<int64_t>(index);
+        break;
+      default:
+        VIXL_UNREACHABLE();
+        return 0;
     }
     return element;
   }
@@ -359,11 +365,21 @@
   uint64_t Uint(VectorFormat vform, int index) const {
     uint64_t element;
     switch (LaneSizeInBitsFromFormat(vform)) {
-      case 8: element = register_.Get<uint8_t>(index); break;
-      case 16: element = register_.Get<uint16_t>(index); break;
-      case 32: element = register_.Get<uint32_t>(index); break;
-      case 64: element = register_.Get<uint64_t>(index); break;
-      default: VIXL_UNREACHABLE(); return 0;
+      case 8:
+        element = register_.Get<uint8_t>(index);
+        break;
+      case 16:
+        element = register_.Get<uint16_t>(index);
+        break;
+      case 32:
+        element = register_.Get<uint32_t>(index);
+        break;
+      case 64:
+        element = register_.Get<uint64_t>(index);
+        break;
+      default:
+        VIXL_UNREACHABLE();
+        return 0;
     }
     return element;
   }
@@ -378,41 +394,79 @@
 
   void SetInt(VectorFormat vform, int index, int64_t value) const {
     switch (LaneSizeInBitsFromFormat(vform)) {
-      case 8: register_.Insert(index, static_cast<int8_t>(value)); break;
-      case 16: register_.Insert(index, static_cast<int16_t>(value)); break;
-      case 32: register_.Insert(index, static_cast<int32_t>(value)); break;
-      case 64: register_.Insert(index, static_cast<int64_t>(value)); break;
-      default: VIXL_UNREACHABLE(); return;
+      case 8:
+        register_.Insert(index, static_cast<int8_t>(value));
+        break;
+      case 16:
+        register_.Insert(index, static_cast<int16_t>(value));
+        break;
+      case 32:
+        register_.Insert(index, static_cast<int32_t>(value));
+        break;
+      case 64:
+        register_.Insert(index, static_cast<int64_t>(value));
+        break;
+      default:
+        VIXL_UNREACHABLE();
+        return;
     }
   }
 
   void SetUint(VectorFormat vform, int index, uint64_t value) const {
     switch (LaneSizeInBitsFromFormat(vform)) {
-      case 8: register_.Insert(index, static_cast<uint8_t>(value)); break;
-      case 16: register_.Insert(index, static_cast<uint16_t>(value)); break;
-      case 32: register_.Insert(index, static_cast<uint32_t>(value)); break;
-      case 64: register_.Insert(index, static_cast<uint64_t>(value)); break;
-      default: VIXL_UNREACHABLE(); return;
+      case 8:
+        register_.Insert(index, static_cast<uint8_t>(value));
+        break;
+      case 16:
+        register_.Insert(index, static_cast<uint16_t>(value));
+        break;
+      case 32:
+        register_.Insert(index, static_cast<uint32_t>(value));
+        break;
+      case 64:
+        register_.Insert(index, static_cast<uint64_t>(value));
+        break;
+      default:
+        VIXL_UNREACHABLE();
+        return;
     }
   }
 
   void ReadUintFromMem(VectorFormat vform, int index, uint64_t addr) const {
     switch (LaneSizeInBitsFromFormat(vform)) {
-      case 8: register_.Insert(index, Memory::Read<uint8_t>(addr)); break;
-      case 16: register_.Insert(index, Memory::Read<uint16_t>(addr)); break;
-      case 32: register_.Insert(index, Memory::Read<uint32_t>(addr)); break;
-      case 64: register_.Insert(index, Memory::Read<uint64_t>(addr)); break;
-      default: VIXL_UNREACHABLE(); return;
+      case 8:
+        register_.Insert(index, Memory::Read<uint8_t>(addr));
+        break;
+      case 16:
+        register_.Insert(index, Memory::Read<uint16_t>(addr));
+        break;
+      case 32:
+        register_.Insert(index, Memory::Read<uint32_t>(addr));
+        break;
+      case 64:
+        register_.Insert(index, Memory::Read<uint64_t>(addr));
+        break;
+      default:
+        VIXL_UNREACHABLE();
+        return;
     }
   }
 
   void WriteUintToMem(VectorFormat vform, int index, uint64_t addr) const {
     uint64_t value = Uint(vform, index);
     switch (LaneSizeInBitsFromFormat(vform)) {
-      case 8: Memory::Write(addr, static_cast<uint8_t>(value)); break;
-      case 16: Memory::Write(addr, static_cast<uint16_t>(value)); break;
-      case 32: Memory::Write(addr, static_cast<uint32_t>(value)); break;
-      case 64: Memory::Write(addr, value); break;
+      case 8:
+        Memory::Write(addr, static_cast<uint8_t>(value));
+        break;
+      case 16:
+        Memory::Write(addr, static_cast<uint16_t>(value));
+        break;
+      case 32:
+        Memory::Write(addr, static_cast<uint32_t>(value));
+        break;
+      case 64:
+        Memory::Write(addr, value);
+        break;
     }
   }
 
@@ -458,9 +512,7 @@
   }
 
   // Setters for saturation state.
-  void ClearSat(int index) {
-    saturated_[index] = kNotSaturated;
-  }
+  void ClearSat(int index) { saturated_[index] = kNotSaturated; }
 
   void SetSignedSat(int index, bool positive) {
     SetSatFlag(index, positive ? kSignedSatPositive : kSignedSatNegative);
@@ -502,14 +554,10 @@
   }
 
   // Getter for rounding state.
-  bool GetRounding(int index) {
-    return round_[index];
-  }
+  bool GetRounding(int index) { return round_[index]; }
 
   // Setter for rounding state.
-  void SetRounding(int index, bool round) {
-    round_[index] = round;
-  }
+  void SetRounding(int index, bool round) { round_[index] = round; }
 
   // Round lanes of a vector based on rounding state.
   LogicVRegister& Round(VectorFormat vform) {
@@ -570,11 +618,9 @@
  public:
   // The default constructor represents a register which has no writable bits.
   // It is not possible to set its value to anything other than 0.
-  SimSystemRegister() : value_(0), write_ignore_mask_(0xffffffff) { }
+  SimSystemRegister() : value_(0), write_ignore_mask_(0xffffffff) {}
 
-  uint32_t RawValue() const {
-    return value_;
-  }
+  uint32_t RawValue() const { return value_; }
 
   void SetRawValue(uint32_t new_value) {
     value_ = (value_ & write_ignore_mask_) | (new_value & ~write_ignore_mask_);
@@ -593,10 +639,10 @@
   // Default system register values.
   static SimSystemRegister DefaultValueFor(SystemRegister id);
 
-#define DEFINE_GETTER(Name, HighBit, LowBit, Func)                            \
-  uint32_t Name() const { return Func(HighBit, LowBit); }              \
+#define DEFINE_GETTER(Name, HighBit, LowBit, Func)        \
+  uint32_t Name() const { return Func(HighBit, LowBit); } \
   void Set##Name(uint32_t bits) { SetBits(HighBit, LowBit, bits); }
-#define DEFINE_WRITE_IGNORE_MASK(Name, Mask)                                  \
+#define DEFINE_WRITE_IGNORE_MASK(Name, Mask) \
   static const uint32_t Name##WriteIgnoreMask = ~static_cast<uint32_t>(Mask);
 
   SYSTEM_REGISTER_FIELDS_LIST(DEFINE_GETTER, DEFINE_WRITE_IGNORE_MASK)
@@ -609,7 +655,7 @@
   // bits are "read-as-zero, write-ignored". The write_ignore_mask argument
   // describes the bits which are not modifiable.
   SimSystemRegister(uint32_t value, uint32_t write_ignore_mask)
-      : value_(value), write_ignore_mask_(write_ignore_mask) { }
+      : value_(value), write_ignore_mask_(write_ignore_mask) {}
 
   uint32_t value_;
   uint32_t write_ignore_mask_;
@@ -694,6 +740,9 @@
   virtual void Run();
   void RunFrom(const Instruction* first);
 
+  // Execution ends when the PC hits this address.
+  static const Instruction* kEndOfSimAddress;
+
   // Simulation helpers.
   const Instruction* pc() const { return pc_; }
   void set_pc(const Instruction* new_pc) {
@@ -705,32 +754,32 @@
     if (!pc_modified_) {
       pc_ = pc_->NextInstruction();
     }
-
-    pc_modified_ = false;
   }
 
   void ExecuteInstruction() {
     // The program counter should always be aligned.
     VIXL_ASSERT(IsWordAligned(pc_));
+    pc_modified_ = false;
     decoder_->Decode(pc_);
     increment_pc();
+    LogAllWrittenRegisters();
   }
 
-  // Declare all Visitor functions.
-  #define DECLARE(A) virtual void Visit##A(const Instruction* instr);
+// Declare all Visitor functions.
+#define DECLARE(A) virtual void Visit##A(const Instruction* instr);
   VISITOR_LIST_THAT_RETURN(DECLARE)
-  #undef DECLARE
+#undef DECLARE
 
-  #define DECLARE(A) \
-      VIXL_DEBUG_NO_RETURN virtual void Visit##A(const Instruction* instr);
+#define DECLARE(A) \
+  VIXL_DEBUG_NO_RETURN virtual void Visit##A(const Instruction* instr);
   VISITOR_LIST_THAT_DONT_RETURN(DECLARE)
-  #undef DECLARE
+#undef DECLARE
 
 
   // Integer register accessors.
 
   // Basic accessor: Read the register as the specified type.
-  template<typename T>
+  template <typename T>
   T reg(unsigned code, Reg31Mode r31mode = Reg31IsZeroRegister) const {
     VIXL_ASSERT(code < kNumberOfRegisters);
     if ((code == 31) && (r31mode == Reg31IsZeroRegister)) {
@@ -742,25 +791,28 @@
   }
 
   // Common specialized accessors for the reg() template.
-  int32_t wreg(unsigned code,
-               Reg31Mode r31mode = Reg31IsZeroRegister) const {
+  int32_t wreg(unsigned code, Reg31Mode r31mode = Reg31IsZeroRegister) const {
     return reg<int32_t>(code, r31mode);
   }
 
-  int64_t xreg(unsigned code,
-               Reg31Mode r31mode = Reg31IsZeroRegister) const {
+  int64_t xreg(unsigned code, Reg31Mode r31mode = Reg31IsZeroRegister) const {
     return reg<int64_t>(code, r31mode);
   }
 
   // As above, with parameterized size and return type. The value is
   // either zero-extended or truncated to fit, as required.
-  template<typename T>
-  T reg(unsigned size, unsigned code,
+  template <typename T>
+  T reg(unsigned size,
+        unsigned code,
         Reg31Mode r31mode = Reg31IsZeroRegister) const {
     uint64_t raw;
     switch (size) {
-      case kWRegSize: raw = reg<uint32_t>(code, r31mode); break;
-      case kXRegSize: raw = reg<uint64_t>(code, r31mode); break;
+      case kWRegSize:
+        raw = reg<uint32_t>(code, r31mode);
+        break;
+      case kXRegSize:
+        raw = reg<uint64_t>(code, r31mode);
+        break;
       default:
         VIXL_UNREACHABLE();
         return 0;
@@ -774,20 +826,19 @@
   }
 
   // Use int64_t by default if T is not specified.
-  int64_t reg(unsigned size, unsigned code,
+  int64_t reg(unsigned size,
+              unsigned code,
               Reg31Mode r31mode = Reg31IsZeroRegister) const {
     return reg<int64_t>(size, code, r31mode);
   }
 
-  enum RegLogMode {
-    LogRegWrites,
-    NoRegLog
-  };
+  enum RegLogMode { LogRegWrites, NoRegLog };
 
   // Write 'value' into an integer register. The value is zero-extended. This
   // behaviour matches AArch64 register writes.
-  template<typename T>
-  void set_reg(unsigned code, T value,
+  template <typename T>
+  void set_reg(unsigned code,
+               T value,
                RegLogMode log_mode = LogRegWrites,
                Reg31Mode r31mode = Reg31IsZeroRegister) {
     VIXL_STATIC_ASSERT((sizeof(T) == kWRegSizeInBytes) ||
@@ -804,13 +855,15 @@
   }
 
   // Common specialized accessors for the set_reg() template.
-  void set_wreg(unsigned code, int32_t value,
+  void set_wreg(unsigned code,
+                int32_t value,
                 RegLogMode log_mode = LogRegWrites,
                 Reg31Mode r31mode = Reg31IsZeroRegister) {
     set_reg(code, value, log_mode, r31mode);
   }
 
-  void set_xreg(unsigned code, int64_t value,
+  void set_xreg(unsigned code,
+                int64_t value,
                 RegLogMode log_mode = LogRegWrites,
                 Reg31Mode r31mode = Reg31IsZeroRegister) {
     set_reg(code, value, log_mode, r31mode);
@@ -818,8 +871,10 @@
 
   // As above, with parameterized size and type. The value is either
   // zero-extended or truncated to fit, as required.
-  template<typename T>
-  void set_reg(unsigned size, unsigned code, T value,
+  template <typename T>
+  void set_reg(unsigned size,
+               unsigned code,
+               T value,
                RegLogMode log_mode = LogRegWrites,
                Reg31Mode r31mode = Reg31IsZeroRegister) {
     // Zero-extend the input.
@@ -844,12 +899,12 @@
   // Common specialized accessors for the set_reg() template.
 
   // Commonly-used special cases.
-  template<typename T>
+  template <typename T>
   void set_lr(T value) {
     set_reg(kLinkRegCode, value);
   }
 
-  template<typename T>
+  template <typename T>
   void set_sp(T value) {
     set_reg(31, value, LogRegWrites, Reg31IsStackPointer);
   }
@@ -859,60 +914,51 @@
   // registers.
 
   // A structure for representing a 128-bit Q register.
-  struct qreg_t { uint8_t val[kQRegSizeInBytes]; };
+  struct qreg_t {
+    uint8_t val[kQRegSizeInBytes];
+  };
 
   // Basic accessor: read the register as the specified type.
-  template<typename T>
+  template <typename T>
   T vreg(unsigned code) const {
-    VIXL_STATIC_ASSERT((sizeof(T) == kBRegSizeInBytes) ||
-                       (sizeof(T) == kHRegSizeInBytes) ||
-                       (sizeof(T) == kSRegSizeInBytes) ||
-                       (sizeof(T) == kDRegSizeInBytes) ||
-                       (sizeof(T) == kQRegSizeInBytes));
+    VIXL_STATIC_ASSERT(
+        (sizeof(T) == kBRegSizeInBytes) || (sizeof(T) == kHRegSizeInBytes) ||
+        (sizeof(T) == kSRegSizeInBytes) || (sizeof(T) == kDRegSizeInBytes) ||
+        (sizeof(T) == kQRegSizeInBytes));
     VIXL_ASSERT(code < kNumberOfVRegisters);
 
     return vregisters_[code].Get<T>();
   }
 
   // Common specialized accessors for the vreg() template.
-  int8_t breg(unsigned code) const {
-    return vreg<int8_t>(code);
-  }
+  int8_t breg(unsigned code) const { return vreg<int8_t>(code); }
 
-  int16_t hreg(unsigned code) const {
-    return vreg<int16_t>(code);
-  }
+  int16_t hreg(unsigned code) const { return vreg<int16_t>(code); }
 
-  float sreg(unsigned code) const {
-    return vreg<float>(code);
-  }
+  float sreg(unsigned code) const { return vreg<float>(code); }
 
-  uint32_t sreg_bits(unsigned code) const {
-    return vreg<uint32_t>(code);
-  }
+  uint32_t sreg_bits(unsigned code) const { return vreg<uint32_t>(code); }
 
-  double dreg(unsigned code) const {
-    return vreg<double>(code);
-  }
+  double dreg(unsigned code) const { return vreg<double>(code); }
 
-  uint64_t dreg_bits(unsigned code) const {
-    return vreg<uint64_t>(code);
-  }
+  uint64_t dreg_bits(unsigned code) const { return vreg<uint64_t>(code); }
 
-  qreg_t qreg(unsigned code)  const {
-    return vreg<qreg_t>(code);
-  }
+  qreg_t qreg(unsigned code) const { return vreg<qreg_t>(code); }
 
   // As above, with parameterized size and return type. The value is
   // either zero-extended or truncated to fit, as required.
-  template<typename T>
+  template <typename T>
   T vreg(unsigned size, unsigned code) const {
     uint64_t raw = 0;
     T result;
 
     switch (size) {
-      case kSRegSize: raw = vreg<uint32_t>(code); break;
-      case kDRegSize: raw = vreg<uint64_t>(code); break;
+      case kSRegSize:
+        raw = vreg<uint32_t>(code);
+        break;
+      case kDRegSize:
+        raw = vreg<uint64_t>(code);
+        break;
       default:
         VIXL_UNREACHABLE();
         break;
@@ -924,14 +970,11 @@
     return result;
   }
 
-  inline SimVRegister& vreg(unsigned code) {
-    return vregisters_[code];
-  }
+  inline SimVRegister& vreg(unsigned code) { return vregisters_[code]; }
 
   // Basic accessor: Write the specified value.
-  template<typename T>
-  void set_vreg(unsigned code, T value,
-                RegLogMode log_mode = LogRegWrites) {
+  template <typename T>
+  void set_vreg(unsigned code, T value, RegLogMode log_mode = LogRegWrites) {
     VIXL_STATIC_ASSERT((sizeof(value) == kBRegSizeInBytes) ||
                        (sizeof(value) == kHRegSizeInBytes) ||
                        (sizeof(value) == kSRegSizeInBytes) ||
@@ -946,37 +989,44 @@
   }
 
   // Common specialized accessors for the set_vreg() template.
-  void set_breg(unsigned code, int8_t value,
+  void set_breg(unsigned code,
+                int8_t value,
                 RegLogMode log_mode = LogRegWrites) {
     set_vreg(code, value, log_mode);
   }
 
-  void set_hreg(unsigned code, int16_t value,
+  void set_hreg(unsigned code,
+                int16_t value,
                 RegLogMode log_mode = LogRegWrites) {
     set_vreg(code, value, log_mode);
   }
 
-  void set_sreg(unsigned code, float value,
+  void set_sreg(unsigned code,
+                float value,
                 RegLogMode log_mode = LogRegWrites) {
     set_vreg(code, value, log_mode);
   }
 
-  void set_sreg_bits(unsigned code, uint32_t value,
+  void set_sreg_bits(unsigned code,
+                     uint32_t value,
+                     RegLogMode log_mode = LogRegWrites) {
+    set_vreg(code, value, log_mode);
+  }
+
+  void set_dreg(unsigned code,
+                double value,
                 RegLogMode log_mode = LogRegWrites) {
     set_vreg(code, value, log_mode);
   }
 
-  void set_dreg(unsigned code, double value,
-                RegLogMode log_mode = LogRegWrites) {
+  void set_dreg_bits(unsigned code,
+                     uint64_t value,
+                     RegLogMode log_mode = LogRegWrites) {
     set_vreg(code, value, log_mode);
   }
 
-  void set_dreg_bits(unsigned code, uint64_t value,
-                RegLogMode log_mode = LogRegWrites) {
-    set_vreg(code, value, log_mode);
-  }
-
-  void set_qreg(unsigned code, qreg_t value,
+  void set_qreg(unsigned code,
+                qreg_t value,
                 RegLogMode log_mode = LogRegWrites) {
     set_vreg(code, value, log_mode);
   }
@@ -1080,9 +1130,13 @@
 
   PrintRegisterFormat GetPrintRegisterFormatForSizeFP(unsigned size) {
     switch (size) {
-      default: VIXL_UNREACHABLE(); return kPrintDReg;
-      case kDRegSizeInBytes: return kPrintDReg;
-      case kSRegSizeInBytes: return kPrintSReg;
+      default:
+        VIXL_UNREACHABLE();
+        return kPrintDReg;
+      case kDRegSizeInBytes:
+        return kPrintDReg;
+      case kSRegSizeInBytes:
+        return kPrintSReg;
     }
   }
 
@@ -1094,7 +1148,7 @@
     return format;
   }
 
-  template<typename T>
+  template <typename T>
   PrintRegisterFormat GetPrintRegisterFormat(T value) {
     return GetPrintRegisterFormatForSize(sizeof(value));
   }
@@ -1110,6 +1164,7 @@
   }
 
   PrintRegisterFormat GetPrintRegisterFormat(VectorFormat vform);
+  PrintRegisterFormat GetPrintRegisterFormatFP(VectorFormat vform);
 
   // Print all registers of the specified types.
   void PrintRegisters();
@@ -1149,44 +1204,60 @@
   }
 
   // Print memory accesses.
-  void PrintRead(uintptr_t address, unsigned reg_code,
+  void PrintRead(uintptr_t address,
+                 unsigned reg_code,
                  PrintRegisterFormat format);
-  void PrintWrite(uintptr_t address, unsigned reg_code,
-                 PrintRegisterFormat format);
-  void PrintVRead(uintptr_t address, unsigned reg_code,
-                  PrintRegisterFormat format, unsigned lane);
-  void PrintVWrite(uintptr_t address, unsigned reg_code,
-                   PrintRegisterFormat format, unsigned lane);
+  void PrintWrite(uintptr_t address,
+                  unsigned reg_code,
+                  PrintRegisterFormat format);
+  void PrintVRead(uintptr_t address,
+                  unsigned reg_code,
+                  PrintRegisterFormat format,
+                  unsigned lane);
+  void PrintVWrite(uintptr_t address,
+                   unsigned reg_code,
+                   PrintRegisterFormat format,
+                   unsigned lane);
 
   // Like Print* (above), but respect trace_parameters().
-  void LogRead(uintptr_t address, unsigned reg_code,
+  void LogRead(uintptr_t address,
+               unsigned reg_code,
                PrintRegisterFormat format) {
     if (trace_parameters() & LOG_REGS) PrintRead(address, reg_code, format);
   }
-  void LogWrite(uintptr_t address, unsigned reg_code,
+  void LogWrite(uintptr_t address,
+                unsigned reg_code,
                 PrintRegisterFormat format) {
     if (trace_parameters() & LOG_WRITE) PrintWrite(address, reg_code, format);
   }
-  void LogVRead(uintptr_t address, unsigned reg_code,
-                PrintRegisterFormat format, unsigned lane = 0) {
+  void LogVRead(uintptr_t address,
+                unsigned reg_code,
+                PrintRegisterFormat format,
+                unsigned lane = 0) {
     if (trace_parameters() & LOG_VREGS) {
       PrintVRead(address, reg_code, format, lane);
     }
   }
-  void LogVWrite(uintptr_t address, unsigned reg_code,
-                 PrintRegisterFormat format, unsigned lane = 0) {
+  void LogVWrite(uintptr_t address,
+                 unsigned reg_code,
+                 PrintRegisterFormat format,
+                 unsigned lane = 0) {
     if (trace_parameters() & LOG_WRITE) {
       PrintVWrite(address, reg_code, format, lane);
     }
   }
 
   // Helper functions for register tracing.
-  void PrintRegisterRawHelper(unsigned code, Reg31Mode r31mode,
+  void PrintRegisterRawHelper(unsigned code,
+                              Reg31Mode r31mode,
                               int size_in_bytes = kXRegSizeInBytes);
-  void PrintVRegisterRawHelper(unsigned code, int bytes = kQRegSizeInBytes,
+  void PrintVRegisterRawHelper(unsigned code,
+                               int bytes = kQRegSizeInBytes,
                                int lsb = 0);
-  void PrintVRegisterFPHelper(unsigned code, unsigned lane_size_in_bytes,
-                              int lane_count = 1, int rightmost_lane = 0);
+  void PrintVRegisterFPHelper(unsigned code,
+                              unsigned lane_size_in_bytes,
+                              int lane_count = 1,
+                              int rightmost_lane = 0);
 
   VIXL_NO_RETURN void DoUnreachable(const Instruction* instr);
   void DoTrace(const Instruction* instr);
@@ -1210,9 +1281,7 @@
 
   // Clear the simulated local monitor to force the next store-exclusive
   // instruction to fail.
-  void ClearLocalMonitor() {
-    local_monitor_.Clear();
-  }
+  void ClearLocalMonitor() { local_monitor_.Clear(); }
 
   void SilenceExclusiveAccessWarning() {
     print_exclusive_access_warning_ = false;
@@ -1276,9 +1345,7 @@
     return ConditionPassed(static_cast<Condition>(cond));
   }
 
-  bool ConditionFailed(Condition cond) {
-    return !ConditionPassed(cond);
-  }
+  bool ConditionFailed(Condition cond) { return !ConditionPassed(cond); }
 
   void AddSubHelper(const Instruction* instr, int64_t op2);
   uint64_t AddWithCarry(unsigned reg_size,
@@ -1300,9 +1367,7 @@
   void NEONLoadStoreSingleStructHelper(const Instruction* instr,
                                        AddrMode addr_mode);
 
-  uint64_t AddressUntag(uint64_t address) {
-    return address & ~kAddressTagMask;
-  }
+  uint64_t AddressUntag(uint64_t address) { return address & ~kAddressTagMask; }
 
   template <typename T>
   T* AddressUntag(T* address) {
@@ -1324,16 +1389,9 @@
                       unsigned left_shift = 0);
   uint16_t PolynomialMult(uint8_t op1, uint8_t op2);
 
-  void ld1(VectorFormat vform,
-           LogicVRegister dst,
-           uint64_t addr);
-  void ld1(VectorFormat vform,
-           LogicVRegister dst,
-           int index,
-           uint64_t addr);
-  void ld1r(VectorFormat vform,
-            LogicVRegister dst,
-            uint64_t addr);
+  void ld1(VectorFormat vform, LogicVRegister dst, uint64_t addr);
+  void ld1(VectorFormat vform, LogicVRegister dst, int index, uint64_t addr);
+  void ld1r(VectorFormat vform, LogicVRegister dst, uint64_t addr);
   void ld2(VectorFormat vform,
            LogicVRegister dst1,
            LogicVRegister dst2,
@@ -1344,9 +1402,9 @@
            int index,
            uint64_t addr);
   void ld2r(VectorFormat vform,
-           LogicVRegister dst1,
-           LogicVRegister dst2,
-           uint64_t addr);
+            LogicVRegister dst1,
+            LogicVRegister dst2,
+            uint64_t addr);
   void ld3(VectorFormat vform,
            LogicVRegister dst1,
            LogicVRegister dst2,
@@ -1359,10 +1417,10 @@
            int index,
            uint64_t addr);
   void ld3r(VectorFormat vform,
-           LogicVRegister dst1,
-           LogicVRegister dst2,
-           LogicVRegister dst3,
-           uint64_t addr);
+            LogicVRegister dst1,
+            LogicVRegister dst2,
+            LogicVRegister dst3,
+            uint64_t addr);
   void ld4(VectorFormat vform,
            LogicVRegister dst1,
            LogicVRegister dst2,
@@ -1377,18 +1435,13 @@
            int index,
            uint64_t addr);
   void ld4r(VectorFormat vform,
-           LogicVRegister dst1,
-           LogicVRegister dst2,
-           LogicVRegister dst3,
-           LogicVRegister dst4,
-           uint64_t addr);
-  void st1(VectorFormat vform,
-           LogicVRegister src,
-           uint64_t addr);
-  void st1(VectorFormat vform,
-           LogicVRegister src,
-           int index,
-           uint64_t addr);
+            LogicVRegister dst1,
+            LogicVRegister dst2,
+            LogicVRegister dst3,
+            LogicVRegister dst4,
+            uint64_t addr);
+  void st1(VectorFormat vform, LogicVRegister src, uint64_t addr);
+  void st1(VectorFormat vform, LogicVRegister src, int index, uint64_t addr);
   void st2(VectorFormat vform,
            LogicVRegister src,
            LogicVRegister src2,
@@ -1707,12 +1760,8 @@
   LogicVRegister dup_immediate(VectorFormat vform,
                                LogicVRegister dst,
                                uint64_t imm);
-  LogicVRegister movi(VectorFormat vform,
-                      LogicVRegister dst,
-                      uint64_t imm);
-  LogicVRegister mvni(VectorFormat vform,
-                      LogicVRegister dst,
-                      uint64_t imm);
+  LogicVRegister movi(VectorFormat vform, LogicVRegister dst, uint64_t imm);
+  LogicVRegister mvni(VectorFormat vform, LogicVRegister dst, uint64_t imm);
   LogicVRegister orr(VectorFormat vform,
                      LogicVRegister dst,
                      const LogicVRegister& src,
@@ -1731,13 +1780,13 @@
                          const LogicVRegister& src2,
                          bool max);
   LogicVRegister smax(VectorFormat vform,
-                     LogicVRegister dst,
-                     const LogicVRegister& src1,
-                     const LogicVRegister& src2);
+                      LogicVRegister dst,
+                      const LogicVRegister& src1,
+                      const LogicVRegister& src2);
   LogicVRegister smin(VectorFormat vform,
-                     LogicVRegister dst,
-                     const LogicVRegister& src1,
-                     const LogicVRegister& src2);
+                      LogicVRegister dst,
+                      const LogicVRegister& src1,
+                      const LogicVRegister& src2);
   LogicVRegister sminmaxp(VectorFormat vform,
                           LogicVRegister dst,
                           int dst_index,
@@ -1862,9 +1911,9 @@
                         const LogicVRegister& src1,
                         const LogicVRegister& src2);
   LogicVRegister usubl(VectorFormat vform,
-                         LogicVRegister dst,
-                         const LogicVRegister& src1,
-                         const LogicVRegister& src2);
+                       LogicVRegister dst,
+                       const LogicVRegister& src1,
+                       const LogicVRegister& src2);
   LogicVRegister usubl2(VectorFormat vform,
                         LogicVRegister dst,
                         const LogicVRegister& src1,
@@ -1899,13 +1948,13 @@
                          const LogicVRegister& src2,
                          bool max);
   LogicVRegister umax(VectorFormat vform,
-                     LogicVRegister dst,
-                     const LogicVRegister& src1,
-                     const LogicVRegister& src2);
+                      LogicVRegister dst,
+                      const LogicVRegister& src1,
+                      const LogicVRegister& src2);
   LogicVRegister umin(VectorFormat vform,
-                     LogicVRegister dst,
-                     const LogicVRegister& src1,
-                     const LogicVRegister& src2);
+                      LogicVRegister dst,
+                      const LogicVRegister& src1,
+                      const LogicVRegister& src2);
   LogicVRegister uminmaxp(VectorFormat vform,
                           LogicVRegister dst,
                           int dst_index,
@@ -2022,11 +2071,11 @@
                        const LogicVRegister& src,
                        int shift);
   LogicVRegister suqadd(VectorFormat vform,
-                       LogicVRegister dst,
-                       const LogicVRegister& src);
+                        LogicVRegister dst,
+                        const LogicVRegister& src);
   LogicVRegister usqadd(VectorFormat vform,
-                       LogicVRegister dst,
-                       const LogicVRegister& src);
+                        LogicVRegister dst,
+                        const LogicVRegister& src);
   LogicVRegister sqshl(VectorFormat vform,
                        LogicVRegister dst,
                        const LogicVRegister& src,
@@ -2080,9 +2129,9 @@
                       const LogicVRegister& src,
                       int shift);
   LogicVRegister shrn2(VectorFormat vform,
-                      LogicVRegister dst,
-                      const LogicVRegister& src,
-                      int shift);
+                       LogicVRegister dst,
+                       const LogicVRegister& src,
+                       int shift);
   LogicVRegister rshrn(VectorFormat vform,
                        LogicVRegister dst,
                        const LogicVRegister& src,
@@ -2148,93 +2197,93 @@
                          LogicVRegister dst,
                          const LogicVRegister& src1,
                          const LogicVRegister& src2);
-  #define NEON_3VREG_LOGIC_LIST(V) \
-    V(addhn)                       \
-    V(addhn2)                      \
-    V(raddhn)                      \
-    V(raddhn2)                     \
-    V(subhn)                       \
-    V(subhn2)                      \
-    V(rsubhn)                      \
-    V(rsubhn2)                     \
-    V(pmull)                       \
-    V(pmull2)                      \
-    V(sabal)                       \
-    V(sabal2)                      \
-    V(uabal)                       \
-    V(uabal2)                      \
-    V(sabdl)                       \
-    V(sabdl2)                      \
-    V(uabdl)                       \
-    V(uabdl2)                      \
-    V(smull)                       \
-    V(smull2)                      \
-    V(umull)                       \
-    V(umull2)                      \
-    V(smlal)                       \
-    V(smlal2)                      \
-    V(umlal)                       \
-    V(umlal2)                      \
-    V(smlsl)                       \
-    V(smlsl2)                      \
-    V(umlsl)                       \
-    V(umlsl2)                      \
-    V(sqdmlal)                     \
-    V(sqdmlal2)                    \
-    V(sqdmlsl)                     \
-    V(sqdmlsl2)                    \
-    V(sqdmull)                     \
-    V(sqdmull2)
+#define NEON_3VREG_LOGIC_LIST(V) \
+  V(addhn)                       \
+  V(addhn2)                      \
+  V(raddhn)                      \
+  V(raddhn2)                     \
+  V(subhn)                       \
+  V(subhn2)                      \
+  V(rsubhn)                      \
+  V(rsubhn2)                     \
+  V(pmull)                       \
+  V(pmull2)                      \
+  V(sabal)                       \
+  V(sabal2)                      \
+  V(uabal)                       \
+  V(uabal2)                      \
+  V(sabdl)                       \
+  V(sabdl2)                      \
+  V(uabdl)                       \
+  V(uabdl2)                      \
+  V(smull)                       \
+  V(smull2)                      \
+  V(umull)                       \
+  V(umull2)                      \
+  V(smlal)                       \
+  V(smlal2)                      \
+  V(umlal)                       \
+  V(umlal2)                      \
+  V(smlsl)                       \
+  V(smlsl2)                      \
+  V(umlsl)                       \
+  V(umlsl2)                      \
+  V(sqdmlal)                     \
+  V(sqdmlal2)                    \
+  V(sqdmlsl)                     \
+  V(sqdmlsl2)                    \
+  V(sqdmull)                     \
+  V(sqdmull2)
 
-  #define DEFINE_LOGIC_FUNC(FXN)                   \
-    LogicVRegister FXN(VectorFormat vform,         \
-                       LogicVRegister dst,         \
-                       const LogicVRegister& src1, \
-                       const LogicVRegister& src2);
+#define DEFINE_LOGIC_FUNC(FXN)                   \
+  LogicVRegister FXN(VectorFormat vform,         \
+                     LogicVRegister dst,         \
+                     const LogicVRegister& src1, \
+                     const LogicVRegister& src2);
   NEON_3VREG_LOGIC_LIST(DEFINE_LOGIC_FUNC)
-  #undef DEFINE_LOGIC_FUNC
+#undef DEFINE_LOGIC_FUNC
 
-  #define NEON_FP3SAME_LIST(V)  \
-    V(fadd,   FPAdd,   false)   \
-    V(fsub,   FPSub,   true)    \
-    V(fmul,   FPMul,   true)    \
-    V(fmulx,  FPMulx,  true)    \
-    V(fdiv,   FPDiv,   true)    \
-    V(fmax,   FPMax,   false)   \
-    V(fmin,   FPMin,   false)   \
-    V(fmaxnm, FPMaxNM, false)   \
-    V(fminnm, FPMinNM, false)
+#define NEON_FP3SAME_LIST(V) \
+  V(fadd, FPAdd, false)      \
+  V(fsub, FPSub, true)       \
+  V(fmul, FPMul, true)       \
+  V(fmulx, FPMulx, true)     \
+  V(fdiv, FPDiv, true)       \
+  V(fmax, FPMax, false)      \
+  V(fmin, FPMin, false)      \
+  V(fmaxnm, FPMaxNM, false)  \
+  V(fminnm, FPMinNM, false)
 
-  #define DECLARE_NEON_FP_VECTOR_OP(FN, OP, PROCNAN) \
-    template <typename T>                            \
-    LogicVRegister FN(VectorFormat vform,            \
-                      LogicVRegister dst,            \
-                      const LogicVRegister& src1,    \
-                      const LogicVRegister& src2);   \
-    LogicVRegister FN(VectorFormat vform,            \
-                      LogicVRegister dst,            \
-                      const LogicVRegister& src1,    \
-                      const LogicVRegister& src2);
+#define DECLARE_NEON_FP_VECTOR_OP(FN, OP, PROCNAN) \
+  template <typename T>                            \
+  LogicVRegister FN(VectorFormat vform,            \
+                    LogicVRegister dst,            \
+                    const LogicVRegister& src1,    \
+                    const LogicVRegister& src2);   \
+  LogicVRegister FN(VectorFormat vform,            \
+                    LogicVRegister dst,            \
+                    const LogicVRegister& src1,    \
+                    const LogicVRegister& src2);
   NEON_FP3SAME_LIST(DECLARE_NEON_FP_VECTOR_OP)
-  #undef DECLARE_NEON_FP_VECTOR_OP
+#undef DECLARE_NEON_FP_VECTOR_OP
 
-  #define NEON_FPPAIRWISE_LIST(V)         \
-    V(faddp,   fadd,   FPAdd)             \
-    V(fmaxp,   fmax,   FPMax)             \
-    V(fmaxnmp, fmaxnm, FPMaxNM)           \
-    V(fminp,   fmin,   FPMin)             \
-    V(fminnmp, fminnm, FPMinNM)
+#define NEON_FPPAIRWISE_LIST(V) \
+  V(faddp, fadd, FPAdd)         \
+  V(fmaxp, fmax, FPMax)         \
+  V(fmaxnmp, fmaxnm, FPMaxNM)   \
+  V(fminp, fmin, FPMin)         \
+  V(fminnmp, fminnm, FPMinNM)
 
-  #define DECLARE_NEON_FP_PAIR_OP(FNP, FN, OP)       \
-    LogicVRegister FNP(VectorFormat vform,           \
-                       LogicVRegister dst,           \
-                       const LogicVRegister& src1,   \
-                       const LogicVRegister& src2);  \
-    LogicVRegister FNP(VectorFormat vform,           \
-                       LogicVRegister dst,           \
-                       const LogicVRegister& src);
+#define DECLARE_NEON_FP_PAIR_OP(FNP, FN, OP)      \
+  LogicVRegister FNP(VectorFormat vform,          \
+                     LogicVRegister dst,          \
+                     const LogicVRegister& src1,  \
+                     const LogicVRegister& src2); \
+  LogicVRegister FNP(VectorFormat vform,          \
+                     LogicVRegister dst,          \
+                     const LogicVRegister& src);
   NEON_FPPAIRWISE_LIST(DECLARE_NEON_FP_PAIR_OP)
-  #undef DECLARE_NEON_FP_PAIR_OP
+#undef DECLARE_NEON_FP_PAIR_OP
 
   template <typename T>
   LogicVRegister frecps(VectorFormat vform,
@@ -2393,7 +2442,7 @@
                          LogicVRegister dst,
                          const LogicVRegister& src);
 
-  static const uint32_t CRC32_POLY  = 0x04C11DB7;
+  static const uint32_t CRC32_POLY = 0x04C11DB7;
   static const uint32_t CRC32C_POLY = 0x1EDC6F41;
   uint32_t Poly32Mod2(unsigned n, uint64_t data, uint32_t poly);
   template <typename T>
@@ -2470,7 +2519,7 @@
 
   // This doesn't do anything at the moment. We'll need it if we want support
   // for cumulative exception bits or floating-point exceptions.
-  void FPProcessException() { }
+  void FPProcessException() {}
 
   bool FPProcessNaNs(const Instruction* instr);
 
@@ -2523,9 +2572,7 @@
     return (result >> (reg_size - 1)) & 1;
   }
 
-  static int CalcZFlag(uint64_t result) {
-    return (result == 0) ? 1 : 0;
-  }
+  static int CalcZFlag(uint64_t result) { return (result == 0) ? 1 : 0; }
 
   static const uint32_t kConditionFlagsMask = 0xf0000000;
 
@@ -2548,8 +2595,6 @@
   static const char* dreg_names[];
   static const char* vreg_names[];
 
-  static const Instruction* kEndOfSimAddress;
-
  private:
   template <typename T>
   static T FPDefaultNaN();
diff --git a/src/vixl/a64/simulator-constants-a64.h b/src/vixl/a64/simulator-constants-a64.h
index 16a3c32..a144a92 100644
--- a/src/vixl/a64/simulator-constants-a64.h
+++ b/src/vixl/a64/simulator-constants-a64.h
@@ -108,22 +108,19 @@
 
 // Trace parameters.
 enum TraceParameters {
-  LOG_DISASM     = 1 << 0,  // Log disassembly.
-  LOG_REGS       = 1 << 1,  // Log general purpose registers.
-  LOG_VREGS      = 1 << 2,  // Log NEON and floating-point registers.
-  LOG_SYSREGS    = 1 << 3,  // Log the flags and system registers.
-  LOG_WRITE      = 1 << 4,  // Log writes to memory.
+  LOG_DISASM = 1 << 0,   // Log disassembly.
+  LOG_REGS = 1 << 1,     // Log general purpose registers.
+  LOG_VREGS = 1 << 2,    // Log NEON and floating-point registers.
+  LOG_SYSREGS = 1 << 3,  // Log the flags and system registers.
+  LOG_WRITE = 1 << 4,    // Log writes to memory.
 
-  LOG_NONE       = 0,
-  LOG_STATE      = LOG_REGS | LOG_VREGS | LOG_SYSREGS,
-  LOG_ALL        = LOG_DISASM | LOG_STATE | LOG_WRITE
+  LOG_NONE = 0,
+  LOG_STATE = LOG_REGS | LOG_VREGS | LOG_SYSREGS,
+  LOG_ALL = LOG_DISASM | LOG_STATE | LOG_WRITE
 };
 
 // Trace commands.
-enum TraceCommand {
-  TRACE_ENABLE   = 1,
-  TRACE_DISABLE  = 2
-};
+enum TraceCommand { TRACE_ENABLE = 1, TRACE_DISABLE = 2 };
 
 // Log - kLogOpcode
 //  - parameter: TraceParameter stored as a uint32_t
diff --git a/src/vixl/code-buffer.cc b/src/vixl/code-buffer.cc
index bb83975..1c90c74 100644
--- a/src/vixl/code-buffer.cc
+++ b/src/vixl/code-buffer.cc
@@ -76,7 +76,7 @@
   const size_t padding_size = end - cursor_;
   VIXL_ASSERT(RemainingBytes() >= padding_size);
   VIXL_ASSERT(padding_size <= 4);
-  const byte padding[] = { 0, 0, 0, 0};
+  const byte padding[] = {0, 0, 0, 0};
   dirty_ = true;
   memcpy(cursor_, padding, padding_size);
   cursor_ = end;
diff --git a/src/vixl/code-buffer.h b/src/vixl/code-buffer.h
index f93ebb6..256759a 100644
--- a/src/vixl/code-buffer.h
+++ b/src/vixl/code-buffer.h
@@ -46,9 +46,7 @@
     return cursor_offset - offset;
   }
 
-  ptrdiff_t CursorOffset() const {
-    return OffsetFrom(0);
-  }
+  ptrdiff_t CursorOffset() const { return OffsetFrom(0); }
 
   template <typename T>
   T GetOffsetAddress(ptrdiff_t offset) const {
@@ -110,4 +108,3 @@
 }  // namespace vixl
 
 #endif  // VIXL_CODE_BUFFER_H
-
diff --git a/src/vixl/compiler-intrinsics.cc b/src/vixl/compiler-intrinsics.cc
index fd551fa..970761b 100644
--- a/src/vixl/compiler-intrinsics.cc
+++ b/src/vixl/compiler-intrinsics.cc
@@ -92,12 +92,12 @@
   //                  \          |
   // value =       h+g+f+e+d+c+b+a
   const uint64_t kMasks[] = {
-    UINT64_C(0x5555555555555555),
-    UINT64_C(0x3333333333333333),
-    UINT64_C(0x0f0f0f0f0f0f0f0f),
-    UINT64_C(0x00ff00ff00ff00ff),
-    UINT64_C(0x0000ffff0000ffff),
-    UINT64_C(0x00000000ffffffff),
+      UINT64_C(0x5555555555555555),
+      UINT64_C(0x3333333333333333),
+      UINT64_C(0x0f0f0f0f0f0f0f0f),
+      UINT64_C(0x00ff00ff00ff00ff),
+      UINT64_C(0x0000ffff0000ffff),
+      UINT64_C(0x00000000ffffffff),
   };
 
   for (unsigned i = 0; i < (sizeof(kMasks) / sizeof(kMasks[0])); i++) {
diff --git a/src/vixl/compiler-intrinsics.h b/src/vixl/compiler-intrinsics.h
index 9431bed..6c87682 100644
--- a/src/vixl/compiler-intrinsics.h
+++ b/src/vixl/compiler-intrinsics.h
@@ -37,13 +37,13 @@
 #define MAJOR 1000000
 #define MINOR 1000
 #if defined(__GNUC__) && defined(__GNUC_MINOR__) && defined(__GNUC_PATCHLEVEL__)
-#define GCC_VERSION_OR_NEWER(major, minor, patchlevel)                         \
-    ((__GNUC__ * MAJOR + __GNUC_MINOR__ * MINOR + __GNUC_PATCHLEVEL__) >=      \
-     ((major) * MAJOR + (minor) * MINOR + (patchlevel)))
+#define GCC_VERSION_OR_NEWER(major, minor, patchlevel)                      \
+  ((__GNUC__ * (MAJOR) + __GNUC_MINOR__ * (MINOR) + __GNUC_PATCHLEVEL__) >= \
+   ((major) * (MAJOR) + ((minor)) * (MINOR) + (patchlevel)))
 #elif defined(__GNUC__) && defined(__GNUC_MINOR__)
-#define GCC_VERSION_OR_NEWER(major, minor, patchlevel)                         \
-    ((__GNUC__ * MAJOR + __GNUC_MINOR__ * MINOR) >=                            \
-     ((major) * MAJOR + (minor) * MINOR + (patchlevel)))
+#define GCC_VERSION_OR_NEWER(major, minor, patchlevel) \
+  ((__GNUC__ * (MAJOR) + __GNUC_MINOR__ * (MINOR)) >=  \
+   ((major) * (MAJOR) + ((minor)) * (MINOR) + (patchlevel)))
 #else
 #define GCC_VERSION_OR_NEWER(major, minor, patchlevel) 0
 #endif
@@ -51,37 +51,43 @@
 
 #if defined(__clang__) && !defined(VIXL_NO_COMPILER_BUILTINS)
 
+// clang-format off
 #define COMPILER_HAS_BUILTIN_CLRSB    (__has_builtin(__builtin_clrsb))
 #define COMPILER_HAS_BUILTIN_CLZ      (__has_builtin(__builtin_clz))
 #define COMPILER_HAS_BUILTIN_CTZ      (__has_builtin(__builtin_ctz))
 #define COMPILER_HAS_BUILTIN_FFS      (__has_builtin(__builtin_ffs))
 #define COMPILER_HAS_BUILTIN_POPCOUNT (__has_builtin(__builtin_popcount))
+// clang-format on
 
 #elif defined(__GNUC__) && !defined(VIXL_NO_COMPILER_BUILTINS)
 // The documentation for these builtins is available at:
 // https://gcc.gnu.org/onlinedocs/gcc-$MAJOR.$MINOR.$PATCHLEVEL/gcc//Other-Builtins.html
 
+// clang-format off
 # define COMPILER_HAS_BUILTIN_CLRSB    (GCC_VERSION_OR_NEWER(4, 7, 0))
 # define COMPILER_HAS_BUILTIN_CLZ      (GCC_VERSION_OR_NEWER(3, 4, 0))
 # define COMPILER_HAS_BUILTIN_CTZ      (GCC_VERSION_OR_NEWER(3, 4, 0))
 # define COMPILER_HAS_BUILTIN_FFS      (GCC_VERSION_OR_NEWER(3, 4, 0))
 # define COMPILER_HAS_BUILTIN_POPCOUNT (GCC_VERSION_OR_NEWER(3, 4, 0))
+// clang-format on
 
 #else
 // One can define VIXL_NO_COMPILER_BUILTINS to force using the manually
 // implemented C++ methods.
 
+// clang-format off
 #define COMPILER_HAS_BUILTIN_BSWAP    false
 #define COMPILER_HAS_BUILTIN_CLRSB    false
 #define COMPILER_HAS_BUILTIN_CLZ      false
 #define COMPILER_HAS_BUILTIN_CTZ      false
 #define COMPILER_HAS_BUILTIN_FFS      false
 #define COMPILER_HAS_BUILTIN_POPCOUNT false
+// clang-format on
 
 #endif
 
 
-template<typename V>
+template <typename V>
 inline bool IsPowerOf2(V value) {
   return (value != 0) && ((value & (value - 1)) == 0);
 }
@@ -98,7 +104,7 @@
 // TODO: The implementations could be improved for sizes different from 32bit
 // and 64bit: we could mask the values and call the appropriate builtin.
 
-template<typename V>
+template <typename V>
 inline int CountLeadingSignBits(V value, int width = (sizeof(V) * 8)) {
 #if COMPILER_HAS_BUILTIN_CLRSB
   if (width == 32) {
@@ -111,7 +117,7 @@
 }
 
 
-template<typename V>
+template <typename V>
 inline int CountLeadingZeros(V value, int width = (sizeof(V) * 8)) {
 #if COMPILER_HAS_BUILTIN_CLZ
   if (width == 32) {
@@ -124,7 +130,7 @@
 }
 
 
-template<typename V>
+template <typename V>
 inline int CountSetBits(V value, int width = (sizeof(V) * 8)) {
 #if COMPILER_HAS_BUILTIN_POPCOUNT
   if (width == 32) {
@@ -137,7 +143,7 @@
 }
 
 
-template<typename V>
+template <typename V>
 inline int CountTrailingZeros(V value, int width = (sizeof(V) * 8)) {
 #if COMPILER_HAS_BUILTIN_CTZ
   if (width == 32) {
@@ -152,4 +158,3 @@
 }  // namespace vixl
 
 #endif  // VIXL_COMPILER_INTRINSICS_H
-
diff --git a/src/vixl/globals.h b/src/vixl/globals.h
index 61dc9f7..3909560 100644
--- a/src/vixl/globals.h
+++ b/src/vixl/globals.h
@@ -60,30 +60,39 @@
 const int KBytes = 1024;
 const int MBytes = 1024 * KBytes;
 
-#define VIXL_ABORT() \
-    do { printf("in %s, line %i", __FILE__, __LINE__); abort(); } while (false)
+#define VIXL_ABORT()                              \
+  do {                                            \
+    printf("in %s, line %i", __FILE__, __LINE__); \
+    abort();                                      \
+  } while (false)
 #ifdef VIXL_DEBUG
-  #define VIXL_ASSERT(condition) assert(condition)
-  #define VIXL_CHECK(condition) VIXL_ASSERT(condition)
-  #define VIXL_UNIMPLEMENTED() \
-    do { fprintf(stderr, "UNIMPLEMENTED\t"); VIXL_ABORT(); } while (false)
-  #define VIXL_UNREACHABLE() \
-    do { fprintf(stderr, "UNREACHABLE\t"); VIXL_ABORT(); } while (false)
+#define VIXL_ASSERT(condition) assert(condition)
+#define VIXL_CHECK(condition) VIXL_ASSERT(condition)
+#define VIXL_UNIMPLEMENTED()            \
+  do {                                  \
+    fprintf(stderr, "UNIMPLEMENTED\t"); \
+    VIXL_ABORT();                       \
+  } while (false)
+#define VIXL_UNREACHABLE()            \
+  do {                                \
+    fprintf(stderr, "UNREACHABLE\t"); \
+    VIXL_ABORT();                     \
+  } while (false)
 #else
-  #define VIXL_ASSERT(condition) ((void) 0)
-  #define VIXL_CHECK(condition) assert(condition)
-  #define VIXL_UNIMPLEMENTED() ((void) 0)
-  #define VIXL_UNREACHABLE() ((void) 0)
+#define VIXL_ASSERT(condition) ((void)0)
+#define VIXL_CHECK(condition) assert(condition)
+#define VIXL_UNIMPLEMENTED() ((void)0)
+#define VIXL_UNREACHABLE() ((void)0)
 #endif
 // This is not as powerful as template based assertions, but it is simple.
 // It assumes that the descriptions are unique. If this starts being a problem,
 // we can switch to a different implemention.
 #define VIXL_CONCAT(a, b) a##b
-#define VIXL_STATIC_ASSERT_LINE(line, condition) \
+#define VIXL_STATIC_ASSERT_LINE(line, condition)                            \
   typedef char VIXL_CONCAT(STATIC_ASSERT_LINE_, line)[(condition) ? 1 : -1] \
-  __attribute__((unused))
+      __attribute__((unused))
 #define VIXL_STATIC_ASSERT(condition) \
-    VIXL_STATIC_ASSERT_LINE(__LINE__, condition)
+  VIXL_STATIC_ASSERT_LINE(__LINE__, condition)
 
 template <typename T1>
 inline void USE(T1) {}
@@ -97,55 +106,60 @@
 template <typename T1, typename T2, typename T3, typename T4>
 inline void USE(T1, T2, T3, T4) {}
 
-#define VIXL_ALIGNMENT_EXCEPTION() \
-    do { fprintf(stderr, "ALIGNMENT EXCEPTION\t"); VIXL_ABORT(); } while (0)
+#define VIXL_ALIGNMENT_EXCEPTION()            \
+  do {                                        \
+    fprintf(stderr, "ALIGNMENT EXCEPTION\t"); \
+    VIXL_ABORT();                             \
+  } while (0)
 
 // The clang::fallthrough attribute is used along with the Wimplicit-fallthrough
 // argument to annotate intentional fall-through between switch labels.
 // For more information please refer to:
 // http://clang.llvm.org/docs/AttributeReference.html#fallthrough-clang-fallthrough
 #ifndef __has_warning
-  #define __has_warning(x)  0
+#define __has_warning(x) 0
 #endif
 
 // Note: This option is only available for Clang. And will only be enabled for
 // C++11(201103L).
 #if __has_warning("-Wimplicit-fallthrough") && __cplusplus >= 201103L
-  #define VIXL_FALLTHROUGH() [[clang::fallthrough]] //NOLINT
+#define VIXL_FALLTHROUGH() [[clang::fallthrough]]  // NOLINT
 #else
-  #define VIXL_FALLTHROUGH() do {} while (0)
+#define VIXL_FALLTHROUGH() \
+  do {                     \
+  } while (0)
 #endif
 
 #if __cplusplus >= 201103L
-  #define VIXL_NO_RETURN  [[noreturn]] //NOLINT
+#define VIXL_NO_RETURN [[noreturn]]  // NOLINT
 #else
-  #define VIXL_NO_RETURN  __attribute__((noreturn))
+#define VIXL_NO_RETURN __attribute__((noreturn))
 #endif
 
 // Some functions might only be marked as "noreturn" for the DEBUG build. This
 // macro should be used for such cases (for more details see what
 // VIXL_UNREACHABLE expands to).
 #ifdef VIXL_DEBUG
-  #define VIXL_DEBUG_NO_RETURN  VIXL_NO_RETURN
+#define VIXL_DEBUG_NO_RETURN VIXL_NO_RETURN
 #else
-  #define VIXL_DEBUG_NO_RETURN
+#define VIXL_DEBUG_NO_RETURN
 #endif
 
 #ifdef VIXL_INCLUDE_SIMULATOR
 #ifndef VIXL_GENERATE_SIMULATOR_INSTRUCTIONS_VALUE
-  #define VIXL_GENERATE_SIMULATOR_INSTRUCTIONS_VALUE  1
+#define VIXL_GENERATE_SIMULATOR_INSTRUCTIONS_VALUE 1
 #endif
 #else
 #ifndef VIXL_GENERATE_SIMULATOR_INSTRUCTIONS_VALUE
-  #define VIXL_GENERATE_SIMULATOR_INSTRUCTIONS_VALUE  0
+#define VIXL_GENERATE_SIMULATOR_INSTRUCTIONS_VALUE 0
 #endif
 #if VIXL_GENERATE_SIMULATOR_INSTRUCTIONS_VALUE
-  #warning "Generating Simulator instructions without Simulator support."
+#warning "Generating Simulator instructions without Simulator support."
 #endif
 #endif
 
 #ifdef USE_SIMULATOR
-  #error "Please see the release notes for USE_SIMULATOR."
+#error "Please see the release notes for USE_SIMULATOR."
 #endif
 
 #endif  // VIXL_GLOBALS_H
diff --git a/src/vixl/invalset.h b/src/vixl/invalset.h
index ffdc023..4348bba 100644
--- a/src/vixl/invalset.h
+++ b/src/vixl/invalset.h
@@ -67,9 +67,10 @@
 // are used, a number of elements are preallocated.
 
 // 'ElementType' and 'KeyType' are respectively the types of the elements and
-// their key.  The structure only reclaims memory when safe to do so, if the
+// their key. The structure only reclaims memory when safe to do so, if the
 // number of elements that can be reclaimed is greater than `RECLAIM_FROM` and
 // greater than `<total number of elements> / RECLAIM_FACTOR.
+// clang-format off
 #define TEMPLATE_INVALSET_P_DECL                                               \
   class ElementType,                                                           \
   unsigned N_PREALLOCATED_ELEMENTS,                                            \
@@ -77,14 +78,17 @@
   KeyType INVALID_KEY,                                                         \
   size_t RECLAIM_FROM,                                                         \
   unsigned RECLAIM_FACTOR
+// clang-format on
 
-#define TEMPLATE_INVALSET_P_DEF                                                \
-ElementType, N_PREALLOCATED_ELEMENTS,                                          \
-KeyType, INVALID_KEY, RECLAIM_FROM, RECLAIM_FACTOR
+#define TEMPLATE_INVALSET_P_DEF                                             \
+  ElementType, N_PREALLOCATED_ELEMENTS, KeyType, INVALID_KEY, RECLAIM_FROM, \
+      RECLAIM_FACTOR
 
-template<class S> class InvalSetIterator;  // Forward declaration.
+template <class S>
+class InvalSetIterator;  // Forward declaration.
 
-template<TEMPLATE_INVALSET_P_DECL> class InvalSet {
+template <TEMPLATE_INVALSET_P_DECL>
+class InvalSet {
  public:
   InvalSet();
   ~InvalSet();
@@ -92,11 +96,17 @@
   static const size_t kNPreallocatedElements = N_PREALLOCATED_ELEMENTS;
   static const KeyType kInvalidKey = INVALID_KEY;
 
+  // C++ STL iterator interface.
+  typedef InvalSetIterator<InvalSet<TEMPLATE_INVALSET_P_DEF> > iterator;
+  iterator begin();
+  iterator end();
+
   // It is illegal to insert an element already present in the set.
   void insert(const ElementType& element);
 
   // Looks for the specified element in the set and - if found - deletes it.
-  void erase(const ElementType& element);
+  // The return value is the number of elements erased: either 0 or 1.
+  size_t erase(const ElementType& element);
 
   // This indicates the number of (valid) elements stored in this set.
   size_t size() const;
@@ -108,15 +118,18 @@
 
   void clear();
 
-  const ElementType min_element();
+  const ElementType GetMinElement();
 
   // This returns the key of the minimum element in the set.
-  KeyType min_element_key();
+  KeyType GetMinElementKey();
 
   static bool IsValid(const ElementType& element);
-  static KeyType Key(const ElementType& element);
+  static KeyType GetKey(const ElementType& element);
   static void SetKey(ElementType* element, KeyType key);
 
+  typedef ElementType _ElementType;
+  typedef KeyType _KeyType;
+
  protected:
   // Returns a pointer to the element in vector_ if it was found, or NULL
   // otherwise.
@@ -162,30 +175,30 @@
 
   // Returns the index of the element within the backing storage. The element
   // must belong to the backing storage.
-  size_t ElementIndex(const ElementType* element) const;
+  size_t GetElementIndex(const ElementType* element) const;
 
   // Returns the element at the specified index in the backing storage.
-  const ElementType* ElementAt(size_t index) const;
-  ElementType* ElementAt(size_t index);
+  const ElementType* GetElementAt(size_t index) const;
+  ElementType* GetElementAt(size_t index);
 
-  static const ElementType* FirstValidElement(const ElementType* from,
-                                              const ElementType* end);
+  static const ElementType* GetFirstValidElement(const ElementType* from,
+                                                 const ElementType* end);
 
   void CacheMinElement();
-  const ElementType CachedMinElement() const;
+  const ElementType GetCachedMinElement() const;
 
   bool ShouldReclaimMemory() const;
   void ReclaimMemory();
 
   bool IsUsingVector() const { return vector_ != NULL; }
-  void set_sorted(bool sorted) { sorted_ = sorted; }
+  void SetSorted(bool sorted) { sorted_ = sorted; }
 
   // We cache some data commonly required by users to improve performance.
   // We cannot cache pointers to elements as we do not control the backing
   // storage.
   bool valid_cached_min_;
   size_t cached_min_index_;  // Valid iff `valid_cached_min_` is true.
-  KeyType cached_min_key_;         // Valid iff `valid_cached_min_` is true.
+  KeyType cached_min_key_;   // Valid iff `valid_cached_min_` is true.
 
   // Indicates whether the elements are sorted.
   bool sorted_;
@@ -215,27 +228,51 @@
   }
 #endif
 
+ private:
+// The copy constructor and assignment operator are not used and the defaults
+// are unsafe, so disable them (without an implementation).
+#if __cplusplus >= 201103L
+  InvalSet(const InvalSet& other) = delete;
+  InvalSet operator=(const InvalSet& other) = delete;
+#else
+  InvalSet(const InvalSet& other);
+  InvalSet operator=(const InvalSet& other);
+#endif
+
   friend class InvalSetIterator<InvalSet<TEMPLATE_INVALSET_P_DEF> >;
-  typedef ElementType _ElementType;
-  typedef KeyType _KeyType;
 };
 
 
-template<class S> class InvalSetIterator {
+template <class S>
+class InvalSetIterator : public std::iterator<std::forward_iterator_tag,
+                                              typename S::_ElementType> {
  private:
   // Redefine types to mirror the associated set types.
   typedef typename S::_ElementType ElementType;
   typedef typename S::_KeyType KeyType;
 
  public:
-  explicit InvalSetIterator(S* inval_set);
-  ~InvalSetIterator();
+  explicit InvalSetIterator(S* inval_set = NULL);
 
-  ElementType* Current() const;
-  void Advance();
+  // This class implements the standard copy-swap idiom.
+  ~InvalSetIterator();
+  InvalSetIterator(const InvalSetIterator<S>& other);
+  InvalSetIterator<S>& operator=(InvalSetIterator<S> other);
+#if __cplusplus >= 201103L
+  InvalSetIterator(InvalSetIterator<S>&& other) noexcept;
+#endif
+
+  friend void swap(InvalSetIterator<S>& a, InvalSetIterator<S>& b) {
+    using std::swap;
+    swap(a.using_vector_, b.using_vector_);
+    swap(a.index_, b.index_);
+    swap(a.inval_set_, b.inval_set_);
+  }
+
+  // Return true if the iterator is at the end of the set.
   bool Done() const;
 
-  // Mark this iterator as 'done'.
+  // Move this iterator to the end of the set.
   void Finish();
 
   // Delete the current element and advance the iterator to point to the next
@@ -243,45 +280,77 @@
   void DeleteCurrentAndAdvance();
 
   static bool IsValid(const ElementType& element);
-  static KeyType Key(const ElementType& element);
+  static KeyType GetKey(const ElementType& element);
+
+  // Extra helpers to support the forward-iterator interface.
+  InvalSetIterator<S>& operator++();    // Pre-increment.
+  InvalSetIterator<S> operator++(int);  // Post-increment.
+  bool operator==(const InvalSetIterator<S>& rhs) const;
+  bool operator!=(const InvalSetIterator<S>& rhs) const {
+    return !(*this == rhs);
+  }
+  ElementType& operator*() { return *Current(); }
+  const ElementType& operator*() const { return *Current(); }
+  ElementType* operator->() { return Current(); }
+  const ElementType* operator->() const { return Current(); }
 
  protected:
   void MoveToValidElement();
 
   // Indicates if the iterator is looking at the vector or at the preallocated
   // elements.
-  const bool using_vector_;
+  bool using_vector_;
   // Used when looking at the preallocated elements, or in debug mode when using
   // the vector to track how many times the iterator has advanced.
   size_t index_;
   typename std::vector<ElementType>::iterator iterator_;
   S* inval_set_;
+
+  // TODO: These helpers are deprecated and will be removed in future versions
+  // of VIXL.
+  ElementType* Current() const;
+  void Advance();
 };
 
 
-template<TEMPLATE_INVALSET_P_DECL>
+template <TEMPLATE_INVALSET_P_DECL>
 InvalSet<TEMPLATE_INVALSET_P_DEF>::InvalSet()
-  : valid_cached_min_(false),
-    sorted_(true), size_(0), vector_(NULL) {
+    : valid_cached_min_(false), sorted_(true), size_(0), vector_(NULL) {
 #ifdef VIXL_DEBUG
   monitor_ = 0;
 #endif
 }
 
 
-template<TEMPLATE_INVALSET_P_DECL>
+template <TEMPLATE_INVALSET_P_DECL>
 InvalSet<TEMPLATE_INVALSET_P_DEF>::~InvalSet() {
   VIXL_ASSERT(monitor_ == 0);
   delete vector_;
 }
 
 
-template<TEMPLATE_INVALSET_P_DECL>
+template <TEMPLATE_INVALSET_P_DECL>
+typename InvalSet<TEMPLATE_INVALSET_P_DEF>::iterator
+InvalSet<TEMPLATE_INVALSET_P_DEF>::begin() {
+  return iterator(this);
+}
+
+
+template <TEMPLATE_INVALSET_P_DECL>
+typename InvalSet<TEMPLATE_INVALSET_P_DEF>::iterator
+InvalSet<TEMPLATE_INVALSET_P_DEF>::end() {
+  iterator end(this);
+  end.Finish();
+  return end;
+}
+
+
+template <TEMPLATE_INVALSET_P_DECL>
 void InvalSet<TEMPLATE_INVALSET_P_DEF>::insert(const ElementType& element) {
   VIXL_ASSERT(monitor() == 0);
   VIXL_ASSERT(IsValid(element));
   VIXL_ASSERT(Search(element) == NULL);
-  set_sorted(empty() || (sorted_ && (element > CleanBack())));
+  SetSorted(empty() || (sorted_ && (element > CleanBack())));
   if (IsUsingVector()) {
     vector_->push_back(element);
   } else {
@@ -289,16 +358,16 @@
       preallocated_[size_] = element;
     } else {
       // Transition to using the vector.
-      vector_ = new std::vector<ElementType>(preallocated_,
-                                             preallocated_ + size_);
+      vector_ =
+          new std::vector<ElementType>(preallocated_, preallocated_ + size_);
       vector_->push_back(element);
     }
   }
   size_++;
 
-  if (valid_cached_min_ && (element < min_element())) {
+  if (valid_cached_min_ && (element < GetMinElement())) {
     cached_min_index_ = IsUsingVector() ? vector_->size() - 1 : size_ - 1;
-    cached_min_key_ = Key(element);
+    cached_min_key_ = GetKey(element);
     valid_cached_min_ = true;
   }
 
@@ -308,18 +377,20 @@
 }
 
 
-template<TEMPLATE_INVALSET_P_DECL>
-void InvalSet<TEMPLATE_INVALSET_P_DEF>::erase(const ElementType& element) {
+template <TEMPLATE_INVALSET_P_DECL>
+size_t InvalSet<TEMPLATE_INVALSET_P_DEF>::erase(const ElementType& element) {
   VIXL_ASSERT(monitor() == 0);
   VIXL_ASSERT(IsValid(element));
   ElementType* local_element = Search(element);
   if (local_element != NULL) {
     EraseInternal(local_element);
+    return 1;
   }
+  return 0;
 }
 
 
-template<TEMPLATE_INVALSET_P_DECL>
+template <TEMPLATE_INVALSET_P_DECL>
 ElementType* InvalSet<TEMPLATE_INVALSET_P_DEF>::Search(
     const ElementType& element) {
   VIXL_ASSERT(monitor() == 0);
@@ -335,66 +406,66 @@
   if (!valid_cached_min_) {
     CacheMinElement();
   }
-  return BinarySearch(element, ElementAt(cached_min_index_), StorageEnd());
+  return BinarySearch(element, GetElementAt(cached_min_index_), StorageEnd());
 }
 
 
-template<TEMPLATE_INVALSET_P_DECL>
+template <TEMPLATE_INVALSET_P_DECL>
 size_t InvalSet<TEMPLATE_INVALSET_P_DEF>::size() const {
   return size_;
 }
 
 
-template<TEMPLATE_INVALSET_P_DECL>
+template <TEMPLATE_INVALSET_P_DECL>
 bool InvalSet<TEMPLATE_INVALSET_P_DEF>::empty() const {
   return size_ == 0;
 }
 
 
-template<TEMPLATE_INVALSET_P_DECL>
+template <TEMPLATE_INVALSET_P_DECL>
 void InvalSet<TEMPLATE_INVALSET_P_DEF>::clear() {
   VIXL_ASSERT(monitor() == 0);
   size_ = 0;
   if (IsUsingVector()) {
     vector_->clear();
   }
-  set_sorted(true);
+  SetSorted(true);
   valid_cached_min_ = false;
 }
 
 
-template<TEMPLATE_INVALSET_P_DECL>
-const ElementType InvalSet<TEMPLATE_INVALSET_P_DEF>::min_element() {
+template <TEMPLATE_INVALSET_P_DECL>
+const ElementType InvalSet<TEMPLATE_INVALSET_P_DEF>::GetMinElement() {
   VIXL_ASSERT(monitor() == 0);
   VIXL_ASSERT(!empty());
   CacheMinElement();
-  return *ElementAt(cached_min_index_);
+  return *GetElementAt(cached_min_index_);
 }
 
 
-template<TEMPLATE_INVALSET_P_DECL>
-KeyType InvalSet<TEMPLATE_INVALSET_P_DEF>::min_element_key() {
+template <TEMPLATE_INVALSET_P_DECL>
+KeyType InvalSet<TEMPLATE_INVALSET_P_DEF>::GetMinElementKey() {
   VIXL_ASSERT(monitor() == 0);
   if (valid_cached_min_) {
     return cached_min_key_;
   } else {
-    return Key(min_element());
+    return GetKey(GetMinElement());
   }
 }
 
 
-template<TEMPLATE_INVALSET_P_DECL>
+template <TEMPLATE_INVALSET_P_DECL>
 bool InvalSet<TEMPLATE_INVALSET_P_DEF>::IsValid(const ElementType& element) {
-  return Key(element) != kInvalidKey;
+  return GetKey(element) != kInvalidKey;
 }
 
 
-template<TEMPLATE_INVALSET_P_DECL>
+template <TEMPLATE_INVALSET_P_DECL>
 void InvalSet<TEMPLATE_INVALSET_P_DEF>::EraseInternal(ElementType* element) {
   // Note that this function must be safe even while an iterator has acquired
   // this set.
   VIXL_ASSERT(element != NULL);
-  size_t deleted_index = ElementIndex(element);
+  size_t deleted_index = GetElementIndex(element);
   if (IsUsingVector()) {
     VIXL_ASSERT((&(vector_->front()) <= element) &&
                 (element <= &(vector_->back())));
@@ -408,12 +479,11 @@
   }
   size_--;
 
-  if (valid_cached_min_ &&
-      (deleted_index == cached_min_index_)) {
+  if (valid_cached_min_ && (deleted_index == cached_min_index_)) {
     if (sorted_ && !empty()) {
-      const ElementType* min = FirstValidElement(element, StorageEnd());
-      cached_min_index_ = ElementIndex(min);
-      cached_min_key_ = Key(*min);
+      const ElementType* min = GetFirstValidElement(element, StorageEnd());
+      cached_min_index_ = GetElementIndex(min);
+      cached_min_key_ = GetKey(*min);
       valid_cached_min_ = true;
     } else {
       valid_cached_min_ = false;
@@ -422,7 +492,7 @@
 }
 
 
-template<TEMPLATE_INVALSET_P_DECL>
+template <TEMPLATE_INVALSET_P_DECL>
 ElementType* InvalSet<TEMPLATE_INVALSET_P_DEF>::BinarySearch(
     const ElementType& element, ElementType* start, ElementType* end) const {
   if (start == end) {
@@ -443,12 +513,12 @@
     while (!IsValid(elements[high]) && (low < high)) --high;
     VIXL_ASSERT(low <= high);
     // Avoid overflow when computing the middle index.
-    size_t middle = low / 2 + high / 2 + (low & high & 1);
+    size_t middle = low + (high - low) / 2;
     if ((middle == low) || (middle == high)) {
       break;
     }
-    while (!IsValid(elements[middle]) && (middle < high - 1)) ++middle;
-    while (!IsValid(elements[middle]) && (low + 1 < middle)) --middle;
+    while ((middle < high - 1) && !IsValid(elements[middle])) ++middle;
+    while ((low + 1 < middle) && !IsValid(elements[middle])) --middle;
     if (!IsValid(elements[middle])) {
       break;
     }
@@ -465,14 +535,14 @@
 }
 
 
-template<TEMPLATE_INVALSET_P_DECL>
+template <TEMPLATE_INVALSET_P_DECL>
 void InvalSet<TEMPLATE_INVALSET_P_DEF>::Sort(SortType sort_type) {
-  VIXL_ASSERT(monitor() == 0);
   if (sort_type == kSoftSort) {
     if (sorted_) {
       return;
     }
   }
+  VIXL_ASSERT(monitor() == 0);
   if (empty()) {
     return;
   }
@@ -480,14 +550,14 @@
   Clean();
   std::sort(StorageBegin(), StorageEnd());
 
-  set_sorted(true);
+  SetSorted(true);
   cached_min_index_ = 0;
-  cached_min_key_ = Key(Front());
+  cached_min_key_ = GetKey(Front());
   valid_cached_min_ = true;
 }
 
 
-template<TEMPLATE_INVALSET_P_DECL>
+template <TEMPLATE_INVALSET_P_DECL>
 void InvalSet<TEMPLATE_INVALSET_P_DEF>::Clean() {
   VIXL_ASSERT(monitor() == 0);
   if (empty() || !IsUsingVector()) {
@@ -501,17 +571,17 @@
   ElementType* first_valid;
   ElementType* next_invalid;
 
-  while (c < end && IsValid(*c)) { c++; }
+  while ((c < end) && IsValid(*c)) c++;
   first_invalid = c;
 
   while (c < end) {
-    while (c < end && !IsValid(*c)) { c++; }
+    while ((c < end) && !IsValid(*c)) c++;
     first_valid = c;
-    while (c < end && IsValid(*c)) { c++; }
+    while ((c < end) && IsValid(*c)) c++;
     next_invalid = c;
 
     ptrdiff_t n_moved_elements = (next_invalid - first_valid);
-    memmove(first_invalid, first_valid,  n_moved_elements * sizeof(*c));
+    memmove(first_invalid, first_valid, n_moved_elements * sizeof(*c));
     first_invalid = first_invalid + n_moved_elements;
     c = next_invalid;
   }
@@ -523,28 +593,28 @@
   if (sorted_) {
     valid_cached_min_ = true;
     cached_min_index_ = 0;
-    cached_min_key_ = Key(*ElementAt(0));
+    cached_min_key_ = GetKey(*GetElementAt(0));
   } else {
     valid_cached_min_ = false;
   }
 }
 
 
-template<TEMPLATE_INVALSET_P_DECL>
+template <TEMPLATE_INVALSET_P_DECL>
 const ElementType InvalSet<TEMPLATE_INVALSET_P_DEF>::Front() const {
   VIXL_ASSERT(!empty());
   return IsUsingVector() ? vector_->front() : preallocated_[0];
 }
 
 
-template<TEMPLATE_INVALSET_P_DECL>
+template <TEMPLATE_INVALSET_P_DECL>
 const ElementType InvalSet<TEMPLATE_INVALSET_P_DEF>::Back() const {
   VIXL_ASSERT(!empty());
   return IsUsingVector() ? vector_->back() : preallocated_[size_ - 1];
 }
 
 
-template<TEMPLATE_INVALSET_P_DECL>
+template <TEMPLATE_INVALSET_P_DECL>
 const ElementType InvalSet<TEMPLATE_INVALSET_P_DEF>::CleanBack() {
   VIXL_ASSERT(monitor() == 0);
   if (IsUsingVector()) {
@@ -559,55 +629,55 @@
 }
 
 
-template<TEMPLATE_INVALSET_P_DECL>
+template <TEMPLATE_INVALSET_P_DECL>
 const ElementType* InvalSet<TEMPLATE_INVALSET_P_DEF>::StorageBegin() const {
   return IsUsingVector() ? &(vector_->front()) : preallocated_;
 }
 
 
-template<TEMPLATE_INVALSET_P_DECL>
+template <TEMPLATE_INVALSET_P_DECL>
 const ElementType* InvalSet<TEMPLATE_INVALSET_P_DEF>::StorageEnd() const {
   return IsUsingVector() ? &(vector_->back()) + 1 : preallocated_ + size_;
 }
 
 
-template<TEMPLATE_INVALSET_P_DECL>
+template <TEMPLATE_INVALSET_P_DECL>
 ElementType* InvalSet<TEMPLATE_INVALSET_P_DEF>::StorageBegin() {
   return IsUsingVector() ? &(vector_->front()) : preallocated_;
 }
 
 
-template<TEMPLATE_INVALSET_P_DECL>
+template <TEMPLATE_INVALSET_P_DECL>
 ElementType* InvalSet<TEMPLATE_INVALSET_P_DEF>::StorageEnd() {
   return IsUsingVector() ? &(vector_->back()) + 1 : preallocated_ + size_;
 }
 
 
-template<TEMPLATE_INVALSET_P_DECL>
-size_t InvalSet<TEMPLATE_INVALSET_P_DEF>::ElementIndex(
+template <TEMPLATE_INVALSET_P_DECL>
+size_t InvalSet<TEMPLATE_INVALSET_P_DEF>::GetElementIndex(
     const ElementType* element) const {
   VIXL_ASSERT((StorageBegin() <= element) && (element < StorageEnd()));
   return element - StorageBegin();
 }
 
 
-template<TEMPLATE_INVALSET_P_DECL>
-const ElementType* InvalSet<TEMPLATE_INVALSET_P_DEF>::ElementAt(
+template <TEMPLATE_INVALSET_P_DECL>
+const ElementType* InvalSet<TEMPLATE_INVALSET_P_DEF>::GetElementAt(
     size_t index) const {
-  VIXL_ASSERT(
-      (IsUsingVector() && (index < vector_->size())) || (index < size_));
+  VIXL_ASSERT((IsUsingVector() && (index < vector_->size())) ||
+              (index < size_));
   return StorageBegin() + index;
 }
 
-template<TEMPLATE_INVALSET_P_DECL>
-ElementType* InvalSet<TEMPLATE_INVALSET_P_DEF>::ElementAt(size_t index) {
-  VIXL_ASSERT(
-      (IsUsingVector() && (index < vector_->size())) || (index < size_));
+template <TEMPLATE_INVALSET_P_DECL>
+ElementType* InvalSet<TEMPLATE_INVALSET_P_DEF>::GetElementAt(size_t index) {
+  VIXL_ASSERT((IsUsingVector() && (index < vector_->size())) ||
+              (index < size_));
   return StorageBegin() + index;
 }
 
-template<TEMPLATE_INVALSET_P_DECL>
-const ElementType* InvalSet<TEMPLATE_INVALSET_P_DEF>::FirstValidElement(
+template <TEMPLATE_INVALSET_P_DECL>
+const ElementType* InvalSet<TEMPLATE_INVALSET_P_DEF>::GetFirstValidElement(
     const ElementType* from, const ElementType* end) {
   while ((from < end) && !IsValid(*from)) {
     from++;
@@ -616,7 +686,7 @@
 }
 
 
-template<TEMPLATE_INVALSET_P_DECL>
+template <TEMPLATE_INVALSET_P_DECL>
 void InvalSet<TEMPLATE_INVALSET_P_DEF>::CacheMinElement() {
   VIXL_ASSERT(monitor() == 0);
   VIXL_ASSERT(!empty());
@@ -626,9 +696,9 @@
   }
 
   if (sorted_) {
-    const ElementType* min = FirstValidElement(StorageBegin(), StorageEnd());
-    cached_min_index_ = ElementIndex(min);
-    cached_min_key_ = Key(*min);
+    const ElementType* min = GetFirstValidElement(StorageBegin(), StorageEnd());
+    cached_min_index_ = GetElementIndex(min);
+    cached_min_key_ = GetKey(*min);
     valid_cached_min_ = true;
   } else {
     Sort(kHardSort);
@@ -637,7 +707,7 @@
 }
 
 
-template<TEMPLATE_INVALSET_P_DECL>
+template <TEMPLATE_INVALSET_P_DECL>
 bool InvalSet<TEMPLATE_INVALSET_P_DEF>::ShouldReclaimMemory() const {
   if (!IsUsingVector()) {
     return false;
@@ -648,14 +718,14 @@
 }
 
 
-template<TEMPLATE_INVALSET_P_DECL>
+template <TEMPLATE_INVALSET_P_DECL>
 void InvalSet<TEMPLATE_INVALSET_P_DEF>::ReclaimMemory() {
   VIXL_ASSERT(monitor() == 0);
   Clean();
 }
 
 
-template<class S>
+template <class S>
 InvalSetIterator<S>::InvalSetIterator(S* inval_set)
     : using_vector_((inval_set != NULL) && inval_set->IsUsingVector()),
       index_(0),
@@ -674,17 +744,15 @@
 }
 
 
-template<class S>
+template <class S>
 InvalSetIterator<S>::~InvalSetIterator() {
 #ifdef VIXL_DEBUG
-  if (inval_set_ != NULL) {
-    inval_set_->Release();
-  }
+  if (inval_set_ != NULL) inval_set_->Release();
 #endif
 }
 
 
-template<class S>
+template <class S>
 typename S::_ElementType* InvalSetIterator<S>::Current() const {
   VIXL_ASSERT(!Done());
   if (using_vector_) {
@@ -695,22 +763,13 @@
 }
 
 
-template<class S>
+template <class S>
 void InvalSetIterator<S>::Advance() {
-  VIXL_ASSERT(!Done());
-  if (using_vector_) {
-    iterator_++;
-#ifdef VIXL_DEBUG
-    index_++;
-#endif
-    MoveToValidElement();
-  } else {
-    index_++;
-  }
+  ++(*this);
 }
 
 
-template<class S>
+template <class S>
 bool InvalSetIterator<S>::Done() const {
   if (using_vector_) {
     bool done = (iterator_ == inval_set_->vector_->end());
@@ -722,7 +781,7 @@
 }
 
 
-template<class S>
+template <class S>
 void InvalSetIterator<S>::Finish() {
   VIXL_ASSERT(inval_set_->sorted_);
   if (using_vector_) {
@@ -732,7 +791,7 @@
 }
 
 
-template<class S>
+template <class S>
 void InvalSetIterator<S>::DeleteCurrentAndAdvance() {
   if (using_vector_) {
     inval_set_->EraseInternal(&(*iterator_));
@@ -743,19 +802,19 @@
 }
 
 
-template<class S>
+template <class S>
 bool InvalSetIterator<S>::IsValid(const ElementType& element) {
   return S::IsValid(element);
 }
 
 
-template<class S>
-typename S::_KeyType InvalSetIterator<S>::Key(const ElementType& element) {
-  return S::Key(element);
+template <class S>
+typename S::_KeyType InvalSetIterator<S>::GetKey(const ElementType& element) {
+  return S::GetKey(element);
 }
 
 
-template<class S>
+template <class S>
 void InvalSetIterator<S>::MoveToValidElement() {
   if (using_vector_) {
     while ((iterator_ != inval_set_->vector_->end()) && !IsValid(*iterator_)) {
@@ -767,6 +826,87 @@
   }
 }
 
+
+template <class S>
+InvalSetIterator<S>::InvalSetIterator(const InvalSetIterator<S>& other)
+    : using_vector_(other.using_vector_),
+      index_(other.index_),
+      inval_set_(other.inval_set_) {
+#ifdef VIXL_DEBUG
+  if (inval_set_ != NULL) inval_set_->Acquire();
+#endif
+}
+
+
+#if __cplusplus >= 201103L
+template <class S>
+InvalSetIterator<S>::InvalSetIterator(InvalSetIterator<S>&& other) noexcept
+    : using_vector_(false),
+      index_(0),
+      inval_set_(NULL) {
+  swap(*this, other);
+}
+#endif
+
+
+template <class S>
+InvalSetIterator<S>& InvalSetIterator<S>::operator=(InvalSetIterator<S> other) {
+  swap(*this, other);
+  return *this;
+}
+
+
+template <class S>
+bool InvalSetIterator<S>::operator==(const InvalSetIterator<S>& rhs) const {
+  bool equal = (inval_set_ == rhs.inval_set_);
+
+  // If the inval_set_ matches, using_vector_ must also match.
+  VIXL_ASSERT(!equal || (using_vector_ == rhs.using_vector_));
+
+  if (using_vector_) {
+    equal = equal && (iterator_ == rhs.iterator_);
+    // In debug mode, index_ is maintained even with using_vector_.
+    VIXL_ASSERT(!equal || (index_ == rhs.index_));
+  } else {
+    equal = equal && (index_ == rhs.index_);
+#ifdef DEBUG
+    // If not using_vector_, iterator_ should be default-initialised.
+    std::vector<ElementType>::iterator default_iterator;
+    VIXL_ASSERT(iterator_ == default_iterator);
+    VIXL_ASSERT(rhs.iterator_ == default_iterator);
+#endif
+  }
+  return equal;
+}
+
+
+template <class S>
+InvalSetIterator<S>& InvalSetIterator<S>::operator++() {
+  // Pre-increment.
+  VIXL_ASSERT(!Done());
+  if (using_vector_) {
+    iterator_++;
+#ifdef VIXL_DEBUG
+    index_++;
+#endif
+    MoveToValidElement();
+  } else {
+    index_++;
+  }
+  return *this;
+}
+
+
+template <class S>
+InvalSetIterator<S> InvalSetIterator<S>::operator++(int /* unused */) {
+  // Post-increment.
+  VIXL_ASSERT(!Done());
+  InvalSetIterator<S> old(*this);
+  ++(*this);
+  return old;
+}
+
+
 #undef TEMPLATE_INVALSET_P_DECL
 #undef TEMPLATE_INVALSET_P_DEF
 
diff --git a/src/vixl/utils.h b/src/vixl/utils.h
index 5ab134e..e84d7c6 100644
--- a/src/vixl/utils.h
+++ b/src/vixl/utils.h
@@ -59,6 +59,7 @@
   return static_cast<uint32_t>(x & ((INT64_C(1) << n) - 1));
 }
 
+// clang-format off
 #define INT_1_TO_63_LIST(V)                                                    \
 V(1)  V(2)  V(3)  V(4)  V(5)  V(6)  V(7)  V(8)                                 \
 V(9)  V(10) V(11) V(12) V(13) V(14) V(15) V(16)                                \
@@ -68,13 +69,14 @@
 V(41) V(42) V(43) V(44) V(45) V(46) V(47) V(48)                                \
 V(49) V(50) V(51) V(52) V(53) V(54) V(55) V(56)                                \
 V(57) V(58) V(59) V(60) V(61) V(62) V(63)
+// clang-format on
 
-#define DECLARE_IS_INT_N(N)                                                    \
-inline bool is_int##N(int64_t x) { return is_intn(N, x); }
-#define DECLARE_IS_UINT_N(N)                                                   \
-inline bool is_uint##N(int64_t x) { return is_uintn(N, x); }
-#define DECLARE_TRUNCATE_TO_INT_N(N)                                           \
-inline uint32_t truncate_to_int##N(int x) { return truncate_to_intn(N, x); }
+#define DECLARE_IS_INT_N(N) \
+  inline bool is_int##N(int64_t x) { return is_intn(N, x); }
+#define DECLARE_IS_UINT_N(N) \
+  inline bool is_uint##N(int64_t x) { return is_uintn(N, x); }
+#define DECLARE_TRUNCATE_TO_INT_N(N) \
+  inline uint32_t truncate_to_int##N(int x) { return truncate_to_intn(N, x); }
 INT_1_TO_63_LIST(DECLARE_IS_INT_N)
 INT_1_TO_63_LIST(DECLARE_IS_UINT_N)
 INT_1_TO_63_LIST(DECLARE_TRUNCATE_TO_INT_N)
@@ -141,8 +143,7 @@
 
 inline bool IsSignallingNaN(float16 num) {
   const uint16_t kFP16QuietNaNMask = 0x0200;
-  return (float16classify(num) == FP_NAN) &&
-         ((num & kFP16QuietNaNMask) == 0);
+  return (float16classify(num) == FP_NAN) && ((num & kFP16QuietNaNMask) == 0);
 }
 
 
@@ -178,19 +179,17 @@
 }
 
 
-inline uint64_t LowestSetBit(uint64_t value) {
-  return value & -value;
-}
+inline uint64_t LowestSetBit(uint64_t value) { return value & -value; }
 
 
-template<typename T>
+template <typename T>
 inline int HighestSetBitPosition(T value) {
   VIXL_ASSERT(value != 0);
   return (sizeof(value) * 8 - 1) - CountLeadingZeros(value);
 }
 
 
-template<typename V>
+template <typename V>
 inline int WhichPowerOf2(V value) {
   VIXL_ASSERT(IsPowerOf2(value));
   return CountTrailingZeros(value);
@@ -231,9 +230,9 @@
   //  permute_table[1] is used by REV32_x, REV_w
   //  permute_table[2] is used by REV_x
   VIXL_ASSERT((0 < block_bytes_log2) && (block_bytes_log2 < 4));
-  static const uint8_t permute_table[3][8] = { {6, 7, 4, 5, 2, 3, 0, 1},
-                                               {4, 5, 6, 7, 0, 1, 2, 3},
-                                               {0, 1, 2, 3, 4, 5, 6, 7} };
+  static const uint8_t permute_table[3][8] = {{6, 7, 4, 5, 2, 3, 0, 1},
+                                              {4, 5, 6, 7, 0, 1, 2, 3},
+                                              {0, 1, 2, 3, 4, 5, 6, 7}};
   T result = 0;
   for (int i = 0; i < 8; i++) {
     result <<= 8;
@@ -245,14 +244,14 @@
 
 // Pointer alignment
 // TODO: rename/refactor to make it specific to instructions.
-template<typename T>
+template <typename T>
 bool IsWordAligned(T pointer) {
-  VIXL_ASSERT(sizeof(pointer) == sizeof(intptr_t));   // NOLINT(runtime/sizeof)
-  return ((intptr_t)(pointer) & 3) == 0;
+  VIXL_ASSERT(sizeof(pointer) == sizeof(intptr_t));  // NOLINT(runtime/sizeof)
+  return ((intptr_t)pointer & 3) == 0;
 }
 
 // Increment a pointer (up to 64 bits) until it has the specified alignment.
-template<class T>
+template <class T>
 T AlignUp(T pointer, size_t alignment) {
   // Use C-style casts to get static_cast behaviour for integral types (T), and
   // reinterpret_cast behaviour for other types.
@@ -267,7 +266,7 @@
 }
 
 // Decrement a pointer (up to 64 bits) until it has the specified alignment.
-template<class T>
+template <class T>
 T AlignDown(T pointer, size_t alignment) {
   // Use C-style casts to get static_cast behaviour for integral types (T), and
   // reinterpret_cast behaviour for other types.
diff --git a/test/test-assembler-a64.cc b/test/test-assembler-a64.cc
index 67cdf73..e6b67cd 100644
--- a/test/test-assembler-a64.cc
+++ b/test/test-assembler-a64.cc
@@ -22007,4 +22007,12 @@
 }
 
 
+TEST(move_immediate_helpers) {
+  // Using these helpers to query information (without generating code) should
+  // not crash.
+  MacroAssembler::MoveImmediateHelper(NULL, x0, 0x12345678);
+  MacroAssembler::OneInstrMoveImmediateHelper(NULL, x1, 0xabcdef);
+}
+
+
 }  // namespace vixl
diff --git a/test/test-disasm-a64.cc b/test/test-disasm-a64.cc
index d4fa02f..3980104 100644
--- a/test/test-disasm-a64.cc
+++ b/test/test-disasm-a64.cc
@@ -26,6 +26,7 @@
 
 #include <stdio.h>
 #include <cstring>
+#include <string>
 #include "test-runner.h"
 
 #include "vixl/a64/macro-assembler-a64.h"
@@ -94,19 +95,44 @@
     printf("%08" PRIx32 "\t%s\n", encoding, disasm->GetOutput());              \
   }
 
-#define COMPARE_MACRO(ASM, EXP)                                                \
+#define COMPARE_MACRO_BASE(ASM, EXP)                                           \
   masm->Reset();                                                               \
   masm->ASM;                                                                   \
   masm->FinalizeCode();                                                        \
-  decoder->Decode(reinterpret_cast<Instruction*>(buf));                        \
-  encoding = *reinterpret_cast<uint32_t*>(buf);                                \
-  if (strncmp(disasm->GetOutput(), EXP, strlen(EXP)) != 0) {                   \
-    printf("\nEncoding: %08" PRIx32 "\nExpected: %s\nFound:    %s\n",          \
-           encoding, EXP, disasm->GetOutput());                                \
-    abort();                                                                   \
-  }                                                                            \
-  if (Test::trace_sim()) {                                                     \
-    printf("%08" PRIx32 "\t%s\n", encoding, disasm->GetOutput());              \
+  std::string res;                                                             \
+                                                                               \
+  Instruction* instruction = masm->GetOffsetAddress<Instruction*>(0);          \
+  Instruction* end = masm->GetOffsetAddress<Instruction*>(                     \
+      masm->SizeOfCodeGenerated());                                            \
+  while (instruction != end) {                                                 \
+    decoder->Decode(instruction);                                              \
+    res.append(disasm->GetOutput());                                           \
+    if (Test::trace_sim()) {                                                   \
+      encoding = *reinterpret_cast<uint32_t*>(instruction);                    \
+      printf("%08" PRIx32 "\t%s\n", encoding, disasm->GetOutput());            \
+    }                                                                          \
+    instruction += kInstructionSize;                                           \
+    if (instruction != end) {                                                  \
+      res.append("\n");                                                        \
+    }                                                                          \
+  }
+
+#define COMPARE_MACRO(ASM, EXP)                                                \
+  {                                                                            \
+    COMPARE_MACRO_BASE(ASM, EXP)                                               \
+    if (strcmp(res.c_str(), EXP) != 0) {                                       \
+      printf("Expected: %s\nFound:    %s\n", EXP, res.c_str());                \
+      abort();                                                                 \
+    }                                                                          \
+  }
+
+#define COMPARE_MACRO_PREFIX(ASM, EXP)                                         \
+  {                                                                            \
+    COMPARE_MACRO_BASE(ASM, EXP)                                               \
+    if (strncmp(res.c_str(), EXP, strlen(EXP)) != 0) {                         \
+      printf("Expected (prefix): %s\nFound:    %s\n", EXP, res.c_str());       \
+      abort();                                                                 \
+    }                                                                          \
   }
 
 #define CLEANUP()                                                              \
@@ -2200,12 +2226,215 @@
 TEST(cond_select_macro) {
   SETUP_MACRO();
 
+  // In the tests below we also test the `GetCselSynthesisInformation()` helper.
+  // These tests are here (rather than in test-assembler-a64.cc) because the
+  // disassembly makes it easy to see whether or not the inputs are synthesised.
+  bool synthesises_left = false;
+  bool synthesises_right = false;
+
   COMPARE(Csel(w0, w1, -1, eq), "csinv w0, w1, wzr, eq");
+  MacroAssembler::GetCselSynthesisInformation(w0, w1, -1,
+                                              &synthesises_left,
+                                              &synthesises_right);
+  VIXL_CHECK(!synthesises_left && !synthesises_right);
+
   COMPARE(Csel(w2, w3, 0, ne), "csel w2, w3, wzr, ne");
+  MacroAssembler::GetCselSynthesisInformation(w2, w3, wzr,
+                                              &synthesises_left,
+                                              &synthesises_right);
+  VIXL_CHECK(!synthesises_left && !synthesises_right);
+
   COMPARE(Csel(w4, w5, 1, hs), "csinc w4, w5, wzr, hs");
+  MacroAssembler::GetCselSynthesisInformation(w4, w5, 1,
+                                              &synthesises_left,
+                                              &synthesises_right);
+  VIXL_CHECK(!synthesises_left && !synthesises_right);
+
   COMPARE(Csel(x6, x7, -1, lo), "csinv x6, x7, xzr, lo");
+  MacroAssembler::GetCselSynthesisInformation(x6, x7, xzr,
+                                              &synthesises_left,
+                                              &synthesises_right);
+  VIXL_CHECK(!synthesises_left && !synthesises_right);
+
   COMPARE(Csel(x8, x9, 0, mi), "csel x8, x9, xzr, mi");
+  MacroAssembler::GetCselSynthesisInformation(x8, x9, xzr,
+                                              &synthesises_left,
+                                              &synthesises_right);
+  VIXL_CHECK(!synthesises_left && !synthesises_right);
+
   COMPARE(Csel(x10, x11, 1, pl), "csinc x10, x11, xzr, pl");
+  MacroAssembler::GetCselSynthesisInformation(x10, x11, xzr,
+                                              &synthesises_left,
+                                              &synthesises_right);
+  VIXL_CHECK(!synthesises_left && !synthesises_right);
+
+  COMPARE_MACRO(Csel(x12,     0,     0, eq), "mov x12, #0x0");
+  MacroAssembler::GetCselSynthesisInformation(x12, 0, 0,
+                                              &synthesises_left,
+                                              &synthesises_right);
+  VIXL_CHECK(!synthesises_left && !synthesises_right);
+
+  COMPARE_MACRO(Csel(w13,     0,     1, eq), "cset w13, eq");
+  MacroAssembler::GetCselSynthesisInformation(w13, 0, 1,
+                                              &synthesises_left,
+                                              &synthesises_right);
+  VIXL_CHECK(!synthesises_left && !synthesises_right);
+
+  COMPARE_MACRO(Csel(x14,     1,     0, eq), "cset x14, ne");
+  MacroAssembler::GetCselSynthesisInformation(x14, 1, 0,
+                                              &synthesises_left,
+                                              &synthesises_right);
+  VIXL_CHECK(!synthesises_left && !synthesises_right);
+
+  COMPARE_MACRO(Csel(w15,     0,    -1, eq), "csetm w15, eq");
+  MacroAssembler::GetCselSynthesisInformation(w15, 0, -1,
+                                              &synthesises_left,
+                                              &synthesises_right);
+  VIXL_CHECK(!synthesises_left && !synthesises_right);
+
+  COMPARE_MACRO(Csel(x18,    -1,     0, eq), "csetm x18, ne");
+  MacroAssembler::GetCselSynthesisInformation(x18, -1, 0,
+                                              &synthesises_left,
+                                              &synthesises_right);
+  VIXL_CHECK(!synthesises_left && !synthesises_right);
+
+  COMPARE_MACRO(Csel(w19,    -1,     1, eq), "mov w19, #0x1\n"
+                                             "cneg w19, w19, eq");
+  MacroAssembler::GetCselSynthesisInformation(w19, -1, 1,
+                                              &synthesises_left,
+                                              &synthesises_right);
+  VIXL_CHECK(!synthesises_left && synthesises_right);
+
+  COMPARE_MACRO(Csel(x20,     1,    -1, eq), "mov x20, #0xffffffffffffffff\n"
+                                             "cneg x20, x20, eq");
+  MacroAssembler::GetCselSynthesisInformation(x20, 1, -1,
+                                              &synthesises_left,
+                                              &synthesises_right);
+  VIXL_CHECK(!synthesises_left && synthesises_right);
+
+  COMPARE_MACRO(Csel(w21,  0xaa,  0xbb, eq), "mov w16, #0xaa\n"
+                                             "mov w17, #0xbb\n"
+                                             "csel w21, w16, w17, eq");
+  MacroAssembler::GetCselSynthesisInformation(w21, 0xaa, 0xbb,
+                                              &synthesises_left,
+                                              &synthesises_right);
+  VIXL_CHECK(synthesises_left && synthesises_right);
+
+  COMPARE_MACRO(Csel(x22,  0xaa, -0xbb, eq), "mov x16, #0xaa\n"
+                                             "mov x17, #0xffffffffffffff45\n"
+                                             "csel x22, x16, x17, eq");
+  MacroAssembler::GetCselSynthesisInformation(x22, 0xaa, -0xbb,
+                                              &synthesises_left,
+                                              &synthesises_right);
+  VIXL_CHECK(synthesises_left && synthesises_right);
+
+  COMPARE_MACRO(Csel(w23,     0,  0xaa, eq), "mov w16, #0xaa\n"
+                                             "csel w23, w16, wzr, ne");
+  MacroAssembler::GetCselSynthesisInformation(w23, 0, 0xaa,
+                                              &synthesises_left,
+                                              &synthesises_right);
+  VIXL_CHECK(!synthesises_left && synthesises_right);
+
+  COMPARE_MACRO(Csel(x24, -0xaa,     0, eq), "mov x16, #0xffffffffffffff56\n"
+                                             "csel x24, x16, xzr, eq");
+  MacroAssembler::GetCselSynthesisInformation(x24, -0xaa, 0,
+                                              &synthesises_left,
+                                              &synthesises_right);
+  VIXL_CHECK(synthesises_left && !synthesises_right);
+
+  COMPARE_MACRO(Csel(w25,  0xcc, -0xcc, eq), "mov w25, #0xffffff34\n"
+                                             "cneg w25, w25, eq");
+  MacroAssembler::GetCselSynthesisInformation(w25, 0xcc, -0xcc,
+                                              &synthesises_left,
+                                              &synthesises_right);
+  VIXL_CHECK(!synthesises_left && synthesises_right);
+
+  COMPARE_MACRO(Csel(x26, -0xcc,  0xcc, eq), "mov x26, #0xcc\n"
+                                             "cneg x26, x26, eq");
+  MacroAssembler::GetCselSynthesisInformation(w25, -0xcc, 0xcc,
+                                              &synthesises_left,
+                                              &synthesises_right);
+  VIXL_CHECK(!synthesises_left && synthesises_right);
+
+  // Test with `Operand` inputs.
+  COMPARE_MACRO(Csel(x0, x1, Operand(x2, LSL, 3), eq), "lsl x16, x2, #3\n"
+                                                        "csel x0, x1, x16, eq");
+  MacroAssembler::GetCselSynthesisInformation(x0, x1,  Operand(x2, LSL, 3),
+                                              &synthesises_left,
+                                              &synthesises_right);
+  VIXL_CHECK(!synthesises_left && synthesises_right);
+
+  COMPARE_MACRO(Csel(x3, x4, Operand(x5, SXTH), eq), "sxth x16, w5\n"
+                                                     "csel x3, x4, x16, eq");
+  MacroAssembler::GetCselSynthesisInformation(x3, x4,  Operand(x5, SXTH),
+                                              &synthesises_left,
+                                              &synthesises_right);
+  VIXL_CHECK(!synthesises_left && synthesises_right);
+
+  COMPARE_MACRO(Csel(x6, Operand(x7, LSL, 7), x8, eq), "lsl x16, x7, #7\n"
+                                                       "csel x6, x16, x8, eq");
+  MacroAssembler::GetCselSynthesisInformation(x6, Operand(x7, LSL, 7), x8,
+                                              &synthesises_left,
+                                              &synthesises_right);
+  VIXL_CHECK(synthesises_left && !synthesises_right);
+
+  COMPARE_MACRO(Csel(x9, Operand(x10, SXTH), x11, eq), "sxth x16, w10\n"
+                                                       "csel x9, x16, x11, eq");
+  MacroAssembler::GetCselSynthesisInformation(x9, Operand(x10, SXTH), x11,
+                                              &synthesises_left,
+                                              &synthesises_right);
+  VIXL_CHECK(synthesises_left && !synthesises_right);
+
+  COMPARE_MACRO(Csel(x12, Operand(x13, LSL, 13), Operand(x14, SXTB), eq),
+                "lsl x16, x13, #13\n"
+                "sxtb x17, w14\n"
+                "csel x12, x16, x17, eq");
+  MacroAssembler::GetCselSynthesisInformation(x12,
+                                              Operand(x13, LSL, 13),
+                                              Operand(x14, SXTB),
+                                              &synthesises_left,
+                                              &synthesises_right);
+  VIXL_CHECK(synthesises_left && synthesises_right);
+
+  COMPARE_MACRO(Csel(x15, 0, Operand(x18, LSR, 18), eq),
+                "lsr x16, x18, #18\n"
+                "csel x15, x16, xzr, ne");
+  MacroAssembler::GetCselSynthesisInformation(x15, 0, Operand(x18, LSR, 18),
+                                              &synthesises_left,
+                                              &synthesises_right);
+  VIXL_CHECK(!synthesises_left && synthesises_right);
+
+  // Test with the zero register.
+  COMPARE_MACRO(Csel(w19, wzr, wzr, eq), "mov w19, #0x0");
+  MacroAssembler::GetCselSynthesisInformation(w19, wzr, wzr,
+                                              &synthesises_left,
+                                              &synthesises_right);
+  VIXL_CHECK(!synthesises_left && !synthesises_right);
+
+  COMPARE_MACRO(Csel(x20, x21, xzr, eq), "csel x20, x21, xzr, eq");
+  MacroAssembler::GetCselSynthesisInformation(x20, x21, xzr,
+                                              &synthesises_left,
+                                              &synthesises_right);
+  VIXL_CHECK(!synthesises_left && !synthesises_right);
+
+  COMPARE_MACRO(Csel(w22, wzr, w23, eq), "csel w22, w23, wzr, ne");
+  MacroAssembler::GetCselSynthesisInformation(w22, wzr, w23,
+                                              &synthesises_left,
+                                              &synthesises_right);
+  VIXL_CHECK(!synthesises_left && !synthesises_right);
+
+  COMPARE_MACRO(Csel(x24, xzr, 0, eq), "mov x24, #0x0");
+  MacroAssembler::GetCselSynthesisInformation(x24, xzr, 0,
+                                              &synthesises_left,
+                                              &synthesises_right);
+  VIXL_CHECK(!synthesises_left && !synthesises_right);
+
+  COMPARE_MACRO(Csel(w25, wzr, 1, eq), "cset w25, eq");
+  MacroAssembler::GetCselSynthesisInformation(w25, wzr, 1,
+                                              &synthesises_left,
+                                              &synthesises_right);
+  VIXL_CHECK(!synthesises_left && !synthesises_right);
+
 
   CLEANUP();
 }
@@ -2615,8 +2844,8 @@
   VIXL_ASSERT(kTraceOpcode == 0xdeb2);
 
   // All Trace calls should produce the same instruction.
-  COMPARE_MACRO(Trace(LOG_ALL, TRACE_ENABLE), "hlt #0xdeb2");
-  COMPARE_MACRO(Trace(LOG_REGS, TRACE_DISABLE), "hlt #0xdeb2");
+  COMPARE_MACRO_PREFIX(Trace(LOG_ALL, TRACE_ENABLE), "hlt #0xdeb2");
+  COMPARE_MACRO_PREFIX(Trace(LOG_REGS, TRACE_DISABLE), "hlt #0xdeb2");
 
   CLEANUP();
 }
@@ -2630,8 +2859,8 @@
   VIXL_ASSERT(kLogOpcode == 0xdeb3);
 
   // All Log calls should produce the same instruction.
-  COMPARE_MACRO(Log(LOG_ALL), "hlt #0xdeb3");
-  COMPARE_MACRO(Log(LOG_SYSREGS), "hlt #0xdeb3");
+  COMPARE_MACRO_PREFIX(Log(LOG_ALL), "hlt #0xdeb3");
+  COMPARE_MACRO_PREFIX(Log(LOG_SYSREGS), "hlt #0xdeb3");
 
   CLEANUP();
 }
@@ -3033,6 +3262,71 @@
 }
 
 
+TEST(neon_load_store_vector_unallocated) {
+  SETUP();
+
+  const char* expected = "unallocated (NEONLoadStoreMultiStruct)";
+  // LD[1-4] (multiple structures) (no offset)
+  COMPARE(dci(0x0c401000), expected);  // opcode = 0b0001
+  COMPARE(dci(0x0c403000), expected);  // opcode = 0b0011
+  COMPARE(dci(0x0c405000), expected);  // opcode = 0b0101
+  COMPARE(dci(0x0c409000), expected);  // opcode = 0b1001
+  COMPARE(dci(0x0c40b000), expected);  // opcode = 0b1011
+  COMPARE(dci(0x0c40c000), expected);  // opcode = 0b1100
+  COMPARE(dci(0x0c40d000), expected);  // opcode = 0b1101
+  COMPARE(dci(0x0c40e000), expected);  // opcode = 0b1110
+  COMPARE(dci(0x0c40f000), expected);  // opcode = 0b1111
+  COMPARE(dci(0x0c400c00), expected);  // opcode = 0b0000, size:Q = 0b110
+  COMPARE(dci(0x0c404c00), expected);  // opcode = 0b0100, size:Q = 0b110
+  COMPARE(dci(0x0c408c00), expected);  // opcode = 0b1000, size:Q = 0b110
+
+  // ST[1-4] (multiple structures) (no offset)
+  COMPARE(dci(0x0c001000), expected);  // opcode = 0b0001
+  COMPARE(dci(0x0c003000), expected);  // opcode = 0b0011
+  COMPARE(dci(0x0c005000), expected);  // opcode = 0b0101
+  COMPARE(dci(0x0c009000), expected);  // opcode = 0b1001
+  COMPARE(dci(0x0c00b000), expected);  // opcode = 0b1011
+  COMPARE(dci(0x0c00c000), expected);  // opcode = 0b1100
+  COMPARE(dci(0x0c00d000), expected);  // opcode = 0b1101
+  COMPARE(dci(0x0c00e000), expected);  // opcode = 0b1110
+  COMPARE(dci(0x0c00f000), expected);  // opcode = 0b1111
+  COMPARE(dci(0x0c000c00), expected);  // opcode = 0b0000, size:Q = 0b110
+  COMPARE(dci(0x0c004c00), expected);  // opcode = 0b0100, size:Q = 0b110
+  COMPARE(dci(0x0c008c00), expected);  // opcode = 0b1000, size:Q = 0b110
+
+  expected = "unallocated (NEONLoadStoreMultiStructPostIndex)";
+  // LD[1-4] (multiple structures) (post index)
+  COMPARE(dci(0x0cc01000), expected);  // opcode = 0b0001
+  COMPARE(dci(0x0cc03000), expected);  // opcode = 0b0011
+  COMPARE(dci(0x0cc05000), expected);  // opcode = 0b0101
+  COMPARE(dci(0x0cc09000), expected);  // opcode = 0b1001
+  COMPARE(dci(0x0cc0b000), expected);  // opcode = 0b1011
+  COMPARE(dci(0x0cc0c000), expected);  // opcode = 0b1100
+  COMPARE(dci(0x0cc0d000), expected);  // opcode = 0b1101
+  COMPARE(dci(0x0cc0e000), expected);  // opcode = 0b1110
+  COMPARE(dci(0x0cc0f000), expected);  // opcode = 0b1111
+  COMPARE(dci(0x0cc00c00), expected);  // opcode = 0b0000, size:Q = 0b110
+  COMPARE(dci(0x0cc04c00), expected);  // opcode = 0b0100, size:Q = 0b110
+  COMPARE(dci(0x0cc08c00), expected);  // opcode = 0b1000, size:Q = 0b110
+
+  // ST[1-4] (multiple structures) (post index)
+  COMPARE(dci(0x0c801000), expected);  // opcode = 0b0001
+  COMPARE(dci(0x0c803000), expected);  // opcode = 0b0011
+  COMPARE(dci(0x0c805000), expected);  // opcode = 0b0101
+  COMPARE(dci(0x0c809000), expected);  // opcode = 0b1001
+  COMPARE(dci(0x0c80b000), expected);  // opcode = 0b1011
+  COMPARE(dci(0x0c80c000), expected);  // opcode = 0b1100
+  COMPARE(dci(0x0c80d000), expected);  // opcode = 0b1101
+  COMPARE(dci(0x0c80e000), expected);  // opcode = 0b1110
+  COMPARE(dci(0x0c80f000), expected);  // opcode = 0b1111
+  COMPARE(dci(0x0c800c00), expected);  // opcode = 0b0000, size:Q = 0b110
+  COMPARE(dci(0x0c804c00), expected);  // opcode = 0b0100, size:Q = 0b110
+  COMPARE(dci(0x0c808c00), expected);  // opcode = 0b1000, size:Q = 0b110
+
+  CLEANUP();
+}
+
+
 TEST(neon_load_store_lane) {
   SETUP_MACRO();
 
@@ -3077,8 +3371,12 @@
           "ld1 {v11.s}[1], [x26], #4");
   COMPARE(Ld1(v12.S(), 3, MemOperand(x27, x5, PostIndex)),
           "ld1 {v12.s}[3], [x27], x5");
+  COMPARE(Ld1(v12.S(), 3, MemOperand(x27, 4, PostIndex)),
+          "ld1 {v12.s}[3], [x27], #4");
   COMPARE(Ld1(v13.D(), 1, MemOperand(sp, x6, PostIndex)),
           "ld1 {v13.d}[1], [sp], x6");
+  COMPARE(Ld1(v13.D(), 1, MemOperand(sp, 8, PostIndex)),
+          "ld1 {v13.d}[1], [sp], #8");
 
   COMPARE(Ld2(v0.V8B(),  v1.V8B(),  0, MemOperand(x15)),
       "ld2 {v0.b, v1.b}[0], [x15]");
@@ -3135,8 +3433,12 @@
       "ld2 {v11.s, v12.s}[1], [x26], #8");
   COMPARE(Ld2(v12.S(),  v13.S(),   3, MemOperand(x27, x5, PostIndex)),
       "ld2 {v12.s, v13.s}[3], [x27], x5");
+  COMPARE(Ld2(v11.S(),  v12.S(),   3, MemOperand(x26, 8, PostIndex)),
+      "ld2 {v11.s, v12.s}[3], [x26], #8");
   COMPARE(Ld2(v13.D(),  v14.D(),   1, MemOperand(sp, x6, PostIndex)),
       "ld2 {v13.d, v14.d}[1], [sp], x6");
+  COMPARE(Ld2(v13.D(),  v14.D(),   1, MemOperand(sp, 16, PostIndex)),
+      "ld2 {v13.d, v14.d}[1], [sp], #16");
 
   COMPARE(Ld3(v0.V8B(),  v1.V8B(),  v2.V8B(),   0, MemOperand(x15)),
       "ld3 {v0.b, v1.b, v2.b}[0], [x15]");
@@ -3206,9 +3508,15 @@
   COMPARE(Ld3(v12.S(),   v13.S(),   v14.S(),   3,
               MemOperand(x27, x5, PostIndex)),
       "ld3 {v12.s, v13.s, v14.s}[3], [x27], x5");
+  COMPARE(Ld3(v12.S(),   v13.S(),   v14.S(),   3,
+              MemOperand(x27, 12, PostIndex)),
+      "ld3 {v12.s, v13.s, v14.s}[3], [x27], #12");
   COMPARE(Ld3(v13.D(),   v14.D(),   v15.D(),   1,
               MemOperand(sp, x6, PostIndex)),
       "ld3 {v13.d, v14.d, v15.d}[1], [sp], x6");
+  COMPARE(Ld3(v13.D(),   v14.D(),   v15.D(),   1,
+              MemOperand(sp, 24, PostIndex)),
+      "ld3 {v13.d, v14.d, v15.d}[1], [sp], #24");
 
   COMPARE(Ld4(v0.V8B(),   v1.V8B(),  v2.V8B(),   v3.V8B(),  0,
               MemOperand(x15)),
@@ -3292,9 +3600,15 @@
   COMPARE(Ld4(v12.S(),   v13.S(),   v14.S(),   v15.S(),    3,
               MemOperand(x27, x5, PostIndex)),
       "ld4 {v12.s, v13.s, v14.s, v15.s}[3], [x27], x5");
+  COMPARE(Ld4(v11.S(),   v12.S(),   v13.S(),   v14.S(),    3,
+              MemOperand(x26, 16, PostIndex)),
+      "ld4 {v11.s, v12.s, v13.s, v14.s}[3], [x26], #16");
   COMPARE(Ld4(v13.D(),   v14.D(),   v15.D(),   v16.D(),    1,
               MemOperand(sp, x6, PostIndex)),
       "ld4 {v13.d, v14.d, v15.d, v16.d}[1], [sp], x6");
+  COMPARE(Ld4(v13.D(),   v14.D(),   v15.D(),   v16.D(),    1,
+              MemOperand(sp, 32, PostIndex)),
+      "ld4 {v13.d, v14.d, v15.d, v16.d}[1], [sp], #32");
 
   COMPARE(St1(v0.V8B(), 0, MemOperand(x15)), "st1 {v0.b}[0], [x15]");
   COMPARE(St1(v1.V16B(), 1, MemOperand(x16)), "st1 {v1.b}[1], [x16]");
@@ -3429,6 +3743,81 @@
 }
 
 
+TEST(neon_load_store_lane_unallocated) {
+  SETUP();
+
+  const char* expected = "unallocated (NEONLoadStoreSingleStruct)";
+  // LD1 (single structure) (no offset)
+  COMPARE(dci(0x0d404400), expected);  // .h, size<0> = 1
+  COMPARE(dci(0x0d408800), expected);  // .s, size<1> = 1
+  COMPARE(dci(0x0d409400), expected);  // .d, size<0> = 1, S = 1
+  // LD2 (single structure) (no offset)
+  COMPARE(dci(0x0d604400), expected);  // .h, size<0> = 1
+  COMPARE(dci(0x0d608800), expected);  // .s, size<1> = 1
+  COMPARE(dci(0x0d609400), expected);  // .d, size<0> = 1, S = 1
+  // LD3 (single structure) (no offset)
+  COMPARE(dci(0x0d406400), expected);  // .h, size<0> = 1
+  COMPARE(dci(0x0d40a800), expected);  // .s, size<1> = 1
+  COMPARE(dci(0x0d40b400), expected);  // .d, size<0> = 1, S = 1
+  // LD4 (single structure) (no offset)
+  COMPARE(dci(0x0d606400), expected);  // .h, size<0> = 1
+  COMPARE(dci(0x0d60a800), expected);  // .s, size<1> = 1
+  COMPARE(dci(0x0d60b400), expected);  // .d, size<0> = 1, S = 1
+  // ST1 (single structure) (no offset)
+  COMPARE(dci(0x0d004400), expected);  // .h, size<0> = 1
+  COMPARE(dci(0x0d008800), expected);  // .s, size<1> = 1
+  COMPARE(dci(0x0d009400), expected);  // .d, size<0> = 1, S = 1
+  // ST2 (single structure) (no offset)
+  COMPARE(dci(0x0d204400), expected);  // .h, size<0> = 1
+  COMPARE(dci(0x0d208800), expected);  // .s, size<1> = 1
+  COMPARE(dci(0x0d209400), expected);  // .d, size<0> = 1, S = 1
+  // ST3 (single structure) (no offset)
+  COMPARE(dci(0x0d006400), expected);  // .h, size<0> = 1
+  COMPARE(dci(0x0d00a800), expected);  // .s, size<1> = 1
+  COMPARE(dci(0x0d00b400), expected);  // .d, size<0> = 1, S = 1
+  // ST4 (single structure) (no offset)
+  COMPARE(dci(0x0d206400), expected);  // .h, size<0> = 1
+  COMPARE(dci(0x0d20a800), expected);  // .s, size<1> = 1
+  COMPARE(dci(0x0d20b400), expected);  // .d, size<0> = 1, S = 1
+
+  expected = "unallocated (NEONLoadStoreSingleStructPostIndex)";
+  // LD1 (single structure) (post index)
+  COMPARE(dci(0x0dc04400), expected);  // .h, size<0> = 1
+  COMPARE(dci(0x0dc08800), expected);  // .s, size<1> = 1
+  COMPARE(dci(0x0dc09400), expected);  // .d, size<0> = 1, S = 1
+  // LD2 (single structure) (post index)
+  COMPARE(dci(0x0de04400), expected);  // .h, size<0> = 1
+  COMPARE(dci(0x0de08800), expected);  // .s, size<1> = 1
+  COMPARE(dci(0x0de09400), expected);  // .d, size<0> = 1, S = 1
+  // LD3 (single structure) (post index)
+  COMPARE(dci(0x0dc06400), expected);  // .h, size<0> = 1
+  COMPARE(dci(0x0dc0a800), expected);  // .s, size<1> = 1
+  COMPARE(dci(0x0dc0b400), expected);  // .d, size<0> = 1, S = 1
+  // LD4 (single structure) (post index)
+  COMPARE(dci(0x0de06400), expected);  // .h, size<0> = 1
+  COMPARE(dci(0x0de0a800), expected);  // .s, size<1> = 1
+  COMPARE(dci(0x0de0b400), expected);  // .d, size<0> = 1, S = 1
+  // ST1 (single structure) (post index)
+  COMPARE(dci(0x0d804400), expected);  // .h, size<0> = 1
+  COMPARE(dci(0x0d808800), expected);  // .s, size<1> = 1
+  COMPARE(dci(0x0d809400), expected);  // .d, size<0> = 1, S = 1
+  // ST2 (single structure) (post index)
+  COMPARE(dci(0x0da04400), expected);  // .h, size<0> = 1
+  COMPARE(dci(0x0da08800), expected);  // .s, size<1> = 1
+  COMPARE(dci(0x0da09400), expected);  // .d, size<0> = 1, S = 1
+  // ST3 (single structure) (post index)
+  COMPARE(dci(0x0d806400), expected);  // .h, size<0> = 1
+  COMPARE(dci(0x0d80a800), expected);  // .s, size<1> = 1
+  COMPARE(dci(0x0d80b400), expected);  // .d, size<0> = 1, S = 1
+  // ST4 (single structure) (post index)
+  COMPARE(dci(0x0da06400), expected);  // .h, size<0> = 1
+  COMPARE(dci(0x0da0a800), expected);  // .s, size<1> = 1
+  COMPARE(dci(0x0da0b400), expected);  // .d, size<0> = 1, S = 1
+
+  CLEANUP();
+}
+
+
 TEST(neon_load_all_lanes) {
   SETUP_MACRO();
 
@@ -3577,6 +3966,41 @@
 }
 
 
+TEST(neon_load_all_lanes_unallocated) {
+  SETUP();
+
+  const char* expected = "unallocated (NEONLoadStoreSingleStruct)";
+  // LD1R (single structure) (no offset)
+  COMPARE(dci(0x0d00c000), expected);  // L = 0
+  COMPARE(dci(0x0d40d000), expected);  // S = 1
+  // LD2R (single structure) (no offset)
+  COMPARE(dci(0x0d20c000), expected);  // L = 0
+  COMPARE(dci(0x0d60d000), expected);  // S = 1
+  // LD3R (single structure) (no offset)
+  COMPARE(dci(0x0d00e000), expected);  // L = 0
+  COMPARE(dci(0x0d40f000), expected);  // S = 1
+  // LD4R (single structure) (no offset)
+  COMPARE(dci(0x0d20e000), expected);  // L = 0
+  COMPARE(dci(0x0d60f000), expected);  // S = 1
+
+  expected = "unallocated (NEONLoadStoreSingleStructPostIndex)";
+  // LD1R (single structure) (post index)
+  COMPARE(dci(0x0d80c000), expected);  // L = 0
+  COMPARE(dci(0x0dc0d000), expected);  // S = 1
+  // LD2R (single structure) (post index)
+  COMPARE(dci(0x0da0c000), expected);  // L = 0
+  COMPARE(dci(0x0de0d000), expected);  // S = 1
+  // LD3R (single structure) (post index)
+  COMPARE(dci(0x0d80e000), expected);  // L = 0
+  COMPARE(dci(0x0dc0f000), expected);  // S = 1
+  // LD4R (single structure) (post index)
+  COMPARE(dci(0x0da0e000), expected);  // L = 0
+  COMPARE(dci(0x0de0f000), expected);  // S = 1
+
+  CLEANUP();
+}
+
+
 TEST(neon_3same) {
   SETUP_MACRO();
 
@@ -4697,6 +5121,9 @@
   COMPARE(Fmov(v1.V2D(), 1.0), "fmov v1.2d, #0x70 (1.0000)");
   COMPARE(Fmov(v29.V2D(), -13.0), "fmov v29.2d, #0xaa (-13.0000)");
 
+  // An unallocated form of fmov.
+  COMPARE(dci(0x2f07ffff), "unallocated (NEONModifiedImmediate)");
+
   CLEANUP();
 }
 
@@ -4711,6 +5138,11 @@
   COMPARE(Shll2(v4.V4S(), v2.V8H(),  16), "shll2 v4.4s, v2.8h, #16");
   COMPARE(Shll2(v6.V2D(), v4.V4S(),  32), "shll2 v6.2d, v4.4s, #32");
 
+  // An unallocated form of shll.
+  COMPARE(dci(0x2ee13bff), "unallocated (NEON2RegMisc)");
+  // An unallocated form of shll2.
+  COMPARE(dci(0x6ee13bff), "unallocated (NEON2RegMisc)");
+
   #define DISASM_INST(M, S)  \
   COMPARE(Cmeq(v0.M, v1.M, 0), "cmeq v0." S ", v1." S ", #0");
   NEON_FORMAT_LIST(DISASM_INST)
diff --git a/test/test-invalset.cc b/test/test-invalset.cc
index 2fb2b34..ded0cb5 100644
--- a/test/test-invalset.cc
+++ b/test/test-invalset.cc
@@ -80,7 +80,7 @@
                         KeyType,
                         kInvalidKey,
                         kReclaimFrom,
-                        kReclaimFactor>::Key(const Obj& obj) {
+                        kReclaimFactor>::GetKey(const Obj& obj) {
   return obj.key_;
 }
 template<>
@@ -106,10 +106,10 @@
   set.insert(Obj(-123, 456));
   set.insert(Obj(2718, 2871828));
   VIXL_CHECK(set.size() == kNPreallocatedElements + 2);
-  VIXL_CHECK(set.min_element() == Obj(-123, 456));
+  VIXL_CHECK(set.GetMinElement() == Obj(-123, 456));
 
   set.erase(Obj(-123, 456));
-  VIXL_CHECK(set.min_element_key() == 0);
+  VIXL_CHECK(set.GetMinElementKey() == 0);
 
   set.clear();
   VIXL_CHECK(set.empty() && (set.size() == 0));
@@ -168,7 +168,7 @@
   set.erase(Obj(100, -1));
   VIXL_CHECK(set.size() == max_size - 1);
   for (size_t i = 2; i <= max_size; i++) {
-    set.erase(set.min_element());
+    set.erase(set.GetMinElement());
     VIXL_CHECK(set.size() == max_size - i);
   }
 
@@ -186,9 +186,9 @@
   set.insert(Obj(-1, 0));
   set.insert(Obj(0, 0));
   set.insert(Obj(1, 0));
-  VIXL_CHECK(set.min_element() == Obj(-1, -1));
-  VIXL_CHECK(set.min_element_key() == -1);
-  VIXL_CHECK(set.min_element().key_ == set.min_element_key());
+  VIXL_CHECK(set.GetMinElement() == Obj(-1, -1));
+  VIXL_CHECK(set.GetMinElementKey() == -1);
+  VIXL_CHECK(set.GetMinElement().key_ == set.GetMinElementKey());
 
   // Test with more elements.
   set.clear();
@@ -198,13 +198,13 @@
     int sign = ((i % 2) == 0) ? -1 : 1;
     set.insert(Obj(sign * i, i));
   }
-  VIXL_CHECK(set.min_element() == Obj(-max_index, max_index));
-  VIXL_CHECK(set.min_element().key_ == set.min_element_key());
+  VIXL_CHECK(set.GetMinElement() == Obj(-max_index, max_index));
+  VIXL_CHECK(set.GetMinElement().key_ == set.GetMinElementKey());
 
   set.erase(Obj(0, 0));
-  VIXL_CHECK(set.min_element() == Obj(-max_index, max_index));
-  set.erase(set.min_element());
-  VIXL_CHECK(set.min_element() == Obj(-(max_index - 2), max_index - 2));
+  VIXL_CHECK(set.GetMinElement() == Obj(-max_index, max_index));
+  set.erase(set.GetMinElement());
+  VIXL_CHECK(set.GetMinElement() == Obj(-(max_index - 2), max_index - 2));
 
   set.clear();
   VIXL_CHECK(set.empty() && (set.size() == 0));
@@ -215,37 +215,191 @@
   TestSet set;
   VIXL_CHECK(set.empty() && (set.size() == 0));
 
+  // Ensure that set.begin() == set.end() for the empty set.
+  VIXL_CHECK(set.begin() == set.end());
+
   // Test with only preallocated elements in the set.
+  size_t expected_total = 0;
   for (unsigned i = 0; i < kNPreallocatedElements; i++) {
     set.insert(Obj(i, i));
+    expected_total += i;
   }
 
   size_t size = 0;
-  for (InvalSetIterator<TestSet> it(&set); !it.Done(); it.Advance()) {
+  size_t total = 0;
+  for (InvalSetIterator<TestSet> it = set.begin(); it != set.end(); ++it) {
+    total += it->val_;
     size++;
   }
   VIXL_CHECK(size == set.size());
+  VIXL_CHECK(total == expected_total);
 
   // Test with more elements.
   for (unsigned i = kNPreallocatedElements;
        i < 4 * kNPreallocatedElements;
        i++) {
     set.insert(Obj(i, i));
+    expected_total += i;
   }
 
   size = 0;
-  for (InvalSetIterator<TestSet> it(&set); !it.Done(); it.Advance()) {
+  total = 0;
+  for (InvalSetIterator<TestSet> it = set.begin(); it != set.end(); ++it) {
+    total += it->val_;
     size++;
   }
   VIXL_CHECK(size == set.size());
+  VIXL_CHECK(total == expected_total);
 
-  // Test after an element has been deleted.
-  size = 0;
-  set.erase(Obj(0, 0));
-  for (InvalSetIterator<TestSet> it(&set); !it.Done(); it.Advance()) {
-    size++;
+  // Test after elements have been deleted.
+  // - Select an interesting list of elements to erase.
+  std::vector<Obj> to_erase;
+  unsigned step = 0;
+  for (unsigned i = 0; i < set.size(); i += step, step++) {
+    to_erase.push_back(Obj(i, i));
   }
-  VIXL_CHECK(size == set.size());
+  to_erase.push_back(Obj(set.size() - 1, set.size() - 1));  // The last element.
+  to_erase.push_back(Obj(set.size(), set.size()));          // Not in the set.
+
+  // - Erase one at a time, retesting after each one.
+  while (!to_erase.empty()) {
+    size_t erased = set.erase(to_erase.back());
+    if (erased > 0) {
+      VIXL_CHECK(erased == 1);
+      expected_total -= to_erase.back().val_;
+    } else {
+    }
+    to_erase.pop_back();
+
+    size = 0;
+    total = 0;
+    for (InvalSetIterator<TestSet> it = set.begin(); it != set.end(); ++it) {
+      total += it->val_;
+      size++;
+    }
+    VIXL_CHECK(size == set.size());
+    VIXL_CHECK(total == expected_total);
+  }
 }
 
+
+#if __cplusplus >= 201103L
+TEST(iterator_cxx11) {
+  TestSet set;
+  VIXL_CHECK(set.empty() && (set.size() == 0));
+
+  // Test with only preallocated elements in the set.
+  size_t expected_total = 0;
+  for (unsigned i = 0; i < kNPreallocatedElements; i++) {
+    set.insert(Obj(i, i));
+    expected_total += i;
+  }
+
+  size_t size = 0;
+  size_t total = 0;
+  for (auto object : set) {
+    total += object.val_;
+    size++;
+  }
+  VIXL_CHECK(size == set.size());
+  VIXL_CHECK(total == expected_total);
+
+  // Test with more elements.
+  for (unsigned i = kNPreallocatedElements;
+       i < 4 * kNPreallocatedElements;
+       i++) {
+    set.insert(Obj(i, i));
+    expected_total += i;
+  }
+
+  size = 0;
+  total = 0;
+  for (auto object : set) {
+    total += object.val_;
+    size++;
+  }
+  VIXL_CHECK(size == set.size());
+  VIXL_CHECK(total == expected_total);
+
+  // Test after elements have been deleted.
+  // - Select an interesting list of elements to erase.
+  std::vector<Obj> to_erase;
+  unsigned step = 0;
+  for (unsigned i = 0; i < set.size(); i += step, step++) {
+    to_erase.push_back(Obj(i, i));
+  }
+  to_erase.push_back(Obj(set.size() - 1, set.size() - 1));  // The last element.
+  to_erase.push_back(Obj(set.size(), set.size()));          // Not in the set.
+
+  // - Erase one at a time, retesting after each one.
+  while (!to_erase.empty()) {
+    size_t erased = set.erase(to_erase.back());
+    if (erased > 0) {
+      VIXL_CHECK(erased == 1);
+      expected_total -= to_erase.back().val_;
+    } else {
+    }
+    to_erase.pop_back();
+
+    size = 0;
+    total = 0;
+    for (auto object : set) {
+      total += object.val_;
+      size++;
+    }
+    VIXL_CHECK(size == set.size());
+    VIXL_CHECK(total == expected_total);
+  }
+}
+#endif
+
+
+TEST(stl_forward_iterator) {
+  {
+    TestSet::iterator default_it;               // Default-constructible.
+    TestSet::iterator copy_it(default_it);      // Copy-constructible.
+    copy_it = default_it;                       // Copy-assignable.
+  }                                             // Destructible.
+
+  TestSet set1;
+  VIXL_CHECK(set1.empty() && (set1.size() == 0));
+
+  TestSet set2;
+  VIXL_CHECK(set2.empty() && (set2.size() == 0));
+
+  // Test with only preallocated elements in the set.
+  for (unsigned i = 0; i < kNPreallocatedElements; i++) {
+    set1.insert(Obj(i, 1));
+    set2.insert(Obj(i, 2));
+  }
+
+  TestSet::iterator it1_a = set1.begin();
+  TestSet::iterator it1_b = set1.begin();
+
+  // Incrementable (whilst valid).
+  it1_a++;
+  ++it1_b;
+
+  // Testable for equivalence.
+  VIXL_CHECK(it1_a == it1_b);
+  VIXL_CHECK(set1.begin() != set1.end());
+  VIXL_CHECK(set2.begin() != set2.end());
+  VIXL_CHECK(set1.begin() != set2.begin());
+  VIXL_CHECK(set1.end() != set2.end());
+
+  // Dereferencable.
+  VIXL_CHECK((*it1_a++).key_ == 1);
+  VIXL_CHECK(((*it1_a).key_ == 2) && ((*it1_a).val_ == 1));
+  *it1_b = Obj(42, 1);
+  VIXL_CHECK((it1_b->key_ == 42) && (it1_b->val_ == 1));
+
+#if __cplusplus >= 201103L
+  // Swappable.
+  std::swap(it1_a, it1_b);
+  VIXL_CHECK(it1_a->key_ == 42);
+  VIXL_CHECK(it1_b->key_ == 2);
+#endif
+}
+
+
 }  // namespace vixl
diff --git a/test/test-runner.cc b/test/test-runner.cc
index 7c3c53d..b312005 100644
--- a/test/test-runner.cc
+++ b/test/test-runner.cc
@@ -47,8 +47,8 @@
 // No instruction statistics by default.
 bool vixl::Test::instruction_stats_ = false;
 
-// Don't generate simulator test traces by default.
-bool vixl::Test::sim_test_trace_ = false;
+// Don't generate traces by default.
+bool vixl::Test::generate_test_trace_ = false;
 
 // Instantiate a Test and append it to the linked list.
 vixl::Test::Test(const char* name, TestFunction* callback)
@@ -96,18 +96,20 @@
 static void PrintHelpMessage() {
   printf("Usage:  ./test [options] [test names]\n"
       "Run all tests specified on the command line.\n"
-      "--help              Print this help message.\n"
-      "--list              List all available tests.\n"
-      "--run_all           Run all available tests.\n"
-      "--debugger          Run in the debugger.\n"
-      "--trace_all         Enable all trace options, plus --coloured_trace.\n"
-      "--trace_sim         Generate a trace of simulated instructions, as\n"
-      "                    well as disassembly from the DISASM tests.\n"
-      "--trace_reg         Generate a trace of simulated registers.\n"
-      "--trace_write       Generate a trace of memory writes.\n"
-      "--coloured_trace    Generate coloured trace.\n"
-      "--instruction_stats Log instruction statistics to vixl_stats.csv.\n"
-      "--sim_test_trace    Print result traces for SIM_* tests.\n");
+      "--help                 Print this help message.\n"
+      "--list                 List all available tests.\n"
+      "--run_all              Run all available tests.\n"
+      "--debugger             Run in the debugger.\n"
+      "--trace_all            "
+      "Enable all trace options, plus --coloured_trace.\n"
+      "--trace_sim            Generate a trace of simulated instructions, as\n"
+      "                       well as disassembly from the DISASM tests.\n"
+      "--trace_reg            Generate a trace of simulated registers.\n"
+      "--trace_write          Generate a trace of memory writes.\n"
+      "--coloured_trace       Generate coloured trace.\n"
+      "--instruction_stats    Log instruction statistics to vixl_stats.csv.\n"
+      "--generate_test_trace  "
+      "Print result traces for SIM_* and TRACE_* tests.\n");
 }
 
 int main(int argc, char* argv[]) {
@@ -157,8 +159,8 @@
     vixl::Test::set_instruction_stats(true);
   }
 
-  if (IsInArgs("--sim-test-trace", argc, argv)) {
-    vixl::Test::set_sim_test_trace(true);
+  if (IsInArgs("--generate-test-trace", argc, argv)) {
+    vixl::Test::set_generate_test_trace(true);
   }
 
   // Basic (mutually-exclusive) operations.
diff --git a/test/test-runner.h b/test/test-runner.h
index 3acf053..99d871a 100644
--- a/test/test-runner.h
+++ b/test/test-runner.h
@@ -56,8 +56,10 @@
   static void set_coloured_trace(bool value) { coloured_trace_ = value; }
   static bool instruction_stats() { return instruction_stats_; }
   static void set_instruction_stats(bool value) { instruction_stats_ = value; }
-  static bool sim_test_trace() { return sim_test_trace_; }
-  static void set_sim_test_trace(bool value) { sim_test_trace_ = value; }
+  static bool generate_test_trace() { return generate_test_trace_; }
+  static void set_generate_test_trace(bool value) {
+    generate_test_trace_ = value;
+  }
 
   // The debugger is needed to trace register values.
   static bool run_debugger() { return debug_; }
@@ -75,7 +77,7 @@
   static bool trace_write_;
   static bool coloured_trace_;
   static bool instruction_stats_;
-  static bool sim_test_trace_;
+  static bool generate_test_trace_;
 };
 
 // Define helper macros for test files.
diff --git a/test/test-simulator-a64.cc b/test/test-simulator-a64.cc
index e67177b..68f6220 100644
--- a/test/test-simulator-a64.cc
+++ b/test/test-simulator-a64.cc
@@ -40,11 +40,12 @@
 //
 // These simulator tests check instruction behaviour against a trace taken from
 // real AArch64 hardware. The same test code is used to generate the trace; the
-// results are printed to stdout when the test is run with --sim_test_trace.
+// results are printed to stdout when the test is run with
+// --generate_test_trace.
 //
 // The input lists and expected results are stored in test/traces. The expected
-// results can be regenerated using tools/generate_simulator_traces.py. Adding
-// a test for a new instruction is described at the top of
+// results can be regenerated using tools/generate_simulator_traces.py. Adding a
+// test for a new instruction is described at the top of
 // test-simulator-traces-a64.h.
 
 #define __ masm.
@@ -261,7 +262,7 @@
   Test1Op_Helper(helper, reinterpret_cast<uintptr_t>(inputs), inputs_length,
                  reinterpret_cast<uintptr_t>(results), d_bits, n_bits);
 
-  if (Test::sim_test_trace()) {
+  if (Test::generate_test_trace()) {
     // Print the results.
     printf("const uint%u_t kExpected_%s[] = {\n", d_bits, name);
     for (unsigned d = 0; d < results_length; d++) {
@@ -375,7 +376,7 @@
   Test2Op_Helper(helper, reinterpret_cast<uintptr_t>(inputs), inputs_length,
                  reinterpret_cast<uintptr_t>(results), bits);
 
-  if (Test::sim_test_trace()) {
+  if (Test::generate_test_trace()) {
     // Print the results.
     printf("const uint%u_t kExpected_%s[] = {\n", bits, name);
     for (unsigned d = 0; d < results_length; d++) {
@@ -505,7 +506,7 @@
   Test3Op_Helper(helper, reinterpret_cast<uintptr_t>(inputs), inputs_length,
                  reinterpret_cast<uintptr_t>(results), bits);
 
-  if (Test::sim_test_trace()) {
+  if (Test::generate_test_trace()) {
     // Print the results.
     printf("const uint%u_t kExpected_%s[] = {\n", bits, name);
     for (unsigned d = 0; d < results_length; d++) {
@@ -632,7 +633,7 @@
   TestCmp_Helper(helper, reinterpret_cast<uintptr_t>(inputs), inputs_length,
                  reinterpret_cast<uintptr_t>(results), bits);
 
-  if (Test::sim_test_trace()) {
+  if (Test::generate_test_trace()) {
     // Print the results.
     printf("const uint8_t kExpected_%s[] = {\n", name);
     for (unsigned d = 0; d < results_length; d++) {
@@ -751,7 +752,7 @@
   TestCmpZero_Helper(helper, reinterpret_cast<uintptr_t>(inputs), inputs_length,
                      reinterpret_cast<uintptr_t>(results), bits);
 
-  if (Test::sim_test_trace()) {
+  if (Test::generate_test_trace()) {
     // Print the results.
     printf("const uint8_t kExpected_%s[] = {\n", name);
     for (unsigned d = 0; d < results_length; d++) {
@@ -918,7 +919,7 @@
   TestFPToInt_Helper(helper, reinterpret_cast<uintptr_t>(inputs), inputs_length,
                      reinterpret_cast<uintptr_t>(results), d_bits, n_bits);
 
-  if (Test::sim_test_trace()) {
+  if (Test::generate_test_trace()) {
     // Print the results.
     printf("const int%u_t kExpected_%s[] = {\n", d_bits, name);
     // There is no simple C++ literal for INT*_MIN that doesn't produce
@@ -996,7 +997,7 @@
                      reinterpret_cast<uintptr_t>(inputs), inputs_length,
                      reinterpret_cast<uintptr_t>(results), d_bits, n_bits);
 
-  if (Test::sim_test_trace()) {
+  if (Test::generate_test_trace()) {
     // Print the results.
     printf("const uint%u_t kExpected_%s[] = {\n", d_bits, name);
     for (unsigned d = 0; d < results_length; d++) {
@@ -1056,7 +1057,7 @@
                        reinterpret_cast<uintptr_t>(inputs), inputs_length,
                        reinterpret_cast<uintptr_t>(results), d_bits, n_bits);
 
-  if (Test::sim_test_trace()) {
+  if (Test::generate_test_trace()) {
     // Print the results.
     printf("const int%u_t kExpected_%s[] = {\n", d_bits, name);
     // There is no simple C++ literal for INT*_MIN that doesn't produce
@@ -1136,7 +1137,7 @@
                        reinterpret_cast<uintptr_t>(inputs), inputs_length,
                        reinterpret_cast<uintptr_t>(results), d_bits, n_bits);
 
-  if (Test::sim_test_trace()) {
+  if (Test::generate_test_trace()) {
     // Print the results.
     printf("const uint%u_t kExpected_%s[] = {\n", d_bits, name);
     for (unsigned d = 0; d < results_length; d++) {
@@ -1286,7 +1287,7 @@
                      reinterpret_cast<uintptr_t>(results),
                      vd_form, vn_form);
 
-  if (Test::sim_test_trace()) {
+  if (Test::generate_test_trace()) {
     // Print the results.
     printf("const uint%u_t kExpected_NEON_%s[] = {\n", lane_bit, name);
     for (unsigned iteration = 0; iteration < results_length; iteration++) {
@@ -1477,7 +1478,7 @@
                            reinterpret_cast<uintptr_t>(results),
                            vd_form, vn_form);
 
-  if (Test::sim_test_trace()) {
+  if (Test::generate_test_trace()) {
     // Print the results.
     printf("const uint%u_t kExpected_NEON_%s[] = {\n", lane_bit, name);
     for (unsigned iteration = 0; iteration < results_length; iteration++) {
@@ -1708,7 +1709,7 @@
                      reinterpret_cast<uintptr_t>(results),
                      vd_form, vn_form, vm_form);
 
-  if (Test::sim_test_trace()) {
+  if (Test::generate_test_trace()) {
     // Print the results.
     printf("const uint%u_t kExpected_NEON_%s[] = {\n", lane_bit, name);
     for (unsigned iteration = 0; iteration < results_length; iteration++) {
@@ -1945,7 +1946,7 @@
     reinterpret_cast<uintptr_t>(results),
     vd_form, vn_form, vm_form);
 
-  if (Test::sim_test_trace()) {
+  if (Test::generate_test_trace()) {
     // Print the results.
     printf("const uint%u_t kExpected_NEON_%s[] = {\n", lane_bit, name);
     for (unsigned iteration = 0; iteration < results_length; iteration++) {
@@ -2155,7 +2156,7 @@
                         reinterpret_cast<uintptr_t>(results),
                         vd_form, vn_form);
 
-  if (Test::sim_test_trace()) {
+  if (Test::generate_test_trace()) {
     // Print the results.
     printf("const uint%u_t kExpected_NEON_%s[] = {\n", lane_bit, name);
     for (unsigned iteration = 0; iteration < results_length; iteration++) {
@@ -2374,7 +2375,7 @@
                             reinterpret_cast<uintptr_t>(results),
                             vd_form, vn_form);
 
-  if (Test::sim_test_trace()) {
+  if (Test::generate_test_trace()) {
     // Print the results.
     printf("const uint%u_t kExpected_NEON_%s[] = {\n", lane_bit, name);
     for (unsigned iteration = 0; iteration < results_length; iteration++) {
diff --git a/test/test-trace-a64.cc b/test/test-trace-a64.cc
new file mode 100644
index 0000000..aeb8f3d
--- /dev/null
+++ b/test/test-trace-a64.cc
@@ -0,0 +1,2701 @@
+// Copyright 2016, ARM Limited
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+//   * Redistributions of source code must retain the above copyright notice,
+//     this list of conditions and the following disclaimer.
+//   * Redistributions in binary form must reproduce the above copyright notice,
+//     this list of conditions and the following disclaimer in the documentation
+//     and/or other materials provided with the distribution.
+//   * Neither the name of ARM Limited nor the names of its contributors may be
+//     used to endorse or promote products derived from this software without
+//     specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
+// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <float.h>
+#include <cmath>
+
+#include "test-runner.h"
+#include "test-utils-a64.h"
+#include "vixl/a64/macro-assembler-a64.h"
+#include "vixl/a64/simulator-a64.h"
+#include "vixl/a64/debugger-a64.h"
+#include "vixl/a64/disasm-a64.h"
+#include "vixl/a64/cpu-a64.h"
+
+namespace vixl {
+// Trace tests can only work with the simulator.
+#ifdef VIXL_INCLUDE_SIMULATOR
+
+#define __ masm->
+#define TEST(name) TEST_(TRACE_##name)
+
+static void GenerateTestSequenceBase(MacroAssembler* masm) {
+  CodeBufferCheckScope guard(masm, masm->RemainingBufferSpace());
+
+  __ adc(w3, w4, w5);
+  __ adc(x6, x7, x8);
+  __ adcs(w9, w10, w11);
+  __ adcs(x12, x13, x14);
+  __ add(w15, w16, w17);
+  __ add(x18, x19, x20);
+  __ adds(w21, w22, w23);
+  __ adds(x24, x25, x26);
+  __ and_(w27, w28, w29);
+  __ and_(x2, x3, x4);
+  __ ands(w5, w6, w7);
+  __ ands(x8, x9, x10);
+  __ asr(w11, w12, 0);
+  __ asr(x13, x14, 1);
+  __ asrv(w15, w16, w17);
+  __ asrv(x18, x19, x20);
+  __ bfm(w21, w22, 5, 6);
+  __ bfm(x23, x24, 7, 8);
+  __ bic(w25, w26, w27);
+  __ bic(x28, x29, x2);
+  __ bics(w3, w4, w5);
+  __ bics(x6, x7, x8);
+  __ ccmn(w9, w10, NoFlag, al);
+  __ ccmn(w9, w10, NoFlag, eq);
+  __ ccmn(w9, w10, NoFlag, ne);
+  __ ccmn(x11, x12, CFlag, al);
+  __ ccmn(x11, x12, CFlag, cc);
+  __ ccmn(x11, x12, CFlag, cs);
+  __ ccmp(w13, w14, VFlag, al);
+  __ ccmp(w13, w14, VFlag, hi);
+  __ ccmp(w13, w14, VFlag, ls);
+  __ ccmp(x15, x16, CVFlag, al);
+  __ ccmp(x15, x16, CVFlag, eq);
+  __ ccmp(x15, x16, CVFlag, ne);
+  __ cinc(w17, w18, cc);
+  __ cinc(w17, w18, cs);
+  __ cinc(x19, x20, hi);
+  __ cinc(x19, x20, ls);
+  __ cinv(w21, w22, eq);
+  __ cinv(w21, w22, ne);
+  __ cinv(x23, x24, cc);
+  __ cinv(x23, x24, cs);
+  __ clrex();
+  __ cls(w25, w26);
+  __ cls(x27, x28);
+  __ clz(w29, w2);
+  __ clz(x3, x4);
+  __ cmn(w5, w6);
+  __ cmn(x7, x8);
+  __ cmp(w9, w10);
+  __ cmp(x11, x12);
+  __ cneg(w13, w14, hi);
+  __ cneg(w13, w14, ls);
+  __ cneg(x15, x16, eq);
+  __ cneg(x15, x16, ne);
+  __ crc32b(w17, w18, w19);
+  __ crc32cb(w20, w21, w22);
+  __ crc32ch(w23, w24, w25);
+  __ crc32cw(w26, w27, w28);
+  __ crc32h(w4, w5, w6);
+  __ crc32w(w7, w8, w9);
+  __ csel(w13, w14, w15, cc);
+  __ csel(w13, w14, w15, cs);
+  __ csel(x16, x17, x18, hi);
+  __ csel(x16, x17, x18, ls);
+  __ cset(w19, eq);
+  __ cset(w19, ne);
+  __ cset(x20, cc);
+  __ cset(x20, cs);
+  __ csetm(w21, hi);
+  __ csetm(w21, ls);
+  __ csetm(x22, eq);
+  __ csetm(x22, ne);
+  __ csinc(w23, w24, w25, cc);
+  __ csinc(w23, w24, w25, cs);
+  __ csinc(x26, x27, x28, hi);
+  __ csinc(x26, x27, x28, ls);
+  __ csinv(w29, w2, w3, eq);
+  __ csinv(w29, w2, w3, ne);
+  __ csinv(x4, x5, x6, cc);
+  __ csinv(x4, x5, x6, cs);
+  __ csneg(w7, w8, w9, hi);
+  __ csneg(w7, w8, w9, ls);
+  __ csneg(x10, x11, x12, eq);
+  __ csneg(x10, x11, x12, ne);
+  __ dc(CVAC, x0);
+  __ dmb(InnerShareable, BarrierAll);
+  __ dsb(InnerShareable, BarrierAll);
+  __ eon(w13, w14, w15);
+  __ eon(x16, x17, x18);
+  __ eor(w19, w20, w21);
+  __ eor(x22, x23, x24);
+  __ extr(w25, w26, w27, 9);
+  __ extr(x28, x29, x2, 10);
+  __ hint(NOP);
+  __ ic(IVAU, x0);
+  __ isb();
+  __ ldar(w3, MemOperand(x0));
+  __ ldar(x4, MemOperand(x0));
+  __ ldarb(w5, MemOperand(x0));
+  __ ldarb(x6, MemOperand(x0));
+  __ ldarh(w7, MemOperand(x0));
+  __ ldarh(x8, MemOperand(x0));
+  __ ldaxp(w9, w10, MemOperand(x0));
+  __ ldaxp(x11, x12, MemOperand(x0));
+  __ ldaxr(w13, MemOperand(x0));
+  __ ldaxr(x14, MemOperand(x0));
+  __ ldaxrb(w15, MemOperand(x0));
+  __ ldaxrb(x16, MemOperand(x0));
+  __ ldaxrh(w17, MemOperand(x0));
+  __ ldaxrh(x18, MemOperand(x0));
+  __ ldnp(w19, w20, MemOperand(x0));
+  __ ldnp(x21, x22, MemOperand(x0));
+  __ ldp(w23, w24, MemOperand(x0));
+  __ ldp(w23, w24, MemOperand(x1, 8, PostIndex));
+  __ ldp(w23, w24, MemOperand(x1, 8, PreIndex));
+  __ ldp(x25, x26, MemOperand(x0));
+  __ ldp(x25, x26, MemOperand(x1, 16, PostIndex));
+  __ ldp(x25, x26, MemOperand(x1, 16, PreIndex));
+  __ ldpsw(x27, x28, MemOperand(x0));
+  __ ldpsw(x27, x28, MemOperand(x1, 8, PostIndex));
+  __ ldpsw(x27, x28, MemOperand(x1, 8, PreIndex));
+  __ ldr(w29, MemOperand(x0));
+  __ ldr(w29, MemOperand(x1, 4, PostIndex));
+  __ ldr(w29, MemOperand(x1, 4, PreIndex));
+  __ ldr(x2, MemOperand(x0));
+  __ ldr(x2, MemOperand(x1, 8, PostIndex));
+  __ ldr(x2, MemOperand(x1, 8, PreIndex));
+  __ ldrb(w3, MemOperand(x0));
+  __ ldrb(w3, MemOperand(x1, 1, PostIndex));
+  __ ldrb(w3, MemOperand(x1, 1, PreIndex));
+  __ ldrb(x4, MemOperand(x0));
+  __ ldrb(x4, MemOperand(x1, 1, PostIndex));
+  __ ldrb(x4, MemOperand(x1, 1, PreIndex));
+  __ ldrh(w5, MemOperand(x0));
+  __ ldrh(w5, MemOperand(x1, 2, PostIndex));
+  __ ldrh(w5, MemOperand(x1, 2, PreIndex));
+  __ ldrh(x6, MemOperand(x0));
+  __ ldrh(x6, MemOperand(x1, 2, PostIndex));
+  __ ldrh(x6, MemOperand(x1, 2, PreIndex));
+  __ ldrsb(w7, MemOperand(x0));
+  __ ldrsb(w7, MemOperand(x1, 1, PostIndex));
+  __ ldrsb(w7, MemOperand(x1, 1, PreIndex));
+  __ ldrsb(x8, MemOperand(x0));
+  __ ldrsb(x8, MemOperand(x1, 1, PostIndex));
+  __ ldrsb(x8, MemOperand(x1, 1, PreIndex));
+  __ ldrsh(w9, MemOperand(x0));
+  __ ldrsh(w9, MemOperand(x1, 2, PostIndex));
+  __ ldrsh(w9, MemOperand(x1, 2, PreIndex));
+  __ ldrsh(x10, MemOperand(x0));
+  __ ldrsh(x10, MemOperand(x1, 2, PostIndex));
+  __ ldrsh(x10, MemOperand(x1, 2, PreIndex));
+  __ ldrsw(x11, MemOperand(x0));
+  __ ldrsw(x11, MemOperand(x1, 4, PostIndex));
+  __ ldrsw(x11, MemOperand(x1, 4, PreIndex));
+  __ ldur(w12, MemOperand(x0, 7));
+  __ ldur(x13, MemOperand(x0, 15));
+  __ ldurb(w14, MemOperand(x0, 1));
+  __ ldurb(x15, MemOperand(x0, 1));
+  __ ldurh(w16, MemOperand(x0, 3));
+  __ ldurh(x17, MemOperand(x0, 3));
+  __ ldursb(w18, MemOperand(x0, 1));
+  __ ldursb(x19, MemOperand(x0, 1));
+  __ ldursh(w20, MemOperand(x0, 3));
+  __ ldursh(x21, MemOperand(x0, 3));
+  __ ldursw(x22, MemOperand(x0, 7));
+  __ ldxp(w23, w24, MemOperand(x0));
+  __ ldxp(x25, x26, MemOperand(x0));
+  __ ldxr(w27, MemOperand(x0));
+  __ ldxr(x28, MemOperand(x0));
+  __ ldxrb(w29, MemOperand(x0));
+  __ ldxrb(x2, MemOperand(x0));
+  __ ldxrh(w3, MemOperand(x0));
+  __ ldxrh(x4, MemOperand(x0));
+  __ lsl(w5, w6, 2);
+  __ lsl(x7, x8, 3);
+  __ lslv(w9, w10, w11);
+  __ lslv(x12, x13, x14);
+  __ lsr(w15, w16, 4);
+  __ lsr(x17, x18, 5);
+  __ lsrv(w19, w20, w21);
+  __ lsrv(x22, x23, x24);
+  __ madd(w25, w26, w27, w28);
+  __ madd(x29, x2, x3, x4);
+  __ mneg(w5, w6, w7);
+  __ mneg(x8, x9, x10);
+  __ mov(w11, w12);
+  __ mov(x13, x14);
+  __ movk(w15, 130);
+  __ movk(x16, 131);
+  __ movn(w17, 132);
+  __ movn(x18, 133);
+  __ movz(w19, 134);
+  __ movz(x20, 135);
+  __ msub(w22, w23, w24, w25);
+  __ msub(x26, x27, x28, x29);
+  __ mul(w2, w3, w4);
+  __ mul(x5, x6, x7);
+  __ mvn(w8, w9);
+  __ mvn(x10, x11);
+  __ neg(w12, w13);
+  __ neg(x14, x15);
+  __ negs(w16, w17);
+  __ negs(x18, x19);
+  __ ngc(w20, w21);
+  __ ngc(x22, x23);
+  __ ngcs(w24, w25);
+  __ ngcs(x26, x27);
+  __ nop();
+  __ orn(w28, w29, w2);
+  __ orn(x3, x4, x5);
+  __ orr(w6, w7, w8);
+  __ orr(x9, x10, x11);
+  __ prfm(PLDL1KEEP, MemOperand(x0, 4));
+  __ prfum(PLDL1KEEP, MemOperand(x0, 1));
+  __ rbit(w12, w13);
+  __ rbit(x14, x15);
+  __ rev(w16, w17);
+  __ rev(x18, x19);
+  __ rev16(w20, w21);
+  __ rev16(x22, x23);
+  __ rev32(x24, x25);
+  __ rorv(w26, w27, w28);
+  __ rorv(x29, x2, x3);
+  __ sbc(w4, w5, w6);
+  __ sbc(x7, x8, x9);
+  __ sbcs(w10, w11, w12);
+  __ sbcs(x13, x14, x15);
+  __ sbfiz(w16, w17, 2, 3);
+  __ sbfiz(x18, x19, 4, 5);
+  __ sbfx(w22, w23, 6, 7);
+  __ sbfx(x24, x25, 8, 9);
+  __ sdiv(w26, w27, w28);
+  __ sdiv(x29, x2, x3);
+  __ smulh(x12, x13, x14);
+  __ stlr(w18, MemOperand(x0));
+  __ stlr(x19, MemOperand(x0));
+  __ stlrb(w20, MemOperand(x0));
+  __ stlrb(x21, MemOperand(x0));
+  __ stlrh(w22, MemOperand(x0));
+  __ stlrh(x23, MemOperand(x0));
+  __ stlxp(w24, w25, w26, MemOperand(x0));
+  __ stlxp(x27, x28, x29, MemOperand(x0));
+  __ stlxr(w2, w3, MemOperand(x0));
+  __ stlxr(x4, x5, MemOperand(x0));
+  __ stlxrb(w6, w7, MemOperand(x0));
+  __ stlxrb(x8, x9, MemOperand(x0));
+  __ stlxrh(w10, w11, MemOperand(x0));
+  __ stlxrh(x12, x13, MemOperand(x0));
+  __ stnp(w14, w15, MemOperand(x0));
+  __ stnp(x16, x17, MemOperand(x0));
+  __ stp(w18, w19, MemOperand(x0));
+  __ stp(w18, w19, MemOperand(x1, 8, PostIndex));
+  __ stp(w18, w19, MemOperand(x1, 8, PreIndex));
+  __ stp(x20, x21, MemOperand(x0));
+  __ stp(x20, x21, MemOperand(x1, 16, PostIndex));
+  __ stp(x20, x21, MemOperand(x1, 16, PreIndex));
+  __ str(w22, MemOperand(x0));
+  __ str(w22, MemOperand(x1, 4, PostIndex));
+  __ str(w22, MemOperand(x1, 4, PreIndex));
+  __ str(x23, MemOperand(x0));
+  __ str(x23, MemOperand(x1, 8, PostIndex));
+  __ str(x23, MemOperand(x1, 8, PreIndex));
+  __ strb(w24, MemOperand(x0));
+  __ strb(w24, MemOperand(x1, 1, PostIndex));
+  __ strb(w24, MemOperand(x1, 1, PreIndex));
+  __ strb(x25, MemOperand(x0));
+  __ strb(x25, MemOperand(x1, 1, PostIndex));
+  __ strb(x25, MemOperand(x1, 1, PreIndex));
+  __ strh(w26, MemOperand(x0));
+  __ strh(w26, MemOperand(x1, 2, PostIndex));
+  __ strh(w26, MemOperand(x1, 2, PreIndex));
+  __ strh(x27, MemOperand(x0));
+  __ strh(x27, MemOperand(x1, 2, PostIndex));
+  __ strh(x27, MemOperand(x1, 2, PreIndex));
+  __ stur(w28, MemOperand(x0, 7));
+  __ stur(x29, MemOperand(x0, 15));
+  __ sturb(w2, MemOperand(x0, 1));
+  __ sturb(x3, MemOperand(x0, 1));
+  __ sturh(w4, MemOperand(x0, 3));
+  __ sturh(x5, MemOperand(x0, 3));
+  __ stxp(w6, w7, w8, MemOperand(x0));
+  __ stxp(x9, x10, x11, MemOperand(x0));
+  __ stxr(w12, w13, MemOperand(x0));
+  __ stxr(x14, x15, MemOperand(x0));
+  __ stxrb(w16, w17, MemOperand(x0));
+  __ stxrb(x18, x19, MemOperand(x0));
+  __ stxrh(w20, w21, MemOperand(x0));
+  __ stxrh(x22, x23, MemOperand(x0));
+  __ sub(w24, w25, w26);
+  __ sub(x27, x28, x29);
+  __ subs(w2, w3, w4);
+  __ subs(x5, x6, x7);
+  __ sxtb(w8, w9);
+  __ sxtb(x10, x11);
+  __ sxth(w12, w13);
+  __ sxth(x14, x15);
+  __ sxtw(w16, w17);
+  __ sxtw(x18, x19);
+  __ tst(w20, w21);
+  __ tst(x22, x23);
+  __ ubfiz(w24, w25, 10, 11);
+  __ ubfiz(x26, x27, 12, 13);
+  __ ubfm(w28, w29, 14, 15);
+  __ ubfm(x2, x3, 1, 2);
+  __ ubfx(w4, w5, 3, 4);
+  __ ubfx(x6, x7, 5, 6);
+  __ udiv(w8, w9, w10);
+  __ udiv(x11, x12, x13);
+  __ umulh(x22, x23, x24);
+  __ uxtb(w28, w29);
+  __ uxtb(x2, x3);
+  __ uxth(w4, w5);
+  __ uxth(x6, x7);
+  __ uxtw(w8, w9);
+  __ uxtw(x10, x11);
+}
+
+
+static void GenerateTestSequenceFP(MacroAssembler* masm) {
+  CodeBufferCheckScope guard(masm, masm->RemainingBufferSpace());
+
+  // Scalar floating point instructions.
+  __ fabd(d13, d2, d19);
+  __ fabd(s8, s10, s30);
+  __ fabs(d1, d1);
+  __ fabs(s25, s7);
+  __ facge(d1, d23, d16);
+  __ facge(s4, s17, s1);
+  __ facgt(d2, d21, d24);
+  __ facgt(s12, s26, s12);
+  __ fadd(d13, d11, d22);
+  __ fadd(s27, s19, s8);
+  __ fccmp(d6, d10, NoFlag, hs);
+  __ fccmp(s29, s20, NZVFlag, ne);
+  __ fccmpe(d10, d2, NZCFlag, al);
+  __ fccmpe(s3, s3, NZVFlag, pl);
+  __ fcmeq(d19, d8, d10);
+  __ fcmeq(d0, d18, 0.0);
+  __ fcmeq(s1, s4, s30);
+  __ fcmeq(s22, s29, 0.0);
+  __ fcmge(d27, d18, d1);
+  __ fcmge(d31, d28, 0.0);
+  __ fcmge(s31, s19, s9);
+  __ fcmge(s1, s25, 0.0);
+  __ fcmgt(d18, d1, d15);
+  __ fcmgt(d3, d31, 0.0);
+  __ fcmgt(s11, s25, s2);
+  __ fcmgt(s17, s16, 0.0);
+  __ fcmle(d24, d17, 0.0);
+  __ fcmle(s11, s8, 0.0);
+  __ fcmlt(d5, d31, 0.0);
+  __ fcmlt(s18, s23, 0.0);
+  __ fcmp(d10, d24);
+  __ fcmp(d13, 0.0);
+  __ fcmp(s18, s6);
+  __ fcmp(s16, 0.0);
+  __ fcmpe(d9, d17);
+  __ fcmpe(d29, 0.0);
+  __ fcmpe(s16, s17);
+  __ fcmpe(s22, 0.0);
+  __ fcsel(d10, d14, d19, gt);
+  __ fcsel(s22, s18, s2, ge);
+  __ fcvt(d4, h24);
+  __ fcvt(d11, s2);
+  __ fcvt(h8, d9);
+  __ fcvt(h12, s1);
+  __ fcvt(s12, d31);
+  __ fcvt(s27, h25);
+  __ fcvtas(d28, d16);
+  __ fcvtas(s3, s5);
+  __ fcvtas(w18, d31);
+  __ fcvtas(w29, s24);
+  __ fcvtas(x9, d1);
+  __ fcvtas(x30, s2);
+  __ fcvtau(d14, d0);
+  __ fcvtau(s31, s14);
+  __ fcvtau(w16, d2);
+  __ fcvtau(w18, s0);
+  __ fcvtau(x26, d7);
+  __ fcvtau(x25, s19);
+  __ fcvtms(d30, d25);
+  __ fcvtms(s12, s15);
+  __ fcvtms(w9, d7);
+  __ fcvtms(w19, s6);
+  __ fcvtms(x6, d6);
+  __ fcvtms(x22, s7);
+  __ fcvtmu(d27, d0);
+  __ fcvtmu(s8, s22);
+  __ fcvtmu(w29, d19);
+  __ fcvtmu(w26, s0);
+  __ fcvtmu(x13, d5);
+  __ fcvtmu(x5, s18);
+  __ fcvtns(d30, d15);
+  __ fcvtns(s10, s11);
+  __ fcvtns(w21, d15);
+  __ fcvtns(w18, s10);
+  __ fcvtns(x8, d17);
+  __ fcvtns(x17, s12);
+  __ fcvtnu(d0, d21);
+  __ fcvtnu(s6, s25);
+  __ fcvtnu(w29, d11);
+  __ fcvtnu(w25, s31);
+  __ fcvtnu(x30, d11);
+  __ fcvtnu(x27, s18);
+  __ fcvtps(d11, d22);
+  __ fcvtps(s29, s20);
+  __ fcvtps(w15, d25);
+  __ fcvtps(w16, s7);
+  __ fcvtps(x13, d20);
+  __ fcvtps(x3, s23);
+  __ fcvtpu(d24, d1);
+  __ fcvtpu(s14, s24);
+  __ fcvtpu(w26, d29);
+  __ fcvtpu(wzr, s26);
+  __ fcvtpu(x27, d6);
+  __ fcvtpu(x29, s14);
+  __ fcvtxn(s12, d12);
+  __ fcvtzs(d15, d0);
+  __ fcvtzs(d13, d4, 42);
+  __ fcvtzs(s8, s11);
+  __ fcvtzs(s31, s6, 25);
+  __ fcvtzs(w6, d9);
+  __ fcvtzs(w25, d10, 20);
+  __ fcvtzs(w9, s1);
+  __ fcvtzs(w17, s29, 30);
+  __ fcvtzs(x19, d2);
+  __ fcvtzs(x22, d14, 1);
+  __ fcvtzs(x14, s20);
+  __ fcvtzs(x3, s30, 33);
+  __ fcvtzu(d28, d15);
+  __ fcvtzu(d0, d4, 3);
+  __ fcvtzu(s2, s5);
+  __ fcvtzu(s4, s0, 30);
+  __ fcvtzu(w11, d4);
+  __ fcvtzu(w7, d24, 32);
+  __ fcvtzu(w18, s24);
+  __ fcvtzu(w14, s27, 4);
+  __ fcvtzu(x22, d11);
+  __ fcvtzu(x8, d27, 52);
+  __ fcvtzu(x7, s20);
+  __ fcvtzu(x22, s7, 44);
+  __ fdiv(d6, d14, d15);
+  __ fdiv(s26, s5, s25);
+  __ fmadd(d18, d26, d12, d30);
+  __ fmadd(s13, s9, s28, s4);
+  __ fmax(d12, d5, d5);
+  __ fmax(s12, s28, s6);
+  __ fmaxnm(d28, d4, d2);
+  __ fmaxnm(s6, s10, s8);
+  __ fmin(d20, d20, d18);
+  __ fmin(s7, s13, s16);
+  __ fminnm(d19, d14, d30);
+  __ fminnm(s0, s1, s1);
+  __ fmov(d13, d6);
+  __ fmov(d2, x17);
+  __ fmov(d8, -2.5000);
+  __ fmov(s5, s3);
+  __ fmov(s25, w20);
+  __ fmov(s21, 2.8750f);
+  __ fmov(w18, s24);
+  __ fmov(x18, d2);
+  __ fmsub(d20, d30, d3, d19);
+  __ fmsub(s5, s19, s4, s12);
+  __ fmul(d30, d27, d23);
+  __ fmul(s25, s17, s15);
+  __ fmulx(d4, d17, d1);
+  __ fmulx(s14, s25, s4);
+  __ fneg(d15, d0);
+  __ fneg(s14, s15);
+  __ fnmadd(d0, d16, d22, d31);
+  __ fnmadd(s0, s18, s26, s18);
+  __ fnmsub(d19, d12, d15, d21);
+  __ fnmsub(s29, s0, s11, s26);
+  __ fnmul(d31, d19, d1);
+  __ fnmul(s18, s3, s17);
+  __ frecpe(d7, d21);
+  __ frecpe(s29, s17);
+  __ frecps(d11, d26, d17);
+  __ frecps(s18, s27, s1);
+  __ frecpx(d15, d18);
+  __ frecpx(s5, s10);
+  __ frinta(d16, d30);
+  __ frinta(s1, s22);
+  __ frinti(d19, d29);
+  __ frinti(s14, s21);
+  __ frintm(d20, d30);
+  __ frintm(s1, s16);
+  __ frintn(d30, d1);
+  __ frintn(s24, s10);
+  __ frintp(d4, d20);
+  __ frintp(s13, s3);
+  __ frintx(d13, d20);
+  __ frintx(s17, s7);
+  __ frintz(d0, d8);
+  __ frintz(s15, s29);
+  __ frsqrte(d21, d10);
+  __ frsqrte(s17, s25);
+  __ frsqrts(d4, d29, d17);
+  __ frsqrts(s14, s3, s24);
+  __ fsqrt(d14, d17);
+  __ fsqrt(s4, s14);
+  __ fsub(d13, d19, d7);
+  __ fsub(s3, s21, s27);
+  __ scvtf(d31, d16);
+  __ scvtf(d26, d31, 24);
+  __ scvtf(d6, w16);
+  __ scvtf(d5, w20, 6);
+  __ scvtf(d16, x8);
+  __ scvtf(d15, x8, 10);
+  __ scvtf(s7, s4);
+  __ scvtf(s8, s15, 14);
+  __ scvtf(s29, w10);
+  __ scvtf(s15, w21, 11);
+  __ scvtf(s27, x26);
+  __ scvtf(s26, x12, 38);
+  __ ucvtf(d0, d9);
+  __ ucvtf(d5, d22, 47);
+  __ ucvtf(d30, w27);
+  __ ucvtf(d3, w19, 1);
+  __ ucvtf(d28, x21);
+  __ ucvtf(d27, x30, 35);
+  __ ucvtf(s11, s5);
+  __ ucvtf(s0, s23, 14);
+  __ ucvtf(s20, w19);
+  __ ucvtf(s21, w22, 18);
+  __ ucvtf(s6, x13);
+  __ ucvtf(s7, x2, 21);
+}
+
+
+static void GenerateTestSequenceNEON(MacroAssembler* masm) {
+  CodeBufferCheckScope guard(masm, masm->RemainingBufferSpace());
+
+  // NEON integer instructions.
+  __ abs(d19, d0);
+  __ abs(v16.V16B(), v11.V16B());
+  __ abs(v0.V2D(), v31.V2D());
+  __ abs(v27.V2S(), v25.V2S());
+  __ abs(v21.V4H(), v27.V4H());
+  __ abs(v16.V4S(), v1.V4S());
+  __ abs(v31.V8B(), v5.V8B());
+  __ abs(v29.V8H(), v13.V8H());
+  __ add(d10, d5, d17);
+  __ add(v31.V16B(), v15.V16B(), v23.V16B());
+  __ add(v10.V2D(), v31.V2D(), v14.V2D());
+  __ add(v15.V2S(), v14.V2S(), v19.V2S());
+  __ add(v27.V4H(), v23.V4H(), v17.V4H());
+  __ add(v25.V4S(), v28.V4S(), v29.V4S());
+  __ add(v13.V8B(), v7.V8B(), v18.V8B());
+  __ add(v4.V8H(), v2.V8H(), v1.V8H());
+  __ addhn(v10.V2S(), v14.V2D(), v15.V2D());
+  __ addhn(v10.V4H(), v30.V4S(), v26.V4S());
+  __ addhn(v31.V8B(), v12.V8H(), v22.V8H());
+  __ addhn2(v16.V16B(), v21.V8H(), v20.V8H());
+  __ addhn2(v0.V4S(), v2.V2D(), v17.V2D());
+  __ addhn2(v31.V8H(), v7.V4S(), v17.V4S());
+  __ addp(d14, v19.V2D());
+  __ addp(v3.V16B(), v8.V16B(), v28.V16B());
+  __ addp(v8.V2D(), v5.V2D(), v17.V2D());
+  __ addp(v22.V2S(), v30.V2S(), v26.V2S());
+  __ addp(v29.V4H(), v24.V4H(), v14.V4H());
+  __ addp(v30.V4S(), v26.V4S(), v24.V4S());
+  __ addp(v12.V8B(), v26.V8B(), v7.V8B());
+  __ addp(v17.V8H(), v8.V8H(), v12.V8H());
+  __ addv(b27, v23.V16B());
+  __ addv(b12, v20.V8B());
+  __ addv(h27, v30.V4H());
+  __ addv(h19, v14.V8H());
+  __ addv(s14, v27.V4S());
+  __ and_(v10.V16B(), v8.V16B(), v27.V16B());
+  __ and_(v5.V8B(), v1.V8B(), v16.V8B());
+  __ bic(v26.V16B(), v3.V16B(), v24.V16B());
+  __ bic(v7.V2S(), 0xe4, 16);
+  __ bic(v28.V4H(), 0x23, 8);
+  __ bic(v29.V4S(), 0xac);
+  __ bic(v12.V8B(), v31.V8B(), v21.V8B());
+  __ bic(v18.V8H(), 0x98);
+  __ bif(v12.V16B(), v26.V16B(), v8.V16B());
+  __ bif(v2.V8B(), v23.V8B(), v27.V8B());
+  __ bit(v8.V16B(), v3.V16B(), v13.V16B());
+  __ bit(v5.V8B(), v5.V8B(), v23.V8B());
+  __ bsl(v9.V16B(), v31.V16B(), v23.V16B());
+  __ bsl(v14.V8B(), v7.V8B(), v3.V8B());
+  __ cls(v29.V16B(), v5.V16B());
+  __ cls(v21.V2S(), v0.V2S());
+  __ cls(v1.V4H(), v12.V4H());
+  __ cls(v27.V4S(), v10.V4S());
+  __ cls(v19.V8B(), v4.V8B());
+  __ cls(v15.V8H(), v14.V8H());
+  __ clz(v1.V16B(), v4.V16B());
+  __ clz(v27.V2S(), v17.V2S());
+  __ clz(v9.V4H(), v9.V4H());
+  __ clz(v31.V4S(), v15.V4S());
+  __ clz(v14.V8B(), v19.V8B());
+  __ clz(v6.V8H(), v11.V8H());
+  __ cmeq(d18, d5, d29);
+  __ cmeq(d14, d31, 0);
+  __ cmeq(v19.V16B(), v3.V16B(), v22.V16B());
+  __ cmeq(v15.V16B(), v9.V16B(), 0);
+  __ cmeq(v12.V2D(), v16.V2D(), v10.V2D());
+  __ cmeq(v8.V2D(), v22.V2D(), 0);
+  __ cmeq(v2.V2S(), v3.V2S(), v9.V2S());
+  __ cmeq(v16.V2S(), v25.V2S(), 0);
+  __ cmeq(v6.V4H(), v23.V4H(), v20.V4H());
+  __ cmeq(v16.V4H(), v13.V4H(), 0);
+  __ cmeq(v21.V4S(), v17.V4S(), v2.V4S());
+  __ cmeq(v6.V4S(), v25.V4S(), 0);
+  __ cmeq(v16.V8B(), v13.V8B(), v2.V8B());
+  __ cmeq(v21.V8B(), v16.V8B(), 0);
+  __ cmeq(v20.V8H(), v7.V8H(), v25.V8H());
+  __ cmeq(v26.V8H(), v8.V8H(), 0);
+  __ cmge(d16, d13, d31);
+  __ cmge(d25, d24, 0);
+  __ cmge(v17.V16B(), v19.V16B(), v17.V16B());
+  __ cmge(v22.V16B(), v30.V16B(), 0);
+  __ cmge(v28.V2D(), v20.V2D(), v26.V2D());
+  __ cmge(v6.V2D(), v23.V2D(), 0);
+  __ cmge(v25.V2S(), v22.V2S(), v3.V2S());
+  __ cmge(v21.V2S(), v11.V2S(), 0);
+  __ cmge(v16.V4H(), v3.V4H(), v12.V4H());
+  __ cmge(v23.V4H(), v9.V4H(), 0);
+  __ cmge(v7.V4S(), v2.V4S(), v11.V4S());
+  __ cmge(v0.V4S(), v22.V4S(), 0);
+  __ cmge(v10.V8B(), v30.V8B(), v9.V8B());
+  __ cmge(v21.V8B(), v8.V8B(), 0);
+  __ cmge(v2.V8H(), v7.V8H(), v26.V8H());
+  __ cmge(v19.V8H(), v10.V8H(), 0);
+  __ cmgt(d6, d13, d1);
+  __ cmgt(d30, d24, 0);
+  __ cmgt(v20.V16B(), v25.V16B(), v27.V16B());
+  __ cmgt(v0.V16B(), v25.V16B(), 0);
+  __ cmgt(v22.V2D(), v25.V2D(), v1.V2D());
+  __ cmgt(v16.V2D(), v16.V2D(), 0);
+  __ cmgt(v5.V2S(), v9.V2S(), v15.V2S());
+  __ cmgt(v12.V2S(), v18.V2S(), 0);
+  __ cmgt(v28.V4H(), v18.V4H(), v11.V4H());
+  __ cmgt(v22.V4H(), v3.V4H(), 0);
+  __ cmgt(v5.V4S(), v11.V4S(), v27.V4S());
+  __ cmgt(v13.V4S(), v20.V4S(), 0);
+  __ cmgt(v27.V8B(), v31.V8B(), v7.V8B());
+  __ cmgt(v5.V8B(), v0.V8B(), 0);
+  __ cmgt(v22.V8H(), v28.V8H(), v13.V8H());
+  __ cmgt(v6.V8H(), v2.V8H(), 0);
+  __ cmhi(d21, d8, d22);
+  __ cmhi(v18.V16B(), v19.V16B(), v19.V16B());
+  __ cmhi(v7.V2D(), v0.V2D(), v21.V2D());
+  __ cmhi(v15.V2S(), v19.V2S(), v0.V2S());
+  __ cmhi(v31.V4H(), v7.V4H(), v12.V4H());
+  __ cmhi(v9.V4S(), v16.V4S(), v22.V4S());
+  __ cmhi(v7.V8B(), v24.V8B(), v28.V8B());
+  __ cmhi(v11.V8H(), v10.V8H(), v25.V8H());
+  __ cmhs(d1, d12, d17);
+  __ cmhs(v21.V16B(), v25.V16B(), v30.V16B());
+  __ cmhs(v8.V2D(), v2.V2D(), v26.V2D());
+  __ cmhs(v1.V2S(), v22.V2S(), v29.V2S());
+  __ cmhs(v26.V4H(), v30.V4H(), v30.V4H());
+  __ cmhs(v19.V4S(), v20.V4S(), v16.V4S());
+  __ cmhs(v1.V8B(), v3.V8B(), v26.V8B());
+  __ cmhs(v20.V8H(), v28.V8H(), v8.V8H());
+  __ cmle(d30, d24, 0);
+  __ cmle(v0.V16B(), v3.V16B(), 0);
+  __ cmle(v2.V2D(), v30.V2D(), 0);
+  __ cmle(v7.V2S(), v10.V2S(), 0);
+  __ cmle(v9.V4H(), v31.V4H(), 0);
+  __ cmle(v9.V4S(), v18.V4S(), 0);
+  __ cmle(v21.V8B(), v31.V8B(), 0);
+  __ cmle(v29.V8H(), v21.V8H(), 0);
+  __ cmlt(d25, d23, 0);
+  __ cmlt(v7.V16B(), v21.V16B(), 0);
+  __ cmlt(v7.V2D(), v30.V2D(), 0);
+  __ cmlt(v25.V2S(), v28.V2S(), 0);
+  __ cmlt(v0.V4H(), v11.V4H(), 0);
+  __ cmlt(v24.V4S(), v5.V4S(), 0);
+  __ cmlt(v26.V8B(), v11.V8B(), 0);
+  __ cmlt(v1.V8H(), v21.V8H(), 0);
+  __ cmtst(d28, d23, d30);
+  __ cmtst(v26.V16B(), v6.V16B(), v31.V16B());
+  __ cmtst(v1.V2D(), v21.V2D(), v4.V2D());
+  __ cmtst(v27.V2S(), v26.V2S(), v20.V2S());
+  __ cmtst(v26.V4H(), v0.V4H(), v18.V4H());
+  __ cmtst(v25.V4S(), v16.V4S(), v4.V4S());
+  __ cmtst(v11.V8B(), v10.V8B(), v9.V8B());
+  __ cmtst(v0.V8H(), v2.V8H(), v1.V8H());
+  __ cnt(v25.V16B(), v15.V16B());
+  __ cnt(v28.V8B(), v6.V8B());
+  __ dup(v6.V16B(), v7.B(), 7);
+  __ dup(v9.V16B(), w20);
+  __ dup(v12.V2D(), v13.D(), 1);
+  __ dup(v9.V2D(), xzr);
+  __ dup(v4.V2S(), v26.S(), 2);
+  __ dup(v3.V2S(), w12);
+  __ dup(v22.V4H(), v5.H(), 7);
+  __ dup(v16.V4H(), w25);
+  __ dup(v20.V4S(), v10.S(), 2);
+  __ dup(v10.V4S(), w7);
+  __ dup(v30.V8B(), v30.B(), 2);
+  __ dup(v31.V8B(), w15);
+  __ dup(v28.V8H(), v17.H(), 4);
+  __ dup(v2.V8H(), w3);
+  __ eor(v29.V16B(), v25.V16B(), v3.V16B());
+  __ eor(v3.V8B(), v16.V8B(), v28.V8B());
+  __ ext(v1.V16B(), v26.V16B(), v6.V16B(), 1);
+  __ ext(v2.V8B(), v30.V8B(), v1.V8B(), 1);
+  __ ld1(v18.V16B(), v19.V16B(), v20.V16B(), v21.V16B(), MemOperand(x0));
+  __ ld1(v23.V16B(), v24.V16B(), v25.V16B(), v26.V16B(),
+         MemOperand(x1, x2, PostIndex));
+  __ ld1(v5.V16B(), v6.V16B(), v7.V16B(), v8.V16B(),
+         MemOperand(x1, 64, PostIndex));
+  __ ld1(v18.V16B(), v19.V16B(), v20.V16B(), MemOperand(x0));
+  __ ld1(v13.V16B(), v14.V16B(), v15.V16B(), MemOperand(x1, x2, PostIndex));
+  __ ld1(v19.V16B(), v20.V16B(), v21.V16B(), MemOperand(x1, 48, PostIndex));
+  __ ld1(v17.V16B(), v18.V16B(), MemOperand(x0));
+  __ ld1(v20.V16B(), v21.V16B(), MemOperand(x1, x2, PostIndex));
+  __ ld1(v28.V16B(), v29.V16B(), MemOperand(x1, 32, PostIndex));
+  __ ld1(v29.V16B(), MemOperand(x0));
+  __ ld1(v21.V16B(), MemOperand(x1, x2, PostIndex));
+  __ ld1(v4.V16B(), MemOperand(x1, 16, PostIndex));
+  __ ld1(v4.V1D(), v5.V1D(), v6.V1D(), v7.V1D(), MemOperand(x0));
+  __ ld1(v17.V1D(), v18.V1D(), v19.V1D(), v20.V1D(),
+         MemOperand(x1, x2, PostIndex));
+  __ ld1(v28.V1D(), v29.V1D(), v30.V1D(), v31.V1D(),
+         MemOperand(x1, 32, PostIndex));
+  __ ld1(v20.V1D(), v21.V1D(), v22.V1D(), MemOperand(x0));
+  __ ld1(v19.V1D(), v20.V1D(), v21.V1D(), MemOperand(x1, x2, PostIndex));
+  __ ld1(v12.V1D(), v13.V1D(), v14.V1D(), MemOperand(x1, 24, PostIndex));
+  __ ld1(v29.V1D(), v30.V1D(), MemOperand(x0));
+  __ ld1(v31.V1D(), v0.V1D(), MemOperand(x1, x2, PostIndex));
+  __ ld1(v3.V1D(), v4.V1D(), MemOperand(x1, 16, PostIndex));
+  __ ld1(v28.V1D(), MemOperand(x0));
+  __ ld1(v11.V1D(), MemOperand(x1, x2, PostIndex));
+  __ ld1(v29.V1D(), MemOperand(x1, 8, PostIndex));
+  __ ld1(v28.V2D(), v29.V2D(), v30.V2D(), v31.V2D(), MemOperand(x0));
+  __ ld1(v8.V2D(), v9.V2D(), v10.V2D(), v11.V2D(),
+         MemOperand(x1, x2, PostIndex));
+  __ ld1(v14.V2D(), v15.V2D(), v16.V2D(), v17.V2D(),
+         MemOperand(x1, 64, PostIndex));
+  __ ld1(v26.V2D(), v27.V2D(), v28.V2D(), MemOperand(x0));
+  __ ld1(v5.V2D(), v6.V2D(), v7.V2D(), MemOperand(x1, x2, PostIndex));
+  __ ld1(v26.V2D(), v27.V2D(), v28.V2D(), MemOperand(x1, 48, PostIndex));
+  __ ld1(v18.V2D(), v19.V2D(), MemOperand(x0));
+  __ ld1(v21.V2D(), v22.V2D(), MemOperand(x1, x2, PostIndex));
+  __ ld1(v17.V2D(), v18.V2D(), MemOperand(x1, 32, PostIndex));
+  __ ld1(v5.V2D(), MemOperand(x0));
+  __ ld1(v6.V2D(), MemOperand(x1, x2, PostIndex));
+  __ ld1(v15.V2D(), MemOperand(x1, 16, PostIndex));
+  __ ld1(v30.V2S(), v31.V2S(), v0.V2S(), v1.V2S(), MemOperand(x0));
+  __ ld1(v24.V2S(), v25.V2S(), v26.V2S(), v27.V2S(),
+         MemOperand(x1, x2, PostIndex));
+  __ ld1(v27.V2S(), v28.V2S(), v29.V2S(), v30.V2S(),
+         MemOperand(x1, 32, PostIndex));
+  __ ld1(v11.V2S(), v12.V2S(), v13.V2S(), MemOperand(x0));
+  __ ld1(v8.V2S(), v9.V2S(), v10.V2S(), MemOperand(x1, x2, PostIndex));
+  __ ld1(v31.V2S(), v0.V2S(), v1.V2S(), MemOperand(x1, 24, PostIndex));
+  __ ld1(v0.V2S(), v1.V2S(), MemOperand(x0));
+  __ ld1(v13.V2S(), v14.V2S(), MemOperand(x1, x2, PostIndex));
+  __ ld1(v3.V2S(), v4.V2S(), MemOperand(x1, 16, PostIndex));
+  __ ld1(v26.V2S(), MemOperand(x0));
+  __ ld1(v0.V2S(), MemOperand(x1, x2, PostIndex));
+  __ ld1(v11.V2S(), MemOperand(x1, 8, PostIndex));
+  __ ld1(v16.V4H(), v17.V4H(), v18.V4H(), v19.V4H(), MemOperand(x0));
+  __ ld1(v24.V4H(), v25.V4H(), v26.V4H(), v27.V4H(),
+         MemOperand(x1, x2, PostIndex));
+  __ ld1(v1.V4H(), v2.V4H(), v3.V4H(), v4.V4H(), MemOperand(x1, 32, PostIndex));
+  __ ld1(v30.V4H(), v31.V4H(), v0.V4H(), MemOperand(x0));
+  __ ld1(v25.V4H(), v26.V4H(), v27.V4H(), MemOperand(x1, x2, PostIndex));
+  __ ld1(v3.V4H(), v4.V4H(), v5.V4H(), MemOperand(x1, 24, PostIndex));
+  __ ld1(v3.V4H(), v4.V4H(), MemOperand(x0));
+  __ ld1(v3.V4H(), v4.V4H(), MemOperand(x1, x2, PostIndex));
+  __ ld1(v23.V4H(), v24.V4H(), MemOperand(x1, 16, PostIndex));
+  __ ld1(v26.V4H(), MemOperand(x0));
+  __ ld1(v1.V4H(), MemOperand(x1, x2, PostIndex));
+  __ ld1(v14.V4H(), MemOperand(x1, 8, PostIndex));
+  __ ld1(v26.V4S(), v27.V4S(), v28.V4S(), v29.V4S(), MemOperand(x0));
+  __ ld1(v28.V4S(), v29.V4S(), v30.V4S(), v31.V4S(),
+         MemOperand(x1, x2, PostIndex));
+  __ ld1(v4.V4S(), v5.V4S(), v6.V4S(), v7.V4S(), MemOperand(x1, 64, PostIndex));
+  __ ld1(v2.V4S(), v3.V4S(), v4.V4S(), MemOperand(x0));
+  __ ld1(v22.V4S(), v23.V4S(), v24.V4S(), MemOperand(x1, x2, PostIndex));
+  __ ld1(v15.V4S(), v16.V4S(), v17.V4S(), MemOperand(x1, 48, PostIndex));
+  __ ld1(v20.V4S(), v21.V4S(), MemOperand(x0));
+  __ ld1(v30.V4S(), v31.V4S(), MemOperand(x1, x2, PostIndex));
+  __ ld1(v11.V4S(), v12.V4S(), MemOperand(x1, 32, PostIndex));
+  __ ld1(v15.V4S(), MemOperand(x0));
+  __ ld1(v12.V4S(), MemOperand(x1, x2, PostIndex));
+  __ ld1(v0.V4S(), MemOperand(x1, 16, PostIndex));
+  __ ld1(v17.V8B(), v18.V8B(), v19.V8B(), v20.V8B(), MemOperand(x0));
+  __ ld1(v5.V8B(), v6.V8B(), v7.V8B(), v8.V8B(), MemOperand(x1, x2, PostIndex));
+  __ ld1(v9.V8B(), v10.V8B(), v11.V8B(), v12.V8B(),
+         MemOperand(x1, 32, PostIndex));
+  __ ld1(v4.V8B(), v5.V8B(), v6.V8B(), MemOperand(x0));
+  __ ld1(v2.V8B(), v3.V8B(), v4.V8B(), MemOperand(x1, x2, PostIndex));
+  __ ld1(v12.V8B(), v13.V8B(), v14.V8B(), MemOperand(x1, 24, PostIndex));
+  __ ld1(v10.V8B(), v11.V8B(), MemOperand(x0));
+  __ ld1(v11.V8B(), v12.V8B(), MemOperand(x1, x2, PostIndex));
+  __ ld1(v27.V8B(), v28.V8B(), MemOperand(x1, 16, PostIndex));
+  __ ld1(v31.V8B(), MemOperand(x0));
+  __ ld1(v10.V8B(), MemOperand(x1, x2, PostIndex));
+  __ ld1(v28.V8B(), MemOperand(x1, 8, PostIndex));
+  __ ld1(v5.V8H(), v6.V8H(), v7.V8H(), v8.V8H(), MemOperand(x0));
+  __ ld1(v2.V8H(), v3.V8H(), v4.V8H(), v5.V8H(), MemOperand(x1, x2, PostIndex));
+  __ ld1(v10.V8H(), v11.V8H(), v12.V8H(), v13.V8H(),
+         MemOperand(x1, 64, PostIndex));
+  __ ld1(v26.V8H(), v27.V8H(), v28.V8H(), MemOperand(x0));
+  __ ld1(v3.V8H(), v4.V8H(), v5.V8H(), MemOperand(x1, x2, PostIndex));
+  __ ld1(v17.V8H(), v18.V8H(), v19.V8H(), MemOperand(x1, 48, PostIndex));
+  __ ld1(v4.V8H(), v5.V8H(), MemOperand(x0));
+  __ ld1(v21.V8H(), v22.V8H(), MemOperand(x1, x2, PostIndex));
+  __ ld1(v4.V8H(), v5.V8H(), MemOperand(x1, 32, PostIndex));
+  __ ld1(v9.V8H(), MemOperand(x0));
+  __ ld1(v27.V8H(), MemOperand(x1, x2, PostIndex));
+  __ ld1(v26.V8H(), MemOperand(x1, 16, PostIndex));
+  __ ld1(v19.B(), 1, MemOperand(x0));
+  __ ld1(v12.B(), 3, MemOperand(x1, x2, PostIndex));
+  __ ld1(v27.B(), 12, MemOperand(x1, 1, PostIndex));
+  __ ld1(v10.D(), 1, MemOperand(x0));
+  __ ld1(v26.D(), 1, MemOperand(x1, x2, PostIndex));
+  __ ld1(v7.D(), 1, MemOperand(x1, 8, PostIndex));
+  __ ld1(v19.H(), 5, MemOperand(x0));
+  __ ld1(v10.H(), 1, MemOperand(x1, x2, PostIndex));
+  __ ld1(v5.H(), 4, MemOperand(x1, 2, PostIndex));
+  __ ld1(v21.S(), 2, MemOperand(x0));
+  __ ld1(v13.S(), 2, MemOperand(x1, x2, PostIndex));
+  __ ld1(v1.S(), 2, MemOperand(x1, 4, PostIndex));
+  __ ld1r(v2.V16B(), MemOperand(x0));
+  __ ld1r(v2.V16B(), MemOperand(x1, x2, PostIndex));
+  __ ld1r(v22.V16B(), MemOperand(x1, 1, PostIndex));
+  __ ld1r(v25.V1D(), MemOperand(x0));
+  __ ld1r(v9.V1D(), MemOperand(x1, x2, PostIndex));
+  __ ld1r(v23.V1D(), MemOperand(x1, 8, PostIndex));
+  __ ld1r(v19.V2D(), MemOperand(x0));
+  __ ld1r(v21.V2D(), MemOperand(x1, x2, PostIndex));
+  __ ld1r(v30.V2D(), MemOperand(x1, 8, PostIndex));
+  __ ld1r(v24.V2S(), MemOperand(x0));
+  __ ld1r(v26.V2S(), MemOperand(x1, x2, PostIndex));
+  __ ld1r(v28.V2S(), MemOperand(x1, 4, PostIndex));
+  __ ld1r(v19.V4H(), MemOperand(x0));
+  __ ld1r(v1.V4H(), MemOperand(x1, x2, PostIndex));
+  __ ld1r(v21.V4H(), MemOperand(x1, 2, PostIndex));
+  __ ld1r(v15.V4S(), MemOperand(x0));
+  __ ld1r(v21.V4S(), MemOperand(x1, x2, PostIndex));
+  __ ld1r(v23.V4S(), MemOperand(x1, 4, PostIndex));
+  __ ld1r(v26.V8B(), MemOperand(x0));
+  __ ld1r(v14.V8B(), MemOperand(x1, x2, PostIndex));
+  __ ld1r(v19.V8B(), MemOperand(x1, 1, PostIndex));
+  __ ld1r(v13.V8H(), MemOperand(x0));
+  __ ld1r(v30.V8H(), MemOperand(x1, x2, PostIndex));
+  __ ld1r(v27.V8H(), MemOperand(x1, 2, PostIndex));
+  __ ld2(v21.V16B(), v22.V16B(), MemOperand(x0));
+  __ ld2(v21.V16B(), v22.V16B(), MemOperand(x1, x2, PostIndex));
+  __ ld2(v12.V16B(), v13.V16B(), MemOperand(x1, 32, PostIndex));
+  __ ld2(v14.V2D(), v15.V2D(), MemOperand(x0));
+  __ ld2(v0.V2D(), v1.V2D(), MemOperand(x1, x2, PostIndex));
+  __ ld2(v12.V2D(), v13.V2D(), MemOperand(x1, 32, PostIndex));
+  __ ld2(v27.V2S(), v28.V2S(), MemOperand(x0));
+  __ ld2(v2.V2S(), v3.V2S(), MemOperand(x1, x2, PostIndex));
+  __ ld2(v12.V2S(), v13.V2S(), MemOperand(x1, 16, PostIndex));
+  __ ld2(v9.V4H(), v10.V4H(), MemOperand(x0));
+  __ ld2(v23.V4H(), v24.V4H(), MemOperand(x1, x2, PostIndex));
+  __ ld2(v1.V4H(), v2.V4H(), MemOperand(x1, 16, PostIndex));
+  __ ld2(v20.V4S(), v21.V4S(), MemOperand(x0));
+  __ ld2(v10.V4S(), v11.V4S(), MemOperand(x1, x2, PostIndex));
+  __ ld2(v24.V4S(), v25.V4S(), MemOperand(x1, 32, PostIndex));
+  __ ld2(v17.V8B(), v18.V8B(), MemOperand(x0));
+  __ ld2(v13.V8B(), v14.V8B(), MemOperand(x1, x2, PostIndex));
+  __ ld2(v7.V8B(), v8.V8B(), MemOperand(x1, 16, PostIndex));
+  __ ld2(v30.V8H(), v31.V8H(), MemOperand(x0));
+  __ ld2(v4.V8H(), v5.V8H(), MemOperand(x1, x2, PostIndex));
+  __ ld2(v13.V8H(), v14.V8H(), MemOperand(x1, 32, PostIndex));
+  __ ld2(v5.B(), v6.B(), 12, MemOperand(x0));
+  __ ld2(v16.B(), v17.B(), 7, MemOperand(x1, x2, PostIndex));
+  __ ld2(v29.B(), v30.B(), 2, MemOperand(x1, 2, PostIndex));
+  __ ld2(v11.D(), v12.D(), 1, MemOperand(x0));
+  __ ld2(v26.D(), v27.D(), 0, MemOperand(x1, x2, PostIndex));
+  __ ld2(v25.D(), v26.D(), 0, MemOperand(x1, 16, PostIndex));
+  __ ld2(v18.H(), v19.H(), 7, MemOperand(x0));
+  __ ld2(v17.H(), v18.H(), 5, MemOperand(x1, x2, PostIndex));
+  __ ld2(v30.H(), v31.H(), 2, MemOperand(x1, 4, PostIndex));
+  __ ld2(v29.S(), v30.S(), 3, MemOperand(x0));
+  __ ld2(v28.S(), v29.S(), 0, MemOperand(x1, x2, PostIndex));
+  __ ld2(v6.S(), v7.S(), 1, MemOperand(x1, 8, PostIndex));
+  __ ld2r(v26.V16B(), v27.V16B(), MemOperand(x0));
+  __ ld2r(v21.V16B(), v22.V16B(), MemOperand(x1, x2, PostIndex));
+  __ ld2r(v5.V16B(), v6.V16B(), MemOperand(x1, 2, PostIndex));
+  __ ld2r(v26.V1D(), v27.V1D(), MemOperand(x0));
+  __ ld2r(v14.V1D(), v15.V1D(), MemOperand(x1, x2, PostIndex));
+  __ ld2r(v23.V1D(), v24.V1D(), MemOperand(x1, 16, PostIndex));
+  __ ld2r(v11.V2D(), v12.V2D(), MemOperand(x0));
+  __ ld2r(v29.V2D(), v30.V2D(), MemOperand(x1, x2, PostIndex));
+  __ ld2r(v15.V2D(), v16.V2D(), MemOperand(x1, 16, PostIndex));
+  __ ld2r(v26.V2S(), v27.V2S(), MemOperand(x0));
+  __ ld2r(v22.V2S(), v23.V2S(), MemOperand(x1, x2, PostIndex));
+  __ ld2r(v2.V2S(), v3.V2S(), MemOperand(x1, 8, PostIndex));
+  __ ld2r(v2.V4H(), v3.V4H(), MemOperand(x0));
+  __ ld2r(v9.V4H(), v10.V4H(), MemOperand(x1, x2, PostIndex));
+  __ ld2r(v6.V4H(), v7.V4H(), MemOperand(x1, 4, PostIndex));
+  __ ld2r(v7.V4S(), v8.V4S(), MemOperand(x0));
+  __ ld2r(v19.V4S(), v20.V4S(), MemOperand(x1, x2, PostIndex));
+  __ ld2r(v21.V4S(), v22.V4S(), MemOperand(x1, 8, PostIndex));
+  __ ld2r(v26.V8B(), v27.V8B(), MemOperand(x0));
+  __ ld2r(v20.V8B(), v21.V8B(), MemOperand(x1, x2, PostIndex));
+  __ ld2r(v11.V8B(), v12.V8B(), MemOperand(x1, 2, PostIndex));
+  __ ld2r(v12.V8H(), v13.V8H(), MemOperand(x0));
+  __ ld2r(v6.V8H(), v7.V8H(), MemOperand(x1, x2, PostIndex));
+  __ ld2r(v25.V8H(), v26.V8H(), MemOperand(x1, 4, PostIndex));
+  __ ld3(v20.V16B(), v21.V16B(), v22.V16B(), MemOperand(x0));
+  __ ld3(v28.V16B(), v29.V16B(), v30.V16B(), MemOperand(x1, x2, PostIndex));
+  __ ld3(v20.V16B(), v21.V16B(), v22.V16B(), MemOperand(x1, 48, PostIndex));
+  __ ld3(v21.V2D(), v22.V2D(), v23.V2D(), MemOperand(x0));
+  __ ld3(v18.V2D(), v19.V2D(), v20.V2D(), MemOperand(x1, x2, PostIndex));
+  __ ld3(v27.V2D(), v28.V2D(), v29.V2D(), MemOperand(x1, 48, PostIndex));
+  __ ld3(v7.V2S(), v8.V2S(), v9.V2S(), MemOperand(x0));
+  __ ld3(v20.V2S(), v21.V2S(), v22.V2S(), MemOperand(x1, x2, PostIndex));
+  __ ld3(v26.V2S(), v27.V2S(), v28.V2S(), MemOperand(x1, 24, PostIndex));
+  __ ld3(v27.V4H(), v28.V4H(), v29.V4H(), MemOperand(x0));
+  __ ld3(v28.V4H(), v29.V4H(), v30.V4H(), MemOperand(x1, x2, PostIndex));
+  __ ld3(v7.V4H(), v8.V4H(), v9.V4H(), MemOperand(x1, 24, PostIndex));
+  __ ld3(v2.V4S(), v3.V4S(), v4.V4S(), MemOperand(x0));
+  __ ld3(v24.V4S(), v25.V4S(), v26.V4S(), MemOperand(x1, x2, PostIndex));
+  __ ld3(v11.V4S(), v12.V4S(), v13.V4S(), MemOperand(x1, 48, PostIndex));
+  __ ld3(v29.V8B(), v30.V8B(), v31.V8B(), MemOperand(x0));
+  __ ld3(v1.V8B(), v2.V8B(), v3.V8B(), MemOperand(x1, x2, PostIndex));
+  __ ld3(v12.V8B(), v13.V8B(), v14.V8B(), MemOperand(x1, 24, PostIndex));
+  __ ld3(v22.V8H(), v23.V8H(), v24.V8H(), MemOperand(x0));
+  __ ld3(v13.V8H(), v14.V8H(), v15.V8H(), MemOperand(x1, x2, PostIndex));
+  __ ld3(v28.V8H(), v29.V8H(), v30.V8H(), MemOperand(x1, 48, PostIndex));
+  __ ld3(v21.B(), v22.B(), v23.B(), 11, MemOperand(x0));
+  __ ld3(v5.B(), v6.B(), v7.B(), 9, MemOperand(x1, x2, PostIndex));
+  __ ld3(v23.B(), v24.B(), v25.B(), 0, MemOperand(x1, 3, PostIndex));
+  __ ld3(v16.D(), v17.D(), v18.D(), 0, MemOperand(x0));
+  __ ld3(v30.D(), v31.D(), v0.D(), 0, MemOperand(x1, x2, PostIndex));
+  __ ld3(v28.D(), v29.D(), v30.D(), 1, MemOperand(x1, 24, PostIndex));
+  __ ld3(v13.H(), v14.H(), v15.H(), 2, MemOperand(x0));
+  __ ld3(v22.H(), v23.H(), v24.H(), 7, MemOperand(x1, x2, PostIndex));
+  __ ld3(v14.H(), v15.H(), v16.H(), 3, MemOperand(x1, 6, PostIndex));
+  __ ld3(v22.S(), v23.S(), v24.S(), 3, MemOperand(x0));
+  __ ld3(v30.S(), v31.S(), v0.S(), 2, MemOperand(x1, x2, PostIndex));
+  __ ld3(v12.S(), v13.S(), v14.S(), 1, MemOperand(x1, 12, PostIndex));
+  __ ld3r(v24.V16B(), v25.V16B(), v26.V16B(), MemOperand(x0));
+  __ ld3r(v24.V16B(), v25.V16B(), v26.V16B(), MemOperand(x1, x2, PostIndex));
+  __ ld3r(v3.V16B(), v4.V16B(), v5.V16B(), MemOperand(x1, 3, PostIndex));
+  __ ld3r(v4.V1D(), v5.V1D(), v6.V1D(), MemOperand(x0));
+  __ ld3r(v7.V1D(), v8.V1D(), v9.V1D(), MemOperand(x1, x2, PostIndex));
+  __ ld3r(v17.V1D(), v18.V1D(), v19.V1D(), MemOperand(x1, 24, PostIndex));
+  __ ld3r(v16.V2D(), v17.V2D(), v18.V2D(), MemOperand(x0));
+  __ ld3r(v20.V2D(), v21.V2D(), v22.V2D(), MemOperand(x1, x2, PostIndex));
+  __ ld3r(v14.V2D(), v15.V2D(), v16.V2D(), MemOperand(x1, 24, PostIndex));
+  __ ld3r(v10.V2S(), v11.V2S(), v12.V2S(), MemOperand(x0));
+  __ ld3r(v0.V2S(), v1.V2S(), v2.V2S(), MemOperand(x1, x2, PostIndex));
+  __ ld3r(v23.V2S(), v24.V2S(), v25.V2S(), MemOperand(x1, 12, PostIndex));
+  __ ld3r(v22.V4H(), v23.V4H(), v24.V4H(), MemOperand(x0));
+  __ ld3r(v6.V4H(), v7.V4H(), v8.V4H(), MemOperand(x1, x2, PostIndex));
+  __ ld3r(v7.V4H(), v8.V4H(), v9.V4H(), MemOperand(x1, 6, PostIndex));
+  __ ld3r(v26.V4S(), v27.V4S(), v28.V4S(), MemOperand(x0));
+  __ ld3r(v0.V4S(), v1.V4S(), v2.V4S(), MemOperand(x1, x2, PostIndex));
+  __ ld3r(v30.V4S(), v31.V4S(), v0.V4S(), MemOperand(x1, 12, PostIndex));
+  __ ld3r(v2.V8B(), v3.V8B(), v4.V8B(), MemOperand(x0));
+  __ ld3r(v10.V8B(), v11.V8B(), v12.V8B(), MemOperand(x1, x2, PostIndex));
+  __ ld3r(v28.V8B(), v29.V8B(), v30.V8B(), MemOperand(x1, 3, PostIndex));
+  __ ld3r(v6.V8H(), v7.V8H(), v8.V8H(), MemOperand(x0));
+  __ ld3r(v29.V8H(), v30.V8H(), v31.V8H(), MemOperand(x1, x2, PostIndex));
+  __ ld3r(v7.V8H(), v8.V8H(), v9.V8H(), MemOperand(x1, 6, PostIndex));
+  __ ld4(v3.V16B(), v4.V16B(), v5.V16B(), v6.V16B(), MemOperand(x0));
+  __ ld4(v2.V16B(), v3.V16B(), v4.V16B(), v5.V16B(),
+         MemOperand(x1, x2, PostIndex));
+  __ ld4(v5.V16B(), v6.V16B(), v7.V16B(), v8.V16B(),
+         MemOperand(x1, 64, PostIndex));
+  __ ld4(v18.V2D(), v19.V2D(), v20.V2D(), v21.V2D(), MemOperand(x0));
+  __ ld4(v4.V2D(), v5.V2D(), v6.V2D(), v7.V2D(), MemOperand(x1, x2, PostIndex));
+  __ ld4(v29.V2D(), v30.V2D(), v31.V2D(), v0.V2D(),
+         MemOperand(x1, 64, PostIndex));
+  __ ld4(v27.V2S(), v28.V2S(), v29.V2S(), v30.V2S(), MemOperand(x0));
+  __ ld4(v24.V2S(), v25.V2S(), v26.V2S(), v27.V2S(),
+         MemOperand(x1, x2, PostIndex));
+  __ ld4(v4.V2S(), v5.V2S(), v6.V2S(), v7.V2S(), MemOperand(x1, 32, PostIndex));
+  __ ld4(v16.V4H(), v17.V4H(), v18.V4H(), v19.V4H(), MemOperand(x0));
+  __ ld4(v23.V4H(), v24.V4H(), v25.V4H(), v26.V4H(),
+         MemOperand(x1, x2, PostIndex));
+  __ ld4(v2.V4H(), v3.V4H(), v4.V4H(), v5.V4H(), MemOperand(x1, 32, PostIndex));
+  __ ld4(v7.V4S(), v8.V4S(), v9.V4S(), v10.V4S(), MemOperand(x0));
+  __ ld4(v28.V4S(), v29.V4S(), v30.V4S(), v31.V4S(),
+         MemOperand(x1, x2, PostIndex));
+  __ ld4(v29.V4S(), v30.V4S(), v31.V4S(), v0.V4S(),
+         MemOperand(x1, 64, PostIndex));
+  __ ld4(v15.V8B(), v16.V8B(), v17.V8B(), v18.V8B(), MemOperand(x0));
+  __ ld4(v27.V8B(), v28.V8B(), v29.V8B(), v30.V8B(),
+         MemOperand(x1, x2, PostIndex));
+  __ ld4(v5.V8B(), v6.V8B(), v7.V8B(), v8.V8B(), MemOperand(x1, 32, PostIndex));
+  __ ld4(v25.V8H(), v26.V8H(), v27.V8H(), v28.V8H(), MemOperand(x0));
+  __ ld4(v2.V8H(), v3.V8H(), v4.V8H(), v5.V8H(), MemOperand(x1, x2, PostIndex));
+  __ ld4(v20.V8H(), v21.V8H(), v22.V8H(), v23.V8H(),
+         MemOperand(x1, 64, PostIndex));
+  __ ld4(v20.B(), v21.B(), v22.B(), v23.B(), 3, MemOperand(x0));
+  __ ld4(v12.B(), v13.B(), v14.B(), v15.B(), 3, MemOperand(x1, x2, PostIndex));
+  __ ld4(v27.B(), v28.B(), v29.B(), v30.B(), 6, MemOperand(x1, 4, PostIndex));
+  __ ld4(v28.D(), v29.D(), v30.D(), v31.D(), 1, MemOperand(x0));
+  __ ld4(v15.D(), v16.D(), v17.D(), v18.D(), 1, MemOperand(x1, x2, PostIndex));
+  __ ld4(v16.D(), v17.D(), v18.D(), v19.D(), 1, MemOperand(x1, 32, PostIndex));
+  __ ld4(v2.H(), v3.H(), v4.H(), v5.H(), 6, MemOperand(x0));
+  __ ld4(v5.H(), v6.H(), v7.H(), v8.H(), 3, MemOperand(x1, x2, PostIndex));
+  __ ld4(v7.H(), v8.H(), v9.H(), v10.H(), 6, MemOperand(x1, 8, PostIndex));
+  __ ld4(v6.S(), v7.S(), v8.S(), v9.S(), 1, MemOperand(x0));
+  __ ld4(v25.S(), v26.S(), v27.S(), v28.S(), 2, MemOperand(x1, x2, PostIndex));
+  __ ld4(v8.S(), v9.S(), v10.S(), v11.S(), 3, MemOperand(x1, 16, PostIndex));
+  __ ld4r(v14.V16B(), v15.V16B(), v16.V16B(), v17.V16B(), MemOperand(x0));
+  __ ld4r(v13.V16B(), v14.V16B(), v15.V16B(), v16.V16B(),
+          MemOperand(x1, x2, PostIndex));
+  __ ld4r(v9.V16B(), v10.V16B(), v11.V16B(), v12.V16B(),
+          MemOperand(x1, 4, PostIndex));
+  __ ld4r(v8.V1D(), v9.V1D(), v10.V1D(), v11.V1D(), MemOperand(x0));
+  __ ld4r(v4.V1D(), v5.V1D(), v6.V1D(), v7.V1D(),
+          MemOperand(x1, x2, PostIndex));
+  __ ld4r(v26.V1D(), v27.V1D(), v28.V1D(), v29.V1D(),
+          MemOperand(x1, 32, PostIndex));
+  __ ld4r(v19.V2D(), v20.V2D(), v21.V2D(), v22.V2D(), MemOperand(x0));
+  __ ld4r(v28.V2D(), v29.V2D(), v30.V2D(), v31.V2D(),
+          MemOperand(x1, x2, PostIndex));
+  __ ld4r(v15.V2D(), v16.V2D(), v17.V2D(), v18.V2D(),
+          MemOperand(x1, 32, PostIndex));
+  __ ld4r(v31.V2S(), v0.V2S(), v1.V2S(), v2.V2S(), MemOperand(x0));
+  __ ld4r(v28.V2S(), v29.V2S(), v30.V2S(), v31.V2S(),
+          MemOperand(x1, x2, PostIndex));
+  __ ld4r(v11.V2S(), v12.V2S(), v13.V2S(), v14.V2S(),
+          MemOperand(x1, 16, PostIndex));
+  __ ld4r(v19.V4H(), v20.V4H(), v21.V4H(), v22.V4H(), MemOperand(x0));
+  __ ld4r(v22.V4H(), v23.V4H(), v24.V4H(), v25.V4H(),
+          MemOperand(x1, x2, PostIndex));
+  __ ld4r(v20.V4H(), v21.V4H(), v22.V4H(), v23.V4H(),
+          MemOperand(x1, 8, PostIndex));
+  __ ld4r(v16.V4S(), v17.V4S(), v18.V4S(), v19.V4S(), MemOperand(x0));
+  __ ld4r(v25.V4S(), v26.V4S(), v27.V4S(), v28.V4S(),
+          MemOperand(x1, x2, PostIndex));
+  __ ld4r(v23.V4S(), v24.V4S(), v25.V4S(), v26.V4S(),
+          MemOperand(x1, 16, PostIndex));
+  __ ld4r(v22.V8B(), v23.V8B(), v24.V8B(), v25.V8B(), MemOperand(x0));
+  __ ld4r(v27.V8B(), v28.V8B(), v29.V8B(), v30.V8B(),
+          MemOperand(x1, x2, PostIndex));
+  __ ld4r(v29.V8B(), v30.V8B(), v31.V8B(), v0.V8B(),
+          MemOperand(x1, 4, PostIndex));
+  __ ld4r(v28.V8H(), v29.V8H(), v30.V8H(), v31.V8H(), MemOperand(x0));
+  __ ld4r(v25.V8H(), v26.V8H(), v27.V8H(), v28.V8H(),
+          MemOperand(x1, x2, PostIndex));
+  __ ld4r(v22.V8H(), v23.V8H(), v24.V8H(), v25.V8H(),
+          MemOperand(x1, 8, PostIndex));
+  __ mla(v29.V16B(), v7.V16B(), v26.V16B());
+  __ mla(v6.V2S(), v4.V2S(), v14.V2S());
+  __ mla(v9.V2S(), v11.V2S(), v0.S(), 2);
+  __ mla(v5.V4H(), v17.V4H(), v25.V4H());
+  __ mla(v24.V4H(), v7.V4H(), v11.H(), 3);
+  __ mla(v12.V4S(), v3.V4S(), v4.V4S());
+  __ mla(v10.V4S(), v7.V4S(), v7.S(), 3);
+  __ mla(v3.V8B(), v16.V8B(), v9.V8B());
+  __ mla(v19.V8H(), v22.V8H(), v18.V8H());
+  __ mla(v6.V8H(), v2.V8H(), v0.H(), 0);
+  __ mls(v23.V16B(), v10.V16B(), v11.V16B());
+  __ mls(v14.V2S(), v31.V2S(), v22.V2S());
+  __ mls(v28.V2S(), v13.V2S(), v1.S(), 3);
+  __ mls(v2.V4H(), v19.V4H(), v13.V4H());
+  __ mls(v18.V4H(), v15.V4H(), v12.H(), 6);
+  __ mls(v6.V4S(), v11.V4S(), v16.V4S());
+  __ mls(v23.V4S(), v16.V4S(), v10.S(), 2);
+  __ mls(v26.V8B(), v13.V8B(), v23.V8B());
+  __ mls(v10.V8H(), v10.V8H(), v12.V8H());
+  __ mls(v14.V8H(), v0.V8H(), v14.H(), 7);
+  __ mov(b22, v1.B(), 3);
+  __ mov(d7, v13.D(), 1);
+  __ mov(h26, v21.H(), 2);
+  __ mov(s26, v19.S(), 0);
+  __ mov(v26.V16B(), v11.V16B());
+  __ mov(v20.V8B(), v0.V8B());
+  __ mov(v19.B(), 13, v6.B(), 4);
+  __ mov(v4.B(), 13, w19);
+  __ mov(v11.D(), 1, v8.D(), 0);
+  __ mov(v3.D(), 0, x30);
+  __ mov(v29.H(), 4, v11.H(), 7);
+  __ mov(v2.H(), 6, w6);
+  __ mov(v22.S(), 0, v5.S(), 2);
+  __ mov(v24.S(), 3, w8);
+  __ mov(w18, v1.S(), 3);
+  __ mov(x28, v21.D(), 0);
+  __ movi(d24, 0xffff0000ffffff);
+  __ movi(v29.V16B(), 0x80);
+  __ movi(v12.V2D(), 0xffff00ff00ffff00);
+  __ movi(v12.V2S(), 0xec, LSL, 24);
+  __ movi(v10.V2S(), 0x4c, MSL, 16);
+  __ movi(v26.V4H(), 0xc0, LSL);
+  __ movi(v24.V4S(), 0x98, LSL, 16);
+  __ movi(v1.V4S(), 0xde, MSL, 16);
+  __ movi(v21.V8B(), 0x4d);
+  __ movi(v29.V8H(), 0x69, LSL);
+  __ mul(v1.V16B(), v15.V16B(), v17.V16B());
+  __ mul(v21.V2S(), v19.V2S(), v29.V2S());
+  __ mul(v19.V2S(), v5.V2S(), v3.S(), 0);
+  __ mul(v29.V4H(), v11.V4H(), v2.V4H());
+  __ mul(v2.V4H(), v7.V4H(), v0.H(), 0);
+  __ mul(v25.V4S(), v26.V4S(), v16.V4S());
+  __ mul(v26.V4S(), v6.V4S(), v15.S(), 2);
+  __ mul(v11.V8B(), v15.V8B(), v31.V8B());
+  __ mul(v20.V8H(), v31.V8H(), v15.V8H());
+  __ mul(v29.V8H(), v5.V8H(), v9.H(), 4);
+  __ mvn(v13.V16B(), v21.V16B());
+  __ mvn(v28.V8B(), v19.V8B());
+  __ mvni(v25.V2S(), 0xb8, LSL, 8);
+  __ mvni(v17.V2S(), 0x6c, MSL, 16);
+  __ mvni(v29.V4H(), 0x48, LSL);
+  __ mvni(v20.V4S(), 0x7a, LSL, 16);
+  __ mvni(v0.V4S(), 0x1e, MSL, 8);
+  __ mvni(v31.V8H(), 0x3e, LSL);
+  __ neg(d25, d11);
+  __ neg(v4.V16B(), v9.V16B());
+  __ neg(v11.V2D(), v25.V2D());
+  __ neg(v7.V2S(), v18.V2S());
+  __ neg(v7.V4H(), v15.V4H());
+  __ neg(v17.V4S(), v18.V4S());
+  __ neg(v20.V8B(), v17.V8B());
+  __ neg(v0.V8H(), v11.V8H());
+  __ orn(v13.V16B(), v11.V16B(), v31.V16B());
+  __ orn(v22.V8B(), v16.V8B(), v22.V8B());
+  __ orr(v17.V16B(), v17.V16B(), v23.V16B());
+  __ orr(v8.V2S(), 0xe3);
+  __ orr(v11.V4H(), 0x97, 8);
+  __ orr(v7.V4S(), 0xab);
+  __ orr(v8.V8B(), v4.V8B(), v3.V8B());
+  __ orr(v31.V8H(), 0xb0, 8);
+  __ pmul(v11.V16B(), v18.V16B(), v23.V16B());
+  __ pmul(v8.V8B(), v24.V8B(), v5.V8B());
+  __ pmull(v24.V8H(), v18.V8B(), v22.V8B());
+  __ pmull2(v13.V8H(), v3.V16B(), v21.V16B());
+  __ raddhn(v22.V2S(), v10.V2D(), v21.V2D());
+  __ raddhn(v5.V4H(), v13.V4S(), v13.V4S());
+  __ raddhn(v10.V8B(), v17.V8H(), v26.V8H());
+  __ raddhn2(v9.V16B(), v29.V8H(), v13.V8H());
+  __ raddhn2(v27.V4S(), v23.V2D(), v26.V2D());
+  __ raddhn2(v0.V8H(), v29.V4S(), v7.V4S());
+  __ rbit(v22.V16B(), v15.V16B());
+  __ rbit(v30.V8B(), v3.V8B());
+  __ rev16(v31.V16B(), v27.V16B());
+  __ rev16(v12.V8B(), v26.V8B());
+  __ rev32(v5.V16B(), v4.V16B());
+  __ rev32(v16.V4H(), v26.V4H());
+  __ rev32(v20.V8B(), v3.V8B());
+  __ rev32(v20.V8H(), v28.V8H());
+  __ rev64(v9.V16B(), v19.V16B());
+  __ rev64(v5.V2S(), v16.V2S());
+  __ rev64(v7.V4H(), v31.V4H());
+  __ rev64(v15.V4S(), v26.V4S());
+  __ rev64(v25.V8B(), v9.V8B());
+  __ rev64(v11.V8H(), v5.V8H());
+  __ rshrn(v18.V2S(), v13.V2D(), 1);
+  __ rshrn(v25.V4H(), v30.V4S(), 2);
+  __ rshrn(v13.V8B(), v9.V8H(), 8);
+  __ rshrn2(v3.V16B(), v6.V8H(), 8);
+  __ rshrn2(v0.V4S(), v29.V2D(), 25);
+  __ rshrn2(v27.V8H(), v26.V4S(), 15);
+  __ rsubhn(v15.V2S(), v25.V2D(), v4.V2D());
+  __ rsubhn(v23.V4H(), v9.V4S(), v3.V4S());
+  __ rsubhn(v6.V8B(), v30.V8H(), v24.V8H());
+  __ rsubhn2(v4.V16B(), v24.V8H(), v20.V8H());
+  __ rsubhn2(v1.V4S(), v23.V2D(), v22.V2D());
+  __ rsubhn2(v19.V8H(), v2.V4S(), v20.V4S());
+  __ saba(v28.V16B(), v9.V16B(), v25.V16B());
+  __ saba(v9.V2S(), v28.V2S(), v20.V2S());
+  __ saba(v17.V4H(), v22.V4H(), v22.V4H());
+  __ saba(v29.V4S(), v5.V4S(), v27.V4S());
+  __ saba(v20.V8B(), v21.V8B(), v18.V8B());
+  __ saba(v27.V8H(), v17.V8H(), v30.V8H());
+  __ sabal(v20.V2D(), v13.V2S(), v7.V2S());
+  __ sabal(v4.V4S(), v12.V4H(), v4.V4H());
+  __ sabal(v23.V8H(), v24.V8B(), v20.V8B());
+  __ sabal2(v26.V2D(), v21.V4S(), v18.V4S());
+  __ sabal2(v27.V4S(), v28.V8H(), v8.V8H());
+  __ sabal2(v12.V8H(), v16.V16B(), v21.V16B());
+  __ sabd(v0.V16B(), v15.V16B(), v13.V16B());
+  __ sabd(v15.V2S(), v7.V2S(), v30.V2S());
+  __ sabd(v17.V4H(), v17.V4H(), v12.V4H());
+  __ sabd(v7.V4S(), v4.V4S(), v22.V4S());
+  __ sabd(v23.V8B(), v3.V8B(), v26.V8B());
+  __ sabd(v20.V8H(), v28.V8H(), v5.V8H());
+  __ sabdl(v27.V2D(), v22.V2S(), v20.V2S());
+  __ sabdl(v31.V4S(), v20.V4H(), v23.V4H());
+  __ sabdl(v0.V8H(), v20.V8B(), v27.V8B());
+  __ sabdl2(v31.V2D(), v11.V4S(), v3.V4S());
+  __ sabdl2(v26.V4S(), v11.V8H(), v27.V8H());
+  __ sabdl2(v6.V8H(), v8.V16B(), v18.V16B());
+  __ sadalp(v8.V1D(), v26.V2S());
+  __ sadalp(v12.V2D(), v26.V4S());
+  __ sadalp(v12.V2S(), v26.V4H());
+  __ sadalp(v4.V4H(), v1.V8B());
+  __ sadalp(v15.V4S(), v17.V8H());
+  __ sadalp(v21.V8H(), v25.V16B());
+  __ saddl(v5.V2D(), v10.V2S(), v14.V2S());
+  __ saddl(v18.V4S(), v3.V4H(), v15.V4H());
+  __ saddl(v15.V8H(), v2.V8B(), v23.V8B());
+  __ saddl2(v16.V2D(), v16.V4S(), v27.V4S());
+  __ saddl2(v6.V4S(), v24.V8H(), v0.V8H());
+  __ saddl2(v7.V8H(), v20.V16B(), v28.V16B());
+  __ saddlp(v10.V1D(), v25.V2S());
+  __ saddlp(v15.V2D(), v16.V4S());
+  __ saddlp(v18.V2S(), v10.V4H());
+  __ saddlp(v29.V4H(), v26.V8B());
+  __ saddlp(v10.V4S(), v1.V8H());
+  __ saddlp(v0.V8H(), v21.V16B());
+  __ saddlv(d12, v7.V4S());
+  __ saddlv(h14, v28.V16B());
+  __ saddlv(h30, v30.V8B());
+  __ saddlv(s27, v3.V4H());
+  __ saddlv(s16, v16.V8H());
+  __ saddw(v24.V2D(), v11.V2D(), v18.V2S());
+  __ saddw(v13.V4S(), v12.V4S(), v6.V4H());
+  __ saddw(v19.V8H(), v19.V8H(), v7.V8B());
+  __ saddw2(v27.V2D(), v9.V2D(), v26.V4S());
+  __ saddw2(v19.V4S(), v23.V4S(), v21.V8H());
+  __ saddw2(v15.V8H(), v25.V8H(), v30.V16B());
+  __ shadd(v7.V16B(), v4.V16B(), v9.V16B());
+  __ shadd(v29.V2S(), v25.V2S(), v24.V2S());
+  __ shadd(v31.V4H(), v10.V4H(), v13.V4H());
+  __ shadd(v21.V4S(), v16.V4S(), v8.V4S());
+  __ shadd(v14.V8B(), v29.V8B(), v22.V8B());
+  __ shadd(v19.V8H(), v24.V8H(), v20.V8H());
+  __ shl(d22, d25, 23);
+  __ shl(v5.V16B(), v17.V16B(), 7);
+  __ shl(v2.V2D(), v4.V2D(), 21);
+  __ shl(v4.V2S(), v3.V2S(), 26);
+  __ shl(v3.V4H(), v28.V4H(), 8);
+  __ shl(v4.V4S(), v31.V4S(), 24);
+  __ shl(v18.V8B(), v16.V8B(), 2);
+  __ shl(v0.V8H(), v11.V8H(), 3);
+  __ shll(v5.V2D(), v24.V2S(), 32);
+  __ shll(v26.V4S(), v20.V4H(), 16);
+  __ shll(v5.V8H(), v9.V8B(), 8);
+  __ shll2(v21.V2D(), v28.V4S(), 32);
+  __ shll2(v22.V4S(), v1.V8H(), 16);
+  __ shll2(v30.V8H(), v25.V16B(), 8);
+  __ shrn(v5.V2S(), v1.V2D(), 28);
+  __ shrn(v29.V4H(), v18.V4S(), 7);
+  __ shrn(v17.V8B(), v29.V8H(), 2);
+  __ shrn2(v5.V16B(), v30.V8H(), 3);
+  __ shrn2(v24.V4S(), v1.V2D(), 1);
+  __ shrn2(v5.V8H(), v14.V4S(), 16);
+  __ shsub(v30.V16B(), v22.V16B(), v23.V16B());
+  __ shsub(v22.V2S(), v27.V2S(), v25.V2S());
+  __ shsub(v13.V4H(), v22.V4H(), v1.V4H());
+  __ shsub(v10.V4S(), v8.V4S(), v23.V4S());
+  __ shsub(v6.V8B(), v9.V8B(), v31.V8B());
+  __ shsub(v8.V8H(), v31.V8H(), v8.V8H());
+  __ sli(d19, d29, 20);
+  __ sli(v9.V16B(), v24.V16B(), 0);
+  __ sli(v22.V2D(), v9.V2D(), 10);
+  __ sli(v11.V2S(), v27.V2S(), 20);
+  __ sli(v16.V4H(), v15.V4H(), 5);
+  __ sli(v8.V4S(), v8.V4S(), 25);
+  __ sli(v10.V8B(), v30.V8B(), 0);
+  __ sli(v7.V8H(), v28.V8H(), 6);
+  __ smax(v18.V16B(), v8.V16B(), v1.V16B());
+  __ smax(v30.V2S(), v5.V2S(), v1.V2S());
+  __ smax(v17.V4H(), v25.V4H(), v19.V4H());
+  __ smax(v1.V4S(), v24.V4S(), v31.V4S());
+  __ smax(v17.V8B(), v24.V8B(), v24.V8B());
+  __ smax(v11.V8H(), v26.V8H(), v10.V8H());
+  __ smaxp(v12.V16B(), v14.V16B(), v7.V16B());
+  __ smaxp(v31.V2S(), v24.V2S(), v6.V2S());
+  __ smaxp(v10.V4H(), v29.V4H(), v10.V4H());
+  __ smaxp(v18.V4S(), v11.V4S(), v7.V4S());
+  __ smaxp(v21.V8B(), v0.V8B(), v18.V8B());
+  __ smaxp(v26.V8H(), v8.V8H(), v15.V8H());
+  __ smaxv(b4, v5.V16B());
+  __ smaxv(b23, v0.V8B());
+  __ smaxv(h6, v0.V4H());
+  __ smaxv(h24, v8.V8H());
+  __ smaxv(s3, v16.V4S());
+  __ smin(v24.V16B(), v8.V16B(), v18.V16B());
+  __ smin(v29.V2S(), v8.V2S(), v23.V2S());
+  __ smin(v6.V4H(), v11.V4H(), v21.V4H());
+  __ smin(v24.V4S(), v23.V4S(), v15.V4S());
+  __ smin(v8.V8B(), v16.V8B(), v4.V8B());
+  __ smin(v12.V8H(), v1.V8H(), v10.V8H());
+  __ sminp(v13.V16B(), v18.V16B(), v28.V16B());
+  __ sminp(v22.V2S(), v28.V2S(), v16.V2S());
+  __ sminp(v15.V4H(), v12.V4H(), v5.V4H());
+  __ sminp(v15.V4S(), v17.V4S(), v8.V4S());
+  __ sminp(v21.V8B(), v2.V8B(), v6.V8B());
+  __ sminp(v21.V8H(), v12.V8H(), v6.V8H());
+  __ sminv(b8, v6.V16B());
+  __ sminv(b6, v18.V8B());
+  __ sminv(h20, v1.V4H());
+  __ sminv(h7, v17.V8H());
+  __ sminv(s21, v4.V4S());
+  __ smlal(v24.V2D(), v14.V2S(), v21.V2S());
+  __ smlal(v31.V2D(), v3.V2S(), v14.S(), 2);
+  __ smlal(v7.V4S(), v20.V4H(), v21.V4H());
+  __ smlal(v19.V4S(), v16.V4H(), v9.H(), 3);
+  __ smlal(v29.V8H(), v14.V8B(), v1.V8B());
+  __ smlal2(v30.V2D(), v26.V4S(), v16.V4S());
+  __ smlal2(v31.V2D(), v30.V4S(), v1.S(), 0);
+  __ smlal2(v17.V4S(), v6.V8H(), v3.V8H());
+  __ smlal2(v11.V4S(), v31.V8H(), v5.H(), 7);
+  __ smlal2(v30.V8H(), v16.V16B(), v29.V16B());
+  __ smlsl(v1.V2D(), v20.V2S(), v17.V2S());
+  __ smlsl(v29.V2D(), v12.V2S(), v5.S(), 3);
+  __ smlsl(v0.V4S(), v26.V4H(), v1.V4H());
+  __ smlsl(v3.V4S(), v5.V4H(), v6.H(), 5);
+  __ smlsl(v4.V8H(), v0.V8B(), v26.V8B());
+  __ smlsl2(v14.V2D(), v14.V4S(), v5.V4S());
+  __ smlsl2(v15.V2D(), v5.V4S(), v0.S(), 1);
+  __ smlsl2(v29.V4S(), v17.V8H(), v31.V8H());
+  __ smlsl2(v6.V4S(), v15.V8H(), v9.H(), 6);
+  __ smlsl2(v30.V8H(), v15.V16B(), v15.V16B());
+  __ smov(w21, v6.B(), 3);
+  __ smov(w13, v26.H(), 7);
+  __ smov(x24, v16.B(), 7);
+  __ smov(x7, v4.H(), 3);
+  __ smov(x29, v7.S(), 1);
+  __ smull(v4.V2D(), v29.V2S(), v17.V2S());
+  __ smull(v30.V2D(), v21.V2S(), v6.S(), 2);
+  __ smull(v23.V4S(), v5.V4H(), v23.V4H());
+  __ smull(v8.V4S(), v9.V4H(), v2.H(), 1);
+  __ smull(v31.V8H(), v17.V8B(), v1.V8B());
+  __ smull2(v3.V2D(), v3.V4S(), v23.V4S());
+  __ smull2(v15.V2D(), v29.V4S(), v6.S(), 1);
+  __ smull2(v19.V4S(), v20.V8H(), v30.V8H());
+  __ smull2(v6.V4S(), v10.V8H(), v7.H(), 4);
+  __ smull2(v25.V8H(), v8.V16B(), v27.V16B());
+  __ sqabs(b3, b15);
+  __ sqabs(d14, d9);
+  __ sqabs(h31, h28);
+  __ sqabs(s8, s0);
+  __ sqabs(v14.V16B(), v7.V16B());
+  __ sqabs(v23.V2D(), v19.V2D());
+  __ sqabs(v10.V2S(), v24.V2S());
+  __ sqabs(v31.V4H(), v19.V4H());
+  __ sqabs(v23.V4S(), v0.V4S());
+  __ sqabs(v29.V8B(), v23.V8B());
+  __ sqabs(v17.V8H(), v21.V8H());
+  __ sqadd(b9, b23, b13);
+  __ sqadd(d2, d25, d26);
+  __ sqadd(h7, h29, h25);
+  __ sqadd(s11, s7, s24);
+  __ sqadd(v20.V16B(), v16.V16B(), v29.V16B());
+  __ sqadd(v23.V2D(), v30.V2D(), v28.V2D());
+  __ sqadd(v8.V2S(), v19.V2S(), v2.V2S());
+  __ sqadd(v20.V4H(), v12.V4H(), v31.V4H());
+  __ sqadd(v14.V4S(), v15.V4S(), v17.V4S());
+  __ sqadd(v2.V8B(), v29.V8B(), v13.V8B());
+  __ sqadd(v7.V8H(), v19.V8H(), v14.V8H());
+  __ sqdmlal(d15, s5, s30);
+  __ sqdmlal(d24, s10, v2.S(), 3);
+  __ sqdmlal(s9, h19, h8);
+  __ sqdmlal(s14, h1, v12.H(), 3);
+  __ sqdmlal(v30.V2D(), v5.V2S(), v31.V2S());
+  __ sqdmlal(v25.V2D(), v14.V2S(), v10.S(), 1);
+  __ sqdmlal(v19.V4S(), v17.V4H(), v16.V4H());
+  __ sqdmlal(v8.V4S(), v5.V4H(), v8.H(), 1);
+  __ sqdmlal2(v1.V2D(), v23.V4S(), v3.V4S());
+  __ sqdmlal2(v19.V2D(), v0.V4S(), v9.S(), 0);
+  __ sqdmlal2(v26.V4S(), v22.V8H(), v11.V8H());
+  __ sqdmlal2(v6.V4S(), v28.V8H(), v13.H(), 4);
+  __ sqdmlsl(d10, s29, s20);
+  __ sqdmlsl(d10, s9, v10.S(), 1);
+  __ sqdmlsl(s30, h9, h24);
+  __ sqdmlsl(s13, h24, v6.H(), 1);
+  __ sqdmlsl(v27.V2D(), v10.V2S(), v20.V2S());
+  __ sqdmlsl(v23.V2D(), v23.V2S(), v3.S(), 3);
+  __ sqdmlsl(v7.V4S(), v17.V4H(), v29.V4H());
+  __ sqdmlsl(v22.V4S(), v21.V4H(), v3.H(), 4);
+  __ sqdmlsl2(v12.V2D(), v7.V4S(), v22.V4S());
+  __ sqdmlsl2(v20.V2D(), v25.V4S(), v8.S(), 0);
+  __ sqdmlsl2(v25.V4S(), v26.V8H(), v18.V8H());
+  __ sqdmlsl2(v25.V4S(), v19.V8H(), v5.H(), 0);
+  __ sqdmulh(h17, h27, h12);
+  __ sqdmulh(h16, h5, v11.H(), 0);
+  __ sqdmulh(s1, s19, s16);
+  __ sqdmulh(s1, s16, v2.S(), 0);
+  __ sqdmulh(v28.V2S(), v1.V2S(), v8.V2S());
+  __ sqdmulh(v28.V2S(), v8.V2S(), v3.S(), 0);
+  __ sqdmulh(v11.V4H(), v25.V4H(), v5.V4H());
+  __ sqdmulh(v30.V4H(), v14.V4H(), v8.H(), 5);
+  __ sqdmulh(v25.V4S(), v21.V4S(), v13.V4S());
+  __ sqdmulh(v23.V4S(), v2.V4S(), v10.S(), 3);
+  __ sqdmulh(v26.V8H(), v5.V8H(), v23.V8H());
+  __ sqdmulh(v4.V8H(), v22.V8H(), v4.H(), 3);
+  __ sqdmull(d25, s2, s26);
+  __ sqdmull(d30, s14, v5.S(), 1);
+  __ sqdmull(s29, h18, h11);
+  __ sqdmull(s11, h13, v7.H(), 6);
+  __ sqdmull(v23.V2D(), v9.V2S(), v8.V2S());
+  __ sqdmull(v18.V2D(), v29.V2S(), v4.S(), 1);
+  __ sqdmull(v17.V4S(), v24.V4H(), v7.V4H());
+  __ sqdmull(v8.V4S(), v15.V4H(), v5.H(), 1);
+  __ sqdmull2(v28.V2D(), v14.V4S(), v2.V4S());
+  __ sqdmull2(v1.V2D(), v24.V4S(), v13.S(), 2);
+  __ sqdmull2(v11.V4S(), v17.V8H(), v31.V8H());
+  __ sqdmull2(v1.V4S(), v20.V8H(), v11.H(), 3);
+  __ sqneg(b2, b0);
+  __ sqneg(d24, d2);
+  __ sqneg(h29, h3);
+  __ sqneg(s4, s9);
+  __ sqneg(v14.V16B(), v29.V16B());
+  __ sqneg(v30.V2D(), v12.V2D());
+  __ sqneg(v28.V2S(), v26.V2S());
+  __ sqneg(v4.V4H(), v4.V4H());
+  __ sqneg(v9.V4S(), v8.V4S());
+  __ sqneg(v20.V8B(), v20.V8B());
+  __ sqneg(v27.V8H(), v10.V8H());
+  __ sqrdmulh(h7, h24, h0);
+  __ sqrdmulh(h14, h3, v4.H(), 6);
+  __ sqrdmulh(s27, s19, s24);
+  __ sqrdmulh(s31, s21, v4.S(), 0);
+  __ sqrdmulh(v18.V2S(), v25.V2S(), v1.V2S());
+  __ sqrdmulh(v22.V2S(), v5.V2S(), v13.S(), 0);
+  __ sqrdmulh(v22.V4H(), v24.V4H(), v9.V4H());
+  __ sqrdmulh(v13.V4H(), v2.V4H(), v12.H(), 6);
+  __ sqrdmulh(v9.V4S(), v27.V4S(), v2.V4S());
+  __ sqrdmulh(v3.V4S(), v23.V4S(), v7.S(), 1);
+  __ sqrdmulh(v2.V8H(), v0.V8H(), v7.V8H());
+  __ sqrdmulh(v16.V8H(), v9.V8H(), v8.H(), 2);
+  __ sqrshl(b8, b21, b13);
+  __ sqrshl(d29, d7, d20);
+  __ sqrshl(h28, h14, h10);
+  __ sqrshl(s26, s18, s2);
+  __ sqrshl(v18.V16B(), v31.V16B(), v26.V16B());
+  __ sqrshl(v28.V2D(), v4.V2D(), v0.V2D());
+  __ sqrshl(v3.V2S(), v6.V2S(), v0.V2S());
+  __ sqrshl(v1.V4H(), v18.V4H(), v22.V4H());
+  __ sqrshl(v16.V4S(), v25.V4S(), v7.V4S());
+  __ sqrshl(v0.V8B(), v21.V8B(), v5.V8B());
+  __ sqrshl(v30.V8H(), v19.V8H(), v8.V8H());
+  __ sqrshrn(b6, h21, 4);
+  __ sqrshrn(h14, s17, 11);
+  __ sqrshrn(s25, d27, 10);
+  __ sqrshrn(v6.V2S(), v13.V2D(), 18);
+  __ sqrshrn(v5.V4H(), v9.V4S(), 15);
+  __ sqrshrn(v19.V8B(), v12.V8H(), 1);
+  __ sqrshrn2(v19.V16B(), v21.V8H(), 7);
+  __ sqrshrn2(v29.V4S(), v24.V2D(), 13);
+  __ sqrshrn2(v12.V8H(), v2.V4S(), 10);
+  __ sqrshrun(b16, h9, 5);
+  __ sqrshrun(h3, s24, 15);
+  __ sqrshrun(s16, d18, 8);
+  __ sqrshrun(v28.V2S(), v23.V2D(), 8);
+  __ sqrshrun(v31.V4H(), v25.V4S(), 10);
+  __ sqrshrun(v19.V8B(), v23.V8H(), 2);
+  __ sqrshrun2(v24.V16B(), v0.V8H(), 8);
+  __ sqrshrun2(v22.V4S(), v1.V2D(), 23);
+  __ sqrshrun2(v28.V8H(), v21.V4S(), 13);
+  __ sqshl(b6, b21, b8);
+  __ sqshl(b11, b26, 2);
+  __ sqshl(d29, d0, d4);
+  __ sqshl(d21, d7, 35);
+  __ sqshl(h20, h25, h17);
+  __ sqshl(h20, h0, 8);
+  __ sqshl(s29, s13, s4);
+  __ sqshl(s10, s11, 20);
+  __ sqshl(v8.V16B(), v18.V16B(), v28.V16B());
+  __ sqshl(v29.V16B(), v29.V16B(), 2);
+  __ sqshl(v8.V2D(), v31.V2D(), v16.V2D());
+  __ sqshl(v7.V2D(), v14.V2D(), 37);
+  __ sqshl(v0.V2S(), v26.V2S(), v7.V2S());
+  __ sqshl(v5.V2S(), v11.V2S(), 19);
+  __ sqshl(v11.V4H(), v30.V4H(), v0.V4H());
+  __ sqshl(v1.V4H(), v18.V4H(), 7);
+  __ sqshl(v22.V4S(), v3.V4S(), v30.V4S());
+  __ sqshl(v16.V4S(), v15.V4S(), 28);
+  __ sqshl(v6.V8B(), v28.V8B(), v25.V8B());
+  __ sqshl(v0.V8B(), v15.V8B(), 0);
+  __ sqshl(v6.V8H(), v16.V8H(), v30.V8H());
+  __ sqshl(v3.V8H(), v20.V8H(), 14);
+  __ sqshlu(b13, b14, 6);
+  __ sqshlu(d0, d16, 44);
+  __ sqshlu(h5, h29, 15);
+  __ sqshlu(s29, s8, 13);
+  __ sqshlu(v27.V16B(), v20.V16B(), 2);
+  __ sqshlu(v24.V2D(), v12.V2D(), 11);
+  __ sqshlu(v12.V2S(), v19.V2S(), 22);
+  __ sqshlu(v8.V4H(), v12.V4H(), 11);
+  __ sqshlu(v18.V4S(), v3.V4S(), 8);
+  __ sqshlu(v3.V8B(), v10.V8B(), 1);
+  __ sqshlu(v30.V8H(), v24.V8H(), 4);
+  __ sqshrn(b1, h28, 1);
+  __ sqshrn(h31, s7, 10);
+  __ sqshrn(s4, d10, 24);
+  __ sqshrn(v10.V2S(), v1.V2D(), 29);
+  __ sqshrn(v3.V4H(), v13.V4S(), 14);
+  __ sqshrn(v27.V8B(), v6.V8H(), 7);
+  __ sqshrn2(v14.V16B(), v23.V8H(), 1);
+  __ sqshrn2(v25.V4S(), v22.V2D(), 27);
+  __ sqshrn2(v31.V8H(), v12.V4S(), 10);
+  __ sqshrun(b9, h0, 1);
+  __ sqshrun(h11, s6, 7);
+  __ sqshrun(s13, d12, 13);
+  __ sqshrun(v10.V2S(), v30.V2D(), 1);
+  __ sqshrun(v31.V4H(), v3.V4S(), 11);
+  __ sqshrun(v28.V8B(), v30.V8H(), 8);
+  __ sqshrun2(v16.V16B(), v27.V8H(), 3);
+  __ sqshrun2(v27.V4S(), v14.V2D(), 18);
+  __ sqshrun2(v23.V8H(), v14.V4S(), 1);
+  __ sqsub(b19, b29, b11);
+  __ sqsub(d21, d31, d6);
+  __ sqsub(h18, h10, h19);
+  __ sqsub(s6, s5, s0);
+  __ sqsub(v21.V16B(), v22.V16B(), v0.V16B());
+  __ sqsub(v22.V2D(), v10.V2D(), v17.V2D());
+  __ sqsub(v8.V2S(), v21.V2S(), v2.V2S());
+  __ sqsub(v18.V4H(), v25.V4H(), v27.V4H());
+  __ sqsub(v13.V4S(), v3.V4S(), v6.V4S());
+  __ sqsub(v28.V8B(), v29.V8B(), v16.V8B());
+  __ sqsub(v17.V8H(), v6.V8H(), v10.V8H());
+  __ sqxtn(b27, h26);
+  __ sqxtn(h17, s11);
+  __ sqxtn(s22, d31);
+  __ sqxtn(v26.V2S(), v5.V2D());
+  __ sqxtn(v13.V4H(), v7.V4S());
+  __ sqxtn(v19.V8B(), v19.V8H());
+  __ sqxtn2(v19.V16B(), v3.V8H());
+  __ sqxtn2(v23.V4S(), v1.V2D());
+  __ sqxtn2(v13.V8H(), v3.V4S());
+  __ sqxtun(b26, h9);
+  __ sqxtun(h19, s12);
+  __ sqxtun(s3, d6);
+  __ sqxtun(v29.V2S(), v26.V2D());
+  __ sqxtun(v26.V4H(), v10.V4S());
+  __ sqxtun(v7.V8B(), v29.V8H());
+  __ sqxtun2(v21.V16B(), v14.V8H());
+  __ sqxtun2(v24.V4S(), v15.V2D());
+  __ sqxtun2(v30.V8H(), v1.V4S());
+  __ srhadd(v21.V16B(), v17.V16B(), v15.V16B());
+  __ srhadd(v28.V2S(), v21.V2S(), v29.V2S());
+  __ srhadd(v9.V4H(), v1.V4H(), v30.V4H());
+  __ srhadd(v24.V4S(), v0.V4S(), v2.V4S());
+  __ srhadd(v6.V8B(), v17.V8B(), v15.V8B());
+  __ srhadd(v5.V8H(), v7.V8H(), v21.V8H());
+  __ sri(d14, d14, 49);
+  __ sri(v23.V16B(), v8.V16B(), 4);
+  __ sri(v20.V2D(), v13.V2D(), 20);
+  __ sri(v16.V2S(), v2.V2S(), 24);
+  __ sri(v5.V4H(), v23.V4H(), 11);
+  __ sri(v27.V4S(), v15.V4S(), 23);
+  __ sri(v19.V8B(), v29.V8B(), 4);
+  __ sri(v7.V8H(), v29.V8H(), 3);
+  __ srshl(d2, d9, d26);
+  __ srshl(v29.V16B(), v17.V16B(), v11.V16B());
+  __ srshl(v8.V2D(), v15.V2D(), v4.V2D());
+  __ srshl(v25.V2S(), v17.V2S(), v8.V2S());
+  __ srshl(v19.V4H(), v7.V4H(), v7.V4H());
+  __ srshl(v13.V4S(), v2.V4S(), v17.V4S());
+  __ srshl(v22.V8B(), v6.V8B(), v21.V8B());
+  __ srshl(v10.V8H(), v17.V8H(), v4.V8H());
+  __ srshr(d21, d18, 45);
+  __ srshr(v3.V16B(), v11.V16B(), 7);
+  __ srshr(v21.V2D(), v26.V2D(), 53);
+  __ srshr(v11.V2S(), v5.V2S(), 28);
+  __ srshr(v7.V4H(), v18.V4H(), 12);
+  __ srshr(v7.V4S(), v3.V4S(), 30);
+  __ srshr(v14.V8B(), v2.V8B(), 6);
+  __ srshr(v21.V8H(), v20.V8H(), 3);
+  __ srsra(d21, d30, 63);
+  __ srsra(v27.V16B(), v30.V16B(), 6);
+  __ srsra(v20.V2D(), v12.V2D(), 27);
+  __ srsra(v0.V2S(), v17.V2S(), 5);
+  __ srsra(v14.V4H(), v16.V4H(), 15);
+  __ srsra(v18.V4S(), v3.V4S(), 20);
+  __ srsra(v21.V8B(), v1.V8B(), 1);
+  __ srsra(v31.V8H(), v25.V8H(), 2);
+  __ sshl(d1, d13, d9);
+  __ sshl(v17.V16B(), v31.V16B(), v15.V16B());
+  __ sshl(v13.V2D(), v16.V2D(), v0.V2D());
+  __ sshl(v0.V2S(), v7.V2S(), v22.V2S());
+  __ sshl(v23.V4H(), v19.V4H(), v4.V4H());
+  __ sshl(v5.V4S(), v5.V4S(), v11.V4S());
+  __ sshl(v23.V8B(), v27.V8B(), v7.V8B());
+  __ sshl(v29.V8H(), v10.V8H(), v5.V8H());
+  __ sshll(v0.V2D(), v2.V2S(), 23);
+  __ sshll(v11.V4S(), v8.V4H(), 8);
+  __ sshll(v4.V8H(), v29.V8B(), 1);
+  __ sshll2(v10.V2D(), v4.V4S(), 14);
+  __ sshll2(v26.V4S(), v31.V8H(), 6);
+  __ sshll2(v3.V8H(), v26.V16B(), 4);
+  __ sshr(d19, d21, 20);
+  __ sshr(v15.V16B(), v23.V16B(), 5);
+  __ sshr(v17.V2D(), v14.V2D(), 38);
+  __ sshr(v3.V2S(), v29.V2S(), 23);
+  __ sshr(v23.V4H(), v27.V4H(), 4);
+  __ sshr(v28.V4S(), v3.V4S(), 4);
+  __ sshr(v14.V8B(), v2.V8B(), 6);
+  __ sshr(v3.V8H(), v8.V8H(), 6);
+  __ ssra(d12, d28, 44);
+  __ ssra(v29.V16B(), v31.V16B(), 4);
+  __ ssra(v3.V2D(), v0.V2D(), 24);
+  __ ssra(v14.V2S(), v28.V2S(), 6);
+  __ ssra(v18.V4H(), v8.V4H(), 7);
+  __ ssra(v31.V4S(), v14.V4S(), 24);
+  __ ssra(v28.V8B(), v26.V8B(), 5);
+  __ ssra(v9.V8H(), v9.V8H(), 14);
+  __ ssubl(v13.V2D(), v14.V2S(), v3.V2S());
+  __ ssubl(v5.V4S(), v16.V4H(), v8.V4H());
+  __ ssubl(v0.V8H(), v28.V8B(), v6.V8B());
+  __ ssubl2(v5.V2D(), v13.V4S(), v25.V4S());
+  __ ssubl2(v3.V4S(), v15.V8H(), v17.V8H());
+  __ ssubl2(v15.V8H(), v15.V16B(), v14.V16B());
+  __ ssubw(v25.V2D(), v23.V2D(), v26.V2S());
+  __ ssubw(v21.V4S(), v18.V4S(), v24.V4H());
+  __ ssubw(v30.V8H(), v22.V8H(), v3.V8B());
+  __ ssubw2(v16.V2D(), v24.V2D(), v28.V4S());
+  __ ssubw2(v31.V4S(), v11.V4S(), v15.V8H());
+  __ ssubw2(v4.V8H(), v8.V8H(), v16.V16B());
+  __ st1(v18.V16B(), v19.V16B(), v20.V16B(), v21.V16B(), MemOperand(x0));
+  __ st1(v10.V16B(), v11.V16B(), v12.V16B(), v13.V16B(),
+         MemOperand(x1, x2, PostIndex));
+  __ st1(v27.V16B(), v28.V16B(), v29.V16B(), v30.V16B(),
+         MemOperand(x1, 64, PostIndex));
+  __ st1(v16.V16B(), v17.V16B(), v18.V16B(), MemOperand(x0));
+  __ st1(v21.V16B(), v22.V16B(), v23.V16B(), MemOperand(x1, x2, PostIndex));
+  __ st1(v9.V16B(), v10.V16B(), v11.V16B(), MemOperand(x1, 48, PostIndex));
+  __ st1(v7.V16B(), v8.V16B(), MemOperand(x0));
+  __ st1(v26.V16B(), v27.V16B(), MemOperand(x1, x2, PostIndex));
+  __ st1(v22.V16B(), v23.V16B(), MemOperand(x1, 32, PostIndex));
+  __ st1(v23.V16B(), MemOperand(x0));
+  __ st1(v28.V16B(), MemOperand(x1, x2, PostIndex));
+  __ st1(v2.V16B(), MemOperand(x1, 16, PostIndex));
+  __ st1(v29.V1D(), v30.V1D(), v31.V1D(), v0.V1D(), MemOperand(x0));
+  __ st1(v12.V1D(), v13.V1D(), v14.V1D(), v15.V1D(),
+         MemOperand(x1, x2, PostIndex));
+  __ st1(v30.V1D(), v31.V1D(), v0.V1D(), v1.V1D(),
+         MemOperand(x1, 32, PostIndex));
+  __ st1(v16.V1D(), v17.V1D(), v18.V1D(), MemOperand(x0));
+  __ st1(v3.V1D(), v4.V1D(), v5.V1D(), MemOperand(x1, x2, PostIndex));
+  __ st1(v14.V1D(), v15.V1D(), v16.V1D(), MemOperand(x1, 24, PostIndex));
+  __ st1(v18.V1D(), v19.V1D(), MemOperand(x0));
+  __ st1(v5.V1D(), v6.V1D(), MemOperand(x1, x2, PostIndex));
+  __ st1(v2.V1D(), v3.V1D(), MemOperand(x1, 16, PostIndex));
+  __ st1(v4.V1D(), MemOperand(x0));
+  __ st1(v27.V1D(), MemOperand(x1, x2, PostIndex));
+  __ st1(v23.V1D(), MemOperand(x1, 8, PostIndex));
+  __ st1(v2.V2D(), v3.V2D(), v4.V2D(), v5.V2D(), MemOperand(x0));
+  __ st1(v22.V2D(), v23.V2D(), v24.V2D(), v25.V2D(),
+         MemOperand(x1, x2, PostIndex));
+  __ st1(v28.V2D(), v29.V2D(), v30.V2D(), v31.V2D(),
+         MemOperand(x1, 64, PostIndex));
+  __ st1(v17.V2D(), v18.V2D(), v19.V2D(), MemOperand(x0));
+  __ st1(v16.V2D(), v17.V2D(), v18.V2D(), MemOperand(x1, x2, PostIndex));
+  __ st1(v22.V2D(), v23.V2D(), v24.V2D(), MemOperand(x1, 48, PostIndex));
+  __ st1(v21.V2D(), v22.V2D(), MemOperand(x0));
+  __ st1(v6.V2D(), v7.V2D(), MemOperand(x1, x2, PostIndex));
+  __ st1(v27.V2D(), v28.V2D(), MemOperand(x1, 32, PostIndex));
+  __ st1(v21.V2D(), MemOperand(x0));
+  __ st1(v29.V2D(), MemOperand(x1, x2, PostIndex));
+  __ st1(v20.V2D(), MemOperand(x1, 16, PostIndex));
+  __ st1(v22.V2S(), v23.V2S(), v24.V2S(), v25.V2S(), MemOperand(x0));
+  __ st1(v8.V2S(), v9.V2S(), v10.V2S(), v11.V2S(),
+         MemOperand(x1, x2, PostIndex));
+  __ st1(v15.V2S(), v16.V2S(), v17.V2S(), v18.V2S(),
+         MemOperand(x1, 32, PostIndex));
+  __ st1(v2.V2S(), v3.V2S(), v4.V2S(), MemOperand(x0));
+  __ st1(v23.V2S(), v24.V2S(), v25.V2S(), MemOperand(x1, x2, PostIndex));
+  __ st1(v7.V2S(), v8.V2S(), v9.V2S(), MemOperand(x1, 24, PostIndex));
+  __ st1(v28.V2S(), v29.V2S(), MemOperand(x0));
+  __ st1(v29.V2S(), v30.V2S(), MemOperand(x1, x2, PostIndex));
+  __ st1(v23.V2S(), v24.V2S(), MemOperand(x1, 16, PostIndex));
+  __ st1(v6.V2S(), MemOperand(x0));
+  __ st1(v11.V2S(), MemOperand(x1, x2, PostIndex));
+  __ st1(v17.V2S(), MemOperand(x1, 8, PostIndex));
+  __ st1(v6.V4H(), v7.V4H(), v8.V4H(), v9.V4H(), MemOperand(x0));
+  __ st1(v9.V4H(), v10.V4H(), v11.V4H(), v12.V4H(),
+         MemOperand(x1, x2, PostIndex));
+  __ st1(v25.V4H(), v26.V4H(), v27.V4H(), v28.V4H(),
+         MemOperand(x1, 32, PostIndex));
+  __ st1(v11.V4H(), v12.V4H(), v13.V4H(), MemOperand(x0));
+  __ st1(v10.V4H(), v11.V4H(), v12.V4H(), MemOperand(x1, x2, PostIndex));
+  __ st1(v12.V4H(), v13.V4H(), v14.V4H(), MemOperand(x1, 24, PostIndex));
+  __ st1(v13.V4H(), v14.V4H(), MemOperand(x0));
+  __ st1(v15.V4H(), v16.V4H(), MemOperand(x1, x2, PostIndex));
+  __ st1(v21.V4H(), v22.V4H(), MemOperand(x1, 16, PostIndex));
+  __ st1(v16.V4H(), MemOperand(x0));
+  __ st1(v8.V4H(), MemOperand(x1, x2, PostIndex));
+  __ st1(v30.V4H(), MemOperand(x1, 8, PostIndex));
+  __ st1(v3.V4S(), v4.V4S(), v5.V4S(), v6.V4S(), MemOperand(x0));
+  __ st1(v25.V4S(), v26.V4S(), v27.V4S(), v28.V4S(),
+         MemOperand(x1, x2, PostIndex));
+  __ st1(v5.V4S(), v6.V4S(), v7.V4S(), v8.V4S(), MemOperand(x1, 64, PostIndex));
+  __ st1(v31.V4S(), v0.V4S(), v1.V4S(), MemOperand(x0));
+  __ st1(v30.V4S(), v31.V4S(), v0.V4S(), MemOperand(x1, x2, PostIndex));
+  __ st1(v6.V4S(), v7.V4S(), v8.V4S(), MemOperand(x1, 48, PostIndex));
+  __ st1(v17.V4S(), v18.V4S(), MemOperand(x0));
+  __ st1(v31.V4S(), v0.V4S(), MemOperand(x1, x2, PostIndex));
+  __ st1(v1.V4S(), v2.V4S(), MemOperand(x1, 32, PostIndex));
+  __ st1(v26.V4S(), MemOperand(x0));
+  __ st1(v15.V4S(), MemOperand(x1, x2, PostIndex));
+  __ st1(v13.V4S(), MemOperand(x1, 16, PostIndex));
+  __ st1(v26.V8B(), v27.V8B(), v28.V8B(), v29.V8B(), MemOperand(x0));
+  __ st1(v10.V8B(), v11.V8B(), v12.V8B(), v13.V8B(),
+         MemOperand(x1, x2, PostIndex));
+  __ st1(v15.V8B(), v16.V8B(), v17.V8B(), v18.V8B(),
+         MemOperand(x1, 32, PostIndex));
+  __ st1(v19.V8B(), v20.V8B(), v21.V8B(), MemOperand(x0));
+  __ st1(v31.V8B(), v0.V8B(), v1.V8B(), MemOperand(x1, x2, PostIndex));
+  __ st1(v9.V8B(), v10.V8B(), v11.V8B(), MemOperand(x1, 24, PostIndex));
+  __ st1(v12.V8B(), v13.V8B(), MemOperand(x0));
+  __ st1(v2.V8B(), v3.V8B(), MemOperand(x1, x2, PostIndex));
+  __ st1(v0.V8B(), v1.V8B(), MemOperand(x1, 16, PostIndex));
+  __ st1(v16.V8B(), MemOperand(x0));
+  __ st1(v25.V8B(), MemOperand(x1, x2, PostIndex));
+  __ st1(v31.V8B(), MemOperand(x1, 8, PostIndex));
+  __ st1(v4.V8H(), v5.V8H(), v6.V8H(), v7.V8H(), MemOperand(x0));
+  __ st1(v3.V8H(), v4.V8H(), v5.V8H(), v6.V8H(), MemOperand(x1, x2, PostIndex));
+  __ st1(v26.V8H(), v27.V8H(), v28.V8H(), v29.V8H(),
+         MemOperand(x1, 64, PostIndex));
+  __ st1(v10.V8H(), v11.V8H(), v12.V8H(), MemOperand(x0));
+  __ st1(v21.V8H(), v22.V8H(), v23.V8H(), MemOperand(x1, x2, PostIndex));
+  __ st1(v18.V8H(), v19.V8H(), v20.V8H(), MemOperand(x1, 48, PostIndex));
+  __ st1(v26.V8H(), v27.V8H(), MemOperand(x0));
+  __ st1(v24.V8H(), v25.V8H(), MemOperand(x1, x2, PostIndex));
+  __ st1(v17.V8H(), v18.V8H(), MemOperand(x1, 32, PostIndex));
+  __ st1(v29.V8H(), MemOperand(x0));
+  __ st1(v19.V8H(), MemOperand(x1, x2, PostIndex));
+  __ st1(v23.V8H(), MemOperand(x1, 16, PostIndex));
+  __ st1(v19.B(), 15, MemOperand(x0));
+  __ st1(v25.B(), 9, MemOperand(x1, x2, PostIndex));
+  __ st1(v4.B(), 8, MemOperand(x1, 1, PostIndex));
+  __ st1(v13.D(), 0, MemOperand(x0));
+  __ st1(v30.D(), 0, MemOperand(x1, x2, PostIndex));
+  __ st1(v3.D(), 0, MemOperand(x1, 8, PostIndex));
+  __ st1(v22.H(), 0, MemOperand(x0));
+  __ st1(v31.H(), 7, MemOperand(x1, x2, PostIndex));
+  __ st1(v23.H(), 3, MemOperand(x1, 2, PostIndex));
+  __ st1(v0.S(), 0, MemOperand(x0));
+  __ st1(v11.S(), 3, MemOperand(x1, x2, PostIndex));
+  __ st1(v24.S(), 3, MemOperand(x1, 4, PostIndex));
+  __ st2(v7.V16B(), v8.V16B(), MemOperand(x0));
+  __ st2(v5.V16B(), v6.V16B(), MemOperand(x1, x2, PostIndex));
+  __ st2(v18.V16B(), v19.V16B(), MemOperand(x1, 32, PostIndex));
+  __ st2(v14.V2D(), v15.V2D(), MemOperand(x0));
+  __ st2(v7.V2D(), v8.V2D(), MemOperand(x1, x2, PostIndex));
+  __ st2(v24.V2D(), v25.V2D(), MemOperand(x1, 32, PostIndex));
+  __ st2(v22.V2S(), v23.V2S(), MemOperand(x0));
+  __ st2(v4.V2S(), v5.V2S(), MemOperand(x1, x2, PostIndex));
+  __ st2(v2.V2S(), v3.V2S(), MemOperand(x1, 16, PostIndex));
+  __ st2(v23.V4H(), v24.V4H(), MemOperand(x0));
+  __ st2(v8.V4H(), v9.V4H(), MemOperand(x1, x2, PostIndex));
+  __ st2(v7.V4H(), v8.V4H(), MemOperand(x1, 16, PostIndex));
+  __ st2(v17.V4S(), v18.V4S(), MemOperand(x0));
+  __ st2(v6.V4S(), v7.V4S(), MemOperand(x1, x2, PostIndex));
+  __ st2(v26.V4S(), v27.V4S(), MemOperand(x1, 32, PostIndex));
+  __ st2(v31.V8B(), v0.V8B(), MemOperand(x0));
+  __ st2(v0.V8B(), v1.V8B(), MemOperand(x1, x2, PostIndex));
+  __ st2(v21.V8B(), v22.V8B(), MemOperand(x1, 16, PostIndex));
+  __ st2(v7.V8H(), v8.V8H(), MemOperand(x0));
+  __ st2(v22.V8H(), v23.V8H(), MemOperand(x1, x2, PostIndex));
+  __ st2(v4.V8H(), v5.V8H(), MemOperand(x1, 32, PostIndex));
+  __ st2(v8.B(), v9.B(), 15, MemOperand(x0));
+  __ st2(v8.B(), v9.B(), 15, MemOperand(x1, x2, PostIndex));
+  __ st2(v7.B(), v8.B(), 4, MemOperand(x1, 2, PostIndex));
+  __ st2(v25.D(), v26.D(), 0, MemOperand(x0));
+  __ st2(v17.D(), v18.D(), 1, MemOperand(x1, x2, PostIndex));
+  __ st2(v3.D(), v4.D(), 1, MemOperand(x1, 16, PostIndex));
+  __ st2(v4.H(), v5.H(), 3, MemOperand(x0));
+  __ st2(v0.H(), v1.H(), 5, MemOperand(x1, x2, PostIndex));
+  __ st2(v22.H(), v23.H(), 2, MemOperand(x1, 4, PostIndex));
+  __ st2(v14.S(), v15.S(), 3, MemOperand(x0));
+  __ st2(v23.S(), v24.S(), 3, MemOperand(x1, x2, PostIndex));
+  __ st2(v0.S(), v1.S(), 2, MemOperand(x1, 8, PostIndex));
+  __ st3(v26.V16B(), v27.V16B(), v28.V16B(), MemOperand(x0));
+  __ st3(v21.V16B(), v22.V16B(), v23.V16B(), MemOperand(x1, x2, PostIndex));
+  __ st3(v24.V16B(), v25.V16B(), v26.V16B(), MemOperand(x1, 48, PostIndex));
+  __ st3(v17.V2D(), v18.V2D(), v19.V2D(), MemOperand(x0));
+  __ st3(v23.V2D(), v24.V2D(), v25.V2D(), MemOperand(x1, x2, PostIndex));
+  __ st3(v10.V2D(), v11.V2D(), v12.V2D(), MemOperand(x1, 48, PostIndex));
+  __ st3(v9.V2S(), v10.V2S(), v11.V2S(), MemOperand(x0));
+  __ st3(v13.V2S(), v14.V2S(), v15.V2S(), MemOperand(x1, x2, PostIndex));
+  __ st3(v22.V2S(), v23.V2S(), v24.V2S(), MemOperand(x1, 24, PostIndex));
+  __ st3(v31.V4H(), v0.V4H(), v1.V4H(), MemOperand(x0));
+  __ st3(v8.V4H(), v9.V4H(), v10.V4H(), MemOperand(x1, x2, PostIndex));
+  __ st3(v19.V4H(), v20.V4H(), v21.V4H(), MemOperand(x1, 24, PostIndex));
+  __ st3(v18.V4S(), v19.V4S(), v20.V4S(), MemOperand(x0));
+  __ st3(v25.V4S(), v26.V4S(), v27.V4S(), MemOperand(x1, x2, PostIndex));
+  __ st3(v16.V4S(), v17.V4S(), v18.V4S(), MemOperand(x1, 48, PostIndex));
+  __ st3(v27.V8B(), v28.V8B(), v29.V8B(), MemOperand(x0));
+  __ st3(v29.V8B(), v30.V8B(), v31.V8B(), MemOperand(x1, x2, PostIndex));
+  __ st3(v30.V8B(), v31.V8B(), v0.V8B(), MemOperand(x1, 24, PostIndex));
+  __ st3(v8.V8H(), v9.V8H(), v10.V8H(), MemOperand(x0));
+  __ st3(v18.V8H(), v19.V8H(), v20.V8H(), MemOperand(x1, x2, PostIndex));
+  __ st3(v18.V8H(), v19.V8H(), v20.V8H(), MemOperand(x1, 48, PostIndex));
+  __ st3(v31.B(), v0.B(), v1.B(), 10, MemOperand(x0));
+  __ st3(v4.B(), v5.B(), v6.B(), 5, MemOperand(x1, x2, PostIndex));
+  __ st3(v5.B(), v6.B(), v7.B(), 1, MemOperand(x1, 3, PostIndex));
+  __ st3(v5.D(), v6.D(), v7.D(), 0, MemOperand(x0));
+  __ st3(v6.D(), v7.D(), v8.D(), 0, MemOperand(x1, x2, PostIndex));
+  __ st3(v0.D(), v1.D(), v2.D(), 0, MemOperand(x1, 24, PostIndex));
+  __ st3(v31.H(), v0.H(), v1.H(), 2, MemOperand(x0));
+  __ st3(v14.H(), v15.H(), v16.H(), 5, MemOperand(x1, x2, PostIndex));
+  __ st3(v21.H(), v22.H(), v23.H(), 6, MemOperand(x1, 6, PostIndex));
+  __ st3(v21.S(), v22.S(), v23.S(), 0, MemOperand(x0));
+  __ st3(v11.S(), v12.S(), v13.S(), 1, MemOperand(x1, x2, PostIndex));
+  __ st3(v15.S(), v16.S(), v17.S(), 0, MemOperand(x1, 12, PostIndex));
+  __ st4(v22.V16B(), v23.V16B(), v24.V16B(), v25.V16B(), MemOperand(x0));
+  __ st4(v24.V16B(), v25.V16B(), v26.V16B(), v27.V16B(),
+         MemOperand(x1, x2, PostIndex));
+  __ st4(v15.V16B(), v16.V16B(), v17.V16B(), v18.V16B(),
+         MemOperand(x1, 64, PostIndex));
+  __ st4(v16.V2D(), v17.V2D(), v18.V2D(), v19.V2D(), MemOperand(x0));
+  __ st4(v17.V2D(), v18.V2D(), v19.V2D(), v20.V2D(),
+         MemOperand(x1, x2, PostIndex));
+  __ st4(v9.V2D(), v10.V2D(), v11.V2D(), v12.V2D(),
+         MemOperand(x1, 64, PostIndex));
+  __ st4(v23.V2S(), v24.V2S(), v25.V2S(), v26.V2S(), MemOperand(x0));
+  __ st4(v15.V2S(), v16.V2S(), v17.V2S(), v18.V2S(),
+         MemOperand(x1, x2, PostIndex));
+  __ st4(v24.V2S(), v25.V2S(), v26.V2S(), v27.V2S(),
+         MemOperand(x1, 32, PostIndex));
+  __ st4(v14.V4H(), v15.V4H(), v16.V4H(), v17.V4H(), MemOperand(x0));
+  __ st4(v18.V4H(), v19.V4H(), v20.V4H(), v21.V4H(),
+         MemOperand(x1, x2, PostIndex));
+  __ st4(v1.V4H(), v2.V4H(), v3.V4H(), v4.V4H(), MemOperand(x1, 32, PostIndex));
+  __ st4(v13.V4S(), v14.V4S(), v15.V4S(), v16.V4S(), MemOperand(x0));
+  __ st4(v6.V4S(), v7.V4S(), v8.V4S(), v9.V4S(), MemOperand(x1, x2, PostIndex));
+  __ st4(v15.V4S(), v16.V4S(), v17.V4S(), v18.V4S(),
+         MemOperand(x1, 64, PostIndex));
+  __ st4(v26.V8B(), v27.V8B(), v28.V8B(), v29.V8B(), MemOperand(x0));
+  __ st4(v25.V8B(), v26.V8B(), v27.V8B(), v28.V8B(),
+         MemOperand(x1, x2, PostIndex));
+  __ st4(v19.V8B(), v20.V8B(), v21.V8B(), v22.V8B(),
+         MemOperand(x1, 32, PostIndex));
+  __ st4(v19.V8H(), v20.V8H(), v21.V8H(), v22.V8H(), MemOperand(x0));
+  __ st4(v15.V8H(), v16.V8H(), v17.V8H(), v18.V8H(),
+         MemOperand(x1, x2, PostIndex));
+  __ st4(v31.V8H(), v0.V8H(), v1.V8H(), v2.V8H(),
+         MemOperand(x1, 64, PostIndex));
+  __ st4(v0.B(), v1.B(), v2.B(), v3.B(), 13, MemOperand(x0));
+  __ st4(v4.B(), v5.B(), v6.B(), v7.B(), 10, MemOperand(x1, x2, PostIndex));
+  __ st4(v9.B(), v10.B(), v11.B(), v12.B(), 9, MemOperand(x1, 4, PostIndex));
+  __ st4(v2.D(), v3.D(), v4.D(), v5.D(), 1, MemOperand(x0));
+  __ st4(v7.D(), v8.D(), v9.D(), v10.D(), 0, MemOperand(x1, x2, PostIndex));
+  __ st4(v31.D(), v0.D(), v1.D(), v2.D(), 1, MemOperand(x1, 32, PostIndex));
+  __ st4(v2.H(), v3.H(), v4.H(), v5.H(), 1, MemOperand(x0));
+  __ st4(v27.H(), v28.H(), v29.H(), v30.H(), 3, MemOperand(x1, x2, PostIndex));
+  __ st4(v24.H(), v25.H(), v26.H(), v27.H(), 4, MemOperand(x1, 8, PostIndex));
+  __ st4(v18.S(), v19.S(), v20.S(), v21.S(), 2, MemOperand(x0));
+  __ st4(v6.S(), v7.S(), v8.S(), v9.S(), 2, MemOperand(x1, x2, PostIndex));
+  __ st4(v25.S(), v26.S(), v27.S(), v28.S(), 1, MemOperand(x1, 16, PostIndex));
+  __ sub(d12, d17, d2);
+  __ sub(v20.V16B(), v24.V16B(), v8.V16B());
+  __ sub(v8.V2D(), v29.V2D(), v5.V2D());
+  __ sub(v2.V2S(), v28.V2S(), v24.V2S());
+  __ sub(v24.V4H(), v10.V4H(), v4.V4H());
+  __ sub(v28.V4S(), v4.V4S(), v17.V4S());
+  __ sub(v16.V8B(), v27.V8B(), v2.V8B());
+  __ sub(v20.V8H(), v10.V8H(), v13.V8H());
+  __ subhn(v5.V2S(), v14.V2D(), v13.V2D());
+  __ subhn(v10.V4H(), v5.V4S(), v8.V4S());
+  __ subhn(v6.V8B(), v10.V8H(), v22.V8H());
+  __ subhn2(v11.V16B(), v6.V8H(), v9.V8H());
+  __ subhn2(v25.V4S(), v18.V2D(), v24.V2D());
+  __ subhn2(v20.V8H(), v21.V4S(), v1.V4S());
+  __ suqadd(b25, b11);
+  __ suqadd(d13, d1);
+  __ suqadd(h0, h9);
+  __ suqadd(s22, s8);
+  __ suqadd(v24.V16B(), v27.V16B());
+  __ suqadd(v26.V2D(), v14.V2D());
+  __ suqadd(v7.V2S(), v10.V2S());
+  __ suqadd(v25.V4H(), v12.V4H());
+  __ suqadd(v4.V4S(), v3.V4S());
+  __ suqadd(v14.V8B(), v18.V8B());
+  __ suqadd(v31.V8H(), v8.V8H());
+  __ sxtl(v16.V2D(), v20.V2S());
+  __ sxtl(v27.V4S(), v28.V4H());
+  __ sxtl(v0.V8H(), v22.V8B());
+  __ sxtl2(v6.V2D(), v7.V4S());
+  __ sxtl2(v9.V4S(), v27.V8H());
+  __ sxtl2(v16.V8H(), v16.V16B());
+  __ tbl(v25.V16B(), v17.V16B(), v18.V16B(), v19.V16B(), v20.V16B(),
+         v22.V16B());
+  __ tbl(v28.V16B(), v13.V16B(), v14.V16B(), v15.V16B(), v4.V16B());
+  __ tbl(v3.V16B(), v0.V16B(), v1.V16B(), v2.V16B());
+  __ tbl(v20.V16B(), v15.V16B(), v4.V16B());
+  __ tbl(v7.V8B(), v23.V16B(), v24.V16B(), v25.V16B(), v26.V16B(), v20.V8B());
+  __ tbl(v8.V8B(), v1.V16B(), v2.V16B(), v3.V16B(), v31.V8B());
+  __ tbl(v8.V8B(), v25.V16B(), v26.V16B(), v16.V8B());
+  __ tbl(v11.V8B(), v19.V16B(), v30.V8B());
+  __ tbx(v25.V16B(), v25.V16B(), v26.V16B(), v27.V16B(), v28.V16B(), v5.V16B());
+  __ tbx(v21.V16B(), v29.V16B(), v30.V16B(), v31.V16B(), v24.V16B());
+  __ tbx(v6.V16B(), v16.V16B(), v17.V16B(), v1.V16B());
+  __ tbx(v13.V16B(), v3.V16B(), v20.V16B());
+  __ tbx(v24.V8B(), v29.V16B(), v30.V16B(), v31.V16B(), v0.V16B(), v9.V8B());
+  __ tbx(v17.V8B(), v9.V16B(), v10.V16B(), v11.V16B(), v26.V8B());
+  __ tbx(v5.V8B(), v3.V16B(), v4.V16B(), v21.V8B());
+  __ tbx(v16.V8B(), v11.V16B(), v29.V8B());
+  __ trn1(v19.V16B(), v24.V16B(), v12.V16B());
+  __ trn1(v2.V2D(), v7.V2D(), v10.V2D());
+  __ trn1(v22.V2S(), v0.V2S(), v21.V2S());
+  __ trn1(v12.V4H(), v15.V4H(), v20.V4H());
+  __ trn1(v30.V4S(), v17.V4S(), v9.V4S());
+  __ trn1(v12.V8B(), v19.V8B(), v29.V8B());
+  __ trn1(v23.V8H(), v8.V8H(), v9.V8H());
+  __ trn2(v28.V16B(), v30.V16B(), v25.V16B());
+  __ trn2(v7.V2D(), v27.V2D(), v7.V2D());
+  __ trn2(v30.V2S(), v16.V2S(), v19.V2S());
+  __ trn2(v24.V4H(), v6.V4H(), v25.V4H());
+  __ trn2(v2.V4S(), v19.V4S(), v11.V4S());
+  __ trn2(v25.V8B(), v27.V8B(), v18.V8B());
+  __ trn2(v12.V8H(), v4.V8H(), v15.V8H());
+  __ uaba(v31.V16B(), v12.V16B(), v28.V16B());
+  __ uaba(v18.V2S(), v5.V2S(), v14.V2S());
+  __ uaba(v9.V4H(), v20.V4H(), v21.V4H());
+  __ uaba(v6.V4S(), v20.V4S(), v2.V4S());
+  __ uaba(v16.V8B(), v12.V8B(), v5.V8B());
+  __ uaba(v15.V8H(), v26.V8H(), v30.V8H());
+  __ uabal(v10.V2D(), v18.V2S(), v15.V2S());
+  __ uabal(v30.V4S(), v19.V4H(), v7.V4H());
+  __ uabal(v4.V8H(), v27.V8B(), v0.V8B());
+  __ uabal2(v19.V2D(), v12.V4S(), v2.V4S());
+  __ uabal2(v26.V4S(), v5.V8H(), v12.V8H());
+  __ uabal2(v19.V8H(), v20.V16B(), v28.V16B());
+  __ uabd(v18.V16B(), v4.V16B(), v21.V16B());
+  __ uabd(v30.V2S(), v21.V2S(), v16.V2S());
+  __ uabd(v8.V4H(), v28.V4H(), v25.V4H());
+  __ uabd(v28.V4S(), v12.V4S(), v21.V4S());
+  __ uabd(v19.V8B(), v16.V8B(), v28.V8B());
+  __ uabd(v9.V8H(), v12.V8H(), v29.V8H());
+  __ uabdl(v26.V2D(), v0.V2S(), v8.V2S());
+  __ uabdl(v29.V4S(), v31.V4H(), v25.V4H());
+  __ uabdl(v27.V8H(), v29.V8B(), v14.V8B());
+  __ uabdl2(v20.V2D(), v20.V4S(), v8.V4S());
+  __ uabdl2(v22.V4S(), v15.V8H(), v18.V8H());
+  __ uabdl2(v9.V8H(), v18.V16B(), v23.V16B());
+  __ uadalp(v9.V1D(), v15.V2S());
+  __ uadalp(v14.V2D(), v12.V4S());
+  __ uadalp(v28.V2S(), v12.V4H());
+  __ uadalp(v0.V4H(), v17.V8B());
+  __ uadalp(v1.V4S(), v29.V8H());
+  __ uadalp(v15.V8H(), v22.V16B());
+  __ uaddl(v1.V2D(), v20.V2S(), v27.V2S());
+  __ uaddl(v31.V4S(), v25.V4H(), v5.V4H());
+  __ uaddl(v12.V8H(), v3.V8B(), v3.V8B());
+  __ uaddl2(v5.V2D(), v23.V4S(), v6.V4S());
+  __ uaddl2(v1.V4S(), v5.V8H(), v25.V8H());
+  __ uaddl2(v22.V8H(), v30.V16B(), v28.V16B());
+  __ uaddlp(v7.V1D(), v9.V2S());
+  __ uaddlp(v26.V2D(), v4.V4S());
+  __ uaddlp(v28.V2S(), v1.V4H());
+  __ uaddlp(v20.V4H(), v31.V8B());
+  __ uaddlp(v16.V4S(), v17.V8H());
+  __ uaddlp(v6.V8H(), v2.V16B());
+  __ uaddlv(d28, v22.V4S());
+  __ uaddlv(h0, v19.V16B());
+  __ uaddlv(h30, v30.V8B());
+  __ uaddlv(s24, v18.V4H());
+  __ uaddlv(s10, v0.V8H());
+  __ uaddw(v9.V2D(), v17.V2D(), v14.V2S());
+  __ uaddw(v9.V4S(), v25.V4S(), v3.V4H());
+  __ uaddw(v18.V8H(), v1.V8H(), v0.V8B());
+  __ uaddw2(v18.V2D(), v5.V2D(), v6.V4S());
+  __ uaddw2(v17.V4S(), v15.V4S(), v11.V8H());
+  __ uaddw2(v29.V8H(), v11.V8H(), v7.V16B());
+  __ uhadd(v13.V16B(), v9.V16B(), v3.V16B());
+  __ uhadd(v17.V2S(), v25.V2S(), v24.V2S());
+  __ uhadd(v25.V4H(), v23.V4H(), v13.V4H());
+  __ uhadd(v0.V4S(), v20.V4S(), v16.V4S());
+  __ uhadd(v5.V8B(), v5.V8B(), v25.V8B());
+  __ uhadd(v3.V8H(), v29.V8H(), v18.V8H());
+  __ uhsub(v1.V16B(), v22.V16B(), v13.V16B());
+  __ uhsub(v14.V2S(), v30.V2S(), v30.V2S());
+  __ uhsub(v29.V4H(), v14.V4H(), v17.V4H());
+  __ uhsub(v26.V4S(), v5.V4S(), v18.V4S());
+  __ uhsub(v3.V8B(), v7.V8B(), v12.V8B());
+  __ uhsub(v25.V8H(), v21.V8H(), v5.V8H());
+  __ umax(v28.V16B(), v12.V16B(), v6.V16B());
+  __ umax(v20.V2S(), v19.V2S(), v26.V2S());
+  __ umax(v0.V4H(), v31.V4H(), v18.V4H());
+  __ umax(v6.V4S(), v21.V4S(), v28.V4S());
+  __ umax(v0.V8B(), v2.V8B(), v20.V8B());
+  __ umax(v4.V8H(), v11.V8H(), v22.V8H());
+  __ umaxp(v1.V16B(), v6.V16B(), v29.V16B());
+  __ umaxp(v19.V2S(), v17.V2S(), v27.V2S());
+  __ umaxp(v21.V4H(), v16.V4H(), v7.V4H());
+  __ umaxp(v9.V4S(), v20.V4S(), v29.V4S());
+  __ umaxp(v13.V8B(), v1.V8B(), v16.V8B());
+  __ umaxp(v19.V8H(), v23.V8H(), v26.V8H());
+  __ umaxv(b17, v30.V16B());
+  __ umaxv(b23, v12.V8B());
+  __ umaxv(h31, v15.V4H());
+  __ umaxv(h15, v25.V8H());
+  __ umaxv(s18, v21.V4S());
+  __ umin(v22.V16B(), v0.V16B(), v18.V16B());
+  __ umin(v1.V2S(), v21.V2S(), v16.V2S());
+  __ umin(v17.V4H(), v4.V4H(), v25.V4H());
+  __ umin(v24.V4S(), v26.V4S(), v13.V4S());
+  __ umin(v20.V8B(), v1.V8B(), v5.V8B());
+  __ umin(v26.V8H(), v25.V8H(), v23.V8H());
+  __ uminp(v5.V16B(), v1.V16B(), v23.V16B());
+  __ uminp(v7.V2S(), v26.V2S(), v30.V2S());
+  __ uminp(v9.V4H(), v5.V4H(), v25.V4H());
+  __ uminp(v23.V4S(), v10.V4S(), v1.V4S());
+  __ uminp(v4.V8B(), v29.V8B(), v14.V8B());
+  __ uminp(v21.V8H(), v0.V8H(), v14.V8H());
+  __ uminv(b0, v17.V16B());
+  __ uminv(b0, v31.V8B());
+  __ uminv(h24, v0.V4H());
+  __ uminv(h29, v14.V8H());
+  __ uminv(s30, v3.V4S());
+  __ umlal(v11.V2D(), v11.V2S(), v24.V2S());
+  __ umlal(v30.V2D(), v16.V2S(), v11.S(), 3);
+  __ umlal(v0.V4S(), v9.V4H(), v26.V4H());
+  __ umlal(v20.V4S(), v24.V4H(), v12.H(), 4);
+  __ umlal(v16.V8H(), v21.V8B(), v6.V8B());
+  __ umlal2(v17.V2D(), v19.V4S(), v23.V4S());
+  __ umlal2(v5.V2D(), v30.V4S(), v8.S(), 0);
+  __ umlal2(v16.V4S(), v8.V8H(), v15.V8H());
+  __ umlal2(v15.V4S(), v26.V8H(), v1.H(), 5);
+  __ umlal2(v30.V8H(), v1.V16B(), v17.V16B());
+  __ umlsl(v18.V2D(), v19.V2S(), v28.V2S());
+  __ umlsl(v7.V2D(), v7.V2S(), v8.S(), 0);
+  __ umlsl(v24.V4S(), v8.V4H(), v4.V4H());
+  __ umlsl(v18.V4S(), v22.V4H(), v12.H(), 4);
+  __ umlsl(v28.V8H(), v14.V8B(), v20.V8B());
+  __ umlsl2(v11.V2D(), v0.V4S(), v9.V4S());
+  __ umlsl2(v26.V2D(), v16.V4S(), v9.S(), 2);
+  __ umlsl2(v3.V4S(), v11.V8H(), v9.V8H());
+  __ umlsl2(v10.V4S(), v25.V8H(), v9.H(), 4);
+  __ umlsl2(v24.V8H(), v16.V16B(), v28.V16B());
+  __ umov(x30, v25.D(), 1);
+  __ umull(v12.V2D(), v10.V2S(), v29.V2S());
+  __ umull(v22.V2D(), v30.V2S(), v5.S(), 3);
+  __ umull(v7.V4S(), v0.V4H(), v25.V4H());
+  __ umull(v11.V4S(), v13.V4H(), v3.H(), 2);
+  __ umull(v25.V8H(), v16.V8B(), v10.V8B());
+  __ umull2(v17.V2D(), v3.V4S(), v26.V4S());
+  __ umull2(v26.V2D(), v11.V4S(), v2.S(), 3);
+  __ umull2(v12.V4S(), v17.V8H(), v23.V8H());
+  __ umull2(v4.V4S(), v31.V8H(), v1.H(), 2);
+  __ umull2(v5.V8H(), v12.V16B(), v17.V16B());
+  __ uqadd(b30, b4, b28);
+  __ uqadd(d27, d20, d16);
+  __ uqadd(h7, h14, h28);
+  __ uqadd(s28, s17, s4);
+  __ uqadd(v19.V16B(), v22.V16B(), v21.V16B());
+  __ uqadd(v16.V2D(), v4.V2D(), v11.V2D());
+  __ uqadd(v20.V2S(), v14.V2S(), v4.V2S());
+  __ uqadd(v5.V4H(), v0.V4H(), v16.V4H());
+  __ uqadd(v21.V4S(), v31.V4S(), v9.V4S());
+  __ uqadd(v23.V8B(), v24.V8B(), v3.V8B());
+  __ uqadd(v17.V8H(), v27.V8H(), v11.V8H());
+  __ uqrshl(b10, b22, b10);
+  __ uqrshl(d29, d5, d11);
+  __ uqrshl(h27, h24, h30);
+  __ uqrshl(s10, s13, s8);
+  __ uqrshl(v9.V16B(), v18.V16B(), v14.V16B());
+  __ uqrshl(v24.V2D(), v15.V2D(), v17.V2D());
+  __ uqrshl(v4.V2S(), v14.V2S(), v27.V2S());
+  __ uqrshl(v15.V4H(), v5.V4H(), v8.V4H());
+  __ uqrshl(v21.V4S(), v29.V4S(), v0.V4S());
+  __ uqrshl(v16.V8B(), v24.V8B(), v9.V8B());
+  __ uqrshl(v2.V8H(), v0.V8H(), v15.V8H());
+  __ uqrshrn(b11, h26, 4);
+  __ uqrshrn(h7, s30, 5);
+  __ uqrshrn(s10, d8, 21);
+  __ uqrshrn(v15.V2S(), v6.V2D(), 11);
+  __ uqrshrn(v5.V4H(), v26.V4S(), 12);
+  __ uqrshrn(v28.V8B(), v25.V8H(), 5);
+  __ uqrshrn2(v25.V16B(), v30.V8H(), 2);
+  __ uqrshrn2(v21.V4S(), v14.V2D(), 32);
+  __ uqrshrn2(v13.V8H(), v7.V4S(), 2);
+  __ uqshl(b13, b0, b23);
+  __ uqshl(b9, b17, 4);
+  __ uqshl(d23, d6, d4);
+  __ uqshl(d8, d11, 44);
+  __ uqshl(h19, h13, h15);
+  __ uqshl(h25, h26, 6);
+  __ uqshl(s4, s24, s10);
+  __ uqshl(s19, s14, 1);
+  __ uqshl(v14.V16B(), v30.V16B(), v25.V16B());
+  __ uqshl(v6.V16B(), v10.V16B(), 5);
+  __ uqshl(v18.V2D(), v8.V2D(), v7.V2D());
+  __ uqshl(v25.V2D(), v14.V2D(), 18);
+  __ uqshl(v25.V2S(), v16.V2S(), v23.V2S());
+  __ uqshl(v13.V2S(), v15.V2S(), 31);
+  __ uqshl(v28.V4H(), v24.V4H(), v15.V4H());
+  __ uqshl(v4.V4H(), v17.V4H(), 1);
+  __ uqshl(v9.V4S(), v31.V4S(), v23.V4S());
+  __ uqshl(v18.V4S(), v28.V4S(), 31);
+  __ uqshl(v31.V8B(), v21.V8B(), v15.V8B());
+  __ uqshl(v6.V8B(), v21.V8B(), 1);
+  __ uqshl(v28.V8H(), v2.V8H(), v17.V8H());
+  __ uqshl(v24.V8H(), v8.V8H(), 14);
+  __ uqshrn(b21, h27, 7);
+  __ uqshrn(h28, s26, 11);
+  __ uqshrn(s13, d31, 17);
+  __ uqshrn(v21.V2S(), v16.V2D(), 8);
+  __ uqshrn(v24.V4H(), v24.V4S(), 2);
+  __ uqshrn(v5.V8B(), v1.V8H(), 8);
+  __ uqshrn2(v16.V16B(), v29.V8H(), 6);
+  __ uqshrn2(v2.V4S(), v6.V2D(), 1);
+  __ uqshrn2(v16.V8H(), v10.V4S(), 14);
+  __ uqsub(b28, b20, b26);
+  __ uqsub(d0, d7, d10);
+  __ uqsub(h26, h24, h7);
+  __ uqsub(s23, s23, s16);
+  __ uqsub(v14.V16B(), v16.V16B(), v24.V16B());
+  __ uqsub(v11.V2D(), v17.V2D(), v6.V2D());
+  __ uqsub(v10.V2S(), v10.V2S(), v8.V2S());
+  __ uqsub(v9.V4H(), v15.V4H(), v12.V4H());
+  __ uqsub(v23.V4S(), v18.V4S(), v7.V4S());
+  __ uqsub(v9.V8B(), v19.V8B(), v17.V8B());
+  __ uqsub(v20.V8H(), v2.V8H(), v6.V8H());
+  __ uqxtn(b29, h19);
+  __ uqxtn(h0, s13);
+  __ uqxtn(s26, d22);
+  __ uqxtn(v5.V2S(), v31.V2D());
+  __ uqxtn(v30.V4H(), v19.V4S());
+  __ uqxtn(v15.V8B(), v2.V8H());
+  __ uqxtn2(v29.V16B(), v3.V8H());
+  __ uqxtn2(v13.V4S(), v17.V2D());
+  __ uqxtn2(v28.V8H(), v11.V4S());
+  __ urecpe(v23.V2S(), v15.V2S());
+  __ urecpe(v27.V4S(), v7.V4S());
+  __ urhadd(v2.V16B(), v15.V16B(), v27.V16B());
+  __ urhadd(v15.V2S(), v1.V2S(), v18.V2S());
+  __ urhadd(v17.V4H(), v4.V4H(), v26.V4H());
+  __ urhadd(v2.V4S(), v27.V4S(), v14.V4S());
+  __ urhadd(v5.V8B(), v17.V8B(), v14.V8B());
+  __ urhadd(v30.V8H(), v2.V8H(), v25.V8H());
+  __ urshl(d4, d28, d30);
+  __ urshl(v13.V16B(), v31.V16B(), v19.V16B());
+  __ urshl(v14.V2D(), v23.V2D(), v21.V2D());
+  __ urshl(v10.V2S(), v7.V2S(), v8.V2S());
+  __ urshl(v15.V4H(), v21.V4H(), v28.V4H());
+  __ urshl(v30.V4S(), v8.V4S(), v23.V4S());
+  __ urshl(v31.V8B(), v20.V8B(), v5.V8B());
+  __ urshl(v30.V8H(), v27.V8H(), v30.V8H());
+  __ urshr(d4, d13, 49);
+  __ urshr(v2.V16B(), v20.V16B(), 1);
+  __ urshr(v13.V2D(), v11.V2D(), 51);
+  __ urshr(v21.V2S(), v31.V2S(), 10);
+  __ urshr(v21.V4H(), v17.V4H(), 11);
+  __ urshr(v4.V4S(), v22.V4S(), 1);
+  __ urshr(v0.V8B(), v1.V8B(), 7);
+  __ urshr(v13.V8H(), v20.V8H(), 1);
+  __ ursqrte(v20.V2S(), v16.V2S());
+  __ ursqrte(v28.V4S(), v8.V4S());
+  __ ursra(d27, d16, 45);
+  __ ursra(v18.V16B(), v17.V16B(), 3);
+  __ ursra(v26.V2D(), v28.V2D(), 58);
+  __ ursra(v8.V2S(), v22.V2S(), 31);
+  __ ursra(v31.V4H(), v4.V4H(), 7);
+  __ ursra(v31.V4S(), v15.V4S(), 2);
+  __ ursra(v3.V8B(), v1.V8B(), 5);
+  __ ursra(v18.V8H(), v14.V8H(), 13);
+  __ ushl(d31, d0, d16);
+  __ ushl(v0.V16B(), v6.V16B(), v2.V16B());
+  __ ushl(v18.V2D(), v1.V2D(), v18.V2D());
+  __ ushl(v27.V2S(), v7.V2S(), v29.V2S());
+  __ ushl(v14.V4H(), v14.V4H(), v13.V4H());
+  __ ushl(v22.V4S(), v4.V4S(), v9.V4S());
+  __ ushl(v23.V8B(), v22.V8B(), v27.V8B());
+  __ ushl(v21.V8H(), v25.V8H(), v8.V8H());
+  __ ushll(v11.V2D(), v0.V2S(), 21);
+  __ ushll(v2.V4S(), v17.V4H(), 8);
+  __ ushll(v11.V8H(), v14.V8B(), 1);
+  __ ushll2(v8.V2D(), v29.V4S(), 7);
+  __ ushll2(v29.V4S(), v9.V8H(), 2);
+  __ ushll2(v5.V8H(), v24.V16B(), 6);
+  __ ushr(d28, d27, 53);
+  __ ushr(v1.V16B(), v9.V16B(), 7);
+  __ ushr(v2.V2D(), v24.V2D(), 43);
+  __ ushr(v30.V2S(), v25.V2S(), 11);
+  __ ushr(v10.V4H(), v26.V4H(), 12);
+  __ ushr(v4.V4S(), v5.V4S(), 30);
+  __ ushr(v30.V8B(), v2.V8B(), 1);
+  __ ushr(v6.V8H(), v12.V8H(), 2);
+  __ usqadd(b19, b5);
+  __ usqadd(d9, d2);
+  __ usqadd(h2, h16);
+  __ usqadd(s16, s3);
+  __ usqadd(v31.V16B(), v29.V16B());
+  __ usqadd(v8.V2D(), v10.V2D());
+  __ usqadd(v18.V2S(), v9.V2S());
+  __ usqadd(v24.V4H(), v14.V4H());
+  __ usqadd(v10.V4S(), v30.V4S());
+  __ usqadd(v16.V8B(), v20.V8B());
+  __ usqadd(v12.V8H(), v16.V8H());
+  __ usra(d28, d27, 37);
+  __ usra(v5.V16B(), v22.V16B(), 5);
+  __ usra(v2.V2D(), v19.V2D(), 33);
+  __ usra(v0.V2S(), v0.V2S(), 21);
+  __ usra(v7.V4H(), v6.V4H(), 12);
+  __ usra(v4.V4S(), v17.V4S(), 9);
+  __ usra(v9.V8B(), v12.V8B(), 7);
+  __ usra(v3.V8H(), v27.V8H(), 14);
+  __ usubl(v29.V2D(), v12.V2S(), v30.V2S());
+  __ usubl(v29.V4S(), v28.V4H(), v6.V4H());
+  __ usubl(v12.V8H(), v4.V8B(), v14.V8B());
+  __ usubl2(v1.V2D(), v24.V4S(), v17.V4S());
+  __ usubl2(v4.V4S(), v1.V8H(), v3.V8H());
+  __ usubl2(v23.V8H(), v4.V16B(), v7.V16B());
+  __ usubw(v9.V2D(), v20.V2D(), v30.V2S());
+  __ usubw(v20.V4S(), v16.V4S(), v23.V4H());
+  __ usubw(v25.V8H(), v8.V8H(), v29.V8B());
+  __ usubw2(v18.V2D(), v29.V2D(), v6.V4S());
+  __ usubw2(v6.V4S(), v6.V4S(), v20.V8H());
+  __ usubw2(v18.V8H(), v4.V8H(), v16.V16B());
+  __ uxtl(v27.V2D(), v21.V2S());
+  __ uxtl(v0.V4S(), v31.V4H());
+  __ uxtl(v27.V8H(), v10.V8B());
+  __ uxtl2(v6.V2D(), v16.V4S());
+  __ uxtl2(v22.V4S(), v20.V8H());
+  __ uxtl2(v20.V8H(), v21.V16B());
+  __ uzp1(v30.V16B(), v9.V16B(), v17.V16B());
+  __ uzp1(v7.V2D(), v26.V2D(), v28.V2D());
+  __ uzp1(v26.V2S(), v16.V2S(), v22.V2S());
+  __ uzp1(v14.V4H(), v19.V4H(), v6.V4H());
+  __ uzp1(v17.V4S(), v23.V4S(), v30.V4S());
+  __ uzp1(v28.V8B(), v27.V8B(), v13.V8B());
+  __ uzp1(v17.V8H(), v1.V8H(), v12.V8H());
+  __ uzp2(v8.V16B(), v18.V16B(), v26.V16B());
+  __ uzp2(v21.V2D(), v22.V2D(), v24.V2D());
+  __ uzp2(v20.V2S(), v21.V2S(), v2.V2S());
+  __ uzp2(v16.V4H(), v31.V4H(), v6.V4H());
+  __ uzp2(v25.V4S(), v11.V4S(), v8.V4S());
+  __ uzp2(v31.V8B(), v31.V8B(), v13.V8B());
+  __ uzp2(v8.V8H(), v17.V8H(), v1.V8H());
+  __ xtn(v17.V2S(), v26.V2D());
+  __ xtn(v3.V4H(), v0.V4S());
+  __ xtn(v18.V8B(), v8.V8H());
+  __ xtn2(v0.V16B(), v0.V8H());
+  __ xtn2(v15.V4S(), v4.V2D());
+  __ xtn2(v31.V8H(), v18.V4S());
+  __ zip1(v22.V16B(), v9.V16B(), v6.V16B());
+  __ zip1(v23.V2D(), v11.V2D(), v2.V2D());
+  __ zip1(v26.V2S(), v16.V2S(), v9.V2S());
+  __ zip1(v1.V4H(), v9.V4H(), v7.V4H());
+  __ zip1(v0.V4S(), v30.V4S(), v20.V4S());
+  __ zip1(v30.V8B(), v17.V8B(), v15.V8B());
+  __ zip1(v17.V8H(), v8.V8H(), v2.V8H());
+  __ zip2(v23.V16B(), v10.V16B(), v11.V16B());
+  __ zip2(v30.V2D(), v6.V2D(), v14.V2D());
+  __ zip2(v9.V2S(), v10.V2S(), v21.V2S());
+  __ zip2(v8.V4H(), v24.V4H(), v29.V4H());
+  __ zip2(v0.V4S(), v21.V4S(), v23.V4S());
+  __ zip2(v25.V8B(), v23.V8B(), v30.V8B());
+  __ zip2(v7.V8H(), v10.V8H(), v30.V8H());
+}  // NOLINT(readability/fn_size)
+
+
+static void GenerateTestSequenceNEONFP(MacroAssembler* masm) {
+  CodeBufferCheckScope guard(masm, masm->RemainingBufferSpace());
+
+  // NEON floating point instructions.
+  __ fabd(v3.V2D(), v25.V2D(), v8.V2D());
+  __ fabd(v14.V2S(), v27.V2S(), v11.V2S());
+  __ fabd(v9.V4S(), v22.V4S(), v18.V4S());
+  __ fabs(v1.V2D(), v29.V2D());
+  __ fabs(v6.V2S(), v21.V2S());
+  __ fabs(v12.V4S(), v25.V4S());
+  __ facge(v18.V2D(), v5.V2D(), v0.V2D());
+  __ facge(v15.V2S(), v11.V2S(), v6.V2S());
+  __ facge(v30.V4S(), v10.V4S(), v25.V4S());
+  __ facgt(v28.V2D(), v16.V2D(), v31.V2D());
+  __ facgt(v15.V2S(), v1.V2S(), v4.V2S());
+  __ facgt(v22.V4S(), v3.V4S(), v10.V4S());
+  __ fadd(v7.V2D(), v10.V2D(), v24.V2D());
+  __ fadd(v10.V2S(), v23.V2S(), v7.V2S());
+  __ fadd(v16.V4S(), v22.V4S(), v11.V4S());
+  __ faddp(d27, v28.V2D());
+  __ faddp(s20, v23.V2S());
+  __ faddp(v21.V2D(), v4.V2D(), v11.V2D());
+  __ faddp(v31.V2S(), v26.V2S(), v1.V2S());
+  __ faddp(v13.V4S(), v27.V4S(), v28.V4S());
+  __ fcmeq(v17.V2D(), v13.V2D(), v20.V2D());
+  __ fcmeq(v24.V2D(), v16.V2D(), 0.0);
+  __ fcmeq(v26.V2S(), v17.V2S(), v10.V2S());
+  __ fcmeq(v24.V2S(), v4.V2S(), 0.0);
+  __ fcmeq(v8.V4S(), v4.V4S(), v14.V4S());
+  __ fcmeq(v26.V4S(), v25.V4S(), 0.0);
+  __ fcmge(v27.V2D(), v0.V2D(), v0.V2D());
+  __ fcmge(v22.V2D(), v30.V2D(), 0.0);
+  __ fcmge(v7.V2S(), v21.V2S(), v25.V2S());
+  __ fcmge(v15.V2S(), v15.V2S(), 0.0);
+  __ fcmge(v29.V4S(), v4.V4S(), v27.V4S());
+  __ fcmge(v22.V4S(), v21.V4S(), 0.0);
+  __ fcmgt(v1.V2D(), v26.V2D(), v15.V2D());
+  __ fcmgt(v15.V2D(), v23.V2D(), 0.0);
+  __ fcmgt(v21.V2S(), v16.V2S(), v6.V2S());
+  __ fcmgt(v1.V2S(), v13.V2S(), 0.0);
+  __ fcmgt(v14.V4S(), v0.V4S(), v25.V4S());
+  __ fcmgt(v13.V4S(), v8.V4S(), 0.0);
+  __ fcmle(v4.V2D(), v6.V2D(), 0.0);
+  __ fcmle(v24.V2S(), v31.V2S(), 0.0);
+  __ fcmle(v8.V4S(), v23.V4S(), 0.0);
+  __ fcmlt(v7.V2D(), v3.V2D(), 0.0);
+  __ fcmlt(v15.V2S(), v21.V2S(), 0.0);
+  __ fcmlt(v1.V4S(), v2.V4S(), 0.0);
+  __ fcvtas(v6.V2D(), v8.V2D());
+  __ fcvtas(v1.V2S(), v9.V2S());
+  __ fcvtas(v8.V4S(), v19.V4S());
+  __ fcvtau(v5.V2D(), v31.V2D());
+  __ fcvtau(v28.V2S(), v29.V2S());
+  __ fcvtau(v11.V4S(), v26.V4S());
+  __ fcvtl(v8.V2D(), v25.V2S());
+  __ fcvtl(v27.V4S(), v14.V4H());
+  __ fcvtl2(v1.V2D(), v6.V4S());
+  __ fcvtl2(v24.V4S(), v9.V8H());
+  __ fcvtms(v9.V2D(), v24.V2D());
+  __ fcvtms(v7.V2S(), v11.V2S());
+  __ fcvtms(v23.V4S(), v21.V4S());
+  __ fcvtmu(v13.V2D(), v1.V2D());
+  __ fcvtmu(v26.V2S(), v12.V2S());
+  __ fcvtmu(v21.V4S(), v21.V4S());
+  __ fcvtn(v11.V2S(), v1.V2D());
+  __ fcvtn(v8.V4H(), v2.V4S());
+  __ fcvtn2(v24.V4S(), v29.V2D());
+  __ fcvtn2(v4.V8H(), v10.V4S());
+  __ fcvtns(v25.V2D(), v10.V2D());
+  __ fcvtns(v4.V2S(), v8.V2S());
+  __ fcvtns(v29.V4S(), v27.V4S());
+  __ fcvtnu(v18.V2D(), v27.V2D());
+  __ fcvtnu(v11.V2S(), v14.V2S());
+  __ fcvtnu(v27.V4S(), v21.V4S());
+  __ fcvtps(v23.V2D(), v5.V2D());
+  __ fcvtps(v24.V2S(), v15.V2S());
+  __ fcvtps(v5.V4S(), v19.V4S());
+  __ fcvtpu(v3.V2D(), v21.V2D());
+  __ fcvtpu(v3.V2S(), v21.V2S());
+  __ fcvtpu(v0.V4S(), v7.V4S());
+  __ fcvtxn(v29.V2S(), v11.V2D());
+  __ fcvtxn2(v31.V4S(), v25.V2D());
+  __ fcvtzs(v19.V2D(), v17.V2D());
+  __ fcvtzs(v12.V2D(), v24.V2D(), 64);
+  __ fcvtzs(v9.V2S(), v2.V2S());
+  __ fcvtzs(v5.V2S(), v20.V2S(), 29);
+  __ fcvtzs(v21.V4S(), v25.V4S());
+  __ fcvtzs(v26.V4S(), v1.V4S(), 6);
+  __ fcvtzu(v13.V2D(), v25.V2D());
+  __ fcvtzu(v28.V2D(), v13.V2D(), 32);
+  __ fcvtzu(v26.V2S(), v6.V2S());
+  __ fcvtzu(v9.V2S(), v10.V2S(), 15);
+  __ fcvtzu(v30.V4S(), v6.V4S());
+  __ fcvtzu(v19.V4S(), v22.V4S(), 18);
+  __ fdiv(v15.V2D(), v8.V2D(), v15.V2D());
+  __ fdiv(v12.V2S(), v9.V2S(), v26.V2S());
+  __ fdiv(v19.V4S(), v22.V4S(), v19.V4S());
+  __ fmax(v19.V2D(), v7.V2D(), v8.V2D());
+  __ fmax(v25.V2S(), v12.V2S(), v29.V2S());
+  __ fmax(v6.V4S(), v15.V4S(), v5.V4S());
+  __ fmaxnm(v16.V2D(), v8.V2D(), v20.V2D());
+  __ fmaxnm(v15.V2S(), v26.V2S(), v25.V2S());
+  __ fmaxnm(v23.V4S(), v14.V4S(), v16.V4S());
+  __ fmaxnmp(d6, v19.V2D());
+  __ fmaxnmp(s27, v26.V2S());
+  __ fmaxnmp(v8.V2D(), v12.V2D(), v23.V2D());
+  __ fmaxnmp(v13.V2S(), v25.V2S(), v22.V2S());
+  __ fmaxnmp(v15.V4S(), v11.V4S(), v17.V4S());
+  __ fmaxnmv(s27, v19.V4S());
+  __ fmaxp(d20, v14.V2D());
+  __ fmaxp(s18, v2.V2S());
+  __ fmaxp(v9.V2D(), v23.V2D(), v31.V2D());
+  __ fmaxp(v7.V2S(), v22.V2S(), v31.V2S());
+  __ fmaxp(v18.V4S(), v7.V4S(), v29.V4S());
+  __ fmaxv(s31, v29.V4S());
+  __ fmin(v2.V2D(), v5.V2D(), v2.V2D());
+  __ fmin(v31.V2S(), v17.V2S(), v10.V2S());
+  __ fmin(v10.V4S(), v4.V4S(), v16.V4S());
+  __ fminnm(v21.V2D(), v6.V2D(), v5.V2D());
+  __ fminnm(v22.V2S(), v18.V2S(), v14.V2S());
+  __ fminnm(v25.V4S(), v31.V4S(), v3.V4S());
+  __ fminnmp(d9, v1.V2D());
+  __ fminnmp(s21, v20.V2S());
+  __ fminnmp(v16.V2D(), v21.V2D(), v19.V2D());
+  __ fminnmp(v16.V2S(), v31.V2S(), v25.V2S());
+  __ fminnmp(v26.V4S(), v16.V4S(), v15.V4S());
+  __ fminnmv(s3, v4.V4S());
+  __ fminp(d24, v26.V2D());
+  __ fminp(s7, v17.V2S());
+  __ fminp(v23.V2D(), v19.V2D(), v3.V2D());
+  __ fminp(v29.V2S(), v21.V2S(), v9.V2S());
+  __ fminp(v0.V4S(), v24.V4S(), v21.V4S());
+  __ fminv(s25, v8.V4S());
+  __ fmla(d23, d0, v9.D(), 1);
+  __ fmla(s23, s15, v7.S(), 0);
+  __ fmla(v17.V2D(), v11.V2D(), v6.V2D());
+  __ fmla(v30.V2D(), v30.V2D(), v11.D(), 0);
+  __ fmla(v19.V2S(), v12.V2S(), v6.V2S());
+  __ fmla(v24.V2S(), v17.V2S(), v9.S(), 0);
+  __ fmla(v16.V4S(), v11.V4S(), v11.V4S());
+  __ fmla(v27.V4S(), v23.V4S(), v9.S(), 2);
+  __ fmls(d27, d30, v6.D(), 0);
+  __ fmls(s21, s16, v2.S(), 0);
+  __ fmls(v5.V2D(), v19.V2D(), v21.V2D());
+  __ fmls(v18.V2D(), v30.V2D(), v12.D(), 0);
+  __ fmls(v5.V2S(), v16.V2S(), v7.V2S());
+  __ fmls(v3.V2S(), v18.V2S(), v11.S(), 1);
+  __ fmls(v27.V4S(), v5.V4S(), v30.V4S());
+  __ fmls(v26.V4S(), v20.V4S(), v4.S(), 3);
+  __ fmov(v14.V2D(), -0.34375);
+  __ fmov(v26.V2S(), 0.90625f);
+  __ fmov(v31.V4S(), -5.0000f);
+  __ fmov(v28.D(), 1, x25);
+  __ fmov(x18, v2.D(), 1);
+  __ fmul(d12, d4, v1.D(), 1);
+  __ fmul(s30, s1, v15.S(), 3);
+  __ fmul(v25.V2D(), v0.V2D(), v21.V2D());
+  __ fmul(v10.V2D(), v24.V2D(), v10.D(), 1);
+  __ fmul(v7.V2S(), v24.V2S(), v16.V2S());
+  __ fmul(v1.V2S(), v16.V2S(), v4.S(), 2);
+  __ fmul(v5.V4S(), v28.V4S(), v25.V4S());
+  __ fmul(v11.V4S(), v3.V4S(), v8.S(), 0);
+  __ fmulx(d28, d9, v3.D(), 1);
+  __ fmulx(s25, s21, v15.S(), 1);
+  __ fmulx(v31.V2D(), v28.V2D(), v8.V2D());
+  __ fmulx(v3.V2D(), v21.V2D(), v6.D(), 0);
+  __ fmulx(v9.V2S(), v1.V2S(), v0.V2S());
+  __ fmulx(v16.V2S(), v27.V2S(), v6.S(), 0);
+  __ fmulx(v2.V4S(), v4.V4S(), v5.V4S());
+  __ fmulx(v18.V4S(), v7.V4S(), v4.S(), 0);
+  __ fneg(v1.V2D(), v25.V2D());
+  __ fneg(v14.V2S(), v31.V2S());
+  __ fneg(v5.V4S(), v4.V4S());
+  __ frecpe(v18.V2D(), v12.V2D());
+  __ frecpe(v10.V2S(), v22.V2S());
+  __ frecpe(v5.V4S(), v6.V4S());
+  __ frecps(v22.V2D(), v7.V2D(), v26.V2D());
+  __ frecps(v31.V2S(), v27.V2S(), v2.V2S());
+  __ frecps(v18.V4S(), v6.V4S(), v27.V4S());
+  __ frinta(v26.V2D(), v13.V2D());
+  __ frinta(v15.V2S(), v26.V2S());
+  __ frinta(v13.V4S(), v16.V4S());
+  __ frinti(v9.V2D(), v12.V2D());
+  __ frinti(v5.V2S(), v19.V2S());
+  __ frinti(v15.V4S(), v11.V4S());
+  __ frintm(v17.V2D(), v29.V2D());
+  __ frintm(v30.V2S(), v11.V2S());
+  __ frintm(v1.V4S(), v20.V4S());
+  __ frintn(v24.V2D(), v6.V2D());
+  __ frintn(v12.V2S(), v17.V2S());
+  __ frintn(v29.V4S(), v11.V4S());
+  __ frintp(v10.V2D(), v7.V2D());
+  __ frintp(v12.V2S(), v18.V2S());
+  __ frintp(v26.V4S(), v31.V4S());
+  __ frintx(v24.V2D(), v13.V2D());
+  __ frintx(v7.V2S(), v9.V2S());
+  __ frintx(v18.V4S(), v21.V4S());
+  __ frintz(v19.V2D(), v25.V2D());
+  __ frintz(v15.V2S(), v8.V2S());
+  __ frintz(v20.V4S(), v3.V4S());
+  __ frsqrte(v23.V2D(), v5.V2D());
+  __ frsqrte(v9.V2S(), v7.V2S());
+  __ frsqrte(v3.V4S(), v9.V4S());
+  __ frsqrts(v25.V2D(), v28.V2D(), v15.V2D());
+  __ frsqrts(v9.V2S(), v26.V2S(), v10.V2S());
+  __ frsqrts(v5.V4S(), v1.V4S(), v10.V4S());
+  __ fsqrt(v6.V2D(), v18.V2D());
+  __ fsqrt(v6.V2S(), v18.V2S());
+  __ fsqrt(v0.V4S(), v31.V4S());
+  __ fsub(v31.V2D(), v30.V2D(), v31.V2D());
+  __ fsub(v11.V2S(), v8.V2S(), v6.V2S());
+  __ fsub(v16.V4S(), v0.V4S(), v31.V4S());
+  __ scvtf(v25.V2D(), v31.V2D());
+  __ scvtf(v10.V2D(), v13.V2D(), 45);
+  __ scvtf(v10.V2S(), v15.V2S());
+  __ scvtf(v18.V2S(), v4.V2S(), 27);
+  __ scvtf(v17.V4S(), v5.V4S());
+  __ scvtf(v11.V4S(), v25.V4S(), 24);
+  __ ucvtf(v9.V2D(), v3.V2D());
+  __ ucvtf(v26.V2D(), v30.V2D(), 46);
+  __ ucvtf(v11.V2S(), v4.V2S());
+  __ ucvtf(v29.V2S(), v3.V2S(), 25);
+  __ ucvtf(v22.V4S(), v23.V4S());
+  __ ucvtf(v18.V4S(), v9.V4S(), 25);
+}
+
+
+static void MaskAddresses(const char* trace) {
+#define COLOUR "(\\x1b\\[[01];([0-9][0-9])?m)?"
+  struct {
+    const char* search;
+    const char* replace;
+  } patterns[] = {
+      // Mask registers that hold addresses that change from run to run.
+      {"((x0|x1|x2|sp): " COLOUR "0x)[0-9a-f]{16}", "\\1~~~~~~~~~~~~~~~~"},
+      // Mask accessed memory addresses.
+      {"((<-|->) " COLOUR "0x)[0-9a-f]{16}", "\\1~~~~~~~~~~~~~~~~"},
+      // Mask instruction addresses.
+      {"^0x[0-9a-f]{16}", "0x~~~~~~~~~~~~~~~~"}
+  };
+  const size_t patterns_length = sizeof(patterns) / sizeof(patterns[0]);
+  // Rewrite `trace`, masking addresses and other values that legitimately vary
+  // from run to run.
+  char command[1024];
+  for (size_t i = 0; i < patterns_length; i++) {
+    size_t length =
+        snprintf(command, sizeof(command), "sed -ri 's/%s/%s/' '%s'",
+                 patterns[i].search, patterns[i].replace, trace);
+    VIXL_CHECK(length < sizeof(command));
+    VIXL_CHECK(system(command) == 0);
+  }
+}
+
+
+static void TraceTestHelper(bool coloured_trace,
+                            TraceParameters trace_parameters,
+                            const char* ref_file) {
+  MacroAssembler masm(12 * KBytes);
+
+  char trace_stream_filename[] = "/tmp/vixl-test-trace-XXXXXX";
+  int trace_stream_fd = mkstemp(trace_stream_filename);
+  FILE* trace_stream = fdopen(trace_stream_fd, "w");
+
+  Decoder decoder;
+  Simulator simulator(&decoder, trace_stream);
+  simulator.set_coloured_trace(coloured_trace);
+  simulator.set_trace_parameters(trace_parameters);
+  simulator.SilenceExclusiveAccessWarning();
+
+  // Set up a scratch buffer so we can test loads and stores.
+  const int kScratchSize = 64 * KBytes;
+  const int kScratchGuardSize = 128;
+  char scratch_buffer[kScratchSize + kScratchGuardSize];
+  for (size_t i = 0;
+       i < (sizeof(scratch_buffer) / sizeof(scratch_buffer[0]));
+       i++) {
+    scratch_buffer[i] = i & 0xff;
+  }
+  simulator.set_reg(0, scratch_buffer);  // Used for offset addressing.
+  simulator.set_reg(1, scratch_buffer);  // Used for pre-/post-index addressing.
+
+  const int kPostIndexRegisterStep = 13;         // Arbitrary interesting value.
+  simulator.set_reg(2, kPostIndexRegisterStep);  // Used for post-index offsets.
+
+  // Initialize the other registers with unique values.
+  uint64_t initial_base_u64 = 0x0100001000100101;
+  for (unsigned i = 3; i < kNumberOfRegisters; i++) {
+    if (i == kLinkRegCode) continue;
+    if (i == kZeroRegCode) continue;
+    // NoRegLog suppresses the log now, but the registers will still be logged
+    // before the first instruction is executed since they have been written but
+    // not printed.
+    simulator.set_reg(i, initial_base_u64 * i, Simulator::NoRegLog);
+  }
+  float initial_base_f32 = 1.2345f;
+  double initial_base_f64 = 1.3456f;
+  for (unsigned i = 0; i < kNumberOfVRegisters; i++) {
+    // Try to initialise V registers with reasonable FP values.
+    uint64_t low = (double_to_rawbits(initial_base_f64 * i) & ~kSRegMask) |
+                   float_to_rawbits(initial_base_f32 * i);
+    uint64_t high = low ^ 0x0005555500555555;
+    LogicVRegister reg(simulator.vreg(i));
+    reg.SetUint(kFormat2D, 0, low);
+    reg.SetUint(kFormat2D, 1, high);
+  }
+
+  GenerateTestSequenceBase(&masm);
+  GenerateTestSequenceFP(&masm);
+  GenerateTestSequenceNEON(&masm);
+  GenerateTestSequenceNEONFP(&masm);
+  masm.Ret();
+  masm.FinalizeCode();
+
+  simulator.RunFrom(masm.GetStartAddress<Instruction*>());
+
+  fclose(trace_stream);
+  MaskAddresses(trace_stream_filename);
+
+  if (Test::generate_test_trace()) {
+    // Copy trace_stream to stdout.
+    trace_stream = fopen(trace_stream_filename, "r");
+    VIXL_ASSERT(trace_stream != NULL);
+    fseek(trace_stream, 0, SEEK_SET);
+    char c;
+    while (1) {
+      c = getc(trace_stream);
+      if (c == EOF) break;
+      putc(c, stdout);
+    }
+    fclose(trace_stream);
+  } else {
+    // Check trace_stream against ref_file.
+    char command[1024];
+    size_t length = snprintf(command, sizeof(command),
+                             "diff -u %s %s", ref_file, trace_stream_filename);
+    VIXL_CHECK(length < sizeof(command));
+    VIXL_CHECK(system(command) == 0);
+  }
+
+  uint64_t offset_base = simulator.reg<uint64_t>(0);
+  uint64_t index_base = simulator.reg<uint64_t>(1);
+  VIXL_CHECK(index_base >= offset_base);
+  VIXL_CHECK((index_base - offset_base) <= kScratchSize);
+
+  // remove(trace_stream_filename);
+}
+
+
+#define REF(name) "test/test-trace-reference/" name
+
+// Test individual options.
+TEST(disasm) {
+  TraceTestHelper(false, LOG_DISASM, REF("log-disasm"));
+}
+TEST(regs) {
+  TraceTestHelper(false, LOG_REGS, REF("log-regs"));
+}
+TEST(vregs) {
+  TraceTestHelper(false, LOG_VREGS, REF("log-vregs"));
+}
+TEST(sysregs) {
+  TraceTestHelper(false, LOG_SYSREGS, REF("log-sysregs"));
+}
+TEST(write) {
+  TraceTestHelper(false, LOG_WRITE, REF("log-write"));
+}
+
+// Test standard combinations.
+TEST(none) {
+  TraceTestHelper(false, LOG_NONE, REF("log-none"));
+}
+TEST(state) {
+  TraceTestHelper(false, LOG_STATE, REF("log-state"));
+}
+TEST(all) {
+  TraceTestHelper(false, LOG_ALL, REF("log-all"));
+}
+
+
+// Test individual options (with colour).
+TEST(disasm_colour) {
+  TraceTestHelper(true, LOG_DISASM, REF("log-disasm-colour"));
+}
+TEST(regs_colour) {
+  TraceTestHelper(true, LOG_REGS, REF("log-regs-colour"));
+}
+TEST(vregs_colour) {
+  TraceTestHelper(true, LOG_VREGS, REF("log-vregs-colour"));
+}
+TEST(sysregs_colour) {
+  TraceTestHelper(true, LOG_SYSREGS, REF("log-sysregs-colour"));
+}
+TEST(write_colour) {
+  TraceTestHelper(true, LOG_WRITE, REF("log-write-colour"));
+}
+
+// Test standard combinations (with colour).
+TEST(none_colour) {
+  TraceTestHelper(true, LOG_NONE, REF("log-none-colour"));
+}
+TEST(state_colour) {
+  TraceTestHelper(true, LOG_STATE, REF("log-state-colour"));
+}
+TEST(all_colour) {
+  TraceTestHelper(true, LOG_ALL, REF("log-all-colour"));
+}
+
+
+#endif  // VIXL_INCLUDE_SIMULATOR
+}
diff --git a/test/test-trace-reference/log-all b/test/test-trace-reference/log-all
new file mode 100644
index 0000000..ccf3dff
--- /dev/null
+++ b/test/test-trace-reference/log-all
@@ -0,0 +1,6065 @@
+#    x0: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x2: 0x~~~~~~~~~~~~~~~~
+#    x3: 0x0300003000300303
+#    x4: 0x0400004000400404
+#    x5: 0x0500005000500505
+#    x6: 0x0600006000600606
+#    x7: 0x0700007000700707
+#    x8: 0x0800008000800808
+#    x9: 0x0900009000900909
+#   x10: 0x0a0000a000a00a0a
+#   x11: 0x0b0000b000b00b0b
+#   x12: 0x0c0000c000c00c0c
+#   x13: 0x0d0000d000d00d0d
+#   x14: 0x0e0000e000e00e0e
+#   x15: 0x0f0000f000f00f0f
+#   x16: 0x1000010001001010
+#   x17: 0x1100011001101111
+#   x18: 0x1200012001201212
+#   x19: 0x1300013001301313
+#   x20: 0x1400014001401414
+#   x21: 0x1500015001501515
+#   x22: 0x1600016001601616
+#   x23: 0x1700017001701717
+#   x24: 0x1800018001801818
+#   x25: 0x1900019001901919
+#   x26: 0x1a0001a001a01a1a
+#   x27: 0x1b0001b001b01b1b
+#   x28: 0x1c0001c001c01c1c
+#   x29: 0x1d0001d001d01d1d
+#    lr: 0x0000000000000000
+#    sp: 0x~~~~~~~~~~~~~~~~
+#    v0: 0x00055555005555550000000000000000
+#    v1: 0x3ff0d2c63fcb514c3ff587933f9e0419
+#    v2: 0x4000d2c6404b514c40058793401e0419
+#    v3: 0x401570fb40385373401025ae406d0626
+#    v4: 0x4010d2c640cb514c40158793409e0419
+#    v5: 0x401fbc2d4090d04a401ae97840c5851f
+#    v6: 0x402570fb40b85373402025ae40ed0626
+#    v7: 0x402783f4415f16c34022d6a1410a4396
+#    v8: 0x4020d2c6414b514c40258793411e0419
+#    v9: 0x402d6dd3416491c9402838864131c49c
+#   v10: 0x402fbc2d4110d04a402ae9784145851f
+#   v11: 0x4028cf3e410c10f7402d9a6b415945a2
+#   v12: 0x403570fb41385373403025ae416d0626
+#   v13: 0x40342b7d41d5360140317e2841806354
+#   v14: 0x403783f441df16c34032d6a1418a4396
+#   v15: 0x40317a4f41c1768240342f1a419423d7
+#   v16: 0x4030d2c641cb514c40358793419e0419
+#   v17: 0x4033b55841f2b10e4036e00d41a7e45b
+#   v18: 0x403d6dd341e491c94038388641b1c49c
+#   v19: 0x403cc5aa41eef18b403990ff41bba4de
+#   v20: 0x403fbc2d4190d04a403ae97841c5851f
+#   v21: 0x403914a7419a3034403c41f241cf6561
+#   v22: 0x4038cf3e418c10f7403d9a6b41d945a2
+#   v23: 0x403ba7b141b670b1403ef2e441e325e4
+#   v24: 0x404570fb41b85373404025ae41ed0626
+#   v25: 0x404584be41a3b3324040d1eb41f6e667
+#   v26: 0x40442b7d4255360140417e2842006354
+#   v27: 0x40477f314250062040422a6442055375
+#   v28: 0x404783f4425f16c34042d6a1420a4396
+#   v29: 0x4046d78b425a66e2404382de420f33b7
+#   v30: 0x40417a4f4241768240442f1a421423d7
+#   v31: 0x40418e02424c46ad4044db57421913f8
+0x~~~~~~~~~~~~~~~~  1a050083		adc w3, w4, w5
+#    x3: 0x0000000000900909
+0x~~~~~~~~~~~~~~~~  9a0800e6		adc x6, x7, x8
+#    x6: 0x0f0000f000f00f0f
+0x~~~~~~~~~~~~~~~~  3a0b0149		adcs w9, w10, w11
+# NZCV: N:0 Z:0 C:0 V:0
+#    x9: 0x0000000001501515
+0x~~~~~~~~~~~~~~~~  ba0e01ac		adcs x12, x13, x14
+# NZCV: N:0 Z:0 C:0 V:0
+#   x12: 0x1b0001b001b01b1b
+0x~~~~~~~~~~~~~~~~  0b11020f		add w15, w16, w17
+#   x15: 0x0000000002102121
+0x~~~~~~~~~~~~~~~~  8b140272		add x18, x19, x20
+#   x18: 0x2700027002702727
+0x~~~~~~~~~~~~~~~~  2b1702d5		adds w21, w22, w23
+# NZCV: N:0 Z:0 C:0 V:0
+#   x21: 0x0000000002d02d2d
+0x~~~~~~~~~~~~~~~~  ab1a0338		adds x24, x25, x26
+# NZCV: N:0 Z:0 C:0 V:0
+#   x24: 0x3300033003303333
+0x~~~~~~~~~~~~~~~~  0a1d039b		and w27, w28, w29
+#   x27: 0x0000000001c01c1c
+0x~~~~~~~~~~~~~~~~  8a040062		and x2, x3, x4
+#    x2: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  6a0700c5		ands w5, w6, w7
+# NZCV: N:0 Z:0 C:0 V:0
+#    x5: 0x0000000000700707
+0x~~~~~~~~~~~~~~~~  ea0a0128		ands x8, x9, x10
+# NZCV: N:0 Z:1 C:0 V:0
+#    x8: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  13007d8b		sbfx w11, w12, #0, #32
+#   x11: 0x0000000001b01b1b
+0x~~~~~~~~~~~~~~~~  9341fdcd		asr x13, x14, #1
+#   x13: 0x0700007000700707
+0x~~~~~~~~~~~~~~~~  1ad12a0f		asr w15, w16, w17
+#   x15: 0x0000000000000080
+0x~~~~~~~~~~~~~~~~  9ad42a72		asr x18, x19, x20
+#   x18: 0x0000013000130013
+0x~~~~~~~~~~~~~~~~  33051ad5		bfxil w21, w22, #5, #2
+#   x21: 0x0000000002d02d2c
+0x~~~~~~~~~~~~~~~~  b3472317		bfxil x23, x24, #7, #2
+#   x23: 0x1700017001701716
+0x~~~~~~~~~~~~~~~~  0a3b0359		bic w25, w26, w27
+#   x25: 0x0000000000200202
+0x~~~~~~~~~~~~~~~~  8a2203bc		bic x28, x29, x2
+#   x28: 0x1d0001d001d01d1d
+0x~~~~~~~~~~~~~~~~  6a250083		bics w3, w4, w5
+# NZCV: N:0 Z:1 C:0 V:0
+#    x3: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  ea2800e6		bics x6, x7, x8
+# NZCV: N:0 Z:0 C:0 V:0
+#    x6: 0x0700007000700707
+0x~~~~~~~~~~~~~~~~  3a4ae120		ccmn w9, w10, #nzcv, al
+# NZCV: N:0 Z:0 C:0 V:0
+0x~~~~~~~~~~~~~~~~  3a4a0120		ccmn w9, w10, #nzcv, eq
+# NZCV: N:0 Z:0 C:0 V:0
+0x~~~~~~~~~~~~~~~~  3a4a1120		ccmn w9, w10, #nzcv, ne
+# NZCV: N:0 Z:0 C:0 V:0
+0x~~~~~~~~~~~~~~~~  ba4ce162		ccmn x11, x12, #nzCv, al
+# NZCV: N:0 Z:0 C:0 V:0
+0x~~~~~~~~~~~~~~~~  ba4c3162		ccmn x11, x12, #nzCv, lo
+# NZCV: N:0 Z:0 C:0 V:0
+0x~~~~~~~~~~~~~~~~  ba4c2162		ccmn x11, x12, #nzCv, hs
+# NZCV: N:0 Z:0 C:1 V:0
+0x~~~~~~~~~~~~~~~~  7a4ee1a1		ccmp w13, w14, #nzcV, al
+# NZCV: N:1 Z:0 C:0 V:0
+0x~~~~~~~~~~~~~~~~  7a4e81a1		ccmp w13, w14, #nzcV, hi
+# NZCV: N:0 Z:0 C:0 V:1
+0x~~~~~~~~~~~~~~~~  7a4e91a1		ccmp w13, w14, #nzcV, ls
+# NZCV: N:1 Z:0 C:0 V:0
+0x~~~~~~~~~~~~~~~~  fa50e1e3		ccmp x15, x16, #nzCV, al
+# NZCV: N:1 Z:0 C:0 V:0
+0x~~~~~~~~~~~~~~~~  fa5001e3		ccmp x15, x16, #nzCV, eq
+# NZCV: N:0 Z:0 C:1 V:1
+0x~~~~~~~~~~~~~~~~  fa5011e3		ccmp x15, x16, #nzCV, ne
+# NZCV: N:1 Z:0 C:0 V:0
+0x~~~~~~~~~~~~~~~~  1a922651		cinc w17, w18, lo
+#   x17: 0x0000000000130014
+0x~~~~~~~~~~~~~~~~  1a923651		cinc w17, w18, hs
+#   x17: 0x0000000000130013
+0x~~~~~~~~~~~~~~~~  9a949693		cinc x19, x20, hi
+#   x19: 0x1400014001401414
+0x~~~~~~~~~~~~~~~~  9a948693		cinc x19, x20, ls
+#   x19: 0x1400014001401415
+0x~~~~~~~~~~~~~~~~  5a9612d5		cinv w21, w22, eq
+#   x21: 0x0000000001601616
+0x~~~~~~~~~~~~~~~~  5a9602d5		cinv w21, w22, ne
+#   x21: 0x00000000fe9fe9e9
+0x~~~~~~~~~~~~~~~~  da982317		cinv x23, x24, lo
+#   x23: 0xccfffccffccfcccc
+0x~~~~~~~~~~~~~~~~  da983317		cinv x23, x24, hs
+#   x23: 0x3300033003303333
+0x~~~~~~~~~~~~~~~~  d5033f5f		clrex
+0x~~~~~~~~~~~~~~~~  5ac01759		cls w25, w26
+#   x25: 0x0000000000000006
+0x~~~~~~~~~~~~~~~~  dac0179b		cls x27, x28
+#   x27: 0x0000000000000002
+0x~~~~~~~~~~~~~~~~  5ac0105d		clz w29, w2
+#   x29: 0x0000000000000020
+0x~~~~~~~~~~~~~~~~  dac01083		clz x3, x4
+#    x3: 0x0000000000000005
+0x~~~~~~~~~~~~~~~~  2b0600bf		cmn w5, w6
+# NZCV: N:0 Z:0 C:0 V:0
+0x~~~~~~~~~~~~~~~~  ab0800ff		cmn x7, x8
+# NZCV: N:0 Z:0 C:0 V:0
+0x~~~~~~~~~~~~~~~~  6b0a013f		cmp w9, w10
+# NZCV: N:0 Z:0 C:1 V:0
+0x~~~~~~~~~~~~~~~~  eb0c017f		cmp x11, x12
+# NZCV: N:1 Z:0 C:0 V:0
+0x~~~~~~~~~~~~~~~~  5a8e95cd		cneg w13, w14, hi
+#   x13: 0x0000000000e00e0e
+0x~~~~~~~~~~~~~~~~  5a8e85cd		cneg w13, w14, ls
+#   x13: 0x00000000ff1ff1f2
+0x~~~~~~~~~~~~~~~~  da90160f		cneg x15, x16, eq
+#   x15: 0x1000010001001010
+0x~~~~~~~~~~~~~~~~  da90060f		cneg x15, x16, ne
+#   x15: 0xeffffefffeffeff0
+0x~~~~~~~~~~~~~~~~  1ad34251		crc32b w17, w18, w19
+#   x17: 0x00000000e963b635
+0x~~~~~~~~~~~~~~~~  1ad652b4		crc32cb w20, w21, w22
+#   x20: 0x00000000ad83ccb8
+0x~~~~~~~~~~~~~~~~  1ad95717		crc32ch w23, w24, w25
+#   x23: 0x000000003ed5525d
+0x~~~~~~~~~~~~~~~~  1adc5b7a		crc32cw w26, w27, w28
+#   x26: 0x00000000bc365145
+0x~~~~~~~~~~~~~~~~  1ac644a4		crc32h w4, w5, w6
+#    x4: 0x0000000000000070
+0x~~~~~~~~~~~~~~~~  1ac94907		crc32w w7, w8, w9
+#    x7: 0x00000000b096abf4
+0x~~~~~~~~~~~~~~~~  1a8f31cd		csel w13, w14, w15, lo
+#   x13: 0x0000000000e00e0e
+0x~~~~~~~~~~~~~~~~  1a8f21cd		csel w13, w14, w15, hs
+#   x13: 0x00000000feffeff0
+0x~~~~~~~~~~~~~~~~  9a928230		csel x16, x17, x18, hi
+#   x16: 0x0000013000130013
+0x~~~~~~~~~~~~~~~~  9a929230		csel x16, x17, x18, ls
+#   x16: 0x00000000e963b635
+0x~~~~~~~~~~~~~~~~  1a9f17f3		cset w19, eq
+#   x19: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  1a9f07f3		cset w19, ne
+#   x19: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  9a9f27f4		cset x20, lo
+#   x20: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  9a9f37f4		cset x20, hs
+#   x20: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  5a9f93f5		csetm w21, hi
+#   x21: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  5a9f83f5		csetm w21, ls
+#   x21: 0x00000000ffffffff
+0x~~~~~~~~~~~~~~~~  da9f13f6		csetm x22, eq
+#   x22: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  da9f03f6		csetm x22, ne
+#   x22: 0xffffffffffffffff
+0x~~~~~~~~~~~~~~~~  1a993717		csinc w23, w24, w25, lo
+#   x23: 0x0000000003303333
+0x~~~~~~~~~~~~~~~~  1a992717		csinc w23, w24, w25, hs
+#   x23: 0x0000000000000007
+0x~~~~~~~~~~~~~~~~  9a9c877a		csinc x26, x27, x28, hi
+#   x26: 0x1d0001d001d01d1e
+0x~~~~~~~~~~~~~~~~  9a9c977a		csinc x26, x27, x28, ls
+#   x26: 0x0000000000000002
+0x~~~~~~~~~~~~~~~~  5a83005d		csinv w29, w2, w3, eq
+#   x29: 0x00000000fffffffa
+0x~~~~~~~~~~~~~~~~  5a83105d		csinv w29, w2, w3, ne
+#   x29: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  da8630a4		csinv x4, x5, x6, lo
+#    x4: 0x0000000000700707
+0x~~~~~~~~~~~~~~~~  da8620a4		csinv x4, x5, x6, hs
+#    x4: 0xf8ffff8fff8ff8f8
+0x~~~~~~~~~~~~~~~~  5a898507		csneg w7, w8, w9, hi
+#    x7: 0x00000000feafeaeb
+0x~~~~~~~~~~~~~~~~  5a899507		csneg w7, w8, w9, ls
+#    x7: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  da8c056a		csneg x10, x11, x12, eq
+#   x10: 0xe4fffe4ffe4fe4e5
+0x~~~~~~~~~~~~~~~~  da8c156a		csneg x10, x11, x12, ne
+#   x10: 0x0000000001b01b1b
+0x~~~~~~~~~~~~~~~~  d50b7a20		dc cvac, x0
+0x~~~~~~~~~~~~~~~~  d5033bbf		dmb ish
+0x~~~~~~~~~~~~~~~~  d5033b9f		dsb ish
+0x~~~~~~~~~~~~~~~~  4a2f01cd		eon w13, w14, w15
+#   x13: 0x0000000001e01e01
+0x~~~~~~~~~~~~~~~~  ca320230		eon x16, x17, x18
+#   x16: 0xfffffecf168f49d9
+0x~~~~~~~~~~~~~~~~  4a150293		eor w19, w20, w21
+#   x19: 0x00000000ffffffff
+0x~~~~~~~~~~~~~~~~  ca1802f6		eor x22, x23, x24
+#   x22: 0x3300033003303334
+0x~~~~~~~~~~~~~~~~  139b2759		extr w25, w26, w27, #9
+#   x25: 0x0000000001000000
+0x~~~~~~~~~~~~~~~~  93c22bbc		extr x28, x29, x2, #10
+#   x28: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  d503201f		nop
+0x~~~~~~~~~~~~~~~~  d50b7520		ic ivau, x0
+0x~~~~~~~~~~~~~~~~  d5033fdf		isb
+0x~~~~~~~~~~~~~~~~  88dffc03		ldar w3, [x0]
+#    x3: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  c8dffc04		ldar x4, [x0]
+#    x4: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  08dffc05		ldarb w5, [x0]
+#    x5: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  08dffc06		ldarb w6, [x0]
+#    x6: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  48dffc07		ldarh w7, [x0]
+#    x7: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  48dffc08		ldarh w8, [x0]
+#    x8: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  887fa809		ldaxp w9, w10, [x0]
+#    x9: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#   x10: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  c87fb00b		ldaxp x11, x12, [x0]
+#   x11: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#   x12: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  885ffc0d		ldaxr w13, [x0]
+#   x13: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  c85ffc0e		ldaxr x14, [x0]
+#   x14: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  085ffc0f		ldaxrb w15, [x0]
+#   x15: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  085ffc10		ldaxrb w16, [x0]
+#   x16: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  485ffc11		ldaxrh w17, [x0]
+#   x17: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  485ffc12		ldaxrh w18, [x0]
+#   x18: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  28405013		ldnp w19, w20, [x0]
+#   x19: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#   x20: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a8405815		ldnp x21, x22, [x0]
+#   x21: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#   x22: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  29406017		ldp w23, w24, [x0]
+#   x23: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#   x24: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  28c16037		ldp w23, w24, [x1], #8
+#   x23: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#   x24: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  29c16037		ldp w23, w24, [x1, #8]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   x23: 0x0000000013121110 <- 0x~~~~~~~~~~~~~~~~
+#   x24: 0x0000000017161514 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a9406819		ldp x25, x26, [x0]
+#   x25: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#   x26: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a8c16839		ldp x25, x26, [x1], #16
+#   x25: 0x1716151413121110 <- 0x~~~~~~~~~~~~~~~~
+#   x26: 0x1f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a9c16839		ldp x25, x26, [x1, #16]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   x25: 0x3736353433323130 <- 0x~~~~~~~~~~~~~~~~
+#   x26: 0x3f3e3d3c3b3a3938 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  6940701b		ldpsw x27, x28, [x0]
+#   x27: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#   x28: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  68c1703b		ldpsw x27, x28, [x1], #8
+#   x27: 0x0000000033323130 <- 0x~~~~~~~~~~~~~~~~
+#   x28: 0x0000000037363534 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  69c1703b		ldpsw x27, x28, [x1, #8]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   x27: 0x0000000043424140 <- 0x~~~~~~~~~~~~~~~~
+#   x28: 0x0000000047464544 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  b940001d		ldr w29, [x0]
+#   x29: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  b840443d		ldr w29, [x1], #4
+#   x29: 0x0000000043424140 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  b8404c3d		ldr w29, [x1, #4]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   x29: 0x000000004b4a4948 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  f9400002		ldr x2, [x0]
+#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  f8408422		ldr x2, [x1], #8
+#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  f8408c22		ldr x2, [x1, #8]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  39400003		ldrb w3, [x0]
+#    x3: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  38401423		ldrb w3, [x1], #1
+#    x3: 0x0000000000000058 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  38401c23		ldrb w3, [x1, #1]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x3: 0x000000000000005a <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  39400004		ldrb w4, [x0]
+#    x4: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  38401424		ldrb w4, [x1], #1
+#    x4: 0x000000000000005a <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  38401c24		ldrb w4, [x1, #1]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x4: 0x000000000000005c <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  79400005		ldrh w5, [x0]
+#    x5: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  78402425		ldrh w5, [x1], #2
+#    x5: 0x0000000000005d5c <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  78402c25		ldrh w5, [x1, #2]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x5: 0x0000000000006160 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  79400006		ldrh w6, [x0]
+#    x6: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  78402426		ldrh w6, [x1], #2
+#    x6: 0x0000000000006160 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  78402c26		ldrh w6, [x1, #2]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x6: 0x0000000000006564 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  39c00007		ldrsb w7, [x0]
+#    x7: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  38c01427		ldrsb w7, [x1], #1
+#    x7: 0x0000000000000064 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  38c01c27		ldrsb w7, [x1, #1]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x7: 0x0000000000000066 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  39800008		ldrsb x8, [x0]
+#    x8: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  38801428		ldrsb x8, [x1], #1
+#    x8: 0x0000000000000066 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  38801c28		ldrsb x8, [x1, #1]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x8: 0x0000000000000068 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  79c00009		ldrsh w9, [x0]
+#    x9: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  78c02429		ldrsh w9, [x1], #2
+#    x9: 0x0000000000006968 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  78c02c29		ldrsh w9, [x1, #2]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x9: 0x0000000000006d6c <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  7980000a		ldrsh x10, [x0]
+#   x10: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  7880242a		ldrsh x10, [x1], #2
+#   x10: 0x0000000000006d6c <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  78802c2a		ldrsh x10, [x1, #2]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   x10: 0x0000000000007170 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  b980000b		ldrsw x11, [x0]
+#   x11: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  b880442b		ldrsw x11, [x1], #4
+#   x11: 0x0000000073727170 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  b8804c2b		ldrsw x11, [x1, #4]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   x11: 0x000000007b7a7978 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  b840700c		ldur w12, [x0, #7]
+#   x12: 0x000000000a090807 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  f840f00d		ldur x13, [x0, #15]
+#   x13: 0x161514131211100f <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  3840100e		ldurb w14, [x0, #1]
+#   x14: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  3840100f		ldurb w15, [x0, #1]
+#   x15: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  78403010		ldurh w16, [x0, #3]
+#   x16: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  78403011		ldurh w17, [x0, #3]
+#   x17: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  38c01012		ldursb w18, [x0, #1]
+#   x18: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  38801013		ldursb x19, [x0, #1]
+#   x19: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  78c03014		ldursh w20, [x0, #3]
+#   x20: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  78803015		ldursh x21, [x0, #3]
+#   x21: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  b8807016		ldursw x22, [x0, #7]
+#   x22: 0x000000000a090807 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  887f6017		ldxp w23, w24, [x0]
+#   x23: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#   x24: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  c87f6819		ldxp x25, x26, [x0]
+#   x25: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#   x26: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  885f7c1b		ldxr w27, [x0]
+#   x27: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  c85f7c1c		ldxr x28, [x0]
+#   x28: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  085f7c1d		ldxrb w29, [x0]
+#   x29: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  085f7c02		ldxrb w2, [x0]
+#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  485f7c03		ldxrh w3, [x0]
+#    x3: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  485f7c04		ldxrh w4, [x0]
+#    x4: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  531e74c5		lsl w5, w6, #2
+#    x5: 0x0000000000019590
+0x~~~~~~~~~~~~~~~~  d37df107		lsl x7, x8, #3
+#    x7: 0x0000000000000340
+0x~~~~~~~~~~~~~~~~  1acb2149		lsl w9, w10, w11
+#    x9: 0x0000000070000000
+0x~~~~~~~~~~~~~~~~  9ace21ac		lsl x12, x13, x14
+#   x12: 0x2c2a28262422201e
+0x~~~~~~~~~~~~~~~~  53047e0f		lsr w15, w16, #4
+#   x15: 0x0000000000000040
+0x~~~~~~~~~~~~~~~~  d345fe51		lsr x17, x18, #5
+#   x17: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  1ad52693		lsr w19, w20, w21
+#   x19: 0x0000000000000080
+0x~~~~~~~~~~~~~~~~  9ad826f6		lsr x22, x23, x24
+#   x22: 0x0000000000302010
+0x~~~~~~~~~~~~~~~~  1b1b7359		madd w25, w26, w27, w28
+#   x25: 0x00000000371b0900
+0x~~~~~~~~~~~~~~~~  9b03105d		madd x29, x2, x3, x4
+#   x29: 0x0000000000000100
+0x~~~~~~~~~~~~~~~~  1b07fcc5		mneg w5, w6, w7
+#    x5: 0x00000000feb67b00
+0x~~~~~~~~~~~~~~~~  9b0afd28		mneg x8, x9, x10
+#    x8: 0xffffce5f00000000
+0x~~~~~~~~~~~~~~~~  2a0c03eb		mov w11, w12
+#   x11: 0x000000002422201e
+0x~~~~~~~~~~~~~~~~  aa0e03ed		mov x13, x14
+#   x13: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  7280104f		movk w15, #0x82
+#   x15: 0x0000000000000082
+0x~~~~~~~~~~~~~~~~  f2801070		movk x16, #0x83
+#   x16: 0x0000000000000083
+0x~~~~~~~~~~~~~~~~  12801091		mov w17, #0xffffff7b
+#   x17: 0x00000000ffffff7b
+0x~~~~~~~~~~~~~~~~  928010b2		mov x18, #0xffffffffffffff7a
+#   x18: 0xffffffffffffff7a
+0x~~~~~~~~~~~~~~~~  528010d3		mov w19, #0x86
+#   x19: 0x0000000000000086
+0x~~~~~~~~~~~~~~~~  d28010f4		mov x20, #0x87
+#   x20: 0x0000000000000087
+0x~~~~~~~~~~~~~~~~  1b18e6f6		msub w22, w23, w24, w25
+#   x22: 0x000000001b0e0500
+0x~~~~~~~~~~~~~~~~  9b1cf77a		msub x26, x27, x28, x29
+#   x26: 0xe3e9eff5fbff0100
+0x~~~~~~~~~~~~~~~~  1b047c62		mul w2, w3, w4
+#    x2: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  9b077cc5		mul x5, x6, x7
+#    x5: 0x0000000001498500
+0x~~~~~~~~~~~~~~~~  2a2903e8		mvn w8, w9
+#    x8: 0x000000008fffffff
+0x~~~~~~~~~~~~~~~~  aa2b03ea		mvn x10, x11
+#   x10: 0xffffffffdbdddfe1
+0x~~~~~~~~~~~~~~~~  4b0d03ec		neg w12, w13
+#   x12: 0x00000000ffffffff
+0x~~~~~~~~~~~~~~~~  cb0f03ee		neg x14, x15
+#   x14: 0xffffffffffffff7e
+0x~~~~~~~~~~~~~~~~  6b1103f0		negs w16, w17
+# NZCV: N:0 Z:0 C:0 V:0
+#   x16: 0x0000000000000085
+0x~~~~~~~~~~~~~~~~  eb1303f2		negs x18, x19
+# NZCV: N:1 Z:0 C:0 V:0
+#   x18: 0xffffffffffffff7a
+0x~~~~~~~~~~~~~~~~  5a1503f4		ngc w20, w21
+#   x20: 0x00000000fffffbfc
+0x~~~~~~~~~~~~~~~~  da1703f6		ngc x22, x23
+#   x22: 0xfffffffffcfdfeff
+0x~~~~~~~~~~~~~~~~  7a1903f8		ngcs w24, w25
+# NZCV: N:1 Z:0 C:0 V:0
+#   x24: 0x00000000c8e4f6ff
+0x~~~~~~~~~~~~~~~~  fa1b03fa		ngcs x26, x27
+# NZCV: N:1 Z:0 C:0 V:0
+#   x26: 0xfffffffffcfdfeff
+0x~~~~~~~~~~~~~~~~  d503201f		nop
+0x~~~~~~~~~~~~~~~~  2a2203bc		orn w28, w29, w2
+#   x28: 0x00000000fffeffff
+0x~~~~~~~~~~~~~~~~  aa250083		orn x3, x4, x5
+#    x3: 0xfffffffffeb67bff
+0x~~~~~~~~~~~~~~~~  2a0800e6		orr w6, w7, w8
+#    x6: 0x000000008fffffff
+0x~~~~~~~~~~~~~~~~  aa0b0149		orr x9, x10, x11
+#    x9: 0xffffffffffffffff
+0x~~~~~~~~~~~~~~~~  f8804000		prfum pldl1keep, [x0, #4]
+0x~~~~~~~~~~~~~~~~  f8801000		prfum pldl1keep, [x0, #1]
+0x~~~~~~~~~~~~~~~~  5ac001ac		rbit w12, w13
+#   x12: 0x0000000080000000
+0x~~~~~~~~~~~~~~~~  dac001ee		rbit x14, x15
+#   x14: 0x4100000000000000
+0x~~~~~~~~~~~~~~~~  5ac00a30		rev w16, w17
+#   x16: 0x000000007bffffff
+0x~~~~~~~~~~~~~~~~  dac00e72		rev x18, x19
+#   x18: 0x8600000000000000
+0x~~~~~~~~~~~~~~~~  5ac006b4		rev16 w20, w21
+#   x20: 0x0000000000000304
+0x~~~~~~~~~~~~~~~~  dac006f6		rev16 x22, x23
+#   x22: 0x0000000002030001
+0x~~~~~~~~~~~~~~~~  dac00b38		rev32 x24, x25
+#   x24: 0x0000000000091b37
+0x~~~~~~~~~~~~~~~~  1adc2f7a		ror w26, w27, w28
+#   x26: 0x0000000006040200
+0x~~~~~~~~~~~~~~~~  9ac32c5d		ror x29, x2, x3
+#   x29: 0x0000000000020000
+0x~~~~~~~~~~~~~~~~  5a0600a4		sbc w4, w5, w6
+#    x4: 0x0000000071498500
+0x~~~~~~~~~~~~~~~~  da090107		sbc x7, x8, x9
+#    x7: 0x000000008fffffff
+0x~~~~~~~~~~~~~~~~  7a0c016a		sbcs w10, w11, w12
+# NZCV: N:1 Z:0 C:0 V:1
+#   x10: 0x00000000a422201d
+0x~~~~~~~~~~~~~~~~  fa0f01cd		sbcs x13, x14, x15
+# NZCV: N:0 Z:0 C:1 V:0
+#   x13: 0x40ffffffffffff7d
+0x~~~~~~~~~~~~~~~~  131e0a30		sbfiz w16, w17, #2, #3
+#   x16: 0x000000000000000c
+0x~~~~~~~~~~~~~~~~  937c1272		sbfiz x18, x19, #4, #5
+#   x18: 0x0000000000000060
+0x~~~~~~~~~~~~~~~~  130632f6		sbfx w22, w23, #6, #7
+#   x22: 0x0000000000000004
+0x~~~~~~~~~~~~~~~~  93484338		sbfx x24, x25, #8, #9
+#   x24: 0xffffffffffffff09
+0x~~~~~~~~~~~~~~~~  1adc0f7a		sdiv w26, w27, w28
+#   x26: 0x00000000fffffcff
+0x~~~~~~~~~~~~~~~~  9ac30c5d		sdiv x29, x2, x3
+#   x29: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  9b4e7dac		smulh x12, x13, x14
+#   x12: 0x1080ffffffffffde
+0x~~~~~~~~~~~~~~~~  889ffc12		stlr w18, [x0]
+#   w18:         0x00000060 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  c89ffc13		stlr x19, [x0]
+#   x19: 0x0000000000000086 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  089ffc14		stlrb w20, [x0]
+#   w20<7:0>:          0x04 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  089ffc15		stlrb w21, [x0]
+#   w21<7:0>:          0x03 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  489ffc16		stlrh w22, [x0]
+#   w22<15:0>:       0x0004 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  489ffc17		stlrh w23, [x0]
+#   w23<15:0>:       0x0100 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  8838e819		stlxp w24, w25, w26, [x0]
+#   x24: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  c83bf41c		stlxp w27, x28, x29, [x0]
+#   x27: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  8802fc03		stlxr w2, w3, [x0]
+#    x2: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  c804fc05		stlxr w4, x5, [x0]
+#    x4: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  0806fc07		stlxrb w6, w7, [x0]
+#    x6: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  0808fc09		stlxrb w8, w9, [x0]
+#    x8: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  480afc0b		stlxrh w10, w11, [x0]
+#   x10: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  480cfc0d		stlxrh w12, w13, [x0]
+#   x12: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  28003c0e		stnp w14, w15, [x0]
+#   w14:         0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#   w15:         0x00000082 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a8004410		stnp x16, x17, [x0]
+#   x16: 0x000000000000000c -> 0x~~~~~~~~~~~~~~~~
+#   x17: 0x00000000ffffff7b -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  29004c12		stp w18, w19, [x0]
+#   w18:         0x00000060 -> 0x~~~~~~~~~~~~~~~~
+#   w19:         0x00000086 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  28814c32		stp w18, w19, [x1], #8
+#   w18:         0x00000060 -> 0x~~~~~~~~~~~~~~~~
+#   w19:         0x00000086 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  29814c32		stp w18, w19, [x1, #8]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   w18:         0x00000060 -> 0x~~~~~~~~~~~~~~~~
+#   w19:         0x00000086 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a9005414		stp x20, x21, [x0]
+#   x20: 0x0000000000000304 -> 0x~~~~~~~~~~~~~~~~
+#   x21: 0x0000000000000403 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a8815434		stp x20, x21, [x1], #16
+#   x20: 0x0000000000000304 -> 0x~~~~~~~~~~~~~~~~
+#   x21: 0x0000000000000403 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a9815434		stp x20, x21, [x1, #16]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   x20: 0x0000000000000304 -> 0x~~~~~~~~~~~~~~~~
+#   x21: 0x0000000000000403 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  b9000016		str w22, [x0]
+#   w22:         0x00000004 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  b8004436		str w22, [x1], #4
+#   w22:         0x00000004 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  b8004c36		str w22, [x1, #4]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   w22:         0x00000004 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  f9000017		str x23, [x0]
+#   x23: 0x0000000003020100 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  f8008437		str x23, [x1], #8
+#   x23: 0x0000000003020100 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  f8008c37		str x23, [x1, #8]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   x23: 0x0000000003020100 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  39000018		strb w24, [x0]
+#   w24<7:0>:          0x01 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  38001438		strb w24, [x1], #1
+#   w24<7:0>:          0x01 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  38001c38		strb w24, [x1, #1]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   w24<7:0>:          0x01 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  39000019		strb w25, [x0]
+#   w25<7:0>:          0x00 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  38001439		strb w25, [x1], #1
+#   w25<7:0>:          0x00 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  38001c39		strb w25, [x1, #1]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   w25<7:0>:          0x00 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  7900001a		strh w26, [x0]
+#   w26<15:0>:       0xfcff -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  7800243a		strh w26, [x1], #2
+#   w26<15:0>:       0xfcff -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  78002c3a		strh w26, [x1, #2]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   w26<15:0>:       0xfcff -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  7900001b		strh w27, [x0]
+#   w27<15:0>:       0x0001 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  7800243b		strh w27, [x1], #2
+#   w27<15:0>:       0x0001 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  78002c3b		strh w27, [x1, #2]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   w27<15:0>:       0x0001 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  b800701c		stur w28, [x0, #7]
+#   w28:         0xfffeffff -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  f800f01d		stur x29, [x0, #15]
+#   x29: 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  38001002		sturb w2, [x0, #1]
+#    w2<7:0>:          0x01 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  38001003		sturb w3, [x0, #1]
+#    w3<7:0>:          0xff -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  78003004		sturh w4, [x0, #3]
+#    w4<15:0>:       0x0001 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  78003005		sturh w5, [x0, #3]
+#    w5<15:0>:       0x8500 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  88262007		stxp w6, w7, w8, [x0]
+#    x6: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  c8292c0a		stxp w9, x10, x11, [x0]
+#    x9: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  880c7c0d		stxr w12, w13, [x0]
+#   x12: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  c80e7c0f		stxr w14, x15, [x0]
+#   x14: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  08107c11		stxrb w16, w17, [x0]
+#   x16: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  08127c13		stxrb w18, w19, [x0]
+#   x18: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  48147c15		stxrh w20, w21, [x0]
+#   x20: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  48167c17		stxrh w22, w23, [x0]
+#   x22: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  4b1a0338		sub w24, w25, w26
+#   x24: 0x00000000371b0c01
+0x~~~~~~~~~~~~~~~~  cb1d039b		sub x27, x28, x29
+#   x27: 0x00000000fffeffff
+0x~~~~~~~~~~~~~~~~  6b040062		subs w2, w3, w4
+# NZCV: N:1 Z:0 C:1 V:0
+#    x2: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  eb0700c5		subs x5, x6, x7
+# NZCV: N:1 Z:0 C:0 V:0
+#    x5: 0xffffffff70000002
+0x~~~~~~~~~~~~~~~~  13001d28		sxtb w8, w9
+#    x8: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  93401d6a		sxtb x10, w11
+#   x10: 0x000000000000001e
+0x~~~~~~~~~~~~~~~~  13003dac		sxth w12, w13
+#   x12: 0x00000000ffffff7d
+0x~~~~~~~~~~~~~~~~  93403dee		sxth x14, w15
+#   x14: 0x0000000000000082
+0x~~~~~~~~~~~~~~~~  13007e30		sbfx w16, w17, #0, #32
+#   x16: 0x00000000ffffff7b
+0x~~~~~~~~~~~~~~~~  93407e72		sxtw x18, w19
+#   x18: 0x0000000000000086
+0x~~~~~~~~~~~~~~~~  6a15029f		tst w20, w21
+# NZCV: N:0 Z:0 C:0 V:0
+0x~~~~~~~~~~~~~~~~  ea1702df		tst x22, x23
+# NZCV: N:0 Z:1 C:0 V:0
+0x~~~~~~~~~~~~~~~~  53162b38		ubfiz w24, w25, #10, #11
+#   x24: 0x0000000000040000
+0x~~~~~~~~~~~~~~~~  d374337a		ubfiz x26, x27, #12, #13
+#   x26: 0x0000000001fff000
+0x~~~~~~~~~~~~~~~~  530e3fbc		ubfx w28, w29, #14, #2
+#   x28: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  d3410862		ubfx x2, x3, #1, #2
+#    x2: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  530318a4		ubfx w4, w5, #3, #4
+#    x4: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  d34528e6		ubfx x6, x7, #5, #6
+#    x6: 0x000000000000003f
+0x~~~~~~~~~~~~~~~~  1aca0928		udiv w8, w9, w10
+#    x8: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  9acd098b		udiv x11, x12, x13
+#   x11: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  9bd87ef6		umulh x22, x23, x24
+#   x22: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  53001fbc		uxtb w28, w29
+#   x28: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  d3401c62		uxtb x2, w3
+#    x2: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  53003ca4		uxth w4, w5
+#    x4: 0x0000000000000002
+0x~~~~~~~~~~~~~~~~  d3403ce6		uxth x6, w7
+#    x6: 0x000000000000ffff
+0x~~~~~~~~~~~~~~~~  53007d28		lsr w8, w9, #0
+#    x8: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  d3407d6a		ubfx x10, x11, #0, #32
+#   x10: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  7ef3d44d		fabd d13, d2, d19
+#   v13: 0x00000000000000004036e00cd9b7e45b
+0x~~~~~~~~~~~~~~~~  7ebed548		fabd s8, s10, s30
+#    v8: 0x00000000000000000000000041c5851e
+0x~~~~~~~~~~~~~~~~  1e60c021		fabs d1, d1
+#    v1: 0x00000000000000003ff587933f9e0419 (d1: 1.34560)
+0x~~~~~~~~~~~~~~~~  1e20c0f9		fabs s25, s7
+#   v25: 0x000000000000000000000000410a4396 (s25: 8.64150)
+0x~~~~~~~~~~~~~~~~  7e70eee1		facge d1, d23, d16
+#    v1: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  7e21ee24		facge s4, s17, s1
+#    v4: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7ef8eea2		facgt d2, d21, d24
+#    v2: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7eacef4c		facgt s12, s26, s12
+#   v12: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  1e76296d		fadd d13, d11, d22
+#   v13: 0x0000000000000000404633d07142f43a (d13: 44.4048)
+0x~~~~~~~~~~~~~~~~  1e282a7b		fadd s27, s19, s8
+#   v27: 0x000000000000000000000000424094fe (s27: 48.1455)
+0x~~~~~~~~~~~~~~~~  1e6a24c0		fccmp d6, d10, #nzcv, hs
+# NZCV: N:0 Z:0 C:0 V:0
+0x~~~~~~~~~~~~~~~~  1e3417ad		fccmp s29, s20, #NZcV, ne
+# NZCV: N:0 Z:0 C:1 V:0
+0x~~~~~~~~~~~~~~~~  1e62e55e		fccmpe d10, d2, #NZCv, al
+# NZCV: N:0 Z:0 C:1 V:0
+0x~~~~~~~~~~~~~~~~  1e23547d		fccmpe s3, s3, #NZcV, pl
+# NZCV: N:0 Z:1 C:1 V:0
+0x~~~~~~~~~~~~~~~~  5e6ae513		fcmeq d19, d8, d10
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5ee0da40		fcmeq d0, d18, #0.0
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5e3ee481		fcmeq s1, s4, s30
+#    v1: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5ea0dbb6		fcmeq s22, s29, #0.0
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7e61e65b		fcmge d27, d18, d1
+#   v27: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  7ee0cb9f		fcmge d31, d28, #0.0
+#   v31: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  7e29e67f		fcmge s31, s19, s9
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7ea0cb21		fcmge s1, s25, #0.0
+#    v1: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  7eefe432		fcmgt d18, d1, d15
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5ee0cbe3		fcmgt d3, d31, #0.0
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7ea2e72b		fcmgt s11, s25, s2
+#   v11: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  5ea0ca11		fcmgt s17, s16, #0.0
+#   v17: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  7ee0da38		fcmle d24, d17, #0.0
+#   v24: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7ea0d90b		fcmle s11, s8, #0.0
+#   v11: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5ee0ebe5		fcmlt d5, d31, #0.0
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5ea0eaf2		fcmlt s18, s23, #0.0
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  1e782140		fcmp d10, d24
+# NZCV: N:0 Z:0 C:1 V:0
+0x~~~~~~~~~~~~~~~~  1e6021a8		fcmp d13, #0.0
+# NZCV: N:0 Z:0 C:1 V:0
+0x~~~~~~~~~~~~~~~~  1e262240		fcmp s18, s6
+# NZCV: N:1 Z:0 C:0 V:0
+0x~~~~~~~~~~~~~~~~  1e202208		fcmp s16, #0.0
+# NZCV: N:0 Z:0 C:1 V:0
+0x~~~~~~~~~~~~~~~~  1e712130		fcmpe d9, d17
+# NZCV: N:0 Z:0 C:1 V:0
+0x~~~~~~~~~~~~~~~~  1e6023b8		fcmpe d29, #0.0
+# NZCV: N:0 Z:0 C:1 V:0
+0x~~~~~~~~~~~~~~~~  1e312210		fcmpe s16, s17
+# NZCV: N:0 Z:0 C:1 V:1
+0x~~~~~~~~~~~~~~~~  1e2022d8		fcmpe s22, #0.0
+# NZCV: N:0 Z:1 C:1 V:0
+0x~~~~~~~~~~~~~~~~  1e73cdca		fcsel d10, d14, d19, gt
+#   v10: 0x00000000000000000000000000000000 (d10: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e22ae56		fcsel s22, s18, s2, ge
+#   v22: 0x00000000000000000000000000000000 (s22: 0.00000)
+0x~~~~~~~~~~~~~~~~  1ee2c304		fcvt d4, h24
+#    v4: 0x00000000000000000000000000000000 (d4: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e22c04b		fcvt d11, s2
+#   v11: 0x00000000000000000000000000000000 (d11: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e63c128		fcvt h8, d9
+#    v8: 0x00000000000000000000000000004a0e
+0x~~~~~~~~~~~~~~~~  1e23c02c		fcvt h12, s1
+#   v12: 0x0000000000000000000000000000ffff
+0x~~~~~~~~~~~~~~~~  1e6243ec		fcvt s12, d31
+#   v12: 0x00000000000000000000000000000000 (s12: 0.00000)
+0x~~~~~~~~~~~~~~~~  1ee2433b		fcvt s27, h25
+#   v27: 0x0000000000000000000000004072c000 (s27: 3.79297)
+0x~~~~~~~~~~~~~~~~  5e61ca1c		fcvtas d28, d16
+#   v28: 0x00000000000000000000000000000016
+0x~~~~~~~~~~~~~~~~  5e21c8a3		fcvtas s3, s5
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  1e6403f2		fcvtas w18, d31
+#   x18: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  1e24031d		fcvtas w29, s24
+#   x29: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  9e640029		fcvtas x9, d1
+#    x9: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  9e24005e		fcvtas x30, s2
+#    lr: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  7e61c80e		fcvtau d14, d0
+#   v14: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7e21c9df		fcvtau s31, s14
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  1e650050		fcvtau w16, d2
+#   x16: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  1e250012		fcvtau w18, s0
+#   x18: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  9e6500fa		fcvtau x26, d7
+#   x26: 0x0000000000000009
+0x~~~~~~~~~~~~~~~~  9e250279		fcvtau x25, s19
+#   x25: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  5e61bb3e		fcvtms d30, d25
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5e21b9ec		fcvtms s12, s15
+#   v12: 0x00000000000000000000000000000012
+0x~~~~~~~~~~~~~~~~  1e7000e9		fcvtms w9, d7
+#    x9: 0x0000000000000009
+0x~~~~~~~~~~~~~~~~  1e3000d3		fcvtms w19, s6
+#   x19: 0x0000000000000007
+0x~~~~~~~~~~~~~~~~  9e7000c6		fcvtms x6, d6
+#    x6: 0x0000000000000008
+0x~~~~~~~~~~~~~~~~  9e3000f6		fcvtms x22, s7
+#   x22: 0x0000000000000008
+0x~~~~~~~~~~~~~~~~  7e61b81b		fcvtmu d27, d0
+#   v27: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7e21bac8		fcvtmu s8, s22
+#    v8: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  1e71027d		fcvtmu w29, d19
+#   x29: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  1e31001a		fcvtmu w26, s0
+#   x26: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  9e7100ad		fcvtmu x13, d5
+#   x13: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  9e310245		fcvtmu x5, s18
+#    x5: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  5e61a9fe		fcvtns d30, d15
+#   v30: 0x00000000000000000000000000000014
+0x~~~~~~~~~~~~~~~~  5e21a96a		fcvtns s10, s11
+#   v10: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  1e6001f5		fcvtns w21, d15
+#   x21: 0x0000000000000014
+0x~~~~~~~~~~~~~~~~  1e200152		fcvtns w18, s10
+#   x18: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  9e600228		fcvtns x8, d17
+#    x8: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  9e200191		fcvtns x17, s12
+#   x17: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  7e61aaa0		fcvtnu d0, d21
+#    v0: 0x0000000000000000000000000000001c
+0x~~~~~~~~~~~~~~~~  7e21ab26		fcvtnu s6, s25
+#    v6: 0x00000000000000000000000000000009
+0x~~~~~~~~~~~~~~~~  1e61017d		fcvtnu w29, d11
+#   x29: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  1e2103f9		fcvtnu w25, s31
+#   x25: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  9e61017e		fcvtnu x30, d11
+#    lr: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  9e21025b		fcvtnu x27, s18
+#   x27: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  5ee1aacb		fcvtps d11, d22
+#   v11: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5ea1aa9d		fcvtps s29, s20
+#   v29: 0x00000000000000000000000000000019
+0x~~~~~~~~~~~~~~~~  1e68032f		fcvtps w15, d25
+#   x15: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  1e2800f0		fcvtps w16, s7
+#   x16: 0x0000000000000009
+0x~~~~~~~~~~~~~~~~  9e68028d		fcvtps x13, d20
+#   x13: 0x000000000000001b
+0x~~~~~~~~~~~~~~~~  9e2802e3		fcvtps x3, s23
+#    x3: 0x000000000000001d
+0x~~~~~~~~~~~~~~~~  7ee1a838		fcvtpu d24, d1
+#   v24: 0x00000000000000000000000000000001
+0x~~~~~~~~~~~~~~~~  7ea1ab0e		fcvtpu s14, s24
+#   v14: 0x00000000000000000000000000000001
+0x~~~~~~~~~~~~~~~~  1e6903ba		fcvtpu w26, d29
+#   x26: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  1e29035f		fcvtpu wzr, s26
+0x~~~~~~~~~~~~~~~~  9e6900db		fcvtpu x27, d6
+#   x27: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  9e2901dd		fcvtpu x29, s14
+#   x29: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  7e61698c		fcvtxn s12, d12
+#   v12: 0x00000000000000000000000000000001
+0x~~~~~~~~~~~~~~~~  5ee1b80f		fcvtzs d15, d0
+#   v15: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5f56fc8d		fcvtzs d13, d4, #42
+#   v13: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5ea1b968		fcvtzs s8, s11
+#    v8: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5f27fcdf		fcvtzs s31, s6, #25
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  1e780126		fcvtzs w6, d9
+#    x6: 0x000000000000000c
+0x~~~~~~~~~~~~~~~~  1e58b159		fcvtzs w25, d10, #20
+#   x25: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  1e380029		fcvtzs w9, s1
+#    x9: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  1e188bb1		fcvtzs w17, s29, #30
+#   x17: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  9e780053		fcvtzs x19, d2
+#   x19: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  9e58fdd6		fcvtzs x22, d14, #1
+#   x22: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  9e38028e		fcvtzs x14, s20
+#   x14: 0x0000000000000018
+0x~~~~~~~~~~~~~~~~  9e187fc3		fcvtzs x3, s30, #33
+#    x3: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  7ee1b9fc		fcvtzu d28, d15
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7f7dfc80		fcvtzu d0, d4, #3
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7ea1b8a2		fcvtzu s2, s5
+#    v2: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7f22fc04		fcvtzu s4, s0, #30
+#    v4: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  1e79008b		fcvtzu w11, d4
+#   x11: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  1e598307		fcvtzu w7, d24, #32
+#    x7: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  1e390312		fcvtzu w18, s24
+#   x18: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  1e19f36e		fcvtzu w14, s27, #4
+#   x14: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  9e790176		fcvtzu x22, d11
+#   x22: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  9e593368		fcvtzu x8, d27, #52
+#    x8: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  9e390287		fcvtzu x7, s20
+#    x7: 0x0000000000000018
+0x~~~~~~~~~~~~~~~~  9e1950f6		fcvtzu x22, s7, #44
+#   x22: 0x00008a4396000000
+0x~~~~~~~~~~~~~~~~  1e6f19c6		fdiv d6, d14, d15
+#    v6: 0x00000000000000007ff0000000000000 (d6: inf)
+0x~~~~~~~~~~~~~~~~  1e3918ba		fdiv s26, s5, s25
+#   v26: 0x00000000000000000000000000000000 (s26: 0.00000)
+0x~~~~~~~~~~~~~~~~  1f4c7b52		fmadd d18, d26, d12, d30
+#   v18: 0x00000000000000000000000000000014 (d18: 9.88131e-323)
+0x~~~~~~~~~~~~~~~~  1f1c112d		fmadd s13, s9, s28, s4
+#   v13: 0x00000000000000000000000000000000 (s13: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e6548ac		fmax d12, d5, d5
+#   v12: 0x00000000000000000000000000000000 (d12: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e264b8c		fmax s12, s28, s6
+#   v12: 0x00000000000000000000000000000000 (s12: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e62689c		fmaxnm d28, d4, d2
+#   v28: 0x00000000000000000000000000000000 (d28: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e286946		fmaxnm s6, s10, s8
+#    v6: 0x00000000000000000000000000000000 (s6: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e725a94		fmin d20, d20, d18
+#   v20: 0x00000000000000000000000000000014 (d20: 9.88131e-323)
+0x~~~~~~~~~~~~~~~~  1e3059a7		fmin s7, s13, s16
+#    v7: 0x00000000000000000000000000000000 (s7: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e7e79d3		fminnm d19, d14, d30
+#   v19: 0x00000000000000000000000000000001 (d19: 4.94066e-324)
+0x~~~~~~~~~~~~~~~~  1e217820		fminnm s0, s1, s1
+#    v0: 0x000000000000000000000000ffffffff (s0: -nan)
+0x~~~~~~~~~~~~~~~~  1e6040cd		fmov d13, d6
+#   v13: 0x00000000000000000000000000000000 (d13: 0.00000)
+0x~~~~~~~~~~~~~~~~  9e670222		fmov d2, x17
+#    v2: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  1e709008		fmov d8, #0x84 (-2.5000)
+#    v8: 0x0000000000000000c004000000000000 (d8: -2.50000)
+0x~~~~~~~~~~~~~~~~  1e204065		fmov s5, s3
+#    v5: 0x00000000000000000000000000000000 (s5: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e270299		fmov s25, w20
+#   v25: 0x00000000000000000000000000000001
+0x~~~~~~~~~~~~~~~~  1e20f015		fmov s21, #0x7 (2.8750)
+#   v21: 0x00000000000000000000000040380000 (s21: 2.87500)
+0x~~~~~~~~~~~~~~~~  1e260312		fmov w18, s24
+#   x18: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  9e660052		fmov x18, d2
+#   x18: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  1f43cfd4		fmsub d20, d30, d3, d19
+#   v20: 0x00000000000000000000000000000001 (d20: 4.94066e-324)
+0x~~~~~~~~~~~~~~~~  1f04b265		fmsub s5, s19, s4, s12
+#    v5: 0x00000000000000000000000000000000 (s5: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e770b7e		fmul d30, d27, d23
+#   v30: 0x00000000000000000000000000000000 (d30: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e2f0a39		fmul s25, s17, s15
+#   v25: 0x000000000000000000000000ffffffff (s25: -nan)
+0x~~~~~~~~~~~~~~~~  5e61de24		fmulx d4, d17, d1
+#    v4: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5e24df2e		fmulx s14, s25, s4
+#   v14: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  1e61400f		fneg d15, d0
+#   v15: 0x000000000000000080000000ffffffff (d15: -2.12200e-314)
+0x~~~~~~~~~~~~~~~~  1e2141ee		fneg s14, s15
+#   v14: 0x0000000000000000000000007fffffff (s14: nan)
+0x~~~~~~~~~~~~~~~~  1f767e00		fnmadd d0, d16, d22, d31
+#    v0: 0x00000000000000008000000000000000 (d0: -0.00000)
+0x~~~~~~~~~~~~~~~~  1f3a4a40		fnmadd s0, s18, s26, s18
+#    v0: 0x00000000000000000000000080000014 (s0: -2.80260e-44)
+0x~~~~~~~~~~~~~~~~  1f6fd593		fnmsub d19, d12, d15, d21
+#   v19: 0x00000000000000008000000040380000 (d19: -5.32312e-315)
+0x~~~~~~~~~~~~~~~~  1f2be81d		fnmsub s29, s0, s11, s26
+#   v29: 0x00000000000000000000000080000000 (s29: -0.00000)
+0x~~~~~~~~~~~~~~~~  1e618a7f		fnmul d31, d19, d1
+#   v31: 0x00000000000000000000000000000000 (d31: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e318872		fnmul s18, s3, s17
+#   v18: 0x0000000000000000000000007fffffff (s18: nan)
+0x~~~~~~~~~~~~~~~~  5ee1daa7		frecpe d7, d21
+#    v7: 0x00000000000000007ff0000000000000
+0x~~~~~~~~~~~~~~~~  5ea1da3d		frecpe s29, s17
+#   v29: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  5e71ff4b		frecps d11, d26, d17
+#   v11: 0x00000000000000004000000000000000
+0x~~~~~~~~~~~~~~~~  5e21ff72		frecps s18, s27, s1
+#   v18: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  5ee1fa4f		frecpx d15, d18
+#   v15: 0x00000000000000007fe0000000000000
+0x~~~~~~~~~~~~~~~~  5ea1f945		frecpx s5, s10
+#    v5: 0x0000000000000000000000007f000000
+0x~~~~~~~~~~~~~~~~  1e6643d0		frinta d16, d30
+#   v16: 0x00000000000000000000000000000000 (d16: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e2642c1		frinta s1, s22
+#    v1: 0x00000000000000000000000000000000 (s1: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e67c3b3		frinti d19, d29
+#   v19: 0x00000000000000000000000000000000 (d19: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e27c2ae		frinti s14, s21
+#   v14: 0x00000000000000000000000040400000 (s14: 3.00000)
+0x~~~~~~~~~~~~~~~~  1e6543d4		frintm d20, d30
+#   v20: 0x00000000000000000000000000000000 (d20: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e254201		frintm s1, s16
+#    v1: 0x00000000000000000000000000000000 (s1: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e64403e		frintn d30, d1
+#   v30: 0x00000000000000000000000000000000 (d30: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e244158		frintn s24, s10
+#   v24: 0x00000000000000000000000000000000 (s24: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e64c284		frintp d4, d20
+#    v4: 0x00000000000000000000000000000000 (d4: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e24c06d		frintp s13, s3
+#   v13: 0x00000000000000000000000000000000 (s13: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e67428d		frintx d13, d20
+#   v13: 0x00000000000000000000000000000000 (d13: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e2740f1		frintx s17, s7
+#   v17: 0x00000000000000000000000000000000 (s17: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e65c100		frintz d0, d8
+#    v0: 0x0000000000000000c000000000000000 (d0: -2.00000)
+0x~~~~~~~~~~~~~~~~  1e25c3af		frintz s15, s29
+#   v15: 0x000000000000000000000000ffffffff (s15: -nan)
+0x~~~~~~~~~~~~~~~~  7ee1d955		frsqrte d21, d10
+#   v21: 0x00000000000000007ff0000000000000
+0x~~~~~~~~~~~~~~~~  7ea1db31		frsqrte s17, s25
+#   v17: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  5ef1ffa4		frsqrts d4, d29, d17
+#    v4: 0x00000000000000003ff8000000000000
+0x~~~~~~~~~~~~~~~~  5eb8fc6e		frsqrts s14, s3, s24
+#   v14: 0x0000000000000000000000003fc00000
+0x~~~~~~~~~~~~~~~~  1e61c22e		fsqrt d14, d17
+#   v14: 0x00000000000000001f5ffffffff00000 (d14: 1.45671e-157)
+0x~~~~~~~~~~~~~~~~  1e21c1c4		fsqrt s4, s14
+#    v4: 0x000000000000000000000000fff00000 (s4: -nan)
+0x~~~~~~~~~~~~~~~~  1e673a6d		fsub d13, d19, d7
+#   v13: 0x0000000000000000fff0000000000000 (d13: -inf)
+0x~~~~~~~~~~~~~~~~  1e3b3aa3		fsub s3, s21, s27
+#    v3: 0x00000000000000000000000000000000 (s3: 0.00000)
+0x~~~~~~~~~~~~~~~~  5e61da1f		scvtf d31, d16
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5f68e7fa		scvtf d26, d31, #24
+#   v26: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  1e620206		scvtf d6, w16
+#    v6: 0x00000000000000004022000000000000 (d6: 9.00000)
+0x~~~~~~~~~~~~~~~~  1e42ea85		scvtf d5, w20, #6
+#    v5: 0x00000000000000003f90000000000000 (d5: 0.0156250)
+0x~~~~~~~~~~~~~~~~  9e620110		scvtf d16, x8
+#   v16: 0x00000000000000000000000000000000 (d16: 0.00000)
+0x~~~~~~~~~~~~~~~~  9e42d90f		scvtf d15, x8, #10
+#   v15: 0x00000000000000000000000000000000 (d15: 0.00000)
+0x~~~~~~~~~~~~~~~~  5e21d887		scvtf s7, s4
+#    v7: 0x00000000000000007ff00000c9800000
+0x~~~~~~~~~~~~~~~~  5f32e5e8		scvtf s8, s15, #14
+#    v8: 0x0000000000000000c004000000000000
+0x~~~~~~~~~~~~~~~~  1e22015d		scvtf s29, w10
+#   v29: 0x00000000000000000000000000000000 (s29: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e02d6af		scvtf s15, w21, #11
+#   v15: 0x0000000000000000000000003c200000 (s15: 0.00976562)
+0x~~~~~~~~~~~~~~~~  9e22035b		scvtf s27, x26
+#   v27: 0x0000000000000000000000003f800000 (s27: 1.00000)
+0x~~~~~~~~~~~~~~~~  9e02699a		scvtf s26, x12, #38
+#   v26: 0x0000000000000000000000003c7fffff (s26: 0.0156250)
+0x~~~~~~~~~~~~~~~~  7e61d920		ucvtf d0, d9
+#    v0: 0x000000000000000043d00a0e21904c71
+0x~~~~~~~~~~~~~~~~  7f51e6c5		ucvtf d5, d22, #47
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  1e63037e		ucvtf d30, w27
+#   v30: 0x00000000000000003ff0000000000000 (d30: 1.00000)
+0x~~~~~~~~~~~~~~~~  1e43fe63		ucvtf d3, w19, #1
+#    v3: 0x00000000000000000000000000000000 (d3: 0.00000)
+0x~~~~~~~~~~~~~~~~  9e6302bc		ucvtf d28, x21
+#   v28: 0x00000000000000004034000000000000 (d28: 20.0000)
+0x~~~~~~~~~~~~~~~~  9e4377db		ucvtf d27, x30, #35
+#   v27: 0x00000000000000000000000000000000 (d27: 0.00000)
+0x~~~~~~~~~~~~~~~~  7e21d8ab		ucvtf s11, s5
+#   v11: 0x00000000000000004000000000000000
+0x~~~~~~~~~~~~~~~~  7f32e6e0		ucvtf s0, s23, #14
+#    v0: 0x000000000000000043d00a0e4783c64c
+0x~~~~~~~~~~~~~~~~  1e230274		ucvtf s20, w19
+#   v20: 0x00000000000000000000000000000000 (s20: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e03bad5		ucvtf s21, w22, #18
+#   v21: 0x00000000000000000000000046160000 (s21: 9600.00)
+0x~~~~~~~~~~~~~~~~  9e2301a6		ucvtf s6, x13
+#    v6: 0x00000000000000000000000041d80000 (s6: 27.0000)
+0x~~~~~~~~~~~~~~~~  9e03ac47		ucvtf s7, x2, #21
+#    v7: 0x00000000000000000000000038ff0000 (s7: 0.000121593)
+0x~~~~~~~~~~~~~~~~  5ee0b813		abs d19, d0
+#   v19: 0x000000000000000043d00a0e4783c64c
+0x~~~~~~~~~~~~~~~~  4e20b970		abs v16.16b, v11.16b
+#   v16: 0x00000000000000004000000000000000
+0x~~~~~~~~~~~~~~~~  4ee0bbe0		abs v0.2d, v31.2d
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ea0bb3b		abs v27.2s, v25.2s
+#   v27: 0x00000000000000000000000000000001
+0x~~~~~~~~~~~~~~~~  0e60bb75		abs v21.4h, v27.4h
+#   v21: 0x00000000000000000000000000000001
+0x~~~~~~~~~~~~~~~~  4ea0b830		abs v16.4s, v1.4s
+#   v16: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e20b8bf		abs v31.8b, v5.8b
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e60b9bd		abs v29.8h, v13.8h
+#   v29: 0x00000000000000000010000000000000
+0x~~~~~~~~~~~~~~~~  5ef184aa		add d10, d5, d17
+#   v10: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  4e3785ff		add v31.16b, v15.16b, v23.16b
+#   v31: 0x403ba7b141b670b1403ef2e47d0325e4
+0x~~~~~~~~~~~~~~~~  4eee87ea		add v10.2d, v31.2d, v14.2d
+#   v10: 0x403ba7b141b670b15f9ef2e47cf325e4
+0x~~~~~~~~~~~~~~~~  0eb385cf		add v15.2s, v14.2s, v19.2s
+#   v15: 0x000000000000000063300a0d4773c64c
+0x~~~~~~~~~~~~~~~~  0e7186fb		add v27.4h, v23.4h, v17.4h
+#   v27: 0x0000000000000000403ef2e441e225e3
+0x~~~~~~~~~~~~~~~~  4ebd8799		add v25.4s, v28.4s, v29.4s
+#   v25: 0x00000000000000004044000000000000
+0x~~~~~~~~~~~~~~~~  0e3284ed		add v13.8b, v7.8b, v18.8b
+#   v13: 0x00000000000000000000000037feffff
+0x~~~~~~~~~~~~~~~~  4e618444		add v4.8h, v2.8h, v1.8h
+#    v4: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0eaf41ca		addhn v10.2s, v14.2d, v15.2d
+#   v10: 0x00000000000000000000000082900a0d
+0x~~~~~~~~~~~~~~~~  0e7a43ca		addhn v10.4h, v30.4s, v26.4s
+#   v10: 0x0000000000000000000000003ff03c7f
+0x~~~~~~~~~~~~~~~~  0e36419f		addhn v31.8b, v12.8h, v22.8h
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e3442b0		addhn2 v16.16b, v21.8h, v20.8h
+#   v16: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4eb14040		addhn2 v0.4s, v2.2d, v17.2d
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e7140ff		addhn2 v31.8h, v7.4s, v17.4s
+#   v31: 0x00000000000038fe0000000000000000
+0x~~~~~~~~~~~~~~~~  5ef1ba6e		addp d14, v19.2d
+#   v14: 0x000000000000000043d00a0e4783c64c
+0x~~~~~~~~~~~~~~~~  4e3cbd03		addp v3.16b, v8.16b, v28.16b
+#    v3: 0x000000007400000000000000c4000000
+0x~~~~~~~~~~~~~~~~  4ef1bca8		addp v8.2d, v5.2d, v17.2d
+#    v8: 0x00000000ffffffff0000000000000000
+0x~~~~~~~~~~~~~~~~  0ebabfd6		addp v22.2s, v30.2s, v26.2s
+#   v22: 0x00000000000000003c7fffff3ff00000
+0x~~~~~~~~~~~~~~~~  0e6ebf1d		addp v29.4h, v24.4h, v14.4h
+#   v29: 0x00000000000000004dde0dcf00000000
+0x~~~~~~~~~~~~~~~~  4eb8bf5e		addp v30.4s, v26.4s, v24.4s
+#   v30: 0x0000000000000000000000003c7fffff
+0x~~~~~~~~~~~~~~~~  0e27bf4c		addp v12.8b, v26.8b, v7.8b
+#   v12: 0x0000000000000000000037000000bbfe
+0x~~~~~~~~~~~~~~~~  4e6cbd11		addp v17.8h, v8.8h, v12.8h
+#   v17: 0x000000003700bbfe0000fffe00000000
+0x~~~~~~~~~~~~~~~~  4e31bafb		addv b27, v23.16b
+#   v27: 0x0000000000000000000000000000006c
+0x~~~~~~~~~~~~~~~~  0e31ba8c		addv b12, v20.8b
+#   v12: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e71bbdb		addv h27, v30.4h
+#   v27: 0x00000000000000000000000000003c7e
+0x~~~~~~~~~~~~~~~~  4e71b9d3		addv h19, v14.8h
+#   v19: 0x00000000000000000000000000005bad
+0x~~~~~~~~~~~~~~~~  4eb1bb6e		addv s14, v27.4s
+#   v14: 0x00000000000000000000000000003c7e
+0x~~~~~~~~~~~~~~~~  4e3b1d0a		and v10.16b, v8.16b, v27.16b
+#   v10: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e301c25		and v5.8b, v1.8b, v16.8b
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e781c7a		bic v26.16b, v3.16b, v24.16b
+#   v26: 0x000000007400000000000000c4000000
+0x~~~~~~~~~~~~~~~~  2f075487		bic v7.2s, #0xe4, lsl #16
+#    v7: 0x000000000000000000000000381b0000
+0x~~~~~~~~~~~~~~~~  2f01b47c		bic v28.4h, #0x23, lsl #8
+#   v28: 0x00000000000000004034000000000000
+0x~~~~~~~~~~~~~~~~  6f05159d		bic v29.4s, #0xac, lsl #0
+#   v29: 0x00000000000000004dde0d4300000000
+0x~~~~~~~~~~~~~~~~  0e751fec		bic v12.8b, v31.8b, v21.8b
+#   v12: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f049712		bic v18.8h, #0x98, lsl #0
+#   v18: 0x000000000000000000000000ff67ff67
+0x~~~~~~~~~~~~~~~~  6ee81f4c		bif v12.16b, v26.16b, v8.16b
+#   v12: 0x000000000000000000000000c4000000
+0x~~~~~~~~~~~~~~~~  2efb1ee2		bif v2.8b, v23.8b, v27.8b
+#    v2: 0x0000000000000000403ef2e441e30180
+0x~~~~~~~~~~~~~~~~  6ead1c68		bit v8.16b, v3.16b, v13.16b
+#    v8: 0x00000000ffffffff0000000004000000
+0x~~~~~~~~~~~~~~~~  2eb71ca5		bit v5.8b, v5.8b, v23.8b
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e771fe9		bsl v9.16b, v31.16b, v23.16b
+#    v9: 0x00128220009270f80016c26000c22160
+0x~~~~~~~~~~~~~~~~  2e631cee		bsl v14.8b, v7.8b, v3.8b
+#   v14: 0x000000000000000000000000c4000000
+0x~~~~~~~~~~~~~~~~  4e2048bd		cls v29.16b, v5.16b
+#   v29: 0x07070707070707070707070707070707
+0x~~~~~~~~~~~~~~~~  0ea04815		cls v21.2s, v0.2s
+#   v21: 0x00000000000000000000001f0000001f
+0x~~~~~~~~~~~~~~~~  0e604981		cls v1.4h, v12.4h
+#    v1: 0x0000000000000000000f000f0001000f
+0x~~~~~~~~~~~~~~~~  4ea0495b		cls v27.4s, v10.4s
+#   v27: 0x0000001f0000001f0000001f0000001f
+0x~~~~~~~~~~~~~~~~  0e204893		cls v19.8b, v4.8b
+#   v19: 0x00000000000000000707070707070707
+0x~~~~~~~~~~~~~~~~  4e6049cf		cls v15.8h, v14.8h
+#   v15: 0x000f000f000f000f000f000f0001000f
+0x~~~~~~~~~~~~~~~~  6e204881		clz v1.16b, v4.16b
+#    v1: 0x08080808080808080808080808080808
+0x~~~~~~~~~~~~~~~~  2ea04a3b		clz v27.2s, v17.2s
+#   v27: 0x00000000000000000000001000000020
+0x~~~~~~~~~~~~~~~~  2e604929		clz v9.4h, v9.4h
+#    v9: 0x0000000000000000000b000000080002
+0x~~~~~~~~~~~~~~~~  6ea049ff		clz v31.4s, v15.4s
+#   v31: 0x0000000c0000000c0000000c0000000f
+0x~~~~~~~~~~~~~~~~  2e204a6e		clz v14.8b, v19.8b
+#   v14: 0x00000000000000000505050505050505
+0x~~~~~~~~~~~~~~~~  6e604966		clz v6.8h, v11.8h
+#    v6: 0x00100010001000100001001000100010
+0x~~~~~~~~~~~~~~~~  7efd8cb2		cmeq d18, d5, d29
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5ee09bee		cmeq d14, d31, #0
+#   v14: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e368c73		cmeq v19.16b, v3.16b, v22.16b
+#   v19: 0xffffffff00ffffff000000000000ffff
+0x~~~~~~~~~~~~~~~~  4e20992f		cmeq v15.16b, v9.16b, #0
+#   v15: 0xffffffffffffffffff00ffffff00ff00
+0x~~~~~~~~~~~~~~~~  6eea8e0c		cmeq v12.2d, v16.2d, v10.2d
+#   v12: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4ee09ac8		cmeq v8.2d, v22.2d, #0
+#    v8: 0xffffffffffffffff0000000000000000
+0x~~~~~~~~~~~~~~~~  2ea98c62		cmeq v2.2s, v3.2s, v9.2s
+#    v2: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ea09b30		cmeq v16.2s, v25.2s, #0
+#   v16: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  2e748ee6		cmeq v6.4h, v23.4h, v20.4h
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e6099b0		cmeq v16.4h, v13.4h, #0
+#   v16: 0x0000000000000000ffffffff00000000
+0x~~~~~~~~~~~~~~~~  6ea28e35		cmeq v21.4s, v17.4s, v2.4s
+#   v21: 0xffffffff0000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  4ea09b26		cmeq v6.4s, v25.4s, #0
+#    v6: 0xffffffffffffffff00000000ffffffff
+0x~~~~~~~~~~~~~~~~  2e228db0		cmeq v16.8b, v13.8b, v2.8b
+#   v16: 0x0000000000000000ffffffff00000000
+0x~~~~~~~~~~~~~~~~  0e209a15		cmeq v21.8b, v16.8b, #0
+#   v21: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  6e798cf4		cmeq v20.8h, v7.8h, v25.8h
+#   v20: 0xffffffffffffffff0000ffff0000ffff
+0x~~~~~~~~~~~~~~~~  4e60991a		cmeq v26.8h, v8.8h, #0
+#   v26: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  5eff3db0		cmge d16, d13, d31
+#   v16: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7ee08b19		cmge d25, d24, #0
+#   v25: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4e313e71		cmge v17.16b, v19.16b, v17.16b
+#   v17: 0x000000000000ffffffffffffffff0000
+0x~~~~~~~~~~~~~~~~  6e208bd6		cmge v22.16b, v30.16b, #0
+#   v22: 0xffffffffffffffffffffffffffff0000
+0x~~~~~~~~~~~~~~~~  4efa3e9c		cmge v28.2d, v20.2d, v26.2d
+#   v28: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  6ee08ae6		cmge v6.2d, v23.2d, #0
+#    v6: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  0ea33ed9		cmge v25.2s, v22.2s, v3.2s
+#   v25: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  2ea08975		cmge v21.2s, v11.2s, #0
+#   v21: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  0e6c3c70		cmge v16.4h, v3.4h, v12.4h
+#   v16: 0x0000000000000000ffffffff0000ffff
+0x~~~~~~~~~~~~~~~~  2e608937		cmge v23.4h, v9.4h, #0
+#   v23: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4eab3c47		cmge v7.4s, v2.4s, v11.4s
+#    v7: 0xffffffffffffffff00000000ffffffff
+0x~~~~~~~~~~~~~~~~  6ea08ac0		cmge v0.4s, v22.4s, #0
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e293fca		cmge v10.8b, v30.8b, v9.8b
+#   v10: 0x0000000000000000ff00ffffffff0000
+0x~~~~~~~~~~~~~~~~  2e208915		cmge v21.8b, v8.8b, #0
+#   v21: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4e7a3ce2		cmge v2.8h, v7.8h, v26.8h
+#    v2: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  6e608953		cmge v19.8h, v10.8h, #0
+#   v19: 0xffffffffffffffff000000000000ffff
+0x~~~~~~~~~~~~~~~~  5ee135a6		cmgt d6, d13, d1
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5ee08b1e		cmgt d30, d24, #0
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e3b3734		cmgt v20.16b, v25.16b, v27.16b
+#   v20: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e208b20		cmgt v0.16b, v25.16b, #0
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ee13736		cmgt v22.2d, v25.2d, v1.2d
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ee08a10		cmgt v16.2d, v16.2d, #0
+#   v16: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0eaf3525		cmgt v5.2s, v9.2s, v15.2s
+#    v5: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  0ea08a4c		cmgt v12.2s, v18.2s, #0
+#   v12: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e6b365c		cmgt v28.4h, v18.4h, v11.4h
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e608876		cmgt v22.4h, v3.4h, #0
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ebb3565		cmgt v5.4s, v11.4s, v27.4s
+#    v5: 0x0000000000000000ffffffff00000000
+0x~~~~~~~~~~~~~~~~  4ea08a8d		cmgt v13.4s, v20.4s, #0
+#   v13: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e2737fb		cmgt v27.8b, v31.8b, v7.8b
+#   v27: 0x0000000000000000000000ffffffffff
+0x~~~~~~~~~~~~~~~~  0e208805		cmgt v5.8b, v0.8b, #0
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e6d3796		cmgt v22.8h, v28.8h, v13.8h
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e608846		cmgt v6.8h, v2.8h, #0
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7ef63515		cmhi d21, d8, d22
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e333672		cmhi v18.16b, v19.16b, v19.16b
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ef53407		cmhi v7.2d, v0.2d, v21.2d
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2ea0366f		cmhi v15.2s, v19.2s, v0.2s
+#   v15: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  2e6c34ff		cmhi v31.4h, v7.4h, v12.4h
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6eb63609		cmhi v9.4s, v16.4s, v22.4s
+#    v9: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e3c3707		cmhi v7.8b, v24.8b, v28.8b
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e79354b		cmhi v11.8h, v10.8h, v25.8h
+#   v11: 0x0000000000000000ffffffff00000000
+0x~~~~~~~~~~~~~~~~  7ef13d81		cmhs d1, d12, d17
+#    v1: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e3e3f35		cmhs v21.16b, v25.16b, v30.16b
+#   v21: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  6efa3c48		cmhs v8.2d, v2.2d, v26.2d
+#    v8: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  2ebd3ec1		cmhs v1.2s, v22.2s, v29.2s
+#    v1: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e7e3fda		cmhs v26.4h, v30.4h, v30.4h
+#   v26: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  6eb03e93		cmhs v19.4s, v20.4s, v16.4s
+#   v19: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  2e3a3c61		cmhs v1.8b, v3.8b, v26.8b
+#    v1: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e683f94		cmhs v20.8h, v28.8h, v8.8h
+#   v20: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7ee09b1e		cmle d30, d24, #0
+#   v30: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  6e209860		cmle v0.16b, v3.16b, #0
+#    v0: 0xffffffff00ffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  6ee09bc2		cmle v2.2d, v30.2d, #0
+#    v2: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  2ea09947		cmle v7.2s, v10.2s, #0
+#    v7: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  2e609be9		cmle v9.4h, v31.4h, #0
+#    v9: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  6ea09a49		cmle v9.4s, v18.4s, #0
+#    v9: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  2e209bf5		cmle v21.8b, v31.8b, #0
+#   v21: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  6e609abd		cmle v29.8h, v21.8h, #0
+#   v29: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  5ee0aaf9		cmlt d25, d23, #0
+#   v25: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4e20aaa7		cmlt v7.16b, v21.16b, #0
+#    v7: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4ee0abc7		cmlt v7.2d, v30.2d, #0
+#    v7: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  0ea0ab99		cmlt v25.2s, v28.2s, #0
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e60a960		cmlt v0.4h, v11.4h, #0
+#    v0: 0x0000000000000000ffffffff00000000
+0x~~~~~~~~~~~~~~~~  4ea0a8b8		cmlt v24.4s, v5.4s, #0
+#   v24: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e20a97a		cmlt v26.8b, v11.8b, #0
+#   v26: 0x0000000000000000ffffffff00000000
+0x~~~~~~~~~~~~~~~~  4e60aaa1		cmlt v1.8h, v21.8h, #0
+#    v1: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  5efe8efc		cmtst d28, d23, d30
+#   v28: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4e3f8cda		cmtst v26.16b, v6.16b, v31.16b
+#   v26: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ee48ea1		cmtst v1.2d, v21.2d, v4.2d
+#    v1: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0eb48f5b		cmtst v27.2s, v26.2s, v20.2s
+#   v27: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e728c1a		cmtst v26.4h, v0.4h, v18.4h
+#   v26: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ea48e19		cmtst v25.4s, v16.4s, v4.4s
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e298d4b		cmtst v11.8b, v10.8b, v9.8b
+#   v11: 0x0000000000000000ff00ffffffff0000
+0x~~~~~~~~~~~~~~~~  4e618c40		cmtst v0.8h, v2.8h, v1.8h
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e2059f9		cnt v25.16b, v15.16b
+#   v25: 0x00000000000000000000000008080808
+0x~~~~~~~~~~~~~~~~  0e2058dc		cnt v28.8b, v6.8b
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e0f04e6		dup v6.16b, v7.b[7]
+#    v6: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4e010e89		dup v9.16b, w20
+#    v9: 0x01010101010101010101010101010101
+0x~~~~~~~~~~~~~~~~  4e1805ac		dup v12.2d, v13.d[1]
+#   v12: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e080fe9		dup v9.2d, xzr
+#    v9: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e140744		dup v4.2s, v26.s[2]
+#    v4: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e040d83		dup v3.2s, w12
+#    v3: 0x0000000000000000ffffff7dffffff7d
+0x~~~~~~~~~~~~~~~~  0e1e04b6		dup v22.4h, v5.h[7]
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e020f30		dup v16.4h, w25
+#   v16: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e140554		dup v20.4s, v10.s[2]
+#   v20: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e040cea		dup v10.4s, w7
+#   v10: 0x00000018000000180000001800000018
+0x~~~~~~~~~~~~~~~~  0e0507de		dup v30.8b, v30.b[2]
+#   v30: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  0e010dff		dup v31.8b, w15
+#   v31: 0x00000000000000000101010101010101
+0x~~~~~~~~~~~~~~~~  4e12063c		dup v28.8h, v17.h[4]
+#   v28: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4e020c62		dup v2.8h, w3
+#    v2: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e231f3d		eor v29.16b, v25.16b, v3.16b
+#   v29: 0x0000000000000000ffffff7df7f7f775
+0x~~~~~~~~~~~~~~~~  2e3c1e03		eor v3.8b, v16.8b, v28.8b
+#    v3: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  6e060b41		ext v1.16b, v26.16b, v6.16b, #1
+#    v1: 0xff000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e010bc2		ext v2.8b, v30.8b, v1.8b, #1
+#    v2: 0x000000000000000000ffffffffffffff
+0x~~~~~~~~~~~~~~~~  4c402012		ld1 {v18.16b, v19.16b, v20.16b, v21.16b}, [x0]
+#   v18: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x2f2e2d2c2b2a29282726252423222120 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x3f3e3d3c3b3a39383736353433323130 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc22037		ld1 {v23.16b, v24.16b, v25.16b, v26.16b}, [x1], x2
+#   v23: 0xdbdad9d8d7d6d5d4d3d2d1d0cfce0001 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0xebeae9e8e7e6e5e4e3e2e1e0dfdedddc <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0xfbfaf9f8f7f6f5f4f3f2f1f0efeeedec <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0b0a09080706050403020100fffefdfc <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf2025		ld1 {v5.16b, v6.16b, v7.16b, v8.16b}, [x1], #64
+#    v5: 0xdad9d8d7d6d5d4d3d2d1d0cfcecdcccb <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0xeae9e8e7e6e5e4e3e2e1e0dfdedddcdb <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0xfaf9f8f7f6f5f4f3f2f1f0efeeedeceb <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0a09080706050403020100fffefdfcfb <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c406012		ld1 {v18.16b, v19.16b, v20.16b}, [x0]
+#   v18: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x2f2e2d2c2b2a29282726252423222120 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc2602d		ld1 {v13.16b, v14.16b, v15.16b}, [x1], x2
+#   v13: 0x1a191817161514131211100f0e0d0c0b <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x2a292827262524232221201f1e1d1c1b <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x3a393837363534333231302f2e2d2c2b <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf6033		ld1 {v19.16b, v20.16b, v21.16b}, [x1], #48
+#   v19: 0x191817161514131211100f0e0d0c0b0a <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x292827262524232221201f1e1d1c1b1a <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x393837363534333231302f2e2d2c2b2a <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c40a011		ld1 {v17.16b, v18.16b}, [x0]
+#   v17: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc2a034		ld1 {v20.16b, v21.16b}, [x1], x2
+#   v20: 0x494847464544434241403f3e3d3c3b3a <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x595857565554535251504f4e4d4c4b4a <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdfa03c		ld1 {v28.16b, v29.16b}, [x1], #32
+#   v28: 0x4847464544434241403f3e3d3c3b3a39 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x5857565554535251504f4e4d4c4b4a49 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c40701d		ld1 {v29.16b}, [x0]
+#   v29: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc27035		ld1 {v21.16b}, [x1], x2
+#   v21: 0x6867666564636261605f5e5d5c5b5a59 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf7024		ld1 {v4.16b}, [x1], #16
+#    v4: 0x67666564636261605f5e5d5c5b5a5958 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c402c04		ld1 {v4.1d, v5.1d, v6.1d, v7.1d}, [x0]
+#    v4: 0x0000000000000000ff0000850002ff01 (d4: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x00000000000000000000000000fffeff (d5: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000001700000000000000 (d6: 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000001f1e1d1c1b1a1918 (d7: 8.56775e-159) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc22c31		ld1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x1], x2
+#   v17: 0x00000000000000006f6e6d6c6b6a6968 (d17: 5.76650e+228) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000007776757473727170 (d18: 2.89670e+267) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000007f7e7d7c7b7a7978 (d19: 1.33818e+306) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x00000000000000008786858483828180 (d20: -2.08158e-272) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf2c3c		ld1 {v28.1d, v29.1d, v30.1d, v31.1d}, [x1], #32
+#   v28: 0x00000000000000006e6d6c6b6a696867 (d28: 8.50866e+223) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000000000767574737271706f (d29: 4.22243e+262) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x00000000000000007e7d7c7b7a797877 (d30: 1.97467e+301) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x0000000000000000868584838281807f (d31: -3.03465e-277) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c406c14		ld1 {v20.1d, v21.1d, v22.1d}, [x0]
+#   v20: 0x0000000000000000ff0000850002ff01 (d20: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x00000000000000000000000000fffeff (d21: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x00000000000000001700000000000000 (d22: 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc26c33		ld1 {v19.1d, v20.1d, v21.1d}, [x1], x2
+#   v19: 0x00000000000000008e8d8c8b8a898887 (d19: -1.41807e-238) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x0000000000000000969594939291908f (d20: -7.04826e-200) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x00000000000000009e9d9c9b9a999897 (d21: -3.29099e-161) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf6c2c		ld1 {v12.1d, v13.1d, v14.1d}, [x1], #24
+#   v12: 0x00000000000000008d8c8b8a89888786 (d12: -2.09028e-243) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x00000000000000009594939291908f8e (d13: -1.02545e-204) <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x00000000000000009d9c9b9a99989796 (d14: -4.85140e-166) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c40ac1d		ld1 {v29.1d, v30.1d}, [x0]
+#   v29: 0x0000000000000000ff0000850002ff01 (d29: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x00000000000000000000000000fffeff (d30: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc2ac3f		ld1 {v31.1d, v0.1d}, [x1], x2
+#   v31: 0x0000000000000000a5a4a3a2a1a09f9e (d31: -2.38202e-127) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x0000000000000000adacabaaa9a8a7a6 (d0: -1.12597e-88) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdfac23		ld1 {v3.1d, v4.1d}, [x1], #16
+#    v3: 0x0000000000000000a4a3a2a1a09f9e9d (d3: -3.45787e-132) <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000acabaaa9a8a7a6a5 (d4: -1.65794e-93) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c407c1c		ld1 {v28.1d}, [x0]
+#   v28: 0x0000000000000000ff0000850002ff01 (d28: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc27c2b		ld1 {v11.1d}, [x1], x2
+#   v11: 0x0000000000000000b4b3b2b1b0afaead (d11: -8.03348e-55) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf7c3d		ld1 {v29.1d}, [x1], #8
+#   v29: 0x0000000000000000b3b2b1b0afaeadac (d29: -1.16334e-59) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c402c1c		ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0]
+#   v28: 0x0000000000fffeffff0000850002ff01 (8.28892e-317, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x1f1e1d1c1b1a19181700000000000000 (8.56775e-159, 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x2f2e2d2c2b2a29282726252423222120 (1.98829e-81, 4.28794e-120) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x3f3e3d3c3b3a39383736353433323130 (0.000461414, 9.95833e-43) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc22c28		ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x1], x2
+#    v8: 0xc3c2c1c0bfbebdbcbbbab9b8b7b6b5b4 (-2.70315e+18, -5.65934e-21) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0xd3d2d1d0cfcecdcccbcac9c8c7c6c5c4 (-6.28100e+95, -1.31369e+57) <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0xe3e2e1e0dfdedddcdbdad9d8d7d6d5d4 (-1.45943e+173, -3.04943e+134) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0xf3f2f1f0efeeedecebeae9e8e7e6e5e4 (-3.39104e+250, -7.07849e+211) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf2c2e		ld1 {v14.2d, v15.2d, v16.2d, v17.2d}, [x1], #64
+#   v14: 0xc2c1c0bfbebdbcbbbab9b8b7b6b5b4b3 (-3.90391e+13, -8.31108e-26) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0xd2d1d0cfcecdcccbcac9c8c7c6c5c4c3 (-9.07279e+90, -1.92941e+52) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0xe2e1e0dfdedddcdbdad9d8d7d6d5d4d3 (-2.10851e+168, -4.47908e+129) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0xf2f1f0efeeedecebeae9e8e7e6e5e4e3 (-4.90012e+245, -1.03980e+207) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c406c1a		ld1 {v26.2d, v27.2d, v28.2d}, [x0]
+#   v26: 0x0000000000fffeffff0000850002ff01 (8.28892e-317, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x1f1e1d1c1b1a19181700000000000000 (8.56775e-159, 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x2f2e2d2c2b2a29282726252423222120 (1.98829e-81, 4.28794e-120) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc26c25		ld1 {v5.2d, v6.2d, v7.2d}, [x1], x2
+#    v5: 0x020100fffefdfcfbfaf9f8f7f6f5f4f3 (5.07812e-299, -2.41385e+284) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x1211100f0e0d0c0b0a09080706050403 (1.18008e-221, 2.54377e-260) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x2221201f1e1d1c1b1a19181716151413 (2.74293e-144, 5.90574e-183) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf6c3a		ld1 {v26.2d, v27.2d, v28.2d}, [x1], #48
+#   v26: 0x0100fffefdfcfbfaf9f8f7f6f5f4f3f2 (7.74681e-304, -3.54087e+279) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x11100f0e0d0c0b0a0908070605040302 (1.69471e-226, 3.72581e-265) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x21201f1e1d1c1b1a1918171615141312 (3.94003e-149, 8.65093e-188) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c40ac12		ld1 {v18.2d, v19.2d}, [x0]
+#   v18: 0x0000000000fffeffff0000850002ff01 (8.28892e-317, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x1f1e1d1c1b1a19181700000000000000 (8.56775e-159, 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc2ac35		ld1 {v21.2d, v22.2d}, [x1], x2
+#   v21: 0x31302f2e2d2c2b2a2928272625242322 (9.15999e-72, 2.00864e-110) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x41403f3e3d3c3b3a3938373635343332 (2.12953e+06, 4.66377e-33) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdfac31		ld1 {v17.2d, v18.2d}, [x1], #32
+#   v17: 0x302f2e2d2c2b2a292827262524232221 (1.34639e-76, 2.93754e-115) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x403f3e3d3c3b3a393837363534333231 (31.2431, 6.82132e-38) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c407c05		ld1 {v5.2d}, [x0]
+#    v5: 0x0000000000fffeffff0000850002ff01 (8.28892e-317, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc27c26		ld1 {v6.2d}, [x1], x2
+#    v6: 0x504f4e4d4c4b4a494847464544434241 (7.24994e+78, 1.58398e+40) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf7c2f		ld1 {v15.2d}, [x1], #16
+#   v15: 0x4f4e4d4c4b4a49484746454443424140 (1.07078e+74, 2.31271e+35) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c40281e		ld1 {v30.2s, v31.2s, v0.2s, v1.2s}, [x0]
+#   v30: 0x0000000000000000ff0000850002ff01 (..., -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x00000000000000000000000000fffeff (..., 0.00000, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x00000000000000001700000000000000 (..., 4.13590e-25, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x00000000000000001f1e1d1c1b1a1918 (..., 3.34819e-20, 1.27467e-22) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc22838		ld1 {v24.2s, v25.2s, v26.2s, v27.2s}, [x1], x2
+#   v24: 0x00000000000000005756555453525150 (..., 2.35662e+14, 9.03307e+11) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x00000000000000005f5e5d5c5b5a5958 (..., 1.60231e+19, 6.14598e+16) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000006766656463626160 (..., 1.08801e+24, 4.17598e+21) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x00000000000000006f6e6d6c6b6a6968 (..., 7.37897e+28, 2.83386e+26) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf283b		ld1 {v27.2s, v28.2s, v29.2s, v30.2s}, [x1], #32
+#   v27: 0x0000000000000000565554535251504f (..., 5.86395e+13, 2.24749e+11) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x00000000000000005e5d5c5b5a595857 (..., 3.98768e+18, 1.52943e+16) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000000000666564636261605f (..., 2.70818e+23, 1.03937e+21) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x00000000000000006e6d6c6b6a696867 (..., 1.83698e+28, 7.05432e+25) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c40680b		ld1 {v11.2s, v12.2s, v13.2s}, [x0]
+#   v11: 0x0000000000000000ff0000850002ff01 (..., -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x00000000000000000000000000fffeff (..., 0.00000, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x00000000000000001700000000000000 (..., 4.13590e-25, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc26828		ld1 {v8.2s, v9.2s, v10.2s}, [x1], x2
+#    v8: 0x0000000000000000767574737271706f (..., 1.24460e+33, 4.78220e+30) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000007e7d7c7b7a797877 (..., 8.42353e+37, 3.23831e+35) <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x0000000000000000868584838281807f (..., -5.02237e-35, -1.90286e-37) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf683f		ld1 {v31.2s, v0.2s, v1.2s}, [x1], #24
+#   v31: 0x00000000000000007574737271706f6e (..., 3.09878e+32, 1.19058e+30) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x00000000000000007d7c7b7a79787776 (..., 2.09754e+37, 8.06320e+34) <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x00000000000000008584838281807f7e (..., -1.24615e-35, -4.72027e-38) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c40a800		ld1 {v0.2s, v1.2s}, [x0]
+#    v0: 0x0000000000000000ff0000850002ff01 (..., -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x00000000000000000000000000fffeff (..., 0.00000, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc2a82d		ld1 {v13.2s, v14.2s}, [x1], x2
+#   v13: 0x00000000000000008d8c8b8a89888786 (..., -8.66176e-31, -3.28683e-33) <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x00000000000000009594939291908f8e (..., -6.00095e-26, -2.28077e-28) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdfa823		ld1 {v3.2s, v4.2s}, [x1], #16
+#    v3: 0x00000000000000008c8b8a8988878685 (..., -2.14997e-31, -8.15664e-34) <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x000000000000000094939291908f8e8d (..., -1.49010e-26, -5.66232e-29) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c40781a		ld1 {v26.2s}, [x0]
+#   v26: 0x0000000000000000ff0000850002ff01 (..., -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc27820		ld1 {v0.2s}, [x1], x2
+#    v0: 0x00000000000000009c9b9a9998979695 (..., -1.02970e-21, -3.91846e-24) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf782b		ld1 {v11.2s}, [x1], #8
+#   v11: 0x00000000000000009b9a999897969594 (..., -2.55764e-22, -9.73128e-25) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c402410		ld1 {v16.4h, v17.4h, v18.4h, v19.4h}, [x0]
+#   v16: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000001700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000001f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc22438		ld1 {v24.4h, v25.4h, v26.4h, v27.4h}, [x1], x2
+#   v24: 0x0000000000000000a3a2a1a09f9e9d9c <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x0000000000000000abaaa9a8a7a6a5a4 <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0000000000000000b3b2b1b0afaeadac <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000bbbab9b8b7b6b5b4 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf2421		ld1 {v1.4h, v2.4h, v3.4h, v4.4h}, [x1], #32
+#    v1: 0x0000000000000000a2a1a09f9e9d9c9b <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000000000aaa9a8a7a6a5a4a3 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000b2b1b0afaeadacab <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000bab9b8b7b6b5b4b3 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c40641e		ld1 {v30.4h, v31.4h, v0.4h}, [x0]
+#   v30: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x00000000000000001700000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc26439		ld1 {v25.4h, v26.4h, v27.4h}, [x1], x2
+#   v25: 0x0000000000000000c2c1c0bfbebdbcbb <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0000000000000000cac9c8c7c6c5c4c3 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000d2d1d0cfcecdcccb <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf6423		ld1 {v3.4h, v4.4h, v5.4h}, [x1], #24
+#    v3: 0x0000000000000000c1c0bfbebdbcbbba <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000c9c8c7c6c5c4c3c2 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x0000000000000000d1d0cfcecdcccbca <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c40a403		ld1 {v3.4h, v4.4h}, [x0]
+#    v3: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc2a423		ld1 {v3.4h, v4.4h}, [x1], x2
+#    v3: 0x0000000000000000d9d8d7d6d5d4d3d2 <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000e1e0dfdedddcdbda <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdfa437		ld1 {v23.4h, v24.4h}, [x1], #16
+#   v23: 0x0000000000000000d8d7d6d5d4d3d2d1 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x0000000000000000e0dfdedddcdbdad9 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c40741a		ld1 {v26.4h}, [x0]
+#   v26: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc27421		ld1 {v1.4h}, [x1], x2
+#    v1: 0x0000000000000000e8e7e6e5e4e3e2e1 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf742e		ld1 {v14.4h}, [x1], #8
+#   v14: 0x0000000000000000e7e6e5e4e3e2e1e0 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c40281a		ld1 {v26.4s, v27.4s, v28.4s, v29.4s}, [x0]
+#   v26: 0x0000000000fffeffff0000850002ff01 (0.00000, 2.35095e-38, -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x1f1e1d1c1b1a19181700000000000000 (3.34819e-20, 1.27467e-22, 4.13590e-25, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x2f2e2d2c2b2a29282726252423222120 (1.58413e-10, 6.04532e-13, 2.30573e-15, 8.78905e-18) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x3f3e3d3c3b3a39383736353433323130 (0.743122, 0.00284155, 1.08604e-05, 4.14886e-08) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc2283c		ld1 {v28.4s, v29.4s, v30.4s, v31.4s}, [x1], x2
+#   v28: 0xf7f6f5f4f3f2f1f0efeeedecebeae9e8 (-1.00179e+34, -3.84962e+31, -1.47890e+29, -5.67986e+26) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0706050403020100fffefdfcfbfaf9f8 (1.00825e-34, 3.82047e-37, -nan, -2.60629e+36) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x17161514131211100f0e0d0c0b0a0908 (4.84942e-25, 1.84362e-27, 7.00365e-30, 2.65846e-32) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x27262524232221201f1e1d1c1b1a1918 (2.30573e-15, 8.78905e-18, 3.34819e-20, 1.27467e-22) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf2824		ld1 {v4.4s, v5.4s, v6.4s, v7.4s}, [x1], #64
+#    v4: 0xf6f5f4f3f2f1f0efeeedecebeae9e8e7 (-2.49430e+33, -9.58428e+30, -3.68172e+28, -1.41390e+26) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x06050403020100fffefdfcfbfaf9f8f7 (2.50175e-35, 9.47771e-38, -1.68804e+38, -6.48966e+35) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x161514131211100f0e0d0c0b0a090807 (1.20425e-25, 4.57737e-28, 1.73854e-30, 6.59782e-33) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x262524232221201f1e1d1c1b1a191817 (5.72948e-16, 2.18366e-18, 8.31732e-21, 3.16591e-23) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c406802		ld1 {v2.4s, v3.4s, v4.4s}, [x0]
+#    v2: 0x0000000000fffeffff0000850002ff01 (0.00000, 2.35095e-38, -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x1f1e1d1c1b1a19181700000000000000 (3.34819e-20, 1.27467e-22, 4.13590e-25, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x2f2e2d2c2b2a29282726252423222120 (1.58413e-10, 6.04532e-13, 2.30573e-15, 8.78905e-18) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc26836		ld1 {v22.4s, v23.4s, v24.4s}, [x1], x2
+#   v22: 0x363534333231302f2e2d2c2b2a292827 (2.70015e-06, 1.03137e-08, 3.93749e-11, 1.50241e-13) <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x464544434241403f3e3d3c3b3a393837 (12625.1, 48.3127, 0.184800, 0.000706557) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x565554535251504f4e4d4c4b4a494847 (5.86395e+13, 2.24749e+11, 8.61082e+08, 3.29781e+06) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf682f		ld1 {v15.4s, v16.4s, v17.4s}, [x1], #48
+#   v15: 0x3534333231302f2e2d2c2b2a29282726 (6.71297e-07, 2.56382e-09, 9.78665e-12, 3.73374e-14) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x4544434241403f3e3d3c3b3a39383736 (3140.20, 12.0154, 0.0459549, 0.000175682) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x5554535251504f4e4d4c4b4a49484746 (1.45909e+13, 5.59177e+10, 2.14218e+08, 820340.) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c40a814		ld1 {v20.4s, v21.4s}, [x0]
+#   v20: 0x0000000000fffeffff0000850002ff01 (0.00000, 2.35095e-38, -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x1f1e1d1c1b1a19181700000000000000 (3.34819e-20, 1.27467e-22, 4.13590e-25, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc2a83e		ld1 {v30.4s, v31.4s}, [x1], x2
+#   v30: 0x6564636261605f5e5d5c5b5a59585756 (6.74083e+22, 2.58684e+20, 9.92399e+17, 3.80591e+15) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x7574737271706f6e6d6c6b6a69686766 (3.09878e+32, 1.19058e+30, 4.57302e+27, 1.75599e+25) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdfa82b		ld1 {v11.4s, v12.4s}, [x1], #32
+#   v11: 0x64636261605f5e5d5c5b5a5958575655 (1.67780e+22, 6.43816e+19, 2.46969e+17, 9.47063e+14) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x74737271706f6e6d6c6b6a6968676665 (7.71514e+31, 2.96402e+29, 1.13840e+27, 4.37102e+24) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c40780f		ld1 {v15.4s}, [x0]
+#   v15: 0x0000000000fffeffff0000850002ff01 (0.00000, 2.35095e-38, -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc2782c		ld1 {v12.4s}, [x1], x2
+#   v12: 0x84838281807f7e7d7c7b7a7978777675 (-3.09178e-36, -1.17085e-38, 5.22300e+36, 2.00766e+34) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf7820		ld1 {v0.4s}, [x1], #16
+#    v0: 0x838281807f7e7d7c7b7a797877767574 (-7.67045e-37, 3.38275e+38, 1.30054e+36, 4.99878e+33) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c402011		ld1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x0]
+#   v17: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000001700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x00000000000000001f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc22025		ld1 {v5.8b, v6.8b, v7.8b, v8.8b}, [x1], x2
+#    v5: 0x00000000000000008b8a898887868584 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x0000000000000000939291908f8e8d8c <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000009b9a999897969594 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0000000000000000a3a2a1a09f9e9d9c <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf2029		ld1 {v9.8b, v10.8b, v11.8b, v12.8b}, [x1], #32
+#    v9: 0x00000000000000008a89888786858483 <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x00000000000000009291908f8e8d8c8b <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x00000000000000009a99989796959493 <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000000000a2a1a09f9e9d9c9b <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c406004		ld1 {v4.8b, v5.8b, v6.8b}, [x0]
+#    v4: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000001700000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc26022		ld1 {v2.8b, v3.8b, v4.8b}, [x1], x2
+#    v2: 0x0000000000000000aaa9a8a7a6a5a4a3 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000b2b1b0afaeadacab <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000bab9b8b7b6b5b4b3 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf602c		ld1 {v12.8b, v13.8b, v14.8b}, [x1], #24
+#   v12: 0x0000000000000000a9a8a7a6a5a4a3a2 <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x0000000000000000b1b0afaeadacabaa <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x0000000000000000b9b8b7b6b5b4b3b2 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c40a00a		ld1 {v10.8b, v11.8b}, [x0]
+#   v10: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc2a02b		ld1 {v11.8b, v12.8b}, [x1], x2
+#   v11: 0x0000000000000000c1c0bfbebdbcbbba <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000000000c9c8c7c6c5c4c3c2 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdfa03b		ld1 {v27.8b, v28.8b}, [x1], #16
+#   v27: 0x0000000000000000c0bfbebdbcbbbab9 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x0000000000000000c8c7c6c5c4c3c2c1 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c40701f		ld1 {v31.8b}, [x0]
+#   v31: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc2702a		ld1 {v10.8b}, [x1], x2
+#   v10: 0x0000000000000000d0cfcecdcccbcac9 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf703c		ld1 {v28.8b}, [x1], #8
+#   v28: 0x0000000000000000cfcecdcccbcac9c8 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c402405		ld1 {v5.8h, v6.8h, v7.8h, v8.8h}, [x0]
+#    v5: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x2f2e2d2c2b2a29282726252423222120 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x3f3e3d3c3b3a39383736353433323130 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc22422		ld1 {v2.8h, v3.8h, v4.8h, v5.8h}, [x1], x2
+#    v2: 0xdfdedddcdbdad9d8d7d6d5d4d3d2d1d0 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0xefeeedecebeae9e8e7e6e5e4e3e2e1e0 <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0xfffefdfcfbfaf9f8f7f6f5f4f3f2f1f0 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x0f0e0d0c0b0a09080706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf242a		ld1 {v10.8h, v11.8h, v12.8h, v13.8h}, [x1], #64
+#   v10: 0xdedddcdbdad9d8d7d6d5d4d3d2d1d0cf <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0xeeedecebeae9e8e7e6e5e4e3e2e1e0df <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0xfefdfcfbfaf9f8f7f6f5f4f3f2f1f0ef <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x0e0d0c0b0a09080706050403020100ff <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c40641a		ld1 {v26.8h, v27.8h, v28.8h}, [x0]
+#   v26: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x2f2e2d2c2b2a29282726252423222120 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc26423		ld1 {v3.8h, v4.8h, v5.8h}, [x1], x2
+#    v3: 0x1e1d1c1b1a191817161514131211100f <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x2e2d2c2b2a292827262524232221201f <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x3e3d3c3b3a393837363534333231302f <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf6431		ld1 {v17.8h, v18.8h, v19.8h}, [x1], #48
+#   v17: 0x1d1c1b1a191817161514131211100f0e <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x2d2c2b2a292827262524232221201f1e <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x3d3c3b3a393837363534333231302f2e <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c40a404		ld1 {v4.8h, v5.8h}, [x0]
+#    v4: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc2a435		ld1 {v21.8h, v22.8h}, [x1], x2
+#   v21: 0x4d4c4b4a494847464544434241403f3e <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x5d5c5b5a595857565554535251504f4e <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdfa424		ld1 {v4.8h, v5.8h}, [x1], #32
+#    v4: 0x4c4b4a494847464544434241403f3e3d <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x5c5b5a595857565554535251504f4e4d <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c407409		ld1 {v9.8h}, [x0]
+#    v9: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc2743b		ld1 {v27.8h}, [x1], x2
+#   v27: 0x6c6b6a696867666564636261605f5e5d <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf743a		ld1 {v26.8h}, [x1], #16
+#   v26: 0x6b6a696867666564636261605f5e5d5c <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d400413		ld1 {v19.b}[1], [x0]
+#   v19: 0x3d3c3b3a39383736353433323130012e <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dc20c2c		ld1 {v12.b}[3], [x1], x2
+#   v12: 0xfefdfcfbfaf9f8f7f6f5f4f36cf1f0ef <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4ddf103b		ld1 {v27.b}[12], [x1], #1
+#   v27: 0x6c6b6a6b6867666564636261605f5e5d <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d40840a		ld1 {v10.d}[1], [x0]
+#   v10: 0xff0000850002ff01d6d5d4d3d2d1d0cf (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dc2843a		ld1 {v26.d}[1], [x1], x2
+#   v26: 0x737271706f6e6d6c636261605f5e5d5c (1.28953e+248, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4ddf8427		ld1 {v7.d}[1], [x1], #8
+#    v7: 0x7271706f6e6d6c6b2726252423222120 (1.86056e+243, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d404813		ld1 {v19.h}[5], [x0]
+#   v19: 0x3d3c3b3aff013736353433323130012e <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dc2482a		ld1 {v10.h}[1], [x1], x2
+#   v10: 0xff0000850002ff01d6d5d4d37473d0cf <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4ddf4025		ld1 {v5.h}[4], [x1], #2
+#    v5: 0x5c5b5a595857737254535251504f4e4d <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d408015		ld1 {v21.s}[2], [x0]
+#   v21: 0x4d4c4b4a0002ff014544434241403f3e (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dc2802d		ld1 {v13.s}[2], [x1], x2
+#   v13: 0x0e0d0c0b7776757406050403020100ff (..., 4.99878e+33, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4ddf8021		ld1 {v1.s}[2], [x1], #4
+#    v1: 0x0000000076757473e8e7e6e5e4e3e2e1 (..., 1.24460e+33, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d40c002		ld1r {v2.16b}, [x0]
+#    v2: 0x01010101010101010101010101010101 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dc2c022		ld1r {v2.16b}, [x1], x2
+#    v2: 0x77777777777777777777777777777777 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4ddfc036		ld1r {v22.16b}, [x1], #1
+#   v22: 0x76767676767676767676767676767676 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d40cc19		ld1r {v25.1d}, [x0]
+#   v25: 0x0000000000000000ff0000850002ff01 (d25: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dc2cc29		ld1r {v9.1d}, [x1], x2
+#    v9: 0x00000000000000007e7d7c7b7a797877 (d9: 1.97467e+301) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0ddfcc37		ld1r {v23.1d}, [x1], #8
+#   v23: 0x00000000000000007d7c7b7a79787776 (d23: 2.91053e+296) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d40cc13		ld1r {v19.2d}, [x0]
+#   v19: 0xff0000850002ff01ff0000850002ff01 (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dc2cc35		ld1r {v21.2d}, [x1], x2
+#   v21: 0x8584838281807f7e8584838281807f7e (-4.41447e-282, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4ddfcc3e		ld1r {v30.2d}, [x1], #8
+#   v30: 0x84838281807f7e7d84838281807f7e7d (-6.40629e-287, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d40c818		ld1r {v24.2s}, [x0]
+#   v24: 0x00000000000000000002ff010002ff01 (s24: 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dc2c83a		ld1r {v26.2s}, [x1], x2
+#   v26: 0x00000000000000008887868588878685 (s26: -8.15664e-34) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0ddfc83c		ld1r {v28.2s}, [x1], #4
+#   v28: 0x00000000000000008786858487868584 (s28: -2.02406e-34) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d40c413		ld1r {v19.4h}, [x0]
+#   v19: 0x0000000000000000ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dc2c421		ld1r {v1.4h}, [x1], x2
+#    v1: 0x00000000000000008988898889888988 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0ddfc435		ld1r {v21.4h}, [x1], #2
+#   v21: 0x00000000000000008887888788878887 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d40c80f		ld1r {v15.4s}, [x0]
+#   v15: 0x0002ff010002ff010002ff010002ff01 (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dc2c835		ld1r {v21.4s}, [x1], x2
+#   v21: 0x8c8b8a898c8b8a898c8b8a898c8b8a89 (..., -2.14997e-31, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4ddfc837		ld1r {v23.4s}, [x1], #4
+#   v23: 0x8b8a89888b8a89888b8a89888b8a8988 (..., -5.33626e-32, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d40c01a		ld1r {v26.8b}, [x0]
+#   v26: 0x00000000000000000101010101010101 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dc2c02e		ld1r {v14.8b}, [x1], x2
+#   v14: 0x00000000000000008c8c8c8c8c8c8c8c <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0ddfc033		ld1r {v19.8b}, [x1], #1
+#   v19: 0x00000000000000008b8b8b8b8b8b8b8b <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d40c40d		ld1r {v13.8h}, [x0]
+#   v13: 0xff01ff01ff01ff01ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dc2c43e		ld1r {v30.8h}, [x1], x2
+#   v30: 0x8d8c8d8c8d8c8d8c8d8c8d8c8d8c8d8c <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4ddfc43b		ld1r {v27.8h}, [x1], #2
+#   v27: 0x8c8b8c8b8c8b8c8b8c8b8c8b8c8b8c8b <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c408015		ld2 {v21.16b, v22.16b}, [x0]
+#   v21: 0x1e1c1a18000000000000ffff00850201 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x1f1d1b1917000000000000feff0000ff <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc28035		ld2 {v21.16b, v22.16b}, [x1], x2
+#   v21: 0xaba9a7a5a3a19f9d9b99979593918f8d <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0xacaaa8a6a4a2a09e9c9a98969492908e <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf802c		ld2 {v12.16b, v13.16b}, [x1], #32
+#   v12: 0xaaa8a6a4a2a09e9c9a98969492908e8c <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0xaba9a7a5a3a19f9d9b99979593918f8d <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c408c0e		ld2 {v14.2d, v15.2d}, [x0]
+#   v14: 0x1700000000000000ff0000850002ff01 (6.68887e-198, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x1f1e1d1c1b1a19180000000000fffeff (8.56775e-159, 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc28c20		ld2 {v0.2d, v1.2d}, [x1], x2
+#    v0: 0xc3c2c1c0bfbebdbcb3b2b1b0afaeadac (-2.70315e+18, -1.16334e-59) <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0xcbcac9c8c7c6c5c4bbbab9b8b7b6b5b4 (-1.31369e+57, -5.65934e-21) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf8c2c		ld2 {v12.2d, v13.2d}, [x1], #32
+#   v12: 0xc2c1c0bfbebdbcbbb2b1b0afaeadacab (-3.90391e+13, -1.67978e-64) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0xcac9c8c7c6c5c4c3bab9b8b7b6b5b4b3 (-1.92941e+52, -8.31108e-26) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c40881b		ld2 {v27.2s, v28.2s}, [x0]
+#   v27: 0x000000000000000000fffeff0002ff01 (..., 2.35095e-38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x000000000000000000000000ff000085 (..., 0.00000, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc28822		ld2 {v2.2s, v3.2s}, [x1], x2
+#    v2: 0x0000000000000000d6d5d4d3cecdcccb (..., -1.17555e+14, -1.72638e+09) <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000dad9d8d7d2d1d0cf (..., -3.06592e+16, -4.50576e+11) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf882c		ld2 {v12.2s, v13.2s}, [x1], #16
+#   v12: 0x0000000000000000d5d4d3d2cdcccbca (..., -2.92508e+13, -4.29488e+08) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x0000000000000000d9d8d7d6d1d0cfce (..., -7.62949e+15, -1.12105e+11) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c408409		ld2 {v9.4h, v10.4h}, [x0]
+#    v9: 0x00000000000000000000feff0085ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x0000000000000000000000ffff000002 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc28437		ld2 {v23.4h, v24.4h}, [x1], x2
+#   v23: 0x0000000000000000e7e6e3e2dfdedbda <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x0000000000000000e9e8e5e4e1e0dddc <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf8421		ld2 {v1.4h, v2.4h}, [x1], #16
+#    v1: 0x0000000000000000e6e5e2e1dedddad9 <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000000000e8e7e4e3e0dfdcdb <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c408814		ld2 {v20.4s, v21.4s}, [x0]
+#   v20: 0x1b1a19180000000000fffeff0002ff01 (1.27467e-22, 0.00000, 2.35095e-38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x1f1e1d1c1700000000000000ff000085 (3.34819e-20, 4.13590e-25, 0.00000, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc2882a		ld2 {v10.4s, v11.4s}, [x1], x2
+#   v10: 0x04030201fcfbfaf9f4f3f2f1ecebeae9 (1.53999e-36, -1.04669e+37, -1.54621e+32, -2.28166e+27) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x0807060500fffefdf8f7f6f5f0efeeed (4.06322e-34, 2.35095e-38, -4.02346e+34, -5.94046e+29) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf8838		ld2 {v24.4s, v25.4s}, [x1], #32
+#   v24: 0x03020100fbfaf9f8f3f2f1f0ebeae9e8 (3.82047e-37, -2.60629e+36, -3.84962e+31, -5.67986e+26) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x07060504fffefdfcf7f6f5f4efeeedec (1.00825e-34, -nan, -1.00179e+34, -1.47890e+29) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c408011		ld2 {v17.8b, v18.8b}, [x0]
+#   v17: 0x00000000000000000000ffff00850201 <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x0000000000000000000000feff0000ff <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc2802d		ld2 {v13.8b, v14.8b}, [x1], x2
+#   v13: 0x0000000000000000161412100e0c0a08 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x0000000000000000171513110f0d0b09 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf8027		ld2 {v7.8b, v8.8b}, [x1], #16
+#    v7: 0x00000000000000001513110f0d0b0907 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0000000000000000161412100e0c0a08 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c40841e		ld2 {v30.8h, v31.8h}, [x0]
+#   v30: 0x1d1c1918000000000000feff0085ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x1f1e1b1a17000000000000ffff000002 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc28424		ld2 {v4.8h, v5.8h}, [x1], x2
+#    v4: 0x3433302f2c2b28272423201f1c1b1817 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x363532312e2d2a29262522211e1d1a19 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf842d		ld2 {v13.8h, v14.8h}, [x1], #32
+#   v13: 0x33322f2e2b2a272623221f1e1b1a1716 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x353431302d2c2928252421201d1c1918 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d601005		ld2 {v5.b, v6.b}[12], [x0]
+#    v5: 0x363532012e2d2a29262522211e1d1a19 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x1f1e1dff1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0de21c30		ld2 {v16.b, v17.b}[7], [x1], x2
+#   v16: 0x4544434241403f3e363c3b3a39383736 <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000003700ffff00850201 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dff083d		ld2 {v29.b, v30.b}[2], [x1], #2
+#   v29: 0x0706050403020100fffefdfcfb35f9f8 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x1d1c1918000000000000feff0036ff01 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d60840b		ld2 {v11.d, v12.d}[1], [x0]
+#   v11: 0xff0000850002ff01f8f7f6f5f0efeeed (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000fffeffd5d4d3d2cdcccbca (8.28892e-317, ...) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0de2843a		ld2 {v26.d, v27.d}[0], [x1], x2
+#   v26: 0x00000000000000003e3d3c3b3a393837 (d26: 6.80687e-09) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000464544434241403f (d27: 3.36984e+30) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dff8439		ld2 {v25.d, v26.d}[0], [x1], #16
+#   v25: 0x07060504fffefdfc3d3c3b3a39383736 (d25: 1.00298e-13) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000004544434241403f3e (d26: 4.89923e+25) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d605812		ld2 {v18.h, v19.h}[7], [x0]
+#   v18: 0xff01000000000000000000feff0000ff <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00020000000000008b8b8b8b8b8b8b8b <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4de24831		ld2 {v17.h, v18.h}[5], [x1], x2
+#   v17: 0x00000000474600003700ffff00850201 <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0xff01000049480000000000feff0000ff <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dff503e		ld2 {v30.h, v31.h}[2], [x1], #4
+#   v30: 0x1d1c191800000000000046450036ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x1f1e1b1a1700000000004847ff000002 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d60901d		ld2 {v29.s, v30.s}[3], [x0]
+#   v29: 0x0002ff0103020100fffefdfcfb35f9f8 (2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0xff00008500000000000046450036ff01 (-1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0de2803c		ld2 {v28.s, v29.s}[0], [x1], x2
+#   v28: 0x0000000000000000000000004c4b4a49 (s28: 5.32913e+07) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0002ff0103020100fffefdfc504f4e4d (s29: 1.39121e+10) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dff9026		ld2 {v6.s, v7.s}[1], [x1], #8
+#    v6: 0x1f1e1dff1b1a19184b4a494800000000 (..., 1.32570e+07, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000004f4e4d4c0d0b0907 (..., 3.46117e+09, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d60c01a		ld2r {v26.16b, v27.16b}, [x0]
+#   v26: 0x01010101010101010101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0xffffffffffffffffffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4de2c035		ld2r {v21.16b, v22.16b}, [x1], x2
+#   v21: 0x50505050505050505050505050505050 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x51515151515151515151515151515151 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dffc025		ld2r {v5.16b, v6.16b}, [x1], #2
+#    v5: 0x4f4f4f4f4f4f4f4f4f4f4f4f4f4f4f4f <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x50505050505050505050505050505050 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d60cc1a		ld2r {v26.1d, v27.1d}, [x0]
+#   v26: 0x0000000000000000ff0000850002ff01 (d26: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x00000000000000000000000000fffeff (d27: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0de2cc2e		ld2r {v14.1d, v15.1d}, [x1], x2
+#   v14: 0x00000000000000005857565554535251 (d14: 3.67814e+117) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x0000000000000000605f5e5d5c5b5a59 (d15: 1.68234e+156) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dffcc37		ld2r {v23.1d, v24.1d}, [x1], #16
+#   v23: 0x00000000000000005756555453525150 (d23: 5.37096e+112) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00000000000000005f5e5d5c5b5a5958 (d24: 2.48489e+151) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d60cc0b		ld2r {v11.2d, v12.2d}, [x0]
+#   v11: 0xff0000850002ff01ff0000850002ff01 (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000fffeff0000000000fffeff (8.28892e-317, ...) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4de2cc3d		ld2r {v29.2d, v30.2d}, [x1], x2
+#   v29: 0x67666564636261606766656463626160 (1.24732e+190, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x6f6e6d6c6b6a69686f6e6d6c6b6a6968 (5.76650e+228, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dffcc2f		ld2r {v15.2d, v16.2d}, [x1], #16
+#   v15: 0x666564636261605f666564636261605f (1.81795e+185, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x6e6d6c6b6a6968676e6d6c6b6a696867 (8.50866e+223, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d60c81a		ld2r {v26.2s, v27.2s}, [x0]
+#   v26: 0x00000000000000000002ff010002ff01 (s26: 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000ff000085ff000085 (s27: -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0de2c836		ld2r {v22.2s, v23.2s}, [x1], x2
+#   v22: 0x00000000000000007271706f7271706f (s22: 4.78220e+30) <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x00000000000000007675747376757473 (s23: 1.24460e+33) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dffc822		ld2r {v2.2s, v3.2s}, [x1], #8
+#    v2: 0x000000000000000071706f6e71706f6e (s2: 1.19058e+30) <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x00000000000000007574737275747372 (s3: 3.09878e+32) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d60c402		ld2r {v2.4h, v3.4h}, [x0]
+#    v2: 0x0000000000000000ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x00000000000000000002000200020002 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0de2c429		ld2r {v9.4h, v10.4h}, [x1], x2
+#    v9: 0x00000000000000007776777677767776 <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x00000000000000007978797879787978 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dffc426		ld2r {v6.4h, v7.4h}, [x1], #4
+#    v6: 0x00000000000000007675767576757675 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000007877787778777877 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d60c807		ld2r {v7.4s, v8.4s}, [x0]
+#    v7: 0x0002ff010002ff010002ff010002ff01 (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0xff000085ff000085ff000085ff000085 (..., -1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4de2c833		ld2r {v19.4s, v20.4s}, [x1], x2
+#   v19: 0x7c7b7a797c7b7a797c7b7a797c7b7a79 (..., 5.22300e+36, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x807f7e7d807f7e7d807f7e7d807f7e7d (..., -1.17085e-38, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dffc835		ld2r {v21.4s, v22.4s}, [x1], #8
+#   v21: 0x7b7a79787b7a79787b7a79787b7a7978 (..., 1.30054e+36, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x7f7e7d7c7f7e7d7c7f7e7d7c7f7e7d7c (..., 3.38275e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d60c01a		ld2r {v26.8b, v27.8b}, [x0]
+#   v26: 0x00000000000000000101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000ffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0de2c034		ld2r {v20.8b, v21.8b}, [x1], x2
+#   v20: 0x00000000000000008080808080808080 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x00000000000000008181818181818181 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dffc02b		ld2r {v11.8b, v12.8b}, [x1], #2
+#   v11: 0x00000000000000007f7f7f7f7f7f7f7f <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x00000000000000008080808080808080 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d60c40c		ld2r {v12.8h, v13.8h}, [x0]
+#   v12: 0xff01ff01ff01ff01ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x00020002000200020002000200020002 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4de2c426		ld2r {v6.8h, v7.8h}, [x1], x2
+#    v6: 0x82818281828182818281828182818281 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x84838483848384838483848384838483 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dffc439		ld2r {v25.8h, v26.8h}, [x1], #4
+#   v25: 0x81808180818081808180818081808180 <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x83828382838283828382838283828382 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c404014		ld3 {v20.16b, v21.16b, v22.16b}, [x0]
+#   v20: 0x2d2a2724211e1b1800000000fe000001 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x2e2b2825221f1c1900000000ffff85ff <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x2f2c292623201d1a1700000000ff0002 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc2403c		ld3 {v28.16b, v29.16b, v30.16b}, [x1], x2
+#   v28: 0xb1aeaba8a5a29f9c999693908d8a8784 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0xb2afaca9a6a3a09d9a9794918e8b8885 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0xb3b0adaaa7a4a19e9b9895928f8c8986 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf4034		ld3 {v20.16b, v21.16b, v22.16b}, [x1], #48
+#   v20: 0xb0adaaa7a4a19e9b9895928f8c898683 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0xb1aeaba8a5a29f9c999693908d8a8784 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0xb2afaca9a6a3a09d9a9794918e8b8885 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c404c15		ld3 {v21.2d, v22.2d, v23.2d}, [x0]
+#   v21: 0x1f1e1d1c1b1a1918ff0000850002ff01 (8.56775e-159, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x27262524232221200000000000fffeff (4.28794e-120, 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x2f2e2d2c2b2a29281700000000000000 (1.98829e-81, 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc24c32		ld3 {v18.2d, v19.2d, v20.2d}, [x1], x2
+#   v18: 0xd2d1d0cfcecdcccbbab9b8b7b6b5b4b3 (-9.07279e+90, -8.31108e-26) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0xdad9d8d7d6d5d4d3c2c1c0bfbebdbcbb (-4.47908e+129, -3.90391e+13) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0xe2e1e0dfdedddcdbcac9c8c7c6c5c4c3 (-2.10851e+168, -1.92941e+52) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf4c3b		ld3 {v27.2d, v28.2d, v29.2d}, [x1], #48
+#   v27: 0xd1d0cfcecdcccbcab9b8b7b6b5b4b3b2 (-1.30639e+86, -1.21867e-30) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0xd9d8d7d6d5d4d3d2c1c0bfbebdbcbbba (-6.56908e+124, -5.62003e+08) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0xe1e0dfdedddcdbdac9c8c7c6c5c4c3c2 (-3.03668e+163, -2.82942e+47) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c404807		ld3 {v7.2s, v8.2s, v9.2s}, [x0]
+#    v7: 0x0000000000000000000000000002ff01 (..., 0.00000, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x000000000000000000000000ff000085 (..., 0.00000, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000001700000000fffeff (..., 4.13590e-25, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc24834		ld3 {v20.2s, v21.2s, v22.2s}, [x1], x2
+#   v20: 0x0000000000000000f1f0efeee5e4e3e2 (..., -2.38613e+30, -1.35113e+23) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x0000000000000000f5f4f3f2e9e8e7e6 (..., -6.21029e+32, -3.51957e+25) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x0000000000000000f9f8f7f6edecebea (..., -1.61590e+35, -9.16546e+27) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf483a		ld3 {v26.2s, v27.2s, v28.2s}, [x1], #24
+#   v26: 0x0000000000000000f0efeeede4e3e2e1 (..., -5.94046e+29, -3.36301e+22) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000f4f3f2f1e8e7e6e5 (..., -1.54621e+32, -8.76101e+24) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x0000000000000000f8f7f6f5ecebeae9 (..., -4.02346e+34, -2.28166e+27) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c40441b		ld3 {v27.4h, v28.4h, v29.4h}, [x0]
+#   v27: 0x000000000000000000000000ff00ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x000000000000000000000000feff0002 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x00000000000000001700000000ff0085 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc2443c		ld3 {v28.4h, v29.4h, v30.4h}, [x1], x2
+#   v28: 0x00000000000000000c0b060500fffaf9 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x00000000000000000e0d08070201fcfb <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x0000000000000000100f0a090403fefd <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf4427		ld3 {v7.4h, v8.4h, v9.4h}, [x1], #24
+#    v7: 0x00000000000000000b0a0504fffef9f8 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00000000000000000d0c07060100fbfa <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000000f0e09080302fdfc <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c404802		ld3 {v2.4s, v3.4s, v4.4s}, [x0]
+#    v2: 0x272625241b1a1918000000000002ff01 (2.30573e-15, 1.27467e-22, 0.00000, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x2b2a29281f1e1d1c00000000ff000085 (6.04532e-13, 3.34819e-20, 0.00000, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x2f2e2d2c232221201700000000fffeff (1.58413e-10, 8.78905e-18, 4.13590e-25, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc24838		ld3 {v24.4s, v25.4s, v26.4s}, [x1], x2
+#   v24: 0x373635342b2a29281f1e1d1c13121110 (1.08604e-05, 6.04532e-13, 3.34819e-20, 1.84362e-27) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x3b3a39382f2e2d2c2322212017161514 (0.00284155, 1.58413e-10, 8.78905e-18, 4.84942e-25) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x3f3e3d3c33323130272625241b1a1918 (0.743122, 4.14886e-08, 2.30573e-15, 1.27467e-22) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf482b		ld3 {v11.4s, v12.4s, v13.4s}, [x1], #48
+#   v11: 0x363534332a2928271e1d1c1b1211100f (2.70015e-06, 1.50241e-13, 8.31732e-21, 4.57737e-28) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x3a3938372e2d2c2b2221201f16151413 (0.000706557, 3.93749e-11, 2.18366e-18, 1.20425e-25) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x3e3d3c3b3231302f262524231a191817 (0.184800, 1.03137e-08, 5.72948e-16, 3.16591e-23) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c40401d		ld3 {v29.8b, v30.8b, v31.8b}, [x0]
+#   v29: 0x000000000000000000000000fe000001 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x000000000000000000000000ffff85ff <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x00000000000000001700000000ff0002 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc24021		ld3 {v1.8b, v2.8b, v3.8b}, [x1], x2
+#    v1: 0x000000000000000054514e4b4845423f <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x000000000000000055524f4c49464340 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x00000000000000005653504d4a474441 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf402c		ld3 {v12.8b, v13.8b, v14.8b}, [x1], #24
+#   v12: 0x000000000000000053504d4a4744413e <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x000000000000000054514e4b4845423f <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x000000000000000055524f4c49464340 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c404416		ld3 {v22.8h, v23.8h, v24.8h}, [x0]
+#   v22: 0x2b2a25241f1e191800000000ff00ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x2d2c272621201b1a00000000feff0002 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x2f2e292823221d1c1700000000ff0085 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc2442d		ld3 {v13.8h, v14.8h, v15.8h}, [x1], x2
+#   v13: 0x81807b7a75746f6e696863625d5c5756 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x83827d7c777671706b6a65645f5e5958 <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x85847f7e797873726d6c676661605b5a <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf443c		ld3 {v28.8h, v29.8h, v30.8h}, [x1], #48
+#   v28: 0x807f7a7974736e6d686762615c5b5655 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x82817c7b7675706f6a6964635e5d5857 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x84837e7d787772716c6b6665605f5a59 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d402c15		ld3 {v21.b, v22.b, v23.b}[11], [x0]
+#   v21: 0x0000000001000000f5f4f3f2e9e8e7e6 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x2b2a2524ff1e191800000000ff00ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x2d2c272602201b1a00000000feff0002 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dc22425		ld3 {v5.b, v6.b, v7.b}[9], [x1], x2
+#    v5: 0x4f4f4f4f4f4f854f4f4f4f4f4f4f4f4f <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x82818281828186818281828182818281 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000087000b0a0504fffef9f8 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0ddf2037		ld3 {v23.b, v24.b, v25.b}[0], [x1], #3
+#   v23: 0x2d2c272602201b1a00000000feff0084 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x2f2e292823221d1c1700000000ff0085 <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x3b3a39382f2e2d2c2322212017161586 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d40a410		ld3 {v16.d, v17.d, v18.d}[0], [x0]
+#   v16: 0x6e6d6c6b6a696867ff0000850002ff01 (d16: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000474600000000000000fffeff (d17: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0xd2d1d0cfcecdcccb1700000000000000 (d18: 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dc2a43e		ld3 {v30.d, v31.d, v0.d}[0], [x1], x2
+#   v30: 0x84837e7d787772718e8d8c8b8a898887 (d30: -1.41807e-238) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x0000000000000000969594939291908f (d31: -7.04826e-200) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0xc3c2c1c0bfbebdbc9e9d9c9b9a999897 (d0: -3.29099e-161) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4ddfa43c		ld3 {v28.d, v29.d, v30.d}[1], [x1], #24
+#   v28: 0x8d8c8b8a89888786686762615c5b5655 (-2.09028e-243, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x9594939291908f8e6a6964635e5d5857 (-1.02545e-204, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x9d9c9b9a999897968e8d8c8b8a898887 (-4.85140e-166, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d40700d		ld3 {v13.h, v14.h, v15.h}[2], [x0]
+#   v13: 0x81807b7a75746f6e6968ff015d5c5756 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x83827d7c777671706b6a00025f5e5958 <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x85847f7e797873726d6c008561605b5a <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dc27836		ld3 {v22.h, v23.h, v24.h}[7], [x1], x2
+#   v22: 0x9f9e2524ff1e191800000000ff00ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0xa1a0272602201b1a00000000feff0084 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0xa3a2292823221d1c1700000000ff0085 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0ddf782e		ld3 {v14.h, v15.h, v16.h}[3], [x1], #6
+#   v14: 0x83827d7c777671709e9d00025f5e5958 <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x85847f7e79787372a09f008561605b5a <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x6e6d6c6b6a696867a2a100850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d40b016		ld3 {v22.s, v23.s, v24.s}[3], [x0]
+#   v22: 0x0002ff01ff1e191800000000ff00ff01 (2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0xff00008502201b1a00000000feff0084 (-1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00fffeff23221d1c1700000000ff0085 (2.35095e-38, ...) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dc2a03e		ld3 {v30.s, v31.s, v0.s}[2], [x1], x2
+#   v30: 0x9d9c9b9aa6a5a4a38e8d8c8b8a898887 (..., -1.14938e-15, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x00000000aaa9a8a7969594939291908f (..., -3.01375e-13, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0xc3c2c1c0aeadacab9e9d9c9b9a999897 (..., -7.89780e-11, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0ddfb02c		ld3 {v12.s, v13.s, v14.s}[1], [x1], #12
+#   v12: 0x0000000000000000a5a4a3a24744413e (..., -2.85603e-16, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x81807b7a75746f6ea9a8a7a65d5c5756 (..., -7.48978e-14, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x83827d7c77767170adacabaa5f5e5958 (..., -1.96304e-11, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d40e018		ld3r {v24.16b, v25.16b, v26.16b}, [x0]
+#   v24: 0x01010101010101010101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0xffffffffffffffffffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x02020202020202020202020202020202 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dc2e038		ld3r {v24.16b, v25.16b, v26.16b}, [x1], x2
+#   v24: 0xaeaeaeaeaeaeaeaeaeaeaeaeaeaeaeae <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0xafafafafafafafafafafafafafafafaf <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0xb0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4ddfe023		ld3r {v3.16b, v4.16b, v5.16b}, [x1], #3
+#    v3: 0xadadadadadadadadadadadadadadadad <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0xaeaeaeaeaeaeaeaeaeaeaeaeaeaeaeae <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0xafafafafafafafafafafafafafafafaf <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d40ec04		ld3r {v4.1d, v5.1d, v6.1d}, [x0]
+#    v4: 0x0000000000000000ff0000850002ff01 (d4: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x00000000000000000000000000fffeff (d5: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000001700000000000000 (d6: 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dc2ec27		ld3r {v7.1d, v8.1d, v9.1d}, [x1], x2
+#    v7: 0x0000000000000000b7b6b5b4b3b2b1b0 (d7: -2.60696e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0000000000000000bfbebdbcbbbab9b8 (d8: -0.120083) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x0000000000000000c7c6c5c4c3c2c1c0 (d9: -6.05398e+37) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0ddfec31		ld3r {v17.1d, v18.1d, v19.1d}, [x1], #24
+#   v17: 0x0000000000000000b6b5b4b3b2b1b0af (d17: -3.80205e-45) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x0000000000000000bebdbcbbbab9b8b7 (d18: -1.77248e-06) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x0000000000000000c6c5c4c3c2c1c0bf (d19: -8.83040e+32) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d40ec10		ld3r {v16.2d, v17.2d, v18.2d}, [x0]
+#   v16: 0xff0000850002ff01ff0000850002ff01 (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x0000000000fffeff0000000000fffeff (8.28892e-317, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x17000000000000001700000000000000 (6.68887e-198, ...) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dc2ec34		ld3r {v20.2d, v21.2d, v22.2d}, [x1], x2
+#   v20: 0xcecdcccbcac9c8c7cecdcccbcac9c8c7 (-4.11344e+71, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0xd6d5d4d3d2d1d0cfd6d5d4d3d2d1d0cf (-2.05087e+110, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0xdedddcdbdad9d8d7dedddcdbdad9d8d7 (-9.54613e+148, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4ddfec2e		ld3r {v14.2d, v15.2d, v16.2d}, [x1], #24
+#   v14: 0xcdcccbcac9c8c7c6cdcccbcac9c8c7c6 (-6.06516e+66, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0xd5d4d3d2d1d0cfced5d4d3d2d1d0cfce (-2.98548e+105, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0xdddcdbdad9d8d7d6dddcdbdad9d8d7d6 (-1.40766e+144, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d40e80a		ld3r {v10.2s, v11.2s, v12.2s}, [x0]
+#   v10: 0x00000000000000000002ff010002ff01 (s10: 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x0000000000000000ff000085ff000085 (s11: -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x000000000000000000fffeff00fffeff (s12: 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dc2e820		ld3r {v0.2s, v1.2s, v2.2s}, [x1], x2
+#    v0: 0x0000000000000000e1e0dfdee1e0dfde (s0: -5.18525e+20) <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x0000000000000000e5e4e3e2e5e4e3e2 (s1: -1.35113e+23) <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000000000e9e8e7e6e9e8e7e6 (s2: -3.51957e+25) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0ddfe837		ld3r {v23.2s, v24.2s, v25.2s}, [x1], #12
+#   v23: 0x0000000000000000e0dfdedde0dfdedd (s23: -1.29053e+20) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x0000000000000000e4e3e2e1e4e3e2e1 (s24: -3.36301e+22) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x0000000000000000e8e7e6e5e8e7e6e5 (s25: -8.76101e+24) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d40e416		ld3r {v22.4h, v23.4h, v24.4h}, [x0]
+#   v22: 0x0000000000000000ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x00000000000000000002000200020002 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00000000000000000085008500850085 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dc2e426		ld3r {v6.4h, v7.4h, v8.4h}, [x1], x2
+#    v6: 0x0000000000000000eae9eae9eae9eae9 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x0000000000000000ecebecebecebeceb <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0000000000000000eeedeeedeeedeeed <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0ddfe427		ld3r {v7.4h, v8.4h, v9.4h}, [x1], #6
+#    v7: 0x0000000000000000e9e8e9e8e9e8e9e8 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0000000000000000ebeaebeaebeaebea <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x0000000000000000edecedecedecedec <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d40e81a		ld3r {v26.4s, v27.4s, v28.4s}, [x0]
+#   v26: 0x0002ff010002ff010002ff010002ff01 (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0xff000085ff000085ff000085ff000085 (..., -1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x00fffeff00fffeff00fffeff00fffeff (..., 2.35095e-38, ...) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dc2e820		ld3r {v0.4s, v1.4s, v2.4s}, [x1], x2
+#    v0: 0xf1f0efeef1f0efeef1f0efeef1f0efee (..., -2.38613e+30, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0xf5f4f3f2f5f4f3f2f5f4f3f2f5f4f3f2 (..., -6.21029e+32, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0xf9f8f7f6f9f8f7f6f9f8f7f6f9f8f7f6 (..., -1.61590e+35, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4ddfe83e		ld3r {v30.4s, v31.4s, v0.4s}, [x1], #12
+#   v30: 0xf0efeeedf0efeeedf0efeeedf0efeeed (..., -5.94046e+29, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0xf4f3f2f1f4f3f2f1f4f3f2f1f4f3f2f1 (..., -1.54621e+32, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0xf8f7f6f5f8f7f6f5f8f7f6f5f8f7f6f5 (..., -4.02346e+34, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d40e002		ld3r {v2.8b, v3.8b, v4.8b}, [x0]
+#    v2: 0x00000000000000000101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000ffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x00000000000000000202020202020202 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dc2e02a		ld3r {v10.8b, v11.8b, v12.8b}, [x1], x2
+#   v10: 0x0000000000000000f9f9f9f9f9f9f9f9 <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x0000000000000000fafafafafafafafa <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000000000fbfbfbfbfbfbfbfb <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0ddfe03c		ld3r {v28.8b, v29.8b, v30.8b}, [x1], #3
+#   v28: 0x0000000000000000f8f8f8f8f8f8f8f8 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000000000f9f9f9f9f9f9f9f9 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x0000000000000000fafafafafafafafa <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d40e406		ld3r {v6.8h, v7.8h, v8.8h}, [x0]
+#    v6: 0xff01ff01ff01ff01ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00020002000200020002000200020002 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00850085008500850085008500850085 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dc2e43d		ld3r {v29.8h, v30.8h, v31.8h}, [x1], x2
+#   v29: 0xfcfbfcfbfcfbfcfbfcfbfcfbfcfbfcfb <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0xfefdfefdfefdfefdfefdfefdfefdfefd <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x00ff00ff00ff00ff00ff00ff00ff00ff <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4ddfe427		ld3r {v7.8h, v8.8h, v9.8h}, [x1], #6
+#    v7: 0xfbfafbfafbfafbfafbfafbfafbfafbfa <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0xfdfcfdfcfdfcfdfcfdfcfdfcfdfcfdfc <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0xfffefffefffefffefffefffefffefffe <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c400003		ld4 {v3.16b, v4.16b, v5.16b, v6.16b}, [x0]
+#    v3: 0x3c3834302c2824201c18000000ff8501 <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x3d3935312d2925211d19000000fe00ff <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x3e3a36322e2a26221e1a000000ff0002 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x3f3b37332f2b27231f1b17000000ff00 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc20022		ld4 {v2.16b, v3.16b, v4.16b, v5.16b}, [x1], x2
+#    v2: 0x3c3834302c2824201c1814100c080400 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x3d3935312d2925211d1915110d090501 <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x3e3a36322e2a26221e1a16120e0a0602 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x3f3b37332f2b27231f1b17130f0b0703 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf0025		ld4 {v5.16b, v6.16b, v7.16b, v8.16b}, [x1], #64
+#    v5: 0x3b37332f2b27231f1b17130f0b0703ff <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x3c3834302c2824201c1814100c080400 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x3d3935312d2925211d1915110d090501 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x3e3a36322e2a26221e1a16120e0a0602 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c400c12		ld4 {v18.2d, v19.2d, v20.2d, v21.2d}, [x0]
+#   v18: 0x2726252423222120ff0000850002ff01 (4.28794e-120, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x2f2e2d2c2b2a29280000000000fffeff (1.98829e-81, 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x37363534333231301700000000000000 (9.95833e-43, 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x3f3e3d3c3b3a39381f1e1d1c1b1a1918 (0.000461414, 8.56775e-159) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc20c24		ld4 {v4.2d, v5.2d, v6.2d, v7.2d}, [x1], x2
+#    v4: 0x666564636261605f464544434241403f (1.81795e+185, 3.36984e+30) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x6e6d6c6b6a6968674e4d4c4b4a494847 (8.50866e+223, 1.57975e+69) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x767574737271706f565554535251504f (4.22243e+262, 7.82703e+107) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x7e7d7c7b7a7978775e5d5c5b5a595857 (1.97467e+301, 3.66628e+146) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf0c3d		ld4 {v29.2d, v30.2d, v31.2d, v0.2d}, [x1], #64
+#   v29: 0x6564636261605f5e4544434241403f3e (2.64379e+180, 4.89923e+25) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x6d6c6b6a696867664d4c4b4a49484746 (1.25402e+219, 2.32790e+64) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x7574737271706f6e5554535251504f4e (6.14144e+257, 1.13810e+103) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x7d7c7b7a797877765d5c5b5a59585756 (2.91053e+296, 5.40301e+141) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c40081b		ld4 {v27.2s, v28.2s, v29.2s, v30.2s}, [x0]
+#   v27: 0x0000000000000000000000000002ff01 (..., 0.00000, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x000000000000000017000000ff000085 (..., 4.13590e-25, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x00000000000000001b1a191800fffeff (..., 1.27467e-22, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x00000000000000001f1e1d1c00000000 (..., 3.34819e-20, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc20838		ld4 {v24.2s, v25.2s, v26.2s, v27.2s}, [x1], x2
+#   v24: 0x000000000000000091908f8e81807f7e (..., -2.28077e-28, -4.72027e-38) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x00000000000000009594939285848382 (..., -6.00095e-26, -1.24615e-35) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000009998979689888786 (..., -1.57777e-23, -3.28683e-33) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x00000000000000009d9c9b9a8d8c8b8a (..., -4.14537e-21, -8.66176e-31) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf0824		ld4 {v4.2s, v5.2s, v6.2s, v7.2s}, [x1], #32
+#    v4: 0x0000000000000000908f8e8d807f7e7d (..., -5.66232e-29, -1.17085e-38) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x00000000000000009493929184838281 (..., -1.49010e-26, -3.09178e-36) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000009897969588878685 (..., -3.91846e-24, -8.15664e-34) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000009c9b9a998c8b8a89 (..., -1.02970e-21, -2.14997e-31) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c400410		ld4 {v16.4h, v17.4h, v18.4h, v19.4h}, [x0]
+#   v16: 0x000000000000000019180000feffff01 <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000001b1a000000ff0002 <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000001d1c000000000085 <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000001f1e17000000ff00 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc20437		ld4 {v23.4h, v24.4h, v25.4h, v26.4h}, [x1], x2
+#   v23: 0x0000000000000000b6b5aeada6a59e9d <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x0000000000000000b8b7b0afa8a7a09f <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x0000000000000000bab9b2b1aaa9a2a1 <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0000000000000000bcbbb4b3acaba4a3 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf0422		ld4 {v2.4h, v3.4h, v4.4h, v5.4h}, [x1], #32
+#    v2: 0x0000000000000000b5b4adaca5a49d9c <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000b7b6afaea7a69f9e <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000b9b8b1b0a9a8a1a0 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x0000000000000000bbbab3b2abaaa3a2 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c400807		ld4 {v7.4s, v8.4s, v9.4s, v10.4s}, [x0]
+#    v7: 0x3332313023222120000000000002ff01 (4.14886e-08, 8.78905e-18, 0.00000, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x373635342726252417000000ff000085 (1.08604e-05, 2.30573e-15, 4.13590e-25, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x3b3a39382b2a29281b1a191800fffeff (0.00284155, 6.04532e-13, 1.27467e-22, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x3f3e3d3c2f2e2d2c1f1e1d1c00000000 (0.743122, 1.58413e-10, 3.34819e-20, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc2083c		ld4 {v28.4s, v29.4s, v30.4s, v31.4s}, [x1], x2
+#   v28: 0xefeeedecdfdedddccfcecdccbfbebdbc (-1.47890e+29, -3.21185e+19, -6.93919e+09, -1.49017) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0xf3f2f1f0e3e2e1e0d3d2d1d0c3c2c1c0 (-3.84962e+31, -8.37048e+21, -1.81093e+12, -389.514) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0xf7f6f5f4e7e6e5e4d7d6d5d4c7c6c5c4 (-1.00179e+34, -2.18077e+24, -4.72428e+14, -101772.) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0xfbfaf9f8ebeae9e8dbdad9d8cbcac9c8 (-2.60629e+36, -5.67986e+26, -1.23202e+17, -2.65799e+07) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf083d		ld4 {v29.4s, v30.4s, v31.4s, v0.4s}, [x1], #64
+#   v29: 0xeeedecebdedddcdbcecdcccbbebdbcbb (-3.68172e+28, -7.99345e+18, -1.72638e+09, -0.370581) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0xf2f1f0efe2e1e0dfd2d1d0cfc2c1c0bf (-9.58428e+30, -2.08336e+21, -4.50576e+11, -96.8765) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0xf6f5f4f3e6e5e4e3d6d5d4d3c6c5c4c3 (-2.49430e+33, -5.42822e+23, -1.17555e+14, -25314.4) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0xfaf9f8f7eae9e8e7dad9d8d7cac9c8c7 (-6.48966e+35, -1.41390e+26, -3.06592e+16, -6.61207e+06) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c40000f		ld4 {v15.8b, v16.8b, v17.8b, v18.8b}, [x0]
+#   v15: 0x00000000000000001c18000000ff8501 <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x00000000000000001d19000000fe00ff <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000001e1a000000ff0002 <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000001f1b17000000ff00 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc2003b		ld4 {v27.8b, v28.8b, v29.8b, v30.8b}, [x1], x2
+#   v27: 0x000000000000000017130f0b0703fffb <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x00000000000000001814100c080400fc <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x00000000000000001915110d090501fd <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x00000000000000001a16120e0a0602fe <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf0025		ld4 {v5.8b, v6.8b, v7.8b, v8.8b}, [x1], #32
+#    v5: 0x000000000000000016120e0a0602fefa <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x000000000000000017130f0b0703fffb <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000001814100c080400fc <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00000000000000001915110d090501fd <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c400419		ld4 {v25.8h, v26.8h, v27.8h, v28.8h}, [x0]
+#   v25: 0x393831302928212019180000feffff01 <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x3b3a33322b2a23221b1a000000ff0002 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x3d3c35342d2c25241d1c000000000085 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x3f3e37362f2e27261f1e17000000ff00 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc20422		ld4 {v2.8h, v3.8h, v4.8h, v5.8h}, [x1], x2
+#    v2: 0x53524b4a43423b3a33322b2a23221b1a <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x55544d4c45443d3c35342d2c25241d1c <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x57564f4e47463f3e37362f2e27261f1e <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x59585150494841403938313029282120 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf0434		ld4 {v20.8h, v21.8h, v22.8h, v23.8h}, [x1], #64
+#   v20: 0x52514a4942413a3932312a2922211a19 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x54534c4b44433c3b34332c2b24231c1b <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x56554e4d46453e3d36352e2d26251e1d <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x5857504f4847403f3837302f2827201f <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d602c14		ld4 {v20.b, v21.b, v22.b, v23.b}[3], [x0]
+#   v20: 0x52514a4942413a3932312a2901211a19 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x54534c4b44433c3b34332c2bff231c1b <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x56554e4d46453e3d36352e2d02251e1d <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x5857504f4847403f3837302f0027201f <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0de22c2c		ld4 {v12.b, v13.b, v14.b, v15.b}[3], [x1], x2
+#   v12: 0x0000000000000000fbfbfbfb59fbfbfb <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x81807b7a75746f6ea9a8a7a65a5c5756 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0xcdcccbcac9c8c7c6cdcccbca5bc8c7c6 <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x00000000000000001c1800005cff8501 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dff383b		ld4 {v27.b, v28.b, v29.b, v30.b}[6], [x1], #4
+#   v27: 0x3d3c35342d2c25241d58000000000085 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x3f3e37362f2e27261f5917000000ff00 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000000000195a110d090501fd <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x00000000000000001a5b120e0a0602fe <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d60a41c		ld4 {v28.d, v29.d, v30.d, v31.d}[1], [x0]
+#   v28: 0xff0000850002ff011f5917000000ff00 (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000fffeff195a110d090501fd (8.28892e-317, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x17000000000000001a5b120e0a0602fe (6.68887e-198, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x1f1e1d1c1b1a1918d6d5d4d3c6c5c4c3 (8.56775e-159, ...) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4de2a42f		ld4 {v15.d, v16.d, v17.d, v18.d}[1], [x1], x2
+#   v15: 0x636261605f5e5d5c1c1800005cff8501 (5.54935e+170, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x6b6a6968676665641d19000000fe00ff (2.71346e+209, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x737271706f6e6d6c1e1a000000ff0002 (1.28953e+248, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x7b7a7978777675741f1b17000000ff00 (6.29888e+286, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dffa430		ld4 {v16.d, v17.d, v18.d, v19.d}[1], [x1], #32
+#   v16: 0x6261605f5e5d5c5b1d19000000fe00ff (8.00514e+165, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x6a696867666564631e1a000000ff0002 (3.98304e+204, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x7271706f6e6d6c6b1f1b17000000ff00 (1.86056e+243, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x7a797877767574731f1e17000000ff00 (9.24687e+281, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d607002		ld4 {v2.h, v3.h, v4.h, v5.h}[6], [x0]
+#    v2: 0x5352ff0143423b3a33322b2a23221b1a <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x5554000245443d3c35342d2c25241d1c <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x5756008547463f3e37362f2e27261f1e <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x5958ff00494841403938313029282120 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0de27825		ld4 {v5.h, v6.h, v7.h, v8.h}[3], [x1], x2
+#    v5: 0x5958ff00494841407c7b313029282120 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000007e7d0f0b0703fffb <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x0000000000000000807f100c080400fc <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00000000000000008281110d090501fd <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dff7027		ld4 {v7.h, v8.h, v9.h, v10.h}[6], [x1], #8
+#    v7: 0x00007b7a00000000807f100c080400fc <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00007d7c000000008281110d090501fd <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x3b3a7f7e2b2a29281b1a191800fffeff <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x3f3e81802f2e2d2c1f1e1d1c00000000 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d60b006		ld4 {v6.s, v7.s, v8.s, v9.s}[1], [x0]
+#    v6: 0x00000000000000000002ff010703fffb (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00007b7a00000000ff000085080400fc (..., -1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00007d7c0000000000fffeff090501fd (..., 2.35095e-38, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x3b3a7f7e2b2a29280000000000fffeff (..., 0.00000, ...) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4de2a039		ld4 {v25.s, v26.s, v27.s, v28.s}[2], [x1], x2
+#   v25: 0x393831308584838219180000feffff01 (..., -1.24615e-35, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x3b3a3332898887861b1a000000ff0002 (..., -3.28683e-33, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x3d3c35348d8c8b8a1d58000000000085 (..., -8.66176e-31, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0xff00008591908f8e1f5917000000ff00 (..., -2.28077e-28, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dffb028		ld4 {v8.s, v9.s, v10.s, v11.s}[3], [x1], #16
+#    v8: 0x848382810000000000fffeff090501fd (-3.09178e-36, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x888786852b2a29280000000000fffeff (-8.15664e-34, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x8c8b8a892f2e2d2c1f1e1d1c00000000 (-2.14997e-31, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x908f8e8d00000000fafafafafafafafa (-5.66232e-29, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d60e00e		ld4r {v14.16b, v15.16b, v16.16b, v17.16b}, [x0]
+#   v14: 0x01010101010101010101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0xffffffffffffffffffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x02020202020202020202020202020202 <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4de2e02d		ld4r {v13.16b, v14.16b, v15.16b, v16.16b}, [x1], x2
+#   v13: 0x91919191919191919191919191919191 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x92929292929292929292929292929292 <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x93939393939393939393939393939393 <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x94949494949494949494949494949494 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dffe029		ld4r {v9.16b, v10.16b, v11.16b, v12.16b}, [x1], #4
+#    v9: 0x90909090909090909090909090909090 <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x91919191919191919191919191919191 <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x92929292929292929292929292929292 <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x93939393939393939393939393939393 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d60ec08		ld4r {v8.1d, v9.1d, v10.1d, v11.1d}, [x0]
+#    v8: 0x0000000000000000ff0000850002ff01 (d8: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000000000000000fffeff (d9: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x00000000000000001700000000000000 (d10: 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x00000000000000001f1e1d1c1b1a1918 (d11: 8.56775e-159) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0de2ec24		ld4r {v4.1d, v5.1d, v6.1d, v7.1d}, [x1], x2
+#    v4: 0x00000000000000009b9a999897969594 (d4: -1.05028e-175) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x0000000000000000a3a2a1a09f9e9d9c (d5: -5.00653e-137) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x0000000000000000abaaa9a8a7a6a5a4 (d6: -2.43801e-98) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x0000000000000000b3b2b1b0afaeadac (d7: -1.16334e-59) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dffec3a		ld4r {v26.1d, v27.1d, v28.1d, v29.1d}, [x1], #32
+#   v26: 0x00000000000000009a99989796959493 (d26: -1.54211e-180) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000a2a1a09f9e9d9c9b (d27: -7.22772e-142) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x0000000000000000aaa9a8a7a6a5a4a3 (d28: -3.58004e-103) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000000000b2b1b0afaeadacab (d29: -1.67978e-64) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d60ec13		ld4r {v19.2d, v20.2d, v21.2d, v22.2d}, [x0]
+#   v19: 0xff0000850002ff01ff0000850002ff01 (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x0000000000fffeff0000000000fffeff (8.28892e-317, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x17000000000000001700000000000000 (6.68887e-198, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x1f1e1d1c1b1a19181f1e1d1c1b1a1918 (8.56775e-159, ...) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4de2ec3c		ld4r {v28.2d, v29.2d, v30.2d, v31.2d}, [x1], x2
+#   v28: 0xbab9b8b7b6b5b4b3bab9b8b7b6b5b4b3 (-8.31108e-26, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0xc2c1c0bfbebdbcbbc2c1c0bfbebdbcbb (-3.90391e+13, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0xcac9c8c7c6c5c4c3cac9c8c7c6c5c4c3 (-1.92941e+52, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0xd2d1d0cfcecdcccbd2d1d0cfcecdcccb (-9.07279e+90, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dffec2f		ld4r {v15.2d, v16.2d, v17.2d, v18.2d}, [x1], #32
+#   v15: 0xb9b8b7b6b5b4b3b2b9b8b7b6b5b4b3b2 (-1.21867e-30, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0xc1c0bfbebdbcbbbac1c0bfbebdbcbbba (-5.62003e+08, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0xc9c8c7c6c5c4c3c2c9c8c7c6c5c4c3c2 (-2.82942e+47, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0xd1d0cfcecdcccbcad1d0cfcecdcccbca (-1.30639e+86, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d60e81f		ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [x0]
+#   v31: 0x00000000000000000002ff010002ff01 (s31: 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x0000000000000000ff000085ff000085 (s0: -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x000000000000000000fffeff00fffeff (s1: 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x00000000000000000000000000000000 (s2: 0.00000) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0de2e83c		ld4r {v28.2s, v29.2s, v30.2s, v31.2s}, [x1], x2
+#   v28: 0x0000000000000000d5d4d3d2d5d4d3d2 (s28: -2.92508e+13) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000000000d9d8d7d6d9d8d7d6 (s29: -7.62949e+15) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x0000000000000000dddcdbdadddcdbda (s30: -1.98932e+18) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x0000000000000000e1e0dfdee1e0dfde (s31: -5.18525e+20) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dffe82b		ld4r {v11.2s, v12.2s, v13.2s, v14.2s}, [x1], #16
+#   v11: 0x0000000000000000d4d3d2d1d4d3d2d1 (s11: -7.27820e+12) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000000000d8d7d6d5d8d7d6d5 (s12: -1.89854e+15) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x0000000000000000dcdbdad9dcdbdad9 (s13: -4.95069e+17) <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x0000000000000000e0dfdedde0dfdedd (s14: -1.29053e+20) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d60e413		ld4r {v19.4h, v20.4h, v21.4h, v22.4h}, [x0]
+#   v19: 0x0000000000000000ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x00000000000000000002000200020002 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x00000000000000000085008500850085 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x0000000000000000ff00ff00ff00ff00 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0de2e436		ld4r {v22.4h, v23.4h, v24.4h, v25.4h}, [x1], x2
+#   v22: 0x0000000000000000e2e1e2e1e2e1e2e1 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x0000000000000000e4e3e4e3e4e3e4e3 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x0000000000000000e6e5e6e5e6e5e6e5 <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x0000000000000000e8e7e8e7e8e7e8e7 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dffe434		ld4r {v20.4h, v21.4h, v22.4h, v23.4h}, [x1], #8
+#   v20: 0x0000000000000000e1e0e1e0e1e0e1e0 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x0000000000000000e3e2e3e2e3e2e3e2 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x0000000000000000e5e4e5e4e5e4e5e4 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x0000000000000000e7e6e7e6e7e6e7e6 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d60e810		ld4r {v16.4s, v17.4s, v18.4s, v19.4s}, [x0]
+#   v16: 0x0002ff010002ff010002ff010002ff01 (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0xff000085ff000085ff000085ff000085 (..., -1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00fffeff00fffeff00fffeff00fffeff (..., 2.35095e-38, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000000000000000000000 (..., 0.00000, ...) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4de2e839		ld4r {v25.4s, v26.4s, v27.4s, v28.4s}, [x1], x2
+#   v25: 0xebeae9e8ebeae9e8ebeae9e8ebeae9e8 (..., -5.67986e+26, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0xefeeedecefeeedecefeeedecefeeedec (..., -1.47890e+29, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0xf3f2f1f0f3f2f1f0f3f2f1f0f3f2f1f0 (..., -3.84962e+31, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0xf7f6f5f4f7f6f5f4f7f6f5f4f7f6f5f4 (..., -1.00179e+34, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dffe837		ld4r {v23.4s, v24.4s, v25.4s, v26.4s}, [x1], #16
+#   v23: 0xeae9e8e7eae9e8e7eae9e8e7eae9e8e7 (..., -1.41390e+26, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0xeeedecebeeedecebeeedecebeeedeceb (..., -3.68172e+28, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0xf2f1f0eff2f1f0eff2f1f0eff2f1f0ef (..., -9.58428e+30, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0xf6f5f4f3f6f5f4f3f6f5f4f3f6f5f4f3 (..., -2.49430e+33, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d60e016		ld4r {v22.8b, v23.8b, v24.8b, v25.8b}, [x0]
+#   v22: 0x00000000000000000101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x0000000000000000ffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00000000000000000202020202020202 <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0de2e03b		ld4r {v27.8b, v28.8b, v29.8b, v30.8b}, [x1], x2
+#   v27: 0x0000000000000000f7f7f7f7f7f7f7f7 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x0000000000000000f8f8f8f8f8f8f8f8 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000000000f9f9f9f9f9f9f9f9 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x0000000000000000fafafafafafafafa <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dffe03d		ld4r {v29.8b, v30.8b, v31.8b, v0.8b}, [x1], #4
+#   v29: 0x0000000000000000f6f6f6f6f6f6f6f6 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x0000000000000000f7f7f7f7f7f7f7f7 <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x0000000000000000f8f8f8f8f8f8f8f8 <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x0000000000000000f9f9f9f9f9f9f9f9 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d60e41c		ld4r {v28.8h, v29.8h, v30.8h, v31.8h}, [x0]
+#   v28: 0xff01ff01ff01ff01ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x00020002000200020002000200020002 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x00850085008500850085008500850085 <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0xff00ff00ff00ff00ff00ff00ff00ff00 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4de2e439		ld4r {v25.8h, v26.8h, v27.8h, v28.8h}, [x1], x2
+#   v25: 0xfbfafbfafbfafbfafbfafbfafbfafbfa <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0xfdfcfdfcfdfcfdfcfdfcfdfcfdfcfdfc <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0xfffefffefffefffefffefffefffefffe <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x01000100010001000100010001000100 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dffe436		ld4r {v22.8h, v23.8h, v24.8h, v25.8h}, [x1], #8
+#   v22: 0xfaf9faf9faf9faf9faf9faf9faf9faf9 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0xfcfbfcfbfcfbfcfbfcfbfcfbfcfbfcfb <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0xfefdfefdfefdfefdfefdfefdfefdfefd <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x00ff00ff00ff00ff00ff00ff00ff00ff <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4e3a94fd		mla v29.16b, v7.16b, v26.16b
+#   v29: 0x0002000200020002e73aed42f34af952
+0x~~~~~~~~~~~~~~~~  0eae9486		mla v6.2s, v4.2s, v14.2s
+#    v6: 0x0000000000000000dcbb11e0e6481e68
+0x~~~~~~~~~~~~~~~~  2f800969		mla v9.2s, v11.2s, v0.s[2]
+#    v9: 0x00000000000000000000000000fffeff
+0x~~~~~~~~~~~~~~~~  0e799625		mla v5.4h, v17.4h, v25.4h
+#    v5: 0x0000000000000000a4a2261ba09e2217
+0x~~~~~~~~~~~~~~~~  2f7b00f8		mla v24.4h, v7.4h, v11.h[3]
+#   v24: 0x000000000000000082b3330de36793c1
+0x~~~~~~~~~~~~~~~~  4ea4946c		mla v12.4s, v3.4s, v4.4s
+#   v12: 0x00000000000000006f49f4f5e911f705
+0x~~~~~~~~~~~~~~~~  6fa708ea		mla v10.4s, v7.4s, v7.s[3]
+#   v10: 0x00000000000000001700000000000000
+0x~~~~~~~~~~~~~~~~  0e299603		mla v3.8b, v16.8b, v9.8b
+#    v3: 0x000000000000000035342d2c25221f1b
+0x~~~~~~~~~~~~~~~~  4e7296d3		mla v19.8h, v22.8h, v18.8h
+#   v19: 0xfe070c07fe070c07fe070c07fe070c07
+0x~~~~~~~~~~~~~~~~  6f400046		mla v6.8h, v2.8h, v0.h[0]
+#    v6: 0x0000000000000000dcbb11e0e6481e68
+0x~~~~~~~~~~~~~~~~  6e2b9557		mls v23.16b, v10.16b, v11.16b
+#   v23: 0xfcfbfcfbfcfbfcfbf0fbfcfbfcfbfcfb
+0x~~~~~~~~~~~~~~~~  2eb697ee		mls v14.2s, v31.2s, v22.2s
+#   v14: 0x0000000000000000d8e1d7ddd8e1d7dd
+0x~~~~~~~~~~~~~~~~  2fa149bc		mls v28.2s, v13.2s, v1.s[3]
+#   v28: 0x00000000000000000100010001000100
+0x~~~~~~~~~~~~~~~~  2e6d9662		mls v2.4h, v19.4h, v13.4h
+#    v2: 0x0000000000000000ac03d811ac03d811
+0x~~~~~~~~~~~~~~~~  2f6c49f2		mls v18.4h, v15.4h, v12.h[6]
+#   v18: 0x000000000000000000fffeff00fffeff
+0x~~~~~~~~~~~~~~~~  6eb09566		mls v6.4s, v11.4s, v16.4s
+#    v6: 0x00000000000000006347100f6cd41c97
+0x~~~~~~~~~~~~~~~~  6f8a4a17		mls v23.4s, v16.4s, v10.s[2]
+#   v23: 0xfcfbfcfbfcfbfcfbf0fbfcfbfcfbfcfb
+0x~~~~~~~~~~~~~~~~  2e3795ba		mls v26.8b, v13.8b, v23.8b
+#   v26: 0x0000000000000000bd4365396d436539
+0x~~~~~~~~~~~~~~~~  6e6c954a		mls v10.8h, v10.8h, v12.8h
+#   v10: 0x00000000000000008800000000000000
+0x~~~~~~~~~~~~~~~~  6f7e480e		mls v14.8h, v0.8h, v14.h[7]
+#   v14: 0x0000000000000000d8e1d7ddd8e1d7dd
+0x~~~~~~~~~~~~~~~~  5e070436		mov b22, v1.b[3]
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5e1805a7		mov d7, v13.d[1]
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5e0a06ba		mov h26, v21.h[2]
+#   v26: 0x0000000000000000000000000000e3e2
+0x~~~~~~~~~~~~~~~~  5e04067a		mov s26, v19.s[0]
+#   v26: 0x000000000000000000000000fe070c07
+0x~~~~~~~~~~~~~~~~  4eab1d7a		mov v26.16b, v11.16b
+#   v26: 0x0000000000000000d4d3d2d1d4d3d2d1
+0x~~~~~~~~~~~~~~~~  0ea01c14		mov v20.8b, v0.8b
+#   v20: 0x0000000000000000f9f9f9f9f9f9f9f9
+0x~~~~~~~~~~~~~~~~  6e1b24d3		mov v19.b[13], v6.b[4]
+#   v19: 0xfe070f07fe070c07fe070c07fe070c07
+0x~~~~~~~~~~~~~~~~  4e1b1e64		mov v4.b[13], w19
+#    v4: 0x00000000000000009b9a999897969594
+0x~~~~~~~~~~~~~~~~  6e18050b		mov v11.d[1], v8.d[0]
+#   v11: 0xff0000850002ff01d4d3d2d1d4d3d2d1
+0x~~~~~~~~~~~~~~~~  4e081fc3		mov v3.d[0], x30
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e12757d		mov v29.h[4], v11.h[7]
+#   v29: 0x000200020002ff00e73aed42f34af952
+0x~~~~~~~~~~~~~~~~  4e1a1cc2		mov v2.h[6], w6
+#    v2: 0x0000000c00000000ac03d811ac03d811
+0x~~~~~~~~~~~~~~~~  6e0444b6		mov v22.s[0], v5.s[2]
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e1c1d18		mov v24.s[3], w8
+#   v24: 0x000000000000000082b3330de36793c1
+0x~~~~~~~~~~~~~~~~  0e1c3c32		mov w18, v1.s[3]
+#   x18: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  4e083ebc		mov x28, v21.d[0]
+#   x28: 0xe3e2e3e2e3e2e3e2
+0x~~~~~~~~~~~~~~~~  2f03e4f8		movi d24, #0xffff0000ffffff
+#   v24: 0x000000000000000000ffff0000ffffff
+0x~~~~~~~~~~~~~~~~  4f04e41d		movi v29.16b, #0x80
+#   v29: 0x80808080808080808080808080808080
+0x~~~~~~~~~~~~~~~~  6f06e6cc		movi v12.2d, #0xffff00ff00ffff00
+#   v12: 0xffff00ff00ffff00ffff00ff00ffff00
+0x~~~~~~~~~~~~~~~~  0f07658c		movi v12.2s, #0xec, lsl #24
+#   v12: 0x0000000000000000ec000000ec000000
+0x~~~~~~~~~~~~~~~~  0f02d58a		movi v10.2s, #0x4c, msl #16
+#   v10: 0x0000000000000000004cffff004cffff
+0x~~~~~~~~~~~~~~~~  0f06841a		movi v26.4h, #0xc0, lsl #0
+#   v26: 0x000000000000000000c000c000c000c0
+0x~~~~~~~~~~~~~~~~  4f044718		movi v24.4s, #0x98, lsl #16
+#   v24: 0x00980000009800000098000000980000
+0x~~~~~~~~~~~~~~~~  4f06d7c1		movi v1.4s, #0xde, msl #16
+#    v1: 0x00deffff00deffff00deffff00deffff
+0x~~~~~~~~~~~~~~~~  0f02e5b5		movi v21.8b, #0x4d
+#   v21: 0x00000000000000004d4d4d4d4d4d4d4d
+0x~~~~~~~~~~~~~~~~  4f03853d		movi v29.8h, #0x69, lsl #0
+#   v29: 0x00690069006900690069006900690069
+0x~~~~~~~~~~~~~~~~  4e319de1		mul v1.16b, v15.16b, v17.16b
+#    v1: 0x4700008e4b00007a4700008e4b00007a
+0x~~~~~~~~~~~~~~~~  0ebd9e75		mul v21.2s, v19.2s, v29.2s
+#   v21: 0x00000000000000001fc2eedf1fc2eedf
+0x~~~~~~~~~~~~~~~~  0f8380b3		mul v19.2s, v5.2s, v3.s[0]
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e629d7d		mul v29.4h, v11.4h, v2.4h
+#   v29: 0x0000000000000000427957e1427957e1
+0x~~~~~~~~~~~~~~~~  0f4080e2		mul v2.4h, v7.4h, v0.h[0]
+#    v2: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4eb09f59		mul v25.4s, v26.4s, v16.4s
+#   v25: 0x000000000000000042ff40c042ff40c0
+0x~~~~~~~~~~~~~~~~  4f8f88da		mul v26.4s, v6.4s, v15.s[2]
+#   v26: 0x00000000000000009d2fa76ed8a575fe
+0x~~~~~~~~~~~~~~~~  0e3f9deb		mul v11.8b, v15.8b, v31.8b
+#   v11: 0x0000000000000000470049004b004d00
+0x~~~~~~~~~~~~~~~~  4e6f9ff4		mul v20.8h, v31.8h, v15.8h
+#   v20: 0x48004a004c004e0048004a004c004e00
+0x~~~~~~~~~~~~~~~~  4f4988bd		mul v29.8h, v5.8h, v9.h[4]
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e205aad		mvn v13.16b, v21.16b
+#   v13: 0xffffffffffffffffe03d1120e03d1120
+0x~~~~~~~~~~~~~~~~  2e205a7c		mvn v28.8b, v19.8b
+#   v28: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  2f052719		mvni v25.2s, #0xb8, lsl #8
+#   v25: 0x0000000000000000ffff47ffffff47ff
+0x~~~~~~~~~~~~~~~~  2f03d591		mvni v17.2s, #0x6c, msl #16
+#   v17: 0x0000000000000000ff930000ff930000
+0x~~~~~~~~~~~~~~~~  2f02851d		mvni v29.4h, #0x48, lsl #0
+#   v29: 0x0000000000000000ffb7ffb7ffb7ffb7
+0x~~~~~~~~~~~~~~~~  6f034754		mvni v20.4s, #0x7a, lsl #16
+#   v20: 0xff85ffffff85ffffff85ffffff85ffff
+0x~~~~~~~~~~~~~~~~  6f00c7c0		mvni v0.4s, #0x1e, msl #8
+#    v0: 0xffffe100ffffe100ffffe100ffffe100
+0x~~~~~~~~~~~~~~~~  6f0187df		mvni v31.8h, #0x3e, lsl #0
+#   v31: 0xffc1ffc1ffc1ffc1ffc1ffc1ffc1ffc1
+0x~~~~~~~~~~~~~~~~  7ee0b979		neg d25, d11
+#   v25: 0x0000000000000000b8ffb6ffb4ffb300
+0x~~~~~~~~~~~~~~~~  6e20b924		neg v4.16b, v9.16b
+#    v4: 0x00000000000000000000000000010201
+0x~~~~~~~~~~~~~~~~  6ee0bb2b		neg v11.2d, v25.2d
+#   v11: 0x0000000000000000470049004b004d00
+0x~~~~~~~~~~~~~~~~  2ea0ba47		neg v7.2s, v18.2s
+#    v7: 0x0000000000000000ff000101ff000101
+0x~~~~~~~~~~~~~~~~  2e60b9e7		neg v7.4h, v15.4h
+#    v7: 0x00000000000000004648484a4a4c4c4e
+0x~~~~~~~~~~~~~~~~  6ea0ba51		neg v17.4s, v18.4s
+#   v17: 0x0000000000000000ff000101ff000101
+0x~~~~~~~~~~~~~~~~  2e20ba34		neg v20.8b, v17.8b
+#   v20: 0x00000000000000000100ffff0100ffff
+0x~~~~~~~~~~~~~~~~  6e60b960		neg v0.8h, v11.8h
+#    v0: 0x0000000000000000b900b700b500b300
+0x~~~~~~~~~~~~~~~~  4eff1d6d		orn v13.16b, v11.16b, v31.16b
+#   v13: 0x003e003e003e003e473e493e4b3e4d3e
+0x~~~~~~~~~~~~~~~~  0ef61e16		orn v22.8b, v16.8b, v22.8b
+#   v22: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4eb71e31		orr v17.16b, v17.16b, v23.16b
+#   v17: 0xfcfbfcfbfcfbfcfbfffbfdfbfffbfdfb
+0x~~~~~~~~~~~~~~~~  0f071468		orr v8.2s, #0xe3, lsl #0
+#    v8: 0x0000000000000000ff0000e70002ffe3
+0x~~~~~~~~~~~~~~~~  0f04b6eb		orr v11.4h, #0x97, lsl #8
+#   v11: 0x0000000000000000d700df00df00df00
+0x~~~~~~~~~~~~~~~~  4f051567		orr v7.4s, #0xab, lsl #0
+#    v7: 0x000000ab000000ab464848eb4a4c4cef
+0x~~~~~~~~~~~~~~~~  0ea31c88		orr v8.8b, v4.8b, v3.8b
+#    v8: 0x00000000000000000000000000010201
+0x~~~~~~~~~~~~~~~~  4f05b61f		orr v31.8h, #0xb0, lsl #8
+#   v31: 0xffc1ffc1ffc1ffc1ffc1ffc1ffc1ffc1
+0x~~~~~~~~~~~~~~~~  6e379e4b		pmul v11.16b, v18.16b, v23.16b
+#   v11: 0x000000000000000000a9a8a900a9a8a9
+0x~~~~~~~~~~~~~~~~  2e259f08		pmul v8.8b, v24.8b, v5.8b
+#    v8: 0x00000000000000000030000000100000
+0x~~~~~~~~~~~~~~~~  0e36e258		pmull v24.8h, v18.8b, v22.8b
+#   v24: 0x0000555555aa55550000555555aa5555
+0x~~~~~~~~~~~~~~~~  4e35e06d		pmull2 v13.8h, v3.16b, v21.16b
+#   v13: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2eb54156		raddhn v22.2s, v10.2d, v21.2d
+#   v22: 0x000000000000000000000000200feede
+0x~~~~~~~~~~~~~~~~  2e6d41a5		raddhn v5.4h, v13.4s, v13.4s
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e3a422a		raddhn v10.8b, v17.8h, v26.8h
+#   v10: 0x0000000000000000fdfdfdfd9da5d974
+0x~~~~~~~~~~~~~~~~  6e2d43a9		raddhn2 v9.16b, v29.8h, v13.8h
+#    v9: 0x00000000000000000000000000fffeff
+0x~~~~~~~~~~~~~~~~  6eba42fb		raddhn2 v27.4s, v23.2d, v26.2d
+#   v27: 0xfcfbfcfc8e2ba46bfffefffefffefffe
+0x~~~~~~~~~~~~~~~~  6e6743a0		raddhn2 v0.8h, v29.4s, v7.4s
+#    v0: 0x0000000046004a04b900b700b500b300
+0x~~~~~~~~~~~~~~~~  6e6059f6		rbit v22.16b, v15.16b
+#   v22: 0x9d1ded6dad2dcd4d9d1ded6dad2dcd4d
+0x~~~~~~~~~~~~~~~~  2e60587e		rbit v30.8b, v3.8b
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e201b7f		rev16 v31.16b, v27.16b
+#   v31: 0xfbfcfcfc2b8e6ba4fefffefffefffeff
+0x~~~~~~~~~~~~~~~~  0e201b4c		rev16 v12.8b, v26.8b
+#   v12: 0x00000000000000002f9d6ea7a5d8fe75
+0x~~~~~~~~~~~~~~~~  6e200885		rev32 v5.16b, v4.16b
+#    v5: 0x00000000000000000000000001020100
+0x~~~~~~~~~~~~~~~~  2e600b50		rev32 v16.4h, v26.4h
+#   v16: 0x0000000000000000a76e9d2f75fed8a5
+0x~~~~~~~~~~~~~~~~  2e200874		rev32 v20.8b, v3.8b
+#   v20: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e600b94		rev32 v20.8h, v28.8h
+#   v20: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4e200a69		rev64 v9.16b, v19.16b
+#    v9: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ea00a05		rev64 v5.2s, v16.2s
+#    v5: 0x000000000000000075fed8a5a76e9d2f
+0x~~~~~~~~~~~~~~~~  0e600be7		rev64 v7.4h, v31.4h
+#    v7: 0x0000000000000000fefffefffefffeff
+0x~~~~~~~~~~~~~~~~  4ea00b4f		rev64 v15.4s, v26.4s
+#   v15: 0x0000000000000000d8a575fe9d2fa76e
+0x~~~~~~~~~~~~~~~~  0e200939		rev64 v25.8b, v9.8b
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e6008ab		rev64 v11.8h, v5.8h
+#   v11: 0x00000000000000009d2fa76ed8a575fe
+0x~~~~~~~~~~~~~~~~  0f3f8db2		rshrn v18.2s, v13.2d, #1
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f1e8fd9		rshrn v25.4h, v30.4s, #2
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f088d2d		rshrn v13.8b, v9.8h, #8
+#   v13: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f088cc3		rshrn2 v3.16b, v6.8h, #8
+#    v3: 0x0000000063106d1d0000000000000000
+0x~~~~~~~~~~~~~~~~  4f278fa0		rshrn2 v0.4s, v29.2d, #25
+#    v0: 0x00000000dbffdc00b900b700b500b300
+0x~~~~~~~~~~~~~~~~  4f118f5b		rshrn2 v27.8h, v26.4s, #15
+#   v27: 0x000000003a5fb14bfffefffefffefffe
+0x~~~~~~~~~~~~~~~~  2ea4632f		rsubhn v15.2s, v25.2d, v4.2d
+#   v15: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e636137		rsubhn v23.4h, v9.4s, v3.4s
+#   v23: 0x000000000000000000009cf000000000
+0x~~~~~~~~~~~~~~~~  2e3863c6		rsubhn v6.8b, v30.8h, v24.8h
+#    v6: 0x000000000000000000abaaab00abaaab
+0x~~~~~~~~~~~~~~~~  6e346304		rsubhn2 v4.16b, v24.8h, v20.8h
+#    v4: 0x00555655005556550000000000010201
+0x~~~~~~~~~~~~~~~~  6eb662e1		rsubhn2 v1.4s, v23.2d, v22.2d
+#    v1: 0x62e2129262e2af824700008e4b00007a
+0x~~~~~~~~~~~~~~~~  6e746053		rsubhn2 v19.8h, v2.4s, v20.4s
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e397d3c		saba v28.16b, v9.16b, v25.16b
+#   v28: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  0eb47f89		saba v9.2s, v28.2s, v20.2s
+#    v9: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e767ed1		saba v17.4h, v22.4h, v22.4h
+#   v17: 0x0000000000000000fffbfdfbfffbfdfb
+0x~~~~~~~~~~~~~~~~  4ebb7cbd		saba v29.4s, v5.4s, v27.4s
+#   v29: 0x000000003a5fb14b75b7d85e58486286
+0x~~~~~~~~~~~~~~~~  0e327eb4		saba v20.8b, v21.8b, v18.8b
+#   v20: 0x00000000000000001e3d11201e3d1120
+0x~~~~~~~~~~~~~~~~  4e7e7e3b		saba v27.8h, v17.8h, v30.8h
+#   v27: 0x000000003a5fb14b0003020300030203
+0x~~~~~~~~~~~~~~~~  0ea751b4		sabal v20.2d, v13.2s, v7.2s
+#   v20: 0x00000000010001011e3d11201f3d1221
+0x~~~~~~~~~~~~~~~~  0e645184		sabal v4.4s, v12.4h, v4.4h
+#    v4: 0x005585f20055c4fc00005a290001058d
+0x~~~~~~~~~~~~~~~~  0e345317		sabal v23.8h, v24.8b, v20.8b
+#   v23: 0x001e003d0044003500369d8300430034
+0x~~~~~~~~~~~~~~~~  4eb252ba		sabal2 v26.2d, v21.4s, v18.4s
+#   v26: 0x00000000000000009d2fa76ed8a575fe
+0x~~~~~~~~~~~~~~~~  4e68539b		sabal2 v27.4s, v28.8h, v8.8h
+#   v27: 0x000000003a5fb14b0003020300030203
+0x~~~~~~~~~~~~~~~~  4e35520c		sabal2 v12.8h, v16.16b, v21.16b
+#   v12: 0x00000000000000002f9d6ea7a5d8fe75
+0x~~~~~~~~~~~~~~~~  4e2d75e0		sabd v0.16b, v15.16b, v13.16b
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ebe74ef		sabd v15.2s, v7.2s, v30.2s
+#   v15: 0x00000000000000000100010101000101
+0x~~~~~~~~~~~~~~~~  0e6c7631		sabd v17.4h, v17.4h, v12.4h
+#   v17: 0x00000000000000002fa270ac5a23007a
+0x~~~~~~~~~~~~~~~~  4eb67487		sabd v7.4s, v4.4s, v22.4s
+#    v7: 0x633798855327f7af62e26cbc52d33840
+0x~~~~~~~~~~~~~~~~  0e3a7477		sabd v23.8b, v3.8b, v26.8b
+#   v23: 0x0000000000000000632f596e285b7502
+0x~~~~~~~~~~~~~~~~  4e657794		sabd v20.8h, v28.8h, v5.8h
+#   v20: 0x000000000000000075ff275a589162d0
+0x~~~~~~~~~~~~~~~~  0eb472db		sabdl v27.2d, v22.2s, v20.2s
+#   v27: 0x00000000d8e139ed00000000ab639583
+0x~~~~~~~~~~~~~~~~  0e77729f		sabdl v31.4s, v20.4h, v23.4h
+#   v31: 0x000012d0000032140000303600001232
+0x~~~~~~~~~~~~~~~~  0e3b7280		sabdl v0.8h, v20.8b, v27.8b
+#    v0: 0x007500010027005a00ad00d200cd004d
+0x~~~~~~~~~~~~~~~~  4ea3717f		sabdl2 v31.2d, v11.4s, v3.4s
+#   v31: 0x00000000000000000000000063106d1d
+0x~~~~~~~~~~~~~~~~  4e7b717a		sabdl2 v26.4s, v11.8h, v27.8h
+#   v26: 0x00000000000000000000271f000039ed
+0x~~~~~~~~~~~~~~~~  4e327106		sabdl2 v6.8h, v8.16b, v18.16b
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ea06b48		sadalp v8.1d, v26.2s
+#    v8: 0x0000000000000000003000000010610c
+0x~~~~~~~~~~~~~~~~  4ea06b4c		sadalp v12.2d, v26.4s
+#   v12: 0x00000000000000002f9d6ea7a5d95f81
+0x~~~~~~~~~~~~~~~~  0e606b4c		sadalp v12.2s, v26.4h
+#   v12: 0x00000000000000002f9d95c6a5d9996e
+0x~~~~~~~~~~~~~~~~  0e206824		sadalp v4.4h, v1.8b
+#    v4: 0x0000000000000000004759b7004c0607
+0x~~~~~~~~~~~~~~~~  4e606a2f		sadalp v15.4s, v17.8h
+#   v15: 0x00000000000000000100a14f01005b9e
+0x~~~~~~~~~~~~~~~~  4e206b35		sadalp v21.8h, v25.16b
+#   v21: 0x00000000000000001fc2eedf1fc2eedf
+0x~~~~~~~~~~~~~~~~  0eae0145		saddl v5.2d, v10.2s, v14.2s
+#    v5: 0xffffffffd6dfd5daffffffff7687b151
+0x~~~~~~~~~~~~~~~~  0e6f0072		saddl v18.4s, v3.4h, v15.4h
+#   v18: 0x00000100ffffa14f0000010000005b9e
+0x~~~~~~~~~~~~~~~~  0e37004f		saddl v15.8h, v2.8b, v23.8b
+#   v15: 0x0063002f0059006e0028005b00750002
+0x~~~~~~~~~~~~~~~~  4ebb0210		saddl2 v16.2d, v16.4s, v27.4s
+#   v16: 0x0000000000000000ffffffffd8e139ed
+0x~~~~~~~~~~~~~~~~  4e600306		saddl2 v6.4s, v24.8h, v0.8h
+#    v6: 0x0000007500005556000055d1000055af
+0x~~~~~~~~~~~~~~~~  4e3c0287		saddl2 v7.8h, v20.16b, v28.16b
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ea02b2a		saddlp v10.1d, v25.2s
+#   v10: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ea02a0f		saddlp v15.2d, v16.4s
+#   v15: 0x0000000000000000ffffffffd8e139ec
+0x~~~~~~~~~~~~~~~~  0e602952		saddlp v18.2s, v10.4h
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e202b5d		saddlp v29.4h, v26.8b
+#   v29: 0x00000000000000000000004600000026
+0x~~~~~~~~~~~~~~~~  4e60282a		saddlp v10.4s, v1.8h
+#   v10: 0x00007574000012640000478e00004b7a
+0x~~~~~~~~~~~~~~~~  4e202aa0		saddlp v0.8h, v21.16b
+#    v0: 0x0000000000000000ffe1ffcdffe1ffcd
+0x~~~~~~~~~~~~~~~~  4eb038ec		saddlv d12, v7.4s
+#   v12: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e303b8e		saddlv h14, v28.16b
+#   v14: 0x0000000000000000000000000000fff8
+0x~~~~~~~~~~~~~~~~  0e303bde		saddlv h30, v30.8b
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e70387b		saddlv s27, v3.4h
+#   v27: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e703a10		saddlv s16, v16.8h
+#   v16: 0x000000000000000000000000000012cc
+0x~~~~~~~~~~~~~~~~  0eb21178		saddw v24.2d, v11.2d, v18.2s
+#   v24: 0x00000000000000009d2fa76ed8a575fe
+0x~~~~~~~~~~~~~~~~  0e66118d		saddw v13.4s, v12.4s, v6.4h
+#   v13: 0x00000000000055d100000000000055af
+0x~~~~~~~~~~~~~~~~  0e271273		saddw v19.8h, v19.8h, v7.8b
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4eba113b		saddw2 v27.2d, v9.2d, v26.4s
+#   v27: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e7512f3		saddw2 v19.4s, v23.4s, v21.8h
+#   v19: 0x0000000000000000632f596e285b7502
+0x~~~~~~~~~~~~~~~~  4e3e132f		saddw2 v15.8h, v25.8h, v30.16b
+#   v15: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e290487		shadd v7.16b, v4.16b, v9.16b
+#    v7: 0x000000000000000000232cdb00260303
+0x~~~~~~~~~~~~~~~~  0eb8073d		shadd v29.2s, v25.2s, v24.2s
+#   v29: 0x0000000000000000ce97d3b7ec52baff
+0x~~~~~~~~~~~~~~~~  0e6d055f		shadd v31.4h, v10.4h, v13.4h
+#   v31: 0x0000000000000000000023c700005094
+0x~~~~~~~~~~~~~~~~  4ea80615		shadd v21.4s, v16.4s, v8.4s
+#   v21: 0x000000000000000000180000000839ec
+0x~~~~~~~~~~~~~~~~  0e3607ae		shadd v14.8b, v29.8b, v22.8b
+#   v14: 0x0000000000000000b5dae012cc3fc326
+0x~~~~~~~~~~~~~~~~  4e740713		shadd v19.8h, v24.8h, v20.8h
+#   v19: 0x00000000000000000997e764189b6c67
+0x~~~~~~~~~~~~~~~~  5f575736		shl d22, d25, #23
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f0f5625		shl v5.16b, v17.16b, #7
+#    v5: 0x00000000000000008000000000800000
+0x~~~~~~~~~~~~~~~~  4f555482		shl v2.2d, v4.2d, #21
+#    v2: 0x000000000000000036e00980c0e00000
+0x~~~~~~~~~~~~~~~~  0f3a5464		shl v4.2s, v3.2s, #26
+#    v4: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f185783		shl v3.4h, v28.4h, #8
+#    v3: 0x0000000000000000ff00ff00ff00ff00
+0x~~~~~~~~~~~~~~~~  4f3857e4		shl v4.4s, v31.4s, #24
+#    v4: 0x0000000000000000c700000094000000
+0x~~~~~~~~~~~~~~~~  0f0a5612		shl v18.8b, v16.8b, #2
+#   v18: 0x00000000000000000000000000004830
+0x~~~~~~~~~~~~~~~~  4f135560		shl v0.8h, v11.8h, #3
+#    v0: 0x0000000000000000e9783b70c528aff0
+0x~~~~~~~~~~~~~~~~  2ea13b05		shll v5.2d, v24.2s, #32
+#    v5: 0x9d2fa76e00000000d8a575fe00000000
+0x~~~~~~~~~~~~~~~~  2e613a9a		shll v26.4s, v20.4h, #16
+#   v26: 0x75ff0000275a00005891000062d00000
+0x~~~~~~~~~~~~~~~~  2e213925		shll v5.8h, v9.8b, #8
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ea13b95		shll2 v21.2d, v28.4s, #32
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e613836		shll2 v22.4s, v1.8h, #16
+#   v22: 0x62e200001292000062e20000af820000
+0x~~~~~~~~~~~~~~~~  6e213b3e		shll2 v30.8h, v25.16b, #8
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f248425		shrn v5.2s, v1.2d, #28
+#    v5: 0x00000000000000002e212926700008e4
+0x~~~~~~~~~~~~~~~~  0f19865d		shrn v29.4h, v18.4s, #7
+#   v29: 0x00000000000000000000000000000090
+0x~~~~~~~~~~~~~~~~  0f0e87b1		shrn v17.8b, v29.8h, #2
+#   v17: 0x00000000000000000000000000000024
+0x~~~~~~~~~~~~~~~~  4f0d87c5		shrn2 v5.16b, v30.8h, #3
+#    v5: 0x00000000000000002e212926700008e4
+0x~~~~~~~~~~~~~~~~  4f3f8438		shrn2 v24.4s, v1.2d, #1
+#   v24: 0x317157c12580003d9d2fa76ed8a575fe
+0x~~~~~~~~~~~~~~~~  4f1085c5		shrn2 v5.8h, v14.4s, #16
+#    v5: 0x00000000b5dacc3f2e212926700008e4
+0x~~~~~~~~~~~~~~~~  4e3726de		shsub v30.16b, v22.16b, v23.16b
+#   v30: 0x31f1000009c90000ffd9d3c9c393c5ff
+0x~~~~~~~~~~~~~~~~  0eb92776		shsub v22.2s, v27.2s, v25.2s
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e6126cd		shsub v13.4h, v22.4h, v1.4h
+#   v13: 0x0000000000000000dc80ffb9da80ffc3
+0x~~~~~~~~~~~~~~~~  4eb7250a		shsub v10.4s, v8.4s, v23.4s
+#   v10: 0x0000000000000000ce805349ebda7605
+0x~~~~~~~~~~~~~~~~  0e3f2526		shsub v6.8b, v9.8b, v31.8b
+#    v6: 0x00000000000000000000ee1c0000d836
+0x~~~~~~~~~~~~~~~~  4e6827e8		shsub v8.8h, v31.8h, v8.8h
+#    v8: 0x0000000000000000ffe811e3fff8f7c4
+0x~~~~~~~~~~~~~~~~  7f5457b3		sli d19, d29, #20
+#   v19: 0x000000000000000000000000090b6c67
+0x~~~~~~~~~~~~~~~~  6f085709		sli v9.16b, v24.16b, #0
+#    v9: 0x317157c12580003d9d2fa76ed8a575fe
+0x~~~~~~~~~~~~~~~~  6f4a5536		sli v22.2d, v9.2d, #10
+#   v22: 0xc55f04960000f400be9dbb6295d7f800
+0x~~~~~~~~~~~~~~~~  2f34576b		sli v11.2s, v27.2s, #20
+#   v11: 0x0000000000000000000fa76e000575fe
+0x~~~~~~~~~~~~~~~~  2f1555f0		sli v16.4h, v15.4h, #5
+#   v16: 0x0000000000000000000000000000000c
+0x~~~~~~~~~~~~~~~~  6f395508		sli v8.4s, v8.4s, #25
+#    v8: 0x0000000000000000c7e811e389f8f7c4
+0x~~~~~~~~~~~~~~~~  2f0857ca		sli v10.8b, v30.8b, #0
+#   v10: 0x0000000000000000ffd9d3c9c393c5ff
+0x~~~~~~~~~~~~~~~~  6f165787		sli v7.8h, v28.8h, #6
+#    v7: 0x0000000000000000ffe3ffdbffe6ffc3
+0x~~~~~~~~~~~~~~~~  4e216512		smax v18.16b, v8.16b, v1.16b
+#   v18: 0x6200120062000000470011e34b00007a
+0x~~~~~~~~~~~~~~~~  0ea164be		smax v30.2s, v5.2s, v1.2s
+#   v30: 0x00000000000000004700008e700008e4
+0x~~~~~~~~~~~~~~~~  0e736731		smax v17.4h, v25.4h, v19.4h
+#   v17: 0x000000000000000000000000090b6c67
+0x~~~~~~~~~~~~~~~~  4ebf6701		smax v1.4s, v24.4s, v31.4s
+#    v1: 0x317157c12580003d000023c700005094
+0x~~~~~~~~~~~~~~~~  0e386711		smax v17.8b, v24.8b, v24.8b
+#   v17: 0x00000000000000009d2fa76ed8a575fe
+0x~~~~~~~~~~~~~~~~  4e6a674b		smax v11.8h, v26.8h, v10.8h
+#   v11: 0x75ff0000275a00005891000062d00000
+0x~~~~~~~~~~~~~~~~  4e27a5cc		smaxp v12.16b, v14.16b, v7.16b
+#   v12: 0x00000000ffffffff00000000da123f26
+0x~~~~~~~~~~~~~~~~  0ea6a71f		smaxp v31.2s, v24.2s, v6.2s
+#   v31: 0x00000000000000000000ee1cd8a575fe
+0x~~~~~~~~~~~~~~~~  0e6aa7aa		smaxp v10.4h, v29.4h, v10.4h
+#   v10: 0x00000000000000000090009000000090
+0x~~~~~~~~~~~~~~~~  4ea7a572		smaxp v18.4s, v11.4s, v7.4s
+#   v18: 0x00000000ffe6ffc375ff000062d00000
+0x~~~~~~~~~~~~~~~~  0e32a415		smaxp v21.8b, v0.8b, v18.8b
+#   v21: 0x000000000000000075006200787028f0
+0x~~~~~~~~~~~~~~~~  4e6fa51a		smaxp v26.8h, v8.8h, v15.8h
+#   v26: 0x00000000000000000000000011e3f7c4
+0x~~~~~~~~~~~~~~~~  4e30a8a4		smaxv b4, v5.16b
+#    v4: 0x00000000000000000000000000000070
+0x~~~~~~~~~~~~~~~~  0e30a817		smaxv b23, v0.8b
+#   v23: 0x00000000000000000000000000000078
+0x~~~~~~~~~~~~~~~~  0e70a806		smaxv h6, v0.4h
+#    v6: 0x00000000000000000000000000003b70
+0x~~~~~~~~~~~~~~~~  4e70a918		smaxv h24, v8.8h
+#   v24: 0x000000000000000000000000000011e3
+0x~~~~~~~~~~~~~~~~  4eb0aa03		smaxv s3, v16.4s
+#    v3: 0x0000000000000000000000000000000c
+0x~~~~~~~~~~~~~~~~  4e326d18		smin v24.16b, v8.16b, v18.16b
+#   v24: 0x00000000ffe6ffc3c7e800e389d0f7c4
+0x~~~~~~~~~~~~~~~~  0eb76d1d		smin v29.2s, v8.2s, v23.2s
+#   v29: 0x0000000000000000c7e811e389f8f7c4
+0x~~~~~~~~~~~~~~~~  0e756d66		smin v6.4h, v11.4h, v21.4h
+#    v6: 0x00000000000000005891000062d00000
+0x~~~~~~~~~~~~~~~~  4eaf6ef8		smin v24.4s, v23.4s, v15.4s
+#   v24: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e246e08		smin v8.8b, v16.8b, v4.8b
+#    v8: 0x0000000000000000000000000000000c
+0x~~~~~~~~~~~~~~~~  4e6a6c2c		smin v12.8h, v1.8h, v10.8h
+#   v12: 0x00000000000000000000009000000090
+0x~~~~~~~~~~~~~~~~  4e3cae4d		sminp v13.16b, v18.16b, v28.16b
+#   v13: 0x00000000ffffffff0000e6c3ff00d000
+0x~~~~~~~~~~~~~~~~  0eb0af96		sminp v22.2s, v28.2s, v16.2s
+#   v22: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  0e65ad8f		sminp v15.4h, v12.4h, v5.4h
+#   v15: 0x0000000000000000292608e400000000
+0x~~~~~~~~~~~~~~~~  4ea8ae2f		sminp v15.4s, v17.4s, v8.4s
+#   v15: 0x0000000000000000000000009d2fa76e
+0x~~~~~~~~~~~~~~~~  0e26ac55		sminp v21.8b, v2.8b, v6.8b
+#   v21: 0x00000000000000009100d000e080c000
+0x~~~~~~~~~~~~~~~~  4e66ad95		sminp v21.8h, v12.8h, v6.8h
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e31a8c8		sminv b8, v6.16b
+#    v8: 0x00000000000000000000000000000091
+0x~~~~~~~~~~~~~~~~  0e31aa46		sminv b6, v18.8b
+#    v6: 0x000000000000000000000000000000d0
+0x~~~~~~~~~~~~~~~~  0e71a834		sminv h20, v1.4h
+#   v20: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e71aa27		sminv h7, v17.8h
+#    v7: 0x00000000000000000000000000009d2f
+0x~~~~~~~~~~~~~~~~  4eb1a895		sminv s21, v4.4s
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0eb581d8		smlal v24.2d, v14.2s, v21.2s
+#   v24: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f8e287f		smlal v31.2d, v3.2s, v14.s[2]
+#   v31: 0x00000000000000000000ee1cd8a575fe
+0x~~~~~~~~~~~~~~~~  0e758287		smlal v7.4s, v20.4h, v21.4h
+#    v7: 0x00000000000000000000000000009d2f
+0x~~~~~~~~~~~~~~~~  0f792213		smlal v19.4s, v16.4h, v9.h[3]
+#   v19: 0x0000000000000000000000000906ca9b
+0x~~~~~~~~~~~~~~~~  0e2181dd		smlal v29.8h, v14.8b, v1.8b
+#   v29: 0x00000000fba0fbfec7e811e376e8e7bc
+0x~~~~~~~~~~~~~~~~  4eb0835e		smlal2 v30.2d, v26.4s, v16.4s
+#   v30: 0x00000000000000004700008e700008e4
+0x~~~~~~~~~~~~~~~~  4f8123df		smlal2 v31.2d, v30.4s, v1.s[0]
+#   v31: 0x00000000000000000000ee1cd8a575fe
+0x~~~~~~~~~~~~~~~~  4e6380d1		smlal2 v17.4s, v6.8h, v3.8h
+#   v17: 0x00000000000000009d2fa76ed8a575fe
+0x~~~~~~~~~~~~~~~~  4f752beb		smlal2 v11.4s, v31.8h, v5.h[7]
+#   v11: 0x75ff0000275a00005891000062d00000
+0x~~~~~~~~~~~~~~~~  4e3d821e		smlal2 v30.8h, v16.16b, v29.16b
+#   v30: 0x00000000000000004700008e700008e4
+0x~~~~~~~~~~~~~~~~  0eb1a281		smlsl v1.2d, v20.2s, v17.2s
+#    v1: 0x317157c12580003d000023c700005094
+0x~~~~~~~~~~~~~~~~  0fa5699d		smlsl v29.2d, v12.2s, v5.s[3]
+#   v29: 0x00000000fba0fbfec7e811e376e8e7bc
+0x~~~~~~~~~~~~~~~~  0e61a340		smlsl v0.4s, v26.4h, v1.4h
+#    v0: 0x0000000000000000e9783b70c7c032a0
+0x~~~~~~~~~~~~~~~~  0f5668a3		smlsl v3.4s, v5.4h, v6.h[5]
+#    v3: 0x0000000000000000000000000000000c
+0x~~~~~~~~~~~~~~~~  0e3aa004		smlsl v4.8h, v0.8b, v26.8b
+#    v4: 0x000000000000000003c9f8c001c2e9f0
+0x~~~~~~~~~~~~~~~~  4ea5a1ce		smlsl2 v14.2d, v14.4s, v5.4s
+#   v14: 0x0000000000000000b5dae012cc3fc326
+0x~~~~~~~~~~~~~~~~  4fa060af		smlsl2 v15.2d, v5.4s, v0.s[1]
+#   v15: 0x0000000000000000f9797b018bdbc6de
+0x~~~~~~~~~~~~~~~~  4e7fa23d		smlsl2 v29.4s, v17.8h, v31.8h
+#   v29: 0x00000000fba0fbfec7e811e376e8e7bc
+0x~~~~~~~~~~~~~~~~  4f6969e6		smlsl2 v6.4s, v15.8h, v9.h[6]
+#    v6: 0x000000000000000000000000000000d0
+0x~~~~~~~~~~~~~~~~  4e2fa1fe		smlsl2 v30.8h, v15.16b, v15.16b
+#   v30: 0x00000000000000004700008e700008e4
+0x~~~~~~~~~~~~~~~~  0e072cd5		smov w21, v6.b[3]
+#   x21: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  0e1e2f4d		smov w13, v26.h[7]
+#   x13: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  4e0f2e18		smov x24, v16.b[7]
+#   x24: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  4e0e2c87		smov x7, v4.h[3]
+#    x7: 0x00000000000003c9
+0x~~~~~~~~~~~~~~~~  4e0c2cfd		smov x29, v7.s[1]
+#   x29: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  0eb1c3a4		smull v4.2d, v29.2s, v17.2s
+#    v4: 0x15a6d000c90fc48aedb876b6692ad888
+0x~~~~~~~~~~~~~~~~  0f86aabe		smull v30.2d, v21.2s, v6.s[2]
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e77c0b7		smull v23.4s, v5.4h, v23.4h
+#   v23: 0x00000000000000000000000000042ae0
+0x~~~~~~~~~~~~~~~~  0f52a128		smull v8.4s, v9.4h, v2.h[1]
+#    v8: 0x185dc92015d7004009b45060e2e7be40
+0x~~~~~~~~~~~~~~~~  0e21c23f		smull v31.8h, v17.8b, v1.8b
+#   v31: 0x00000000f3d5e78200000000249000d8
+0x~~~~~~~~~~~~~~~~  4eb7c063		smull2 v3.2d, v3.4s, v23.4s
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4fa6a3af		smull2 v15.2d, v29.4s, v6.s[1]
+#   v15: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e7ec293		smull2 v19.4s, v20.8h, v30.8h
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f47a946		smull2 v6.4s, v10.8h, v7.h[4]
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e3bc119		smull2 v25.8h, v8.16b, v27.16b
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5e2079e3		sqabs b3, b15
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5ee0792e		sqabs d14, d9
+#   v14: 0x000000000000000062d05891275a8a02
+0x~~~~~~~~~~~~~~~~  5e607b9f		sqabs h31, h28
+#   v31: 0x00000000000000000000000000000001
+0x~~~~~~~~~~~~~~~~  5ea07808		sqabs s8, s0
+#    v8: 0x000000000000000000000000383fcd60
+0x~~~~~~~~~~~~~~~~  4e2078ee		sqabs v14.16b, v7.16b
+#   v14: 0x0000000000000000000000000000632f
+0x~~~~~~~~~~~~~~~~  4ee07a77		sqabs v23.2d, v19.2d
+#   v23: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ea07b0a		sqabs v10.2s, v24.2s
+#   v10: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e607a7f		sqabs v31.4h, v19.4h
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ea07817		sqabs v23.4s, v0.4s
+#   v23: 0x00000000000000001687c490383fcd60
+0x~~~~~~~~~~~~~~~~  0e207afd		sqabs v29.8b, v23.8b
+#   v29: 0x000000000000000016793c70383f3360
+0x~~~~~~~~~~~~~~~~  4e607ab1		sqabs v17.8h, v21.8h
+#   v17: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5e2d0ee9		sqadd b9, b23, b13
+#    v9: 0x00000000000000000000000000000060
+0x~~~~~~~~~~~~~~~~  5efa0f22		sqadd d2, d25, d26
+#    v2: 0x00000000000000000000000011e3f7c4
+0x~~~~~~~~~~~~~~~~  5e790fa7		sqadd h7, h29, h25
+#    v7: 0x00000000000000000000000000003360
+0x~~~~~~~~~~~~~~~~  5eb80ceb		sqadd s11, s7, s24
+#   v11: 0x00000000000000000000000000003360
+0x~~~~~~~~~~~~~~~~  4e3d0e14		sqadd v20.16b, v16.16b, v29.16b
+#   v20: 0x000000000000000016793c70383f336c
+0x~~~~~~~~~~~~~~~~  4efc0fd7		sqadd v23.2d, v30.2d, v28.2d
+#   v23: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  0ea20e68		sqadd v8.2s, v19.2s, v2.2s
+#    v8: 0x00000000000000000000000011e3f7c4
+0x~~~~~~~~~~~~~~~~  0e7f0d94		sqadd v20.4h, v12.4h, v31.4h
+#   v20: 0x00000000000000000000009000000090
+0x~~~~~~~~~~~~~~~~  4eb10dee		sqadd v14.4s, v15.4s, v17.4s
+#   v14: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e2d0fa2		sqadd v2.8b, v29.8b, v13.8b
+#    v2: 0x000000000000000016792233373f0360
+0x~~~~~~~~~~~~~~~~  4e6e0e67		sqadd v7.8h, v19.8h, v14.8h
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5ebe90af		sqdmlal d15, s5, s30
+#   v15: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5fa23958		sqdmlal d24, s10, v2.s[3]
+#   v24: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5e689269		sqdmlal s9, h19, h8
+#    v9: 0x00000000000000000000000000000060
+0x~~~~~~~~~~~~~~~~  5f7c302e		sqdmlal s14, h1, v12.h[3]
+#   v14: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ebf90be		sqdmlal v30.2d, v5.2s, v31.2s
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0faa31d9		sqdmlal v25.2d, v14.2s, v10.s[1]
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e709233		sqdmlal v19.4s, v17.4h, v16.4h
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f5830a8		sqdmlal v8.4s, v5.4h, v8.h[1]
+#    v8: 0x0672308605c005640fa6a0001322041c
+0x~~~~~~~~~~~~~~~~  4ea392e1		sqdmlal2 v1.2d, v23.4s, v3.4s
+#    v1: 0x317157c12580003d000023c700005094
+0x~~~~~~~~~~~~~~~~  4f893013		sqdmlal2 v19.2d, v0.4s, v9.s[0]
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e6b92da		sqdmlal2 v26.4s, v22.8h, v11.8h
+#   v26: 0x00000000000000000000000011e3f7c4
+0x~~~~~~~~~~~~~~~~  4f4d3b86		sqdmlal2 v6.4s, v28.8h, v13.h[4]
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5eb4b3aa		sqdmlsl d10, s29, s20
+#   v10: 0x0000000000000000ffffffc0b8e63400
+0x~~~~~~~~~~~~~~~~  5faa712a		sqdmlsl d10, s9, v10.s[1]
+#   v10: 0x0000000000000000ffffffc0b8e66400
+0x~~~~~~~~~~~~~~~~  5e78b13e		sqdmlsl s30, h9, h24
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5f56730d		sqdmlsl s13, h24, v6.h[1]
+#   v13: 0x000000000000000000000000ff00d000
+0x~~~~~~~~~~~~~~~~  0eb4b15b		sqdmlsl v27.2d, v10.2s, v20.2s
+#   v27: 0x00000000000048000000004ffccf8000
+0x~~~~~~~~~~~~~~~~  0fa37af7		sqdmlsl v23.2d, v23.2s, v3.s[3]
+#   v23: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  0e7db227		sqdmlsl v7.4s, v17.4h, v29.4h
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f437ab6		sqdmlsl v22.4s, v21.4h, v3.h[4]
+#   v22: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  4eb6b0ec		sqdmlsl2 v12.2d, v7.4s, v22.4s
+#   v12: 0x00000000000000000000009000000090
+0x~~~~~~~~~~~~~~~~  4f887334		sqdmlsl2 v20.2d, v25.4s, v8.s[0]
+#   v20: 0x00000000000000000000009000000090
+0x~~~~~~~~~~~~~~~~  4e72b359		sqdmlsl2 v25.4s, v26.8h, v18.8h
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f457279		sqdmlsl2 v25.4s, v19.8h, v5.h[0]
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5e6cb771		sqdmulh h17, h27, h12
+#   v17: 0x0000000000000000000000000000ff70
+0x~~~~~~~~~~~~~~~~  5f4bc0b0		sqdmulh h16, h5, v11.h[0]
+#   v16: 0x00000000000000000000000000000391
+0x~~~~~~~~~~~~~~~~  5eb0b661		sqdmulh s1, s19, s16
+#    v1: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5f82c201		sqdmulh s1, s16, v2.s[0]
+#    v1: 0x0000000000000000000000000000018a
+0x~~~~~~~~~~~~~~~~  0ea8b43c		sqdmulh v28.2s, v1.2s, v8.2s
+#   v28: 0x0000000000000000000000000000003a
+0x~~~~~~~~~~~~~~~~  0f83c11c		sqdmulh v28.2s, v8.2s, v3.s[0]
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e65b72b		sqdmulh v11.4h, v25.4h, v5.4h
+#   v11: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f58c9de		sqdmulh v30.4h, v14.4h, v8.h[5]
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4eadb6b9		sqdmulh v25.4s, v21.4s, v13.4s
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4faac857		sqdmulh v23.4s, v2.4s, v10.s[3]
+#   v23: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e77b4ba		sqdmulh v26.8h, v5.8h, v23.8h
+#   v26: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f74c2c4		sqdmulh v4.8h, v22.8h, v4.h[3]
+#    v4: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5ebad059		sqdmull d25, s2, s26
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5fa5b1de		sqdmull d30, s14, v5.s[1]
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5e6bd25d		sqdmull s29, h18, h11
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5f67b9ab		sqdmull s11, h13, v7.h[6]
+#   v11: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ea8d137		sqdmull v23.2d, v9.2s, v8.2s
+#   v23: 0x00000000000000000000000e59831500
+0x~~~~~~~~~~~~~~~~  0fa4b3b2		sqdmull v18.2d, v29.2s, v4.s[1]
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e67d311		sqdmull v17.4s, v24.4h, v7.4h
+#   v17: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f55b1e8		sqdmull v8.4s, v15.4h, v5.h[1]
+#    v8: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ea2d1dc		sqdmull2 v28.2d, v14.4s, v2.4s
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f8dbb01		sqdmull2 v1.2d, v24.4s, v13.s[2]
+#    v1: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e7fd22b		sqdmull2 v11.4s, v17.8h, v31.8h
+#   v11: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f7bb281		sqdmull2 v1.4s, v20.8h, v11.h[3]
+#    v1: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7e207802		sqneg b2, b0
+#    v2: 0x00000000000000000000000000000060
+0x~~~~~~~~~~~~~~~~  7ee07858		sqneg d24, d2
+#   v24: 0x0000000000000000ffffffffffffffa0
+0x~~~~~~~~~~~~~~~~  7e60787d		sqneg h29, h3
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7ea07924		sqneg s4, s9
+#    v4: 0x000000000000000000000000ffffffa0
+0x~~~~~~~~~~~~~~~~  6e207bae		sqneg v14.16b, v29.16b
+#   v14: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ee0799e		sqneg v30.2d, v12.2d
+#   v30: 0x0000000000000000ffffff6fffffff70
+0x~~~~~~~~~~~~~~~~  2ea07b5c		sqneg v28.2s, v26.2s
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e607884		sqneg v4.4h, v4.4h
+#    v4: 0x00000000000000000000000000010060
+0x~~~~~~~~~~~~~~~~  6ea07909		sqneg v9.4s, v8.4s
+#    v9: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e207a94		sqneg v20.8b, v20.8b
+#   v20: 0x00000000000000000000007000000070
+0x~~~~~~~~~~~~~~~~  6e60795b		sqneg v27.8h, v10.8h
+#   v27: 0x000000000000000000010040471a9c00
+0x~~~~~~~~~~~~~~~~  7e60b707		sqrdmulh h7, h24, h0
+#    v7: 0x0000000000000000000000000000ffda
+0x~~~~~~~~~~~~~~~~  5f64d86e		sqrdmulh h14, h3, v4.h[6]
+#   v14: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7eb8b67b		sqrdmulh s27, s19, s24
+#   v27: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5f84d2bf		sqrdmulh s31, s21, v4.s[0]
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2ea1b732		sqrdmulh v18.2s, v25.2s, v1.2s
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f8dd0b6		sqrdmulh v22.2s, v5.2s, v13.s[0]
+#   v22: 0x0000000000000000ffa408a4ff20b5ee
+0x~~~~~~~~~~~~~~~~  2e69b716		sqrdmulh v22.4h, v24.4h, v9.4h
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f6cd84d		sqrdmulh v13.4h, v2.4h, v12.h[6]
+#   v13: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ea2b769		sqrdmulh v9.4s, v27.4s, v2.4s
+#    v9: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4fa7d2e3		sqrdmulh v3.4s, v23.4s, v7.s[1]
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e67b402		sqrdmulh v2.8h, v0.8h, v7.8h
+#    v2: 0x0000000000000000000000000000fff1
+0x~~~~~~~~~~~~~~~~  4f68d130		sqrdmulh v16.8h, v9.8h, v8.h[2]
+#   v16: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5e2d5ea8		sqrshl b8, b21, b13
+#    v8: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5ef45cfd		sqrshl d29, d7, d20
+#   v29: 0x00000000000000007fffffffffffffff
+0x~~~~~~~~~~~~~~~~  5e6a5ddc		sqrshl h28, h14, h10
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5ea25e5a		sqrshl s26, s18, s2
+#   v26: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e3a5ff2		sqrshl v18.16b, v31.16b, v26.16b
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ee05c9c		sqrshl v28.2d, v4.2d, v0.2d
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ea05cc3		sqrshl v3.2s, v6.2s, v0.2s
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e765e41		sqrshl v1.4h, v18.4h, v22.4h
+#    v1: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ea75f30		sqrshl v16.4s, v25.4s, v7.4s
+#   v16: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e255ea0		sqrshl v0.8b, v21.8b, v5.8b
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e685e7e		sqrshl v30.8h, v19.8h, v8.8h
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5f0c9ea6		sqrshrn b6, h21, #4
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5f159e2e		sqrshrn h14, s17, #11
+#   v14: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5f369f79		sqrshrn s25, d27, #10
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f2e9da6		sqrshrn v6.2s, v13.2d, #18
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f119d25		sqrshrn v5.4h, v9.4s, #15
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f0f9d93		sqrshrn v19.8b, v12.8h, #1
+#   v19: 0x00000000000000000000000000480048
+0x~~~~~~~~~~~~~~~~  4f099eb3		sqrshrn2 v19.16b, v21.8h, #7
+#   v19: 0x00000000000000000000000000480048
+0x~~~~~~~~~~~~~~~~  4f339f1d		sqrshrn2 v29.4s, v24.2d, #13
+#   v29: 0x00000000000000007fffffffffffffff
+0x~~~~~~~~~~~~~~~~  4f169c4c		sqrshrn2 v12.8h, v2.4s, #10
+#   v12: 0x00000000000000400000009000000090
+0x~~~~~~~~~~~~~~~~  7f0b8d30		sqrshrun b16, h9, #5
+#   v16: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7f118f03		sqrshrun h3, s24, #15
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7f388e50		sqrshrun s16, d18, #8
+#   v16: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f388efc		sqrshrun v28.2s, v23.2d, #8
+#   v28: 0x0000000000000000000000000e598315
+0x~~~~~~~~~~~~~~~~  2f168f3f		sqrshrun v31.4h, v25.4s, #10
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f0e8ef3		sqrshrun v19.8b, v23.8h, #2
+#   v19: 0x0000000000000000000000000004ffff
+0x~~~~~~~~~~~~~~~~  6f088c18		sqrshrun2 v24.16b, v0.8h, #8
+#   v24: 0x0000000000000000ffffffffffffffa0
+0x~~~~~~~~~~~~~~~~  6f298c36		sqrshrun2 v22.4s, v1.2d, #23
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f138ebc		sqrshrun2 v28.8h, v21.4s, #13
+#   v28: 0x0000000000000000000000000e598315
+0x~~~~~~~~~~~~~~~~  5e284ea6		sqshl b6, b21, b8
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5f0a774b		sqshl b11, b26, #2
+#   v11: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5ee44c1d		sqshl d29, d0, d4
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5f6374f5		sqshl d21, d7, #35
+#   v21: 0x00000000000000000007fed000000000
+0x~~~~~~~~~~~~~~~~  5e714f34		sqshl h20, h25, h17
+#   v20: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5f187414		sqshl h20, h0, #8
+#   v20: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5ea44dbd		sqshl s29, s13, s4
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5f34756a		sqshl s10, s11, #20
+#   v10: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e3c4e48		sqshl v8.16b, v18.16b, v28.16b
+#    v8: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f0a77bd		sqshl v29.16b, v29.16b, #2
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ef04fe8		sqshl v8.2d, v31.2d, v16.2d
+#    v8: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f6575c7		sqshl v7.2d, v14.2d, #37
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ea74f40		sqshl v0.2s, v26.2s, v7.2s
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f337565		sqshl v5.2s, v11.2s, #19
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e604fcb		sqshl v11.4h, v30.4h, v0.4h
+#   v11: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f177641		sqshl v1.4h, v18.4h, #7
+#    v1: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ebe4c76		sqshl v22.4s, v3.4s, v30.4s
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f3c75f0		sqshl v16.4s, v15.4s, #28
+#   v16: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e394f86		sqshl v6.8b, v28.8b, v25.8b
+#    v6: 0x0000000000000000000000000e598315
+0x~~~~~~~~~~~~~~~~  0f0875e0		sqshl v0.8b, v15.8b, #0
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e7e4e06		sqshl v6.8h, v16.8h, v30.8h
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f1e7683		sqshl v3.8h, v20.8h, #14
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7f0e65cd		sqshlu b13, b14, #6
+#   v13: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7f6c6600		sqshlu d0, d16, #44
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7f1f67a5		sqshlu h5, h29, #15
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7f2d651d		sqshlu s29, s8, #13
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f0a669b		sqshlu v27.16b, v20.16b, #2
+#   v27: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f4b6598		sqshlu v24.2d, v12.2d, #11
+#   v24: 0x00000000000200000004800000048000
+0x~~~~~~~~~~~~~~~~  2f36666c		sqshlu v12.2s, v19.2s, #22
+#   v12: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  2f1b6588		sqshlu v8.4h, v12.4h, #11
+#    v8: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f286472		sqshlu v18.4s, v3.4s, #8
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f096543		sqshlu v3.8b, v10.8b, #1
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f14671e		sqshlu v30.8h, v24.8h, #4
+#   v30: 0x00000000002000000040000000400000
+0x~~~~~~~~~~~~~~~~  5f0f9781		sqshrn b1, h28, #1
+#    v1: 0x00000000000000000000000000000080
+0x~~~~~~~~~~~~~~~~  5f1694ff		sqshrn h31, s7, #10
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5f289544		sqshrn s4, d10, #24
+#    v4: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f23942a		sqshrn v10.2s, v1.2d, #29
+#   v10: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f1295a3		sqshrn v3.4h, v13.4s, #14
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f0994db		sqshrn v27.8b, v6.8h, #7
+#   v27: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f0f96ee		sqshrn2 v14.16b, v23.8h, #1
+#   v14: 0x0000000000077f7f0000000000000000
+0x~~~~~~~~~~~~~~~~  4f2596d9		sqshrn2 v25.4s, v22.2d, #27
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f16959f		sqshrn2 v31.8h, v12.4s, #10
+#   v31: 0x000000000000ffff0000000000000000
+0x~~~~~~~~~~~~~~~~  7f0f8409		sqshrun b9, h0, #1
+#    v9: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7f1984cb		sqshrun h11, s6, #7
+#   v11: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7f33858d		sqshrun s13, d12, #13
+#   v13: 0x0000000000000000000000000007ffff
+0x~~~~~~~~~~~~~~~~  2f3f87ca		sqshrun v10.2s, v30.2d, #1
+#   v10: 0x000000000000000000100000ffffffff
+0x~~~~~~~~~~~~~~~~  2f15847f		sqshrun v31.4h, v3.4s, #11
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f0887dc		sqshrun v28.8b, v30.8h, #8
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f0d8770		sqshrun2 v16.16b, v27.8h, #3
+#   v16: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f2e85db		sqshrun2 v27.4s, v14.2d, #18
+#   v27: 0x00000001000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f1f85d7		sqshrun2 v23.8h, v14.4s, #1
+#   v23: 0x0000ffff000000000000000e59831500
+0x~~~~~~~~~~~~~~~~  5e2b2fb3		sqsub b19, b29, b11
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5ee62ff5		sqsub d21, d31, d6
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5e732d52		sqsub h18, h10, h19
+#   v18: 0x0000000000000000000000000000ffff
+0x~~~~~~~~~~~~~~~~  5ea02ca6		sqsub s6, s5, s0
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e202ed5		sqsub v21.16b, v22.16b, v0.16b
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ef12d56		sqsub v22.2d, v10.2d, v17.2d
+#   v22: 0x000000000000000000100000ffffffff
+0x~~~~~~~~~~~~~~~~  0ea22ea8		sqsub v8.2s, v21.2s, v2.2s
+#    v8: 0x000000000000000000000000ffff000f
+0x~~~~~~~~~~~~~~~~  0e7b2f32		sqsub v18.4h, v25.4h, v27.4h
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ea62c6d		sqsub v13.4s, v3.4s, v6.4s
+#   v13: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e302fbc		sqsub v28.8b, v29.8b, v16.8b
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e6a2cd1		sqsub v17.8h, v6.8h, v10.8h
+#   v17: 0x0000000000000000fff0000000010001
+0x~~~~~~~~~~~~~~~~  5e214b5b		sqxtn b27, h26
+#   v27: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5e614971		sqxtn h17, s11
+#   v17: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5ea14bf6		sqxtn s22, d31
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ea148ba		sqxtn v26.2s, v5.2d
+#   v26: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e6148ed		sqxtn v13.4h, v7.4s
+#   v13: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e214a73		sqxtn v19.8b, v19.8h
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e214873		sqxtn2 v19.16b, v3.8h
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ea14837		sqxtn2 v23.4s, v1.2d
+#   v23: 0x00000000000000800000000e59831500
+0x~~~~~~~~~~~~~~~~  4e61486d		sqxtn2 v13.8h, v3.4s
+#   v13: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7e21293a		sqxtun b26, h9
+#   v26: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7e612993		sqxtun h19, s12
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7ea128c3		sqxtun s3, d6
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2ea12b5d		sqxtun v29.2s, v26.2d
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e61295a		sqxtun v26.4h, v10.4s
+#   v26: 0x000000000000000000000000ffff0000
+0x~~~~~~~~~~~~~~~~  2e212ba7		sqxtun v7.8b, v29.8h
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e2129d5		sqxtun2 v21.16b, v14.8h
+#   v21: 0x000007ff000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ea129f8		sqxtun2 v24.4s, v15.2d
+#   v24: 0x00000000000000000004800000048000
+0x~~~~~~~~~~~~~~~~  6e61283e		sqxtun2 v30.8h, v1.4s
+#   v30: 0x00000000000000800040000000400000
+0x~~~~~~~~~~~~~~~~  4e2f1635		srhadd v21.16b, v17.16b, v15.16b
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ebd16bc		srhadd v28.2s, v21.2s, v29.2s
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e7e1429		srhadd v9.4h, v1.4h, v30.4h
+#    v9: 0x00000000000000000020000000200040
+0x~~~~~~~~~~~~~~~~  4ea21418		srhadd v24.4s, v0.4s, v2.4s
+#   v24: 0x00000000000000000000000000007ff9
+0x~~~~~~~~~~~~~~~~  0e2f1626		srhadd v6.8b, v17.8b, v15.8b
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e7514e5		srhadd v5.8h, v7.8h, v21.8h
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7f4f45ce		sri d14, d14, #49
+#   v14: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f0c4517		sri v23.16b, v8.16b, #4
+#   v23: 0x0000000000000080000000005f8f1000
+0x~~~~~~~~~~~~~~~~  6f6c45b4		sri v20.2d, v13.2d, #20
+#   v20: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f284450		sri v16.2s, v2.2s, #24
+#   v16: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f1546e5		sri v5.4h, v23.4h, #11
+#    v5: 0x000000000000000000000000000b0002
+0x~~~~~~~~~~~~~~~~  6f2945fb		sri v27.4s, v15.4s, #23
+#   v27: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f0c47b3		sri v19.8b, v29.8b, #4
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f1d47a7		sri v7.8h, v29.8h, #3
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5efa5522		srshl d2, d9, d26
+#    v2: 0x00000000000000000020000000200040
+0x~~~~~~~~~~~~~~~~  4e2b563d		srshl v29.16b, v17.16b, v11.16b
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ee455e8		srshl v8.2d, v15.2d, v4.2d
+#    v8: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ea85639		srshl v25.2s, v17.2s, v8.2s
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e6754f3		srshl v19.4h, v7.4h, v7.4h
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4eb1544d		srshl v13.4s, v2.4s, v17.4s
+#   v13: 0x00000000000000000020000000200040
+0x~~~~~~~~~~~~~~~~  0e3554d6		srshl v22.8b, v6.8b, v21.8b
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e64562a		srshl v10.8h, v17.8h, v4.8h
+#   v10: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5f532655		srshr d21, d18, #45
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f092563		srshr v3.16b, v11.16b, #7
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f4b2755		srshr v21.2d, v26.2d, #53
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f2424ab		srshr v11.2s, v5.2s, #28
+#   v11: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f142647		srshr v7.4h, v18.4h, #12
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f222467		srshr v7.4s, v3.4s, #30
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f0a244e		srshr v14.8b, v2.8b, #6
+#   v14: 0x00000000000000000001000000010001
+0x~~~~~~~~~~~~~~~~  4f1d2695		srshr v21.8h, v20.8h, #3
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5f4137d5		srsra d21, d30, #63
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f0a37db		srsra v27.16b, v30.16b, #6
+#   v27: 0x00000000000000fe0001000000010000
+0x~~~~~~~~~~~~~~~~  4f653594		srsra v20.2d, v12.2d, #27
+#   v20: 0x00000000000000000000000000000020
+0x~~~~~~~~~~~~~~~~  0f3b3620		srsra v0.2s, v17.2s, #5
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f11360e		srsra v14.4h, v16.4h, #15
+#   v14: 0x00000000000000000001000000010001
+0x~~~~~~~~~~~~~~~~  4f2c3472		srsra v18.4s, v3.4s, #20
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f0f3435		srsra v21.8b, v1.8b, #1
+#   v21: 0x000000000000000000000000000000c0
+0x~~~~~~~~~~~~~~~~  4f1e373f		srsra v31.8h, v25.8h, #2
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5ee945a1		sshl d1, d13, d9
+#    v1: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e2f47f1		sshl v17.16b, v31.16b, v15.16b
+#   v17: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ee0460d		sshl v13.2d, v16.2d, v0.2d
+#   v13: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0eb644e0		sshl v0.2s, v7.2s, v22.2s
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e644677		sshl v23.4h, v19.4h, v4.4h
+#   v23: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4eab44a5		sshl v5.4s, v5.4s, v11.4s
+#    v5: 0x000000000000000000000000000b0002
+0x~~~~~~~~~~~~~~~~  0e274777		sshl v23.8b, v27.8b, v7.8b
+#   v23: 0x00000000000000000001000000010000
+0x~~~~~~~~~~~~~~~~  4e65455d		sshl v29.8h, v10.8h, v5.8h
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f37a440		sshll v0.2d, v2.2s, #23
+#    v0: 0x00001000000000000000100020000000
+0x~~~~~~~~~~~~~~~~  0f18a50b		sshll v11.4s, v8.4h, #8
+#   v11: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f09a7a4		sshll v4.8h, v29.8b, #1
+#    v4: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f2ea48a		sshll2 v10.2d, v4.4s, #14
+#   v10: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f16a7fa		sshll2 v26.4s, v31.8h, #6
+#   v26: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f0ca743		sshll2 v3.8h, v26.16b, #4
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5f6c06b3		sshr d19, d21, #20
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f0b06ef		sshr v15.16b, v23.16b, #5
+#   v15: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f5a05d1		sshr v17.2d, v14.2d, #38
+#   v17: 0x00000000000000000000000000000400
+0x~~~~~~~~~~~~~~~~  0f2907a3		sshr v3.2s, v29.2s, #23
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f1c0777		sshr v23.4h, v27.4h, #4
+#   v23: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f3c047c		sshr v28.4s, v3.4s, #4
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f0a044e		sshr v14.8b, v2.8b, #6
+#   v14: 0x00000000000000000000000000000001
+0x~~~~~~~~~~~~~~~~  4f1a0503		sshr v3.8h, v8.8h, #6
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5f54178c		ssra d12, d28, #44
+#   v12: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  4f0c17fd		ssra v29.16b, v31.16b, #4
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f681403		ssra v3.2d, v0.2d, #24
+#    v3: 0x00000000001000000000000000100020
+0x~~~~~~~~~~~~~~~~  0f3a178e		ssra v14.2s, v28.2s, #6
+#   v14: 0x00000000000000000000000000000001
+0x~~~~~~~~~~~~~~~~  0f191512		ssra v18.4h, v8.4h, #7
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f2815df		ssra v31.4s, v14.4s, #24
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f0b175c		ssra v28.8b, v26.8b, #5
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f121529		ssra v9.8h, v9.8h, #14
+#    v9: 0x00000000000000000020000000200040
+0x~~~~~~~~~~~~~~~~  0ea321cd		ssubl v13.2d, v14.2s, v3.2s
+#   v13: 0x0000000000000000ffffffffffefffe1
+0x~~~~~~~~~~~~~~~~  0e682205		ssubl v5.4s, v16.4h, v8.4h
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e262380		ssubl v0.8h, v28.8b, v6.8b
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4eb921a5		ssubl2 v5.2d, v13.4s, v25.4s
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e7121e3		ssubl2 v3.4s, v15.8h, v17.8h
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e2e21ef		ssubl2 v15.8h, v15.16b, v14.16b
+#   v15: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0eba32f9		ssubw v25.2d, v23.2d, v26.2s
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e783255		ssubw v21.4s, v18.4s, v24.4h
+#   v21: 0x000000000000000000000000ffff8007
+0x~~~~~~~~~~~~~~~~  0e2332de		ssubw v30.8h, v22.8h, v3.8b
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ebc3310		ssubw2 v16.2d, v24.2d, v28.4s
+#   v16: 0x00000000000000000000000000007ff9
+0x~~~~~~~~~~~~~~~~  4e6f317f		ssubw2 v31.4s, v11.4s, v15.8h
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e303104		ssubw2 v4.8h, v8.8h, v16.16b
+#    v4: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4c002012		st1 {v18.16b, v19.16b, v20.16b, v21.16b}, [x0]
+#   v18: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v20: 0x00000000000000000000000000000020 -> 0x~~~~~~~~~~~~~~~~
+#   v21: 0x000000000000000000000000ffff8007 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c82202a		st1 {v10.16b, v11.16b, v12.16b, v13.16b}, [x1], x2
+#   v10: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v11: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v12: 0x000000000000000000000000ffffffff -> 0x~~~~~~~~~~~~~~~~
+#   v13: 0x0000000000000000ffffffffffefffe1 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9f203b		st1 {v27.16b, v28.16b, v29.16b, v30.16b}, [x1], #64
+#   v27: 0x00000000000000fe0001000000010000 -> 0x~~~~~~~~~~~~~~~~
+#   v28: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v29: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v30: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c006010		st1 {v16.16b, v17.16b, v18.16b}, [x0]
+#   v16: 0x00000000000000000000000000007ff9 -> 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000000000000000000400 -> 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c826035		st1 {v21.16b, v22.16b, v23.16b}, [x1], x2
+#   v21: 0x000000000000000000000000ffff8007 -> 0x~~~~~~~~~~~~~~~~
+#   v22: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v23: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9f6029		st1 {v9.16b, v10.16b, v11.16b}, [x1], #48
+#    v9: 0x00000000000000000020000000200040 -> 0x~~~~~~~~~~~~~~~~
+#   v10: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v11: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c00a007		st1 {v7.16b, v8.16b}, [x0]
+#    v7: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c82a03a		st1 {v26.16b, v27.16b}, [x1], x2
+#   v26: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v27: 0x00000000000000fe0001000000010000 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9fa036		st1 {v22.16b, v23.16b}, [x1], #32
+#   v22: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v23: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c007017		st1 {v23.16b}, [x0]
+#   v23: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c82703c		st1 {v28.16b}, [x1], x2
+#   v28: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9f7022		st1 {v2.16b}, [x1], #16
+#    v2: 0x00000000000000000020000000200040 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c002c1d		st1 {v29.1d, v30.1d, v31.1d, v0.1d}, [x0]
+#   v29:                 0x0000000000000000 (d29: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#   v30:                 0x0000000000000000 (d30: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#   v31:                 0x0000000000000000 (d31: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v0:                 0x0000000000000000 (d0: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c822c2c		st1 {v12.1d, v13.1d, v14.1d, v15.1d}, [x1], x2
+#   v12:                 0x00000000ffffffff (d12: 2.12200e-314) -> 0x~~~~~~~~~~~~~~~~
+#   v13:                 0xffffffffffefffe1 (d13: -nan) -> 0x~~~~~~~~~~~~~~~~
+#   v14:                 0x0000000000000001 (d14: 4.94066e-324) -> 0x~~~~~~~~~~~~~~~~
+#   v15:                 0x0000000000000000 (d15: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c9f2c3e		st1 {v30.1d, v31.1d, v0.1d, v1.1d}, [x1], #32
+#   v30:                 0x0000000000000000 (d30: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#   v31:                 0x0000000000000000 (d31: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v0:                 0x0000000000000000 (d0: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v1:                 0x0000000000000000 (d1: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c006c10		st1 {v16.1d, v17.1d, v18.1d}, [x0]
+#   v16:                 0x0000000000007ff9 (d16: 1.61861e-319) -> 0x~~~~~~~~~~~~~~~~
+#   v17:                 0x0000000000000400 (d17: 5.05923e-321) -> 0x~~~~~~~~~~~~~~~~
+#   v18:                 0x0000000000000000 (d18: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c826c23		st1 {v3.1d, v4.1d, v5.1d}, [x1], x2
+#    v3:                 0x0000000000000000 (d3: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v4:                 0x0000000000000000 (d4: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v5:                 0x0000000000000000 (d5: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c9f6c2e		st1 {v14.1d, v15.1d, v16.1d}, [x1], #24
+#   v14:                 0x0000000000000001 (d14: 4.94066e-324) -> 0x~~~~~~~~~~~~~~~~
+#   v15:                 0x0000000000000000 (d15: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#   v16:                 0x0000000000007ff9 (d16: 1.61861e-319) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c00ac12		st1 {v18.1d, v19.1d}, [x0]
+#   v18:                 0x0000000000000000 (d18: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#   v19:                 0x0000000000000000 (d19: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c82ac25		st1 {v5.1d, v6.1d}, [x1], x2
+#    v5:                 0x0000000000000000 (d5: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v6:                 0x0000000000000000 (d6: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c9fac22		st1 {v2.1d, v3.1d}, [x1], #16
+#    v2:                 0x0020000000200040 (d2: 4.45015e-308) -> 0x~~~~~~~~~~~~~~~~
+#    v3:                 0x0000000000000000 (d3: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c007c04		st1 {v4.1d}, [x0]
+#    v4:                 0x0000000000000000 (d4: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c827c3b		st1 {v27.1d}, [x1], x2
+#   v27:                 0x0001000000010000 (d27: 1.39067e-309) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c9f7c37		st1 {v23.1d}, [x1], #8
+#   v23:                 0x0000000000000000 (d23: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c002c02		st1 {v2.2d, v3.2d, v4.2d, v5.2d}, [x0]
+#    v2: 0x00000000000000000020000000200040 (0.00000, 4.45015e-308) -> 0x~~~~~~~~~~~~~~~~
+#    v3: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v4: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v5: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c822c36		st1 {v22.2d, v23.2d, v24.2d, v25.2d}, [x1], x2
+#   v22: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#   v23: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00000000000000000000000000007ff9 (0.00000, 1.61861e-319) -> 0x~~~~~~~~~~~~~~~~
+#   v25: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9f2c3c		st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x1], #64
+#   v28: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#   v29: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#   v30: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#   v31: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c006c11		st1 {v17.2d, v18.2d, v19.2d}, [x0]
+#   v17: 0x00000000000000000000000000000400 (0.00000, 5.05923e-321) -> 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c826c30		st1 {v16.2d, v17.2d, v18.2d}, [x1], x2
+#   v16: 0x00000000000000000000000000007ff9 (0.00000, 1.61861e-319) -> 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000000000000000000400 (0.00000, 5.05923e-321) -> 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9f6c36		st1 {v22.2d, v23.2d, v24.2d}, [x1], #48
+#   v22: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#   v23: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00000000000000000000000000007ff9 (0.00000, 1.61861e-319) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c00ac15		st1 {v21.2d, v22.2d}, [x0]
+#   v21: 0x000000000000000000000000ffff8007 (0.00000, 2.12198e-314) -> 0x~~~~~~~~~~~~~~~~
+#   v22: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c82ac26		st1 {v6.2d, v7.2d}, [x1], x2
+#    v6: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9fac3b		st1 {v27.2d, v28.2d}, [x1], #32
+#   v27: 0x00000000000000fe0001000000010000 (1.25493e-321, 1.39067e-309) -> 0x~~~~~~~~~~~~~~~~
+#   v28: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c007c15		st1 {v21.2d}, [x0]
+#   v21: 0x000000000000000000000000ffff8007 (0.00000, 2.12198e-314) -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c827c3d		st1 {v29.2d}, [x1], x2
+#   v29: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9f7c34		st1 {v20.2d}, [x1], #16
+#   v20: 0x00000000000000000000000000000020 (0.00000, 1.58101e-322) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c002816		st1 {v22.2s, v23.2s, v24.2s, v25.2s}, [x0]
+#   v22:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#   v23:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#   v24:                 0x0000000000007ff9 (..., 0.00000, 4.59079e-41) -> 0x~~~~~~~~~~~~~~~~
+#   v25:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c822828		st1 {v8.2s, v9.2s, v10.2s, v11.2s}, [x1], x2
+#    v8:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v9:                 0x0020000000200040 (..., 2.93874e-39, 2.93883e-39) -> 0x~~~~~~~~~~~~~~~~
+#   v10:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#   v11:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c9f282f		st1 {v15.2s, v16.2s, v17.2s, v18.2s}, [x1], #32
+#   v15:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#   v16:                 0x0000000000007ff9 (..., 0.00000, 4.59079e-41) -> 0x~~~~~~~~~~~~~~~~
+#   v17:                 0x0000000000000400 (..., 0.00000, 1.43493e-42) -> 0x~~~~~~~~~~~~~~~~
+#   v18:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c006802		st1 {v2.2s, v3.2s, v4.2s}, [x0]
+#    v2:                 0x0020000000200040 (..., 2.93874e-39, 2.93883e-39) -> 0x~~~~~~~~~~~~~~~~
+#    v3:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v4:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c826837		st1 {v23.2s, v24.2s, v25.2s}, [x1], x2
+#   v23:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#   v24:                 0x0000000000007ff9 (..., 0.00000, 4.59079e-41) -> 0x~~~~~~~~~~~~~~~~
+#   v25:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c9f6827		st1 {v7.2s, v8.2s, v9.2s}, [x1], #24
+#    v7:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v8:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v9:                 0x0020000000200040 (..., 2.93874e-39, 2.93883e-39) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c00a81c		st1 {v28.2s, v29.2s}, [x0]
+#   v28:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#   v29:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c82a83d		st1 {v29.2s, v30.2s}, [x1], x2
+#   v29:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#   v30:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c9fa837		st1 {v23.2s, v24.2s}, [x1], #16
+#   v23:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#   v24:                 0x0000000000007ff9 (..., 0.00000, 4.59079e-41) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c007806		st1 {v6.2s}, [x0]
+#    v6:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c82782b		st1 {v11.2s}, [x1], x2
+#   v11:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c9f7831		st1 {v17.2s}, [x1], #8
+#   v17:                 0x0000000000000400 (..., 0.00000, 1.43493e-42) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c002406		st1 {v6.4h, v7.4h, v8.4h, v9.4h}, [x0]
+#    v6:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    v7:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    v8:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    v9:                 0x0020000000200040 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c822429		st1 {v9.4h, v10.4h, v11.4h, v12.4h}, [x1], x2
+#    v9:                 0x0020000000200040 -> 0x~~~~~~~~~~~~~~~~
+#   v10:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v11:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v12:                 0x00000000ffffffff -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c9f2439		st1 {v25.4h, v26.4h, v27.4h, v28.4h}, [x1], #32
+#   v25:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v26:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v27:                 0x0001000000010000 -> 0x~~~~~~~~~~~~~~~~
+#   v28:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c00640b		st1 {v11.4h, v12.4h, v13.4h}, [x0]
+#   v11:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v12:                 0x00000000ffffffff -> 0x~~~~~~~~~~~~~~~~
+#   v13:                 0xffffffffffefffe1 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c82642a		st1 {v10.4h, v11.4h, v12.4h}, [x1], x2
+#   v10:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v11:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v12:                 0x00000000ffffffff -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c9f642c		st1 {v12.4h, v13.4h, v14.4h}, [x1], #24
+#   v12:                 0x00000000ffffffff -> 0x~~~~~~~~~~~~~~~~
+#   v13:                 0xffffffffffefffe1 -> 0x~~~~~~~~~~~~~~~~
+#   v14:                 0x0000000000000001 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c00a40d		st1 {v13.4h, v14.4h}, [x0]
+#   v13:                 0xffffffffffefffe1 -> 0x~~~~~~~~~~~~~~~~
+#   v14:                 0x0000000000000001 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c82a42f		st1 {v15.4h, v16.4h}, [x1], x2
+#   v15:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v16:                 0x0000000000007ff9 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c9fa435		st1 {v21.4h, v22.4h}, [x1], #16
+#   v21:                 0x00000000ffff8007 -> 0x~~~~~~~~~~~~~~~~
+#   v22:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c007410		st1 {v16.4h}, [x0]
+#   v16:                 0x0000000000007ff9 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c827428		st1 {v8.4h}, [x1], x2
+#    v8:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c9f743e		st1 {v30.4h}, [x1], #8
+#   v30:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c002803		st1 {v3.4s, v4.4s, v5.4s, v6.4s}, [x0]
+#    v3: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v4: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v5: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c822839		st1 {v25.4s, v26.4s, v27.4s, v28.4s}, [x1], x2
+#   v25: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#   v27: 0x00000000000000fe0001000000010000 (0.00000, 3.55930e-43, 9.18355e-41, 9.18355e-41) -> 0x~~~~~~~~~~~~~~~~
+#   v28: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9f2825		st1 {v5.4s, v6.4s, v7.4s, v8.4s}, [x1], #64
+#    v5: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c00681f		st1 {v31.4s, v0.4s, v1.4s}, [x0]
+#   v31: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v0: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v1: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c82683e		st1 {v30.4s, v31.4s, v0.4s}, [x1], x2
+#   v30: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#   v31: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v0: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9f6826		st1 {v6.4s, v7.4s, v8.4s}, [x1], #48
+#    v6: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c00a811		st1 {v17.4s, v18.4s}, [x0]
+#   v17: 0x00000000000000000000000000000400 (0.00000, 0.00000, 0.00000, 1.43493e-42) -> 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c82a83f		st1 {v31.4s, v0.4s}, [x1], x2
+#   v31: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v0: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9fa821		st1 {v1.4s, v2.4s}, [x1], #32
+#    v1: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v2: 0x00000000000000000020000000200040 (0.00000, 0.00000, 2.93874e-39, 2.93883e-39) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c00781a		st1 {v26.4s}, [x0]
+#   v26: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c82782f		st1 {v15.4s}, [x1], x2
+#   v15: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9f782d		st1 {v13.4s}, [x1], #16
+#   v13: 0x0000000000000000ffffffffffefffe1 (0.00000, 0.00000, -nan, -nan) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c00201a		st1 {v26.8b, v27.8b, v28.8b, v29.8b}, [x0]
+#   v26:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v27:                 0x0001000000010000 -> 0x~~~~~~~~~~~~~~~~
+#   v28:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v29:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c82202a		st1 {v10.8b, v11.8b, v12.8b, v13.8b}, [x1], x2
+#   v10:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v11:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v12:                 0x00000000ffffffff -> 0x~~~~~~~~~~~~~~~~
+#   v13:                 0xffffffffffefffe1 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c9f202f		st1 {v15.8b, v16.8b, v17.8b, v18.8b}, [x1], #32
+#   v15:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v16:                 0x0000000000007ff9 -> 0x~~~~~~~~~~~~~~~~
+#   v17:                 0x0000000000000400 -> 0x~~~~~~~~~~~~~~~~
+#   v18:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c006013		st1 {v19.8b, v20.8b, v21.8b}, [x0]
+#   v19:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v20:                 0x0000000000000020 -> 0x~~~~~~~~~~~~~~~~
+#   v21:                 0x00000000ffff8007 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c82603f		st1 {v31.8b, v0.8b, v1.8b}, [x1], x2
+#   v31:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    v0:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    v1:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c9f6029		st1 {v9.8b, v10.8b, v11.8b}, [x1], #24
+#    v9:                 0x0020000000200040 -> 0x~~~~~~~~~~~~~~~~
+#   v10:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v11:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c00a00c		st1 {v12.8b, v13.8b}, [x0]
+#   v12:                 0x00000000ffffffff -> 0x~~~~~~~~~~~~~~~~
+#   v13:                 0xffffffffffefffe1 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c82a022		st1 {v2.8b, v3.8b}, [x1], x2
+#    v2:                 0x0020000000200040 -> 0x~~~~~~~~~~~~~~~~
+#    v3:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c9fa020		st1 {v0.8b, v1.8b}, [x1], #16
+#    v0:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    v1:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c007010		st1 {v16.8b}, [x0]
+#   v16:                 0x0000000000007ff9 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c827039		st1 {v25.8b}, [x1], x2
+#   v25:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c9f703f		st1 {v31.8b}, [x1], #8
+#   v31:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c002404		st1 {v4.8h, v5.8h, v6.8h, v7.8h}, [x0]
+#    v4: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    v5: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c822423		st1 {v3.8h, v4.8h, v5.8h, v6.8h}, [x1], x2
+#    v3: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    v4: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    v5: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9f243a		st1 {v26.8h, v27.8h, v28.8h, v29.8h}, [x1], #64
+#   v26: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v27: 0x00000000000000fe0001000000010000 -> 0x~~~~~~~~~~~~~~~~
+#   v28: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v29: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c00640a		st1 {v10.8h, v11.8h, v12.8h}, [x0]
+#   v10: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v11: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v12: 0x000000000000000000000000ffffffff -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c826435		st1 {v21.8h, v22.8h, v23.8h}, [x1], x2
+#   v21: 0x000000000000000000000000ffff8007 -> 0x~~~~~~~~~~~~~~~~
+#   v22: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v23: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9f6432		st1 {v18.8h, v19.8h, v20.8h}, [x1], #48
+#   v18: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v20: 0x00000000000000000000000000000020 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c00a41a		st1 {v26.8h, v27.8h}, [x0]
+#   v26: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v27: 0x00000000000000fe0001000000010000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c82a438		st1 {v24.8h, v25.8h}, [x1], x2
+#   v24: 0x00000000000000000000000000007ff9 -> 0x~~~~~~~~~~~~~~~~
+#   v25: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9fa431		st1 {v17.8h, v18.8h}, [x1], #32
+#   v17: 0x00000000000000000000000000000400 -> 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c00741d		st1 {v29.8h}, [x0]
+#   v29: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c827433		st1 {v19.8h}, [x1], x2
+#   v19: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9f7437		st1 {v23.8h}, [x1], #16
+#   v23: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d001c13		st1 {v19.b}[15], [x0]
+#   v19: 0x00                               -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d820439		st1 {v25.b}[9], [x1], x2
+#   v25:             0x00                   -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d9f0024		st1 {v4.b}[8], [x1], #1
+#    v4:               0x00                 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d00840d		st1 {v13.d}[0], [x0]
+#   v13:                 0xffffffffffefffe1 (d13: -nan) -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d82843e		st1 {v30.d}[0], [x1], x2
+#   v30:                 0x0000000000000000 (d30: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d9f8423		st1 {v3.d}[0], [x1], #8
+#    v3:                 0x0000000000000000 (d3: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d004016		st1 {v22.h}[0], [x0]
+#   v22:                             0x0000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d82583f		st1 {v31.h}[7], [x1], x2
+#   v31: 0x0000                             -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d9f5837		st1 {v23.h}[3], [x1], #2
+#   v23:                 0x0000             -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d008000		st1 {v0.s}[0], [x0]
+#    v0:                         0x00000000 (s0: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d82902b		st1 {v11.s}[3], [x1], x2
+#   v11: 0x00000000                         (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d9f9038		st1 {v24.s}[3], [x1], #4
+#   v24: 0x00000000                         (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c008007		st2 {v7.16b, v8.16b}, [x0]
+#    v7: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c828025		st2 {v5.16b, v6.16b}, [x1], x2
+#    v5: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9f8032		st2 {v18.16b, v19.16b}, [x1], #32
+#   v18: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c008c0e		st2 {v14.2d, v15.2d}, [x0]
+#   v14: 0x00000000000000000000000000000001 (0.00000, 4.94066e-324) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x00000000000000000000000000000000 (0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c828c27		st2 {v7.2d, v8.2d}, [x1], x2
+#    v7: 0x00000000000000000000000000000000 (0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00000000000000000000000000000000 (0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9f8c38		st2 {v24.2d, v25.2d}, [x1], #32
+#   v24: 0x00000000000000000000000000007ff9 (0.00000, 1.61861e-319) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x00000000000000000000000000000000 (0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c008816		st2 {v22.2s, v23.2s}, [x0]
+#   v22: 0x00000000000000000000000000000000 (..., 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x00000000000000000000000000000000 (..., 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c828824		st2 {v4.2s, v5.2s}, [x1], x2
+#    v4: 0x00000000000000000000000000000000 (..., 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x00000000000000000000000000000000 (..., 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c9f8822		st2 {v2.2s, v3.2s}, [x1], #16
+#    v2: 0x00000000000000000020000000200040 (..., 2.93874e-39, 2.93883e-39) <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x00000000000000000000000000000000 (..., 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c008417		st2 {v23.4h, v24.4h}, [x0]
+#   v23: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00000000000000000000000000007ff9 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c828428		st2 {v8.4h, v9.4h}, [x1], x2
+#    v8: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000000020000000200040 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c9f8427		st2 {v7.4h, v8.4h}, [x1], #16
+#    v7: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c008811		st2 {v17.4s, v18.4s}, [x0]
+#   v17: 0x00000000000000000000000000000400 (0.00000, 0.00000, 0.00000, 1.43493e-42) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c828826		st2 {v6.4s, v7.4s}, [x1], x2
+#    v6: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9f883a		st2 {v26.4s, v27.4s}, [x1], #32
+#   v26: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x00000000000000fe0001000000010000 (0.00000, 3.55930e-43, 9.18355e-41, 9.18355e-41) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c00801f		st2 {v31.8b, v0.8b}, [x0]
+#   v31: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c828020		st2 {v0.8b, v1.8b}, [x1], x2
+#    v0: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c9f8035		st2 {v21.8b, v22.8b}, [x1], #16
+#   v21: 0x000000000000000000000000ffff8007 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c008407		st2 {v7.8h, v8.8h}, [x0]
+#    v7: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c828436		st2 {v22.8h, v23.8h}, [x1], x2
+#   v22: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9f8424		st2 {v4.8h, v5.8h}, [x1], #32
+#    v4: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d201c08		st2 {v8.b, v9.b}[15], [x0]
+#    v8: 0x00                               -> 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00                               -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4da21c28		st2 {v8.b, v9.b}[15], [x1], x2
+#    v8: 0x00                               -> 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00                               -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dbf1027		st2 {v7.b, v8.b}[4], [x1], #2
+#    v7:                       0x00         -> 0x~~~~~~~~~~~~~~~~
+#    v8:                       0x00         -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d208419		st2 {v25.d, v26.d}[0], [x0]
+#   v25:                 0x0000000000000000 (d25: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#   v26:                 0x0000000000000000 (d26: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4da28431		st2 {v17.d, v18.d}[1], [x1], x2
+#   v17: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#   v18: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dbf8423		st2 {v3.d, v4.d}[1], [x1], #16
+#    v3: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d205804		st2 {v4.h, v5.h}[3], [x0]
+#    v4:                 0x0000             -> 0x~~~~~~~~~~~~~~~~
+#    v5:                 0x0000             -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4da24820		st2 {v0.h, v1.h}[5], [x1], x2
+#    v0:         0x0000                     -> 0x~~~~~~~~~~~~~~~~
+#    v1:         0x0000                     -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dbf5036		st2 {v22.h, v23.h}[2], [x1], #4
+#   v22:                     0x0000         -> 0x~~~~~~~~~~~~~~~~
+#   v23:                     0x0000         -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d20900e		st2 {v14.s, v15.s}[3], [x0]
+#   v14: 0x00000000                         (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#   v15: 0x00000000                         (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4da29037		st2 {v23.s, v24.s}[3], [x1], x2
+#   v23: 0x00000000                         (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00000000                         (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dbf8020		st2 {v0.s, v1.s}[2], [x1], #8
+#    v0:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    v1:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c00401a		st3 {v26.16b, v27.16b, v28.16b}, [x0]
+#   v26: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x00000000000000fe0001000000010000 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c824035		st3 {v21.16b, v22.16b, v23.16b}, [x1], x2
+#   v21: 0x000000000000000000000000ffff8007 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9f4038		st3 {v24.16b, v25.16b, v26.16b}, [x1], #48
+#   v24: 0x00000000000000000000000000007ff9 <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c004c11		st3 {v17.2d, v18.2d, v19.2d}, [x0]
+#   v17: 0x00000000000000000000000000000400 (0.00000, 5.05923e-321) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000000000000000000000 (0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000000000000000000000 (0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c824c37		st3 {v23.2d, v24.2d, v25.2d}, [x1], x2
+#   v23: 0x00000000000000000000000000000000 (0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00000000000000000000000000007ff9 (0.00000, 1.61861e-319) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x00000000000000000000000000000000 (0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9f4c2a		st3 {v10.2d, v11.2d, v12.2d}, [x1], #48
+#   v10: 0x00000000000000000000000000000000 (0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x00000000000000000000000000000000 (0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x000000000000000000000000ffffffff (0.00000, 2.12200e-314) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c004809		st3 {v9.2s, v10.2s, v11.2s}, [x0]
+#    v9: 0x00000000000000000020000000200040 (..., 2.93874e-39, 2.93883e-39) <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x00000000000000000000000000000000 (..., 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x00000000000000000000000000000000 (..., 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c82482d		st3 {v13.2s, v14.2s, v15.2s}, [x1], x2
+#   v13: 0x0000000000000000ffffffffffefffe1 (..., -nan, -nan) <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x00000000000000000000000000000001 (..., 0.00000, 1.40130e-45) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x00000000000000000000000000000000 (..., 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c9f4836		st3 {v22.2s, v23.2s, v24.2s}, [x1], #24
+#   v22: 0x00000000000000000000000000000000 (..., 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x00000000000000000000000000000000 (..., 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00000000000000000000000000007ff9 (..., 0.00000, 4.59079e-41) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c00441f		st3 {v31.4h, v0.4h, v1.4h}, [x0]
+#   v31: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c824428		st3 {v8.4h, v9.4h, v10.4h}, [x1], x2
+#    v8: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000000020000000200040 <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c9f4433		st3 {v19.4h, v20.4h, v21.4h}, [x1], #24
+#   v19: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x00000000000000000000000000000020 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x000000000000000000000000ffff8007 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c004812		st3 {v18.4s, v19.4s, v20.4s}, [x0]
+#   v18: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x00000000000000000000000000000020 (0.00000, 0.00000, 0.00000, 4.48416e-44) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c824839		st3 {v25.4s, v26.4s, v27.4s}, [x1], x2
+#   v25: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x00000000000000fe0001000000010000 (0.00000, 3.55930e-43, 9.18355e-41, 9.18355e-41) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9f4830		st3 {v16.4s, v17.4s, v18.4s}, [x1], #48
+#   v16: 0x00000000000000000000000000007ff9 (0.00000, 0.00000, 0.00000, 4.59079e-41) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000000000000000000400 (0.00000, 0.00000, 0.00000, 1.43493e-42) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c00401b		st3 {v27.8b, v28.8b, v29.8b}, [x0]
+#   v27: 0x00000000000000fe0001000000010000 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c82403d		st3 {v29.8b, v30.8b, v31.8b}, [x1], x2
+#   v29: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c9f403e		st3 {v30.8b, v31.8b, v0.8b}, [x1], #24
+#   v30: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c004408		st3 {v8.8h, v9.8h, v10.8h}, [x0]
+#    v8: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000000020000000200040 <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c824432		st3 {v18.8h, v19.8h, v20.8h}, [x1], x2
+#   v18: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x00000000000000000000000000000020 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9f4432		st3 {v18.8h, v19.8h, v20.8h}, [x1], #48
+#   v18: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x00000000000000000000000000000020 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d00281f		st3 {v31.b, v0.b, v1.b}[10], [x0]
+#   v31:           0x00                     -> 0x~~~~~~~~~~~~~~~~
+#    v0:           0x00                     -> 0x~~~~~~~~~~~~~~~~
+#    v1:           0x00                     -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d823424		st3 {v4.b, v5.b, v6.b}[5], [x1], x2
+#    v4:                     0x00           -> 0x~~~~~~~~~~~~~~~~
+#    v5:                     0x00           -> 0x~~~~~~~~~~~~~~~~
+#    v6:                     0x00           -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d9f2425		st3 {v5.b, v6.b, v7.b}[1], [x1], #3
+#    v5:                             0x00   -> 0x~~~~~~~~~~~~~~~~
+#    v6:                             0x00   -> 0x~~~~~~~~~~~~~~~~
+#    v7:                             0x00   -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d00a405		st3 {v5.d, v6.d, v7.d}[0], [x0]
+#    v5:                 0x0000000000000000 (d5: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v6:                 0x0000000000000000 (d6: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v7:                 0x0000000000000000 (d7: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d82a426		st3 {v6.d, v7.d, v8.d}[0], [x1], x2
+#    v6:                 0x0000000000000000 (d6: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v7:                 0x0000000000000000 (d7: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v8:                 0x0000000000000000 (d8: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d9fa420		st3 {v0.d, v1.d, v2.d}[0], [x1], #24
+#    v0:                 0x0000000000000000 (d0: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v1:                 0x0000000000000000 (d1: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v2:                 0x0020000000200040 (d2: 4.45015e-308) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d00701f		st3 {v31.h, v0.h, v1.h}[2], [x0]
+#   v31:                     0x0000         -> 0x~~~~~~~~~~~~~~~~
+#    v0:                     0x0000         -> 0x~~~~~~~~~~~~~~~~
+#    v1:                     0x0000         -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d82682e		st3 {v14.h, v15.h, v16.h}[5], [x1], x2
+#   v14:         0x0000                     -> 0x~~~~~~~~~~~~~~~~
+#   v15:         0x0000                     -> 0x~~~~~~~~~~~~~~~~
+#   v16:         0x0000                     -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d9f7035		st3 {v21.h, v22.h, v23.h}[6], [x1], #6
+#   v21:     0x0000                         -> 0x~~~~~~~~~~~~~~~~
+#   v22:     0x0000                         -> 0x~~~~~~~~~~~~~~~~
+#   v23:     0x0000                         -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d00a015		st3 {v21.s, v22.s, v23.s}[0], [x0]
+#   v21:                         0xffff8007 (s21: -nan) -> 0x~~~~~~~~~~~~~~~~
+#   v22:                         0x00000000 (s22: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#   v23:                         0x00000000 (s23: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d82b02b		st3 {v11.s, v12.s, v13.s}[1], [x1], x2
+#   v11:                 0x00000000         (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#   v12:                 0x00000000         (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#   v13:                 0xffffffff         (..., -nan, ...) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d9fa02f		st3 {v15.s, v16.s, v17.s}[0], [x1], #12
+#   v15:                         0x00000000 (s15: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#   v16:                         0x00007ff9 (s16: 4.59079e-41) -> 0x~~~~~~~~~~~~~~~~
+#   v17:                         0x00000400 (s17: 1.43493e-42) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c000016		st4 {v22.16b, v23.16b, v24.16b, v25.16b}, [x0]
+#   v22: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00000000000000000000000000007ff9 <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c820038		st4 {v24.16b, v25.16b, v26.16b, v27.16b}, [x1], x2
+#   v24: 0x00000000000000000000000000007ff9 <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x00000000000000fe0001000000010000 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9f002f		st4 {v15.16b, v16.16b, v17.16b, v18.16b}, [x1], #64
+#   v15: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x00000000000000000000000000007ff9 <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000000000000000000400 <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c000c10		st4 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0]
+#   v16: 0x00000000000000000000000000007ff9 (0.00000, 1.61861e-319) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000000000000000000400 (0.00000, 5.05923e-321) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000000000000000000000 (0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000000000000000000000 (0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c820c31		st4 {v17.2d, v18.2d, v19.2d, v20.2d}, [x1], x2
+#   v17: 0x00000000000000000000000000000400 (0.00000, 5.05923e-321) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000000000000000000000 (0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000000000000000000000 (0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x00000000000000000000000000000020 (0.00000, 1.58101e-322) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9f0c29		st4 {v9.2d, v10.2d, v11.2d, v12.2d}, [x1], #64
+#    v9: 0x00000000000000000020000000200040 (0.00000, 4.45015e-308) <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x00000000000000000000000000000000 (0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x00000000000000000000000000000000 (0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x000000000000000000000000ffffffff (0.00000, 2.12200e-314) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c000817		st4 {v23.2s, v24.2s, v25.2s, v26.2s}, [x0]
+#   v23: 0x00000000000000000000000000000000 (..., 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00000000000000000000000000007ff9 (..., 0.00000, 4.59079e-41) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x00000000000000000000000000000000 (..., 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000000000000000000000 (..., 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c82082f		st4 {v15.2s, v16.2s, v17.2s, v18.2s}, [x1], x2
+#   v15: 0x00000000000000000000000000000000 (..., 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x00000000000000000000000000007ff9 (..., 0.00000, 4.59079e-41) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000000000000000000400 (..., 0.00000, 1.43493e-42) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000000000000000000000 (..., 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c9f0838		st4 {v24.2s, v25.2s, v26.2s, v27.2s}, [x1], #32
+#   v24: 0x00000000000000000000000000007ff9 (..., 0.00000, 4.59079e-41) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x00000000000000000000000000000000 (..., 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000000000000000000000 (..., 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x00000000000000fe0001000000010000 (..., 9.18355e-41, 9.18355e-41) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c00040e		st4 {v14.4h, v15.4h, v16.4h, v17.4h}, [x0]
+#   v14: 0x00000000000000000000000000000001 <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x00000000000000000000000000007ff9 <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000000000000000000400 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c820432		st4 {v18.4h, v19.4h, v20.4h, v21.4h}, [x1], x2
+#   v18: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x00000000000000000000000000000020 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x000000000000000000000000ffff8007 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c9f0421		st4 {v1.4h, v2.4h, v3.4h, v4.4h}, [x1], #32
+#    v1: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x00000000000000000020000000200040 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c00080d		st4 {v13.4s, v14.4s, v15.4s, v16.4s}, [x0]
+#   v13: 0x0000000000000000ffffffffffefffe1 (0.00000, 0.00000, -nan, -nan) <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x00000000000000000000000000000001 (0.00000, 0.00000, 0.00000, 1.40130e-45) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x00000000000000000000000000007ff9 (0.00000, 0.00000, 0.00000, 4.59079e-41) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c820826		st4 {v6.4s, v7.4s, v8.4s, v9.4s}, [x1], x2
+#    v6: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000000020000000200040 (0.00000, 0.00000, 2.93874e-39, 2.93883e-39) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9f082f		st4 {v15.4s, v16.4s, v17.4s, v18.4s}, [x1], #64
+#   v15: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x00000000000000000000000000007ff9 (0.00000, 0.00000, 0.00000, 4.59079e-41) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000000000000000000400 (0.00000, 0.00000, 0.00000, 1.43493e-42) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c00001a		st4 {v26.8b, v27.8b, v28.8b, v29.8b}, [x0]
+#   v26: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x00000000000000fe0001000000010000 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c820039		st4 {v25.8b, v26.8b, v27.8b, v28.8b}, [x1], x2
+#   v25: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x00000000000000fe0001000000010000 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c9f0033		st4 {v19.8b, v20.8b, v21.8b, v22.8b}, [x1], #32
+#   v19: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x00000000000000000000000000000020 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x000000000000000000000000ffff8007 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c000413		st4 {v19.8h, v20.8h, v21.8h, v22.8h}, [x0]
+#   v19: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x00000000000000000000000000000020 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x000000000000000000000000ffff8007 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c82042f		st4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x1], x2
+#   v15: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x00000000000000000000000000007ff9 <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000000000000000000400 <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9f043f		st4 {v31.8h, v0.8h, v1.8h, v2.8h}, [x1], #64
+#   v31: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x00000000000000000020000000200040 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d203400		st4 {v0.b, v1.b, v2.b, v3.b}[13], [x0]
+#    v0:     0x00                           -> 0x~~~~~~~~~~~~~~~~
+#    v1:     0x00                           -> 0x~~~~~~~~~~~~~~~~
+#    v2:     0x00                           -> 0x~~~~~~~~~~~~~~~~
+#    v3:     0x00                           -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4da22824		st4 {v4.b, v5.b, v6.b, v7.b}[10], [x1], x2
+#    v4:           0x00                     -> 0x~~~~~~~~~~~~~~~~
+#    v5:           0x00                     -> 0x~~~~~~~~~~~~~~~~
+#    v6:           0x00                     -> 0x~~~~~~~~~~~~~~~~
+#    v7:           0x00                     -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dbf2429		st4 {v9.b, v10.b, v11.b, v12.b}[9], [x1], #4
+#    v9:             0x00                   -> 0x~~~~~~~~~~~~~~~~
+#   v10:             0x00                   -> 0x~~~~~~~~~~~~~~~~
+#   v11:             0x00                   -> 0x~~~~~~~~~~~~~~~~
+#   v12:             0x00                   -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d20a402		st4 {v2.d, v3.d, v4.d, v5.d}[1], [x0]
+#    v2: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    v5: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0da2a427		st4 {v7.d, v8.d, v9.d, v10.d}[0], [x1], x2
+#    v7:                 0x0000000000000000 (d7: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v8:                 0x0000000000000000 (d8: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v9:                 0x0020000000200040 (d9: 4.45015e-308) -> 0x~~~~~~~~~~~~~~~~
+#   v10:                 0x0000000000000000 (d10: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dbfa43f		st4 {v31.d, v0.d, v1.d, v2.d}[1], [x1], #32
+#   v31: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    v0: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    v1: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d206802		st4 {v2.h, v3.h, v4.h, v5.h}[1], [x0]
+#    v2:                         0x0020     -> 0x~~~~~~~~~~~~~~~~
+#    v3:                         0x0000     -> 0x~~~~~~~~~~~~~~~~
+#    v4:                         0x0000     -> 0x~~~~~~~~~~~~~~~~
+#    v5:                         0x0000     -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0da2783b		st4 {v27.h, v28.h, v29.h, v30.h}[3], [x1], x2
+#   v27:                 0x0001             -> 0x~~~~~~~~~~~~~~~~
+#   v28:                 0x0000             -> 0x~~~~~~~~~~~~~~~~
+#   v29:                 0x0000             -> 0x~~~~~~~~~~~~~~~~
+#   v30:                 0x0000             -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dbf6038		st4 {v24.h, v25.h, v26.h, v27.h}[4], [x1], #8
+#   v24:             0x0000                 -> 0x~~~~~~~~~~~~~~~~
+#   v25:             0x0000                 -> 0x~~~~~~~~~~~~~~~~
+#   v26:             0x0000                 -> 0x~~~~~~~~~~~~~~~~
+#   v27:             0x00fe                 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d20a012		st4 {v18.s, v19.s, v20.s, v21.s}[2], [x0]
+#   v18:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#   v19:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#   v20:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#   v21:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4da2a026		st4 {v6.s, v7.s, v8.s, v9.s}[2], [x1], x2
+#    v6:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    v7:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    v8:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    v9:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dbfb039		st4 {v25.s, v26.s, v27.s, v28.s}[1], [x1], #16
+#   v25:                 0x00000000         (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#   v26:                 0x00000000         (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#   v27:                 0x00010000         (..., 9.18355e-41, ...) -> 0x~~~~~~~~~~~~~~~~
+#   v28:                 0x00000000         (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  7ee2862c		sub d12, d17, d2
+#   v12: 0x0000000000000000ffdfffffffe003c0
+0x~~~~~~~~~~~~~~~~  6e288714		sub v20.16b, v24.16b, v8.16b
+#   v20: 0x00000000000000000000000000007ff9
+0x~~~~~~~~~~~~~~~~  6ee587a8		sub v8.2d, v29.2d, v5.2d
+#    v8: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2eb88782		sub v2.2s, v28.2s, v24.2s
+#    v2: 0x000000000000000000000000ffff8007
+0x~~~~~~~~~~~~~~~~  2e648558		sub v24.4h, v10.4h, v4.4h
+#   v24: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6eb1849c		sub v28.4s, v4.4s, v17.4s
+#   v28: 0x000000000000000000000000fffffc00
+0x~~~~~~~~~~~~~~~~  2e228770		sub v16.8b, v27.8b, v2.8b
+#   v16: 0x000000000000000000010000010280f9
+0x~~~~~~~~~~~~~~~~  6e6d8554		sub v20.8h, v10.8h, v13.8h
+#   v20: 0x0000000000000000000100010011001f
+0x~~~~~~~~~~~~~~~~  0ead61c5		subhn v5.2s, v14.2d, v13.2d
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e6860aa		subhn v10.4h, v5.4s, v8.4s
+#   v10: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e366146		subhn v6.8b, v10.8h, v22.8h
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e2960cb		subhn2 v11.16b, v6.8h, v9.8h
+#   v11: 0x00000000ff00ffff0000000000000000
+0x~~~~~~~~~~~~~~~~  4eb86259		subhn2 v25.4s, v18.2d, v24.2d
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e6162b4		subhn2 v20.8h, v21.4s, v1.4s
+#   v20: 0x000000000000ffff000100010011001f
+0x~~~~~~~~~~~~~~~~  5e203979		suqadd b25, b11
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5ee0382d		suqadd d13, d1
+#   v13: 0x0000000000000000ffffffffffefffe1
+0x~~~~~~~~~~~~~~~~  5e603920		suqadd h0, h9
+#    v0: 0x00000000000000000000000000000040
+0x~~~~~~~~~~~~~~~~  5ea03916		suqadd s22, s8
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e203b78		suqadd v24.16b, v27.16b
+#   v24: 0x000000000000007f0001000000010000
+0x~~~~~~~~~~~~~~~~  4ee039da		suqadd v26.2d, v14.2d
+#   v26: 0x00000000000000000000000000000001
+0x~~~~~~~~~~~~~~~~  0ea03947		suqadd v7.2s, v10.2s
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e603999		suqadd v25.4h, v12.4h
+#   v25: 0x00000000000000007fff7fff7fff03c0
+0x~~~~~~~~~~~~~~~~  4ea03864		suqadd v4.4s, v3.4s
+#    v4: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e203a4e		suqadd v14.8b, v18.8b
+#   v14: 0x00000000000000000000000000000001
+0x~~~~~~~~~~~~~~~~  4e60391f		suqadd v31.8h, v8.8h
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f20a690		sxtl v16.2d, v20.2s
+#   v16: 0x0000000000010001000000000011001f
+0x~~~~~~~~~~~~~~~~  0f10a79b		sxtl v27.4s, v28.4h
+#   v27: 0x0000000000000000fffffffffffffc00
+0x~~~~~~~~~~~~~~~~  0f08a6c0		sxtl v0.8h, v22.8b
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f20a4e6		sxtl2 v6.2d, v7.4s
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f10a769		sxtl2 v9.4s, v27.8h
+#    v9: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f08a610		sxtl2 v16.8h, v16.16b
+#   v16: 0x00000000000000000000000100000001
+0x~~~~~~~~~~~~~~~~  4e166239		tbl v25.16b, {v17.16b, v18.16b, v19.16b, v20.16b}, v22.16b
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e0441bc		tbl v28.16b, {v13.16b, v14.16b, v15.16b}, v4.16b
+#   v28: 0xe1e1e1e1e1e1e1e1e1e1e1e1e1e1e1e1
+0x~~~~~~~~~~~~~~~~  4e022003		tbl v3.16b, {v0.16b, v1.16b}, v2.16b
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e0401f4		tbl v20.16b, {v15.16b}, v4.16b
+#   v20: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e1462e7		tbl v7.8b, {v23.16b, v24.16b, v25.16b, v26.16b}, v20.8b
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e1f4028		tbl v8.8b, {v1.16b, v2.16b, v3.16b}, v31.8b
+#    v8: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e102328		tbl v8.8b, {v25.16b, v26.16b}, v16.8b
+#    v8: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e1e026b		tbl v11.8b, {v19.16b}, v30.8b
+#   v11: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e057339		tbx v25.16b, {v25.16b, v26.16b, v27.16b, v28.16b}, v5.16b
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e1853b5		tbx v21.16b, {v29.16b, v30.16b, v31.16b}, v24.16b
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e013206		tbx v6.16b, {v16.16b, v17.16b}, v1.16b
+#    v6: 0x01010101010101010101010101010101
+0x~~~~~~~~~~~~~~~~  4e14106d		tbx v13.16b, {v3.16b}, v20.16b
+#   v13: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e0973b8		tbx v24.8b, {v29.16b, v30.16b, v31.16b, v0.16b}, v9.8b
+#   v24: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e1a5131		tbx v17.8b, {v9.16b, v10.16b, v11.16b}, v26.8b
+#   v17: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e153065		tbx v5.8b, {v3.16b, v4.16b}, v21.8b
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e1d1170		tbx v16.8b, {v11.16b}, v29.8b
+#   v16: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e0c2b13		trn1 v19.16b, v24.16b, v12.16b
+#   v19: 0x0000000000000000df00ff00e000c000
+0x~~~~~~~~~~~~~~~~  4eca28e2		trn1 v2.2d, v7.2d, v10.2d
+#    v2: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e952816		trn1 v22.2s, v0.2s, v21.2s
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e5429ec		trn1 v12.4h, v15.4h, v20.4h
+#   v12: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e892a3e		trn1 v30.4s, v17.4s, v9.4s
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e1d2a6c		trn1 v12.8b, v19.8b, v29.8b
+#   v12: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e492917		trn1 v23.8h, v8.8h, v9.8h
+#   v23: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e196bdc		trn2 v28.16b, v30.16b, v25.16b
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ec76b67		trn2 v7.2d, v27.2d, v7.2d
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e936a1e		trn2 v30.2s, v16.2s, v19.2s
+#   v30: 0x0000000000000000df00ff0000000000
+0x~~~~~~~~~~~~~~~~  0e5968d8		trn2 v24.4h, v6.4h, v25.4h
+#   v24: 0x00000000000000000000010100000101
+0x~~~~~~~~~~~~~~~~  4e8b6a62		trn2 v2.4s, v19.4s, v11.4s
+#    v2: 0x000000000000000000000000df00ff00
+0x~~~~~~~~~~~~~~~~  0e126b79		trn2 v25.8b, v27.8b, v18.8b
+#   v25: 0x000000000000000000ff00ff00ff00fc
+0x~~~~~~~~~~~~~~~~  4e4f688c		trn2 v12.8h, v4.8h, v15.8h
+#   v12: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e3c7d9f		uaba v31.16b, v12.16b, v28.16b
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2eae7cb2		uaba v18.2s, v5.2s, v14.2s
+#   v18: 0x00000000000000000000000000000001
+0x~~~~~~~~~~~~~~~~  2e757e89		uaba v9.4h, v20.4h, v21.4h
+#    v9: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ea27e86		uaba v6.4s, v20.4s, v2.4s
+#    v6: 0x010101010101010101010101e0020001
+0x~~~~~~~~~~~~~~~~  2e257d90		uaba v16.8b, v12.8b, v5.8b
+#   v16: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e7e7f4f		uaba v15.8h, v26.8h, v30.8h
+#   v15: 0x0000000000000000df00ff0000000001
+0x~~~~~~~~~~~~~~~~  2eaf524a		uabal v10.2d, v18.2s, v15.2s
+#   v10: 0x00000000df00ff000000000000000000
+0x~~~~~~~~~~~~~~~~  2e67527e		uabal v30.4s, v19.4h, v7.4h
+#   v30: 0x0000df000000ff00df01df000000c000
+0x~~~~~~~~~~~~~~~~  2e205364		uabal v4.8h, v27.8b, v0.8b
+#    v4: 0x00ff00ff00ff00ff00ff00ff00fc0000
+0x~~~~~~~~~~~~~~~~  6ea25193		uabal2 v19.2d, v12.4s, v2.4s
+#   v19: 0x0000000000000000df00ff00e000c000
+0x~~~~~~~~~~~~~~~~  6e6c50ba		uabal2 v26.4s, v5.8h, v12.8h
+#   v26: 0x00000000000000000000000000000001
+0x~~~~~~~~~~~~~~~~  6e3c5293		uabal2 v19.8h, v20.16b, v28.16b
+#   v19: 0x0000000000000000df00ff00e000c000
+0x~~~~~~~~~~~~~~~~  6e357492		uabd v18.16b, v4.16b, v21.16b
+#   v18: 0x00ff00ff00ff00ff00ff00ff00fc0000
+0x~~~~~~~~~~~~~~~~  2eb076be		uabd v30.2s, v21.2s, v16.2s
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e797788		uabd v8.4h, v28.4h, v25.4h
+#    v8: 0x000000000000000000ff00ff00ff00fc
+0x~~~~~~~~~~~~~~~~  6eb5759c		uabd v28.4s, v12.4s, v21.4s
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e3c7613		uabd v19.8b, v16.8b, v28.8b
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e7d7589		uabd v9.8h, v12.8h, v29.8h
+#    v9: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2ea8701a		uabdl v26.2d, v0.2s, v8.2s
+#   v26: 0x0000000000ff00ff0000000000ff00fc
+0x~~~~~~~~~~~~~~~~  2e7973fd		uabdl v29.4s, v31.4h, v25.4h
+#   v29: 0x000000ff000000ff000000ff000000fc
+0x~~~~~~~~~~~~~~~~  2e2e73bb		uabdl v27.8h, v29.8b, v14.8b
+#   v27: 0x00000000000000ff00000000000000fb
+0x~~~~~~~~~~~~~~~~  6ea87294		uabdl2 v20.2d, v20.4s, v8.4s
+#   v20: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e7271f6		uabdl2 v22.4s, v15.8h, v18.8h
+#   v22: 0x000000ff000000ff000000ff000000ff
+0x~~~~~~~~~~~~~~~~  6e377249		uabdl2 v9.8h, v18.16b, v23.16b
+#    v9: 0x000000ff000000ff000000ff000000ff
+0x~~~~~~~~~~~~~~~~  2ea069e9		uadalp v9.1d, v15.2s
+#    v9: 0x0000000000000000000000ffdf010000
+0x~~~~~~~~~~~~~~~~  6ea0698e		uadalp v14.2d, v12.4s
+#   v14: 0x00000000000000000000000000000001
+0x~~~~~~~~~~~~~~~~  2e60699c		uadalp v28.2s, v12.4h
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e206a20		uadalp v0.4h, v17.8b
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e606ba1		uadalp v1.4s, v29.8h
+#    v1: 0x000000ff000000ff000000ff000000fc
+0x~~~~~~~~~~~~~~~~  6e206acf		uadalp v15.8h, v22.16b
+#   v15: 0x000000ff000000ffdf00ffff00000100
+0x~~~~~~~~~~~~~~~~  2ebb0281		uaddl v1.2d, v20.2s, v27.2s
+#    v1: 0x000000000000000000000000000000fb
+0x~~~~~~~~~~~~~~~~  2e65033f		uaddl v31.4s, v25.4h, v5.4h
+#   v31: 0x000000ff000000ff000000ff000000fc
+0x~~~~~~~~~~~~~~~~  2e23006c		uaddl v12.8h, v3.8b, v3.8b
+#   v12: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ea602e5		uaddl2 v5.2d, v23.4s, v6.4s
+#    v5: 0x00000000010101010000000001010101
+0x~~~~~~~~~~~~~~~~  6e7900a1		uaddl2 v1.4s, v5.8h, v25.8h
+#    v1: 0x00000000000000000000010100000101
+0x~~~~~~~~~~~~~~~~  6e3c03d6		uaddl2 v22.8h, v30.16b, v28.16b
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2ea02927		uaddlp v7.1d, v9.2s
+#    v7: 0x000000000000000000000000df0100ff
+0x~~~~~~~~~~~~~~~~  6ea0289a		uaddlp v26.2d, v4.4s
+#   v26: 0x0000000001fe01fe0000000001fb00ff
+0x~~~~~~~~~~~~~~~~  2e60283c		uaddlp v28.2s, v1.4h
+#   v28: 0x00000000000000000000010100000101
+0x~~~~~~~~~~~~~~~~  2e202bf4		uaddlp v20.4h, v31.8b
+#   v20: 0x0000000000000000000000ff000000fc
+0x~~~~~~~~~~~~~~~~  6e602a30		uaddlp v16.4s, v17.8h
+#   v16: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e202846		uaddlp v6.8h, v2.16b
+#    v6: 0x00000000000000000000000000df00ff
+0x~~~~~~~~~~~~~~~~  6eb03adc		uaddlv d28, v22.4s
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e303a60		uaddlv h0, v19.16b
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e303bde		uaddlv h30, v30.8b
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e703a58		uaddlv s24, v18.4h
+#   v24: 0x000000000000000000000000000002fa
+0x~~~~~~~~~~~~~~~~  6e70380a		uaddlv s10, v0.8h
+#   v10: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2eae1229		uaddw v9.2d, v17.2d, v14.2s
+#    v9: 0x00000000000000000000000000000001
+0x~~~~~~~~~~~~~~~~  2e631329		uaddw v9.4s, v25.4s, v3.4h
+#    v9: 0x000000000000000000ff00ff00ff00fc
+0x~~~~~~~~~~~~~~~~  2e201032		uaddw v18.8h, v1.8h, v0.8b
+#   v18: 0x00000000000000000000010100000101
+0x~~~~~~~~~~~~~~~~  6ea610b2		uaddw2 v18.2d, v5.2d, v6.4s
+#   v18: 0x00000000010101010000000001010101
+0x~~~~~~~~~~~~~~~~  6e6b11f1		uaddw2 v17.4s, v15.4s, v11.8h
+#   v17: 0x000000ff000000ffdf00ffff00000100
+0x~~~~~~~~~~~~~~~~  6e27117d		uaddw2 v29.8h, v11.8h, v7.16b
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e23052d		uhadd v13.16b, v9.16b, v3.16b
+#   v13: 0x0000000000000000007f007f007f007e
+0x~~~~~~~~~~~~~~~~  2eb80731		uhadd v17.2s, v25.2s, v24.2s
+#   v17: 0x0000000000000000007f807f007f81fb
+0x~~~~~~~~~~~~~~~~  2e6d06f9		uhadd v25.4h, v23.4h, v13.4h
+#   v25: 0x0000000000000000003f003f003f003f
+0x~~~~~~~~~~~~~~~~  6eb00680		uhadd v0.4s, v20.4s, v16.4s
+#    v0: 0x00000000000000000000007f0000007e
+0x~~~~~~~~~~~~~~~~  2e3904a5		uhadd v5.8b, v5.8b, v25.8b
+#    v5: 0x0000000000000000001f001f00200020
+0x~~~~~~~~~~~~~~~~  6e7207a3		uhadd v3.8h, v29.8h, v18.8h
+#    v3: 0x00000000008000800000000000800080
+0x~~~~~~~~~~~~~~~~  6e2d26c1		uhsub v1.16b, v22.16b, v13.16b
+#    v1: 0x000000000000000000c000c000c000c1
+0x~~~~~~~~~~~~~~~~  2ebe27ce		uhsub v14.2s, v30.2s, v30.2s
+#   v14: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e7125dd		uhsub v29.4h, v14.4h, v17.4h
+#   v29: 0x0000000000000000ffc0bfc0ffc0bf02
+0x~~~~~~~~~~~~~~~~  6eb224ba		uhsub v26.4s, v5.4s, v18.4s
+#   v26: 0x00000000ff7f7f7f000f800fff8f7f8f
+0x~~~~~~~~~~~~~~~~  2e2c24e3		uhsub v3.8b, v7.8b, v12.8b
+#    v3: 0x0000000000000000000000006f00007f
+0x~~~~~~~~~~~~~~~~  6e6526b9		uhsub v25.8h, v21.8h, v5.8h
+#   v25: 0x0000000000000000fff0fff0fff0fff0
+0x~~~~~~~~~~~~~~~~  6e26659c		umax v28.16b, v12.16b, v6.16b
+#   v28: 0x00000000000000000000000000df00ff
+0x~~~~~~~~~~~~~~~~  2eba6674		umax v20.2s, v19.2s, v26.2s
+#   v20: 0x0000000000000000000f800fff8f7f8f
+0x~~~~~~~~~~~~~~~~  2e7267e0		umax v0.4h, v31.4h, v18.4h
+#    v0: 0x0000000000000000000000ff01010101
+0x~~~~~~~~~~~~~~~~  6ebc66a6		umax v6.4s, v21.4s, v28.4s
+#    v6: 0x00000000000000000000000000df00ff
+0x~~~~~~~~~~~~~~~~  2e346440		umax v0.8b, v2.8b, v20.8b
+#    v0: 0x0000000000000000000f800fff8fff8f
+0x~~~~~~~~~~~~~~~~  6e766564		umax v4.8h, v11.8h, v22.8h
+#    v4: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e3da4c1		umaxp v1.16b, v6.16b, v29.16b
+#    v1: 0x00000000ffc0ffbf000000000000dfff
+0x~~~~~~~~~~~~~~~~  2ebba633		umaxp v19.2s, v17.2s, v27.2s
+#   v19: 0x0000000000000000000000fb007f81fb
+0x~~~~~~~~~~~~~~~~  2e67a615		umaxp v21.4h, v16.4h, v7.4h
+#   v21: 0x00000000000000000000df0100000000
+0x~~~~~~~~~~~~~~~~  6ebda689		umaxp v9.4s, v20.4s, v29.4s
+#    v9: 0x00000000ffc0bfc000000000ff8f7f8f
+0x~~~~~~~~~~~~~~~~  2e30a42d		umaxp v13.8b, v1.8b, v16.8b
+#   v13: 0x000000000000000000000000000000ff
+0x~~~~~~~~~~~~~~~~  6e7aa6f3		umaxp v19.8h, v23.8h, v26.8h
+#   v19: 0x0000ff7f800fff8f0000000000000000
+0x~~~~~~~~~~~~~~~~  6e30abd1		umaxv b17, v30.16b
+#   v17: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e30a997		umaxv b23, v12.8b
+#   v23: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e70a9ff		umaxv h31, v15.4h
+#   v31: 0x0000000000000000000000000000ffff
+0x~~~~~~~~~~~~~~~~  6e70ab2f		umaxv h15, v25.8h
+#   v15: 0x0000000000000000000000000000fff0
+0x~~~~~~~~~~~~~~~~  6eb0aab2		umaxv s18, v21.4s
+#   v18: 0x0000000000000000000000000000df01
+0x~~~~~~~~~~~~~~~~  6e326c16		umin v22.16b, v0.16b, v18.16b
+#   v22: 0x0000000000000000000000000000df01
+0x~~~~~~~~~~~~~~~~  2eb06ea1		umin v1.2s, v21.2s, v16.2s
+#    v1: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e796c91		umin v17.4h, v4.4h, v25.4h
+#   v17: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ead6f58		umin v24.4s, v26.4s, v13.4s
+#   v24: 0x000000000000000000000000000000ff
+0x~~~~~~~~~~~~~~~~  2e256c34		umin v20.8b, v1.8b, v5.8b
+#   v20: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e776f3a		umin v26.8h, v25.8h, v23.8h
+#   v26: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e37ac25		uminp v5.16b, v1.16b, v23.16b
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2ebeaf47		uminp v7.2s, v26.2s, v30.2s
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e79aca9		uminp v9.4h, v5.4h, v25.4h
+#    v9: 0x0000000000000000fff0fff000000000
+0x~~~~~~~~~~~~~~~~  6ea1ad57		uminp v23.4s, v10.4s, v1.4s
+#   v23: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e2eafa4		uminp v4.8b, v29.8b, v14.8b
+#    v4: 0x000000000000000000000000c0bfc002
+0x~~~~~~~~~~~~~~~~  6e6eac15		uminp v21.8h, v0.8h, v14.8h
+#   v21: 0x000000000000000000000000000fff8f
+0x~~~~~~~~~~~~~~~~  6e31aa20		uminv b0, v17.16b
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e31abe0		uminv b0, v31.8b
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e71a818		uminv h24, v0.4h
+#   v24: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e71a9dd		uminv h29, v14.8h
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6eb1a87e		uminv s30, v3.4s
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2eb8816b		umlal v11.2d, v11.2s, v24.2s
+#   v11: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2fab2a1e		umlal v30.2d, v16.2s, v11.s[3]
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e7a8120		umlal v0.4s, v9.4h, v26.4h
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f4c2b14		umlal v20.4s, v24.4h, v12.h[4]
+#   v20: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e2682b0		umlal v16.8h, v21.8b, v6.8b
+#   v16: 0x000000000000000000000d1100008e71
+0x~~~~~~~~~~~~~~~~  6eb78271		umlal2 v17.2d, v19.4s, v23.4s
+#   v17: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f8823c5		umlal2 v5.2d, v30.4s, v8.s[0]
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e6f8110		umlal2 v16.4s, v8.8h, v15.8h
+#   v16: 0x000000000000000000000d1100008e71
+0x~~~~~~~~~~~~~~~~  6f512b4f		umlal2 v15.4s, v26.8h, v1.h[5]
+#   v15: 0x0000000000000000000000000000fff0
+0x~~~~~~~~~~~~~~~~  6e31803e		umlal2 v30.8h, v1.16b, v17.16b
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2ebca272		umlsl v18.2d, v19.2s, v28.2s
+#   v18: 0x0000000000000000000000000000df01
+0x~~~~~~~~~~~~~~~~  2f8860e7		umlsl v7.2d, v7.2s, v8.s[0]
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e64a118		umlsl v24.4s, v8.4h, v4.4h
+#   v24: 0x0000000000000000ff4001bfff42fe08
+0x~~~~~~~~~~~~~~~~  2f4c6ad2		umlsl v18.4s, v22.4h, v12.h[4]
+#   v18: 0x0000000000000000000000000000df01
+0x~~~~~~~~~~~~~~~~  2e34a1dc		umlsl v28.8h, v14.8b, v20.8b
+#   v28: 0x00000000000000000000000000df00ff
+0x~~~~~~~~~~~~~~~~  6ea9a00b		umlsl2 v11.2d, v0.4s, v9.4s
+#   v11: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f896a1a		umlsl2 v26.2d, v16.4s, v9.s[2]
+#   v26: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e69a163		umlsl2 v3.4s, v11.8h, v9.8h
+#    v3: 0x0000000000000000000000006f00007f
+0x~~~~~~~~~~~~~~~~  6f496b2a		umlsl2 v10.4s, v25.8h, v9.h[4]
+#   v10: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e3ca218		umlsl2 v24.8h, v16.16b, v28.16b
+#   v24: 0x0000000000000000ff4001bfff42fe08
+0x~~~~~~~~~~~~~~~~  4e183f3e		mov x30, v25.d[1]
+#    lr: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  2ebdc14c		umull v12.2d, v10.2s, v29.2s
+#   v12: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2fa5abd6		umull v22.2d, v30.2s, v5.s[3]
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e79c007		umull v7.4s, v0.4h, v25.4h
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f63a1ab		umull v11.4s, v13.4h, v3.h[2]
+#   v11: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e2ac219		umull v25.8h, v16.8b, v10.8b
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ebac071		umull2 v17.2d, v3.4s, v26.4s
+#   v17: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6fa2a97a		umull2 v26.2d, v11.4s, v2.s[3]
+#   v26: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e77c22c		umull2 v12.4s, v17.8h, v23.8h
+#   v12: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f61a3e4		umull2 v4.4s, v31.8h, v1.h[2]
+#    v4: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e31c185		umull2 v5.8h, v12.16b, v17.16b
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7e3c0c9e		uqadd b30, b4, b28
+#   v30: 0x000000000000000000000000000000ff
+0x~~~~~~~~~~~~~~~~  7ef00e9b		uqadd d27, d20, d16
+#   v27: 0x000000000000000000000d1100008e71
+0x~~~~~~~~~~~~~~~~  7e7c0dc7		uqadd h7, h14, h28
+#    v7: 0x000000000000000000000000000000ff
+0x~~~~~~~~~~~~~~~~  7ea40e3c		uqadd s28, s17, s4
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e350ed3		uqadd v19.16b, v22.16b, v21.16b
+#   v19: 0x000000000000000000000000000fff8f
+0x~~~~~~~~~~~~~~~~  6eeb0c90		uqadd v16.2d, v4.2d, v11.2d
+#   v16: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2ea40dd4		uqadd v20.2s, v14.2s, v4.2s
+#   v20: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e700c05		uqadd v5.4h, v0.4h, v16.4h
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ea90ff5		uqadd v21.4s, v31.4s, v9.4s
+#   v21: 0x0000000000000000fff0fff00000ffff
+0x~~~~~~~~~~~~~~~~  2e230f17		uqadd v23.8b, v24.8b, v3.8b
+#   v23: 0x0000000000000000ff4001bfff42fe87
+0x~~~~~~~~~~~~~~~~  6e6b0f71		uqadd v17.8h, v27.8h, v11.8h
+#   v17: 0x000000000000000000000d1100008e71
+0x~~~~~~~~~~~~~~~~  7e2a5eca		uqrshl b10, b22, b10
+#   v10: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7eeb5cbd		uqrshl d29, d5, d11
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7e7e5f1b		uqrshl h27, h24, h30
+#   v27: 0x00000000000000000000000000007f04
+0x~~~~~~~~~~~~~~~~  7ea85daa		uqrshl s10, s13, s8
+#   v10: 0x00000000000000000000000000000010
+0x~~~~~~~~~~~~~~~~  6e2e5e49		uqrshl v9.16b, v18.16b, v14.16b
+#    v9: 0x0000000000000000000000000000df01
+0x~~~~~~~~~~~~~~~~  6ef15df8		uqrshl v24.2d, v15.2d, v17.2d
+#   v24: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  2ebb5dc4		uqrshl v4.2s, v14.2s, v27.2s
+#    v4: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e685caf		uqrshl v15.4h, v5.4h, v8.4h
+#   v15: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ea05fb5		uqrshl v21.4s, v29.4s, v0.4s
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e295f10		uqrshl v16.8b, v24.8b, v9.8b
+#   v16: 0x0000000000000000ffffffffffff00ff
+0x~~~~~~~~~~~~~~~~  6e6f5c02		uqrshl v2.8h, v0.8h, v15.8h
+#    v2: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7f0c9f4b		uqrshrn b11, h26, #4
+#   v11: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7f1b9fc7		uqrshrn h7, s30, #5
+#    v7: 0x00000000000000000000000000000008
+0x~~~~~~~~~~~~~~~~  7f2b9d0a		uqrshrn s10, d8, #21
+#   v10: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  2f359ccf		uqrshrn v15.2s, v6.2d, #11
+#   v15: 0x00000000000000000000000000001be0
+0x~~~~~~~~~~~~~~~~  2f149f45		uqrshrn v5.4h, v26.4s, #12
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f0b9f3c		uqrshrn v28.8b, v25.8h, #5
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f0e9fd9		uqrshrn2 v25.16b, v30.8h, #2
+#   v25: 0x00000000000000400000000000000000
+0x~~~~~~~~~~~~~~~~  6f209dd5		uqrshrn2 v21.4s, v14.2d, #32
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f1e9ced		uqrshrn2 v13.8h, v7.4s, #2
+#   v13: 0x000000000000000200000000000000ff
+0x~~~~~~~~~~~~~~~~  7e374c0d		uqshl b13, b0, b23
+#   v13: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7f0c7629		uqshl b9, b17, #4
+#    v9: 0x000000000000000000000000000000ff
+0x~~~~~~~~~~~~~~~~  7ee44cd7		uqshl d23, d6, d4
+#   v23: 0x00000000000000000000000000df00ff
+0x~~~~~~~~~~~~~~~~  7f6c7568		uqshl d8, d11, #44
+#    v8: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7e6f4db3		uqshl h19, h13, h15
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7f167759		uqshl h25, h26, #6
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7eaa4f04		uqshl s4, s24, s10
+#    v4: 0x0000000000000000000000007fffffff
+0x~~~~~~~~~~~~~~~~  7f2175d3		uqshl s19, s14, #1
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e394fce		uqshl v14.16b, v30.16b, v25.16b
+#   v14: 0x000000000000000000000000000000ff
+0x~~~~~~~~~~~~~~~~  6f0d7546		uqshl v6.16b, v10.16b, #5
+#    v6: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  6ee74d12		uqshl v18.2d, v8.2d, v7.2d
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f5275d9		uqshl v25.2d, v14.2d, #18
+#   v25: 0x00000000000000000000000003fc0000
+0x~~~~~~~~~~~~~~~~  2eb74e19		uqshl v25.2s, v16.2s, v23.2s
+#   v25: 0x0000000000000000ffffffff7fff807f
+0x~~~~~~~~~~~~~~~~  2f3f75ed		uqshl v13.2s, v15.2s, #31
+#   v13: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  2e6f4f1c		uqshl v28.4h, v24.4h, v15.4h
+#   v28: 0x0000000000000000ffffffffffff0000
+0x~~~~~~~~~~~~~~~~  2f117624		uqshl v4.4h, v17.4h, #1
+#    v4: 0x000000000000000000001a220000ffff
+0x~~~~~~~~~~~~~~~~  6eb74fe9		uqshl v9.4s, v31.4s, v23.4s
+#    v9: 0x00000000000000000000000000007fff
+0x~~~~~~~~~~~~~~~~  6f3f7792		uqshl v18.4s, v28.4s, #31
+#   v18: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  2e2f4ebf		uqshl v31.8b, v21.8b, v15.8b
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f0976a6		uqshl v6.8b, v21.8b, #1
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e714c5c		uqshl v28.8h, v2.8h, v17.8h
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f1e7518		uqshl v24.8h, v8.8h, #14
+#   v24: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7f099775		uqshrn b21, h27, #7
+#   v21: 0x000000000000000000000000000000fe
+0x~~~~~~~~~~~~~~~~  7f15975c		uqshrn h28, s26, #11
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7f2f97ed		uqshrn s13, d31, #17
+#   v13: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f389615		uqshrn v21.2s, v16.2d, #8
+#   v21: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  2f1e9718		uqshrn v24.4h, v24.4s, #2
+#   v24: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f089425		uqshrn v5.8b, v1.8h, #8
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f0a97b0		uqshrn2 v16.16b, v29.8h, #6
+#   v16: 0x0000000000000000ffffffffffff00ff
+0x~~~~~~~~~~~~~~~~  6f3f94c2		uqshrn2 v2.4s, v6.2d, #1
+#    v2: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f129550		uqshrn2 v16.8h, v10.4s, #14
+#   v16: 0x000000000000ffffffffffffffff00ff
+0x~~~~~~~~~~~~~~~~  7e3a2e9c		uqsub b28, b20, b26
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7eea2ce0		uqsub d0, d7, d10
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7e672f1a		uqsub h26, h24, h7
+#   v26: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7eb02ef7		uqsub s23, s23, s16
+#   v23: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e382e0e		uqsub v14.16b, v16.16b, v24.16b
+#   v14: 0x000000000000ffffffffffffffff00ff
+0x~~~~~~~~~~~~~~~~  6ee62e2b		uqsub v11.2d, v17.2d, v6.2d
+#   v11: 0x000000000000000000000d1100008e71
+0x~~~~~~~~~~~~~~~~  2ea82d4a		uqsub v10.2s, v10.2s, v8.2s
+#   v10: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  2e6c2de9		uqsub v9.4h, v15.4h, v12.4h
+#    v9: 0x00000000000000000000000000001be0
+0x~~~~~~~~~~~~~~~~  6ea72e57		uqsub v23.4s, v18.4s, v7.4s
+#   v23: 0x0000000000000000fffffffffffffff7
+0x~~~~~~~~~~~~~~~~  2e312e69		uqsub v9.8b, v19.8b, v17.8b
+#    v9: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e662c54		uqsub v20.8h, v2.8h, v6.8h
+#   v20: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7e214a7d		uqxtn b29, h19
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7e6149a0		uqxtn h0, s13
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7ea14ada		uqxtn s26, d22
+#   v26: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2ea14be5		uqxtn v5.2s, v31.2d
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e614a7e		uqxtn v30.4h, v19.4s
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e21484f		uqxtn v15.8b, v2.8h
+#   v15: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e21487d		uqxtn2 v29.16b, v3.8h
+#   v29: 0x000000000000ff7f0000000000000000
+0x~~~~~~~~~~~~~~~~  6ea14a2d		uqxtn2 v13.4s, v17.2d
+#   v13: 0x00000000ffffffff0000000000000000
+0x~~~~~~~~~~~~~~~~  6e61497c		uqxtn2 v28.8h, v11.4s
+#   v28: 0x000000000d118e710000000000000000
+0x~~~~~~~~~~~~~~~~  0ea1c9f7		urecpe v23.2s, v15.2s
+#   v23: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4ea1c8fb		urecpe v27.4s, v7.4s
+#   v27: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  6e3b15e2		urhadd v2.16b, v15.16b, v27.16b
+#    v2: 0x80808080808080808080808080808080
+0x~~~~~~~~~~~~~~~~  2eb2142f		urhadd v15.2s, v1.2s, v18.2s
+#   v15: 0x00000000000000008000000080000000
+0x~~~~~~~~~~~~~~~~  2e7a1491		urhadd v17.4h, v4.4h, v26.4h
+#   v17: 0x000000000000000000000d1100008000
+0x~~~~~~~~~~~~~~~~  6eae1762		urhadd v2.4s, v27.4s, v14.4s
+#    v2: 0x8000000080007fffffffffffffff807f
+0x~~~~~~~~~~~~~~~~  2e2e1625		urhadd v5.8b, v17.8b, v14.8b
+#    v5: 0x00000000000000008080868880804080
+0x~~~~~~~~~~~~~~~~  6e79145e		urhadd v30.8h, v2.8h, v25.8h
+#   v30: 0x4000000040004000ffffffffbfff807f
+0x~~~~~~~~~~~~~~~~  7efe5784		urshl d4, d28, d30
+#    v4: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e3357ed		urshl v13.16b, v31.16b, v19.16b
+#   v13: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ef556ee		urshl v14.2d, v23.2d, v21.2d
+#   v14: 0x00000000000000008000000000000000
+0x~~~~~~~~~~~~~~~~  2ea854ea		urshl v10.2s, v7.2s, v8.2s
+#   v10: 0x00000000000000000000000000000008
+0x~~~~~~~~~~~~~~~~  2e7c56af		urshl v15.4h, v21.4h, v28.4h
+#   v15: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  6eb7551e		urshl v30.4s, v8.4s, v23.4s
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e25569f		urshl v31.8b, v20.8b, v5.8b
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e7e577e		urshl v30.8h, v27.8h, v30.8h
+#   v30: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  7f4f25a4		urshr d4, d13, #49
+#    v4: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f0f2682		urshr v2.16b, v20.16b, #1
+#    v2: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f4d256d		urshr v13.2d, v11.2d, #51
+#   v13: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f3627f5		urshr v21.2s, v31.2s, #10
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f152635		urshr v21.4h, v17.4h, #11
+#   v21: 0x00000000000000000000000200000010
+0x~~~~~~~~~~~~~~~~  6f3f26c4		urshr v4.4s, v22.4s, #1
+#    v4: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f092420		urshr v0.8b, v1.8b, #7
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f1f268d		urshr v13.8h, v20.8h, #1
+#   v13: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2ea1ca14		ursqrte v20.2s, v16.2s
+#   v20: 0x00000000000000008000000080000000
+0x~~~~~~~~~~~~~~~~  6ea1c91c		ursqrte v28.4s, v8.4s
+#   v28: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  7f53361b		ursra d27, d16, #45
+#   v27: 0x0000000000000000000000000007ffff
+0x~~~~~~~~~~~~~~~~  6f0d3632		ursra v18.16b, v17.16b, #3
+#   v18: 0x0000000000000000ffff0101ffff0fff
+0x~~~~~~~~~~~~~~~~  6f46379a		ursra v26.2d, v28.2d, #58
+#   v26: 0x00000000000000400000000000000040
+0x~~~~~~~~~~~~~~~~  2f2136c8		ursra v8.2s, v22.2s, #31
+#    v8: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f19349f		ursra v31.4h, v4.4h, #7
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f3e35ff		ursra v31.4s, v15.4s, #2
+#   v31: 0x00000000000000000000000040000000
+0x~~~~~~~~~~~~~~~~  2f0b3423		ursra v3.8b, v1.8b, #5
+#    v3: 0x0000000000000000000000006f00007f
+0x~~~~~~~~~~~~~~~~  6f1335d2		ursra v18.8h, v14.8h, #13
+#   v18: 0x000000000000000000030101ffff0fff
+0x~~~~~~~~~~~~~~~~  7ef0441f		ushl d31, d0, d16
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e2244c0		ushl v0.16b, v6.16b, v2.16b
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ef24432		ushl v18.2d, v1.2d, v18.2d
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2ebd44fb		ushl v27.2s, v7.2s, v29.2s
+#   v27: 0x00000000000000000000000000000008
+0x~~~~~~~~~~~~~~~~  2e6d45ce		ushl v14.4h, v14.4h, v13.4h
+#   v14: 0x00000000000000008000000000000000
+0x~~~~~~~~~~~~~~~~  6ea94496		ushl v22.4s, v4.4s, v9.4s
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e3b46d7		ushl v23.8b, v22.8b, v27.8b
+#   v23: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e684735		ushl v21.8h, v25.8h, v8.8h
+#   v21: 0x0000000000000000ffffffff7fff807f
+0x~~~~~~~~~~~~~~~~  2f35a40b		ushll v11.2d, v0.2s, #21
+#   v11: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f18a622		ushll v2.4s, v17.4h, #8
+#    v2: 0x00000000000d11000000000000800000
+0x~~~~~~~~~~~~~~~~  2f09a5cb		ushll v11.8h, v14.8b, #1
+#   v11: 0x01000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f27a7a8		ushll2 v8.2d, v29.4s, #7
+#    v8: 0x000000000000000000000000007fbf80
+0x~~~~~~~~~~~~~~~~  6f12a53d		ushll2 v29.4s, v9.8h, #2
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f0ea705		ushll2 v5.8h, v24.16b, #6
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7f4b077c		ushr d28, d27, #53
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f090521		ushr v1.16b, v9.16b, #7
+#    v1: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f550702		ushr v2.2d, v24.2d, #43
+#    v2: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f35073e		ushr v30.2s, v25.2s, #11
+#   v30: 0x0000000000000000001fffff000ffff0
+0x~~~~~~~~~~~~~~~~  2f14074a		ushr v10.4h, v26.4h, #12
+#   v10: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f2204a4		ushr v4.4s, v5.4s, #30
+#    v4: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f0f045e		ushr v30.8b, v2.8b, #1
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f1e0586		ushr v6.8h, v12.8h, #2
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7e2038b3		usqadd b19, b5
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7ee03849		usqadd d9, d2
+#    v9: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7e603a02		usqadd h2, h16
+#    v2: 0x000000000000000000000000000000ff
+0x~~~~~~~~~~~~~~~~  7ea03870		usqadd s16, s3
+#   v16: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  6e203bbf		usqadd v31.16b, v29.16b
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ee03948		usqadd v8.2d, v10.2d
+#    v8: 0x000000000000000000000000007fbf80
+0x~~~~~~~~~~~~~~~~  2ea03932		usqadd v18.2s, v9.2s
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e6039d8		usqadd v24.4h, v14.4h
+#   v24: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ea03bca		usqadd v10.4s, v30.4s
+#   v10: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e203a90		usqadd v16.8b, v20.8b
+#   v16: 0x0000000000000000000000007fffffff
+0x~~~~~~~~~~~~~~~~  6e603a0c		usqadd v12.8h, v16.8h
+#   v12: 0x0000000000000000000000007fff0000
+0x~~~~~~~~~~~~~~~~  7f5b177c		usra d28, d27, #37
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f0b16c5		usra v5.16b, v22.16b, #5
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f5f1662		usra v2.2d, v19.2d, #33
+#    v2: 0x000000000000000000000000000000ff
+0x~~~~~~~~~~~~~~~~  2f2b1400		usra v0.2s, v0.2s, #21
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f1414c7		usra v7.4h, v6.4h, #12
+#    v7: 0x00000000000000000000000000000008
+0x~~~~~~~~~~~~~~~~  6f371624		usra v4.4s, v17.4s, #9
+#    v4: 0x00000000000000000000000600000040
+0x~~~~~~~~~~~~~~~~  2f091589		usra v9.8b, v12.8b, #7
+#    v9: 0x00000000000000000000000000010000
+0x~~~~~~~~~~~~~~~~  6f121763		usra v3.8h, v27.8h, #14
+#    v3: 0x0000000000000000000000006f00007f
+0x~~~~~~~~~~~~~~~~  2ebe219d		usubl v29.2d, v12.2s, v30.2s
+#   v29: 0x0000000000000000000000007fff0000
+0x~~~~~~~~~~~~~~~~  2e66239d		usubl v29.4s, v28.4h, v6.4h
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e2e208c		usubl v12.8h, v4.8b, v14.8b
+#   v12: 0xff800000000000060000000000000040
+0x~~~~~~~~~~~~~~~~  6eb12301		usubl2 v1.2d, v24.4s, v17.4s
+#    v1: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e632024		usubl2 v4.4s, v1.8h, v3.8h
+#    v4: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e272097		usubl2 v23.8h, v4.16b, v7.16b
+#   v23: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2ebe3289		usubw v9.2d, v20.2d, v30.2s
+#    v9: 0x00000000000000008000000080000000
+0x~~~~~~~~~~~~~~~~  2e773214		usubw v20.4s, v16.4s, v23.4h
+#   v20: 0x0000000000000000000000007fffffff
+0x~~~~~~~~~~~~~~~~  2e3d3119		usubw v25.8h, v8.8h, v29.8b
+#   v25: 0x000000000000000000000000007fbf80
+0x~~~~~~~~~~~~~~~~  6ea633b2		usubw2 v18.2d, v29.2d, v6.4s
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e7430c6		usubw2 v6.4s, v6.4s, v20.8h
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e303092		usubw2 v18.8h, v4.8h, v16.16b
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f20a6bb		uxtl v27.2d, v21.2s
+#   v27: 0x00000000ffffffff000000007fff807f
+0x~~~~~~~~~~~~~~~~  2f10a7e0		uxtl v0.4s, v31.4h
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f08a55b		uxtl v27.8h, v10.8b
+#   v27: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f20a606		uxtl2 v6.2d, v16.4s
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f10a696		uxtl2 v22.4s, v20.8h
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f08a6b4		uxtl2 v20.8h, v21.16b
+#   v20: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e11193e		uzp1 v30.16b, v9.16b, v17.16b
+#   v30: 0x00000000001100000000000000000000
+0x~~~~~~~~~~~~~~~~  4edc1b47		uzp1 v7.2d, v26.2d, v28.2d
+#    v7: 0x00000000000000000000000000000040
+0x~~~~~~~~~~~~~~~~  0e961a1a		uzp1 v26.2s, v16.2s, v22.2s
+#   v26: 0x0000000000000000000000007fffffff
+0x~~~~~~~~~~~~~~~~  0e461a6e		uzp1 v14.4h, v19.4h, v6.4h
+#   v14: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e9e1af1		uzp1 v17.4s, v23.4s, v30.4s
+#   v17: 0x00110000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e0d1b7c		uzp1 v28.8b, v27.8b, v13.8b
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e4c1831		uzp1 v17.8h, v1.8h, v12.8h
+#   v17: 0x00000006000000400000000000000000
+0x~~~~~~~~~~~~~~~~  4e1a5a48		uzp2 v8.16b, v18.16b, v26.16b
+#    v8: 0x0000000000007fff0000000000000000
+0x~~~~~~~~~~~~~~~~  4ed85ad5		uzp2 v21.2d, v22.2d, v24.2d
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e825ab4		uzp2 v20.2s, v21.2s, v2.2s
+#   v20: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e465bf0		uzp2 v16.4h, v31.4h, v6.4h
+#   v16: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e885979		uzp2 v25.4s, v11.4s, v8.4s
+#   v25: 0x00000000000000000100000000000000
+0x~~~~~~~~~~~~~~~~  0e0d5bff		uzp2 v31.8b, v31.8b, v13.8b
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e415a28		uzp2 v8.8h, v17.8h, v1.8h
+#    v8: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ea12b51		xtn v17.2s, v26.2d
+#   v17: 0x0000000000000000000000007fffffff
+0x~~~~~~~~~~~~~~~~  0e612803		xtn v3.4h, v0.4s
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e212912		xtn v18.8b, v8.8h
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e212800		xtn2 v0.16b, v0.8h
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ea1288f		xtn2 v15.4s, v4.2d
+#   v15: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  4e612a5f		xtn2 v31.8h, v18.4s
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e063936		zip1 v22.16b, v9.16b, v6.16b
+#   v22: 0x00800000000000000080000000000000
+0x~~~~~~~~~~~~~~~~  4ec23977		zip1 v23.2d, v11.2d, v2.2d
+#   v23: 0x00000000000000ff0000000000000000
+0x~~~~~~~~~~~~~~~~  0e893a1a		zip1 v26.2s, v16.2s, v9.2s
+#   v26: 0x00000000000000008000000000000000
+0x~~~~~~~~~~~~~~~~  0e473921		zip1 v1.4h, v9.4h, v7.4h
+#    v1: 0x00000000000000000000800000400000
+0x~~~~~~~~~~~~~~~~  4e943bc0		zip1 v0.4s, v30.4s, v20.4s
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e0f3a3e		zip1 v30.8b, v17.8b, v15.8b
+#   v30: 0x0000000000000000ff7fffffffffffff
+0x~~~~~~~~~~~~~~~~  4e423911		zip1 v17.8h, v8.8h, v2.8h
+#   v17: 0x00000000000000000000000000ff0000
+0x~~~~~~~~~~~~~~~~  4e0b7957		zip2 v23.16b, v10.16b, v11.16b
+#   v23: 0x01000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ece78de		zip2 v30.2d, v6.2d, v14.2d
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e957949		zip2 v9.2s, v10.2s, v21.2s
+#    v9: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e5d7b08		zip2 v8.4h, v24.4h, v29.4h
+#    v8: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e977aa0		zip2 v0.4s, v21.4s, v23.4s
+#    v0: 0x01000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e1e7af9		zip2 v25.8b, v23.8b, v30.8b
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e5e7947		zip2 v7.8h, v10.8h, v30.8h
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ee8d723		fabd v3.2d, v25.2d, v8.2d
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2eabd76e		fabd v14.2s, v27.2s, v11.2s
+#   v14: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6eb2d6c9		fabd v9.4s, v22.4s, v18.4s
+#    v9: 0x00800000000000000080000000000000
+0x~~~~~~~~~~~~~~~~  4ee0fba1		fabs v1.2d, v29.2d
+#    v1: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ea0faa6		fabs v6.2s, v21.2s
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ea0fb2c		fabs v12.4s, v25.4s
+#   v12: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e60ecb2		facge v18.2d, v5.2d, v0.2d
+#   v18: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  2e26ed6f		facge v15.2s, v11.2s, v6.2s
+#   v15: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  6e39ed5e		facge v30.4s, v10.4s, v25.4s
+#   v30: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  6effee1c		facgt v28.2d, v16.2d, v31.2d
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2ea4ec2f		facgt v15.2s, v1.2s, v4.2s
+#   v15: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6eaaec76		facgt v22.4s, v3.4s, v10.4s
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e78d547		fadd v7.2d, v10.2d, v24.2d
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e27d6ea		fadd v10.2s, v23.2s, v7.2s
+#   v10: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e2bd6d0		fadd v16.4s, v22.4s, v11.4s
+#   v16: 0x01000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7e70db9b		faddp d27, v28.2d
+#   v27: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7e30daf4		faddp s20, v23.2s
+#   v20: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e6bd495		faddp v21.2d, v4.2d, v11.2d
+#   v21: 0x01000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e21d75f		faddp v31.2s, v26.2s, v1.2s
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e3cd76d		faddp v13.4s, v27.4s, v28.4s
+#   v13: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e74e5b1		fcmeq v17.2d, v13.2d, v20.2d
+#   v17: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4ee0da18		fcmeq v24.2d, v16.2d, #0.0
+#   v24: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  0e2ae63a		fcmeq v26.2s, v17.2s, v10.2s
+#   v26: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ea0d898		fcmeq v24.2s, v4.2s, #0.0
+#   v24: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4e2ee488		fcmeq v8.4s, v4.4s, v14.4s
+#    v8: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4ea0db3a		fcmeq v26.4s, v25.4s, #0.0
+#   v26: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  6e60e41b		fcmge v27.2d, v0.2d, v0.2d
+#   v27: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  6ee0cbd6		fcmge v22.2d, v30.2d, #0.0
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e39e6a7		fcmge v7.2s, v21.2s, v25.2s
+#    v7: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  2ea0c9ef		fcmge v15.2s, v15.2s, #0.0
+#   v15: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  6e3be49d		fcmge v29.4s, v4.4s, v27.4s
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ea0cab6		fcmge v22.4s, v21.4s, #0.0
+#   v22: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  6eefe741		fcmgt v1.2d, v26.2d, v15.2d
+#    v1: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ee0caef		fcmgt v15.2d, v23.2d, #0.0
+#   v15: 0xffffffffffffffff0000000000000000
+0x~~~~~~~~~~~~~~~~  2ea6e615		fcmgt v21.2s, v16.2s, v6.2s
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ea0c9a1		fcmgt v1.2s, v13.2s, #0.0
+#    v1: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6eb9e40e		fcmgt v14.4s, v0.4s, v25.4s
+#   v14: 0xffffffff000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ea0c90d		fcmgt v13.4s, v8.4s, #0.0
+#   v13: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ee0d8c4		fcmle v4.2d, v6.2d, #0.0
+#    v4: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  2ea0dbf8		fcmle v24.2s, v31.2s, #0.0
+#   v24: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  6ea0dae8		fcmle v8.4s, v23.4s, #0.0
+#    v8: 0x00000000ffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4ee0e867		fcmlt v7.2d, v3.2d, #0.0
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ea0eaaf		fcmlt v15.2s, v21.2s, #0.0
+#   v15: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ea0e841		fcmlt v1.4s, v2.4s, #0.0
+#    v1: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e61c906		fcvtas v6.2d, v8.2d
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e21c921		fcvtas v1.2s, v9.2s
+#    v1: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e21ca68		fcvtas v8.4s, v19.4s
+#    v8: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e61cbe5		fcvtau v5.2d, v31.2d
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e21cbbc		fcvtau v28.2s, v29.2s
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e21cb4b		fcvtau v11.4s, v26.4s
+#   v11: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e617b28		fcvtl v8.2d, v25.2s
+#    v8: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e2179db		fcvtl v27.4s, v14.4h
+#   v27: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e6178c1		fcvtl2 v1.2d, v6.4s
+#    v1: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e217938		fcvtl2 v24.4s, v9.8h
+#   v24: 0x37000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e61bb09		fcvtms v9.2d, v24.2d
+#    v9: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e21b967		fcvtms v7.2s, v11.2s
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e21bab7		fcvtms v23.4s, v21.4s
+#   v23: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e61b82d		fcvtmu v13.2d, v1.2d
+#   v13: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e21b99a		fcvtmu v26.2s, v12.2s
+#   v26: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e21bab5		fcvtmu v21.4s, v21.4s
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e61682b		fcvtn v11.2s, v1.2d
+#   v11: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e216848		fcvtn v8.4h, v2.4s
+#    v8: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e616bb8		fcvtn2 v24.4s, v29.2d
+#   v24: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e216944		fcvtn2 v4.8h, v10.4s
+#    v4: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4e61a959		fcvtns v25.2d, v10.2d
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e21a904		fcvtns v4.2s, v8.2s
+#    v4: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e21ab7d		fcvtns v29.4s, v27.4s
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e61ab72		fcvtnu v18.2d, v27.2d
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e21a9cb		fcvtnu v11.2s, v14.2s
+#   v11: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e21aabb		fcvtnu v27.4s, v21.4s
+#   v27: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ee1a8b7		fcvtps v23.2d, v5.2d
+#   v23: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ea1a9f8		fcvtps v24.2s, v15.2s
+#   v24: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ea1aa65		fcvtps v5.4s, v19.4s
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ee1aaa3		fcvtpu v3.2d, v21.2d
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2ea1aaa3		fcvtpu v3.2s, v21.2s
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ea1a8e0		fcvtpu v0.4s, v7.4s
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e61697d		fcvtxn v29.2s, v11.2d
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e616b3f		fcvtxn2 v31.4s, v25.2d
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ee1ba33		fcvtzs v19.2d, v17.2d
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f40ff0c		fcvtzs v12.2d, v24.2d, #64
+#   v12: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ea1b849		fcvtzs v9.2s, v2.2s
+#    v9: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f23fe85		fcvtzs v5.2s, v20.2s, #29
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ea1bb35		fcvtzs v21.4s, v25.4s
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f3afc3a		fcvtzs v26.4s, v1.4s, #6
+#   v26: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ee1bb2d		fcvtzu v13.2d, v25.2d
+#   v13: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f60fdbc		fcvtzu v28.2d, v13.2d, #32
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2ea1b8da		fcvtzu v26.2s, v6.2s
+#   v26: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f31fd49		fcvtzu v9.2s, v10.2s, #15
+#    v9: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ea1b8de		fcvtzu v30.4s, v6.4s
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f2efed3		fcvtzu v19.4s, v22.4s, #18
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e6ffd0f		fdiv v15.2d, v8.2d, v15.2d
+#   v15: 0x7ff80000000000007ff8000000000000
+0x~~~~~~~~~~~~~~~~  2e3afd2c		fdiv v12.2s, v9.2s, v26.2s
+#   v12: 0x00000000000000007fc000007fc00000
+0x~~~~~~~~~~~~~~~~  6e33fed3		fdiv v19.4s, v22.4s, v19.4s
+#   v19: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4e68f4f3		fmax v19.2d, v7.2d, v8.2d
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e3df599		fmax v25.2s, v12.2s, v29.2s
+#   v25: 0x00000000000000007fc000007fc00000
+0x~~~~~~~~~~~~~~~~  4e25f5e6		fmax v6.4s, v15.4s, v5.4s
+#    v6: 0x7ff80000000000007ff8000000000000
+0x~~~~~~~~~~~~~~~~  4e74c510		fmaxnm v16.2d, v8.2d, v20.2d
+#   v16: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e39c74f		fmaxnm v15.2s, v26.2s, v25.2s
+#   v15: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e30c5d7		fmaxnm v23.4s, v14.4s, v16.4s
+#   v23: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7e70ca66		fmaxnmp d6, v19.2d
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7e30cb5b		fmaxnmp s27, v26.2s
+#   v27: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e77c588		fmaxnmp v8.2d, v12.2d, v23.2d
+#    v8: 0x00000000000000007fc000007fc00000
+0x~~~~~~~~~~~~~~~~  2e36c72d		fmaxnmp v13.2s, v25.2s, v22.2s
+#   v13: 0x0000000000000000ffffffff7fc00000
+0x~~~~~~~~~~~~~~~~  6e31c56f		fmaxnmp v15.4s, v11.4s, v17.4s
+#   v15: 0xffffffffffffffff0000000000000000
+0x~~~~~~~~~~~~~~~~  6e30ca7b		fmaxnmv s27, v19.4s
+#   v27: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7e70f9d4		fmaxp d20, v14.2d
+#   v20: 0x0000000000000000ffffffff00000000
+0x~~~~~~~~~~~~~~~~  7e30f852		fmaxp s18, v2.2s
+#   v18: 0x000000000000000000000000000000ff
+0x~~~~~~~~~~~~~~~~  6e7ff6e9		fmaxp v9.2d, v23.2d, v31.2d
+#    v9: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e3ff6c7		fmaxp v7.2s, v22.2s, v31.2s
+#    v7: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  6e3df4f2		fmaxp v18.4s, v7.4s, v29.4s
+#   v18: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  6e30fbbf		fmaxv s31, v29.4s
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ee2f4a2		fmin v2.2d, v5.2d, v2.2d
+#    v2: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0eaaf63f		fmin v31.2s, v17.2s, v10.2s
+#   v31: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4eb0f48a		fmin v10.4s, v4.4s, v16.4s
+#   v10: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ee5c4d5		fminnm v21.2d, v6.2d, v5.2d
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0eaec656		fminnm v22.2s, v18.2s, v14.2s
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ea3c7f9		fminnm v25.4s, v31.4s, v3.4s
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7ef0c829		fminnmp d9, v1.2d
+#    v9: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7eb0ca95		fminnmp s21, v20.2s
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ef3c6b0		fminnmp v16.2d, v21.2d, v19.2d
+#   v16: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2eb9c7f0		fminnmp v16.2s, v31.2s, v25.2s
+#   v16: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  6eafc61a		fminnmp v26.4s, v16.4s, v15.4s
+#   v26: 0xffffffff000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6eb0c883		fminnmv s3, v4.4s
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7ef0fb58		fminp d24, v26.2d
+#   v24: 0x0000000000000000ffffffff00000000
+0x~~~~~~~~~~~~~~~~  7eb0fa27		fminp s7, v17.2s
+#    v7: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  6ee3f677		fminp v23.2d, v19.2d, v3.2d
+#   v23: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2ea9f6bd		fminp v29.2s, v21.2s, v9.2s
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6eb5f700		fminp v0.4s, v24.4s, v21.4s
+#    v0: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  6eb0f919		fminv s25, v8.4s
+#   v25: 0x0000000000000000000000007fc00000
+0x~~~~~~~~~~~~~~~~  5fc91817		fmla d23, d0, v9.d[2]
+#   v23: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5f8711f7		fmla s23, s15, v7.s[0]
+#   v23: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  4e66cd71		fmla v17.2d, v11.2d, v6.2d
+#   v17: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4fcb13de		fmla v30.2d, v30.2d, v11.d[0]
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e26cd93		fmla v19.2s, v12.2s, v6.2s
+#   v19: 0x00000000000000007fc000007fc00000
+0x~~~~~~~~~~~~~~~~  0f891238		fmla v24.2s, v17.2s, v9.s[0]
+#   v24: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4e2bcd70		fmla v16.4s, v11.4s, v11.4s
+#   v16: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  4f891afb		fmla v27.4s, v23.4s, v9.s[2]
+#   v27: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  5fc653db		fmls d27, d30, v6.d[0]
+#   v27: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  5f825215		fmls s21, s16, v2.s[0]
+#   v21: 0x0000000000000000000000007fffffff
+0x~~~~~~~~~~~~~~~~  4ef5ce65		fmls v5.2d, v19.2d, v21.2d
+#    v5: 0x0000000000000000be9000007f9fffff
+0x~~~~~~~~~~~~~~~~  4fcc53d2		fmls v18.2d, v30.2d, v12.d[0]
+#   v18: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  0ea7ce05		fmls v5.2s, v16.2s, v7.2s
+#    v5: 0x0000000000000000be9000007fdfffff
+0x~~~~~~~~~~~~~~~~  0fab5243		fmls v3.2s, v18.2s, v11.s[1]
+#    v3: 0x0000000000000000000000007fffffff
+0x~~~~~~~~~~~~~~~~  4ebeccbb		fmls v27.4s, v5.4s, v30.4s
+#   v27: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  4fa45a9a		fmls v26.4s, v20.4s, v4.s[3]
+#   v26: 0xffffffff000000007fffffff00000000
+0x~~~~~~~~~~~~~~~~  6f06f6ce		fmov v14.2d, #0xd6 (-0.3438)
+#   v14: 0xbfd6000000000000bfd6000000000000
+0x~~~~~~~~~~~~~~~~  0f03f5ba		fmov v26.2s, #0x6d (0.9062)
+#   v26: 0x00000000000000003f6800003f680000
+0x~~~~~~~~~~~~~~~~  4f04f69f		fmov v31.4s, #0x94 (-5.0000)
+#   v31: 0xc0a00000c0a00000c0a00000c0a00000
+0x~~~~~~~~~~~~~~~~  9eaf033c		fmov v28.D[1], x25
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  9eae0052		fmov x18, v2.D[1]
+#   x18: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  5fc1988c		fmul d12, d4, v1.d[2]
+#   v12: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5faf983e		fmul s30, s1, v15.s[3]
+#   v30: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  6e75dc19		fmul v25.2d, v0.2d, v21.2d
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4fca9b0a		fmul v10.2d, v24.2d, v10.d[2]
+#   v10: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  2e30df07		fmul v7.2s, v24.2s, v16.2s
+#    v7: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  0f849a01		fmul v1.2s, v16.2s, v4.s[2]
+#    v1: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  6e39df85		fmul v5.4s, v28.4s, v25.4s
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f88906b		fmul v11.4s, v3.4s, v8.s[0]
+#   v11: 0x7fc000007fc000007fc000007fffffff
+0x~~~~~~~~~~~~~~~~  7fc3993c		fmulx d28, d9, v3.d[2]
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7faf92b9		fmulx s25, s21, v15.s[1]
+#   v25: 0x0000000000000000000000007fffffff
+0x~~~~~~~~~~~~~~~~  4e68df9f		fmulx v31.2d, v28.2d, v8.2d
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6fc692a3		fmulx v3.2d, v21.2d, v6.d[0]
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e20dc29		fmulx v9.2s, v1.2s, v0.2s
+#    v9: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  2f869370		fmulx v16.2s, v27.2s, v6.s[0]
+#   v16: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  4e25dc82		fmulx v2.4s, v4.4s, v5.4s
+#    v2: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f8490f2		fmulx v18.4s, v7.4s, v4.s[0]
+#   v18: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  6ee0fb21		fneg v1.2d, v25.2d
+#    v1: 0x8000000000000000800000007fffffff
+0x~~~~~~~~~~~~~~~~  2ea0fbee		fneg v14.2s, v31.2s
+#   v14: 0x00000000000000008000000080000000
+0x~~~~~~~~~~~~~~~~  6ea0f885		fneg v5.4s, v4.4s
+#    v5: 0x80000000800000008000000080000000
+0x~~~~~~~~~~~~~~~~  4ee1d992		frecpe v18.2d, v12.2d
+#   v18: 0x7ff00000000000007ff0000000000000
+0x~~~~~~~~~~~~~~~~  0ea1daca		frecpe v10.2s, v22.2s
+#   v10: 0x00000000000000007f8000007f800000
+0x~~~~~~~~~~~~~~~~  4ea1d8c5		frecpe v5.4s, v6.4s
+#    v5: 0x7f8000007f8000007f8000007f800000
+0x~~~~~~~~~~~~~~~~  4e7afcf6		frecps v22.2d, v7.2d, v26.2d
+#   v22: 0x40000000000000007fffffffffffffff
+0x~~~~~~~~~~~~~~~~  0e22ff7f		frecps v31.2s, v27.2s, v2.2s
+#   v31: 0x0000000000000000400000007fffffff
+0x~~~~~~~~~~~~~~~~  4e3bfcd2		frecps v18.4s, v6.4s, v27.4s
+#   v18: 0x400000004000000040000000ffffffff
+0x~~~~~~~~~~~~~~~~  6e6189ba		frinta v26.2d, v13.2d
+#   v26: 0x0000000000000000ffffffff7fc00000
+0x~~~~~~~~~~~~~~~~  2e218b4f		frinta v15.2s, v26.2s
+#   v15: 0x0000000000000000ffffffff7fc00000
+0x~~~~~~~~~~~~~~~~  6e218a0d		frinta v13.4s, v16.4s
+#   v13: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  6ee19989		frinti v9.2d, v12.2d
+#    v9: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2ea19a65		frinti v5.2s, v19.2s
+#    v5: 0x00000000000000007fc000007fc00000
+0x~~~~~~~~~~~~~~~~  6ea1996f		frinti v15.4s, v11.4s
+#   v15: 0x7fc000007fc000007fc000007fffffff
+0x~~~~~~~~~~~~~~~~  4e619bb1		frintm v17.2d, v29.2d
+#   v17: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e21997e		frintm v30.2s, v11.2s
+#   v30: 0x00000000000000007fc000007fffffff
+0x~~~~~~~~~~~~~~~~  4e219a81		frintm v1.4s, v20.4s
+#    v1: 0x0000000000000000ffffffff00000000
+0x~~~~~~~~~~~~~~~~  4e6188d8		frintn v24.2d, v6.2d
+#   v24: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e218a2c		frintn v12.2s, v17.2s
+#   v12: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e21897d		frintn v29.4s, v11.4s
+#   v29: 0x7fc000007fc000007fc000007fffffff
+0x~~~~~~~~~~~~~~~~  4ee188ea		frintp v10.2d, v7.2d
+#   v10: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  0ea18a4c		frintp v12.2s, v18.2s
+#   v12: 0x000000000000000040000000ffffffff
+0x~~~~~~~~~~~~~~~~  4ea18bfa		frintp v26.4s, v31.4s
+#   v26: 0x0000000000000000400000007fffffff
+0x~~~~~~~~~~~~~~~~  6e6199b8		frintx v24.2d, v13.2d
+#   v24: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e219927		frintx v7.2s, v9.2s
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e219ab2		frintx v18.4s, v21.4s
+#   v18: 0x0000000000000000000000007fffffff
+0x~~~~~~~~~~~~~~~~  4ee19b33		frintz v19.2d, v25.2d
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ea1990f		frintz v15.2s, v8.2s
+#   v15: 0x00000000000000007fc000007fc00000
+0x~~~~~~~~~~~~~~~~  4ea19874		frintz v20.4s, v3.4s
+#   v20: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ee1d8b7		frsqrte v23.2d, v5.2d
+#   v23: 0x7ff00000000000002006900000000000
+0x~~~~~~~~~~~~~~~~  2ea1d8e9		frsqrte v9.2s, v7.2s
+#    v9: 0x00000000000000007f8000007f800000
+0x~~~~~~~~~~~~~~~~  6ea1d923		frsqrte v3.4s, v9.4s
+#    v3: 0x7f8000007f8000000000000000000000
+0x~~~~~~~~~~~~~~~~  4eefff99		frsqrts v25.2d, v28.2d, v15.2d
+#   v25: 0x3ff80000000000003ff8000000000000
+0x~~~~~~~~~~~~~~~~  0eaaff49		frsqrts v9.2s, v26.2s, v10.2s
+#    v9: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4eaafc25		frsqrts v5.4s, v1.4s, v10.4s
+#    v5: 0x3fc000003fc000007fffffffffffffff
+0x~~~~~~~~~~~~~~~~  6ee1fa46		fsqrt v6.2d, v18.2d
+#    v6: 0x00000000000000001f56a09e66689b2e
+0x~~~~~~~~~~~~~~~~  2ea1fa46		fsqrt v6.2s, v18.2s
+#    v6: 0x0000000000000000000000007fffffff
+0x~~~~~~~~~~~~~~~~  6ea1fbe0		fsqrt v0.4s, v31.4s
+#    v0: 0x00000000000000003fb504f37fffffff
+0x~~~~~~~~~~~~~~~~  4effd7df		fsub v31.2d, v30.2d, v31.2d
+#   v31: 0x00000000000000007fc000007fffffff
+0x~~~~~~~~~~~~~~~~  0ea6d50b		fsub v11.2s, v8.2s, v6.2s
+#   v11: 0x00000000000000007fc000007fc00000
+0x~~~~~~~~~~~~~~~~  4ebfd410		fsub v16.4s, v0.4s, v31.4s
+#   v16: 0x00000000000000007fc000007fffffff
+0x~~~~~~~~~~~~~~~~  4e61dbf9		scvtf v25.2d, v31.2d
+#   v25: 0x000000000000000043dff00000200000
+0x~~~~~~~~~~~~~~~~  4f53e5aa		scvtf v10.2d, v13.2d, #45
+#   v10: 0x00000000000000003f1fffffffe00000
+0x~~~~~~~~~~~~~~~~  0e21d9ea		scvtf v10.2s, v15.2s
+#   v10: 0x00000000000000004eff80004eff8000
+0x~~~~~~~~~~~~~~~~  0f25e492		scvtf v18.2s, v4.2s, #27
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e21d8b1		scvtf v17.4s, v5.4s
+#   v17: 0x4e7f00004e7f00004f000000bf800000
+0x~~~~~~~~~~~~~~~~  4f28e72b		scvtf v11.4s, v25.4s, #24
+#   v11: 0x00000000000000004287bfe03e000000
+0x~~~~~~~~~~~~~~~~  6e61d869		ucvtf v9.2d, v3.2d
+#    v9: 0x43dfe000001fe0000000000000000000
+0x~~~~~~~~~~~~~~~~  6f52e7da		ucvtf v26.2d, v30.2d, #46
+#   v26: 0x000000000000000040fff00000200000
+0x~~~~~~~~~~~~~~~~  2e21d88b		ucvtf v11.2s, v4.2s
+#   v11: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f27e47d		ucvtf v29.2s, v3.2s, #25
+#   v29: 0x7fc000007fc000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e21daf6		ucvtf v22.4s, v23.4s
+#   v22: 0x4effe000000000004e001a4000000000
+0x~~~~~~~~~~~~~~~~  6f27e532		ucvtf v18.4s, v9.4s, #25
+#   v18: 0x4207bfc03d7f00000000000000000000
+0x~~~~~~~~~~~~~~~~  d65f03c0		ret
diff --git a/test/test-trace-reference/log-all-colour b/test/test-trace-reference/log-all-colour
new file mode 100644
index 0000000..0080afe
--- /dev/null
+++ b/test/test-trace-reference/log-all-colour
@@ -0,0 +1,6065 @@
+#    x0: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x2: 0x~~~~~~~~~~~~~~~~
+#    x3: 0x0300003000300303
+#    x4: 0x0400004000400404
+#    x5: 0x0500005000500505
+#    x6: 0x0600006000600606
+#    x7: 0x0700007000700707
+#    x8: 0x0800008000800808
+#    x9: 0x0900009000900909
+#   x10: 0x0a0000a000a00a0a
+#   x11: 0x0b0000b000b00b0b
+#   x12: 0x0c0000c000c00c0c
+#   x13: 0x0d0000d000d00d0d
+#   x14: 0x0e0000e000e00e0e
+#   x15: 0x0f0000f000f00f0f
+#   x16: 0x1000010001001010
+#   x17: 0x1100011001101111
+#   x18: 0x1200012001201212
+#   x19: 0x1300013001301313
+#   x20: 0x1400014001401414
+#   x21: 0x1500015001501515
+#   x22: 0x1600016001601616
+#   x23: 0x1700017001701717
+#   x24: 0x1800018001801818
+#   x25: 0x1900019001901919
+#   x26: 0x1a0001a001a01a1a
+#   x27: 0x1b0001b001b01b1b
+#   x28: 0x1c0001c001c01c1c
+#   x29: 0x1d0001d001d01d1d
+#    lr: 0x0000000000000000
+#    sp: 0x~~~~~~~~~~~~~~~~
+#    v0: 0x00055555005555550000000000000000
+#    v1: 0x3ff0d2c63fcb514c3ff587933f9e0419
+#    v2: 0x4000d2c6404b514c40058793401e0419
+#    v3: 0x401570fb40385373401025ae406d0626
+#    v4: 0x4010d2c640cb514c40158793409e0419
+#    v5: 0x401fbc2d4090d04a401ae97840c5851f
+#    v6: 0x402570fb40b85373402025ae40ed0626
+#    v7: 0x402783f4415f16c34022d6a1410a4396
+#    v8: 0x4020d2c6414b514c40258793411e0419
+#    v9: 0x402d6dd3416491c9402838864131c49c
+#   v10: 0x402fbc2d4110d04a402ae9784145851f
+#   v11: 0x4028cf3e410c10f7402d9a6b415945a2
+#   v12: 0x403570fb41385373403025ae416d0626
+#   v13: 0x40342b7d41d5360140317e2841806354
+#   v14: 0x403783f441df16c34032d6a1418a4396
+#   v15: 0x40317a4f41c1768240342f1a419423d7
+#   v16: 0x4030d2c641cb514c40358793419e0419
+#   v17: 0x4033b55841f2b10e4036e00d41a7e45b
+#   v18: 0x403d6dd341e491c94038388641b1c49c
+#   v19: 0x403cc5aa41eef18b403990ff41bba4de
+#   v20: 0x403fbc2d4190d04a403ae97841c5851f
+#   v21: 0x403914a7419a3034403c41f241cf6561
+#   v22: 0x4038cf3e418c10f7403d9a6b41d945a2
+#   v23: 0x403ba7b141b670b1403ef2e441e325e4
+#   v24: 0x404570fb41b85373404025ae41ed0626
+#   v25: 0x404584be41a3b3324040d1eb41f6e667
+#   v26: 0x40442b7d4255360140417e2842006354
+#   v27: 0x40477f314250062040422a6442055375
+#   v28: 0x404783f4425f16c34042d6a1420a4396
+#   v29: 0x4046d78b425a66e2404382de420f33b7
+#   v30: 0x40417a4f4241768240442f1a421423d7
+#   v31: 0x40418e02424c46ad4044db57421913f8
+0x~~~~~~~~~~~~~~~~  1a050083		adc w3, w4, w5
+#    x3: 0x0000000000900909
+0x~~~~~~~~~~~~~~~~  9a0800e6		adc x6, x7, x8
+#    x6: 0x0f0000f000f00f0f
+0x~~~~~~~~~~~~~~~~  3a0b0149		adcs w9, w10, w11
+# NZCV: N:0 Z:0 C:0 V:0
+#    x9: 0x0000000001501515
+0x~~~~~~~~~~~~~~~~  ba0e01ac		adcs x12, x13, x14
+# NZCV: N:0 Z:0 C:0 V:0
+#   x12: 0x1b0001b001b01b1b
+0x~~~~~~~~~~~~~~~~  0b11020f		add w15, w16, w17
+#   x15: 0x0000000002102121
+0x~~~~~~~~~~~~~~~~  8b140272		add x18, x19, x20
+#   x18: 0x2700027002702727
+0x~~~~~~~~~~~~~~~~  2b1702d5		adds w21, w22, w23
+# NZCV: N:0 Z:0 C:0 V:0
+#   x21: 0x0000000002d02d2d
+0x~~~~~~~~~~~~~~~~  ab1a0338		adds x24, x25, x26
+# NZCV: N:0 Z:0 C:0 V:0
+#   x24: 0x3300033003303333
+0x~~~~~~~~~~~~~~~~  0a1d039b		and w27, w28, w29
+#   x27: 0x0000000001c01c1c
+0x~~~~~~~~~~~~~~~~  8a040062		and x2, x3, x4
+#    x2: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  6a0700c5		ands w5, w6, w7
+# NZCV: N:0 Z:0 C:0 V:0
+#    x5: 0x0000000000700707
+0x~~~~~~~~~~~~~~~~  ea0a0128		ands x8, x9, x10
+# NZCV: N:0 Z:1 C:0 V:0
+#    x8: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  13007d8b		sbfx w11, w12, #0, #32
+#   x11: 0x0000000001b01b1b
+0x~~~~~~~~~~~~~~~~  9341fdcd		asr x13, x14, #1
+#   x13: 0x0700007000700707
+0x~~~~~~~~~~~~~~~~  1ad12a0f		asr w15, w16, w17
+#   x15: 0x0000000000000080
+0x~~~~~~~~~~~~~~~~  9ad42a72		asr x18, x19, x20
+#   x18: 0x0000013000130013
+0x~~~~~~~~~~~~~~~~  33051ad5		bfxil w21, w22, #5, #2
+#   x21: 0x0000000002d02d2c
+0x~~~~~~~~~~~~~~~~  b3472317		bfxil x23, x24, #7, #2
+#   x23: 0x1700017001701716
+0x~~~~~~~~~~~~~~~~  0a3b0359		bic w25, w26, w27
+#   x25: 0x0000000000200202
+0x~~~~~~~~~~~~~~~~  8a2203bc		bic x28, x29, x2
+#   x28: 0x1d0001d001d01d1d
+0x~~~~~~~~~~~~~~~~  6a250083		bics w3, w4, w5
+# NZCV: N:0 Z:1 C:0 V:0
+#    x3: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  ea2800e6		bics x6, x7, x8
+# NZCV: N:0 Z:0 C:0 V:0
+#    x6: 0x0700007000700707
+0x~~~~~~~~~~~~~~~~  3a4ae120		ccmn w9, w10, #nzcv, al
+# NZCV: N:0 Z:0 C:0 V:0
+0x~~~~~~~~~~~~~~~~  3a4a0120		ccmn w9, w10, #nzcv, eq
+# NZCV: N:0 Z:0 C:0 V:0
+0x~~~~~~~~~~~~~~~~  3a4a1120		ccmn w9, w10, #nzcv, ne
+# NZCV: N:0 Z:0 C:0 V:0
+0x~~~~~~~~~~~~~~~~  ba4ce162		ccmn x11, x12, #nzCv, al
+# NZCV: N:0 Z:0 C:0 V:0
+0x~~~~~~~~~~~~~~~~  ba4c3162		ccmn x11, x12, #nzCv, lo
+# NZCV: N:0 Z:0 C:0 V:0
+0x~~~~~~~~~~~~~~~~  ba4c2162		ccmn x11, x12, #nzCv, hs
+# NZCV: N:0 Z:0 C:1 V:0
+0x~~~~~~~~~~~~~~~~  7a4ee1a1		ccmp w13, w14, #nzcV, al
+# NZCV: N:1 Z:0 C:0 V:0
+0x~~~~~~~~~~~~~~~~  7a4e81a1		ccmp w13, w14, #nzcV, hi
+# NZCV: N:0 Z:0 C:0 V:1
+0x~~~~~~~~~~~~~~~~  7a4e91a1		ccmp w13, w14, #nzcV, ls
+# NZCV: N:1 Z:0 C:0 V:0
+0x~~~~~~~~~~~~~~~~  fa50e1e3		ccmp x15, x16, #nzCV, al
+# NZCV: N:1 Z:0 C:0 V:0
+0x~~~~~~~~~~~~~~~~  fa5001e3		ccmp x15, x16, #nzCV, eq
+# NZCV: N:0 Z:0 C:1 V:1
+0x~~~~~~~~~~~~~~~~  fa5011e3		ccmp x15, x16, #nzCV, ne
+# NZCV: N:1 Z:0 C:0 V:0
+0x~~~~~~~~~~~~~~~~  1a922651		cinc w17, w18, lo
+#   x17: 0x0000000000130014
+0x~~~~~~~~~~~~~~~~  1a923651		cinc w17, w18, hs
+#   x17: 0x0000000000130013
+0x~~~~~~~~~~~~~~~~  9a949693		cinc x19, x20, hi
+#   x19: 0x1400014001401414
+0x~~~~~~~~~~~~~~~~  9a948693		cinc x19, x20, ls
+#   x19: 0x1400014001401415
+0x~~~~~~~~~~~~~~~~  5a9612d5		cinv w21, w22, eq
+#   x21: 0x0000000001601616
+0x~~~~~~~~~~~~~~~~  5a9602d5		cinv w21, w22, ne
+#   x21: 0x00000000fe9fe9e9
+0x~~~~~~~~~~~~~~~~  da982317		cinv x23, x24, lo
+#   x23: 0xccfffccffccfcccc
+0x~~~~~~~~~~~~~~~~  da983317		cinv x23, x24, hs
+#   x23: 0x3300033003303333
+0x~~~~~~~~~~~~~~~~  d5033f5f		clrex
+0x~~~~~~~~~~~~~~~~  5ac01759		cls w25, w26
+#   x25: 0x0000000000000006
+0x~~~~~~~~~~~~~~~~  dac0179b		cls x27, x28
+#   x27: 0x0000000000000002
+0x~~~~~~~~~~~~~~~~  5ac0105d		clz w29, w2
+#   x29: 0x0000000000000020
+0x~~~~~~~~~~~~~~~~  dac01083		clz x3, x4
+#    x3: 0x0000000000000005
+0x~~~~~~~~~~~~~~~~  2b0600bf		cmn w5, w6
+# NZCV: N:0 Z:0 C:0 V:0
+0x~~~~~~~~~~~~~~~~  ab0800ff		cmn x7, x8
+# NZCV: N:0 Z:0 C:0 V:0
+0x~~~~~~~~~~~~~~~~  6b0a013f		cmp w9, w10
+# NZCV: N:0 Z:0 C:1 V:0
+0x~~~~~~~~~~~~~~~~  eb0c017f		cmp x11, x12
+# NZCV: N:1 Z:0 C:0 V:0
+0x~~~~~~~~~~~~~~~~  5a8e95cd		cneg w13, w14, hi
+#   x13: 0x0000000000e00e0e
+0x~~~~~~~~~~~~~~~~  5a8e85cd		cneg w13, w14, ls
+#   x13: 0x00000000ff1ff1f2
+0x~~~~~~~~~~~~~~~~  da90160f		cneg x15, x16, eq
+#   x15: 0x1000010001001010
+0x~~~~~~~~~~~~~~~~  da90060f		cneg x15, x16, ne
+#   x15: 0xeffffefffeffeff0
+0x~~~~~~~~~~~~~~~~  1ad34251		crc32b w17, w18, w19
+#   x17: 0x00000000e963b635
+0x~~~~~~~~~~~~~~~~  1ad652b4		crc32cb w20, w21, w22
+#   x20: 0x00000000ad83ccb8
+0x~~~~~~~~~~~~~~~~  1ad95717		crc32ch w23, w24, w25
+#   x23: 0x000000003ed5525d
+0x~~~~~~~~~~~~~~~~  1adc5b7a		crc32cw w26, w27, w28
+#   x26: 0x00000000bc365145
+0x~~~~~~~~~~~~~~~~  1ac644a4		crc32h w4, w5, w6
+#    x4: 0x0000000000000070
+0x~~~~~~~~~~~~~~~~  1ac94907		crc32w w7, w8, w9
+#    x7: 0x00000000b096abf4
+0x~~~~~~~~~~~~~~~~  1a8f31cd		csel w13, w14, w15, lo
+#   x13: 0x0000000000e00e0e
+0x~~~~~~~~~~~~~~~~  1a8f21cd		csel w13, w14, w15, hs
+#   x13: 0x00000000feffeff0
+0x~~~~~~~~~~~~~~~~  9a928230		csel x16, x17, x18, hi
+#   x16: 0x0000013000130013
+0x~~~~~~~~~~~~~~~~  9a929230		csel x16, x17, x18, ls
+#   x16: 0x00000000e963b635
+0x~~~~~~~~~~~~~~~~  1a9f17f3		cset w19, eq
+#   x19: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  1a9f07f3		cset w19, ne
+#   x19: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  9a9f27f4		cset x20, lo
+#   x20: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  9a9f37f4		cset x20, hs
+#   x20: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  5a9f93f5		csetm w21, hi
+#   x21: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  5a9f83f5		csetm w21, ls
+#   x21: 0x00000000ffffffff
+0x~~~~~~~~~~~~~~~~  da9f13f6		csetm x22, eq
+#   x22: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  da9f03f6		csetm x22, ne
+#   x22: 0xffffffffffffffff
+0x~~~~~~~~~~~~~~~~  1a993717		csinc w23, w24, w25, lo
+#   x23: 0x0000000003303333
+0x~~~~~~~~~~~~~~~~  1a992717		csinc w23, w24, w25, hs
+#   x23: 0x0000000000000007
+0x~~~~~~~~~~~~~~~~  9a9c877a		csinc x26, x27, x28, hi
+#   x26: 0x1d0001d001d01d1e
+0x~~~~~~~~~~~~~~~~  9a9c977a		csinc x26, x27, x28, ls
+#   x26: 0x0000000000000002
+0x~~~~~~~~~~~~~~~~  5a83005d		csinv w29, w2, w3, eq
+#   x29: 0x00000000fffffffa
+0x~~~~~~~~~~~~~~~~  5a83105d		csinv w29, w2, w3, ne
+#   x29: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  da8630a4		csinv x4, x5, x6, lo
+#    x4: 0x0000000000700707
+0x~~~~~~~~~~~~~~~~  da8620a4		csinv x4, x5, x6, hs
+#    x4: 0xf8ffff8fff8ff8f8
+0x~~~~~~~~~~~~~~~~  5a898507		csneg w7, w8, w9, hi
+#    x7: 0x00000000feafeaeb
+0x~~~~~~~~~~~~~~~~  5a899507		csneg w7, w8, w9, ls
+#    x7: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  da8c056a		csneg x10, x11, x12, eq
+#   x10: 0xe4fffe4ffe4fe4e5
+0x~~~~~~~~~~~~~~~~  da8c156a		csneg x10, x11, x12, ne
+#   x10: 0x0000000001b01b1b
+0x~~~~~~~~~~~~~~~~  d50b7a20		dc cvac, x0
+0x~~~~~~~~~~~~~~~~  d5033bbf		dmb ish
+0x~~~~~~~~~~~~~~~~  d5033b9f		dsb ish
+0x~~~~~~~~~~~~~~~~  4a2f01cd		eon w13, w14, w15
+#   x13: 0x0000000001e01e01
+0x~~~~~~~~~~~~~~~~  ca320230		eon x16, x17, x18
+#   x16: 0xfffffecf168f49d9
+0x~~~~~~~~~~~~~~~~  4a150293		eor w19, w20, w21
+#   x19: 0x00000000ffffffff
+0x~~~~~~~~~~~~~~~~  ca1802f6		eor x22, x23, x24
+#   x22: 0x3300033003303334
+0x~~~~~~~~~~~~~~~~  139b2759		extr w25, w26, w27, #9
+#   x25: 0x0000000001000000
+0x~~~~~~~~~~~~~~~~  93c22bbc		extr x28, x29, x2, #10
+#   x28: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  d503201f		nop
+0x~~~~~~~~~~~~~~~~  d50b7520		ic ivau, x0
+0x~~~~~~~~~~~~~~~~  d5033fdf		isb
+0x~~~~~~~~~~~~~~~~  88dffc03		ldar w3, [x0]
+#    x3: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  c8dffc04		ldar x4, [x0]
+#    x4: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  08dffc05		ldarb w5, [x0]
+#    x5: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  08dffc06		ldarb w6, [x0]
+#    x6: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  48dffc07		ldarh w7, [x0]
+#    x7: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  48dffc08		ldarh w8, [x0]
+#    x8: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  887fa809		ldaxp w9, w10, [x0]
+#    x9: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#   x10: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  c87fb00b		ldaxp x11, x12, [x0]
+#   x11: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#   x12: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  885ffc0d		ldaxr w13, [x0]
+#   x13: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  c85ffc0e		ldaxr x14, [x0]
+#   x14: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  085ffc0f		ldaxrb w15, [x0]
+#   x15: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  085ffc10		ldaxrb w16, [x0]
+#   x16: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  485ffc11		ldaxrh w17, [x0]
+#   x17: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  485ffc12		ldaxrh w18, [x0]
+#   x18: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  28405013		ldnp w19, w20, [x0]
+#   x19: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#   x20: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a8405815		ldnp x21, x22, [x0]
+#   x21: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#   x22: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  29406017		ldp w23, w24, [x0]
+#   x23: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#   x24: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  28c16037		ldp w23, w24, [x1], #8
+#   x23: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#   x24: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  29c16037		ldp w23, w24, [x1, #8]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   x23: 0x0000000013121110 <- 0x~~~~~~~~~~~~~~~~
+#   x24: 0x0000000017161514 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a9406819		ldp x25, x26, [x0]
+#   x25: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#   x26: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a8c16839		ldp x25, x26, [x1], #16
+#   x25: 0x1716151413121110 <- 0x~~~~~~~~~~~~~~~~
+#   x26: 0x1f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a9c16839		ldp x25, x26, [x1, #16]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   x25: 0x3736353433323130 <- 0x~~~~~~~~~~~~~~~~
+#   x26: 0x3f3e3d3c3b3a3938 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  6940701b		ldpsw x27, x28, [x0]
+#   x27: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#   x28: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  68c1703b		ldpsw x27, x28, [x1], #8
+#   x27: 0x0000000033323130 <- 0x~~~~~~~~~~~~~~~~
+#   x28: 0x0000000037363534 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  69c1703b		ldpsw x27, x28, [x1, #8]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   x27: 0x0000000043424140 <- 0x~~~~~~~~~~~~~~~~
+#   x28: 0x0000000047464544 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  b940001d		ldr w29, [x0]
+#   x29: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  b840443d		ldr w29, [x1], #4
+#   x29: 0x0000000043424140 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  b8404c3d		ldr w29, [x1, #4]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   x29: 0x000000004b4a4948 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  f9400002		ldr x2, [x0]
+#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  f8408422		ldr x2, [x1], #8
+#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  f8408c22		ldr x2, [x1, #8]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  39400003		ldrb w3, [x0]
+#    x3: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  38401423		ldrb w3, [x1], #1
+#    x3: 0x0000000000000058 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  38401c23		ldrb w3, [x1, #1]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x3: 0x000000000000005a <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  39400004		ldrb w4, [x0]
+#    x4: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  38401424		ldrb w4, [x1], #1
+#    x4: 0x000000000000005a <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  38401c24		ldrb w4, [x1, #1]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x4: 0x000000000000005c <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  79400005		ldrh w5, [x0]
+#    x5: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  78402425		ldrh w5, [x1], #2
+#    x5: 0x0000000000005d5c <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  78402c25		ldrh w5, [x1, #2]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x5: 0x0000000000006160 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  79400006		ldrh w6, [x0]
+#    x6: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  78402426		ldrh w6, [x1], #2
+#    x6: 0x0000000000006160 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  78402c26		ldrh w6, [x1, #2]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x6: 0x0000000000006564 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  39c00007		ldrsb w7, [x0]
+#    x7: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  38c01427		ldrsb w7, [x1], #1
+#    x7: 0x0000000000000064 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  38c01c27		ldrsb w7, [x1, #1]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x7: 0x0000000000000066 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  39800008		ldrsb x8, [x0]
+#    x8: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  38801428		ldrsb x8, [x1], #1
+#    x8: 0x0000000000000066 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  38801c28		ldrsb x8, [x1, #1]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x8: 0x0000000000000068 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  79c00009		ldrsh w9, [x0]
+#    x9: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  78c02429		ldrsh w9, [x1], #2
+#    x9: 0x0000000000006968 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  78c02c29		ldrsh w9, [x1, #2]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x9: 0x0000000000006d6c <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  7980000a		ldrsh x10, [x0]
+#   x10: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  7880242a		ldrsh x10, [x1], #2
+#   x10: 0x0000000000006d6c <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  78802c2a		ldrsh x10, [x1, #2]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   x10: 0x0000000000007170 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  b980000b		ldrsw x11, [x0]
+#   x11: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  b880442b		ldrsw x11, [x1], #4
+#   x11: 0x0000000073727170 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  b8804c2b		ldrsw x11, [x1, #4]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   x11: 0x000000007b7a7978 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  b840700c		ldur w12, [x0, #7]
+#   x12: 0x000000000a090807 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  f840f00d		ldur x13, [x0, #15]
+#   x13: 0x161514131211100f <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  3840100e		ldurb w14, [x0, #1]
+#   x14: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  3840100f		ldurb w15, [x0, #1]
+#   x15: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  78403010		ldurh w16, [x0, #3]
+#   x16: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  78403011		ldurh w17, [x0, #3]
+#   x17: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  38c01012		ldursb w18, [x0, #1]
+#   x18: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  38801013		ldursb x19, [x0, #1]
+#   x19: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  78c03014		ldursh w20, [x0, #3]
+#   x20: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  78803015		ldursh x21, [x0, #3]
+#   x21: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  b8807016		ldursw x22, [x0, #7]
+#   x22: 0x000000000a090807 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  887f6017		ldxp w23, w24, [x0]
+#   x23: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#   x24: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  c87f6819		ldxp x25, x26, [x0]
+#   x25: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#   x26: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  885f7c1b		ldxr w27, [x0]
+#   x27: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  c85f7c1c		ldxr x28, [x0]
+#   x28: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  085f7c1d		ldxrb w29, [x0]
+#   x29: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  085f7c02		ldxrb w2, [x0]
+#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  485f7c03		ldxrh w3, [x0]
+#    x3: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  485f7c04		ldxrh w4, [x0]
+#    x4: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  531e74c5		lsl w5, w6, #2
+#    x5: 0x0000000000019590
+0x~~~~~~~~~~~~~~~~  d37df107		lsl x7, x8, #3
+#    x7: 0x0000000000000340
+0x~~~~~~~~~~~~~~~~  1acb2149		lsl w9, w10, w11
+#    x9: 0x0000000070000000
+0x~~~~~~~~~~~~~~~~  9ace21ac		lsl x12, x13, x14
+#   x12: 0x2c2a28262422201e
+0x~~~~~~~~~~~~~~~~  53047e0f		lsr w15, w16, #4
+#   x15: 0x0000000000000040
+0x~~~~~~~~~~~~~~~~  d345fe51		lsr x17, x18, #5
+#   x17: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  1ad52693		lsr w19, w20, w21
+#   x19: 0x0000000000000080
+0x~~~~~~~~~~~~~~~~  9ad826f6		lsr x22, x23, x24
+#   x22: 0x0000000000302010
+0x~~~~~~~~~~~~~~~~  1b1b7359		madd w25, w26, w27, w28
+#   x25: 0x00000000371b0900
+0x~~~~~~~~~~~~~~~~  9b03105d		madd x29, x2, x3, x4
+#   x29: 0x0000000000000100
+0x~~~~~~~~~~~~~~~~  1b07fcc5		mneg w5, w6, w7
+#    x5: 0x00000000feb67b00
+0x~~~~~~~~~~~~~~~~  9b0afd28		mneg x8, x9, x10
+#    x8: 0xffffce5f00000000
+0x~~~~~~~~~~~~~~~~  2a0c03eb		mov w11, w12
+#   x11: 0x000000002422201e
+0x~~~~~~~~~~~~~~~~  aa0e03ed		mov x13, x14
+#   x13: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  7280104f		movk w15, #0x82
+#   x15: 0x0000000000000082
+0x~~~~~~~~~~~~~~~~  f2801070		movk x16, #0x83
+#   x16: 0x0000000000000083
+0x~~~~~~~~~~~~~~~~  12801091		mov w17, #0xffffff7b
+#   x17: 0x00000000ffffff7b
+0x~~~~~~~~~~~~~~~~  928010b2		mov x18, #0xffffffffffffff7a
+#   x18: 0xffffffffffffff7a
+0x~~~~~~~~~~~~~~~~  528010d3		mov w19, #0x86
+#   x19: 0x0000000000000086
+0x~~~~~~~~~~~~~~~~  d28010f4		mov x20, #0x87
+#   x20: 0x0000000000000087
+0x~~~~~~~~~~~~~~~~  1b18e6f6		msub w22, w23, w24, w25
+#   x22: 0x000000001b0e0500
+0x~~~~~~~~~~~~~~~~  9b1cf77a		msub x26, x27, x28, x29
+#   x26: 0xe3e9eff5fbff0100
+0x~~~~~~~~~~~~~~~~  1b047c62		mul w2, w3, w4
+#    x2: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  9b077cc5		mul x5, x6, x7
+#    x5: 0x0000000001498500
+0x~~~~~~~~~~~~~~~~  2a2903e8		mvn w8, w9
+#    x8: 0x000000008fffffff
+0x~~~~~~~~~~~~~~~~  aa2b03ea		mvn x10, x11
+#   x10: 0xffffffffdbdddfe1
+0x~~~~~~~~~~~~~~~~  4b0d03ec		neg w12, w13
+#   x12: 0x00000000ffffffff
+0x~~~~~~~~~~~~~~~~  cb0f03ee		neg x14, x15
+#   x14: 0xffffffffffffff7e
+0x~~~~~~~~~~~~~~~~  6b1103f0		negs w16, w17
+# NZCV: N:0 Z:0 C:0 V:0
+#   x16: 0x0000000000000085
+0x~~~~~~~~~~~~~~~~  eb1303f2		negs x18, x19
+# NZCV: N:1 Z:0 C:0 V:0
+#   x18: 0xffffffffffffff7a
+0x~~~~~~~~~~~~~~~~  5a1503f4		ngc w20, w21
+#   x20: 0x00000000fffffbfc
+0x~~~~~~~~~~~~~~~~  da1703f6		ngc x22, x23
+#   x22: 0xfffffffffcfdfeff
+0x~~~~~~~~~~~~~~~~  7a1903f8		ngcs w24, w25
+# NZCV: N:1 Z:0 C:0 V:0
+#   x24: 0x00000000c8e4f6ff
+0x~~~~~~~~~~~~~~~~  fa1b03fa		ngcs x26, x27
+# NZCV: N:1 Z:0 C:0 V:0
+#   x26: 0xfffffffffcfdfeff
+0x~~~~~~~~~~~~~~~~  d503201f		nop
+0x~~~~~~~~~~~~~~~~  2a2203bc		orn w28, w29, w2
+#   x28: 0x00000000fffeffff
+0x~~~~~~~~~~~~~~~~  aa250083		orn x3, x4, x5
+#    x3: 0xfffffffffeb67bff
+0x~~~~~~~~~~~~~~~~  2a0800e6		orr w6, w7, w8
+#    x6: 0x000000008fffffff
+0x~~~~~~~~~~~~~~~~  aa0b0149		orr x9, x10, x11
+#    x9: 0xffffffffffffffff
+0x~~~~~~~~~~~~~~~~  f8804000		prfum pldl1keep, [x0, #4]
+0x~~~~~~~~~~~~~~~~  f8801000		prfum pldl1keep, [x0, #1]
+0x~~~~~~~~~~~~~~~~  5ac001ac		rbit w12, w13
+#   x12: 0x0000000080000000
+0x~~~~~~~~~~~~~~~~  dac001ee		rbit x14, x15
+#   x14: 0x4100000000000000
+0x~~~~~~~~~~~~~~~~  5ac00a30		rev w16, w17
+#   x16: 0x000000007bffffff
+0x~~~~~~~~~~~~~~~~  dac00e72		rev x18, x19
+#   x18: 0x8600000000000000
+0x~~~~~~~~~~~~~~~~  5ac006b4		rev16 w20, w21
+#   x20: 0x0000000000000304
+0x~~~~~~~~~~~~~~~~  dac006f6		rev16 x22, x23
+#   x22: 0x0000000002030001
+0x~~~~~~~~~~~~~~~~  dac00b38		rev32 x24, x25
+#   x24: 0x0000000000091b37
+0x~~~~~~~~~~~~~~~~  1adc2f7a		ror w26, w27, w28
+#   x26: 0x0000000006040200
+0x~~~~~~~~~~~~~~~~  9ac32c5d		ror x29, x2, x3
+#   x29: 0x0000000000020000
+0x~~~~~~~~~~~~~~~~  5a0600a4		sbc w4, w5, w6
+#    x4: 0x0000000071498500
+0x~~~~~~~~~~~~~~~~  da090107		sbc x7, x8, x9
+#    x7: 0x000000008fffffff
+0x~~~~~~~~~~~~~~~~  7a0c016a		sbcs w10, w11, w12
+# NZCV: N:1 Z:0 C:0 V:1
+#   x10: 0x00000000a422201d
+0x~~~~~~~~~~~~~~~~  fa0f01cd		sbcs x13, x14, x15
+# NZCV: N:0 Z:0 C:1 V:0
+#   x13: 0x40ffffffffffff7d
+0x~~~~~~~~~~~~~~~~  131e0a30		sbfiz w16, w17, #2, #3
+#   x16: 0x000000000000000c
+0x~~~~~~~~~~~~~~~~  937c1272		sbfiz x18, x19, #4, #5
+#   x18: 0x0000000000000060
+0x~~~~~~~~~~~~~~~~  130632f6		sbfx w22, w23, #6, #7
+#   x22: 0x0000000000000004
+0x~~~~~~~~~~~~~~~~  93484338		sbfx x24, x25, #8, #9
+#   x24: 0xffffffffffffff09
+0x~~~~~~~~~~~~~~~~  1adc0f7a		sdiv w26, w27, w28
+#   x26: 0x00000000fffffcff
+0x~~~~~~~~~~~~~~~~  9ac30c5d		sdiv x29, x2, x3
+#   x29: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  9b4e7dac		smulh x12, x13, x14
+#   x12: 0x1080ffffffffffde
+0x~~~~~~~~~~~~~~~~  889ffc12		stlr w18, [x0]
+#   w18:         0x00000060 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  c89ffc13		stlr x19, [x0]
+#   x19: 0x0000000000000086 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  089ffc14		stlrb w20, [x0]
+#   w20<7:0>:          0x04 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  089ffc15		stlrb w21, [x0]
+#   w21<7:0>:          0x03 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  489ffc16		stlrh w22, [x0]
+#   w22<15:0>:       0x0004 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  489ffc17		stlrh w23, [x0]
+#   w23<15:0>:       0x0100 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  8838e819		stlxp w24, w25, w26, [x0]
+#   x24: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  c83bf41c		stlxp w27, x28, x29, [x0]
+#   x27: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  8802fc03		stlxr w2, w3, [x0]
+#    x2: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  c804fc05		stlxr w4, x5, [x0]
+#    x4: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  0806fc07		stlxrb w6, w7, [x0]
+#    x6: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  0808fc09		stlxrb w8, w9, [x0]
+#    x8: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  480afc0b		stlxrh w10, w11, [x0]
+#   x10: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  480cfc0d		stlxrh w12, w13, [x0]
+#   x12: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  28003c0e		stnp w14, w15, [x0]
+#   w14:         0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#   w15:         0x00000082 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a8004410		stnp x16, x17, [x0]
+#   x16: 0x000000000000000c -> 0x~~~~~~~~~~~~~~~~
+#   x17: 0x00000000ffffff7b -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  29004c12		stp w18, w19, [x0]
+#   w18:         0x00000060 -> 0x~~~~~~~~~~~~~~~~
+#   w19:         0x00000086 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  28814c32		stp w18, w19, [x1], #8
+#   w18:         0x00000060 -> 0x~~~~~~~~~~~~~~~~
+#   w19:         0x00000086 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  29814c32		stp w18, w19, [x1, #8]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   w18:         0x00000060 -> 0x~~~~~~~~~~~~~~~~
+#   w19:         0x00000086 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a9005414		stp x20, x21, [x0]
+#   x20: 0x0000000000000304 -> 0x~~~~~~~~~~~~~~~~
+#   x21: 0x0000000000000403 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a8815434		stp x20, x21, [x1], #16
+#   x20: 0x0000000000000304 -> 0x~~~~~~~~~~~~~~~~
+#   x21: 0x0000000000000403 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a9815434		stp x20, x21, [x1, #16]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   x20: 0x0000000000000304 -> 0x~~~~~~~~~~~~~~~~
+#   x21: 0x0000000000000403 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  b9000016		str w22, [x0]
+#   w22:         0x00000004 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  b8004436		str w22, [x1], #4
+#   w22:         0x00000004 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  b8004c36		str w22, [x1, #4]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   w22:         0x00000004 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  f9000017		str x23, [x0]
+#   x23: 0x0000000003020100 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  f8008437		str x23, [x1], #8
+#   x23: 0x0000000003020100 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  f8008c37		str x23, [x1, #8]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   x23: 0x0000000003020100 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  39000018		strb w24, [x0]
+#   w24<7:0>:          0x01 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  38001438		strb w24, [x1], #1
+#   w24<7:0>:          0x01 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  38001c38		strb w24, [x1, #1]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   w24<7:0>:          0x01 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  39000019		strb w25, [x0]
+#   w25<7:0>:          0x00 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  38001439		strb w25, [x1], #1
+#   w25<7:0>:          0x00 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  38001c39		strb w25, [x1, #1]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   w25<7:0>:          0x00 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  7900001a		strh w26, [x0]
+#   w26<15:0>:       0xfcff -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  7800243a		strh w26, [x1], #2
+#   w26<15:0>:       0xfcff -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  78002c3a		strh w26, [x1, #2]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   w26<15:0>:       0xfcff -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  7900001b		strh w27, [x0]
+#   w27<15:0>:       0x0001 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  7800243b		strh w27, [x1], #2
+#   w27<15:0>:       0x0001 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  78002c3b		strh w27, [x1, #2]!
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   w27<15:0>:       0x0001 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  b800701c		stur w28, [x0, #7]
+#   w28:         0xfffeffff -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  f800f01d		stur x29, [x0, #15]
+#   x29: 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  38001002		sturb w2, [x0, #1]
+#    w2<7:0>:          0x01 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  38001003		sturb w3, [x0, #1]
+#    w3<7:0>:          0xff -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  78003004		sturh w4, [x0, #3]
+#    w4<15:0>:       0x0001 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  78003005		sturh w5, [x0, #3]
+#    w5<15:0>:       0x8500 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  88262007		stxp w6, w7, w8, [x0]
+#    x6: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  c8292c0a		stxp w9, x10, x11, [x0]
+#    x9: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  880c7c0d		stxr w12, w13, [x0]
+#   x12: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  c80e7c0f		stxr w14, x15, [x0]
+#   x14: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  08107c11		stxrb w16, w17, [x0]
+#   x16: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  08127c13		stxrb w18, w19, [x0]
+#   x18: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  48147c15		stxrh w20, w21, [x0]
+#   x20: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  48167c17		stxrh w22, w23, [x0]
+#   x22: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  4b1a0338		sub w24, w25, w26
+#   x24: 0x00000000371b0c01
+0x~~~~~~~~~~~~~~~~  cb1d039b		sub x27, x28, x29
+#   x27: 0x00000000fffeffff
+0x~~~~~~~~~~~~~~~~  6b040062		subs w2, w3, w4
+# NZCV: N:1 Z:0 C:1 V:0
+#    x2: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  eb0700c5		subs x5, x6, x7
+# NZCV: N:1 Z:0 C:0 V:0
+#    x5: 0xffffffff70000002
+0x~~~~~~~~~~~~~~~~  13001d28		sxtb w8, w9
+#    x8: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  93401d6a		sxtb x10, w11
+#   x10: 0x000000000000001e
+0x~~~~~~~~~~~~~~~~  13003dac		sxth w12, w13
+#   x12: 0x00000000ffffff7d
+0x~~~~~~~~~~~~~~~~  93403dee		sxth x14, w15
+#   x14: 0x0000000000000082
+0x~~~~~~~~~~~~~~~~  13007e30		sbfx w16, w17, #0, #32
+#   x16: 0x00000000ffffff7b
+0x~~~~~~~~~~~~~~~~  93407e72		sxtw x18, w19
+#   x18: 0x0000000000000086
+0x~~~~~~~~~~~~~~~~  6a15029f		tst w20, w21
+# NZCV: N:0 Z:0 C:0 V:0
+0x~~~~~~~~~~~~~~~~  ea1702df		tst x22, x23
+# NZCV: N:0 Z:1 C:0 V:0
+0x~~~~~~~~~~~~~~~~  53162b38		ubfiz w24, w25, #10, #11
+#   x24: 0x0000000000040000
+0x~~~~~~~~~~~~~~~~  d374337a		ubfiz x26, x27, #12, #13
+#   x26: 0x0000000001fff000
+0x~~~~~~~~~~~~~~~~  530e3fbc		ubfx w28, w29, #14, #2
+#   x28: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  d3410862		ubfx x2, x3, #1, #2
+#    x2: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  530318a4		ubfx w4, w5, #3, #4
+#    x4: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  d34528e6		ubfx x6, x7, #5, #6
+#    x6: 0x000000000000003f
+0x~~~~~~~~~~~~~~~~  1aca0928		udiv w8, w9, w10
+#    x8: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  9acd098b		udiv x11, x12, x13
+#   x11: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  9bd87ef6		umulh x22, x23, x24
+#   x22: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  53001fbc		uxtb w28, w29
+#   x28: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  d3401c62		uxtb x2, w3
+#    x2: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  53003ca4		uxth w4, w5
+#    x4: 0x0000000000000002
+0x~~~~~~~~~~~~~~~~  d3403ce6		uxth x6, w7
+#    x6: 0x000000000000ffff
+0x~~~~~~~~~~~~~~~~  53007d28		lsr w8, w9, #0
+#    x8: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  d3407d6a		ubfx x10, x11, #0, #32
+#   x10: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  7ef3d44d		fabd d13, d2, d19
+#   v13: 0x00000000000000004036e00cd9b7e45b
+0x~~~~~~~~~~~~~~~~  7ebed548		fabd s8, s10, s30
+#    v8: 0x00000000000000000000000041c5851e
+0x~~~~~~~~~~~~~~~~  1e60c021		fabs d1, d1
+#    v1: 0x00000000000000003ff587933f9e0419 (d1: 1.34560)
+0x~~~~~~~~~~~~~~~~  1e20c0f9		fabs s25, s7
+#   v25: 0x000000000000000000000000410a4396 (s25: 8.64150)
+0x~~~~~~~~~~~~~~~~  7e70eee1		facge d1, d23, d16
+#    v1: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  7e21ee24		facge s4, s17, s1
+#    v4: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7ef8eea2		facgt d2, d21, d24
+#    v2: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7eacef4c		facgt s12, s26, s12
+#   v12: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  1e76296d		fadd d13, d11, d22
+#   v13: 0x0000000000000000404633d07142f43a (d13: 44.4048)
+0x~~~~~~~~~~~~~~~~  1e282a7b		fadd s27, s19, s8
+#   v27: 0x000000000000000000000000424094fe (s27: 48.1455)
+0x~~~~~~~~~~~~~~~~  1e6a24c0		fccmp d6, d10, #nzcv, hs
+# NZCV: N:0 Z:0 C:0 V:0
+0x~~~~~~~~~~~~~~~~  1e3417ad		fccmp s29, s20, #NZcV, ne
+# NZCV: N:0 Z:0 C:1 V:0
+0x~~~~~~~~~~~~~~~~  1e62e55e		fccmpe d10, d2, #NZCv, al
+# NZCV: N:0 Z:0 C:1 V:0
+0x~~~~~~~~~~~~~~~~  1e23547d		fccmpe s3, s3, #NZcV, pl
+# NZCV: N:0 Z:1 C:1 V:0
+0x~~~~~~~~~~~~~~~~  5e6ae513		fcmeq d19, d8, d10
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5ee0da40		fcmeq d0, d18, #0.0
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5e3ee481		fcmeq s1, s4, s30
+#    v1: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5ea0dbb6		fcmeq s22, s29, #0.0
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7e61e65b		fcmge d27, d18, d1
+#   v27: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  7ee0cb9f		fcmge d31, d28, #0.0
+#   v31: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  7e29e67f		fcmge s31, s19, s9
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7ea0cb21		fcmge s1, s25, #0.0
+#    v1: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  7eefe432		fcmgt d18, d1, d15
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5ee0cbe3		fcmgt d3, d31, #0.0
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7ea2e72b		fcmgt s11, s25, s2
+#   v11: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  5ea0ca11		fcmgt s17, s16, #0.0
+#   v17: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  7ee0da38		fcmle d24, d17, #0.0
+#   v24: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7ea0d90b		fcmle s11, s8, #0.0
+#   v11: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5ee0ebe5		fcmlt d5, d31, #0.0
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5ea0eaf2		fcmlt s18, s23, #0.0
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  1e782140		fcmp d10, d24
+# NZCV: N:0 Z:0 C:1 V:0
+0x~~~~~~~~~~~~~~~~  1e6021a8		fcmp d13, #0.0
+# NZCV: N:0 Z:0 C:1 V:0
+0x~~~~~~~~~~~~~~~~  1e262240		fcmp s18, s6
+# NZCV: N:1 Z:0 C:0 V:0
+0x~~~~~~~~~~~~~~~~  1e202208		fcmp s16, #0.0
+# NZCV: N:0 Z:0 C:1 V:0
+0x~~~~~~~~~~~~~~~~  1e712130		fcmpe d9, d17
+# NZCV: N:0 Z:0 C:1 V:0
+0x~~~~~~~~~~~~~~~~  1e6023b8		fcmpe d29, #0.0
+# NZCV: N:0 Z:0 C:1 V:0
+0x~~~~~~~~~~~~~~~~  1e312210		fcmpe s16, s17
+# NZCV: N:0 Z:0 C:1 V:1
+0x~~~~~~~~~~~~~~~~  1e2022d8		fcmpe s22, #0.0
+# NZCV: N:0 Z:1 C:1 V:0
+0x~~~~~~~~~~~~~~~~  1e73cdca		fcsel d10, d14, d19, gt
+#   v10: 0x00000000000000000000000000000000 (d10: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e22ae56		fcsel s22, s18, s2, ge
+#   v22: 0x00000000000000000000000000000000 (s22: 0.00000)
+0x~~~~~~~~~~~~~~~~  1ee2c304		fcvt d4, h24
+#    v4: 0x00000000000000000000000000000000 (d4: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e22c04b		fcvt d11, s2
+#   v11: 0x00000000000000000000000000000000 (d11: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e63c128		fcvt h8, d9
+#    v8: 0x00000000000000000000000000004a0e
+0x~~~~~~~~~~~~~~~~  1e23c02c		fcvt h12, s1
+#   v12: 0x0000000000000000000000000000ffff
+0x~~~~~~~~~~~~~~~~  1e6243ec		fcvt s12, d31
+#   v12: 0x00000000000000000000000000000000 (s12: 0.00000)
+0x~~~~~~~~~~~~~~~~  1ee2433b		fcvt s27, h25
+#   v27: 0x0000000000000000000000004072c000 (s27: 3.79297)
+0x~~~~~~~~~~~~~~~~  5e61ca1c		fcvtas d28, d16
+#   v28: 0x00000000000000000000000000000016
+0x~~~~~~~~~~~~~~~~  5e21c8a3		fcvtas s3, s5
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  1e6403f2		fcvtas w18, d31
+#   x18: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  1e24031d		fcvtas w29, s24
+#   x29: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  9e640029		fcvtas x9, d1
+#    x9: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  9e24005e		fcvtas x30, s2
+#    lr: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  7e61c80e		fcvtau d14, d0
+#   v14: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7e21c9df		fcvtau s31, s14
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  1e650050		fcvtau w16, d2
+#   x16: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  1e250012		fcvtau w18, s0
+#   x18: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  9e6500fa		fcvtau x26, d7
+#   x26: 0x0000000000000009
+0x~~~~~~~~~~~~~~~~  9e250279		fcvtau x25, s19
+#   x25: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  5e61bb3e		fcvtms d30, d25
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5e21b9ec		fcvtms s12, s15
+#   v12: 0x00000000000000000000000000000012
+0x~~~~~~~~~~~~~~~~  1e7000e9		fcvtms w9, d7
+#    x9: 0x0000000000000009
+0x~~~~~~~~~~~~~~~~  1e3000d3		fcvtms w19, s6
+#   x19: 0x0000000000000007
+0x~~~~~~~~~~~~~~~~  9e7000c6		fcvtms x6, d6
+#    x6: 0x0000000000000008
+0x~~~~~~~~~~~~~~~~  9e3000f6		fcvtms x22, s7
+#   x22: 0x0000000000000008
+0x~~~~~~~~~~~~~~~~  7e61b81b		fcvtmu d27, d0
+#   v27: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7e21bac8		fcvtmu s8, s22
+#    v8: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  1e71027d		fcvtmu w29, d19
+#   x29: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  1e31001a		fcvtmu w26, s0
+#   x26: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  9e7100ad		fcvtmu x13, d5
+#   x13: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  9e310245		fcvtmu x5, s18
+#    x5: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  5e61a9fe		fcvtns d30, d15
+#   v30: 0x00000000000000000000000000000014
+0x~~~~~~~~~~~~~~~~  5e21a96a		fcvtns s10, s11
+#   v10: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  1e6001f5		fcvtns w21, d15
+#   x21: 0x0000000000000014
+0x~~~~~~~~~~~~~~~~  1e200152		fcvtns w18, s10
+#   x18: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  9e600228		fcvtns x8, d17
+#    x8: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  9e200191		fcvtns x17, s12
+#   x17: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  7e61aaa0		fcvtnu d0, d21
+#    v0: 0x0000000000000000000000000000001c
+0x~~~~~~~~~~~~~~~~  7e21ab26		fcvtnu s6, s25
+#    v6: 0x00000000000000000000000000000009
+0x~~~~~~~~~~~~~~~~  1e61017d		fcvtnu w29, d11
+#   x29: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  1e2103f9		fcvtnu w25, s31
+#   x25: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  9e61017e		fcvtnu x30, d11
+#    lr: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  9e21025b		fcvtnu x27, s18
+#   x27: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  5ee1aacb		fcvtps d11, d22
+#   v11: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5ea1aa9d		fcvtps s29, s20
+#   v29: 0x00000000000000000000000000000019
+0x~~~~~~~~~~~~~~~~  1e68032f		fcvtps w15, d25
+#   x15: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  1e2800f0		fcvtps w16, s7
+#   x16: 0x0000000000000009
+0x~~~~~~~~~~~~~~~~  9e68028d		fcvtps x13, d20
+#   x13: 0x000000000000001b
+0x~~~~~~~~~~~~~~~~  9e2802e3		fcvtps x3, s23
+#    x3: 0x000000000000001d
+0x~~~~~~~~~~~~~~~~  7ee1a838		fcvtpu d24, d1
+#   v24: 0x00000000000000000000000000000001
+0x~~~~~~~~~~~~~~~~  7ea1ab0e		fcvtpu s14, s24
+#   v14: 0x00000000000000000000000000000001
+0x~~~~~~~~~~~~~~~~  1e6903ba		fcvtpu w26, d29
+#   x26: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  1e29035f		fcvtpu wzr, s26
+0x~~~~~~~~~~~~~~~~  9e6900db		fcvtpu x27, d6
+#   x27: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  9e2901dd		fcvtpu x29, s14
+#   x29: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  7e61698c		fcvtxn s12, d12
+#   v12: 0x00000000000000000000000000000001
+0x~~~~~~~~~~~~~~~~  5ee1b80f		fcvtzs d15, d0
+#   v15: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5f56fc8d		fcvtzs d13, d4, #42
+#   v13: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5ea1b968		fcvtzs s8, s11
+#    v8: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5f27fcdf		fcvtzs s31, s6, #25
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  1e780126		fcvtzs w6, d9
+#    x6: 0x000000000000000c
+0x~~~~~~~~~~~~~~~~  1e58b159		fcvtzs w25, d10, #20
+#   x25: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  1e380029		fcvtzs w9, s1
+#    x9: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  1e188bb1		fcvtzs w17, s29, #30
+#   x17: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  9e780053		fcvtzs x19, d2
+#   x19: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  9e58fdd6		fcvtzs x22, d14, #1
+#   x22: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  9e38028e		fcvtzs x14, s20
+#   x14: 0x0000000000000018
+0x~~~~~~~~~~~~~~~~  9e187fc3		fcvtzs x3, s30, #33
+#    x3: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  7ee1b9fc		fcvtzu d28, d15
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7f7dfc80		fcvtzu d0, d4, #3
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7ea1b8a2		fcvtzu s2, s5
+#    v2: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7f22fc04		fcvtzu s4, s0, #30
+#    v4: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  1e79008b		fcvtzu w11, d4
+#   x11: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  1e598307		fcvtzu w7, d24, #32
+#    x7: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  1e390312		fcvtzu w18, s24
+#   x18: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  1e19f36e		fcvtzu w14, s27, #4
+#   x14: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  9e790176		fcvtzu x22, d11
+#   x22: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  9e593368		fcvtzu x8, d27, #52
+#    x8: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  9e390287		fcvtzu x7, s20
+#    x7: 0x0000000000000018
+0x~~~~~~~~~~~~~~~~  9e1950f6		fcvtzu x22, s7, #44
+#   x22: 0x00008a4396000000
+0x~~~~~~~~~~~~~~~~  1e6f19c6		fdiv d6, d14, d15
+#    v6: 0x00000000000000007ff0000000000000 (d6: inf)
+0x~~~~~~~~~~~~~~~~  1e3918ba		fdiv s26, s5, s25
+#   v26: 0x00000000000000000000000000000000 (s26: 0.00000)
+0x~~~~~~~~~~~~~~~~  1f4c7b52		fmadd d18, d26, d12, d30
+#   v18: 0x00000000000000000000000000000014 (d18: 9.88131e-323)
+0x~~~~~~~~~~~~~~~~  1f1c112d		fmadd s13, s9, s28, s4
+#   v13: 0x00000000000000000000000000000000 (s13: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e6548ac		fmax d12, d5, d5
+#   v12: 0x00000000000000000000000000000000 (d12: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e264b8c		fmax s12, s28, s6
+#   v12: 0x00000000000000000000000000000000 (s12: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e62689c		fmaxnm d28, d4, d2
+#   v28: 0x00000000000000000000000000000000 (d28: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e286946		fmaxnm s6, s10, s8
+#    v6: 0x00000000000000000000000000000000 (s6: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e725a94		fmin d20, d20, d18
+#   v20: 0x00000000000000000000000000000014 (d20: 9.88131e-323)
+0x~~~~~~~~~~~~~~~~  1e3059a7		fmin s7, s13, s16
+#    v7: 0x00000000000000000000000000000000 (s7: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e7e79d3		fminnm d19, d14, d30
+#   v19: 0x00000000000000000000000000000001 (d19: 4.94066e-324)
+0x~~~~~~~~~~~~~~~~  1e217820		fminnm s0, s1, s1
+#    v0: 0x000000000000000000000000ffffffff (s0: -nan)
+0x~~~~~~~~~~~~~~~~  1e6040cd		fmov d13, d6
+#   v13: 0x00000000000000000000000000000000 (d13: 0.00000)
+0x~~~~~~~~~~~~~~~~  9e670222		fmov d2, x17
+#    v2: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  1e709008		fmov d8, #0x84 (-2.5000)
+#    v8: 0x0000000000000000c004000000000000 (d8: -2.50000)
+0x~~~~~~~~~~~~~~~~  1e204065		fmov s5, s3
+#    v5: 0x00000000000000000000000000000000 (s5: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e270299		fmov s25, w20
+#   v25: 0x00000000000000000000000000000001
+0x~~~~~~~~~~~~~~~~  1e20f015		fmov s21, #0x7 (2.8750)
+#   v21: 0x00000000000000000000000040380000 (s21: 2.87500)
+0x~~~~~~~~~~~~~~~~  1e260312		fmov w18, s24
+#   x18: 0x0000000000000001
+0x~~~~~~~~~~~~~~~~  9e660052		fmov x18, d2
+#   x18: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  1f43cfd4		fmsub d20, d30, d3, d19
+#   v20: 0x00000000000000000000000000000001 (d20: 4.94066e-324)
+0x~~~~~~~~~~~~~~~~  1f04b265		fmsub s5, s19, s4, s12
+#    v5: 0x00000000000000000000000000000000 (s5: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e770b7e		fmul d30, d27, d23
+#   v30: 0x00000000000000000000000000000000 (d30: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e2f0a39		fmul s25, s17, s15
+#   v25: 0x000000000000000000000000ffffffff (s25: -nan)
+0x~~~~~~~~~~~~~~~~  5e61de24		fmulx d4, d17, d1
+#    v4: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5e24df2e		fmulx s14, s25, s4
+#   v14: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  1e61400f		fneg d15, d0
+#   v15: 0x000000000000000080000000ffffffff (d15: -2.12200e-314)
+0x~~~~~~~~~~~~~~~~  1e2141ee		fneg s14, s15
+#   v14: 0x0000000000000000000000007fffffff (s14: nan)
+0x~~~~~~~~~~~~~~~~  1f767e00		fnmadd d0, d16, d22, d31
+#    v0: 0x00000000000000008000000000000000 (d0: -0.00000)
+0x~~~~~~~~~~~~~~~~  1f3a4a40		fnmadd s0, s18, s26, s18
+#    v0: 0x00000000000000000000000080000014 (s0: -2.80260e-44)
+0x~~~~~~~~~~~~~~~~  1f6fd593		fnmsub d19, d12, d15, d21
+#   v19: 0x00000000000000008000000040380000 (d19: -5.32312e-315)
+0x~~~~~~~~~~~~~~~~  1f2be81d		fnmsub s29, s0, s11, s26
+#   v29: 0x00000000000000000000000080000000 (s29: -0.00000)
+0x~~~~~~~~~~~~~~~~  1e618a7f		fnmul d31, d19, d1
+#   v31: 0x00000000000000000000000000000000 (d31: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e318872		fnmul s18, s3, s17
+#   v18: 0x0000000000000000000000007fffffff (s18: nan)
+0x~~~~~~~~~~~~~~~~  5ee1daa7		frecpe d7, d21
+#    v7: 0x00000000000000007ff0000000000000
+0x~~~~~~~~~~~~~~~~  5ea1da3d		frecpe s29, s17
+#   v29: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  5e71ff4b		frecps d11, d26, d17
+#   v11: 0x00000000000000004000000000000000
+0x~~~~~~~~~~~~~~~~  5e21ff72		frecps s18, s27, s1
+#   v18: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  5ee1fa4f		frecpx d15, d18
+#   v15: 0x00000000000000007fe0000000000000
+0x~~~~~~~~~~~~~~~~  5ea1f945		frecpx s5, s10
+#    v5: 0x0000000000000000000000007f000000
+0x~~~~~~~~~~~~~~~~  1e6643d0		frinta d16, d30
+#   v16: 0x00000000000000000000000000000000 (d16: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e2642c1		frinta s1, s22
+#    v1: 0x00000000000000000000000000000000 (s1: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e67c3b3		frinti d19, d29
+#   v19: 0x00000000000000000000000000000000 (d19: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e27c2ae		frinti s14, s21
+#   v14: 0x00000000000000000000000040400000 (s14: 3.00000)
+0x~~~~~~~~~~~~~~~~  1e6543d4		frintm d20, d30
+#   v20: 0x00000000000000000000000000000000 (d20: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e254201		frintm s1, s16
+#    v1: 0x00000000000000000000000000000000 (s1: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e64403e		frintn d30, d1
+#   v30: 0x00000000000000000000000000000000 (d30: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e244158		frintn s24, s10
+#   v24: 0x00000000000000000000000000000000 (s24: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e64c284		frintp d4, d20
+#    v4: 0x00000000000000000000000000000000 (d4: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e24c06d		frintp s13, s3
+#   v13: 0x00000000000000000000000000000000 (s13: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e67428d		frintx d13, d20
+#   v13: 0x00000000000000000000000000000000 (d13: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e2740f1		frintx s17, s7
+#   v17: 0x00000000000000000000000000000000 (s17: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e65c100		frintz d0, d8
+#    v0: 0x0000000000000000c000000000000000 (d0: -2.00000)
+0x~~~~~~~~~~~~~~~~  1e25c3af		frintz s15, s29
+#   v15: 0x000000000000000000000000ffffffff (s15: -nan)
+0x~~~~~~~~~~~~~~~~  7ee1d955		frsqrte d21, d10
+#   v21: 0x00000000000000007ff0000000000000
+0x~~~~~~~~~~~~~~~~  7ea1db31		frsqrte s17, s25
+#   v17: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  5ef1ffa4		frsqrts d4, d29, d17
+#    v4: 0x00000000000000003ff8000000000000
+0x~~~~~~~~~~~~~~~~  5eb8fc6e		frsqrts s14, s3, s24
+#   v14: 0x0000000000000000000000003fc00000
+0x~~~~~~~~~~~~~~~~  1e61c22e		fsqrt d14, d17
+#   v14: 0x00000000000000001f5ffffffff00000 (d14: 1.45671e-157)
+0x~~~~~~~~~~~~~~~~  1e21c1c4		fsqrt s4, s14
+#    v4: 0x000000000000000000000000fff00000 (s4: -nan)
+0x~~~~~~~~~~~~~~~~  1e673a6d		fsub d13, d19, d7
+#   v13: 0x0000000000000000fff0000000000000 (d13: -inf)
+0x~~~~~~~~~~~~~~~~  1e3b3aa3		fsub s3, s21, s27
+#    v3: 0x00000000000000000000000000000000 (s3: 0.00000)
+0x~~~~~~~~~~~~~~~~  5e61da1f		scvtf d31, d16
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5f68e7fa		scvtf d26, d31, #24
+#   v26: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  1e620206		scvtf d6, w16
+#    v6: 0x00000000000000004022000000000000 (d6: 9.00000)
+0x~~~~~~~~~~~~~~~~  1e42ea85		scvtf d5, w20, #6
+#    v5: 0x00000000000000003f90000000000000 (d5: 0.0156250)
+0x~~~~~~~~~~~~~~~~  9e620110		scvtf d16, x8
+#   v16: 0x00000000000000000000000000000000 (d16: 0.00000)
+0x~~~~~~~~~~~~~~~~  9e42d90f		scvtf d15, x8, #10
+#   v15: 0x00000000000000000000000000000000 (d15: 0.00000)
+0x~~~~~~~~~~~~~~~~  5e21d887		scvtf s7, s4
+#    v7: 0x00000000000000007ff00000c9800000
+0x~~~~~~~~~~~~~~~~  5f32e5e8		scvtf s8, s15, #14
+#    v8: 0x0000000000000000c004000000000000
+0x~~~~~~~~~~~~~~~~  1e22015d		scvtf s29, w10
+#   v29: 0x00000000000000000000000000000000 (s29: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e02d6af		scvtf s15, w21, #11
+#   v15: 0x0000000000000000000000003c200000 (s15: 0.00976562)
+0x~~~~~~~~~~~~~~~~  9e22035b		scvtf s27, x26
+#   v27: 0x0000000000000000000000003f800000 (s27: 1.00000)
+0x~~~~~~~~~~~~~~~~  9e02699a		scvtf s26, x12, #38
+#   v26: 0x0000000000000000000000003c7fffff (s26: 0.0156250)
+0x~~~~~~~~~~~~~~~~  7e61d920		ucvtf d0, d9
+#    v0: 0x000000000000000043d00a0e21904c71
+0x~~~~~~~~~~~~~~~~  7f51e6c5		ucvtf d5, d22, #47
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  1e63037e		ucvtf d30, w27
+#   v30: 0x00000000000000003ff0000000000000 (d30: 1.00000)
+0x~~~~~~~~~~~~~~~~  1e43fe63		ucvtf d3, w19, #1
+#    v3: 0x00000000000000000000000000000000 (d3: 0.00000)
+0x~~~~~~~~~~~~~~~~  9e6302bc		ucvtf d28, x21
+#   v28: 0x00000000000000004034000000000000 (d28: 20.0000)
+0x~~~~~~~~~~~~~~~~  9e4377db		ucvtf d27, x30, #35
+#   v27: 0x00000000000000000000000000000000 (d27: 0.00000)
+0x~~~~~~~~~~~~~~~~  7e21d8ab		ucvtf s11, s5
+#   v11: 0x00000000000000004000000000000000
+0x~~~~~~~~~~~~~~~~  7f32e6e0		ucvtf s0, s23, #14
+#    v0: 0x000000000000000043d00a0e4783c64c
+0x~~~~~~~~~~~~~~~~  1e230274		ucvtf s20, w19
+#   v20: 0x00000000000000000000000000000000 (s20: 0.00000)
+0x~~~~~~~~~~~~~~~~  1e03bad5		ucvtf s21, w22, #18
+#   v21: 0x00000000000000000000000046160000 (s21: 9600.00)
+0x~~~~~~~~~~~~~~~~  9e2301a6		ucvtf s6, x13
+#    v6: 0x00000000000000000000000041d80000 (s6: 27.0000)
+0x~~~~~~~~~~~~~~~~  9e03ac47		ucvtf s7, x2, #21
+#    v7: 0x00000000000000000000000038ff0000 (s7: 0.000121593)
+0x~~~~~~~~~~~~~~~~  5ee0b813		abs d19, d0
+#   v19: 0x000000000000000043d00a0e4783c64c
+0x~~~~~~~~~~~~~~~~  4e20b970		abs v16.16b, v11.16b
+#   v16: 0x00000000000000004000000000000000
+0x~~~~~~~~~~~~~~~~  4ee0bbe0		abs v0.2d, v31.2d
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ea0bb3b		abs v27.2s, v25.2s
+#   v27: 0x00000000000000000000000000000001
+0x~~~~~~~~~~~~~~~~  0e60bb75		abs v21.4h, v27.4h
+#   v21: 0x00000000000000000000000000000001
+0x~~~~~~~~~~~~~~~~  4ea0b830		abs v16.4s, v1.4s
+#   v16: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e20b8bf		abs v31.8b, v5.8b
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e60b9bd		abs v29.8h, v13.8h
+#   v29: 0x00000000000000000010000000000000
+0x~~~~~~~~~~~~~~~~  5ef184aa		add d10, d5, d17
+#   v10: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  4e3785ff		add v31.16b, v15.16b, v23.16b
+#   v31: 0x403ba7b141b670b1403ef2e47d0325e4
+0x~~~~~~~~~~~~~~~~  4eee87ea		add v10.2d, v31.2d, v14.2d
+#   v10: 0x403ba7b141b670b15f9ef2e47cf325e4
+0x~~~~~~~~~~~~~~~~  0eb385cf		add v15.2s, v14.2s, v19.2s
+#   v15: 0x000000000000000063300a0d4773c64c
+0x~~~~~~~~~~~~~~~~  0e7186fb		add v27.4h, v23.4h, v17.4h
+#   v27: 0x0000000000000000403ef2e441e225e3
+0x~~~~~~~~~~~~~~~~  4ebd8799		add v25.4s, v28.4s, v29.4s
+#   v25: 0x00000000000000004044000000000000
+0x~~~~~~~~~~~~~~~~  0e3284ed		add v13.8b, v7.8b, v18.8b
+#   v13: 0x00000000000000000000000037feffff
+0x~~~~~~~~~~~~~~~~  4e618444		add v4.8h, v2.8h, v1.8h
+#    v4: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0eaf41ca		addhn v10.2s, v14.2d, v15.2d
+#   v10: 0x00000000000000000000000082900a0d
+0x~~~~~~~~~~~~~~~~  0e7a43ca		addhn v10.4h, v30.4s, v26.4s
+#   v10: 0x0000000000000000000000003ff03c7f
+0x~~~~~~~~~~~~~~~~  0e36419f		addhn v31.8b, v12.8h, v22.8h
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e3442b0		addhn2 v16.16b, v21.8h, v20.8h
+#   v16: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4eb14040		addhn2 v0.4s, v2.2d, v17.2d
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e7140ff		addhn2 v31.8h, v7.4s, v17.4s
+#   v31: 0x00000000000038fe0000000000000000
+0x~~~~~~~~~~~~~~~~  5ef1ba6e		addp d14, v19.2d
+#   v14: 0x000000000000000043d00a0e4783c64c
+0x~~~~~~~~~~~~~~~~  4e3cbd03		addp v3.16b, v8.16b, v28.16b
+#    v3: 0x000000007400000000000000c4000000
+0x~~~~~~~~~~~~~~~~  4ef1bca8		addp v8.2d, v5.2d, v17.2d
+#    v8: 0x00000000ffffffff0000000000000000
+0x~~~~~~~~~~~~~~~~  0ebabfd6		addp v22.2s, v30.2s, v26.2s
+#   v22: 0x00000000000000003c7fffff3ff00000
+0x~~~~~~~~~~~~~~~~  0e6ebf1d		addp v29.4h, v24.4h, v14.4h
+#   v29: 0x00000000000000004dde0dcf00000000
+0x~~~~~~~~~~~~~~~~  4eb8bf5e		addp v30.4s, v26.4s, v24.4s
+#   v30: 0x0000000000000000000000003c7fffff
+0x~~~~~~~~~~~~~~~~  0e27bf4c		addp v12.8b, v26.8b, v7.8b
+#   v12: 0x0000000000000000000037000000bbfe
+0x~~~~~~~~~~~~~~~~  4e6cbd11		addp v17.8h, v8.8h, v12.8h
+#   v17: 0x000000003700bbfe0000fffe00000000
+0x~~~~~~~~~~~~~~~~  4e31bafb		addv b27, v23.16b
+#   v27: 0x0000000000000000000000000000006c
+0x~~~~~~~~~~~~~~~~  0e31ba8c		addv b12, v20.8b
+#   v12: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e71bbdb		addv h27, v30.4h
+#   v27: 0x00000000000000000000000000003c7e
+0x~~~~~~~~~~~~~~~~  4e71b9d3		addv h19, v14.8h
+#   v19: 0x00000000000000000000000000005bad
+0x~~~~~~~~~~~~~~~~  4eb1bb6e		addv s14, v27.4s
+#   v14: 0x00000000000000000000000000003c7e
+0x~~~~~~~~~~~~~~~~  4e3b1d0a		and v10.16b, v8.16b, v27.16b
+#   v10: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e301c25		and v5.8b, v1.8b, v16.8b
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e781c7a		bic v26.16b, v3.16b, v24.16b
+#   v26: 0x000000007400000000000000c4000000
+0x~~~~~~~~~~~~~~~~  2f075487		bic v7.2s, #0xe4, lsl #16
+#    v7: 0x000000000000000000000000381b0000
+0x~~~~~~~~~~~~~~~~  2f01b47c		bic v28.4h, #0x23, lsl #8
+#   v28: 0x00000000000000004034000000000000
+0x~~~~~~~~~~~~~~~~  6f05159d		bic v29.4s, #0xac, lsl #0
+#   v29: 0x00000000000000004dde0d4300000000
+0x~~~~~~~~~~~~~~~~  0e751fec		bic v12.8b, v31.8b, v21.8b
+#   v12: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f049712		bic v18.8h, #0x98, lsl #0
+#   v18: 0x000000000000000000000000ff67ff67
+0x~~~~~~~~~~~~~~~~  6ee81f4c		bif v12.16b, v26.16b, v8.16b
+#   v12: 0x000000000000000000000000c4000000
+0x~~~~~~~~~~~~~~~~  2efb1ee2		bif v2.8b, v23.8b, v27.8b
+#    v2: 0x0000000000000000403ef2e441e30180
+0x~~~~~~~~~~~~~~~~  6ead1c68		bit v8.16b, v3.16b, v13.16b
+#    v8: 0x00000000ffffffff0000000004000000
+0x~~~~~~~~~~~~~~~~  2eb71ca5		bit v5.8b, v5.8b, v23.8b
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e771fe9		bsl v9.16b, v31.16b, v23.16b
+#    v9: 0x00128220009270f80016c26000c22160
+0x~~~~~~~~~~~~~~~~  2e631cee		bsl v14.8b, v7.8b, v3.8b
+#   v14: 0x000000000000000000000000c4000000
+0x~~~~~~~~~~~~~~~~  4e2048bd		cls v29.16b, v5.16b
+#   v29: 0x07070707070707070707070707070707
+0x~~~~~~~~~~~~~~~~  0ea04815		cls v21.2s, v0.2s
+#   v21: 0x00000000000000000000001f0000001f
+0x~~~~~~~~~~~~~~~~  0e604981		cls v1.4h, v12.4h
+#    v1: 0x0000000000000000000f000f0001000f
+0x~~~~~~~~~~~~~~~~  4ea0495b		cls v27.4s, v10.4s
+#   v27: 0x0000001f0000001f0000001f0000001f
+0x~~~~~~~~~~~~~~~~  0e204893		cls v19.8b, v4.8b
+#   v19: 0x00000000000000000707070707070707
+0x~~~~~~~~~~~~~~~~  4e6049cf		cls v15.8h, v14.8h
+#   v15: 0x000f000f000f000f000f000f0001000f
+0x~~~~~~~~~~~~~~~~  6e204881		clz v1.16b, v4.16b
+#    v1: 0x08080808080808080808080808080808
+0x~~~~~~~~~~~~~~~~  2ea04a3b		clz v27.2s, v17.2s
+#   v27: 0x00000000000000000000001000000020
+0x~~~~~~~~~~~~~~~~  2e604929		clz v9.4h, v9.4h
+#    v9: 0x0000000000000000000b000000080002
+0x~~~~~~~~~~~~~~~~  6ea049ff		clz v31.4s, v15.4s
+#   v31: 0x0000000c0000000c0000000c0000000f
+0x~~~~~~~~~~~~~~~~  2e204a6e		clz v14.8b, v19.8b
+#   v14: 0x00000000000000000505050505050505
+0x~~~~~~~~~~~~~~~~  6e604966		clz v6.8h, v11.8h
+#    v6: 0x00100010001000100001001000100010
+0x~~~~~~~~~~~~~~~~  7efd8cb2		cmeq d18, d5, d29
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5ee09bee		cmeq d14, d31, #0
+#   v14: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e368c73		cmeq v19.16b, v3.16b, v22.16b
+#   v19: 0xffffffff00ffffff000000000000ffff
+0x~~~~~~~~~~~~~~~~  4e20992f		cmeq v15.16b, v9.16b, #0
+#   v15: 0xffffffffffffffffff00ffffff00ff00
+0x~~~~~~~~~~~~~~~~  6eea8e0c		cmeq v12.2d, v16.2d, v10.2d
+#   v12: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4ee09ac8		cmeq v8.2d, v22.2d, #0
+#    v8: 0xffffffffffffffff0000000000000000
+0x~~~~~~~~~~~~~~~~  2ea98c62		cmeq v2.2s, v3.2s, v9.2s
+#    v2: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ea09b30		cmeq v16.2s, v25.2s, #0
+#   v16: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  2e748ee6		cmeq v6.4h, v23.4h, v20.4h
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e6099b0		cmeq v16.4h, v13.4h, #0
+#   v16: 0x0000000000000000ffffffff00000000
+0x~~~~~~~~~~~~~~~~  6ea28e35		cmeq v21.4s, v17.4s, v2.4s
+#   v21: 0xffffffff0000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  4ea09b26		cmeq v6.4s, v25.4s, #0
+#    v6: 0xffffffffffffffff00000000ffffffff
+0x~~~~~~~~~~~~~~~~  2e228db0		cmeq v16.8b, v13.8b, v2.8b
+#   v16: 0x0000000000000000ffffffff00000000
+0x~~~~~~~~~~~~~~~~  0e209a15		cmeq v21.8b, v16.8b, #0
+#   v21: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  6e798cf4		cmeq v20.8h, v7.8h, v25.8h
+#   v20: 0xffffffffffffffff0000ffff0000ffff
+0x~~~~~~~~~~~~~~~~  4e60991a		cmeq v26.8h, v8.8h, #0
+#   v26: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  5eff3db0		cmge d16, d13, d31
+#   v16: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7ee08b19		cmge d25, d24, #0
+#   v25: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4e313e71		cmge v17.16b, v19.16b, v17.16b
+#   v17: 0x000000000000ffffffffffffffff0000
+0x~~~~~~~~~~~~~~~~  6e208bd6		cmge v22.16b, v30.16b, #0
+#   v22: 0xffffffffffffffffffffffffffff0000
+0x~~~~~~~~~~~~~~~~  4efa3e9c		cmge v28.2d, v20.2d, v26.2d
+#   v28: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  6ee08ae6		cmge v6.2d, v23.2d, #0
+#    v6: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  0ea33ed9		cmge v25.2s, v22.2s, v3.2s
+#   v25: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  2ea08975		cmge v21.2s, v11.2s, #0
+#   v21: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  0e6c3c70		cmge v16.4h, v3.4h, v12.4h
+#   v16: 0x0000000000000000ffffffff0000ffff
+0x~~~~~~~~~~~~~~~~  2e608937		cmge v23.4h, v9.4h, #0
+#   v23: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4eab3c47		cmge v7.4s, v2.4s, v11.4s
+#    v7: 0xffffffffffffffff00000000ffffffff
+0x~~~~~~~~~~~~~~~~  6ea08ac0		cmge v0.4s, v22.4s, #0
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e293fca		cmge v10.8b, v30.8b, v9.8b
+#   v10: 0x0000000000000000ff00ffffffff0000
+0x~~~~~~~~~~~~~~~~  2e208915		cmge v21.8b, v8.8b, #0
+#   v21: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4e7a3ce2		cmge v2.8h, v7.8h, v26.8h
+#    v2: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  6e608953		cmge v19.8h, v10.8h, #0
+#   v19: 0xffffffffffffffff000000000000ffff
+0x~~~~~~~~~~~~~~~~  5ee135a6		cmgt d6, d13, d1
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5ee08b1e		cmgt d30, d24, #0
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e3b3734		cmgt v20.16b, v25.16b, v27.16b
+#   v20: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e208b20		cmgt v0.16b, v25.16b, #0
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ee13736		cmgt v22.2d, v25.2d, v1.2d
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ee08a10		cmgt v16.2d, v16.2d, #0
+#   v16: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0eaf3525		cmgt v5.2s, v9.2s, v15.2s
+#    v5: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  0ea08a4c		cmgt v12.2s, v18.2s, #0
+#   v12: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e6b365c		cmgt v28.4h, v18.4h, v11.4h
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e608876		cmgt v22.4h, v3.4h, #0
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ebb3565		cmgt v5.4s, v11.4s, v27.4s
+#    v5: 0x0000000000000000ffffffff00000000
+0x~~~~~~~~~~~~~~~~  4ea08a8d		cmgt v13.4s, v20.4s, #0
+#   v13: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e2737fb		cmgt v27.8b, v31.8b, v7.8b
+#   v27: 0x0000000000000000000000ffffffffff
+0x~~~~~~~~~~~~~~~~  0e208805		cmgt v5.8b, v0.8b, #0
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e6d3796		cmgt v22.8h, v28.8h, v13.8h
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e608846		cmgt v6.8h, v2.8h, #0
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7ef63515		cmhi d21, d8, d22
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e333672		cmhi v18.16b, v19.16b, v19.16b
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ef53407		cmhi v7.2d, v0.2d, v21.2d
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2ea0366f		cmhi v15.2s, v19.2s, v0.2s
+#   v15: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  2e6c34ff		cmhi v31.4h, v7.4h, v12.4h
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6eb63609		cmhi v9.4s, v16.4s, v22.4s
+#    v9: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e3c3707		cmhi v7.8b, v24.8b, v28.8b
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e79354b		cmhi v11.8h, v10.8h, v25.8h
+#   v11: 0x0000000000000000ffffffff00000000
+0x~~~~~~~~~~~~~~~~  7ef13d81		cmhs d1, d12, d17
+#    v1: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e3e3f35		cmhs v21.16b, v25.16b, v30.16b
+#   v21: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  6efa3c48		cmhs v8.2d, v2.2d, v26.2d
+#    v8: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  2ebd3ec1		cmhs v1.2s, v22.2s, v29.2s
+#    v1: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e7e3fda		cmhs v26.4h, v30.4h, v30.4h
+#   v26: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  6eb03e93		cmhs v19.4s, v20.4s, v16.4s
+#   v19: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  2e3a3c61		cmhs v1.8b, v3.8b, v26.8b
+#    v1: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e683f94		cmhs v20.8h, v28.8h, v8.8h
+#   v20: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7ee09b1e		cmle d30, d24, #0
+#   v30: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  6e209860		cmle v0.16b, v3.16b, #0
+#    v0: 0xffffffff00ffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  6ee09bc2		cmle v2.2d, v30.2d, #0
+#    v2: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  2ea09947		cmle v7.2s, v10.2s, #0
+#    v7: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  2e609be9		cmle v9.4h, v31.4h, #0
+#    v9: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  6ea09a49		cmle v9.4s, v18.4s, #0
+#    v9: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  2e209bf5		cmle v21.8b, v31.8b, #0
+#   v21: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  6e609abd		cmle v29.8h, v21.8h, #0
+#   v29: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  5ee0aaf9		cmlt d25, d23, #0
+#   v25: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4e20aaa7		cmlt v7.16b, v21.16b, #0
+#    v7: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4ee0abc7		cmlt v7.2d, v30.2d, #0
+#    v7: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  0ea0ab99		cmlt v25.2s, v28.2s, #0
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e60a960		cmlt v0.4h, v11.4h, #0
+#    v0: 0x0000000000000000ffffffff00000000
+0x~~~~~~~~~~~~~~~~  4ea0a8b8		cmlt v24.4s, v5.4s, #0
+#   v24: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e20a97a		cmlt v26.8b, v11.8b, #0
+#   v26: 0x0000000000000000ffffffff00000000
+0x~~~~~~~~~~~~~~~~  4e60aaa1		cmlt v1.8h, v21.8h, #0
+#    v1: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  5efe8efc		cmtst d28, d23, d30
+#   v28: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4e3f8cda		cmtst v26.16b, v6.16b, v31.16b
+#   v26: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ee48ea1		cmtst v1.2d, v21.2d, v4.2d
+#    v1: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0eb48f5b		cmtst v27.2s, v26.2s, v20.2s
+#   v27: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e728c1a		cmtst v26.4h, v0.4h, v18.4h
+#   v26: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ea48e19		cmtst v25.4s, v16.4s, v4.4s
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e298d4b		cmtst v11.8b, v10.8b, v9.8b
+#   v11: 0x0000000000000000ff00ffffffff0000
+0x~~~~~~~~~~~~~~~~  4e618c40		cmtst v0.8h, v2.8h, v1.8h
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e2059f9		cnt v25.16b, v15.16b
+#   v25: 0x00000000000000000000000008080808
+0x~~~~~~~~~~~~~~~~  0e2058dc		cnt v28.8b, v6.8b
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e0f04e6		dup v6.16b, v7.b[7]
+#    v6: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4e010e89		dup v9.16b, w20
+#    v9: 0x01010101010101010101010101010101
+0x~~~~~~~~~~~~~~~~  4e1805ac		dup v12.2d, v13.d[1]
+#   v12: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e080fe9		dup v9.2d, xzr
+#    v9: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e140744		dup v4.2s, v26.s[2]
+#    v4: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e040d83		dup v3.2s, w12
+#    v3: 0x0000000000000000ffffff7dffffff7d
+0x~~~~~~~~~~~~~~~~  0e1e04b6		dup v22.4h, v5.h[7]
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e020f30		dup v16.4h, w25
+#   v16: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e140554		dup v20.4s, v10.s[2]
+#   v20: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e040cea		dup v10.4s, w7
+#   v10: 0x00000018000000180000001800000018
+0x~~~~~~~~~~~~~~~~  0e0507de		dup v30.8b, v30.b[2]
+#   v30: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  0e010dff		dup v31.8b, w15
+#   v31: 0x00000000000000000101010101010101
+0x~~~~~~~~~~~~~~~~  4e12063c		dup v28.8h, v17.h[4]
+#   v28: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4e020c62		dup v2.8h, w3
+#    v2: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e231f3d		eor v29.16b, v25.16b, v3.16b
+#   v29: 0x0000000000000000ffffff7df7f7f775
+0x~~~~~~~~~~~~~~~~  2e3c1e03		eor v3.8b, v16.8b, v28.8b
+#    v3: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  6e060b41		ext v1.16b, v26.16b, v6.16b, #1
+#    v1: 0xff000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e010bc2		ext v2.8b, v30.8b, v1.8b, #1
+#    v2: 0x000000000000000000ffffffffffffff
+0x~~~~~~~~~~~~~~~~  4c402012		ld1 {v18.16b, v19.16b, v20.16b, v21.16b}, [x0]
+#   v18: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x2f2e2d2c2b2a29282726252423222120 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x3f3e3d3c3b3a39383736353433323130 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc22037		ld1 {v23.16b, v24.16b, v25.16b, v26.16b}, [x1], x2
+#   v23: 0xdbdad9d8d7d6d5d4d3d2d1d0cfce0001 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0xebeae9e8e7e6e5e4e3e2e1e0dfdedddc <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0xfbfaf9f8f7f6f5f4f3f2f1f0efeeedec <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0b0a09080706050403020100fffefdfc <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf2025		ld1 {v5.16b, v6.16b, v7.16b, v8.16b}, [x1], #64
+#    v5: 0xdad9d8d7d6d5d4d3d2d1d0cfcecdcccb <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0xeae9e8e7e6e5e4e3e2e1e0dfdedddcdb <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0xfaf9f8f7f6f5f4f3f2f1f0efeeedeceb <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0a09080706050403020100fffefdfcfb <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c406012		ld1 {v18.16b, v19.16b, v20.16b}, [x0]
+#   v18: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x2f2e2d2c2b2a29282726252423222120 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc2602d		ld1 {v13.16b, v14.16b, v15.16b}, [x1], x2
+#   v13: 0x1a191817161514131211100f0e0d0c0b <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x2a292827262524232221201f1e1d1c1b <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x3a393837363534333231302f2e2d2c2b <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf6033		ld1 {v19.16b, v20.16b, v21.16b}, [x1], #48
+#   v19: 0x191817161514131211100f0e0d0c0b0a <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x292827262524232221201f1e1d1c1b1a <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x393837363534333231302f2e2d2c2b2a <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c40a011		ld1 {v17.16b, v18.16b}, [x0]
+#   v17: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc2a034		ld1 {v20.16b, v21.16b}, [x1], x2
+#   v20: 0x494847464544434241403f3e3d3c3b3a <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x595857565554535251504f4e4d4c4b4a <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdfa03c		ld1 {v28.16b, v29.16b}, [x1], #32
+#   v28: 0x4847464544434241403f3e3d3c3b3a39 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x5857565554535251504f4e4d4c4b4a49 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c40701d		ld1 {v29.16b}, [x0]
+#   v29: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc27035		ld1 {v21.16b}, [x1], x2
+#   v21: 0x6867666564636261605f5e5d5c5b5a59 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf7024		ld1 {v4.16b}, [x1], #16
+#    v4: 0x67666564636261605f5e5d5c5b5a5958 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c402c04		ld1 {v4.1d, v5.1d, v6.1d, v7.1d}, [x0]
+#    v4: 0x0000000000000000ff0000850002ff01 (d4: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x00000000000000000000000000fffeff (d5: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000001700000000000000 (d6: 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000001f1e1d1c1b1a1918 (d7: 8.56775e-159) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc22c31		ld1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x1], x2
+#   v17: 0x00000000000000006f6e6d6c6b6a6968 (d17: 5.76650e+228) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000007776757473727170 (d18: 2.89670e+267) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000007f7e7d7c7b7a7978 (d19: 1.33818e+306) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x00000000000000008786858483828180 (d20: -2.08158e-272) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf2c3c		ld1 {v28.1d, v29.1d, v30.1d, v31.1d}, [x1], #32
+#   v28: 0x00000000000000006e6d6c6b6a696867 (d28: 8.50866e+223) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000000000767574737271706f (d29: 4.22243e+262) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x00000000000000007e7d7c7b7a797877 (d30: 1.97467e+301) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x0000000000000000868584838281807f (d31: -3.03465e-277) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c406c14		ld1 {v20.1d, v21.1d, v22.1d}, [x0]
+#   v20: 0x0000000000000000ff0000850002ff01 (d20: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x00000000000000000000000000fffeff (d21: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x00000000000000001700000000000000 (d22: 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc26c33		ld1 {v19.1d, v20.1d, v21.1d}, [x1], x2
+#   v19: 0x00000000000000008e8d8c8b8a898887 (d19: -1.41807e-238) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x0000000000000000969594939291908f (d20: -7.04826e-200) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x00000000000000009e9d9c9b9a999897 (d21: -3.29099e-161) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf6c2c		ld1 {v12.1d, v13.1d, v14.1d}, [x1], #24
+#   v12: 0x00000000000000008d8c8b8a89888786 (d12: -2.09028e-243) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x00000000000000009594939291908f8e (d13: -1.02545e-204) <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x00000000000000009d9c9b9a99989796 (d14: -4.85140e-166) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c40ac1d		ld1 {v29.1d, v30.1d}, [x0]
+#   v29: 0x0000000000000000ff0000850002ff01 (d29: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x00000000000000000000000000fffeff (d30: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc2ac3f		ld1 {v31.1d, v0.1d}, [x1], x2
+#   v31: 0x0000000000000000a5a4a3a2a1a09f9e (d31: -2.38202e-127) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x0000000000000000adacabaaa9a8a7a6 (d0: -1.12597e-88) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdfac23		ld1 {v3.1d, v4.1d}, [x1], #16
+#    v3: 0x0000000000000000a4a3a2a1a09f9e9d (d3: -3.45787e-132) <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000acabaaa9a8a7a6a5 (d4: -1.65794e-93) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c407c1c		ld1 {v28.1d}, [x0]
+#   v28: 0x0000000000000000ff0000850002ff01 (d28: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc27c2b		ld1 {v11.1d}, [x1], x2
+#   v11: 0x0000000000000000b4b3b2b1b0afaead (d11: -8.03348e-55) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf7c3d		ld1 {v29.1d}, [x1], #8
+#   v29: 0x0000000000000000b3b2b1b0afaeadac (d29: -1.16334e-59) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c402c1c		ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0]
+#   v28: 0x0000000000fffeffff0000850002ff01 (8.28892e-317, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x1f1e1d1c1b1a19181700000000000000 (8.56775e-159, 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x2f2e2d2c2b2a29282726252423222120 (1.98829e-81, 4.28794e-120) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x3f3e3d3c3b3a39383736353433323130 (0.000461414, 9.95833e-43) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc22c28		ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x1], x2
+#    v8: 0xc3c2c1c0bfbebdbcbbbab9b8b7b6b5b4 (-2.70315e+18, -5.65934e-21) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0xd3d2d1d0cfcecdcccbcac9c8c7c6c5c4 (-6.28100e+95, -1.31369e+57) <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0xe3e2e1e0dfdedddcdbdad9d8d7d6d5d4 (-1.45943e+173, -3.04943e+134) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0xf3f2f1f0efeeedecebeae9e8e7e6e5e4 (-3.39104e+250, -7.07849e+211) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf2c2e		ld1 {v14.2d, v15.2d, v16.2d, v17.2d}, [x1], #64
+#   v14: 0xc2c1c0bfbebdbcbbbab9b8b7b6b5b4b3 (-3.90391e+13, -8.31108e-26) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0xd2d1d0cfcecdcccbcac9c8c7c6c5c4c3 (-9.07279e+90, -1.92941e+52) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0xe2e1e0dfdedddcdbdad9d8d7d6d5d4d3 (-2.10851e+168, -4.47908e+129) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0xf2f1f0efeeedecebeae9e8e7e6e5e4e3 (-4.90012e+245, -1.03980e+207) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c406c1a		ld1 {v26.2d, v27.2d, v28.2d}, [x0]
+#   v26: 0x0000000000fffeffff0000850002ff01 (8.28892e-317, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x1f1e1d1c1b1a19181700000000000000 (8.56775e-159, 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x2f2e2d2c2b2a29282726252423222120 (1.98829e-81, 4.28794e-120) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc26c25		ld1 {v5.2d, v6.2d, v7.2d}, [x1], x2
+#    v5: 0x020100fffefdfcfbfaf9f8f7f6f5f4f3 (5.07812e-299, -2.41385e+284) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x1211100f0e0d0c0b0a09080706050403 (1.18008e-221, 2.54377e-260) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x2221201f1e1d1c1b1a19181716151413 (2.74293e-144, 5.90574e-183) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf6c3a		ld1 {v26.2d, v27.2d, v28.2d}, [x1], #48
+#   v26: 0x0100fffefdfcfbfaf9f8f7f6f5f4f3f2 (7.74681e-304, -3.54087e+279) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x11100f0e0d0c0b0a0908070605040302 (1.69471e-226, 3.72581e-265) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x21201f1e1d1c1b1a1918171615141312 (3.94003e-149, 8.65093e-188) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c40ac12		ld1 {v18.2d, v19.2d}, [x0]
+#   v18: 0x0000000000fffeffff0000850002ff01 (8.28892e-317, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x1f1e1d1c1b1a19181700000000000000 (8.56775e-159, 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc2ac35		ld1 {v21.2d, v22.2d}, [x1], x2
+#   v21: 0x31302f2e2d2c2b2a2928272625242322 (9.15999e-72, 2.00864e-110) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x41403f3e3d3c3b3a3938373635343332 (2.12953e+06, 4.66377e-33) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdfac31		ld1 {v17.2d, v18.2d}, [x1], #32
+#   v17: 0x302f2e2d2c2b2a292827262524232221 (1.34639e-76, 2.93754e-115) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x403f3e3d3c3b3a393837363534333231 (31.2431, 6.82132e-38) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c407c05		ld1 {v5.2d}, [x0]
+#    v5: 0x0000000000fffeffff0000850002ff01 (8.28892e-317, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc27c26		ld1 {v6.2d}, [x1], x2
+#    v6: 0x504f4e4d4c4b4a494847464544434241 (7.24994e+78, 1.58398e+40) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf7c2f		ld1 {v15.2d}, [x1], #16
+#   v15: 0x4f4e4d4c4b4a49484746454443424140 (1.07078e+74, 2.31271e+35) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c40281e		ld1 {v30.2s, v31.2s, v0.2s, v1.2s}, [x0]
+#   v30: 0x0000000000000000ff0000850002ff01 (..., -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x00000000000000000000000000fffeff (..., 0.00000, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x00000000000000001700000000000000 (..., 4.13590e-25, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x00000000000000001f1e1d1c1b1a1918 (..., 3.34819e-20, 1.27467e-22) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc22838		ld1 {v24.2s, v25.2s, v26.2s, v27.2s}, [x1], x2
+#   v24: 0x00000000000000005756555453525150 (..., 2.35662e+14, 9.03307e+11) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x00000000000000005f5e5d5c5b5a5958 (..., 1.60231e+19, 6.14598e+16) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000006766656463626160 (..., 1.08801e+24, 4.17598e+21) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x00000000000000006f6e6d6c6b6a6968 (..., 7.37897e+28, 2.83386e+26) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf283b		ld1 {v27.2s, v28.2s, v29.2s, v30.2s}, [x1], #32
+#   v27: 0x0000000000000000565554535251504f (..., 5.86395e+13, 2.24749e+11) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x00000000000000005e5d5c5b5a595857 (..., 3.98768e+18, 1.52943e+16) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000000000666564636261605f (..., 2.70818e+23, 1.03937e+21) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x00000000000000006e6d6c6b6a696867 (..., 1.83698e+28, 7.05432e+25) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c40680b		ld1 {v11.2s, v12.2s, v13.2s}, [x0]
+#   v11: 0x0000000000000000ff0000850002ff01 (..., -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x00000000000000000000000000fffeff (..., 0.00000, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x00000000000000001700000000000000 (..., 4.13590e-25, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc26828		ld1 {v8.2s, v9.2s, v10.2s}, [x1], x2
+#    v8: 0x0000000000000000767574737271706f (..., 1.24460e+33, 4.78220e+30) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000007e7d7c7b7a797877 (..., 8.42353e+37, 3.23831e+35) <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x0000000000000000868584838281807f (..., -5.02237e-35, -1.90286e-37) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf683f		ld1 {v31.2s, v0.2s, v1.2s}, [x1], #24
+#   v31: 0x00000000000000007574737271706f6e (..., 3.09878e+32, 1.19058e+30) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x00000000000000007d7c7b7a79787776 (..., 2.09754e+37, 8.06320e+34) <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x00000000000000008584838281807f7e (..., -1.24615e-35, -4.72027e-38) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c40a800		ld1 {v0.2s, v1.2s}, [x0]
+#    v0: 0x0000000000000000ff0000850002ff01 (..., -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x00000000000000000000000000fffeff (..., 0.00000, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc2a82d		ld1 {v13.2s, v14.2s}, [x1], x2
+#   v13: 0x00000000000000008d8c8b8a89888786 (..., -8.66176e-31, -3.28683e-33) <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x00000000000000009594939291908f8e (..., -6.00095e-26, -2.28077e-28) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdfa823		ld1 {v3.2s, v4.2s}, [x1], #16
+#    v3: 0x00000000000000008c8b8a8988878685 (..., -2.14997e-31, -8.15664e-34) <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x000000000000000094939291908f8e8d (..., -1.49010e-26, -5.66232e-29) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c40781a		ld1 {v26.2s}, [x0]
+#   v26: 0x0000000000000000ff0000850002ff01 (..., -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc27820		ld1 {v0.2s}, [x1], x2
+#    v0: 0x00000000000000009c9b9a9998979695 (..., -1.02970e-21, -3.91846e-24) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf782b		ld1 {v11.2s}, [x1], #8
+#   v11: 0x00000000000000009b9a999897969594 (..., -2.55764e-22, -9.73128e-25) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c402410		ld1 {v16.4h, v17.4h, v18.4h, v19.4h}, [x0]
+#   v16: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000001700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000001f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc22438		ld1 {v24.4h, v25.4h, v26.4h, v27.4h}, [x1], x2
+#   v24: 0x0000000000000000a3a2a1a09f9e9d9c <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x0000000000000000abaaa9a8a7a6a5a4 <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0000000000000000b3b2b1b0afaeadac <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000bbbab9b8b7b6b5b4 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf2421		ld1 {v1.4h, v2.4h, v3.4h, v4.4h}, [x1], #32
+#    v1: 0x0000000000000000a2a1a09f9e9d9c9b <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000000000aaa9a8a7a6a5a4a3 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000b2b1b0afaeadacab <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000bab9b8b7b6b5b4b3 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c40641e		ld1 {v30.4h, v31.4h, v0.4h}, [x0]
+#   v30: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x00000000000000001700000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc26439		ld1 {v25.4h, v26.4h, v27.4h}, [x1], x2
+#   v25: 0x0000000000000000c2c1c0bfbebdbcbb <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0000000000000000cac9c8c7c6c5c4c3 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000d2d1d0cfcecdcccb <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf6423		ld1 {v3.4h, v4.4h, v5.4h}, [x1], #24
+#    v3: 0x0000000000000000c1c0bfbebdbcbbba <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000c9c8c7c6c5c4c3c2 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x0000000000000000d1d0cfcecdcccbca <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c40a403		ld1 {v3.4h, v4.4h}, [x0]
+#    v3: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc2a423		ld1 {v3.4h, v4.4h}, [x1], x2
+#    v3: 0x0000000000000000d9d8d7d6d5d4d3d2 <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000e1e0dfdedddcdbda <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdfa437		ld1 {v23.4h, v24.4h}, [x1], #16
+#   v23: 0x0000000000000000d8d7d6d5d4d3d2d1 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x0000000000000000e0dfdedddcdbdad9 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c40741a		ld1 {v26.4h}, [x0]
+#   v26: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc27421		ld1 {v1.4h}, [x1], x2
+#    v1: 0x0000000000000000e8e7e6e5e4e3e2e1 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf742e		ld1 {v14.4h}, [x1], #8
+#   v14: 0x0000000000000000e7e6e5e4e3e2e1e0 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c40281a		ld1 {v26.4s, v27.4s, v28.4s, v29.4s}, [x0]
+#   v26: 0x0000000000fffeffff0000850002ff01 (0.00000, 2.35095e-38, -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x1f1e1d1c1b1a19181700000000000000 (3.34819e-20, 1.27467e-22, 4.13590e-25, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x2f2e2d2c2b2a29282726252423222120 (1.58413e-10, 6.04532e-13, 2.30573e-15, 8.78905e-18) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x3f3e3d3c3b3a39383736353433323130 (0.743122, 0.00284155, 1.08604e-05, 4.14886e-08) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc2283c		ld1 {v28.4s, v29.4s, v30.4s, v31.4s}, [x1], x2
+#   v28: 0xf7f6f5f4f3f2f1f0efeeedecebeae9e8 (-1.00179e+34, -3.84962e+31, -1.47890e+29, -5.67986e+26) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0706050403020100fffefdfcfbfaf9f8 (1.00825e-34, 3.82047e-37, -nan, -2.60629e+36) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x17161514131211100f0e0d0c0b0a0908 (4.84942e-25, 1.84362e-27, 7.00365e-30, 2.65846e-32) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x27262524232221201f1e1d1c1b1a1918 (2.30573e-15, 8.78905e-18, 3.34819e-20, 1.27467e-22) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf2824		ld1 {v4.4s, v5.4s, v6.4s, v7.4s}, [x1], #64
+#    v4: 0xf6f5f4f3f2f1f0efeeedecebeae9e8e7 (-2.49430e+33, -9.58428e+30, -3.68172e+28, -1.41390e+26) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x06050403020100fffefdfcfbfaf9f8f7 (2.50175e-35, 9.47771e-38, -1.68804e+38, -6.48966e+35) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x161514131211100f0e0d0c0b0a090807 (1.20425e-25, 4.57737e-28, 1.73854e-30, 6.59782e-33) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x262524232221201f1e1d1c1b1a191817 (5.72948e-16, 2.18366e-18, 8.31732e-21, 3.16591e-23) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c406802		ld1 {v2.4s, v3.4s, v4.4s}, [x0]
+#    v2: 0x0000000000fffeffff0000850002ff01 (0.00000, 2.35095e-38, -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x1f1e1d1c1b1a19181700000000000000 (3.34819e-20, 1.27467e-22, 4.13590e-25, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x2f2e2d2c2b2a29282726252423222120 (1.58413e-10, 6.04532e-13, 2.30573e-15, 8.78905e-18) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc26836		ld1 {v22.4s, v23.4s, v24.4s}, [x1], x2
+#   v22: 0x363534333231302f2e2d2c2b2a292827 (2.70015e-06, 1.03137e-08, 3.93749e-11, 1.50241e-13) <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x464544434241403f3e3d3c3b3a393837 (12625.1, 48.3127, 0.184800, 0.000706557) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x565554535251504f4e4d4c4b4a494847 (5.86395e+13, 2.24749e+11, 8.61082e+08, 3.29781e+06) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf682f		ld1 {v15.4s, v16.4s, v17.4s}, [x1], #48
+#   v15: 0x3534333231302f2e2d2c2b2a29282726 (6.71297e-07, 2.56382e-09, 9.78665e-12, 3.73374e-14) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x4544434241403f3e3d3c3b3a39383736 (3140.20, 12.0154, 0.0459549, 0.000175682) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x5554535251504f4e4d4c4b4a49484746 (1.45909e+13, 5.59177e+10, 2.14218e+08, 820340.) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c40a814		ld1 {v20.4s, v21.4s}, [x0]
+#   v20: 0x0000000000fffeffff0000850002ff01 (0.00000, 2.35095e-38, -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x1f1e1d1c1b1a19181700000000000000 (3.34819e-20, 1.27467e-22, 4.13590e-25, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc2a83e		ld1 {v30.4s, v31.4s}, [x1], x2
+#   v30: 0x6564636261605f5e5d5c5b5a59585756 (6.74083e+22, 2.58684e+20, 9.92399e+17, 3.80591e+15) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x7574737271706f6e6d6c6b6a69686766 (3.09878e+32, 1.19058e+30, 4.57302e+27, 1.75599e+25) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdfa82b		ld1 {v11.4s, v12.4s}, [x1], #32
+#   v11: 0x64636261605f5e5d5c5b5a5958575655 (1.67780e+22, 6.43816e+19, 2.46969e+17, 9.47063e+14) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x74737271706f6e6d6c6b6a6968676665 (7.71514e+31, 2.96402e+29, 1.13840e+27, 4.37102e+24) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c40780f		ld1 {v15.4s}, [x0]
+#   v15: 0x0000000000fffeffff0000850002ff01 (0.00000, 2.35095e-38, -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc2782c		ld1 {v12.4s}, [x1], x2
+#   v12: 0x84838281807f7e7d7c7b7a7978777675 (-3.09178e-36, -1.17085e-38, 5.22300e+36, 2.00766e+34) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf7820		ld1 {v0.4s}, [x1], #16
+#    v0: 0x838281807f7e7d7c7b7a797877767574 (-7.67045e-37, 3.38275e+38, 1.30054e+36, 4.99878e+33) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c402011		ld1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x0]
+#   v17: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000001700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x00000000000000001f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc22025		ld1 {v5.8b, v6.8b, v7.8b, v8.8b}, [x1], x2
+#    v5: 0x00000000000000008b8a898887868584 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x0000000000000000939291908f8e8d8c <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000009b9a999897969594 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0000000000000000a3a2a1a09f9e9d9c <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf2029		ld1 {v9.8b, v10.8b, v11.8b, v12.8b}, [x1], #32
+#    v9: 0x00000000000000008a89888786858483 <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x00000000000000009291908f8e8d8c8b <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x00000000000000009a99989796959493 <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000000000a2a1a09f9e9d9c9b <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c406004		ld1 {v4.8b, v5.8b, v6.8b}, [x0]
+#    v4: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000001700000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc26022		ld1 {v2.8b, v3.8b, v4.8b}, [x1], x2
+#    v2: 0x0000000000000000aaa9a8a7a6a5a4a3 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000b2b1b0afaeadacab <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000bab9b8b7b6b5b4b3 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf602c		ld1 {v12.8b, v13.8b, v14.8b}, [x1], #24
+#   v12: 0x0000000000000000a9a8a7a6a5a4a3a2 <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x0000000000000000b1b0afaeadacabaa <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x0000000000000000b9b8b7b6b5b4b3b2 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c40a00a		ld1 {v10.8b, v11.8b}, [x0]
+#   v10: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc2a02b		ld1 {v11.8b, v12.8b}, [x1], x2
+#   v11: 0x0000000000000000c1c0bfbebdbcbbba <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000000000c9c8c7c6c5c4c3c2 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdfa03b		ld1 {v27.8b, v28.8b}, [x1], #16
+#   v27: 0x0000000000000000c0bfbebdbcbbbab9 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x0000000000000000c8c7c6c5c4c3c2c1 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c40701f		ld1 {v31.8b}, [x0]
+#   v31: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc2702a		ld1 {v10.8b}, [x1], x2
+#   v10: 0x0000000000000000d0cfcecdcccbcac9 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf703c		ld1 {v28.8b}, [x1], #8
+#   v28: 0x0000000000000000cfcecdcccbcac9c8 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c402405		ld1 {v5.8h, v6.8h, v7.8h, v8.8h}, [x0]
+#    v5: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x2f2e2d2c2b2a29282726252423222120 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x3f3e3d3c3b3a39383736353433323130 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc22422		ld1 {v2.8h, v3.8h, v4.8h, v5.8h}, [x1], x2
+#    v2: 0xdfdedddcdbdad9d8d7d6d5d4d3d2d1d0 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0xefeeedecebeae9e8e7e6e5e4e3e2e1e0 <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0xfffefdfcfbfaf9f8f7f6f5f4f3f2f1f0 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x0f0e0d0c0b0a09080706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf242a		ld1 {v10.8h, v11.8h, v12.8h, v13.8h}, [x1], #64
+#   v10: 0xdedddcdbdad9d8d7d6d5d4d3d2d1d0cf <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0xeeedecebeae9e8e7e6e5e4e3e2e1e0df <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0xfefdfcfbfaf9f8f7f6f5f4f3f2f1f0ef <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x0e0d0c0b0a09080706050403020100ff <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c40641a		ld1 {v26.8h, v27.8h, v28.8h}, [x0]
+#   v26: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x2f2e2d2c2b2a29282726252423222120 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc26423		ld1 {v3.8h, v4.8h, v5.8h}, [x1], x2
+#    v3: 0x1e1d1c1b1a191817161514131211100f <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x2e2d2c2b2a292827262524232221201f <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x3e3d3c3b3a393837363534333231302f <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf6431		ld1 {v17.8h, v18.8h, v19.8h}, [x1], #48
+#   v17: 0x1d1c1b1a191817161514131211100f0e <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x2d2c2b2a292827262524232221201f1e <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x3d3c3b3a393837363534333231302f2e <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c40a404		ld1 {v4.8h, v5.8h}, [x0]
+#    v4: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc2a435		ld1 {v21.8h, v22.8h}, [x1], x2
+#   v21: 0x4d4c4b4a494847464544434241403f3e <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x5d5c5b5a595857565554535251504f4e <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdfa424		ld1 {v4.8h, v5.8h}, [x1], #32
+#    v4: 0x4c4b4a494847464544434241403f3e3d <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x5c5b5a595857565554535251504f4e4d <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c407409		ld1 {v9.8h}, [x0]
+#    v9: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc2743b		ld1 {v27.8h}, [x1], x2
+#   v27: 0x6c6b6a696867666564636261605f5e5d <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf743a		ld1 {v26.8h}, [x1], #16
+#   v26: 0x6b6a696867666564636261605f5e5d5c <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d400413		ld1 {v19.b}[1], [x0]
+#   v19: 0x3d3c3b3a39383736353433323130012e <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dc20c2c		ld1 {v12.b}[3], [x1], x2
+#   v12: 0xfefdfcfbfaf9f8f7f6f5f4f36cf1f0ef <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4ddf103b		ld1 {v27.b}[12], [x1], #1
+#   v27: 0x6c6b6a6b6867666564636261605f5e5d <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d40840a		ld1 {v10.d}[1], [x0]
+#   v10: 0xff0000850002ff01d6d5d4d3d2d1d0cf (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dc2843a		ld1 {v26.d}[1], [x1], x2
+#   v26: 0x737271706f6e6d6c636261605f5e5d5c (1.28953e+248, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4ddf8427		ld1 {v7.d}[1], [x1], #8
+#    v7: 0x7271706f6e6d6c6b2726252423222120 (1.86056e+243, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d404813		ld1 {v19.h}[5], [x0]
+#   v19: 0x3d3c3b3aff013736353433323130012e <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dc2482a		ld1 {v10.h}[1], [x1], x2
+#   v10: 0xff0000850002ff01d6d5d4d37473d0cf <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4ddf4025		ld1 {v5.h}[4], [x1], #2
+#    v5: 0x5c5b5a595857737254535251504f4e4d <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d408015		ld1 {v21.s}[2], [x0]
+#   v21: 0x4d4c4b4a0002ff014544434241403f3e (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dc2802d		ld1 {v13.s}[2], [x1], x2
+#   v13: 0x0e0d0c0b7776757406050403020100ff (..., 4.99878e+33, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4ddf8021		ld1 {v1.s}[2], [x1], #4
+#    v1: 0x0000000076757473e8e7e6e5e4e3e2e1 (..., 1.24460e+33, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d40c002		ld1r {v2.16b}, [x0]
+#    v2: 0x01010101010101010101010101010101 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dc2c022		ld1r {v2.16b}, [x1], x2
+#    v2: 0x77777777777777777777777777777777 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4ddfc036		ld1r {v22.16b}, [x1], #1
+#   v22: 0x76767676767676767676767676767676 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d40cc19		ld1r {v25.1d}, [x0]
+#   v25: 0x0000000000000000ff0000850002ff01 (d25: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dc2cc29		ld1r {v9.1d}, [x1], x2
+#    v9: 0x00000000000000007e7d7c7b7a797877 (d9: 1.97467e+301) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0ddfcc37		ld1r {v23.1d}, [x1], #8
+#   v23: 0x00000000000000007d7c7b7a79787776 (d23: 2.91053e+296) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d40cc13		ld1r {v19.2d}, [x0]
+#   v19: 0xff0000850002ff01ff0000850002ff01 (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dc2cc35		ld1r {v21.2d}, [x1], x2
+#   v21: 0x8584838281807f7e8584838281807f7e (-4.41447e-282, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4ddfcc3e		ld1r {v30.2d}, [x1], #8
+#   v30: 0x84838281807f7e7d84838281807f7e7d (-6.40629e-287, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d40c818		ld1r {v24.2s}, [x0]
+#   v24: 0x00000000000000000002ff010002ff01 (s24: 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dc2c83a		ld1r {v26.2s}, [x1], x2
+#   v26: 0x00000000000000008887868588878685 (s26: -8.15664e-34) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0ddfc83c		ld1r {v28.2s}, [x1], #4
+#   v28: 0x00000000000000008786858487868584 (s28: -2.02406e-34) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d40c413		ld1r {v19.4h}, [x0]
+#   v19: 0x0000000000000000ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dc2c421		ld1r {v1.4h}, [x1], x2
+#    v1: 0x00000000000000008988898889888988 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0ddfc435		ld1r {v21.4h}, [x1], #2
+#   v21: 0x00000000000000008887888788878887 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d40c80f		ld1r {v15.4s}, [x0]
+#   v15: 0x0002ff010002ff010002ff010002ff01 (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dc2c835		ld1r {v21.4s}, [x1], x2
+#   v21: 0x8c8b8a898c8b8a898c8b8a898c8b8a89 (..., -2.14997e-31, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4ddfc837		ld1r {v23.4s}, [x1], #4
+#   v23: 0x8b8a89888b8a89888b8a89888b8a8988 (..., -5.33626e-32, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d40c01a		ld1r {v26.8b}, [x0]
+#   v26: 0x00000000000000000101010101010101 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dc2c02e		ld1r {v14.8b}, [x1], x2
+#   v14: 0x00000000000000008c8c8c8c8c8c8c8c <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0ddfc033		ld1r {v19.8b}, [x1], #1
+#   v19: 0x00000000000000008b8b8b8b8b8b8b8b <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d40c40d		ld1r {v13.8h}, [x0]
+#   v13: 0xff01ff01ff01ff01ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dc2c43e		ld1r {v30.8h}, [x1], x2
+#   v30: 0x8d8c8d8c8d8c8d8c8d8c8d8c8d8c8d8c <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4ddfc43b		ld1r {v27.8h}, [x1], #2
+#   v27: 0x8c8b8c8b8c8b8c8b8c8b8c8b8c8b8c8b <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c408015		ld2 {v21.16b, v22.16b}, [x0]
+#   v21: 0x1e1c1a18000000000000ffff00850201 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x1f1d1b1917000000000000feff0000ff <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc28035		ld2 {v21.16b, v22.16b}, [x1], x2
+#   v21: 0xaba9a7a5a3a19f9d9b99979593918f8d <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0xacaaa8a6a4a2a09e9c9a98969492908e <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf802c		ld2 {v12.16b, v13.16b}, [x1], #32
+#   v12: 0xaaa8a6a4a2a09e9c9a98969492908e8c <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0xaba9a7a5a3a19f9d9b99979593918f8d <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c408c0e		ld2 {v14.2d, v15.2d}, [x0]
+#   v14: 0x1700000000000000ff0000850002ff01 (6.68887e-198, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x1f1e1d1c1b1a19180000000000fffeff (8.56775e-159, 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc28c20		ld2 {v0.2d, v1.2d}, [x1], x2
+#    v0: 0xc3c2c1c0bfbebdbcb3b2b1b0afaeadac (-2.70315e+18, -1.16334e-59) <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0xcbcac9c8c7c6c5c4bbbab9b8b7b6b5b4 (-1.31369e+57, -5.65934e-21) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf8c2c		ld2 {v12.2d, v13.2d}, [x1], #32
+#   v12: 0xc2c1c0bfbebdbcbbb2b1b0afaeadacab (-3.90391e+13, -1.67978e-64) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0xcac9c8c7c6c5c4c3bab9b8b7b6b5b4b3 (-1.92941e+52, -8.31108e-26) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c40881b		ld2 {v27.2s, v28.2s}, [x0]
+#   v27: 0x000000000000000000fffeff0002ff01 (..., 2.35095e-38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x000000000000000000000000ff000085 (..., 0.00000, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc28822		ld2 {v2.2s, v3.2s}, [x1], x2
+#    v2: 0x0000000000000000d6d5d4d3cecdcccb (..., -1.17555e+14, -1.72638e+09) <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000dad9d8d7d2d1d0cf (..., -3.06592e+16, -4.50576e+11) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf882c		ld2 {v12.2s, v13.2s}, [x1], #16
+#   v12: 0x0000000000000000d5d4d3d2cdcccbca (..., -2.92508e+13, -4.29488e+08) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x0000000000000000d9d8d7d6d1d0cfce (..., -7.62949e+15, -1.12105e+11) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c408409		ld2 {v9.4h, v10.4h}, [x0]
+#    v9: 0x00000000000000000000feff0085ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x0000000000000000000000ffff000002 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc28437		ld2 {v23.4h, v24.4h}, [x1], x2
+#   v23: 0x0000000000000000e7e6e3e2dfdedbda <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x0000000000000000e9e8e5e4e1e0dddc <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf8421		ld2 {v1.4h, v2.4h}, [x1], #16
+#    v1: 0x0000000000000000e6e5e2e1dedddad9 <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000000000e8e7e4e3e0dfdcdb <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c408814		ld2 {v20.4s, v21.4s}, [x0]
+#   v20: 0x1b1a19180000000000fffeff0002ff01 (1.27467e-22, 0.00000, 2.35095e-38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x1f1e1d1c1700000000000000ff000085 (3.34819e-20, 4.13590e-25, 0.00000, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc2882a		ld2 {v10.4s, v11.4s}, [x1], x2
+#   v10: 0x04030201fcfbfaf9f4f3f2f1ecebeae9 (1.53999e-36, -1.04669e+37, -1.54621e+32, -2.28166e+27) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x0807060500fffefdf8f7f6f5f0efeeed (4.06322e-34, 2.35095e-38, -4.02346e+34, -5.94046e+29) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf8838		ld2 {v24.4s, v25.4s}, [x1], #32
+#   v24: 0x03020100fbfaf9f8f3f2f1f0ebeae9e8 (3.82047e-37, -2.60629e+36, -3.84962e+31, -5.67986e+26) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x07060504fffefdfcf7f6f5f4efeeedec (1.00825e-34, -nan, -1.00179e+34, -1.47890e+29) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c408011		ld2 {v17.8b, v18.8b}, [x0]
+#   v17: 0x00000000000000000000ffff00850201 <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x0000000000000000000000feff0000ff <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc2802d		ld2 {v13.8b, v14.8b}, [x1], x2
+#   v13: 0x0000000000000000161412100e0c0a08 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x0000000000000000171513110f0d0b09 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf8027		ld2 {v7.8b, v8.8b}, [x1], #16
+#    v7: 0x00000000000000001513110f0d0b0907 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0000000000000000161412100e0c0a08 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c40841e		ld2 {v30.8h, v31.8h}, [x0]
+#   v30: 0x1d1c1918000000000000feff0085ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x1f1e1b1a17000000000000ffff000002 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc28424		ld2 {v4.8h, v5.8h}, [x1], x2
+#    v4: 0x3433302f2c2b28272423201f1c1b1817 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x363532312e2d2a29262522211e1d1a19 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf842d		ld2 {v13.8h, v14.8h}, [x1], #32
+#   v13: 0x33322f2e2b2a272623221f1e1b1a1716 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x353431302d2c2928252421201d1c1918 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d601005		ld2 {v5.b, v6.b}[12], [x0]
+#    v5: 0x363532012e2d2a29262522211e1d1a19 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x1f1e1dff1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0de21c30		ld2 {v16.b, v17.b}[7], [x1], x2
+#   v16: 0x4544434241403f3e363c3b3a39383736 <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000003700ffff00850201 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dff083d		ld2 {v29.b, v30.b}[2], [x1], #2
+#   v29: 0x0706050403020100fffefdfcfb35f9f8 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x1d1c1918000000000000feff0036ff01 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d60840b		ld2 {v11.d, v12.d}[1], [x0]
+#   v11: 0xff0000850002ff01f8f7f6f5f0efeeed (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000fffeffd5d4d3d2cdcccbca (8.28892e-317, ...) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0de2843a		ld2 {v26.d, v27.d}[0], [x1], x2
+#   v26: 0x00000000000000003e3d3c3b3a393837 (d26: 6.80687e-09) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000464544434241403f (d27: 3.36984e+30) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dff8439		ld2 {v25.d, v26.d}[0], [x1], #16
+#   v25: 0x07060504fffefdfc3d3c3b3a39383736 (d25: 1.00298e-13) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000004544434241403f3e (d26: 4.89923e+25) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d605812		ld2 {v18.h, v19.h}[7], [x0]
+#   v18: 0xff01000000000000000000feff0000ff <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00020000000000008b8b8b8b8b8b8b8b <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4de24831		ld2 {v17.h, v18.h}[5], [x1], x2
+#   v17: 0x00000000474600003700ffff00850201 <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0xff01000049480000000000feff0000ff <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dff503e		ld2 {v30.h, v31.h}[2], [x1], #4
+#   v30: 0x1d1c191800000000000046450036ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x1f1e1b1a1700000000004847ff000002 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d60901d		ld2 {v29.s, v30.s}[3], [x0]
+#   v29: 0x0002ff0103020100fffefdfcfb35f9f8 (2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0xff00008500000000000046450036ff01 (-1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0de2803c		ld2 {v28.s, v29.s}[0], [x1], x2
+#   v28: 0x0000000000000000000000004c4b4a49 (s28: 5.32913e+07) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0002ff0103020100fffefdfc504f4e4d (s29: 1.39121e+10) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dff9026		ld2 {v6.s, v7.s}[1], [x1], #8
+#    v6: 0x1f1e1dff1b1a19184b4a494800000000 (..., 1.32570e+07, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000004f4e4d4c0d0b0907 (..., 3.46117e+09, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d60c01a		ld2r {v26.16b, v27.16b}, [x0]
+#   v26: 0x01010101010101010101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0xffffffffffffffffffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4de2c035		ld2r {v21.16b, v22.16b}, [x1], x2
+#   v21: 0x50505050505050505050505050505050 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x51515151515151515151515151515151 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dffc025		ld2r {v5.16b, v6.16b}, [x1], #2
+#    v5: 0x4f4f4f4f4f4f4f4f4f4f4f4f4f4f4f4f <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x50505050505050505050505050505050 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d60cc1a		ld2r {v26.1d, v27.1d}, [x0]
+#   v26: 0x0000000000000000ff0000850002ff01 (d26: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x00000000000000000000000000fffeff (d27: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0de2cc2e		ld2r {v14.1d, v15.1d}, [x1], x2
+#   v14: 0x00000000000000005857565554535251 (d14: 3.67814e+117) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x0000000000000000605f5e5d5c5b5a59 (d15: 1.68234e+156) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dffcc37		ld2r {v23.1d, v24.1d}, [x1], #16
+#   v23: 0x00000000000000005756555453525150 (d23: 5.37096e+112) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00000000000000005f5e5d5c5b5a5958 (d24: 2.48489e+151) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d60cc0b		ld2r {v11.2d, v12.2d}, [x0]
+#   v11: 0xff0000850002ff01ff0000850002ff01 (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000fffeff0000000000fffeff (8.28892e-317, ...) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4de2cc3d		ld2r {v29.2d, v30.2d}, [x1], x2
+#   v29: 0x67666564636261606766656463626160 (1.24732e+190, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x6f6e6d6c6b6a69686f6e6d6c6b6a6968 (5.76650e+228, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dffcc2f		ld2r {v15.2d, v16.2d}, [x1], #16
+#   v15: 0x666564636261605f666564636261605f (1.81795e+185, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x6e6d6c6b6a6968676e6d6c6b6a696867 (8.50866e+223, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d60c81a		ld2r {v26.2s, v27.2s}, [x0]
+#   v26: 0x00000000000000000002ff010002ff01 (s26: 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000ff000085ff000085 (s27: -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0de2c836		ld2r {v22.2s, v23.2s}, [x1], x2
+#   v22: 0x00000000000000007271706f7271706f (s22: 4.78220e+30) <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x00000000000000007675747376757473 (s23: 1.24460e+33) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dffc822		ld2r {v2.2s, v3.2s}, [x1], #8
+#    v2: 0x000000000000000071706f6e71706f6e (s2: 1.19058e+30) <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x00000000000000007574737275747372 (s3: 3.09878e+32) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d60c402		ld2r {v2.4h, v3.4h}, [x0]
+#    v2: 0x0000000000000000ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x00000000000000000002000200020002 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0de2c429		ld2r {v9.4h, v10.4h}, [x1], x2
+#    v9: 0x00000000000000007776777677767776 <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x00000000000000007978797879787978 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dffc426		ld2r {v6.4h, v7.4h}, [x1], #4
+#    v6: 0x00000000000000007675767576757675 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000007877787778777877 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d60c807		ld2r {v7.4s, v8.4s}, [x0]
+#    v7: 0x0002ff010002ff010002ff010002ff01 (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0xff000085ff000085ff000085ff000085 (..., -1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4de2c833		ld2r {v19.4s, v20.4s}, [x1], x2
+#   v19: 0x7c7b7a797c7b7a797c7b7a797c7b7a79 (..., 5.22300e+36, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x807f7e7d807f7e7d807f7e7d807f7e7d (..., -1.17085e-38, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dffc835		ld2r {v21.4s, v22.4s}, [x1], #8
+#   v21: 0x7b7a79787b7a79787b7a79787b7a7978 (..., 1.30054e+36, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x7f7e7d7c7f7e7d7c7f7e7d7c7f7e7d7c (..., 3.38275e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d60c01a		ld2r {v26.8b, v27.8b}, [x0]
+#   v26: 0x00000000000000000101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000ffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0de2c034		ld2r {v20.8b, v21.8b}, [x1], x2
+#   v20: 0x00000000000000008080808080808080 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x00000000000000008181818181818181 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dffc02b		ld2r {v11.8b, v12.8b}, [x1], #2
+#   v11: 0x00000000000000007f7f7f7f7f7f7f7f <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x00000000000000008080808080808080 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d60c40c		ld2r {v12.8h, v13.8h}, [x0]
+#   v12: 0xff01ff01ff01ff01ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x00020002000200020002000200020002 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4de2c426		ld2r {v6.8h, v7.8h}, [x1], x2
+#    v6: 0x82818281828182818281828182818281 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x84838483848384838483848384838483 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dffc439		ld2r {v25.8h, v26.8h}, [x1], #4
+#   v25: 0x81808180818081808180818081808180 <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x83828382838283828382838283828382 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c404014		ld3 {v20.16b, v21.16b, v22.16b}, [x0]
+#   v20: 0x2d2a2724211e1b1800000000fe000001 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x2e2b2825221f1c1900000000ffff85ff <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x2f2c292623201d1a1700000000ff0002 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc2403c		ld3 {v28.16b, v29.16b, v30.16b}, [x1], x2
+#   v28: 0xb1aeaba8a5a29f9c999693908d8a8784 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0xb2afaca9a6a3a09d9a9794918e8b8885 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0xb3b0adaaa7a4a19e9b9895928f8c8986 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf4034		ld3 {v20.16b, v21.16b, v22.16b}, [x1], #48
+#   v20: 0xb0adaaa7a4a19e9b9895928f8c898683 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0xb1aeaba8a5a29f9c999693908d8a8784 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0xb2afaca9a6a3a09d9a9794918e8b8885 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c404c15		ld3 {v21.2d, v22.2d, v23.2d}, [x0]
+#   v21: 0x1f1e1d1c1b1a1918ff0000850002ff01 (8.56775e-159, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x27262524232221200000000000fffeff (4.28794e-120, 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x2f2e2d2c2b2a29281700000000000000 (1.98829e-81, 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc24c32		ld3 {v18.2d, v19.2d, v20.2d}, [x1], x2
+#   v18: 0xd2d1d0cfcecdcccbbab9b8b7b6b5b4b3 (-9.07279e+90, -8.31108e-26) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0xdad9d8d7d6d5d4d3c2c1c0bfbebdbcbb (-4.47908e+129, -3.90391e+13) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0xe2e1e0dfdedddcdbcac9c8c7c6c5c4c3 (-2.10851e+168, -1.92941e+52) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf4c3b		ld3 {v27.2d, v28.2d, v29.2d}, [x1], #48
+#   v27: 0xd1d0cfcecdcccbcab9b8b7b6b5b4b3b2 (-1.30639e+86, -1.21867e-30) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0xd9d8d7d6d5d4d3d2c1c0bfbebdbcbbba (-6.56908e+124, -5.62003e+08) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0xe1e0dfdedddcdbdac9c8c7c6c5c4c3c2 (-3.03668e+163, -2.82942e+47) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c404807		ld3 {v7.2s, v8.2s, v9.2s}, [x0]
+#    v7: 0x0000000000000000000000000002ff01 (..., 0.00000, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x000000000000000000000000ff000085 (..., 0.00000, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000001700000000fffeff (..., 4.13590e-25, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc24834		ld3 {v20.2s, v21.2s, v22.2s}, [x1], x2
+#   v20: 0x0000000000000000f1f0efeee5e4e3e2 (..., -2.38613e+30, -1.35113e+23) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x0000000000000000f5f4f3f2e9e8e7e6 (..., -6.21029e+32, -3.51957e+25) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x0000000000000000f9f8f7f6edecebea (..., -1.61590e+35, -9.16546e+27) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf483a		ld3 {v26.2s, v27.2s, v28.2s}, [x1], #24
+#   v26: 0x0000000000000000f0efeeede4e3e2e1 (..., -5.94046e+29, -3.36301e+22) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000f4f3f2f1e8e7e6e5 (..., -1.54621e+32, -8.76101e+24) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x0000000000000000f8f7f6f5ecebeae9 (..., -4.02346e+34, -2.28166e+27) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c40441b		ld3 {v27.4h, v28.4h, v29.4h}, [x0]
+#   v27: 0x000000000000000000000000ff00ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x000000000000000000000000feff0002 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x00000000000000001700000000ff0085 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc2443c		ld3 {v28.4h, v29.4h, v30.4h}, [x1], x2
+#   v28: 0x00000000000000000c0b060500fffaf9 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x00000000000000000e0d08070201fcfb <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x0000000000000000100f0a090403fefd <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf4427		ld3 {v7.4h, v8.4h, v9.4h}, [x1], #24
+#    v7: 0x00000000000000000b0a0504fffef9f8 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00000000000000000d0c07060100fbfa <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000000f0e09080302fdfc <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c404802		ld3 {v2.4s, v3.4s, v4.4s}, [x0]
+#    v2: 0x272625241b1a1918000000000002ff01 (2.30573e-15, 1.27467e-22, 0.00000, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x2b2a29281f1e1d1c00000000ff000085 (6.04532e-13, 3.34819e-20, 0.00000, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x2f2e2d2c232221201700000000fffeff (1.58413e-10, 8.78905e-18, 4.13590e-25, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc24838		ld3 {v24.4s, v25.4s, v26.4s}, [x1], x2
+#   v24: 0x373635342b2a29281f1e1d1c13121110 (1.08604e-05, 6.04532e-13, 3.34819e-20, 1.84362e-27) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x3b3a39382f2e2d2c2322212017161514 (0.00284155, 1.58413e-10, 8.78905e-18, 4.84942e-25) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x3f3e3d3c33323130272625241b1a1918 (0.743122, 4.14886e-08, 2.30573e-15, 1.27467e-22) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf482b		ld3 {v11.4s, v12.4s, v13.4s}, [x1], #48
+#   v11: 0x363534332a2928271e1d1c1b1211100f (2.70015e-06, 1.50241e-13, 8.31732e-21, 4.57737e-28) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x3a3938372e2d2c2b2221201f16151413 (0.000706557, 3.93749e-11, 2.18366e-18, 1.20425e-25) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x3e3d3c3b3231302f262524231a191817 (0.184800, 1.03137e-08, 5.72948e-16, 3.16591e-23) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c40401d		ld3 {v29.8b, v30.8b, v31.8b}, [x0]
+#   v29: 0x000000000000000000000000fe000001 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x000000000000000000000000ffff85ff <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x00000000000000001700000000ff0002 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc24021		ld3 {v1.8b, v2.8b, v3.8b}, [x1], x2
+#    v1: 0x000000000000000054514e4b4845423f <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x000000000000000055524f4c49464340 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x00000000000000005653504d4a474441 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf402c		ld3 {v12.8b, v13.8b, v14.8b}, [x1], #24
+#   v12: 0x000000000000000053504d4a4744413e <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x000000000000000054514e4b4845423f <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x000000000000000055524f4c49464340 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c404416		ld3 {v22.8h, v23.8h, v24.8h}, [x0]
+#   v22: 0x2b2a25241f1e191800000000ff00ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x2d2c272621201b1a00000000feff0002 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x2f2e292823221d1c1700000000ff0085 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc2442d		ld3 {v13.8h, v14.8h, v15.8h}, [x1], x2
+#   v13: 0x81807b7a75746f6e696863625d5c5756 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x83827d7c777671706b6a65645f5e5958 <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x85847f7e797873726d6c676661605b5a <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf443c		ld3 {v28.8h, v29.8h, v30.8h}, [x1], #48
+#   v28: 0x807f7a7974736e6d686762615c5b5655 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x82817c7b7675706f6a6964635e5d5857 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x84837e7d787772716c6b6665605f5a59 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d402c15		ld3 {v21.b, v22.b, v23.b}[11], [x0]
+#   v21: 0x0000000001000000f5f4f3f2e9e8e7e6 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x2b2a2524ff1e191800000000ff00ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x2d2c272602201b1a00000000feff0002 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dc22425		ld3 {v5.b, v6.b, v7.b}[9], [x1], x2
+#    v5: 0x4f4f4f4f4f4f854f4f4f4f4f4f4f4f4f <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x82818281828186818281828182818281 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000087000b0a0504fffef9f8 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0ddf2037		ld3 {v23.b, v24.b, v25.b}[0], [x1], #3
+#   v23: 0x2d2c272602201b1a00000000feff0084 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x2f2e292823221d1c1700000000ff0085 <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x3b3a39382f2e2d2c2322212017161586 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d40a410		ld3 {v16.d, v17.d, v18.d}[0], [x0]
+#   v16: 0x6e6d6c6b6a696867ff0000850002ff01 (d16: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000474600000000000000fffeff (d17: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0xd2d1d0cfcecdcccb1700000000000000 (d18: 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dc2a43e		ld3 {v30.d, v31.d, v0.d}[0], [x1], x2
+#   v30: 0x84837e7d787772718e8d8c8b8a898887 (d30: -1.41807e-238) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x0000000000000000969594939291908f (d31: -7.04826e-200) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0xc3c2c1c0bfbebdbc9e9d9c9b9a999897 (d0: -3.29099e-161) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4ddfa43c		ld3 {v28.d, v29.d, v30.d}[1], [x1], #24
+#   v28: 0x8d8c8b8a89888786686762615c5b5655 (-2.09028e-243, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x9594939291908f8e6a6964635e5d5857 (-1.02545e-204, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x9d9c9b9a999897968e8d8c8b8a898887 (-4.85140e-166, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d40700d		ld3 {v13.h, v14.h, v15.h}[2], [x0]
+#   v13: 0x81807b7a75746f6e6968ff015d5c5756 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x83827d7c777671706b6a00025f5e5958 <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x85847f7e797873726d6c008561605b5a <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dc27836		ld3 {v22.h, v23.h, v24.h}[7], [x1], x2
+#   v22: 0x9f9e2524ff1e191800000000ff00ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0xa1a0272602201b1a00000000feff0084 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0xa3a2292823221d1c1700000000ff0085 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0ddf782e		ld3 {v14.h, v15.h, v16.h}[3], [x1], #6
+#   v14: 0x83827d7c777671709e9d00025f5e5958 <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x85847f7e79787372a09f008561605b5a <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x6e6d6c6b6a696867a2a100850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d40b016		ld3 {v22.s, v23.s, v24.s}[3], [x0]
+#   v22: 0x0002ff01ff1e191800000000ff00ff01 (2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0xff00008502201b1a00000000feff0084 (-1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00fffeff23221d1c1700000000ff0085 (2.35095e-38, ...) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dc2a03e		ld3 {v30.s, v31.s, v0.s}[2], [x1], x2
+#   v30: 0x9d9c9b9aa6a5a4a38e8d8c8b8a898887 (..., -1.14938e-15, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x00000000aaa9a8a7969594939291908f (..., -3.01375e-13, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0xc3c2c1c0aeadacab9e9d9c9b9a999897 (..., -7.89780e-11, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0ddfb02c		ld3 {v12.s, v13.s, v14.s}[1], [x1], #12
+#   v12: 0x0000000000000000a5a4a3a24744413e (..., -2.85603e-16, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x81807b7a75746f6ea9a8a7a65d5c5756 (..., -7.48978e-14, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x83827d7c77767170adacabaa5f5e5958 (..., -1.96304e-11, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d40e018		ld3r {v24.16b, v25.16b, v26.16b}, [x0]
+#   v24: 0x01010101010101010101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0xffffffffffffffffffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x02020202020202020202020202020202 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dc2e038		ld3r {v24.16b, v25.16b, v26.16b}, [x1], x2
+#   v24: 0xaeaeaeaeaeaeaeaeaeaeaeaeaeaeaeae <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0xafafafafafafafafafafafafafafafaf <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0xb0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4ddfe023		ld3r {v3.16b, v4.16b, v5.16b}, [x1], #3
+#    v3: 0xadadadadadadadadadadadadadadadad <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0xaeaeaeaeaeaeaeaeaeaeaeaeaeaeaeae <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0xafafafafafafafafafafafafafafafaf <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d40ec04		ld3r {v4.1d, v5.1d, v6.1d}, [x0]
+#    v4: 0x0000000000000000ff0000850002ff01 (d4: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x00000000000000000000000000fffeff (d5: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000001700000000000000 (d6: 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dc2ec27		ld3r {v7.1d, v8.1d, v9.1d}, [x1], x2
+#    v7: 0x0000000000000000b7b6b5b4b3b2b1b0 (d7: -2.60696e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0000000000000000bfbebdbcbbbab9b8 (d8: -0.120083) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x0000000000000000c7c6c5c4c3c2c1c0 (d9: -6.05398e+37) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0ddfec31		ld3r {v17.1d, v18.1d, v19.1d}, [x1], #24
+#   v17: 0x0000000000000000b6b5b4b3b2b1b0af (d17: -3.80205e-45) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x0000000000000000bebdbcbbbab9b8b7 (d18: -1.77248e-06) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x0000000000000000c6c5c4c3c2c1c0bf (d19: -8.83040e+32) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d40ec10		ld3r {v16.2d, v17.2d, v18.2d}, [x0]
+#   v16: 0xff0000850002ff01ff0000850002ff01 (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x0000000000fffeff0000000000fffeff (8.28892e-317, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x17000000000000001700000000000000 (6.68887e-198, ...) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dc2ec34		ld3r {v20.2d, v21.2d, v22.2d}, [x1], x2
+#   v20: 0xcecdcccbcac9c8c7cecdcccbcac9c8c7 (-4.11344e+71, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0xd6d5d4d3d2d1d0cfd6d5d4d3d2d1d0cf (-2.05087e+110, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0xdedddcdbdad9d8d7dedddcdbdad9d8d7 (-9.54613e+148, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4ddfec2e		ld3r {v14.2d, v15.2d, v16.2d}, [x1], #24
+#   v14: 0xcdcccbcac9c8c7c6cdcccbcac9c8c7c6 (-6.06516e+66, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0xd5d4d3d2d1d0cfced5d4d3d2d1d0cfce (-2.98548e+105, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0xdddcdbdad9d8d7d6dddcdbdad9d8d7d6 (-1.40766e+144, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d40e80a		ld3r {v10.2s, v11.2s, v12.2s}, [x0]
+#   v10: 0x00000000000000000002ff010002ff01 (s10: 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x0000000000000000ff000085ff000085 (s11: -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x000000000000000000fffeff00fffeff (s12: 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dc2e820		ld3r {v0.2s, v1.2s, v2.2s}, [x1], x2
+#    v0: 0x0000000000000000e1e0dfdee1e0dfde (s0: -5.18525e+20) <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x0000000000000000e5e4e3e2e5e4e3e2 (s1: -1.35113e+23) <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000000000e9e8e7e6e9e8e7e6 (s2: -3.51957e+25) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0ddfe837		ld3r {v23.2s, v24.2s, v25.2s}, [x1], #12
+#   v23: 0x0000000000000000e0dfdedde0dfdedd (s23: -1.29053e+20) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x0000000000000000e4e3e2e1e4e3e2e1 (s24: -3.36301e+22) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x0000000000000000e8e7e6e5e8e7e6e5 (s25: -8.76101e+24) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d40e416		ld3r {v22.4h, v23.4h, v24.4h}, [x0]
+#   v22: 0x0000000000000000ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x00000000000000000002000200020002 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00000000000000000085008500850085 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dc2e426		ld3r {v6.4h, v7.4h, v8.4h}, [x1], x2
+#    v6: 0x0000000000000000eae9eae9eae9eae9 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x0000000000000000ecebecebecebeceb <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0000000000000000eeedeeedeeedeeed <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0ddfe427		ld3r {v7.4h, v8.4h, v9.4h}, [x1], #6
+#    v7: 0x0000000000000000e9e8e9e8e9e8e9e8 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0000000000000000ebeaebeaebeaebea <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x0000000000000000edecedecedecedec <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d40e81a		ld3r {v26.4s, v27.4s, v28.4s}, [x0]
+#   v26: 0x0002ff010002ff010002ff010002ff01 (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0xff000085ff000085ff000085ff000085 (..., -1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x00fffeff00fffeff00fffeff00fffeff (..., 2.35095e-38, ...) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dc2e820		ld3r {v0.4s, v1.4s, v2.4s}, [x1], x2
+#    v0: 0xf1f0efeef1f0efeef1f0efeef1f0efee (..., -2.38613e+30, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0xf5f4f3f2f5f4f3f2f5f4f3f2f5f4f3f2 (..., -6.21029e+32, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0xf9f8f7f6f9f8f7f6f9f8f7f6f9f8f7f6 (..., -1.61590e+35, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4ddfe83e		ld3r {v30.4s, v31.4s, v0.4s}, [x1], #12
+#   v30: 0xf0efeeedf0efeeedf0efeeedf0efeeed (..., -5.94046e+29, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0xf4f3f2f1f4f3f2f1f4f3f2f1f4f3f2f1 (..., -1.54621e+32, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0xf8f7f6f5f8f7f6f5f8f7f6f5f8f7f6f5 (..., -4.02346e+34, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d40e002		ld3r {v2.8b, v3.8b, v4.8b}, [x0]
+#    v2: 0x00000000000000000101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000ffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x00000000000000000202020202020202 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dc2e02a		ld3r {v10.8b, v11.8b, v12.8b}, [x1], x2
+#   v10: 0x0000000000000000f9f9f9f9f9f9f9f9 <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x0000000000000000fafafafafafafafa <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000000000fbfbfbfbfbfbfbfb <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0ddfe03c		ld3r {v28.8b, v29.8b, v30.8b}, [x1], #3
+#   v28: 0x0000000000000000f8f8f8f8f8f8f8f8 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000000000f9f9f9f9f9f9f9f9 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x0000000000000000fafafafafafafafa <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d40e406		ld3r {v6.8h, v7.8h, v8.8h}, [x0]
+#    v6: 0xff01ff01ff01ff01ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00020002000200020002000200020002 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00850085008500850085008500850085 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dc2e43d		ld3r {v29.8h, v30.8h, v31.8h}, [x1], x2
+#   v29: 0xfcfbfcfbfcfbfcfbfcfbfcfbfcfbfcfb <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0xfefdfefdfefdfefdfefdfefdfefdfefd <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x00ff00ff00ff00ff00ff00ff00ff00ff <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4ddfe427		ld3r {v7.8h, v8.8h, v9.8h}, [x1], #6
+#    v7: 0xfbfafbfafbfafbfafbfafbfafbfafbfa <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0xfdfcfdfcfdfcfdfcfdfcfdfcfdfcfdfc <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0xfffefffefffefffefffefffefffefffe <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c400003		ld4 {v3.16b, v4.16b, v5.16b, v6.16b}, [x0]
+#    v3: 0x3c3834302c2824201c18000000ff8501 <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x3d3935312d2925211d19000000fe00ff <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x3e3a36322e2a26221e1a000000ff0002 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x3f3b37332f2b27231f1b17000000ff00 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc20022		ld4 {v2.16b, v3.16b, v4.16b, v5.16b}, [x1], x2
+#    v2: 0x3c3834302c2824201c1814100c080400 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x3d3935312d2925211d1915110d090501 <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x3e3a36322e2a26221e1a16120e0a0602 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x3f3b37332f2b27231f1b17130f0b0703 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf0025		ld4 {v5.16b, v6.16b, v7.16b, v8.16b}, [x1], #64
+#    v5: 0x3b37332f2b27231f1b17130f0b0703ff <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x3c3834302c2824201c1814100c080400 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x3d3935312d2925211d1915110d090501 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x3e3a36322e2a26221e1a16120e0a0602 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c400c12		ld4 {v18.2d, v19.2d, v20.2d, v21.2d}, [x0]
+#   v18: 0x2726252423222120ff0000850002ff01 (4.28794e-120, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x2f2e2d2c2b2a29280000000000fffeff (1.98829e-81, 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x37363534333231301700000000000000 (9.95833e-43, 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x3f3e3d3c3b3a39381f1e1d1c1b1a1918 (0.000461414, 8.56775e-159) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc20c24		ld4 {v4.2d, v5.2d, v6.2d, v7.2d}, [x1], x2
+#    v4: 0x666564636261605f464544434241403f (1.81795e+185, 3.36984e+30) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x6e6d6c6b6a6968674e4d4c4b4a494847 (8.50866e+223, 1.57975e+69) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x767574737271706f565554535251504f (4.22243e+262, 7.82703e+107) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x7e7d7c7b7a7978775e5d5c5b5a595857 (1.97467e+301, 3.66628e+146) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf0c3d		ld4 {v29.2d, v30.2d, v31.2d, v0.2d}, [x1], #64
+#   v29: 0x6564636261605f5e4544434241403f3e (2.64379e+180, 4.89923e+25) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x6d6c6b6a696867664d4c4b4a49484746 (1.25402e+219, 2.32790e+64) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x7574737271706f6e5554535251504f4e (6.14144e+257, 1.13810e+103) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x7d7c7b7a797877765d5c5b5a59585756 (2.91053e+296, 5.40301e+141) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c40081b		ld4 {v27.2s, v28.2s, v29.2s, v30.2s}, [x0]
+#   v27: 0x0000000000000000000000000002ff01 (..., 0.00000, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x000000000000000017000000ff000085 (..., 4.13590e-25, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x00000000000000001b1a191800fffeff (..., 1.27467e-22, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x00000000000000001f1e1d1c00000000 (..., 3.34819e-20, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc20838		ld4 {v24.2s, v25.2s, v26.2s, v27.2s}, [x1], x2
+#   v24: 0x000000000000000091908f8e81807f7e (..., -2.28077e-28, -4.72027e-38) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x00000000000000009594939285848382 (..., -6.00095e-26, -1.24615e-35) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000009998979689888786 (..., -1.57777e-23, -3.28683e-33) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x00000000000000009d9c9b9a8d8c8b8a (..., -4.14537e-21, -8.66176e-31) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf0824		ld4 {v4.2s, v5.2s, v6.2s, v7.2s}, [x1], #32
+#    v4: 0x0000000000000000908f8e8d807f7e7d (..., -5.66232e-29, -1.17085e-38) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x00000000000000009493929184838281 (..., -1.49010e-26, -3.09178e-36) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000009897969588878685 (..., -3.91846e-24, -8.15664e-34) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000009c9b9a998c8b8a89 (..., -1.02970e-21, -2.14997e-31) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c400410		ld4 {v16.4h, v17.4h, v18.4h, v19.4h}, [x0]
+#   v16: 0x000000000000000019180000feffff01 <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000001b1a000000ff0002 <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000001d1c000000000085 <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000001f1e17000000ff00 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc20437		ld4 {v23.4h, v24.4h, v25.4h, v26.4h}, [x1], x2
+#   v23: 0x0000000000000000b6b5aeada6a59e9d <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x0000000000000000b8b7b0afa8a7a09f <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x0000000000000000bab9b2b1aaa9a2a1 <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0000000000000000bcbbb4b3acaba4a3 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf0422		ld4 {v2.4h, v3.4h, v4.4h, v5.4h}, [x1], #32
+#    v2: 0x0000000000000000b5b4adaca5a49d9c <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000b7b6afaea7a69f9e <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000b9b8b1b0a9a8a1a0 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x0000000000000000bbbab3b2abaaa3a2 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c400807		ld4 {v7.4s, v8.4s, v9.4s, v10.4s}, [x0]
+#    v7: 0x3332313023222120000000000002ff01 (4.14886e-08, 8.78905e-18, 0.00000, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x373635342726252417000000ff000085 (1.08604e-05, 2.30573e-15, 4.13590e-25, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x3b3a39382b2a29281b1a191800fffeff (0.00284155, 6.04532e-13, 1.27467e-22, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x3f3e3d3c2f2e2d2c1f1e1d1c00000000 (0.743122, 1.58413e-10, 3.34819e-20, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc2083c		ld4 {v28.4s, v29.4s, v30.4s, v31.4s}, [x1], x2
+#   v28: 0xefeeedecdfdedddccfcecdccbfbebdbc (-1.47890e+29, -3.21185e+19, -6.93919e+09, -1.49017) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0xf3f2f1f0e3e2e1e0d3d2d1d0c3c2c1c0 (-3.84962e+31, -8.37048e+21, -1.81093e+12, -389.514) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0xf7f6f5f4e7e6e5e4d7d6d5d4c7c6c5c4 (-1.00179e+34, -2.18077e+24, -4.72428e+14, -101772.) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0xfbfaf9f8ebeae9e8dbdad9d8cbcac9c8 (-2.60629e+36, -5.67986e+26, -1.23202e+17, -2.65799e+07) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf083d		ld4 {v29.4s, v30.4s, v31.4s, v0.4s}, [x1], #64
+#   v29: 0xeeedecebdedddcdbcecdcccbbebdbcbb (-3.68172e+28, -7.99345e+18, -1.72638e+09, -0.370581) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0xf2f1f0efe2e1e0dfd2d1d0cfc2c1c0bf (-9.58428e+30, -2.08336e+21, -4.50576e+11, -96.8765) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0xf6f5f4f3e6e5e4e3d6d5d4d3c6c5c4c3 (-2.49430e+33, -5.42822e+23, -1.17555e+14, -25314.4) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0xfaf9f8f7eae9e8e7dad9d8d7cac9c8c7 (-6.48966e+35, -1.41390e+26, -3.06592e+16, -6.61207e+06) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c40000f		ld4 {v15.8b, v16.8b, v17.8b, v18.8b}, [x0]
+#   v15: 0x00000000000000001c18000000ff8501 <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x00000000000000001d19000000fe00ff <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000001e1a000000ff0002 <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000001f1b17000000ff00 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cc2003b		ld4 {v27.8b, v28.8b, v29.8b, v30.8b}, [x1], x2
+#   v27: 0x000000000000000017130f0b0703fffb <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x00000000000000001814100c080400fc <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x00000000000000001915110d090501fd <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x00000000000000001a16120e0a0602fe <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0cdf0025		ld4 {v5.8b, v6.8b, v7.8b, v8.8b}, [x1], #32
+#    v5: 0x000000000000000016120e0a0602fefa <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x000000000000000017130f0b0703fffb <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000001814100c080400fc <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00000000000000001915110d090501fd <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c400419		ld4 {v25.8h, v26.8h, v27.8h, v28.8h}, [x0]
+#   v25: 0x393831302928212019180000feffff01 <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x3b3a33322b2a23221b1a000000ff0002 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x3d3c35342d2c25241d1c000000000085 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x3f3e37362f2e27261f1e17000000ff00 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cc20422		ld4 {v2.8h, v3.8h, v4.8h, v5.8h}, [x1], x2
+#    v2: 0x53524b4a43423b3a33322b2a23221b1a <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x55544d4c45443d3c35342d2c25241d1c <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x57564f4e47463f3e37362f2e27261f1e <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x59585150494841403938313029282120 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4cdf0434		ld4 {v20.8h, v21.8h, v22.8h, v23.8h}, [x1], #64
+#   v20: 0x52514a4942413a3932312a2922211a19 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x54534c4b44433c3b34332c2b24231c1b <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x56554e4d46453e3d36352e2d26251e1d <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x5857504f4847403f3837302f2827201f <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d602c14		ld4 {v20.b, v21.b, v22.b, v23.b}[3], [x0]
+#   v20: 0x52514a4942413a3932312a2901211a19 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x54534c4b44433c3b34332c2bff231c1b <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x56554e4d46453e3d36352e2d02251e1d <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x5857504f4847403f3837302f0027201f <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0de22c2c		ld4 {v12.b, v13.b, v14.b, v15.b}[3], [x1], x2
+#   v12: 0x0000000000000000fbfbfbfb59fbfbfb <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x81807b7a75746f6ea9a8a7a65a5c5756 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0xcdcccbcac9c8c7c6cdcccbca5bc8c7c6 <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x00000000000000001c1800005cff8501 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dff383b		ld4 {v27.b, v28.b, v29.b, v30.b}[6], [x1], #4
+#   v27: 0x3d3c35342d2c25241d58000000000085 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x3f3e37362f2e27261f5917000000ff00 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000000000195a110d090501fd <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x00000000000000001a5b120e0a0602fe <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d60a41c		ld4 {v28.d, v29.d, v30.d, v31.d}[1], [x0]
+#   v28: 0xff0000850002ff011f5917000000ff00 (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000fffeff195a110d090501fd (8.28892e-317, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x17000000000000001a5b120e0a0602fe (6.68887e-198, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x1f1e1d1c1b1a1918d6d5d4d3c6c5c4c3 (8.56775e-159, ...) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4de2a42f		ld4 {v15.d, v16.d, v17.d, v18.d}[1], [x1], x2
+#   v15: 0x636261605f5e5d5c1c1800005cff8501 (5.54935e+170, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x6b6a6968676665641d19000000fe00ff (2.71346e+209, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x737271706f6e6d6c1e1a000000ff0002 (1.28953e+248, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x7b7a7978777675741f1b17000000ff00 (6.29888e+286, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dffa430		ld4 {v16.d, v17.d, v18.d, v19.d}[1], [x1], #32
+#   v16: 0x6261605f5e5d5c5b1d19000000fe00ff (8.00514e+165, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x6a696867666564631e1a000000ff0002 (3.98304e+204, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x7271706f6e6d6c6b1f1b17000000ff00 (1.86056e+243, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x7a797877767574731f1e17000000ff00 (9.24687e+281, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d607002		ld4 {v2.h, v3.h, v4.h, v5.h}[6], [x0]
+#    v2: 0x5352ff0143423b3a33322b2a23221b1a <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x5554000245443d3c35342d2c25241d1c <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x5756008547463f3e37362f2e27261f1e <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x5958ff00494841403938313029282120 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0de27825		ld4 {v5.h, v6.h, v7.h, v8.h}[3], [x1], x2
+#    v5: 0x5958ff00494841407c7b313029282120 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000007e7d0f0b0703fffb <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x0000000000000000807f100c080400fc <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00000000000000008281110d090501fd <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dff7027		ld4 {v7.h, v8.h, v9.h, v10.h}[6], [x1], #8
+#    v7: 0x00007b7a00000000807f100c080400fc <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00007d7c000000008281110d090501fd <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x3b3a7f7e2b2a29281b1a191800fffeff <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x3f3e81802f2e2d2c1f1e1d1c00000000 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d60b006		ld4 {v6.s, v7.s, v8.s, v9.s}[1], [x0]
+#    v6: 0x00000000000000000002ff010703fffb (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00007b7a00000000ff000085080400fc (..., -1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00007d7c0000000000fffeff090501fd (..., 2.35095e-38, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x3b3a7f7e2b2a29280000000000fffeff (..., 0.00000, ...) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4de2a039		ld4 {v25.s, v26.s, v27.s, v28.s}[2], [x1], x2
+#   v25: 0x393831308584838219180000feffff01 (..., -1.24615e-35, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x3b3a3332898887861b1a000000ff0002 (..., -3.28683e-33, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x3d3c35348d8c8b8a1d58000000000085 (..., -8.66176e-31, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0xff00008591908f8e1f5917000000ff00 (..., -2.28077e-28, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dffb028		ld4 {v8.s, v9.s, v10.s, v11.s}[3], [x1], #16
+#    v8: 0x848382810000000000fffeff090501fd (-3.09178e-36, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x888786852b2a29280000000000fffeff (-8.15664e-34, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x8c8b8a892f2e2d2c1f1e1d1c00000000 (-2.14997e-31, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x908f8e8d00000000fafafafafafafafa (-5.66232e-29, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d60e00e		ld4r {v14.16b, v15.16b, v16.16b, v17.16b}, [x0]
+#   v14: 0x01010101010101010101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0xffffffffffffffffffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x02020202020202020202020202020202 <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4de2e02d		ld4r {v13.16b, v14.16b, v15.16b, v16.16b}, [x1], x2
+#   v13: 0x91919191919191919191919191919191 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x92929292929292929292929292929292 <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x93939393939393939393939393939393 <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x94949494949494949494949494949494 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dffe029		ld4r {v9.16b, v10.16b, v11.16b, v12.16b}, [x1], #4
+#    v9: 0x90909090909090909090909090909090 <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x91919191919191919191919191919191 <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x92929292929292929292929292929292 <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x93939393939393939393939393939393 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d60ec08		ld4r {v8.1d, v9.1d, v10.1d, v11.1d}, [x0]
+#    v8: 0x0000000000000000ff0000850002ff01 (d8: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000000000000000fffeff (d9: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x00000000000000001700000000000000 (d10: 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x00000000000000001f1e1d1c1b1a1918 (d11: 8.56775e-159) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0de2ec24		ld4r {v4.1d, v5.1d, v6.1d, v7.1d}, [x1], x2
+#    v4: 0x00000000000000009b9a999897969594 (d4: -1.05028e-175) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x0000000000000000a3a2a1a09f9e9d9c (d5: -5.00653e-137) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x0000000000000000abaaa9a8a7a6a5a4 (d6: -2.43801e-98) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x0000000000000000b3b2b1b0afaeadac (d7: -1.16334e-59) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dffec3a		ld4r {v26.1d, v27.1d, v28.1d, v29.1d}, [x1], #32
+#   v26: 0x00000000000000009a99989796959493 (d26: -1.54211e-180) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000a2a1a09f9e9d9c9b (d27: -7.22772e-142) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x0000000000000000aaa9a8a7a6a5a4a3 (d28: -3.58004e-103) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000000000b2b1b0afaeadacab (d29: -1.67978e-64) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d60ec13		ld4r {v19.2d, v20.2d, v21.2d, v22.2d}, [x0]
+#   v19: 0xff0000850002ff01ff0000850002ff01 (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x0000000000fffeff0000000000fffeff (8.28892e-317, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x17000000000000001700000000000000 (6.68887e-198, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x1f1e1d1c1b1a19181f1e1d1c1b1a1918 (8.56775e-159, ...) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4de2ec3c		ld4r {v28.2d, v29.2d, v30.2d, v31.2d}, [x1], x2
+#   v28: 0xbab9b8b7b6b5b4b3bab9b8b7b6b5b4b3 (-8.31108e-26, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0xc2c1c0bfbebdbcbbc2c1c0bfbebdbcbb (-3.90391e+13, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0xcac9c8c7c6c5c4c3cac9c8c7c6c5c4c3 (-1.92941e+52, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0xd2d1d0cfcecdcccbd2d1d0cfcecdcccb (-9.07279e+90, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dffec2f		ld4r {v15.2d, v16.2d, v17.2d, v18.2d}, [x1], #32
+#   v15: 0xb9b8b7b6b5b4b3b2b9b8b7b6b5b4b3b2 (-1.21867e-30, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0xc1c0bfbebdbcbbbac1c0bfbebdbcbbba (-5.62003e+08, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0xc9c8c7c6c5c4c3c2c9c8c7c6c5c4c3c2 (-2.82942e+47, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0xd1d0cfcecdcccbcad1d0cfcecdcccbca (-1.30639e+86, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d60e81f		ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [x0]
+#   v31: 0x00000000000000000002ff010002ff01 (s31: 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x0000000000000000ff000085ff000085 (s0: -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x000000000000000000fffeff00fffeff (s1: 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x00000000000000000000000000000000 (s2: 0.00000) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0de2e83c		ld4r {v28.2s, v29.2s, v30.2s, v31.2s}, [x1], x2
+#   v28: 0x0000000000000000d5d4d3d2d5d4d3d2 (s28: -2.92508e+13) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000000000d9d8d7d6d9d8d7d6 (s29: -7.62949e+15) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x0000000000000000dddcdbdadddcdbda (s30: -1.98932e+18) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x0000000000000000e1e0dfdee1e0dfde (s31: -5.18525e+20) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dffe82b		ld4r {v11.2s, v12.2s, v13.2s, v14.2s}, [x1], #16
+#   v11: 0x0000000000000000d4d3d2d1d4d3d2d1 (s11: -7.27820e+12) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000000000d8d7d6d5d8d7d6d5 (s12: -1.89854e+15) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x0000000000000000dcdbdad9dcdbdad9 (s13: -4.95069e+17) <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x0000000000000000e0dfdedde0dfdedd (s14: -1.29053e+20) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d60e413		ld4r {v19.4h, v20.4h, v21.4h, v22.4h}, [x0]
+#   v19: 0x0000000000000000ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x00000000000000000002000200020002 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x00000000000000000085008500850085 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x0000000000000000ff00ff00ff00ff00 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0de2e436		ld4r {v22.4h, v23.4h, v24.4h, v25.4h}, [x1], x2
+#   v22: 0x0000000000000000e2e1e2e1e2e1e2e1 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x0000000000000000e4e3e4e3e4e3e4e3 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x0000000000000000e6e5e6e5e6e5e6e5 <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x0000000000000000e8e7e8e7e8e7e8e7 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dffe434		ld4r {v20.4h, v21.4h, v22.4h, v23.4h}, [x1], #8
+#   v20: 0x0000000000000000e1e0e1e0e1e0e1e0 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x0000000000000000e3e2e3e2e3e2e3e2 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x0000000000000000e5e4e5e4e5e4e5e4 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x0000000000000000e7e6e7e6e7e6e7e6 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d60e810		ld4r {v16.4s, v17.4s, v18.4s, v19.4s}, [x0]
+#   v16: 0x0002ff010002ff010002ff010002ff01 (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0xff000085ff000085ff000085ff000085 (..., -1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00fffeff00fffeff00fffeff00fffeff (..., 2.35095e-38, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000000000000000000000 (..., 0.00000, ...) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4de2e839		ld4r {v25.4s, v26.4s, v27.4s, v28.4s}, [x1], x2
+#   v25: 0xebeae9e8ebeae9e8ebeae9e8ebeae9e8 (..., -5.67986e+26, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0xefeeedecefeeedecefeeedecefeeedec (..., -1.47890e+29, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0xf3f2f1f0f3f2f1f0f3f2f1f0f3f2f1f0 (..., -3.84962e+31, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0xf7f6f5f4f7f6f5f4f7f6f5f4f7f6f5f4 (..., -1.00179e+34, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dffe837		ld4r {v23.4s, v24.4s, v25.4s, v26.4s}, [x1], #16
+#   v23: 0xeae9e8e7eae9e8e7eae9e8e7eae9e8e7 (..., -1.41390e+26, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0xeeedecebeeedecebeeedecebeeedeceb (..., -3.68172e+28, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0xf2f1f0eff2f1f0eff2f1f0eff2f1f0ef (..., -9.58428e+30, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0xf6f5f4f3f6f5f4f3f6f5f4f3f6f5f4f3 (..., -2.49430e+33, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d60e016		ld4r {v22.8b, v23.8b, v24.8b, v25.8b}, [x0]
+#   v22: 0x00000000000000000101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x0000000000000000ffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00000000000000000202020202020202 <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0de2e03b		ld4r {v27.8b, v28.8b, v29.8b, v30.8b}, [x1], x2
+#   v27: 0x0000000000000000f7f7f7f7f7f7f7f7 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x0000000000000000f8f8f8f8f8f8f8f8 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000000000f9f9f9f9f9f9f9f9 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x0000000000000000fafafafafafafafa <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dffe03d		ld4r {v29.8b, v30.8b, v31.8b, v0.8b}, [x1], #4
+#   v29: 0x0000000000000000f6f6f6f6f6f6f6f6 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x0000000000000000f7f7f7f7f7f7f7f7 <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x0000000000000000f8f8f8f8f8f8f8f8 <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x0000000000000000f9f9f9f9f9f9f9f9 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d60e41c		ld4r {v28.8h, v29.8h, v30.8h, v31.8h}, [x0]
+#   v28: 0xff01ff01ff01ff01ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x00020002000200020002000200020002 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x00850085008500850085008500850085 <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0xff00ff00ff00ff00ff00ff00ff00ff00 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4de2e439		ld4r {v25.8h, v26.8h, v27.8h, v28.8h}, [x1], x2
+#   v25: 0xfbfafbfafbfafbfafbfafbfafbfafbfa <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0xfdfcfdfcfdfcfdfcfdfcfdfcfdfcfdfc <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0xfffefffefffefffefffefffefffefffe <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x01000100010001000100010001000100 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dffe436		ld4r {v22.8h, v23.8h, v24.8h, v25.8h}, [x1], #8
+#   v22: 0xfaf9faf9faf9faf9faf9faf9faf9faf9 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0xfcfbfcfbfcfbfcfbfcfbfcfbfcfbfcfb <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0xfefdfefdfefdfefdfefdfefdfefdfefd <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x00ff00ff00ff00ff00ff00ff00ff00ff <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4e3a94fd		mla v29.16b, v7.16b, v26.16b
+#   v29: 0x0002000200020002e73aed42f34af952
+0x~~~~~~~~~~~~~~~~  0eae9486		mla v6.2s, v4.2s, v14.2s
+#    v6: 0x0000000000000000dcbb11e0e6481e68
+0x~~~~~~~~~~~~~~~~  2f800969		mla v9.2s, v11.2s, v0.s[2]
+#    v9: 0x00000000000000000000000000fffeff
+0x~~~~~~~~~~~~~~~~  0e799625		mla v5.4h, v17.4h, v25.4h
+#    v5: 0x0000000000000000a4a2261ba09e2217
+0x~~~~~~~~~~~~~~~~  2f7b00f8		mla v24.4h, v7.4h, v11.h[3]
+#   v24: 0x000000000000000082b3330de36793c1
+0x~~~~~~~~~~~~~~~~  4ea4946c		mla v12.4s, v3.4s, v4.4s
+#   v12: 0x00000000000000006f49f4f5e911f705
+0x~~~~~~~~~~~~~~~~  6fa708ea		mla v10.4s, v7.4s, v7.s[3]
+#   v10: 0x00000000000000001700000000000000
+0x~~~~~~~~~~~~~~~~  0e299603		mla v3.8b, v16.8b, v9.8b
+#    v3: 0x000000000000000035342d2c25221f1b
+0x~~~~~~~~~~~~~~~~  4e7296d3		mla v19.8h, v22.8h, v18.8h
+#   v19: 0xfe070c07fe070c07fe070c07fe070c07
+0x~~~~~~~~~~~~~~~~  6f400046		mla v6.8h, v2.8h, v0.h[0]
+#    v6: 0x0000000000000000dcbb11e0e6481e68
+0x~~~~~~~~~~~~~~~~  6e2b9557		mls v23.16b, v10.16b, v11.16b
+#   v23: 0xfcfbfcfbfcfbfcfbf0fbfcfbfcfbfcfb
+0x~~~~~~~~~~~~~~~~  2eb697ee		mls v14.2s, v31.2s, v22.2s
+#   v14: 0x0000000000000000d8e1d7ddd8e1d7dd
+0x~~~~~~~~~~~~~~~~  2fa149bc		mls v28.2s, v13.2s, v1.s[3]
+#   v28: 0x00000000000000000100010001000100
+0x~~~~~~~~~~~~~~~~  2e6d9662		mls v2.4h, v19.4h, v13.4h
+#    v2: 0x0000000000000000ac03d811ac03d811
+0x~~~~~~~~~~~~~~~~  2f6c49f2		mls v18.4h, v15.4h, v12.h[6]
+#   v18: 0x000000000000000000fffeff00fffeff
+0x~~~~~~~~~~~~~~~~  6eb09566		mls v6.4s, v11.4s, v16.4s
+#    v6: 0x00000000000000006347100f6cd41c97
+0x~~~~~~~~~~~~~~~~  6f8a4a17		mls v23.4s, v16.4s, v10.s[2]
+#   v23: 0xfcfbfcfbfcfbfcfbf0fbfcfbfcfbfcfb
+0x~~~~~~~~~~~~~~~~  2e3795ba		mls v26.8b, v13.8b, v23.8b
+#   v26: 0x0000000000000000bd4365396d436539
+0x~~~~~~~~~~~~~~~~  6e6c954a		mls v10.8h, v10.8h, v12.8h
+#   v10: 0x00000000000000008800000000000000
+0x~~~~~~~~~~~~~~~~  6f7e480e		mls v14.8h, v0.8h, v14.h[7]
+#   v14: 0x0000000000000000d8e1d7ddd8e1d7dd
+0x~~~~~~~~~~~~~~~~  5e070436		mov b22, v1.b[3]
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5e1805a7		mov d7, v13.d[1]
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5e0a06ba		mov h26, v21.h[2]
+#   v26: 0x0000000000000000000000000000e3e2
+0x~~~~~~~~~~~~~~~~  5e04067a		mov s26, v19.s[0]
+#   v26: 0x000000000000000000000000fe070c07
+0x~~~~~~~~~~~~~~~~  4eab1d7a		mov v26.16b, v11.16b
+#   v26: 0x0000000000000000d4d3d2d1d4d3d2d1
+0x~~~~~~~~~~~~~~~~  0ea01c14		mov v20.8b, v0.8b
+#   v20: 0x0000000000000000f9f9f9f9f9f9f9f9
+0x~~~~~~~~~~~~~~~~  6e1b24d3		mov v19.b[13], v6.b[4]
+#   v19: 0xfe070f07fe070c07fe070c07fe070c07
+0x~~~~~~~~~~~~~~~~  4e1b1e64		mov v4.b[13], w19
+#    v4: 0x00000000000000009b9a999897969594
+0x~~~~~~~~~~~~~~~~  6e18050b		mov v11.d[1], v8.d[0]
+#   v11: 0xff0000850002ff01d4d3d2d1d4d3d2d1
+0x~~~~~~~~~~~~~~~~  4e081fc3		mov v3.d[0], x30
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e12757d		mov v29.h[4], v11.h[7]
+#   v29: 0x000200020002ff00e73aed42f34af952
+0x~~~~~~~~~~~~~~~~  4e1a1cc2		mov v2.h[6], w6
+#    v2: 0x0000000c00000000ac03d811ac03d811
+0x~~~~~~~~~~~~~~~~  6e0444b6		mov v22.s[0], v5.s[2]
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e1c1d18		mov v24.s[3], w8
+#   v24: 0x000000000000000082b3330de36793c1
+0x~~~~~~~~~~~~~~~~  0e1c3c32		mov w18, v1.s[3]
+#   x18: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  4e083ebc		mov x28, v21.d[0]
+#   x28: 0xe3e2e3e2e3e2e3e2
+0x~~~~~~~~~~~~~~~~  2f03e4f8		movi d24, #0xffff0000ffffff
+#   v24: 0x000000000000000000ffff0000ffffff
+0x~~~~~~~~~~~~~~~~  4f04e41d		movi v29.16b, #0x80
+#   v29: 0x80808080808080808080808080808080
+0x~~~~~~~~~~~~~~~~  6f06e6cc		movi v12.2d, #0xffff00ff00ffff00
+#   v12: 0xffff00ff00ffff00ffff00ff00ffff00
+0x~~~~~~~~~~~~~~~~  0f07658c		movi v12.2s, #0xec, lsl #24
+#   v12: 0x0000000000000000ec000000ec000000
+0x~~~~~~~~~~~~~~~~  0f02d58a		movi v10.2s, #0x4c, msl #16
+#   v10: 0x0000000000000000004cffff004cffff
+0x~~~~~~~~~~~~~~~~  0f06841a		movi v26.4h, #0xc0, lsl #0
+#   v26: 0x000000000000000000c000c000c000c0
+0x~~~~~~~~~~~~~~~~  4f044718		movi v24.4s, #0x98, lsl #16
+#   v24: 0x00980000009800000098000000980000
+0x~~~~~~~~~~~~~~~~  4f06d7c1		movi v1.4s, #0xde, msl #16
+#    v1: 0x00deffff00deffff00deffff00deffff
+0x~~~~~~~~~~~~~~~~  0f02e5b5		movi v21.8b, #0x4d
+#   v21: 0x00000000000000004d4d4d4d4d4d4d4d
+0x~~~~~~~~~~~~~~~~  4f03853d		movi v29.8h, #0x69, lsl #0
+#   v29: 0x00690069006900690069006900690069
+0x~~~~~~~~~~~~~~~~  4e319de1		mul v1.16b, v15.16b, v17.16b
+#    v1: 0x4700008e4b00007a4700008e4b00007a
+0x~~~~~~~~~~~~~~~~  0ebd9e75		mul v21.2s, v19.2s, v29.2s
+#   v21: 0x00000000000000001fc2eedf1fc2eedf
+0x~~~~~~~~~~~~~~~~  0f8380b3		mul v19.2s, v5.2s, v3.s[0]
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e629d7d		mul v29.4h, v11.4h, v2.4h
+#   v29: 0x0000000000000000427957e1427957e1
+0x~~~~~~~~~~~~~~~~  0f4080e2		mul v2.4h, v7.4h, v0.h[0]
+#    v2: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4eb09f59		mul v25.4s, v26.4s, v16.4s
+#   v25: 0x000000000000000042ff40c042ff40c0
+0x~~~~~~~~~~~~~~~~  4f8f88da		mul v26.4s, v6.4s, v15.s[2]
+#   v26: 0x00000000000000009d2fa76ed8a575fe
+0x~~~~~~~~~~~~~~~~  0e3f9deb		mul v11.8b, v15.8b, v31.8b
+#   v11: 0x0000000000000000470049004b004d00
+0x~~~~~~~~~~~~~~~~  4e6f9ff4		mul v20.8h, v31.8h, v15.8h
+#   v20: 0x48004a004c004e0048004a004c004e00
+0x~~~~~~~~~~~~~~~~  4f4988bd		mul v29.8h, v5.8h, v9.h[4]
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e205aad		mvn v13.16b, v21.16b
+#   v13: 0xffffffffffffffffe03d1120e03d1120
+0x~~~~~~~~~~~~~~~~  2e205a7c		mvn v28.8b, v19.8b
+#   v28: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  2f052719		mvni v25.2s, #0xb8, lsl #8
+#   v25: 0x0000000000000000ffff47ffffff47ff
+0x~~~~~~~~~~~~~~~~  2f03d591		mvni v17.2s, #0x6c, msl #16
+#   v17: 0x0000000000000000ff930000ff930000
+0x~~~~~~~~~~~~~~~~  2f02851d		mvni v29.4h, #0x48, lsl #0
+#   v29: 0x0000000000000000ffb7ffb7ffb7ffb7
+0x~~~~~~~~~~~~~~~~  6f034754		mvni v20.4s, #0x7a, lsl #16
+#   v20: 0xff85ffffff85ffffff85ffffff85ffff
+0x~~~~~~~~~~~~~~~~  6f00c7c0		mvni v0.4s, #0x1e, msl #8
+#    v0: 0xffffe100ffffe100ffffe100ffffe100
+0x~~~~~~~~~~~~~~~~  6f0187df		mvni v31.8h, #0x3e, lsl #0
+#   v31: 0xffc1ffc1ffc1ffc1ffc1ffc1ffc1ffc1
+0x~~~~~~~~~~~~~~~~  7ee0b979		neg d25, d11
+#   v25: 0x0000000000000000b8ffb6ffb4ffb300
+0x~~~~~~~~~~~~~~~~  6e20b924		neg v4.16b, v9.16b
+#    v4: 0x00000000000000000000000000010201
+0x~~~~~~~~~~~~~~~~  6ee0bb2b		neg v11.2d, v25.2d
+#   v11: 0x0000000000000000470049004b004d00
+0x~~~~~~~~~~~~~~~~  2ea0ba47		neg v7.2s, v18.2s
+#    v7: 0x0000000000000000ff000101ff000101
+0x~~~~~~~~~~~~~~~~  2e60b9e7		neg v7.4h, v15.4h
+#    v7: 0x00000000000000004648484a4a4c4c4e
+0x~~~~~~~~~~~~~~~~  6ea0ba51		neg v17.4s, v18.4s
+#   v17: 0x0000000000000000ff000101ff000101
+0x~~~~~~~~~~~~~~~~  2e20ba34		neg v20.8b, v17.8b
+#   v20: 0x00000000000000000100ffff0100ffff
+0x~~~~~~~~~~~~~~~~  6e60b960		neg v0.8h, v11.8h
+#    v0: 0x0000000000000000b900b700b500b300
+0x~~~~~~~~~~~~~~~~  4eff1d6d		orn v13.16b, v11.16b, v31.16b
+#   v13: 0x003e003e003e003e473e493e4b3e4d3e
+0x~~~~~~~~~~~~~~~~  0ef61e16		orn v22.8b, v16.8b, v22.8b
+#   v22: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4eb71e31		orr v17.16b, v17.16b, v23.16b
+#   v17: 0xfcfbfcfbfcfbfcfbfffbfdfbfffbfdfb
+0x~~~~~~~~~~~~~~~~  0f071468		orr v8.2s, #0xe3, lsl #0
+#    v8: 0x0000000000000000ff0000e70002ffe3
+0x~~~~~~~~~~~~~~~~  0f04b6eb		orr v11.4h, #0x97, lsl #8
+#   v11: 0x0000000000000000d700df00df00df00
+0x~~~~~~~~~~~~~~~~  4f051567		orr v7.4s, #0xab, lsl #0
+#    v7: 0x000000ab000000ab464848eb4a4c4cef
+0x~~~~~~~~~~~~~~~~  0ea31c88		orr v8.8b, v4.8b, v3.8b
+#    v8: 0x00000000000000000000000000010201
+0x~~~~~~~~~~~~~~~~  4f05b61f		orr v31.8h, #0xb0, lsl #8
+#   v31: 0xffc1ffc1ffc1ffc1ffc1ffc1ffc1ffc1
+0x~~~~~~~~~~~~~~~~  6e379e4b		pmul v11.16b, v18.16b, v23.16b
+#   v11: 0x000000000000000000a9a8a900a9a8a9
+0x~~~~~~~~~~~~~~~~  2e259f08		pmul v8.8b, v24.8b, v5.8b
+#    v8: 0x00000000000000000030000000100000
+0x~~~~~~~~~~~~~~~~  0e36e258		pmull v24.8h, v18.8b, v22.8b
+#   v24: 0x0000555555aa55550000555555aa5555
+0x~~~~~~~~~~~~~~~~  4e35e06d		pmull2 v13.8h, v3.16b, v21.16b
+#   v13: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2eb54156		raddhn v22.2s, v10.2d, v21.2d
+#   v22: 0x000000000000000000000000200feede
+0x~~~~~~~~~~~~~~~~  2e6d41a5		raddhn v5.4h, v13.4s, v13.4s
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e3a422a		raddhn v10.8b, v17.8h, v26.8h
+#   v10: 0x0000000000000000fdfdfdfd9da5d974
+0x~~~~~~~~~~~~~~~~  6e2d43a9		raddhn2 v9.16b, v29.8h, v13.8h
+#    v9: 0x00000000000000000000000000fffeff
+0x~~~~~~~~~~~~~~~~  6eba42fb		raddhn2 v27.4s, v23.2d, v26.2d
+#   v27: 0xfcfbfcfc8e2ba46bfffefffefffefffe
+0x~~~~~~~~~~~~~~~~  6e6743a0		raddhn2 v0.8h, v29.4s, v7.4s
+#    v0: 0x0000000046004a04b900b700b500b300
+0x~~~~~~~~~~~~~~~~  6e6059f6		rbit v22.16b, v15.16b
+#   v22: 0x9d1ded6dad2dcd4d9d1ded6dad2dcd4d
+0x~~~~~~~~~~~~~~~~  2e60587e		rbit v30.8b, v3.8b
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e201b7f		rev16 v31.16b, v27.16b
+#   v31: 0xfbfcfcfc2b8e6ba4fefffefffefffeff
+0x~~~~~~~~~~~~~~~~  0e201b4c		rev16 v12.8b, v26.8b
+#   v12: 0x00000000000000002f9d6ea7a5d8fe75
+0x~~~~~~~~~~~~~~~~  6e200885		rev32 v5.16b, v4.16b
+#    v5: 0x00000000000000000000000001020100
+0x~~~~~~~~~~~~~~~~  2e600b50		rev32 v16.4h, v26.4h
+#   v16: 0x0000000000000000a76e9d2f75fed8a5
+0x~~~~~~~~~~~~~~~~  2e200874		rev32 v20.8b, v3.8b
+#   v20: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e600b94		rev32 v20.8h, v28.8h
+#   v20: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4e200a69		rev64 v9.16b, v19.16b
+#    v9: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ea00a05		rev64 v5.2s, v16.2s
+#    v5: 0x000000000000000075fed8a5a76e9d2f
+0x~~~~~~~~~~~~~~~~  0e600be7		rev64 v7.4h, v31.4h
+#    v7: 0x0000000000000000fefffefffefffeff
+0x~~~~~~~~~~~~~~~~  4ea00b4f		rev64 v15.4s, v26.4s
+#   v15: 0x0000000000000000d8a575fe9d2fa76e
+0x~~~~~~~~~~~~~~~~  0e200939		rev64 v25.8b, v9.8b
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e6008ab		rev64 v11.8h, v5.8h
+#   v11: 0x00000000000000009d2fa76ed8a575fe
+0x~~~~~~~~~~~~~~~~  0f3f8db2		rshrn v18.2s, v13.2d, #1
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f1e8fd9		rshrn v25.4h, v30.4s, #2
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f088d2d		rshrn v13.8b, v9.8h, #8
+#   v13: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f088cc3		rshrn2 v3.16b, v6.8h, #8
+#    v3: 0x0000000063106d1d0000000000000000
+0x~~~~~~~~~~~~~~~~  4f278fa0		rshrn2 v0.4s, v29.2d, #25
+#    v0: 0x00000000dbffdc00b900b700b500b300
+0x~~~~~~~~~~~~~~~~  4f118f5b		rshrn2 v27.8h, v26.4s, #15
+#   v27: 0x000000003a5fb14bfffefffefffefffe
+0x~~~~~~~~~~~~~~~~  2ea4632f		rsubhn v15.2s, v25.2d, v4.2d
+#   v15: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e636137		rsubhn v23.4h, v9.4s, v3.4s
+#   v23: 0x000000000000000000009cf000000000
+0x~~~~~~~~~~~~~~~~  2e3863c6		rsubhn v6.8b, v30.8h, v24.8h
+#    v6: 0x000000000000000000abaaab00abaaab
+0x~~~~~~~~~~~~~~~~  6e346304		rsubhn2 v4.16b, v24.8h, v20.8h
+#    v4: 0x00555655005556550000000000010201
+0x~~~~~~~~~~~~~~~~  6eb662e1		rsubhn2 v1.4s, v23.2d, v22.2d
+#    v1: 0x62e2129262e2af824700008e4b00007a
+0x~~~~~~~~~~~~~~~~  6e746053		rsubhn2 v19.8h, v2.4s, v20.4s
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e397d3c		saba v28.16b, v9.16b, v25.16b
+#   v28: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  0eb47f89		saba v9.2s, v28.2s, v20.2s
+#    v9: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e767ed1		saba v17.4h, v22.4h, v22.4h
+#   v17: 0x0000000000000000fffbfdfbfffbfdfb
+0x~~~~~~~~~~~~~~~~  4ebb7cbd		saba v29.4s, v5.4s, v27.4s
+#   v29: 0x000000003a5fb14b75b7d85e58486286
+0x~~~~~~~~~~~~~~~~  0e327eb4		saba v20.8b, v21.8b, v18.8b
+#   v20: 0x00000000000000001e3d11201e3d1120
+0x~~~~~~~~~~~~~~~~  4e7e7e3b		saba v27.8h, v17.8h, v30.8h
+#   v27: 0x000000003a5fb14b0003020300030203
+0x~~~~~~~~~~~~~~~~  0ea751b4		sabal v20.2d, v13.2s, v7.2s
+#   v20: 0x00000000010001011e3d11201f3d1221
+0x~~~~~~~~~~~~~~~~  0e645184		sabal v4.4s, v12.4h, v4.4h
+#    v4: 0x005585f20055c4fc00005a290001058d
+0x~~~~~~~~~~~~~~~~  0e345317		sabal v23.8h, v24.8b, v20.8b
+#   v23: 0x001e003d0044003500369d8300430034
+0x~~~~~~~~~~~~~~~~  4eb252ba		sabal2 v26.2d, v21.4s, v18.4s
+#   v26: 0x00000000000000009d2fa76ed8a575fe
+0x~~~~~~~~~~~~~~~~  4e68539b		sabal2 v27.4s, v28.8h, v8.8h
+#   v27: 0x000000003a5fb14b0003020300030203
+0x~~~~~~~~~~~~~~~~  4e35520c		sabal2 v12.8h, v16.16b, v21.16b
+#   v12: 0x00000000000000002f9d6ea7a5d8fe75
+0x~~~~~~~~~~~~~~~~  4e2d75e0		sabd v0.16b, v15.16b, v13.16b
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ebe74ef		sabd v15.2s, v7.2s, v30.2s
+#   v15: 0x00000000000000000100010101000101
+0x~~~~~~~~~~~~~~~~  0e6c7631		sabd v17.4h, v17.4h, v12.4h
+#   v17: 0x00000000000000002fa270ac5a23007a
+0x~~~~~~~~~~~~~~~~  4eb67487		sabd v7.4s, v4.4s, v22.4s
+#    v7: 0x633798855327f7af62e26cbc52d33840
+0x~~~~~~~~~~~~~~~~  0e3a7477		sabd v23.8b, v3.8b, v26.8b
+#   v23: 0x0000000000000000632f596e285b7502
+0x~~~~~~~~~~~~~~~~  4e657794		sabd v20.8h, v28.8h, v5.8h
+#   v20: 0x000000000000000075ff275a589162d0
+0x~~~~~~~~~~~~~~~~  0eb472db		sabdl v27.2d, v22.2s, v20.2s
+#   v27: 0x00000000d8e139ed00000000ab639583
+0x~~~~~~~~~~~~~~~~  0e77729f		sabdl v31.4s, v20.4h, v23.4h
+#   v31: 0x000012d0000032140000303600001232
+0x~~~~~~~~~~~~~~~~  0e3b7280		sabdl v0.8h, v20.8b, v27.8b
+#    v0: 0x007500010027005a00ad00d200cd004d
+0x~~~~~~~~~~~~~~~~  4ea3717f		sabdl2 v31.2d, v11.4s, v3.4s
+#   v31: 0x00000000000000000000000063106d1d
+0x~~~~~~~~~~~~~~~~  4e7b717a		sabdl2 v26.4s, v11.8h, v27.8h
+#   v26: 0x00000000000000000000271f000039ed
+0x~~~~~~~~~~~~~~~~  4e327106		sabdl2 v6.8h, v8.16b, v18.16b
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ea06b48		sadalp v8.1d, v26.2s
+#    v8: 0x0000000000000000003000000010610c
+0x~~~~~~~~~~~~~~~~  4ea06b4c		sadalp v12.2d, v26.4s
+#   v12: 0x00000000000000002f9d6ea7a5d95f81
+0x~~~~~~~~~~~~~~~~  0e606b4c		sadalp v12.2s, v26.4h
+#   v12: 0x00000000000000002f9d95c6a5d9996e
+0x~~~~~~~~~~~~~~~~  0e206824		sadalp v4.4h, v1.8b
+#    v4: 0x0000000000000000004759b7004c0607
+0x~~~~~~~~~~~~~~~~  4e606a2f		sadalp v15.4s, v17.8h
+#   v15: 0x00000000000000000100a14f01005b9e
+0x~~~~~~~~~~~~~~~~  4e206b35		sadalp v21.8h, v25.16b
+#   v21: 0x00000000000000001fc2eedf1fc2eedf
+0x~~~~~~~~~~~~~~~~  0eae0145		saddl v5.2d, v10.2s, v14.2s
+#    v5: 0xffffffffd6dfd5daffffffff7687b151
+0x~~~~~~~~~~~~~~~~  0e6f0072		saddl v18.4s, v3.4h, v15.4h
+#   v18: 0x00000100ffffa14f0000010000005b9e
+0x~~~~~~~~~~~~~~~~  0e37004f		saddl v15.8h, v2.8b, v23.8b
+#   v15: 0x0063002f0059006e0028005b00750002
+0x~~~~~~~~~~~~~~~~  4ebb0210		saddl2 v16.2d, v16.4s, v27.4s
+#   v16: 0x0000000000000000ffffffffd8e139ed
+0x~~~~~~~~~~~~~~~~  4e600306		saddl2 v6.4s, v24.8h, v0.8h
+#    v6: 0x0000007500005556000055d1000055af
+0x~~~~~~~~~~~~~~~~  4e3c0287		saddl2 v7.8h, v20.16b, v28.16b
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ea02b2a		saddlp v10.1d, v25.2s
+#   v10: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ea02a0f		saddlp v15.2d, v16.4s
+#   v15: 0x0000000000000000ffffffffd8e139ec
+0x~~~~~~~~~~~~~~~~  0e602952		saddlp v18.2s, v10.4h
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e202b5d		saddlp v29.4h, v26.8b
+#   v29: 0x00000000000000000000004600000026
+0x~~~~~~~~~~~~~~~~  4e60282a		saddlp v10.4s, v1.8h
+#   v10: 0x00007574000012640000478e00004b7a
+0x~~~~~~~~~~~~~~~~  4e202aa0		saddlp v0.8h, v21.16b
+#    v0: 0x0000000000000000ffe1ffcdffe1ffcd
+0x~~~~~~~~~~~~~~~~  4eb038ec		saddlv d12, v7.4s
+#   v12: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e303b8e		saddlv h14, v28.16b
+#   v14: 0x0000000000000000000000000000fff8
+0x~~~~~~~~~~~~~~~~  0e303bde		saddlv h30, v30.8b
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e70387b		saddlv s27, v3.4h
+#   v27: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e703a10		saddlv s16, v16.8h
+#   v16: 0x000000000000000000000000000012cc
+0x~~~~~~~~~~~~~~~~  0eb21178		saddw v24.2d, v11.2d, v18.2s
+#   v24: 0x00000000000000009d2fa76ed8a575fe
+0x~~~~~~~~~~~~~~~~  0e66118d		saddw v13.4s, v12.4s, v6.4h
+#   v13: 0x00000000000055d100000000000055af
+0x~~~~~~~~~~~~~~~~  0e271273		saddw v19.8h, v19.8h, v7.8b
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4eba113b		saddw2 v27.2d, v9.2d, v26.4s
+#   v27: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e7512f3		saddw2 v19.4s, v23.4s, v21.8h
+#   v19: 0x0000000000000000632f596e285b7502
+0x~~~~~~~~~~~~~~~~  4e3e132f		saddw2 v15.8h, v25.8h, v30.16b
+#   v15: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e290487		shadd v7.16b, v4.16b, v9.16b
+#    v7: 0x000000000000000000232cdb00260303
+0x~~~~~~~~~~~~~~~~  0eb8073d		shadd v29.2s, v25.2s, v24.2s
+#   v29: 0x0000000000000000ce97d3b7ec52baff
+0x~~~~~~~~~~~~~~~~  0e6d055f		shadd v31.4h, v10.4h, v13.4h
+#   v31: 0x0000000000000000000023c700005094
+0x~~~~~~~~~~~~~~~~  4ea80615		shadd v21.4s, v16.4s, v8.4s
+#   v21: 0x000000000000000000180000000839ec
+0x~~~~~~~~~~~~~~~~  0e3607ae		shadd v14.8b, v29.8b, v22.8b
+#   v14: 0x0000000000000000b5dae012cc3fc326
+0x~~~~~~~~~~~~~~~~  4e740713		shadd v19.8h, v24.8h, v20.8h
+#   v19: 0x00000000000000000997e764189b6c67
+0x~~~~~~~~~~~~~~~~  5f575736		shl d22, d25, #23
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f0f5625		shl v5.16b, v17.16b, #7
+#    v5: 0x00000000000000008000000000800000
+0x~~~~~~~~~~~~~~~~  4f555482		shl v2.2d, v4.2d, #21
+#    v2: 0x000000000000000036e00980c0e00000
+0x~~~~~~~~~~~~~~~~  0f3a5464		shl v4.2s, v3.2s, #26
+#    v4: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f185783		shl v3.4h, v28.4h, #8
+#    v3: 0x0000000000000000ff00ff00ff00ff00
+0x~~~~~~~~~~~~~~~~  4f3857e4		shl v4.4s, v31.4s, #24
+#    v4: 0x0000000000000000c700000094000000
+0x~~~~~~~~~~~~~~~~  0f0a5612		shl v18.8b, v16.8b, #2
+#   v18: 0x00000000000000000000000000004830
+0x~~~~~~~~~~~~~~~~  4f135560		shl v0.8h, v11.8h, #3
+#    v0: 0x0000000000000000e9783b70c528aff0
+0x~~~~~~~~~~~~~~~~  2ea13b05		shll v5.2d, v24.2s, #32
+#    v5: 0x9d2fa76e00000000d8a575fe00000000
+0x~~~~~~~~~~~~~~~~  2e613a9a		shll v26.4s, v20.4h, #16
+#   v26: 0x75ff0000275a00005891000062d00000
+0x~~~~~~~~~~~~~~~~  2e213925		shll v5.8h, v9.8b, #8
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ea13b95		shll2 v21.2d, v28.4s, #32
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e613836		shll2 v22.4s, v1.8h, #16
+#   v22: 0x62e200001292000062e20000af820000
+0x~~~~~~~~~~~~~~~~  6e213b3e		shll2 v30.8h, v25.16b, #8
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f248425		shrn v5.2s, v1.2d, #28
+#    v5: 0x00000000000000002e212926700008e4
+0x~~~~~~~~~~~~~~~~  0f19865d		shrn v29.4h, v18.4s, #7
+#   v29: 0x00000000000000000000000000000090
+0x~~~~~~~~~~~~~~~~  0f0e87b1		shrn v17.8b, v29.8h, #2
+#   v17: 0x00000000000000000000000000000024
+0x~~~~~~~~~~~~~~~~  4f0d87c5		shrn2 v5.16b, v30.8h, #3
+#    v5: 0x00000000000000002e212926700008e4
+0x~~~~~~~~~~~~~~~~  4f3f8438		shrn2 v24.4s, v1.2d, #1
+#   v24: 0x317157c12580003d9d2fa76ed8a575fe
+0x~~~~~~~~~~~~~~~~  4f1085c5		shrn2 v5.8h, v14.4s, #16
+#    v5: 0x00000000b5dacc3f2e212926700008e4
+0x~~~~~~~~~~~~~~~~  4e3726de		shsub v30.16b, v22.16b, v23.16b
+#   v30: 0x31f1000009c90000ffd9d3c9c393c5ff
+0x~~~~~~~~~~~~~~~~  0eb92776		shsub v22.2s, v27.2s, v25.2s
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e6126cd		shsub v13.4h, v22.4h, v1.4h
+#   v13: 0x0000000000000000dc80ffb9da80ffc3
+0x~~~~~~~~~~~~~~~~  4eb7250a		shsub v10.4s, v8.4s, v23.4s
+#   v10: 0x0000000000000000ce805349ebda7605
+0x~~~~~~~~~~~~~~~~  0e3f2526		shsub v6.8b, v9.8b, v31.8b
+#    v6: 0x00000000000000000000ee1c0000d836
+0x~~~~~~~~~~~~~~~~  4e6827e8		shsub v8.8h, v31.8h, v8.8h
+#    v8: 0x0000000000000000ffe811e3fff8f7c4
+0x~~~~~~~~~~~~~~~~  7f5457b3		sli d19, d29, #20
+#   v19: 0x000000000000000000000000090b6c67
+0x~~~~~~~~~~~~~~~~  6f085709		sli v9.16b, v24.16b, #0
+#    v9: 0x317157c12580003d9d2fa76ed8a575fe
+0x~~~~~~~~~~~~~~~~  6f4a5536		sli v22.2d, v9.2d, #10
+#   v22: 0xc55f04960000f400be9dbb6295d7f800
+0x~~~~~~~~~~~~~~~~  2f34576b		sli v11.2s, v27.2s, #20
+#   v11: 0x0000000000000000000fa76e000575fe
+0x~~~~~~~~~~~~~~~~  2f1555f0		sli v16.4h, v15.4h, #5
+#   v16: 0x0000000000000000000000000000000c
+0x~~~~~~~~~~~~~~~~  6f395508		sli v8.4s, v8.4s, #25
+#    v8: 0x0000000000000000c7e811e389f8f7c4
+0x~~~~~~~~~~~~~~~~  2f0857ca		sli v10.8b, v30.8b, #0
+#   v10: 0x0000000000000000ffd9d3c9c393c5ff
+0x~~~~~~~~~~~~~~~~  6f165787		sli v7.8h, v28.8h, #6
+#    v7: 0x0000000000000000ffe3ffdbffe6ffc3
+0x~~~~~~~~~~~~~~~~  4e216512		smax v18.16b, v8.16b, v1.16b
+#   v18: 0x6200120062000000470011e34b00007a
+0x~~~~~~~~~~~~~~~~  0ea164be		smax v30.2s, v5.2s, v1.2s
+#   v30: 0x00000000000000004700008e700008e4
+0x~~~~~~~~~~~~~~~~  0e736731		smax v17.4h, v25.4h, v19.4h
+#   v17: 0x000000000000000000000000090b6c67
+0x~~~~~~~~~~~~~~~~  4ebf6701		smax v1.4s, v24.4s, v31.4s
+#    v1: 0x317157c12580003d000023c700005094
+0x~~~~~~~~~~~~~~~~  0e386711		smax v17.8b, v24.8b, v24.8b
+#   v17: 0x00000000000000009d2fa76ed8a575fe
+0x~~~~~~~~~~~~~~~~  4e6a674b		smax v11.8h, v26.8h, v10.8h
+#   v11: 0x75ff0000275a00005891000062d00000
+0x~~~~~~~~~~~~~~~~  4e27a5cc		smaxp v12.16b, v14.16b, v7.16b
+#   v12: 0x00000000ffffffff00000000da123f26
+0x~~~~~~~~~~~~~~~~  0ea6a71f		smaxp v31.2s, v24.2s, v6.2s
+#   v31: 0x00000000000000000000ee1cd8a575fe
+0x~~~~~~~~~~~~~~~~  0e6aa7aa		smaxp v10.4h, v29.4h, v10.4h
+#   v10: 0x00000000000000000090009000000090
+0x~~~~~~~~~~~~~~~~  4ea7a572		smaxp v18.4s, v11.4s, v7.4s
+#   v18: 0x00000000ffe6ffc375ff000062d00000
+0x~~~~~~~~~~~~~~~~  0e32a415		smaxp v21.8b, v0.8b, v18.8b
+#   v21: 0x000000000000000075006200787028f0
+0x~~~~~~~~~~~~~~~~  4e6fa51a		smaxp v26.8h, v8.8h, v15.8h
+#   v26: 0x00000000000000000000000011e3f7c4
+0x~~~~~~~~~~~~~~~~  4e30a8a4		smaxv b4, v5.16b
+#    v4: 0x00000000000000000000000000000070
+0x~~~~~~~~~~~~~~~~  0e30a817		smaxv b23, v0.8b
+#   v23: 0x00000000000000000000000000000078
+0x~~~~~~~~~~~~~~~~  0e70a806		smaxv h6, v0.4h
+#    v6: 0x00000000000000000000000000003b70
+0x~~~~~~~~~~~~~~~~  4e70a918		smaxv h24, v8.8h
+#   v24: 0x000000000000000000000000000011e3
+0x~~~~~~~~~~~~~~~~  4eb0aa03		smaxv s3, v16.4s
+#    v3: 0x0000000000000000000000000000000c
+0x~~~~~~~~~~~~~~~~  4e326d18		smin v24.16b, v8.16b, v18.16b
+#   v24: 0x00000000ffe6ffc3c7e800e389d0f7c4
+0x~~~~~~~~~~~~~~~~  0eb76d1d		smin v29.2s, v8.2s, v23.2s
+#   v29: 0x0000000000000000c7e811e389f8f7c4
+0x~~~~~~~~~~~~~~~~  0e756d66		smin v6.4h, v11.4h, v21.4h
+#    v6: 0x00000000000000005891000062d00000
+0x~~~~~~~~~~~~~~~~  4eaf6ef8		smin v24.4s, v23.4s, v15.4s
+#   v24: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e246e08		smin v8.8b, v16.8b, v4.8b
+#    v8: 0x0000000000000000000000000000000c
+0x~~~~~~~~~~~~~~~~  4e6a6c2c		smin v12.8h, v1.8h, v10.8h
+#   v12: 0x00000000000000000000009000000090
+0x~~~~~~~~~~~~~~~~  4e3cae4d		sminp v13.16b, v18.16b, v28.16b
+#   v13: 0x00000000ffffffff0000e6c3ff00d000
+0x~~~~~~~~~~~~~~~~  0eb0af96		sminp v22.2s, v28.2s, v16.2s
+#   v22: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  0e65ad8f		sminp v15.4h, v12.4h, v5.4h
+#   v15: 0x0000000000000000292608e400000000
+0x~~~~~~~~~~~~~~~~  4ea8ae2f		sminp v15.4s, v17.4s, v8.4s
+#   v15: 0x0000000000000000000000009d2fa76e
+0x~~~~~~~~~~~~~~~~  0e26ac55		sminp v21.8b, v2.8b, v6.8b
+#   v21: 0x00000000000000009100d000e080c000
+0x~~~~~~~~~~~~~~~~  4e66ad95		sminp v21.8h, v12.8h, v6.8h
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e31a8c8		sminv b8, v6.16b
+#    v8: 0x00000000000000000000000000000091
+0x~~~~~~~~~~~~~~~~  0e31aa46		sminv b6, v18.8b
+#    v6: 0x000000000000000000000000000000d0
+0x~~~~~~~~~~~~~~~~  0e71a834		sminv h20, v1.4h
+#   v20: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e71aa27		sminv h7, v17.8h
+#    v7: 0x00000000000000000000000000009d2f
+0x~~~~~~~~~~~~~~~~  4eb1a895		sminv s21, v4.4s
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0eb581d8		smlal v24.2d, v14.2s, v21.2s
+#   v24: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f8e287f		smlal v31.2d, v3.2s, v14.s[2]
+#   v31: 0x00000000000000000000ee1cd8a575fe
+0x~~~~~~~~~~~~~~~~  0e758287		smlal v7.4s, v20.4h, v21.4h
+#    v7: 0x00000000000000000000000000009d2f
+0x~~~~~~~~~~~~~~~~  0f792213		smlal v19.4s, v16.4h, v9.h[3]
+#   v19: 0x0000000000000000000000000906ca9b
+0x~~~~~~~~~~~~~~~~  0e2181dd		smlal v29.8h, v14.8b, v1.8b
+#   v29: 0x00000000fba0fbfec7e811e376e8e7bc
+0x~~~~~~~~~~~~~~~~  4eb0835e		smlal2 v30.2d, v26.4s, v16.4s
+#   v30: 0x00000000000000004700008e700008e4
+0x~~~~~~~~~~~~~~~~  4f8123df		smlal2 v31.2d, v30.4s, v1.s[0]
+#   v31: 0x00000000000000000000ee1cd8a575fe
+0x~~~~~~~~~~~~~~~~  4e6380d1		smlal2 v17.4s, v6.8h, v3.8h
+#   v17: 0x00000000000000009d2fa76ed8a575fe
+0x~~~~~~~~~~~~~~~~  4f752beb		smlal2 v11.4s, v31.8h, v5.h[7]
+#   v11: 0x75ff0000275a00005891000062d00000
+0x~~~~~~~~~~~~~~~~  4e3d821e		smlal2 v30.8h, v16.16b, v29.16b
+#   v30: 0x00000000000000004700008e700008e4
+0x~~~~~~~~~~~~~~~~  0eb1a281		smlsl v1.2d, v20.2s, v17.2s
+#    v1: 0x317157c12580003d000023c700005094
+0x~~~~~~~~~~~~~~~~  0fa5699d		smlsl v29.2d, v12.2s, v5.s[3]
+#   v29: 0x00000000fba0fbfec7e811e376e8e7bc
+0x~~~~~~~~~~~~~~~~  0e61a340		smlsl v0.4s, v26.4h, v1.4h
+#    v0: 0x0000000000000000e9783b70c7c032a0
+0x~~~~~~~~~~~~~~~~  0f5668a3		smlsl v3.4s, v5.4h, v6.h[5]
+#    v3: 0x0000000000000000000000000000000c
+0x~~~~~~~~~~~~~~~~  0e3aa004		smlsl v4.8h, v0.8b, v26.8b
+#    v4: 0x000000000000000003c9f8c001c2e9f0
+0x~~~~~~~~~~~~~~~~  4ea5a1ce		smlsl2 v14.2d, v14.4s, v5.4s
+#   v14: 0x0000000000000000b5dae012cc3fc326
+0x~~~~~~~~~~~~~~~~  4fa060af		smlsl2 v15.2d, v5.4s, v0.s[1]
+#   v15: 0x0000000000000000f9797b018bdbc6de
+0x~~~~~~~~~~~~~~~~  4e7fa23d		smlsl2 v29.4s, v17.8h, v31.8h
+#   v29: 0x00000000fba0fbfec7e811e376e8e7bc
+0x~~~~~~~~~~~~~~~~  4f6969e6		smlsl2 v6.4s, v15.8h, v9.h[6]
+#    v6: 0x000000000000000000000000000000d0
+0x~~~~~~~~~~~~~~~~  4e2fa1fe		smlsl2 v30.8h, v15.16b, v15.16b
+#   v30: 0x00000000000000004700008e700008e4
+0x~~~~~~~~~~~~~~~~  0e072cd5		smov w21, v6.b[3]
+#   x21: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  0e1e2f4d		smov w13, v26.h[7]
+#   x13: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  4e0f2e18		smov x24, v16.b[7]
+#   x24: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  4e0e2c87		smov x7, v4.h[3]
+#    x7: 0x00000000000003c9
+0x~~~~~~~~~~~~~~~~  4e0c2cfd		smov x29, v7.s[1]
+#   x29: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  0eb1c3a4		smull v4.2d, v29.2s, v17.2s
+#    v4: 0x15a6d000c90fc48aedb876b6692ad888
+0x~~~~~~~~~~~~~~~~  0f86aabe		smull v30.2d, v21.2s, v6.s[2]
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e77c0b7		smull v23.4s, v5.4h, v23.4h
+#   v23: 0x00000000000000000000000000042ae0
+0x~~~~~~~~~~~~~~~~  0f52a128		smull v8.4s, v9.4h, v2.h[1]
+#    v8: 0x185dc92015d7004009b45060e2e7be40
+0x~~~~~~~~~~~~~~~~  0e21c23f		smull v31.8h, v17.8b, v1.8b
+#   v31: 0x00000000f3d5e78200000000249000d8
+0x~~~~~~~~~~~~~~~~  4eb7c063		smull2 v3.2d, v3.4s, v23.4s
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4fa6a3af		smull2 v15.2d, v29.4s, v6.s[1]
+#   v15: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e7ec293		smull2 v19.4s, v20.8h, v30.8h
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f47a946		smull2 v6.4s, v10.8h, v7.h[4]
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e3bc119		smull2 v25.8h, v8.16b, v27.16b
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5e2079e3		sqabs b3, b15
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5ee0792e		sqabs d14, d9
+#   v14: 0x000000000000000062d05891275a8a02
+0x~~~~~~~~~~~~~~~~  5e607b9f		sqabs h31, h28
+#   v31: 0x00000000000000000000000000000001
+0x~~~~~~~~~~~~~~~~  5ea07808		sqabs s8, s0
+#    v8: 0x000000000000000000000000383fcd60
+0x~~~~~~~~~~~~~~~~  4e2078ee		sqabs v14.16b, v7.16b
+#   v14: 0x0000000000000000000000000000632f
+0x~~~~~~~~~~~~~~~~  4ee07a77		sqabs v23.2d, v19.2d
+#   v23: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ea07b0a		sqabs v10.2s, v24.2s
+#   v10: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e607a7f		sqabs v31.4h, v19.4h
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ea07817		sqabs v23.4s, v0.4s
+#   v23: 0x00000000000000001687c490383fcd60
+0x~~~~~~~~~~~~~~~~  0e207afd		sqabs v29.8b, v23.8b
+#   v29: 0x000000000000000016793c70383f3360
+0x~~~~~~~~~~~~~~~~  4e607ab1		sqabs v17.8h, v21.8h
+#   v17: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5e2d0ee9		sqadd b9, b23, b13
+#    v9: 0x00000000000000000000000000000060
+0x~~~~~~~~~~~~~~~~  5efa0f22		sqadd d2, d25, d26
+#    v2: 0x00000000000000000000000011e3f7c4
+0x~~~~~~~~~~~~~~~~  5e790fa7		sqadd h7, h29, h25
+#    v7: 0x00000000000000000000000000003360
+0x~~~~~~~~~~~~~~~~  5eb80ceb		sqadd s11, s7, s24
+#   v11: 0x00000000000000000000000000003360
+0x~~~~~~~~~~~~~~~~  4e3d0e14		sqadd v20.16b, v16.16b, v29.16b
+#   v20: 0x000000000000000016793c70383f336c
+0x~~~~~~~~~~~~~~~~  4efc0fd7		sqadd v23.2d, v30.2d, v28.2d
+#   v23: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  0ea20e68		sqadd v8.2s, v19.2s, v2.2s
+#    v8: 0x00000000000000000000000011e3f7c4
+0x~~~~~~~~~~~~~~~~  0e7f0d94		sqadd v20.4h, v12.4h, v31.4h
+#   v20: 0x00000000000000000000009000000090
+0x~~~~~~~~~~~~~~~~  4eb10dee		sqadd v14.4s, v15.4s, v17.4s
+#   v14: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e2d0fa2		sqadd v2.8b, v29.8b, v13.8b
+#    v2: 0x000000000000000016792233373f0360
+0x~~~~~~~~~~~~~~~~  4e6e0e67		sqadd v7.8h, v19.8h, v14.8h
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5ebe90af		sqdmlal d15, s5, s30
+#   v15: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5fa23958		sqdmlal d24, s10, v2.s[3]
+#   v24: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5e689269		sqdmlal s9, h19, h8
+#    v9: 0x00000000000000000000000000000060
+0x~~~~~~~~~~~~~~~~  5f7c302e		sqdmlal s14, h1, v12.h[3]
+#   v14: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ebf90be		sqdmlal v30.2d, v5.2s, v31.2s
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0faa31d9		sqdmlal v25.2d, v14.2s, v10.s[1]
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e709233		sqdmlal v19.4s, v17.4h, v16.4h
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f5830a8		sqdmlal v8.4s, v5.4h, v8.h[1]
+#    v8: 0x0672308605c005640fa6a0001322041c
+0x~~~~~~~~~~~~~~~~  4ea392e1		sqdmlal2 v1.2d, v23.4s, v3.4s
+#    v1: 0x317157c12580003d000023c700005094
+0x~~~~~~~~~~~~~~~~  4f893013		sqdmlal2 v19.2d, v0.4s, v9.s[0]
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e6b92da		sqdmlal2 v26.4s, v22.8h, v11.8h
+#   v26: 0x00000000000000000000000011e3f7c4
+0x~~~~~~~~~~~~~~~~  4f4d3b86		sqdmlal2 v6.4s, v28.8h, v13.h[4]
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5eb4b3aa		sqdmlsl d10, s29, s20
+#   v10: 0x0000000000000000ffffffc0b8e63400
+0x~~~~~~~~~~~~~~~~  5faa712a		sqdmlsl d10, s9, v10.s[1]
+#   v10: 0x0000000000000000ffffffc0b8e66400
+0x~~~~~~~~~~~~~~~~  5e78b13e		sqdmlsl s30, h9, h24
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5f56730d		sqdmlsl s13, h24, v6.h[1]
+#   v13: 0x000000000000000000000000ff00d000
+0x~~~~~~~~~~~~~~~~  0eb4b15b		sqdmlsl v27.2d, v10.2s, v20.2s
+#   v27: 0x00000000000048000000004ffccf8000
+0x~~~~~~~~~~~~~~~~  0fa37af7		sqdmlsl v23.2d, v23.2s, v3.s[3]
+#   v23: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  0e7db227		sqdmlsl v7.4s, v17.4h, v29.4h
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f437ab6		sqdmlsl v22.4s, v21.4h, v3.h[4]
+#   v22: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  4eb6b0ec		sqdmlsl2 v12.2d, v7.4s, v22.4s
+#   v12: 0x00000000000000000000009000000090
+0x~~~~~~~~~~~~~~~~  4f887334		sqdmlsl2 v20.2d, v25.4s, v8.s[0]
+#   v20: 0x00000000000000000000009000000090
+0x~~~~~~~~~~~~~~~~  4e72b359		sqdmlsl2 v25.4s, v26.8h, v18.8h
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f457279		sqdmlsl2 v25.4s, v19.8h, v5.h[0]
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5e6cb771		sqdmulh h17, h27, h12
+#   v17: 0x0000000000000000000000000000ff70
+0x~~~~~~~~~~~~~~~~  5f4bc0b0		sqdmulh h16, h5, v11.h[0]
+#   v16: 0x00000000000000000000000000000391
+0x~~~~~~~~~~~~~~~~  5eb0b661		sqdmulh s1, s19, s16
+#    v1: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5f82c201		sqdmulh s1, s16, v2.s[0]
+#    v1: 0x0000000000000000000000000000018a
+0x~~~~~~~~~~~~~~~~  0ea8b43c		sqdmulh v28.2s, v1.2s, v8.2s
+#   v28: 0x0000000000000000000000000000003a
+0x~~~~~~~~~~~~~~~~  0f83c11c		sqdmulh v28.2s, v8.2s, v3.s[0]
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e65b72b		sqdmulh v11.4h, v25.4h, v5.4h
+#   v11: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f58c9de		sqdmulh v30.4h, v14.4h, v8.h[5]
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4eadb6b9		sqdmulh v25.4s, v21.4s, v13.4s
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4faac857		sqdmulh v23.4s, v2.4s, v10.s[3]
+#   v23: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e77b4ba		sqdmulh v26.8h, v5.8h, v23.8h
+#   v26: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f74c2c4		sqdmulh v4.8h, v22.8h, v4.h[3]
+#    v4: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5ebad059		sqdmull d25, s2, s26
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5fa5b1de		sqdmull d30, s14, v5.s[1]
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5e6bd25d		sqdmull s29, h18, h11
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5f67b9ab		sqdmull s11, h13, v7.h[6]
+#   v11: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ea8d137		sqdmull v23.2d, v9.2s, v8.2s
+#   v23: 0x00000000000000000000000e59831500
+0x~~~~~~~~~~~~~~~~  0fa4b3b2		sqdmull v18.2d, v29.2s, v4.s[1]
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e67d311		sqdmull v17.4s, v24.4h, v7.4h
+#   v17: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f55b1e8		sqdmull v8.4s, v15.4h, v5.h[1]
+#    v8: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ea2d1dc		sqdmull2 v28.2d, v14.4s, v2.4s
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f8dbb01		sqdmull2 v1.2d, v24.4s, v13.s[2]
+#    v1: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e7fd22b		sqdmull2 v11.4s, v17.8h, v31.8h
+#   v11: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f7bb281		sqdmull2 v1.4s, v20.8h, v11.h[3]
+#    v1: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7e207802		sqneg b2, b0
+#    v2: 0x00000000000000000000000000000060
+0x~~~~~~~~~~~~~~~~  7ee07858		sqneg d24, d2
+#   v24: 0x0000000000000000ffffffffffffffa0
+0x~~~~~~~~~~~~~~~~  7e60787d		sqneg h29, h3
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7ea07924		sqneg s4, s9
+#    v4: 0x000000000000000000000000ffffffa0
+0x~~~~~~~~~~~~~~~~  6e207bae		sqneg v14.16b, v29.16b
+#   v14: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ee0799e		sqneg v30.2d, v12.2d
+#   v30: 0x0000000000000000ffffff6fffffff70
+0x~~~~~~~~~~~~~~~~  2ea07b5c		sqneg v28.2s, v26.2s
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e607884		sqneg v4.4h, v4.4h
+#    v4: 0x00000000000000000000000000010060
+0x~~~~~~~~~~~~~~~~  6ea07909		sqneg v9.4s, v8.4s
+#    v9: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e207a94		sqneg v20.8b, v20.8b
+#   v20: 0x00000000000000000000007000000070
+0x~~~~~~~~~~~~~~~~  6e60795b		sqneg v27.8h, v10.8h
+#   v27: 0x000000000000000000010040471a9c00
+0x~~~~~~~~~~~~~~~~  7e60b707		sqrdmulh h7, h24, h0
+#    v7: 0x0000000000000000000000000000ffda
+0x~~~~~~~~~~~~~~~~  5f64d86e		sqrdmulh h14, h3, v4.h[6]
+#   v14: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7eb8b67b		sqrdmulh s27, s19, s24
+#   v27: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5f84d2bf		sqrdmulh s31, s21, v4.s[0]
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2ea1b732		sqrdmulh v18.2s, v25.2s, v1.2s
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f8dd0b6		sqrdmulh v22.2s, v5.2s, v13.s[0]
+#   v22: 0x0000000000000000ffa408a4ff20b5ee
+0x~~~~~~~~~~~~~~~~  2e69b716		sqrdmulh v22.4h, v24.4h, v9.4h
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f6cd84d		sqrdmulh v13.4h, v2.4h, v12.h[6]
+#   v13: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ea2b769		sqrdmulh v9.4s, v27.4s, v2.4s
+#    v9: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4fa7d2e3		sqrdmulh v3.4s, v23.4s, v7.s[1]
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e67b402		sqrdmulh v2.8h, v0.8h, v7.8h
+#    v2: 0x0000000000000000000000000000fff1
+0x~~~~~~~~~~~~~~~~  4f68d130		sqrdmulh v16.8h, v9.8h, v8.h[2]
+#   v16: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5e2d5ea8		sqrshl b8, b21, b13
+#    v8: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5ef45cfd		sqrshl d29, d7, d20
+#   v29: 0x00000000000000007fffffffffffffff
+0x~~~~~~~~~~~~~~~~  5e6a5ddc		sqrshl h28, h14, h10
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5ea25e5a		sqrshl s26, s18, s2
+#   v26: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e3a5ff2		sqrshl v18.16b, v31.16b, v26.16b
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ee05c9c		sqrshl v28.2d, v4.2d, v0.2d
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ea05cc3		sqrshl v3.2s, v6.2s, v0.2s
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e765e41		sqrshl v1.4h, v18.4h, v22.4h
+#    v1: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ea75f30		sqrshl v16.4s, v25.4s, v7.4s
+#   v16: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e255ea0		sqrshl v0.8b, v21.8b, v5.8b
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e685e7e		sqrshl v30.8h, v19.8h, v8.8h
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5f0c9ea6		sqrshrn b6, h21, #4
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5f159e2e		sqrshrn h14, s17, #11
+#   v14: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5f369f79		sqrshrn s25, d27, #10
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f2e9da6		sqrshrn v6.2s, v13.2d, #18
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f119d25		sqrshrn v5.4h, v9.4s, #15
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f0f9d93		sqrshrn v19.8b, v12.8h, #1
+#   v19: 0x00000000000000000000000000480048
+0x~~~~~~~~~~~~~~~~  4f099eb3		sqrshrn2 v19.16b, v21.8h, #7
+#   v19: 0x00000000000000000000000000480048
+0x~~~~~~~~~~~~~~~~  4f339f1d		sqrshrn2 v29.4s, v24.2d, #13
+#   v29: 0x00000000000000007fffffffffffffff
+0x~~~~~~~~~~~~~~~~  4f169c4c		sqrshrn2 v12.8h, v2.4s, #10
+#   v12: 0x00000000000000400000009000000090
+0x~~~~~~~~~~~~~~~~  7f0b8d30		sqrshrun b16, h9, #5
+#   v16: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7f118f03		sqrshrun h3, s24, #15
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7f388e50		sqrshrun s16, d18, #8
+#   v16: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f388efc		sqrshrun v28.2s, v23.2d, #8
+#   v28: 0x0000000000000000000000000e598315
+0x~~~~~~~~~~~~~~~~  2f168f3f		sqrshrun v31.4h, v25.4s, #10
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f0e8ef3		sqrshrun v19.8b, v23.8h, #2
+#   v19: 0x0000000000000000000000000004ffff
+0x~~~~~~~~~~~~~~~~  6f088c18		sqrshrun2 v24.16b, v0.8h, #8
+#   v24: 0x0000000000000000ffffffffffffffa0
+0x~~~~~~~~~~~~~~~~  6f298c36		sqrshrun2 v22.4s, v1.2d, #23
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f138ebc		sqrshrun2 v28.8h, v21.4s, #13
+#   v28: 0x0000000000000000000000000e598315
+0x~~~~~~~~~~~~~~~~  5e284ea6		sqshl b6, b21, b8
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5f0a774b		sqshl b11, b26, #2
+#   v11: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5ee44c1d		sqshl d29, d0, d4
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5f6374f5		sqshl d21, d7, #35
+#   v21: 0x00000000000000000007fed000000000
+0x~~~~~~~~~~~~~~~~  5e714f34		sqshl h20, h25, h17
+#   v20: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5f187414		sqshl h20, h0, #8
+#   v20: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5ea44dbd		sqshl s29, s13, s4
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5f34756a		sqshl s10, s11, #20
+#   v10: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e3c4e48		sqshl v8.16b, v18.16b, v28.16b
+#    v8: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f0a77bd		sqshl v29.16b, v29.16b, #2
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ef04fe8		sqshl v8.2d, v31.2d, v16.2d
+#    v8: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f6575c7		sqshl v7.2d, v14.2d, #37
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ea74f40		sqshl v0.2s, v26.2s, v7.2s
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f337565		sqshl v5.2s, v11.2s, #19
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e604fcb		sqshl v11.4h, v30.4h, v0.4h
+#   v11: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f177641		sqshl v1.4h, v18.4h, #7
+#    v1: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ebe4c76		sqshl v22.4s, v3.4s, v30.4s
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f3c75f0		sqshl v16.4s, v15.4s, #28
+#   v16: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e394f86		sqshl v6.8b, v28.8b, v25.8b
+#    v6: 0x0000000000000000000000000e598315
+0x~~~~~~~~~~~~~~~~  0f0875e0		sqshl v0.8b, v15.8b, #0
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e7e4e06		sqshl v6.8h, v16.8h, v30.8h
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f1e7683		sqshl v3.8h, v20.8h, #14
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7f0e65cd		sqshlu b13, b14, #6
+#   v13: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7f6c6600		sqshlu d0, d16, #44
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7f1f67a5		sqshlu h5, h29, #15
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7f2d651d		sqshlu s29, s8, #13
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f0a669b		sqshlu v27.16b, v20.16b, #2
+#   v27: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f4b6598		sqshlu v24.2d, v12.2d, #11
+#   v24: 0x00000000000200000004800000048000
+0x~~~~~~~~~~~~~~~~  2f36666c		sqshlu v12.2s, v19.2s, #22
+#   v12: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  2f1b6588		sqshlu v8.4h, v12.4h, #11
+#    v8: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f286472		sqshlu v18.4s, v3.4s, #8
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f096543		sqshlu v3.8b, v10.8b, #1
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f14671e		sqshlu v30.8h, v24.8h, #4
+#   v30: 0x00000000002000000040000000400000
+0x~~~~~~~~~~~~~~~~  5f0f9781		sqshrn b1, h28, #1
+#    v1: 0x00000000000000000000000000000080
+0x~~~~~~~~~~~~~~~~  5f1694ff		sqshrn h31, s7, #10
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5f289544		sqshrn s4, d10, #24
+#    v4: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f23942a		sqshrn v10.2s, v1.2d, #29
+#   v10: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f1295a3		sqshrn v3.4h, v13.4s, #14
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f0994db		sqshrn v27.8b, v6.8h, #7
+#   v27: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f0f96ee		sqshrn2 v14.16b, v23.8h, #1
+#   v14: 0x0000000000077f7f0000000000000000
+0x~~~~~~~~~~~~~~~~  4f2596d9		sqshrn2 v25.4s, v22.2d, #27
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f16959f		sqshrn2 v31.8h, v12.4s, #10
+#   v31: 0x000000000000ffff0000000000000000
+0x~~~~~~~~~~~~~~~~  7f0f8409		sqshrun b9, h0, #1
+#    v9: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7f1984cb		sqshrun h11, s6, #7
+#   v11: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7f33858d		sqshrun s13, d12, #13
+#   v13: 0x0000000000000000000000000007ffff
+0x~~~~~~~~~~~~~~~~  2f3f87ca		sqshrun v10.2s, v30.2d, #1
+#   v10: 0x000000000000000000100000ffffffff
+0x~~~~~~~~~~~~~~~~  2f15847f		sqshrun v31.4h, v3.4s, #11
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f0887dc		sqshrun v28.8b, v30.8h, #8
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f0d8770		sqshrun2 v16.16b, v27.8h, #3
+#   v16: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f2e85db		sqshrun2 v27.4s, v14.2d, #18
+#   v27: 0x00000001000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f1f85d7		sqshrun2 v23.8h, v14.4s, #1
+#   v23: 0x0000ffff000000000000000e59831500
+0x~~~~~~~~~~~~~~~~  5e2b2fb3		sqsub b19, b29, b11
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5ee62ff5		sqsub d21, d31, d6
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5e732d52		sqsub h18, h10, h19
+#   v18: 0x0000000000000000000000000000ffff
+0x~~~~~~~~~~~~~~~~  5ea02ca6		sqsub s6, s5, s0
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e202ed5		sqsub v21.16b, v22.16b, v0.16b
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ef12d56		sqsub v22.2d, v10.2d, v17.2d
+#   v22: 0x000000000000000000100000ffffffff
+0x~~~~~~~~~~~~~~~~  0ea22ea8		sqsub v8.2s, v21.2s, v2.2s
+#    v8: 0x000000000000000000000000ffff000f
+0x~~~~~~~~~~~~~~~~  0e7b2f32		sqsub v18.4h, v25.4h, v27.4h
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ea62c6d		sqsub v13.4s, v3.4s, v6.4s
+#   v13: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e302fbc		sqsub v28.8b, v29.8b, v16.8b
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e6a2cd1		sqsub v17.8h, v6.8h, v10.8h
+#   v17: 0x0000000000000000fff0000000010001
+0x~~~~~~~~~~~~~~~~  5e214b5b		sqxtn b27, h26
+#   v27: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5e614971		sqxtn h17, s11
+#   v17: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5ea14bf6		sqxtn s22, d31
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ea148ba		sqxtn v26.2s, v5.2d
+#   v26: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e6148ed		sqxtn v13.4h, v7.4s
+#   v13: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e214a73		sqxtn v19.8b, v19.8h
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e214873		sqxtn2 v19.16b, v3.8h
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ea14837		sqxtn2 v23.4s, v1.2d
+#   v23: 0x00000000000000800000000e59831500
+0x~~~~~~~~~~~~~~~~  4e61486d		sqxtn2 v13.8h, v3.4s
+#   v13: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7e21293a		sqxtun b26, h9
+#   v26: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7e612993		sqxtun h19, s12
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7ea128c3		sqxtun s3, d6
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2ea12b5d		sqxtun v29.2s, v26.2d
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e61295a		sqxtun v26.4h, v10.4s
+#   v26: 0x000000000000000000000000ffff0000
+0x~~~~~~~~~~~~~~~~  2e212ba7		sqxtun v7.8b, v29.8h
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e2129d5		sqxtun2 v21.16b, v14.8h
+#   v21: 0x000007ff000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ea129f8		sqxtun2 v24.4s, v15.2d
+#   v24: 0x00000000000000000004800000048000
+0x~~~~~~~~~~~~~~~~  6e61283e		sqxtun2 v30.8h, v1.4s
+#   v30: 0x00000000000000800040000000400000
+0x~~~~~~~~~~~~~~~~  4e2f1635		srhadd v21.16b, v17.16b, v15.16b
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ebd16bc		srhadd v28.2s, v21.2s, v29.2s
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e7e1429		srhadd v9.4h, v1.4h, v30.4h
+#    v9: 0x00000000000000000020000000200040
+0x~~~~~~~~~~~~~~~~  4ea21418		srhadd v24.4s, v0.4s, v2.4s
+#   v24: 0x00000000000000000000000000007ff9
+0x~~~~~~~~~~~~~~~~  0e2f1626		srhadd v6.8b, v17.8b, v15.8b
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e7514e5		srhadd v5.8h, v7.8h, v21.8h
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7f4f45ce		sri d14, d14, #49
+#   v14: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f0c4517		sri v23.16b, v8.16b, #4
+#   v23: 0x0000000000000080000000005f8f1000
+0x~~~~~~~~~~~~~~~~  6f6c45b4		sri v20.2d, v13.2d, #20
+#   v20: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f284450		sri v16.2s, v2.2s, #24
+#   v16: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f1546e5		sri v5.4h, v23.4h, #11
+#    v5: 0x000000000000000000000000000b0002
+0x~~~~~~~~~~~~~~~~  6f2945fb		sri v27.4s, v15.4s, #23
+#   v27: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f0c47b3		sri v19.8b, v29.8b, #4
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f1d47a7		sri v7.8h, v29.8h, #3
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5efa5522		srshl d2, d9, d26
+#    v2: 0x00000000000000000020000000200040
+0x~~~~~~~~~~~~~~~~  4e2b563d		srshl v29.16b, v17.16b, v11.16b
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ee455e8		srshl v8.2d, v15.2d, v4.2d
+#    v8: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ea85639		srshl v25.2s, v17.2s, v8.2s
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e6754f3		srshl v19.4h, v7.4h, v7.4h
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4eb1544d		srshl v13.4s, v2.4s, v17.4s
+#   v13: 0x00000000000000000020000000200040
+0x~~~~~~~~~~~~~~~~  0e3554d6		srshl v22.8b, v6.8b, v21.8b
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e64562a		srshl v10.8h, v17.8h, v4.8h
+#   v10: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5f532655		srshr d21, d18, #45
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f092563		srshr v3.16b, v11.16b, #7
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f4b2755		srshr v21.2d, v26.2d, #53
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f2424ab		srshr v11.2s, v5.2s, #28
+#   v11: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f142647		srshr v7.4h, v18.4h, #12
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f222467		srshr v7.4s, v3.4s, #30
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f0a244e		srshr v14.8b, v2.8b, #6
+#   v14: 0x00000000000000000001000000010001
+0x~~~~~~~~~~~~~~~~  4f1d2695		srshr v21.8h, v20.8h, #3
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5f4137d5		srsra d21, d30, #63
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f0a37db		srsra v27.16b, v30.16b, #6
+#   v27: 0x00000000000000fe0001000000010000
+0x~~~~~~~~~~~~~~~~  4f653594		srsra v20.2d, v12.2d, #27
+#   v20: 0x00000000000000000000000000000020
+0x~~~~~~~~~~~~~~~~  0f3b3620		srsra v0.2s, v17.2s, #5
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f11360e		srsra v14.4h, v16.4h, #15
+#   v14: 0x00000000000000000001000000010001
+0x~~~~~~~~~~~~~~~~  4f2c3472		srsra v18.4s, v3.4s, #20
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f0f3435		srsra v21.8b, v1.8b, #1
+#   v21: 0x000000000000000000000000000000c0
+0x~~~~~~~~~~~~~~~~  4f1e373f		srsra v31.8h, v25.8h, #2
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5ee945a1		sshl d1, d13, d9
+#    v1: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e2f47f1		sshl v17.16b, v31.16b, v15.16b
+#   v17: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ee0460d		sshl v13.2d, v16.2d, v0.2d
+#   v13: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0eb644e0		sshl v0.2s, v7.2s, v22.2s
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e644677		sshl v23.4h, v19.4h, v4.4h
+#   v23: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4eab44a5		sshl v5.4s, v5.4s, v11.4s
+#    v5: 0x000000000000000000000000000b0002
+0x~~~~~~~~~~~~~~~~  0e274777		sshl v23.8b, v27.8b, v7.8b
+#   v23: 0x00000000000000000001000000010000
+0x~~~~~~~~~~~~~~~~  4e65455d		sshl v29.8h, v10.8h, v5.8h
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f37a440		sshll v0.2d, v2.2s, #23
+#    v0: 0x00001000000000000000100020000000
+0x~~~~~~~~~~~~~~~~  0f18a50b		sshll v11.4s, v8.4h, #8
+#   v11: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f09a7a4		sshll v4.8h, v29.8b, #1
+#    v4: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f2ea48a		sshll2 v10.2d, v4.4s, #14
+#   v10: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f16a7fa		sshll2 v26.4s, v31.8h, #6
+#   v26: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f0ca743		sshll2 v3.8h, v26.16b, #4
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5f6c06b3		sshr d19, d21, #20
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f0b06ef		sshr v15.16b, v23.16b, #5
+#   v15: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f5a05d1		sshr v17.2d, v14.2d, #38
+#   v17: 0x00000000000000000000000000000400
+0x~~~~~~~~~~~~~~~~  0f2907a3		sshr v3.2s, v29.2s, #23
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f1c0777		sshr v23.4h, v27.4h, #4
+#   v23: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f3c047c		sshr v28.4s, v3.4s, #4
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f0a044e		sshr v14.8b, v2.8b, #6
+#   v14: 0x00000000000000000000000000000001
+0x~~~~~~~~~~~~~~~~  4f1a0503		sshr v3.8h, v8.8h, #6
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5f54178c		ssra d12, d28, #44
+#   v12: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  4f0c17fd		ssra v29.16b, v31.16b, #4
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f681403		ssra v3.2d, v0.2d, #24
+#    v3: 0x00000000001000000000000000100020
+0x~~~~~~~~~~~~~~~~  0f3a178e		ssra v14.2s, v28.2s, #6
+#   v14: 0x00000000000000000000000000000001
+0x~~~~~~~~~~~~~~~~  0f191512		ssra v18.4h, v8.4h, #7
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f2815df		ssra v31.4s, v14.4s, #24
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f0b175c		ssra v28.8b, v26.8b, #5
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f121529		ssra v9.8h, v9.8h, #14
+#    v9: 0x00000000000000000020000000200040
+0x~~~~~~~~~~~~~~~~  0ea321cd		ssubl v13.2d, v14.2s, v3.2s
+#   v13: 0x0000000000000000ffffffffffefffe1
+0x~~~~~~~~~~~~~~~~  0e682205		ssubl v5.4s, v16.4h, v8.4h
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e262380		ssubl v0.8h, v28.8b, v6.8b
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4eb921a5		ssubl2 v5.2d, v13.4s, v25.4s
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e7121e3		ssubl2 v3.4s, v15.8h, v17.8h
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e2e21ef		ssubl2 v15.8h, v15.16b, v14.16b
+#   v15: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0eba32f9		ssubw v25.2d, v23.2d, v26.2s
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e783255		ssubw v21.4s, v18.4s, v24.4h
+#   v21: 0x000000000000000000000000ffff8007
+0x~~~~~~~~~~~~~~~~  0e2332de		ssubw v30.8h, v22.8h, v3.8b
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ebc3310		ssubw2 v16.2d, v24.2d, v28.4s
+#   v16: 0x00000000000000000000000000007ff9
+0x~~~~~~~~~~~~~~~~  4e6f317f		ssubw2 v31.4s, v11.4s, v15.8h
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e303104		ssubw2 v4.8h, v8.8h, v16.16b
+#    v4: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4c002012		st1 {v18.16b, v19.16b, v20.16b, v21.16b}, [x0]
+#   v18: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v20: 0x00000000000000000000000000000020 -> 0x~~~~~~~~~~~~~~~~
+#   v21: 0x000000000000000000000000ffff8007 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c82202a		st1 {v10.16b, v11.16b, v12.16b, v13.16b}, [x1], x2
+#   v10: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v11: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v12: 0x000000000000000000000000ffffffff -> 0x~~~~~~~~~~~~~~~~
+#   v13: 0x0000000000000000ffffffffffefffe1 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9f203b		st1 {v27.16b, v28.16b, v29.16b, v30.16b}, [x1], #64
+#   v27: 0x00000000000000fe0001000000010000 -> 0x~~~~~~~~~~~~~~~~
+#   v28: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v29: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v30: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c006010		st1 {v16.16b, v17.16b, v18.16b}, [x0]
+#   v16: 0x00000000000000000000000000007ff9 -> 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000000000000000000400 -> 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c826035		st1 {v21.16b, v22.16b, v23.16b}, [x1], x2
+#   v21: 0x000000000000000000000000ffff8007 -> 0x~~~~~~~~~~~~~~~~
+#   v22: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v23: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9f6029		st1 {v9.16b, v10.16b, v11.16b}, [x1], #48
+#    v9: 0x00000000000000000020000000200040 -> 0x~~~~~~~~~~~~~~~~
+#   v10: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v11: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c00a007		st1 {v7.16b, v8.16b}, [x0]
+#    v7: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c82a03a		st1 {v26.16b, v27.16b}, [x1], x2
+#   v26: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v27: 0x00000000000000fe0001000000010000 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9fa036		st1 {v22.16b, v23.16b}, [x1], #32
+#   v22: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v23: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c007017		st1 {v23.16b}, [x0]
+#   v23: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c82703c		st1 {v28.16b}, [x1], x2
+#   v28: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9f7022		st1 {v2.16b}, [x1], #16
+#    v2: 0x00000000000000000020000000200040 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c002c1d		st1 {v29.1d, v30.1d, v31.1d, v0.1d}, [x0]
+#   v29:                 0x0000000000000000 (d29: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#   v30:                 0x0000000000000000 (d30: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#   v31:                 0x0000000000000000 (d31: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v0:                 0x0000000000000000 (d0: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c822c2c		st1 {v12.1d, v13.1d, v14.1d, v15.1d}, [x1], x2
+#   v12:                 0x00000000ffffffff (d12: 2.12200e-314) -> 0x~~~~~~~~~~~~~~~~
+#   v13:                 0xffffffffffefffe1 (d13: -nan) -> 0x~~~~~~~~~~~~~~~~
+#   v14:                 0x0000000000000001 (d14: 4.94066e-324) -> 0x~~~~~~~~~~~~~~~~
+#   v15:                 0x0000000000000000 (d15: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c9f2c3e		st1 {v30.1d, v31.1d, v0.1d, v1.1d}, [x1], #32
+#   v30:                 0x0000000000000000 (d30: 0.00000) -> 0x~~~~~~~~~~~~~~~~
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+#   v17: 0x00000000000000000000000000000400 -> 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c00741d		st1 {v29.8h}, [x0]
+#   v29: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c827433		st1 {v19.8h}, [x1], x2
+#   v19: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9f7437		st1 {v23.8h}, [x1], #16
+#   v23: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d001c13		st1 {v19.b}[15], [x0]
+#   v19: 0x00                               -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d820439		st1 {v25.b}[9], [x1], x2
+#   v25:             0x00                   -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d9f0024		st1 {v4.b}[8], [x1], #1
+#    v4:               0x00                 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d00840d		st1 {v13.d}[0], [x0]
+#   v13:                 0xffffffffffefffe1 (d13: -nan) -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d82843e		st1 {v30.d}[0], [x1], x2
+#   v30:                 0x0000000000000000 (d30: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d9f8423		st1 {v3.d}[0], [x1], #8
+#    v3:                 0x0000000000000000 (d3: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d004016		st1 {v22.h}[0], [x0]
+#   v22:                             0x0000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d82583f		st1 {v31.h}[7], [x1], x2
+#   v31: 0x0000                             -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d9f5837		st1 {v23.h}[3], [x1], #2
+#   v23:                 0x0000             -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d008000		st1 {v0.s}[0], [x0]
+#    v0:                         0x00000000 (s0: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d82902b		st1 {v11.s}[3], [x1], x2
+#   v11: 0x00000000                         (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d9f9038		st1 {v24.s}[3], [x1], #4
+#   v24: 0x00000000                         (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c008007		st2 {v7.16b, v8.16b}, [x0]
+#    v7: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c828025		st2 {v5.16b, v6.16b}, [x1], x2
+#    v5: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9f8032		st2 {v18.16b, v19.16b}, [x1], #32
+#   v18: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c008c0e		st2 {v14.2d, v15.2d}, [x0]
+#   v14: 0x00000000000000000000000000000001 (0.00000, 4.94066e-324) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x00000000000000000000000000000000 (0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c828c27		st2 {v7.2d, v8.2d}, [x1], x2
+#    v7: 0x00000000000000000000000000000000 (0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00000000000000000000000000000000 (0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9f8c38		st2 {v24.2d, v25.2d}, [x1], #32
+#   v24: 0x00000000000000000000000000007ff9 (0.00000, 1.61861e-319) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x00000000000000000000000000000000 (0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c008816		st2 {v22.2s, v23.2s}, [x0]
+#   v22: 0x00000000000000000000000000000000 (..., 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x00000000000000000000000000000000 (..., 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c828824		st2 {v4.2s, v5.2s}, [x1], x2
+#    v4: 0x00000000000000000000000000000000 (..., 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x00000000000000000000000000000000 (..., 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c9f8822		st2 {v2.2s, v3.2s}, [x1], #16
+#    v2: 0x00000000000000000020000000200040 (..., 2.93874e-39, 2.93883e-39) <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x00000000000000000000000000000000 (..., 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c008417		st2 {v23.4h, v24.4h}, [x0]
+#   v23: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00000000000000000000000000007ff9 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c828428		st2 {v8.4h, v9.4h}, [x1], x2
+#    v8: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000000020000000200040 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c9f8427		st2 {v7.4h, v8.4h}, [x1], #16
+#    v7: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c008811		st2 {v17.4s, v18.4s}, [x0]
+#   v17: 0x00000000000000000000000000000400 (0.00000, 0.00000, 0.00000, 1.43493e-42) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c828826		st2 {v6.4s, v7.4s}, [x1], x2
+#    v6: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9f883a		st2 {v26.4s, v27.4s}, [x1], #32
+#   v26: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x00000000000000fe0001000000010000 (0.00000, 3.55930e-43, 9.18355e-41, 9.18355e-41) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c00801f		st2 {v31.8b, v0.8b}, [x0]
+#   v31: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c828020		st2 {v0.8b, v1.8b}, [x1], x2
+#    v0: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c9f8035		st2 {v21.8b, v22.8b}, [x1], #16
+#   v21: 0x000000000000000000000000ffff8007 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c008407		st2 {v7.8h, v8.8h}, [x0]
+#    v7: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c828436		st2 {v22.8h, v23.8h}, [x1], x2
+#   v22: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9f8424		st2 {v4.8h, v5.8h}, [x1], #32
+#    v4: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d201c08		st2 {v8.b, v9.b}[15], [x0]
+#    v8: 0x00                               -> 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00                               -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4da21c28		st2 {v8.b, v9.b}[15], [x1], x2
+#    v8: 0x00                               -> 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00                               -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dbf1027		st2 {v7.b, v8.b}[4], [x1], #2
+#    v7:                       0x00         -> 0x~~~~~~~~~~~~~~~~
+#    v8:                       0x00         -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d208419		st2 {v25.d, v26.d}[0], [x0]
+#   v25:                 0x0000000000000000 (d25: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#   v26:                 0x0000000000000000 (d26: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4da28431		st2 {v17.d, v18.d}[1], [x1], x2
+#   v17: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#   v18: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dbf8423		st2 {v3.d, v4.d}[1], [x1], #16
+#    v3: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d205804		st2 {v4.h, v5.h}[3], [x0]
+#    v4:                 0x0000             -> 0x~~~~~~~~~~~~~~~~
+#    v5:                 0x0000             -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4da24820		st2 {v0.h, v1.h}[5], [x1], x2
+#    v0:         0x0000                     -> 0x~~~~~~~~~~~~~~~~
+#    v1:         0x0000                     -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dbf5036		st2 {v22.h, v23.h}[2], [x1], #4
+#   v22:                     0x0000         -> 0x~~~~~~~~~~~~~~~~
+#   v23:                     0x0000         -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d20900e		st2 {v14.s, v15.s}[3], [x0]
+#   v14: 0x00000000                         (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#   v15: 0x00000000                         (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4da29037		st2 {v23.s, v24.s}[3], [x1], x2
+#   v23: 0x00000000                         (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00000000                         (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dbf8020		st2 {v0.s, v1.s}[2], [x1], #8
+#    v0:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    v1:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c00401a		st3 {v26.16b, v27.16b, v28.16b}, [x0]
+#   v26: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x00000000000000fe0001000000010000 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c824035		st3 {v21.16b, v22.16b, v23.16b}, [x1], x2
+#   v21: 0x000000000000000000000000ffff8007 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9f4038		st3 {v24.16b, v25.16b, v26.16b}, [x1], #48
+#   v24: 0x00000000000000000000000000007ff9 <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c004c11		st3 {v17.2d, v18.2d, v19.2d}, [x0]
+#   v17: 0x00000000000000000000000000000400 (0.00000, 5.05923e-321) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000000000000000000000 (0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000000000000000000000 (0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c824c37		st3 {v23.2d, v24.2d, v25.2d}, [x1], x2
+#   v23: 0x00000000000000000000000000000000 (0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00000000000000000000000000007ff9 (0.00000, 1.61861e-319) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x00000000000000000000000000000000 (0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9f4c2a		st3 {v10.2d, v11.2d, v12.2d}, [x1], #48
+#   v10: 0x00000000000000000000000000000000 (0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x00000000000000000000000000000000 (0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x000000000000000000000000ffffffff (0.00000, 2.12200e-314) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c004809		st3 {v9.2s, v10.2s, v11.2s}, [x0]
+#    v9: 0x00000000000000000020000000200040 (..., 2.93874e-39, 2.93883e-39) <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x00000000000000000000000000000000 (..., 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x00000000000000000000000000000000 (..., 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c82482d		st3 {v13.2s, v14.2s, v15.2s}, [x1], x2
+#   v13: 0x0000000000000000ffffffffffefffe1 (..., -nan, -nan) <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x00000000000000000000000000000001 (..., 0.00000, 1.40130e-45) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x00000000000000000000000000000000 (..., 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c9f4836		st3 {v22.2s, v23.2s, v24.2s}, [x1], #24
+#   v22: 0x00000000000000000000000000000000 (..., 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x00000000000000000000000000000000 (..., 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00000000000000000000000000007ff9 (..., 0.00000, 4.59079e-41) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c00441f		st3 {v31.4h, v0.4h, v1.4h}, [x0]
+#   v31: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c824428		st3 {v8.4h, v9.4h, v10.4h}, [x1], x2
+#    v8: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000000020000000200040 <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c9f4433		st3 {v19.4h, v20.4h, v21.4h}, [x1], #24
+#   v19: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x00000000000000000000000000000020 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x000000000000000000000000ffff8007 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c004812		st3 {v18.4s, v19.4s, v20.4s}, [x0]
+#   v18: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x00000000000000000000000000000020 (0.00000, 0.00000, 0.00000, 4.48416e-44) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c824839		st3 {v25.4s, v26.4s, v27.4s}, [x1], x2
+#   v25: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x00000000000000fe0001000000010000 (0.00000, 3.55930e-43, 9.18355e-41, 9.18355e-41) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9f4830		st3 {v16.4s, v17.4s, v18.4s}, [x1], #48
+#   v16: 0x00000000000000000000000000007ff9 (0.00000, 0.00000, 0.00000, 4.59079e-41) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000000000000000000400 (0.00000, 0.00000, 0.00000, 1.43493e-42) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c00401b		st3 {v27.8b, v28.8b, v29.8b}, [x0]
+#   v27: 0x00000000000000fe0001000000010000 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c82403d		st3 {v29.8b, v30.8b, v31.8b}, [x1], x2
+#   v29: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c9f403e		st3 {v30.8b, v31.8b, v0.8b}, [x1], #24
+#   v30: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c004408		st3 {v8.8h, v9.8h, v10.8h}, [x0]
+#    v8: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000000020000000200040 <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c824432		st3 {v18.8h, v19.8h, v20.8h}, [x1], x2
+#   v18: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x00000000000000000000000000000020 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9f4432		st3 {v18.8h, v19.8h, v20.8h}, [x1], #48
+#   v18: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x00000000000000000000000000000020 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d00281f		st3 {v31.b, v0.b, v1.b}[10], [x0]
+#   v31:           0x00                     -> 0x~~~~~~~~~~~~~~~~
+#    v0:           0x00                     -> 0x~~~~~~~~~~~~~~~~
+#    v1:           0x00                     -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d823424		st3 {v4.b, v5.b, v6.b}[5], [x1], x2
+#    v4:                     0x00           -> 0x~~~~~~~~~~~~~~~~
+#    v5:                     0x00           -> 0x~~~~~~~~~~~~~~~~
+#    v6:                     0x00           -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d9f2425		st3 {v5.b, v6.b, v7.b}[1], [x1], #3
+#    v5:                             0x00   -> 0x~~~~~~~~~~~~~~~~
+#    v6:                             0x00   -> 0x~~~~~~~~~~~~~~~~
+#    v7:                             0x00   -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d00a405		st3 {v5.d, v6.d, v7.d}[0], [x0]
+#    v5:                 0x0000000000000000 (d5: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v6:                 0x0000000000000000 (d6: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v7:                 0x0000000000000000 (d7: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d82a426		st3 {v6.d, v7.d, v8.d}[0], [x1], x2
+#    v6:                 0x0000000000000000 (d6: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v7:                 0x0000000000000000 (d7: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v8:                 0x0000000000000000 (d8: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d9fa420		st3 {v0.d, v1.d, v2.d}[0], [x1], #24
+#    v0:                 0x0000000000000000 (d0: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v1:                 0x0000000000000000 (d1: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v2:                 0x0020000000200040 (d2: 4.45015e-308) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d00701f		st3 {v31.h, v0.h, v1.h}[2], [x0]
+#   v31:                     0x0000         -> 0x~~~~~~~~~~~~~~~~
+#    v0:                     0x0000         -> 0x~~~~~~~~~~~~~~~~
+#    v1:                     0x0000         -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d82682e		st3 {v14.h, v15.h, v16.h}[5], [x1], x2
+#   v14:         0x0000                     -> 0x~~~~~~~~~~~~~~~~
+#   v15:         0x0000                     -> 0x~~~~~~~~~~~~~~~~
+#   v16:         0x0000                     -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d9f7035		st3 {v21.h, v22.h, v23.h}[6], [x1], #6
+#   v21:     0x0000                         -> 0x~~~~~~~~~~~~~~~~
+#   v22:     0x0000                         -> 0x~~~~~~~~~~~~~~~~
+#   v23:     0x0000                         -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d00a015		st3 {v21.s, v22.s, v23.s}[0], [x0]
+#   v21:                         0xffff8007 (s21: -nan) -> 0x~~~~~~~~~~~~~~~~
+#   v22:                         0x00000000 (s22: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#   v23:                         0x00000000 (s23: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d82b02b		st3 {v11.s, v12.s, v13.s}[1], [x1], x2
+#   v11:                 0x00000000         (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#   v12:                 0x00000000         (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#   v13:                 0xffffffff         (..., -nan, ...) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d9fa02f		st3 {v15.s, v16.s, v17.s}[0], [x1], #12
+#   v15:                         0x00000000 (s15: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#   v16:                         0x00007ff9 (s16: 4.59079e-41) -> 0x~~~~~~~~~~~~~~~~
+#   v17:                         0x00000400 (s17: 1.43493e-42) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c000016		st4 {v22.16b, v23.16b, v24.16b, v25.16b}, [x0]
+#   v22: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00000000000000000000000000007ff9 <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c820038		st4 {v24.16b, v25.16b, v26.16b, v27.16b}, [x1], x2
+#   v24: 0x00000000000000000000000000007ff9 <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x00000000000000fe0001000000010000 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9f002f		st4 {v15.16b, v16.16b, v17.16b, v18.16b}, [x1], #64
+#   v15: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x00000000000000000000000000007ff9 <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000000000000000000400 <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c000c10		st4 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0]
+#   v16: 0x00000000000000000000000000007ff9 (0.00000, 1.61861e-319) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000000000000000000400 (0.00000, 5.05923e-321) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000000000000000000000 (0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000000000000000000000 (0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c820c31		st4 {v17.2d, v18.2d, v19.2d, v20.2d}, [x1], x2
+#   v17: 0x00000000000000000000000000000400 (0.00000, 5.05923e-321) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000000000000000000000 (0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000000000000000000000 (0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x00000000000000000000000000000020 (0.00000, 1.58101e-322) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9f0c29		st4 {v9.2d, v10.2d, v11.2d, v12.2d}, [x1], #64
+#    v9: 0x00000000000000000020000000200040 (0.00000, 4.45015e-308) <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x00000000000000000000000000000000 (0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x00000000000000000000000000000000 (0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x000000000000000000000000ffffffff (0.00000, 2.12200e-314) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c000817		st4 {v23.2s, v24.2s, v25.2s, v26.2s}, [x0]
+#   v23: 0x00000000000000000000000000000000 (..., 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00000000000000000000000000007ff9 (..., 0.00000, 4.59079e-41) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x00000000000000000000000000000000 (..., 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000000000000000000000 (..., 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c82082f		st4 {v15.2s, v16.2s, v17.2s, v18.2s}, [x1], x2
+#   v15: 0x00000000000000000000000000000000 (..., 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x00000000000000000000000000007ff9 (..., 0.00000, 4.59079e-41) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000000000000000000400 (..., 0.00000, 1.43493e-42) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000000000000000000000 (..., 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c9f0838		st4 {v24.2s, v25.2s, v26.2s, v27.2s}, [x1], #32
+#   v24: 0x00000000000000000000000000007ff9 (..., 0.00000, 4.59079e-41) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x00000000000000000000000000000000 (..., 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000000000000000000000 (..., 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x00000000000000fe0001000000010000 (..., 9.18355e-41, 9.18355e-41) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c00040e		st4 {v14.4h, v15.4h, v16.4h, v17.4h}, [x0]
+#   v14: 0x00000000000000000000000000000001 <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x00000000000000000000000000007ff9 <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000000000000000000400 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c820432		st4 {v18.4h, v19.4h, v20.4h, v21.4h}, [x1], x2
+#   v18: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x00000000000000000000000000000020 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x000000000000000000000000ffff8007 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c9f0421		st4 {v1.4h, v2.4h, v3.4h, v4.4h}, [x1], #32
+#    v1: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x00000000000000000020000000200040 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c00080d		st4 {v13.4s, v14.4s, v15.4s, v16.4s}, [x0]
+#   v13: 0x0000000000000000ffffffffffefffe1 (0.00000, 0.00000, -nan, -nan) <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x00000000000000000000000000000001 (0.00000, 0.00000, 0.00000, 1.40130e-45) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x00000000000000000000000000007ff9 (0.00000, 0.00000, 0.00000, 4.59079e-41) <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c820826		st4 {v6.4s, v7.4s, v8.4s, v9.4s}, [x1], x2
+#    v6: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000000020000000200040 (0.00000, 0.00000, 2.93874e-39, 2.93883e-39) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9f082f		st4 {v15.4s, v16.4s, v17.4s, v18.4s}, [x1], #64
+#   v15: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x00000000000000000000000000007ff9 (0.00000, 0.00000, 0.00000, 4.59079e-41) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000000000000000000400 (0.00000, 0.00000, 0.00000, 1.43493e-42) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c00001a		st4 {v26.8b, v27.8b, v28.8b, v29.8b}, [x0]
+#   v26: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x00000000000000fe0001000000010000 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c820039		st4 {v25.8b, v26.8b, v27.8b, v28.8b}, [x1], x2
+#   v25: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x00000000000000fe0001000000010000 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0c9f0033		st4 {v19.8b, v20.8b, v21.8b, v22.8b}, [x1], #32
+#   v19: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x00000000000000000000000000000020 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x000000000000000000000000ffff8007 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c000413		st4 {v19.8h, v20.8h, v21.8h, v22.8h}, [x0]
+#   v19: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x00000000000000000000000000000020 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x000000000000000000000000ffff8007 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c82042f		st4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x1], x2
+#   v15: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x00000000000000000000000000007ff9 <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000000000000000000400 <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4c9f043f		st4 {v31.8h, v0.8h, v1.8h, v2.8h}, [x1], #64
+#   v31: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x00000000000000000020000000200040 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d203400		st4 {v0.b, v1.b, v2.b, v3.b}[13], [x0]
+#    v0:     0x00                           -> 0x~~~~~~~~~~~~~~~~
+#    v1:     0x00                           -> 0x~~~~~~~~~~~~~~~~
+#    v2:     0x00                           -> 0x~~~~~~~~~~~~~~~~
+#    v3:     0x00                           -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4da22824		st4 {v4.b, v5.b, v6.b, v7.b}[10], [x1], x2
+#    v4:           0x00                     -> 0x~~~~~~~~~~~~~~~~
+#    v5:           0x00                     -> 0x~~~~~~~~~~~~~~~~
+#    v6:           0x00                     -> 0x~~~~~~~~~~~~~~~~
+#    v7:           0x00                     -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dbf2429		st4 {v9.b, v10.b, v11.b, v12.b}[9], [x1], #4
+#    v9:             0x00                   -> 0x~~~~~~~~~~~~~~~~
+#   v10:             0x00                   -> 0x~~~~~~~~~~~~~~~~
+#   v11:             0x00                   -> 0x~~~~~~~~~~~~~~~~
+#   v12:             0x00                   -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d20a402		st4 {v2.d, v3.d, v4.d, v5.d}[1], [x0]
+#    v2: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    v5: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0da2a427		st4 {v7.d, v8.d, v9.d, v10.d}[0], [x1], x2
+#    v7:                 0x0000000000000000 (d7: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v8:                 0x0000000000000000 (d8: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v9:                 0x0020000000200040 (d9: 4.45015e-308) -> 0x~~~~~~~~~~~~~~~~
+#   v10:                 0x0000000000000000 (d10: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dbfa43f		st4 {v31.d, v0.d, v1.d, v2.d}[1], [x1], #32
+#   v31: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    v0: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    v1: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0d206802		st4 {v2.h, v3.h, v4.h, v5.h}[1], [x0]
+#    v2:                         0x0020     -> 0x~~~~~~~~~~~~~~~~
+#    v3:                         0x0000     -> 0x~~~~~~~~~~~~~~~~
+#    v4:                         0x0000     -> 0x~~~~~~~~~~~~~~~~
+#    v5:                         0x0000     -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0da2783b		st4 {v27.h, v28.h, v29.h, v30.h}[3], [x1], x2
+#   v27:                 0x0001             -> 0x~~~~~~~~~~~~~~~~
+#   v28:                 0x0000             -> 0x~~~~~~~~~~~~~~~~
+#   v29:                 0x0000             -> 0x~~~~~~~~~~~~~~~~
+#   v30:                 0x0000             -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4dbf6038		st4 {v24.h, v25.h, v26.h, v27.h}[4], [x1], #8
+#   v24:             0x0000                 -> 0x~~~~~~~~~~~~~~~~
+#   v25:             0x0000                 -> 0x~~~~~~~~~~~~~~~~
+#   v26:             0x0000                 -> 0x~~~~~~~~~~~~~~~~
+#   v27:             0x00fe                 -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4d20a012		st4 {v18.s, v19.s, v20.s, v21.s}[2], [x0]
+#   v18:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#   v19:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#   v20:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#   v21:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  4da2a026		st4 {v6.s, v7.s, v8.s, v9.s}[2], [x1], x2
+#    v6:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    v7:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    v8:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    v9:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  0dbfb039		st4 {v25.s, v26.s, v27.s, v28.s}[1], [x1], #16
+#   v25:                 0x00000000         (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#   v26:                 0x00000000         (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#   v27:                 0x00010000         (..., 9.18355e-41, ...) -> 0x~~~~~~~~~~~~~~~~
+#   v28:                 0x00000000         (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  7ee2862c		sub d12, d17, d2
+#   v12: 0x0000000000000000ffdfffffffe003c0
+0x~~~~~~~~~~~~~~~~  6e288714		sub v20.16b, v24.16b, v8.16b
+#   v20: 0x00000000000000000000000000007ff9
+0x~~~~~~~~~~~~~~~~  6ee587a8		sub v8.2d, v29.2d, v5.2d
+#    v8: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2eb88782		sub v2.2s, v28.2s, v24.2s
+#    v2: 0x000000000000000000000000ffff8007
+0x~~~~~~~~~~~~~~~~  2e648558		sub v24.4h, v10.4h, v4.4h
+#   v24: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6eb1849c		sub v28.4s, v4.4s, v17.4s
+#   v28: 0x000000000000000000000000fffffc00
+0x~~~~~~~~~~~~~~~~  2e228770		sub v16.8b, v27.8b, v2.8b
+#   v16: 0x000000000000000000010000010280f9
+0x~~~~~~~~~~~~~~~~  6e6d8554		sub v20.8h, v10.8h, v13.8h
+#   v20: 0x0000000000000000000100010011001f
+0x~~~~~~~~~~~~~~~~  0ead61c5		subhn v5.2s, v14.2d, v13.2d
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e6860aa		subhn v10.4h, v5.4s, v8.4s
+#   v10: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e366146		subhn v6.8b, v10.8h, v22.8h
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e2960cb		subhn2 v11.16b, v6.8h, v9.8h
+#   v11: 0x00000000ff00ffff0000000000000000
+0x~~~~~~~~~~~~~~~~  4eb86259		subhn2 v25.4s, v18.2d, v24.2d
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e6162b4		subhn2 v20.8h, v21.4s, v1.4s
+#   v20: 0x000000000000ffff000100010011001f
+0x~~~~~~~~~~~~~~~~  5e203979		suqadd b25, b11
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5ee0382d		suqadd d13, d1
+#   v13: 0x0000000000000000ffffffffffefffe1
+0x~~~~~~~~~~~~~~~~  5e603920		suqadd h0, h9
+#    v0: 0x00000000000000000000000000000040
+0x~~~~~~~~~~~~~~~~  5ea03916		suqadd s22, s8
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e203b78		suqadd v24.16b, v27.16b
+#   v24: 0x000000000000007f0001000000010000
+0x~~~~~~~~~~~~~~~~  4ee039da		suqadd v26.2d, v14.2d
+#   v26: 0x00000000000000000000000000000001
+0x~~~~~~~~~~~~~~~~  0ea03947		suqadd v7.2s, v10.2s
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e603999		suqadd v25.4h, v12.4h
+#   v25: 0x00000000000000007fff7fff7fff03c0
+0x~~~~~~~~~~~~~~~~  4ea03864		suqadd v4.4s, v3.4s
+#    v4: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e203a4e		suqadd v14.8b, v18.8b
+#   v14: 0x00000000000000000000000000000001
+0x~~~~~~~~~~~~~~~~  4e60391f		suqadd v31.8h, v8.8h
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f20a690		sxtl v16.2d, v20.2s
+#   v16: 0x0000000000010001000000000011001f
+0x~~~~~~~~~~~~~~~~  0f10a79b		sxtl v27.4s, v28.4h
+#   v27: 0x0000000000000000fffffffffffffc00
+0x~~~~~~~~~~~~~~~~  0f08a6c0		sxtl v0.8h, v22.8b
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f20a4e6		sxtl2 v6.2d, v7.4s
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f10a769		sxtl2 v9.4s, v27.8h
+#    v9: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f08a610		sxtl2 v16.8h, v16.16b
+#   v16: 0x00000000000000000000000100000001
+0x~~~~~~~~~~~~~~~~  4e166239		tbl v25.16b, {v17.16b, v18.16b, v19.16b, v20.16b}, v22.16b
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e0441bc		tbl v28.16b, {v13.16b, v14.16b, v15.16b}, v4.16b
+#   v28: 0xe1e1e1e1e1e1e1e1e1e1e1e1e1e1e1e1
+0x~~~~~~~~~~~~~~~~  4e022003		tbl v3.16b, {v0.16b, v1.16b}, v2.16b
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e0401f4		tbl v20.16b, {v15.16b}, v4.16b
+#   v20: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e1462e7		tbl v7.8b, {v23.16b, v24.16b, v25.16b, v26.16b}, v20.8b
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e1f4028		tbl v8.8b, {v1.16b, v2.16b, v3.16b}, v31.8b
+#    v8: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e102328		tbl v8.8b, {v25.16b, v26.16b}, v16.8b
+#    v8: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e1e026b		tbl v11.8b, {v19.16b}, v30.8b
+#   v11: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e057339		tbx v25.16b, {v25.16b, v26.16b, v27.16b, v28.16b}, v5.16b
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e1853b5		tbx v21.16b, {v29.16b, v30.16b, v31.16b}, v24.16b
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e013206		tbx v6.16b, {v16.16b, v17.16b}, v1.16b
+#    v6: 0x01010101010101010101010101010101
+0x~~~~~~~~~~~~~~~~  4e14106d		tbx v13.16b, {v3.16b}, v20.16b
+#   v13: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e0973b8		tbx v24.8b, {v29.16b, v30.16b, v31.16b, v0.16b}, v9.8b
+#   v24: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e1a5131		tbx v17.8b, {v9.16b, v10.16b, v11.16b}, v26.8b
+#   v17: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e153065		tbx v5.8b, {v3.16b, v4.16b}, v21.8b
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e1d1170		tbx v16.8b, {v11.16b}, v29.8b
+#   v16: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e0c2b13		trn1 v19.16b, v24.16b, v12.16b
+#   v19: 0x0000000000000000df00ff00e000c000
+0x~~~~~~~~~~~~~~~~  4eca28e2		trn1 v2.2d, v7.2d, v10.2d
+#    v2: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e952816		trn1 v22.2s, v0.2s, v21.2s
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e5429ec		trn1 v12.4h, v15.4h, v20.4h
+#   v12: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e892a3e		trn1 v30.4s, v17.4s, v9.4s
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e1d2a6c		trn1 v12.8b, v19.8b, v29.8b
+#   v12: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e492917		trn1 v23.8h, v8.8h, v9.8h
+#   v23: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e196bdc		trn2 v28.16b, v30.16b, v25.16b
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ec76b67		trn2 v7.2d, v27.2d, v7.2d
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e936a1e		trn2 v30.2s, v16.2s, v19.2s
+#   v30: 0x0000000000000000df00ff0000000000
+0x~~~~~~~~~~~~~~~~  0e5968d8		trn2 v24.4h, v6.4h, v25.4h
+#   v24: 0x00000000000000000000010100000101
+0x~~~~~~~~~~~~~~~~  4e8b6a62		trn2 v2.4s, v19.4s, v11.4s
+#    v2: 0x000000000000000000000000df00ff00
+0x~~~~~~~~~~~~~~~~  0e126b79		trn2 v25.8b, v27.8b, v18.8b
+#   v25: 0x000000000000000000ff00ff00ff00fc
+0x~~~~~~~~~~~~~~~~  4e4f688c		trn2 v12.8h, v4.8h, v15.8h
+#   v12: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e3c7d9f		uaba v31.16b, v12.16b, v28.16b
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2eae7cb2		uaba v18.2s, v5.2s, v14.2s
+#   v18: 0x00000000000000000000000000000001
+0x~~~~~~~~~~~~~~~~  2e757e89		uaba v9.4h, v20.4h, v21.4h
+#    v9: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ea27e86		uaba v6.4s, v20.4s, v2.4s
+#    v6: 0x010101010101010101010101e0020001
+0x~~~~~~~~~~~~~~~~  2e257d90		uaba v16.8b, v12.8b, v5.8b
+#   v16: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e7e7f4f		uaba v15.8h, v26.8h, v30.8h
+#   v15: 0x0000000000000000df00ff0000000001
+0x~~~~~~~~~~~~~~~~  2eaf524a		uabal v10.2d, v18.2s, v15.2s
+#   v10: 0x00000000df00ff000000000000000000
+0x~~~~~~~~~~~~~~~~  2e67527e		uabal v30.4s, v19.4h, v7.4h
+#   v30: 0x0000df000000ff00df01df000000c000
+0x~~~~~~~~~~~~~~~~  2e205364		uabal v4.8h, v27.8b, v0.8b
+#    v4: 0x00ff00ff00ff00ff00ff00ff00fc0000
+0x~~~~~~~~~~~~~~~~  6ea25193		uabal2 v19.2d, v12.4s, v2.4s
+#   v19: 0x0000000000000000df00ff00e000c000
+0x~~~~~~~~~~~~~~~~  6e6c50ba		uabal2 v26.4s, v5.8h, v12.8h
+#   v26: 0x00000000000000000000000000000001
+0x~~~~~~~~~~~~~~~~  6e3c5293		uabal2 v19.8h, v20.16b, v28.16b
+#   v19: 0x0000000000000000df00ff00e000c000
+0x~~~~~~~~~~~~~~~~  6e357492		uabd v18.16b, v4.16b, v21.16b
+#   v18: 0x00ff00ff00ff00ff00ff00ff00fc0000
+0x~~~~~~~~~~~~~~~~  2eb076be		uabd v30.2s, v21.2s, v16.2s
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e797788		uabd v8.4h, v28.4h, v25.4h
+#    v8: 0x000000000000000000ff00ff00ff00fc
+0x~~~~~~~~~~~~~~~~  6eb5759c		uabd v28.4s, v12.4s, v21.4s
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e3c7613		uabd v19.8b, v16.8b, v28.8b
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e7d7589		uabd v9.8h, v12.8h, v29.8h
+#    v9: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2ea8701a		uabdl v26.2d, v0.2s, v8.2s
+#   v26: 0x0000000000ff00ff0000000000ff00fc
+0x~~~~~~~~~~~~~~~~  2e7973fd		uabdl v29.4s, v31.4h, v25.4h
+#   v29: 0x000000ff000000ff000000ff000000fc
+0x~~~~~~~~~~~~~~~~  2e2e73bb		uabdl v27.8h, v29.8b, v14.8b
+#   v27: 0x00000000000000ff00000000000000fb
+0x~~~~~~~~~~~~~~~~  6ea87294		uabdl2 v20.2d, v20.4s, v8.4s
+#   v20: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e7271f6		uabdl2 v22.4s, v15.8h, v18.8h
+#   v22: 0x000000ff000000ff000000ff000000ff
+0x~~~~~~~~~~~~~~~~  6e377249		uabdl2 v9.8h, v18.16b, v23.16b
+#    v9: 0x000000ff000000ff000000ff000000ff
+0x~~~~~~~~~~~~~~~~  2ea069e9		uadalp v9.1d, v15.2s
+#    v9: 0x0000000000000000000000ffdf010000
+0x~~~~~~~~~~~~~~~~  6ea0698e		uadalp v14.2d, v12.4s
+#   v14: 0x00000000000000000000000000000001
+0x~~~~~~~~~~~~~~~~  2e60699c		uadalp v28.2s, v12.4h
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e206a20		uadalp v0.4h, v17.8b
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e606ba1		uadalp v1.4s, v29.8h
+#    v1: 0x000000ff000000ff000000ff000000fc
+0x~~~~~~~~~~~~~~~~  6e206acf		uadalp v15.8h, v22.16b
+#   v15: 0x000000ff000000ffdf00ffff00000100
+0x~~~~~~~~~~~~~~~~  2ebb0281		uaddl v1.2d, v20.2s, v27.2s
+#    v1: 0x000000000000000000000000000000fb
+0x~~~~~~~~~~~~~~~~  2e65033f		uaddl v31.4s, v25.4h, v5.4h
+#   v31: 0x000000ff000000ff000000ff000000fc
+0x~~~~~~~~~~~~~~~~  2e23006c		uaddl v12.8h, v3.8b, v3.8b
+#   v12: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ea602e5		uaddl2 v5.2d, v23.4s, v6.4s
+#    v5: 0x00000000010101010000000001010101
+0x~~~~~~~~~~~~~~~~  6e7900a1		uaddl2 v1.4s, v5.8h, v25.8h
+#    v1: 0x00000000000000000000010100000101
+0x~~~~~~~~~~~~~~~~  6e3c03d6		uaddl2 v22.8h, v30.16b, v28.16b
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2ea02927		uaddlp v7.1d, v9.2s
+#    v7: 0x000000000000000000000000df0100ff
+0x~~~~~~~~~~~~~~~~  6ea0289a		uaddlp v26.2d, v4.4s
+#   v26: 0x0000000001fe01fe0000000001fb00ff
+0x~~~~~~~~~~~~~~~~  2e60283c		uaddlp v28.2s, v1.4h
+#   v28: 0x00000000000000000000010100000101
+0x~~~~~~~~~~~~~~~~  2e202bf4		uaddlp v20.4h, v31.8b
+#   v20: 0x0000000000000000000000ff000000fc
+0x~~~~~~~~~~~~~~~~  6e602a30		uaddlp v16.4s, v17.8h
+#   v16: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e202846		uaddlp v6.8h, v2.16b
+#    v6: 0x00000000000000000000000000df00ff
+0x~~~~~~~~~~~~~~~~  6eb03adc		uaddlv d28, v22.4s
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e303a60		uaddlv h0, v19.16b
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e303bde		uaddlv h30, v30.8b
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e703a58		uaddlv s24, v18.4h
+#   v24: 0x000000000000000000000000000002fa
+0x~~~~~~~~~~~~~~~~  6e70380a		uaddlv s10, v0.8h
+#   v10: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2eae1229		uaddw v9.2d, v17.2d, v14.2s
+#    v9: 0x00000000000000000000000000000001
+0x~~~~~~~~~~~~~~~~  2e631329		uaddw v9.4s, v25.4s, v3.4h
+#    v9: 0x000000000000000000ff00ff00ff00fc
+0x~~~~~~~~~~~~~~~~  2e201032		uaddw v18.8h, v1.8h, v0.8b
+#   v18: 0x00000000000000000000010100000101
+0x~~~~~~~~~~~~~~~~  6ea610b2		uaddw2 v18.2d, v5.2d, v6.4s
+#   v18: 0x00000000010101010000000001010101
+0x~~~~~~~~~~~~~~~~  6e6b11f1		uaddw2 v17.4s, v15.4s, v11.8h
+#   v17: 0x000000ff000000ffdf00ffff00000100
+0x~~~~~~~~~~~~~~~~  6e27117d		uaddw2 v29.8h, v11.8h, v7.16b
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e23052d		uhadd v13.16b, v9.16b, v3.16b
+#   v13: 0x0000000000000000007f007f007f007e
+0x~~~~~~~~~~~~~~~~  2eb80731		uhadd v17.2s, v25.2s, v24.2s
+#   v17: 0x0000000000000000007f807f007f81fb
+0x~~~~~~~~~~~~~~~~  2e6d06f9		uhadd v25.4h, v23.4h, v13.4h
+#   v25: 0x0000000000000000003f003f003f003f
+0x~~~~~~~~~~~~~~~~  6eb00680		uhadd v0.4s, v20.4s, v16.4s
+#    v0: 0x00000000000000000000007f0000007e
+0x~~~~~~~~~~~~~~~~  2e3904a5		uhadd v5.8b, v5.8b, v25.8b
+#    v5: 0x0000000000000000001f001f00200020
+0x~~~~~~~~~~~~~~~~  6e7207a3		uhadd v3.8h, v29.8h, v18.8h
+#    v3: 0x00000000008000800000000000800080
+0x~~~~~~~~~~~~~~~~  6e2d26c1		uhsub v1.16b, v22.16b, v13.16b
+#    v1: 0x000000000000000000c000c000c000c1
+0x~~~~~~~~~~~~~~~~  2ebe27ce		uhsub v14.2s, v30.2s, v30.2s
+#   v14: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e7125dd		uhsub v29.4h, v14.4h, v17.4h
+#   v29: 0x0000000000000000ffc0bfc0ffc0bf02
+0x~~~~~~~~~~~~~~~~  6eb224ba		uhsub v26.4s, v5.4s, v18.4s
+#   v26: 0x00000000ff7f7f7f000f800fff8f7f8f
+0x~~~~~~~~~~~~~~~~  2e2c24e3		uhsub v3.8b, v7.8b, v12.8b
+#    v3: 0x0000000000000000000000006f00007f
+0x~~~~~~~~~~~~~~~~  6e6526b9		uhsub v25.8h, v21.8h, v5.8h
+#   v25: 0x0000000000000000fff0fff0fff0fff0
+0x~~~~~~~~~~~~~~~~  6e26659c		umax v28.16b, v12.16b, v6.16b
+#   v28: 0x00000000000000000000000000df00ff
+0x~~~~~~~~~~~~~~~~  2eba6674		umax v20.2s, v19.2s, v26.2s
+#   v20: 0x0000000000000000000f800fff8f7f8f
+0x~~~~~~~~~~~~~~~~  2e7267e0		umax v0.4h, v31.4h, v18.4h
+#    v0: 0x0000000000000000000000ff01010101
+0x~~~~~~~~~~~~~~~~  6ebc66a6		umax v6.4s, v21.4s, v28.4s
+#    v6: 0x00000000000000000000000000df00ff
+0x~~~~~~~~~~~~~~~~  2e346440		umax v0.8b, v2.8b, v20.8b
+#    v0: 0x0000000000000000000f800fff8fff8f
+0x~~~~~~~~~~~~~~~~  6e766564		umax v4.8h, v11.8h, v22.8h
+#    v4: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e3da4c1		umaxp v1.16b, v6.16b, v29.16b
+#    v1: 0x00000000ffc0ffbf000000000000dfff
+0x~~~~~~~~~~~~~~~~  2ebba633		umaxp v19.2s, v17.2s, v27.2s
+#   v19: 0x0000000000000000000000fb007f81fb
+0x~~~~~~~~~~~~~~~~  2e67a615		umaxp v21.4h, v16.4h, v7.4h
+#   v21: 0x00000000000000000000df0100000000
+0x~~~~~~~~~~~~~~~~  6ebda689		umaxp v9.4s, v20.4s, v29.4s
+#    v9: 0x00000000ffc0bfc000000000ff8f7f8f
+0x~~~~~~~~~~~~~~~~  2e30a42d		umaxp v13.8b, v1.8b, v16.8b
+#   v13: 0x000000000000000000000000000000ff
+0x~~~~~~~~~~~~~~~~  6e7aa6f3		umaxp v19.8h, v23.8h, v26.8h
+#   v19: 0x0000ff7f800fff8f0000000000000000
+0x~~~~~~~~~~~~~~~~  6e30abd1		umaxv b17, v30.16b
+#   v17: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e30a997		umaxv b23, v12.8b
+#   v23: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e70a9ff		umaxv h31, v15.4h
+#   v31: 0x0000000000000000000000000000ffff
+0x~~~~~~~~~~~~~~~~  6e70ab2f		umaxv h15, v25.8h
+#   v15: 0x0000000000000000000000000000fff0
+0x~~~~~~~~~~~~~~~~  6eb0aab2		umaxv s18, v21.4s
+#   v18: 0x0000000000000000000000000000df01
+0x~~~~~~~~~~~~~~~~  6e326c16		umin v22.16b, v0.16b, v18.16b
+#   v22: 0x0000000000000000000000000000df01
+0x~~~~~~~~~~~~~~~~  2eb06ea1		umin v1.2s, v21.2s, v16.2s
+#    v1: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e796c91		umin v17.4h, v4.4h, v25.4h
+#   v17: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ead6f58		umin v24.4s, v26.4s, v13.4s
+#   v24: 0x000000000000000000000000000000ff
+0x~~~~~~~~~~~~~~~~  2e256c34		umin v20.8b, v1.8b, v5.8b
+#   v20: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e776f3a		umin v26.8h, v25.8h, v23.8h
+#   v26: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e37ac25		uminp v5.16b, v1.16b, v23.16b
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2ebeaf47		uminp v7.2s, v26.2s, v30.2s
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e79aca9		uminp v9.4h, v5.4h, v25.4h
+#    v9: 0x0000000000000000fff0fff000000000
+0x~~~~~~~~~~~~~~~~  6ea1ad57		uminp v23.4s, v10.4s, v1.4s
+#   v23: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e2eafa4		uminp v4.8b, v29.8b, v14.8b
+#    v4: 0x000000000000000000000000c0bfc002
+0x~~~~~~~~~~~~~~~~  6e6eac15		uminp v21.8h, v0.8h, v14.8h
+#   v21: 0x000000000000000000000000000fff8f
+0x~~~~~~~~~~~~~~~~  6e31aa20		uminv b0, v17.16b
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e31abe0		uminv b0, v31.8b
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e71a818		uminv h24, v0.4h
+#   v24: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e71a9dd		uminv h29, v14.8h
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6eb1a87e		uminv s30, v3.4s
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2eb8816b		umlal v11.2d, v11.2s, v24.2s
+#   v11: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2fab2a1e		umlal v30.2d, v16.2s, v11.s[3]
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e7a8120		umlal v0.4s, v9.4h, v26.4h
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f4c2b14		umlal v20.4s, v24.4h, v12.h[4]
+#   v20: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e2682b0		umlal v16.8h, v21.8b, v6.8b
+#   v16: 0x000000000000000000000d1100008e71
+0x~~~~~~~~~~~~~~~~  6eb78271		umlal2 v17.2d, v19.4s, v23.4s
+#   v17: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f8823c5		umlal2 v5.2d, v30.4s, v8.s[0]
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e6f8110		umlal2 v16.4s, v8.8h, v15.8h
+#   v16: 0x000000000000000000000d1100008e71
+0x~~~~~~~~~~~~~~~~  6f512b4f		umlal2 v15.4s, v26.8h, v1.h[5]
+#   v15: 0x0000000000000000000000000000fff0
+0x~~~~~~~~~~~~~~~~  6e31803e		umlal2 v30.8h, v1.16b, v17.16b
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2ebca272		umlsl v18.2d, v19.2s, v28.2s
+#   v18: 0x0000000000000000000000000000df01
+0x~~~~~~~~~~~~~~~~  2f8860e7		umlsl v7.2d, v7.2s, v8.s[0]
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e64a118		umlsl v24.4s, v8.4h, v4.4h
+#   v24: 0x0000000000000000ff4001bfff42fe08
+0x~~~~~~~~~~~~~~~~  2f4c6ad2		umlsl v18.4s, v22.4h, v12.h[4]
+#   v18: 0x0000000000000000000000000000df01
+0x~~~~~~~~~~~~~~~~  2e34a1dc		umlsl v28.8h, v14.8b, v20.8b
+#   v28: 0x00000000000000000000000000df00ff
+0x~~~~~~~~~~~~~~~~  6ea9a00b		umlsl2 v11.2d, v0.4s, v9.4s
+#   v11: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f896a1a		umlsl2 v26.2d, v16.4s, v9.s[2]
+#   v26: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e69a163		umlsl2 v3.4s, v11.8h, v9.8h
+#    v3: 0x0000000000000000000000006f00007f
+0x~~~~~~~~~~~~~~~~  6f496b2a		umlsl2 v10.4s, v25.8h, v9.h[4]
+#   v10: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e3ca218		umlsl2 v24.8h, v16.16b, v28.16b
+#   v24: 0x0000000000000000ff4001bfff42fe08
+0x~~~~~~~~~~~~~~~~  4e183f3e		mov x30, v25.d[1]
+#    lr: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  2ebdc14c		umull v12.2d, v10.2s, v29.2s
+#   v12: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2fa5abd6		umull v22.2d, v30.2s, v5.s[3]
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e79c007		umull v7.4s, v0.4h, v25.4h
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f63a1ab		umull v11.4s, v13.4h, v3.h[2]
+#   v11: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e2ac219		umull v25.8h, v16.8b, v10.8b
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ebac071		umull2 v17.2d, v3.4s, v26.4s
+#   v17: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6fa2a97a		umull2 v26.2d, v11.4s, v2.s[3]
+#   v26: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e77c22c		umull2 v12.4s, v17.8h, v23.8h
+#   v12: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f61a3e4		umull2 v4.4s, v31.8h, v1.h[2]
+#    v4: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e31c185		umull2 v5.8h, v12.16b, v17.16b
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7e3c0c9e		uqadd b30, b4, b28
+#   v30: 0x000000000000000000000000000000ff
+0x~~~~~~~~~~~~~~~~  7ef00e9b		uqadd d27, d20, d16
+#   v27: 0x000000000000000000000d1100008e71
+0x~~~~~~~~~~~~~~~~  7e7c0dc7		uqadd h7, h14, h28
+#    v7: 0x000000000000000000000000000000ff
+0x~~~~~~~~~~~~~~~~  7ea40e3c		uqadd s28, s17, s4
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e350ed3		uqadd v19.16b, v22.16b, v21.16b
+#   v19: 0x000000000000000000000000000fff8f
+0x~~~~~~~~~~~~~~~~  6eeb0c90		uqadd v16.2d, v4.2d, v11.2d
+#   v16: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2ea40dd4		uqadd v20.2s, v14.2s, v4.2s
+#   v20: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e700c05		uqadd v5.4h, v0.4h, v16.4h
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ea90ff5		uqadd v21.4s, v31.4s, v9.4s
+#   v21: 0x0000000000000000fff0fff00000ffff
+0x~~~~~~~~~~~~~~~~  2e230f17		uqadd v23.8b, v24.8b, v3.8b
+#   v23: 0x0000000000000000ff4001bfff42fe87
+0x~~~~~~~~~~~~~~~~  6e6b0f71		uqadd v17.8h, v27.8h, v11.8h
+#   v17: 0x000000000000000000000d1100008e71
+0x~~~~~~~~~~~~~~~~  7e2a5eca		uqrshl b10, b22, b10
+#   v10: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7eeb5cbd		uqrshl d29, d5, d11
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7e7e5f1b		uqrshl h27, h24, h30
+#   v27: 0x00000000000000000000000000007f04
+0x~~~~~~~~~~~~~~~~  7ea85daa		uqrshl s10, s13, s8
+#   v10: 0x00000000000000000000000000000010
+0x~~~~~~~~~~~~~~~~  6e2e5e49		uqrshl v9.16b, v18.16b, v14.16b
+#    v9: 0x0000000000000000000000000000df01
+0x~~~~~~~~~~~~~~~~  6ef15df8		uqrshl v24.2d, v15.2d, v17.2d
+#   v24: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  2ebb5dc4		uqrshl v4.2s, v14.2s, v27.2s
+#    v4: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e685caf		uqrshl v15.4h, v5.4h, v8.4h
+#   v15: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ea05fb5		uqrshl v21.4s, v29.4s, v0.4s
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e295f10		uqrshl v16.8b, v24.8b, v9.8b
+#   v16: 0x0000000000000000ffffffffffff00ff
+0x~~~~~~~~~~~~~~~~  6e6f5c02		uqrshl v2.8h, v0.8h, v15.8h
+#    v2: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7f0c9f4b		uqrshrn b11, h26, #4
+#   v11: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7f1b9fc7		uqrshrn h7, s30, #5
+#    v7: 0x00000000000000000000000000000008
+0x~~~~~~~~~~~~~~~~  7f2b9d0a		uqrshrn s10, d8, #21
+#   v10: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  2f359ccf		uqrshrn v15.2s, v6.2d, #11
+#   v15: 0x00000000000000000000000000001be0
+0x~~~~~~~~~~~~~~~~  2f149f45		uqrshrn v5.4h, v26.4s, #12
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f0b9f3c		uqrshrn v28.8b, v25.8h, #5
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f0e9fd9		uqrshrn2 v25.16b, v30.8h, #2
+#   v25: 0x00000000000000400000000000000000
+0x~~~~~~~~~~~~~~~~  6f209dd5		uqrshrn2 v21.4s, v14.2d, #32
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f1e9ced		uqrshrn2 v13.8h, v7.4s, #2
+#   v13: 0x000000000000000200000000000000ff
+0x~~~~~~~~~~~~~~~~  7e374c0d		uqshl b13, b0, b23
+#   v13: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7f0c7629		uqshl b9, b17, #4
+#    v9: 0x000000000000000000000000000000ff
+0x~~~~~~~~~~~~~~~~  7ee44cd7		uqshl d23, d6, d4
+#   v23: 0x00000000000000000000000000df00ff
+0x~~~~~~~~~~~~~~~~  7f6c7568		uqshl d8, d11, #44
+#    v8: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7e6f4db3		uqshl h19, h13, h15
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7f167759		uqshl h25, h26, #6
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7eaa4f04		uqshl s4, s24, s10
+#    v4: 0x0000000000000000000000007fffffff
+0x~~~~~~~~~~~~~~~~  7f2175d3		uqshl s19, s14, #1
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e394fce		uqshl v14.16b, v30.16b, v25.16b
+#   v14: 0x000000000000000000000000000000ff
+0x~~~~~~~~~~~~~~~~  6f0d7546		uqshl v6.16b, v10.16b, #5
+#    v6: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  6ee74d12		uqshl v18.2d, v8.2d, v7.2d
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f5275d9		uqshl v25.2d, v14.2d, #18
+#   v25: 0x00000000000000000000000003fc0000
+0x~~~~~~~~~~~~~~~~  2eb74e19		uqshl v25.2s, v16.2s, v23.2s
+#   v25: 0x0000000000000000ffffffff7fff807f
+0x~~~~~~~~~~~~~~~~  2f3f75ed		uqshl v13.2s, v15.2s, #31
+#   v13: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  2e6f4f1c		uqshl v28.4h, v24.4h, v15.4h
+#   v28: 0x0000000000000000ffffffffffff0000
+0x~~~~~~~~~~~~~~~~  2f117624		uqshl v4.4h, v17.4h, #1
+#    v4: 0x000000000000000000001a220000ffff
+0x~~~~~~~~~~~~~~~~  6eb74fe9		uqshl v9.4s, v31.4s, v23.4s
+#    v9: 0x00000000000000000000000000007fff
+0x~~~~~~~~~~~~~~~~  6f3f7792		uqshl v18.4s, v28.4s, #31
+#   v18: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  2e2f4ebf		uqshl v31.8b, v21.8b, v15.8b
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f0976a6		uqshl v6.8b, v21.8b, #1
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e714c5c		uqshl v28.8h, v2.8h, v17.8h
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f1e7518		uqshl v24.8h, v8.8h, #14
+#   v24: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7f099775		uqshrn b21, h27, #7
+#   v21: 0x000000000000000000000000000000fe
+0x~~~~~~~~~~~~~~~~  7f15975c		uqshrn h28, s26, #11
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7f2f97ed		uqshrn s13, d31, #17
+#   v13: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f389615		uqshrn v21.2s, v16.2d, #8
+#   v21: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  2f1e9718		uqshrn v24.4h, v24.4s, #2
+#   v24: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f089425		uqshrn v5.8b, v1.8h, #8
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f0a97b0		uqshrn2 v16.16b, v29.8h, #6
+#   v16: 0x0000000000000000ffffffffffff00ff
+0x~~~~~~~~~~~~~~~~  6f3f94c2		uqshrn2 v2.4s, v6.2d, #1
+#    v2: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f129550		uqshrn2 v16.8h, v10.4s, #14
+#   v16: 0x000000000000ffffffffffffffff00ff
+0x~~~~~~~~~~~~~~~~  7e3a2e9c		uqsub b28, b20, b26
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7eea2ce0		uqsub d0, d7, d10
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7e672f1a		uqsub h26, h24, h7
+#   v26: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7eb02ef7		uqsub s23, s23, s16
+#   v23: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e382e0e		uqsub v14.16b, v16.16b, v24.16b
+#   v14: 0x000000000000ffffffffffffffff00ff
+0x~~~~~~~~~~~~~~~~  6ee62e2b		uqsub v11.2d, v17.2d, v6.2d
+#   v11: 0x000000000000000000000d1100008e71
+0x~~~~~~~~~~~~~~~~  2ea82d4a		uqsub v10.2s, v10.2s, v8.2s
+#   v10: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  2e6c2de9		uqsub v9.4h, v15.4h, v12.4h
+#    v9: 0x00000000000000000000000000001be0
+0x~~~~~~~~~~~~~~~~  6ea72e57		uqsub v23.4s, v18.4s, v7.4s
+#   v23: 0x0000000000000000fffffffffffffff7
+0x~~~~~~~~~~~~~~~~  2e312e69		uqsub v9.8b, v19.8b, v17.8b
+#    v9: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e662c54		uqsub v20.8h, v2.8h, v6.8h
+#   v20: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7e214a7d		uqxtn b29, h19
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7e6149a0		uqxtn h0, s13
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7ea14ada		uqxtn s26, d22
+#   v26: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2ea14be5		uqxtn v5.2s, v31.2d
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e614a7e		uqxtn v30.4h, v19.4s
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e21484f		uqxtn v15.8b, v2.8h
+#   v15: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e21487d		uqxtn2 v29.16b, v3.8h
+#   v29: 0x000000000000ff7f0000000000000000
+0x~~~~~~~~~~~~~~~~  6ea14a2d		uqxtn2 v13.4s, v17.2d
+#   v13: 0x00000000ffffffff0000000000000000
+0x~~~~~~~~~~~~~~~~  6e61497c		uqxtn2 v28.8h, v11.4s
+#   v28: 0x000000000d118e710000000000000000
+0x~~~~~~~~~~~~~~~~  0ea1c9f7		urecpe v23.2s, v15.2s
+#   v23: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4ea1c8fb		urecpe v27.4s, v7.4s
+#   v27: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  6e3b15e2		urhadd v2.16b, v15.16b, v27.16b
+#    v2: 0x80808080808080808080808080808080
+0x~~~~~~~~~~~~~~~~  2eb2142f		urhadd v15.2s, v1.2s, v18.2s
+#   v15: 0x00000000000000008000000080000000
+0x~~~~~~~~~~~~~~~~  2e7a1491		urhadd v17.4h, v4.4h, v26.4h
+#   v17: 0x000000000000000000000d1100008000
+0x~~~~~~~~~~~~~~~~  6eae1762		urhadd v2.4s, v27.4s, v14.4s
+#    v2: 0x8000000080007fffffffffffffff807f
+0x~~~~~~~~~~~~~~~~  2e2e1625		urhadd v5.8b, v17.8b, v14.8b
+#    v5: 0x00000000000000008080868880804080
+0x~~~~~~~~~~~~~~~~  6e79145e		urhadd v30.8h, v2.8h, v25.8h
+#   v30: 0x4000000040004000ffffffffbfff807f
+0x~~~~~~~~~~~~~~~~  7efe5784		urshl d4, d28, d30
+#    v4: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e3357ed		urshl v13.16b, v31.16b, v19.16b
+#   v13: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ef556ee		urshl v14.2d, v23.2d, v21.2d
+#   v14: 0x00000000000000008000000000000000
+0x~~~~~~~~~~~~~~~~  2ea854ea		urshl v10.2s, v7.2s, v8.2s
+#   v10: 0x00000000000000000000000000000008
+0x~~~~~~~~~~~~~~~~  2e7c56af		urshl v15.4h, v21.4h, v28.4h
+#   v15: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  6eb7551e		urshl v30.4s, v8.4s, v23.4s
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e25569f		urshl v31.8b, v20.8b, v5.8b
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e7e577e		urshl v30.8h, v27.8h, v30.8h
+#   v30: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  7f4f25a4		urshr d4, d13, #49
+#    v4: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f0f2682		urshr v2.16b, v20.16b, #1
+#    v2: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f4d256d		urshr v13.2d, v11.2d, #51
+#   v13: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f3627f5		urshr v21.2s, v31.2s, #10
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f152635		urshr v21.4h, v17.4h, #11
+#   v21: 0x00000000000000000000000200000010
+0x~~~~~~~~~~~~~~~~  6f3f26c4		urshr v4.4s, v22.4s, #1
+#    v4: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f092420		urshr v0.8b, v1.8b, #7
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f1f268d		urshr v13.8h, v20.8h, #1
+#   v13: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2ea1ca14		ursqrte v20.2s, v16.2s
+#   v20: 0x00000000000000008000000080000000
+0x~~~~~~~~~~~~~~~~  6ea1c91c		ursqrte v28.4s, v8.4s
+#   v28: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  7f53361b		ursra d27, d16, #45
+#   v27: 0x0000000000000000000000000007ffff
+0x~~~~~~~~~~~~~~~~  6f0d3632		ursra v18.16b, v17.16b, #3
+#   v18: 0x0000000000000000ffff0101ffff0fff
+0x~~~~~~~~~~~~~~~~  6f46379a		ursra v26.2d, v28.2d, #58
+#   v26: 0x00000000000000400000000000000040
+0x~~~~~~~~~~~~~~~~  2f2136c8		ursra v8.2s, v22.2s, #31
+#    v8: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f19349f		ursra v31.4h, v4.4h, #7
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f3e35ff		ursra v31.4s, v15.4s, #2
+#   v31: 0x00000000000000000000000040000000
+0x~~~~~~~~~~~~~~~~  2f0b3423		ursra v3.8b, v1.8b, #5
+#    v3: 0x0000000000000000000000006f00007f
+0x~~~~~~~~~~~~~~~~  6f1335d2		ursra v18.8h, v14.8h, #13
+#   v18: 0x000000000000000000030101ffff0fff
+0x~~~~~~~~~~~~~~~~  7ef0441f		ushl d31, d0, d16
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e2244c0		ushl v0.16b, v6.16b, v2.16b
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ef24432		ushl v18.2d, v1.2d, v18.2d
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2ebd44fb		ushl v27.2s, v7.2s, v29.2s
+#   v27: 0x00000000000000000000000000000008
+0x~~~~~~~~~~~~~~~~  2e6d45ce		ushl v14.4h, v14.4h, v13.4h
+#   v14: 0x00000000000000008000000000000000
+0x~~~~~~~~~~~~~~~~  6ea94496		ushl v22.4s, v4.4s, v9.4s
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e3b46d7		ushl v23.8b, v22.8b, v27.8b
+#   v23: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e684735		ushl v21.8h, v25.8h, v8.8h
+#   v21: 0x0000000000000000ffffffff7fff807f
+0x~~~~~~~~~~~~~~~~  2f35a40b		ushll v11.2d, v0.2s, #21
+#   v11: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f18a622		ushll v2.4s, v17.4h, #8
+#    v2: 0x00000000000d11000000000000800000
+0x~~~~~~~~~~~~~~~~  2f09a5cb		ushll v11.8h, v14.8b, #1
+#   v11: 0x01000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f27a7a8		ushll2 v8.2d, v29.4s, #7
+#    v8: 0x000000000000000000000000007fbf80
+0x~~~~~~~~~~~~~~~~  6f12a53d		ushll2 v29.4s, v9.8h, #2
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f0ea705		ushll2 v5.8h, v24.16b, #6
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7f4b077c		ushr d28, d27, #53
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f090521		ushr v1.16b, v9.16b, #7
+#    v1: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f550702		ushr v2.2d, v24.2d, #43
+#    v2: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f35073e		ushr v30.2s, v25.2s, #11
+#   v30: 0x0000000000000000001fffff000ffff0
+0x~~~~~~~~~~~~~~~~  2f14074a		ushr v10.4h, v26.4h, #12
+#   v10: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f2204a4		ushr v4.4s, v5.4s, #30
+#    v4: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f0f045e		ushr v30.8b, v2.8b, #1
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f1e0586		ushr v6.8h, v12.8h, #2
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7e2038b3		usqadd b19, b5
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7ee03849		usqadd d9, d2
+#    v9: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7e603a02		usqadd h2, h16
+#    v2: 0x000000000000000000000000000000ff
+0x~~~~~~~~~~~~~~~~  7ea03870		usqadd s16, s3
+#   v16: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  6e203bbf		usqadd v31.16b, v29.16b
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ee03948		usqadd v8.2d, v10.2d
+#    v8: 0x000000000000000000000000007fbf80
+0x~~~~~~~~~~~~~~~~  2ea03932		usqadd v18.2s, v9.2s
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e6039d8		usqadd v24.4h, v14.4h
+#   v24: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ea03bca		usqadd v10.4s, v30.4s
+#   v10: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e203a90		usqadd v16.8b, v20.8b
+#   v16: 0x0000000000000000000000007fffffff
+0x~~~~~~~~~~~~~~~~  6e603a0c		usqadd v12.8h, v16.8h
+#   v12: 0x0000000000000000000000007fff0000
+0x~~~~~~~~~~~~~~~~  7f5b177c		usra d28, d27, #37
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f0b16c5		usra v5.16b, v22.16b, #5
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f5f1662		usra v2.2d, v19.2d, #33
+#    v2: 0x000000000000000000000000000000ff
+0x~~~~~~~~~~~~~~~~  2f2b1400		usra v0.2s, v0.2s, #21
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f1414c7		usra v7.4h, v6.4h, #12
+#    v7: 0x00000000000000000000000000000008
+0x~~~~~~~~~~~~~~~~  6f371624		usra v4.4s, v17.4s, #9
+#    v4: 0x00000000000000000000000600000040
+0x~~~~~~~~~~~~~~~~  2f091589		usra v9.8b, v12.8b, #7
+#    v9: 0x00000000000000000000000000010000
+0x~~~~~~~~~~~~~~~~  6f121763		usra v3.8h, v27.8h, #14
+#    v3: 0x0000000000000000000000006f00007f
+0x~~~~~~~~~~~~~~~~  2ebe219d		usubl v29.2d, v12.2s, v30.2s
+#   v29: 0x0000000000000000000000007fff0000
+0x~~~~~~~~~~~~~~~~  2e66239d		usubl v29.4s, v28.4h, v6.4h
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e2e208c		usubl v12.8h, v4.8b, v14.8b
+#   v12: 0xff800000000000060000000000000040
+0x~~~~~~~~~~~~~~~~  6eb12301		usubl2 v1.2d, v24.4s, v17.4s
+#    v1: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e632024		usubl2 v4.4s, v1.8h, v3.8h
+#    v4: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e272097		usubl2 v23.8h, v4.16b, v7.16b
+#   v23: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2ebe3289		usubw v9.2d, v20.2d, v30.2s
+#    v9: 0x00000000000000008000000080000000
+0x~~~~~~~~~~~~~~~~  2e773214		usubw v20.4s, v16.4s, v23.4h
+#   v20: 0x0000000000000000000000007fffffff
+0x~~~~~~~~~~~~~~~~  2e3d3119		usubw v25.8h, v8.8h, v29.8b
+#   v25: 0x000000000000000000000000007fbf80
+0x~~~~~~~~~~~~~~~~  6ea633b2		usubw2 v18.2d, v29.2d, v6.4s
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e7430c6		usubw2 v6.4s, v6.4s, v20.8h
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e303092		usubw2 v18.8h, v4.8h, v16.16b
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f20a6bb		uxtl v27.2d, v21.2s
+#   v27: 0x00000000ffffffff000000007fff807f
+0x~~~~~~~~~~~~~~~~  2f10a7e0		uxtl v0.4s, v31.4h
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f08a55b		uxtl v27.8h, v10.8b
+#   v27: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f20a606		uxtl2 v6.2d, v16.4s
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f10a696		uxtl2 v22.4s, v20.8h
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f08a6b4		uxtl2 v20.8h, v21.16b
+#   v20: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e11193e		uzp1 v30.16b, v9.16b, v17.16b
+#   v30: 0x00000000001100000000000000000000
+0x~~~~~~~~~~~~~~~~  4edc1b47		uzp1 v7.2d, v26.2d, v28.2d
+#    v7: 0x00000000000000000000000000000040
+0x~~~~~~~~~~~~~~~~  0e961a1a		uzp1 v26.2s, v16.2s, v22.2s
+#   v26: 0x0000000000000000000000007fffffff
+0x~~~~~~~~~~~~~~~~  0e461a6e		uzp1 v14.4h, v19.4h, v6.4h
+#   v14: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e9e1af1		uzp1 v17.4s, v23.4s, v30.4s
+#   v17: 0x00110000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e0d1b7c		uzp1 v28.8b, v27.8b, v13.8b
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e4c1831		uzp1 v17.8h, v1.8h, v12.8h
+#   v17: 0x00000006000000400000000000000000
+0x~~~~~~~~~~~~~~~~  4e1a5a48		uzp2 v8.16b, v18.16b, v26.16b
+#    v8: 0x0000000000007fff0000000000000000
+0x~~~~~~~~~~~~~~~~  4ed85ad5		uzp2 v21.2d, v22.2d, v24.2d
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e825ab4		uzp2 v20.2s, v21.2s, v2.2s
+#   v20: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e465bf0		uzp2 v16.4h, v31.4h, v6.4h
+#   v16: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e885979		uzp2 v25.4s, v11.4s, v8.4s
+#   v25: 0x00000000000000000100000000000000
+0x~~~~~~~~~~~~~~~~  0e0d5bff		uzp2 v31.8b, v31.8b, v13.8b
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e415a28		uzp2 v8.8h, v17.8h, v1.8h
+#    v8: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ea12b51		xtn v17.2s, v26.2d
+#   v17: 0x0000000000000000000000007fffffff
+0x~~~~~~~~~~~~~~~~  0e612803		xtn v3.4h, v0.4s
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e212912		xtn v18.8b, v8.8h
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e212800		xtn2 v0.16b, v0.8h
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ea1288f		xtn2 v15.4s, v4.2d
+#   v15: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  4e612a5f		xtn2 v31.8h, v18.4s
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e063936		zip1 v22.16b, v9.16b, v6.16b
+#   v22: 0x00800000000000000080000000000000
+0x~~~~~~~~~~~~~~~~  4ec23977		zip1 v23.2d, v11.2d, v2.2d
+#   v23: 0x00000000000000ff0000000000000000
+0x~~~~~~~~~~~~~~~~  0e893a1a		zip1 v26.2s, v16.2s, v9.2s
+#   v26: 0x00000000000000008000000000000000
+0x~~~~~~~~~~~~~~~~  0e473921		zip1 v1.4h, v9.4h, v7.4h
+#    v1: 0x00000000000000000000800000400000
+0x~~~~~~~~~~~~~~~~  4e943bc0		zip1 v0.4s, v30.4s, v20.4s
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e0f3a3e		zip1 v30.8b, v17.8b, v15.8b
+#   v30: 0x0000000000000000ff7fffffffffffff
+0x~~~~~~~~~~~~~~~~  4e423911		zip1 v17.8h, v8.8h, v2.8h
+#   v17: 0x00000000000000000000000000ff0000
+0x~~~~~~~~~~~~~~~~  4e0b7957		zip2 v23.16b, v10.16b, v11.16b
+#   v23: 0x01000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ece78de		zip2 v30.2d, v6.2d, v14.2d
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e957949		zip2 v9.2s, v10.2s, v21.2s
+#    v9: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e5d7b08		zip2 v8.4h, v24.4h, v29.4h
+#    v8: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e977aa0		zip2 v0.4s, v21.4s, v23.4s
+#    v0: 0x01000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e1e7af9		zip2 v25.8b, v23.8b, v30.8b
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e5e7947		zip2 v7.8h, v10.8h, v30.8h
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ee8d723		fabd v3.2d, v25.2d, v8.2d
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2eabd76e		fabd v14.2s, v27.2s, v11.2s
+#   v14: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6eb2d6c9		fabd v9.4s, v22.4s, v18.4s
+#    v9: 0x00800000000000000080000000000000
+0x~~~~~~~~~~~~~~~~  4ee0fba1		fabs v1.2d, v29.2d
+#    v1: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ea0faa6		fabs v6.2s, v21.2s
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ea0fb2c		fabs v12.4s, v25.4s
+#   v12: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e60ecb2		facge v18.2d, v5.2d, v0.2d
+#   v18: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  2e26ed6f		facge v15.2s, v11.2s, v6.2s
+#   v15: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  6e39ed5e		facge v30.4s, v10.4s, v25.4s
+#   v30: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  6effee1c		facgt v28.2d, v16.2d, v31.2d
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2ea4ec2f		facgt v15.2s, v1.2s, v4.2s
+#   v15: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6eaaec76		facgt v22.4s, v3.4s, v10.4s
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e78d547		fadd v7.2d, v10.2d, v24.2d
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e27d6ea		fadd v10.2s, v23.2s, v7.2s
+#   v10: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e2bd6d0		fadd v16.4s, v22.4s, v11.4s
+#   v16: 0x01000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7e70db9b		faddp d27, v28.2d
+#   v27: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7e30daf4		faddp s20, v23.2s
+#   v20: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e6bd495		faddp v21.2d, v4.2d, v11.2d
+#   v21: 0x01000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e21d75f		faddp v31.2s, v26.2s, v1.2s
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e3cd76d		faddp v13.4s, v27.4s, v28.4s
+#   v13: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e74e5b1		fcmeq v17.2d, v13.2d, v20.2d
+#   v17: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4ee0da18		fcmeq v24.2d, v16.2d, #0.0
+#   v24: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  0e2ae63a		fcmeq v26.2s, v17.2s, v10.2s
+#   v26: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ea0d898		fcmeq v24.2s, v4.2s, #0.0
+#   v24: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4e2ee488		fcmeq v8.4s, v4.4s, v14.4s
+#    v8: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4ea0db3a		fcmeq v26.4s, v25.4s, #0.0
+#   v26: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  6e60e41b		fcmge v27.2d, v0.2d, v0.2d
+#   v27: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  6ee0cbd6		fcmge v22.2d, v30.2d, #0.0
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e39e6a7		fcmge v7.2s, v21.2s, v25.2s
+#    v7: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  2ea0c9ef		fcmge v15.2s, v15.2s, #0.0
+#   v15: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  6e3be49d		fcmge v29.4s, v4.4s, v27.4s
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ea0cab6		fcmge v22.4s, v21.4s, #0.0
+#   v22: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  6eefe741		fcmgt v1.2d, v26.2d, v15.2d
+#    v1: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ee0caef		fcmgt v15.2d, v23.2d, #0.0
+#   v15: 0xffffffffffffffff0000000000000000
+0x~~~~~~~~~~~~~~~~  2ea6e615		fcmgt v21.2s, v16.2s, v6.2s
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ea0c9a1		fcmgt v1.2s, v13.2s, #0.0
+#    v1: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6eb9e40e		fcmgt v14.4s, v0.4s, v25.4s
+#   v14: 0xffffffff000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ea0c90d		fcmgt v13.4s, v8.4s, #0.0
+#   v13: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ee0d8c4		fcmle v4.2d, v6.2d, #0.0
+#    v4: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  2ea0dbf8		fcmle v24.2s, v31.2s, #0.0
+#   v24: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  6ea0dae8		fcmle v8.4s, v23.4s, #0.0
+#    v8: 0x00000000ffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4ee0e867		fcmlt v7.2d, v3.2d, #0.0
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ea0eaaf		fcmlt v15.2s, v21.2s, #0.0
+#   v15: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ea0e841		fcmlt v1.4s, v2.4s, #0.0
+#    v1: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e61c906		fcvtas v6.2d, v8.2d
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e21c921		fcvtas v1.2s, v9.2s
+#    v1: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e21ca68		fcvtas v8.4s, v19.4s
+#    v8: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e61cbe5		fcvtau v5.2d, v31.2d
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e21cbbc		fcvtau v28.2s, v29.2s
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e21cb4b		fcvtau v11.4s, v26.4s
+#   v11: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e617b28		fcvtl v8.2d, v25.2s
+#    v8: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e2179db		fcvtl v27.4s, v14.4h
+#   v27: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e6178c1		fcvtl2 v1.2d, v6.4s
+#    v1: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e217938		fcvtl2 v24.4s, v9.8h
+#   v24: 0x37000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e61bb09		fcvtms v9.2d, v24.2d
+#    v9: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e21b967		fcvtms v7.2s, v11.2s
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e21bab7		fcvtms v23.4s, v21.4s
+#   v23: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e61b82d		fcvtmu v13.2d, v1.2d
+#   v13: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e21b99a		fcvtmu v26.2s, v12.2s
+#   v26: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e21bab5		fcvtmu v21.4s, v21.4s
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e61682b		fcvtn v11.2s, v1.2d
+#   v11: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e216848		fcvtn v8.4h, v2.4s
+#    v8: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e616bb8		fcvtn2 v24.4s, v29.2d
+#   v24: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e216944		fcvtn2 v4.8h, v10.4s
+#    v4: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4e61a959		fcvtns v25.2d, v10.2d
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e21a904		fcvtns v4.2s, v8.2s
+#    v4: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e21ab7d		fcvtns v29.4s, v27.4s
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e61ab72		fcvtnu v18.2d, v27.2d
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e21a9cb		fcvtnu v11.2s, v14.2s
+#   v11: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e21aabb		fcvtnu v27.4s, v21.4s
+#   v27: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ee1a8b7		fcvtps v23.2d, v5.2d
+#   v23: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ea1a9f8		fcvtps v24.2s, v15.2s
+#   v24: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ea1aa65		fcvtps v5.4s, v19.4s
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ee1aaa3		fcvtpu v3.2d, v21.2d
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2ea1aaa3		fcvtpu v3.2s, v21.2s
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ea1a8e0		fcvtpu v0.4s, v7.4s
+#    v0: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e61697d		fcvtxn v29.2s, v11.2d
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e616b3f		fcvtxn2 v31.4s, v25.2d
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ee1ba33		fcvtzs v19.2d, v17.2d
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f40ff0c		fcvtzs v12.2d, v24.2d, #64
+#   v12: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ea1b849		fcvtzs v9.2s, v2.2s
+#    v9: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0f23fe85		fcvtzs v5.2s, v20.2s, #29
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ea1bb35		fcvtzs v21.4s, v25.4s
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f3afc3a		fcvtzs v26.4s, v1.4s, #6
+#   v26: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ee1bb2d		fcvtzu v13.2d, v25.2d
+#   v13: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f60fdbc		fcvtzu v28.2d, v13.2d, #32
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2ea1b8da		fcvtzu v26.2s, v6.2s
+#   v26: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f31fd49		fcvtzu v9.2s, v10.2s, #15
+#    v9: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ea1b8de		fcvtzu v30.4s, v6.4s
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f2efed3		fcvtzu v19.4s, v22.4s, #18
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e6ffd0f		fdiv v15.2d, v8.2d, v15.2d
+#   v15: 0x7ff80000000000007ff8000000000000
+0x~~~~~~~~~~~~~~~~  2e3afd2c		fdiv v12.2s, v9.2s, v26.2s
+#   v12: 0x00000000000000007fc000007fc00000
+0x~~~~~~~~~~~~~~~~  6e33fed3		fdiv v19.4s, v22.4s, v19.4s
+#   v19: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4e68f4f3		fmax v19.2d, v7.2d, v8.2d
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e3df599		fmax v25.2s, v12.2s, v29.2s
+#   v25: 0x00000000000000007fc000007fc00000
+0x~~~~~~~~~~~~~~~~  4e25f5e6		fmax v6.4s, v15.4s, v5.4s
+#    v6: 0x7ff80000000000007ff8000000000000
+0x~~~~~~~~~~~~~~~~  4e74c510		fmaxnm v16.2d, v8.2d, v20.2d
+#   v16: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e39c74f		fmaxnm v15.2s, v26.2s, v25.2s
+#   v15: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e30c5d7		fmaxnm v23.4s, v14.4s, v16.4s
+#   v23: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7e70ca66		fmaxnmp d6, v19.2d
+#    v6: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7e30cb5b		fmaxnmp s27, v26.2s
+#   v27: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e77c588		fmaxnmp v8.2d, v12.2d, v23.2d
+#    v8: 0x00000000000000007fc000007fc00000
+0x~~~~~~~~~~~~~~~~  2e36c72d		fmaxnmp v13.2s, v25.2s, v22.2s
+#   v13: 0x0000000000000000ffffffff7fc00000
+0x~~~~~~~~~~~~~~~~  6e31c56f		fmaxnmp v15.4s, v11.4s, v17.4s
+#   v15: 0xffffffffffffffff0000000000000000
+0x~~~~~~~~~~~~~~~~  6e30ca7b		fmaxnmv s27, v19.4s
+#   v27: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7e70f9d4		fmaxp d20, v14.2d
+#   v20: 0x0000000000000000ffffffff00000000
+0x~~~~~~~~~~~~~~~~  7e30f852		fmaxp s18, v2.2s
+#   v18: 0x000000000000000000000000000000ff
+0x~~~~~~~~~~~~~~~~  6e7ff6e9		fmaxp v9.2d, v23.2d, v31.2d
+#    v9: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e3ff6c7		fmaxp v7.2s, v22.2s, v31.2s
+#    v7: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  6e3df4f2		fmaxp v18.4s, v7.4s, v29.4s
+#   v18: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  6e30fbbf		fmaxv s31, v29.4s
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ee2f4a2		fmin v2.2d, v5.2d, v2.2d
+#    v2: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0eaaf63f		fmin v31.2s, v17.2s, v10.2s
+#   v31: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4eb0f48a		fmin v10.4s, v4.4s, v16.4s
+#   v10: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ee5c4d5		fminnm v21.2d, v6.2d, v5.2d
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0eaec656		fminnm v22.2s, v18.2s, v14.2s
+#   v22: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4ea3c7f9		fminnm v25.4s, v31.4s, v3.4s
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7ef0c829		fminnmp d9, v1.2d
+#    v9: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7eb0ca95		fminnmp s21, v20.2s
+#   v21: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ef3c6b0		fminnmp v16.2d, v21.2d, v19.2d
+#   v16: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2eb9c7f0		fminnmp v16.2s, v31.2s, v25.2s
+#   v16: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  6eafc61a		fminnmp v26.4s, v16.4s, v15.4s
+#   v26: 0xffffffff000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6eb0c883		fminnmv s3, v4.4s
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7ef0fb58		fminp d24, v26.2d
+#   v24: 0x0000000000000000ffffffff00000000
+0x~~~~~~~~~~~~~~~~  7eb0fa27		fminp s7, v17.2s
+#    v7: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  6ee3f677		fminp v23.2d, v19.2d, v3.2d
+#   v23: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2ea9f6bd		fminp v29.2s, v21.2s, v9.2s
+#   v29: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6eb5f700		fminp v0.4s, v24.4s, v21.4s
+#    v0: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  6eb0f919		fminv s25, v8.4s
+#   v25: 0x0000000000000000000000007fc00000
+0x~~~~~~~~~~~~~~~~  5fc91817		fmla d23, d0, v9.d[2]
+#   v23: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5f8711f7		fmla s23, s15, v7.s[0]
+#   v23: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  4e66cd71		fmla v17.2d, v11.2d, v6.2d
+#   v17: 0xffffffffffffffffffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4fcb13de		fmla v30.2d, v30.2d, v11.d[0]
+#   v30: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e26cd93		fmla v19.2s, v12.2s, v6.2s
+#   v19: 0x00000000000000007fc000007fc00000
+0x~~~~~~~~~~~~~~~~  0f891238		fmla v24.2s, v17.2s, v9.s[0]
+#   v24: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4e2bcd70		fmla v16.4s, v11.4s, v11.4s
+#   v16: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  4f891afb		fmla v27.4s, v23.4s, v9.s[2]
+#   v27: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  5fc653db		fmls d27, d30, v6.d[0]
+#   v27: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  5f825215		fmls s21, s16, v2.s[0]
+#   v21: 0x0000000000000000000000007fffffff
+0x~~~~~~~~~~~~~~~~  4ef5ce65		fmls v5.2d, v19.2d, v21.2d
+#    v5: 0x0000000000000000be9000007f9fffff
+0x~~~~~~~~~~~~~~~~  4fcc53d2		fmls v18.2d, v30.2d, v12.d[0]
+#   v18: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  0ea7ce05		fmls v5.2s, v16.2s, v7.2s
+#    v5: 0x0000000000000000be9000007fdfffff
+0x~~~~~~~~~~~~~~~~  0fab5243		fmls v3.2s, v18.2s, v11.s[1]
+#    v3: 0x0000000000000000000000007fffffff
+0x~~~~~~~~~~~~~~~~  4ebeccbb		fmls v27.4s, v5.4s, v30.4s
+#   v27: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  4fa45a9a		fmls v26.4s, v20.4s, v4.s[3]
+#   v26: 0xffffffff000000007fffffff00000000
+0x~~~~~~~~~~~~~~~~  6f06f6ce		fmov v14.2d, #0xd6 (-0.3438)
+#   v14: 0xbfd6000000000000bfd6000000000000
+0x~~~~~~~~~~~~~~~~  0f03f5ba		fmov v26.2s, #0x6d (0.9062)
+#   v26: 0x00000000000000003f6800003f680000
+0x~~~~~~~~~~~~~~~~  4f04f69f		fmov v31.4s, #0x94 (-5.0000)
+#   v31: 0xc0a00000c0a00000c0a00000c0a00000
+0x~~~~~~~~~~~~~~~~  9eaf033c		fmov v28.D[1], x25
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  9eae0052		fmov x18, v2.D[1]
+#   x18: 0x0000000000000000
+0x~~~~~~~~~~~~~~~~  5fc1988c		fmul d12, d4, v1.d[2]
+#   v12: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  5faf983e		fmul s30, s1, v15.s[3]
+#   v30: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  6e75dc19		fmul v25.2d, v0.2d, v21.2d
+#   v25: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4fca9b0a		fmul v10.2d, v24.2d, v10.d[2]
+#   v10: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  2e30df07		fmul v7.2s, v24.2s, v16.2s
+#    v7: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  0f849a01		fmul v1.2s, v16.2s, v4.s[2]
+#    v1: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  6e39df85		fmul v5.4s, v28.4s, v25.4s
+#    v5: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4f88906b		fmul v11.4s, v3.4s, v8.s[0]
+#   v11: 0x7fc000007fc000007fc000007fffffff
+0x~~~~~~~~~~~~~~~~  7fc3993c		fmulx d28, d9, v3.d[2]
+#   v28: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  7faf92b9		fmulx s25, s21, v15.s[1]
+#   v25: 0x0000000000000000000000007fffffff
+0x~~~~~~~~~~~~~~~~  4e68df9f		fmulx v31.2d, v28.2d, v8.2d
+#   v31: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6fc692a3		fmulx v3.2d, v21.2d, v6.d[0]
+#    v3: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e20dc29		fmulx v9.2s, v1.2s, v0.2s
+#    v9: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  2f869370		fmulx v16.2s, v27.2s, v6.s[0]
+#   v16: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  4e25dc82		fmulx v2.4s, v4.4s, v5.4s
+#    v2: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6f8490f2		fmulx v18.4s, v7.4s, v4.s[0]
+#   v18: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  6ee0fb21		fneg v1.2d, v25.2d
+#    v1: 0x8000000000000000800000007fffffff
+0x~~~~~~~~~~~~~~~~  2ea0fbee		fneg v14.2s, v31.2s
+#   v14: 0x00000000000000008000000080000000
+0x~~~~~~~~~~~~~~~~  6ea0f885		fneg v5.4s, v4.4s
+#    v5: 0x80000000800000008000000080000000
+0x~~~~~~~~~~~~~~~~  4ee1d992		frecpe v18.2d, v12.2d
+#   v18: 0x7ff00000000000007ff0000000000000
+0x~~~~~~~~~~~~~~~~  0ea1daca		frecpe v10.2s, v22.2s
+#   v10: 0x00000000000000007f8000007f800000
+0x~~~~~~~~~~~~~~~~  4ea1d8c5		frecpe v5.4s, v6.4s
+#    v5: 0x7f8000007f8000007f8000007f800000
+0x~~~~~~~~~~~~~~~~  4e7afcf6		frecps v22.2d, v7.2d, v26.2d
+#   v22: 0x40000000000000007fffffffffffffff
+0x~~~~~~~~~~~~~~~~  0e22ff7f		frecps v31.2s, v27.2s, v2.2s
+#   v31: 0x0000000000000000400000007fffffff
+0x~~~~~~~~~~~~~~~~  4e3bfcd2		frecps v18.4s, v6.4s, v27.4s
+#   v18: 0x400000004000000040000000ffffffff
+0x~~~~~~~~~~~~~~~~  6e6189ba		frinta v26.2d, v13.2d
+#   v26: 0x0000000000000000ffffffff7fc00000
+0x~~~~~~~~~~~~~~~~  2e218b4f		frinta v15.2s, v26.2s
+#   v15: 0x0000000000000000ffffffff7fc00000
+0x~~~~~~~~~~~~~~~~  6e218a0d		frinta v13.4s, v16.4s
+#   v13: 0x000000000000000000000000ffffffff
+0x~~~~~~~~~~~~~~~~  6ee19989		frinti v9.2d, v12.2d
+#    v9: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2ea19a65		frinti v5.2s, v19.2s
+#    v5: 0x00000000000000007fc000007fc00000
+0x~~~~~~~~~~~~~~~~  6ea1996f		frinti v15.4s, v11.4s
+#   v15: 0x7fc000007fc000007fc000007fffffff
+0x~~~~~~~~~~~~~~~~  4e619bb1		frintm v17.2d, v29.2d
+#   v17: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e21997e		frintm v30.2s, v11.2s
+#   v30: 0x00000000000000007fc000007fffffff
+0x~~~~~~~~~~~~~~~~  4e219a81		frintm v1.4s, v20.4s
+#    v1: 0x0000000000000000ffffffff00000000
+0x~~~~~~~~~~~~~~~~  4e6188d8		frintn v24.2d, v6.2d
+#   v24: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0e218a2c		frintn v12.2s, v17.2s
+#   v12: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e21897d		frintn v29.4s, v11.4s
+#   v29: 0x7fc000007fc000007fc000007fffffff
+0x~~~~~~~~~~~~~~~~  4ee188ea		frintp v10.2d, v7.2d
+#   v10: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  0ea18a4c		frintp v12.2s, v18.2s
+#   v12: 0x000000000000000040000000ffffffff
+0x~~~~~~~~~~~~~~~~  4ea18bfa		frintp v26.4s, v31.4s
+#   v26: 0x0000000000000000400000007fffffff
+0x~~~~~~~~~~~~~~~~  6e6199b8		frintx v24.2d, v13.2d
+#   v24: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2e219927		frintx v7.2s, v9.2s
+#    v7: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e219ab2		frintx v18.4s, v21.4s
+#   v18: 0x0000000000000000000000007fffffff
+0x~~~~~~~~~~~~~~~~  4ee19b33		frintz v19.2d, v25.2d
+#   v19: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  0ea1990f		frintz v15.2s, v8.2s
+#   v15: 0x00000000000000007fc000007fc00000
+0x~~~~~~~~~~~~~~~~  4ea19874		frintz v20.4s, v3.4s
+#   v20: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  6ee1d8b7		frsqrte v23.2d, v5.2d
+#   v23: 0x7ff00000000000002006900000000000
+0x~~~~~~~~~~~~~~~~  2ea1d8e9		frsqrte v9.2s, v7.2s
+#    v9: 0x00000000000000007f8000007f800000
+0x~~~~~~~~~~~~~~~~  6ea1d923		frsqrte v3.4s, v9.4s
+#    v3: 0x7f8000007f8000000000000000000000
+0x~~~~~~~~~~~~~~~~  4eefff99		frsqrts v25.2d, v28.2d, v15.2d
+#   v25: 0x3ff80000000000003ff8000000000000
+0x~~~~~~~~~~~~~~~~  0eaaff49		frsqrts v9.2s, v26.2s, v10.2s
+#    v9: 0x0000000000000000ffffffffffffffff
+0x~~~~~~~~~~~~~~~~  4eaafc25		frsqrts v5.4s, v1.4s, v10.4s
+#    v5: 0x3fc000003fc000007fffffffffffffff
+0x~~~~~~~~~~~~~~~~  6ee1fa46		fsqrt v6.2d, v18.2d
+#    v6: 0x00000000000000001f56a09e66689b2e
+0x~~~~~~~~~~~~~~~~  2ea1fa46		fsqrt v6.2s, v18.2s
+#    v6: 0x0000000000000000000000007fffffff
+0x~~~~~~~~~~~~~~~~  6ea1fbe0		fsqrt v0.4s, v31.4s
+#    v0: 0x00000000000000003fb504f37fffffff
+0x~~~~~~~~~~~~~~~~  4effd7df		fsub v31.2d, v30.2d, v31.2d
+#   v31: 0x00000000000000007fc000007fffffff
+0x~~~~~~~~~~~~~~~~  0ea6d50b		fsub v11.2s, v8.2s, v6.2s
+#   v11: 0x00000000000000007fc000007fc00000
+0x~~~~~~~~~~~~~~~~  4ebfd410		fsub v16.4s, v0.4s, v31.4s
+#   v16: 0x00000000000000007fc000007fffffff
+0x~~~~~~~~~~~~~~~~  4e61dbf9		scvtf v25.2d, v31.2d
+#   v25: 0x000000000000000043dff00000200000
+0x~~~~~~~~~~~~~~~~  4f53e5aa		scvtf v10.2d, v13.2d, #45
+#   v10: 0x00000000000000003f1fffffffe00000
+0x~~~~~~~~~~~~~~~~  0e21d9ea		scvtf v10.2s, v15.2s
+#   v10: 0x00000000000000004eff80004eff8000
+0x~~~~~~~~~~~~~~~~  0f25e492		scvtf v18.2s, v4.2s, #27
+#   v18: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  4e21d8b1		scvtf v17.4s, v5.4s
+#   v17: 0x4e7f00004e7f00004f000000bf800000
+0x~~~~~~~~~~~~~~~~  4f28e72b		scvtf v11.4s, v25.4s, #24
+#   v11: 0x00000000000000004287bfe03e000000
+0x~~~~~~~~~~~~~~~~  6e61d869		ucvtf v9.2d, v3.2d
+#    v9: 0x43dfe000001fe0000000000000000000
+0x~~~~~~~~~~~~~~~~  6f52e7da		ucvtf v26.2d, v30.2d, #46
+#   v26: 0x000000000000000040fff00000200000
+0x~~~~~~~~~~~~~~~~  2e21d88b		ucvtf v11.2s, v4.2s
+#   v11: 0x00000000000000000000000000000000
+0x~~~~~~~~~~~~~~~~  2f27e47d		ucvtf v29.2s, v3.2s, #25
+#   v29: 0x7fc000007fc000000000000000000000
+0x~~~~~~~~~~~~~~~~  6e21daf6		ucvtf v22.4s, v23.4s
+#   v22: 0x4effe000000000004e001a4000000000
+0x~~~~~~~~~~~~~~~~  6f27e532		ucvtf v18.4s, v9.4s, #25
+#   v18: 0x4207bfc03d7f00000000000000000000
+0x~~~~~~~~~~~~~~~~  d65f03c0		ret
diff --git a/test/test-trace-reference/log-disasm b/test/test-trace-reference/log-disasm
new file mode 100644
index 0000000..f1ca65c
--- /dev/null
+++ b/test/test-trace-reference/log-disasm
@@ -0,0 +1,2381 @@
+0x~~~~~~~~~~~~~~~~  1a050083		adc w3, w4, w5
+0x~~~~~~~~~~~~~~~~  9a0800e6		adc x6, x7, x8
+0x~~~~~~~~~~~~~~~~  3a0b0149		adcs w9, w10, w11
+0x~~~~~~~~~~~~~~~~  ba0e01ac		adcs x12, x13, x14
+0x~~~~~~~~~~~~~~~~  0b11020f		add w15, w16, w17
+0x~~~~~~~~~~~~~~~~  8b140272		add x18, x19, x20
+0x~~~~~~~~~~~~~~~~  2b1702d5		adds w21, w22, w23
+0x~~~~~~~~~~~~~~~~  ab1a0338		adds x24, x25, x26
+0x~~~~~~~~~~~~~~~~  0a1d039b		and w27, w28, w29
+0x~~~~~~~~~~~~~~~~  8a040062		and x2, x3, x4
+0x~~~~~~~~~~~~~~~~  6a0700c5		ands w5, w6, w7
+0x~~~~~~~~~~~~~~~~  ea0a0128		ands x8, x9, x10
+0x~~~~~~~~~~~~~~~~  13007d8b		sbfx w11, w12, #0, #32
+0x~~~~~~~~~~~~~~~~  9341fdcd		asr x13, x14, #1
+0x~~~~~~~~~~~~~~~~  1ad12a0f		asr w15, w16, w17
+0x~~~~~~~~~~~~~~~~  9ad42a72		asr x18, x19, x20
+0x~~~~~~~~~~~~~~~~  33051ad5		bfxil w21, w22, #5, #2
+0x~~~~~~~~~~~~~~~~  b3472317		bfxil x23, x24, #7, #2
+0x~~~~~~~~~~~~~~~~  0a3b0359		bic w25, w26, w27
+0x~~~~~~~~~~~~~~~~  8a2203bc		bic x28, x29, x2
+0x~~~~~~~~~~~~~~~~  6a250083		bics w3, w4, w5
+0x~~~~~~~~~~~~~~~~  ea2800e6		bics x6, x7, x8
+0x~~~~~~~~~~~~~~~~  3a4ae120		ccmn w9, w10, #nzcv, al
+0x~~~~~~~~~~~~~~~~  3a4a0120		ccmn w9, w10, #nzcv, eq
+0x~~~~~~~~~~~~~~~~  3a4a1120		ccmn w9, w10, #nzcv, ne
+0x~~~~~~~~~~~~~~~~  ba4ce162		ccmn x11, x12, #nzCv, al
+0x~~~~~~~~~~~~~~~~  ba4c3162		ccmn x11, x12, #nzCv, lo
+0x~~~~~~~~~~~~~~~~  ba4c2162		ccmn x11, x12, #nzCv, hs
+0x~~~~~~~~~~~~~~~~  7a4ee1a1		ccmp w13, w14, #nzcV, al
+0x~~~~~~~~~~~~~~~~  7a4e81a1		ccmp w13, w14, #nzcV, hi
+0x~~~~~~~~~~~~~~~~  7a4e91a1		ccmp w13, w14, #nzcV, ls
+0x~~~~~~~~~~~~~~~~  fa50e1e3		ccmp x15, x16, #nzCV, al
+0x~~~~~~~~~~~~~~~~  fa5001e3		ccmp x15, x16, #nzCV, eq
+0x~~~~~~~~~~~~~~~~  fa5011e3		ccmp x15, x16, #nzCV, ne
+0x~~~~~~~~~~~~~~~~  1a922651		cinc w17, w18, lo
+0x~~~~~~~~~~~~~~~~  1a923651		cinc w17, w18, hs
+0x~~~~~~~~~~~~~~~~  9a949693		cinc x19, x20, hi
+0x~~~~~~~~~~~~~~~~  9a948693		cinc x19, x20, ls
+0x~~~~~~~~~~~~~~~~  5a9612d5		cinv w21, w22, eq
+0x~~~~~~~~~~~~~~~~  5a9602d5		cinv w21, w22, ne
+0x~~~~~~~~~~~~~~~~  da982317		cinv x23, x24, lo
+0x~~~~~~~~~~~~~~~~  da983317		cinv x23, x24, hs
+0x~~~~~~~~~~~~~~~~  d5033f5f		clrex
+0x~~~~~~~~~~~~~~~~  5ac01759		cls w25, w26
+0x~~~~~~~~~~~~~~~~  dac0179b		cls x27, x28
+0x~~~~~~~~~~~~~~~~  5ac0105d		clz w29, w2
+0x~~~~~~~~~~~~~~~~  dac01083		clz x3, x4
+0x~~~~~~~~~~~~~~~~  2b0600bf		cmn w5, w6
+0x~~~~~~~~~~~~~~~~  ab0800ff		cmn x7, x8
+0x~~~~~~~~~~~~~~~~  6b0a013f		cmp w9, w10
+0x~~~~~~~~~~~~~~~~  eb0c017f		cmp x11, x12
+0x~~~~~~~~~~~~~~~~  5a8e95cd		cneg w13, w14, hi
+0x~~~~~~~~~~~~~~~~  5a8e85cd		cneg w13, w14, ls
+0x~~~~~~~~~~~~~~~~  da90160f		cneg x15, x16, eq
+0x~~~~~~~~~~~~~~~~  da90060f		cneg x15, x16, ne
+0x~~~~~~~~~~~~~~~~  1ad34251		crc32b w17, w18, w19
+0x~~~~~~~~~~~~~~~~  1ad652b4		crc32cb w20, w21, w22
+0x~~~~~~~~~~~~~~~~  1ad95717		crc32ch w23, w24, w25
+0x~~~~~~~~~~~~~~~~  1adc5b7a		crc32cw w26, w27, w28
+0x~~~~~~~~~~~~~~~~  1ac644a4		crc32h w4, w5, w6
+0x~~~~~~~~~~~~~~~~  1ac94907		crc32w w7, w8, w9
+0x~~~~~~~~~~~~~~~~  1a8f31cd		csel w13, w14, w15, lo
+0x~~~~~~~~~~~~~~~~  1a8f21cd		csel w13, w14, w15, hs
+0x~~~~~~~~~~~~~~~~  9a928230		csel x16, x17, x18, hi
+0x~~~~~~~~~~~~~~~~  9a929230		csel x16, x17, x18, ls
+0x~~~~~~~~~~~~~~~~  1a9f17f3		cset w19, eq
+0x~~~~~~~~~~~~~~~~  1a9f07f3		cset w19, ne
+0x~~~~~~~~~~~~~~~~  9a9f27f4		cset x20, lo
+0x~~~~~~~~~~~~~~~~  9a9f37f4		cset x20, hs
+0x~~~~~~~~~~~~~~~~  5a9f93f5		csetm w21, hi
+0x~~~~~~~~~~~~~~~~  5a9f83f5		csetm w21, ls
+0x~~~~~~~~~~~~~~~~  da9f13f6		csetm x22, eq
+0x~~~~~~~~~~~~~~~~  da9f03f6		csetm x22, ne
+0x~~~~~~~~~~~~~~~~  1a993717		csinc w23, w24, w25, lo
+0x~~~~~~~~~~~~~~~~  1a992717		csinc w23, w24, w25, hs
+0x~~~~~~~~~~~~~~~~  9a9c877a		csinc x26, x27, x28, hi
+0x~~~~~~~~~~~~~~~~  9a9c977a		csinc x26, x27, x28, ls
+0x~~~~~~~~~~~~~~~~  5a83005d		csinv w29, w2, w3, eq
+0x~~~~~~~~~~~~~~~~  5a83105d		csinv w29, w2, w3, ne
+0x~~~~~~~~~~~~~~~~  da8630a4		csinv x4, x5, x6, lo
+0x~~~~~~~~~~~~~~~~  da8620a4		csinv x4, x5, x6, hs
+0x~~~~~~~~~~~~~~~~  5a898507		csneg w7, w8, w9, hi
+0x~~~~~~~~~~~~~~~~  5a899507		csneg w7, w8, w9, ls
+0x~~~~~~~~~~~~~~~~  da8c056a		csneg x10, x11, x12, eq
+0x~~~~~~~~~~~~~~~~  da8c156a		csneg x10, x11, x12, ne
+0x~~~~~~~~~~~~~~~~  d50b7a20		dc cvac, x0
+0x~~~~~~~~~~~~~~~~  d5033bbf		dmb ish
+0x~~~~~~~~~~~~~~~~  d5033b9f		dsb ish
+0x~~~~~~~~~~~~~~~~  4a2f01cd		eon w13, w14, w15
+0x~~~~~~~~~~~~~~~~  ca320230		eon x16, x17, x18
+0x~~~~~~~~~~~~~~~~  4a150293		eor w19, w20, w21
+0x~~~~~~~~~~~~~~~~  ca1802f6		eor x22, x23, x24
+0x~~~~~~~~~~~~~~~~  139b2759		extr w25, w26, w27, #9
+0x~~~~~~~~~~~~~~~~  93c22bbc		extr x28, x29, x2, #10
+0x~~~~~~~~~~~~~~~~  d503201f		nop
+0x~~~~~~~~~~~~~~~~  d50b7520		ic ivau, x0
+0x~~~~~~~~~~~~~~~~  d5033fdf		isb
+0x~~~~~~~~~~~~~~~~  88dffc03		ldar w3, [x0]
+0x~~~~~~~~~~~~~~~~  c8dffc04		ldar x4, [x0]
+0x~~~~~~~~~~~~~~~~  08dffc05		ldarb w5, [x0]
+0x~~~~~~~~~~~~~~~~  08dffc06		ldarb w6, [x0]
+0x~~~~~~~~~~~~~~~~  48dffc07		ldarh w7, [x0]
+0x~~~~~~~~~~~~~~~~  48dffc08		ldarh w8, [x0]
+0x~~~~~~~~~~~~~~~~  887fa809		ldaxp w9, w10, [x0]
+0x~~~~~~~~~~~~~~~~  c87fb00b		ldaxp x11, x12, [x0]
+0x~~~~~~~~~~~~~~~~  885ffc0d		ldaxr w13, [x0]
+0x~~~~~~~~~~~~~~~~  c85ffc0e		ldaxr x14, [x0]
+0x~~~~~~~~~~~~~~~~  085ffc0f		ldaxrb w15, [x0]
+0x~~~~~~~~~~~~~~~~  085ffc10		ldaxrb w16, [x0]
+0x~~~~~~~~~~~~~~~~  485ffc11		ldaxrh w17, [x0]
+0x~~~~~~~~~~~~~~~~  485ffc12		ldaxrh w18, [x0]
+0x~~~~~~~~~~~~~~~~  28405013		ldnp w19, w20, [x0]
+0x~~~~~~~~~~~~~~~~  a8405815		ldnp x21, x22, [x0]
+0x~~~~~~~~~~~~~~~~  29406017		ldp w23, w24, [x0]
+0x~~~~~~~~~~~~~~~~  28c16037		ldp w23, w24, [x1], #8
+0x~~~~~~~~~~~~~~~~  29c16037		ldp w23, w24, [x1, #8]!
+0x~~~~~~~~~~~~~~~~  a9406819		ldp x25, x26, [x0]
+0x~~~~~~~~~~~~~~~~  a8c16839		ldp x25, x26, [x1], #16
+0x~~~~~~~~~~~~~~~~  a9c16839		ldp x25, x26, [x1, #16]!
+0x~~~~~~~~~~~~~~~~  6940701b		ldpsw x27, x28, [x0]
+0x~~~~~~~~~~~~~~~~  68c1703b		ldpsw x27, x28, [x1], #8
+0x~~~~~~~~~~~~~~~~  69c1703b		ldpsw x27, x28, [x1, #8]!
+0x~~~~~~~~~~~~~~~~  b940001d		ldr w29, [x0]
+0x~~~~~~~~~~~~~~~~  b840443d		ldr w29, [x1], #4
+0x~~~~~~~~~~~~~~~~  b8404c3d		ldr w29, [x1, #4]!
+0x~~~~~~~~~~~~~~~~  f9400002		ldr x2, [x0]
+0x~~~~~~~~~~~~~~~~  f8408422		ldr x2, [x1], #8
+0x~~~~~~~~~~~~~~~~  f8408c22		ldr x2, [x1, #8]!
+0x~~~~~~~~~~~~~~~~  39400003		ldrb w3, [x0]
+0x~~~~~~~~~~~~~~~~  38401423		ldrb w3, [x1], #1
+0x~~~~~~~~~~~~~~~~  38401c23		ldrb w3, [x1, #1]!
+0x~~~~~~~~~~~~~~~~  39400004		ldrb w4, [x0]
+0x~~~~~~~~~~~~~~~~  38401424		ldrb w4, [x1], #1
+0x~~~~~~~~~~~~~~~~  38401c24		ldrb w4, [x1, #1]!
+0x~~~~~~~~~~~~~~~~  79400005		ldrh w5, [x0]
+0x~~~~~~~~~~~~~~~~  78402425		ldrh w5, [x1], #2
+0x~~~~~~~~~~~~~~~~  78402c25		ldrh w5, [x1, #2]!
+0x~~~~~~~~~~~~~~~~  79400006		ldrh w6, [x0]
+0x~~~~~~~~~~~~~~~~  78402426		ldrh w6, [x1], #2
+0x~~~~~~~~~~~~~~~~  78402c26		ldrh w6, [x1, #2]!
+0x~~~~~~~~~~~~~~~~  39c00007		ldrsb w7, [x0]
+0x~~~~~~~~~~~~~~~~  38c01427		ldrsb w7, [x1], #1
+0x~~~~~~~~~~~~~~~~  38c01c27		ldrsb w7, [x1, #1]!
+0x~~~~~~~~~~~~~~~~  39800008		ldrsb x8, [x0]
+0x~~~~~~~~~~~~~~~~  38801428		ldrsb x8, [x1], #1
+0x~~~~~~~~~~~~~~~~  38801c28		ldrsb x8, [x1, #1]!
+0x~~~~~~~~~~~~~~~~  79c00009		ldrsh w9, [x0]
+0x~~~~~~~~~~~~~~~~  78c02429		ldrsh w9, [x1], #2
+0x~~~~~~~~~~~~~~~~  78c02c29		ldrsh w9, [x1, #2]!
+0x~~~~~~~~~~~~~~~~  7980000a		ldrsh x10, [x0]
+0x~~~~~~~~~~~~~~~~  7880242a		ldrsh x10, [x1], #2
+0x~~~~~~~~~~~~~~~~  78802c2a		ldrsh x10, [x1, #2]!
+0x~~~~~~~~~~~~~~~~  b980000b		ldrsw x11, [x0]
+0x~~~~~~~~~~~~~~~~  b880442b		ldrsw x11, [x1], #4
+0x~~~~~~~~~~~~~~~~  b8804c2b		ldrsw x11, [x1, #4]!
+0x~~~~~~~~~~~~~~~~  b840700c		ldur w12, [x0, #7]
+0x~~~~~~~~~~~~~~~~  f840f00d		ldur x13, [x0, #15]
+0x~~~~~~~~~~~~~~~~  3840100e		ldurb w14, [x0, #1]
+0x~~~~~~~~~~~~~~~~  3840100f		ldurb w15, [x0, #1]
+0x~~~~~~~~~~~~~~~~  78403010		ldurh w16, [x0, #3]
+0x~~~~~~~~~~~~~~~~  78403011		ldurh w17, [x0, #3]
+0x~~~~~~~~~~~~~~~~  38c01012		ldursb w18, [x0, #1]
+0x~~~~~~~~~~~~~~~~  38801013		ldursb x19, [x0, #1]
+0x~~~~~~~~~~~~~~~~  78c03014		ldursh w20, [x0, #3]
+0x~~~~~~~~~~~~~~~~  78803015		ldursh x21, [x0, #3]
+0x~~~~~~~~~~~~~~~~  b8807016		ldursw x22, [x0, #7]
+0x~~~~~~~~~~~~~~~~  887f6017		ldxp w23, w24, [x0]
+0x~~~~~~~~~~~~~~~~  c87f6819		ldxp x25, x26, [x0]
+0x~~~~~~~~~~~~~~~~  885f7c1b		ldxr w27, [x0]
+0x~~~~~~~~~~~~~~~~  c85f7c1c		ldxr x28, [x0]
+0x~~~~~~~~~~~~~~~~  085f7c1d		ldxrb w29, [x0]
+0x~~~~~~~~~~~~~~~~  085f7c02		ldxrb w2, [x0]
+0x~~~~~~~~~~~~~~~~  485f7c03		ldxrh w3, [x0]
+0x~~~~~~~~~~~~~~~~  485f7c04		ldxrh w4, [x0]
+0x~~~~~~~~~~~~~~~~  531e74c5		lsl w5, w6, #2
+0x~~~~~~~~~~~~~~~~  d37df107		lsl x7, x8, #3
+0x~~~~~~~~~~~~~~~~  1acb2149		lsl w9, w10, w11
+0x~~~~~~~~~~~~~~~~  9ace21ac		lsl x12, x13, x14
+0x~~~~~~~~~~~~~~~~  53047e0f		lsr w15, w16, #4
+0x~~~~~~~~~~~~~~~~  d345fe51		lsr x17, x18, #5
+0x~~~~~~~~~~~~~~~~  1ad52693		lsr w19, w20, w21
+0x~~~~~~~~~~~~~~~~  9ad826f6		lsr x22, x23, x24
+0x~~~~~~~~~~~~~~~~  1b1b7359		madd w25, w26, w27, w28
+0x~~~~~~~~~~~~~~~~  9b03105d		madd x29, x2, x3, x4
+0x~~~~~~~~~~~~~~~~  1b07fcc5		mneg w5, w6, w7
+0x~~~~~~~~~~~~~~~~  9b0afd28		mneg x8, x9, x10
+0x~~~~~~~~~~~~~~~~  2a0c03eb		mov w11, w12
+0x~~~~~~~~~~~~~~~~  aa0e03ed		mov x13, x14
+0x~~~~~~~~~~~~~~~~  7280104f		movk w15, #0x82
+0x~~~~~~~~~~~~~~~~  f2801070		movk x16, #0x83
+0x~~~~~~~~~~~~~~~~  12801091		mov w17, #0xffffff7b
+0x~~~~~~~~~~~~~~~~  928010b2		mov x18, #0xffffffffffffff7a
+0x~~~~~~~~~~~~~~~~  528010d3		mov w19, #0x86
+0x~~~~~~~~~~~~~~~~  d28010f4		mov x20, #0x87
+0x~~~~~~~~~~~~~~~~  1b18e6f6		msub w22, w23, w24, w25
+0x~~~~~~~~~~~~~~~~  9b1cf77a		msub x26, x27, x28, x29
+0x~~~~~~~~~~~~~~~~  1b047c62		mul w2, w3, w4
+0x~~~~~~~~~~~~~~~~  9b077cc5		mul x5, x6, x7
+0x~~~~~~~~~~~~~~~~  2a2903e8		mvn w8, w9
+0x~~~~~~~~~~~~~~~~  aa2b03ea		mvn x10, x11
+0x~~~~~~~~~~~~~~~~  4b0d03ec		neg w12, w13
+0x~~~~~~~~~~~~~~~~  cb0f03ee		neg x14, x15
+0x~~~~~~~~~~~~~~~~  6b1103f0		negs w16, w17
+0x~~~~~~~~~~~~~~~~  eb1303f2		negs x18, x19
+0x~~~~~~~~~~~~~~~~  5a1503f4		ngc w20, w21
+0x~~~~~~~~~~~~~~~~  da1703f6		ngc x22, x23
+0x~~~~~~~~~~~~~~~~  7a1903f8		ngcs w24, w25
+0x~~~~~~~~~~~~~~~~  fa1b03fa		ngcs x26, x27
+0x~~~~~~~~~~~~~~~~  d503201f		nop
+0x~~~~~~~~~~~~~~~~  2a2203bc		orn w28, w29, w2
+0x~~~~~~~~~~~~~~~~  aa250083		orn x3, x4, x5
+0x~~~~~~~~~~~~~~~~  2a0800e6		orr w6, w7, w8
+0x~~~~~~~~~~~~~~~~  aa0b0149		orr x9, x10, x11
+0x~~~~~~~~~~~~~~~~  f8804000		prfum pldl1keep, [x0, #4]
+0x~~~~~~~~~~~~~~~~  f8801000		prfum pldl1keep, [x0, #1]
+0x~~~~~~~~~~~~~~~~  5ac001ac		rbit w12, w13
+0x~~~~~~~~~~~~~~~~  dac001ee		rbit x14, x15
+0x~~~~~~~~~~~~~~~~  5ac00a30		rev w16, w17
+0x~~~~~~~~~~~~~~~~  dac00e72		rev x18, x19
+0x~~~~~~~~~~~~~~~~  5ac006b4		rev16 w20, w21
+0x~~~~~~~~~~~~~~~~  dac006f6		rev16 x22, x23
+0x~~~~~~~~~~~~~~~~  dac00b38		rev32 x24, x25
+0x~~~~~~~~~~~~~~~~  1adc2f7a		ror w26, w27, w28
+0x~~~~~~~~~~~~~~~~  9ac32c5d		ror x29, x2, x3
+0x~~~~~~~~~~~~~~~~  5a0600a4		sbc w4, w5, w6
+0x~~~~~~~~~~~~~~~~  da090107		sbc x7, x8, x9
+0x~~~~~~~~~~~~~~~~  7a0c016a		sbcs w10, w11, w12
+0x~~~~~~~~~~~~~~~~  fa0f01cd		sbcs x13, x14, x15
+0x~~~~~~~~~~~~~~~~  131e0a30		sbfiz w16, w17, #2, #3
+0x~~~~~~~~~~~~~~~~  937c1272		sbfiz x18, x19, #4, #5
+0x~~~~~~~~~~~~~~~~  130632f6		sbfx w22, w23, #6, #7
+0x~~~~~~~~~~~~~~~~  93484338		sbfx x24, x25, #8, #9
+0x~~~~~~~~~~~~~~~~  1adc0f7a		sdiv w26, w27, w28
+0x~~~~~~~~~~~~~~~~  9ac30c5d		sdiv x29, x2, x3
+0x~~~~~~~~~~~~~~~~  9b4e7dac		smulh x12, x13, x14
+0x~~~~~~~~~~~~~~~~  889ffc12		stlr w18, [x0]
+0x~~~~~~~~~~~~~~~~  c89ffc13		stlr x19, [x0]
+0x~~~~~~~~~~~~~~~~  089ffc14		stlrb w20, [x0]
+0x~~~~~~~~~~~~~~~~  089ffc15		stlrb w21, [x0]
+0x~~~~~~~~~~~~~~~~  489ffc16		stlrh w22, [x0]
+0x~~~~~~~~~~~~~~~~  489ffc17		stlrh w23, [x0]
+0x~~~~~~~~~~~~~~~~  8838e819		stlxp w24, w25, w26, [x0]
+0x~~~~~~~~~~~~~~~~  c83bf41c		stlxp w27, x28, x29, [x0]
+0x~~~~~~~~~~~~~~~~  8802fc03		stlxr w2, w3, [x0]
+0x~~~~~~~~~~~~~~~~  c804fc05		stlxr w4, x5, [x0]
+0x~~~~~~~~~~~~~~~~  0806fc07		stlxrb w6, w7, [x0]
+0x~~~~~~~~~~~~~~~~  0808fc09		stlxrb w8, w9, [x0]
+0x~~~~~~~~~~~~~~~~  480afc0b		stlxrh w10, w11, [x0]
+0x~~~~~~~~~~~~~~~~  480cfc0d		stlxrh w12, w13, [x0]
+0x~~~~~~~~~~~~~~~~  28003c0e		stnp w14, w15, [x0]
+0x~~~~~~~~~~~~~~~~  a8004410		stnp x16, x17, [x0]
+0x~~~~~~~~~~~~~~~~  29004c12		stp w18, w19, [x0]
+0x~~~~~~~~~~~~~~~~  28814c32		stp w18, w19, [x1], #8
+0x~~~~~~~~~~~~~~~~  29814c32		stp w18, w19, [x1, #8]!
+0x~~~~~~~~~~~~~~~~  a9005414		stp x20, x21, [x0]
+0x~~~~~~~~~~~~~~~~  a8815434		stp x20, x21, [x1], #16
+0x~~~~~~~~~~~~~~~~  a9815434		stp x20, x21, [x1, #16]!
+0x~~~~~~~~~~~~~~~~  b9000016		str w22, [x0]
+0x~~~~~~~~~~~~~~~~  b8004436		str w22, [x1], #4
+0x~~~~~~~~~~~~~~~~  b8004c36		str w22, [x1, #4]!
+0x~~~~~~~~~~~~~~~~  f9000017		str x23, [x0]
+0x~~~~~~~~~~~~~~~~  f8008437		str x23, [x1], #8
+0x~~~~~~~~~~~~~~~~  f8008c37		str x23, [x1, #8]!
+0x~~~~~~~~~~~~~~~~  39000018		strb w24, [x0]
+0x~~~~~~~~~~~~~~~~  38001438		strb w24, [x1], #1
+0x~~~~~~~~~~~~~~~~  38001c38		strb w24, [x1, #1]!
+0x~~~~~~~~~~~~~~~~  39000019		strb w25, [x0]
+0x~~~~~~~~~~~~~~~~  38001439		strb w25, [x1], #1
+0x~~~~~~~~~~~~~~~~  38001c39		strb w25, [x1, #1]!
+0x~~~~~~~~~~~~~~~~  7900001a		strh w26, [x0]
+0x~~~~~~~~~~~~~~~~  7800243a		strh w26, [x1], #2
+0x~~~~~~~~~~~~~~~~  78002c3a		strh w26, [x1, #2]!
+0x~~~~~~~~~~~~~~~~  7900001b		strh w27, [x0]
+0x~~~~~~~~~~~~~~~~  7800243b		strh w27, [x1], #2
+0x~~~~~~~~~~~~~~~~  78002c3b		strh w27, [x1, #2]!
+0x~~~~~~~~~~~~~~~~  b800701c		stur w28, [x0, #7]
+0x~~~~~~~~~~~~~~~~  f800f01d		stur x29, [x0, #15]
+0x~~~~~~~~~~~~~~~~  38001002		sturb w2, [x0, #1]
+0x~~~~~~~~~~~~~~~~  38001003		sturb w3, [x0, #1]
+0x~~~~~~~~~~~~~~~~  78003004		sturh w4, [x0, #3]
+0x~~~~~~~~~~~~~~~~  78003005		sturh w5, [x0, #3]
+0x~~~~~~~~~~~~~~~~  88262007		stxp w6, w7, w8, [x0]
+0x~~~~~~~~~~~~~~~~  c8292c0a		stxp w9, x10, x11, [x0]
+0x~~~~~~~~~~~~~~~~  880c7c0d		stxr w12, w13, [x0]
+0x~~~~~~~~~~~~~~~~  c80e7c0f		stxr w14, x15, [x0]
+0x~~~~~~~~~~~~~~~~  08107c11		stxrb w16, w17, [x0]
+0x~~~~~~~~~~~~~~~~  08127c13		stxrb w18, w19, [x0]
+0x~~~~~~~~~~~~~~~~  48147c15		stxrh w20, w21, [x0]
+0x~~~~~~~~~~~~~~~~  48167c17		stxrh w22, w23, [x0]
+0x~~~~~~~~~~~~~~~~  4b1a0338		sub w24, w25, w26
+0x~~~~~~~~~~~~~~~~  cb1d039b		sub x27, x28, x29
+0x~~~~~~~~~~~~~~~~  6b040062		subs w2, w3, w4
+0x~~~~~~~~~~~~~~~~  eb0700c5		subs x5, x6, x7
+0x~~~~~~~~~~~~~~~~  13001d28		sxtb w8, w9
+0x~~~~~~~~~~~~~~~~  93401d6a		sxtb x10, w11
+0x~~~~~~~~~~~~~~~~  13003dac		sxth w12, w13
+0x~~~~~~~~~~~~~~~~  93403dee		sxth x14, w15
+0x~~~~~~~~~~~~~~~~  13007e30		sbfx w16, w17, #0, #32
+0x~~~~~~~~~~~~~~~~  93407e72		sxtw x18, w19
+0x~~~~~~~~~~~~~~~~  6a15029f		tst w20, w21
+0x~~~~~~~~~~~~~~~~  ea1702df		tst x22, x23
+0x~~~~~~~~~~~~~~~~  53162b38		ubfiz w24, w25, #10, #11
+0x~~~~~~~~~~~~~~~~  d374337a		ubfiz x26, x27, #12, #13
+0x~~~~~~~~~~~~~~~~  530e3fbc		ubfx w28, w29, #14, #2
+0x~~~~~~~~~~~~~~~~  d3410862		ubfx x2, x3, #1, #2
+0x~~~~~~~~~~~~~~~~  530318a4		ubfx w4, w5, #3, #4
+0x~~~~~~~~~~~~~~~~  d34528e6		ubfx x6, x7, #5, #6
+0x~~~~~~~~~~~~~~~~  1aca0928		udiv w8, w9, w10
+0x~~~~~~~~~~~~~~~~  9acd098b		udiv x11, x12, x13
+0x~~~~~~~~~~~~~~~~  9bd87ef6		umulh x22, x23, x24
+0x~~~~~~~~~~~~~~~~  53001fbc		uxtb w28, w29
+0x~~~~~~~~~~~~~~~~  d3401c62		uxtb x2, w3
+0x~~~~~~~~~~~~~~~~  53003ca4		uxth w4, w5
+0x~~~~~~~~~~~~~~~~  d3403ce6		uxth x6, w7
+0x~~~~~~~~~~~~~~~~  53007d28		lsr w8, w9, #0
+0x~~~~~~~~~~~~~~~~  d3407d6a		ubfx x10, x11, #0, #32
+0x~~~~~~~~~~~~~~~~  7ef3d44d		fabd d13, d2, d19
+0x~~~~~~~~~~~~~~~~  7ebed548		fabd s8, s10, s30
+0x~~~~~~~~~~~~~~~~  1e60c021		fabs d1, d1
+0x~~~~~~~~~~~~~~~~  1e20c0f9		fabs s25, s7
+0x~~~~~~~~~~~~~~~~  7e70eee1		facge d1, d23, d16
+0x~~~~~~~~~~~~~~~~  7e21ee24		facge s4, s17, s1
+0x~~~~~~~~~~~~~~~~  7ef8eea2		facgt d2, d21, d24
+0x~~~~~~~~~~~~~~~~  7eacef4c		facgt s12, s26, s12
+0x~~~~~~~~~~~~~~~~  1e76296d		fadd d13, d11, d22
+0x~~~~~~~~~~~~~~~~  1e282a7b		fadd s27, s19, s8
+0x~~~~~~~~~~~~~~~~  1e6a24c0		fccmp d6, d10, #nzcv, hs
+0x~~~~~~~~~~~~~~~~  1e3417ad		fccmp s29, s20, #NZcV, ne
+0x~~~~~~~~~~~~~~~~  1e62e55e		fccmpe d10, d2, #NZCv, al
+0x~~~~~~~~~~~~~~~~  1e23547d		fccmpe s3, s3, #NZcV, pl
+0x~~~~~~~~~~~~~~~~  5e6ae513		fcmeq d19, d8, d10
+0x~~~~~~~~~~~~~~~~  5ee0da40		fcmeq d0, d18, #0.0
+0x~~~~~~~~~~~~~~~~  5e3ee481		fcmeq s1, s4, s30
+0x~~~~~~~~~~~~~~~~  5ea0dbb6		fcmeq s22, s29, #0.0
+0x~~~~~~~~~~~~~~~~  7e61e65b		fcmge d27, d18, d1
+0x~~~~~~~~~~~~~~~~  7ee0cb9f		fcmge d31, d28, #0.0
+0x~~~~~~~~~~~~~~~~  7e29e67f		fcmge s31, s19, s9
+0x~~~~~~~~~~~~~~~~  7ea0cb21		fcmge s1, s25, #0.0
+0x~~~~~~~~~~~~~~~~  7eefe432		fcmgt d18, d1, d15
+0x~~~~~~~~~~~~~~~~  5ee0cbe3		fcmgt d3, d31, #0.0
+0x~~~~~~~~~~~~~~~~  7ea2e72b		fcmgt s11, s25, s2
+0x~~~~~~~~~~~~~~~~  5ea0ca11		fcmgt s17, s16, #0.0
+0x~~~~~~~~~~~~~~~~  7ee0da38		fcmle d24, d17, #0.0
+0x~~~~~~~~~~~~~~~~  7ea0d90b		fcmle s11, s8, #0.0
+0x~~~~~~~~~~~~~~~~  5ee0ebe5		fcmlt d5, d31, #0.0
+0x~~~~~~~~~~~~~~~~  5ea0eaf2		fcmlt s18, s23, #0.0
+0x~~~~~~~~~~~~~~~~  1e782140		fcmp d10, d24
+0x~~~~~~~~~~~~~~~~  1e6021a8		fcmp d13, #0.0
+0x~~~~~~~~~~~~~~~~  1e262240		fcmp s18, s6
+0x~~~~~~~~~~~~~~~~  1e202208		fcmp s16, #0.0
+0x~~~~~~~~~~~~~~~~  1e712130		fcmpe d9, d17
+0x~~~~~~~~~~~~~~~~  1e6023b8		fcmpe d29, #0.0
+0x~~~~~~~~~~~~~~~~  1e312210		fcmpe s16, s17
+0x~~~~~~~~~~~~~~~~  1e2022d8		fcmpe s22, #0.0
+0x~~~~~~~~~~~~~~~~  1e73cdca		fcsel d10, d14, d19, gt
+0x~~~~~~~~~~~~~~~~  1e22ae56		fcsel s22, s18, s2, ge
+0x~~~~~~~~~~~~~~~~  1ee2c304		fcvt d4, h24
+0x~~~~~~~~~~~~~~~~  1e22c04b		fcvt d11, s2
+0x~~~~~~~~~~~~~~~~  1e63c128		fcvt h8, d9
+0x~~~~~~~~~~~~~~~~  1e23c02c		fcvt h12, s1
+0x~~~~~~~~~~~~~~~~  1e6243ec		fcvt s12, d31
+0x~~~~~~~~~~~~~~~~  1ee2433b		fcvt s27, h25
+0x~~~~~~~~~~~~~~~~  5e61ca1c		fcvtas d28, d16
+0x~~~~~~~~~~~~~~~~  5e21c8a3		fcvtas s3, s5
+0x~~~~~~~~~~~~~~~~  1e6403f2		fcvtas w18, d31
+0x~~~~~~~~~~~~~~~~  1e24031d		fcvtas w29, s24
+0x~~~~~~~~~~~~~~~~  9e640029		fcvtas x9, d1
+0x~~~~~~~~~~~~~~~~  9e24005e		fcvtas x30, s2
+0x~~~~~~~~~~~~~~~~  7e61c80e		fcvtau d14, d0
+0x~~~~~~~~~~~~~~~~  7e21c9df		fcvtau s31, s14
+0x~~~~~~~~~~~~~~~~  1e650050		fcvtau w16, d2
+0x~~~~~~~~~~~~~~~~  1e250012		fcvtau w18, s0
+0x~~~~~~~~~~~~~~~~  9e6500fa		fcvtau x26, d7
+0x~~~~~~~~~~~~~~~~  9e250279		fcvtau x25, s19
+0x~~~~~~~~~~~~~~~~  5e61bb3e		fcvtms d30, d25
+0x~~~~~~~~~~~~~~~~  5e21b9ec		fcvtms s12, s15
+0x~~~~~~~~~~~~~~~~  1e7000e9		fcvtms w9, d7
+0x~~~~~~~~~~~~~~~~  1e3000d3		fcvtms w19, s6
+0x~~~~~~~~~~~~~~~~  9e7000c6		fcvtms x6, d6
+0x~~~~~~~~~~~~~~~~  9e3000f6		fcvtms x22, s7
+0x~~~~~~~~~~~~~~~~  7e61b81b		fcvtmu d27, d0
+0x~~~~~~~~~~~~~~~~  7e21bac8		fcvtmu s8, s22
+0x~~~~~~~~~~~~~~~~  1e71027d		fcvtmu w29, d19
+0x~~~~~~~~~~~~~~~~  1e31001a		fcvtmu w26, s0
+0x~~~~~~~~~~~~~~~~  9e7100ad		fcvtmu x13, d5
+0x~~~~~~~~~~~~~~~~  9e310245		fcvtmu x5, s18
+0x~~~~~~~~~~~~~~~~  5e61a9fe		fcvtns d30, d15
+0x~~~~~~~~~~~~~~~~  5e21a96a		fcvtns s10, s11
+0x~~~~~~~~~~~~~~~~  1e6001f5		fcvtns w21, d15
+0x~~~~~~~~~~~~~~~~  1e200152		fcvtns w18, s10
+0x~~~~~~~~~~~~~~~~  9e600228		fcvtns x8, d17
+0x~~~~~~~~~~~~~~~~  9e200191		fcvtns x17, s12
+0x~~~~~~~~~~~~~~~~  7e61aaa0		fcvtnu d0, d21
+0x~~~~~~~~~~~~~~~~  7e21ab26		fcvtnu s6, s25
+0x~~~~~~~~~~~~~~~~  1e61017d		fcvtnu w29, d11
+0x~~~~~~~~~~~~~~~~  1e2103f9		fcvtnu w25, s31
+0x~~~~~~~~~~~~~~~~  9e61017e		fcvtnu x30, d11
+0x~~~~~~~~~~~~~~~~  9e21025b		fcvtnu x27, s18
+0x~~~~~~~~~~~~~~~~  5ee1aacb		fcvtps d11, d22
+0x~~~~~~~~~~~~~~~~  5ea1aa9d		fcvtps s29, s20
+0x~~~~~~~~~~~~~~~~  1e68032f		fcvtps w15, d25
+0x~~~~~~~~~~~~~~~~  1e2800f0		fcvtps w16, s7
+0x~~~~~~~~~~~~~~~~  9e68028d		fcvtps x13, d20
+0x~~~~~~~~~~~~~~~~  9e2802e3		fcvtps x3, s23
+0x~~~~~~~~~~~~~~~~  7ee1a838		fcvtpu d24, d1
+0x~~~~~~~~~~~~~~~~  7ea1ab0e		fcvtpu s14, s24
+0x~~~~~~~~~~~~~~~~  1e6903ba		fcvtpu w26, d29
+0x~~~~~~~~~~~~~~~~  1e29035f		fcvtpu wzr, s26
+0x~~~~~~~~~~~~~~~~  9e6900db		fcvtpu x27, d6
+0x~~~~~~~~~~~~~~~~  9e2901dd		fcvtpu x29, s14
+0x~~~~~~~~~~~~~~~~  7e61698c		fcvtxn s12, d12
+0x~~~~~~~~~~~~~~~~  5ee1b80f		fcvtzs d15, d0
+0x~~~~~~~~~~~~~~~~  5f56fc8d		fcvtzs d13, d4, #42
+0x~~~~~~~~~~~~~~~~  5ea1b968		fcvtzs s8, s11
+0x~~~~~~~~~~~~~~~~  5f27fcdf		fcvtzs s31, s6, #25
+0x~~~~~~~~~~~~~~~~  1e780126		fcvtzs w6, d9
+0x~~~~~~~~~~~~~~~~  1e58b159		fcvtzs w25, d10, #20
+0x~~~~~~~~~~~~~~~~  1e380029		fcvtzs w9, s1
+0x~~~~~~~~~~~~~~~~  1e188bb1		fcvtzs w17, s29, #30
+0x~~~~~~~~~~~~~~~~  9e780053		fcvtzs x19, d2
+0x~~~~~~~~~~~~~~~~  9e58fdd6		fcvtzs x22, d14, #1
+0x~~~~~~~~~~~~~~~~  9e38028e		fcvtzs x14, s20
+0x~~~~~~~~~~~~~~~~  9e187fc3		fcvtzs x3, s30, #33
+0x~~~~~~~~~~~~~~~~  7ee1b9fc		fcvtzu d28, d15
+0x~~~~~~~~~~~~~~~~  7f7dfc80		fcvtzu d0, d4, #3
+0x~~~~~~~~~~~~~~~~  7ea1b8a2		fcvtzu s2, s5
+0x~~~~~~~~~~~~~~~~  7f22fc04		fcvtzu s4, s0, #30
+0x~~~~~~~~~~~~~~~~  1e79008b		fcvtzu w11, d4
+0x~~~~~~~~~~~~~~~~  1e598307		fcvtzu w7, d24, #32
+0x~~~~~~~~~~~~~~~~  1e390312		fcvtzu w18, s24
+0x~~~~~~~~~~~~~~~~  1e19f36e		fcvtzu w14, s27, #4
+0x~~~~~~~~~~~~~~~~  9e790176		fcvtzu x22, d11
+0x~~~~~~~~~~~~~~~~  9e593368		fcvtzu x8, d27, #52
+0x~~~~~~~~~~~~~~~~  9e390287		fcvtzu x7, s20
+0x~~~~~~~~~~~~~~~~  9e1950f6		fcvtzu x22, s7, #44
+0x~~~~~~~~~~~~~~~~  1e6f19c6		fdiv d6, d14, d15
+0x~~~~~~~~~~~~~~~~  1e3918ba		fdiv s26, s5, s25
+0x~~~~~~~~~~~~~~~~  1f4c7b52		fmadd d18, d26, d12, d30
+0x~~~~~~~~~~~~~~~~  1f1c112d		fmadd s13, s9, s28, s4
+0x~~~~~~~~~~~~~~~~  1e6548ac		fmax d12, d5, d5
+0x~~~~~~~~~~~~~~~~  1e264b8c		fmax s12, s28, s6
+0x~~~~~~~~~~~~~~~~  1e62689c		fmaxnm d28, d4, d2
+0x~~~~~~~~~~~~~~~~  1e286946		fmaxnm s6, s10, s8
+0x~~~~~~~~~~~~~~~~  1e725a94		fmin d20, d20, d18
+0x~~~~~~~~~~~~~~~~  1e3059a7		fmin s7, s13, s16
+0x~~~~~~~~~~~~~~~~  1e7e79d3		fminnm d19, d14, d30
+0x~~~~~~~~~~~~~~~~  1e217820		fminnm s0, s1, s1
+0x~~~~~~~~~~~~~~~~  1e6040cd		fmov d13, d6
+0x~~~~~~~~~~~~~~~~  9e670222		fmov d2, x17
+0x~~~~~~~~~~~~~~~~  1e709008		fmov d8, #0x84 (-2.5000)
+0x~~~~~~~~~~~~~~~~  1e204065		fmov s5, s3
+0x~~~~~~~~~~~~~~~~  1e270299		fmov s25, w20
+0x~~~~~~~~~~~~~~~~  1e20f015		fmov s21, #0x7 (2.8750)
+0x~~~~~~~~~~~~~~~~  1e260312		fmov w18, s24
+0x~~~~~~~~~~~~~~~~  9e660052		fmov x18, d2
+0x~~~~~~~~~~~~~~~~  1f43cfd4		fmsub d20, d30, d3, d19
+0x~~~~~~~~~~~~~~~~  1f04b265		fmsub s5, s19, s4, s12
+0x~~~~~~~~~~~~~~~~  1e770b7e		fmul d30, d27, d23
+0x~~~~~~~~~~~~~~~~  1e2f0a39		fmul s25, s17, s15
+0x~~~~~~~~~~~~~~~~  5e61de24		fmulx d4, d17, d1
+0x~~~~~~~~~~~~~~~~  5e24df2e		fmulx s14, s25, s4
+0x~~~~~~~~~~~~~~~~  1e61400f		fneg d15, d0
+0x~~~~~~~~~~~~~~~~  1e2141ee		fneg s14, s15
+0x~~~~~~~~~~~~~~~~  1f767e00		fnmadd d0, d16, d22, d31
+0x~~~~~~~~~~~~~~~~  1f3a4a40		fnmadd s0, s18, s26, s18
+0x~~~~~~~~~~~~~~~~  1f6fd593		fnmsub d19, d12, d15, d21
+0x~~~~~~~~~~~~~~~~  1f2be81d		fnmsub s29, s0, s11, s26
+0x~~~~~~~~~~~~~~~~  1e618a7f		fnmul d31, d19, d1
+0x~~~~~~~~~~~~~~~~  1e318872		fnmul s18, s3, s17
+0x~~~~~~~~~~~~~~~~  5ee1daa7		frecpe d7, d21
+0x~~~~~~~~~~~~~~~~  5ea1da3d		frecpe s29, s17
+0x~~~~~~~~~~~~~~~~  5e71ff4b		frecps d11, d26, d17
+0x~~~~~~~~~~~~~~~~  5e21ff72		frecps s18, s27, s1
+0x~~~~~~~~~~~~~~~~  5ee1fa4f		frecpx d15, d18
+0x~~~~~~~~~~~~~~~~  5ea1f945		frecpx s5, s10
+0x~~~~~~~~~~~~~~~~  1e6643d0		frinta d16, d30
+0x~~~~~~~~~~~~~~~~  1e2642c1		frinta s1, s22
+0x~~~~~~~~~~~~~~~~  1e67c3b3		frinti d19, d29
+0x~~~~~~~~~~~~~~~~  1e27c2ae		frinti s14, s21
+0x~~~~~~~~~~~~~~~~  1e6543d4		frintm d20, d30
+0x~~~~~~~~~~~~~~~~  1e254201		frintm s1, s16
+0x~~~~~~~~~~~~~~~~  1e64403e		frintn d30, d1
+0x~~~~~~~~~~~~~~~~  1e244158		frintn s24, s10
+0x~~~~~~~~~~~~~~~~  1e64c284		frintp d4, d20
+0x~~~~~~~~~~~~~~~~  1e24c06d		frintp s13, s3
+0x~~~~~~~~~~~~~~~~  1e67428d		frintx d13, d20
+0x~~~~~~~~~~~~~~~~  1e2740f1		frintx s17, s7
+0x~~~~~~~~~~~~~~~~  1e65c100		frintz d0, d8
+0x~~~~~~~~~~~~~~~~  1e25c3af		frintz s15, s29
+0x~~~~~~~~~~~~~~~~  7ee1d955		frsqrte d21, d10
+0x~~~~~~~~~~~~~~~~  7ea1db31		frsqrte s17, s25
+0x~~~~~~~~~~~~~~~~  5ef1ffa4		frsqrts d4, d29, d17
+0x~~~~~~~~~~~~~~~~  5eb8fc6e		frsqrts s14, s3, s24
+0x~~~~~~~~~~~~~~~~  1e61c22e		fsqrt d14, d17
+0x~~~~~~~~~~~~~~~~  1e21c1c4		fsqrt s4, s14
+0x~~~~~~~~~~~~~~~~  1e673a6d		fsub d13, d19, d7
+0x~~~~~~~~~~~~~~~~  1e3b3aa3		fsub s3, s21, s27
+0x~~~~~~~~~~~~~~~~  5e61da1f		scvtf d31, d16
+0x~~~~~~~~~~~~~~~~  5f68e7fa		scvtf d26, d31, #24
+0x~~~~~~~~~~~~~~~~  1e620206		scvtf d6, w16
+0x~~~~~~~~~~~~~~~~  1e42ea85		scvtf d5, w20, #6
+0x~~~~~~~~~~~~~~~~  9e620110		scvtf d16, x8
+0x~~~~~~~~~~~~~~~~  9e42d90f		scvtf d15, x8, #10
+0x~~~~~~~~~~~~~~~~  5e21d887		scvtf s7, s4
+0x~~~~~~~~~~~~~~~~  5f32e5e8		scvtf s8, s15, #14
+0x~~~~~~~~~~~~~~~~  1e22015d		scvtf s29, w10
+0x~~~~~~~~~~~~~~~~  1e02d6af		scvtf s15, w21, #11
+0x~~~~~~~~~~~~~~~~  9e22035b		scvtf s27, x26
+0x~~~~~~~~~~~~~~~~  9e02699a		scvtf s26, x12, #38
+0x~~~~~~~~~~~~~~~~  7e61d920		ucvtf d0, d9
+0x~~~~~~~~~~~~~~~~  7f51e6c5		ucvtf d5, d22, #47
+0x~~~~~~~~~~~~~~~~  1e63037e		ucvtf d30, w27
+0x~~~~~~~~~~~~~~~~  1e43fe63		ucvtf d3, w19, #1
+0x~~~~~~~~~~~~~~~~  9e6302bc		ucvtf d28, x21
+0x~~~~~~~~~~~~~~~~  9e4377db		ucvtf d27, x30, #35
+0x~~~~~~~~~~~~~~~~  7e21d8ab		ucvtf s11, s5
+0x~~~~~~~~~~~~~~~~  7f32e6e0		ucvtf s0, s23, #14
+0x~~~~~~~~~~~~~~~~  1e230274		ucvtf s20, w19
+0x~~~~~~~~~~~~~~~~  1e03bad5		ucvtf s21, w22, #18
+0x~~~~~~~~~~~~~~~~  9e2301a6		ucvtf s6, x13
+0x~~~~~~~~~~~~~~~~  9e03ac47		ucvtf s7, x2, #21
+0x~~~~~~~~~~~~~~~~  5ee0b813		abs d19, d0
+0x~~~~~~~~~~~~~~~~  4e20b970		abs v16.16b, v11.16b
+0x~~~~~~~~~~~~~~~~  4ee0bbe0		abs v0.2d, v31.2d
+0x~~~~~~~~~~~~~~~~  0ea0bb3b		abs v27.2s, v25.2s
+0x~~~~~~~~~~~~~~~~  0e60bb75		abs v21.4h, v27.4h
+0x~~~~~~~~~~~~~~~~  4ea0b830		abs v16.4s, v1.4s
+0x~~~~~~~~~~~~~~~~  0e20b8bf		abs v31.8b, v5.8b
+0x~~~~~~~~~~~~~~~~  4e60b9bd		abs v29.8h, v13.8h
+0x~~~~~~~~~~~~~~~~  5ef184aa		add d10, d5, d17
+0x~~~~~~~~~~~~~~~~  4e3785ff		add v31.16b, v15.16b, v23.16b
+0x~~~~~~~~~~~~~~~~  4eee87ea		add v10.2d, v31.2d, v14.2d
+0x~~~~~~~~~~~~~~~~  0eb385cf		add v15.2s, v14.2s, v19.2s
+0x~~~~~~~~~~~~~~~~  0e7186fb		add v27.4h, v23.4h, v17.4h
+0x~~~~~~~~~~~~~~~~  4ebd8799		add v25.4s, v28.4s, v29.4s
+0x~~~~~~~~~~~~~~~~  0e3284ed		add v13.8b, v7.8b, v18.8b
+0x~~~~~~~~~~~~~~~~  4e618444		add v4.8h, v2.8h, v1.8h
+0x~~~~~~~~~~~~~~~~  0eaf41ca		addhn v10.2s, v14.2d, v15.2d
+0x~~~~~~~~~~~~~~~~  0e7a43ca		addhn v10.4h, v30.4s, v26.4s
+0x~~~~~~~~~~~~~~~~  0e36419f		addhn v31.8b, v12.8h, v22.8h
+0x~~~~~~~~~~~~~~~~  4e3442b0		addhn2 v16.16b, v21.8h, v20.8h
+0x~~~~~~~~~~~~~~~~  4eb14040		addhn2 v0.4s, v2.2d, v17.2d
+0x~~~~~~~~~~~~~~~~  4e7140ff		addhn2 v31.8h, v7.4s, v17.4s
+0x~~~~~~~~~~~~~~~~  5ef1ba6e		addp d14, v19.2d
+0x~~~~~~~~~~~~~~~~  4e3cbd03		addp v3.16b, v8.16b, v28.16b
+0x~~~~~~~~~~~~~~~~  4ef1bca8		addp v8.2d, v5.2d, v17.2d
+0x~~~~~~~~~~~~~~~~  0ebabfd6		addp v22.2s, v30.2s, v26.2s
+0x~~~~~~~~~~~~~~~~  0e6ebf1d		addp v29.4h, v24.4h, v14.4h
+0x~~~~~~~~~~~~~~~~  4eb8bf5e		addp v30.4s, v26.4s, v24.4s
+0x~~~~~~~~~~~~~~~~  0e27bf4c		addp v12.8b, v26.8b, v7.8b
+0x~~~~~~~~~~~~~~~~  4e6cbd11		addp v17.8h, v8.8h, v12.8h
+0x~~~~~~~~~~~~~~~~  4e31bafb		addv b27, v23.16b
+0x~~~~~~~~~~~~~~~~  0e31ba8c		addv b12, v20.8b
+0x~~~~~~~~~~~~~~~~  0e71bbdb		addv h27, v30.4h
+0x~~~~~~~~~~~~~~~~  4e71b9d3		addv h19, v14.8h
+0x~~~~~~~~~~~~~~~~  4eb1bb6e		addv s14, v27.4s
+0x~~~~~~~~~~~~~~~~  4e3b1d0a		and v10.16b, v8.16b, v27.16b
+0x~~~~~~~~~~~~~~~~  0e301c25		and v5.8b, v1.8b, v16.8b
+0x~~~~~~~~~~~~~~~~  4e781c7a		bic v26.16b, v3.16b, v24.16b
+0x~~~~~~~~~~~~~~~~  2f075487		bic v7.2s, #0xe4, lsl #16
+0x~~~~~~~~~~~~~~~~  2f01b47c		bic v28.4h, #0x23, lsl #8
+0x~~~~~~~~~~~~~~~~  6f05159d		bic v29.4s, #0xac, lsl #0
+0x~~~~~~~~~~~~~~~~  0e751fec		bic v12.8b, v31.8b, v21.8b
+0x~~~~~~~~~~~~~~~~  6f049712		bic v18.8h, #0x98, lsl #0
+0x~~~~~~~~~~~~~~~~  6ee81f4c		bif v12.16b, v26.16b, v8.16b
+0x~~~~~~~~~~~~~~~~  2efb1ee2		bif v2.8b, v23.8b, v27.8b
+0x~~~~~~~~~~~~~~~~  6ead1c68		bit v8.16b, v3.16b, v13.16b
+0x~~~~~~~~~~~~~~~~  2eb71ca5		bit v5.8b, v5.8b, v23.8b
+0x~~~~~~~~~~~~~~~~  6e771fe9		bsl v9.16b, v31.16b, v23.16b
+0x~~~~~~~~~~~~~~~~  2e631cee		bsl v14.8b, v7.8b, v3.8b
+0x~~~~~~~~~~~~~~~~  4e2048bd		cls v29.16b, v5.16b
+0x~~~~~~~~~~~~~~~~  0ea04815		cls v21.2s, v0.2s
+0x~~~~~~~~~~~~~~~~  0e604981		cls v1.4h, v12.4h
+0x~~~~~~~~~~~~~~~~  4ea0495b		cls v27.4s, v10.4s
+0x~~~~~~~~~~~~~~~~  0e204893		cls v19.8b, v4.8b
+0x~~~~~~~~~~~~~~~~  4e6049cf		cls v15.8h, v14.8h
+0x~~~~~~~~~~~~~~~~  6e204881		clz v1.16b, v4.16b
+0x~~~~~~~~~~~~~~~~  2ea04a3b		clz v27.2s, v17.2s
+0x~~~~~~~~~~~~~~~~  2e604929		clz v9.4h, v9.4h
+0x~~~~~~~~~~~~~~~~  6ea049ff		clz v31.4s, v15.4s
+0x~~~~~~~~~~~~~~~~  2e204a6e		clz v14.8b, v19.8b
+0x~~~~~~~~~~~~~~~~  6e604966		clz v6.8h, v11.8h
+0x~~~~~~~~~~~~~~~~  7efd8cb2		cmeq d18, d5, d29
+0x~~~~~~~~~~~~~~~~  5ee09bee		cmeq d14, d31, #0
+0x~~~~~~~~~~~~~~~~  6e368c73		cmeq v19.16b, v3.16b, v22.16b
+0x~~~~~~~~~~~~~~~~  4e20992f		cmeq v15.16b, v9.16b, #0
+0x~~~~~~~~~~~~~~~~  6eea8e0c		cmeq v12.2d, v16.2d, v10.2d
+0x~~~~~~~~~~~~~~~~  4ee09ac8		cmeq v8.2d, v22.2d, #0
+0x~~~~~~~~~~~~~~~~  2ea98c62		cmeq v2.2s, v3.2s, v9.2s
+0x~~~~~~~~~~~~~~~~  0ea09b30		cmeq v16.2s, v25.2s, #0
+0x~~~~~~~~~~~~~~~~  2e748ee6		cmeq v6.4h, v23.4h, v20.4h
+0x~~~~~~~~~~~~~~~~  0e6099b0		cmeq v16.4h, v13.4h, #0
+0x~~~~~~~~~~~~~~~~  6ea28e35		cmeq v21.4s, v17.4s, v2.4s
+0x~~~~~~~~~~~~~~~~  4ea09b26		cmeq v6.4s, v25.4s, #0
+0x~~~~~~~~~~~~~~~~  2e228db0		cmeq v16.8b, v13.8b, v2.8b
+0x~~~~~~~~~~~~~~~~  0e209a15		cmeq v21.8b, v16.8b, #0
+0x~~~~~~~~~~~~~~~~  6e798cf4		cmeq v20.8h, v7.8h, v25.8h
+0x~~~~~~~~~~~~~~~~  4e60991a		cmeq v26.8h, v8.8h, #0
+0x~~~~~~~~~~~~~~~~  5eff3db0		cmge d16, d13, d31
+0x~~~~~~~~~~~~~~~~  7ee08b19		cmge d25, d24, #0
+0x~~~~~~~~~~~~~~~~  4e313e71		cmge v17.16b, v19.16b, v17.16b
+0x~~~~~~~~~~~~~~~~  6e208bd6		cmge v22.16b, v30.16b, #0
+0x~~~~~~~~~~~~~~~~  4efa3e9c		cmge v28.2d, v20.2d, v26.2d
+0x~~~~~~~~~~~~~~~~  6ee08ae6		cmge v6.2d, v23.2d, #0
+0x~~~~~~~~~~~~~~~~  0ea33ed9		cmge v25.2s, v22.2s, v3.2s
+0x~~~~~~~~~~~~~~~~  2ea08975		cmge v21.2s, v11.2s, #0
+0x~~~~~~~~~~~~~~~~  0e6c3c70		cmge v16.4h, v3.4h, v12.4h
+0x~~~~~~~~~~~~~~~~  2e608937		cmge v23.4h, v9.4h, #0
+0x~~~~~~~~~~~~~~~~  4eab3c47		cmge v7.4s, v2.4s, v11.4s
+0x~~~~~~~~~~~~~~~~  6ea08ac0		cmge v0.4s, v22.4s, #0
+0x~~~~~~~~~~~~~~~~  0e293fca		cmge v10.8b, v30.8b, v9.8b
+0x~~~~~~~~~~~~~~~~  2e208915		cmge v21.8b, v8.8b, #0
+0x~~~~~~~~~~~~~~~~  4e7a3ce2		cmge v2.8h, v7.8h, v26.8h
+0x~~~~~~~~~~~~~~~~  6e608953		cmge v19.8h, v10.8h, #0
+0x~~~~~~~~~~~~~~~~  5ee135a6		cmgt d6, d13, d1
+0x~~~~~~~~~~~~~~~~  5ee08b1e		cmgt d30, d24, #0
+0x~~~~~~~~~~~~~~~~  4e3b3734		cmgt v20.16b, v25.16b, v27.16b
+0x~~~~~~~~~~~~~~~~  4e208b20		cmgt v0.16b, v25.16b, #0
+0x~~~~~~~~~~~~~~~~  4ee13736		cmgt v22.2d, v25.2d, v1.2d
+0x~~~~~~~~~~~~~~~~  4ee08a10		cmgt v16.2d, v16.2d, #0
+0x~~~~~~~~~~~~~~~~  0eaf3525		cmgt v5.2s, v9.2s, v15.2s
+0x~~~~~~~~~~~~~~~~  0ea08a4c		cmgt v12.2s, v18.2s, #0
+0x~~~~~~~~~~~~~~~~  0e6b365c		cmgt v28.4h, v18.4h, v11.4h
+0x~~~~~~~~~~~~~~~~  0e608876		cmgt v22.4h, v3.4h, #0
+0x~~~~~~~~~~~~~~~~  4ebb3565		cmgt v5.4s, v11.4s, v27.4s
+0x~~~~~~~~~~~~~~~~  4ea08a8d		cmgt v13.4s, v20.4s, #0
+0x~~~~~~~~~~~~~~~~  0e2737fb		cmgt v27.8b, v31.8b, v7.8b
+0x~~~~~~~~~~~~~~~~  0e208805		cmgt v5.8b, v0.8b, #0
+0x~~~~~~~~~~~~~~~~  4e6d3796		cmgt v22.8h, v28.8h, v13.8h
+0x~~~~~~~~~~~~~~~~  4e608846		cmgt v6.8h, v2.8h, #0
+0x~~~~~~~~~~~~~~~~  7ef63515		cmhi d21, d8, d22
+0x~~~~~~~~~~~~~~~~  6e333672		cmhi v18.16b, v19.16b, v19.16b
+0x~~~~~~~~~~~~~~~~  6ef53407		cmhi v7.2d, v0.2d, v21.2d
+0x~~~~~~~~~~~~~~~~  2ea0366f		cmhi v15.2s, v19.2s, v0.2s
+0x~~~~~~~~~~~~~~~~  2e6c34ff		cmhi v31.4h, v7.4h, v12.4h
+0x~~~~~~~~~~~~~~~~  6eb63609		cmhi v9.4s, v16.4s, v22.4s
+0x~~~~~~~~~~~~~~~~  2e3c3707		cmhi v7.8b, v24.8b, v28.8b
+0x~~~~~~~~~~~~~~~~  6e79354b		cmhi v11.8h, v10.8h, v25.8h
+0x~~~~~~~~~~~~~~~~  7ef13d81		cmhs d1, d12, d17
+0x~~~~~~~~~~~~~~~~  6e3e3f35		cmhs v21.16b, v25.16b, v30.16b
+0x~~~~~~~~~~~~~~~~  6efa3c48		cmhs v8.2d, v2.2d, v26.2d
+0x~~~~~~~~~~~~~~~~  2ebd3ec1		cmhs v1.2s, v22.2s, v29.2s
+0x~~~~~~~~~~~~~~~~  2e7e3fda		cmhs v26.4h, v30.4h, v30.4h
+0x~~~~~~~~~~~~~~~~  6eb03e93		cmhs v19.4s, v20.4s, v16.4s
+0x~~~~~~~~~~~~~~~~  2e3a3c61		cmhs v1.8b, v3.8b, v26.8b
+0x~~~~~~~~~~~~~~~~  6e683f94		cmhs v20.8h, v28.8h, v8.8h
+0x~~~~~~~~~~~~~~~~  7ee09b1e		cmle d30, d24, #0
+0x~~~~~~~~~~~~~~~~  6e209860		cmle v0.16b, v3.16b, #0
+0x~~~~~~~~~~~~~~~~  6ee09bc2		cmle v2.2d, v30.2d, #0
+0x~~~~~~~~~~~~~~~~  2ea09947		cmle v7.2s, v10.2s, #0
+0x~~~~~~~~~~~~~~~~  2e609be9		cmle v9.4h, v31.4h, #0
+0x~~~~~~~~~~~~~~~~  6ea09a49		cmle v9.4s, v18.4s, #0
+0x~~~~~~~~~~~~~~~~  2e209bf5		cmle v21.8b, v31.8b, #0
+0x~~~~~~~~~~~~~~~~  6e609abd		cmle v29.8h, v21.8h, #0
+0x~~~~~~~~~~~~~~~~  5ee0aaf9		cmlt d25, d23, #0
+0x~~~~~~~~~~~~~~~~  4e20aaa7		cmlt v7.16b, v21.16b, #0
+0x~~~~~~~~~~~~~~~~  4ee0abc7		cmlt v7.2d, v30.2d, #0
+0x~~~~~~~~~~~~~~~~  0ea0ab99		cmlt v25.2s, v28.2s, #0
+0x~~~~~~~~~~~~~~~~  0e60a960		cmlt v0.4h, v11.4h, #0
+0x~~~~~~~~~~~~~~~~  4ea0a8b8		cmlt v24.4s, v5.4s, #0
+0x~~~~~~~~~~~~~~~~  0e20a97a		cmlt v26.8b, v11.8b, #0
+0x~~~~~~~~~~~~~~~~  4e60aaa1		cmlt v1.8h, v21.8h, #0
+0x~~~~~~~~~~~~~~~~  5efe8efc		cmtst d28, d23, d30
+0x~~~~~~~~~~~~~~~~  4e3f8cda		cmtst v26.16b, v6.16b, v31.16b
+0x~~~~~~~~~~~~~~~~  4ee48ea1		cmtst v1.2d, v21.2d, v4.2d
+0x~~~~~~~~~~~~~~~~  0eb48f5b		cmtst v27.2s, v26.2s, v20.2s
+0x~~~~~~~~~~~~~~~~  0e728c1a		cmtst v26.4h, v0.4h, v18.4h
+0x~~~~~~~~~~~~~~~~  4ea48e19		cmtst v25.4s, v16.4s, v4.4s
+0x~~~~~~~~~~~~~~~~  0e298d4b		cmtst v11.8b, v10.8b, v9.8b
+0x~~~~~~~~~~~~~~~~  4e618c40		cmtst v0.8h, v2.8h, v1.8h
+0x~~~~~~~~~~~~~~~~  4e2059f9		cnt v25.16b, v15.16b
+0x~~~~~~~~~~~~~~~~  0e2058dc		cnt v28.8b, v6.8b
+0x~~~~~~~~~~~~~~~~  4e0f04e6		dup v6.16b, v7.b[7]
+0x~~~~~~~~~~~~~~~~  4e010e89		dup v9.16b, w20
+0x~~~~~~~~~~~~~~~~  4e1805ac		dup v12.2d, v13.d[1]
+0x~~~~~~~~~~~~~~~~  4e080fe9		dup v9.2d, xzr
+0x~~~~~~~~~~~~~~~~  0e140744		dup v4.2s, v26.s[2]
+0x~~~~~~~~~~~~~~~~  0e040d83		dup v3.2s, w12
+0x~~~~~~~~~~~~~~~~  0e1e04b6		dup v22.4h, v5.h[7]
+0x~~~~~~~~~~~~~~~~  0e020f30		dup v16.4h, w25
+0x~~~~~~~~~~~~~~~~  4e140554		dup v20.4s, v10.s[2]
+0x~~~~~~~~~~~~~~~~  4e040cea		dup v10.4s, w7
+0x~~~~~~~~~~~~~~~~  0e0507de		dup v30.8b, v30.b[2]
+0x~~~~~~~~~~~~~~~~  0e010dff		dup v31.8b, w15
+0x~~~~~~~~~~~~~~~~  4e12063c		dup v28.8h, v17.h[4]
+0x~~~~~~~~~~~~~~~~  4e020c62		dup v2.8h, w3
+0x~~~~~~~~~~~~~~~~  6e231f3d		eor v29.16b, v25.16b, v3.16b
+0x~~~~~~~~~~~~~~~~  2e3c1e03		eor v3.8b, v16.8b, v28.8b
+0x~~~~~~~~~~~~~~~~  6e060b41		ext v1.16b, v26.16b, v6.16b, #1
+0x~~~~~~~~~~~~~~~~  2e010bc2		ext v2.8b, v30.8b, v1.8b, #1
+0x~~~~~~~~~~~~~~~~  4c402012		ld1 {v18.16b, v19.16b, v20.16b, v21.16b}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc22037		ld1 {v23.16b, v24.16b, v25.16b, v26.16b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf2025		ld1 {v5.16b, v6.16b, v7.16b, v8.16b}, [x1], #64
+0x~~~~~~~~~~~~~~~~  4c406012		ld1 {v18.16b, v19.16b, v20.16b}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc2602d		ld1 {v13.16b, v14.16b, v15.16b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf6033		ld1 {v19.16b, v20.16b, v21.16b}, [x1], #48
+0x~~~~~~~~~~~~~~~~  4c40a011		ld1 {v17.16b, v18.16b}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc2a034		ld1 {v20.16b, v21.16b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdfa03c		ld1 {v28.16b, v29.16b}, [x1], #32
+0x~~~~~~~~~~~~~~~~  4c40701d		ld1 {v29.16b}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc27035		ld1 {v21.16b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf7024		ld1 {v4.16b}, [x1], #16
+0x~~~~~~~~~~~~~~~~  0c402c04		ld1 {v4.1d, v5.1d, v6.1d, v7.1d}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc22c31		ld1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf2c3c		ld1 {v28.1d, v29.1d, v30.1d, v31.1d}, [x1], #32
+0x~~~~~~~~~~~~~~~~  0c406c14		ld1 {v20.1d, v21.1d, v22.1d}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc26c33		ld1 {v19.1d, v20.1d, v21.1d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf6c2c		ld1 {v12.1d, v13.1d, v14.1d}, [x1], #24
+0x~~~~~~~~~~~~~~~~  0c40ac1d		ld1 {v29.1d, v30.1d}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc2ac3f		ld1 {v31.1d, v0.1d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdfac23		ld1 {v3.1d, v4.1d}, [x1], #16
+0x~~~~~~~~~~~~~~~~  0c407c1c		ld1 {v28.1d}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc27c2b		ld1 {v11.1d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf7c3d		ld1 {v29.1d}, [x1], #8
+0x~~~~~~~~~~~~~~~~  4c402c1c		ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc22c28		ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf2c2e		ld1 {v14.2d, v15.2d, v16.2d, v17.2d}, [x1], #64
+0x~~~~~~~~~~~~~~~~  4c406c1a		ld1 {v26.2d, v27.2d, v28.2d}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc26c25		ld1 {v5.2d, v6.2d, v7.2d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf6c3a		ld1 {v26.2d, v27.2d, v28.2d}, [x1], #48
+0x~~~~~~~~~~~~~~~~  4c40ac12		ld1 {v18.2d, v19.2d}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc2ac35		ld1 {v21.2d, v22.2d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdfac31		ld1 {v17.2d, v18.2d}, [x1], #32
+0x~~~~~~~~~~~~~~~~  4c407c05		ld1 {v5.2d}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc27c26		ld1 {v6.2d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf7c2f		ld1 {v15.2d}, [x1], #16
+0x~~~~~~~~~~~~~~~~  0c40281e		ld1 {v30.2s, v31.2s, v0.2s, v1.2s}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc22838		ld1 {v24.2s, v25.2s, v26.2s, v27.2s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf283b		ld1 {v27.2s, v28.2s, v29.2s, v30.2s}, [x1], #32
+0x~~~~~~~~~~~~~~~~  0c40680b		ld1 {v11.2s, v12.2s, v13.2s}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc26828		ld1 {v8.2s, v9.2s, v10.2s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf683f		ld1 {v31.2s, v0.2s, v1.2s}, [x1], #24
+0x~~~~~~~~~~~~~~~~  0c40a800		ld1 {v0.2s, v1.2s}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc2a82d		ld1 {v13.2s, v14.2s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdfa823		ld1 {v3.2s, v4.2s}, [x1], #16
+0x~~~~~~~~~~~~~~~~  0c40781a		ld1 {v26.2s}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc27820		ld1 {v0.2s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf782b		ld1 {v11.2s}, [x1], #8
+0x~~~~~~~~~~~~~~~~  0c402410		ld1 {v16.4h, v17.4h, v18.4h, v19.4h}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc22438		ld1 {v24.4h, v25.4h, v26.4h, v27.4h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf2421		ld1 {v1.4h, v2.4h, v3.4h, v4.4h}, [x1], #32
+0x~~~~~~~~~~~~~~~~  0c40641e		ld1 {v30.4h, v31.4h, v0.4h}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc26439		ld1 {v25.4h, v26.4h, v27.4h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf6423		ld1 {v3.4h, v4.4h, v5.4h}, [x1], #24
+0x~~~~~~~~~~~~~~~~  0c40a403		ld1 {v3.4h, v4.4h}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc2a423		ld1 {v3.4h, v4.4h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdfa437		ld1 {v23.4h, v24.4h}, [x1], #16
+0x~~~~~~~~~~~~~~~~  0c40741a		ld1 {v26.4h}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc27421		ld1 {v1.4h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf742e		ld1 {v14.4h}, [x1], #8
+0x~~~~~~~~~~~~~~~~  4c40281a		ld1 {v26.4s, v27.4s, v28.4s, v29.4s}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc2283c		ld1 {v28.4s, v29.4s, v30.4s, v31.4s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf2824		ld1 {v4.4s, v5.4s, v6.4s, v7.4s}, [x1], #64
+0x~~~~~~~~~~~~~~~~  4c406802		ld1 {v2.4s, v3.4s, v4.4s}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc26836		ld1 {v22.4s, v23.4s, v24.4s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf682f		ld1 {v15.4s, v16.4s, v17.4s}, [x1], #48
+0x~~~~~~~~~~~~~~~~  4c40a814		ld1 {v20.4s, v21.4s}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc2a83e		ld1 {v30.4s, v31.4s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdfa82b		ld1 {v11.4s, v12.4s}, [x1], #32
+0x~~~~~~~~~~~~~~~~  4c40780f		ld1 {v15.4s}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc2782c		ld1 {v12.4s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf7820		ld1 {v0.4s}, [x1], #16
+0x~~~~~~~~~~~~~~~~  0c402011		ld1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc22025		ld1 {v5.8b, v6.8b, v7.8b, v8.8b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf2029		ld1 {v9.8b, v10.8b, v11.8b, v12.8b}, [x1], #32
+0x~~~~~~~~~~~~~~~~  0c406004		ld1 {v4.8b, v5.8b, v6.8b}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc26022		ld1 {v2.8b, v3.8b, v4.8b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf602c		ld1 {v12.8b, v13.8b, v14.8b}, [x1], #24
+0x~~~~~~~~~~~~~~~~  0c40a00a		ld1 {v10.8b, v11.8b}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc2a02b		ld1 {v11.8b, v12.8b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdfa03b		ld1 {v27.8b, v28.8b}, [x1], #16
+0x~~~~~~~~~~~~~~~~  0c40701f		ld1 {v31.8b}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc2702a		ld1 {v10.8b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf703c		ld1 {v28.8b}, [x1], #8
+0x~~~~~~~~~~~~~~~~  4c402405		ld1 {v5.8h, v6.8h, v7.8h, v8.8h}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc22422		ld1 {v2.8h, v3.8h, v4.8h, v5.8h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf242a		ld1 {v10.8h, v11.8h, v12.8h, v13.8h}, [x1], #64
+0x~~~~~~~~~~~~~~~~  4c40641a		ld1 {v26.8h, v27.8h, v28.8h}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc26423		ld1 {v3.8h, v4.8h, v5.8h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf6431		ld1 {v17.8h, v18.8h, v19.8h}, [x1], #48
+0x~~~~~~~~~~~~~~~~  4c40a404		ld1 {v4.8h, v5.8h}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc2a435		ld1 {v21.8h, v22.8h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdfa424		ld1 {v4.8h, v5.8h}, [x1], #32
+0x~~~~~~~~~~~~~~~~  4c407409		ld1 {v9.8h}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc2743b		ld1 {v27.8h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf743a		ld1 {v26.8h}, [x1], #16
+0x~~~~~~~~~~~~~~~~  0d400413		ld1 {v19.b}[1], [x0]
+0x~~~~~~~~~~~~~~~~  0dc20c2c		ld1 {v12.b}[3], [x1], x2
+0x~~~~~~~~~~~~~~~~  4ddf103b		ld1 {v27.b}[12], [x1], #1
+0x~~~~~~~~~~~~~~~~  4d40840a		ld1 {v10.d}[1], [x0]
+0x~~~~~~~~~~~~~~~~  4dc2843a		ld1 {v26.d}[1], [x1], x2
+0x~~~~~~~~~~~~~~~~  4ddf8427		ld1 {v7.d}[1], [x1], #8
+0x~~~~~~~~~~~~~~~~  4d404813		ld1 {v19.h}[5], [x0]
+0x~~~~~~~~~~~~~~~~  0dc2482a		ld1 {v10.h}[1], [x1], x2
+0x~~~~~~~~~~~~~~~~  4ddf4025		ld1 {v5.h}[4], [x1], #2
+0x~~~~~~~~~~~~~~~~  4d408015		ld1 {v21.s}[2], [x0]
+0x~~~~~~~~~~~~~~~~  4dc2802d		ld1 {v13.s}[2], [x1], x2
+0x~~~~~~~~~~~~~~~~  4ddf8021		ld1 {v1.s}[2], [x1], #4
+0x~~~~~~~~~~~~~~~~  4d40c002		ld1r {v2.16b}, [x0]
+0x~~~~~~~~~~~~~~~~  4dc2c022		ld1r {v2.16b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4ddfc036		ld1r {v22.16b}, [x1], #1
+0x~~~~~~~~~~~~~~~~  0d40cc19		ld1r {v25.1d}, [x0]
+0x~~~~~~~~~~~~~~~~  0dc2cc29		ld1r {v9.1d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0ddfcc37		ld1r {v23.1d}, [x1], #8
+0x~~~~~~~~~~~~~~~~  4d40cc13		ld1r {v19.2d}, [x0]
+0x~~~~~~~~~~~~~~~~  4dc2cc35		ld1r {v21.2d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4ddfcc3e		ld1r {v30.2d}, [x1], #8
+0x~~~~~~~~~~~~~~~~  0d40c818		ld1r {v24.2s}, [x0]
+0x~~~~~~~~~~~~~~~~  0dc2c83a		ld1r {v26.2s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0ddfc83c		ld1r {v28.2s}, [x1], #4
+0x~~~~~~~~~~~~~~~~  0d40c413		ld1r {v19.4h}, [x0]
+0x~~~~~~~~~~~~~~~~  0dc2c421		ld1r {v1.4h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0ddfc435		ld1r {v21.4h}, [x1], #2
+0x~~~~~~~~~~~~~~~~  4d40c80f		ld1r {v15.4s}, [x0]
+0x~~~~~~~~~~~~~~~~  4dc2c835		ld1r {v21.4s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4ddfc837		ld1r {v23.4s}, [x1], #4
+0x~~~~~~~~~~~~~~~~  0d40c01a		ld1r {v26.8b}, [x0]
+0x~~~~~~~~~~~~~~~~  0dc2c02e		ld1r {v14.8b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0ddfc033		ld1r {v19.8b}, [x1], #1
+0x~~~~~~~~~~~~~~~~  4d40c40d		ld1r {v13.8h}, [x0]
+0x~~~~~~~~~~~~~~~~  4dc2c43e		ld1r {v30.8h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4ddfc43b		ld1r {v27.8h}, [x1], #2
+0x~~~~~~~~~~~~~~~~  4c408015		ld2 {v21.16b, v22.16b}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc28035		ld2 {v21.16b, v22.16b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf802c		ld2 {v12.16b, v13.16b}, [x1], #32
+0x~~~~~~~~~~~~~~~~  4c408c0e		ld2 {v14.2d, v15.2d}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc28c20		ld2 {v0.2d, v1.2d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf8c2c		ld2 {v12.2d, v13.2d}, [x1], #32
+0x~~~~~~~~~~~~~~~~  0c40881b		ld2 {v27.2s, v28.2s}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc28822		ld2 {v2.2s, v3.2s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf882c		ld2 {v12.2s, v13.2s}, [x1], #16
+0x~~~~~~~~~~~~~~~~  0c408409		ld2 {v9.4h, v10.4h}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc28437		ld2 {v23.4h, v24.4h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf8421		ld2 {v1.4h, v2.4h}, [x1], #16
+0x~~~~~~~~~~~~~~~~  4c408814		ld2 {v20.4s, v21.4s}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc2882a		ld2 {v10.4s, v11.4s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf8838		ld2 {v24.4s, v25.4s}, [x1], #32
+0x~~~~~~~~~~~~~~~~  0c408011		ld2 {v17.8b, v18.8b}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc2802d		ld2 {v13.8b, v14.8b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf8027		ld2 {v7.8b, v8.8b}, [x1], #16
+0x~~~~~~~~~~~~~~~~  4c40841e		ld2 {v30.8h, v31.8h}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc28424		ld2 {v4.8h, v5.8h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf842d		ld2 {v13.8h, v14.8h}, [x1], #32
+0x~~~~~~~~~~~~~~~~  4d601005		ld2 {v5.b, v6.b}[12], [x0]
+0x~~~~~~~~~~~~~~~~  0de21c30		ld2 {v16.b, v17.b}[7], [x1], x2
+0x~~~~~~~~~~~~~~~~  0dff083d		ld2 {v29.b, v30.b}[2], [x1], #2
+0x~~~~~~~~~~~~~~~~  4d60840b		ld2 {v11.d, v12.d}[1], [x0]
+0x~~~~~~~~~~~~~~~~  0de2843a		ld2 {v26.d, v27.d}[0], [x1], x2
+0x~~~~~~~~~~~~~~~~  0dff8439		ld2 {v25.d, v26.d}[0], [x1], #16
+0x~~~~~~~~~~~~~~~~  4d605812		ld2 {v18.h, v19.h}[7], [x0]
+0x~~~~~~~~~~~~~~~~  4de24831		ld2 {v17.h, v18.h}[5], [x1], x2
+0x~~~~~~~~~~~~~~~~  0dff503e		ld2 {v30.h, v31.h}[2], [x1], #4
+0x~~~~~~~~~~~~~~~~  4d60901d		ld2 {v29.s, v30.s}[3], [x0]
+0x~~~~~~~~~~~~~~~~  0de2803c		ld2 {v28.s, v29.s}[0], [x1], x2
+0x~~~~~~~~~~~~~~~~  0dff9026		ld2 {v6.s, v7.s}[1], [x1], #8
+0x~~~~~~~~~~~~~~~~  4d60c01a		ld2r {v26.16b, v27.16b}, [x0]
+0x~~~~~~~~~~~~~~~~  4de2c035		ld2r {v21.16b, v22.16b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4dffc025		ld2r {v5.16b, v6.16b}, [x1], #2
+0x~~~~~~~~~~~~~~~~  0d60cc1a		ld2r {v26.1d, v27.1d}, [x0]
+0x~~~~~~~~~~~~~~~~  0de2cc2e		ld2r {v14.1d, v15.1d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0dffcc37		ld2r {v23.1d, v24.1d}, [x1], #16
+0x~~~~~~~~~~~~~~~~  4d60cc0b		ld2r {v11.2d, v12.2d}, [x0]
+0x~~~~~~~~~~~~~~~~  4de2cc3d		ld2r {v29.2d, v30.2d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4dffcc2f		ld2r {v15.2d, v16.2d}, [x1], #16
+0x~~~~~~~~~~~~~~~~  0d60c81a		ld2r {v26.2s, v27.2s}, [x0]
+0x~~~~~~~~~~~~~~~~  0de2c836		ld2r {v22.2s, v23.2s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0dffc822		ld2r {v2.2s, v3.2s}, [x1], #8
+0x~~~~~~~~~~~~~~~~  0d60c402		ld2r {v2.4h, v3.4h}, [x0]
+0x~~~~~~~~~~~~~~~~  0de2c429		ld2r {v9.4h, v10.4h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0dffc426		ld2r {v6.4h, v7.4h}, [x1], #4
+0x~~~~~~~~~~~~~~~~  4d60c807		ld2r {v7.4s, v8.4s}, [x0]
+0x~~~~~~~~~~~~~~~~  4de2c833		ld2r {v19.4s, v20.4s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4dffc835		ld2r {v21.4s, v22.4s}, [x1], #8
+0x~~~~~~~~~~~~~~~~  0d60c01a		ld2r {v26.8b, v27.8b}, [x0]
+0x~~~~~~~~~~~~~~~~  0de2c034		ld2r {v20.8b, v21.8b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0dffc02b		ld2r {v11.8b, v12.8b}, [x1], #2
+0x~~~~~~~~~~~~~~~~  4d60c40c		ld2r {v12.8h, v13.8h}, [x0]
+0x~~~~~~~~~~~~~~~~  4de2c426		ld2r {v6.8h, v7.8h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4dffc439		ld2r {v25.8h, v26.8h}, [x1], #4
+0x~~~~~~~~~~~~~~~~  4c404014		ld3 {v20.16b, v21.16b, v22.16b}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc2403c		ld3 {v28.16b, v29.16b, v30.16b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf4034		ld3 {v20.16b, v21.16b, v22.16b}, [x1], #48
+0x~~~~~~~~~~~~~~~~  4c404c15		ld3 {v21.2d, v22.2d, v23.2d}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc24c32		ld3 {v18.2d, v19.2d, v20.2d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf4c3b		ld3 {v27.2d, v28.2d, v29.2d}, [x1], #48
+0x~~~~~~~~~~~~~~~~  0c404807		ld3 {v7.2s, v8.2s, v9.2s}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc24834		ld3 {v20.2s, v21.2s, v22.2s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf483a		ld3 {v26.2s, v27.2s, v28.2s}, [x1], #24
+0x~~~~~~~~~~~~~~~~  0c40441b		ld3 {v27.4h, v28.4h, v29.4h}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc2443c		ld3 {v28.4h, v29.4h, v30.4h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf4427		ld3 {v7.4h, v8.4h, v9.4h}, [x1], #24
+0x~~~~~~~~~~~~~~~~  4c404802		ld3 {v2.4s, v3.4s, v4.4s}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc24838		ld3 {v24.4s, v25.4s, v26.4s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf482b		ld3 {v11.4s, v12.4s, v13.4s}, [x1], #48
+0x~~~~~~~~~~~~~~~~  0c40401d		ld3 {v29.8b, v30.8b, v31.8b}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc24021		ld3 {v1.8b, v2.8b, v3.8b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf402c		ld3 {v12.8b, v13.8b, v14.8b}, [x1], #24
+0x~~~~~~~~~~~~~~~~  4c404416		ld3 {v22.8h, v23.8h, v24.8h}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc2442d		ld3 {v13.8h, v14.8h, v15.8h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf443c		ld3 {v28.8h, v29.8h, v30.8h}, [x1], #48
+0x~~~~~~~~~~~~~~~~  4d402c15		ld3 {v21.b, v22.b, v23.b}[11], [x0]
+0x~~~~~~~~~~~~~~~~  4dc22425		ld3 {v5.b, v6.b, v7.b}[9], [x1], x2
+0x~~~~~~~~~~~~~~~~  0ddf2037		ld3 {v23.b, v24.b, v25.b}[0], [x1], #3
+0x~~~~~~~~~~~~~~~~  0d40a410		ld3 {v16.d, v17.d, v18.d}[0], [x0]
+0x~~~~~~~~~~~~~~~~  0dc2a43e		ld3 {v30.d, v31.d, v0.d}[0], [x1], x2
+0x~~~~~~~~~~~~~~~~  4ddfa43c		ld3 {v28.d, v29.d, v30.d}[1], [x1], #24
+0x~~~~~~~~~~~~~~~~  0d40700d		ld3 {v13.h, v14.h, v15.h}[2], [x0]
+0x~~~~~~~~~~~~~~~~  4dc27836		ld3 {v22.h, v23.h, v24.h}[7], [x1], x2
+0x~~~~~~~~~~~~~~~~  0ddf782e		ld3 {v14.h, v15.h, v16.h}[3], [x1], #6
+0x~~~~~~~~~~~~~~~~  4d40b016		ld3 {v22.s, v23.s, v24.s}[3], [x0]
+0x~~~~~~~~~~~~~~~~  4dc2a03e		ld3 {v30.s, v31.s, v0.s}[2], [x1], x2
+0x~~~~~~~~~~~~~~~~  0ddfb02c		ld3 {v12.s, v13.s, v14.s}[1], [x1], #12
+0x~~~~~~~~~~~~~~~~  4d40e018		ld3r {v24.16b, v25.16b, v26.16b}, [x0]
+0x~~~~~~~~~~~~~~~~  4dc2e038		ld3r {v24.16b, v25.16b, v26.16b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4ddfe023		ld3r {v3.16b, v4.16b, v5.16b}, [x1], #3
+0x~~~~~~~~~~~~~~~~  0d40ec04		ld3r {v4.1d, v5.1d, v6.1d}, [x0]
+0x~~~~~~~~~~~~~~~~  0dc2ec27		ld3r {v7.1d, v8.1d, v9.1d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0ddfec31		ld3r {v17.1d, v18.1d, v19.1d}, [x1], #24
+0x~~~~~~~~~~~~~~~~  4d40ec10		ld3r {v16.2d, v17.2d, v18.2d}, [x0]
+0x~~~~~~~~~~~~~~~~  4dc2ec34		ld3r {v20.2d, v21.2d, v22.2d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4ddfec2e		ld3r {v14.2d, v15.2d, v16.2d}, [x1], #24
+0x~~~~~~~~~~~~~~~~  0d40e80a		ld3r {v10.2s, v11.2s, v12.2s}, [x0]
+0x~~~~~~~~~~~~~~~~  0dc2e820		ld3r {v0.2s, v1.2s, v2.2s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0ddfe837		ld3r {v23.2s, v24.2s, v25.2s}, [x1], #12
+0x~~~~~~~~~~~~~~~~  0d40e416		ld3r {v22.4h, v23.4h, v24.4h}, [x0]
+0x~~~~~~~~~~~~~~~~  0dc2e426		ld3r {v6.4h, v7.4h, v8.4h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0ddfe427		ld3r {v7.4h, v8.4h, v9.4h}, [x1], #6
+0x~~~~~~~~~~~~~~~~  4d40e81a		ld3r {v26.4s, v27.4s, v28.4s}, [x0]
+0x~~~~~~~~~~~~~~~~  4dc2e820		ld3r {v0.4s, v1.4s, v2.4s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4ddfe83e		ld3r {v30.4s, v31.4s, v0.4s}, [x1], #12
+0x~~~~~~~~~~~~~~~~  0d40e002		ld3r {v2.8b, v3.8b, v4.8b}, [x0]
+0x~~~~~~~~~~~~~~~~  0dc2e02a		ld3r {v10.8b, v11.8b, v12.8b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0ddfe03c		ld3r {v28.8b, v29.8b, v30.8b}, [x1], #3
+0x~~~~~~~~~~~~~~~~  4d40e406		ld3r {v6.8h, v7.8h, v8.8h}, [x0]
+0x~~~~~~~~~~~~~~~~  4dc2e43d		ld3r {v29.8h, v30.8h, v31.8h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4ddfe427		ld3r {v7.8h, v8.8h, v9.8h}, [x1], #6
+0x~~~~~~~~~~~~~~~~  4c400003		ld4 {v3.16b, v4.16b, v5.16b, v6.16b}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc20022		ld4 {v2.16b, v3.16b, v4.16b, v5.16b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf0025		ld4 {v5.16b, v6.16b, v7.16b, v8.16b}, [x1], #64
+0x~~~~~~~~~~~~~~~~  4c400c12		ld4 {v18.2d, v19.2d, v20.2d, v21.2d}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc20c24		ld4 {v4.2d, v5.2d, v6.2d, v7.2d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf0c3d		ld4 {v29.2d, v30.2d, v31.2d, v0.2d}, [x1], #64
+0x~~~~~~~~~~~~~~~~  0c40081b		ld4 {v27.2s, v28.2s, v29.2s, v30.2s}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc20838		ld4 {v24.2s, v25.2s, v26.2s, v27.2s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf0824		ld4 {v4.2s, v5.2s, v6.2s, v7.2s}, [x1], #32
+0x~~~~~~~~~~~~~~~~  0c400410		ld4 {v16.4h, v17.4h, v18.4h, v19.4h}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc20437		ld4 {v23.4h, v24.4h, v25.4h, v26.4h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf0422		ld4 {v2.4h, v3.4h, v4.4h, v5.4h}, [x1], #32
+0x~~~~~~~~~~~~~~~~  4c400807		ld4 {v7.4s, v8.4s, v9.4s, v10.4s}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc2083c		ld4 {v28.4s, v29.4s, v30.4s, v31.4s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf083d		ld4 {v29.4s, v30.4s, v31.4s, v0.4s}, [x1], #64
+0x~~~~~~~~~~~~~~~~  0c40000f		ld4 {v15.8b, v16.8b, v17.8b, v18.8b}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc2003b		ld4 {v27.8b, v28.8b, v29.8b, v30.8b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf0025		ld4 {v5.8b, v6.8b, v7.8b, v8.8b}, [x1], #32
+0x~~~~~~~~~~~~~~~~  4c400419		ld4 {v25.8h, v26.8h, v27.8h, v28.8h}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc20422		ld4 {v2.8h, v3.8h, v4.8h, v5.8h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf0434		ld4 {v20.8h, v21.8h, v22.8h, v23.8h}, [x1], #64
+0x~~~~~~~~~~~~~~~~  0d602c14		ld4 {v20.b, v21.b, v22.b, v23.b}[3], [x0]
+0x~~~~~~~~~~~~~~~~  0de22c2c		ld4 {v12.b, v13.b, v14.b, v15.b}[3], [x1], x2
+0x~~~~~~~~~~~~~~~~  0dff383b		ld4 {v27.b, v28.b, v29.b, v30.b}[6], [x1], #4
+0x~~~~~~~~~~~~~~~~  4d60a41c		ld4 {v28.d, v29.d, v30.d, v31.d}[1], [x0]
+0x~~~~~~~~~~~~~~~~  4de2a42f		ld4 {v15.d, v16.d, v17.d, v18.d}[1], [x1], x2
+0x~~~~~~~~~~~~~~~~  4dffa430		ld4 {v16.d, v17.d, v18.d, v19.d}[1], [x1], #32
+0x~~~~~~~~~~~~~~~~  4d607002		ld4 {v2.h, v3.h, v4.h, v5.h}[6], [x0]
+0x~~~~~~~~~~~~~~~~  0de27825		ld4 {v5.h, v6.h, v7.h, v8.h}[3], [x1], x2
+0x~~~~~~~~~~~~~~~~  4dff7027		ld4 {v7.h, v8.h, v9.h, v10.h}[6], [x1], #8
+0x~~~~~~~~~~~~~~~~  0d60b006		ld4 {v6.s, v7.s, v8.s, v9.s}[1], [x0]
+0x~~~~~~~~~~~~~~~~  4de2a039		ld4 {v25.s, v26.s, v27.s, v28.s}[2], [x1], x2
+0x~~~~~~~~~~~~~~~~  4dffb028		ld4 {v8.s, v9.s, v10.s, v11.s}[3], [x1], #16
+0x~~~~~~~~~~~~~~~~  4d60e00e		ld4r {v14.16b, v15.16b, v16.16b, v17.16b}, [x0]
+0x~~~~~~~~~~~~~~~~  4de2e02d		ld4r {v13.16b, v14.16b, v15.16b, v16.16b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4dffe029		ld4r {v9.16b, v10.16b, v11.16b, v12.16b}, [x1], #4
+0x~~~~~~~~~~~~~~~~  0d60ec08		ld4r {v8.1d, v9.1d, v10.1d, v11.1d}, [x0]
+0x~~~~~~~~~~~~~~~~  0de2ec24		ld4r {v4.1d, v5.1d, v6.1d, v7.1d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0dffec3a		ld4r {v26.1d, v27.1d, v28.1d, v29.1d}, [x1], #32
+0x~~~~~~~~~~~~~~~~  4d60ec13		ld4r {v19.2d, v20.2d, v21.2d, v22.2d}, [x0]
+0x~~~~~~~~~~~~~~~~  4de2ec3c		ld4r {v28.2d, v29.2d, v30.2d, v31.2d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4dffec2f		ld4r {v15.2d, v16.2d, v17.2d, v18.2d}, [x1], #32
+0x~~~~~~~~~~~~~~~~  0d60e81f		ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [x0]
+0x~~~~~~~~~~~~~~~~  0de2e83c		ld4r {v28.2s, v29.2s, v30.2s, v31.2s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0dffe82b		ld4r {v11.2s, v12.2s, v13.2s, v14.2s}, [x1], #16
+0x~~~~~~~~~~~~~~~~  0d60e413		ld4r {v19.4h, v20.4h, v21.4h, v22.4h}, [x0]
+0x~~~~~~~~~~~~~~~~  0de2e436		ld4r {v22.4h, v23.4h, v24.4h, v25.4h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0dffe434		ld4r {v20.4h, v21.4h, v22.4h, v23.4h}, [x1], #8
+0x~~~~~~~~~~~~~~~~  4d60e810		ld4r {v16.4s, v17.4s, v18.4s, v19.4s}, [x0]
+0x~~~~~~~~~~~~~~~~  4de2e839		ld4r {v25.4s, v26.4s, v27.4s, v28.4s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4dffe837		ld4r {v23.4s, v24.4s, v25.4s, v26.4s}, [x1], #16
+0x~~~~~~~~~~~~~~~~  0d60e016		ld4r {v22.8b, v23.8b, v24.8b, v25.8b}, [x0]
+0x~~~~~~~~~~~~~~~~  0de2e03b		ld4r {v27.8b, v28.8b, v29.8b, v30.8b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0dffe03d		ld4r {v29.8b, v30.8b, v31.8b, v0.8b}, [x1], #4
+0x~~~~~~~~~~~~~~~~  4d60e41c		ld4r {v28.8h, v29.8h, v30.8h, v31.8h}, [x0]
+0x~~~~~~~~~~~~~~~~  4de2e439		ld4r {v25.8h, v26.8h, v27.8h, v28.8h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4dffe436		ld4r {v22.8h, v23.8h, v24.8h, v25.8h}, [x1], #8
+0x~~~~~~~~~~~~~~~~  4e3a94fd		mla v29.16b, v7.16b, v26.16b
+0x~~~~~~~~~~~~~~~~  0eae9486		mla v6.2s, v4.2s, v14.2s
+0x~~~~~~~~~~~~~~~~  2f800969		mla v9.2s, v11.2s, v0.s[2]
+0x~~~~~~~~~~~~~~~~  0e799625		mla v5.4h, v17.4h, v25.4h
+0x~~~~~~~~~~~~~~~~  2f7b00f8		mla v24.4h, v7.4h, v11.h[3]
+0x~~~~~~~~~~~~~~~~  4ea4946c		mla v12.4s, v3.4s, v4.4s
+0x~~~~~~~~~~~~~~~~  6fa708ea		mla v10.4s, v7.4s, v7.s[3]
+0x~~~~~~~~~~~~~~~~  0e299603		mla v3.8b, v16.8b, v9.8b
+0x~~~~~~~~~~~~~~~~  4e7296d3		mla v19.8h, v22.8h, v18.8h
+0x~~~~~~~~~~~~~~~~  6f400046		mla v6.8h, v2.8h, v0.h[0]
+0x~~~~~~~~~~~~~~~~  6e2b9557		mls v23.16b, v10.16b, v11.16b
+0x~~~~~~~~~~~~~~~~  2eb697ee		mls v14.2s, v31.2s, v22.2s
+0x~~~~~~~~~~~~~~~~  2fa149bc		mls v28.2s, v13.2s, v1.s[3]
+0x~~~~~~~~~~~~~~~~  2e6d9662		mls v2.4h, v19.4h, v13.4h
+0x~~~~~~~~~~~~~~~~  2f6c49f2		mls v18.4h, v15.4h, v12.h[6]
+0x~~~~~~~~~~~~~~~~  6eb09566		mls v6.4s, v11.4s, v16.4s
+0x~~~~~~~~~~~~~~~~  6f8a4a17		mls v23.4s, v16.4s, v10.s[2]
+0x~~~~~~~~~~~~~~~~  2e3795ba		mls v26.8b, v13.8b, v23.8b
+0x~~~~~~~~~~~~~~~~  6e6c954a		mls v10.8h, v10.8h, v12.8h
+0x~~~~~~~~~~~~~~~~  6f7e480e		mls v14.8h, v0.8h, v14.h[7]
+0x~~~~~~~~~~~~~~~~  5e070436		mov b22, v1.b[3]
+0x~~~~~~~~~~~~~~~~  5e1805a7		mov d7, v13.d[1]
+0x~~~~~~~~~~~~~~~~  5e0a06ba		mov h26, v21.h[2]
+0x~~~~~~~~~~~~~~~~  5e04067a		mov s26, v19.s[0]
+0x~~~~~~~~~~~~~~~~  4eab1d7a		mov v26.16b, v11.16b
+0x~~~~~~~~~~~~~~~~  0ea01c14		mov v20.8b, v0.8b
+0x~~~~~~~~~~~~~~~~  6e1b24d3		mov v19.b[13], v6.b[4]
+0x~~~~~~~~~~~~~~~~  4e1b1e64		mov v4.b[13], w19
+0x~~~~~~~~~~~~~~~~  6e18050b		mov v11.d[1], v8.d[0]
+0x~~~~~~~~~~~~~~~~  4e081fc3		mov v3.d[0], x30
+0x~~~~~~~~~~~~~~~~  6e12757d		mov v29.h[4], v11.h[7]
+0x~~~~~~~~~~~~~~~~  4e1a1cc2		mov v2.h[6], w6
+0x~~~~~~~~~~~~~~~~  6e0444b6		mov v22.s[0], v5.s[2]
+0x~~~~~~~~~~~~~~~~  4e1c1d18		mov v24.s[3], w8
+0x~~~~~~~~~~~~~~~~  0e1c3c32		mov w18, v1.s[3]
+0x~~~~~~~~~~~~~~~~  4e083ebc		mov x28, v21.d[0]
+0x~~~~~~~~~~~~~~~~  2f03e4f8		movi d24, #0xffff0000ffffff
+0x~~~~~~~~~~~~~~~~  4f04e41d		movi v29.16b, #0x80
+0x~~~~~~~~~~~~~~~~  6f06e6cc		movi v12.2d, #0xffff00ff00ffff00
+0x~~~~~~~~~~~~~~~~  0f07658c		movi v12.2s, #0xec, lsl #24
+0x~~~~~~~~~~~~~~~~  0f02d58a		movi v10.2s, #0x4c, msl #16
+0x~~~~~~~~~~~~~~~~  0f06841a		movi v26.4h, #0xc0, lsl #0
+0x~~~~~~~~~~~~~~~~  4f044718		movi v24.4s, #0x98, lsl #16
+0x~~~~~~~~~~~~~~~~  4f06d7c1		movi v1.4s, #0xde, msl #16
+0x~~~~~~~~~~~~~~~~  0f02e5b5		movi v21.8b, #0x4d
+0x~~~~~~~~~~~~~~~~  4f03853d		movi v29.8h, #0x69, lsl #0
+0x~~~~~~~~~~~~~~~~  4e319de1		mul v1.16b, v15.16b, v17.16b
+0x~~~~~~~~~~~~~~~~  0ebd9e75		mul v21.2s, v19.2s, v29.2s
+0x~~~~~~~~~~~~~~~~  0f8380b3		mul v19.2s, v5.2s, v3.s[0]
+0x~~~~~~~~~~~~~~~~  0e629d7d		mul v29.4h, v11.4h, v2.4h
+0x~~~~~~~~~~~~~~~~  0f4080e2		mul v2.4h, v7.4h, v0.h[0]
+0x~~~~~~~~~~~~~~~~  4eb09f59		mul v25.4s, v26.4s, v16.4s
+0x~~~~~~~~~~~~~~~~  4f8f88da		mul v26.4s, v6.4s, v15.s[2]
+0x~~~~~~~~~~~~~~~~  0e3f9deb		mul v11.8b, v15.8b, v31.8b
+0x~~~~~~~~~~~~~~~~  4e6f9ff4		mul v20.8h, v31.8h, v15.8h
+0x~~~~~~~~~~~~~~~~  4f4988bd		mul v29.8h, v5.8h, v9.h[4]
+0x~~~~~~~~~~~~~~~~  6e205aad		mvn v13.16b, v21.16b
+0x~~~~~~~~~~~~~~~~  2e205a7c		mvn v28.8b, v19.8b
+0x~~~~~~~~~~~~~~~~  2f052719		mvni v25.2s, #0xb8, lsl #8
+0x~~~~~~~~~~~~~~~~  2f03d591		mvni v17.2s, #0x6c, msl #16
+0x~~~~~~~~~~~~~~~~  2f02851d		mvni v29.4h, #0x48, lsl #0
+0x~~~~~~~~~~~~~~~~  6f034754		mvni v20.4s, #0x7a, lsl #16
+0x~~~~~~~~~~~~~~~~  6f00c7c0		mvni v0.4s, #0x1e, msl #8
+0x~~~~~~~~~~~~~~~~  6f0187df		mvni v31.8h, #0x3e, lsl #0
+0x~~~~~~~~~~~~~~~~  7ee0b979		neg d25, d11
+0x~~~~~~~~~~~~~~~~  6e20b924		neg v4.16b, v9.16b
+0x~~~~~~~~~~~~~~~~  6ee0bb2b		neg v11.2d, v25.2d
+0x~~~~~~~~~~~~~~~~  2ea0ba47		neg v7.2s, v18.2s
+0x~~~~~~~~~~~~~~~~  2e60b9e7		neg v7.4h, v15.4h
+0x~~~~~~~~~~~~~~~~  6ea0ba51		neg v17.4s, v18.4s
+0x~~~~~~~~~~~~~~~~  2e20ba34		neg v20.8b, v17.8b
+0x~~~~~~~~~~~~~~~~  6e60b960		neg v0.8h, v11.8h
+0x~~~~~~~~~~~~~~~~  4eff1d6d		orn v13.16b, v11.16b, v31.16b
+0x~~~~~~~~~~~~~~~~  0ef61e16		orn v22.8b, v16.8b, v22.8b
+0x~~~~~~~~~~~~~~~~  4eb71e31		orr v17.16b, v17.16b, v23.16b
+0x~~~~~~~~~~~~~~~~  0f071468		orr v8.2s, #0xe3, lsl #0
+0x~~~~~~~~~~~~~~~~  0f04b6eb		orr v11.4h, #0x97, lsl #8
+0x~~~~~~~~~~~~~~~~  4f051567		orr v7.4s, #0xab, lsl #0
+0x~~~~~~~~~~~~~~~~  0ea31c88		orr v8.8b, v4.8b, v3.8b
+0x~~~~~~~~~~~~~~~~  4f05b61f		orr v31.8h, #0xb0, lsl #8
+0x~~~~~~~~~~~~~~~~  6e379e4b		pmul v11.16b, v18.16b, v23.16b
+0x~~~~~~~~~~~~~~~~  2e259f08		pmul v8.8b, v24.8b, v5.8b
+0x~~~~~~~~~~~~~~~~  0e36e258		pmull v24.8h, v18.8b, v22.8b
+0x~~~~~~~~~~~~~~~~  4e35e06d		pmull2 v13.8h, v3.16b, v21.16b
+0x~~~~~~~~~~~~~~~~  2eb54156		raddhn v22.2s, v10.2d, v21.2d
+0x~~~~~~~~~~~~~~~~  2e6d41a5		raddhn v5.4h, v13.4s, v13.4s
+0x~~~~~~~~~~~~~~~~  2e3a422a		raddhn v10.8b, v17.8h, v26.8h
+0x~~~~~~~~~~~~~~~~  6e2d43a9		raddhn2 v9.16b, v29.8h, v13.8h
+0x~~~~~~~~~~~~~~~~  6eba42fb		raddhn2 v27.4s, v23.2d, v26.2d
+0x~~~~~~~~~~~~~~~~  6e6743a0		raddhn2 v0.8h, v29.4s, v7.4s
+0x~~~~~~~~~~~~~~~~  6e6059f6		rbit v22.16b, v15.16b
+0x~~~~~~~~~~~~~~~~  2e60587e		rbit v30.8b, v3.8b
+0x~~~~~~~~~~~~~~~~  4e201b7f		rev16 v31.16b, v27.16b
+0x~~~~~~~~~~~~~~~~  0e201b4c		rev16 v12.8b, v26.8b
+0x~~~~~~~~~~~~~~~~  6e200885		rev32 v5.16b, v4.16b
+0x~~~~~~~~~~~~~~~~  2e600b50		rev32 v16.4h, v26.4h
+0x~~~~~~~~~~~~~~~~  2e200874		rev32 v20.8b, v3.8b
+0x~~~~~~~~~~~~~~~~  6e600b94		rev32 v20.8h, v28.8h
+0x~~~~~~~~~~~~~~~~  4e200a69		rev64 v9.16b, v19.16b
+0x~~~~~~~~~~~~~~~~  0ea00a05		rev64 v5.2s, v16.2s
+0x~~~~~~~~~~~~~~~~  0e600be7		rev64 v7.4h, v31.4h
+0x~~~~~~~~~~~~~~~~  4ea00b4f		rev64 v15.4s, v26.4s
+0x~~~~~~~~~~~~~~~~  0e200939		rev64 v25.8b, v9.8b
+0x~~~~~~~~~~~~~~~~  4e6008ab		rev64 v11.8h, v5.8h
+0x~~~~~~~~~~~~~~~~  0f3f8db2		rshrn v18.2s, v13.2d, #1
+0x~~~~~~~~~~~~~~~~  0f1e8fd9		rshrn v25.4h, v30.4s, #2
+0x~~~~~~~~~~~~~~~~  0f088d2d		rshrn v13.8b, v9.8h, #8
+0x~~~~~~~~~~~~~~~~  4f088cc3		rshrn2 v3.16b, v6.8h, #8
+0x~~~~~~~~~~~~~~~~  4f278fa0		rshrn2 v0.4s, v29.2d, #25
+0x~~~~~~~~~~~~~~~~  4f118f5b		rshrn2 v27.8h, v26.4s, #15
+0x~~~~~~~~~~~~~~~~  2ea4632f		rsubhn v15.2s, v25.2d, v4.2d
+0x~~~~~~~~~~~~~~~~  2e636137		rsubhn v23.4h, v9.4s, v3.4s
+0x~~~~~~~~~~~~~~~~  2e3863c6		rsubhn v6.8b, v30.8h, v24.8h
+0x~~~~~~~~~~~~~~~~  6e346304		rsubhn2 v4.16b, v24.8h, v20.8h
+0x~~~~~~~~~~~~~~~~  6eb662e1		rsubhn2 v1.4s, v23.2d, v22.2d
+0x~~~~~~~~~~~~~~~~  6e746053		rsubhn2 v19.8h, v2.4s, v20.4s
+0x~~~~~~~~~~~~~~~~  4e397d3c		saba v28.16b, v9.16b, v25.16b
+0x~~~~~~~~~~~~~~~~  0eb47f89		saba v9.2s, v28.2s, v20.2s
+0x~~~~~~~~~~~~~~~~  0e767ed1		saba v17.4h, v22.4h, v22.4h
+0x~~~~~~~~~~~~~~~~  4ebb7cbd		saba v29.4s, v5.4s, v27.4s
+0x~~~~~~~~~~~~~~~~  0e327eb4		saba v20.8b, v21.8b, v18.8b
+0x~~~~~~~~~~~~~~~~  4e7e7e3b		saba v27.8h, v17.8h, v30.8h
+0x~~~~~~~~~~~~~~~~  0ea751b4		sabal v20.2d, v13.2s, v7.2s
+0x~~~~~~~~~~~~~~~~  0e645184		sabal v4.4s, v12.4h, v4.4h
+0x~~~~~~~~~~~~~~~~  0e345317		sabal v23.8h, v24.8b, v20.8b
+0x~~~~~~~~~~~~~~~~  4eb252ba		sabal2 v26.2d, v21.4s, v18.4s
+0x~~~~~~~~~~~~~~~~  4e68539b		sabal2 v27.4s, v28.8h, v8.8h
+0x~~~~~~~~~~~~~~~~  4e35520c		sabal2 v12.8h, v16.16b, v21.16b
+0x~~~~~~~~~~~~~~~~  4e2d75e0		sabd v0.16b, v15.16b, v13.16b
+0x~~~~~~~~~~~~~~~~  0ebe74ef		sabd v15.2s, v7.2s, v30.2s
+0x~~~~~~~~~~~~~~~~  0e6c7631		sabd v17.4h, v17.4h, v12.4h
+0x~~~~~~~~~~~~~~~~  4eb67487		sabd v7.4s, v4.4s, v22.4s
+0x~~~~~~~~~~~~~~~~  0e3a7477		sabd v23.8b, v3.8b, v26.8b
+0x~~~~~~~~~~~~~~~~  4e657794		sabd v20.8h, v28.8h, v5.8h
+0x~~~~~~~~~~~~~~~~  0eb472db		sabdl v27.2d, v22.2s, v20.2s
+0x~~~~~~~~~~~~~~~~  0e77729f		sabdl v31.4s, v20.4h, v23.4h
+0x~~~~~~~~~~~~~~~~  0e3b7280		sabdl v0.8h, v20.8b, v27.8b
+0x~~~~~~~~~~~~~~~~  4ea3717f		sabdl2 v31.2d, v11.4s, v3.4s
+0x~~~~~~~~~~~~~~~~  4e7b717a		sabdl2 v26.4s, v11.8h, v27.8h
+0x~~~~~~~~~~~~~~~~  4e327106		sabdl2 v6.8h, v8.16b, v18.16b
+0x~~~~~~~~~~~~~~~~  0ea06b48		sadalp v8.1d, v26.2s
+0x~~~~~~~~~~~~~~~~  4ea06b4c		sadalp v12.2d, v26.4s
+0x~~~~~~~~~~~~~~~~  0e606b4c		sadalp v12.2s, v26.4h
+0x~~~~~~~~~~~~~~~~  0e206824		sadalp v4.4h, v1.8b
+0x~~~~~~~~~~~~~~~~  4e606a2f		sadalp v15.4s, v17.8h
+0x~~~~~~~~~~~~~~~~  4e206b35		sadalp v21.8h, v25.16b
+0x~~~~~~~~~~~~~~~~  0eae0145		saddl v5.2d, v10.2s, v14.2s
+0x~~~~~~~~~~~~~~~~  0e6f0072		saddl v18.4s, v3.4h, v15.4h
+0x~~~~~~~~~~~~~~~~  0e37004f		saddl v15.8h, v2.8b, v23.8b
+0x~~~~~~~~~~~~~~~~  4ebb0210		saddl2 v16.2d, v16.4s, v27.4s
+0x~~~~~~~~~~~~~~~~  4e600306		saddl2 v6.4s, v24.8h, v0.8h
+0x~~~~~~~~~~~~~~~~  4e3c0287		saddl2 v7.8h, v20.16b, v28.16b
+0x~~~~~~~~~~~~~~~~  0ea02b2a		saddlp v10.1d, v25.2s
+0x~~~~~~~~~~~~~~~~  4ea02a0f		saddlp v15.2d, v16.4s
+0x~~~~~~~~~~~~~~~~  0e602952		saddlp v18.2s, v10.4h
+0x~~~~~~~~~~~~~~~~  0e202b5d		saddlp v29.4h, v26.8b
+0x~~~~~~~~~~~~~~~~  4e60282a		saddlp v10.4s, v1.8h
+0x~~~~~~~~~~~~~~~~  4e202aa0		saddlp v0.8h, v21.16b
+0x~~~~~~~~~~~~~~~~  4eb038ec		saddlv d12, v7.4s
+0x~~~~~~~~~~~~~~~~  4e303b8e		saddlv h14, v28.16b
+0x~~~~~~~~~~~~~~~~  0e303bde		saddlv h30, v30.8b
+0x~~~~~~~~~~~~~~~~  0e70387b		saddlv s27, v3.4h
+0x~~~~~~~~~~~~~~~~  4e703a10		saddlv s16, v16.8h
+0x~~~~~~~~~~~~~~~~  0eb21178		saddw v24.2d, v11.2d, v18.2s
+0x~~~~~~~~~~~~~~~~  0e66118d		saddw v13.4s, v12.4s, v6.4h
+0x~~~~~~~~~~~~~~~~  0e271273		saddw v19.8h, v19.8h, v7.8b
+0x~~~~~~~~~~~~~~~~  4eba113b		saddw2 v27.2d, v9.2d, v26.4s
+0x~~~~~~~~~~~~~~~~  4e7512f3		saddw2 v19.4s, v23.4s, v21.8h
+0x~~~~~~~~~~~~~~~~  4e3e132f		saddw2 v15.8h, v25.8h, v30.16b
+0x~~~~~~~~~~~~~~~~  4e290487		shadd v7.16b, v4.16b, v9.16b
+0x~~~~~~~~~~~~~~~~  0eb8073d		shadd v29.2s, v25.2s, v24.2s
+0x~~~~~~~~~~~~~~~~  0e6d055f		shadd v31.4h, v10.4h, v13.4h
+0x~~~~~~~~~~~~~~~~  4ea80615		shadd v21.4s, v16.4s, v8.4s
+0x~~~~~~~~~~~~~~~~  0e3607ae		shadd v14.8b, v29.8b, v22.8b
+0x~~~~~~~~~~~~~~~~  4e740713		shadd v19.8h, v24.8h, v20.8h
+0x~~~~~~~~~~~~~~~~  5f575736		shl d22, d25, #23
+0x~~~~~~~~~~~~~~~~  4f0f5625		shl v5.16b, v17.16b, #7
+0x~~~~~~~~~~~~~~~~  4f555482		shl v2.2d, v4.2d, #21
+0x~~~~~~~~~~~~~~~~  0f3a5464		shl v4.2s, v3.2s, #26
+0x~~~~~~~~~~~~~~~~  0f185783		shl v3.4h, v28.4h, #8
+0x~~~~~~~~~~~~~~~~  4f3857e4		shl v4.4s, v31.4s, #24
+0x~~~~~~~~~~~~~~~~  0f0a5612		shl v18.8b, v16.8b, #2
+0x~~~~~~~~~~~~~~~~  4f135560		shl v0.8h, v11.8h, #3
+0x~~~~~~~~~~~~~~~~  2ea13b05		shll v5.2d, v24.2s, #32
+0x~~~~~~~~~~~~~~~~  2e613a9a		shll v26.4s, v20.4h, #16
+0x~~~~~~~~~~~~~~~~  2e213925		shll v5.8h, v9.8b, #8
+0x~~~~~~~~~~~~~~~~  6ea13b95		shll2 v21.2d, v28.4s, #32
+0x~~~~~~~~~~~~~~~~  6e613836		shll2 v22.4s, v1.8h, #16
+0x~~~~~~~~~~~~~~~~  6e213b3e		shll2 v30.8h, v25.16b, #8
+0x~~~~~~~~~~~~~~~~  0f248425		shrn v5.2s, v1.2d, #28
+0x~~~~~~~~~~~~~~~~  0f19865d		shrn v29.4h, v18.4s, #7
+0x~~~~~~~~~~~~~~~~  0f0e87b1		shrn v17.8b, v29.8h, #2
+0x~~~~~~~~~~~~~~~~  4f0d87c5		shrn2 v5.16b, v30.8h, #3
+0x~~~~~~~~~~~~~~~~  4f3f8438		shrn2 v24.4s, v1.2d, #1
+0x~~~~~~~~~~~~~~~~  4f1085c5		shrn2 v5.8h, v14.4s, #16
+0x~~~~~~~~~~~~~~~~  4e3726de		shsub v30.16b, v22.16b, v23.16b
+0x~~~~~~~~~~~~~~~~  0eb92776		shsub v22.2s, v27.2s, v25.2s
+0x~~~~~~~~~~~~~~~~  0e6126cd		shsub v13.4h, v22.4h, v1.4h
+0x~~~~~~~~~~~~~~~~  4eb7250a		shsub v10.4s, v8.4s, v23.4s
+0x~~~~~~~~~~~~~~~~  0e3f2526		shsub v6.8b, v9.8b, v31.8b
+0x~~~~~~~~~~~~~~~~  4e6827e8		shsub v8.8h, v31.8h, v8.8h
+0x~~~~~~~~~~~~~~~~  7f5457b3		sli d19, d29, #20
+0x~~~~~~~~~~~~~~~~  6f085709		sli v9.16b, v24.16b, #0
+0x~~~~~~~~~~~~~~~~  6f4a5536		sli v22.2d, v9.2d, #10
+0x~~~~~~~~~~~~~~~~  2f34576b		sli v11.2s, v27.2s, #20
+0x~~~~~~~~~~~~~~~~  2f1555f0		sli v16.4h, v15.4h, #5
+0x~~~~~~~~~~~~~~~~  6f395508		sli v8.4s, v8.4s, #25
+0x~~~~~~~~~~~~~~~~  2f0857ca		sli v10.8b, v30.8b, #0
+0x~~~~~~~~~~~~~~~~  6f165787		sli v7.8h, v28.8h, #6
+0x~~~~~~~~~~~~~~~~  4e216512		smax v18.16b, v8.16b, v1.16b
+0x~~~~~~~~~~~~~~~~  0ea164be		smax v30.2s, v5.2s, v1.2s
+0x~~~~~~~~~~~~~~~~  0e736731		smax v17.4h, v25.4h, v19.4h
+0x~~~~~~~~~~~~~~~~  4ebf6701		smax v1.4s, v24.4s, v31.4s
+0x~~~~~~~~~~~~~~~~  0e386711		smax v17.8b, v24.8b, v24.8b
+0x~~~~~~~~~~~~~~~~  4e6a674b		smax v11.8h, v26.8h, v10.8h
+0x~~~~~~~~~~~~~~~~  4e27a5cc		smaxp v12.16b, v14.16b, v7.16b
+0x~~~~~~~~~~~~~~~~  0ea6a71f		smaxp v31.2s, v24.2s, v6.2s
+0x~~~~~~~~~~~~~~~~  0e6aa7aa		smaxp v10.4h, v29.4h, v10.4h
+0x~~~~~~~~~~~~~~~~  4ea7a572		smaxp v18.4s, v11.4s, v7.4s
+0x~~~~~~~~~~~~~~~~  0e32a415		smaxp v21.8b, v0.8b, v18.8b
+0x~~~~~~~~~~~~~~~~  4e6fa51a		smaxp v26.8h, v8.8h, v15.8h
+0x~~~~~~~~~~~~~~~~  4e30a8a4		smaxv b4, v5.16b
+0x~~~~~~~~~~~~~~~~  0e30a817		smaxv b23, v0.8b
+0x~~~~~~~~~~~~~~~~  0e70a806		smaxv h6, v0.4h
+0x~~~~~~~~~~~~~~~~  4e70a918		smaxv h24, v8.8h
+0x~~~~~~~~~~~~~~~~  4eb0aa03		smaxv s3, v16.4s
+0x~~~~~~~~~~~~~~~~  4e326d18		smin v24.16b, v8.16b, v18.16b
+0x~~~~~~~~~~~~~~~~  0eb76d1d		smin v29.2s, v8.2s, v23.2s
+0x~~~~~~~~~~~~~~~~  0e756d66		smin v6.4h, v11.4h, v21.4h
+0x~~~~~~~~~~~~~~~~  4eaf6ef8		smin v24.4s, v23.4s, v15.4s
+0x~~~~~~~~~~~~~~~~  0e246e08		smin v8.8b, v16.8b, v4.8b
+0x~~~~~~~~~~~~~~~~  4e6a6c2c		smin v12.8h, v1.8h, v10.8h
+0x~~~~~~~~~~~~~~~~  4e3cae4d		sminp v13.16b, v18.16b, v28.16b
+0x~~~~~~~~~~~~~~~~  0eb0af96		sminp v22.2s, v28.2s, v16.2s
+0x~~~~~~~~~~~~~~~~  0e65ad8f		sminp v15.4h, v12.4h, v5.4h
+0x~~~~~~~~~~~~~~~~  4ea8ae2f		sminp v15.4s, v17.4s, v8.4s
+0x~~~~~~~~~~~~~~~~  0e26ac55		sminp v21.8b, v2.8b, v6.8b
+0x~~~~~~~~~~~~~~~~  4e66ad95		sminp v21.8h, v12.8h, v6.8h
+0x~~~~~~~~~~~~~~~~  4e31a8c8		sminv b8, v6.16b
+0x~~~~~~~~~~~~~~~~  0e31aa46		sminv b6, v18.8b
+0x~~~~~~~~~~~~~~~~  0e71a834		sminv h20, v1.4h
+0x~~~~~~~~~~~~~~~~  4e71aa27		sminv h7, v17.8h
+0x~~~~~~~~~~~~~~~~  4eb1a895		sminv s21, v4.4s
+0x~~~~~~~~~~~~~~~~  0eb581d8		smlal v24.2d, v14.2s, v21.2s
+0x~~~~~~~~~~~~~~~~  0f8e287f		smlal v31.2d, v3.2s, v14.s[2]
+0x~~~~~~~~~~~~~~~~  0e758287		smlal v7.4s, v20.4h, v21.4h
+0x~~~~~~~~~~~~~~~~  0f792213		smlal v19.4s, v16.4h, v9.h[3]
+0x~~~~~~~~~~~~~~~~  0e2181dd		smlal v29.8h, v14.8b, v1.8b
+0x~~~~~~~~~~~~~~~~  4eb0835e		smlal2 v30.2d, v26.4s, v16.4s
+0x~~~~~~~~~~~~~~~~  4f8123df		smlal2 v31.2d, v30.4s, v1.s[0]
+0x~~~~~~~~~~~~~~~~  4e6380d1		smlal2 v17.4s, v6.8h, v3.8h
+0x~~~~~~~~~~~~~~~~  4f752beb		smlal2 v11.4s, v31.8h, v5.h[7]
+0x~~~~~~~~~~~~~~~~  4e3d821e		smlal2 v30.8h, v16.16b, v29.16b
+0x~~~~~~~~~~~~~~~~  0eb1a281		smlsl v1.2d, v20.2s, v17.2s
+0x~~~~~~~~~~~~~~~~  0fa5699d		smlsl v29.2d, v12.2s, v5.s[3]
+0x~~~~~~~~~~~~~~~~  0e61a340		smlsl v0.4s, v26.4h, v1.4h
+0x~~~~~~~~~~~~~~~~  0f5668a3		smlsl v3.4s, v5.4h, v6.h[5]
+0x~~~~~~~~~~~~~~~~  0e3aa004		smlsl v4.8h, v0.8b, v26.8b
+0x~~~~~~~~~~~~~~~~  4ea5a1ce		smlsl2 v14.2d, v14.4s, v5.4s
+0x~~~~~~~~~~~~~~~~  4fa060af		smlsl2 v15.2d, v5.4s, v0.s[1]
+0x~~~~~~~~~~~~~~~~  4e7fa23d		smlsl2 v29.4s, v17.8h, v31.8h
+0x~~~~~~~~~~~~~~~~  4f6969e6		smlsl2 v6.4s, v15.8h, v9.h[6]
+0x~~~~~~~~~~~~~~~~  4e2fa1fe		smlsl2 v30.8h, v15.16b, v15.16b
+0x~~~~~~~~~~~~~~~~  0e072cd5		smov w21, v6.b[3]
+0x~~~~~~~~~~~~~~~~  0e1e2f4d		smov w13, v26.h[7]
+0x~~~~~~~~~~~~~~~~  4e0f2e18		smov x24, v16.b[7]
+0x~~~~~~~~~~~~~~~~  4e0e2c87		smov x7, v4.h[3]
+0x~~~~~~~~~~~~~~~~  4e0c2cfd		smov x29, v7.s[1]
+0x~~~~~~~~~~~~~~~~  0eb1c3a4		smull v4.2d, v29.2s, v17.2s
+0x~~~~~~~~~~~~~~~~  0f86aabe		smull v30.2d, v21.2s, v6.s[2]
+0x~~~~~~~~~~~~~~~~  0e77c0b7		smull v23.4s, v5.4h, v23.4h
+0x~~~~~~~~~~~~~~~~  0f52a128		smull v8.4s, v9.4h, v2.h[1]
+0x~~~~~~~~~~~~~~~~  0e21c23f		smull v31.8h, v17.8b, v1.8b
+0x~~~~~~~~~~~~~~~~  4eb7c063		smull2 v3.2d, v3.4s, v23.4s
+0x~~~~~~~~~~~~~~~~  4fa6a3af		smull2 v15.2d, v29.4s, v6.s[1]
+0x~~~~~~~~~~~~~~~~  4e7ec293		smull2 v19.4s, v20.8h, v30.8h
+0x~~~~~~~~~~~~~~~~  4f47a946		smull2 v6.4s, v10.8h, v7.h[4]
+0x~~~~~~~~~~~~~~~~  4e3bc119		smull2 v25.8h, v8.16b, v27.16b
+0x~~~~~~~~~~~~~~~~  5e2079e3		sqabs b3, b15
+0x~~~~~~~~~~~~~~~~  5ee0792e		sqabs d14, d9
+0x~~~~~~~~~~~~~~~~  5e607b9f		sqabs h31, h28
+0x~~~~~~~~~~~~~~~~  5ea07808		sqabs s8, s0
+0x~~~~~~~~~~~~~~~~  4e2078ee		sqabs v14.16b, v7.16b
+0x~~~~~~~~~~~~~~~~  4ee07a77		sqabs v23.2d, v19.2d
+0x~~~~~~~~~~~~~~~~  0ea07b0a		sqabs v10.2s, v24.2s
+0x~~~~~~~~~~~~~~~~  0e607a7f		sqabs v31.4h, v19.4h
+0x~~~~~~~~~~~~~~~~  4ea07817		sqabs v23.4s, v0.4s
+0x~~~~~~~~~~~~~~~~  0e207afd		sqabs v29.8b, v23.8b
+0x~~~~~~~~~~~~~~~~  4e607ab1		sqabs v17.8h, v21.8h
+0x~~~~~~~~~~~~~~~~  5e2d0ee9		sqadd b9, b23, b13
+0x~~~~~~~~~~~~~~~~  5efa0f22		sqadd d2, d25, d26
+0x~~~~~~~~~~~~~~~~  5e790fa7		sqadd h7, h29, h25
+0x~~~~~~~~~~~~~~~~  5eb80ceb		sqadd s11, s7, s24
+0x~~~~~~~~~~~~~~~~  4e3d0e14		sqadd v20.16b, v16.16b, v29.16b
+0x~~~~~~~~~~~~~~~~  4efc0fd7		sqadd v23.2d, v30.2d, v28.2d
+0x~~~~~~~~~~~~~~~~  0ea20e68		sqadd v8.2s, v19.2s, v2.2s
+0x~~~~~~~~~~~~~~~~  0e7f0d94		sqadd v20.4h, v12.4h, v31.4h
+0x~~~~~~~~~~~~~~~~  4eb10dee		sqadd v14.4s, v15.4s, v17.4s
+0x~~~~~~~~~~~~~~~~  0e2d0fa2		sqadd v2.8b, v29.8b, v13.8b
+0x~~~~~~~~~~~~~~~~  4e6e0e67		sqadd v7.8h, v19.8h, v14.8h
+0x~~~~~~~~~~~~~~~~  5ebe90af		sqdmlal d15, s5, s30
+0x~~~~~~~~~~~~~~~~  5fa23958		sqdmlal d24, s10, v2.s[3]
+0x~~~~~~~~~~~~~~~~  5e689269		sqdmlal s9, h19, h8
+0x~~~~~~~~~~~~~~~~  5f7c302e		sqdmlal s14, h1, v12.h[3]
+0x~~~~~~~~~~~~~~~~  0ebf90be		sqdmlal v30.2d, v5.2s, v31.2s
+0x~~~~~~~~~~~~~~~~  0faa31d9		sqdmlal v25.2d, v14.2s, v10.s[1]
+0x~~~~~~~~~~~~~~~~  0e709233		sqdmlal v19.4s, v17.4h, v16.4h
+0x~~~~~~~~~~~~~~~~  0f5830a8		sqdmlal v8.4s, v5.4h, v8.h[1]
+0x~~~~~~~~~~~~~~~~  4ea392e1		sqdmlal2 v1.2d, v23.4s, v3.4s
+0x~~~~~~~~~~~~~~~~  4f893013		sqdmlal2 v19.2d, v0.4s, v9.s[0]
+0x~~~~~~~~~~~~~~~~  4e6b92da		sqdmlal2 v26.4s, v22.8h, v11.8h
+0x~~~~~~~~~~~~~~~~  4f4d3b86		sqdmlal2 v6.4s, v28.8h, v13.h[4]
+0x~~~~~~~~~~~~~~~~  5eb4b3aa		sqdmlsl d10, s29, s20
+0x~~~~~~~~~~~~~~~~  5faa712a		sqdmlsl d10, s9, v10.s[1]
+0x~~~~~~~~~~~~~~~~  5e78b13e		sqdmlsl s30, h9, h24
+0x~~~~~~~~~~~~~~~~  5f56730d		sqdmlsl s13, h24, v6.h[1]
+0x~~~~~~~~~~~~~~~~  0eb4b15b		sqdmlsl v27.2d, v10.2s, v20.2s
+0x~~~~~~~~~~~~~~~~  0fa37af7		sqdmlsl v23.2d, v23.2s, v3.s[3]
+0x~~~~~~~~~~~~~~~~  0e7db227		sqdmlsl v7.4s, v17.4h, v29.4h
+0x~~~~~~~~~~~~~~~~  0f437ab6		sqdmlsl v22.4s, v21.4h, v3.h[4]
+0x~~~~~~~~~~~~~~~~  4eb6b0ec		sqdmlsl2 v12.2d, v7.4s, v22.4s
+0x~~~~~~~~~~~~~~~~  4f887334		sqdmlsl2 v20.2d, v25.4s, v8.s[0]
+0x~~~~~~~~~~~~~~~~  4e72b359		sqdmlsl2 v25.4s, v26.8h, v18.8h
+0x~~~~~~~~~~~~~~~~  4f457279		sqdmlsl2 v25.4s, v19.8h, v5.h[0]
+0x~~~~~~~~~~~~~~~~  5e6cb771		sqdmulh h17, h27, h12
+0x~~~~~~~~~~~~~~~~  5f4bc0b0		sqdmulh h16, h5, v11.h[0]
+0x~~~~~~~~~~~~~~~~  5eb0b661		sqdmulh s1, s19, s16
+0x~~~~~~~~~~~~~~~~  5f82c201		sqdmulh s1, s16, v2.s[0]
+0x~~~~~~~~~~~~~~~~  0ea8b43c		sqdmulh v28.2s, v1.2s, v8.2s
+0x~~~~~~~~~~~~~~~~  0f83c11c		sqdmulh v28.2s, v8.2s, v3.s[0]
+0x~~~~~~~~~~~~~~~~  0e65b72b		sqdmulh v11.4h, v25.4h, v5.4h
+0x~~~~~~~~~~~~~~~~  0f58c9de		sqdmulh v30.4h, v14.4h, v8.h[5]
+0x~~~~~~~~~~~~~~~~  4eadb6b9		sqdmulh v25.4s, v21.4s, v13.4s
+0x~~~~~~~~~~~~~~~~  4faac857		sqdmulh v23.4s, v2.4s, v10.s[3]
+0x~~~~~~~~~~~~~~~~  4e77b4ba		sqdmulh v26.8h, v5.8h, v23.8h
+0x~~~~~~~~~~~~~~~~  4f74c2c4		sqdmulh v4.8h, v22.8h, v4.h[3]
+0x~~~~~~~~~~~~~~~~  5ebad059		sqdmull d25, s2, s26
+0x~~~~~~~~~~~~~~~~  5fa5b1de		sqdmull d30, s14, v5.s[1]
+0x~~~~~~~~~~~~~~~~  5e6bd25d		sqdmull s29, h18, h11
+0x~~~~~~~~~~~~~~~~  5f67b9ab		sqdmull s11, h13, v7.h[6]
+0x~~~~~~~~~~~~~~~~  0ea8d137		sqdmull v23.2d, v9.2s, v8.2s
+0x~~~~~~~~~~~~~~~~  0fa4b3b2		sqdmull v18.2d, v29.2s, v4.s[1]
+0x~~~~~~~~~~~~~~~~  0e67d311		sqdmull v17.4s, v24.4h, v7.4h
+0x~~~~~~~~~~~~~~~~  0f55b1e8		sqdmull v8.4s, v15.4h, v5.h[1]
+0x~~~~~~~~~~~~~~~~  4ea2d1dc		sqdmull2 v28.2d, v14.4s, v2.4s
+0x~~~~~~~~~~~~~~~~  4f8dbb01		sqdmull2 v1.2d, v24.4s, v13.s[2]
+0x~~~~~~~~~~~~~~~~  4e7fd22b		sqdmull2 v11.4s, v17.8h, v31.8h
+0x~~~~~~~~~~~~~~~~  4f7bb281		sqdmull2 v1.4s, v20.8h, v11.h[3]
+0x~~~~~~~~~~~~~~~~  7e207802		sqneg b2, b0
+0x~~~~~~~~~~~~~~~~  7ee07858		sqneg d24, d2
+0x~~~~~~~~~~~~~~~~  7e60787d		sqneg h29, h3
+0x~~~~~~~~~~~~~~~~  7ea07924		sqneg s4, s9
+0x~~~~~~~~~~~~~~~~  6e207bae		sqneg v14.16b, v29.16b
+0x~~~~~~~~~~~~~~~~  6ee0799e		sqneg v30.2d, v12.2d
+0x~~~~~~~~~~~~~~~~  2ea07b5c		sqneg v28.2s, v26.2s
+0x~~~~~~~~~~~~~~~~  2e607884		sqneg v4.4h, v4.4h
+0x~~~~~~~~~~~~~~~~  6ea07909		sqneg v9.4s, v8.4s
+0x~~~~~~~~~~~~~~~~  2e207a94		sqneg v20.8b, v20.8b
+0x~~~~~~~~~~~~~~~~  6e60795b		sqneg v27.8h, v10.8h
+0x~~~~~~~~~~~~~~~~  7e60b707		sqrdmulh h7, h24, h0
+0x~~~~~~~~~~~~~~~~  5f64d86e		sqrdmulh h14, h3, v4.h[6]
+0x~~~~~~~~~~~~~~~~  7eb8b67b		sqrdmulh s27, s19, s24
+0x~~~~~~~~~~~~~~~~  5f84d2bf		sqrdmulh s31, s21, v4.s[0]
+0x~~~~~~~~~~~~~~~~  2ea1b732		sqrdmulh v18.2s, v25.2s, v1.2s
+0x~~~~~~~~~~~~~~~~  0f8dd0b6		sqrdmulh v22.2s, v5.2s, v13.s[0]
+0x~~~~~~~~~~~~~~~~  2e69b716		sqrdmulh v22.4h, v24.4h, v9.4h
+0x~~~~~~~~~~~~~~~~  0f6cd84d		sqrdmulh v13.4h, v2.4h, v12.h[6]
+0x~~~~~~~~~~~~~~~~  6ea2b769		sqrdmulh v9.4s, v27.4s, v2.4s
+0x~~~~~~~~~~~~~~~~  4fa7d2e3		sqrdmulh v3.4s, v23.4s, v7.s[1]
+0x~~~~~~~~~~~~~~~~  6e67b402		sqrdmulh v2.8h, v0.8h, v7.8h
+0x~~~~~~~~~~~~~~~~  4f68d130		sqrdmulh v16.8h, v9.8h, v8.h[2]
+0x~~~~~~~~~~~~~~~~  5e2d5ea8		sqrshl b8, b21, b13
+0x~~~~~~~~~~~~~~~~  5ef45cfd		sqrshl d29, d7, d20
+0x~~~~~~~~~~~~~~~~  5e6a5ddc		sqrshl h28, h14, h10
+0x~~~~~~~~~~~~~~~~  5ea25e5a		sqrshl s26, s18, s2
+0x~~~~~~~~~~~~~~~~  4e3a5ff2		sqrshl v18.16b, v31.16b, v26.16b
+0x~~~~~~~~~~~~~~~~  4ee05c9c		sqrshl v28.2d, v4.2d, v0.2d
+0x~~~~~~~~~~~~~~~~  0ea05cc3		sqrshl v3.2s, v6.2s, v0.2s
+0x~~~~~~~~~~~~~~~~  0e765e41		sqrshl v1.4h, v18.4h, v22.4h
+0x~~~~~~~~~~~~~~~~  4ea75f30		sqrshl v16.4s, v25.4s, v7.4s
+0x~~~~~~~~~~~~~~~~  0e255ea0		sqrshl v0.8b, v21.8b, v5.8b
+0x~~~~~~~~~~~~~~~~  4e685e7e		sqrshl v30.8h, v19.8h, v8.8h
+0x~~~~~~~~~~~~~~~~  5f0c9ea6		sqrshrn b6, h21, #4
+0x~~~~~~~~~~~~~~~~  5f159e2e		sqrshrn h14, s17, #11
+0x~~~~~~~~~~~~~~~~  5f369f79		sqrshrn s25, d27, #10
+0x~~~~~~~~~~~~~~~~  0f2e9da6		sqrshrn v6.2s, v13.2d, #18
+0x~~~~~~~~~~~~~~~~  0f119d25		sqrshrn v5.4h, v9.4s, #15
+0x~~~~~~~~~~~~~~~~  0f0f9d93		sqrshrn v19.8b, v12.8h, #1
+0x~~~~~~~~~~~~~~~~  4f099eb3		sqrshrn2 v19.16b, v21.8h, #7
+0x~~~~~~~~~~~~~~~~  4f339f1d		sqrshrn2 v29.4s, v24.2d, #13
+0x~~~~~~~~~~~~~~~~  4f169c4c		sqrshrn2 v12.8h, v2.4s, #10
+0x~~~~~~~~~~~~~~~~  7f0b8d30		sqrshrun b16, h9, #5
+0x~~~~~~~~~~~~~~~~  7f118f03		sqrshrun h3, s24, #15
+0x~~~~~~~~~~~~~~~~  7f388e50		sqrshrun s16, d18, #8
+0x~~~~~~~~~~~~~~~~  2f388efc		sqrshrun v28.2s, v23.2d, #8
+0x~~~~~~~~~~~~~~~~  2f168f3f		sqrshrun v31.4h, v25.4s, #10
+0x~~~~~~~~~~~~~~~~  2f0e8ef3		sqrshrun v19.8b, v23.8h, #2
+0x~~~~~~~~~~~~~~~~  6f088c18		sqrshrun2 v24.16b, v0.8h, #8
+0x~~~~~~~~~~~~~~~~  6f298c36		sqrshrun2 v22.4s, v1.2d, #23
+0x~~~~~~~~~~~~~~~~  6f138ebc		sqrshrun2 v28.8h, v21.4s, #13
+0x~~~~~~~~~~~~~~~~  5e284ea6		sqshl b6, b21, b8
+0x~~~~~~~~~~~~~~~~  5f0a774b		sqshl b11, b26, #2
+0x~~~~~~~~~~~~~~~~  5ee44c1d		sqshl d29, d0, d4
+0x~~~~~~~~~~~~~~~~  5f6374f5		sqshl d21, d7, #35
+0x~~~~~~~~~~~~~~~~  5e714f34		sqshl h20, h25, h17
+0x~~~~~~~~~~~~~~~~  5f187414		sqshl h20, h0, #8
+0x~~~~~~~~~~~~~~~~  5ea44dbd		sqshl s29, s13, s4
+0x~~~~~~~~~~~~~~~~  5f34756a		sqshl s10, s11, #20
+0x~~~~~~~~~~~~~~~~  4e3c4e48		sqshl v8.16b, v18.16b, v28.16b
+0x~~~~~~~~~~~~~~~~  4f0a77bd		sqshl v29.16b, v29.16b, #2
+0x~~~~~~~~~~~~~~~~  4ef04fe8		sqshl v8.2d, v31.2d, v16.2d
+0x~~~~~~~~~~~~~~~~  4f6575c7		sqshl v7.2d, v14.2d, #37
+0x~~~~~~~~~~~~~~~~  0ea74f40		sqshl v0.2s, v26.2s, v7.2s
+0x~~~~~~~~~~~~~~~~  0f337565		sqshl v5.2s, v11.2s, #19
+0x~~~~~~~~~~~~~~~~  0e604fcb		sqshl v11.4h, v30.4h, v0.4h
+0x~~~~~~~~~~~~~~~~  0f177641		sqshl v1.4h, v18.4h, #7
+0x~~~~~~~~~~~~~~~~  4ebe4c76		sqshl v22.4s, v3.4s, v30.4s
+0x~~~~~~~~~~~~~~~~  4f3c75f0		sqshl v16.4s, v15.4s, #28
+0x~~~~~~~~~~~~~~~~  0e394f86		sqshl v6.8b, v28.8b, v25.8b
+0x~~~~~~~~~~~~~~~~  0f0875e0		sqshl v0.8b, v15.8b, #0
+0x~~~~~~~~~~~~~~~~  4e7e4e06		sqshl v6.8h, v16.8h, v30.8h
+0x~~~~~~~~~~~~~~~~  4f1e7683		sqshl v3.8h, v20.8h, #14
+0x~~~~~~~~~~~~~~~~  7f0e65cd		sqshlu b13, b14, #6
+0x~~~~~~~~~~~~~~~~  7f6c6600		sqshlu d0, d16, #44
+0x~~~~~~~~~~~~~~~~  7f1f67a5		sqshlu h5, h29, #15
+0x~~~~~~~~~~~~~~~~  7f2d651d		sqshlu s29, s8, #13
+0x~~~~~~~~~~~~~~~~  6f0a669b		sqshlu v27.16b, v20.16b, #2
+0x~~~~~~~~~~~~~~~~  6f4b6598		sqshlu v24.2d, v12.2d, #11
+0x~~~~~~~~~~~~~~~~  2f36666c		sqshlu v12.2s, v19.2s, #22
+0x~~~~~~~~~~~~~~~~  2f1b6588		sqshlu v8.4h, v12.4h, #11
+0x~~~~~~~~~~~~~~~~  6f286472		sqshlu v18.4s, v3.4s, #8
+0x~~~~~~~~~~~~~~~~  2f096543		sqshlu v3.8b, v10.8b, #1
+0x~~~~~~~~~~~~~~~~  6f14671e		sqshlu v30.8h, v24.8h, #4
+0x~~~~~~~~~~~~~~~~  5f0f9781		sqshrn b1, h28, #1
+0x~~~~~~~~~~~~~~~~  5f1694ff		sqshrn h31, s7, #10
+0x~~~~~~~~~~~~~~~~  5f289544		sqshrn s4, d10, #24
+0x~~~~~~~~~~~~~~~~  0f23942a		sqshrn v10.2s, v1.2d, #29
+0x~~~~~~~~~~~~~~~~  0f1295a3		sqshrn v3.4h, v13.4s, #14
+0x~~~~~~~~~~~~~~~~  0f0994db		sqshrn v27.8b, v6.8h, #7
+0x~~~~~~~~~~~~~~~~  4f0f96ee		sqshrn2 v14.16b, v23.8h, #1
+0x~~~~~~~~~~~~~~~~  4f2596d9		sqshrn2 v25.4s, v22.2d, #27
+0x~~~~~~~~~~~~~~~~  4f16959f		sqshrn2 v31.8h, v12.4s, #10
+0x~~~~~~~~~~~~~~~~  7f0f8409		sqshrun b9, h0, #1
+0x~~~~~~~~~~~~~~~~  7f1984cb		sqshrun h11, s6, #7
+0x~~~~~~~~~~~~~~~~  7f33858d		sqshrun s13, d12, #13
+0x~~~~~~~~~~~~~~~~  2f3f87ca		sqshrun v10.2s, v30.2d, #1
+0x~~~~~~~~~~~~~~~~  2f15847f		sqshrun v31.4h, v3.4s, #11
+0x~~~~~~~~~~~~~~~~  2f0887dc		sqshrun v28.8b, v30.8h, #8
+0x~~~~~~~~~~~~~~~~  6f0d8770		sqshrun2 v16.16b, v27.8h, #3
+0x~~~~~~~~~~~~~~~~  6f2e85db		sqshrun2 v27.4s, v14.2d, #18
+0x~~~~~~~~~~~~~~~~  6f1f85d7		sqshrun2 v23.8h, v14.4s, #1
+0x~~~~~~~~~~~~~~~~  5e2b2fb3		sqsub b19, b29, b11
+0x~~~~~~~~~~~~~~~~  5ee62ff5		sqsub d21, d31, d6
+0x~~~~~~~~~~~~~~~~  5e732d52		sqsub h18, h10, h19
+0x~~~~~~~~~~~~~~~~  5ea02ca6		sqsub s6, s5, s0
+0x~~~~~~~~~~~~~~~~  4e202ed5		sqsub v21.16b, v22.16b, v0.16b
+0x~~~~~~~~~~~~~~~~  4ef12d56		sqsub v22.2d, v10.2d, v17.2d
+0x~~~~~~~~~~~~~~~~  0ea22ea8		sqsub v8.2s, v21.2s, v2.2s
+0x~~~~~~~~~~~~~~~~  0e7b2f32		sqsub v18.4h, v25.4h, v27.4h
+0x~~~~~~~~~~~~~~~~  4ea62c6d		sqsub v13.4s, v3.4s, v6.4s
+0x~~~~~~~~~~~~~~~~  0e302fbc		sqsub v28.8b, v29.8b, v16.8b
+0x~~~~~~~~~~~~~~~~  4e6a2cd1		sqsub v17.8h, v6.8h, v10.8h
+0x~~~~~~~~~~~~~~~~  5e214b5b		sqxtn b27, h26
+0x~~~~~~~~~~~~~~~~  5e614971		sqxtn h17, s11
+0x~~~~~~~~~~~~~~~~  5ea14bf6		sqxtn s22, d31
+0x~~~~~~~~~~~~~~~~  0ea148ba		sqxtn v26.2s, v5.2d
+0x~~~~~~~~~~~~~~~~  0e6148ed		sqxtn v13.4h, v7.4s
+0x~~~~~~~~~~~~~~~~  0e214a73		sqxtn v19.8b, v19.8h
+0x~~~~~~~~~~~~~~~~  4e214873		sqxtn2 v19.16b, v3.8h
+0x~~~~~~~~~~~~~~~~  4ea14837		sqxtn2 v23.4s, v1.2d
+0x~~~~~~~~~~~~~~~~  4e61486d		sqxtn2 v13.8h, v3.4s
+0x~~~~~~~~~~~~~~~~  7e21293a		sqxtun b26, h9
+0x~~~~~~~~~~~~~~~~  7e612993		sqxtun h19, s12
+0x~~~~~~~~~~~~~~~~  7ea128c3		sqxtun s3, d6
+0x~~~~~~~~~~~~~~~~  2ea12b5d		sqxtun v29.2s, v26.2d
+0x~~~~~~~~~~~~~~~~  2e61295a		sqxtun v26.4h, v10.4s
+0x~~~~~~~~~~~~~~~~  2e212ba7		sqxtun v7.8b, v29.8h
+0x~~~~~~~~~~~~~~~~  6e2129d5		sqxtun2 v21.16b, v14.8h
+0x~~~~~~~~~~~~~~~~  6ea129f8		sqxtun2 v24.4s, v15.2d
+0x~~~~~~~~~~~~~~~~  6e61283e		sqxtun2 v30.8h, v1.4s
+0x~~~~~~~~~~~~~~~~  4e2f1635		srhadd v21.16b, v17.16b, v15.16b
+0x~~~~~~~~~~~~~~~~  0ebd16bc		srhadd v28.2s, v21.2s, v29.2s
+0x~~~~~~~~~~~~~~~~  0e7e1429		srhadd v9.4h, v1.4h, v30.4h
+0x~~~~~~~~~~~~~~~~  4ea21418		srhadd v24.4s, v0.4s, v2.4s
+0x~~~~~~~~~~~~~~~~  0e2f1626		srhadd v6.8b, v17.8b, v15.8b
+0x~~~~~~~~~~~~~~~~  4e7514e5		srhadd v5.8h, v7.8h, v21.8h
+0x~~~~~~~~~~~~~~~~  7f4f45ce		sri d14, d14, #49
+0x~~~~~~~~~~~~~~~~  6f0c4517		sri v23.16b, v8.16b, #4
+0x~~~~~~~~~~~~~~~~  6f6c45b4		sri v20.2d, v13.2d, #20
+0x~~~~~~~~~~~~~~~~  2f284450		sri v16.2s, v2.2s, #24
+0x~~~~~~~~~~~~~~~~  2f1546e5		sri v5.4h, v23.4h, #11
+0x~~~~~~~~~~~~~~~~  6f2945fb		sri v27.4s, v15.4s, #23
+0x~~~~~~~~~~~~~~~~  2f0c47b3		sri v19.8b, v29.8b, #4
+0x~~~~~~~~~~~~~~~~  6f1d47a7		sri v7.8h, v29.8h, #3
+0x~~~~~~~~~~~~~~~~  5efa5522		srshl d2, d9, d26
+0x~~~~~~~~~~~~~~~~  4e2b563d		srshl v29.16b, v17.16b, v11.16b
+0x~~~~~~~~~~~~~~~~  4ee455e8		srshl v8.2d, v15.2d, v4.2d
+0x~~~~~~~~~~~~~~~~  0ea85639		srshl v25.2s, v17.2s, v8.2s
+0x~~~~~~~~~~~~~~~~  0e6754f3		srshl v19.4h, v7.4h, v7.4h
+0x~~~~~~~~~~~~~~~~  4eb1544d		srshl v13.4s, v2.4s, v17.4s
+0x~~~~~~~~~~~~~~~~  0e3554d6		srshl v22.8b, v6.8b, v21.8b
+0x~~~~~~~~~~~~~~~~  4e64562a		srshl v10.8h, v17.8h, v4.8h
+0x~~~~~~~~~~~~~~~~  5f532655		srshr d21, d18, #45
+0x~~~~~~~~~~~~~~~~  4f092563		srshr v3.16b, v11.16b, #7
+0x~~~~~~~~~~~~~~~~  4f4b2755		srshr v21.2d, v26.2d, #53
+0x~~~~~~~~~~~~~~~~  0f2424ab		srshr v11.2s, v5.2s, #28
+0x~~~~~~~~~~~~~~~~  0f142647		srshr v7.4h, v18.4h, #12
+0x~~~~~~~~~~~~~~~~  4f222467		srshr v7.4s, v3.4s, #30
+0x~~~~~~~~~~~~~~~~  0f0a244e		srshr v14.8b, v2.8b, #6
+0x~~~~~~~~~~~~~~~~  4f1d2695		srshr v21.8h, v20.8h, #3
+0x~~~~~~~~~~~~~~~~  5f4137d5		srsra d21, d30, #63
+0x~~~~~~~~~~~~~~~~  4f0a37db		srsra v27.16b, v30.16b, #6
+0x~~~~~~~~~~~~~~~~  4f653594		srsra v20.2d, v12.2d, #27
+0x~~~~~~~~~~~~~~~~  0f3b3620		srsra v0.2s, v17.2s, #5
+0x~~~~~~~~~~~~~~~~  0f11360e		srsra v14.4h, v16.4h, #15
+0x~~~~~~~~~~~~~~~~  4f2c3472		srsra v18.4s, v3.4s, #20
+0x~~~~~~~~~~~~~~~~  0f0f3435		srsra v21.8b, v1.8b, #1
+0x~~~~~~~~~~~~~~~~  4f1e373f		srsra v31.8h, v25.8h, #2
+0x~~~~~~~~~~~~~~~~  5ee945a1		sshl d1, d13, d9
+0x~~~~~~~~~~~~~~~~  4e2f47f1		sshl v17.16b, v31.16b, v15.16b
+0x~~~~~~~~~~~~~~~~  4ee0460d		sshl v13.2d, v16.2d, v0.2d
+0x~~~~~~~~~~~~~~~~  0eb644e0		sshl v0.2s, v7.2s, v22.2s
+0x~~~~~~~~~~~~~~~~  0e644677		sshl v23.4h, v19.4h, v4.4h
+0x~~~~~~~~~~~~~~~~  4eab44a5		sshl v5.4s, v5.4s, v11.4s
+0x~~~~~~~~~~~~~~~~  0e274777		sshl v23.8b, v27.8b, v7.8b
+0x~~~~~~~~~~~~~~~~  4e65455d		sshl v29.8h, v10.8h, v5.8h
+0x~~~~~~~~~~~~~~~~  0f37a440		sshll v0.2d, v2.2s, #23
+0x~~~~~~~~~~~~~~~~  0f18a50b		sshll v11.4s, v8.4h, #8
+0x~~~~~~~~~~~~~~~~  0f09a7a4		sshll v4.8h, v29.8b, #1
+0x~~~~~~~~~~~~~~~~  4f2ea48a		sshll2 v10.2d, v4.4s, #14
+0x~~~~~~~~~~~~~~~~  4f16a7fa		sshll2 v26.4s, v31.8h, #6
+0x~~~~~~~~~~~~~~~~  4f0ca743		sshll2 v3.8h, v26.16b, #4
+0x~~~~~~~~~~~~~~~~  5f6c06b3		sshr d19, d21, #20
+0x~~~~~~~~~~~~~~~~  4f0b06ef		sshr v15.16b, v23.16b, #5
+0x~~~~~~~~~~~~~~~~  4f5a05d1		sshr v17.2d, v14.2d, #38
+0x~~~~~~~~~~~~~~~~  0f2907a3		sshr v3.2s, v29.2s, #23
+0x~~~~~~~~~~~~~~~~  0f1c0777		sshr v23.4h, v27.4h, #4
+0x~~~~~~~~~~~~~~~~  4f3c047c		sshr v28.4s, v3.4s, #4
+0x~~~~~~~~~~~~~~~~  0f0a044e		sshr v14.8b, v2.8b, #6
+0x~~~~~~~~~~~~~~~~  4f1a0503		sshr v3.8h, v8.8h, #6
+0x~~~~~~~~~~~~~~~~  5f54178c		ssra d12, d28, #44
+0x~~~~~~~~~~~~~~~~  4f0c17fd		ssra v29.16b, v31.16b, #4
+0x~~~~~~~~~~~~~~~~  4f681403		ssra v3.2d, v0.2d, #24
+0x~~~~~~~~~~~~~~~~  0f3a178e		ssra v14.2s, v28.2s, #6
+0x~~~~~~~~~~~~~~~~  0f191512		ssra v18.4h, v8.4h, #7
+0x~~~~~~~~~~~~~~~~  4f2815df		ssra v31.4s, v14.4s, #24
+0x~~~~~~~~~~~~~~~~  0f0b175c		ssra v28.8b, v26.8b, #5
+0x~~~~~~~~~~~~~~~~  4f121529		ssra v9.8h, v9.8h, #14
+0x~~~~~~~~~~~~~~~~  0ea321cd		ssubl v13.2d, v14.2s, v3.2s
+0x~~~~~~~~~~~~~~~~  0e682205		ssubl v5.4s, v16.4h, v8.4h
+0x~~~~~~~~~~~~~~~~  0e262380		ssubl v0.8h, v28.8b, v6.8b
+0x~~~~~~~~~~~~~~~~  4eb921a5		ssubl2 v5.2d, v13.4s, v25.4s
+0x~~~~~~~~~~~~~~~~  4e7121e3		ssubl2 v3.4s, v15.8h, v17.8h
+0x~~~~~~~~~~~~~~~~  4e2e21ef		ssubl2 v15.8h, v15.16b, v14.16b
+0x~~~~~~~~~~~~~~~~  0eba32f9		ssubw v25.2d, v23.2d, v26.2s
+0x~~~~~~~~~~~~~~~~  0e783255		ssubw v21.4s, v18.4s, v24.4h
+0x~~~~~~~~~~~~~~~~  0e2332de		ssubw v30.8h, v22.8h, v3.8b
+0x~~~~~~~~~~~~~~~~  4ebc3310		ssubw2 v16.2d, v24.2d, v28.4s
+0x~~~~~~~~~~~~~~~~  4e6f317f		ssubw2 v31.4s, v11.4s, v15.8h
+0x~~~~~~~~~~~~~~~~  4e303104		ssubw2 v4.8h, v8.8h, v16.16b
+0x~~~~~~~~~~~~~~~~  4c002012		st1 {v18.16b, v19.16b, v20.16b, v21.16b}, [x0]
+0x~~~~~~~~~~~~~~~~  4c82202a		st1 {v10.16b, v11.16b, v12.16b, v13.16b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f203b		st1 {v27.16b, v28.16b, v29.16b, v30.16b}, [x1], #64
+0x~~~~~~~~~~~~~~~~  4c006010		st1 {v16.16b, v17.16b, v18.16b}, [x0]
+0x~~~~~~~~~~~~~~~~  4c826035		st1 {v21.16b, v22.16b, v23.16b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f6029		st1 {v9.16b, v10.16b, v11.16b}, [x1], #48
+0x~~~~~~~~~~~~~~~~  4c00a007		st1 {v7.16b, v8.16b}, [x0]
+0x~~~~~~~~~~~~~~~~  4c82a03a		st1 {v26.16b, v27.16b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9fa036		st1 {v22.16b, v23.16b}, [x1], #32
+0x~~~~~~~~~~~~~~~~  4c007017		st1 {v23.16b}, [x0]
+0x~~~~~~~~~~~~~~~~  4c82703c		st1 {v28.16b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f7022		st1 {v2.16b}, [x1], #16
+0x~~~~~~~~~~~~~~~~  0c002c1d		st1 {v29.1d, v30.1d, v31.1d, v0.1d}, [x0]
+0x~~~~~~~~~~~~~~~~  0c822c2c		st1 {v12.1d, v13.1d, v14.1d, v15.1d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f2c3e		st1 {v30.1d, v31.1d, v0.1d, v1.1d}, [x1], #32
+0x~~~~~~~~~~~~~~~~  0c006c10		st1 {v16.1d, v17.1d, v18.1d}, [x0]
+0x~~~~~~~~~~~~~~~~  0c826c23		st1 {v3.1d, v4.1d, v5.1d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f6c2e		st1 {v14.1d, v15.1d, v16.1d}, [x1], #24
+0x~~~~~~~~~~~~~~~~  0c00ac12		st1 {v18.1d, v19.1d}, [x0]
+0x~~~~~~~~~~~~~~~~  0c82ac25		st1 {v5.1d, v6.1d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9fac22		st1 {v2.1d, v3.1d}, [x1], #16
+0x~~~~~~~~~~~~~~~~  0c007c04		st1 {v4.1d}, [x0]
+0x~~~~~~~~~~~~~~~~  0c827c3b		st1 {v27.1d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f7c37		st1 {v23.1d}, [x1], #8
+0x~~~~~~~~~~~~~~~~  4c002c02		st1 {v2.2d, v3.2d, v4.2d, v5.2d}, [x0]
+0x~~~~~~~~~~~~~~~~  4c822c36		st1 {v22.2d, v23.2d, v24.2d, v25.2d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f2c3c		st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x1], #64
+0x~~~~~~~~~~~~~~~~  4c006c11		st1 {v17.2d, v18.2d, v19.2d}, [x0]
+0x~~~~~~~~~~~~~~~~  4c826c30		st1 {v16.2d, v17.2d, v18.2d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f6c36		st1 {v22.2d, v23.2d, v24.2d}, [x1], #48
+0x~~~~~~~~~~~~~~~~  4c00ac15		st1 {v21.2d, v22.2d}, [x0]
+0x~~~~~~~~~~~~~~~~  4c82ac26		st1 {v6.2d, v7.2d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9fac3b		st1 {v27.2d, v28.2d}, [x1], #32
+0x~~~~~~~~~~~~~~~~  4c007c15		st1 {v21.2d}, [x0]
+0x~~~~~~~~~~~~~~~~  4c827c3d		st1 {v29.2d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f7c34		st1 {v20.2d}, [x1], #16
+0x~~~~~~~~~~~~~~~~  0c002816		st1 {v22.2s, v23.2s, v24.2s, v25.2s}, [x0]
+0x~~~~~~~~~~~~~~~~  0c822828		st1 {v8.2s, v9.2s, v10.2s, v11.2s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f282f		st1 {v15.2s, v16.2s, v17.2s, v18.2s}, [x1], #32
+0x~~~~~~~~~~~~~~~~  0c006802		st1 {v2.2s, v3.2s, v4.2s}, [x0]
+0x~~~~~~~~~~~~~~~~  0c826837		st1 {v23.2s, v24.2s, v25.2s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f6827		st1 {v7.2s, v8.2s, v9.2s}, [x1], #24
+0x~~~~~~~~~~~~~~~~  0c00a81c		st1 {v28.2s, v29.2s}, [x0]
+0x~~~~~~~~~~~~~~~~  0c82a83d		st1 {v29.2s, v30.2s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9fa837		st1 {v23.2s, v24.2s}, [x1], #16
+0x~~~~~~~~~~~~~~~~  0c007806		st1 {v6.2s}, [x0]
+0x~~~~~~~~~~~~~~~~  0c82782b		st1 {v11.2s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f7831		st1 {v17.2s}, [x1], #8
+0x~~~~~~~~~~~~~~~~  0c002406		st1 {v6.4h, v7.4h, v8.4h, v9.4h}, [x0]
+0x~~~~~~~~~~~~~~~~  0c822429		st1 {v9.4h, v10.4h, v11.4h, v12.4h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f2439		st1 {v25.4h, v26.4h, v27.4h, v28.4h}, [x1], #32
+0x~~~~~~~~~~~~~~~~  0c00640b		st1 {v11.4h, v12.4h, v13.4h}, [x0]
+0x~~~~~~~~~~~~~~~~  0c82642a		st1 {v10.4h, v11.4h, v12.4h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f642c		st1 {v12.4h, v13.4h, v14.4h}, [x1], #24
+0x~~~~~~~~~~~~~~~~  0c00a40d		st1 {v13.4h, v14.4h}, [x0]
+0x~~~~~~~~~~~~~~~~  0c82a42f		st1 {v15.4h, v16.4h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9fa435		st1 {v21.4h, v22.4h}, [x1], #16
+0x~~~~~~~~~~~~~~~~  0c007410		st1 {v16.4h}, [x0]
+0x~~~~~~~~~~~~~~~~  0c827428		st1 {v8.4h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f743e		st1 {v30.4h}, [x1], #8
+0x~~~~~~~~~~~~~~~~  4c002803		st1 {v3.4s, v4.4s, v5.4s, v6.4s}, [x0]
+0x~~~~~~~~~~~~~~~~  4c822839		st1 {v25.4s, v26.4s, v27.4s, v28.4s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f2825		st1 {v5.4s, v6.4s, v7.4s, v8.4s}, [x1], #64
+0x~~~~~~~~~~~~~~~~  4c00681f		st1 {v31.4s, v0.4s, v1.4s}, [x0]
+0x~~~~~~~~~~~~~~~~  4c82683e		st1 {v30.4s, v31.4s, v0.4s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f6826		st1 {v6.4s, v7.4s, v8.4s}, [x1], #48
+0x~~~~~~~~~~~~~~~~  4c00a811		st1 {v17.4s, v18.4s}, [x0]
+0x~~~~~~~~~~~~~~~~  4c82a83f		st1 {v31.4s, v0.4s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9fa821		st1 {v1.4s, v2.4s}, [x1], #32
+0x~~~~~~~~~~~~~~~~  4c00781a		st1 {v26.4s}, [x0]
+0x~~~~~~~~~~~~~~~~  4c82782f		st1 {v15.4s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f782d		st1 {v13.4s}, [x1], #16
+0x~~~~~~~~~~~~~~~~  0c00201a		st1 {v26.8b, v27.8b, v28.8b, v29.8b}, [x0]
+0x~~~~~~~~~~~~~~~~  0c82202a		st1 {v10.8b, v11.8b, v12.8b, v13.8b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f202f		st1 {v15.8b, v16.8b, v17.8b, v18.8b}, [x1], #32
+0x~~~~~~~~~~~~~~~~  0c006013		st1 {v19.8b, v20.8b, v21.8b}, [x0]
+0x~~~~~~~~~~~~~~~~  0c82603f		st1 {v31.8b, v0.8b, v1.8b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f6029		st1 {v9.8b, v10.8b, v11.8b}, [x1], #24
+0x~~~~~~~~~~~~~~~~  0c00a00c		st1 {v12.8b, v13.8b}, [x0]
+0x~~~~~~~~~~~~~~~~  0c82a022		st1 {v2.8b, v3.8b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9fa020		st1 {v0.8b, v1.8b}, [x1], #16
+0x~~~~~~~~~~~~~~~~  0c007010		st1 {v16.8b}, [x0]
+0x~~~~~~~~~~~~~~~~  0c827039		st1 {v25.8b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f703f		st1 {v31.8b}, [x1], #8
+0x~~~~~~~~~~~~~~~~  4c002404		st1 {v4.8h, v5.8h, v6.8h, v7.8h}, [x0]
+0x~~~~~~~~~~~~~~~~  4c822423		st1 {v3.8h, v4.8h, v5.8h, v6.8h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f243a		st1 {v26.8h, v27.8h, v28.8h, v29.8h}, [x1], #64
+0x~~~~~~~~~~~~~~~~  4c00640a		st1 {v10.8h, v11.8h, v12.8h}, [x0]
+0x~~~~~~~~~~~~~~~~  4c826435		st1 {v21.8h, v22.8h, v23.8h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f6432		st1 {v18.8h, v19.8h, v20.8h}, [x1], #48
+0x~~~~~~~~~~~~~~~~  4c00a41a		st1 {v26.8h, v27.8h}, [x0]
+0x~~~~~~~~~~~~~~~~  4c82a438		st1 {v24.8h, v25.8h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9fa431		st1 {v17.8h, v18.8h}, [x1], #32
+0x~~~~~~~~~~~~~~~~  4c00741d		st1 {v29.8h}, [x0]
+0x~~~~~~~~~~~~~~~~  4c827433		st1 {v19.8h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f7437		st1 {v23.8h}, [x1], #16
+0x~~~~~~~~~~~~~~~~  4d001c13		st1 {v19.b}[15], [x0]
+0x~~~~~~~~~~~~~~~~  4d820439		st1 {v25.b}[9], [x1], x2
+0x~~~~~~~~~~~~~~~~  4d9f0024		st1 {v4.b}[8], [x1], #1
+0x~~~~~~~~~~~~~~~~  0d00840d		st1 {v13.d}[0], [x0]
+0x~~~~~~~~~~~~~~~~  0d82843e		st1 {v30.d}[0], [x1], x2
+0x~~~~~~~~~~~~~~~~  0d9f8423		st1 {v3.d}[0], [x1], #8
+0x~~~~~~~~~~~~~~~~  0d004016		st1 {v22.h}[0], [x0]
+0x~~~~~~~~~~~~~~~~  4d82583f		st1 {v31.h}[7], [x1], x2
+0x~~~~~~~~~~~~~~~~  0d9f5837		st1 {v23.h}[3], [x1], #2
+0x~~~~~~~~~~~~~~~~  0d008000		st1 {v0.s}[0], [x0]
+0x~~~~~~~~~~~~~~~~  4d82902b		st1 {v11.s}[3], [x1], x2
+0x~~~~~~~~~~~~~~~~  4d9f9038		st1 {v24.s}[3], [x1], #4
+0x~~~~~~~~~~~~~~~~  4c008007		st2 {v7.16b, v8.16b}, [x0]
+0x~~~~~~~~~~~~~~~~  4c828025		st2 {v5.16b, v6.16b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f8032		st2 {v18.16b, v19.16b}, [x1], #32
+0x~~~~~~~~~~~~~~~~  4c008c0e		st2 {v14.2d, v15.2d}, [x0]
+0x~~~~~~~~~~~~~~~~  4c828c27		st2 {v7.2d, v8.2d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f8c38		st2 {v24.2d, v25.2d}, [x1], #32
+0x~~~~~~~~~~~~~~~~  0c008816		st2 {v22.2s, v23.2s}, [x0]
+0x~~~~~~~~~~~~~~~~  0c828824		st2 {v4.2s, v5.2s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f8822		st2 {v2.2s, v3.2s}, [x1], #16
+0x~~~~~~~~~~~~~~~~  0c008417		st2 {v23.4h, v24.4h}, [x0]
+0x~~~~~~~~~~~~~~~~  0c828428		st2 {v8.4h, v9.4h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f8427		st2 {v7.4h, v8.4h}, [x1], #16
+0x~~~~~~~~~~~~~~~~  4c008811		st2 {v17.4s, v18.4s}, [x0]
+0x~~~~~~~~~~~~~~~~  4c828826		st2 {v6.4s, v7.4s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f883a		st2 {v26.4s, v27.4s}, [x1], #32
+0x~~~~~~~~~~~~~~~~  0c00801f		st2 {v31.8b, v0.8b}, [x0]
+0x~~~~~~~~~~~~~~~~  0c828020		st2 {v0.8b, v1.8b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f8035		st2 {v21.8b, v22.8b}, [x1], #16
+0x~~~~~~~~~~~~~~~~  4c008407		st2 {v7.8h, v8.8h}, [x0]
+0x~~~~~~~~~~~~~~~~  4c828436		st2 {v22.8h, v23.8h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f8424		st2 {v4.8h, v5.8h}, [x1], #32
+0x~~~~~~~~~~~~~~~~  4d201c08		st2 {v8.b, v9.b}[15], [x0]
+0x~~~~~~~~~~~~~~~~  4da21c28		st2 {v8.b, v9.b}[15], [x1], x2
+0x~~~~~~~~~~~~~~~~  0dbf1027		st2 {v7.b, v8.b}[4], [x1], #2
+0x~~~~~~~~~~~~~~~~  0d208419		st2 {v25.d, v26.d}[0], [x0]
+0x~~~~~~~~~~~~~~~~  4da28431		st2 {v17.d, v18.d}[1], [x1], x2
+0x~~~~~~~~~~~~~~~~  4dbf8423		st2 {v3.d, v4.d}[1], [x1], #16
+0x~~~~~~~~~~~~~~~~  0d205804		st2 {v4.h, v5.h}[3], [x0]
+0x~~~~~~~~~~~~~~~~  4da24820		st2 {v0.h, v1.h}[5], [x1], x2
+0x~~~~~~~~~~~~~~~~  0dbf5036		st2 {v22.h, v23.h}[2], [x1], #4
+0x~~~~~~~~~~~~~~~~  4d20900e		st2 {v14.s, v15.s}[3], [x0]
+0x~~~~~~~~~~~~~~~~  4da29037		st2 {v23.s, v24.s}[3], [x1], x2
+0x~~~~~~~~~~~~~~~~  4dbf8020		st2 {v0.s, v1.s}[2], [x1], #8
+0x~~~~~~~~~~~~~~~~  4c00401a		st3 {v26.16b, v27.16b, v28.16b}, [x0]
+0x~~~~~~~~~~~~~~~~  4c824035		st3 {v21.16b, v22.16b, v23.16b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f4038		st3 {v24.16b, v25.16b, v26.16b}, [x1], #48
+0x~~~~~~~~~~~~~~~~  4c004c11		st3 {v17.2d, v18.2d, v19.2d}, [x0]
+0x~~~~~~~~~~~~~~~~  4c824c37		st3 {v23.2d, v24.2d, v25.2d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f4c2a		st3 {v10.2d, v11.2d, v12.2d}, [x1], #48
+0x~~~~~~~~~~~~~~~~  0c004809		st3 {v9.2s, v10.2s, v11.2s}, [x0]
+0x~~~~~~~~~~~~~~~~  0c82482d		st3 {v13.2s, v14.2s, v15.2s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f4836		st3 {v22.2s, v23.2s, v24.2s}, [x1], #24
+0x~~~~~~~~~~~~~~~~  0c00441f		st3 {v31.4h, v0.4h, v1.4h}, [x0]
+0x~~~~~~~~~~~~~~~~  0c824428		st3 {v8.4h, v9.4h, v10.4h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f4433		st3 {v19.4h, v20.4h, v21.4h}, [x1], #24
+0x~~~~~~~~~~~~~~~~  4c004812		st3 {v18.4s, v19.4s, v20.4s}, [x0]
+0x~~~~~~~~~~~~~~~~  4c824839		st3 {v25.4s, v26.4s, v27.4s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f4830		st3 {v16.4s, v17.4s, v18.4s}, [x1], #48
+0x~~~~~~~~~~~~~~~~  0c00401b		st3 {v27.8b, v28.8b, v29.8b}, [x0]
+0x~~~~~~~~~~~~~~~~  0c82403d		st3 {v29.8b, v30.8b, v31.8b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f403e		st3 {v30.8b, v31.8b, v0.8b}, [x1], #24
+0x~~~~~~~~~~~~~~~~  4c004408		st3 {v8.8h, v9.8h, v10.8h}, [x0]
+0x~~~~~~~~~~~~~~~~  4c824432		st3 {v18.8h, v19.8h, v20.8h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f4432		st3 {v18.8h, v19.8h, v20.8h}, [x1], #48
+0x~~~~~~~~~~~~~~~~  4d00281f		st3 {v31.b, v0.b, v1.b}[10], [x0]
+0x~~~~~~~~~~~~~~~~  0d823424		st3 {v4.b, v5.b, v6.b}[5], [x1], x2
+0x~~~~~~~~~~~~~~~~  0d9f2425		st3 {v5.b, v6.b, v7.b}[1], [x1], #3
+0x~~~~~~~~~~~~~~~~  0d00a405		st3 {v5.d, v6.d, v7.d}[0], [x0]
+0x~~~~~~~~~~~~~~~~  0d82a426		st3 {v6.d, v7.d, v8.d}[0], [x1], x2
+0x~~~~~~~~~~~~~~~~  0d9fa420		st3 {v0.d, v1.d, v2.d}[0], [x1], #24
+0x~~~~~~~~~~~~~~~~  0d00701f		st3 {v31.h, v0.h, v1.h}[2], [x0]
+0x~~~~~~~~~~~~~~~~  4d82682e		st3 {v14.h, v15.h, v16.h}[5], [x1], x2
+0x~~~~~~~~~~~~~~~~  4d9f7035		st3 {v21.h, v22.h, v23.h}[6], [x1], #6
+0x~~~~~~~~~~~~~~~~  0d00a015		st3 {v21.s, v22.s, v23.s}[0], [x0]
+0x~~~~~~~~~~~~~~~~  0d82b02b		st3 {v11.s, v12.s, v13.s}[1], [x1], x2
+0x~~~~~~~~~~~~~~~~  0d9fa02f		st3 {v15.s, v16.s, v17.s}[0], [x1], #12
+0x~~~~~~~~~~~~~~~~  4c000016		st4 {v22.16b, v23.16b, v24.16b, v25.16b}, [x0]
+0x~~~~~~~~~~~~~~~~  4c820038		st4 {v24.16b, v25.16b, v26.16b, v27.16b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f002f		st4 {v15.16b, v16.16b, v17.16b, v18.16b}, [x1], #64
+0x~~~~~~~~~~~~~~~~  4c000c10		st4 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0]
+0x~~~~~~~~~~~~~~~~  4c820c31		st4 {v17.2d, v18.2d, v19.2d, v20.2d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f0c29		st4 {v9.2d, v10.2d, v11.2d, v12.2d}, [x1], #64
+0x~~~~~~~~~~~~~~~~  0c000817		st4 {v23.2s, v24.2s, v25.2s, v26.2s}, [x0]
+0x~~~~~~~~~~~~~~~~  0c82082f		st4 {v15.2s, v16.2s, v17.2s, v18.2s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f0838		st4 {v24.2s, v25.2s, v26.2s, v27.2s}, [x1], #32
+0x~~~~~~~~~~~~~~~~  0c00040e		st4 {v14.4h, v15.4h, v16.4h, v17.4h}, [x0]
+0x~~~~~~~~~~~~~~~~  0c820432		st4 {v18.4h, v19.4h, v20.4h, v21.4h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f0421		st4 {v1.4h, v2.4h, v3.4h, v4.4h}, [x1], #32
+0x~~~~~~~~~~~~~~~~  4c00080d		st4 {v13.4s, v14.4s, v15.4s, v16.4s}, [x0]
+0x~~~~~~~~~~~~~~~~  4c820826		st4 {v6.4s, v7.4s, v8.4s, v9.4s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f082f		st4 {v15.4s, v16.4s, v17.4s, v18.4s}, [x1], #64
+0x~~~~~~~~~~~~~~~~  0c00001a		st4 {v26.8b, v27.8b, v28.8b, v29.8b}, [x0]
+0x~~~~~~~~~~~~~~~~  0c820039		st4 {v25.8b, v26.8b, v27.8b, v28.8b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f0033		st4 {v19.8b, v20.8b, v21.8b, v22.8b}, [x1], #32
+0x~~~~~~~~~~~~~~~~  4c000413		st4 {v19.8h, v20.8h, v21.8h, v22.8h}, [x0]
+0x~~~~~~~~~~~~~~~~  4c82042f		st4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f043f		st4 {v31.8h, v0.8h, v1.8h, v2.8h}, [x1], #64
+0x~~~~~~~~~~~~~~~~  4d203400		st4 {v0.b, v1.b, v2.b, v3.b}[13], [x0]
+0x~~~~~~~~~~~~~~~~  4da22824		st4 {v4.b, v5.b, v6.b, v7.b}[10], [x1], x2
+0x~~~~~~~~~~~~~~~~  4dbf2429		st4 {v9.b, v10.b, v11.b, v12.b}[9], [x1], #4
+0x~~~~~~~~~~~~~~~~  4d20a402		st4 {v2.d, v3.d, v4.d, v5.d}[1], [x0]
+0x~~~~~~~~~~~~~~~~  0da2a427		st4 {v7.d, v8.d, v9.d, v10.d}[0], [x1], x2
+0x~~~~~~~~~~~~~~~~  4dbfa43f		st4 {v31.d, v0.d, v1.d, v2.d}[1], [x1], #32
+0x~~~~~~~~~~~~~~~~  0d206802		st4 {v2.h, v3.h, v4.h, v5.h}[1], [x0]
+0x~~~~~~~~~~~~~~~~  0da2783b		st4 {v27.h, v28.h, v29.h, v30.h}[3], [x1], x2
+0x~~~~~~~~~~~~~~~~  4dbf6038		st4 {v24.h, v25.h, v26.h, v27.h}[4], [x1], #8
+0x~~~~~~~~~~~~~~~~  4d20a012		st4 {v18.s, v19.s, v20.s, v21.s}[2], [x0]
+0x~~~~~~~~~~~~~~~~  4da2a026		st4 {v6.s, v7.s, v8.s, v9.s}[2], [x1], x2
+0x~~~~~~~~~~~~~~~~  0dbfb039		st4 {v25.s, v26.s, v27.s, v28.s}[1], [x1], #16
+0x~~~~~~~~~~~~~~~~  7ee2862c		sub d12, d17, d2
+0x~~~~~~~~~~~~~~~~  6e288714		sub v20.16b, v24.16b, v8.16b
+0x~~~~~~~~~~~~~~~~  6ee587a8		sub v8.2d, v29.2d, v5.2d
+0x~~~~~~~~~~~~~~~~  2eb88782		sub v2.2s, v28.2s, v24.2s
+0x~~~~~~~~~~~~~~~~  2e648558		sub v24.4h, v10.4h, v4.4h
+0x~~~~~~~~~~~~~~~~  6eb1849c		sub v28.4s, v4.4s, v17.4s
+0x~~~~~~~~~~~~~~~~  2e228770		sub v16.8b, v27.8b, v2.8b
+0x~~~~~~~~~~~~~~~~  6e6d8554		sub v20.8h, v10.8h, v13.8h
+0x~~~~~~~~~~~~~~~~  0ead61c5		subhn v5.2s, v14.2d, v13.2d
+0x~~~~~~~~~~~~~~~~  0e6860aa		subhn v10.4h, v5.4s, v8.4s
+0x~~~~~~~~~~~~~~~~  0e366146		subhn v6.8b, v10.8h, v22.8h
+0x~~~~~~~~~~~~~~~~  4e2960cb		subhn2 v11.16b, v6.8h, v9.8h
+0x~~~~~~~~~~~~~~~~  4eb86259		subhn2 v25.4s, v18.2d, v24.2d
+0x~~~~~~~~~~~~~~~~  4e6162b4		subhn2 v20.8h, v21.4s, v1.4s
+0x~~~~~~~~~~~~~~~~  5e203979		suqadd b25, b11
+0x~~~~~~~~~~~~~~~~  5ee0382d		suqadd d13, d1
+0x~~~~~~~~~~~~~~~~  5e603920		suqadd h0, h9
+0x~~~~~~~~~~~~~~~~  5ea03916		suqadd s22, s8
+0x~~~~~~~~~~~~~~~~  4e203b78		suqadd v24.16b, v27.16b
+0x~~~~~~~~~~~~~~~~  4ee039da		suqadd v26.2d, v14.2d
+0x~~~~~~~~~~~~~~~~  0ea03947		suqadd v7.2s, v10.2s
+0x~~~~~~~~~~~~~~~~  0e603999		suqadd v25.4h, v12.4h
+0x~~~~~~~~~~~~~~~~  4ea03864		suqadd v4.4s, v3.4s
+0x~~~~~~~~~~~~~~~~  0e203a4e		suqadd v14.8b, v18.8b
+0x~~~~~~~~~~~~~~~~  4e60391f		suqadd v31.8h, v8.8h
+0x~~~~~~~~~~~~~~~~  0f20a690		sxtl v16.2d, v20.2s
+0x~~~~~~~~~~~~~~~~  0f10a79b		sxtl v27.4s, v28.4h
+0x~~~~~~~~~~~~~~~~  0f08a6c0		sxtl v0.8h, v22.8b
+0x~~~~~~~~~~~~~~~~  4f20a4e6		sxtl2 v6.2d, v7.4s
+0x~~~~~~~~~~~~~~~~  4f10a769		sxtl2 v9.4s, v27.8h
+0x~~~~~~~~~~~~~~~~  4f08a610		sxtl2 v16.8h, v16.16b
+0x~~~~~~~~~~~~~~~~  4e166239		tbl v25.16b, {v17.16b, v18.16b, v19.16b, v20.16b}, v22.16b
+0x~~~~~~~~~~~~~~~~  4e0441bc		tbl v28.16b, {v13.16b, v14.16b, v15.16b}, v4.16b
+0x~~~~~~~~~~~~~~~~  4e022003		tbl v3.16b, {v0.16b, v1.16b}, v2.16b
+0x~~~~~~~~~~~~~~~~  4e0401f4		tbl v20.16b, {v15.16b}, v4.16b
+0x~~~~~~~~~~~~~~~~  0e1462e7		tbl v7.8b, {v23.16b, v24.16b, v25.16b, v26.16b}, v20.8b
+0x~~~~~~~~~~~~~~~~  0e1f4028		tbl v8.8b, {v1.16b, v2.16b, v3.16b}, v31.8b
+0x~~~~~~~~~~~~~~~~  0e102328		tbl v8.8b, {v25.16b, v26.16b}, v16.8b
+0x~~~~~~~~~~~~~~~~  0e1e026b		tbl v11.8b, {v19.16b}, v30.8b
+0x~~~~~~~~~~~~~~~~  4e057339		tbx v25.16b, {v25.16b, v26.16b, v27.16b, v28.16b}, v5.16b
+0x~~~~~~~~~~~~~~~~  4e1853b5		tbx v21.16b, {v29.16b, v30.16b, v31.16b}, v24.16b
+0x~~~~~~~~~~~~~~~~  4e013206		tbx v6.16b, {v16.16b, v17.16b}, v1.16b
+0x~~~~~~~~~~~~~~~~  4e14106d		tbx v13.16b, {v3.16b}, v20.16b
+0x~~~~~~~~~~~~~~~~  0e0973b8		tbx v24.8b, {v29.16b, v30.16b, v31.16b, v0.16b}, v9.8b
+0x~~~~~~~~~~~~~~~~  0e1a5131		tbx v17.8b, {v9.16b, v10.16b, v11.16b}, v26.8b
+0x~~~~~~~~~~~~~~~~  0e153065		tbx v5.8b, {v3.16b, v4.16b}, v21.8b
+0x~~~~~~~~~~~~~~~~  0e1d1170		tbx v16.8b, {v11.16b}, v29.8b
+0x~~~~~~~~~~~~~~~~  4e0c2b13		trn1 v19.16b, v24.16b, v12.16b
+0x~~~~~~~~~~~~~~~~  4eca28e2		trn1 v2.2d, v7.2d, v10.2d
+0x~~~~~~~~~~~~~~~~  0e952816		trn1 v22.2s, v0.2s, v21.2s
+0x~~~~~~~~~~~~~~~~  0e5429ec		trn1 v12.4h, v15.4h, v20.4h
+0x~~~~~~~~~~~~~~~~  4e892a3e		trn1 v30.4s, v17.4s, v9.4s
+0x~~~~~~~~~~~~~~~~  0e1d2a6c		trn1 v12.8b, v19.8b, v29.8b
+0x~~~~~~~~~~~~~~~~  4e492917		trn1 v23.8h, v8.8h, v9.8h
+0x~~~~~~~~~~~~~~~~  4e196bdc		trn2 v28.16b, v30.16b, v25.16b
+0x~~~~~~~~~~~~~~~~  4ec76b67		trn2 v7.2d, v27.2d, v7.2d
+0x~~~~~~~~~~~~~~~~  0e936a1e		trn2 v30.2s, v16.2s, v19.2s
+0x~~~~~~~~~~~~~~~~  0e5968d8		trn2 v24.4h, v6.4h, v25.4h
+0x~~~~~~~~~~~~~~~~  4e8b6a62		trn2 v2.4s, v19.4s, v11.4s
+0x~~~~~~~~~~~~~~~~  0e126b79		trn2 v25.8b, v27.8b, v18.8b
+0x~~~~~~~~~~~~~~~~  4e4f688c		trn2 v12.8h, v4.8h, v15.8h
+0x~~~~~~~~~~~~~~~~  6e3c7d9f		uaba v31.16b, v12.16b, v28.16b
+0x~~~~~~~~~~~~~~~~  2eae7cb2		uaba v18.2s, v5.2s, v14.2s
+0x~~~~~~~~~~~~~~~~  2e757e89		uaba v9.4h, v20.4h, v21.4h
+0x~~~~~~~~~~~~~~~~  6ea27e86		uaba v6.4s, v20.4s, v2.4s
+0x~~~~~~~~~~~~~~~~  2e257d90		uaba v16.8b, v12.8b, v5.8b
+0x~~~~~~~~~~~~~~~~  6e7e7f4f		uaba v15.8h, v26.8h, v30.8h
+0x~~~~~~~~~~~~~~~~  2eaf524a		uabal v10.2d, v18.2s, v15.2s
+0x~~~~~~~~~~~~~~~~  2e67527e		uabal v30.4s, v19.4h, v7.4h
+0x~~~~~~~~~~~~~~~~  2e205364		uabal v4.8h, v27.8b, v0.8b
+0x~~~~~~~~~~~~~~~~  6ea25193		uabal2 v19.2d, v12.4s, v2.4s
+0x~~~~~~~~~~~~~~~~  6e6c50ba		uabal2 v26.4s, v5.8h, v12.8h
+0x~~~~~~~~~~~~~~~~  6e3c5293		uabal2 v19.8h, v20.16b, v28.16b
+0x~~~~~~~~~~~~~~~~  6e357492		uabd v18.16b, v4.16b, v21.16b
+0x~~~~~~~~~~~~~~~~  2eb076be		uabd v30.2s, v21.2s, v16.2s
+0x~~~~~~~~~~~~~~~~  2e797788		uabd v8.4h, v28.4h, v25.4h
+0x~~~~~~~~~~~~~~~~  6eb5759c		uabd v28.4s, v12.4s, v21.4s
+0x~~~~~~~~~~~~~~~~  2e3c7613		uabd v19.8b, v16.8b, v28.8b
+0x~~~~~~~~~~~~~~~~  6e7d7589		uabd v9.8h, v12.8h, v29.8h
+0x~~~~~~~~~~~~~~~~  2ea8701a		uabdl v26.2d, v0.2s, v8.2s
+0x~~~~~~~~~~~~~~~~  2e7973fd		uabdl v29.4s, v31.4h, v25.4h
+0x~~~~~~~~~~~~~~~~  2e2e73bb		uabdl v27.8h, v29.8b, v14.8b
+0x~~~~~~~~~~~~~~~~  6ea87294		uabdl2 v20.2d, v20.4s, v8.4s
+0x~~~~~~~~~~~~~~~~  6e7271f6		uabdl2 v22.4s, v15.8h, v18.8h
+0x~~~~~~~~~~~~~~~~  6e377249		uabdl2 v9.8h, v18.16b, v23.16b
+0x~~~~~~~~~~~~~~~~  2ea069e9		uadalp v9.1d, v15.2s
+0x~~~~~~~~~~~~~~~~  6ea0698e		uadalp v14.2d, v12.4s
+0x~~~~~~~~~~~~~~~~  2e60699c		uadalp v28.2s, v12.4h
+0x~~~~~~~~~~~~~~~~  2e206a20		uadalp v0.4h, v17.8b
+0x~~~~~~~~~~~~~~~~  6e606ba1		uadalp v1.4s, v29.8h
+0x~~~~~~~~~~~~~~~~  6e206acf		uadalp v15.8h, v22.16b
+0x~~~~~~~~~~~~~~~~  2ebb0281		uaddl v1.2d, v20.2s, v27.2s
+0x~~~~~~~~~~~~~~~~  2e65033f		uaddl v31.4s, v25.4h, v5.4h
+0x~~~~~~~~~~~~~~~~  2e23006c		uaddl v12.8h, v3.8b, v3.8b
+0x~~~~~~~~~~~~~~~~  6ea602e5		uaddl2 v5.2d, v23.4s, v6.4s
+0x~~~~~~~~~~~~~~~~  6e7900a1		uaddl2 v1.4s, v5.8h, v25.8h
+0x~~~~~~~~~~~~~~~~  6e3c03d6		uaddl2 v22.8h, v30.16b, v28.16b
+0x~~~~~~~~~~~~~~~~  2ea02927		uaddlp v7.1d, v9.2s
+0x~~~~~~~~~~~~~~~~  6ea0289a		uaddlp v26.2d, v4.4s
+0x~~~~~~~~~~~~~~~~  2e60283c		uaddlp v28.2s, v1.4h
+0x~~~~~~~~~~~~~~~~  2e202bf4		uaddlp v20.4h, v31.8b
+0x~~~~~~~~~~~~~~~~  6e602a30		uaddlp v16.4s, v17.8h
+0x~~~~~~~~~~~~~~~~  6e202846		uaddlp v6.8h, v2.16b
+0x~~~~~~~~~~~~~~~~  6eb03adc		uaddlv d28, v22.4s
+0x~~~~~~~~~~~~~~~~  6e303a60		uaddlv h0, v19.16b
+0x~~~~~~~~~~~~~~~~  2e303bde		uaddlv h30, v30.8b
+0x~~~~~~~~~~~~~~~~  2e703a58		uaddlv s24, v18.4h
+0x~~~~~~~~~~~~~~~~  6e70380a		uaddlv s10, v0.8h
+0x~~~~~~~~~~~~~~~~  2eae1229		uaddw v9.2d, v17.2d, v14.2s
+0x~~~~~~~~~~~~~~~~  2e631329		uaddw v9.4s, v25.4s, v3.4h
+0x~~~~~~~~~~~~~~~~  2e201032		uaddw v18.8h, v1.8h, v0.8b
+0x~~~~~~~~~~~~~~~~  6ea610b2		uaddw2 v18.2d, v5.2d, v6.4s
+0x~~~~~~~~~~~~~~~~  6e6b11f1		uaddw2 v17.4s, v15.4s, v11.8h
+0x~~~~~~~~~~~~~~~~  6e27117d		uaddw2 v29.8h, v11.8h, v7.16b
+0x~~~~~~~~~~~~~~~~  6e23052d		uhadd v13.16b, v9.16b, v3.16b
+0x~~~~~~~~~~~~~~~~  2eb80731		uhadd v17.2s, v25.2s, v24.2s
+0x~~~~~~~~~~~~~~~~  2e6d06f9		uhadd v25.4h, v23.4h, v13.4h
+0x~~~~~~~~~~~~~~~~  6eb00680		uhadd v0.4s, v20.4s, v16.4s
+0x~~~~~~~~~~~~~~~~  2e3904a5		uhadd v5.8b, v5.8b, v25.8b
+0x~~~~~~~~~~~~~~~~  6e7207a3		uhadd v3.8h, v29.8h, v18.8h
+0x~~~~~~~~~~~~~~~~  6e2d26c1		uhsub v1.16b, v22.16b, v13.16b
+0x~~~~~~~~~~~~~~~~  2ebe27ce		uhsub v14.2s, v30.2s, v30.2s
+0x~~~~~~~~~~~~~~~~  2e7125dd		uhsub v29.4h, v14.4h, v17.4h
+0x~~~~~~~~~~~~~~~~  6eb224ba		uhsub v26.4s, v5.4s, v18.4s
+0x~~~~~~~~~~~~~~~~  2e2c24e3		uhsub v3.8b, v7.8b, v12.8b
+0x~~~~~~~~~~~~~~~~  6e6526b9		uhsub v25.8h, v21.8h, v5.8h
+0x~~~~~~~~~~~~~~~~  6e26659c		umax v28.16b, v12.16b, v6.16b
+0x~~~~~~~~~~~~~~~~  2eba6674		umax v20.2s, v19.2s, v26.2s
+0x~~~~~~~~~~~~~~~~  2e7267e0		umax v0.4h, v31.4h, v18.4h
+0x~~~~~~~~~~~~~~~~  6ebc66a6		umax v6.4s, v21.4s, v28.4s
+0x~~~~~~~~~~~~~~~~  2e346440		umax v0.8b, v2.8b, v20.8b
+0x~~~~~~~~~~~~~~~~  6e766564		umax v4.8h, v11.8h, v22.8h
+0x~~~~~~~~~~~~~~~~  6e3da4c1		umaxp v1.16b, v6.16b, v29.16b
+0x~~~~~~~~~~~~~~~~  2ebba633		umaxp v19.2s, v17.2s, v27.2s
+0x~~~~~~~~~~~~~~~~  2e67a615		umaxp v21.4h, v16.4h, v7.4h
+0x~~~~~~~~~~~~~~~~  6ebda689		umaxp v9.4s, v20.4s, v29.4s
+0x~~~~~~~~~~~~~~~~  2e30a42d		umaxp v13.8b, v1.8b, v16.8b
+0x~~~~~~~~~~~~~~~~  6e7aa6f3		umaxp v19.8h, v23.8h, v26.8h
+0x~~~~~~~~~~~~~~~~  6e30abd1		umaxv b17, v30.16b
+0x~~~~~~~~~~~~~~~~  2e30a997		umaxv b23, v12.8b
+0x~~~~~~~~~~~~~~~~  2e70a9ff		umaxv h31, v15.4h
+0x~~~~~~~~~~~~~~~~  6e70ab2f		umaxv h15, v25.8h
+0x~~~~~~~~~~~~~~~~  6eb0aab2		umaxv s18, v21.4s
+0x~~~~~~~~~~~~~~~~  6e326c16		umin v22.16b, v0.16b, v18.16b
+0x~~~~~~~~~~~~~~~~  2eb06ea1		umin v1.2s, v21.2s, v16.2s
+0x~~~~~~~~~~~~~~~~  2e796c91		umin v17.4h, v4.4h, v25.4h
+0x~~~~~~~~~~~~~~~~  6ead6f58		umin v24.4s, v26.4s, v13.4s
+0x~~~~~~~~~~~~~~~~  2e256c34		umin v20.8b, v1.8b, v5.8b
+0x~~~~~~~~~~~~~~~~  6e776f3a		umin v26.8h, v25.8h, v23.8h
+0x~~~~~~~~~~~~~~~~  6e37ac25		uminp v5.16b, v1.16b, v23.16b
+0x~~~~~~~~~~~~~~~~  2ebeaf47		uminp v7.2s, v26.2s, v30.2s
+0x~~~~~~~~~~~~~~~~  2e79aca9		uminp v9.4h, v5.4h, v25.4h
+0x~~~~~~~~~~~~~~~~  6ea1ad57		uminp v23.4s, v10.4s, v1.4s
+0x~~~~~~~~~~~~~~~~  2e2eafa4		uminp v4.8b, v29.8b, v14.8b
+0x~~~~~~~~~~~~~~~~  6e6eac15		uminp v21.8h, v0.8h, v14.8h
+0x~~~~~~~~~~~~~~~~  6e31aa20		uminv b0, v17.16b
+0x~~~~~~~~~~~~~~~~  2e31abe0		uminv b0, v31.8b
+0x~~~~~~~~~~~~~~~~  2e71a818		uminv h24, v0.4h
+0x~~~~~~~~~~~~~~~~  6e71a9dd		uminv h29, v14.8h
+0x~~~~~~~~~~~~~~~~  6eb1a87e		uminv s30, v3.4s
+0x~~~~~~~~~~~~~~~~  2eb8816b		umlal v11.2d, v11.2s, v24.2s
+0x~~~~~~~~~~~~~~~~  2fab2a1e		umlal v30.2d, v16.2s, v11.s[3]
+0x~~~~~~~~~~~~~~~~  2e7a8120		umlal v0.4s, v9.4h, v26.4h
+0x~~~~~~~~~~~~~~~~  2f4c2b14		umlal v20.4s, v24.4h, v12.h[4]
+0x~~~~~~~~~~~~~~~~  2e2682b0		umlal v16.8h, v21.8b, v6.8b
+0x~~~~~~~~~~~~~~~~  6eb78271		umlal2 v17.2d, v19.4s, v23.4s
+0x~~~~~~~~~~~~~~~~  6f8823c5		umlal2 v5.2d, v30.4s, v8.s[0]
+0x~~~~~~~~~~~~~~~~  6e6f8110		umlal2 v16.4s, v8.8h, v15.8h
+0x~~~~~~~~~~~~~~~~  6f512b4f		umlal2 v15.4s, v26.8h, v1.h[5]
+0x~~~~~~~~~~~~~~~~  6e31803e		umlal2 v30.8h, v1.16b, v17.16b
+0x~~~~~~~~~~~~~~~~  2ebca272		umlsl v18.2d, v19.2s, v28.2s
+0x~~~~~~~~~~~~~~~~  2f8860e7		umlsl v7.2d, v7.2s, v8.s[0]
+0x~~~~~~~~~~~~~~~~  2e64a118		umlsl v24.4s, v8.4h, v4.4h
+0x~~~~~~~~~~~~~~~~  2f4c6ad2		umlsl v18.4s, v22.4h, v12.h[4]
+0x~~~~~~~~~~~~~~~~  2e34a1dc		umlsl v28.8h, v14.8b, v20.8b
+0x~~~~~~~~~~~~~~~~  6ea9a00b		umlsl2 v11.2d, v0.4s, v9.4s
+0x~~~~~~~~~~~~~~~~  6f896a1a		umlsl2 v26.2d, v16.4s, v9.s[2]
+0x~~~~~~~~~~~~~~~~  6e69a163		umlsl2 v3.4s, v11.8h, v9.8h
+0x~~~~~~~~~~~~~~~~  6f496b2a		umlsl2 v10.4s, v25.8h, v9.h[4]
+0x~~~~~~~~~~~~~~~~  6e3ca218		umlsl2 v24.8h, v16.16b, v28.16b
+0x~~~~~~~~~~~~~~~~  4e183f3e		mov x30, v25.d[1]
+0x~~~~~~~~~~~~~~~~  2ebdc14c		umull v12.2d, v10.2s, v29.2s
+0x~~~~~~~~~~~~~~~~  2fa5abd6		umull v22.2d, v30.2s, v5.s[3]
+0x~~~~~~~~~~~~~~~~  2e79c007		umull v7.4s, v0.4h, v25.4h
+0x~~~~~~~~~~~~~~~~  2f63a1ab		umull v11.4s, v13.4h, v3.h[2]
+0x~~~~~~~~~~~~~~~~  2e2ac219		umull v25.8h, v16.8b, v10.8b
+0x~~~~~~~~~~~~~~~~  6ebac071		umull2 v17.2d, v3.4s, v26.4s
+0x~~~~~~~~~~~~~~~~  6fa2a97a		umull2 v26.2d, v11.4s, v2.s[3]
+0x~~~~~~~~~~~~~~~~  6e77c22c		umull2 v12.4s, v17.8h, v23.8h
+0x~~~~~~~~~~~~~~~~  6f61a3e4		umull2 v4.4s, v31.8h, v1.h[2]
+0x~~~~~~~~~~~~~~~~  6e31c185		umull2 v5.8h, v12.16b, v17.16b
+0x~~~~~~~~~~~~~~~~  7e3c0c9e		uqadd b30, b4, b28
+0x~~~~~~~~~~~~~~~~  7ef00e9b		uqadd d27, d20, d16
+0x~~~~~~~~~~~~~~~~  7e7c0dc7		uqadd h7, h14, h28
+0x~~~~~~~~~~~~~~~~  7ea40e3c		uqadd s28, s17, s4
+0x~~~~~~~~~~~~~~~~  6e350ed3		uqadd v19.16b, v22.16b, v21.16b
+0x~~~~~~~~~~~~~~~~  6eeb0c90		uqadd v16.2d, v4.2d, v11.2d
+0x~~~~~~~~~~~~~~~~  2ea40dd4		uqadd v20.2s, v14.2s, v4.2s
+0x~~~~~~~~~~~~~~~~  2e700c05		uqadd v5.4h, v0.4h, v16.4h
+0x~~~~~~~~~~~~~~~~  6ea90ff5		uqadd v21.4s, v31.4s, v9.4s
+0x~~~~~~~~~~~~~~~~  2e230f17		uqadd v23.8b, v24.8b, v3.8b
+0x~~~~~~~~~~~~~~~~  6e6b0f71		uqadd v17.8h, v27.8h, v11.8h
+0x~~~~~~~~~~~~~~~~  7e2a5eca		uqrshl b10, b22, b10
+0x~~~~~~~~~~~~~~~~  7eeb5cbd		uqrshl d29, d5, d11
+0x~~~~~~~~~~~~~~~~  7e7e5f1b		uqrshl h27, h24, h30
+0x~~~~~~~~~~~~~~~~  7ea85daa		uqrshl s10, s13, s8
+0x~~~~~~~~~~~~~~~~  6e2e5e49		uqrshl v9.16b, v18.16b, v14.16b
+0x~~~~~~~~~~~~~~~~  6ef15df8		uqrshl v24.2d, v15.2d, v17.2d
+0x~~~~~~~~~~~~~~~~  2ebb5dc4		uqrshl v4.2s, v14.2s, v27.2s
+0x~~~~~~~~~~~~~~~~  2e685caf		uqrshl v15.4h, v5.4h, v8.4h
+0x~~~~~~~~~~~~~~~~  6ea05fb5		uqrshl v21.4s, v29.4s, v0.4s
+0x~~~~~~~~~~~~~~~~  2e295f10		uqrshl v16.8b, v24.8b, v9.8b
+0x~~~~~~~~~~~~~~~~  6e6f5c02		uqrshl v2.8h, v0.8h, v15.8h
+0x~~~~~~~~~~~~~~~~  7f0c9f4b		uqrshrn b11, h26, #4
+0x~~~~~~~~~~~~~~~~  7f1b9fc7		uqrshrn h7, s30, #5
+0x~~~~~~~~~~~~~~~~  7f2b9d0a		uqrshrn s10, d8, #21
+0x~~~~~~~~~~~~~~~~  2f359ccf		uqrshrn v15.2s, v6.2d, #11
+0x~~~~~~~~~~~~~~~~  2f149f45		uqrshrn v5.4h, v26.4s, #12
+0x~~~~~~~~~~~~~~~~  2f0b9f3c		uqrshrn v28.8b, v25.8h, #5
+0x~~~~~~~~~~~~~~~~  6f0e9fd9		uqrshrn2 v25.16b, v30.8h, #2
+0x~~~~~~~~~~~~~~~~  6f209dd5		uqrshrn2 v21.4s, v14.2d, #32
+0x~~~~~~~~~~~~~~~~  6f1e9ced		uqrshrn2 v13.8h, v7.4s, #2
+0x~~~~~~~~~~~~~~~~  7e374c0d		uqshl b13, b0, b23
+0x~~~~~~~~~~~~~~~~  7f0c7629		uqshl b9, b17, #4
+0x~~~~~~~~~~~~~~~~  7ee44cd7		uqshl d23, d6, d4
+0x~~~~~~~~~~~~~~~~  7f6c7568		uqshl d8, d11, #44
+0x~~~~~~~~~~~~~~~~  7e6f4db3		uqshl h19, h13, h15
+0x~~~~~~~~~~~~~~~~  7f167759		uqshl h25, h26, #6
+0x~~~~~~~~~~~~~~~~  7eaa4f04		uqshl s4, s24, s10
+0x~~~~~~~~~~~~~~~~  7f2175d3		uqshl s19, s14, #1
+0x~~~~~~~~~~~~~~~~  6e394fce		uqshl v14.16b, v30.16b, v25.16b
+0x~~~~~~~~~~~~~~~~  6f0d7546		uqshl v6.16b, v10.16b, #5
+0x~~~~~~~~~~~~~~~~  6ee74d12		uqshl v18.2d, v8.2d, v7.2d
+0x~~~~~~~~~~~~~~~~  6f5275d9		uqshl v25.2d, v14.2d, #18
+0x~~~~~~~~~~~~~~~~  2eb74e19		uqshl v25.2s, v16.2s, v23.2s
+0x~~~~~~~~~~~~~~~~  2f3f75ed		uqshl v13.2s, v15.2s, #31
+0x~~~~~~~~~~~~~~~~  2e6f4f1c		uqshl v28.4h, v24.4h, v15.4h
+0x~~~~~~~~~~~~~~~~  2f117624		uqshl v4.4h, v17.4h, #1
+0x~~~~~~~~~~~~~~~~  6eb74fe9		uqshl v9.4s, v31.4s, v23.4s
+0x~~~~~~~~~~~~~~~~  6f3f7792		uqshl v18.4s, v28.4s, #31
+0x~~~~~~~~~~~~~~~~  2e2f4ebf		uqshl v31.8b, v21.8b, v15.8b
+0x~~~~~~~~~~~~~~~~  2f0976a6		uqshl v6.8b, v21.8b, #1
+0x~~~~~~~~~~~~~~~~  6e714c5c		uqshl v28.8h, v2.8h, v17.8h
+0x~~~~~~~~~~~~~~~~  6f1e7518		uqshl v24.8h, v8.8h, #14
+0x~~~~~~~~~~~~~~~~  7f099775		uqshrn b21, h27, #7
+0x~~~~~~~~~~~~~~~~  7f15975c		uqshrn h28, s26, #11
+0x~~~~~~~~~~~~~~~~  7f2f97ed		uqshrn s13, d31, #17
+0x~~~~~~~~~~~~~~~~  2f389615		uqshrn v21.2s, v16.2d, #8
+0x~~~~~~~~~~~~~~~~  2f1e9718		uqshrn v24.4h, v24.4s, #2
+0x~~~~~~~~~~~~~~~~  2f089425		uqshrn v5.8b, v1.8h, #8
+0x~~~~~~~~~~~~~~~~  6f0a97b0		uqshrn2 v16.16b, v29.8h, #6
+0x~~~~~~~~~~~~~~~~  6f3f94c2		uqshrn2 v2.4s, v6.2d, #1
+0x~~~~~~~~~~~~~~~~  6f129550		uqshrn2 v16.8h, v10.4s, #14
+0x~~~~~~~~~~~~~~~~  7e3a2e9c		uqsub b28, b20, b26
+0x~~~~~~~~~~~~~~~~  7eea2ce0		uqsub d0, d7, d10
+0x~~~~~~~~~~~~~~~~  7e672f1a		uqsub h26, h24, h7
+0x~~~~~~~~~~~~~~~~  7eb02ef7		uqsub s23, s23, s16
+0x~~~~~~~~~~~~~~~~  6e382e0e		uqsub v14.16b, v16.16b, v24.16b
+0x~~~~~~~~~~~~~~~~  6ee62e2b		uqsub v11.2d, v17.2d, v6.2d
+0x~~~~~~~~~~~~~~~~  2ea82d4a		uqsub v10.2s, v10.2s, v8.2s
+0x~~~~~~~~~~~~~~~~  2e6c2de9		uqsub v9.4h, v15.4h, v12.4h
+0x~~~~~~~~~~~~~~~~  6ea72e57		uqsub v23.4s, v18.4s, v7.4s
+0x~~~~~~~~~~~~~~~~  2e312e69		uqsub v9.8b, v19.8b, v17.8b
+0x~~~~~~~~~~~~~~~~  6e662c54		uqsub v20.8h, v2.8h, v6.8h
+0x~~~~~~~~~~~~~~~~  7e214a7d		uqxtn b29, h19
+0x~~~~~~~~~~~~~~~~  7e6149a0		uqxtn h0, s13
+0x~~~~~~~~~~~~~~~~  7ea14ada		uqxtn s26, d22
+0x~~~~~~~~~~~~~~~~  2ea14be5		uqxtn v5.2s, v31.2d
+0x~~~~~~~~~~~~~~~~  2e614a7e		uqxtn v30.4h, v19.4s
+0x~~~~~~~~~~~~~~~~  2e21484f		uqxtn v15.8b, v2.8h
+0x~~~~~~~~~~~~~~~~  6e21487d		uqxtn2 v29.16b, v3.8h
+0x~~~~~~~~~~~~~~~~  6ea14a2d		uqxtn2 v13.4s, v17.2d
+0x~~~~~~~~~~~~~~~~  6e61497c		uqxtn2 v28.8h, v11.4s
+0x~~~~~~~~~~~~~~~~  0ea1c9f7		urecpe v23.2s, v15.2s
+0x~~~~~~~~~~~~~~~~  4ea1c8fb		urecpe v27.4s, v7.4s
+0x~~~~~~~~~~~~~~~~  6e3b15e2		urhadd v2.16b, v15.16b, v27.16b
+0x~~~~~~~~~~~~~~~~  2eb2142f		urhadd v15.2s, v1.2s, v18.2s
+0x~~~~~~~~~~~~~~~~  2e7a1491		urhadd v17.4h, v4.4h, v26.4h
+0x~~~~~~~~~~~~~~~~  6eae1762		urhadd v2.4s, v27.4s, v14.4s
+0x~~~~~~~~~~~~~~~~  2e2e1625		urhadd v5.8b, v17.8b, v14.8b
+0x~~~~~~~~~~~~~~~~  6e79145e		urhadd v30.8h, v2.8h, v25.8h
+0x~~~~~~~~~~~~~~~~  7efe5784		urshl d4, d28, d30
+0x~~~~~~~~~~~~~~~~  6e3357ed		urshl v13.16b, v31.16b, v19.16b
+0x~~~~~~~~~~~~~~~~  6ef556ee		urshl v14.2d, v23.2d, v21.2d
+0x~~~~~~~~~~~~~~~~  2ea854ea		urshl v10.2s, v7.2s, v8.2s
+0x~~~~~~~~~~~~~~~~  2e7c56af		urshl v15.4h, v21.4h, v28.4h
+0x~~~~~~~~~~~~~~~~  6eb7551e		urshl v30.4s, v8.4s, v23.4s
+0x~~~~~~~~~~~~~~~~  2e25569f		urshl v31.8b, v20.8b, v5.8b
+0x~~~~~~~~~~~~~~~~  6e7e577e		urshl v30.8h, v27.8h, v30.8h
+0x~~~~~~~~~~~~~~~~  7f4f25a4		urshr d4, d13, #49
+0x~~~~~~~~~~~~~~~~  6f0f2682		urshr v2.16b, v20.16b, #1
+0x~~~~~~~~~~~~~~~~  6f4d256d		urshr v13.2d, v11.2d, #51
+0x~~~~~~~~~~~~~~~~  2f3627f5		urshr v21.2s, v31.2s, #10
+0x~~~~~~~~~~~~~~~~  2f152635		urshr v21.4h, v17.4h, #11
+0x~~~~~~~~~~~~~~~~  6f3f26c4		urshr v4.4s, v22.4s, #1
+0x~~~~~~~~~~~~~~~~  2f092420		urshr v0.8b, v1.8b, #7
+0x~~~~~~~~~~~~~~~~  6f1f268d		urshr v13.8h, v20.8h, #1
+0x~~~~~~~~~~~~~~~~  2ea1ca14		ursqrte v20.2s, v16.2s
+0x~~~~~~~~~~~~~~~~  6ea1c91c		ursqrte v28.4s, v8.4s
+0x~~~~~~~~~~~~~~~~  7f53361b		ursra d27, d16, #45
+0x~~~~~~~~~~~~~~~~  6f0d3632		ursra v18.16b, v17.16b, #3
+0x~~~~~~~~~~~~~~~~  6f46379a		ursra v26.2d, v28.2d, #58
+0x~~~~~~~~~~~~~~~~  2f2136c8		ursra v8.2s, v22.2s, #31
+0x~~~~~~~~~~~~~~~~  2f19349f		ursra v31.4h, v4.4h, #7
+0x~~~~~~~~~~~~~~~~  6f3e35ff		ursra v31.4s, v15.4s, #2
+0x~~~~~~~~~~~~~~~~  2f0b3423		ursra v3.8b, v1.8b, #5
+0x~~~~~~~~~~~~~~~~  6f1335d2		ursra v18.8h, v14.8h, #13
+0x~~~~~~~~~~~~~~~~  7ef0441f		ushl d31, d0, d16
+0x~~~~~~~~~~~~~~~~  6e2244c0		ushl v0.16b, v6.16b, v2.16b
+0x~~~~~~~~~~~~~~~~  6ef24432		ushl v18.2d, v1.2d, v18.2d
+0x~~~~~~~~~~~~~~~~  2ebd44fb		ushl v27.2s, v7.2s, v29.2s
+0x~~~~~~~~~~~~~~~~  2e6d45ce		ushl v14.4h, v14.4h, v13.4h
+0x~~~~~~~~~~~~~~~~  6ea94496		ushl v22.4s, v4.4s, v9.4s
+0x~~~~~~~~~~~~~~~~  2e3b46d7		ushl v23.8b, v22.8b, v27.8b
+0x~~~~~~~~~~~~~~~~  6e684735		ushl v21.8h, v25.8h, v8.8h
+0x~~~~~~~~~~~~~~~~  2f35a40b		ushll v11.2d, v0.2s, #21
+0x~~~~~~~~~~~~~~~~  2f18a622		ushll v2.4s, v17.4h, #8
+0x~~~~~~~~~~~~~~~~  2f09a5cb		ushll v11.8h, v14.8b, #1
+0x~~~~~~~~~~~~~~~~  6f27a7a8		ushll2 v8.2d, v29.4s, #7
+0x~~~~~~~~~~~~~~~~  6f12a53d		ushll2 v29.4s, v9.8h, #2
+0x~~~~~~~~~~~~~~~~  6f0ea705		ushll2 v5.8h, v24.16b, #6
+0x~~~~~~~~~~~~~~~~  7f4b077c		ushr d28, d27, #53
+0x~~~~~~~~~~~~~~~~  6f090521		ushr v1.16b, v9.16b, #7
+0x~~~~~~~~~~~~~~~~  6f550702		ushr v2.2d, v24.2d, #43
+0x~~~~~~~~~~~~~~~~  2f35073e		ushr v30.2s, v25.2s, #11
+0x~~~~~~~~~~~~~~~~  2f14074a		ushr v10.4h, v26.4h, #12
+0x~~~~~~~~~~~~~~~~  6f2204a4		ushr v4.4s, v5.4s, #30
+0x~~~~~~~~~~~~~~~~  2f0f045e		ushr v30.8b, v2.8b, #1
+0x~~~~~~~~~~~~~~~~  6f1e0586		ushr v6.8h, v12.8h, #2
+0x~~~~~~~~~~~~~~~~  7e2038b3		usqadd b19, b5
+0x~~~~~~~~~~~~~~~~  7ee03849		usqadd d9, d2
+0x~~~~~~~~~~~~~~~~  7e603a02		usqadd h2, h16
+0x~~~~~~~~~~~~~~~~  7ea03870		usqadd s16, s3
+0x~~~~~~~~~~~~~~~~  6e203bbf		usqadd v31.16b, v29.16b
+0x~~~~~~~~~~~~~~~~  6ee03948		usqadd v8.2d, v10.2d
+0x~~~~~~~~~~~~~~~~  2ea03932		usqadd v18.2s, v9.2s
+0x~~~~~~~~~~~~~~~~  2e6039d8		usqadd v24.4h, v14.4h
+0x~~~~~~~~~~~~~~~~  6ea03bca		usqadd v10.4s, v30.4s
+0x~~~~~~~~~~~~~~~~  2e203a90		usqadd v16.8b, v20.8b
+0x~~~~~~~~~~~~~~~~  6e603a0c		usqadd v12.8h, v16.8h
+0x~~~~~~~~~~~~~~~~  7f5b177c		usra d28, d27, #37
+0x~~~~~~~~~~~~~~~~  6f0b16c5		usra v5.16b, v22.16b, #5
+0x~~~~~~~~~~~~~~~~  6f5f1662		usra v2.2d, v19.2d, #33
+0x~~~~~~~~~~~~~~~~  2f2b1400		usra v0.2s, v0.2s, #21
+0x~~~~~~~~~~~~~~~~  2f1414c7		usra v7.4h, v6.4h, #12
+0x~~~~~~~~~~~~~~~~  6f371624		usra v4.4s, v17.4s, #9
+0x~~~~~~~~~~~~~~~~  2f091589		usra v9.8b, v12.8b, #7
+0x~~~~~~~~~~~~~~~~  6f121763		usra v3.8h, v27.8h, #14
+0x~~~~~~~~~~~~~~~~  2ebe219d		usubl v29.2d, v12.2s, v30.2s
+0x~~~~~~~~~~~~~~~~  2e66239d		usubl v29.4s, v28.4h, v6.4h
+0x~~~~~~~~~~~~~~~~  2e2e208c		usubl v12.8h, v4.8b, v14.8b
+0x~~~~~~~~~~~~~~~~  6eb12301		usubl2 v1.2d, v24.4s, v17.4s
+0x~~~~~~~~~~~~~~~~  6e632024		usubl2 v4.4s, v1.8h, v3.8h
+0x~~~~~~~~~~~~~~~~  6e272097		usubl2 v23.8h, v4.16b, v7.16b
+0x~~~~~~~~~~~~~~~~  2ebe3289		usubw v9.2d, v20.2d, v30.2s
+0x~~~~~~~~~~~~~~~~  2e773214		usubw v20.4s, v16.4s, v23.4h
+0x~~~~~~~~~~~~~~~~  2e3d3119		usubw v25.8h, v8.8h, v29.8b
+0x~~~~~~~~~~~~~~~~  6ea633b2		usubw2 v18.2d, v29.2d, v6.4s
+0x~~~~~~~~~~~~~~~~  6e7430c6		usubw2 v6.4s, v6.4s, v20.8h
+0x~~~~~~~~~~~~~~~~  6e303092		usubw2 v18.8h, v4.8h, v16.16b
+0x~~~~~~~~~~~~~~~~  2f20a6bb		uxtl v27.2d, v21.2s
+0x~~~~~~~~~~~~~~~~  2f10a7e0		uxtl v0.4s, v31.4h
+0x~~~~~~~~~~~~~~~~  2f08a55b		uxtl v27.8h, v10.8b
+0x~~~~~~~~~~~~~~~~  6f20a606		uxtl2 v6.2d, v16.4s
+0x~~~~~~~~~~~~~~~~  6f10a696		uxtl2 v22.4s, v20.8h
+0x~~~~~~~~~~~~~~~~  6f08a6b4		uxtl2 v20.8h, v21.16b
+0x~~~~~~~~~~~~~~~~  4e11193e		uzp1 v30.16b, v9.16b, v17.16b
+0x~~~~~~~~~~~~~~~~  4edc1b47		uzp1 v7.2d, v26.2d, v28.2d
+0x~~~~~~~~~~~~~~~~  0e961a1a		uzp1 v26.2s, v16.2s, v22.2s
+0x~~~~~~~~~~~~~~~~  0e461a6e		uzp1 v14.4h, v19.4h, v6.4h
+0x~~~~~~~~~~~~~~~~  4e9e1af1		uzp1 v17.4s, v23.4s, v30.4s
+0x~~~~~~~~~~~~~~~~  0e0d1b7c		uzp1 v28.8b, v27.8b, v13.8b
+0x~~~~~~~~~~~~~~~~  4e4c1831		uzp1 v17.8h, v1.8h, v12.8h
+0x~~~~~~~~~~~~~~~~  4e1a5a48		uzp2 v8.16b, v18.16b, v26.16b
+0x~~~~~~~~~~~~~~~~  4ed85ad5		uzp2 v21.2d, v22.2d, v24.2d
+0x~~~~~~~~~~~~~~~~  0e825ab4		uzp2 v20.2s, v21.2s, v2.2s
+0x~~~~~~~~~~~~~~~~  0e465bf0		uzp2 v16.4h, v31.4h, v6.4h
+0x~~~~~~~~~~~~~~~~  4e885979		uzp2 v25.4s, v11.4s, v8.4s
+0x~~~~~~~~~~~~~~~~  0e0d5bff		uzp2 v31.8b, v31.8b, v13.8b
+0x~~~~~~~~~~~~~~~~  4e415a28		uzp2 v8.8h, v17.8h, v1.8h
+0x~~~~~~~~~~~~~~~~  0ea12b51		xtn v17.2s, v26.2d
+0x~~~~~~~~~~~~~~~~  0e612803		xtn v3.4h, v0.4s
+0x~~~~~~~~~~~~~~~~  0e212912		xtn v18.8b, v8.8h
+0x~~~~~~~~~~~~~~~~  4e212800		xtn2 v0.16b, v0.8h
+0x~~~~~~~~~~~~~~~~  4ea1288f		xtn2 v15.4s, v4.2d
+0x~~~~~~~~~~~~~~~~  4e612a5f		xtn2 v31.8h, v18.4s
+0x~~~~~~~~~~~~~~~~  4e063936		zip1 v22.16b, v9.16b, v6.16b
+0x~~~~~~~~~~~~~~~~  4ec23977		zip1 v23.2d, v11.2d, v2.2d
+0x~~~~~~~~~~~~~~~~  0e893a1a		zip1 v26.2s, v16.2s, v9.2s
+0x~~~~~~~~~~~~~~~~  0e473921		zip1 v1.4h, v9.4h, v7.4h
+0x~~~~~~~~~~~~~~~~  4e943bc0		zip1 v0.4s, v30.4s, v20.4s
+0x~~~~~~~~~~~~~~~~  0e0f3a3e		zip1 v30.8b, v17.8b, v15.8b
+0x~~~~~~~~~~~~~~~~  4e423911		zip1 v17.8h, v8.8h, v2.8h
+0x~~~~~~~~~~~~~~~~  4e0b7957		zip2 v23.16b, v10.16b, v11.16b
+0x~~~~~~~~~~~~~~~~  4ece78de		zip2 v30.2d, v6.2d, v14.2d
+0x~~~~~~~~~~~~~~~~  0e957949		zip2 v9.2s, v10.2s, v21.2s
+0x~~~~~~~~~~~~~~~~  0e5d7b08		zip2 v8.4h, v24.4h, v29.4h
+0x~~~~~~~~~~~~~~~~  4e977aa0		zip2 v0.4s, v21.4s, v23.4s
+0x~~~~~~~~~~~~~~~~  0e1e7af9		zip2 v25.8b, v23.8b, v30.8b
+0x~~~~~~~~~~~~~~~~  4e5e7947		zip2 v7.8h, v10.8h, v30.8h
+0x~~~~~~~~~~~~~~~~  6ee8d723		fabd v3.2d, v25.2d, v8.2d
+0x~~~~~~~~~~~~~~~~  2eabd76e		fabd v14.2s, v27.2s, v11.2s
+0x~~~~~~~~~~~~~~~~  6eb2d6c9		fabd v9.4s, v22.4s, v18.4s
+0x~~~~~~~~~~~~~~~~  4ee0fba1		fabs v1.2d, v29.2d
+0x~~~~~~~~~~~~~~~~  0ea0faa6		fabs v6.2s, v21.2s
+0x~~~~~~~~~~~~~~~~  4ea0fb2c		fabs v12.4s, v25.4s
+0x~~~~~~~~~~~~~~~~  6e60ecb2		facge v18.2d, v5.2d, v0.2d
+0x~~~~~~~~~~~~~~~~  2e26ed6f		facge v15.2s, v11.2s, v6.2s
+0x~~~~~~~~~~~~~~~~  6e39ed5e		facge v30.4s, v10.4s, v25.4s
+0x~~~~~~~~~~~~~~~~  6effee1c		facgt v28.2d, v16.2d, v31.2d
+0x~~~~~~~~~~~~~~~~  2ea4ec2f		facgt v15.2s, v1.2s, v4.2s
+0x~~~~~~~~~~~~~~~~  6eaaec76		facgt v22.4s, v3.4s, v10.4s
+0x~~~~~~~~~~~~~~~~  4e78d547		fadd v7.2d, v10.2d, v24.2d
+0x~~~~~~~~~~~~~~~~  0e27d6ea		fadd v10.2s, v23.2s, v7.2s
+0x~~~~~~~~~~~~~~~~  4e2bd6d0		fadd v16.4s, v22.4s, v11.4s
+0x~~~~~~~~~~~~~~~~  7e70db9b		faddp d27, v28.2d
+0x~~~~~~~~~~~~~~~~  7e30daf4		faddp s20, v23.2s
+0x~~~~~~~~~~~~~~~~  6e6bd495		faddp v21.2d, v4.2d, v11.2d
+0x~~~~~~~~~~~~~~~~  2e21d75f		faddp v31.2s, v26.2s, v1.2s
+0x~~~~~~~~~~~~~~~~  6e3cd76d		faddp v13.4s, v27.4s, v28.4s
+0x~~~~~~~~~~~~~~~~  4e74e5b1		fcmeq v17.2d, v13.2d, v20.2d
+0x~~~~~~~~~~~~~~~~  4ee0da18		fcmeq v24.2d, v16.2d, #0.0
+0x~~~~~~~~~~~~~~~~  0e2ae63a		fcmeq v26.2s, v17.2s, v10.2s
+0x~~~~~~~~~~~~~~~~  0ea0d898		fcmeq v24.2s, v4.2s, #0.0
+0x~~~~~~~~~~~~~~~~  4e2ee488		fcmeq v8.4s, v4.4s, v14.4s
+0x~~~~~~~~~~~~~~~~  4ea0db3a		fcmeq v26.4s, v25.4s, #0.0
+0x~~~~~~~~~~~~~~~~  6e60e41b		fcmge v27.2d, v0.2d, v0.2d
+0x~~~~~~~~~~~~~~~~  6ee0cbd6		fcmge v22.2d, v30.2d, #0.0
+0x~~~~~~~~~~~~~~~~  2e39e6a7		fcmge v7.2s, v21.2s, v25.2s
+0x~~~~~~~~~~~~~~~~  2ea0c9ef		fcmge v15.2s, v15.2s, #0.0
+0x~~~~~~~~~~~~~~~~  6e3be49d		fcmge v29.4s, v4.4s, v27.4s
+0x~~~~~~~~~~~~~~~~  6ea0cab6		fcmge v22.4s, v21.4s, #0.0
+0x~~~~~~~~~~~~~~~~  6eefe741		fcmgt v1.2d, v26.2d, v15.2d
+0x~~~~~~~~~~~~~~~~  4ee0caef		fcmgt v15.2d, v23.2d, #0.0
+0x~~~~~~~~~~~~~~~~  2ea6e615		fcmgt v21.2s, v16.2s, v6.2s
+0x~~~~~~~~~~~~~~~~  0ea0c9a1		fcmgt v1.2s, v13.2s, #0.0
+0x~~~~~~~~~~~~~~~~  6eb9e40e		fcmgt v14.4s, v0.4s, v25.4s
+0x~~~~~~~~~~~~~~~~  4ea0c90d		fcmgt v13.4s, v8.4s, #0.0
+0x~~~~~~~~~~~~~~~~  6ee0d8c4		fcmle v4.2d, v6.2d, #0.0
+0x~~~~~~~~~~~~~~~~  2ea0dbf8		fcmle v24.2s, v31.2s, #0.0
+0x~~~~~~~~~~~~~~~~  6ea0dae8		fcmle v8.4s, v23.4s, #0.0
+0x~~~~~~~~~~~~~~~~  4ee0e867		fcmlt v7.2d, v3.2d, #0.0
+0x~~~~~~~~~~~~~~~~  0ea0eaaf		fcmlt v15.2s, v21.2s, #0.0
+0x~~~~~~~~~~~~~~~~  4ea0e841		fcmlt v1.4s, v2.4s, #0.0
+0x~~~~~~~~~~~~~~~~  4e61c906		fcvtas v6.2d, v8.2d
+0x~~~~~~~~~~~~~~~~  0e21c921		fcvtas v1.2s, v9.2s
+0x~~~~~~~~~~~~~~~~  4e21ca68		fcvtas v8.4s, v19.4s
+0x~~~~~~~~~~~~~~~~  6e61cbe5		fcvtau v5.2d, v31.2d
+0x~~~~~~~~~~~~~~~~  2e21cbbc		fcvtau v28.2s, v29.2s
+0x~~~~~~~~~~~~~~~~  6e21cb4b		fcvtau v11.4s, v26.4s
+0x~~~~~~~~~~~~~~~~  0e617b28		fcvtl v8.2d, v25.2s
+0x~~~~~~~~~~~~~~~~  0e2179db		fcvtl v27.4s, v14.4h
+0x~~~~~~~~~~~~~~~~  4e6178c1		fcvtl2 v1.2d, v6.4s
+0x~~~~~~~~~~~~~~~~  4e217938		fcvtl2 v24.4s, v9.8h
+0x~~~~~~~~~~~~~~~~  4e61bb09		fcvtms v9.2d, v24.2d
+0x~~~~~~~~~~~~~~~~  0e21b967		fcvtms v7.2s, v11.2s
+0x~~~~~~~~~~~~~~~~  4e21bab7		fcvtms v23.4s, v21.4s
+0x~~~~~~~~~~~~~~~~  6e61b82d		fcvtmu v13.2d, v1.2d
+0x~~~~~~~~~~~~~~~~  2e21b99a		fcvtmu v26.2s, v12.2s
+0x~~~~~~~~~~~~~~~~  6e21bab5		fcvtmu v21.4s, v21.4s
+0x~~~~~~~~~~~~~~~~  0e61682b		fcvtn v11.2s, v1.2d
+0x~~~~~~~~~~~~~~~~  0e216848		fcvtn v8.4h, v2.4s
+0x~~~~~~~~~~~~~~~~  4e616bb8		fcvtn2 v24.4s, v29.2d
+0x~~~~~~~~~~~~~~~~  4e216944		fcvtn2 v4.8h, v10.4s
+0x~~~~~~~~~~~~~~~~  4e61a959		fcvtns v25.2d, v10.2d
+0x~~~~~~~~~~~~~~~~  0e21a904		fcvtns v4.2s, v8.2s
+0x~~~~~~~~~~~~~~~~  4e21ab7d		fcvtns v29.4s, v27.4s
+0x~~~~~~~~~~~~~~~~  6e61ab72		fcvtnu v18.2d, v27.2d
+0x~~~~~~~~~~~~~~~~  2e21a9cb		fcvtnu v11.2s, v14.2s
+0x~~~~~~~~~~~~~~~~  6e21aabb		fcvtnu v27.4s, v21.4s
+0x~~~~~~~~~~~~~~~~  4ee1a8b7		fcvtps v23.2d, v5.2d
+0x~~~~~~~~~~~~~~~~  0ea1a9f8		fcvtps v24.2s, v15.2s
+0x~~~~~~~~~~~~~~~~  4ea1aa65		fcvtps v5.4s, v19.4s
+0x~~~~~~~~~~~~~~~~  6ee1aaa3		fcvtpu v3.2d, v21.2d
+0x~~~~~~~~~~~~~~~~  2ea1aaa3		fcvtpu v3.2s, v21.2s
+0x~~~~~~~~~~~~~~~~  6ea1a8e0		fcvtpu v0.4s, v7.4s
+0x~~~~~~~~~~~~~~~~  2e61697d		fcvtxn v29.2s, v11.2d
+0x~~~~~~~~~~~~~~~~  6e616b3f		fcvtxn2 v31.4s, v25.2d
+0x~~~~~~~~~~~~~~~~  4ee1ba33		fcvtzs v19.2d, v17.2d
+0x~~~~~~~~~~~~~~~~  4f40ff0c		fcvtzs v12.2d, v24.2d, #64
+0x~~~~~~~~~~~~~~~~  0ea1b849		fcvtzs v9.2s, v2.2s
+0x~~~~~~~~~~~~~~~~  0f23fe85		fcvtzs v5.2s, v20.2s, #29
+0x~~~~~~~~~~~~~~~~  4ea1bb35		fcvtzs v21.4s, v25.4s
+0x~~~~~~~~~~~~~~~~  4f3afc3a		fcvtzs v26.4s, v1.4s, #6
+0x~~~~~~~~~~~~~~~~  6ee1bb2d		fcvtzu v13.2d, v25.2d
+0x~~~~~~~~~~~~~~~~  6f60fdbc		fcvtzu v28.2d, v13.2d, #32
+0x~~~~~~~~~~~~~~~~  2ea1b8da		fcvtzu v26.2s, v6.2s
+0x~~~~~~~~~~~~~~~~  2f31fd49		fcvtzu v9.2s, v10.2s, #15
+0x~~~~~~~~~~~~~~~~  6ea1b8de		fcvtzu v30.4s, v6.4s
+0x~~~~~~~~~~~~~~~~  6f2efed3		fcvtzu v19.4s, v22.4s, #18
+0x~~~~~~~~~~~~~~~~  6e6ffd0f		fdiv v15.2d, v8.2d, v15.2d
+0x~~~~~~~~~~~~~~~~  2e3afd2c		fdiv v12.2s, v9.2s, v26.2s
+0x~~~~~~~~~~~~~~~~  6e33fed3		fdiv v19.4s, v22.4s, v19.4s
+0x~~~~~~~~~~~~~~~~  4e68f4f3		fmax v19.2d, v7.2d, v8.2d
+0x~~~~~~~~~~~~~~~~  0e3df599		fmax v25.2s, v12.2s, v29.2s
+0x~~~~~~~~~~~~~~~~  4e25f5e6		fmax v6.4s, v15.4s, v5.4s
+0x~~~~~~~~~~~~~~~~  4e74c510		fmaxnm v16.2d, v8.2d, v20.2d
+0x~~~~~~~~~~~~~~~~  0e39c74f		fmaxnm v15.2s, v26.2s, v25.2s
+0x~~~~~~~~~~~~~~~~  4e30c5d7		fmaxnm v23.4s, v14.4s, v16.4s
+0x~~~~~~~~~~~~~~~~  7e70ca66		fmaxnmp d6, v19.2d
+0x~~~~~~~~~~~~~~~~  7e30cb5b		fmaxnmp s27, v26.2s
+0x~~~~~~~~~~~~~~~~  6e77c588		fmaxnmp v8.2d, v12.2d, v23.2d
+0x~~~~~~~~~~~~~~~~  2e36c72d		fmaxnmp v13.2s, v25.2s, v22.2s
+0x~~~~~~~~~~~~~~~~  6e31c56f		fmaxnmp v15.4s, v11.4s, v17.4s
+0x~~~~~~~~~~~~~~~~  6e30ca7b		fmaxnmv s27, v19.4s
+0x~~~~~~~~~~~~~~~~  7e70f9d4		fmaxp d20, v14.2d
+0x~~~~~~~~~~~~~~~~  7e30f852		fmaxp s18, v2.2s
+0x~~~~~~~~~~~~~~~~  6e7ff6e9		fmaxp v9.2d, v23.2d, v31.2d
+0x~~~~~~~~~~~~~~~~  2e3ff6c7		fmaxp v7.2s, v22.2s, v31.2s
+0x~~~~~~~~~~~~~~~~  6e3df4f2		fmaxp v18.4s, v7.4s, v29.4s
+0x~~~~~~~~~~~~~~~~  6e30fbbf		fmaxv s31, v29.4s
+0x~~~~~~~~~~~~~~~~  4ee2f4a2		fmin v2.2d, v5.2d, v2.2d
+0x~~~~~~~~~~~~~~~~  0eaaf63f		fmin v31.2s, v17.2s, v10.2s
+0x~~~~~~~~~~~~~~~~  4eb0f48a		fmin v10.4s, v4.4s, v16.4s
+0x~~~~~~~~~~~~~~~~  4ee5c4d5		fminnm v21.2d, v6.2d, v5.2d
+0x~~~~~~~~~~~~~~~~  0eaec656		fminnm v22.2s, v18.2s, v14.2s
+0x~~~~~~~~~~~~~~~~  4ea3c7f9		fminnm v25.4s, v31.4s, v3.4s
+0x~~~~~~~~~~~~~~~~  7ef0c829		fminnmp d9, v1.2d
+0x~~~~~~~~~~~~~~~~  7eb0ca95		fminnmp s21, v20.2s
+0x~~~~~~~~~~~~~~~~  6ef3c6b0		fminnmp v16.2d, v21.2d, v19.2d
+0x~~~~~~~~~~~~~~~~  2eb9c7f0		fminnmp v16.2s, v31.2s, v25.2s
+0x~~~~~~~~~~~~~~~~  6eafc61a		fminnmp v26.4s, v16.4s, v15.4s
+0x~~~~~~~~~~~~~~~~  6eb0c883		fminnmv s3, v4.4s
+0x~~~~~~~~~~~~~~~~  7ef0fb58		fminp d24, v26.2d
+0x~~~~~~~~~~~~~~~~  7eb0fa27		fminp s7, v17.2s
+0x~~~~~~~~~~~~~~~~  6ee3f677		fminp v23.2d, v19.2d, v3.2d
+0x~~~~~~~~~~~~~~~~  2ea9f6bd		fminp v29.2s, v21.2s, v9.2s
+0x~~~~~~~~~~~~~~~~  6eb5f700		fminp v0.4s, v24.4s, v21.4s
+0x~~~~~~~~~~~~~~~~  6eb0f919		fminv s25, v8.4s
+0x~~~~~~~~~~~~~~~~  5fc91817		fmla d23, d0, v9.d[2]
+0x~~~~~~~~~~~~~~~~  5f8711f7		fmla s23, s15, v7.s[0]
+0x~~~~~~~~~~~~~~~~  4e66cd71		fmla v17.2d, v11.2d, v6.2d
+0x~~~~~~~~~~~~~~~~  4fcb13de		fmla v30.2d, v30.2d, v11.d[0]
+0x~~~~~~~~~~~~~~~~  0e26cd93		fmla v19.2s, v12.2s, v6.2s
+0x~~~~~~~~~~~~~~~~  0f891238		fmla v24.2s, v17.2s, v9.s[0]
+0x~~~~~~~~~~~~~~~~  4e2bcd70		fmla v16.4s, v11.4s, v11.4s
+0x~~~~~~~~~~~~~~~~  4f891afb		fmla v27.4s, v23.4s, v9.s[2]
+0x~~~~~~~~~~~~~~~~  5fc653db		fmls d27, d30, v6.d[0]
+0x~~~~~~~~~~~~~~~~  5f825215		fmls s21, s16, v2.s[0]
+0x~~~~~~~~~~~~~~~~  4ef5ce65		fmls v5.2d, v19.2d, v21.2d
+0x~~~~~~~~~~~~~~~~  4fcc53d2		fmls v18.2d, v30.2d, v12.d[0]
+0x~~~~~~~~~~~~~~~~  0ea7ce05		fmls v5.2s, v16.2s, v7.2s
+0x~~~~~~~~~~~~~~~~  0fab5243		fmls v3.2s, v18.2s, v11.s[1]
+0x~~~~~~~~~~~~~~~~  4ebeccbb		fmls v27.4s, v5.4s, v30.4s
+0x~~~~~~~~~~~~~~~~  4fa45a9a		fmls v26.4s, v20.4s, v4.s[3]
+0x~~~~~~~~~~~~~~~~  6f06f6ce		fmov v14.2d, #0xd6 (-0.3438)
+0x~~~~~~~~~~~~~~~~  0f03f5ba		fmov v26.2s, #0x6d (0.9062)
+0x~~~~~~~~~~~~~~~~  4f04f69f		fmov v31.4s, #0x94 (-5.0000)
+0x~~~~~~~~~~~~~~~~  9eaf033c		fmov v28.D[1], x25
+0x~~~~~~~~~~~~~~~~  9eae0052		fmov x18, v2.D[1]
+0x~~~~~~~~~~~~~~~~  5fc1988c		fmul d12, d4, v1.d[2]
+0x~~~~~~~~~~~~~~~~  5faf983e		fmul s30, s1, v15.s[3]
+0x~~~~~~~~~~~~~~~~  6e75dc19		fmul v25.2d, v0.2d, v21.2d
+0x~~~~~~~~~~~~~~~~  4fca9b0a		fmul v10.2d, v24.2d, v10.d[2]
+0x~~~~~~~~~~~~~~~~  2e30df07		fmul v7.2s, v24.2s, v16.2s
+0x~~~~~~~~~~~~~~~~  0f849a01		fmul v1.2s, v16.2s, v4.s[2]
+0x~~~~~~~~~~~~~~~~  6e39df85		fmul v5.4s, v28.4s, v25.4s
+0x~~~~~~~~~~~~~~~~  4f88906b		fmul v11.4s, v3.4s, v8.s[0]
+0x~~~~~~~~~~~~~~~~  7fc3993c		fmulx d28, d9, v3.d[2]
+0x~~~~~~~~~~~~~~~~  7faf92b9		fmulx s25, s21, v15.s[1]
+0x~~~~~~~~~~~~~~~~  4e68df9f		fmulx v31.2d, v28.2d, v8.2d
+0x~~~~~~~~~~~~~~~~  6fc692a3		fmulx v3.2d, v21.2d, v6.d[0]
+0x~~~~~~~~~~~~~~~~  0e20dc29		fmulx v9.2s, v1.2s, v0.2s
+0x~~~~~~~~~~~~~~~~  2f869370		fmulx v16.2s, v27.2s, v6.s[0]
+0x~~~~~~~~~~~~~~~~  4e25dc82		fmulx v2.4s, v4.4s, v5.4s
+0x~~~~~~~~~~~~~~~~  6f8490f2		fmulx v18.4s, v7.4s, v4.s[0]
+0x~~~~~~~~~~~~~~~~  6ee0fb21		fneg v1.2d, v25.2d
+0x~~~~~~~~~~~~~~~~  2ea0fbee		fneg v14.2s, v31.2s
+0x~~~~~~~~~~~~~~~~  6ea0f885		fneg v5.4s, v4.4s
+0x~~~~~~~~~~~~~~~~  4ee1d992		frecpe v18.2d, v12.2d
+0x~~~~~~~~~~~~~~~~  0ea1daca		frecpe v10.2s, v22.2s
+0x~~~~~~~~~~~~~~~~  4ea1d8c5		frecpe v5.4s, v6.4s
+0x~~~~~~~~~~~~~~~~  4e7afcf6		frecps v22.2d, v7.2d, v26.2d
+0x~~~~~~~~~~~~~~~~  0e22ff7f		frecps v31.2s, v27.2s, v2.2s
+0x~~~~~~~~~~~~~~~~  4e3bfcd2		frecps v18.4s, v6.4s, v27.4s
+0x~~~~~~~~~~~~~~~~  6e6189ba		frinta v26.2d, v13.2d
+0x~~~~~~~~~~~~~~~~  2e218b4f		frinta v15.2s, v26.2s
+0x~~~~~~~~~~~~~~~~  6e218a0d		frinta v13.4s, v16.4s
+0x~~~~~~~~~~~~~~~~  6ee19989		frinti v9.2d, v12.2d
+0x~~~~~~~~~~~~~~~~  2ea19a65		frinti v5.2s, v19.2s
+0x~~~~~~~~~~~~~~~~  6ea1996f		frinti v15.4s, v11.4s
+0x~~~~~~~~~~~~~~~~  4e619bb1		frintm v17.2d, v29.2d
+0x~~~~~~~~~~~~~~~~  0e21997e		frintm v30.2s, v11.2s
+0x~~~~~~~~~~~~~~~~  4e219a81		frintm v1.4s, v20.4s
+0x~~~~~~~~~~~~~~~~  4e6188d8		frintn v24.2d, v6.2d
+0x~~~~~~~~~~~~~~~~  0e218a2c		frintn v12.2s, v17.2s
+0x~~~~~~~~~~~~~~~~  4e21897d		frintn v29.4s, v11.4s
+0x~~~~~~~~~~~~~~~~  4ee188ea		frintp v10.2d, v7.2d
+0x~~~~~~~~~~~~~~~~  0ea18a4c		frintp v12.2s, v18.2s
+0x~~~~~~~~~~~~~~~~  4ea18bfa		frintp v26.4s, v31.4s
+0x~~~~~~~~~~~~~~~~  6e6199b8		frintx v24.2d, v13.2d
+0x~~~~~~~~~~~~~~~~  2e219927		frintx v7.2s, v9.2s
+0x~~~~~~~~~~~~~~~~  6e219ab2		frintx v18.4s, v21.4s
+0x~~~~~~~~~~~~~~~~  4ee19b33		frintz v19.2d, v25.2d
+0x~~~~~~~~~~~~~~~~  0ea1990f		frintz v15.2s, v8.2s
+0x~~~~~~~~~~~~~~~~  4ea19874		frintz v20.4s, v3.4s
+0x~~~~~~~~~~~~~~~~  6ee1d8b7		frsqrte v23.2d, v5.2d
+0x~~~~~~~~~~~~~~~~  2ea1d8e9		frsqrte v9.2s, v7.2s
+0x~~~~~~~~~~~~~~~~  6ea1d923		frsqrte v3.4s, v9.4s
+0x~~~~~~~~~~~~~~~~  4eefff99		frsqrts v25.2d, v28.2d, v15.2d
+0x~~~~~~~~~~~~~~~~  0eaaff49		frsqrts v9.2s, v26.2s, v10.2s
+0x~~~~~~~~~~~~~~~~  4eaafc25		frsqrts v5.4s, v1.4s, v10.4s
+0x~~~~~~~~~~~~~~~~  6ee1fa46		fsqrt v6.2d, v18.2d
+0x~~~~~~~~~~~~~~~~  2ea1fa46		fsqrt v6.2s, v18.2s
+0x~~~~~~~~~~~~~~~~  6ea1fbe0		fsqrt v0.4s, v31.4s
+0x~~~~~~~~~~~~~~~~  4effd7df		fsub v31.2d, v30.2d, v31.2d
+0x~~~~~~~~~~~~~~~~  0ea6d50b		fsub v11.2s, v8.2s, v6.2s
+0x~~~~~~~~~~~~~~~~  4ebfd410		fsub v16.4s, v0.4s, v31.4s
+0x~~~~~~~~~~~~~~~~  4e61dbf9		scvtf v25.2d, v31.2d
+0x~~~~~~~~~~~~~~~~  4f53e5aa		scvtf v10.2d, v13.2d, #45
+0x~~~~~~~~~~~~~~~~  0e21d9ea		scvtf v10.2s, v15.2s
+0x~~~~~~~~~~~~~~~~  0f25e492		scvtf v18.2s, v4.2s, #27
+0x~~~~~~~~~~~~~~~~  4e21d8b1		scvtf v17.4s, v5.4s
+0x~~~~~~~~~~~~~~~~  4f28e72b		scvtf v11.4s, v25.4s, #24
+0x~~~~~~~~~~~~~~~~  6e61d869		ucvtf v9.2d, v3.2d
+0x~~~~~~~~~~~~~~~~  6f52e7da		ucvtf v26.2d, v30.2d, #46
+0x~~~~~~~~~~~~~~~~  2e21d88b		ucvtf v11.2s, v4.2s
+0x~~~~~~~~~~~~~~~~  2f27e47d		ucvtf v29.2s, v3.2s, #25
+0x~~~~~~~~~~~~~~~~  6e21daf6		ucvtf v22.4s, v23.4s
+0x~~~~~~~~~~~~~~~~  6f27e532		ucvtf v18.4s, v9.4s, #25
+0x~~~~~~~~~~~~~~~~  d65f03c0		ret
diff --git a/test/test-trace-reference/log-disasm-colour b/test/test-trace-reference/log-disasm-colour
new file mode 100644
index 0000000..f1ca65c
--- /dev/null
+++ b/test/test-trace-reference/log-disasm-colour
@@ -0,0 +1,2381 @@
+0x~~~~~~~~~~~~~~~~  1a050083		adc w3, w4, w5
+0x~~~~~~~~~~~~~~~~  9a0800e6		adc x6, x7, x8
+0x~~~~~~~~~~~~~~~~  3a0b0149		adcs w9, w10, w11
+0x~~~~~~~~~~~~~~~~  ba0e01ac		adcs x12, x13, x14
+0x~~~~~~~~~~~~~~~~  0b11020f		add w15, w16, w17
+0x~~~~~~~~~~~~~~~~  8b140272		add x18, x19, x20
+0x~~~~~~~~~~~~~~~~  2b1702d5		adds w21, w22, w23
+0x~~~~~~~~~~~~~~~~  ab1a0338		adds x24, x25, x26
+0x~~~~~~~~~~~~~~~~  0a1d039b		and w27, w28, w29
+0x~~~~~~~~~~~~~~~~  8a040062		and x2, x3, x4
+0x~~~~~~~~~~~~~~~~  6a0700c5		ands w5, w6, w7
+0x~~~~~~~~~~~~~~~~  ea0a0128		ands x8, x9, x10
+0x~~~~~~~~~~~~~~~~  13007d8b		sbfx w11, w12, #0, #32
+0x~~~~~~~~~~~~~~~~  9341fdcd		asr x13, x14, #1
+0x~~~~~~~~~~~~~~~~  1ad12a0f		asr w15, w16, w17
+0x~~~~~~~~~~~~~~~~  9ad42a72		asr x18, x19, x20
+0x~~~~~~~~~~~~~~~~  33051ad5		bfxil w21, w22, #5, #2
+0x~~~~~~~~~~~~~~~~  b3472317		bfxil x23, x24, #7, #2
+0x~~~~~~~~~~~~~~~~  0a3b0359		bic w25, w26, w27
+0x~~~~~~~~~~~~~~~~  8a2203bc		bic x28, x29, x2
+0x~~~~~~~~~~~~~~~~  6a250083		bics w3, w4, w5
+0x~~~~~~~~~~~~~~~~  ea2800e6		bics x6, x7, x8
+0x~~~~~~~~~~~~~~~~  3a4ae120		ccmn w9, w10, #nzcv, al
+0x~~~~~~~~~~~~~~~~  3a4a0120		ccmn w9, w10, #nzcv, eq
+0x~~~~~~~~~~~~~~~~  3a4a1120		ccmn w9, w10, #nzcv, ne
+0x~~~~~~~~~~~~~~~~  ba4ce162		ccmn x11, x12, #nzCv, al
+0x~~~~~~~~~~~~~~~~  ba4c3162		ccmn x11, x12, #nzCv, lo
+0x~~~~~~~~~~~~~~~~  ba4c2162		ccmn x11, x12, #nzCv, hs
+0x~~~~~~~~~~~~~~~~  7a4ee1a1		ccmp w13, w14, #nzcV, al
+0x~~~~~~~~~~~~~~~~  7a4e81a1		ccmp w13, w14, #nzcV, hi
+0x~~~~~~~~~~~~~~~~  7a4e91a1		ccmp w13, w14, #nzcV, ls
+0x~~~~~~~~~~~~~~~~  fa50e1e3		ccmp x15, x16, #nzCV, al
+0x~~~~~~~~~~~~~~~~  fa5001e3		ccmp x15, x16, #nzCV, eq
+0x~~~~~~~~~~~~~~~~  fa5011e3		ccmp x15, x16, #nzCV, ne
+0x~~~~~~~~~~~~~~~~  1a922651		cinc w17, w18, lo
+0x~~~~~~~~~~~~~~~~  1a923651		cinc w17, w18, hs
+0x~~~~~~~~~~~~~~~~  9a949693		cinc x19, x20, hi
+0x~~~~~~~~~~~~~~~~  9a948693		cinc x19, x20, ls
+0x~~~~~~~~~~~~~~~~  5a9612d5		cinv w21, w22, eq
+0x~~~~~~~~~~~~~~~~  5a9602d5		cinv w21, w22, ne
+0x~~~~~~~~~~~~~~~~  da982317		cinv x23, x24, lo
+0x~~~~~~~~~~~~~~~~  da983317		cinv x23, x24, hs
+0x~~~~~~~~~~~~~~~~  d5033f5f		clrex
+0x~~~~~~~~~~~~~~~~  5ac01759		cls w25, w26
+0x~~~~~~~~~~~~~~~~  dac0179b		cls x27, x28
+0x~~~~~~~~~~~~~~~~  5ac0105d		clz w29, w2
+0x~~~~~~~~~~~~~~~~  dac01083		clz x3, x4
+0x~~~~~~~~~~~~~~~~  2b0600bf		cmn w5, w6
+0x~~~~~~~~~~~~~~~~  ab0800ff		cmn x7, x8
+0x~~~~~~~~~~~~~~~~  6b0a013f		cmp w9, w10
+0x~~~~~~~~~~~~~~~~  eb0c017f		cmp x11, x12
+0x~~~~~~~~~~~~~~~~  5a8e95cd		cneg w13, w14, hi
+0x~~~~~~~~~~~~~~~~  5a8e85cd		cneg w13, w14, ls
+0x~~~~~~~~~~~~~~~~  da90160f		cneg x15, x16, eq
+0x~~~~~~~~~~~~~~~~  da90060f		cneg x15, x16, ne
+0x~~~~~~~~~~~~~~~~  1ad34251		crc32b w17, w18, w19
+0x~~~~~~~~~~~~~~~~  1ad652b4		crc32cb w20, w21, w22
+0x~~~~~~~~~~~~~~~~  1ad95717		crc32ch w23, w24, w25
+0x~~~~~~~~~~~~~~~~  1adc5b7a		crc32cw w26, w27, w28
+0x~~~~~~~~~~~~~~~~  1ac644a4		crc32h w4, w5, w6
+0x~~~~~~~~~~~~~~~~  1ac94907		crc32w w7, w8, w9
+0x~~~~~~~~~~~~~~~~  1a8f31cd		csel w13, w14, w15, lo
+0x~~~~~~~~~~~~~~~~  1a8f21cd		csel w13, w14, w15, hs
+0x~~~~~~~~~~~~~~~~  9a928230		csel x16, x17, x18, hi
+0x~~~~~~~~~~~~~~~~  9a929230		csel x16, x17, x18, ls
+0x~~~~~~~~~~~~~~~~  1a9f17f3		cset w19, eq
+0x~~~~~~~~~~~~~~~~  1a9f07f3		cset w19, ne
+0x~~~~~~~~~~~~~~~~  9a9f27f4		cset x20, lo
+0x~~~~~~~~~~~~~~~~  9a9f37f4		cset x20, hs
+0x~~~~~~~~~~~~~~~~  5a9f93f5		csetm w21, hi
+0x~~~~~~~~~~~~~~~~  5a9f83f5		csetm w21, ls
+0x~~~~~~~~~~~~~~~~  da9f13f6		csetm x22, eq
+0x~~~~~~~~~~~~~~~~  da9f03f6		csetm x22, ne
+0x~~~~~~~~~~~~~~~~  1a993717		csinc w23, w24, w25, lo
+0x~~~~~~~~~~~~~~~~  1a992717		csinc w23, w24, w25, hs
+0x~~~~~~~~~~~~~~~~  9a9c877a		csinc x26, x27, x28, hi
+0x~~~~~~~~~~~~~~~~  9a9c977a		csinc x26, x27, x28, ls
+0x~~~~~~~~~~~~~~~~  5a83005d		csinv w29, w2, w3, eq
+0x~~~~~~~~~~~~~~~~  5a83105d		csinv w29, w2, w3, ne
+0x~~~~~~~~~~~~~~~~  da8630a4		csinv x4, x5, x6, lo
+0x~~~~~~~~~~~~~~~~  da8620a4		csinv x4, x5, x6, hs
+0x~~~~~~~~~~~~~~~~  5a898507		csneg w7, w8, w9, hi
+0x~~~~~~~~~~~~~~~~  5a899507		csneg w7, w8, w9, ls
+0x~~~~~~~~~~~~~~~~  da8c056a		csneg x10, x11, x12, eq
+0x~~~~~~~~~~~~~~~~  da8c156a		csneg x10, x11, x12, ne
+0x~~~~~~~~~~~~~~~~  d50b7a20		dc cvac, x0
+0x~~~~~~~~~~~~~~~~  d5033bbf		dmb ish
+0x~~~~~~~~~~~~~~~~  d5033b9f		dsb ish
+0x~~~~~~~~~~~~~~~~  4a2f01cd		eon w13, w14, w15
+0x~~~~~~~~~~~~~~~~  ca320230		eon x16, x17, x18
+0x~~~~~~~~~~~~~~~~  4a150293		eor w19, w20, w21
+0x~~~~~~~~~~~~~~~~  ca1802f6		eor x22, x23, x24
+0x~~~~~~~~~~~~~~~~  139b2759		extr w25, w26, w27, #9
+0x~~~~~~~~~~~~~~~~  93c22bbc		extr x28, x29, x2, #10
+0x~~~~~~~~~~~~~~~~  d503201f		nop
+0x~~~~~~~~~~~~~~~~  d50b7520		ic ivau, x0
+0x~~~~~~~~~~~~~~~~  d5033fdf		isb
+0x~~~~~~~~~~~~~~~~  88dffc03		ldar w3, [x0]
+0x~~~~~~~~~~~~~~~~  c8dffc04		ldar x4, [x0]
+0x~~~~~~~~~~~~~~~~  08dffc05		ldarb w5, [x0]
+0x~~~~~~~~~~~~~~~~  08dffc06		ldarb w6, [x0]
+0x~~~~~~~~~~~~~~~~  48dffc07		ldarh w7, [x0]
+0x~~~~~~~~~~~~~~~~  48dffc08		ldarh w8, [x0]
+0x~~~~~~~~~~~~~~~~  887fa809		ldaxp w9, w10, [x0]
+0x~~~~~~~~~~~~~~~~  c87fb00b		ldaxp x11, x12, [x0]
+0x~~~~~~~~~~~~~~~~  885ffc0d		ldaxr w13, [x0]
+0x~~~~~~~~~~~~~~~~  c85ffc0e		ldaxr x14, [x0]
+0x~~~~~~~~~~~~~~~~  085ffc0f		ldaxrb w15, [x0]
+0x~~~~~~~~~~~~~~~~  085ffc10		ldaxrb w16, [x0]
+0x~~~~~~~~~~~~~~~~  485ffc11		ldaxrh w17, [x0]
+0x~~~~~~~~~~~~~~~~  485ffc12		ldaxrh w18, [x0]
+0x~~~~~~~~~~~~~~~~  28405013		ldnp w19, w20, [x0]
+0x~~~~~~~~~~~~~~~~  a8405815		ldnp x21, x22, [x0]
+0x~~~~~~~~~~~~~~~~  29406017		ldp w23, w24, [x0]
+0x~~~~~~~~~~~~~~~~  28c16037		ldp w23, w24, [x1], #8
+0x~~~~~~~~~~~~~~~~  29c16037		ldp w23, w24, [x1, #8]!
+0x~~~~~~~~~~~~~~~~  a9406819		ldp x25, x26, [x0]
+0x~~~~~~~~~~~~~~~~  a8c16839		ldp x25, x26, [x1], #16
+0x~~~~~~~~~~~~~~~~  a9c16839		ldp x25, x26, [x1, #16]!
+0x~~~~~~~~~~~~~~~~  6940701b		ldpsw x27, x28, [x0]
+0x~~~~~~~~~~~~~~~~  68c1703b		ldpsw x27, x28, [x1], #8
+0x~~~~~~~~~~~~~~~~  69c1703b		ldpsw x27, x28, [x1, #8]!
+0x~~~~~~~~~~~~~~~~  b940001d		ldr w29, [x0]
+0x~~~~~~~~~~~~~~~~  b840443d		ldr w29, [x1], #4
+0x~~~~~~~~~~~~~~~~  b8404c3d		ldr w29, [x1, #4]!
+0x~~~~~~~~~~~~~~~~  f9400002		ldr x2, [x0]
+0x~~~~~~~~~~~~~~~~  f8408422		ldr x2, [x1], #8
+0x~~~~~~~~~~~~~~~~  f8408c22		ldr x2, [x1, #8]!
+0x~~~~~~~~~~~~~~~~  39400003		ldrb w3, [x0]
+0x~~~~~~~~~~~~~~~~  38401423		ldrb w3, [x1], #1
+0x~~~~~~~~~~~~~~~~  38401c23		ldrb w3, [x1, #1]!
+0x~~~~~~~~~~~~~~~~  39400004		ldrb w4, [x0]
+0x~~~~~~~~~~~~~~~~  38401424		ldrb w4, [x1], #1
+0x~~~~~~~~~~~~~~~~  38401c24		ldrb w4, [x1, #1]!
+0x~~~~~~~~~~~~~~~~  79400005		ldrh w5, [x0]
+0x~~~~~~~~~~~~~~~~  78402425		ldrh w5, [x1], #2
+0x~~~~~~~~~~~~~~~~  78402c25		ldrh w5, [x1, #2]!
+0x~~~~~~~~~~~~~~~~  79400006		ldrh w6, [x0]
+0x~~~~~~~~~~~~~~~~  78402426		ldrh w6, [x1], #2
+0x~~~~~~~~~~~~~~~~  78402c26		ldrh w6, [x1, #2]!
+0x~~~~~~~~~~~~~~~~  39c00007		ldrsb w7, [x0]
+0x~~~~~~~~~~~~~~~~  38c01427		ldrsb w7, [x1], #1
+0x~~~~~~~~~~~~~~~~  38c01c27		ldrsb w7, [x1, #1]!
+0x~~~~~~~~~~~~~~~~  39800008		ldrsb x8, [x0]
+0x~~~~~~~~~~~~~~~~  38801428		ldrsb x8, [x1], #1
+0x~~~~~~~~~~~~~~~~  38801c28		ldrsb x8, [x1, #1]!
+0x~~~~~~~~~~~~~~~~  79c00009		ldrsh w9, [x0]
+0x~~~~~~~~~~~~~~~~  78c02429		ldrsh w9, [x1], #2
+0x~~~~~~~~~~~~~~~~  78c02c29		ldrsh w9, [x1, #2]!
+0x~~~~~~~~~~~~~~~~  7980000a		ldrsh x10, [x0]
+0x~~~~~~~~~~~~~~~~  7880242a		ldrsh x10, [x1], #2
+0x~~~~~~~~~~~~~~~~  78802c2a		ldrsh x10, [x1, #2]!
+0x~~~~~~~~~~~~~~~~  b980000b		ldrsw x11, [x0]
+0x~~~~~~~~~~~~~~~~  b880442b		ldrsw x11, [x1], #4
+0x~~~~~~~~~~~~~~~~  b8804c2b		ldrsw x11, [x1, #4]!
+0x~~~~~~~~~~~~~~~~  b840700c		ldur w12, [x0, #7]
+0x~~~~~~~~~~~~~~~~  f840f00d		ldur x13, [x0, #15]
+0x~~~~~~~~~~~~~~~~  3840100e		ldurb w14, [x0, #1]
+0x~~~~~~~~~~~~~~~~  3840100f		ldurb w15, [x0, #1]
+0x~~~~~~~~~~~~~~~~  78403010		ldurh w16, [x0, #3]
+0x~~~~~~~~~~~~~~~~  78403011		ldurh w17, [x0, #3]
+0x~~~~~~~~~~~~~~~~  38c01012		ldursb w18, [x0, #1]
+0x~~~~~~~~~~~~~~~~  38801013		ldursb x19, [x0, #1]
+0x~~~~~~~~~~~~~~~~  78c03014		ldursh w20, [x0, #3]
+0x~~~~~~~~~~~~~~~~  78803015		ldursh x21, [x0, #3]
+0x~~~~~~~~~~~~~~~~  b8807016		ldursw x22, [x0, #7]
+0x~~~~~~~~~~~~~~~~  887f6017		ldxp w23, w24, [x0]
+0x~~~~~~~~~~~~~~~~  c87f6819		ldxp x25, x26, [x0]
+0x~~~~~~~~~~~~~~~~  885f7c1b		ldxr w27, [x0]
+0x~~~~~~~~~~~~~~~~  c85f7c1c		ldxr x28, [x0]
+0x~~~~~~~~~~~~~~~~  085f7c1d		ldxrb w29, [x0]
+0x~~~~~~~~~~~~~~~~  085f7c02		ldxrb w2, [x0]
+0x~~~~~~~~~~~~~~~~  485f7c03		ldxrh w3, [x0]
+0x~~~~~~~~~~~~~~~~  485f7c04		ldxrh w4, [x0]
+0x~~~~~~~~~~~~~~~~  531e74c5		lsl w5, w6, #2
+0x~~~~~~~~~~~~~~~~  d37df107		lsl x7, x8, #3
+0x~~~~~~~~~~~~~~~~  1acb2149		lsl w9, w10, w11
+0x~~~~~~~~~~~~~~~~  9ace21ac		lsl x12, x13, x14
+0x~~~~~~~~~~~~~~~~  53047e0f		lsr w15, w16, #4
+0x~~~~~~~~~~~~~~~~  d345fe51		lsr x17, x18, #5
+0x~~~~~~~~~~~~~~~~  1ad52693		lsr w19, w20, w21
+0x~~~~~~~~~~~~~~~~  9ad826f6		lsr x22, x23, x24
+0x~~~~~~~~~~~~~~~~  1b1b7359		madd w25, w26, w27, w28
+0x~~~~~~~~~~~~~~~~  9b03105d		madd x29, x2, x3, x4
+0x~~~~~~~~~~~~~~~~  1b07fcc5		mneg w5, w6, w7
+0x~~~~~~~~~~~~~~~~  9b0afd28		mneg x8, x9, x10
+0x~~~~~~~~~~~~~~~~  2a0c03eb		mov w11, w12
+0x~~~~~~~~~~~~~~~~  aa0e03ed		mov x13, x14
+0x~~~~~~~~~~~~~~~~  7280104f		movk w15, #0x82
+0x~~~~~~~~~~~~~~~~  f2801070		movk x16, #0x83
+0x~~~~~~~~~~~~~~~~  12801091		mov w17, #0xffffff7b
+0x~~~~~~~~~~~~~~~~  928010b2		mov x18, #0xffffffffffffff7a
+0x~~~~~~~~~~~~~~~~  528010d3		mov w19, #0x86
+0x~~~~~~~~~~~~~~~~  d28010f4		mov x20, #0x87
+0x~~~~~~~~~~~~~~~~  1b18e6f6		msub w22, w23, w24, w25
+0x~~~~~~~~~~~~~~~~  9b1cf77a		msub x26, x27, x28, x29
+0x~~~~~~~~~~~~~~~~  1b047c62		mul w2, w3, w4
+0x~~~~~~~~~~~~~~~~  9b077cc5		mul x5, x6, x7
+0x~~~~~~~~~~~~~~~~  2a2903e8		mvn w8, w9
+0x~~~~~~~~~~~~~~~~  aa2b03ea		mvn x10, x11
+0x~~~~~~~~~~~~~~~~  4b0d03ec		neg w12, w13
+0x~~~~~~~~~~~~~~~~  cb0f03ee		neg x14, x15
+0x~~~~~~~~~~~~~~~~  6b1103f0		negs w16, w17
+0x~~~~~~~~~~~~~~~~  eb1303f2		negs x18, x19
+0x~~~~~~~~~~~~~~~~  5a1503f4		ngc w20, w21
+0x~~~~~~~~~~~~~~~~  da1703f6		ngc x22, x23
+0x~~~~~~~~~~~~~~~~  7a1903f8		ngcs w24, w25
+0x~~~~~~~~~~~~~~~~  fa1b03fa		ngcs x26, x27
+0x~~~~~~~~~~~~~~~~  d503201f		nop
+0x~~~~~~~~~~~~~~~~  2a2203bc		orn w28, w29, w2
+0x~~~~~~~~~~~~~~~~  aa250083		orn x3, x4, x5
+0x~~~~~~~~~~~~~~~~  2a0800e6		orr w6, w7, w8
+0x~~~~~~~~~~~~~~~~  aa0b0149		orr x9, x10, x11
+0x~~~~~~~~~~~~~~~~  f8804000		prfum pldl1keep, [x0, #4]
+0x~~~~~~~~~~~~~~~~  f8801000		prfum pldl1keep, [x0, #1]
+0x~~~~~~~~~~~~~~~~  5ac001ac		rbit w12, w13
+0x~~~~~~~~~~~~~~~~  dac001ee		rbit x14, x15
+0x~~~~~~~~~~~~~~~~  5ac00a30		rev w16, w17
+0x~~~~~~~~~~~~~~~~  dac00e72		rev x18, x19
+0x~~~~~~~~~~~~~~~~  5ac006b4		rev16 w20, w21
+0x~~~~~~~~~~~~~~~~  dac006f6		rev16 x22, x23
+0x~~~~~~~~~~~~~~~~  dac00b38		rev32 x24, x25
+0x~~~~~~~~~~~~~~~~  1adc2f7a		ror w26, w27, w28
+0x~~~~~~~~~~~~~~~~  9ac32c5d		ror x29, x2, x3
+0x~~~~~~~~~~~~~~~~  5a0600a4		sbc w4, w5, w6
+0x~~~~~~~~~~~~~~~~  da090107		sbc x7, x8, x9
+0x~~~~~~~~~~~~~~~~  7a0c016a		sbcs w10, w11, w12
+0x~~~~~~~~~~~~~~~~  fa0f01cd		sbcs x13, x14, x15
+0x~~~~~~~~~~~~~~~~  131e0a30		sbfiz w16, w17, #2, #3
+0x~~~~~~~~~~~~~~~~  937c1272		sbfiz x18, x19, #4, #5
+0x~~~~~~~~~~~~~~~~  130632f6		sbfx w22, w23, #6, #7
+0x~~~~~~~~~~~~~~~~  93484338		sbfx x24, x25, #8, #9
+0x~~~~~~~~~~~~~~~~  1adc0f7a		sdiv w26, w27, w28
+0x~~~~~~~~~~~~~~~~  9ac30c5d		sdiv x29, x2, x3
+0x~~~~~~~~~~~~~~~~  9b4e7dac		smulh x12, x13, x14
+0x~~~~~~~~~~~~~~~~  889ffc12		stlr w18, [x0]
+0x~~~~~~~~~~~~~~~~  c89ffc13		stlr x19, [x0]
+0x~~~~~~~~~~~~~~~~  089ffc14		stlrb w20, [x0]
+0x~~~~~~~~~~~~~~~~  089ffc15		stlrb w21, [x0]
+0x~~~~~~~~~~~~~~~~  489ffc16		stlrh w22, [x0]
+0x~~~~~~~~~~~~~~~~  489ffc17		stlrh w23, [x0]
+0x~~~~~~~~~~~~~~~~  8838e819		stlxp w24, w25, w26, [x0]
+0x~~~~~~~~~~~~~~~~  c83bf41c		stlxp w27, x28, x29, [x0]
+0x~~~~~~~~~~~~~~~~  8802fc03		stlxr w2, w3, [x0]
+0x~~~~~~~~~~~~~~~~  c804fc05		stlxr w4, x5, [x0]
+0x~~~~~~~~~~~~~~~~  0806fc07		stlxrb w6, w7, [x0]
+0x~~~~~~~~~~~~~~~~  0808fc09		stlxrb w8, w9, [x0]
+0x~~~~~~~~~~~~~~~~  480afc0b		stlxrh w10, w11, [x0]
+0x~~~~~~~~~~~~~~~~  480cfc0d		stlxrh w12, w13, [x0]
+0x~~~~~~~~~~~~~~~~  28003c0e		stnp w14, w15, [x0]
+0x~~~~~~~~~~~~~~~~  a8004410		stnp x16, x17, [x0]
+0x~~~~~~~~~~~~~~~~  29004c12		stp w18, w19, [x0]
+0x~~~~~~~~~~~~~~~~  28814c32		stp w18, w19, [x1], #8
+0x~~~~~~~~~~~~~~~~  29814c32		stp w18, w19, [x1, #8]!
+0x~~~~~~~~~~~~~~~~  a9005414		stp x20, x21, [x0]
+0x~~~~~~~~~~~~~~~~  a8815434		stp x20, x21, [x1], #16
+0x~~~~~~~~~~~~~~~~  a9815434		stp x20, x21, [x1, #16]!
+0x~~~~~~~~~~~~~~~~  b9000016		str w22, [x0]
+0x~~~~~~~~~~~~~~~~  b8004436		str w22, [x1], #4
+0x~~~~~~~~~~~~~~~~  b8004c36		str w22, [x1, #4]!
+0x~~~~~~~~~~~~~~~~  f9000017		str x23, [x0]
+0x~~~~~~~~~~~~~~~~  f8008437		str x23, [x1], #8
+0x~~~~~~~~~~~~~~~~  f8008c37		str x23, [x1, #8]!
+0x~~~~~~~~~~~~~~~~  39000018		strb w24, [x0]
+0x~~~~~~~~~~~~~~~~  38001438		strb w24, [x1], #1
+0x~~~~~~~~~~~~~~~~  38001c38		strb w24, [x1, #1]!
+0x~~~~~~~~~~~~~~~~  39000019		strb w25, [x0]
+0x~~~~~~~~~~~~~~~~  38001439		strb w25, [x1], #1
+0x~~~~~~~~~~~~~~~~  38001c39		strb w25, [x1, #1]!
+0x~~~~~~~~~~~~~~~~  7900001a		strh w26, [x0]
+0x~~~~~~~~~~~~~~~~  7800243a		strh w26, [x1], #2
+0x~~~~~~~~~~~~~~~~  78002c3a		strh w26, [x1, #2]!
+0x~~~~~~~~~~~~~~~~  7900001b		strh w27, [x0]
+0x~~~~~~~~~~~~~~~~  7800243b		strh w27, [x1], #2
+0x~~~~~~~~~~~~~~~~  78002c3b		strh w27, [x1, #2]!
+0x~~~~~~~~~~~~~~~~  b800701c		stur w28, [x0, #7]
+0x~~~~~~~~~~~~~~~~  f800f01d		stur x29, [x0, #15]
+0x~~~~~~~~~~~~~~~~  38001002		sturb w2, [x0, #1]
+0x~~~~~~~~~~~~~~~~  38001003		sturb w3, [x0, #1]
+0x~~~~~~~~~~~~~~~~  78003004		sturh w4, [x0, #3]
+0x~~~~~~~~~~~~~~~~  78003005		sturh w5, [x0, #3]
+0x~~~~~~~~~~~~~~~~  88262007		stxp w6, w7, w8, [x0]
+0x~~~~~~~~~~~~~~~~  c8292c0a		stxp w9, x10, x11, [x0]
+0x~~~~~~~~~~~~~~~~  880c7c0d		stxr w12, w13, [x0]
+0x~~~~~~~~~~~~~~~~  c80e7c0f		stxr w14, x15, [x0]
+0x~~~~~~~~~~~~~~~~  08107c11		stxrb w16, w17, [x0]
+0x~~~~~~~~~~~~~~~~  08127c13		stxrb w18, w19, [x0]
+0x~~~~~~~~~~~~~~~~  48147c15		stxrh w20, w21, [x0]
+0x~~~~~~~~~~~~~~~~  48167c17		stxrh w22, w23, [x0]
+0x~~~~~~~~~~~~~~~~  4b1a0338		sub w24, w25, w26
+0x~~~~~~~~~~~~~~~~  cb1d039b		sub x27, x28, x29
+0x~~~~~~~~~~~~~~~~  6b040062		subs w2, w3, w4
+0x~~~~~~~~~~~~~~~~  eb0700c5		subs x5, x6, x7
+0x~~~~~~~~~~~~~~~~  13001d28		sxtb w8, w9
+0x~~~~~~~~~~~~~~~~  93401d6a		sxtb x10, w11
+0x~~~~~~~~~~~~~~~~  13003dac		sxth w12, w13
+0x~~~~~~~~~~~~~~~~  93403dee		sxth x14, w15
+0x~~~~~~~~~~~~~~~~  13007e30		sbfx w16, w17, #0, #32
+0x~~~~~~~~~~~~~~~~  93407e72		sxtw x18, w19
+0x~~~~~~~~~~~~~~~~  6a15029f		tst w20, w21
+0x~~~~~~~~~~~~~~~~  ea1702df		tst x22, x23
+0x~~~~~~~~~~~~~~~~  53162b38		ubfiz w24, w25, #10, #11
+0x~~~~~~~~~~~~~~~~  d374337a		ubfiz x26, x27, #12, #13
+0x~~~~~~~~~~~~~~~~  530e3fbc		ubfx w28, w29, #14, #2
+0x~~~~~~~~~~~~~~~~  d3410862		ubfx x2, x3, #1, #2
+0x~~~~~~~~~~~~~~~~  530318a4		ubfx w4, w5, #3, #4
+0x~~~~~~~~~~~~~~~~  d34528e6		ubfx x6, x7, #5, #6
+0x~~~~~~~~~~~~~~~~  1aca0928		udiv w8, w9, w10
+0x~~~~~~~~~~~~~~~~  9acd098b		udiv x11, x12, x13
+0x~~~~~~~~~~~~~~~~  9bd87ef6		umulh x22, x23, x24
+0x~~~~~~~~~~~~~~~~  53001fbc		uxtb w28, w29
+0x~~~~~~~~~~~~~~~~  d3401c62		uxtb x2, w3
+0x~~~~~~~~~~~~~~~~  53003ca4		uxth w4, w5
+0x~~~~~~~~~~~~~~~~  d3403ce6		uxth x6, w7
+0x~~~~~~~~~~~~~~~~  53007d28		lsr w8, w9, #0
+0x~~~~~~~~~~~~~~~~  d3407d6a		ubfx x10, x11, #0, #32
+0x~~~~~~~~~~~~~~~~  7ef3d44d		fabd d13, d2, d19
+0x~~~~~~~~~~~~~~~~  7ebed548		fabd s8, s10, s30
+0x~~~~~~~~~~~~~~~~  1e60c021		fabs d1, d1
+0x~~~~~~~~~~~~~~~~  1e20c0f9		fabs s25, s7
+0x~~~~~~~~~~~~~~~~  7e70eee1		facge d1, d23, d16
+0x~~~~~~~~~~~~~~~~  7e21ee24		facge s4, s17, s1
+0x~~~~~~~~~~~~~~~~  7ef8eea2		facgt d2, d21, d24
+0x~~~~~~~~~~~~~~~~  7eacef4c		facgt s12, s26, s12
+0x~~~~~~~~~~~~~~~~  1e76296d		fadd d13, d11, d22
+0x~~~~~~~~~~~~~~~~  1e282a7b		fadd s27, s19, s8
+0x~~~~~~~~~~~~~~~~  1e6a24c0		fccmp d6, d10, #nzcv, hs
+0x~~~~~~~~~~~~~~~~  1e3417ad		fccmp s29, s20, #NZcV, ne
+0x~~~~~~~~~~~~~~~~  1e62e55e		fccmpe d10, d2, #NZCv, al
+0x~~~~~~~~~~~~~~~~  1e23547d		fccmpe s3, s3, #NZcV, pl
+0x~~~~~~~~~~~~~~~~  5e6ae513		fcmeq d19, d8, d10
+0x~~~~~~~~~~~~~~~~  5ee0da40		fcmeq d0, d18, #0.0
+0x~~~~~~~~~~~~~~~~  5e3ee481		fcmeq s1, s4, s30
+0x~~~~~~~~~~~~~~~~  5ea0dbb6		fcmeq s22, s29, #0.0
+0x~~~~~~~~~~~~~~~~  7e61e65b		fcmge d27, d18, d1
+0x~~~~~~~~~~~~~~~~  7ee0cb9f		fcmge d31, d28, #0.0
+0x~~~~~~~~~~~~~~~~  7e29e67f		fcmge s31, s19, s9
+0x~~~~~~~~~~~~~~~~  7ea0cb21		fcmge s1, s25, #0.0
+0x~~~~~~~~~~~~~~~~  7eefe432		fcmgt d18, d1, d15
+0x~~~~~~~~~~~~~~~~  5ee0cbe3		fcmgt d3, d31, #0.0
+0x~~~~~~~~~~~~~~~~  7ea2e72b		fcmgt s11, s25, s2
+0x~~~~~~~~~~~~~~~~  5ea0ca11		fcmgt s17, s16, #0.0
+0x~~~~~~~~~~~~~~~~  7ee0da38		fcmle d24, d17, #0.0
+0x~~~~~~~~~~~~~~~~  7ea0d90b		fcmle s11, s8, #0.0
+0x~~~~~~~~~~~~~~~~  5ee0ebe5		fcmlt d5, d31, #0.0
+0x~~~~~~~~~~~~~~~~  5ea0eaf2		fcmlt s18, s23, #0.0
+0x~~~~~~~~~~~~~~~~  1e782140		fcmp d10, d24
+0x~~~~~~~~~~~~~~~~  1e6021a8		fcmp d13, #0.0
+0x~~~~~~~~~~~~~~~~  1e262240		fcmp s18, s6
+0x~~~~~~~~~~~~~~~~  1e202208		fcmp s16, #0.0
+0x~~~~~~~~~~~~~~~~  1e712130		fcmpe d9, d17
+0x~~~~~~~~~~~~~~~~  1e6023b8		fcmpe d29, #0.0
+0x~~~~~~~~~~~~~~~~  1e312210		fcmpe s16, s17
+0x~~~~~~~~~~~~~~~~  1e2022d8		fcmpe s22, #0.0
+0x~~~~~~~~~~~~~~~~  1e73cdca		fcsel d10, d14, d19, gt
+0x~~~~~~~~~~~~~~~~  1e22ae56		fcsel s22, s18, s2, ge
+0x~~~~~~~~~~~~~~~~  1ee2c304		fcvt d4, h24
+0x~~~~~~~~~~~~~~~~  1e22c04b		fcvt d11, s2
+0x~~~~~~~~~~~~~~~~  1e63c128		fcvt h8, d9
+0x~~~~~~~~~~~~~~~~  1e23c02c		fcvt h12, s1
+0x~~~~~~~~~~~~~~~~  1e6243ec		fcvt s12, d31
+0x~~~~~~~~~~~~~~~~  1ee2433b		fcvt s27, h25
+0x~~~~~~~~~~~~~~~~  5e61ca1c		fcvtas d28, d16
+0x~~~~~~~~~~~~~~~~  5e21c8a3		fcvtas s3, s5
+0x~~~~~~~~~~~~~~~~  1e6403f2		fcvtas w18, d31
+0x~~~~~~~~~~~~~~~~  1e24031d		fcvtas w29, s24
+0x~~~~~~~~~~~~~~~~  9e640029		fcvtas x9, d1
+0x~~~~~~~~~~~~~~~~  9e24005e		fcvtas x30, s2
+0x~~~~~~~~~~~~~~~~  7e61c80e		fcvtau d14, d0
+0x~~~~~~~~~~~~~~~~  7e21c9df		fcvtau s31, s14
+0x~~~~~~~~~~~~~~~~  1e650050		fcvtau w16, d2
+0x~~~~~~~~~~~~~~~~  1e250012		fcvtau w18, s0
+0x~~~~~~~~~~~~~~~~  9e6500fa		fcvtau x26, d7
+0x~~~~~~~~~~~~~~~~  9e250279		fcvtau x25, s19
+0x~~~~~~~~~~~~~~~~  5e61bb3e		fcvtms d30, d25
+0x~~~~~~~~~~~~~~~~  5e21b9ec		fcvtms s12, s15
+0x~~~~~~~~~~~~~~~~  1e7000e9		fcvtms w9, d7
+0x~~~~~~~~~~~~~~~~  1e3000d3		fcvtms w19, s6
+0x~~~~~~~~~~~~~~~~  9e7000c6		fcvtms x6, d6
+0x~~~~~~~~~~~~~~~~  9e3000f6		fcvtms x22, s7
+0x~~~~~~~~~~~~~~~~  7e61b81b		fcvtmu d27, d0
+0x~~~~~~~~~~~~~~~~  7e21bac8		fcvtmu s8, s22
+0x~~~~~~~~~~~~~~~~  1e71027d		fcvtmu w29, d19
+0x~~~~~~~~~~~~~~~~  1e31001a		fcvtmu w26, s0
+0x~~~~~~~~~~~~~~~~  9e7100ad		fcvtmu x13, d5
+0x~~~~~~~~~~~~~~~~  9e310245		fcvtmu x5, s18
+0x~~~~~~~~~~~~~~~~  5e61a9fe		fcvtns d30, d15
+0x~~~~~~~~~~~~~~~~  5e21a96a		fcvtns s10, s11
+0x~~~~~~~~~~~~~~~~  1e6001f5		fcvtns w21, d15
+0x~~~~~~~~~~~~~~~~  1e200152		fcvtns w18, s10
+0x~~~~~~~~~~~~~~~~  9e600228		fcvtns x8, d17
+0x~~~~~~~~~~~~~~~~  9e200191		fcvtns x17, s12
+0x~~~~~~~~~~~~~~~~  7e61aaa0		fcvtnu d0, d21
+0x~~~~~~~~~~~~~~~~  7e21ab26		fcvtnu s6, s25
+0x~~~~~~~~~~~~~~~~  1e61017d		fcvtnu w29, d11
+0x~~~~~~~~~~~~~~~~  1e2103f9		fcvtnu w25, s31
+0x~~~~~~~~~~~~~~~~  9e61017e		fcvtnu x30, d11
+0x~~~~~~~~~~~~~~~~  9e21025b		fcvtnu x27, s18
+0x~~~~~~~~~~~~~~~~  5ee1aacb		fcvtps d11, d22
+0x~~~~~~~~~~~~~~~~  5ea1aa9d		fcvtps s29, s20
+0x~~~~~~~~~~~~~~~~  1e68032f		fcvtps w15, d25
+0x~~~~~~~~~~~~~~~~  1e2800f0		fcvtps w16, s7
+0x~~~~~~~~~~~~~~~~  9e68028d		fcvtps x13, d20
+0x~~~~~~~~~~~~~~~~  9e2802e3		fcvtps x3, s23
+0x~~~~~~~~~~~~~~~~  7ee1a838		fcvtpu d24, d1
+0x~~~~~~~~~~~~~~~~  7ea1ab0e		fcvtpu s14, s24
+0x~~~~~~~~~~~~~~~~  1e6903ba		fcvtpu w26, d29
+0x~~~~~~~~~~~~~~~~  1e29035f		fcvtpu wzr, s26
+0x~~~~~~~~~~~~~~~~  9e6900db		fcvtpu x27, d6
+0x~~~~~~~~~~~~~~~~  9e2901dd		fcvtpu x29, s14
+0x~~~~~~~~~~~~~~~~  7e61698c		fcvtxn s12, d12
+0x~~~~~~~~~~~~~~~~  5ee1b80f		fcvtzs d15, d0
+0x~~~~~~~~~~~~~~~~  5f56fc8d		fcvtzs d13, d4, #42
+0x~~~~~~~~~~~~~~~~  5ea1b968		fcvtzs s8, s11
+0x~~~~~~~~~~~~~~~~  5f27fcdf		fcvtzs s31, s6, #25
+0x~~~~~~~~~~~~~~~~  1e780126		fcvtzs w6, d9
+0x~~~~~~~~~~~~~~~~  1e58b159		fcvtzs w25, d10, #20
+0x~~~~~~~~~~~~~~~~  1e380029		fcvtzs w9, s1
+0x~~~~~~~~~~~~~~~~  1e188bb1		fcvtzs w17, s29, #30
+0x~~~~~~~~~~~~~~~~  9e780053		fcvtzs x19, d2
+0x~~~~~~~~~~~~~~~~  9e58fdd6		fcvtzs x22, d14, #1
+0x~~~~~~~~~~~~~~~~  9e38028e		fcvtzs x14, s20
+0x~~~~~~~~~~~~~~~~  9e187fc3		fcvtzs x3, s30, #33
+0x~~~~~~~~~~~~~~~~  7ee1b9fc		fcvtzu d28, d15
+0x~~~~~~~~~~~~~~~~  7f7dfc80		fcvtzu d0, d4, #3
+0x~~~~~~~~~~~~~~~~  7ea1b8a2		fcvtzu s2, s5
+0x~~~~~~~~~~~~~~~~  7f22fc04		fcvtzu s4, s0, #30
+0x~~~~~~~~~~~~~~~~  1e79008b		fcvtzu w11, d4
+0x~~~~~~~~~~~~~~~~  1e598307		fcvtzu w7, d24, #32
+0x~~~~~~~~~~~~~~~~  1e390312		fcvtzu w18, s24
+0x~~~~~~~~~~~~~~~~  1e19f36e		fcvtzu w14, s27, #4
+0x~~~~~~~~~~~~~~~~  9e790176		fcvtzu x22, d11
+0x~~~~~~~~~~~~~~~~  9e593368		fcvtzu x8, d27, #52
+0x~~~~~~~~~~~~~~~~  9e390287		fcvtzu x7, s20
+0x~~~~~~~~~~~~~~~~  9e1950f6		fcvtzu x22, s7, #44
+0x~~~~~~~~~~~~~~~~  1e6f19c6		fdiv d6, d14, d15
+0x~~~~~~~~~~~~~~~~  1e3918ba		fdiv s26, s5, s25
+0x~~~~~~~~~~~~~~~~  1f4c7b52		fmadd d18, d26, d12, d30
+0x~~~~~~~~~~~~~~~~  1f1c112d		fmadd s13, s9, s28, s4
+0x~~~~~~~~~~~~~~~~  1e6548ac		fmax d12, d5, d5
+0x~~~~~~~~~~~~~~~~  1e264b8c		fmax s12, s28, s6
+0x~~~~~~~~~~~~~~~~  1e62689c		fmaxnm d28, d4, d2
+0x~~~~~~~~~~~~~~~~  1e286946		fmaxnm s6, s10, s8
+0x~~~~~~~~~~~~~~~~  1e725a94		fmin d20, d20, d18
+0x~~~~~~~~~~~~~~~~  1e3059a7		fmin s7, s13, s16
+0x~~~~~~~~~~~~~~~~  1e7e79d3		fminnm d19, d14, d30
+0x~~~~~~~~~~~~~~~~  1e217820		fminnm s0, s1, s1
+0x~~~~~~~~~~~~~~~~  1e6040cd		fmov d13, d6
+0x~~~~~~~~~~~~~~~~  9e670222		fmov d2, x17
+0x~~~~~~~~~~~~~~~~  1e709008		fmov d8, #0x84 (-2.5000)
+0x~~~~~~~~~~~~~~~~  1e204065		fmov s5, s3
+0x~~~~~~~~~~~~~~~~  1e270299		fmov s25, w20
+0x~~~~~~~~~~~~~~~~  1e20f015		fmov s21, #0x7 (2.8750)
+0x~~~~~~~~~~~~~~~~  1e260312		fmov w18, s24
+0x~~~~~~~~~~~~~~~~  9e660052		fmov x18, d2
+0x~~~~~~~~~~~~~~~~  1f43cfd4		fmsub d20, d30, d3, d19
+0x~~~~~~~~~~~~~~~~  1f04b265		fmsub s5, s19, s4, s12
+0x~~~~~~~~~~~~~~~~  1e770b7e		fmul d30, d27, d23
+0x~~~~~~~~~~~~~~~~  1e2f0a39		fmul s25, s17, s15
+0x~~~~~~~~~~~~~~~~  5e61de24		fmulx d4, d17, d1
+0x~~~~~~~~~~~~~~~~  5e24df2e		fmulx s14, s25, s4
+0x~~~~~~~~~~~~~~~~  1e61400f		fneg d15, d0
+0x~~~~~~~~~~~~~~~~  1e2141ee		fneg s14, s15
+0x~~~~~~~~~~~~~~~~  1f767e00		fnmadd d0, d16, d22, d31
+0x~~~~~~~~~~~~~~~~  1f3a4a40		fnmadd s0, s18, s26, s18
+0x~~~~~~~~~~~~~~~~  1f6fd593		fnmsub d19, d12, d15, d21
+0x~~~~~~~~~~~~~~~~  1f2be81d		fnmsub s29, s0, s11, s26
+0x~~~~~~~~~~~~~~~~  1e618a7f		fnmul d31, d19, d1
+0x~~~~~~~~~~~~~~~~  1e318872		fnmul s18, s3, s17
+0x~~~~~~~~~~~~~~~~  5ee1daa7		frecpe d7, d21
+0x~~~~~~~~~~~~~~~~  5ea1da3d		frecpe s29, s17
+0x~~~~~~~~~~~~~~~~  5e71ff4b		frecps d11, d26, d17
+0x~~~~~~~~~~~~~~~~  5e21ff72		frecps s18, s27, s1
+0x~~~~~~~~~~~~~~~~  5ee1fa4f		frecpx d15, d18
+0x~~~~~~~~~~~~~~~~  5ea1f945		frecpx s5, s10
+0x~~~~~~~~~~~~~~~~  1e6643d0		frinta d16, d30
+0x~~~~~~~~~~~~~~~~  1e2642c1		frinta s1, s22
+0x~~~~~~~~~~~~~~~~  1e67c3b3		frinti d19, d29
+0x~~~~~~~~~~~~~~~~  1e27c2ae		frinti s14, s21
+0x~~~~~~~~~~~~~~~~  1e6543d4		frintm d20, d30
+0x~~~~~~~~~~~~~~~~  1e254201		frintm s1, s16
+0x~~~~~~~~~~~~~~~~  1e64403e		frintn d30, d1
+0x~~~~~~~~~~~~~~~~  1e244158		frintn s24, s10
+0x~~~~~~~~~~~~~~~~  1e64c284		frintp d4, d20
+0x~~~~~~~~~~~~~~~~  1e24c06d		frintp s13, s3
+0x~~~~~~~~~~~~~~~~  1e67428d		frintx d13, d20
+0x~~~~~~~~~~~~~~~~  1e2740f1		frintx s17, s7
+0x~~~~~~~~~~~~~~~~  1e65c100		frintz d0, d8
+0x~~~~~~~~~~~~~~~~  1e25c3af		frintz s15, s29
+0x~~~~~~~~~~~~~~~~  7ee1d955		frsqrte d21, d10
+0x~~~~~~~~~~~~~~~~  7ea1db31		frsqrte s17, s25
+0x~~~~~~~~~~~~~~~~  5ef1ffa4		frsqrts d4, d29, d17
+0x~~~~~~~~~~~~~~~~  5eb8fc6e		frsqrts s14, s3, s24
+0x~~~~~~~~~~~~~~~~  1e61c22e		fsqrt d14, d17
+0x~~~~~~~~~~~~~~~~  1e21c1c4		fsqrt s4, s14
+0x~~~~~~~~~~~~~~~~  1e673a6d		fsub d13, d19, d7
+0x~~~~~~~~~~~~~~~~  1e3b3aa3		fsub s3, s21, s27
+0x~~~~~~~~~~~~~~~~  5e61da1f		scvtf d31, d16
+0x~~~~~~~~~~~~~~~~  5f68e7fa		scvtf d26, d31, #24
+0x~~~~~~~~~~~~~~~~  1e620206		scvtf d6, w16
+0x~~~~~~~~~~~~~~~~  1e42ea85		scvtf d5, w20, #6
+0x~~~~~~~~~~~~~~~~  9e620110		scvtf d16, x8
+0x~~~~~~~~~~~~~~~~  9e42d90f		scvtf d15, x8, #10
+0x~~~~~~~~~~~~~~~~  5e21d887		scvtf s7, s4
+0x~~~~~~~~~~~~~~~~  5f32e5e8		scvtf s8, s15, #14
+0x~~~~~~~~~~~~~~~~  1e22015d		scvtf s29, w10
+0x~~~~~~~~~~~~~~~~  1e02d6af		scvtf s15, w21, #11
+0x~~~~~~~~~~~~~~~~  9e22035b		scvtf s27, x26
+0x~~~~~~~~~~~~~~~~  9e02699a		scvtf s26, x12, #38
+0x~~~~~~~~~~~~~~~~  7e61d920		ucvtf d0, d9
+0x~~~~~~~~~~~~~~~~  7f51e6c5		ucvtf d5, d22, #47
+0x~~~~~~~~~~~~~~~~  1e63037e		ucvtf d30, w27
+0x~~~~~~~~~~~~~~~~  1e43fe63		ucvtf d3, w19, #1
+0x~~~~~~~~~~~~~~~~  9e6302bc		ucvtf d28, x21
+0x~~~~~~~~~~~~~~~~  9e4377db		ucvtf d27, x30, #35
+0x~~~~~~~~~~~~~~~~  7e21d8ab		ucvtf s11, s5
+0x~~~~~~~~~~~~~~~~  7f32e6e0		ucvtf s0, s23, #14
+0x~~~~~~~~~~~~~~~~  1e230274		ucvtf s20, w19
+0x~~~~~~~~~~~~~~~~  1e03bad5		ucvtf s21, w22, #18
+0x~~~~~~~~~~~~~~~~  9e2301a6		ucvtf s6, x13
+0x~~~~~~~~~~~~~~~~  9e03ac47		ucvtf s7, x2, #21
+0x~~~~~~~~~~~~~~~~  5ee0b813		abs d19, d0
+0x~~~~~~~~~~~~~~~~  4e20b970		abs v16.16b, v11.16b
+0x~~~~~~~~~~~~~~~~  4ee0bbe0		abs v0.2d, v31.2d
+0x~~~~~~~~~~~~~~~~  0ea0bb3b		abs v27.2s, v25.2s
+0x~~~~~~~~~~~~~~~~  0e60bb75		abs v21.4h, v27.4h
+0x~~~~~~~~~~~~~~~~  4ea0b830		abs v16.4s, v1.4s
+0x~~~~~~~~~~~~~~~~  0e20b8bf		abs v31.8b, v5.8b
+0x~~~~~~~~~~~~~~~~  4e60b9bd		abs v29.8h, v13.8h
+0x~~~~~~~~~~~~~~~~  5ef184aa		add d10, d5, d17
+0x~~~~~~~~~~~~~~~~  4e3785ff		add v31.16b, v15.16b, v23.16b
+0x~~~~~~~~~~~~~~~~  4eee87ea		add v10.2d, v31.2d, v14.2d
+0x~~~~~~~~~~~~~~~~  0eb385cf		add v15.2s, v14.2s, v19.2s
+0x~~~~~~~~~~~~~~~~  0e7186fb		add v27.4h, v23.4h, v17.4h
+0x~~~~~~~~~~~~~~~~  4ebd8799		add v25.4s, v28.4s, v29.4s
+0x~~~~~~~~~~~~~~~~  0e3284ed		add v13.8b, v7.8b, v18.8b
+0x~~~~~~~~~~~~~~~~  4e618444		add v4.8h, v2.8h, v1.8h
+0x~~~~~~~~~~~~~~~~  0eaf41ca		addhn v10.2s, v14.2d, v15.2d
+0x~~~~~~~~~~~~~~~~  0e7a43ca		addhn v10.4h, v30.4s, v26.4s
+0x~~~~~~~~~~~~~~~~  0e36419f		addhn v31.8b, v12.8h, v22.8h
+0x~~~~~~~~~~~~~~~~  4e3442b0		addhn2 v16.16b, v21.8h, v20.8h
+0x~~~~~~~~~~~~~~~~  4eb14040		addhn2 v0.4s, v2.2d, v17.2d
+0x~~~~~~~~~~~~~~~~  4e7140ff		addhn2 v31.8h, v7.4s, v17.4s
+0x~~~~~~~~~~~~~~~~  5ef1ba6e		addp d14, v19.2d
+0x~~~~~~~~~~~~~~~~  4e3cbd03		addp v3.16b, v8.16b, v28.16b
+0x~~~~~~~~~~~~~~~~  4ef1bca8		addp v8.2d, v5.2d, v17.2d
+0x~~~~~~~~~~~~~~~~  0ebabfd6		addp v22.2s, v30.2s, v26.2s
+0x~~~~~~~~~~~~~~~~  0e6ebf1d		addp v29.4h, v24.4h, v14.4h
+0x~~~~~~~~~~~~~~~~  4eb8bf5e		addp v30.4s, v26.4s, v24.4s
+0x~~~~~~~~~~~~~~~~  0e27bf4c		addp v12.8b, v26.8b, v7.8b
+0x~~~~~~~~~~~~~~~~  4e6cbd11		addp v17.8h, v8.8h, v12.8h
+0x~~~~~~~~~~~~~~~~  4e31bafb		addv b27, v23.16b
+0x~~~~~~~~~~~~~~~~  0e31ba8c		addv b12, v20.8b
+0x~~~~~~~~~~~~~~~~  0e71bbdb		addv h27, v30.4h
+0x~~~~~~~~~~~~~~~~  4e71b9d3		addv h19, v14.8h
+0x~~~~~~~~~~~~~~~~  4eb1bb6e		addv s14, v27.4s
+0x~~~~~~~~~~~~~~~~  4e3b1d0a		and v10.16b, v8.16b, v27.16b
+0x~~~~~~~~~~~~~~~~  0e301c25		and v5.8b, v1.8b, v16.8b
+0x~~~~~~~~~~~~~~~~  4e781c7a		bic v26.16b, v3.16b, v24.16b
+0x~~~~~~~~~~~~~~~~  2f075487		bic v7.2s, #0xe4, lsl #16
+0x~~~~~~~~~~~~~~~~  2f01b47c		bic v28.4h, #0x23, lsl #8
+0x~~~~~~~~~~~~~~~~  6f05159d		bic v29.4s, #0xac, lsl #0
+0x~~~~~~~~~~~~~~~~  0e751fec		bic v12.8b, v31.8b, v21.8b
+0x~~~~~~~~~~~~~~~~  6f049712		bic v18.8h, #0x98, lsl #0
+0x~~~~~~~~~~~~~~~~  6ee81f4c		bif v12.16b, v26.16b, v8.16b
+0x~~~~~~~~~~~~~~~~  2efb1ee2		bif v2.8b, v23.8b, v27.8b
+0x~~~~~~~~~~~~~~~~  6ead1c68		bit v8.16b, v3.16b, v13.16b
+0x~~~~~~~~~~~~~~~~  2eb71ca5		bit v5.8b, v5.8b, v23.8b
+0x~~~~~~~~~~~~~~~~  6e771fe9		bsl v9.16b, v31.16b, v23.16b
+0x~~~~~~~~~~~~~~~~  2e631cee		bsl v14.8b, v7.8b, v3.8b
+0x~~~~~~~~~~~~~~~~  4e2048bd		cls v29.16b, v5.16b
+0x~~~~~~~~~~~~~~~~  0ea04815		cls v21.2s, v0.2s
+0x~~~~~~~~~~~~~~~~  0e604981		cls v1.4h, v12.4h
+0x~~~~~~~~~~~~~~~~  4ea0495b		cls v27.4s, v10.4s
+0x~~~~~~~~~~~~~~~~  0e204893		cls v19.8b, v4.8b
+0x~~~~~~~~~~~~~~~~  4e6049cf		cls v15.8h, v14.8h
+0x~~~~~~~~~~~~~~~~  6e204881		clz v1.16b, v4.16b
+0x~~~~~~~~~~~~~~~~  2ea04a3b		clz v27.2s, v17.2s
+0x~~~~~~~~~~~~~~~~  2e604929		clz v9.4h, v9.4h
+0x~~~~~~~~~~~~~~~~  6ea049ff		clz v31.4s, v15.4s
+0x~~~~~~~~~~~~~~~~  2e204a6e		clz v14.8b, v19.8b
+0x~~~~~~~~~~~~~~~~  6e604966		clz v6.8h, v11.8h
+0x~~~~~~~~~~~~~~~~  7efd8cb2		cmeq d18, d5, d29
+0x~~~~~~~~~~~~~~~~  5ee09bee		cmeq d14, d31, #0
+0x~~~~~~~~~~~~~~~~  6e368c73		cmeq v19.16b, v3.16b, v22.16b
+0x~~~~~~~~~~~~~~~~  4e20992f		cmeq v15.16b, v9.16b, #0
+0x~~~~~~~~~~~~~~~~  6eea8e0c		cmeq v12.2d, v16.2d, v10.2d
+0x~~~~~~~~~~~~~~~~  4ee09ac8		cmeq v8.2d, v22.2d, #0
+0x~~~~~~~~~~~~~~~~  2ea98c62		cmeq v2.2s, v3.2s, v9.2s
+0x~~~~~~~~~~~~~~~~  0ea09b30		cmeq v16.2s, v25.2s, #0
+0x~~~~~~~~~~~~~~~~  2e748ee6		cmeq v6.4h, v23.4h, v20.4h
+0x~~~~~~~~~~~~~~~~  0e6099b0		cmeq v16.4h, v13.4h, #0
+0x~~~~~~~~~~~~~~~~  6ea28e35		cmeq v21.4s, v17.4s, v2.4s
+0x~~~~~~~~~~~~~~~~  4ea09b26		cmeq v6.4s, v25.4s, #0
+0x~~~~~~~~~~~~~~~~  2e228db0		cmeq v16.8b, v13.8b, v2.8b
+0x~~~~~~~~~~~~~~~~  0e209a15		cmeq v21.8b, v16.8b, #0
+0x~~~~~~~~~~~~~~~~  6e798cf4		cmeq v20.8h, v7.8h, v25.8h
+0x~~~~~~~~~~~~~~~~  4e60991a		cmeq v26.8h, v8.8h, #0
+0x~~~~~~~~~~~~~~~~  5eff3db0		cmge d16, d13, d31
+0x~~~~~~~~~~~~~~~~  7ee08b19		cmge d25, d24, #0
+0x~~~~~~~~~~~~~~~~  4e313e71		cmge v17.16b, v19.16b, v17.16b
+0x~~~~~~~~~~~~~~~~  6e208bd6		cmge v22.16b, v30.16b, #0
+0x~~~~~~~~~~~~~~~~  4efa3e9c		cmge v28.2d, v20.2d, v26.2d
+0x~~~~~~~~~~~~~~~~  6ee08ae6		cmge v6.2d, v23.2d, #0
+0x~~~~~~~~~~~~~~~~  0ea33ed9		cmge v25.2s, v22.2s, v3.2s
+0x~~~~~~~~~~~~~~~~  2ea08975		cmge v21.2s, v11.2s, #0
+0x~~~~~~~~~~~~~~~~  0e6c3c70		cmge v16.4h, v3.4h, v12.4h
+0x~~~~~~~~~~~~~~~~  2e608937		cmge v23.4h, v9.4h, #0
+0x~~~~~~~~~~~~~~~~  4eab3c47		cmge v7.4s, v2.4s, v11.4s
+0x~~~~~~~~~~~~~~~~  6ea08ac0		cmge v0.4s, v22.4s, #0
+0x~~~~~~~~~~~~~~~~  0e293fca		cmge v10.8b, v30.8b, v9.8b
+0x~~~~~~~~~~~~~~~~  2e208915		cmge v21.8b, v8.8b, #0
+0x~~~~~~~~~~~~~~~~  4e7a3ce2		cmge v2.8h, v7.8h, v26.8h
+0x~~~~~~~~~~~~~~~~  6e608953		cmge v19.8h, v10.8h, #0
+0x~~~~~~~~~~~~~~~~  5ee135a6		cmgt d6, d13, d1
+0x~~~~~~~~~~~~~~~~  5ee08b1e		cmgt d30, d24, #0
+0x~~~~~~~~~~~~~~~~  4e3b3734		cmgt v20.16b, v25.16b, v27.16b
+0x~~~~~~~~~~~~~~~~  4e208b20		cmgt v0.16b, v25.16b, #0
+0x~~~~~~~~~~~~~~~~  4ee13736		cmgt v22.2d, v25.2d, v1.2d
+0x~~~~~~~~~~~~~~~~  4ee08a10		cmgt v16.2d, v16.2d, #0
+0x~~~~~~~~~~~~~~~~  0eaf3525		cmgt v5.2s, v9.2s, v15.2s
+0x~~~~~~~~~~~~~~~~  0ea08a4c		cmgt v12.2s, v18.2s, #0
+0x~~~~~~~~~~~~~~~~  0e6b365c		cmgt v28.4h, v18.4h, v11.4h
+0x~~~~~~~~~~~~~~~~  0e608876		cmgt v22.4h, v3.4h, #0
+0x~~~~~~~~~~~~~~~~  4ebb3565		cmgt v5.4s, v11.4s, v27.4s
+0x~~~~~~~~~~~~~~~~  4ea08a8d		cmgt v13.4s, v20.4s, #0
+0x~~~~~~~~~~~~~~~~  0e2737fb		cmgt v27.8b, v31.8b, v7.8b
+0x~~~~~~~~~~~~~~~~  0e208805		cmgt v5.8b, v0.8b, #0
+0x~~~~~~~~~~~~~~~~  4e6d3796		cmgt v22.8h, v28.8h, v13.8h
+0x~~~~~~~~~~~~~~~~  4e608846		cmgt v6.8h, v2.8h, #0
+0x~~~~~~~~~~~~~~~~  7ef63515		cmhi d21, d8, d22
+0x~~~~~~~~~~~~~~~~  6e333672		cmhi v18.16b, v19.16b, v19.16b
+0x~~~~~~~~~~~~~~~~  6ef53407		cmhi v7.2d, v0.2d, v21.2d
+0x~~~~~~~~~~~~~~~~  2ea0366f		cmhi v15.2s, v19.2s, v0.2s
+0x~~~~~~~~~~~~~~~~  2e6c34ff		cmhi v31.4h, v7.4h, v12.4h
+0x~~~~~~~~~~~~~~~~  6eb63609		cmhi v9.4s, v16.4s, v22.4s
+0x~~~~~~~~~~~~~~~~  2e3c3707		cmhi v7.8b, v24.8b, v28.8b
+0x~~~~~~~~~~~~~~~~  6e79354b		cmhi v11.8h, v10.8h, v25.8h
+0x~~~~~~~~~~~~~~~~  7ef13d81		cmhs d1, d12, d17
+0x~~~~~~~~~~~~~~~~  6e3e3f35		cmhs v21.16b, v25.16b, v30.16b
+0x~~~~~~~~~~~~~~~~  6efa3c48		cmhs v8.2d, v2.2d, v26.2d
+0x~~~~~~~~~~~~~~~~  2ebd3ec1		cmhs v1.2s, v22.2s, v29.2s
+0x~~~~~~~~~~~~~~~~  2e7e3fda		cmhs v26.4h, v30.4h, v30.4h
+0x~~~~~~~~~~~~~~~~  6eb03e93		cmhs v19.4s, v20.4s, v16.4s
+0x~~~~~~~~~~~~~~~~  2e3a3c61		cmhs v1.8b, v3.8b, v26.8b
+0x~~~~~~~~~~~~~~~~  6e683f94		cmhs v20.8h, v28.8h, v8.8h
+0x~~~~~~~~~~~~~~~~  7ee09b1e		cmle d30, d24, #0
+0x~~~~~~~~~~~~~~~~  6e209860		cmle v0.16b, v3.16b, #0
+0x~~~~~~~~~~~~~~~~  6ee09bc2		cmle v2.2d, v30.2d, #0
+0x~~~~~~~~~~~~~~~~  2ea09947		cmle v7.2s, v10.2s, #0
+0x~~~~~~~~~~~~~~~~  2e609be9		cmle v9.4h, v31.4h, #0
+0x~~~~~~~~~~~~~~~~  6ea09a49		cmle v9.4s, v18.4s, #0
+0x~~~~~~~~~~~~~~~~  2e209bf5		cmle v21.8b, v31.8b, #0
+0x~~~~~~~~~~~~~~~~  6e609abd		cmle v29.8h, v21.8h, #0
+0x~~~~~~~~~~~~~~~~  5ee0aaf9		cmlt d25, d23, #0
+0x~~~~~~~~~~~~~~~~  4e20aaa7		cmlt v7.16b, v21.16b, #0
+0x~~~~~~~~~~~~~~~~  4ee0abc7		cmlt v7.2d, v30.2d, #0
+0x~~~~~~~~~~~~~~~~  0ea0ab99		cmlt v25.2s, v28.2s, #0
+0x~~~~~~~~~~~~~~~~  0e60a960		cmlt v0.4h, v11.4h, #0
+0x~~~~~~~~~~~~~~~~  4ea0a8b8		cmlt v24.4s, v5.4s, #0
+0x~~~~~~~~~~~~~~~~  0e20a97a		cmlt v26.8b, v11.8b, #0
+0x~~~~~~~~~~~~~~~~  4e60aaa1		cmlt v1.8h, v21.8h, #0
+0x~~~~~~~~~~~~~~~~  5efe8efc		cmtst d28, d23, d30
+0x~~~~~~~~~~~~~~~~  4e3f8cda		cmtst v26.16b, v6.16b, v31.16b
+0x~~~~~~~~~~~~~~~~  4ee48ea1		cmtst v1.2d, v21.2d, v4.2d
+0x~~~~~~~~~~~~~~~~  0eb48f5b		cmtst v27.2s, v26.2s, v20.2s
+0x~~~~~~~~~~~~~~~~  0e728c1a		cmtst v26.4h, v0.4h, v18.4h
+0x~~~~~~~~~~~~~~~~  4ea48e19		cmtst v25.4s, v16.4s, v4.4s
+0x~~~~~~~~~~~~~~~~  0e298d4b		cmtst v11.8b, v10.8b, v9.8b
+0x~~~~~~~~~~~~~~~~  4e618c40		cmtst v0.8h, v2.8h, v1.8h
+0x~~~~~~~~~~~~~~~~  4e2059f9		cnt v25.16b, v15.16b
+0x~~~~~~~~~~~~~~~~  0e2058dc		cnt v28.8b, v6.8b
+0x~~~~~~~~~~~~~~~~  4e0f04e6		dup v6.16b, v7.b[7]
+0x~~~~~~~~~~~~~~~~  4e010e89		dup v9.16b, w20
+0x~~~~~~~~~~~~~~~~  4e1805ac		dup v12.2d, v13.d[1]
+0x~~~~~~~~~~~~~~~~  4e080fe9		dup v9.2d, xzr
+0x~~~~~~~~~~~~~~~~  0e140744		dup v4.2s, v26.s[2]
+0x~~~~~~~~~~~~~~~~  0e040d83		dup v3.2s, w12
+0x~~~~~~~~~~~~~~~~  0e1e04b6		dup v22.4h, v5.h[7]
+0x~~~~~~~~~~~~~~~~  0e020f30		dup v16.4h, w25
+0x~~~~~~~~~~~~~~~~  4e140554		dup v20.4s, v10.s[2]
+0x~~~~~~~~~~~~~~~~  4e040cea		dup v10.4s, w7
+0x~~~~~~~~~~~~~~~~  0e0507de		dup v30.8b, v30.b[2]
+0x~~~~~~~~~~~~~~~~  0e010dff		dup v31.8b, w15
+0x~~~~~~~~~~~~~~~~  4e12063c		dup v28.8h, v17.h[4]
+0x~~~~~~~~~~~~~~~~  4e020c62		dup v2.8h, w3
+0x~~~~~~~~~~~~~~~~  6e231f3d		eor v29.16b, v25.16b, v3.16b
+0x~~~~~~~~~~~~~~~~  2e3c1e03		eor v3.8b, v16.8b, v28.8b
+0x~~~~~~~~~~~~~~~~  6e060b41		ext v1.16b, v26.16b, v6.16b, #1
+0x~~~~~~~~~~~~~~~~  2e010bc2		ext v2.8b, v30.8b, v1.8b, #1
+0x~~~~~~~~~~~~~~~~  4c402012		ld1 {v18.16b, v19.16b, v20.16b, v21.16b}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc22037		ld1 {v23.16b, v24.16b, v25.16b, v26.16b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf2025		ld1 {v5.16b, v6.16b, v7.16b, v8.16b}, [x1], #64
+0x~~~~~~~~~~~~~~~~  4c406012		ld1 {v18.16b, v19.16b, v20.16b}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc2602d		ld1 {v13.16b, v14.16b, v15.16b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf6033		ld1 {v19.16b, v20.16b, v21.16b}, [x1], #48
+0x~~~~~~~~~~~~~~~~  4c40a011		ld1 {v17.16b, v18.16b}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc2a034		ld1 {v20.16b, v21.16b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdfa03c		ld1 {v28.16b, v29.16b}, [x1], #32
+0x~~~~~~~~~~~~~~~~  4c40701d		ld1 {v29.16b}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc27035		ld1 {v21.16b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf7024		ld1 {v4.16b}, [x1], #16
+0x~~~~~~~~~~~~~~~~  0c402c04		ld1 {v4.1d, v5.1d, v6.1d, v7.1d}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc22c31		ld1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf2c3c		ld1 {v28.1d, v29.1d, v30.1d, v31.1d}, [x1], #32
+0x~~~~~~~~~~~~~~~~  0c406c14		ld1 {v20.1d, v21.1d, v22.1d}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc26c33		ld1 {v19.1d, v20.1d, v21.1d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf6c2c		ld1 {v12.1d, v13.1d, v14.1d}, [x1], #24
+0x~~~~~~~~~~~~~~~~  0c40ac1d		ld1 {v29.1d, v30.1d}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc2ac3f		ld1 {v31.1d, v0.1d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdfac23		ld1 {v3.1d, v4.1d}, [x1], #16
+0x~~~~~~~~~~~~~~~~  0c407c1c		ld1 {v28.1d}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc27c2b		ld1 {v11.1d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf7c3d		ld1 {v29.1d}, [x1], #8
+0x~~~~~~~~~~~~~~~~  4c402c1c		ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc22c28		ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf2c2e		ld1 {v14.2d, v15.2d, v16.2d, v17.2d}, [x1], #64
+0x~~~~~~~~~~~~~~~~  4c406c1a		ld1 {v26.2d, v27.2d, v28.2d}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc26c25		ld1 {v5.2d, v6.2d, v7.2d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf6c3a		ld1 {v26.2d, v27.2d, v28.2d}, [x1], #48
+0x~~~~~~~~~~~~~~~~  4c40ac12		ld1 {v18.2d, v19.2d}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc2ac35		ld1 {v21.2d, v22.2d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdfac31		ld1 {v17.2d, v18.2d}, [x1], #32
+0x~~~~~~~~~~~~~~~~  4c407c05		ld1 {v5.2d}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc27c26		ld1 {v6.2d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf7c2f		ld1 {v15.2d}, [x1], #16
+0x~~~~~~~~~~~~~~~~  0c40281e		ld1 {v30.2s, v31.2s, v0.2s, v1.2s}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc22838		ld1 {v24.2s, v25.2s, v26.2s, v27.2s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf283b		ld1 {v27.2s, v28.2s, v29.2s, v30.2s}, [x1], #32
+0x~~~~~~~~~~~~~~~~  0c40680b		ld1 {v11.2s, v12.2s, v13.2s}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc26828		ld1 {v8.2s, v9.2s, v10.2s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf683f		ld1 {v31.2s, v0.2s, v1.2s}, [x1], #24
+0x~~~~~~~~~~~~~~~~  0c40a800		ld1 {v0.2s, v1.2s}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc2a82d		ld1 {v13.2s, v14.2s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdfa823		ld1 {v3.2s, v4.2s}, [x1], #16
+0x~~~~~~~~~~~~~~~~  0c40781a		ld1 {v26.2s}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc27820		ld1 {v0.2s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf782b		ld1 {v11.2s}, [x1], #8
+0x~~~~~~~~~~~~~~~~  0c402410		ld1 {v16.4h, v17.4h, v18.4h, v19.4h}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc22438		ld1 {v24.4h, v25.4h, v26.4h, v27.4h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf2421		ld1 {v1.4h, v2.4h, v3.4h, v4.4h}, [x1], #32
+0x~~~~~~~~~~~~~~~~  0c40641e		ld1 {v30.4h, v31.4h, v0.4h}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc26439		ld1 {v25.4h, v26.4h, v27.4h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf6423		ld1 {v3.4h, v4.4h, v5.4h}, [x1], #24
+0x~~~~~~~~~~~~~~~~  0c40a403		ld1 {v3.4h, v4.4h}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc2a423		ld1 {v3.4h, v4.4h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdfa437		ld1 {v23.4h, v24.4h}, [x1], #16
+0x~~~~~~~~~~~~~~~~  0c40741a		ld1 {v26.4h}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc27421		ld1 {v1.4h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf742e		ld1 {v14.4h}, [x1], #8
+0x~~~~~~~~~~~~~~~~  4c40281a		ld1 {v26.4s, v27.4s, v28.4s, v29.4s}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc2283c		ld1 {v28.4s, v29.4s, v30.4s, v31.4s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf2824		ld1 {v4.4s, v5.4s, v6.4s, v7.4s}, [x1], #64
+0x~~~~~~~~~~~~~~~~  4c406802		ld1 {v2.4s, v3.4s, v4.4s}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc26836		ld1 {v22.4s, v23.4s, v24.4s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf682f		ld1 {v15.4s, v16.4s, v17.4s}, [x1], #48
+0x~~~~~~~~~~~~~~~~  4c40a814		ld1 {v20.4s, v21.4s}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc2a83e		ld1 {v30.4s, v31.4s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdfa82b		ld1 {v11.4s, v12.4s}, [x1], #32
+0x~~~~~~~~~~~~~~~~  4c40780f		ld1 {v15.4s}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc2782c		ld1 {v12.4s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf7820		ld1 {v0.4s}, [x1], #16
+0x~~~~~~~~~~~~~~~~  0c402011		ld1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc22025		ld1 {v5.8b, v6.8b, v7.8b, v8.8b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf2029		ld1 {v9.8b, v10.8b, v11.8b, v12.8b}, [x1], #32
+0x~~~~~~~~~~~~~~~~  0c406004		ld1 {v4.8b, v5.8b, v6.8b}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc26022		ld1 {v2.8b, v3.8b, v4.8b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf602c		ld1 {v12.8b, v13.8b, v14.8b}, [x1], #24
+0x~~~~~~~~~~~~~~~~  0c40a00a		ld1 {v10.8b, v11.8b}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc2a02b		ld1 {v11.8b, v12.8b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdfa03b		ld1 {v27.8b, v28.8b}, [x1], #16
+0x~~~~~~~~~~~~~~~~  0c40701f		ld1 {v31.8b}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc2702a		ld1 {v10.8b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf703c		ld1 {v28.8b}, [x1], #8
+0x~~~~~~~~~~~~~~~~  4c402405		ld1 {v5.8h, v6.8h, v7.8h, v8.8h}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc22422		ld1 {v2.8h, v3.8h, v4.8h, v5.8h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf242a		ld1 {v10.8h, v11.8h, v12.8h, v13.8h}, [x1], #64
+0x~~~~~~~~~~~~~~~~  4c40641a		ld1 {v26.8h, v27.8h, v28.8h}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc26423		ld1 {v3.8h, v4.8h, v5.8h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf6431		ld1 {v17.8h, v18.8h, v19.8h}, [x1], #48
+0x~~~~~~~~~~~~~~~~  4c40a404		ld1 {v4.8h, v5.8h}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc2a435		ld1 {v21.8h, v22.8h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdfa424		ld1 {v4.8h, v5.8h}, [x1], #32
+0x~~~~~~~~~~~~~~~~  4c407409		ld1 {v9.8h}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc2743b		ld1 {v27.8h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf743a		ld1 {v26.8h}, [x1], #16
+0x~~~~~~~~~~~~~~~~  0d400413		ld1 {v19.b}[1], [x0]
+0x~~~~~~~~~~~~~~~~  0dc20c2c		ld1 {v12.b}[3], [x1], x2
+0x~~~~~~~~~~~~~~~~  4ddf103b		ld1 {v27.b}[12], [x1], #1
+0x~~~~~~~~~~~~~~~~  4d40840a		ld1 {v10.d}[1], [x0]
+0x~~~~~~~~~~~~~~~~  4dc2843a		ld1 {v26.d}[1], [x1], x2
+0x~~~~~~~~~~~~~~~~  4ddf8427		ld1 {v7.d}[1], [x1], #8
+0x~~~~~~~~~~~~~~~~  4d404813		ld1 {v19.h}[5], [x0]
+0x~~~~~~~~~~~~~~~~  0dc2482a		ld1 {v10.h}[1], [x1], x2
+0x~~~~~~~~~~~~~~~~  4ddf4025		ld1 {v5.h}[4], [x1], #2
+0x~~~~~~~~~~~~~~~~  4d408015		ld1 {v21.s}[2], [x0]
+0x~~~~~~~~~~~~~~~~  4dc2802d		ld1 {v13.s}[2], [x1], x2
+0x~~~~~~~~~~~~~~~~  4ddf8021		ld1 {v1.s}[2], [x1], #4
+0x~~~~~~~~~~~~~~~~  4d40c002		ld1r {v2.16b}, [x0]
+0x~~~~~~~~~~~~~~~~  4dc2c022		ld1r {v2.16b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4ddfc036		ld1r {v22.16b}, [x1], #1
+0x~~~~~~~~~~~~~~~~  0d40cc19		ld1r {v25.1d}, [x0]
+0x~~~~~~~~~~~~~~~~  0dc2cc29		ld1r {v9.1d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0ddfcc37		ld1r {v23.1d}, [x1], #8
+0x~~~~~~~~~~~~~~~~  4d40cc13		ld1r {v19.2d}, [x0]
+0x~~~~~~~~~~~~~~~~  4dc2cc35		ld1r {v21.2d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4ddfcc3e		ld1r {v30.2d}, [x1], #8
+0x~~~~~~~~~~~~~~~~  0d40c818		ld1r {v24.2s}, [x0]
+0x~~~~~~~~~~~~~~~~  0dc2c83a		ld1r {v26.2s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0ddfc83c		ld1r {v28.2s}, [x1], #4
+0x~~~~~~~~~~~~~~~~  0d40c413		ld1r {v19.4h}, [x0]
+0x~~~~~~~~~~~~~~~~  0dc2c421		ld1r {v1.4h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0ddfc435		ld1r {v21.4h}, [x1], #2
+0x~~~~~~~~~~~~~~~~  4d40c80f		ld1r {v15.4s}, [x0]
+0x~~~~~~~~~~~~~~~~  4dc2c835		ld1r {v21.4s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4ddfc837		ld1r {v23.4s}, [x1], #4
+0x~~~~~~~~~~~~~~~~  0d40c01a		ld1r {v26.8b}, [x0]
+0x~~~~~~~~~~~~~~~~  0dc2c02e		ld1r {v14.8b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0ddfc033		ld1r {v19.8b}, [x1], #1
+0x~~~~~~~~~~~~~~~~  4d40c40d		ld1r {v13.8h}, [x0]
+0x~~~~~~~~~~~~~~~~  4dc2c43e		ld1r {v30.8h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4ddfc43b		ld1r {v27.8h}, [x1], #2
+0x~~~~~~~~~~~~~~~~  4c408015		ld2 {v21.16b, v22.16b}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc28035		ld2 {v21.16b, v22.16b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf802c		ld2 {v12.16b, v13.16b}, [x1], #32
+0x~~~~~~~~~~~~~~~~  4c408c0e		ld2 {v14.2d, v15.2d}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc28c20		ld2 {v0.2d, v1.2d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf8c2c		ld2 {v12.2d, v13.2d}, [x1], #32
+0x~~~~~~~~~~~~~~~~  0c40881b		ld2 {v27.2s, v28.2s}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc28822		ld2 {v2.2s, v3.2s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf882c		ld2 {v12.2s, v13.2s}, [x1], #16
+0x~~~~~~~~~~~~~~~~  0c408409		ld2 {v9.4h, v10.4h}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc28437		ld2 {v23.4h, v24.4h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf8421		ld2 {v1.4h, v2.4h}, [x1], #16
+0x~~~~~~~~~~~~~~~~  4c408814		ld2 {v20.4s, v21.4s}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc2882a		ld2 {v10.4s, v11.4s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf8838		ld2 {v24.4s, v25.4s}, [x1], #32
+0x~~~~~~~~~~~~~~~~  0c408011		ld2 {v17.8b, v18.8b}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc2802d		ld2 {v13.8b, v14.8b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf8027		ld2 {v7.8b, v8.8b}, [x1], #16
+0x~~~~~~~~~~~~~~~~  4c40841e		ld2 {v30.8h, v31.8h}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc28424		ld2 {v4.8h, v5.8h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf842d		ld2 {v13.8h, v14.8h}, [x1], #32
+0x~~~~~~~~~~~~~~~~  4d601005		ld2 {v5.b, v6.b}[12], [x0]
+0x~~~~~~~~~~~~~~~~  0de21c30		ld2 {v16.b, v17.b}[7], [x1], x2
+0x~~~~~~~~~~~~~~~~  0dff083d		ld2 {v29.b, v30.b}[2], [x1], #2
+0x~~~~~~~~~~~~~~~~  4d60840b		ld2 {v11.d, v12.d}[1], [x0]
+0x~~~~~~~~~~~~~~~~  0de2843a		ld2 {v26.d, v27.d}[0], [x1], x2
+0x~~~~~~~~~~~~~~~~  0dff8439		ld2 {v25.d, v26.d}[0], [x1], #16
+0x~~~~~~~~~~~~~~~~  4d605812		ld2 {v18.h, v19.h}[7], [x0]
+0x~~~~~~~~~~~~~~~~  4de24831		ld2 {v17.h, v18.h}[5], [x1], x2
+0x~~~~~~~~~~~~~~~~  0dff503e		ld2 {v30.h, v31.h}[2], [x1], #4
+0x~~~~~~~~~~~~~~~~  4d60901d		ld2 {v29.s, v30.s}[3], [x0]
+0x~~~~~~~~~~~~~~~~  0de2803c		ld2 {v28.s, v29.s}[0], [x1], x2
+0x~~~~~~~~~~~~~~~~  0dff9026		ld2 {v6.s, v7.s}[1], [x1], #8
+0x~~~~~~~~~~~~~~~~  4d60c01a		ld2r {v26.16b, v27.16b}, [x0]
+0x~~~~~~~~~~~~~~~~  4de2c035		ld2r {v21.16b, v22.16b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4dffc025		ld2r {v5.16b, v6.16b}, [x1], #2
+0x~~~~~~~~~~~~~~~~  0d60cc1a		ld2r {v26.1d, v27.1d}, [x0]
+0x~~~~~~~~~~~~~~~~  0de2cc2e		ld2r {v14.1d, v15.1d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0dffcc37		ld2r {v23.1d, v24.1d}, [x1], #16
+0x~~~~~~~~~~~~~~~~  4d60cc0b		ld2r {v11.2d, v12.2d}, [x0]
+0x~~~~~~~~~~~~~~~~  4de2cc3d		ld2r {v29.2d, v30.2d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4dffcc2f		ld2r {v15.2d, v16.2d}, [x1], #16
+0x~~~~~~~~~~~~~~~~  0d60c81a		ld2r {v26.2s, v27.2s}, [x0]
+0x~~~~~~~~~~~~~~~~  0de2c836		ld2r {v22.2s, v23.2s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0dffc822		ld2r {v2.2s, v3.2s}, [x1], #8
+0x~~~~~~~~~~~~~~~~  0d60c402		ld2r {v2.4h, v3.4h}, [x0]
+0x~~~~~~~~~~~~~~~~  0de2c429		ld2r {v9.4h, v10.4h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0dffc426		ld2r {v6.4h, v7.4h}, [x1], #4
+0x~~~~~~~~~~~~~~~~  4d60c807		ld2r {v7.4s, v8.4s}, [x0]
+0x~~~~~~~~~~~~~~~~  4de2c833		ld2r {v19.4s, v20.4s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4dffc835		ld2r {v21.4s, v22.4s}, [x1], #8
+0x~~~~~~~~~~~~~~~~  0d60c01a		ld2r {v26.8b, v27.8b}, [x0]
+0x~~~~~~~~~~~~~~~~  0de2c034		ld2r {v20.8b, v21.8b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0dffc02b		ld2r {v11.8b, v12.8b}, [x1], #2
+0x~~~~~~~~~~~~~~~~  4d60c40c		ld2r {v12.8h, v13.8h}, [x0]
+0x~~~~~~~~~~~~~~~~  4de2c426		ld2r {v6.8h, v7.8h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4dffc439		ld2r {v25.8h, v26.8h}, [x1], #4
+0x~~~~~~~~~~~~~~~~  4c404014		ld3 {v20.16b, v21.16b, v22.16b}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc2403c		ld3 {v28.16b, v29.16b, v30.16b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf4034		ld3 {v20.16b, v21.16b, v22.16b}, [x1], #48
+0x~~~~~~~~~~~~~~~~  4c404c15		ld3 {v21.2d, v22.2d, v23.2d}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc24c32		ld3 {v18.2d, v19.2d, v20.2d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf4c3b		ld3 {v27.2d, v28.2d, v29.2d}, [x1], #48
+0x~~~~~~~~~~~~~~~~  0c404807		ld3 {v7.2s, v8.2s, v9.2s}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc24834		ld3 {v20.2s, v21.2s, v22.2s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf483a		ld3 {v26.2s, v27.2s, v28.2s}, [x1], #24
+0x~~~~~~~~~~~~~~~~  0c40441b		ld3 {v27.4h, v28.4h, v29.4h}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc2443c		ld3 {v28.4h, v29.4h, v30.4h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf4427		ld3 {v7.4h, v8.4h, v9.4h}, [x1], #24
+0x~~~~~~~~~~~~~~~~  4c404802		ld3 {v2.4s, v3.4s, v4.4s}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc24838		ld3 {v24.4s, v25.4s, v26.4s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf482b		ld3 {v11.4s, v12.4s, v13.4s}, [x1], #48
+0x~~~~~~~~~~~~~~~~  0c40401d		ld3 {v29.8b, v30.8b, v31.8b}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc24021		ld3 {v1.8b, v2.8b, v3.8b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf402c		ld3 {v12.8b, v13.8b, v14.8b}, [x1], #24
+0x~~~~~~~~~~~~~~~~  4c404416		ld3 {v22.8h, v23.8h, v24.8h}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc2442d		ld3 {v13.8h, v14.8h, v15.8h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf443c		ld3 {v28.8h, v29.8h, v30.8h}, [x1], #48
+0x~~~~~~~~~~~~~~~~  4d402c15		ld3 {v21.b, v22.b, v23.b}[11], [x0]
+0x~~~~~~~~~~~~~~~~  4dc22425		ld3 {v5.b, v6.b, v7.b}[9], [x1], x2
+0x~~~~~~~~~~~~~~~~  0ddf2037		ld3 {v23.b, v24.b, v25.b}[0], [x1], #3
+0x~~~~~~~~~~~~~~~~  0d40a410		ld3 {v16.d, v17.d, v18.d}[0], [x0]
+0x~~~~~~~~~~~~~~~~  0dc2a43e		ld3 {v30.d, v31.d, v0.d}[0], [x1], x2
+0x~~~~~~~~~~~~~~~~  4ddfa43c		ld3 {v28.d, v29.d, v30.d}[1], [x1], #24
+0x~~~~~~~~~~~~~~~~  0d40700d		ld3 {v13.h, v14.h, v15.h}[2], [x0]
+0x~~~~~~~~~~~~~~~~  4dc27836		ld3 {v22.h, v23.h, v24.h}[7], [x1], x2
+0x~~~~~~~~~~~~~~~~  0ddf782e		ld3 {v14.h, v15.h, v16.h}[3], [x1], #6
+0x~~~~~~~~~~~~~~~~  4d40b016		ld3 {v22.s, v23.s, v24.s}[3], [x0]
+0x~~~~~~~~~~~~~~~~  4dc2a03e		ld3 {v30.s, v31.s, v0.s}[2], [x1], x2
+0x~~~~~~~~~~~~~~~~  0ddfb02c		ld3 {v12.s, v13.s, v14.s}[1], [x1], #12
+0x~~~~~~~~~~~~~~~~  4d40e018		ld3r {v24.16b, v25.16b, v26.16b}, [x0]
+0x~~~~~~~~~~~~~~~~  4dc2e038		ld3r {v24.16b, v25.16b, v26.16b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4ddfe023		ld3r {v3.16b, v4.16b, v5.16b}, [x1], #3
+0x~~~~~~~~~~~~~~~~  0d40ec04		ld3r {v4.1d, v5.1d, v6.1d}, [x0]
+0x~~~~~~~~~~~~~~~~  0dc2ec27		ld3r {v7.1d, v8.1d, v9.1d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0ddfec31		ld3r {v17.1d, v18.1d, v19.1d}, [x1], #24
+0x~~~~~~~~~~~~~~~~  4d40ec10		ld3r {v16.2d, v17.2d, v18.2d}, [x0]
+0x~~~~~~~~~~~~~~~~  4dc2ec34		ld3r {v20.2d, v21.2d, v22.2d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4ddfec2e		ld3r {v14.2d, v15.2d, v16.2d}, [x1], #24
+0x~~~~~~~~~~~~~~~~  0d40e80a		ld3r {v10.2s, v11.2s, v12.2s}, [x0]
+0x~~~~~~~~~~~~~~~~  0dc2e820		ld3r {v0.2s, v1.2s, v2.2s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0ddfe837		ld3r {v23.2s, v24.2s, v25.2s}, [x1], #12
+0x~~~~~~~~~~~~~~~~  0d40e416		ld3r {v22.4h, v23.4h, v24.4h}, [x0]
+0x~~~~~~~~~~~~~~~~  0dc2e426		ld3r {v6.4h, v7.4h, v8.4h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0ddfe427		ld3r {v7.4h, v8.4h, v9.4h}, [x1], #6
+0x~~~~~~~~~~~~~~~~  4d40e81a		ld3r {v26.4s, v27.4s, v28.4s}, [x0]
+0x~~~~~~~~~~~~~~~~  4dc2e820		ld3r {v0.4s, v1.4s, v2.4s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4ddfe83e		ld3r {v30.4s, v31.4s, v0.4s}, [x1], #12
+0x~~~~~~~~~~~~~~~~  0d40e002		ld3r {v2.8b, v3.8b, v4.8b}, [x0]
+0x~~~~~~~~~~~~~~~~  0dc2e02a		ld3r {v10.8b, v11.8b, v12.8b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0ddfe03c		ld3r {v28.8b, v29.8b, v30.8b}, [x1], #3
+0x~~~~~~~~~~~~~~~~  4d40e406		ld3r {v6.8h, v7.8h, v8.8h}, [x0]
+0x~~~~~~~~~~~~~~~~  4dc2e43d		ld3r {v29.8h, v30.8h, v31.8h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4ddfe427		ld3r {v7.8h, v8.8h, v9.8h}, [x1], #6
+0x~~~~~~~~~~~~~~~~  4c400003		ld4 {v3.16b, v4.16b, v5.16b, v6.16b}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc20022		ld4 {v2.16b, v3.16b, v4.16b, v5.16b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf0025		ld4 {v5.16b, v6.16b, v7.16b, v8.16b}, [x1], #64
+0x~~~~~~~~~~~~~~~~  4c400c12		ld4 {v18.2d, v19.2d, v20.2d, v21.2d}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc20c24		ld4 {v4.2d, v5.2d, v6.2d, v7.2d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf0c3d		ld4 {v29.2d, v30.2d, v31.2d, v0.2d}, [x1], #64
+0x~~~~~~~~~~~~~~~~  0c40081b		ld4 {v27.2s, v28.2s, v29.2s, v30.2s}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc20838		ld4 {v24.2s, v25.2s, v26.2s, v27.2s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf0824		ld4 {v4.2s, v5.2s, v6.2s, v7.2s}, [x1], #32
+0x~~~~~~~~~~~~~~~~  0c400410		ld4 {v16.4h, v17.4h, v18.4h, v19.4h}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc20437		ld4 {v23.4h, v24.4h, v25.4h, v26.4h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf0422		ld4 {v2.4h, v3.4h, v4.4h, v5.4h}, [x1], #32
+0x~~~~~~~~~~~~~~~~  4c400807		ld4 {v7.4s, v8.4s, v9.4s, v10.4s}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc2083c		ld4 {v28.4s, v29.4s, v30.4s, v31.4s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf083d		ld4 {v29.4s, v30.4s, v31.4s, v0.4s}, [x1], #64
+0x~~~~~~~~~~~~~~~~  0c40000f		ld4 {v15.8b, v16.8b, v17.8b, v18.8b}, [x0]
+0x~~~~~~~~~~~~~~~~  0cc2003b		ld4 {v27.8b, v28.8b, v29.8b, v30.8b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0cdf0025		ld4 {v5.8b, v6.8b, v7.8b, v8.8b}, [x1], #32
+0x~~~~~~~~~~~~~~~~  4c400419		ld4 {v25.8h, v26.8h, v27.8h, v28.8h}, [x0]
+0x~~~~~~~~~~~~~~~~  4cc20422		ld4 {v2.8h, v3.8h, v4.8h, v5.8h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4cdf0434		ld4 {v20.8h, v21.8h, v22.8h, v23.8h}, [x1], #64
+0x~~~~~~~~~~~~~~~~  0d602c14		ld4 {v20.b, v21.b, v22.b, v23.b}[3], [x0]
+0x~~~~~~~~~~~~~~~~  0de22c2c		ld4 {v12.b, v13.b, v14.b, v15.b}[3], [x1], x2
+0x~~~~~~~~~~~~~~~~  0dff383b		ld4 {v27.b, v28.b, v29.b, v30.b}[6], [x1], #4
+0x~~~~~~~~~~~~~~~~  4d60a41c		ld4 {v28.d, v29.d, v30.d, v31.d}[1], [x0]
+0x~~~~~~~~~~~~~~~~  4de2a42f		ld4 {v15.d, v16.d, v17.d, v18.d}[1], [x1], x2
+0x~~~~~~~~~~~~~~~~  4dffa430		ld4 {v16.d, v17.d, v18.d, v19.d}[1], [x1], #32
+0x~~~~~~~~~~~~~~~~  4d607002		ld4 {v2.h, v3.h, v4.h, v5.h}[6], [x0]
+0x~~~~~~~~~~~~~~~~  0de27825		ld4 {v5.h, v6.h, v7.h, v8.h}[3], [x1], x2
+0x~~~~~~~~~~~~~~~~  4dff7027		ld4 {v7.h, v8.h, v9.h, v10.h}[6], [x1], #8
+0x~~~~~~~~~~~~~~~~  0d60b006		ld4 {v6.s, v7.s, v8.s, v9.s}[1], [x0]
+0x~~~~~~~~~~~~~~~~  4de2a039		ld4 {v25.s, v26.s, v27.s, v28.s}[2], [x1], x2
+0x~~~~~~~~~~~~~~~~  4dffb028		ld4 {v8.s, v9.s, v10.s, v11.s}[3], [x1], #16
+0x~~~~~~~~~~~~~~~~  4d60e00e		ld4r {v14.16b, v15.16b, v16.16b, v17.16b}, [x0]
+0x~~~~~~~~~~~~~~~~  4de2e02d		ld4r {v13.16b, v14.16b, v15.16b, v16.16b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4dffe029		ld4r {v9.16b, v10.16b, v11.16b, v12.16b}, [x1], #4
+0x~~~~~~~~~~~~~~~~  0d60ec08		ld4r {v8.1d, v9.1d, v10.1d, v11.1d}, [x0]
+0x~~~~~~~~~~~~~~~~  0de2ec24		ld4r {v4.1d, v5.1d, v6.1d, v7.1d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0dffec3a		ld4r {v26.1d, v27.1d, v28.1d, v29.1d}, [x1], #32
+0x~~~~~~~~~~~~~~~~  4d60ec13		ld4r {v19.2d, v20.2d, v21.2d, v22.2d}, [x0]
+0x~~~~~~~~~~~~~~~~  4de2ec3c		ld4r {v28.2d, v29.2d, v30.2d, v31.2d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4dffec2f		ld4r {v15.2d, v16.2d, v17.2d, v18.2d}, [x1], #32
+0x~~~~~~~~~~~~~~~~  0d60e81f		ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [x0]
+0x~~~~~~~~~~~~~~~~  0de2e83c		ld4r {v28.2s, v29.2s, v30.2s, v31.2s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0dffe82b		ld4r {v11.2s, v12.2s, v13.2s, v14.2s}, [x1], #16
+0x~~~~~~~~~~~~~~~~  0d60e413		ld4r {v19.4h, v20.4h, v21.4h, v22.4h}, [x0]
+0x~~~~~~~~~~~~~~~~  0de2e436		ld4r {v22.4h, v23.4h, v24.4h, v25.4h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0dffe434		ld4r {v20.4h, v21.4h, v22.4h, v23.4h}, [x1], #8
+0x~~~~~~~~~~~~~~~~  4d60e810		ld4r {v16.4s, v17.4s, v18.4s, v19.4s}, [x0]
+0x~~~~~~~~~~~~~~~~  4de2e839		ld4r {v25.4s, v26.4s, v27.4s, v28.4s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4dffe837		ld4r {v23.4s, v24.4s, v25.4s, v26.4s}, [x1], #16
+0x~~~~~~~~~~~~~~~~  0d60e016		ld4r {v22.8b, v23.8b, v24.8b, v25.8b}, [x0]
+0x~~~~~~~~~~~~~~~~  0de2e03b		ld4r {v27.8b, v28.8b, v29.8b, v30.8b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0dffe03d		ld4r {v29.8b, v30.8b, v31.8b, v0.8b}, [x1], #4
+0x~~~~~~~~~~~~~~~~  4d60e41c		ld4r {v28.8h, v29.8h, v30.8h, v31.8h}, [x0]
+0x~~~~~~~~~~~~~~~~  4de2e439		ld4r {v25.8h, v26.8h, v27.8h, v28.8h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4dffe436		ld4r {v22.8h, v23.8h, v24.8h, v25.8h}, [x1], #8
+0x~~~~~~~~~~~~~~~~  4e3a94fd		mla v29.16b, v7.16b, v26.16b
+0x~~~~~~~~~~~~~~~~  0eae9486		mla v6.2s, v4.2s, v14.2s
+0x~~~~~~~~~~~~~~~~  2f800969		mla v9.2s, v11.2s, v0.s[2]
+0x~~~~~~~~~~~~~~~~  0e799625		mla v5.4h, v17.4h, v25.4h
+0x~~~~~~~~~~~~~~~~  2f7b00f8		mla v24.4h, v7.4h, v11.h[3]
+0x~~~~~~~~~~~~~~~~  4ea4946c		mla v12.4s, v3.4s, v4.4s
+0x~~~~~~~~~~~~~~~~  6fa708ea		mla v10.4s, v7.4s, v7.s[3]
+0x~~~~~~~~~~~~~~~~  0e299603		mla v3.8b, v16.8b, v9.8b
+0x~~~~~~~~~~~~~~~~  4e7296d3		mla v19.8h, v22.8h, v18.8h
+0x~~~~~~~~~~~~~~~~  6f400046		mla v6.8h, v2.8h, v0.h[0]
+0x~~~~~~~~~~~~~~~~  6e2b9557		mls v23.16b, v10.16b, v11.16b
+0x~~~~~~~~~~~~~~~~  2eb697ee		mls v14.2s, v31.2s, v22.2s
+0x~~~~~~~~~~~~~~~~  2fa149bc		mls v28.2s, v13.2s, v1.s[3]
+0x~~~~~~~~~~~~~~~~  2e6d9662		mls v2.4h, v19.4h, v13.4h
+0x~~~~~~~~~~~~~~~~  2f6c49f2		mls v18.4h, v15.4h, v12.h[6]
+0x~~~~~~~~~~~~~~~~  6eb09566		mls v6.4s, v11.4s, v16.4s
+0x~~~~~~~~~~~~~~~~  6f8a4a17		mls v23.4s, v16.4s, v10.s[2]
+0x~~~~~~~~~~~~~~~~  2e3795ba		mls v26.8b, v13.8b, v23.8b
+0x~~~~~~~~~~~~~~~~  6e6c954a		mls v10.8h, v10.8h, v12.8h
+0x~~~~~~~~~~~~~~~~  6f7e480e		mls v14.8h, v0.8h, v14.h[7]
+0x~~~~~~~~~~~~~~~~  5e070436		mov b22, v1.b[3]
+0x~~~~~~~~~~~~~~~~  5e1805a7		mov d7, v13.d[1]
+0x~~~~~~~~~~~~~~~~  5e0a06ba		mov h26, v21.h[2]
+0x~~~~~~~~~~~~~~~~  5e04067a		mov s26, v19.s[0]
+0x~~~~~~~~~~~~~~~~  4eab1d7a		mov v26.16b, v11.16b
+0x~~~~~~~~~~~~~~~~  0ea01c14		mov v20.8b, v0.8b
+0x~~~~~~~~~~~~~~~~  6e1b24d3		mov v19.b[13], v6.b[4]
+0x~~~~~~~~~~~~~~~~  4e1b1e64		mov v4.b[13], w19
+0x~~~~~~~~~~~~~~~~  6e18050b		mov v11.d[1], v8.d[0]
+0x~~~~~~~~~~~~~~~~  4e081fc3		mov v3.d[0], x30
+0x~~~~~~~~~~~~~~~~  6e12757d		mov v29.h[4], v11.h[7]
+0x~~~~~~~~~~~~~~~~  4e1a1cc2		mov v2.h[6], w6
+0x~~~~~~~~~~~~~~~~  6e0444b6		mov v22.s[0], v5.s[2]
+0x~~~~~~~~~~~~~~~~  4e1c1d18		mov v24.s[3], w8
+0x~~~~~~~~~~~~~~~~  0e1c3c32		mov w18, v1.s[3]
+0x~~~~~~~~~~~~~~~~  4e083ebc		mov x28, v21.d[0]
+0x~~~~~~~~~~~~~~~~  2f03e4f8		movi d24, #0xffff0000ffffff
+0x~~~~~~~~~~~~~~~~  4f04e41d		movi v29.16b, #0x80
+0x~~~~~~~~~~~~~~~~  6f06e6cc		movi v12.2d, #0xffff00ff00ffff00
+0x~~~~~~~~~~~~~~~~  0f07658c		movi v12.2s, #0xec, lsl #24
+0x~~~~~~~~~~~~~~~~  0f02d58a		movi v10.2s, #0x4c, msl #16
+0x~~~~~~~~~~~~~~~~  0f06841a		movi v26.4h, #0xc0, lsl #0
+0x~~~~~~~~~~~~~~~~  4f044718		movi v24.4s, #0x98, lsl #16
+0x~~~~~~~~~~~~~~~~  4f06d7c1		movi v1.4s, #0xde, msl #16
+0x~~~~~~~~~~~~~~~~  0f02e5b5		movi v21.8b, #0x4d
+0x~~~~~~~~~~~~~~~~  4f03853d		movi v29.8h, #0x69, lsl #0
+0x~~~~~~~~~~~~~~~~  4e319de1		mul v1.16b, v15.16b, v17.16b
+0x~~~~~~~~~~~~~~~~  0ebd9e75		mul v21.2s, v19.2s, v29.2s
+0x~~~~~~~~~~~~~~~~  0f8380b3		mul v19.2s, v5.2s, v3.s[0]
+0x~~~~~~~~~~~~~~~~  0e629d7d		mul v29.4h, v11.4h, v2.4h
+0x~~~~~~~~~~~~~~~~  0f4080e2		mul v2.4h, v7.4h, v0.h[0]
+0x~~~~~~~~~~~~~~~~  4eb09f59		mul v25.4s, v26.4s, v16.4s
+0x~~~~~~~~~~~~~~~~  4f8f88da		mul v26.4s, v6.4s, v15.s[2]
+0x~~~~~~~~~~~~~~~~  0e3f9deb		mul v11.8b, v15.8b, v31.8b
+0x~~~~~~~~~~~~~~~~  4e6f9ff4		mul v20.8h, v31.8h, v15.8h
+0x~~~~~~~~~~~~~~~~  4f4988bd		mul v29.8h, v5.8h, v9.h[4]
+0x~~~~~~~~~~~~~~~~  6e205aad		mvn v13.16b, v21.16b
+0x~~~~~~~~~~~~~~~~  2e205a7c		mvn v28.8b, v19.8b
+0x~~~~~~~~~~~~~~~~  2f052719		mvni v25.2s, #0xb8, lsl #8
+0x~~~~~~~~~~~~~~~~  2f03d591		mvni v17.2s, #0x6c, msl #16
+0x~~~~~~~~~~~~~~~~  2f02851d		mvni v29.4h, #0x48, lsl #0
+0x~~~~~~~~~~~~~~~~  6f034754		mvni v20.4s, #0x7a, lsl #16
+0x~~~~~~~~~~~~~~~~  6f00c7c0		mvni v0.4s, #0x1e, msl #8
+0x~~~~~~~~~~~~~~~~  6f0187df		mvni v31.8h, #0x3e, lsl #0
+0x~~~~~~~~~~~~~~~~  7ee0b979		neg d25, d11
+0x~~~~~~~~~~~~~~~~  6e20b924		neg v4.16b, v9.16b
+0x~~~~~~~~~~~~~~~~  6ee0bb2b		neg v11.2d, v25.2d
+0x~~~~~~~~~~~~~~~~  2ea0ba47		neg v7.2s, v18.2s
+0x~~~~~~~~~~~~~~~~  2e60b9e7		neg v7.4h, v15.4h
+0x~~~~~~~~~~~~~~~~  6ea0ba51		neg v17.4s, v18.4s
+0x~~~~~~~~~~~~~~~~  2e20ba34		neg v20.8b, v17.8b
+0x~~~~~~~~~~~~~~~~  6e60b960		neg v0.8h, v11.8h
+0x~~~~~~~~~~~~~~~~  4eff1d6d		orn v13.16b, v11.16b, v31.16b
+0x~~~~~~~~~~~~~~~~  0ef61e16		orn v22.8b, v16.8b, v22.8b
+0x~~~~~~~~~~~~~~~~  4eb71e31		orr v17.16b, v17.16b, v23.16b
+0x~~~~~~~~~~~~~~~~  0f071468		orr v8.2s, #0xe3, lsl #0
+0x~~~~~~~~~~~~~~~~  0f04b6eb		orr v11.4h, #0x97, lsl #8
+0x~~~~~~~~~~~~~~~~  4f051567		orr v7.4s, #0xab, lsl #0
+0x~~~~~~~~~~~~~~~~  0ea31c88		orr v8.8b, v4.8b, v3.8b
+0x~~~~~~~~~~~~~~~~  4f05b61f		orr v31.8h, #0xb0, lsl #8
+0x~~~~~~~~~~~~~~~~  6e379e4b		pmul v11.16b, v18.16b, v23.16b
+0x~~~~~~~~~~~~~~~~  2e259f08		pmul v8.8b, v24.8b, v5.8b
+0x~~~~~~~~~~~~~~~~  0e36e258		pmull v24.8h, v18.8b, v22.8b
+0x~~~~~~~~~~~~~~~~  4e35e06d		pmull2 v13.8h, v3.16b, v21.16b
+0x~~~~~~~~~~~~~~~~  2eb54156		raddhn v22.2s, v10.2d, v21.2d
+0x~~~~~~~~~~~~~~~~  2e6d41a5		raddhn v5.4h, v13.4s, v13.4s
+0x~~~~~~~~~~~~~~~~  2e3a422a		raddhn v10.8b, v17.8h, v26.8h
+0x~~~~~~~~~~~~~~~~  6e2d43a9		raddhn2 v9.16b, v29.8h, v13.8h
+0x~~~~~~~~~~~~~~~~  6eba42fb		raddhn2 v27.4s, v23.2d, v26.2d
+0x~~~~~~~~~~~~~~~~  6e6743a0		raddhn2 v0.8h, v29.4s, v7.4s
+0x~~~~~~~~~~~~~~~~  6e6059f6		rbit v22.16b, v15.16b
+0x~~~~~~~~~~~~~~~~  2e60587e		rbit v30.8b, v3.8b
+0x~~~~~~~~~~~~~~~~  4e201b7f		rev16 v31.16b, v27.16b
+0x~~~~~~~~~~~~~~~~  0e201b4c		rev16 v12.8b, v26.8b
+0x~~~~~~~~~~~~~~~~  6e200885		rev32 v5.16b, v4.16b
+0x~~~~~~~~~~~~~~~~  2e600b50		rev32 v16.4h, v26.4h
+0x~~~~~~~~~~~~~~~~  2e200874		rev32 v20.8b, v3.8b
+0x~~~~~~~~~~~~~~~~  6e600b94		rev32 v20.8h, v28.8h
+0x~~~~~~~~~~~~~~~~  4e200a69		rev64 v9.16b, v19.16b
+0x~~~~~~~~~~~~~~~~  0ea00a05		rev64 v5.2s, v16.2s
+0x~~~~~~~~~~~~~~~~  0e600be7		rev64 v7.4h, v31.4h
+0x~~~~~~~~~~~~~~~~  4ea00b4f		rev64 v15.4s, v26.4s
+0x~~~~~~~~~~~~~~~~  0e200939		rev64 v25.8b, v9.8b
+0x~~~~~~~~~~~~~~~~  4e6008ab		rev64 v11.8h, v5.8h
+0x~~~~~~~~~~~~~~~~  0f3f8db2		rshrn v18.2s, v13.2d, #1
+0x~~~~~~~~~~~~~~~~  0f1e8fd9		rshrn v25.4h, v30.4s, #2
+0x~~~~~~~~~~~~~~~~  0f088d2d		rshrn v13.8b, v9.8h, #8
+0x~~~~~~~~~~~~~~~~  4f088cc3		rshrn2 v3.16b, v6.8h, #8
+0x~~~~~~~~~~~~~~~~  4f278fa0		rshrn2 v0.4s, v29.2d, #25
+0x~~~~~~~~~~~~~~~~  4f118f5b		rshrn2 v27.8h, v26.4s, #15
+0x~~~~~~~~~~~~~~~~  2ea4632f		rsubhn v15.2s, v25.2d, v4.2d
+0x~~~~~~~~~~~~~~~~  2e636137		rsubhn v23.4h, v9.4s, v3.4s
+0x~~~~~~~~~~~~~~~~  2e3863c6		rsubhn v6.8b, v30.8h, v24.8h
+0x~~~~~~~~~~~~~~~~  6e346304		rsubhn2 v4.16b, v24.8h, v20.8h
+0x~~~~~~~~~~~~~~~~  6eb662e1		rsubhn2 v1.4s, v23.2d, v22.2d
+0x~~~~~~~~~~~~~~~~  6e746053		rsubhn2 v19.8h, v2.4s, v20.4s
+0x~~~~~~~~~~~~~~~~  4e397d3c		saba v28.16b, v9.16b, v25.16b
+0x~~~~~~~~~~~~~~~~  0eb47f89		saba v9.2s, v28.2s, v20.2s
+0x~~~~~~~~~~~~~~~~  0e767ed1		saba v17.4h, v22.4h, v22.4h
+0x~~~~~~~~~~~~~~~~  4ebb7cbd		saba v29.4s, v5.4s, v27.4s
+0x~~~~~~~~~~~~~~~~  0e327eb4		saba v20.8b, v21.8b, v18.8b
+0x~~~~~~~~~~~~~~~~  4e7e7e3b		saba v27.8h, v17.8h, v30.8h
+0x~~~~~~~~~~~~~~~~  0ea751b4		sabal v20.2d, v13.2s, v7.2s
+0x~~~~~~~~~~~~~~~~  0e645184		sabal v4.4s, v12.4h, v4.4h
+0x~~~~~~~~~~~~~~~~  0e345317		sabal v23.8h, v24.8b, v20.8b
+0x~~~~~~~~~~~~~~~~  4eb252ba		sabal2 v26.2d, v21.4s, v18.4s
+0x~~~~~~~~~~~~~~~~  4e68539b		sabal2 v27.4s, v28.8h, v8.8h
+0x~~~~~~~~~~~~~~~~  4e35520c		sabal2 v12.8h, v16.16b, v21.16b
+0x~~~~~~~~~~~~~~~~  4e2d75e0		sabd v0.16b, v15.16b, v13.16b
+0x~~~~~~~~~~~~~~~~  0ebe74ef		sabd v15.2s, v7.2s, v30.2s
+0x~~~~~~~~~~~~~~~~  0e6c7631		sabd v17.4h, v17.4h, v12.4h
+0x~~~~~~~~~~~~~~~~  4eb67487		sabd v7.4s, v4.4s, v22.4s
+0x~~~~~~~~~~~~~~~~  0e3a7477		sabd v23.8b, v3.8b, v26.8b
+0x~~~~~~~~~~~~~~~~  4e657794		sabd v20.8h, v28.8h, v5.8h
+0x~~~~~~~~~~~~~~~~  0eb472db		sabdl v27.2d, v22.2s, v20.2s
+0x~~~~~~~~~~~~~~~~  0e77729f		sabdl v31.4s, v20.4h, v23.4h
+0x~~~~~~~~~~~~~~~~  0e3b7280		sabdl v0.8h, v20.8b, v27.8b
+0x~~~~~~~~~~~~~~~~  4ea3717f		sabdl2 v31.2d, v11.4s, v3.4s
+0x~~~~~~~~~~~~~~~~  4e7b717a		sabdl2 v26.4s, v11.8h, v27.8h
+0x~~~~~~~~~~~~~~~~  4e327106		sabdl2 v6.8h, v8.16b, v18.16b
+0x~~~~~~~~~~~~~~~~  0ea06b48		sadalp v8.1d, v26.2s
+0x~~~~~~~~~~~~~~~~  4ea06b4c		sadalp v12.2d, v26.4s
+0x~~~~~~~~~~~~~~~~  0e606b4c		sadalp v12.2s, v26.4h
+0x~~~~~~~~~~~~~~~~  0e206824		sadalp v4.4h, v1.8b
+0x~~~~~~~~~~~~~~~~  4e606a2f		sadalp v15.4s, v17.8h
+0x~~~~~~~~~~~~~~~~  4e206b35		sadalp v21.8h, v25.16b
+0x~~~~~~~~~~~~~~~~  0eae0145		saddl v5.2d, v10.2s, v14.2s
+0x~~~~~~~~~~~~~~~~  0e6f0072		saddl v18.4s, v3.4h, v15.4h
+0x~~~~~~~~~~~~~~~~  0e37004f		saddl v15.8h, v2.8b, v23.8b
+0x~~~~~~~~~~~~~~~~  4ebb0210		saddl2 v16.2d, v16.4s, v27.4s
+0x~~~~~~~~~~~~~~~~  4e600306		saddl2 v6.4s, v24.8h, v0.8h
+0x~~~~~~~~~~~~~~~~  4e3c0287		saddl2 v7.8h, v20.16b, v28.16b
+0x~~~~~~~~~~~~~~~~  0ea02b2a		saddlp v10.1d, v25.2s
+0x~~~~~~~~~~~~~~~~  4ea02a0f		saddlp v15.2d, v16.4s
+0x~~~~~~~~~~~~~~~~  0e602952		saddlp v18.2s, v10.4h
+0x~~~~~~~~~~~~~~~~  0e202b5d		saddlp v29.4h, v26.8b
+0x~~~~~~~~~~~~~~~~  4e60282a		saddlp v10.4s, v1.8h
+0x~~~~~~~~~~~~~~~~  4e202aa0		saddlp v0.8h, v21.16b
+0x~~~~~~~~~~~~~~~~  4eb038ec		saddlv d12, v7.4s
+0x~~~~~~~~~~~~~~~~  4e303b8e		saddlv h14, v28.16b
+0x~~~~~~~~~~~~~~~~  0e303bde		saddlv h30, v30.8b
+0x~~~~~~~~~~~~~~~~  0e70387b		saddlv s27, v3.4h
+0x~~~~~~~~~~~~~~~~  4e703a10		saddlv s16, v16.8h
+0x~~~~~~~~~~~~~~~~  0eb21178		saddw v24.2d, v11.2d, v18.2s
+0x~~~~~~~~~~~~~~~~  0e66118d		saddw v13.4s, v12.4s, v6.4h
+0x~~~~~~~~~~~~~~~~  0e271273		saddw v19.8h, v19.8h, v7.8b
+0x~~~~~~~~~~~~~~~~  4eba113b		saddw2 v27.2d, v9.2d, v26.4s
+0x~~~~~~~~~~~~~~~~  4e7512f3		saddw2 v19.4s, v23.4s, v21.8h
+0x~~~~~~~~~~~~~~~~  4e3e132f		saddw2 v15.8h, v25.8h, v30.16b
+0x~~~~~~~~~~~~~~~~  4e290487		shadd v7.16b, v4.16b, v9.16b
+0x~~~~~~~~~~~~~~~~  0eb8073d		shadd v29.2s, v25.2s, v24.2s
+0x~~~~~~~~~~~~~~~~  0e6d055f		shadd v31.4h, v10.4h, v13.4h
+0x~~~~~~~~~~~~~~~~  4ea80615		shadd v21.4s, v16.4s, v8.4s
+0x~~~~~~~~~~~~~~~~  0e3607ae		shadd v14.8b, v29.8b, v22.8b
+0x~~~~~~~~~~~~~~~~  4e740713		shadd v19.8h, v24.8h, v20.8h
+0x~~~~~~~~~~~~~~~~  5f575736		shl d22, d25, #23
+0x~~~~~~~~~~~~~~~~  4f0f5625		shl v5.16b, v17.16b, #7
+0x~~~~~~~~~~~~~~~~  4f555482		shl v2.2d, v4.2d, #21
+0x~~~~~~~~~~~~~~~~  0f3a5464		shl v4.2s, v3.2s, #26
+0x~~~~~~~~~~~~~~~~  0f185783		shl v3.4h, v28.4h, #8
+0x~~~~~~~~~~~~~~~~  4f3857e4		shl v4.4s, v31.4s, #24
+0x~~~~~~~~~~~~~~~~  0f0a5612		shl v18.8b, v16.8b, #2
+0x~~~~~~~~~~~~~~~~  4f135560		shl v0.8h, v11.8h, #3
+0x~~~~~~~~~~~~~~~~  2ea13b05		shll v5.2d, v24.2s, #32
+0x~~~~~~~~~~~~~~~~  2e613a9a		shll v26.4s, v20.4h, #16
+0x~~~~~~~~~~~~~~~~  2e213925		shll v5.8h, v9.8b, #8
+0x~~~~~~~~~~~~~~~~  6ea13b95		shll2 v21.2d, v28.4s, #32
+0x~~~~~~~~~~~~~~~~  6e613836		shll2 v22.4s, v1.8h, #16
+0x~~~~~~~~~~~~~~~~  6e213b3e		shll2 v30.8h, v25.16b, #8
+0x~~~~~~~~~~~~~~~~  0f248425		shrn v5.2s, v1.2d, #28
+0x~~~~~~~~~~~~~~~~  0f19865d		shrn v29.4h, v18.4s, #7
+0x~~~~~~~~~~~~~~~~  0f0e87b1		shrn v17.8b, v29.8h, #2
+0x~~~~~~~~~~~~~~~~  4f0d87c5		shrn2 v5.16b, v30.8h, #3
+0x~~~~~~~~~~~~~~~~  4f3f8438		shrn2 v24.4s, v1.2d, #1
+0x~~~~~~~~~~~~~~~~  4f1085c5		shrn2 v5.8h, v14.4s, #16
+0x~~~~~~~~~~~~~~~~  4e3726de		shsub v30.16b, v22.16b, v23.16b
+0x~~~~~~~~~~~~~~~~  0eb92776		shsub v22.2s, v27.2s, v25.2s
+0x~~~~~~~~~~~~~~~~  0e6126cd		shsub v13.4h, v22.4h, v1.4h
+0x~~~~~~~~~~~~~~~~  4eb7250a		shsub v10.4s, v8.4s, v23.4s
+0x~~~~~~~~~~~~~~~~  0e3f2526		shsub v6.8b, v9.8b, v31.8b
+0x~~~~~~~~~~~~~~~~  4e6827e8		shsub v8.8h, v31.8h, v8.8h
+0x~~~~~~~~~~~~~~~~  7f5457b3		sli d19, d29, #20
+0x~~~~~~~~~~~~~~~~  6f085709		sli v9.16b, v24.16b, #0
+0x~~~~~~~~~~~~~~~~  6f4a5536		sli v22.2d, v9.2d, #10
+0x~~~~~~~~~~~~~~~~  2f34576b		sli v11.2s, v27.2s, #20
+0x~~~~~~~~~~~~~~~~  2f1555f0		sli v16.4h, v15.4h, #5
+0x~~~~~~~~~~~~~~~~  6f395508		sli v8.4s, v8.4s, #25
+0x~~~~~~~~~~~~~~~~  2f0857ca		sli v10.8b, v30.8b, #0
+0x~~~~~~~~~~~~~~~~  6f165787		sli v7.8h, v28.8h, #6
+0x~~~~~~~~~~~~~~~~  4e216512		smax v18.16b, v8.16b, v1.16b
+0x~~~~~~~~~~~~~~~~  0ea164be		smax v30.2s, v5.2s, v1.2s
+0x~~~~~~~~~~~~~~~~  0e736731		smax v17.4h, v25.4h, v19.4h
+0x~~~~~~~~~~~~~~~~  4ebf6701		smax v1.4s, v24.4s, v31.4s
+0x~~~~~~~~~~~~~~~~  0e386711		smax v17.8b, v24.8b, v24.8b
+0x~~~~~~~~~~~~~~~~  4e6a674b		smax v11.8h, v26.8h, v10.8h
+0x~~~~~~~~~~~~~~~~  4e27a5cc		smaxp v12.16b, v14.16b, v7.16b
+0x~~~~~~~~~~~~~~~~  0ea6a71f		smaxp v31.2s, v24.2s, v6.2s
+0x~~~~~~~~~~~~~~~~  0e6aa7aa		smaxp v10.4h, v29.4h, v10.4h
+0x~~~~~~~~~~~~~~~~  4ea7a572		smaxp v18.4s, v11.4s, v7.4s
+0x~~~~~~~~~~~~~~~~  0e32a415		smaxp v21.8b, v0.8b, v18.8b
+0x~~~~~~~~~~~~~~~~  4e6fa51a		smaxp v26.8h, v8.8h, v15.8h
+0x~~~~~~~~~~~~~~~~  4e30a8a4		smaxv b4, v5.16b
+0x~~~~~~~~~~~~~~~~  0e30a817		smaxv b23, v0.8b
+0x~~~~~~~~~~~~~~~~  0e70a806		smaxv h6, v0.4h
+0x~~~~~~~~~~~~~~~~  4e70a918		smaxv h24, v8.8h
+0x~~~~~~~~~~~~~~~~  4eb0aa03		smaxv s3, v16.4s
+0x~~~~~~~~~~~~~~~~  4e326d18		smin v24.16b, v8.16b, v18.16b
+0x~~~~~~~~~~~~~~~~  0eb76d1d		smin v29.2s, v8.2s, v23.2s
+0x~~~~~~~~~~~~~~~~  0e756d66		smin v6.4h, v11.4h, v21.4h
+0x~~~~~~~~~~~~~~~~  4eaf6ef8		smin v24.4s, v23.4s, v15.4s
+0x~~~~~~~~~~~~~~~~  0e246e08		smin v8.8b, v16.8b, v4.8b
+0x~~~~~~~~~~~~~~~~  4e6a6c2c		smin v12.8h, v1.8h, v10.8h
+0x~~~~~~~~~~~~~~~~  4e3cae4d		sminp v13.16b, v18.16b, v28.16b
+0x~~~~~~~~~~~~~~~~  0eb0af96		sminp v22.2s, v28.2s, v16.2s
+0x~~~~~~~~~~~~~~~~  0e65ad8f		sminp v15.4h, v12.4h, v5.4h
+0x~~~~~~~~~~~~~~~~  4ea8ae2f		sminp v15.4s, v17.4s, v8.4s
+0x~~~~~~~~~~~~~~~~  0e26ac55		sminp v21.8b, v2.8b, v6.8b
+0x~~~~~~~~~~~~~~~~  4e66ad95		sminp v21.8h, v12.8h, v6.8h
+0x~~~~~~~~~~~~~~~~  4e31a8c8		sminv b8, v6.16b
+0x~~~~~~~~~~~~~~~~  0e31aa46		sminv b6, v18.8b
+0x~~~~~~~~~~~~~~~~  0e71a834		sminv h20, v1.4h
+0x~~~~~~~~~~~~~~~~  4e71aa27		sminv h7, v17.8h
+0x~~~~~~~~~~~~~~~~  4eb1a895		sminv s21, v4.4s
+0x~~~~~~~~~~~~~~~~  0eb581d8		smlal v24.2d, v14.2s, v21.2s
+0x~~~~~~~~~~~~~~~~  0f8e287f		smlal v31.2d, v3.2s, v14.s[2]
+0x~~~~~~~~~~~~~~~~  0e758287		smlal v7.4s, v20.4h, v21.4h
+0x~~~~~~~~~~~~~~~~  0f792213		smlal v19.4s, v16.4h, v9.h[3]
+0x~~~~~~~~~~~~~~~~  0e2181dd		smlal v29.8h, v14.8b, v1.8b
+0x~~~~~~~~~~~~~~~~  4eb0835e		smlal2 v30.2d, v26.4s, v16.4s
+0x~~~~~~~~~~~~~~~~  4f8123df		smlal2 v31.2d, v30.4s, v1.s[0]
+0x~~~~~~~~~~~~~~~~  4e6380d1		smlal2 v17.4s, v6.8h, v3.8h
+0x~~~~~~~~~~~~~~~~  4f752beb		smlal2 v11.4s, v31.8h, v5.h[7]
+0x~~~~~~~~~~~~~~~~  4e3d821e		smlal2 v30.8h, v16.16b, v29.16b
+0x~~~~~~~~~~~~~~~~  0eb1a281		smlsl v1.2d, v20.2s, v17.2s
+0x~~~~~~~~~~~~~~~~  0fa5699d		smlsl v29.2d, v12.2s, v5.s[3]
+0x~~~~~~~~~~~~~~~~  0e61a340		smlsl v0.4s, v26.4h, v1.4h
+0x~~~~~~~~~~~~~~~~  0f5668a3		smlsl v3.4s, v5.4h, v6.h[5]
+0x~~~~~~~~~~~~~~~~  0e3aa004		smlsl v4.8h, v0.8b, v26.8b
+0x~~~~~~~~~~~~~~~~  4ea5a1ce		smlsl2 v14.2d, v14.4s, v5.4s
+0x~~~~~~~~~~~~~~~~  4fa060af		smlsl2 v15.2d, v5.4s, v0.s[1]
+0x~~~~~~~~~~~~~~~~  4e7fa23d		smlsl2 v29.4s, v17.8h, v31.8h
+0x~~~~~~~~~~~~~~~~  4f6969e6		smlsl2 v6.4s, v15.8h, v9.h[6]
+0x~~~~~~~~~~~~~~~~  4e2fa1fe		smlsl2 v30.8h, v15.16b, v15.16b
+0x~~~~~~~~~~~~~~~~  0e072cd5		smov w21, v6.b[3]
+0x~~~~~~~~~~~~~~~~  0e1e2f4d		smov w13, v26.h[7]
+0x~~~~~~~~~~~~~~~~  4e0f2e18		smov x24, v16.b[7]
+0x~~~~~~~~~~~~~~~~  4e0e2c87		smov x7, v4.h[3]
+0x~~~~~~~~~~~~~~~~  4e0c2cfd		smov x29, v7.s[1]
+0x~~~~~~~~~~~~~~~~  0eb1c3a4		smull v4.2d, v29.2s, v17.2s
+0x~~~~~~~~~~~~~~~~  0f86aabe		smull v30.2d, v21.2s, v6.s[2]
+0x~~~~~~~~~~~~~~~~  0e77c0b7		smull v23.4s, v5.4h, v23.4h
+0x~~~~~~~~~~~~~~~~  0f52a128		smull v8.4s, v9.4h, v2.h[1]
+0x~~~~~~~~~~~~~~~~  0e21c23f		smull v31.8h, v17.8b, v1.8b
+0x~~~~~~~~~~~~~~~~  4eb7c063		smull2 v3.2d, v3.4s, v23.4s
+0x~~~~~~~~~~~~~~~~  4fa6a3af		smull2 v15.2d, v29.4s, v6.s[1]
+0x~~~~~~~~~~~~~~~~  4e7ec293		smull2 v19.4s, v20.8h, v30.8h
+0x~~~~~~~~~~~~~~~~  4f47a946		smull2 v6.4s, v10.8h, v7.h[4]
+0x~~~~~~~~~~~~~~~~  4e3bc119		smull2 v25.8h, v8.16b, v27.16b
+0x~~~~~~~~~~~~~~~~  5e2079e3		sqabs b3, b15
+0x~~~~~~~~~~~~~~~~  5ee0792e		sqabs d14, d9
+0x~~~~~~~~~~~~~~~~  5e607b9f		sqabs h31, h28
+0x~~~~~~~~~~~~~~~~  5ea07808		sqabs s8, s0
+0x~~~~~~~~~~~~~~~~  4e2078ee		sqabs v14.16b, v7.16b
+0x~~~~~~~~~~~~~~~~  4ee07a77		sqabs v23.2d, v19.2d
+0x~~~~~~~~~~~~~~~~  0ea07b0a		sqabs v10.2s, v24.2s
+0x~~~~~~~~~~~~~~~~  0e607a7f		sqabs v31.4h, v19.4h
+0x~~~~~~~~~~~~~~~~  4ea07817		sqabs v23.4s, v0.4s
+0x~~~~~~~~~~~~~~~~  0e207afd		sqabs v29.8b, v23.8b
+0x~~~~~~~~~~~~~~~~  4e607ab1		sqabs v17.8h, v21.8h
+0x~~~~~~~~~~~~~~~~  5e2d0ee9		sqadd b9, b23, b13
+0x~~~~~~~~~~~~~~~~  5efa0f22		sqadd d2, d25, d26
+0x~~~~~~~~~~~~~~~~  5e790fa7		sqadd h7, h29, h25
+0x~~~~~~~~~~~~~~~~  5eb80ceb		sqadd s11, s7, s24
+0x~~~~~~~~~~~~~~~~  4e3d0e14		sqadd v20.16b, v16.16b, v29.16b
+0x~~~~~~~~~~~~~~~~  4efc0fd7		sqadd v23.2d, v30.2d, v28.2d
+0x~~~~~~~~~~~~~~~~  0ea20e68		sqadd v8.2s, v19.2s, v2.2s
+0x~~~~~~~~~~~~~~~~  0e7f0d94		sqadd v20.4h, v12.4h, v31.4h
+0x~~~~~~~~~~~~~~~~  4eb10dee		sqadd v14.4s, v15.4s, v17.4s
+0x~~~~~~~~~~~~~~~~  0e2d0fa2		sqadd v2.8b, v29.8b, v13.8b
+0x~~~~~~~~~~~~~~~~  4e6e0e67		sqadd v7.8h, v19.8h, v14.8h
+0x~~~~~~~~~~~~~~~~  5ebe90af		sqdmlal d15, s5, s30
+0x~~~~~~~~~~~~~~~~  5fa23958		sqdmlal d24, s10, v2.s[3]
+0x~~~~~~~~~~~~~~~~  5e689269		sqdmlal s9, h19, h8
+0x~~~~~~~~~~~~~~~~  5f7c302e		sqdmlal s14, h1, v12.h[3]
+0x~~~~~~~~~~~~~~~~  0ebf90be		sqdmlal v30.2d, v5.2s, v31.2s
+0x~~~~~~~~~~~~~~~~  0faa31d9		sqdmlal v25.2d, v14.2s, v10.s[1]
+0x~~~~~~~~~~~~~~~~  0e709233		sqdmlal v19.4s, v17.4h, v16.4h
+0x~~~~~~~~~~~~~~~~  0f5830a8		sqdmlal v8.4s, v5.4h, v8.h[1]
+0x~~~~~~~~~~~~~~~~  4ea392e1		sqdmlal2 v1.2d, v23.4s, v3.4s
+0x~~~~~~~~~~~~~~~~  4f893013		sqdmlal2 v19.2d, v0.4s, v9.s[0]
+0x~~~~~~~~~~~~~~~~  4e6b92da		sqdmlal2 v26.4s, v22.8h, v11.8h
+0x~~~~~~~~~~~~~~~~  4f4d3b86		sqdmlal2 v6.4s, v28.8h, v13.h[4]
+0x~~~~~~~~~~~~~~~~  5eb4b3aa		sqdmlsl d10, s29, s20
+0x~~~~~~~~~~~~~~~~  5faa712a		sqdmlsl d10, s9, v10.s[1]
+0x~~~~~~~~~~~~~~~~  5e78b13e		sqdmlsl s30, h9, h24
+0x~~~~~~~~~~~~~~~~  5f56730d		sqdmlsl s13, h24, v6.h[1]
+0x~~~~~~~~~~~~~~~~  0eb4b15b		sqdmlsl v27.2d, v10.2s, v20.2s
+0x~~~~~~~~~~~~~~~~  0fa37af7		sqdmlsl v23.2d, v23.2s, v3.s[3]
+0x~~~~~~~~~~~~~~~~  0e7db227		sqdmlsl v7.4s, v17.4h, v29.4h
+0x~~~~~~~~~~~~~~~~  0f437ab6		sqdmlsl v22.4s, v21.4h, v3.h[4]
+0x~~~~~~~~~~~~~~~~  4eb6b0ec		sqdmlsl2 v12.2d, v7.4s, v22.4s
+0x~~~~~~~~~~~~~~~~  4f887334		sqdmlsl2 v20.2d, v25.4s, v8.s[0]
+0x~~~~~~~~~~~~~~~~  4e72b359		sqdmlsl2 v25.4s, v26.8h, v18.8h
+0x~~~~~~~~~~~~~~~~  4f457279		sqdmlsl2 v25.4s, v19.8h, v5.h[0]
+0x~~~~~~~~~~~~~~~~  5e6cb771		sqdmulh h17, h27, h12
+0x~~~~~~~~~~~~~~~~  5f4bc0b0		sqdmulh h16, h5, v11.h[0]
+0x~~~~~~~~~~~~~~~~  5eb0b661		sqdmulh s1, s19, s16
+0x~~~~~~~~~~~~~~~~  5f82c201		sqdmulh s1, s16, v2.s[0]
+0x~~~~~~~~~~~~~~~~  0ea8b43c		sqdmulh v28.2s, v1.2s, v8.2s
+0x~~~~~~~~~~~~~~~~  0f83c11c		sqdmulh v28.2s, v8.2s, v3.s[0]
+0x~~~~~~~~~~~~~~~~  0e65b72b		sqdmulh v11.4h, v25.4h, v5.4h
+0x~~~~~~~~~~~~~~~~  0f58c9de		sqdmulh v30.4h, v14.4h, v8.h[5]
+0x~~~~~~~~~~~~~~~~  4eadb6b9		sqdmulh v25.4s, v21.4s, v13.4s
+0x~~~~~~~~~~~~~~~~  4faac857		sqdmulh v23.4s, v2.4s, v10.s[3]
+0x~~~~~~~~~~~~~~~~  4e77b4ba		sqdmulh v26.8h, v5.8h, v23.8h
+0x~~~~~~~~~~~~~~~~  4f74c2c4		sqdmulh v4.8h, v22.8h, v4.h[3]
+0x~~~~~~~~~~~~~~~~  5ebad059		sqdmull d25, s2, s26
+0x~~~~~~~~~~~~~~~~  5fa5b1de		sqdmull d30, s14, v5.s[1]
+0x~~~~~~~~~~~~~~~~  5e6bd25d		sqdmull s29, h18, h11
+0x~~~~~~~~~~~~~~~~  5f67b9ab		sqdmull s11, h13, v7.h[6]
+0x~~~~~~~~~~~~~~~~  0ea8d137		sqdmull v23.2d, v9.2s, v8.2s
+0x~~~~~~~~~~~~~~~~  0fa4b3b2		sqdmull v18.2d, v29.2s, v4.s[1]
+0x~~~~~~~~~~~~~~~~  0e67d311		sqdmull v17.4s, v24.4h, v7.4h
+0x~~~~~~~~~~~~~~~~  0f55b1e8		sqdmull v8.4s, v15.4h, v5.h[1]
+0x~~~~~~~~~~~~~~~~  4ea2d1dc		sqdmull2 v28.2d, v14.4s, v2.4s
+0x~~~~~~~~~~~~~~~~  4f8dbb01		sqdmull2 v1.2d, v24.4s, v13.s[2]
+0x~~~~~~~~~~~~~~~~  4e7fd22b		sqdmull2 v11.4s, v17.8h, v31.8h
+0x~~~~~~~~~~~~~~~~  4f7bb281		sqdmull2 v1.4s, v20.8h, v11.h[3]
+0x~~~~~~~~~~~~~~~~  7e207802		sqneg b2, b0
+0x~~~~~~~~~~~~~~~~  7ee07858		sqneg d24, d2
+0x~~~~~~~~~~~~~~~~  7e60787d		sqneg h29, h3
+0x~~~~~~~~~~~~~~~~  7ea07924		sqneg s4, s9
+0x~~~~~~~~~~~~~~~~  6e207bae		sqneg v14.16b, v29.16b
+0x~~~~~~~~~~~~~~~~  6ee0799e		sqneg v30.2d, v12.2d
+0x~~~~~~~~~~~~~~~~  2ea07b5c		sqneg v28.2s, v26.2s
+0x~~~~~~~~~~~~~~~~  2e607884		sqneg v4.4h, v4.4h
+0x~~~~~~~~~~~~~~~~  6ea07909		sqneg v9.4s, v8.4s
+0x~~~~~~~~~~~~~~~~  2e207a94		sqneg v20.8b, v20.8b
+0x~~~~~~~~~~~~~~~~  6e60795b		sqneg v27.8h, v10.8h
+0x~~~~~~~~~~~~~~~~  7e60b707		sqrdmulh h7, h24, h0
+0x~~~~~~~~~~~~~~~~  5f64d86e		sqrdmulh h14, h3, v4.h[6]
+0x~~~~~~~~~~~~~~~~  7eb8b67b		sqrdmulh s27, s19, s24
+0x~~~~~~~~~~~~~~~~  5f84d2bf		sqrdmulh s31, s21, v4.s[0]
+0x~~~~~~~~~~~~~~~~  2ea1b732		sqrdmulh v18.2s, v25.2s, v1.2s
+0x~~~~~~~~~~~~~~~~  0f8dd0b6		sqrdmulh v22.2s, v5.2s, v13.s[0]
+0x~~~~~~~~~~~~~~~~  2e69b716		sqrdmulh v22.4h, v24.4h, v9.4h
+0x~~~~~~~~~~~~~~~~  0f6cd84d		sqrdmulh v13.4h, v2.4h, v12.h[6]
+0x~~~~~~~~~~~~~~~~  6ea2b769		sqrdmulh v9.4s, v27.4s, v2.4s
+0x~~~~~~~~~~~~~~~~  4fa7d2e3		sqrdmulh v3.4s, v23.4s, v7.s[1]
+0x~~~~~~~~~~~~~~~~  6e67b402		sqrdmulh v2.8h, v0.8h, v7.8h
+0x~~~~~~~~~~~~~~~~  4f68d130		sqrdmulh v16.8h, v9.8h, v8.h[2]
+0x~~~~~~~~~~~~~~~~  5e2d5ea8		sqrshl b8, b21, b13
+0x~~~~~~~~~~~~~~~~  5ef45cfd		sqrshl d29, d7, d20
+0x~~~~~~~~~~~~~~~~  5e6a5ddc		sqrshl h28, h14, h10
+0x~~~~~~~~~~~~~~~~  5ea25e5a		sqrshl s26, s18, s2
+0x~~~~~~~~~~~~~~~~  4e3a5ff2		sqrshl v18.16b, v31.16b, v26.16b
+0x~~~~~~~~~~~~~~~~  4ee05c9c		sqrshl v28.2d, v4.2d, v0.2d
+0x~~~~~~~~~~~~~~~~  0ea05cc3		sqrshl v3.2s, v6.2s, v0.2s
+0x~~~~~~~~~~~~~~~~  0e765e41		sqrshl v1.4h, v18.4h, v22.4h
+0x~~~~~~~~~~~~~~~~  4ea75f30		sqrshl v16.4s, v25.4s, v7.4s
+0x~~~~~~~~~~~~~~~~  0e255ea0		sqrshl v0.8b, v21.8b, v5.8b
+0x~~~~~~~~~~~~~~~~  4e685e7e		sqrshl v30.8h, v19.8h, v8.8h
+0x~~~~~~~~~~~~~~~~  5f0c9ea6		sqrshrn b6, h21, #4
+0x~~~~~~~~~~~~~~~~  5f159e2e		sqrshrn h14, s17, #11
+0x~~~~~~~~~~~~~~~~  5f369f79		sqrshrn s25, d27, #10
+0x~~~~~~~~~~~~~~~~  0f2e9da6		sqrshrn v6.2s, v13.2d, #18
+0x~~~~~~~~~~~~~~~~  0f119d25		sqrshrn v5.4h, v9.4s, #15
+0x~~~~~~~~~~~~~~~~  0f0f9d93		sqrshrn v19.8b, v12.8h, #1
+0x~~~~~~~~~~~~~~~~  4f099eb3		sqrshrn2 v19.16b, v21.8h, #7
+0x~~~~~~~~~~~~~~~~  4f339f1d		sqrshrn2 v29.4s, v24.2d, #13
+0x~~~~~~~~~~~~~~~~  4f169c4c		sqrshrn2 v12.8h, v2.4s, #10
+0x~~~~~~~~~~~~~~~~  7f0b8d30		sqrshrun b16, h9, #5
+0x~~~~~~~~~~~~~~~~  7f118f03		sqrshrun h3, s24, #15
+0x~~~~~~~~~~~~~~~~  7f388e50		sqrshrun s16, d18, #8
+0x~~~~~~~~~~~~~~~~  2f388efc		sqrshrun v28.2s, v23.2d, #8
+0x~~~~~~~~~~~~~~~~  2f168f3f		sqrshrun v31.4h, v25.4s, #10
+0x~~~~~~~~~~~~~~~~  2f0e8ef3		sqrshrun v19.8b, v23.8h, #2
+0x~~~~~~~~~~~~~~~~  6f088c18		sqrshrun2 v24.16b, v0.8h, #8
+0x~~~~~~~~~~~~~~~~  6f298c36		sqrshrun2 v22.4s, v1.2d, #23
+0x~~~~~~~~~~~~~~~~  6f138ebc		sqrshrun2 v28.8h, v21.4s, #13
+0x~~~~~~~~~~~~~~~~  5e284ea6		sqshl b6, b21, b8
+0x~~~~~~~~~~~~~~~~  5f0a774b		sqshl b11, b26, #2
+0x~~~~~~~~~~~~~~~~  5ee44c1d		sqshl d29, d0, d4
+0x~~~~~~~~~~~~~~~~  5f6374f5		sqshl d21, d7, #35
+0x~~~~~~~~~~~~~~~~  5e714f34		sqshl h20, h25, h17
+0x~~~~~~~~~~~~~~~~  5f187414		sqshl h20, h0, #8
+0x~~~~~~~~~~~~~~~~  5ea44dbd		sqshl s29, s13, s4
+0x~~~~~~~~~~~~~~~~  5f34756a		sqshl s10, s11, #20
+0x~~~~~~~~~~~~~~~~  4e3c4e48		sqshl v8.16b, v18.16b, v28.16b
+0x~~~~~~~~~~~~~~~~  4f0a77bd		sqshl v29.16b, v29.16b, #2
+0x~~~~~~~~~~~~~~~~  4ef04fe8		sqshl v8.2d, v31.2d, v16.2d
+0x~~~~~~~~~~~~~~~~  4f6575c7		sqshl v7.2d, v14.2d, #37
+0x~~~~~~~~~~~~~~~~  0ea74f40		sqshl v0.2s, v26.2s, v7.2s
+0x~~~~~~~~~~~~~~~~  0f337565		sqshl v5.2s, v11.2s, #19
+0x~~~~~~~~~~~~~~~~  0e604fcb		sqshl v11.4h, v30.4h, v0.4h
+0x~~~~~~~~~~~~~~~~  0f177641		sqshl v1.4h, v18.4h, #7
+0x~~~~~~~~~~~~~~~~  4ebe4c76		sqshl v22.4s, v3.4s, v30.4s
+0x~~~~~~~~~~~~~~~~  4f3c75f0		sqshl v16.4s, v15.4s, #28
+0x~~~~~~~~~~~~~~~~  0e394f86		sqshl v6.8b, v28.8b, v25.8b
+0x~~~~~~~~~~~~~~~~  0f0875e0		sqshl v0.8b, v15.8b, #0
+0x~~~~~~~~~~~~~~~~  4e7e4e06		sqshl v6.8h, v16.8h, v30.8h
+0x~~~~~~~~~~~~~~~~  4f1e7683		sqshl v3.8h, v20.8h, #14
+0x~~~~~~~~~~~~~~~~  7f0e65cd		sqshlu b13, b14, #6
+0x~~~~~~~~~~~~~~~~  7f6c6600		sqshlu d0, d16, #44
+0x~~~~~~~~~~~~~~~~  7f1f67a5		sqshlu h5, h29, #15
+0x~~~~~~~~~~~~~~~~  7f2d651d		sqshlu s29, s8, #13
+0x~~~~~~~~~~~~~~~~  6f0a669b		sqshlu v27.16b, v20.16b, #2
+0x~~~~~~~~~~~~~~~~  6f4b6598		sqshlu v24.2d, v12.2d, #11
+0x~~~~~~~~~~~~~~~~  2f36666c		sqshlu v12.2s, v19.2s, #22
+0x~~~~~~~~~~~~~~~~  2f1b6588		sqshlu v8.4h, v12.4h, #11
+0x~~~~~~~~~~~~~~~~  6f286472		sqshlu v18.4s, v3.4s, #8
+0x~~~~~~~~~~~~~~~~  2f096543		sqshlu v3.8b, v10.8b, #1
+0x~~~~~~~~~~~~~~~~  6f14671e		sqshlu v30.8h, v24.8h, #4
+0x~~~~~~~~~~~~~~~~  5f0f9781		sqshrn b1, h28, #1
+0x~~~~~~~~~~~~~~~~  5f1694ff		sqshrn h31, s7, #10
+0x~~~~~~~~~~~~~~~~  5f289544		sqshrn s4, d10, #24
+0x~~~~~~~~~~~~~~~~  0f23942a		sqshrn v10.2s, v1.2d, #29
+0x~~~~~~~~~~~~~~~~  0f1295a3		sqshrn v3.4h, v13.4s, #14
+0x~~~~~~~~~~~~~~~~  0f0994db		sqshrn v27.8b, v6.8h, #7
+0x~~~~~~~~~~~~~~~~  4f0f96ee		sqshrn2 v14.16b, v23.8h, #1
+0x~~~~~~~~~~~~~~~~  4f2596d9		sqshrn2 v25.4s, v22.2d, #27
+0x~~~~~~~~~~~~~~~~  4f16959f		sqshrn2 v31.8h, v12.4s, #10
+0x~~~~~~~~~~~~~~~~  7f0f8409		sqshrun b9, h0, #1
+0x~~~~~~~~~~~~~~~~  7f1984cb		sqshrun h11, s6, #7
+0x~~~~~~~~~~~~~~~~  7f33858d		sqshrun s13, d12, #13
+0x~~~~~~~~~~~~~~~~  2f3f87ca		sqshrun v10.2s, v30.2d, #1
+0x~~~~~~~~~~~~~~~~  2f15847f		sqshrun v31.4h, v3.4s, #11
+0x~~~~~~~~~~~~~~~~  2f0887dc		sqshrun v28.8b, v30.8h, #8
+0x~~~~~~~~~~~~~~~~  6f0d8770		sqshrun2 v16.16b, v27.8h, #3
+0x~~~~~~~~~~~~~~~~  6f2e85db		sqshrun2 v27.4s, v14.2d, #18
+0x~~~~~~~~~~~~~~~~  6f1f85d7		sqshrun2 v23.8h, v14.4s, #1
+0x~~~~~~~~~~~~~~~~  5e2b2fb3		sqsub b19, b29, b11
+0x~~~~~~~~~~~~~~~~  5ee62ff5		sqsub d21, d31, d6
+0x~~~~~~~~~~~~~~~~  5e732d52		sqsub h18, h10, h19
+0x~~~~~~~~~~~~~~~~  5ea02ca6		sqsub s6, s5, s0
+0x~~~~~~~~~~~~~~~~  4e202ed5		sqsub v21.16b, v22.16b, v0.16b
+0x~~~~~~~~~~~~~~~~  4ef12d56		sqsub v22.2d, v10.2d, v17.2d
+0x~~~~~~~~~~~~~~~~  0ea22ea8		sqsub v8.2s, v21.2s, v2.2s
+0x~~~~~~~~~~~~~~~~  0e7b2f32		sqsub v18.4h, v25.4h, v27.4h
+0x~~~~~~~~~~~~~~~~  4ea62c6d		sqsub v13.4s, v3.4s, v6.4s
+0x~~~~~~~~~~~~~~~~  0e302fbc		sqsub v28.8b, v29.8b, v16.8b
+0x~~~~~~~~~~~~~~~~  4e6a2cd1		sqsub v17.8h, v6.8h, v10.8h
+0x~~~~~~~~~~~~~~~~  5e214b5b		sqxtn b27, h26
+0x~~~~~~~~~~~~~~~~  5e614971		sqxtn h17, s11
+0x~~~~~~~~~~~~~~~~  5ea14bf6		sqxtn s22, d31
+0x~~~~~~~~~~~~~~~~  0ea148ba		sqxtn v26.2s, v5.2d
+0x~~~~~~~~~~~~~~~~  0e6148ed		sqxtn v13.4h, v7.4s
+0x~~~~~~~~~~~~~~~~  0e214a73		sqxtn v19.8b, v19.8h
+0x~~~~~~~~~~~~~~~~  4e214873		sqxtn2 v19.16b, v3.8h
+0x~~~~~~~~~~~~~~~~  4ea14837		sqxtn2 v23.4s, v1.2d
+0x~~~~~~~~~~~~~~~~  4e61486d		sqxtn2 v13.8h, v3.4s
+0x~~~~~~~~~~~~~~~~  7e21293a		sqxtun b26, h9
+0x~~~~~~~~~~~~~~~~  7e612993		sqxtun h19, s12
+0x~~~~~~~~~~~~~~~~  7ea128c3		sqxtun s3, d6
+0x~~~~~~~~~~~~~~~~  2ea12b5d		sqxtun v29.2s, v26.2d
+0x~~~~~~~~~~~~~~~~  2e61295a		sqxtun v26.4h, v10.4s
+0x~~~~~~~~~~~~~~~~  2e212ba7		sqxtun v7.8b, v29.8h
+0x~~~~~~~~~~~~~~~~  6e2129d5		sqxtun2 v21.16b, v14.8h
+0x~~~~~~~~~~~~~~~~  6ea129f8		sqxtun2 v24.4s, v15.2d
+0x~~~~~~~~~~~~~~~~  6e61283e		sqxtun2 v30.8h, v1.4s
+0x~~~~~~~~~~~~~~~~  4e2f1635		srhadd v21.16b, v17.16b, v15.16b
+0x~~~~~~~~~~~~~~~~  0ebd16bc		srhadd v28.2s, v21.2s, v29.2s
+0x~~~~~~~~~~~~~~~~  0e7e1429		srhadd v9.4h, v1.4h, v30.4h
+0x~~~~~~~~~~~~~~~~  4ea21418		srhadd v24.4s, v0.4s, v2.4s
+0x~~~~~~~~~~~~~~~~  0e2f1626		srhadd v6.8b, v17.8b, v15.8b
+0x~~~~~~~~~~~~~~~~  4e7514e5		srhadd v5.8h, v7.8h, v21.8h
+0x~~~~~~~~~~~~~~~~  7f4f45ce		sri d14, d14, #49
+0x~~~~~~~~~~~~~~~~  6f0c4517		sri v23.16b, v8.16b, #4
+0x~~~~~~~~~~~~~~~~  6f6c45b4		sri v20.2d, v13.2d, #20
+0x~~~~~~~~~~~~~~~~  2f284450		sri v16.2s, v2.2s, #24
+0x~~~~~~~~~~~~~~~~  2f1546e5		sri v5.4h, v23.4h, #11
+0x~~~~~~~~~~~~~~~~  6f2945fb		sri v27.4s, v15.4s, #23
+0x~~~~~~~~~~~~~~~~  2f0c47b3		sri v19.8b, v29.8b, #4
+0x~~~~~~~~~~~~~~~~  6f1d47a7		sri v7.8h, v29.8h, #3
+0x~~~~~~~~~~~~~~~~  5efa5522		srshl d2, d9, d26
+0x~~~~~~~~~~~~~~~~  4e2b563d		srshl v29.16b, v17.16b, v11.16b
+0x~~~~~~~~~~~~~~~~  4ee455e8		srshl v8.2d, v15.2d, v4.2d
+0x~~~~~~~~~~~~~~~~  0ea85639		srshl v25.2s, v17.2s, v8.2s
+0x~~~~~~~~~~~~~~~~  0e6754f3		srshl v19.4h, v7.4h, v7.4h
+0x~~~~~~~~~~~~~~~~  4eb1544d		srshl v13.4s, v2.4s, v17.4s
+0x~~~~~~~~~~~~~~~~  0e3554d6		srshl v22.8b, v6.8b, v21.8b
+0x~~~~~~~~~~~~~~~~  4e64562a		srshl v10.8h, v17.8h, v4.8h
+0x~~~~~~~~~~~~~~~~  5f532655		srshr d21, d18, #45
+0x~~~~~~~~~~~~~~~~  4f092563		srshr v3.16b, v11.16b, #7
+0x~~~~~~~~~~~~~~~~  4f4b2755		srshr v21.2d, v26.2d, #53
+0x~~~~~~~~~~~~~~~~  0f2424ab		srshr v11.2s, v5.2s, #28
+0x~~~~~~~~~~~~~~~~  0f142647		srshr v7.4h, v18.4h, #12
+0x~~~~~~~~~~~~~~~~  4f222467		srshr v7.4s, v3.4s, #30
+0x~~~~~~~~~~~~~~~~  0f0a244e		srshr v14.8b, v2.8b, #6
+0x~~~~~~~~~~~~~~~~  4f1d2695		srshr v21.8h, v20.8h, #3
+0x~~~~~~~~~~~~~~~~  5f4137d5		srsra d21, d30, #63
+0x~~~~~~~~~~~~~~~~  4f0a37db		srsra v27.16b, v30.16b, #6
+0x~~~~~~~~~~~~~~~~  4f653594		srsra v20.2d, v12.2d, #27
+0x~~~~~~~~~~~~~~~~  0f3b3620		srsra v0.2s, v17.2s, #5
+0x~~~~~~~~~~~~~~~~  0f11360e		srsra v14.4h, v16.4h, #15
+0x~~~~~~~~~~~~~~~~  4f2c3472		srsra v18.4s, v3.4s, #20
+0x~~~~~~~~~~~~~~~~  0f0f3435		srsra v21.8b, v1.8b, #1
+0x~~~~~~~~~~~~~~~~  4f1e373f		srsra v31.8h, v25.8h, #2
+0x~~~~~~~~~~~~~~~~  5ee945a1		sshl d1, d13, d9
+0x~~~~~~~~~~~~~~~~  4e2f47f1		sshl v17.16b, v31.16b, v15.16b
+0x~~~~~~~~~~~~~~~~  4ee0460d		sshl v13.2d, v16.2d, v0.2d
+0x~~~~~~~~~~~~~~~~  0eb644e0		sshl v0.2s, v7.2s, v22.2s
+0x~~~~~~~~~~~~~~~~  0e644677		sshl v23.4h, v19.4h, v4.4h
+0x~~~~~~~~~~~~~~~~  4eab44a5		sshl v5.4s, v5.4s, v11.4s
+0x~~~~~~~~~~~~~~~~  0e274777		sshl v23.8b, v27.8b, v7.8b
+0x~~~~~~~~~~~~~~~~  4e65455d		sshl v29.8h, v10.8h, v5.8h
+0x~~~~~~~~~~~~~~~~  0f37a440		sshll v0.2d, v2.2s, #23
+0x~~~~~~~~~~~~~~~~  0f18a50b		sshll v11.4s, v8.4h, #8
+0x~~~~~~~~~~~~~~~~  0f09a7a4		sshll v4.8h, v29.8b, #1
+0x~~~~~~~~~~~~~~~~  4f2ea48a		sshll2 v10.2d, v4.4s, #14
+0x~~~~~~~~~~~~~~~~  4f16a7fa		sshll2 v26.4s, v31.8h, #6
+0x~~~~~~~~~~~~~~~~  4f0ca743		sshll2 v3.8h, v26.16b, #4
+0x~~~~~~~~~~~~~~~~  5f6c06b3		sshr d19, d21, #20
+0x~~~~~~~~~~~~~~~~  4f0b06ef		sshr v15.16b, v23.16b, #5
+0x~~~~~~~~~~~~~~~~  4f5a05d1		sshr v17.2d, v14.2d, #38
+0x~~~~~~~~~~~~~~~~  0f2907a3		sshr v3.2s, v29.2s, #23
+0x~~~~~~~~~~~~~~~~  0f1c0777		sshr v23.4h, v27.4h, #4
+0x~~~~~~~~~~~~~~~~  4f3c047c		sshr v28.4s, v3.4s, #4
+0x~~~~~~~~~~~~~~~~  0f0a044e		sshr v14.8b, v2.8b, #6
+0x~~~~~~~~~~~~~~~~  4f1a0503		sshr v3.8h, v8.8h, #6
+0x~~~~~~~~~~~~~~~~  5f54178c		ssra d12, d28, #44
+0x~~~~~~~~~~~~~~~~  4f0c17fd		ssra v29.16b, v31.16b, #4
+0x~~~~~~~~~~~~~~~~  4f681403		ssra v3.2d, v0.2d, #24
+0x~~~~~~~~~~~~~~~~  0f3a178e		ssra v14.2s, v28.2s, #6
+0x~~~~~~~~~~~~~~~~  0f191512		ssra v18.4h, v8.4h, #7
+0x~~~~~~~~~~~~~~~~  4f2815df		ssra v31.4s, v14.4s, #24
+0x~~~~~~~~~~~~~~~~  0f0b175c		ssra v28.8b, v26.8b, #5
+0x~~~~~~~~~~~~~~~~  4f121529		ssra v9.8h, v9.8h, #14
+0x~~~~~~~~~~~~~~~~  0ea321cd		ssubl v13.2d, v14.2s, v3.2s
+0x~~~~~~~~~~~~~~~~  0e682205		ssubl v5.4s, v16.4h, v8.4h
+0x~~~~~~~~~~~~~~~~  0e262380		ssubl v0.8h, v28.8b, v6.8b
+0x~~~~~~~~~~~~~~~~  4eb921a5		ssubl2 v5.2d, v13.4s, v25.4s
+0x~~~~~~~~~~~~~~~~  4e7121e3		ssubl2 v3.4s, v15.8h, v17.8h
+0x~~~~~~~~~~~~~~~~  4e2e21ef		ssubl2 v15.8h, v15.16b, v14.16b
+0x~~~~~~~~~~~~~~~~  0eba32f9		ssubw v25.2d, v23.2d, v26.2s
+0x~~~~~~~~~~~~~~~~  0e783255		ssubw v21.4s, v18.4s, v24.4h
+0x~~~~~~~~~~~~~~~~  0e2332de		ssubw v30.8h, v22.8h, v3.8b
+0x~~~~~~~~~~~~~~~~  4ebc3310		ssubw2 v16.2d, v24.2d, v28.4s
+0x~~~~~~~~~~~~~~~~  4e6f317f		ssubw2 v31.4s, v11.4s, v15.8h
+0x~~~~~~~~~~~~~~~~  4e303104		ssubw2 v4.8h, v8.8h, v16.16b
+0x~~~~~~~~~~~~~~~~  4c002012		st1 {v18.16b, v19.16b, v20.16b, v21.16b}, [x0]
+0x~~~~~~~~~~~~~~~~  4c82202a		st1 {v10.16b, v11.16b, v12.16b, v13.16b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f203b		st1 {v27.16b, v28.16b, v29.16b, v30.16b}, [x1], #64
+0x~~~~~~~~~~~~~~~~  4c006010		st1 {v16.16b, v17.16b, v18.16b}, [x0]
+0x~~~~~~~~~~~~~~~~  4c826035		st1 {v21.16b, v22.16b, v23.16b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f6029		st1 {v9.16b, v10.16b, v11.16b}, [x1], #48
+0x~~~~~~~~~~~~~~~~  4c00a007		st1 {v7.16b, v8.16b}, [x0]
+0x~~~~~~~~~~~~~~~~  4c82a03a		st1 {v26.16b, v27.16b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9fa036		st1 {v22.16b, v23.16b}, [x1], #32
+0x~~~~~~~~~~~~~~~~  4c007017		st1 {v23.16b}, [x0]
+0x~~~~~~~~~~~~~~~~  4c82703c		st1 {v28.16b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f7022		st1 {v2.16b}, [x1], #16
+0x~~~~~~~~~~~~~~~~  0c002c1d		st1 {v29.1d, v30.1d, v31.1d, v0.1d}, [x0]
+0x~~~~~~~~~~~~~~~~  0c822c2c		st1 {v12.1d, v13.1d, v14.1d, v15.1d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f2c3e		st1 {v30.1d, v31.1d, v0.1d, v1.1d}, [x1], #32
+0x~~~~~~~~~~~~~~~~  0c006c10		st1 {v16.1d, v17.1d, v18.1d}, [x0]
+0x~~~~~~~~~~~~~~~~  0c826c23		st1 {v3.1d, v4.1d, v5.1d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f6c2e		st1 {v14.1d, v15.1d, v16.1d}, [x1], #24
+0x~~~~~~~~~~~~~~~~  0c00ac12		st1 {v18.1d, v19.1d}, [x0]
+0x~~~~~~~~~~~~~~~~  0c82ac25		st1 {v5.1d, v6.1d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9fac22		st1 {v2.1d, v3.1d}, [x1], #16
+0x~~~~~~~~~~~~~~~~  0c007c04		st1 {v4.1d}, [x0]
+0x~~~~~~~~~~~~~~~~  0c827c3b		st1 {v27.1d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f7c37		st1 {v23.1d}, [x1], #8
+0x~~~~~~~~~~~~~~~~  4c002c02		st1 {v2.2d, v3.2d, v4.2d, v5.2d}, [x0]
+0x~~~~~~~~~~~~~~~~  4c822c36		st1 {v22.2d, v23.2d, v24.2d, v25.2d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f2c3c		st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x1], #64
+0x~~~~~~~~~~~~~~~~  4c006c11		st1 {v17.2d, v18.2d, v19.2d}, [x0]
+0x~~~~~~~~~~~~~~~~  4c826c30		st1 {v16.2d, v17.2d, v18.2d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f6c36		st1 {v22.2d, v23.2d, v24.2d}, [x1], #48
+0x~~~~~~~~~~~~~~~~  4c00ac15		st1 {v21.2d, v22.2d}, [x0]
+0x~~~~~~~~~~~~~~~~  4c82ac26		st1 {v6.2d, v7.2d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9fac3b		st1 {v27.2d, v28.2d}, [x1], #32
+0x~~~~~~~~~~~~~~~~  4c007c15		st1 {v21.2d}, [x0]
+0x~~~~~~~~~~~~~~~~  4c827c3d		st1 {v29.2d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f7c34		st1 {v20.2d}, [x1], #16
+0x~~~~~~~~~~~~~~~~  0c002816		st1 {v22.2s, v23.2s, v24.2s, v25.2s}, [x0]
+0x~~~~~~~~~~~~~~~~  0c822828		st1 {v8.2s, v9.2s, v10.2s, v11.2s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f282f		st1 {v15.2s, v16.2s, v17.2s, v18.2s}, [x1], #32
+0x~~~~~~~~~~~~~~~~  0c006802		st1 {v2.2s, v3.2s, v4.2s}, [x0]
+0x~~~~~~~~~~~~~~~~  0c826837		st1 {v23.2s, v24.2s, v25.2s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f6827		st1 {v7.2s, v8.2s, v9.2s}, [x1], #24
+0x~~~~~~~~~~~~~~~~  0c00a81c		st1 {v28.2s, v29.2s}, [x0]
+0x~~~~~~~~~~~~~~~~  0c82a83d		st1 {v29.2s, v30.2s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9fa837		st1 {v23.2s, v24.2s}, [x1], #16
+0x~~~~~~~~~~~~~~~~  0c007806		st1 {v6.2s}, [x0]
+0x~~~~~~~~~~~~~~~~  0c82782b		st1 {v11.2s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f7831		st1 {v17.2s}, [x1], #8
+0x~~~~~~~~~~~~~~~~  0c002406		st1 {v6.4h, v7.4h, v8.4h, v9.4h}, [x0]
+0x~~~~~~~~~~~~~~~~  0c822429		st1 {v9.4h, v10.4h, v11.4h, v12.4h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f2439		st1 {v25.4h, v26.4h, v27.4h, v28.4h}, [x1], #32
+0x~~~~~~~~~~~~~~~~  0c00640b		st1 {v11.4h, v12.4h, v13.4h}, [x0]
+0x~~~~~~~~~~~~~~~~  0c82642a		st1 {v10.4h, v11.4h, v12.4h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f642c		st1 {v12.4h, v13.4h, v14.4h}, [x1], #24
+0x~~~~~~~~~~~~~~~~  0c00a40d		st1 {v13.4h, v14.4h}, [x0]
+0x~~~~~~~~~~~~~~~~  0c82a42f		st1 {v15.4h, v16.4h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9fa435		st1 {v21.4h, v22.4h}, [x1], #16
+0x~~~~~~~~~~~~~~~~  0c007410		st1 {v16.4h}, [x0]
+0x~~~~~~~~~~~~~~~~  0c827428		st1 {v8.4h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f743e		st1 {v30.4h}, [x1], #8
+0x~~~~~~~~~~~~~~~~  4c002803		st1 {v3.4s, v4.4s, v5.4s, v6.4s}, [x0]
+0x~~~~~~~~~~~~~~~~  4c822839		st1 {v25.4s, v26.4s, v27.4s, v28.4s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f2825		st1 {v5.4s, v6.4s, v7.4s, v8.4s}, [x1], #64
+0x~~~~~~~~~~~~~~~~  4c00681f		st1 {v31.4s, v0.4s, v1.4s}, [x0]
+0x~~~~~~~~~~~~~~~~  4c82683e		st1 {v30.4s, v31.4s, v0.4s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f6826		st1 {v6.4s, v7.4s, v8.4s}, [x1], #48
+0x~~~~~~~~~~~~~~~~  4c00a811		st1 {v17.4s, v18.4s}, [x0]
+0x~~~~~~~~~~~~~~~~  4c82a83f		st1 {v31.4s, v0.4s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9fa821		st1 {v1.4s, v2.4s}, [x1], #32
+0x~~~~~~~~~~~~~~~~  4c00781a		st1 {v26.4s}, [x0]
+0x~~~~~~~~~~~~~~~~  4c82782f		st1 {v15.4s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f782d		st1 {v13.4s}, [x1], #16
+0x~~~~~~~~~~~~~~~~  0c00201a		st1 {v26.8b, v27.8b, v28.8b, v29.8b}, [x0]
+0x~~~~~~~~~~~~~~~~  0c82202a		st1 {v10.8b, v11.8b, v12.8b, v13.8b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f202f		st1 {v15.8b, v16.8b, v17.8b, v18.8b}, [x1], #32
+0x~~~~~~~~~~~~~~~~  0c006013		st1 {v19.8b, v20.8b, v21.8b}, [x0]
+0x~~~~~~~~~~~~~~~~  0c82603f		st1 {v31.8b, v0.8b, v1.8b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f6029		st1 {v9.8b, v10.8b, v11.8b}, [x1], #24
+0x~~~~~~~~~~~~~~~~  0c00a00c		st1 {v12.8b, v13.8b}, [x0]
+0x~~~~~~~~~~~~~~~~  0c82a022		st1 {v2.8b, v3.8b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9fa020		st1 {v0.8b, v1.8b}, [x1], #16
+0x~~~~~~~~~~~~~~~~  0c007010		st1 {v16.8b}, [x0]
+0x~~~~~~~~~~~~~~~~  0c827039		st1 {v25.8b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f703f		st1 {v31.8b}, [x1], #8
+0x~~~~~~~~~~~~~~~~  4c002404		st1 {v4.8h, v5.8h, v6.8h, v7.8h}, [x0]
+0x~~~~~~~~~~~~~~~~  4c822423		st1 {v3.8h, v4.8h, v5.8h, v6.8h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f243a		st1 {v26.8h, v27.8h, v28.8h, v29.8h}, [x1], #64
+0x~~~~~~~~~~~~~~~~  4c00640a		st1 {v10.8h, v11.8h, v12.8h}, [x0]
+0x~~~~~~~~~~~~~~~~  4c826435		st1 {v21.8h, v22.8h, v23.8h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f6432		st1 {v18.8h, v19.8h, v20.8h}, [x1], #48
+0x~~~~~~~~~~~~~~~~  4c00a41a		st1 {v26.8h, v27.8h}, [x0]
+0x~~~~~~~~~~~~~~~~  4c82a438		st1 {v24.8h, v25.8h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9fa431		st1 {v17.8h, v18.8h}, [x1], #32
+0x~~~~~~~~~~~~~~~~  4c00741d		st1 {v29.8h}, [x0]
+0x~~~~~~~~~~~~~~~~  4c827433		st1 {v19.8h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f7437		st1 {v23.8h}, [x1], #16
+0x~~~~~~~~~~~~~~~~  4d001c13		st1 {v19.b}[15], [x0]
+0x~~~~~~~~~~~~~~~~  4d820439		st1 {v25.b}[9], [x1], x2
+0x~~~~~~~~~~~~~~~~  4d9f0024		st1 {v4.b}[8], [x1], #1
+0x~~~~~~~~~~~~~~~~  0d00840d		st1 {v13.d}[0], [x0]
+0x~~~~~~~~~~~~~~~~  0d82843e		st1 {v30.d}[0], [x1], x2
+0x~~~~~~~~~~~~~~~~  0d9f8423		st1 {v3.d}[0], [x1], #8
+0x~~~~~~~~~~~~~~~~  0d004016		st1 {v22.h}[0], [x0]
+0x~~~~~~~~~~~~~~~~  4d82583f		st1 {v31.h}[7], [x1], x2
+0x~~~~~~~~~~~~~~~~  0d9f5837		st1 {v23.h}[3], [x1], #2
+0x~~~~~~~~~~~~~~~~  0d008000		st1 {v0.s}[0], [x0]
+0x~~~~~~~~~~~~~~~~  4d82902b		st1 {v11.s}[3], [x1], x2
+0x~~~~~~~~~~~~~~~~  4d9f9038		st1 {v24.s}[3], [x1], #4
+0x~~~~~~~~~~~~~~~~  4c008007		st2 {v7.16b, v8.16b}, [x0]
+0x~~~~~~~~~~~~~~~~  4c828025		st2 {v5.16b, v6.16b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f8032		st2 {v18.16b, v19.16b}, [x1], #32
+0x~~~~~~~~~~~~~~~~  4c008c0e		st2 {v14.2d, v15.2d}, [x0]
+0x~~~~~~~~~~~~~~~~  4c828c27		st2 {v7.2d, v8.2d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f8c38		st2 {v24.2d, v25.2d}, [x1], #32
+0x~~~~~~~~~~~~~~~~  0c008816		st2 {v22.2s, v23.2s}, [x0]
+0x~~~~~~~~~~~~~~~~  0c828824		st2 {v4.2s, v5.2s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f8822		st2 {v2.2s, v3.2s}, [x1], #16
+0x~~~~~~~~~~~~~~~~  0c008417		st2 {v23.4h, v24.4h}, [x0]
+0x~~~~~~~~~~~~~~~~  0c828428		st2 {v8.4h, v9.4h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f8427		st2 {v7.4h, v8.4h}, [x1], #16
+0x~~~~~~~~~~~~~~~~  4c008811		st2 {v17.4s, v18.4s}, [x0]
+0x~~~~~~~~~~~~~~~~  4c828826		st2 {v6.4s, v7.4s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f883a		st2 {v26.4s, v27.4s}, [x1], #32
+0x~~~~~~~~~~~~~~~~  0c00801f		st2 {v31.8b, v0.8b}, [x0]
+0x~~~~~~~~~~~~~~~~  0c828020		st2 {v0.8b, v1.8b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f8035		st2 {v21.8b, v22.8b}, [x1], #16
+0x~~~~~~~~~~~~~~~~  4c008407		st2 {v7.8h, v8.8h}, [x0]
+0x~~~~~~~~~~~~~~~~  4c828436		st2 {v22.8h, v23.8h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f8424		st2 {v4.8h, v5.8h}, [x1], #32
+0x~~~~~~~~~~~~~~~~  4d201c08		st2 {v8.b, v9.b}[15], [x0]
+0x~~~~~~~~~~~~~~~~  4da21c28		st2 {v8.b, v9.b}[15], [x1], x2
+0x~~~~~~~~~~~~~~~~  0dbf1027		st2 {v7.b, v8.b}[4], [x1], #2
+0x~~~~~~~~~~~~~~~~  0d208419		st2 {v25.d, v26.d}[0], [x0]
+0x~~~~~~~~~~~~~~~~  4da28431		st2 {v17.d, v18.d}[1], [x1], x2
+0x~~~~~~~~~~~~~~~~  4dbf8423		st2 {v3.d, v4.d}[1], [x1], #16
+0x~~~~~~~~~~~~~~~~  0d205804		st2 {v4.h, v5.h}[3], [x0]
+0x~~~~~~~~~~~~~~~~  4da24820		st2 {v0.h, v1.h}[5], [x1], x2
+0x~~~~~~~~~~~~~~~~  0dbf5036		st2 {v22.h, v23.h}[2], [x1], #4
+0x~~~~~~~~~~~~~~~~  4d20900e		st2 {v14.s, v15.s}[3], [x0]
+0x~~~~~~~~~~~~~~~~  4da29037		st2 {v23.s, v24.s}[3], [x1], x2
+0x~~~~~~~~~~~~~~~~  4dbf8020		st2 {v0.s, v1.s}[2], [x1], #8
+0x~~~~~~~~~~~~~~~~  4c00401a		st3 {v26.16b, v27.16b, v28.16b}, [x0]
+0x~~~~~~~~~~~~~~~~  4c824035		st3 {v21.16b, v22.16b, v23.16b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f4038		st3 {v24.16b, v25.16b, v26.16b}, [x1], #48
+0x~~~~~~~~~~~~~~~~  4c004c11		st3 {v17.2d, v18.2d, v19.2d}, [x0]
+0x~~~~~~~~~~~~~~~~  4c824c37		st3 {v23.2d, v24.2d, v25.2d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f4c2a		st3 {v10.2d, v11.2d, v12.2d}, [x1], #48
+0x~~~~~~~~~~~~~~~~  0c004809		st3 {v9.2s, v10.2s, v11.2s}, [x0]
+0x~~~~~~~~~~~~~~~~  0c82482d		st3 {v13.2s, v14.2s, v15.2s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f4836		st3 {v22.2s, v23.2s, v24.2s}, [x1], #24
+0x~~~~~~~~~~~~~~~~  0c00441f		st3 {v31.4h, v0.4h, v1.4h}, [x0]
+0x~~~~~~~~~~~~~~~~  0c824428		st3 {v8.4h, v9.4h, v10.4h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f4433		st3 {v19.4h, v20.4h, v21.4h}, [x1], #24
+0x~~~~~~~~~~~~~~~~  4c004812		st3 {v18.4s, v19.4s, v20.4s}, [x0]
+0x~~~~~~~~~~~~~~~~  4c824839		st3 {v25.4s, v26.4s, v27.4s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f4830		st3 {v16.4s, v17.4s, v18.4s}, [x1], #48
+0x~~~~~~~~~~~~~~~~  0c00401b		st3 {v27.8b, v28.8b, v29.8b}, [x0]
+0x~~~~~~~~~~~~~~~~  0c82403d		st3 {v29.8b, v30.8b, v31.8b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f403e		st3 {v30.8b, v31.8b, v0.8b}, [x1], #24
+0x~~~~~~~~~~~~~~~~  4c004408		st3 {v8.8h, v9.8h, v10.8h}, [x0]
+0x~~~~~~~~~~~~~~~~  4c824432		st3 {v18.8h, v19.8h, v20.8h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f4432		st3 {v18.8h, v19.8h, v20.8h}, [x1], #48
+0x~~~~~~~~~~~~~~~~  4d00281f		st3 {v31.b, v0.b, v1.b}[10], [x0]
+0x~~~~~~~~~~~~~~~~  0d823424		st3 {v4.b, v5.b, v6.b}[5], [x1], x2
+0x~~~~~~~~~~~~~~~~  0d9f2425		st3 {v5.b, v6.b, v7.b}[1], [x1], #3
+0x~~~~~~~~~~~~~~~~  0d00a405		st3 {v5.d, v6.d, v7.d}[0], [x0]
+0x~~~~~~~~~~~~~~~~  0d82a426		st3 {v6.d, v7.d, v8.d}[0], [x1], x2
+0x~~~~~~~~~~~~~~~~  0d9fa420		st3 {v0.d, v1.d, v2.d}[0], [x1], #24
+0x~~~~~~~~~~~~~~~~  0d00701f		st3 {v31.h, v0.h, v1.h}[2], [x0]
+0x~~~~~~~~~~~~~~~~  4d82682e		st3 {v14.h, v15.h, v16.h}[5], [x1], x2
+0x~~~~~~~~~~~~~~~~  4d9f7035		st3 {v21.h, v22.h, v23.h}[6], [x1], #6
+0x~~~~~~~~~~~~~~~~  0d00a015		st3 {v21.s, v22.s, v23.s}[0], [x0]
+0x~~~~~~~~~~~~~~~~  0d82b02b		st3 {v11.s, v12.s, v13.s}[1], [x1], x2
+0x~~~~~~~~~~~~~~~~  0d9fa02f		st3 {v15.s, v16.s, v17.s}[0], [x1], #12
+0x~~~~~~~~~~~~~~~~  4c000016		st4 {v22.16b, v23.16b, v24.16b, v25.16b}, [x0]
+0x~~~~~~~~~~~~~~~~  4c820038		st4 {v24.16b, v25.16b, v26.16b, v27.16b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f002f		st4 {v15.16b, v16.16b, v17.16b, v18.16b}, [x1], #64
+0x~~~~~~~~~~~~~~~~  4c000c10		st4 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0]
+0x~~~~~~~~~~~~~~~~  4c820c31		st4 {v17.2d, v18.2d, v19.2d, v20.2d}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f0c29		st4 {v9.2d, v10.2d, v11.2d, v12.2d}, [x1], #64
+0x~~~~~~~~~~~~~~~~  0c000817		st4 {v23.2s, v24.2s, v25.2s, v26.2s}, [x0]
+0x~~~~~~~~~~~~~~~~  0c82082f		st4 {v15.2s, v16.2s, v17.2s, v18.2s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f0838		st4 {v24.2s, v25.2s, v26.2s, v27.2s}, [x1], #32
+0x~~~~~~~~~~~~~~~~  0c00040e		st4 {v14.4h, v15.4h, v16.4h, v17.4h}, [x0]
+0x~~~~~~~~~~~~~~~~  0c820432		st4 {v18.4h, v19.4h, v20.4h, v21.4h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f0421		st4 {v1.4h, v2.4h, v3.4h, v4.4h}, [x1], #32
+0x~~~~~~~~~~~~~~~~  4c00080d		st4 {v13.4s, v14.4s, v15.4s, v16.4s}, [x0]
+0x~~~~~~~~~~~~~~~~  4c820826		st4 {v6.4s, v7.4s, v8.4s, v9.4s}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f082f		st4 {v15.4s, v16.4s, v17.4s, v18.4s}, [x1], #64
+0x~~~~~~~~~~~~~~~~  0c00001a		st4 {v26.8b, v27.8b, v28.8b, v29.8b}, [x0]
+0x~~~~~~~~~~~~~~~~  0c820039		st4 {v25.8b, v26.8b, v27.8b, v28.8b}, [x1], x2
+0x~~~~~~~~~~~~~~~~  0c9f0033		st4 {v19.8b, v20.8b, v21.8b, v22.8b}, [x1], #32
+0x~~~~~~~~~~~~~~~~  4c000413		st4 {v19.8h, v20.8h, v21.8h, v22.8h}, [x0]
+0x~~~~~~~~~~~~~~~~  4c82042f		st4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x1], x2
+0x~~~~~~~~~~~~~~~~  4c9f043f		st4 {v31.8h, v0.8h, v1.8h, v2.8h}, [x1], #64
+0x~~~~~~~~~~~~~~~~  4d203400		st4 {v0.b, v1.b, v2.b, v3.b}[13], [x0]
+0x~~~~~~~~~~~~~~~~  4da22824		st4 {v4.b, v5.b, v6.b, v7.b}[10], [x1], x2
+0x~~~~~~~~~~~~~~~~  4dbf2429		st4 {v9.b, v10.b, v11.b, v12.b}[9], [x1], #4
+0x~~~~~~~~~~~~~~~~  4d20a402		st4 {v2.d, v3.d, v4.d, v5.d}[1], [x0]
+0x~~~~~~~~~~~~~~~~  0da2a427		st4 {v7.d, v8.d, v9.d, v10.d}[0], [x1], x2
+0x~~~~~~~~~~~~~~~~  4dbfa43f		st4 {v31.d, v0.d, v1.d, v2.d}[1], [x1], #32
+0x~~~~~~~~~~~~~~~~  0d206802		st4 {v2.h, v3.h, v4.h, v5.h}[1], [x0]
+0x~~~~~~~~~~~~~~~~  0da2783b		st4 {v27.h, v28.h, v29.h, v30.h}[3], [x1], x2
+0x~~~~~~~~~~~~~~~~  4dbf6038		st4 {v24.h, v25.h, v26.h, v27.h}[4], [x1], #8
+0x~~~~~~~~~~~~~~~~  4d20a012		st4 {v18.s, v19.s, v20.s, v21.s}[2], [x0]
+0x~~~~~~~~~~~~~~~~  4da2a026		st4 {v6.s, v7.s, v8.s, v9.s}[2], [x1], x2
+0x~~~~~~~~~~~~~~~~  0dbfb039		st4 {v25.s, v26.s, v27.s, v28.s}[1], [x1], #16
+0x~~~~~~~~~~~~~~~~  7ee2862c		sub d12, d17, d2
+0x~~~~~~~~~~~~~~~~  6e288714		sub v20.16b, v24.16b, v8.16b
+0x~~~~~~~~~~~~~~~~  6ee587a8		sub v8.2d, v29.2d, v5.2d
+0x~~~~~~~~~~~~~~~~  2eb88782		sub v2.2s, v28.2s, v24.2s
+0x~~~~~~~~~~~~~~~~  2e648558		sub v24.4h, v10.4h, v4.4h
+0x~~~~~~~~~~~~~~~~  6eb1849c		sub v28.4s, v4.4s, v17.4s
+0x~~~~~~~~~~~~~~~~  2e228770		sub v16.8b, v27.8b, v2.8b
+0x~~~~~~~~~~~~~~~~  6e6d8554		sub v20.8h, v10.8h, v13.8h
+0x~~~~~~~~~~~~~~~~  0ead61c5		subhn v5.2s, v14.2d, v13.2d
+0x~~~~~~~~~~~~~~~~  0e6860aa		subhn v10.4h, v5.4s, v8.4s
+0x~~~~~~~~~~~~~~~~  0e366146		subhn v6.8b, v10.8h, v22.8h
+0x~~~~~~~~~~~~~~~~  4e2960cb		subhn2 v11.16b, v6.8h, v9.8h
+0x~~~~~~~~~~~~~~~~  4eb86259		subhn2 v25.4s, v18.2d, v24.2d
+0x~~~~~~~~~~~~~~~~  4e6162b4		subhn2 v20.8h, v21.4s, v1.4s
+0x~~~~~~~~~~~~~~~~  5e203979		suqadd b25, b11
+0x~~~~~~~~~~~~~~~~  5ee0382d		suqadd d13, d1
+0x~~~~~~~~~~~~~~~~  5e603920		suqadd h0, h9
+0x~~~~~~~~~~~~~~~~  5ea03916		suqadd s22, s8
+0x~~~~~~~~~~~~~~~~  4e203b78		suqadd v24.16b, v27.16b
+0x~~~~~~~~~~~~~~~~  4ee039da		suqadd v26.2d, v14.2d
+0x~~~~~~~~~~~~~~~~  0ea03947		suqadd v7.2s, v10.2s
+0x~~~~~~~~~~~~~~~~  0e603999		suqadd v25.4h, v12.4h
+0x~~~~~~~~~~~~~~~~  4ea03864		suqadd v4.4s, v3.4s
+0x~~~~~~~~~~~~~~~~  0e203a4e		suqadd v14.8b, v18.8b
+0x~~~~~~~~~~~~~~~~  4e60391f		suqadd v31.8h, v8.8h
+0x~~~~~~~~~~~~~~~~  0f20a690		sxtl v16.2d, v20.2s
+0x~~~~~~~~~~~~~~~~  0f10a79b		sxtl v27.4s, v28.4h
+0x~~~~~~~~~~~~~~~~  0f08a6c0		sxtl v0.8h, v22.8b
+0x~~~~~~~~~~~~~~~~  4f20a4e6		sxtl2 v6.2d, v7.4s
+0x~~~~~~~~~~~~~~~~  4f10a769		sxtl2 v9.4s, v27.8h
+0x~~~~~~~~~~~~~~~~  4f08a610		sxtl2 v16.8h, v16.16b
+0x~~~~~~~~~~~~~~~~  4e166239		tbl v25.16b, {v17.16b, v18.16b, v19.16b, v20.16b}, v22.16b
+0x~~~~~~~~~~~~~~~~  4e0441bc		tbl v28.16b, {v13.16b, v14.16b, v15.16b}, v4.16b
+0x~~~~~~~~~~~~~~~~  4e022003		tbl v3.16b, {v0.16b, v1.16b}, v2.16b
+0x~~~~~~~~~~~~~~~~  4e0401f4		tbl v20.16b, {v15.16b}, v4.16b
+0x~~~~~~~~~~~~~~~~  0e1462e7		tbl v7.8b, {v23.16b, v24.16b, v25.16b, v26.16b}, v20.8b
+0x~~~~~~~~~~~~~~~~  0e1f4028		tbl v8.8b, {v1.16b, v2.16b, v3.16b}, v31.8b
+0x~~~~~~~~~~~~~~~~  0e102328		tbl v8.8b, {v25.16b, v26.16b}, v16.8b
+0x~~~~~~~~~~~~~~~~  0e1e026b		tbl v11.8b, {v19.16b}, v30.8b
+0x~~~~~~~~~~~~~~~~  4e057339		tbx v25.16b, {v25.16b, v26.16b, v27.16b, v28.16b}, v5.16b
+0x~~~~~~~~~~~~~~~~  4e1853b5		tbx v21.16b, {v29.16b, v30.16b, v31.16b}, v24.16b
+0x~~~~~~~~~~~~~~~~  4e013206		tbx v6.16b, {v16.16b, v17.16b}, v1.16b
+0x~~~~~~~~~~~~~~~~  4e14106d		tbx v13.16b, {v3.16b}, v20.16b
+0x~~~~~~~~~~~~~~~~  0e0973b8		tbx v24.8b, {v29.16b, v30.16b, v31.16b, v0.16b}, v9.8b
+0x~~~~~~~~~~~~~~~~  0e1a5131		tbx v17.8b, {v9.16b, v10.16b, v11.16b}, v26.8b
+0x~~~~~~~~~~~~~~~~  0e153065		tbx v5.8b, {v3.16b, v4.16b}, v21.8b
+0x~~~~~~~~~~~~~~~~  0e1d1170		tbx v16.8b, {v11.16b}, v29.8b
+0x~~~~~~~~~~~~~~~~  4e0c2b13		trn1 v19.16b, v24.16b, v12.16b
+0x~~~~~~~~~~~~~~~~  4eca28e2		trn1 v2.2d, v7.2d, v10.2d
+0x~~~~~~~~~~~~~~~~  0e952816		trn1 v22.2s, v0.2s, v21.2s
+0x~~~~~~~~~~~~~~~~  0e5429ec		trn1 v12.4h, v15.4h, v20.4h
+0x~~~~~~~~~~~~~~~~  4e892a3e		trn1 v30.4s, v17.4s, v9.4s
+0x~~~~~~~~~~~~~~~~  0e1d2a6c		trn1 v12.8b, v19.8b, v29.8b
+0x~~~~~~~~~~~~~~~~  4e492917		trn1 v23.8h, v8.8h, v9.8h
+0x~~~~~~~~~~~~~~~~  4e196bdc		trn2 v28.16b, v30.16b, v25.16b
+0x~~~~~~~~~~~~~~~~  4ec76b67		trn2 v7.2d, v27.2d, v7.2d
+0x~~~~~~~~~~~~~~~~  0e936a1e		trn2 v30.2s, v16.2s, v19.2s
+0x~~~~~~~~~~~~~~~~  0e5968d8		trn2 v24.4h, v6.4h, v25.4h
+0x~~~~~~~~~~~~~~~~  4e8b6a62		trn2 v2.4s, v19.4s, v11.4s
+0x~~~~~~~~~~~~~~~~  0e126b79		trn2 v25.8b, v27.8b, v18.8b
+0x~~~~~~~~~~~~~~~~  4e4f688c		trn2 v12.8h, v4.8h, v15.8h
+0x~~~~~~~~~~~~~~~~  6e3c7d9f		uaba v31.16b, v12.16b, v28.16b
+0x~~~~~~~~~~~~~~~~  2eae7cb2		uaba v18.2s, v5.2s, v14.2s
+0x~~~~~~~~~~~~~~~~  2e757e89		uaba v9.4h, v20.4h, v21.4h
+0x~~~~~~~~~~~~~~~~  6ea27e86		uaba v6.4s, v20.4s, v2.4s
+0x~~~~~~~~~~~~~~~~  2e257d90		uaba v16.8b, v12.8b, v5.8b
+0x~~~~~~~~~~~~~~~~  6e7e7f4f		uaba v15.8h, v26.8h, v30.8h
+0x~~~~~~~~~~~~~~~~  2eaf524a		uabal v10.2d, v18.2s, v15.2s
+0x~~~~~~~~~~~~~~~~  2e67527e		uabal v30.4s, v19.4h, v7.4h
+0x~~~~~~~~~~~~~~~~  2e205364		uabal v4.8h, v27.8b, v0.8b
+0x~~~~~~~~~~~~~~~~  6ea25193		uabal2 v19.2d, v12.4s, v2.4s
+0x~~~~~~~~~~~~~~~~  6e6c50ba		uabal2 v26.4s, v5.8h, v12.8h
+0x~~~~~~~~~~~~~~~~  6e3c5293		uabal2 v19.8h, v20.16b, v28.16b
+0x~~~~~~~~~~~~~~~~  6e357492		uabd v18.16b, v4.16b, v21.16b
+0x~~~~~~~~~~~~~~~~  2eb076be		uabd v30.2s, v21.2s, v16.2s
+0x~~~~~~~~~~~~~~~~  2e797788		uabd v8.4h, v28.4h, v25.4h
+0x~~~~~~~~~~~~~~~~  6eb5759c		uabd v28.4s, v12.4s, v21.4s
+0x~~~~~~~~~~~~~~~~  2e3c7613		uabd v19.8b, v16.8b, v28.8b
+0x~~~~~~~~~~~~~~~~  6e7d7589		uabd v9.8h, v12.8h, v29.8h
+0x~~~~~~~~~~~~~~~~  2ea8701a		uabdl v26.2d, v0.2s, v8.2s
+0x~~~~~~~~~~~~~~~~  2e7973fd		uabdl v29.4s, v31.4h, v25.4h
+0x~~~~~~~~~~~~~~~~  2e2e73bb		uabdl v27.8h, v29.8b, v14.8b
+0x~~~~~~~~~~~~~~~~  6ea87294		uabdl2 v20.2d, v20.4s, v8.4s
+0x~~~~~~~~~~~~~~~~  6e7271f6		uabdl2 v22.4s, v15.8h, v18.8h
+0x~~~~~~~~~~~~~~~~  6e377249		uabdl2 v9.8h, v18.16b, v23.16b
+0x~~~~~~~~~~~~~~~~  2ea069e9		uadalp v9.1d, v15.2s
+0x~~~~~~~~~~~~~~~~  6ea0698e		uadalp v14.2d, v12.4s
+0x~~~~~~~~~~~~~~~~  2e60699c		uadalp v28.2s, v12.4h
+0x~~~~~~~~~~~~~~~~  2e206a20		uadalp v0.4h, v17.8b
+0x~~~~~~~~~~~~~~~~  6e606ba1		uadalp v1.4s, v29.8h
+0x~~~~~~~~~~~~~~~~  6e206acf		uadalp v15.8h, v22.16b
+0x~~~~~~~~~~~~~~~~  2ebb0281		uaddl v1.2d, v20.2s, v27.2s
+0x~~~~~~~~~~~~~~~~  2e65033f		uaddl v31.4s, v25.4h, v5.4h
+0x~~~~~~~~~~~~~~~~  2e23006c		uaddl v12.8h, v3.8b, v3.8b
+0x~~~~~~~~~~~~~~~~  6ea602e5		uaddl2 v5.2d, v23.4s, v6.4s
+0x~~~~~~~~~~~~~~~~  6e7900a1		uaddl2 v1.4s, v5.8h, v25.8h
+0x~~~~~~~~~~~~~~~~  6e3c03d6		uaddl2 v22.8h, v30.16b, v28.16b
+0x~~~~~~~~~~~~~~~~  2ea02927		uaddlp v7.1d, v9.2s
+0x~~~~~~~~~~~~~~~~  6ea0289a		uaddlp v26.2d, v4.4s
+0x~~~~~~~~~~~~~~~~  2e60283c		uaddlp v28.2s, v1.4h
+0x~~~~~~~~~~~~~~~~  2e202bf4		uaddlp v20.4h, v31.8b
+0x~~~~~~~~~~~~~~~~  6e602a30		uaddlp v16.4s, v17.8h
+0x~~~~~~~~~~~~~~~~  6e202846		uaddlp v6.8h, v2.16b
+0x~~~~~~~~~~~~~~~~  6eb03adc		uaddlv d28, v22.4s
+0x~~~~~~~~~~~~~~~~  6e303a60		uaddlv h0, v19.16b
+0x~~~~~~~~~~~~~~~~  2e303bde		uaddlv h30, v30.8b
+0x~~~~~~~~~~~~~~~~  2e703a58		uaddlv s24, v18.4h
+0x~~~~~~~~~~~~~~~~  6e70380a		uaddlv s10, v0.8h
+0x~~~~~~~~~~~~~~~~  2eae1229		uaddw v9.2d, v17.2d, v14.2s
+0x~~~~~~~~~~~~~~~~  2e631329		uaddw v9.4s, v25.4s, v3.4h
+0x~~~~~~~~~~~~~~~~  2e201032		uaddw v18.8h, v1.8h, v0.8b
+0x~~~~~~~~~~~~~~~~  6ea610b2		uaddw2 v18.2d, v5.2d, v6.4s
+0x~~~~~~~~~~~~~~~~  6e6b11f1		uaddw2 v17.4s, v15.4s, v11.8h
+0x~~~~~~~~~~~~~~~~  6e27117d		uaddw2 v29.8h, v11.8h, v7.16b
+0x~~~~~~~~~~~~~~~~  6e23052d		uhadd v13.16b, v9.16b, v3.16b
+0x~~~~~~~~~~~~~~~~  2eb80731		uhadd v17.2s, v25.2s, v24.2s
+0x~~~~~~~~~~~~~~~~  2e6d06f9		uhadd v25.4h, v23.4h, v13.4h
+0x~~~~~~~~~~~~~~~~  6eb00680		uhadd v0.4s, v20.4s, v16.4s
+0x~~~~~~~~~~~~~~~~  2e3904a5		uhadd v5.8b, v5.8b, v25.8b
+0x~~~~~~~~~~~~~~~~  6e7207a3		uhadd v3.8h, v29.8h, v18.8h
+0x~~~~~~~~~~~~~~~~  6e2d26c1		uhsub v1.16b, v22.16b, v13.16b
+0x~~~~~~~~~~~~~~~~  2ebe27ce		uhsub v14.2s, v30.2s, v30.2s
+0x~~~~~~~~~~~~~~~~  2e7125dd		uhsub v29.4h, v14.4h, v17.4h
+0x~~~~~~~~~~~~~~~~  6eb224ba		uhsub v26.4s, v5.4s, v18.4s
+0x~~~~~~~~~~~~~~~~  2e2c24e3		uhsub v3.8b, v7.8b, v12.8b
+0x~~~~~~~~~~~~~~~~  6e6526b9		uhsub v25.8h, v21.8h, v5.8h
+0x~~~~~~~~~~~~~~~~  6e26659c		umax v28.16b, v12.16b, v6.16b
+0x~~~~~~~~~~~~~~~~  2eba6674		umax v20.2s, v19.2s, v26.2s
+0x~~~~~~~~~~~~~~~~  2e7267e0		umax v0.4h, v31.4h, v18.4h
+0x~~~~~~~~~~~~~~~~  6ebc66a6		umax v6.4s, v21.4s, v28.4s
+0x~~~~~~~~~~~~~~~~  2e346440		umax v0.8b, v2.8b, v20.8b
+0x~~~~~~~~~~~~~~~~  6e766564		umax v4.8h, v11.8h, v22.8h
+0x~~~~~~~~~~~~~~~~  6e3da4c1		umaxp v1.16b, v6.16b, v29.16b
+0x~~~~~~~~~~~~~~~~  2ebba633		umaxp v19.2s, v17.2s, v27.2s
+0x~~~~~~~~~~~~~~~~  2e67a615		umaxp v21.4h, v16.4h, v7.4h
+0x~~~~~~~~~~~~~~~~  6ebda689		umaxp v9.4s, v20.4s, v29.4s
+0x~~~~~~~~~~~~~~~~  2e30a42d		umaxp v13.8b, v1.8b, v16.8b
+0x~~~~~~~~~~~~~~~~  6e7aa6f3		umaxp v19.8h, v23.8h, v26.8h
+0x~~~~~~~~~~~~~~~~  6e30abd1		umaxv b17, v30.16b
+0x~~~~~~~~~~~~~~~~  2e30a997		umaxv b23, v12.8b
+0x~~~~~~~~~~~~~~~~  2e70a9ff		umaxv h31, v15.4h
+0x~~~~~~~~~~~~~~~~  6e70ab2f		umaxv h15, v25.8h
+0x~~~~~~~~~~~~~~~~  6eb0aab2		umaxv s18, v21.4s
+0x~~~~~~~~~~~~~~~~  6e326c16		umin v22.16b, v0.16b, v18.16b
+0x~~~~~~~~~~~~~~~~  2eb06ea1		umin v1.2s, v21.2s, v16.2s
+0x~~~~~~~~~~~~~~~~  2e796c91		umin v17.4h, v4.4h, v25.4h
+0x~~~~~~~~~~~~~~~~  6ead6f58		umin v24.4s, v26.4s, v13.4s
+0x~~~~~~~~~~~~~~~~  2e256c34		umin v20.8b, v1.8b, v5.8b
+0x~~~~~~~~~~~~~~~~  6e776f3a		umin v26.8h, v25.8h, v23.8h
+0x~~~~~~~~~~~~~~~~  6e37ac25		uminp v5.16b, v1.16b, v23.16b
+0x~~~~~~~~~~~~~~~~  2ebeaf47		uminp v7.2s, v26.2s, v30.2s
+0x~~~~~~~~~~~~~~~~  2e79aca9		uminp v9.4h, v5.4h, v25.4h
+0x~~~~~~~~~~~~~~~~  6ea1ad57		uminp v23.4s, v10.4s, v1.4s
+0x~~~~~~~~~~~~~~~~  2e2eafa4		uminp v4.8b, v29.8b, v14.8b
+0x~~~~~~~~~~~~~~~~  6e6eac15		uminp v21.8h, v0.8h, v14.8h
+0x~~~~~~~~~~~~~~~~  6e31aa20		uminv b0, v17.16b
+0x~~~~~~~~~~~~~~~~  2e31abe0		uminv b0, v31.8b
+0x~~~~~~~~~~~~~~~~  2e71a818		uminv h24, v0.4h
+0x~~~~~~~~~~~~~~~~  6e71a9dd		uminv h29, v14.8h
+0x~~~~~~~~~~~~~~~~  6eb1a87e		uminv s30, v3.4s
+0x~~~~~~~~~~~~~~~~  2eb8816b		umlal v11.2d, v11.2s, v24.2s
+0x~~~~~~~~~~~~~~~~  2fab2a1e		umlal v30.2d, v16.2s, v11.s[3]
+0x~~~~~~~~~~~~~~~~  2e7a8120		umlal v0.4s, v9.4h, v26.4h
+0x~~~~~~~~~~~~~~~~  2f4c2b14		umlal v20.4s, v24.4h, v12.h[4]
+0x~~~~~~~~~~~~~~~~  2e2682b0		umlal v16.8h, v21.8b, v6.8b
+0x~~~~~~~~~~~~~~~~  6eb78271		umlal2 v17.2d, v19.4s, v23.4s
+0x~~~~~~~~~~~~~~~~  6f8823c5		umlal2 v5.2d, v30.4s, v8.s[0]
+0x~~~~~~~~~~~~~~~~  6e6f8110		umlal2 v16.4s, v8.8h, v15.8h
+0x~~~~~~~~~~~~~~~~  6f512b4f		umlal2 v15.4s, v26.8h, v1.h[5]
+0x~~~~~~~~~~~~~~~~  6e31803e		umlal2 v30.8h, v1.16b, v17.16b
+0x~~~~~~~~~~~~~~~~  2ebca272		umlsl v18.2d, v19.2s, v28.2s
+0x~~~~~~~~~~~~~~~~  2f8860e7		umlsl v7.2d, v7.2s, v8.s[0]
+0x~~~~~~~~~~~~~~~~  2e64a118		umlsl v24.4s, v8.4h, v4.4h
+0x~~~~~~~~~~~~~~~~  2f4c6ad2		umlsl v18.4s, v22.4h, v12.h[4]
+0x~~~~~~~~~~~~~~~~  2e34a1dc		umlsl v28.8h, v14.8b, v20.8b
+0x~~~~~~~~~~~~~~~~  6ea9a00b		umlsl2 v11.2d, v0.4s, v9.4s
+0x~~~~~~~~~~~~~~~~  6f896a1a		umlsl2 v26.2d, v16.4s, v9.s[2]
+0x~~~~~~~~~~~~~~~~  6e69a163		umlsl2 v3.4s, v11.8h, v9.8h
+0x~~~~~~~~~~~~~~~~  6f496b2a		umlsl2 v10.4s, v25.8h, v9.h[4]
+0x~~~~~~~~~~~~~~~~  6e3ca218		umlsl2 v24.8h, v16.16b, v28.16b
+0x~~~~~~~~~~~~~~~~  4e183f3e		mov x30, v25.d[1]
+0x~~~~~~~~~~~~~~~~  2ebdc14c		umull v12.2d, v10.2s, v29.2s
+0x~~~~~~~~~~~~~~~~  2fa5abd6		umull v22.2d, v30.2s, v5.s[3]
+0x~~~~~~~~~~~~~~~~  2e79c007		umull v7.4s, v0.4h, v25.4h
+0x~~~~~~~~~~~~~~~~  2f63a1ab		umull v11.4s, v13.4h, v3.h[2]
+0x~~~~~~~~~~~~~~~~  2e2ac219		umull v25.8h, v16.8b, v10.8b
+0x~~~~~~~~~~~~~~~~  6ebac071		umull2 v17.2d, v3.4s, v26.4s
+0x~~~~~~~~~~~~~~~~  6fa2a97a		umull2 v26.2d, v11.4s, v2.s[3]
+0x~~~~~~~~~~~~~~~~  6e77c22c		umull2 v12.4s, v17.8h, v23.8h
+0x~~~~~~~~~~~~~~~~  6f61a3e4		umull2 v4.4s, v31.8h, v1.h[2]
+0x~~~~~~~~~~~~~~~~  6e31c185		umull2 v5.8h, v12.16b, v17.16b
+0x~~~~~~~~~~~~~~~~  7e3c0c9e		uqadd b30, b4, b28
+0x~~~~~~~~~~~~~~~~  7ef00e9b		uqadd d27, d20, d16
+0x~~~~~~~~~~~~~~~~  7e7c0dc7		uqadd h7, h14, h28
+0x~~~~~~~~~~~~~~~~  7ea40e3c		uqadd s28, s17, s4
+0x~~~~~~~~~~~~~~~~  6e350ed3		uqadd v19.16b, v22.16b, v21.16b
+0x~~~~~~~~~~~~~~~~  6eeb0c90		uqadd v16.2d, v4.2d, v11.2d
+0x~~~~~~~~~~~~~~~~  2ea40dd4		uqadd v20.2s, v14.2s, v4.2s
+0x~~~~~~~~~~~~~~~~  2e700c05		uqadd v5.4h, v0.4h, v16.4h
+0x~~~~~~~~~~~~~~~~  6ea90ff5		uqadd v21.4s, v31.4s, v9.4s
+0x~~~~~~~~~~~~~~~~  2e230f17		uqadd v23.8b, v24.8b, v3.8b
+0x~~~~~~~~~~~~~~~~  6e6b0f71		uqadd v17.8h, v27.8h, v11.8h
+0x~~~~~~~~~~~~~~~~  7e2a5eca		uqrshl b10, b22, b10
+0x~~~~~~~~~~~~~~~~  7eeb5cbd		uqrshl d29, d5, d11
+0x~~~~~~~~~~~~~~~~  7e7e5f1b		uqrshl h27, h24, h30
+0x~~~~~~~~~~~~~~~~  7ea85daa		uqrshl s10, s13, s8
+0x~~~~~~~~~~~~~~~~  6e2e5e49		uqrshl v9.16b, v18.16b, v14.16b
+0x~~~~~~~~~~~~~~~~  6ef15df8		uqrshl v24.2d, v15.2d, v17.2d
+0x~~~~~~~~~~~~~~~~  2ebb5dc4		uqrshl v4.2s, v14.2s, v27.2s
+0x~~~~~~~~~~~~~~~~  2e685caf		uqrshl v15.4h, v5.4h, v8.4h
+0x~~~~~~~~~~~~~~~~  6ea05fb5		uqrshl v21.4s, v29.4s, v0.4s
+0x~~~~~~~~~~~~~~~~  2e295f10		uqrshl v16.8b, v24.8b, v9.8b
+0x~~~~~~~~~~~~~~~~  6e6f5c02		uqrshl v2.8h, v0.8h, v15.8h
+0x~~~~~~~~~~~~~~~~  7f0c9f4b		uqrshrn b11, h26, #4
+0x~~~~~~~~~~~~~~~~  7f1b9fc7		uqrshrn h7, s30, #5
+0x~~~~~~~~~~~~~~~~  7f2b9d0a		uqrshrn s10, d8, #21
+0x~~~~~~~~~~~~~~~~  2f359ccf		uqrshrn v15.2s, v6.2d, #11
+0x~~~~~~~~~~~~~~~~  2f149f45		uqrshrn v5.4h, v26.4s, #12
+0x~~~~~~~~~~~~~~~~  2f0b9f3c		uqrshrn v28.8b, v25.8h, #5
+0x~~~~~~~~~~~~~~~~  6f0e9fd9		uqrshrn2 v25.16b, v30.8h, #2
+0x~~~~~~~~~~~~~~~~  6f209dd5		uqrshrn2 v21.4s, v14.2d, #32
+0x~~~~~~~~~~~~~~~~  6f1e9ced		uqrshrn2 v13.8h, v7.4s, #2
+0x~~~~~~~~~~~~~~~~  7e374c0d		uqshl b13, b0, b23
+0x~~~~~~~~~~~~~~~~  7f0c7629		uqshl b9, b17, #4
+0x~~~~~~~~~~~~~~~~  7ee44cd7		uqshl d23, d6, d4
+0x~~~~~~~~~~~~~~~~  7f6c7568		uqshl d8, d11, #44
+0x~~~~~~~~~~~~~~~~  7e6f4db3		uqshl h19, h13, h15
+0x~~~~~~~~~~~~~~~~  7f167759		uqshl h25, h26, #6
+0x~~~~~~~~~~~~~~~~  7eaa4f04		uqshl s4, s24, s10
+0x~~~~~~~~~~~~~~~~  7f2175d3		uqshl s19, s14, #1
+0x~~~~~~~~~~~~~~~~  6e394fce		uqshl v14.16b, v30.16b, v25.16b
+0x~~~~~~~~~~~~~~~~  6f0d7546		uqshl v6.16b, v10.16b, #5
+0x~~~~~~~~~~~~~~~~  6ee74d12		uqshl v18.2d, v8.2d, v7.2d
+0x~~~~~~~~~~~~~~~~  6f5275d9		uqshl v25.2d, v14.2d, #18
+0x~~~~~~~~~~~~~~~~  2eb74e19		uqshl v25.2s, v16.2s, v23.2s
+0x~~~~~~~~~~~~~~~~  2f3f75ed		uqshl v13.2s, v15.2s, #31
+0x~~~~~~~~~~~~~~~~  2e6f4f1c		uqshl v28.4h, v24.4h, v15.4h
+0x~~~~~~~~~~~~~~~~  2f117624		uqshl v4.4h, v17.4h, #1
+0x~~~~~~~~~~~~~~~~  6eb74fe9		uqshl v9.4s, v31.4s, v23.4s
+0x~~~~~~~~~~~~~~~~  6f3f7792		uqshl v18.4s, v28.4s, #31
+0x~~~~~~~~~~~~~~~~  2e2f4ebf		uqshl v31.8b, v21.8b, v15.8b
+0x~~~~~~~~~~~~~~~~  2f0976a6		uqshl v6.8b, v21.8b, #1
+0x~~~~~~~~~~~~~~~~  6e714c5c		uqshl v28.8h, v2.8h, v17.8h
+0x~~~~~~~~~~~~~~~~  6f1e7518		uqshl v24.8h, v8.8h, #14
+0x~~~~~~~~~~~~~~~~  7f099775		uqshrn b21, h27, #7
+0x~~~~~~~~~~~~~~~~  7f15975c		uqshrn h28, s26, #11
+0x~~~~~~~~~~~~~~~~  7f2f97ed		uqshrn s13, d31, #17
+0x~~~~~~~~~~~~~~~~  2f389615		uqshrn v21.2s, v16.2d, #8
+0x~~~~~~~~~~~~~~~~  2f1e9718		uqshrn v24.4h, v24.4s, #2
+0x~~~~~~~~~~~~~~~~  2f089425		uqshrn v5.8b, v1.8h, #8
+0x~~~~~~~~~~~~~~~~  6f0a97b0		uqshrn2 v16.16b, v29.8h, #6
+0x~~~~~~~~~~~~~~~~  6f3f94c2		uqshrn2 v2.4s, v6.2d, #1
+0x~~~~~~~~~~~~~~~~  6f129550		uqshrn2 v16.8h, v10.4s, #14
+0x~~~~~~~~~~~~~~~~  7e3a2e9c		uqsub b28, b20, b26
+0x~~~~~~~~~~~~~~~~  7eea2ce0		uqsub d0, d7, d10
+0x~~~~~~~~~~~~~~~~  7e672f1a		uqsub h26, h24, h7
+0x~~~~~~~~~~~~~~~~  7eb02ef7		uqsub s23, s23, s16
+0x~~~~~~~~~~~~~~~~  6e382e0e		uqsub v14.16b, v16.16b, v24.16b
+0x~~~~~~~~~~~~~~~~  6ee62e2b		uqsub v11.2d, v17.2d, v6.2d
+0x~~~~~~~~~~~~~~~~  2ea82d4a		uqsub v10.2s, v10.2s, v8.2s
+0x~~~~~~~~~~~~~~~~  2e6c2de9		uqsub v9.4h, v15.4h, v12.4h
+0x~~~~~~~~~~~~~~~~  6ea72e57		uqsub v23.4s, v18.4s, v7.4s
+0x~~~~~~~~~~~~~~~~  2e312e69		uqsub v9.8b, v19.8b, v17.8b
+0x~~~~~~~~~~~~~~~~  6e662c54		uqsub v20.8h, v2.8h, v6.8h
+0x~~~~~~~~~~~~~~~~  7e214a7d		uqxtn b29, h19
+0x~~~~~~~~~~~~~~~~  7e6149a0		uqxtn h0, s13
+0x~~~~~~~~~~~~~~~~  7ea14ada		uqxtn s26, d22
+0x~~~~~~~~~~~~~~~~  2ea14be5		uqxtn v5.2s, v31.2d
+0x~~~~~~~~~~~~~~~~  2e614a7e		uqxtn v30.4h, v19.4s
+0x~~~~~~~~~~~~~~~~  2e21484f		uqxtn v15.8b, v2.8h
+0x~~~~~~~~~~~~~~~~  6e21487d		uqxtn2 v29.16b, v3.8h
+0x~~~~~~~~~~~~~~~~  6ea14a2d		uqxtn2 v13.4s, v17.2d
+0x~~~~~~~~~~~~~~~~  6e61497c		uqxtn2 v28.8h, v11.4s
+0x~~~~~~~~~~~~~~~~  0ea1c9f7		urecpe v23.2s, v15.2s
+0x~~~~~~~~~~~~~~~~  4ea1c8fb		urecpe v27.4s, v7.4s
+0x~~~~~~~~~~~~~~~~  6e3b15e2		urhadd v2.16b, v15.16b, v27.16b
+0x~~~~~~~~~~~~~~~~  2eb2142f		urhadd v15.2s, v1.2s, v18.2s
+0x~~~~~~~~~~~~~~~~  2e7a1491		urhadd v17.4h, v4.4h, v26.4h
+0x~~~~~~~~~~~~~~~~  6eae1762		urhadd v2.4s, v27.4s, v14.4s
+0x~~~~~~~~~~~~~~~~  2e2e1625		urhadd v5.8b, v17.8b, v14.8b
+0x~~~~~~~~~~~~~~~~  6e79145e		urhadd v30.8h, v2.8h, v25.8h
+0x~~~~~~~~~~~~~~~~  7efe5784		urshl d4, d28, d30
+0x~~~~~~~~~~~~~~~~  6e3357ed		urshl v13.16b, v31.16b, v19.16b
+0x~~~~~~~~~~~~~~~~  6ef556ee		urshl v14.2d, v23.2d, v21.2d
+0x~~~~~~~~~~~~~~~~  2ea854ea		urshl v10.2s, v7.2s, v8.2s
+0x~~~~~~~~~~~~~~~~  2e7c56af		urshl v15.4h, v21.4h, v28.4h
+0x~~~~~~~~~~~~~~~~  6eb7551e		urshl v30.4s, v8.4s, v23.4s
+0x~~~~~~~~~~~~~~~~  2e25569f		urshl v31.8b, v20.8b, v5.8b
+0x~~~~~~~~~~~~~~~~  6e7e577e		urshl v30.8h, v27.8h, v30.8h
+0x~~~~~~~~~~~~~~~~  7f4f25a4		urshr d4, d13, #49
+0x~~~~~~~~~~~~~~~~  6f0f2682		urshr v2.16b, v20.16b, #1
+0x~~~~~~~~~~~~~~~~  6f4d256d		urshr v13.2d, v11.2d, #51
+0x~~~~~~~~~~~~~~~~  2f3627f5		urshr v21.2s, v31.2s, #10
+0x~~~~~~~~~~~~~~~~  2f152635		urshr v21.4h, v17.4h, #11
+0x~~~~~~~~~~~~~~~~  6f3f26c4		urshr v4.4s, v22.4s, #1
+0x~~~~~~~~~~~~~~~~  2f092420		urshr v0.8b, v1.8b, #7
+0x~~~~~~~~~~~~~~~~  6f1f268d		urshr v13.8h, v20.8h, #1
+0x~~~~~~~~~~~~~~~~  2ea1ca14		ursqrte v20.2s, v16.2s
+0x~~~~~~~~~~~~~~~~  6ea1c91c		ursqrte v28.4s, v8.4s
+0x~~~~~~~~~~~~~~~~  7f53361b		ursra d27, d16, #45
+0x~~~~~~~~~~~~~~~~  6f0d3632		ursra v18.16b, v17.16b, #3
+0x~~~~~~~~~~~~~~~~  6f46379a		ursra v26.2d, v28.2d, #58
+0x~~~~~~~~~~~~~~~~  2f2136c8		ursra v8.2s, v22.2s, #31
+0x~~~~~~~~~~~~~~~~  2f19349f		ursra v31.4h, v4.4h, #7
+0x~~~~~~~~~~~~~~~~  6f3e35ff		ursra v31.4s, v15.4s, #2
+0x~~~~~~~~~~~~~~~~  2f0b3423		ursra v3.8b, v1.8b, #5
+0x~~~~~~~~~~~~~~~~  6f1335d2		ursra v18.8h, v14.8h, #13
+0x~~~~~~~~~~~~~~~~  7ef0441f		ushl d31, d0, d16
+0x~~~~~~~~~~~~~~~~  6e2244c0		ushl v0.16b, v6.16b, v2.16b
+0x~~~~~~~~~~~~~~~~  6ef24432		ushl v18.2d, v1.2d, v18.2d
+0x~~~~~~~~~~~~~~~~  2ebd44fb		ushl v27.2s, v7.2s, v29.2s
+0x~~~~~~~~~~~~~~~~  2e6d45ce		ushl v14.4h, v14.4h, v13.4h
+0x~~~~~~~~~~~~~~~~  6ea94496		ushl v22.4s, v4.4s, v9.4s
+0x~~~~~~~~~~~~~~~~  2e3b46d7		ushl v23.8b, v22.8b, v27.8b
+0x~~~~~~~~~~~~~~~~  6e684735		ushl v21.8h, v25.8h, v8.8h
+0x~~~~~~~~~~~~~~~~  2f35a40b		ushll v11.2d, v0.2s, #21
+0x~~~~~~~~~~~~~~~~  2f18a622		ushll v2.4s, v17.4h, #8
+0x~~~~~~~~~~~~~~~~  2f09a5cb		ushll v11.8h, v14.8b, #1
+0x~~~~~~~~~~~~~~~~  6f27a7a8		ushll2 v8.2d, v29.4s, #7
+0x~~~~~~~~~~~~~~~~  6f12a53d		ushll2 v29.4s, v9.8h, #2
+0x~~~~~~~~~~~~~~~~  6f0ea705		ushll2 v5.8h, v24.16b, #6
+0x~~~~~~~~~~~~~~~~  7f4b077c		ushr d28, d27, #53
+0x~~~~~~~~~~~~~~~~  6f090521		ushr v1.16b, v9.16b, #7
+0x~~~~~~~~~~~~~~~~  6f550702		ushr v2.2d, v24.2d, #43
+0x~~~~~~~~~~~~~~~~  2f35073e		ushr v30.2s, v25.2s, #11
+0x~~~~~~~~~~~~~~~~  2f14074a		ushr v10.4h, v26.4h, #12
+0x~~~~~~~~~~~~~~~~  6f2204a4		ushr v4.4s, v5.4s, #30
+0x~~~~~~~~~~~~~~~~  2f0f045e		ushr v30.8b, v2.8b, #1
+0x~~~~~~~~~~~~~~~~  6f1e0586		ushr v6.8h, v12.8h, #2
+0x~~~~~~~~~~~~~~~~  7e2038b3		usqadd b19, b5
+0x~~~~~~~~~~~~~~~~  7ee03849		usqadd d9, d2
+0x~~~~~~~~~~~~~~~~  7e603a02		usqadd h2, h16
+0x~~~~~~~~~~~~~~~~  7ea03870		usqadd s16, s3
+0x~~~~~~~~~~~~~~~~  6e203bbf		usqadd v31.16b, v29.16b
+0x~~~~~~~~~~~~~~~~  6ee03948		usqadd v8.2d, v10.2d
+0x~~~~~~~~~~~~~~~~  2ea03932		usqadd v18.2s, v9.2s
+0x~~~~~~~~~~~~~~~~  2e6039d8		usqadd v24.4h, v14.4h
+0x~~~~~~~~~~~~~~~~  6ea03bca		usqadd v10.4s, v30.4s
+0x~~~~~~~~~~~~~~~~  2e203a90		usqadd v16.8b, v20.8b
+0x~~~~~~~~~~~~~~~~  6e603a0c		usqadd v12.8h, v16.8h
+0x~~~~~~~~~~~~~~~~  7f5b177c		usra d28, d27, #37
+0x~~~~~~~~~~~~~~~~  6f0b16c5		usra v5.16b, v22.16b, #5
+0x~~~~~~~~~~~~~~~~  6f5f1662		usra v2.2d, v19.2d, #33
+0x~~~~~~~~~~~~~~~~  2f2b1400		usra v0.2s, v0.2s, #21
+0x~~~~~~~~~~~~~~~~  2f1414c7		usra v7.4h, v6.4h, #12
+0x~~~~~~~~~~~~~~~~  6f371624		usra v4.4s, v17.4s, #9
+0x~~~~~~~~~~~~~~~~  2f091589		usra v9.8b, v12.8b, #7
+0x~~~~~~~~~~~~~~~~  6f121763		usra v3.8h, v27.8h, #14
+0x~~~~~~~~~~~~~~~~  2ebe219d		usubl v29.2d, v12.2s, v30.2s
+0x~~~~~~~~~~~~~~~~  2e66239d		usubl v29.4s, v28.4h, v6.4h
+0x~~~~~~~~~~~~~~~~  2e2e208c		usubl v12.8h, v4.8b, v14.8b
+0x~~~~~~~~~~~~~~~~  6eb12301		usubl2 v1.2d, v24.4s, v17.4s
+0x~~~~~~~~~~~~~~~~  6e632024		usubl2 v4.4s, v1.8h, v3.8h
+0x~~~~~~~~~~~~~~~~  6e272097		usubl2 v23.8h, v4.16b, v7.16b
+0x~~~~~~~~~~~~~~~~  2ebe3289		usubw v9.2d, v20.2d, v30.2s
+0x~~~~~~~~~~~~~~~~  2e773214		usubw v20.4s, v16.4s, v23.4h
+0x~~~~~~~~~~~~~~~~  2e3d3119		usubw v25.8h, v8.8h, v29.8b
+0x~~~~~~~~~~~~~~~~  6ea633b2		usubw2 v18.2d, v29.2d, v6.4s
+0x~~~~~~~~~~~~~~~~  6e7430c6		usubw2 v6.4s, v6.4s, v20.8h
+0x~~~~~~~~~~~~~~~~  6e303092		usubw2 v18.8h, v4.8h, v16.16b
+0x~~~~~~~~~~~~~~~~  2f20a6bb		uxtl v27.2d, v21.2s
+0x~~~~~~~~~~~~~~~~  2f10a7e0		uxtl v0.4s, v31.4h
+0x~~~~~~~~~~~~~~~~  2f08a55b		uxtl v27.8h, v10.8b
+0x~~~~~~~~~~~~~~~~  6f20a606		uxtl2 v6.2d, v16.4s
+0x~~~~~~~~~~~~~~~~  6f10a696		uxtl2 v22.4s, v20.8h
+0x~~~~~~~~~~~~~~~~  6f08a6b4		uxtl2 v20.8h, v21.16b
+0x~~~~~~~~~~~~~~~~  4e11193e		uzp1 v30.16b, v9.16b, v17.16b
+0x~~~~~~~~~~~~~~~~  4edc1b47		uzp1 v7.2d, v26.2d, v28.2d
+0x~~~~~~~~~~~~~~~~  0e961a1a		uzp1 v26.2s, v16.2s, v22.2s
+0x~~~~~~~~~~~~~~~~  0e461a6e		uzp1 v14.4h, v19.4h, v6.4h
+0x~~~~~~~~~~~~~~~~  4e9e1af1		uzp1 v17.4s, v23.4s, v30.4s
+0x~~~~~~~~~~~~~~~~  0e0d1b7c		uzp1 v28.8b, v27.8b, v13.8b
+0x~~~~~~~~~~~~~~~~  4e4c1831		uzp1 v17.8h, v1.8h, v12.8h
+0x~~~~~~~~~~~~~~~~  4e1a5a48		uzp2 v8.16b, v18.16b, v26.16b
+0x~~~~~~~~~~~~~~~~  4ed85ad5		uzp2 v21.2d, v22.2d, v24.2d
+0x~~~~~~~~~~~~~~~~  0e825ab4		uzp2 v20.2s, v21.2s, v2.2s
+0x~~~~~~~~~~~~~~~~  0e465bf0		uzp2 v16.4h, v31.4h, v6.4h
+0x~~~~~~~~~~~~~~~~  4e885979		uzp2 v25.4s, v11.4s, v8.4s
+0x~~~~~~~~~~~~~~~~  0e0d5bff		uzp2 v31.8b, v31.8b, v13.8b
+0x~~~~~~~~~~~~~~~~  4e415a28		uzp2 v8.8h, v17.8h, v1.8h
+0x~~~~~~~~~~~~~~~~  0ea12b51		xtn v17.2s, v26.2d
+0x~~~~~~~~~~~~~~~~  0e612803		xtn v3.4h, v0.4s
+0x~~~~~~~~~~~~~~~~  0e212912		xtn v18.8b, v8.8h
+0x~~~~~~~~~~~~~~~~  4e212800		xtn2 v0.16b, v0.8h
+0x~~~~~~~~~~~~~~~~  4ea1288f		xtn2 v15.4s, v4.2d
+0x~~~~~~~~~~~~~~~~  4e612a5f		xtn2 v31.8h, v18.4s
+0x~~~~~~~~~~~~~~~~  4e063936		zip1 v22.16b, v9.16b, v6.16b
+0x~~~~~~~~~~~~~~~~  4ec23977		zip1 v23.2d, v11.2d, v2.2d
+0x~~~~~~~~~~~~~~~~  0e893a1a		zip1 v26.2s, v16.2s, v9.2s
+0x~~~~~~~~~~~~~~~~  0e473921		zip1 v1.4h, v9.4h, v7.4h
+0x~~~~~~~~~~~~~~~~  4e943bc0		zip1 v0.4s, v30.4s, v20.4s
+0x~~~~~~~~~~~~~~~~  0e0f3a3e		zip1 v30.8b, v17.8b, v15.8b
+0x~~~~~~~~~~~~~~~~  4e423911		zip1 v17.8h, v8.8h, v2.8h
+0x~~~~~~~~~~~~~~~~  4e0b7957		zip2 v23.16b, v10.16b, v11.16b
+0x~~~~~~~~~~~~~~~~  4ece78de		zip2 v30.2d, v6.2d, v14.2d
+0x~~~~~~~~~~~~~~~~  0e957949		zip2 v9.2s, v10.2s, v21.2s
+0x~~~~~~~~~~~~~~~~  0e5d7b08		zip2 v8.4h, v24.4h, v29.4h
+0x~~~~~~~~~~~~~~~~  4e977aa0		zip2 v0.4s, v21.4s, v23.4s
+0x~~~~~~~~~~~~~~~~  0e1e7af9		zip2 v25.8b, v23.8b, v30.8b
+0x~~~~~~~~~~~~~~~~  4e5e7947		zip2 v7.8h, v10.8h, v30.8h
+0x~~~~~~~~~~~~~~~~  6ee8d723		fabd v3.2d, v25.2d, v8.2d
+0x~~~~~~~~~~~~~~~~  2eabd76e		fabd v14.2s, v27.2s, v11.2s
+0x~~~~~~~~~~~~~~~~  6eb2d6c9		fabd v9.4s, v22.4s, v18.4s
+0x~~~~~~~~~~~~~~~~  4ee0fba1		fabs v1.2d, v29.2d
+0x~~~~~~~~~~~~~~~~  0ea0faa6		fabs v6.2s, v21.2s
+0x~~~~~~~~~~~~~~~~  4ea0fb2c		fabs v12.4s, v25.4s
+0x~~~~~~~~~~~~~~~~  6e60ecb2		facge v18.2d, v5.2d, v0.2d
+0x~~~~~~~~~~~~~~~~  2e26ed6f		facge v15.2s, v11.2s, v6.2s
+0x~~~~~~~~~~~~~~~~  6e39ed5e		facge v30.4s, v10.4s, v25.4s
+0x~~~~~~~~~~~~~~~~  6effee1c		facgt v28.2d, v16.2d, v31.2d
+0x~~~~~~~~~~~~~~~~  2ea4ec2f		facgt v15.2s, v1.2s, v4.2s
+0x~~~~~~~~~~~~~~~~  6eaaec76		facgt v22.4s, v3.4s, v10.4s
+0x~~~~~~~~~~~~~~~~  4e78d547		fadd v7.2d, v10.2d, v24.2d
+0x~~~~~~~~~~~~~~~~  0e27d6ea		fadd v10.2s, v23.2s, v7.2s
+0x~~~~~~~~~~~~~~~~  4e2bd6d0		fadd v16.4s, v22.4s, v11.4s
+0x~~~~~~~~~~~~~~~~  7e70db9b		faddp d27, v28.2d
+0x~~~~~~~~~~~~~~~~  7e30daf4		faddp s20, v23.2s
+0x~~~~~~~~~~~~~~~~  6e6bd495		faddp v21.2d, v4.2d, v11.2d
+0x~~~~~~~~~~~~~~~~  2e21d75f		faddp v31.2s, v26.2s, v1.2s
+0x~~~~~~~~~~~~~~~~  6e3cd76d		faddp v13.4s, v27.4s, v28.4s
+0x~~~~~~~~~~~~~~~~  4e74e5b1		fcmeq v17.2d, v13.2d, v20.2d
+0x~~~~~~~~~~~~~~~~  4ee0da18		fcmeq v24.2d, v16.2d, #0.0
+0x~~~~~~~~~~~~~~~~  0e2ae63a		fcmeq v26.2s, v17.2s, v10.2s
+0x~~~~~~~~~~~~~~~~  0ea0d898		fcmeq v24.2s, v4.2s, #0.0
+0x~~~~~~~~~~~~~~~~  4e2ee488		fcmeq v8.4s, v4.4s, v14.4s
+0x~~~~~~~~~~~~~~~~  4ea0db3a		fcmeq v26.4s, v25.4s, #0.0
+0x~~~~~~~~~~~~~~~~  6e60e41b		fcmge v27.2d, v0.2d, v0.2d
+0x~~~~~~~~~~~~~~~~  6ee0cbd6		fcmge v22.2d, v30.2d, #0.0
+0x~~~~~~~~~~~~~~~~  2e39e6a7		fcmge v7.2s, v21.2s, v25.2s
+0x~~~~~~~~~~~~~~~~  2ea0c9ef		fcmge v15.2s, v15.2s, #0.0
+0x~~~~~~~~~~~~~~~~  6e3be49d		fcmge v29.4s, v4.4s, v27.4s
+0x~~~~~~~~~~~~~~~~  6ea0cab6		fcmge v22.4s, v21.4s, #0.0
+0x~~~~~~~~~~~~~~~~  6eefe741		fcmgt v1.2d, v26.2d, v15.2d
+0x~~~~~~~~~~~~~~~~  4ee0caef		fcmgt v15.2d, v23.2d, #0.0
+0x~~~~~~~~~~~~~~~~  2ea6e615		fcmgt v21.2s, v16.2s, v6.2s
+0x~~~~~~~~~~~~~~~~  0ea0c9a1		fcmgt v1.2s, v13.2s, #0.0
+0x~~~~~~~~~~~~~~~~  6eb9e40e		fcmgt v14.4s, v0.4s, v25.4s
+0x~~~~~~~~~~~~~~~~  4ea0c90d		fcmgt v13.4s, v8.4s, #0.0
+0x~~~~~~~~~~~~~~~~  6ee0d8c4		fcmle v4.2d, v6.2d, #0.0
+0x~~~~~~~~~~~~~~~~  2ea0dbf8		fcmle v24.2s, v31.2s, #0.0
+0x~~~~~~~~~~~~~~~~  6ea0dae8		fcmle v8.4s, v23.4s, #0.0
+0x~~~~~~~~~~~~~~~~  4ee0e867		fcmlt v7.2d, v3.2d, #0.0
+0x~~~~~~~~~~~~~~~~  0ea0eaaf		fcmlt v15.2s, v21.2s, #0.0
+0x~~~~~~~~~~~~~~~~  4ea0e841		fcmlt v1.4s, v2.4s, #0.0
+0x~~~~~~~~~~~~~~~~  4e61c906		fcvtas v6.2d, v8.2d
+0x~~~~~~~~~~~~~~~~  0e21c921		fcvtas v1.2s, v9.2s
+0x~~~~~~~~~~~~~~~~  4e21ca68		fcvtas v8.4s, v19.4s
+0x~~~~~~~~~~~~~~~~  6e61cbe5		fcvtau v5.2d, v31.2d
+0x~~~~~~~~~~~~~~~~  2e21cbbc		fcvtau v28.2s, v29.2s
+0x~~~~~~~~~~~~~~~~  6e21cb4b		fcvtau v11.4s, v26.4s
+0x~~~~~~~~~~~~~~~~  0e617b28		fcvtl v8.2d, v25.2s
+0x~~~~~~~~~~~~~~~~  0e2179db		fcvtl v27.4s, v14.4h
+0x~~~~~~~~~~~~~~~~  4e6178c1		fcvtl2 v1.2d, v6.4s
+0x~~~~~~~~~~~~~~~~  4e217938		fcvtl2 v24.4s, v9.8h
+0x~~~~~~~~~~~~~~~~  4e61bb09		fcvtms v9.2d, v24.2d
+0x~~~~~~~~~~~~~~~~  0e21b967		fcvtms v7.2s, v11.2s
+0x~~~~~~~~~~~~~~~~  4e21bab7		fcvtms v23.4s, v21.4s
+0x~~~~~~~~~~~~~~~~  6e61b82d		fcvtmu v13.2d, v1.2d
+0x~~~~~~~~~~~~~~~~  2e21b99a		fcvtmu v26.2s, v12.2s
+0x~~~~~~~~~~~~~~~~  6e21bab5		fcvtmu v21.4s, v21.4s
+0x~~~~~~~~~~~~~~~~  0e61682b		fcvtn v11.2s, v1.2d
+0x~~~~~~~~~~~~~~~~  0e216848		fcvtn v8.4h, v2.4s
+0x~~~~~~~~~~~~~~~~  4e616bb8		fcvtn2 v24.4s, v29.2d
+0x~~~~~~~~~~~~~~~~  4e216944		fcvtn2 v4.8h, v10.4s
+0x~~~~~~~~~~~~~~~~  4e61a959		fcvtns v25.2d, v10.2d
+0x~~~~~~~~~~~~~~~~  0e21a904		fcvtns v4.2s, v8.2s
+0x~~~~~~~~~~~~~~~~  4e21ab7d		fcvtns v29.4s, v27.4s
+0x~~~~~~~~~~~~~~~~  6e61ab72		fcvtnu v18.2d, v27.2d
+0x~~~~~~~~~~~~~~~~  2e21a9cb		fcvtnu v11.2s, v14.2s
+0x~~~~~~~~~~~~~~~~  6e21aabb		fcvtnu v27.4s, v21.4s
+0x~~~~~~~~~~~~~~~~  4ee1a8b7		fcvtps v23.2d, v5.2d
+0x~~~~~~~~~~~~~~~~  0ea1a9f8		fcvtps v24.2s, v15.2s
+0x~~~~~~~~~~~~~~~~  4ea1aa65		fcvtps v5.4s, v19.4s
+0x~~~~~~~~~~~~~~~~  6ee1aaa3		fcvtpu v3.2d, v21.2d
+0x~~~~~~~~~~~~~~~~  2ea1aaa3		fcvtpu v3.2s, v21.2s
+0x~~~~~~~~~~~~~~~~  6ea1a8e0		fcvtpu v0.4s, v7.4s
+0x~~~~~~~~~~~~~~~~  2e61697d		fcvtxn v29.2s, v11.2d
+0x~~~~~~~~~~~~~~~~  6e616b3f		fcvtxn2 v31.4s, v25.2d
+0x~~~~~~~~~~~~~~~~  4ee1ba33		fcvtzs v19.2d, v17.2d
+0x~~~~~~~~~~~~~~~~  4f40ff0c		fcvtzs v12.2d, v24.2d, #64
+0x~~~~~~~~~~~~~~~~  0ea1b849		fcvtzs v9.2s, v2.2s
+0x~~~~~~~~~~~~~~~~  0f23fe85		fcvtzs v5.2s, v20.2s, #29
+0x~~~~~~~~~~~~~~~~  4ea1bb35		fcvtzs v21.4s, v25.4s
+0x~~~~~~~~~~~~~~~~  4f3afc3a		fcvtzs v26.4s, v1.4s, #6
+0x~~~~~~~~~~~~~~~~  6ee1bb2d		fcvtzu v13.2d, v25.2d
+0x~~~~~~~~~~~~~~~~  6f60fdbc		fcvtzu v28.2d, v13.2d, #32
+0x~~~~~~~~~~~~~~~~  2ea1b8da		fcvtzu v26.2s, v6.2s
+0x~~~~~~~~~~~~~~~~  2f31fd49		fcvtzu v9.2s, v10.2s, #15
+0x~~~~~~~~~~~~~~~~  6ea1b8de		fcvtzu v30.4s, v6.4s
+0x~~~~~~~~~~~~~~~~  6f2efed3		fcvtzu v19.4s, v22.4s, #18
+0x~~~~~~~~~~~~~~~~  6e6ffd0f		fdiv v15.2d, v8.2d, v15.2d
+0x~~~~~~~~~~~~~~~~  2e3afd2c		fdiv v12.2s, v9.2s, v26.2s
+0x~~~~~~~~~~~~~~~~  6e33fed3		fdiv v19.4s, v22.4s, v19.4s
+0x~~~~~~~~~~~~~~~~  4e68f4f3		fmax v19.2d, v7.2d, v8.2d
+0x~~~~~~~~~~~~~~~~  0e3df599		fmax v25.2s, v12.2s, v29.2s
+0x~~~~~~~~~~~~~~~~  4e25f5e6		fmax v6.4s, v15.4s, v5.4s
+0x~~~~~~~~~~~~~~~~  4e74c510		fmaxnm v16.2d, v8.2d, v20.2d
+0x~~~~~~~~~~~~~~~~  0e39c74f		fmaxnm v15.2s, v26.2s, v25.2s
+0x~~~~~~~~~~~~~~~~  4e30c5d7		fmaxnm v23.4s, v14.4s, v16.4s
+0x~~~~~~~~~~~~~~~~  7e70ca66		fmaxnmp d6, v19.2d
+0x~~~~~~~~~~~~~~~~  7e30cb5b		fmaxnmp s27, v26.2s
+0x~~~~~~~~~~~~~~~~  6e77c588		fmaxnmp v8.2d, v12.2d, v23.2d
+0x~~~~~~~~~~~~~~~~  2e36c72d		fmaxnmp v13.2s, v25.2s, v22.2s
+0x~~~~~~~~~~~~~~~~  6e31c56f		fmaxnmp v15.4s, v11.4s, v17.4s
+0x~~~~~~~~~~~~~~~~  6e30ca7b		fmaxnmv s27, v19.4s
+0x~~~~~~~~~~~~~~~~  7e70f9d4		fmaxp d20, v14.2d
+0x~~~~~~~~~~~~~~~~  7e30f852		fmaxp s18, v2.2s
+0x~~~~~~~~~~~~~~~~  6e7ff6e9		fmaxp v9.2d, v23.2d, v31.2d
+0x~~~~~~~~~~~~~~~~  2e3ff6c7		fmaxp v7.2s, v22.2s, v31.2s
+0x~~~~~~~~~~~~~~~~  6e3df4f2		fmaxp v18.4s, v7.4s, v29.4s
+0x~~~~~~~~~~~~~~~~  6e30fbbf		fmaxv s31, v29.4s
+0x~~~~~~~~~~~~~~~~  4ee2f4a2		fmin v2.2d, v5.2d, v2.2d
+0x~~~~~~~~~~~~~~~~  0eaaf63f		fmin v31.2s, v17.2s, v10.2s
+0x~~~~~~~~~~~~~~~~  4eb0f48a		fmin v10.4s, v4.4s, v16.4s
+0x~~~~~~~~~~~~~~~~  4ee5c4d5		fminnm v21.2d, v6.2d, v5.2d
+0x~~~~~~~~~~~~~~~~  0eaec656		fminnm v22.2s, v18.2s, v14.2s
+0x~~~~~~~~~~~~~~~~  4ea3c7f9		fminnm v25.4s, v31.4s, v3.4s
+0x~~~~~~~~~~~~~~~~  7ef0c829		fminnmp d9, v1.2d
+0x~~~~~~~~~~~~~~~~  7eb0ca95		fminnmp s21, v20.2s
+0x~~~~~~~~~~~~~~~~  6ef3c6b0		fminnmp v16.2d, v21.2d, v19.2d
+0x~~~~~~~~~~~~~~~~  2eb9c7f0		fminnmp v16.2s, v31.2s, v25.2s
+0x~~~~~~~~~~~~~~~~  6eafc61a		fminnmp v26.4s, v16.4s, v15.4s
+0x~~~~~~~~~~~~~~~~  6eb0c883		fminnmv s3, v4.4s
+0x~~~~~~~~~~~~~~~~  7ef0fb58		fminp d24, v26.2d
+0x~~~~~~~~~~~~~~~~  7eb0fa27		fminp s7, v17.2s
+0x~~~~~~~~~~~~~~~~  6ee3f677		fminp v23.2d, v19.2d, v3.2d
+0x~~~~~~~~~~~~~~~~  2ea9f6bd		fminp v29.2s, v21.2s, v9.2s
+0x~~~~~~~~~~~~~~~~  6eb5f700		fminp v0.4s, v24.4s, v21.4s
+0x~~~~~~~~~~~~~~~~  6eb0f919		fminv s25, v8.4s
+0x~~~~~~~~~~~~~~~~  5fc91817		fmla d23, d0, v9.d[2]
+0x~~~~~~~~~~~~~~~~  5f8711f7		fmla s23, s15, v7.s[0]
+0x~~~~~~~~~~~~~~~~  4e66cd71		fmla v17.2d, v11.2d, v6.2d
+0x~~~~~~~~~~~~~~~~  4fcb13de		fmla v30.2d, v30.2d, v11.d[0]
+0x~~~~~~~~~~~~~~~~  0e26cd93		fmla v19.2s, v12.2s, v6.2s
+0x~~~~~~~~~~~~~~~~  0f891238		fmla v24.2s, v17.2s, v9.s[0]
+0x~~~~~~~~~~~~~~~~  4e2bcd70		fmla v16.4s, v11.4s, v11.4s
+0x~~~~~~~~~~~~~~~~  4f891afb		fmla v27.4s, v23.4s, v9.s[2]
+0x~~~~~~~~~~~~~~~~  5fc653db		fmls d27, d30, v6.d[0]
+0x~~~~~~~~~~~~~~~~  5f825215		fmls s21, s16, v2.s[0]
+0x~~~~~~~~~~~~~~~~  4ef5ce65		fmls v5.2d, v19.2d, v21.2d
+0x~~~~~~~~~~~~~~~~  4fcc53d2		fmls v18.2d, v30.2d, v12.d[0]
+0x~~~~~~~~~~~~~~~~  0ea7ce05		fmls v5.2s, v16.2s, v7.2s
+0x~~~~~~~~~~~~~~~~  0fab5243		fmls v3.2s, v18.2s, v11.s[1]
+0x~~~~~~~~~~~~~~~~  4ebeccbb		fmls v27.4s, v5.4s, v30.4s
+0x~~~~~~~~~~~~~~~~  4fa45a9a		fmls v26.4s, v20.4s, v4.s[3]
+0x~~~~~~~~~~~~~~~~  6f06f6ce		fmov v14.2d, #0xd6 (-0.3438)
+0x~~~~~~~~~~~~~~~~  0f03f5ba		fmov v26.2s, #0x6d (0.9062)
+0x~~~~~~~~~~~~~~~~  4f04f69f		fmov v31.4s, #0x94 (-5.0000)
+0x~~~~~~~~~~~~~~~~  9eaf033c		fmov v28.D[1], x25
+0x~~~~~~~~~~~~~~~~  9eae0052		fmov x18, v2.D[1]
+0x~~~~~~~~~~~~~~~~  5fc1988c		fmul d12, d4, v1.d[2]
+0x~~~~~~~~~~~~~~~~  5faf983e		fmul s30, s1, v15.s[3]
+0x~~~~~~~~~~~~~~~~  6e75dc19		fmul v25.2d, v0.2d, v21.2d
+0x~~~~~~~~~~~~~~~~  4fca9b0a		fmul v10.2d, v24.2d, v10.d[2]
+0x~~~~~~~~~~~~~~~~  2e30df07		fmul v7.2s, v24.2s, v16.2s
+0x~~~~~~~~~~~~~~~~  0f849a01		fmul v1.2s, v16.2s, v4.s[2]
+0x~~~~~~~~~~~~~~~~  6e39df85		fmul v5.4s, v28.4s, v25.4s
+0x~~~~~~~~~~~~~~~~  4f88906b		fmul v11.4s, v3.4s, v8.s[0]
+0x~~~~~~~~~~~~~~~~  7fc3993c		fmulx d28, d9, v3.d[2]
+0x~~~~~~~~~~~~~~~~  7faf92b9		fmulx s25, s21, v15.s[1]
+0x~~~~~~~~~~~~~~~~  4e68df9f		fmulx v31.2d, v28.2d, v8.2d
+0x~~~~~~~~~~~~~~~~  6fc692a3		fmulx v3.2d, v21.2d, v6.d[0]
+0x~~~~~~~~~~~~~~~~  0e20dc29		fmulx v9.2s, v1.2s, v0.2s
+0x~~~~~~~~~~~~~~~~  2f869370		fmulx v16.2s, v27.2s, v6.s[0]
+0x~~~~~~~~~~~~~~~~  4e25dc82		fmulx v2.4s, v4.4s, v5.4s
+0x~~~~~~~~~~~~~~~~  6f8490f2		fmulx v18.4s, v7.4s, v4.s[0]
+0x~~~~~~~~~~~~~~~~  6ee0fb21		fneg v1.2d, v25.2d
+0x~~~~~~~~~~~~~~~~  2ea0fbee		fneg v14.2s, v31.2s
+0x~~~~~~~~~~~~~~~~  6ea0f885		fneg v5.4s, v4.4s
+0x~~~~~~~~~~~~~~~~  4ee1d992		frecpe v18.2d, v12.2d
+0x~~~~~~~~~~~~~~~~  0ea1daca		frecpe v10.2s, v22.2s
+0x~~~~~~~~~~~~~~~~  4ea1d8c5		frecpe v5.4s, v6.4s
+0x~~~~~~~~~~~~~~~~  4e7afcf6		frecps v22.2d, v7.2d, v26.2d
+0x~~~~~~~~~~~~~~~~  0e22ff7f		frecps v31.2s, v27.2s, v2.2s
+0x~~~~~~~~~~~~~~~~  4e3bfcd2		frecps v18.4s, v6.4s, v27.4s
+0x~~~~~~~~~~~~~~~~  6e6189ba		frinta v26.2d, v13.2d
+0x~~~~~~~~~~~~~~~~  2e218b4f		frinta v15.2s, v26.2s
+0x~~~~~~~~~~~~~~~~  6e218a0d		frinta v13.4s, v16.4s
+0x~~~~~~~~~~~~~~~~  6ee19989		frinti v9.2d, v12.2d
+0x~~~~~~~~~~~~~~~~  2ea19a65		frinti v5.2s, v19.2s
+0x~~~~~~~~~~~~~~~~  6ea1996f		frinti v15.4s, v11.4s
+0x~~~~~~~~~~~~~~~~  4e619bb1		frintm v17.2d, v29.2d
+0x~~~~~~~~~~~~~~~~  0e21997e		frintm v30.2s, v11.2s
+0x~~~~~~~~~~~~~~~~  4e219a81		frintm v1.4s, v20.4s
+0x~~~~~~~~~~~~~~~~  4e6188d8		frintn v24.2d, v6.2d
+0x~~~~~~~~~~~~~~~~  0e218a2c		frintn v12.2s, v17.2s
+0x~~~~~~~~~~~~~~~~  4e21897d		frintn v29.4s, v11.4s
+0x~~~~~~~~~~~~~~~~  4ee188ea		frintp v10.2d, v7.2d
+0x~~~~~~~~~~~~~~~~  0ea18a4c		frintp v12.2s, v18.2s
+0x~~~~~~~~~~~~~~~~  4ea18bfa		frintp v26.4s, v31.4s
+0x~~~~~~~~~~~~~~~~  6e6199b8		frintx v24.2d, v13.2d
+0x~~~~~~~~~~~~~~~~  2e219927		frintx v7.2s, v9.2s
+0x~~~~~~~~~~~~~~~~  6e219ab2		frintx v18.4s, v21.4s
+0x~~~~~~~~~~~~~~~~  4ee19b33		frintz v19.2d, v25.2d
+0x~~~~~~~~~~~~~~~~  0ea1990f		frintz v15.2s, v8.2s
+0x~~~~~~~~~~~~~~~~  4ea19874		frintz v20.4s, v3.4s
+0x~~~~~~~~~~~~~~~~  6ee1d8b7		frsqrte v23.2d, v5.2d
+0x~~~~~~~~~~~~~~~~  2ea1d8e9		frsqrte v9.2s, v7.2s
+0x~~~~~~~~~~~~~~~~  6ea1d923		frsqrte v3.4s, v9.4s
+0x~~~~~~~~~~~~~~~~  4eefff99		frsqrts v25.2d, v28.2d, v15.2d
+0x~~~~~~~~~~~~~~~~  0eaaff49		frsqrts v9.2s, v26.2s, v10.2s
+0x~~~~~~~~~~~~~~~~  4eaafc25		frsqrts v5.4s, v1.4s, v10.4s
+0x~~~~~~~~~~~~~~~~  6ee1fa46		fsqrt v6.2d, v18.2d
+0x~~~~~~~~~~~~~~~~  2ea1fa46		fsqrt v6.2s, v18.2s
+0x~~~~~~~~~~~~~~~~  6ea1fbe0		fsqrt v0.4s, v31.4s
+0x~~~~~~~~~~~~~~~~  4effd7df		fsub v31.2d, v30.2d, v31.2d
+0x~~~~~~~~~~~~~~~~  0ea6d50b		fsub v11.2s, v8.2s, v6.2s
+0x~~~~~~~~~~~~~~~~  4ebfd410		fsub v16.4s, v0.4s, v31.4s
+0x~~~~~~~~~~~~~~~~  4e61dbf9		scvtf v25.2d, v31.2d
+0x~~~~~~~~~~~~~~~~  4f53e5aa		scvtf v10.2d, v13.2d, #45
+0x~~~~~~~~~~~~~~~~  0e21d9ea		scvtf v10.2s, v15.2s
+0x~~~~~~~~~~~~~~~~  0f25e492		scvtf v18.2s, v4.2s, #27
+0x~~~~~~~~~~~~~~~~  4e21d8b1		scvtf v17.4s, v5.4s
+0x~~~~~~~~~~~~~~~~  4f28e72b		scvtf v11.4s, v25.4s, #24
+0x~~~~~~~~~~~~~~~~  6e61d869		ucvtf v9.2d, v3.2d
+0x~~~~~~~~~~~~~~~~  6f52e7da		ucvtf v26.2d, v30.2d, #46
+0x~~~~~~~~~~~~~~~~  2e21d88b		ucvtf v11.2s, v4.2s
+0x~~~~~~~~~~~~~~~~  2f27e47d		ucvtf v29.2s, v3.2s, #25
+0x~~~~~~~~~~~~~~~~  6e21daf6		ucvtf v22.4s, v23.4s
+0x~~~~~~~~~~~~~~~~  6f27e532		ucvtf v18.4s, v9.4s, #25
+0x~~~~~~~~~~~~~~~~  d65f03c0		ret
diff --git a/test/test-trace-reference/log-none b/test/test-trace-reference/log-none
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/test/test-trace-reference/log-none
diff --git a/test/test-trace-reference/log-none-colour b/test/test-trace-reference/log-none-colour
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/test/test-trace-reference/log-none-colour
diff --git a/test/test-trace-reference/log-regs b/test/test-trace-reference/log-regs
new file mode 100644
index 0000000..12a56cf
--- /dev/null
+++ b/test/test-trace-reference/log-regs
@@ -0,0 +1,739 @@
+#    x0: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x2: 0x~~~~~~~~~~~~~~~~
+#    x3: 0x0300003000300303
+#    x4: 0x0400004000400404
+#    x5: 0x0500005000500505
+#    x6: 0x0600006000600606
+#    x7: 0x0700007000700707
+#    x8: 0x0800008000800808
+#    x9: 0x0900009000900909
+#   x10: 0x0a0000a000a00a0a
+#   x11: 0x0b0000b000b00b0b
+#   x12: 0x0c0000c000c00c0c
+#   x13: 0x0d0000d000d00d0d
+#   x14: 0x0e0000e000e00e0e
+#   x15: 0x0f0000f000f00f0f
+#   x16: 0x1000010001001010
+#   x17: 0x1100011001101111
+#   x18: 0x1200012001201212
+#   x19: 0x1300013001301313
+#   x20: 0x1400014001401414
+#   x21: 0x1500015001501515
+#   x22: 0x1600016001601616
+#   x23: 0x1700017001701717
+#   x24: 0x1800018001801818
+#   x25: 0x1900019001901919
+#   x26: 0x1a0001a001a01a1a
+#   x27: 0x1b0001b001b01b1b
+#   x28: 0x1c0001c001c01c1c
+#   x29: 0x1d0001d001d01d1d
+#    lr: 0x0000000000000000
+#    sp: 0x~~~~~~~~~~~~~~~~
+#    x3: 0x0000000000900909
+#    x6: 0x0f0000f000f00f0f
+#    x9: 0x0000000001501515
+#   x12: 0x1b0001b001b01b1b
+#   x15: 0x0000000002102121
+#   x18: 0x2700027002702727
+#   x21: 0x0000000002d02d2d
+#   x24: 0x3300033003303333
+#   x27: 0x0000000001c01c1c
+#    x2: 0x~~~~~~~~~~~~~~~~
+#    x5: 0x0000000000700707
+#    x8: 0x0000000000000000
+#   x11: 0x0000000001b01b1b
+#   x13: 0x0700007000700707
+#   x15: 0x0000000000000080
+#   x18: 0x0000013000130013
+#   x21: 0x0000000002d02d2c
+#   x23: 0x1700017001701716
+#   x25: 0x0000000000200202
+#   x28: 0x1d0001d001d01d1d
+#    x3: 0x0000000000000000
+#    x6: 0x0700007000700707
+#   x17: 0x0000000000130014
+#   x17: 0x0000000000130013
+#   x19: 0x1400014001401414
+#   x19: 0x1400014001401415
+#   x21: 0x0000000001601616
+#   x21: 0x00000000fe9fe9e9
+#   x23: 0xccfffccffccfcccc
+#   x23: 0x3300033003303333
+#   x25: 0x0000000000000006
+#   x27: 0x0000000000000002
+#   x29: 0x0000000000000020
+#    x3: 0x0000000000000005
+#   x13: 0x0000000000e00e0e
+#   x13: 0x00000000ff1ff1f2
+#   x15: 0x1000010001001010
+#   x15: 0xeffffefffeffeff0
+#   x17: 0x00000000e963b635
+#   x20: 0x00000000ad83ccb8
+#   x23: 0x000000003ed5525d
+#   x26: 0x00000000bc365145
+#    x4: 0x0000000000000070
+#    x7: 0x00000000b096abf4
+#   x13: 0x0000000000e00e0e
+#   x13: 0x00000000feffeff0
+#   x16: 0x0000013000130013
+#   x16: 0x00000000e963b635
+#   x19: 0x0000000000000000
+#   x19: 0x0000000000000001
+#   x20: 0x0000000000000001
+#   x20: 0x0000000000000000
+#   x21: 0x0000000000000000
+#   x21: 0x00000000ffffffff
+#   x22: 0x0000000000000000
+#   x22: 0xffffffffffffffff
+#   x23: 0x0000000003303333
+#   x23: 0x0000000000000007
+#   x26: 0x1d0001d001d01d1e
+#   x26: 0x0000000000000002
+#   x29: 0x00000000fffffffa
+#   x29: 0x0000000000000000
+#    x4: 0x0000000000700707
+#    x4: 0xf8ffff8fff8ff8f8
+#    x7: 0x00000000feafeaeb
+#    x7: 0x0000000000000000
+#   x10: 0xe4fffe4ffe4fe4e5
+#   x10: 0x0000000001b01b1b
+#   x13: 0x0000000001e01e01
+#   x16: 0xfffffecf168f49d9
+#   x19: 0x00000000ffffffff
+#   x22: 0x3300033003303334
+#   x25: 0x0000000001000000
+#   x28: 0x0000000000000000
+#    x3: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#    x4: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#    x5: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x6: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x7: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#    x8: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#    x9: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#   x10: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
+#   x11: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#   x12: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
+#   x13: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#   x14: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#   x15: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   x16: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   x17: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#   x18: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#   x19: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#   x20: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
+#   x21: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#   x22: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
+#   x23: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#   x24: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
+#   x23: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#   x24: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   x23: 0x0000000013121110 <- 0x~~~~~~~~~~~~~~~~
+#   x24: 0x0000000017161514 <- 0x~~~~~~~~~~~~~~~~
+#   x25: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#   x26: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
+#   x25: 0x1716151413121110 <- 0x~~~~~~~~~~~~~~~~
+#   x26: 0x1f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   x25: 0x3736353433323130 <- 0x~~~~~~~~~~~~~~~~
+#   x26: 0x3f3e3d3c3b3a3938 <- 0x~~~~~~~~~~~~~~~~
+#   x27: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#   x28: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
+#   x27: 0x0000000033323130 <- 0x~~~~~~~~~~~~~~~~
+#   x28: 0x0000000037363534 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   x27: 0x0000000043424140 <- 0x~~~~~~~~~~~~~~~~
+#   x28: 0x0000000047464544 <- 0x~~~~~~~~~~~~~~~~
+#   x29: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#   x29: 0x0000000043424140 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   x29: 0x000000004b4a4948 <- 0x~~~~~~~~~~~~~~~~
+#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
+#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
+#    x3: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x3: 0x0000000000000058 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x3: 0x000000000000005a <- 0x~~~~~~~~~~~~~~~~
+#    x4: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x4: 0x000000000000005a <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x4: 0x000000000000005c <- 0x~~~~~~~~~~~~~~~~
+#    x5: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#    x5: 0x0000000000005d5c <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x5: 0x0000000000006160 <- 0x~~~~~~~~~~~~~~~~
+#    x6: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#    x6: 0x0000000000006160 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x6: 0x0000000000006564 <- 0x~~~~~~~~~~~~~~~~
+#    x7: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x7: 0x0000000000000064 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x7: 0x0000000000000066 <- 0x~~~~~~~~~~~~~~~~
+#    x8: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x8: 0x0000000000000066 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x8: 0x0000000000000068 <- 0x~~~~~~~~~~~~~~~~
+#    x9: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#    x9: 0x0000000000006968 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x9: 0x0000000000006d6c <- 0x~~~~~~~~~~~~~~~~
+#   x10: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#   x10: 0x0000000000006d6c <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   x10: 0x0000000000007170 <- 0x~~~~~~~~~~~~~~~~
+#   x11: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#   x11: 0x0000000073727170 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   x11: 0x000000007b7a7978 <- 0x~~~~~~~~~~~~~~~~
+#   x12: 0x000000000a090807 <- 0x~~~~~~~~~~~~~~~~
+#   x13: 0x161514131211100f <- 0x~~~~~~~~~~~~~~~~
+#   x14: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
+#   x15: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
+#   x16: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
+#   x17: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
+#   x18: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
+#   x19: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
+#   x20: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
+#   x21: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
+#   x22: 0x000000000a090807 <- 0x~~~~~~~~~~~~~~~~
+#   x23: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#   x24: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
+#   x25: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#   x26: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
+#   x27: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#   x28: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#   x29: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
+#    x3: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#    x4: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#    x5: 0x0000000000019590
+#    x7: 0x0000000000000340
+#    x9: 0x0000000070000000
+#   x12: 0x2c2a28262422201e
+#   x15: 0x0000000000000040
+#   x17: 0x0000000000000000
+#   x19: 0x0000000000000080
+#   x22: 0x0000000000302010
+#   x25: 0x00000000371b0900
+#   x29: 0x0000000000000100
+#    x5: 0x00000000feb67b00
+#    x8: 0xffffce5f00000000
+#   x11: 0x000000002422201e
+#   x13: 0x0000000000000001
+#   x15: 0x0000000000000082
+#   x16: 0x0000000000000083
+#   x17: 0x00000000ffffff7b
+#   x18: 0xffffffffffffff7a
+#   x19: 0x0000000000000086
+#   x20: 0x0000000000000087
+#   x22: 0x000000001b0e0500
+#   x26: 0xe3e9eff5fbff0100
+#    x2: 0x~~~~~~~~~~~~~~~~
+#    x5: 0x0000000001498500
+#    x8: 0x000000008fffffff
+#   x10: 0xffffffffdbdddfe1
+#   x12: 0x00000000ffffffff
+#   x14: 0xffffffffffffff7e
+#   x16: 0x0000000000000085
+#   x18: 0xffffffffffffff7a
+#   x20: 0x00000000fffffbfc
+#   x22: 0xfffffffffcfdfeff
+#   x24: 0x00000000c8e4f6ff
+#   x26: 0xfffffffffcfdfeff
+#   x28: 0x00000000fffeffff
+#    x3: 0xfffffffffeb67bff
+#    x6: 0x000000008fffffff
+#    x9: 0xffffffffffffffff
+#   x12: 0x0000000080000000
+#   x14: 0x4100000000000000
+#   x16: 0x000000007bffffff
+#   x18: 0x8600000000000000
+#   x20: 0x0000000000000304
+#   x22: 0x0000000002030001
+#   x24: 0x0000000000091b37
+#   x26: 0x0000000006040200
+#   x29: 0x0000000000020000
+#    x4: 0x0000000071498500
+#    x7: 0x000000008fffffff
+#   x10: 0x00000000a422201d
+#   x13: 0x40ffffffffffff7d
+#   x16: 0x000000000000000c
+#   x18: 0x0000000000000060
+#   x22: 0x0000000000000004
+#   x24: 0xffffffffffffff09
+#   x26: 0x00000000fffffcff
+#   x29: 0x0000000000000000
+#   x12: 0x1080ffffffffffde
+#   x24: 0x0000000000000001
+#   x27: 0x0000000000000001
+#    x2: 0x~~~~~~~~~~~~~~~~
+#    x4: 0x0000000000000001
+#    x6: 0x0000000000000001
+#    x8: 0x0000000000000001
+#   x10: 0x0000000000000001
+#   x12: 0x0000000000000001
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x6: 0x0000000000000001
+#    x9: 0x0000000000000001
+#   x12: 0x0000000000000001
+#   x14: 0x0000000000000001
+#   x16: 0x0000000000000001
+#   x18: 0x0000000000000001
+#   x20: 0x0000000000000001
+#   x22: 0x0000000000000001
+#   x24: 0x00000000371b0c01
+#   x27: 0x00000000fffeffff
+#    x2: 0x~~~~~~~~~~~~~~~~
+#    x5: 0xffffffff70000002
+#    x8: 0x0000000000000001
+#   x10: 0x000000000000001e
+#   x12: 0x00000000ffffff7d
+#   x14: 0x0000000000000082
+#   x16: 0x00000000ffffff7b
+#   x18: 0x0000000000000086
+#   x24: 0x0000000000040000
+#   x26: 0x0000000001fff000
+#   x28: 0x0000000000000000
+#    x2: 0x~~~~~~~~~~~~~~~~
+#    x4: 0x0000000000000000
+#    x6: 0x000000000000003f
+#    x8: 0x0000000000000000
+#   x11: 0x0000000000000000
+#   x22: 0x0000000000000000
+#   x28: 0x0000000000000000
+#    x2: 0x~~~~~~~~~~~~~~~~
+#    x4: 0x0000000000000002
+#    x6: 0x000000000000ffff
+#    x8: 0x0000000000000001
+#   x10: 0x0000000000000000
+#   x18: 0x0000000000000000
+#   x29: 0x0000000000000000
+#    x9: 0x0000000000000000
+#    lr: 0x0000000000000000
+#   x16: 0x0000000000000000
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+#    lr: 0x0000000000000000
+#   x18: 0x0000000000000000
diff --git a/test/test-trace-reference/log-regs-colour b/test/test-trace-reference/log-regs-colour
new file mode 100644
index 0000000..e7f2f80
--- /dev/null
+++ b/test/test-trace-reference/log-regs-colour
@@ -0,0 +1,739 @@
+#    x0: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x2: 0x~~~~~~~~~~~~~~~~
+#    x3: 0x0300003000300303
+#    x4: 0x0400004000400404
+#    x5: 0x0500005000500505
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+#   x11: 0x0b0000b000b00b0b
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+#   x13: 0x0d0000d000d00d0d
+#   x14: 0x0e0000e000e00e0e
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+#   x20: 0x1400014001401414
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+#   x25: 0x1900019001901919
+#   x26: 0x1a0001a001a01a1a
+#   x27: 0x1b0001b001b01b1b
+#   x28: 0x1c0001c001c01c1c
+#   x29: 0x1d0001d001d01d1d
+#    lr: 0x0000000000000000
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+#    x3: 0x0000000000900909
+#    x6: 0x0f0000f000f00f0f
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+#   x12: 0x1b0001b001b01b1b
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+#   x21: 0x0000000002d02d2d
+#   x24: 0x3300033003303333
+#   x27: 0x0000000001c01c1c
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+#    x8: 0x0000000000000000
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+#   x11: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
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+#   x15: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   x16: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
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+#   x23: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#   x24: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
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+#   x28: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
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+#   x29: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
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+#   x29: 0x000000004b4a4948 <- 0x~~~~~~~~~~~~~~~~
+#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
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+#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
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+#    x5: 0x0000000000005d5c <- 0x~~~~~~~~~~~~~~~~
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+#    x5: 0x0000000000006160 <- 0x~~~~~~~~~~~~~~~~
+#    x6: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
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+#    x6: 0x0000000000006564 <- 0x~~~~~~~~~~~~~~~~
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+#    x8: 0x0000000000000068 <- 0x~~~~~~~~~~~~~~~~
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+#    x9: 0x0000000000006d6c <- 0x~~~~~~~~~~~~~~~~
+#   x10: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#   x10: 0x0000000000006d6c <- 0x~~~~~~~~~~~~~~~~
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+#   x11: 0x0000000073727170 <- 0x~~~~~~~~~~~~~~~~
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+#   x11: 0x000000007b7a7978 <- 0x~~~~~~~~~~~~~~~~
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+#   x13: 0x161514131211100f <- 0x~~~~~~~~~~~~~~~~
+#   x14: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
+#   x15: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
+#   x16: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
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+#   x18: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
+#   x19: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
+#   x20: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
+#   x21: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
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+#   x23: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#   x24: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
+#   x25: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#   x26: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
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+#   x28: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#   x29: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
+#    x3: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#    x4: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#    x5: 0x0000000000019590
+#    x7: 0x0000000000000340
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+#    lr: 0x0000000000000000
+#   x18: 0x0000000000000000
diff --git a/test/test-trace-reference/log-state b/test/test-trace-reference/log-state
new file mode 100644
index 0000000..9e29204
--- /dev/null
+++ b/test/test-trace-reference/log-state
@@ -0,0 +1,3278 @@
+#    x0: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x2: 0x~~~~~~~~~~~~~~~~
+#    x3: 0x0300003000300303
+#    x4: 0x0400004000400404
+#    x5: 0x0500005000500505
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+#   x27: 0x1b0001b001b01b1b
+#   x28: 0x1c0001c001c01c1c
+#   x29: 0x1d0001d001d01d1d
+#    lr: 0x0000000000000000
+#    sp: 0x~~~~~~~~~~~~~~~~
+#    v0: 0x00055555005555550000000000000000
+#    v1: 0x3ff0d2c63fcb514c3ff587933f9e0419
+#    v2: 0x4000d2c6404b514c40058793401e0419
+#    v3: 0x401570fb40385373401025ae406d0626
+#    v4: 0x4010d2c640cb514c40158793409e0419
+#    v5: 0x401fbc2d4090d04a401ae97840c5851f
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+#    v8: 0x4020d2c6414b514c40258793411e0419
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+#    x3: 0x0000000000900909
+#    x6: 0x0f0000f000f00f0f
+# NZCV: N:0 Z:0 C:0 V:0
+#    x9: 0x0000000001501515
+# NZCV: N:0 Z:0 C:0 V:0
+#   x12: 0x1b0001b001b01b1b
+#   x15: 0x0000000002102121
+#   x18: 0x2700027002702727
+# NZCV: N:0 Z:0 C:0 V:0
+#   x21: 0x0000000002d02d2d
+# NZCV: N:0 Z:0 C:0 V:0
+#   x24: 0x3300033003303333
+#   x27: 0x0000000001c01c1c
+#    x2: 0x~~~~~~~~~~~~~~~~
+# NZCV: N:0 Z:0 C:0 V:0
+#    x5: 0x0000000000700707
+# NZCV: N:0 Z:1 C:0 V:0
+#    x8: 0x0000000000000000
+#   x11: 0x0000000001b01b1b
+#   x13: 0x0700007000700707
+#   x15: 0x0000000000000080
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+#   x23: 0x1700017001701716
+#   x25: 0x0000000000200202
+#   x28: 0x1d0001d001d01d1d
+# NZCV: N:0 Z:1 C:0 V:0
+#    x3: 0x0000000000000000
+# NZCV: N:0 Z:0 C:0 V:0
+#    x6: 0x0700007000700707
+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:1 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:0 V:1
+# NZCV: N:1 Z:0 C:0 V:0
+# NZCV: N:1 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:1 V:1
+# NZCV: N:1 Z:0 C:0 V:0
+#   x17: 0x0000000000130014
+#   x17: 0x0000000000130013
+#   x19: 0x1400014001401414
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+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:1 Z:0 C:0 V:0
+#   x13: 0x0000000000e00e0e
+#   x13: 0x00000000ff1ff1f2
+#   x15: 0x1000010001001010
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+#    x4: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#    x5: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x6: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
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+#   x10: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
+#   x11: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#   x12: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
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+#   x14: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#   x15: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   x16: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   x17: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#   x18: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
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+#   x20: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
+#   x21: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#   x22: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
+#   x23: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#   x24: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
+#   x23: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#   x24: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
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+#   x25: 0x3736353433323130 <- 0x~~~~~~~~~~~~~~~~
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+#   x27: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#   x28: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
+#   x27: 0x0000000033323130 <- 0x~~~~~~~~~~~~~~~~
+#   x28: 0x0000000037363534 <- 0x~~~~~~~~~~~~~~~~
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+#    x1: 0x~~~~~~~~~~~~~~~~
+#   x27: 0x0000000043424140 <- 0x~~~~~~~~~~~~~~~~
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+#   x29: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#   x29: 0x0000000043424140 <- 0x~~~~~~~~~~~~~~~~
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+#    x1: 0x~~~~~~~~~~~~~~~~
+#   x29: 0x000000004b4a4948 <- 0x~~~~~~~~~~~~~~~~
+#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
+#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
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+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x3: 0x000000000000005a <- 0x~~~~~~~~~~~~~~~~
+#    x4: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
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+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x4: 0x000000000000005c <- 0x~~~~~~~~~~~~~~~~
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+#    x5: 0x0000000000005d5c <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x5: 0x0000000000006160 <- 0x~~~~~~~~~~~~~~~~
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+#    x6: 0x0000000000006160 <- 0x~~~~~~~~~~~~~~~~
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+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x6: 0x0000000000006564 <- 0x~~~~~~~~~~~~~~~~
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+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x9: 0x0000000000006d6c <- 0x~~~~~~~~~~~~~~~~
+#   x10: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#   x10: 0x0000000000006d6c <- 0x~~~~~~~~~~~~~~~~
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+#    x1: 0x~~~~~~~~~~~~~~~~
+#   x10: 0x0000000000007170 <- 0x~~~~~~~~~~~~~~~~
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+#   x11: 0x0000000073727170 <- 0x~~~~~~~~~~~~~~~~
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+#   x11: 0x000000007b7a7978 <- 0x~~~~~~~~~~~~~~~~
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+#   x13: 0x161514131211100f <- 0x~~~~~~~~~~~~~~~~
+#   x14: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
+#   x15: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
+#   x16: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
+#   x17: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
+#   x18: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
+#   x19: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
+#   x20: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
+#   x21: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
+#   x22: 0x000000000a090807 <- 0x~~~~~~~~~~~~~~~~
+#   x23: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#   x24: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
+#   x25: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#   x26: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
+#   x27: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#   x28: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
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+#    x7: 0x0000000000000340
+#    x9: 0x0000000070000000
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+# NZCV: N:0 Z:0 C:0 V:0
+#   x16: 0x0000000000000085
+# NZCV: N:1 Z:0 C:0 V:0
+#   x18: 0xffffffffffffff7a
+#   x20: 0x00000000fffffbfc
+#   x22: 0xfffffffffcfdfeff
+# NZCV: N:1 Z:0 C:0 V:0
+#   x24: 0x00000000c8e4f6ff
+# NZCV: N:1 Z:0 C:0 V:0
+#   x26: 0xfffffffffcfdfeff
+#   x28: 0x00000000fffeffff
+#    x3: 0xfffffffffeb67bff
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+#    x7: 0x000000008fffffff
+# NZCV: N:1 Z:0 C:0 V:1
+#   x10: 0x00000000a422201d
+# NZCV: N:0 Z:0 C:1 V:0
+#   x13: 0x40ffffffffffff7d
+#   x16: 0x000000000000000c
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+#   x22: 0x0000000000000004
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+#   x27: 0x00000000fffeffff
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+#    x2: 0x~~~~~~~~~~~~~~~~
+# NZCV: N:1 Z:0 C:0 V:0
+#    x5: 0xffffffff70000002
+#    x8: 0x0000000000000001
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+#   x12: 0x00000000ffffff7d
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+#   x18: 0x0000000000000086
+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:0 Z:1 C:0 V:0
+#   x24: 0x0000000000040000
+#   x26: 0x0000000001fff000
+#   x28: 0x0000000000000000
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+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:0 Z:1 C:1 V:0
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+# NZCV: N:1 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:0 Z:0 C:1 V:1
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+#   v10: 0x00000000000000000000000000000000 (d10: 0.00000)
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+#   v20: 0x0000000000000000ff0000850002ff01 (d20: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x00000000000000000000000000fffeff (d21: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
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+#    v8: 0xc3c2c1c0bfbebdbcbbbab9b8b7b6b5b4 (-2.70315e+18, -5.65934e-21) <- 0x~~~~~~~~~~~~~~~~
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+#   v27: 0x1f1e1d1c1b1a19181700000000000000 (8.56775e-159, 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x2f2e2d2c2b2a29282726252423222120 (1.98829e-81, 4.28794e-120) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x020100fffefdfcfbfaf9f8f7f6f5f4f3 (5.07812e-299, -2.41385e+284) <- 0x~~~~~~~~~~~~~~~~
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+#   v28: 0x21201f1e1d1c1b1a1918171615141312 (3.94003e-149, 8.65093e-188) <- 0x~~~~~~~~~~~~~~~~
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+#   v19: 0x1f1e1d1c1b1a19181700000000000000 (8.56775e-159, 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
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+#   v18: 0x403f3e3d3c3b3a393837363534333231 (31.2431, 6.82132e-38) <- 0x~~~~~~~~~~~~~~~~
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+#    v6: 0x504f4e4d4c4b4a494847464544434241 (7.24994e+78, 1.58398e+40) <- 0x~~~~~~~~~~~~~~~~
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+#   v30: 0x0000000000000000ff0000850002ff01 (..., -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x00000000000000000000000000fffeff (..., 0.00000, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x00000000000000001700000000000000 (..., 4.13590e-25, 0.00000) <- 0x~~~~~~~~~~~~~~~~
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+#   v24: 0x00000000000000005756555453525150 (..., 2.35662e+14, 9.03307e+11) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x00000000000000005f5e5d5c5b5a5958 (..., 1.60231e+19, 6.14598e+16) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000006766656463626160 (..., 1.08801e+24, 4.17598e+21) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x00000000000000006f6e6d6c6b6a6968 (..., 7.37897e+28, 2.83386e+26) <- 0x~~~~~~~~~~~~~~~~
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+#   v29: 0x0000000000000000666564636261605f (..., 2.70818e+23, 1.03937e+21) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x00000000000000006e6d6c6b6a696867 (..., 1.83698e+28, 7.05432e+25) <- 0x~~~~~~~~~~~~~~~~
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+#   v11: 0x0000000000000000ff0000850002ff01 (..., -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x00000000000000000000000000fffeff (..., 0.00000, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x00000000000000001700000000000000 (..., 4.13590e-25, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0000000000000000767574737271706f (..., 1.24460e+33, 4.78220e+30) <- 0x~~~~~~~~~~~~~~~~
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+#    v0: 0x0000000000000000ff0000850002ff01 (..., -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x00000000000000000000000000fffeff (..., 0.00000, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x00000000000000008d8c8b8a89888786 (..., -8.66176e-31, -3.28683e-33) <- 0x~~~~~~~~~~~~~~~~
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+#    v3: 0x00000000000000008c8b8a8988878685 (..., -2.14997e-31, -8.15664e-34) <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x000000000000000094939291908f8e8d (..., -1.49010e-26, -5.66232e-29) <- 0x~~~~~~~~~~~~~~~~
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+#   v31: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
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+#   v26: 0x0000000000fffeffff0000850002ff01 (0.00000, 2.35095e-38, -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x1f1e1d1c1b1a19181700000000000000 (3.34819e-20, 1.27467e-22, 4.13590e-25, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x2f2e2d2c2b2a29282726252423222120 (1.58413e-10, 6.04532e-13, 2.30573e-15, 8.78905e-18) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x3f3e3d3c3b3a39383736353433323130 (0.743122, 0.00284155, 1.08604e-05, 4.14886e-08) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0xf7f6f5f4f3f2f1f0efeeedecebeae9e8 (-1.00179e+34, -3.84962e+31, -1.47890e+29, -5.67986e+26) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0706050403020100fffefdfcfbfaf9f8 (1.00825e-34, 3.82047e-37, -nan, -2.60629e+36) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x17161514131211100f0e0d0c0b0a0908 (4.84942e-25, 1.84362e-27, 7.00365e-30, 2.65846e-32) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x27262524232221201f1e1d1c1b1a1918 (2.30573e-15, 8.78905e-18, 3.34819e-20, 1.27467e-22) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v4: 0xf6f5f4f3f2f1f0efeeedecebeae9e8e7 (-2.49430e+33, -9.58428e+30, -3.68172e+28, -1.41390e+26) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x06050403020100fffefdfcfbfaf9f8f7 (2.50175e-35, 9.47771e-38, -1.68804e+38, -6.48966e+35) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x161514131211100f0e0d0c0b0a090807 (1.20425e-25, 4.57737e-28, 1.73854e-30, 6.59782e-33) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x262524232221201f1e1d1c1b1a191817 (5.72948e-16, 2.18366e-18, 8.31732e-21, 3.16591e-23) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000fffeffff0000850002ff01 (0.00000, 2.35095e-38, -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x1f1e1d1c1b1a19181700000000000000 (3.34819e-20, 1.27467e-22, 4.13590e-25, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x2f2e2d2c2b2a29282726252423222120 (1.58413e-10, 6.04532e-13, 2.30573e-15, 8.78905e-18) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x363534333231302f2e2d2c2b2a292827 (2.70015e-06, 1.03137e-08, 3.93749e-11, 1.50241e-13) <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x464544434241403f3e3d3c3b3a393837 (12625.1, 48.3127, 0.184800, 0.000706557) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x565554535251504f4e4d4c4b4a494847 (5.86395e+13, 2.24749e+11, 8.61082e+08, 3.29781e+06) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v15: 0x3534333231302f2e2d2c2b2a29282726 (6.71297e-07, 2.56382e-09, 9.78665e-12, 3.73374e-14) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x4544434241403f3e3d3c3b3a39383736 (3140.20, 12.0154, 0.0459549, 0.000175682) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x5554535251504f4e4d4c4b4a49484746 (1.45909e+13, 5.59177e+10, 2.14218e+08, 820340.) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v20: 0x0000000000fffeffff0000850002ff01 (0.00000, 2.35095e-38, -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x1f1e1d1c1b1a19181700000000000000 (3.34819e-20, 1.27467e-22, 4.13590e-25, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x6564636261605f5e5d5c5b5a59585756 (6.74083e+22, 2.58684e+20, 9.92399e+17, 3.80591e+15) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x7574737271706f6e6d6c6b6a69686766 (3.09878e+32, 1.19058e+30, 4.57302e+27, 1.75599e+25) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v11: 0x64636261605f5e5d5c5b5a5958575655 (1.67780e+22, 6.43816e+19, 2.46969e+17, 9.47063e+14) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x74737271706f6e6d6c6b6a6968676665 (7.71514e+31, 2.96402e+29, 1.13840e+27, 4.37102e+24) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v15: 0x0000000000fffeffff0000850002ff01 (0.00000, 2.35095e-38, -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x84838281807f7e7d7c7b7a7978777675 (-3.09178e-36, -1.17085e-38, 5.22300e+36, 2.00766e+34) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v0: 0x838281807f7e7d7c7b7a797877767574 (-7.67045e-37, 3.38275e+38, 1.30054e+36, 4.99878e+33) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v17: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000001700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x00000000000000001f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x00000000000000008b8a898887868584 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x0000000000000000939291908f8e8d8c <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000009b9a999897969594 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0000000000000000a3a2a1a09f9e9d9c <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000008a89888786858483 <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x00000000000000009291908f8e8d8c8b <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x00000000000000009a99989796959493 <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000000000a2a1a09f9e9d9c9b <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000001700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000000000aaa9a8a7a6a5a4a3 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000b2b1b0afaeadacab <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000bab9b8b7b6b5b4b3 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000000000a9a8a7a6a5a4a3a2 <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x0000000000000000b1b0afaeadacabaa <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x0000000000000000b9b8b7b6b5b4b3b2 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v10: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x0000000000000000c1c0bfbebdbcbbba <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000000000c9c8c7c6c5c4c3c2 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000c0bfbebdbcbbbab9 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x0000000000000000c8c7c6c5c4c3c2c1 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v31: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x0000000000000000d0cfcecdcccbcac9 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v28: 0x0000000000000000cfcecdcccbcac9c8 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v5: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x2f2e2d2c2b2a29282726252423222120 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x3f3e3d3c3b3a39383736353433323130 <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0xdfdedddcdbdad9d8d7d6d5d4d3d2d1d0 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0xefeeedecebeae9e8e7e6e5e4e3e2e1e0 <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0xfffefdfcfbfaf9f8f7f6f5f4f3f2f1f0 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x0f0e0d0c0b0a09080706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v10: 0xdedddcdbdad9d8d7d6d5d4d3d2d1d0cf <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0xeeedecebeae9e8e7e6e5e4e3e2e1e0df <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0xfefdfcfbfaf9f8f7f6f5f4f3f2f1f0ef <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x0e0d0c0b0a09080706050403020100ff <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x2f2e2d2c2b2a29282726252423222120 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x1e1d1c1b1a191817161514131211100f <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x2e2d2c2b2a292827262524232221201f <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x3e3d3c3b3a393837363534333231302f <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v17: 0x1d1c1b1a191817161514131211100f0e <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x2d2c2b2a292827262524232221201f1e <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x3d3c3b3a393837363534333231302f2e <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x4d4c4b4a494847464544434241403f3e <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x5d5c5b5a595857565554535251504f4e <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v4: 0x4c4b4a494847464544434241403f3e3d <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x5c5b5a595857565554535251504f4e4d <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v9: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x6c6b6a696867666564636261605f5e5d <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v26: 0x6b6a696867666564636261605f5e5d5c <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v19: 0x3d3c3b3a39383736353433323130012e <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0xfefdfcfbfaf9f8f7f6f5f4f36cf1f0ef <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v27: 0x6c6b6a6b6867666564636261605f5e5d <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v10: 0xff0000850002ff01d6d5d4d3d2d1d0cf (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x737271706f6e6d6c636261605f5e5d5c (1.28953e+248, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v7: 0x7271706f6e6d6c6b2726252423222120 (1.86056e+243, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v19: 0x3d3c3b3aff013736353433323130012e <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0xff0000850002ff01d6d5d4d37473d0cf <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v5: 0x5c5b5a595857737254535251504f4e4d <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v21: 0x4d4c4b4a0002ff014544434241403f3e (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x0e0d0c0b7776757406050403020100ff (..., 4.99878e+33, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v1: 0x0000000076757473e8e7e6e5e4e3e2e1 (..., 1.24460e+33, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v2: 0x01010101010101010101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x77777777777777777777777777777777 <- 0x~~~~~~~~~~~~~~~~
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+#   v22: 0x76767676767676767676767676767676 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v25: 0x0000000000000000ff0000850002ff01 (d25: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000007e7d7c7b7a797877 (d9: 1.97467e+301) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v23: 0x00000000000000007d7c7b7a79787776 (d23: 2.91053e+296) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v19: 0xff0000850002ff01ff0000850002ff01 (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x8584838281807f7e8584838281807f7e (-4.41447e-282, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v30: 0x84838281807f7e7d84838281807f7e7d (-6.40629e-287, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00000000000000000002ff010002ff01 (s24: 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000008887868588878685 (s26: -8.15664e-34) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v28: 0x00000000000000008786858487868584 (s28: -2.02406e-34) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v19: 0x0000000000000000ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x00000000000000008988898889888988 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v21: 0x00000000000000008887888788878887 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v15: 0x0002ff010002ff010002ff010002ff01 (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x8c8b8a898c8b8a898c8b8a898c8b8a89 (..., -2.14997e-31, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v23: 0x8b8a89888b8a89888b8a89888b8a8988 (..., -5.33626e-32, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000000101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x00000000000000008c8c8c8c8c8c8c8c <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000008b8b8b8b8b8b8b8b <- 0x~~~~~~~~~~~~~~~~
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+#   v13: 0xff01ff01ff01ff01ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x8d8c8d8c8d8c8d8c8d8c8d8c8d8c8d8c <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v27: 0x8c8b8c8b8c8b8c8b8c8b8c8b8c8b8c8b <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v21: 0x1e1c1a18000000000000ffff00850201 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x1f1d1b1917000000000000feff0000ff <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0xaba9a7a5a3a19f9d9b99979593918f8d <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0xacaaa8a6a4a2a09e9c9a98969492908e <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v12: 0xaaa8a6a4a2a09e9c9a98969492908e8c <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0xaba9a7a5a3a19f9d9b99979593918f8d <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v14: 0x1700000000000000ff0000850002ff01 (6.68887e-198, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x1f1e1d1c1b1a19180000000000fffeff (8.56775e-159, 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0xc3c2c1c0bfbebdbcb3b2b1b0afaeadac (-2.70315e+18, -1.16334e-59) <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0xcbcac9c8c7c6c5c4bbbab9b8b7b6b5b4 (-1.31369e+57, -5.65934e-21) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v12: 0xc2c1c0bfbebdbcbbb2b1b0afaeadacab (-3.90391e+13, -1.67978e-64) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0xcac9c8c7c6c5c4c3bab9b8b7b6b5b4b3 (-1.92941e+52, -8.31108e-26) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v27: 0x000000000000000000fffeff0002ff01 (..., 2.35095e-38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x000000000000000000000000ff000085 (..., 0.00000, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000000000d6d5d4d3cecdcccb (..., -1.17555e+14, -1.72638e+09) <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000dad9d8d7d2d1d0cf (..., -3.06592e+16, -4.50576e+11) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000000000d5d4d3d2cdcccbca (..., -2.92508e+13, -4.29488e+08) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x0000000000000000d9d8d7d6d1d0cfce (..., -7.62949e+15, -1.12105e+11) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000000000feff0085ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x0000000000000000000000ffff000002 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x0000000000000000e7e6e3e2dfdedbda <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x0000000000000000e9e8e5e4e1e0dddc <- 0x~~~~~~~~~~~~~~~~
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+#    v1: 0x0000000000000000e6e5e2e1dedddad9 <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000000000e8e7e4e3e0dfdcdb <- 0x~~~~~~~~~~~~~~~~
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+#   v20: 0x1b1a19180000000000fffeff0002ff01 (1.27467e-22, 0.00000, 2.35095e-38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x1f1e1d1c1700000000000000ff000085 (3.34819e-20, 4.13590e-25, 0.00000, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x04030201fcfbfaf9f4f3f2f1ecebeae9 (1.53999e-36, -1.04669e+37, -1.54621e+32, -2.28166e+27) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x0807060500fffefdf8f7f6f5f0efeeed (4.06322e-34, 2.35095e-38, -4.02346e+34, -5.94046e+29) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v24: 0x03020100fbfaf9f8f3f2f1f0ebeae9e8 (3.82047e-37, -2.60629e+36, -3.84962e+31, -5.67986e+26) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x07060504fffefdfcf7f6f5f4efeeedec (1.00825e-34, -nan, -1.00179e+34, -1.47890e+29) <- 0x~~~~~~~~~~~~~~~~
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+#   v17: 0x00000000000000000000ffff00850201 <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x0000000000000000000000feff0000ff <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x0000000000000000161412100e0c0a08 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x0000000000000000171513110f0d0b09 <- 0x~~~~~~~~~~~~~~~~
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+#    v7: 0x00000000000000001513110f0d0b0907 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0000000000000000161412100e0c0a08 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v30: 0x1d1c1918000000000000feff0085ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x1f1e1b1a17000000000000ffff000002 <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x3433302f2c2b28272423201f1c1b1817 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x363532312e2d2a29262522211e1d1a19 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v13: 0x33322f2e2b2a272623221f1e1b1a1716 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x353431302d2c2928252421201d1c1918 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v5: 0x363532012e2d2a29262522211e1d1a19 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x1f1e1dff1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x4544434241403f3e363c3b3a39383736 <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000003700ffff00850201 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0706050403020100fffefdfcfb35f9f8 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x1d1c1918000000000000feff0036ff01 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v11: 0xff0000850002ff01f8f7f6f5f0efeeed (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000fffeffd5d4d3d2cdcccbca (8.28892e-317, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000003e3d3c3b3a393837 (d26: 6.80687e-09) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000464544434241403f (d27: 3.36984e+30) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v25: 0x07060504fffefdfc3d3c3b3a39383736 (d25: 1.00298e-13) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000004544434241403f3e (d26: 4.89923e+25) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v18: 0xff01000000000000000000feff0000ff <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00020000000000008b8b8b8b8b8b8b8b <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000474600003700ffff00850201 <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0xff01000049480000000000feff0000ff <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v30: 0x1d1c191800000000000046450036ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x1f1e1b1a1700000000004847ff000002 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0002ff0103020100fffefdfcfb35f9f8 (2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0xff00008500000000000046450036ff01 (-1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x0000000000000000000000004c4b4a49 (s28: 5.32913e+07) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0002ff0103020100fffefdfc504f4e4d (s29: 1.39121e+10) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v6: 0x1f1e1dff1b1a19184b4a494800000000 (..., 1.32570e+07, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000004f4e4d4c0d0b0907 (..., 3.46117e+09, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v26: 0x01010101010101010101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0xffffffffffffffffffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x50505050505050505050505050505050 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x51515151515151515151515151515151 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v5: 0x4f4f4f4f4f4f4f4f4f4f4f4f4f4f4f4f <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x50505050505050505050505050505050 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0000000000000000ff0000850002ff01 (d26: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x00000000000000000000000000fffeff (d27: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x00000000000000005857565554535251 (d14: 3.67814e+117) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x0000000000000000605f5e5d5c5b5a59 (d15: 1.68234e+156) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v23: 0x00000000000000005756555453525150 (d23: 5.37096e+112) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00000000000000005f5e5d5c5b5a5958 (d24: 2.48489e+151) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v11: 0xff0000850002ff01ff0000850002ff01 (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000fffeff0000000000fffeff (8.28892e-317, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x67666564636261606766656463626160 (1.24732e+190, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x6f6e6d6c6b6a69686f6e6d6c6b6a6968 (5.76650e+228, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v15: 0x666564636261605f666564636261605f (1.81795e+185, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x6e6d6c6b6a6968676e6d6c6b6a696867 (8.50866e+223, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000000002ff010002ff01 (s26: 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000ff000085ff000085 (s27: -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x00000000000000007271706f7271706f (s22: 4.78220e+30) <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x00000000000000007675747376757473 (s23: 1.24460e+33) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v2: 0x000000000000000071706f6e71706f6e (s2: 1.19058e+30) <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x00000000000000007574737275747372 (s3: 3.09878e+32) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000000000ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x00000000000000000002000200020002 <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000007776777677767776 <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x00000000000000007978797879787978 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000007675767576757675 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000007877787778777877 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v7: 0x0002ff010002ff010002ff010002ff01 (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0xff000085ff000085ff000085ff000085 (..., -1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x7c7b7a797c7b7a797c7b7a797c7b7a79 (..., 5.22300e+36, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x807f7e7d807f7e7d807f7e7d807f7e7d (..., -1.17085e-38, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v21: 0x7b7a79787b7a79787b7a79787b7a7978 (..., 1.30054e+36, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x7f7e7d7c7f7e7d7c7f7e7d7c7f7e7d7c (..., 3.38275e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000000101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000ffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x00000000000000008080808080808080 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x00000000000000008181818181818181 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v11: 0x00000000000000007f7f7f7f7f7f7f7f <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x00000000000000008080808080808080 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v12: 0xff01ff01ff01ff01ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x00020002000200020002000200020002 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x82818281828182818281828182818281 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x84838483848384838483848384838483 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v25: 0x81808180818081808180818081808180 <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x83828382838283828382838283828382 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v20: 0x2d2a2724211e1b1800000000fe000001 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x2e2b2825221f1c1900000000ffff85ff <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x2f2c292623201d1a1700000000ff0002 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0xb1aeaba8a5a29f9c999693908d8a8784 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0xb2afaca9a6a3a09d9a9794918e8b8885 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0xb3b0adaaa7a4a19e9b9895928f8c8986 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v20: 0xb0adaaa7a4a19e9b9895928f8c898683 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0xb1aeaba8a5a29f9c999693908d8a8784 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0xb2afaca9a6a3a09d9a9794918e8b8885 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v21: 0x1f1e1d1c1b1a1918ff0000850002ff01 (8.56775e-159, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x27262524232221200000000000fffeff (4.28794e-120, 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x2f2e2d2c2b2a29281700000000000000 (1.98829e-81, 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0xd2d1d0cfcecdcccbbab9b8b7b6b5b4b3 (-9.07279e+90, -8.31108e-26) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0xdad9d8d7d6d5d4d3c2c1c0bfbebdbcbb (-4.47908e+129, -3.90391e+13) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0xe2e1e0dfdedddcdbcac9c8c7c6c5c4c3 (-2.10851e+168, -1.92941e+52) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v27: 0xd1d0cfcecdcccbcab9b8b7b6b5b4b3b2 (-1.30639e+86, -1.21867e-30) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0xd9d8d7d6d5d4d3d2c1c0bfbebdbcbbba (-6.56908e+124, -5.62003e+08) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0xe1e0dfdedddcdbdac9c8c7c6c5c4c3c2 (-3.03668e+163, -2.82942e+47) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v7: 0x0000000000000000000000000002ff01 (..., 0.00000, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x000000000000000000000000ff000085 (..., 0.00000, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000001700000000fffeff (..., 4.13590e-25, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x0000000000000000f1f0efeee5e4e3e2 (..., -2.38613e+30, -1.35113e+23) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x0000000000000000f5f4f3f2e9e8e7e6 (..., -6.21029e+32, -3.51957e+25) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x0000000000000000f9f8f7f6edecebea (..., -1.61590e+35, -9.16546e+27) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0000000000000000f0efeeede4e3e2e1 (..., -5.94046e+29, -3.36301e+22) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000f4f3f2f1e8e7e6e5 (..., -1.54621e+32, -8.76101e+24) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x0000000000000000f8f7f6f5ecebeae9 (..., -4.02346e+34, -2.28166e+27) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v27: 0x000000000000000000000000ff00ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x000000000000000000000000feff0002 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x00000000000000001700000000ff0085 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x00000000000000000c0b060500fffaf9 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x00000000000000000e0d08070201fcfb <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x0000000000000000100f0a090403fefd <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000000b0a0504fffef9f8 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00000000000000000d0c07060100fbfa <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000000f0e09080302fdfc <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v2: 0x272625241b1a1918000000000002ff01 (2.30573e-15, 1.27467e-22, 0.00000, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x2b2a29281f1e1d1c00000000ff000085 (6.04532e-13, 3.34819e-20, 0.00000, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x2f2e2d2c232221201700000000fffeff (1.58413e-10, 8.78905e-18, 4.13590e-25, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x373635342b2a29281f1e1d1c13121110 (1.08604e-05, 6.04532e-13, 3.34819e-20, 1.84362e-27) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x3b3a39382f2e2d2c2322212017161514 (0.00284155, 1.58413e-10, 8.78905e-18, 4.84942e-25) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x3f3e3d3c33323130272625241b1a1918 (0.743122, 4.14886e-08, 2.30573e-15, 1.27467e-22) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v11: 0x363534332a2928271e1d1c1b1211100f (2.70015e-06, 1.50241e-13, 8.31732e-21, 4.57737e-28) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x3a3938372e2d2c2b2221201f16151413 (0.000706557, 3.93749e-11, 2.18366e-18, 1.20425e-25) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x3e3d3c3b3231302f262524231a191817 (0.184800, 1.03137e-08, 5.72948e-16, 3.16591e-23) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v29: 0x000000000000000000000000fe000001 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x000000000000000000000000ffff85ff <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x00000000000000001700000000ff0002 <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x000000000000000054514e4b4845423f <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x000000000000000055524f4c49464340 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x00000000000000005653504d4a474441 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v12: 0x000000000000000053504d4a4744413e <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x000000000000000054514e4b4845423f <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x000000000000000055524f4c49464340 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v22: 0x2b2a25241f1e191800000000ff00ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x2d2c272621201b1a00000000feff0002 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x2f2e292823221d1c1700000000ff0085 <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x81807b7a75746f6e696863625d5c5756 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x83827d7c777671706b6a65645f5e5958 <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x85847f7e797873726d6c676661605b5a <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v28: 0x807f7a7974736e6d686762615c5b5655 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x82817c7b7675706f6a6964635e5d5857 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x84837e7d787772716c6b6665605f5a59 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v21: 0x0000000001000000f5f4f3f2e9e8e7e6 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x2b2a2524ff1e191800000000ff00ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x2d2c272602201b1a00000000feff0002 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x4f4f4f4f4f4f854f4f4f4f4f4f4f4f4f <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x82818281828186818281828182818281 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000087000b0a0504fffef9f8 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v23: 0x2d2c272602201b1a00000000feff0084 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x2f2e292823221d1c1700000000ff0085 <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x3b3a39382f2e2d2c2322212017161586 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v16: 0x6e6d6c6b6a696867ff0000850002ff01 (d16: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000474600000000000000fffeff (d17: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0xd2d1d0cfcecdcccb1700000000000000 (d18: 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x84837e7d787772718e8d8c8b8a898887 (d30: -1.41807e-238) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x0000000000000000969594939291908f (d31: -7.04826e-200) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0xc3c2c1c0bfbebdbc9e9d9c9b9a999897 (d0: -3.29099e-161) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v28: 0x8d8c8b8a89888786686762615c5b5655 (-2.09028e-243, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x9594939291908f8e6a6964635e5d5857 (-1.02545e-204, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x9d9c9b9a999897968e8d8c8b8a898887 (-4.85140e-166, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v13: 0x81807b7a75746f6e6968ff015d5c5756 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x83827d7c777671706b6a00025f5e5958 <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x85847f7e797873726d6c008561605b5a <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x9f9e2524ff1e191800000000ff00ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0xa1a0272602201b1a00000000feff0084 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0xa3a2292823221d1c1700000000ff0085 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v14: 0x83827d7c777671709e9d00025f5e5958 <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x85847f7e79787372a09f008561605b5a <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x6e6d6c6b6a696867a2a100850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v22: 0x0002ff01ff1e191800000000ff00ff01 (2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0xff00008502201b1a00000000feff0084 (-1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00fffeff23221d1c1700000000ff0085 (2.35095e-38, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x9d9c9b9aa6a5a4a38e8d8c8b8a898887 (..., -1.14938e-15, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x00000000aaa9a8a7969594939291908f (..., -3.01375e-13, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0xc3c2c1c0aeadacab9e9d9c9b9a999897 (..., -7.89780e-11, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000000000a5a4a3a24744413e (..., -2.85603e-16, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x81807b7a75746f6ea9a8a7a65d5c5756 (..., -7.48978e-14, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x83827d7c77767170adacabaa5f5e5958 (..., -1.96304e-11, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v24: 0x01010101010101010101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0xffffffffffffffffffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x02020202020202020202020202020202 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0xaeaeaeaeaeaeaeaeaeaeaeaeaeaeaeae <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0xafafafafafafafafafafafafafafafaf <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0xb0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v3: 0xadadadadadadadadadadadadadadadad <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0xaeaeaeaeaeaeaeaeaeaeaeaeaeaeaeae <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0xafafafafafafafafafafafafafafafaf <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000ff0000850002ff01 (d4: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x00000000000000000000000000fffeff (d5: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000001700000000000000 (d6: 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x0000000000000000b7b6b5b4b3b2b1b0 (d7: -2.60696e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0000000000000000bfbebdbcbbbab9b8 (d8: -0.120083) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x0000000000000000c7c6c5c4c3c2c1c0 (d9: -6.05398e+37) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v17: 0x0000000000000000b6b5b4b3b2b1b0af (d17: -3.80205e-45) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x0000000000000000bebdbcbbbab9b8b7 (d18: -1.77248e-06) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x0000000000000000c6c5c4c3c2c1c0bf (d19: -8.83040e+32) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v16: 0xff0000850002ff01ff0000850002ff01 (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x0000000000fffeff0000000000fffeff (8.28892e-317, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x17000000000000001700000000000000 (6.68887e-198, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0xcecdcccbcac9c8c7cecdcccbcac9c8c7 (-4.11344e+71, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0xd6d5d4d3d2d1d0cfd6d5d4d3d2d1d0cf (-2.05087e+110, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0xdedddcdbdad9d8d7dedddcdbdad9d8d7 (-9.54613e+148, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v14: 0xcdcccbcac9c8c7c6cdcccbcac9c8c7c6 (-6.06516e+66, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0xd5d4d3d2d1d0cfced5d4d3d2d1d0cfce (-2.98548e+105, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0xdddcdbdad9d8d7d6dddcdbdad9d8d7d6 (-1.40766e+144, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v10: 0x00000000000000000002ff010002ff01 (s10: 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x0000000000000000ff000085ff000085 (s11: -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x000000000000000000fffeff00fffeff (s12: 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x0000000000000000e1e0dfdee1e0dfde (s0: -5.18525e+20) <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x0000000000000000e5e4e3e2e5e4e3e2 (s1: -1.35113e+23) <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000000000e9e8e7e6e9e8e7e6 (s2: -3.51957e+25) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v23: 0x0000000000000000e0dfdedde0dfdedd (s23: -1.29053e+20) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x0000000000000000e4e3e2e1e4e3e2e1 (s24: -3.36301e+22) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x0000000000000000e8e7e6e5e8e7e6e5 (s25: -8.76101e+24) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v22: 0x0000000000000000ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x00000000000000000002000200020002 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00000000000000000085008500850085 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x0000000000000000eae9eae9eae9eae9 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x0000000000000000ecebecebecebeceb <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0000000000000000eeedeeedeeedeeed <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v7: 0x0000000000000000e9e8e9e8e9e8e9e8 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0000000000000000ebeaebeaebeaebea <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x0000000000000000edecedecedecedec <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0002ff010002ff010002ff010002ff01 (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0xff000085ff000085ff000085ff000085 (..., -1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x00fffeff00fffeff00fffeff00fffeff (..., 2.35095e-38, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0xf1f0efeef1f0efeef1f0efeef1f0efee (..., -2.38613e+30, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0xf5f4f3f2f5f4f3f2f5f4f3f2f5f4f3f2 (..., -6.21029e+32, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0xf9f8f7f6f9f8f7f6f9f8f7f6f9f8f7f6 (..., -1.61590e+35, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v30: 0xf0efeeedf0efeeedf0efeeedf0efeeed (..., -5.94046e+29, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0xf4f3f2f1f4f3f2f1f4f3f2f1f4f3f2f1 (..., -1.54621e+32, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0xf8f7f6f5f8f7f6f5f8f7f6f5f8f7f6f5 (..., -4.02346e+34, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v2: 0x00000000000000000101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000ffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x00000000000000000202020202020202 <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x0000000000000000f9f9f9f9f9f9f9f9 <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x0000000000000000fafafafafafafafa <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000000000fbfbfbfbfbfbfbfb <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v28: 0x0000000000000000f8f8f8f8f8f8f8f8 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000000000f9f9f9f9f9f9f9f9 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x0000000000000000fafafafafafafafa <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v6: 0xff01ff01ff01ff01ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00020002000200020002000200020002 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00850085008500850085008500850085 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0xfcfbfcfbfcfbfcfbfcfbfcfbfcfbfcfb <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0xfefdfefdfefdfefdfefdfefdfefdfefd <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x00ff00ff00ff00ff00ff00ff00ff00ff <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v7: 0xfbfafbfafbfafbfafbfafbfafbfafbfa <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0xfdfcfdfcfdfcfdfcfdfcfdfcfdfcfdfc <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0xfffefffefffefffefffefffefffefffe <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v3: 0x3c3834302c2824201c18000000ff8501 <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x3d3935312d2925211d19000000fe00ff <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x3e3a36322e2a26221e1a000000ff0002 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x3f3b37332f2b27231f1b17000000ff00 <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x3c3834302c2824201c1814100c080400 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x3d3935312d2925211d1915110d090501 <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x3e3a36322e2a26221e1a16120e0a0602 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x3f3b37332f2b27231f1b17130f0b0703 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v5: 0x3b37332f2b27231f1b17130f0b0703ff <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x3c3834302c2824201c1814100c080400 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x3d3935312d2925211d1915110d090501 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x3e3a36322e2a26221e1a16120e0a0602 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v18: 0x2726252423222120ff0000850002ff01 (4.28794e-120, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x2f2e2d2c2b2a29280000000000fffeff (1.98829e-81, 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x37363534333231301700000000000000 (9.95833e-43, 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x3f3e3d3c3b3a39381f1e1d1c1b1a1918 (0.000461414, 8.56775e-159) <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x666564636261605f464544434241403f (1.81795e+185, 3.36984e+30) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x6e6d6c6b6a6968674e4d4c4b4a494847 (8.50866e+223, 1.57975e+69) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x767574737271706f565554535251504f (4.22243e+262, 7.82703e+107) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x7e7d7c7b7a7978775e5d5c5b5a595857 (1.97467e+301, 3.66628e+146) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v29: 0x6564636261605f5e4544434241403f3e (2.64379e+180, 4.89923e+25) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x6d6c6b6a696867664d4c4b4a49484746 (1.25402e+219, 2.32790e+64) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x7574737271706f6e5554535251504f4e (6.14144e+257, 1.13810e+103) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x7d7c7b7a797877765d5c5b5a59585756 (2.91053e+296, 5.40301e+141) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000000000000002ff01 (..., 0.00000, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x000000000000000017000000ff000085 (..., 4.13590e-25, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x00000000000000001b1a191800fffeff (..., 1.27467e-22, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x00000000000000001f1e1d1c00000000 (..., 3.34819e-20, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x000000000000000091908f8e81807f7e (..., -2.28077e-28, -4.72027e-38) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x00000000000000009594939285848382 (..., -6.00095e-26, -1.24615e-35) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000009998979689888786 (..., -1.57777e-23, -3.28683e-33) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x00000000000000009d9c9b9a8d8c8b8a (..., -4.14537e-21, -8.66176e-31) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000908f8e8d807f7e7d (..., -5.66232e-29, -1.17085e-38) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x00000000000000009493929184838281 (..., -1.49010e-26, -3.09178e-36) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000009897969588878685 (..., -3.91846e-24, -8.15664e-34) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000009c9b9a998c8b8a89 (..., -1.02970e-21, -2.14997e-31) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v16: 0x000000000000000019180000feffff01 <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000001b1a000000ff0002 <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000001d1c000000000085 <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000001f1e17000000ff00 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x0000000000000000b6b5aeada6a59e9d <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x0000000000000000b8b7b0afa8a7a09f <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x0000000000000000bab9b2b1aaa9a2a1 <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0000000000000000bcbbb4b3acaba4a3 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000000000b5b4adaca5a49d9c <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000b7b6afaea7a69f9e <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000b9b8b1b0a9a8a1a0 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x0000000000000000bbbab3b2abaaa3a2 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v7: 0x3332313023222120000000000002ff01 (4.14886e-08, 8.78905e-18, 0.00000, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x373635342726252417000000ff000085 (1.08604e-05, 2.30573e-15, 4.13590e-25, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x3b3a39382b2a29281b1a191800fffeff (0.00284155, 6.04532e-13, 1.27467e-22, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x3f3e3d3c2f2e2d2c1f1e1d1c00000000 (0.743122, 1.58413e-10, 3.34819e-20, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0xefeeedecdfdedddccfcecdccbfbebdbc (-1.47890e+29, -3.21185e+19, -6.93919e+09, -1.49017) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0xf3f2f1f0e3e2e1e0d3d2d1d0c3c2c1c0 (-3.84962e+31, -8.37048e+21, -1.81093e+12, -389.514) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0xf7f6f5f4e7e6e5e4d7d6d5d4c7c6c5c4 (-1.00179e+34, -2.18077e+24, -4.72428e+14, -101772.) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0xfbfaf9f8ebeae9e8dbdad9d8cbcac9c8 (-2.60629e+36, -5.67986e+26, -1.23202e+17, -2.65799e+07) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v29: 0xeeedecebdedddcdbcecdcccbbebdbcbb (-3.68172e+28, -7.99345e+18, -1.72638e+09, -0.370581) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0xf2f1f0efe2e1e0dfd2d1d0cfc2c1c0bf (-9.58428e+30, -2.08336e+21, -4.50576e+11, -96.8765) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0xf6f5f4f3e6e5e4e3d6d5d4d3c6c5c4c3 (-2.49430e+33, -5.42822e+23, -1.17555e+14, -25314.4) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0xfaf9f8f7eae9e8e7dad9d8d7cac9c8c7 (-6.48966e+35, -1.41390e+26, -3.06592e+16, -6.61207e+06) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v15: 0x00000000000000001c18000000ff8501 <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x00000000000000001d19000000fe00ff <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000001e1a000000ff0002 <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000001f1b17000000ff00 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x000000000000000017130f0b0703fffb <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x00000000000000001814100c080400fc <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x00000000000000001915110d090501fd <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x00000000000000001a16120e0a0602fe <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v5: 0x000000000000000016120e0a0602fefa <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x000000000000000017130f0b0703fffb <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000001814100c080400fc <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00000000000000001915110d090501fd <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v25: 0x393831302928212019180000feffff01 <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x3b3a33322b2a23221b1a000000ff0002 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x3d3c35342d2c25241d1c000000000085 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x3f3e37362f2e27261f1e17000000ff00 <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x53524b4a43423b3a33322b2a23221b1a <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x55544d4c45443d3c35342d2c25241d1c <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x57564f4e47463f3e37362f2e27261f1e <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x59585150494841403938313029282120 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v20: 0x52514a4942413a3932312a2922211a19 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x54534c4b44433c3b34332c2b24231c1b <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x56554e4d46453e3d36352e2d26251e1d <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x5857504f4847403f3837302f2827201f <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v20: 0x52514a4942413a3932312a2901211a19 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x54534c4b44433c3b34332c2bff231c1b <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x56554e4d46453e3d36352e2d02251e1d <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x5857504f4847403f3837302f0027201f <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000000000fbfbfbfb59fbfbfb <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x81807b7a75746f6ea9a8a7a65a5c5756 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0xcdcccbcac9c8c7c6cdcccbca5bc8c7c6 <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x00000000000000001c1800005cff8501 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v27: 0x3d3c35342d2c25241d58000000000085 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x3f3e37362f2e27261f5917000000ff00 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000000000195a110d090501fd <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x00000000000000001a5b120e0a0602fe <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v28: 0xff0000850002ff011f5917000000ff00 (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000fffeff195a110d090501fd (8.28892e-317, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x17000000000000001a5b120e0a0602fe (6.68887e-198, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x1f1e1d1c1b1a1918d6d5d4d3c6c5c4c3 (8.56775e-159, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x636261605f5e5d5c1c1800005cff8501 (5.54935e+170, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x6b6a6968676665641d19000000fe00ff (2.71346e+209, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x737271706f6e6d6c1e1a000000ff0002 (1.28953e+248, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x7b7a7978777675741f1b17000000ff00 (6.29888e+286, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v16: 0x6261605f5e5d5c5b1d19000000fe00ff (8.00514e+165, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x6a696867666564631e1a000000ff0002 (3.98304e+204, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x7271706f6e6d6c6b1f1b17000000ff00 (1.86056e+243, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x7a797877767574731f1e17000000ff00 (9.24687e+281, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v2: 0x5352ff0143423b3a33322b2a23221b1a <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x5554000245443d3c35342d2c25241d1c <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x5756008547463f3e37362f2e27261f1e <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x5958ff00494841403938313029282120 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x5958ff00494841407c7b313029282120 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000007e7d0f0b0703fffb <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x0000000000000000807f100c080400fc <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00000000000000008281110d090501fd <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00007b7a00000000807f100c080400fc <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00007d7c000000008281110d090501fd <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x3b3a7f7e2b2a29281b1a191800fffeff <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x3f3e81802f2e2d2c1f1e1d1c00000000 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000000002ff010703fffb (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00007b7a00000000ff000085080400fc (..., -1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00007d7c0000000000fffeff090501fd (..., 2.35095e-38, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x3b3a7f7e2b2a29280000000000fffeff (..., 0.00000, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x393831308584838219180000feffff01 (..., -1.24615e-35, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x3b3a3332898887861b1a000000ff0002 (..., -3.28683e-33, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x3d3c35348d8c8b8a1d58000000000085 (..., -8.66176e-31, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0xff00008591908f8e1f5917000000ff00 (..., -2.28077e-28, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v8: 0x848382810000000000fffeff090501fd (-3.09178e-36, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x888786852b2a29280000000000fffeff (-8.15664e-34, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x8c8b8a892f2e2d2c1f1e1d1c00000000 (-2.14997e-31, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x908f8e8d00000000fafafafafafafafa (-5.66232e-29, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v14: 0x01010101010101010101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0xffffffffffffffffffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x02020202020202020202020202020202 <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x91919191919191919191919191919191 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x92929292929292929292929292929292 <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x93939393939393939393939393939393 <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x94949494949494949494949494949494 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v9: 0x90909090909090909090909090909090 <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x91919191919191919191919191919191 <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x92929292929292929292929292929292 <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x93939393939393939393939393939393 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0000000000000000ff0000850002ff01 (d8: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000000000000000fffeff (d9: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x00000000000000001700000000000000 (d10: 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x00000000000000001f1e1d1c1b1a1918 (d11: 8.56775e-159) <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x00000000000000009b9a999897969594 (d4: -1.05028e-175) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x0000000000000000a3a2a1a09f9e9d9c (d5: -5.00653e-137) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x0000000000000000abaaa9a8a7a6a5a4 (d6: -2.43801e-98) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x0000000000000000b3b2b1b0afaeadac (d7: -1.16334e-59) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000009a99989796959493 (d26: -1.54211e-180) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000a2a1a09f9e9d9c9b (d27: -7.22772e-142) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x0000000000000000aaa9a8a7a6a5a4a3 (d28: -3.58004e-103) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000000000b2b1b0afaeadacab (d29: -1.67978e-64) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v19: 0xff0000850002ff01ff0000850002ff01 (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x0000000000fffeff0000000000fffeff (8.28892e-317, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x17000000000000001700000000000000 (6.68887e-198, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x1f1e1d1c1b1a19181f1e1d1c1b1a1918 (8.56775e-159, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0xbab9b8b7b6b5b4b3bab9b8b7b6b5b4b3 (-8.31108e-26, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0xc2c1c0bfbebdbcbbc2c1c0bfbebdbcbb (-3.90391e+13, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0xcac9c8c7c6c5c4c3cac9c8c7c6c5c4c3 (-1.92941e+52, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0xd2d1d0cfcecdcccbd2d1d0cfcecdcccb (-9.07279e+90, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v15: 0xb9b8b7b6b5b4b3b2b9b8b7b6b5b4b3b2 (-1.21867e-30, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0xc1c0bfbebdbcbbbac1c0bfbebdbcbbba (-5.62003e+08, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0xc9c8c7c6c5c4c3c2c9c8c7c6c5c4c3c2 (-2.82942e+47, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0xd1d0cfcecdcccbcad1d0cfcecdcccbca (-1.30639e+86, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v31: 0x00000000000000000002ff010002ff01 (s31: 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x0000000000000000ff000085ff000085 (s0: -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x000000000000000000fffeff00fffeff (s1: 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x00000000000000000000000000000000 (s2: 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x0000000000000000d5d4d3d2d5d4d3d2 (s28: -2.92508e+13) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000000000d9d8d7d6d9d8d7d6 (s29: -7.62949e+15) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x0000000000000000dddcdbdadddcdbda (s30: -1.98932e+18) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x0000000000000000e1e0dfdee1e0dfde (s31: -5.18525e+20) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v11: 0x0000000000000000d4d3d2d1d4d3d2d1 (s11: -7.27820e+12) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000000000d8d7d6d5d8d7d6d5 (s12: -1.89854e+15) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x0000000000000000dcdbdad9dcdbdad9 (s13: -4.95069e+17) <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x0000000000000000e0dfdedde0dfdedd (s14: -1.29053e+20) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v19: 0x0000000000000000ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x00000000000000000002000200020002 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x00000000000000000085008500850085 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x0000000000000000ff00ff00ff00ff00 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x0000000000000000e2e1e2e1e2e1e2e1 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x0000000000000000e4e3e4e3e4e3e4e3 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x0000000000000000e6e5e6e5e6e5e6e5 <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x0000000000000000e8e7e8e7e8e7e8e7 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v20: 0x0000000000000000e1e0e1e0e1e0e1e0 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x0000000000000000e3e2e3e2e3e2e3e2 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x0000000000000000e5e4e5e4e5e4e5e4 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x0000000000000000e7e6e7e6e7e6e7e6 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v16: 0x0002ff010002ff010002ff010002ff01 (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0xff000085ff000085ff000085ff000085 (..., -1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00fffeff00fffeff00fffeff00fffeff (..., 2.35095e-38, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000000000000000000000 (..., 0.00000, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0xebeae9e8ebeae9e8ebeae9e8ebeae9e8 (..., -5.67986e+26, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0xefeeedecefeeedecefeeedecefeeedec (..., -1.47890e+29, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0xf3f2f1f0f3f2f1f0f3f2f1f0f3f2f1f0 (..., -3.84962e+31, ...) <- 0x~~~~~~~~~~~~~~~~
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diff --git a/test/test-trace-reference/log-state-colour b/test/test-trace-reference/log-state-colour
new file mode 100644
index 0000000..a962bdb
--- /dev/null
+++ b/test/test-trace-reference/log-state-colour
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+#    v1: 0x3ff0d2c63fcb514c3ff587933f9e0419
+#    v2: 0x4000d2c6404b514c40058793401e0419
+#    v3: 0x401570fb40385373401025ae406d0626
+#    v4: 0x4010d2c640cb514c40158793409e0419
+#    v5: 0x401fbc2d4090d04a401ae97840c5851f
+#    v6: 0x402570fb40b85373402025ae40ed0626
+#    v7: 0x402783f4415f16c34022d6a1410a4396
+#    v8: 0x4020d2c6414b514c40258793411e0419
+#    v9: 0x402d6dd3416491c9402838864131c49c
+#   v10: 0x402fbc2d4110d04a402ae9784145851f
+#   v11: 0x4028cf3e410c10f7402d9a6b415945a2
+#   v12: 0x403570fb41385373403025ae416d0626
+#   v13: 0x40342b7d41d5360140317e2841806354
+#   v14: 0x403783f441df16c34032d6a1418a4396
+#   v15: 0x40317a4f41c1768240342f1a419423d7
+#   v16: 0x4030d2c641cb514c40358793419e0419
+#   v17: 0x4033b55841f2b10e4036e00d41a7e45b
+#   v18: 0x403d6dd341e491c94038388641b1c49c
+#   v19: 0x403cc5aa41eef18b403990ff41bba4de
+#   v20: 0x403fbc2d4190d04a403ae97841c5851f
+#   v21: 0x403914a7419a3034403c41f241cf6561
+#   v22: 0x4038cf3e418c10f7403d9a6b41d945a2
+#   v23: 0x403ba7b141b670b1403ef2e441e325e4
+#   v24: 0x404570fb41b85373404025ae41ed0626
+#   v25: 0x404584be41a3b3324040d1eb41f6e667
+#   v26: 0x40442b7d4255360140417e2842006354
+#   v27: 0x40477f314250062040422a6442055375
+#   v28: 0x404783f4425f16c34042d6a1420a4396
+#   v29: 0x4046d78b425a66e2404382de420f33b7
+#   v30: 0x40417a4f4241768240442f1a421423d7
+#   v31: 0x40418e02424c46ad4044db57421913f8
+#    x3: 0x0000000000900909
+#    x6: 0x0f0000f000f00f0f
+# NZCV: N:0 Z:0 C:0 V:0
+#    x9: 0x0000000001501515
+# NZCV: N:0 Z:0 C:0 V:0
+#   x12: 0x1b0001b001b01b1b
+#   x15: 0x0000000002102121
+#   x18: 0x2700027002702727
+# NZCV: N:0 Z:0 C:0 V:0
+#   x21: 0x0000000002d02d2d
+# NZCV: N:0 Z:0 C:0 V:0
+#   x24: 0x3300033003303333
+#   x27: 0x0000000001c01c1c
+#    x2: 0x~~~~~~~~~~~~~~~~
+# NZCV: N:0 Z:0 C:0 V:0
+#    x5: 0x0000000000700707
+# NZCV: N:0 Z:1 C:0 V:0
+#    x8: 0x0000000000000000
+#   x11: 0x0000000001b01b1b
+#   x13: 0x0700007000700707
+#   x15: 0x0000000000000080
+#   x18: 0x0000013000130013
+#   x21: 0x0000000002d02d2c
+#   x23: 0x1700017001701716
+#   x25: 0x0000000000200202
+#   x28: 0x1d0001d001d01d1d
+# NZCV: N:0 Z:1 C:0 V:0
+#    x3: 0x0000000000000000
+# NZCV: N:0 Z:0 C:0 V:0
+#    x6: 0x0700007000700707
+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:1 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:0 V:1
+# NZCV: N:1 Z:0 C:0 V:0
+# NZCV: N:1 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:1 V:1
+# NZCV: N:1 Z:0 C:0 V:0
+#   x17: 0x0000000000130014
+#   x17: 0x0000000000130013
+#   x19: 0x1400014001401414
+#   x19: 0x1400014001401415
+#   x21: 0x0000000001601616
+#   x21: 0x00000000fe9fe9e9
+#   x23: 0xccfffccffccfcccc
+#   x23: 0x3300033003303333
+#   x25: 0x0000000000000006
+#   x27: 0x0000000000000002
+#   x29: 0x0000000000000020
+#    x3: 0x0000000000000005
+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:1 Z:0 C:0 V:0
+#   x13: 0x0000000000e00e0e
+#   x13: 0x00000000ff1ff1f2
+#   x15: 0x1000010001001010
+#   x15: 0xeffffefffeffeff0
+#   x17: 0x00000000e963b635
+#   x20: 0x00000000ad83ccb8
+#   x23: 0x000000003ed5525d
+#   x26: 0x00000000bc365145
+#    x4: 0x0000000000000070
+#    x7: 0x00000000b096abf4
+#   x13: 0x0000000000e00e0e
+#   x13: 0x00000000feffeff0
+#   x16: 0x0000013000130013
+#   x16: 0x00000000e963b635
+#   x19: 0x0000000000000000
+#   x19: 0x0000000000000001
+#   x20: 0x0000000000000001
+#   x20: 0x0000000000000000
+#   x21: 0x0000000000000000
+#   x21: 0x00000000ffffffff
+#   x22: 0x0000000000000000
+#   x22: 0xffffffffffffffff
+#   x23: 0x0000000003303333
+#   x23: 0x0000000000000007
+#   x26: 0x1d0001d001d01d1e
+#   x26: 0x0000000000000002
+#   x29: 0x00000000fffffffa
+#   x29: 0x0000000000000000
+#    x4: 0x0000000000700707
+#    x4: 0xf8ffff8fff8ff8f8
+#    x7: 0x00000000feafeaeb
+#    x7: 0x0000000000000000
+#   x10: 0xe4fffe4ffe4fe4e5
+#   x10: 0x0000000001b01b1b
+#   x13: 0x0000000001e01e01
+#   x16: 0xfffffecf168f49d9
+#   x19: 0x00000000ffffffff
+#   x22: 0x3300033003303334
+#   x25: 0x0000000001000000
+#   x28: 0x0000000000000000
+#    x3: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#    x4: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#    x5: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x6: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x7: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#    x8: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#    x9: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#   x10: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
+#   x11: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#   x12: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
+#   x13: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#   x14: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#   x15: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   x16: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   x17: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#   x18: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#   x19: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#   x20: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
+#   x21: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#   x22: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
+#   x23: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#   x24: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
+#   x23: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#   x24: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   x23: 0x0000000013121110 <- 0x~~~~~~~~~~~~~~~~
+#   x24: 0x0000000017161514 <- 0x~~~~~~~~~~~~~~~~
+#   x25: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#   x26: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
+#   x25: 0x1716151413121110 <- 0x~~~~~~~~~~~~~~~~
+#   x26: 0x1f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   x25: 0x3736353433323130 <- 0x~~~~~~~~~~~~~~~~
+#   x26: 0x3f3e3d3c3b3a3938 <- 0x~~~~~~~~~~~~~~~~
+#   x27: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#   x28: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
+#   x27: 0x0000000033323130 <- 0x~~~~~~~~~~~~~~~~
+#   x28: 0x0000000037363534 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   x27: 0x0000000043424140 <- 0x~~~~~~~~~~~~~~~~
+#   x28: 0x0000000047464544 <- 0x~~~~~~~~~~~~~~~~
+#   x29: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#   x29: 0x0000000043424140 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   x29: 0x000000004b4a4948 <- 0x~~~~~~~~~~~~~~~~
+#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
+#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
+#    x3: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x3: 0x0000000000000058 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x3: 0x000000000000005a <- 0x~~~~~~~~~~~~~~~~
+#    x4: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x4: 0x000000000000005a <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x4: 0x000000000000005c <- 0x~~~~~~~~~~~~~~~~
+#    x5: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#    x5: 0x0000000000005d5c <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x5: 0x0000000000006160 <- 0x~~~~~~~~~~~~~~~~
+#    x6: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#    x6: 0x0000000000006160 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x6: 0x0000000000006564 <- 0x~~~~~~~~~~~~~~~~
+#    x7: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x7: 0x0000000000000064 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x7: 0x0000000000000066 <- 0x~~~~~~~~~~~~~~~~
+#    x8: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x8: 0x0000000000000066 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x8: 0x0000000000000068 <- 0x~~~~~~~~~~~~~~~~
+#    x9: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#    x9: 0x0000000000006968 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x9: 0x0000000000006d6c <- 0x~~~~~~~~~~~~~~~~
+#   x10: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#   x10: 0x0000000000006d6c <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   x10: 0x0000000000007170 <- 0x~~~~~~~~~~~~~~~~
+#   x11: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#   x11: 0x0000000073727170 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   x11: 0x000000007b7a7978 <- 0x~~~~~~~~~~~~~~~~
+#   x12: 0x000000000a090807 <- 0x~~~~~~~~~~~~~~~~
+#   x13: 0x161514131211100f <- 0x~~~~~~~~~~~~~~~~
+#   x14: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
+#   x15: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
+#   x16: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
+#   x17: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
+#   x18: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
+#   x19: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
+#   x20: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
+#   x21: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
+#   x22: 0x000000000a090807 <- 0x~~~~~~~~~~~~~~~~
+#   x23: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#   x24: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
+#   x25: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#   x26: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
+#   x27: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#   x28: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#   x29: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
+#    x3: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#    x4: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#    x5: 0x0000000000019590
+#    x7: 0x0000000000000340
+#    x9: 0x0000000070000000
+#   x12: 0x2c2a28262422201e
+#   x15: 0x0000000000000040
+#   x17: 0x0000000000000000
+#   x19: 0x0000000000000080
+#   x22: 0x0000000000302010
+#   x25: 0x00000000371b0900
+#   x29: 0x0000000000000100
+#    x5: 0x00000000feb67b00
+#    x8: 0xffffce5f00000000
+#   x11: 0x000000002422201e
+#   x13: 0x0000000000000001
+#   x15: 0x0000000000000082
+#   x16: 0x0000000000000083
+#   x17: 0x00000000ffffff7b
+#   x18: 0xffffffffffffff7a
+#   x19: 0x0000000000000086
+#   x20: 0x0000000000000087
+#   x22: 0x000000001b0e0500
+#   x26: 0xe3e9eff5fbff0100
+#    x2: 0x~~~~~~~~~~~~~~~~
+#    x5: 0x0000000001498500
+#    x8: 0x000000008fffffff
+#   x10: 0xffffffffdbdddfe1
+#   x12: 0x00000000ffffffff
+#   x14: 0xffffffffffffff7e
+# NZCV: N:0 Z:0 C:0 V:0
+#   x16: 0x0000000000000085
+# NZCV: N:1 Z:0 C:0 V:0
+#   x18: 0xffffffffffffff7a
+#   x20: 0x00000000fffffbfc
+#   x22: 0xfffffffffcfdfeff
+# NZCV: N:1 Z:0 C:0 V:0
+#   x24: 0x00000000c8e4f6ff
+# NZCV: N:1 Z:0 C:0 V:0
+#   x26: 0xfffffffffcfdfeff
+#   x28: 0x00000000fffeffff
+#    x3: 0xfffffffffeb67bff
+#    x6: 0x000000008fffffff
+#    x9: 0xffffffffffffffff
+#   x12: 0x0000000080000000
+#   x14: 0x4100000000000000
+#   x16: 0x000000007bffffff
+#   x18: 0x8600000000000000
+#   x20: 0x0000000000000304
+#   x22: 0x0000000002030001
+#   x24: 0x0000000000091b37
+#   x26: 0x0000000006040200
+#   x29: 0x0000000000020000
+#    x4: 0x0000000071498500
+#    x7: 0x000000008fffffff
+# NZCV: N:1 Z:0 C:0 V:1
+#   x10: 0x00000000a422201d
+# NZCV: N:0 Z:0 C:1 V:0
+#   x13: 0x40ffffffffffff7d
+#   x16: 0x000000000000000c
+#   x18: 0x0000000000000060
+#   x22: 0x0000000000000004
+#   x24: 0xffffffffffffff09
+#   x26: 0x00000000fffffcff
+#   x29: 0x0000000000000000
+#   x12: 0x1080ffffffffffde
+#   x24: 0x0000000000000001
+#   x27: 0x0000000000000001
+#    x2: 0x~~~~~~~~~~~~~~~~
+#    x4: 0x0000000000000001
+#    x6: 0x0000000000000001
+#    x8: 0x0000000000000001
+#   x10: 0x0000000000000001
+#   x12: 0x0000000000000001
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    x6: 0x0000000000000001
+#    x9: 0x0000000000000001
+#   x12: 0x0000000000000001
+#   x14: 0x0000000000000001
+#   x16: 0x0000000000000001
+#   x18: 0x0000000000000001
+#   x20: 0x0000000000000001
+#   x22: 0x0000000000000001
+#   x24: 0x00000000371b0c01
+#   x27: 0x00000000fffeffff
+# NZCV: N:1 Z:0 C:1 V:0
+#    x2: 0x~~~~~~~~~~~~~~~~
+# NZCV: N:1 Z:0 C:0 V:0
+#    x5: 0xffffffff70000002
+#    x8: 0x0000000000000001
+#   x10: 0x000000000000001e
+#   x12: 0x00000000ffffff7d
+#   x14: 0x0000000000000082
+#   x16: 0x00000000ffffff7b
+#   x18: 0x0000000000000086
+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:0 Z:1 C:0 V:0
+#   x24: 0x0000000000040000
+#   x26: 0x0000000001fff000
+#   x28: 0x0000000000000000
+#    x2: 0x~~~~~~~~~~~~~~~~
+#    x4: 0x0000000000000000
+#    x6: 0x000000000000003f
+#    x8: 0x0000000000000000
+#   x11: 0x0000000000000000
+#   x22: 0x0000000000000000
+#   x28: 0x0000000000000000
+#    x2: 0x~~~~~~~~~~~~~~~~
+#    x4: 0x0000000000000002
+#    x6: 0x000000000000ffff
+#    x8: 0x0000000000000001
+#   x10: 0x0000000000000000
+#   v13: 0x00000000000000004036e00cd9b7e45b
+#    v8: 0x00000000000000000000000041c5851e
+#    v1: 0x00000000000000003ff587933f9e0419 (d1: 1.34560)
+#   v25: 0x000000000000000000000000410a4396 (s25: 8.64150)
+#    v1: 0x0000000000000000ffffffffffffffff
+#    v4: 0x00000000000000000000000000000000
+#    v2: 0x00000000000000000000000000000000
+#   v12: 0x000000000000000000000000ffffffff
+#   v13: 0x0000000000000000404633d07142f43a (d13: 44.4048)
+#   v27: 0x000000000000000000000000424094fe (s27: 48.1455)
+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:0 Z:1 C:1 V:0
+#   v19: 0x00000000000000000000000000000000
+#    v0: 0x00000000000000000000000000000000
+#    v1: 0x00000000000000000000000000000000
+#   v22: 0x00000000000000000000000000000000
+#   v27: 0x0000000000000000ffffffffffffffff
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+#   v17: 0x000000000000000000000000ffffffff
+#   v24: 0x00000000000000000000000000000000
+#   v11: 0x00000000000000000000000000000000
+#    v5: 0x00000000000000000000000000000000
+#   v18: 0x00000000000000000000000000000000
+# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:1 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:0 Z:0 C:1 V:1
+# NZCV: N:0 Z:1 C:1 V:0
+#   v10: 0x00000000000000000000000000000000 (d10: 0.00000)
+#   v22: 0x00000000000000000000000000000000 (s22: 0.00000)
+#    v4: 0x00000000000000000000000000000000 (d4: 0.00000)
+#   v11: 0x00000000000000000000000000000000 (d11: 0.00000)
+#    v8: 0x00000000000000000000000000004a0e
+#   v12: 0x0000000000000000000000000000ffff
+#   v12: 0x00000000000000000000000000000000 (s12: 0.00000)
+#   v27: 0x0000000000000000000000004072c000 (s27: 3.79297)
+#   v28: 0x00000000000000000000000000000016
+#    v3: 0x00000000000000000000000000000000
+#   x18: 0x0000000000000000
+#   x29: 0x0000000000000000
+#    x9: 0x0000000000000000
+#    lr: 0x0000000000000000
+#   v14: 0x00000000000000000000000000000000
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+#   x16: 0x0000000000000000
+#   x18: 0x0000000000000000
+#   x26: 0x0000000000000009
+#   x25: 0x0000000000000000
+#   v30: 0x00000000000000000000000000000000
+#   v12: 0x00000000000000000000000000000012
+#    x9: 0x0000000000000009
+#   x19: 0x0000000000000007
+#    x6: 0x0000000000000008
+#   x22: 0x0000000000000008
+#   v27: 0x00000000000000000000000000000000
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+#   x29: 0x0000000000000000
+#   x26: 0x0000000000000000
+#   x13: 0x0000000000000000
+#    x5: 0x0000000000000000
+#   v30: 0x00000000000000000000000000000014
+#   v10: 0x00000000000000000000000000000000
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+#   x18: 0x0000000000000000
+#    x8: 0x0000000000000000
+#   x17: 0x0000000000000000
+#    v0: 0x0000000000000000000000000000001c
+#    v6: 0x00000000000000000000000000000009
+#   x29: 0x0000000000000000
+#   x25: 0x0000000000000000
+#    lr: 0x0000000000000000
+#   x27: 0x0000000000000000
+#   v11: 0x00000000000000000000000000000000
+#   v29: 0x00000000000000000000000000000019
+#   x15: 0x0000000000000001
+#   x16: 0x0000000000000009
+#   x13: 0x000000000000001b
+#    x3: 0x000000000000001d
+#   v24: 0x00000000000000000000000000000001
+#   v14: 0x00000000000000000000000000000001
+#   x26: 0x0000000000000001
+#   x27: 0x0000000000000001
+#   x29: 0x0000000000000001
+#   v12: 0x00000000000000000000000000000001
+#   v15: 0x00000000000000000000000000000000
+#   v13: 0x00000000000000000000000000000000
+#    v8: 0x00000000000000000000000000000000
+#   v31: 0x00000000000000000000000000000000
+#    x6: 0x000000000000000c
+#   x25: 0x0000000000000000
+#    x9: 0x0000000000000000
+#   x17: 0x0000000000000000
+#   x19: 0x0000000000000000
+#   x22: 0x0000000000000000
+#   x14: 0x0000000000000018
+#    x3: 0x0000000000000000
+#   v28: 0x00000000000000000000000000000000
+#    v0: 0x00000000000000000000000000000000
+#    v2: 0x00000000000000000000000000000000
+#    v4: 0x00000000000000000000000000000000
+#   x11: 0x0000000000000000
+#    x7: 0x0000000000000000
+#   x18: 0x0000000000000000
+#   x14: 0x0000000000000000
+#   x22: 0x0000000000000000
+#    x8: 0x0000000000000000
+#    x7: 0x0000000000000018
+#   x22: 0x00008a4396000000
+#    v6: 0x00000000000000007ff0000000000000 (d6: inf)
+#   v26: 0x00000000000000000000000000000000 (s26: 0.00000)
+#   v18: 0x00000000000000000000000000000014 (d18: 9.88131e-323)
+#   v13: 0x00000000000000000000000000000000 (s13: 0.00000)
+#   v12: 0x00000000000000000000000000000000 (d12: 0.00000)
+#   v12: 0x00000000000000000000000000000000 (s12: 0.00000)
+#   v28: 0x00000000000000000000000000000000 (d28: 0.00000)
+#    v6: 0x00000000000000000000000000000000 (s6: 0.00000)
+#   v20: 0x00000000000000000000000000000014 (d20: 9.88131e-323)
+#    v7: 0x00000000000000000000000000000000 (s7: 0.00000)
+#   v19: 0x00000000000000000000000000000001 (d19: 4.94066e-324)
+#    v0: 0x000000000000000000000000ffffffff (s0: -nan)
+#   v13: 0x00000000000000000000000000000000 (d13: 0.00000)
+#    v2: 0x00000000000000000000000000000000
+#    v8: 0x0000000000000000c004000000000000 (d8: -2.50000)
+#    v5: 0x00000000000000000000000000000000 (s5: 0.00000)
+#   v25: 0x00000000000000000000000000000001
+#   v21: 0x00000000000000000000000040380000 (s21: 2.87500)
+#   x18: 0x0000000000000001
+#   x18: 0x0000000000000000
+#   v20: 0x00000000000000000000000000000001 (d20: 4.94066e-324)
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+#   v12: 0x00000000000000000000000000fffeff (..., 0.00000, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x00000000000000001700000000000000 (..., 4.13590e-25, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0000000000000000767574737271706f (..., 1.24460e+33, 4.78220e+30) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000007e7d7c7b7a797877 (..., 8.42353e+37, 3.23831e+35) <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x0000000000000000868584838281807f (..., -5.02237e-35, -1.90286e-37) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v31: 0x00000000000000007574737271706f6e (..., 3.09878e+32, 1.19058e+30) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x00000000000000007d7c7b7a79787776 (..., 2.09754e+37, 8.06320e+34) <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x00000000000000008584838281807f7e (..., -1.24615e-35, -4.72027e-38) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v0: 0x0000000000000000ff0000850002ff01 (..., -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x00000000000000000000000000fffeff (..., 0.00000, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x00000000000000008d8c8b8a89888786 (..., -8.66176e-31, -3.28683e-33) <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x00000000000000009594939291908f8e (..., -6.00095e-26, -2.28077e-28) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v3: 0x00000000000000008c8b8a8988878685 (..., -2.14997e-31, -8.15664e-34) <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x000000000000000094939291908f8e8d (..., -1.49010e-26, -5.66232e-29) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0000000000000000ff0000850002ff01 (..., -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x00000000000000009c9b9a9998979695 (..., -1.02970e-21, -3.91846e-24) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v11: 0x00000000000000009b9a999897969594 (..., -2.55764e-22, -9.73128e-25) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v16: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000001700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000001f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x0000000000000000a3a2a1a09f9e9d9c <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x0000000000000000abaaa9a8a7a6a5a4 <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0000000000000000b3b2b1b0afaeadac <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000bbbab9b8b7b6b5b4 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v1: 0x0000000000000000a2a1a09f9e9d9c9b <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000000000aaa9a8a7a6a5a4a3 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000b2b1b0afaeadacab <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000bab9b8b7b6b5b4b3 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v30: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x00000000000000001700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x0000000000000000c2c1c0bfbebdbcbb <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0000000000000000cac9c8c7c6c5c4c3 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000d2d1d0cfcecdcccb <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000c1c0bfbebdbcbbba <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000c9c8c7c6c5c4c3c2 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x0000000000000000d1d0cfcecdcccbca <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000d9d8d7d6d5d4d3d2 <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000e1e0dfdedddcdbda <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v23: 0x0000000000000000d8d7d6d5d4d3d2d1 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x0000000000000000e0dfdedddcdbdad9 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x0000000000000000e8e7e6e5e4e3e2e1 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v14: 0x0000000000000000e7e6e5e4e3e2e1e0 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0000000000fffeffff0000850002ff01 (0.00000, 2.35095e-38, -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x1f1e1d1c1b1a19181700000000000000 (3.34819e-20, 1.27467e-22, 4.13590e-25, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x2f2e2d2c2b2a29282726252423222120 (1.58413e-10, 6.04532e-13, 2.30573e-15, 8.78905e-18) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x3f3e3d3c3b3a39383736353433323130 (0.743122, 0.00284155, 1.08604e-05, 4.14886e-08) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0xf7f6f5f4f3f2f1f0efeeedecebeae9e8 (-1.00179e+34, -3.84962e+31, -1.47890e+29, -5.67986e+26) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0706050403020100fffefdfcfbfaf9f8 (1.00825e-34, 3.82047e-37, -nan, -2.60629e+36) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x17161514131211100f0e0d0c0b0a0908 (4.84942e-25, 1.84362e-27, 7.00365e-30, 2.65846e-32) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x27262524232221201f1e1d1c1b1a1918 (2.30573e-15, 8.78905e-18, 3.34819e-20, 1.27467e-22) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v4: 0xf6f5f4f3f2f1f0efeeedecebeae9e8e7 (-2.49430e+33, -9.58428e+30, -3.68172e+28, -1.41390e+26) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x06050403020100fffefdfcfbfaf9f8f7 (2.50175e-35, 9.47771e-38, -1.68804e+38, -6.48966e+35) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x161514131211100f0e0d0c0b0a090807 (1.20425e-25, 4.57737e-28, 1.73854e-30, 6.59782e-33) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x262524232221201f1e1d1c1b1a191817 (5.72948e-16, 2.18366e-18, 8.31732e-21, 3.16591e-23) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000fffeffff0000850002ff01 (0.00000, 2.35095e-38, -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x1f1e1d1c1b1a19181700000000000000 (3.34819e-20, 1.27467e-22, 4.13590e-25, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x2f2e2d2c2b2a29282726252423222120 (1.58413e-10, 6.04532e-13, 2.30573e-15, 8.78905e-18) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x363534333231302f2e2d2c2b2a292827 (2.70015e-06, 1.03137e-08, 3.93749e-11, 1.50241e-13) <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x464544434241403f3e3d3c3b3a393837 (12625.1, 48.3127, 0.184800, 0.000706557) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x565554535251504f4e4d4c4b4a494847 (5.86395e+13, 2.24749e+11, 8.61082e+08, 3.29781e+06) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v15: 0x3534333231302f2e2d2c2b2a29282726 (6.71297e-07, 2.56382e-09, 9.78665e-12, 3.73374e-14) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x4544434241403f3e3d3c3b3a39383736 (3140.20, 12.0154, 0.0459549, 0.000175682) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x5554535251504f4e4d4c4b4a49484746 (1.45909e+13, 5.59177e+10, 2.14218e+08, 820340.) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v20: 0x0000000000fffeffff0000850002ff01 (0.00000, 2.35095e-38, -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x1f1e1d1c1b1a19181700000000000000 (3.34819e-20, 1.27467e-22, 4.13590e-25, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x6564636261605f5e5d5c5b5a59585756 (6.74083e+22, 2.58684e+20, 9.92399e+17, 3.80591e+15) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x7574737271706f6e6d6c6b6a69686766 (3.09878e+32, 1.19058e+30, 4.57302e+27, 1.75599e+25) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v11: 0x64636261605f5e5d5c5b5a5958575655 (1.67780e+22, 6.43816e+19, 2.46969e+17, 9.47063e+14) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x74737271706f6e6d6c6b6a6968676665 (7.71514e+31, 2.96402e+29, 1.13840e+27, 4.37102e+24) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v15: 0x0000000000fffeffff0000850002ff01 (0.00000, 2.35095e-38, -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x84838281807f7e7d7c7b7a7978777675 (-3.09178e-36, -1.17085e-38, 5.22300e+36, 2.00766e+34) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v0: 0x838281807f7e7d7c7b7a797877767574 (-7.67045e-37, 3.38275e+38, 1.30054e+36, 4.99878e+33) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v17: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000001700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x00000000000000001f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x00000000000000008b8a898887868584 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x0000000000000000939291908f8e8d8c <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000009b9a999897969594 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0000000000000000a3a2a1a09f9e9d9c <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000008a89888786858483 <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x00000000000000009291908f8e8d8c8b <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x00000000000000009a99989796959493 <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000000000a2a1a09f9e9d9c9b <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000001700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000000000aaa9a8a7a6a5a4a3 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000b2b1b0afaeadacab <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000bab9b8b7b6b5b4b3 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000000000a9a8a7a6a5a4a3a2 <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x0000000000000000b1b0afaeadacabaa <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x0000000000000000b9b8b7b6b5b4b3b2 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v10: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x0000000000000000c1c0bfbebdbcbbba <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000000000c9c8c7c6c5c4c3c2 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000c0bfbebdbcbbbab9 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x0000000000000000c8c7c6c5c4c3c2c1 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v31: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x0000000000000000d0cfcecdcccbcac9 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v28: 0x0000000000000000cfcecdcccbcac9c8 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v5: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x2f2e2d2c2b2a29282726252423222120 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x3f3e3d3c3b3a39383736353433323130 <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0xdfdedddcdbdad9d8d7d6d5d4d3d2d1d0 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0xefeeedecebeae9e8e7e6e5e4e3e2e1e0 <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0xfffefdfcfbfaf9f8f7f6f5f4f3f2f1f0 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x0f0e0d0c0b0a09080706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v10: 0xdedddcdbdad9d8d7d6d5d4d3d2d1d0cf <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0xeeedecebeae9e8e7e6e5e4e3e2e1e0df <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0xfefdfcfbfaf9f8f7f6f5f4f3f2f1f0ef <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x0e0d0c0b0a09080706050403020100ff <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x2f2e2d2c2b2a29282726252423222120 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x1e1d1c1b1a191817161514131211100f <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x2e2d2c2b2a292827262524232221201f <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x3e3d3c3b3a393837363534333231302f <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v17: 0x1d1c1b1a191817161514131211100f0e <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x2d2c2b2a292827262524232221201f1e <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x3d3c3b3a393837363534333231302f2e <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x4d4c4b4a494847464544434241403f3e <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x5d5c5b5a595857565554535251504f4e <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v4: 0x4c4b4a494847464544434241403f3e3d <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x5c5b5a595857565554535251504f4e4d <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v9: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x6c6b6a696867666564636261605f5e5d <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v26: 0x6b6a696867666564636261605f5e5d5c <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v19: 0x3d3c3b3a39383736353433323130012e <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0xfefdfcfbfaf9f8f7f6f5f4f36cf1f0ef <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v27: 0x6c6b6a6b6867666564636261605f5e5d <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v10: 0xff0000850002ff01d6d5d4d3d2d1d0cf (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x737271706f6e6d6c636261605f5e5d5c (1.28953e+248, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v7: 0x7271706f6e6d6c6b2726252423222120 (1.86056e+243, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v19: 0x3d3c3b3aff013736353433323130012e <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0xff0000850002ff01d6d5d4d37473d0cf <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v5: 0x5c5b5a595857737254535251504f4e4d <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v21: 0x4d4c4b4a0002ff014544434241403f3e (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x0e0d0c0b7776757406050403020100ff (..., 4.99878e+33, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v1: 0x0000000076757473e8e7e6e5e4e3e2e1 (..., 1.24460e+33, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v2: 0x01010101010101010101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x77777777777777777777777777777777 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v22: 0x76767676767676767676767676767676 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v25: 0x0000000000000000ff0000850002ff01 (d25: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000007e7d7c7b7a797877 (d9: 1.97467e+301) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v23: 0x00000000000000007d7c7b7a79787776 (d23: 2.91053e+296) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v19: 0xff0000850002ff01ff0000850002ff01 (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x8584838281807f7e8584838281807f7e (-4.41447e-282, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v30: 0x84838281807f7e7d84838281807f7e7d (-6.40629e-287, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00000000000000000002ff010002ff01 (s24: 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000008887868588878685 (s26: -8.15664e-34) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v28: 0x00000000000000008786858487868584 (s28: -2.02406e-34) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v19: 0x0000000000000000ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x00000000000000008988898889888988 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v21: 0x00000000000000008887888788878887 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v15: 0x0002ff010002ff010002ff010002ff01 (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x8c8b8a898c8b8a898c8b8a898c8b8a89 (..., -2.14997e-31, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v23: 0x8b8a89888b8a89888b8a89888b8a8988 (..., -5.33626e-32, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000000101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x00000000000000008c8c8c8c8c8c8c8c <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000008b8b8b8b8b8b8b8b <- 0x~~~~~~~~~~~~~~~~
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+#   v13: 0xff01ff01ff01ff01ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x8d8c8d8c8d8c8d8c8d8c8d8c8d8c8d8c <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v27: 0x8c8b8c8b8c8b8c8b8c8b8c8b8c8b8c8b <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v21: 0x1e1c1a18000000000000ffff00850201 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x1f1d1b1917000000000000feff0000ff <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0xaba9a7a5a3a19f9d9b99979593918f8d <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0xacaaa8a6a4a2a09e9c9a98969492908e <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v12: 0xaaa8a6a4a2a09e9c9a98969492908e8c <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0xaba9a7a5a3a19f9d9b99979593918f8d <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v14: 0x1700000000000000ff0000850002ff01 (6.68887e-198, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x1f1e1d1c1b1a19180000000000fffeff (8.56775e-159, 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0xc3c2c1c0bfbebdbcb3b2b1b0afaeadac (-2.70315e+18, -1.16334e-59) <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0xcbcac9c8c7c6c5c4bbbab9b8b7b6b5b4 (-1.31369e+57, -5.65934e-21) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v12: 0xc2c1c0bfbebdbcbbb2b1b0afaeadacab (-3.90391e+13, -1.67978e-64) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0xcac9c8c7c6c5c4c3bab9b8b7b6b5b4b3 (-1.92941e+52, -8.31108e-26) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v27: 0x000000000000000000fffeff0002ff01 (..., 2.35095e-38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x000000000000000000000000ff000085 (..., 0.00000, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000000000d6d5d4d3cecdcccb (..., -1.17555e+14, -1.72638e+09) <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000dad9d8d7d2d1d0cf (..., -3.06592e+16, -4.50576e+11) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000000000d5d4d3d2cdcccbca (..., -2.92508e+13, -4.29488e+08) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x0000000000000000d9d8d7d6d1d0cfce (..., -7.62949e+15, -1.12105e+11) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000000000feff0085ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x0000000000000000000000ffff000002 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x0000000000000000e7e6e3e2dfdedbda <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x0000000000000000e9e8e5e4e1e0dddc <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v1: 0x0000000000000000e6e5e2e1dedddad9 <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000000000e8e7e4e3e0dfdcdb <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v20: 0x1b1a19180000000000fffeff0002ff01 (1.27467e-22, 0.00000, 2.35095e-38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x1f1e1d1c1700000000000000ff000085 (3.34819e-20, 4.13590e-25, 0.00000, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x04030201fcfbfaf9f4f3f2f1ecebeae9 (1.53999e-36, -1.04669e+37, -1.54621e+32, -2.28166e+27) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x0807060500fffefdf8f7f6f5f0efeeed (4.06322e-34, 2.35095e-38, -4.02346e+34, -5.94046e+29) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v24: 0x03020100fbfaf9f8f3f2f1f0ebeae9e8 (3.82047e-37, -2.60629e+36, -3.84962e+31, -5.67986e+26) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x07060504fffefdfcf7f6f5f4efeeedec (1.00825e-34, -nan, -1.00179e+34, -1.47890e+29) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000000000ffff00850201 <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x0000000000000000000000feff0000ff <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x0000000000000000161412100e0c0a08 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x0000000000000000171513110f0d0b09 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000001513110f0d0b0907 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0000000000000000161412100e0c0a08 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v30: 0x1d1c1918000000000000feff0085ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x1f1e1b1a17000000000000ffff000002 <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x3433302f2c2b28272423201f1c1b1817 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x363532312e2d2a29262522211e1d1a19 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v13: 0x33322f2e2b2a272623221f1e1b1a1716 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x353431302d2c2928252421201d1c1918 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v5: 0x363532012e2d2a29262522211e1d1a19 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x1f1e1dff1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x4544434241403f3e363c3b3a39383736 <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000003700ffff00850201 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0706050403020100fffefdfcfb35f9f8 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x1d1c1918000000000000feff0036ff01 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v11: 0xff0000850002ff01f8f7f6f5f0efeeed (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000fffeffd5d4d3d2cdcccbca (8.28892e-317, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000003e3d3c3b3a393837 (d26: 6.80687e-09) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000464544434241403f (d27: 3.36984e+30) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v25: 0x07060504fffefdfc3d3c3b3a39383736 (d25: 1.00298e-13) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000004544434241403f3e (d26: 4.89923e+25) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v18: 0xff01000000000000000000feff0000ff <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00020000000000008b8b8b8b8b8b8b8b <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000474600003700ffff00850201 <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0xff01000049480000000000feff0000ff <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v30: 0x1d1c191800000000000046450036ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x1f1e1b1a1700000000004847ff000002 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0002ff0103020100fffefdfcfb35f9f8 (2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0xff00008500000000000046450036ff01 (-1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x0000000000000000000000004c4b4a49 (s28: 5.32913e+07) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0002ff0103020100fffefdfc504f4e4d (s29: 1.39121e+10) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v6: 0x1f1e1dff1b1a19184b4a494800000000 (..., 1.32570e+07, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000004f4e4d4c0d0b0907 (..., 3.46117e+09, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v26: 0x01010101010101010101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0xffffffffffffffffffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x50505050505050505050505050505050 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x51515151515151515151515151515151 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v5: 0x4f4f4f4f4f4f4f4f4f4f4f4f4f4f4f4f <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x50505050505050505050505050505050 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0000000000000000ff0000850002ff01 (d26: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x00000000000000000000000000fffeff (d27: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x00000000000000005857565554535251 (d14: 3.67814e+117) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x0000000000000000605f5e5d5c5b5a59 (d15: 1.68234e+156) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v23: 0x00000000000000005756555453525150 (d23: 5.37096e+112) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00000000000000005f5e5d5c5b5a5958 (d24: 2.48489e+151) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v11: 0xff0000850002ff01ff0000850002ff01 (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000fffeff0000000000fffeff (8.28892e-317, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x67666564636261606766656463626160 (1.24732e+190, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x6f6e6d6c6b6a69686f6e6d6c6b6a6968 (5.76650e+228, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v15: 0x666564636261605f666564636261605f (1.81795e+185, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x6e6d6c6b6a6968676e6d6c6b6a696867 (8.50866e+223, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000000002ff010002ff01 (s26: 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000ff000085ff000085 (s27: -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x00000000000000007271706f7271706f (s22: 4.78220e+30) <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x00000000000000007675747376757473 (s23: 1.24460e+33) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v2: 0x000000000000000071706f6e71706f6e (s2: 1.19058e+30) <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x00000000000000007574737275747372 (s3: 3.09878e+32) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000000000ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x00000000000000000002000200020002 <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000007776777677767776 <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x00000000000000007978797879787978 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000007675767576757675 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000007877787778777877 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v7: 0x0002ff010002ff010002ff010002ff01 (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0xff000085ff000085ff000085ff000085 (..., -1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x7c7b7a797c7b7a797c7b7a797c7b7a79 (..., 5.22300e+36, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x807f7e7d807f7e7d807f7e7d807f7e7d (..., -1.17085e-38, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v21: 0x7b7a79787b7a79787b7a79787b7a7978 (..., 1.30054e+36, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x7f7e7d7c7f7e7d7c7f7e7d7c7f7e7d7c (..., 3.38275e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000000101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000ffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x00000000000000008080808080808080 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x00000000000000008181818181818181 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v11: 0x00000000000000007f7f7f7f7f7f7f7f <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x00000000000000008080808080808080 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v12: 0xff01ff01ff01ff01ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x00020002000200020002000200020002 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x82818281828182818281828182818281 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x84838483848384838483848384838483 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v25: 0x81808180818081808180818081808180 <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x83828382838283828382838283828382 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v20: 0x2d2a2724211e1b1800000000fe000001 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x2e2b2825221f1c1900000000ffff85ff <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x2f2c292623201d1a1700000000ff0002 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0xb1aeaba8a5a29f9c999693908d8a8784 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0xb2afaca9a6a3a09d9a9794918e8b8885 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0xb3b0adaaa7a4a19e9b9895928f8c8986 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v20: 0xb0adaaa7a4a19e9b9895928f8c898683 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0xb1aeaba8a5a29f9c999693908d8a8784 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0xb2afaca9a6a3a09d9a9794918e8b8885 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v21: 0x1f1e1d1c1b1a1918ff0000850002ff01 (8.56775e-159, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x27262524232221200000000000fffeff (4.28794e-120, 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x2f2e2d2c2b2a29281700000000000000 (1.98829e-81, 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0xd2d1d0cfcecdcccbbab9b8b7b6b5b4b3 (-9.07279e+90, -8.31108e-26) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0xdad9d8d7d6d5d4d3c2c1c0bfbebdbcbb (-4.47908e+129, -3.90391e+13) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0xe2e1e0dfdedddcdbcac9c8c7c6c5c4c3 (-2.10851e+168, -1.92941e+52) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v27: 0xd1d0cfcecdcccbcab9b8b7b6b5b4b3b2 (-1.30639e+86, -1.21867e-30) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0xd9d8d7d6d5d4d3d2c1c0bfbebdbcbbba (-6.56908e+124, -5.62003e+08) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0xe1e0dfdedddcdbdac9c8c7c6c5c4c3c2 (-3.03668e+163, -2.82942e+47) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v7: 0x0000000000000000000000000002ff01 (..., 0.00000, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x000000000000000000000000ff000085 (..., 0.00000, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000001700000000fffeff (..., 4.13590e-25, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x0000000000000000f1f0efeee5e4e3e2 (..., -2.38613e+30, -1.35113e+23) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x0000000000000000f5f4f3f2e9e8e7e6 (..., -6.21029e+32, -3.51957e+25) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x0000000000000000f9f8f7f6edecebea (..., -1.61590e+35, -9.16546e+27) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0000000000000000f0efeeede4e3e2e1 (..., -5.94046e+29, -3.36301e+22) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000f4f3f2f1e8e7e6e5 (..., -1.54621e+32, -8.76101e+24) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x0000000000000000f8f7f6f5ecebeae9 (..., -4.02346e+34, -2.28166e+27) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v27: 0x000000000000000000000000ff00ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x000000000000000000000000feff0002 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x00000000000000001700000000ff0085 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x00000000000000000c0b060500fffaf9 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x00000000000000000e0d08070201fcfb <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x0000000000000000100f0a090403fefd <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000000b0a0504fffef9f8 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00000000000000000d0c07060100fbfa <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000000f0e09080302fdfc <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v2: 0x272625241b1a1918000000000002ff01 (2.30573e-15, 1.27467e-22, 0.00000, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x2b2a29281f1e1d1c00000000ff000085 (6.04532e-13, 3.34819e-20, 0.00000, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x2f2e2d2c232221201700000000fffeff (1.58413e-10, 8.78905e-18, 4.13590e-25, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x373635342b2a29281f1e1d1c13121110 (1.08604e-05, 6.04532e-13, 3.34819e-20, 1.84362e-27) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x3b3a39382f2e2d2c2322212017161514 (0.00284155, 1.58413e-10, 8.78905e-18, 4.84942e-25) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x3f3e3d3c33323130272625241b1a1918 (0.743122, 4.14886e-08, 2.30573e-15, 1.27467e-22) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v11: 0x363534332a2928271e1d1c1b1211100f (2.70015e-06, 1.50241e-13, 8.31732e-21, 4.57737e-28) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x3a3938372e2d2c2b2221201f16151413 (0.000706557, 3.93749e-11, 2.18366e-18, 1.20425e-25) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x3e3d3c3b3231302f262524231a191817 (0.184800, 1.03137e-08, 5.72948e-16, 3.16591e-23) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v29: 0x000000000000000000000000fe000001 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x000000000000000000000000ffff85ff <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x00000000000000001700000000ff0002 <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x000000000000000054514e4b4845423f <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x000000000000000055524f4c49464340 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x00000000000000005653504d4a474441 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v12: 0x000000000000000053504d4a4744413e <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x000000000000000054514e4b4845423f <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x000000000000000055524f4c49464340 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v22: 0x2b2a25241f1e191800000000ff00ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x2d2c272621201b1a00000000feff0002 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x2f2e292823221d1c1700000000ff0085 <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x81807b7a75746f6e696863625d5c5756 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x83827d7c777671706b6a65645f5e5958 <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x85847f7e797873726d6c676661605b5a <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v28: 0x807f7a7974736e6d686762615c5b5655 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x82817c7b7675706f6a6964635e5d5857 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x84837e7d787772716c6b6665605f5a59 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v21: 0x0000000001000000f5f4f3f2e9e8e7e6 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x2b2a2524ff1e191800000000ff00ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x2d2c272602201b1a00000000feff0002 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x4f4f4f4f4f4f854f4f4f4f4f4f4f4f4f <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x82818281828186818281828182818281 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000087000b0a0504fffef9f8 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v23: 0x2d2c272602201b1a00000000feff0084 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x2f2e292823221d1c1700000000ff0085 <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x3b3a39382f2e2d2c2322212017161586 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v16: 0x6e6d6c6b6a696867ff0000850002ff01 (d16: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000474600000000000000fffeff (d17: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0xd2d1d0cfcecdcccb1700000000000000 (d18: 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x84837e7d787772718e8d8c8b8a898887 (d30: -1.41807e-238) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x0000000000000000969594939291908f (d31: -7.04826e-200) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0xc3c2c1c0bfbebdbc9e9d9c9b9a999897 (d0: -3.29099e-161) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v28: 0x8d8c8b8a89888786686762615c5b5655 (-2.09028e-243, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x9594939291908f8e6a6964635e5d5857 (-1.02545e-204, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x9d9c9b9a999897968e8d8c8b8a898887 (-4.85140e-166, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v13: 0x81807b7a75746f6e6968ff015d5c5756 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x83827d7c777671706b6a00025f5e5958 <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x85847f7e797873726d6c008561605b5a <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x9f9e2524ff1e191800000000ff00ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0xa1a0272602201b1a00000000feff0084 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0xa3a2292823221d1c1700000000ff0085 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v14: 0x83827d7c777671709e9d00025f5e5958 <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x85847f7e79787372a09f008561605b5a <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x6e6d6c6b6a696867a2a100850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v22: 0x0002ff01ff1e191800000000ff00ff01 (2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0xff00008502201b1a00000000feff0084 (-1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00fffeff23221d1c1700000000ff0085 (2.35095e-38, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x9d9c9b9aa6a5a4a38e8d8c8b8a898887 (..., -1.14938e-15, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x00000000aaa9a8a7969594939291908f (..., -3.01375e-13, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0xc3c2c1c0aeadacab9e9d9c9b9a999897 (..., -7.89780e-11, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000000000a5a4a3a24744413e (..., -2.85603e-16, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x81807b7a75746f6ea9a8a7a65d5c5756 (..., -7.48978e-14, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x83827d7c77767170adacabaa5f5e5958 (..., -1.96304e-11, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v24: 0x01010101010101010101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0xffffffffffffffffffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x02020202020202020202020202020202 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0xaeaeaeaeaeaeaeaeaeaeaeaeaeaeaeae <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0xafafafafafafafafafafafafafafafaf <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0xb0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v3: 0xadadadadadadadadadadadadadadadad <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0xaeaeaeaeaeaeaeaeaeaeaeaeaeaeaeae <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0xafafafafafafafafafafafafafafafaf <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000ff0000850002ff01 (d4: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x00000000000000000000000000fffeff (d5: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000001700000000000000 (d6: 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x0000000000000000b7b6b5b4b3b2b1b0 (d7: -2.60696e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0000000000000000bfbebdbcbbbab9b8 (d8: -0.120083) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x0000000000000000c7c6c5c4c3c2c1c0 (d9: -6.05398e+37) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v17: 0x0000000000000000b6b5b4b3b2b1b0af (d17: -3.80205e-45) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x0000000000000000bebdbcbbbab9b8b7 (d18: -1.77248e-06) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x0000000000000000c6c5c4c3c2c1c0bf (d19: -8.83040e+32) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v16: 0xff0000850002ff01ff0000850002ff01 (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x0000000000fffeff0000000000fffeff (8.28892e-317, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x17000000000000001700000000000000 (6.68887e-198, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0xcecdcccbcac9c8c7cecdcccbcac9c8c7 (-4.11344e+71, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0xd6d5d4d3d2d1d0cfd6d5d4d3d2d1d0cf (-2.05087e+110, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0xdedddcdbdad9d8d7dedddcdbdad9d8d7 (-9.54613e+148, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v14: 0xcdcccbcac9c8c7c6cdcccbcac9c8c7c6 (-6.06516e+66, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0xd5d4d3d2d1d0cfced5d4d3d2d1d0cfce (-2.98548e+105, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0xdddcdbdad9d8d7d6dddcdbdad9d8d7d6 (-1.40766e+144, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v10: 0x00000000000000000002ff010002ff01 (s10: 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x0000000000000000ff000085ff000085 (s11: -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x000000000000000000fffeff00fffeff (s12: 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x0000000000000000e1e0dfdee1e0dfde (s0: -5.18525e+20) <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x0000000000000000e5e4e3e2e5e4e3e2 (s1: -1.35113e+23) <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000000000e9e8e7e6e9e8e7e6 (s2: -3.51957e+25) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v23: 0x0000000000000000e0dfdedde0dfdedd (s23: -1.29053e+20) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x0000000000000000e4e3e2e1e4e3e2e1 (s24: -3.36301e+22) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x0000000000000000e8e7e6e5e8e7e6e5 (s25: -8.76101e+24) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v22: 0x0000000000000000ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x00000000000000000002000200020002 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00000000000000000085008500850085 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x0000000000000000eae9eae9eae9eae9 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x0000000000000000ecebecebecebeceb <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0000000000000000eeedeeedeeedeeed <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v7: 0x0000000000000000e9e8e9e8e9e8e9e8 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0000000000000000ebeaebeaebeaebea <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x0000000000000000edecedecedecedec <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0002ff010002ff010002ff010002ff01 (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0xff000085ff000085ff000085ff000085 (..., -1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x00fffeff00fffeff00fffeff00fffeff (..., 2.35095e-38, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0xf1f0efeef1f0efeef1f0efeef1f0efee (..., -2.38613e+30, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0xf5f4f3f2f5f4f3f2f5f4f3f2f5f4f3f2 (..., -6.21029e+32, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0xf9f8f7f6f9f8f7f6f9f8f7f6f9f8f7f6 (..., -1.61590e+35, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v30: 0xf0efeeedf0efeeedf0efeeedf0efeeed (..., -5.94046e+29, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0xf4f3f2f1f4f3f2f1f4f3f2f1f4f3f2f1 (..., -1.54621e+32, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0xf8f7f6f5f8f7f6f5f8f7f6f5f8f7f6f5 (..., -4.02346e+34, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v2: 0x00000000000000000101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000ffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x00000000000000000202020202020202 <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x0000000000000000f9f9f9f9f9f9f9f9 <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x0000000000000000fafafafafafafafa <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000000000fbfbfbfbfbfbfbfb <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v28: 0x0000000000000000f8f8f8f8f8f8f8f8 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000000000f9f9f9f9f9f9f9f9 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x0000000000000000fafafafafafafafa <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v6: 0xff01ff01ff01ff01ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00020002000200020002000200020002 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00850085008500850085008500850085 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0xfcfbfcfbfcfbfcfbfcfbfcfbfcfbfcfb <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0xfefdfefdfefdfefdfefdfefdfefdfefd <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x00ff00ff00ff00ff00ff00ff00ff00ff <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v7: 0xfbfafbfafbfafbfafbfafbfafbfafbfa <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0xfdfcfdfcfdfcfdfcfdfcfdfcfdfcfdfc <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0xfffefffefffefffefffefffefffefffe <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v3: 0x3c3834302c2824201c18000000ff8501 <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x3d3935312d2925211d19000000fe00ff <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x3e3a36322e2a26221e1a000000ff0002 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x3f3b37332f2b27231f1b17000000ff00 <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x3c3834302c2824201c1814100c080400 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x3d3935312d2925211d1915110d090501 <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x3e3a36322e2a26221e1a16120e0a0602 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x3f3b37332f2b27231f1b17130f0b0703 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v5: 0x3b37332f2b27231f1b17130f0b0703ff <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x3c3834302c2824201c1814100c080400 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x3d3935312d2925211d1915110d090501 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x3e3a36322e2a26221e1a16120e0a0602 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v18: 0x2726252423222120ff0000850002ff01 (4.28794e-120, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x2f2e2d2c2b2a29280000000000fffeff (1.98829e-81, 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x37363534333231301700000000000000 (9.95833e-43, 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x3f3e3d3c3b3a39381f1e1d1c1b1a1918 (0.000461414, 8.56775e-159) <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x666564636261605f464544434241403f (1.81795e+185, 3.36984e+30) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x6e6d6c6b6a6968674e4d4c4b4a494847 (8.50866e+223, 1.57975e+69) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x767574737271706f565554535251504f (4.22243e+262, 7.82703e+107) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x7e7d7c7b7a7978775e5d5c5b5a595857 (1.97467e+301, 3.66628e+146) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v29: 0x6564636261605f5e4544434241403f3e (2.64379e+180, 4.89923e+25) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x6d6c6b6a696867664d4c4b4a49484746 (1.25402e+219, 2.32790e+64) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x7574737271706f6e5554535251504f4e (6.14144e+257, 1.13810e+103) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x7d7c7b7a797877765d5c5b5a59585756 (2.91053e+296, 5.40301e+141) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000000000000002ff01 (..., 0.00000, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x000000000000000017000000ff000085 (..., 4.13590e-25, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x00000000000000001b1a191800fffeff (..., 1.27467e-22, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x00000000000000001f1e1d1c00000000 (..., 3.34819e-20, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x000000000000000091908f8e81807f7e (..., -2.28077e-28, -4.72027e-38) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x00000000000000009594939285848382 (..., -6.00095e-26, -1.24615e-35) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000009998979689888786 (..., -1.57777e-23, -3.28683e-33) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x00000000000000009d9c9b9a8d8c8b8a (..., -4.14537e-21, -8.66176e-31) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000908f8e8d807f7e7d (..., -5.66232e-29, -1.17085e-38) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x00000000000000009493929184838281 (..., -1.49010e-26, -3.09178e-36) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000009897969588878685 (..., -3.91846e-24, -8.15664e-34) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000009c9b9a998c8b8a89 (..., -1.02970e-21, -2.14997e-31) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v16: 0x000000000000000019180000feffff01 <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000001b1a000000ff0002 <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000001d1c000000000085 <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000001f1e17000000ff00 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x0000000000000000b6b5aeada6a59e9d <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x0000000000000000b8b7b0afa8a7a09f <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x0000000000000000bab9b2b1aaa9a2a1 <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0000000000000000bcbbb4b3acaba4a3 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000000000b5b4adaca5a49d9c <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000b7b6afaea7a69f9e <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000b9b8b1b0a9a8a1a0 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x0000000000000000bbbab3b2abaaa3a2 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v7: 0x3332313023222120000000000002ff01 (4.14886e-08, 8.78905e-18, 0.00000, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x373635342726252417000000ff000085 (1.08604e-05, 2.30573e-15, 4.13590e-25, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x3b3a39382b2a29281b1a191800fffeff (0.00284155, 6.04532e-13, 1.27467e-22, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x3f3e3d3c2f2e2d2c1f1e1d1c00000000 (0.743122, 1.58413e-10, 3.34819e-20, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0xefeeedecdfdedddccfcecdccbfbebdbc (-1.47890e+29, -3.21185e+19, -6.93919e+09, -1.49017) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0xf3f2f1f0e3e2e1e0d3d2d1d0c3c2c1c0 (-3.84962e+31, -8.37048e+21, -1.81093e+12, -389.514) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0xf7f6f5f4e7e6e5e4d7d6d5d4c7c6c5c4 (-1.00179e+34, -2.18077e+24, -4.72428e+14, -101772.) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0xfbfaf9f8ebeae9e8dbdad9d8cbcac9c8 (-2.60629e+36, -5.67986e+26, -1.23202e+17, -2.65799e+07) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v29: 0xeeedecebdedddcdbcecdcccbbebdbcbb (-3.68172e+28, -7.99345e+18, -1.72638e+09, -0.370581) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0xf2f1f0efe2e1e0dfd2d1d0cfc2c1c0bf (-9.58428e+30, -2.08336e+21, -4.50576e+11, -96.8765) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0xf6f5f4f3e6e5e4e3d6d5d4d3c6c5c4c3 (-2.49430e+33, -5.42822e+23, -1.17555e+14, -25314.4) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0xfaf9f8f7eae9e8e7dad9d8d7cac9c8c7 (-6.48966e+35, -1.41390e+26, -3.06592e+16, -6.61207e+06) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v15: 0x00000000000000001c18000000ff8501 <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x00000000000000001d19000000fe00ff <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000001e1a000000ff0002 <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000001f1b17000000ff00 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x000000000000000017130f0b0703fffb <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x00000000000000001814100c080400fc <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x00000000000000001915110d090501fd <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x00000000000000001a16120e0a0602fe <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v5: 0x000000000000000016120e0a0602fefa <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x000000000000000017130f0b0703fffb <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000001814100c080400fc <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00000000000000001915110d090501fd <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v25: 0x393831302928212019180000feffff01 <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x3b3a33322b2a23221b1a000000ff0002 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x3d3c35342d2c25241d1c000000000085 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x3f3e37362f2e27261f1e17000000ff00 <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x53524b4a43423b3a33322b2a23221b1a <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x55544d4c45443d3c35342d2c25241d1c <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x57564f4e47463f3e37362f2e27261f1e <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x59585150494841403938313029282120 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v20: 0x52514a4942413a3932312a2922211a19 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x54534c4b44433c3b34332c2b24231c1b <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x56554e4d46453e3d36352e2d26251e1d <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x5857504f4847403f3837302f2827201f <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v20: 0x52514a4942413a3932312a2901211a19 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x54534c4b44433c3b34332c2bff231c1b <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x56554e4d46453e3d36352e2d02251e1d <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x5857504f4847403f3837302f0027201f <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000000000fbfbfbfb59fbfbfb <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x81807b7a75746f6ea9a8a7a65a5c5756 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0xcdcccbcac9c8c7c6cdcccbca5bc8c7c6 <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x00000000000000001c1800005cff8501 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v27: 0x3d3c35342d2c25241d58000000000085 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x3f3e37362f2e27261f5917000000ff00 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000000000195a110d090501fd <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x00000000000000001a5b120e0a0602fe <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v28: 0xff0000850002ff011f5917000000ff00 (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000fffeff195a110d090501fd (8.28892e-317, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x17000000000000001a5b120e0a0602fe (6.68887e-198, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x1f1e1d1c1b1a1918d6d5d4d3c6c5c4c3 (8.56775e-159, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x636261605f5e5d5c1c1800005cff8501 (5.54935e+170, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x6b6a6968676665641d19000000fe00ff (2.71346e+209, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x737271706f6e6d6c1e1a000000ff0002 (1.28953e+248, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x7b7a7978777675741f1b17000000ff00 (6.29888e+286, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v16: 0x6261605f5e5d5c5b1d19000000fe00ff (8.00514e+165, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x6a696867666564631e1a000000ff0002 (3.98304e+204, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x7271706f6e6d6c6b1f1b17000000ff00 (1.86056e+243, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x7a797877767574731f1e17000000ff00 (9.24687e+281, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v2: 0x5352ff0143423b3a33322b2a23221b1a <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x5554000245443d3c35342d2c25241d1c <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x5756008547463f3e37362f2e27261f1e <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x5958ff00494841403938313029282120 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x5958ff00494841407c7b313029282120 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000007e7d0f0b0703fffb <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x0000000000000000807f100c080400fc <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00000000000000008281110d090501fd <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00007b7a00000000807f100c080400fc <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00007d7c000000008281110d090501fd <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x3b3a7f7e2b2a29281b1a191800fffeff <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x3f3e81802f2e2d2c1f1e1d1c00000000 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000000002ff010703fffb (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00007b7a00000000ff000085080400fc (..., -1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00007d7c0000000000fffeff090501fd (..., 2.35095e-38, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x3b3a7f7e2b2a29280000000000fffeff (..., 0.00000, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x393831308584838219180000feffff01 (..., -1.24615e-35, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x3b3a3332898887861b1a000000ff0002 (..., -3.28683e-33, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x3d3c35348d8c8b8a1d58000000000085 (..., -8.66176e-31, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0xff00008591908f8e1f5917000000ff00 (..., -2.28077e-28, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v8: 0x848382810000000000fffeff090501fd (-3.09178e-36, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x888786852b2a29280000000000fffeff (-8.15664e-34, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x8c8b8a892f2e2d2c1f1e1d1c00000000 (-2.14997e-31, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x908f8e8d00000000fafafafafafafafa (-5.66232e-29, ...) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v14: 0x01010101010101010101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0xffffffffffffffffffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x02020202020202020202020202020202 <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x91919191919191919191919191919191 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x92929292929292929292929292929292 <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x93939393939393939393939393939393 <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x94949494949494949494949494949494 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v9: 0x90909090909090909090909090909090 <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x91919191919191919191919191919191 <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x92929292929292929292929292929292 <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x93939393939393939393939393939393 <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0000000000000000ff0000850002ff01 (d8: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000000000000000fffeff (d9: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x00000000000000001700000000000000 (d10: 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x00000000000000001f1e1d1c1b1a1918 (d11: 8.56775e-159) <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x00000000000000009b9a999897969594 (d4: -1.05028e-175) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x0000000000000000a3a2a1a09f9e9d9c (d5: -5.00653e-137) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x0000000000000000abaaa9a8a7a6a5a4 (d6: -2.43801e-98) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x0000000000000000b3b2b1b0afaeadac (d7: -1.16334e-59) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000009a99989796959493 (d26: -1.54211e-180) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000a2a1a09f9e9d9c9b (d27: -7.22772e-142) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x0000000000000000aaa9a8a7a6a5a4a3 (d28: -3.58004e-103) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000000000b2b1b0afaeadacab (d29: -1.67978e-64) <- 0x~~~~~~~~~~~~~~~~
+#    x1: 0x~~~~~~~~~~~~~~~~
+#   v19: 0xff0000850002ff01ff0000850002ff01 (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x0000000000fffeff0000000000fffeff (8.28892e-317, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x17000000000000001700000000000000 (6.68887e-198, ...) <- 0x~~~~~~~~~~~~~~~~
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diff --git a/test/test-trace-reference/log-sysregs b/test/test-trace-reference/log-sysregs
new file mode 100644
index 0000000..ae8ad7c
--- /dev/null
+++ b/test/test-trace-reference/log-sysregs
@@ -0,0 +1,46 @@
+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:0 Z:1 C:0 V:0
+# NZCV: N:0 Z:1 C:0 V:0
+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:1 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:0 V:1
+# NZCV: N:1 Z:0 C:0 V:0
+# NZCV: N:1 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:1 V:1
+# NZCV: N:1 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:1 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:1 Z:0 C:0 V:0
+# NZCV: N:1 Z:0 C:0 V:0
+# NZCV: N:1 Z:0 C:0 V:0
+# NZCV: N:1 Z:0 C:0 V:1
+# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:1 Z:0 C:1 V:0
+# NZCV: N:1 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:0 Z:1 C:0 V:0
+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:0 Z:1 C:1 V:0
+# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:1 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:0 Z:0 C:1 V:1
+# NZCV: N:0 Z:1 C:1 V:0
diff --git a/test/test-trace-reference/log-sysregs-colour b/test/test-trace-reference/log-sysregs-colour
new file mode 100644
index 0000000..aba0521
--- /dev/null
+++ b/test/test-trace-reference/log-sysregs-colour
@@ -0,0 +1,46 @@
+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:0 V:0
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+# NZCV: N:0 Z:0 C:0 V:0
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+# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:1 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:0 V:1
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+# NZCV: N:1 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:1 V:1
+# NZCV: N:1 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:0 V:0
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+# NZCV: N:1 Z:0 C:0 V:0
+# NZCV: N:1 Z:0 C:0 V:0
+# NZCV: N:1 Z:0 C:0 V:1
+# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:1 Z:0 C:1 V:0
+# NZCV: N:1 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:0 Z:1 C:0 V:0
+# NZCV: N:0 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:0 Z:1 C:1 V:0
+# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:1 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:0 Z:0 C:1 V:1
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diff --git a/test/test-trace-reference/log-vregs b/test/test-trace-reference/log-vregs
new file mode 100644
index 0000000..d8d8d76
--- /dev/null
+++ b/test/test-trace-reference/log-vregs
@@ -0,0 +1,2493 @@
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+#   v30: 0x0000000000000000ffffffffffffffff
+#   v31: 0x00000000000000000101010101010101
+#   v28: 0xffffffffffffffffffffffffffffffff
+#    v2: 0x00000000000000000000000000000000
+#   v29: 0x0000000000000000ffffff7df7f7f775
+#    v3: 0x0000000000000000ffffffffffffffff
+#    v1: 0xff000000000000000000000000000000
+#    v2: 0x000000000000000000ffffffffffffff
+#   v18: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x2f2e2d2c2b2a29282726252423222120 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x3f3e3d3c3b3a39383736353433323130 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0xdbdad9d8d7d6d5d4d3d2d1d0cfce0001 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0xebeae9e8e7e6e5e4e3e2e1e0dfdedddc <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0xfbfaf9f8f7f6f5f4f3f2f1f0efeeedec <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0b0a09080706050403020100fffefdfc <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0xdad9d8d7d6d5d4d3d2d1d0cfcecdcccb <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0xeae9e8e7e6e5e4e3e2e1e0dfdedddcdb <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0xfaf9f8f7f6f5f4f3f2f1f0efeeedeceb <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0a09080706050403020100fffefdfcfb <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x2f2e2d2c2b2a29282726252423222120 <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x1a191817161514131211100f0e0d0c0b <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x2a292827262524232221201f1e1d1c1b <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x3a393837363534333231302f2e2d2c2b <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x191817161514131211100f0e0d0c0b0a <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x292827262524232221201f1e1d1c1b1a <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x393837363534333231302f2e2d2c2b2a <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x494847464544434241403f3e3d3c3b3a <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x595857565554535251504f4e4d4c4b4a <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x4847464544434241403f3e3d3c3b3a39 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x5857565554535251504f4e4d4c4b4a49 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x6867666564636261605f5e5d5c5b5a59 <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x67666564636261605f5e5d5c5b5a5958 <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000ff0000850002ff01 (d4: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x00000000000000000000000000fffeff (d5: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000001700000000000000 (d6: 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000001f1e1d1c1b1a1918 (d7: 8.56775e-159) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000006f6e6d6c6b6a6968 (d17: 5.76650e+228) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000007776757473727170 (d18: 2.89670e+267) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000007f7e7d7c7b7a7978 (d19: 1.33818e+306) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x00000000000000008786858483828180 (d20: -2.08158e-272) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x00000000000000006e6d6c6b6a696867 (d28: 8.50866e+223) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000000000767574737271706f (d29: 4.22243e+262) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x00000000000000007e7d7c7b7a797877 (d30: 1.97467e+301) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x0000000000000000868584838281807f (d31: -3.03465e-277) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x0000000000000000ff0000850002ff01 (d20: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x00000000000000000000000000fffeff (d21: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x00000000000000001700000000000000 (d22: 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000008e8d8c8b8a898887 (d19: -1.41807e-238) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x0000000000000000969594939291908f (d20: -7.04826e-200) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x00000000000000009e9d9c9b9a999897 (d21: -3.29099e-161) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x00000000000000008d8c8b8a89888786 (d12: -2.09028e-243) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x00000000000000009594939291908f8e (d13: -1.02545e-204) <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x00000000000000009d9c9b9a99989796 (d14: -4.85140e-166) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000000000ff0000850002ff01 (d29: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x00000000000000000000000000fffeff (d30: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x0000000000000000a5a4a3a2a1a09f9e (d31: -2.38202e-127) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x0000000000000000adacabaaa9a8a7a6 (d0: -1.12597e-88) <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000a4a3a2a1a09f9e9d (d3: -3.45787e-132) <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000acabaaa9a8a7a6a5 (d4: -1.65794e-93) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x0000000000000000ff0000850002ff01 (d28: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x0000000000000000b4b3b2b1b0afaead (d11: -8.03348e-55) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000000000b3b2b1b0afaeadac (d29: -1.16334e-59) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x0000000000fffeffff0000850002ff01 (8.28892e-317, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x1f1e1d1c1b1a19181700000000000000 (8.56775e-159, 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x2f2e2d2c2b2a29282726252423222120 (1.98829e-81, 4.28794e-120) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x3f3e3d3c3b3a39383736353433323130 (0.000461414, 9.95833e-43) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0xc3c2c1c0bfbebdbcbbbab9b8b7b6b5b4 (-2.70315e+18, -5.65934e-21) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0xd3d2d1d0cfcecdcccbcac9c8c7c6c5c4 (-6.28100e+95, -1.31369e+57) <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0xe3e2e1e0dfdedddcdbdad9d8d7d6d5d4 (-1.45943e+173, -3.04943e+134) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0xf3f2f1f0efeeedecebeae9e8e7e6e5e4 (-3.39104e+250, -7.07849e+211) <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0xc2c1c0bfbebdbcbbbab9b8b7b6b5b4b3 (-3.90391e+13, -8.31108e-26) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0xd2d1d0cfcecdcccbcac9c8c7c6c5c4c3 (-9.07279e+90, -1.92941e+52) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0xe2e1e0dfdedddcdbdad9d8d7d6d5d4d3 (-2.10851e+168, -4.47908e+129) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0xf2f1f0efeeedecebeae9e8e7e6e5e4e3 (-4.90012e+245, -1.03980e+207) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0000000000fffeffff0000850002ff01 (8.28892e-317, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x1f1e1d1c1b1a19181700000000000000 (8.56775e-159, 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x2f2e2d2c2b2a29282726252423222120 (1.98829e-81, 4.28794e-120) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x020100fffefdfcfbfaf9f8f7f6f5f4f3 (5.07812e-299, -2.41385e+284) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x1211100f0e0d0c0b0a09080706050403 (1.18008e-221, 2.54377e-260) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x2221201f1e1d1c1b1a19181716151413 (2.74293e-144, 5.90574e-183) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0100fffefdfcfbfaf9f8f7f6f5f4f3f2 (7.74681e-304, -3.54087e+279) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x11100f0e0d0c0b0a0908070605040302 (1.69471e-226, 3.72581e-265) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x21201f1e1d1c1b1a1918171615141312 (3.94003e-149, 8.65093e-188) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x0000000000fffeffff0000850002ff01 (8.28892e-317, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x1f1e1d1c1b1a19181700000000000000 (8.56775e-159, 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x31302f2e2d2c2b2a2928272625242322 (9.15999e-72, 2.00864e-110) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x41403f3e3d3c3b3a3938373635343332 (2.12953e+06, 4.66377e-33) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x302f2e2d2c2b2a292827262524232221 (1.34639e-76, 2.93754e-115) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x403f3e3d3c3b3a393837363534333231 (31.2431, 6.82132e-38) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x0000000000fffeffff0000850002ff01 (8.28892e-317, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x504f4e4d4c4b4a494847464544434241 (7.24994e+78, 1.58398e+40) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x4f4e4d4c4b4a49484746454443424140 (1.07078e+74, 2.31271e+35) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x0000000000000000ff0000850002ff01 (..., -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x00000000000000000000000000fffeff (..., 0.00000, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x00000000000000001700000000000000 (..., 4.13590e-25, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x00000000000000001f1e1d1c1b1a1918 (..., 3.34819e-20, 1.27467e-22) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00000000000000005756555453525150 (..., 2.35662e+14, 9.03307e+11) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x00000000000000005f5e5d5c5b5a5958 (..., 1.60231e+19, 6.14598e+16) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000006766656463626160 (..., 1.08801e+24, 4.17598e+21) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x00000000000000006f6e6d6c6b6a6968 (..., 7.37897e+28, 2.83386e+26) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000565554535251504f (..., 5.86395e+13, 2.24749e+11) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x00000000000000005e5d5c5b5a595857 (..., 3.98768e+18, 1.52943e+16) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000000000666564636261605f (..., 2.70818e+23, 1.03937e+21) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x00000000000000006e6d6c6b6a696867 (..., 1.83698e+28, 7.05432e+25) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x0000000000000000ff0000850002ff01 (..., -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x00000000000000000000000000fffeff (..., 0.00000, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x00000000000000001700000000000000 (..., 4.13590e-25, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0000000000000000767574737271706f (..., 1.24460e+33, 4.78220e+30) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000007e7d7c7b7a797877 (..., 8.42353e+37, 3.23831e+35) <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x0000000000000000868584838281807f (..., -5.02237e-35, -1.90286e-37) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x00000000000000007574737271706f6e (..., 3.09878e+32, 1.19058e+30) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x00000000000000007d7c7b7a79787776 (..., 2.09754e+37, 8.06320e+34) <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x00000000000000008584838281807f7e (..., -1.24615e-35, -4.72027e-38) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x0000000000000000ff0000850002ff01 (..., -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x00000000000000000000000000fffeff (..., 0.00000, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x00000000000000008d8c8b8a89888786 (..., -8.66176e-31, -3.28683e-33) <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x00000000000000009594939291908f8e (..., -6.00095e-26, -2.28077e-28) <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x00000000000000008c8b8a8988878685 (..., -2.14997e-31, -8.15664e-34) <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x000000000000000094939291908f8e8d (..., -1.49010e-26, -5.66232e-29) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0000000000000000ff0000850002ff01 (..., -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x00000000000000009c9b9a9998979695 (..., -1.02970e-21, -3.91846e-24) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x00000000000000009b9a999897969594 (..., -2.55764e-22, -9.73128e-25) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000001700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000001f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x0000000000000000a3a2a1a09f9e9d9c <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x0000000000000000abaaa9a8a7a6a5a4 <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0000000000000000b3b2b1b0afaeadac <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000bbbab9b8b7b6b5b4 <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x0000000000000000a2a1a09f9e9d9c9b <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000000000aaa9a8a7a6a5a4a3 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000b2b1b0afaeadacab <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000bab9b8b7b6b5b4b3 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x00000000000000001700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x0000000000000000c2c1c0bfbebdbcbb <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0000000000000000cac9c8c7c6c5c4c3 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000d2d1d0cfcecdcccb <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000c1c0bfbebdbcbbba <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000c9c8c7c6c5c4c3c2 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x0000000000000000d1d0cfcecdcccbca <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000d9d8d7d6d5d4d3d2 <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000e1e0dfdedddcdbda <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x0000000000000000d8d7d6d5d4d3d2d1 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x0000000000000000e0dfdedddcdbdad9 <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x0000000000000000e8e7e6e5e4e3e2e1 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x0000000000000000e7e6e5e4e3e2e1e0 <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0000000000fffeffff0000850002ff01 (0.00000, 2.35095e-38, -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x1f1e1d1c1b1a19181700000000000000 (3.34819e-20, 1.27467e-22, 4.13590e-25, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x2f2e2d2c2b2a29282726252423222120 (1.58413e-10, 6.04532e-13, 2.30573e-15, 8.78905e-18) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x3f3e3d3c3b3a39383736353433323130 (0.743122, 0.00284155, 1.08604e-05, 4.14886e-08) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0xf7f6f5f4f3f2f1f0efeeedecebeae9e8 (-1.00179e+34, -3.84962e+31, -1.47890e+29, -5.67986e+26) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0706050403020100fffefdfcfbfaf9f8 (1.00825e-34, 3.82047e-37, -nan, -2.60629e+36) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x17161514131211100f0e0d0c0b0a0908 (4.84942e-25, 1.84362e-27, 7.00365e-30, 2.65846e-32) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x27262524232221201f1e1d1c1b1a1918 (2.30573e-15, 8.78905e-18, 3.34819e-20, 1.27467e-22) <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0xf6f5f4f3f2f1f0efeeedecebeae9e8e7 (-2.49430e+33, -9.58428e+30, -3.68172e+28, -1.41390e+26) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x06050403020100fffefdfcfbfaf9f8f7 (2.50175e-35, 9.47771e-38, -1.68804e+38, -6.48966e+35) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x161514131211100f0e0d0c0b0a090807 (1.20425e-25, 4.57737e-28, 1.73854e-30, 6.59782e-33) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x262524232221201f1e1d1c1b1a191817 (5.72948e-16, 2.18366e-18, 8.31732e-21, 3.16591e-23) <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000fffeffff0000850002ff01 (0.00000, 2.35095e-38, -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x1f1e1d1c1b1a19181700000000000000 (3.34819e-20, 1.27467e-22, 4.13590e-25, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x2f2e2d2c2b2a29282726252423222120 (1.58413e-10, 6.04532e-13, 2.30573e-15, 8.78905e-18) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x363534333231302f2e2d2c2b2a292827 (2.70015e-06, 1.03137e-08, 3.93749e-11, 1.50241e-13) <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x464544434241403f3e3d3c3b3a393837 (12625.1, 48.3127, 0.184800, 0.000706557) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x565554535251504f4e4d4c4b4a494847 (5.86395e+13, 2.24749e+11, 8.61082e+08, 3.29781e+06) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x3534333231302f2e2d2c2b2a29282726 (6.71297e-07, 2.56382e-09, 9.78665e-12, 3.73374e-14) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x4544434241403f3e3d3c3b3a39383736 (3140.20, 12.0154, 0.0459549, 0.000175682) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x5554535251504f4e4d4c4b4a49484746 (1.45909e+13, 5.59177e+10, 2.14218e+08, 820340.) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x0000000000fffeffff0000850002ff01 (0.00000, 2.35095e-38, -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x1f1e1d1c1b1a19181700000000000000 (3.34819e-20, 1.27467e-22, 4.13590e-25, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x6564636261605f5e5d5c5b5a59585756 (6.74083e+22, 2.58684e+20, 9.92399e+17, 3.80591e+15) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x7574737271706f6e6d6c6b6a69686766 (3.09878e+32, 1.19058e+30, 4.57302e+27, 1.75599e+25) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x64636261605f5e5d5c5b5a5958575655 (1.67780e+22, 6.43816e+19, 2.46969e+17, 9.47063e+14) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x74737271706f6e6d6c6b6a6968676665 (7.71514e+31, 2.96402e+29, 1.13840e+27, 4.37102e+24) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x0000000000fffeffff0000850002ff01 (0.00000, 2.35095e-38, -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x84838281807f7e7d7c7b7a7978777675 (-3.09178e-36, -1.17085e-38, 5.22300e+36, 2.00766e+34) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x838281807f7e7d7c7b7a797877767574 (-7.67045e-37, 3.38275e+38, 1.30054e+36, 4.99878e+33) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000001700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x00000000000000001f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x00000000000000008b8a898887868584 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x0000000000000000939291908f8e8d8c <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000009b9a999897969594 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0000000000000000a3a2a1a09f9e9d9c <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000008a89888786858483 <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x00000000000000009291908f8e8d8c8b <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x00000000000000009a99989796959493 <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000000000a2a1a09f9e9d9c9b <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000001700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000000000aaa9a8a7a6a5a4a3 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000b2b1b0afaeadacab <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000bab9b8b7b6b5b4b3 <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000000000a9a8a7a6a5a4a3a2 <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x0000000000000000b1b0afaeadacabaa <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x0000000000000000b9b8b7b6b5b4b3b2 <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x0000000000000000c1c0bfbebdbcbbba <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000000000c9c8c7c6c5c4c3c2 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000c0bfbebdbcbbbab9 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x0000000000000000c8c7c6c5c4c3c2c1 <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x0000000000000000d0cfcecdcccbcac9 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x0000000000000000cfcecdcccbcac9c8 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x2f2e2d2c2b2a29282726252423222120 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x3f3e3d3c3b3a39383736353433323130 <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0xdfdedddcdbdad9d8d7d6d5d4d3d2d1d0 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0xefeeedecebeae9e8e7e6e5e4e3e2e1e0 <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0xfffefdfcfbfaf9f8f7f6f5f4f3f2f1f0 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x0f0e0d0c0b0a09080706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0xdedddcdbdad9d8d7d6d5d4d3d2d1d0cf <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0xeeedecebeae9e8e7e6e5e4e3e2e1e0df <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0xfefdfcfbfaf9f8f7f6f5f4f3f2f1f0ef <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x0e0d0c0b0a09080706050403020100ff <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x2f2e2d2c2b2a29282726252423222120 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x1e1d1c1b1a191817161514131211100f <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x2e2d2c2b2a292827262524232221201f <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x3e3d3c3b3a393837363534333231302f <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x1d1c1b1a191817161514131211100f0e <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x2d2c2b2a292827262524232221201f1e <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x3d3c3b3a393837363534333231302f2e <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x4d4c4b4a494847464544434241403f3e <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x5d5c5b5a595857565554535251504f4e <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x4c4b4a494847464544434241403f3e3d <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x5c5b5a595857565554535251504f4e4d <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x6c6b6a696867666564636261605f5e5d <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x6b6a696867666564636261605f5e5d5c <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x3d3c3b3a39383736353433323130012e <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0xfefdfcfbfaf9f8f7f6f5f4f36cf1f0ef <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x6c6b6a6b6867666564636261605f5e5d <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0xff0000850002ff01d6d5d4d3d2d1d0cf (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x737271706f6e6d6c636261605f5e5d5c (1.28953e+248, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x7271706f6e6d6c6b2726252423222120 (1.86056e+243, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x3d3c3b3aff013736353433323130012e <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0xff0000850002ff01d6d5d4d37473d0cf <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x5c5b5a595857737254535251504f4e4d <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x4d4c4b4a0002ff014544434241403f3e (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x0e0d0c0b7776757406050403020100ff (..., 4.99878e+33, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x0000000076757473e8e7e6e5e4e3e2e1 (..., 1.24460e+33, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x01010101010101010101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x77777777777777777777777777777777 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x76767676767676767676767676767676 <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x0000000000000000ff0000850002ff01 (d25: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000007e7d7c7b7a797877 (d9: 1.97467e+301) <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x00000000000000007d7c7b7a79787776 (d23: 2.91053e+296) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0xff0000850002ff01ff0000850002ff01 (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x8584838281807f7e8584838281807f7e (-4.41447e-282, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x84838281807f7e7d84838281807f7e7d (-6.40629e-287, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00000000000000000002ff010002ff01 (s24: 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000008887868588878685 (s26: -8.15664e-34) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x00000000000000008786858487868584 (s28: -2.02406e-34) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x0000000000000000ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x00000000000000008988898889888988 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x00000000000000008887888788878887 <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x0002ff010002ff010002ff010002ff01 (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x8c8b8a898c8b8a898c8b8a898c8b8a89 (..., -2.14997e-31, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x8b8a89888b8a89888b8a89888b8a8988 (..., -5.33626e-32, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000000101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x00000000000000008c8c8c8c8c8c8c8c <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000008b8b8b8b8b8b8b8b <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0xff01ff01ff01ff01ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x8d8c8d8c8d8c8d8c8d8c8d8c8d8c8d8c <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x8c8b8c8b8c8b8c8b8c8b8c8b8c8b8c8b <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x1e1c1a18000000000000ffff00850201 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x1f1d1b1917000000000000feff0000ff <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0xaba9a7a5a3a19f9d9b99979593918f8d <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0xacaaa8a6a4a2a09e9c9a98969492908e <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0xaaa8a6a4a2a09e9c9a98969492908e8c <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0xaba9a7a5a3a19f9d9b99979593918f8d <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x1700000000000000ff0000850002ff01 (6.68887e-198, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x1f1e1d1c1b1a19180000000000fffeff (8.56775e-159, 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0xc3c2c1c0bfbebdbcb3b2b1b0afaeadac (-2.70315e+18, -1.16334e-59) <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0xcbcac9c8c7c6c5c4bbbab9b8b7b6b5b4 (-1.31369e+57, -5.65934e-21) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0xc2c1c0bfbebdbcbbb2b1b0afaeadacab (-3.90391e+13, -1.67978e-64) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0xcac9c8c7c6c5c4c3bab9b8b7b6b5b4b3 (-1.92941e+52, -8.31108e-26) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x000000000000000000fffeff0002ff01 (..., 2.35095e-38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x000000000000000000000000ff000085 (..., 0.00000, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000000000d6d5d4d3cecdcccb (..., -1.17555e+14, -1.72638e+09) <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000dad9d8d7d2d1d0cf (..., -3.06592e+16, -4.50576e+11) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000000000d5d4d3d2cdcccbca (..., -2.92508e+13, -4.29488e+08) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x0000000000000000d9d8d7d6d1d0cfce (..., -7.62949e+15, -1.12105e+11) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000000000feff0085ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x0000000000000000000000ffff000002 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x0000000000000000e7e6e3e2dfdedbda <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x0000000000000000e9e8e5e4e1e0dddc <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x0000000000000000e6e5e2e1dedddad9 <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000000000e8e7e4e3e0dfdcdb <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x1b1a19180000000000fffeff0002ff01 (1.27467e-22, 0.00000, 2.35095e-38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x1f1e1d1c1700000000000000ff000085 (3.34819e-20, 4.13590e-25, 0.00000, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x04030201fcfbfaf9f4f3f2f1ecebeae9 (1.53999e-36, -1.04669e+37, -1.54621e+32, -2.28166e+27) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x0807060500fffefdf8f7f6f5f0efeeed (4.06322e-34, 2.35095e-38, -4.02346e+34, -5.94046e+29) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x03020100fbfaf9f8f3f2f1f0ebeae9e8 (3.82047e-37, -2.60629e+36, -3.84962e+31, -5.67986e+26) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x07060504fffefdfcf7f6f5f4efeeedec (1.00825e-34, -nan, -1.00179e+34, -1.47890e+29) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000000000ffff00850201 <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x0000000000000000000000feff0000ff <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x0000000000000000161412100e0c0a08 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x0000000000000000171513110f0d0b09 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000001513110f0d0b0907 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0000000000000000161412100e0c0a08 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x1d1c1918000000000000feff0085ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x1f1e1b1a17000000000000ffff000002 <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x3433302f2c2b28272423201f1c1b1817 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x363532312e2d2a29262522211e1d1a19 <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x33322f2e2b2a272623221f1e1b1a1716 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x353431302d2c2928252421201d1c1918 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x363532012e2d2a29262522211e1d1a19 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x1f1e1dff1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x4544434241403f3e363c3b3a39383736 <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000003700ffff00850201 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0706050403020100fffefdfcfb35f9f8 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x1d1c1918000000000000feff0036ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0xff0000850002ff01f8f7f6f5f0efeeed (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000fffeffd5d4d3d2cdcccbca (8.28892e-317, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000003e3d3c3b3a393837 (d26: 6.80687e-09) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000464544434241403f (d27: 3.36984e+30) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x07060504fffefdfc3d3c3b3a39383736 (d25: 1.00298e-13) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000004544434241403f3e (d26: 4.89923e+25) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0xff01000000000000000000feff0000ff <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00020000000000008b8b8b8b8b8b8b8b <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000474600003700ffff00850201 <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0xff01000049480000000000feff0000ff <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x1d1c191800000000000046450036ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x1f1e1b1a1700000000004847ff000002 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0002ff0103020100fffefdfcfb35f9f8 (2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0xff00008500000000000046450036ff01 (-1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x0000000000000000000000004c4b4a49 (s28: 5.32913e+07) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0002ff0103020100fffefdfc504f4e4d (s29: 1.39121e+10) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x1f1e1dff1b1a19184b4a494800000000 (..., 1.32570e+07, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000004f4e4d4c0d0b0907 (..., 3.46117e+09, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x01010101010101010101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0xffffffffffffffffffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x50505050505050505050505050505050 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x51515151515151515151515151515151 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x4f4f4f4f4f4f4f4f4f4f4f4f4f4f4f4f <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x50505050505050505050505050505050 <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0000000000000000ff0000850002ff01 (d26: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x00000000000000000000000000fffeff (d27: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x00000000000000005857565554535251 (d14: 3.67814e+117) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x0000000000000000605f5e5d5c5b5a59 (d15: 1.68234e+156) <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x00000000000000005756555453525150 (d23: 5.37096e+112) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00000000000000005f5e5d5c5b5a5958 (d24: 2.48489e+151) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0xff0000850002ff01ff0000850002ff01 (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000fffeff0000000000fffeff (8.28892e-317, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x67666564636261606766656463626160 (1.24732e+190, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x6f6e6d6c6b6a69686f6e6d6c6b6a6968 (5.76650e+228, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x666564636261605f666564636261605f (1.81795e+185, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x6e6d6c6b6a6968676e6d6c6b6a696867 (8.50866e+223, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000000002ff010002ff01 (s26: 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000ff000085ff000085 (s27: -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x00000000000000007271706f7271706f (s22: 4.78220e+30) <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x00000000000000007675747376757473 (s23: 1.24460e+33) <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x000000000000000071706f6e71706f6e (s2: 1.19058e+30) <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x00000000000000007574737275747372 (s3: 3.09878e+32) <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000000000ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x00000000000000000002000200020002 <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000007776777677767776 <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x00000000000000007978797879787978 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000007675767576757675 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000007877787778777877 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x0002ff010002ff010002ff010002ff01 (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0xff000085ff000085ff000085ff000085 (..., -1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x7c7b7a797c7b7a797c7b7a797c7b7a79 (..., 5.22300e+36, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x807f7e7d807f7e7d807f7e7d807f7e7d (..., -1.17085e-38, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x7b7a79787b7a79787b7a79787b7a7978 (..., 1.30054e+36, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x7f7e7d7c7f7e7d7c7f7e7d7c7f7e7d7c (..., 3.38275e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000000101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000ffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x00000000000000008080808080808080 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x00000000000000008181818181818181 <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x00000000000000007f7f7f7f7f7f7f7f <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x00000000000000008080808080808080 <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0xff01ff01ff01ff01ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x00020002000200020002000200020002 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x82818281828182818281828182818281 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x84838483848384838483848384838483 <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x81808180818081808180818081808180 <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x83828382838283828382838283828382 <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x2d2a2724211e1b1800000000fe000001 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x2e2b2825221f1c1900000000ffff85ff <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x2f2c292623201d1a1700000000ff0002 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0xb1aeaba8a5a29f9c999693908d8a8784 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0xb2afaca9a6a3a09d9a9794918e8b8885 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0xb3b0adaaa7a4a19e9b9895928f8c8986 <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0xb0adaaa7a4a19e9b9895928f8c898683 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0xb1aeaba8a5a29f9c999693908d8a8784 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0xb2afaca9a6a3a09d9a9794918e8b8885 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x1f1e1d1c1b1a1918ff0000850002ff01 (8.56775e-159, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x27262524232221200000000000fffeff (4.28794e-120, 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x2f2e2d2c2b2a29281700000000000000 (1.98829e-81, 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0xd2d1d0cfcecdcccbbab9b8b7b6b5b4b3 (-9.07279e+90, -8.31108e-26) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0xdad9d8d7d6d5d4d3c2c1c0bfbebdbcbb (-4.47908e+129, -3.90391e+13) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0xe2e1e0dfdedddcdbcac9c8c7c6c5c4c3 (-2.10851e+168, -1.92941e+52) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0xd1d0cfcecdcccbcab9b8b7b6b5b4b3b2 (-1.30639e+86, -1.21867e-30) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0xd9d8d7d6d5d4d3d2c1c0bfbebdbcbbba (-6.56908e+124, -5.62003e+08) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0xe1e0dfdedddcdbdac9c8c7c6c5c4c3c2 (-3.03668e+163, -2.82942e+47) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x0000000000000000000000000002ff01 (..., 0.00000, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x000000000000000000000000ff000085 (..., 0.00000, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000001700000000fffeff (..., 4.13590e-25, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x0000000000000000f1f0efeee5e4e3e2 (..., -2.38613e+30, -1.35113e+23) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x0000000000000000f5f4f3f2e9e8e7e6 (..., -6.21029e+32, -3.51957e+25) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x0000000000000000f9f8f7f6edecebea (..., -1.61590e+35, -9.16546e+27) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0000000000000000f0efeeede4e3e2e1 (..., -5.94046e+29, -3.36301e+22) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000f4f3f2f1e8e7e6e5 (..., -1.54621e+32, -8.76101e+24) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x0000000000000000f8f7f6f5ecebeae9 (..., -4.02346e+34, -2.28166e+27) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x000000000000000000000000ff00ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x000000000000000000000000feff0002 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x00000000000000001700000000ff0085 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x00000000000000000c0b060500fffaf9 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x00000000000000000e0d08070201fcfb <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x0000000000000000100f0a090403fefd <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000000b0a0504fffef9f8 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00000000000000000d0c07060100fbfa <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000000f0e09080302fdfc <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x272625241b1a1918000000000002ff01 (2.30573e-15, 1.27467e-22, 0.00000, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x2b2a29281f1e1d1c00000000ff000085 (6.04532e-13, 3.34819e-20, 0.00000, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x2f2e2d2c232221201700000000fffeff (1.58413e-10, 8.78905e-18, 4.13590e-25, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x373635342b2a29281f1e1d1c13121110 (1.08604e-05, 6.04532e-13, 3.34819e-20, 1.84362e-27) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x3b3a39382f2e2d2c2322212017161514 (0.00284155, 1.58413e-10, 8.78905e-18, 4.84942e-25) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x3f3e3d3c33323130272625241b1a1918 (0.743122, 4.14886e-08, 2.30573e-15, 1.27467e-22) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x363534332a2928271e1d1c1b1211100f (2.70015e-06, 1.50241e-13, 8.31732e-21, 4.57737e-28) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x3a3938372e2d2c2b2221201f16151413 (0.000706557, 3.93749e-11, 2.18366e-18, 1.20425e-25) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x3e3d3c3b3231302f262524231a191817 (0.184800, 1.03137e-08, 5.72948e-16, 3.16591e-23) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x000000000000000000000000fe000001 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x000000000000000000000000ffff85ff <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x00000000000000001700000000ff0002 <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x000000000000000054514e4b4845423f <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x000000000000000055524f4c49464340 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x00000000000000005653504d4a474441 <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x000000000000000053504d4a4744413e <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x000000000000000054514e4b4845423f <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x000000000000000055524f4c49464340 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x2b2a25241f1e191800000000ff00ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x2d2c272621201b1a00000000feff0002 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x2f2e292823221d1c1700000000ff0085 <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x81807b7a75746f6e696863625d5c5756 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x83827d7c777671706b6a65645f5e5958 <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x85847f7e797873726d6c676661605b5a <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x807f7a7974736e6d686762615c5b5655 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x82817c7b7675706f6a6964635e5d5857 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x84837e7d787772716c6b6665605f5a59 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x0000000001000000f5f4f3f2e9e8e7e6 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x2b2a2524ff1e191800000000ff00ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x2d2c272602201b1a00000000feff0002 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x4f4f4f4f4f4f854f4f4f4f4f4f4f4f4f <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x82818281828186818281828182818281 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000087000b0a0504fffef9f8 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x2d2c272602201b1a00000000feff0084 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x2f2e292823221d1c1700000000ff0085 <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x3b3a39382f2e2d2c2322212017161586 <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x6e6d6c6b6a696867ff0000850002ff01 (d16: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000474600000000000000fffeff (d17: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0xd2d1d0cfcecdcccb1700000000000000 (d18: 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x84837e7d787772718e8d8c8b8a898887 (d30: -1.41807e-238) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x0000000000000000969594939291908f (d31: -7.04826e-200) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0xc3c2c1c0bfbebdbc9e9d9c9b9a999897 (d0: -3.29099e-161) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x8d8c8b8a89888786686762615c5b5655 (-2.09028e-243, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x9594939291908f8e6a6964635e5d5857 (-1.02545e-204, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x9d9c9b9a999897968e8d8c8b8a898887 (-4.85140e-166, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x81807b7a75746f6e6968ff015d5c5756 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x83827d7c777671706b6a00025f5e5958 <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x85847f7e797873726d6c008561605b5a <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x9f9e2524ff1e191800000000ff00ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0xa1a0272602201b1a00000000feff0084 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0xa3a2292823221d1c1700000000ff0085 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x83827d7c777671709e9d00025f5e5958 <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x85847f7e79787372a09f008561605b5a <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x6e6d6c6b6a696867a2a100850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x0002ff01ff1e191800000000ff00ff01 (2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0xff00008502201b1a00000000feff0084 (-1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00fffeff23221d1c1700000000ff0085 (2.35095e-38, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x9d9c9b9aa6a5a4a38e8d8c8b8a898887 (..., -1.14938e-15, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x00000000aaa9a8a7969594939291908f (..., -3.01375e-13, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0xc3c2c1c0aeadacab9e9d9c9b9a999897 (..., -7.89780e-11, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000000000a5a4a3a24744413e (..., -2.85603e-16, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x81807b7a75746f6ea9a8a7a65d5c5756 (..., -7.48978e-14, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x83827d7c77767170adacabaa5f5e5958 (..., -1.96304e-11, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x01010101010101010101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0xffffffffffffffffffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x02020202020202020202020202020202 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0xaeaeaeaeaeaeaeaeaeaeaeaeaeaeaeae <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0xafafafafafafafafafafafafafafafaf <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0xb0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0xadadadadadadadadadadadadadadadad <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0xaeaeaeaeaeaeaeaeaeaeaeaeaeaeaeae <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0xafafafafafafafafafafafafafafafaf <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000ff0000850002ff01 (d4: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x00000000000000000000000000fffeff (d5: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000001700000000000000 (d6: 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x0000000000000000b7b6b5b4b3b2b1b0 (d7: -2.60696e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0000000000000000bfbebdbcbbbab9b8 (d8: -0.120083) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x0000000000000000c7c6c5c4c3c2c1c0 (d9: -6.05398e+37) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x0000000000000000b6b5b4b3b2b1b0af (d17: -3.80205e-45) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x0000000000000000bebdbcbbbab9b8b7 (d18: -1.77248e-06) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x0000000000000000c6c5c4c3c2c1c0bf (d19: -8.83040e+32) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0xff0000850002ff01ff0000850002ff01 (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x0000000000fffeff0000000000fffeff (8.28892e-317, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x17000000000000001700000000000000 (6.68887e-198, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0xcecdcccbcac9c8c7cecdcccbcac9c8c7 (-4.11344e+71, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0xd6d5d4d3d2d1d0cfd6d5d4d3d2d1d0cf (-2.05087e+110, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0xdedddcdbdad9d8d7dedddcdbdad9d8d7 (-9.54613e+148, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0xcdcccbcac9c8c7c6cdcccbcac9c8c7c6 (-6.06516e+66, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0xd5d4d3d2d1d0cfced5d4d3d2d1d0cfce (-2.98548e+105, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0xdddcdbdad9d8d7d6dddcdbdad9d8d7d6 (-1.40766e+144, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x00000000000000000002ff010002ff01 (s10: 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x0000000000000000ff000085ff000085 (s11: -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x000000000000000000fffeff00fffeff (s12: 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x0000000000000000e1e0dfdee1e0dfde (s0: -5.18525e+20) <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x0000000000000000e5e4e3e2e5e4e3e2 (s1: -1.35113e+23) <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000000000e9e8e7e6e9e8e7e6 (s2: -3.51957e+25) <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x0000000000000000e0dfdedde0dfdedd (s23: -1.29053e+20) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x0000000000000000e4e3e2e1e4e3e2e1 (s24: -3.36301e+22) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x0000000000000000e8e7e6e5e8e7e6e5 (s25: -8.76101e+24) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x0000000000000000ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x00000000000000000002000200020002 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00000000000000000085008500850085 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x0000000000000000eae9eae9eae9eae9 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x0000000000000000ecebecebecebeceb <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0000000000000000eeedeeedeeedeeed <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x0000000000000000e9e8e9e8e9e8e9e8 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0000000000000000ebeaebeaebeaebea <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x0000000000000000edecedecedecedec <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0002ff010002ff010002ff010002ff01 (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0xff000085ff000085ff000085ff000085 (..., -1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x00fffeff00fffeff00fffeff00fffeff (..., 2.35095e-38, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0xf1f0efeef1f0efeef1f0efeef1f0efee (..., -2.38613e+30, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0xf5f4f3f2f5f4f3f2f5f4f3f2f5f4f3f2 (..., -6.21029e+32, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0xf9f8f7f6f9f8f7f6f9f8f7f6f9f8f7f6 (..., -1.61590e+35, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0xf0efeeedf0efeeedf0efeeedf0efeeed (..., -5.94046e+29, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0xf4f3f2f1f4f3f2f1f4f3f2f1f4f3f2f1 (..., -1.54621e+32, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0xf8f7f6f5f8f7f6f5f8f7f6f5f8f7f6f5 (..., -4.02346e+34, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x00000000000000000101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000ffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x00000000000000000202020202020202 <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x0000000000000000f9f9f9f9f9f9f9f9 <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x0000000000000000fafafafafafafafa <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000000000fbfbfbfbfbfbfbfb <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x0000000000000000f8f8f8f8f8f8f8f8 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000000000f9f9f9f9f9f9f9f9 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x0000000000000000fafafafafafafafa <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0xff01ff01ff01ff01ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00020002000200020002000200020002 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00850085008500850085008500850085 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0xfcfbfcfbfcfbfcfbfcfbfcfbfcfbfcfb <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0xfefdfefdfefdfefdfefdfefdfefdfefd <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x00ff00ff00ff00ff00ff00ff00ff00ff <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0xfbfafbfafbfafbfafbfafbfafbfafbfa <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0xfdfcfdfcfdfcfdfcfdfcfdfcfdfcfdfc <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0xfffefffefffefffefffefffefffefffe <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x3c3834302c2824201c18000000ff8501 <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x3d3935312d2925211d19000000fe00ff <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x3e3a36322e2a26221e1a000000ff0002 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x3f3b37332f2b27231f1b17000000ff00 <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x3c3834302c2824201c1814100c080400 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x3d3935312d2925211d1915110d090501 <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x3e3a36322e2a26221e1a16120e0a0602 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x3f3b37332f2b27231f1b17130f0b0703 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x3b37332f2b27231f1b17130f0b0703ff <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x3c3834302c2824201c1814100c080400 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x3d3935312d2925211d1915110d090501 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x3e3a36322e2a26221e1a16120e0a0602 <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x2726252423222120ff0000850002ff01 (4.28794e-120, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x2f2e2d2c2b2a29280000000000fffeff (1.98829e-81, 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x37363534333231301700000000000000 (9.95833e-43, 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x3f3e3d3c3b3a39381f1e1d1c1b1a1918 (0.000461414, 8.56775e-159) <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x666564636261605f464544434241403f (1.81795e+185, 3.36984e+30) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x6e6d6c6b6a6968674e4d4c4b4a494847 (8.50866e+223, 1.57975e+69) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x767574737271706f565554535251504f (4.22243e+262, 7.82703e+107) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x7e7d7c7b7a7978775e5d5c5b5a595857 (1.97467e+301, 3.66628e+146) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x6564636261605f5e4544434241403f3e (2.64379e+180, 4.89923e+25) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x6d6c6b6a696867664d4c4b4a49484746 (1.25402e+219, 2.32790e+64) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x7574737271706f6e5554535251504f4e (6.14144e+257, 1.13810e+103) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x7d7c7b7a797877765d5c5b5a59585756 (2.91053e+296, 5.40301e+141) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000000000000002ff01 (..., 0.00000, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x000000000000000017000000ff000085 (..., 4.13590e-25, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x00000000000000001b1a191800fffeff (..., 1.27467e-22, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x00000000000000001f1e1d1c00000000 (..., 3.34819e-20, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x000000000000000091908f8e81807f7e (..., -2.28077e-28, -4.72027e-38) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x00000000000000009594939285848382 (..., -6.00095e-26, -1.24615e-35) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000009998979689888786 (..., -1.57777e-23, -3.28683e-33) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x00000000000000009d9c9b9a8d8c8b8a (..., -4.14537e-21, -8.66176e-31) <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000908f8e8d807f7e7d (..., -5.66232e-29, -1.17085e-38) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x00000000000000009493929184838281 (..., -1.49010e-26, -3.09178e-36) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000009897969588878685 (..., -3.91846e-24, -8.15664e-34) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000009c9b9a998c8b8a89 (..., -1.02970e-21, -2.14997e-31) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x000000000000000019180000feffff01 <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000001b1a000000ff0002 <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000001d1c000000000085 <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000001f1e17000000ff00 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x0000000000000000b6b5aeada6a59e9d <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x0000000000000000b8b7b0afa8a7a09f <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x0000000000000000bab9b2b1aaa9a2a1 <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0000000000000000bcbbb4b3acaba4a3 <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000000000b5b4adaca5a49d9c <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000b7b6afaea7a69f9e <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000b9b8b1b0a9a8a1a0 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x0000000000000000bbbab3b2abaaa3a2 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x3332313023222120000000000002ff01 (4.14886e-08, 8.78905e-18, 0.00000, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x373635342726252417000000ff000085 (1.08604e-05, 2.30573e-15, 4.13590e-25, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x3b3a39382b2a29281b1a191800fffeff (0.00284155, 6.04532e-13, 1.27467e-22, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x3f3e3d3c2f2e2d2c1f1e1d1c00000000 (0.743122, 1.58413e-10, 3.34819e-20, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0xefeeedecdfdedddccfcecdccbfbebdbc (-1.47890e+29, -3.21185e+19, -6.93919e+09, -1.49017) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0xf3f2f1f0e3e2e1e0d3d2d1d0c3c2c1c0 (-3.84962e+31, -8.37048e+21, -1.81093e+12, -389.514) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0xf7f6f5f4e7e6e5e4d7d6d5d4c7c6c5c4 (-1.00179e+34, -2.18077e+24, -4.72428e+14, -101772.) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0xfbfaf9f8ebeae9e8dbdad9d8cbcac9c8 (-2.60629e+36, -5.67986e+26, -1.23202e+17, -2.65799e+07) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0xeeedecebdedddcdbcecdcccbbebdbcbb (-3.68172e+28, -7.99345e+18, -1.72638e+09, -0.370581) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0xf2f1f0efe2e1e0dfd2d1d0cfc2c1c0bf (-9.58428e+30, -2.08336e+21, -4.50576e+11, -96.8765) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0xf6f5f4f3e6e5e4e3d6d5d4d3c6c5c4c3 (-2.49430e+33, -5.42822e+23, -1.17555e+14, -25314.4) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0xfaf9f8f7eae9e8e7dad9d8d7cac9c8c7 (-6.48966e+35, -1.41390e+26, -3.06592e+16, -6.61207e+06) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x00000000000000001c18000000ff8501 <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x00000000000000001d19000000fe00ff <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000001e1a000000ff0002 <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000001f1b17000000ff00 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x000000000000000017130f0b0703fffb <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x00000000000000001814100c080400fc <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x00000000000000001915110d090501fd <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x00000000000000001a16120e0a0602fe <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x000000000000000016120e0a0602fefa <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x000000000000000017130f0b0703fffb <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000001814100c080400fc <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00000000000000001915110d090501fd <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x393831302928212019180000feffff01 <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x3b3a33322b2a23221b1a000000ff0002 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x3d3c35342d2c25241d1c000000000085 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x3f3e37362f2e27261f1e17000000ff00 <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x53524b4a43423b3a33322b2a23221b1a <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x55544d4c45443d3c35342d2c25241d1c <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x57564f4e47463f3e37362f2e27261f1e <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x59585150494841403938313029282120 <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x52514a4942413a3932312a2922211a19 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x54534c4b44433c3b34332c2b24231c1b <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x56554e4d46453e3d36352e2d26251e1d <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x5857504f4847403f3837302f2827201f <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x52514a4942413a3932312a2901211a19 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x54534c4b44433c3b34332c2bff231c1b <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x56554e4d46453e3d36352e2d02251e1d <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x5857504f4847403f3837302f0027201f <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000000000fbfbfbfb59fbfbfb <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x81807b7a75746f6ea9a8a7a65a5c5756 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0xcdcccbcac9c8c7c6cdcccbca5bc8c7c6 <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x00000000000000001c1800005cff8501 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x3d3c35342d2c25241d58000000000085 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x3f3e37362f2e27261f5917000000ff00 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000000000195a110d090501fd <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x00000000000000001a5b120e0a0602fe <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0xff0000850002ff011f5917000000ff00 (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000fffeff195a110d090501fd (8.28892e-317, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x17000000000000001a5b120e0a0602fe (6.68887e-198, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x1f1e1d1c1b1a1918d6d5d4d3c6c5c4c3 (8.56775e-159, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x636261605f5e5d5c1c1800005cff8501 (5.54935e+170, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x6b6a6968676665641d19000000fe00ff (2.71346e+209, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x737271706f6e6d6c1e1a000000ff0002 (1.28953e+248, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x7b7a7978777675741f1b17000000ff00 (6.29888e+286, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x6261605f5e5d5c5b1d19000000fe00ff (8.00514e+165, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x6a696867666564631e1a000000ff0002 (3.98304e+204, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x7271706f6e6d6c6b1f1b17000000ff00 (1.86056e+243, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x7a797877767574731f1e17000000ff00 (9.24687e+281, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x5352ff0143423b3a33322b2a23221b1a <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x5554000245443d3c35342d2c25241d1c <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x5756008547463f3e37362f2e27261f1e <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x5958ff00494841403938313029282120 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x5958ff00494841407c7b313029282120 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000007e7d0f0b0703fffb <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x0000000000000000807f100c080400fc <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00000000000000008281110d090501fd <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00007b7a00000000807f100c080400fc <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00007d7c000000008281110d090501fd <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x3b3a7f7e2b2a29281b1a191800fffeff <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x3f3e81802f2e2d2c1f1e1d1c00000000 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000000002ff010703fffb (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00007b7a00000000ff000085080400fc (..., -1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00007d7c0000000000fffeff090501fd (..., 2.35095e-38, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x3b3a7f7e2b2a29280000000000fffeff (..., 0.00000, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x393831308584838219180000feffff01 (..., -1.24615e-35, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x3b3a3332898887861b1a000000ff0002 (..., -3.28683e-33, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x3d3c35348d8c8b8a1d58000000000085 (..., -8.66176e-31, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0xff00008591908f8e1f5917000000ff00 (..., -2.28077e-28, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x848382810000000000fffeff090501fd (-3.09178e-36, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x888786852b2a29280000000000fffeff (-8.15664e-34, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x8c8b8a892f2e2d2c1f1e1d1c00000000 (-2.14997e-31, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x908f8e8d00000000fafafafafafafafa (-5.66232e-29, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x01010101010101010101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0xffffffffffffffffffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x02020202020202020202020202020202 <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x91919191919191919191919191919191 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x92929292929292929292929292929292 <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x93939393939393939393939393939393 <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x94949494949494949494949494949494 <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x90909090909090909090909090909090 <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x91919191919191919191919191919191 <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x92929292929292929292929292929292 <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x93939393939393939393939393939393 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0000000000000000ff0000850002ff01 (d8: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000000000000000fffeff (d9: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x00000000000000001700000000000000 (d10: 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x00000000000000001f1e1d1c1b1a1918 (d11: 8.56775e-159) <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x00000000000000009b9a999897969594 (d4: -1.05028e-175) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x0000000000000000a3a2a1a09f9e9d9c (d5: -5.00653e-137) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x0000000000000000abaaa9a8a7a6a5a4 (d6: -2.43801e-98) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x0000000000000000b3b2b1b0afaeadac (d7: -1.16334e-59) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000009a99989796959493 (d26: -1.54211e-180) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000a2a1a09f9e9d9c9b (d27: -7.22772e-142) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x0000000000000000aaa9a8a7a6a5a4a3 (d28: -3.58004e-103) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000000000b2b1b0afaeadacab (d29: -1.67978e-64) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0xff0000850002ff01ff0000850002ff01 (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x0000000000fffeff0000000000fffeff (8.28892e-317, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x17000000000000001700000000000000 (6.68887e-198, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x1f1e1d1c1b1a19181f1e1d1c1b1a1918 (8.56775e-159, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0xbab9b8b7b6b5b4b3bab9b8b7b6b5b4b3 (-8.31108e-26, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0xc2c1c0bfbebdbcbbc2c1c0bfbebdbcbb (-3.90391e+13, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0xcac9c8c7c6c5c4c3cac9c8c7c6c5c4c3 (-1.92941e+52, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0xd2d1d0cfcecdcccbd2d1d0cfcecdcccb (-9.07279e+90, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0xb9b8b7b6b5b4b3b2b9b8b7b6b5b4b3b2 (-1.21867e-30, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0xc1c0bfbebdbcbbbac1c0bfbebdbcbbba (-5.62003e+08, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0xc9c8c7c6c5c4c3c2c9c8c7c6c5c4c3c2 (-2.82942e+47, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0xd1d0cfcecdcccbcad1d0cfcecdcccbca (-1.30639e+86, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x00000000000000000002ff010002ff01 (s31: 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x0000000000000000ff000085ff000085 (s0: -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x000000000000000000fffeff00fffeff (s1: 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x00000000000000000000000000000000 (s2: 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x0000000000000000d5d4d3d2d5d4d3d2 (s28: -2.92508e+13) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000000000d9d8d7d6d9d8d7d6 (s29: -7.62949e+15) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x0000000000000000dddcdbdadddcdbda (s30: -1.98932e+18) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x0000000000000000e1e0dfdee1e0dfde (s31: -5.18525e+20) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x0000000000000000d4d3d2d1d4d3d2d1 (s11: -7.27820e+12) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000000000d8d7d6d5d8d7d6d5 (s12: -1.89854e+15) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x0000000000000000dcdbdad9dcdbdad9 (s13: -4.95069e+17) <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x0000000000000000e0dfdedde0dfdedd (s14: -1.29053e+20) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x0000000000000000ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x00000000000000000002000200020002 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x00000000000000000085008500850085 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x0000000000000000ff00ff00ff00ff00 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x0000000000000000e2e1e2e1e2e1e2e1 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x0000000000000000e4e3e4e3e4e3e4e3 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x0000000000000000e6e5e6e5e6e5e6e5 <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x0000000000000000e8e7e8e7e8e7e8e7 <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x0000000000000000e1e0e1e0e1e0e1e0 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x0000000000000000e3e2e3e2e3e2e3e2 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x0000000000000000e5e4e5e4e5e4e5e4 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x0000000000000000e7e6e7e6e7e6e7e6 <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x0002ff010002ff010002ff010002ff01 (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0xff000085ff000085ff000085ff000085 (..., -1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00fffeff00fffeff00fffeff00fffeff (..., 2.35095e-38, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000000000000000000000 (..., 0.00000, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0xebeae9e8ebeae9e8ebeae9e8ebeae9e8 (..., -5.67986e+26, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0xefeeedecefeeedecefeeedecefeeedec (..., -1.47890e+29, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0xf3f2f1f0f3f2f1f0f3f2f1f0f3f2f1f0 (..., -3.84962e+31, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0xf7f6f5f4f7f6f5f4f7f6f5f4f7f6f5f4 (..., -1.00179e+34, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0xeae9e8e7eae9e8e7eae9e8e7eae9e8e7 (..., -1.41390e+26, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0xeeedecebeeedecebeeedecebeeedeceb (..., -3.68172e+28, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0xf2f1f0eff2f1f0eff2f1f0eff2f1f0ef (..., -9.58428e+30, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0xf6f5f4f3f6f5f4f3f6f5f4f3f6f5f4f3 (..., -2.49430e+33, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x00000000000000000101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x0000000000000000ffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00000000000000000202020202020202 <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000f7f7f7f7f7f7f7f7 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x0000000000000000f8f8f8f8f8f8f8f8 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000000000f9f9f9f9f9f9f9f9 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x0000000000000000fafafafafafafafa <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000000000f6f6f6f6f6f6f6f6 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x0000000000000000f7f7f7f7f7f7f7f7 <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x0000000000000000f8f8f8f8f8f8f8f8 <- 0x~~~~~~~~~~~~~~~~
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diff --git a/test/test-trace-reference/log-vregs-colour b/test/test-trace-reference/log-vregs-colour
new file mode 100644
index 0000000..64fd534
--- /dev/null
+++ b/test/test-trace-reference/log-vregs-colour
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+#   v10: 0x00000018000000180000001800000018
+#   v30: 0x0000000000000000ffffffffffffffff
+#   v31: 0x00000000000000000101010101010101
+#   v28: 0xffffffffffffffffffffffffffffffff
+#    v2: 0x00000000000000000000000000000000
+#   v29: 0x0000000000000000ffffff7df7f7f775
+#    v3: 0x0000000000000000ffffffffffffffff
+#    v1: 0xff000000000000000000000000000000
+#    v2: 0x000000000000000000ffffffffffffff
+#   v18: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x2f2e2d2c2b2a29282726252423222120 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x3f3e3d3c3b3a39383736353433323130 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0xdbdad9d8d7d6d5d4d3d2d1d0cfce0001 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0xebeae9e8e7e6e5e4e3e2e1e0dfdedddc <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0xfbfaf9f8f7f6f5f4f3f2f1f0efeeedec <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0b0a09080706050403020100fffefdfc <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0xdad9d8d7d6d5d4d3d2d1d0cfcecdcccb <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0xeae9e8e7e6e5e4e3e2e1e0dfdedddcdb <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0xfaf9f8f7f6f5f4f3f2f1f0efeeedeceb <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0a09080706050403020100fffefdfcfb <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x2f2e2d2c2b2a29282726252423222120 <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x1a191817161514131211100f0e0d0c0b <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x2a292827262524232221201f1e1d1c1b <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x3a393837363534333231302f2e2d2c2b <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x191817161514131211100f0e0d0c0b0a <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x292827262524232221201f1e1d1c1b1a <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x393837363534333231302f2e2d2c2b2a <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x494847464544434241403f3e3d3c3b3a <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x595857565554535251504f4e4d4c4b4a <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x4847464544434241403f3e3d3c3b3a39 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x5857565554535251504f4e4d4c4b4a49 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x6867666564636261605f5e5d5c5b5a59 <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x67666564636261605f5e5d5c5b5a5958 <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000ff0000850002ff01 (d4: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x00000000000000000000000000fffeff (d5: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000001700000000000000 (d6: 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000001f1e1d1c1b1a1918 (d7: 8.56775e-159) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000006f6e6d6c6b6a6968 (d17: 5.76650e+228) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000007776757473727170 (d18: 2.89670e+267) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000007f7e7d7c7b7a7978 (d19: 1.33818e+306) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x00000000000000008786858483828180 (d20: -2.08158e-272) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x00000000000000006e6d6c6b6a696867 (d28: 8.50866e+223) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000000000767574737271706f (d29: 4.22243e+262) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x00000000000000007e7d7c7b7a797877 (d30: 1.97467e+301) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x0000000000000000868584838281807f (d31: -3.03465e-277) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x0000000000000000ff0000850002ff01 (d20: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x00000000000000000000000000fffeff (d21: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x00000000000000001700000000000000 (d22: 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000008e8d8c8b8a898887 (d19: -1.41807e-238) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x0000000000000000969594939291908f (d20: -7.04826e-200) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x00000000000000009e9d9c9b9a999897 (d21: -3.29099e-161) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x00000000000000008d8c8b8a89888786 (d12: -2.09028e-243) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x00000000000000009594939291908f8e (d13: -1.02545e-204) <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x00000000000000009d9c9b9a99989796 (d14: -4.85140e-166) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000000000ff0000850002ff01 (d29: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x00000000000000000000000000fffeff (d30: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x0000000000000000a5a4a3a2a1a09f9e (d31: -2.38202e-127) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x0000000000000000adacabaaa9a8a7a6 (d0: -1.12597e-88) <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000a4a3a2a1a09f9e9d (d3: -3.45787e-132) <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000acabaaa9a8a7a6a5 (d4: -1.65794e-93) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x0000000000000000ff0000850002ff01 (d28: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x0000000000000000b4b3b2b1b0afaead (d11: -8.03348e-55) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000000000b3b2b1b0afaeadac (d29: -1.16334e-59) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x0000000000fffeffff0000850002ff01 (8.28892e-317, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x1f1e1d1c1b1a19181700000000000000 (8.56775e-159, 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x2f2e2d2c2b2a29282726252423222120 (1.98829e-81, 4.28794e-120) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x3f3e3d3c3b3a39383736353433323130 (0.000461414, 9.95833e-43) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0xc3c2c1c0bfbebdbcbbbab9b8b7b6b5b4 (-2.70315e+18, -5.65934e-21) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0xd3d2d1d0cfcecdcccbcac9c8c7c6c5c4 (-6.28100e+95, -1.31369e+57) <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0xe3e2e1e0dfdedddcdbdad9d8d7d6d5d4 (-1.45943e+173, -3.04943e+134) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0xf3f2f1f0efeeedecebeae9e8e7e6e5e4 (-3.39104e+250, -7.07849e+211) <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0xc2c1c0bfbebdbcbbbab9b8b7b6b5b4b3 (-3.90391e+13, -8.31108e-26) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0xd2d1d0cfcecdcccbcac9c8c7c6c5c4c3 (-9.07279e+90, -1.92941e+52) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0xe2e1e0dfdedddcdbdad9d8d7d6d5d4d3 (-2.10851e+168, -4.47908e+129) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0xf2f1f0efeeedecebeae9e8e7e6e5e4e3 (-4.90012e+245, -1.03980e+207) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0000000000fffeffff0000850002ff01 (8.28892e-317, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x1f1e1d1c1b1a19181700000000000000 (8.56775e-159, 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x2f2e2d2c2b2a29282726252423222120 (1.98829e-81, 4.28794e-120) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x020100fffefdfcfbfaf9f8f7f6f5f4f3 (5.07812e-299, -2.41385e+284) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x1211100f0e0d0c0b0a09080706050403 (1.18008e-221, 2.54377e-260) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x2221201f1e1d1c1b1a19181716151413 (2.74293e-144, 5.90574e-183) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0100fffefdfcfbfaf9f8f7f6f5f4f3f2 (7.74681e-304, -3.54087e+279) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x11100f0e0d0c0b0a0908070605040302 (1.69471e-226, 3.72581e-265) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x21201f1e1d1c1b1a1918171615141312 (3.94003e-149, 8.65093e-188) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x0000000000fffeffff0000850002ff01 (8.28892e-317, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x1f1e1d1c1b1a19181700000000000000 (8.56775e-159, 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x31302f2e2d2c2b2a2928272625242322 (9.15999e-72, 2.00864e-110) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x41403f3e3d3c3b3a3938373635343332 (2.12953e+06, 4.66377e-33) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x302f2e2d2c2b2a292827262524232221 (1.34639e-76, 2.93754e-115) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x403f3e3d3c3b3a393837363534333231 (31.2431, 6.82132e-38) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x0000000000fffeffff0000850002ff01 (8.28892e-317, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x504f4e4d4c4b4a494847464544434241 (7.24994e+78, 1.58398e+40) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x4f4e4d4c4b4a49484746454443424140 (1.07078e+74, 2.31271e+35) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x0000000000000000ff0000850002ff01 (..., -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x00000000000000000000000000fffeff (..., 0.00000, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x00000000000000001700000000000000 (..., 4.13590e-25, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x00000000000000001f1e1d1c1b1a1918 (..., 3.34819e-20, 1.27467e-22) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00000000000000005756555453525150 (..., 2.35662e+14, 9.03307e+11) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x00000000000000005f5e5d5c5b5a5958 (..., 1.60231e+19, 6.14598e+16) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000006766656463626160 (..., 1.08801e+24, 4.17598e+21) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x00000000000000006f6e6d6c6b6a6968 (..., 7.37897e+28, 2.83386e+26) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000565554535251504f (..., 5.86395e+13, 2.24749e+11) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x00000000000000005e5d5c5b5a595857 (..., 3.98768e+18, 1.52943e+16) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000000000666564636261605f (..., 2.70818e+23, 1.03937e+21) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x00000000000000006e6d6c6b6a696867 (..., 1.83698e+28, 7.05432e+25) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x0000000000000000ff0000850002ff01 (..., -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x00000000000000000000000000fffeff (..., 0.00000, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x00000000000000001700000000000000 (..., 4.13590e-25, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0000000000000000767574737271706f (..., 1.24460e+33, 4.78220e+30) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000007e7d7c7b7a797877 (..., 8.42353e+37, 3.23831e+35) <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x0000000000000000868584838281807f (..., -5.02237e-35, -1.90286e-37) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x00000000000000007574737271706f6e (..., 3.09878e+32, 1.19058e+30) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x00000000000000007d7c7b7a79787776 (..., 2.09754e+37, 8.06320e+34) <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x00000000000000008584838281807f7e (..., -1.24615e-35, -4.72027e-38) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x0000000000000000ff0000850002ff01 (..., -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x00000000000000000000000000fffeff (..., 0.00000, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x00000000000000008d8c8b8a89888786 (..., -8.66176e-31, -3.28683e-33) <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x00000000000000009594939291908f8e (..., -6.00095e-26, -2.28077e-28) <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x00000000000000008c8b8a8988878685 (..., -2.14997e-31, -8.15664e-34) <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x000000000000000094939291908f8e8d (..., -1.49010e-26, -5.66232e-29) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0000000000000000ff0000850002ff01 (..., -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x00000000000000009c9b9a9998979695 (..., -1.02970e-21, -3.91846e-24) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x00000000000000009b9a999897969594 (..., -2.55764e-22, -9.73128e-25) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000001700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000001f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x0000000000000000a3a2a1a09f9e9d9c <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x0000000000000000abaaa9a8a7a6a5a4 <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0000000000000000b3b2b1b0afaeadac <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000bbbab9b8b7b6b5b4 <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x0000000000000000a2a1a09f9e9d9c9b <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000000000aaa9a8a7a6a5a4a3 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000b2b1b0afaeadacab <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000bab9b8b7b6b5b4b3 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x00000000000000001700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x0000000000000000c2c1c0bfbebdbcbb <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0000000000000000cac9c8c7c6c5c4c3 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000d2d1d0cfcecdcccb <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000c1c0bfbebdbcbbba <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000c9c8c7c6c5c4c3c2 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x0000000000000000d1d0cfcecdcccbca <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000d9d8d7d6d5d4d3d2 <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000e1e0dfdedddcdbda <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x0000000000000000d8d7d6d5d4d3d2d1 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x0000000000000000e0dfdedddcdbdad9 <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x0000000000000000e8e7e6e5e4e3e2e1 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x0000000000000000e7e6e5e4e3e2e1e0 <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0000000000fffeffff0000850002ff01 (0.00000, 2.35095e-38, -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x1f1e1d1c1b1a19181700000000000000 (3.34819e-20, 1.27467e-22, 4.13590e-25, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x2f2e2d2c2b2a29282726252423222120 (1.58413e-10, 6.04532e-13, 2.30573e-15, 8.78905e-18) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x3f3e3d3c3b3a39383736353433323130 (0.743122, 0.00284155, 1.08604e-05, 4.14886e-08) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0xf7f6f5f4f3f2f1f0efeeedecebeae9e8 (-1.00179e+34, -3.84962e+31, -1.47890e+29, -5.67986e+26) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0706050403020100fffefdfcfbfaf9f8 (1.00825e-34, 3.82047e-37, -nan, -2.60629e+36) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x17161514131211100f0e0d0c0b0a0908 (4.84942e-25, 1.84362e-27, 7.00365e-30, 2.65846e-32) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x27262524232221201f1e1d1c1b1a1918 (2.30573e-15, 8.78905e-18, 3.34819e-20, 1.27467e-22) <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0xf6f5f4f3f2f1f0efeeedecebeae9e8e7 (-2.49430e+33, -9.58428e+30, -3.68172e+28, -1.41390e+26) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x06050403020100fffefdfcfbfaf9f8f7 (2.50175e-35, 9.47771e-38, -1.68804e+38, -6.48966e+35) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x161514131211100f0e0d0c0b0a090807 (1.20425e-25, 4.57737e-28, 1.73854e-30, 6.59782e-33) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x262524232221201f1e1d1c1b1a191817 (5.72948e-16, 2.18366e-18, 8.31732e-21, 3.16591e-23) <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000fffeffff0000850002ff01 (0.00000, 2.35095e-38, -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x1f1e1d1c1b1a19181700000000000000 (3.34819e-20, 1.27467e-22, 4.13590e-25, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x2f2e2d2c2b2a29282726252423222120 (1.58413e-10, 6.04532e-13, 2.30573e-15, 8.78905e-18) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x363534333231302f2e2d2c2b2a292827 (2.70015e-06, 1.03137e-08, 3.93749e-11, 1.50241e-13) <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x464544434241403f3e3d3c3b3a393837 (12625.1, 48.3127, 0.184800, 0.000706557) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x565554535251504f4e4d4c4b4a494847 (5.86395e+13, 2.24749e+11, 8.61082e+08, 3.29781e+06) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x3534333231302f2e2d2c2b2a29282726 (6.71297e-07, 2.56382e-09, 9.78665e-12, 3.73374e-14) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x4544434241403f3e3d3c3b3a39383736 (3140.20, 12.0154, 0.0459549, 0.000175682) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x5554535251504f4e4d4c4b4a49484746 (1.45909e+13, 5.59177e+10, 2.14218e+08, 820340.) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x0000000000fffeffff0000850002ff01 (0.00000, 2.35095e-38, -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x1f1e1d1c1b1a19181700000000000000 (3.34819e-20, 1.27467e-22, 4.13590e-25, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x6564636261605f5e5d5c5b5a59585756 (6.74083e+22, 2.58684e+20, 9.92399e+17, 3.80591e+15) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x7574737271706f6e6d6c6b6a69686766 (3.09878e+32, 1.19058e+30, 4.57302e+27, 1.75599e+25) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x64636261605f5e5d5c5b5a5958575655 (1.67780e+22, 6.43816e+19, 2.46969e+17, 9.47063e+14) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x74737271706f6e6d6c6b6a6968676665 (7.71514e+31, 2.96402e+29, 1.13840e+27, 4.37102e+24) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x0000000000fffeffff0000850002ff01 (0.00000, 2.35095e-38, -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x84838281807f7e7d7c7b7a7978777675 (-3.09178e-36, -1.17085e-38, 5.22300e+36, 2.00766e+34) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x838281807f7e7d7c7b7a797877767574 (-7.67045e-37, 3.38275e+38, 1.30054e+36, 4.99878e+33) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000001700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x00000000000000001f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x00000000000000008b8a898887868584 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x0000000000000000939291908f8e8d8c <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000009b9a999897969594 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0000000000000000a3a2a1a09f9e9d9c <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000008a89888786858483 <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x00000000000000009291908f8e8d8c8b <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x00000000000000009a99989796959493 <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000000000a2a1a09f9e9d9c9b <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000001700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000000000aaa9a8a7a6a5a4a3 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000b2b1b0afaeadacab <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000bab9b8b7b6b5b4b3 <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000000000a9a8a7a6a5a4a3a2 <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x0000000000000000b1b0afaeadacabaa <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x0000000000000000b9b8b7b6b5b4b3b2 <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x0000000000000000c1c0bfbebdbcbbba <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000000000c9c8c7c6c5c4c3c2 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000c0bfbebdbcbbbab9 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x0000000000000000c8c7c6c5c4c3c2c1 <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x0000000000000000d0cfcecdcccbcac9 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x0000000000000000cfcecdcccbcac9c8 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x2f2e2d2c2b2a29282726252423222120 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x3f3e3d3c3b3a39383736353433323130 <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0xdfdedddcdbdad9d8d7d6d5d4d3d2d1d0 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0xefeeedecebeae9e8e7e6e5e4e3e2e1e0 <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0xfffefdfcfbfaf9f8f7f6f5f4f3f2f1f0 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x0f0e0d0c0b0a09080706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0xdedddcdbdad9d8d7d6d5d4d3d2d1d0cf <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0xeeedecebeae9e8e7e6e5e4e3e2e1e0df <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0xfefdfcfbfaf9f8f7f6f5f4f3f2f1f0ef <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x0e0d0c0b0a09080706050403020100ff <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x2f2e2d2c2b2a29282726252423222120 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x1e1d1c1b1a191817161514131211100f <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x2e2d2c2b2a292827262524232221201f <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x3e3d3c3b3a393837363534333231302f <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x1d1c1b1a191817161514131211100f0e <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x2d2c2b2a292827262524232221201f1e <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x3d3c3b3a393837363534333231302f2e <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x4d4c4b4a494847464544434241403f3e <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x5d5c5b5a595857565554535251504f4e <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x4c4b4a494847464544434241403f3e3d <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x5c5b5a595857565554535251504f4e4d <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x6c6b6a696867666564636261605f5e5d <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x6b6a696867666564636261605f5e5d5c <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x3d3c3b3a39383736353433323130012e <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0xfefdfcfbfaf9f8f7f6f5f4f36cf1f0ef <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x6c6b6a6b6867666564636261605f5e5d <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0xff0000850002ff01d6d5d4d3d2d1d0cf (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x737271706f6e6d6c636261605f5e5d5c (1.28953e+248, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x7271706f6e6d6c6b2726252423222120 (1.86056e+243, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x3d3c3b3aff013736353433323130012e <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0xff0000850002ff01d6d5d4d37473d0cf <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x5c5b5a595857737254535251504f4e4d <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x4d4c4b4a0002ff014544434241403f3e (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x0e0d0c0b7776757406050403020100ff (..., 4.99878e+33, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x0000000076757473e8e7e6e5e4e3e2e1 (..., 1.24460e+33, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x01010101010101010101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x77777777777777777777777777777777 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x76767676767676767676767676767676 <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x0000000000000000ff0000850002ff01 (d25: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000007e7d7c7b7a797877 (d9: 1.97467e+301) <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x00000000000000007d7c7b7a79787776 (d23: 2.91053e+296) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0xff0000850002ff01ff0000850002ff01 (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x8584838281807f7e8584838281807f7e (-4.41447e-282, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x84838281807f7e7d84838281807f7e7d (-6.40629e-287, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00000000000000000002ff010002ff01 (s24: 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000008887868588878685 (s26: -8.15664e-34) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x00000000000000008786858487868584 (s28: -2.02406e-34) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x0000000000000000ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x00000000000000008988898889888988 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x00000000000000008887888788878887 <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x0002ff010002ff010002ff010002ff01 (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x8c8b8a898c8b8a898c8b8a898c8b8a89 (..., -2.14997e-31, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x8b8a89888b8a89888b8a89888b8a8988 (..., -5.33626e-32, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000000101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x00000000000000008c8c8c8c8c8c8c8c <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000008b8b8b8b8b8b8b8b <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0xff01ff01ff01ff01ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x8d8c8d8c8d8c8d8c8d8c8d8c8d8c8d8c <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x8c8b8c8b8c8b8c8b8c8b8c8b8c8b8c8b <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x1e1c1a18000000000000ffff00850201 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x1f1d1b1917000000000000feff0000ff <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0xaba9a7a5a3a19f9d9b99979593918f8d <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0xacaaa8a6a4a2a09e9c9a98969492908e <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0xaaa8a6a4a2a09e9c9a98969492908e8c <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0xaba9a7a5a3a19f9d9b99979593918f8d <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x1700000000000000ff0000850002ff01 (6.68887e-198, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x1f1e1d1c1b1a19180000000000fffeff (8.56775e-159, 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0xc3c2c1c0bfbebdbcb3b2b1b0afaeadac (-2.70315e+18, -1.16334e-59) <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0xcbcac9c8c7c6c5c4bbbab9b8b7b6b5b4 (-1.31369e+57, -5.65934e-21) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0xc2c1c0bfbebdbcbbb2b1b0afaeadacab (-3.90391e+13, -1.67978e-64) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0xcac9c8c7c6c5c4c3bab9b8b7b6b5b4b3 (-1.92941e+52, -8.31108e-26) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x000000000000000000fffeff0002ff01 (..., 2.35095e-38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x000000000000000000000000ff000085 (..., 0.00000, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000000000d6d5d4d3cecdcccb (..., -1.17555e+14, -1.72638e+09) <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000dad9d8d7d2d1d0cf (..., -3.06592e+16, -4.50576e+11) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000000000d5d4d3d2cdcccbca (..., -2.92508e+13, -4.29488e+08) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x0000000000000000d9d8d7d6d1d0cfce (..., -7.62949e+15, -1.12105e+11) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000000000feff0085ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x0000000000000000000000ffff000002 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x0000000000000000e7e6e3e2dfdedbda <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x0000000000000000e9e8e5e4e1e0dddc <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x0000000000000000e6e5e2e1dedddad9 <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000000000e8e7e4e3e0dfdcdb <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x1b1a19180000000000fffeff0002ff01 (1.27467e-22, 0.00000, 2.35095e-38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x1f1e1d1c1700000000000000ff000085 (3.34819e-20, 4.13590e-25, 0.00000, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x04030201fcfbfaf9f4f3f2f1ecebeae9 (1.53999e-36, -1.04669e+37, -1.54621e+32, -2.28166e+27) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x0807060500fffefdf8f7f6f5f0efeeed (4.06322e-34, 2.35095e-38, -4.02346e+34, -5.94046e+29) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x03020100fbfaf9f8f3f2f1f0ebeae9e8 (3.82047e-37, -2.60629e+36, -3.84962e+31, -5.67986e+26) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x07060504fffefdfcf7f6f5f4efeeedec (1.00825e-34, -nan, -1.00179e+34, -1.47890e+29) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000000000ffff00850201 <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x0000000000000000000000feff0000ff <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x0000000000000000161412100e0c0a08 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x0000000000000000171513110f0d0b09 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000001513110f0d0b0907 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0000000000000000161412100e0c0a08 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x1d1c1918000000000000feff0085ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x1f1e1b1a17000000000000ffff000002 <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x3433302f2c2b28272423201f1c1b1817 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x363532312e2d2a29262522211e1d1a19 <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x33322f2e2b2a272623221f1e1b1a1716 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x353431302d2c2928252421201d1c1918 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x363532012e2d2a29262522211e1d1a19 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x1f1e1dff1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x4544434241403f3e363c3b3a39383736 <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000003700ffff00850201 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0706050403020100fffefdfcfb35f9f8 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x1d1c1918000000000000feff0036ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0xff0000850002ff01f8f7f6f5f0efeeed (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000fffeffd5d4d3d2cdcccbca (8.28892e-317, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000003e3d3c3b3a393837 (d26: 6.80687e-09) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000464544434241403f (d27: 3.36984e+30) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x07060504fffefdfc3d3c3b3a39383736 (d25: 1.00298e-13) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000004544434241403f3e (d26: 4.89923e+25) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0xff01000000000000000000feff0000ff <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00020000000000008b8b8b8b8b8b8b8b <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000474600003700ffff00850201 <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0xff01000049480000000000feff0000ff <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x1d1c191800000000000046450036ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x1f1e1b1a1700000000004847ff000002 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0002ff0103020100fffefdfcfb35f9f8 (2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0xff00008500000000000046450036ff01 (-1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x0000000000000000000000004c4b4a49 (s28: 5.32913e+07) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0002ff0103020100fffefdfc504f4e4d (s29: 1.39121e+10) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x1f1e1dff1b1a19184b4a494800000000 (..., 1.32570e+07, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000004f4e4d4c0d0b0907 (..., 3.46117e+09, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x01010101010101010101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0xffffffffffffffffffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x50505050505050505050505050505050 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x51515151515151515151515151515151 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x4f4f4f4f4f4f4f4f4f4f4f4f4f4f4f4f <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x50505050505050505050505050505050 <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0000000000000000ff0000850002ff01 (d26: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x00000000000000000000000000fffeff (d27: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x00000000000000005857565554535251 (d14: 3.67814e+117) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x0000000000000000605f5e5d5c5b5a59 (d15: 1.68234e+156) <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x00000000000000005756555453525150 (d23: 5.37096e+112) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00000000000000005f5e5d5c5b5a5958 (d24: 2.48489e+151) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0xff0000850002ff01ff0000850002ff01 (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000fffeff0000000000fffeff (8.28892e-317, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x67666564636261606766656463626160 (1.24732e+190, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x6f6e6d6c6b6a69686f6e6d6c6b6a6968 (5.76650e+228, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x666564636261605f666564636261605f (1.81795e+185, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x6e6d6c6b6a6968676e6d6c6b6a696867 (8.50866e+223, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000000002ff010002ff01 (s26: 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000ff000085ff000085 (s27: -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x00000000000000007271706f7271706f (s22: 4.78220e+30) <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x00000000000000007675747376757473 (s23: 1.24460e+33) <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x000000000000000071706f6e71706f6e (s2: 1.19058e+30) <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x00000000000000007574737275747372 (s3: 3.09878e+32) <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000000000ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x00000000000000000002000200020002 <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000007776777677767776 <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x00000000000000007978797879787978 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000007675767576757675 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000007877787778777877 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x0002ff010002ff010002ff010002ff01 (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0xff000085ff000085ff000085ff000085 (..., -1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x7c7b7a797c7b7a797c7b7a797c7b7a79 (..., 5.22300e+36, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x807f7e7d807f7e7d807f7e7d807f7e7d (..., -1.17085e-38, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x7b7a79787b7a79787b7a79787b7a7978 (..., 1.30054e+36, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x7f7e7d7c7f7e7d7c7f7e7d7c7f7e7d7c (..., 3.38275e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000000101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000ffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x00000000000000008080808080808080 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x00000000000000008181818181818181 <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x00000000000000007f7f7f7f7f7f7f7f <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x00000000000000008080808080808080 <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0xff01ff01ff01ff01ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x00020002000200020002000200020002 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x82818281828182818281828182818281 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x84838483848384838483848384838483 <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x81808180818081808180818081808180 <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x83828382838283828382838283828382 <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x2d2a2724211e1b1800000000fe000001 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x2e2b2825221f1c1900000000ffff85ff <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x2f2c292623201d1a1700000000ff0002 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0xb1aeaba8a5a29f9c999693908d8a8784 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0xb2afaca9a6a3a09d9a9794918e8b8885 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0xb3b0adaaa7a4a19e9b9895928f8c8986 <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0xb0adaaa7a4a19e9b9895928f8c898683 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0xb1aeaba8a5a29f9c999693908d8a8784 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0xb2afaca9a6a3a09d9a9794918e8b8885 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x1f1e1d1c1b1a1918ff0000850002ff01 (8.56775e-159, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x27262524232221200000000000fffeff (4.28794e-120, 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x2f2e2d2c2b2a29281700000000000000 (1.98829e-81, 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0xd2d1d0cfcecdcccbbab9b8b7b6b5b4b3 (-9.07279e+90, -8.31108e-26) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0xdad9d8d7d6d5d4d3c2c1c0bfbebdbcbb (-4.47908e+129, -3.90391e+13) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0xe2e1e0dfdedddcdbcac9c8c7c6c5c4c3 (-2.10851e+168, -1.92941e+52) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0xd1d0cfcecdcccbcab9b8b7b6b5b4b3b2 (-1.30639e+86, -1.21867e-30) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0xd9d8d7d6d5d4d3d2c1c0bfbebdbcbbba (-6.56908e+124, -5.62003e+08) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0xe1e0dfdedddcdbdac9c8c7c6c5c4c3c2 (-3.03668e+163, -2.82942e+47) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x0000000000000000000000000002ff01 (..., 0.00000, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x000000000000000000000000ff000085 (..., 0.00000, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000001700000000fffeff (..., 4.13590e-25, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x0000000000000000f1f0efeee5e4e3e2 (..., -2.38613e+30, -1.35113e+23) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x0000000000000000f5f4f3f2e9e8e7e6 (..., -6.21029e+32, -3.51957e+25) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x0000000000000000f9f8f7f6edecebea (..., -1.61590e+35, -9.16546e+27) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0000000000000000f0efeeede4e3e2e1 (..., -5.94046e+29, -3.36301e+22) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000f4f3f2f1e8e7e6e5 (..., -1.54621e+32, -8.76101e+24) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x0000000000000000f8f7f6f5ecebeae9 (..., -4.02346e+34, -2.28166e+27) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x000000000000000000000000ff00ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x000000000000000000000000feff0002 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x00000000000000001700000000ff0085 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x00000000000000000c0b060500fffaf9 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x00000000000000000e0d08070201fcfb <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x0000000000000000100f0a090403fefd <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000000b0a0504fffef9f8 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00000000000000000d0c07060100fbfa <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000000f0e09080302fdfc <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x272625241b1a1918000000000002ff01 (2.30573e-15, 1.27467e-22, 0.00000, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x2b2a29281f1e1d1c00000000ff000085 (6.04532e-13, 3.34819e-20, 0.00000, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x2f2e2d2c232221201700000000fffeff (1.58413e-10, 8.78905e-18, 4.13590e-25, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x373635342b2a29281f1e1d1c13121110 (1.08604e-05, 6.04532e-13, 3.34819e-20, 1.84362e-27) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x3b3a39382f2e2d2c2322212017161514 (0.00284155, 1.58413e-10, 8.78905e-18, 4.84942e-25) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x3f3e3d3c33323130272625241b1a1918 (0.743122, 4.14886e-08, 2.30573e-15, 1.27467e-22) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x363534332a2928271e1d1c1b1211100f (2.70015e-06, 1.50241e-13, 8.31732e-21, 4.57737e-28) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x3a3938372e2d2c2b2221201f16151413 (0.000706557, 3.93749e-11, 2.18366e-18, 1.20425e-25) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x3e3d3c3b3231302f262524231a191817 (0.184800, 1.03137e-08, 5.72948e-16, 3.16591e-23) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x000000000000000000000000fe000001 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x000000000000000000000000ffff85ff <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x00000000000000001700000000ff0002 <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x000000000000000054514e4b4845423f <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x000000000000000055524f4c49464340 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x00000000000000005653504d4a474441 <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x000000000000000053504d4a4744413e <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x000000000000000054514e4b4845423f <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x000000000000000055524f4c49464340 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x2b2a25241f1e191800000000ff00ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x2d2c272621201b1a00000000feff0002 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x2f2e292823221d1c1700000000ff0085 <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x81807b7a75746f6e696863625d5c5756 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x83827d7c777671706b6a65645f5e5958 <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x85847f7e797873726d6c676661605b5a <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x807f7a7974736e6d686762615c5b5655 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x82817c7b7675706f6a6964635e5d5857 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x84837e7d787772716c6b6665605f5a59 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x0000000001000000f5f4f3f2e9e8e7e6 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x2b2a2524ff1e191800000000ff00ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x2d2c272602201b1a00000000feff0002 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x4f4f4f4f4f4f854f4f4f4f4f4f4f4f4f <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x82818281828186818281828182818281 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000087000b0a0504fffef9f8 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x2d2c272602201b1a00000000feff0084 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x2f2e292823221d1c1700000000ff0085 <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x3b3a39382f2e2d2c2322212017161586 <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x6e6d6c6b6a696867ff0000850002ff01 (d16: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000474600000000000000fffeff (d17: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0xd2d1d0cfcecdcccb1700000000000000 (d18: 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x84837e7d787772718e8d8c8b8a898887 (d30: -1.41807e-238) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x0000000000000000969594939291908f (d31: -7.04826e-200) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0xc3c2c1c0bfbebdbc9e9d9c9b9a999897 (d0: -3.29099e-161) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x8d8c8b8a89888786686762615c5b5655 (-2.09028e-243, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x9594939291908f8e6a6964635e5d5857 (-1.02545e-204, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x9d9c9b9a999897968e8d8c8b8a898887 (-4.85140e-166, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x81807b7a75746f6e6968ff015d5c5756 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x83827d7c777671706b6a00025f5e5958 <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x85847f7e797873726d6c008561605b5a <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x9f9e2524ff1e191800000000ff00ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0xa1a0272602201b1a00000000feff0084 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0xa3a2292823221d1c1700000000ff0085 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x83827d7c777671709e9d00025f5e5958 <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x85847f7e79787372a09f008561605b5a <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x6e6d6c6b6a696867a2a100850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x0002ff01ff1e191800000000ff00ff01 (2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0xff00008502201b1a00000000feff0084 (-1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00fffeff23221d1c1700000000ff0085 (2.35095e-38, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x9d9c9b9aa6a5a4a38e8d8c8b8a898887 (..., -1.14938e-15, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x00000000aaa9a8a7969594939291908f (..., -3.01375e-13, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0xc3c2c1c0aeadacab9e9d9c9b9a999897 (..., -7.89780e-11, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000000000a5a4a3a24744413e (..., -2.85603e-16, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x81807b7a75746f6ea9a8a7a65d5c5756 (..., -7.48978e-14, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x83827d7c77767170adacabaa5f5e5958 (..., -1.96304e-11, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x01010101010101010101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0xffffffffffffffffffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x02020202020202020202020202020202 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0xaeaeaeaeaeaeaeaeaeaeaeaeaeaeaeae <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0xafafafafafafafafafafafafafafafaf <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0xb0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0xadadadadadadadadadadadadadadadad <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0xaeaeaeaeaeaeaeaeaeaeaeaeaeaeaeae <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0xafafafafafafafafafafafafafafafaf <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000ff0000850002ff01 (d4: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x00000000000000000000000000fffeff (d5: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000001700000000000000 (d6: 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x0000000000000000b7b6b5b4b3b2b1b0 (d7: -2.60696e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0000000000000000bfbebdbcbbbab9b8 (d8: -0.120083) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x0000000000000000c7c6c5c4c3c2c1c0 (d9: -6.05398e+37) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x0000000000000000b6b5b4b3b2b1b0af (d17: -3.80205e-45) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x0000000000000000bebdbcbbbab9b8b7 (d18: -1.77248e-06) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x0000000000000000c6c5c4c3c2c1c0bf (d19: -8.83040e+32) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0xff0000850002ff01ff0000850002ff01 (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x0000000000fffeff0000000000fffeff (8.28892e-317, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x17000000000000001700000000000000 (6.68887e-198, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0xcecdcccbcac9c8c7cecdcccbcac9c8c7 (-4.11344e+71, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0xd6d5d4d3d2d1d0cfd6d5d4d3d2d1d0cf (-2.05087e+110, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0xdedddcdbdad9d8d7dedddcdbdad9d8d7 (-9.54613e+148, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0xcdcccbcac9c8c7c6cdcccbcac9c8c7c6 (-6.06516e+66, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0xd5d4d3d2d1d0cfced5d4d3d2d1d0cfce (-2.98548e+105, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0xdddcdbdad9d8d7d6dddcdbdad9d8d7d6 (-1.40766e+144, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x00000000000000000002ff010002ff01 (s10: 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x0000000000000000ff000085ff000085 (s11: -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x000000000000000000fffeff00fffeff (s12: 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x0000000000000000e1e0dfdee1e0dfde (s0: -5.18525e+20) <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x0000000000000000e5e4e3e2e5e4e3e2 (s1: -1.35113e+23) <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000000000e9e8e7e6e9e8e7e6 (s2: -3.51957e+25) <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x0000000000000000e0dfdedde0dfdedd (s23: -1.29053e+20) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x0000000000000000e4e3e2e1e4e3e2e1 (s24: -3.36301e+22) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x0000000000000000e8e7e6e5e8e7e6e5 (s25: -8.76101e+24) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x0000000000000000ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x00000000000000000002000200020002 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00000000000000000085008500850085 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x0000000000000000eae9eae9eae9eae9 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x0000000000000000ecebecebecebeceb <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0000000000000000eeedeeedeeedeeed <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x0000000000000000e9e8e9e8e9e8e9e8 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0000000000000000ebeaebeaebeaebea <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x0000000000000000edecedecedecedec <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0002ff010002ff010002ff010002ff01 (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0xff000085ff000085ff000085ff000085 (..., -1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x00fffeff00fffeff00fffeff00fffeff (..., 2.35095e-38, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0xf1f0efeef1f0efeef1f0efeef1f0efee (..., -2.38613e+30, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0xf5f4f3f2f5f4f3f2f5f4f3f2f5f4f3f2 (..., -6.21029e+32, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0xf9f8f7f6f9f8f7f6f9f8f7f6f9f8f7f6 (..., -1.61590e+35, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0xf0efeeedf0efeeedf0efeeedf0efeeed (..., -5.94046e+29, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0xf4f3f2f1f4f3f2f1f4f3f2f1f4f3f2f1 (..., -1.54621e+32, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0xf8f7f6f5f8f7f6f5f8f7f6f5f8f7f6f5 (..., -4.02346e+34, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x00000000000000000101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000ffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x00000000000000000202020202020202 <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x0000000000000000f9f9f9f9f9f9f9f9 <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x0000000000000000fafafafafafafafa <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000000000fbfbfbfbfbfbfbfb <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x0000000000000000f8f8f8f8f8f8f8f8 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000000000f9f9f9f9f9f9f9f9 <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x0000000000000000fafafafafafafafa <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0xff01ff01ff01ff01ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00020002000200020002000200020002 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00850085008500850085008500850085 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0xfcfbfcfbfcfbfcfbfcfbfcfbfcfbfcfb <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0xfefdfefdfefdfefdfefdfefdfefdfefd <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x00ff00ff00ff00ff00ff00ff00ff00ff <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0xfbfafbfafbfafbfafbfafbfafbfafbfa <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0xfdfcfdfcfdfcfdfcfdfcfdfcfdfcfdfc <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0xfffefffefffefffefffefffefffefffe <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x3c3834302c2824201c18000000ff8501 <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x3d3935312d2925211d19000000fe00ff <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x3e3a36322e2a26221e1a000000ff0002 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x3f3b37332f2b27231f1b17000000ff00 <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x3c3834302c2824201c1814100c080400 <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x3d3935312d2925211d1915110d090501 <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x3e3a36322e2a26221e1a16120e0a0602 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x3f3b37332f2b27231f1b17130f0b0703 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x3b37332f2b27231f1b17130f0b0703ff <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x3c3834302c2824201c1814100c080400 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x3d3935312d2925211d1915110d090501 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x3e3a36322e2a26221e1a16120e0a0602 <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x2726252423222120ff0000850002ff01 (4.28794e-120, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x2f2e2d2c2b2a29280000000000fffeff (1.98829e-81, 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x37363534333231301700000000000000 (9.95833e-43, 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x3f3e3d3c3b3a39381f1e1d1c1b1a1918 (0.000461414, 8.56775e-159) <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x666564636261605f464544434241403f (1.81795e+185, 3.36984e+30) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x6e6d6c6b6a6968674e4d4c4b4a494847 (8.50866e+223, 1.57975e+69) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x767574737271706f565554535251504f (4.22243e+262, 7.82703e+107) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x7e7d7c7b7a7978775e5d5c5b5a595857 (1.97467e+301, 3.66628e+146) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x6564636261605f5e4544434241403f3e (2.64379e+180, 4.89923e+25) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x6d6c6b6a696867664d4c4b4a49484746 (1.25402e+219, 2.32790e+64) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x7574737271706f6e5554535251504f4e (6.14144e+257, 1.13810e+103) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x7d7c7b7a797877765d5c5b5a59585756 (2.91053e+296, 5.40301e+141) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000000000000002ff01 (..., 0.00000, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x000000000000000017000000ff000085 (..., 4.13590e-25, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x00000000000000001b1a191800fffeff (..., 1.27467e-22, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x00000000000000001f1e1d1c00000000 (..., 3.34819e-20, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x000000000000000091908f8e81807f7e (..., -2.28077e-28, -4.72027e-38) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x00000000000000009594939285848382 (..., -6.00095e-26, -1.24615e-35) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000009998979689888786 (..., -1.57777e-23, -3.28683e-33) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x00000000000000009d9c9b9a8d8c8b8a (..., -4.14537e-21, -8.66176e-31) <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000908f8e8d807f7e7d (..., -5.66232e-29, -1.17085e-38) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x00000000000000009493929184838281 (..., -1.49010e-26, -3.09178e-36) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000009897969588878685 (..., -3.91846e-24, -8.15664e-34) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000009c9b9a998c8b8a89 (..., -1.02970e-21, -2.14997e-31) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x000000000000000019180000feffff01 <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000001b1a000000ff0002 <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000001d1c000000000085 <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000001f1e17000000ff00 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x0000000000000000b6b5aeada6a59e9d <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x0000000000000000b8b7b0afa8a7a09f <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x0000000000000000bab9b2b1aaa9a2a1 <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x0000000000000000bcbbb4b3acaba4a3 <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000000000b5b4adaca5a49d9c <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000b7b6afaea7a69f9e <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000b9b8b1b0a9a8a1a0 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x0000000000000000bbbab3b2abaaa3a2 <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x3332313023222120000000000002ff01 (4.14886e-08, 8.78905e-18, 0.00000, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x373635342726252417000000ff000085 (1.08604e-05, 2.30573e-15, 4.13590e-25, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x3b3a39382b2a29281b1a191800fffeff (0.00284155, 6.04532e-13, 1.27467e-22, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x3f3e3d3c2f2e2d2c1f1e1d1c00000000 (0.743122, 1.58413e-10, 3.34819e-20, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0xefeeedecdfdedddccfcecdccbfbebdbc (-1.47890e+29, -3.21185e+19, -6.93919e+09, -1.49017) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0xf3f2f1f0e3e2e1e0d3d2d1d0c3c2c1c0 (-3.84962e+31, -8.37048e+21, -1.81093e+12, -389.514) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0xf7f6f5f4e7e6e5e4d7d6d5d4c7c6c5c4 (-1.00179e+34, -2.18077e+24, -4.72428e+14, -101772.) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0xfbfaf9f8ebeae9e8dbdad9d8cbcac9c8 (-2.60629e+36, -5.67986e+26, -1.23202e+17, -2.65799e+07) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0xeeedecebdedddcdbcecdcccbbebdbcbb (-3.68172e+28, -7.99345e+18, -1.72638e+09, -0.370581) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0xf2f1f0efe2e1e0dfd2d1d0cfc2c1c0bf (-9.58428e+30, -2.08336e+21, -4.50576e+11, -96.8765) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0xf6f5f4f3e6e5e4e3d6d5d4d3c6c5c4c3 (-2.49430e+33, -5.42822e+23, -1.17555e+14, -25314.4) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0xfaf9f8f7eae9e8e7dad9d8d7cac9c8c7 (-6.48966e+35, -1.41390e+26, -3.06592e+16, -6.61207e+06) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x00000000000000001c18000000ff8501 <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x00000000000000001d19000000fe00ff <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000001e1a000000ff0002 <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000001f1b17000000ff00 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x000000000000000017130f0b0703fffb <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x00000000000000001814100c080400fc <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x00000000000000001915110d090501fd <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x00000000000000001a16120e0a0602fe <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x000000000000000016120e0a0602fefa <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x000000000000000017130f0b0703fffb <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000001814100c080400fc <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00000000000000001915110d090501fd <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x393831302928212019180000feffff01 <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x3b3a33322b2a23221b1a000000ff0002 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x3d3c35342d2c25241d1c000000000085 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x3f3e37362f2e27261f1e17000000ff00 <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x53524b4a43423b3a33322b2a23221b1a <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x55544d4c45443d3c35342d2c25241d1c <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x57564f4e47463f3e37362f2e27261f1e <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x59585150494841403938313029282120 <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x52514a4942413a3932312a2922211a19 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x54534c4b44433c3b34332c2b24231c1b <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x56554e4d46453e3d36352e2d26251e1d <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x5857504f4847403f3837302f2827201f <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x52514a4942413a3932312a2901211a19 <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x54534c4b44433c3b34332c2bff231c1b <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x56554e4d46453e3d36352e2d02251e1d <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x5857504f4847403f3837302f0027201f <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000000000fbfbfbfb59fbfbfb <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x81807b7a75746f6ea9a8a7a65a5c5756 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0xcdcccbcac9c8c7c6cdcccbca5bc8c7c6 <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x00000000000000001c1800005cff8501 <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x3d3c35342d2c25241d58000000000085 <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x3f3e37362f2e27261f5917000000ff00 <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000000000195a110d090501fd <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x00000000000000001a5b120e0a0602fe <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0xff0000850002ff011f5917000000ff00 (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000fffeff195a110d090501fd (8.28892e-317, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x17000000000000001a5b120e0a0602fe (6.68887e-198, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x1f1e1d1c1b1a1918d6d5d4d3c6c5c4c3 (8.56775e-159, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x636261605f5e5d5c1c1800005cff8501 (5.54935e+170, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x6b6a6968676665641d19000000fe00ff (2.71346e+209, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x737271706f6e6d6c1e1a000000ff0002 (1.28953e+248, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x7b7a7978777675741f1b17000000ff00 (6.29888e+286, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x6261605f5e5d5c5b1d19000000fe00ff (8.00514e+165, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x6a696867666564631e1a000000ff0002 (3.98304e+204, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0x7271706f6e6d6c6b1f1b17000000ff00 (1.86056e+243, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x7a797877767574731f1e17000000ff00 (9.24687e+281, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x5352ff0143423b3a33322b2a23221b1a <- 0x~~~~~~~~~~~~~~~~
+#    v3: 0x5554000245443d3c35342d2c25241d1c <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x5756008547463f3e37362f2e27261f1e <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x5958ff00494841403938313029282120 <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x5958ff00494841407c7b313029282120 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000007e7d0f0b0703fffb <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x0000000000000000807f100c080400fc <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00000000000000008281110d090501fd <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00007b7a00000000807f100c080400fc <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00007d7c000000008281110d090501fd <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x3b3a7f7e2b2a29281b1a191800fffeff <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x3f3e81802f2e2d2c1f1e1d1c00000000 <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000000002ff010703fffb (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00007b7a00000000ff000085080400fc (..., -1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00007d7c0000000000fffeff090501fd (..., 2.35095e-38, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x3b3a7f7e2b2a29280000000000fffeff (..., 0.00000, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v25: 0x393831308584838219180000feffff01 (..., -1.24615e-35, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x3b3a3332898887861b1a000000ff0002 (..., -3.28683e-33, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x3d3c35348d8c8b8a1d58000000000085 (..., -8.66176e-31, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0xff00008591908f8e1f5917000000ff00 (..., -2.28077e-28, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x848382810000000000fffeff090501fd (-3.09178e-36, ...) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x888786852b2a29280000000000fffeff (-8.15664e-34, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x8c8b8a892f2e2d2c1f1e1d1c00000000 (-2.14997e-31, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x908f8e8d00000000fafafafafafafafa (-5.66232e-29, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x01010101010101010101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0xffffffffffffffffffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x02020202020202020202020202020202 <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x91919191919191919191919191919191 <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x92929292929292929292929292929292 <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0x93939393939393939393939393939393 <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0x94949494949494949494949494949494 <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x90909090909090909090909090909090 <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x91919191919191919191919191919191 <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x92929292929292929292929292929292 <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x93939393939393939393939393939393 <- 0x~~~~~~~~~~~~~~~~
+#    v8: 0x0000000000000000ff0000850002ff01 (d8: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00000000000000000000000000fffeff (d9: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#   v10: 0x00000000000000001700000000000000 (d10: 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x00000000000000001f1e1d1c1b1a1918 (d11: 8.56775e-159) <- 0x~~~~~~~~~~~~~~~~
+#    v4: 0x00000000000000009b9a999897969594 (d4: -1.05028e-175) <- 0x~~~~~~~~~~~~~~~~
+#    v5: 0x0000000000000000a3a2a1a09f9e9d9c (d5: -5.00653e-137) <- 0x~~~~~~~~~~~~~~~~
+#    v6: 0x0000000000000000abaaa9a8a7a6a5a4 (d6: -2.43801e-98) <- 0x~~~~~~~~~~~~~~~~
+#    v7: 0x0000000000000000b3b2b1b0afaeadac (d7: -1.16334e-59) <- 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000009a99989796959493 (d26: -1.54211e-180) <- 0x~~~~~~~~~~~~~~~~
+#   v27: 0x0000000000000000a2a1a09f9e9d9c9b (d27: -7.22772e-142) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x0000000000000000aaa9a8a7a6a5a4a3 (d28: -3.58004e-103) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000000000b2b1b0afaeadacab (d29: -1.67978e-64) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0xff0000850002ff01ff0000850002ff01 (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x0000000000fffeff0000000000fffeff (8.28892e-317, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v21: 0x17000000000000001700000000000000 (6.68887e-198, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x1f1e1d1c1b1a19181f1e1d1c1b1a1918 (8.56775e-159, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0xbab9b8b7b6b5b4b3bab9b8b7b6b5b4b3 (-8.31108e-26, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0xc2c1c0bfbebdbcbbc2c1c0bfbebdbcbb (-3.90391e+13, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0xcac9c8c7c6c5c4c3cac9c8c7c6c5c4c3 (-1.92941e+52, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0xd2d1d0cfcecdcccbd2d1d0cfcecdcccb (-9.07279e+90, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v15: 0xb9b8b7b6b5b4b3b2b9b8b7b6b5b4b3b2 (-1.21867e-30, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v16: 0xc1c0bfbebdbcbbbac1c0bfbebdbcbbba (-5.62003e+08, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v17: 0xc9c8c7c6c5c4c3c2c9c8c7c6c5c4c3c2 (-2.82942e+47, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v18: 0xd1d0cfcecdcccbcad1d0cfcecdcccbca (-1.30639e+86, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x00000000000000000002ff010002ff01 (s31: 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#    v0: 0x0000000000000000ff000085ff000085 (s0: -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#    v1: 0x000000000000000000fffeff00fffeff (s1: 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#    v2: 0x00000000000000000000000000000000 (s2: 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0x0000000000000000d5d4d3d2d5d4d3d2 (s28: -2.92508e+13) <- 0x~~~~~~~~~~~~~~~~
+#   v29: 0x0000000000000000d9d8d7d6d9d8d7d6 (s29: -7.62949e+15) <- 0x~~~~~~~~~~~~~~~~
+#   v30: 0x0000000000000000dddcdbdadddcdbda (s30: -1.98932e+18) <- 0x~~~~~~~~~~~~~~~~
+#   v31: 0x0000000000000000e1e0dfdee1e0dfde (s31: -5.18525e+20) <- 0x~~~~~~~~~~~~~~~~
+#   v11: 0x0000000000000000d4d3d2d1d4d3d2d1 (s11: -7.27820e+12) <- 0x~~~~~~~~~~~~~~~~
+#   v12: 0x0000000000000000d8d7d6d5d8d7d6d5 (s12: -1.89854e+15) <- 0x~~~~~~~~~~~~~~~~
+#   v13: 0x0000000000000000dcdbdad9dcdbdad9 (s13: -4.95069e+17) <- 0x~~~~~~~~~~~~~~~~
+#   v14: 0x0000000000000000e0dfdedde0dfdedd (s14: -1.29053e+20) <- 0x~~~~~~~~~~~~~~~~
+#   v19: 0x0000000000000000ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#   v20: 0x00000000000000000002000200020002 <- 0x~~~~~~~~~~~~~~~~
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+#   v22: 0x0000000000000000e2e1e2e1e2e1e2e1 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x0000000000000000e4e3e4e3e4e3e4e3 <- 0x~~~~~~~~~~~~~~~~
+#   v24: 0x0000000000000000e6e5e6e5e6e5e6e5 <- 0x~~~~~~~~~~~~~~~~
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+#   v21: 0x0000000000000000e3e2e3e2e3e2e3e2 <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x0000000000000000e5e4e5e4e5e4e5e4 <- 0x~~~~~~~~~~~~~~~~
+#   v23: 0x0000000000000000e7e6e7e6e7e6e7e6 <- 0x~~~~~~~~~~~~~~~~
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+#   v19: 0x00000000000000000000000000000000 (..., 0.00000, ...) <- 0x~~~~~~~~~~~~~~~~
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+#   v27: 0xf3f2f1f0f3f2f1f0f3f2f1f0f3f2f1f0 (..., -3.84962e+31, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v28: 0xf7f6f5f4f7f6f5f4f7f6f5f4f7f6f5f4 (..., -1.00179e+34, ...) <- 0x~~~~~~~~~~~~~~~~
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+#   v26: 0xf6f5f4f3f6f5f4f3f6f5f4f3f6f5f4f3 (..., -2.49430e+33, ...) <- 0x~~~~~~~~~~~~~~~~
+#   v22: 0x00000000000000000101010101010101 <- 0x~~~~~~~~~~~~~~~~
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+#   v24: 0x00000000000000000202020202020202 <- 0x~~~~~~~~~~~~~~~~
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new file mode 100644
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diff --git a/test/test-trace-reference/log-write-colour b/test/test-trace-reference/log-write-colour
new file mode 100644
index 0000000..01feb9d
--- /dev/null
+++ b/test/test-trace-reference/log-write-colour
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+#   v17:                 0x0000000000000400 -> 0x~~~~~~~~~~~~~~~~
+#   v18:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v19:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v20:                 0x0000000000000020 -> 0x~~~~~~~~~~~~~~~~
+#   v21:                 0x00000000ffff8007 -> 0x~~~~~~~~~~~~~~~~
+#   v31:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    v0:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    v1:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    v9:                 0x0020000000200040 -> 0x~~~~~~~~~~~~~~~~
+#   v10:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v11:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v12:                 0x00000000ffffffff -> 0x~~~~~~~~~~~~~~~~
+#   v13:                 0xffffffffffefffe1 -> 0x~~~~~~~~~~~~~~~~
+#    v2:                 0x0020000000200040 -> 0x~~~~~~~~~~~~~~~~
+#    v3:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    v0:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    v1:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v16:                 0x0000000000007ff9 -> 0x~~~~~~~~~~~~~~~~
+#   v25:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v31:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    v4: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    v5: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    v7: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    v3: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    v4: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    v5: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    v6: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v27: 0x00000000000000fe0001000000010000 -> 0x~~~~~~~~~~~~~~~~
+#   v28: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v29: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v10: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v11: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v12: 0x000000000000000000000000ffffffff -> 0x~~~~~~~~~~~~~~~~
+#   v21: 0x000000000000000000000000ffff8007 -> 0x~~~~~~~~~~~~~~~~
+#   v22: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v23: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v20: 0x00000000000000000000000000000020 -> 0x~~~~~~~~~~~~~~~~
+#   v26: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v27: 0x00000000000000fe0001000000010000 -> 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00000000000000000000000000007ff9 -> 0x~~~~~~~~~~~~~~~~
+#   v25: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v17: 0x00000000000000000000000000000400 -> 0x~~~~~~~~~~~~~~~~
+#   v18: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v29: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v23: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#   v19: 0x00                               -> 0x~~~~~~~~~~~~~~~~
+#   v25:             0x00                   -> 0x~~~~~~~~~~~~~~~~
+#    v4:               0x00                 -> 0x~~~~~~~~~~~~~~~~
+#   v13:                 0xffffffffffefffe1 (d13: -nan) -> 0x~~~~~~~~~~~~~~~~
+#   v30:                 0x0000000000000000 (d30: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v3:                 0x0000000000000000 (d3: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#   v22:                             0x0000 -> 0x~~~~~~~~~~~~~~~~
+#   v31: 0x0000                             -> 0x~~~~~~~~~~~~~~~~
+#   v23:                 0x0000             -> 0x~~~~~~~~~~~~~~~~
+#    v0:                         0x00000000 (s0: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#   v11: 0x00000000                         (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00000000                         (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00                               -> 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00                               -> 0x~~~~~~~~~~~~~~~~
+#    v8: 0x00                               -> 0x~~~~~~~~~~~~~~~~
+#    v9: 0x00                               -> 0x~~~~~~~~~~~~~~~~
+#    v7:                       0x00         -> 0x~~~~~~~~~~~~~~~~
+#    v8:                       0x00         -> 0x~~~~~~~~~~~~~~~~
+#   v25:                 0x0000000000000000 (d25: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#   v26:                 0x0000000000000000 (d26: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#   v17: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#   v18: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    v4:                 0x0000             -> 0x~~~~~~~~~~~~~~~~
+#    v5:                 0x0000             -> 0x~~~~~~~~~~~~~~~~
+#    v0:         0x0000                     -> 0x~~~~~~~~~~~~~~~~
+#    v1:         0x0000                     -> 0x~~~~~~~~~~~~~~~~
+#   v22:                     0x0000         -> 0x~~~~~~~~~~~~~~~~
+#   v23:                     0x0000         -> 0x~~~~~~~~~~~~~~~~
+#   v14: 0x00000000                         (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#   v15: 0x00000000                         (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#   v23: 0x00000000                         (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#   v24: 0x00000000                         (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    v0:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    v1:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#   v31:           0x00                     -> 0x~~~~~~~~~~~~~~~~
+#    v0:           0x00                     -> 0x~~~~~~~~~~~~~~~~
+#    v1:           0x00                     -> 0x~~~~~~~~~~~~~~~~
+#    v4:                     0x00           -> 0x~~~~~~~~~~~~~~~~
+#    v5:                     0x00           -> 0x~~~~~~~~~~~~~~~~
+#    v6:                     0x00           -> 0x~~~~~~~~~~~~~~~~
+#    v5:                             0x00   -> 0x~~~~~~~~~~~~~~~~
+#    v6:                             0x00   -> 0x~~~~~~~~~~~~~~~~
+#    v7:                             0x00   -> 0x~~~~~~~~~~~~~~~~
+#    v5:                 0x0000000000000000 (d5: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v6:                 0x0000000000000000 (d6: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v7:                 0x0000000000000000 (d7: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v6:                 0x0000000000000000 (d6: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v7:                 0x0000000000000000 (d7: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v8:                 0x0000000000000000 (d8: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v0:                 0x0000000000000000 (d0: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v1:                 0x0000000000000000 (d1: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v2:                 0x0020000000200040 (d2: 4.45015e-308) -> 0x~~~~~~~~~~~~~~~~
+#   v31:                     0x0000         -> 0x~~~~~~~~~~~~~~~~
+#    v0:                     0x0000         -> 0x~~~~~~~~~~~~~~~~
+#    v1:                     0x0000         -> 0x~~~~~~~~~~~~~~~~
+#   v14:         0x0000                     -> 0x~~~~~~~~~~~~~~~~
+#   v15:         0x0000                     -> 0x~~~~~~~~~~~~~~~~
+#   v16:         0x0000                     -> 0x~~~~~~~~~~~~~~~~
+#   v21:     0x0000                         -> 0x~~~~~~~~~~~~~~~~
+#   v22:     0x0000                         -> 0x~~~~~~~~~~~~~~~~
+#   v23:     0x0000                         -> 0x~~~~~~~~~~~~~~~~
+#   v21:                         0xffff8007 (s21: -nan) -> 0x~~~~~~~~~~~~~~~~
+#   v22:                         0x00000000 (s22: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#   v23:                         0x00000000 (s23: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#   v11:                 0x00000000         (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#   v12:                 0x00000000         (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#   v13:                 0xffffffff         (..., -nan, ...) -> 0x~~~~~~~~~~~~~~~~
+#   v15:                         0x00000000 (s15: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#   v16:                         0x00007ff9 (s16: 4.59079e-41) -> 0x~~~~~~~~~~~~~~~~
+#   v17:                         0x00000400 (s17: 1.43493e-42) -> 0x~~~~~~~~~~~~~~~~
+#    v0:     0x00                           -> 0x~~~~~~~~~~~~~~~~
+#    v1:     0x00                           -> 0x~~~~~~~~~~~~~~~~
+#    v2:     0x00                           -> 0x~~~~~~~~~~~~~~~~
+#    v3:     0x00                           -> 0x~~~~~~~~~~~~~~~~
+#    v4:           0x00                     -> 0x~~~~~~~~~~~~~~~~
+#    v5:           0x00                     -> 0x~~~~~~~~~~~~~~~~
+#    v6:           0x00                     -> 0x~~~~~~~~~~~~~~~~
+#    v7:           0x00                     -> 0x~~~~~~~~~~~~~~~~
+#    v9:             0x00                   -> 0x~~~~~~~~~~~~~~~~
+#   v10:             0x00                   -> 0x~~~~~~~~~~~~~~~~
+#   v11:             0x00                   -> 0x~~~~~~~~~~~~~~~~
+#   v12:             0x00                   -> 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    v3: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    v4: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    v5: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    v7:                 0x0000000000000000 (d7: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v8:                 0x0000000000000000 (d8: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#    v9:                 0x0020000000200040 (d9: 4.45015e-308) -> 0x~~~~~~~~~~~~~~~~
+#   v10:                 0x0000000000000000 (d10: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#   v31: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    v0: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    v1: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    v2: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    v2:                         0x0020     -> 0x~~~~~~~~~~~~~~~~
+#    v3:                         0x0000     -> 0x~~~~~~~~~~~~~~~~
+#    v4:                         0x0000     -> 0x~~~~~~~~~~~~~~~~
+#    v5:                         0x0000     -> 0x~~~~~~~~~~~~~~~~
+#   v27:                 0x0001             -> 0x~~~~~~~~~~~~~~~~
+#   v28:                 0x0000             -> 0x~~~~~~~~~~~~~~~~
+#   v29:                 0x0000             -> 0x~~~~~~~~~~~~~~~~
+#   v30:                 0x0000             -> 0x~~~~~~~~~~~~~~~~
+#   v24:             0x0000                 -> 0x~~~~~~~~~~~~~~~~
+#   v25:             0x0000                 -> 0x~~~~~~~~~~~~~~~~
+#   v26:             0x0000                 -> 0x~~~~~~~~~~~~~~~~
+#   v27:             0x00fe                 -> 0x~~~~~~~~~~~~~~~~
+#   v18:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#   v19:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#   v20:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#   v21:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    v6:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    v7:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    v8:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#    v9:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#   v25:                 0x00000000         (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#   v26:                 0x00000000         (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#   v27:                 0x00010000         (..., 9.18355e-41, ...) -> 0x~~~~~~~~~~~~~~~~
+#   v28:                 0x00000000         (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
diff --git a/test/test-utils-a64.cc b/test/test-utils-a64.cc
index 9de5b44..0d03dea 100644
--- a/test/test-utils-a64.cc
+++ b/test/test-utils-a64.cc
@@ -430,7 +430,7 @@
   __ Str(tmp, MemOperand(dump_base, flags_offset));
 
   // To dump the values that were in tmp amd dump, we need a new scratch
-  // register.  We can use any of the already dumped registers since we can
+  // register. We can use any of the already dumped registers since we can
   // easily restore them.
   Register dump2_base = x10;
   Register dump2 = x11;
diff --git a/third_party/android/Android.mk.template b/third_party/android/Android.mk.template
index 9a1cee6..5a627de 100644
--- a/third_party/android/Android.mk.template
+++ b/third_party/android/Android.mk.template
@@ -221,6 +221,6 @@
 .PHONY: run-vixl-tests
 run-vixl-tests: vixl-test-runner
 	$(vixl_root)/third_party/android/check_top_level_android_mk.sh
-	$(HOST_OUT)/bin/vixl-test-runner --run_all
-	$(HOST_OUT)/bin/vixl-test-runner --run_all --debugger
+	cd $(vixl_root) && $(ANDROID_BUILD_TOP)/$(HOST_OUT)/bin/vixl-test-runner --run_all
+	cd $(vixl_root) && $(ANDROID_BUILD_TOP)/$(HOST_OUT)/bin/vixl-test-runner --run_all --debugger
 	@echo vixl tests PASSED
diff --git a/tools/clang_format.py b/tools/clang_format.py
new file mode 100755
index 0000000..50dc0eb
--- /dev/null
+++ b/tools/clang_format.py
@@ -0,0 +1,193 @@
+#!/usr/bin/env python2.7
+
+# Copyright 2016, ARM Limited
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+#   * Redistributions of source code must retain the above copyright notice,
+#     this list of conditions and the following disclaimer.
+#   * Redistributions in binary form must reproduce the above copyright notice,
+#     this list of conditions and the following disclaimer in the documentation
+#     and/or other materials provided with the distribution.
+#   * Neither the name of ARM Limited nor the names of its contributors may be
+#     used to endorse or promote products derived from this software without
+#     specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
+# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import argparse
+import fnmatch
+import multiprocessing
+import os
+import signal
+import subprocess
+import sys
+import tempfile
+
+import config
+import git
+import printer
+import util
+
+
+is_output_redirected = not sys.stdout.isatty()
+
+# Catch SIGINT to gracefully exit when ctrl+C is pressed.
+def sigint_handler(signal, frame):
+  sys.exit(1)
+signal.signal(signal.SIGINT, sigint_handler)
+
+def BuildOptions():
+  parser = argparse.ArgumentParser(
+    description = '''This tool runs `clang-format` on C++ files.
+    If no files are provided on the command-line, all C++ source files in `src`,
+    `sample`, and `benchmarks` are processed.
+    When available, `colordiff` is automatically used to clour the output.''',
+    # Print default values.
+    formatter_class = argparse.ArgumentDefaultsHelpFormatter)
+  parser.add_argument('files', nargs = '*')
+  parser.add_argument('--in-place', '-i',
+                      action = 'store_true', default = False,
+                      help = 'Edit files in place.')
+  parser.add_argument('--jobs', '-j', metavar = 'N', type = int, nargs = '?',
+                      default = multiprocessing.cpu_count(),
+                      const = multiprocessing.cpu_count(),
+                      help = '''Runs the tests using N jobs. If the option is set
+                      but no value is provided, the script will use as many jobs
+                      as it thinks useful.''')
+  return parser.parse_args()
+
+
+# Returns 0 if the file is correctly formatted, or 1 otherwise.
+def ClangFormat(filename, in_place = False, progress_prefix = ''):
+  rc = 0
+  printer.PrintOverwritableLine('Processing %s' % filename,
+                                type = printer.LINE_TYPE_LINTER)
+
+  cmd_format = ['clang-format-3.6', filename]
+  temp_file, temp_file_name = tempfile.mkstemp(prefix = 'clang_format_')
+  cmd_format_string = '$ ' + ' '.join(cmd_format) + ' > %s' % temp_file_name
+  p_format = subprocess.Popen(cmd_format,
+                              stdout = temp_file, stderr = subprocess.STDOUT)
+
+  rc += p_format.wait()
+
+  cmd_diff = ['diff', '--unified', filename, temp_file_name]
+  cmd_diff_string = '$ ' + ' '.join(cmd_diff)
+  p_diff = subprocess.Popen(cmd_diff,
+                            stdout = subprocess.PIPE, stderr = subprocess.STDOUT)
+
+  if util.IsCommandAvailable('colordiff') and not is_output_redirected:
+    p_colordiff = subprocess.Popen(
+            ['colordiff', '--unified'],
+            stdin = p_diff.stdout,
+            stdout = subprocess.PIPE, stderr = subprocess.STDOUT)
+    out, unused = p_colordiff.communicate()
+  else:
+    out, unused = p_diff.communicate()
+
+  rc += p_diff.wait()
+
+  if in_place:
+      cmd_format = ['clang-format-3.6', '-i', filename]
+      p_format = subprocess.Popen(cmd_format,
+                                  stdout=temp_file, stderr=subprocess.STDOUT)
+
+  if rc != 0:
+    printer.Print('Incorrectly formatted file: ' + filename + '\n' + \
+                  cmd_format_string + '\n' + \
+                  cmd_diff_string + '\n' + \
+                  out)
+
+  return 0 if rc == 0 else 1
+
+
+# The multiprocessing map_async function does not allow passing multiple
+# arguments directly, so use a wrapper.
+def ClangFormatWrapper(args):
+  # Run under a try-catch  to avoid flooding the output when the script is
+  # interrupted from the keyboard with ctrl+C.
+  try:
+    return ClangFormat(*args)
+  except:
+    sys.exit(1)
+
+
+# Returns the total number of files incorrectly formatted.
+def ClangFormatFiles(files, in_place = False, jobs = 1, progress_prefix = ''):
+  if not util.IsCommandAvailable('clang-format-3.6'):
+    print(
+      printer.COLOUR_RED + \
+      ("`clang-format-3.6` not found. Please ensure it is installed "
+       "and in your PATH.") + \
+      printer.NO_COLOUR)
+    return -1
+
+  pool = multiprocessing.Pool(jobs)
+  # The '.get(9999999)' is workaround to allow killing the test script with
+  # ctrl+C from the shell. This bug is documented at
+  # http://bugs.python.org/issue8296.
+  tasks = [(f, in_place, progress_prefix) for f in files]
+  # Run under a try-catch  to avoid flooding the output when the script is
+  # interrupted from the keyboard with ctrl+C.
+  try:
+    results = pool.map_async(ClangFormatWrapper, tasks).get(9999999)
+    pool.close()
+    pool.join()
+  except KeyboardInterrupt:
+    pool.terminate()
+    sys.exit(1)
+  rc = sum(results)
+
+  printer.PrintOverwritableLine(
+      progress_prefix + '%d files are incorrectly formatted.' % rc,
+      type = printer.LINE_TYPE_LINTER)
+  printer.EnsureNewLine()
+  return rc
+
+
+def Find(path, filters = ['*']):
+  files_found = []
+
+  def NameMatchesAnyFilter(name, ff):
+    for f in ff:
+      if fnmatch.fnmatch(name, f):
+        return True
+    return False
+
+  for root, dirs, files in os.walk(path):
+    files_found += [os.path.relpath(os.path.join(root, fn))
+                    for fn in files if NameMatchesAnyFilter(fn, filters)]
+  return files_found
+
+
+def GetCppSourceFilesToFormat():
+  sources = []
+  source_dirs = [config.dir_benchmarks,
+                 config.dir_examples,
+                 config.dir_src_vixl ]
+  for directory in source_dirs:
+    sources += Find(directory, ['*.h', '*.cc'])
+  return sources
+
+
+if __name__ == '__main__':
+  # Parse the arguments.
+  args = BuildOptions()
+  files = args.files
+  if not files:
+    files = GetCppSourceFilesToFormat()
+
+  rc = ClangFormatFiles(files, in_place = args.in_place, jobs = args.jobs)
+  sys.exit(rc)
diff --git a/tools/generate_simulator_traces.py b/tools/generate_simulator_traces.py
index de017d4..aaccb14 100755
--- a/tools/generate_simulator_traces.py
+++ b/tools/generate_simulator_traces.py
@@ -106,7 +106,8 @@
 
 def BuildOptions(root):
   result = argparse.ArgumentParser(description = 'Simulator test generator.')
-  result.add_argument('--runner', action='store', default=root+'/test-runner',
+  result.add_argument('--runner', action='store',
+                      default=os.path.join(root, 'obj/latest/test/test-runner'),
                       help='The test executable to run.')
   result.add_argument('--out', action='store',
                       default='test/test-simulator-traces-a64.h')
@@ -120,8 +121,8 @@
 
   args = BuildOptions(root_dir)
 
-  # Run each simulator test (SIM_*) with the --sim_test_trace option, and use
-  # the output to create the traces header (from --out). In addition, the
+  # Run each simulator test (SIM_*) with the --generate_test_trace option, and
+  # use the output to create the traces header (from --out). In addition, the
   # test-simulator-traces-a64.h file, the master trace file, which includes all
   # other trace files is generated.
 
@@ -140,7 +141,7 @@
   for test in tests:
     # Run each test.
     print 'Generating trace for ' + test;
-    cmd = ' '.join([args.runner, '--sim_test_trace', test])
+    cmd = ' '.join([args.runner, '--generate_test_trace', test])
     status, output = util.getstatusoutput(cmd)
     if status != 0: util.abort('Failed to run ' + cmd + '.')
 
diff --git a/tools/generate_test_trace_a64_reference.py b/tools/generate_test_trace_a64_reference.py
new file mode 100755
index 0000000..fd2bdb7
--- /dev/null
+++ b/tools/generate_test_trace_a64_reference.py
@@ -0,0 +1,77 @@
+#!/usr/bin/env python2.7
+
+# Copyright 2016, ARM Limited
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+#   * Redistributions of source code must retain the above copyright notice,
+#     this list of conditions and the following disclaimer.
+#   * Redistributions in binary form must reproduce the above copyright notice,
+#     this list of conditions and the following disclaimer in the documentation
+#     and/or other materials provided with the distribution.
+#   * Neither the name of ARM Limited nor the names of its contributors may be
+#     used to endorse or promote products derived from this software without
+#     specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
+# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import os
+import sys
+import argparse
+import re
+import util
+
+
+def BuildOptions(root):
+  result = argparse.ArgumentParser(
+      description = 'Generate reference output for TRACE_* tests')
+  result.add_argument('--runner', action='store',
+                      default=os.path.join(root, 'obj/latest/test/test-runner'),
+                      help='The test executable to run.')
+  result.add_argument('--outdir', action='store',
+                      default='test/test-trace-reference/')
+  return result.parse_args()
+
+if __name__ == '__main__':
+  root_dir = os.path.dirname(os.path.dirname(os.path.abspath(sys.argv[0])))
+  os.chdir(root_dir)
+
+  args = BuildOptions(root_dir)
+
+  # Run each trace test (TRACE_*) with the --generate_test_trace option, and
+  # use the output to create the reference traces (in --outdir).
+
+  # Find the trace tests.
+  status, output = util.getstatusoutput(args.runner + ' --list')
+  if status != 0: util.abort('Failed to list all tests')
+  tests = filter(lambda t: 'TRACE_' in t, output.split())
+  tests.sort()
+
+  if not os.path.exists(args.outdir):
+    os.makedirs(args.outdir)
+
+  for test in tests:
+    # Run each test.
+    print 'Generating trace for ' + test;
+    cmd = ' '.join([args.runner, '--generate_test_trace', test])
+    status, output = util.getstatusoutput(cmd)
+    if status != 0: util.abort('Failed to run ' + cmd + '.')
+
+    # Create a new trace header file.
+    trace_filename = 'log-' + test.replace('TRACE_', '').lower().replace('_', '-')
+    trace_f =  open(os.path.join(args.outdir, trace_filename), 'w')
+    trace_f.write(output)
+    # `getstatusoutput` removes the trailing newline. Put it back, but only if
+    # the output was not empty.
+    if len(output) > 0: trace_f.write('\n')
diff --git a/tools/lint.py b/tools/lint.py
index 36c5358..fa99525 100755
--- a/tools/lint.py
+++ b/tools/lint.py
@@ -45,18 +45,21 @@
 signal.signal(signal.SIGINT, sigint_handler)
 
 def BuildOptions():
-  result = argparse.ArgumentParser(
+  parser = argparse.ArgumentParser(
       description =
-      '''This tool lints the C++ files tracked by the git repository, and
-      produces a summary of the errors found.''',
+      '''This tool lints C++ files and produces a summary of the errors found.
+      If no files are provided on the command-line, all C++ source files in the
+      repository are processed.''',
       # Print default values.
       formatter_class=argparse.ArgumentDefaultsHelpFormatter)
-  result.add_argument('--jobs', '-j', metavar='N', type=int, nargs='?',
-                      default=1, const=multiprocessing.cpu_count(),
+  parser.add_argument('files', nargs = '*')
+  parser.add_argument('--jobs', '-j', metavar='N', type=int, nargs='?',
+                      default=multiprocessing.cpu_count(),
+                      const=multiprocessing.cpu_count(),
                       help='''Runs the tests using N jobs. If the option is set
                       but no value is provided, the script will use as many jobs
                       as it thinks useful.''')
-  return result.parse_args()
+  return parser.parse_args()
 
 
 
@@ -178,9 +181,10 @@
   # Parse the arguments.
   args = BuildOptions()
 
-  retcode, default_tracked_files = GetDefaultTrackedFiles()
-  if retcode:
-    sys.exit(retcode)
-  retcode = LintFiles(default_tracked_files,
-                      jobs = args.jobs)
+  files = args.files
+  if not files:
+    retcode, files = GetDefaultTrackedFiles()
+    if retcode:
+      sys.exit(retcode)
+  retcode = LintFiles(files, jobs = args.jobs)
   sys.exit(retcode)
diff --git a/tools/make_instruction_doc.pl b/tools/make_instruction_doc.pl
index 8ecc8c4..d5c2c67 100755
--- a/tools/make_instruction_doc.pl
+++ b/tools/make_instruction_doc.pl
@@ -26,6 +26,9 @@
 # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+use v5.10.1;
+no warnings 'experimental::smartmatch';
+
 # Assembler header file.
 my $hfile = "src/vixl/a64/assembler-a64.h";
 
@@ -35,7 +38,7 @@
 my %inst = ();  # Global hash of instructions.
 
 $/ = '';
-open(IN, "<$hfile") or die("Can't open header file $header.\n");
+open(IN, "<$hfile") or die("Can't open header file $hfile.\n");
 while(<IN>)
 {
   # Find a function formatted like an instruction.
diff --git a/tools/test.py b/tools/test.py
index b4e9da9..b89ac08 100755
--- a/tools/test.py
+++ b/tools/test.py
@@ -40,6 +40,7 @@
 import time
 
 import config
+import clang_format
 import lint
 import printer
 import test
@@ -178,7 +179,7 @@
 def BuildOptions():
   args = argparse.ArgumentParser(
     description =
-    '''This tool runs all tests matching the speficied filters for multiple
+    '''This tool runs all tests matching the specified filters for multiple
     environment, build options, and runtime options configurations.''',
     # Print default values.
     formatter_class=argparse.ArgumentDefaultsHelpFormatter)
@@ -204,12 +205,13 @@
 
   general_arguments = args.add_argument_group('General options')
   general_arguments.add_argument('--fast', action='store_true',
-                                 help='''Skip the lint tests, and run only with
-                                 one compiler, in one mode, with one C++
-                                 standard, and with an appropriate default for
-                                 runtime options. The compiler, mode, and C++
-                                 standard used are the first ones provided to
-                                 the script or in the default arguments.''')
+                                 help='''Skip the lint and clang-format tests,
+                                 and run only with one compiler, in one mode,
+                                 with one C++ standard, and with an appropriate
+                                 default for runtime options. The compiler,
+                                 mode, and C++ standard used are the first ones
+                                 provided to the script or in the default
+                                 arguments.''')
   general_arguments.add_argument(
     '--jobs', '-j', metavar='N', type=int, nargs='?',
     default=multiprocessing.cpu_count(),
@@ -220,6 +222,8 @@
                                  help='Do not run benchmarks.')
   general_arguments.add_argument('--nolint', action='store_true',
                                  help='Do not run the linter.')
+  general_arguments.add_argument('--noclang-format', action='store_true',
+                                 help='Do not run clang-format.')
   general_arguments.add_argument('--notest', action='store_true',
                                  help='Do not run tests.')
   sim_default = 'off' if platform.machine() == 'aarch64' else 'on'
@@ -323,6 +327,12 @@
                         jobs = args.jobs, progress_prefix = 'cpp lint: ')
 
 
+def RunClangFormat():
+  return clang_format.ClangFormatFiles(clang_format.GetCppSourceFilesToFormat(),
+                                       jobs = args.jobs,
+                                       progress_prefix = 'clang-format: ')
+
+
 
 def BuildAll(build_options, jobs):
   scons_command = ["scons", "-C", dir_root, 'all', '-j', str(jobs)]
@@ -368,6 +378,8 @@
 
   if not args.nolint and not args.fast:
     rc |= RunLinter()
+  if not args.noclang_format and not args.fast:
+    rc |= RunClangFormat()
 
   # Don't try to test the debugger if we are not running with the simulator.
   if not args.simulator:
diff --git a/tools/util.py b/tools/util.py
index 6862b89..6a71360 100644
--- a/tools/util.py
+++ b/tools/util.py
@@ -52,6 +52,11 @@
     return e.returncode, e.output.rstrip('\n')
 
 
+def IsCommandAvailable(command):
+    retcode, unused_output = getstatusoutput('which %s' % command)
+    return retcode == 0
+
+
 def ensure_dir(path_name):
   if not os.path.exists(path_name):
     os.makedirs(path_name)