Enable test cases for
LD1/ST1 (multiple 1-elem structs to/from 2 regs
LD1/ST1 (multiple 1-elem structs to/from 3 regs
LD1/ST1 (multiple 1-elem structs to/from 4 regs
LD1R (single structure, replicate)
LD2R (single structure, replicate)
LD3R (single structure, replicate)
LD4R (single structure, replicate)
LD1/ST1 (single structure, to/from one lane)
LD2/ST2 (single structure, to/from one lane)
LD3/ST3 (single structure, to/from one lane)
LD4/ST4 (single structure, to/from one lane)
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@14667 a5019735-40e9-0310-863c-91ae7b9d1cf9
diff --git a/none/tests/arm64/memory.c b/none/tests/arm64/memory.c
index 9ac4818..c1453c2 100644
--- a/none/tests/arm64/memory.c
+++ b/none/tests/arm64/memory.c
@@ -987,212 +987,212 @@
////////////////////////////////////////////////////////////////
printf("LD1/ST1 (multiple 1-elem structs to/from 2/3/4 regs\n");
-//MEM_TEST("st1 {v19.2d, v20.2d}, [x5]", 17, 7)
-//MEM_TEST("st1 {v19.2d, v20.2d}, [x5], #32", 9, 9)
-//MEM_TEST("st1 {v19.2d, v20.2d}, [x5], x6", -13, -5)
-//
-//MEM_TEST("st1 {v17.2d, v18.2d, v19.2d}, [x5]", 17, 7)
-//MEM_TEST("st1 {v17.2d, v18.2d, v19.2d}, [x5], #48", 9, 9)
-//MEM_TEST("st1 {v17.2d, v18.2d, v19.2d}, [x5], x6", -13, -5)
-//
-//MEM_TEST("st1 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5]", 17, 7)
-//MEM_TEST("st1 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], #64", 9, 9)
-//MEM_TEST("st1 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], x6", -13, -5)
-//
-//
-//MEM_TEST("st1 {v19.1d, v20.1d}, [x5]", 17, 7)
-//MEM_TEST("st1 {v19.1d, v20.1d}, [x5], #16", 9, 9)
-//MEM_TEST("st1 {v19.1d, v20.1d}, [x5], x6", -13, -5)
-//
-//MEM_TEST("st1 {v17.1d, v18.1d, v19.1d}, [x5]", 17, 7)
-//MEM_TEST("st1 {v17.1d, v18.1d, v19.1d}, [x5], #24", 9, 9)
-//MEM_TEST("st1 {v17.1d, v18.1d, v19.1d}, [x5], x6", -13, -5)
-//
-//MEM_TEST("st1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x5]", 17, 7)
-//MEM_TEST("st1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x5], #32", 9, 9)
-//MEM_TEST("st1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x5], x6", -13, -5)
-//
-//
-//MEM_TEST("st1 {v19.4s, v20.4s}, [x5]", 17, 7)
-//MEM_TEST("st1 {v19.4s, v20.4s}, [x5], #32", 9, 9)
-//MEM_TEST("st1 {v19.4s, v20.4s}, [x5], x6", -13, -5)
-//
-//MEM_TEST("st1 {v17.4s, v18.4s, v19.4s}, [x5]", 17, 7)
-//MEM_TEST("st1 {v17.4s, v18.4s, v19.4s}, [x5], #48", 9, 9)
-//MEM_TEST("st1 {v17.4s, v18.4s, v19.4s}, [x5], x6", -13, -5)
-//
-//MEM_TEST("st1 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5]", 17, 7)
-//MEM_TEST("st1 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], #64", 9, 9)
-//MEM_TEST("st1 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], x6", -13, -5)
-//
-//
-//MEM_TEST("st1 {v19.2s, v20.2s}, [x5]", 17, 7)
-//MEM_TEST("st1 {v19.2s, v20.2s}, [x5], #16", 9, 9)
-//MEM_TEST("st1 {v19.2s, v20.2s}, [x5], x6", -13, -5)
-//
-//MEM_TEST("st1 {v17.2s, v18.2s, v19.2s}, [x5]", 17, 7)
-//MEM_TEST("st1 {v17.2s, v18.2s, v19.2s}, [x5], #24", 9, 9)
-//MEM_TEST("st1 {v17.2s, v18.2s, v19.2s}, [x5], x6", -13, -5)
-//
-//MEM_TEST("st1 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5]", 17, 7)
-//MEM_TEST("st1 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], #32", 9, 9)
-//MEM_TEST("st1 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], x6", -13, -5)
-//
-//
-//MEM_TEST("st1 {v19.8h, v20.8h}, [x5]", 17, 7)
-//MEM_TEST("st1 {v19.8h, v20.8h}, [x5], #32", 9, 9)
-//MEM_TEST("st1 {v19.8h, v20.8h}, [x5], x6", -13, -5)
-//
-//MEM_TEST("st1 {v17.8h, v18.8h, v19.8h}, [x5]", 17, 7)
-//MEM_TEST("st1 {v17.8h, v18.8h, v19.8h}, [x5], #48", 9, 9)
-//MEM_TEST("st1 {v17.8h, v18.8h, v19.8h}, [x5], x6", -13, -5)
-//
-//MEM_TEST("st1 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5]", 17, 7)
-//MEM_TEST("st1 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], #64", 9, 9)
-//MEM_TEST("st1 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], x6", -13, -5)
-//
-//
-//MEM_TEST("st1 {v19.4h, v20.4h}, [x5]", 17, 7)
-//MEM_TEST("st1 {v19.4h, v20.4h}, [x5], #16", 9, 9)
-//MEM_TEST("st1 {v19.4h, v20.4h}, [x5], x6", -13, -5)
-//
-//MEM_TEST("st1 {v17.4h, v18.4h, v19.4h}, [x5]", 17, 7)
-//MEM_TEST("st1 {v17.4h, v18.4h, v19.4h}, [x5], #24", 9, 9)
-//MEM_TEST("st1 {v17.4h, v18.4h, v19.4h}, [x5], x6", -13, -5)
-//
-//MEM_TEST("st1 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5]", 17, 7)
-//MEM_TEST("st1 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], #32", 9, 9)
-//MEM_TEST("st1 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], x6", -13, -5)
+MEM_TEST("st1 {v19.2d, v20.2d}, [x5]", 17, 7)
+MEM_TEST("st1 {v19.2d, v20.2d}, [x5], #32", 9, 9)
+MEM_TEST("st1 {v19.2d, v20.2d}, [x5], x6", -13, -5)
+
+MEM_TEST("st1 {v17.2d, v18.2d, v19.2d}, [x5]", 17, 7)
+MEM_TEST("st1 {v17.2d, v18.2d, v19.2d}, [x5], #48", 9, 9)
+MEM_TEST("st1 {v17.2d, v18.2d, v19.2d}, [x5], x6", -13, -5)
+
+MEM_TEST("st1 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5]", 17, 7)
+MEM_TEST("st1 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], #64", 9, 9)
+MEM_TEST("st1 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], x6", -13, -5)
+
+
+MEM_TEST("st1 {v19.1d, v20.1d}, [x5]", 17, 7)
+MEM_TEST("st1 {v19.1d, v20.1d}, [x5], #16", 9, 9)
+MEM_TEST("st1 {v19.1d, v20.1d}, [x5], x6", -13, -5)
+
+MEM_TEST("st1 {v17.1d, v18.1d, v19.1d}, [x5]", 17, 7)
+MEM_TEST("st1 {v17.1d, v18.1d, v19.1d}, [x5], #24", 9, 9)
+MEM_TEST("st1 {v17.1d, v18.1d, v19.1d}, [x5], x6", -13, -5)
+
+MEM_TEST("st1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x5]", 17, 7)
+MEM_TEST("st1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x5], #32", 9, 9)
+MEM_TEST("st1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x5], x6", -13, -5)
+
+
+MEM_TEST("st1 {v19.4s, v20.4s}, [x5]", 17, 7)
+MEM_TEST("st1 {v19.4s, v20.4s}, [x5], #32", 9, 9)
+MEM_TEST("st1 {v19.4s, v20.4s}, [x5], x6", -13, -5)
+
+MEM_TEST("st1 {v17.4s, v18.4s, v19.4s}, [x5]", 17, 7)
+MEM_TEST("st1 {v17.4s, v18.4s, v19.4s}, [x5], #48", 9, 9)
+MEM_TEST("st1 {v17.4s, v18.4s, v19.4s}, [x5], x6", -13, -5)
+
+MEM_TEST("st1 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5]", 17, 7)
+MEM_TEST("st1 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], #64", 9, 9)
+MEM_TEST("st1 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], x6", -13, -5)
+
+
+MEM_TEST("st1 {v19.2s, v20.2s}, [x5]", 17, 7)
+MEM_TEST("st1 {v19.2s, v20.2s}, [x5], #16", 9, 9)
+MEM_TEST("st1 {v19.2s, v20.2s}, [x5], x6", -13, -5)
+
+MEM_TEST("st1 {v17.2s, v18.2s, v19.2s}, [x5]", 17, 7)
+MEM_TEST("st1 {v17.2s, v18.2s, v19.2s}, [x5], #24", 9, 9)
+MEM_TEST("st1 {v17.2s, v18.2s, v19.2s}, [x5], x6", -13, -5)
+
+MEM_TEST("st1 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5]", 17, 7)
+MEM_TEST("st1 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], #32", 9, 9)
+MEM_TEST("st1 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], x6", -13, -5)
+
+
+MEM_TEST("st1 {v19.8h, v20.8h}, [x5]", 17, 7)
+MEM_TEST("st1 {v19.8h, v20.8h}, [x5], #32", 9, 9)
+MEM_TEST("st1 {v19.8h, v20.8h}, [x5], x6", -13, -5)
+
+MEM_TEST("st1 {v17.8h, v18.8h, v19.8h}, [x5]", 17, 7)
+MEM_TEST("st1 {v17.8h, v18.8h, v19.8h}, [x5], #48", 9, 9)
+MEM_TEST("st1 {v17.8h, v18.8h, v19.8h}, [x5], x6", -13, -5)
+
+MEM_TEST("st1 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5]", 17, 7)
+MEM_TEST("st1 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], #64", 9, 9)
+MEM_TEST("st1 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], x6", -13, -5)
+
+
+MEM_TEST("st1 {v19.4h, v20.4h}, [x5]", 17, 7)
+MEM_TEST("st1 {v19.4h, v20.4h}, [x5], #16", 9, 9)
+MEM_TEST("st1 {v19.4h, v20.4h}, [x5], x6", -13, -5)
+
+MEM_TEST("st1 {v17.4h, v18.4h, v19.4h}, [x5]", 17, 7)
+MEM_TEST("st1 {v17.4h, v18.4h, v19.4h}, [x5], #24", 9, 9)
+MEM_TEST("st1 {v17.4h, v18.4h, v19.4h}, [x5], x6", -13, -5)
+
+MEM_TEST("st1 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5]", 17, 7)
+MEM_TEST("st1 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], #32", 9, 9)
+MEM_TEST("st1 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], x6", -13, -5)
MEM_TEST("st1 {v19.16b, v20.16b}, [x5]", 17, 7)
MEM_TEST("st1 {v19.16b, v20.16b}, [x5], #32", 9, 9)
-//MEM_TEST("st1 {v19.16b, v20.16b}, [x5], x6", -13, -5)
+MEM_TEST("st1 {v19.16b, v20.16b}, [x5], x6", -13, -5)
MEM_TEST("st1 {v17.16b, v18.16b, v19.16b}, [x5]", 17, 7)
-//MEM_TEST("st1 {v17.16b, v18.16b, v19.16b}, [x5], #48", 9, 9)
-//MEM_TEST("st1 {v17.16b, v18.16b, v19.16b}, [x5], x6", -13, -5)
-//
-//MEM_TEST("st1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5]", 17, 7)
-//MEM_TEST("st1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], #64", 9, 9)
-//MEM_TEST("st1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], x6", -13, -5)
-//
-//
-//MEM_TEST("st1 {v19.8b, v20.8b}, [x5]", 17, 7)
-//MEM_TEST("st1 {v19.8b, v20.8b}, [x5], #16", 9, 9)
-//MEM_TEST("st1 {v19.8b, v20.8b}, [x5], x6", -13, -5)
-//
-//MEM_TEST("st1 {v17.8b, v18.8b, v19.8b}, [x5]", 17, 7)
-//MEM_TEST("st1 {v17.8b, v18.8b, v19.8b}, [x5], #24", 9, 9)
-//MEM_TEST("st1 {v17.8b, v18.8b, v19.8b}, [x5], x6", -13, -5)
-//
-//MEM_TEST("st1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5]", 17, 7)
-//MEM_TEST("st1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], #32", 9, 9)
-//MEM_TEST("st1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], x6", -13, -5)
-//
-//
-//MEM_TEST("ld1 {v19.2d, v20.2d}, [x5]", 17, 7)
-//MEM_TEST("ld1 {v19.2d, v20.2d}, [x5], #32", 9, 9)
-//MEM_TEST("ld1 {v19.2d, v20.2d}, [x5], x6", -13, -5)
-//
-//MEM_TEST("ld1 {v17.2d, v18.2d, v19.2d}, [x5]", 17, 7)
-//MEM_TEST("ld1 {v17.2d, v18.2d, v19.2d}, [x5], #48", 9, 9)
-//MEM_TEST("ld1 {v17.2d, v18.2d, v19.2d}, [x5], x6", -13, -5)
-//
-//MEM_TEST("ld1 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5]", 17, 7)
-//MEM_TEST("ld1 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], #64", 9, 9)
-//MEM_TEST("ld1 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], x6", -13, -5)
-//
-//
-//MEM_TEST("ld1 {v19.1d, v20.1d}, [x5]", 17, 7)
-//MEM_TEST("ld1 {v19.1d, v20.1d}, [x5], #16", 9, 9)
-//MEM_TEST("ld1 {v19.1d, v20.1d}, [x5], x6", -13, -5)
-//
-//MEM_TEST("ld1 {v17.1d, v18.1d, v19.1d}, [x5]", 17, 7)
-//MEM_TEST("ld1 {v17.1d, v18.1d, v19.1d}, [x5], #24", 9, 9)
-//MEM_TEST("ld1 {v17.1d, v18.1d, v19.1d}, [x5], x6", -13, -5)
-//
-//MEM_TEST("ld1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x5]", 17, 7)
-//MEM_TEST("ld1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x5], #32", 9, 9)
-//MEM_TEST("ld1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x5], x6", -13, -5)
-//
-//
-//MEM_TEST("ld1 {v19.4s, v20.4s}, [x5]", 17, 7)
-//MEM_TEST("ld1 {v19.4s, v20.4s}, [x5], #32", 9, 9)
-//MEM_TEST("ld1 {v19.4s, v20.4s}, [x5], x6", -13, -5)
-//
-//MEM_TEST("ld1 {v17.4s, v18.4s, v19.4s}, [x5]", 17, 7)
-//MEM_TEST("ld1 {v17.4s, v18.4s, v19.4s}, [x5], #48", 9, 9)
-//MEM_TEST("ld1 {v17.4s, v18.4s, v19.4s}, [x5], x6", -13, -5)
-//
-//MEM_TEST("ld1 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5]", 17, 7)
-//MEM_TEST("ld1 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], #64", 9, 9)
-//MEM_TEST("ld1 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], x6", -13, -5)
-//
-//
-//MEM_TEST("ld1 {v19.2s, v20.2s}, [x5]", 17, 7)
-//MEM_TEST("ld1 {v19.2s, v20.2s}, [x5], #16", 9, 9)
-//MEM_TEST("ld1 {v19.2s, v20.2s}, [x5], x6", -13, -5)
-//
-//MEM_TEST("ld1 {v17.2s, v18.2s, v19.2s}, [x5]", 17, 7)
-//MEM_TEST("ld1 {v17.2s, v18.2s, v19.2s}, [x5], #24", 9, 9)
-//MEM_TEST("ld1 {v17.2s, v18.2s, v19.2s}, [x5], x6", -13, -5)
-//
-//MEM_TEST("ld1 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5]", 17, 7)
-//MEM_TEST("ld1 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], #32", 9, 9)
-//MEM_TEST("ld1 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], x6", -13, -5)
-//
-//
-//MEM_TEST("ld1 {v19.8h, v20.8h}, [x5]", 17, 7)
-//MEM_TEST("ld1 {v19.8h, v20.8h}, [x5], #32", 9, 9)
-//MEM_TEST("ld1 {v19.8h, v20.8h}, [x5], x6", -13, -5)
-//
-//MEM_TEST("ld1 {v17.8h, v18.8h, v19.8h}, [x5]", 17, 7)
-//MEM_TEST("ld1 {v17.8h, v18.8h, v19.8h}, [x5], #48", 9, 9)
-//MEM_TEST("ld1 {v17.8h, v18.8h, v19.8h}, [x5], x6", -13, -5)
-//
-//MEM_TEST("ld1 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5]", 17, 7)
-//MEM_TEST("ld1 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], #64", 9, 9)
-//MEM_TEST("ld1 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], x6", -13, -5)
-//
-//
-//MEM_TEST("ld1 {v19.4h, v20.4h}, [x5]", 17, 7)
-//MEM_TEST("ld1 {v19.4h, v20.4h}, [x5], #16", 9, 9)
-//MEM_TEST("ld1 {v19.4h, v20.4h}, [x5], x6", -13, -5)
-//
-//MEM_TEST("ld1 {v17.4h, v18.4h, v19.4h}, [x5]", 17, 7)
-//MEM_TEST("ld1 {v17.4h, v18.4h, v19.4h}, [x5], #24", 9, 9)
-//MEM_TEST("ld1 {v17.4h, v18.4h, v19.4h}, [x5], x6", -13, -5)
-//
-//MEM_TEST("ld1 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5]", 17, 7)
-//MEM_TEST("ld1 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], #32", 9, 9)
-//MEM_TEST("ld1 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], x6", -13, -5)
+MEM_TEST("st1 {v17.16b, v18.16b, v19.16b}, [x5], #48", 9, 9)
+MEM_TEST("st1 {v17.16b, v18.16b, v19.16b}, [x5], x6", -13, -5)
+
+MEM_TEST("st1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5]", 17, 7)
+MEM_TEST("st1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], #64", 9, 9)
+MEM_TEST("st1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], x6", -13, -5)
+
+
+MEM_TEST("st1 {v19.8b, v20.8b}, [x5]", 17, 7)
+MEM_TEST("st1 {v19.8b, v20.8b}, [x5], #16", 9, 9)
+MEM_TEST("st1 {v19.8b, v20.8b}, [x5], x6", -13, -5)
+
+MEM_TEST("st1 {v17.8b, v18.8b, v19.8b}, [x5]", 17, 7)
+MEM_TEST("st1 {v17.8b, v18.8b, v19.8b}, [x5], #24", 9, 9)
+MEM_TEST("st1 {v17.8b, v18.8b, v19.8b}, [x5], x6", -13, -5)
+
+MEM_TEST("st1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5]", 17, 7)
+MEM_TEST("st1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], #32", 9, 9)
+MEM_TEST("st1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], x6", -13, -5)
+
+
+MEM_TEST("ld1 {v19.2d, v20.2d}, [x5]", 17, 7)
+MEM_TEST("ld1 {v19.2d, v20.2d}, [x5], #32", 9, 9)
+MEM_TEST("ld1 {v19.2d, v20.2d}, [x5], x6", -13, -5)
+
+MEM_TEST("ld1 {v17.2d, v18.2d, v19.2d}, [x5]", 17, 7)
+MEM_TEST("ld1 {v17.2d, v18.2d, v19.2d}, [x5], #48", 9, 9)
+MEM_TEST("ld1 {v17.2d, v18.2d, v19.2d}, [x5], x6", -13, -5)
+
+MEM_TEST("ld1 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5]", 17, 7)
+MEM_TEST("ld1 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], #64", 9, 9)
+MEM_TEST("ld1 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], x6", -13, -5)
+
+
+MEM_TEST("ld1 {v19.1d, v20.1d}, [x5]", 17, 7)
+MEM_TEST("ld1 {v19.1d, v20.1d}, [x5], #16", 9, 9)
+MEM_TEST("ld1 {v19.1d, v20.1d}, [x5], x6", -13, -5)
+
+MEM_TEST("ld1 {v17.1d, v18.1d, v19.1d}, [x5]", 17, 7)
+MEM_TEST("ld1 {v17.1d, v18.1d, v19.1d}, [x5], #24", 9, 9)
+MEM_TEST("ld1 {v17.1d, v18.1d, v19.1d}, [x5], x6", -13, -5)
+
+MEM_TEST("ld1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x5]", 17, 7)
+MEM_TEST("ld1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x5], #32", 9, 9)
+MEM_TEST("ld1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x5], x6", -13, -5)
+
+
+MEM_TEST("ld1 {v19.4s, v20.4s}, [x5]", 17, 7)
+MEM_TEST("ld1 {v19.4s, v20.4s}, [x5], #32", 9, 9)
+MEM_TEST("ld1 {v19.4s, v20.4s}, [x5], x6", -13, -5)
+
+MEM_TEST("ld1 {v17.4s, v18.4s, v19.4s}, [x5]", 17, 7)
+MEM_TEST("ld1 {v17.4s, v18.4s, v19.4s}, [x5], #48", 9, 9)
+MEM_TEST("ld1 {v17.4s, v18.4s, v19.4s}, [x5], x6", -13, -5)
+
+MEM_TEST("ld1 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5]", 17, 7)
+MEM_TEST("ld1 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], #64", 9, 9)
+MEM_TEST("ld1 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], x6", -13, -5)
+
+
+MEM_TEST("ld1 {v19.2s, v20.2s}, [x5]", 17, 7)
+MEM_TEST("ld1 {v19.2s, v20.2s}, [x5], #16", 9, 9)
+MEM_TEST("ld1 {v19.2s, v20.2s}, [x5], x6", -13, -5)
+
+MEM_TEST("ld1 {v17.2s, v18.2s, v19.2s}, [x5]", 17, 7)
+MEM_TEST("ld1 {v17.2s, v18.2s, v19.2s}, [x5], #24", 9, 9)
+MEM_TEST("ld1 {v17.2s, v18.2s, v19.2s}, [x5], x6", -13, -5)
+
+MEM_TEST("ld1 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5]", 17, 7)
+MEM_TEST("ld1 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], #32", 9, 9)
+MEM_TEST("ld1 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], x6", -13, -5)
+
+
+MEM_TEST("ld1 {v19.8h, v20.8h}, [x5]", 17, 7)
+MEM_TEST("ld1 {v19.8h, v20.8h}, [x5], #32", 9, 9)
+MEM_TEST("ld1 {v19.8h, v20.8h}, [x5], x6", -13, -5)
+
+MEM_TEST("ld1 {v17.8h, v18.8h, v19.8h}, [x5]", 17, 7)
+MEM_TEST("ld1 {v17.8h, v18.8h, v19.8h}, [x5], #48", 9, 9)
+MEM_TEST("ld1 {v17.8h, v18.8h, v19.8h}, [x5], x6", -13, -5)
+
+MEM_TEST("ld1 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5]", 17, 7)
+MEM_TEST("ld1 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], #64", 9, 9)
+MEM_TEST("ld1 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], x6", -13, -5)
+
+
+MEM_TEST("ld1 {v19.4h, v20.4h}, [x5]", 17, 7)
+MEM_TEST("ld1 {v19.4h, v20.4h}, [x5], #16", 9, 9)
+MEM_TEST("ld1 {v19.4h, v20.4h}, [x5], x6", -13, -5)
+
+MEM_TEST("ld1 {v17.4h, v18.4h, v19.4h}, [x5]", 17, 7)
+MEM_TEST("ld1 {v17.4h, v18.4h, v19.4h}, [x5], #24", 9, 9)
+MEM_TEST("ld1 {v17.4h, v18.4h, v19.4h}, [x5], x6", -13, -5)
+
+MEM_TEST("ld1 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5]", 17, 7)
+MEM_TEST("ld1 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], #32", 9, 9)
+MEM_TEST("ld1 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], x6", -13, -5)
MEM_TEST("ld1 {v19.16b, v20.16b}, [x5]", 17, 7)
MEM_TEST("ld1 {v19.16b, v20.16b}, [x5], #32", 9, 9)
-//MEM_TEST("ld1 {v19.16b, v20.16b}, [x5], x6", -13, -5)
+MEM_TEST("ld1 {v19.16b, v20.16b}, [x5], x6", -13, -5)
MEM_TEST("ld1 {v17.16b, v18.16b, v19.16b}, [x5]", 17, 7)
-//MEM_TEST("ld1 {v17.16b, v18.16b, v19.16b}, [x5], #48", 9, 9)
-//MEM_TEST("ld1 {v17.16b, v18.16b, v19.16b}, [x5], x6", -13, -5)
-//
-//MEM_TEST("ld1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5]", 17, 7)
-//MEM_TEST("ld1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], #64", 9, 9)
-//MEM_TEST("ld1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], x6", -13, -5)
-//
-//
-//MEM_TEST("ld1 {v19.8b, v20.8b}, [x5]", 17, 7)
-//MEM_TEST("ld1 {v19.8b, v20.8b}, [x5], #16", 9, 9)
-//MEM_TEST("ld1 {v19.8b, v20.8b}, [x5], x6", -13, -5)
-//
-//MEM_TEST("ld1 {v17.8b, v18.8b, v19.8b}, [x5]", 17, 7)
-//MEM_TEST("ld1 {v17.8b, v18.8b, v19.8b}, [x5], #24", 9, 9)
-//MEM_TEST("ld1 {v17.8b, v18.8b, v19.8b}, [x5], x6", -13, -5)
-//
-//MEM_TEST("ld1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5]", 17, 7)
-//MEM_TEST("ld1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], #32", 9, 9)
-//MEM_TEST("ld1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], x6", -13, -5)
+MEM_TEST("ld1 {v17.16b, v18.16b, v19.16b}, [x5], #48", 9, 9)
+MEM_TEST("ld1 {v17.16b, v18.16b, v19.16b}, [x5], x6", -13, -5)
+
+MEM_TEST("ld1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5]", 17, 7)
+MEM_TEST("ld1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], #64", 9, 9)
+MEM_TEST("ld1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], x6", -13, -5)
+
+
+MEM_TEST("ld1 {v19.8b, v20.8b}, [x5]", 17, 7)
+MEM_TEST("ld1 {v19.8b, v20.8b}, [x5], #16", 9, 9)
+MEM_TEST("ld1 {v19.8b, v20.8b}, [x5], x6", -13, -5)
+
+MEM_TEST("ld1 {v17.8b, v18.8b, v19.8b}, [x5]", 17, 7)
+MEM_TEST("ld1 {v17.8b, v18.8b, v19.8b}, [x5], #24", 9, 9)
+MEM_TEST("ld1 {v17.8b, v18.8b, v19.8b}, [x5], x6", -13, -5)
+
+MEM_TEST("ld1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5]", 17, 7)
+MEM_TEST("ld1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], #32", 9, 9)
+MEM_TEST("ld1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], x6", -13, -5)
////////////////////////////////////////////////////////////////
@@ -1229,370 +1229,370 @@
////////////////////////////////////////////////////////////////
printf("LD2R (single structure, replicate)\n");
-//MEM_TEST("ld2r {v17.2d , v18.2d }, [x5]", 3, -5)
-//MEM_TEST("ld2r {v18.1d , v19.1d }, [x5]", 3, -4)
-//MEM_TEST("ld2r {v19.4s , v20.4s }, [x5]", 3, -3)
-//MEM_TEST("ld2r {v17.2s , v18.2s }, [x5]", 3, -2)
-//MEM_TEST("ld2r {v18.8h , v19.8h }, [x5]", 3, -1)
-//MEM_TEST("ld2r {v19.4h , v20.4h }, [x5]", 3, 1)
-//MEM_TEST("ld2r {v17.16b, v18.16b}, [x5]", 3, 2)
-//MEM_TEST("ld2r {v18.8b , v19.8b }, [x5]", 3, 3)
-//
-//MEM_TEST("ld2r {v19.2d , v20.2d }, [x5], #16", 3, -5)
-//MEM_TEST("ld2r {v17.1d , v18.1d }, [x5], #16", 3, -4)
-//MEM_TEST("ld2r {v18.4s , v19.4s }, [x5], #8", 3, -3)
-//MEM_TEST("ld2r {v19.2s , v20.2s }, [x5], #8", 3, -2)
-//MEM_TEST("ld2r {v17.8h , v18.8h }, [x5], #4", 3, -1)
-//MEM_TEST("ld2r {v18.4h , v19.4h }, [x5], #4", 3, 1)
-//MEM_TEST("ld2r {v19.16b, v20.16b}, [x5], #2", 3, 2)
-//MEM_TEST("ld2r {v17.8b , v18.8b }, [x5], #2", 3, 3)
-//
-//MEM_TEST("ld2r {v18.2d , v19.2d }, [x5], x6", 3, -5)
-//MEM_TEST("ld2r {v19.1d , v20.1d }, [x5], x6", 3, -4)
-//MEM_TEST("ld2r {v17.4s , v18.4s }, [x5], x6", 3, -3)
-//MEM_TEST("ld2r {v18.2s , v19.2s }, [x5], x6", 3, -2)
-//MEM_TEST("ld2r {v19.8h , v20.8h }, [x5], x6", 3, -1)
-//MEM_TEST("ld2r {v17.4h , v18.4h }, [x5], x6", 3, 1)
-//MEM_TEST("ld2r {v18.16b, v19.16b}, [x5], x6", 3, 2)
-//MEM_TEST("ld2r {v19.8b , v20.8b }, [x5], x6", 3, 3)
+MEM_TEST("ld2r {v17.2d , v18.2d }, [x5]", 3, -5)
+MEM_TEST("ld2r {v18.1d , v19.1d }, [x5]", 3, -4)
+MEM_TEST("ld2r {v19.4s , v20.4s }, [x5]", 3, -3)
+MEM_TEST("ld2r {v17.2s , v18.2s }, [x5]", 3, -2)
+MEM_TEST("ld2r {v18.8h , v19.8h }, [x5]", 3, -1)
+MEM_TEST("ld2r {v19.4h , v20.4h }, [x5]", 3, 1)
+MEM_TEST("ld2r {v17.16b, v18.16b}, [x5]", 3, 2)
+MEM_TEST("ld2r {v18.8b , v19.8b }, [x5]", 3, 3)
+
+MEM_TEST("ld2r {v19.2d , v20.2d }, [x5], #16", 3, -5)
+MEM_TEST("ld2r {v17.1d , v18.1d }, [x5], #16", 3, -4)
+MEM_TEST("ld2r {v18.4s , v19.4s }, [x5], #8", 3, -3)
+MEM_TEST("ld2r {v19.2s , v20.2s }, [x5], #8", 3, -2)
+MEM_TEST("ld2r {v17.8h , v18.8h }, [x5], #4", 3, -1)
+MEM_TEST("ld2r {v18.4h , v19.4h }, [x5], #4", 3, 1)
+MEM_TEST("ld2r {v19.16b, v20.16b}, [x5], #2", 3, 2)
+MEM_TEST("ld2r {v17.8b , v18.8b }, [x5], #2", 3, 3)
+
+MEM_TEST("ld2r {v18.2d , v19.2d }, [x5], x6", 3, -5)
+MEM_TEST("ld2r {v19.1d , v20.1d }, [x5], x6", 3, -4)
+MEM_TEST("ld2r {v17.4s , v18.4s }, [x5], x6", 3, -3)
+MEM_TEST("ld2r {v18.2s , v19.2s }, [x5], x6", 3, -2)
+MEM_TEST("ld2r {v19.8h , v20.8h }, [x5], x6", 3, -1)
+MEM_TEST("ld2r {v17.4h , v18.4h }, [x5], x6", 3, 1)
+MEM_TEST("ld2r {v18.16b, v19.16b}, [x5], x6", 3, 2)
+MEM_TEST("ld2r {v19.8b , v20.8b }, [x5], x6", 3, 3)
//////////////////////////////////////////////////////////////////
-//printf("LD3R (single structure, replicate)\n");
+printf("LD3R (single structure, replicate)\n");
-//MEM_TEST("ld3r {v17.2d , v18.2d , v19.2d }, [x5]", 3, -5)
-//MEM_TEST("ld3r {v18.1d , v19.1d , v20.1d }, [x5]", 3, -4)
-//MEM_TEST("ld3r {v17.4s , v18.4s , v19.4s }, [x5]", 3, -3)
-//MEM_TEST("ld3r {v18.2s , v19.2s , v20.2s }, [x5]", 3, -2)
-//MEM_TEST("ld3r {v17.8h , v18.8h , v19.8h }, [x5]", 3, -5)
-//MEM_TEST("ld3r {v18.4h , v19.4h , v20.4h }, [x5]", 3, -4)
-//MEM_TEST("ld3r {v17.16b, v18.16b, v19.16b}, [x5]", 3, -3)
-//MEM_TEST("ld3r {v18.8b , v19.8b , v20.8b }, [x5]", 3, -2)
-//
-//MEM_TEST("ld3r {v17.2d , v18.2d , v19.2d }, [x5], #24", 3, -5)
-//MEM_TEST("ld3r {v18.1d , v19.1d , v20.1d }, [x5], #24", 3, -4)
-//MEM_TEST("ld3r {v17.4s , v18.4s , v19.4s }, [x5], #12", 3, -3)
-//MEM_TEST("ld3r {v18.2s , v19.2s , v20.2s }, [x5], #12", 3, -2)
-//MEM_TEST("ld3r {v17.8h , v18.8h , v19.8h }, [x5], #6", 3, -5)
-//MEM_TEST("ld3r {v18.4h , v19.4h , v20.4h }, [x5], #6", 3, -4)
-//MEM_TEST("ld3r {v17.16b, v18.16b, v19.16b}, [x5], #3", 3, -3)
-//MEM_TEST("ld3r {v18.8b , v19.8b , v20.8b }, [x5], #3", 3, -2)
-//
-//MEM_TEST("ld3r {v17.2d , v18.2d , v19.2d }, [x5], x6", 3, -5)
-//MEM_TEST("ld3r {v18.1d , v19.1d , v20.1d }, [x5], x6", 3, -4)
-//MEM_TEST("ld3r {v17.4s , v18.4s , v19.4s }, [x5], x6", 3, -3)
-//MEM_TEST("ld3r {v18.2s , v19.2s , v20.2s }, [x5], x6", 3, -2)
-//MEM_TEST("ld3r {v17.8h , v18.8h , v19.8h }, [x5], x6", 3, -5)
-//MEM_TEST("ld3r {v18.4h , v19.4h , v20.4h }, [x5], x6", 3, -4)
-//MEM_TEST("ld3r {v17.16b, v18.16b, v19.16b}, [x5], x6", 3, -3)
-//MEM_TEST("ld3r {v18.8b , v19.8b , v20.8b }, [x5], x6", 3, -2)
+MEM_TEST("ld3r {v17.2d , v18.2d , v19.2d }, [x5]", 3, -5)
+MEM_TEST("ld3r {v18.1d , v19.1d , v20.1d }, [x5]", 3, -4)
+MEM_TEST("ld3r {v17.4s , v18.4s , v19.4s }, [x5]", 3, -3)
+MEM_TEST("ld3r {v18.2s , v19.2s , v20.2s }, [x5]", 3, -2)
+MEM_TEST("ld3r {v17.8h , v18.8h , v19.8h }, [x5]", 3, -5)
+MEM_TEST("ld3r {v18.4h , v19.4h , v20.4h }, [x5]", 3, -4)
+MEM_TEST("ld3r {v17.16b, v18.16b, v19.16b}, [x5]", 3, -3)
+MEM_TEST("ld3r {v18.8b , v19.8b , v20.8b }, [x5]", 3, -2)
+
+MEM_TEST("ld3r {v17.2d , v18.2d , v19.2d }, [x5], #24", 3, -5)
+MEM_TEST("ld3r {v18.1d , v19.1d , v20.1d }, [x5], #24", 3, -4)
+MEM_TEST("ld3r {v17.4s , v18.4s , v19.4s }, [x5], #12", 3, -3)
+MEM_TEST("ld3r {v18.2s , v19.2s , v20.2s }, [x5], #12", 3, -2)
+MEM_TEST("ld3r {v17.8h , v18.8h , v19.8h }, [x5], #6", 3, -5)
+MEM_TEST("ld3r {v18.4h , v19.4h , v20.4h }, [x5], #6", 3, -4)
+MEM_TEST("ld3r {v17.16b, v18.16b, v19.16b}, [x5], #3", 3, -3)
+MEM_TEST("ld3r {v18.8b , v19.8b , v20.8b }, [x5], #3", 3, -2)
+
+MEM_TEST("ld3r {v17.2d , v18.2d , v19.2d }, [x5], x6", 3, -5)
+MEM_TEST("ld3r {v18.1d , v19.1d , v20.1d }, [x5], x6", 3, -4)
+MEM_TEST("ld3r {v17.4s , v18.4s , v19.4s }, [x5], x6", 3, -3)
+MEM_TEST("ld3r {v18.2s , v19.2s , v20.2s }, [x5], x6", 3, -2)
+MEM_TEST("ld3r {v17.8h , v18.8h , v19.8h }, [x5], x6", 3, -5)
+MEM_TEST("ld3r {v18.4h , v19.4h , v20.4h }, [x5], x6", 3, -4)
+MEM_TEST("ld3r {v17.16b, v18.16b, v19.16b}, [x5], x6", 3, -3)
+MEM_TEST("ld3r {v18.8b , v19.8b , v20.8b }, [x5], x6", 3, -2)
////////////////////////////////////////////////////////////////
printf("LD4R (single structure, replicate)\n");
-//MEM_TEST("ld4r {v17.2d , v18.2d , v19.2d , v20.2d }, [x5]", 3, -5)
-//MEM_TEST("ld4r {v17.1d , v18.1d , v19.1d , v20.1d }, [x5]", 3, -4)
-//MEM_TEST("ld4r {v17.4s , v18.4s , v19.4s , v20.4s }, [x5]", 3, -3)
-//MEM_TEST("ld4r {v17.2s , v18.2s , v19.2s , v20.2s }, [x5]", 3, -2)
-//MEM_TEST("ld4r {v17.8h , v18.8h , v19.8h , v20.8h }, [x5]", 3, -5)
-//MEM_TEST("ld4r {v17.4h , v18.4h , v19.4h , v20.4h }, [x5]", 3, -4)
-//MEM_TEST("ld4r {v17.16b, v18.16b, v19.16b, v20.16b}, [x5]", 3, -3)
-//MEM_TEST("ld4r {v17.8b , v18.8b , v19.8b , v20.8b }, [x5]", 3, -2)
-//
-//MEM_TEST("ld4r {v17.2d , v18.2d , v19.2d , v20.2d }, [x5], #32", 3, -5)
-//MEM_TEST("ld4r {v17.1d , v18.1d , v19.1d , v20.1d }, [x5], #32", 3, -4)
-//MEM_TEST("ld4r {v17.4s , v18.4s , v19.4s , v20.4s }, [x5], #16", 3, -3)
-//MEM_TEST("ld4r {v17.2s , v18.2s , v19.2s , v20.2s }, [x5], #16", 3, -2)
-//MEM_TEST("ld4r {v17.8h , v18.8h , v19.8h , v20.8h }, [x5], #8", 3, -5)
-//MEM_TEST("ld4r {v17.4h , v18.4h , v19.4h , v20.4h }, [x5], #8", 3, -4)
-//MEM_TEST("ld4r {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], #4", 3, -3)
-//MEM_TEST("ld4r {v17.8b , v18.8b , v19.8b , v20.8b }, [x5], #4", 3, -2)
-//
-//MEM_TEST("ld4r {v17.2d , v18.2d , v19.2d , v20.2d }, [x5], x6", 3, -5)
-//MEM_TEST("ld4r {v17.1d , v18.1d , v19.1d , v20.1d }, [x5], x6", 3, -4)
-//MEM_TEST("ld4r {v17.4s , v18.4s , v19.4s , v20.4s }, [x5], x6", 3, -3)
-//MEM_TEST("ld4r {v17.2s , v18.2s , v19.2s , v20.2s }, [x5], x6", 3, -2)
-//MEM_TEST("ld4r {v17.8h , v18.8h , v19.8h , v20.8h }, [x5], x6", 3, -5)
-//MEM_TEST("ld4r {v17.4h , v18.4h , v19.4h , v20.4h }, [x5], x6", 3, -4)
-//MEM_TEST("ld4r {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], x6", 3, -3)
-//MEM_TEST("ld4r {v17.8b , v18.8b , v19.8b , v20.8b }, [x5], x6", 3, -2)
+MEM_TEST("ld4r {v17.2d , v18.2d , v19.2d , v20.2d }, [x5]", 3, -5)
+MEM_TEST("ld4r {v17.1d , v18.1d , v19.1d , v20.1d }, [x5]", 3, -4)
+MEM_TEST("ld4r {v17.4s , v18.4s , v19.4s , v20.4s }, [x5]", 3, -3)
+MEM_TEST("ld4r {v17.2s , v18.2s , v19.2s , v20.2s }, [x5]", 3, -2)
+MEM_TEST("ld4r {v17.8h , v18.8h , v19.8h , v20.8h }, [x5]", 3, -5)
+MEM_TEST("ld4r {v17.4h , v18.4h , v19.4h , v20.4h }, [x5]", 3, -4)
+MEM_TEST("ld4r {v17.16b, v18.16b, v19.16b, v20.16b}, [x5]", 3, -3)
+MEM_TEST("ld4r {v17.8b , v18.8b , v19.8b , v20.8b }, [x5]", 3, -2)
+
+MEM_TEST("ld4r {v17.2d , v18.2d , v19.2d , v20.2d }, [x5], #32", 3, -5)
+MEM_TEST("ld4r {v17.1d , v18.1d , v19.1d , v20.1d }, [x5], #32", 3, -4)
+MEM_TEST("ld4r {v17.4s , v18.4s , v19.4s , v20.4s }, [x5], #16", 3, -3)
+MEM_TEST("ld4r {v17.2s , v18.2s , v19.2s , v20.2s }, [x5], #16", 3, -2)
+MEM_TEST("ld4r {v17.8h , v18.8h , v19.8h , v20.8h }, [x5], #8", 3, -5)
+MEM_TEST("ld4r {v17.4h , v18.4h , v19.4h , v20.4h }, [x5], #8", 3, -4)
+MEM_TEST("ld4r {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], #4", 3, -3)
+MEM_TEST("ld4r {v17.8b , v18.8b , v19.8b , v20.8b }, [x5], #4", 3, -2)
+
+MEM_TEST("ld4r {v17.2d , v18.2d , v19.2d , v20.2d }, [x5], x6", 3, -5)
+MEM_TEST("ld4r {v17.1d , v18.1d , v19.1d , v20.1d }, [x5], x6", 3, -4)
+MEM_TEST("ld4r {v17.4s , v18.4s , v19.4s , v20.4s }, [x5], x6", 3, -3)
+MEM_TEST("ld4r {v17.2s , v18.2s , v19.2s , v20.2s }, [x5], x6", 3, -2)
+MEM_TEST("ld4r {v17.8h , v18.8h , v19.8h , v20.8h }, [x5], x6", 3, -5)
+MEM_TEST("ld4r {v17.4h , v18.4h , v19.4h , v20.4h }, [x5], x6", 3, -4)
+MEM_TEST("ld4r {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], x6", 3, -3)
+MEM_TEST("ld4r {v17.8b , v18.8b , v19.8b , v20.8b }, [x5], x6", 3, -2)
////////////////////////////////////////////////////////////////
printf("LD1/ST1 (single 1-elem struct to/from one lane of 1 reg\n");
-//MEM_TEST("st1 {v19.d}[0], [x5]", 17, 7)
-//MEM_TEST("st1 {v19.d}[0], [x5], #8", -9, 12)
-//MEM_TEST("st1 {v19.d}[0], [x5], x6", 9, 13)
-//
-//MEM_TEST("st1 {v19.d}[1], [x5]", 17, 7)
-//MEM_TEST("st1 {v19.d}[1], [x5], #8", -9, 12)
-//MEM_TEST("st1 {v19.d}[1], [x5], x6", 9, 13)
-//
-//MEM_TEST("st1 {v19.s}[0], [x5]", 17, 7)
-//MEM_TEST("st1 {v19.s}[0], [x5], #4", -9, 12)
-//MEM_TEST("st1 {v19.s}[0], [x5], x6", 9, 13)
-//
-//MEM_TEST("st1 {v19.s}[3], [x5]", 17, 7)
-//MEM_TEST("st1 {v19.s}[3], [x5], #4", -9, 12)
-//MEM_TEST("st1 {v19.s}[3], [x5], x6", 9, 13)
-//
-//MEM_TEST("st1 {v19.h}[0], [x5]", 17, 7)
-//MEM_TEST("st1 {v19.h}[0], [x5], #2", -9, 12)
-//MEM_TEST("st1 {v19.h}[0], [x5], x6", 9, 13)
-//
-//MEM_TEST("st1 {v19.h}[6], [x5]", 17, 7)
-//MEM_TEST("st1 {v19.h}[6], [x5], #2", -9, 12)
-//MEM_TEST("st1 {v19.h}[6], [x5], x6", 9, 13)
-//
-//MEM_TEST("st1 {v19.b}[0], [x5]", 17, 7)
-//MEM_TEST("st1 {v19.b}[0], [x5], #1", -9, 12)
-//MEM_TEST("st1 {v19.b}[0], [x5], x6", 9, 13)
-//
-//MEM_TEST("st1 {v19.b}[13], [x5]", 17, 7)
-//MEM_TEST("st1 {v19.b}[13], [x5], #1", -9, 12)
-//MEM_TEST("st1 {v19.b}[13], [x5], x6", 9, 13)
-//
-//
-//MEM_TEST("ld1 {v19.d}[0], [x5]", 17, 7)
-//MEM_TEST("ld1 {v19.d}[0], [x5], #8", -9, 12)
-//MEM_TEST("ld1 {v19.d}[0], [x5], x6", 9, 13)
-//
-//MEM_TEST("ld1 {v19.d}[1], [x5]", 17, 7)
-//MEM_TEST("ld1 {v19.d}[1], [x5], #8", -9, 12)
-//MEM_TEST("ld1 {v19.d}[1], [x5], x6", 9, 13)
-//
-//MEM_TEST("ld1 {v19.s}[0], [x5]", 17, 7)
-//MEM_TEST("ld1 {v19.s}[0], [x5], #4", -9, 12)
-//MEM_TEST("ld1 {v19.s}[0], [x5], x6", 9, 13)
-//
-//MEM_TEST("ld1 {v19.s}[3], [x5]", 17, 7)
-//MEM_TEST("ld1 {v19.s}[3], [x5], #4", -9, 12)
-//MEM_TEST("ld1 {v19.s}[3], [x5], x6", 9, 13)
-//
-//MEM_TEST("ld1 {v19.h}[0], [x5]", 17, 7)
-//MEM_TEST("ld1 {v19.h}[0], [x5], #2", -9, 12)
-//MEM_TEST("ld1 {v19.h}[0], [x5], x6", 9, 13)
-//
-//MEM_TEST("ld1 {v19.h}[6], [x5]", 17, 7)
-//MEM_TEST("ld1 {v19.h}[6], [x5], #2", -9, 12)
-//MEM_TEST("ld1 {v19.h}[6], [x5], x6", 9, 13)
-//
-//MEM_TEST("ld1 {v19.b}[0], [x5]", 17, 7)
-//MEM_TEST("ld1 {v19.b}[0], [x5], #1", -9, 12)
-//MEM_TEST("ld1 {v19.b}[0], [x5], x6", 9, 13)
-//
-//MEM_TEST("ld1 {v19.b}[13], [x5]", 17, 7)
-//MEM_TEST("ld1 {v19.b}[13], [x5], #1", -9, 12)
-//MEM_TEST("ld1 {v19.b}[13], [x5], x6", 9, 13)
+MEM_TEST("st1 {v19.d}[0], [x5]", 17, 7)
+MEM_TEST("st1 {v19.d}[0], [x5], #8", -9, 12)
+MEM_TEST("st1 {v19.d}[0], [x5], x6", 9, 13)
+
+MEM_TEST("st1 {v19.d}[1], [x5]", 17, 7)
+MEM_TEST("st1 {v19.d}[1], [x5], #8", -9, 12)
+MEM_TEST("st1 {v19.d}[1], [x5], x6", 9, 13)
+
+MEM_TEST("st1 {v19.s}[0], [x5]", 17, 7)
+MEM_TEST("st1 {v19.s}[0], [x5], #4", -9, 12)
+MEM_TEST("st1 {v19.s}[0], [x5], x6", 9, 13)
+
+MEM_TEST("st1 {v19.s}[3], [x5]", 17, 7)
+MEM_TEST("st1 {v19.s}[3], [x5], #4", -9, 12)
+MEM_TEST("st1 {v19.s}[3], [x5], x6", 9, 13)
+
+MEM_TEST("st1 {v19.h}[0], [x5]", 17, 7)
+MEM_TEST("st1 {v19.h}[0], [x5], #2", -9, 12)
+MEM_TEST("st1 {v19.h}[0], [x5], x6", 9, 13)
+
+MEM_TEST("st1 {v19.h}[6], [x5]", 17, 7)
+MEM_TEST("st1 {v19.h}[6], [x5], #2", -9, 12)
+MEM_TEST("st1 {v19.h}[6], [x5], x6", 9, 13)
+
+MEM_TEST("st1 {v19.b}[0], [x5]", 17, 7)
+MEM_TEST("st1 {v19.b}[0], [x5], #1", -9, 12)
+MEM_TEST("st1 {v19.b}[0], [x5], x6", 9, 13)
+
+MEM_TEST("st1 {v19.b}[13], [x5]", 17, 7)
+MEM_TEST("st1 {v19.b}[13], [x5], #1", -9, 12)
+MEM_TEST("st1 {v19.b}[13], [x5], x6", 9, 13)
+
+
+MEM_TEST("ld1 {v19.d}[0], [x5]", 17, 7)
+MEM_TEST("ld1 {v19.d}[0], [x5], #8", -9, 12)
+MEM_TEST("ld1 {v19.d}[0], [x5], x6", 9, 13)
+
+MEM_TEST("ld1 {v19.d}[1], [x5]", 17, 7)
+MEM_TEST("ld1 {v19.d}[1], [x5], #8", -9, 12)
+MEM_TEST("ld1 {v19.d}[1], [x5], x6", 9, 13)
+
+MEM_TEST("ld1 {v19.s}[0], [x5]", 17, 7)
+MEM_TEST("ld1 {v19.s}[0], [x5], #4", -9, 12)
+MEM_TEST("ld1 {v19.s}[0], [x5], x6", 9, 13)
+
+MEM_TEST("ld1 {v19.s}[3], [x5]", 17, 7)
+MEM_TEST("ld1 {v19.s}[3], [x5], #4", -9, 12)
+MEM_TEST("ld1 {v19.s}[3], [x5], x6", 9, 13)
+
+MEM_TEST("ld1 {v19.h}[0], [x5]", 17, 7)
+MEM_TEST("ld1 {v19.h}[0], [x5], #2", -9, 12)
+MEM_TEST("ld1 {v19.h}[0], [x5], x6", 9, 13)
+
+MEM_TEST("ld1 {v19.h}[6], [x5]", 17, 7)
+MEM_TEST("ld1 {v19.h}[6], [x5], #2", -9, 12)
+MEM_TEST("ld1 {v19.h}[6], [x5], x6", 9, 13)
+
+MEM_TEST("ld1 {v19.b}[0], [x5]", 17, 7)
+MEM_TEST("ld1 {v19.b}[0], [x5], #1", -9, 12)
+MEM_TEST("ld1 {v19.b}[0], [x5], x6", 9, 13)
+
+MEM_TEST("ld1 {v19.b}[13], [x5]", 17, 7)
+MEM_TEST("ld1 {v19.b}[13], [x5], #1", -9, 12)
+MEM_TEST("ld1 {v19.b}[13], [x5], x6", 9, 13)
////////////////////////////////////////////////////////////////
printf("LD2/ST2 (single 2-elem struct to/from one lane of 2 regs\n");
-//MEM_TEST("st2 {v18.d, v19.d}[0], [x5]", 17, 7)
-//MEM_TEST("st2 {v18.d, v19.d}[0], [x5], #16", -9, 12)
-//MEM_TEST("st2 {v18.d, v19.d}[0], [x5], x6", 9, 13)
-//
-//MEM_TEST("st2 {v18.d, v19.d}[1], [x5]", 17, 7)
-//MEM_TEST("st2 {v18.d, v19.d}[1], [x5], #16", -9, 12)
-//MEM_TEST("st2 {v18.d, v19.d}[1], [x5], x6", 9, 13)
-//
-//MEM_TEST("st2 {v18.s, v19.s}[0], [x5]", 17, 7)
-//MEM_TEST("st2 {v18.s, v19.s}[0], [x5], #8", -9, 12)
-//MEM_TEST("st2 {v18.s, v19.s}[0], [x5], x6", 9, 13)
-//
-//MEM_TEST("st2 {v18.s, v19.s}[3], [x5]", 17, 7)
-//MEM_TEST("st2 {v18.s, v19.s}[3], [x5], #8", -9, 12)
-//MEM_TEST("st2 {v18.s, v19.s}[3], [x5], x6", 9, 13)
-//
-//MEM_TEST("st2 {v18.h, v19.h}[0], [x5]", 17, 7)
-//MEM_TEST("st2 {v18.h, v19.h}[0], [x5], #4", -9, 12)
-//MEM_TEST("st2 {v18.h, v19.h}[0], [x5], x6", 9, 13)
-//
-//MEM_TEST("st2 {v18.h, v19.h}[6], [x5]", 17, 7)
-//MEM_TEST("st2 {v18.h, v19.h}[6], [x5], #4", -9, 12)
-//MEM_TEST("st2 {v18.h, v19.h}[6], [x5], x6", 9, 13)
-//
-//MEM_TEST("st2 {v18.b, v19.b}[0], [x5]", 17, 7)
-//MEM_TEST("st2 {v18.b, v19.b}[0], [x5], #2", -9, 12)
-//MEM_TEST("st2 {v18.b, v19.b}[0], [x5], x6", 9, 13)
-//
-//MEM_TEST("st2 {v18.b, v19.b}[13], [x5]", 17, 7)
-//MEM_TEST("st2 {v18.b, v19.b}[13], [x5], #2", -9, 12)
-//MEM_TEST("st2 {v18.b, v19.b}[13], [x5], x6", 9, 13)
-//
-//
-//MEM_TEST("ld2 {v18.d, v19.d}[0], [x5]", 17, 7)
-//MEM_TEST("ld2 {v18.d, v19.d}[0], [x5], #16", -9, 12)
-//MEM_TEST("ld2 {v18.d, v19.d}[0], [x5], x6", 9, 13)
-//
-//MEM_TEST("ld2 {v18.d, v19.d}[1], [x5]", 17, 7)
-//MEM_TEST("ld2 {v18.d, v19.d}[1], [x5], #16", -9, 12)
-//MEM_TEST("ld2 {v18.d, v19.d}[1], [x5], x6", 9, 13)
-//
-//MEM_TEST("ld2 {v18.s, v19.s}[0], [x5]", 17, 7)
-//MEM_TEST("ld2 {v18.s, v19.s}[0], [x5], #8", -9, 12)
-//MEM_TEST("ld2 {v18.s, v19.s}[0], [x5], x6", 9, 13)
-//
-//MEM_TEST("ld2 {v18.s, v19.s}[3], [x5]", 17, 7)
-//MEM_TEST("ld2 {v18.s, v19.s}[3], [x5], #8", -9, 12)
-//MEM_TEST("ld2 {v18.s, v19.s}[3], [x5], x6", 9, 13)
-//
-//MEM_TEST("ld2 {v18.h, v19.h}[0], [x5]", 17, 7)
-//MEM_TEST("ld2 {v18.h, v19.h}[0], [x5], #4", -9, 12)
-//MEM_TEST("ld2 {v18.h, v19.h}[0], [x5], x6", 9, 13)
-//
-//MEM_TEST("ld2 {v18.h, v19.h}[6], [x5]", 17, 7)
-//MEM_TEST("ld2 {v18.h, v19.h}[6], [x5], #4", -9, 12)
-//MEM_TEST("ld2 {v18.h, v19.h}[6], [x5], x6", 9, 13)
-//
-//MEM_TEST("ld2 {v18.b, v19.b}[0], [x5]", 17, 7)
-//MEM_TEST("ld2 {v18.b, v19.b}[0], [x5], #2", -9, 12)
-//MEM_TEST("ld2 {v18.b, v19.b}[0], [x5], x6", 9, 13)
-//
-//MEM_TEST("ld2 {v18.b, v19.b}[13], [x5]", 17, 7)
-//MEM_TEST("ld2 {v18.b, v19.b}[13], [x5], #2", -9, 12)
-//MEM_TEST("ld2 {v18.b, v19.b}[13], [x5], x6", 9, 13)
+MEM_TEST("st2 {v18.d, v19.d}[0], [x5]", 17, 7)
+MEM_TEST("st2 {v18.d, v19.d}[0], [x5], #16", -9, 12)
+MEM_TEST("st2 {v18.d, v19.d}[0], [x5], x6", 9, 13)
+
+MEM_TEST("st2 {v18.d, v19.d}[1], [x5]", 17, 7)
+MEM_TEST("st2 {v18.d, v19.d}[1], [x5], #16", -9, 12)
+MEM_TEST("st2 {v18.d, v19.d}[1], [x5], x6", 9, 13)
+
+MEM_TEST("st2 {v18.s, v19.s}[0], [x5]", 17, 7)
+MEM_TEST("st2 {v18.s, v19.s}[0], [x5], #8", -9, 12)
+MEM_TEST("st2 {v18.s, v19.s}[0], [x5], x6", 9, 13)
+
+MEM_TEST("st2 {v18.s, v19.s}[3], [x5]", 17, 7)
+MEM_TEST("st2 {v18.s, v19.s}[3], [x5], #8", -9, 12)
+MEM_TEST("st2 {v18.s, v19.s}[3], [x5], x6", 9, 13)
+
+MEM_TEST("st2 {v18.h, v19.h}[0], [x5]", 17, 7)
+MEM_TEST("st2 {v18.h, v19.h}[0], [x5], #4", -9, 12)
+MEM_TEST("st2 {v18.h, v19.h}[0], [x5], x6", 9, 13)
+
+MEM_TEST("st2 {v18.h, v19.h}[6], [x5]", 17, 7)
+MEM_TEST("st2 {v18.h, v19.h}[6], [x5], #4", -9, 12)
+MEM_TEST("st2 {v18.h, v19.h}[6], [x5], x6", 9, 13)
+
+MEM_TEST("st2 {v18.b, v19.b}[0], [x5]", 17, 7)
+MEM_TEST("st2 {v18.b, v19.b}[0], [x5], #2", -9, 12)
+MEM_TEST("st2 {v18.b, v19.b}[0], [x5], x6", 9, 13)
+
+MEM_TEST("st2 {v18.b, v19.b}[13], [x5]", 17, 7)
+MEM_TEST("st2 {v18.b, v19.b}[13], [x5], #2", -9, 12)
+MEM_TEST("st2 {v18.b, v19.b}[13], [x5], x6", 9, 13)
+
+
+MEM_TEST("ld2 {v18.d, v19.d}[0], [x5]", 17, 7)
+MEM_TEST("ld2 {v18.d, v19.d}[0], [x5], #16", -9, 12)
+MEM_TEST("ld2 {v18.d, v19.d}[0], [x5], x6", 9, 13)
+
+MEM_TEST("ld2 {v18.d, v19.d}[1], [x5]", 17, 7)
+MEM_TEST("ld2 {v18.d, v19.d}[1], [x5], #16", -9, 12)
+MEM_TEST("ld2 {v18.d, v19.d}[1], [x5], x6", 9, 13)
+
+MEM_TEST("ld2 {v18.s, v19.s}[0], [x5]", 17, 7)
+MEM_TEST("ld2 {v18.s, v19.s}[0], [x5], #8", -9, 12)
+MEM_TEST("ld2 {v18.s, v19.s}[0], [x5], x6", 9, 13)
+
+MEM_TEST("ld2 {v18.s, v19.s}[3], [x5]", 17, 7)
+MEM_TEST("ld2 {v18.s, v19.s}[3], [x5], #8", -9, 12)
+MEM_TEST("ld2 {v18.s, v19.s}[3], [x5], x6", 9, 13)
+
+MEM_TEST("ld2 {v18.h, v19.h}[0], [x5]", 17, 7)
+MEM_TEST("ld2 {v18.h, v19.h}[0], [x5], #4", -9, 12)
+MEM_TEST("ld2 {v18.h, v19.h}[0], [x5], x6", 9, 13)
+
+MEM_TEST("ld2 {v18.h, v19.h}[6], [x5]", 17, 7)
+MEM_TEST("ld2 {v18.h, v19.h}[6], [x5], #4", -9, 12)
+MEM_TEST("ld2 {v18.h, v19.h}[6], [x5], x6", 9, 13)
+
+MEM_TEST("ld2 {v18.b, v19.b}[0], [x5]", 17, 7)
+MEM_TEST("ld2 {v18.b, v19.b}[0], [x5], #2", -9, 12)
+MEM_TEST("ld2 {v18.b, v19.b}[0], [x5], x6", 9, 13)
+
+MEM_TEST("ld2 {v18.b, v19.b}[13], [x5]", 17, 7)
+MEM_TEST("ld2 {v18.b, v19.b}[13], [x5], #2", -9, 12)
+MEM_TEST("ld2 {v18.b, v19.b}[13], [x5], x6", 9, 13)
////////////////////////////////////////////////////////////////
printf("LD3/ST3 (single 3-elem struct to/from one lane of 3 regs\n");
-//MEM_TEST("st3 {v17.d, v18.d, v19.d}[0], [x5]", 17, 7)
-//MEM_TEST("st3 {v17.d, v18.d, v19.d}[0], [x5], #24", -9, 12)
-//MEM_TEST("st3 {v17.d, v18.d, v19.d}[0], [x5], x6", 9, 13)
-//
-//MEM_TEST("st3 {v17.d, v18.d, v19.d}[1], [x5]", 17, 7)
-//MEM_TEST("st3 {v17.d, v18.d, v19.d}[1], [x5], #24", -9, 12)
-//MEM_TEST("st3 {v17.d, v18.d, v19.d}[1], [x5], x6", 9, 13)
-//
-//MEM_TEST("st3 {v17.s, v18.s, v19.s}[0], [x5]", 17, 7)
-//MEM_TEST("st3 {v17.s, v18.s, v19.s}[0], [x5], #12", -9, 12)
-//MEM_TEST("st3 {v17.s, v18.s, v19.s}[0], [x5], x6", 9, 13)
-//
-//MEM_TEST("st3 {v17.s, v18.s, v19.s}[3], [x5]", 17, 7)
-//MEM_TEST("st3 {v17.s, v18.s, v19.s}[3], [x5], #12", -9, 12)
-//MEM_TEST("st3 {v17.s, v18.s, v19.s}[3], [x5], x6", 9, 13)
-//
-//MEM_TEST("st3 {v17.h, v18.h, v19.h}[0], [x5]", 17, 7)
-//MEM_TEST("st3 {v17.h, v18.h, v19.h}[0], [x5], #6", -9, 12)
-//MEM_TEST("st3 {v17.h, v18.h, v19.h}[0], [x5], x6", 9, 13)
-//
-//MEM_TEST("st3 {v17.h, v18.h, v19.h}[6], [x5]", 17, 7)
-//MEM_TEST("st3 {v17.h, v18.h, v19.h}[6], [x5], #6", -9, 12)
-//MEM_TEST("st3 {v17.h, v18.h, v19.h}[6], [x5], x6", 9, 13)
-//
-//MEM_TEST("st3 {v17.b, v18.b, v19.b}[0], [x5]", 17, 7)
-//MEM_TEST("st3 {v17.b, v18.b, v19.b}[0], [x5], #3", -9, 12)
-//MEM_TEST("st3 {v17.b, v18.b, v19.b}[0], [x5], x6", 9, 13)
-//
-//MEM_TEST("st3 {v17.b, v18.b, v19.b}[13], [x5]", 17, 7)
-//MEM_TEST("st3 {v17.b, v18.b, v19.b}[13], [x5], #3", -9, 12)
-//MEM_TEST("st3 {v17.b, v18.b, v19.b}[13], [x5], x6", 9, 13)
-//
-//
-//MEM_TEST("ld3 {v17.d, v18.d, v19.d}[0], [x5]", 17, 7)
-//MEM_TEST("ld3 {v17.d, v18.d, v19.d}[0], [x5], #24", -9, 12)
-//MEM_TEST("ld3 {v17.d, v18.d, v19.d}[0], [x5], x6", 9, 13)
-//
-//MEM_TEST("ld3 {v17.d, v18.d, v19.d}[1], [x5]", 17, 7)
-//MEM_TEST("ld3 {v17.d, v18.d, v19.d}[1], [x5], #24", -9, 12)
-//MEM_TEST("ld3 {v17.d, v18.d, v19.d}[1], [x5], x6", 9, 13)
-//
-//MEM_TEST("ld3 {v17.s, v18.s, v19.s}[0], [x5]", 17, 7)
-//MEM_TEST("ld3 {v17.s, v18.s, v19.s}[0], [x5], #12", -9, 12)
-//MEM_TEST("ld3 {v17.s, v18.s, v19.s}[0], [x5], x6", 9, 13)
-//
-//MEM_TEST("ld3 {v17.s, v18.s, v19.s}[3], [x5]", 17, 7)
-//MEM_TEST("ld3 {v17.s, v18.s, v19.s}[3], [x5], #12", -9, 12)
-//MEM_TEST("ld3 {v17.s, v18.s, v19.s}[3], [x5], x6", 9, 13)
-//
-//MEM_TEST("ld3 {v17.h, v18.h, v19.h}[0], [x5]", 17, 7)
-//MEM_TEST("ld3 {v17.h, v18.h, v19.h}[0], [x5], #6", -9, 12)
-//MEM_TEST("ld3 {v17.h, v18.h, v19.h}[0], [x5], x6", 9, 13)
-//
-//MEM_TEST("ld3 {v17.h, v18.h, v19.h}[6], [x5]", 17, 7)
-//MEM_TEST("ld3 {v17.h, v18.h, v19.h}[6], [x5], #6", -9, 12)
-//MEM_TEST("ld3 {v17.h, v18.h, v19.h}[6], [x5], x6", 9, 13)
-//
-//MEM_TEST("ld3 {v17.b, v18.b, v19.b}[0], [x5]", 17, 7)
-//MEM_TEST("ld3 {v17.b, v18.b, v19.b}[0], [x5], #3", -9, 12)
-//MEM_TEST("ld3 {v17.b, v18.b, v19.b}[0], [x5], x6", 9, 13)
-//
-//MEM_TEST("ld3 {v17.b, v18.b, v19.b}[13], [x5]", 17, 7)
-//MEM_TEST("ld3 {v17.b, v18.b, v19.b}[13], [x5], #3", -9, 12)
-//MEM_TEST("ld3 {v17.b, v18.b, v19.b}[13], [x5], x6", 9, 13)
+MEM_TEST("st3 {v17.d, v18.d, v19.d}[0], [x5]", 17, 7)
+MEM_TEST("st3 {v17.d, v18.d, v19.d}[0], [x5], #24", -9, 12)
+MEM_TEST("st3 {v17.d, v18.d, v19.d}[0], [x5], x6", 9, 13)
+
+MEM_TEST("st3 {v17.d, v18.d, v19.d}[1], [x5]", 17, 7)
+MEM_TEST("st3 {v17.d, v18.d, v19.d}[1], [x5], #24", -9, 12)
+MEM_TEST("st3 {v17.d, v18.d, v19.d}[1], [x5], x6", 9, 13)
+
+MEM_TEST("st3 {v17.s, v18.s, v19.s}[0], [x5]", 17, 7)
+MEM_TEST("st3 {v17.s, v18.s, v19.s}[0], [x5], #12", -9, 12)
+MEM_TEST("st3 {v17.s, v18.s, v19.s}[0], [x5], x6", 9, 13)
+
+MEM_TEST("st3 {v17.s, v18.s, v19.s}[3], [x5]", 17, 7)
+MEM_TEST("st3 {v17.s, v18.s, v19.s}[3], [x5], #12", -9, 12)
+MEM_TEST("st3 {v17.s, v18.s, v19.s}[3], [x5], x6", 9, 13)
+
+MEM_TEST("st3 {v17.h, v18.h, v19.h}[0], [x5]", 17, 7)
+MEM_TEST("st3 {v17.h, v18.h, v19.h}[0], [x5], #6", -9, 12)
+MEM_TEST("st3 {v17.h, v18.h, v19.h}[0], [x5], x6", 9, 13)
+
+MEM_TEST("st3 {v17.h, v18.h, v19.h}[6], [x5]", 17, 7)
+MEM_TEST("st3 {v17.h, v18.h, v19.h}[6], [x5], #6", -9, 12)
+MEM_TEST("st3 {v17.h, v18.h, v19.h}[6], [x5], x6", 9, 13)
+
+MEM_TEST("st3 {v17.b, v18.b, v19.b}[0], [x5]", 17, 7)
+MEM_TEST("st3 {v17.b, v18.b, v19.b}[0], [x5], #3", -9, 12)
+MEM_TEST("st3 {v17.b, v18.b, v19.b}[0], [x5], x6", 9, 13)
+
+MEM_TEST("st3 {v17.b, v18.b, v19.b}[13], [x5]", 17, 7)
+MEM_TEST("st3 {v17.b, v18.b, v19.b}[13], [x5], #3", -9, 12)
+MEM_TEST("st3 {v17.b, v18.b, v19.b}[13], [x5], x6", 9, 13)
+
+
+MEM_TEST("ld3 {v17.d, v18.d, v19.d}[0], [x5]", 17, 7)
+MEM_TEST("ld3 {v17.d, v18.d, v19.d}[0], [x5], #24", -9, 12)
+MEM_TEST("ld3 {v17.d, v18.d, v19.d}[0], [x5], x6", 9, 13)
+
+MEM_TEST("ld3 {v17.d, v18.d, v19.d}[1], [x5]", 17, 7)
+MEM_TEST("ld3 {v17.d, v18.d, v19.d}[1], [x5], #24", -9, 12)
+MEM_TEST("ld3 {v17.d, v18.d, v19.d}[1], [x5], x6", 9, 13)
+
+MEM_TEST("ld3 {v17.s, v18.s, v19.s}[0], [x5]", 17, 7)
+MEM_TEST("ld3 {v17.s, v18.s, v19.s}[0], [x5], #12", -9, 12)
+MEM_TEST("ld3 {v17.s, v18.s, v19.s}[0], [x5], x6", 9, 13)
+
+MEM_TEST("ld3 {v17.s, v18.s, v19.s}[3], [x5]", 17, 7)
+MEM_TEST("ld3 {v17.s, v18.s, v19.s}[3], [x5], #12", -9, 12)
+MEM_TEST("ld3 {v17.s, v18.s, v19.s}[3], [x5], x6", 9, 13)
+
+MEM_TEST("ld3 {v17.h, v18.h, v19.h}[0], [x5]", 17, 7)
+MEM_TEST("ld3 {v17.h, v18.h, v19.h}[0], [x5], #6", -9, 12)
+MEM_TEST("ld3 {v17.h, v18.h, v19.h}[0], [x5], x6", 9, 13)
+
+MEM_TEST("ld3 {v17.h, v18.h, v19.h}[6], [x5]", 17, 7)
+MEM_TEST("ld3 {v17.h, v18.h, v19.h}[6], [x5], #6", -9, 12)
+MEM_TEST("ld3 {v17.h, v18.h, v19.h}[6], [x5], x6", 9, 13)
+
+MEM_TEST("ld3 {v17.b, v18.b, v19.b}[0], [x5]", 17, 7)
+MEM_TEST("ld3 {v17.b, v18.b, v19.b}[0], [x5], #3", -9, 12)
+MEM_TEST("ld3 {v17.b, v18.b, v19.b}[0], [x5], x6", 9, 13)
+
+MEM_TEST("ld3 {v17.b, v18.b, v19.b}[13], [x5]", 17, 7)
+MEM_TEST("ld3 {v17.b, v18.b, v19.b}[13], [x5], #3", -9, 12)
+MEM_TEST("ld3 {v17.b, v18.b, v19.b}[13], [x5], x6", 9, 13)
////////////////////////////////////////////////////////////////
printf("LD4/ST4 (single 4-elem struct to/from one lane of 4 regs\n");
-//MEM_TEST("st4 {v17.d, v18.d, v19.d, v20.d}[0], [x5]", 17, 7)
-//MEM_TEST("st4 {v17.d, v18.d, v19.d, v20.d}[0], [x5], #32", -9, 12)
-//MEM_TEST("st4 {v17.d, v18.d, v19.d, v20.d}[0], [x5], x6", 9, 13)
-//
-//MEM_TEST("st4 {v17.d, v18.d, v19.d, v20.d}[1], [x5]", 17, 7)
-//MEM_TEST("st4 {v17.d, v18.d, v19.d, v20.d}[1], [x5], #32", -9, 12)
-//MEM_TEST("st4 {v17.d, v18.d, v19.d, v20.d}[1], [x5], x6", 9, 13)
-//
-//MEM_TEST("st4 {v17.s, v18.s, v19.s, v20.s}[0], [x5]", 17, 7)
-//MEM_TEST("st4 {v17.s, v18.s, v19.s, v20.s}[0], [x5], #16", -9, 12)
-//MEM_TEST("st4 {v17.s, v18.s, v19.s, v20.s}[0], [x5], x6", 9, 13)
-//
-//MEM_TEST("st4 {v17.s, v18.s, v19.s, v20.s}[3], [x5]", 17, 7)
-//MEM_TEST("st4 {v17.s, v18.s, v19.s, v20.s}[3], [x5], #16", -9, 12)
-//MEM_TEST("st4 {v17.s, v18.s, v19.s, v20.s}[3], [x5], x6", 9, 13)
-//
-//MEM_TEST("st4 {v17.h, v18.h, v19.h, v20.h}[0], [x5]", 17, 7)
-//MEM_TEST("st4 {v17.h, v18.h, v19.h, v20.h}[0], [x5], #8", -9, 12)
-//MEM_TEST("st4 {v17.h, v18.h, v19.h, v20.h}[0], [x5], x6", 9, 13)
-//
-//MEM_TEST("st4 {v17.h, v18.h, v19.h, v20.h}[6], [x5]", 17, 7)
-//MEM_TEST("st4 {v17.h, v18.h, v19.h, v20.h}[6], [x5], #8", -9, 12)
-//MEM_TEST("st4 {v17.h, v18.h, v19.h, v20.h}[6], [x5], x6", 9, 13)
-//
-//MEM_TEST("st4 {v17.b, v18.b, v19.b, v20.b}[0], [x5]", 17, 7)
-//MEM_TEST("st4 {v17.b, v18.b, v19.b, v20.b}[0], [x5], #4", -9, 12)
-//MEM_TEST("st4 {v17.b, v18.b, v19.b, v20.b}[0], [x5], x6", 9, 13)
-//
-//MEM_TEST("st4 {v17.b, v18.b, v19.b, v20.b}[13], [x5]", 17, 7)
-//MEM_TEST("st4 {v17.b, v18.b, v19.b, v20.b}[13], [x5], #4", -9, 12)
-//MEM_TEST("st4 {v17.b, v18.b, v19.b, v20.b}[13], [x5], x6", 9, 13)
-//
-//
-//MEM_TEST("ld4 {v17.d, v18.d, v19.d, v20.d}[0], [x5]", 17, 7)
-//MEM_TEST("ld4 {v17.d, v18.d, v19.d, v20.d}[0], [x5], #32", -9, 12)
-//MEM_TEST("ld4 {v17.d, v18.d, v19.d, v20.d}[0], [x5], x6", 9, 13)
-//
-//MEM_TEST("ld4 {v17.d, v18.d, v19.d, v20.d}[1], [x5]", 17, 7)
-//MEM_TEST("ld4 {v17.d, v18.d, v19.d, v20.d}[1], [x5], #32", -9, 12)
-//MEM_TEST("ld4 {v17.d, v18.d, v19.d, v20.d}[1], [x5], x6", 9, 13)
-//
-//MEM_TEST("ld4 {v17.s, v18.s, v19.s, v20.s}[0], [x5]", 17, 7)
-//MEM_TEST("ld4 {v17.s, v18.s, v19.s, v20.s}[0], [x5], #16", -9, 12)
-//MEM_TEST("ld4 {v17.s, v18.s, v19.s, v20.s}[0], [x5], x6", 9, 13)
-//
-//MEM_TEST("ld4 {v17.s, v18.s, v19.s, v20.s}[3], [x5]", 17, 7)
-//MEM_TEST("ld4 {v17.s, v18.s, v19.s, v20.s}[3], [x5], #16", -9, 12)
-//MEM_TEST("ld4 {v17.s, v18.s, v19.s, v20.s}[3], [x5], x6", 9, 13)
-//
-//MEM_TEST("ld4 {v17.h, v18.h, v19.h, v20.h}[0], [x5]", 17, 7)
-//MEM_TEST("ld4 {v17.h, v18.h, v19.h, v20.h}[0], [x5], #8", -9, 12)
-//MEM_TEST("ld4 {v17.h, v18.h, v19.h, v20.h}[0], [x5], x6", 9, 13)
-//
-//MEM_TEST("ld4 {v17.h, v18.h, v19.h, v20.h}[6], [x5]", 17, 7)
-//MEM_TEST("ld4 {v17.h, v18.h, v19.h, v20.h}[6], [x5], #8", -9, 12)
-//MEM_TEST("ld4 {v17.h, v18.h, v19.h, v20.h}[6], [x5], x6", 9, 13)
-//
-//MEM_TEST("ld4 {v17.b, v18.b, v19.b, v20.b}[0], [x5]", 17, 7)
-//MEM_TEST("ld4 {v17.b, v18.b, v19.b, v20.b}[0], [x5], #4", -9, 12)
-//MEM_TEST("ld4 {v17.b, v18.b, v19.b, v20.b}[0], [x5], x6", 9, 13)
-//
-//MEM_TEST("ld4 {v17.b, v18.b, v19.b, v20.b}[13], [x5]", 17, 7)
-//MEM_TEST("ld4 {v17.b, v18.b, v19.b, v20.b}[13], [x5], #4", -9, 12)
-//MEM_TEST("ld4 {v17.b, v18.b, v19.b, v20.b}[13], [x5], x6", 9, 13)
+MEM_TEST("st4 {v17.d, v18.d, v19.d, v20.d}[0], [x5]", 17, 7)
+MEM_TEST("st4 {v17.d, v18.d, v19.d, v20.d}[0], [x5], #32", -9, 12)
+MEM_TEST("st4 {v17.d, v18.d, v19.d, v20.d}[0], [x5], x6", 9, 13)
+
+MEM_TEST("st4 {v17.d, v18.d, v19.d, v20.d}[1], [x5]", 17, 7)
+MEM_TEST("st4 {v17.d, v18.d, v19.d, v20.d}[1], [x5], #32", -9, 12)
+MEM_TEST("st4 {v17.d, v18.d, v19.d, v20.d}[1], [x5], x6", 9, 13)
+
+MEM_TEST("st4 {v17.s, v18.s, v19.s, v20.s}[0], [x5]", 17, 7)
+MEM_TEST("st4 {v17.s, v18.s, v19.s, v20.s}[0], [x5], #16", -9, 12)
+MEM_TEST("st4 {v17.s, v18.s, v19.s, v20.s}[0], [x5], x6", 9, 13)
+
+MEM_TEST("st4 {v17.s, v18.s, v19.s, v20.s}[3], [x5]", 17, 7)
+MEM_TEST("st4 {v17.s, v18.s, v19.s, v20.s}[3], [x5], #16", -9, 12)
+MEM_TEST("st4 {v17.s, v18.s, v19.s, v20.s}[3], [x5], x6", 9, 13)
+
+MEM_TEST("st4 {v17.h, v18.h, v19.h, v20.h}[0], [x5]", 17, 7)
+MEM_TEST("st4 {v17.h, v18.h, v19.h, v20.h}[0], [x5], #8", -9, 12)
+MEM_TEST("st4 {v17.h, v18.h, v19.h, v20.h}[0], [x5], x6", 9, 13)
+
+MEM_TEST("st4 {v17.h, v18.h, v19.h, v20.h}[6], [x5]", 17, 7)
+MEM_TEST("st4 {v17.h, v18.h, v19.h, v20.h}[6], [x5], #8", -9, 12)
+MEM_TEST("st4 {v17.h, v18.h, v19.h, v20.h}[6], [x5], x6", 9, 13)
+
+MEM_TEST("st4 {v17.b, v18.b, v19.b, v20.b}[0], [x5]", 17, 7)
+MEM_TEST("st4 {v17.b, v18.b, v19.b, v20.b}[0], [x5], #4", -9, 12)
+MEM_TEST("st4 {v17.b, v18.b, v19.b, v20.b}[0], [x5], x6", 9, 13)
+
+MEM_TEST("st4 {v17.b, v18.b, v19.b, v20.b}[13], [x5]", 17, 7)
+MEM_TEST("st4 {v17.b, v18.b, v19.b, v20.b}[13], [x5], #4", -9, 12)
+MEM_TEST("st4 {v17.b, v18.b, v19.b, v20.b}[13], [x5], x6", 9, 13)
+
+
+MEM_TEST("ld4 {v17.d, v18.d, v19.d, v20.d}[0], [x5]", 17, 7)
+MEM_TEST("ld4 {v17.d, v18.d, v19.d, v20.d}[0], [x5], #32", -9, 12)
+MEM_TEST("ld4 {v17.d, v18.d, v19.d, v20.d}[0], [x5], x6", 9, 13)
+
+MEM_TEST("ld4 {v17.d, v18.d, v19.d, v20.d}[1], [x5]", 17, 7)
+MEM_TEST("ld4 {v17.d, v18.d, v19.d, v20.d}[1], [x5], #32", -9, 12)
+MEM_TEST("ld4 {v17.d, v18.d, v19.d, v20.d}[1], [x5], x6", 9, 13)
+
+MEM_TEST("ld4 {v17.s, v18.s, v19.s, v20.s}[0], [x5]", 17, 7)
+MEM_TEST("ld4 {v17.s, v18.s, v19.s, v20.s}[0], [x5], #16", -9, 12)
+MEM_TEST("ld4 {v17.s, v18.s, v19.s, v20.s}[0], [x5], x6", 9, 13)
+
+MEM_TEST("ld4 {v17.s, v18.s, v19.s, v20.s}[3], [x5]", 17, 7)
+MEM_TEST("ld4 {v17.s, v18.s, v19.s, v20.s}[3], [x5], #16", -9, 12)
+MEM_TEST("ld4 {v17.s, v18.s, v19.s, v20.s}[3], [x5], x6", 9, 13)
+
+MEM_TEST("ld4 {v17.h, v18.h, v19.h, v20.h}[0], [x5]", 17, 7)
+MEM_TEST("ld4 {v17.h, v18.h, v19.h, v20.h}[0], [x5], #8", -9, 12)
+MEM_TEST("ld4 {v17.h, v18.h, v19.h, v20.h}[0], [x5], x6", 9, 13)
+
+MEM_TEST("ld4 {v17.h, v18.h, v19.h, v20.h}[6], [x5]", 17, 7)
+MEM_TEST("ld4 {v17.h, v18.h, v19.h, v20.h}[6], [x5], #8", -9, 12)
+MEM_TEST("ld4 {v17.h, v18.h, v19.h, v20.h}[6], [x5], x6", 9, 13)
+
+MEM_TEST("ld4 {v17.b, v18.b, v19.b, v20.b}[0], [x5]", 17, 7)
+MEM_TEST("ld4 {v17.b, v18.b, v19.b, v20.b}[0], [x5], #4", -9, 12)
+MEM_TEST("ld4 {v17.b, v18.b, v19.b, v20.b}[0], [x5], x6", 9, 13)
+
+MEM_TEST("ld4 {v17.b, v18.b, v19.b, v20.b}[13], [x5]", 17, 7)
+MEM_TEST("ld4 {v17.b, v18.b, v19.b, v20.b}[13], [x5], #4", -9, 12)
+MEM_TEST("ld4 {v17.b, v18.b, v19.b, v20.b}[13], [x5], x6", 9, 13)
} /* end of test_memory2() */
diff --git a/none/tests/arm64/memory.stdout.exp b/none/tests/arm64/memory.stdout.exp
index 328b5e0..f271f62 100644
--- a/none/tests/arm64/memory.stdout.exp
+++ b/none/tests/arm64/memory.stdout.exp
@@ -12868,7 +12868,7 @@
0 x6 (sub, index reg)
LD1/ST1 (multiple 1-elem structs to/from 2/3/4 regs
-st1 {v19.16b, v20.16b}, [x5] with x5 = middle_of_block+17, x6=7
+st1 {v19.2d, v20.2d}, [x5] with x5 = middle_of_block+17, x6=7
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
@@ -12898,7 +12898,7 @@
0 x5 (sub, base reg)
0 x6 (sub, index reg)
-st1 {v19.16b, v20.16b}, [x5], #32 with x5 = middle_of_block+9, x6=9
+st1 {v19.2d, v20.2d}, [x5], #32 with x5 = middle_of_block+9, x6=9
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
@@ -12928,7 +12928,37 @@
32 x5 (sub, base reg)
0 x6 (sub, index reg)
-st1 {v17.16b, v18.16b, v19.16b}, [x5] with x5 = middle_of_block+17, x6=7
+st1 {v19.2d, v20.2d}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. b7 10 15 41 15 b8 2c 6e db 28 f2 d7 47
+ [128] 4f bf a9 40 86 92 62 1c f1 f3 38 6d 13 a2 5a 69
+ [144] 84 87 11 .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.2d, v18.2d, v19.2d}, [x5] with x5 = middle_of_block+17, x6=7
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
@@ -12938,10 +12968,10 @@
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. 42 2e 44 6a fb 83 b4 f8 8a c7 10 14 20 59 b0
- [160] 05 87 6c 37 a4 c4 2d 54 60 57 58 a3 b8 3d 03 bd
- [176] 2f 8a 69 10 f2 0f 3e 9d 59 1f 1e 07 f1 f1 a1 35
- [192] 84 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 1f e8 e3 6e 69 c8 54 f8 f9 56 9e b5 97 .. b8
+ [160] f5 d0 8c a2 60 56 7c 78 4a 06 45 9a 11 3c be 74
+ [176] 1d 67 e0 .. 66 0d a8 1e 51 35 59 1e .. c1 7d 75
+ [192] 8e .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
@@ -12958,6 +12988,3666 @@
0 x5 (sub, base reg)
0 x6 (sub, index reg)
+st1 {v17.2d, v18.2d, v19.2d}, [x5], #48 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 21 c8 67 be 01 c2 e8
+ [144] 3d fc 44 99 7b 2d 90 02 49 ec e0 27 8d 9b 7f 0b
+ [160] ea 43 a3 7e 70 f2 fc c8 c0 04 74 19 de 49 13 c8
+ [176] 6b de 1b 86 cf 2a 72 6f 8a .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 48 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.2d, v18.2d, v19.2d}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. b6 e3 13 2f 3e 50 28 17 88 37 9a be 73
+ [128] 14 9e e3 d4 a8 94 58 61 65 a2 a3 9b 37 e7 49 d5
+ [144] c1 a9 a5 ff 73 7b 55 81 f7 ea 68 3f 7e 39 a7 f0
+ [160] 26 59 97 .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 48 ef 91 5a a4 81 65 25 24 bc 89 74 7e 02 af
+ [160] 3b dc 84 94 74 1e 93 75 be 8e 84 9c f8 db 36 db
+ [176] d6 cd 98 5d a2 39 4e 91 6a 95 40 60 10 f0 9d d5
+ [192] 1e 58 97 .. e3 e3 47 7a 58 f4 59 67 bb 29 d0 e0
+ [208] 3f .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], #64 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 31 fd 13 1d 73 d8 5c
+ [144] 1e a2 df 21 b6 82 4b 3d bf 4f be dd 0e d0 d3 39
+ [160] 74 4a 1e f3 9e c7 5c 50 dd 52 69 20 22 3c 74 56
+ [176] 9c db e5 2f 90 79 47 ee 50 07 b9 fd 25 33 a4 89
+ [192] 99 a6 ec 78 5b 94 f6 6a 17 .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 64 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. 56 a0 d8 73 22 84 48 55 7c 1d 36 93 ef
+ [128] 5b d0 8c 5f 5a a4 5b 6f da 3c cc 81 95 0c d9 f3
+ [144] bd 03 25 83 a2 55 8e a9 15 5d d4 28 de 68 69 a1
+ [160] 3d 3c 45 4e 3d 2c c9 c8 e7 59 18 f8 3c 88 7f ef
+ [176] 10 2b 19 .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.1d, v20.1d}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 24 dd 94 f3 3c c6 d9 68 67 0a f4 71 1b e2 9d
+ [160] c4 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.1d, v20.1d}, [x5], #16 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. a0 be 83 71 16 e5 24
+ [144] 6e 66 8e 54 40 07 ee 34 37 .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 16 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.1d, v20.1d}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. 41 7e 9c 5b 1b e4 2b fe 58 .. 15 71 1b
+ [128] 5f 8c 8f .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.1d, v18.1d, v19.1d}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 58 44 53 21 95 89 a7 e3 59 de 93 7f 16 e0 3c
+ [160] 98 cd 4a 87 24 f4 67 8d 1c .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.1d, v18.1d, v19.1d}, [x5], #24 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. f6 36 ae ea 62 14 6d
+ [144] d1 d9 5c c4 59 2c 85 a5 9c 31 96 f1 2c c8 bb f8
+ [160] 88 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 24 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.1d, v18.1d, v19.1d}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. 35 66 20 e4 c8 be 21 81 24 52 4c f7 7f
+ [128] 50 19 03 b6 77 a7 13 49 a4 67 84 .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 02 12 a7 fd 0a 5a 16 71 4f 8f 9e b9 e6 d0 c8
+ [160] a2 44 8d 5d 2f c0 9f 92 f0 ac 10 95 bf ab 49 c5
+ [176] ae .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x5], #32 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 6b ba dc 57 a1 bb 49
+ [144] a4 a1 29 c3 b5 40 15 4a 7d e9 a2 7a 72 3c 24 ed
+ [160] d0 6a 81 a0 8c a3 df 0a af .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. f4 b2 a2 d1 07 06 db 2e 6d 72 5c b5 14
+ [128] 46 76 d4 66 c6 6c 72 d9 .. 3d 07 1d 08 16 a8 75
+ [144] c2 65 d1 .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.4s, v20.4s}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 63 0e .. 81 cf 96 44 d4 be 4b d6 fa 99 0c f0
+ [160] 76 79 1e d7 e2 e6 5a 0f 5b b8 ed b5 bf 98 27 08
+ [176] 13 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.4s, v20.4s}, [x5], #32 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. e6 c4 81 48 68 a9 9a
+ [144] f6 ba 32 80 8e ab 8d 53 ce cc b7 c5 9a 6c cb 9a
+ [160] 11 36 03 c5 d0 9c fb b9 c6 .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.4s, v20.4s}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. 68 6d f9 26 35 e0 5a 4c 64 b4 3b 95 56
+ [128] 22 37 7b f9 ce bd 6d c1 c9 86 40 b1 22 32 a4 4e
+ [144] 3e 04 14 .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.4s, v18.4s, v19.4s}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. f6 37 55 a4 ce 55 35 70 66 0d 55 e3 28 16 72
+ [160] 97 09 e2 5a 86 56 e2 d7 a4 bc 72 8f 2e 6f 3b c5
+ [176] bf d0 1d ed 7c b7 06 2b cb 05 de 40 0e a6 84 8c
+ [192] 70 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.4s, v18.4s, v19.4s}, [x5], #48 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 58 50 99 c1 0c 57 cd
+ [144] 36 22 c0 a7 0e 93 30 ee ba e6 78 fb 20 52 e3 fa
+ [160] d4 76 7e 85 72 6d dc 34 22 53 ba 3f bf 7e 26 b0
+ [176] 45 ae f3 35 01 8c 72 4e dc .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 48 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.4s, v18.4s, v19.4s}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. 4d b7 62 75 20 07 66 97 02 7d 68 ef f0
+ [128] d8 e1 87 c9 2a a0 27 5f d1 f9 f1 a3 42 f0 ec 3c
+ [144] f2 25 a0 b1 d4 43 7d 39 87 9a 94 34 81 7f 8a e2
+ [160] 31 4d f9 .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. 0c ee 6f de fe 24 e0 43 21 1c 82 f3 28 77
+ [160] 5d 96 69 17 7a 11 2a 13 da 97 20 4c f6 12 05 9a
+ [176] 7b 58 26 f6 97 f7 1d 3d 26 58 f4 1e fe f9 34 bb
+ [192] 82 85 ab 9e c9 7b 6f 65 f5 40 05 23 99 15 4f 1c
+ [208] a5 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], #64 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 90 e3 68 be f8 cc b4
+ [144] f8 81 58 .. a8 33 2b 8d 11 93 f2 32 bf a2 56 7a
+ [160] 3d 55 36 2b 7f 2e 3b 01 1f 0a 8c 26 a1 2c 66 72
+ [176] 56 a4 3b 6f 20 65 06 f0 82 c4 6a 64 34 10 e6 6e
+ [192] 42 bb 21 71 58 d5 73 ae 39 .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 64 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. 69 b0 a0 eb 7b 03 38 12 d1 cf 7c c6 81
+ [128] 56 04 7d 8e 79 28 fd 23 ed c5 77 24 6f 8e 1e af
+ [144] 05 f1 8c 31 .. 95 2a 57 2b bf 7c 78 0f 26 8f 27
+ [160] 40 23 33 d8 0b 27 2e 10 72 d5 cf 55 f3 82 55 e0
+ [176] 3f 4a 9d .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.2s, v20.2s}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 0b 29 e2 92 34 84 8e 57 3f f8 db 1c e9 fb 51
+ [160] 3c .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.2s, v20.2s}, [x5], #16 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. bd c8 05 81 c6 70 92
+ [144] c2 3b c0 a8 dd 11 b1 51 ae .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 16 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.2s, v20.2s}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. eb 3c 2f 40 a2 8b 37 79 41 fd e0 c7 aa
+ [128] 38 e6 c3 .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.2s, v18.2s, v19.2s}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 97 80 c8 f7 37 6a 60 20 c0 6e 6c 61 69 ed 5f
+ [160] 82 39 60 d3 ea 5c ba f1 b0 .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.2s, v18.2s, v19.2s}, [x5], #24 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 66 56 86 c7 9c 46 ec
+ [144] 6c fd 14 f6 86 5a 81 fd 3b 57 cb 7e ad bf 4a f1
+ [160] 5a .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 24 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.2s, v18.2s, v19.2s}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. be 33 d8 81 8a 0c 75 77 b5 60 14 d9 b4
+ [128] f3 36 a3 11 0c 14 42 7a 09 e8 44 .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. e3 9e 47 b3 41 ab ed f2 ff bc f8 b8 54 fc 3d
+ [160] 6c de cd c1 90 09 ff bf 42 1f 68 a3 a8 43 ca 13
+ [176] d6 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], #32 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. c3 b7 15 d2 15 cc 7c
+ [144] 1e 14 cd 6c 7d ee 5d 4c 5a 03 10 d5 cc 3a b0 c5
+ [160] 7d 87 6b 3d cf d3 47 12 ad .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. 77 fc d2 62 be 5c e1 20 2f 9a 01 96 54
+ [128] ee 8b df 67 54 5e ef 6b a9 3c df af 93 f6 9b 71
+ [144] 2a fc b8 .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.8h, v20.8h}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. bb ee 18 28 8c d0 19 71 12 e1 c9 57 c6 7c 16
+ [160] 59 bd 62 20 b5 8a 87 0f d5 61 d7 52 c9 34 9c f0
+ [176] 73 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.8h, v20.8h}, [x5], #32 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 43 0d 70 9b d0 f8 ea
+ [144] d2 2e 7c a0 ed 76 56 e0 .. f9 ea c1 38 4e 87 20
+ [160] 59 42 08 ca db c7 21 74 e4 .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.8h, v20.8h}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. 8a 4b 3e 4a a3 c5 43 a5 9f e2 e3 71 73
+ [128] 51 ec 26 a5 d7 4a 76 36 9f d4 83 25 13 23 cf c2
+ [144] 95 bd b2 .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.8h, v18.8h, v19.8h}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. db df 8c 1a ef 07 87 74 c2 5d 71 50 d3 11 bd
+ [160] 44 0f 12 17 ec d0 ed e8 89 22 bb 29 8c 7c 1f e7
+ [176] 6c c9 b5 20 d2 9c 89 2b d1 44 fd 48 5c 26 70 b5
+ [192] 5f .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.8h, v18.8h, v19.8h}, [x5], #48 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 41 88 d6 79 b5 a6 a7
+ [144] 70 5c aa dd d4 79 cb 6f 6d 54 3d 19 66 68 82 1e
+ [160] fe 7c 46 f4 a8 28 36 77 c3 d4 ae ec 54 d2 f5 0c
+ [176] 5e 10 3b 8d 65 ec 6b 43 6e .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 48 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.8h, v18.8h, v19.8h}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. 46 3b 81 aa 42 ad d1 41 1e 92 06 ef 6b
+ [128] 29 d0 b7 9f 9e 7b a5 1a 6a 7c 2a cc 5f ca 1d 22
+ [144] ee 4d e6 c6 67 da 15 30 84 76 6b cb d4 94 bd d3
+ [160] 49 ee 66 .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 48 85 91 c6 53 a1 d3 26 d2 21 93 cf 03 34 4f
+ [160] 8c 9f 28 1f bf 01 66 e1 81 d0 d8 23 34 a4 39 aa
+ [176] 2b f3 0c 55 cd 71 11 5a 6e 09 43 41 2c 1d b1 31
+ [192] f3 81 9a 42 ef 8f 3c 01 1e 3a cb 84 b7 dc 35 29
+ [208] 16 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], #64 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 23 77 46 14 9c 7a 81
+ [144] 12 f4 3f 89 cc e3 04 f0 a2 c9 54 51 23 54 13 72
+ [160] 47 b3 3b 4c 93 54 94 07 a1 75 5d 35 d4 ba 14 82
+ [176] 4f 7f ff d9 e2 d0 be 87 f4 f2 4a 15 f6 4c 62 89
+ [192] 2c a1 43 d4 8b 55 6c c7 9a .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 64 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. dd f3 38 d3 11 f0 54 79 c7 d3 90 48 10
+ [128] 5f e5 79 a1 0b 7c cd 94 ae 7a 8c e8 d9 df 71 ea
+ [144] 98 8b bf 41 10 a4 b4 42 30 4d 4f 6a 10 b2 84 ac
+ [160] d1 b6 ac 45 c9 f3 41 16 2a 7d 71 d5 bb 4b bb 50
+ [176] 3a 16 6c .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.4h, v20.4h}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 12 1f 84 41 f7 b8 45 a2 18 63 1c 4a a6 9e 4b
+ [160] c3 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.4h, v20.4h}, [x5], #16 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 9b d1 21 16 26 04 84
+ [144] 26 39 42 19 f2 6f 12 b5 69 .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 16 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.4h, v20.4h}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. 05 fa 23 e4 77 6f ff ef df ae 6e 30 0c
+ [128] 43 a0 88 .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.4h, v18.4h, v19.4h}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 64 16 81 0d 15 6f 0a eb 9b 2b 8c f8 1b 33 b6
+ [160] ac 7c f8 ec 58 c9 dc 4e b8 .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.4h, v18.4h, v19.4h}, [x5], #24 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 0a 25 e7 58 f5 33 df
+ [144] 45 b9 d0 36 59 4b cb 8d 4e f7 d6 1c 48 9c 3d 67
+ [160] 54 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 24 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.4h, v18.4h, v19.4h}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. a8 30 5f 8e 8a c8 f6 17 eb 53 10 7c ac
+ [128] f7 22 83 d6 bb 98 07 71 43 5d 56 .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. d2 82 ad a9 33 22 35 fd a2 17 1b 6d a1 61 68
+ [160] 75 d1 90 70 99 d5 2d 65 08 cc 14 01 ae 83 2b 1d
+ [176] 25 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], #32 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. cf 62 58 02 29 96 a4
+ [144] d7 9e 73 a3 ec e1 f4 06 ab 19 54 c2 42 9e 9d 9a
+ [160] 54 03 80 ef 22 0e a5 db 07 .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. 5c f7 d1 e1 b4 9f 13 3c 97 28 db bb 56
+ [128] 78 6f aa d3 7c 67 84 c3 a7 2f 8a ee 6b 52 fa b7
+ [144] da 29 06 .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.16b, v20.16b}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. b1 79 06 df 94 80 71 6a e5 61 31 c4 9f 22 db
+ [160] 18 60 d1 80 98 38 ac d1 ab 49 2b a4 e2 3c c6 ba
+ [176] b0 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.16b, v20.16b}, [x5], #32 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. e4 54 78 72 67 53 3f
+ [144] bf 44 85 f8 52 50 69 11 42 2b 9c 17 59 1e cc ea
+ [160] b2 b0 4a 47 ea c2 10 13 12 .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.16b, v20.16b}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. 1e aa e2 ad 5e 68 ea 78 8c b1 eb 6e 9e
+ [128] de dc ac 43 a1 36 7f 78 71 e0 01 cc e4 72 d8 c4
+ [144] 89 b3 eb .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.16b, v18.16b, v19.16b}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. d0 e2 88 d0 ca e0 4a 05 0d 48 f2 fe 9a f2 9a
+ [160] fd e5 1c d9 91 c6 9e a9 fa 36 1d 67 2a 65 68 da
+ [176] 26 4f a6 98 68 bc 33 1b 64 f1 b7 34 e9 40 43 ef
+ [192] 5b .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.16b, v18.16b, v19.16b}, [x5], #48 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. df 6c 1b e4 fe ae 76
+ [144] ea a9 03 3d cf de 60 84 5e 36 30 7f 60 de 5a 75
+ [160] 67 55 fe cc 12 23 0a 8e a5 8a 50 23 9e 45 7c df
+ [176] b8 05 f0 8e fe 4b 5e 4b 40 .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 48 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.16b, v18.16b, v19.16b}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. a2 71 71 ce a2 3f 66 17 dc 79 73 be e3
+ [128] 07 6b 72 58 03 27 d3 95 30 2c 4e 18 8d 74 dd 86
+ [144] b8 20 77 3b 2a 42 1c 64 ed 7e ed 05 79 79 3e c1
+ [160] 6f 3b dd .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 20 56 79 5c 02 6b 74 f9 d0 ba ef 5d ae 26 39
+ [160] c7 f8 c2 ad 45 eb 48 e0 b4 37 a8 1d b1 91 d4 0a
+ [176] e6 9d 4d 77 43 a5 2c e8 43 a9 2b c8 99 5e 15 39
+ [192] 70 4c 61 eb 55 1e b0 4e d4 e4 ab 8a 15 7e 81 07
+ [208] 95 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], #64 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. e8 b9 ac 1d 5e e2 c4
+ [144] 6c fa 95 ba 25 93 d7 69 74 f3 e5 38 3c e3 0a 1d
+ [160] 90 65 2f 55 da 38 67 61 63 93 dc 4d bb e7 7a 88
+ [176] 8a 6d 32 6b d8 ba 71 b4 a6 94 57 0d 6d e6 18 d8
+ [192] 56 5c 54 9f f1 14 dd b6 3c .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 64 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. b4 66 9f 2a e6 4a 9c 8c 61 28 76 1a 9e
+ [128] 74 71 80 94 0d 9f ce c2 1a 5b 0c cf d5 01 d4 a2
+ [144] 7a d1 bc b1 d1 83 2d 6c 20 07 4e fe e2 10 47 2f
+ [160] ed f5 b0 94 78 8e 04 da 0e 4f fe 76 95 e5 b0 3d
+ [176] 03 8e 86 .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.8b, v20.8b}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 38 bf 7d 01 84 63 fc 49 f5 4d b5 fb 53 cc 8a
+ [160] 5c .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.8b, v20.8b}, [x5], #16 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 3d d6 d6 2f 34 a4 fc
+ [144] 9b 5d 17 a6 7e 1f 11 63 68 .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 16 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.8b, v20.8b}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. 93 ba 78 46 9a 90 83 60 34 16 c0 ac 3f
+ [128] 7e bb db .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.8b, v18.8b, v19.8b}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. c0 06 7f 62 2e 9b a6 41 e8 17 f6 42 2d b4 43
+ [160] 16 97 11 d2 6d 37 ca a4 34 .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.8b, v18.8b, v19.8b}, [x5], #24 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. e0 a0 d1 9e 6d d8 48
+ [144] 5f 0c 8c 82 d5 ff 63 57 d5 13 b7 cd .. 61 91 5a
+ [160] 76 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 24 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.8b, v18.8b, v19.8b}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. f5 5f b6 0a c9 f1 a2 61 ca 2a 3f e3 66
+ [128] 5b df a3 05 82 35 64 2d 53 c6 bb .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. d1 c0 d7 de e1 bf ee 96 37 9f 06 d6 cd .. 48
+ [160] bf 1a d4 6e 4b 25 2a 85 41 b6 19 b1 ce 6a 6f e5
+ [176] 9e .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], #32 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 8e bb a3 e5 da 1b c0
+ [144] d1 3f 1b 67 04 15 d9 7a 6f 29 6e 3f d3 68 ec 6d
+ [160] 51 e0 bd b7 85 55 fa 65 bc .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. a4 a2 a0 4f e8 cf 71 84 a5 1b e9 21 1a
+ [128] e2 24 34 aa 3c 88 2f e0 fa 17 08 dd 91 2a c3 46
+ [144] d5 f0 bb .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.2d, v20.2d}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 4349eeeba6d872be v19.d[0] (xor, xfer vecreg #3)
+ 54bf0263c2124d48 v19.d[1] (xor, xfer vecreg #3)
+ e4ec7af28c74f9e3 v20.d[0] (xor, xfer vecreg #3)
+ 49a5e7563faa7890 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.2d, v20.2d}, [x5], #32 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 4fa9de5d4fa6a9d8 v19.d[0] (xor, xfer vecreg #3)
+ 9d284758458ef60f v19.d[1] (xor, xfer vecreg #3)
+ e90b7bed00cfcd6e v20.d[0] (xor, xfer vecreg #3)
+ d099f7940245f582 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.2d, v20.2d}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 49cdc7a8f73aba3d v19.d[0] (xor, xfer vecreg #3)
+ 11184bd897b42334 v19.d[1] (xor, xfer vecreg #3)
+ 466a41888a867c2c v20.d[0] (xor, xfer vecreg #3)
+ c7fbe6fdc0e29eac v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.2d, v18.2d, v19.2d}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ e1822fe1cd49c1f4 v17.d[0] (xor, xfer vecreg #1)
+ cf0bcb8df428f458 v17.d[1] (xor, xfer vecreg #1)
+ 182436cb8be0009e v18.d[0] (xor, xfer vecreg #2)
+ eceee83b084fef07 v18.d[1] (xor, xfer vecreg #2)
+ 82051ffbc3dc12ba v19.d[0] (xor, xfer vecreg #3)
+ e7ca0a1e4b7d0e0f v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.2d, v18.2d, v19.2d}, [x5], #48 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ a44ab1251db700f2 v17.d[0] (xor, xfer vecreg #1)
+ b03216ce0e454809 v17.d[1] (xor, xfer vecreg #1)
+ 110394bf31326eff v18.d[0] (xor, xfer vecreg #2)
+ 47ba58a4f033e307 v18.d[1] (xor, xfer vecreg #2)
+ 572e422be522a0be v19.d[0] (xor, xfer vecreg #3)
+ b1694dae4d78358e v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 48 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.2d, v18.2d, v19.2d}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ e87b42c1625078e1 v17.d[0] (xor, xfer vecreg #1)
+ 5b5e7eee6cd0515c v17.d[1] (xor, xfer vecreg #1)
+ a33b2d3d50a2b71e v18.d[0] (xor, xfer vecreg #2)
+ dca0b1eafd177486 v18.d[1] (xor, xfer vecreg #2)
+ 27cec436968fee1c v19.d[0] (xor, xfer vecreg #3)
+ e1d4e35433539361 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ a90de512535b829f v17.d[0] (xor, xfer vecreg #1)
+ 3653020d55d36e3c v17.d[1] (xor, xfer vecreg #1)
+ 8cef30d00d415761 v18.d[0] (xor, xfer vecreg #2)
+ d24454d997cb74d4 v18.d[1] (xor, xfer vecreg #2)
+ a31ab3ac086169d5 v19.d[0] (xor, xfer vecreg #3)
+ 19715ed8c7d6d6cb v19.d[1] (xor, xfer vecreg #3)
+ 2edd49383eab04e6 v20.d[0] (xor, xfer vecreg #3)
+ 227f520e4d3ce5c4 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], #64 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 1e8a07c02a646be1 v17.d[0] (xor, xfer vecreg #1)
+ 8608abc1cebc68fe v17.d[1] (xor, xfer vecreg #1)
+ 2a8144d2081fa30f v18.d[0] (xor, xfer vecreg #2)
+ ac11b7dcda5831fe v18.d[1] (xor, xfer vecreg #2)
+ 048de55c79ae3963 v19.d[0] (xor, xfer vecreg #3)
+ a9f5222303e936ad v19.d[1] (xor, xfer vecreg #3)
+ c07c0920ef51bfe9 v20.d[0] (xor, xfer vecreg #3)
+ fe8f3f12ba547568 v20.d[1] (xor, xfer vecreg #3)
+ 64 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ d811300f10f67af5 v17.d[0] (xor, xfer vecreg #1)
+ 925baff6ce3455a4 v17.d[1] (xor, xfer vecreg #1)
+ 38a9d5b705fd8faa v18.d[0] (xor, xfer vecreg #2)
+ 853d58d9460ea1d7 v18.d[1] (xor, xfer vecreg #2)
+ 981d01d7bd3d438b v19.d[0] (xor, xfer vecreg #3)
+ c1217fb1274e87d4 v19.d[1] (xor, xfer vecreg #3)
+ 9af72fbfbb093945 v20.d[0] (xor, xfer vecreg #3)
+ ecd79ba85dde82da v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.1d, v20.1d}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 4b4b8f63d0570883 v19.d[0] (xor, xfer vecreg #3)
+ 74f02a3ed329b63c v19.d[1] (xor, xfer vecreg #3)
+ 0c15823271d953db v20.d[0] (xor, xfer vecreg #3)
+ c9f1f9763decd0f1 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.1d, v20.1d}, [x5], #16 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ ee08d40e542426a2 v19.d[0] (xor, xfer vecreg #3)
+ 909319a4965e86b9 v19.d[1] (xor, xfer vecreg #3)
+ bb6e566587534659 v20.d[0] (xor, xfer vecreg #3)
+ d5995cacb1816d2c v20.d[1] (xor, xfer vecreg #3)
+ 16 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.1d, v20.1d}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 345c1236796b8b92 v19.d[0] (xor, xfer vecreg #3)
+ 60062587836aa3c7 v19.d[1] (xor, xfer vecreg #3)
+ 473c3ebbcd6bd242 v20.d[0] (xor, xfer vecreg #3)
+ 7bff31fd95bb0f75 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.1d, v18.1d, v19.1d}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ fd5e1d8608c471bd v17.d[0] (xor, xfer vecreg #1)
+ b3e92ec493788abb v17.d[1] (xor, xfer vecreg #1)
+ c00493a6c3a93068 v18.d[0] (xor, xfer vecreg #2)
+ d2b6a273e03f21e0 v18.d[1] (xor, xfer vecreg #2)
+ 230f986bea845f88 v19.d[0] (xor, xfer vecreg #3)
+ 2a3d31fa1e8133b9 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.1d, v18.1d, v19.1d}, [x5], #24 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ c9dbc9079fc55a1a v17.d[0] (xor, xfer vecreg #1)
+ c029f68f571ac3ee v17.d[1] (xor, xfer vecreg #1)
+ 73aec88d09e45cf6 v18.d[0] (xor, xfer vecreg #2)
+ 0f3b1e4f94806810 v18.d[1] (xor, xfer vecreg #2)
+ c036c80f6f92eefb v19.d[0] (xor, xfer vecreg #3)
+ 302c2212ecd858e3 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 24 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.1d, v18.1d, v19.1d}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ b88687ba3422c2a5 v17.d[0] (xor, xfer vecreg #1)
+ 02b95a57c613c930 v17.d[1] (xor, xfer vecreg #1)
+ ffab61270fbd7a55 v18.d[0] (xor, xfer vecreg #2)
+ 66fe8cc439e832ce v18.d[1] (xor, xfer vecreg #2)
+ 9c2f4ff0a8eba2a2 v19.d[0] (xor, xfer vecreg #3)
+ b7c7dbe371a23899 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 476981f76cc6aa62 v17.d[0] (xor, xfer vecreg #1)
+ bc8e40306297c1d7 v17.d[1] (xor, xfer vecreg #1)
+ dbede72816dbae47 v18.d[0] (xor, xfer vecreg #2)
+ 1df3d1e952a8a56e v18.d[1] (xor, xfer vecreg #2)
+ 31263c1bdc78ff4f v19.d[0] (xor, xfer vecreg #3)
+ 030241812f14f62f v19.d[1] (xor, xfer vecreg #3)
+ c5babb781571b1e9 v20.d[0] (xor, xfer vecreg #3)
+ 7313d1dbd72a8eb7 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x5], #32 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0d36aaf487775e00 v17.d[0] (xor, xfer vecreg #1)
+ 339a892db1dbd036 v17.d[1] (xor, xfer vecreg #1)
+ a8bb1b9cc7d85df8 v18.d[0] (xor, xfer vecreg #2)
+ 770ed1d064f6e444 v18.d[1] (xor, xfer vecreg #2)
+ 98dfe7ad814da254 v19.d[0] (xor, xfer vecreg #3)
+ 58d138ffad61b6fa v19.d[1] (xor, xfer vecreg #3)
+ 52d04fa518922726 v20.d[0] (xor, xfer vecreg #3)
+ 1c7b3fdea9ab6033 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0904145e6cc0035d v17.d[0] (xor, xfer vecreg #1)
+ abd21c63371219a1 v17.d[1] (xor, xfer vecreg #1)
+ 84e835e3cdda9369 v18.d[0] (xor, xfer vecreg #2)
+ b7436f8ef20612a5 v18.d[1] (xor, xfer vecreg #2)
+ af0ea2c47fc07619 v19.d[0] (xor, xfer vecreg #3)
+ f928a3736cbe9c4d v19.d[1] (xor, xfer vecreg #3)
+ 594e1f63087e3d98 v20.d[0] (xor, xfer vecreg #3)
+ f8597873030a0eb5 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.4s, v20.4s}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 9162c78b8de0739d v19.d[0] (xor, xfer vecreg #3)
+ 7bbc10af32e120f9 v19.d[1] (xor, xfer vecreg #3)
+ 9aa85e4e9284565c v20.d[0] (xor, xfer vecreg #3)
+ 4c31fd95c79a70f5 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.4s, v20.4s}, [x5], #32 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 5e082465ec3c2f35 v19.d[0] (xor, xfer vecreg #3)
+ 199cb2302abd52ed v19.d[1] (xor, xfer vecreg #3)
+ 92520d8c6bdf8995 v20.d[0] (xor, xfer vecreg #3)
+ ae0ffc6f14ec97cf v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.4s, v20.4s}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 71ab64c0f05e14bd v19.d[0] (xor, xfer vecreg #3)
+ ccb31d3e426d5183 v19.d[1] (xor, xfer vecreg #3)
+ b2ea33679c7e997f v20.d[0] (xor, xfer vecreg #3)
+ f6afdfb799f37af1 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.4s, v18.4s, v19.4s}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 5f3f044e0557fe3a v17.d[0] (xor, xfer vecreg #1)
+ 92057a7b6e276a91 v17.d[1] (xor, xfer vecreg #1)
+ 81c01322fd94c102 v18.d[0] (xor, xfer vecreg #2)
+ c675fd3b2e54d294 v18.d[1] (xor, xfer vecreg #2)
+ 37d30753de56980e v19.d[0] (xor, xfer vecreg #3)
+ 949de8f84743f96e v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.4s, v18.4s, v19.4s}, [x5], #48 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 661e1d9f2bc0c057 v17.d[0] (xor, xfer vecreg #1)
+ 039ebfda61790d84 v17.d[1] (xor, xfer vecreg #1)
+ 07cbb91bf3e7a1b3 v18.d[0] (xor, xfer vecreg #2)
+ 3847e0fc82b8d583 v18.d[1] (xor, xfer vecreg #2)
+ 3463d989546f7e73 v19.d[0] (xor, xfer vecreg #3)
+ 7fe45409fb8ca46f v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 48 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.4s, v18.4s, v19.4s}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ cf296a6525c01083 v17.d[0] (xor, xfer vecreg #1)
+ 98dc96d2d9c25a46 v17.d[1] (xor, xfer vecreg #1)
+ ab13c34d4cf69e90 v18.d[0] (xor, xfer vecreg #2)
+ 8dccbec63a7a672b v18.d[1] (xor, xfer vecreg #2)
+ 1d151b788b8145f6 v19.d[0] (xor, xfer vecreg #3)
+ 2c2be1b65eccb5e3 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 418b91744a19088f v17.d[0] (xor, xfer vecreg #1)
+ e14144d449d9bbf8 v17.d[1] (xor, xfer vecreg #1)
+ 43920150776b8195 v18.d[0] (xor, xfer vecreg #2)
+ 82c6cd849580687e v18.d[1] (xor, xfer vecreg #2)
+ 9756ff411133e423 v19.d[0] (xor, xfer vecreg #3)
+ b70a8ff557184bb9 v19.d[1] (xor, xfer vecreg #3)
+ 7f0b98d4e0538171 v20.d[0] (xor, xfer vecreg #3)
+ 54f64a56f09cd945 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], #64 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 6f796040542d7a34 v17.d[0] (xor, xfer vecreg #1)
+ 299df537bfea99c3 v17.d[1] (xor, xfer vecreg #1)
+ 6494b8e08966bf66 v18.d[0] (xor, xfer vecreg #2)
+ a6fa845f7e2c2042 v18.d[1] (xor, xfer vecreg #2)
+ c7b28a1fd998e719 v19.d[0] (xor, xfer vecreg #3)
+ cb744435650ce081 v19.d[1] (xor, xfer vecreg #3)
+ 9b2a33c88b5e03d1 v20.d[0] (xor, xfer vecreg #3)
+ c36f5373e970c157 v20.d[1] (xor, xfer vecreg #3)
+ 64 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 71b3bccb5d65e38a v17.d[0] (xor, xfer vecreg #1)
+ 509149fcba51c799 v17.d[1] (xor, xfer vecreg #1)
+ f25e04aae5dd636e v18.d[0] (xor, xfer vecreg #2)
+ 19a023b37adcbe06 v18.d[1] (xor, xfer vecreg #2)
+ d30136b9145e6dca v19.d[0] (xor, xfer vecreg #3)
+ a9b972f2c44b0914 v19.d[1] (xor, xfer vecreg #3)
+ 6786a1a5aa5ceaf8 v20.d[0] (xor, xfer vecreg #3)
+ 648f0c9148899821 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.2s, v20.2s}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ da721f01b3bf05e0 v19.d[0] (xor, xfer vecreg #3)
+ 3c74cfb59660b7fe v19.d[1] (xor, xfer vecreg #3)
+ cc2a448875119958 v20.d[0] (xor, xfer vecreg #3)
+ ec0c29fc41041551 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.2s, v20.2s}, [x5], #16 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 768907df1d0e2c3e v19.d[0] (xor, xfer vecreg #3)
+ b38b04d438cf88d3 v19.d[1] (xor, xfer vecreg #3)
+ ce9a188e03384824 v20.d[0] (xor, xfer vecreg #3)
+ 7fe4df077e4f80c0 v20.d[1] (xor, xfer vecreg #3)
+ 16 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.2s, v20.2s}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ d7c18939c940c40d v19.d[0] (xor, xfer vecreg #3)
+ a7995fd84bbd2f21 v19.d[1] (xor, xfer vecreg #3)
+ 3613b91d6f4f0502 v20.d[0] (xor, xfer vecreg #3)
+ 75a10f9574e87725 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.2s, v18.2s, v19.2s}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 92d0a4174e77f3fd v17.d[0] (xor, xfer vecreg #1)
+ eef794d6e9d96db7 v17.d[1] (xor, xfer vecreg #1)
+ ae05e29e0da5892b v18.d[0] (xor, xfer vecreg #2)
+ e7db1414f501c8fa v18.d[1] (xor, xfer vecreg #2)
+ 86da157ff10755b1 v19.d[0] (xor, xfer vecreg #3)
+ 5c94c1d4555fd03b v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.2s, v18.2s, v19.2s}, [x5], #24 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ d58ab249bc41be6e v17.d[0] (xor, xfer vecreg #1)
+ 56aba35a8bb5a742 v17.d[1] (xor, xfer vecreg #1)
+ 426a83705f463d99 v18.d[0] (xor, xfer vecreg #2)
+ ab90e3c474f9dc5e v18.d[1] (xor, xfer vecreg #2)
+ cdc96060dbe00dcc v19.d[0] (xor, xfer vecreg #3)
+ 156e11ddd9e89075 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 24 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.2s, v18.2s, v19.2s}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ fa839b01d2564d7f v17.d[0] (xor, xfer vecreg #1)
+ bad65642209037c4 v17.d[1] (xor, xfer vecreg #1)
+ bed8f8263e4b988a v18.d[0] (xor, xfer vecreg #2)
+ 52aaac772bbffd38 v18.d[1] (xor, xfer vecreg #2)
+ 808b100b665bab61 v19.d[0] (xor, xfer vecreg #3)
+ 171d31075c8d9123 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 9d556e9c0ab9cc05 v17.d[0] (xor, xfer vecreg #1)
+ 606e92a42b9f4193 v17.d[1] (xor, xfer vecreg #1)
+ 33e913c342c87eca v18.d[0] (xor, xfer vecreg #2)
+ 201f54409e864ddc v18.d[1] (xor, xfer vecreg #2)
+ 115ff4ccaa5164b0 v19.d[0] (xor, xfer vecreg #3)
+ a69306666081f999 v19.d[1] (xor, xfer vecreg #3)
+ 1a6fe3559f0662cb v20.d[0] (xor, xfer vecreg #3)
+ 7aa36977d0619de7 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], #32 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 8c5bed1c38ac972f v17.d[0] (xor, xfer vecreg #1)
+ 8a663a923015e902 v17.d[1] (xor, xfer vecreg #1)
+ ad7575c73b9ab749 v18.d[0] (xor, xfer vecreg #2)
+ 58e1be355282f19e v18.d[1] (xor, xfer vecreg #2)
+ c618d1dc5415ecca v19.d[0] (xor, xfer vecreg #3)
+ 06c6730d6cf9ea2c v19.d[1] (xor, xfer vecreg #3)
+ 4cc78c068483c8fc v20.d[0] (xor, xfer vecreg #3)
+ 5a2b5abf1b896d07 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 754e1619085014a8 v17.d[0] (xor, xfer vecreg #1)
+ 7eb13321b3275465 v17.d[1] (xor, xfer vecreg #1)
+ 9c056b36cba1505c v18.d[0] (xor, xfer vecreg #2)
+ 40e6cf68cae80ed3 v18.d[1] (xor, xfer vecreg #2)
+ fe439e9e5ef176b3 v19.d[0] (xor, xfer vecreg #3)
+ 7ba85d1101288a2f v19.d[1] (xor, xfer vecreg #3)
+ 5b44a445e9b17ec2 v20.d[0] (xor, xfer vecreg #3)
+ 35501e013836a115 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.8h, v20.8h}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 8785dff6a4fcefb2 v19.d[0] (xor, xfer vecreg #3)
+ 8e0da735b428a6b8 v19.d[1] (xor, xfer vecreg #3)
+ d4a3e39fa21e298d v20.d[0] (xor, xfer vecreg #3)
+ 9465ba749ee9a285 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.8h, v20.8h}, [x5], #32 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ e3a4a44af15b7cb7 v19.d[0] (xor, xfer vecreg #3)
+ ae9fa0c9a9a817fa v19.d[1] (xor, xfer vecreg #3)
+ 2a3838ebdb54a471 v20.d[0] (xor, xfer vecreg #3)
+ 04d0eb97d0778ed7 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.8h, v20.8h}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 774547e67032cff8 v19.d[0] (xor, xfer vecreg #3)
+ 9dfb70976b442280 v19.d[1] (xor, xfer vecreg #3)
+ 2478db6f6efa84f9 v20.d[0] (xor, xfer vecreg #3)
+ c80b14fc556d6615 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.8h, v18.8h, v19.8h}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 025fb3c391ea1908 v17.d[0] (xor, xfer vecreg #1)
+ 91fc0bf089f56799 v17.d[1] (xor, xfer vecreg #1)
+ aff7bef902c7e941 v18.d[0] (xor, xfer vecreg #2)
+ 9daf694f8d1ee193 v18.d[1] (xor, xfer vecreg #2)
+ 9db61d82d87c98c1 v19.d[0] (xor, xfer vecreg #3)
+ 6d027cd52d6881ed v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.8h, v18.8h, v19.8h}, [x5], #48 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 69a16bf0a2e07127 v17.d[0] (xor, xfer vecreg #1)
+ 4dc61a0b08b1e102 v17.d[1] (xor, xfer vecreg #1)
+ 6442c198879a268f v18.d[0] (xor, xfer vecreg #2)
+ 4a32669499cbd5df v18.d[1] (xor, xfer vecreg #2)
+ daec736872034bec v19.d[0] (xor, xfer vecreg #3)
+ 351b1ce40187a3e8 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 48 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.8h, v18.8h, v19.8h}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 9a36bc37d521c800 v17.d[0] (xor, xfer vecreg #1)
+ fb45f3420cfc2c22 v17.d[1] (xor, xfer vecreg #1)
+ cd4393b9770f3df2 v18.d[0] (xor, xfer vecreg #2)
+ 37a41ddd98f19c5f v18.d[1] (xor, xfer vecreg #2)
+ faa3489ed6b86717 v19.d[0] (xor, xfer vecreg #3)
+ 9d29ed86e409cd84 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ c805b38ce43e3f03 v17.d[0] (xor, xfer vecreg #1)
+ 405da7509ba32da6 v17.d[1] (xor, xfer vecreg #1)
+ 6f7df38d5a7cb85a v18.d[0] (xor, xfer vecreg #2)
+ 63121b8a5a7f4886 v18.d[1] (xor, xfer vecreg #2)
+ 0bc8a0edec81550c v19.d[0] (xor, xfer vecreg #3)
+ 36f4e17d66c18124 v19.d[1] (xor, xfer vecreg #3)
+ c4efedd71a045b87 v20.d[0] (xor, xfer vecreg #3)
+ ba9f499cd2887b06 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], #64 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0bf8ff6097e992ad v17.d[0] (xor, xfer vecreg #1)
+ a8b26ebfa8c72984 v17.d[1] (xor, xfer vecreg #1)
+ 7ee7774d45a5ef27 v18.d[0] (xor, xfer vecreg #2)
+ e890c3a0f679e2b4 v18.d[1] (xor, xfer vecreg #2)
+ 49ab0e6956d5f41e v19.d[0] (xor, xfer vecreg #3)
+ db486596f529dc78 v19.d[1] (xor, xfer vecreg #3)
+ 5c0ca83019ae95d4 v20.d[0] (xor, xfer vecreg #3)
+ e18170cbdbfb7e84 v20.d[1] (xor, xfer vecreg #3)
+ 64 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 448e1c3878dbe686 v17.d[0] (xor, xfer vecreg #1)
+ 2b2005cc983a0b1f v17.d[1] (xor, xfer vecreg #1)
+ 101bb1443929c8cb v18.d[0] (xor, xfer vecreg #2)
+ 9f7e2bc1755cd4d2 v18.d[1] (xor, xfer vecreg #2)
+ 53c68ee3f5025bb1 v19.d[0] (xor, xfer vecreg #3)
+ 07597277bf09c68a v19.d[1] (xor, xfer vecreg #3)
+ 66313ceaa740545c v20.d[0] (xor, xfer vecreg #3)
+ be0ddc093a918427 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.4h, v20.4h}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ fff92f13a2a2fae3 v19.d[0] (xor, xfer vecreg #3)
+ f6fe3355021a1e97 v19.d[1] (xor, xfer vecreg #3)
+ 9c65f13158aa046d v20.d[0] (xor, xfer vecreg #3)
+ 1865f2a483581800 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.4h, v20.4h}, [x5], #16 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 7780c486939f2c5f v19.d[0] (xor, xfer vecreg #3)
+ d858407d91938114 v19.d[1] (xor, xfer vecreg #3)
+ 032247250e058e7d v20.d[0] (xor, xfer vecreg #3)
+ 433c8ad49b2ae1f3 v20.d[1] (xor, xfer vecreg #3)
+ 16 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.4h, v20.4h}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ fe9be72a18d40e68 v19.d[0] (xor, xfer vecreg #3)
+ ffd279f2db3441f2 v19.d[1] (xor, xfer vecreg #3)
+ 3257f75a92508874 v20.d[0] (xor, xfer vecreg #3)
+ 9821a5eeb3f1bec4 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.4h, v18.4h, v19.4h}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 932e037d1c2e3371 v17.d[0] (xor, xfer vecreg #1)
+ 190bbb10e7bdb68a v17.d[1] (xor, xfer vecreg #1)
+ d32690ac5e2a2d80 v18.d[0] (xor, xfer vecreg #2)
+ 053e1fd649ff2e63 v18.d[1] (xor, xfer vecreg #2)
+ 5e8494ada571ba10 v19.d[0] (xor, xfer vecreg #3)
+ af60c2c763308483 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.4h, v18.4h, v19.4h}, [x5], #24 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 74c266926d5d28f5 v17.d[0] (xor, xfer vecreg #1)
+ ed02a09d77a481bd v17.d[1] (xor, xfer vecreg #1)
+ 211a02fcdaced192 v18.d[0] (xor, xfer vecreg #2)
+ 61f2d0aba27d9f4b v18.d[1] (xor, xfer vecreg #2)
+ 34602a19f1c2e2c8 v19.d[0] (xor, xfer vecreg #3)
+ 2bf60011adbc6d1d v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 24 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.4h, v18.4h, v19.4h}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 45b13b0979a3125d v17.d[0] (xor, xfer vecreg #1)
+ 859932f642312bcf v17.d[1] (xor, xfer vecreg #1)
+ 7b14f162da08f7bb v18.d[0] (xor, xfer vecreg #2)
+ 673484ea7c71a591 v18.d[1] (xor, xfer vecreg #2)
+ ee4f810f04ac7ef2 v19.d[0] (xor, xfer vecreg #3)
+ b98817e43e0b2014 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ ebdebacb011f992b v17.d[0] (xor, xfer vecreg #1)
+ 25c45531cb9bd716 v17.d[1] (xor, xfer vecreg #1)
+ 65da3e77da827c76 v18.d[0] (xor, xfer vecreg #2)
+ 5cf81ea9590f6389 v18.d[1] (xor, xfer vecreg #2)
+ 7f5bf324d0d55202 v19.d[0] (xor, xfer vecreg #3)
+ 9b0aea549952c2ba v19.d[1] (xor, xfer vecreg #3)
+ 0e5a9e19da6f7972 v20.d[0] (xor, xfer vecreg #3)
+ e951fa1567b3cb45 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], #32 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 46340ebd47462a0c v17.d[0] (xor, xfer vecreg #1)
+ 1377ec609613a9e5 v17.d[1] (xor, xfer vecreg #1)
+ 752be47cdd0121de v18.d[0] (xor, xfer vecreg #2)
+ 843283fabf8afe87 v18.d[1] (xor, xfer vecreg #2)
+ c5323e5456e3474b v19.d[0] (xor, xfer vecreg #3)
+ 16705e7442c47564 v19.d[1] (xor, xfer vecreg #3)
+ 3b895a9b318fb4bc v20.d[0] (xor, xfer vecreg #3)
+ 11c8fef13d522859 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ bdfcf3095d33cdc5 v17.d[0] (xor, xfer vecreg #1)
+ 91a6db9828cfc590 v17.d[1] (xor, xfer vecreg #1)
+ 55617a342ecbb2cb v18.d[0] (xor, xfer vecreg #2)
+ 23d697f2311698df v18.d[1] (xor, xfer vecreg #2)
+ 8b8c11274a8efbaa v19.d[0] (xor, xfer vecreg #3)
+ 6ead5759be965e67 v19.d[1] (xor, xfer vecreg #3)
+ c4368873a6a53147 v20.d[0] (xor, xfer vecreg #3)
+ fb05dc302c1e7243 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
ld1 {v19.16b, v20.16b}, [x5] with x5 = middle_of_block+17, x6=7
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
@@ -12981,10 +16671,10 @@
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 31a43e0a5e012507 v19.d[0] (xor, xfer vecreg #3)
- ffc16831bac1764c v19.d[1] (xor, xfer vecreg #3)
- ba5fe9de7f2bc566 v20.d[0] (xor, xfer vecreg #3)
- 0b988387fa86a920 v20.d[1] (xor, xfer vecreg #3)
+ 1f7b2665ed3558c0 v19.d[0] (xor, xfer vecreg #3)
+ 724036de39a48b2b v19.d[1] (xor, xfer vecreg #3)
+ a6a759e3c5d6335d v20.d[0] (xor, xfer vecreg #3)
+ c85f7c8b2b03a2e0 v20.d[1] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
@@ -13011,13 +16701,43 @@
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 924e806699528e97 v19.d[0] (xor, xfer vecreg #3)
- 2d7a9db532e32205 v19.d[1] (xor, xfer vecreg #3)
- 4d31cf518f003578 v20.d[0] (xor, xfer vecreg #3)
- 4bcfc3df3ae33639 v20.d[1] (xor, xfer vecreg #3)
+ 11c5237916acfb0c v19.d[0] (xor, xfer vecreg #3)
+ 754d64cc749a1707 v19.d[1] (xor, xfer vecreg #3)
+ 5279c6bf1825d70c v20.d[0] (xor, xfer vecreg #3)
+ bb83d0ccd10a43de v20.d[1] (xor, xfer vecreg #3)
32 x5 (sub, base reg)
0 x6 (sub, index reg)
+ld1 {v19.16b, v20.16b}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ ab6f7ca9d0f6f024 v19.d[0] (xor, xfer vecreg #3)
+ ed0bb12e9d543c37 v19.d[1] (xor, xfer vecreg #3)
+ 5a65a5bf7aeaf2f3 v20.d[0] (xor, xfer vecreg #3)
+ 2320845ed3970de6 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
ld1 {v17.16b, v18.16b, v19.16b}, [x5] with x5 = middle_of_block+17, x6=7
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
@@ -13037,17 +16757,437 @@
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 1633997eeefe0b8e v17.d[0] (xor, xfer vecreg #1)
- ef6aaf66a48aef2a v17.d[1] (xor, xfer vecreg #1)
- 8ad7739f4891d97f v18.d[0] (xor, xfer vecreg #2)
- 90fcabef304aad06 v18.d[1] (xor, xfer vecreg #2)
- 29487185424a39eb v19.d[0] (xor, xfer vecreg #3)
- 5aed4c9ff73637b0 v19.d[1] (xor, xfer vecreg #3)
+ 4ec0cf8adad791cb v17.d[0] (xor, xfer vecreg #1)
+ 58b4b27ecd280a91 v17.d[1] (xor, xfer vecreg #1)
+ 48e7619aa81557d3 v18.d[0] (xor, xfer vecreg #2)
+ 85f0959e23dda8e2 v18.d[1] (xor, xfer vecreg #2)
+ 5b596a8acfe8f306 v19.d[0] (xor, xfer vecreg #3)
+ c2808acbe1d86007 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
+ld1 {v17.16b, v18.16b, v19.16b}, [x5], #48 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ d1cd15bdbe8b5450 v17.d[0] (xor, xfer vecreg #1)
+ abecbab8c56dd1ae v17.d[1] (xor, xfer vecreg #1)
+ 722e006eee13ca39 v18.d[0] (xor, xfer vecreg #2)
+ 54431e86c2c82408 v18.d[1] (xor, xfer vecreg #2)
+ 9f4a27bad55fdc65 v19.d[0] (xor, xfer vecreg #3)
+ 09ce31c179ec10a9 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 48 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.16b, v18.16b, v19.16b}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 2d784af355d13327 v17.d[0] (xor, xfer vecreg #1)
+ 5f92014e704bc328 v17.d[1] (xor, xfer vecreg #1)
+ 15633939e0340e0f v18.d[0] (xor, xfer vecreg #2)
+ 5e581f03f74612eb v18.d[1] (xor, xfer vecreg #2)
+ 6bab2ae69700612f v19.d[0] (xor, xfer vecreg #3)
+ d8669ba4d9577a45 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ cae1313072cf6112 v17.d[0] (xor, xfer vecreg #1)
+ 77963fa81fdfece4 v17.d[1] (xor, xfer vecreg #1)
+ 063bb2aee42cae91 v18.d[0] (xor, xfer vecreg #2)
+ de564adcd9bb30d8 v18.d[1] (xor, xfer vecreg #2)
+ 759b74cc664af329 v19.d[0] (xor, xfer vecreg #3)
+ 64007ca9307f3680 v19.d[1] (xor, xfer vecreg #3)
+ e6b6186fabc10675 v20.d[0] (xor, xfer vecreg #3)
+ 056bfe9d1c7551af v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], #64 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ d2a6c5a34ae19504 v17.d[0] (xor, xfer vecreg #1)
+ 3ae037c67028d64f v17.d[1] (xor, xfer vecreg #1)
+ cb215d6ee7f0123e v18.d[0] (xor, xfer vecreg #2)
+ 3766b9473eabdaaf v18.d[1] (xor, xfer vecreg #2)
+ 0f53a6359f79ac08 v19.d[0] (xor, xfer vecreg #3)
+ 14c83f69ddd04e62 v19.d[1] (xor, xfer vecreg #3)
+ 8328fb0bd24b7b9a v20.d[0] (xor, xfer vecreg #3)
+ 43c0bb9b90666582 v20.d[1] (xor, xfer vecreg #3)
+ 64 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 828d11a5fdbcff60 v17.d[0] (xor, xfer vecreg #1)
+ 17e3d34696345ce9 v17.d[1] (xor, xfer vecreg #1)
+ c4b9961fe454825f v18.d[0] (xor, xfer vecreg #2)
+ 7f6001901cde9443 v18.d[1] (xor, xfer vecreg #2)
+ 38b869819866fdcf v19.d[0] (xor, xfer vecreg #3)
+ 77a86fdab7a6d4ee v19.d[1] (xor, xfer vecreg #3)
+ dfd59dd764fd6064 v20.d[0] (xor, xfer vecreg #3)
+ 63653822e4fee1d0 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.8b, v20.8b}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ fc1dddd7e5bfe10f v19.d[0] (xor, xfer vecreg #3)
+ c12e78be34f80ba7 v19.d[1] (xor, xfer vecreg #3)
+ e5f61ca96a95de9a v20.d[0] (xor, xfer vecreg #3)
+ 6e9d730c2588fa9e v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.8b, v20.8b}, [x5], #16 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 1b3582bbcaa739a3 v19.d[0] (xor, xfer vecreg #3)
+ 1e9beb3fc24c901c v19.d[1] (xor, xfer vecreg #3)
+ 1475c920af02af75 v20.d[0] (xor, xfer vecreg #3)
+ 40437eb127b0b165 v20.d[1] (xor, xfer vecreg #3)
+ 16 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.8b, v20.8b}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0f2d8a3059884247 v19.d[0] (xor, xfer vecreg #3)
+ 89519375526ffada v19.d[1] (xor, xfer vecreg #3)
+ c727d4425ed3c4a7 v20.d[0] (xor, xfer vecreg #3)
+ 041f13a9717603f1 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.8b, v18.8b, v19.8b}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 73fece60ca3cd87a v17.d[0] (xor, xfer vecreg #1)
+ 57c5c213abc585d4 v17.d[1] (xor, xfer vecreg #1)
+ cd9a08d6949890aa v18.d[0] (xor, xfer vecreg #2)
+ 4d7fe258fdd971bb v18.d[1] (xor, xfer vecreg #2)
+ 567aac10f39ff4bb v19.d[0] (xor, xfer vecreg #3)
+ 4442537368966f33 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.8b, v18.8b, v19.8b}, [x5], #24 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ c680b482cbde6449 v17.d[0] (xor, xfer vecreg #1)
+ a5d00ef83a8672fe v17.d[1] (xor, xfer vecreg #1)
+ 7fb8f2f5563aee7d v18.d[0] (xor, xfer vecreg #2)
+ 500306a240aed177 v18.d[1] (xor, xfer vecreg #2)
+ 8f3956ba38d6b670 v19.d[0] (xor, xfer vecreg #3)
+ 9364104e88f4117d v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 24 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.8b, v18.8b, v19.8b}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 440ffa30f1cf011a v17.d[0] (xor, xfer vecreg #1)
+ 80a20e134b96c6f1 v17.d[1] (xor, xfer vecreg #1)
+ 6e33b8231d798647 v18.d[0] (xor, xfer vecreg #2)
+ c53c34bf4ca04d78 v18.d[1] (xor, xfer vecreg #2)
+ 701366634ca8991c v19.d[0] (xor, xfer vecreg #3)
+ bca9ad1a37be060b v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ f03cf22b3733c1a7 v17.d[0] (xor, xfer vecreg #1)
+ 2c31a876622aa3ff v17.d[1] (xor, xfer vecreg #1)
+ bae6c2f38392f71a v18.d[0] (xor, xfer vecreg #2)
+ f11f51c2a4e40814 v18.d[1] (xor, xfer vecreg #2)
+ d044fb87e1e405a5 v19.d[0] (xor, xfer vecreg #3)
+ 02060feaf9277131 v19.d[1] (xor, xfer vecreg #3)
+ 15a7f29c9ba882f9 v20.d[0] (xor, xfer vecreg #3)
+ e2bda353bec23773 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], #32 with x5 = middle_of_block+9, x6=9
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 48cb8d5a9e6b1e89 v17.d[0] (xor, xfer vecreg #1)
+ ed6fbd3603752f7e v17.d[1] (xor, xfer vecreg #1)
+ 778088fc360951aa v18.d[0] (xor, xfer vecreg #2)
+ 18a141c0ccad289e v18.d[1] (xor, xfer vecreg #2)
+ 29a803a7d4ded7db v19.d[0] (xor, xfer vecreg #3)
+ a8701ad350637644 v19.d[1] (xor, xfer vecreg #3)
+ f4771924d65c6605 v20.d[0] (xor, xfer vecreg #3)
+ 61f34a142fa7b2ca v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 51675122ed06c6b5 v17.d[0] (xor, xfer vecreg #1)
+ 06513467b3ac8dc1 v17.d[1] (xor, xfer vecreg #1)
+ 2ffadf40e228f9aa v18.d[0] (xor, xfer vecreg #2)
+ 7eb4e7cd4830d06b v18.d[1] (xor, xfer vecreg #2)
+ c1c79b6c433e5fe4 v19.d[0] (xor, xfer vecreg #3)
+ f3d9b1e9c2a73997 v19.d[1] (xor, xfer vecreg #3)
+ ea1896986aa7d867 v20.d[0] (xor, xfer vecreg #3)
+ 6a17d3a0ff61a1e0 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
LD1R (single structure, replicate)
ld1r {v17.2d}, [x5] with x5 = middle_of_block+3, x6=-5
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
@@ -13068,8 +17208,8 @@
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- e1f0837e84b68683 v17.d[0] (xor, xfer vecreg #1)
- e9a6ec8cff7474b3 v17.d[1] (xor, xfer vecreg #1)
+ 78c1efa3ad67ac8e v17.d[0] (xor, xfer vecreg #1)
+ d0029ff8a47b2180 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
@@ -13098,8 +17238,8 @@
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 1bc3341432dc6604 v17.d[0] (xor, xfer vecreg #1)
- 64833826bd0baf0a v17.d[1] (xor, xfer vecreg #1)
+ e7b9db9d6c0fd9bd v17.d[0] (xor, xfer vecreg #1)
+ 54d2d26b4eac4fe4 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
@@ -13128,8 +17268,8 @@
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 0a7c91ae32af6e7d v17.d[0] (xor, xfer vecreg #1)
- 49a6c882c10e8cbf v17.d[1] (xor, xfer vecreg #1)
+ f5ddf6b25ea828c3 v17.d[0] (xor, xfer vecreg #1)
+ 1cf9d1c64c7ce9cc v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
@@ -13158,8 +17298,8 @@
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- a5b299eb90f5790f v17.d[0] (xor, xfer vecreg #1)
- cd4cb5e79a5bb831 v17.d[1] (xor, xfer vecreg #1)
+ 12feefd5cf4ecb5f v17.d[0] (xor, xfer vecreg #1)
+ 3652a32152c90908 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
@@ -13188,8 +17328,8 @@
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- f7482086533cc722 v17.d[0] (xor, xfer vecreg #1)
- f9df7b08611cc893 v17.d[1] (xor, xfer vecreg #1)
+ 486e3a976df4de3b v17.d[0] (xor, xfer vecreg #1)
+ bdc7e3c0bcd7277e v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
@@ -13218,8 +17358,8 @@
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 893ff710eff56429 v17.d[0] (xor, xfer vecreg #1)
- 4995e4da614938d9 v17.d[1] (xor, xfer vecreg #1)
+ fa7ad1186cc62d7d v17.d[0] (xor, xfer vecreg #1)
+ ca73c72be0a4dccc v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
@@ -13248,8 +17388,8 @@
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 1a5fdd6af4164e63 v17.d[0] (xor, xfer vecreg #1)
- 4f9c6e6fb16a7758 v17.d[1] (xor, xfer vecreg #1)
+ 972320ed1b86b9d0 v17.d[0] (xor, xfer vecreg #1)
+ 71326212d7485b2e v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
@@ -13278,8 +17418,8 @@
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 056cdcd43f5f808d v17.d[0] (xor, xfer vecreg #1)
- f8fee69f317551a2 v17.d[1] (xor, xfer vecreg #1)
+ d314ed43d78e2919 v17.d[0] (xor, xfer vecreg #1)
+ 32d35c2717dee6d2 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
@@ -13308,8 +17448,8 @@
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 10cf519ed1f11fe7 v17.d[0] (xor, xfer vecreg #1)
- 771a6a1970e4d881 v17.d[1] (xor, xfer vecreg #1)
+ 1f03c426bc80c750 v17.d[0] (xor, xfer vecreg #1)
+ d226b3eb27b671bc v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
@@ -13338,8 +17478,8 @@
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- f5050c8d137bfa17 v17.d[0] (xor, xfer vecreg #1)
- fa27dad82a7f232c v17.d[1] (xor, xfer vecreg #1)
+ 10f46aad16f386cf v17.d[0] (xor, xfer vecreg #1)
+ 8e1384b617154ab8 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
@@ -13368,8 +17508,8 @@
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- ebe0cc912e044127 v17.d[0] (xor, xfer vecreg #1)
- 93338793978fa5ca v17.d[1] (xor, xfer vecreg #1)
+ 47f268c45d2ebeb5 v17.d[0] (xor, xfer vecreg #1)
+ e86f1be584540513 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
@@ -13398,8 +17538,8 @@
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 237643f435a6133d v17.d[0] (xor, xfer vecreg #1)
- 70afe1246d06cd17 v17.d[1] (xor, xfer vecreg #1)
+ 72e69c376e931872 v17.d[0] (xor, xfer vecreg #1)
+ fcd35f7801ea261f v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
@@ -13428,8 +17568,8 @@
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 800678a83fe98c73 v17.d[0] (xor, xfer vecreg #1)
- 08d54d2ffc97a56e v17.d[1] (xor, xfer vecreg #1)
+ 6973ffa402fd0860 v17.d[0] (xor, xfer vecreg #1)
+ ea95e62e78c2d465 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
@@ -13458,8 +17598,8 @@
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- b1a8115281eeb40c v17.d[0] (xor, xfer vecreg #1)
- 79381a2219ac6f02 v17.d[1] (xor, xfer vecreg #1)
+ bc879d96fd1e0aa0 v17.d[0] (xor, xfer vecreg #1)
+ 9eb30c0df4fd9aa7 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
@@ -13488,8 +17628,8 @@
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 6d94b259250c504b v17.d[0] (xor, xfer vecreg #1)
- d9988551a7caf1ed v17.d[1] (xor, xfer vecreg #1)
+ 18aa71c4f9ee72d3 v17.d[0] (xor, xfer vecreg #1)
+ 401c86b4d6d2aa47 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
@@ -13518,8 +17658,8 @@
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 5ccf8332a7b6af5e v17.d[0] (xor, xfer vecreg #1)
- 3660a5744f0f298f v17.d[1] (xor, xfer vecreg #1)
+ 5d7c1e42d935b2dc v17.d[0] (xor, xfer vecreg #1)
+ 9453ab1510eec6f0 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
@@ -13548,8 +17688,8 @@
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- f089b2feb2543ba0 v17.d[0] (xor, xfer vecreg #1)
- f7f5f85088bff4cb v17.d[1] (xor, xfer vecreg #1)
+ 21bb7b3e05fd59b8 v17.d[0] (xor, xfer vecreg #1)
+ a5498aed344a3637 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
@@ -13578,8 +17718,8 @@
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 330bb577859e83d6 v17.d[0] (xor, xfer vecreg #1)
- c6c8a3b82ed11c5c v17.d[1] (xor, xfer vecreg #1)
+ f6e0d66273639291 v17.d[0] (xor, xfer vecreg #1)
+ fd525d30765ccb9a v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
@@ -13608,8 +17748,8 @@
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- f68a070e043e28c1 v17.d[0] (xor, xfer vecreg #1)
- 07227f20e7c21d0a v17.d[1] (xor, xfer vecreg #1)
+ d1a290bae16e030a v17.d[0] (xor, xfer vecreg #1)
+ 2c7011c424ad5e97 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
@@ -13638,8 +17778,8 @@
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 5d921db2ee29bd8f v17.d[0] (xor, xfer vecreg #1)
- 4910338fd690680b v17.d[1] (xor, xfer vecreg #1)
+ dd8de5f1889b29d1 v17.d[0] (xor, xfer vecreg #1)
+ f95240fd45e9c844 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
@@ -13668,8 +17808,8 @@
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- d66c4e76b0aabf7c v17.d[0] (xor, xfer vecreg #1)
- 1884040a48fe4126 v17.d[1] (xor, xfer vecreg #1)
+ f5757c6da3ee4b78 v17.d[0] (xor, xfer vecreg #1)
+ 43cfa565c4402470 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
@@ -13698,8 +17838,8 @@
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 7748963dcf2b9583 v17.d[0] (xor, xfer vecreg #1)
- e0d8759968ed2c3a v17.d[1] (xor, xfer vecreg #1)
+ 333e06ab82905a95 v17.d[0] (xor, xfer vecreg #1)
+ a9f1771e9e33de90 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
@@ -13728,8 +17868,8 @@
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 5abea78a1d55be57 v17.d[0] (xor, xfer vecreg #1)
- 39ca974096dcf130 v17.d[1] (xor, xfer vecreg #1)
+ 28a89ff642e4eff2 v17.d[0] (xor, xfer vecreg #1)
+ 5acb3fabbcf5b850 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
@@ -13758,8 +17898,8 @@
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 3ec4c291eadf5671 v17.d[0] (xor, xfer vecreg #1)
- aac08a760388888a v17.d[1] (xor, xfer vecreg #1)
+ 7abcdfc010a86347 v17.d[0] (xor, xfer vecreg #1)
+ 2cd02031a0db2c1c v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
@@ -13770,8 +17910,7929 @@
0 x6 (sub, index reg)
LD2R (single structure, replicate)
+ld2r {v17.2d , v18.2d }, [x5] with x5 = middle_of_block+3, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 6e4de75203b54027 v17.d[0] (xor, xfer vecreg #1)
+ 69343983099fe2b6 v17.d[1] (xor, xfer vecreg #1)
+ 7dc631c5319c8bcc v18.d[0] (xor, xfer vecreg #2)
+ 2c6ba8893227492c v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2r {v18.1d , v19.1d }, [x5] with x5 = middle_of_block+3, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 8cba82b58d898167 v18.d[0] (xor, xfer vecreg #2)
+ 333dd539bf3527e8 v18.d[1] (xor, xfer vecreg #2)
+ f41e26dbeae071fd v19.d[0] (xor, xfer vecreg #3)
+ cbef8063a33e5cfa v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2r {v19.4s , v20.4s }, [x5] with x5 = middle_of_block+3, x6=-3
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 809448c91f486078 v19.d[0] (xor, xfer vecreg #3)
+ 92b62728b73ae08a v19.d[1] (xor, xfer vecreg #3)
+ 0b2aa7efd5e57b77 v20.d[0] (xor, xfer vecreg #3)
+ 98f56f60c8844445 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2r {v17.2s , v18.2s }, [x5] with x5 = middle_of_block+3, x6=-2
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 631deaf081c65f94 v17.d[0] (xor, xfer vecreg #1)
+ 2cce48b020c6f178 v17.d[1] (xor, xfer vecreg #1)
+ 09946513af1bd9c0 v18.d[0] (xor, xfer vecreg #2)
+ bf009dbc1754f4fa v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2r {v18.8h , v19.8h }, [x5] with x5 = middle_of_block+3, x6=-1
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 24bb867fbebed565 v18.d[0] (xor, xfer vecreg #2)
+ cbed45a576e028d6 v18.d[1] (xor, xfer vecreg #2)
+ 6b096748a7e38e88 v19.d[0] (xor, xfer vecreg #3)
+ 67e6fc6fc2fb99e2 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2r {v19.4h , v20.4h }, [x5] with x5 = middle_of_block+3, x6=1
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ ea558ff617e37459 v19.d[0] (xor, xfer vecreg #3)
+ b0a0493576b1de6e v19.d[1] (xor, xfer vecreg #3)
+ dcdcea9bff1baf1d v20.d[0] (xor, xfer vecreg #3)
+ 3915f9c0ec730979 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2r {v17.16b, v18.16b}, [x5] with x5 = middle_of_block+3, x6=2
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ d006096087133535 v17.d[0] (xor, xfer vecreg #1)
+ 8ca2f8fa03cb3e44 v17.d[1] (xor, xfer vecreg #1)
+ 7e4d71611c606229 v18.d[0] (xor, xfer vecreg #2)
+ a06268667ad96dce v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2r {v18.8b , v19.8b }, [x5] with x5 = middle_of_block+3, x6=3
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 3d5318724b24a49d v18.d[0] (xor, xfer vecreg #2)
+ 5aadca434b92ff0b v18.d[1] (xor, xfer vecreg #2)
+ f9ac510f26bdee7d v19.d[0] (xor, xfer vecreg #3)
+ d7711062d5102de1 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2r {v19.2d , v20.2d }, [x5], #16 with x5 = middle_of_block+3, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 1f413b3833665d37 v19.d[0] (xor, xfer vecreg #3)
+ 00f89a19ee1fb943 v19.d[1] (xor, xfer vecreg #3)
+ d97d77eca8f044de v20.d[0] (xor, xfer vecreg #3)
+ b2f5bb69f462f8f1 v20.d[1] (xor, xfer vecreg #3)
+ 16 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2r {v17.1d , v18.1d }, [x5], #16 with x5 = middle_of_block+3, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 08493dd1fa363bd9 v17.d[0] (xor, xfer vecreg #1)
+ 7dcb7fadf6855f88 v17.d[1] (xor, xfer vecreg #1)
+ 5090a8afe744662a v18.d[0] (xor, xfer vecreg #2)
+ a8d8718767f27d48 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 16 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2r {v18.4s , v19.4s }, [x5], #8 with x5 = middle_of_block+3, x6=-3
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 248adef2375d25a5 v18.d[0] (xor, xfer vecreg #2)
+ dfb0b3726220cd67 v18.d[1] (xor, xfer vecreg #2)
+ 22b44be65a17530a v19.d[0] (xor, xfer vecreg #3)
+ f2cb79bcafa4a136 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 8 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2r {v19.2s , v20.2s }, [x5], #8 with x5 = middle_of_block+3, x6=-2
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 7114920c1fcc7fa2 v19.d[0] (xor, xfer vecreg #3)
+ 302107652037825a v19.d[1] (xor, xfer vecreg #3)
+ 51007297e3ec06c8 v20.d[0] (xor, xfer vecreg #3)
+ c5d6e9c2c47b9be8 v20.d[1] (xor, xfer vecreg #3)
+ 8 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2r {v17.8h , v18.8h }, [x5], #4 with x5 = middle_of_block+3, x6=-1
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 97d3b0cba7a884c5 v17.d[0] (xor, xfer vecreg #1)
+ d1976d855cf6a479 v17.d[1] (xor, xfer vecreg #1)
+ 93448a10aea9d137 v18.d[0] (xor, xfer vecreg #2)
+ b1ba2047c58d13c1 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 4 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2r {v18.4h , v19.4h }, [x5], #4 with x5 = middle_of_block+3, x6=1
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 79c6d3c2997837e4 v18.d[0] (xor, xfer vecreg #2)
+ e7f47c2f42540b4d v18.d[1] (xor, xfer vecreg #2)
+ e71f5dcd379f40ba v19.d[0] (xor, xfer vecreg #3)
+ a241767b4c3fc9a0 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 4 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2r {v19.16b, v20.16b}, [x5], #2 with x5 = middle_of_block+3, x6=2
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ ce621fb4b93373b6 v19.d[0] (xor, xfer vecreg #3)
+ 96b584fd5dba9e07 v19.d[1] (xor, xfer vecreg #3)
+ 20b63611f3b1c299 v20.d[0] (xor, xfer vecreg #3)
+ 70fd2a6ada7fdd99 v20.d[1] (xor, xfer vecreg #3)
+ 2 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2r {v17.8b , v18.8b }, [x5], #2 with x5 = middle_of_block+3, x6=3
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 213461fd8902fd05 v17.d[0] (xor, xfer vecreg #1)
+ fdc67bf38151899f v17.d[1] (xor, xfer vecreg #1)
+ 0e47146603b9f595 v18.d[0] (xor, xfer vecreg #2)
+ 182722d442955a56 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 2 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2r {v18.2d , v19.2d }, [x5], x6 with x5 = middle_of_block+3, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ b6bb43fcb441679e v18.d[0] (xor, xfer vecreg #2)
+ 0125831577e7ecab v18.d[1] (xor, xfer vecreg #2)
+ 2a5ee43c264d28e4 v19.d[0] (xor, xfer vecreg #3)
+ 69b71e980148350a v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2r {v19.1d , v20.1d }, [x5], x6 with x5 = middle_of_block+3, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ b93532be132f6752 v19.d[0] (xor, xfer vecreg #3)
+ b031dbef4f59305e v19.d[1] (xor, xfer vecreg #3)
+ bbd7c04e69baff2e v20.d[0] (xor, xfer vecreg #3)
+ a89e0657f819d026 v20.d[1] (xor, xfer vecreg #3)
+ -4 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2r {v17.4s , v18.4s }, [x5], x6 with x5 = middle_of_block+3, x6=-3
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 3784bc3685159dc7 v17.d[0] (xor, xfer vecreg #1)
+ cb5dcd6fee16eee3 v17.d[1] (xor, xfer vecreg #1)
+ bd31b3ae329e1f43 v18.d[0] (xor, xfer vecreg #2)
+ 94cec3f017202a8b v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -3 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2r {v18.2s , v19.2s }, [x5], x6 with x5 = middle_of_block+3, x6=-2
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 2c58144998e36da5 v18.d[0] (xor, xfer vecreg #2)
+ 3bf24cdd065aa990 v18.d[1] (xor, xfer vecreg #2)
+ 4f6e7abf02ad896a v19.d[0] (xor, xfer vecreg #3)
+ 8b41118d67ab9117 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -2 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2r {v19.8h , v20.8h }, [x5], x6 with x5 = middle_of_block+3, x6=-1
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 6c7875fee654dc37 v19.d[0] (xor, xfer vecreg #3)
+ dd364b4847682a5c v19.d[1] (xor, xfer vecreg #3)
+ 4baedbd782c4ff95 v20.d[0] (xor, xfer vecreg #3)
+ a636aad12d996815 v20.d[1] (xor, xfer vecreg #3)
+ -1 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2r {v17.4h , v18.4h }, [x5], x6 with x5 = middle_of_block+3, x6=1
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ baea6010762e53b4 v17.d[0] (xor, xfer vecreg #1)
+ 0ca09c63200ace9f v17.d[1] (xor, xfer vecreg #1)
+ afc24dd5be81f8dd v18.d[0] (xor, xfer vecreg #2)
+ 6ecc11820b1eea03 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 1 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2r {v18.16b, v19.16b}, [x5], x6 with x5 = middle_of_block+3, x6=2
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 513555e6994d649a v18.d[0] (xor, xfer vecreg #2)
+ c3f2e35d9df01026 v18.d[1] (xor, xfer vecreg #2)
+ d714ea6439703719 v19.d[0] (xor, xfer vecreg #3)
+ 118139b248856bf5 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 2 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2r {v19.8b , v20.8b }, [x5], x6 with x5 = middle_of_block+3, x6=3
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 67efcfe941317496 v19.d[0] (xor, xfer vecreg #3)
+ 8db024b263f84a5a v19.d[1] (xor, xfer vecreg #3)
+ ee6cbf42c93263aa v20.d[0] (xor, xfer vecreg #3)
+ 414cb15de82b0914 v20.d[1] (xor, xfer vecreg #3)
+ 3 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+LD3R (single structure, replicate)
+ld3r {v17.2d , v18.2d , v19.2d }, [x5] with x5 = middle_of_block+3, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 57193325a146cdd4 v17.d[0] (xor, xfer vecreg #1)
+ 702a2ffe4edcdf4c v17.d[1] (xor, xfer vecreg #1)
+ 175087ebb597fe2a v18.d[0] (xor, xfer vecreg #2)
+ ebba02b33822f0ce v18.d[1] (xor, xfer vecreg #2)
+ 35fdc98502b00972 v19.d[0] (xor, xfer vecreg #3)
+ 86a3d76abf65709d v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3r {v18.1d , v19.1d , v20.1d }, [x5] with x5 = middle_of_block+3, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 560843da0bef0cea v18.d[0] (xor, xfer vecreg #2)
+ b587992df7863cb3 v18.d[1] (xor, xfer vecreg #2)
+ 97f1ba96b79cceeb v19.d[0] (xor, xfer vecreg #3)
+ f35041798733e425 v19.d[1] (xor, xfer vecreg #3)
+ 1dad02b6c736fbc7 v20.d[0] (xor, xfer vecreg #3)
+ 166cf42adbfd5d1f v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3r {v17.4s , v18.4s , v19.4s }, [x5] with x5 = middle_of_block+3, x6=-3
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 75d17e6471b81b36 v17.d[0] (xor, xfer vecreg #1)
+ 8b9fbcc042a2e6c0 v17.d[1] (xor, xfer vecreg #1)
+ 12b9ce73dced6fb4 v18.d[0] (xor, xfer vecreg #2)
+ a9c6c24f88152246 v18.d[1] (xor, xfer vecreg #2)
+ cf0fba22cac44348 v19.d[0] (xor, xfer vecreg #3)
+ 586b39a2e5a814e9 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3r {v18.2s , v19.2s , v20.2s }, [x5] with x5 = middle_of_block+3, x6=-2
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 9e2d7313ea9eb1f2 v18.d[0] (xor, xfer vecreg #2)
+ 0aa99d731f6b8d30 v18.d[1] (xor, xfer vecreg #2)
+ d701483fa74bef5b v19.d[0] (xor, xfer vecreg #3)
+ 1c5f41e344fd25e1 v19.d[1] (xor, xfer vecreg #3)
+ 1b2513bb408c40cb v20.d[0] (xor, xfer vecreg #3)
+ 45b3711280953114 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3r {v17.8h , v18.8h , v19.8h }, [x5] with x5 = middle_of_block+3, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 527cda24e5a617d3 v17.d[0] (xor, xfer vecreg #1)
+ 206eb6a73ba52443 v17.d[1] (xor, xfer vecreg #1)
+ 6d6e279031465866 v18.d[0] (xor, xfer vecreg #2)
+ 360e35b657ee27d0 v18.d[1] (xor, xfer vecreg #2)
+ 0b82783e6b9d197c v19.d[0] (xor, xfer vecreg #3)
+ 2db9f90d8f73f601 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3r {v18.4h , v19.4h , v20.4h }, [x5] with x5 = middle_of_block+3, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 190d5ff27be14404 v18.d[0] (xor, xfer vecreg #2)
+ aa224b83e946cf46 v18.d[1] (xor, xfer vecreg #2)
+ 09b4cf76a33711fa v19.d[0] (xor, xfer vecreg #3)
+ 297e4390bbf4302e v19.d[1] (xor, xfer vecreg #3)
+ bf21393e726f5b40 v20.d[0] (xor, xfer vecreg #3)
+ f1c249b5f592a592 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3r {v17.16b, v18.16b, v19.16b}, [x5] with x5 = middle_of_block+3, x6=-3
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0901b9ec44b0d96e v17.d[0] (xor, xfer vecreg #1)
+ 937fdb594aeb86c7 v17.d[1] (xor, xfer vecreg #1)
+ 35b5573fe82cc322 v18.d[0] (xor, xfer vecreg #2)
+ 81439d2bb55065bc v18.d[1] (xor, xfer vecreg #2)
+ 45be6fb9b46773c0 v19.d[0] (xor, xfer vecreg #3)
+ 3861484632748d4a v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3r {v18.8b , v19.8b , v20.8b }, [x5] with x5 = middle_of_block+3, x6=-2
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 073fc2e0f2c2d708 v18.d[0] (xor, xfer vecreg #2)
+ b693c3ff74b62195 v18.d[1] (xor, xfer vecreg #2)
+ 8d93c2f05afd3fe1 v19.d[0] (xor, xfer vecreg #3)
+ 394d67200bb922ac v19.d[1] (xor, xfer vecreg #3)
+ 715bc502bb86b0b3 v20.d[0] (xor, xfer vecreg #3)
+ 37399bb25c96da38 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3r {v17.2d , v18.2d , v19.2d }, [x5], #24 with x5 = middle_of_block+3, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 01dc0c2fa02185c5 v17.d[0] (xor, xfer vecreg #1)
+ 7246d0c2b63cc243 v17.d[1] (xor, xfer vecreg #1)
+ fa783633fe737f5d v18.d[0] (xor, xfer vecreg #2)
+ 90074f397d46a392 v18.d[1] (xor, xfer vecreg #2)
+ 5d96f0c5b65397a4 v19.d[0] (xor, xfer vecreg #3)
+ 3981b56b99323e77 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 24 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3r {v18.1d , v19.1d , v20.1d }, [x5], #24 with x5 = middle_of_block+3, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 4608c89ab04907aa v18.d[0] (xor, xfer vecreg #2)
+ 4c9c2685e05da4bd v18.d[1] (xor, xfer vecreg #2)
+ 081bf80aff7016f7 v19.d[0] (xor, xfer vecreg #3)
+ 6d6cce3254ec1dfa v19.d[1] (xor, xfer vecreg #3)
+ 6f443fee750ce931 v20.d[0] (xor, xfer vecreg #3)
+ 39b887abd53fefa7 v20.d[1] (xor, xfer vecreg #3)
+ 24 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3r {v17.4s , v18.4s , v19.4s }, [x5], #12 with x5 = middle_of_block+3, x6=-3
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 4f8200d55602c6c6 v17.d[0] (xor, xfer vecreg #1)
+ dffdce62121ee2cf v17.d[1] (xor, xfer vecreg #1)
+ 80e10ad0f9947bea v18.d[0] (xor, xfer vecreg #2)
+ 555d52d476278a7f v18.d[1] (xor, xfer vecreg #2)
+ 33e92c4b07d8c425 v19.d[0] (xor, xfer vecreg #3)
+ 854321bcdbee8d80 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 12 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3r {v18.2s , v19.2s , v20.2s }, [x5], #12 with x5 = middle_of_block+3, x6=-2
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ a1127b756b4577ee v18.d[0] (xor, xfer vecreg #2)
+ 8fdd93b64ed9775e v18.d[1] (xor, xfer vecreg #2)
+ 7b64bdfc7071d468 v19.d[0] (xor, xfer vecreg #3)
+ e37b9767b72d40ba v19.d[1] (xor, xfer vecreg #3)
+ 55fe24d389e6f649 v20.d[0] (xor, xfer vecreg #3)
+ 17de2e3f7f2e057f v20.d[1] (xor, xfer vecreg #3)
+ 12 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3r {v17.8h , v18.8h , v19.8h }, [x5], #6 with x5 = middle_of_block+3, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 146ff15e3d0300f6 v17.d[0] (xor, xfer vecreg #1)
+ 58f57519715bd55a v17.d[1] (xor, xfer vecreg #1)
+ 79799fd8a0d695ef v18.d[0] (xor, xfer vecreg #2)
+ b13a632f6484f240 v18.d[1] (xor, xfer vecreg #2)
+ d9fa84f1a21c9d0f v19.d[0] (xor, xfer vecreg #3)
+ 75276df8cb4d8ccf v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 6 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3r {v18.4h , v19.4h , v20.4h }, [x5], #6 with x5 = middle_of_block+3, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 902f74978296ce48 v18.d[0] (xor, xfer vecreg #2)
+ 9cf62b32ddccba18 v18.d[1] (xor, xfer vecreg #2)
+ 5aecc0225232b9b4 v19.d[0] (xor, xfer vecreg #3)
+ be1ae260531bac8a v19.d[1] (xor, xfer vecreg #3)
+ 145efc5ca77ea861 v20.d[0] (xor, xfer vecreg #3)
+ ef4daf0d7a043b60 v20.d[1] (xor, xfer vecreg #3)
+ 6 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3r {v17.16b, v18.16b, v19.16b}, [x5], #3 with x5 = middle_of_block+3, x6=-3
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ c3e2f8fae3c5d78b v17.d[0] (xor, xfer vecreg #1)
+ 57ecaeba58c4b4d1 v17.d[1] (xor, xfer vecreg #1)
+ 1f6bd6e1f1f50080 v18.d[0] (xor, xfer vecreg #2)
+ 4ac5f1ef2bc3d000 v18.d[1] (xor, xfer vecreg #2)
+ 642cec80f4da0fb5 v19.d[0] (xor, xfer vecreg #3)
+ 253eacc8fe898814 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 3 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3r {v18.8b , v19.8b , v20.8b }, [x5], #3 with x5 = middle_of_block+3, x6=-2
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 7045c00b6a03c5fc v18.d[0] (xor, xfer vecreg #2)
+ 95860d99add48e8a v18.d[1] (xor, xfer vecreg #2)
+ fc18f38bc00b22fb v19.d[0] (xor, xfer vecreg #3)
+ 1be8d0bb4858800b v19.d[1] (xor, xfer vecreg #3)
+ 6c73b3e7364eb24d v20.d[0] (xor, xfer vecreg #3)
+ e3a32bb6e65eb1ea v20.d[1] (xor, xfer vecreg #3)
+ 3 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3r {v17.2d , v18.2d , v19.2d }, [x5], x6 with x5 = middle_of_block+3, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 7ee07e1ff08e6342 v17.d[0] (xor, xfer vecreg #1)
+ 07e3d1dcde9d256e v17.d[1] (xor, xfer vecreg #1)
+ f683eafe678c1363 v18.d[0] (xor, xfer vecreg #2)
+ 9f97b8e5a3b24c73 v18.d[1] (xor, xfer vecreg #2)
+ 92f91a7e673136ed v19.d[0] (xor, xfer vecreg #3)
+ c79d5e8d96801c2e v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3r {v18.1d , v19.1d , v20.1d }, [x5], x6 with x5 = middle_of_block+3, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 7dc9215dbafe1fe2 v18.d[0] (xor, xfer vecreg #2)
+ 9a2f598bdf921256 v18.d[1] (xor, xfer vecreg #2)
+ 9328eab8187cdaf8 v19.d[0] (xor, xfer vecreg #3)
+ 1c878019b782dcdd v19.d[1] (xor, xfer vecreg #3)
+ 1ce5976bbd8ac35c v20.d[0] (xor, xfer vecreg #3)
+ 1382c0dae4df88bd v20.d[1] (xor, xfer vecreg #3)
+ -4 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3r {v17.4s , v18.4s , v19.4s }, [x5], x6 with x5 = middle_of_block+3, x6=-3
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 190ac9035745033c v17.d[0] (xor, xfer vecreg #1)
+ efa956cd91c3f59b v17.d[1] (xor, xfer vecreg #1)
+ a5bae777a1234087 v18.d[0] (xor, xfer vecreg #2)
+ b69133793b6822fc v18.d[1] (xor, xfer vecreg #2)
+ cbf7d18f083c965e v19.d[0] (xor, xfer vecreg #3)
+ 0391ed6401c4eec8 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -3 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3r {v18.2s , v19.2s , v20.2s }, [x5], x6 with x5 = middle_of_block+3, x6=-2
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 05e1bfca872e95df v18.d[0] (xor, xfer vecreg #2)
+ ca8f30a892a6671a v18.d[1] (xor, xfer vecreg #2)
+ 3a87354bb15cda67 v19.d[0] (xor, xfer vecreg #3)
+ e095131ac03be1a0 v19.d[1] (xor, xfer vecreg #3)
+ a26ee91e0381057b v20.d[0] (xor, xfer vecreg #3)
+ 9e8891199426df78 v20.d[1] (xor, xfer vecreg #3)
+ -2 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3r {v17.8h , v18.8h , v19.8h }, [x5], x6 with x5 = middle_of_block+3, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ bd49ed003a6ce16f v17.d[0] (xor, xfer vecreg #1)
+ 1768c877333afbb5 v17.d[1] (xor, xfer vecreg #1)
+ a6e1d25080eb02c5 v18.d[0] (xor, xfer vecreg #2)
+ 3fca4a54a4befa20 v18.d[1] (xor, xfer vecreg #2)
+ 4c8a47fd816716f2 v19.d[0] (xor, xfer vecreg #3)
+ 8a3ef71f1bf8e158 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3r {v18.4h , v19.4h , v20.4h }, [x5], x6 with x5 = middle_of_block+3, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 9824b4e5f5864995 v18.d[0] (xor, xfer vecreg #2)
+ 4548b18fe7b0ac77 v18.d[1] (xor, xfer vecreg #2)
+ 8bfeace0acf1e35e v19.d[0] (xor, xfer vecreg #3)
+ 88b3a75d8121aef4 v19.d[1] (xor, xfer vecreg #3)
+ a8cb4f2231fcf587 v20.d[0] (xor, xfer vecreg #3)
+ a456bb1314d3d6bd v20.d[1] (xor, xfer vecreg #3)
+ -4 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3r {v17.16b, v18.16b, v19.16b}, [x5], x6 with x5 = middle_of_block+3, x6=-3
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 11948038eb6ad93b v17.d[0] (xor, xfer vecreg #1)
+ 874d4def07e1020f v17.d[1] (xor, xfer vecreg #1)
+ d44ba9e79b8f51bf v18.d[0] (xor, xfer vecreg #2)
+ 9d93f8f52c4716c5 v18.d[1] (xor, xfer vecreg #2)
+ dfb910384c7cc409 v19.d[0] (xor, xfer vecreg #3)
+ 3e0fe8cf77e2df83 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -3 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3r {v18.8b , v19.8b , v20.8b }, [x5], x6 with x5 = middle_of_block+3, x6=-2
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ b960c673da301f50 v18.d[0] (xor, xfer vecreg #2)
+ 2bf8fde2fd4f010d v18.d[1] (xor, xfer vecreg #2)
+ 7ef8356f3884c820 v19.d[0] (xor, xfer vecreg #3)
+ 33815f841cd56479 v19.d[1] (xor, xfer vecreg #3)
+ fee1278033273425 v20.d[0] (xor, xfer vecreg #3)
+ 468c616886858e2a v20.d[1] (xor, xfer vecreg #3)
+ -2 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
LD4R (single structure, replicate)
+ld4r {v17.2d , v18.2d , v19.2d , v20.2d }, [x5] with x5 = middle_of_block+3, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 3dec6888d0fbd8f8 v17.d[0] (xor, xfer vecreg #1)
+ 38399d2a4ff35576 v17.d[1] (xor, xfer vecreg #1)
+ 945bf52d8b3668f2 v18.d[0] (xor, xfer vecreg #2)
+ 0eaa4b41303679a8 v18.d[1] (xor, xfer vecreg #2)
+ da5d57a8121374a9 v19.d[0] (xor, xfer vecreg #3)
+ c34ee3d345ef8191 v19.d[1] (xor, xfer vecreg #3)
+ 7ebcda4b6488fc7a v20.d[0] (xor, xfer vecreg #3)
+ 86f369a89c6c5c88 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4r {v17.1d , v18.1d , v19.1d , v20.1d }, [x5] with x5 = middle_of_block+3, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 5a9dd7b91d2f638f v17.d[0] (xor, xfer vecreg #1)
+ f0d46d8a7797fb4f v17.d[1] (xor, xfer vecreg #1)
+ 516528c8f2e4e10a v18.d[0] (xor, xfer vecreg #2)
+ 9d40333ff425867c v18.d[1] (xor, xfer vecreg #2)
+ 49eae2512834e0c9 v19.d[0] (xor, xfer vecreg #3)
+ 029f582db1f722ce v19.d[1] (xor, xfer vecreg #3)
+ a0eb8b3d0463bdeb v20.d[0] (xor, xfer vecreg #3)
+ a3caa0b80ade2661 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4r {v17.4s , v18.4s , v19.4s , v20.4s }, [x5] with x5 = middle_of_block+3, x6=-3
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 570fa2517339b1c5 v17.d[0] (xor, xfer vecreg #1)
+ bbcb7fe44151a9ba v17.d[1] (xor, xfer vecreg #1)
+ be1501768dbd36fe v18.d[0] (xor, xfer vecreg #2)
+ 6f83204fb41a6adc v18.d[1] (xor, xfer vecreg #2)
+ 1e6a906e20c3d801 v19.d[0] (xor, xfer vecreg #3)
+ 5843c4ce9a7ef2d1 v19.d[1] (xor, xfer vecreg #3)
+ c243fb1f896dea26 v20.d[0] (xor, xfer vecreg #3)
+ ede35f4710e76a4e v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4r {v17.2s , v18.2s , v19.2s , v20.2s }, [x5] with x5 = middle_of_block+3, x6=-2
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 35aa862a7ac642ca v17.d[0] (xor, xfer vecreg #1)
+ cb9094a88d28e3d2 v17.d[1] (xor, xfer vecreg #1)
+ 7e891e8cc5d38e3f v18.d[0] (xor, xfer vecreg #2)
+ bbc07347edd05c64 v18.d[1] (xor, xfer vecreg #2)
+ 6bb19c88cb153c35 v19.d[0] (xor, xfer vecreg #3)
+ 14adb4fa5e270895 v19.d[1] (xor, xfer vecreg #3)
+ 2c4eeb5aaaebe137 v20.d[0] (xor, xfer vecreg #3)
+ dbaf9aa2be7cbf00 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4r {v17.8h , v18.8h , v19.8h , v20.8h }, [x5] with x5 = middle_of_block+3, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 89ae565107adeee8 v17.d[0] (xor, xfer vecreg #1)
+ b9b654ea09984ec0 v17.d[1] (xor, xfer vecreg #1)
+ 0fc9b43972fa6a17 v18.d[0] (xor, xfer vecreg #2)
+ b37f91d7349140fe v18.d[1] (xor, xfer vecreg #2)
+ 91f3df3aca9a86e1 v19.d[0] (xor, xfer vecreg #3)
+ 96f117be1f077235 v19.d[1] (xor, xfer vecreg #3)
+ 754e38eaaea47719 v20.d[0] (xor, xfer vecreg #3)
+ 7e95faf2d851c89f v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4r {v17.4h , v18.4h , v19.4h , v20.4h }, [x5] with x5 = middle_of_block+3, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ c1694eab0a7ea1f8 v17.d[0] (xor, xfer vecreg #1)
+ d96c8c99acf76376 v17.d[1] (xor, xfer vecreg #1)
+ 7cf2d85bd04d5b8e v18.d[0] (xor, xfer vecreg #2)
+ a317dd9b07f2a365 v18.d[1] (xor, xfer vecreg #2)
+ 9549a414a2d5954e v19.d[0] (xor, xfer vecreg #3)
+ 894a93894605376c v19.d[1] (xor, xfer vecreg #3)
+ 94b5093698442938 v20.d[0] (xor, xfer vecreg #3)
+ 0fdd6ec8c50078a8 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4r {v17.16b, v18.16b, v19.16b, v20.16b}, [x5] with x5 = middle_of_block+3, x6=-3
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 7a5751d725c24de7 v17.d[0] (xor, xfer vecreg #1)
+ 7207fdbde67739e9 v17.d[1] (xor, xfer vecreg #1)
+ 086d364dfc40d03b v18.d[0] (xor, xfer vecreg #2)
+ 01d9f2dd245f654f v18.d[1] (xor, xfer vecreg #2)
+ b8cad441f54271b3 v19.d[0] (xor, xfer vecreg #3)
+ fb7905a4d19feb98 v19.d[1] (xor, xfer vecreg #3)
+ 217d79fdd53c1b09 v20.d[0] (xor, xfer vecreg #3)
+ 9292870173b95992 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4r {v17.8b , v18.8b , v19.8b , v20.8b }, [x5] with x5 = middle_of_block+3, x6=-2
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 679f56d75dadaa65 v17.d[0] (xor, xfer vecreg #1)
+ 3a0878fcf5a49bdb v17.d[1] (xor, xfer vecreg #1)
+ 487e577d77324075 v18.d[0] (xor, xfer vecreg #2)
+ 77e792d963297a1e v18.d[1] (xor, xfer vecreg #2)
+ e5959eea367028b9 v19.d[0] (xor, xfer vecreg #3)
+ 8118147b8630cef4 v19.d[1] (xor, xfer vecreg #3)
+ 45168193557dc6a0 v20.d[0] (xor, xfer vecreg #3)
+ 5ef23dc83c0a71f9 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4r {v17.2d , v18.2d , v19.2d , v20.2d }, [x5], #32 with x5 = middle_of_block+3, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 88bfa474c3f0c131 v17.d[0] (xor, xfer vecreg #1)
+ db944a2f9b52b49e v17.d[1] (xor, xfer vecreg #1)
+ c94e1dd11b9895e0 v18.d[0] (xor, xfer vecreg #2)
+ dd817247114369e4 v18.d[1] (xor, xfer vecreg #2)
+ 2ef0cf5895114f19 v19.d[0] (xor, xfer vecreg #3)
+ c876721e7cafbbef v19.d[1] (xor, xfer vecreg #3)
+ 5618da4ae12b465b v20.d[0] (xor, xfer vecreg #3)
+ 238e9a76d3ad9c0b v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4r {v17.1d , v18.1d , v19.1d , v20.1d }, [x5], #32 with x5 = middle_of_block+3, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ dfc69b61e6b60859 v17.d[0] (xor, xfer vecreg #1)
+ 0f04757386cfaca1 v17.d[1] (xor, xfer vecreg #1)
+ b3ac3201c52f5bf8 v18.d[0] (xor, xfer vecreg #2)
+ 57cfb2a120160131 v18.d[1] (xor, xfer vecreg #2)
+ cde371b2e5adf735 v19.d[0] (xor, xfer vecreg #3)
+ 1db55770404aedce v19.d[1] (xor, xfer vecreg #3)
+ 5e248f4068a70ca2 v20.d[0] (xor, xfer vecreg #3)
+ e8902543453acb92 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4r {v17.4s , v18.4s , v19.4s , v20.4s }, [x5], #16 with x5 = middle_of_block+3, x6=-3
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 24461d234ddd5316 v17.d[0] (xor, xfer vecreg #1)
+ 1af219c4a0208c16 v17.d[1] (xor, xfer vecreg #1)
+ 073d4c52453226f4 v18.d[0] (xor, xfer vecreg #2)
+ b5fbe21dcde5a19c v18.d[1] (xor, xfer vecreg #2)
+ 868e4f0d876cf685 v19.d[0] (xor, xfer vecreg #3)
+ 82b622dbe410934f v19.d[1] (xor, xfer vecreg #3)
+ 2be92b2b23b1b64d v20.d[0] (xor, xfer vecreg #3)
+ 31a488fa1595c037 v20.d[1] (xor, xfer vecreg #3)
+ 16 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4r {v17.2s , v18.2s , v19.2s , v20.2s }, [x5], #16 with x5 = middle_of_block+3, x6=-2
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ bf5f9dac3c0f91e9 v17.d[0] (xor, xfer vecreg #1)
+ 77ffa59d8217b567 v17.d[1] (xor, xfer vecreg #1)
+ 55e8b47145432ec8 v18.d[0] (xor, xfer vecreg #2)
+ 616e5c955e59583c v18.d[1] (xor, xfer vecreg #2)
+ b4a49506597180e5 v19.d[0] (xor, xfer vecreg #3)
+ 7dc37c0893f1b597 v19.d[1] (xor, xfer vecreg #3)
+ 83c2e7768c167f43 v20.d[0] (xor, xfer vecreg #3)
+ ce5549d9ff2fa515 v20.d[1] (xor, xfer vecreg #3)
+ 16 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4r {v17.8h , v18.8h , v19.8h , v20.8h }, [x5], #8 with x5 = middle_of_block+3, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 98bce726b8a2b3f1 v17.d[0] (xor, xfer vecreg #1)
+ 860d0135fa1bbaef v17.d[1] (xor, xfer vecreg #1)
+ aaf27951b23edde2 v18.d[0] (xor, xfer vecreg #2)
+ 25067ab2d37f88f2 v18.d[1] (xor, xfer vecreg #2)
+ 727dda8037191bd0 v19.d[0] (xor, xfer vecreg #3)
+ d8cf7999e7061593 v19.d[1] (xor, xfer vecreg #3)
+ 27a846ef14b03098 v20.d[0] (xor, xfer vecreg #3)
+ 5639d150f22787b0 v20.d[1] (xor, xfer vecreg #3)
+ 8 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4r {v17.4h , v18.4h , v19.4h , v20.4h }, [x5], #8 with x5 = middle_of_block+3, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 43a5a1b8094894c5 v17.d[0] (xor, xfer vecreg #1)
+ 939a2819061ed7cf v17.d[1] (xor, xfer vecreg #1)
+ 128b4f4e6c7ddfb3 v18.d[0] (xor, xfer vecreg #2)
+ b865b0543d92a0e0 v18.d[1] (xor, xfer vecreg #2)
+ f630c25655344d77 v19.d[0] (xor, xfer vecreg #3)
+ bfe0a4e3a0c645f2 v19.d[1] (xor, xfer vecreg #3)
+ cc1a58623d75d281 v20.d[0] (xor, xfer vecreg #3)
+ 2fe2c62a8b8b1f20 v20.d[1] (xor, xfer vecreg #3)
+ 8 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4r {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], #4 with x5 = middle_of_block+3, x6=-3
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 4d5b9be73a4c6be6 v17.d[0] (xor, xfer vecreg #1)
+ a8c0c4ae60ecedd7 v17.d[1] (xor, xfer vecreg #1)
+ 1a7cc4dff3fe9fd4 v18.d[0] (xor, xfer vecreg #2)
+ 16fbeb2e6bf38761 v18.d[1] (xor, xfer vecreg #2)
+ 51aca0692d105c93 v19.d[0] (xor, xfer vecreg #3)
+ cafc7911fc0ed802 v19.d[1] (xor, xfer vecreg #3)
+ bc1682e5808c42ee v20.d[0] (xor, xfer vecreg #3)
+ 004e9992d159ebd3 v20.d[1] (xor, xfer vecreg #3)
+ 4 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4r {v17.8b , v18.8b , v19.8b , v20.8b }, [x5], #4 with x5 = middle_of_block+3, x6=-2
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 5c7de6537c708bbe v17.d[0] (xor, xfer vecreg #1)
+ 82761c8834823177 v17.d[1] (xor, xfer vecreg #1)
+ 68f23214d87c0da2 v18.d[0] (xor, xfer vecreg #2)
+ 7954ce7dde60f8bd v18.d[1] (xor, xfer vecreg #2)
+ ead44cc7aed16b35 v19.d[0] (xor, xfer vecreg #3)
+ 05adeea08669be7e v19.d[1] (xor, xfer vecreg #3)
+ 239841f67ce02c68 v20.d[0] (xor, xfer vecreg #3)
+ 2cd7bed608ed5a55 v20.d[1] (xor, xfer vecreg #3)
+ 4 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4r {v17.2d , v18.2d , v19.2d , v20.2d }, [x5], x6 with x5 = middle_of_block+3, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ ecacf6f0c29e76bb v17.d[0] (xor, xfer vecreg #1)
+ 43d1af092592243f v17.d[1] (xor, xfer vecreg #1)
+ b3b79c7e76e9e252 v18.d[0] (xor, xfer vecreg #2)
+ 55fd373f7fa5bc41 v18.d[1] (xor, xfer vecreg #2)
+ 19ccda0f1932baae v19.d[0] (xor, xfer vecreg #3)
+ e5127d0ad64aec8a v19.d[1] (xor, xfer vecreg #3)
+ d76ce6b97b89b337 v20.d[0] (xor, xfer vecreg #3)
+ f3d6d21386a90766 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4r {v17.1d , v18.1d , v19.1d , v20.1d }, [x5], x6 with x5 = middle_of_block+3, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 8553f4d808431cbf v17.d[0] (xor, xfer vecreg #1)
+ 6431a38b2ce4e300 v17.d[1] (xor, xfer vecreg #1)
+ 49b7cfbbe873e61a v18.d[0] (xor, xfer vecreg #2)
+ c6dbd7b161658173 v18.d[1] (xor, xfer vecreg #2)
+ 3567519d3cd48f3d v19.d[0] (xor, xfer vecreg #3)
+ 6fca7be1657a3fdb v19.d[1] (xor, xfer vecreg #3)
+ 1390aea305113b46 v20.d[0] (xor, xfer vecreg #3)
+ e4d4517c97f47552 v20.d[1] (xor, xfer vecreg #3)
+ -4 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4r {v17.4s , v18.4s , v19.4s , v20.4s }, [x5], x6 with x5 = middle_of_block+3, x6=-3
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ ae118b94f835a542 v17.d[0] (xor, xfer vecreg #1)
+ 7642b02ed070bf70 v17.d[1] (xor, xfer vecreg #1)
+ 5505391c408bf047 v18.d[0] (xor, xfer vecreg #2)
+ a174b7668af30b36 v18.d[1] (xor, xfer vecreg #2)
+ 93244b350239b369 v19.d[0] (xor, xfer vecreg #3)
+ 95cca808329aa065 v19.d[1] (xor, xfer vecreg #3)
+ 0873e6ebd01431e4 v20.d[0] (xor, xfer vecreg #3)
+ a9a9198d9726c623 v20.d[1] (xor, xfer vecreg #3)
+ -3 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4r {v17.2s , v18.2s , v19.2s , v20.2s }, [x5], x6 with x5 = middle_of_block+3, x6=-2
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ fd4f6423959cb07c v17.d[0] (xor, xfer vecreg #1)
+ 5a6cddc00ce40e0b v17.d[1] (xor, xfer vecreg #1)
+ 0f28484e37342c92 v18.d[0] (xor, xfer vecreg #2)
+ be9aea91e43f5aa2 v18.d[1] (xor, xfer vecreg #2)
+ 1e3bcc4c28cc93d2 v19.d[0] (xor, xfer vecreg #3)
+ 1cd76a445e99e8a8 v19.d[1] (xor, xfer vecreg #3)
+ 8ade38ca52795efb v20.d[0] (xor, xfer vecreg #3)
+ 77799ebe564191b8 v20.d[1] (xor, xfer vecreg #3)
+ -2 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4r {v17.8h , v18.8h , v19.8h , v20.8h }, [x5], x6 with x5 = middle_of_block+3, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ dedae42bbab86bee v17.d[0] (xor, xfer vecreg #1)
+ fae06a44829a56c9 v17.d[1] (xor, xfer vecreg #1)
+ 8a7b62799e3d40e8 v18.d[0] (xor, xfer vecreg #2)
+ 8b8a5c295fa491e2 v18.d[1] (xor, xfer vecreg #2)
+ 34d8ba65b68bc3c0 v19.d[0] (xor, xfer vecreg #3)
+ d83b8d77a312ebe9 v19.d[1] (xor, xfer vecreg #3)
+ b9df25785d24edc6 v20.d[0] (xor, xfer vecreg #3)
+ 5244cb035c0cf64c v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4r {v17.4h , v18.4h , v19.4h , v20.4h }, [x5], x6 with x5 = middle_of_block+3, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ a5d79dee9888e836 v17.d[0] (xor, xfer vecreg #1)
+ 83c7e9c8f622d136 v17.d[1] (xor, xfer vecreg #1)
+ d0c4ee882ae52c93 v18.d[0] (xor, xfer vecreg #2)
+ 823128bb8a8fa3ea v18.d[1] (xor, xfer vecreg #2)
+ 460a9ee9d2bf2070 v19.d[0] (xor, xfer vecreg #3)
+ 2c73db6a9066d986 v19.d[1] (xor, xfer vecreg #3)
+ 8c38cff987bc3b6a v20.d[0] (xor, xfer vecreg #3)
+ 0665c53a6774cd27 v20.d[1] (xor, xfer vecreg #3)
+ -4 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4r {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], x6 with x5 = middle_of_block+3, x6=-3
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 734b28334f8f35cd v17.d[0] (xor, xfer vecreg #1)
+ fee95c2612d14da2 v17.d[1] (xor, xfer vecreg #1)
+ fe24622d3a16e0a9 v18.d[0] (xor, xfer vecreg #2)
+ 3ce99738d5604acf v18.d[1] (xor, xfer vecreg #2)
+ 16233741cded106e v19.d[0] (xor, xfer vecreg #3)
+ e910d55303a56de4 v19.d[1] (xor, xfer vecreg #3)
+ e8af529943f49043 v20.d[0] (xor, xfer vecreg #3)
+ 26eb57b2ca55e2e7 v20.d[1] (xor, xfer vecreg #3)
+ -3 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4r {v17.8b , v18.8b , v19.8b , v20.8b }, [x5], x6 with x5 = middle_of_block+3, x6=-2
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ bcaf91f214d7642b v17.d[0] (xor, xfer vecreg #1)
+ 00e1e7420a3e4c21 v17.d[1] (xor, xfer vecreg #1)
+ e878268f83314d30 v18.d[0] (xor, xfer vecreg #2)
+ 3140b0d070f67dea v18.d[1] (xor, xfer vecreg #2)
+ 07a2b0211f7c931c v19.d[0] (xor, xfer vecreg #3)
+ bf40eff41c803416 v19.d[1] (xor, xfer vecreg #3)
+ 72da637b846c9a7b v20.d[0] (xor, xfer vecreg #3)
+ b03ae692ea2d493f v20.d[1] (xor, xfer vecreg #3)
+ -2 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
LD1/ST1 (single 1-elem struct to/from one lane of 1 reg
+st1 {v19.d}[0], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 01 2d a8 b4 0f b2 76 64 .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.d}[0], [x5], #8 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. 47 2e e1 a2 2c ea e4 0f ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 8 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.d}[0], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. ce 65 39 dd 2d 55 fc
+ [144] 35 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.d}[1], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. a9 4a ef 94 6f 52 36 db .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.d}[1], [x5], #8 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. 09 36 99 d5 0d 16 9f 76 ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 8 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.d}[1], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 24 76 a6 c3 1b 40 25
+ [144] ff .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.s}[0], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. ef cb ae 80 .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.s}[0], [x5], #4 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. 48 a7 db 1b .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 4 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.s}[0], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 40 f8 3a 9a .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.s}[3], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. f2 5d f7 79 .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.s}[3], [x5], #4 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. 89 e2 76 5c .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 4 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.s}[3], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 99 3e 68 99 .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.h}[0], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 44 42 .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.h}[0], [x5], #2 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. a8 80 .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 2 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.h}[0], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 1d 18 .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.h}[6], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 2b 91 .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.h}[6], [x5], #2 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. c5 41 .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 2 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.h}[6], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 13 44 .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.b}[0], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 01 .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.b}[0], [x5], #1 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. 68 .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 1 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.b}[0], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 65 .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.b}[13], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 1d .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.b}[13], [x5], #1 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. e0 .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 1 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v19.b}[13], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. c5 .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.d}[0], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 3ed778c2c8b1c15d v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.d}[0], [x5], #8 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 6f58669cd01c52bb v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 8 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.d}[0], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 4608b4c0dfe51f18 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.d}[1], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ f37bec4088138ccc v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.d}[1], [x5], #8 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ e76dcdf9933b90cb v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 8 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.d}[1], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ f1206a8f9d810ce1 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.s}[0], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 000000005b1c4dd3 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.s}[0], [x5], #4 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000024524409 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 4 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.s}[0], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 00000000b73752d9 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.s}[3], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 18d15a1200000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.s}[3], [x5], #4 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 22ec138d00000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 4 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.s}[3], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ fcec24d300000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.h}[0], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000006460 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.h}[0], [x5], #2 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 000000000000e876 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 2 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.h}[0], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 000000000000eb40 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.h}[6], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 00001af400000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.h}[6], [x5], #2 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000ba5800000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 2 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.h}[6], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 00000f8d00000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.b}[0], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 00000000000000f8 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.b}[0], [x5], #1 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 000000000000002a v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 1 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.b}[0], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 00000000000000d5 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.b}[13], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000760000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.b}[13], [x5], #1 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 00001b0000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 1 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v19.b}[13], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000f00000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
LD2/ST2 (single 2-elem struct to/from one lane of 2 regs
+st2 {v18.d, v19.d}[0], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 12 5f 5e bf 65 62 7a 42 a5 8e 0b 6f 59 9c 2f
+ [160] ae .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.d, v19.d}[0], [x5], #16 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. 61 03 e5 36 b3 52 e5 08 6b
+ [128] 3c bc 98 94 d0 37 f4 .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 16 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.d, v19.d}[0], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 23 d3 76 23 ae 25 62
+ [144] f6 2b 37 55 e6 3e 98 ff 18 .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.d, v19.d}[1], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 3f 63 e8 11 fa 0e d9 77 3b 1b b2 7d 12 99 56
+ [160] bc .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.d, v19.d}[1], [x5], #16 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. da 49 1f eb 38 f8 f9 97 cb
+ [128] 89 18 2b 2e 21 f1 a4 .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 16 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.d, v19.d}[1], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 71 e0 ee 46 33 e2 64
+ [144] 7c 76 e1 31 64 b0 5d 64 59 .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.s, v19.s}[0], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 41 ff bf 05 ed e2 93 99 .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.s, v19.s}[0], [x5], #8 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. de 6b 95 b2 bf f1 72 bf ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 8 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.s, v19.s}[0], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. df 90 99 3f 6a 8b 7d
+ [144] 7a .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.s, v19.s}[3], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. ee 0b 86 d0 2b ad dc a2 .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.s, v19.s}[3], [x5], #8 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. 08 f4 cd 30 96 0c e8 68 ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 8 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.s, v19.s}[3], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 8a 01 e9 2e 69 79 71
+ [144] 91 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.h, v19.h}[0], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 90 10 0c f6 .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.h, v19.h}[0], [x5], #4 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. 73 c9 dd 71 .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 4 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.h, v19.h}[0], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. bd 72 16 9d .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.h, v19.h}[6], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 64 fb 6d c0 .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.h, v19.h}[6], [x5], #4 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. fc 39 c1 a3 .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 4 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.h, v19.h}[6], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. c7 6a 09 d6 .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.b, v19.b}[0], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. fe 27 .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.b, v19.b}[0], [x5], #2 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. 21 1f .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 2 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.b, v19.b}[0], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. bf a3 .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.b, v19.b}[13], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 7c 5a .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.b, v19.b}[13], [x5], #2 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. 2f 6a .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 2 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v18.b, v19.b}[13], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. ca 0b .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.d, v19.d}[0], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 46c7fb3efcc3799e v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 70f211874bdc0202 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.d, v19.d}[0], [x5], #16 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 970df7ce67d7ad2d v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0c4a09642da2c063 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 16 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.d, v19.d}[0], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 5199e278057a5763 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ de440b1dca39ffa3 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.d, v19.d}[1], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 8950bb755312a3f9 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ a1b582cd79dc4288 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.d, v19.d}[1], [x5], #16 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 01bacf25a6c00afc v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 306ea57546858787 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 16 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.d, v19.d}[1], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 7c7649218dd1e1ff v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ d7206af619e1cd77 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.s, v19.s}[0], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 000000002b77117a v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 00000000dbef7046 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.s, v19.s}[0], [x5], #8 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 00000000ddf0d34d v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 00000000a8eee7a2 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 8 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.s, v19.s}[0], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 000000003b820676 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 00000000c7a5cf0f v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.s, v19.s}[3], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ cbf812b400000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ ae90fa5900000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.s, v19.s}[3], [x5], #8 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ d9d15e4d00000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ ed6a3cb000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 8 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.s, v19.s}[3], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 5797046700000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 4cd024e300000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.h, v19.h}[0], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 000000000000ca00 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 000000000000754b v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.h, v19.h}[0], [x5], #4 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 00000000000029c9 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 000000000000d547 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 4 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.h, v19.h}[0], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000008897 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 000000000000c5b2 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.h, v19.h}[6], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000afc600000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 000032e600000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.h, v19.h}[6], [x5], #4 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000e41100000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000f65700000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 4 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.h, v19.h}[6], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000fc9100000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000486400000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.b, v19.b}[0], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000079 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000023 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.b, v19.b}[0], [x5], #2 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 000000000000003a v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 000000000000005d v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 2 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.b, v19.b}[0], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000022 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 00000000000000b0 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.b, v19.b}[13], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 00004a0000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000630000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.b, v19.b}[13], [x5], #2 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000040000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 00000c0000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 2 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v18.b, v19.b}[13], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000630000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000b00000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
LD3/ST3 (single 3-elem struct to/from one lane of 3 regs
+st3 {v17.d, v18.d, v19.d}[0], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 2e 41 c4 69 4b fd b8 f1 53 72 62 fe bd 68 55
+ [160] 48 ec 83 60 6f 1b 5f 66 d2 .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.d, v18.d, v19.d}[0], [x5], #24 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. a6 57 42 df c0 84 1f d9 b9
+ [128] e8 22 db 54 c9 2d a7 05 5f 66 99 f2 5b 97 07 ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 24 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.d, v18.d, v19.d}[0], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. ca 8f b9 f4 a7 a0 fb
+ [144] 97 c2 2a 78 a2 b2 9a 0d ca 64 90 35 f0 f9 b0 74
+ [160] 9f .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.d, v18.d, v19.d}[1], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 5e 1f ad 76 21 e3 81 0d 75 8e 14 e5 33 97 64
+ [160] fe 9a a1 d8 99 56 25 c2 93 .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.d, v18.d, v19.d}[1], [x5], #24 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. 38 2e fd c2 d1 33 33 18 5b
+ [128] 9b 49 db 97 3c 08 e8 94 cb 0c c8 eb 98 70 04 ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 24 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.d, v18.d, v19.d}[1], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 4c 4b 1a 60 8f 1c 5d
+ [144] bf 0a 78 28 c6 44 56 92 ae 56 de bb 1d 20 23 2a
+ [160] 1a .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.s, v18.s, v19.s}[0], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 70 bc 81 f0 73 8d 72 78 ac ea 28 72 .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.s, v18.s, v19.s}[0], [x5], #12 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. 72 87 ab 29 40 b9 a7 26 1f
+ [128] 3e 9c ae .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 12 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.s, v18.s, v19.s}[0], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. a0 4f 01 3b 9e 53 dd
+ [144] c5 36 46 d5 8c .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.s, v18.s, v19.s}[3], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. f9 ce be 09 af b6 ee 18 cd 8d b0 88 .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.s, v18.s, v19.s}[3], [x5], #12 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. 69 5a a6 4f 95 47 ae 10 26
+ [128] 42 d1 c7 .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 12 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.s, v18.s, v19.s}[3], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 2e 57 c9 73 42 51 a7
+ [144] 91 04 d8 24 a4 .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.h, v18.h, v19.h}[0], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 8a 41 ae 99 36 cb .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.h, v18.h, v19.h}[0], [x5], #6 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. 0e 46 a1 92 f2 db .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 6 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.h, v18.h, v19.h}[0], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 52 cd 39 f5 2f 7d ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.h, v18.h, v19.h}[6], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 9f f4 c5 47 6f a2 .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.h, v18.h, v19.h}[6], [x5], #6 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. 08 01 5b dd 80 80 .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 6 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.h, v18.h, v19.h}[6], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 22 9c 89 c2 c2 81 ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.b, v18.b, v19.b}[0], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 79 b0 85 .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.b, v18.b, v19.b}[0], [x5], #3 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. 7b df 96 .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 3 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.b, v18.b, v19.b}[0], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. de c6 45 .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.b, v18.b, v19.b}[13], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 43 93 7b .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.b, v18.b, v19.b}[13], [x5], #3 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. 25 be 6f .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 3 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.b, v18.b, v19.b}[13], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. b5 e6 a8 .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.d, v18.d, v19.d}[0], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 5c104d370d6a99bf v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ ddc0c548cc240d8b v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 2186bd305c4ba5a2 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.d, v18.d, v19.d}[0], [x5], #24 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ cf21c69d6a3f91db v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 990f82a2c1d6d70f v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ c9a85f822490e1df v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 24 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.d, v18.d, v19.d}[0], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ a49542978622047d v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 52649a9f095a6c2d v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 625084b59de2ddd9 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.d, v18.d, v19.d}[1], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 06db0b02eae3e801 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 9b46e6f3d2170de5 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 8991b547f4b8ccbb v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.d, v18.d, v19.d}[1], [x5], #24 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ a3f362eba70c37e6 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ b64cc7d0e58f7da5 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 53a3a97695487365 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 24 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.d, v18.d, v19.d}[1], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 4a71397d600868b2 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ bd7c335aae66c22b v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 9635d0015a975857 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.s, v18.s, v19.s}[0], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000093771321 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 000000005f9a2d47 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 000000006b73bb0e v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.s, v18.s, v19.s}[0], [x5], #12 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 00000000d4486dcc v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000007fa3838 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 000000005826513b v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 12 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.s, v18.s, v19.s}[0], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 000000007c2e44f9 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000041ccd6d0 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 00000000ef725879 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.s, v18.s, v19.s}[3], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0412ea6f00000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 5b58a4be00000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 41cde01c00000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.s, v18.s, v19.s}[3], [x5], #12 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ be69f27000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ fc7207a100000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ bbc1c11f00000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 12 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.s, v18.s, v19.s}[3], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ d52de6f200000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 196eb09e00000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 3a1f37ec00000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.h, v18.h, v19.h}[0], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 000000000000ceb4 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 000000000000deec v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 000000000000688f v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.h, v18.h, v19.h}[0], [x5], #6 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 00000000000037a0 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000006698 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000b8c v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 6 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.h, v18.h, v19.h}[0], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 000000000000567b v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000007ec6 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 000000000000ce51 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.h, v18.h, v19.h}[6], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000311a00000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000b90c00000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000924800000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.h, v18.h, v19.h}[6], [x5], #6 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000d93900000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000692800000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 00006c1a00000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 6 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.h, v18.h, v19.h}[6], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000c42a00000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 00003e4600000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000adcc00000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.b, v18.b, v19.b}[0], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 00000000000000ae v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000055 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 00000000000000c8 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.b, v18.b, v19.b}[0], [x5], #3 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000053 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000027 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 000000000000006c v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 3 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.b, v18.b, v19.b}[0], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 000000000000009f v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 00000000000000bb v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 00000000000000af v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.b, v18.b, v19.b}[13], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 00006f0000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000280000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000090000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.b, v18.b, v19.b}[13], [x5], #3 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000810000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000bc0000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000ce0000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 3 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld3 {v17.b, v18.b, v19.b}[13], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000c20000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000ab0000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 00006b0000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
LD4/ST4 (single 4-elem struct to/from one lane of 4 regs
+st4 {v17.d, v18.d, v19.d, v20.d}[0], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. c5 33 d9 a3 ca fe b6 48 67 68 67 aa 22 b1 fb
+ [160] 63 c9 59 7e c8 75 8b 9f ac df 14 38 a6 7b 99 db
+ [176] 3c .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.d, v18.d, v19.d, v20.d}[0], [x5], #32 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. c9 76 4b 9c ca a8 c3 4d 72
+ [128] b1 59 b7 ee 2a ca 5b c0 4d 19 6f 49 34 3a 98 99
+ [144] c2 49 76 0d 1f b6 4f .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.d, v18.d, v19.d, v20.d}[0], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 70 59 13 58 a7 84 fd
+ [144] 32 0a 4d 83 eb fd 59 bc db 18 68 9f db 1c 67 3c
+ [160] a4 95 93 51 38 e1 32 a7 b0 .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.d, v18.d, v19.d, v20.d}[1], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 53 70 a4 1d 4c cb fd e7 c0 9c 11 f6 9d fd 20
+ [160] 14 86 46 07 50 0b a5 ab e0 a3 6a e8 fa da 35 9c
+ [176] 0e .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.d, v18.d, v19.d, v20.d}[1], [x5], #32 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. cc b0 1b 90 dc 81 cb f4 de
+ [128] fd 2e 40 0a 7d b0 fc 71 8b 04 a0 f1 09 36 ed b5
+ [144] fa e3 c9 91 25 0b fd .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.d, v18.d, v19.d, v20.d}[1], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. c0 25 45 61 aa 96 d0
+ [144] 0d f7 63 1d a5 02 e3 48 ec 89 34 26 96 0e dd 91
+ [160] c2 71 6b 95 6d 34 72 9c 5d .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.s, v18.s, v19.s, v20.s}[0], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. be fe 7e 2a d4 98 8b fd 71 e1 c2 9c a3 d2 20
+ [160] 2e .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.s, v18.s, v19.s, v20.s}[0], [x5], #16 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. 15 1d a4 4e 2f 28 e6 89 b1
+ [128] 10 d1 51 ff b1 ad 59 .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 16 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.s, v18.s, v19.s, v20.s}[0], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 1e 0a 62 3f 12 11 0c
+ [144] dd 0d cb 57 b4 8e ec 55 07 .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.s, v18.s, v19.s, v20.s}[3], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 59 a6 0e 8f bd a3 14 d6 5a 32 95 58 d8 5a fb
+ [160] 3e .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.s, v18.s, v19.s, v20.s}[3], [x5], #16 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. d8 d1 8d 6d 2c 22 d6 97 bb
+ [128] 8d 6c 3a 0b de d0 31 .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 16 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.s, v18.s, v19.s, v20.s}[3], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 7d e6 3c 03 21 2f a4
+ [144] 22 64 49 af b1 77 95 fe 99 .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.h, v18.h, v19.h, v20.h}[0], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 90 d3 ab 13 17 66 05 7a .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.h, v18.h, v19.h, v20.h}[0], [x5], #8 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. 31 54 de 0b 08 62 e5 95 ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 8 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.h, v18.h, v19.h, v20.h}[0], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. a8 77 33 30 03 2d 44
+ [144] 42 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.h, v18.h, v19.h, v20.h}[6], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. c6 6a f3 56 72 e3 cb ca .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.h, v18.h, v19.h, v20.h}[6], [x5], #8 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. 07 41 24 56 b3 39 9a 60 ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 8 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.h, v18.h, v19.h, v20.h}[6], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 59 6c f3 52 77 15 3c
+ [144] d9 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.b, v18.b, v19.b, v20.b}[0], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 39 fd 2b e5 .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.b, v18.b, v19.b, v20.b}[0], [x5], #4 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. 1e 0a e2 e3 .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 4 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.b, v18.b, v19.b, v20.b}[0], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. 0c 40 c6 ca .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.b, v18.b, v19.b, v20.b}[13], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. 3a de 20 79 .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.b, v18.b, v19.b, v20.b}[13], [x5], #4 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. 42 db 9d ca .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 4 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st4 {v17.b, v18.b, v19.b, v20.b}[13], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. e8 eb 75 c6 .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.d, v18.d, v19.d, v20.d}[0], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ b21c70d140a4a5c8 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 911dbd0d6f01540f v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ bb53b169cf059d60 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 999066d058bedf20 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.d, v18.d, v19.d, v20.d}[0], [x5], #32 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ e10c4430d5e0976a v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ f6b93f4443a7e356 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 8b45f9b4b2026ca6 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 75214dfc6f3a3117 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.d, v18.d, v19.d, v20.d}[0], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 06d96e52beb9724b v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 5c7d196ab0be972b v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 29a9939410ac2447 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ f71fbadce385d97d v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.d, v18.d, v19.d, v20.d}[1], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 3c735209b67f98aa v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0f6a005a4188afb3 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ cf3917d2df16ea45 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 524d601b9e7f2999 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.d, v18.d, v19.d, v20.d}[1], [x5], #32 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 392b70a19059b817 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ e24bff2d17d05e20 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ fe687a5f6c73fb80 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ c3d6ac54dc629146 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.d, v18.d, v19.d, v20.d}[1], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 1c213ec0225d4126 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 4a6ce8d95b709956 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 49e45d5fb2945f76 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ edaa67901c7c8afd v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.s, v18.s, v19.s, v20.s}[0], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 000000005fcd9113 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 00000000b0e6225e v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 00000000d22b956a v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 000000000c064e35 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.s, v18.s, v19.s, v20.s}[0], [x5], #16 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 00000000293051fa v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000046ea3756 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 000000007ba48f27 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 00000000749f40bc v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 16 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.s, v18.s, v19.s, v20.s}[0], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 00000000e0ab4aa6 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 000000001e56ef23 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000048700361 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 00000000db1d74f5 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.s, v18.s, v19.s, v20.s}[3], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 4d22f02100000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 7520c8dc00000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 33718c2900000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 3411c24500000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.s, v18.s, v19.s, v20.s}[3], [x5], #16 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ ad00a7c700000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ d39cc8c900000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ dcbb3a7600000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ ee9b605800000000 v20.d[1] (xor, xfer vecreg #3)
+ 16 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.s, v18.s, v19.s, v20.s}[3], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ fec2152c00000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 160a515e00000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 59af637500000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ f4c3804700000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.h, v18.h, v19.h, v20.h}[0], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000009cc4 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 000000000000276e v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000003d07 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000008e95 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.h, v18.h, v19.h, v20.h}[0], [x5], #8 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 000000000000cccd v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000009704 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 000000000000e1ec v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000007688 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 8 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.h, v18.h, v19.h, v20.h}[0], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 000000000000a766 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000004a00 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 000000000000ec4f v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000005cc0 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.h, v18.h, v19.h, v20.h}[6], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 00000b4f00000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 00003aaf00000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 000015a500000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 000039eb00000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.h, v18.h, v19.h, v20.h}[6], [x5], #8 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000b8ca00000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 00003ec700000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 00000f7400000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 00007ecd00000000 v20.d[1] (xor, xfer vecreg #3)
+ 8 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.h, v18.h, v19.h, v20.h}[6], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000eff400000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 000082d800000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000716b00000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000568000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.b, v18.b, v19.b, v20.b}[0], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000040 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 00000000000000d9 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 00000000000000d1 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 00000000000000f9 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.b, v18.b, v19.b, v20.b}[0], [x5], #4 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000031 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000064 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 00000000000000df v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 000000000000001d v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 4 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.b, v18.b, v19.b, v20.b}[0], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 000000000000006b v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 00000000000000a0 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 00000000000000a8 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 00000000000000fa v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.b, v18.b, v19.b, v20.b}[13], [x5] with x5 = middle_of_block+17, x6=7
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 00008e0000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 00006c0000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000c60000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000620000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.b, v18.b, v19.b, v20.b}[13], [x5], #4 with x5 = middle_of_block+-9, x6=12
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000740000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000810000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000280000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000940000000000 v20.d[1] (xor, xfer vecreg #3)
+ 4 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld4 {v17.b, v18.b, v19.b, v20.b}[13], [x5], x6 with x5 = middle_of_block+9, x6=13
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000ff0000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000ae0000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 00001f0000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000630000000000 v20.d[1] (xor, xfer vecreg #3)
+ 13 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
