commit db546602d7ef0053c41870ac75296fff720ce0de
author sewardj <sewardj@8f6e269a-dfd6-0310-a8e1-e2731360e62c> Thu Feb 16 19:09:43 2012 +0000
committer sewardj <sewardj@8f6e269a-dfd6-0310-a8e1-e2731360e62c> Thu Feb 16 19:09:43 2012 +0000
tree dd7b34d37f1505912504acaf0f5799a918e2209b
parent 3c3d6d62cb9fcf2cb8f96b21f28788a51960c5c3

Re-enable RET $imm16 following insn decoding framework rework. 
Fixes #292430 (a regression).


git-svn-id: svn://svn.valgrind.org/vex/trunk@2255 8f6e269a-dfd6-0310-a8e1-e2731360e62c

priv/guest_amd64_toIR.c

diff --git a/priv/guest_amd64_toIR.c b/priv/guest_amd64_toIR.c
index 1beca98..a8ba1d4 100644
--- a/priv/guest_amd64_toIR.c
+++ b/priv/guest_amd64_toIR.c
@@ -17432,6 +17432,15 @@
       return delta;
    }
 
+   case 0xC2: /* RET imm16 */
+      if (have66orF2orF3(pfx)) goto decode_failure;
+      d64 = getUDisp16(delta); 
+      delta += 2;
+      dis_ret(vbi, d64);
+      dres->whatNext = Dis_StopHere;
+      DIP("ret $%lld\n", d64);
+      return delta;
+
    case 0xC3: /* RET */
       if (have66orF2(pfx)) goto decode_failure;
       /* F3 is acceptable on AMD. */
@@ -19153,15 +19162,6 @@
 
    /* ------------------------ Control flow --------------- */
 
-   case 0xC2: /* RET imm16 */
-      if (have66orF2orF3(pfx)) goto decode_failure;
-      d64 = getUDisp16(delta); 
-      delta += 2;
-      dis_ret(vbi, d64);
-      dres.whatNext = Dis_StopHere;
-      DIP("ret %lld\n", d64);
-      break;
-
    /* ------------------------ CWD/CDQ -------------------- */
 
    /* ------------------------ FPU ops -------------------- */