commit b963eef76b2c754c4717b120cdf1912ba4b926d0
author sewardj <sewardj@8f6e269a-dfd6-0310-a8e1-e2731360e62c> Mon Nov 17 14:16:56 2014 +0000
committer sewardj <sewardj@8f6e269a-dfd6-0310-a8e1-e2731360e62c> Mon Nov 17 14:16:56 2014 +0000
tree 513418ccadf4280bc53621130848cdba895d7b59
parent 76927e6e81a18405ac41f667d1d598fe597a8465

Fix stupid bug introduced in r2993, which causes many simple scalar
floating point instructions to ignore their operands and return zero.  Sigh.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2994 8f6e269a-dfd6-0310-a8e1-e2731360e62c

priv/guest_arm64_toIR.c

diff --git a/priv/guest_arm64_toIR.c b/priv/guest_arm64_toIR.c
index 9d07328..f46fd5d 100644
--- a/priv/guest_arm64_toIR.c
+++ b/priv/guest_arm64_toIR.c
@@ -12171,9 +12171,11 @@
       }
       if (opcode <= BITS4(0,0,1,1)) {
          // This is really not good code.  TODO: avoid width-changing
+         IRTemp res = newTemp(ity);
+         assign(res, triop(iop, mkexpr(mk_get_IR_rounding_mode()),
+                                getQRegLO(nn, ity), getQRegLO(mm, ity)));
          putQReg128(dd, mkV128(0));
-         putQRegLO(dd, triop(iop, mkexpr(mk_get_IR_rounding_mode()),
-                                  getQRegLO(nn, ity), getQRegLO(mm, ity)));
+         putQRegLO(dd, mkexpr(res));
       } else {
          putQReg128(dd, unop(mkVecZEROHIxxOFV128(ty+2),
                              binop(iop, getQReg128(nn), getQReg128(mm))));