commit aec051d4ba2557d9bd9a5d54bc236396d33950a9
author sewardj <sewardj@8f6e269a-dfd6-0310-a8e1-e2731360e62c> Wed Jun 04 11:36:54 2014 +0000
committer sewardj <sewardj@8f6e269a-dfd6-0310-a8e1-e2731360e62c> Wed Jun 04 11:36:54 2014 +0000
tree 991b3f78951a40119291ad29d1360c64c96fa6bc
parent 6ced72b3286a45a9fd05989a1e13c0ac5b911fee

Support movi_{16b,8b}_#imm8.  Fixes #335262.  (dimitry@google.com)



git-svn-id: svn://svn.valgrind.org/vex/trunk@2866 8f6e269a-dfd6-0310-a8e1-e2731360e62c

priv/guest_arm64_toIR.c

diff --git a/priv/guest_arm64_toIR.c b/priv/guest_arm64_toIR.c
index 25659b8..7876ee1 100644
--- a/priv/guest_arm64_toIR.c
+++ b/priv/guest_arm64_toIR.c
@@ -5398,7 +5398,7 @@
                                               MOV Vd.2d #imm (q=1)
       Allowable op:cmode
          FMOV = 1:1111
-         MOVI = 0:xx00, 1:0x00, 1:10x0, 1:110x, 11110
+         MOVI = 0:xx00, 1:0x00, 1:10x0, 1:110x, x:1110
    */
    if (INSN(31,31) == 0
        && INSN(28,19) == BITS10(0,1,1,1,1,0,0,0,0,0)
@@ -5418,7 +5418,7 @@
          case BITS5(1,0,0,0,0): case BITS5(1,0,1,0,0): // 1:0x00
          case BITS5(1,1,0,0,0): case BITS5(1,1,0,1,0): // 1:10x0
          case BITS5(1,1,1,0,0): case BITS5(1,1,1,0,1): // 1:110x
-         case BITS5(1,1,1,1,0): // 1:1110
+         case BITS5(1,1,1,1,0): case BITS5(0,1,1,1,0): // x:1110
             ok = True; break;
          default:
            break;