The vector versions of the count leading zeros/sign bits primops
(Iop_Cls* and Iop_Clz*) misleadingly imply a signedness in the
incoming lanes. Rename them to fix this. Fixes #326026.
git-svn-id: svn://svn.valgrind.org/vex/trunk@2889 8f6e269a-dfd6-0310-a8e1-e2731360e62c
diff --git a/priv/guest_arm64_toIR.c b/priv/guest_arm64_toIR.c
index 84fac0e..48851aa 100644
--- a/priv/guest_arm64_toIR.c
+++ b/priv/guest_arm64_toIR.c
@@ -7468,8 +7468,8 @@
/* -------- 0,xx,00100: CLS std6_std6 -------- */
/* -------- 1,xx,00100: CLZ std6_std6 -------- */
if (size == X11) return False; // no 1d or 2d cases
- const IROp opsCLS[3] = { Iop_Cls8Sx16, Iop_Cls16Sx8, Iop_Cls32Sx4 };
- const IROp opsCLZ[3] = { Iop_Clz8Sx16, Iop_Clz16Sx8, Iop_Clz32Sx4 };
+ const IROp opsCLS[3] = { Iop_Cls8x16, Iop_Cls16x8, Iop_Cls32x4 };
+ const IROp opsCLZ[3] = { Iop_Clz8x16, Iop_Clz16x8, Iop_Clz32x4 };
Bool isCLZ = bitU == 1;
IRTemp res = newTemp(Ity_V128);
vassert(size <= 2);
diff --git a/priv/guest_arm_toIR.c b/priv/guest_arm_toIR.c
index dd9d155..cb186b0 100644
--- a/priv/guest_arm_toIR.c
+++ b/priv/guest_arm_toIR.c
@@ -6740,9 +6740,9 @@
/* VCLS */
IROp op;
switch (size) {
- case 0: op = Q ? Iop_Cls8Sx16 : Iop_Cls8Sx8; break;
- case 1: op = Q ? Iop_Cls16Sx8 : Iop_Cls16Sx4; break;
- case 2: op = Q ? Iop_Cls32Sx4 : Iop_Cls32Sx2; break;
+ case 0: op = Q ? Iop_Cls8x16 : Iop_Cls8x8; break;
+ case 1: op = Q ? Iop_Cls16x8 : Iop_Cls16x4; break;
+ case 2: op = Q ? Iop_Cls32x4 : Iop_Cls32x2; break;
case 3: return False;
default: vassert(0);
}
@@ -6755,9 +6755,9 @@
/* VCLZ */
IROp op;
switch (size) {
- case 0: op = Q ? Iop_Clz8Sx16 : Iop_Clz8Sx8; break;
- case 1: op = Q ? Iop_Clz16Sx8 : Iop_Clz16Sx4; break;
- case 2: op = Q ? Iop_Clz32Sx4 : Iop_Clz32Sx2; break;
+ case 0: op = Q ? Iop_Clz8x16 : Iop_Clz8x8; break;
+ case 1: op = Q ? Iop_Clz16x8 : Iop_Clz16x4; break;
+ case 2: op = Q ? Iop_Clz32x4 : Iop_Clz32x2; break;
case 3: return False;
default: vassert(0);
}
diff --git a/priv/guest_ppc_toIR.c b/priv/guest_ppc_toIR.c
index ebf0388..d39debf 100644
--- a/priv/guest_ppc_toIR.c
+++ b/priv/guest_ppc_toIR.c
@@ -13303,17 +13303,17 @@
switch (opc2) {
case 0x702: // vclzb
DIP("vclzb v%d,v%d\n", vRT_addr, vRB_addr);
- putVReg( vRT_addr, unop(Iop_Clz8Sx16, mkexpr( vB ) ) );
+ putVReg( vRT_addr, unop(Iop_Clz8x16, mkexpr( vB ) ) );
break;
case 0x742: // vclzh
DIP("vclzh v%d,v%d\n", vRT_addr, vRB_addr);
- putVReg( vRT_addr, unop(Iop_Clz16Sx8, mkexpr( vB ) ) );
+ putVReg( vRT_addr, unop(Iop_Clz16x8, mkexpr( vB ) ) );
break;
case 0x782: // vclzw
DIP("vclzw v%d,v%d\n", vRT_addr, vRB_addr);
- putVReg( vRT_addr, unop(Iop_Clz32Sx4, mkexpr( vB ) ) );
+ putVReg( vRT_addr, unop(Iop_Clz32x4, mkexpr( vB ) ) );
break;
case 0x7C2: // vclzd
diff --git a/priv/host_arm64_isel.c b/priv/host_arm64_isel.c
index d640a0d..35bebfa 100644
--- a/priv/host_arm64_isel.c
+++ b/priv/host_arm64_isel.c
@@ -4414,8 +4414,8 @@
case Iop_Neg64Fx2: case Iop_Neg32Fx4:
case Iop_Abs64x2: case Iop_Abs32x4:
case Iop_Abs16x8: case Iop_Abs8x16:
- case Iop_Cls32Sx4: case Iop_Cls16Sx8: case Iop_Cls8Sx16:
- case Iop_Clz32Sx4: case Iop_Clz16Sx8: case Iop_Clz8Sx16:
+ case Iop_Cls32x4: case Iop_Cls16x8: case Iop_Cls8x16:
+ case Iop_Clz32x4: case Iop_Clz16x8: case Iop_Clz8x16:
case Iop_Cnt8x16:
{
HReg res = newVRegV(env);
@@ -4431,12 +4431,12 @@
case Iop_Abs32x4: op = ARM64vecu_ABS32x4; break;
case Iop_Abs16x8: op = ARM64vecu_ABS16x8; break;
case Iop_Abs8x16: op = ARM64vecu_ABS8x16; break;
- case Iop_Cls32Sx4: op = ARM64vecu_CLS32x4; break;
- case Iop_Cls16Sx8: op = ARM64vecu_CLS16x8; break;
- case Iop_Cls8Sx16: op = ARM64vecu_CLS8x16; break;
- case Iop_Clz32Sx4: op = ARM64vecu_CLZ32x4; break;
- case Iop_Clz16Sx8: op = ARM64vecu_CLZ16x8; break;
- case Iop_Clz8Sx16: op = ARM64vecu_CLZ8x16; break;
+ case Iop_Cls32x4: op = ARM64vecu_CLS32x4; break;
+ case Iop_Cls16x8: op = ARM64vecu_CLS16x8; break;
+ case Iop_Cls8x16: op = ARM64vecu_CLS8x16; break;
+ case Iop_Clz32x4: op = ARM64vecu_CLZ32x4; break;
+ case Iop_Clz16x8: op = ARM64vecu_CLZ16x8; break;
+ case Iop_Clz8x16: op = ARM64vecu_CLZ8x16; break;
case Iop_Cnt8x16: op = ARM64vecu_CNT8x16; break;
default: vassert(0);
}
diff --git a/priv/host_arm_isel.c b/priv/host_arm_isel.c
index c8be9e4..4a19a81 100644
--- a/priv/host_arm_isel.c
+++ b/priv/host_arm_isel.c
@@ -3577,32 +3577,32 @@
res, arg, size, False));
return res;
}
- case Iop_Clz8Sx8:
- case Iop_Clz16Sx4:
- case Iop_Clz32Sx2: {
+ case Iop_Clz8x8:
+ case Iop_Clz16x4:
+ case Iop_Clz32x2: {
HReg res = newVRegD(env);
HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
UInt size = 0;
switch(e->Iex.Binop.op) {
- case Iop_Clz8Sx8: size = 0; break;
- case Iop_Clz16Sx4: size = 1; break;
- case Iop_Clz32Sx2: size = 2; break;
+ case Iop_Clz8x8: size = 0; break;
+ case Iop_Clz16x4: size = 1; break;
+ case Iop_Clz32x2: size = 2; break;
default: vassert(0);
}
addInstr(env, ARMInstr_NUnary(ARMneon_CLZ,
res, arg, size, False));
return res;
}
- case Iop_Cls8Sx8:
- case Iop_Cls16Sx4:
- case Iop_Cls32Sx2: {
+ case Iop_Cls8x8:
+ case Iop_Cls16x4:
+ case Iop_Cls32x2: {
HReg res = newVRegD(env);
HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
UInt size = 0;
switch(e->Iex.Binop.op) {
- case Iop_Cls8Sx8: size = 0; break;
- case Iop_Cls16Sx4: size = 1; break;
- case Iop_Cls32Sx2: size = 2; break;
+ case Iop_Cls8x8: size = 0; break;
+ case Iop_Cls16x4: size = 1; break;
+ case Iop_Cls32x2: size = 2; break;
default: vassert(0);
}
addInstr(env, ARMInstr_NUnary(ARMneon_CLS,
@@ -4174,31 +4174,31 @@
addInstr(env, ARMInstr_NUnary(ARMneon_CNT, res, arg, size, True));
return res;
}
- case Iop_Clz8Sx16:
- case Iop_Clz16Sx8:
- case Iop_Clz32Sx4: {
+ case Iop_Clz8x16:
+ case Iop_Clz16x8:
+ case Iop_Clz32x4: {
HReg res = newVRegV(env);
HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
UInt size = 0;
switch(e->Iex.Binop.op) {
- case Iop_Clz8Sx16: size = 0; break;
- case Iop_Clz16Sx8: size = 1; break;
- case Iop_Clz32Sx4: size = 2; break;
+ case Iop_Clz8x16: size = 0; break;
+ case Iop_Clz16x8: size = 1; break;
+ case Iop_Clz32x4: size = 2; break;
default: vassert(0);
}
addInstr(env, ARMInstr_NUnary(ARMneon_CLZ, res, arg, size, True));
return res;
}
- case Iop_Cls8Sx16:
- case Iop_Cls16Sx8:
- case Iop_Cls32Sx4: {
+ case Iop_Cls8x16:
+ case Iop_Cls16x8:
+ case Iop_Cls32x4: {
HReg res = newVRegV(env);
HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
UInt size = 0;
switch(e->Iex.Binop.op) {
- case Iop_Cls8Sx16: size = 0; break;
- case Iop_Cls16Sx8: size = 1; break;
- case Iop_Cls32Sx4: size = 2; break;
+ case Iop_Cls8x16: size = 0; break;
+ case Iop_Cls16x8: size = 1; break;
+ case Iop_Cls32x4: size = 2; break;
default: vassert(0);
}
addInstr(env, ARMInstr_NUnary(ARMneon_CLS, res, arg, size, True));
diff --git a/priv/host_ppc_isel.c b/priv/host_ppc_isel.c
index d35ea6d..5a4b71b 100644
--- a/priv/host_ppc_isel.c
+++ b/priv/host_ppc_isel.c
@@ -4853,10 +4853,10 @@
return dst;
}
- case Iop_Clz8Sx16: op = Pav_ZEROCNTBYTE; goto do_zerocnt;
- case Iop_Clz16Sx8: op = Pav_ZEROCNTHALF; goto do_zerocnt;
- case Iop_Clz32Sx4: op = Pav_ZEROCNTWORD; goto do_zerocnt;
- case Iop_Clz64x2: op = Pav_ZEROCNTDBL; goto do_zerocnt;
+ case Iop_Clz8x16: op = Pav_ZEROCNTBYTE; goto do_zerocnt;
+ case Iop_Clz16x8: op = Pav_ZEROCNTHALF; goto do_zerocnt;
+ case Iop_Clz32x4: op = Pav_ZEROCNTWORD; goto do_zerocnt;
+ case Iop_Clz64x2: op = Pav_ZEROCNTDBL; goto do_zerocnt;
case Iop_PwBitMtxXpose64x2: op = Pav_BITMTXXPOSE; goto do_zerocnt;
do_zerocnt:
{
diff --git a/priv/ir_defs.c b/priv/ir_defs.c
index 4d65daf..9cdc9f6 100644
--- a/priv/ir_defs.c
+++ b/priv/ir_defs.c
@@ -508,12 +508,12 @@
case Iop_CmpGT16Sx4: vex_printf("CmpGT16Sx4"); return;
case Iop_CmpGT32Sx2: vex_printf("CmpGT32Sx2"); return;
case Iop_Cnt8x8: vex_printf("Cnt8x8"); return;
- case Iop_Clz8Sx8: vex_printf("Clz8Sx8"); return;
- case Iop_Clz16Sx4: vex_printf("Clz16Sx4"); return;
- case Iop_Clz32Sx2: vex_printf("Clz32Sx2"); return;
- case Iop_Cls8Sx8: vex_printf("Cls8Sx8"); return;
- case Iop_Cls16Sx4: vex_printf("Cls16Sx4"); return;
- case Iop_Cls32Sx2: vex_printf("Cls32Sx2"); return;
+ case Iop_Clz8x8: vex_printf("Clz8x8"); return;
+ case Iop_Clz16x4: vex_printf("Clz16x4"); return;
+ case Iop_Clz32x2: vex_printf("Clz32x2"); return;
+ case Iop_Cls8x8: vex_printf("Cls8x8"); return;
+ case Iop_Cls16x4: vex_printf("Cls16x4"); return;
+ case Iop_Cls32x2: vex_printf("Cls32x2"); return;
case Iop_ShlN8x8: vex_printf("ShlN8x8"); return;
case Iop_ShlN16x4: vex_printf("ShlN16x4"); return;
case Iop_ShlN32x2: vex_printf("ShlN32x2"); return;
@@ -838,13 +838,13 @@
case Iop_CmpGT64Ux2: vex_printf("CmpGT64Ux2"); return;
case Iop_Cnt8x16: vex_printf("Cnt8x16"); return;
- case Iop_Clz8Sx16: vex_printf("Clz8Sx16"); return;
- case Iop_Clz16Sx8: vex_printf("Clz16Sx8"); return;
- case Iop_Clz32Sx4: vex_printf("Clz32Sx4"); return;
+ case Iop_Clz8x16: vex_printf("Clz8x16"); return;
+ case Iop_Clz16x8: vex_printf("Clz16x8"); return;
+ case Iop_Clz32x4: vex_printf("Clz32x4"); return;
case Iop_Clz64x2: vex_printf("Clz64x2"); return;
- case Iop_Cls8Sx16: vex_printf("Cls8Sx16"); return;
- case Iop_Cls16Sx8: vex_printf("Cls16Sx8"); return;
- case Iop_Cls32Sx4: vex_printf("Cls32Sx4"); return;
+ case Iop_Cls8x16: vex_printf("Cls8x16"); return;
+ case Iop_Cls16x8: vex_printf("Cls16x8"); return;
+ case Iop_Cls32x4: vex_printf("Cls32x4"); return;
case Iop_ShlV128: vex_printf("ShlV128"); return;
case Iop_ShrV128: vex_printf("ShrV128"); return;
@@ -2518,8 +2518,8 @@
case Iop_Not64:
case Iop_CmpNEZ32x2: case Iop_CmpNEZ16x4: case Iop_CmpNEZ8x8:
case Iop_Cnt8x8:
- case Iop_Clz8Sx8: case Iop_Clz16Sx4: case Iop_Clz32Sx2:
- case Iop_Cls8Sx8: case Iop_Cls16Sx4: case Iop_Cls32Sx2:
+ case Iop_Clz8x8: case Iop_Clz16x4: case Iop_Clz32x2:
+ case Iop_Cls8x8: case Iop_Cls16x4: case Iop_Cls32x2:
case Iop_PwAddL8Ux8: case Iop_PwAddL16Ux4: case Iop_PwAddL32Ux2:
case Iop_PwAddL8Sx8: case Iop_PwAddL16Sx4: case Iop_PwAddL32Sx2:
case Iop_Reverse64_8x8: case Iop_Reverse64_16x4: case Iop_Reverse64_32x2:
@@ -2903,8 +2903,8 @@
case Iop_CmpNEZ8x16: case Iop_CmpNEZ16x8:
case Iop_CmpNEZ32x4: case Iop_CmpNEZ64x2:
case Iop_Cnt8x16:
- case Iop_Clz8Sx16: case Iop_Clz16Sx8: case Iop_Clz32Sx4: case Iop_Clz64x2:
- case Iop_Cls8Sx16: case Iop_Cls16Sx8: case Iop_Cls32Sx4:
+ case Iop_Clz8x16: case Iop_Clz16x8: case Iop_Clz32x4: case Iop_Clz64x2:
+ case Iop_Cls8x16: case Iop_Cls16x8: case Iop_Cls32x4:
case Iop_PwAddL8Ux16: case Iop_PwAddL16Ux8: case Iop_PwAddL32Ux4:
case Iop_PwAddL8Sx16: case Iop_PwAddL16Sx8: case Iop_PwAddL32Sx4:
case Iop_Reverse64_8x16: case Iop_Reverse64_16x8: case Iop_Reverse64_32x4:
diff --git a/pub/libvex_ir.h b/pub/libvex_ir.h
index c61ce23..aa9defc 100644
--- a/pub/libvex_ir.h
+++ b/pub/libvex_ir.h
@@ -900,8 +900,8 @@
/* COUNT ones / leading zeroes / leading sign bits (not including topmost
bit) */
Iop_Cnt8x8,
- Iop_Clz8Sx8, Iop_Clz16Sx4, Iop_Clz32Sx2,
- Iop_Cls8Sx8, Iop_Cls16Sx4, Iop_Cls32Sx2,
+ Iop_Clz8x8, Iop_Clz16x4, Iop_Clz32x2,
+ Iop_Cls8x8, Iop_Cls16x4, Iop_Cls32x2,
Iop_Clz64x2,
/* VECTOR x VECTOR SHIFT / ROTATE */
@@ -1503,8 +1503,8 @@
/* COUNT ones / leading zeroes / leading sign bits (not including topmost
bit) */
Iop_Cnt8x16,
- Iop_Clz8Sx16, Iop_Clz16Sx8, Iop_Clz32Sx4,
- Iop_Cls8Sx16, Iop_Cls16Sx8, Iop_Cls32Sx4,
+ Iop_Clz8x16, Iop_Clz16x8, Iop_Clz32x4,
+ Iop_Cls8x16, Iop_Cls16x8, Iop_Cls32x4,
/* VECTOR x SCALAR SHIFT (shift amt :: Ity_I8) */
Iop_ShlN8x16, Iop_ShlN16x8, Iop_ShlN32x4, Iop_ShlN64x2,
