commit 999ef56da3e4426c5f6bf74de40d23ff02dafb34
author carll <carll@8f6e269a-dfd6-0310-a8e1-e2731360e62c> Mon Apr 20 23:34:33 2015 +0000
committer carll <carll@8f6e269a-dfd6-0310-a8e1-e2731360e62c> Mon Apr 20 23:34:33 2015 +0000
tree c5f5ee044786f78b26388929e3b423e6de0a34ab
parent d826889bd512ded2fbbc4781c595ecf0513f46f6

Fix for an error in the stq, stqcx, lqarx and lq instructions with LE.



git-svn-id: svn://svn.valgrind.org/vex/trunk@3138 8f6e269a-dfd6-0310-a8e1-e2731360e62c

priv/guest_ppc_toIR.c

diff --git a/priv/guest_ppc_toIR.c b/priv/guest_ppc_toIR.c
index c76a2ef..6a29c47 100644
--- a/priv/guest_ppc_toIR.c
+++ b/priv/guest_ppc_toIR.c
@@ -5125,10 +5125,17 @@
        */
       // trap if EA misaligned on 16 byte address
       if (mode64) {
-         assign(high, load(ty, mkexpr( EA ) ) );
-         assign(low, load(ty, binop( Iop_Add64,
-                                     mkexpr( EA ),
-                                     mkU64( 8 ) ) ) );
+         if (host_endness == VexEndnessBE) {
+            assign(high, load(ty, mkexpr( EA ) ) );
+            assign(low, load(ty, binop( Iop_Add64,
+                                        mkexpr( EA ),
+                                        mkU64( 8 ) ) ) );
+	 } else {
+            assign(low, load(ty, mkexpr( EA ) ) );
+            assign(high, load(ty, binop( Iop_Add64,
+                                         mkexpr( EA ),
+                                         mkU64( 8 ) ) ) );
+	 }
       } else {
          assign(high, load(ty, binop( Iop_Add32,
                                       mkexpr( EA ),
@@ -5336,11 +5343,20 @@
          DIP("stq r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);
 
          if (mode64) {
-            /* upper 64-bits */
-            assign( EA_hi, ea_rAor0_simm( rA_addr, simm16 ) );
+            if (host_endness == VexEndnessBE) {
 
-            /* lower 64-bits */
-            assign( EA_lo, ea_rAor0_simm( rA_addr, simm16+8 ) );
+               /* upper 64-bits */
+               assign( EA_hi, ea_rAor0_simm( rA_addr, simm16 ) );
+
+               /* lower 64-bits */
+               assign( EA_lo, ea_rAor0_simm( rA_addr, simm16+8 ) );
+	    } else {
+               /* upper 64-bits */
+               assign( EA_hi, ea_rAor0_simm( rA_addr, simm16+8 ) );
+
+               /* lower 64-bits */
+               assign( EA_lo, ea_rAor0_simm( rA_addr, simm16 ) );
+	    }
          } else {
             /* upper half of upper 64-bits */
             assign( EA_hi, ea_rAor0_simm( rA_addr, simm16+4 ) );
@@ -6535,11 +6551,19 @@
 
          // and actually do the load
          if (mode64) {
-            stmt( stmt_load( res_hi,
-                             mkexpr(EA), NULL/*this is a load*/) );
-            stmt( stmt_load( res_lo,
-                             binop(Iop_Add64, mkexpr(EA), mkU64(8) ),
-                             NULL/*this is a load*/) );
+            if (host_endness == VexEndnessBE) {
+               stmt( stmt_load( res_hi,
+                                mkexpr(EA), NULL/*this is a load*/) );
+               stmt( stmt_load( res_lo,
+                                binop(Iop_Add64, mkexpr(EA), mkU64(8) ),
+                                NULL/*this is a load*/) );
+	    } else {
+               stmt( stmt_load( res_lo,
+                                mkexpr(EA), NULL/*this is a load*/) );
+               stmt( stmt_load( res_hi,
+                                binop(Iop_Add64, mkexpr(EA), mkU64(8) ),
+                                NULL/*this is a load*/) );
+            }
          } else {
             stmt( stmt_load( res_hi,
                              binop( Iop_Add32, mkexpr(EA), mkU32(4) ),
@@ -6575,8 +6599,15 @@
          resSC = newTemp(Ity_I1);
 
          if (mode64) {
-            stmt( stmt_load( resSC, mkexpr(EA), mkexpr(rS_hi) ) );
-            store( binop( Iop_Add64, mkexpr(EA), mkU64(8) ), mkexpr(rS_lo) );
+            if (host_endness == VexEndnessBE) {
+               stmt( stmt_load( resSC, mkexpr(EA), mkexpr(rS_hi) ) );
+               store( binop( Iop_Add64, mkexpr(EA), mkU64(8) ),
+                      mkexpr(rS_lo) );
+	    } else {
+               stmt( stmt_load( resSC, mkexpr(EA), mkexpr(rS_lo) ) );
+               store( binop( Iop_Add64, mkexpr(EA), mkU64(8) ),
+                      mkexpr(rS_hi) );
+	    }
          } else {
             stmt( stmt_load( resSC, binop( Iop_Add32,
                                            mkexpr(EA),