commit 89d1d5eeafed6a27f86caf17d7271990f6494986
author mjw <mjw@a5019735-40e9-0310-863c-91ae7b9d1cf9> Thu Mar 28 21:24:57 2013 +0000
committer mjw <mjw@a5019735-40e9-0310-863c-91ae7b9d1cf9> Thu Mar 28 21:24:57 2013 +0000
tree 036cc5f783d3b851b4c85358fd781543221a9c8f
parent 04ce9f5a123696267c2c2302dc64d2b254bfb0fa

Add new MISC vector Iops to memcheck/tests/vbit-test/irops.c.

memcheck/tests/vbit-test fails with unknown opcode after introduction
of new Iops for AVX2, BMI, FMA support #317506

git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13347 a5019735-40e9-0310-863c-91ae7b9d1cf9

memcheck/tests/vbit-test/irops.c

diff --git a/memcheck/tests/vbit-test/irops.c b/memcheck/tests/vbit-test/irops.c
index e187f32..c8b9ef3 100644
--- a/memcheck/tests/vbit-test/irops.c
+++ b/memcheck/tests/vbit-test/irops.c
@@ -858,8 +858,62 @@
   { DEFOP(Iop_OrV256,  UNDEF_UNKNOWN), },
   { DEFOP(Iop_XorV256, UNDEF_UNKNOWN), },
   { DEFOP(Iop_NotV256, UNDEF_UNKNOWN), },
+  /* --------------- MISC (vector integer cmp != 0) -------------*/
+  { DEFOP(Iop_CmpNEZ8x32, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_CmpNEZ16x16, UNDEF_UNKNOWN), },
   { DEFOP(Iop_CmpNEZ32x8, UNDEF_UNKNOWN), },
   { DEFOP(Iop_CmpNEZ64x4, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_Add8x32, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_Add16x16, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_Add32x8, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_Add64x4, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_Sub8x32, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_Sub16x16, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_Sub32x8, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_Sub64x4, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_CmpEQ8x32, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_CmpEQ16x16, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_CmpEQ32x8, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_CmpEQ64x4, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_CmpGT8Sx32, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_CmpGT16Sx16, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_CmpGT32Sx8, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_CmpGT64Sx4, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_ShlN16x16, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_ShlN32x8, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_ShlN64x4, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_ShrN16x16, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_ShrN32x8, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_ShrN64x4, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_SarN16x16, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_SarN32x8, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_Max8Sx32, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_Max16Sx16, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_Max32Sx8, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_Max8Ux32, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_Max16Ux16, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_Max32Ux8, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_Min8Sx32, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_Min16Sx16, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_Min32Sx8, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_Min8Ux32, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_Min16Ux16, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_Min32Ux8, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_Mul16x16, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_Mul32x8, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_MulHi16Ux16, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_MulHi16Sx16, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_QAdd8Ux32, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_QAdd16Ux16, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_QAdd8Sx32, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_QAdd16Sx16, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_QSub8Ux32, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_QSub16Ux16, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_QSub8Sx32, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_QSub16Sx16, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_Avg8Ux32, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_Avg16Ux16, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_Perm32x8, UNDEF_UNKNOWN), },
   /* ------------------ 256-bit SIMD FP. ------------------ */
   { DEFOP(Iop_Add64Fx4, UNDEF_UNKNOWN), },
   { DEFOP(Iop_Sub64Fx4, UNDEF_UNKNOWN), },