commit 7fce7cc5134d2f496d23b407c7556bc69adb2bad
author sewardj <sewardj@8f6e269a-dfd6-0310-a8e1-e2731360e62c> Wed May 07 09:41:40 2014 +0000
committer sewardj <sewardj@8f6e269a-dfd6-0310-a8e1-e2731360e62c> Wed May 07 09:41:40 2014 +0000
tree 2014f788cfdbe0ee20fd8b42a35e073d34286328
parent ac0c92bd3ff8700c78166e38ed602bfbc6acce6b

Enable 'smulh'.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2856 8f6e269a-dfd6-0310-a8e1-e2731360e62c

priv/guest_arm64_toIR.c

diff --git a/priv/guest_arm64_toIR.c b/priv/guest_arm64_toIR.c
index 55ca7e2..57a2d4f 100644
--- a/priv/guest_arm64_toIR.c
+++ b/priv/guest_arm64_toIR.c
@@ -2373,8 +2373,7 @@
       10011011 0  10 Rm 011111 Rn Rd   SMULH Xd,Xn,Xm
    */
    if (INSN(31,24) == BITS8(1,0,0,1,1,0,1,1)
-       && INSN(22,21) == BITS2(1,0) && INSN(15,10) == BITS6(0,1,1,1,1,1)
-       && INSN(23,23) == 1/*ATC*/) {
+       && INSN(22,21) == BITS2(1,0) && INSN(15,10) == BITS6(0,1,1,1,1,1)) {
       Bool isU = INSN(23,23) == 1;
       UInt mm  = INSN(20,16);
       UInt nn  = INSN(9,5);

priv/host_arm64_defs.c

diff --git a/priv/host_arm64_defs.c b/priv/host_arm64_defs.c
index 8aa27e6..3bc5217 100644
--- a/priv/host_arm64_defs.c
+++ b/priv/host_arm64_defs.c
@@ -4591,9 +4591,9 @@
             case ARM64mul_ZX:
                *p++ = X_3_8_5_6_5_5(X100, X11011110, mm, X011111, nn, dd);
                goto done;
-            //case ARM64mul_SX:
-            //   *p++ = X_3_8_5_6_5_5(X100, X11011010, mm, X011111, nn, dd);
-            //   goto done;
+            case ARM64mul_SX:
+               *p++ = X_3_8_5_6_5_5(X100, X11011010, mm, X011111, nn, dd);
+               goto done;
             case ARM64mul_PLAIN:
                *p++ = X_3_8_5_6_5_5(X100, X11011000, mm, X011111, nn, dd);
                goto done;

priv/host_arm64_isel.c

diff --git a/priv/host_arm64_isel.c b/priv/host_arm64_isel.c
index c54c973..eb06cdf 100644
--- a/priv/host_arm64_isel.c
+++ b/priv/host_arm64_isel.c
@@ -2408,7 +2408,7 @@
       switch (e->Iex.Binop.op) {
          /* 64 x 64 -> 128 multiply */
          case Iop_MullU64:
-         /*case Iop_MullS64:*/ {
+         case Iop_MullS64: {
             Bool syned = toBool(e->Iex.Binop.op == Iop_MullS64);
             HReg argL  = iselIntExpr_R(env, e->Iex.Binop.arg1);
             HReg argR  = iselIntExpr_R(env, e->Iex.Binop.arg2);