commit 702054ef0b1f8ca632c6c07280e04fadf49eb477
author sewardj <sewardj@8f6e269a-dfd6-0310-a8e1-e2731360e62c> Wed May 07 11:09:28 2014 +0000
committer sewardj <sewardj@8f6e269a-dfd6-0310-a8e1-e2731360e62c> Wed May 07 11:09:28 2014 +0000
tree 391ef22dc011590e95489410dde28b9050f7396d
parent 7fce7cc5134d2f496d23b407c7556bc69adb2bad

Handle "blr lr" correctly -- read the destination register
_before_ writing the return address in LR.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2857 8f6e269a-dfd6-0310-a8e1-e2731360e62c

priv/guest_arm64_toIR.c

diff --git a/priv/guest_arm64_toIR.c b/priv/guest_arm64_toIR.c
index 57a2d4f..862eb20 100644
--- a/priv/guest_arm64_toIR.c
+++ b/priv/guest_arm64_toIR.c
@@ -4453,8 +4453,10 @@
          return True;
       }
       if (branch_type == BITS2(0,1) /* CALL */) {
+         IRTemp dst = newTemp(Ity_I64);
+         assign(dst, getIReg64orZR(nn));
          putIReg64orSP(30, mkU64(guest_PC_curr_instr + 4));
-         putPC(getIReg64orZR(nn));
+         putPC(mkexpr(dst));
          dres->whatNext = Dis_StopHere;
          dres->jk_StopHere = Ijk_Call;
          DIP("blr %s\n", nameIReg64orZR(nn));