commit 643d501b0ac9478a58058952f367aef30e9b80b4
author sewardj <sewardj@a5019735-40e9-0310-863c-91ae7b9d1cf9> Mon Oct 14 11:41:46 2013 +0000
committer sewardj <sewardj@a5019735-40e9-0310-863c-91ae7b9d1cf9> Mon Oct 14 11:41:46 2013 +0000
tree 9ce7948a8a41ced6fff63e8e74ae8d6693daccf5
parent ad56d00b1219e8ecd55959f4ea87d42c825e877f

PPC32/64: Allow 16 byte icache and dcache lines.
Partial fix for #308135.  (christophe.leroy@c-s.fr)


git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13637 a5019735-40e9-0310-863c-91ae7b9d1cf9

coregrind/m_libcproc.c

diff --git a/coregrind/m_libcproc.c b/coregrind/m_libcproc.c
index 0b9ae23..9a434b3 100644
--- a/coregrind/m_libcproc.c
+++ b/coregrind/m_libcproc.c
@@ -745,7 +745,7 @@
    cls = vai.ppc_icache_line_szB;
 
    /* Stay sane .. */
-   vg_assert(cls == 32 || cls == 64 || cls == 128);
+   vg_assert(cls == 16 || cls == 32 || cls == 64 || cls == 128);
 
    startaddr &= ~(cls - 1);
    for (addr = startaddr; addr < endaddr; addr += cls) {

coregrind/m_machine.c

diff --git a/coregrind/m_machine.c b/coregrind/m_machine.c
index 7dacdc7..69bd7ac 100644
--- a/coregrind/m_machine.c
+++ b/coregrind/m_machine.c
@@ -486,7 +486,7 @@
       if (!test_block[i])
          ++dcbz_szB;
    }
-   vg_assert(dcbz_szB == 32 || dcbz_szB == 64 || dcbz_szB == 128);
+   vg_assert(dcbz_szB == 16 || dcbz_szB == 32 || dcbz_szB == 64 || dcbz_szB == 128);
 
    /* dcbzl clears 128B on G5/PPC970, and usually 32B on other platforms */
    if (VG_MINIMAL_SETJMP(env_unsup_insn)) {
@@ -504,7 +504,7 @@
          if (!test_block[i])
             ++dcbzl_szB;
       }
-      vg_assert(dcbzl_szB == 32 || dcbzl_szB == 64 || dcbzl_szB == 128);
+      vg_assert(dcbzl_szB == 16 || dcbzl_szB == 32 || dcbzl_szB == 64 || dcbzl_szB == 128);
    }
 
    arch_info->ppc_dcbz_szB  = dcbz_szB;
@@ -1541,7 +1541,7 @@
    vg_assert(vai.ppc_icache_line_szB == 0
              || vai.ppc_icache_line_szB == szB);
 
-   vg_assert(szB == 32 || szB == 64 || szB == 128);
+   vg_assert(szB == 16 || szB == 32 || szB == 64 || szB == 128);
    vai.ppc_icache_line_szB = szB;
 }
 #endif
@@ -1559,7 +1559,7 @@
    vg_assert(vai.ppc_icache_line_szB == 0
              || vai.ppc_icache_line_szB == szB);
 
-   vg_assert(szB == 32 || szB == 64 || szB == 128);
+   vg_assert(szB == 16 || szB == 32 || szB == 64 || szB == 128);
    vai.ppc_icache_line_szB = szB;
 }
 #endif