Fix HChar / UCHar / Char mixups. VEX now compiles without
warnings about assigning pointers to incompatible types.
git-svn-id: svn://svn.valgrind.org/vex/trunk@2550 8f6e269a-dfd6-0310-a8e1-e2731360e62c
diff --git a/priv/guest_amd64_helpers.c b/priv/guest_amd64_helpers.c
index 5f95e45..4b3508b 100644
--- a/priv/guest_amd64_helpers.c
+++ b/priv/guest_amd64_helpers.c
@@ -514,7 +514,7 @@
static void showCounts ( void )
{
Int op, co;
- Char ch;
+ HChar ch;
vex_printf("\nTotal calls: calc_all=%u calc_cond=%u calc_c=%u\n",
n_calc_all, n_calc_cond, n_calc_c);
diff --git a/priv/guest_amd64_toIR.c b/priv/guest_amd64_toIR.c
index ed12a3e..7474802 100644
--- a/priv/guest_amd64_toIR.c
+++ b/priv/guest_amd64_toIR.c
@@ -10773,7 +10773,7 @@
UChar modrm = getUChar(delta);
IRTemp arg64 = newTemp(Ity_I64);
UInt rG = gregOfRexRM(pfx,modrm);
- UChar* mbV = isAvx ? "v" : "";
+ HChar* mbV = isAvx ? "v" : "";
if (epartIsReg(modrm)) {
UInt rE = eregOfRexRM(pfx,modrm);
assign( arg64, getXMMRegLane64(rE, 0) );
@@ -15704,8 +15704,8 @@
HChar dis_buf[50];
IRTemp srcVec = newTemp(Ity_V128);
UChar modrm = getUChar(delta);
- UChar* mbV = isAvx ? "v" : "";
- UChar how = xIsZ ? 'z' : 's';
+ HChar* mbV = isAvx ? "v" : "";
+ HChar how = xIsZ ? 'z' : 's';
UInt rG = gregOfRexRM(pfx, modrm);
if ( epartIsReg(modrm) ) {
UInt rE = eregOfRexRM(pfx, modrm);
@@ -15746,8 +15746,8 @@
HChar dis_buf[50];
IRTemp srcVec = newTemp(Ity_V128);
UChar modrm = getUChar(delta);
- UChar* mbV = isAvx ? "v" : "";
- UChar how = xIsZ ? 'z' : 's';
+ HChar* mbV = isAvx ? "v" : "";
+ HChar how = xIsZ ? 'z' : 's';
UInt rG = gregOfRexRM(pfx, modrm);
if ( epartIsReg(modrm) ) {
@@ -15785,7 +15785,7 @@
HChar dis_buf[50];
IRTemp srcBytes = newTemp(Ity_I32);
UChar modrm = getUChar(delta);
- UChar* mbV = isAvx ? "v" : "";
+ HChar* mbV = isAvx ? "v" : "";
UInt rG = gregOfRexRM(pfx, modrm);
if ( epartIsReg( modrm ) ) {
@@ -15818,7 +15818,7 @@
HChar dis_buf[50];
IRTemp srcVec = newTemp(Ity_V128);
UChar modrm = getUChar(delta);
- UChar* mbV = isAvx ? "v" : "";
+ HChar* mbV = isAvx ? "v" : "";
UInt rG = gregOfRexRM(pfx, modrm);
if ( epartIsReg( modrm ) ) {
@@ -15856,8 +15856,8 @@
IRTemp srcI64 = newTemp(Ity_I64);
IRTemp srcVec = newTemp(Ity_V128);
UChar modrm = getUChar(delta);
- UChar* mbV = isAvx ? "v" : "";
- UChar how = xIsZ ? 'z' : 's';
+ HChar* mbV = isAvx ? "v" : "";
+ HChar how = xIsZ ? 'z' : 's';
UInt rG = gregOfRexRM(pfx, modrm);
/* Compute both srcI64 -- the value to expand -- and srcVec -- same
thing in a V128, with arbitrary junk in the top 64 bits. Use
@@ -15902,8 +15902,8 @@
HChar dis_buf[50];
IRTemp srcVec = newTemp(Ity_V128);
UChar modrm = getUChar(delta);
- UChar* mbV = isAvx ? "v" : "";
- UChar how = xIsZ ? 'z' : 's';
+ HChar* mbV = isAvx ? "v" : "";
+ HChar how = xIsZ ? 'z' : 's';
UInt rG = gregOfRexRM(pfx, modrm);
if ( epartIsReg(modrm) ) {
UInt rE = eregOfRexRM(pfx, modrm);
@@ -15945,7 +15945,7 @@
HChar dis_buf[50];
IRTemp srcBytes = newTemp(Ity_I16);
UChar modrm = getUChar(delta);
- UChar* mbV = isAvx ? "v" : "";
+ HChar* mbV = isAvx ? "v" : "";
UInt rG = gregOfRexRM(pfx, modrm);
if ( epartIsReg(modrm) ) {
UInt rE = eregOfRexRM(pfx, modrm);
@@ -15978,7 +15978,7 @@
HChar dis_buf[50];
IRTemp srcVec = newTemp(Ity_V128);
UChar modrm = getUChar(delta);
- UChar* mbV = isAvx ? "v" : "";
+ HChar* mbV = isAvx ? "v" : "";
UInt rG = gregOfRexRM(pfx, modrm);
if ( epartIsReg(modrm) ) {
UInt rE = eregOfRexRM(pfx, modrm);
@@ -16015,7 +16015,7 @@
Int alen = 0;
HChar dis_buf[50];
UChar modrm = getUChar(delta);
- UChar* mbV = isAvx ? "v" : "";
+ HChar* mbV = isAvx ? "v" : "";
IRTemp sV = newTemp(Ity_V128);
IRTemp sHi = newTemp(Ity_I64);
IRTemp sLo = newTemp(Ity_I64);
@@ -17120,7 +17120,7 @@
IRTemp xmm_vec = newTemp(Ity_V128);
IRTemp sel_lane = newTemp(Ity_I32);
IRTemp shr_lane = newTemp(Ity_I32);
- UChar* mbV = isAvx ? "v" : "";
+ HChar* mbV = isAvx ? "v" : "";
UChar modrm = getUChar(delta);
IRTemp t3, t2, t1, t0;
Int imm8;
@@ -23164,7 +23164,7 @@
UInt rD = gregOfRexRM(pfx, modrm);
IRTemp tD = newTemp(Ity_V256);
Bool isA = have66noF2noF3(pfx);
- UChar ch = isA ? 'a' : 'u';
+ HChar ch = isA ? 'a' : 'u';
if (epartIsReg(modrm)) {
UInt rS = eregOfRexRM(pfx, modrm);
delta += 1;
@@ -23189,7 +23189,7 @@
UInt rD = gregOfRexRM(pfx, modrm);
IRTemp tD = newTemp(Ity_V128);
Bool isA = have66noF2noF3(pfx);
- UChar ch = isA ? 'a' : 'u';
+ HChar ch = isA ? 'a' : 'u';
if (epartIsReg(modrm)) {
UInt rS = eregOfRexRM(pfx, modrm);
delta += 1;
@@ -23590,7 +23590,7 @@
UInt rS = gregOfRexRM(pfx, modrm);
IRTemp tS = newTemp(Ity_V256);
Bool isA = have66noF2noF3(pfx);
- UChar ch = isA ? 'a' : 'u';
+ HChar ch = isA ? 'a' : 'u';
assign(tS, getYMMReg(rS));
if (epartIsReg(modrm)) {
UInt rD = eregOfRexRM(pfx, modrm);
@@ -23615,7 +23615,7 @@
UInt rS = gregOfRexRM(pfx, modrm);
IRTemp tS = newTemp(Ity_V128);
Bool isA = have66noF2noF3(pfx);
- UChar ch = isA ? 'a' : 'u';
+ HChar ch = isA ? 'a' : 'u';
assign(tS, getXMMReg(rS));
if (epartIsReg(modrm)) {
UInt rD = eregOfRexRM(pfx, modrm);
@@ -24597,7 +24597,7 @@
IRTemp dV = newTemp(Ity_V128);
IRTemp sHi, sLo, dHi, dLo;
sHi = sLo = dHi = dLo = IRTemp_INVALID;
- UChar ch = '?';
+ HChar ch = '?';
Int laneszB = 0;
UChar modrm = getUChar(delta);
UInt rG = gregOfRexRM(pfx,modrm);
diff --git a/priv/guest_arm_toIR.c b/priv/guest_arm_toIR.c
index 34b925d..5f5a0c8 100644
--- a/priv/guest_arm_toIR.c
+++ b/priv/guest_arm_toIR.c
@@ -2383,7 +2383,7 @@
vassert(rN < 16);
vassert(bU < 2);
vassert(imm12 < 0x1000);
- UChar opChar = bU == 1 ? '+' : '-';
+ HChar opChar = bU == 1 ? '+' : '-';
DIS(buf, "[r%u, #%c%u]", rN, opChar, imm12);
return
binop( (bU == 1 ? Iop_Add32 : Iop_Sub32),
@@ -2405,7 +2405,7 @@
vassert(rM < 16);
vassert(sh2 < 4);
vassert(imm5 < 32);
- UChar opChar = bU == 1 ? '+' : '-';
+ HChar opChar = bU == 1 ? '+' : '-';
IRExpr* index = NULL;
switch (sh2) {
case 0: /* LSL */
@@ -2472,7 +2472,7 @@
vassert(rN < 16);
vassert(bU < 2);
vassert(imm8 < 0x100);
- UChar opChar = bU == 1 ? '+' : '-';
+ HChar opChar = bU == 1 ? '+' : '-';
DIS(buf, "[r%u, #%c%u]", rN, opChar, imm8);
return
binop( (bU == 1 ? Iop_Add32 : Iop_Sub32),
@@ -2489,7 +2489,7 @@
vassert(rN < 16);
vassert(bU < 2);
vassert(rM < 16);
- UChar opChar = bU == 1 ? '+' : '-';
+ HChar opChar = bU == 1 ? '+' : '-';
IRExpr* index = getIRegA(rM);
DIS(buf, "[r%u, %c r%u]", rN, opChar, rM);
return binop(bU == 1 ? Iop_Add32 : Iop_Sub32,
@@ -2644,9 +2644,9 @@
block are tagged with a 1 bit.
*/
static Bool compute_ITSTATE ( /*OUT*/UInt* itstate,
- /*OUT*/UChar* ch1,
- /*OUT*/UChar* ch2,
- /*OUT*/UChar* ch3,
+ /*OUT*/HChar* ch1,
+ /*OUT*/HChar* ch2,
+ /*OUT*/HChar* ch3,
UInt firstcond, UInt mask )
{
vassert(firstcond <= 0xF);
@@ -3061,7 +3061,7 @@
IROp addOp;
IROp andOp;
IROp shOp;
- char regType = Q ? 'q' : 'd';
+ HChar regType = Q ? 'q' : 'd';
if (size == 3)
return False;
@@ -3130,7 +3130,7 @@
/* VQADD */
IROp op, op2;
IRTemp tmp;
- char reg_t = Q ? 'q' : 'd';
+ HChar reg_t = Q ? 'q' : 'd';
if (Q) {
switch (size) {
case 0:
@@ -15715,9 +15715,9 @@
UInt newITSTATE = 0;
/* This is the ITSTATE represented as described in
libvex_guest_arm.h. It is not the ARM ARM representation. */
- UChar c1 = '.';
- UChar c2 = '.';
- UChar c3 = '.';
+ HChar c1 = '.';
+ HChar c2 = '.';
+ HChar c3 = '.';
Bool valid = compute_ITSTATE( &newITSTATE, &c1, &c2, &c3,
firstcond, mask );
if (valid && firstcond != 0xF/*NV*/) {
diff --git a/priv/guest_ppc_toIR.c b/priv/guest_ppc_toIR.c
index f7d8d0f..800f8ef 100644
--- a/priv/guest_ppc_toIR.c
+++ b/priv/guest_ppc_toIR.c
@@ -12089,7 +12089,7 @@
case 0x1A0: // xvsubdp (VSX Vector Subtract Double-Precision)
{
IROp mOp;
- Char * oper_name;
+ HChar * oper_name;
switch (opc2) {
case 0x1E0:
mOp = Iop_DivF64;
@@ -12158,7 +12158,7 @@
*/
Bool negate;
IROp mOp = Iop_INVALID;
- Char * oper_name = NULL;
+ HChar * oper_name = NULL;
Bool mdp = False;
switch (opc2) {
@@ -12420,7 +12420,7 @@
IRTemp t3, t2, t1, t0;
Bool msp = False;
Bool negate;
- Char * oper_name = NULL;
+ HChar * oper_name = NULL;
IROp mOp = Iop_INVALID;
switch (opc2) {
case 0x104: case 0x124:
@@ -12811,7 +12811,7 @@
/*
* Helper function for vector/scalar double precision fp round to integer instructions.
*/
-static IRExpr * _do_vsx_fp_roundToInt(IRTemp frB_I64, UInt opc2, UChar * insn_suffix)
+static IRExpr * _do_vsx_fp_roundToInt(IRTemp frB_I64, UInt opc2, HChar * insn_suffix)
{
/* The same rules apply for x{s|v}rdpi{m|p|c|z} as for floating point round operations (fri{m|n|p|z}). */
@@ -13271,7 +13271,7 @@
IRTemp frBLo_I64 = newTemp(Ity_I64);
IRExpr * frD_fp_roundHi = NULL;
IRExpr * frD_fp_roundLo = NULL;
- UChar * insn_suffix = NULL;
+ HChar * insn_suffix = NULL;
assign( frBHi_I64, unop( Iop_V128HIto64, getVSReg( XB ) ) );
frD_fp_roundHi = _do_vsx_fp_roundToInt(frBHi_I64, opc2, insn_suffix);
@@ -13291,7 +13291,7 @@
case 0x152: // xvrspip (VSX Vector Round to SinglePrecision Integer using round toward +Infinity)
case 0x132: // xvrspiz (VSX Vector Round to SinglePrecision Integer using round toward Zero)
{
- UChar * insn_suffix = NULL;
+ HChar * insn_suffix = NULL;
IROp op;
if (opc2 != 0x156) {
// Use pre-defined IRop's for vrfi{m|n|p|z}
@@ -13880,7 +13880,7 @@
{
IRTemp frB_I64 = newTemp(Ity_I64);
IRExpr * frD_fp_round = NULL;
- UChar * insn_suffix = NULL;
+ HChar * insn_suffix = NULL;
assign(frB_I64, unop(Iop_V128HIto64, mkexpr( vB )));
frD_fp_round = _do_vsx_fp_roundToInt(frB_I64, opc2, insn_suffix);
@@ -14218,7 +14218,7 @@
case 0x48: // xxmrghw (VSX Merge High Word)
case 0xc8: // xxmrglw (VSX Merge Low Word)
{
- char type = (opc2 == 0x48) ? 'h' : 'l';
+ HChar type = (opc2 == 0x48) ? 'h' : 'l';
IROp word_op = (opc2 == 0x48) ? Iop_V128HIto64 : Iop_V128to64;
IRTemp a64 = newTemp(Ity_I64);
IRTemp ahi32 = newTemp(Ity_I32);
@@ -16273,7 +16273,7 @@
struct vsx_insn {
UInt opcode;
- Char * name;
+ HChar * name;
};
// ATTENTION: Keep this array sorted on the opcocde!!!
diff --git a/priv/guest_x86_helpers.c b/priv/guest_x86_helpers.c
index 1a6f894..1ae1d3c 100644
--- a/priv/guest_x86_helpers.c
+++ b/priv/guest_x86_helpers.c
@@ -436,7 +436,7 @@
static void showCounts ( void )
{
Int op, co;
- Char ch;
+ HChar ch;
vex_printf("\nTotal calls: calc_all=%u calc_cond=%u calc_c=%u\n",
n_calc_all, n_calc_cond, n_calc_c);
diff --git a/priv/host_mips_defs.c b/priv/host_mips_defs.c
index 590372a..02f3967 100644
--- a/priv/host_mips_defs.c
+++ b/priv/host_mips_defs.c
@@ -1648,7 +1648,7 @@
case Min_Load: {
Bool idxd = toBool(i->Min.Load.src->tag == Mam_RR);
UChar sz = i->Min.Load.sz;
- UChar c_sz = sz == 1 ? 'b' : sz == 2 ? 'h' : sz == 4 ? 'w' : 'd';
+ HChar c_sz = sz == 1 ? 'b' : sz == 2 ? 'h' : sz == 4 ? 'w' : 'd';
vex_printf("l%c%s ", c_sz, idxd ? "x" : "");
ppHRegMIPS(i->Min.Load.dst, mode64);
vex_printf(",");
@@ -1658,7 +1658,7 @@
case Min_Store: {
UChar sz = i->Min.Store.sz;
Bool idxd = toBool(i->Min.Store.dst->tag == Mam_RR);
- UChar c_sz = sz == 1 ? 'b' : sz == 2 ? 'h' : sz == 4 ? 'w' : 'd';
+ HChar c_sz = sz == 1 ? 'b' : sz == 2 ? 'h' : sz == 4 ? 'w' : 'd';
vex_printf("s%c%s ", c_sz, idxd ? "x" : "");
ppHRegMIPS(i->Min.Store.src, mode64);
vex_printf(",");
diff --git a/priv/host_ppc_defs.c b/priv/host_ppc_defs.c
index 44c23ba..52f84ef 100644
--- a/priv/host_ppc_defs.c
+++ b/priv/host_ppc_defs.c
@@ -1624,7 +1624,7 @@
case Pin_Load: {
Bool idxd = toBool(i->Pin.Load.src->tag == Pam_RR);
UChar sz = i->Pin.Load.sz;
- UChar c_sz = sz==1 ? 'b' : sz==2 ? 'h' : sz==4 ? 'w' : 'd';
+ HChar c_sz = sz==1 ? 'b' : sz==2 ? 'h' : sz==4 ? 'w' : 'd';
vex_printf("l%c%s%s ", c_sz, sz==8 ? "" : "z", idxd ? "x" : "" );
ppHRegPPC(i->Pin.Load.dst);
vex_printf(",");
@@ -1640,7 +1640,7 @@
case Pin_Store: {
UChar sz = i->Pin.Store.sz;
Bool idxd = toBool(i->Pin.Store.dst->tag == Pam_RR);
- UChar c_sz = sz==1 ? 'b' : sz==2 ? 'h' : sz==4 ? 'w' : /*8*/ 'd';
+ HChar c_sz = sz==1 ? 'b' : sz==2 ? 'h' : sz==4 ? 'w' : /*8*/ 'd';
vex_printf("st%c%s ", c_sz, idxd ? "x" : "" );
ppHRegPPC(i->Pin.Store.src);
vex_printf(",");
@@ -1927,7 +1927,7 @@
case Pin_AvSplat: {
UChar sz = i->Pin.AvSplat.sz;
- UChar ch_sz = toUChar( (sz == 8) ? 'b' : (sz == 16) ? 'h' : 'w' );
+ HChar ch_sz = toUChar( (sz == 8) ? 'b' : (sz == 16) ? 'h' : 'w' );
vex_printf("vsplt%s%c ",
i->Pin.AvSplat.src->tag == Pvi_Imm ? "is" : "", ch_sz);
ppHRegPPC(i->Pin.AvSplat.dst);
