commit 5ba41309fde9d8eaccd95511e0d21de399cd70c6
author sewardj <sewardj@8f6e269a-dfd6-0310-a8e1-e2731360e62c> Mon Mar 03 08:42:16 2014 +0000
committer sewardj <sewardj@8f6e269a-dfd6-0310-a8e1-e2731360e62c> Mon Mar 03 08:42:16 2014 +0000
tree ded604d71798610d53e9d9bd9d49b879fbab491b
parent 32d86752b69511cce5caab9f731a9751c9ac2262

Fix error in 64-bit and smaller load versions of 
LDR/STR (immediate, SIMD&FP, unsigned offset)


git-svn-id: svn://svn.valgrind.org/vex/trunk@2831 8f6e269a-dfd6-0310-a8e1-e2731360e62c

priv/guest_arm64_toIR.c

diff --git a/priv/guest_arm64_toIR.c b/priv/guest_arm64_toIR.c
index b8a5875..73c7f8b 100644
--- a/priv/guest_arm64_toIR.c
+++ b/priv/guest_arm64_toIR.c
@@ -3276,7 +3276,6 @@
                     getIReg64orZR(rT2));
          } else {
             vassert(bL == 0 && bX == 0);
-            vassert(0); //ATC
             // 32 bit store
             storeLE(binop(Iop_Add64,mkexpr(tTA),mkU64(0)),
                     getIReg32orZR(rT1));
@@ -3685,8 +3684,14 @@
          }
 
          if (isLD) {
+            if (szB < 16) {
+               putQReg128(tt1, mkV128(0x0000));
+            }
             putQRegLO(tt1,
                       loadLE(ty, binop(Iop_Add64, mkexpr(tTA), mkU64(0))));
+            if (szB < 16) {
+               putQReg128(tt2, mkV128(0x0000));
+            }
             putQRegLO(tt2,
                       loadLE(ty, binop(Iop_Add64, mkexpr(tTA), mkU64(szB))));
          } else {