| misc ad-hoc tests |
| add x3, x4, x5 :: rd 0000000000004abe rm 0000000000003039, rn 0000000000001a85, cin 0, nzcv 00000000 |
| add w3, w4, w5 :: rd 0000000000004abe rm 0000000000003039, rn 0000000000001a85, cin 0, nzcv 00000000 |
| adc x3, x4, x5 :: rd 0000000000004abe rm 0000000000003039, rn 0000000000001a85, cin 0, nzcv 00000000 |
| adc x3, x4, x5 :: rd 0000000000004abf rm 0000000000003039, rn 0000000000001a85, cin 1, nzcv 20000000 C |
| adc x3, x4, x5 :: rd ffffffffffffffff rm 0000000000000000, rn ffffffffffffffff, cin 0, nzcv 00000000 |
| adc x3, x4, x5 :: rd 0000000000000000 rm 0000000000000000, rn ffffffffffffffff, cin 1, nzcv 20000000 C |
| adc x3, x4, x5 :: rd 5859704f00000000 rm 3141592700000000, rn 2718172800000000, cin 0, nzcv 00000000 |
| adc x3, x4, x5 :: rd 5859704f00000001 rm 3141592700000000, rn 2718172800000000, cin 1, nzcv 20000000 C |
| adc x3, x4, x5 :: rd 0000000000000000 rm 0000000000000000, rn 0000000000000000, cin 0, nzcv 00000000 |
| adc x3, x4, x5 :: rd 0000000000000001 rm 0000000000000000, rn 0000000000000000, cin 1, nzcv 20000000 C |
| adc x3, x4, x5 :: rd 0000000100000000 rm 0000000100000000, rn 0000000000000000, cin 0, nzcv 00000000 |
| adc x3, x4, x5 :: rd 0000000100000001 rm 0000000100000000, rn 0000000000000000, cin 1, nzcv 20000000 C |
| adc x3, x4, x5 :: rd 0000000100000000 rm 0000000000000000, rn 0000000100000000, cin 0, nzcv 00000000 |
| adc x3, x4, x5 :: rd 0000000100000001 rm 0000000000000000, rn 0000000100000000, cin 1, nzcv 20000000 C |
| adc x3, x4, x5 :: rd 8000000000000000 rm 8000000000000000, rn 0000000000000000, cin 0, nzcv 00000000 |
| adc x3, x4, x5 :: rd 8000000000000001 rm 8000000000000000, rn 0000000000000000, cin 1, nzcv 20000000 C |
| adc x3, x4, x5 :: rd 8000000000000000 rm 0000000000000000, rn 8000000000000000, cin 0, nzcv 00000000 |
| adc x3, x4, x5 :: rd 8000000000000001 rm 0000000000000000, rn 8000000000000000, cin 1, nzcv 20000000 C |
| adc x3, x4, x5 :: rd 0000000000000000 rm 8000000000000000, rn 8000000000000000, cin 0, nzcv 00000000 |
| adc x3, x4, x5 :: rd 0000000000000001 rm 8000000000000000, rn 8000000000000000, cin 1, nzcv 20000000 C |
| adc w3, w4, w5 :: rd 0000000000004abe rm 0000000000003039, rn 0000000000001a85, cin 0, nzcv 00000000 |
| adc w3, w4, w5 :: rd 0000000000004abf rm 0000000000003039, rn 0000000000001a85, cin 1, nzcv 20000000 C |
| adc w3, w4, w5 :: rd 00000000ffffffff rm 0000000000000000, rn 00000000ffffffff, cin 0, nzcv 00000000 |
| adc w3, w4, w5 :: rd 0000000000000000 rm 0000000000000000, rn 00000000ffffffff, cin 1, nzcv 20000000 C |
| adc w3, w4, w5 :: rd 000000005859704f rm 0000000031415927, rn 0000000027181728, cin 0, nzcv 00000000 |
| adc w3, w4, w5 :: rd 0000000058597050 rm 0000000031415927, rn 0000000027181728, cin 1, nzcv 20000000 C |
| adc w3, w4, w5 :: rd 0000000000000000 rm 0000000000000000, rn 0000000000000000, cin 0, nzcv 00000000 |
| adc w3, w4, w5 :: rd 0000000000000001 rm 0000000000000000, rn 0000000000000000, cin 1, nzcv 20000000 C |
| adc w3, w4, w5 :: rd 0000000000000001 rm 0000000000000001, rn 0000000000000000, cin 0, nzcv 00000000 |
| adc w3, w4, w5 :: rd 0000000000000002 rm 0000000000000001, rn 0000000000000000, cin 1, nzcv 20000000 C |
| adc w3, w4, w5 :: rd 0000000000000001 rm 0000000000000000, rn 0000000000000001, cin 0, nzcv 00000000 |
| adc w3, w4, w5 :: rd 0000000000000002 rm 0000000000000000, rn 0000000000000001, cin 1, nzcv 20000000 C |
| adc w3, w4, w5 :: rd 0000000080000000 rm 0000000080000000, rn 0000000000000000, cin 0, nzcv 00000000 |
| adc w3, w4, w5 :: rd 0000000080000001 rm 0000000080000000, rn 0000000000000000, cin 1, nzcv 20000000 C |
| adc w3, w4, w5 :: rd 0000000080000000 rm 0000000000000000, rn 0000000080000000, cin 0, nzcv 00000000 |
| adc w3, w4, w5 :: rd 0000000080000001 rm 0000000000000000, rn 0000000080000000, cin 1, nzcv 20000000 C |
| adc w3, w4, w5 :: rd 0000000000000000 rm 0000000080000000, rn 0000000080000000, cin 0, nzcv 00000000 |
| adc w3, w4, w5 :: rd 0000000000000001 rm 0000000080000000, rn 0000000080000000, cin 1, nzcv 20000000 C |
| adcs x3, x4, x5 :: rd 0000000000004abe rm 0000000000003039, rn 0000000000001a85, cin 0, nzcv 00000000 |
| adcs x3, x4, x5 :: rd 0000000000004abf rm 0000000000003039, rn 0000000000001a85, cin 1, nzcv 00000000 |
| adcs x3, x4, x5 :: rd ffffffffffffffff rm 0000000000000000, rn ffffffffffffffff, cin 0, nzcv 80000000 N |
| adcs x3, x4, x5 :: rd 0000000000000000 rm 0000000000000000, rn ffffffffffffffff, cin 1, nzcv 60000000 ZC |
| adcs x3, x4, x5 :: rd 5859704f00000000 rm 3141592700000000, rn 2718172800000000, cin 0, nzcv 00000000 |
| adcs x3, x4, x5 :: rd 5859704f00000001 rm 3141592700000000, rn 2718172800000000, cin 1, nzcv 00000000 |
| adcs x3, x4, x5 :: rd 0000000000000000 rm 0000000000000000, rn 0000000000000000, cin 0, nzcv 40000000 Z |
| adcs x3, x4, x5 :: rd 0000000000000001 rm 0000000000000000, rn 0000000000000000, cin 1, nzcv 00000000 |
| adcs x3, x4, x5 :: rd 0000000100000000 rm 0000000100000000, rn 0000000000000000, cin 0, nzcv 00000000 |
| adcs x3, x4, x5 :: rd 0000000100000001 rm 0000000100000000, rn 0000000000000000, cin 1, nzcv 00000000 |
| adcs x3, x4, x5 :: rd 0000000100000000 rm 0000000000000000, rn 0000000100000000, cin 0, nzcv 00000000 |
| adcs x3, x4, x5 :: rd 0000000100000001 rm 0000000000000000, rn 0000000100000000, cin 1, nzcv 00000000 |
| adcs x3, x4, x5 :: rd 8000000000000000 rm 8000000000000000, rn 0000000000000000, cin 0, nzcv 80000000 N |
| adcs x3, x4, x5 :: rd 8000000000000001 rm 8000000000000000, rn 0000000000000000, cin 1, nzcv 80000000 N |
| adcs x3, x4, x5 :: rd 8000000000000000 rm 0000000000000000, rn 8000000000000000, cin 0, nzcv 80000000 N |
| adcs x3, x4, x5 :: rd 8000000000000001 rm 0000000000000000, rn 8000000000000000, cin 1, nzcv 80000000 N |
| adcs x3, x4, x5 :: rd 0000000000000000 rm 8000000000000000, rn 8000000000000000, cin 0, nzcv 70000000 ZCV |
| adcs x3, x4, x5 :: rd 0000000000000001 rm 8000000000000000, rn 8000000000000000, cin 1, nzcv 30000000 CV |
| adcs w3, w4, w5 :: rd 0000000000004abe rm 0000000000003039, rn 0000000000001a85, cin 0, nzcv 00000000 |
| adcs w3, w4, w5 :: rd 0000000000004abf rm 0000000000003039, rn 0000000000001a85, cin 1, nzcv 00000000 |
| adcs w3, w4, w5 :: rd 00000000ffffffff rm 0000000000000000, rn 00000000ffffffff, cin 0, nzcv 80000000 N |
| adcs w3, w4, w5 :: rd 0000000000000000 rm 0000000000000000, rn 00000000ffffffff, cin 1, nzcv 60000000 ZC |
| adcs w3, w4, w5 :: rd 000000005859704f rm 0000000031415927, rn 0000000027181728, cin 0, nzcv 00000000 |
| adcs w3, w4, w5 :: rd 0000000058597050 rm 0000000031415927, rn 0000000027181728, cin 1, nzcv 00000000 |
| adcs w3, w4, w5 :: rd 0000000000000000 rm 0000000000000000, rn 0000000000000000, cin 0, nzcv 40000000 Z |
| adcs w3, w4, w5 :: rd 0000000000000001 rm 0000000000000000, rn 0000000000000000, cin 1, nzcv 00000000 |
| adcs w3, w4, w5 :: rd 0000000000000001 rm 0000000000000001, rn 0000000000000000, cin 0, nzcv 00000000 |
| adcs w3, w4, w5 :: rd 0000000000000002 rm 0000000000000001, rn 0000000000000000, cin 1, nzcv 00000000 |
| adcs w3, w4, w5 :: rd 0000000000000001 rm 0000000000000000, rn 0000000000000001, cin 0, nzcv 00000000 |
| adcs w3, w4, w5 :: rd 0000000000000002 rm 0000000000000000, rn 0000000000000001, cin 1, nzcv 00000000 |
| adcs w3, w4, w5 :: rd 0000000080000000 rm 0000000080000000, rn 0000000000000000, cin 0, nzcv 80000000 N |
| adcs w3, w4, w5 :: rd 0000000080000001 rm 0000000080000000, rn 0000000000000000, cin 1, nzcv 80000000 N |
| adcs w3, w4, w5 :: rd 0000000080000000 rm 0000000000000000, rn 0000000080000000, cin 0, nzcv 80000000 N |
| adcs w3, w4, w5 :: rd 0000000080000001 rm 0000000000000000, rn 0000000080000000, cin 1, nzcv 80000000 N |
| adcs w3, w4, w5 :: rd 0000000000000000 rm 0000000080000000, rn 0000000080000000, cin 0, nzcv 70000000 ZCV |
| adcs w3, w4, w5 :: rd 0000000000000001 rm 0000000080000000, rn 0000000080000000, cin 1, nzcv 30000000 CV |
| sbc x3, x4, x5 :: rd 00000000000015b3 rm 0000000000003039, rn 0000000000001a85, cin 0, nzcv 00000000 |
| sbc x3, x4, x5 :: rd 00000000000015b4 rm 0000000000003039, rn 0000000000001a85, cin 1, nzcv 20000000 C |
| sbc x3, x4, x5 :: rd 0000000000000000 rm 0000000000000000, rn ffffffffffffffff, cin 0, nzcv 00000000 |
| sbc x3, x4, x5 :: rd 0000000000000001 rm 0000000000000000, rn ffffffffffffffff, cin 1, nzcv 20000000 C |
| sbc x3, x4, x5 :: rd 0a2941feffffffff rm 3141592700000000, rn 2718172800000000, cin 0, nzcv 00000000 |
| sbc x3, x4, x5 :: rd 0a2941ff00000000 rm 3141592700000000, rn 2718172800000000, cin 1, nzcv 20000000 C |
| sbc x3, x4, x5 :: rd ffffffffffffffff rm 0000000000000000, rn 0000000000000000, cin 0, nzcv 00000000 |
| sbc x3, x4, x5 :: rd 0000000000000000 rm 0000000000000000, rn 0000000000000000, cin 1, nzcv 20000000 C |
| sbc x3, x4, x5 :: rd 00000000ffffffff rm 0000000100000000, rn 0000000000000000, cin 0, nzcv 00000000 |
| sbc x3, x4, x5 :: rd 0000000100000000 rm 0000000100000000, rn 0000000000000000, cin 1, nzcv 20000000 C |
| sbc x3, x4, x5 :: rd fffffffeffffffff rm 0000000000000000, rn 0000000100000000, cin 0, nzcv 00000000 |
| sbc x3, x4, x5 :: rd ffffffff00000000 rm 0000000000000000, rn 0000000100000000, cin 1, nzcv 20000000 C |
| sbc x3, x4, x5 :: rd 7fffffffffffffff rm 8000000000000000, rn 0000000000000000, cin 0, nzcv 00000000 |
| sbc x3, x4, x5 :: rd 8000000000000000 rm 8000000000000000, rn 0000000000000000, cin 1, nzcv 20000000 C |
| sbc x3, x4, x5 :: rd 7fffffffffffffff rm 0000000000000000, rn 8000000000000000, cin 0, nzcv 00000000 |
| sbc x3, x4, x5 :: rd 8000000000000000 rm 0000000000000000, rn 8000000000000000, cin 1, nzcv 20000000 C |
| sbc x3, x4, x5 :: rd ffffffffffffffff rm 8000000000000000, rn 8000000000000000, cin 0, nzcv 00000000 |
| sbc x3, x4, x5 :: rd 0000000000000000 rm 8000000000000000, rn 8000000000000000, cin 1, nzcv 20000000 C |
| sbc w3, w4, w5 :: rd 00000000000015b3 rm 0000000000003039, rn 0000000000001a85, cin 0, nzcv 00000000 |
| sbc w3, w4, w5 :: rd 00000000000015b4 rm 0000000000003039, rn 0000000000001a85, cin 1, nzcv 20000000 C |
| sbc w3, w4, w5 :: rd 0000000000000000 rm 0000000000000000, rn 00000000ffffffff, cin 0, nzcv 00000000 |
| sbc w3, w4, w5 :: rd 0000000000000001 rm 0000000000000000, rn 00000000ffffffff, cin 1, nzcv 20000000 C |
| sbc w3, w4, w5 :: rd 000000000a2941fe rm 0000000031415927, rn 0000000027181728, cin 0, nzcv 00000000 |
| sbc w3, w4, w5 :: rd 000000000a2941ff rm 0000000031415927, rn 0000000027181728, cin 1, nzcv 20000000 C |
| sbc w3, w4, w5 :: rd 00000000ffffffff rm 0000000000000000, rn 0000000000000000, cin 0, nzcv 00000000 |
| sbc w3, w4, w5 :: rd 0000000000000000 rm 0000000000000000, rn 0000000000000000, cin 1, nzcv 20000000 C |
| sbc w3, w4, w5 :: rd 0000000000000000 rm 0000000000000001, rn 0000000000000000, cin 0, nzcv 00000000 |
| sbc w3, w4, w5 :: rd 0000000000000001 rm 0000000000000001, rn 0000000000000000, cin 1, nzcv 20000000 C |
| sbc w3, w4, w5 :: rd 00000000fffffffe rm 0000000000000000, rn 0000000000000001, cin 0, nzcv 00000000 |
| sbc w3, w4, w5 :: rd 00000000ffffffff rm 0000000000000000, rn 0000000000000001, cin 1, nzcv 20000000 C |
| sbc w3, w4, w5 :: rd 000000007fffffff rm 0000000080000000, rn 0000000000000000, cin 0, nzcv 00000000 |
| sbc w3, w4, w5 :: rd 0000000080000000 rm 0000000080000000, rn 0000000000000000, cin 1, nzcv 20000000 C |
| sbc w3, w4, w5 :: rd 000000007fffffff rm 0000000000000000, rn 0000000080000000, cin 0, nzcv 00000000 |
| sbc w3, w4, w5 :: rd 0000000080000000 rm 0000000000000000, rn 0000000080000000, cin 1, nzcv 20000000 C |
| sbc w3, w4, w5 :: rd 00000000ffffffff rm 0000000080000000, rn 0000000080000000, cin 0, nzcv 00000000 |
| sbc w3, w4, w5 :: rd 0000000000000000 rm 0000000080000000, rn 0000000080000000, cin 1, nzcv 20000000 C |
| sbcs x3, x4, x5 :: rd 00000000000015b3 rm 0000000000003039, rn 0000000000001a85, cin 0, nzcv 20000000 C |
| sbcs x3, x4, x5 :: rd 00000000000015b4 rm 0000000000003039, rn 0000000000001a85, cin 1, nzcv 20000000 C |
| sbcs x3, x4, x5 :: rd 0000000000000000 rm 0000000000000000, rn ffffffffffffffff, cin 0, nzcv 40000000 Z |
| sbcs x3, x4, x5 :: rd 0000000000000001 rm 0000000000000000, rn ffffffffffffffff, cin 1, nzcv 00000000 |
| sbcs x3, x4, x5 :: rd 0a2941feffffffff rm 3141592700000000, rn 2718172800000000, cin 0, nzcv 20000000 C |
| sbcs x3, x4, x5 :: rd 0a2941ff00000000 rm 3141592700000000, rn 2718172800000000, cin 1, nzcv 20000000 C |
| sbcs x3, x4, x5 :: rd ffffffffffffffff rm 0000000000000000, rn 0000000000000000, cin 0, nzcv 80000000 N |
| sbcs x3, x4, x5 :: rd 0000000000000000 rm 0000000000000000, rn 0000000000000000, cin 1, nzcv 60000000 ZC |
| sbcs x3, x4, x5 :: rd 00000000ffffffff rm 0000000100000000, rn 0000000000000000, cin 0, nzcv 20000000 C |
| sbcs x3, x4, x5 :: rd 0000000100000000 rm 0000000100000000, rn 0000000000000000, cin 1, nzcv 20000000 C |
| sbcs x3, x4, x5 :: rd fffffffeffffffff rm 0000000000000000, rn 0000000100000000, cin 0, nzcv 80000000 N |
| sbcs x3, x4, x5 :: rd ffffffff00000000 rm 0000000000000000, rn 0000000100000000, cin 1, nzcv 80000000 N |
| sbcs x3, x4, x5 :: rd 7fffffffffffffff rm 8000000000000000, rn 0000000000000000, cin 0, nzcv 30000000 CV |
| sbcs x3, x4, x5 :: rd 8000000000000000 rm 8000000000000000, rn 0000000000000000, cin 1, nzcv a0000000 N C |
| sbcs x3, x4, x5 :: rd 7fffffffffffffff rm 0000000000000000, rn 8000000000000000, cin 0, nzcv 00000000 |
| sbcs x3, x4, x5 :: rd 8000000000000000 rm 0000000000000000, rn 8000000000000000, cin 1, nzcv 90000000 N V |
| sbcs x3, x4, x5 :: rd ffffffffffffffff rm 8000000000000000, rn 8000000000000000, cin 0, nzcv 80000000 N |
| sbcs x3, x4, x5 :: rd 0000000000000000 rm 8000000000000000, rn 8000000000000000, cin 1, nzcv 60000000 ZC |
| sbcs w3, w4, w5 :: rd 00000000000015b3 rm 0000000000003039, rn 0000000000001a85, cin 0, nzcv 20000000 C |
| sbcs w3, w4, w5 :: rd 00000000000015b4 rm 0000000000003039, rn 0000000000001a85, cin 1, nzcv 20000000 C |
| sbcs w3, w4, w5 :: rd 0000000000000000 rm 0000000000000000, rn 00000000ffffffff, cin 0, nzcv 40000000 Z |
| sbcs w3, w4, w5 :: rd 0000000000000001 rm 0000000000000000, rn 00000000ffffffff, cin 1, nzcv 00000000 |
| sbcs w3, w4, w5 :: rd 000000000a2941fe rm 0000000031415927, rn 0000000027181728, cin 0, nzcv 20000000 C |
| sbcs w3, w4, w5 :: rd 000000000a2941ff rm 0000000031415927, rn 0000000027181728, cin 1, nzcv 20000000 C |
| sbcs w3, w4, w5 :: rd 00000000ffffffff rm 0000000000000000, rn 0000000000000000, cin 0, nzcv 80000000 N |
| sbcs w3, w4, w5 :: rd 0000000000000000 rm 0000000000000000, rn 0000000000000000, cin 1, nzcv 60000000 ZC |
| sbcs w3, w4, w5 :: rd 0000000000000000 rm 0000000000000001, rn 0000000000000000, cin 0, nzcv 60000000 ZC |
| sbcs w3, w4, w5 :: rd 0000000000000001 rm 0000000000000001, rn 0000000000000000, cin 1, nzcv 20000000 C |
| sbcs w3, w4, w5 :: rd 00000000fffffffe rm 0000000000000000, rn 0000000000000001, cin 0, nzcv 80000000 N |
| sbcs w3, w4, w5 :: rd 00000000ffffffff rm 0000000000000000, rn 0000000000000001, cin 1, nzcv 80000000 N |
| sbcs w3, w4, w5 :: rd 000000007fffffff rm 0000000080000000, rn 0000000000000000, cin 0, nzcv 30000000 CV |
| sbcs w3, w4, w5 :: rd 0000000080000000 rm 0000000080000000, rn 0000000000000000, cin 1, nzcv a0000000 N C |
| sbcs w3, w4, w5 :: rd 000000007fffffff rm 0000000000000000, rn 0000000080000000, cin 0, nzcv 00000000 |
| sbcs w3, w4, w5 :: rd 0000000080000000 rm 0000000000000000, rn 0000000080000000, cin 1, nzcv 90000000 N V |
| sbcs w3, w4, w5 :: rd 00000000ffffffff rm 0000000080000000, rn 0000000080000000, cin 0, nzcv 80000000 N |
| sbcs w3, w4, w5 :: rd 0000000000000000 rm 0000000080000000, rn 0000000080000000, cin 1, nzcv 60000000 ZC |
| bfm x2, x4, #0, #63 :: rd 5555555555555555 rn 5555555555555555, cin 0, nzcv 00000000 |
| bfm x2, x4, #0, #63 :: rd aaaaaaaaaaaaaaaa rn aaaaaaaaaaaaaaaa, cin 0, nzcv 00000000 |
| cmp x4, x5 ; cset x3, ne :: rd 0000000000000001 rm 0000000000003039, rn 0000000000001a85, cin 0, nzcv 20000000 C |
| cmp x4, x5 ; cset x3, eq :: rd 0000000000000000 rm 0000000000003039, rn 0000000000001a85, cin 0, nzcv 20000000 C |
| cmp w4, w5 ; cset x3, ne :: rd 0000000000000000 rm 000000ab12345678, rn 000000cd12345678, cin 0, nzcv 60000000 ZC |
| cmp w4, w5 ; cset x3, eq :: rd 0000000000000000 rm 000000cd12345678, rn 000000cd12345670, cin 0, nzcv 20000000 C |
| cmp x4, x5 ; mrs x3, nzcv :: rd 0000000020000000 rm db432311d1e3a1d0, rn a6325ae016fbd710, cin 0, nzcv 20000000 C |
| cmp x4, x5 ; mrs x3, nzcv :: rd 0000000000000000 rm 192e7217e1ab63b0, rn fd370f11bfcd4a4a, cin 0, nzcv 00000000 |
| cmp x4, x5 ; mrs x3, nzcv :: rd 00000000a0000000 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv a0000000 N C |
| cmp x4, x5 ; mrs x3, nzcv :: rd 0000000080000000 rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 80000000 N |
| cmp x4, x5 ; mrs x3, nzcv :: rd 00000000a0000000 rm e51579fec3892795, rn 507865169b052546, cin 0, nzcv a0000000 N C |
| cmp x4, x5 ; mrs x3, nzcv :: rd 0000000090000000 rm 1b834ed5b21de6b5, rn 9a1140d0fd1dbf6c, cin 0, nzcv 90000000 N V |
| cmp x4, x5 ; mrs x3, nzcv :: rd 0000000000000000 rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 00000000 |
| cmp x4, x5 ; mrs x3, nzcv :: rd 00000000a0000000 rm fc9a9d8be2434f5e, rn 6a13f7db3dfa4a3f, cin 0, nzcv a0000000 N C |
| cmp x4, x5 ; mrs x3, nzcv :: rd 0000000020000000 rm d98d2022a9b876ab, rn a7e754e8ff3a554e, cin 0, nzcv 20000000 C |
| cmp x4, x5 ; mrs x3, nzcv :: rd 0000000080000000 rm 33566e6515990527, rn 3d7e7390195d82e2, cin 0, nzcv 80000000 N |
| cmp x4, x5 ; mrs x3, nzcv :: rd 0000000020000000 rm e57b3a514f5207f4, rn 8ef7bac0f0ac903a, cin 0, nzcv 20000000 C |
| cmp x4, x5 ; mrs x3, nzcv :: rd 0000000080000000 rm 9d4a481b12743bf8, rn 9f014e8d2644ee47, cin 0, nzcv 80000000 N |
| cmp x4, x5 ; mrs x3, nzcv :: rd 00000000a0000000 rm efdd33d64e6d6a8b, rn 44e875422d202c19, cin 0, nzcv a0000000 N C |
| cmp x4, x5 ; mrs x3, nzcv :: rd 0000000020000000 rm 5c6c9b2a7f109f5b, rn 568ee275e665f075, cin 0, nzcv 20000000 C |
| cmp x4, x5 ; mrs x3, nzcv :: rd 0000000030000000 rm 9b14b0a4fbbd2c11, rn 6b5bac44aaa93980, cin 0, nzcv 30000000 CV |
| cmp x4, x5 ; mrs x3, nzcv :: rd 0000000000000000 rm 2e01dd24f43ab651, rn e7d992b63e93eed4, cin 0, nzcv 00000000 |
| cmp x4, x5 ; mrs x3, nzcv :: rd 0000000020000000 rm f51464d0135fb75c, rn cb60e536ad0b94e9, cin 0, nzcv 20000000 C |
| cmp x4, x5 ; mrs x3, nzcv :: rd 0000000080000000 rm ca38ffb7de3bd6b0, rn eef048dd9ed9490c, cin 0, nzcv 80000000 N |
| cmp x4, x5 ; mrs x3, nzcv :: rd 0000000000000000 rm 54ec6fe1530c7d86, rn e7aa4d6f69edb5d0, cin 0, nzcv 00000000 |
| cmp x4, x5 ; mrs x3, nzcv :: rd 0000000080000000 rm 401b30e3b8b5d629, rn 635a5c613cdb7919, cin 0, nzcv 80000000 N |
| cmp w4, w5 ; mrs x3, nzcv :: rd 00000000a0000000 rm db432311d1e3a1d0, rn a6325ae016fbd710, cin 0, nzcv a0000000 N C |
| cmp w4, w5 ; mrs x3, nzcv :: rd 0000000020000000 rm 192e7217e1ab63b0, rn fd370f11bfcd4a4a, cin 0, nzcv 20000000 C |
| cmp w4, w5 ; mrs x3, nzcv :: rd 00000000a0000000 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv a0000000 N C |
| cmp w4, w5 ; mrs x3, nzcv :: rd 0000000080000000 rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 80000000 N |
| cmp w4, w5 ; mrs x3, nzcv :: rd 0000000020000000 rm e51579fec3892795, rn 507865169b052546, cin 0, nzcv 20000000 C |
| cmp w4, w5 ; mrs x3, nzcv :: rd 0000000080000000 rm 1b834ed5b21de6b5, rn 9a1140d0fd1dbf6c, cin 0, nzcv 80000000 N |
| cmp w4, w5 ; mrs x3, nzcv :: rd 0000000020000000 rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 20000000 C |
| cmp w4, w5 ; mrs x3, nzcv :: rd 00000000a0000000 rm fc9a9d8be2434f5e, rn 6a13f7db3dfa4a3f, cin 0, nzcv a0000000 N C |
| cmp w4, w5 ; mrs x3, nzcv :: rd 0000000080000000 rm d98d2022a9b876ab, rn a7e754e8ff3a554e, cin 0, nzcv 80000000 N |
| cmp w4, w5 ; mrs x3, nzcv :: rd 0000000080000000 rm 33566e6515990527, rn 3d7e7390195d82e2, cin 0, nzcv 80000000 N |
| cmp w4, w5 ; mrs x3, nzcv :: rd 0000000000000000 rm e57b3a514f5207f4, rn 8ef7bac0f0ac903a, cin 0, nzcv 00000000 |
| cmp w4, w5 ; mrs x3, nzcv :: rd 0000000080000000 rm 9d4a481b12743bf8, rn 9f014e8d2644ee47, cin 0, nzcv 80000000 N |
| cmp w4, w5 ; mrs x3, nzcv :: rd 0000000020000000 rm efdd33d64e6d6a8b, rn 44e875422d202c19, cin 0, nzcv 20000000 C |
| cmp w4, w5 ; mrs x3, nzcv :: rd 0000000090000000 rm 5c6c9b2a7f109f5b, rn 568ee275e665f075, cin 0, nzcv 90000000 N V |
| cmp w4, w5 ; mrs x3, nzcv :: rd 0000000020000000 rm 9b14b0a4fbbd2c11, rn 6b5bac44aaa93980, cin 0, nzcv 20000000 C |
| cmp w4, w5 ; mrs x3, nzcv :: rd 00000000a0000000 rm 2e01dd24f43ab651, rn e7d992b63e93eed4, cin 0, nzcv a0000000 N C |
| cmp w4, w5 ; mrs x3, nzcv :: rd 0000000000000000 rm f51464d0135fb75c, rn cb60e536ad0b94e9, cin 0, nzcv 00000000 |
| cmp w4, w5 ; mrs x3, nzcv :: rd 0000000020000000 rm ca38ffb7de3bd6b0, rn eef048dd9ed9490c, cin 0, nzcv 20000000 C |
| cmp w4, w5 ; mrs x3, nzcv :: rd 0000000080000000 rm 54ec6fe1530c7d86, rn e7aa4d6f69edb5d0, cin 0, nzcv 80000000 N |
| cmp w4, w5 ; mrs x3, nzcv :: rd 0000000030000000 rm 401b30e3b8b5d629, rn 635a5c613cdb7919, cin 0, nzcv 30000000 CV |
| ADD imm12 |
| add x3, x4, #0x876, lsl #0 :: rd 5555555555555dcb rn 5555555555555555, cin 0, nzcv 00000000 |
| add x3, x4, #0x876, lsl #0 :: rd 0000000000000875 rn ffffffffffffffff, cin 0, nzcv 00000000 |
| add x3, x4, #0x876, lsl #12 :: rd 5555555555dcb555 rn 5555555555555555, cin 0, nzcv 00000000 |
| add x3, x4, #0x876, lsl #12 :: rd 0000000000875fff rn ffffffffffffffff, cin 0, nzcv 00000000 |
| add w3, w4, #0x876, lsl #0 :: rd 0000000055555dcb rn 5555555555555555, cin 0, nzcv 00000000 |
| add w3, w4, #0x876, lsl #0 :: rd 0000000000000875 rn ffffffffffffffff, cin 0, nzcv 00000000 |
| add w3, w4, #0x876, lsl #12 :: rd 0000000055dcb555 rn 5555555555555555, cin 0, nzcv 00000000 |
| add w3, w4, #0x876, lsl #12 :: rd 0000000000875fff rn ffffffffffffffff, cin 0, nzcv 00000000 |
| adds x3, x4, #0x876, lsl #0 :: rd 5555555555555dcb rn 5555555555555555, cin 0, nzcv 00000000 |
| adds x3, x4, #0x876, lsl #0 :: rd 0000000000000875 rn ffffffffffffffff, cin 0, nzcv 20000000 C |
| adds x3, x4, #0x876, lsl #12 :: rd 5555555555dcb555 rn 5555555555555555, cin 0, nzcv 00000000 |
| adds x3, x4, #0x876, lsl #12 :: rd 0000000000875fff rn ffffffffffffffff, cin 0, nzcv 20000000 C |
| adds w3, w4, #0x876, lsl #0 :: rd 0000000055555dcb rn 5555555555555555, cin 0, nzcv 00000000 |
| adds w3, w4, #0x876, lsl #0 :: rd 0000000000000875 rn ffffffffffffffff, cin 0, nzcv 20000000 C |
| adds w3, w4, #0x876, lsl #12 :: rd 0000000055dcb555 rn 5555555555555555, cin 0, nzcv 00000000 |
| adds w3, w4, #0x876, lsl #12 :: rd 0000000000875fff rn ffffffffffffffff, cin 0, nzcv 20000000 C |
| adds x3, x4, #0xD87, lsl #0 :: rd c5446fe48c6118af rn c5446fe48c610b28, cin 0, nzcv 80000000 N |
| adds x3, x4, #0xD87, lsl #0 :: rd efdd33d64e6d7812 rn efdd33d64e6d6a8b, cin 0, nzcv 80000000 N |
| adds x3, x4, #0xD87, lsl #0 :: rd 8b0a4c8f910c2821 rn 8b0a4c8f910c1a9a, cin 0, nzcv 80000000 N |
| adds x3, x4, #0xD87, lsl #0 :: rd 5c6c9b2a7f10ace2 rn 5c6c9b2a7f109f5b, cin 0, nzcv 00000000 |
| adds x3, x4, #0xD87, lsl #0 :: rd 1f699b1d954a6844 rn 1f699b1d954a5abd, cin 0, nzcv 00000000 |
| adds x3, x4, #0xD87, lsl #0 :: rd 9b14b0a4fbbd3998 rn 9b14b0a4fbbd2c11, cin 0, nzcv 80000000 N |
| adds x3, x4, #0xD87, lsl #0 :: rd d55d1c942f952ce5 rn d55d1c942f951f5e, cin 0, nzcv 80000000 N |
| adds x3, x4, #0xD87, lsl #0 :: rd 31d5b14395d5b2c1 rn 31d5b14395d5a53a, cin 0, nzcv 00000000 |
| adds x3, x4, #0xD87, lsl #0 :: rd 2e01dd24f43ac3d8 rn 2e01dd24f43ab651, cin 0, nzcv 00000000 |
| adds x3, x4, #0xD87, lsl #0 :: rd f44e040002468590 rn f44e040002467809, cin 0, nzcv 80000000 N |
| adds x3, x4, #0xD87, lsl #0 :: rd 843fdf81027786f5 rn 843fdf810277796e, cin 0, nzcv 80000000 N |
| adds x3, x4, #0xD87, lsl #0 :: rd 64d24626922b55f3 rn 64d24626922b486c, cin 0, nzcv 00000000 |
| adds w3, w4, #0xD87, lsl #0 :: rd 000000008c6118af rn c5446fe48c610b28, cin 0, nzcv 80000000 N |
| adds w3, w4, #0xD87, lsl #0 :: rd 000000004e6d7812 rn efdd33d64e6d6a8b, cin 0, nzcv 00000000 |
| adds w3, w4, #0xD87, lsl #0 :: rd 00000000910c2821 rn 8b0a4c8f910c1a9a, cin 0, nzcv 80000000 N |
| adds w3, w4, #0xD87, lsl #0 :: rd 000000007f10ace2 rn 5c6c9b2a7f109f5b, cin 0, nzcv 00000000 |
| adds w3, w4, #0xD87, lsl #0 :: rd 00000000954a6844 rn 1f699b1d954a5abd, cin 0, nzcv 80000000 N |
| adds w3, w4, #0xD87, lsl #0 :: rd 00000000fbbd3998 rn 9b14b0a4fbbd2c11, cin 0, nzcv 80000000 N |
| adds w3, w4, #0xD87, lsl #0 :: rd 000000002f952ce5 rn d55d1c942f951f5e, cin 0, nzcv 00000000 |
| adds w3, w4, #0xD87, lsl #0 :: rd 0000000095d5b2c1 rn 31d5b14395d5a53a, cin 0, nzcv 80000000 N |
| adds w3, w4, #0xD87, lsl #0 :: rd 00000000f43ac3d8 rn 2e01dd24f43ab651, cin 0, nzcv 80000000 N |
| adds w3, w4, #0xD87, lsl #0 :: rd 0000000002468590 rn f44e040002467809, cin 0, nzcv 00000000 |
| adds w3, w4, #0xD87, lsl #0 :: rd 00000000027786f5 rn 843fdf810277796e, cin 0, nzcv 00000000 |
| adds w3, w4, #0xD87, lsl #0 :: rd 00000000922b55f3 rn 64d24626922b486c, cin 0, nzcv 80000000 N |
| SUB imm12 |
| sub w3, w4, #0x876, lsl #0 :: rd 0000000055554cdf rn 5555555555555555, cin 0, nzcv 00000000 |
| sub w3, w4, #0x876, lsl #0 :: rd 00000000fffff789 rn ffffffffffffffff, cin 0, nzcv 00000000 |
| sub w3, w4, #0x876, lsl #12 :: rd 0000000054cdf555 rn 5555555555555555, cin 0, nzcv 00000000 |
| sub w3, w4, #0x876, lsl #12 :: rd 00000000ff789fff rn ffffffffffffffff, cin 0, nzcv 00000000 |
| sub w3, w4, #0x876, lsl #0 :: rd 0000000055554cdf rn 5555555555555555, cin 0, nzcv 00000000 |
| sub w3, w4, #0x876, lsl #0 :: rd 00000000fffff789 rn ffffffffffffffff, cin 0, nzcv 00000000 |
| sub w3, w4, #0x876, lsl #12 :: rd 0000000054cdf555 rn 5555555555555555, cin 0, nzcv 00000000 |
| sub w3, w4, #0x876, lsl #12 :: rd 00000000ff789fff rn ffffffffffffffff, cin 0, nzcv 00000000 |
| subs w3, w4, #0x876, lsl #0 :: rd 0000000055554cdf rn 5555555555555555, cin 0, nzcv 20000000 C |
| subs w3, w4, #0x876, lsl #0 :: rd 00000000fffff789 rn ffffffffffffffff, cin 0, nzcv a0000000 N C |
| subs w3, w4, #0x876, lsl #12 :: rd 0000000054cdf555 rn 5555555555555555, cin 0, nzcv 20000000 C |
| subs w3, w4, #0x876, lsl #12 :: rd 00000000ff789fff rn ffffffffffffffff, cin 0, nzcv a0000000 N C |
| subs w3, w4, #0x876, lsl #0 :: rd 0000000055554cdf rn 5555555555555555, cin 0, nzcv 20000000 C |
| subs w3, w4, #0x876, lsl #0 :: rd 00000000fffff789 rn ffffffffffffffff, cin 0, nzcv a0000000 N C |
| subs w3, w4, #0x876, lsl #12 :: rd 0000000054cdf555 rn 5555555555555555, cin 0, nzcv 20000000 C |
| subs w3, w4, #0x876, lsl #12 :: rd 00000000ff789fff rn ffffffffffffffff, cin 0, nzcv a0000000 N C |
| subs x3, x4, #0xD87, lsl #0 :: rd c5446fe48c60fda1 rn c5446fe48c610b28, cin 0, nzcv a0000000 N C |
| subs x3, x4, #0xD87, lsl #0 :: rd efdd33d64e6d5d04 rn efdd33d64e6d6a8b, cin 0, nzcv a0000000 N C |
| subs x3, x4, #0xD87, lsl #0 :: rd 8b0a4c8f910c0d13 rn 8b0a4c8f910c1a9a, cin 0, nzcv a0000000 N C |
| subs x3, x4, #0xD87, lsl #0 :: rd 5c6c9b2a7f1091d4 rn 5c6c9b2a7f109f5b, cin 0, nzcv 20000000 C |
| subs x3, x4, #0xD87, lsl #0 :: rd 1f699b1d954a4d36 rn 1f699b1d954a5abd, cin 0, nzcv 20000000 C |
| subs x3, x4, #0xD87, lsl #0 :: rd 9b14b0a4fbbd1e8a rn 9b14b0a4fbbd2c11, cin 0, nzcv a0000000 N C |
| subs x3, x4, #0xD87, lsl #0 :: rd d55d1c942f9511d7 rn d55d1c942f951f5e, cin 0, nzcv a0000000 N C |
| subs x3, x4, #0xD87, lsl #0 :: rd 31d5b14395d597b3 rn 31d5b14395d5a53a, cin 0, nzcv 20000000 C |
| subs x3, x4, #0xD87, lsl #0 :: rd 2e01dd24f43aa8ca rn 2e01dd24f43ab651, cin 0, nzcv 20000000 C |
| subs x3, x4, #0xD87, lsl #0 :: rd f44e040002466a82 rn f44e040002467809, cin 0, nzcv a0000000 N C |
| subs x3, x4, #0xD87, lsl #0 :: rd 843fdf8102776be7 rn 843fdf810277796e, cin 0, nzcv a0000000 N C |
| subs x3, x4, #0xD87, lsl #0 :: rd 64d24626922b3ae5 rn 64d24626922b486c, cin 0, nzcv 20000000 C |
| subs w3, w4, #0xD87, lsl #0 :: rd 000000008c60fda1 rn c5446fe48c610b28, cin 0, nzcv a0000000 N C |
| subs w3, w4, #0xD87, lsl #0 :: rd 000000004e6d5d04 rn efdd33d64e6d6a8b, cin 0, nzcv 20000000 C |
| subs w3, w4, #0xD87, lsl #0 :: rd 00000000910c0d13 rn 8b0a4c8f910c1a9a, cin 0, nzcv a0000000 N C |
| subs w3, w4, #0xD87, lsl #0 :: rd 000000007f1091d4 rn 5c6c9b2a7f109f5b, cin 0, nzcv 20000000 C |
| subs w3, w4, #0xD87, lsl #0 :: rd 00000000954a4d36 rn 1f699b1d954a5abd, cin 0, nzcv a0000000 N C |
| subs w3, w4, #0xD87, lsl #0 :: rd 00000000fbbd1e8a rn 9b14b0a4fbbd2c11, cin 0, nzcv a0000000 N C |
| subs w3, w4, #0xD87, lsl #0 :: rd 000000002f9511d7 rn d55d1c942f951f5e, cin 0, nzcv 20000000 C |
| subs w3, w4, #0xD87, lsl #0 :: rd 0000000095d597b3 rn 31d5b14395d5a53a, cin 0, nzcv a0000000 N C |
| subs w3, w4, #0xD87, lsl #0 :: rd 00000000f43aa8ca rn 2e01dd24f43ab651, cin 0, nzcv a0000000 N C |
| subs w3, w4, #0xD87, lsl #0 :: rd 0000000002466a82 rn f44e040002467809, cin 0, nzcv 20000000 C |
| subs w3, w4, #0xD87, lsl #0 :: rd 0000000002776be7 rn 843fdf810277796e, cin 0, nzcv 20000000 C |
| subs w3, w4, #0xD87, lsl #0 :: rd 00000000922b3ae5 rn 64d24626922b486c, cin 0, nzcv a0000000 N C |
| subs w3, w4, #0xD87, lsl #0 :: rd 00000000ffffffff rn 64d2462600000d86, cin 0, nzcv 80000000 N |
| subs w3, w4, #0xD87, lsl #0 :: rd 0000000000000000 rn 64d2462600000d87, cin 0, nzcv 60000000 ZC |
| subs w3, w4, #0xD87, lsl #0 :: rd 0000000000000001 rn 64d2462600000d88, cin 0, nzcv 20000000 C |
| subs w3, w4, #0xD87, lsl #0 :: rd 000000007fffffff rn 64d2462680000d86, cin 0, nzcv 30000000 CV |
| subs w3, w4, #0xD87, lsl #0 :: rd 0000000080000000 rn 64d2462680000d87, cin 0, nzcv a0000000 N C |
| subs w3, w4, #0xD87, lsl #0 :: rd 0000000080000001 rn 64d2462680000d88, cin 0, nzcv a0000000 N C |
| subs x3, x4, #0xD87, lsl #0 :: rd ffffffffffffffff rn 0000000000000d86, cin 0, nzcv 80000000 N |
| subs x3, x4, #0xD87, lsl #0 :: rd 0000000000000000 rn 0000000000000d87, cin 0, nzcv 60000000 ZC |
| subs x3, x4, #0xD87, lsl #0 :: rd 0000000000000001 rn 0000000000000d88, cin 0, nzcv 20000000 C |
| subs x3, x4, #0xD87, lsl #0 :: rd 7fffffffffffffff rn 8000000000000d86, cin 0, nzcv 30000000 CV |
| subs x3, x4, #0xD87, lsl #0 :: rd 8000000000000000 rn 8000000000000d87, cin 0, nzcv a0000000 N C |
| subs x3, x4, #0xD87, lsl #0 :: rd 8000000000000001 rn 8000000000000d88, cin 0, nzcv a0000000 N C |
| ADR/ADRP MISSING (results are PC dependant) |
| AND(imm) |
| and x3,x4, #0xF :: rd 0000000000000005 rn 5555555555555555, cin 0, nzcv 00000000 |
| and x3,x4, #0x8080808080808080 :: rd 8000808000000000 rn 843fdf810277796e, cin 0, nzcv 00000000 |
| and x3,x4, #0xC0C0C0C0C0C0C0C0 :: rd c04040c080400000 rn c5446fe48c610b28, cin 0, nzcv 00000000 |
| ands x3,x4, #0x8080808080808080 :: rd 8000808000000000 rn 843fdf810277796e, cin 0, nzcv 80000000 N |
| ands x3,x4, #0xC0C0C0C0C0C0C0C0 :: rd c04040c080400000 rn c5446fe48c610b28, cin 0, nzcv 80000000 N |
| ands x3,x4, #0x8080808080808080 :: rd 0000808000000000 rn 143fdf810277796e, cin 0, nzcv 00000000 |
| ands x3,x4, #0xC0C0C0C0C0C0C0C0 :: rd 804040c080400000 rn a5446fe48c610b28, cin 0, nzcv 80000000 N |
| ands x3,x4, #0x8080808080808080 :: rd 0000000000000000 rn 7070707070707070, cin 0, nzcv 40000000 Z |
| ands x3,x4, #0x8080808080808080 :: rd 8000000000000000 rn f070707070707070, cin 0, nzcv 80000000 N |
| and w3,w4, #0xF :: rd 0000000000000005 rn 5555555555555555, cin 0, nzcv 00000000 |
| and w3,w4, #0x80808080 :: rd 0000000000000000 rn 843fdf810277796e, cin 0, nzcv 00000000 |
| and w3,w4, #0xC0C0C0C0 :: rd 0000000080400000 rn c5446fe48c610b28, cin 0, nzcv 00000000 |
| ands w3,w4, #0x80808080 :: rd 0000000000000000 rn 843fdf810277796e, cin 0, nzcv 40000000 Z |
| ands w3,w4, #0xC0C0C0C0 :: rd 0000000080400000 rn c5446fe48c610b28, cin 0, nzcv 80000000 N |
| ands w3,w4, #0x80808080 :: rd 0000000000000000 rn 143fdf810277796e, cin 0, nzcv 40000000 Z |
| ands w3,w4, #0xC0C0C0C0 :: rd 0000000080400000 rn a5446fe48c610b28, cin 0, nzcv 80000000 N |
| ands w3,w4, #0x80808080 :: rd 0000000000000000 rn 7070707070707070, cin 0, nzcv 40000000 Z |
| ands w3,w4, #0x80808080 :: rd 0000000080000000 rn 70707070f0707070, cin 0, nzcv 80000000 N |
| ORR(imm) |
| orr x3,x4, #0xF :: rd 555555555555555f rn 5555555555555555, cin 0, nzcv 00000000 |
| orr x3,x4, #0x8080808080808080 :: rd 84bfdf8182f7f9ee rn 843fdf810277796e, cin 0, nzcv 00000000 |
| orr x3,x4, #0xC0C0C0C0C0C0C0C0 :: rd c5c4efe4cce1cbe8 rn c5446fe48c610b28, cin 0, nzcv 00000000 |
| orr w3,w4, #0xF :: rd 000000005555555f rn 5555555555555555, cin 0, nzcv 00000000 |
| orr w3,w4, #0x80808080 :: rd 0000000082f7f9ee rn 843fdf810277796e, cin 0, nzcv 00000000 |
| orr w3,w4, #0xC0C0C0C0 :: rd 00000000cce1cbe8 rn c5446fe48c610b28, cin 0, nzcv 00000000 |
| EOR(imm) |
| eor x3,x4, #0xF :: rd 555555555555555a rn 5555555555555555, cin 0, nzcv 00000000 |
| eor x3,x4, #0x8080808080808080 :: rd 04bf5f0182f7f9ee rn 843fdf810277796e, cin 0, nzcv 00000000 |
| eor x3,x4, #0xC0C0C0C0C0C0C0C0 :: rd 0584af244ca1cbe8 rn c5446fe48c610b28, cin 0, nzcv 00000000 |
| eor w3,w4, #0xF :: rd 000000005555555a rn 5555555555555555, cin 0, nzcv 00000000 |
| eor w3,w4, #0x80808080 :: rd 0000000082f7f9ee rn 843fdf810277796e, cin 0, nzcv 00000000 |
| eor w3,w4, #0xC0C0C0C0 :: rd 000000004ca1cbe8 rn c5446fe48c610b28, cin 0, nzcv 00000000 |
| MOVZ |
| movz x27, #0x987 :: rd 0000000000000987 cin 0, nzcv 00000000 |
| movz x27, #0x987, lsl #16 :: rd 0000000009870000 cin 0, nzcv 00000000 |
| movz x27, #0x987, lsl #32 :: rd 0000098700000000 cin 0, nzcv 00000000 |
| movz x27, #0x987, lsl #48 :: rd 0987000000000000 cin 0, nzcv 00000000 |
| MOVN |
| movn x27, #0x987 :: rd fffffffffffff678 cin 0, nzcv 00000000 |
| movn x27, #0x987, lsl #16 :: rd fffffffff678ffff cin 0, nzcv 00000000 |
| movn x27, #0x987, lsl #32 :: rd fffff678ffffffff cin 0, nzcv 00000000 |
| movn x27, #0x987, lsl #48 :: rd f678ffffffffffff cin 0, nzcv 00000000 |
| MOVK |
| movn x27, #0xdef, lsl #48 ; movk x27, #0x987, lsl #0 ; movk x27, #0xabc, lsl #32 ; movk x27, #0x5123, lsl #16 :: rd f2100abc51230987 cin 0, nzcv 00000000 |
| EXTR(64) |
| extr x3, x4, x5, #0 :: rd a6325ae016fbd710 rm db432311d1e3a1d0, rn a6325ae016fbd710, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #0 :: rd fd370f11bfcd4a4a rm 192e7217e1ab63b0, rn fd370f11bfcd4a4a, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #0 :: rd 5bc94f0d3ee4863a rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #0 :: rd e861540945421773 rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #0 :: rd 507865169b052546 rm e51579fec3892795, rn 507865169b052546, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #0 :: rd 9a1140d0fd1dbf6c rm 1b834ed5b21de6b5, rn 9a1140d0fd1dbf6c, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #1 :: rd 53192d700b7deb88 rm db432311d1e3a1d0, rn a6325ae016fbd710, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #1 :: rd 7e9b8788dfe6a525 rm 192e7217e1ab63b0, rn fd370f11bfcd4a4a, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #1 :: rd 2de4a7869f72431d rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #1 :: rd f430aa04a2a10bb9 rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #1 :: rd a83c328b4d8292a3 rm e51579fec3892795, rn 507865169b052546, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #1 :: rd cd08a0687e8edfb6 rm 1b834ed5b21de6b5, rn 9a1140d0fd1dbf6c, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #2 :: rd 298c96b805bef5c4 rm db432311d1e3a1d0, rn a6325ae016fbd710, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #2 :: rd 3f4dc3c46ff35292 rm 192e7217e1ab63b0, rn fd370f11bfcd4a4a, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #2 :: rd 16f253c34fb9218e rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #2 :: rd fa185502515085dc rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #2 :: rd 541e1945a6c14951 rm e51579fec3892795, rn 507865169b052546, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #2 :: rd 668450343f476fdb rm 1b834ed5b21de6b5, rn 9a1140d0fd1dbf6c, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #3 :: rd 14c64b5c02df7ae2 rm db432311d1e3a1d0, rn a6325ae016fbd710, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #3 :: rd 1fa6e1e237f9a949 rm 192e7217e1ab63b0, rn fd370f11bfcd4a4a, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #3 :: rd 0b7929e1a7dc90c7 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #3 :: rd fd0c2a8128a842ee rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #3 :: rd aa0f0ca2d360a4a8 rm e51579fec3892795, rn 507865169b052546, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #3 :: rd b342281a1fa3b7ed rm 1b834ed5b21de6b5, rn 9a1140d0fd1dbf6c, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #32 :: rd d1e3a1d0a6325ae0 rm db432311d1e3a1d0, rn a6325ae016fbd710, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #32 :: rd e1ab63b0fd370f11 rm 192e7217e1ab63b0, rn fd370f11bfcd4a4a, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #32 :: rd e550b4885bc94f0d rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #32 :: rd 2c6954dfe8615409 rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #32 :: rd c389279550786516 rm e51579fec3892795, rn 507865169b052546, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #32 :: rd b21de6b59a1140d0 rm 1b834ed5b21de6b5, rn 9a1140d0fd1dbf6c, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #60 :: rd b432311d1e3a1d0a rm db432311d1e3a1d0, rn a6325ae016fbd710, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #60 :: rd 92e7217e1ab63b0f rm 192e7217e1ab63b0, rn fd370f11bfcd4a4a, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #60 :: rd d79baaee550b4885 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #60 :: rd 58586ea2c6954dfe rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #60 :: rd 51579fec38927955 rm e51579fec3892795, rn 507865169b052546, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #60 :: rd b834ed5b21de6b59 rm 1b834ed5b21de6b5, rn 9a1140d0fd1dbf6c, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #61 :: rd da19188e8f1d0e85 rm db432311d1e3a1d0, rn a6325ae016fbd710, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #61 :: rd c97390bf0d5b1d87 rm 192e7217e1ab63b0, rn fd370f11bfcd4a4a, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #61 :: rd ebcdd5772a85a442 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #61 :: rd 2c2c3751634aa6ff rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #61 :: rd 28abcff61c493caa rm e51579fec3892795, rn 507865169b052546, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #61 :: rd dc1a76ad90ef35ac rm 1b834ed5b21de6b5, rn 9a1140d0fd1dbf6c, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #62 :: rd 6d0c8c47478e8742 rm db432311d1e3a1d0, rn a6325ae016fbd710, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #62 :: rd 64b9c85f86ad8ec3 rm 192e7217e1ab63b0, rn fd370f11bfcd4a4a, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #62 :: rd f5e6eabb9542d221 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #62 :: rd 16161ba8b1a5537f rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #62 :: rd 9455e7fb0e249e55 rm e51579fec3892795, rn 507865169b052546, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #62 :: rd 6e0d3b56c8779ad6 rm 1b834ed5b21de6b5, rn 9a1140d0fd1dbf6c, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #63 :: rd 56f8b273af81ea51 rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #63 :: rd f9353b17c4869ebc rm fc9a9d8be2434f5e, rn 6a13f7db3dfa4a3f, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #63 :: rd b31a40455370ed57 rm d98d2022a9b876ab, rn a7e754e8ff3a554e, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #63 :: rd 66acdcca2b320a4e rm 33566e6515990527, rn 3d7e7390195d82e2, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #63 :: rd caf674a29ea40fe9 rm e57b3a514f5207f4, rn 8ef7bac0f0ac903a, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #63 :: rd 3a94903624e877f1 rm 9d4a481b12743bf8, rn 9f014e8d2644ee47, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #63 :: rd dfba67ac9cdad516 rm efdd33d64e6d6a8b, rn 44e875422d202c19, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #63 :: rd b8d93654fe213eb6 rm 5c6c9b2a7f109f5b, rn 568ee275e665f075, cin 0, nzcv 00000000 |
| extr x3, x4, x5, #63 :: rd 36296149f77a5822 rm 9b14b0a4fbbd2c11, rn 6b5bac44aaa93980, cin 0, nzcv 00000000 |
| EXTR(32) |
| extr w3, w4, w5, #0 :: rd 0000000016fbd710 rm db432311d1e3a1d0, rn a6325ae016fbd710, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #0 :: rd 00000000bfcd4a4a rm 192e7217e1ab63b0, rn fd370f11bfcd4a4a, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #0 :: rd 000000003ee4863a rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #0 :: rd 0000000045421773 rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #0 :: rd 000000009b052546 rm e51579fec3892795, rn 507865169b052546, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #0 :: rd 00000000fd1dbf6c rm 1b834ed5b21de6b5, rn 9a1140d0fd1dbf6c, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #1 :: rd 000000000b7deb88 rm db432311d1e3a1d0, rn a6325ae016fbd710, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #1 :: rd 000000005fe6a525 rm 192e7217e1ab63b0, rn fd370f11bfcd4a4a, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #1 :: rd 000000001f72431d rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #1 :: rd 00000000a2a10bb9 rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #1 :: rd 00000000cd8292a3 rm e51579fec3892795, rn 507865169b052546, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #1 :: rd 00000000fe8edfb6 rm 1b834ed5b21de6b5, rn 9a1140d0fd1dbf6c, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #2 :: rd 0000000005bef5c4 rm db432311d1e3a1d0, rn a6325ae016fbd710, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #2 :: rd 000000002ff35292 rm 192e7217e1ab63b0, rn fd370f11bfcd4a4a, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #2 :: rd 000000000fb9218e rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #2 :: rd 00000000d15085dc rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #2 :: rd 0000000066c14951 rm e51579fec3892795, rn 507865169b052546, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #2 :: rd 000000007f476fdb rm 1b834ed5b21de6b5, rn 9a1140d0fd1dbf6c, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #3 :: rd 0000000002df7ae2 rm db432311d1e3a1d0, rn a6325ae016fbd710, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #3 :: rd 0000000017f9a949 rm 192e7217e1ab63b0, rn fd370f11bfcd4a4a, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #3 :: rd 0000000007dc90c7 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #3 :: rd 00000000e8a842ee rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #3 :: rd 00000000b360a4a8 rm e51579fec3892795, rn 507865169b052546, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #3 :: rd 00000000bfa3b7ed rm 1b834ed5b21de6b5, rn 9a1140d0fd1dbf6c, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #16 :: rd 00000000a1d016fb rm db432311d1e3a1d0, rn a6325ae016fbd710, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #16 :: rd 0000000063b0bfcd rm 192e7217e1ab63b0, rn fd370f11bfcd4a4a, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #16 :: rd 00000000b4883ee4 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #16 :: rd 0000000054df4542 rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #16 :: rd 0000000027959b05 rm e51579fec3892795, rn 507865169b052546, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #16 :: rd 00000000e6b5fd1d rm 1b834ed5b21de6b5, rn 9a1140d0fd1dbf6c, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #28 :: rd 000000001e3a1d01 rm db432311d1e3a1d0, rn a6325ae016fbd710, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #28 :: rd 000000001ab63b0b rm 192e7217e1ab63b0, rn fd370f11bfcd4a4a, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #28 :: rd 00000000550b4883 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #28 :: rd 00000000c6954df4 rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #28 :: rd 0000000038927959 rm e51579fec3892795, rn 507865169b052546, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #28 :: rd 0000000021de6b5f rm 1b834ed5b21de6b5, rn 9a1140d0fd1dbf6c, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #29 :: rd 000000008f1d0e80 rm db432311d1e3a1d0, rn a6325ae016fbd710, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #29 :: rd 000000000d5b1d85 rm 192e7217e1ab63b0, rn fd370f11bfcd4a4a, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #29 :: rd 000000002a85a441 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #29 :: rd 00000000634aa6fa rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #29 :: rd 000000001c493cac rm e51579fec3892795, rn 507865169b052546, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #29 :: rd 0000000090ef35af rm 1b834ed5b21de6b5, rn 9a1140d0fd1dbf6c, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #30 :: rd 00000000478e8740 rm db432311d1e3a1d0, rn a6325ae016fbd710, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #30 :: rd 0000000086ad8ec2 rm 192e7217e1ab63b0, rn fd370f11bfcd4a4a, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #30 :: rd 000000009542d220 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #30 :: rd 00000000b1a5537d rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #30 :: rd 000000000e249e56 rm e51579fec3892795, rn 507865169b052546, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #30 :: rd 00000000c8779ad7 rm 1b834ed5b21de6b5, rn 9a1140d0fd1dbf6c, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #31 :: rd 00000000af81ea51 rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #31 :: rd 00000000c4869ebc rm fc9a9d8be2434f5e, rn 6a13f7db3dfa4a3f, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #31 :: rd 000000005370ed57 rm d98d2022a9b876ab, rn a7e754e8ff3a554e, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #31 :: rd 000000002b320a4e rm 33566e6515990527, rn 3d7e7390195d82e2, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #31 :: rd 000000009ea40fe9 rm e57b3a514f5207f4, rn 8ef7bac0f0ac903a, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #31 :: rd 0000000024e877f0 rm 9d4a481b12743bf8, rn 9f014e8d2644ee47, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #31 :: rd 000000009cdad516 rm efdd33d64e6d6a8b, rn 44e875422d202c19, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #31 :: rd 00000000fe213eb7 rm 5c6c9b2a7f109f5b, rn 568ee275e665f075, cin 0, nzcv 00000000 |
| extr w3, w4, w5, #31 :: rd 00000000f77a5823 rm 9b14b0a4fbbd2c11, rn 6b5bac44aaa93980, cin 0, nzcv 00000000 |
| ADD/SUB(reg,64) |
| add x7,x8,x9,lsl #0 :: rd e2b4c9df7e23f68a rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 00000000 |
| add x7,x8,x9,lsl #1 :: rd d0c28d425e37e3dc rm fc9a9d8be2434f5e, rn 6a13f7db3dfa4a3f, cin 0, nzcv 00000000 |
| add x7,x8,x9,lsl #62 :: rd 598d2022a9b876ab rm d98d2022a9b876ab, rn a7e754e8ff3a554e, cin 0, nzcv 00000000 |
| add x7,x8,x9,lsl #63 :: rd 33566e6515990527 rm 33566e6515990527, rn 3d7e7390195d82e2, cin 0, nzcv 00000000 |
| adds x7,x8,x9,lsl #0 :: rd e2b4c9df7e23f68a rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 80000000 N |
| adds x7,x8,x9,lsl #1 :: rd d0c28d425e37e3dc rm fc9a9d8be2434f5e, rn 6a13f7db3dfa4a3f, cin 0, nzcv a0000000 N C |
| adds x7,x8,x9,lsl #62 :: rd 598d2022a9b876ab rm d98d2022a9b876ab, rn a7e754e8ff3a554e, cin 0, nzcv 30000000 CV |
| adds x7,x8,x9,lsl #63 :: rd 33566e6515990527 rm 33566e6515990527, rn 3d7e7390195d82e2, cin 0, nzcv 00000000 |
| adds x7,x8,x9,lsl #0 :: rd 0000000000000000 rm 5555555555555556, rn aaaaaaaaaaaaaaaa, cin 0, nzcv 60000000 ZC |
| add x7,x8,x9,lsr #0 :: rd e2b4c9df7e23f68a rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 00000000 |
| add x7,x8,x9,lsr #1 :: rd 31a499798140747d rm fc9a9d8be2434f5e, rn 6a13f7db3dfa4a3f, cin 0, nzcv 00000000 |
| add x7,x8,x9,lsr #62 :: rd d98d2022a9b876ad rm d98d2022a9b876ab, rn a7e754e8ff3a554e, cin 0, nzcv 00000000 |
| add x7,x8,x9,lsr #63 :: rd 33566e6515990527 rm 33566e6515990527, rn 3d7e7390195d82e2, cin 0, nzcv 00000000 |
| adds x7,x8,x9,lsr #0 :: rd e2b4c9df7e23f68a rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 80000000 N |
| adds x7,x8,x9,lsr #1 :: rd 31a499798140747d rm fc9a9d8be2434f5e, rn 6a13f7db3dfa4a3f, cin 0, nzcv 20000000 C |
| adds x7,x8,x9,lsr #62 :: rd d98d2022a9b876ad rm d98d2022a9b876ab, rn a7e754e8ff3a554e, cin 0, nzcv 80000000 N |
| adds x7,x8,x9,lsr #63 :: rd 33566e6515990527 rm 33566e6515990527, rn 3d7e7390195d82e2, cin 0, nzcv 00000000 |
| adds x7,x8,x9,lsr #0 :: rd 0000000000000000 rm 5555555555555556, rn aaaaaaaaaaaaaaaa, cin 0, nzcv 60000000 ZC |
| add x7,x8,x9,asr #0 :: rd e2b4c9df7e23f68a rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 00000000 |
| add x7,x8,x9,asr #1 :: rd 31a499798140747d rm fc9a9d8be2434f5e, rn 6a13f7db3dfa4a3f, cin 0, nzcv 00000000 |
| add x7,x8,x9,asr #62 :: rd d98d2022a9b876a9 rm d98d2022a9b876ab, rn a7e754e8ff3a554e, cin 0, nzcv 00000000 |
| add x7,x8,x9,asr #63 :: rd 33566e6515990527 rm 33566e6515990527, rn 3d7e7390195d82e2, cin 0, nzcv 00000000 |
| adds x7,x8,x9,asr #0 :: rd e2b4c9df7e23f68a rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 80000000 N |
| adds x7,x8,x9,asr #1 :: rd 31a499798140747d rm fc9a9d8be2434f5e, rn 6a13f7db3dfa4a3f, cin 0, nzcv 20000000 C |
| adds x7,x8,x9,asr #62 :: rd d98d2022a9b876a9 rm d98d2022a9b876ab, rn a7e754e8ff3a554e, cin 0, nzcv a0000000 N C |
| adds x7,x8,x9,asr #63 :: rd 33566e6515990527 rm 33566e6515990527, rn 3d7e7390195d82e2, cin 0, nzcv 00000000 |
| adds x7,x8,x9,asr #0 :: rd 0000000000000000 rm 5555555555555556, rn aaaaaaaaaaaaaaaa, cin 0, nzcv 60000000 ZC |
| sub x7,x8,x9,lsl #0 :: rd 7443e894315df3c6 rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 00000000 |
| sub x7,x8,x9,lsl #1 :: rd 2872add5664ebae0 rm fc9a9d8be2434f5e, rn 6a13f7db3dfa4a3f, cin 0, nzcv 00000000 |
| sub x7,x8,x9,lsl #62 :: rd 598d2022a9b876ab rm d98d2022a9b876ab, rn a7e754e8ff3a554e, cin 0, nzcv 00000000 |
| sub x7,x8,x9,lsl #63 :: rd 33566e6515990527 rm 33566e6515990527, rn 3d7e7390195d82e2, cin 0, nzcv 00000000 |
| subs x7,x8,x9,lsl #0 :: rd 7443e894315df3c6 rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 00000000 |
| subs x7,x8,x9,lsl #1 :: rd 2872add5664ebae0 rm fc9a9d8be2434f5e, rn 6a13f7db3dfa4a3f, cin 0, nzcv 20000000 C |
| subs x7,x8,x9,lsl #62 :: rd 598d2022a9b876ab rm d98d2022a9b876ab, rn a7e754e8ff3a554e, cin 0, nzcv 20000000 C |
| subs x7,x8,x9,lsl #63 :: rd 33566e6515990527 rm 33566e6515990527, rn 3d7e7390195d82e2, cin 0, nzcv 20000000 C |
| subs x7,x8,x9,lsl #0 :: rd aaaaaaaaaaaaaaac rm 5555555555555556, rn aaaaaaaaaaaaaaaa, cin 0, nzcv 90000000 N V |
| sub x7,x8,x9,lsr #0 :: rd 7443e894315df3c6 rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 00000000 |
| sub x7,x8,x9,lsr #1 :: rd c790a19e43462a3f rm fc9a9d8be2434f5e, rn 6a13f7db3dfa4a3f, cin 0, nzcv 00000000 |
| sub x7,x8,x9,lsr #62 :: rd d98d2022a9b876a9 rm d98d2022a9b876ab, rn a7e754e8ff3a554e, cin 0, nzcv 00000000 |
| sub x7,x8,x9,lsr #63 :: rd 33566e6515990527 rm 33566e6515990527, rn 3d7e7390195d82e2, cin 0, nzcv 00000000 |
| subs x7,x8,x9,lsr #0 :: rd 7443e894315df3c6 rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 00000000 |
| subs x7,x8,x9,lsr #1 :: rd c790a19e43462a3f rm fc9a9d8be2434f5e, rn 6a13f7db3dfa4a3f, cin 0, nzcv a0000000 N C |
| subs x7,x8,x9,lsr #62 :: rd d98d2022a9b876a9 rm d98d2022a9b876ab, rn a7e754e8ff3a554e, cin 0, nzcv a0000000 N C |
| subs x7,x8,x9,lsr #63 :: rd 33566e6515990527 rm 33566e6515990527, rn 3d7e7390195d82e2, cin 0, nzcv 20000000 C |
| subs x7,x8,x9,lsr #0 :: rd aaaaaaaaaaaaaaac rm 5555555555555556, rn aaaaaaaaaaaaaaaa, cin 0, nzcv 90000000 N V |
| sub x7,x8,x9,asr #0 :: rd 7443e894315df3c6 rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 00000000 |
| sub x7,x8,x9,asr #1 :: rd c790a19e43462a3f rm fc9a9d8be2434f5e, rn 6a13f7db3dfa4a3f, cin 0, nzcv 00000000 |
| sub x7,x8,x9,asr #62 :: rd d98d2022a9b876ad rm d98d2022a9b876ab, rn a7e754e8ff3a554e, cin 0, nzcv 00000000 |
| sub x7,x8,x9,asr #63 :: rd 33566e6515990527 rm 33566e6515990527, rn 3d7e7390195d82e2, cin 0, nzcv 00000000 |
| subs x7,x8,x9,asr #0 :: rd 7443e894315df3c6 rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 00000000 |
| subs x7,x8,x9,asr #1 :: rd c790a19e43462a3f rm fc9a9d8be2434f5e, rn 6a13f7db3dfa4a3f, cin 0, nzcv a0000000 N C |
| subs x7,x8,x9,asr #62 :: rd d98d2022a9b876ad rm d98d2022a9b876ab, rn a7e754e8ff3a554e, cin 0, nzcv 80000000 N |
| subs x7,x8,x9,asr #63 :: rd 33566e6515990527 rm 33566e6515990527, rn 3d7e7390195d82e2, cin 0, nzcv 20000000 C |
| subs x7,x8,x9,asr #0 :: rd 0000000000000000 rm 5555555555555555, rn 5555555555555555, cin 0, nzcv 60000000 ZC |
| subs x7,x8,x9,asr #0 :: rd 5555555555555555 rm aaaaaaaaaaaaaaaa, rn 5555555555555555, cin 0, nzcv 30000000 CV |
| ADD/SUB(reg,32) |
| add w7,w8,w9,lsl #0 :: rd 000000007e23f68a rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 00000000 |
| add w7,w8,w9,lsl #1 :: rd 000000005e37e3dc rm fc9a9d8be2434f5e, rn 6a13f7db3dfa4a3f, cin 0, nzcv 00000000 |
| add w7,w8,w9,lsl #30 :: rd 0000000029b876ab rm d98d2022a9b876ab, rn a7e754e8ff3a554e, cin 0, nzcv 00000000 |
| add w7,w8,w9,lsl #31 :: rd 0000000015990527 rm 33566e6515990527, rn 3d7e7390195d82e2, cin 0, nzcv 00000000 |
| adds w7,w8,w9,lsl #0 :: rd 000000007e23f68a rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 30000000 CV |
| adds w7,w8,w9,lsl #1 :: rd 000000005e37e3dc rm fc9a9d8be2434f5e, rn 6a13f7db3dfa4a3f, cin 0, nzcv 20000000 C |
| adds w7,w8,w9,lsl #30 :: rd 0000000029b876ab rm d98d2022a9b876ab, rn a7e754e8ff3a554e, cin 0, nzcv 30000000 CV |
| adds w7,w8,w9,lsl #31 :: rd 0000000015990527 rm 33566e6515990527, rn 3d7e7390195d82e2, cin 0, nzcv 00000000 |
| adds w7,w8,w9,lsl #0 :: rd 0000000000000000 rm 5555555555555556, rn aaaaaaaaaaaaaaaa, cin 0, nzcv 60000000 ZC |
| add w7,w8,w9,lsr #0 :: rd 000000007e23f68a rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 00000000 |
| add w7,w8,w9,lsr #1 :: rd 000000000140747d rm fc9a9d8be2434f5e, rn 6a13f7db3dfa4a3f, cin 0, nzcv 00000000 |
| add w7,w8,w9,lsr #30 :: rd 00000000a9b876ae rm d98d2022a9b876ab, rn a7e754e8ff3a554e, cin 0, nzcv 00000000 |
| add w7,w8,w9,lsr #31 :: rd 0000000015990527 rm 33566e6515990527, rn 3d7e7390195d82e2, cin 0, nzcv 00000000 |
| adds w7,w8,w9,lsr #0 :: rd 000000007e23f68a rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 30000000 CV |
| adds w7,w8,w9,lsr #1 :: rd 000000000140747d rm fc9a9d8be2434f5e, rn 6a13f7db3dfa4a3f, cin 0, nzcv 20000000 C |
| adds w7,w8,w9,lsr #30 :: rd 00000000a9b876ae rm d98d2022a9b876ab, rn a7e754e8ff3a554e, cin 0, nzcv 80000000 N |
| adds w7,w8,w9,lsr #31 :: rd 0000000015990527 rm 33566e6515990527, rn 3d7e7390195d82e2, cin 0, nzcv 00000000 |
| adds w7,w8,w9,lsr #0 :: rd 0000000000000000 rm 5555555555555556, rn aaaaaaaaaaaaaaaa, cin 0, nzcv 60000000 ZC |
| add w7,w8,w9,asr #0 :: rd 000000007e23f68a rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 00000000 |
| add w7,w8,w9,asr #1 :: rd 000000000140747d rm fc9a9d8be2434f5e, rn 6a13f7db3dfa4a3f, cin 0, nzcv 00000000 |
| add w7,w8,w9,asr #30 :: rd 00000000a9b876aa rm d98d2022a9b876ab, rn a7e754e8ff3a554e, cin 0, nzcv 00000000 |
| add w7,w8,w9,asr #31 :: rd 0000000015990527 rm 33566e6515990527, rn 3d7e7390195d82e2, cin 0, nzcv 00000000 |
| adds w7,w8,w9,asr #0 :: rd 000000007e23f68a rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 30000000 CV |
| adds w7,w8,w9,asr #1 :: rd 000000000140747d rm fc9a9d8be2434f5e, rn 6a13f7db3dfa4a3f, cin 0, nzcv 20000000 C |
| adds w7,w8,w9,asr #30 :: rd 00000000a9b876aa rm d98d2022a9b876ab, rn a7e754e8ff3a554e, cin 0, nzcv a0000000 N C |
| adds w7,w8,w9,asr #31 :: rd 0000000015990527 rm 33566e6515990527, rn 3d7e7390195d82e2, cin 0, nzcv 00000000 |
| adds w7,w8,w9,asr #0 :: rd 0000000000000000 rm 5555555555555556, rn aaaaaaaaaaaaaaaa, cin 0, nzcv 60000000 ZC |
| sub w7,w8,w9,lsl #0 :: rd 00000000315df3c6 rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 00000000 |
| sub w7,w8,w9,lsl #1 :: rd 00000000664ebae0 rm fc9a9d8be2434f5e, rn 6a13f7db3dfa4a3f, cin 0, nzcv 00000000 |
| sub w7,w8,w9,lsl #30 :: rd 0000000029b876ab rm d98d2022a9b876ab, rn a7e754e8ff3a554e, cin 0, nzcv 00000000 |
| sub w7,w8,w9,lsl #31 :: rd 0000000015990527 rm 33566e6515990527, rn 3d7e7390195d82e2, cin 0, nzcv 00000000 |
| subs w7,w8,w9,lsl #0 :: rd 00000000315df3c6 rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 20000000 C |
| subs w7,w8,w9,lsl #1 :: rd 00000000664ebae0 rm fc9a9d8be2434f5e, rn 6a13f7db3dfa4a3f, cin 0, nzcv 30000000 CV |
| subs w7,w8,w9,lsl #30 :: rd 0000000029b876ab rm d98d2022a9b876ab, rn a7e754e8ff3a554e, cin 0, nzcv 20000000 C |
| subs w7,w8,w9,lsl #31 :: rd 0000000015990527 rm 33566e6515990527, rn 3d7e7390195d82e2, cin 0, nzcv 20000000 C |
| subs w7,w8,w9,lsl #0 :: rd 00000000aaaaaaac rm 5555555555555556, rn aaaaaaaaaaaaaaaa, cin 0, nzcv 90000000 N V |
| sub w7,w8,w9,lsr #0 :: rd 00000000315df3c6 rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 00000000 |
| sub w7,w8,w9,lsr #1 :: rd 00000000c3462a3f rm fc9a9d8be2434f5e, rn 6a13f7db3dfa4a3f, cin 0, nzcv 00000000 |
| sub w7,w8,w9,lsr #30 :: rd 00000000a9b876a8 rm d98d2022a9b876ab, rn a7e754e8ff3a554e, cin 0, nzcv 00000000 |
| sub w7,w8,w9,lsr #31 :: rd 0000000015990527 rm 33566e6515990527, rn 3d7e7390195d82e2, cin 0, nzcv 00000000 |
| subs w7,w8,w9,lsr #0 :: rd 00000000315df3c6 rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 20000000 C |
| subs w7,w8,w9,lsr #1 :: rd 00000000c3462a3f rm fc9a9d8be2434f5e, rn 6a13f7db3dfa4a3f, cin 0, nzcv a0000000 N C |
| subs w7,w8,w9,lsr #30 :: rd 00000000a9b876a8 rm d98d2022a9b876ab, rn a7e754e8ff3a554e, cin 0, nzcv a0000000 N C |
| subs w7,w8,w9,lsr #31 :: rd 0000000015990527 rm 33566e6515990527, rn 3d7e7390195d82e2, cin 0, nzcv 20000000 C |
| subs w7,w8,w9,lsr #0 :: rd 00000000aaaaaaac rm 5555555555555556, rn aaaaaaaaaaaaaaaa, cin 0, nzcv 90000000 N V |
| sub w7,w8,w9,asr #0 :: rd 00000000315df3c6 rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 00000000 |
| sub w7,w8,w9,asr #1 :: rd 00000000c3462a3f rm fc9a9d8be2434f5e, rn 6a13f7db3dfa4a3f, cin 0, nzcv 00000000 |
| sub w7,w8,w9,asr #30 :: rd 00000000a9b876ac rm d98d2022a9b876ab, rn a7e754e8ff3a554e, cin 0, nzcv 00000000 |
| sub w7,w8,w9,asr #31 :: rd 0000000015990527 rm 33566e6515990527, rn 3d7e7390195d82e2, cin 0, nzcv 00000000 |
| subs w7,w8,w9,asr #0 :: rd 00000000315df3c6 rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 20000000 C |
| subs w7,w8,w9,asr #1 :: rd 00000000c3462a3f rm fc9a9d8be2434f5e, rn 6a13f7db3dfa4a3f, cin 0, nzcv a0000000 N C |
| subs w7,w8,w9,asr #30 :: rd 00000000a9b876ac rm d98d2022a9b876ab, rn a7e754e8ff3a554e, cin 0, nzcv 80000000 N |
| subs w7,w8,w9,asr #31 :: rd 0000000015990527 rm 33566e6515990527, rn 3d7e7390195d82e2, cin 0, nzcv 20000000 C |
| subs w7,w8,w9,asr #0 :: rd 0000000000000000 rm 5555555555555555, rn 5555555555555555, cin 0, nzcv 60000000 ZC |
| subs w7,w8,w9,asr #0 :: rd 0000000055555555 rm aaaaaaaaaaaaaaaa, rn 5555555555555555, cin 0, nzcv 30000000 CV |
| LOGIC(reg,64) |
| and x7,x8,x9,lsl #0 :: rd 8202020010e38110 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| and x7,x8,x9,lsl #1 :: rd b5109a0a65400400 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| and x7,x8,x9,lsl #62 :: rd c000000000000000 rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| and x7,x8,x9,lsl #63 :: rd 8000000000000000 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| and x7,x8,x9,lsr #0 :: rd 8202020010e38110 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| and x7,x8,x9,lsr #1 :: rd 2d60a28685500008 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| and x7,x8,x9,lsr #62 :: rd 0000000000000003 rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| and x7,x8,x9,lsr #63 :: rd 0000000000000001 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| and x7,x8,x9,asr #0 :: rd 8202020010e38110 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| and x7,x8,x9,asr #1 :: rd 2d60a28685500008 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| and x7,x8,x9,asr #62 :: rd c58586ea2c6954df rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| and x7,x8,x9,asr #63 :: rd fb834ed5b21de6b5 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| and x7,x8,x9,ror #0 :: rd 8202020010e38110 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| and x7,x8,x9,ror #1 :: rd 2d60a28685500008 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| and x7,x8,x9,ror #62 :: rd 81850020040854cf rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| and x7,x8,x9,ror #63 :: rd 30020081b2196695 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| orr x7,x8,x9,lsl #0 :: rd ff737bf1d7fbf7df rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| orr x7,x8,x9,lsl #1 :: rd fffbbebefdd9bcfc rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| orr x7,x8,x9,lsl #62 :: rd c58586ea2c6954df rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| orr x7,x8,x9,lsl #63 :: rd fb834ed5b21de6b5 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| orr x7,x8,x9,lsr #0 :: rd ff737bf1d7fbf7df rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| orr x7,x8,x9,lsr #1 :: rd fdfdbfaeff72f79d rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| orr x7,x8,x9,lsr #62 :: rd c58586ea2c6954df rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| orr x7,x8,x9,lsr #63 :: rd fb834ed5b21de6b5 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| orr x7,x8,x9,asr #0 :: rd ff737bf1d7fbf7df rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| orr x7,x8,x9,asr #1 :: rd fdfdbfaeff72f79d rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| orr x7,x8,x9,asr #62 :: rd ffffffffffffffff rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| orr x7,x8,x9,asr #63 :: rd ffffffffffffffff rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| orr x7,x8,x9,ror #0 :: rd ff737bf1d7fbf7df rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| orr x7,x8,x9,ror #1 :: rd fdfdbfaeff72f79d rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| orr x7,x8,x9,ror #62 :: rd e585d6ef3d695ddf rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| orr x7,x8,x9,ror #63 :: rd ffa3cff5fa3ffeff rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| eor x7,x8,x9,lsl #0 :: rd 7d7179f1c71876cf rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| eor x7,x8,x9,lsl #1 :: rd 4aeb24b49899b8fc rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| eor x7,x8,x9,lsl #62 :: rd 058586ea2c6954df rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| eor x7,x8,x9,lsl #63 :: rd 7b834ed5b21de6b5 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| eor x7,x8,x9,lsr #0 :: rd 7d7179f1c71876cf rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| eor x7,x8,x9,lsr #1 :: rd d09d1d287a22f795 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| eor x7,x8,x9,lsr #62 :: rd c58586ea2c6954dc rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| eor x7,x8,x9,lsr #63 :: rd fb834ed5b21de6b4 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| eor x7,x8,x9,asr #0 :: rd 7d7179f1c71876cf rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| eor x7,x8,x9,asr #1 :: rd d09d1d287a22f795 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| eor x7,x8,x9,asr #62 :: rd 3a7a7915d396ab20 rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| eor x7,x8,x9,asr #63 :: rd 047cb12a4de2194a rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| eor x7,x8,x9,ror #0 :: rd 7d7179f1c71876cf rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| eor x7,x8,x9,ror #1 :: rd d09d1d287a22f795 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| eor x7,x8,x9,ror #62 :: rd 6400d6cf39610910 rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| eor x7,x8,x9,ror #63 :: rd cfa1cf744826986a rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| ands x7,x8,x9,lsl #0 :: rd 8202020010e38110 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 80000000 N |
| ands x7,x8,x9,lsl #1 :: rd b5109a0a65400400 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 80000000 N |
| ands x7,x8,x9,lsl #62 :: rd c000000000000000 rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 80000000 N |
| ands x7,x8,x9,lsl #63 :: rd 8000000000000000 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 80000000 N |
| ands x7,x8,x9,lsr #0 :: rd 8202020010e38110 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 80000000 N |
| ands x7,x8,x9,lsr #1 :: rd 2d60a28685500008 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| ands x7,x8,x9,lsr #62 :: rd 0000000000000003 rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| ands x7,x8,x9,lsr #63 :: rd 0000000000000001 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| ands x7,x8,x9,asr #0 :: rd 8202020010e38110 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 80000000 N |
| ands x7,x8,x9,asr #1 :: rd 2d60a28685500008 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| ands x7,x8,x9,asr #62 :: rd c58586ea2c6954df rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 80000000 N |
| ands x7,x8,x9,asr #63 :: rd fb834ed5b21de6b5 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 80000000 N |
| ands x7,x8,x9,ror #0 :: rd 8202020010e38110 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 80000000 N |
| ands x7,x8,x9,ror #1 :: rd 2d60a28685500008 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| ands x7,x8,x9,ror #62 :: rd 81850020040854cf rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 80000000 N |
| ands x7,x8,x9,ror #63 :: rd 30020081b2196695 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| ands x7,x8,x9,ror #22 :: rd 0000000000000000 rm 5555555555555555, rn aaaaaaaaaaaaaaaa, cin 0, nzcv 40000000 Z |
| bic x7,x8,x9,lsl #0 :: rd 59412111c10020c5 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| bic x7,x8,x9,lsl #1 :: rd 486920a48010b088 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| bic x7,x8,x9,lsl #62 :: rd 058586ea2c6954df rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| bic x7,x8,x9,lsl #63 :: rd 7b834ed5b21de6b5 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| bic x7,x8,x9,lsr #0 :: rd 59412111c10020c5 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| bic x7,x8,x9,lsr #1 :: rd d01918286000b480 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| bic x7,x8,x9,lsr #62 :: rd c58586ea2c6954dc rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| bic x7,x8,x9,lsr #63 :: rd fb834ed5b21de6b4 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| bic x7,x8,x9,asr #0 :: rd 59412111c10020c5 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| bic x7,x8,x9,asr #1 :: rd d01918286000b480 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| bic x7,x8,x9,asr #62 :: rd 0000000000000000 rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| bic x7,x8,x9,asr #63 :: rd 0000000000000000 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| bic x7,x8,x9,ror #0 :: rd 59412111c10020c5 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| bic x7,x8,x9,ror #1 :: rd d01918286000b480 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| bic x7,x8,x9,ror #62 :: rd 440086ca28610010 rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| bic x7,x8,x9,ror #63 :: rd cb814e5400048020 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| orn x7,x8,x9,lsl #0 :: rd dbcfa71ff9e7a9f5 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| orn x7,x8,x9,lsl #1 :: rd fd7dfbefe776f78b rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| orn x7,x8,x9,lsl #62 :: rd ffffffffffffffff rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| orn x7,x8,x9,lsl #63 :: rd ffffffffffffffff rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| orn x7,x8,x9,lsr #0 :: rd dbcfa71ff9e7a9f5 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| orn x7,x8,x9,lsr #1 :: rd ff7bfaffe5ddbcea rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| orn x7,x8,x9,lsr #62 :: rd ffffffffffffffff rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| orn x7,x8,x9,lsr #63 :: rd ffffffffffffffff rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| orn x7,x8,x9,asr #0 :: rd dbcfa71ff9e7a9f5 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| orn x7,x8,x9,asr #1 :: rd ff7bfaffe5ddbcea rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| orn x7,x8,x9,asr #62 :: rd c58586ea2c6954df rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| orn x7,x8,x9,asr #63 :: rd fb834ed5b21de6b5 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| orn x7,x8,x9,ror #0 :: rd dbcfa71ff9e7a9f5 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| orn x7,x8,x9,ror #1 :: rd ff7bfaffe5ddbcea rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| orn x7,x8,x9,ror #62 :: rd dfffaffaeefff6ff rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| orn x7,x8,x9,ror #63 :: rd fbdf7edfb7dde7b5 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| eon x7,x8,x9,lsl #0 :: rd 828e860e38e78930 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| eon x7,x8,x9,lsl #1 :: rd b514db4b67664703 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| eon x7,x8,x9,lsl #62 :: rd fa7a7915d396ab20 rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| eon x7,x8,x9,lsl #63 :: rd 847cb12a4de2194a rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| eon x7,x8,x9,lsr #0 :: rd 828e860e38e78930 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| eon x7,x8,x9,lsr #1 :: rd 2f62e2d785dd086a rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| eon x7,x8,x9,lsr #62 :: rd 3a7a7915d396ab23 rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| eon x7,x8,x9,lsr #63 :: rd 047cb12a4de2194b rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| eon x7,x8,x9,asr #0 :: rd 828e860e38e78930 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| eon x7,x8,x9,asr #1 :: rd 2f62e2d785dd086a rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| eon x7,x8,x9,asr #62 :: rd c58586ea2c6954df rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| eon x7,x8,x9,asr #63 :: rd fb834ed5b21de6b5 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| eon x7,x8,x9,ror #0 :: rd 828e860e38e78930 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| eon x7,x8,x9,ror #1 :: rd 2f62e2d785dd086a rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| eon x7,x8,x9,ror #62 :: rd 9bff2930c69ef6ef rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| eon x7,x8,x9,ror #63 :: rd 305e308bb7d96795 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| bics x7,x8,x9,lsl #0 :: rd 59412111c10020c5 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| bics x7,x8,x9,lsl #1 :: rd 486920a48010b088 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| bics x7,x8,x9,lsl #62 :: rd 058586ea2c6954df rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| bics x7,x8,x9,lsl #63 :: rd 7b834ed5b21de6b5 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| bics x7,x8,x9,lsr #0 :: rd 59412111c10020c5 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| bics x7,x8,x9,lsr #1 :: rd d01918286000b480 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 80000000 N |
| bics x7,x8,x9,lsr #62 :: rd c58586ea2c6954dc rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 80000000 N |
| bics x7,x8,x9,lsr #63 :: rd fb834ed5b21de6b4 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 80000000 N |
| bics x7,x8,x9,asr #0 :: rd 59412111c10020c5 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| bics x7,x8,x9,asr #1 :: rd d01918286000b480 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 80000000 N |
| bics x7,x8,x9,asr #62 :: rd 0000000000000000 rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 40000000 Z |
| bics x7,x8,x9,asr #63 :: rd 0000000000000000 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 40000000 Z |
| bics x7,x8,x9,ror #0 :: rd 59412111c10020c5 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| bics x7,x8,x9,ror #1 :: rd d01918286000b480 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 80000000 N |
| bics x7,x8,x9,ror #62 :: rd 440086ca28610010 rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| bics x7,x8,x9,ror #63 :: rd cb814e5400048020 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 80000000 N |
| LOGIC(reg,32) |
| and w7,w8,w9,lsl #0 :: rd 0000000010e38110 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| and w7,w8,w9,lsl #1 :: rd 0000000065400400 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| and w7,w8,w9,lsl #30 :: rd 0000000000000000 rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| and w7,w8,w9,lsl #31 :: rd 0000000080000000 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| and w7,w8,w9,lsr #0 :: rd 0000000010e38110 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| and w7,w8,w9,lsr #1 :: rd 0000000005500008 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| and w7,w8,w9,lsr #30 :: rd 0000000000000001 rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| and w7,w8,w9,lsr #31 :: rd 0000000000000001 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| and w7,w8,w9,asr #0 :: rd 0000000010e38110 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| and w7,w8,w9,asr #1 :: rd 0000000005500008 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| and w7,w8,w9,asr #30 :: rd 0000000000000001 rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| and w7,w8,w9,asr #31 :: rd 00000000b21de6b5 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| and w7,w8,w9,ror #0 :: rd 0000000010e38110 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| and w7,w8,w9,ror #1 :: rd 0000000005500008 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| and w7,w8,w9,ror #30 :: rd 00000000040854cd rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| and w7,w8,w9,ror #31 :: rd 00000000b2196695 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| orr w7,w8,w9,lsl #0 :: rd 00000000d7fbf7df rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| orr w7,w8,w9,lsl #1 :: rd 00000000fdd9bcfc rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| orr w7,w8,w9,lsl #30 :: rd 00000000ec6954df rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| orr w7,w8,w9,lsl #31 :: rd 00000000b21de6b5 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| orr w7,w8,w9,lsr #0 :: rd 00000000d7fbf7df rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| orr w7,w8,w9,lsr #1 :: rd 00000000ff72f79d rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| orr w7,w8,w9,lsr #30 :: rd 000000002c6954df rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| orr w7,w8,w9,lsr #31 :: rd 00000000b21de6b5 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| orr w7,w8,w9,asr #0 :: rd 00000000d7fbf7df rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| orr w7,w8,w9,asr #1 :: rd 00000000ff72f79d rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| orr w7,w8,w9,asr #30 :: rd 000000002c6954df rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| orr w7,w8,w9,asr #31 :: rd 00000000ffffffff rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| orr w7,w8,w9,ror #0 :: rd 00000000d7fbf7df rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| orr w7,w8,w9,ror #1 :: rd 00000000ff72f79d rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| orr w7,w8,w9,ror #30 :: rd 000000003d695ddf rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| orr w7,w8,w9,ror #31 :: rd 00000000fa3ffeff rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| eor w7,w8,w9,lsl #0 :: rd 00000000c71876cf rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| eor w7,w8,w9,lsl #1 :: rd 000000009899b8fc rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| eor w7,w8,w9,lsl #30 :: rd 00000000ec6954df rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| eor w7,w8,w9,lsl #31 :: rd 00000000321de6b5 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| eor w7,w8,w9,lsr #0 :: rd 00000000c71876cf rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| eor w7,w8,w9,lsr #1 :: rd 00000000fa22f795 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| eor w7,w8,w9,lsr #30 :: rd 000000002c6954de rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| eor w7,w8,w9,lsr #31 :: rd 00000000b21de6b4 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| eor w7,w8,w9,asr #0 :: rd 00000000c71876cf rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| eor w7,w8,w9,asr #1 :: rd 00000000fa22f795 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| eor w7,w8,w9,asr #30 :: rd 000000002c6954de rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| eor w7,w8,w9,asr #31 :: rd 000000004de2194a rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| eor w7,w8,w9,ror #0 :: rd 00000000c71876cf rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| eor w7,w8,w9,ror #1 :: rd 00000000fa22f795 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| eor w7,w8,w9,ror #30 :: rd 0000000039610912 rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| eor w7,w8,w9,ror #31 :: rd 000000004826986a rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| ands w7,w8,w9,lsl #0 :: rd 0000000010e38110 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| ands w7,w8,w9,lsl #1 :: rd 0000000065400400 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| ands w7,w8,w9,lsl #30 :: rd 0000000000000000 rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 40000000 Z |
| ands w7,w8,w9,lsl #31 :: rd 0000000080000000 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 80000000 N |
| ands w7,w8,w9,lsr #0 :: rd 0000000010e38110 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| ands w7,w8,w9,lsr #1 :: rd 0000000005500008 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| ands w7,w8,w9,lsr #30 :: rd 0000000000000001 rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| ands w7,w8,w9,lsr #31 :: rd 0000000000000001 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| ands w7,w8,w9,asr #0 :: rd 0000000010e38110 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| ands w7,w8,w9,asr #1 :: rd 0000000005500008 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| ands w7,w8,w9,asr #30 :: rd 0000000000000001 rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| ands w7,w8,w9,asr #31 :: rd 00000000b21de6b5 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 80000000 N |
| ands w7,w8,w9,ror #0 :: rd 0000000010e38110 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| ands w7,w8,w9,ror #1 :: rd 0000000005500008 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| ands w7,w8,w9,ror #30 :: rd 00000000040854cd rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| ands w7,w8,w9,ror #31 :: rd 00000000b2196695 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 80000000 N |
| ands w7,w8,w9,ror #22 :: rd 0000000000000000 rm 5555555555555555, rn aaaaaaaaaaaaaaaa, cin 0, nzcv 40000000 Z |
| bic w7,w8,w9,lsl #0 :: rd 00000000c10020c5 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| bic w7,w8,w9,lsl #1 :: rd 000000008010b088 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| bic w7,w8,w9,lsl #30 :: rd 000000002c6954df rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| bic w7,w8,w9,lsl #31 :: rd 00000000321de6b5 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| bic w7,w8,w9,lsr #0 :: rd 00000000c10020c5 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| bic w7,w8,w9,lsr #1 :: rd 00000000e000b480 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| bic w7,w8,w9,lsr #30 :: rd 000000002c6954de rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| bic w7,w8,w9,lsr #31 :: rd 00000000b21de6b4 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| bic w7,w8,w9,asr #0 :: rd 00000000c10020c5 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| bic w7,w8,w9,asr #1 :: rd 00000000e000b480 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| bic w7,w8,w9,asr #30 :: rd 000000002c6954de rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| bic w7,w8,w9,asr #31 :: rd 0000000000000000 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| bic w7,w8,w9,ror #0 :: rd 00000000c10020c5 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| bic w7,w8,w9,ror #1 :: rd 00000000e000b480 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| bic w7,w8,w9,ror #30 :: rd 0000000028610012 rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| bic w7,w8,w9,ror #31 :: rd 0000000000048020 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| orn w7,w8,w9,lsl #0 :: rd 00000000f9e7a9f5 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| orn w7,w8,w9,lsl #1 :: rd 00000000e776f78b rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| orn w7,w8,w9,lsl #30 :: rd 000000003fffffff rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| orn w7,w8,w9,lsl #31 :: rd 00000000ffffffff rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| orn w7,w8,w9,lsr #0 :: rd 00000000f9e7a9f5 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| orn w7,w8,w9,lsr #1 :: rd 00000000e5ddbcea rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| orn w7,w8,w9,lsr #30 :: rd 00000000ffffffff rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| orn w7,w8,w9,lsr #31 :: rd 00000000ffffffff rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| orn w7,w8,w9,asr #0 :: rd 00000000f9e7a9f5 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| orn w7,w8,w9,asr #1 :: rd 00000000e5ddbcea rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| orn w7,w8,w9,asr #30 :: rd 00000000ffffffff rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| orn w7,w8,w9,asr #31 :: rd 00000000b21de6b5 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| orn w7,w8,w9,ror #0 :: rd 00000000f9e7a9f5 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| orn w7,w8,w9,ror #1 :: rd 00000000e5ddbcea rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| orn w7,w8,w9,ror #30 :: rd 00000000eefff6ff rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| orn w7,w8,w9,ror #31 :: rd 00000000b7dde7b5 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| eon w7,w8,w9,lsl #0 :: rd 0000000038e78930 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| eon w7,w8,w9,lsl #1 :: rd 0000000067664703 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| eon w7,w8,w9,lsl #30 :: rd 000000001396ab20 rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| eon w7,w8,w9,lsl #31 :: rd 00000000cde2194a rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| eon w7,w8,w9,lsr #0 :: rd 0000000038e78930 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| eon w7,w8,w9,lsr #1 :: rd 0000000005dd086a rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| eon w7,w8,w9,lsr #30 :: rd 00000000d396ab21 rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| eon w7,w8,w9,lsr #31 :: rd 000000004de2194b rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| eon w7,w8,w9,asr #0 :: rd 0000000038e78930 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| eon w7,w8,w9,asr #1 :: rd 0000000005dd086a rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| eon w7,w8,w9,asr #30 :: rd 00000000d396ab21 rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| eon w7,w8,w9,asr #31 :: rd 00000000b21de6b5 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| eon w7,w8,w9,ror #0 :: rd 0000000038e78930 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 00000000 |
| eon w7,w8,w9,ror #1 :: rd 0000000005dd086a rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 00000000 |
| eon w7,w8,w9,ror #30 :: rd 00000000c69ef6ed rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| eon w7,w8,w9,ror #31 :: rd 00000000b7d96795 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| bics w7,w8,w9,lsl #0 :: rd 00000000c10020c5 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 80000000 N |
| bics w7,w8,w9,lsl #1 :: rd 000000008010b088 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 80000000 N |
| bics w7,w8,w9,lsl #30 :: rd 000000002c6954df rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| bics w7,w8,w9,lsl #31 :: rd 00000000321de6b5 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| bics w7,w8,w9,lsr #0 :: rd 00000000c10020c5 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 80000000 N |
| bics w7,w8,w9,lsr #1 :: rd 00000000e000b480 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 80000000 N |
| bics w7,w8,w9,lsr #30 :: rd 000000002c6954de rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| bics w7,w8,w9,lsr #31 :: rd 00000000b21de6b4 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 80000000 N |
| bics w7,w8,w9,asr #0 :: rd 00000000c10020c5 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 80000000 N |
| bics w7,w8,w9,asr #1 :: rd 00000000e000b480 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 80000000 N |
| bics w7,w8,w9,asr #30 :: rd 000000002c6954de rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| bics w7,w8,w9,asr #31 :: rd 0000000000000000 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 40000000 Z |
| bics w7,w8,w9,ror #0 :: rd 00000000c10020c5 rm db432311d1e3a1d5, rn a6325ae016fbd71a, cin 0, nzcv 80000000 N |
| bics w7,w8,w9,ror #1 :: rd 00000000e000b480 rm fd79baaee550b488, rn 5bc94f0d3ee4863a, cin 0, nzcv 80000000 N |
| bics w7,w8,w9,ror #30 :: rd 0000000028610012 rm c58586ea2c6954df, rn e861540945421773, cin 0, nzcv 00000000 |
| bics w7,w8,w9,ror #31 :: rd 0000000000048020 rm fb834ed5b21de6b5, rn 9a1140d0fd1dbf6f, cin 0, nzcv 00000000 |
| UMULH/SMULH |
| umulh x9,x8,x7 :: rd 4090901a010c79a2 rm efdd33d64e6d6a8b, rn 44e875422d202c19, cin 0, nzcv 00000000 |
| umulh x9,x8,x7 :: rd 1f1f7a1e6854654f rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 00000000 |
| umulh x9,x8,x7 :: rd 80286ba6dafc0fec rm e57b3a514f5207f4, rn 8ef7bac0f0ac903a, cin 0, nzcv 00000000 |
| smulh x9,x8,x7 :: rd fba81ad7d3ec4d89 rm efdd33d64e6d6a8b, rn 44e875422d202c19, cin 0, nzcv 00000000 |
| smulh x9,x8,x7 :: rd f3a320e490937027 rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 00000000 |
| smulh x9,x8,x7 :: rd 0bb576949afd77be rm e57b3a514f5207f4, rn 8ef7bac0f0ac903a, cin 0, nzcv 00000000 |
| MADD/MSUB |
| madd x30,x26,x28,x27 :: rd 1bfc004f8e50d913 rm 7a3847909557e2b4, rn cbbb98441b9e1029, ra 6a13f7db3dfa4a3f, cin 0, nzcv 00000000 |
| madd x30,x26,x28,x27 :: rd 657c15cdfc9563db rm e39b12157cf9610f, rn 0eb420e934db9f92, ra 7564a539bf3eb84d, cin 0, nzcv 00000000 |
| madd x30,x26,x28,x27 :: rd d990e4e3f2995139 rm d7588df1ecb46297, rn 26557c93f44473fa, ra 09fb0ab6a60b34c3, cin 0, nzcv 00000000 |
| madd x30,x26,x28,x27 :: rd 9250e99b8bee2ac2 rm 4f0c54f61ac8f7bd, rn 99b1794bbb4b19cd, ra 52d448b3d56f5369, cin 0, nzcv 00000000 |
| madd x30,x26,x28,x27 :: rd f1280fbc46efe21f rm 5370e6469b1e28ed, rn 0a1925a090f7aaf5, ra a7e754e8ff3a554e, cin 0, nzcv 00000000 |
| msub x30,x26,x28,x27 :: rd b82bef66eda3bb6b rm 7a3847909557e2b4, rn cbbb98441b9e1029, ra 6a13f7db3dfa4a3f, cin 0, nzcv 00000000 |
| msub x30,x26,x28,x27 :: rd 854d34a581e80cbf rm e39b12157cf9610f, rn 0eb420e934db9f92, ra 7564a539bf3eb84d, cin 0, nzcv 00000000 |
| msub x30,x26,x28,x27 :: rd 3a653089597d184d rm d7588df1ecb46297, rn 26557c93f44473fa, ra 09fb0ab6a60b34c3, cin 0, nzcv 00000000 |
| msub x30,x26,x28,x27 :: rd 1357a7cc1ef07c10 rm 4f0c54f61ac8f7bd, rn 99b1794bbb4b19cd, ra 52d448b3d56f5369, cin 0, nzcv 00000000 |
| msub x30,x26,x28,x27 :: rd 5ea69a15b784c87d rm 5370e6469b1e28ed, rn 0a1925a090f7aaf5, ra a7e754e8ff3a554e, cin 0, nzcv 00000000 |
| madd w30,w26,w28,w27 :: rd 000000008e50d913 rm 7a3847909557e2b4, rn cbbb98441b9e1029, ra 6a13f7db3dfa4a3f, cin 0, nzcv 00000000 |
| madd w30,w26,w28,w27 :: rd 00000000fc9563db rm e39b12157cf9610f, rn 0eb420e934db9f92, ra 7564a539bf3eb84d, cin 0, nzcv 00000000 |
| madd w30,w26,w28,w27 :: rd 00000000f2995139 rm d7588df1ecb46297, rn 26557c93f44473fa, ra 09fb0ab6a60b34c3, cin 0, nzcv 00000000 |
| madd w30,w26,w28,w27 :: rd 000000008bee2ac2 rm 4f0c54f61ac8f7bd, rn 99b1794bbb4b19cd, ra 52d448b3d56f5369, cin 0, nzcv 00000000 |
| madd w30,w26,w28,w27 :: rd 0000000046efe21f rm 5370e6469b1e28ed, rn 0a1925a090f7aaf5, ra a7e754e8ff3a554e, cin 0, nzcv 00000000 |
| msub w30,w26,w28,w27 :: rd 00000000eda3bb6b rm 7a3847909557e2b4, rn cbbb98441b9e1029, ra 6a13f7db3dfa4a3f, cin 0, nzcv 00000000 |
| msub w30,w26,w28,w27 :: rd 0000000081e80cbf rm e39b12157cf9610f, rn 0eb420e934db9f92, ra 7564a539bf3eb84d, cin 0, nzcv 00000000 |
| msub w30,w26,w28,w27 :: rd 00000000597d184d rm d7588df1ecb46297, rn 26557c93f44473fa, ra 09fb0ab6a60b34c3, cin 0, nzcv 00000000 |
| msub w30,w26,w28,w27 :: rd 000000001ef07c10 rm 4f0c54f61ac8f7bd, rn 99b1794bbb4b19cd, ra 52d448b3d56f5369, cin 0, nzcv 00000000 |
| msub w30,w26,w28,w27 :: rd 00000000b784c87d rm 5370e6469b1e28ed, rn 0a1925a090f7aaf5, ra a7e754e8ff3a554e, cin 0, nzcv 00000000 |
| CS{EL,INC,INV,NEG}(64) |
| cmp x17,x18 ; csel x16,x17,x18,eq :: rd 7a6c3d1a51246495 rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 30000000 CV |
| cmp x17,x18 ; csel x16,x17,x18,ne :: rd afa6ef803bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 30000000 CV |
| cmp x17,x18 ; csel x16,x17,x18,cc :: rd 7a6c3d1a51246495 rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 30000000 CV |
| cmp x17,x18 ; csel x16,x17,x18,cs :: rd afa6ef803bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 30000000 CV |
| cmp x17,x18 ; csel x16,x17,x18,mi :: rd 7a6c3d1a51246495 rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 30000000 CV |
| cmp x17,x18 ; csel x16,x17,x18,pl :: rd afa6ef803bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 30000000 CV |
| cmp x17,x18 ; csel x16,x17,x18,vc :: rd 7a6c3d1a51246495 rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 30000000 CV |
| cmp x17,x18 ; csel x16,x17,x18,vs :: rd afa6ef803bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 30000000 CV |
| cmp x17,x18 ; csinc x16,x17,x18,eq :: rd 7a6c3d1a51246496 rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 30000000 CV |
| cmp x17,x18 ; csinc x16,x17,x18,ne :: rd afa6ef803bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 30000000 CV |
| cmp x17,x18 ; csinc x16,x17,x18,cc :: rd 7a6c3d1a51246496 rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 30000000 CV |
| cmp x17,x18 ; csinc x16,x17,x18,cs :: rd afa6ef803bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 30000000 CV |
| cmp x17,x18 ; csinc x16,x17,x18,mi :: rd 7a6c3d1a51246496 rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 30000000 CV |
| cmp x17,x18 ; csinc x16,x17,x18,pl :: rd afa6ef803bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 30000000 CV |
| cmp x17,x18 ; csinc x16,x17,x18,vc :: rd 7a6c3d1a51246496 rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 30000000 CV |
| cmp x17,x18 ; csinc x16,x17,x18,vs :: rd afa6ef803bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 30000000 CV |
| cmp x17,x18 ; csinv x16,x17,x18,eq :: rd 8593c2e5aedb9b6a rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 30000000 CV |
| cmp x17,x18 ; csinv x16,x17,x18,ne :: rd afa6ef803bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 30000000 CV |
| cmp x17,x18 ; csinv x16,x17,x18,cc :: rd 8593c2e5aedb9b6a rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 30000000 CV |
| cmp x17,x18 ; csinv x16,x17,x18,cs :: rd afa6ef803bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 30000000 CV |
| cmp x17,x18 ; csinv x16,x17,x18,mi :: rd 8593c2e5aedb9b6a rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 30000000 CV |
| cmp x17,x18 ; csinv x16,x17,x18,pl :: rd afa6ef803bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 30000000 CV |
| cmp x17,x18 ; csinv x16,x17,x18,vc :: rd 8593c2e5aedb9b6a rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 30000000 CV |
| cmp x17,x18 ; csinv x16,x17,x18,vs :: rd afa6ef803bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 30000000 CV |
| cmp x17,x18 ; csneg x16,x17,x18,eq :: rd 8593c2e5aedb9b6b rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 30000000 CV |
| cmp x17,x18 ; csneg x16,x17,x18,ne :: rd afa6ef803bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 30000000 CV |
| cmp x17,x18 ; csneg x16,x17,x18,cc :: rd 8593c2e5aedb9b6b rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 30000000 CV |
| cmp x17,x18 ; csneg x16,x17,x18,cs :: rd afa6ef803bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 30000000 CV |
| cmp x17,x18 ; csneg x16,x17,x18,mi :: rd 8593c2e5aedb9b6b rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 30000000 CV |
| cmp x17,x18 ; csneg x16,x17,x18,pl :: rd afa6ef803bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 30000000 CV |
| cmp x17,x18 ; csneg x16,x17,x18,vc :: rd 8593c2e5aedb9b6b rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 30000000 CV |
| cmp x17,x18 ; csneg x16,x17,x18,vs :: rd afa6ef803bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 30000000 CV |
| CS{EL,INC,INV,NEG}(32) |
| cmp w17,w18 ; csel w16,w17,w18,eq :: rd 0000000051246495 rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 80000000 N |
| cmp w17,w18 ; csel w16,w17,w18,ne :: rd 000000003bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 80000000 N |
| cmp w17,w18 ; csel w16,w17,w18,cc :: rd 000000003bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 80000000 N |
| cmp w17,w18 ; csel w16,w17,w18,cs :: rd 0000000051246495 rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 80000000 N |
| cmp w17,w18 ; csel w16,w17,w18,mi :: rd 000000003bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 80000000 N |
| cmp w17,w18 ; csel w16,w17,w18,pl :: rd 0000000051246495 rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 80000000 N |
| cmp w17,w18 ; csel w16,w17,w18,vc :: rd 000000003bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 80000000 N |
| cmp w17,w18 ; csel w16,w17,w18,vs :: rd 0000000051246495 rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 80000000 N |
| cmp w17,w18 ; csinc w16,w17,w18,eq :: rd 0000000051246496 rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 80000000 N |
| cmp w17,w18 ; csinc w16,w17,w18,ne :: rd 000000003bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 80000000 N |
| cmp w17,w18 ; csinc w16,w17,w18,cc :: rd 000000003bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 80000000 N |
| cmp w17,w18 ; csinc w16,w17,w18,cs :: rd 0000000051246496 rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 80000000 N |
| cmp w17,w18 ; csinc w16,w17,w18,mi :: rd 000000003bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 80000000 N |
| cmp w17,w18 ; csinc w16,w17,w18,pl :: rd 0000000051246496 rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 80000000 N |
| cmp w17,w18 ; csinc w16,w17,w18,vc :: rd 000000003bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 80000000 N |
| cmp w17,w18 ; csinc w16,w17,w18,vs :: rd 0000000051246496 rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 80000000 N |
| cmp w17,w18 ; csinv w16,w17,w18,eq :: rd 00000000aedb9b6a rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 80000000 N |
| cmp w17,w18 ; csinv w16,w17,w18,ne :: rd 000000003bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 80000000 N |
| cmp w17,w18 ; csinv w16,w17,w18,cc :: rd 000000003bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 80000000 N |
| cmp w17,w18 ; csinv w16,w17,w18,cs :: rd 00000000aedb9b6a rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 80000000 N |
| cmp w17,w18 ; csinv w16,w17,w18,mi :: rd 000000003bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 80000000 N |
| cmp w17,w18 ; csinv w16,w17,w18,pl :: rd 00000000aedb9b6a rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 80000000 N |
| cmp w17,w18 ; csinv w16,w17,w18,vc :: rd 000000003bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 80000000 N |
| cmp w17,w18 ; csinv w16,w17,w18,vs :: rd 00000000aedb9b6a rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 80000000 N |
| cmp w17,w18 ; csneg w16,w17,w18,eq :: rd 00000000aedb9b6b rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 80000000 N |
| cmp w17,w18 ; csneg w16,w17,w18,ne :: rd 000000003bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 80000000 N |
| cmp w17,w18 ; csneg w16,w17,w18,cc :: rd 000000003bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 80000000 N |
| cmp w17,w18 ; csneg w16,w17,w18,cs :: rd 00000000aedb9b6b rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 80000000 N |
| cmp w17,w18 ; csneg w16,w17,w18,mi :: rd 000000003bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 80000000 N |
| cmp w17,w18 ; csneg w16,w17,w18,pl :: rd 00000000aedb9b6b rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 80000000 N |
| cmp w17,w18 ; csneg w16,w17,w18,vc :: rd 000000003bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 80000000 N |
| cmp w17,w18 ; csneg w16,w17,w18,vs :: rd 00000000aedb9b6b rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 80000000 N |
| ADD/SUB(extended reg)(64) |
| add x21,x22,x23,uxtb #0 :: rd a3ca7e66297c4707 rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 |
| add x21,x22,x23,uxtb #1 :: rd 09fb0ab6a60b350b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 |
| add x21,x22,x23,uxtb #2 :: rd 52d448b3d56f5615 rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000 |
| add x21,x22,x23,uxtb #3 :: rd a7e754e8ff3a5596 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 00000000 |
| add x21,x22,x23,uxtb #4 :: rd 2e10f2a4055bf2ae rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| add x21,x22,x23,uxth #0 :: rd a3ca7e66297ca007 rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 |
| add x21,x22,x23,uxth #1 :: rd 09fb0ab6a60b470b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 |
| add x21,x22,x23,uxth #2 :: rd 52d448b3d5712e15 rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000 |
| add x21,x22,x23,uxth #3 :: rd a7e754e8ff3ef596 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 00000000 |
| add x21,x22,x23,uxth #4 :: rd 2e10f2a4056782ae rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| add x21,x22,x23,uxtw #0 :: rd a3ca7e670aa2a007 rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 |
| add x21,x22,x23,uxtw #1 :: rd 09fb0ab7b7bd470b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 |
| add x21,x22,x23,uxtw #2 :: rd 52d448b67c512e15 rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000 |
| add x21,x22,x23,uxtw #3 :: rd a7e754e9135ef596 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 00000000 |
| add x21,x22,x23,uxtw #4 :: rd 2e10f2b0786782ae rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| add x21,x22,x23,uxtx #0 :: rd 4a48881f0aa2a007 rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 |
| add x21,x22,x23,uxtx #1 :: rd 550438d7b7bd470b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 |
| add x21,x22,x23,uxtx #2 :: rd b908c93e7c512e15 rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000 |
| add x21,x22,x23,uxtx #3 :: rd 7d79e501135ef596 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 00000000 |
| add x21,x22,x23,uxtx #4 :: rd ad4c8070786782ae rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| add x21,x22,x23,sxtb #0 :: rd a3ca7e66297c4707 rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 |
| add x21,x22,x23,sxtb #1 :: rd 09fb0ab6a60b350b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 |
| add x21,x22,x23,sxtb #2 :: rd 52d448b3d56f5215 rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000 |
| add x21,x22,x23,sxtb #3 :: rd a7e754e8ff3a5596 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 00000000 |
| add x21,x22,x23,sxtb #4 :: rd 2e10f2a4055bf2ae rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| add x21,x22,x23,sxth #0 :: rd a3ca7e66297ca007 rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 |
| add x21,x22,x23,sxth #1 :: rd 09fb0ab6a60b470b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 |
| add x21,x22,x23,sxth #2 :: rd 52d448b3d5712e15 rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000 |
| add x21,x22,x23,sxth #3 :: rd a7e754e8ff36f596 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 00000000 |
| add x21,x22,x23,sxth #4 :: rd 2e10f2a4055782ae rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| add x21,x22,x23,sxtw #0 :: rd a3ca7e660aa2a007 rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 |
| add x21,x22,x23,sxtw #1 :: rd 09fb0ab5b7bd470b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 |
| add x21,x22,x23,sxtw #2 :: rd 52d448b27c512e15 rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000 |
| add x21,x22,x23,sxtw #3 :: rd a7e754e9135ef596 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 00000000 |
| add x21,x22,x23,sxtw #4 :: rd 2e10f2a0786782ae rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| add x21,x22,x23,sxtx #0 :: rd 4a48881f0aa2a007 rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 |
| add x21,x22,x23,sxtx #1 :: rd 550438d7b7bd470b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 |
| add x21,x22,x23,sxtx #2 :: rd b908c93e7c512e15 rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000 |
| add x21,x22,x23,sxtx #3 :: rd 7d79e501135ef596 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 00000000 |
| add x21,x22,x23,sxtx #4 :: rd ad4c8070786782ae rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| adds x21,x22,x23,uxtb #0 :: rd a3ca7e66297c4707 rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 80000000 N |
| adds x21,x22,x23,uxtb #1 :: rd 09fb0ab6a60b350b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 |
| adds x21,x22,x23,uxtb #2 :: rd 52d448b3d56f5615 rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000 |
| adds x21,x22,x23,uxtb #3 :: rd a7e754e8ff3a5596 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 80000000 N |
| adds x21,x22,x23,uxtb #4 :: rd 2e10f2a4055bf2ae rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| adds x21,x22,x23,uxth #0 :: rd a3ca7e66297ca007 rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 80000000 N |
| adds x21,x22,x23,uxth #1 :: rd 09fb0ab6a60b470b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 |
| adds x21,x22,x23,uxth #2 :: rd 52d448b3d5712e15 rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000 |
| adds x21,x22,x23,uxth #3 :: rd a7e754e8ff3ef596 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 80000000 N |
| adds x21,x22,x23,uxth #4 :: rd 2e10f2a4056782ae rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| adds x21,x22,x23,uxtw #0 :: rd a3ca7e670aa2a007 rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 80000000 N |
| adds x21,x22,x23,uxtw #1 :: rd 09fb0ab7b7bd470b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 |
| adds x21,x22,x23,uxtw #2 :: rd 52d448b67c512e15 rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000 |
| adds x21,x22,x23,uxtw #3 :: rd a7e754e9135ef596 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 80000000 N |
| adds x21,x22,x23,uxtw #4 :: rd 2e10f2b0786782ae rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| adds x21,x22,x23,uxtx #0 :: rd 4a48881f0aa2a007 rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 30000000 CV |
| adds x21,x22,x23,uxtx #1 :: rd 550438d7b7bd470b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 |
| adds x21,x22,x23,uxtx #2 :: rd b908c93e7c512e15 rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 90000000 N V |
| adds x21,x22,x23,uxtx #3 :: rd 7d79e501135ef596 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 30000000 CV |
| adds x21,x22,x23,uxtx #4 :: rd ad4c8070786782ae rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 90000000 N V |
| adds x21,x22,x23,sxtb #0 :: rd a3ca7e66297c4707 rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 80000000 N |
| adds x21,x22,x23,sxtb #1 :: rd 09fb0ab6a60b350b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 |
| adds x21,x22,x23,sxtb #2 :: rd 52d448b3d56f5215 rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 20000000 C |
| adds x21,x22,x23,sxtb #3 :: rd a7e754e8ff3a5596 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 80000000 N |
| adds x21,x22,x23,sxtb #4 :: rd 2e10f2a4055bf2ae rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| adds x21,x22,x23,sxth #0 :: rd a3ca7e66297ca007 rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 80000000 N |
| adds x21,x22,x23,sxth #1 :: rd 09fb0ab6a60b470b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 |
| adds x21,x22,x23,sxth #2 :: rd 52d448b3d5712e15 rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000 |
| adds x21,x22,x23,sxth #3 :: rd a7e754e8ff36f596 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv a0000000 N C |
| adds x21,x22,x23,sxth #4 :: rd 2e10f2a4055782ae rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 20000000 C |
| adds x21,x22,x23,sxtw #0 :: rd a3ca7e660aa2a007 rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv a0000000 N C |
| adds x21,x22,x23,sxtw #1 :: rd 09fb0ab5b7bd470b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 20000000 C |
| adds x21,x22,x23,sxtw #2 :: rd 52d448b27c512e15 rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 20000000 C |
| adds x21,x22,x23,sxtw #3 :: rd a7e754e9135ef596 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 80000000 N |
| adds x21,x22,x23,sxtw #4 :: rd 2e10f2a0786782ae rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 20000000 C |
| adds x21,x22,x23,sxtx #0 :: rd 4a48881f0aa2a007 rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 30000000 CV |
| adds x21,x22,x23,sxtx #1 :: rd 550438d7b7bd470b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 |
| adds x21,x22,x23,sxtx #2 :: rd b908c93e7c512e15 rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 90000000 N V |
| adds x21,x22,x23,sxtx #3 :: rd 7d79e501135ef596 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 30000000 CV |
| adds x21,x22,x23,sxtx #4 :: rd ad4c8070786782ae rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 90000000 N V |
| sub x21,x22,x23,uxtb #0 :: rd a3ca7e66297c462f rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 |
| sub x21,x22,x23,uxtb #1 :: rd 09fb0ab6a60b347b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 |
| sub x21,x22,x23,uxtb #2 :: rd 52d448b3d56f50bd rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000 |
| sub x21,x22,x23,uxtb #3 :: rd a7e754e8ff3a5506 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 00000000 |
| sub x21,x22,x23,uxtb #4 :: rd 2e10f2a4055be56e rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| sub x21,x22,x23,uxth #0 :: rd a3ca7e66297bed2f rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 |
| sub x21,x22,x23,uxth #1 :: rd 09fb0ab6a60b227b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 |
| sub x21,x22,x23,uxth #2 :: rd 52d448b3d56d78bd rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000 |
| sub x21,x22,x23,uxth #3 :: rd a7e754e8ff35b506 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 00000000 |
| sub x21,x22,x23,uxth #4 :: rd 2e10f2a40550556e rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| sub x21,x22,x23,uxtw #0 :: rd a3ca7e654855ed2f rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 |
| sub x21,x22,x23,uxtw #1 :: rd 09fb0ab59459227b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 |
| sub x21,x22,x23,uxtw #2 :: rd 52d448b12e8d78bd rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000 |
| sub x21,x22,x23,uxtw #3 :: rd a7e754e8eb15b506 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 00000000 |
| sub x21,x22,x23,uxtw #4 :: rd 2e10f2979250556e rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| sub x21,x22,x23,uxtx #0 :: rd fd4c74ad4855ed2f rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 |
| sub x21,x22,x23,uxtx #1 :: rd bef1dc959459227b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 |
| sub x21,x22,x23,uxtx #2 :: rd ec9fc8292e8d78bd rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000 |
| sub x21,x22,x23,uxtx #3 :: rd d254c4d0eb15b506 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 00000000 |
| sub x21,x22,x23,uxtx #4 :: rd aed564d79250556e rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| sub x21,x22,x23,sxtb #0 :: rd a3ca7e66297c462f rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 |
| sub x21,x22,x23,sxtb #1 :: rd 09fb0ab6a60b347b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 |
| sub x21,x22,x23,sxtb #2 :: rd 52d448b3d56f54bd rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000 |
| sub x21,x22,x23,sxtb #3 :: rd a7e754e8ff3a5506 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 00000000 |
| sub x21,x22,x23,sxtb #4 :: rd 2e10f2a4055be56e rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| sub x21,x22,x23,sxth #0 :: rd a3ca7e66297bed2f rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 |
| sub x21,x22,x23,sxth #1 :: rd 09fb0ab6a60b227b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 |
| sub x21,x22,x23,sxth #2 :: rd 52d448b3d56d78bd rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000 |
| sub x21,x22,x23,sxth #3 :: rd a7e754e8ff3db506 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 00000000 |
| sub x21,x22,x23,sxth #4 :: rd 2e10f2a40560556e rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| sub x21,x22,x23,sxtw #0 :: rd a3ca7e664855ed2f rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 |
| sub x21,x22,x23,sxtw #1 :: rd 09fb0ab79459227b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 |
| sub x21,x22,x23,sxtw #2 :: rd 52d448b52e8d78bd rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000 |
| sub x21,x22,x23,sxtw #3 :: rd a7e754e8eb15b506 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 00000000 |
| sub x21,x22,x23,sxtw #4 :: rd 2e10f2a79250556e rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| sub x21,x22,x23,sxtx #0 :: rd fd4c74ad4855ed2f rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 |
| sub x21,x22,x23,sxtx #1 :: rd bef1dc959459227b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 |
| sub x21,x22,x23,sxtx #2 :: rd ec9fc8292e8d78bd rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000 |
| sub x21,x22,x23,sxtx #3 :: rd d254c4d0eb15b506 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 00000000 |
| sub x21,x22,x23,sxtx #4 :: rd aed564d79250556e rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| subs x21,x22,x23,uxtb #0 :: rd a3ca7e66297c462f rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv a0000000 N C |
| subs x21,x22,x23,uxtb #1 :: rd 09fb0ab6a60b347b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 20000000 C |
| subs x21,x22,x23,uxtb #2 :: rd 52d448b3d56f50bd rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 20000000 C |
| subs x21,x22,x23,uxtb #3 :: rd a7e754e8ff3a5506 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv a0000000 N C |
| subs x21,x22,x23,uxtb #4 :: rd 2e10f2a4055be56e rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 20000000 C |
| subs x21,x22,x23,uxth #0 :: rd a3ca7e66297bed2f rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv a0000000 N C |
| subs x21,x22,x23,uxth #1 :: rd 09fb0ab6a60b227b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 20000000 C |
| subs x21,x22,x23,uxth #2 :: rd 52d448b3d56d78bd rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 20000000 C |
| subs x21,x22,x23,uxth #3 :: rd a7e754e8ff35b506 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv a0000000 N C |
| subs x21,x22,x23,uxth #4 :: rd 2e10f2a40550556e rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 20000000 C |
| subs x21,x22,x23,uxtw #0 :: rd a3ca7e654855ed2f rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv a0000000 N C |
| subs x21,x22,x23,uxtw #1 :: rd 09fb0ab59459227b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 20000000 C |
| subs x21,x22,x23,uxtw #2 :: rd 52d448b12e8d78bd rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 20000000 C |
| subs x21,x22,x23,uxtw #3 :: rd a7e754e8eb15b506 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv a0000000 N C |
| subs x21,x22,x23,uxtw #4 :: rd 2e10f2979250556e rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 20000000 C |
| subs x21,x22,x23,uxtx #0 :: rd fd4c74ad4855ed2f rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 80000000 N |
| subs x21,x22,x23,uxtx #1 :: rd bef1dc959459227b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 80000000 N |
| subs x21,x22,x23,uxtx #2 :: rd ec9fc8292e8d78bd rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 80000000 N |
| subs x21,x22,x23,uxtx #3 :: rd d254c4d0eb15b506 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 80000000 N |
| subs x21,x22,x23,uxtx #4 :: rd aed564d79250556e rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 80000000 N |
| subs x21,x22,x23,sxtb #0 :: rd a3ca7e66297c462f rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv a0000000 N C |
| subs x21,x22,x23,sxtb #1 :: rd 09fb0ab6a60b347b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 20000000 C |
| subs x21,x22,x23,sxtb #2 :: rd 52d448b3d56f54bd rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000 |
| subs x21,x22,x23,sxtb #3 :: rd a7e754e8ff3a5506 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv a0000000 N C |
| subs x21,x22,x23,sxtb #4 :: rd 2e10f2a4055be56e rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 20000000 C |
| subs x21,x22,x23,sxth #0 :: rd a3ca7e66297bed2f rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv a0000000 N C |
| subs x21,x22,x23,sxth #1 :: rd 09fb0ab6a60b227b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 20000000 C |
| subs x21,x22,x23,sxth #2 :: rd 52d448b3d56d78bd rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 20000000 C |
| subs x21,x22,x23,sxth #3 :: rd a7e754e8ff3db506 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 80000000 N |
| subs x21,x22,x23,sxth #4 :: rd 2e10f2a40560556e rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| subs x21,x22,x23,sxtw #0 :: rd a3ca7e664855ed2f rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 80000000 N |
| subs x21,x22,x23,sxtw #1 :: rd 09fb0ab79459227b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 |
| subs x21,x22,x23,sxtw #2 :: rd 52d448b52e8d78bd rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000 |
| subs x21,x22,x23,sxtw #3 :: rd a7e754e8eb15b506 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv a0000000 N C |
| subs x21,x22,x23,sxtw #4 :: rd 2e10f2a79250556e rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| subs x21,x22,x23,sxtx #0 :: rd fd4c74ad4855ed2f rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 80000000 N |
| subs x21,x22,x23,sxtx #1 :: rd bef1dc959459227b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 80000000 N |
| subs x21,x22,x23,sxtx #2 :: rd ec9fc8292e8d78bd rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 80000000 N |
| subs x21,x22,x23,sxtx #3 :: rd d254c4d0eb15b506 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 80000000 N |
| subs x21,x22,x23,sxtx #4 :: rd aed564d79250556e rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 80000000 N |
| ADD/SUB(extended reg)(32) |
| add w21,w22,w23,uxtb #0 :: rd 00000000297c4707 rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 |
| add w21,w22,w23,uxtb #1 :: rd 00000000a60b350b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 |
| add w21,w22,w23,uxtb #2 :: rd 00000000d56f5615 rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000 |
| add w21,w22,w23,uxtb #3 :: rd 00000000ff3a5596 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 00000000 |
| add w21,w22,w23,uxtb #4 :: rd 00000000055bf2ae rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| add w21,w22,w23,uxth #0 :: rd 00000000297ca007 rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 |
| add w21,w22,w23,uxth #1 :: rd 00000000a60b470b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 |
| add w21,w22,w23,uxth #2 :: rd 00000000d5712e15 rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000 |
| add w21,w22,w23,uxth #3 :: rd 00000000ff3ef596 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 00000000 |
| add w21,w22,w23,uxth #4 :: rd 00000000056782ae rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| add w21,w22,w23,uxtw #0 :: rd 000000000aa2a007 rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 |
| add w21,w22,w23,uxtw #1 :: rd 00000000b7bd470b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 |
| add w21,w22,w23,uxtw #2 :: rd 000000007c512e15 rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000 |
| add w21,w22,w23,uxtw #3 :: rd 00000000135ef596 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 00000000 |
| add w21,w22,w23,uxtw #4 :: rd 00000000786782ae rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| add w21,w22,w23,uxtx #0 :: rd 000000000aa2a007 rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 |
| add w21,w22,w23,uxtx #1 :: rd 00000000b7bd470b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 |
| add w21,w22,w23,uxtx #2 :: rd 000000007c512e15 rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000 |
| add w21,w22,w23,uxtx #3 :: rd 00000000135ef596 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 00000000 |
| add w21,w22,w23,uxtx #4 :: rd 00000000786782ae rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| add w21,w22,w23,sxtb #0 :: rd 00000000297c4707 rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 |
| add w21,w22,w23,sxtb #1 :: rd 00000000a60b350b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 |
| add w21,w22,w23,sxtb #2 :: rd 00000000d56f5215 rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000 |
| add w21,w22,w23,sxtb #3 :: rd 00000000ff3a5596 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 00000000 |
| add w21,w22,w23,sxtb #4 :: rd 00000000055bf2ae rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| add w21,w22,w23,sxth #0 :: rd 00000000297ca007 rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 |
| add w21,w22,w23,sxth #1 :: rd 00000000a60b470b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 |
| add w21,w22,w23,sxth #2 :: rd 00000000d5712e15 rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000 |
| add w21,w22,w23,sxth #3 :: rd 00000000ff36f596 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 00000000 |
| add w21,w22,w23,sxth #4 :: rd 00000000055782ae rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| add w21,w22,w23,sxtw #0 :: rd 000000000aa2a007 rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 |
| add w21,w22,w23,sxtw #1 :: rd 00000000b7bd470b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 |
| add w21,w22,w23,sxtw #2 :: rd 000000007c512e15 rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000 |
| add w21,w22,w23,sxtw #3 :: rd 00000000135ef596 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 00000000 |
| add w21,w22,w23,sxtw #4 :: rd 00000000786782ae rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| add w21,w22,w23,sxtx #0 :: rd 000000000aa2a007 rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 |
| add w21,w22,w23,sxtx #1 :: rd 00000000b7bd470b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 |
| add w21,w22,w23,sxtx #2 :: rd 000000007c512e15 rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000 |
| add w21,w22,w23,sxtx #3 :: rd 00000000135ef596 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 00000000 |
| add w21,w22,w23,sxtx #4 :: rd 00000000786782ae rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| adds w21,w22,w23,uxtb #0 :: rd 00000000297c4707 rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 |
| adds w21,w22,w23,uxtb #1 :: rd 00000000a60b350b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 80000000 N |
| adds w21,w22,w23,uxtb #2 :: rd 00000000d56f5615 rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 80000000 N |
| adds w21,w22,w23,uxtb #3 :: rd 00000000ff3a5596 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 80000000 N |
| adds w21,w22,w23,uxtb #4 :: rd 00000000055bf2ae rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| adds w21,w22,w23,uxth #0 :: rd 00000000297ca007 rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 |
| adds w21,w22,w23,uxth #1 :: rd 00000000a60b470b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 80000000 N |
| adds w21,w22,w23,uxth #2 :: rd 00000000d5712e15 rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 80000000 N |
| adds w21,w22,w23,uxth #3 :: rd 00000000ff3ef596 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 80000000 N |
| adds w21,w22,w23,uxth #4 :: rd 00000000056782ae rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| adds w21,w22,w23,uxtw #0 :: rd 000000000aa2a007 rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 20000000 C |
| adds w21,w22,w23,uxtw #1 :: rd 00000000b7bd470b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 80000000 N |
| adds w21,w22,w23,uxtw #2 :: rd 000000007c512e15 rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 30000000 CV |
| adds w21,w22,w23,uxtw #3 :: rd 00000000135ef596 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 20000000 C |
| adds w21,w22,w23,uxtw #4 :: rd 00000000786782ae rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| adds w21,w22,w23,uxtx #0 :: rd 000000000aa2a007 rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 20000000 C |
| adds w21,w22,w23,uxtx #1 :: rd 00000000b7bd470b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 80000000 N |
| adds w21,w22,w23,uxtx #2 :: rd 000000007c512e15 rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 30000000 CV |
| adds w21,w22,w23,uxtx #3 :: rd 00000000135ef596 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 20000000 C |
| adds w21,w22,w23,uxtx #4 :: rd 00000000786782ae rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| adds w21,w22,w23,sxtb #0 :: rd 00000000297c4707 rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 |
| adds w21,w22,w23,sxtb #1 :: rd 00000000a60b350b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 80000000 N |
| adds w21,w22,w23,sxtb #2 :: rd 00000000d56f5215 rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv a0000000 N C |
| adds w21,w22,w23,sxtb #3 :: rd 00000000ff3a5596 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 80000000 N |
| adds w21,w22,w23,sxtb #4 :: rd 00000000055bf2ae rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| adds w21,w22,w23,sxth #0 :: rd 00000000297ca007 rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 |
| adds w21,w22,w23,sxth #1 :: rd 00000000a60b470b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 80000000 N |
| adds w21,w22,w23,sxth #2 :: rd 00000000d5712e15 rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 80000000 N |
| adds w21,w22,w23,sxth #3 :: rd 00000000ff36f596 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv a0000000 N C |
| adds w21,w22,w23,sxth #4 :: rd 00000000055782ae rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 20000000 C |
| adds w21,w22,w23,sxtw #0 :: rd 000000000aa2a007 rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 20000000 C |
| adds w21,w22,w23,sxtw #1 :: rd 00000000b7bd470b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 80000000 N |
| adds w21,w22,w23,sxtw #2 :: rd 000000007c512e15 rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 30000000 CV |
| adds w21,w22,w23,sxtw #3 :: rd 00000000135ef596 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 20000000 C |
| adds w21,w22,w23,sxtw #4 :: rd 00000000786782ae rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| adds w21,w22,w23,sxtx #0 :: rd 000000000aa2a007 rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 20000000 C |
| adds w21,w22,w23,sxtx #1 :: rd 00000000b7bd470b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 80000000 N |
| adds w21,w22,w23,sxtx #2 :: rd 000000007c512e15 rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 30000000 CV |
| adds w21,w22,w23,sxtx #3 :: rd 00000000135ef596 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 20000000 C |
| adds w21,w22,w23,sxtx #4 :: rd 00000000786782ae rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| sub w21,w22,w23,uxtb #0 :: rd 00000000297c462f rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 |
| sub w21,w22,w23,uxtb #1 :: rd 00000000a60b347b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 |
| sub w21,w22,w23,uxtb #2 :: rd 00000000d56f50bd rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000 |
| sub w21,w22,w23,uxtb #3 :: rd 00000000ff3a5506 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 00000000 |
| sub w21,w22,w23,uxtb #4 :: rd 00000000055be56e rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| sub w21,w22,w23,uxth #0 :: rd 00000000297bed2f rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 |
| sub w21,w22,w23,uxth #1 :: rd 00000000a60b227b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 |
| sub w21,w22,w23,uxth #2 :: rd 00000000d56d78bd rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000 |
| sub w21,w22,w23,uxth #3 :: rd 00000000ff35b506 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 00000000 |
| sub w21,w22,w23,uxth #4 :: rd 000000000550556e rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| sub w21,w22,w23,uxtw #0 :: rd 000000004855ed2f rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 |
| sub w21,w22,w23,uxtw #1 :: rd 000000009459227b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 |
| sub w21,w22,w23,uxtw #2 :: rd 000000002e8d78bd rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000 |
| sub w21,w22,w23,uxtw #3 :: rd 00000000eb15b506 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 00000000 |
| sub w21,w22,w23,uxtw #4 :: rd 000000009250556e rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| sub w21,w22,w23,uxtx #0 :: rd 000000004855ed2f rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 |
| sub w21,w22,w23,uxtx #1 :: rd 000000009459227b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 |
| sub w21,w22,w23,uxtx #2 :: rd 000000002e8d78bd rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000 |
| sub w21,w22,w23,uxtx #3 :: rd 00000000eb15b506 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 00000000 |
| sub w21,w22,w23,uxtx #4 :: rd 000000009250556e rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| sub w21,w22,w23,sxtb #0 :: rd 00000000297c462f rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 |
| sub w21,w22,w23,sxtb #1 :: rd 00000000a60b347b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 |
| sub w21,w22,w23,sxtb #2 :: rd 00000000d56f54bd rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000 |
| sub w21,w22,w23,sxtb #3 :: rd 00000000ff3a5506 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 00000000 |
| sub w21,w22,w23,sxtb #4 :: rd 00000000055be56e rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| sub w21,w22,w23,sxth #0 :: rd 00000000297bed2f rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 |
| sub w21,w22,w23,sxth #1 :: rd 00000000a60b227b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 |
| sub w21,w22,w23,sxth #2 :: rd 00000000d56d78bd rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000 |
| sub w21,w22,w23,sxth #3 :: rd 00000000ff3db506 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 00000000 |
| sub w21,w22,w23,sxth #4 :: rd 000000000560556e rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| sub w21,w22,w23,sxtw #0 :: rd 000000004855ed2f rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 |
| sub w21,w22,w23,sxtw #1 :: rd 000000009459227b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 |
| sub w21,w22,w23,sxtw #2 :: rd 000000002e8d78bd rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000 |
| sub w21,w22,w23,sxtw #3 :: rd 00000000eb15b506 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 00000000 |
| sub w21,w22,w23,sxtw #4 :: rd 000000009250556e rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| sub w21,w22,w23,sxtx #0 :: rd 000000004855ed2f rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 |
| sub w21,w22,w23,sxtx #1 :: rd 000000009459227b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 |
| sub w21,w22,w23,sxtx #2 :: rd 000000002e8d78bd rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000 |
| sub w21,w22,w23,sxtx #3 :: rd 00000000eb15b506 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 00000000 |
| sub w21,w22,w23,sxtx #4 :: rd 000000009250556e rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| subs w21,w22,w23,uxtb #0 :: rd 00000000297c462f rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 20000000 C |
| subs w21,w22,w23,uxtb #1 :: rd 00000000a60b347b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv a0000000 N C |
| subs w21,w22,w23,uxtb #2 :: rd 00000000d56f50bd rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv a0000000 N C |
| subs w21,w22,w23,uxtb #3 :: rd 00000000ff3a5506 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv a0000000 N C |
| subs w21,w22,w23,uxtb #4 :: rd 00000000055be56e rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 20000000 C |
| subs w21,w22,w23,uxth #0 :: rd 00000000297bed2f rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 20000000 C |
| subs w21,w22,w23,uxth #1 :: rd 00000000a60b227b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv a0000000 N C |
| subs w21,w22,w23,uxth #2 :: rd 00000000d56d78bd rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv a0000000 N C |
| subs w21,w22,w23,uxth #3 :: rd 00000000ff35b506 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv a0000000 N C |
| subs w21,w22,w23,uxth #4 :: rd 000000000550556e rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 20000000 C |
| subs w21,w22,w23,uxtw #0 :: rd 000000004855ed2f rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 |
| subs w21,w22,w23,uxtw #1 :: rd 000000009459227b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv a0000000 N C |
| subs w21,w22,w23,uxtw #2 :: rd 000000002e8d78bd rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 20000000 C |
| subs w21,w22,w23,uxtw #3 :: rd 00000000eb15b506 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv a0000000 N C |
| subs w21,w22,w23,uxtw #4 :: rd 000000009250556e rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 80000000 N |
| subs w21,w22,w23,uxtx #0 :: rd 000000004855ed2f rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 |
| subs w21,w22,w23,uxtx #1 :: rd 000000009459227b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv a0000000 N C |
| subs w21,w22,w23,uxtx #2 :: rd 000000002e8d78bd rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 20000000 C |
| subs w21,w22,w23,uxtx #3 :: rd 00000000eb15b506 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv a0000000 N C |
| subs w21,w22,w23,uxtx #4 :: rd 000000009250556e rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 80000000 N |
| subs w21,w22,w23,sxtb #0 :: rd 00000000297c462f rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 20000000 C |
| subs w21,w22,w23,sxtb #1 :: rd 00000000a60b347b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv a0000000 N C |
| subs w21,w22,w23,sxtb #2 :: rd 00000000d56f54bd rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 80000000 N |
| subs w21,w22,w23,sxtb #3 :: rd 00000000ff3a5506 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv a0000000 N C |
| subs w21,w22,w23,sxtb #4 :: rd 00000000055be56e rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 20000000 C |
| subs w21,w22,w23,sxth #0 :: rd 00000000297bed2f rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 20000000 C |
| subs w21,w22,w23,sxth #1 :: rd 00000000a60b227b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv a0000000 N C |
| subs w21,w22,w23,sxth #2 :: rd 00000000d56d78bd rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv a0000000 N C |
| subs w21,w22,w23,sxth #3 :: rd 00000000ff3db506 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 80000000 N |
| subs w21,w22,w23,sxth #4 :: rd 000000000560556e rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 |
| subs w21,w22,w23,sxtw #0 :: rd 000000004855ed2f rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 |
| subs w21,w22,w23,sxtw #1 :: rd 000000009459227b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv a0000000 N C |
| subs w21,w22,w23,sxtw #2 :: rd 000000002e8d78bd rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 20000000 C |
| subs w21,w22,w23,sxtw #3 :: rd 00000000eb15b506 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv a0000000 N C |
| subs w21,w22,w23,sxtw #4 :: rd 000000009250556e rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 80000000 N |
| subs w21,w22,w23,sxtx #0 :: rd 000000004855ed2f rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 |
| subs w21,w22,w23,sxtx #1 :: rd 000000009459227b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv a0000000 N C |
| subs w21,w22,w23,sxtx #2 :: rd 000000002e8d78bd rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 20000000 C |
| subs w21,w22,w23,sxtx #3 :: rd 00000000eb15b506 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv a0000000 N C |
| subs w21,w22,w23,sxtx #4 :: rd 000000009250556e rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 80000000 N |
| CCMP/CCMN(imm)(64) |
| msr nzcv,x24; ccmp x25,#17,#0x0,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,#17,#0x1,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,#17,#0x2,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,#17,#0x3,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,#17,#0x4,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,#17,#0x5,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,#17,#0x6,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,#17,#0x7,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,#17,#0x8,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,#17,#0x9,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,#17,#0xA,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,#17,#0xB,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,#17,#0xC,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,#17,#0xD,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,#17,#0xE,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,#17,#0xF,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| |
| msr nzcv,x24; ccmp x25,#17,#0x0,ne; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmp x25,#17,#0x1,ne; mrs x23,nzcv :: rd 0000000010000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 10000000 V |
| msr nzcv,x24; ccmp x25,#17,#0x2,ne; mrs x23,nzcv :: rd 0000000020000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 20000000 C |
| msr nzcv,x24; ccmp x25,#17,#0x3,ne; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmp x25,#17,#0x4,ne; mrs x23,nzcv :: rd 0000000040000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 40000000 Z |
| msr nzcv,x24; ccmp x25,#17,#0x5,ne; mrs x23,nzcv :: rd 0000000050000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 50000000 Z V |
| msr nzcv,x24; ccmp x25,#17,#0x6,ne; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,#17,#0x7,ne; mrs x23,nzcv :: rd 0000000070000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 70000000 ZCV |
| msr nzcv,x24; ccmp x25,#17,#0x8,ne; mrs x23,nzcv :: rd 0000000080000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 80000000 N |
| msr nzcv,x24; ccmp x25,#17,#0x9,ne; mrs x23,nzcv :: rd 0000000090000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 90000000 N V |
| msr nzcv,x24; ccmp x25,#17,#0xA,ne; mrs x23,nzcv :: rd 00000000a0000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv a0000000 N C |
| msr nzcv,x24; ccmp x25,#17,#0xB,ne; mrs x23,nzcv :: rd 00000000b0000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv b0000000 N CV |
| msr nzcv,x24; ccmp x25,#17,#0xC,ne; mrs x23,nzcv :: rd 00000000c0000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv c0000000 NZ |
| msr nzcv,x24; ccmp x25,#17,#0xD,ne; mrs x23,nzcv :: rd 00000000d0000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv d0000000 NZ V |
| msr nzcv,x24; ccmp x25,#17,#0xE,ne; mrs x23,nzcv :: rd 00000000e0000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv e0000000 NZC |
| msr nzcv,x24; ccmp x25,#17,#0xF,ne; mrs x23,nzcv :: rd 00000000f0000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv f0000000 NZCV |
| |
| msr nzcv,x24; ccmp x25,#17,#0x6,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,#17,#0x5,eq; mrs x23,nzcv :: rd 0000000050000000 rm 0000000020000000, rn 0000000000000011, cin 0, nzcv 50000000 Z V |
| msr nzcv,x24; ccmp x25,#17,#0x3,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,#17,#0x7,eq; mrs x23,nzcv :: rd 0000000070000000 rm ffffffff80000000, rn 0000000000000011, cin 0, nzcv 70000000 ZCV |
| msr nzcv,x24; ccmp x25,#17,#0x6,lt; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,#17,#0x5,lt; mrs x23,nzcv :: rd 0000000050000000 rm 0000000020000000, rn 0000000000000011, cin 0, nzcv 50000000 Z V |
| msr nzcv,x24; ccmp x25,#17,#0x3,lt; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmp x25,#17,#0x7,lt; mrs x23,nzcv :: rd 0000000060000000 rm ffffffff80000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,#17,#0x6,gt; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,#17,#0x5,gt; mrs x23,nzcv :: rd 0000000060000000 rm 0000000020000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,#17,#0x3,gt; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmp x25,#17,#0x7,gt; mrs x23,nzcv :: rd 0000000070000000 rm ffffffff80000000, rn 0000000000000011, cin 0, nzcv 70000000 ZCV |
| msr nzcv,x24; ccmp x25,#17,#0x6,ne; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,#17,#0x5,ne; mrs x23,nzcv :: rd 0000000060000000 rm 0000000020000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,#17,#0x3,ne; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmp x25,#17,#0x7,ne; mrs x23,nzcv :: rd 0000000060000000 rm ffffffff80000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,#18,#0x6,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,#18,#0x5,eq; mrs x23,nzcv :: rd 0000000050000000 rm 0000000020000000, rn 0000000000000011, cin 0, nzcv 50000000 Z V |
| msr nzcv,x24; ccmp x25,#18,#0x3,eq; mrs x23,nzcv :: rd 0000000080000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 80000000 N |
| msr nzcv,x24; ccmp x25,#18,#0x7,eq; mrs x23,nzcv :: rd 0000000070000000 rm ffffffff80000000, rn 0000000000000011, cin 0, nzcv 70000000 ZCV |
| msr nzcv,x24; ccmp x25,#18,#0x6,lt; mrs x23,nzcv :: rd 0000000080000000 rm 0000000010000000, rn 0000000000000011, cin 0, nzcv 80000000 N |
| msr nzcv,x24; ccmp x25,#18,#0x5,lt; mrs x23,nzcv :: rd 0000000050000000 rm 0000000020000000, rn 0000000000000011, cin 0, nzcv 50000000 Z V |
| msr nzcv,x24; ccmp x25,#18,#0x3,lt; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmp x25,#18,#0x7,lt; mrs x23,nzcv :: rd 0000000080000000 rm ffffffff80000000, rn 0000000000000011, cin 0, nzcv 80000000 N |
| msr nzcv,x24; ccmp x25,#18,#0x6,gt; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,#18,#0x5,gt; mrs x23,nzcv :: rd 0000000080000000 rm 0000000020000000, rn 0000000000000011, cin 0, nzcv 80000000 N |
| msr nzcv,x24; ccmp x25,#18,#0x3,gt; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmp x25,#18,#0x7,gt; mrs x23,nzcv :: rd 0000000070000000 rm ffffffff80000000, rn 0000000000000011, cin 0, nzcv 70000000 ZCV |
| msr nzcv,x24; ccmp x25,#18,#0x6,ne; mrs x23,nzcv :: rd 0000000080000000 rm 0000000010000000, rn 0000000000000011, cin 0, nzcv 80000000 N |
| msr nzcv,x24; ccmp x25,#18,#0x5,ne; mrs x23,nzcv :: rd 0000000080000000 rm 0000000020000000, rn 0000000000000011, cin 0, nzcv 80000000 N |
| msr nzcv,x24; ccmp x25,#18,#0x3,ne; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmp x25,#18,#0x7,ne; mrs x23,nzcv :: rd 0000000080000000 rm ffffffff80000000, rn 0000000000000011, cin 0, nzcv 80000000 N |
| msr nzcv,x24; ccmn x25,#17,#0x0,eq; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,#17,#0x1,eq; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,#17,#0x2,eq; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,#17,#0x3,eq; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,#17,#0x4,eq; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,#17,#0x5,eq; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,#17,#0x6,eq; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,#17,#0x7,eq; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,#17,#0x8,eq; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,#17,#0x9,eq; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,#17,#0xA,eq; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,#17,#0xB,eq; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,#17,#0xC,eq; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,#17,#0xD,eq; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,#17,#0xE,eq; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,#17,#0xF,eq; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 00000000 |
| |
| msr nzcv,x24; ccmn x25,#17,#0x0,ne; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,#17,#0x1,ne; mrs x23,nzcv :: rd 0000000010000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 10000000 V |
| msr nzcv,x24; ccmn x25,#17,#0x2,ne; mrs x23,nzcv :: rd 0000000020000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 20000000 C |
| msr nzcv,x24; ccmn x25,#17,#0x3,ne; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmn x25,#17,#0x4,ne; mrs x23,nzcv :: rd 0000000040000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 40000000 Z |
| msr nzcv,x24; ccmn x25,#17,#0x5,ne; mrs x23,nzcv :: rd 0000000050000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 50000000 Z V |
| msr nzcv,x24; ccmn x25,#17,#0x6,ne; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn x25,#17,#0x7,ne; mrs x23,nzcv :: rd 0000000070000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 70000000 ZCV |
| msr nzcv,x24; ccmn x25,#17,#0x8,ne; mrs x23,nzcv :: rd 0000000080000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 80000000 N |
| msr nzcv,x24; ccmn x25,#17,#0x9,ne; mrs x23,nzcv :: rd 0000000090000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 90000000 N V |
| msr nzcv,x24; ccmn x25,#17,#0xA,ne; mrs x23,nzcv :: rd 00000000a0000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv a0000000 N C |
| msr nzcv,x24; ccmn x25,#17,#0xB,ne; mrs x23,nzcv :: rd 00000000b0000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv b0000000 N CV |
| msr nzcv,x24; ccmn x25,#17,#0xC,ne; mrs x23,nzcv :: rd 00000000c0000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv c0000000 NZ |
| msr nzcv,x24; ccmn x25,#17,#0xD,ne; mrs x23,nzcv :: rd 00000000d0000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv d0000000 NZ V |
| msr nzcv,x24; ccmn x25,#17,#0xE,ne; mrs x23,nzcv :: rd 00000000e0000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv e0000000 NZC |
| msr nzcv,x24; ccmn x25,#17,#0xF,ne; mrs x23,nzcv :: rd 00000000f0000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv f0000000 NZCV |
| |
| msr nzcv,x24; ccmn x25,#17,#0x6,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn ffffffffffffffef, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn x25,#17,#0x5,eq; mrs x23,nzcv :: rd 0000000050000000 rm 0000000020000000, rn ffffffffffffffef, cin 0, nzcv 50000000 Z V |
| msr nzcv,x24; ccmn x25,#17,#0x3,eq; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,#17,#0x7,eq; mrs x23,nzcv :: rd 0000000070000000 rm ffffffff80000000, rn ffffffffffffffef, cin 0, nzcv 70000000 ZCV |
| msr nzcv,x24; ccmn x25,#17,#0x6,lt; mrs x23,nzcv :: rd 0000000000000000 rm 0000000010000000, rn ffffffffffffffef, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,#17,#0x5,lt; mrs x23,nzcv :: rd 0000000050000000 rm 0000000020000000, rn ffffffffffffffef, cin 0, nzcv 50000000 Z V |
| msr nzcv,x24; ccmn x25,#17,#0x3,lt; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmn x25,#17,#0x7,lt; mrs x23,nzcv :: rd 0000000000000000 rm ffffffff80000000, rn ffffffffffffffef, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,#17,#0x6,gt; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn ffffffffffffffef, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn x25,#17,#0x5,gt; mrs x23,nzcv :: rd 0000000000000000 rm 0000000020000000, rn ffffffffffffffef, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,#17,#0x3,gt; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmn x25,#17,#0x7,gt; mrs x23,nzcv :: rd 0000000070000000 rm ffffffff80000000, rn ffffffffffffffef, cin 0, nzcv 70000000 ZCV |
| msr nzcv,x24; ccmn x25,#17,#0x6,ne; mrs x23,nzcv :: rd 0000000000000000 rm 0000000010000000, rn ffffffffffffffef, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,#17,#0x5,ne; mrs x23,nzcv :: rd 0000000000000000 rm 0000000020000000, rn ffffffffffffffef, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,#17,#0x3,ne; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmn x25,#17,#0x7,ne; mrs x23,nzcv :: rd 0000000000000000 rm ffffffff80000000, rn ffffffffffffffef, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,#18,#0x6,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn ffffffffffffffef, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn x25,#18,#0x5,eq; mrs x23,nzcv :: rd 0000000050000000 rm 0000000020000000, rn ffffffffffffffef, cin 0, nzcv 50000000 Z V |
| msr nzcv,x24; ccmn x25,#18,#0x3,eq; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,#18,#0x7,eq; mrs x23,nzcv :: rd 0000000070000000 rm ffffffff80000000, rn ffffffffffffffef, cin 0, nzcv 70000000 ZCV |
| msr nzcv,x24; ccmn x25,#18,#0x6,lt; mrs x23,nzcv :: rd 0000000000000000 rm 0000000010000000, rn ffffffffffffffef, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,#18,#0x5,lt; mrs x23,nzcv :: rd 0000000050000000 rm 0000000020000000, rn ffffffffffffffef, cin 0, nzcv 50000000 Z V |
| msr nzcv,x24; ccmn x25,#18,#0x3,lt; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmn x25,#18,#0x7,lt; mrs x23,nzcv :: rd 0000000000000000 rm ffffffff80000000, rn ffffffffffffffef, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,#18,#0x6,gt; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn ffffffffffffffef, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn x25,#18,#0x5,gt; mrs x23,nzcv :: rd 0000000000000000 rm 0000000020000000, rn ffffffffffffffef, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,#18,#0x3,gt; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmn x25,#18,#0x7,gt; mrs x23,nzcv :: rd 0000000070000000 rm ffffffff80000000, rn ffffffffffffffef, cin 0, nzcv 70000000 ZCV |
| msr nzcv,x24; ccmn x25,#18,#0x6,ne; mrs x23,nzcv :: rd 0000000000000000 rm 0000000010000000, rn ffffffffffffffef, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,#18,#0x5,ne; mrs x23,nzcv :: rd 0000000000000000 rm 0000000020000000, rn ffffffffffffffef, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,#18,#0x3,ne; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmn x25,#18,#0x7,ne; mrs x23,nzcv :: rd 0000000000000000 rm ffffffff80000000, rn ffffffffffffffef, cin 0, nzcv 00000000 |
| CCMP/CCMN(imm)(32) |
| msr nzcv,x24; ccmp w25,#17,#0xF,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,#17,#0xF,ne; mrs x23,nzcv :: rd 00000000f0000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv f0000000 NZCV |
| msr nzcv,x24; ccmp w25,#17,#0xF,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000001100000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,#17,#0xF,ne; mrs x23,nzcv :: rd 00000000f0000000 rm 0000000040000000, rn 0000001100000011, cin 0, nzcv f0000000 NZCV |
| msr nzcv,x24; ccmp x25,#17,#0xF,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,#17,#0xF,ne; mrs x23,nzcv :: rd 00000000f0000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv f0000000 NZCV |
| msr nzcv,x24; ccmp x25,#17,#0xF,eq; mrs x23,nzcv :: rd 0000000020000000 rm 0000000040000000, rn 0000001100000011, cin 0, nzcv 20000000 C |
| msr nzcv,x24; ccmp x25,#17,#0xF,ne; mrs x23,nzcv :: rd 00000000f0000000 rm 0000000040000000, rn 0000001100000011, cin 0, nzcv f0000000 NZCV |
| msr nzcv,x24; ccmp w25,#17,#0x0,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,#17,#0x1,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,#17,#0x2,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,#17,#0x3,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,#17,#0x4,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,#17,#0x5,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,#17,#0x6,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,#17,#0x7,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,#17,#0x8,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,#17,#0x9,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,#17,#0xA,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,#17,#0xB,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,#17,#0xC,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,#17,#0xD,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,#17,#0xE,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,#17,#0xF,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| |
| msr nzcv,x24; ccmp w25,#17,#0x0,ne; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmp w25,#17,#0x1,ne; mrs x23,nzcv :: rd 0000000010000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 10000000 V |
| msr nzcv,x24; ccmp w25,#17,#0x2,ne; mrs x23,nzcv :: rd 0000000020000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 20000000 C |
| msr nzcv,x24; ccmp w25,#17,#0x3,ne; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmp w25,#17,#0x4,ne; mrs x23,nzcv :: rd 0000000040000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 40000000 Z |
| msr nzcv,x24; ccmp w25,#17,#0x5,ne; mrs x23,nzcv :: rd 0000000050000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 50000000 Z V |
| msr nzcv,x24; ccmp w25,#17,#0x6,ne; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,#17,#0x7,ne; mrs x23,nzcv :: rd 0000000070000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 70000000 ZCV |
| msr nzcv,x24; ccmp w25,#17,#0x8,ne; mrs x23,nzcv :: rd 0000000080000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 80000000 N |
| msr nzcv,x24; ccmp w25,#17,#0x9,ne; mrs x23,nzcv :: rd 0000000090000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 90000000 N V |
| msr nzcv,x24; ccmp w25,#17,#0xA,ne; mrs x23,nzcv :: rd 00000000a0000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv a0000000 N C |
| msr nzcv,x24; ccmp w25,#17,#0xB,ne; mrs x23,nzcv :: rd 00000000b0000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv b0000000 N CV |
| msr nzcv,x24; ccmp w25,#17,#0xC,ne; mrs x23,nzcv :: rd 00000000c0000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv c0000000 NZ |
| msr nzcv,x24; ccmp w25,#17,#0xD,ne; mrs x23,nzcv :: rd 00000000d0000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv d0000000 NZ V |
| msr nzcv,x24; ccmp w25,#17,#0xE,ne; mrs x23,nzcv :: rd 00000000e0000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv e0000000 NZC |
| msr nzcv,x24; ccmp w25,#17,#0xF,ne; mrs x23,nzcv :: rd 00000000f0000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv f0000000 NZCV |
| |
| msr nzcv,x24; ccmp w25,#17,#0x6,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,#17,#0x5,eq; mrs x23,nzcv :: rd 0000000050000000 rm 0000000020000000, rn 0000000000000011, cin 0, nzcv 50000000 Z V |
| msr nzcv,x24; ccmp w25,#17,#0x3,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,#17,#0x7,eq; mrs x23,nzcv :: rd 0000000070000000 rm ffffffff80000000, rn 0000000000000011, cin 0, nzcv 70000000 ZCV |
| msr nzcv,x24; ccmp w25,#17,#0x6,lt; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,#17,#0x5,lt; mrs x23,nzcv :: rd 0000000050000000 rm 0000000020000000, rn 0000000000000011, cin 0, nzcv 50000000 Z V |
| msr nzcv,x24; ccmp w25,#17,#0x3,lt; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmp w25,#17,#0x7,lt; mrs x23,nzcv :: rd 0000000060000000 rm ffffffff80000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,#17,#0x6,gt; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,#17,#0x5,gt; mrs x23,nzcv :: rd 0000000060000000 rm 0000000020000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,#17,#0x3,gt; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmp w25,#17,#0x7,gt; mrs x23,nzcv :: rd 0000000070000000 rm ffffffff80000000, rn 0000000000000011, cin 0, nzcv 70000000 ZCV |
| msr nzcv,x24; ccmp w25,#17,#0x6,ne; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,#17,#0x5,ne; mrs x23,nzcv :: rd 0000000060000000 rm 0000000020000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,#17,#0x3,ne; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmp w25,#17,#0x7,ne; mrs x23,nzcv :: rd 0000000060000000 rm ffffffff80000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,#18,#0x6,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,#18,#0x5,eq; mrs x23,nzcv :: rd 0000000050000000 rm 0000000020000000, rn 0000000000000011, cin 0, nzcv 50000000 Z V |
| msr nzcv,x24; ccmp w25,#18,#0x3,eq; mrs x23,nzcv :: rd 0000000080000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 80000000 N |
| msr nzcv,x24; ccmp w25,#18,#0x7,eq; mrs x23,nzcv :: rd 0000000070000000 rm ffffffff80000000, rn 0000000000000011, cin 0, nzcv 70000000 ZCV |
| msr nzcv,x24; ccmp w25,#18,#0x6,lt; mrs x23,nzcv :: rd 0000000080000000 rm 0000000010000000, rn 0000000000000011, cin 0, nzcv 80000000 N |
| msr nzcv,x24; ccmp w25,#18,#0x5,lt; mrs x23,nzcv :: rd 0000000050000000 rm 0000000020000000, rn 0000000000000011, cin 0, nzcv 50000000 Z V |
| msr nzcv,x24; ccmp w25,#18,#0x3,lt; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmp w25,#18,#0x7,lt; mrs x23,nzcv :: rd 0000000080000000 rm ffffffff80000000, rn 0000000000000011, cin 0, nzcv 80000000 N |
| msr nzcv,x24; ccmp w25,#18,#0x6,gt; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,#18,#0x5,gt; mrs x23,nzcv :: rd 0000000080000000 rm 0000000020000000, rn 0000000000000011, cin 0, nzcv 80000000 N |
| msr nzcv,x24; ccmp w25,#18,#0x3,gt; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmp w25,#18,#0x7,gt; mrs x23,nzcv :: rd 0000000070000000 rm ffffffff80000000, rn 0000000000000011, cin 0, nzcv 70000000 ZCV |
| msr nzcv,x24; ccmp w25,#18,#0x6,ne; mrs x23,nzcv :: rd 0000000080000000 rm 0000000010000000, rn 0000000000000011, cin 0, nzcv 80000000 N |
| msr nzcv,x24; ccmp w25,#18,#0x5,ne; mrs x23,nzcv :: rd 0000000080000000 rm 0000000020000000, rn 0000000000000011, cin 0, nzcv 80000000 N |
| msr nzcv,x24; ccmp w25,#18,#0x3,ne; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn 0000000000000011, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmp w25,#18,#0x7,ne; mrs x23,nzcv :: rd 0000000080000000 rm ffffffff80000000, rn 0000000000000011, cin 0, nzcv 80000000 N |
| msr nzcv,x24; ccmn w25,#17,#0xF,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,#17,#0xF,ne; mrs x23,nzcv :: rd 00000000f0000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv f0000000 NZCV |
| msr nzcv,x24; ccmn w25,#17,#0xF,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffeeffffffef, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,#17,#0xF,ne; mrs x23,nzcv :: rd 00000000f0000000 rm 0000000040000000, rn ffffffeeffffffef, cin 0, nzcv f0000000 NZCV |
| msr nzcv,x24; ccmn x25,#17,#0xF,eq; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,#17,#0xF,ne; mrs x23,nzcv :: rd 00000000f0000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv f0000000 NZCV |
| msr nzcv,x24; ccmn x25,#17,#0xF,eq; mrs x23,nzcv :: rd 0000000080000000 rm 0000000040000000, rn ffffffeeffffffef, cin 0, nzcv 80000000 N |
| msr nzcv,x24; ccmn x25,#17,#0xF,ne; mrs x23,nzcv :: rd 00000000f0000000 rm 0000000040000000, rn ffffffeeffffffef, cin 0, nzcv f0000000 NZCV |
| msr nzcv,x24; ccmn w25,#17,#0x0,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,#17,#0x1,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,#17,#0x2,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,#17,#0x3,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,#17,#0x4,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,#17,#0x5,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,#17,#0x6,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,#17,#0x7,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,#17,#0x8,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,#17,#0x9,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,#17,#0xA,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,#17,#0xB,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,#17,#0xC,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,#17,#0xD,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,#17,#0xE,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,#17,#0xF,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 60000000 ZC |
| |
| msr nzcv,x24; ccmn w25,#17,#0x0,ne; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn w25,#17,#0x1,ne; mrs x23,nzcv :: rd 0000000010000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 10000000 V |
| msr nzcv,x24; ccmn w25,#17,#0x2,ne; mrs x23,nzcv :: rd 0000000020000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 20000000 C |
| msr nzcv,x24; ccmn w25,#17,#0x3,ne; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmn w25,#17,#0x4,ne; mrs x23,nzcv :: rd 0000000040000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 40000000 Z |
| msr nzcv,x24; ccmn w25,#17,#0x5,ne; mrs x23,nzcv :: rd 0000000050000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 50000000 Z V |
| msr nzcv,x24; ccmn w25,#17,#0x6,ne; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,#17,#0x7,ne; mrs x23,nzcv :: rd 0000000070000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 70000000 ZCV |
| msr nzcv,x24; ccmn w25,#17,#0x8,ne; mrs x23,nzcv :: rd 0000000080000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 80000000 N |
| msr nzcv,x24; ccmn w25,#17,#0x9,ne; mrs x23,nzcv :: rd 0000000090000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 90000000 N V |
| msr nzcv,x24; ccmn w25,#17,#0xA,ne; mrs x23,nzcv :: rd 00000000a0000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv a0000000 N C |
| msr nzcv,x24; ccmn w25,#17,#0xB,ne; mrs x23,nzcv :: rd 00000000b0000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv b0000000 N CV |
| msr nzcv,x24; ccmn w25,#17,#0xC,ne; mrs x23,nzcv :: rd 00000000c0000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv c0000000 NZ |
| msr nzcv,x24; ccmn w25,#17,#0xD,ne; mrs x23,nzcv :: rd 00000000d0000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv d0000000 NZ V |
| msr nzcv,x24; ccmn w25,#17,#0xE,ne; mrs x23,nzcv :: rd 00000000e0000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv e0000000 NZC |
| msr nzcv,x24; ccmn w25,#17,#0xF,ne; mrs x23,nzcv :: rd 00000000f0000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv f0000000 NZCV |
| |
| msr nzcv,x24; ccmn w25,#17,#0x6,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn ffffffffffffffef, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,#17,#0x5,eq; mrs x23,nzcv :: rd 0000000050000000 rm 0000000020000000, rn ffffffffffffffef, cin 0, nzcv 50000000 Z V |
| msr nzcv,x24; ccmn w25,#17,#0x3,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,#17,#0x7,eq; mrs x23,nzcv :: rd 0000000070000000 rm ffffffff80000000, rn ffffffffffffffef, cin 0, nzcv 70000000 ZCV |
| msr nzcv,x24; ccmn w25,#17,#0x6,lt; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn ffffffffffffffef, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,#17,#0x5,lt; mrs x23,nzcv :: rd 0000000050000000 rm 0000000020000000, rn ffffffffffffffef, cin 0, nzcv 50000000 Z V |
| msr nzcv,x24; ccmn w25,#17,#0x3,lt; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmn w25,#17,#0x7,lt; mrs x23,nzcv :: rd 0000000060000000 rm ffffffff80000000, rn ffffffffffffffef, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,#17,#0x6,gt; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn ffffffffffffffef, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,#17,#0x5,gt; mrs x23,nzcv :: rd 0000000060000000 rm 0000000020000000, rn ffffffffffffffef, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,#17,#0x3,gt; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmn w25,#17,#0x7,gt; mrs x23,nzcv :: rd 0000000070000000 rm ffffffff80000000, rn ffffffffffffffef, cin 0, nzcv 70000000 ZCV |
| msr nzcv,x24; ccmn w25,#17,#0x6,ne; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn ffffffffffffffef, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,#17,#0x5,ne; mrs x23,nzcv :: rd 0000000060000000 rm 0000000020000000, rn ffffffffffffffef, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,#17,#0x3,ne; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmn w25,#17,#0x7,ne; mrs x23,nzcv :: rd 0000000060000000 rm ffffffff80000000, rn ffffffffffffffef, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,#18,#0x6,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn ffffffffffffffef, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,#18,#0x5,eq; mrs x23,nzcv :: rd 0000000050000000 rm 0000000020000000, rn ffffffffffffffef, cin 0, nzcv 50000000 Z V |
| msr nzcv,x24; ccmn w25,#18,#0x3,eq; mrs x23,nzcv :: rd 0000000020000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 20000000 C |
| msr nzcv,x24; ccmn w25,#18,#0x7,eq; mrs x23,nzcv :: rd 0000000070000000 rm ffffffff80000000, rn ffffffffffffffef, cin 0, nzcv 70000000 ZCV |
| msr nzcv,x24; ccmn w25,#18,#0x6,lt; mrs x23,nzcv :: rd 0000000020000000 rm 0000000010000000, rn ffffffffffffffef, cin 0, nzcv 20000000 C |
| msr nzcv,x24; ccmn w25,#18,#0x5,lt; mrs x23,nzcv :: rd 0000000050000000 rm 0000000020000000, rn ffffffffffffffef, cin 0, nzcv 50000000 Z V |
| msr nzcv,x24; ccmn w25,#18,#0x3,lt; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmn w25,#18,#0x7,lt; mrs x23,nzcv :: rd 0000000020000000 rm ffffffff80000000, rn ffffffffffffffef, cin 0, nzcv 20000000 C |
| msr nzcv,x24; ccmn w25,#18,#0x6,gt; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn ffffffffffffffef, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,#18,#0x5,gt; mrs x23,nzcv :: rd 0000000020000000 rm 0000000020000000, rn ffffffffffffffef, cin 0, nzcv 20000000 C |
| msr nzcv,x24; ccmn w25,#18,#0x3,gt; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmn w25,#18,#0x7,gt; mrs x23,nzcv :: rd 0000000070000000 rm ffffffff80000000, rn ffffffffffffffef, cin 0, nzcv 70000000 ZCV |
| msr nzcv,x24; ccmn w25,#18,#0x6,ne; mrs x23,nzcv :: rd 0000000020000000 rm 0000000010000000, rn ffffffffffffffef, cin 0, nzcv 20000000 C |
| msr nzcv,x24; ccmn w25,#18,#0x5,ne; mrs x23,nzcv :: rd 0000000020000000 rm 0000000020000000, rn ffffffffffffffef, cin 0, nzcv 20000000 C |
| msr nzcv,x24; ccmn w25,#18,#0x3,ne; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn ffffffffffffffef, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmn w25,#18,#0x7,ne; mrs x23,nzcv :: rd 0000000020000000 rm ffffffff80000000, rn ffffffffffffffef, cin 0, nzcv 20000000 C |
| CCMP/CCMN(reg)(64) |
| msr nzcv,x24; ccmp x25,x26,#0x0,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,x26,#0x1,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,x26,#0x2,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,x26,#0x3,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,x26,#0x4,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,x26,#0x5,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,x26,#0x6,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,x26,#0x7,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,x26,#0x8,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,x26,#0x9,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,x26,#0xA,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,x26,#0xB,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,x26,#0xC,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,x26,#0xD,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,x26,#0xE,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,x26,#0xF,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| |
| msr nzcv,x24; ccmp x25,x26,#0x0,ne; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmp x25,x26,#0x1,ne; mrs x23,nzcv :: rd 0000000010000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 10000000 V |
| msr nzcv,x24; ccmp x25,x26,#0x2,ne; mrs x23,nzcv :: rd 0000000020000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 20000000 C |
| msr nzcv,x24; ccmp x25,x26,#0x3,ne; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmp x25,x26,#0x4,ne; mrs x23,nzcv :: rd 0000000040000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 40000000 Z |
| msr nzcv,x24; ccmp x25,x26,#0x5,ne; mrs x23,nzcv :: rd 0000000050000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 50000000 Z V |
| msr nzcv,x24; ccmp x25,x26,#0x6,ne; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,x26,#0x7,ne; mrs x23,nzcv :: rd 0000000070000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 70000000 ZCV |
| msr nzcv,x24; ccmp x25,x26,#0x8,ne; mrs x23,nzcv :: rd 0000000080000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 80000000 N |
| msr nzcv,x24; ccmp x25,x26,#0x9,ne; mrs x23,nzcv :: rd 0000000090000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 90000000 N V |
| msr nzcv,x24; ccmp x25,x26,#0xA,ne; mrs x23,nzcv :: rd 00000000a0000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv a0000000 N C |
| msr nzcv,x24; ccmp x25,x26,#0xB,ne; mrs x23,nzcv :: rd 00000000b0000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv b0000000 N CV |
| msr nzcv,x24; ccmp x25,x26,#0xC,ne; mrs x23,nzcv :: rd 00000000c0000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv c0000000 NZ |
| msr nzcv,x24; ccmp x25,x26,#0xD,ne; mrs x23,nzcv :: rd 00000000d0000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv d0000000 NZ V |
| msr nzcv,x24; ccmp x25,x26,#0xE,ne; mrs x23,nzcv :: rd 00000000e0000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv e0000000 NZC |
| msr nzcv,x24; ccmp x25,x26,#0xF,ne; mrs x23,nzcv :: rd 00000000f0000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv f0000000 NZCV |
| |
| msr nzcv,x24; ccmp x25,x26,#0x6,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,x26,#0x5,eq; mrs x23,nzcv :: rd 0000000050000000 rm 0000000020000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 50000000 Z V |
| msr nzcv,x24; ccmp x25,x26,#0x3,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,x26,#0x7,eq; mrs x23,nzcv :: rd 0000000070000000 rm ffffffff80000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 70000000 ZCV |
| msr nzcv,x24; ccmp x25,x26,#0x6,lt; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,x26,#0x5,lt; mrs x23,nzcv :: rd 0000000050000000 rm 0000000020000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 50000000 Z V |
| msr nzcv,x24; ccmp x25,x26,#0x3,lt; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmp x25,x26,#0x7,lt; mrs x23,nzcv :: rd 0000000060000000 rm ffffffff80000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,x26,#0x6,gt; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,x26,#0x5,gt; mrs x23,nzcv :: rd 0000000060000000 rm 0000000020000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,x26,#0x3,gt; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmp x25,x26,#0x7,gt; mrs x23,nzcv :: rd 0000000070000000 rm ffffffff80000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 70000000 ZCV |
| msr nzcv,x24; ccmp x25,x26,#0x6,ne; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,x26,#0x5,ne; mrs x23,nzcv :: rd 0000000060000000 rm 0000000020000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,x26,#0x3,ne; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmp x25,x26,#0x7,ne; mrs x23,nzcv :: rd 0000000060000000 rm ffffffff80000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,x26,#0x6,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn 0000000000000011, ra 0000000000000012, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,x26,#0x5,eq; mrs x23,nzcv :: rd 0000000050000000 rm 0000000020000000, rn 0000000000000011, ra 0000000000000012, cin 0, nzcv 50000000 Z V |
| msr nzcv,x24; ccmp x25,x26,#0x3,eq; mrs x23,nzcv :: rd 0000000080000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000012, cin 0, nzcv 80000000 N |
| msr nzcv,x24; ccmp x25,x26,#0x7,eq; mrs x23,nzcv :: rd 0000000070000000 rm ffffffff80000000, rn 0000000000000011, ra 0000000000000012, cin 0, nzcv 70000000 ZCV |
| msr nzcv,x24; ccmp x25,x26,#0x6,lt; mrs x23,nzcv :: rd 0000000080000000 rm 0000000010000000, rn 0000000000000011, ra 0000000000000012, cin 0, nzcv 80000000 N |
| msr nzcv,x24; ccmp x25,x26,#0x5,lt; mrs x23,nzcv :: rd 0000000050000000 rm 0000000020000000, rn 0000000000000011, ra 0000000000000012, cin 0, nzcv 50000000 Z V |
| msr nzcv,x24; ccmp x25,x26,#0x3,lt; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000012, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmp x25,x26,#0x7,lt; mrs x23,nzcv :: rd 0000000080000000 rm ffffffff80000000, rn 0000000000000011, ra 0000000000000012, cin 0, nzcv 80000000 N |
| msr nzcv,x24; ccmp x25,x26,#0x6,gt; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn 0000000000000011, ra 0000000000000012, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,x26,#0x5,gt; mrs x23,nzcv :: rd 0000000080000000 rm 0000000020000000, rn 0000000000000011, ra 0000000000000012, cin 0, nzcv 80000000 N |
| msr nzcv,x24; ccmp x25,x26,#0x3,gt; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000012, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmp x25,x26,#0x7,gt; mrs x23,nzcv :: rd 0000000070000000 rm ffffffff80000000, rn 0000000000000011, ra 0000000000000012, cin 0, nzcv 70000000 ZCV |
| msr nzcv,x24; ccmp x25,x26,#0x6,ne; mrs x23,nzcv :: rd 0000000080000000 rm 0000000010000000, rn 0000000000000011, ra 0000000000000012, cin 0, nzcv 80000000 N |
| msr nzcv,x24; ccmp x25,x26,#0x5,ne; mrs x23,nzcv :: rd 0000000080000000 rm 0000000020000000, rn 0000000000000011, ra 0000000000000012, cin 0, nzcv 80000000 N |
| msr nzcv,x24; ccmp x25,x26,#0x3,ne; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000012, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmp x25,x26,#0x7,ne; mrs x23,nzcv :: rd 0000000080000000 rm ffffffff80000000, rn 0000000000000011, ra 0000000000000012, cin 0, nzcv 80000000 N |
| msr nzcv,x24; ccmn x25,x26,#0x0,eq; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,x26,#0x1,eq; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,x26,#0x2,eq; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,x26,#0x3,eq; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,x26,#0x4,eq; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,x26,#0x5,eq; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,x26,#0x6,eq; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,x26,#0x7,eq; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,x26,#0x8,eq; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,x26,#0x9,eq; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,x26,#0xA,eq; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,x26,#0xB,eq; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,x26,#0xC,eq; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,x26,#0xD,eq; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,x26,#0xE,eq; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,x26,#0xF,eq; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 00000000 |
| |
| msr nzcv,x24; ccmn x25,x26,#0x0,ne; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,x26,#0x1,ne; mrs x23,nzcv :: rd 0000000010000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 10000000 V |
| msr nzcv,x24; ccmn x25,x26,#0x2,ne; mrs x23,nzcv :: rd 0000000020000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 20000000 C |
| msr nzcv,x24; ccmn x25,x26,#0x3,ne; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmn x25,x26,#0x4,ne; mrs x23,nzcv :: rd 0000000040000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 40000000 Z |
| msr nzcv,x24; ccmn x25,x26,#0x5,ne; mrs x23,nzcv :: rd 0000000050000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 50000000 Z V |
| msr nzcv,x24; ccmn x25,x26,#0x6,ne; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn x25,x26,#0x7,ne; mrs x23,nzcv :: rd 0000000070000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 70000000 ZCV |
| msr nzcv,x24; ccmn x25,x26,#0x8,ne; mrs x23,nzcv :: rd 0000000080000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 80000000 N |
| msr nzcv,x24; ccmn x25,x26,#0x9,ne; mrs x23,nzcv :: rd 0000000090000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 90000000 N V |
| msr nzcv,x24; ccmn x25,x26,#0xA,ne; mrs x23,nzcv :: rd 00000000a0000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv a0000000 N C |
| msr nzcv,x24; ccmn x25,x26,#0xB,ne; mrs x23,nzcv :: rd 00000000b0000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv b0000000 N CV |
| msr nzcv,x24; ccmn x25,x26,#0xC,ne; mrs x23,nzcv :: rd 00000000c0000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv c0000000 NZ |
| msr nzcv,x24; ccmn x25,x26,#0xD,ne; mrs x23,nzcv :: rd 00000000d0000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv d0000000 NZ V |
| msr nzcv,x24; ccmn x25,x26,#0xE,ne; mrs x23,nzcv :: rd 00000000e0000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv e0000000 NZC |
| msr nzcv,x24; ccmn x25,x26,#0xF,ne; mrs x23,nzcv :: rd 00000000f0000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv f0000000 NZCV |
| |
| msr nzcv,x24; ccmn x25,x26,#0x6,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn x25,x26,#0x5,eq; mrs x23,nzcv :: rd 0000000050000000 rm 0000000020000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 50000000 Z V |
| msr nzcv,x24; ccmn x25,x26,#0x3,eq; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,x26,#0x7,eq; mrs x23,nzcv :: rd 0000000070000000 rm ffffffff80000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 70000000 ZCV |
| msr nzcv,x24; ccmn x25,x26,#0x6,lt; mrs x23,nzcv :: rd 0000000000000000 rm 0000000010000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,x26,#0x5,lt; mrs x23,nzcv :: rd 0000000050000000 rm 0000000020000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 50000000 Z V |
| msr nzcv,x24; ccmn x25,x26,#0x3,lt; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmn x25,x26,#0x7,lt; mrs x23,nzcv :: rd 0000000000000000 rm ffffffff80000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,x26,#0x6,gt; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn x25,x26,#0x5,gt; mrs x23,nzcv :: rd 0000000000000000 rm 0000000020000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,x26,#0x3,gt; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmn x25,x26,#0x7,gt; mrs x23,nzcv :: rd 0000000070000000 rm ffffffff80000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 70000000 ZCV |
| msr nzcv,x24; ccmn x25,x26,#0x6,ne; mrs x23,nzcv :: rd 0000000000000000 rm 0000000010000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,x26,#0x5,ne; mrs x23,nzcv :: rd 0000000000000000 rm 0000000020000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,x26,#0x3,ne; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmn x25,x26,#0x7,ne; mrs x23,nzcv :: rd 0000000000000000 rm ffffffff80000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,x26,#0x6,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn ffffffffffffffef, ra 0000000000000012, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn x25,x26,#0x5,eq; mrs x23,nzcv :: rd 0000000050000000 rm 0000000020000000, rn ffffffffffffffef, ra 0000000000000012, cin 0, nzcv 50000000 Z V |
| msr nzcv,x24; ccmn x25,x26,#0x3,eq; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000012, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,x26,#0x7,eq; mrs x23,nzcv :: rd 0000000070000000 rm ffffffff80000000, rn ffffffffffffffef, ra 0000000000000012, cin 0, nzcv 70000000 ZCV |
| msr nzcv,x24; ccmn x25,x26,#0x6,lt; mrs x23,nzcv :: rd 0000000000000000 rm 0000000010000000, rn ffffffffffffffef, ra 0000000000000012, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,x26,#0x5,lt; mrs x23,nzcv :: rd 0000000050000000 rm 0000000020000000, rn ffffffffffffffef, ra 0000000000000012, cin 0, nzcv 50000000 Z V |
| msr nzcv,x24; ccmn x25,x26,#0x3,lt; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000012, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmn x25,x26,#0x7,lt; mrs x23,nzcv :: rd 0000000000000000 rm ffffffff80000000, rn ffffffffffffffef, ra 0000000000000012, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,x26,#0x6,gt; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn ffffffffffffffef, ra 0000000000000012, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn x25,x26,#0x5,gt; mrs x23,nzcv :: rd 0000000000000000 rm 0000000020000000, rn ffffffffffffffef, ra 0000000000000012, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,x26,#0x3,gt; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000012, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmn x25,x26,#0x7,gt; mrs x23,nzcv :: rd 0000000070000000 rm ffffffff80000000, rn ffffffffffffffef, ra 0000000000000012, cin 0, nzcv 70000000 ZCV |
| msr nzcv,x24; ccmn x25,x26,#0x6,ne; mrs x23,nzcv :: rd 0000000000000000 rm 0000000010000000, rn ffffffffffffffef, ra 0000000000000012, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,x26,#0x5,ne; mrs x23,nzcv :: rd 0000000000000000 rm 0000000020000000, rn ffffffffffffffef, ra 0000000000000012, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,x26,#0x3,ne; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000012, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmn x25,x26,#0x7,ne; mrs x23,nzcv :: rd 0000000000000000 rm ffffffff80000000, rn ffffffffffffffef, ra 0000000000000012, cin 0, nzcv 00000000 |
| CCMP/CCMN(reg)(32) |
| msr nzcv,x24; ccmp w25,w26,#0xF,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,w26,#0xF,ne; mrs x23,nzcv :: rd 00000000f0000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv f0000000 NZCV |
| msr nzcv,x24; ccmp w25,w26,#0xF,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000001100000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,w26,#0xF,ne; mrs x23,nzcv :: rd 00000000f0000000 rm 0000000040000000, rn 0000001100000011, ra 0000000000000011, cin 0, nzcv f0000000 NZCV |
| msr nzcv,x24; ccmp x25,x26,#0xF,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp x25,x26,#0xF,ne; mrs x23,nzcv :: rd 00000000f0000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv f0000000 NZCV |
| msr nzcv,x24; ccmp x25,x26,#0xF,eq; mrs x23,nzcv :: rd 0000000020000000 rm 0000000040000000, rn 0000001100000011, ra 0000000000000011, cin 0, nzcv 20000000 C |
| msr nzcv,x24; ccmp x25,x26,#0xF,ne; mrs x23,nzcv :: rd 00000000f0000000 rm 0000000040000000, rn 0000001100000011, ra 0000000000000011, cin 0, nzcv f0000000 NZCV |
| msr nzcv,x24; ccmp w25,w26,#0x0,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,w26,#0x1,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,w26,#0x2,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,w26,#0x3,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,w26,#0x4,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,w26,#0x5,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,w26,#0x6,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,w26,#0x7,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,w26,#0x8,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,w26,#0x9,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,w26,#0xA,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,w26,#0xB,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,w26,#0xC,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,w26,#0xD,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,w26,#0xE,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,w26,#0xF,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| |
| msr nzcv,x24; ccmp w25,w26,#0x0,ne; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmp w25,w26,#0x1,ne; mrs x23,nzcv :: rd 0000000010000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 10000000 V |
| msr nzcv,x24; ccmp w25,w26,#0x2,ne; mrs x23,nzcv :: rd 0000000020000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 20000000 C |
| msr nzcv,x24; ccmp w25,w26,#0x3,ne; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmp w25,w26,#0x4,ne; mrs x23,nzcv :: rd 0000000040000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 40000000 Z |
| msr nzcv,x24; ccmp w25,w26,#0x5,ne; mrs x23,nzcv :: rd 0000000050000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 50000000 Z V |
| msr nzcv,x24; ccmp w25,w26,#0x6,ne; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,w26,#0x7,ne; mrs x23,nzcv :: rd 0000000070000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 70000000 ZCV |
| msr nzcv,x24; ccmp w25,w26,#0x8,ne; mrs x23,nzcv :: rd 0000000080000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 80000000 N |
| msr nzcv,x24; ccmp w25,w26,#0x9,ne; mrs x23,nzcv :: rd 0000000090000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 90000000 N V |
| msr nzcv,x24; ccmp w25,w26,#0xA,ne; mrs x23,nzcv :: rd 00000000a0000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv a0000000 N C |
| msr nzcv,x24; ccmp w25,w26,#0xB,ne; mrs x23,nzcv :: rd 00000000b0000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv b0000000 N CV |
| msr nzcv,x24; ccmp w25,w26,#0xC,ne; mrs x23,nzcv :: rd 00000000c0000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv c0000000 NZ |
| msr nzcv,x24; ccmp w25,w26,#0xD,ne; mrs x23,nzcv :: rd 00000000d0000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv d0000000 NZ V |
| msr nzcv,x24; ccmp w25,w26,#0xE,ne; mrs x23,nzcv :: rd 00000000e0000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv e0000000 NZC |
| msr nzcv,x24; ccmp w25,w26,#0xF,ne; mrs x23,nzcv :: rd 00000000f0000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv f0000000 NZCV |
| |
| msr nzcv,x24; ccmp w25,w26,#0x6,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,w26,#0x5,eq; mrs x23,nzcv :: rd 0000000050000000 rm 0000000020000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 50000000 Z V |
| msr nzcv,x24; ccmp w25,w26,#0x3,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,w26,#0x7,eq; mrs x23,nzcv :: rd 0000000070000000 rm ffffffff80000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 70000000 ZCV |
| msr nzcv,x24; ccmp w25,w26,#0x6,lt; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,w26,#0x5,lt; mrs x23,nzcv :: rd 0000000050000000 rm 0000000020000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 50000000 Z V |
| msr nzcv,x24; ccmp w25,w26,#0x3,lt; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmp w25,w26,#0x7,lt; mrs x23,nzcv :: rd 0000000060000000 rm ffffffff80000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,w26,#0x6,gt; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,w26,#0x5,gt; mrs x23,nzcv :: rd 0000000060000000 rm 0000000020000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,w26,#0x3,gt; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmp w25,w26,#0x7,gt; mrs x23,nzcv :: rd 0000000070000000 rm ffffffff80000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 70000000 ZCV |
| msr nzcv,x24; ccmp w25,w26,#0x6,ne; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,w26,#0x5,ne; mrs x23,nzcv :: rd 0000000060000000 rm 0000000020000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,w26,#0x3,ne; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmp w25,w26,#0x7,ne; mrs x23,nzcv :: rd 0000000060000000 rm ffffffff80000000, rn 0000000000000011, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,w26,#0x6,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn 0000000000000011, ra 0000000000000012, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,w26,#0x5,eq; mrs x23,nzcv :: rd 0000000050000000 rm 0000000020000000, rn 0000000000000011, ra 0000000000000012, cin 0, nzcv 50000000 Z V |
| msr nzcv,x24; ccmp w25,w26,#0x3,eq; mrs x23,nzcv :: rd 0000000080000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000012, cin 0, nzcv 80000000 N |
| msr nzcv,x24; ccmp w25,w26,#0x7,eq; mrs x23,nzcv :: rd 0000000070000000 rm ffffffff80000000, rn 0000000000000011, ra 0000000000000012, cin 0, nzcv 70000000 ZCV |
| msr nzcv,x24; ccmp w25,w26,#0x6,lt; mrs x23,nzcv :: rd 0000000080000000 rm 0000000010000000, rn 0000000000000011, ra 0000000000000012, cin 0, nzcv 80000000 N |
| msr nzcv,x24; ccmp w25,w26,#0x5,lt; mrs x23,nzcv :: rd 0000000050000000 rm 0000000020000000, rn 0000000000000011, ra 0000000000000012, cin 0, nzcv 50000000 Z V |
| msr nzcv,x24; ccmp w25,w26,#0x3,lt; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000012, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmp w25,w26,#0x7,lt; mrs x23,nzcv :: rd 0000000080000000 rm ffffffff80000000, rn 0000000000000011, ra 0000000000000012, cin 0, nzcv 80000000 N |
| msr nzcv,x24; ccmp w25,w26,#0x6,gt; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn 0000000000000011, ra 0000000000000012, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmp w25,w26,#0x5,gt; mrs x23,nzcv :: rd 0000000080000000 rm 0000000020000000, rn 0000000000000011, ra 0000000000000012, cin 0, nzcv 80000000 N |
| msr nzcv,x24; ccmp w25,w26,#0x3,gt; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000012, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmp w25,w26,#0x7,gt; mrs x23,nzcv :: rd 0000000070000000 rm ffffffff80000000, rn 0000000000000011, ra 0000000000000012, cin 0, nzcv 70000000 ZCV |
| msr nzcv,x24; ccmp w25,w26,#0x6,ne; mrs x23,nzcv :: rd 0000000080000000 rm 0000000010000000, rn 0000000000000011, ra 0000000000000012, cin 0, nzcv 80000000 N |
| msr nzcv,x24; ccmp w25,w26,#0x5,ne; mrs x23,nzcv :: rd 0000000080000000 rm 0000000020000000, rn 0000000000000011, ra 0000000000000012, cin 0, nzcv 80000000 N |
| msr nzcv,x24; ccmp w25,w26,#0x3,ne; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn 0000000000000011, ra 0000000000000012, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmp w25,w26,#0x7,ne; mrs x23,nzcv :: rd 0000000080000000 rm ffffffff80000000, rn 0000000000000011, ra 0000000000000012, cin 0, nzcv 80000000 N |
| msr nzcv,x24; ccmn w25,w26,#0xF,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,w26,#0xF,ne; mrs x23,nzcv :: rd 00000000f0000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv f0000000 NZCV |
| msr nzcv,x24; ccmn w25,w26,#0xF,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffeeffffffef, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,w26,#0xF,ne; mrs x23,nzcv :: rd 00000000f0000000 rm 0000000040000000, rn ffffffeeffffffef, ra 0000000000000011, cin 0, nzcv f0000000 NZCV |
| msr nzcv,x24; ccmn x25,x26,#0xF,eq; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn x25,x26,#0xF,ne; mrs x23,nzcv :: rd 00000000f0000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv f0000000 NZCV |
| msr nzcv,x24; ccmn x25,x26,#0xF,eq; mrs x23,nzcv :: rd 0000000080000000 rm 0000000040000000, rn ffffffeeffffffef, ra 0000000000000011, cin 0, nzcv 80000000 N |
| msr nzcv,x24; ccmn x25,x26,#0xF,ne; mrs x23,nzcv :: rd 00000000f0000000 rm 0000000040000000, rn ffffffeeffffffef, ra 0000000000000011, cin 0, nzcv f0000000 NZCV |
| msr nzcv,x24; ccmn w25,w26,#0x0,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,w26,#0x1,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,w26,#0x2,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,w26,#0x3,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,w26,#0x4,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,w26,#0x5,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,w26,#0x6,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,w26,#0x7,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,w26,#0x8,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,w26,#0x9,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,w26,#0xA,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,w26,#0xB,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,w26,#0xC,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,w26,#0xD,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,w26,#0xE,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,w26,#0xF,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| |
| msr nzcv,x24; ccmn w25,w26,#0x0,ne; mrs x23,nzcv :: rd 0000000000000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 00000000 |
| msr nzcv,x24; ccmn w25,w26,#0x1,ne; mrs x23,nzcv :: rd 0000000010000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 10000000 V |
| msr nzcv,x24; ccmn w25,w26,#0x2,ne; mrs x23,nzcv :: rd 0000000020000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 20000000 C |
| msr nzcv,x24; ccmn w25,w26,#0x3,ne; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmn w25,w26,#0x4,ne; mrs x23,nzcv :: rd 0000000040000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 40000000 Z |
| msr nzcv,x24; ccmn w25,w26,#0x5,ne; mrs x23,nzcv :: rd 0000000050000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 50000000 Z V |
| msr nzcv,x24; ccmn w25,w26,#0x6,ne; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,w26,#0x7,ne; mrs x23,nzcv :: rd 0000000070000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 70000000 ZCV |
| msr nzcv,x24; ccmn w25,w26,#0x8,ne; mrs x23,nzcv :: rd 0000000080000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 80000000 N |
| msr nzcv,x24; ccmn w25,w26,#0x9,ne; mrs x23,nzcv :: rd 0000000090000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 90000000 N V |
| msr nzcv,x24; ccmn w25,w26,#0xA,ne; mrs x23,nzcv :: rd 00000000a0000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv a0000000 N C |
| msr nzcv,x24; ccmn w25,w26,#0xB,ne; mrs x23,nzcv :: rd 00000000b0000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv b0000000 N CV |
| msr nzcv,x24; ccmn w25,w26,#0xC,ne; mrs x23,nzcv :: rd 00000000c0000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv c0000000 NZ |
| msr nzcv,x24; ccmn w25,w26,#0xD,ne; mrs x23,nzcv :: rd 00000000d0000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv d0000000 NZ V |
| msr nzcv,x24; ccmn w25,w26,#0xE,ne; mrs x23,nzcv :: rd 00000000e0000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv e0000000 NZC |
| msr nzcv,x24; ccmn w25,w26,#0xF,ne; mrs x23,nzcv :: rd 00000000f0000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv f0000000 NZCV |
| |
| msr nzcv,x24; ccmn w25,w26,#0x6,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,w26,#0x5,eq; mrs x23,nzcv :: rd 0000000050000000 rm 0000000020000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 50000000 Z V |
| msr nzcv,x24; ccmn w25,w26,#0x3,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,w26,#0x7,eq; mrs x23,nzcv :: rd 0000000070000000 rm ffffffff80000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 70000000 ZCV |
| msr nzcv,x24; ccmn w25,w26,#0x6,lt; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,w26,#0x5,lt; mrs x23,nzcv :: rd 0000000050000000 rm 0000000020000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 50000000 Z V |
| msr nzcv,x24; ccmn w25,w26,#0x3,lt; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmn w25,w26,#0x7,lt; mrs x23,nzcv :: rd 0000000060000000 rm ffffffff80000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,w26,#0x6,gt; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,w26,#0x5,gt; mrs x23,nzcv :: rd 0000000060000000 rm 0000000020000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,w26,#0x3,gt; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmn w25,w26,#0x7,gt; mrs x23,nzcv :: rd 0000000070000000 rm ffffffff80000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 70000000 ZCV |
| msr nzcv,x24; ccmn w25,w26,#0x6,ne; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,w26,#0x5,ne; mrs x23,nzcv :: rd 0000000060000000 rm 0000000020000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,w26,#0x3,ne; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmn w25,w26,#0x7,ne; mrs x23,nzcv :: rd 0000000060000000 rm ffffffff80000000, rn ffffffffffffffef, ra 0000000000000011, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,w26,#0x6,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn ffffffffffffffef, ra 0000000000000012, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,w26,#0x5,eq; mrs x23,nzcv :: rd 0000000050000000 rm 0000000020000000, rn ffffffffffffffef, ra 0000000000000012, cin 0, nzcv 50000000 Z V |
| msr nzcv,x24; ccmn w25,w26,#0x3,eq; mrs x23,nzcv :: rd 0000000020000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000012, cin 0, nzcv 20000000 C |
| msr nzcv,x24; ccmn w25,w26,#0x7,eq; mrs x23,nzcv :: rd 0000000070000000 rm ffffffff80000000, rn ffffffffffffffef, ra 0000000000000012, cin 0, nzcv 70000000 ZCV |
| msr nzcv,x24; ccmn w25,w26,#0x6,lt; mrs x23,nzcv :: rd 0000000020000000 rm 0000000010000000, rn ffffffffffffffef, ra 0000000000000012, cin 0, nzcv 20000000 C |
| msr nzcv,x24; ccmn w25,w26,#0x5,lt; mrs x23,nzcv :: rd 0000000050000000 rm 0000000020000000, rn ffffffffffffffef, ra 0000000000000012, cin 0, nzcv 50000000 Z V |
| msr nzcv,x24; ccmn w25,w26,#0x3,lt; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000012, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmn w25,w26,#0x7,lt; mrs x23,nzcv :: rd 0000000020000000 rm ffffffff80000000, rn ffffffffffffffef, ra 0000000000000012, cin 0, nzcv 20000000 C |
| msr nzcv,x24; ccmn w25,w26,#0x6,gt; mrs x23,nzcv :: rd 0000000060000000 rm 0000000010000000, rn ffffffffffffffef, ra 0000000000000012, cin 0, nzcv 60000000 ZC |
| msr nzcv,x24; ccmn w25,w26,#0x5,gt; mrs x23,nzcv :: rd 0000000020000000 rm 0000000020000000, rn ffffffffffffffef, ra 0000000000000012, cin 0, nzcv 20000000 C |
| msr nzcv,x24; ccmn w25,w26,#0x3,gt; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000012, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmn w25,w26,#0x7,gt; mrs x23,nzcv :: rd 0000000070000000 rm ffffffff80000000, rn ffffffffffffffef, ra 0000000000000012, cin 0, nzcv 70000000 ZCV |
| msr nzcv,x24; ccmn w25,w26,#0x6,ne; mrs x23,nzcv :: rd 0000000020000000 rm 0000000010000000, rn ffffffffffffffef, ra 0000000000000012, cin 0, nzcv 20000000 C |
| msr nzcv,x24; ccmn w25,w26,#0x5,ne; mrs x23,nzcv :: rd 0000000020000000 rm 0000000020000000, rn ffffffffffffffef, ra 0000000000000012, cin 0, nzcv 20000000 C |
| msr nzcv,x24; ccmn w25,w26,#0x3,ne; mrs x23,nzcv :: rd 0000000030000000 rm 0000000040000000, rn ffffffffffffffef, ra 0000000000000012, cin 0, nzcv 30000000 CV |
| msr nzcv,x24; ccmn w25,w26,#0x7,ne; mrs x23,nzcv :: rd 0000000020000000 rm ffffffff80000000, rn ffffffffffffffef, ra 0000000000000012, cin 0, nzcv 20000000 C |
| REV |
| rev x11,x23 :: rd 88b450e5aeba79fd rn fd79baaee550b488, cin 0, nzcv 00000000 |
| rev x11,x23 :: rd 73174245095461e8 rn e861540945421773, cin 0, nzcv 00000000 |
| rev x11,x23 :: rd 6cbf1dfdd040119a rn 9a1140d0fd1dbf6c, cin 0, nzcv 00000000 |
| rev w11,w23 :: rd 0000000088b450e5 rn fd79baaee550b488, cin 0, nzcv 00000000 |
| rev w11,w23 :: rd 0000000073174245 rn e861540945421773, cin 0, nzcv 00000000 |
| rev w11,w23 :: rd 000000006cbf1dfd rn 9a1140d0fd1dbf6c, cin 0, nzcv 00000000 |
| RBIT |
| rbit x11,x23 :: rd 112d0aa7755d9ebf rn fd79baaee550b488, cin 0, nzcv 00000000 |
| rbit x11,x23 :: rd cee842a2902a8617 rn e861540945421773, cin 0, nzcv 00000000 |
| rbit x11,x23 :: rd 36fdb8bf0b028859 rn 9a1140d0fd1dbf6c, cin 0, nzcv 00000000 |
| rbit w11,w23 :: rd 00000000112d0aa7 rn fd79baaee550b488, cin 0, nzcv 00000000 |
| rbit w11,w23 :: rd 00000000cee842a2 rn e861540945421773, cin 0, nzcv 00000000 |
| rbit w11,w23 :: rd 0000000036fdb8bf rn 9a1140d0fd1dbf6c, cin 0, nzcv 00000000 |
| REV16 |
| rev16 x11,x23 :: rd 79fdaeba50e588b4 rn fd79baaee550b488, cin 0, nzcv 00000000 |
| rev16 x11,x23 :: rd 61e8095442457317 rn e861540945421773, cin 0, nzcv 00000000 |
| rev16 x11,x23 :: rd 119ad0401dfd6cbf rn 9a1140d0fd1dbf6c, cin 0, nzcv 00000000 |
| rev16 w11,w23 :: rd 0000000050e588b4 rn fd79baaee550b488, cin 0, nzcv 00000000 |
| rev16 w11,w23 :: rd 0000000042457317 rn e861540945421773, cin 0, nzcv 00000000 |
| rev16 w11,w23 :: rd 000000001dfd6cbf rn 9a1140d0fd1dbf6c, cin 0, nzcv 00000000 |
| REV32 |
| rev32 x11,x23 :: rd aeba79fd88b450e5 rn fd79baaee550b488, cin 0, nzcv 00000000 |
| rev32 x11,x23 :: rd 095461e873174245 rn e861540945421773, cin 0, nzcv 00000000 |
| rev32 x11,x23 :: rd d040119a6cbf1dfd rn 9a1140d0fd1dbf6c, cin 0, nzcv 00000000 |
| CLZ |
| clz x17, x22 :: rd 0000000000000000 rn ffffffffffffffff, cin 0, nzcv 00000000 |
| clz x17, x22 :: rd 0000000000000040 rn 0000000000000000, cin 0, nzcv 00000000 |
| clz x17, x22 :: rd 0000000000000009 rn 0070ffff01ffffff, cin 0, nzcv 00000000 |
| clz w17, w22 :: rd 0000000000000000 rn ffffffffffffffff, cin 0, nzcv 00000000 |
| clz w17, w22 :: rd 0000000000000020 rn 0000000000000000, cin 0, nzcv 00000000 |
| clz w17, w22 :: rd 0000000000000007 rn 0070ffff01ffffff, cin 0, nzcv 00000000 |
| LSLV/LSRV/ASRV |
| lslv x21,x20,x19 :: rd 2a8227efa64a2800 rm 4b154113f7d32514, rn cce230caafbf9cc9, cin 0, nzcv 00000000 |
| lslv x21,x20,x19 :: rd 75655c8753c4c000 rm 33d5d595721d4f13, rn f4509311f443a7ce, cin 0, nzcv 00000000 |
| lslv x21,x20,x19 :: rd de6954cbc1700000 rm 4a3c6de6954cbc17, rn 111b21e39fbd7254, cin 0, nzcv 00000000 |
| lslv x21,x20,x19 :: rd 6c11318000000000 rm fbb5c64ed1b044c6, rn 33ca4c4fb3960326, cin 0, nzcv 00000000 |
| lslv x21,x20,x19 :: rd 5f03d4a000000000 rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 00000000 |
| lslv x21,x20,x19 :: rd 5fc8323158b9b740 rm 02fe41918ac5cdba, rn 48e0815289728f05, cin 0, nzcv 00000000 |
| lslv x21,x20,x19 :: rd eeb8000000000000 rm b60a8f381f187bae, rn 008c208cc413ff72, cin 0, nzcv 00000000 |
| lsrv x21,x20,x19 :: rd 00258aa089fbe992 rm 4b154113f7d32514, rn cce230caafbf9cc9, cin 0, nzcv 00000000 |
| lsrv x21,x20,x19 :: rd 0000cf575655c875 rm 33d5d595721d4f13, rn f4509311f443a7ce, cin 0, nzcv 00000000 |
| lsrv x21,x20,x19 :: rd 000004a3c6de6954 rm 4a3c6de6954cbc17, rn 111b21e39fbd7254, cin 0, nzcv 00000000 |
| lsrv x21,x20,x19 :: rd 0000000003eed719 rm fbb5c64ed1b044c6, rn 33ca4c4fb3960326, cin 0, nzcv 00000000 |
| lsrv x21,x20,x19 :: rd 000000000adf164e rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 00000000 |
| lsrv x21,x20,x19 :: rd 0017f20c8c562e6d rm 02fe41918ac5cdba, rn 48e0815289728f05, cin 0, nzcv 00000000 |
| lsrv x21,x20,x19 :: rd 0000000000002d82 rm b60a8f381f187bae, rn 008c208cc413ff72, cin 0, nzcv 00000000 |
| asrv x21,x20,x19 :: rd 00258aa089fbe992 rm 4b154113f7d32514, rn cce230caafbf9cc9, cin 0, nzcv 00000000 |
| asrv x21,x20,x19 :: rd 0000cf575655c875 rm 33d5d595721d4f13, rn f4509311f443a7ce, cin 0, nzcv 00000000 |
| asrv x21,x20,x19 :: rd 000004a3c6de6954 rm 4a3c6de6954cbc17, rn 111b21e39fbd7254, cin 0, nzcv 00000000 |
| asrv x21,x20,x19 :: rd ffffffffffeed719 rm fbb5c64ed1b044c6, rn 33ca4c4fb3960326, cin 0, nzcv 00000000 |
| asrv x21,x20,x19 :: rd 000000000adf164e rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 00000000 |
| asrv x21,x20,x19 :: rd 0017f20c8c562e6d rm 02fe41918ac5cdba, rn 48e0815289728f05, cin 0, nzcv 00000000 |
| asrv x21,x20,x19 :: rd ffffffffffffed82 rm b60a8f381f187bae, rn 008c208cc413ff72, cin 0, nzcv 00000000 |
| lslv w21,w20,w19 :: rd 00000000a64a2800 rm 4b154113f7d32514, rn cce230caafbf9cc9, cin 0, nzcv 00000000 |
| lslv w21,w20,w19 :: rd 0000000053c4c000 rm 33d5d595721d4f13, rn f4509311f443a7ce, cin 0, nzcv 00000000 |
| lslv w21,w20,w19 :: rd 00000000c1700000 rm 4a3c6de6954cbc17, rn 111b21e39fbd7254, cin 0, nzcv 00000000 |
| lslv w21,w20,w19 :: rd 000000006c113180 rm fbb5c64ed1b044c6, rn 33ca4c4fb3960326, cin 0, nzcv 00000000 |
| lslv w21,w20,w19 :: rd 000000005f03d4a0 rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 00000000 |
| lslv w21,w20,w19 :: rd 0000000058b9b740 rm 02fe41918ac5cdba, rn 48e0815289728f05, cin 0, nzcv 00000000 |
| lslv w21,w20,w19 :: rd 00000000eeb80000 rm b60a8f381f187bae, rn 008c208cc413ff72, cin 0, nzcv 00000000 |
| lsrv w21,w20,w19 :: rd 00000000007be992 rm 4b154113f7d32514, rn cce230caafbf9cc9, cin 0, nzcv 00000000 |
| lsrv w21,w20,w19 :: rd 000000000001c875 rm 33d5d595721d4f13, rn f4509311f443a7ce, cin 0, nzcv 00000000 |
| lsrv w21,w20,w19 :: rd 0000000000000954 rm 4a3c6de6954cbc17, rn 111b21e39fbd7254, cin 0, nzcv 00000000 |
| lsrv w21,w20,w19 :: rd 000000000346c113 rm fbb5c64ed1b044c6, rn 33ca4c4fb3960326, cin 0, nzcv 00000000 |
| lsrv w21,w20,w19 :: rd 0000000035f03d4a rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 00000000 |
| lsrv w21,w20,w19 :: rd 0000000004562e6d rm 02fe41918ac5cdba, rn 48e0815289728f05, cin 0, nzcv 00000000 |
| lsrv w21,w20,w19 :: rd 00000000000007c6 rm b60a8f381f187bae, rn 008c208cc413ff72, cin 0, nzcv 00000000 |
| asrv w21,w20,w19 :: rd 00000000fffbe992 rm 4b154113f7d32514, rn cce230caafbf9cc9, cin 0, nzcv 00000000 |
| asrv w21,w20,w19 :: rd 000000000001c875 rm 33d5d595721d4f13, rn f4509311f443a7ce, cin 0, nzcv 00000000 |
| asrv w21,w20,w19 :: rd 00000000fffff954 rm 4a3c6de6954cbc17, rn 111b21e39fbd7254, cin 0, nzcv 00000000 |
| asrv w21,w20,w19 :: rd 00000000ff46c113 rm fbb5c64ed1b044c6, rn 33ca4c4fb3960326, cin 0, nzcv 00000000 |
| asrv w21,w20,w19 :: rd 00000000f5f03d4a rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 00000000 |
| asrv w21,w20,w19 :: rd 00000000fc562e6d rm 02fe41918ac5cdba, rn 48e0815289728f05, cin 0, nzcv 00000000 |
| asrv w21,w20,w19 :: rd 00000000000007c6 rm b60a8f381f187bae, rn 008c208cc413ff72, cin 0, nzcv 00000000 |
| SDIV/UDIV |
| sdiv x21,x20,x19 :: rd ffffffffffffffff rm 4b154113f7d32514, rn cce230caafbf9cc9, cin 0, nzcv 00000000 |
| sdiv x21,x20,x19 :: rd fffffffffffffffc rm 33d5d595721d4f13, rn f4509311f443a7ce, cin 0, nzcv 00000000 |
| sdiv x21,x20,x19 :: rd 0000000000000004 rm 4a3c6de6954cbc17, rn 111b21e39fbd7254, cin 0, nzcv 00000000 |
| sdiv x21,x20,x19 :: rd 0000000000000000 rm fbb5c64ed1b044c6, rn 33ca4c4fb3960326, cin 0, nzcv 00000000 |
| sdiv x21,x20,x19 :: rd 0000000000000000 rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 00000000 |
| sdiv x21,x20,x19 :: rd 0000000000000000 rm 02fe41918ac5cdba, rn 48e0815289728f05, cin 0, nzcv 00000000 |
| sdiv x21,x20,x19 :: rd ffffffffffffff79 rm b60a8f381f187bae, rn 008c208cc413ff72, cin 0, nzcv 00000000 |
| sdiv x21,x20,x19 :: rd 0000000000000005 rm 0000000000000065, rn 0000000000000014, cin 0, nzcv 00000000 |
| sdiv x21,x20,x19 :: rd 0000000000000005 rm 0000000000000064, rn 0000000000000014, cin 0, nzcv 00000000 |
| sdiv x21,x20,x19 :: rd 0000000000000004 rm 0000000000000063, rn 0000000000000014, cin 0, nzcv 00000000 |
| sdiv x21,x20,x19 :: rd 0000000000000004 rm 0000000000000062, rn 0000000000000014, cin 0, nzcv 00000000 |
| sdiv x21,x20,x19 :: rd fffffffffffffffb rm ffffffffffffff9b, rn 0000000000000014, cin 0, nzcv 00000000 |
| sdiv x21,x20,x19 :: rd fffffffffffffffb rm ffffffffffffff9c, rn 0000000000000014, cin 0, nzcv 00000000 |
| sdiv x21,x20,x19 :: rd fffffffffffffffc rm ffffffffffffff9d, rn 0000000000000014, cin 0, nzcv 00000000 |
| sdiv x21,x20,x19 :: rd fffffffffffffffc rm ffffffffffffff9e, rn 0000000000000014, cin 0, nzcv 00000000 |
| sdiv x21,x20,x19 :: rd fffffffffffffffb rm 0000000000000065, rn ffffffffffffffec, cin 0, nzcv 00000000 |
| sdiv x21,x20,x19 :: rd fffffffffffffffb rm 0000000000000064, rn ffffffffffffffec, cin 0, nzcv 00000000 |
| sdiv x21,x20,x19 :: rd fffffffffffffffc rm 0000000000000063, rn ffffffffffffffec, cin 0, nzcv 00000000 |
| sdiv x21,x20,x19 :: rd fffffffffffffffc rm 0000000000000062, rn ffffffffffffffec, cin 0, nzcv 00000000 |
| sdiv x21,x20,x19 :: rd 0000000000000005 rm ffffffffffffff9b, rn ffffffffffffffec, cin 0, nzcv 00000000 |
| sdiv x21,x20,x19 :: rd 0000000000000005 rm ffffffffffffff9c, rn ffffffffffffffec, cin 0, nzcv 00000000 |
| sdiv x21,x20,x19 :: rd 0000000000000004 rm ffffffffffffff9d, rn ffffffffffffffec, cin 0, nzcv 00000000 |
| sdiv x21,x20,x19 :: rd 0000000000000004 rm ffffffffffffff9e, rn ffffffffffffffec, cin 0, nzcv 00000000 |
| sdiv x21,x20,x19 :: rd 0000000000000000 rm 0000000000000001, rn 0000000000000000, cin 0, nzcv 00000000 |
| sdiv x21,x20,x19 :: rd 0000000000000000 rm 0000000000000000, rn 0000000000000000, cin 0, nzcv 00000000 |
| sdiv x21,x20,x19 :: rd 0000000000000000 rm ffffffffffffffff, rn 0000000000000000, cin 0, nzcv 00000000 |
| sdiv x21,x20,x19 :: rd 8000000000000000 rm 8000000000000000, rn ffffffffffffffff, cin 0, nzcv 00000000 |
| sdiv w21,w20,w19 :: rd 0000000000000000 rm 4b154113f7d32514, rn cce230caafbf9cc9, cin 0, nzcv 00000000 |
| sdiv w21,w20,w19 :: rd 00000000fffffff7 rm 33d5d595721d4f13, rn f4509311f443a7ce, cin 0, nzcv 00000000 |
| sdiv w21,w20,w19 :: rd 0000000000000001 rm 4a3c6de6954cbc17, rn 111b21e39fbd7254, cin 0, nzcv 00000000 |
| sdiv w21,w20,w19 :: rd 0000000000000000 rm fbb5c64ed1b044c6, rn 33ca4c4fb3960326, cin 0, nzcv 00000000 |
| sdiv w21,w20,w19 :: rd 0000000000000000 rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 00000000 |
| sdiv w21,w20,w19 :: rd 0000000000000000 rm 02fe41918ac5cdba, rn 48e0815289728f05, cin 0, nzcv 00000000 |
| sdiv w21,w20,w19 :: rd 0000000000000000 rm b60a8f381f187bae, rn 008c208cc413ff72, cin 0, nzcv 00000000 |
| sdiv w21,w20,w19 :: rd 0000000000000005 rm 0000000000000065, rn 0000000000000014, cin 0, nzcv 00000000 |
| sdiv w21,w20,w19 :: rd 0000000000000005 rm 0000000000000064, rn 0000000000000014, cin 0, nzcv 00000000 |
| sdiv w21,w20,w19 :: rd 0000000000000004 rm 0000000000000063, rn 0000000000000014, cin 0, nzcv 00000000 |
| sdiv w21,w20,w19 :: rd 0000000000000004 rm 0000000000000062, rn 0000000000000014, cin 0, nzcv 00000000 |
| sdiv w21,w20,w19 :: rd 00000000fffffffb rm ffffffffffffff9b, rn 0000000000000014, cin 0, nzcv 00000000 |
| sdiv w21,w20,w19 :: rd 00000000fffffffb rm ffffffffffffff9c, rn 0000000000000014, cin 0, nzcv 00000000 |
| sdiv w21,w20,w19 :: rd 00000000fffffffc rm ffffffffffffff9d, rn 0000000000000014, cin 0, nzcv 00000000 |
| sdiv w21,w20,w19 :: rd 00000000fffffffc rm ffffffffffffff9e, rn 0000000000000014, cin 0, nzcv 00000000 |
| sdiv w21,w20,w19 :: rd 00000000fffffffb rm 0000000000000065, rn ffffffffffffffec, cin 0, nzcv 00000000 |
| sdiv w21,w20,w19 :: rd 00000000fffffffb rm 0000000000000064, rn ffffffffffffffec, cin 0, nzcv 00000000 |
| sdiv w21,w20,w19 :: rd 00000000fffffffc rm 0000000000000063, rn ffffffffffffffec, cin 0, nzcv 00000000 |
| sdiv w21,w20,w19 :: rd 00000000fffffffc rm 0000000000000062, rn ffffffffffffffec, cin 0, nzcv 00000000 |
| sdiv w21,w20,w19 :: rd 0000000000000005 rm ffffffffffffff9b, rn ffffffffffffffec, cin 0, nzcv 00000000 |
| sdiv w21,w20,w19 :: rd 0000000000000005 rm ffffffffffffff9c, rn ffffffffffffffec, cin 0, nzcv 00000000 |
| sdiv w21,w20,w19 :: rd 0000000000000004 rm ffffffffffffff9d, rn ffffffffffffffec, cin 0, nzcv 00000000 |
| sdiv w21,w20,w19 :: rd 0000000000000004 rm ffffffffffffff9e, rn ffffffffffffffec, cin 0, nzcv 00000000 |
| sdiv w21,w20,w19 :: rd 0000000000000000 rm 0000000000000001, rn 0000000000000000, cin 0, nzcv 00000000 |
| sdiv w21,w20,w19 :: rd 0000000000000000 rm 0000000000000000, rn 0000000000000000, cin 0, nzcv 00000000 |
| sdiv w21,w20,w19 :: rd 0000000000000000 rm ffffffffffffffff, rn 0000000000000000, cin 0, nzcv 00000000 |
| sdiv w21,w20,w19 :: rd 0000000080000000 rm 0000000080000000, rn 00000000ffffffff, cin 0, nzcv 00000000 |
| udiv x21,x20,x19 :: rd 0000000000000000 rm 4b154113f7d32514, rn cce230caafbf9cc9, cin 0, nzcv 00000000 |
| udiv x21,x20,x19 :: rd 0000000000000000 rm 33d5d595721d4f13, rn f4509311f443a7ce, cin 0, nzcv 00000000 |
| udiv x21,x20,x19 :: rd 0000000000000004 rm 4a3c6de6954cbc17, rn 111b21e39fbd7254, cin 0, nzcv 00000000 |
| udiv x21,x20,x19 :: rd 0000000000000004 rm fbb5c64ed1b044c6, rn 33ca4c4fb3960326, cin 0, nzcv 00000000 |
| udiv x21,x20,x19 :: rd 0000000000000000 rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 00000000 |
| udiv x21,x20,x19 :: rd 0000000000000000 rm 02fe41918ac5cdba, rn 48e0815289728f05, cin 0, nzcv 00000000 |
| udiv x21,x20,x19 :: rd 000000000000014c rm b60a8f381f187bae, rn 008c208cc413ff72, cin 0, nzcv 00000000 |
| udiv x21,x20,x19 :: rd 0000000000000005 rm 0000000000000065, rn 0000000000000014, cin 0, nzcv 00000000 |
| udiv x21,x20,x19 :: rd 0000000000000005 rm 0000000000000064, rn 0000000000000014, cin 0, nzcv 00000000 |
| udiv x21,x20,x19 :: rd 0000000000000004 rm 0000000000000063, rn 0000000000000014, cin 0, nzcv 00000000 |
| udiv x21,x20,x19 :: rd 0000000000000004 rm 0000000000000062, rn 0000000000000014, cin 0, nzcv 00000000 |
| udiv x21,x20,x19 :: rd 0cccccccccccccc7 rm ffffffffffffff9b, rn 0000000000000014, cin 0, nzcv 00000000 |
| udiv x21,x20,x19 :: rd 0cccccccccccccc7 rm ffffffffffffff9c, rn 0000000000000014, cin 0, nzcv 00000000 |
| udiv x21,x20,x19 :: rd 0cccccccccccccc7 rm ffffffffffffff9d, rn 0000000000000014, cin 0, nzcv 00000000 |
| udiv x21,x20,x19 :: rd 0cccccccccccccc7 rm ffffffffffffff9e, rn 0000000000000014, cin 0, nzcv 00000000 |
| udiv x21,x20,x19 :: rd 0000000000000000 rm 0000000000000065, rn ffffffffffffffec, cin 0, nzcv 00000000 |
| udiv x21,x20,x19 :: rd 0000000000000000 rm 0000000000000064, rn ffffffffffffffec, cin 0, nzcv 00000000 |
| udiv x21,x20,x19 :: rd 0000000000000000 rm 0000000000000063, rn ffffffffffffffec, cin 0, nzcv 00000000 |
| udiv x21,x20,x19 :: rd 0000000000000000 rm 0000000000000062, rn ffffffffffffffec, cin 0, nzcv 00000000 |
| udiv x21,x20,x19 :: rd 0000000000000000 rm ffffffffffffff9b, rn ffffffffffffffec, cin 0, nzcv 00000000 |
| udiv x21,x20,x19 :: rd 0000000000000000 rm ffffffffffffff9c, rn ffffffffffffffec, cin 0, nzcv 00000000 |
| udiv x21,x20,x19 :: rd 0000000000000000 rm ffffffffffffff9d, rn ffffffffffffffec, cin 0, nzcv 00000000 |
| udiv x21,x20,x19 :: rd 0000000000000000 rm ffffffffffffff9e, rn ffffffffffffffec, cin 0, nzcv 00000000 |
| udiv x21,x20,x19 :: rd 0000000000000000 rm 0000000000000001, rn 0000000000000000, cin 0, nzcv 00000000 |
| udiv x21,x20,x19 :: rd 0000000000000000 rm 0000000000000000, rn 0000000000000000, cin 0, nzcv 00000000 |
| udiv x21,x20,x19 :: rd 0000000000000000 rm ffffffffffffffff, rn 0000000000000000, cin 0, nzcv 00000000 |
| udiv x21,x20,x19 :: rd 0000000000000000 rm 8000000000000000, rn ffffffffffffffff, cin 0, nzcv 00000000 |
| udiv w21,w20,w19 :: rd 0000000000000001 rm 4b154113f7d32514, rn cce230caafbf9cc9, cin 0, nzcv 00000000 |
| udiv w21,w20,w19 :: rd 0000000000000000 rm 33d5d595721d4f13, rn f4509311f443a7ce, cin 0, nzcv 00000000 |
| udiv w21,w20,w19 :: rd 0000000000000000 rm 4a3c6de6954cbc17, rn 111b21e39fbd7254, cin 0, nzcv 00000000 |
| udiv w21,w20,w19 :: rd 0000000000000001 rm fbb5c64ed1b044c6, rn 33ca4c4fb3960326, cin 0, nzcv 00000000 |
| udiv w21,w20,w19 :: rd 0000000000000001 rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 00000000 |
| udiv w21,w20,w19 :: rd 0000000000000001 rm 02fe41918ac5cdba, rn 48e0815289728f05, cin 0, nzcv 00000000 |
| udiv w21,w20,w19 :: rd 0000000000000000 rm b60a8f381f187bae, rn 008c208cc413ff72, cin 0, nzcv 00000000 |
| udiv w21,w20,w19 :: rd 0000000000000005 rm 0000000000000065, rn 0000000000000014, cin 0, nzcv 00000000 |
| udiv w21,w20,w19 :: rd 0000000000000005 rm 0000000000000064, rn 0000000000000014, cin 0, nzcv 00000000 |
| udiv w21,w20,w19 :: rd 0000000000000004 rm 0000000000000063, rn 0000000000000014, cin 0, nzcv 00000000 |
| udiv w21,w20,w19 :: rd 0000000000000004 rm 0000000000000062, rn 0000000000000014, cin 0, nzcv 00000000 |
| udiv w21,w20,w19 :: rd 000000000cccccc7 rm ffffffffffffff9b, rn 0000000000000014, cin 0, nzcv 00000000 |
| udiv w21,w20,w19 :: rd 000000000cccccc7 rm ffffffffffffff9c, rn 0000000000000014, cin 0, nzcv 00000000 |
| udiv w21,w20,w19 :: rd 000000000cccccc7 rm ffffffffffffff9d, rn 0000000000000014, cin 0, nzcv 00000000 |
| udiv w21,w20,w19 :: rd 000000000cccccc7 rm ffffffffffffff9e, rn 0000000000000014, cin 0, nzcv 00000000 |
| udiv w21,w20,w19 :: rd 0000000000000000 rm 0000000000000065, rn ffffffffffffffec, cin 0, nzcv 00000000 |
| udiv w21,w20,w19 :: rd 0000000000000000 rm 0000000000000064, rn ffffffffffffffec, cin 0, nzcv 00000000 |
| udiv w21,w20,w19 :: rd 0000000000000000 rm 0000000000000063, rn ffffffffffffffec, cin 0, nzcv 00000000 |
| udiv w21,w20,w19 :: rd 0000000000000000 rm 0000000000000062, rn ffffffffffffffec, cin 0, nzcv 00000000 |
| udiv w21,w20,w19 :: rd 0000000000000000 rm ffffffffffffff9b, rn ffffffffffffffec, cin 0, nzcv 00000000 |
| udiv w21,w20,w19 :: rd 0000000000000000 rm ffffffffffffff9c, rn ffffffffffffffec, cin 0, nzcv 00000000 |
| udiv w21,w20,w19 :: rd 0000000000000000 rm ffffffffffffff9d, rn ffffffffffffffec, cin 0, nzcv 00000000 |
| udiv w21,w20,w19 :: rd 0000000000000000 rm ffffffffffffff9e, rn ffffffffffffffec, cin 0, nzcv 00000000 |
| udiv w21,w20,w19 :: rd 0000000000000000 rm 0000000000000001, rn 0000000000000000, cin 0, nzcv 00000000 |
| udiv w21,w20,w19 :: rd 0000000000000000 rm 0000000000000000, rn 0000000000000000, cin 0, nzcv 00000000 |
| udiv w21,w20,w19 :: rd 0000000000000000 rm ffffffffffffffff, rn 0000000000000000, cin 0, nzcv 00000000 |
| udiv w21,w20,w19 :: rd 0000000000000000 rm 0000000080000000, rn 00000000ffffffff, cin 0, nzcv 00000000 |
| UMADDL/SMADDL/UMSUBL/SMSUBL |
| umaddl x14,w15,w16,x17 :: rd dc434eff2588c2a5 rm 8318f285284c6473, rn f2deaa8a065b5b97, ra db432311d1e3a1d0, cin 0, nzcv 00000000 |
| umaddl x14,w15,w16,x17 :: rd 853ed3b21d01dd68 rm a6325ae016fbd710, rn f0211fade82d1008, ra 70668d1659e224e8, cin 0, nzcv 00000000 |
| umaddl x14,w15,w16,x17 :: rd 579e22bab0475d0c rm 1f1dd8017f191501, rn f69aef71040bfeab, ra 559bc9e2fca45761, cin 0, nzcv 00000000 |
| umaddl x14,w15,w16,x17 :: rd b8dcb007dc22414f rm 389ce2f3140cec0c, rn 7a3ab866f2dcd171, ra a5d72d6243684403, cin 0, nzcv 00000000 |
| smaddl x14,w15,w16,x17 :: rd dc434eff2588c2a5 rm 8318f285284c6473, rn f2deaa8a065b5b97, ra db432311d1e3a1d0, cin 0, nzcv 00000000 |
| smaddl x14,w15,w16,x17 :: rd 6e42fca21d01dd68 rm a6325ae016fbd710, rn f0211fade82d1008, ra 70668d1659e224e8, cin 0, nzcv 00000000 |
| smaddl x14,w15,w16,x17 :: rd 579e22bab0475d0c rm 1f1dd8017f191501, rn f69aef71040bfeab, ra 559bc9e2fca45761, cin 0, nzcv 00000000 |
| smaddl x14,w15,w16,x17 :: rd a4cfc3fbdc22414f rm 389ce2f3140cec0c, rn 7a3ab866f2dcd171, ra a5d72d6243684403, cin 0, nzcv 00000000 |
| umsubl x14,w15,w16,x17 :: rd da42f7247e3e80fb rm 8318f285284c6473, rn f2deaa8a065b5b97, ra db432311d1e3a1d0, cin 0, nzcv 00000000 |
| umsubl x14,w15,w16,x17 :: rd 5b8e467a96c26c68 rm a6325ae016fbd710, rn f0211fade82d1008, ra 70668d1659e224e8, cin 0, nzcv 00000000 |
| umsubl x14,w15,w16,x17 :: rd 5399710b490151b6 rm 1f1dd8017f191501, rn f69aef71040bfeab, ra 559bc9e2fca45761, cin 0, nzcv 00000000 |
| umsubl x14,w15,w16,x17 :: rd 92d1aabcaaae46b7 rm 389ce2f3140cec0c, rn 7a3ab866f2dcd171, ra a5d72d6243684403, cin 0, nzcv 00000000 |
| smsubl x14,w15,w16,x17 :: rd da42f7247e3e80fb rm 8318f285284c6473, rn f2deaa8a065b5b97, ra db432311d1e3a1d0, cin 0, nzcv 00000000 |
| smsubl x14,w15,w16,x17 :: rd 728a1d8a96c26c68 rm a6325ae016fbd710, rn f0211fade82d1008, ra 70668d1659e224e8, cin 0, nzcv 00000000 |
| smsubl x14,w15,w16,x17 :: rd 5399710b490151b6 rm 1f1dd8017f191501, rn f69aef71040bfeab, ra 559bc9e2fca45761, cin 0, nzcv 00000000 |
| smsubl x14,w15,w16,x17 :: rd a6de96c8aaae46b7 rm 389ce2f3140cec0c, rn 7a3ab866f2dcd171, ra a5d72d6243684403, cin 0, nzcv 00000000 |
| Integer loads |
| LDR,STR (immediate, uimm12) (STR cases are MISSING)ldr x21, [x22, #24] :: rd 8f8e8d8c8b8a8988 rn (hidden), cin 0, nzcv 00000000 |
| ldr w21, [x22, #20] :: rd 0000000087868584 rn (hidden), cin 0, nzcv 00000000 |
| ldrh w21, [x22, #44] :: rd 0000000000009d9c rn (hidden), cin 0, nzcv 00000000 |
| ldrb w21, [x22, #56] :: rd 00000000000000a8 rn (hidden), cin 0, nzcv 00000000 |
| LDUR,STUR (immediate, simm9) (STR cases and wb check are MISSING) |
| ldr x21, [x22], #-24 :: rd f7f6f5f4f3f2f1f0 rn (hidden), cin 0, nzcv 00000000 |
| ldr x21, [x22, #-40]! :: rd cfcecdcccbcac9c8 rn (hidden), cin 0, nzcv 00000000 |
| ldr x21, [x22, #-48] :: rd c7c6c5c4c3c2c1c0 rn (hidden), cin 0, nzcv 00000000 |
| LDUR,STUR (immediate, simm9): STR cases are MISSINGLDP,STP (immediate, simm7) (STR cases and wb check is MISSING) |
| ldp x21, x28, [x22], #-24 ; add x21,x21,x28 :: rd f7f5f3f1efedebe8 rn (hidden), cin 0, nzcv 00000000 |
| ldp x21, x28, [x22], #-24 ; eor x21,x21,x28 :: rd 0808080808080808 rn (hidden), cin 0, nzcv 00000000 |
| ldp x21, x28, [x22, #-40]! ; add x21,x21,x28 :: rd a7a5a3a19f9d9b98 rn (hidden), cin 0, nzcv 00000000 |
| ldp x21, x28, [x22, #-40]! ; eor x21,x21,x28 :: rd 1818181818181818 rn (hidden), cin 0, nzcv 00000000 |
| ldp x21, x28, [x22, #-40] ; add x21,x21,x28 :: rd a7a5a3a19f9d9b98 rn (hidden), cin 0, nzcv 00000000 |
| ldp x21, x28, [x22, #-40] ; eor x21,x21,x28 :: rd 1818181818181818 rn (hidden), cin 0, nzcv 00000000 |
| ldp w21, w28, [x22], #-24 ; add x21,x21,x28 :: rd 00000001ebe9e7e4 rn (hidden), cin 0, nzcv 00000000 |
| ldp w21, w28, [x22], #-24 ; eor x21,x21,x28 :: rd 0000000004040404 rn (hidden), cin 0, nzcv 00000000 |
| ldp w21, w28, [x22, #-40]! ; add x21,x21,x28 :: rd 000000019b999794 rn (hidden), cin 0, nzcv 00000000 |
| ldp w21, w28, [x22, #-40]! ; eor x21,x21,x28 :: rd 0000000004040404 rn (hidden), cin 0, nzcv 00000000 |
| ldp w21, w28, [x22, #-40] ; add x21,x21,x28 :: rd 000000019b999794 rn (hidden), cin 0, nzcv 00000000 |
| ldp w21, w28, [x22, #-40] ; eor x21,x21,x28 :: rd 0000000004040404 rn (hidden), cin 0, nzcv 00000000 |
| LDR (literal, int reg) |
| xyzzy00: ldr x21, xyzzy00 - 8 :: rd aa0003f6d51b4203 rn (hidden), cin 0, nzcv 00000000 |
| xyzzy01: ldr x21, xyzzy01 + 0 :: rd aa1503e258000015 rn (hidden), cin 0, nzcv 00000000 |
| xyzzy02: ldr x21, xyzzy02 + 8 :: rd 911e43a0d53b4201 rn (hidden), cin 0, nzcv 00000000 |
| xyzzy03: ldr x21, xyzzy03 - 4 :: rd 58fffff5aa0003f6 rn (hidden), cin 0, nzcv 00000000 |
| xyzzy04: ldr x21, xyzzy04 + 0 :: rd aa1503e258000015 rn (hidden), cin 0, nzcv 00000000 |
| xyzzy05: ldr x21, xyzzy05 + 4 :: rd d53b4201aa1503e2 rn (hidden), cin 0, nzcv 00000000 |
| {LD,ST}R (integer register) (entirely MISSING) |
| LDRS{B,H,W} (uimm12) |
| ldrsw x21, [x22, #24] :: rd ffffffff8b8a8988 rn (hidden), cin 0, nzcv 00000000 |
| ldrsh x21, [x22, #20] :: rd ffffffffffff8584 rn (hidden), cin 0, nzcv 00000000 |
| ldrsh w21, [x22, #44] :: rd 00000000ffff9d9c rn (hidden), cin 0, nzcv 00000000 |
| ldrsb x21, [x22, #88] :: rd ffffffffffffffc8 rn (hidden), cin 0, nzcv 00000000 |
| ldrsb w21, [x22, #56] :: rd 00000000ffffffa8 rn (hidden), cin 0, nzcv 00000000 |
| LDRS{B,H,W} (simm9, upd) (upd check is MISSING) |
| ldrsw x21, [x22, #-24]! :: rd ffffffffdbdad9d8 rn (hidden), cin 0, nzcv 00000000 |
| ldrsh x21, [x22, #-20]! :: rd ffffffffffffdddc rn (hidden), cin 0, nzcv 00000000 |
| ldrsh w21, [x22, #-44]! :: rd 00000000ffffc5c4 rn (hidden), cin 0, nzcv 00000000 |
| ldrsb x21, [x22, #-88]! :: rd ffffffffffffff98 rn (hidden), cin 0, nzcv 00000000 |
| ldrsb w21, [x22, #-56]! :: rd 00000000ffffffb8 rn (hidden), cin 0, nzcv 00000000 |
| ldrsw x21, [x22], #-24 :: rd fffffffff3f2f1f0 rn (hidden), cin 0, nzcv 00000000 |
| ldrsh x21, [x22], #-20 :: rd fffffffffffff1f0 rn (hidden), cin 0, nzcv 00000000 |
| ldrsh w21, [x22], #-44 :: rd 00000000fffff1f0 rn (hidden), cin 0, nzcv 00000000 |
| ldrsb x21, [x22], #-88 :: rd fffffffffffffff0 rn (hidden), cin 0, nzcv 00000000 |
| ldrsb w21, [x22], #-56 :: rd 00000000fffffff0 rn (hidden), cin 0, nzcv 00000000 |
| LDRS{B,H,W} (simm9, noUpd) |
| ldrsw x21, [x22, #-24] :: rd ffffffffdbdad9d8 rn (hidden), cin 0, nzcv 00000000 |
| ldrsh x21, [x22, #-20] :: rd ffffffffffffdddc rn (hidden), cin 0, nzcv 00000000 |
| ldrsh w21, [x22, #-44] :: rd 00000000ffffc5c4 rn (hidden), cin 0, nzcv 00000000 |
| ldrsb x21, [x22, #-88] :: rd ffffffffffffff98 rn (hidden), cin 0, nzcv 00000000 |
| ldrsb w21, [x22, #-56] :: rd 00000000ffffffb8 rn (hidden), cin 0, nzcv 00000000 |
| LDP,STP (immediate, simm7) (FP&VEC) (entirely MISSING) |
| {LD,ST}R (vector register) (entirely MISSING) |
| LDRS{B,H,W} (integer register, SX) |
| ldrsw x21, [x22,x23] :: rd fffffffff8f7f6f5 rm (hidden), rn (hidden), cin 0, nzcv 00000000 |
| ldrsw x21, [x22,x23, lsl #2] :: rd ffffffff87868584 rm (hidden), rn (hidden), cin 0, nzcv 00000000 |
| ldrsw x21, [x22,w23,uxtw #0] :: rd fffffffff8f7f6f5 rm (hidden), rn (hidden), cin 0, nzcv 00000000 |
| ldrsw x21, [x22,w23,uxtw #2] :: rd ffffffff87868584 rm (hidden), rn (hidden), cin 0, nzcv 00000000 |
| ldrsw x21, [x22,w23,sxtw #0] :: rd ffffffffeeedeceb rm (hidden), rn (hidden), cin 0, nzcv 00000000 |
| ldrsw x21, [x22,w23,sxtw #2] :: rd ffffffffdfdedddc rm (hidden), rn (hidden), cin 0, nzcv 00000000 |
| ldrsh x21, [x22,x23] :: rd fffffffffffff6f5 rm (hidden), rn (hidden), cin 0, nzcv 00000000 |
| ldrsh x21, [x22,x23, lsl #1] :: rd fffffffffffffbfa rm (hidden), rn (hidden), cin 0, nzcv 00000000 |
| ldrsh x21, [x22,w23,uxtw #0] :: rd fffffffffffff6f5 rm (hidden), rn (hidden), cin 0, nzcv 00000000 |
| ldrsh x21, [x22,w23,uxtw #1] :: rd fffffffffffffbfa rm (hidden), rn (hidden), cin 0, nzcv 00000000 |
| ldrsh x21, [x22,w23,sxtw #0] :: rd ffffffffffffeceb rm (hidden), rn (hidden), cin 0, nzcv 00000000 |
| ldrsh x21, [x22,w23,sxtw #1] :: rd ffffffffffffe7e6 rm (hidden), rn (hidden), cin 0, nzcv 00000000 |
| ldrsh w21, [x22,x23] :: rd 00000000fffff6f5 rm (hidden), rn (hidden), cin 0, nzcv 00000000 |
| ldrsh w21, [x22,x23, lsl #1] :: rd 00000000fffffbfa rm (hidden), rn (hidden), cin 0, nzcv 00000000 |
| ldrsh w21, [x22,w23,uxtw #0] :: rd 00000000fffff6f5 rm (hidden), rn (hidden), cin 0, nzcv 00000000 |
| ldrsh w21, [x22,w23,uxtw #1] :: rd 00000000fffffbfa rm (hidden), rn (hidden), cin 0, nzcv 00000000 |
| ldrsh w21, [x22,w23,sxtw #0] :: rd 00000000ffffeceb rm (hidden), rn (hidden), cin 0, nzcv 00000000 |
| ldrsh w21, [x22,w23,sxtw #1] :: rd 00000000ffffe7e6 rm (hidden), rn (hidden), cin 0, nzcv 00000000 |
| ldrsb x21, [x22,x23] :: rd fffffffffffffff5 rm (hidden), rn (hidden), cin 0, nzcv 00000000 |
| ldrsb x21, [x22,x23, lsl #0] :: rd fffffffffffffff5 rm (hidden), rn (hidden), cin 0, nzcv 00000000 |
| ldrsb x21, [x22,w23,uxtw #0] :: rd fffffffffffffff5 rm (hidden), rn (hidden), cin 0, nzcv 00000000 |
| ldrsb x21, [x22,w23,uxtw #0] :: rd fffffffffffffff5 rm (hidden), rn (hidden), cin 0, nzcv 00000000 |
| ldrsb x21, [x22,w23,sxtw #0] :: rd ffffffffffffffeb rm (hidden), rn (hidden), cin 0, nzcv 00000000 |
| ldrsb x21, [x22,w23,sxtw #0] :: rd ffffffffffffffeb rm (hidden), rn (hidden), cin 0, nzcv 00000000 |
| ldrsb w21, [x22,x23] :: rd 00000000fffffff5 rm (hidden), rn (hidden), cin 0, nzcv 00000000 |
| ldrsb w21, [x22,x23, lsl #0] :: rd 00000000fffffff5 rm (hidden), rn (hidden), cin 0, nzcv 00000000 |
| ldrsb w21, [x22,w23,uxtw #0] :: rd 00000000fffffff5 rm (hidden), rn (hidden), cin 0, nzcv 00000000 |
| ldrsb w21, [x22,w23,uxtw #0] :: rd 00000000fffffff5 rm (hidden), rn (hidden), cin 0, nzcv 00000000 |
| ldrsb w21, [x22,w23,sxtw #0] :: rd 00000000ffffffeb rm (hidden), rn (hidden), cin 0, nzcv 00000000 |
| ldrsb w21, [x22,w23,sxtw #0] :: rd 00000000ffffffeb rm (hidden), rn (hidden), cin 0, nzcv 00000000 |
| LDR/STR (immediate, SIMD&FP, unsigned offset) (entirely MISSING) |
| LDR/STR (immediate, SIMD&FP, pre/post index) (entirely MISSING) |
| LDUR/STUR (unscaled offset, SIMD&FP) (entirely MISSING) |
| LDR (literal, SIMD&FP) (entirely MISSING) |
| LD1/ST1 (single structure, no offset) (entirely MISSING) |
| LD1/ST1 (single structure, post index) (entirely MISSING) |
| LD{,A}X{R,RH,RB} (entirely MISSING) |
| ST{,L}X{R,RH,RB} (entirely MISSING) |
| LDA{R,RH,RB} |
| ldar x21, [x22] :: rd f7f6f5f4f3f2f1f0 rn (hidden), cin 0, nzcv 00000000 |
| ldar w21, [x22] :: rd 00000000f3f2f1f0 rn (hidden), cin 0, nzcv 00000000 |
| ldarh w21, [x22] :: rd 000000000000f1f0 rn (hidden), cin 0, nzcv 00000000 |
| ldarb w21, [x22] :: rd 00000000000000f0 rn (hidden), cin 0, nzcv 00000000 |
| STL{R,RH,RB} (entirely MISSING) |
| LDR,STR (immediate, uimm12)ldr x13, [x5, #24] with x5 = middle_of_block+-1, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 37c6ea00e0f4f257 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldr w13, [x5, #20] with x5 = middle_of_block+1, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 663cba29f1fe102a x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrh w13, [x5, #44] with x5 = middle_of_block+2, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 74b2685cb1630837 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrb w13, [x5, #56] with x5 = middle_of_block+3, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| bf73927edcc8e3a7 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| str x13, [x5, #24] with x5 = middle_of_block+-3, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. 3d b5 fe cd 8f 1e a7 32 .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| str w13, [x5, #20] with x5 = middle_of_block+5, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. fb 48 5c 15 .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| strh w13, [x5, #44] with x5 = middle_of_block+6, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. 43 .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| strb w13, [x5, #56] with x5 = middle_of_block+7, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. bd |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| LDUR,STUR (immediate, simm9) |
| ldr x13, [x5], #-24 with x5 = middle_of_block+0, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 5e602f48b53d6e42 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| -24 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldr x13, [x5, #-40]! with x5 = middle_of_block+0, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| c2a40eb09d08f981 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| -40 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldr x13, [x5, #-48] with x5 = middle_of_block+0, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| c5349b34f359e130 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| str x13, [x5], #-24 with x5 = middle_of_block+0, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] 3a 9b 1d 46 18 b0 ef 81 .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| -24 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| str x13, [x5, #-40]! with x5 = middle_of_block+0, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. 3f 73 c0 0a b7 5c 8d 74 |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| -40 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| str x13, [x5, #-48] with x5 = middle_of_block+0, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] 09 95 f8 6e 41 d0 2d 47 .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| LDP,STP (immediate, simm7) |
| ldp x13, x23, [x5], #-24 with x5 = middle_of_block+0, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 1b66ab089f41ee43 x13 (xor, xfer intreg #1) |
| ac8fc79beb26e5f5 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| -24 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldp x13, x23, [x5, #-40]! with x5 = middle_of_block+0, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| b98f2dea69fe5015 x13 (xor, xfer intreg #1) |
| 5913a7a99bcd1811 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| -40 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldp x13, x23, [x5, #-40] with x5 = middle_of_block+0, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| ba55d10667c950ff x13 (xor, xfer intreg #1) |
| b91a382f89560923 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| stp x13, x23, [x5], #-24 with x5 = middle_of_block+0, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] 22 0e b6 7d 25 b1 49 6c 85 67 29 ca e9 6b 42 6c |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| -24 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| stp x13, x23, [x5, #-40]! with x5 = middle_of_block+0, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. 72 af 97 76 3d b0 cc 4f |
| [ 96] 22 1a 6b 79 8f 52 63 1e .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| -40 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| stp x13, x23, [x5, #-40] with x5 = middle_of_block+0, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. ef cf 9b 01 25 8f 11 54 |
| [ 96] 58 be 1c a8 1f 77 e8 26 .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldp w13, w23, [x5], #-24 with x5 = middle_of_block+0, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 5826bd372d9e2ece x13 (xor, xfer intreg #1) |
| a690cbe50b71f694 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| -24 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldp w13, w23, [x5, #-40]! with x5 = middle_of_block+0, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| c4a8641060c8618a x13 (xor, xfer intreg #1) |
| f5f25be4fdcff02a x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| -40 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldp w13, w23, [x5, #-40] with x5 = middle_of_block+0, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| f711f2d5f6d39080 x13 (xor, xfer intreg #1) |
| 2e212f8dcab7fa0d x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| stp w13, w23, [x5], #-24 with x5 = middle_of_block+0, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] c0 f4 d9 ba de 39 bb 1f .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| -24 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| stp w13, w23, [x5, #-40]! with x5 = middle_of_block+0, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. b3 3b 5a ac f6 fc e4 |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| -40 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| stp w13, w23, [x5, #-40] with x5 = middle_of_block+0, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. 66 84 fc c9 b9 a8 37 28 |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| LDR (literal, int reg) (DONE ABOVE) |
| {LD,ST}R (integer register) (entirely MISSING) |
| str x13, [x5, x6] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. b8 34 a7 48 08 af c1 91 |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| str x13, [x5, x6, lsl #3] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. e8 b0 5c d8 |
| [112] 52 99 34 7c .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| str x13, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] 35 92 d1 bb d7 45 bf dc .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| str x13, [x5, w6, uxtw #3] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. 3d 99 5a 39 |
| [176] a9 f4 a3 2d .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| str x13, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] a5 3f df 5d 66 f7 20 e8 .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| str x13, [x5, w6, sxtw #3] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. 5d e8 12 15 |
| [112] 96 8e 05 30 .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldr x13, [x5, x6] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 91e9b1a8348ca797 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldr x13, [x5, x6, lsl #3] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 1cb5b125b109faeb x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldr x13, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 4085aae03ffeda0c x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldr x13, [x5, w6, uxtw #3] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 6a28851da073b3f9 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldr x13, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 72858dcc143fe6ef x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldr x13, [x5, w6, sxtw #3] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| de1c29d387e40b0c x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| str w13, [x5, x6] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. 44 ba 04 81 .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| str w13, [x5, x6, lsl #2] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. d6 af 6a d7 |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| str w13, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] 80 ee 73 ad .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| str w13, [x5, w6, uxtw #2] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. cf 5c 96 91 |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| str w13, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] 4f 39 ed 78 .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| str w13, [x5, w6, sxtw #2] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. 8a 61 ee 1b |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldr w13, [x5, x6] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 8482adce109203e3 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldr w13, [x5, x6, lsl #2] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| fcbcda5053fe3119 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldr w13, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 9bbc4e9ea534edef x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldr w13, [x5, w6, uxtw #2] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 27f86f4c86c32be6 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldr w13, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 62e39eed83444fa6 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldr w13, [x5, w6, sxtw #2] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 12f04216e80ea35a x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| strh w13, [x5, x6] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. 59 fc .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| strh w13, [x5, x6, lsl #1] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. dc 12 .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| strh w13, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] 05 f8 .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| strh w13, [x5, w6, uxtw #1] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. fa ac .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| strh w13, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] 33 e0 .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| strh w13, [x5, w6, sxtw #1] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. c8 9a .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrh w13, [x5, x6] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| d8322d9d06f127c8 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrh w13, [x5, x6, lsl #1] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| b6a77dd46effc11f x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrh w13, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| ec53c5c6d2bc4105 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrh w13, [x5, w6, uxtw #1] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 3dab680838dbf069 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrh w13, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 6f21cb2ea4117de5 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrh w13, [x5, w6, sxtw #1] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 442a51cc1911c952 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| strb w13, [x5, x6] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. f9 .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| strb w13, [x5, x6, lsl #0] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. 87 .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| strb w13, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] c4 .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| strb w13, [x5, w6, uxtw #0] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] c3 .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| strb w13, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] 51 .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| strb w13, [x5, w6, sxtw #0] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. d4 .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrb w13, [x5, x6] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 568db3c39f462465 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrb w13, [x5, x6, lsl #0] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| da7e66eeefeac8c3 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrb w13, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| e616c1c66bacf629 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrb w13, [x5, w6, uxtw #0] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 3dc827dc1a415140 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrb w13, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| a50afdc7fd5c7dde x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrb w13, [x5, w6, sxtw #0] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| e14fa7191ab21ead x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| LDRS{B,H,W} (uimm12) |
| ldrsw x13, [x5, #24] with x5 = middle_of_block+-16, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 4bf47798b0084d23 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsh x13, [x5, #20] with x5 = middle_of_block+-16, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 1c4efbbaef23ef5c x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsh w13, [x5, #44] with x5 = middle_of_block+-16, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 32b781460ee5ea9b x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsb x13, [x5, #72] with x5 = middle_of_block+-16, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 9a6f9e00e49efa40 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsb w13, [x5, #56] with x5 = middle_of_block+-16, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 40af08046d98739f x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| LDRS{B,H,W} (simm9, upd) (upd check is MISSING) |
| ldrsw x13, [x5, #-24]! with x5 = middle_of_block+-16, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 868adbe916974e3c x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| -24 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsh x13, [x5, #-20]! with x5 = middle_of_block+-16, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 026cc1be8681bd68 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| -20 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsh w13, [x5, #-44]! with x5 = middle_of_block+-16, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 674094a1f1f871a6 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| -44 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsb x13, [x5, #-72]! with x5 = middle_of_block+-16, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 8903429dc60011fa x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| -72 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsb w13, [x5, #-56]! with x5 = middle_of_block+-16, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 2752acc8fc4a8119 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| -56 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsw x13, [x5], #-24 with x5 = middle_of_block+-16, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 059f35b78686b811 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| -24 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsh x13, [x5], #-20 with x5 = middle_of_block+-16, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 199fbe0162896025 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| -20 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsh w13, [x5], #-44 with x5 = middle_of_block+-16, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 900736310fc037e8 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| -44 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsb x13, [x5], #-72 with x5 = middle_of_block+-16, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| c50975e3f31cb340 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| -72 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsb w13, [x5], #-56 with x5 = middle_of_block+-16, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 4adb65a9b3c0ee9d x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| -56 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| LDRS{B,H,W} (simm9, noUpd) |
| ldrsw x13, [x5, #-24] with x5 = middle_of_block+-16, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| e3ef68173ef979fb x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsh x13, [x5, #-20] with x5 = middle_of_block+-16, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 54bae2c06ea881e0 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsh w13, [x5, #-44] with x5 = middle_of_block+-16, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 61b03939c0a975cd x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsb x13, [x5, #-72] with x5 = middle_of_block+-16, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 32b930e96a65fd89 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsb w13, [x5, #-56] with x5 = middle_of_block+-16, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 5eee08eb7529502a x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| LDP,STP (immediate, simm7) (FP&VEC) |
| stp q17, q18, [x5, 32] with x5 = middle_of_block+-16, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] 55 18 f1 5c aa 84 c0 38 cd 7e 31 c8 92 f4 b0 e7 |
| [160] 0e 6c 4b d1 1e 2a 76 4c e2 a7 c8 5a 26 59 0e 5b |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| stp q17, q18, [x5, 32]! with x5 = middle_of_block+-16, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] 02 3e c1 07 ca e4 d0 ed 19 98 1e 29 25 e0 75 25 |
| [160] e1 0f a7 69 a1 4c 5b 2c 01 08 48 ca f8 ff dc 16 |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 32 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| stp q17, q18, [x5], 32 with x5 = middle_of_block+-16, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] 67 98 a3 78 5f 8e f9 57 5e 90 fc 32 c8 db d6 2c |
| [128] 20 68 2a 31 1b f7 e9 b2 9f 6a 21 20 db 21 17 27 |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 32 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| stp d17, d18, [x5, 32] with x5 = middle_of_block+-16, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] a0 6c d2 7f 89 d1 b1 b6 c5 5d 74 11 63 9d cb b9 |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| stp d17, d18, [x5, 32]! with x5 = middle_of_block+-16, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] 6f 14 75 6c 06 fe e1 ea 40 30 6e 55 7c 36 4d c4 |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 32 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| stp d17, d18, [x5], 32 with x5 = middle_of_block+-16, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] c2 ae 80 3d 80 4f 9f 9e 93 76 25 55 85 51 97 1a |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 32 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldp q17, q18, [x5, 32] with x5 = middle_of_block+-16, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| c3aeec76faa5f5c3 v17.d[0] (xor, xfer vecreg #1) |
| d81dc8f6818b6e41 v17.d[1] (xor, xfer vecreg #1) |
| c4709239d600ee90 v18.d[0] (xor, xfer vecreg #2) |
| a640a2efa8725362 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldp q17, q18, [x5, 32]! with x5 = middle_of_block+-16, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 80b42ff8dc0573ed v17.d[0] (xor, xfer vecreg #1) |
| 978d0461007b54b8 v17.d[1] (xor, xfer vecreg #1) |
| 47b1ef6f289cbd69 v18.d[0] (xor, xfer vecreg #2) |
| 4283a680f9f42f27 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 32 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldp q17, q18, [x5], 32 with x5 = middle_of_block+-16, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 32e4abace36584a4 v17.d[0] (xor, xfer vecreg #1) |
| 94465539af6bee2a v17.d[1] (xor, xfer vecreg #1) |
| 45ee7595ed87a70a v18.d[0] (xor, xfer vecreg #2) |
| 0b0689e9f49030da v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 32 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldp d17, d18, [x5, 32] with x5 = middle_of_block+-16, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 81468c3a81e28308 v17.d[0] (xor, xfer vecreg #1) |
| 9402389a9fd7e622 v17.d[1] (xor, xfer vecreg #1) |
| ac80e445d56aaf23 v18.d[0] (xor, xfer vecreg #2) |
| f429df6f28a16e8a v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldp d17, d18, [x5, 32]! with x5 = middle_of_block+-16, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 63c656d72c05e674 v17.d[0] (xor, xfer vecreg #1) |
| 0693fb5daf24d9a0 v17.d[1] (xor, xfer vecreg #1) |
| ce871ca48d1a40cc v18.d[0] (xor, xfer vecreg #2) |
| d38bf1af25daca31 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 32 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldp d17, d18, [x5], 32 with x5 = middle_of_block+-16, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| ce2bf285733f1da6 v17.d[0] (xor, xfer vecreg #1) |
| d57bc365125181f6 v17.d[1] (xor, xfer vecreg #1) |
| 0fde67d4c6716a14 v18.d[0] (xor, xfer vecreg #2) |
| f4335fd1bac1932e v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 32 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| {LD,ST}R (vector register) |
| str d17, [x5, x6] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. db 63 b8 ac e6 bd 2f 97 |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| str d17, [x5, x6, lsl #3] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. 0e cf b0 95 |
| [112] ba ca a7 9c .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| str d17, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] 20 05 ac 34 8e ff 78 7a .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| str d17, [x5, w6, uxtw #3] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. 61 1e 17 07 |
| [176] cd a0 14 3e .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| str d17, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] fe 3c 6b 02 b7 fe 10 c3 .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| str d17, [x5, w6, sxtw #3] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. 7f b8 e7 ca |
| [112] 50 fb 04 68 .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldr d17, [x5, x6] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 368c5b732c1248a5 v17.d[0] (xor, xfer vecreg #1) |
| f68888b1170ad684 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldr d17, [x5, x6, lsl #3] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| ee01fe34a2d85c41 v17.d[0] (xor, xfer vecreg #1) |
| 3b8184af9c823f6c v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldr d17, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| dc4fd084ba3953c1 v17.d[0] (xor, xfer vecreg #1) |
| 426589a518aea21f v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldr d17, [x5, w6, uxtw #3] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 619304aa5a129766 v17.d[0] (xor, xfer vecreg #1) |
| 4e2a7aa80ec124f3 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldr d17, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 8d7d6fe89f4f3dd9 v17.d[0] (xor, xfer vecreg #1) |
| a2c23ccc03f0e73c v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldr d17, [x5, w6, sxtw #3] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 480d291c1baa1e67 v17.d[0] (xor, xfer vecreg #1) |
| 8323b3257a6e114c v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| str s17, [x5, x6] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. 05 44 01 d5 .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| str s17, [x5, x6, lsl #2] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. 5b 32 ec e5 |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| str s17, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] 79 ee 29 c6 .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| str s17, [x5, w6, uxtw #2] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. 41 e4 eb 1d |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| str s17, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] e6 b1 03 2d .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| str s17, [x5, w6, sxtw #2] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. ec f6 d1 82 |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldr s17, [x5, x6] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| f1bb54fe78f0286a v17.d[0] (xor, xfer vecreg #1) |
| 63b582e54ba32e35 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldr s17, [x5, x6, lsl #2] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 59faf450fdf6566e v17.d[0] (xor, xfer vecreg #1) |
| 3ba5adb465ed9857 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldr s17, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| cfed330c080743c7 v17.d[0] (xor, xfer vecreg #1) |
| 03f1916ba55aac35 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldr s17, [x5, w6, uxtw #2] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 160a73c656d57e46 v17.d[0] (xor, xfer vecreg #1) |
| 018e121e8f1f8f24 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldr s17, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| f4c4181184dc39c4 v17.d[0] (xor, xfer vecreg #1) |
| 776e13e3a8706377 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldr s17, [x5, w6, sxtw #2] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 2c8e878293ad5852 v17.d[0] (xor, xfer vecreg #1) |
| ab8679cc737f4e82 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| LDRS{B,H,W} (integer register, SX) |
| ldrsw x13, [x5,x6] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 4991809b592766de x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsw x13, [x5,x6, lsl #2] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| ecab746191e71575 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsw x13, [x5,w6,uxtw #0] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 22a74ae38fee367e x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsw x13, [x5,w6,uxtw #2] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 1cd6637ce5e8e8da x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsw x13, [x5,w6,sxtw #0] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 9eab24c24f0ac55c x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsw x13, [x5,w6,sxtw #2] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 6c9cf046e9a2bfa3 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsh x13, [x5,x6] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| b5e3d360b748922c x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsh x13, [x5,x6, lsl #1] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| fb9f3c5f3b2bddc4 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsh x13, [x5,w6,uxtw #0] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| ba667ce49472fbca x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsh x13, [x5,w6,uxtw #1] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| ea7d6667dd92cdf2 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsh x13, [x5,w6,sxtw #0] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| afc148d693ed6288 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsh x13, [x5,w6,sxtw #1] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 58d88efd9452995d x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsh w13, [x5,x6] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| a8359b70e176717b x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsh w13, [x5,x6, lsl #1] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 654ed4c3800da87c x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsh w13, [x5,w6,uxtw #0] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 51959d8974ca561f x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsh w13, [x5,w6,uxtw #1] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 32805957c26143f5 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsh w13, [x5,w6,sxtw #0] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| ca816dc1927863b6 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsh w13, [x5,w6,sxtw #1] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| de0e3d5a79ef9f53 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsb x13, [x5,x6] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| ce66d34814b16659 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsb x13, [x5,x6, lsl #0] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 89989f6cc65775a1 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsb x13, [x5,w6,uxtw #0] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 578206f2f140e49e x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsb x13, [x5,w6,uxtw #0] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 54bd9f2dc8392d13 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsb x13, [x5,w6,sxtw #0] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| b0320b9e0885afab x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsb x13, [x5,w6,sxtw #0] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| a1e0a2c260cad60b x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsb w13, [x5,x6] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 45283e54c51f5bad x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsb w13, [x5,x6, lsl #0] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| c75cfa3b6ceb89d9 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsb w13, [x5,w6,uxtw #0] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| aa2ff686984d59d6 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsb w13, [x5,w6,uxtw #0] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| b01695c9b1059196 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsb w13, [x5,w6,sxtw #0] with x5 = middle_of_block+12, x6=4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 9f833c9791a66c27 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldrsb w13, [x5,w6,sxtw #0] with x5 = middle_of_block+12, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 39eb4f856504f7ce x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| LDR/STR (immediate, SIMD&FP, unsigned offset) |
| str q17, [x5, #-32] with x5 = middle_of_block+16, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] 7b 5d 69 f7 64 8c 79 47 6f 8f 57 84 7b c3 9c 9f |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| str d17, [x5, #-32] with x5 = middle_of_block+16, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] 42 cd cc 36 af 70 5a 49 .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| str s17, [x5, #-32] with x5 = middle_of_block+16, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] 8d 06 22 df .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldr q17, [x5, #-32] with x5 = middle_of_block+16, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| eedbb4bf846226cd v17.d[0] (xor, xfer vecreg #1) |
| 94094b6d188de7fa v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldr d17, [x5, #-32] with x5 = middle_of_block+16, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 029fcee15d9319f2 v17.d[0] (xor, xfer vecreg #1) |
| 50541814802369e6 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldr s17, [x5, #-32] with x5 = middle_of_block+16, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 86bcef9905c6716d v17.d[0] (xor, xfer vecreg #1) |
| fa13cb2fc8681760 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| LDR/STR (immediate, SIMD&FP, pre/post index) |
| str q17, [x5], #-32 with x5 = middle_of_block+16, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] 3a fc f2 7c 33 4d e6 bb 98 8b 63 7d c8 cc ed c5 |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| -32 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| str d17, [x5], #-32 with x5 = middle_of_block+16, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] d6 89 52 b2 c9 1c 8f 84 .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| -32 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| str s17, [x5], #-32 with x5 = middle_of_block+16, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] 61 9d 73 ee .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| -32 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldr q17, [x5], #-32 with x5 = middle_of_block+16, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| f3e66911400e0ffd v17.d[0] (xor, xfer vecreg #1) |
| bceee589d845dc5c v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| -32 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldr d17, [x5], #-32 with x5 = middle_of_block+16, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 476d9e9cc8b9ac0a v17.d[0] (xor, xfer vecreg #1) |
| 17224cc91cc3a43e v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| -32 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldr s17, [x5], #-32 with x5 = middle_of_block+16, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 20d04ccbe8ce283b v17.d[0] (xor, xfer vecreg #1) |
| 22146e45c5a92bce v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| -32 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| str q17, [x5, #-32]! with x5 = middle_of_block+16, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] 3c 68 70 1a e9 09 6a 17 ff 65 da cd 31 9d 99 f7 |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| -32 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| str d17, [x5, #-32]! with x5 = middle_of_block+16, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] 1a ee af 76 38 32 54 22 .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| -32 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| str s17, [x5, #-32]! with x5 = middle_of_block+16, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] bd ff 23 fb .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| -32 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldr q17, [x5, #-32]! with x5 = middle_of_block+16, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| c08cfa3f5c85e9ec v17.d[0] (xor, xfer vecreg #1) |
| d13f15e778e3733d v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| -32 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldr d17, [x5, #-32]! with x5 = middle_of_block+16, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 8cd8469c4bb50f10 v17.d[0] (xor, xfer vecreg #1) |
| 0cee45c96b719b9f v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| -32 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldr s17, [x5, #-32]! with x5 = middle_of_block+16, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 8cb8b23ad49fbfa0 v17.d[0] (xor, xfer vecreg #1) |
| 0864e77407470a14 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| -32 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| LDUR/STUR (unscaled offset, SIMD&FP) |
| str q17, [x5, #-13] with x5 = middle_of_block+16, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. 92 be 41 c2 36 e0 f2 76 79 06 b2 b1 bd |
| [144] 83 b1 f0 .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| str d17, [x5, #-13] with x5 = middle_of_block+16, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. ff 9d d1 08 13 ab 3d b9 .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| str s17, [x5, #-13] with x5 = middle_of_block+16, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. bb bb 62 b6 .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldr q17, [x5, #-13] with x5 = middle_of_block+16, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 315438529f368984 v17.d[0] (xor, xfer vecreg #1) |
| 63c745a60b8405eb v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldr d17, [x5, #-13] with x5 = middle_of_block+16, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 61d08c15c6fc312c v17.d[0] (xor, xfer vecreg #1) |
| 8f9963f2cf0bade7 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ldr s17, [x5, #-13] with x5 = middle_of_block+16, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 2b5282c8bfe45946 v17.d[0] (xor, xfer vecreg #1) |
| 0ce3959eed221512 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| LDR (literal, SIMD&FP) (entirely MISSING) |
| LD1/ST1 (single structure, no offset) |
| st1 {v17.2d}, [x5] with x5 = middle_of_block+3, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. b8 20 bd e5 8a f9 76 f3 cc ae a8 d0 18 |
| [144] 47 f5 2c .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| st1 {v17.4s}, [x5] with x5 = middle_of_block+5, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. 64 0a f3 ac 33 39 0b fb cb 96 09 |
| [144] 7b ac c2 61 4e .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| st1 {v17.8h}, [x5] with x5 = middle_of_block+7, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. 24 9d d3 60 d7 68 98 1a d1 |
| [144] 3c 02 23 a5 ab 09 03 .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| st1 {v17.16b}, [x5] with x5 = middle_of_block+13, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. c0 d2 1e |
| [144] 09 b5 58 b4 9e d4 9d d9 78 3f 12 c7 ad .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| st1 {v17.1d}, [x5] with x5 = middle_of_block+3, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. 9e 6a 38 6f 46 53 2c 51 .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| st1 {v17.2s}, [x5] with x5 = middle_of_block+5, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. 99 50 bc c2 fb 65 .. cc .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| st1 {v17.4h}, [x5] with x5 = middle_of_block+7, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. e6 45 98 4f 7f 3f 99 04 .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| st1 {v17.8b}, [x5] with x5 = middle_of_block+13, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. 97 b2 c4 |
| [144] d8 5e dc 6a b7 .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ld1 {v17.2d}, [x5] with x5 = middle_of_block+3, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0e7683e67672f875 v17.d[0] (xor, xfer vecreg #1) |
| 5849c62885094425 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ld1 {v17.4s}, [x5] with x5 = middle_of_block+5, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| cc566178b0505ce2 v17.d[0] (xor, xfer vecreg #1) |
| 9ba578e187b7ec29 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ld1 {v17.8h}, [x5] with x5 = middle_of_block+7, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| f5a2c2db348d79c9 v17.d[0] (xor, xfer vecreg #1) |
| 2d19eece1ac4cfe1 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ld1 {v17.16b}, [x5] with x5 = middle_of_block+13, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 2895e1c44e7d6375 v17.d[0] (xor, xfer vecreg #1) |
| 68121b8e14fe75c3 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ld1 {v17.1d}, [x5] with x5 = middle_of_block+3, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 11488cce9b957a63 v17.d[0] (xor, xfer vecreg #1) |
| a8e3a2dc36f2376f v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ld1 {v17.2s}, [x5] with x5 = middle_of_block+5, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| e400b2d8baf17a43 v17.d[0] (xor, xfer vecreg #1) |
| 2ce128ce0966e831 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ld1 {v17.4h}, [x5] with x5 = middle_of_block+7, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| fad3b103f776773a v17.d[0] (xor, xfer vecreg #1) |
| c2db8749219d644f v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ld1 {v17.8b}, [x5] with x5 = middle_of_block+13, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 1fb93f52acada1d3 v17.d[0] (xor, xfer vecreg #1) |
| acc5a26005cccd1d v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| LD1/ST1 (single structure, post index) |
| st1 {v17.2d}, [x5], #16 with x5 = middle_of_block+3, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. be 9f 67 38 8a 5a ae 31 9f 68 ea 98 79 |
| [144] 97 d9 93 .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 16 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| st1 {v17.4s}, [x5], #16 with x5 = middle_of_block+5, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. af df 1d d5 ec ca 0a 2c b4 22 83 |
| [144] 5d a8 8e 56 3d .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 16 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| st1 {v17.8h}, [x5], #16 with x5 = middle_of_block+7, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. ec a6 76 d8 d7 cd cc 1d f1 |
| [144] 42 d5 a2 31 e1 24 e2 .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 16 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| st1 {v17.16b}, [x5], #16 with x5 = middle_of_block+13, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. 36 31 5c |
| [144] 32 93 67 52 11 bd f9 5b 3f 75 e0 8e 03 .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 16 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| st1 {v17.1d}, [x5], #8 with x5 = middle_of_block+3, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. 44 79 62 32 a6 05 a4 be .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 8 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| st1 {v17.2s}, [x5], #8 with x5 = middle_of_block+5, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. 34 a3 95 cb c4 36 6f 9d .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 8 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| st1 {v17.4h}, [x5], #8 with x5 = middle_of_block+7, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. 2f 3e 9a 97 bf 54 ee 97 .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 8 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| st1 {v17.8b}, [x5], #8 with x5 = middle_of_block+13, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. 1d 51 72 |
| [144] a0 0d e9 38 8b .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 8 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ld1 {v17.2d}, [x5], #16 with x5 = middle_of_block+3, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 6856852b89835e57 v17.d[0] (xor, xfer vecreg #1) |
| 926cd97a6fcb250a v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 16 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ld1 {v17.4s}, [x5], #16 with x5 = middle_of_block+5, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| d5d11520d94f1b33 v17.d[0] (xor, xfer vecreg #1) |
| 5cbb554327b8a8e3 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 16 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ld1 {v17.8h}, [x5], #16 with x5 = middle_of_block+7, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| b9391b4ebce992b0 v17.d[0] (xor, xfer vecreg #1) |
| 2aee8c5bebb07542 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 16 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ld1 {v17.16b}, [x5], #16 with x5 = middle_of_block+13, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 677b9246bea3c7b9 v17.d[0] (xor, xfer vecreg #1) |
| c2cbc85912c50a5e v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 16 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ld1 {v17.1d}, [x5], #8 with x5 = middle_of_block+3, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 45c02b25ccc83819 v17.d[0] (xor, xfer vecreg #1) |
| 979e4bd3158ec388 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 8 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ld1 {v17.2s}, [x5], #8 with x5 = middle_of_block+5, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 17ce07c71f09fd99 v17.d[0] (xor, xfer vecreg #1) |
| 09bc3bb12d99f56d v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 8 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ld1 {v17.4h}, [x5], #8 with x5 = middle_of_block+7, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| bb582a4317d4a712 v17.d[0] (xor, xfer vecreg #1) |
| cc154357cca832ef v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 8 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ld1 {v17.8b}, [x5], #8 with x5 = middle_of_block+13, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 843b172475108087 v17.d[0] (xor, xfer vecreg #1) |
| 249f48da74ee9d60 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 8 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| LD1R (single structure, replicate) |
| ld1r {v17.2d}, [x5] with x5 = middle_of_block+3, x6=-5 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| f2660509f772e2c4 v17.d[0] (xor, xfer vecreg #1) |
| 4ce39e650ae364b8 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ld1r {v17.1d}, [x5] with x5 = middle_of_block+3, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 4e86be680cf6eb99 v17.d[0] (xor, xfer vecreg #1) |
| a211d8c7f4f18c65 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ld1r {v17.4s}, [x5] with x5 = middle_of_block+3, x6=-3 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 993c272115d4d6de v17.d[0] (xor, xfer vecreg #1) |
| 34921415b16467d2 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ld1r {v17.2s}, [x5] with x5 = middle_of_block+3, x6=-2 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| eec233adaef7ff96 v17.d[0] (xor, xfer vecreg #1) |
| a4b40916ce41e41a v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ld1r {v17.8h}, [x5] with x5 = middle_of_block+3, x6=-1 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 935cc2072eb1386a v17.d[0] (xor, xfer vecreg #1) |
| 6613df7ee0c3d743 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ld1r {v17.4h}, [x5] with x5 = middle_of_block+3, x6=1 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| c328131db4585dfa v17.d[0] (xor, xfer vecreg #1) |
| 4926fd682180c520 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ld1r {v17.16b}, [x5] with x5 = middle_of_block+3, x6=2 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| f087f060b8d625f7 v17.d[0] (xor, xfer vecreg #1) |
| 870a7f81275fc7f6 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ld1r {v17.8b}, [x5] with x5 = middle_of_block+3, x6=3 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| cf9a2fa5f98755c2 v17.d[0] (xor, xfer vecreg #1) |
| b109d45d0d4c4d17 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ld1r {v17.2d}, [x5], #8 with x5 = middle_of_block+3, x6=-5 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0c265c7984382b89 v17.d[0] (xor, xfer vecreg #1) |
| e9b2ff4b2c9fcf1f v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 8 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ld1r {v17.1d}, [x5], #8 with x5 = middle_of_block+3, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| bdfdd39474eccc4f v17.d[0] (xor, xfer vecreg #1) |
| fdfbad94b3469f9f v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 8 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ld1r {v17.4s}, [x5], #4 with x5 = middle_of_block+3, x6=-3 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0bcc9003fe0271dc v17.d[0] (xor, xfer vecreg #1) |
| 82366f42151d77f2 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 4 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ld1r {v17.2s}, [x5], #4 with x5 = middle_of_block+3, x6=-2 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| c9fd7dc362339d38 v17.d[0] (xor, xfer vecreg #1) |
| 4c9da8af320ed858 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 4 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ld1r {v17.8h}, [x5], #2 with x5 = middle_of_block+3, x6=-1 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 9a6cf746f39749b4 v17.d[0] (xor, xfer vecreg #1) |
| 870355d295f3be89 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 2 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ld1r {v17.4h}, [x5], #2 with x5 = middle_of_block+3, x6=1 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 205edc63fd70f66d v17.d[0] (xor, xfer vecreg #1) |
| be8fe64caa441ae1 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 2 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ld1r {v17.16b}, [x5], #1 with x5 = middle_of_block+3, x6=2 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 163053439f6c0c42 v17.d[0] (xor, xfer vecreg #1) |
| e601d1578762518f v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 1 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ld1r {v17.8b}, [x5], #1 with x5 = middle_of_block+3, x6=3 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 85f87dd58efe3327 v17.d[0] (xor, xfer vecreg #1) |
| 7470860d3c8884dc v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 1 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ld1r {v17.2d}, [x5], x6 with x5 = middle_of_block+3, x6=-5 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 742ee30b26c3644a v17.d[0] (xor, xfer vecreg #1) |
| 620afd520355620a v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| -5 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ld1r {v17.1d}, [x5], x6 with x5 = middle_of_block+3, x6=-4 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| d77f537144c905fd v17.d[0] (xor, xfer vecreg #1) |
| 8de2a890077a37e7 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| -4 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ld1r {v17.4s}, [x5], x6 with x5 = middle_of_block+3, x6=-3 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 733c2c6280caff90 v17.d[0] (xor, xfer vecreg #1) |
| 0bd32ad90eb64b11 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| -3 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ld1r {v17.2s}, [x5], x6 with x5 = middle_of_block+3, x6=-2 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 8f097b9699ca1fd8 v17.d[0] (xor, xfer vecreg #1) |
| 2a846d762bba52a3 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| -2 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ld1r {v17.8h}, [x5], x6 with x5 = middle_of_block+3, x6=-1 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 64a4000905e8aa3e v17.d[0] (xor, xfer vecreg #1) |
| 930f6607495e81b1 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| -1 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ld1r {v17.4h}, [x5], x6 with x5 = middle_of_block+3, x6=1 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| a61deef2566f701d v17.d[0] (xor, xfer vecreg #1) |
| 6af5f45fc9e7f5b0 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 1 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ld1r {v17.16b}, [x5], x6 with x5 = middle_of_block+3, x6=2 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 3ad49e64bf2c15cb v17.d[0] (xor, xfer vecreg #1) |
| ab04a19d6ae38e9d v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 2 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ld1r {v17.8b}, [x5], x6 with x5 = middle_of_block+3, x6=3 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 47e6864987e1a4e7 v17.d[0] (xor, xfer vecreg #1) |
| 6dd65eeb01a241ae v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 3 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| LD2/ST2 (multiple 2-elem structs to/from 2/regs, post index) (VERY INCOMPLETE) |
| ld2 {v17.2d, v18.2d}, [x5], #32 with x5 = middle_of_block+3, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 16e55b1873ee34c3 v17.d[0] (xor, xfer vecreg #1) |
| 34707980f120b864 v17.d[1] (xor, xfer vecreg #1) |
| ba093b5d784363cf v18.d[0] (xor, xfer vecreg #2) |
| 7111d1b5c20be11e v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 32 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| st2 {v17.2d, v18.2d}, [x5], #32 with x5 = middle_of_block+7, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. 0e 3f 31 98 6e 90 de 8d 3f |
| [144] ea 85 9a 2a e6 4c b8 d3 c7 c8 62 8c 43 99 75 2c |
| [160] fe 89 33 25 52 9d a8 .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 32 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| ld2 {v17.4s, v18.4s}, [x5], #32 with x5 = middle_of_block+13, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 1d1dad5f22f91503 v17.d[0] (xor, xfer vecreg #1) |
| b57248c23e0baef6 v17.d[1] (xor, xfer vecreg #1) |
| 05bbead3136a567d v18.d[0] (xor, xfer vecreg #2) |
| baed025f106d8588 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 32 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| st2 {v17.4s, v18.4s}, [x5], #32 with x5 = middle_of_block+17, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. cd 11 7d 61 05 62 71 d9 e4 fa ea f5 7b 7d c4 |
| [160] e5 8f 06 7e 21 0a c6 48 5a 02 12 03 3a 27 30 ff |
| [176] c5 .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 32 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| LD1/ST1 (multiple 1-elem structs to/from 2 regs, no offset) (VERY INCOMPLETE) |
| ld1 {v17.16b, v18.16b}, [x5] with x5 = middle_of_block+3, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 683f58edc2f5f671 v17.d[0] (xor, xfer vecreg #1) |
| 174e8d675cf2632a v17.d[1] (xor, xfer vecreg #1) |
| 15633f2c6ebd44da v18.d[0] (xor, xfer vecreg #2) |
| ab3a9c72639ef492 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| st1 {v17.16b, v18.16b}, [x5] with x5 = middle_of_block+7, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. 49 .. .. a2 31 44 0c 57 db |
| [144] df fe 73 d3 d7 67 7d ae da 61 fc b3 41 3a 20 e8 |
| [160] 95 ed 8a f3 1c 8a 7f .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| LD1/ST1 (multiple 1-elem structs to/from 2 regs, post index) (VERY INCOMPLETE) |
| ld1 {v17.16b, v18.16b}, [x5], #32 with x5 = middle_of_block+3, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 9bf660d5bdff8c3c v17.d[0] (xor, xfer vecreg #1) |
| a0ccbbec9ef6f2ca v17.d[1] (xor, xfer vecreg #1) |
| 8303595518823d47 v18.d[0] (xor, xfer vecreg #2) |
| 75f70396adc8eda8 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 32 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| st1 {v17.16b, v18.16b}, [x5], #32 with x5 = middle_of_block+7, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. d2 47 11 63 39 8e 47 81 6e |
| [144] 46 95 76 6d ba 9e 22 ad b5 07 7b 8e e5 46 4e b2 |
| [160] b8 27 42 be 20 42 bf .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 32 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| LD1/ST1 (multiple 1-elem structs to/from 3 regs, no offset) (VERY INCOMPLETE) |
| ld1 {v17.16b, v18.16b, v19.16b}, [x5] with x5 = middle_of_block+3, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| a9d70e88d1e89d30 v17.d[0] (xor, xfer vecreg #1) |
| 478a0f9d90561d2b v17.d[1] (xor, xfer vecreg #1) |
| 3e85525215476b1e v18.d[0] (xor, xfer vecreg #2) |
| 353dc370e1ffd26a v18.d[1] (xor, xfer vecreg #2) |
| 6f4831650bbf0b6a v19.d[0] (xor, xfer vecreg #3) |
| 51807f1bc8292233 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| st1 {v17.16b, v18.16b, v19.16b}, [x5] with x5 = middle_of_block+7, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. a3 7d e6 a1 06 24 44 85 4b |
| [144] 7c b1 95 4b 4a d7 c1 f5 3e f1 b7 2d 92 94 93 c4 |
| [160] 69 68 57 cf 90 7d 39 5f 16 3a 12 93 0b b3 fd e7 |
| [176] ca eb da 1a f6 75 3d .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 0 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| LD3/ST3 (multiple 3-elem structs to/from 3/regs, post index) (VERY INCOMPLETE) |
| ld3 {v17.2d, v18.2d, v19.2d}, [x5], #48 with x5 = middle_of_block+13, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 446f3899b211b6a0 v17.d[0] (xor, xfer vecreg #1) |
| 6437eeb9f3204807 v17.d[1] (xor, xfer vecreg #1) |
| 60e1161912e2876e v18.d[0] (xor, xfer vecreg #2) |
| e1a4654ef78b7a07 v18.d[1] (xor, xfer vecreg #2) |
| aed5a7373cd64d1f v19.d[0] (xor, xfer vecreg #3) |
| 739aef5767e6aa1f v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 48 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
| st3 {v17.2d, v18.2d, v19.2d}, [x5], #48 with x5 = middle_of_block+17, x6=0 |
| [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [144] .. c5 1c bb 41 0f c0 bd f1 9b b6 ab 88 aa 17 31 |
| [160] 94 7d ee 24 ee 14 61 cd 93 9f 71 69 88 94 38 eb |
| [176] 2f 75 95 31 3e 9e 0e 6c .. 58 4a a7 86 5e 21 08 |
| [192] c0 .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. |
| 0000000000000000 x13 (xor, xfer intreg #1) |
| 0000000000000000 x23 (xor, xfer intreg #2) |
| 0000000000000000 v17.d[0] (xor, xfer vecreg #1) |
| 0000000000000000 v17.d[1] (xor, xfer vecreg #1) |
| 0000000000000000 v18.d[0] (xor, xfer vecreg #2) |
| 0000000000000000 v18.d[1] (xor, xfer vecreg #2) |
| 0000000000000000 v19.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v19.d[1] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[0] (xor, xfer vecreg #3) |
| 0000000000000000 v20.d[1] (xor, xfer vecreg #3) |
| 48 x5 (sub, base reg) |
| 0 x6 (sub, index reg) |
| |
