Snap for 6001391 from baf94e52b8a25e2b7890e4c4070696ed75db3d38 to qt-aml-resolv-release
Change-Id: Ibc235847bebd2606e369207a678e47dd03b6704e
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
new file mode 100644
index 0000000..0c43434
--- /dev/null
+++ b/.gitlab-ci.yml
@@ -0,0 +1,335 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+# Grab our configured image. The source for this is found at:
+# https://gitlab.denx.de/u-boot/gitlab-ci-runner
+image: trini/u-boot-gitlab-ci-runner:xenial-20190720-02Aug2019
+
+# We run some tests in different order, to catch some failures quicker.
+stages:
+ - testsuites
+ - test.py
+ - world build
+
+.buildman_and_testpy_template: &buildman_and_testpy_dfn
+ tags: [ 'all' ]
+ stage: test.py
+ before_script:
+ # Clone uboot-test-hooks
+ - git clone --depth=1 git://github.com/swarren/uboot-test-hooks.git /tmp/uboot-test-hooks
+ - ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname`
+ - ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname`
+ - virtualenv /tmp/venv
+ - . /tmp/venv/bin/activate
+ - pip install pytest==2.8.7
+ - pip install python-subunit
+ - grub-mkimage -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
+ - grub-mkimage -o ~/grub_x64.efi -O x86_64-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
+ - mkdir ~/grub2-arm
+ - ( cd ~/grub2-arm; wget -O - http://download.opensuse.org/ports/armv7hl/distribution/leap/42.2/repo/oss/suse/armv7hl/grub2-arm-efi-2.02~beta2-87.1.armv7hl.rpm | rpm2cpio | cpio -di )
+ - mkdir ~/grub2-arm64
+ - ( cd ~/grub2-arm64; wget -O - http://download.opensuse.org/ports/aarch64/distribution/leap/42.2/repo/oss/suse/aarch64/grub2-arm64-efi-2.02~beta2-87.1.aarch64.rpm | rpm2cpio | cpio -di )
+
+ after_script:
+ - rm -rf ~/grub2* /tmp/uboot-test-hooks /tmp/venv
+ script:
+ # From buildman, exit code 129 means warnings only. If we've been asked to
+ # use clang only do one configuration.
+ - if [[ "${BUILDMAN}" != "" ]]; then
+ ret=0;
+ tools/buildman/buildman -P -E ${BUILDMAN} ${OVERRIDE}|| ret=$?;
+ if [[ $ret -ne 0 && $ret -ne 129 ]]; then
+ tools/buildman/buildman -sdeP ${BUILDMAN};
+ exit $ret;
+ fi;
+ fi
+ # "not a_test_which_does_not_exist" is a dummy -k parameter which will
+ # never prevent any test from running. That way, we can always pass
+ # "-k something" even when $TEST_PY_TEST_SPEC doesnt need a custom
+ # value.
+ - export UBOOT_TRAVIS_BUILD_DIR=`cd .. && pwd`/.bm-work/${TEST_PY_BD};
+ export PATH=/opt/qemu/bin:/tmp/uboot-test-hooks/bin:/usr/bin:/bin;
+ export PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci;
+ if [[ "${TEST_PY_BD}" != "" ]]; then
+ ./test/py/test.py --bd ${TEST_PY_BD} ${TEST_PY_ID}
+ -k "${TEST_PY_TEST_SPEC:-not a_test_which_does_not_exist}"
+ --build-dir "$UBOOT_TRAVIS_BUILD_DIR";
+ ret=$?;
+ if [[ $ret -ne 0 ]]; then
+ exit $ret;
+ fi;
+ fi;
+
+build all 32bit ARM platforms:
+ tags: [ 'all' ]
+ stage: world build
+ script:
+ - ret=0;
+ ./tools/buildman/buildman -P -E arm -x aarch64 || ret=$?;
+ if [[ $ret -ne 0 && $ret -ne 129 ]]; then
+ ./tools/buildman/buildman -sdeP;
+ exit $ret;
+ fi;
+
+build all 64bit ARM platforms:
+ tags: [ 'all' ]
+ stage: world build
+ script:
+ - virtualenv /tmp/venv
+ - . /tmp/venv/bin/activate
+ - pip install pyelftools
+ - ret=0;
+ ./tools/buildman/buildman -P -E aarch64 || ret=$?;
+ if [[ $ret -ne 0 && $ret -ne 129 ]]; then
+ ./tools/buildman/buildman -sdeP;
+ exit $ret;
+ fi;
+
+build all PowerPC platforms:
+ tags: [ 'all' ]
+ stage: world build
+ script:
+ - ret=0;
+ ./tools/buildman/buildman -P -E powerpc || ret=$?;
+ if [[ $ret -ne 0 && $ret -ne 129 ]]; then
+ ./tools/buildman/buildman -sdeP;
+ exit $ret;
+ fi;
+
+build all other platforms:
+ tags: [ 'all' ]
+ stage: world build
+ script:
+ - ret=0;
+ ./tools/buildman/buildman -P -E -x arm,powerpc || ret=$?;
+ if [[ $ret -ne 0 && $ret -ne 129 ]]; then
+ ./tools/buildman/buildman -sdeP;
+ exit $ret;
+ fi;
+
+# QA jobs for code analytics
+# static code analysis with cppcheck (we can add --enable=all later)
+cppcheck:
+ tags: [ 'all' ]
+ stage: testsuites
+ script:
+ - cppcheck --force --quiet --inline-suppr .
+
+# search for TODO within source tree
+grep TODO/FIXME/HACK:
+ tags: [ 'all' ]
+ stage: testsuites
+ script:
+ - grep -r TODO .
+ - grep -r FIXME .
+ # search for HACK within source tree and ignore HACKKIT board
+ - grep -r HACK . | grep -v HACKKIT
+
+# some statistics about the code base
+sloccount:
+ tags: [ 'all' ]
+ stage: testsuites
+ script:
+ - sloccount .
+
+# ensure all configs have MAINTAINERS entries
+Check for configs without MAINTAINERS entry:
+ tags: [ 'all' ]
+ stage: testsuites
+ script:
+ - if [ `./tools/genboardscfg.py -f 2>&1 | wc -l` -ne 0 ]; then exit 1; fi
+
+# Ensure host tools build
+Build tools-only:
+ tags: [ 'all' ]
+ stage: testsuites
+ script:
+ - make tools-only_config tools-only -j$(nproc)
+
+# Ensure env tools build
+Build envtools:
+ tags: [ 'all' ]
+ stage: testsuites
+ script:
+ - make tools-only_config envtools -j$(nproc)
+
+Run binman, buildman, dtoc and patman testsuites:
+ tags: [ 'all' ]
+ stage: testsuites
+ script:
+ - git config --global user.name "GitLab CI Runner";
+ git config --global user.email trini@konsulko.com;
+ export USER=gitlab;
+ virtualenv /tmp/venv;
+ . /tmp/venv/bin/activate;
+ pip install pyelftools;
+ export UBOOT_TRAVIS_BUILD_DIR=`cd .. && pwd`/.bm-work/sandbox_spl;
+ export PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt";
+ export PATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}";
+ ./tools/buildman/buildman -P sandbox_spl;
+ ./tools/binman/binman --toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools test;
+ ./tools/buildman/buildman -t;
+ ./tools/dtoc/dtoc -t;
+ ./tools/patman/patman --test
+
+# Test sandbox with test.py
+sandbox test.py:
+ tags: [ 'all' ]
+ variables:
+ TEST_PY_BD: "sandbox"
+ BUILDMAN: "^sandbox$"
+ <<: *buildman_and_testpy_dfn
+
+sandbox_spl test.py:
+ tags: [ 'all' ]
+ variables:
+ TEST_PY_BD: "sandbox_spl"
+ BUILDMAN: "^sandbox_spl$"
+ TEST_PY_TEST_SPEC: "test_ofplatdata"
+ <<: *buildman_and_testpy_dfn
+
+evb-ast2500 test.py:
+ tags: [ 'all' ]
+ variables:
+ TEST_PY_BD: "evb-ast2500"
+ TEST_PY_ID: "--id qemu"
+ BUILDMAN: "^evb-ast2500$"
+ <<: *buildman_and_testpy_dfn
+
+sandbox_flattree test.py:
+ tags: [ 'all' ]
+ variables:
+ TEST_PY_BD: "sandbox_flattree"
+ BUILDMAN: "^sandbox_flattree$"
+ <<: *buildman_and_testpy_dfn
+
+vexpress_ca15_tc2 test.py:
+ tags: [ 'all' ]
+ variables:
+ TEST_PY_BD: "vexpress_ca15_tc2"
+ TEST_PY_ID: "--id qemu"
+ BUILDMAN: "^vexpress_ca15_tc2$"
+ <<: *buildman_and_testpy_dfn
+
+vexpress_ca9x4 test.py:
+ tags: [ 'all' ]
+ variables:
+ TEST_PY_BD: "vexpress_ca9x4"
+ TEST_PY_ID: "--id qemu"
+ BUILDMAN: "^vexpress_ca9x4$"
+ <<: *buildman_and_testpy_dfn
+
+integratorcp_cm926ejs test.py:
+ tags: [ 'all' ]
+ variables:
+ TEST_PY_BD: "integratorcp_cm926ejs"
+ TEST_PY_TEST_SPEC: "not sleep"
+ TEST_PY_ID: "--id qemu"
+ BUILDMAN: "^integratorcp_cm926ejs$"
+ <<: *buildman_and_testpy_dfn
+
+qemu_arm test.py:
+ tags: [ 'all' ]
+ variables:
+ TEST_PY_BD: "qemu_arm"
+ TEST_PY_TEST_SPEC: "not sleep"
+ BUILDMAN: "^qemu_arm$"
+ <<: *buildman_and_testpy_dfn
+
+qemu_arm64 test.py:
+ tags: [ 'all' ]
+ variables:
+ TEST_PY_BD: "qemu_arm64"
+ TEST_PY_TEST_SPEC: "not sleep"
+ BUILDMAN: "^qemu_arm64$"
+ <<: *buildman_and_testpy_dfn
+
+qemu_mips test.py:
+ tags: [ 'all' ]
+ variables:
+ TEST_PY_BD: "qemu_mips"
+ TEST_PY_TEST_SPEC: "not sleep"
+ BUILDMAN: "^qemu_mips$"
+ <<: *buildman_and_testpy_dfn
+
+qemu_mipsel test.py:
+ tags: [ 'all' ]
+ variables:
+ TEST_PY_BD: "qemu_mipsel"
+ TEST_PY_TEST_SPEC: "not sleep"
+ BUILDMAN: "^qemu_mipsel$"
+ <<: *buildman_and_testpy_dfn
+
+qemu_mips64 test.py:
+ tags: [ 'all' ]
+ variables:
+ TEST_PY_BD: "qemu_mips64"
+ TEST_PY_TEST_SPEC: "not sleep"
+ BUILDMAN: "^qemu_mips64$"
+ <<: *buildman_and_testpy_dfn
+
+qemu_mips64el test.py:
+ tags: [ 'all' ]
+ variables:
+ TEST_PY_BD: "qemu_mips64el"
+ TEST_PY_TEST_SPEC: "not sleep"
+ BUILDMAN: "^qemu_mips64el$"
+ <<: *buildman_and_testpy_dfn
+
+qemu-ppce500 test.py:
+ tags: [ 'all' ]
+ variables:
+ TEST_PY_BD: "qemu-ppce500"
+ TEST_PY_TEST_SPEC: "not sleep"
+ BUILDMAN: "^qemu-ppce500$"
+ <<: *buildman_and_testpy_dfn
+
+qemu-riscv64 test.py:
+ tags: [ 'all' ]
+ variables:
+ TEST_PY_BD: "qemu-riscv64"
+ TEST_PY_TEST_SPEC: "not sleep"
+ BUILDMAN: "^qemu-riscv64$"
+ <<: *buildman_and_testpy_dfn
+
+qemu-x86 test.py:
+ tags: [ 'all' ]
+ variables:
+ TEST_PY_BD: "qemu-x86"
+ TEST_PY_TEST_SPEC: "not sleep"
+ BUILDMAN: "^qemu-x86$"
+ <<: *buildman_and_testpy_dfn
+
+qemu-x86_64 test.py:
+ tags: [ 'all' ]
+ variables:
+ TEST_PY_BD: "qemu-x86_64"
+ TEST_PY_TEST_SPEC: "not sleep"
+ BUILDMAN: "^qemu-x86_64$"
+ <<: *buildman_and_testpy_dfn
+
+zynq_zc702 test.py:
+ tags: [ 'all' ]
+ variables:
+ TEST_PY_BD: "zynq_zc702"
+ TEST_PY_TEST_SPEC: "not sleep"
+ TEST_PY_ID: "--id qemu"
+ BUILDMAN: "^zynq_zc702$"
+ <<: *buildman_and_testpy_dfn
+
+xilinx_versal_virt test.py:
+ tags: [ 'all' ]
+ variables:
+ TEST_PY_BD: "xilinx_versal_virt"
+ TEST_PY_TEST_SPEC: "not sleep"
+ TEST_PY_ID: "--id qemu"
+ BUILDMAN: "^xilinx_versal_virt$"
+ <<: *buildman_and_testpy_dfn
+
+xtfpga test.py:
+ tags: [ 'all' ]
+ variables:
+ TEST_PY_BD: "xtfpga"
+ TEST_PY_TEST_SPEC: "not sleep"
+ TEST_PY_ID: "--id qemu"
+ BUILDMAN: "^xtfpga$"
+ <<: *buildman_and_testpy_dfn
diff --git a/.mailmap b/.mailmap
index 1bee048..63afce3 100644
--- a/.mailmap
+++ b/.mailmap
@@ -4,10 +4,18 @@
# and/or not always written the same way, making contributions from the
# same person appearing not to be so or badly displayed.
#
+# This file is also used by scripts/get_maintainer.pl.
+#
# This file can be modified by hand or updated by the following command:
# scripts/mailmapper > tmp; mv tmp .mailmap
#
+# Entries in this file take one of the following forms:
+# Proper Name <commit@email.xx>
+# <proper@email.xx> <commit@email.xx>
+# Proper Name <proper@email.xx> <commit@email.xx>
+# Proper Name <proper@email.xx> Commit Name <commit@email.xx>
+Alexander Graf <agraf@csgraf.de> <agraf@suse.de>
Allen Martin <amartin@nvidia.com>
Andreas Bießmann <andreas.devel@googlemail.com>
Andreas Bießmann <andreas@biessmann.org>
@@ -23,8 +31,8 @@
Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com>
Prabhakar Kushwaha <prabhakar@freescale.com>
Rajeshwari Shinde <rajeshwari.s@samsung.com>
-Ricardo Ribalda <ricardo.ribalda@uam.es>
-Ricardo Ribalda <ricardo.ribalda@gmail.com>
+Ricardo Ribalda <ricardo@ribalda.com> <ricardo.ribalda@uam.es>
+Ricardo Ribalda <ricardo@ribalda.com> <ricardo.ribalda@gmail.com>
Sandeep Paulraj <s-paulraj@ti.com>
Shaohui Xie <Shaohui.Xie@freescale.com>
Stefan Roese <stroese>
diff --git a/.travis.yml b/.travis.yml
index 6662ca1..0ce09e3 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -4,7 +4,7 @@
# build U-Boot on Travis CI - https://travis-ci.org/
sudo: required
-dist: trusty
+dist: xenial
language: c
@@ -12,7 +12,7 @@
apt:
sources:
- ubuntu-toolchain-r-test
- - llvm-toolchain-trusty-7
+ - llvm-toolchain-xenial-7
packages:
- cppcheck
- sloccount
@@ -32,6 +32,7 @@
- device-tree-compiler
- lzop
- liblz4-tool
+ - lzma-alone
- libisl15
- clang-7
- srecord
@@ -60,7 +61,7 @@
env:
global:
- - PATH=/tmp/qemu-install/bin:/tmp/uboot-test-hooks/bin:/usr/bin:/bin
+ - PATH=/tmp/qemu-install/bin:/tmp/uboot-test-hooks/bin:/usr/bin:/bin:/usr/local/bin
- PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci
- BUILD_DIR=build
- HOSTCC="cc"
@@ -146,7 +147,7 @@
if [[ -n "${TEST_PY_TOOLS}" ]]; then
PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt"
PATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}"
- ./tools/binman/binman -t &&
+ ./tools/binman/binman --toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools test &&
./tools/patman/patman --test &&
./tools/buildman/buildman -t &&
PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt"
@@ -360,6 +361,10 @@
- name: "Build tools-only"
script:
- make tools-only_config tools-only -j$(nproc)
+ # Ensure env tools build
+ - name: "Build envtools"
+ script:
+ - make tools-only_config envtools -j$(nproc)
# test/py
- name: "test/py sandbox"
@@ -384,6 +389,13 @@
- TEST_PY_BD="sandbox_flattree"
BUILDMAN="^sandbox_flattree$"
TOOLCHAIN="i386"
+ - name: "test/py evb-ast2500"
+ env:
+ - TEST_PY_BD="evb-ast2500"
+ TEST_PY_ID="--id qemu"
+ QEMU_TARGET="arm-softmmu"
+ QEMU_VERSION="506179e42112be77bfd071f050b15762d3b2cd43"
+ BUILDMAN="^evb-ast2500$"
- name: "test/py vexpress_ca15_tc2"
env:
- TEST_PY_BD="vexpress_ca15_tc2"
@@ -451,6 +463,13 @@
QEMU_TARGET="ppc-softmmu"
BUILDMAN="^qemu-ppce500$"
TOOLCHAIN="powerpc"
+ - name: "test/py qemu-riscv64"
+ env:
+ - TEST_PY_BD="qemu-riscv64"
+ TEST_PY_TEST_SPEC="not sleep"
+ QEMU_TARGET="riscv64-softmmu"
+ BUILDMAN="^qemu-riscv64$"
+ TOOLCHAIN="riscv"
- name: "test/py qemu-x86"
env:
- TEST_PY_BD="qemu-x86"
diff --git a/Documentation/.gitignore b/Documentation/.gitignore
index e74fec8..0d20b64 100644
--- a/Documentation/.gitignore
+++ b/Documentation/.gitignore
@@ -1,2 +1 @@
-output
*.pyc
diff --git a/Kconfig b/Kconfig
index df8f294..1f0904f 100644
--- a/Kconfig
+++ b/Kconfig
@@ -156,14 +156,15 @@
config SYS_MALLOC_LEN
hex "Define memory for Dynamic allocation"
- depends on ARCH_ZYNQ || ARCH_VERSAL || ARCH_STM32MP
+ depends on ARCH_ZYNQ || ARCH_VERSAL || ARCH_STM32MP || ARCH_ROCKCHIP
+ default 0x2000000 if ARCH_ROCKCHIP
help
This defines memory to be allocated for Dynamic allocation
TODO: Use for other architectures
config SPL_SYS_MALLOC_F_LEN
hex "Size of malloc() pool in SPL before relocation"
- depends on SYS_MALLOC_F
+ depends on SYS_MALLOC_F && SPL
default 0x2800 if RCAR_GEN3
default SYS_MALLOC_F_LEN
help
@@ -174,7 +175,7 @@
config TPL_SYS_MALLOC_F_LEN
hex "Size of malloc() pool in TPL before relocation"
- depends on SYS_MALLOC_F
+ depends on SYS_MALLOC_F && TPL
default SYS_MALLOC_F_LEN
help
Before relocation, memory is very limited on many platforms. Still,
@@ -238,6 +239,7 @@
string "SPL image used in the combined SPL+U-Boot image"
default "spl/boot.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
default "spl/u-boot-spl.bin"
+ depends on SPL
help
Select the SPL build target that shall be generated by the SPL
build process (default spl/u-boot-spl.bin). This image will be
@@ -250,7 +252,8 @@
default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_GEN5
default "u-boot-spl.kwb" if ARCH_MVEBU && SPL
default "u-boot-elf.srec" if RCAR_GEN3
- default "u-boot.itb" if SPL_LOAD_FIT && (ROCKCHIP_RK3399 || ARCH_SUNXI)
+ default "u-boot.itb" if SPL_LOAD_FIT && (ROCKCHIP_RK3399 || \
+ ARCH_SUNXI || RISCV)
default "u-boot.kwb" if KIRKWOOD
default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
help
@@ -344,7 +347,7 @@
check the legacy image format is disabled by default, so that
unsigned images cannot be loaded. If a board needs the legacy image
format support in this case, enable it using
- CONFIG_IMAGE_FORMAT_LEGACY.
+ CONFIG_LEGACY_IMAGE_FORMAT.
config FIT_SIGNATURE_MAX_SIZE
hex "Max size of signed FIT structures"
@@ -463,6 +466,7 @@
depends on SPL_FIT
default "board/sunxi/mksunxi_fit_atf.sh" if SPL_LOAD_FIT && ARCH_SUNXI
default "arch/arm/mach-rockchip/make_fit_atf.py" if SPL_LOAD_FIT && ARCH_ROCKCHIP
+ default "arch/riscv/lib/mkimage_fit_opensbi.sh" if SPL_LOAD_FIT && RISCV
help
Specifies a (platform specific) script file to generate the FIT
source file used to build the U-Boot FIT image file. This gets
@@ -473,7 +477,7 @@
endif # FIT
-config IMAGE_FORMAT_LEGACY
+config LEGACY_IMAGE_FORMAT
bool "Enable support for the legacy image format"
default y if !FIT_SIGNATURE
help
diff --git a/MAINTAINERS b/MAINTAINERS
index bea3122..c536566 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -50,6 +50,26 @@
Maintainers List (try to look for most precise areas first)
-----------------------------------
+ANDROID AB
+M: Igor Opaniuk <igor.opaniuk@gmail.com>
+R: Sam Protsenko <semen.protsenko@linaro.org>
+S: Maintained
+F: cmd/ab_select.c
+F: common/android_ab.c
+F: doc/android/ab.txt
+F: include/android_ab.h
+F: test/py/tests/test_android/test_ab.py
+
+ANDROID AVB
+M: Igor Opaniuk <igor.opaniuk@gmail.com>
+S: Maintained
+F: cmd/avb.c
+F: common/avb_verify.c
+F: doc/android/avb2.txt
+F: include/avb_verify.h
+F: lib/libavb/
+F: test/py/tests/test_android/test_avb.py
+
ARC
M: Alexey Brodkin <alexey.brodkin@synopsys.com>
M: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
@@ -91,9 +111,11 @@
ARM ALTERA SOCFPGA
M: Marek Vasut <marex@denx.de>
M: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
+M: Ley Foon Tan <ley.foon.tan@intel.com>
S: Maintainted
T: git https://gitlab.denx.de/u-boot/custodians/u-boot-socfpga.git
F: arch/arm/mach-socfpga/
+F: drivers/sysreset/sysreset_socfpga*
ARM AMLOGIC SOC SUPPORT
M: Neil Armstrong <narmstrong@baylibre.com>
@@ -167,9 +189,11 @@
ARM HISILICON
M: Peter Griffin <peter.griffin@linaro.org>
+M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
S: Maintained
F: arch/arm/cpu/armv8/hisilicon
F: arch/arm/include/asm/arch-hi6220/
+F: arch/arm/include/asm/arch-hi3660/
ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K
M: Stefan Roese <sr@denx.de>
@@ -195,6 +219,7 @@
ARM MEDIATEK
M: Ryder Lee <ryder.lee@mediatek.com>
M: Weijie Gao <weijie.gao@mediatek.com>
+R: GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>
S: Maintained
F: arch/arm/mach-mediatek/
F: arch/arm/include/asm/arch-mediatek/
@@ -205,7 +230,7 @@
F: drivers/pinctrl/mediatek/
F: drivers/power/domain/mtk-power-domain.c
F: drivers/ram/mediatek/
-F: drivers/spi/mtk_qspi.c
+F: drivers/spi/mtk_snfi_spi.c
F: drivers/timer/mtk_timer.c
F: drivers/watchdog/mtk_wdt.c
F: drivers/net/mtk_eth.c
@@ -297,23 +322,41 @@
M: Patrick Delaunay <patrick.delaunay@st.com>
M: Patrice Chotard <patrice.chotard@st.com>
L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers)
+T: git https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git
S: Maintained
F: arch/arm/mach-stm32mp/
+F: drivers/adc/stm32-adc*
F: drivers/clk/clk_stm32mp1.c
+F: drivers/gpio/stm32_gpio.c
+F: drivers/hwspinlock/stm32_hwspinlock.c
F: drivers/i2c/stm32f7_i2c.c
+F: drivers/mailbox/stm32-ipcc.c
F: drivers/misc/stm32mp_fuse.c
+F: drivers/misc/stm32_rcc.c
F: drivers/mmc/stm32_sdmmc2.c
+F: drivers/mtd/nand/raw/stm32_fmc2_nand.c
F: drivers/phy/phy-stm32-usbphyc.c
F: drivers/pinctrl/pinctrl_stm32.c
F: drivers/power/pmic/stpmic1.c
F: drivers/power/regulator/stm32-vrefbuf.c
F: drivers/power/regulator/stpmic1.c
F: drivers/ram/stm32mp1/
-F: drivers/misc/stm32_rcc.c
+F: drivers/remoteproc/stm32_copro.c
F: drivers/reset/stm32-reset.c
+F: drivers/rtc/stm32_rtc.c
+F: drivers/serial/serial_stm32.*
F: drivers/spi/stm32_qspi.c
F: drivers/spi/stm32_spi.c
+F: drivers/video/stm32/stm32_ltdc.c
F: drivers/watchdog/stm32mp_wdt.c
+F: include/dt-bindings/clock/stm32fx-clock.h
+F: include/dt-bindings/clock/stm32mp1-clks.h
+F: include/dt-bindings/clock/stm32mp1-clksrc.h
+F: include/dt-bindings/pinctrl/stm32-pinfunc.h
+F: include/dt-bindings/reset/stm32mp1-resets.h
+F: include/stm32_rcc.h
+F: tools/stm32image.c
+
ARM STM STV0991
M: Vikas Manocha <vikas.manocha@st.com>
@@ -323,7 +366,7 @@
ARM SUNXI
M: Jagan Teki <jagan@amarulasolutions.com>
-M: Maxime Ripard <maxime.ripard@bootlin.com>
+M: Maxime Ripard <mripard@kernel.org>
S: Maintained
T: git https://gitlab.denx.de/u-boot/custodians/u-boot-sunxi.git
F: arch/arm/cpu/armv7/sunxi/
@@ -442,6 +485,13 @@
F: drivers/mtd/cfi_flash.c
F: drivers/mtd/jedec_flash.c
+CLOCK
+M: Lukasz Majewski <lukma@denx.de>
+S: Maintained
+T: git git://git.denx.de/u-boot-dfu.git
+F: drivers/clk/
+F: drivers/clk/imx/
+
COLDFIRE
M: Huan Wang <alison.wang@nxp.com>
M: Angelo Dureghello <angelo@sysam.it>
@@ -474,9 +524,7 @@
R: Alexander Graf <agraf@csgraf.de>
S: Maintained
T: git https://gitlab.denx.de/u-boot/custodians/u-boot-efi.git
-F: doc/README.uefi
-F: doc/README.iscsi
-F: doc/efi.rst
+F: doc/uefi/*
F: include/capitalization.h
F: include/charset.h
F: include/cp1250.h
@@ -518,7 +566,7 @@
T: git https://gitlab.denx.de/u-boot/custodians/u-boot-freebsd.git
FREESCALE QORIQ
-M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+M: Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
T: git https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq.git
F: drivers/watchdog/sp805_wdt.c
@@ -604,7 +652,7 @@
F: drivers/mtd/nand/raw/
NDS32
-M: Macpaul Lin <macpaul@andestech.com>
+M: Rick Chen <rick@andestech.com>
S: Maintained
T: git https://gitlab.denx.de/u-boot/custodians/u-boot-nds32.git
F: arch/nds32/
@@ -614,6 +662,7 @@
S: Maintained
T: git https://gitlab.denx.de/u-boot/custodians/u-boot-net.git
F: drivers/net/
+F: include/net.h
F: net/
NIOS
@@ -633,6 +682,12 @@
S: Maintained
F: tools/patman/
+PCI Endpoint
+M: Ramon Fried <rfried.dev@gmail.com>
+S: Maintained
+F: drivers/pci_endpoint/
+F: include/pci_ep.h
+
POWER
M: Jaehoon Chung <jh80.chung@samsung.com>
S: Maintained
@@ -669,13 +724,13 @@
F: arch/powerpc/include/asm/arch-mpc83xx/
POWERPC MPC85XX
-M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+M: Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
T: git https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx.git
F: arch/powerpc/cpu/mpc85xx/
POWERPC MPC86XX
-M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+M: Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
T: git https://gitlab.denx.de/u-boot/custodians/u-boot-mpc86xx.git
F: arch/powerpc/cpu/mpc86xx/
@@ -768,6 +823,11 @@
F: include/tee.h
F: include/tee/
+TEE-lib
+M: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
+S: Maintained
+F: lib/optee
+
UBI
M: Kyungmin Park <kmpark@infradead.org>
M: Heiko Schocher <hs@denx.de>
diff --git a/Makefile b/Makefile
index 516260f..54da5cd 100644
--- a/Makefile
+++ b/Makefile
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
VERSION = 2019
-PATCHLEVEL = 07
+PATCHLEVEL = 10
SUBLEVEL =
EXTRAVERSION =
NAME =
@@ -874,7 +874,7 @@
ALL-y += $(CONFIG_BUILD_TARGET:"%"=%)
endif
-ifneq ($(CONFIG_SYS_INIT_SP_BSS_OFFSET),)
+ifdef CONFIG_INIT_SP_RELATIVE
ALL-y += init_sp_bss_offset_check
endif
@@ -882,6 +882,10 @@
ALL-y += u-boot-with-dtb.bin
endif
+ifeq ($(CONFIG_ARCH_ROCKCHIP)$(CONFIG_SPL)$(CONFIG_TPL),yyy)
+ALL-y += idbloader.img
+endif
+
LDFLAGS_u-boot += $(LDFLAGS_FINAL)
# Avoid 'Not enough room for program headers' error on binutils 2.28 onwards.
@@ -936,11 +940,12 @@
endif
endif
endif
-ifeq ($(CONFIG_DM_I2C_COMPAT)$(CONFIG_SANDBOX),y)
+ifneq ($(CONFIG_DM),y)
@echo >&2 "===================== WARNING ======================"
- @echo >&2 "This board uses CONFIG_DM_I2C_COMPAT. Please remove"
- @echo >&2 "(possibly in a subsequent patch in your series)"
- @echo >&2 "before sending patches to the mailing list."
+ @echo >&2 "This board does not use CONFIG_DM. CONFIG_DM will be"
+ @echo >&2 "compulsory starting with the v2020.01 release."
+ @echo >&2 "Failure to update may result in board removal."
+ @echo >&2 "See doc/driver-model/migration.rst for more info."
@echo >&2 "===================================================="
endif
ifeq ($(CONFIG_MMC),y)
@@ -1033,6 +1038,17 @@
@echo >&2 "===================================================="
endif
endif
+ifneq ($(CONFIG_NET),)
+ifneq ($(CONFIG_DM_ETH),y)
+ @echo >&2 "===================== WARNING ======================"
+ @echo >&2 "This board does not use CONFIG_DM_ETH (Driver Model"
+ @echo >&2 "for Ethernet drivers). Please update the board to use"
+ @echo >&2 "CONFIG_DM_ETH before the v2020.07 release. Failure to"
+ @echo >&2 "update by the deadline may result in board removal."
+ @echo >&2 "See doc/driver-model/migration.rst for more info."
+ @echo >&2 "===================================================="
+endif
+endif
@# Check that this build does not use CONFIG options that we do not
@# know about unless they are in Kconfig. All the existing CONFIG
@# options are whitelisted, so new ones should not be added.
@@ -1155,7 +1171,7 @@
fi \
fi
-ifneq ($(CONFIG_SYS_INIT_SP_BSS_OFFSET),)
+ifdef CONFIG_INIT_SP_RELATIVE
ifneq ($(CONFIG_SYS_MALLOC_F_LEN),)
subtract_sys_malloc_f_len = space=$$(($${space} - $(CONFIG_SYS_MALLOC_F_LEN)))
else
@@ -1196,9 +1212,10 @@
# ---------------------------------------------------------------------------
# Use 'make BINMAN_DEBUG=1' to enable debugging
quiet_cmd_binman = BINMAN $@
-cmd_binman = $(srctree)/tools/binman/binman -u -d u-boot.dtb -O . -m \
+cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \
+ build -u -d u-boot.dtb -O . -m \
-I . -I $(srctree) -I $(srctree)/board/$(BOARDDIR) \
- $(if $(BINMAN_DEBUG),-D) $(BINMAN_$(@F)) $<
+ $(BINMAN_$(@F))
OBJCOPYFLAGS_u-boot.ldr.hex := -I binary -O ihex
@@ -1215,7 +1232,7 @@
CONFIG_SYS_UBOOT_START := 0
endif
-# Boards with more complex image requirments can provide an .its source file
+# Boards with more complex image requirements can provide an .its source file
# or a generator script
ifneq ($(CONFIG_SPL_FIT_SOURCE),"")
U_BOOT_ITS = $(subst ",,$(CONFIG_SPL_FIT_SOURCE))
@@ -1262,8 +1279,16 @@
MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
-R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage
+ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy)
+UBOOT_BIN := u-boot-with-dtb.bin
+else
+UBOOT_BIN := u-boot.bin
+endif
+
u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl u-boot-ivt.img: \
- $(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin dts/dt.dtb,u-boot.bin) FORCE
+ $(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin \
+ $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_OF_HOSTFILE),dts/dt.dtb) \
+ ,$(UBOOT_BIN)) FORCE
$(call if_changed,mkimage)
$(BOARD_SIZE_CHECK)
@@ -1273,7 +1298,9 @@
MKIMAGEFLAGS_u-boot.itb = -E
endif
-u-boot.itb: u-boot-nodtb.bin dts/dt.dtb $(U_BOOT_ITS) FORCE
+u-boot.itb: u-boot-nodtb.bin \
+ $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_OF_HOSTFILE),dts/dt.dtb) \
+ $(U_BOOT_ITS) FORCE
$(call if_changed,mkfitimage)
$(BOARD_SIZE_CHECK)
@@ -1299,6 +1326,14 @@
u-boot-with-spl.bin: $(SPL_IMAGE) $(SPL_PAYLOAD) FORCE
$(call if_changed,pad_cat)
+ifeq ($(CONFIG_ARCH_ROCKCHIP),y)
+MKIMAGEFLAGS_u-boot-tpl.img = -n $(CONFIG_SYS_SOC) -T rksd
+tpl/u-boot-tpl.img: tpl/u-boot-tpl.bin FORCE
+ $(call if_changed,mkimage)
+idbloader.img: tpl/u-boot-tpl.img spl/u-boot-spl.bin FORCE
+ $(call if_changed,cat)
+endif
+
ifeq ($(CONFIG_ARCH_LPC32XX)$(CONFIG_SPL),yy)
MKIMAGEFLAGS_lpc32xx-spl.img = -T lpc32xximage -a $(CONFIG_SPL_TEXT_BASE)
@@ -1696,7 +1731,7 @@
(grep -v '^#' | \
grep -v '^$$' | \
tr '\n' '\0' | \
- sed -e 's/\\\x0/\n/' | \
+ sed -e 's/\\\x0/\n/g' | \
xxd -i ; echo ", 0x00" ; )
endef
@@ -1840,7 +1875,7 @@
$(call cmd,rmfiles)
@find $(if $(KBUILD_EXTMOD), $(KBUILD_EXTMOD), .) $(RCS_FIND_IGNORE) \
\( -name '*.[oas]' -o -name '*.ko' -o -name '.*.cmd' \
- -o -name '*.ko.*' -o -name '*.su' \
+ -o -name '*.ko.*' -o -name '*.su' -o -name '*.pyc' \
-o -name '.*.d' -o -name '.*.tmp' -o -name '*.mod.c' \
-o -name '*.lex.c' -o -name '*.tab.[ch]' \
-o -name '*.symtypes' -o -name 'modules.order' \
@@ -1848,7 +1883,7 @@
-o -name 'dsdt.aml' -o -name 'dsdt.asl.tmp' -o -name 'dsdt.c' \
-o -name '*.efi' -o -name '*.gcno' -o -name '*.so' \) \
-type f -print | xargs rm -f \
- bl31.c bl31.elf bl31_*.bin image.map
+ bl31.c bl31.elf bl31_*.bin image.map tispl.bin*
# mrproper - Delete all generated files, including .config
#
diff --git a/README b/README
index 8f816ad..1389e8f 100644
--- a/README
+++ b/README
@@ -83,7 +83,7 @@
* Provide extended interface to Linux boot loader
* S-Record download
* network boot
- * PCMCIA / CompactFlash / ATA disk / SCSI ... boot
+ * ATA disk / SCSI ... boot
- create ARMBoot project (http://sourceforge.net/projects/armboot)
- add other CPU families (starting with ARM)
- create U-Boot project (http://sourceforge.net/projects/u-boot)
@@ -212,7 +212,7 @@
specific to be undertaken on a native platform. The sandbox is also used to
run some of U-Boot's tests.
-See board/sandbox/README.sandbox for more details.
+See doc/arch/index.rst for more details.
Board Initialisation Flow:
@@ -267,6 +267,13 @@
- preloader_console_init() can be called here in extremis
- should set up SDRAM, and anything needed to make the UART work
- these is no need to clear BSS, it will be done by crt0.S
+ - for specific scenarios on certain architectures an early BSS *can*
+ be made available (via CONFIG_SPL_EARLY_BSS by moving the clearing
+ of BSS prior to entering board_init_f()) but doing so is discouraged.
+ Instead it is strongly recommended to architect any code changes
+ or additions such to not depend on the availability of BSS during
+ board_init_f() as indicated in other sections of this README to
+ maintain compatibility and consistency across the entire code base.
- must return normally from this function (don't call board_init_r()
directly)
@@ -960,10 +967,6 @@
CONFIG_SH_ETHER_CACHE_WRITEBACK
If this option is set, the driver enables cache flush.
-- PWM Support:
- CONFIG_PWM_IMX
- Support for PWM module on the imx6.
-
- TPM Support:
CONFIG_TPM
Support TPM devices.
@@ -2138,171 +2141,6 @@
A better solution is to properly configure the firewall,
but sometimes that is not allowed.
-- Show boot progress:
- CONFIG_SHOW_BOOT_PROGRESS
-
- Defining this option allows to add some board-
- specific code (calling a user-provided function
- "show_boot_progress(int)") that enables you to show
- the system's boot progress on some display (for
- example, some LED's) on your board. At the moment,
- the following checkpoints are implemented:
-
-
-Legacy uImage format:
-
- Arg Where When
- 1 common/cmd_bootm.c before attempting to boot an image
- -1 common/cmd_bootm.c Image header has bad magic number
- 2 common/cmd_bootm.c Image header has correct magic number
- -2 common/cmd_bootm.c Image header has bad checksum
- 3 common/cmd_bootm.c Image header has correct checksum
- -3 common/cmd_bootm.c Image data has bad checksum
- 4 common/cmd_bootm.c Image data has correct checksum
- -4 common/cmd_bootm.c Image is for unsupported architecture
- 5 common/cmd_bootm.c Architecture check OK
- -5 common/cmd_bootm.c Wrong Image Type (not kernel, multi)
- 6 common/cmd_bootm.c Image Type check OK
- -6 common/cmd_bootm.c gunzip uncompression error
- -7 common/cmd_bootm.c Unimplemented compression type
- 7 common/cmd_bootm.c Uncompression OK
- 8 common/cmd_bootm.c No uncompress/copy overwrite error
- -9 common/cmd_bootm.c Unsupported OS (not Linux, BSD, VxWorks, QNX)
-
- 9 common/image.c Start initial ramdisk verification
- -10 common/image.c Ramdisk header has bad magic number
- -11 common/image.c Ramdisk header has bad checksum
- 10 common/image.c Ramdisk header is OK
- -12 common/image.c Ramdisk data has bad checksum
- 11 common/image.c Ramdisk data has correct checksum
- 12 common/image.c Ramdisk verification complete, start loading
- -13 common/image.c Wrong Image Type (not PPC Linux ramdisk)
- 13 common/image.c Start multifile image verification
- 14 common/image.c No initial ramdisk, no multifile, continue.
-
- 15 arch/<arch>/lib/bootm.c All preparation done, transferring control to OS
-
- -30 arch/powerpc/lib/board.c Fatal error, hang the system
- -31 post/post.c POST test failed, detected by post_output_backlog()
- -32 post/post.c POST test failed, detected by post_run_single()
-
- 34 common/cmd_doc.c before loading a Image from a DOC device
- -35 common/cmd_doc.c Bad usage of "doc" command
- 35 common/cmd_doc.c correct usage of "doc" command
- -36 common/cmd_doc.c No boot device
- 36 common/cmd_doc.c correct boot device
- -37 common/cmd_doc.c Unknown Chip ID on boot device
- 37 common/cmd_doc.c correct chip ID found, device available
- -38 common/cmd_doc.c Read Error on boot device
- 38 common/cmd_doc.c reading Image header from DOC device OK
- -39 common/cmd_doc.c Image header has bad magic number
- 39 common/cmd_doc.c Image header has correct magic number
- -40 common/cmd_doc.c Error reading Image from DOC device
- 40 common/cmd_doc.c Image header has correct magic number
- 41 common/cmd_ide.c before loading a Image from a IDE device
- -42 common/cmd_ide.c Bad usage of "ide" command
- 42 common/cmd_ide.c correct usage of "ide" command
- -43 common/cmd_ide.c No boot device
- 43 common/cmd_ide.c boot device found
- -44 common/cmd_ide.c Device not available
- 44 common/cmd_ide.c Device available
- -45 common/cmd_ide.c wrong partition selected
- 45 common/cmd_ide.c partition selected
- -46 common/cmd_ide.c Unknown partition table
- 46 common/cmd_ide.c valid partition table found
- -47 common/cmd_ide.c Invalid partition type
- 47 common/cmd_ide.c correct partition type
- -48 common/cmd_ide.c Error reading Image Header on boot device
- 48 common/cmd_ide.c reading Image Header from IDE device OK
- -49 common/cmd_ide.c Image header has bad magic number
- 49 common/cmd_ide.c Image header has correct magic number
- -50 common/cmd_ide.c Image header has bad checksum
- 50 common/cmd_ide.c Image header has correct checksum
- -51 common/cmd_ide.c Error reading Image from IDE device
- 51 common/cmd_ide.c reading Image from IDE device OK
- 52 common/cmd_nand.c before loading a Image from a NAND device
- -53 common/cmd_nand.c Bad usage of "nand" command
- 53 common/cmd_nand.c correct usage of "nand" command
- -54 common/cmd_nand.c No boot device
- 54 common/cmd_nand.c boot device found
- -55 common/cmd_nand.c Unknown Chip ID on boot device
- 55 common/cmd_nand.c correct chip ID found, device available
- -56 common/cmd_nand.c Error reading Image Header on boot device
- 56 common/cmd_nand.c reading Image Header from NAND device OK
- -57 common/cmd_nand.c Image header has bad magic number
- 57 common/cmd_nand.c Image header has correct magic number
- -58 common/cmd_nand.c Error reading Image from NAND device
- 58 common/cmd_nand.c reading Image from NAND device OK
-
- -60 common/env_common.c Environment has a bad CRC, using default
-
- 64 net/eth.c starting with Ethernet configuration.
- -64 net/eth.c no Ethernet found.
- 65 net/eth.c Ethernet found.
-
- -80 common/cmd_net.c usage wrong
- 80 common/cmd_net.c before calling net_loop()
- -81 common/cmd_net.c some error in net_loop() occurred
- 81 common/cmd_net.c net_loop() back without error
- -82 common/cmd_net.c size == 0 (File with size 0 loaded)
- 82 common/cmd_net.c trying automatic boot
- 83 common/cmd_net.c running "source" command
- -83 common/cmd_net.c some error in automatic boot or "source" command
- 84 common/cmd_net.c end without errors
-
-FIT uImage format:
-
- Arg Where When
- 100 common/cmd_bootm.c Kernel FIT Image has correct format
- -100 common/cmd_bootm.c Kernel FIT Image has incorrect format
- 101 common/cmd_bootm.c No Kernel subimage unit name, using configuration
- -101 common/cmd_bootm.c Can't get configuration for kernel subimage
- 102 common/cmd_bootm.c Kernel unit name specified
- -103 common/cmd_bootm.c Can't get kernel subimage node offset
- 103 common/cmd_bootm.c Found configuration node
- 104 common/cmd_bootm.c Got kernel subimage node offset
- -104 common/cmd_bootm.c Kernel subimage hash verification failed
- 105 common/cmd_bootm.c Kernel subimage hash verification OK
- -105 common/cmd_bootm.c Kernel subimage is for unsupported architecture
- 106 common/cmd_bootm.c Architecture check OK
- -106 common/cmd_bootm.c Kernel subimage has wrong type
- 107 common/cmd_bootm.c Kernel subimage type OK
- -107 common/cmd_bootm.c Can't get kernel subimage data/size
- 108 common/cmd_bootm.c Got kernel subimage data/size
- -108 common/cmd_bootm.c Wrong image type (not legacy, FIT)
- -109 common/cmd_bootm.c Can't get kernel subimage type
- -110 common/cmd_bootm.c Can't get kernel subimage comp
- -111 common/cmd_bootm.c Can't get kernel subimage os
- -112 common/cmd_bootm.c Can't get kernel subimage load address
- -113 common/cmd_bootm.c Image uncompress/copy overwrite error
-
- 120 common/image.c Start initial ramdisk verification
- -120 common/image.c Ramdisk FIT image has incorrect format
- 121 common/image.c Ramdisk FIT image has correct format
- 122 common/image.c No ramdisk subimage unit name, using configuration
- -122 common/image.c Can't get configuration for ramdisk subimage
- 123 common/image.c Ramdisk unit name specified
- -124 common/image.c Can't get ramdisk subimage node offset
- 125 common/image.c Got ramdisk subimage node offset
- -125 common/image.c Ramdisk subimage hash verification failed
- 126 common/image.c Ramdisk subimage hash verification OK
- -126 common/image.c Ramdisk subimage for unsupported architecture
- 127 common/image.c Architecture check OK
- -127 common/image.c Can't get ramdisk subimage data/size
- 128 common/image.c Got ramdisk subimage data/size
- 129 common/image.c Can't get ramdisk load address
- -129 common/image.c Got ramdisk load address
-
- -130 common/cmd_doc.c Incorrect FIT image format
- 131 common/cmd_doc.c FIT image format OK
-
- -140 common/cmd_ide.c Incorrect FIT image format
- 141 common/cmd_ide.c FIT image format OK
-
- -150 common/cmd_nand.c Incorrect FIT image format
- 151 common/cmd_nand.c FIT image format OK
-
-- Standalone program support:
CONFIG_STANDALONE_LOAD_ADDR
This option defines a board specific value for the
@@ -3590,6 +3428,8 @@
allowed for use by the bootm command. See also "bootm_low"
environment variable.
+ bootstopkeysha256, bootdelaykey, bootstopkey - See README.autoboot
+
updatefile - Location of the software update file on a TFTP server, used
by the automatic software update feature. Please refer to
documentation in doc/README.update for more details.
diff --git a/api/api.c b/api/api.c
index 9f03f1a..bc9454e 100644
--- a/api/api.c
+++ b/api/api.c
@@ -8,8 +8,9 @@
#include <config.h>
#include <command.h>
#include <common.h>
+#include <env.h>
#include <malloc.h>
-#include <environment.h>
+#include <env_internal.h>
#include <linux/types.h>
#include <api_public.h>
@@ -496,7 +497,7 @@
{
int i, buflen;
char *last, **next, *s;
- ENTRY *match, search;
+ struct env_entry *match, search;
static char *var;
last = (char *)va_arg(ap, unsigned long);
@@ -513,7 +514,7 @@
if (s != NULL)
*s = 0;
search.key = var;
- i = hsearch_r(search, FIND, &match, &env_htab, 0);
+ i = hsearch_r(search, ENV_FIND, &match, &env_htab, 0);
if (i == 0) {
i = API_EINVAL;
goto done;
diff --git a/arch/Kconfig b/arch/Kconfig
index 28afe39..141e48b 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -76,6 +76,12 @@
imply MTD
imply TIMER
imply CMD_DM
+ imply SPL_DM
+ imply SPL_OF_CONTROL
+ imply SPL_LIBCOMMON_SUPPORT
+ imply SPL_LIBGENERIC_SUPPORT
+ imply SPL_SERIAL_SUPPORT
+ imply SPL_TIMER
config SANDBOX
bool "Sandbox"
@@ -90,8 +96,10 @@
select DM_SPI_FLASH
select HAVE_BLOCK_DEVICE
select LZO
+ select PCI_ENDPOINT
select SPI
select SUPPORT_OF_CONTROL
+ select SYSRESET_CMD_POWEROFF if CMD_POWEROFF
imply BITREVERSE
select BLOBLIST
imply CMD_DM
@@ -120,11 +128,16 @@
imply VIRTIO_BLK
imply VIRTIO_NET
imply DM_SOUND
+ imply PCI_SANDBOX_EP
imply PCH
+ imply PHYLIB
+ imply DM_MDIO
+ imply DM_MDIO_MUX
config SH
bool "SuperH architecture"
select HAVE_PRIVATE_LIBGCC
+ select SUPPORT_OF_CONTROL
config X86
bool "x86 architecture"
diff --git a/arch/arc/dts/axs10x_mb.dtsi b/arch/arc/dts/axs10x_mb.dtsi
index 6d97de9..5b77642 100644
--- a/arch/arc/dts/axs10x_mb.dtsi
+++ b/arch/arc/dts/axs10x_mb.dtsi
@@ -53,7 +53,7 @@
};
ethernet@18000 {
- compatible = "altr,socfpga-stmmac";
+ compatible = "snps,arc-dwmac-3.70a";
reg = < 0x18000 0x2000 >;
phy-mode = "gmii";
snps,pbl = < 32 >;
diff --git a/arch/arc/dts/hsdk.dts b/arch/arc/dts/hsdk.dts
index 7028050..34ef3a6 100644
--- a/arch/arc/dts/hsdk.dts
+++ b/arch/arc/dts/hsdk.dts
@@ -71,7 +71,7 @@
ethernet@f0008000 {
#interrupt-cells = <1>;
- compatible = "altr,socfpga-stmmac";
+ compatible = "snps,arc-dwmac-3.70a";
reg = <0xf0008000 0x2000>;
phy-mode = "gmii";
};
diff --git a/arch/arc/lib/libgcc2.c b/arch/arc/lib/libgcc2.c
index b92a841..ab1dbe1 100644
--- a/arch/arc/lib/libgcc2.c
+++ b/arch/arc/lib/libgcc2.c
@@ -158,3 +158,78 @@
{
return udivmodsi4(a, b, 1);
}
+
+UDWtype
+__udivmoddi4(UDWtype n, UDWtype d, UDWtype *rp)
+{
+ UDWtype q = 0, r = n, y = d;
+ UWtype lz1, lz2, i, k;
+
+ /*
+ * Implements align divisor shift dividend method. This algorithm
+ * aligns the divisor under the dividend and then perform number of
+ * test-subtract iterations which shift the dividend left. Number of
+ * iterations is k + 1 where k is the number of bit positions the
+ * divisor must be shifted left to align it under the dividend.
+ * quotient bits can be saved in the rightmost positions of the
+ * dividend as it shifts left on each test-subtract iteration.
+ */
+
+ if (y <= r) {
+ lz1 = __builtin_clzll(d);
+ lz2 = __builtin_clzll(n);
+
+ k = lz1 - lz2;
+ y = (y << k);
+
+ /*
+ * Dividend can exceed 2 ^ (width - 1) - 1 but still be less
+ * than the aligned divisor. Normal iteration can drops the
+ * high order bit of the dividend. Therefore, first
+ * test-subtract iteration is a special case, saving its
+ * quotient bit in a separate location and not shifting
+ * the dividend.
+ */
+
+ if (r >= y) {
+ r = r - y;
+ q = (1ULL << k);
+ }
+
+ if (k > 0) {
+ y = y >> 1;
+
+ /*
+ * k additional iterations where k regular test
+ * subtract shift dividend iterations are done.
+ */
+ i = k;
+ do {
+ if (r >= y)
+ r = ((r - y) << 1) + 1;
+ else
+ r = (r << 1);
+ i = i - 1;
+ } while (i != 0);
+
+ /*
+ * First quotient bit is combined with the quotient
+ * bits resulting from the k regular iterations.
+ */
+ q = q + r;
+ r = r >> k;
+ q = q - (r << k);
+ }
+ }
+
+ if (rp)
+ *rp = r;
+
+ return q;
+}
+
+UDWtype
+__udivdi3(UDWtype n, UDWtype d)
+{
+ return __udivmoddi4(n, d, (UDWtype *)0);
+}
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f5a7630..3b0e315 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -20,15 +20,25 @@
information that is embedded into the binary to support U-Boot
relocating itself to the top-of-RAM later during execution.
-config SYS_INIT_SP_BSS_OFFSET
- int
+config INIT_SP_RELATIVE
+ bool "Specify the early stack pointer relative to the .bss section"
help
U-Boot typically uses a hard-coded value for the stack pointer
- before relocation. Define this option to instead calculate the
+ before relocation. Enable this option to instead calculate the
initial SP at run-time. This is useful to avoid hard-coding addresses
into U-Boot, so that can be loaded and executed at arbitrary
- addresses and thus avoid using arbitrary addresses at runtime. This
- option's value is the offset added to &_bss_start in order to
+ addresses and thus avoid using arbitrary addresses at runtime.
+
+ If this option is enabled, the early stack pointer is set to
+ &_bss_start with a offset value added. The offset is specified by
+ SYS_INIT_SP_BSS_OFFSET.
+
+config SYS_INIT_SP_BSS_OFFSET
+ int "Early stack offset from the .bss base address"
+ depends on INIT_SP_RELATIVE
+ default 524288
+ help
+ This option's value is the offset added to &_bss_start in order to
calculate the stack pointer. This offset should be large enough so
that the early malloc region, global data (gd), and early stack usage
do not overlap any appended DTB.
@@ -319,6 +329,12 @@
default 64 if SYS_CACHE_SHIFT_6
default 32 if SYS_CACHE_SHIFT_5
+config ARCH_CPU_INIT
+ bool "Enable ARCH_CPU_INIT"
+ help
+ Some architectures require a call to arch_cpu_init()
+ Say Y here to enable it
+
config SYS_ARCH_TIMER
bool "ARM Generic Timer support"
depends on CPU_V7A || ARM64
@@ -357,7 +373,7 @@
config SPL_SYS_THUMB_BUILD
bool "Build SPL using the Thumb instruction set"
default y if SYS_THUMB_BUILD
- depends on !ARM64
+ depends on !ARM64 && SPL
help
Use this flag to build SPL using the Thumb instruction set for
ARM architectures. Thumb instruction set provides better code
@@ -404,7 +420,7 @@
config SPL_USE_ARCH_MEMCPY
bool "Use an assembly optimized implementation of memcpy for SPL"
default y if USE_ARCH_MEMCPY
- depends on !ARM64
+ depends on !ARM64 && SPL
help
Enable the generation of an optimized version of memcpy.
Such implementation may be faster under some conditions
@@ -413,7 +429,7 @@
config TPL_USE_ARCH_MEMCPY
bool "Use an assembly optimized implementation of memcpy for TPL"
default y if USE_ARCH_MEMCPY
- depends on !ARM64
+ depends on !ARM64 && TPL
help
Enable the generation of an optimized version of memcpy.
Such implementation may be faster under some conditions
@@ -431,7 +447,7 @@
config SPL_USE_ARCH_MEMSET
bool "Use an assembly optimized implementation of memset for SPL"
default y if USE_ARCH_MEMSET
- depends on !ARM64
+ depends on !ARM64 && SPL
help
Enable the generation of an optimized version of memset.
Such implementation may be faster under some conditions
@@ -440,7 +456,7 @@
config TPL_USE_ARCH_MEMSET
bool "Use an assembly optimized implementation of memset for TPL"
default y if USE_ARCH_MEMSET
- depends on !ARM64
+ depends on !ARM64 && TPL
help
Enable the generation of an optimized version of memset.
Such implementation may be faster under some conditions
@@ -448,7 +464,8 @@
config ARM64_SUPPORT_AARCH32
bool "ARM64 system support AArch32 execution state"
- default y if ARM64 && !TARGET_THUNDERX_88XX
+ depends on ARM64
+ default y if !TARGET_THUNDERX_88XX
help
This ARM64 system supports AArch32 execution state.
@@ -830,6 +847,7 @@
config ARCH_QEMU
bool "QEMU Virtual Platform"
+ select ARCH_SUPPORT_TFABOOT
select DM
select DM_SERIAL
select OF_CONTROL
@@ -884,10 +902,14 @@
select SPL_OF_CONTROL
select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10
select SPL_SERIAL_SUPPORT
+ select SPL_SYSRESET
select SPL_WATCHDOG_SUPPORT
select SUPPORT_SPL
select SYS_NS16550
select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
+ select SYSRESET
+ select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
+ select SYSRESET_SOCFPGA_S10 if TARGET_SOCFPGA_STRATIX10
imply CMD_DM
imply CMD_MTDPARTS
imply CRC32_VERIFY
@@ -926,6 +948,7 @@
select SPL_STACK_R if SPL
select SPL_SYS_MALLOC_SIMPLE if SPL
select SPL_SYS_THUMB_BUILD if !ARM64
+ select SUNXI_GPIO
select SYS_NS16550
select SYS_THUMB_BUILD if !ARM64
select USB if DISTRO_DEFAULTS
@@ -1043,16 +1066,6 @@
select PL01X_SERIAL
select SEMIHOSTING
-config TARGET_VEXPRESS64_BASE_FVP_DRAM
- bool "Support Versatile Express ARMv8a FVP BASE model booting from DRAM"
- select ARM64
- select PL01X_SERIAL
- help
- This target is derived from TARGET_VEXPRESS64_BASE_FVP and over-rides
- the default config to allow the user to load the images directly into
- DRAM using model parameters rather than by using semi-hosting to load
- the files from the host filesystem.
-
config TARGET_VEXPRESS64_JUNO
bool "Support Versatile Express Juno Development Platform"
select ARM64
@@ -1077,6 +1090,7 @@
select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
+ select BOARD_LATE_INIT
help
Support for Freescale LS2080A_SIMU platform
The LS2080A Development System (QDS) is a pre silicon
@@ -1089,6 +1103,7 @@
select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
+ select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
select SUPPORT_SPL
select FSL_DDR_INTERACTIVE if !SD_BOOT
@@ -1104,6 +1119,7 @@
select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
+ select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
select SUPPORT_SPL
imply SCSI
@@ -1122,6 +1138,7 @@
select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
+ select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
select SUPPORT_SPL
select FSL_DDR_BIST
@@ -1154,6 +1171,7 @@
select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
+ select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
help
Support for NXP LX2160ARDB platform.
@@ -1167,6 +1185,7 @@
select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
+ select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
help
Support for NXP LX2160AQDS platform.
@@ -1188,6 +1207,18 @@
Support for HiKey 96boards platform. It features a HI6220
SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
+config TARGET_HIKEY960
+ bool "Support HiKey960 96boards Consumer Edition Platform"
+ select ARM64
+ select DM
+ select DM_SERIAL
+ select OF_CONTROL
+ select PL01X_SERIAL
+ imply CMD_DM
+ help
+ Support for HiKey960 96boards platform. It features a HI3660
+ SoC, with 4xA73 CPU, 4xA53 CPU, MALI-G71 GPU, and 3GB RAM.
+
config TARGET_POPLAR
bool "Support Poplar 96boards Enterprise Edition Platform"
select ARM64
@@ -1207,6 +1238,7 @@
bool "Support ls1012aqds"
select ARCH_LS1012A
select ARM64
+ select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
help
Support for Freescale LS1012AQDS platform.
@@ -1218,6 +1250,7 @@
bool "Support ls1012ardb"
select ARCH_LS1012A
select ARM64
+ select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
imply SCSI
imply SCSI_AHCI
@@ -1231,6 +1264,7 @@
bool "Support ls1012a2g5rdb"
select ARCH_LS1012A
select ARM64
+ select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
imply SCSI
help
@@ -1243,6 +1277,7 @@
bool "Support ls1012afrwy"
select ARCH_LS1012A
select ARM64
+ select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
imply SCSI
imply SCSI_AHCI
@@ -1256,6 +1291,7 @@
bool "Support ls1012afrdm"
select ARCH_LS1012A
select ARM64
+ select ARCH_SUPPORT_TFABOOT
help
Support for Freescale LS1012AFRDM platform.
The LS1012A Freedom board (FRDM) is a high-performance
@@ -1267,6 +1303,9 @@
select ARCH_LS1028A
select ARM64
select ARMV8_MULTIENTRY
+ select ARCH_SUPPORT_TFABOOT
+ select BOARD_LATE_INIT
+ select ARCH_MISC_INIT
help
Support for Freescale LS1028AQDS platform
The LS1028A Development System (QDS) is a high-performance
@@ -1278,6 +1317,7 @@
select ARCH_LS1028A
select ARM64
select ARMV8_MULTIENTRY
+ select ARCH_SUPPORT_TFABOOT
help
Support for Freescale LS1028ARDB platform
The LS1028A Development System (RDB) is a high-performance
@@ -1290,6 +1330,7 @@
select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
+ select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
select SUPPORT_SPL
select FSL_DDR_INTERACTIVE if !SD_BOOT
@@ -1327,6 +1368,19 @@
select SUPPORT_SPL
imply SCSI
+config TARGET_LS1021ATSN
+ bool "Support ls1021atsn"
+ select ARCH_LS1021A
+ select ARCH_SUPPORT_PSCI
+ select BOARD_EARLY_INIT_F
+ select BOARD_LATE_INIT
+ select CPU_V7A
+ select CPU_V7_HAS_NONSEC
+ select CPU_V7_HAS_VIRT
+ select LS1_DEEP_SLEEP
+ select SUPPORT_SPL
+ imply SCSI
+
config TARGET_LS1021AIOT
bool "Support ls1021aiot"
select ARCH_LS1021A
@@ -1348,6 +1402,7 @@
select ARCH_LS1043A
select ARM64
select ARMV8_MULTIENTRY
+ select ARCH_SUPPORT_TFABOOT
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select SUPPORT_SPL
@@ -1362,6 +1417,7 @@
select ARCH_LS1043A
select ARM64
select ARMV8_MULTIENTRY
+ select ARCH_SUPPORT_TFABOOT
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select SUPPORT_SPL
@@ -1373,6 +1429,7 @@
select ARCH_LS1046A
select ARM64
select ARMV8_MULTIENTRY
+ select ARCH_SUPPORT_TFABOOT
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select DM_SPI_FLASH if DM_SPI
@@ -1392,6 +1449,7 @@
select ARCH_LS1046A
select ARM64
select ARMV8_MULTIENTRY
+ select ARCH_SUPPORT_TFABOOT
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select DM_SPI_FLASH if DM_SPI
@@ -1411,6 +1469,7 @@
select ARCH_LS1046A
select ARM64
select ARMV8_MULTIENTRY
+ select ARCH_SUPPORT_TFABOOT
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select DM_SPI_FLASH if DM_SPI
@@ -1488,6 +1547,7 @@
select MISC
select OF_CONTROL
select OF_LIBFDT
+ select OF_SYSTEM_SETUP
select PINCTRL
select REGMAP
select SUPPORT_SPL
@@ -1497,6 +1557,7 @@
imply SPL_SYSRESET
imply CMD_DM
imply CMD_POWEROFF
+ imply OF_LIBFDT_OVERLAY
imply ENV_VARS_UBOOT_RUNTIME_CONFIG
imply USE_PREBOOT
help
@@ -1553,6 +1614,17 @@
endchoice
+config ARCH_SUPPORT_TFABOOT
+ bool
+
+config TFABOOT
+ bool "Support for booting from TF-A"
+ depends on ARCH_SUPPORT_TFABOOT
+ default n
+ help
+ Enabling this will make a U-Boot binary that is capable of being
+ booted via TF-A.
+
config TI_SECURE_DEVICE
bool "HS Device Type Support"
depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
@@ -1703,6 +1775,7 @@
source "board/freescale/ls1021aqds/Kconfig"
source "board/freescale/ls1043aqds/Kconfig"
source "board/freescale/ls1021atwr/Kconfig"
+source "board/freescale/ls1021atsn/Kconfig"
source "board/freescale/ls1021aiot/Kconfig"
source "board/freescale/ls1046aqds/Kconfig"
source "board/freescale/ls1043ardb/Kconfig"
@@ -1718,6 +1791,7 @@
source "board/gumstix/pepper/Kconfig"
source "board/h2200/Kconfig"
source "board/hisilicon/hikey/Kconfig"
+source "board/hisilicon/hikey960/Kconfig"
source "board/hisilicon/poplar/Kconfig"
source "board/isee/igep003x/Kconfig"
source "board/phytec/pcm051/Kconfig"
diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c
index cbc4364..a651b8c 100644
--- a/arch/arm/cpu/arm1136/mx35/generic.c
+++ b/arch/arm/cpu/arm1136/mx35/generic.c
@@ -14,8 +14,8 @@
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
-#ifdef CONFIG_FSL_ESDHC
-#include <fsl_esdhc.h>
+#ifdef CONFIG_FSL_ESDHC_IMX
+#include <fsl_esdhc_imx.h>
#endif
#include <netdev.h>
#include <spl.h>
@@ -27,7 +27,7 @@
#define CCM_GET_DIVIDER(x, m, o) (((x) & (m)) >> (o))
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
DECLARE_GLOBAL_DATA_PTR;
#endif
@@ -446,7 +446,7 @@
return rc;
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
/*
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()
@@ -459,7 +459,7 @@
int get_clocks(void)
{
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c
index 2795a5f..5fcf06a 100644
--- a/arch/arm/cpu/arm926ejs/mx25/generic.c
+++ b/arch/arm/cpu/arm926ejs/mx25/generic.c
@@ -16,8 +16,8 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
-#ifdef CONFIG_FSL_ESDHC
-#include <fsl_esdhc.h>
+#ifdef CONFIG_FSL_ESDHC_IMX
+#include <fsl_esdhc_imx.h>
DECLARE_GLOBAL_DATA_PTR;
#endif
@@ -233,7 +233,7 @@
int get_clocks(void)
{
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
#if CONFIG_SYS_FSL_ESDHC_ADDR == IMX_MMC_SDHC2_BASE
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
#else
@@ -243,7 +243,7 @@
return 0;
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
/*
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()
diff --git a/arch/arm/cpu/arm926ejs/spear/spl.c b/arch/arm/cpu/arm926ejs/spear/spl.c
index d2bddb5..fc332fb 100644
--- a/arch/arm/cpu/arm926ejs/spear/spl.c
+++ b/arch/arm/cpu/arm926ejs/spear/spl.c
@@ -16,6 +16,12 @@
#include <asm/arch/spr_syscntl.h>
#include <linux/mtd/st_smi.h>
+/* Reserve some space to store the BootROM's stack pointer during SPL operation.
+ * The BSS cannot be used for this purpose because it will be zeroed after
+ * having stored the pointer, so force the location to the data section.
+ */
+u32 bootrom_stash_sp __attribute__((section(".data")));
+
static void ddr_clock_init(void)
{
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
@@ -223,8 +229,9 @@
{
u32 mode = 0;
- /* Currently only SNOR is supported as the only */
- if (snor_boot_selected()) {
+ if (usb_boot_selected()) {
+ mode = BOOT_DEVICE_BOOTROM;
+ } else if (snor_boot_selected()) {
/* SNOR-SMI initialization */
snor_init();
@@ -234,6 +241,18 @@
return mode;
}
+void board_boot_order(u32 *spl_boot_list)
+{
+ spl_boot_list[0] = spl_boot_device();
+
+ /*
+ * If the main boot device (eg. NOR) is empty, try to jump back into the
+ * BootROM for USB boot process.
+ */
+ if (USB_BOOT_SUPPORTED)
+ spl_boot_list[1] = BOOT_DEVICE_BOOTROM;
+}
+
void board_init_f(ulong dummy)
{
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
@@ -251,6 +270,28 @@
puts("Configure DDR\n");
mpmc_init();
spear_late_init();
+}
- board_init_r(NULL, 0);
+/*
+ * In a few cases (Ethernet, UART or USB boot, we might want to go back into the
+ * BootROM code right after having initialized a few components like the DRAM).
+ * The following function is called from SPL common code (board_init_r).
+ */
+void board_return_to_bootrom(void)
+{
+ /*
+ * Retrieve the BootROM's stack pointer and jump back to the start of
+ * the SPL, where we can easily branch back into the BootROM. Don't do
+ * it right here because SPL might be compiled in Thumb mode while the
+ * BootROM expects ARM mode.
+ */
+ asm volatile ("ldr r0, =bootrom_stash_sp;"
+ "ldr r0, [r0];"
+ "mov sp, r0;"
+#if defined(CONFIG_SPL_SYS_THUMB_BUILD)
+ "blx back_to_bootrom;"
+#else
+ "bl back_to_bootrom;"
+#endif
+ );
}
diff --git a/arch/arm/cpu/arm926ejs/spear/spr_misc.c b/arch/arm/cpu/arm926ejs/spear/spr_misc.c
index 371dea5..d36484c 100644
--- a/arch/arm/cpu/arm926ejs/spear/spr_misc.c
+++ b/arch/arm/cpu/arm926ejs/spear/spr_misc.c
@@ -6,7 +6,7 @@
#include <common.h>
#include <command.h>
-#include <environment.h>
+#include <env.h>
#include <i2c.h>
#include <net.h>
#include <linux/mtd/st_smi.h>
diff --git a/arch/arm/cpu/arm926ejs/spear/start.S b/arch/arm/cpu/arm926ejs/spear/start.S
index 1cab4ca..9ac9629 100644
--- a/arch/arm/cpu/arm926ejs/spear/start.S
+++ b/arch/arm/cpu/arm926ejs/spear/start.S
@@ -21,51 +21,35 @@
*
* Startup Code (reset vector)
*
- * Below are the critical initializations already taken place in BootROM.
- * So, these are not taken care in Xloader
- * 1. Relocation to RAM
- * 2. Initializing stacks
+ * The BootROM already initialized its own stack in the [0-0xb00] reserved
+ * range of the SRAM. The SPL (in _main) will update the stack pointer to
+ * its own SRAM area (right before the gd section).
*
*************************************************************************
*/
.globl reset
+ .globl back_to_bootrom
reset:
-/*
- * Xloader has to return back to BootROM in a few cases.
- * eg. Ethernet boot, UART boot, USB boot
- * Saving registers for returning back
- */
- stmdb sp!, {r0-r12,r14}
- bl cpu_init_crit
-/*
- * Clearing bss area is not done in Xloader.
- * BSS area lies in the DDR location which is not yet initialized
- * bss is assumed to be uninitialized.
- */
- ldmia sp!, {r0-r12,pc}
-
-/*
- *************************************************************************
- *
- * CPU_init_critical registers
- *
- * setup important registers
- * setup memory timing
- *
- *************************************************************************
- */
-cpu_init_crit:
/*
- * flush v4 I/D caches
+ * SPL has to return back to BootROM in a few cases (eg. Ethernet boot,
+ * UART boot, USB boot): save registers in BootROM's stack and then the
+ * BootROM's stack pointer in the SPL's data section.
+ */
+ push {r0-r12,lr}
+ ldr r0, =bootrom_stash_sp
+ str sp, [r0]
+
+ /*
+ * Flush v4 I/D caches
*/
mov r0, #0
- mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
- mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
+ mcr p15, 0, r0, c7, c7, 0 /* Flush v3/v4 cache */
+ mcr p15, 0, r0, c8, c7, 0 /* Flush v4 TLB */
/*
- * enable instruction cache
+ * Enable instruction cache
*/
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
@@ -73,7 +57,9 @@
/*
* Go setup Memory and board specific bits prior to relocation.
+ * This call is not supposed to return.
*/
- stmdb sp!, {lr}
- bl _main /* _main will call board_init_f */
- ldmia sp!, {pc}
+ b _main /* _main will call board_init_f */
+
+back_to_bootrom:
+ pop {r0-r12,pc}
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index ecf9e86..9ccfe10 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -296,7 +296,7 @@
int cpu_eth_init(bd_t *bis)
{
-#ifdef CONFIG_TSEC_ENET
+#if defined(CONFIG_TSEC_ENET) && !defined(CONFIG_DM_ETH)
tsec_standard_init(bis);
#endif
diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c
index 8bf9c42..1aadfff 100644
--- a/arch/arm/cpu/armv7/ls102xa/fdt.c
+++ b/arch/arm/cpu/armv7/ls102xa/fdt.c
@@ -16,12 +16,17 @@
#include <tsec.h>
#include <asm/arch/immap_ls102xa.h>
#include <fsl_sec.h>
+#include <dm.h>
DECLARE_GLOBAL_DATA_PTR;
void ft_fixup_enet_phy_connect_type(void *fdt)
{
+#ifdef CONFIG_DM_ETH
+ struct udevice *dev;
+#else
struct eth_device *dev;
+#endif
struct tsec_private *priv;
const char *enet_path, *phy_path;
char enet[16];
@@ -29,7 +34,12 @@
int phy_node;
int i = 0;
uint32_t ph;
+#ifdef CONFIG_DM_ETH
+ char *name[3] = { "ethernet@2d10000", "ethernet@2d50000",
+ "ethernet@2d90000" };
+#else
char *name[3] = { "eTSEC1", "eTSEC2", "eTSEC3" };
+#endif
for (; i < ARRAY_SIZE(name); i++) {
dev = eth_get_dev_by_name(name[i]);
diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c
index f3e8f99..2c5d99e 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.c
+++ b/arch/arm/cpu/armv7/sunxi/psci.c
@@ -276,7 +276,7 @@
return ARM_PSCI_RET_SUCCESS;
}
-void __secure psci_cpu_off(void)
+s32 __secure psci_cpu_off(void)
{
psci_cpu_off_common();
diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c
index f962903..7e4641f 100644
--- a/arch/arm/cpu/armv7/vf610/generic.c
+++ b/arch/arm/cpu/armv7/vf610/generic.c
@@ -9,12 +9,13 @@
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/mach-imx/sys_proto.h>
+#include <env.h>
#include <netdev.h>
-#ifdef CONFIG_FSL_ESDHC
-#include <fsl_esdhc.h>
+#ifdef CONFIG_FSL_ESDHC_IMX
+#include <fsl_esdhc_imx.h>
#endif
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
DECLARE_GLOBAL_DATA_PTR;
#endif
@@ -345,7 +346,7 @@
return rc;
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
int cpu_mmc_init(bd_t *bis)
{
return fsl_esdhc_mmc_init(bis);
@@ -354,7 +355,7 @@
int get_clocks(void)
{
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
#endif
return 0;
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 3f6c983..24c606a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -40,14 +40,6 @@
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
select SYS_I2C_MXC
- select SYS_I2C_MXC_I2C1
- select SYS_I2C_MXC_I2C2
- select SYS_I2C_MXC_I2C3
- select SYS_I2C_MXC_I2C4
- select SYS_I2C_MXC_I2C5
- select SYS_I2C_MXC_I2C6
- select SYS_I2C_MXC_I2C7
- select SYS_I2C_MXC_I2C8
select SYS_FSL_ERRATUM_A008997
select SYS_FSL_ERRATUM_A009007
select SYS_FSL_ERRATUM_A008514 if !TFABOOT
@@ -155,10 +147,10 @@
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
select SYS_I2C_MXC
- select SYS_I2C_MXC_I2C1
- select SYS_I2C_MXC_I2C2
- select SYS_I2C_MXC_I2C3
- select SYS_I2C_MXC_I2C4
+ select SYS_I2C_MXC_I2C1 if !TFABOOT
+ select SYS_I2C_MXC_I2C2 if !TFABOOT
+ select SYS_I2C_MXC_I2C3 if !TFABOOT
+ select SYS_I2C_MXC_I2C4 if !TFABOOT
imply SCSI
imply PANIC_HANG
@@ -205,10 +197,10 @@
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
select SYS_I2C_MXC
- select SYS_I2C_MXC_I2C1
- select SYS_I2C_MXC_I2C2
- select SYS_I2C_MXC_I2C3
- select SYS_I2C_MXC_I2C4
+ select SYS_I2C_MXC_I2C1 if !TFABOOT
+ select SYS_I2C_MXC_I2C2 if !TFABOOT
+ select SYS_I2C_MXC_I2C3 if !TFABOOT
+ select SYS_I2C_MXC_I2C4 if !TFABOOT
imply DISTRO_DEFAULTS
imply PANIC_HANG
@@ -235,14 +227,6 @@
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
select SYS_I2C_MXC
- select SYS_I2C_MXC_I2C1
- select SYS_I2C_MXC_I2C2
- select SYS_I2C_MXC_I2C3
- select SYS_I2C_MXC_I2C4
- select SYS_I2C_MXC_I2C5
- select SYS_I2C_MXC_I2C6
- select SYS_I2C_MXC_I2C7
- select SYS_I2C_MXC_I2C8
imply DISTRO_DEFAULTS
imply PANIC_HANG
imply SCSI
@@ -261,14 +245,6 @@
config NXP_LSCH3_2
bool
-config FSL_MC_ENET
- bool "Management Complex network"
- depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A
- default y
- select RESV_RAM
- help
- Enable Management Complex (MC) network
-
menu "Layerscape architecture"
depends on FSL_LSCH2 || FSL_LSCH3
@@ -513,6 +489,10 @@
config SYS_FSL_I2C_CLK_DIV
int "I2C clock divider"
default 1 if ARCH_LS1043A
+ default 4 if ARCH_LS1012A
+ default 4 if ARCH_LS1028A
+ default 8 if ARCH_LX2160A
+ default 8 if ARCH_LS1088A
default 2
help
This is the divider that is used to derive I2C clock from Platform
@@ -521,6 +501,10 @@
config SYS_FSL_IFC_CLK_DIV
int "IFC clock divider"
default 1 if ARCH_LS1043A
+ default 4 if ARCH_LS1012A
+ default 4 if ARCH_LS1028A
+ default 8 if ARCH_LX2160A
+ default 8 if ARCH_LS1088A
default 2
help
This is the divider that is used to derive IFC clock from Platform
@@ -605,15 +589,6 @@
bool
depends on SYS_FSL_EC1 || SYS_FSL_EC2
-
-config SYS_MC_RSV_MEM_ALIGN
- hex "Management Complex reserved memory alignment"
- depends on RESV_RAM
- default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A
- help
- Reserved memory needs to be aligned for MC to use. Default value
- is 512MB.
-
config SPL_LDSCRIPT
default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
@@ -623,10 +598,3 @@
help
For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
pins, select it when the pins are assigned to USB.
-
-config TFABOOT
- bool "Support for booting from TFA"
- default n
- help
- Enabling this will make a U-Boot binary that is capable of being
- booted via TFA.
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index a8d3cf9..efecbc0 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -47,8 +47,10 @@
ifneq ($(CONFIG_ARCH_LS1088A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls1088a_serdes.o
+obj-y += icid.o ls1088_ids.o
endif
ifneq ($(CONFIG_ARCH_LS1028A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls1028a_serdes.o
+obj-y += icid.o ls1028_ids.o
endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index edb9c96..a5d0b53 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
+#include <env.h>
#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <linux/errno.h>
@@ -32,7 +33,7 @@
#include <fsl_qbman.h>
#ifdef CONFIG_TFABOOT
-#include <environment.h>
+#include <env_internal.h>
#ifdef CONFIG_CHAIN_OF_TRUST
#include <fsl_validate.h>
#endif
@@ -1153,7 +1154,8 @@
#ifdef CONFIG_FSL_LSCH3
u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
#endif
-#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
+#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
+ defined(CONFIG_ARCH_LS1028A)
u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
u32 svr_dev_id;
#endif
@@ -1172,7 +1174,8 @@
out_le32(cltbenr, 0xf);
#endif
-#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
+#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
+ defined(CONFIG_ARCH_LS1028A)
/*
* In certain Layerscape SoCs, the clock for each core's
* has an enable bit in the PMU Physical Core Time Base Enable
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index fabe0f0..19917b2 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -435,7 +435,7 @@
do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency",
CONFIG_SYS_CLK_FREQ, 1);
-#ifdef CONFIG_PCI_LAYERSCAPE
+#if defined(CONFIG_PCIE_LAYERSCAPE) || defined(CONFIG_PCIE_LAYERSCAPE_GEN4)
ft_pci_setup(blob, bd);
#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index 9ece4b9..df4df9a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -22,10 +22,12 @@
void get_sys_info(struct sys_info *sys_info)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
-#if (defined(CONFIG_FSL_ESDHC) &&\
- defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)) ||\
- defined(CONFIG_SYS_DPAA_FMAN)
-
+/* rcw_tmp is needed to get FMAN clock, or to get cluster group A
+ * mux 2 clock for LS1043A/LS1046A.
+ */
+#if defined(CONFIG_SYS_DPAA_FMAN) || \
+ defined(CONFIG_TARGET_LS1046ARDB) || \
+ defined(CONFIG_TARGET_LS1043ARDB)
u32 rcw_tmp;
#endif
struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
@@ -122,32 +124,32 @@
}
#endif
+#ifdef CONFIG_FSL_ESDHC
#define HWA_CGA_M2_CLK_SEL 0x00000007
#define HWA_CGA_M2_CLK_SHIFT 0
-#ifdef CONFIG_FSL_ESDHC
-#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
+#if defined(CONFIG_TARGET_LS1046ARDB) || defined(CONFIG_TARGET_LS1043ARDB)
rcw_tmp = in_be32(&gur->rcwsr[15]);
switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) {
case 1:
- sys_info->freq_sdhc = freq_c_pll[1];
+ sys_info->freq_cga_m2 = freq_c_pll[1];
break;
+#if defined(CONFIG_TARGET_LS1046ARDB)
case 2:
- sys_info->freq_sdhc = freq_c_pll[1] / 2;
+ sys_info->freq_cga_m2 = freq_c_pll[1] / 2;
break;
+#endif
case 3:
- sys_info->freq_sdhc = freq_c_pll[1] / 3;
+ sys_info->freq_cga_m2 = freq_c_pll[1] / 3;
break;
+#if defined(CONFIG_TARGET_LS1046ARDB)
case 6:
- sys_info->freq_sdhc = freq_c_pll[0] / 2;
+ sys_info->freq_cga_m2 = freq_c_pll[0] / 2;
break;
+#endif
default:
- printf("Error: Unknown ESDHC clock select!\n");
+ printf("Error: Unknown peripheral clock select!\n");
break;
}
-#else
- sys_info->freq_sdhc = (sys_info->freq_systembus /
- CONFIG_SYS_FSL_PCLK_DIV) /
- CONFIG_SYS_FSL_SDHC_CLK_DIV;
#endif
#endif
@@ -183,9 +185,22 @@
gd->mem_clk = sys_info.freq_ddrbus;
#ifdef CONFIG_FSL_ESDHC
- gd->arch.sdhc_clk = sys_info.freq_sdhc;
+#if defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)
+#if defined(CONFIG_TARGET_LS1046ARDB)
+ gd->arch.sdhc_clk = sys_info.freq_cga_m2 / 2;
#endif
-
+#if defined(CONFIG_TARGET_LS1043ARDB)
+ gd->arch.sdhc_clk = sys_info.freq_cga_m2;
+#endif
+#if defined(CONFIG_TARGET_LS1012ARDB)
+ gd->arch.sdhc_clk = sys_info.freq_systembus;
+#endif
+#else
+ gd->arch.sdhc_clk = (sys_info.freq_systembus /
+ CONFIG_SYS_FSL_PCLK_DIV) /
+ CONFIG_SYS_FSL_SDHC_CLK_DIV;
+#endif
+#endif
if (gd->cpu_clk != 0)
return 0;
else
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
index a5540f2..b3e6732 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
@@ -64,6 +64,9 @@
};
uint i, cluster;
+#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LS1088ARDB)
+ uint rcw_tmp;
+#endif
uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
@@ -127,8 +130,39 @@
sys_info->freq_localbus = sys_info->freq_systembus /
CONFIG_SYS_FSL_IFC_CLK_DIV;
#endif
-}
+#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LS1088ARDB)
+#define HWA_CGA_M2_CLK_SEL 0x00380000
+#define HWA_CGA_M2_CLK_SHIFT 19
+ rcw_tmp = in_le32(&gur->rcwsr[5]);
+ switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) {
+ case 1:
+ sys_info->freq_cga_m2 = freq_c_pll[1];
+ break;
+ case 2:
+ sys_info->freq_cga_m2 = freq_c_pll[1] / 2;
+ break;
+ case 3:
+ sys_info->freq_cga_m2 = freq_c_pll[1] / 3;
+ break;
+ case 4:
+ sys_info->freq_cga_m2 = freq_c_pll[1] / 4;
+ break;
+ case 6:
+ sys_info->freq_cga_m2 = freq_c_pll[0] / 2;
+ break;
+ case 7:
+ sys_info->freq_cga_m2 = freq_c_pll[0] / 3;
+ break;
+ default:
+ printf("Error: Unknown peripheral clock select!\n");
+ break;
+ }
+#endif
+#if defined(CONFIG_TARGET_LX2160ARDB) || defined(CONFIG_TARGET_LS2080ARDB)
+ sys_info->freq_cga_m2 = sys_info->freq_systembus;
+#endif
+}
int get_clocks(void)
{
@@ -141,7 +175,16 @@
gd->arch.mem2_clk = sys_info.freq_ddrbus2;
#endif
#if defined(CONFIG_FSL_ESDHC)
+#if defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)
+#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LX2160ARDB)
+ gd->arch.sdhc_clk = sys_info.freq_cga_m2 / 2;
+#endif
+#if defined(CONFIG_TARGET_LS2080ARDB) || defined(CONFIG_TARGET_LS1088ARDB)
+ gd->arch.sdhc_clk = sys_info.freq_cga_m2;
+#endif
+#else
gd->arch.sdhc_clk = gd->bus_clk / CONFIG_SYS_FSL_SDHC_CLK_DIV;
+#endif
#endif /* defined(CONFIG_FSL_ESDHC) */
if (gd->cpu_clk != 0)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
index b1a950e..82c5a8b 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
@@ -17,7 +17,10 @@
int i;
for (i = 0; i < size; i++)
- out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg);
+ if (tbl[i].le)
+ out_le32((u32 *)(tbl[i].reg_addr), tbl[i].reg);
+ else
+ out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg);
}
#ifdef CONFIG_SYS_DPAA_FMAN
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
new file mode 100644
index 0000000..d9d125e
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <asm/arch-fsl-layerscape/immap_lsch3.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
+#include <asm/arch-fsl-layerscape/fsl_portals.h>
+
+struct icid_id_table icid_tbl[] = {
+ SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
+ SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
+ SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID),
+ SET_SDHC_ICID(2, FSL_SDMMC2_STREAM_ID),
+ SET_SATA_ICID(1, "fsl,ls1028a-ahci", FSL_SATA1_STREAM_ID),
+ SET_EDMA_ICID(FSL_EDMA_STREAM_ID),
+ SET_QDMA_ICID("fsl,ls1028a-qdma", FSL_DMA_STREAM_ID),
+ SET_GPU_ICID("fsl,ls1028a-gpu", FSL_GPU_STREAM_ID),
+ SET_DISPLAY_ICID(FSL_DISPLAY_STREAM_ID),
+ SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
+ SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
+ SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
+ SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
+};
+
+int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c
index 5835a3a..313f3f1 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c
@@ -24,7 +24,7 @@
{0xDDDD, {PCIE1, PCIE1, PCIE1, PCIE1} },
{0xE031, {SXGMII1, QXGMII2, NONE, SATA1} },
{0xB991, {SXGMII1, SGMII1, SGMII2, PCIE1} },
- {0xBB31, {SXGMII1, QXGMII2, PCIE1, PCIE1} },
+ {0xBB31, {SXGMII1, QXGMII2, PCIE2, PCIE1} },
{0xCC31, {SXGMII1, QXGMII2, PCIE2, PCIE2} },
{0xBB51, {SXGMII1, QSGMII_B, PCIE2, PCIE1} },
{0xBB38, {SGMII_T1, QXGMII2, PCIE2, PCIE1} },
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
new file mode 100644
index 0000000..49e2755
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <asm/arch-fsl-layerscape/immap_lsch3.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
+#include <asm/arch-fsl-layerscape/fsl_portals.h>
+
+struct icid_id_table icid_tbl[] = {
+ SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID),
+ SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
+ SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
+ SET_SATA_ICID(1, "fsl,ls1088a-ahci", FSL_SATA1_STREAM_ID),
+ SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
+ SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
+ SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
+ SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
+};
+
+int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 7414215..3fd34e3 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
+#include <env.h>
#include <fsl_immap.h>
#include <fsl_ifc.h>
#include <asm/arch/fsl_serdes.h>
@@ -26,7 +27,7 @@
#endif
#include <fsl_immap.h>
#ifdef CONFIG_TFABOOT
-#include <environment.h>
+#include <env_internal.h>
DECLARE_GLOBAL_DATA_PTR;
#endif
@@ -339,6 +340,10 @@
if (fsl_check_boot_mode_secure() == 1)
bypass_smmu();
#endif
+
+#if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A)
+ set_icids();
+#endif
}
/* Get VDD in the unit mV from voltage ID */
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
index 3e53084..8eeeef1 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
@@ -4,6 +4,7 @@
*/
#include <common.h>
+#include <env.h>
#include <spl.h>
#include <asm/io.h>
#include <fsl_ifc.h>
diff --git a/arch/arm/cpu/armv8/linux-kernel-image-header-vars.h b/arch/arm/cpu/armv8/linux-kernel-image-header-vars.h
index fa6e86d..b4220e4 100644
--- a/arch/arm/cpu/armv8/linux-kernel-image-header-vars.h
+++ b/arch/arm/cpu/armv8/linux-kernel-image-header-vars.h
@@ -48,7 +48,7 @@
#define __MAX(a, b) (((a) > (b)) ? (a) : (b))
#define __CODE_DATA_SIZE (__bss_start - _start)
#define __BSS_SIZE (__bss_end - __bss_start)
-#ifdef CONFIG_SYS_INIT_SP_BSS_OFFSET
+#ifdef CONFIG_INIT_SP_RELATIVE
#define __MAX_EXTRA_RAM_USAGE __MAX(__BSS_SIZE, CONFIG_SYS_INIT_SP_BSS_OFFSET)
#else
#define __MAX_EXTRA_RAM_USAGE __BSS_SIZE
diff --git a/arch/arm/cpu/armv8/s32v234/generic.c b/arch/arm/cpu/armv8/s32v234/generic.c
index 273b88e..2c4ea36 100644
--- a/arch/arm/cpu/armv8/s32v234/generic.c
+++ b/arch/arm/cpu/armv8/s32v234/generic.c
@@ -342,7 +342,7 @@
int get_clocks(void)
{
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
gd->arch.sdhc_clk = mxc_get_clock(MXC_USDHC_CLK);
#endif
return 0;
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 20dbc2f..62da168 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -15,6 +15,7 @@
exynos4412-odroid.dtb
dtb-$(CONFIG_TARGET_HIKEY) += hi6220-hikey.dtb
+dtb-$(CONFIG_TARGET_HIKEY960) += hi3660-hikey960.dtb
dtb-$(CONFIG_TARGET_POPLAR) += hi3798cv200-poplar.dtb
@@ -30,7 +31,8 @@
dtb-$(CONFIG_ARCH_DAVINCI) += \
da850-evm.dtb \
- da850-lcdk.dtb
+ da850-lcdk.dtb \
+ da850-lego-ev3.dtb
dtb-$(CONFIG_KIRKWOOD) += \
kirkwood-atl-sbx81lifkw.dtb \
@@ -79,7 +81,6 @@
dtb-$(CONFIG_ROCKCHIP_RK3288) += \
rk3288-evb.dtb \
- rk3288-fennec.dtb \
rk3288-firefly.dtb \
rk3288-miqi.dtb \
rk3288-phycore-rdk.dtb \
@@ -107,6 +108,9 @@
rk3399-ficus.dtb \
rk3399-firefly.dtb \
rk3399-gru-bob.dtb \
+ rk3399-khadas-edge.dtb \
+ rk3399-khadas-edge-captain.dtb \
+ rk3399-khadas-edge-v.dtb \
rk3399-nanopc-t4.dtb \
rk3399-nanopi-m4.dtb \
rk3399-nanopi-neo4.dtb \
@@ -114,6 +118,7 @@
rk3399-puma-ddr1333.dtb \
rk3399-puma-ddr1600.dtb \
rk3399-puma-ddr1866.dtb \
+ rk3399-roc-pc.dtb \
rk3399-rock-pi-4.dtb \
rk3399-rock960.dtb \
rk3399-rockpro64.dtb
@@ -134,7 +139,9 @@
meson-gxl-s905x-khadas-vim.dtb \
meson-gxm-khadas-vim2.dtb \
meson-axg-s400.dtb \
- meson-g12a-u200.dtb
+ meson-g12a-u200.dtb \
+ meson-g12a-sei510.dtb \
+ meson-g12b-odroid-n2.dtb
dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
tegra20-paz00.dtb \
@@ -239,6 +246,7 @@
zynq-zybo-z7.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += \
avnet-ultra96-rev1.dtb \
+ avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dtb \
zynqmp-mini.dtb \
zynqmp-mini-emmc0.dtb \
zynqmp-mini-emmc1.dtb \
@@ -252,10 +260,10 @@
zynqmp-zcu104-revC.dtb \
zynqmp-zcu106-revA.dtb \
zynqmp-zcu111-revA.dtb \
+ zynqmp-zcu1275-revA.dtb \
+ zynqmp-zcu1275-revB.dtb \
zynqmp-zc1232-revA.dtb \
zynqmp-zc1254-revA.dtb \
- zynqmp-zc1275-revA.dtb \
- zynqmp-zc1275-revB.dtb \
zynqmp-zc1751-xm015-dc1.dtb \
zynqmp-zc1751-xm016-dc2.dtb \
zynqmp-zc1751-xm017-dc3.dtb \
@@ -275,6 +283,7 @@
am335x-brppt1-nand.dtb \
am335x-brppt1-spi.dtb \
am335x-brxre1.dtb \
+ am335x-brsmarc1.dtb \
am335x-draco.dtb \
am335x-evm.dtb \
am335x-evmsk.dtb \
@@ -288,11 +297,13 @@
am335x-chiliboard.dtb \
am335x-sl50.dtb \
am335x-base0033.dtb \
- am335x-guardian.dtb
+ am335x-guardian.dtb \
+ am335x-wega-rdk.dtb
dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \
am43x-epos-evm.dtb \
am437x-idk-evm.dtb \
- am4372-generic.dtb
+ am4372-generic.dtb \
+ am437x-cm-t43.dtb
dtb-$(CONFIG_TARGET_AM3517_EVM) += am3517-evm.dtb
dtb-$(CONFIG_TI816X) += dm8168-evm.dtb
dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
@@ -326,7 +337,7 @@
dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \
ls1021a-qds-lpuart.dtb \
ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \
- ls1021a-iot-duart.dtb
+ ls1021a-iot-duart.dtb ls1021a-tsn.dtb
dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-ls2080a-rdb.dtb \
fsl-ls2081a-rdb.dtb \
@@ -480,6 +491,7 @@
sun8i-h2-plus-orangepi-r1.dtb \
sun8i-h2-plus-orangepi-zero.dtb \
sun8i-h3-bananapi-m2-plus.dtb \
+ sun8i-h3-beelink-x2.dtb \
sun8i-h3-libretech-all-h3-cc.dtb \
sun8i-h3-nanopi-m1.dtb \
sun8i-h3-nanopi-m1-plus.dtb \
@@ -548,6 +560,7 @@
imx6q-tbs2910.dtb
dtb-$(CONFIG_MX6QDL) += \
+ imx6dl-dhcom-pdk2.dtb \
imx6dl-icore.dtb \
imx6dl-icore-mipi.dtb \
imx6dl-icore-rqs.dtb \
@@ -556,6 +569,7 @@
imx6dl-sabresd.dtb \
imx6dl-wandboard-revb1.dtb \
imx6q-cm-fx6.dtb \
+ imx6q-dhcom-pdk2.dtb \
imx6q-icore.dtb \
imx6q-icore-mipi.dtb \
imx6q-icore-rqs.dtb \
@@ -596,8 +610,7 @@
dtb-$(CONFIG_ARCH_MX6) += \
imx6-apalis.dtb \
- imx6-colibri.dtb \
- imx6q-dhcom-pdk2.dtb
+ imx6-colibri.dtb
dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
imx7d-sdb-qspi.dtb \
@@ -636,6 +649,7 @@
r8a77965-m3nulcb-u-boot.dtb \
r8a77965-salvator-x-u-boot.dtb \
r8a77970-eagle-u-boot.dtb \
+ r8a77980-condor-u-boot.dtb \
r8a77990-ebisu-u-boot.dtb \
r8a77995-draak-u-boot.dtb
@@ -769,10 +783,13 @@
stm32mp157c-ev1.dtb
dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb k3-am654-r5-base-board.dtb
+dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
+ k3-j721e-r5-common-proc-board.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7623n-bananapi-bpi-r2.dtb \
- mt7629-rfb.dtb
+ mt7629-rfb.dtb \
+ mt8516-pumpkin.dtb
dtb-$(CONFIG_TARGET_GE_BX50V3) += imx6q-bx50v3.dtb
dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb
@@ -790,4 +807,4 @@
dtbs: $(addprefix $(obj)/, $(dtb-y))
@:
-clean-files := *.dtb
+clean-files := *.dtb *_HS
diff --git a/arch/arm/dts/am335x-brsmarc1.dts b/arch/arm/dts/am335x-brsmarc1.dts
new file mode 100644
index 0000000..1a7f9a5
--- /dev/null
+++ b/arch/arm/dts/am335x-brsmarc1.dts
@@ -0,0 +1,416 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 B&R Industrial Automation GmbH
+ * http://www.br-automation.com
+ *
+ */
+/dts-v1/;
+
+#include "am33xx.dtsi"
+#include "dt-bindings/thermal/thermal.h"
+
+/ {
+ model = "BRSMARC1 SoM";
+ compatible = "ti,am33xx";
+
+ fset: factory-settings {
+ bl-version = " ";
+ order-no = " ";
+ cpu-order-no = " ";
+ hw-revision = " ";
+ serial-no = <0>;
+ device-id = <0x0>;
+ parent-id = <0x0>;
+ hw-variant = <0x0>;
+ hw-platform = <0x7>;
+ fram-offset = <0x100>;
+ fram-size = <0x1F00>;
+ cache-disable = <0x0>;
+ cpu-clock = <0x0>;
+ };
+
+ chosen {
+ bootargs = "console=ttyO0,115200 earlyprintk";
+ stdout-path = &uart0;
+ };
+
+ aliases {
+ fset = &fset;
+ mmc = &mmc2;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ touch0 = &burtouch0;
+ screen0 = &lcdscreen0;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>; /* 256 MB */
+ };
+
+ vmmcsd_fixed: fixedregulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vmmcsd_fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ lcdscreen0: lcdscreen@0 {
+ /*backlight = <&tps_bl>; */
+ compatible = "ti,tilcdc,panel";
+ status = "okay";
+
+ panel-info {
+ ac-bias = <255>;
+ ac-bias-intrpt = <0>;
+ dma-burst-sz = <16>;
+ bpp = <32>;
+ fdd = <0x80>;
+ sync-edge = <0>;
+ sync-ctrl = <1>;
+ raster-order = <0>;
+ fifo-th = <0>;
+ rotation = <0>;
+ pupdelay = <0>;
+ pondelay = <0>;
+ pwrpin = <0x000000B1>;
+ brightdrv = <0>;
+ brightfdim = <100>;
+ brightdef = <50>;
+ };
+
+ display-timings {
+ default {
+ clock-frequency = <0>;
+ hactive = <0>;
+ vactive = <0>;
+ hfront-porch = <0>;
+ hback-porch = <0>;
+ hsync-len = <0>;
+ vfront-porch = <0>;
+ vback-porch = <0>;
+ vsync-len = <0>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pupdelay = <10>;
+ pondelay = <10>;
+ };
+ };
+ };
+
+ board_thermal: board-thermal {
+ polling-delay-passive = <1000>; /* milliseconds */
+ polling-delay = <2500>; /* milliseconds */
+
+ thermal-sensors = <&cputemp>;
+
+ trips {
+ crit_trip: crit-trip {
+ temperature = <95000>; /* millicelsius */
+ hysteresis = <5000>; /* millicelsius */
+ type = "critical";
+ };
+ };
+ cooling-maps {
+ map0 {
+ trip = <&crit_trip>;
+ cooling-device =
+ <&resetc THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+};
+
+&uart0 { /* console uart */
+ u-boot,dm-spl;
+ status = "okay";
+};
+
+&uart2 { /* X2X - P2P */
+ status = "okay";
+};
+
+&uart3 { /* RS485 */
+ status = "okay";
+};
+
+&uart4 { /* RS232 */
+ status = "okay";
+};
+
+&i2c0 {
+ u-boot,dm-spl;
+ status = "okay";
+ clock-frequency = <100000>;
+
+ tps: tps@24 { /* PMIC controller */
+ u-boot,dm-spl;
+ reg = <0x24>;
+ compatible = "ti,tps65217";
+ };
+
+ cputemp: temperature-sensor@48 { /* cpu temperature */
+ #thermal-sensor-cells = <0>;
+ compatible = "nxp,pct2075";
+ reg = <0x48>;
+ };
+
+ basetemp: temperature-sensor@49 { /* baseboard temperature */
+ #thermal-sensor-cells = <0>;
+ compatible = "nxp,pct2075";
+ reg = <0x49>;
+ };
+ extrtc: rtc@51 { /* realtime clock */
+ compatible = "epson,rx8571";
+ reg = <0x51>;
+ };
+
+ resetc: reset-controller@60 {
+ compatible = "bur,rststm";
+ reg = <0x60>;
+
+ cooling-min-state = <0>;
+ cooling-max-state = <1>; /* reset gets fired */
+ #cooling-cells = <2>; /* min followed by max */
+ };
+};
+
+&i2c1 {
+ u-boot,dm-spl;
+ status = "okay";
+};
+
+&spi0 {
+ u-boot,dm-spl;
+ status = "okay";
+
+ cs-gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>,
+ <&gpio0 6 GPIO_ACTIVE_HIGH>,
+ <0>,
+ <0>;
+
+ spi-max-frequency = <24000000>;
+
+ spi_flash: spiflash@0 {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+ compatible = "spidev", "spi-flash";
+ spi-max-frequency = <24000000>;
+ reg = <0>;
+ };
+};
+
+&spi1 {
+ u-boot,dm-spl;
+ status = "okay";
+ cs-gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>,
+ <&gpio0 19 GPIO_ACTIVE_HIGH>,
+ <0>,
+ <0>;
+
+ spi-max-frequency = <24000000>;
+};
+
+&edma {
+ status = "okay";
+};
+
+&cppi41dma {
+ status = "okay";
+};
+
+&usb {
+ status = "okay";
+};
+
+&usb_ctrl_mod {
+ status = "okay";
+};
+
+&usb0_phy {
+ status = "okay";
+};
+
+&usb1_phy {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb1 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&davinci_mdio {
+ status = "okay";
+};
+
+&mac {
+ status = "okay";
+};
+
+&phy_sel {
+ rmii-clock-ext;
+};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <1>;
+ phy-mode = "rmii";
+ ti,ledcr = <0x0480>;
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <3>;
+ phy-mode = "rmii";
+ ti,ledcr = <0x0480>;
+};
+
+&mmc1 {
+ vmmc-supply = <&vmmcsd_fixed>;
+ bus-width = <0x4>;
+ ti,non-removable;
+ ti,needs-special-hs-handling;
+ ti,vcc-aux-disable-is-sleep;
+ status = "okay";
+};
+
+&mmc2 {
+ vmmc-supply = <&vmmcsd_fixed>;
+ bus-width = <0x8>;
+ ti,non-removable;
+ ti,needs-special-hs-handling;
+ ti,vcc-aux-disable-is-sleep;
+ status = "okay";
+};
+
+&lcdc {
+ status = "okay";
+ ti,no-reset-on-init;
+ ti,no-idle-on-init;
+};
+
+&elm {
+ status = "okay";
+};
+
+&sham {
+ status = "okay";
+};
+
+&aes {
+ status = "okay";
+};
+
+&gpio0 {
+ u-boot,dm-spl;
+ ti,no-reset-on-init;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+ ti,no-reset-on-init;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+ ti,no-reset-on-init;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+ ti,no-reset-on-init;
+};
+
+&timer1 { /* today unused */
+ status = "okay";
+ ti,no-reset-on-init;
+ ti,no-idle-on-init;
+};
+
+&timer2 { /* used for vxworks primary timer device */
+ status = "okay";
+ ti,no-reset-on-init;
+ ti,no-idle-on-init;
+};
+
+&timer3 { /* used sysdelay and hal tsc counter*/
+ status = "okay";
+ ti,no-reset-on-init;
+ ti,no-idle-on-init;
+};
+
+&timer4 { /* used for PWM beeper */
+ status = "okay";
+ ti,no-reset-on-init;
+ ti,no-idle-on-init;
+};
+
+&timer5 { /* used for PWM backlight */
+ status = "okay";
+ ti,no-reset-on-init;
+ ti,no-idle-on-init;
+};
+
+&timer6 { /* used for cpsw end device */
+ status = "okay";
+ ti,no-reset-on-init;
+ ti,no-idle-on-init;
+};
+
+&timer7 { /* used for cpsw end device */
+ status = "okay";
+ ti,no-reset-on-init;
+ ti,no-idle-on-init;
+};
+
+&wdt2 {
+ status = "okay";
+ ti,no-reset-on-init;
+ ti,no-idle-on-init;
+};
+
+&epwmss0 {
+ status = "okay";
+};
+
+&tscadc {
+ status = "okay";
+
+ tsc {
+ burtouch0: burtouch@0 {
+ status = "okay";
+ compatible = "bur,DdVxSfTouchXXX";
+ bur,hwtree = "IF7";
+ bur,KX0 = <0x0>;
+ bur,KX1 = <0x0>;
+ bur,KX2 = <0x0>;
+ bur,KY0 = <0x0>;
+ bur,KY1 = <0x0>;
+ bur,KY2 = <0x0>;
+ };
+ };
+};
+
+&dcan0 {
+ status = "okay";
+};
+
+&dcan1 {
+ status = "okay";
+};
+
+&sham {
+ status = "disabled";
+};
+
+&aes {
+ status = "disabled";
+};
+
+&rng {
+ status = "disabled";
+};
diff --git a/arch/arm/dts/am335x-phycore-som.dtsi b/arch/arm/dts/am335x-phycore-som.dtsi
new file mode 100644
index 0000000..8d7c19e
--- /dev/null
+++ b/arch/arm/dts/am335x-phycore-som.dtsi
@@ -0,0 +1,322 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2015 Phytec Messtechnik GmbH
+ * Author: Teresa Remmet <t.remmet@phytec.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "am33xx.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ model = "Phytec AM335x phyCORE";
+ compatible = "phytec,am335x-phycore-som", "ti,am33xx";
+
+ aliases {
+ rtc0 = &i2c_rtc;
+ rtc1 = &rtc;
+ };
+
+ cpus {
+ cpu@0 {
+ cpu0-supply = <&vdd1_reg>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>; /* 256 MB */
+ };
+
+ regulators {
+ compatible = "simple-bus";
+
+ vcc5v: fixedregulator0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+};
+
+/* Crypto Module */
+&aes {
+ status = "okay";
+};
+
+&sham {
+ status = "okay";
+};
+
+/* Ethernet */
+&am33xx_pinmux {
+ ethernet0_pins: pinmux_ethernet0 {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */
+ AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */
+ AM33XX_IOPAD(0x914, PIN_OUTPUT | MUX_MODE1) /* mii1_txen.rmii1_txen */
+ AM33XX_IOPAD(0x924, PIN_OUTPUT | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
+ AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
+ AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
+ AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
+ AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */
+ >;
+ };
+
+ mdio_pins: pinmux_mdio {
+ pinctrl-single,pins = <
+ /* MDIO */
+ AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
+ AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
+ >;
+ };
+};
+
+&cpsw_emac0 {
+ phy-handle = <&phy0>;
+ phy-mode = "rmii";
+ dual_emac_res_vlan = <1>;
+};
+
+&davinci_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio_pins>;
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+&mac {
+ slaves = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <ðernet0_pins>;
+ status = "okay";
+};
+
+/* I2C Busses */
+&am33xx_pinmux {
+ i2c0_pins: pinmux_i2c0 {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* i2c0_sda.i2c0_sda */
+ AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* i2c0_scl.i2c0_scl */
+ >;
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ tps: pmic@2d {
+ reg = <0x2d>;
+ };
+
+ i2c_tmp102: temp@4b {
+ compatible = "ti,tmp102";
+ reg = <0x4b>;
+ status = "disabled";
+ };
+
+ i2c_eeprom: eeprom@52 {
+ compatible = "atmel,24c32";
+ pagesize = <32>;
+ reg = <0x52>;
+ status = "disabled";
+ };
+
+ i2c_rtc: rtc@68 {
+ compatible = "microcrystal,rv4162";
+ reg = <0x68>;
+ status = "disabled";
+ };
+};
+
+/* NAND memory */
+&am33xx_pinmux {
+ nandflash_pins: pinmux_nandflash {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
+ AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
+ AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
+ AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
+ AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
+ AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
+ AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
+ AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
+ AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
+ AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
+ AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
+ AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
+ AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
+ AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
+ >;
+ };
+};
+
+&elm {
+ status = "okay";
+};
+
+&gpmc {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&nandflash_pins>;
+ ranges = <0 0 0x08000000 0x1000000>; /* CS0: NAND */
+ nandflash: nand@0,0 {
+ compatible = "ti,omap2-nand";
+ reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+ interrupt-parent = <&gpmc>;
+ interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+ <1 IRQ_TYPE_NONE>; /* termcount */
+ rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
+ nand-bus-width = <8>;
+ ti,nand-ecc-opt = "bch8";
+ gpmc,device-nand = "true";
+ gpmc,device-width = <1>;
+ gpmc,sync-clk-ps = <0>;
+ gpmc,cs-on-ns = <0>;
+ gpmc,cs-rd-off-ns = <30>;
+ gpmc,cs-wr-off-ns = <30>;
+ gpmc,adv-on-ns = <0>;
+ gpmc,adv-rd-off-ns = <30>;
+ gpmc,adv-wr-off-ns = <30>;
+ gpmc,we-on-ns = <0>;
+ gpmc,we-off-ns = <20>;
+ gpmc,oe-on-ns = <10>;
+ gpmc,oe-off-ns = <30>;
+ gpmc,access-ns = <30>;
+ gpmc,rd-cycle-ns = <30>;
+ gpmc,wr-cycle-ns = <30>;
+ gpmc,bus-turnaround-ns = <0>;
+ gpmc,cycle2cycle-delay-ns = <50>;
+ gpmc,cycle2cycle-diffcsen;
+ gpmc,clk-activation-ns = <0>;
+ gpmc,wr-access-ns = <30>;
+ gpmc,wr-data-mux-bus-ns = <0>;
+
+ ti,elm-id = <&elm>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
+
+/* Power */
+#include "tps65910.dtsi"
+
+&tps {
+ vcc1-supply = <&vcc5v>;
+ vcc2-supply = <&vcc5v>;
+ vcc3-supply = <&vcc5v>;
+ vcc4-supply = <&vcc5v>;
+ vcc5-supply = <&vcc5v>;
+ vcc6-supply = <&vcc5v>;
+ vcc7-supply = <&vcc5v>;
+ vccio-supply = <&vcc5v>;
+
+ regulators {
+ vrtc_reg: regulator@0 {
+ regulator-always-on;
+ };
+
+ vio_reg: regulator@1 {
+ regulator-always-on;
+ };
+
+ vdd1_reg: regulator@2 {
+ /* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */
+ regulator-name = "vdd_mpu";
+ regulator-min-microvolt = <912500>;
+ regulator-max-microvolt = <1378000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd2_reg: regulator@3 {
+ /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+ regulator-name = "vdd_core";
+ regulator-min-microvolt = <912500>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd3_reg: regulator@4 {
+ regulator-always-on;
+ };
+
+ vdig1_reg: regulator@5 {
+ regulator-name = "vdig1_1p8v";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vdig2_reg: regulator@6 {
+ regulator-always-on;
+ };
+
+ vpll_reg: regulator@7 {
+ regulator-always-on;
+ };
+
+ vdac_reg: regulator@8 {
+ regulator-always-on;
+ };
+
+ vaux1_reg: regulator@9 {
+ regulator-always-on;
+ };
+
+ vaux2_reg: regulator@10 {
+ regulator-always-on;
+ };
+
+ vaux33_reg: regulator@11 {
+ regulator-always-on;
+ };
+
+ vmmc_reg: regulator@12 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+};
+
+/* SPI Busses */
+&am33xx_pinmux {
+ spi0_pins: pinmux_spi0 {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x950, PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_clk.spi0_clk */
+ AM33XX_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_d0.spi0_d0 */
+ AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */
+ AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
+ >;
+ };
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins>;
+ status = "okay";
+
+ serial_flash: m25p80@0 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <48000000>;
+ reg = <0x0>;
+ m25p,fast-read;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
diff --git a/arch/arm/dts/am335x-wega-rdk-u-boot.dtsi b/arch/arm/dts/am335x-wega-rdk-u-boot.dtsi
new file mode 100644
index 0000000..634f1b0
--- /dev/null
+++ b/arch/arm/dts/am335x-wega-rdk-u-boot.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 DENX Software Engineering GmbH
+ */
+
+/ {
+ chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ bootargs = "console=ttyO0,115200 earlyprintk";
+ stdout-path = &uart0;
+ };
+
+ ocp {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&i2c0 {
+ u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+};
+
+&mmc1 {
+ u-boot,dm-pre-reloc;
+ cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+};
diff --git a/arch/arm/dts/am335x-wega-rdk.dts b/arch/arm/dts/am335x-wega-rdk.dts
new file mode 100644
index 0000000..fe50f30
--- /dev/null
+++ b/arch/arm/dts/am335x-wega-rdk.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2015 Phytec Messtechnik GmbH
+ * Author: Teresa Remmet <t.remmet@phytec.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "am335x-phycore-som.dtsi"
+#include "am335x-wega.dtsi"
+
+/* SoM */
+&i2c_eeprom {
+ status = "okay";
+};
+
+&i2c_rtc {
+ status = "okay";
+};
diff --git a/arch/arm/dts/am335x-wega.dtsi b/arch/arm/dts/am335x-wega.dtsi
new file mode 100644
index 0000000..f3e045d
--- /dev/null
+++ b/arch/arm/dts/am335x-wega.dtsi
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2015 Phytec Messtechnik GmbH
+ * Author: Teresa Remmet <t.remmet@phytec.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/ {
+ model = "Phytec AM335x phyBOARD-WEGA";
+ compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx";
+
+ sound: sound_iface {
+ compatible = "ti,da830-evm-audio";
+ };
+
+ regulators {
+ compatible = "simple-bus";
+
+ vcc3v3: fixedregulator1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ };
+ };
+};
+
+/* Audio */
+&am33xx_pinmux {
+ mcasp0_pins: pinmux_mcasp0 {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x9AC, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahclkx.mcasp0_ahclkx */
+ AM33XX_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */
+ AM33XX_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */
+ AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr0.mcasp0_axr0 */
+ AM33XX_IOPAD(0x9A8, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr1.mcasp0_axr1 */
+ >;
+ };
+};
+
+&i2c0 {
+ tlv320aic3007: tlv320aic3007@18 {
+ compatible = "ti,tlv320aic3007";
+ reg = <0x18>;
+ AVDD-supply = <&vcc3v3>;
+ IOVDD-supply = <&vcc3v3>;
+ DRVDD-supply = <&vcc3v3>;
+ DVDD-supply = <&vdig1_reg>;
+ status = "okay";
+ };
+};
+
+&mcasp0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcasp0_pins>;
+ op-mode = <0>; /* DAVINCI_MCASP_IIS_MODE */
+ tdm-slots = <2>;
+ serial-dir = <
+ 2 1 0 0 /* # 0: INACTIVE, 1: TX, 2: RX */
+ >;
+ tx-num-evt = <16>;
+ rt-num-evt = <16>;
+ status = "okay";
+};
+
+&sound {
+ ti,model = "AM335x-Wega";
+ ti,audio-codec = <&tlv320aic3007>;
+ ti,mcasp-controller = <&mcasp0>;
+ ti,audio-routing =
+ "Line Out", "LLOUT",
+ "Line Out", "RLOUT",
+ "LINE1L", "Line In",
+ "LINE1R", "Line In";
+ clocks = <&mcasp0_fck>;
+ clock-names = "mclk";
+ status = "okay";
+};
+
+/* CAN Busses */
+&am33xx_pinmux {
+ dcan1_pins: pinmux_dcan1 {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x968, PIN_OUTPUT_PULLUP | MUX_MODE2) /* uart0_ctsn.d_can1_tx */
+ AM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE2) /* uart0_rtsn.d_can1_rx */
+ >;
+ };
+};
+
+&dcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&dcan1_pins>;
+ status = "okay";
+};
+
+/* Ethernet */
+&am33xx_pinmux {
+ ethernet1_pins: pinmux_ethernet1 {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE1) /* gpmc_a0.mii2_txen */
+ AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a1.mii2_rxdv */
+ AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE1) /* gpmc_a2.mii2_txd3 */
+ AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE1) /* gpmc_a3.mii2_txd2 */
+ AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE1) /* gpmc_a4.mii2_txd1 */
+ AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE1) /* gpmc_a5.mii2_txd0 */
+ AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a6.mii2_txclk */
+ AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a7.mii2_rxclk */
+ AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a8.mii2_rxd3 */
+ AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a9.mii2_rxd2 */
+ AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a10.mii2_rxd1 */
+ AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a11.mii2_rxd0 */
+ AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_wpn.mii2_rxerr */
+ AM33XX_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_ben1.mii2_col */
+ >;
+ };
+};
+
+&cpsw_emac1 {
+ phy-handle = <&phy1>;
+ phy-mode = "mii";
+ dual_emac_res_vlan = <2>;
+};
+
+&davinci_mdio {
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&mac {
+ slaves = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <ðernet0_pins ðernet1_pins>;
+ dual_emac = <1>;
+};
+
+/* MMC */
+&am33xx_pinmux {
+ mmc1_pins: pinmux_mmc1 {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
+ AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
+ AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
+ AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
+ AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
+ AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
+ AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE7) /* spi0_cs1.mmc0_sdcd */
+ >;
+ };
+};
+
+&mmc1 {
+ vmmc-supply = <&vcc3v3>;
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+/* Power */
+&vdig1_reg {
+ regulator-boot-on;
+ regulator-always-on;
+};
+
+/* UARTs */
+&am33xx_pinmux {
+ uart0_pins: pinmux_uart0 {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
+ AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
+ >;
+ };
+
+ uart1_pins: pinmux_uart1_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
+ AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
+ AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */
+ AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */
+ >;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ status = "okay";
+};
+
+/* USB */
+&cppi41dma {
+ status = "okay";
+};
+
+&usb_ctrl_mod {
+ status = "okay";
+};
+
+&usb {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb0_phy {
+ status = "okay";
+};
+
+&usb1 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb1_phy {
+ status = "okay";
+};
diff --git a/arch/arm/dts/am3517-evm-u-boot.dtsi b/arch/arm/dts/am3517-evm-u-boot.dtsi
index 59df819..d5a4ce9 100644
--- a/arch/arm/dts/am3517-evm-u-boot.dtsi
+++ b/arch/arm/dts/am3517-evm-u-boot.dtsi
@@ -4,20 +4,40 @@
* Logic PD - http://www.logicpd.com
*/
+#include "omap3-u-boot.dtsi"
+
/ {
- chosen {
- stdout-path = &uart3;
+ aliases {
+ /delete-property/ serial0;
+ /delete-property/ serial1;
+ };
+
+ ocp@68000000 {
+ /delete-node/ bandgap@48002524;
};
};
-&uart1 {
- reg-shift = <2>;
+&gpio1 {
+ /delete-property/ u-boot,dm-spl;
};
-&uart2 {
- reg-shift = <2>;
+&gpio2 {
+ /delete-property/ u-boot,dm-spl;
};
-&uart3 {
- reg-shift = <2>;
+&gpio3 {
+ /delete-property/ u-boot,dm-spl;
};
+
+&gpio5 {
+ /delete-property/ u-boot,dm-spl;
+};
+
+&gpio6 {
+ /delete-property/ u-boot,dm-spl;
+};
+
+/delete-node/ &uart1;
+/delete-node/ &uart2;
+/delete-node/ &mmc2;
+/delete-node/ &mmc3;
diff --git a/arch/arm/dts/am437x-cm-t43.dts b/arch/arm/dts/am437x-cm-t43.dts
new file mode 100644
index 0000000..063113a
--- /dev/null
+++ b/arch/arm/dts/am437x-cm-t43.dts
@@ -0,0 +1,420 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2015 CompuLab, Ltd. - http://www.compulab.co.il/
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/pinctrl/am43xx.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "am4372.dtsi"
+
+/ {
+ model = "CompuLab CM-T43";
+ compatible = "compulab,am437x-cm-t43", "ti,am4372", "ti,am43";
+
+ leds {
+ compatible = "gpio-leds";
+
+ ledb {
+ label = "cm-t43:green";
+ gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ vmmc_3v3: fixedregulator-v3_3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vmmc_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ enable-active-high;
+ };
+};
+
+&am43xx_pinmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cm_t43_led_pins>;
+
+ cm_t43_led_pins: cm_t43_led_pins {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0xa78, MUX_MODE7)
+ >;
+ };
+
+ i2c0_pins: i2c0_pins {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
+ AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
+ >;
+ };
+
+ emmc_pins: emmc_pins {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad8.mmc1_dat0 */
+ AM4372_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad9.mmc1_dat1 */
+ AM4372_IOPAD(0x828, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad10.mmc1_dat2 */
+ AM4372_IOPAD(0x82c, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad11.mmc1_dat3 */
+ AM4372_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad12.mmc1_dat4 */
+ AM4372_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad13.mmc1_dat5 */
+ AM4372_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad14.mmc1_dat6 */
+ AM4372_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad15.mmc1_dat7 */
+ AM4372_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
+ AM4372_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
+ >;
+ };
+
+ spi0_pins: pinmux_spi0_pins {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x950, PIN_INPUT | MUX_MODE0) /* spi0_sclk.spi0_sclk */
+ AM4372_IOPAD(0x954, PIN_INPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */
+ AM4372_IOPAD(0x958, PIN_OUTPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */
+ AM4372_IOPAD(0x95C, PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
+ >;
+ };
+
+ nand_flash_x8: nand_flash_x8 {
+ pinctrl-single,pins = <
+ AM4372_IOPAD(0x800, PIN_INPUT | PULL_DISABLE | MUX_MODE0)
+ AM4372_IOPAD(0x804, PIN_INPUT | PULL_DISABLE | MUX_MODE0)
+ AM4372_IOPAD(0x808, PIN_INPUT | PULL_DISABLE | MUX_MODE0)
+ AM4372_IOPAD(0x80c, PIN_INPUT | PULL_DISABLE | MUX_MODE0)
+ AM4372_IOPAD(0x810, PIN_INPUT | PULL_DISABLE | MUX_MODE0)
+ AM4372_IOPAD(0x814, PIN_INPUT | PULL_DISABLE | MUX_MODE0)
+ AM4372_IOPAD(0x818, PIN_INPUT | PULL_DISABLE | MUX_MODE0)
+ AM4372_IOPAD(0x81c, PIN_INPUT | PULL_DISABLE | MUX_MODE0)
+ AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0)
+ AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE0)
+ AM4372_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE0)
+ AM4372_IOPAD(0x898, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
+ AM4372_IOPAD(0x894, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
+ AM4372_IOPAD(0x890, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
+ AM4372_IOPAD(0x89c, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
+ >;
+ };
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins = <
+ /* Slave 1 */
+ AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */
+ AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */
+ AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */
+ AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */
+ AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */
+ AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */
+ AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
+ AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
+ AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */
+ AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */
+ AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */
+ AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */
+ AM4372_IOPAD(0xa74, MUX_MODE3)
+ /* Slave 2 */
+ AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.txen */
+ AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rxctl */
+ AM4372_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.txd3 */
+ AM4372_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.txd2 */
+ AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.txd1 */
+ AM4372_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.txd0 */
+ AM4372_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.tclk */
+ AM4372_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rclk */
+ AM4372_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rxd3 */
+ AM4372_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rxd2 */
+ AM4372_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rxd1 */
+ AM4372_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rxd0 */
+ AM4372_IOPAD(0xa38, MUX_MODE7)
+ >;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins = <
+ /* MDIO */
+ AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
+ AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
+ >;
+ };
+};
+
+&gpmc {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&nand_flash_x8>;
+ ranges = <0 0 0x08000000 0x1000000>;
+ nand@0,0 {
+ compatible = "ti,omap2-nand";
+ reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+ interrupt-parent = <&gpmc>;
+ interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+ <1 IRQ_TYPE_NONE>; /* termcount */
+ ti,nand-ecc-opt = "bch8";
+ ti,elm-id = <&elm>;
+
+ nand-bus-width = <8>;
+ gpmc,device-width = <1>;
+ gpmc,sync-clk-ps = <0>;
+ gpmc,cs-on-ns = <0>;
+ gpmc,cs-rd-off-ns = <44>;
+ gpmc,cs-wr-off-ns = <44>;
+ gpmc,adv-on-ns = <6>;
+ gpmc,adv-rd-off-ns = <34>;
+ gpmc,adv-wr-off-ns = <44>;
+ gpmc,we-on-ns = <0>;
+ gpmc,we-off-ns = <40>;
+ gpmc,oe-on-ns = <0>;
+ gpmc,oe-off-ns = <54>;
+ gpmc,access-ns = <64>;
+ gpmc,rd-cycle-ns = <82>;
+ gpmc,wr-cycle-ns = <82>;
+ gpmc,bus-turnaround-ns = <0>;
+ gpmc,cycle2cycle-delay-ns = <0>;
+ gpmc,clk-activation-ns = <0>;
+ gpmc,wr-access-ns = <40>;
+ gpmc,wr-data-mux-bus-ns = <0>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ /* MTD partition table */
+ partition@0 {
+ label = "kernel";
+ reg = <0x0 0x00980000>;
+ };
+ partition@980000 {
+ label = "dtb";
+ reg = <0x00980000 0x00080000>;
+ };
+ partition@a00000 {
+ label = "rootfs";
+ reg = <0x00a00000 0x0>;
+ };
+ };
+};
+
+&i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ clock-frequency = <100000>;
+
+ tps65218: tps65218@24 {
+ compatible = "ti,tps65218";
+ reg = <0x24>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* NMIn */
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ dcdc1: regulator-dcdc1 {
+ regulator-name = "vdd_core";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <1144000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ dcdc2: regulator-dcdc2 {
+ regulator-name = "vdd_mpu";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <1378000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ dcdc3: regulator-dcdc3 {
+ regulator-name = "vdcdc3";
+ regulator-suspend-enable;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ dcdc5: regulator-dcdc5 {
+ regulator-name = "v1_0bat";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ dcdc6: regulator-dcdc6 {
+ regulator-name = "v1_8bat";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1: regulator-ldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+
+ eeprom_module: at24@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gpio2 {
+ status = "okay";
+};
+
+&gpio3 {
+ status = "okay";
+};
+
+&gpio4 {
+ status = "okay";
+};
+
+&gpio5 {
+ status = "okay";
+};
+
+&mmc2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_pins>;
+ vmmc-supply = <&vmmc_3v3>;
+ bus-width = <8>;
+ ti,non-removable;
+};
+
+&spi0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins>;
+ dmas = <&edma 16 0
+ &edma 17 0>;
+ dma-names = "tx0", "rx0";
+
+ flash: w25q64cvzpig@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ partition@0 {
+ label = "uboot";
+ reg = <0x0 0xc0000>;
+ };
+
+ partition@c0000 {
+ label = "uboot environment";
+ reg = <0xc0000 0x40000>;
+ };
+
+ partition@100000 {
+ label = "reserved";
+ reg = <0x100000 0x100000>;
+ };
+ };
+};
+
+&mac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpsw_default>;
+ dual_emac = <1>;
+ status = "okay";
+};
+
+&davinci_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&davinci_mdio_default>;
+ status = "okay";
+
+ ethphy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ ethphy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&cpsw_emac0 {
+ phy-handle = <ðphy0>;
+ phy-mode = "rgmii-txid";
+ dual_emac_res_vlan = <1>;
+};
+
+&cpsw_emac1 {
+ phy-handle = <ðphy1>;
+ phy-mode = "rgmii-txid";
+ dual_emac_res_vlan = <2>;
+};
+
+&dwc3_1 {
+ status = "okay";
+};
+
+&usb2_phy1 {
+ status = "okay";
+};
+
+&usb1 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&dwc3_2 {
+ status = "okay";
+};
+
+&usb2_phy2 {
+ status = "okay";
+};
+
+&usb2 {
+ dr_mode = "host";
+ status = "okay";
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "peripheral", "host", "otg";
+};
+
+&elm {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&tscadc {
+ status = "okay";
+ tsc {
+ ti,wires = <4>;
+ ti,x-plate-resistance = <200>;
+ ti,coordiante-readouts = <5>;
+ ti,wire-config = <0x00 0x11 0x22 0x33>;
+ };
+
+ adc {
+ ti,adc-channels = <4 5 6 7>;
+ };
+};
+
+&cpu {
+ cpu0-supply = <&dcdc2>;
+ operating-points = <1000000 1330000>,
+ <800000 1260000>,
+ <720000 1200000>,
+ <600000 1100000>,
+ <300000 950000>;
+};
diff --git a/arch/arm/dts/am571x-idk.dts b/arch/arm/dts/am571x-idk.dts
index debf946..798fbfe 100644
--- a/arch/arm/dts/am571x-idk.dts
+++ b/arch/arm/dts/am571x-idk.dts
@@ -11,6 +11,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "am57xx-idk-common.dtsi"
+#include "dra7-mmc-iodelay.dtsi"
#include "dra72x-mmc-iodelay.dtsi"
/ {
@@ -101,14 +102,9 @@
};
&mmc1 {
- pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
- pinctrl-0 = <&mmc1_pins_default>;
+ pinctrl-names = "default", "hs";
+ pinctrl-0 = <&mmc1_pins_default_no_clk_pu>;
pinctrl-1 = <&mmc1_pins_hs>;
- pinctrl-2 = <&mmc1_pins_sdr12>;
- pinctrl-3 = <&mmc1_pins_sdr25>;
- pinctrl-4 = <&mmc1_pins_sdr50>;
- pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>;
- pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
};
&mmc2 {
diff --git a/arch/arm/dts/am572x-idk.dts b/arch/arm/dts/am572x-idk.dts
index 9212931..42e88c1 100644
--- a/arch/arm/dts/am572x-idk.dts
+++ b/arch/arm/dts/am572x-idk.dts
@@ -11,6 +11,7 @@
#include "dra74x.dtsi"
#include "am572x-idk-common.dtsi"
#include "am57xx-idk-common.dtsi"
+#include "dra7-mmc-iodelay.dtsi"
#include "dra74x-mmc-iodelay.dtsi"
/ {
@@ -20,14 +21,9 @@
};
&mmc1 {
- pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
- pinctrl-0 = <&mmc1_pins_default>;
+ pinctrl-names = "default", "hs";
+ pinctrl-0 = <&mmc1_pins_default_no_clk_pu>;
pinctrl-1 = <&mmc1_pins_hs>;
- pinctrl-2 = <&mmc1_pins_sdr12>;
- pinctrl-3 = <&mmc1_pins_sdr25>;
- pinctrl-4 = <&mmc1_pins_sdr50>;
- pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>;
- pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
};
&mmc2 {
diff --git a/arch/arm/dts/am574x-idk.dts b/arch/arm/dts/am574x-idk.dts
index 41e12a3..0de7361 100644
--- a/arch/arm/dts/am574x-idk.dts
+++ b/arch/arm/dts/am574x-idk.dts
@@ -7,6 +7,8 @@
/dts-v1/;
#include "dra76x.dtsi"
+#include "dra7-mmc-iodelay.dtsi"
+#include "dra76x-mmc-iodelay.dtsi"
#include "am572x-idk-common.dtsi"
/ {
@@ -20,3 +22,16 @@
spi-max-frequency = <96000000>;
};
};
+
+&mmc1 {
+ pinctrl-names = "default", "hs";
+ pinctrl-0 = <&mmc1_pins_default_no_clk_pu>;
+ pinctrl-1 = <&mmc1_pins_hs>;
+};
+
+&mmc2 {
+ pinctrl-names = "default", "hs", "ddr_1_8v";
+ pinctrl-0 = <&mmc2_pins_default>;
+ pinctrl-1 = <&mmc2_pins_default>;
+ pinctrl-2 = <&mmc2_pins_default>;
+};
diff --git a/arch/arm/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/dts/am57xx-beagle-x15-common.dtsi
index 49aeecd..d6b94d5 100644
--- a/arch/arm/dts/am57xx-beagle-x15-common.dtsi
+++ b/arch/arm/dts/am57xx-beagle-x15-common.dtsi
@@ -433,6 +433,7 @@
bus-width = <4>;
cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
+ no-1-8-v;
};
&mmc2 {
diff --git a/arch/arm/dts/am57xx-beagle-x15-revb1.dts b/arch/arm/dts/am57xx-beagle-x15-revb1.dts
index 5a77b33..34c6996 100644
--- a/arch/arm/dts/am57xx-beagle-x15-revb1.dts
+++ b/arch/arm/dts/am57xx-beagle-x15-revb1.dts
@@ -19,14 +19,9 @@
};
&mmc1 {
- pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
+ pinctrl-names = "default", "hs";
pinctrl-0 = <&mmc1_pins_default>;
pinctrl-1 = <&mmc1_pins_hs>;
- pinctrl-2 = <&mmc1_pins_sdr12>;
- pinctrl-3 = <&mmc1_pins_sdr25>;
- pinctrl-4 = <&mmc1_pins_sdr50>;
- pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev11_conf>;
- pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev11_conf>;
vmmc-supply = <&vdd_3v3>;
vqmmc-supply = <&ldo1_reg>;
};
diff --git a/arch/arm/dts/am57xx-beagle-x15-revc.dts b/arch/arm/dts/am57xx-beagle-x15-revc.dts
index 17c41da..ccd9916 100644
--- a/arch/arm/dts/am57xx-beagle-x15-revc.dts
+++ b/arch/arm/dts/am57xx-beagle-x15-revc.dts
@@ -19,14 +19,9 @@
};
&mmc1 {
- pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
+ pinctrl-names = "default", "hs";
pinctrl-0 = <&mmc1_pins_default>;
pinctrl-1 = <&mmc1_pins_hs>;
- pinctrl-2 = <&mmc1_pins_sdr12>;
- pinctrl-3 = <&mmc1_pins_sdr25>;
- pinctrl-4 = <&mmc1_pins_sdr50>;
- pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>;
- pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
vmmc-supply = <&vdd_3v3>;
vqmmc-supply = <&ldo1_reg>;
};
diff --git a/arch/arm/dts/am57xx-idk-common.dtsi b/arch/arm/dts/am57xx-idk-common.dtsi
index fa5a078..fdb4e0e 100644
--- a/arch/arm/dts/am57xx-idk-common.dtsi
+++ b/arch/arm/dts/am57xx-idk-common.dtsi
@@ -405,6 +405,7 @@
vqmmc-supply = <&ldo1_reg>;
bus-width = <4>;
cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
+ no-1-8-v;
};
&mmc2 {
diff --git a/arch/arm/dts/armada-388-clearfog-u-boot.dtsi b/arch/arm/dts/armada-388-clearfog-u-boot.dtsi
index a12694e..cf6c088 100644
--- a/arch/arm/dts/armada-388-clearfog-u-boot.dtsi
+++ b/arch/arm/dts/armada-388-clearfog-u-boot.dtsi
@@ -11,3 +11,11 @@
&sdhci {
u-boot,dm-spl;
};
+
+&ahci0 {
+ u-boot,dm-spl;
+};
+
+&ahci1 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/armada-cp110-master.dtsi b/arch/arm/dts/armada-cp110-master.dtsi
index 551d00d..e4c17e9 100644
--- a/arch/arm/dts/armada-cp110-master.dtsi
+++ b/arch/arm/dts/armada-cp110-master.dtsi
@@ -96,6 +96,7 @@
#size-cells = <0>;
compatible = "marvell,orion-mdio";
reg = <0x12a200 0x10>;
+ device-name = "cpm-mdio";
};
cpm_syscon0: system-controller@440000 {
diff --git a/arch/arm/dts/armada-cp110-slave.dtsi b/arch/arm/dts/armada-cp110-slave.dtsi
index 2ea9004..2fbd7b5 100644
--- a/arch/arm/dts/armada-cp110-slave.dtsi
+++ b/arch/arm/dts/armada-cp110-slave.dtsi
@@ -96,6 +96,7 @@
#size-cells = <0>;
compatible = "marvell,orion-mdio";
reg = <0x12a200 0x10>;
+ device-name = "cps-mdio";
};
cps_syscon0: system-controller@440000 {
diff --git a/arch/arm/dts/ast2500-evb.dts b/arch/arm/dts/ast2500-evb.dts
index ebf44fd..4796ed4 100644
--- a/arch/arm/dts/ast2500-evb.dts
+++ b/arch/arm/dts/ast2500-evb.dts
@@ -59,3 +59,17 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mac2link_default &pinctrl_mdio2_default>;
};
+
+&sdhci0 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sd1_default>;
+};
+
+&sdhci1 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sd2_default>;
+};
diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
index 7f80bad..8ac4215 100644
--- a/arch/arm/dts/ast2500-u-boot.dtsi
+++ b/arch/arm/dts/ast2500-u-boot.dtsi
@@ -34,6 +34,22 @@
apb {
u-boot,dm-pre-reloc;
+
+ sdhci0: sdhci@1e740100 {
+ compatible = "aspeed,ast2500-sdhci";
+ reg = <0x1e740100>;
+ #reset-cells = <1>;
+ clocks = <&scu BCLK_SDCLK>;
+ resets = <&rst AST_RESET_SDIO>;
+ };
+
+ sdhci1: sdhci@1e740200 {
+ compatible = "aspeed,ast2500-sdhci";
+ reg = <0x1e740200>;
+ #reset-cells = <1>;
+ clocks = <&scu BCLK_SDCLK>;
+ resets = <&rst AST_RESET_SDIO>;
+ };
};
};
diff --git a/arch/arm/dts/at91-sama5d2_xplained.dts b/arch/arm/dts/at91-sama5d2_xplained.dts
index c0708fe..7f0d169 100644
--- a/arch/arm/dts/at91-sama5d2_xplained.dts
+++ b/arch/arm/dts/at91-sama5d2_xplained.dts
@@ -79,26 +79,18 @@
};
qspi0: spi@f0020000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi0_sck_cs_default &pinctrl_qspi0_dat_default>;
status = "okay";
+ u-boot,dm-pre-reloc;
flash@0 {
- compatible = "atmel,sama5d2-qspi-flash";
+ compatible = "jedec,spi-nor";
reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_qspi0_default>;
spi-max-frequency = <83000000>;
-
- partition@00000000 {
- label = "boot";
- reg = <0x00000000 0x00c00000>;
- };
-
- partition@00c00000 {
- label = "rootfs";
- reg = <0x00c00000 0x00000000>;
- };
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ u-boot,dm-pre-reloc;
};
};
@@ -208,14 +200,20 @@
bias-disable;
};
- pinctrl_qspi0_default: qspi0_default {
+ pinctrl_qspi0_sck_cs_default: qspi0_sck_cs_default {
pinmux = <PIN_PA22__QSPI0_SCK>,
- <PIN_PA23__QSPI0_CS>,
- <PIN_PA24__QSPI0_IO0>,
+ <PIN_PA23__QSPI0_CS>;
+ bias-disable;
+ u-boot,dm-pre-reloc;
+ };
+
+ pinctrl_qspi0_dat_default: qspi0_dat_default {
+ pinmux = <PIN_PA24__QSPI0_IO0>,
<PIN_PA25__QSPI0_IO1>,
<PIN_PA26__QSPI0_IO2>,
<PIN_PA27__QSPI0_IO3>;
- bias-disable;
+ bias-pull-up;
+ u-boot,dm-pre-reloc;
};
pinctrl_sdmmc0_cmd_dat_default: sdmmc0_cmd_dat_default {
diff --git a/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts b/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts
new file mode 100644
index 0000000..ac641ff
--- /dev/null
+++ b/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+
+/*
+ * UltraZed-EV Carrier Card v1 (based on the UltraZed-EV SoM)
+ * http://ultrazed.org/product/ultrazed-ev-carrier-card
+ */
+
+/dts-v1/;
+
+#include "avnet-ultrazedev-som-v1.0.dtsi"
+
+/ {
+ model = "Avnet UltraZed EV Carrier Card v1.0";
+ compatible = "avnet,ultrazedev-cc-v1.0-ultrazedev-som-v1.0",
+ "xlnx,zynqmp";
+ chosen {
+ stdout-path = "serial0:115200n8";
+ xlnx,eeprom = &eeprom;
+ };
+ aliases {
+ ethernet0 = &gem3;
+ serial0 = &uart0;
+ };
+};
+
+&uart0 {
+ device_type = "serial";
+ status = "okay";
+};
+
+&i2c_cc {
+ /* Microchip 24AA025E48T-I/OT: 2K I2C Serial EEPROM with EUI-48 */
+ eeprom: eeprom@51 {
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ };
+
+ /* IDT Versa Clock 5P49V5935B */
+ vc5: clock-generator@6a {
+ compatible = "idt,5p49v5935";
+ reg = <0x6a>;
+ #clock-cells = <1>;
+ };
+};
+
+/* Ethernet RJ-45 */
+&gem3 {
+ status = "okay";
+};
+
+/* microSD card slot */
+&sdhci1 {
+ status = "okay";
+ xlnx,mio_bank = <1>;
+ clock-frequency = <199998000>;
+ max-frequency = <50000000>;
+ no-1-8-v;
+ disable-wp;
+};
diff --git a/arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi b/arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi
new file mode 100644
index 0000000..b635db6
--- /dev/null
+++ b/arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+
+/*
+ * UltraZed-EV SoM v1
+ * http://ultrazed.org/product/ultrazed-ev
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+
+/ {
+ model = "Avnet UltraZed EV SoM v1.0";
+ compatible = "avnet,ultrazedev-som-v1.0", "xlnx,zynqmp";
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, /* 2 GB @ offset 0 */
+ <0x8 0x0 0x0 0x80000000>; /* 2 GB @ offset 32GB */
+ };
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ i2cswitch@70 {
+ compatible = "nxp,pca9543";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x70>;
+
+ /* I2C connected to Carrier Card via JX3A1/JX3C1 */
+ i2c_cc: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+/* Marvell 88E1512-A0-NNP2I000 Ethernet PHY */
+&gem3 {
+ phy-mode = "rgmii-id";
+ phy-handle = <&gem3phy>;
+ gem3phy: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+/* Micron MTFC8GAKAJCN-4M 8 GB eMMC */
+&sdhci0 {
+ status = "okay";
+ xlnx,mio_bank = <0>;
+ clock-frequency = <199998000>;
+};
diff --git a/arch/arm/dts/da850-evm-u-boot.dtsi b/arch/arm/dts/da850-evm-u-boot.dtsi
index 1683f34..aa42d30 100644
--- a/arch/arm/dts/da850-evm-u-boot.dtsi
+++ b/arch/arm/dts/da850-evm-u-boot.dtsi
@@ -10,6 +10,14 @@
soc@1c00000 {
u-boot,dm-spl;
};
+
+ nand {
+ compatible = "ti,davinci-nand";
+ };
+};
+
+ð0 {
+ pinctrl-0 = <&mii_pins>, <&mdio_pins>;
};
&flash {
diff --git a/arch/arm/dts/da850-lcdk-u-boot.dtsi b/arch/arm/dts/da850-lcdk-u-boot.dtsi
index 80dda8e..541f4ca 100644
--- a/arch/arm/dts/da850-lcdk-u-boot.dtsi
+++ b/arch/arm/dts/da850-lcdk-u-boot.dtsi
@@ -9,4 +9,8 @@
aliases {
i2c0 = &i2c0;
};
+
+ nand {
+ compatible = "ti,davinci-nand";
+ };
};
diff --git a/arch/arm/dts/da850-lego-ev3.dts b/arch/arm/dts/da850-lego-ev3.dts
new file mode 100644
index 0000000..e281d03
--- /dev/null
+++ b/arch/arm/dts/da850-lego-ev3.dts
@@ -0,0 +1,89 @@
+/*
+ * Device tree for LEGO MINDSTORMS EV3
+ *
+ * Copyright (C) 2017 David Lechner <david@lechnology.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * This is an absolute minimum device tree instead of using the one from Linux
+ * because the bootloader on the EV3 is limited to 256k. This saves us >10k.
+ */
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "lego,ev3", "ti,da850";
+ model = "LEGO MINDSTORMS EV3";
+
+ aliases {
+ serial1 = &serial1;
+ spi0 = &spi0;
+ };
+
+ chosen {
+ stdout-path = &serial1;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0xc0000000 0x04000000>;
+ };
+
+ arm {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ intc: interrupt-controller@fffee000 {
+ compatible = "ti,cp-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ ti,intc-size = <101>;
+ reg = <0xfffee000 0x2000>;
+ };
+ };
+
+ soc@1c00000 {
+ compatible = "simple-bus";
+ model = "da850";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x01c00000 0x400000>;
+ interrupt-parent = <&intc>;
+
+ mmc0: mmc@40000 {
+ compatible = "ti,da830-mmc";
+ reg = <0x40000 0x1000>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ interrupts = <16>;
+ max-frequency = <50000000>;
+ bus-width = <4>;
+ };
+
+ spi0: spi@41000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "ti,da830-spi";
+ reg = <0x41000 0x1000>;
+ num-cs = <6>;
+ ti,davinci-spi-intr-line = <1>;
+ interrupts = <20>;
+
+ flash@0 {
+ compatible = "micron,n25q128a13", "jedec,spi-nor", "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ };
+ };
+
+ serial1: serial@10c000 {
+ compatible = "ti,da830-uart", "ns16550a";
+ reg = <0x10c000 0x100>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupts = <53>;
+ };
+ };
+};
diff --git a/arch/arm/dts/da850.dtsi b/arch/arm/dts/da850.dtsi
index 47aa53b..559659b 100644
--- a/arch/arm/dts/da850.dtsi
+++ b/arch/arm/dts/da850.dtsi
@@ -476,7 +476,7 @@
clocksource: timer@20000 {
compatible = "ti,da830-timer";
reg = <0x20000 0x1000>;
- interrupts = <12>, <13>;
+ interrupts = <21>, <22>;
interrupt-names = "tint12", "tint34";
clocks = <&pll0_auxclk>;
};
diff --git a/arch/arm/dts/dra7-mmc-iodelay.dtsi b/arch/arm/dts/dra7-mmc-iodelay.dtsi
new file mode 100644
index 0000000..4acc215
--- /dev/null
+++ b/arch/arm/dts/dra7-mmc-iodelay.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MMC IOdelay values for TI's DRA7xx SoCs.
+ * Copyright (C) 2019 Texas Instruments
+ * Author: Faiz Abbas <faiz_abbas@ti.com>
+ */
+
+&dra7_pmx_core {
+ mmc1_pins_default_no_clk_pu: mmc1_pins_default_no_clk_pu {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+};
diff --git a/arch/arm/dts/dra74x-mmc-iodelay.dtsi b/arch/arm/dts/dra74x-mmc-iodelay.dtsi
index 28ebb4e..214b9e6 100644
--- a/arch/arm/dts/dra74x-mmc-iodelay.dtsi
+++ b/arch/arm/dts/dra74x-mmc-iodelay.dtsi
@@ -32,7 +32,7 @@
*
* Datamanual Revisions:
*
- * AM572x Silicon Revision 2.0: SPRS953B, Revised November 2016
+ * AM572x Silicon Revision 2.0: SPRS953F, Revised May 2019
* AM572x Silicon Revision 1.1: SPRS915R, Revised November 2016
*
*/
@@ -229,45 +229,45 @@
mmc3_pins_default: mmc3_pins_default {
pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
- DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
- DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
- DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
- DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
- DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
+ DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
+ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
+ DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
+ DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
+ DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
+ DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
>;
};
mmc3_pins_hs: mmc3_pins_hs {
pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
- DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
- DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
- DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
- DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
- DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
+ DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
+ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
+ DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
+ DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
+ DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
+ DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
>;
};
mmc3_pins_sdr12: mmc3_pins_sdr12 {
pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
- DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
- DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
- DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
- DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
- DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
+ DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
+ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
+ DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
+ DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
+ DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
+ DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
>;
};
mmc3_pins_sdr25: mmc3_pins_sdr25 {
pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
- DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
- DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
- DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
- DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
- DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
+ DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
+ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
+ DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
+ DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
+ DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
+ DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
>;
};
diff --git a/arch/arm/dts/dra76x-mmc-iodelay.dtsi b/arch/arm/dts/dra76x-mmc-iodelay.dtsi
index baba7b0..fdca481 100644
--- a/arch/arm/dts/dra76x-mmc-iodelay.dtsi
+++ b/arch/arm/dts/dra76x-mmc-iodelay.dtsi
@@ -22,7 +22,7 @@
*
* Datamanual Revisions:
*
- * DRA76x Silicon Revision 1.0: SPRS993A, Revised July 2017
+ * DRA76x Silicon Revision 1.0: SPRS993E, Revised December 2018
*
*/
@@ -169,25 +169,25 @@
/* Corresponds to MMC2_HS200_MANUAL1 in datamanual */
mmc2_iodelay_hs200_conf: mmc2_iodelay_hs200_conf {
pinctrl-pin-array = <
- 0x190 A_DELAY_PS(384) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */
- 0x194 A_DELAY_PS(0) G_DELAY_PS(174) /* CFG_GPMC_A19_OUT */
- 0x1a8 A_DELAY_PS(410) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */
- 0x1ac A_DELAY_PS(85) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */
- 0x1b4 A_DELAY_PS(468) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */
- 0x1b8 A_DELAY_PS(139) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */
- 0x1c0 A_DELAY_PS(676) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */
- 0x1c4 A_DELAY_PS(69) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */
- 0x1d0 A_DELAY_PS(1062) G_DELAY_PS(154) /* CFG_GPMC_A23_OUT */
- 0x1d8 A_DELAY_PS(640) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */
- 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */
- 0x1e4 A_DELAY_PS(356) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */
- 0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */
- 0x1f0 A_DELAY_PS(579) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */
- 0x1f4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */
- 0x1fc A_DELAY_PS(435) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */
- 0x200 A_DELAY_PS(36) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */
- 0x364 A_DELAY_PS(759) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */
- 0x368 A_DELAY_PS(72) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */
+ 0x190 A_DELAY_PS(384) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */
+ 0x194 A_DELAY_PS(350) G_DELAY_PS(174) /* CFG_GPMC_A19_OUT */
+ 0x1a8 A_DELAY_PS(410) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */
+ 0x1ac A_DELAY_PS(335) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */
+ 0x1b4 A_DELAY_PS(468) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */
+ 0x1b8 A_DELAY_PS(339) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */
+ 0x1c0 A_DELAY_PS(676) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */
+ 0x1c4 A_DELAY_PS(219) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */
+ 0x1d0 A_DELAY_PS(1062) G_DELAY_PS(154) /* CFG_GPMC_A23_OUT */
+ 0x1d8 A_DELAY_PS(640) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */
+ 0x1dc A_DELAY_PS(150) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */
+ 0x1e4 A_DELAY_PS(356) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */
+ 0x1e8 A_DELAY_PS(150) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */
+ 0x1f0 A_DELAY_PS(579) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */
+ 0x1f4 A_DELAY_PS(200) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */
+ 0x1fc A_DELAY_PS(435) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */
+ 0x200 A_DELAY_PS(236) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */
+ 0x364 A_DELAY_PS(759) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */
+ 0x368 A_DELAY_PS(372) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */
>;
};
diff --git a/arch/arm/dts/fsl-imx8dx.dtsi b/arch/arm/dts/fsl-imx8dx.dtsi
index 715abb4..0c33eee 100644
--- a/arch/arm/dts/fsl-imx8dx.dtsi
+++ b/arch/arm/dts/fsl-imx8dx.dtsi
@@ -11,6 +11,7 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/pads-imx8qxp.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
model = "Freescale i.MX8DX";
@@ -30,6 +31,14 @@
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ gpio4 = &gpio4;
+ gpio5 = &gpio5;
+ gpio6 = &gpio6;
+ gpio7 = &gpio7;
};
memory@80000000 {
@@ -543,6 +552,61 @@
power-domains = <&pd_conn_enet1>;
status = "disabled";
};
+
+ tsens: thermal-sensor {
+ compatible = "nxp,imx8qxp-sc-tsens";
+ /* number of the temp sensor on the chip */
+ tsens-num = <2>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal_zones: thermal-zones {
+ /* cpu thermal */
+ cpu-thermal0 {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ /*the slope and offset of the temp sensor */
+ thermal-sensors = <&tsens 0>;
+ trips {
+ cpu_alert0: trip0 {
+ temperature = <107000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu_crit0: trip1 {
+ temperature = <127000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device =
+ <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ drc-thermal0 {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&tsens 1>;
+ status = "disabled";
+ trips {
+ drc_alert0: trip0 {
+ temperature = <107000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ drc_crit0: trip1 {
+ temperature = <127000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
};
&A35_0 {
diff --git a/arch/arm/dts/fsl-ls1012a-rdb.dtsi b/arch/arm/dts/fsl-ls1012a-rdb.dtsi
index f053e78..55155fd 100644
--- a/arch/arm/dts/fsl-ls1012a-rdb.dtsi
+++ b/arch/arm/dts/fsl-ls1012a-rdb.dtsi
@@ -14,6 +14,10 @@
};
};
+&esdhc1 {
+ mmc-hs200-1_8v;
+};
+
&qspi {
bus-num = <0>;
status = "okay";
diff --git a/arch/arm/dts/fsl-ls1028a-qds.dts b/arch/arm/dts/fsl-ls1028a-qds.dts
index 46a0419..5d143ba 100644
--- a/arch/arm/dts/fsl-ls1028a-qds.dts
+++ b/arch/arm/dts/fsl-ls1028a-qds.dts
@@ -33,14 +33,80 @@
&esdhc1 {
status = "okay";
+
};
&i2c0 {
status = "okay";
+ u-boot,dm-pre-reloc;
+
+ fpga@66 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "simple-mfd";
+ reg = <0x66>;
+
+ mux-mdio@54 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mdio-mux-i2creg";
+ reg = <0x54>;
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x54 0xf0>;
+ mdio-parent-bus = <&mdio0>;
+
+ /* on-board MDIO with a single RGMII PHY */
+ mdio@00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x00>;
+
+ qds_phy0: phy@5 {
+ reg = <5>;
+ };
+ };
+ /* slot 1 */
+ slot1: mdio@40 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x40>;
+ };
+ /* slot 2 */
+ slot2: mdio@50 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x50>;
+ };
+ /* slot 3 */
+ slot3: mdio@60 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x60>;
+ };
+ /* slot 4 */
+ slot4: mdio@70 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x70>;
+ };
+ };
+ };
+
+ i2c-mux@77 {
+ compatible = "nxp,pca9547";
+ reg = <0x77>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
};
&i2c1 {
status = "okay";
+
+ rtc@51 {
+ compatible = "pcf2127-rtc";
+ reg = <0x51>;
+ };
};
&i2c2 {
@@ -86,3 +152,13 @@
&usb2 {
status = "okay";
};
+
+&enetc1 {
+ status = "okay";
+ phy-mode = "rgmii";
+ phy-handle = <&qds_phy0>;
+};
+
+&mdio0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1028a-rdb.dts b/arch/arm/dts/fsl-ls1028a-rdb.dts
index 932cfa2..3d5e8ad 100644
--- a/arch/arm/dts/fsl-ls1028a-rdb.dts
+++ b/arch/arm/dts/fsl-ls1028a-rdb.dts
@@ -33,10 +33,31 @@
&esdhc1 {
status = "okay";
+ mmc-hs200-1_8v;
};
&i2c0 {
status = "okay";
+ u-boot,dm-pre-reloc;
+
+ i2c-mux@77 {
+
+ compatible = "nxp,pca9547";
+ reg = <0x77>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+
+ rtc@51 {
+ compatible = "pcf2127-rtc";
+ reg = <0x51>;
+ };
+ };
+ };
};
&i2c1 {
@@ -86,3 +107,16 @@
&usb2 {
status = "okay";
};
+
+&enetc0 {
+ status = "okay";
+ phy-mode = "sgmii";
+ phy-handle = <&rdb_phy0>;
+};
+
+&mdio0 {
+ status = "okay";
+ rdb_phy0: phy@2 {
+ reg = <2>;
+ };
+};
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index 4907411..43a154e 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -117,6 +117,30 @@
#size-cells = <2>;
device_type = "pci";
ranges= <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000>;
+ enetc0: pci@0,0 {
+ reg = <0x000000 0 0 0 0>;
+ status = "disabled";
+ };
+ enetc1: pci@0,1 {
+ reg = <0x000100 0 0 0 0>;
+ status = "disabled";
+ };
+ enetc2: pci@0,2 {
+ reg = <0x000200 0 0 0 0>;
+ status = "okay";
+ phy-mode = "internal";
+ };
+ mdio0: pci@0,3 {
+ #address-cells=<0>;
+ #size-cells=<1>;
+ reg = <0x000300 0 0 0 0>;
+ status = "disabled";
+ };
+ enetc6: pci@0,6 {
+ reg = <0x000600 0 0 0 0>;
+ status = "okay";
+ phy-mode = "internal";
+ };
};
i2c0: i2c@2000000 {
diff --git a/arch/arm/dts/fsl-ls1088a-qds.dts b/arch/arm/dts/fsl-ls1088a-qds.dts
index 8fbb52f..f07d0c6 100644
--- a/arch/arm/dts/fsl-ls1088a-qds.dts
+++ b/arch/arm/dts/fsl-ls1088a-qds.dts
@@ -18,6 +18,29 @@
};
};
+&i2c0 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+
+ i2c-mux@77 {
+ compatible = "nxp,pca9547";
+ reg = <0x77>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+
+ rtc@51 {
+ compatible = "pcf2127-rtc";
+ reg = <0x51>;
+ };
+ };
+ };
+};
+
&ifc {
#address-cells = <2>;
#size-cells = <1>;
diff --git a/arch/arm/dts/fsl-ls1088a-rdb.dts b/arch/arm/dts/fsl-ls1088a-rdb.dts
index 765d1e3..0fe3519 100644
--- a/arch/arm/dts/fsl-ls1088a-rdb.dts
+++ b/arch/arm/dts/fsl-ls1088a-rdb.dts
@@ -17,6 +17,29 @@
};
};
+&i2c0 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+
+ i2c-mux@77 {
+ compatible = "nxp,pca9547";
+ reg = <0x77>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+
+ rtc@51 {
+ compatible = "pcf2127-rtc";
+ reg = <0x51>;
+ };
+ };
+ };
+};
+
&qspi {
bus-num = <0>;
status = "okay";
diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi
index 7c70585..4be1ab8 100644
--- a/arch/arm/dts/fsl-ls1088a.dtsi
+++ b/arch/arm/dts/fsl-ls1088a.dtsi
@@ -34,6 +34,38 @@
<1 10 0x8>; /* Hypervisor PPI, active-low */
};
+ i2c0: i2c@2000000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2000000 0x0 0x10000>;
+ interrupts = <0 34 4>;
+ };
+
+ i2c1: i2c@2010000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2010000 0x0 0x10000>;
+ interrupts = <0 34 4>;
+ };
+
+ i2c2: i2c@2020000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2020000 0x0 0x10000>;
+ interrupts = <0 35 4>;
+ };
+
+ i2c3: i2c@2030000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2030000 0x0 0x10000>;
+ interrupts = <0 35 4>;
+ };
+
serial0: serial@21c0500 {
device_type = "serial";
compatible = "fsl,ns16550", "ns16550a";
diff --git a/arch/arm/dts/fsl-ls2080a-qds.dts b/arch/arm/dts/fsl-ls2080a-qds.dts
index 2a0a528..13461b5 100644
--- a/arch/arm/dts/fsl-ls2080a-qds.dts
+++ b/arch/arm/dts/fsl-ls2080a-qds.dts
@@ -19,6 +19,25 @@
};
};
+&i2c0 {
+ status = "okay";
+ pca9547@77 {
+ compatible = "nxp,pca9547";
+ reg = <0x77>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x00>;
+ rtc@68 {
+ compatible = "dallas,ds3232";
+ reg = <0x68>;
+ };
+ };
+ };
+};
+
&dspi {
bus-num = <0>;
status = "okay";
diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index 5c0769b..99ed33a 100644
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -56,6 +56,42 @@
<0x00000000 0x08340000 0 0x40000>; /* MC control reg */
};
+ i2c0: i2c@2000000 {
+ status = "disabled";
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2000000 0x0 0x10000>;
+ interrupts = <0 34 0x4>; /* Level high type */
+ };
+
+ i2c1: i2c@2010000 {
+ status = "disabled";
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2010000 0x0 0x10000>;
+ interrupts = <0 34 0x4>; /* Level high type */
+ };
+
+ i2c2: i2c@2020000 {
+ status = "disabled";
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2020000 0x0 0x10000>;
+ interrupts = <0 35 0x4>; /* Level high type */
+ };
+
+ i2c3: i2c@2030000 {
+ status = "disabled";
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2030000 0x0 0x10000>;
+ interrupts = <0 35 0x4>; /* Level high type */
+ };
+
dspi: dspi@2100000 {
compatible = "fsl,vf610-dspi";
#address-cells = <1>;
diff --git a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
index bf97d13..72b2177 100644
--- a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
+++ b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
@@ -57,6 +57,28 @@
};
};
+&i2c0 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+
+ pca9547@75 {
+ compatible = "nxp,pca9547";
+ reg = <0x75>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x01>;
+ rtc@68 {
+ compatible = "dallas,ds3232";
+ reg = <0x68>;
+ };
+ };
+ };
+};
+
&sata {
status = "okay";
};
diff --git a/arch/arm/dts/fsl-lx2160a-qds.dts b/arch/arm/dts/fsl-lx2160a-qds.dts
index 99836c4..34df0f5 100644
--- a/arch/arm/dts/fsl-lx2160a-qds.dts
+++ b/arch/arm/dts/fsl-lx2160a-qds.dts
@@ -23,6 +23,29 @@
status = "okay";
};
+&i2c0 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+
+ i2c-mux@77 {
+ compatible = "nxp,pca9547";
+ reg = <0x77>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+
+ rtc@51 {
+ compatible = "pcf2127-rtc";
+ reg = <0x51>;
+ };
+ };
+ };
+};
+
&sata0 {
status = "okay";
};
diff --git a/arch/arm/dts/fsl-lx2160a-rdb.dts b/arch/arm/dts/fsl-lx2160a-rdb.dts
index 4b52644..46a9239 100644
--- a/arch/arm/dts/fsl-lx2160a-rdb.dts
+++ b/arch/arm/dts/fsl-lx2160a-rdb.dts
@@ -25,6 +25,21 @@
&esdhc1 {
status = "okay";
+ mmc-hs200-1_8v;
+};
+
+&i2c0 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+};
+
+&i2c4 {
+ status = "okay";
+
+ rtc@51 {
+ compatible = "pcf2127-rtc";
+ reg = <0x51>;
+ };
};
&sata0 {
diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi
index 2822078..a189333 100644
--- a/arch/arm/dts/fsl-lx2160a.dtsi
+++ b/arch/arm/dts/fsl-lx2160a.dtsi
@@ -49,6 +49,80 @@
<1 10 0x8>; /* Hypervisor PPI, active-low */
};
+ i2c0: i2c@2000000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2000000 0x0 0x10000>;
+ interrupts = <0 34 4>;
+ scl-gpio = <&gpio2 15 0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@2010000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2010000 0x0 0x10000>;
+ interrupts = <0 34 4>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@2020000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2020000 0x0 0x10000>;
+ interrupts = <0 35 4>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@2030000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2030000 0x0 0x10000>;
+ interrupts = <0 35 4>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@2040000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2040000 0x0 0x10000>;
+ interrupts = <0 74 4>;
+ scl-gpio = <&gpio2 16 0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@2050000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2050000 0x0 0x10000>;
+ interrupts = <0 74 4>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@2060000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2060000 0x0 0x10000>;
+ interrupts = <0 75 4>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@2070000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2070000 0x0 0x10000>;
+ interrupts = <0 75 4>;
+ status = "disabled";
+ };
+
uart0: serial@21c0000 {
compatible = "arm,pl011";
reg = <0x0 0x21c0000 0x0 0x1000>;
@@ -102,6 +176,17 @@
num-cs = <6>;
};
+ gpio2: gpio@2320000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2320000 0x0 0x10000>;
+ interrupts = <0 37 4>;
+ gpio-controller;
+ little-endian;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
usb0: usb3@3100000 {
compatible = "fsl,layerscape-dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
diff --git a/arch/arm/dts/hi3660-hikey960-u-boot.dtsi b/arch/arm/dts/hi3660-hikey960-u-boot.dtsi
new file mode 100644
index 0000000..648c77f
--- /dev/null
+++ b/arch/arm/dts/hi3660-hikey960-u-boot.dtsi
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (c) 2019 Linaro Ltd.
+ */
+
+&dwmmc1 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/hi3660-hikey960.dts b/arch/arm/dts/hi3660-hikey960.dts
new file mode 100644
index 0000000..9fbfb42
--- /dev/null
+++ b/arch/arm/dts/hi3660-hikey960.dts
@@ -0,0 +1,607 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Hisilicon HiKey960 Development Board
+ *
+ * Copyright (C) 2016, Hisilicon Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include "hi3660.dtsi"
+#include "hikey960-pinctrl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ model = "HiKey960";
+ compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
+
+ aliases {
+ mshc1 = &dwmmc1;
+ mshc2 = &dwmmc2;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
+ serial6 = &uart6;
+ };
+
+ chosen {
+ stdout-path = "serial6:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ /* rewrite this at bootloader */
+ reg = <0x0 0x0 0x0 0x0>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ramoops@32000000 {
+ compatible = "ramoops";
+ reg = <0x0 0x32000000 0x0 0x00100000>;
+ record-size = <0x00020000>;
+ console-size = <0x00020000>;
+ ftrace-size = <0x00020000>;
+ };
+ };
+
+ reboot-mode-syscon@32100000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x0 0x32100000 0x0 0x00001000>;
+
+ reboot-mode {
+ compatible = "syscon-reboot-mode";
+ offset = <0x0>;
+
+ mode-normal = <0x77665501>;
+ mode-bootloader = <0x77665500>;
+ mode-recovery = <0x77665502>;
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwr_key_pmx_func &pwr_key_cfg_func>;
+
+ power {
+ wakeup-source;
+ gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
+ label = "GPIO Power";
+ linux,code = <KEY_POWER>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ user_led1 {
+ label = "green:user1";
+ /* gpio_150_user_led1 */
+ gpios = <&gpio18 6 0>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ user_led2 {
+ label = "green:user2";
+ /* gpio_151_user_led2 */
+ gpios = <&gpio18 7 0>;
+ linux,default-trigger = "none";
+ };
+
+ user_led3 {
+ label = "green:user3";
+ /* gpio_189_user_led3 */
+ gpios = <&gpio23 5 0>;
+ linux,default-trigger = "mmc0";
+ };
+
+ user_led4 {
+ label = "green:user4";
+ /* gpio_190_user_led4 */
+ gpios = <&gpio23 6 0>;
+ panic-indicator;
+ linux,default-trigger = "none";
+ };
+
+ wlan_active_led {
+ label = "yellow:wlan";
+ /* gpio_205_wifi_active */
+ gpios = <&gpio25 5 0>;
+ linux,default-trigger = "phy0tx";
+ default-state = "off";
+ };
+
+ bt_active_led {
+ label = "blue:bt";
+ gpios = <&gpio25 7 0>;
+ /* gpio_207_user_led1 */
+ linux,default-trigger = "hci0-power";
+ default-state = "off";
+ };
+ };
+
+ pmic: pmic@fff34000 {
+ compatible = "hisilicon,hi6421v530-pmic";
+ reg = <0x0 0xfff34000 0x0 0x1000>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ regulators {
+ ldo3: LDO3 { /* HDMI */
+ regulator-name = "VOUT3_1V85";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2200000>;
+ regulator-enable-ramp-delay = <120>;
+ };
+
+ ldo9: LDO9 { /* SDCARD I/O */
+ regulator-name = "VOUT9_1V8_2V95";
+ regulator-min-microvolt = <1750000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <240>;
+ };
+
+ ldo11: LDO11 { /* Low Speed Connector */
+ regulator-name = "VOUT11_1V8_2V95";
+ regulator-min-microvolt = <1750000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <240>;
+ };
+
+ ldo15: LDO15 { /* UFS VCC */
+ regulator-name = "VOUT15_3V0";
+ regulator-min-microvolt = <1750000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-enable-ramp-delay = <120>;
+ };
+
+ ldo16: LDO16 { /* SD VDD */
+ regulator-name = "VOUT16_2V95";
+ regulator-min-microvolt = <1750000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-enable-ramp-delay = <360>;
+ };
+ };
+ };
+
+ wlan_en: wlan-en-1-8v {
+ compatible = "regulator-fixed";
+ regulator-name = "wlan-en-regulator";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ /* GPIO_051_WIFI_EN */
+ gpio = <&gpio6 3 0>;
+
+ /* WLAN card specific delay */
+ startup-delay-us = <70000>;
+ enable-active-high;
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+};
+
+/*
+ * Legend: proper name = the GPIO line is used as GPIO
+ * NC = not connected (pin out but not routed from the chip to
+ * anything the board)
+ * "[PER]" = pin is muxed for [peripheral] (not GPIO)
+ * "" = no idea, schematic doesn't say, could be
+ * unrouted (not connected to any external pin)
+ * LSEC = Low Speed External Connector
+ * HSEC = High Speed External Connector
+ *
+ * Line names are taken from "HiKey 960 Board ver A" schematics
+ * from Huawei. The 40 pin low speed expansion connector is named
+ * J2002 63453-140LF.
+ *
+ * For the lines routed to the external connectors the
+ * lines are named after the 96Boards CE Specification 1.0,
+ * Appendix "Expansion Connector Signal Description".
+ *
+ * When the 96Board naming of a line and the schematic name of
+ * the same line are in conflict, the 96Board specification
+ * takes precedence, which means that the external UART on the
+ * LSEC is named UART0 while the schematic and SoC names this
+ * UART3. This is only for the informational lines i.e. "[FOO]",
+ * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only
+ * ones actually used for GPIO.
+ */
+&gpio0 {
+ /* GPIO_000-GPIO_007 */
+ gpio-line-names =
+ "",
+ "TP901", /* TEST_MODE connected to TP901 */
+ "[PMU0_SSI]",
+ "[PMU1_SSI]",
+ "[PMU2_SSI]",
+ "[PMU0_CLKOUT]",
+ "[JTAG_TCK]",
+ "[JTAG_TMS]";
+};
+
+&gpio1 {
+ /* GPIO_008-GPIO_015 */
+ gpio-line-names =
+ "[JTAG_TRST_N]",
+ "[JTAG_TDI]",
+ "[JTAG_TDO]",
+ "NC", "NC",
+ "[I2C3_SCL]",
+ "[I2C3_SDA]",
+ "NC";
+};
+
+&gpio2 {
+ /* GPIO_016-GPIO_023 */
+ gpio-line-names =
+ "NC", "NC", "NC",
+ "GPIO-J", /* LSEC pin 32: GPIO_019 */
+ "GPIO_020_HDMI_SEL",
+ "GPIO-L", /* LSEC pin 34: GPIO_021 */
+ "GPIO_022_UFSBUCK_INT_N",
+ "GPIO-G"; /* LSEC pin 29: LCD_TE0 */
+};
+
+&gpio3 {
+ /* GPIO_024-GPIO_031 */
+ /* The rail from pin BK36 is named LCD_TE0, we assume to be muxed as GPIO for GPIO-G */
+ gpio-line-names =
+ "[CSI0_MCLK]", /* HSEC pin 15: ISP_CCLK0_MCAM */
+ "[CSI1_MCLK]", /* HSEC pin 17: ISP_CCLK1_SCAM */
+ "NC",
+ "[I2C2_SCL]", /* HSEC pin 32: ISP_SCL0 */
+ "[I2C2_SDA]", /* HSEC pin 34: ISP_SDA0 */
+ "[I2C3_SCL]", /* HSEC pin 36: ISP_SCL1 */
+ "[I2C3_SDA]", /* HSEC pin 38: ISP_SDA1 */
+ "NC";
+};
+
+&gpio4 {
+ /* GPIO_032-GPIO_039 */
+ gpio-line-names =
+ "NC", "NC",
+ "PWR_BTN_N", /* LSEC pin 4: GPIO_034_PWRON_DET */
+ "GPIO_035_PMU2_EN",
+ "GPIO_036_USB_HUB_RESET",
+ "NC", "NC", "NC";
+};
+
+&gpio5 {
+ /* GPIO_040-GPIO_047 */
+ gpio-line-names =
+ "GPIO-H", /* LSEC pin 30: GPIO_040_LCD_RST_N */
+ "GPIO_041_HDMI_PD",
+ "TP904", /* Test point */
+ "TP905", /* Test point */
+ "NC", "NC",
+ "GPIO_046_HUB_VDD33_EN",
+ "GPIO_047_PMU1_EN";
+};
+
+&gpio6 {
+ /* GPIO_048-GPIO_055 */
+ gpio-line-names =
+ "NC", "NC", "NC",
+ "GPIO_051_WIFI_EN",
+ "GPIO-I", /* LSEC pin 31: GPIO_052_CAM0_RST_N */
+ /*
+ * These two pins should be used for SD(IO) data according to the
+ * 96boards specification but seems to be repurposed for a IRDA UART.
+ * They are however named according to the spec.
+ */
+ "[SD_DAT1]", /* HSEC pin 3: UART0_IRDA_RXD */
+ "[SD_DAT2]", /* HSEC pin 5: UART0_IRDA_TXD */
+ "[UART1_RXD]"; /* LSEC pin 13: DEBUG_UART6_RXD */
+};
+
+&gpio7 {
+ /* GPIO_056-GPIO_063 */
+ gpio-line-names =
+ "[UART1_TXD]", /* LSEC pin 11: DEBUG_UART6_TXD */
+ "[UART0_CTS]", /* LSEC pin 3: UART3_CTS_N */
+ "[UART0_RTS]", /* LSEC pin 9: UART3_RTS_N */
+ "[UART0_RXD]", /* LSEC pin 7: UART3_RXD */
+ "[UART0_TXD]", /* LSEC pin 5: UART3_TXD */
+ "[SOC_BT_UART4_CTS_N]",
+ "[SOC_BT_UART4_RTS_N]",
+ "[SOC_BT_UART4_RXD]";
+};
+
+&gpio8 {
+ /* GPIO_064-GPIO_071 */
+ gpio-line-names =
+ "[SOC_BT_UART4_TXD]",
+ "NC",
+ "[PMU_HKADC_SSI]",
+ "NC",
+ "GPIO_068_SEL",
+ "NC", "NC", "NC";
+
+};
+
+&gpio9 {
+ /* GPIO_072-GPIO_079 */
+ gpio-line-names =
+ "NC", "NC", "NC",
+ "GPIO-K", /* LSEC pin 33: GPIO_075_CAM1_RST_N */
+ "NC", "NC", "NC", "NC";
+};
+
+&gpio10 {
+ /* GPIO_080-GPIO_087 */
+ gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC";
+};
+
+&gpio11 {
+ /* GPIO_088-GPIO_095 */
+ gpio-line-names =
+ "NC",
+ "[PCIE_PERST_N]",
+ "NC", "NC", "NC", "NC", "NC", "NC";
+};
+
+&gpio12 {
+ /* GPIO_096-GPIO_103 */
+ gpio-line-names = "NC", "NC", "NC", "", "", "", "", "NC";
+};
+
+&gpio13 {
+ /* GPIO_104-GPIO_111 */
+ gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC";
+};
+
+&gpio14 {
+ /* GPIO_112-GPIO_119 */
+ gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC";
+};
+
+&gpio15 {
+ /* GPIO_120-GPIO_127 */
+ gpio-line-names =
+ "NC", "NC", "NC", "NC", "NC", "NC",
+ "GPIO_126_BT_EN",
+ "TP902"; /* GPIO_127_JTAG_SEL0 */
+};
+
+&gpio16 {
+ /* GPIO_128-GPIO_135 */
+ gpio-line-names = "", "", "", "", "", "", "", "";
+};
+
+&gpio17 {
+ /* GPIO_136-GPIO_143 */
+ gpio-line-names = "", "", "", "", "", "", "", "";
+};
+
+&gpio18 {
+ /* GPIO_144-GPIO_151 */
+ gpio-line-names =
+ "[UFS_REF_CLK]",
+ "[UFS_RST_N]",
+ "[SPI1_SCLK]", /* HSEC pin 9: GPIO_146_SPI3_CLK */
+ "[SPI1_DIN]", /* HSEC pin 11: GPIO_147_SPI3_DI */
+ "[SPI1_DOUT]", /* HSEC pin 1: GPIO_148_SPI3_DO */
+ "[SPI1_CS]", /* HSEC pin 7: GPIO_149_SPI3_CS0_N */
+ "GPIO_150_USER_LED1",
+ "GPIO_151_USER_LED2";
+};
+
+&gpio19 {
+ /* GPIO_152-GPIO_159 */
+ gpio-line-names = "NC", "NC", "NC", "NC", "", "", "", "";
+};
+
+&gpio20 {
+ /* GPIO_160-GPIO_167 */
+ gpio-line-names =
+ "[SD_CLK]",
+ "[SD_CMD]",
+ "[SD_DATA0]",
+ "[SD_DATA1]",
+ "[SD_DATA2]",
+ "[SD_DATA3]",
+ "", "";
+};
+
+&gpio21 {
+ /* GPIO_168-GPIO_175 */
+ gpio-line-names =
+ "[WL_SDIO_CLK]",
+ "[WL_SDIO_CMD]",
+ "[WL_SDIO_DATA0]",
+ "[WL_SDIO_DATA1]",
+ "[WL_SDIO_DATA2]",
+ "[WL_SDIO_DATA3]",
+ "", "";
+};
+
+&gpio22 {
+ /* GPIO_176-GPIO_183 */
+ gpio-line-names =
+ "[GPIO_176_PMU_PWR_HOLD]",
+ "NA",
+ "[SYSCLK_EN]",
+ "GPIO_179_WL_WAKEUP_AP",
+ "GPIO_180_HDMI_INT",
+ "NA",
+ "GPIO-F", /* LSEC pin 28: LCD_BL_PWM */
+ "[I2C0_SCL]"; /* LSEC pin 15 */
+};
+
+&gpio23 {
+ /* GPIO_184-GPIO_191 */
+ gpio-line-names =
+ "[I2C0_SDA]", /* LSEC pin 17 */
+ "[I2C1_SCL]", /* Actual SoC I2C1 */
+ "[I2C1_SDA]", /* Actual SoC I2C1 */
+ "[I2C1_SCL]", /* LSEC pin 19: I2C7_SCL */
+ "[I2C1_SDA]", /* LSEC pin 21: I2C7_SDA */
+ "GPIO_189_USER_LED3",
+ "GPIO_190_USER_LED4",
+ "";
+};
+
+&gpio24 {
+ /* GPIO_192-GPIO_199 */
+ gpio-line-names =
+ "[PCM_DI]", /* LSEC pin 22: GPIO_192_I2S0_DI */
+ "[PCM_DO]", /* LSEC pin 20: GPIO_193_I2S0_DO */
+ "[PCM_CLK]", /* LSEC pin 18: GPIO_194_I2S0_XCLK */
+ "[PCM_FS]", /* LSEC pin 16: GPIO_195_I2S0_XFS */
+ "[GPIO_196_I2S2_DI]",
+ "[GPIO_197_I2S2_DO]",
+ "[GPIO_198_I2S2_XCLK]",
+ "[GPIO_199_I2S2_XFS]";
+};
+
+&gpio25 {
+ /* GPIO_200-GPIO_207 */
+ gpio-line-names =
+ "NC",
+ "NC",
+ "GPIO_202_VBUS_TYPEC",
+ "GPIO_203_SD_DET",
+ "GPIO_204_PMU12_IRQ_N",
+ "GPIO_205_WIFI_ACTIVE",
+ "GPIO_206_USBSW_SEL",
+ "GPIO_207_BT_ACTIVE";
+};
+
+&gpio26 {
+ /* GPIO_208-GPIO_215 */
+ gpio-line-names =
+ "GPIO-A", /* LSEC pin 23: GPIO_208 */
+ "GPIO-B", /* LSEC pin 24: GPIO_209 */
+ "GPIO-C", /* LSEC pin 25: GPIO_210 */
+ "GPIO-D", /* LSEC pin 26: GPIO_211 */
+ "GPIO-E", /* LSEC pin 27: GPIO_212 */
+ "[PCIE_CLKREQ_N]",
+ "[PCIE_WAKE_N]",
+ "[SPI0_CLK]"; /* LSEC pin 8: SPI2_CLK */
+};
+
+&gpio27 {
+ /* GPIO_216-GPIO_223 */
+ gpio-line-names =
+ "[SPI0_DIN]", /* LSEC pin 10: SPI2_DI */
+ "[SPI0_DOUT]", /* LSEC pin 14: SPI2_DO */
+ "[SPI0_CS]", /* LSEC pin 12: SPI2_CS0_N */
+ "GPIO_219_CC_INT",
+ "NC",
+ "NC",
+ "[PMU_INT]",
+ "";
+};
+
+&gpio28 {
+ /* GPIO_224-GPIO_231 */
+ gpio-line-names =
+ "", "", "", "", "", "", "", "";
+};
+
+&i2c0 {
+ /* On Low speed expansion */
+ label = "LS-I2C0";
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+
+ adv7533: adv7533@39 {
+ status = "ok";
+ compatible = "adi,adv7533";
+ reg = <0x39>;
+ };
+};
+
+&uart3 {
+ /* On Low speed expansion */
+ label = "LS-UART0";
+ status = "okay";
+};
+
+&uart4 {
+ status = "okay";
+
+ bluetooth {
+ compatible = "ti,wl1837-st";
+ enable-gpios = <&gpio15 6 GPIO_ACTIVE_HIGH>;
+ max-speed = <3000000>;
+ };
+};
+
+&i2c7 {
+ /* On Low speed expansion */
+ label = "LS-I2C1";
+ status = "okay";
+};
+
+&uart6 {
+ /* On Low speed expansion */
+ label = "LS-UART1";
+ status = "okay";
+};
+
+&spi2 {
+ /* On Low speed expansion */
+ label = "LS-SPI0";
+ status = "okay";
+};
+
+&spi3 {
+ /* On High speed expansion */
+ label = "HS-SPI1";
+ status = "okay";
+};
+
+&dwmmc1 {
+ cd-gpios = <&gpio25 3 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd_pmx_func
+ &sd_clk_cfg_func
+ &sd_cfg_func>;
+ vmmc-supply = <&ldo16>;
+ vqmmc-supply = <&ldo9>;
+ status = "okay";
+};
+
+&dwmmc2 { /* WIFI */
+ bus-width = <0x4>;
+ non-removable;
+ broken-cd;
+ cap-power-off-card;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio_pmx_func
+ &sdio_clk_cfg_func
+ &sdio_cfg_func>;
+ /* WL_EN */
+ vmmc-supply = <&wlan_en>;
+ status = "ok";
+
+ wlcore: wlcore@2 {
+ compatible = "ti,wl1837";
+ reg = <2>; /* sdio func num */
+ /* WL_IRQ, GPIO_179_WL_WAKEUP_AP */
+ interrupt-parent = <&gpio22>;
+ interrupts = <3 IRQ_TYPE_EDGE_RISING>;
+ };
+};
diff --git a/arch/arm/dts/hi3660.dtsi b/arch/arm/dts/hi3660.dtsi
new file mode 100644
index 0000000..65a45b0
--- /dev/null
+++ b/arch/arm/dts/hi3660.dtsi
@@ -0,0 +1,1157 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Hisilicon Hi3660 SoC
+ *
+ * Copyright (C) 2016, Hisilicon Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/hi3660-clock.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+ compatible = "hisilicon,hi3660";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+ core1 {
+ cpu = <&cpu5>;
+ };
+ core2 {
+ cpu = <&cpu6>;
+ };
+ core3 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&A53_L2>;
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ capacity-dmips-mhz = <592>;
+ clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
+ operating-points-v2 = <&cluster0_opp>;
+ #cooling-cells = <2>;
+ dynamic-power-coefficient = <110>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ next-level-cache = <&A53_L2>;
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ capacity-dmips-mhz = <592>;
+ clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
+ operating-points-v2 = <&cluster0_opp>;
+ #cooling-cells = <2>;
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ next-level-cache = <&A53_L2>;
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ capacity-dmips-mhz = <592>;
+ clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
+ operating-points-v2 = <&cluster0_opp>;
+ #cooling-cells = <2>;
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ next-level-cache = <&A53_L2>;
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ capacity-dmips-mhz = <592>;
+ clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
+ operating-points-v2 = <&cluster0_opp>;
+ #cooling-cells = <2>;
+ };
+
+ cpu4: cpu@100 {
+ compatible = "arm,cortex-a73";
+ device_type = "cpu";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ next-level-cache = <&A73_L2>;
+ cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>;
+ capacity-dmips-mhz = <1024>;
+ clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
+ operating-points-v2 = <&cluster1_opp>;
+ #cooling-cells = <2>;
+ dynamic-power-coefficient = <550>;
+ };
+
+ cpu5: cpu@101 {
+ compatible = "arm,cortex-a73";
+ device_type = "cpu";
+ reg = <0x0 0x101>;
+ enable-method = "psci";
+ next-level-cache = <&A73_L2>;
+ cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>;
+ capacity-dmips-mhz = <1024>;
+ clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
+ operating-points-v2 = <&cluster1_opp>;
+ #cooling-cells = <2>;
+ };
+
+ cpu6: cpu@102 {
+ compatible = "arm,cortex-a73";
+ device_type = "cpu";
+ reg = <0x0 0x102>;
+ enable-method = "psci";
+ next-level-cache = <&A73_L2>;
+ cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>;
+ capacity-dmips-mhz = <1024>;
+ clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
+ operating-points-v2 = <&cluster1_opp>;
+ #cooling-cells = <2>;
+ };
+
+ cpu7: cpu@103 {
+ compatible = "arm,cortex-a73";
+ device_type = "cpu";
+ reg = <0x0 0x103>;
+ enable-method = "psci";
+ next-level-cache = <&A73_L2>;
+ cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>;
+ capacity-dmips-mhz = <1024>;
+ clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
+ operating-points-v2 = <&cluster1_opp>;
+ #cooling-cells = <2>;
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ CPU_SLEEP_0: cpu-sleep-0 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <400>;
+ exit-latency-us = <650>;
+ min-residency-us = <1500>;
+ };
+ CLUSTER_SLEEP_0: cluster-sleep-0 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x1010000>;
+ entry-latency-us = <500>;
+ exit-latency-us = <1600>;
+ min-residency-us = <3500>;
+ };
+
+
+ CPU_SLEEP_1: cpu-sleep-1 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <400>;
+ exit-latency-us = <550>;
+ min-residency-us = <1500>;
+ };
+
+ CLUSTER_SLEEP_1: cluster-sleep-1 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x1010000>;
+ entry-latency-us = <800>;
+ exit-latency-us = <2900>;
+ min-residency-us = <3500>;
+ };
+ };
+
+ A53_L2: l2-cache0 {
+ compatible = "cache";
+ };
+
+ A73_L2: l2-cache1 {
+ compatible = "cache";
+ };
+ };
+
+ cluster0_opp: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <533000000>;
+ opp-microvolt = <700000>;
+ clock-latency-ns = <300000>;
+ };
+
+ opp01 {
+ opp-hz = /bits/ 64 <999000000>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <300000>;
+ };
+
+ opp02 {
+ opp-hz = /bits/ 64 <1402000000>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <300000>;
+ };
+
+ opp03 {
+ opp-hz = /bits/ 64 <1709000000>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <300000>;
+ };
+
+ opp04 {
+ opp-hz = /bits/ 64 <1844000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <300000>;
+ };
+ };
+
+ cluster1_opp: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp10 {
+ opp-hz = /bits/ 64 <903000000>;
+ opp-microvolt = <700000>;
+ clock-latency-ns = <300000>;
+ };
+
+ opp11 {
+ opp-hz = /bits/ 64 <1421000000>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <300000>;
+ };
+
+ opp12 {
+ opp-hz = /bits/ 64 <1805000000>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <300000>;
+ };
+
+ opp13 {
+ opp-hz = /bits/ 64 <2112000000>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <300000>;
+ };
+
+ opp14 {
+ opp-hz = /bits/ 64 <2362000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <300000>;
+ };
+ };
+
+ gic: interrupt-controller@e82b0000 {
+ compatible = "arm,gic-400";
+ reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */
+ <0x0 0xe82b2000 0 0x2000>, /* GICC */
+ <0x0 0xe82b4000 0 0x2000>, /* GICH */
+ <0x0 0xe82b6000 0 0x2000>; /* GICV */
+ #address-cells = <0>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ a53-pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>,
+ <&cpu1>,
+ <&cpu2>,
+ <&cpu3>;
+ };
+
+ a73-pmu {
+ compatible = "arm,cortex-a73-pmu";
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu4>,
+ <&cpu5>,
+ <&cpu6>,
+ <&cpu7>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ crg_ctrl: crg_ctrl@fff35000 {
+ compatible = "hisilicon,hi3660-crgctrl", "syscon";
+ reg = <0x0 0xfff35000 0x0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ crg_rst: crg_rst_controller {
+ compatible = "hisilicon,hi3660-reset";
+ #reset-cells = <2>;
+ hisi,rst-syscon = <&crg_ctrl>;
+ };
+
+
+ pctrl: pctrl@e8a09000 {
+ compatible = "hisilicon,hi3660-pctrl", "syscon";
+ reg = <0x0 0xe8a09000 0x0 0x2000>;
+ #clock-cells = <1>;
+ };
+
+ pmuctrl: crg_ctrl@fff34000 {
+ compatible = "hisilicon,hi3660-pmuctrl", "syscon";
+ reg = <0x0 0xfff34000 0x0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ sctrl: sctrl@fff0a000 {
+ compatible = "hisilicon,hi3660-sctrl", "syscon";
+ reg = <0x0 0xfff0a000 0x0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ iomcu: iomcu@ffd7e000 {
+ compatible = "hisilicon,hi3660-iomcu", "syscon";
+ reg = <0x0 0xffd7e000 0x0 0x1000>;
+ #clock-cells = <1>;
+
+ };
+
+ iomcu_rst: reset {
+ compatible = "hisilicon,hi3660-reset";
+ hisi,rst-syscon = <&iomcu>;
+ #reset-cells = <2>;
+ };
+
+ mailbox: mailbox@e896b000 {
+ compatible = "hisilicon,hi3660-mbox";
+ reg = <0x0 0xe896b000 0x0 0x1000>;
+ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <3>;
+ };
+
+ stub_clock: stub_clock@e896b500 {
+ compatible = "hisilicon,hi3660-stub-clk";
+ reg = <0x0 0xe896b500 0x0 0x0100>;
+ #clock-cells = <1>;
+ mboxes = <&mailbox 13 3 0>;
+ };
+
+ dual_timer0: timer@fff14000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x0 0xfff14000 0x0 0x1000>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_OSC32K>,
+ <&crg_ctrl HI3660_OSC32K>,
+ <&crg_ctrl HI3660_OSC32K>;
+ clock-names = "timer1", "timer2", "apb_pclk";
+ };
+
+ i2c0: i2c@ffd71000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0xffd71000 0x0 0x1000>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>;
+ resets = <&iomcu_rst 0x20 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@ffd72000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0xffd72000 0x0 0x1000>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>;
+ resets = <&iomcu_rst 0x20 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@fdf0c000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0xfdf0c000 0x0 0x1000>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>;
+ resets = <&crg_rst 0x78 7>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@fdf0b000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0xfdf0b000 0x0 0x1000>;
+ interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>;
+ resets = <&crg_rst 0x60 14>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>;
+ status = "disabled";
+ };
+
+ uart0: serial@fdf02000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xfdf02000 0x0 0x1000>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>,
+ <&crg_ctrl HI3660_PCLK>;
+ clock-names = "uartclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
+ status = "disabled";
+ };
+
+ uart1: serial@fdf00000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xfdf00000 0x0 0x1000>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ dma-names = "rx", "tx";
+ dmas = <&dma0 2 &dma0 3>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>,
+ <&crg_ctrl HI3660_CLK_GATE_UART1>;
+ clock-names = "uartclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>;
+ status = "disabled";
+ };
+
+ uart2: serial@fdf03000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xfdf03000 0x0 0x1000>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ dma-names = "rx", "tx";
+ dmas = <&dma0 4 &dma0 5>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>,
+ <&crg_ctrl HI3660_PCLK>;
+ clock-names = "uartclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
+ status = "disabled";
+ };
+
+ uart3: serial@ffd74000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xffd74000 0x0 0x1000>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_FACTOR_UART3>,
+ <&crg_ctrl HI3660_PCLK>;
+ clock-names = "uartclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
+ status = "disabled";
+ };
+
+ uart4: serial@fdf01000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xfdf01000 0x0 0x1000>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ dma-names = "rx", "tx";
+ dmas = <&dma0 6 &dma0 7>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>,
+ <&crg_ctrl HI3660_CLK_GATE_UART4>;
+ clock-names = "uartclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
+ status = "disabled";
+ };
+
+ uart5: serial@fdf05000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xfdf05000 0x0 0x1000>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ dma-names = "rx", "tx";
+ dmas = <&dma0 8 &dma0 9>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>,
+ <&crg_ctrl HI3660_CLK_GATE_UART5>;
+ clock-names = "uartclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>;
+ status = "disabled";
+ };
+
+ uart6: serial@fff32000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xfff32000 0x0 0x1000>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ clock = <19200000>;
+ clocks = <&crg_ctrl HI3660_CLK_UART6>,
+ <&crg_ctrl HI3660_PCLK>;
+ clock-names = "uartclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>;
+ status = "disabled";
+ };
+
+ dma0: dma@fdf30000 {
+ compatible = "hisilicon,k3-dma-1.0";
+ reg = <0x0 0xfdf30000 0x0 0x1000>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ dma-requests = <32>;
+ dma-channel-mask = <0xfffe>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>;
+ dma-no-cci;
+ dma-type = "hi3660_dma";
+ };
+
+ asp_dmac: dma-controller@e804b000 {
+ compatible = "hisilicon,hisi-pcm-asp-dma-1.0";
+ reg = <0x0 0xe804b000 0x0 0x1000>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ dma-requests = <32>;
+ interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "asp_dma_irq";
+ };
+
+ rtc0: rtc@fff04000 {
+ compatible = "arm,pl031", "arm,primecell";
+ reg = <0x0 0Xfff04000 0x0 0x1000>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_PCLK>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio0: gpio@e8a0b000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a0b000 0 0x1000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 1 0 7>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO0>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio1: gpio@e8a0c000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a0c000 0 0x1000>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 1 7 7>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO1>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio2: gpio@e8a0d000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a0d000 0 0x1000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 14 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO2>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio3: gpio@e8a0e000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a0e000 0 0x1000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 22 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO3>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio4: gpio@e8a0f000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a0f000 0 0x1000>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 30 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO4>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio5: gpio@e8a10000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a10000 0 0x1000>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 38 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO5>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio6: gpio@e8a11000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a11000 0 0x1000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 46 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO6>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio7: gpio@e8a12000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a12000 0 0x1000>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 54 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO7>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio8: gpio@e8a13000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a13000 0 0x1000>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 62 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO8>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio9: gpio@e8a14000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a14000 0 0x1000>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 70 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO9>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio10: gpio@e8a15000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a15000 0 0x1000>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 78 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO10>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio11: gpio@e8a16000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a16000 0 0x1000>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 86 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO11>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio12: gpio@e8a17000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a17000 0 0x1000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO12>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio13: gpio@e8a18000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a18000 0 0x1000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 102 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO13>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio14: gpio@e8a19000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a19000 0 0x1000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 110 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO14>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio15: gpio@e8a1a000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a1a000 0 0x1000>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 118 6>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO15>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio16: gpio@e8a1b000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a1b000 0 0x1000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO16>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio17: gpio@e8a1c000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a1c000 0 0x1000>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO17>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio18: gpio@ff3b4000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xff3b4000 0 0x1000>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx2 0 0 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO18>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio19: gpio@ff3b5000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xff3b5000 0 0x1000>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx2 0 8 4>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO19>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio20: gpio@e8a1f000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a1f000 0 0x1000>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx1 0 0 6>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO20>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio21: gpio@e8a20000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a20000 0 0x1000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&pmx3 0 0 6>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO21>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio22: gpio@fff0b000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xfff0b000 0 0x1000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* GPIO176 */
+ gpio-ranges = <&pmx4 2 0 6>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&sctrl HI3660_PCLK_AO_GPIO0>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio23: gpio@fff0c000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xfff0c000 0 0x1000>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* GPIO184 */
+ gpio-ranges = <&pmx4 0 6 7>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&sctrl HI3660_PCLK_AO_GPIO1>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio24: gpio@fff0d000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xfff0d000 0 0x1000>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* GPIO192 */
+ gpio-ranges = <&pmx4 0 13 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&sctrl HI3660_PCLK_AO_GPIO2>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio25: gpio@fff0e000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xfff0e000 0 0x1000>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* GPIO200 */
+ gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&sctrl HI3660_PCLK_AO_GPIO3>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio26: gpio@fff0f000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xfff0f000 0 0x1000>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* GPIO208 */
+ gpio-ranges = <&pmx4 0 28 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&sctrl HI3660_PCLK_AO_GPIO4>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio27: gpio@fff10000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xfff10000 0 0x1000>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* GPIO216 */
+ gpio-ranges = <&pmx4 0 36 6>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&sctrl HI3660_PCLK_AO_GPIO5>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio28: gpio@fff1d000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xfff1d000 0 0x1000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&sctrl HI3660_PCLK_AO_GPIO6>;
+ clock-names = "apb_pclk";
+ };
+
+ spi2: spi@ffd68000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x0 0xffd68000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>;
+ clock-names = "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pmx_func>;
+ num-cs = <1>;
+ cs-gpios = <&gpio27 2 0>;
+ status = "disabled";
+ };
+
+ spi3: spi@ff3b3000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x0 0xff3b3000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>;
+ clock-names = "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi3_pmx_func>;
+ num-cs = <1>;
+ cs-gpios = <&gpio18 5 0>;
+ status = "disabled";
+ };
+
+ pcie@f4000000 {
+ compatible = "hisilicon,kirin960-pcie";
+ reg = <0x0 0xf4000000 0x0 0x1000>,
+ <0x0 0xff3fe000 0x0 0x1000>,
+ <0x0 0xf3f20000 0x0 0x40000>,
+ <0x0 0xf5000000 0x0 0x2000>;
+ reg-names = "dbi", "apb", "phy", "config";
+ bus-range = <0x0 0x1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x02000000 0x0 0x00000000
+ 0x0 0xf6000000
+ 0x0 0x02000000>;
+ num-lanes = <1>;
+ #interrupt-cells = <1>;
+ interrupts = <0 283 4>;
+ interrupt-names = "msi";
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <0x0 0 0 1
+ &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0 0 0 2
+ &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0 0 0 3
+ &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0 0 0 4
+ &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
+ <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
+ <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
+ <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
+ <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
+ clock-names = "pcie_phy_ref", "pcie_aux",
+ "pcie_apb_phy", "pcie_apb_sys",
+ "pcie_aclk";
+ reset-gpios = <&gpio11 1 0 >;
+ };
+
+ /* UFS */
+ ufs: ufs@ff3b0000 {
+ compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1";
+ /* 0: HCI standard */
+ /* 1: UFS SYS CTRL */
+ reg = <0x0 0xff3b0000 0x0 0x1000>,
+ <0x0 0xff3b1000 0x0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,
+ <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
+ clock-names = "ref_clk", "phy_clk";
+ freq-table-hz = <0 0>, <0 0>;
+ /* offset: 0x84; bit: 12 */
+ resets = <&crg_rst 0x84 12>;
+ reset-names = "rst";
+ };
+
+ /* SD */
+ dwmmc1: dwmmc1@ff37f000 {
+ compatible = "hisilicon,hi3660-dw-mshc";
+ reg = <0x0 0xff37f000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_SD>,
+ <&crg_ctrl HI3660_HCLK_GATE_SD>;
+ clock-names = "ciu", "biu";
+ clock-frequency = <3200000>;
+ resets = <&crg_rst 0x94 18>;
+ reset-names = "reset";
+ hisilicon,peripheral-syscon = <&sctrl>;
+ card-detect-delay = <200>;
+ status = "disabled";
+ };
+
+ /* SDIO */
+ dwmmc2: dwmmc2@ff3ff000 {
+ compatible = "hisilicon,hi3660-dw-mshc";
+ reg = <0x0 0xff3ff000 0x0 0x1000>;
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>,
+ <&crg_ctrl HI3660_HCLK_GATE_SDIO0>;
+ clock-names = "ciu", "biu";
+ resets = <&crg_rst 0x94 20>;
+ reset-names = "reset";
+ card-detect-delay = <200>;
+ status = "disabled";
+ };
+
+ watchdog0: watchdog@e8a06000 {
+ compatible = "arm,sp805-wdt", "arm,primecell";
+ reg = <0x0 0xe8a06000 0x0 0x1000>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_OSC32K>;
+ clock-names = "apb_pclk";
+ };
+
+ watchdog1: watchdog@e8a07000 {
+ compatible = "arm,sp805-wdt", "arm,primecell";
+ reg = <0x0 0xe8a07000 0x0 0x1000>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_OSC32K>;
+ clock-names = "apb_pclk";
+ };
+
+ tsensor: tsensor@fff30000 {
+ compatible = "hisilicon,hi3660-tsensor";
+ reg = <0x0 0xfff30000 0x0 0x1000>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+
+ cls0: cls0 {
+ polling-delay = <1000>;
+ polling-delay-passive = <100>;
+ sustainable-power = <4500>;
+
+ /* sensor ID */
+ thermal-sensors = <&tsensor 1>;
+
+ trips {
+ threshold: trip-point@0 {
+ temperature = <65000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ target: trip-point@1 {
+ temperature = <75000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&target>;
+ contribution = <1024>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&target>;
+ contribution = <512>;
+ cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/hikey960-pinctrl.dtsi b/arch/arm/dts/hikey960-pinctrl.dtsi
new file mode 100644
index 0000000..d11efc8
--- /dev/null
+++ b/arch/arm/dts/hikey960-pinctrl.dtsi
@@ -0,0 +1,1060 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * pinctrl dts fils for Hislicon HiKey960 development board
+ *
+ */
+
+#include <dt-bindings/pinctrl/hisi.h>
+
+/ {
+ soc {
+ /* [IOMG_000, IOMG_123] */
+ range: gpio-range {
+ #pinctrl-single,gpio-range-cells = <3>;
+ };
+
+ pmx0: pinmux@e896c000 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0xe896c000 0x0 0x1f0>;
+ #pinctrl-cells = <1>;
+ #gpio-range-cells = <0x3>;
+ pinctrl-single,register-width = <0x20>;
+ pinctrl-single,function-mask = <0x7>;
+ /* pin base, nr pins & gpio function */
+ pinctrl-single,gpio-range = <
+ &range 0 7 0
+ &range 8 116 0>;
+
+ pmu_pmx_func: pmu_pmx_func {
+ pinctrl-single,pins = <
+ 0x008 MUX_M1 /* PMU1_SSI */
+ 0x00c MUX_M1 /* PMU2_SSI */
+ 0x010 MUX_M1 /* PMU_CLKOUT */
+ 0x100 MUX_M1 /* PMU_HKADC_SSI */
+ >;
+ };
+
+ csi0_pwd_n_pmx_func: csi0_pwd_n_pmx_func {
+ pinctrl-single,pins = <
+ 0x044 MUX_M0 /* CSI0_PWD_N */
+ >;
+ };
+
+ csi1_pwd_n_pmx_func: csi1_pwd_n_pmx_func {
+ pinctrl-single,pins = <
+ 0x04c MUX_M0 /* CSI1_PWD_N */
+ >;
+ };
+
+ isp0_pmx_func: isp0_pmx_func {
+ pinctrl-single,pins = <
+ 0x058 MUX_M1 /* ISP_CLK0 */
+ 0x064 MUX_M1 /* ISP_SCL0 */
+ 0x068 MUX_M1 /* ISP_SDA0 */
+ >;
+ };
+
+ isp1_pmx_func: isp1_pmx_func {
+ pinctrl-single,pins = <
+ 0x05c MUX_M1 /* ISP_CLK1 */
+ 0x06c MUX_M1 /* ISP_SCL1 */
+ 0x070 MUX_M1 /* ISP_SDA1 */
+ >;
+ };
+
+ pwr_key_pmx_func: pwr_key_pmx_func {
+ pinctrl-single,pins = <
+ 0x080 MUX_M0 /* GPIO_034 */
+ >;
+ };
+
+ i2c3_pmx_func: i2c3_pmx_func {
+ pinctrl-single,pins = <
+ 0x02c MUX_M1 /* I2C3_SCL */
+ 0x030 MUX_M1 /* I2C3_SDA */
+ >;
+ };
+
+ i2c4_pmx_func: i2c4_pmx_func {
+ pinctrl-single,pins = <
+ 0x090 MUX_M1 /* I2C4_SCL */
+ 0x094 MUX_M1 /* I2C4_SDA */
+ >;
+ };
+
+ pcie_perstn_pmx_func: pcie_perstn_pmx_func {
+ pinctrl-single,pins = <
+ 0x15c MUX_M1 /* PCIE_PERST_N */
+ >;
+ };
+
+ usbhub5734_pmx_func: usbhub5734_pmx_func {
+ pinctrl-single,pins = <
+ 0x11c MUX_M0 /* GPIO_073 */
+ 0x120 MUX_M0 /* GPIO_074 */
+ >;
+ };
+
+ uart0_pmx_func: uart0_pmx_func {
+ pinctrl-single,pins = <
+ 0x0cc MUX_M2 /* UART0_RXD */
+ 0x0d0 MUX_M2 /* UART0_TXD */
+ >;
+ };
+
+ uart1_pmx_func: uart1_pmx_func {
+ pinctrl-single,pins = <
+ 0x0b0 MUX_M2 /* UART1_CTS_N */
+ 0x0b4 MUX_M2 /* UART1_RTS_N */
+ 0x0a8 MUX_M2 /* UART1_RXD */
+ 0x0ac MUX_M2 /* UART1_TXD */
+ >;
+ };
+
+ uart2_pmx_func: uart2_pmx_func {
+ pinctrl-single,pins = <
+ 0x0bc MUX_M2 /* UART2_CTS_N */
+ 0x0c0 MUX_M2 /* UART2_RTS_N */
+ 0x0c8 MUX_M2 /* UART2_RXD */
+ 0x0c4 MUX_M2 /* UART2_TXD */
+ >;
+ };
+
+ uart3_pmx_func: uart3_pmx_func {
+ pinctrl-single,pins = <
+ 0x0dc MUX_M1 /* UART3_CTS_N */
+ 0x0e0 MUX_M1 /* UART3_RTS_N */
+ 0x0e4 MUX_M1 /* UART3_RXD */
+ 0x0e8 MUX_M1 /* UART3_TXD */
+ >;
+ };
+
+ uart4_pmx_func: uart4_pmx_func {
+ pinctrl-single,pins = <
+ 0x0ec MUX_M1 /* UART4_CTS_N */
+ 0x0f0 MUX_M1 /* UART4_RTS_N */
+ 0x0f4 MUX_M1 /* UART4_RXD */
+ 0x0f8 MUX_M1 /* UART4_TXD */
+ >;
+ };
+
+ uart5_pmx_func: uart5_pmx_func {
+ pinctrl-single,pins = <
+ 0x0c4 MUX_M3 /* UART5_CTS_N */
+ 0x0c8 MUX_M3 /* UART5_RTS_N */
+ 0x0bc MUX_M3 /* UART5_RXD */
+ 0x0c0 MUX_M3 /* UART5_TXD */
+ >;
+ };
+
+ uart6_pmx_func: uart6_pmx_func {
+ pinctrl-single,pins = <
+ 0x0cc MUX_M1 /* UART6_CTS_N */
+ 0x0d0 MUX_M1 /* UART6_RTS_N */
+ 0x0d4 MUX_M1 /* UART6_RXD */
+ 0x0d8 MUX_M1 /* UART6_TXD */
+ >;
+ };
+
+ cam0_rst_pmx_func: cam0_rst_pmx_func {
+ pinctrl-single,pins = <
+ 0x0c8 MUX_M0 /* CAM0_RST */
+ >;
+ };
+
+ cam1_rst_pmx_func: cam1_rst_pmx_func {
+ pinctrl-single,pins = <
+ 0x124 MUX_M0 /* CAM1_RST */
+ >;
+ };
+ };
+
+ /* [IOMG_MMC0_000, IOMG_MMC0_005] */
+ pmx1: pinmux@ff37e000 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0xff37e000 0x0 0x18>;
+ #gpio-range-cells = <0x3>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <0x20>;
+ pinctrl-single,function-mask = <0x7>;
+ /* pin base, nr pins & gpio function */
+ pinctrl-single,gpio-range = <&range 0 6 0>;
+
+ sd_pmx_func: sd_pmx_func {
+ pinctrl-single,pins = <
+ 0x000 MUX_M1 /* SD_CLK */
+ 0x004 MUX_M1 /* SD_CMD */
+ 0x008 MUX_M1 /* SD_DATA0 */
+ 0x00c MUX_M1 /* SD_DATA1 */
+ 0x010 MUX_M1 /* SD_DATA2 */
+ 0x014 MUX_M1 /* SD_DATA3 */
+ >;
+ };
+ };
+
+ /* [IOMG_FIX_000, IOMG_FIX_011] */
+ pmx2: pinmux@ff3b6000 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0xff3b6000 0x0 0x30>;
+ #pinctrl-cells = <1>;
+ #gpio-range-cells = <0x3>;
+ pinctrl-single,register-width = <0x20>;
+ pinctrl-single,function-mask = <0x7>;
+ /* pin base, nr pins & gpio function */
+ pinctrl-single,gpio-range = <&range 0 12 0>;
+
+ ufs_pmx_func: ufs_pmx_func {
+ pinctrl-single,pins = <
+ 0x000 MUX_M1 /* UFS_REF_CLK */
+ 0x004 MUX_M1 /* UFS_RST_N */
+ >;
+ };
+
+ spi3_pmx_func: spi3_pmx_func {
+ pinctrl-single,pins = <
+ 0x008 MUX_M1 /* SPI3_CLK */
+ 0x00c MUX_M1 /* SPI3_DI */
+ 0x010 MUX_M1 /* SPI3_DO */
+ 0x014 MUX_M1 /* SPI3_CS0_N */
+ >;
+ };
+ };
+
+ /* [IOMG_MMC1_000, IOMG_MMC1_005] */
+ pmx3: pinmux@ff3fd000 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0xff3fd000 0x0 0x18>;
+ #pinctrl-cells = <1>;
+ #gpio-range-cells = <0x3>;
+ pinctrl-single,register-width = <0x20>;
+ pinctrl-single,function-mask = <0x7>;
+ /* pin base, nr pins & gpio function */
+ pinctrl-single,gpio-range = <&range 0 6 0>;
+
+ sdio_pmx_func: sdio_pmx_func {
+ pinctrl-single,pins = <
+ 0x000 MUX_M1 /* SDIO_CLK */
+ 0x004 MUX_M1 /* SDIO_CMD */
+ 0x008 MUX_M1 /* SDIO_DATA0 */
+ 0x00c MUX_M1 /* SDIO_DATA1 */
+ 0x010 MUX_M1 /* SDIO_DATA2 */
+ 0x014 MUX_M1 /* SDIO_DATA3 */
+ >;
+ };
+ };
+
+ /* [IOMG_AO_000, IOMG_AO_041] */
+ pmx4: pinmux@fff11000 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0xfff11000 0x0 0xa8>;
+ #pinctrl-cells = <1>;
+ #gpio-range-cells = <0x3>;
+ pinctrl-single,register-width = <0x20>;
+ pinctrl-single,function-mask = <0x7>;
+ /* pin base in node, nr pins & gpio function */
+ pinctrl-single,gpio-range = <&range 0 42 0>;
+
+ i2s2_pmx_func: i2s2_pmx_func {
+ pinctrl-single,pins = <
+ 0x044 MUX_M1 /* I2S2_DI */
+ 0x048 MUX_M1 /* I2S2_DO */
+ 0x04c MUX_M1 /* I2S2_XCLK */
+ 0x050 MUX_M1 /* I2S2_XFS */
+ >;
+ };
+
+ slimbus_pmx_func: slimbus_pmx_func {
+ pinctrl-single,pins = <
+ 0x02c MUX_M1 /* SLIMBUS_CLK */
+ 0x030 MUX_M1 /* SLIMBUS_DATA */
+ >;
+ };
+
+ i2c0_pmx_func: i2c0_pmx_func {
+ pinctrl-single,pins = <
+ 0x014 MUX_M1 /* I2C0_SCL */
+ 0x018 MUX_M1 /* I2C0_SDA */
+ >;
+ };
+
+ i2c1_pmx_func: i2c1_pmx_func {
+ pinctrl-single,pins = <
+ 0x01c MUX_M1 /* I2C1_SCL */
+ 0x020 MUX_M1 /* I2C1_SDA */
+ >;
+ };
+
+ i2c7_pmx_func: i2c7_pmx_func {
+ pinctrl-single,pins = <
+ 0x024 MUX_M3 /* I2C7_SCL */
+ 0x028 MUX_M3 /* I2C7_SDA */
+ >;
+ };
+
+ pcie_pmx_func: pcie_pmx_func {
+ pinctrl-single,pins = <
+ 0x084 MUX_M1 /* PCIE_CLKREQ_N */
+ 0x088 MUX_M1 /* PCIE_WAKE_N */
+ >;
+ };
+
+ spi2_pmx_func: spi2_pmx_func {
+ pinctrl-single,pins = <
+ 0x08c MUX_M1 /* SPI2_CLK */
+ 0x090 MUX_M1 /* SPI2_DI */
+ 0x094 MUX_M1 /* SPI2_DO */
+ 0x098 MUX_M1 /* SPI2_CS0_N */
+ >;
+ };
+
+ i2s0_pmx_func: i2s0_pmx_func {
+ pinctrl-single,pins = <
+ 0x034 MUX_M1 /* I2S0_DI */
+ 0x038 MUX_M1 /* I2S0_DO */
+ 0x03c MUX_M1 /* I2S0_XCLK */
+ 0x040 MUX_M1 /* I2S0_XFS */
+ >;
+ };
+ };
+
+ pmx5: pinmux@e896c800 {
+ compatible = "pinconf-single";
+ reg = <0x0 0xe896c800 0x0 0x200>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <0x20>;
+
+ pmu_cfg_func: pmu_cfg_func {
+ pinctrl-single,pins = <
+ 0x010 0x0 /* PMU1_SSI */
+ 0x014 0x0 /* PMU2_SSI */
+ 0x018 0x0 /* PMU_CLKOUT */
+ 0x10c 0x0 /* PMU_HKADC_SSI */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_06MA DRIVE6_MASK
+ >;
+ };
+
+ i2c3_cfg_func: i2c3_cfg_func {
+ pinctrl-single,pins = <
+ 0x038 0x0 /* I2C3_SCL */
+ 0x03c 0x0 /* I2C3_SDA */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ csi0_pwd_n_cfg_func: csi0_pwd_n_cfg_func {
+ pinctrl-single,pins = <
+ 0x050 0x0 /* CSI0_PWD_N */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_04MA DRIVE6_MASK
+ >;
+ };
+
+ csi1_pwd_n_cfg_func: csi1_pwd_n_cfg_func {
+ pinctrl-single,pins = <
+ 0x058 0x0 /* CSI1_PWD_N */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_04MA DRIVE6_MASK
+ >;
+ };
+
+ isp0_cfg_func: isp0_cfg_func {
+ pinctrl-single,pins = <
+ 0x064 0x0 /* ISP_CLK0 */
+ 0x070 0x0 /* ISP_SCL0 */
+ 0x074 0x0 /* ISP_SDA0 */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_04MA DRIVE6_MASK>;
+ };
+
+ isp1_cfg_func: isp1_cfg_func {
+ pinctrl-single,pins = <
+ 0x068 0x0 /* ISP_CLK1 */
+ 0x078 0x0 /* ISP_SCL1 */
+ 0x07c 0x0 /* ISP_SDA1 */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_04MA DRIVE6_MASK
+ >;
+ };
+
+ pwr_key_cfg_func: pwr_key_cfg_func {
+ pinctrl-single,pins = <
+ 0x08c 0x0 /* GPIO_034 */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ uart1_cfg_func: uart1_cfg_func {
+ pinctrl-single,pins = <
+ 0x0b4 0x0 /* UART1_RXD */
+ 0x0b8 0x0 /* UART1_TXD */
+ 0x0bc 0x0 /* UART1_CTS_N */
+ 0x0c0 0x0 /* UART1_RTS_N */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ uart2_cfg_func: uart2_cfg_func {
+ pinctrl-single,pins = <
+ 0x0c8 0x0 /* UART2_CTS_N */
+ 0x0cc 0x0 /* UART2_RTS_N */
+ 0x0d0 0x0 /* UART2_TXD */
+ 0x0d4 0x0 /* UART2_RXD */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ uart5_cfg_func: uart5_cfg_func {
+ pinctrl-single,pins = <
+ 0x0c8 0x0 /* UART5_RXD */
+ 0x0cc 0x0 /* UART5_TXD */
+ 0x0d0 0x0 /* UART5_CTS_N */
+ 0x0d4 0x0 /* UART5_RTS_N */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ cam0_rst_cfg_func: cam0_rst_cfg_func {
+ pinctrl-single,pins = <
+ 0x0d4 0x0 /* CAM0_RST */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_04MA DRIVE6_MASK
+ >;
+ };
+
+ uart0_cfg_func: uart0_cfg_func {
+ pinctrl-single,pins = <
+ 0x0d8 0x0 /* UART0_RXD */
+ 0x0dc 0x0 /* UART0_TXD */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ uart6_cfg_func: uart6_cfg_func {
+ pinctrl-single,pins = <
+ 0x0d8 0x0 /* UART6_CTS_N */
+ 0x0dc 0x0 /* UART6_RTS_N */
+ 0x0e0 0x0 /* UART6_RXD */
+ 0x0e4 0x0 /* UART6_TXD */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ uart3_cfg_func: uart3_cfg_func {
+ pinctrl-single,pins = <
+ 0x0e8 0x0 /* UART3_CTS_N */
+ 0x0ec 0x0 /* UART3_RTS_N */
+ 0x0f0 0x0 /* UART3_RXD */
+ 0x0f4 0x0 /* UART3_TXD */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ uart4_cfg_func: uart4_cfg_func {
+ pinctrl-single,pins = <
+ 0x0f8 0x0 /* UART4_CTS_N */
+ 0x0fc 0x0 /* UART4_RTS_N */
+ 0x100 0x0 /* UART4_RXD */
+ 0x104 0x0 /* UART4_TXD */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ cam1_rst_cfg_func: cam1_rst_cfg_func {
+ pinctrl-single,pins = <
+ 0x130 0x0 /* CAM1_RST */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_04MA DRIVE6_MASK
+ >;
+ };
+ };
+
+ pmx6: pinmux@ff3b6800 {
+ compatible = "pinconf-single";
+ reg = <0x0 0xff3b6800 0x0 0x18>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <0x20>;
+
+ ufs_cfg_func: ufs_cfg_func {
+ pinctrl-single,pins = <
+ 0x000 0x0 /* UFS_REF_CLK */
+ 0x004 0x0 /* UFS_RST_N */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_08MA DRIVE6_MASK
+ >;
+ };
+
+ spi3_cfg_func: spi3_cfg_func {
+ pinctrl-single,pins = <
+ 0x008 0x0 /* SPI3_CLK */
+ 0x0 /* SPI3_DI */
+ 0x010 0x0 /* SPI3_DO */
+ 0x014 0x0 /* SPI3_CS0_N */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+ };
+
+ pmx7: pinmux@ff3fd800 {
+ compatible = "pinconf-single";
+ reg = <0x0 0xff3fd800 0x0 0x18>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <0x20>;
+
+ sdio_clk_cfg_func: sdio_clk_cfg_func {
+ pinctrl-single,pins = <
+ 0x000 0x0 /* SDIO_CLK */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE6_32MA DRIVE6_MASK
+ >;
+ };
+
+ sdio_cfg_func: sdio_cfg_func {
+ pinctrl-single,pins = <
+ 0x004 0x0 /* SDIO_CMD */
+ 0x008 0x0 /* SDIO_DATA0 */
+ 0x00c 0x0 /* SDIO_DATA1 */
+ 0x010 0x0 /* SDIO_DATA2 */
+ 0x014 0x0 /* SDIO_DATA3 */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_UP
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE6_19MA DRIVE6_MASK
+ >;
+ };
+ };
+
+ pmx8: pinmux@ff37e800 {
+ compatible = "pinconf-single";
+ reg = <0x0 0xff37e800 0x0 0x18>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <0x20>;
+
+ sd_clk_cfg_func: sd_clk_cfg_func {
+ pinctrl-single,pins = <
+ 0x000 0x0 /* SD_CLK */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE6_32MA
+ DRIVE6_MASK
+ >;
+ };
+
+ sd_cfg_func: sd_cfg_func {
+ pinctrl-single,pins = <
+ 0x004 0x0 /* SD_CMD */
+ 0x008 0x0 /* SD_DATA0 */
+ 0x00c 0x0 /* SD_DATA1 */
+ 0x010 0x0 /* SD_DATA2 */
+ 0x014 0x0 /* SD_DATA3 */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_UP
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE6_19MA
+ DRIVE6_MASK
+ >;
+ };
+ };
+
+ pmx9: pinmux@fff11800 {
+ compatible = "pinconf-single";
+ reg = <0x0 0xfff11800 0x0 0xbc>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <0x20>;
+
+ i2c0_cfg_func: i2c0_cfg_func {
+ pinctrl-single,pins = <
+ 0x01c 0x0 /* I2C0_SCL */
+ 0x020 0x0 /* I2C0_SDA */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_UP
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ i2c1_cfg_func: i2c1_cfg_func {
+ pinctrl-single,pins = <
+ 0x024 0x0 /* I2C1_SCL */
+ 0x028 0x0 /* I2C1_SDA */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_UP
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ i2c7_cfg_func: i2c7_cfg_func {
+ pinctrl-single,pins = <
+ 0x02c 0x0 /* I2C7_SCL */
+ 0x030 0x0 /* I2C7_SDA */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_UP
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ slimbus_cfg_func: slimbus_cfg_func {
+ pinctrl-single,pins = <
+ 0x034 0x0 /* SLIMBUS_CLK */
+ 0x038 0x0 /* SLIMBUS_DATA */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_UP
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ i2s0_cfg_func: i2s0_cfg_func {
+ pinctrl-single,pins = <
+ 0x040 0x0 /* I2S0_DI */
+ 0x044 0x0 /* I2S0_DO */
+ 0x048 0x0 /* I2S0_XCLK */
+ 0x04c 0x0 /* I2S0_XFS */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_UP
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ i2s2_cfg_func: i2s2_cfg_func {
+ pinctrl-single,pins = <
+ 0x050 0x0 /* I2S2_DI */
+ 0x054 0x0 /* I2S2_DO */
+ 0x058 0x0 /* I2S2_XCLK */
+ 0x05c 0x0 /* I2S2_XFS */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_UP
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ pcie_cfg_func: pcie_cfg_func {
+ pinctrl-single,pins = <
+ 0x094 0x0 /* PCIE_CLKREQ_N */
+ 0x098 0x0 /* PCIE_WAKE_N */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_UP
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ spi2_cfg_func: spi2_cfg_func {
+ pinctrl-single,pins = <
+ 0x09c 0x0 /* SPI2_CLK */
+ 0x0a0 0x0 /* SPI2_DI */
+ 0x0a4 0x0 /* SPI2_DO */
+ 0x0a8 0x0 /* SPI2_CS0_N */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_UP
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ usb_cfg_func: usb_cfg_func {
+ pinctrl-single,pins = <
+ 0x0ac 0x0 /* GPIO_219 */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_UP
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/imx28-pinfunc.h b/arch/arm/dts/imx28-pinfunc.h
new file mode 100644
index 0000000..e11f69b
--- /dev/null
+++ b/arch/arm/dts/imx28-pinfunc.h
@@ -0,0 +1,506 @@
+/*
+ * Header providing constants for i.MX28 pinctrl bindings.
+ *
+ * Copyright (C) 2013 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __DT_BINDINGS_MX28_PINCTRL_H__
+#define __DT_BINDINGS_MX28_PINCTRL_H__
+
+#include "mxs-pinfunc.h"
+
+#define MX28_PAD_GPMI_D00__GPMI_D0 0x0000
+#define MX28_PAD_GPMI_D01__GPMI_D1 0x0010
+#define MX28_PAD_GPMI_D02__GPMI_D2 0x0020
+#define MX28_PAD_GPMI_D03__GPMI_D3 0x0030
+#define MX28_PAD_GPMI_D04__GPMI_D4 0x0040
+#define MX28_PAD_GPMI_D05__GPMI_D5 0x0050
+#define MX28_PAD_GPMI_D06__GPMI_D6 0x0060
+#define MX28_PAD_GPMI_D07__GPMI_D7 0x0070
+#define MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100
+#define MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110
+#define MX28_PAD_GPMI_CE2N__GPMI_CE2N 0x0120
+#define MX28_PAD_GPMI_CE3N__GPMI_CE3N 0x0130
+#define MX28_PAD_GPMI_RDY0__GPMI_READY0 0x0140
+#define MX28_PAD_GPMI_RDY1__GPMI_READY1 0x0150
+#define MX28_PAD_GPMI_RDY2__GPMI_READY2 0x0160
+#define MX28_PAD_GPMI_RDY3__GPMI_READY3 0x0170
+#define MX28_PAD_GPMI_RDN__GPMI_RDN 0x0180
+#define MX28_PAD_GPMI_WRN__GPMI_WRN 0x0190
+#define MX28_PAD_GPMI_ALE__GPMI_ALE 0x01a0
+#define MX28_PAD_GPMI_CLE__GPMI_CLE 0x01b0
+#define MX28_PAD_GPMI_RESETN__GPMI_RESETN 0x01c0
+#define MX28_PAD_LCD_D00__LCD_D0 0x1000
+#define MX28_PAD_LCD_D01__LCD_D1 0x1010
+#define MX28_PAD_LCD_D02__LCD_D2 0x1020
+#define MX28_PAD_LCD_D03__LCD_D3 0x1030
+#define MX28_PAD_LCD_D04__LCD_D4 0x1040
+#define MX28_PAD_LCD_D05__LCD_D5 0x1050
+#define MX28_PAD_LCD_D06__LCD_D6 0x1060
+#define MX28_PAD_LCD_D07__LCD_D7 0x1070
+#define MX28_PAD_LCD_D08__LCD_D8 0x1080
+#define MX28_PAD_LCD_D09__LCD_D9 0x1090
+#define MX28_PAD_LCD_D10__LCD_D10 0x10a0
+#define MX28_PAD_LCD_D11__LCD_D11 0x10b0
+#define MX28_PAD_LCD_D12__LCD_D12 0x10c0
+#define MX28_PAD_LCD_D13__LCD_D13 0x10d0
+#define MX28_PAD_LCD_D14__LCD_D14 0x10e0
+#define MX28_PAD_LCD_D15__LCD_D15 0x10f0
+#define MX28_PAD_LCD_D16__LCD_D16 0x1100
+#define MX28_PAD_LCD_D17__LCD_D17 0x1110
+#define MX28_PAD_LCD_D18__LCD_D18 0x1120
+#define MX28_PAD_LCD_D19__LCD_D19 0x1130
+#define MX28_PAD_LCD_D20__LCD_D20 0x1140
+#define MX28_PAD_LCD_D21__LCD_D21 0x1150
+#define MX28_PAD_LCD_D22__LCD_D22 0x1160
+#define MX28_PAD_LCD_D23__LCD_D23 0x1170
+#define MX28_PAD_LCD_RD_E__LCD_RD_E 0x1180
+#define MX28_PAD_LCD_WR_RWN__LCD_WR_RWN 0x1190
+#define MX28_PAD_LCD_RS__LCD_RS 0x11a0
+#define MX28_PAD_LCD_CS__LCD_CS 0x11b0
+#define MX28_PAD_LCD_VSYNC__LCD_VSYNC 0x11c0
+#define MX28_PAD_LCD_HSYNC__LCD_HSYNC 0x11d0
+#define MX28_PAD_LCD_DOTCLK__LCD_DOTCLK 0x11e0
+#define MX28_PAD_LCD_ENABLE__LCD_ENABLE 0x11f0
+#define MX28_PAD_SSP0_DATA0__SSP0_D0 0x2000
+#define MX28_PAD_SSP0_DATA1__SSP0_D1 0x2010
+#define MX28_PAD_SSP0_DATA2__SSP0_D2 0x2020
+#define MX28_PAD_SSP0_DATA3__SSP0_D3 0x2030
+#define MX28_PAD_SSP0_DATA4__SSP0_D4 0x2040
+#define MX28_PAD_SSP0_DATA5__SSP0_D5 0x2050
+#define MX28_PAD_SSP0_DATA6__SSP0_D6 0x2060
+#define MX28_PAD_SSP0_DATA7__SSP0_D7 0x2070
+#define MX28_PAD_SSP0_CMD__SSP0_CMD 0x2080
+#define MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT 0x2090
+#define MX28_PAD_SSP0_SCK__SSP0_SCK 0x20a0
+#define MX28_PAD_SSP1_SCK__SSP1_SCK 0x20c0
+#define MX28_PAD_SSP1_CMD__SSP1_CMD 0x20d0
+#define MX28_PAD_SSP1_DATA0__SSP1_D0 0x20e0
+#define MX28_PAD_SSP1_DATA3__SSP1_D3 0x20f0
+#define MX28_PAD_SSP2_SCK__SSP2_SCK 0x2100
+#define MX28_PAD_SSP2_MOSI__SSP2_CMD 0x2110
+#define MX28_PAD_SSP2_MISO__SSP2_D0 0x2120
+#define MX28_PAD_SSP2_SS0__SSP2_D3 0x2130
+#define MX28_PAD_SSP2_SS1__SSP2_D4 0x2140
+#define MX28_PAD_SSP2_SS2__SSP2_D5 0x2150
+#define MX28_PAD_SSP3_SCK__SSP3_SCK 0x2180
+#define MX28_PAD_SSP3_MOSI__SSP3_CMD 0x2190
+#define MX28_PAD_SSP3_MISO__SSP3_D0 0x21a0
+#define MX28_PAD_SSP3_SS0__SSP3_D3 0x21b0
+#define MX28_PAD_AUART0_RX__AUART0_RX 0x3000
+#define MX28_PAD_AUART0_TX__AUART0_TX 0x3010
+#define MX28_PAD_AUART0_CTS__AUART0_CTS 0x3020
+#define MX28_PAD_AUART0_RTS__AUART0_RTS 0x3030
+#define MX28_PAD_AUART1_RX__AUART1_RX 0x3040
+#define MX28_PAD_AUART1_TX__AUART1_TX 0x3050
+#define MX28_PAD_AUART1_CTS__AUART1_CTS 0x3060
+#define MX28_PAD_AUART1_RTS__AUART1_RTS 0x3070
+#define MX28_PAD_AUART2_RX__AUART2_RX 0x3080
+#define MX28_PAD_AUART2_TX__AUART2_TX 0x3090
+#define MX28_PAD_AUART2_CTS__AUART2_CTS 0x30a0
+#define MX28_PAD_AUART2_RTS__AUART2_RTS 0x30b0
+#define MX28_PAD_AUART3_RX__AUART3_RX 0x30c0
+#define MX28_PAD_AUART3_TX__AUART3_TX 0x30d0
+#define MX28_PAD_AUART3_CTS__AUART3_CTS 0x30e0
+#define MX28_PAD_AUART3_RTS__AUART3_RTS 0x30f0
+#define MX28_PAD_PWM0__PWM_0 0x3100
+#define MX28_PAD_PWM1__PWM_1 0x3110
+#define MX28_PAD_PWM2__PWM_2 0x3120
+#define MX28_PAD_SAIF0_MCLK__SAIF0_MCLK 0x3140
+#define MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK 0x3150
+#define MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK 0x3160
+#define MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 0x3170
+#define MX28_PAD_I2C0_SCL__I2C0_SCL 0x3180
+#define MX28_PAD_I2C0_SDA__I2C0_SDA 0x3190
+#define MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 0x31a0
+#define MX28_PAD_SPDIF__SPDIF_TX 0x31b0
+#define MX28_PAD_PWM3__PWM_3 0x31c0
+#define MX28_PAD_PWM4__PWM_4 0x31d0
+#define MX28_PAD_LCD_RESET__LCD_RESET 0x31e0
+#define MX28_PAD_ENET0_MDC__ENET0_MDC 0x4000
+#define MX28_PAD_ENET0_MDIO__ENET0_MDIO 0x4010
+#define MX28_PAD_ENET0_RX_EN__ENET0_RX_EN 0x4020
+#define MX28_PAD_ENET0_RXD0__ENET0_RXD0 0x4030
+#define MX28_PAD_ENET0_RXD1__ENET0_RXD1 0x4040
+#define MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK 0x4050
+#define MX28_PAD_ENET0_TX_EN__ENET0_TX_EN 0x4060
+#define MX28_PAD_ENET0_TXD0__ENET0_TXD0 0x4070
+#define MX28_PAD_ENET0_TXD1__ENET0_TXD1 0x4080
+#define MX28_PAD_ENET0_RXD2__ENET0_RXD2 0x4090
+#define MX28_PAD_ENET0_RXD3__ENET0_RXD3 0x40a0
+#define MX28_PAD_ENET0_TXD2__ENET0_TXD2 0x40b0
+#define MX28_PAD_ENET0_TXD3__ENET0_TXD3 0x40c0
+#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK 0x40d0
+#define MX28_PAD_ENET0_COL__ENET0_COL 0x40e0
+#define MX28_PAD_ENET0_CRS__ENET0_CRS 0x40f0
+#define MX28_PAD_ENET_CLK__CLKCTRL_ENET 0x4100
+#define MX28_PAD_JTAG_RTCK__JTAG_RTCK 0x4140
+#define MX28_PAD_EMI_D00__EMI_DATA0 0x5000
+#define MX28_PAD_EMI_D01__EMI_DATA1 0x5010
+#define MX28_PAD_EMI_D02__EMI_DATA2 0x5020
+#define MX28_PAD_EMI_D03__EMI_DATA3 0x5030
+#define MX28_PAD_EMI_D04__EMI_DATA4 0x5040
+#define MX28_PAD_EMI_D05__EMI_DATA5 0x5050
+#define MX28_PAD_EMI_D06__EMI_DATA6 0x5060
+#define MX28_PAD_EMI_D07__EMI_DATA7 0x5070
+#define MX28_PAD_EMI_D08__EMI_DATA8 0x5080
+#define MX28_PAD_EMI_D09__EMI_DATA9 0x5090
+#define MX28_PAD_EMI_D10__EMI_DATA10 0x50a0
+#define MX28_PAD_EMI_D11__EMI_DATA11 0x50b0
+#define MX28_PAD_EMI_D12__EMI_DATA12 0x50c0
+#define MX28_PAD_EMI_D13__EMI_DATA13 0x50d0
+#define MX28_PAD_EMI_D14__EMI_DATA14 0x50e0
+#define MX28_PAD_EMI_D15__EMI_DATA15 0x50f0
+#define MX28_PAD_EMI_ODT0__EMI_ODT0 0x5100
+#define MX28_PAD_EMI_DQM0__EMI_DQM0 0x5110
+#define MX28_PAD_EMI_ODT1__EMI_ODT1 0x5120
+#define MX28_PAD_EMI_DQM1__EMI_DQM1 0x5130
+#define MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK 0x5140
+#define MX28_PAD_EMI_CLK__EMI_CLK 0x5150
+#define MX28_PAD_EMI_DQS0__EMI_DQS0 0x5160
+#define MX28_PAD_EMI_DQS1__EMI_DQS1 0x5170
+#define MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN 0x51a0
+#define MX28_PAD_EMI_A00__EMI_ADDR0 0x6000
+#define MX28_PAD_EMI_A01__EMI_ADDR1 0x6010
+#define MX28_PAD_EMI_A02__EMI_ADDR2 0x6020
+#define MX28_PAD_EMI_A03__EMI_ADDR3 0x6030
+#define MX28_PAD_EMI_A04__EMI_ADDR4 0x6040
+#define MX28_PAD_EMI_A05__EMI_ADDR5 0x6050
+#define MX28_PAD_EMI_A06__EMI_ADDR6 0x6060
+#define MX28_PAD_EMI_A07__EMI_ADDR7 0x6070
+#define MX28_PAD_EMI_A08__EMI_ADDR8 0x6080
+#define MX28_PAD_EMI_A09__EMI_ADDR9 0x6090
+#define MX28_PAD_EMI_A10__EMI_ADDR10 0x60a0
+#define MX28_PAD_EMI_A11__EMI_ADDR11 0x60b0
+#define MX28_PAD_EMI_A12__EMI_ADDR12 0x60c0
+#define MX28_PAD_EMI_A13__EMI_ADDR13 0x60d0
+#define MX28_PAD_EMI_A14__EMI_ADDR14 0x60e0
+#define MX28_PAD_EMI_BA0__EMI_BA0 0x6100
+#define MX28_PAD_EMI_BA1__EMI_BA1 0x6110
+#define MX28_PAD_EMI_BA2__EMI_BA2 0x6120
+#define MX28_PAD_EMI_CASN__EMI_CASN 0x6130
+#define MX28_PAD_EMI_RASN__EMI_RASN 0x6140
+#define MX28_PAD_EMI_WEN__EMI_WEN 0x6150
+#define MX28_PAD_EMI_CE0N__EMI_CE0N 0x6160
+#define MX28_PAD_EMI_CE1N__EMI_CE1N 0x6170
+#define MX28_PAD_EMI_CKE__EMI_CKE 0x6180
+#define MX28_PAD_GPMI_D00__SSP1_D0 0x0001
+#define MX28_PAD_GPMI_D01__SSP1_D1 0x0011
+#define MX28_PAD_GPMI_D02__SSP1_D2 0x0021
+#define MX28_PAD_GPMI_D03__SSP1_D3 0x0031
+#define MX28_PAD_GPMI_D04__SSP1_D4 0x0041
+#define MX28_PAD_GPMI_D05__SSP1_D5 0x0051
+#define MX28_PAD_GPMI_D06__SSP1_D6 0x0061
+#define MX28_PAD_GPMI_D07__SSP1_D7 0x0071
+#define MX28_PAD_GPMI_CE0N__SSP3_D0 0x0101
+#define MX28_PAD_GPMI_CE1N__SSP3_D3 0x0111
+#define MX28_PAD_GPMI_CE2N__CAN1_TX 0x0121
+#define MX28_PAD_GPMI_CE3N__CAN1_RX 0x0131
+#define MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT 0x0141
+#define MX28_PAD_GPMI_RDY1__SSP1_CMD 0x0151
+#define MX28_PAD_GPMI_RDY2__CAN0_TX 0x0161
+#define MX28_PAD_GPMI_RDY3__CAN0_RX 0x0171
+#define MX28_PAD_GPMI_RDN__SSP3_SCK 0x0181
+#define MX28_PAD_GPMI_WRN__SSP1_SCK 0x0191
+#define MX28_PAD_GPMI_ALE__SSP3_D1 0x01a1
+#define MX28_PAD_GPMI_CLE__SSP3_D2 0x01b1
+#define MX28_PAD_GPMI_RESETN__SSP3_CMD 0x01c1
+#define MX28_PAD_LCD_D03__ETM_DA8 0x1031
+#define MX28_PAD_LCD_D04__ETM_DA9 0x1041
+#define MX28_PAD_LCD_D08__ETM_DA3 0x1081
+#define MX28_PAD_LCD_D09__ETM_DA4 0x1091
+#define MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT 0x1141
+#define MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN 0x1151
+#define MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT 0x1161
+#define MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN 0x1171
+#define MX28_PAD_LCD_RD_E__LCD_VSYNC 0x1181
+#define MX28_PAD_LCD_WR_RWN__LCD_HSYNC 0x1191
+#define MX28_PAD_LCD_RS__LCD_DOTCLK 0x11a1
+#define MX28_PAD_LCD_CS__LCD_ENABLE 0x11b1
+#define MX28_PAD_LCD_VSYNC__SAIF1_SDATA0 0x11c1
+#define MX28_PAD_LCD_HSYNC__SAIF1_SDATA1 0x11d1
+#define MX28_PAD_LCD_DOTCLK__SAIF1_MCLK 0x11e1
+#define MX28_PAD_SSP0_DATA4__SSP2_D0 0x2041
+#define MX28_PAD_SSP0_DATA5__SSP2_D3 0x2051
+#define MX28_PAD_SSP0_DATA6__SSP2_CMD 0x2061
+#define MX28_PAD_SSP0_DATA7__SSP2_SCK 0x2071
+#define MX28_PAD_SSP1_SCK__SSP2_D1 0x20c1
+#define MX28_PAD_SSP1_CMD__SSP2_D2 0x20d1
+#define MX28_PAD_SSP1_DATA0__SSP2_D6 0x20e1
+#define MX28_PAD_SSP1_DATA3__SSP2_D7 0x20f1
+#define MX28_PAD_SSP2_SCK__AUART2_RX 0x2101
+#define MX28_PAD_SSP2_MOSI__AUART2_TX 0x2111
+#define MX28_PAD_SSP2_MISO__AUART3_RX 0x2121
+#define MX28_PAD_SSP2_SS0__AUART3_TX 0x2131
+#define MX28_PAD_SSP2_SS1__SSP2_D1 0x2141
+#define MX28_PAD_SSP2_SS2__SSP2_D2 0x2151
+#define MX28_PAD_SSP3_SCK__AUART4_TX 0x2181
+#define MX28_PAD_SSP3_MOSI__AUART4_RX 0x2191
+#define MX28_PAD_SSP3_MISO__AUART4_RTS 0x21a1
+#define MX28_PAD_SSP3_SS0__AUART4_CTS 0x21b1
+#define MX28_PAD_AUART0_RX__I2C0_SCL 0x3001
+#define MX28_PAD_AUART0_TX__I2C0_SDA 0x3011
+#define MX28_PAD_AUART0_CTS__AUART4_RX 0x3021
+#define MX28_PAD_AUART0_RTS__AUART4_TX 0x3031
+#define MX28_PAD_AUART1_RX__SSP2_CARD_DETECT 0x3041
+#define MX28_PAD_AUART1_TX__SSP3_CARD_DETECT 0x3051
+#define MX28_PAD_AUART1_CTS__USB0_OVERCURRENT 0x3061
+#define MX28_PAD_AUART1_RTS__USB0_ID 0x3071
+#define MX28_PAD_AUART2_RX__SSP3_D1 0x3081
+#define MX28_PAD_AUART2_TX__SSP3_D2 0x3091
+#define MX28_PAD_AUART2_CTS__I2C1_SCL 0x30a1
+#define MX28_PAD_AUART2_RTS__I2C1_SDA 0x30b1
+#define MX28_PAD_AUART3_RX__CAN0_TX 0x30c1
+#define MX28_PAD_AUART3_TX__CAN0_RX 0x30d1
+#define MX28_PAD_AUART3_CTS__CAN1_TX 0x30e1
+#define MX28_PAD_AUART3_RTS__CAN1_RX 0x30f1
+#define MX28_PAD_PWM0__I2C1_SCL 0x3101
+#define MX28_PAD_PWM1__I2C1_SDA 0x3111
+#define MX28_PAD_PWM2__USB0_ID 0x3121
+#define MX28_PAD_SAIF0_MCLK__PWM_3 0x3141
+#define MX28_PAD_SAIF0_LRCLK__PWM_4 0x3151
+#define MX28_PAD_SAIF0_BITCLK__PWM_5 0x3161
+#define MX28_PAD_SAIF0_SDATA0__PWM_6 0x3171
+#define MX28_PAD_I2C0_SCL__TIMROT_ROTARYA 0x3181
+#define MX28_PAD_I2C0_SDA__TIMROT_ROTARYB 0x3191
+#define MX28_PAD_SAIF1_SDATA0__PWM_7 0x31a1
+#define MX28_PAD_LCD_RESET__LCD_VSYNC 0x31e1
+#define MX28_PAD_ENET0_MDC__GPMI_CE4N 0x4001
+#define MX28_PAD_ENET0_MDIO__GPMI_CE5N 0x4011
+#define MX28_PAD_ENET0_RX_EN__GPMI_CE6N 0x4021
+#define MX28_PAD_ENET0_RXD0__GPMI_CE7N 0x4031
+#define MX28_PAD_ENET0_RXD1__GPMI_READY4 0x4041
+#define MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER 0x4051
+#define MX28_PAD_ENET0_TX_EN__GPMI_READY5 0x4061
+#define MX28_PAD_ENET0_TXD0__GPMI_READY6 0x4071
+#define MX28_PAD_ENET0_TXD1__GPMI_READY7 0x4081
+#define MX28_PAD_ENET0_RXD2__ENET1_RXD0 0x4091
+#define MX28_PAD_ENET0_RXD3__ENET1_RXD1 0x40a1
+#define MX28_PAD_ENET0_TXD2__ENET1_TXD0 0x40b1
+#define MX28_PAD_ENET0_TXD3__ENET1_TXD1 0x40c1
+#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER 0x40d1
+#define MX28_PAD_ENET0_COL__ENET1_TX_EN 0x40e1
+#define MX28_PAD_ENET0_CRS__ENET1_RX_EN 0x40f1
+#define MX28_PAD_GPMI_CE2N__ENET0_RX_ER 0x0122
+#define MX28_PAD_GPMI_CE3N__SAIF1_MCLK 0x0132
+#define MX28_PAD_GPMI_RDY0__USB0_ID 0x0142
+#define MX28_PAD_GPMI_RDY2__ENET0_TX_ER 0x0162
+#define MX28_PAD_GPMI_RDY3__HSADC_TRIGGER 0x0172
+#define MX28_PAD_GPMI_ALE__SSP3_D4 0x01a2
+#define MX28_PAD_GPMI_CLE__SSP3_D5 0x01b2
+#define MX28_PAD_LCD_D00__ETM_DA0 0x1002
+#define MX28_PAD_LCD_D01__ETM_DA1 0x1012
+#define MX28_PAD_LCD_D02__ETM_DA2 0x1022
+#define MX28_PAD_LCD_D03__ETM_DA3 0x1032
+#define MX28_PAD_LCD_D04__ETM_DA4 0x1042
+#define MX28_PAD_LCD_D05__ETM_DA5 0x1052
+#define MX28_PAD_LCD_D06__ETM_DA6 0x1062
+#define MX28_PAD_LCD_D07__ETM_DA7 0x1072
+#define MX28_PAD_LCD_D08__ETM_DA8 0x1082
+#define MX28_PAD_LCD_D09__ETM_DA9 0x1092
+#define MX28_PAD_LCD_D10__ETM_DA10 0x10a2
+#define MX28_PAD_LCD_D11__ETM_DA11 0x10b2
+#define MX28_PAD_LCD_D12__ETM_DA12 0x10c2
+#define MX28_PAD_LCD_D13__ETM_DA13 0x10d2
+#define MX28_PAD_LCD_D14__ETM_DA14 0x10e2
+#define MX28_PAD_LCD_D15__ETM_DA15 0x10f2
+#define MX28_PAD_LCD_D16__ETM_DA7 0x1102
+#define MX28_PAD_LCD_D17__ETM_DA6 0x1112
+#define MX28_PAD_LCD_D18__ETM_DA5 0x1122
+#define MX28_PAD_LCD_D19__ETM_DA4 0x1132
+#define MX28_PAD_LCD_D20__ETM_DA3 0x1142
+#define MX28_PAD_LCD_D21__ETM_DA2 0x1152
+#define MX28_PAD_LCD_D22__ETM_DA1 0x1162
+#define MX28_PAD_LCD_D23__ETM_DA0 0x1172
+#define MX28_PAD_LCD_RD_E__ETM_TCTL 0x1182
+#define MX28_PAD_LCD_WR_RWN__ETM_TCLK 0x1192
+#define MX28_PAD_LCD_HSYNC__ETM_TCTL 0x11d2
+#define MX28_PAD_LCD_DOTCLK__ETM_TCLK 0x11e2
+#define MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT 0x20c2
+#define MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN 0x20d2
+#define MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT 0x20e2
+#define MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN 0x20f2
+#define MX28_PAD_SSP2_SCK__SAIF0_SDATA1 0x2102
+#define MX28_PAD_SSP2_MOSI__SAIF0_SDATA2 0x2112
+#define MX28_PAD_SSP2_MISO__SAIF1_SDATA1 0x2122
+#define MX28_PAD_SSP2_SS0__SAIF1_SDATA2 0x2132
+#define MX28_PAD_SSP2_SS1__USB1_OVERCURRENT 0x2142
+#define MX28_PAD_SSP2_SS2__USB0_OVERCURRENT 0x2152
+#define MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT 0x2182
+#define MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN 0x2192
+#define MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT 0x21a2
+#define MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN 0x21b2
+#define MX28_PAD_AUART0_RX__DUART_CTS 0x3002
+#define MX28_PAD_AUART0_TX__DUART_RTS 0x3012
+#define MX28_PAD_AUART0_CTS__DUART_RX 0x3022
+#define MX28_PAD_AUART0_RTS__DUART_TX 0x3032
+#define MX28_PAD_AUART1_RX__PWM_0 0x3042
+#define MX28_PAD_AUART1_TX__PWM_1 0x3052
+#define MX28_PAD_AUART1_CTS__TIMROT_ROTARYA 0x3062
+#define MX28_PAD_AUART1_RTS__TIMROT_ROTARYB 0x3072
+#define MX28_PAD_AUART2_RX__SSP3_D4 0x3082
+#define MX28_PAD_AUART2_TX__SSP3_D5 0x3092
+#define MX28_PAD_AUART2_CTS__SAIF1_BITCLK 0x30a2
+#define MX28_PAD_AUART2_RTS__SAIF1_LRCLK 0x30b2
+#define MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT 0x30c2
+#define MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN 0x30d2
+#define MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT 0x30e2
+#define MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN 0x30f2
+#define MX28_PAD_PWM0__DUART_RX 0x3102
+#define MX28_PAD_PWM1__DUART_TX 0x3112
+#define MX28_PAD_PWM2__USB1_OVERCURRENT 0x3122
+#define MX28_PAD_SAIF0_MCLK__AUART4_CTS 0x3142
+#define MX28_PAD_SAIF0_LRCLK__AUART4_RTS 0x3152
+#define MX28_PAD_SAIF0_BITCLK__AUART4_RX 0x3162
+#define MX28_PAD_SAIF0_SDATA0__AUART4_TX 0x3172
+#define MX28_PAD_I2C0_SCL__DUART_RX 0x3182
+#define MX28_PAD_I2C0_SDA__DUART_TX 0x3192
+#define MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1 0x31a2
+#define MX28_PAD_SPDIF__ENET1_RX_ER 0x31b2
+#define MX28_PAD_ENET0_MDC__SAIF0_SDATA1 0x4002
+#define MX28_PAD_ENET0_MDIO__SAIF0_SDATA2 0x4012
+#define MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1 0x4022
+#define MX28_PAD_ENET0_RXD0__SAIF1_SDATA2 0x4032
+#define MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT 0x4052
+#define MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT 0x4092
+#define MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN 0x40a2
+#define MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT 0x40b2
+#define MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN 0x40c2
+#define MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN 0x40d2
+#define MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT 0x40e2
+#define MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN 0x40f2
+#define MX28_PAD_GPMI_D00__GPIO_0_0 0x0003
+#define MX28_PAD_GPMI_D01__GPIO_0_1 0x0013
+#define MX28_PAD_GPMI_D02__GPIO_0_2 0x0023
+#define MX28_PAD_GPMI_D03__GPIO_0_3 0x0033
+#define MX28_PAD_GPMI_D04__GPIO_0_4 0x0043
+#define MX28_PAD_GPMI_D05__GPIO_0_5 0x0053
+#define MX28_PAD_GPMI_D06__GPIO_0_6 0x0063
+#define MX28_PAD_GPMI_D07__GPIO_0_7 0x0073
+#define MX28_PAD_GPMI_CE0N__GPIO_0_16 0x0103
+#define MX28_PAD_GPMI_CE1N__GPIO_0_17 0x0113
+#define MX28_PAD_GPMI_CE2N__GPIO_0_18 0x0123
+#define MX28_PAD_GPMI_CE3N__GPIO_0_19 0x0133
+#define MX28_PAD_GPMI_RDY0__GPIO_0_20 0x0143
+#define MX28_PAD_GPMI_RDY1__GPIO_0_21 0x0153
+#define MX28_PAD_GPMI_RDY2__GPIO_0_22 0x0163
+#define MX28_PAD_GPMI_RDY3__GPIO_0_23 0x0173
+#define MX28_PAD_GPMI_RDN__GPIO_0_24 0x0183
+#define MX28_PAD_GPMI_WRN__GPIO_0_25 0x0193
+#define MX28_PAD_GPMI_ALE__GPIO_0_26 0x01a3
+#define MX28_PAD_GPMI_CLE__GPIO_0_27 0x01b3
+#define MX28_PAD_GPMI_RESETN__GPIO_0_28 0x01c3
+#define MX28_PAD_LCD_D00__GPIO_1_0 0x1003
+#define MX28_PAD_LCD_D01__GPIO_1_1 0x1013
+#define MX28_PAD_LCD_D02__GPIO_1_2 0x1023
+#define MX28_PAD_LCD_D03__GPIO_1_3 0x1033
+#define MX28_PAD_LCD_D04__GPIO_1_4 0x1043
+#define MX28_PAD_LCD_D05__GPIO_1_5 0x1053
+#define MX28_PAD_LCD_D06__GPIO_1_6 0x1063
+#define MX28_PAD_LCD_D07__GPIO_1_7 0x1073
+#define MX28_PAD_LCD_D08__GPIO_1_8 0x1083
+#define MX28_PAD_LCD_D09__GPIO_1_9 0x1093
+#define MX28_PAD_LCD_D10__GPIO_1_10 0x10a3
+#define MX28_PAD_LCD_D11__GPIO_1_11 0x10b3
+#define MX28_PAD_LCD_D12__GPIO_1_12 0x10c3
+#define MX28_PAD_LCD_D13__GPIO_1_13 0x10d3
+#define MX28_PAD_LCD_D14__GPIO_1_14 0x10e3
+#define MX28_PAD_LCD_D15__GPIO_1_15 0x10f3
+#define MX28_PAD_LCD_D16__GPIO_1_16 0x1103
+#define MX28_PAD_LCD_D17__GPIO_1_17 0x1113
+#define MX28_PAD_LCD_D18__GPIO_1_18 0x1123
+#define MX28_PAD_LCD_D19__GPIO_1_19 0x1133
+#define MX28_PAD_LCD_D20__GPIO_1_20 0x1143
+#define MX28_PAD_LCD_D21__GPIO_1_21 0x1153
+#define MX28_PAD_LCD_D22__GPIO_1_22 0x1163
+#define MX28_PAD_LCD_D23__GPIO_1_23 0x1173
+#define MX28_PAD_LCD_RD_E__GPIO_1_24 0x1183
+#define MX28_PAD_LCD_WR_RWN__GPIO_1_25 0x1193
+#define MX28_PAD_LCD_RS__GPIO_1_26 0x11a3
+#define MX28_PAD_LCD_CS__GPIO_1_27 0x11b3
+#define MX28_PAD_LCD_VSYNC__GPIO_1_28 0x11c3
+#define MX28_PAD_LCD_HSYNC__GPIO_1_29 0x11d3
+#define MX28_PAD_LCD_DOTCLK__GPIO_1_30 0x11e3
+#define MX28_PAD_LCD_ENABLE__GPIO_1_31 0x11f3
+#define MX28_PAD_SSP0_DATA0__GPIO_2_0 0x2003
+#define MX28_PAD_SSP0_DATA1__GPIO_2_1 0x2013
+#define MX28_PAD_SSP0_DATA2__GPIO_2_2 0x2023
+#define MX28_PAD_SSP0_DATA3__GPIO_2_3 0x2033
+#define MX28_PAD_SSP0_DATA4__GPIO_2_4 0x2043
+#define MX28_PAD_SSP0_DATA5__GPIO_2_5 0x2053
+#define MX28_PAD_SSP0_DATA6__GPIO_2_6 0x2063
+#define MX28_PAD_SSP0_DATA7__GPIO_2_7 0x2073
+#define MX28_PAD_SSP0_CMD__GPIO_2_8 0x2083
+#define MX28_PAD_SSP0_DETECT__GPIO_2_9 0x2093
+#define MX28_PAD_SSP0_SCK__GPIO_2_10 0x20a3
+#define MX28_PAD_SSP1_SCK__GPIO_2_12 0x20c3
+#define MX28_PAD_SSP1_CMD__GPIO_2_13 0x20d3
+#define MX28_PAD_SSP1_DATA0__GPIO_2_14 0x20e3
+#define MX28_PAD_SSP1_DATA3__GPIO_2_15 0x20f3
+#define MX28_PAD_SSP2_SCK__GPIO_2_16 0x2103
+#define MX28_PAD_SSP2_MOSI__GPIO_2_17 0x2113
+#define MX28_PAD_SSP2_MISO__GPIO_2_18 0x2123
+#define MX28_PAD_SSP2_SS0__GPIO_2_19 0x2133
+#define MX28_PAD_SSP2_SS1__GPIO_2_20 0x2143
+#define MX28_PAD_SSP2_SS2__GPIO_2_21 0x2153
+#define MX28_PAD_SSP3_SCK__GPIO_2_24 0x2183
+#define MX28_PAD_SSP3_MOSI__GPIO_2_25 0x2193
+#define MX28_PAD_SSP3_MISO__GPIO_2_26 0x21a3
+#define MX28_PAD_SSP3_SS0__GPIO_2_27 0x21b3
+#define MX28_PAD_AUART0_RX__GPIO_3_0 0x3003
+#define MX28_PAD_AUART0_TX__GPIO_3_1 0x3013
+#define MX28_PAD_AUART0_CTS__GPIO_3_2 0x3023
+#define MX28_PAD_AUART0_RTS__GPIO_3_3 0x3033
+#define MX28_PAD_AUART1_RX__GPIO_3_4 0x3043
+#define MX28_PAD_AUART1_TX__GPIO_3_5 0x3053
+#define MX28_PAD_AUART1_CTS__GPIO_3_6 0x3063
+#define MX28_PAD_AUART1_RTS__GPIO_3_7 0x3073
+#define MX28_PAD_AUART2_RX__GPIO_3_8 0x3083
+#define MX28_PAD_AUART2_TX__GPIO_3_9 0x3093
+#define MX28_PAD_AUART2_CTS__GPIO_3_10 0x30a3
+#define MX28_PAD_AUART2_RTS__GPIO_3_11 0x30b3
+#define MX28_PAD_AUART3_RX__GPIO_3_12 0x30c3
+#define MX28_PAD_AUART3_TX__GPIO_3_13 0x30d3
+#define MX28_PAD_AUART3_CTS__GPIO_3_14 0x30e3
+#define MX28_PAD_AUART3_RTS__GPIO_3_15 0x30f3
+#define MX28_PAD_PWM0__GPIO_3_16 0x3103
+#define MX28_PAD_PWM1__GPIO_3_17 0x3113
+#define MX28_PAD_PWM2__GPIO_3_18 0x3123
+#define MX28_PAD_SAIF0_MCLK__GPIO_3_20 0x3143
+#define MX28_PAD_SAIF0_LRCLK__GPIO_3_21 0x3153
+#define MX28_PAD_SAIF0_BITCLK__GPIO_3_22 0x3163
+#define MX28_PAD_SAIF0_SDATA0__GPIO_3_23 0x3173
+#define MX28_PAD_I2C0_SCL__GPIO_3_24 0x3183
+#define MX28_PAD_I2C0_SDA__GPIO_3_25 0x3193
+#define MX28_PAD_SAIF1_SDATA0__GPIO_3_26 0x31a3
+#define MX28_PAD_SPDIF__GPIO_3_27 0x31b3
+#define MX28_PAD_PWM3__GPIO_3_28 0x31c3
+#define MX28_PAD_PWM4__GPIO_3_29 0x31d3
+#define MX28_PAD_LCD_RESET__GPIO_3_30 0x31e3
+#define MX28_PAD_ENET0_MDC__GPIO_4_0 0x4003
+#define MX28_PAD_ENET0_MDIO__GPIO_4_1 0x4013
+#define MX28_PAD_ENET0_RX_EN__GPIO_4_2 0x4023
+#define MX28_PAD_ENET0_RXD0__GPIO_4_3 0x4033
+#define MX28_PAD_ENET0_RXD1__GPIO_4_4 0x4043
+#define MX28_PAD_ENET0_TX_CLK__GPIO_4_5 0x4053
+#define MX28_PAD_ENET0_TX_EN__GPIO_4_6 0x4063
+#define MX28_PAD_ENET0_TXD0__GPIO_4_7 0x4073
+#define MX28_PAD_ENET0_TXD1__GPIO_4_8 0x4083
+#define MX28_PAD_ENET0_RXD2__GPIO_4_9 0x4093
+#define MX28_PAD_ENET0_RXD3__GPIO_4_10 0x40a3
+#define MX28_PAD_ENET0_TXD2__GPIO_4_11 0x40b3
+#define MX28_PAD_ENET0_TXD3__GPIO_4_12 0x40c3
+#define MX28_PAD_ENET0_RX_CLK__GPIO_4_13 0x40d3
+#define MX28_PAD_ENET0_COL__GPIO_4_14 0x40e3
+#define MX28_PAD_ENET0_CRS__GPIO_4_15 0x40f3
+#define MX28_PAD_ENET_CLK__GPIO_4_16 0x4103
+#define MX28_PAD_JTAG_RTCK__GPIO_4_20 0x4143
+
+#endif /* __DT_BINDINGS_MX28_PINCTRL_H__ */
diff --git a/arch/arm/dts/imx28-u-boot.dtsi b/arch/arm/dts/imx28-u-boot.dtsi
new file mode 100644
index 0000000..d545b40
--- /dev/null
+++ b/arch/arm/dts/imx28-u-boot.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+ or X11
+ */
+#include "imx28.dtsi"
+
+&gpio0 {
+ gpio-ranges = <&pinctrl 0 0 29>;
+};
+
+&gpio1 {
+ gpio-ranges = <&pinctrl 0 29 32>;
+};
+
+&gpio2 {
+ gpio-ranges = <&pinctrl 0 61 28>;
+};
+
+&gpio3 {
+ gpio-ranges = <&pinctrl 0 89 31>;
+};
+
+&gpio4 {
+ gpio-ranges = <&pinctrl 0 120 21>;
+};
diff --git a/arch/arm/dts/imx28.dtsi b/arch/arm/dts/imx28.dtsi
new file mode 100644
index 0000000..e14d8ef
--- /dev/null
+++ b/arch/arm/dts/imx28.dtsi
@@ -0,0 +1,1330 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright 2012 Freescale Semiconductor, Inc.
+
+#include <dt-bindings/gpio/gpio.h>
+#include "imx28-pinfunc.h"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&icoll>;
+ /*
+ * The decompressor and also some bootloaders rely on a
+ * pre-existing /chosen node to be available to insert the
+ * command line and merge other ATAGS info.
+ */
+ chosen {};
+
+ aliases {
+ ethernet0 = &mac0;
+ ethernet1 = &mac1;
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ gpio4 = &gpio4;
+ saif0 = &saif0;
+ saif1 = &saif1;
+ serial0 = &auart0;
+ serial1 = &auart1;
+ serial2 = &auart2;
+ serial3 = &auart3;
+ serial4 = &auart4;
+ spi0 = &ssp1;
+ spi1 = &ssp2;
+ usbphy0 = &usbphy0;
+ usbphy1 = &usbphy1;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
+ reg = <0>;
+ };
+ };
+
+ apb@80000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x80000000 0x80000>;
+ ranges;
+
+ apbh@80000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x80000000 0x3c900>;
+ ranges;
+
+ icoll: interrupt-controller@80000000 {
+ compatible = "fsl,imx28-icoll", "fsl,icoll";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x80000000 0x2000>;
+ };
+
+ hsadc: hsadc@80002000 {
+ reg = <0x80002000 0x2000>;
+ interrupts = <13>;
+ dmas = <&dma_apbh 12>;
+ dma-names = "rx";
+ status = "disabled";
+ };
+
+ dma_apbh: dma-apbh@80004000 {
+ compatible = "fsl,imx28-dma-apbh";
+ reg = <0x80004000 0x2000>;
+ interrupts = <82 83 84 85
+ 88 88 88 88
+ 88 88 88 88
+ 87 86 0 0>;
+ interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
+ "gpmi0", "gmpi1", "gpmi2", "gmpi3",
+ "gpmi4", "gmpi5", "gpmi6", "gmpi7",
+ "hsadc", "lcdif", "empty", "empty";
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ clocks = <&clks 25>;
+ };
+
+ perfmon: perfmon@80006000 {
+ reg = <0x80006000 0x800>;
+ interrupts = <27>;
+ status = "disabled";
+ };
+
+ gpmi: gpmi-nand@8000c000 {
+ compatible = "fsl,imx28-gpmi-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
+ reg-names = "gpmi-nand", "bch";
+ interrupts = <41>;
+ interrupt-names = "bch";
+ clocks = <&clks 50>;
+ clock-names = "gpmi_io";
+ dmas = <&dma_apbh 4>;
+ dma-names = "rx-tx";
+ status = "disabled";
+ };
+
+ ssp0: spi@80010000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x80010000 0x2000>;
+ interrupts = <96>;
+ clocks = <&clks 46>;
+ dmas = <&dma_apbh 0>;
+ dma-names = "rx-tx";
+ status = "disabled";
+ };
+
+ ssp1: spi@80012000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x80012000 0x2000>;
+ interrupts = <97>;
+ clocks = <&clks 47>;
+ dmas = <&dma_apbh 1>;
+ dma-names = "rx-tx";
+ status = "disabled";
+ };
+
+ ssp2: spi@80014000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x80014000 0x2000>;
+ interrupts = <98>;
+ clocks = <&clks 48>;
+ dmas = <&dma_apbh 2>;
+ dma-names = "rx-tx";
+ status = "disabled";
+ };
+
+ ssp3: spi@80016000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x80016000 0x2000>;
+ interrupts = <99>;
+ clocks = <&clks 49>;
+ dmas = <&dma_apbh 3>;
+ dma-names = "rx-tx";
+ status = "disabled";
+ };
+
+ pinctrl: pinctrl@80018000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx28-pinctrl", "simple-bus";
+ reg = <0x80018000 0x2000>;
+
+ gpio0: gpio@0 {
+ compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
+ reg = <0>;
+ interrupts = <127>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@1 {
+ compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
+ reg = <1>;
+ interrupts = <126>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@2 {
+ compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
+ reg = <2>;
+ interrupts = <125>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@3 {
+ compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
+ reg = <3>;
+ interrupts = <124>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@4 {
+ compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
+ reg = <4>;
+ interrupts = <123>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ duart_pins_a: duart@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_PWM0__DUART_RX
+ MX28_PAD_PWM1__DUART_TX
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ duart_pins_b: duart@1 {
+ reg = <1>;
+ fsl,pinmux-ids = <
+ MX28_PAD_AUART0_CTS__DUART_RX
+ MX28_PAD_AUART0_RTS__DUART_TX
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ duart_4pins_a: duart-4pins@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_AUART0_CTS__DUART_RX
+ MX28_PAD_AUART0_RTS__DUART_TX
+ MX28_PAD_AUART0_RX__DUART_CTS
+ MX28_PAD_AUART0_TX__DUART_RTS
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ gpmi_pins_a: gpmi-nand@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_GPMI_D00__GPMI_D0
+ MX28_PAD_GPMI_D01__GPMI_D1
+ MX28_PAD_GPMI_D02__GPMI_D2
+ MX28_PAD_GPMI_D03__GPMI_D3
+ MX28_PAD_GPMI_D04__GPMI_D4
+ MX28_PAD_GPMI_D05__GPMI_D5
+ MX28_PAD_GPMI_D06__GPMI_D6
+ MX28_PAD_GPMI_D07__GPMI_D7
+ MX28_PAD_GPMI_CE0N__GPMI_CE0N
+ MX28_PAD_GPMI_RDY0__GPMI_READY0
+ MX28_PAD_GPMI_RDN__GPMI_RDN
+ MX28_PAD_GPMI_WRN__GPMI_WRN
+ MX28_PAD_GPMI_ALE__GPMI_ALE
+ MX28_PAD_GPMI_CLE__GPMI_CLE
+ MX28_PAD_GPMI_RESETN__GPMI_RESETN
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ gpmi_status_cfg: gpmi-status-cfg@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_GPMI_RDN__GPMI_RDN
+ MX28_PAD_GPMI_WRN__GPMI_WRN
+ MX28_PAD_GPMI_RESETN__GPMI_RESETN
+ >;
+ fsl,drive-strength = <MXS_DRIVE_12mA>;
+ };
+
+ auart0_pins_a: auart0@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_AUART0_RX__AUART0_RX
+ MX28_PAD_AUART0_TX__AUART0_TX
+ MX28_PAD_AUART0_CTS__AUART0_CTS
+ MX28_PAD_AUART0_RTS__AUART0_RTS
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ auart0_2pins_a: auart0-2pins@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_AUART0_RX__AUART0_RX
+ MX28_PAD_AUART0_TX__AUART0_TX
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ auart1_pins_a: auart1@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_AUART1_RX__AUART1_RX
+ MX28_PAD_AUART1_TX__AUART1_TX
+ MX28_PAD_AUART1_CTS__AUART1_CTS
+ MX28_PAD_AUART1_RTS__AUART1_RTS
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ auart1_2pins_a: auart1-2pins@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_AUART1_RX__AUART1_RX
+ MX28_PAD_AUART1_TX__AUART1_TX
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ auart2_2pins_a: auart2-2pins@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SSP2_SCK__AUART2_RX
+ MX28_PAD_SSP2_MOSI__AUART2_TX
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ auart2_2pins_b: auart2-2pins@1 {
+ reg = <1>;
+ fsl,pinmux-ids = <
+ MX28_PAD_AUART2_RX__AUART2_RX
+ MX28_PAD_AUART2_TX__AUART2_TX
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ auart2_pins_a: auart2-pins@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_AUART2_RX__AUART2_RX
+ MX28_PAD_AUART2_TX__AUART2_TX
+ MX28_PAD_AUART2_CTS__AUART2_CTS
+ MX28_PAD_AUART2_RTS__AUART2_RTS
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ auart3_pins_a: auart3@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_AUART3_RX__AUART3_RX
+ MX28_PAD_AUART3_TX__AUART3_TX
+ MX28_PAD_AUART3_CTS__AUART3_CTS
+ MX28_PAD_AUART3_RTS__AUART3_RTS
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ auart3_2pins_a: auart3-2pins@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SSP2_MISO__AUART3_RX
+ MX28_PAD_SSP2_SS0__AUART3_TX
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ auart3_2pins_b: auart3-2pins@1 {
+ reg = <1>;
+ fsl,pinmux-ids = <
+ MX28_PAD_AUART3_RX__AUART3_RX
+ MX28_PAD_AUART3_TX__AUART3_TX
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ auart4_2pins_a: auart4@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SSP3_SCK__AUART4_TX
+ MX28_PAD_SSP3_MOSI__AUART4_RX
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ auart4_2pins_b: auart4@1 {
+ reg = <1>;
+ fsl,pinmux-ids = <
+ MX28_PAD_AUART0_CTS__AUART4_RX
+ MX28_PAD_AUART0_RTS__AUART4_TX
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ mac0_pins_a: mac0@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_ENET0_MDC__ENET0_MDC
+ MX28_PAD_ENET0_MDIO__ENET0_MDIO
+ MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
+ MX28_PAD_ENET0_RXD0__ENET0_RXD0
+ MX28_PAD_ENET0_RXD1__ENET0_RXD1
+ MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
+ MX28_PAD_ENET0_TXD0__ENET0_TXD0
+ MX28_PAD_ENET0_TXD1__ENET0_TXD1
+ MX28_PAD_ENET_CLK__CLKCTRL_ENET
+ >;
+ fsl,drive-strength = <MXS_DRIVE_8mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+
+ mac0_pins_b: mac0@1 {
+ reg = <1>;
+ fsl,pinmux-ids = <
+ MX28_PAD_ENET0_MDC__ENET0_MDC
+ MX28_PAD_ENET0_MDIO__ENET0_MDIO
+ MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
+ MX28_PAD_ENET0_RXD0__ENET0_RXD0
+ MX28_PAD_ENET0_RXD1__ENET0_RXD1
+ MX28_PAD_ENET0_RXD2__ENET0_RXD2
+ MX28_PAD_ENET0_RXD3__ENET0_RXD3
+ MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
+ MX28_PAD_ENET0_TXD0__ENET0_TXD0
+ MX28_PAD_ENET0_TXD1__ENET0_TXD1
+ MX28_PAD_ENET0_TXD2__ENET0_TXD2
+ MX28_PAD_ENET0_TXD3__ENET0_TXD3
+ MX28_PAD_ENET_CLK__CLKCTRL_ENET
+ MX28_PAD_ENET0_COL__ENET0_COL
+ MX28_PAD_ENET0_CRS__ENET0_CRS
+ MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK
+ MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK
+ >;
+ fsl,drive-strength = <MXS_DRIVE_8mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+
+ mac1_pins_a: mac1@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_ENET0_CRS__ENET1_RX_EN
+ MX28_PAD_ENET0_RXD2__ENET1_RXD0
+ MX28_PAD_ENET0_RXD3__ENET1_RXD1
+ MX28_PAD_ENET0_COL__ENET1_TX_EN
+ MX28_PAD_ENET0_TXD2__ENET1_TXD0
+ MX28_PAD_ENET0_TXD3__ENET1_TXD1
+ >;
+ fsl,drive-strength = <MXS_DRIVE_8mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+
+ mmc0_8bit_pins_a: mmc0-8bit@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SSP0_DATA0__SSP0_D0
+ MX28_PAD_SSP0_DATA1__SSP0_D1
+ MX28_PAD_SSP0_DATA2__SSP0_D2
+ MX28_PAD_SSP0_DATA3__SSP0_D3
+ MX28_PAD_SSP0_DATA4__SSP0_D4
+ MX28_PAD_SSP0_DATA5__SSP0_D5
+ MX28_PAD_SSP0_DATA6__SSP0_D6
+ MX28_PAD_SSP0_DATA7__SSP0_D7
+ MX28_PAD_SSP0_CMD__SSP0_CMD
+ MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
+ MX28_PAD_SSP0_SCK__SSP0_SCK
+ >;
+ fsl,drive-strength = <MXS_DRIVE_8mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+
+ mmc0_4bit_pins_a: mmc0-4bit@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SSP0_DATA0__SSP0_D0
+ MX28_PAD_SSP0_DATA1__SSP0_D1
+ MX28_PAD_SSP0_DATA2__SSP0_D2
+ MX28_PAD_SSP0_DATA3__SSP0_D3
+ MX28_PAD_SSP0_CMD__SSP0_CMD
+ MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
+ MX28_PAD_SSP0_SCK__SSP0_SCK
+ >;
+ fsl,drive-strength = <MXS_DRIVE_8mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+
+ mmc0_cd_cfg: mmc0-cd-cfg@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
+ >;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ mmc0_sck_cfg: mmc0-sck-cfg@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SSP0_SCK__SSP0_SCK
+ >;
+ fsl,drive-strength = <MXS_DRIVE_12mA>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ mmc1_4bit_pins_a: mmc1-4bit@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_GPMI_D00__SSP1_D0
+ MX28_PAD_GPMI_D01__SSP1_D1
+ MX28_PAD_GPMI_D02__SSP1_D2
+ MX28_PAD_GPMI_D03__SSP1_D3
+ MX28_PAD_GPMI_RDY1__SSP1_CMD
+ MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
+ MX28_PAD_GPMI_WRN__SSP1_SCK
+ >;
+ fsl,drive-strength = <MXS_DRIVE_8mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+
+ mmc1_cd_cfg: mmc1-cd-cfg@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
+ >;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ mmc1_sck_cfg: mmc1-sck-cfg@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_GPMI_WRN__SSP1_SCK
+ >;
+ fsl,drive-strength = <MXS_DRIVE_12mA>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+
+ mmc2_4bit_pins_a: mmc2-4bit@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SSP0_DATA4__SSP2_D0
+ MX28_PAD_SSP1_SCK__SSP2_D1
+ MX28_PAD_SSP1_CMD__SSP2_D2
+ MX28_PAD_SSP0_DATA5__SSP2_D3
+ MX28_PAD_SSP0_DATA6__SSP2_CMD
+ MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
+ MX28_PAD_SSP0_DATA7__SSP2_SCK
+ >;
+ fsl,drive-strength = <MXS_DRIVE_8mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+
+ mmc2_4bit_pins_b: mmc2-4bit@1 {
+ reg = <1>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SSP2_SCK__SSP2_SCK
+ MX28_PAD_SSP2_MOSI__SSP2_CMD
+ MX28_PAD_SSP2_MISO__SSP2_D0
+ MX28_PAD_SSP2_SS0__SSP2_D3
+ MX28_PAD_SSP2_SS1__SSP2_D1
+ MX28_PAD_SSP2_SS2__SSP2_D2
+ MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
+ >;
+ fsl,drive-strength = <MXS_DRIVE_8mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+
+ mmc2_cd_cfg: mmc2-cd-cfg@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
+ >;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ mmc2_sck_cfg_a: mmc2-sck-cfg@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SSP0_DATA7__SSP2_SCK
+ >;
+ fsl,drive-strength = <MXS_DRIVE_12mA>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ mmc2_sck_cfg_b: mmc2-sck-cfg@1 {
+ reg = <1>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SSP2_SCK__SSP2_SCK
+ >;
+ fsl,drive-strength = <MXS_DRIVE_12mA>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ i2c0_pins_a: i2c0@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_I2C0_SCL__I2C0_SCL
+ MX28_PAD_I2C0_SDA__I2C0_SDA
+ >;
+ fsl,drive-strength = <MXS_DRIVE_8mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+
+ i2c0_pins_b: i2c0@1 {
+ reg = <1>;
+ fsl,pinmux-ids = <
+ MX28_PAD_AUART0_RX__I2C0_SCL
+ MX28_PAD_AUART0_TX__I2C0_SDA
+ >;
+ fsl,drive-strength = <MXS_DRIVE_8mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+
+ i2c1_pins_a: i2c1@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_PWM0__I2C1_SCL
+ MX28_PAD_PWM1__I2C1_SDA
+ >;
+ fsl,drive-strength = <MXS_DRIVE_8mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+
+ i2c1_pins_b: i2c1@1 {
+ reg = <1>;
+ fsl,pinmux-ids = <
+ MX28_PAD_AUART2_CTS__I2C1_SCL
+ MX28_PAD_AUART2_RTS__I2C1_SDA
+ >;
+ fsl,drive-strength = <MXS_DRIVE_8mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+
+ saif0_pins_a: saif0@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SAIF0_MCLK__SAIF0_MCLK
+ MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
+ MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
+ MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
+ >;
+ fsl,drive-strength = <MXS_DRIVE_12mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+
+ saif0_pins_b: saif0@1 {
+ reg = <1>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
+ MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
+ MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
+ >;
+ fsl,drive-strength = <MXS_DRIVE_12mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+
+ saif1_pins_a: saif1@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0
+ >;
+ fsl,drive-strength = <MXS_DRIVE_12mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+
+ pwm0_pins_a: pwm0@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_PWM0__PWM_0
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ pwm2_pins_a: pwm2@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_PWM2__PWM_2
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ pwm3_pins_a: pwm3@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_PWM3__PWM_3
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ pwm3_pins_b: pwm3@1 {
+ reg = <1>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SAIF0_MCLK__PWM_3
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ pwm4_pins_a: pwm4@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_PWM4__PWM_4
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ lcdif_24bit_pins_a: lcdif-24bit@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_LCD_D00__LCD_D0
+ MX28_PAD_LCD_D01__LCD_D1
+ MX28_PAD_LCD_D02__LCD_D2
+ MX28_PAD_LCD_D03__LCD_D3
+ MX28_PAD_LCD_D04__LCD_D4
+ MX28_PAD_LCD_D05__LCD_D5
+ MX28_PAD_LCD_D06__LCD_D6
+ MX28_PAD_LCD_D07__LCD_D7
+ MX28_PAD_LCD_D08__LCD_D8
+ MX28_PAD_LCD_D09__LCD_D9
+ MX28_PAD_LCD_D10__LCD_D10
+ MX28_PAD_LCD_D11__LCD_D11
+ MX28_PAD_LCD_D12__LCD_D12
+ MX28_PAD_LCD_D13__LCD_D13
+ MX28_PAD_LCD_D14__LCD_D14
+ MX28_PAD_LCD_D15__LCD_D15
+ MX28_PAD_LCD_D16__LCD_D16
+ MX28_PAD_LCD_D17__LCD_D17
+ MX28_PAD_LCD_D18__LCD_D18
+ MX28_PAD_LCD_D19__LCD_D19
+ MX28_PAD_LCD_D20__LCD_D20
+ MX28_PAD_LCD_D21__LCD_D21
+ MX28_PAD_LCD_D22__LCD_D22
+ MX28_PAD_LCD_D23__LCD_D23
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ lcdif_18bit_pins_a: lcdif-18bit@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_LCD_D00__LCD_D0
+ MX28_PAD_LCD_D01__LCD_D1
+ MX28_PAD_LCD_D02__LCD_D2
+ MX28_PAD_LCD_D03__LCD_D3
+ MX28_PAD_LCD_D04__LCD_D4
+ MX28_PAD_LCD_D05__LCD_D5
+ MX28_PAD_LCD_D06__LCD_D6
+ MX28_PAD_LCD_D07__LCD_D7
+ MX28_PAD_LCD_D08__LCD_D8
+ MX28_PAD_LCD_D09__LCD_D9
+ MX28_PAD_LCD_D10__LCD_D10
+ MX28_PAD_LCD_D11__LCD_D11
+ MX28_PAD_LCD_D12__LCD_D12
+ MX28_PAD_LCD_D13__LCD_D13
+ MX28_PAD_LCD_D14__LCD_D14
+ MX28_PAD_LCD_D15__LCD_D15
+ MX28_PAD_LCD_D16__LCD_D16
+ MX28_PAD_LCD_D17__LCD_D17
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ lcdif_16bit_pins_a: lcdif-16bit@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_LCD_D00__LCD_D0
+ MX28_PAD_LCD_D01__LCD_D1
+ MX28_PAD_LCD_D02__LCD_D2
+ MX28_PAD_LCD_D03__LCD_D3
+ MX28_PAD_LCD_D04__LCD_D4
+ MX28_PAD_LCD_D05__LCD_D5
+ MX28_PAD_LCD_D06__LCD_D6
+ MX28_PAD_LCD_D07__LCD_D7
+ MX28_PAD_LCD_D08__LCD_D8
+ MX28_PAD_LCD_D09__LCD_D9
+ MX28_PAD_LCD_D10__LCD_D10
+ MX28_PAD_LCD_D11__LCD_D11
+ MX28_PAD_LCD_D12__LCD_D12
+ MX28_PAD_LCD_D13__LCD_D13
+ MX28_PAD_LCD_D14__LCD_D14
+ MX28_PAD_LCD_D15__LCD_D15
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ lcdif_sync_pins_a: lcdif-sync@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_LCD_RS__LCD_DOTCLK
+ MX28_PAD_LCD_CS__LCD_ENABLE
+ MX28_PAD_LCD_RD_E__LCD_VSYNC
+ MX28_PAD_LCD_WR_RWN__LCD_HSYNC
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ can0_pins_a: can0@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_GPMI_RDY2__CAN0_TX
+ MX28_PAD_GPMI_RDY3__CAN0_RX
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ can1_pins_a: can1@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_GPMI_CE2N__CAN1_TX
+ MX28_PAD_GPMI_CE3N__CAN1_RX
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ spi2_pins_a: spi2@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SSP2_SCK__SSP2_SCK
+ MX28_PAD_SSP2_MOSI__SSP2_CMD
+ MX28_PAD_SSP2_MISO__SSP2_D0
+ MX28_PAD_SSP2_SS0__SSP2_D3
+ >;
+ fsl,drive-strength = <MXS_DRIVE_8mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+
+ spi3_pins_a: spi3@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_AUART2_RX__SSP3_D4
+ MX28_PAD_AUART2_TX__SSP3_D5
+ MX28_PAD_SSP3_SCK__SSP3_SCK
+ MX28_PAD_SSP3_MOSI__SSP3_CMD
+ MX28_PAD_SSP3_MISO__SSP3_D0
+ MX28_PAD_SSP3_SS0__SSP3_D3
+ >;
+ fsl,drive-strength = <MXS_DRIVE_8mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ spi3_pins_b: spi3@1 {
+ reg = <1>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SSP3_SCK__SSP3_SCK
+ MX28_PAD_SSP3_MOSI__SSP3_CMD
+ MX28_PAD_SSP3_MISO__SSP3_D0
+ MX28_PAD_SSP3_SS0__SSP3_D3
+ >;
+ fsl,drive-strength = <MXS_DRIVE_8mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+
+ usb0_pins_a: usb0@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SSP2_SS2__USB0_OVERCURRENT
+ >;
+ fsl,drive-strength = <MXS_DRIVE_12mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ usb0_pins_b: usb0@1 {
+ reg = <1>;
+ fsl,pinmux-ids = <
+ MX28_PAD_AUART1_CTS__USB0_OVERCURRENT
+ >;
+ fsl,drive-strength = <MXS_DRIVE_12mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ usb1_pins_a: usb1@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_SSP2_SS1__USB1_OVERCURRENT
+ >;
+ fsl,drive-strength = <MXS_DRIVE_12mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ usb0_id_pins_a: usb0id@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_AUART1_RTS__USB0_ID
+ >;
+ fsl,drive-strength = <MXS_DRIVE_12mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+
+ usb0_id_pins_b: usb0id1@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_PWM2__USB0_ID
+ >;
+ fsl,drive-strength = <MXS_DRIVE_12mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+
+ };
+
+ digctl: digctl@8001c000 {
+ compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
+ reg = <0x8001c000 0x2000>;
+ interrupts = <89>;
+ status = "disabled";
+ };
+
+ etm: etm@80022000 {
+ reg = <0x80022000 0x2000>;
+ status = "disabled";
+ };
+
+ dma_apbx: dma-apbx@80024000 {
+ compatible = "fsl,imx28-dma-apbx";
+ reg = <0x80024000 0x2000>;
+ interrupts = <78 79 66 0
+ 80 81 68 69
+ 70 71 72 73
+ 74 75 76 77>;
+ interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty",
+ "saif0", "saif1", "i2c0", "i2c1",
+ "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
+ "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ clocks = <&clks 26>;
+ };
+
+ dcp: dcp@80028000 {
+ compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
+ reg = <0x80028000 0x2000>;
+ interrupts = <52 53 54>;
+ status = "okay";
+ };
+
+ pxp: pxp@8002a000 {
+ reg = <0x8002a000 0x2000>;
+ interrupts = <39>;
+ status = "disabled";
+ };
+
+ ocotp: ocotp@8002c000 {
+ compatible = "fsl,imx28-ocotp", "fsl,ocotp";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x8002c000 0x2000>;
+ clocks = <&clks 25>;
+ };
+
+ axi-ahb@8002e000 {
+ reg = <0x8002e000 0x2000>;
+ status = "disabled";
+ };
+
+ lcdif: lcdif@80030000 {
+ compatible = "fsl,imx28-lcdif";
+ reg = <0x80030000 0x2000>;
+ interrupts = <38>;
+ clocks = <&clks 55>;
+ dmas = <&dma_apbh 13>;
+ dma-names = "rx";
+ status = "disabled";
+ };
+
+ can0: can@80032000 {
+ compatible = "fsl,imx28-flexcan";
+ reg = <0x80032000 0x2000>;
+ interrupts = <8>;
+ clocks = <&clks 58>, <&clks 58>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ can1: can@80034000 {
+ compatible = "fsl,imx28-flexcan";
+ reg = <0x80034000 0x2000>;
+ interrupts = <9>;
+ clocks = <&clks 59>, <&clks 59>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ simdbg: simdbg@8003c000 {
+ reg = <0x8003c000 0x200>;
+ status = "disabled";
+ };
+
+ simgpmisel: simgpmisel@8003c200 {
+ reg = <0x8003c200 0x100>;
+ status = "disabled";
+ };
+
+ simsspsel: simsspsel@8003c300 {
+ reg = <0x8003c300 0x100>;
+ status = "disabled";
+ };
+
+ simmemsel: simmemsel@8003c400 {
+ reg = <0x8003c400 0x100>;
+ status = "disabled";
+ };
+
+ gpiomon: gpiomon@8003c500 {
+ reg = <0x8003c500 0x100>;
+ status = "disabled";
+ };
+
+ simenet: simenet@8003c700 {
+ reg = <0x8003c700 0x100>;
+ status = "disabled";
+ };
+
+ armjtag: armjtag@8003c800 {
+ reg = <0x8003c800 0x100>;
+ status = "disabled";
+ };
+ };
+
+ apbx@80040000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x80040000 0x40000>;
+ ranges;
+
+ clks: clkctrl@80040000 {
+ compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
+ reg = <0x80040000 0x2000>;
+ #clock-cells = <1>;
+ };
+
+ saif0: saif@80042000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx28-saif";
+ reg = <0x80042000 0x2000>;
+ interrupts = <59>;
+ #clock-cells = <0>;
+ clocks = <&clks 53>;
+ dmas = <&dma_apbx 4>;
+ dma-names = "rx-tx";
+ status = "disabled";
+ };
+
+ power: power@80044000 {
+ reg = <0x80044000 0x2000>;
+ status = "disabled";
+ };
+
+ saif1: saif@80046000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx28-saif";
+ reg = <0x80046000 0x2000>;
+ interrupts = <58>;
+ clocks = <&clks 54>;
+ dmas = <&dma_apbx 5>;
+ dma-names = "rx-tx";
+ status = "disabled";
+ };
+
+ lradc: lradc@80050000 {
+ compatible = "fsl,imx28-lradc";
+ reg = <0x80050000 0x2000>;
+ interrupts = <10 14 15 16 17 18 19
+ 20 21 22 23 24 25>;
+ status = "disabled";
+ clocks = <&clks 41>;
+ #io-channel-cells = <1>;
+ };
+
+ spdif: spdif@80054000 {
+ reg = <0x80054000 0x2000>;
+ interrupts = <45>;
+ dmas = <&dma_apbx 2>;
+ dma-names = "tx";
+ status = "disabled";
+ };
+
+ mxs_rtc: rtc@80056000 {
+ compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
+ reg = <0x80056000 0x2000>;
+ interrupts = <29>;
+ };
+
+ i2c0: i2c@80058000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx28-i2c";
+ reg = <0x80058000 0x2000>;
+ interrupts = <111>;
+ clock-frequency = <100000>;
+ dmas = <&dma_apbx 6>;
+ dma-names = "rx-tx";
+ status = "disabled";
+ };
+
+ i2c1: i2c@8005a000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx28-i2c";
+ reg = <0x8005a000 0x2000>;
+ interrupts = <110>;
+ clock-frequency = <100000>;
+ dmas = <&dma_apbx 7>;
+ dma-names = "rx-tx";
+ status = "disabled";
+ };
+
+ pwm: pwm@80064000 {
+ compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
+ reg = <0x80064000 0x2000>;
+ clocks = <&clks 44>;
+ #pwm-cells = <2>;
+ fsl,pwm-number = <8>;
+ status = "disabled";
+ };
+
+ timer: timrot@80068000 {
+ compatible = "fsl,imx28-timrot", "fsl,timrot";
+ reg = <0x80068000 0x2000>;
+ interrupts = <48 49 50 51>;
+ clocks = <&clks 26>;
+ };
+
+ auart0: serial@8006a000 {
+ compatible = "fsl,imx28-auart", "fsl,imx23-auart";
+ reg = <0x8006a000 0x2000>;
+ interrupts = <112>;
+ dmas = <&dma_apbx 8>, <&dma_apbx 9>;
+ dma-names = "rx", "tx";
+ clocks = <&clks 45>;
+ status = "disabled";
+ };
+
+ auart1: serial@8006c000 {
+ compatible = "fsl,imx28-auart", "fsl,imx23-auart";
+ reg = <0x8006c000 0x2000>;
+ interrupts = <113>;
+ dmas = <&dma_apbx 10>, <&dma_apbx 11>;
+ dma-names = "rx", "tx";
+ clocks = <&clks 45>;
+ status = "disabled";
+ };
+
+ auart2: serial@8006e000 {
+ compatible = "fsl,imx28-auart", "fsl,imx23-auart";
+ reg = <0x8006e000 0x2000>;
+ interrupts = <114>;
+ dmas = <&dma_apbx 12>, <&dma_apbx 13>;
+ dma-names = "rx", "tx";
+ clocks = <&clks 45>;
+ status = "disabled";
+ };
+
+ auart3: serial@80070000 {
+ compatible = "fsl,imx28-auart", "fsl,imx23-auart";
+ reg = <0x80070000 0x2000>;
+ interrupts = <115>;
+ dmas = <&dma_apbx 14>, <&dma_apbx 15>;
+ dma-names = "rx", "tx";
+ clocks = <&clks 45>;
+ status = "disabled";
+ };
+
+ auart4: serial@80072000 {
+ compatible = "fsl,imx28-auart", "fsl,imx23-auart";
+ reg = <0x80072000 0x2000>;
+ interrupts = <116>;
+ dmas = <&dma_apbx 0>, <&dma_apbx 1>;
+ dma-names = "rx", "tx";
+ clocks = <&clks 45>;
+ status = "disabled";
+ };
+
+ duart: serial@80074000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x80074000 0x1000>;
+ interrupts = <47>;
+ clocks = <&clks 45>, <&clks 26>;
+ clock-names = "uart", "apb_pclk";
+ status = "disabled";
+ };
+
+ usbphy0: usbphy@8007c000 {
+ compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
+ reg = <0x8007c000 0x2000>;
+ clocks = <&clks 62>;
+ status = "disabled";
+ };
+
+ usbphy1: usbphy@8007e000 {
+ compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
+ reg = <0x8007e000 0x2000>;
+ clocks = <&clks 63>;
+ status = "disabled";
+ };
+ };
+ };
+
+ ahb@80080000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x80080000 0x80000>;
+ ranges;
+
+ usb0: usb@80080000 {
+ compatible = "fsl,imx28-usb", "fsl,imx27-usb";
+ reg = <0x80080000 0x10000>;
+ interrupts = <93>;
+ clocks = <&clks 60>;
+ fsl,usbphy = <&usbphy0>;
+ status = "disabled";
+ };
+
+ usb1: usb@80090000 {
+ compatible = "fsl,imx28-usb", "fsl,imx27-usb";
+ reg = <0x80090000 0x10000>;
+ interrupts = <92>;
+ clocks = <&clks 61>;
+ fsl,usbphy = <&usbphy1>;
+ dr_mode = "host";
+ status = "disabled";
+ };
+
+ dflpt: dflpt@800c0000 {
+ reg = <0x800c0000 0x10000>;
+ status = "disabled";
+ };
+
+ mac0: ethernet@800f0000 {
+ compatible = "fsl,imx28-fec";
+ reg = <0x800f0000 0x4000>;
+ interrupts = <101>;
+ clocks = <&clks 57>, <&clks 57>, <&clks 64>;
+ clock-names = "ipg", "ahb", "enet_out";
+ status = "disabled";
+ };
+
+ mac1: ethernet@800f4000 {
+ compatible = "fsl,imx28-fec";
+ reg = <0x800f4000 0x4000>;
+ interrupts = <102>;
+ clocks = <&clks 57>, <&clks 57>;
+ clock-names = "ipg", "ahb";
+ status = "disabled";
+ };
+
+ etn_switch: switch@800f8000 {
+ reg = <0x800f8000 0x8000>;
+ status = "disabled";
+ };
+ };
+
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&lradc 8>;
+ };
+};
diff --git a/arch/arm/dts/imx53-m53menlo-u-boot.dtsi b/arch/arm/dts/imx53-m53menlo-u-boot.dtsi
index 329fa3b..bc4b348 100644
--- a/arch/arm/dts/imx53-m53menlo-u-boot.dtsi
+++ b/arch/arm/dts/imx53-m53menlo-u-boot.dtsi
@@ -11,6 +11,11 @@
u-boot,dm-pre-reloc;
};
};
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ };
};
&gpio1 {
diff --git a/arch/arm/dts/imx6dl-dhcom-pdk2.dts b/arch/arm/dts/imx6dl-dhcom-pdk2.dts
new file mode 100644
index 0000000..a0b51bc
--- /dev/null
+++ b/arch/arm/dts/imx6dl-dhcom-pdk2.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0+)
+/*
+ * Copyright (C) 2019 DH electronics GmbH
+ */
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-dhcom-pdk2.dtsi"
+
+/ {
+ model = "Freescale i.MX6 Duallite/Solo DHCOM Premium Developer Kit (2)";
+ compatible = "dh,imx6dl-dhcom-pdk2", "dh,imx6dl-dhcom", "fsl,imx6dl";
+};
diff --git a/arch/arm/dts/imx6q-dhcom-pdk2.dts b/arch/arm/dts/imx6q-dhcom-pdk2.dts
index 9c61e3b..5bab2db 100644
--- a/arch/arm/dts/imx6q-dhcom-pdk2.dts
+++ b/arch/arm/dts/imx6q-dhcom-pdk2.dts
@@ -1,151 +1,20 @@
// SPDX-License-Identifier: (GPL-2.0+)
/*
- * Copyright (C) 2015 DH electronics GmbH
+ * Copyright (C) 2015-2019 DH electronics GmbH
* Copyright (C) 2018 Marek Vasut <marex@denx.de>
*/
/dts-v1/;
-#include "imx6q-dhcom-som.dtsi"
+#include "imx6q.dtsi"
+#include "imx6qdl-dhcom-pdk2.dtsi"
/ {
- model = "Freescale i.MX6 Quad DHCOM Premium Developer Kit (2)";
- compatible = "dh,imx6q-dhcom-pdk2", "dh,imx6q-dhcom-som", "fsl,imx6q";
-
- chosen {
- stdout-path = &uart1;
- };
-
- clk_ext_audio_codec: clock-codec {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24000000>;
- };
-
- sound {
- compatible = "fsl,imx-audio-sgtl5000";
- model = "imx-sgtl5000";
- ssi-controller = <&ssi1>;
- audio-codec = <&sgtl5000>;
- audio-routing =
- "MIC_IN", "Mic Jack",
- "Mic Jack", "Mic Bias",
- "LINE_IN", "Line In Jack",
- "Headphone Jack", "HP_OUT";
- mux-int-port = <1>;
- mux-ext-port = <3>;
- };
-};
-
-&audmux {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_audmux_ext>;
- status = "okay";
-};
-
-&hdmi {
- ddc-i2c-bus = <&i2c2>;
- status = "okay";
-};
-
-&i2c2 {
- sgtl5000: codec@a {
- compatible = "fsl,sgtl5000";
- reg = <0x0a>;
- #sound-dai-cells = <0>;
- clocks = <&clk_ext_audio_codec>;
- VDDA-supply = <®_3p3v>;
- VDDIO-supply = <®_3p3v>;
- };
-};
-
-&iomuxc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hog_base &pinctrl_hog>;
-
- pinctrl_hog: hog-grp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x400120b0
- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x400120b0
- MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x400120b0
- MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x400120b0
- MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x120b0
- MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x400120b0
- MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x120b0
- MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x120b0
- MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x400120b0
- MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x400120b0
- MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x400120b0
- MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x400120b0
- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x400120b0
- MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x400120b0
- MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x400120b0
- MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x400120b0
- MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x400120b0
- MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x400120b0
- MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x400120b0
- MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x400120b0
- MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x400120b0
- MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x400120b0
- MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x400120b0
- MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x400120b0
- >;
- };
-
- pinctrl_audmux_ext: audmux-ext-grp {
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
- >;
- };
-
- pinctrl_enet_1G: enet-1G-grp {
- fsl,pins = <
- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
- MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x000b0
- MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x000b1
- MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x000b1
- >;
- };
-
- pinctrl_pcie: pcie-grp {
- fsl,pins = <
- MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1
- >;
- };
-};
-
-&pcie {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie>;
- reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>;
- status = "okay";
-};
-
-&ssi1 {
- status = "okay";
+ model = "Freescale i.MX6 Quad/Dual DHCOM Premium Developer Kit (2)";
+ compatible = "dh,imx6q-dhcom-pdk2", "dh,imx6q-dhcom", "fsl,imx6q";
};
&sata {
status = "okay";
};
-&usdhc3 {
- status = "okay";
-};
diff --git a/arch/arm/dts/imx6q-dhcom-som.dtsi b/arch/arm/dts/imx6q-dhcom-som.dtsi
deleted file mode 100644
index 524cd28..0000000
--- a/arch/arm/dts/imx6q-dhcom-som.dtsi
+++ /dev/null
@@ -1,477 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+)
-/*
- * Copyright (C) 2015 DH electronics GmbH
- * Copyright (C) 2018 Marek Vasut <marex@denx.de>
- */
-
-#include "imx6q.dtsi"
-#include <dt-bindings/pwm/pwm.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/clock/imx6qdl-clock.h>
-#include <dt-bindings/input/input.h>
-
-/ {
- aliases {
- mmc0 = &usdhc2;
- mmc1 = &usdhc3;
- mmc2 = &usdhc4;
- mmc3 = &usdhc1;
- };
-
- memory@10000000 {
- device_type = "memory";
- reg = <0x10000000 0x40000000>;
- };
-
- reg_usb_otg_vbus: regulator-usb-otg-vbus {
- compatible = "regulator-fixed";
- regulator-name = "usb_otg_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- reg_usb_h1_vbus: regulator-usb-h1-vbus {
- compatible = "regulator-fixed";
- regulator-name = "usb_h1_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- reg_3p3v: regulator-3P3V {
- compatible = "regulator-fixed";
- regulator-name = "3P3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-};
-
-&can1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan1>;
- status = "okay";
-};
-
-&can2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan2>;
- status = "okay";
-};
-
-&ecspi1 {
- cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio4 11 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi1>;
- status = "okay";
-
- flash@0 { /* S25FL116K */
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <50000000>;
- reg = <0>;
- m25p,fast-read;
- };
-};
-
-&ecspi2 {
- cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi2>;
- status = "okay";
-};
-
-&fec {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet_100M>;
- phy-mode = "rmii";
- phy-handle = <ðphy0>;
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy0: ethernet-phy@0 { /* SMSC LAN8710Ai */
- reg = <0>;
- max-speed = <100>;
- reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
- reset-delay-us = <1000>;
- reset-post-delay-us = <1000>;
- };
- };
-};
-
-&i2c1 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- status = "okay";
-};
-
-&i2c2 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- status = "okay";
-};
-
-&i2c3 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- status = "okay";
-
- ltc3676: pmic@3c {
- compatible = "lltc,ltc3676";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pmic_hw300>;
- reg = <0x3c>;
- interrupt-parent = <&gpio5>;
- interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
-
- regulators {
- sw1_reg: sw1 {
- regulator-min-microvolt = <787500>;
- regulator-max-microvolt = <1527272>;
- lltc,fb-voltage-divider = <100000 110000>;
- regulator-suspend-mem-microvolt = <1040000>;
- regulator-ramp-delay = <7000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- sw2_reg: sw2 {
- regulator-min-microvolt = <1885714>;
- regulator-max-microvolt = <3657142>;
- lltc,fb-voltage-divider = <100000 28000>;
- regulator-ramp-delay = <7000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- sw3_reg: sw3 {
- regulator-min-microvolt = <787500>;
- regulator-max-microvolt = <1527272>;
- lltc,fb-voltage-divider = <100000 110000>;
- regulator-suspend-mem-microvolt = <980000>;
- regulator-ramp-delay = <7000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- sw4_reg: sw4 {
- regulator-min-microvolt = <855571>;
- regulator-max-microvolt = <1659291>;
- lltc,fb-voltage-divider = <100000 93100>;
- regulator-ramp-delay = <7000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo1_reg: ldo1 {
- regulator-min-microvolt = <3240306>;
- regulator-max-microvolt = <3240306>;
- lltc,fb-voltage-divider = <102000 29400>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo2_reg: ldo2 {
- regulator-min-microvolt = <2484708>;
- regulator-max-microvolt = <2484708>;
- lltc,fb-voltage-divider = <100000 41200>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
-
- touchscreen@49 { /* TSC2004 */
- compatible = "ti,tsc2004";
- reg = <0x49>;
- vio-supply = <®_3p3v>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_tsc2004_hw300>;
- interrupts-extended = <&gpio4 14 IRQ_TYPE_EDGE_FALLING>;
- status = "disabled";
- };
-
- eeprom@50 {
- compatible = "atmel,24c02";
- reg = <0x50>;
- pagesize = <16>;
- };
-
- rtc@56 {
- compatible = "rv3029c2";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_rtc_hw300>;
- reg = <0x56>;
- interrupt-parent = <&gpio7>;
- interrupts = <12 2>;
- };
-};
-
-&iomuxc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hog_base>;
-
- pinctrl_hog_base: hog-base-grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x120b0
- MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x120b0
- MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x120b0
- MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x120b0
- MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x120b0
- >;
- };
-
- pinctrl_ecspi1: ecspi1-grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
- MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
- MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
- >;
- };
-
- pinctrl_ecspi2: ecspi2-grp {
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1
- MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1
- MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1
- MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x1b0b0
- >;
- };
-
- pinctrl_enet_100M: enet-100M-grp {
- fsl,pins = <
- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
- MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
- MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
- MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
- MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
- MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
- MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
- MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x000b0
- MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b1
- MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x120b0
- >;
- };
-
- pinctrl_flexcan1: flexcan1-grp {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
- MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
- >;
- };
-
- pinctrl_flexcan2: flexcan2-grp {
- fsl,pins = <
- MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0
- MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0
- >;
- };
-
- pinctrl_i2c1: i2c1-grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
- >;
- };
-
- pinctrl_i2c2: i2c2-grp {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
- >;
- };
-
- pinctrl_i2c3: i2c3-grp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
- >;
- };
-
- pinctrl_pmic_hw300: pmic-hw300-grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1B0B0
- >;
- };
-
- pinctrl_rtc_hw300: rtc-hw300-grp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x120B0
- >;
- };
-
- pinctrl_tsc2004_hw300: tsc2004-hw300-grp {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x120B0
- >;
- };
-
- pinctrl_uart1: uart1-grp {
- fsl,pins = <
- MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
- MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
- MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1
- MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x4001b0b1
- MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x4001b0b1
- MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x4001b0b1
- MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x4001b0b1
- MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x4001b0b1
- >;
- };
-
- pinctrl_uart4: uart4-grp {
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
- MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
- >;
- };
-
- pinctrl_uart5: uart5-grp {
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
- MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
- MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1
- MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x4001b0b1
- >;
- };
-
- pinctrl_usbh1: usbh1-grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x120B0
- >;
- };
-
- pinctrl_usbotg: usbotg-grp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
- >;
- };
-
- pinctrl_usdhc2: usdhc2-grp {
- fsl,pins = <
- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
- MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x120B0
- >;
- };
-
- pinctrl_usdhc3: usdhc3-grp {
- fsl,pins = <
- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
- MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x120B0
- >;
- };
-
- pinctrl_usdhc4: usdhc4-grp {
- fsl,pins = <
- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
- MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
- MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
- MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
- MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
- >;
- };
-};
-
-®_arm {
- vin-supply = <&sw3_reg>;
-};
-
-®_soc {
- vin-supply = <&sw1_reg>;
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- uart-has-rtscts;
- dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
- dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
- dcd-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
- rng-gpios = <&gpio2 31 GPIO_ACTIVE_LOW>;
- status = "okay";
-};
-
-&uart4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart4>;
- status = "okay";
-};
-
-&uart5 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart5>;
- uart-has-rtscts;
- status = "okay";
-};
-
-&usbh1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbh1>;
- vbus-supply = <®_usb_h1_vbus>;
- dr_mode = "host";
- status = "okay";
-};
-
-&usbotg {
- vbus-supply = <®_usb_otg_vbus>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg>;
- disable-over-current;
- dr_mode = "otg";
- status = "okay";
-};
-
-&usdhc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc2>;
- cd-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
- keep-power-in-suspend;
- status = "okay";
-};
-
-&usdhc3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc3>;
- cd-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>;
- fsl,wp-controller;
- keep-power-in-suspend;
- status = "disabled";
-};
-
-&usdhc4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc4>;
- non-removable;
- bus-width = <8>;
- no-1-8-v;
- keep-power-in-suspend;
- status = "okay";
-};
diff --git a/arch/arm/dts/imx6q-display5-u-boot.dtsi b/arch/arm/dts/imx6q-display5-u-boot.dtsi
new file mode 100644
index 0000000..b942218
--- /dev/null
+++ b/arch/arm/dts/imx6q-display5-u-boot.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+ or X11
+ */
+
+/*
+ * The minimal augmentation DTS U-Boot file to allow UART5
+ * configuration in the pre-relocation stage of U-Boot
+ * proper.
+ *
+ * As the same UART is already configured in SPL, we don't need
+ * setup pinmux for it again.
+ */
+
+/ {
+ aliases {
+ mmc0 = &usdhc4;
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+
+ aips-bus@2100000 {
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ chosen {
+ stdout-path = &uart5;
+ };
+};
+
+&i2c3 {
+ at24@50 {
+ u-boot,i2c-offset-len = <2>;
+ };
+};
+
+&uart5 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/imx6q-display5.dts b/arch/arm/dts/imx6q-display5.dts
index 50347ff..4e2aa36 100644
--- a/arch/arm/dts/imx6q-display5.dts
+++ b/arch/arm/dts/imx6q-display5.dts
@@ -10,9 +10,361 @@
/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
#include "imx6q.dtsi"
/ {
model = "Liebherr (LWN) display5 i.MX6 Quad Board";
compatible = "lwn,display5", "fsl,imx6q";
+
+ memory@10000000 {
+ device_type = "memory";
+ reg = <0x10000000 0x40000000>;
+ };
+};
+
+&ecspi2 {
+ cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs &pinctrl_ecspi2_flwp>;
+ status = "okay";
+
+ s25fl256s: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <40000000>;
+ reg = <0>;
+
+ partition@0 {
+ label = "SPL (spi)";
+ reg = <0x0 0x20000>;
+ read-only;
+ };
+ partition@1 {
+ label = "u-boot (spi)";
+ reg = <0x20000 0x100000>;
+ read-only;
+ };
+ partition@2 {
+ label = "uboot-env (spi)";
+ reg = <0x120000 0x10000>;
+ };
+ partition@3 {
+ label = "uboot-envr (spi)";
+ reg = <0x130000 0x10000>;
+ };
+ partition@4 {
+ label = "linux-recovery (spi)";
+ reg = <0x140000 0x800000>;
+ };
+ partition@5 {
+ label = "swupdate-fitImg (spi)";
+ reg = <0x940000 0x400000>;
+ };
+ partition@6 {
+ label = "swupdate-initramfs (spi)";
+ reg = <0xD40000 0x800000>;
+ };
+ };
+};
+
+&ecspi3 {
+ cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs &pinctrl_ecspi3_flwp>;
+ status = "okay";
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-handle = <ðernet_phy0>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ethernet_phy0: ethernet-phy@0 {
+ compatible = "marvell,88E1510";
+ device_type = "ethernet-phy";
+ /* Set LED0 control: */
+ /* On - Link, Blink - Activity, Off - No Link */
+ marvell,reg-init = <3 0x10 0 0x1011>;
+ max-speed = <100>;
+ reg = <0>;
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ codec: tfa9879@6c {
+ #sound-dai-cells = <0>;
+ compatible = "nxp,tfa9879";
+ reg = <0x6C>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ at24@50 {
+ compatible = "atmel,24c256";
+ pagesize = <64>;
+ reg = <0x50>;
+ };
+
+ pfuze100: pmic@8 {
+ compatible = "fsl,pfuze100";
+ reg = <0x08>;
+
+ regulators {
+ sw1a_reg: sw1ab {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw1c_reg: sw1c {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw2_reg: sw2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3950000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3a_reg: sw3a {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3b_reg: sw3b {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw4_reg: sw4 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ swbst_reg: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ };
+
+ snvs_reg: vsnvs {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vgen1_reg: vgen1 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ };
+
+ vgen2_reg: vgen2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ };
+
+ vgen3_reg: vgen3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vgen4_reg: vgen4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen5_reg: vgen5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen6_reg: vgen6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5>;
+ status = "okay";
+};
+
+&usdhc4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc4>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1
+ MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1
+ MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1
+ >;
+ };
+
+ pinctrl_ecspi2_cs: ecspi2csgrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1
+ >;
+ };
+
+ pinctrl_ecspi2_flwp: ecspi2flwpgrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0
+ >;
+ };
+
+ pinctrl_ecspi3: ecspi3grp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
+ MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
+ MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
+ >;
+ };
+
+ pinctrl_ecspi3_cs: ecspi3csgrp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b0
+ >;
+ };
+
+ pinctrl_ecspi3_flwp: ecspi3flwpgrp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0
+ >;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+ MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
+ MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart5: uart5grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc4: usdhc4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
+ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
+ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
+ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
+ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
+ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
+ MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
+ MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
+ MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
+ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
+ MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x17059
+ >;
+ };
};
diff --git a/arch/arm/dts/imx6q-logicpd-u-boot.dtsi b/arch/arm/dts/imx6q-logicpd-u-boot.dtsi
new file mode 100644
index 0000000..625bed8
--- /dev/null
+++ b/arch/arm/dts/imx6q-logicpd-u-boot.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Logic PD <aford173@gmail.com>
+ */
+
+#include "imx6qdl-u-boot.dtsi"
+
+&uart1 {
+ u-boot,dm-spl;
+};
+
+&usdhc1 {
+ u-boot,dm-spl;
+};
+
+&usdhc2 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx6qdl-dhcom-pdk2.dtsi b/arch/arm/dts/imx6qdl-dhcom-pdk2.dtsi
new file mode 100644
index 0000000..af4719a
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-dhcom-pdk2.dtsi
@@ -0,0 +1,142 @@
+// SPDX-License-Identifier: (GPL-2.0+)
+/*
+ * Copyright (C) 2015-2019 DH electronics GmbH
+ * Copyright (C) 2018 Marek Vasut <marex@denx.de>
+ */
+
+#include "imx6qdl-dhcom.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ clk_ext_audio_codec: clock-codec {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+
+ sound {
+ compatible = "fsl,imx-audio-sgtl5000";
+ model = "imx-sgtl5000";
+ ssi-controller = <&ssi1>;
+ audio-codec = <&sgtl5000>;
+ audio-routing =
+ "MIC_IN", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "LINE_IN", "Line In Jack",
+ "Headphone Jack", "HP_OUT";
+ mux-int-port = <1>;
+ mux-ext-port = <3>;
+ };
+};
+
+&audmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audmux_ext>;
+ status = "okay";
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c2>;
+ status = "okay";
+};
+
+&i2c2 {
+ sgtl5000: codec@a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ #sound-dai-cells = <0>;
+ clocks = <&clk_ext_audio_codec>;
+ VDDA-supply = <®_3p3v>;
+ VDDIO-supply = <®_3p3v>;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog_base &pinctrl_hog>;
+
+ pinctrl_hog: hog-grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x400120b0
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x400120b0
+ MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x400120b0
+ MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x400120b0
+ MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x120b0
+ MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x400120b0
+ MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x120b0
+ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x120b0
+ MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x400120b0
+ MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x400120b0
+ MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x400120b0
+ MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x400120b0
+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x400120b0
+ MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x400120b0
+ MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x400120b0
+ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x400120b0
+ MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x400120b0
+ MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x400120b0
+ MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x400120b0
+ MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x400120b0
+ MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x400120b0
+ MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x400120b0
+ MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x400120b0
+ MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x400120b0
+ >;
+ };
+
+ pinctrl_audmux_ext: audmux-ext-grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
+ MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
+ MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
+ MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
+ >;
+ };
+
+ pinctrl_enet_1G: enet-1G-grp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x000b0
+ MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x000b1
+ MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x000b1
+ >;
+ };
+
+ pinctrl_pcie: pcie-grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1
+ >;
+ };
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie>;
+ reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&ssi1 {
+ status = "okay";
+};
+
+&usdhc3 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/imx6qdl-dhcom.dtsi b/arch/arm/dts/imx6qdl-dhcom.dtsi
new file mode 100644
index 0000000..1141b6a
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-dhcom.dtsi
@@ -0,0 +1,476 @@
+// SPDX-License-Identifier: (GPL-2.0+)
+/*
+ * Copyright (C) 2015-2019 DH electronics GmbH
+ * Copyright (C) 2018 Marek Vasut <marex@denx.de>
+ */
+
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/imx6qdl-clock.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ aliases {
+ mmc0 = &usdhc2;
+ mmc1 = &usdhc3;
+ mmc2 = &usdhc4;
+ mmc3 = &usdhc1;
+ };
+
+ memory@10000000 {
+ device_type = "memory";
+ reg = <0x10000000 0x40000000>;
+ };
+
+ reg_usb_otg_vbus: regulator-usb-otg-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usb_h1_vbus: regulator-usb-h1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_h1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_3p3v: regulator-3P3V {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ status = "okay";
+};
+
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ status = "okay";
+};
+
+&ecspi1 {
+ cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio4 11 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ status = "okay";
+
+ flash@0 { /* S25FL116K */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ m25p,fast-read;
+ };
+};
+
+&ecspi2 {
+ cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ status = "okay";
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet_100M>;
+ phy-mode = "rmii";
+ phy-handle = <ðphy0>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 { /* SMSC LAN8710Ai */
+ reg = <0>;
+ max-speed = <100>;
+ reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <1000>;
+ reset-post-delay-us = <1000>;
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ ltc3676: pmic@3c {
+ compatible = "lltc,ltc3676";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic_hw300>;
+ reg = <0x3c>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+
+ regulators {
+ sw1_reg: sw1 {
+ regulator-min-microvolt = <787500>;
+ regulator-max-microvolt = <1527272>;
+ lltc,fb-voltage-divider = <100000 110000>;
+ regulator-suspend-mem-microvolt = <1040000>;
+ regulator-ramp-delay = <7000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw2_reg: sw2 {
+ regulator-min-microvolt = <1885714>;
+ regulator-max-microvolt = <3657142>;
+ lltc,fb-voltage-divider = <100000 28000>;
+ regulator-ramp-delay = <7000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3_reg: sw3 {
+ regulator-min-microvolt = <787500>;
+ regulator-max-microvolt = <1527272>;
+ lltc,fb-voltage-divider = <100000 110000>;
+ regulator-suspend-mem-microvolt = <980000>;
+ regulator-ramp-delay = <7000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw4_reg: sw4 {
+ regulator-min-microvolt = <855571>;
+ regulator-max-microvolt = <1659291>;
+ lltc,fb-voltage-divider = <100000 93100>;
+ regulator-ramp-delay = <7000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1_reg: ldo1 {
+ regulator-min-microvolt = <3240306>;
+ regulator-max-microvolt = <3240306>;
+ lltc,fb-voltage-divider = <102000 29400>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2_reg: ldo2 {
+ regulator-min-microvolt = <2484708>;
+ regulator-max-microvolt = <2484708>;
+ lltc,fb-voltage-divider = <100000 41200>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+
+ touchscreen@49 { /* TSC2004 */
+ compatible = "ti,tsc2004";
+ reg = <0x49>;
+ vio-supply = <®_3p3v>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tsc2004_hw300>;
+ interrupts-extended = <&gpio4 14 IRQ_TYPE_EDGE_FALLING>;
+ status = "disabled";
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+
+ rtc@56 {
+ compatible = "rv3029c2";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rtc_hw300>;
+ reg = <0x56>;
+ interrupt-parent = <&gpio7>;
+ interrupts = <12 2>;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog_base>;
+
+ pinctrl_hog_base: hog-base-grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x120b0
+ MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x120b0
+ MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x120b0
+ MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x120b0
+ MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x120b0
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1-grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+ MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
+ MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
+ >;
+ };
+
+ pinctrl_ecspi2: ecspi2-grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1
+ MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1
+ MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1
+ MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x1b0b0
+ >;
+ };
+
+ pinctrl_enet_100M: enet-100M-grp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
+ MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
+ MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
+ MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
+ MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
+ MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
+ MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+ MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x000b0
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b1
+ MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x120b0
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1-grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
+ MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2-grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0
+ MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0
+ >;
+ };
+
+ pinctrl_i2c1: i2c1-grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2-grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3-grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_pmic_hw300: pmic-hw300-grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1B0B0
+ >;
+ };
+
+ pinctrl_rtc_hw300: rtc-hw300-grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x120B0
+ >;
+ };
+
+ pinctrl_tsc2004_hw300: tsc2004-hw300-grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x120B0
+ >;
+ };
+
+ pinctrl_uart1: uart1-grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1
+ MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x4001b0b1
+ MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x4001b0b1
+ MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x4001b0b1
+ MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x4001b0b1
+ MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x4001b0b1
+ >;
+ };
+
+ pinctrl_uart4: uart4-grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart5: uart5-grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x4001b0b1
+ >;
+ };
+
+ pinctrl_usbh1: usbh1-grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x120B0
+ >;
+ };
+
+ pinctrl_usbotg: usbotg-grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2-grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x120B0
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3-grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x120B0
+ >;
+ };
+
+ pinctrl_usdhc4: usdhc4-grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
+ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
+ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
+ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
+ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
+ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
+ MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
+ MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
+ MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
+ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
+ >;
+ };
+};
+
+®_arm {
+ vin-supply = <&sw3_reg>;
+};
+
+®_soc {
+ vin-supply = <&sw1_reg>;
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ uart-has-rtscts;
+ dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
+ dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
+ dcd-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
+ rng-gpios = <&gpio2 31 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&usbh1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh1>;
+ vbus-supply = <®_usb_h1_vbus>;
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbotg {
+ vbus-supply = <®_usb_otg_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ disable-over-current;
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ cd-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
+ keep-power-in-suspend;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ cd-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>;
+ fsl,wp-controller;
+ keep-power-in-suspend;
+ status = "disabled";
+};
+
+&usdhc4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc4>;
+ non-removable;
+ bus-width = <8>;
+ no-1-8-v;
+ keep-power-in-suspend;
+ status = "okay";
+};
diff --git a/arch/arm/dts/imx6ull-colibri.dts b/arch/arm/dts/imx6ull-colibri.dts
index 6c847ab..262205a 100644
--- a/arch/arm/dts/imx6ull-colibri.dts
+++ b/arch/arm/dts/imx6ull-colibri.dts
@@ -12,8 +12,10 @@
compatible = "toradex,colibri-imx6ull", "fsl,imx6ull";
aliases {
+ u-boot,dm-pre-reloc;
mmc0 = &usdhc1;
usb0 = &usbotg1; /* required for ums */
+ display0 = &lcdif;
};
chosen {
@@ -156,6 +158,36 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif_dat
&pinctrl_lcdif_ctrl>;
+ status = "okay";
+ display = <&display0>;
+ u-boot,dm-pre-reloc;
+
+ display0: display0 {
+ bits-per-pixel = <18>;
+ bus-width = <24>;
+ status = "okay";
+
+ display-timings {
+ native-mode = <&timing_vga>;
+ timing_vga: 640x480 {
+ u-boot,dm-pre-reloc;
+ clock-frequency = <25175000>;
+ hactive = <640>;
+ vactive = <480>;
+ hback-porch = <48>;
+ hfront-porch = <16>;
+ vback-porch = <33>;
+ vfront-porch = <10>;
+ hsync-len = <96>;
+ vsync-len = <2>;
+
+ de-active = <1>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pixelclk-active = <0>;
+ };
+ };
+ };
};
/* PWM <A> */
diff --git a/arch/arm/dts/imx7-colibri.dtsi b/arch/arm/dts/imx7-colibri.dtsi
index 81717c2..308e0b2 100644
--- a/arch/arm/dts/imx7-colibri.dtsi
+++ b/arch/arm/dts/imx7-colibri.dtsi
@@ -113,29 +113,34 @@
};
&lcdif {
- u-boot,dm-pre-reloc;
status = "okay";
+ display = <&display0>;
+ u-boot,dm-pre-reloc;
- display-timings {
- native-mode = <&timing_vga>;
+ display0: display0 {
+ bits-per-pixel = <18>;
+ bus-width = <24>;
+ status = "okay";
- /* Standard VGA timing */
- timing_vga: 640x480 {
- u-boot,dm-pre-reloc;
- clock-frequency = <25175000>;
- hactive = <640>;
- vactive = <480>;
- hback-porch = <48>;
- hfront-porch = <16>;
- vback-porch = <33>;
- vfront-porch = <10>;
- hsync-len = <96>;
- vsync-len = <2>;
+ display-timings {
+ native-mode = <&timing_vga>;
+ timing_vga: 640x480 {
+ u-boot,dm-pre-reloc;
+ clock-frequency = <25175000>;
+ hactive = <640>;
+ vactive = <480>;
+ hback-porch = <48>;
+ hfront-porch = <16>;
+ vback-porch = <33>;
+ vfront-porch = <10>;
+ hsync-len = <96>;
+ vsync-len = <2>;
- de-active = <1>;
- hsync-active = <0>;
- vsync-active = <0>;
- pixelclk-active = <0>;
+ de-active = <1>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pixelclk-active = <0>;
+ };
};
};
};
diff --git a/arch/arm/dts/imx7d-pico.dtsi b/arch/arm/dts/imx7d-pico.dtsi
index 9f1fe68..7cd8be2 100644
--- a/arch/arm/dts/imx7d-pico.dtsi
+++ b/arch/arm/dts/imx7d-pico.dtsi
@@ -10,6 +10,7 @@
/ {
aliases {
mmc0 = &usdhc3;
+ usb0 = &usbotg1;
};
/* Will be filled by the bootloader */
@@ -296,6 +297,7 @@
&usbotg1 {
vbus-supply = <®_usb_otg1_vbus>;
+ dr_mode = "peripheral";
status = "okay";
};
diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi
index adcd634..0f5da9a 100644
--- a/arch/arm/dts/k3-am65-main.dtsi
+++ b/arch/arm/dts/k3-am65-main.dtsi
@@ -5,6 +5,9 @@
* Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
*/
+#include <dt-bindings/phy/phy-am654-serdes.h>
+#include <dt-bindings/phy/phy.h>
+
&cbass_main {
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
@@ -69,4 +72,183 @@
clock-frequency = <48000000>;
current-speed = <115200>;
};
+
+ main_pmx0: pinmux@11c000 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0x11c000 0x0 0x2e4>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ };
+
+ main_pmx1: pinmux@11c2e8 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0x11c2e8 0x0 0x24>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ };
+
+ sdhci0: sdhci@4f80000 {
+ compatible = "ti,am654-sdhci-5.1";
+ reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
+ power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
+ clock-names = "clk_ahb", "clk_xin";
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ ti,otap-del-sel = <0x2>;
+ ti,trm-icp = <0x8>;
+ dma-coherent;
+ };
+
+ main_i2c0: i2c@2000000 {
+ compatible = "ti,am654-i2c", "ti,omap4-i2c";
+ reg = <0x0 0x2000000 0x0 0x100>;
+ interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "fck";
+ clocks = <&k3_clks 110 1>;
+ power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ main_i2c1: i2c@2010000 {
+ compatible = "ti,am654-i2c", "ti,omap4-i2c";
+ reg = <0x0 0x2010000 0x0 0x100>;
+ interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "fck";
+ clocks = <&k3_clks 111 1>;
+ power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ main_i2c2: i2c@2020000 {
+ compatible = "ti,am654-i2c", "ti,omap4-i2c";
+ reg = <0x0 0x2020000 0x0 0x100>;
+ interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "fck";
+ clocks = <&k3_clks 112 1>;
+ power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ main_i2c3: i2c@2030000 {
+ compatible = "ti,am654-i2c", "ti,omap4-i2c";
+ reg = <0x0 0x2030000 0x0 0x100>;
+ interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "fck";
+ clocks = <&k3_clks 113 1>;
+ power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ scm_conf: scm_conf@100000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0 0x00100000 0 0x1c000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x00100000 0x1c000>;
+
+ serdes_mux: mux-controller {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
+ <0x4090 0x3>; /* SERDES1 lane select */
+ };
+
+ pcie0_mode: pcie-mode@4060 {
+ compatible = "syscon";
+ reg = <0x00004060 0x4>;
+ };
+
+ pcie1_mode: pcie-mode@4070 {
+ compatible = "syscon";
+ reg = <0x00004070 0x4>;
+ };
+
+ serdes0_clk: serdes_clk@4080 {
+ compatible = "syscon";
+ reg = <0x00004080 0x4>;
+ };
+
+ serdes1_clk: serdes_clk@4090 {
+ compatible = "syscon";
+ reg = <0x00004090 0x4>;
+ };
+
+ pcie_devid: pcie-devid@210 {
+ compatible = "syscon";
+ reg = <0x00000210 0x4>;
+ };
+ };
+
+ serdes0: serdes@900000 {
+ compatible = "ti,phy-am654-serdes";
+ reg = <0x0 0x900000 0x0 0x2000>;
+ reg-names = "serdes";
+ #phy-cells = <2>;
+ power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>;
+ clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
+ assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
+ assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
+ ti,serdes-clk = <&serdes0_clk>;
+ mux-controls = <&serdes_mux 0>;
+ #clock-cells = <1>;
+ };
+
+ serdes1: serdes@910000 {
+ compatible = "ti,phy-am654-serdes";
+ reg = <0x0 0x910000 0x0 0x2000>;
+ reg-names = "serdes";
+ #phy-cells = <2>;
+ power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>;
+ clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk";
+ assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>;
+ assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>;
+ ti,serdes-clk = <&serdes1_clk>;
+ mux-controls = <&serdes_mux 1>;
+ #clock-cells = <1>;
+ };
+
+ pcie0_rc: pcie@5500000 {
+ compatible = "ti,am654-pcie-rc";
+ reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
+ reg-names = "app", "dbics", "config", "atu";
+ power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000
+ 0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
+ ti,syscon-pcie-id = <&pcie_devid>;
+ ti,syscon-pcie-mode = <&pcie0_mode>;
+ bus-range = <0x0 0xff>;
+ status = "disabled";
+ device_type = "pci";
+ num-lanes = <1>;
+ num-ob-windows = <16>;
+ num-viewport = <16>;
+ max-link-speed = <3>;
+ interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie0_intc 0>, /* INT A */
+ <0 0 0 2 &pcie0_intc 0>, /* INT B */
+ <0 0 0 3 &pcie0_intc 0>, /* INT C */
+ <0 0 0 4 &pcie0_intc 0>; /* INT D */
+ msi-map = <0x0 &gic_its 0x0 0x10000>;
+
+ pcie0_intc: legacy-interrupt-controller@1 {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
};
diff --git a/arch/arm/dts/k3-am65-mcu.dtsi b/arch/arm/dts/k3-am65-mcu.dtsi
index 8c611d1..c9bfd9b 100644
--- a/arch/arm/dts/k3-am65-mcu.dtsi
+++ b/arch/arm/dts/k3-am65-mcu.dtsi
@@ -15,4 +15,15 @@
clock-frequency = <96000000>;
current-speed = <115200>;
};
+
+ mcu_i2c0: i2c@40b00000 {
+ compatible = "ti,am654-i2c", "ti,omap4-i2c";
+ reg = <0x0 0x40b00000 0x0 0x100>;
+ interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "fck";
+ clocks = <&k3_clks 114 1>;
+ power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
+ };
};
diff --git a/arch/arm/dts/k3-am65-wakeup.dtsi b/arch/arm/dts/k3-am65-wakeup.dtsi
index 1f591ef..2676d60 100644
--- a/arch/arm/dts/k3-am65-wakeup.dtsi
+++ b/arch/arm/dts/k3-am65-wakeup.dtsi
@@ -20,7 +20,7 @@
k3_pds: power-controller {
compatible = "ti,sci-pm-domain";
- #power-domain-cells = <1>;
+ #power-domain-cells = <2>;
};
k3_clks: clocks {
@@ -34,6 +34,14 @@
};
};
+ wkup_pmx0: pinmux@4301c000 {
+ compatible = "pinctrl-single";
+ reg = <0x4301c000 0x118>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ };
+
wkup_uart0: serial@42300000 {
compatible = "ti,am654-uart";
reg = <0x42300000 0x100>;
@@ -43,4 +51,15 @@
clock-frequency = <48000000>;
current-speed = <115200>;
};
+
+ wkup_i2c0: i2c@42120000 {
+ compatible = "ti,am654-i2c", "ti,omap4-i2c";
+ reg = <0x42120000 0x100>;
+ interrupts = <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "fck";
+ clocks = <&k3_clks 115 1>;
+ power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
+ };
};
diff --git a/arch/arm/dts/k3-am65.dtsi b/arch/arm/dts/k3-am65.dtsi
index 3d4bf36..a1467a4 100644
--- a/arch/arm/dts/k3-am65.dtsi
+++ b/arch/arm/dts/k3-am65.dtsi
@@ -8,6 +8,8 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/k3.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
/ {
model = "Texas Instruments K3 AM654 SoC";
@@ -22,6 +24,12 @@
serial2 = &main_uart0;
serial3 = &main_uart1;
serial4 = &main_uart2;
+ i2c0 = &wkup_i2c0;
+ i2c1 = &mcu_i2c0;
+ i2c2 = &main_i2c0;
+ i2c3 = &main_i2c1;
+ i2c4 = &main_i2c2;
+ i2c5 = &main_i2c3;
};
chosen { };
@@ -61,9 +69,11 @@
<0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
<0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
<0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
+ <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
/* MCUSS Range */
<0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
<0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
+ <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
@@ -75,6 +85,7 @@
#size-cells = <2>;
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
<0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */
+ <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
index f5c8253..8589f76 100644
--- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
@@ -5,6 +5,7 @@
#include <dt-bindings/pinctrl/k3.h>
#include <dt-bindings/dma/k3-udma.h>
+#include <dt-bindings/net/ti-dp83867.h>
/ {
chosen {
@@ -13,57 +14,28 @@
aliases {
serial2 = &main_uart0;
+ ethernet0 = &cpsw_port1;
};
};
&cbass_main{
u-boot,dm-spl;
- main_pmx0: pinmux@11c000 {
- compatible = "pinctrl-single";
- reg = <0x0 0x11c000 0x0 0x2e4>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0xffffffff>;
- };
-
- main_pmx1: pinmux@11c2e8 {
- compatible = "pinctrl-single";
- reg = <0x0 0x11c2e8 0x0 0x24>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0xffffffff>;
- };
-
- sdhci0: sdhci@04F80000 {
- compatible = "arasan,sdhci-5.1";
- reg = <0x0 0x4F80000 0x0 0x1000>,
- <0x0 0x4F90000 0x0 0x400>;
- clocks = <&k3_clks 47 1>;
- power-domains = <&k3_pds 47>;
- max-frequency = <25000000>;
- };
-
sdhci1: sdhci@04FA0000 {
- compatible = "arasan,sdhci-5.1";
+ compatible = "ti,am654-sdhci-5.1";
reg = <0x0 0x4FA0000 0x0 0x1000>,
<0x0 0x4FB0000 0x0 0x400>;
clocks = <&k3_clks 48 1>;
- power-domains = <&k3_pds 48>;
+ power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
max-frequency = <25000000>;
+ ti,otap-del-sel = <0x2>;
+ ti,trm-icp = <0x8>;
};
};
&cbass_mcu {
u-boot,dm-spl;
- wkup_pmx0: pinmux@4301c000 {
- compatible = "pinctrl-single";
- reg = <0x0 0x4301c000 0x0 0x118>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0xffffffff>;
- };
navss_mcu: navss-mcu {
compatible = "simple-bus";
@@ -110,6 +82,116 @@
dma-coherent;
};
};
+
+ mcu_conf: scm_conf@40f00000 {
+ compatible = "syscon";
+ reg = <0x0 0x40f00000 0x0 0x20000>;
+ };
+
+ mcu_cpsw: cpsw_nuss@046000000 {
+ compatible = "ti,am654-cpsw-nuss";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x46000000 0x0 0x200000>;
+ reg-names = "cpsw_nuss";
+ ranges;
+ dma-coherent;
+ clocks = <&k3_clks 5 10>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
+ ti,psil-base = <0x7000>;
+
+ dmas = <&mcu_udmap &mcu_cpsw 0 UDMA_DIR_TX>,
+ <&mcu_udmap &mcu_cpsw 1 UDMA_DIR_TX>,
+ <&mcu_udmap &mcu_cpsw 2 UDMA_DIR_TX>,
+ <&mcu_udmap &mcu_cpsw 3 UDMA_DIR_TX>,
+ <&mcu_udmap &mcu_cpsw 4 UDMA_DIR_TX>,
+ <&mcu_udmap &mcu_cpsw 5 UDMA_DIR_TX>,
+ <&mcu_udmap &mcu_cpsw 6 UDMA_DIR_TX>,
+ <&mcu_udmap &mcu_cpsw 7 UDMA_DIR_TX>,
+ <&mcu_udmap &mcu_cpsw 0 UDMA_DIR_RX>;
+ dma-names = "tx0", "tx1", "tx2", "tx3",
+ "tx4", "tx5", "tx6", "tx7",
+ "rx";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ host: host@0 {
+ reg = <0>;
+ ti,label = "host";
+ };
+
+ cpsw_port1: port@1 {
+ reg = <1>;
+ ti,mac-only;
+ ti,label = "port1";
+ ti,syscon-efuse = <&mcu_conf 0x200>;
+ };
+ };
+
+ davinci_mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus_freq = <1000000>;
+ };
+
+ ti,psil-config0 {
+ linux,udma-mode = <UDMA_PKT_MODE>;
+ statictr-type = <PSIL_STATIC_TR_NONE>;
+ ti,needs-epib;
+ ti,psd-size = <16>;
+ };
+
+ ti,psil-config1 {
+ linux,udma-mode = <UDMA_PKT_MODE>;
+ statictr-type = <PSIL_STATIC_TR_NONE>;
+ ti,needs-epib;
+ ti,psd-size = <16>;
+ };
+
+ ti,psil-config2 {
+ linux,udma-mode = <UDMA_PKT_MODE>;
+ statictr-type = <PSIL_STATIC_TR_NONE>;
+ ti,needs-epib;
+ ti,psd-size = <16>;
+ };
+
+ ti,psil-config3 {
+ linux,udma-mode = <UDMA_PKT_MODE>;
+ statictr-type = <PSIL_STATIC_TR_NONE>;
+ ti,needs-epib;
+ ti,psd-size = <16>;
+ };
+
+ ti,psil-config4 {
+ linux,udma-mode = <UDMA_PKT_MODE>;
+ statictr-type = <PSIL_STATIC_TR_NONE>;
+ ti,needs-epib;
+ ti,psd-size = <16>;
+ };
+
+ ti,psil-config5 {
+ linux,udma-mode = <UDMA_PKT_MODE>;
+ statictr-type = <PSIL_STATIC_TR_NONE>;
+ ti,needs-epib;
+ ti,psd-size = <16>;
+ };
+
+ ti,psil-config6 {
+ linux,udma-mode = <UDMA_PKT_MODE>;
+ statictr-type = <PSIL_STATIC_TR_NONE>;
+ ti,needs-epib;
+ ti,psd-size = <16>;
+ };
+
+ ti,psil-config7 {
+ linux,udma-mode = <UDMA_PKT_MODE>;
+ statictr-type = <PSIL_STATIC_TR_NONE>;
+ ti,needs-epib;
+ ti,psd-size = <16>;
+ };
+ };
};
&cbass_wakeup {
@@ -140,6 +222,14 @@
u-boot,dm-spl;
};
+&wkup_pmx0 {
+ u-boot,dm-spl;
+
+ wkup_i2c0_pins_default {
+ u-boot,dm-spl;
+ };
+};
+
&main_pmx0 {
u-boot,dm-spl;
main_uart0_pins_default: main_uart0_pins_default {
@@ -164,7 +254,8 @@
AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
- AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
+ AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */
+ AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
>;
u-boot,dm-spl;
};
@@ -189,6 +280,32 @@
u-boot,dm-spl;
};
+&wkup_pmx0 {
+ mcu_cpsw_pins_default: mcu_cpsw_pins_default {
+ pinctrl-single,pins = <
+ AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
+ AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
+ AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
+ AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
+ AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
+ AM65X_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
+ AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
+ AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
+ AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
+ AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
+ AM65X_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
+ AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
+ >;
+ };
+
+ mcu_mdio_pins_default: mcu_mdio1_pins_default {
+ pinctrl-single,pins = <
+ AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
+ AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
+ >;
+ };
+};
+
&main_uart0 {
u-boot,dm-spl;
pinctrl-names = "default";
@@ -198,11 +315,6 @@
&sdhci0 {
u-boot,dm-spl;
- status = "okay";
- non-removable;
- bus-width = <8>;
- pinctrl-names = "default";
- pinctrl-0 = <&main_mmc0_pins_default>;
};
&sdhci1 {
@@ -211,4 +323,41 @@
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
sdhci-caps-mask = <0x7 0x0>;
+ ti,driver-strength-ohm = <50>;
+};
+
+&mcu_cpsw {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+};
+
+&davinci_mdio {
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ /* TODO: phy reset: TCA9555RTWR(i2c:0x21)[p04].GPIO_MCU_RGMII_RSTN */
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+};
+
+&cpsw_port1 {
+ phy-mode = "rgmii-id";
+ phy-handle = <&phy0>;
+};
+
+&mcu_cpsw {
+ reg = <0x0 0x46000000 0x0 0x200000>,
+ <0x0 0x40f00200 0x0 0x2>;
+ reg-names = "cpsw_nuss", "mac_efuse";
+
+ cpsw-phy-sel@40f04040 {
+ compatible = "ti,am654-cpsw-phy-sel";
+ reg= <0x0 0x40f04040 0x0 0x4>;
+ reg-names = "gmii-sel";
+ };
+};
+
+&wkup_i2c0 {
+ u-boot,dm-spl;
};
diff --git a/arch/arm/dts/k3-am654-base-board.dts b/arch/arm/dts/k3-am654-base-board.dts
index af6956f..e73b9aa 100644
--- a/arch/arm/dts/k3-am654-base-board.dts
+++ b/arch/arm/dts/k3-am654-base-board.dts
@@ -6,6 +6,7 @@
/dts-v1/;
#include "k3-am654.dtsi"
+#include <dt-bindings/pinctrl/k3.h>
/ {
compatible = "ti,am654-evm", "ti,am654";
@@ -34,3 +35,52 @@
};
};
};
+
+&main_pmx0 {
+ main_mmc0_pins_default: main_mmc0_pins_default {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
+ AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
+ AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
+ AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
+ AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
+ AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
+ AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
+ AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
+ AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
+ AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
+ AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */
+ AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
+ >;
+ };
+};
+
+&wkup_pmx0 {
+ wkup_i2c0_pins_default: wkup-i2c0-pins-default {
+ pinctrl-single,pins = <
+ AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */
+ AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */
+ >;
+ };
+};
+
+&sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mmc0_pins_default>;
+ bus-width = <8>;
+ non-removable;
+ ti,driver-strength-ohm = <50>;
+};
+
+&wkup_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_i2c0_pins_default>;
+ clock-frequency = <400000>;
+
+ tca9554: gpio@38 {
+ compatible = "nxp,pca9554";
+ reg = <0x38>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
diff --git a/arch/arm/dts/k3-am654-ddr.dtsi b/arch/arm/dts/k3-am654-ddr.dtsi
index 964eb17..622a3ed 100644
--- a/arch/arm/dts/k3-am654-ddr.dtsi
+++ b/arch/arm/dts/k3-am654-ddr.dtsi
@@ -11,8 +11,8 @@
<0x0 0x02988000 0x0 0x2000>;
reg-names = "ss", "ctl", "phy";
clocks = <&k3_clks 20 0>;
- power-domains = <&k3_pds 20>,
- <&k3_pds 244>;
+ power-domains = <&k3_pds 20 TI_SCI_PD_SHARED>,
+ <&k3_pds 244 TI_SCI_PD_SHARED>;
assigned-clocks = <&k3_clks 20 1>;
assigned-clock-rates = <DDR_PLL_FREQUENCY>;
u-boot,dm-spl;
diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts
index a07038b..7ed307f 100644
--- a/arch/arm/dts/k3-am654-r5-base-board.dts
+++ b/arch/arm/dts/k3-am654-r5-base-board.dts
@@ -32,8 +32,8 @@
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x0 0x00a90000 0x0 0x10>;
- power-domains = <&k3_pds 61>,
- <&k3_pds 202>;
+ power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+ <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 202 0>;
assigned-clocks = <&k3_clks 202 0>;
assigned-clock-rates = <800000000>;
@@ -96,6 +96,12 @@
u-boot,dm-spl;
};
+ clk_200mhz: dummy_clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ u-boot,dm-spl;
+ };
};
&dmsc {
@@ -112,6 +118,10 @@
status = "okay";
};
+&main_uart0 {
+ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
+};
+
&wkup_pmx0 {
u-boot,dm-spl;
wkup_uart0_pins_default: wkup_uart0_pins_default {
@@ -130,6 +140,32 @@
>;
u-boot,dm-spl;
};
+
+ wkup_i2c0_pins_default: wkup-i2c0-pins-default {
+ pinctrl-single,pins = <
+ AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */
+ AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */
+ >;
+ };
+};
+
+&main_pmx0 {
+ u-boot,dm-spl;
+ main_mmc0_pins_default: main_mmc0_pins_default {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
+ AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
+ AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
+ AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
+ AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
+ AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
+ AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
+ AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
+ AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
+ AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
+ AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
+ >;
+ };
};
&memorycontroller {
@@ -137,3 +173,23 @@
pinctrl-names = "default";
pinctrl-0 = <&wkup_vtt_pins_default>;
};
+
+&sdhci0 {
+ clock-names = "clk_xin";
+ clocks = <&clk_200mhz>;
+ /delete-property/ power-domains;
+ ti,driver-strength-ohm = <50>;
+};
+
+&sdhci1 {
+ clock-names = "clk_xin";
+ clocks = <&clk_200mhz>;
+ /delete-property/ power-domains;
+ ti,driver-strength-ohm = <50>;
+};
+
+&wkup_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_i2c0_pins_default>;
+ clock-frequency = <400000>;
+};
diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
new file mode 100644
index 0000000..541da22
--- /dev/null
+++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+/ {
+ chosen {
+ stdout-path = "serial2:115200n8";
+ tick-timer = &timer1;
+ };
+};
+
+&cbass_main{
+ u-boot,dm-spl;
+};
+
+&cbass_mcu_wakeup {
+ u-boot,dm-spl;
+
+ timer1: timer@40400000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x40400000 0x0 0x80>;
+ ti,timer-alwon;
+ clock-frequency = <25000000>;
+ u-boot,dm-spl;
+ };
+};
+
+&secure_proxy_main {
+ u-boot,dm-spl;
+};
+
+&dmsc {
+ u-boot,dm-spl;
+ k3_sysreset: sysreset-controller {
+ compatible = "ti,sci-sysreset";
+ u-boot,dm-spl;
+ };
+};
+
+&k3_pds {
+ u-boot,dm-spl;
+};
+
+&k3_clks {
+ u-boot,dm-spl;
+};
+
+&k3_reset {
+ u-boot,dm-spl;
+};
+
+&wkup_pmx0 {
+ u-boot,dm-spl;
+};
+
+&main_pmx0 {
+ u-boot,dm-spl;
+};
+
+&main_uart0 {
+ u-boot,dm-spl;
+};
+
+&mcu_uart0 {
+ u-boot,dm-spl;
+};
+
+&main_sdhci0 {
+ u-boot,dm-spl;
+};
+
+&main_sdhci1 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/k3-j721e-common-proc-board.dts b/arch/arm/dts/k3-j721e-common-proc-board.dts
new file mode 100644
index 0000000..b5b8c3c
--- /dev/null
+++ b/arch/arm/dts/k3-j721e-common-proc-board.dts
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-j721e-som-p0.dtsi"
+
+/ {
+ chosen {
+ stdout-path = "serial2:115200n8";
+ bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
+ };
+};
+
+&wkup_uart0 {
+ /* Wakeup UART is used by System firmware */
+ status = "disabled";
+};
+
+&main_uart3 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_uart5 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_uart6 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_uart7 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_uart8 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_uart9 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_sdhci0 {
+ /* eMMC */
+ voltage-ranges = <1800 1800>;
+ non-removable;
+ ti,driver-strength-ohm = <50>;
+};
+
+&main_sdhci1 {
+ /* SD/MMC */
+ voltage-ranges = <1800 1800 3300 3300>;
+ ti,driver-strength-ohm = <50>;
+};
diff --git a/arch/arm/dts/k3-j721e-main.dtsi b/arch/arm/dts/k3-j721e-main.dtsi
new file mode 100644
index 0000000..3445784
--- /dev/null
+++ b/arch/arm/dts/k3-j721e-main.dtsi
@@ -0,0 +1,231 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for J721E SoC Family Main Domain peripherals
+ *
+ * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+&cbass_main {
+ msmc_ram: sram@70000000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x70000000 0x0 0x800000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x70000000 0x800000>;
+
+ atf-sram@0 {
+ reg = <0x0 0x20000>;
+ };
+ };
+
+ gic500: interrupt-controller@1800000 {
+ compatible = "arm,gic-v3";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
+ <0x00 0x01900000 0x00 0x100000>; /* GICR */
+
+ /* vcpumntirq: virtual CPU interface maintenance interrupt */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ gic_its: gic-its@18200000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x00 0x01820000 0x00 0x10000>;
+ socionext,synquacer-pre-its = <0x1000000 0x400000>;
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ };
+
+ smmu0: smmu@36600000 {
+ compatible = "arm,smmu-v3";
+ reg = <0x0 0x36600000 0x0 0x100000>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "eventq", "gerror";
+ #iommu-cells = <1>;
+ };
+
+ secure_proxy_main: mailbox@32c00000 {
+ compatible = "ti,am654-secure-proxy";
+ #mbox-cells = <1>;
+ reg-names = "target_data", "rt", "scfg";
+ reg = <0x00 0x32c00000 0x00 0x100000>,
+ <0x00 0x32400000 0x00 0x100000>,
+ <0x00 0x32800000 0x00 0x100000>;
+ interrupt-names = "rx_011";
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ main_pmx0: pinmux@11c000 {
+ compatible = "pinctrl-single";
+ /* Proxy 0 addressing */
+ reg = <0x0 0x11c000 0x0 0x2b4>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ };
+
+ main_uart0: serial@2800000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02800000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 146 0>;
+ clock-names = "fclk";
+ };
+
+ main_uart1: serial@2810000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02810000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 278 0>;
+ clock-names = "fclk";
+ };
+
+ main_uart2: serial@2820000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02820000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 279 0>;
+ clock-names = "fclk";
+ };
+
+ main_uart3: serial@2830000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02830000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 280 0>;
+ clock-names = "fclk";
+ };
+
+ main_uart4: serial@2840000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02840000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 281 0>;
+ clock-names = "fclk";
+ };
+
+ main_uart5: serial@2850000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02850000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 282 0>;
+ clock-names = "fclk";
+ };
+
+ main_uart6: serial@2860000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02860000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 283 0>;
+ clock-names = "fclk";
+ };
+
+ main_uart7: serial@2870000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02870000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 284 0>;
+ clock-names = "fclk";
+ };
+
+ main_uart8: serial@2880000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02880000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 285 0>;
+ clock-names = "fclk";
+ };
+
+ main_uart9: serial@2890000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02890000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 286 0>;
+ clock-names = "fclk";
+ };
+
+ main_sdhci0: sdhci@4f80000 {
+ compatible = "ti,j721e-sdhci-8bit";
+ reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&k3_clks 91 1>, <&k3_clks 91 0>;
+ assigned-clocks = <&k3_clks 91 1>;
+ assigned-clock-parents = <&k3_clks 91 2>;
+ bus-width = <8>;
+ ti,otap-del-sel = <0x2>;
+ ti,trm-icp = <0x8>;
+ dma-coherent;
+ };
+
+ main_sdhci1: sdhci@4fb0000 {
+ compatible = "ti,j721e-sdhci-4bit";
+ reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&k3_clks 92 0>, <&k3_clks 92 5>;
+ assigned-clocks = <&k3_clks 92 0>;
+ assigned-clock-parents = <&k3_clks 92 1>;
+ ti,otap-del-sel = <0x2>;
+ ti,trm-icp = <0x8>;
+ dma-coherent;
+ };
+};
diff --git a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
new file mode 100644
index 0000000..1175fa9
--- /dev/null
+++ b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals
+ *
+ * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+&cbass_mcu_wakeup {
+ dmsc: dmsc@44083000 {
+ compatible = "ti,k2g-sci";
+ ti,host-id = <12>;
+
+ mbox-names = "rx", "tx";
+
+ mboxes= <&secure_proxy_main 11>,
+ <&secure_proxy_main 13>;
+
+ reg-names = "debug_messages";
+ reg = <0x00 0x44083000 0x0 0x1000>;
+
+ k3_pds: power-controller {
+ compatible = "ti,sci-pm-domain";
+ #power-domain-cells = <2>;
+ };
+
+ k3_clks: clocks {
+ compatible = "ti,k2g-sci-clk";
+ #clock-cells = <2>;
+ ti,scan-clocks-from-dt;
+ };
+
+ k3_reset: reset-controller {
+ compatible = "ti,sci-reset";
+ #reset-cells = <2>;
+ };
+ };
+
+ wkup_pmx0: pinmux@4301c000 {
+ compatible = "pinctrl-single";
+ /* Proxy 0 addressing */
+ reg = <0x00 0x4301c000 0x00 0x178>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ };
+
+ wkup_uart0: serial@42300000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x42300000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 287 0>;
+ clock-names = "fclk";
+ };
+
+ mcu_uart0: serial@40a00000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x40a00000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <96000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 149 0>;
+ clock-names = "fclk";
+ };
+};
diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
new file mode 100644
index 0000000..815e334
--- /dev/null
+++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
@@ -0,0 +1,141 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-j721e-som-p0.dtsi"
+
+/ {
+ aliases {
+ remoteproc0 = &sysctrler;
+ remoteproc1 = &a72_0;
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ tick-timer = &timer1;
+ };
+
+ a72_0: a72@0 {
+ compatible = "ti,am654-rproc";
+ reg = <0x0 0x00a90000 0x0 0x10>;
+ power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+ <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
+ resets = <&k3_reset 202 0>;
+ assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;
+ assigned-clock-rates = <2000000000>, <200000000>;
+ ti,sci = <&dmsc>;
+ ti,sci-proc-id = <32>;
+ ti,sci-host-id = <10>;
+ u-boot,dm-spl;
+ };
+
+ clk_200mhz: dummy_clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ u-boot,dm-spl;
+ };
+};
+
+&cbass_mcu_wakeup {
+ mcu_secproxy: secproxy@28380000 {
+ u-boot,dm-spl;
+ compatible = "ti,am654-secure-proxy";
+ reg = <0x0 0x2a380000 0x0 0x80000>,
+ <0x0 0x2a400000 0x0 0x80000>,
+ <0x0 0x2a480000 0x0 0x80000>;
+ reg-names = "rt", "scfg", "target_data";
+ #mbox-cells = <1>;
+ };
+
+ sysctrler: sysctrler {
+ u-boot,dm-spl;
+ compatible = "ti,am654-system-controller";
+ mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
+ mbox-names = "tx", "rx";
+ };
+};
+
+&dmsc {
+ mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
+ mbox-names = "tx", "rx", "notify";
+ ti,host-id = <4>;
+ ti,secure-host;
+};
+
+&wkup_pmx0 {
+ wkup_uart0_pins_default: wkup_uart0_pins_default {
+ u-boot,dm-spl;
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
+ J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
+ >;
+ };
+
+ mcu_uart0_pins_default: mcu_uart0_pins_default {
+ u-boot,dm-spl;
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xe8, PIN_INPUT, 0) /* (H29) WKUP_GPIO0_14.MCU_UART0_CTSn */
+ J721E_WKUP_IOPAD(0xec, PIN_OUTPUT, 0) /* (J27) WKUP_GPIO0_15.MCU_UART0_RTSn */
+ J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */
+ J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0) /* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
+ >;
+ };
+};
+
+&main_pmx0 {
+ main_uart0_pins_default: main_uart0_pins_default {
+ u-boot,dm-spl;
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1d4, PIN_INPUT, 1) /* (Y3) SPI1_CS0.UART0_CTSn */
+ J721E_IOPAD(0x1c0, PIN_OUTPUT, 1) /* (AA2) SPI0_CS0.UART0_RTSn */
+ J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
+ J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
+ >;
+ };
+};
+
+&wkup_uart0 {
+ u-boot,dm-spl;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_uart0_pins_default>;
+ status = "okay";
+};
+
+&mcu_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_uart0_pins_default>;
+ status = "okay";
+};
+
+&main_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart0_pins_default>;
+ status = "okay";
+ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
+};
+
+&main_sdhci0 {
+ /delete-property/ power-domains;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ clock-names = "clk_xin";
+ clocks = <&clk_200mhz>;
+ ti,driver-strength-ohm = <50>;
+ non-removable;
+ bus-width = <8>;
+};
+
+&main_sdhci1 {
+ /delete-property/ power-domains;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ clock-names = "clk_xin";
+ clocks = <&clk_200mhz>;
+ ti,driver-strength-ohm = <50>;
+};
+
+#include "k3-j721e-common-proc-board-u-boot.dtsi"
diff --git a/arch/arm/dts/k3-j721e-som-p0.dtsi b/arch/arm/dts/k3-j721e-som-p0.dtsi
new file mode 100644
index 0000000..1884fc7
--- /dev/null
+++ b/arch/arm/dts/k3-j721e-som-p0.dtsi
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-j721e.dtsi"
+
+/ {
+ memory@80000000 {
+ device_type = "memory";
+ /* 4G RAM */
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
+ <0x00000008 0x80000000 0x00000000 0x80000000>;
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ secure_ddr: optee@9e800000 {
+ reg = <0x00 0x9e800000 0x00 0x01800000>;
+ alignment = <0x1000>;
+ no-map;
+ };
+ };
+};
diff --git a/arch/arm/dts/k3-j721e.dtsi b/arch/arm/dts/k3-j721e.dtsi
new file mode 100644
index 0000000..aea17e2
--- /dev/null
+++ b/arch/arm/dts/k3-j721e.dtsi
@@ -0,0 +1,177 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for J721E SoC Family
+ *
+ * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/k3.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+/ {
+ model = "Texas Instruments K3 J721E SoC";
+ compatible = "ti,j721e";
+ interrupt-parent = <&gic500>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &wkup_uart0;
+ serial1 = &mcu_uart0;
+ serial2 = &main_uart0;
+ serial3 = &main_uart1;
+ serial4 = &main_uart2;
+ serial5 = &main_uart3;
+ serial6 = &main_uart4;
+ serial7 = &main_uart5;
+ serial8 = &main_uart6;
+ serial9 = &main_uart7;
+ serial10 = &main_uart8;
+ serial11 = &main_uart9;
+ };
+
+ chosen { };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu-map {
+ cluster0: cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+
+ };
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a72";
+ reg = <0x000>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0xC000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&L2_0>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a72";
+ reg = <0x001>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0xC000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&L2_0>;
+ };
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <0x100000>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ next-level-cache = <&msmc_l3>;
+ };
+
+ msmc_l3: l3-cache0 {
+ compatible = "cache";
+ cache-level = <3>;
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+
+ psci: psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+ };
+
+ a72_timer0: timer-cl0-cpu0 {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
+ };
+
+ pmu: pmu {
+ compatible = "arm,armv8-pmuv3";
+ /* Recommendation from GIC500 TRM Table A.3 */
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ cbass_main: interconnect@100000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
+ <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
+ <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
+ <0x00 0x00A40000 0x00 0x00A40000 0x00 0x00000800>, /* timesync router */
+ <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
+ <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
+ <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/
+ <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
+ <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */
+ <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
+ <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* C66_1 */
+ <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
+ /* MCUSS_WKUP Range */
+ <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
+ <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
+ <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
+ <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
+ <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
+ <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
+ <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
+ <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
+ <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
+ <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
+ <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
+ <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>,
+ <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
+ <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
+
+ cbass_mcu_wakeup: interconnect@28380000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
+ <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
+ <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
+ <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
+ <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
+ <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
+ <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
+ <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
+ <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
+ <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
+ <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
+ <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
+ <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/
+ };
+ };
+};
+
+/* Now include the peripherals for each bus segments */
+#include "k3-j721e-main.dtsi"
+#include "k3-j721e-mcu-wakeup.dtsi"
diff --git a/arch/arm/dts/kirkwood-km_common.dtsi b/arch/arm/dts/kirkwood-km_common.dtsi
index 75dc839..9d0fc51 100644
--- a/arch/arm/dts/kirkwood-km_common.dtsi
+++ b/arch/arm/dts/kirkwood-km_common.dtsi
@@ -22,6 +22,7 @@
serial@12000 {
status = "okay";
+ clock-frequency = <200000000>;
};
};
diff --git a/arch/arm/dts/kirkwood-km_kirkwood.dts b/arch/arm/dts/kirkwood-km_kirkwood.dts
index f035eff..b2c0209 100644
--- a/arch/arm/dts/kirkwood-km_kirkwood.dts
+++ b/arch/arm/dts/kirkwood-km_kirkwood.dts
@@ -13,6 +13,10 @@
device_type = "memory";
reg = <0x00000000 0x08000000>;
};
+
+ aliases {
+ spi0 = &spi0;
+ };
};
&mdio {
@@ -29,3 +33,21 @@
phy-handle = <ðphy0>;
};
};
+
+&spi0 {
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,m25p80", "jedec,spi-nor", "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <33000000>;
+ mode = <3>;
+
+ partition@uboot {
+ reg = <0x000000 0x0c0000>;
+ label = "uboot";
+ };
+ };
+};
diff --git a/arch/arm/dts/logicpd-som-lv-35xx-devkit-u-boot.dtsi b/arch/arm/dts/logicpd-som-lv-35xx-devkit-u-boot.dtsi
index b3da8b1..1abd9a3 100644
--- a/arch/arm/dts/logicpd-som-lv-35xx-devkit-u-boot.dtsi
+++ b/arch/arm/dts/logicpd-som-lv-35xx-devkit-u-boot.dtsi
@@ -10,6 +10,11 @@
chosen {
stdout-path = &uart1;
};
+
+ aliases {
+ /delete-property/ serial1;
+ /delete-property/ serial2;
+ };
};
&i2c1 {
@@ -20,15 +25,8 @@
clock-frequency = <400000>;
};
-&mmc1 {
- cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* gpio_110 */
-};
-
-&mmc2 {
- status = "disabled";
-};
-
-&mmc3 {
- status = "disabled";
-};
+/delete-node/ &uart2;
+/delete-node/ &uart3;
+/delete-node/ &mmc2;
+/delete-node/ &mmc3;
diff --git a/arch/arm/dts/logicpd-som-lv-35xx-devkit.dts b/arch/arm/dts/logicpd-som-lv-35xx-devkit.dts
index 32d0dc3..f7a841a 100644
--- a/arch/arm/dts/logicpd-som-lv-35xx-devkit.dts
+++ b/arch/arm/dts/logicpd-som-lv-35xx-devkit.dts
@@ -1,8 +1,4 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
+// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
diff --git a/arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi b/arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi
index 956199a..1abd9a3 100644
--- a/arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi
+++ b/arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi
@@ -10,6 +10,11 @@
chosen {
stdout-path = &uart1;
};
+
+ aliases {
+ /delete-property/ serial1;
+ /delete-property/ serial2;
+ };
};
&i2c1 {
@@ -20,11 +25,8 @@
clock-frequency = <400000>;
};
-&mmc2 {
- status = "disabled";
-};
-
-&mmc3 {
- status = "disabled";
-};
+/delete-node/ &uart2;
+/delete-node/ &uart3;
+/delete-node/ &mmc2;
+/delete-node/ &mmc3;
diff --git a/arch/arm/dts/logicpd-som-lv-37xx-devkit.dts b/arch/arm/dts/logicpd-som-lv-37xx-devkit.dts
index 2428373..a604d92 100644
--- a/arch/arm/dts/logicpd-som-lv-37xx-devkit.dts
+++ b/arch/arm/dts/logicpd-som-lv-37xx-devkit.dts
@@ -1,8 +1,4 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
+// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
diff --git a/arch/arm/dts/logicpd-som-lv-baseboard.dtsi b/arch/arm/dts/logicpd-som-lv-baseboard.dtsi
index 3524766..100396f 100644
--- a/arch/arm/dts/logicpd-som-lv-baseboard.dtsi
+++ b/arch/arm/dts/logicpd-som-lv-baseboard.dtsi
@@ -1,8 +1,4 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
+// SPDX-License-Identifier: GPL-2.0-only
/ {
gpio_keys {
@@ -152,8 +148,8 @@
interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
- wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; /* gpio_126 */
- cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* gpio_110 */
+ wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; /* gpio_126 */
+ cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* gpio_110 */
vmmc-supply = <&vmmc1>;
bus-width = <4>;
cap-power-off-card;
diff --git a/arch/arm/dts/logicpd-som-lv.dtsi b/arch/arm/dts/logicpd-som-lv.dtsi
index 98b682a..b56524c 100644
--- a/arch/arm/dts/logicpd-som-lv.dtsi
+++ b/arch/arm/dts/logicpd-som-lv.dtsi
@@ -1,8 +1,4 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
+// SPDX-License-Identifier: GPL-2.0-only
#include <dt-bindings/input/input.h>
@@ -232,6 +228,20 @@
>;
};
+ i2c2_pins: pinmux_i2c2_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */
+ OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */
+ >;
+ };
+
+ i2c3_pins: pinmux_i2c3_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */
+ OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */
+ >;
+ };
+
tsc2004_pins: pinmux_tsc2004_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE4) /* mcbsp4_dr.gpio_153 */
@@ -253,18 +263,6 @@
OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */
>;
};
- i2c2_pins: pinmux_i2c2_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */
- OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */
- >;
- };
- i2c3_pins: pinmux_i2c3_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */
- OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */
- >;
- };
};
&omap3_pmx_core2 {
diff --git a/arch/arm/dts/logicpd-torpedo-35xx-devkit-u-boot.dtsi b/arch/arm/dts/logicpd-torpedo-35xx-devkit-u-boot.dtsi
index 2c599f1..1635e42 100644
--- a/arch/arm/dts/logicpd-torpedo-35xx-devkit-u-boot.dtsi
+++ b/arch/arm/dts/logicpd-torpedo-35xx-devkit-u-boot.dtsi
@@ -6,6 +6,13 @@
#include "omap3-u-boot.dtsi"
+/ {
+ aliases {
+ /delete-property/ serial1;
+ /delete-property/ serial2;
+ };
+};
+
&i2c1 {
clock-frequency = <400000>;
};
@@ -14,11 +21,7 @@
clock-frequency = <400000>;
};
-&mmc2 {
- status = "disabled";
-};
-
-&mmc3 {
- status = "disabled";
-};
-
+/delete-node/ &uart2;
+/delete-node/ &uart3;
+/delete-node/ &mmc2;
+/delete-node/ &mmc3;
diff --git a/arch/arm/dts/logicpd-torpedo-35xx-devkit.dts b/arch/arm/dts/logicpd-torpedo-35xx-devkit.dts
index d7cb659..7675bc3 100644
--- a/arch/arm/dts/logicpd-torpedo-35xx-devkit.dts
+++ b/arch/arm/dts/logicpd-torpedo-35xx-devkit.dts
@@ -1,8 +1,4 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
+// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
diff --git a/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi b/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi
index 2c599f1..976330f 100644
--- a/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi
+++ b/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi
@@ -6,6 +6,13 @@
#include "omap3-u-boot.dtsi"
+/ {
+ aliases {
+ /delete-property/ serial1;
+ /delete-property/ serial2;
+ };
+};
+
&i2c1 {
clock-frequency = <400000>;
};
@@ -14,11 +21,8 @@
clock-frequency = <400000>;
};
-&mmc2 {
- status = "disabled";
-};
-
-&mmc3 {
- status = "disabled";
-};
+/delete-node/ &uart2;
+/delete-node/ &uart3;
+/delete-node/ &mmc2;
+/delete-node/ &mmc3;
diff --git a/arch/arm/dts/logicpd-torpedo-37xx-devkit.dts b/arch/arm/dts/logicpd-torpedo-37xx-devkit.dts
index c39cf2c..18c27e8 100644
--- a/arch/arm/dts/logicpd-torpedo-37xx-devkit.dts
+++ b/arch/arm/dts/logicpd-torpedo-37xx-devkit.dts
@@ -1,8 +1,4 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
+// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
diff --git a/arch/arm/dts/logicpd-torpedo-baseboard.dtsi b/arch/arm/dts/logicpd-torpedo-baseboard.dtsi
index 86c5644..642e809 100644
--- a/arch/arm/dts/logicpd-torpedo-baseboard.dtsi
+++ b/arch/arm/dts/logicpd-torpedo-baseboard.dtsi
@@ -1,8 +1,4 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
+// SPDX-License-Identifier: GPL-2.0-only
/ {
gpio_keys {
diff --git a/arch/arm/dts/logicpd-torpedo-som.dtsi b/arch/arm/dts/logicpd-torpedo-som.dtsi
index 7d2302e..3fdd0a7 100644
--- a/arch/arm/dts/logicpd-torpedo-som.dtsi
+++ b/arch/arm/dts/logicpd-torpedo-som.dtsi
@@ -1,8 +1,4 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
+// SPDX-License-Identifier: GPL-2.0-only
#include <dt-bindings/input/input.h>
diff --git a/arch/arm/dts/ls1021a-tsn.dts b/arch/arm/dts/ls1021a-tsn.dts
new file mode 100644
index 0000000..f633074
--- /dev/null
+++ b/arch/arm/dts/ls1021a-tsn.dts
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2016-2018 NXP Semiconductors
+ * Copyright 2019 Vladimir Oltean <olteanv@gmail.com>
+ */
+
+/dts-v1/;
+#include "ls1021a.dtsi"
+
+/ {
+ model = "NXP LS1021A-TSN Board";
+
+ aliases {
+ enet0-sgmii-phy = &sgmii_phy2;
+ enet1-sgmii-phy = &sgmii_phy1;
+ spi0 = &qspi;
+ spi1 = &dspi1;
+ };
+};
+
+&enet0 {
+ tbi-handle = <&tbi0>;
+ phy-handle = <&sgmii_phy2>;
+ phy-mode = "sgmii";
+ status = "okay";
+};
+
+&enet1 {
+ tbi-handle = <&tbi1>;
+ phy-handle = <&sgmii_phy1>;
+ phy-mode = "sgmii";
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&mdio0 {
+ /* AR8031 */
+ sgmii_phy1: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+
+ /* AR8031 */
+ sgmii_phy2: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+
+ /* SGMII PCS for enet0 */
+ tbi0: tbi-phy@1f {
+ reg = <0x1f>;
+ device_type = "tbi-phy";
+ };
+};
+
+&mdio1 {
+ /* SGMII PCS for enet1 */
+ tbi1: tbi-phy@1f {
+ reg = <0x1f>;
+ device_type = "tbi-phy";
+ };
+};
+
+&qspi {
+ bus-num = <0>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "spi-flash";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/ls1021a-twr.dtsi b/arch/arm/dts/ls1021a-twr.dtsi
index 5d3275c..27c96f9 100644
--- a/arch/arm/dts/ls1021a-twr.dtsi
+++ b/arch/arm/dts/ls1021a-twr.dtsi
@@ -51,6 +51,26 @@
};
};
+&enet0 {
+ tbi-handle = <&tbi0>;
+ phy-handle = <&sgmii_phy2>;
+ phy-connection-type = "sgmii";
+ status = "okay";
+};
+
+&enet1 {
+ tbi-handle = <&tbi1>;
+ phy-handle = <&sgmii_phy0>;
+ phy-connection-type = "sgmii";
+ status = "okay";
+};
+
+&enet2 {
+ phy-handle = <&rgmii_phy1>;
+ phy-connection-type = "rgmii-id";
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
};
@@ -84,12 +104,24 @@
sgmii_phy0: ethernet-phy@0 {
reg = <0x0>;
};
+
rgmii_phy1: ethernet-phy@1 {
reg = <0x1>;
};
+
sgmii_phy2: ethernet-phy@2 {
reg = <0x2>;
};
+
+ /* SGMII PCS for enet0 */
+ tbi0: tbi-phy@1f {
+ reg = <0x1f>;
+ device_type = "tbi-phy";
+ };
+};
+
+&mdio1 {
+ /* SGMII PCS for enet1 */
tbi1: tbi-phy@1f {
reg = <0x1f>;
device_type = "tbi-phy";
diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi
index 7fb24ab..e419d9c 100644
--- a/arch/arm/dts/ls1021a.dtsi
+++ b/arch/arm/dts/ls1021a.dtsi
@@ -350,12 +350,36 @@
<&platform_clk 1>;
};
+ enet0: ethernet@2d10000 {
+ compatible = "fsl,etsec2";
+ reg = <0x2d10000 0x1000>;
+ status = "disabled";
+ };
+
+ enet1: ethernet@2d50000 {
+ compatible = "fsl,etsec2";
+ reg = <0x2d50000 0x1000>;
+ status = "disabled";
+ };
+
+ enet2: ethernet@2d90000 {
+ compatible = "fsl,etsec2";
+ reg = <0x2d90000 0x1000>;
+ status = "disabled";
+ };
+
mdio0: mdio@2d24000 {
- compatible = "gianfar";
- device_type = "mdio";
+ compatible = "fsl,etsec2-mdio";
+ reg = <0x2d24000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
- reg = <0x2d24000 0x4000>;
+ };
+
+ mdio1: mdio@2d64000 {
+ compatible = "fsl,etsec2-mdio";
+ reg = <0x2d64000 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
};
usb@8600000 {
diff --git a/arch/arm/dts/meson-g12a-sei510.dts b/arch/arm/dts/meson-g12a-sei510.dts
new file mode 100644
index 0000000..c7a8736
--- /dev/null
+++ b/arch/arm/dts/meson-g12a-sei510.dts
@@ -0,0 +1,502 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre SAS. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "meson-g12a.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+ compatible = "seirobotics,sei510", "amlogic,g12a";
+ model = "SEI Robotics SEI510";
+
+ adc_keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 0>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+
+ button-onoff {
+ label = "On/Off";
+ linux,code = <KEY_POWER>;
+ press-threshold-microvolt = <1700000>;
+ };
+ };
+
+ aliases {
+ serial0 = &uart_AO;
+ ethernet0 = ðmac;
+ };
+
+ mono_dac: audio-codec-0 {
+ compatible = "maxim,max98357a";
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "U16";
+ sdmode-gpios = <&gpio GPIOX_8 GPIO_ACTIVE_HIGH>;
+ };
+
+ dmics: audio-codec-1 {
+ #sound-dai-cells = <0>;
+ compatible = "dmic-codec";
+ num-channels = <2>;
+ wakeup-delay-ms = <50>;
+ status = "okay";
+ sound-name-prefix = "MIC";
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ cvbs-connector {
+ compatible = "composite-video-connector";
+
+ port {
+ cvbs_connector_in: endpoint {
+ remote-endpoint = <&cvbs_vdac_out>;
+ };
+ };
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ ao_5v: regulator-ao_5v {
+ compatible = "regulator-fixed";
+ regulator-name = "AO_5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_in>;
+ regulator-always-on;
+ };
+
+ dc_in: regulator-dc_in {
+ compatible = "regulator-fixed";
+ regulator-name = "DC_IN";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ emmc_1v8: regulator-emmc_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "EMMC_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_in>;
+ regulator-always-on;
+ };
+
+ vddao_3v3_t: regultor-vddao_3v3_t {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3_T";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vddao_3v3>;
+ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
+ enable-active-high;
+ };
+
+ vddio_ao1v8: regulator-vddio_ao1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ reserved-memory {
+ /* TEE Reserved Memory */
+ bl32_reserved: bl32@5000000 {
+ reg = <0x0 0x05300000 0x0 0x2000000>;
+ no-map;
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sound {
+ compatible = "amlogic,axg-sound-card";
+ model = "G12A-SEI510";
+ audio-aux-devs = <&tdmout_a>, <&tdmout_b>,
+ <&tdmin_a>, <&tdmin_b>;
+ audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",
+ "TDMOUT_A IN 1", "FRDDR_B OUT 0",
+ "TDMOUT_A IN 2", "FRDDR_C OUT 0",
+ "TDM_A Playback", "TDMOUT_A OUT",
+ "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+ "TDMOUT_B IN 1", "FRDDR_B OUT 1",
+ "TDMOUT_B IN 2", "FRDDR_C OUT 1",
+ "TDM_B Playback", "TDMOUT_B OUT",
+ "TODDR_A IN 4", "PDM Capture",
+ "TODDR_B IN 4", "PDM Capture",
+ "TODDR_C IN 4", "PDM Capture",
+ "TDMIN_A IN 0", "TDM_A Capture",
+ "TDMIN_A IN 3", "TDM_A Loopback",
+ "TDMIN_B IN 0", "TDM_A Capture",
+ "TDMIN_B IN 3", "TDM_A Loopback",
+ "TDMIN_A IN 1", "TDM_B Capture",
+ "TDMIN_A IN 4", "TDM_B Loopback",
+ "TDMIN_B IN 1", "TDM_B Capture",
+ "TDMIN_B IN 4", "TDM_B Loopback",
+ "TODDR_A IN 0", "TDMIN_A OUT",
+ "TODDR_B IN 0", "TDMIN_A OUT",
+ "TODDR_C IN 0", "TDMIN_A OUT",
+ "TODDR_A IN 1", "TDMIN_B OUT",
+ "TODDR_B IN 1", "TDMIN_B OUT",
+ "TODDR_C IN 1", "TDMIN_B OUT";
+
+ assigned-clocks = <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+ status = "okay";
+
+ dai-link-0 {
+ sound-dai = <&frddr_a>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&frddr_b>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&frddr_c>;
+ };
+
+ dai-link-3 {
+ sound-dai = <&toddr_a>;
+ };
+
+ dai-link-4 {
+ sound-dai = <&toddr_b>;
+ };
+
+ dai-link-5 {
+ sound-dai = <&toddr_c>;
+ };
+
+ /* internal speaker interface */
+ dai-link-6 {
+ sound-dai = <&tdmif_a>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ mclk-fs = <256>;
+
+ codec-0 {
+ sound-dai = <&mono_dac>;
+ };
+
+ codec-1 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>;
+ };
+ };
+
+ /* 8ch hdmi interface */
+ dai-link-7 {
+ sound-dai = <&tdmif_b>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ dai-tdm-slot-tx-mask-1 = <1 1>;
+ dai-tdm-slot-tx-mask-2 = <1 1>;
+ dai-tdm-slot-tx-mask-3 = <1 1>;
+ mclk-fs = <256>;
+
+ codec@0 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+ };
+ };
+
+ /* internal digital mics */
+ dai-link-8 {
+ sound-dai = <&pdm>;
+
+ codec {
+ sound-dai = <&dmics>;
+ };
+ };
+
+ /* hdmi glue */
+ dai-link-9 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+ codec {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+};
+
+&arb {
+ status = "okay";
+};
+
+&cec_AO {
+ pinctrl-0 = <&cec_ao_a_h_pins>;
+ pinctrl-names = "default";
+ status = "disabled";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&cecb_AO {
+ pinctrl-0 = <&cec_ao_b_h_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&clkc_audio {
+ status = "okay";
+};
+
+&cvbs_vdac_port {
+ cvbs_vdac_out: endpoint {
+ remote-endpoint = <&cvbs_connector_in>;
+ };
+};
+
+ðmac {
+ status = "okay";
+ phy-handle = <&internal_ephy>;
+ phy-mode = "rmii";
+};
+
+&frddr_a {
+ status = "okay";
+};
+
+&frddr_b {
+ status = "okay";
+};
+
+&frddr_c {
+ status = "okay";
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
+ pinctrl-names = "default";
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+&i2c3 {
+ status = "okay";
+ pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
+ pinctrl-names = "default";
+};
+
+&pwm_ef {
+ status = "okay";
+ pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin0";
+};
+
+&pdm {
+ pinctrl-0 = <&pdm_din0_z_pins>, <&pdm_din1_z_pins>,
+ <&pdm_din2_z_pins>, <&pdm_din3_z_pins>,
+ <&pdm_dclk_z_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddio_ao1v8>;
+};
+
+/* SDIO */
+&sd_emmc_a {
+ status = "okay";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ sd-uhs-sdr50;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_ao1v8>;
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_c_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_c_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <50000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddao_3v3>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&emmc_1v8>;
+};
+
+&tdmif_a {
+ pinctrl-0 = <&tdm_a_dout0_pins>, <&tdm_a_fs_pins>, <&tdm_a_sclk_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ assigned-clocks = <&clkc_audio AUD_CLKID_TDM_SCLK_PAD0>,
+ <&clkc_audio AUD_CLKID_TDM_LRCLK_PAD0>;
+ assigned-clock-parents = <&clkc_audio AUD_CLKID_MST_A_SCLK>,
+ <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
+ assigned-clock-rates = <0>, <0>;
+};
+
+&tdmif_b {
+ status = "okay";
+};
+
+&tdmin_a {
+ status = "okay";
+};
+
+&tdmin_b {
+ status = "okay";
+};
+
+&tdmout_a {
+ status = "okay";
+};
+
+&tdmout_b {
+ status = "okay";
+};
+
+&toddr_a {
+ status = "okay";
+};
+
+&toddr_b {
+ status = "okay";
+};
+
+&toddr_c {
+ status = "okay";
+};
+
+&tohdmitx {
+ status = "okay";
+};
+
+&uart_A {
+ status = "okay";
+ pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+ max-speed = <2000000>;
+ clocks = <&wifi32k>;
+ clock-names = "lpo";
+ vbat-supply = <&vddao_3v3>;
+ vddio-supply = <&vddio_ao1v8>;
+ };
+};
+
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+&usb {
+ status = "okay";
+ dr_mode = "host";
+};
diff --git a/arch/arm/dts/meson-g12a-u-boot.dtsi b/arch/arm/dts/meson-g12a-u-boot.dtsi
deleted file mode 100644
index 8e0c81f..0000000
--- a/arch/arm/dts/meson-g12a-u-boot.dtsi
+++ /dev/null
@@ -1,216 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 BayLibre, SAS.
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-/ {
- soc {
- ethmac: ethernet@ff3f0000 {
- compatible = "amlogic,meson-axg-dwmac", "snps,dwmac-3.710",
- "snps,dwmac";
- reg = <0x0 0xff3f0000 0x0 0x10000
- 0x0 0xff634540 0x0 0x8>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
- clocks = <&clkc CLKID_ETH>,
- <&clkc CLKID_FCLK_DIV2>,
- <&clkc CLKID_MPLL2>;
- clock-names = "stmmaceth", "clkin0", "clkin1";
- status = "disabled";
-
- mdio0: mdio {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- };
- };
-
- sd_emmc_a: sd@ffe03000 {
- compatible = "amlogic,meson-axg-mmc";
- reg = <0x0 0xffe03000 0x0 0x800>;
- interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
- status = "disabled";
- clocks = <&clkc CLKID_SD_EMMC_A>,
- <&clkc CLKID_SD_EMMC_A_CLK0>,
- <&clkc CLKID_FCLK_DIV2>;
- clock-names = "core", "clkin0", "clkin1";
- resets = <&reset RESET_SD_EMMC_A>;
- };
-
- sd_emmc_b: sd@ffe05000 {
- compatible = "amlogic,meson-axg-mmc";
- reg = <0x0 0xffe05000 0x0 0x800>;
- interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>;
- status = "disabled";
- clocks = <&clkc CLKID_SD_EMMC_B>,
- <&clkc CLKID_SD_EMMC_B_CLK0>,
- <&clkc CLKID_FCLK_DIV2>;
- clock-names = "core", "clkin0", "clkin1";
- resets = <&reset RESET_SD_EMMC_B>;
- };
-
- sd_emmc_c: mmc@ffe07000 {
- compatible = "amlogic,meson-axg-mmc";
- reg = <0x0 0xffe07000 0x0 0x800>;
- interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>;
- status = "disabled";
- clocks = <&clkc CLKID_SD_EMMC_C>,
- <&clkc CLKID_SD_EMMC_C_CLK0>,
- <&clkc CLKID_FCLK_DIV2>;
- clock-names = "core", "clkin0", "clkin1";
- resets = <&reset RESET_SD_EMMC_C>;
- };
- };
-};
-
-&periphs_pinctrl {
- emmc_pins: emmc {
- mux {
- groups = "emmc_nand_d0",
- "emmc_nand_d1",
- "emmc_nand_d2",
- "emmc_nand_d3",
- "emmc_nand_d4",
- "emmc_nand_d5",
- "emmc_nand_d6",
- "emmc_nand_d7",
- "emmc_clk",
- "emmc_cmd";
- function = "emmc";
- bias-pull-up;
- };
- };
-
- emmc_ds_pins: emmc-ds {
- mux {
- groups = "emmc_nand_ds";
- function = "emmc";
- bias-pull-down;
- };
- };
-
- emmc_clk_gate_pins: emmc_clk_gate {
- mux {
- groups = "BOOT_8";
- function = "gpio_periphs";
- bias-pull-down;
- };
- };
-
- eth_leds_pins: eth-leds {
- mux {
- groups = "eth_link_led",
- "eth_act_led";
- function = "eth";
- bias-disable;
- };
- };
-
- eth_rmii_pins: eth-rmii {
- mux {
- groups = "eth_mdio",
- "eth_mdc",
- "eth_rgmii_rx_clk",
- "eth_rx_dv",
- "eth_rxd0",
- "eth_rxd1",
- "eth_txen",
- "eth_txd0",
- "eth_txd1";
- function = "eth";
- bias-disable;
- };
- };
-
- eth_rgmii_pins: eth-rgmii {
- mux {
- groups = "eth_rxd2_rgmii",
- "eth_rxd3_rgmii",
- "eth_rgmii_tx_clk",
- "eth_txd2_rgmii",
- "eth_txd3_rgmii";
- function = "eth";
- bias-disable;
- };
- };
-
- sdcard_c_pins: sdcard_c {
- mux {
- groups = "sdcard_d0_c",
- "sdcard_d1_c",
- "sdcard_d2_c",
- "sdcard_d3_c",
- "sdcard_cmd_c",
- "sdcard_clk_c";
- function = "sdcard";
- bias-pull-up;
- };
- };
-
- sdcard_clk_gate_c_pins: sdcard_clk_gate_c {
- mux {
- groups = "GPIOC_4";
- function = "gpio_periphs";
- bias-pull-down;
- };
- };
-
- sdcard_z_pins: sdcard_z {
- mux {
- groups = "sdcard_d0_z",
- "sdcard_d1_z",
- "sdcard_d2_z",
- "sdcard_d3_z",
- "sdcard_cmd_z",
- "sdcard_clk_z";
- function = "sdcard";
- bias-pull-up;
- };
- };
-
- sdcard_clk_gate_z_pins: sdcard_clk_gate_z {
- mux {
- groups = "GPIOZ_6";
- function = "gpio_periphs";
- bias-pull-down;
- };
- };
-};
-
-&periphs {
- eth_phy: mdio-multiplexer@4c000 {
- compatible = "amlogic,g12a-mdio-mux";
- reg = <0x0 0x4c000 0x0 0xa4>;
- clocks = <&clkc CLKID_ETH_PHY>,
- <&xtal>,
- <&clkc CLKID_MPLL_5OM>;
- clock-names = "pclk", "clkin0", "clkin1";
- mdio-parent-bus = <&mdio0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- ext_mdio: mdio@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- int_mdio: mdio@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- internal_ephy: ethernet_phy@8 {
- compatible = "ethernet-phy-id0180.3300",
- "ethernet-phy-ieee802.3-c22";
- reg = <8>;
- max-speed = <100>;
-
- /* FIXME: Add irq support */
- };
- };
- };
-};
-
-
diff --git a/arch/arm/dts/meson-g12a-u200-u-boot.dtsi b/arch/arm/dts/meson-g12a-u200-u-boot.dtsi
deleted file mode 100644
index 9486ab0..0000000
--- a/arch/arm/dts/meson-g12a-u200-u-boot.dtsi
+++ /dev/null
@@ -1,63 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 BayLibre, SAS.
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#include "meson-g12a-u-boot.dtsi"
-
- / {
- aliases {
- ethernet0 = ðmac;
- };
-
- emmc_pwrseq: emmc-pwrseq {
- compatible = "mmc-pwrseq-emmc";
- reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
- };
-};
-
-ðmac {
- status = "okay";
- pinctrl-0 = <ð_leds_pins>;
- pinctrl-names = "default";
- phy-handle = <&internal_ephy>;
- phy-mode = "rmii";
-};
-
-
-/* SD card */
-&sd_emmc_b {
- status = "okay";
- pinctrl-0 = <&sdcard_c_pins>;
- pinctrl-1 = <&sdcard_clk_gate_c_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <4>;
- cap-sd-highspeed;
- max-frequency = <50000000>;
- disable-wp;
-
- cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
- vmmc-supply = <&vddao_3v3>;
- vqmmc-supply = <&vddao_3v3>;
-};
-
-/* eMMC */
-&sd_emmc_c {
- status = "okay";
- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
- pinctrl-1 = <&emmc_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <8>;
- cap-mmc-highspeed;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- max-frequency = <200000000>;
- disable-wp;
-
- mmc-pwrseq = <&emmc_pwrseq>;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&flash_1v8>;
-};
diff --git a/arch/arm/dts/meson-g12a-u200.dts b/arch/arm/dts/meson-g12a-u200.dts
index 0e8045b..8551fbd 100644
--- a/arch/arm/dts/meson-g12a-u200.dts
+++ b/arch/arm/dts/meson-g12a-u200.dts
@@ -15,14 +15,12 @@
aliases {
serial0 = &uart_AO;
+ ethernet0 = ðmac;
};
+
chosen {
stdout-path = "serial0:115200n8";
};
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x40000000>;
- };
cvbs-connector {
compatible = "composite-video-connector";
@@ -34,13 +32,9 @@
};
};
- flash_1v8: regulator-flash_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "FLASH_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_3v3>;
- regulator-always-on;
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
};
hdmi-connector {
@@ -54,6 +48,20 @@
};
};
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ flash_1v8: regulator-flash_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "FLASH_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ regulator-always-on;
+ };
+
main_12v: regulator-main_12v {
compatible = "regulator-fixed";
regulator-name = "12V";
@@ -62,6 +70,17 @@
regulator-always-on;
};
+ usb_pwr_en: regulator-usb_pwr_en {
+ compatible = "regulator-fixed";
+ regulator-name = "USB_PWR_EN";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc_5v>;
+
+ gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
vcc_1v8: regulator-vcc_1v8 {
compatible = "regulator-fixed";
regulator-name = "VCC_1V8";
@@ -92,17 +111,6 @@
enable-active-high;
};
- usb_pwr_en: regulator-usb_pwr_en {
- compatible = "regulator-fixed";
- regulator-name = "USB_PWR_EN";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc_5v>;
-
- gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
vddao_1v8: regulator-vddao_1v8 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_1V8";
@@ -143,6 +151,12 @@
};
};
+ðmac {
+ status = "okay";
+ phy-handle = <&internal_ephy>;
+ phy-mode = "rmii";
+};
+
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
@@ -156,6 +170,70 @@
};
};
+&ir {
+ status = "okay";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
+};
+
+/* i2c Touch */
+&i2c0 {
+ status = "okay";
+ pinctrl-0 = <&i2c0_sda_z0_pins>, <&i2c0_sck_z1_pins>;
+ pinctrl-names = "default";
+};
+
+/* i2c CM */
+&i2c2 {
+ status = "okay";
+ pinctrl-0 = <&i2c2_sda_z_pins>, <&i2c2_sck_z_pins>;
+ pinctrl-names = "default";
+};
+
+/* i2c Audio */
+&i2c3 {
+ status = "okay";
+ pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
+ pinctrl-names = "default";
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_c_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_c_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <50000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddao_3v3>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&flash_1v8>;
+};
+
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
diff --git a/arch/arm/dts/meson-g12a.dtsi b/arch/arm/dts/meson-g12a.dtsi
index 9f72396..f8d43e3 100644
--- a/arch/arm/dts/meson-g12a.dtsi
+++ b/arch/arm/dts/meson-g12a.dtsi
@@ -5,10 +5,12 @@
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/axg-audio-clkc.h>
#include <dt-bindings/clock/g12a-clkc.h>
#include <dt-bindings/clock/g12a-aoclkc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
#include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
/ {
@@ -18,6 +20,39 @@
#address-cells = <2>;
#size-cells = <2>;
+ tdmif_a: audio-controller-0 {
+ compatible = "amlogic,axg-tdm-iface";
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "TDM_A";
+ clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
+ <&clkc_audio AUD_CLKID_MST_A_SCLK>,
+ <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
+ clock-names = "mclk", "sclk", "lrclk";
+ status = "disabled";
+ };
+
+ tdmif_b: audio-controller-1 {
+ compatible = "amlogic,axg-tdm-iface";
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "TDM_B";
+ clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
+ <&clkc_audio AUD_CLKID_MST_B_SCLK>,
+ <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
+ clock-names = "mclk", "sclk", "lrclk";
+ status = "disabled";
+ };
+
+ tdmif_c: audio-controller-2 {
+ compatible = "amlogic,axg-tdm-iface";
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "TDM_C";
+ clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
+ <&clkc_audio AUD_CLKID_MST_C_SCLK>,
+ <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
+ clock-names = "mclk", "sclk", "lrclk";
+ status = "disabled";
+ };
+
cpus {
#address-cells = <0x2>;
#size-cells = <0x0>;
@@ -102,6 +137,27 @@
#size-cells = <2>;
ranges;
+ ethmac: ethernet@ff3f0000 {
+ compatible = "amlogic,meson-axg-dwmac",
+ "snps,dwmac-3.70a",
+ "snps,dwmac";
+ reg = <0x0 0xff3f0000 0x0 0x10000
+ 0x0 0xff634540 0x0 0x8>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clocks = <&clkc CLKID_ETH>,
+ <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_MPLL2>;
+ clock-names = "stmmaceth", "clkin0", "clkin1";
+ status = "disabled";
+
+ mdio0: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ };
+ };
+
apb: bus@ff600000 {
compatible = "simple-bus";
reg = <0x0 0xff600000 0x0 0x200000>;
@@ -123,6 +179,7 @@
clock-names = "isfr", "iahb", "venci";
#address-cells = <1>;
#size-cells = <0>;
+ #sound-dai-cells = <0>;
status = "disabled";
/* VPU VENC Input */
@@ -140,6 +197,19 @@
};
};
+ apb_efuse: bus@30000 {
+ compatible = "simple-bus";
+ reg = <0x0 0x30000 0x0 0x2000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>;
+
+ hwrng: rng@218 {
+ compatible = "amlogic,meson-rng";
+ reg = <0x0 0x218 0x0 0x4>;
+ };
+ };
+
periphs: bus@34400 {
compatible = "simple-bus";
reg = <0x0 0x34400 0x0 0x400>;
@@ -185,12 +255,55 @@
};
};
+ emmc_pins: emmc {
+ mux-0 {
+ groups = "emmc_nand_d0",
+ "emmc_nand_d1",
+ "emmc_nand_d2",
+ "emmc_nand_d3",
+ "emmc_nand_d4",
+ "emmc_nand_d5",
+ "emmc_nand_d6",
+ "emmc_nand_d7",
+ "emmc_cmd";
+ function = "emmc";
+ bias-pull-up;
+ drive-strength-microamp = <4000>;
+ };
+
+ mux-1 {
+ groups = "emmc_clk";
+ function = "emmc";
+ bias-disable;
+ drive-strength-microamp = <4000>;
+ };
+ };
+
+ emmc_ds_pins: emmc-ds {
+ mux {
+ groups = "emmc_nand_ds";
+ function = "emmc";
+ bias-pull-down;
+ drive-strength-microamp = <4000>;
+ };
+ };
+
+ emmc_clk_gate_pins: emmc_clk_gate {
+ mux {
+ groups = "BOOT_8";
+ function = "gpio_periphs";
+ bias-pull-down;
+ drive-strength-microamp = <4000>;
+ };
+ };
+
hdmitx_ddc_pins: hdmitx_ddc {
mux {
groups = "hdmitx_sda",
"hdmitx_sck";
function = "hdmitx";
bias-disable;
+ drive-strength-microamp = <4000>;
};
};
@@ -202,6 +315,1040 @@
};
};
+
+ i2c0_sda_c_pins: i2c0-sda-c {
+ mux {
+ groups = "i2c0_sda_c";
+ function = "i2c0";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+
+ };
+ };
+
+ i2c0_sck_c_pins: i2c0-sck-c {
+ mux {
+ groups = "i2c0_sck_c";
+ function = "i2c0";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c0_sda_z0_pins: i2c0-sda-z0 {
+ mux {
+ groups = "i2c0_sda_z0";
+ function = "i2c0";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c0_sck_z1_pins: i2c0-sck-z1 {
+ mux {
+ groups = "i2c0_sck_z1";
+ function = "i2c0";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c0_sda_z7_pins: i2c0-sda-z7 {
+ mux {
+ groups = "i2c0_sda_z7";
+ function = "i2c0";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c0_sda_z8_pins: i2c0-sda-z8 {
+ mux {
+ groups = "i2c0_sda_z8";
+ function = "i2c0";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c1_sda_x_pins: i2c1-sda-x {
+ mux {
+ groups = "i2c1_sda_x";
+ function = "i2c1";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c1_sck_x_pins: i2c1-sck-x {
+ mux {
+ groups = "i2c1_sck_x";
+ function = "i2c1";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c1_sda_h2_pins: i2c1-sda-h2 {
+ mux {
+ groups = "i2c1_sda_h2";
+ function = "i2c1";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c1_sck_h3_pins: i2c1-sck-h3 {
+ mux {
+ groups = "i2c1_sck_h3";
+ function = "i2c1";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c1_sda_h6_pins: i2c1-sda-h6 {
+ mux {
+ groups = "i2c1_sda_h6";
+ function = "i2c1";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c1_sck_h7_pins: i2c1-sck-h7 {
+ mux {
+ groups = "i2c1_sck_h7";
+ function = "i2c1";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c2_sda_x_pins: i2c2-sda-x {
+ mux {
+ groups = "i2c2_sda_x";
+ function = "i2c2";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c2_sck_x_pins: i2c2-sck-x {
+ mux {
+ groups = "i2c2_sck_x";
+ function = "i2c2";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c2_sda_z_pins: i2c2-sda-z {
+ mux {
+ groups = "i2c2_sda_z";
+ function = "i2c2";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c2_sck_z_pins: i2c2-sck-z {
+ mux {
+ groups = "i2c2_sck_z";
+ function = "i2c2";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c3_sda_h_pins: i2c3-sda-h {
+ mux {
+ groups = "i2c3_sda_h";
+ function = "i2c3";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c3_sck_h_pins: i2c3-sck-h {
+ mux {
+ groups = "i2c3_sck_h";
+ function = "i2c3";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c3_sda_a_pins: i2c3-sda-a {
+ mux {
+ groups = "i2c3_sda_a";
+ function = "i2c3";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c3_sck_a_pins: i2c3-sck-a {
+ mux {
+ groups = "i2c3_sck_a";
+ function = "i2c3";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ mclk0_a_pins: mclk0-a {
+ mux {
+ groups = "mclk0_a";
+ function = "mclk0";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ mclk1_a_pins: mclk1-a {
+ mux {
+ groups = "mclk1_a";
+ function = "mclk1";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ mclk1_x_pins: mclk1-x {
+ mux {
+ groups = "mclk1_x";
+ function = "mclk1";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ mclk1_z_pins: mclk1-z {
+ mux {
+ groups = "mclk1_z";
+ function = "mclk1";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ pdm_din0_a_pins: pdm-din0-a {
+ mux {
+ groups = "pdm_din0_a";
+ function = "pdm";
+ bias-disable;
+ };
+ };
+
+ pdm_din0_c_pins: pdm-din0-c {
+ mux {
+ groups = "pdm_din0_c";
+ function = "pdm";
+ bias-disable;
+ };
+ };
+
+ pdm_din0_x_pins: pdm-din0-x {
+ mux {
+ groups = "pdm_din0_x";
+ function = "pdm";
+ bias-disable;
+ };
+ };
+
+ pdm_din0_z_pins: pdm-din0-z {
+ mux {
+ groups = "pdm_din0_z";
+ function = "pdm";
+ bias-disable;
+ };
+ };
+
+ pdm_din1_a_pins: pdm-din1-a {
+ mux {
+ groups = "pdm_din1_a";
+ function = "pdm";
+ bias-disable;
+ };
+ };
+
+ pdm_din1_c_pins: pdm-din1-c {
+ mux {
+ groups = "pdm_din1_c";
+ function = "pdm";
+ bias-disable;
+ };
+ };
+
+ pdm_din1_x_pins: pdm-din1-x {
+ mux {
+ groups = "pdm_din1_x";
+ function = "pdm";
+ bias-disable;
+ };
+ };
+
+ pdm_din1_z_pins: pdm-din1-z {
+ mux {
+ groups = "pdm_din1_z";
+ function = "pdm";
+ bias-disable;
+ };
+ };
+
+ pdm_din2_a_pins: pdm-din2-a {
+ mux {
+ groups = "pdm_din2_a";
+ function = "pdm";
+ bias-disable;
+ };
+ };
+
+ pdm_din2_c_pins: pdm-din2-c {
+ mux {
+ groups = "pdm_din2_c";
+ function = "pdm";
+ bias-disable;
+ };
+ };
+
+ pdm_din2_x_pins: pdm-din2-x {
+ mux {
+ groups = "pdm_din2_x";
+ function = "pdm";
+ bias-disable;
+ };
+ };
+
+ pdm_din2_z_pins: pdm-din2-z {
+ mux {
+ groups = "pdm_din2_z";
+ function = "pdm";
+ bias-disable;
+ };
+ };
+
+ pdm_din3_a_pins: pdm-din3-a {
+ mux {
+ groups = "pdm_din3_a";
+ function = "pdm";
+ bias-disable;
+ };
+ };
+
+ pdm_din3_c_pins: pdm-din3-c {
+ mux {
+ groups = "pdm_din3_c";
+ function = "pdm";
+ bias-disable;
+ };
+ };
+
+ pdm_din3_x_pins: pdm-din3-x {
+ mux {
+ groups = "pdm_din3_x";
+ function = "pdm";
+ bias-disable;
+ };
+ };
+
+ pdm_din3_z_pins: pdm-din3-z {
+ mux {
+ groups = "pdm_din3_z";
+ function = "pdm";
+ bias-disable;
+ };
+ };
+
+ pdm_dclk_a_pins: pdm-dclk-a {
+ mux {
+ groups = "pdm_dclk_a";
+ function = "pdm";
+ bias-disable;
+ drive-strength-microamp = <500>;
+ };
+ };
+
+ pdm_dclk_c_pins: pdm-dclk-c {
+ mux {
+ groups = "pdm_dclk_c";
+ function = "pdm";
+ bias-disable;
+ drive-strength-microamp = <500>;
+ };
+ };
+
+ pdm_dclk_x_pins: pdm-dclk-x {
+ mux {
+ groups = "pdm_dclk_x";
+ function = "pdm";
+ bias-disable;
+ drive-strength-microamp = <500>;
+ };
+ };
+
+ pdm_dclk_z_pins: pdm-dclk-z {
+ mux {
+ groups = "pdm_dclk_z";
+ function = "pdm";
+ bias-disable;
+ drive-strength-microamp = <500>;
+ };
+ };
+
+ pwm_a_pins: pwm-a {
+ mux {
+ groups = "pwm_a";
+ function = "pwm_a";
+ bias-disable;
+ };
+ };
+
+ pwm_b_x7_pins: pwm-b-x7 {
+ mux {
+ groups = "pwm_b_x7";
+ function = "pwm_b";
+ bias-disable;
+ };
+ };
+
+ pwm_b_x19_pins: pwm-b-x19 {
+ mux {
+ groups = "pwm_b_x19";
+ function = "pwm_b";
+ bias-disable;
+ };
+ };
+
+ pwm_c_c_pins: pwm-c-c {
+ mux {
+ groups = "pwm_c_c";
+ function = "pwm_c";
+ bias-disable;
+ };
+ };
+
+ pwm_c_x5_pins: pwm-c-x5 {
+ mux {
+ groups = "pwm_c_x5";
+ function = "pwm_c";
+ bias-disable;
+ };
+ };
+
+ pwm_c_x8_pins: pwm-c-x8 {
+ mux {
+ groups = "pwm_c_x8";
+ function = "pwm_c";
+ bias-disable;
+ };
+ };
+
+ pwm_d_x3_pins: pwm-d-x3 {
+ mux {
+ groups = "pwm_d_x3";
+ function = "pwm_d";
+ bias-disable;
+ };
+ };
+
+ pwm_d_x6_pins: pwm-d-x6 {
+ mux {
+ groups = "pwm_d_x6";
+ function = "pwm_d";
+ bias-disable;
+ };
+ };
+
+ pwm_e_pins: pwm-e {
+ mux {
+ groups = "pwm_e";
+ function = "pwm_e";
+ bias-disable;
+ };
+ };
+
+ pwm_f_x_pins: pwm-f-x {
+ mux {
+ groups = "pwm_f_x";
+ function = "pwm_f";
+ bias-disable;
+ };
+ };
+
+ pwm_f_h_pins: pwm-f-h {
+ mux {
+ groups = "pwm_f_h";
+ function = "pwm_f";
+ bias-disable;
+ };
+ };
+
+ sdcard_c_pins: sdcard_c {
+ mux-0 {
+ groups = "sdcard_d0_c",
+ "sdcard_d1_c",
+ "sdcard_d2_c",
+ "sdcard_d3_c",
+ "sdcard_cmd_c";
+ function = "sdcard";
+ bias-pull-up;
+ drive-strength-microamp = <4000>;
+ };
+
+ mux-1 {
+ groups = "sdcard_clk_c";
+ function = "sdcard";
+ bias-disable;
+ drive-strength-microamp = <4000>;
+ };
+ };
+
+ sdcard_clk_gate_c_pins: sdcard_clk_gate_c {
+ mux {
+ groups = "GPIOC_4";
+ function = "gpio_periphs";
+ bias-pull-down;
+ drive-strength-microamp = <4000>;
+ };
+ };
+
+ sdcard_z_pins: sdcard_z {
+ mux-0 {
+ groups = "sdcard_d0_z",
+ "sdcard_d1_z",
+ "sdcard_d2_z",
+ "sdcard_d3_z",
+ "sdcard_cmd_z";
+ function = "sdcard";
+ bias-pull-up;
+ drive-strength-microamp = <4000>;
+ };
+
+ mux-1 {
+ groups = "sdcard_clk_z";
+ function = "sdcard";
+ bias-disable;
+ drive-strength-microamp = <4000>;
+ };
+ };
+
+ sdcard_clk_gate_z_pins: sdcard_clk_gate_z {
+ mux {
+ groups = "GPIOZ_6";
+ function = "gpio_periphs";
+ bias-pull-down;
+ drive-strength-microamp = <4000>;
+ };
+ };
+
+ sdio_pins: sdio {
+ mux {
+ groups = "sdio_d0",
+ "sdio_d1",
+ "sdio_d2",
+ "sdio_d3",
+ "sdio_clk",
+ "sdio_cmd";
+ function = "sdio";
+ bias-disable;
+ drive-strength-microamp = <4000>;
+ };
+ };
+
+ sdio_clk_gate_pins: sdio_clk_gate {
+ mux {
+ groups = "GPIOX_4";
+ function = "gpio_periphs";
+ bias-pull-down;
+ drive-strength-microamp = <4000>;
+ };
+ };
+
+ spdif_in_a10_pins: spdif-in-a10 {
+ mux {
+ groups = "spdif_in_a10";
+ function = "spdif_in";
+ bias-disable;
+ };
+ };
+
+ spdif_in_a12_pins: spdif-in-a12 {
+ mux {
+ groups = "spdif_in_a12";
+ function = "spdif_in";
+ bias-disable;
+ };
+ };
+
+ spdif_in_h_pins: spdif-in-h {
+ mux {
+ groups = "spdif_in_h";
+ function = "spdif_in";
+ bias-disable;
+ };
+ };
+
+ spdif_out_h_pins: spdif-out-h {
+ mux {
+ groups = "spdif_out_h";
+ function = "spdif_out";
+ drive-strength-microamp = <500>;
+ bias-disable;
+ };
+ };
+
+ spdif_out_a11_pins: spdif-out-a11 {
+ mux {
+ groups = "spdif_out_a11";
+ function = "spdif_out";
+ drive-strength-microamp = <500>;
+ bias-disable;
+ };
+ };
+
+ spdif_out_a13_pins: spdif-out-a13 {
+ mux {
+ groups = "spdif_out_a13";
+ function = "spdif_out";
+ drive-strength-microamp = <500>;
+ bias-disable;
+ };
+ };
+
+ tdm_a_din0_pins: tdm-a-din0 {
+ mux {
+ groups = "tdm_a_din0";
+ function = "tdm_a";
+ bias-disable;
+ };
+ };
+
+
+ tdm_a_din1_pins: tdm-a-din1 {
+ mux {
+ groups = "tdm_a_din1";
+ function = "tdm_a";
+ bias-disable;
+ };
+ };
+
+ tdm_a_dout0_pins: tdm-a-dout0 {
+ mux {
+ groups = "tdm_a_dout0";
+ function = "tdm_a";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_a_dout1_pins: tdm-a-dout1 {
+ mux {
+ groups = "tdm_a_dout1";
+ function = "tdm_a";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_a_fs_pins: tdm-a-fs {
+ mux {
+ groups = "tdm_a_fs";
+ function = "tdm_a";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_a_sclk_pins: tdm-a-sclk {
+ mux {
+ groups = "tdm_a_sclk";
+ function = "tdm_a";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_a_slv_fs_pins: tdm-a-slv-fs {
+ mux {
+ groups = "tdm_a_slv_fs";
+ function = "tdm_a";
+ bias-disable;
+ };
+ };
+
+
+ tdm_a_slv_sclk_pins: tdm-a-slv-sclk {
+ mux {
+ groups = "tdm_a_slv_sclk";
+ function = "tdm_a";
+ bias-disable;
+ };
+ };
+
+ tdm_b_din0_pins: tdm-b-din0 {
+ mux {
+ groups = "tdm_b_din0";
+ function = "tdm_b";
+ bias-disable;
+ };
+ };
+
+ tdm_b_din1_pins: tdm-b-din1 {
+ mux {
+ groups = "tdm_b_din1";
+ function = "tdm_b";
+ bias-disable;
+ };
+ };
+
+ tdm_b_din2_pins: tdm-b-din2 {
+ mux {
+ groups = "tdm_b_din2";
+ function = "tdm_b";
+ bias-disable;
+ };
+ };
+
+ tdm_b_din3_a_pins: tdm-b-din3-a {
+ mux {
+ groups = "tdm_b_din3_a";
+ function = "tdm_b";
+ bias-disable;
+ };
+ };
+
+ tdm_b_din3_h_pins: tdm-b-din3-h {
+ mux {
+ groups = "tdm_b_din3_h";
+ function = "tdm_b";
+ bias-disable;
+ };
+ };
+
+ tdm_b_dout0_pins: tdm-b-dout0 {
+ mux {
+ groups = "tdm_b_dout0";
+ function = "tdm_b";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_b_dout1_pins: tdm-b-dout1 {
+ mux {
+ groups = "tdm_b_dout1";
+ function = "tdm_b";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_b_dout2_pins: tdm-b-dout2 {
+ mux {
+ groups = "tdm_b_dout2";
+ function = "tdm_b";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_b_dout3_a_pins: tdm-b-dout3-a {
+ mux {
+ groups = "tdm_b_dout3_a";
+ function = "tdm_b";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_b_dout3_h_pins: tdm-b-dout3-h {
+ mux {
+ groups = "tdm_b_dout3_h";
+ function = "tdm_b";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_b_fs_pins: tdm-b-fs {
+ mux {
+ groups = "tdm_b_fs";
+ function = "tdm_b";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_b_sclk_pins: tdm-b-sclk {
+ mux {
+ groups = "tdm_b_sclk";
+ function = "tdm_b";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_b_slv_fs_pins: tdm-b-slv-fs {
+ mux {
+ groups = "tdm_b_slv_fs";
+ function = "tdm_b";
+ bias-disable;
+ };
+ };
+
+ tdm_b_slv_sclk_pins: tdm-b-slv-sclk {
+ mux {
+ groups = "tdm_b_slv_sclk";
+ function = "tdm_b";
+ bias-disable;
+ };
+ };
+
+ tdm_c_din0_a_pins: tdm-c-din0-a {
+ mux {
+ groups = "tdm_c_din0_a";
+ function = "tdm_c";
+ bias-disable;
+ };
+ };
+
+ tdm_c_din0_z_pins: tdm-c-din0-z {
+ mux {
+ groups = "tdm_c_din0_z";
+ function = "tdm_c";
+ bias-disable;
+ };
+ };
+
+ tdm_c_din1_a_pins: tdm-c-din1-a {
+ mux {
+ groups = "tdm_c_din1_a";
+ function = "tdm_c";
+ bias-disable;
+ };
+ };
+
+ tdm_c_din1_z_pins: tdm-c-din1-z {
+ mux {
+ groups = "tdm_c_din1_z";
+ function = "tdm_c";
+ bias-disable;
+ };
+ };
+
+ tdm_c_din2_a_pins: tdm-c-din2-a {
+ mux {
+ groups = "tdm_c_din2_a";
+ function = "tdm_c";
+ bias-disable;
+ };
+ };
+
+ eth_leds_pins: eth-leds {
+ mux {
+ groups = "eth_link_led",
+ "eth_act_led";
+ function = "eth";
+ bias-disable;
+ };
+ };
+
+ eth_pins: eth {
+ mux {
+ groups = "eth_mdio",
+ "eth_mdc",
+ "eth_rgmii_rx_clk",
+ "eth_rx_dv",
+ "eth_rxd0",
+ "eth_rxd1",
+ "eth_txen",
+ "eth_txd0",
+ "eth_txd1";
+ function = "eth";
+ drive-strength-microamp = <4000>;
+ bias-disable;
+ };
+ };
+
+ eth_rgmii_pins: eth-rgmii {
+ mux {
+ groups = "eth_rxd2_rgmii",
+ "eth_rxd3_rgmii",
+ "eth_rgmii_tx_clk",
+ "eth_txd2_rgmii",
+ "eth_txd3_rgmii";
+ function = "eth";
+ drive-strength-microamp = <4000>;
+ bias-disable;
+ };
+ };
+
+ tdm_c_din2_z_pins: tdm-c-din2-z {
+ mux {
+ groups = "tdm_c_din2_z";
+ function = "tdm_c";
+ bias-disable;
+ };
+ };
+
+ tdm_c_din3_a_pins: tdm-c-din3-a {
+ mux {
+ groups = "tdm_c_din3_a";
+ function = "tdm_c";
+ bias-disable;
+ };
+ };
+
+ tdm_c_din3_z_pins: tdm-c-din3-z {
+ mux {
+ groups = "tdm_c_din3_z";
+ function = "tdm_c";
+ bias-disable;
+ };
+ };
+
+ tdm_c_dout0_a_pins: tdm-c-dout0-a {
+ mux {
+ groups = "tdm_c_dout0_a";
+ function = "tdm_c";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_c_dout0_z_pins: tdm-c-dout0-z {
+ mux {
+ groups = "tdm_c_dout0_z";
+ function = "tdm_c";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_c_dout1_a_pins: tdm-c-dout1-a {
+ mux {
+ groups = "tdm_c_dout1_a";
+ function = "tdm_c";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_c_dout1_z_pins: tdm-c-dout1-z {
+ mux {
+ groups = "tdm_c_dout1_z";
+ function = "tdm_c";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_c_dout2_a_pins: tdm-c-dout2-a {
+ mux {
+ groups = "tdm_c_dout2_a";
+ function = "tdm_c";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_c_dout2_z_pins: tdm-c-dout2-z {
+ mux {
+ groups = "tdm_c_dout2_z";
+ function = "tdm_c";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_c_dout3_a_pins: tdm-c-dout3-a {
+ mux {
+ groups = "tdm_c_dout3_a";
+ function = "tdm_c";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_c_dout3_z_pins: tdm-c-dout3-z {
+ mux {
+ groups = "tdm_c_dout3_z";
+ function = "tdm_c";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_c_fs_a_pins: tdm-c-fs-a {
+ mux {
+ groups = "tdm_c_fs_a";
+ function = "tdm_c";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_c_fs_z_pins: tdm-c-fs-z {
+ mux {
+ groups = "tdm_c_fs_z";
+ function = "tdm_c";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_c_sclk_a_pins: tdm-c-sclk-a {
+ mux {
+ groups = "tdm_c_sclk_a";
+ function = "tdm_c";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_c_sclk_z_pins: tdm-c-sclk-z {
+ mux {
+ groups = "tdm_c_sclk_z";
+ function = "tdm_c";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a {
+ mux {
+ groups = "tdm_c_slv_fs_a";
+ function = "tdm_c";
+ bias-disable;
+ };
+ };
+
+ tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z {
+ mux {
+ groups = "tdm_c_slv_fs_z";
+ function = "tdm_c";
+ bias-disable;
+ };
+ };
+
+ tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a {
+ mux {
+ groups = "tdm_c_slv_sclk_a";
+ function = "tdm_c";
+ bias-disable;
+ };
+ };
+
+ tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z {
+ mux {
+ groups = "tdm_c_slv_sclk_z";
+ function = "tdm_c";
+ bias-disable;
+ };
+ };
+
uart_a_pins: uart-a {
mux {
groups = "uart_a_tx",
@@ -303,6 +1450,282 @@
};
};
+ pdm: audio-controller@40000 {
+ compatible = "amlogic,g12a-pdm",
+ "amlogic,axg-pdm";
+ reg = <0x0 0x40000 0x0 0x34>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "PDM";
+ clocks = <&clkc_audio AUD_CLKID_PDM>,
+ <&clkc_audio AUD_CLKID_PDM_DCLK>,
+ <&clkc_audio AUD_CLKID_PDM_SYSCLK>;
+ clock-names = "pclk", "dclk", "sysclk";
+ status = "disabled";
+ };
+
+ audio: bus@42000 {
+ compatible = "simple-bus";
+ reg = <0x0 0x42000 0x0 0x2000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0x42000 0x0 0x2000>;
+
+ clkc_audio: clock-controller@0 {
+ status = "disabled";
+ compatible = "amlogic,g12a-audio-clkc";
+ reg = <0x0 0x0 0x0 0xb4>;
+ #clock-cells = <1>;
+
+ clocks = <&clkc CLKID_AUDIO>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>,
+ <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL3>,
+ <&clkc CLKID_HIFI_PLL>,
+ <&clkc CLKID_FCLK_DIV3>,
+ <&clkc CLKID_FCLK_DIV4>,
+ <&clkc CLKID_GP0_PLL>;
+ clock-names = "pclk",
+ "mst_in0",
+ "mst_in1",
+ "mst_in2",
+ "mst_in3",
+ "mst_in4",
+ "mst_in5",
+ "mst_in6",
+ "mst_in7";
+
+ resets = <&reset RESET_AUDIO>;
+ };
+
+ toddr_a: audio-controller@100 {
+ compatible = "amlogic,g12a-toddr",
+ "amlogic,axg-toddr";
+ reg = <0x0 0x100 0x0 0x1c>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "TODDR_A";
+ interrupts = <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
+ resets = <&arb AXG_ARB_TODDR_A>;
+ status = "disabled";
+ };
+
+ toddr_b: audio-controller@140 {
+ compatible = "amlogic,g12a-toddr",
+ "amlogic,axg-toddr";
+ reg = <0x0 0x140 0x0 0x1c>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "TODDR_B";
+ interrupts = <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
+ resets = <&arb AXG_ARB_TODDR_B>;
+ status = "disabled";
+ };
+
+ toddr_c: audio-controller@180 {
+ compatible = "amlogic,g12a-toddr",
+ "amlogic,axg-toddr";
+ reg = <0x0 0x180 0x0 0x1c>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "TODDR_C";
+ interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
+ resets = <&arb AXG_ARB_TODDR_C>;
+ status = "disabled";
+ };
+
+ frddr_a: audio-controller@1c0 {
+ compatible = "amlogic,g12a-frddr",
+ "amlogic,axg-frddr";
+ reg = <0x0 0x1c0 0x0 0x1c>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "FRDDR_A";
+ interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
+ resets = <&arb AXG_ARB_FRDDR_A>;
+ status = "disabled";
+ };
+
+ frddr_b: audio-controller@200 {
+ compatible = "amlogic,g12a-frddr",
+ "amlogic,axg-frddr";
+ reg = <0x0 0x200 0x0 0x1c>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "FRDDR_B";
+ interrupts = <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
+ resets = <&arb AXG_ARB_FRDDR_B>;
+ status = "disabled";
+ };
+
+ frddr_c: audio-controller@240 {
+ compatible = "amlogic,g12a-frddr",
+ "amlogic,axg-frddr";
+ reg = <0x0 0x240 0x0 0x1c>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "FRDDR_C";
+ interrupts = <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
+ resets = <&arb AXG_ARB_FRDDR_C>;
+ status = "disabled";
+ };
+
+ arb: reset-controller@280 {
+ status = "disabled";
+ compatible = "amlogic,meson-axg-audio-arb";
+ reg = <0x0 0x280 0x0 0x4>;
+ #reset-cells = <1>;
+ clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
+ };
+
+ tdmin_a: audio-controller@300 {
+ compatible = "amlogic,g12a-tdmin",
+ "amlogic,axg-tdmin";
+ reg = <0x0 0x300 0x0 0x40>;
+ sound-name-prefix = "TDMIN_A";
+ clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
+ <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
+ <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
+ <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
+ <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
+ clock-names = "pclk", "sclk", "sclk_sel",
+ "lrclk", "lrclk_sel";
+ status = "disabled";
+ };
+
+ tdmin_b: audio-controller@340 {
+ compatible = "amlogic,g12a-tdmin",
+ "amlogic,axg-tdmin";
+ reg = <0x0 0x340 0x0 0x40>;
+ sound-name-prefix = "TDMIN_B";
+ clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
+ <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
+ <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
+ <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
+ <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
+ clock-names = "pclk", "sclk", "sclk_sel",
+ "lrclk", "lrclk_sel";
+ status = "disabled";
+ };
+
+ tdmin_c: audio-controller@380 {
+ compatible = "amlogic,g12a-tdmin",
+ "amlogic,axg-tdmin";
+ reg = <0x0 0x380 0x0 0x40>;
+ sound-name-prefix = "TDMIN_C";
+ clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
+ <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
+ <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
+ <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
+ <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
+ clock-names = "pclk", "sclk", "sclk_sel",
+ "lrclk", "lrclk_sel";
+ status = "disabled";
+ };
+
+ tdmin_lb: audio-controller@3c0 {
+ compatible = "amlogic,g12a-tdmin",
+ "amlogic,axg-tdmin";
+ reg = <0x0 0x3c0 0x0 0x40>;
+ sound-name-prefix = "TDMIN_LB";
+ clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
+ <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
+ <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
+ <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
+ <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
+ clock-names = "pclk", "sclk", "sclk_sel",
+ "lrclk", "lrclk_sel";
+ status = "disabled";
+ };
+
+ spdifin: audio-controller@400 {
+ compatible = "amlogic,g12a-spdifin",
+ "amlogic,axg-spdifin";
+ reg = <0x0 0x400 0x0 0x30>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SPDIFIN";
+ interrupts = <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkc_audio AUD_CLKID_SPDIFIN>,
+ <&clkc_audio AUD_CLKID_SPDIFIN_CLK>;
+ clock-names = "pclk", "refclk";
+ status = "disabled";
+ };
+
+ spdifout: audio-controller@480 {
+ compatible = "amlogic,g12a-spdifout",
+ "amlogic,axg-spdifout";
+ reg = <0x0 0x480 0x0 0x50>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SPDIFOUT";
+ clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
+ <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
+ clock-names = "pclk", "mclk";
+ status = "disabled";
+ };
+
+ tdmout_a: audio-controller@500 {
+ compatible = "amlogic,g12a-tdmout";
+ reg = <0x0 0x500 0x0 0x40>;
+ sound-name-prefix = "TDMOUT_A";
+ clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
+ <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
+ <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
+ <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
+ <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
+ clock-names = "pclk", "sclk", "sclk_sel",
+ "lrclk", "lrclk_sel";
+ status = "disabled";
+ };
+
+ tdmout_b: audio-controller@540 {
+ compatible = "amlogic,g12a-tdmout";
+ reg = <0x0 0x540 0x0 0x40>;
+ sound-name-prefix = "TDMOUT_B";
+ clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
+ <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
+ <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
+ <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
+ <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
+ clock-names = "pclk", "sclk", "sclk_sel",
+ "lrclk", "lrclk_sel";
+ status = "disabled";
+ };
+
+ tdmout_c: audio-controller@580 {
+ compatible = "amlogic,g12a-tdmout";
+ reg = <0x0 0x580 0x0 0x40>;
+ sound-name-prefix = "TDMOUT_C";
+ clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
+ <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
+ <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
+ <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
+ <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
+ clock-names = "pclk", "sclk", "sclk_sel",
+ "lrclk", "lrclk_sel";
+ status = "disabled";
+ };
+
+ spdifout_b: audio-controller@680 {
+ compatible = "amlogic,g12a-spdifout",
+ "amlogic,axg-spdifout";
+ reg = <0x0 0x680 0x0 0x50>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SPDIFOUT_B";
+ clocks = <&clkc_audio AUD_CLKID_SPDIFOUT_B>,
+ <&clkc_audio AUD_CLKID_SPDIFOUT_B_CLK>;
+ clock-names = "pclk", "mclk";
+ status = "disabled";
+ };
+
+ tohdmitx: audio-controller@744 {
+ compatible = "amlogic,g12a-tohdmitx";
+ reg = <0x0 0x744 0x0 0x4>;
+ #sound-dai-cells = <1>;
+ sound-name-prefix = "TOHDMITX";
+ status = "disabled";
+ };
+ };
+
usb3_pcie_phy: phy@46000 {
compatible = "amlogic,g12a-usb3-pcie-phy";
reg = <0x0 0x46000 0x0 0x2000>;
@@ -314,6 +1737,38 @@
assigned-clock-rates = <100000000>;
#phy-cells = <1>;
};
+
+ eth_phy: mdio-multiplexer@4c000 {
+ compatible = "amlogic,g12a-mdio-mux";
+ reg = <0x0 0x4c000 0x0 0xa4>;
+ clocks = <&clkc CLKID_ETH_PHY>,
+ <&xtal>,
+ <&clkc CLKID_MPLL_50M>;
+ clock-names = "pclk", "clkin0", "clkin1";
+ mdio-parent-bus = <&mdio0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ext_mdio: mdio@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ int_mdio: mdio@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ internal_ephy: ethernet_phy@8 {
+ compatible = "ethernet-phy-id0180.3301",
+ "ethernet-phy-ieee802.3-c22";
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <8>;
+ max-speed = <100>;
+ };
+ };
+ };
};
aobus: bus@ff800000 {
@@ -401,6 +1856,145 @@
gpio-ranges = <&ao_pinctrl 0 0 15>;
};
+ i2c_ao_sck_pins: i2c_ao_sck_pins {
+ mux {
+ groups = "i2c_ao_sck";
+ function = "i2c_ao";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c_ao_sda_pins: i2c_ao_sda {
+ mux {
+ groups = "i2c_ao_sda";
+ function = "i2c_ao";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c_ao_sck_e_pins: i2c_ao_sck_e {
+ mux {
+ groups = "i2c_ao_sck_e";
+ function = "i2c_ao";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ i2c_ao_sda_e_pins: i2c_ao_sda_e {
+ mux {
+ groups = "i2c_ao_sda_e";
+ function = "i2c_ao";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ mclk0_ao_pins: mclk0-ao {
+ mux {
+ groups = "mclk0_ao";
+ function = "mclk0_ao";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_ao_b_din0_pins: tdm-ao-b-din0 {
+ mux {
+ groups = "tdm_ao_b_din0";
+ function = "tdm_ao_b";
+ bias-disable;
+ };
+ };
+
+ spdif_ao_out_pins: spdif-ao-out {
+ mux {
+ groups = "spdif_ao_out";
+ function = "spdif_ao_out";
+ drive-strength-microamp = <500>;
+ bias-disable;
+ };
+ };
+
+ tdm_ao_b_din1_pins: tdm-ao-b-din1 {
+ mux {
+ groups = "tdm_ao_b_din1";
+ function = "tdm_ao_b";
+ bias-disable;
+ };
+ };
+
+ tdm_ao_b_din2_pins: tdm-ao-b-din2 {
+ mux {
+ groups = "tdm_ao_b_din2";
+ function = "tdm_ao_b";
+ bias-disable;
+ };
+ };
+
+ tdm_ao_b_dout0_pins: tdm-ao-b-dout0 {
+ mux {
+ groups = "tdm_ao_b_dout0";
+ function = "tdm_ao_b";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_ao_b_dout1_pins: tdm-ao-b-dout1 {
+ mux {
+ groups = "tdm_ao_b_dout1";
+ function = "tdm_ao_b";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_ao_b_dout2_pins: tdm-ao-b-dout2 {
+ mux {
+ groups = "tdm_ao_b_dout2";
+ function = "tdm_ao_b";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_ao_b_fs_pins: tdm-ao-b-fs {
+ mux {
+ groups = "tdm_ao_b_fs";
+ function = "tdm_ao_b";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_ao_b_sclk_pins: tdm-ao-b-sclk {
+ mux {
+ groups = "tdm_ao_b_sclk";
+ function = "tdm_ao_b";
+ bias-disable;
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs {
+ mux {
+ groups = "tdm_ao_b_slv_fs";
+ function = "tdm_ao_b";
+ bias-disable;
+ };
+ };
+
+ tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk {
+ mux {
+ groups = "tdm_ao_b_slv_sclk";
+ function = "tdm_ao_b";
+ bias-disable;
+ };
+ };
+
uart_ao_a_pins: uart-a-ao {
mux {
groups = "uart_ao_a_tx",
@@ -418,6 +2012,69 @@
bias-disable;
};
};
+
+ pwm_ao_a_pins: pwm-ao-a {
+ mux {
+ groups = "pwm_ao_a";
+ function = "pwm_ao_a";
+ bias-disable;
+ };
+ };
+
+ pwm_ao_b_pins: pwm-ao-b {
+ mux {
+ groups = "pwm_ao_b";
+ function = "pwm_ao_b";
+ bias-disable;
+ };
+ };
+
+ pwm_ao_c_4_pins: pwm-ao-c-4 {
+ mux {
+ groups = "pwm_ao_c_4";
+ function = "pwm_ao_c";
+ bias-disable;
+ };
+ };
+
+ pwm_ao_c_6_pins: pwm-ao-c-6 {
+ mux {
+ groups = "pwm_ao_c_6";
+ function = "pwm_ao_c";
+ bias-disable;
+ };
+ };
+
+ pwm_ao_d_5_pins: pwm-ao-d-5 {
+ mux {
+ groups = "pwm_ao_d_5";
+ function = "pwm_ao_d";
+ bias-disable;
+ };
+ };
+
+ pwm_ao_d_10_pins: pwm-ao-d-10 {
+ mux {
+ groups = "pwm_ao_d_10";
+ function = "pwm_ao_d";
+ bias-disable;
+ };
+ };
+
+ pwm_ao_d_e_pins: pwm-ao-d-e {
+ mux {
+ groups = "pwm_ao_d_e";
+ function = "pwm_ao_d";
+ };
+ };
+
+ remote_input_ao_pins: remote-input-ao {
+ mux {
+ groups = "remote_ao_input";
+ function = "remote_ao_input";
+ bias-disable;
+ };
+ };
};
};
@@ -445,12 +2102,19 @@
status = "disabled";
};
+ pwm_AO_cd: pwm@2000 {
+ compatible = "amlogic,meson-g12a-ao-pwm-cd";
+ reg = <0x0 0x2000 0x0 0x20>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
uart_AO: serial@3000 {
compatible = "amlogic,meson-gx-uart",
"amlogic,meson-ao-uart";
reg = <0x0 0x3000 0x0 0x18>;
interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
- clocks = <&xtal>, <&xtal>, <&xtal>;
+ clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
@@ -460,11 +2124,35 @@
"amlogic,meson-ao-uart";
reg = <0x0 0x4000 0x0 0x18>;
interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
- clocks = <&xtal>, <&xtal>, <&xtal>;
+ clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
+ i2c_AO: i2c@5000 {
+ compatible = "amlogic,meson-axg-i2c";
+ status = "disabled";
+ reg = <0x0 0x05000 0x0 0x20>;
+ interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clkc CLKID_I2C>;
+ };
+
+ pwm_AO_ab: pwm@7000 {
+ compatible = "amlogic,meson-g12a-ao-pwm-ab";
+ reg = <0x0 0x7000 0x0 0x20>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ ir: ir@8000 {
+ compatible = "amlogic,meson-gxbb-ir";
+ reg = <0x0 0x8000 0x0 0x20>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ };
+
saradc: adc@9000 {
compatible = "amlogic,meson-g12a-saradc",
"amlogic,meson-saradc";
@@ -533,6 +2221,76 @@
#reset-cells = <1>;
};
+ gpio_intc: interrupt-controller@f080 {
+ compatible = "amlogic,meson-g12a-gpio-intc",
+ "amlogic,meson-gpio-intc";
+ reg = <0x0 0xf080 0x0 0x10>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
+ };
+
+ pwm_ef: pwm@19000 {
+ compatible = "amlogic,meson-g12a-ee-pwm";
+ reg = <0x0 0x19000 0x0 0x20>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm_cd: pwm@1a000 {
+ compatible = "amlogic,meson-g12a-ee-pwm";
+ reg = <0x0 0x1a000 0x0 0x20>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm_ab: pwm@1b000 {
+ compatible = "amlogic,meson-g12a-ee-pwm";
+ reg = <0x0 0x1b000 0x0 0x20>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@1c000 {
+ compatible = "amlogic,meson-axg-i2c";
+ status = "disabled";
+ reg = <0x0 0x1c000 0x0 0x20>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clkc CLKID_I2C>;
+ };
+
+ i2c2: i2c@1d000 {
+ compatible = "amlogic,meson-axg-i2c";
+ status = "disabled";
+ reg = <0x0 0x1d000 0x0 0x20>;
+ interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clkc CLKID_I2C>;
+ };
+
+ i2c1: i2c@1e000 {
+ compatible = "amlogic,meson-axg-i2c";
+ status = "disabled";
+ reg = <0x0 0x1e000 0x0 0x20>;
+ interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clkc CLKID_I2C>;
+ };
+
+ i2c0: i2c@1f000 {
+ compatible = "amlogic,meson-axg-i2c";
+ status = "disabled";
+ reg = <0x0 0x1f000 0x0 0x20>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clkc CLKID_I2C>;
+ };
+
clk_msr: clock-measure@18000 {
compatible = "amlogic,meson-g12a-clk-measure";
reg = <0x0 0x18000 0x0 0x10>;
@@ -566,6 +2324,43 @@
};
};
+ sd_emmc_a: sd@ffe03000 {
+ compatible = "amlogic,meson-axg-mmc";
+ reg = <0x0 0xffe03000 0x0 0x800>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ clocks = <&clkc CLKID_SD_EMMC_A>,
+ <&clkc CLKID_SD_EMMC_A_CLK0>,
+ <&clkc CLKID_FCLK_DIV2>;
+ clock-names = "core", "clkin0", "clkin1";
+ resets = <&reset RESET_SD_EMMC_A>;
+ amlogic,dram-access-quirk;
+ };
+
+ sd_emmc_b: sd@ffe05000 {
+ compatible = "amlogic,meson-axg-mmc";
+ reg = <0x0 0xffe05000 0x0 0x800>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ clocks = <&clkc CLKID_SD_EMMC_B>,
+ <&clkc CLKID_SD_EMMC_B_CLK0>,
+ <&clkc CLKID_FCLK_DIV2>;
+ clock-names = "core", "clkin0", "clkin1";
+ resets = <&reset RESET_SD_EMMC_B>;
+ };
+
+ sd_emmc_c: mmc@ffe07000 {
+ compatible = "amlogic,meson-axg-mmc";
+ reg = <0x0 0xffe07000 0x0 0x800>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ clocks = <&clkc CLKID_SD_EMMC_C>,
+ <&clkc CLKID_SD_EMMC_C_CLK0>,
+ <&clkc CLKID_FCLK_DIV2>;
+ clock-names = "core", "clkin0", "clkin1";
+ resets = <&reset RESET_SD_EMMC_C>;
+ };
+
usb: usb@ffe09000 {
status = "disabled";
compatible = "amlogic,meson-g12a-usb-ctrl";
diff --git a/arch/arm/dts/meson-g12b-odroid-n2.dts b/arch/arm/dts/meson-g12b-odroid-n2.dts
new file mode 100644
index 0000000..81780ff
--- /dev/null
+++ b/arch/arm/dts/meson-g12b-odroid-n2.dts
@@ -0,0 +1,386 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/dts-v1/;
+
+#include "meson-g12b.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+ compatible = "hardkernel,odroid-n2", "amlogic,g12b";
+ model = "Hardkernel ODROID-N2";
+
+ aliases {
+ serial0 = &uart_AO;
+ ethernet0 = ðmac;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ blue {
+ label = "n2:blue";
+ gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ tflash_vdd: regulator-tflash_vdd {
+ compatible = "regulator-fixed";
+
+ regulator-name = "TFLASH_VDD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio_ao GPIOAO_8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ tf_io: gpio-regulator-tf_io {
+ compatible = "regulator-gpio";
+
+ regulator-name = "TF_IO";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0>;
+
+ states = <3300000 0
+ 1800000 1>;
+ };
+
+ flash_1v8: regulator-flash_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "FLASH_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ regulator-always-on;
+ };
+
+ main_12v: regulator-main_12v {
+ compatible = "regulator-fixed";
+ regulator-name = "12V";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ };
+
+ vcc_5v: regulator-vcc_5v {
+ compatible = "regulator-fixed";
+ regulator-name = "5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ vin-supply = <&main_12v>;
+ };
+
+ vcc_1v8: regulator-vcc_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ regulator-always-on;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ /* FIXME: actually controlled by VDDCPU_B_EN */
+ };
+
+ hub_5v: regulator-hub_5v {
+ compatible = "regulator-fixed";
+ regulator-name = "HUB_5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc_5v>;
+
+ /* Connected to the Hub CHIPENABLE, LOW sets low power state */
+ gpio = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ usb_pwr_en: regulator-usb_pwr_en {
+ compatible = "regulator-fixed";
+ regulator-name = "USB_PWR_EN";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc_5v>;
+
+ /* Connected to the microUSB port power enable */
+ gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vddao_1v8: regulator-vddao_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&main_12v>;
+ regulator-always-on;
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ sound {
+ compatible = "amlogic,axg-sound-card";
+ model = "G12A-ODROIDN2";
+ audio-aux-devs = <&tdmout_b>;
+ audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+ "TDMOUT_B IN 1", "FRDDR_B OUT 1",
+ "TDMOUT_B IN 2", "FRDDR_C OUT 1",
+ "TDM_B Playback", "TDMOUT_B OUT";
+
+ assigned-clocks = <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+ status = "okay";
+
+ dai-link-0 {
+ sound-dai = <&frddr_a>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&frddr_b>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&frddr_c>;
+ };
+
+ /* 8ch hdmi interface */
+ dai-link-3 {
+ sound-dai = <&tdmif_b>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ dai-tdm-slot-tx-mask-1 = <1 1>;
+ dai-tdm-slot-tx-mask-2 = <1 1>;
+ dai-tdm-slot-tx-mask-3 = <1 1>;
+ mclk-fs = <256>;
+
+ codec {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+ };
+ };
+
+ /* hdmi glue */
+ dai-link-4 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+ codec {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+};
+
+&arb {
+ status = "okay";
+};
+
+&cec_AO {
+ pinctrl-0 = <&cec_ao_a_h_pins>;
+ pinctrl-names = "default";
+ status = "disabled";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&cecb_AO {
+ pinctrl-0 = <&cec_ao_b_h_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&clkc_audio {
+ status = "okay";
+};
+
+&ext_mdio {
+ external_phy: ethernet-phy@0 {
+ /* Realtek RTL8211F (0x001cc916) */
+ reg = <0>;
+ max-speed = <1000>;
+
+ reset-assert-us = <10000>;
+ reset-deassert-us = <30000>;
+ reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+
+ interrupt-parent = <&gpio_intc>;
+ /* MAC_INTR on GPIOZ_14 */
+ interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+ðmac {
+ pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ phy-mode = "rgmii";
+ phy-handle = <&external_phy>;
+ amlogic,tx-delay-ns = <2>;
+};
+
+&frddr_a {
+ status = "okay";
+};
+
+&frddr_b {
+ status = "okay";
+};
+
+&frddr_c {
+ status = "okay";
+};
+
+&gpio {
+ /*
+ * WARNING: The USB Hub on the Odroid-N2 needs a reset signal
+ * to be turned high in order to be detected by the USB Controller
+ * This signal should be handled by a USB specific power sequence
+ * in order to reset the Hub when USB bus is powered down.
+ */
+ usb-hub {
+ gpio-hog;
+ gpios = <GPIOH_4 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "usb-hub-reset";
+ };
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
+ pinctrl-names = "default";
+ hdmi-supply = <&vcc_5v>;
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+&ir {
+ status = "okay";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_c_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_c_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <50000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&tflash_vdd>;
+ vqmmc-supply = <&tf_io>;
+
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ disable-wp;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&flash_1v8>;
+};
+
+&tdmif_b {
+ status = "okay";
+};
+
+&tdmout_b {
+ status = "okay";
+};
+
+&tohdmitx {
+ status = "okay";
+};
+
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+&usb {
+ status = "okay";
+ vbus-supply = <&usb_pwr_en>;
+};
+
+&usb2_phy0 {
+ phy-supply = <&vcc_5v>;
+};
+
+&usb2_phy1 {
+ /* Enable the hub which is connected to this port */
+ phy-supply = <&hub_5v>;
+};
diff --git a/arch/arm/dts/meson-g12b.dtsi b/arch/arm/dts/meson-g12b.dtsi
new file mode 100644
index 0000000..9e88e51
--- /dev/null
+++ b/arch/arm/dts/meson-g12b.dtsi
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include "meson-g12a.dtsi"
+
+/ {
+ compatible = "amlogic,g12b";
+
+ cpus {
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu100>;
+ };
+
+ core1 {
+ cpu = <&cpu101>;
+ };
+
+ core2 {
+ cpu = <&cpu102>;
+ };
+
+ core3 {
+ cpu = <&cpu103>;
+ };
+ };
+ };
+
+ /delete-node/ cpu@2;
+ /delete-node/ cpu@3;
+
+ cpu100: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ };
+
+ cpu101: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x0 0x101>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ };
+
+ cpu102: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x0 0x102>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ };
+
+ cpu103: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x0 0x103>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ };
+ };
+};
+
+&clkc {
+ compatible = "amlogic,g12b-clkc";
+};
diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi
index 448d1d7..64079c6 100644
--- a/arch/arm/dts/mt7623.dtsi
+++ b/arch/arm/dts/mt7623.dtsi
@@ -248,6 +248,13 @@
status = "disabled";
};
+ hifsys: syscon@1a000000 {
+ compatible = "mediatek,mt7623-hifsys", "syscon";
+ reg = <0x1a000000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
ethsys: syscon@1b000000 {
compatible = "mediatek,mt7623-ethsys", "syscon";
reg = <0x1b000000 0x1000>;
diff --git a/arch/arm/dts/mt7629-rfb.dts b/arch/arm/dts/mt7629-rfb.dts
index 4612218..0981f9b 100644
--- a/arch/arm/dts/mt7629-rfb.dts
+++ b/arch/arm/dts/mt7629-rfb.dts
@@ -13,12 +13,11 @@
compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
aliases {
- spi0 = &qspi;
+ spi0 = &snfi;
};
chosen {
stdout-path = &uart0;
- tick-timer = &timer0;
};
};
@@ -34,7 +33,14 @@
};
&pinctrl {
- qspi_pins: qspi-pins {
+ snfi_pins: snfi-pins {
+ mux {
+ function = "flash";
+ groups = "snfi";
+ };
+ };
+
+ snor_pins: snor-pins {
mux {
function = "flash";
groups = "spi_nor";
@@ -56,9 +62,10 @@
};
};
-&qspi {
- pinctrl-names = "default";
- pinctrl-0 = <&qspi_pins>;
+&snfi {
+ pinctrl-names = "default", "snfi";
+ pinctrl-0 = <&snor_pins>;
+ pinctrl-1 = <&snfi_pins>;
status = "okay";
spi-flash@0{
diff --git a/arch/arm/dts/mt7629.dtsi b/arch/arm/dts/mt7629.dtsi
index c87115e..8ff1916 100644
--- a/arch/arm/dts/mt7629.dtsi
+++ b/arch/arm/dts/mt7629.dtsi
@@ -82,8 +82,8 @@
compatible = "mediatek,timer";
reg = <0x10004000 0x80>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&topckgen CLK_TOP_10M_SEL>,
- <&topckgen CLK_TOP_CLKXTAL_D4>;
+ clocks = <&topckgen CLK_TOP_CLKXTAL_D4>,
+ <&topckgen CLK_TOP_10M_SEL>;
clock-names = "mux", "src";
u-boot,dm-pre-reloc;
};
@@ -215,10 +215,16 @@
status = "disabled";
};
- qspi: qspi@11014000 {
- compatible = "mediatek,mt7629-qspi";
- reg = <0x11014000 0xe0>, <0x30000000 0x10000000>;
- reg-names = "reg_base", "mem_base";
+ snfi: snfi@1100d000 {
+ compatible = "mediatek,mtk-snfi-spi";
+ reg = <0x1100d000 0x2000>;
+ clocks = <&pericfg CLK_PERI_NFI_PD>,
+ <&pericfg CLK_PERI_SNFI_PD>;
+ clock-names = "nfi_clk", "pad_clk";
+ assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
+ <&topckgen CLK_TOP_NFI_INFRA_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
+ <&topckgen CLK_TOP_UNIVPLL2_D8>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/dts/mt8516-pumpkin.dts b/arch/arm/dts/mt8516-pumpkin.dts
new file mode 100644
index 0000000..cd43c1f
--- /dev/null
+++ b/arch/arm/dts/mt8516-pumpkin.dts
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2019 BayLibre SAS.
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+/dts-v1/;
+
+#include <config.h>
+#include "mt8516.dtsi"
+
+/ {
+ model = "Pumpkin MT8516";
+
+ chosen {
+ stdout-path = &uart0;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x40000000 0x20000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ /* 128 KiB reserved for ARM Trusted Firmware (BL31) */
+ bl31_secmon_reserved: secmon@43000000 {
+ no-map;
+ reg = <0 0x43000000 0 0x20000>;
+ };
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_default>;
+ bus-width = <4>;
+ max-frequency = <200000000>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ cap-mmc-hw-reset;
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_1p8v>;
+ non-removable;
+ status = "okay";
+};
+
+&pinctrl {
+ mmc0_pins_default: mmc0default {
+ mux {
+ function = "msdc";
+ groups = "msdc0";
+ };
+
+ conf-cmd-data {
+ pins = "MSDC0_CMD", "MSDC0_DAT0", "MSDC0_DAT1",
+ "MSDC0_DAT2", "MSDC0_DAT3", "MSDC0_DAT4",
+ "MSDC0_DAT5", "MSDC0_DAT6", "MSDC0_DAT7";
+ input-enable;
+ bias-pull-up;
+ };
+
+ conf-clk {
+ pins = "MSDC0_CLK";
+ bias-pull-down;
+ };
+
+ conf-rst {
+ pins = "MSDC0_RSTB";
+ bias-pull-up;
+ };
+ };
+
+ uart0_pins: uart0 {
+ mux {
+ function = "uart";
+ groups = "uart0_0_rxd_txd";
+ };
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+};
diff --git a/arch/arm/dts/mxs-pinfunc.h b/arch/arm/dts/mxs-pinfunc.h
new file mode 100644
index 0000000..c6da987
--- /dev/null
+++ b/arch/arm/dts/mxs-pinfunc.h
@@ -0,0 +1,31 @@
+/*
+ * Header providing constants for i.MX28 pinctrl bindings.
+ *
+ * Copyright (C) 2013 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __DT_BINDINGS_MXS_PINCTRL_H__
+#define __DT_BINDINGS_MXS_PINCTRL_H__
+
+/* fsl,drive-strength property */
+#define MXS_DRIVE_4mA 0
+#define MXS_DRIVE_8mA 1
+#define MXS_DRIVE_12mA 2
+#define MXS_DRIVE_16mA 3
+
+/* fsl,voltage property */
+#define MXS_VOLTAGE_LOW 0
+#define MXS_VOLTAGE_HIGH 1
+
+/* fsl,pull-up property */
+#define MXS_PULL_DISABLE 0
+#define MXS_PULL_ENABLE 1
+
+#endif /* __DT_BINDINGS_MXS_PINCTRL_H__ */
diff --git a/arch/arm/dts/omap3-evm-37xx.dts b/arch/arm/dts/omap3-evm-37xx.dts
index 5a4ba0a..a14303b 100644
--- a/arch/arm/dts/omap3-evm-37xx.dts
+++ b/arch/arm/dts/omap3-evm-37xx.dts
@@ -90,19 +90,19 @@
label = "X-Loader";
reg = <0 0x80000>;
};
- partition@0x80000 {
+ partition@80000 {
label = "U-Boot";
reg = <0x80000 0x1c0000>;
};
- partition@0x1c0000 {
+ partition@1c0000 {
label = "Environment";
reg = <0x240000 0x40000>;
};
- partition@0x280000 {
+ partition@280000 {
label = "Kernel";
reg = <0x280000 0x500000>;
};
- partition@0x780000 {
+ partition@780000 {
label = "Filesystem";
reg = <0x780000 0x1f880000>;
};
diff --git a/arch/arm/dts/omap3-evm-common.dtsi b/arch/arm/dts/omap3-evm-common.dtsi
index ee64191..17c89df 100644
--- a/arch/arm/dts/omap3-evm-common.dtsi
+++ b/arch/arm/dts/omap3-evm-common.dtsi
@@ -122,6 +122,7 @@
};
&mmc2 {
+ interrupts-extended = <&intc 86 &omap3_pmx_core 0x12e>;
vmmc-supply = <&wl12xx_vmmc>;
non-removable;
bus-width = <4>;
@@ -132,8 +133,10 @@
wlcore: wlcore@2 {
compatible = "ti,wl1271";
reg = <2>;
- interrupt-parent = <&gpio5>;
- interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 149 */
+ /* gpio_149 with uart1_rts pad as wakeirq */
+ interrupts-extended = <&gpio5 21 IRQ_TYPE_EDGE_RISING>,
+ <&omap3_pmx_core 0x14e>;
+ interrupt-names = "irq", "wakeup";
ref-clock-frequency = <38400000>;
};
};
diff --git a/arch/arm/dts/omap3-evm-processor-common.dtsi b/arch/arm/dts/omap3-evm-processor-common.dtsi
index ce7f42f..b4109f4 100644
--- a/arch/arm/dts/omap3-evm-processor-common.dtsi
+++ b/arch/arm/dts/omap3-evm-processor-common.dtsi
@@ -86,6 +86,10 @@
OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
+ OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dir_dat0 */
+ OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dir_dat1 */
+ OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dir_cmd */
+ OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */
>;
};
@@ -127,9 +131,13 @@
>;
};
+ /*
+ * Note that gpio_150 pulled high with internal pull to prevent wlcore
+ * reset on return from off mode in idle.
+ */
wl12xx_gpio: pinmux_wl12xx_gpio {
pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x2180, PIN_OUTPUT | MUX_MODE4) /* uart1_cts.gpio_150 */
+ OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_cts.gpio_150 */
OMAP3_CORE1_IOPAD(0x217e, PIN_INPUT | MUX_MODE4) /* uart1_rts.gpio_149 */
>;
};
diff --git a/arch/arm/dts/r7s72100-gr-peach-u-boot.dts b/arch/arm/dts/r7s72100-gr-peach-u-boot.dts
index 28247d1..30e35e4 100644
--- a/arch/arm/dts/r7s72100-gr-peach-u-boot.dts
+++ b/arch/arm/dts/r7s72100-gr-peach-u-boot.dts
@@ -37,6 +37,15 @@
};
};
+ reg_usbhs0_vbus: regulator-usbhs0-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usbhs0_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&port4 1 GPIO_ACTIVE_LOW>;
+ };
+
+
rpc: rpc@0xee200000 {
compatible = "renesas,rpc-r7s72100", "renesas,rpc";
reg = <0x3fefa000 0x100>, <0x18000000 0x08000000>;
@@ -76,3 +85,8 @@
&scif2_pins {
u-boot,dm-pre-reloc;
};
+
+&usbhs0 {
+ vbus-supply = <®_usbhs0_vbus>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/r8a7795-h3ulcb-u-boot.dts b/arch/arm/dts/r8a7795-h3ulcb-u-boot.dts
index dda339b..ef1c57f 100644
--- a/arch/arm/dts/r8a7795-h3ulcb-u-boot.dts
+++ b/arch/arm/dts/r8a7795-h3ulcb-u-boot.dts
@@ -30,3 +30,7 @@
mmc-hs400-1_8v;
max-frequency = <200000000>;
};
+
+&vcc_sdhi0 {
+ u-boot,off-on-delay-us = <20000>;
+};
diff --git a/arch/arm/dts/r8a7795-salvator-x-u-boot.dts b/arch/arm/dts/r8a7795-salvator-x-u-boot.dts
index 66b608a..e93afe3 100644
--- a/arch/arm/dts/r8a7795-salvator-x-u-boot.dts
+++ b/arch/arm/dts/r8a7795-salvator-x-u-boot.dts
@@ -26,3 +26,11 @@
sd-uhs-sdr104;
max-frequency = <208000000>;
};
+
+&vcc_sdhi0 {
+ u-boot,off-on-delay-us = <20000>;
+};
+
+&vcc_sdhi3 {
+ u-boot,off-on-delay-us = <20000>;
+};
diff --git a/arch/arm/dts/r8a7795.dtsi b/arch/arm/dts/r8a7795.dtsi
index abeac30..097538c 100644
--- a/arch/arm/dts/r8a7795.dtsi
+++ b/arch/arm/dts/r8a7795.dtsi
@@ -462,6 +462,76 @@
reg = <0 0xe6060000 0 0x50c>;
};
+ cmt0: timer@e60f0000 {
+ compatible = "renesas,r8a7795-cmt0",
+ "renesas,rcar-gen3-cmt0";
+ reg = <0 0xe60f0000 0 0x1004>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 303>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 303>;
+ status = "disabled";
+ };
+
+ cmt1: timer@e6130000 {
+ compatible = "renesas,r8a7795-cmt1",
+ "renesas,rcar-gen3-cmt1";
+ reg = <0 0xe6130000 0 0x1004>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 302>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 302>;
+ status = "disabled";
+ };
+
+ cmt2: timer@e6140000 {
+ compatible = "renesas,r8a7795-cmt1",
+ "renesas,rcar-gen3-cmt1";
+ reg = <0 0xe6140000 0 0x1004>;
+ interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 301>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 301>;
+ status = "disabled";
+ };
+
+ cmt3: timer@e6148000 {
+ compatible = "renesas,r8a7795-cmt1",
+ "renesas,rcar-gen3-cmt1";
+ reg = <0 0xe6148000 0 0x1004>;
+ interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 300>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 300>;
+ status = "disabled";
+ };
+
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a7795-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
@@ -1836,7 +1906,7 @@
<0 0xec5a0000 0 0x100>, /* ADG */
<0 0xec540000 0 0x1000>, /* SSIU */
<0 0xec541000 0 0x280>, /* SSI */
- <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
+ <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
clocks = <&cpg CPG_MOD 1005>,
diff --git a/arch/arm/dts/r8a7796-m3ulcb-u-boot.dts b/arch/arm/dts/r8a7796-m3ulcb-u-boot.dts
index 1defe84..314eacc 100644
--- a/arch/arm/dts/r8a7796-m3ulcb-u-boot.dts
+++ b/arch/arm/dts/r8a7796-m3ulcb-u-boot.dts
@@ -30,3 +30,7 @@
mmc-hs400-1_8v;
max-frequency = <200000000>;
};
+
+&vcc_sdhi0 {
+ u-boot,off-on-delay-us = <20000>;
+};
diff --git a/arch/arm/dts/r8a7796-salvator-x-u-boot.dts b/arch/arm/dts/r8a7796-salvator-x-u-boot.dts
index 2610f8b..2a7b149 100644
--- a/arch/arm/dts/r8a7796-salvator-x-u-boot.dts
+++ b/arch/arm/dts/r8a7796-salvator-x-u-boot.dts
@@ -26,3 +26,11 @@
sd-uhs-sdr104;
max-frequency = <208000000>;
};
+
+&vcc_sdhi0 {
+ u-boot,off-on-delay-us = <20000>;
+};
+
+&vcc_sdhi3 {
+ u-boot,off-on-delay-us = <20000>;
+};
diff --git a/arch/arm/dts/r8a7796-salvator-x.dts b/arch/arm/dts/r8a7796-salvator-x.dts
index b4f9567..2aefa53 100644
--- a/arch/arm/dts/r8a7796-salvator-x.dts
+++ b/arch/arm/dts/r8a7796-salvator-x.dts
@@ -68,6 +68,7 @@
ports {
/* rsnd_port0 is on salvator-common */
rsnd_port1: port@1 {
+ reg = <1>;
rsnd_endpoint1: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
diff --git a/arch/arm/dts/r8a7796.dtsi b/arch/arm/dts/r8a7796.dtsi
index cdf7848..d5e2f4a 100644
--- a/arch/arm/dts/r8a7796.dtsi
+++ b/arch/arm/dts/r8a7796.dtsi
@@ -1775,7 +1775,7 @@
<0 0xec5a0000 0 0x100>, /* ADG */
<0 0xec540000 0 0x1000>, /* SSIU */
<0 0xec541000 0 0x280>, /* SSI */
- <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
+ <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
clocks = <&cpg CPG_MOD 1005>,
@@ -2162,17 +2162,6 @@
dma-names = "rx", "tx";
};
};
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- };
- port@1 {
- reg = <1>;
- };
- };
};
audma0: dma-controller@ec700000 {
diff --git a/arch/arm/dts/r8a77965-m3nulcb-u-boot.dts b/arch/arm/dts/r8a77965-m3nulcb-u-boot.dts
index 8ecfc7a..cf10431 100644
--- a/arch/arm/dts/r8a77965-m3nulcb-u-boot.dts
+++ b/arch/arm/dts/r8a77965-m3nulcb-u-boot.dts
@@ -32,3 +32,7 @@
max-frequency = <200000000>;
status = "okay";
};
+
+&vcc_sdhi0 {
+ u-boot,off-on-delay-us = <20000>;
+};
diff --git a/arch/arm/dts/r8a77965-salvator-x-u-boot.dts b/arch/arm/dts/r8a77965-salvator-x-u-boot.dts
index 208ed56..e4bd2d3 100644
--- a/arch/arm/dts/r8a77965-salvator-x-u-boot.dts
+++ b/arch/arm/dts/r8a77965-salvator-x-u-boot.dts
@@ -29,3 +29,11 @@
max-frequency = <208000000>;
status = "okay";
};
+
+&vcc_sdhi0 {
+ u-boot,off-on-delay-us = <20000>;
+};
+
+&vcc_sdhi3 {
+ u-boot,off-on-delay-us = <20000>;
+};
diff --git a/arch/arm/dts/r8a77965.dtsi b/arch/arm/dts/r8a77965.dtsi
index 9763d10..2554b17 100644
--- a/arch/arm/dts/r8a77965.dtsi
+++ b/arch/arm/dts/r8a77965.dtsi
@@ -317,6 +317,76 @@
reg = <0 0xe6060000 0 0x50c>;
};
+ cmt0: timer@e60f0000 {
+ compatible = "renesas,r8a77965-cmt0",
+ "renesas,rcar-gen3-cmt0";
+ reg = <0 0xe60f0000 0 0x1004>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 303>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 303>;
+ status = "disabled";
+ };
+
+ cmt1: timer@e6130000 {
+ compatible = "renesas,r8a77965-cmt1",
+ "renesas,rcar-gen3-cmt1";
+ reg = <0 0xe6130000 0 0x1004>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 302>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 302>;
+ status = "disabled";
+ };
+
+ cmt2: timer@e6140000 {
+ compatible = "renesas,r8a77965-cmt1",
+ "renesas,rcar-gen3-cmt1";
+ reg = <0 0xe6140000 0 0x1004>;
+ interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 301>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 301>;
+ status = "disabled";
+ };
+
+ cmt3: timer@e6148000 {
+ compatible = "renesas,r8a77965-cmt1",
+ "renesas,rcar-gen3-cmt1";
+ reg = <0 0xe6148000 0 0x1004>;
+ interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 300>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 300>;
+ status = "disabled";
+ };
+
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a77965-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
@@ -1461,7 +1531,7 @@
<0 0xec5a0000 0 0x100>, /* ADG */
<0 0xec540000 0 0x1000>, /* SSIU */
<0 0xec541000 0 0x280>, /* SSI */
- <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
+ <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
clocks = <&cpg CPG_MOD 1005>,
@@ -1585,56 +1655,267 @@
};
};
+ rcar_sound,ssiu {
+ ssiu00: ssiu-0 {
+ dmas = <&audma0 0x15>, <&audma1 0x16>;
+ dma-names = "rx", "tx";
+ };
+ ssiu01: ssiu-1 {
+ dmas = <&audma0 0x35>, <&audma1 0x36>;
+ dma-names = "rx", "tx";
+ };
+ ssiu02: ssiu-2 {
+ dmas = <&audma0 0x37>, <&audma1 0x38>;
+ dma-names = "rx", "tx";
+ };
+ ssiu03: ssiu-3 {
+ dmas = <&audma0 0x47>, <&audma1 0x48>;
+ dma-names = "rx", "tx";
+ };
+ ssiu04: ssiu-4 {
+ dmas = <&audma0 0x3F>, <&audma1 0x40>;
+ dma-names = "rx", "tx";
+ };
+ ssiu05: ssiu-5 {
+ dmas = <&audma0 0x43>, <&audma1 0x44>;
+ dma-names = "rx", "tx";
+ };
+ ssiu06: ssiu-6 {
+ dmas = <&audma0 0x4F>, <&audma1 0x50>;
+ dma-names = "rx", "tx";
+ };
+ ssiu07: ssiu-7 {
+ dmas = <&audma0 0x53>, <&audma1 0x54>;
+ dma-names = "rx", "tx";
+ };
+ ssiu10: ssiu-8 {
+ dmas = <&audma0 0x49>, <&audma1 0x4a>;
+ dma-names = "rx", "tx";
+ };
+ ssiu11: ssiu-9 {
+ dmas = <&audma0 0x4B>, <&audma1 0x4C>;
+ dma-names = "rx", "tx";
+ };
+ ssiu12: ssiu-10 {
+ dmas = <&audma0 0x57>, <&audma1 0x58>;
+ dma-names = "rx", "tx";
+ };
+ ssiu13: ssiu-11 {
+ dmas = <&audma0 0x59>, <&audma1 0x5A>;
+ dma-names = "rx", "tx";
+ };
+ ssiu14: ssiu-12 {
+ dmas = <&audma0 0x5F>, <&audma1 0x60>;
+ dma-names = "rx", "tx";
+ };
+ ssiu15: ssiu-13 {
+ dmas = <&audma0 0xC3>, <&audma1 0xC4>;
+ dma-names = "rx", "tx";
+ };
+ ssiu16: ssiu-14 {
+ dmas = <&audma0 0xC7>, <&audma1 0xC8>;
+ dma-names = "rx", "tx";
+ };
+ ssiu17: ssiu-15 {
+ dmas = <&audma0 0xCB>, <&audma1 0xCC>;
+ dma-names = "rx", "tx";
+ };
+ ssiu20: ssiu-16 {
+ dmas = <&audma0 0x63>, <&audma1 0x64>;
+ dma-names = "rx", "tx";
+ };
+ ssiu21: ssiu-17 {
+ dmas = <&audma0 0x67>, <&audma1 0x68>;
+ dma-names = "rx", "tx";
+ };
+ ssiu22: ssiu-18 {
+ dmas = <&audma0 0x6B>, <&audma1 0x6C>;
+ dma-names = "rx", "tx";
+ };
+ ssiu23: ssiu-19 {
+ dmas = <&audma0 0x6D>, <&audma1 0x6E>;
+ dma-names = "rx", "tx";
+ };
+ ssiu24: ssiu-20 {
+ dmas = <&audma0 0xCF>, <&audma1 0xCE>;
+ dma-names = "rx", "tx";
+ };
+ ssiu25: ssiu-21 {
+ dmas = <&audma0 0xEB>, <&audma1 0xEC>;
+ dma-names = "rx", "tx";
+ };
+ ssiu26: ssiu-22 {
+ dmas = <&audma0 0xED>, <&audma1 0xEE>;
+ dma-names = "rx", "tx";
+ };
+ ssiu27: ssiu-23 {
+ dmas = <&audma0 0xEF>, <&audma1 0xF0>;
+ dma-names = "rx", "tx";
+ };
+ ssiu30: ssiu-24 {
+ dmas = <&audma0 0x6f>, <&audma1 0x70>;
+ dma-names = "rx", "tx";
+ };
+ ssiu31: ssiu-25 {
+ dmas = <&audma0 0x21>, <&audma1 0x22>;
+ dma-names = "rx", "tx";
+ };
+ ssiu32: ssiu-26 {
+ dmas = <&audma0 0x23>, <&audma1 0x24>;
+ dma-names = "rx", "tx";
+ };
+ ssiu33: ssiu-27 {
+ dmas = <&audma0 0x25>, <&audma1 0x26>;
+ dma-names = "rx", "tx";
+ };
+ ssiu34: ssiu-28 {
+ dmas = <&audma0 0x27>, <&audma1 0x28>;
+ dma-names = "rx", "tx";
+ };
+ ssiu35: ssiu-29 {
+ dmas = <&audma0 0x29>, <&audma1 0x2A>;
+ dma-names = "rx", "tx";
+ };
+ ssiu36: ssiu-30 {
+ dmas = <&audma0 0x2B>, <&audma1 0x2C>;
+ dma-names = "rx", "tx";
+ };
+ ssiu37: ssiu-31 {
+ dmas = <&audma0 0x2D>, <&audma1 0x2E>;
+ dma-names = "rx", "tx";
+ };
+ ssiu40: ssiu-32 {
+ dmas = <&audma0 0x71>, <&audma1 0x72>;
+ dma-names = "rx", "tx";
+ };
+ ssiu41: ssiu-33 {
+ dmas = <&audma0 0x17>, <&audma1 0x18>;
+ dma-names = "rx", "tx";
+ };
+ ssiu42: ssiu-34 {
+ dmas = <&audma0 0x19>, <&audma1 0x1A>;
+ dma-names = "rx", "tx";
+ };
+ ssiu43: ssiu-35 {
+ dmas = <&audma0 0x1B>, <&audma1 0x1C>;
+ dma-names = "rx", "tx";
+ };
+ ssiu44: ssiu-36 {
+ dmas = <&audma0 0x1D>, <&audma1 0x1E>;
+ dma-names = "rx", "tx";
+ };
+ ssiu45: ssiu-37 {
+ dmas = <&audma0 0x1F>, <&audma1 0x20>;
+ dma-names = "rx", "tx";
+ };
+ ssiu46: ssiu-38 {
+ dmas = <&audma0 0x31>, <&audma1 0x32>;
+ dma-names = "rx", "tx";
+ };
+ ssiu47: ssiu-39 {
+ dmas = <&audma0 0x33>, <&audma1 0x34>;
+ dma-names = "rx", "tx";
+ };
+ ssiu50: ssiu-40 {
+ dmas = <&audma0 0x73>, <&audma1 0x74>;
+ dma-names = "rx", "tx";
+ };
+ ssiu60: ssiu-41 {
+ dmas = <&audma0 0x75>, <&audma1 0x76>;
+ dma-names = "rx", "tx";
+ };
+ ssiu70: ssiu-42 {
+ dmas = <&audma0 0x79>, <&audma1 0x7a>;
+ dma-names = "rx", "tx";
+ };
+ ssiu80: ssiu-43 {
+ dmas = <&audma0 0x7b>, <&audma1 0x7c>;
+ dma-names = "rx", "tx";
+ };
+ ssiu90: ssiu-44 {
+ dmas = <&audma0 0x7d>, <&audma1 0x7e>;
+ dma-names = "rx", "tx";
+ };
+ ssiu91: ssiu-45 {
+ dmas = <&audma0 0x7F>, <&audma1 0x80>;
+ dma-names = "rx", "tx";
+ };
+ ssiu92: ssiu-46 {
+ dmas = <&audma0 0x81>, <&audma1 0x82>;
+ dma-names = "rx", "tx";
+ };
+ ssiu93: ssiu-47 {
+ dmas = <&audma0 0x83>, <&audma1 0x84>;
+ dma-names = "rx", "tx";
+ };
+ ssiu94: ssiu-48 {
+ dmas = <&audma0 0xA3>, <&audma1 0xA4>;
+ dma-names = "rx", "tx";
+ };
+ ssiu95: ssiu-49 {
+ dmas = <&audma0 0xA5>, <&audma1 0xA6>;
+ dma-names = "rx", "tx";
+ };
+ ssiu96: ssiu-50 {
+ dmas = <&audma0 0xA7>, <&audma1 0xA8>;
+ dma-names = "rx", "tx";
+ };
+ ssiu97: ssiu-51 {
+ dmas = <&audma0 0xA9>, <&audma1 0xAA>;
+ dma-names = "rx", "tx";
+ };
+ };
+
rcar_sound,ssi {
ssi0: ssi-0 {
interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
- dma-names = "rx", "tx", "rxu", "txu";
+ dmas = <&audma0 0x01>, <&audma1 0x02>;
+ dma-names = "rx", "tx";
};
ssi1: ssi-1 {
interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
- dma-names = "rx", "tx", "rxu", "txu";
+ dmas = <&audma0 0x03>, <&audma1 0x04>;
+ dma-names = "rx", "tx";
};
ssi2: ssi-2 {
interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
- dma-names = "rx", "tx", "rxu", "txu";
+ dmas = <&audma0 0x05>, <&audma1 0x06>;
+ dma-names = "rx", "tx";
};
ssi3: ssi-3 {
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
- dma-names = "rx", "tx", "rxu", "txu";
+ dmas = <&audma0 0x07>, <&audma1 0x08>;
+ dma-names = "rx", "tx";
};
ssi4: ssi-4 {
interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
- dma-names = "rx", "tx", "rxu", "txu";
+ dmas = <&audma0 0x09>, <&audma1 0x0a>;
+ dma-names = "rx", "tx";
};
ssi5: ssi-5 {
interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
- dma-names = "rx", "tx", "rxu", "txu";
+ dmas = <&audma0 0x0b>, <&audma1 0x0c>;
+ dma-names = "rx", "tx";
};
ssi6: ssi-6 {
interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
- dma-names = "rx", "tx", "rxu", "txu";
+ dmas = <&audma0 0x0d>, <&audma1 0x0e>;
+ dma-names = "rx", "tx";
};
ssi7: ssi-7 {
interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
- dma-names = "rx", "tx", "rxu", "txu";
+ dmas = <&audma0 0x0f>, <&audma1 0x10>;
+ dma-names = "rx", "tx";
};
ssi8: ssi-8 {
interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
- dma-names = "rx", "tx", "rxu", "txu";
+ dmas = <&audma0 0x11>, <&audma1 0x12>;
+ dma-names = "rx", "tx";
};
ssi9: ssi-9 {
interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
- dma-names = "rx", "tx", "rxu", "txu";
+ dmas = <&audma0 0x13>, <&audma1 0x14>;
+ dma-names = "rx", "tx";
};
};
};
@@ -2166,7 +2447,6 @@
du: display@feb00000 {
compatible = "renesas,du-r8a77965";
reg = <0 0xfeb00000 0 0x80000>;
- reg-names = "du";
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/dts/r8a77980-condor-u-boot.dts b/arch/arm/dts/r8a77980-condor-u-boot.dts
new file mode 100644
index 0000000..1b22c7f
--- /dev/null
+++ b/arch/arm/dts/r8a77980-condor-u-boot.dts
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot for the Condor board
+ *
+ * Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
+ */
+
+#include "r8a77980-condor.dts"
+#include "r8a77980-u-boot.dtsi"
+
+/ {
+ aliases {
+ spi0 = &rpc;
+ };
+};
+
+&rpc {
+ num-cs = <1>;
+ status = "okay";
+ spi-max-frequency = <50000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flash0: spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "s25fs512s", "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ reg = <0>;
+ status = "okay";
+ };
+};
diff --git a/arch/arm/dts/r8a77980-condor.dts b/arch/arm/dts/r8a77980-condor.dts
new file mode 100644
index 0000000..5a7012b
--- /dev/null
+++ b/arch/arm/dts/r8a77980-condor.dts
@@ -0,0 +1,292 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the Condor board
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
+ */
+
+/dts-v1/;
+#include "r8a77980.dtsi"
+
+/ {
+ model = "Renesas Condor board based on r8a77980";
+ compatible = "renesas,condor", "renesas,r8a77980";
+
+ aliases {
+ serial0 = &scif0;
+ ethernet0 = &gether;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0 0x48000000 0 0x78000000>;
+ };
+
+ d3_3v: regulator-0 {
+ compatible = "regulator-fixed";
+ regulator-name = "D3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vddq_vin01: regulator-1 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDQ_VIN01";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ d1_8v: regulator-2 {
+ compatible = "regulator-fixed";
+ regulator-name = "D1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <&adv7511_out>;
+ };
+ };
+ };
+
+ lvds-decoder {
+ compatible = "thine,thc63lvd1024";
+ vcc-supply = <&d3_3v>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ thc63lvd1024_in: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ thc63lvd1024_out: endpoint {
+ remote-endpoint = <&adv7511_in>;
+ };
+ };
+ };
+ };
+
+ x1_clk: x1-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <148500000>;
+ };
+};
+
+&canfd {
+ pinctrl-0 = <&canfd0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ channel0 {
+ status = "okay";
+ };
+};
+
+&du {
+ clocks = <&cpg CPG_MOD 724>,
+ <&x1_clk>;
+ clock-names = "du.0", "dclkin.0";
+ status = "okay";
+};
+
+&extal_clk {
+ clock-frequency = <16666666>;
+};
+
+&extalr_clk {
+ clock-frequency = <32768>;
+};
+
+&gether {
+ pinctrl-0 = <&gether_pins>;
+ pinctrl-names = "default";
+
+ phy-mode = "rgmii-id";
+ phy-handle = <&phy0>;
+ renesas,no-ether-link;
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ rxc-skew-ps = <1500>;
+ reg = <0>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&i2c0 {
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ io_expander0: gpio@20 {
+ compatible = "onnn,pca9654";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ io_expander1: gpio@21 {
+ compatible = "onnn,pca9654";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ hdmi@39 {
+ compatible = "adi,adv7511w";
+ reg = <0x39>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
+ avdd-supply = <&d1_8v>;
+ dvdd-supply = <&d1_8v>;
+ pvdd-supply = <&d1_8v>;
+ bgvdd-supply = <&d1_8v>;
+ dvdd-3v-supply = <&d3_3v>;
+
+ adi,input-depth = <8>;
+ adi,input-colorspace = "rgb";
+ adi,input-clock = "1x";
+ adi,input-style = <1>;
+ adi,input-justification = "evenly";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7511_in: endpoint {
+ remote-endpoint = <&thc63lvd1024_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ adv7511_out: endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+ };
+ };
+};
+
+&lvds0 {
+ status = "okay";
+
+ ports {
+ port@1 {
+ lvds0_out: endpoint {
+ remote-endpoint = <&thc63lvd1024_in>;
+ };
+ };
+ };
+};
+
+&mmc0 {
+ pinctrl-0 = <&mmc_pins>;
+ pinctrl-1 = <&mmc_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <&d3_3v>;
+ vqmmc-supply = <&vddq_vin01>;
+ mmc-hs200-1_8v;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&pciec {
+ status = "okay";
+};
+
+&pcie_bus_clk {
+ clock-frequency = <100000000>;
+};
+
+&pcie_phy {
+ status = "okay";
+};
+
+&pfc {
+ canfd0_pins: canfd0 {
+ groups = "canfd0_data_a";
+ function = "canfd0";
+ };
+
+ gether_pins: gether {
+ groups = "gether_mdio_a", "gether_rgmii",
+ "gether_txcrefclk", "gether_txcrefclk_mega";
+ function = "gether";
+ };
+
+ i2c0_pins: i2c0 {
+ groups = "i2c0";
+ function = "i2c0";
+ };
+
+ mmc_pins: mmc {
+ groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
+ function = "mmc";
+ power-source = <3300>;
+ };
+
+ mmc_pins_uhs: mmc_uhs {
+ groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
+ function = "mmc";
+ power-source = <1800>;
+ };
+
+ scif0_pins: scif0 {
+ groups = "scif0_data";
+ function = "scif0";
+ };
+
+ scif_clk_pins: scif_clk {
+ groups = "scif_clk_b";
+ function = "scif_clk";
+ };
+};
+
+&rwdt {
+ timeout-sec = <60>;
+ status = "okay";
+};
+
+&scif0 {
+ pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&scif_clk {
+ clock-frequency = <14745600>;
+};
diff --git a/arch/arm/dts/r8a77980-u-boot.dtsi b/arch/arm/dts/r8a77980-u-boot.dtsi
new file mode 100644
index 0000000..1050f6e
--- /dev/null
+++ b/arch/arm/dts/r8a77980-u-boot.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot on RCar R8A77980 SoC
+ *
+ * Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
+ */
+
+#include "r8a779x-u-boot.dtsi"
+
+&extalr_clk {
+ u-boot,dm-pre-reloc;
+};
+
+/ {
+ soc {
+ rpc: rpc@0xee200000 {
+ compatible = "renesas,rpc-r8a77980", "renesas,rpc";
+ reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
+ clocks = <&cpg CPG_MOD 917>;
+ bank-width = <2>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/dts/r8a77980.dtsi b/arch/arm/dts/r8a77980.dtsi
new file mode 100644
index 0000000..a901a34
--- /dev/null
+++ b/arch/arm/dts/r8a77980.dtsi
@@ -0,0 +1,1605 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the R-Car V3H (R8A77980) SoC
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
+ */
+
+#include <dt-bindings/clock/r8a77980-cpg-mssr.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/r8a77980-sysc.h>
+
+/ {
+ compatible = "renesas,r8a77980";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ };
+
+ /* External CAN clock - to be overridden by boards that provide it */
+ can_clk: can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ a53_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0>;
+ clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
+ power-domains = <&sysc R8A77980_PD_CA53_CPU0>;
+ next-level-cache = <&L2_CA53>;
+ enable-method = "psci";
+ };
+
+ a53_1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <1>;
+ clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
+ power-domains = <&sysc R8A77980_PD_CA53_CPU1>;
+ next-level-cache = <&L2_CA53>;
+ enable-method = "psci";
+ };
+
+ a53_2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <2>;
+ clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
+ power-domains = <&sysc R8A77980_PD_CA53_CPU2>;
+ next-level-cache = <&L2_CA53>;
+ enable-method = "psci";
+ };
+
+ a53_3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <3>;
+ clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
+ power-domains = <&sysc R8A77980_PD_CA53_CPU3>;
+ next-level-cache = <&L2_CA53>;
+ enable-method = "psci";
+ };
+
+ L2_CA53: cache-controller {
+ compatible = "cache";
+ power-domains = <&sysc R8A77980_PD_CA53_SCU>;
+ cache-unified;
+ cache-level = <2>;
+ };
+ };
+
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ extalr_clk: extalr {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ /* External PCIe clock - can be overridden by the board */
+ pcie_bus_clk: pcie_bus {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ pmu_a53 {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
+ /* External SCIF clock - to be overridden by boards that provide it */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ rwdt: watchdog@e6020000 {
+ compatible = "renesas,r8a77980-wdt",
+ "renesas,rcar-gen3-wdt";
+ reg = <0 0xe6020000 0 0x0c>;
+ clocks = <&cpg CPG_MOD 402>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 402>;
+ status = "disabled";
+ };
+
+ gpio0: gpio@e6050000 {
+ compatible = "renesas,gpio-r8a77980",
+ "renesas,rcar-gen3-gpio";
+ reg = <0 0xe6050000 0 0x50>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 0 22>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 912>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 912>;
+ };
+
+ gpio1: gpio@e6051000 {
+ compatible = "renesas,gpio-r8a77980",
+ "renesas,rcar-gen3-gpio";
+ reg = <0 0xe6051000 0 0x50>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 32 28>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 911>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 911>;
+ };
+
+ gpio2: gpio@e6052000 {
+ compatible = "renesas,gpio-r8a77980",
+ "renesas,rcar-gen3-gpio";
+ reg = <0 0xe6052000 0 0x50>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 64 30>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 910>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 910>;
+ };
+
+ gpio3: gpio@e6053000 {
+ compatible = "renesas,gpio-r8a77980",
+ "renesas,rcar-gen3-gpio";
+ reg = <0 0xe6053000 0 0x50>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 96 17>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 909>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 909>;
+ };
+
+ gpio4: gpio@e6054000 {
+ compatible = "renesas,gpio-r8a77980",
+ "renesas,rcar-gen3-gpio";
+ reg = <0 0xe6054000 0 0x50>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 128 25>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 908>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 908>;
+ };
+
+ gpio5: gpio@e6055000 {
+ compatible = "renesas,gpio-r8a77980",
+ "renesas,rcar-gen3-gpio";
+ reg = <0 0xe6055000 0 0x50>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 160 15>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 907>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 907>;
+ };
+
+ pfc: pin-controller@e6060000 {
+ compatible = "renesas,pfc-r8a77980";
+ reg = <0 0xe6060000 0 0x50c>;
+ };
+
+ cmt0: timer@e60f0000 {
+ compatible = "renesas,r8a77980-cmt0",
+ "renesas,rcar-gen3-cmt0";
+ reg = <0 0xe60f0000 0 0x1004>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 303>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 303>;
+ status = "disabled";
+ };
+
+ cmt1: timer@e6130000 {
+ compatible = "renesas,r8a77980-cmt1",
+ "renesas,rcar-gen3-cmt1";
+ reg = <0 0xe6130000 0 0x1004>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 302>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 302>;
+ status = "disabled";
+ };
+
+ cmt2: timer@e6140000 {
+ compatible = "renesas,r8a77980-cmt1",
+ "renesas,rcar-gen3-cmt1";
+ reg = <0 0xe6140000 0 0x1004>;
+ interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 301>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 301>;
+ status = "disabled";
+ };
+
+ cmt3: timer@e6148000 {
+ compatible = "renesas,r8a77980-cmt1",
+ "renesas,rcar-gen3-cmt1";
+ reg = <0 0xe6148000 0 0x1004>;
+ interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 300>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 300>;
+ status = "disabled";
+ };
+
+ cpg: clock-controller@e6150000 {
+ compatible = "renesas,r8a77980-cpg-mssr";
+ reg = <0 0xe6150000 0 0x1000>;
+ clocks = <&extal_clk>, <&extalr_clk>;
+ clock-names = "extal", "extalr";
+ #clock-cells = <2>;
+ #power-domain-cells = <0>;
+ #reset-cells = <1>;
+ };
+
+ rst: reset-controller@e6160000 {
+ compatible = "renesas,r8a77980-rst";
+ reg = <0 0xe6160000 0 0x200>;
+ };
+
+ sysc: system-controller@e6180000 {
+ compatible = "renesas,r8a77980-sysc";
+ reg = <0 0xe6180000 0 0x440>;
+ #power-domain-cells = <1>;
+ };
+
+ tsc: thermal@e6198000 {
+ compatible = "renesas,r8a77980-thermal";
+ reg = <0 0xe6198000 0 0x100>,
+ <0 0xe61a0000 0 0x100>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 522>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 522>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ intc_ex: interrupt-controller@e61c0000 {
+ compatible = "renesas,intc-ex-r8a77980", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 407>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 407>;
+ };
+
+ tmu0: timer@e61e0000 {
+ compatible = "renesas,tmu-r8a77980", "renesas,tmu";
+ reg = <0 0xe61e0000 0 0x30>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 125>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 125>;
+ status = "disabled";
+ };
+
+ tmu1: timer@e6fc0000 {
+ compatible = "renesas,tmu-r8a77980", "renesas,tmu";
+ reg = <0 0xe6fc0000 0 0x30>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 124>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 124>;
+ status = "disabled";
+ };
+
+ tmu2: timer@e6fd0000 {
+ compatible = "renesas,tmu-r8a77980", "renesas,tmu";
+ reg = <0 0xe6fd0000 0 0x30>;
+ interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 123>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 123>;
+ status = "disabled";
+ };
+
+ tmu3: timer@e6fe0000 {
+ compatible = "renesas,tmu-r8a77980", "renesas,tmu";
+ reg = <0 0xe6fe0000 0 0x30>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 122>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 122>;
+ status = "disabled";
+ };
+
+ tmu4: timer@ffc00000 {
+ compatible = "renesas,tmu-r8a77980", "renesas,tmu";
+ reg = <0 0xffc00000 0 0x30>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 121>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 121>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@e6500000 {
+ compatible = "renesas,i2c-r8a77980",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe6500000 0 0x40>;
+ interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 931>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 931>;
+ dmas = <&dmac1 0x91>, <&dmac1 0x90>,
+ <&dmac2 0x91>, <&dmac2 0x90>;
+ dma-names = "tx", "rx", "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@e6508000 {
+ compatible = "renesas,i2c-r8a77980",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe6508000 0 0x40>;
+ interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 930>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 930>;
+ dmas = <&dmac1 0x93>, <&dmac1 0x92>,
+ <&dmac2 0x93>, <&dmac2 0x92>;
+ dma-names = "tx", "rx", "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@e6510000 {
+ compatible = "renesas,i2c-r8a77980",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe6510000 0 0x40>;
+ interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 929>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 929>;
+ dmas = <&dmac1 0x95>, <&dmac1 0x94>,
+ <&dmac2 0x95>, <&dmac2 0x94>;
+ dma-names = "tx", "rx", "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@e66d0000 {
+ compatible = "renesas,i2c-r8a77980",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe66d0000 0 0x40>;
+ interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 928>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 928>;
+ i2c-scl-internal-delay-ns = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@e66d8000 {
+ compatible = "renesas,i2c-r8a77980",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe66d8000 0 0x40>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 927>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 927>;
+ i2c-scl-internal-delay-ns = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@e66e0000 {
+ compatible = "renesas,i2c-r8a77980",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe66e0000 0 0x40>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 919>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 919>;
+ dmas = <&dmac1 0x9b>, <&dmac1 0x9a>,
+ <&dmac2 0x9b>, <&dmac2 0x9a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ hscif0: serial@e6540000 {
+ compatible = "renesas,hscif-r8a77980",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe6540000 0 0x60>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 520>,
+ <&cpg CPG_CORE R8A77980_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x31>, <&dmac1 0x30>,
+ <&dmac2 0x31>, <&dmac2 0x30>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 520>;
+ status = "disabled";
+ };
+
+ hscif1: serial@e6550000 {
+ compatible = "renesas,hscif-r8a77980",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe6550000 0 0x60>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 519>,
+ <&cpg CPG_CORE R8A77980_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x33>, <&dmac1 0x32>,
+ <&dmac2 0x33>, <&dmac2 0x32>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 519>;
+ status = "disabled";
+ };
+
+ hscif2: serial@e6560000 {
+ compatible = "renesas,hscif-r8a77980",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe6560000 0 0x60>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 518>,
+ <&cpg CPG_CORE R8A77980_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x35>, <&dmac1 0x34>,
+ <&dmac2 0x35>, <&dmac2 0x34>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 518>;
+ status = "disabled";
+ };
+
+ hscif3: serial@e66a0000 {
+ compatible = "renesas,hscif-r8a77980",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe66a0000 0 0x60>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 517>,
+ <&cpg CPG_CORE R8A77980_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x37>, <&dmac1 0x36>,
+ <&dmac2 0x37>, <&dmac2 0x36>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 517>;
+ status = "disabled";
+ };
+
+ pcie_phy: pcie-phy@e65d0000 {
+ compatible = "renesas,r8a77980-pcie-phy";
+ reg = <0 0xe65d0000 0 0x8000>;
+ #phy-cells = <0>;
+ clocks = <&cpg CPG_MOD 319>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 319>;
+ status = "disabled";
+ };
+
+ canfd: can@e66c0000 {
+ compatible = "renesas,r8a77980-canfd",
+ "renesas,rcar-gen3-canfd";
+ reg = <0 0xe66c0000 0 0x8000>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 914>,
+ <&cpg CPG_CORE R8A77980_CLK_CANFD>,
+ <&can_clk>;
+ clock-names = "fck", "canfd", "can_clk";
+ assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>;
+ assigned-clock-rates = <40000000>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 914>;
+ status = "disabled";
+
+ channel0 {
+ status = "disabled";
+ };
+
+ channel1 {
+ status = "disabled";
+ };
+ };
+
+ avb: ethernet@e6800000 {
+ compatible = "renesas,etheravb-r8a77980",
+ "renesas,etheravb-rcar-gen3";
+ reg = <0 0xe6800000 0 0x800>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15",
+ "ch16", "ch17", "ch18", "ch19",
+ "ch20", "ch21", "ch22", "ch23",
+ "ch24";
+ clocks = <&cpg CPG_MOD 812>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 812>;
+ phy-mode = "rgmii";
+ iommus = <&ipmmu_ds1 33>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ pwm0: pwm@e6e30000 {
+ compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
+ reg = <0 0xe6e30000 0 0x10>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ status = "disabled";
+ };
+
+ pwm1: pwm@e6e31000 {
+ compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
+ reg = <0 0xe6e31000 0 0x10>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ status = "disabled";
+ };
+
+ pwm2: pwm@e6e32000 {
+ compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
+ reg = <0 0xe6e32000 0 0x10>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ status = "disabled";
+ };
+
+ pwm3: pwm@e6e33000 {
+ compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
+ reg = <0 0xe6e33000 0 0x10>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ status = "disabled";
+ };
+
+ pwm4: pwm@e6e34000 {
+ compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
+ reg = <0 0xe6e34000 0 0x10>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ status = "disabled";
+ };
+
+ scif0: serial@e6e60000 {
+ compatible = "renesas,scif-r8a77980",
+ "renesas,rcar-gen3-scif",
+ "renesas,scif";
+ reg = <0 0xe6e60000 0 0x40>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 207>,
+ <&cpg CPG_CORE R8A77980_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x51>, <&dmac1 0x50>,
+ <&dmac2 0x51>, <&dmac2 0x50>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 207>;
+ status = "disabled";
+ };
+
+ scif1: serial@e6e68000 {
+ compatible = "renesas,scif-r8a77980",
+ "renesas,rcar-gen3-scif",
+ "renesas,scif";
+ reg = <0 0xe6e68000 0 0x40>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 206>,
+ <&cpg CPG_CORE R8A77980_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x53>, <&dmac1 0x52>,
+ <&dmac2 0x53>, <&dmac2 0x52>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 206>;
+ status = "disabled";
+ };
+
+ scif3: serial@e6c50000 {
+ compatible = "renesas,scif-r8a77980",
+ "renesas,rcar-gen3-scif",
+ "renesas,scif";
+ reg = <0 0xe6c50000 0 0x40>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 204>,
+ <&cpg CPG_CORE R8A77980_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x57>, <&dmac1 0x56>,
+ <&dmac2 0x57>, <&dmac2 0x56>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 204>;
+ status = "disabled";
+ };
+
+ scif4: serial@e6c40000 {
+ compatible = "renesas,scif-r8a77980",
+ "renesas,rcar-gen3-scif",
+ "renesas,scif";
+ reg = <0 0xe6c40000 0 0x40>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 203>,
+ <&cpg CPG_CORE R8A77980_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x59>, <&dmac1 0x58>,
+ <&dmac2 0x59>, <&dmac2 0x58>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 203>;
+ status = "disabled";
+ };
+
+ tpu: pwm@e6e80000 {
+ compatible = "renesas,tpu-r8a77980", "renesas,tpu";
+ reg = <0 0xe6e80000 0 0x148>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 304>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 304>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ msiof0: spi@e6e90000 {
+ compatible = "renesas,msiof-r8a77980",
+ "renesas,rcar-gen3-msiof";
+ reg = <0 0xe6e90000 0 0x64>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 211>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 211>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof1: spi@e6ea0000 {
+ compatible = "renesas,msiof-r8a77980",
+ "renesas,rcar-gen3-msiof";
+ reg = <0 0xe6ea0000 0 0x0064>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 210>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 210>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof2: spi@e6c00000 {
+ compatible = "renesas,msiof-r8a77980",
+ "renesas,rcar-gen3-msiof";
+ reg = <0 0xe6c00000 0 0x0064>;
+ interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 209>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 209>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof3: spi@e6c10000 {
+ compatible = "renesas,msiof-r8a77980",
+ "renesas,rcar-gen3-msiof";
+ reg = <0 0xe6c10000 0 0x0064>;
+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 208>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 208>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ vin0: video@e6ef0000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef0000 0 0x1000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 811>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 811>;
+ renesas,id = <0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin0csi40: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&csi40vin0>;
+ };
+ };
+ };
+ };
+
+ vin1: video@e6ef1000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef1000 0 0x1000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 810>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ status = "disabled";
+ renesas,id = <1>;
+ resets = <&cpg 810>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin1csi40: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&csi40vin1>;
+ };
+ };
+ };
+ };
+
+ vin2: video@e6ef2000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef2000 0 0x1000>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 809>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 809>;
+ renesas,id = <2>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin2csi40: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&csi40vin2>;
+ };
+ };
+ };
+ };
+
+ vin3: video@e6ef3000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef3000 0 0x1000>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 808>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 808>;
+ renesas,id = <3>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin3csi40: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&csi40vin3>;
+ };
+ };
+ };
+ };
+
+ vin4: video@e6ef4000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef4000 0 0x1000>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 807>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 807>;
+ renesas,id = <4>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin4csi41: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&csi41vin4>;
+ };
+ };
+ };
+ };
+
+ vin5: video@e6ef5000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef5000 0 0x1000>;
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 806>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 806>;
+ renesas,id = <5>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin5csi41: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&csi41vin5>;
+ };
+ };
+ };
+ };
+
+ vin6: video@e6ef6000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef6000 0 0x1000>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 805>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 805>;
+ renesas,id = <6>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin6csi41: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&csi41vin6>;
+ };
+ };
+ };
+ };
+
+ vin7: video@e6ef7000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef7000 0 0x1000>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 804>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 804>;
+ renesas,id = <7>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin7csi41: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&csi41vin7>;
+ };
+ };
+ };
+ };
+
+ vin8: video@e6ef8000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef8000 0 0x1000>;
+ interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 628>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 628>;
+ renesas,id = <8>;
+ status = "disabled";
+ };
+
+ vin9: video@e6ef9000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef9000 0 0x1000>;
+ interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 627>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 627>;
+ renesas,id = <9>;
+ status = "disabled";
+ };
+
+ vin10: video@e6efa000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efa000 0 0x1000>;
+ interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 625>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 625>;
+ renesas,id = <10>;
+ status = "disabled";
+ };
+
+ vin11: video@e6efb000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efb000 0 0x1000>;
+ interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 618>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 618>;
+ renesas,id = <11>;
+ status = "disabled";
+ };
+
+ vin12: video@e6efc000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efc000 0 0x1000>;
+ interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 612>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 612>;
+ renesas,id = <12>;
+ status = "disabled";
+ };
+
+ vin13: video@e6efd000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efd000 0 0x1000>;
+ interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 608>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 608>;
+ renesas,id = <13>;
+ status = "disabled";
+ };
+
+ vin14: video@e6efe000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efe000 0 0x1000>;
+ interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 605>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 605>;
+ renesas,id = <14>;
+ status = "disabled";
+ };
+
+ vin15: video@e6eff000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6eff000 0 0x1000>;
+ interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 604>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 604>;
+ renesas,id = <15>;
+ status = "disabled";
+ };
+
+ dmac1: dma-controller@e7300000 {
+ compatible = "renesas,dmac-r8a77980",
+ "renesas,rcar-dmac";
+ reg = <0 0xe7300000 0 0x10000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 218>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 218>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
+ <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
+ <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
+ <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
+ <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
+ <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
+ <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
+ <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
+ };
+
+ dmac2: dma-controller@e7310000 {
+ compatible = "renesas,dmac-r8a77980",
+ "renesas,rcar-dmac";
+ reg = <0 0xe7310000 0 0x10000>;
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 217>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 217>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
+ <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
+ <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
+ <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
+ <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
+ <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
+ <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
+ <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
+ };
+
+ gether: ethernet@e7400000 {
+ compatible = "renesas,gether-r8a77980";
+ reg = <0 0xe7400000 0 0x1000>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 813>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 813>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ ipmmu_ds1: mmu@e7740000 {
+ compatible = "renesas,ipmmu-r8a77980";
+ reg = <0 0xe7740000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 0>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_ir: mmu@ff8b0000 {
+ compatible = "renesas,ipmmu-r8a77980";
+ reg = <0 0xff8b0000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 3>;
+ power-domains = <&sysc R8A77980_PD_A3IR>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_mm: mmu@e67b0000 {
+ compatible = "renesas,ipmmu-r8a77980";
+ reg = <0 0xe67b0000 0 0x1000>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_rt: mmu@ffc80000 {
+ compatible = "renesas,ipmmu-r8a77980";
+ reg = <0 0xffc80000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 10>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_vc0: mmu@fe6b0000 {
+ compatible = "renesas,ipmmu-r8a77980";
+ reg = <0 0xfe6b0000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 12>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_vi0: mmu@febd0000 {
+ compatible = "renesas,ipmmu-r8a77980";
+ reg = <0 0xfebd0000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 14>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_vip0: mmu@e7b00000 {
+ compatible = "renesas,ipmmu-r8a77980";
+ reg = <0 0xe7b00000 0 0x1000>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_vip1: mmu@e7960000 {
+ compatible = "renesas,ipmmu-r8a77980";
+ reg = <0 0xe7960000 0 0x1000>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ mmc0: mmc@ee140000 {
+ compatible = "renesas,sdhi-r8a77980",
+ "renesas,rcar-gen3-sdhi";
+ reg = <0 0xee140000 0 0x2000>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 314>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 314>;
+ max-frequency = <200000000>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@f1010000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x0 0xf1010000 0 0x1000>,
+ <0x0 0xf1020000 0 0x20000>,
+ <0x0 0xf1040000 0 0x20000>,
+ <0x0 0xf1060000 0 0x20000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&cpg CPG_MOD 408>;
+ clock-names = "clk";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 408>;
+ };
+
+ pciec: pcie@fe000000 {
+ compatible = "renesas,pcie-r8a77980",
+ "renesas,pcie-rcar-gen3";
+ reg = <0 0xfe000000 0 0x80000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <
+ 0x01000000 0 0x00000000 0 0xfe100000 0 0x0100000
+ 0x02000000 0 0xfe200000 0 0xfe200000 0 0x0200000
+ 0x02000000 0 0x30000000 0 0x30000000 0 0x8000000
+ 0x42000000 0 0x38000000 0 0x38000000 0 0x8000000
+ >;
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000
+ 0 0x80000000>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 148
+ IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
+ clock-names = "pcie", "pcie_bus";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 319>;
+ phys = <&pcie_phy>;
+ phy-names = "pcie";
+ status = "disabled";
+ };
+
+ vspd0: vsp@fea20000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfea20000 0 0x5000>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 623>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 623>;
+ renesas,fcp = <&fcpvd0>;
+ };
+
+ fcpvd0: fcp@fea27000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfea27000 0 0x200>;
+ clocks = <&cpg CPG_MOD 603>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 603>;
+ };
+
+ csi40: csi2@feaa0000 {
+ compatible = "renesas,r8a77980-csi2";
+ reg = <0 0xfeaa0000 0 0x10000>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 716>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 716>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ csi40vin0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vin0csi40>;
+ };
+ csi40vin1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vin1csi40>;
+ };
+ csi40vin2: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&vin2csi40>;
+ };
+ csi40vin3: endpoint@3 {
+ reg = <3>;
+ remote-endpoint = <&vin3csi40>;
+ };
+ };
+ };
+ };
+
+ csi41: csi2@feab0000 {
+ compatible = "renesas,r8a77980-csi2";
+ reg = <0 0xfeab0000 0 0x10000>;
+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 715>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 715>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ csi41vin4: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vin4csi41>;
+ };
+ csi41vin5: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vin5csi41>;
+ };
+ csi41vin6: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&vin6csi41>;
+ };
+ csi41vin7: endpoint@3 {
+ reg = <3>;
+ remote-endpoint = <&vin7csi41>;
+ };
+ };
+ };
+ };
+
+ du: display@feb00000 {
+ compatible = "renesas,du-r8a77980",
+ "renesas,du-r8a77970";
+ reg = <0 0xfeb00000 0 0x80000>;
+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 724>;
+ clock-names = "du.0";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 724>;
+ vsps = <&vspd0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ du_out_rgb: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ du_out_lvds0: endpoint {
+ remote-endpoint = <&lvds0_in>;
+ };
+ };
+ };
+ };
+
+ lvds0: lvds-encoder@feb90000 {
+ compatible = "renesas,r8a77980-lvds";
+ reg = <0 0xfeb90000 0 0x14>;
+ clocks = <&cpg CPG_MOD 727>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 727>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ lvds0_in: endpoint {
+ remote-endpoint =
+ <&du_out_lvds0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ lvds0_out: endpoint {
+ };
+ };
+ };
+ };
+
+ prr: chipid@fff00044 {
+ compatible = "renesas,prr";
+ reg = <0 0xfff00044 0 4>;
+ };
+ };
+
+ thermal-zones {
+ thermal-sensor-1 {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsc 0>;
+
+ trips {
+ sensor1-passive {
+ temperature = <95000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ sensor1-critical {
+ temperature = <120000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ thermal-sensor-2 {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsc 1>;
+
+ trips {
+ sensor2-passive {
+ temperature = <95000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ sensor2-critical {
+ temperature = <120000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
diff --git a/arch/arm/dts/r8a77990-ebisu-u-boot.dts b/arch/arm/dts/r8a77990-ebisu-u-boot.dts
index 1ce22e5..0ea0cc9 100644
--- a/arch/arm/dts/r8a77990-ebisu-u-boot.dts
+++ b/arch/arm/dts/r8a77990-ebisu-u-boot.dts
@@ -29,3 +29,11 @@
sd-uhs-sdr25;
max-frequency = <208000000>;
};
+
+&vcc_sdhi0 {
+ u-boot,off-on-delay-us = <20000>;
+};
+
+&vcc_sdhi1 {
+ u-boot,off-on-delay-us = <20000>;
+};
diff --git a/arch/arm/dts/r8a77990-ebisu.dts b/arch/arm/dts/r8a77990-ebisu.dts
index 144c082..c727725 100644
--- a/arch/arm/dts/r8a77990-ebisu.dts
+++ b/arch/arm/dts/r8a77990-ebisu.dts
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the ebisu board
*
@@ -19,7 +19,7 @@
};
chosen {
- bootargs = "ignore_loglevel";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = "serial0:115200n8";
};
@@ -337,6 +337,15 @@
&i2c0 {
status = "okay";
+ io_expander: gpio@20 {
+ compatible = "onnn,pca9654";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
+ };
+
hdmi-encoder@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
@@ -398,7 +407,7 @@
};
port@a {
- reg = <0xa>;
+ reg = <10>;
adv7482_txa: endpoint {
clock-lanes = <0>;
@@ -440,6 +449,28 @@
};
};
+&i2c_dvfs {
+ status = "okay";
+
+ clock-frequency = <400000>;
+
+ pmic: pmic@30 {
+ pinctrl-0 = <&irq0_pins>;
+ pinctrl-names = "default";
+
+ compatible = "rohm,bd9571mwv";
+ reg = <0x30>;
+ interrupt-parent = <&intc_ex>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ rohm,ddr-backup-power = <0x1>;
+ rohm,rstbmode-level;
+ };
+};
+
&lvds0 {
status = "okay";
@@ -458,6 +489,13 @@
};
&lvds1 {
+ /*
+ * Even though the LVDS1 output is not connected, the encoder must be
+ * enabled to supply a pixel clock to the DU for the DPAD output when
+ * LVDS0 is in use.
+ */
+ status = "okay";
+
clocks = <&cpg CPG_MOD 727>,
<&x13_clk>,
<&extal_clk>;
@@ -495,6 +533,11 @@
function = "du";
};
+ irq0_pins: irq0 {
+ groups = "intc_ex_irq0";
+ function = "intc_ex";
+ };
+
pwm3_pins: pwm3 {
groups = "pwm3_b";
function = "pwm3";
@@ -650,6 +693,10 @@
status = "okay";
};
+&vin5 {
+ status = "okay";
+};
+
&xhci0 {
pinctrl-0 = <&usb30_pins>;
pinctrl-names = "default";
diff --git a/arch/arm/dts/r8a77990.dtsi b/arch/arm/dts/r8a77990.dtsi
index d2ad665..56cb566 100644
--- a/arch/arm/dts/r8a77990.dtsi
+++ b/arch/arm/dts/r8a77990.dtsi
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the R-Car E3 (R8A77990) SoC
*
@@ -284,6 +284,76 @@
status = "disabled";
};
+ cmt0: timer@e60f0000 {
+ compatible = "renesas,r8a77990-cmt0",
+ "renesas,rcar-gen3-cmt0";
+ reg = <0 0xe60f0000 0 0x1004>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 303>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 303>;
+ status = "disabled";
+ };
+
+ cmt1: timer@e6130000 {
+ compatible = "renesas,r8a77990-cmt1",
+ "renesas,rcar-gen3-cmt1";
+ reg = <0 0xe6130000 0 0x1004>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 302>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 302>;
+ status = "disabled";
+ };
+
+ cmt2: timer@e6140000 {
+ compatible = "renesas,r8a77990-cmt1",
+ "renesas,rcar-gen3-cmt1";
+ reg = <0 0xe6140000 0 0x1004>;
+ interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 301>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 301>;
+ status = "disabled";
+ };
+
+ cmt3: timer@e6148000 {
+ compatible = "renesas,r8a77990-cmt1",
+ "renesas,rcar-gen3-cmt1";
+ reg = <0 0xe6148000 0 0x1004>;
+ interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 300>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 300>;
+ status = "disabled";
+ };
+
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a77990-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
@@ -1656,7 +1726,7 @@
};
csi40: csi2@feaa0000 {
- compatible = "renesas,r8a77990-csi2", "renesas,rcar-gen3-csi2";
+ compatible = "renesas,r8a77990-csi2";
reg = <0 0xfeaa0000 0 0x10000>;
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 716>;
diff --git a/arch/arm/dts/r8a77995-draak.dts b/arch/arm/dts/r8a77995-draak.dts
index db2bed1..a7dc11e 100644
--- a/arch/arm/dts/r8a77995-draak.dts
+++ b/arch/arm/dts/r8a77995-draak.dts
@@ -20,7 +20,7 @@
};
chosen {
- bootargs = "ignore_loglevel";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = "serial0:115200n8";
};
@@ -168,7 +168,6 @@
pinctrl-names = "default";
renesas,no-ether-link;
phy-handle = <&phy0>;
- phy-mode = "rgmii-txid";
status = "okay";
phy0: ethernet-phy@0 {
@@ -179,6 +178,18 @@
};
};
+&can0 {
+ pinctrl-0 = <&can0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&can1 {
+ pinctrl-0 = <&can1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
&du {
pinctrl-0 = <&du_pins>;
pinctrl-names = "default";
@@ -356,6 +367,13 @@
};
&lvds1 {
+ /*
+ * Even though the LVDS1 output is not connected, the encoder must be
+ * enabled to supply a pixel clock to the DU for the DPAD output when
+ * LVDS0 is in use.
+ */
+ status = "okay";
+
clocks = <&cpg CPG_MOD 727>,
<&x12_clk>,
<&extal_clk>;
@@ -375,6 +393,16 @@
};
};
+ can0_pins: can0 {
+ groups = "can0_data_a";
+ function = "can0";
+ };
+
+ can1_pins: can1 {
+ groups = "can1_data_a";
+ function = "can1";
+ };
+
du_pins: du {
groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
function = "du";
diff --git a/arch/arm/dts/rk3288-evb-u-boot.dtsi b/arch/arm/dts/rk3288-evb-u-boot.dtsi
new file mode 100644
index 0000000..8ac7840
--- /dev/null
+++ b/arch/arm/dts/rk3288-evb-u-boot.dtsi
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Rockchip Electronics Co., Ltd
+ */
+
+#include "rk3288-u-boot.dtsi"
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
+
+&uart2 {
+ u-boot,dm-pre-reloc;
+};
+
+&sdmmc {
+ u-boot,dm-pre-reloc;
+};
+
+&emmc {
+ u-boot,dm-pre-reloc;
+};
+
+&gpio3 {
+ u-boot,dm-pre-reloc;
+};
+
+&gpio8 {
+ u-boot,dm-pre-reloc;
+};
+
+&sdmmc_bus4 {
+ u-boot,dm-spl;
+};
+
+&sdmmc_clk {
+ u-boot,dm-spl;
+};
+
+&sdmmc_cmd {
+ u-boot,dm-spl;
+};
+
+&sdmmc_pwr {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/rk3288-evb.dts b/arch/arm/dts/rk3288-evb.dts
index 575de44..eac91a8 100644
--- a/arch/arm/dts/rk3288-evb.dts
+++ b/arch/arm/dts/rk3288-evb.dts
@@ -26,31 +26,6 @@
rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>;
};
-&pinctrl {
- u-boot,dm-pre-reloc;
-};
-
&pwm1 {
status = "okay";
};
-
-&uart2 {
- u-boot,dm-pre-reloc;
- reg-shift = <2>;
-};
-
-&sdmmc {
- u-boot,dm-pre-reloc;
-};
-
-&emmc {
- u-boot,dm-pre-reloc;
-};
-
-&gpio3 {
- u-boot,dm-pre-reloc;
-};
-
-&gpio8 {
- u-boot,dm-pre-reloc;
-};
diff --git a/arch/arm/dts/rk3288-fennec.dts b/arch/arm/dts/rk3288-fennec.dts
deleted file mode 100644
index b569307..0000000
--- a/arch/arm/dts/rk3288-fennec.dts
+++ /dev/null
@@ -1,56 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- */
-
-/dts-v1/;
-#include "rk3288-fennec.dtsi"
-
-/ {
- model = "Rockchip RK3288 Fennec Board";
- compatible = "rockchip,rk3288-fennec", "rockchip,rk3288";
-
- chosen {
- stdout-path = &uart2;
- };
-};
-
-&dmc {
- rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
- 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
- 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
- 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
- 0x8 0x1f4>;
- rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
- 0x0 0xc3 0x6 0x2>;
- rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>;
-};
-
-&pinctrl {
- u-boot,dm-pre-reloc;
-};
-
-&pwm1 {
- status = "okay";
-};
-
-&uart2 {
- u-boot,dm-pre-reloc;
- reg-shift = <2>;
-};
-
-&sdmmc {
- u-boot,dm-pre-reloc;
-};
-
-&emmc {
- u-boot,dm-pre-reloc;
-};
-
-&gpio3 {
- u-boot,dm-pre-reloc;
-};
-
-&gpio8 {
- u-boot,dm-pre-reloc;
-};
diff --git a/arch/arm/dts/rk3288-fennec.dtsi b/arch/arm/dts/rk3288-fennec.dtsi
deleted file mode 100644
index f61252c..0000000
--- a/arch/arm/dts/rk3288-fennec.dtsi
+++ /dev/null
@@ -1,421 +0,0 @@
-/*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include "rk3288.dtsi"
-
-/ {
- memory {
- reg = <0x0 0x80000000>;
- device_type = "memory";
- };
-
- ext_gmac: external-gmac-clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <125000000>;
- clock-output-names = "ext_gmac";
- };
-
- vcc_sys: vsys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc_sys";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- };
-};
-
-&cpu0 {
- cpu0-supply = <&vdd_cpu>;
-};
-
-&emmc {
- bus-width = <8>;
- cap-mmc-highspeed;
- disable-wp;
- non-removable;
- num-slots = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
- status = "okay";
-};
-
-&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- card-detect-delay = <200>;
- disable-wp;
- num-slots = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
- status = "okay";
- vmmc-supply = <&vcc_sd>;
- vqmmc-supply = <&vccio_sd>;
-};
-
-&gmac {
- assigned-clocks = <&cru SCLK_MAC>;
- assigned-clock-parents = <&ext_gmac>;
- clock_in_out = "input";
- pinctrl-names = "default";
- pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>;
- phy-supply = <&vcc_lan>;
- phy-mode = "rgmii";
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 1000000>;
- snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>;
- tx_delay = <0x30>;
- rx_delay = <0x10>;
- status = "okay";
-};
-
-&gpu {
- mali-supply = <&vdd_gpu>;
- status = "okay";
-};
-
-&hdmi {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
- clock-frequency = <400000>;
-
- rk808: pmic@1b {
- compatible = "rockchip,rk808";
- reg = <0x1b>;
- interrupt-parent = <&gpio0>;
- interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
- #clock-cells = <1>;
- clock-output-names = "xin32k", "rk808-clkout2";
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int &global_pwroff>;
- rockchip,system-power-controller;
- wakeup-source;
-
- vcc1-supply = <&vcc_sys>;
- vcc2-supply = <&vcc_sys>;
- vcc3-supply = <&vcc_sys>;
- vcc4-supply = <&vcc_sys>;
- vcc6-supply = <&vcc_sys>;
- vcc7-supply = <&vcc_sys>;
- vcc8-supply = <&vcc_io>;
- vcc9-supply = <&vcc_io>;
- vcc10-supply = <&vcc_io>;
- vcc11-supply = <&vcc_io>;
- vcc12-supply = <&vcc_io>;
- vddio-supply = <&vcc_io>;
-
- regulators {
- vdd_cpu: DCDC_REG1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
- regulator-name = "vdd_arm";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_gpu: DCDC_REG2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1250000>;
- regulator-name = "vdd_gpu";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1000000>;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-name = "vcc_ddr";
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_io: DCDC_REG4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc_io";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vccio_pmu: LDO_REG1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vccio_pmu";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcca_33: LDO_REG2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcca_33";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_10: LDO_REG3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-name = "vdd_10";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1000000>;
- };
- };
-
- vcc_wl: LDO_REG4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc_wl";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vccio_sd: LDO_REG5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vccio_sd";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vdd10_lcd: LDO_REG6 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-name = "vdd10_lcd";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1000000>;
- };
- };
-
- vcc_18: LDO_REG7 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc_18";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc18_lcd: LDO_REG8 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vcc18_lcd";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc_sd: SWITCH_REG1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-name = "vcc_sd";
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_lan: SWITCH_REG2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-name = "vcc_lan";
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
- };
- };
-};
-
-&pinctrl {
- pcfg_output_high: pcfg-output-high {
- output-high;
- };
-
- pcfg_output_low: pcfg-output-low {
- output-low;
- };
-
- pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
- drive-strength = <8>;
- };
-
- pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
- bias-pull-up;
- drive-strength = <8>;
- };
-
- gmac {
- phy_int: phy-int {
- rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>;
- };
-
- phy_pmeb: phy-pmeb {
- rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>;
- };
-
- phy_rst: phy-rst {
- rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>;
- };
- };
-
- pmic {
- pmic_int: pmic-int {
- rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- sdmmc {
- sdmmc_bus4: sdmmc-bus4 {
- rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
- <6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
- <6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
- <6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
- };
-
- sdmmc_clk: sdmmc-clk {
- rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
- };
-
- sdmmc_cmd: sdmmc-cmd {
- rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
- };
-
- sdmmc_pwr: sdmmc-pwr {
- rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- usbphy {
- host_drv: host-drv {
- rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&uart2 {
- status = "okay";
-};
-
-&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&host_drv>;
- vbus_drv-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host1 {
- status = "okay";
-};
-
-&usb_otg {
- status = "okay";
-};
-
-&usb_hsic {
- status = "okay";
-};
-
-&vopb {
- status = "okay";
-};
-
-&vopb_mmu {
- status = "okay";
-};
-
-&vopl {
- status = "okay";
-};
-
-&vopl_mmu {
- status = "okay";
-};
-
-&vpu {
- status = "okay";
-};
diff --git a/arch/arm/dts/rk3288-firefly-u-boot.dtsi b/arch/arm/dts/rk3288-firefly-u-boot.dtsi
new file mode 100644
index 0000000..8b9c383
--- /dev/null
+++ b/arch/arm/dts/rk3288-firefly-u-boot.dtsi
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Rockchip Electronics Co., Ltd
+ */
+
+#include "rk3288-u-boot.dtsi"
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
+
+&uart2 {
+ u-boot,dm-pre-reloc;
+};
+
+&sdmmc {
+ u-boot,dm-pre-reloc;
+};
+
+&emmc {
+ u-boot,dm-pre-reloc;
+};
+
+&gpio3 {
+ u-boot,dm-pre-reloc;
+};
+
+&gpio8 {
+ u-boot,dm-pre-reloc;
+};
+
+&pcfg_pull_up_drv_12ma {
+ u-boot,dm-spl;
+};
+
+&sdmmc_bus4 {
+ u-boot,dm-spl;
+};
+
+&sdmmc_clk {
+ u-boot,dm-spl;
+};
+
+&sdmmc_cmd {
+ u-boot,dm-spl;
+};
+
+&sdmmc_pwr {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/rk3288-firefly.dts b/arch/arm/dts/rk3288-firefly.dts
index 2e075406..1cff04e 100644
--- a/arch/arm/dts/rk3288-firefly.dts
+++ b/arch/arm/dts/rk3288-firefly.dts
@@ -37,7 +37,6 @@
};
&pinctrl {
- u-boot,dm-pre-reloc;
act8846 {
pmic_vsel: pmic-vsel {
rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_output_low>;
@@ -59,25 +58,3 @@
&pwm1 {
status = "okay";
};
-
-&uart2 {
- u-boot,dm-pre-reloc;
- reg-shift = <2>;
-};
-
-&usb_host1 {
- vbus-supply = <&vcc_host_5v>;
- status = "okay";
-};
-
-&sdmmc {
- u-boot,dm-pre-reloc;
-};
-
-&gpio3 {
- u-boot,dm-pre-reloc;
-};
-
-&gpio8 {
- u-boot,dm-pre-reloc;
-};
diff --git a/arch/arm/dts/rk3288-firefly.dtsi b/arch/arm/dts/rk3288-firefly.dtsi
index 2239ab9..b7f279f 100644
--- a/arch/arm/dts/rk3288-firefly.dtsi
+++ b/arch/arm/dts/rk3288-firefly.dtsi
@@ -320,6 +320,11 @@
output-low;
};
+ pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma {
+ bias-pull-up;
+ drive-strength = <12>;
+ };
+
act8846 {
pwr_hold: pwr-hold {
rockchip,pins = <0 1 RK_FUNC_GPIO &pcfg_output_high>;
@@ -363,8 +368,27 @@
};
sdmmc {
+ /*
+ * Default drive strength isn't enough to achieve even
+ * high-speed mode on firefly board so bump up to 12ma.
+ */
+ sdmmc_bus4: sdmmc-bus4 {
+ rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_12ma>,
+ <6 RK_PC1 1 &pcfg_pull_up_drv_12ma>,
+ <6 RK_PC2 1 &pcfg_pull_up_drv_12ma>,
+ <6 RK_PC3 1 &pcfg_pull_up_drv_12ma>;
+ };
+
+ sdmmc_clk: sdmmc-clk {
+ rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_12ma>;
+ };
+
+ sdmmc_cmd: sdmmc-cmd {
+ rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_12ma>;
+ };
+
sdmmc_pwr: sdmmc-pwr {
- rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
diff --git a/arch/arm/dts/rk3288-miqi-u-boot.dtsi b/arch/arm/dts/rk3288-miqi-u-boot.dtsi
new file mode 100644
index 0000000..4f63fc9
--- /dev/null
+++ b/arch/arm/dts/rk3288-miqi-u-boot.dtsi
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Rockchip Electronics Co., Ltd
+ */
+
+#include "rk3288-u-boot.dtsi"
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
+
+&uart2 {
+ u-boot,dm-pre-reloc;
+};
+
+&sdmmc {
+ u-boot,dm-pre-reloc;
+};
+
+&emmc {
+ u-boot,dm-pre-reloc;
+};
+
+&sdmmc_bus4 {
+ u-boot,dm-spl;
+};
+
+&sdmmc_clk {
+ u-boot,dm-spl;
+};
+
+&sdmmc_cmd {
+ u-boot,dm-spl;
+};
+
+&sdmmc_pwr {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/rk3288-miqi.dts b/arch/arm/dts/rk3288-miqi.dts
index 29e60dd..e47170c 100644
--- a/arch/arm/dts/rk3288-miqi.dts
+++ b/arch/arm/dts/rk3288-miqi.dts
@@ -25,21 +25,3 @@
0xa60 0x40 0x10 0x0>;
rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
};
-
-
-&pinctrl {
- u-boot,dm-pre-reloc;
-};
-
-&uart2 {
- u-boot,dm-pre-reloc;
- reg-shift = <2>;
-};
-
-&sdmmc {
- u-boot,dm-pre-reloc;
-};
-
-&emmc {
- u-boot,dm-pre-reloc;
-};
diff --git a/arch/arm/dts/rk3288-phycore-rdk.dts b/arch/arm/dts/rk3288-phycore-rdk.dts
index f2bb7b5..cc39210 100644
--- a/arch/arm/dts/rk3288-phycore-rdk.dts
+++ b/arch/arm/dts/rk3288-phycore-rdk.dts
@@ -55,11 +55,6 @@
stdout-path = &uart2;
};
- config {
- u-boot,dm-pre-reloc;
- u-boot,boot0 = &emmc;
- };
-
user_buttons: user-buttons {
compatible = "gpio-keys";
pinctrl-names = "default";
diff --git a/arch/arm/dts/rk3288-popmetal-u-boot.dtsi b/arch/arm/dts/rk3288-popmetal-u-boot.dtsi
new file mode 100644
index 0000000..8ac7840
--- /dev/null
+++ b/arch/arm/dts/rk3288-popmetal-u-boot.dtsi
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Rockchip Electronics Co., Ltd
+ */
+
+#include "rk3288-u-boot.dtsi"
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
+
+&uart2 {
+ u-boot,dm-pre-reloc;
+};
+
+&sdmmc {
+ u-boot,dm-pre-reloc;
+};
+
+&emmc {
+ u-boot,dm-pre-reloc;
+};
+
+&gpio3 {
+ u-boot,dm-pre-reloc;
+};
+
+&gpio8 {
+ u-boot,dm-pre-reloc;
+};
+
+&sdmmc_bus4 {
+ u-boot,dm-spl;
+};
+
+&sdmmc_clk {
+ u-boot,dm-spl;
+};
+
+&sdmmc_cmd {
+ u-boot,dm-spl;
+};
+
+&sdmmc_pwr {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/rk3288-popmetal.dts b/arch/arm/dts/rk3288-popmetal.dts
index d1e1cd5..5c6d06f 100644
--- a/arch/arm/dts/rk3288-popmetal.dts
+++ b/arch/arm/dts/rk3288-popmetal.dts
@@ -26,32 +26,6 @@
rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
};
-
-&pinctrl {
- u-boot,dm-pre-reloc;
-};
-
&pwm1 {
status = "okay";
};
-
-&uart2 {
- u-boot,dm-pre-reloc;
- reg-shift = <2>;
-};
-
-&sdmmc {
- u-boot,dm-pre-reloc;
-};
-
-&emmc {
- u-boot,dm-pre-reloc;
-};
-
-&gpio3 {
- u-boot,dm-pre-reloc;
-};
-
-&gpio8 {
- u-boot,dm-pre-reloc;
-};
diff --git a/arch/arm/dts/rk3288-tinker-u-boot.dtsi b/arch/arm/dts/rk3288-tinker-u-boot.dtsi
index 2efb309..f7f9d6d 100644
--- a/arch/arm/dts/rk3288-tinker-u-boot.dtsi
+++ b/arch/arm/dts/rk3288-tinker-u-boot.dtsi
@@ -13,20 +13,20 @@
u-boot,dm-pre-reloc;
};
+&uart2_xfer {
+ u-boot,dm-pre-reloc;
+};
+
&sdmmc {
- u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
};
-&emmc {
- u-boot,dm-pre-reloc;
+&gpio7 {
+ u-boot,dm-spl;
};
-&gpio3 {
- u-boot,dm-pre-reloc;
-};
-
-&gpio8 {
- u-boot,dm-pre-reloc;
+&vcc_sd {
+ u-boot,dm-spl;
};
&pcfg_pull_none_drv_8ma {
@@ -37,10 +37,22 @@
u-boot,dm-spl;
};
+&pcfg_pull_none {
+ u-boot,dm-spl;
+};
+
+&pcfg_pull_up {
+ u-boot,dm-spl;
+};
+
&sdmmc_bus4 {
u-boot,dm-spl;
};
+&sdmmc_cd {
+ u-boot,dm-spl;
+};
+
&sdmmc_clk {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi
index 4cf75c7..3f00a3b 100644
--- a/arch/arm/dts/rk3288-u-boot.dtsi
+++ b/arch/arm/dts/rk3288-u-boot.dtsi
@@ -3,6 +3,13 @@
* Copyright (C) 2019 Rockchip Electronics Co., Ltd
*/
+/ {
+ chosen {
+ u-boot,spl-boot-order = \
+ "same-as-spl", &emmc, &sdmmc;
+ };
+};
+
&dmc {
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi
index 916dd48..8754043 100644
--- a/arch/arm/dts/rk3288-veyron.dtsi
+++ b/arch/arm/dts/rk3288-veyron.dtsi
@@ -16,11 +16,7 @@
chosen {
stdout-path = &uart2;
- };
-
- config {
- u-boot,dm-pre-reloc;
- u-boot,boot0 = &spi_flash;
+ u-boot,spl-boot-order = &spi_flash;
};
firmware {
diff --git a/arch/arm/dts/rk3328-evb-u-boot.dtsi b/arch/arm/dts/rk3328-evb-u-boot.dtsi
new file mode 100644
index 0000000..4a82706
--- /dev/null
+++ b/arch/arm/dts/rk3328-evb-u-boot.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016-2019 Rockchip Electronics Co., Ltd
+ */
+
+#include "rk3328-u-boot.dtsi"
+#include "rk3328-sdram-ddr3-666.dtsi"
+
+&usb_host0_xhci {
+ vbus-supply = <&vcc5v0_host_xhci>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts
index ec594a8..a2ee838 100644
--- a/arch/arm/dts/rk3328-evb.dts
+++ b/arch/arm/dts/rk3328-evb.dts
@@ -116,11 +116,6 @@
status = "okay";
};
-&usb_host0_xhci {
- vbus-supply = <&vcc5v0_host_xhci>;
- status = "okay";
-};
-
&i2c1 {
clock-frequency = <400000>;
i2c-scl-rising-time-ns = <168>;
diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi
index b077436..1d441f7 100644
--- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi
@@ -1,34 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
- * (C) Copyright 2018 Rockchip Electronics Co., Ltd
- *
- * SPDX-License-Identifier: GPL-2.0+
+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
*/
-/ {
- aliases {
- mmc0 = &emmc;
- mmc1 = &sdmmc;
- };
+#include "rk3328-u-boot.dtsi"
+#include "rk3328-sdram-lpddr3-1600.dtsi"
- chosen {
- u-boot,spl-boot-order = &emmc, &sdmmc;
- };
-};
-
-&cru {
- u-boot,dm-pre-reloc;
-};
-
-&uart2 {
- u-boot,dm-pre-reloc;
-};
-
-&emmc {
- u-boot,dm-pre-reloc;
- fifo-mode;
-};
-
-&sdmmc {
- u-boot,dm-pre-reloc;
- fifo-mode;
+&usb_host0_xhci {
+ status = "okay";
};
diff --git a/arch/arm/dts/rk3328-rock64.dts b/arch/arm/dts/rk3328-rock64.dts
index 7bcc53f..a78eb4a 100644
--- a/arch/arm/dts/rk3328-rock64.dts
+++ b/arch/arm/dts/rk3328-rock64.dts
@@ -34,23 +34,10 @@
vcc_host_5v: vcc-host-5v-regulator {
compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&usb30_host_drv>;
- regulator-name = "vcc_host_5v";
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc_sys>;
- };
-
- vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&usb20_host_drv>;
- regulator-name = "vcc_host1_5v";
+ regulator-name = "vcc_host_5v";
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc_sys>;
@@ -244,12 +231,6 @@
rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
-
- usb3 {
- usb30_host_drv: usb30-host-drv {
- rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
};
&sdmmc {
diff --git a/arch/arm/dts/rk3328-sdram-ddr3-666.dtsi b/arch/arm/dts/rk3328-sdram-ddr3-666.dtsi
new file mode 100644
index 0000000..d99e7e0
--- /dev/null
+++ b/arch/arm/dts/rk3328-sdram-ddr3-666.dtsi
@@ -0,0 +1,215 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+&dmc {
+ rockchip,sdram-params = <
+ 0x1
+ 0xC
+ 0x3
+ 0x1
+ 0x0
+ 0x0
+ 0x10
+ 0x10
+ 0
+
+ 0x9028b189
+ 0x00000000
+ 0x00000021
+ 0x00000482
+ 0x00000015
+ 0x00000222
+ 0x000000ff
+
+ 333
+ 3
+ 0
+
+ 0x00000000
+ 0x43041001
+ 0x00000064
+ 0x0028003b
+ 0x000000d0
+ 0x00020053
+ 0x000000d4
+ 0x00020000
+ 0x000000d8
+ 0x00000100
+ 0x000000dc
+ 0x03200000
+ 0x000000e0
+ 0x00000000
+ 0x000000e4
+ 0x00090000
+ 0x000000f4
+ 0x000f011f
+ 0x00000100
+ 0x07090b06
+ 0x00000104
+ 0x00050209
+ 0x00000108
+ 0x03030407
+ 0x0000010c
+ 0x00202006
+ 0x00000110
+ 0x03020204
+ 0x00000114
+ 0x03030202
+ 0x00000120
+ 0x00000903
+ 0x00000180
+ 0x00800020
+ 0x00000184
+ 0x00000000
+ 0x00000190
+ 0x07010001
+ 0x00000198
+ 0x05001100
+ 0x000001a0
+ 0xc0400003
+ 0x00000240
+ 0x06000604
+ 0x00000244
+ 0x00000201
+ 0x00000250
+ 0x00000f00
+ 0x00000490
+ 0x00000001
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+
+ 0x00000004
+ 0x0000000a
+ 0x00000028
+ 0x00000006
+ 0x0000002c
+ 0x00000000
+ 0x00000030
+ 0x00000005
+ 0xffffffff
+ 0xffffffff
+
+ 0x77
+ 0x88
+ 0x79
+ 0x79
+ 0x87
+ 0x97
+ 0x87
+ 0x78
+ 0x77
+ 0x78
+ 0x87
+ 0x88
+ 0x87
+ 0x87
+ 0x77
+
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x69
+ 0x9
+
+ 0x77
+ 0x78
+ 0x77
+ 0x78
+ 0x77
+ 0x78
+ 0x77
+ 0x78
+ 0x77
+ 0x79
+ 0x9
+
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x69
+ 0x9
+
+ 0x77
+ 0x78
+ 0x77
+ 0x77
+ 0x77
+ 0x77
+ 0x77
+ 0x77
+ 0x77
+ 0x79
+ 0x9
+
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x69
+ 0x9
+
+ 0x77
+ 0x78
+ 0x77
+ 0x78
+ 0x77
+ 0x78
+ 0x77
+ 0x78
+ 0x77
+ 0x79
+ 0x9
+
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x69
+ 0x9
+
+ 0x77
+ 0x78
+ 0x77
+ 0x77
+ 0x77
+ 0x77
+ 0x77
+ 0x77
+ 0x77
+ 0x79
+ 0x9
+ >;
+};
diff --git a/arch/arm/dts/rk3328-sdram-lpddr3-1600.dtsi b/arch/arm/dts/rk3328-sdram-lpddr3-1600.dtsi
new file mode 100644
index 0000000..cc0011c
--- /dev/null
+++ b/arch/arm/dts/rk3328-sdram-lpddr3-1600.dtsi
@@ -0,0 +1,215 @@
+/*
+ * (C) 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+&dmc {
+ rockchip,sdram-params = <
+ 0x1
+ 0xC
+ 0x3
+ 0x1
+ 0x0
+ 0x0
+ 0x10
+ 0x10
+ 0
+
+ 0x98899459
+ 0x00000000
+ 0x0000002e
+ 0x00000544
+ 0x00000015
+ 0x00000432
+ 0x000000ff
+
+ 800
+ 6
+ 1
+
+ 0x00000000
+ 0x43041008
+ 0x00000064
+ 0x00300054
+ 0x000000d0
+ 0x00500002
+ 0x000000d4
+ 0x00010000
+ 0x000000d8
+ 0x00000e03
+ 0x000000dc
+ 0x0043001a
+ 0x000000e0
+ 0x00010000
+ 0x000000e4
+ 0x000e0005
+ 0x000000f4
+ 0x000f011f
+ 0x00000100
+ 0x0b141b11
+ 0x00000104
+ 0x0003031a
+ 0x00000108
+ 0x03060809
+ 0x0000010c
+ 0x00606000
+ 0x00000110
+ 0x08020409
+ 0x00000114
+ 0x01010606
+ 0x00000118
+ 0x02020004
+ 0x00000120
+ 0x00000404
+ 0x00000138
+ 0x00000058
+ 0x00000180
+ 0x00900024
+ 0x00000184
+ 0x01400000
+ 0x00000190
+ 0x07050002
+ 0x00000198
+ 0x05001100
+ 0x000001a0
+ 0xc0400003
+ 0x00000240
+ 0x0a020b28
+ 0x00000244
+ 0x00000101
+ 0x00000250
+ 0x00000f00
+ 0x00000490
+ 0x00000001
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+
+ 0x00000004
+ 0x0000000b
+ 0x00000028
+ 0x0000000c
+ 0x0000002c
+ 0x00000000
+ 0x00000030
+ 0x00000006
+ 0xffffffff
+ 0xffffffff
+
+ 0x77
+ 0x88
+ 0x79
+ 0x79
+ 0x87
+ 0x97
+ 0x87
+ 0x78
+ 0x77
+ 0x78
+ 0x87
+ 0x88
+ 0x87
+ 0x87
+ 0x77
+
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x69
+ 0x9
+
+ 0x77
+ 0x78
+ 0x77
+ 0x78
+ 0x77
+ 0x78
+ 0x77
+ 0x78
+ 0x77
+ 0x79
+ 0x9
+
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x69
+ 0x9
+
+ 0x77
+ 0x78
+ 0x77
+ 0x77
+ 0x77
+ 0x77
+ 0x77
+ 0x77
+ 0x77
+ 0x79
+ 0x9
+
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x69
+ 0x9
+
+ 0x77
+ 0x78
+ 0x77
+ 0x78
+ 0x77
+ 0x78
+ 0x77
+ 0x78
+ 0x77
+ 0x79
+ 0x9
+
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x69
+ 0x9
+
+ 0x77
+ 0x78
+ 0x77
+ 0x77
+ 0x77
+ 0x77
+ 0x77
+ 0x77
+ 0x77
+ 0x79
+ 0x9
+ >;
+};
diff --git a/arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi b/arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi
new file mode 100644
index 0000000..62d809e
--- /dev/null
+++ b/arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi
@@ -0,0 +1,215 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+&dmc {
+ rockchip,sdram-params = <
+ 0x1
+ 0xC
+ 0x3
+ 0x1
+ 0x0
+ 0x0
+ 0x10
+ 0x10
+ 0
+
+ 0x0c48a18a
+ 0x00000000
+ 0x00000021
+ 0x00000482
+ 0x00000015
+ 0x0000021a
+ 0x000000ff
+
+ 333
+ 6
+ 0
+
+ 0x00000000
+ 0xc3040008
+ 0x00000064
+ 0x00140023
+ 0x000000d0
+ 0x00220002
+ 0x000000d4
+ 0x00010000
+ 0x000000d8
+ 0x00000703
+ 0x000000dc
+ 0x00830004
+ 0x000000e0
+ 0x00010000
+ 0x000000e4
+ 0x00070003
+ 0x00000100
+ 0x06090b07
+ 0x00000104
+ 0x0002020b
+ 0x00000108
+ 0x02030506
+ 0x0000010c
+ 0x00505000
+ 0x00000110
+ 0x03020204
+ 0x00000114
+ 0x01010303
+ 0x00000118
+ 0x02020003
+ 0x00000120
+ 0x00000303
+ 0x00000138
+ 0x00000025
+ 0x00000180
+ 0x003c000f
+ 0x00000184
+ 0x00900000
+ 0x00000190
+ 0x07020000
+ 0x00000198
+ 0x05001100
+ 0x000001a0
+ 0xc0400003
+ 0x00000240
+ 0x0900090c
+ 0x00000244
+ 0x00000101
+ 0x00000250
+ 0x00000f00
+ 0x00000490
+ 0x00000001
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+
+ 0x00000004
+ 0x0000000b
+ 0x00000028
+ 0x00000006
+ 0x0000002c
+ 0x00000000
+ 0x00000030
+ 0x00000003
+ 0xffffffff
+ 0xffffffff
+
+ 0x77
+ 0x88
+ 0x79
+ 0x79
+ 0x87
+ 0x97
+ 0x87
+ 0x78
+ 0x77
+ 0x78
+ 0x87
+ 0x88
+ 0x87
+ 0x87
+ 0x77
+
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x69
+ 0x9
+
+ 0x77
+ 0x78
+ 0x77
+ 0x78
+ 0x77
+ 0x78
+ 0x77
+ 0x78
+ 0x77
+ 0x79
+ 0x9
+
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x69
+ 0x9
+
+ 0x77
+ 0x78
+ 0x77
+ 0x77
+ 0x77
+ 0x77
+ 0x77
+ 0x77
+ 0x77
+ 0x79
+ 0x9
+
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x69
+ 0x9
+
+ 0x77
+ 0x78
+ 0x77
+ 0x78
+ 0x77
+ 0x78
+ 0x77
+ 0x78
+ 0x77
+ 0x79
+ 0x9
+
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x69
+ 0x9
+
+ 0x77
+ 0x78
+ 0x77
+ 0x77
+ 0x77
+ 0x77
+ 0x77
+ 0x77
+ 0x77
+ 0x79
+ 0x9
+ >;
+};
diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi
new file mode 100644
index 0000000..ffbd657
--- /dev/null
+++ b/arch/arm/dts/rk3328-u-boot.dtsi
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+/ {
+ aliases {
+ mmc0 = &emmc;
+ mmc1 = &sdmmc;
+ };
+
+ chosen {
+ u-boot,spl-boot-order = &emmc, &sdmmc;
+ };
+
+ dmc: dmc {
+ u-boot,dm-pre-reloc;
+ compatible = "rockchip,rk3328-dmc";
+ reg = <0x0 0xff400000 0x0 0x1000
+ 0x0 0xff780000 0x0 0x3000
+ 0x0 0xff100000 0x0 0x1000
+ 0x0 0xff440000 0x0 0x1000
+ 0x0 0xff720000 0x0 0x1000
+ 0x0 0xff798000 0x0 0x1000>;
+ };
+
+ usb_host0_xhci: usb@ff600000 {
+ compatible = "rockchip,rk3328-xhci";
+ reg = <0x0 0xff600000 0x0 0x100000>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ snps,dis-enblslpm-quirk;
+ snps,phyif-utmi-bits = <16>;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis-u2-susphy-quirk;
+ status = "disabled";
+ };
+};
+
+&cru {
+ u-boot,dm-pre-reloc;
+};
+
+&grf {
+ u-boot,dm-pre-reloc;
+};
+
+&uart2 {
+ u-boot,dm-pre-reloc;
+ clock-frequency = <24000000>;
+};
+
+&emmc {
+ u-boot,dm-pre-reloc;
+};
+
+&sdmmc {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi
index 2d80add..060c84e 100644
--- a/arch/arm/dts/rk3328.dtsi
+++ b/arch/arm/dts/rk3328.dtsi
@@ -186,7 +186,6 @@
};
grf: syscon@ff100000 {
- u-boot,dm-pre-reloc;
compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
reg = <0x0 0xff100000 0x0 0x1000>;
@@ -232,7 +231,6 @@
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
- clock-frequency = <24000000>;
reg-shift = <2>;
reg-io-width = <4>;
dmas = <&dmac 6>, <&dmac 7>;
@@ -351,12 +349,6 @@
status = "disabled";
};
- dmc: dmc@ff400000 {
- u-boot,dm-pre-reloc;
- compatible = "rockchip,rk3328-dmc", "syscon";
- reg = <0x0 0xff400000 0x0 0x1000>;
- };
-
cru: clock-controller@ff440000 {
compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
reg = <0x0 0xff440000 0x0 0x1000>;
@@ -507,17 +499,6 @@
status = "disabled";
};
- usb_host0_xhci: usb@ff600000 {
- compatible = "rockchip,rk3328-xhci";
- reg = <0x0 0xff600000 0x0 0x100000>;
- interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
- snps,dis-enblslpm-quirk;
- snps,phyif-utmi-bits = <16>;
- snps,dis-u2-freeclk-exists-quirk;
- snps,dis-u2-susphy-quirk;
- status = "disabled";
- };
-
gic: interrupt-controller@ffb70000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
diff --git a/arch/arm/dts/rk3368-lion-u-boot.dtsi b/arch/arm/dts/rk3368-lion-u-boot.dtsi
index fb4a4fb..edc93e4 100644
--- a/arch/arm/dts/rk3368-lion-u-boot.dtsi
+++ b/arch/arm/dts/rk3368-lion-u-boot.dtsi
@@ -12,7 +12,6 @@
chosen {
stdout-path = "serial0:115200n8";
u-boot,spl-boot-order = &emmc, &sdmmc;
- tick-timer = "/timer@ff810000";
};
};
diff --git a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
index f5406d4..002767a 100644
--- a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
@@ -5,7 +5,6 @@
/ {
chosen {
u-boot,spl-boot-order = &emmc;
- tick-timer = "/timer@ff810000";
};
};
diff --git a/arch/arm/dts/rk3399-ficus-u-boot.dtsi b/arch/arm/dts/rk3399-ficus-u-boot.dtsi
index eab86bd..f3f7aa7 100644
--- a/arch/arm/dts/rk3399-ficus-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-ficus-u-boot.dtsi
@@ -3,4 +3,11 @@
* Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
*/
+#include "rk3399-u-boot.dtsi"
#include "rk3399-sdram-ddr3-1600.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = &sdhci, &sdmmc;
+ };
+};
diff --git a/arch/arm/dts/rk3399-ficus.dts b/arch/arm/dts/rk3399-ficus.dts
index 4b2dd82..6b059bd 100644
--- a/arch/arm/dts/rk3399-ficus.dts
+++ b/arch/arm/dts/rk3399-ficus.dts
@@ -23,6 +23,52 @@
clock-output-names = "clkin_gmac";
#clock-cells = <0>;
};
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&user_led1>, <&user_led2>, <&user_led3>,
+ <&user_led4>, <&wlan_led>, <&bt_led>;
+
+ user_led1 {
+ label = "red:user1";
+ gpios = <&gpio4 25 0>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ user_led2 {
+ label = "red:user2";
+ gpios = <&gpio4 26 0>;
+ linux,default-trigger = "mmc0";
+ };
+
+ user_led3 {
+ label = "red:user3";
+ gpios = <&gpio4 30 0>;
+ linux,default-trigger = "mmc1";
+ };
+
+ user_led4 {
+ label = "red:user4";
+ gpios = <&gpio1 0 0>;
+ panic-indicator;
+ linux,default-trigger = "none";
+ };
+
+ wlan_active_led {
+ label = "red:wlan";
+ gpios = <&gpio1 1 0>;
+ linux,default-trigger = "phy0tx";
+ default-state = "off";
+ };
+
+ bt_active_led {
+ label = "red:bt";
+ gpios = <&gpio1 4 0>;
+ linux,default-trigger = "hci0-power";
+ default-state = "off";
+ };
+ };
};
&gmac {
@@ -49,23 +95,63 @@
gmac {
rgmii_sleep_pins: rgmii-sleep-pins {
rockchip,pins =
- <3 15 RK_FUNC_GPIO &pcfg_output_low>;
+ <3 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>;
};
};
pcie {
pcie_drv: pcie-drv {
rockchip,pins =
- <1 24 RK_FUNC_GPIO &pcfg_pull_none>;
+ <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb2 {
host_vbus_drv: host-vbus-drv {
rockchip,pins =
- <4 27 RK_FUNC_GPIO &pcfg_pull_none>;
+ <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
+
+ leds {
+ user_led1: user_led1 {
+ rockchip,pins =
+ <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ user_led2: user_led2 {
+ rockchip,pins =
+ <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ user_led3: user_led3 {
+ rockchip,pins =
+ <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ user_led4: user_led4 {
+ rockchip,pins =
+ <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ wlan_led: wlan_led {
+ rockchip,pins =
+ <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_led: bt_led {
+ rockchip,pins =
+ <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&usbdrd_dwc3_0 {
+ dr_mode = "host";
+};
+
+&usbdrd_dwc3_1 {
+ dr_mode = "host";
};
&vcc3v3_pcie {
diff --git a/arch/arm/dts/rk3399-khadas-edge-captain-u-boot.dtsi b/arch/arm/dts/rk3399-khadas-edge-captain-u-boot.dtsi
new file mode 100644
index 0000000..ca1bbff
--- /dev/null
+++ b/arch/arm/dts/rk3399-khadas-edge-captain-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Nick Xie <nick@khadas.com>
+ */
+
+#include "rk3399-khadas-edge-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3399-khadas-edge-captain.dts b/arch/arm/dts/rk3399-khadas-edge-captain.dts
new file mode 100644
index 0000000..8302e51
--- /dev/null
+++ b/arch/arm/dts/rk3399-khadas-edge-captain.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd.
+ * (https://www.khadas.com)
+ */
+
+/dts-v1/;
+#include "rk3399-khadas-edge.dtsi"
+
+/ {
+ model = "Khadas Edge-Captain";
+ compatible = "khadas,edge-captain", "rockchip,rk3399";
+};
+
+&gmac {
+ status = "okay";
+};
+
+&pcie_phy {
+ status = "okay";
+};
+
+&pcie0 {
+ ep-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
+ num-lanes = <4>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi b/arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi
new file mode 100644
index 0000000..35b9fdd
--- /dev/null
+++ b/arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Nick Xie <nick@khadas.com>
+ */
+
+#include "rk3399-u-boot.dtsi"
+#include "rk3399-sdram-lpddr4-100.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
+ };
+};
diff --git a/arch/arm/dts/rk3399-khadas-edge-v-u-boot.dtsi b/arch/arm/dts/rk3399-khadas-edge-v-u-boot.dtsi
new file mode 100644
index 0000000..ca1bbff
--- /dev/null
+++ b/arch/arm/dts/rk3399-khadas-edge-v-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Nick Xie <nick@khadas.com>
+ */
+
+#include "rk3399-khadas-edge-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3399-khadas-edge-v.dts b/arch/arm/dts/rk3399-khadas-edge-v.dts
new file mode 100644
index 0000000..f5dcb99
--- /dev/null
+++ b/arch/arm/dts/rk3399-khadas-edge-v.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd.
+ * (https://www.khadas.com)
+ */
+
+/dts-v1/;
+#include "rk3399-khadas-edge.dtsi"
+
+/ {
+ model = "Khadas Edge-V";
+ compatible = "khadas,edge-v", "rockchip,rk3399";
+};
+
+&gmac {
+ status = "okay";
+};
+
+&pcie_phy {
+ status = "okay";
+};
+
+&pcie0 {
+ ep-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
+ num-lanes = <4>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3399-khadas-edge.dts b/arch/arm/dts/rk3399-khadas-edge.dts
new file mode 100644
index 0000000..31616e7
--- /dev/null
+++ b/arch/arm/dts/rk3399-khadas-edge.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd.
+ * (https://www.khadas.com)
+ */
+
+/dts-v1/;
+#include "rk3399-khadas-edge.dtsi"
+
+/ {
+ model = "Khadas Edge";
+ compatible = "khadas,edge", "rockchip,rk3399";
+};
diff --git a/arch/arm/dts/rk3399-khadas-edge.dtsi b/arch/arm/dts/rk3399-khadas-edge.dtsi
new file mode 100644
index 0000000..4944d78
--- /dev/null
+++ b/arch/arm/dts/rk3399-khadas-edge.dtsi
@@ -0,0 +1,804 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd.
+ * (https://www.khadas.com)
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/pwm/pwm.h>
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk808 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+
+ /*
+ * On the module itself this is one of these (depending
+ * on the actual card populated):
+ * - SDIO_RESET_L_WL_REG_ON
+ * - PDN (power down when low)
+ */
+ reset-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_LOW>;
+ };
+
+ /* switched by pmic_sleep */
+ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc1v8_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_1v8>;
+ };
+
+ vcc3v3_pcie: vcc3v3-pcie-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_pcie";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vsys_3v3>;
+ };
+
+ /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */
+ vcc5v0_host: vcc5v0-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_host_en>;
+ regulator-name = "vcc5v0_host";
+ regulator-always-on;
+ vin-supply = <&vsys_5v0>;
+ };
+
+ vdd_log: vdd-log {
+ compatible = "pwm-regulator";
+ pwms = <&pwm2 0 25000 1>;
+ regulator-name = "vdd_log";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ vin-supply = <&vsys_3v3>;
+ };
+
+ vsys: vsys {
+ compatible = "regulator-fixed";
+ regulator-name = "vsys";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vsys_3v3: vsys-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vsys>;
+ };
+
+ vsys_5v0: vsys-5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_5v0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vsys>;
+ };
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 1>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+ poll-interval = <100>;
+
+ recovery {
+ label = "Recovery";
+ linux,code = <KEY_VENDOR>;
+ press-threshold-microvolt = <18000>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwrbtn>;
+
+ power {
+ debounce-interval = <100>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "GPIO Key Power";
+ linux,code = <KEY_POWER>;
+ wakeup-source;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sys_led_gpio>, <&user_led_gpio>;
+
+ sys-led {
+ label = "sys_led";
+ linux,default-trigger = "heartbeat";
+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+ };
+
+ user-led {
+ label = "user_led";
+ default-state = "off";
+ gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ fan: pwm-fan {
+ compatible = "pwm-fan";
+ cooling-levels = <0 150 200 255>;
+ #cooling-cells = <2>;
+ fan-supply = <&vsys_5v0>;
+ pwms = <&pwm0 0 40000 0>;
+ };
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_thermal {
+ trips {
+ cpu_warm: cpu_warm {
+ temperature = <55000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ cpu_hot: cpu_hot {
+ temperature = <65000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map2 {
+ trip = <&cpu_warm>;
+ cooling-device = <&fan THERMAL_NO_LIMIT 1>;
+ };
+
+ map3 {
+ trip = <&cpu_hot>;
+ cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
+ };
+ };
+};
+
+&emmc_phy {
+ status = "okay";
+};
+
+&gmac {
+ assigned-clocks = <&cru SCLK_RMII_SRC>;
+ assigned-clock-parents = <&clkin_gmac>;
+ clock_in_out = "input";
+ phy-supply = <&vcc_lan>;
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 50000>;
+ tx_delay = <0x28>;
+ rx_delay = <0x11>;
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&gpu_thermal {
+ trips {
+ gpu_warm: gpu_warm {
+ temperature = <55000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ gpu_hot: gpu_hot {
+ temperature = <65000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map1 {
+ trip = <&gpu_warm>;
+ cooling-device = <&fan THERMAL_NO_LIMIT 1>;
+ };
+
+ map2 {
+ trip = <&gpu_hot>;
+ cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
+ };
+ };
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_cec>;
+ status = "okay";
+};
+
+&hdmi_sound {
+ status = "okay";
+};
+
+&i2c3 {
+ i2c-scl-rising-time-ns = <450>;
+ i2c-scl-falling-time-ns = <15>;
+ status = "okay";
+};
+
+&i2c4 {
+ clock-frequency = <400000>;
+ i2c-scl-rising-time-ns = <168>;
+ i2c-scl-falling-time-ns = <4>;
+ status = "okay";
+
+ rk808: pmic@1b {
+ compatible = "rockchip,rk808";
+ reg = <0x1b>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <RK_PC6 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk808-clkout2";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vsys_3v3>;
+ vcc2-supply = <&vsys_3v3>;
+ vcc3-supply = <&vsys_3v3>;
+ vcc4-supply = <&vsys_3v3>;
+ vcc6-supply = <&vsys_3v3>;
+ vcc7-supply = <&vsys_3v3>;
+ vcc8-supply = <&vsys_3v3>;
+ vcc9-supply = <&vsys_3v3>;
+ vcc10-supply = <&vsys_3v3>;
+ vcc11-supply = <&vsys_3v3>;
+ vcc12-supply = <&vsys_3v3>;
+ vddio-supply = <&vcc_1v8>;
+
+ regulators {
+ vdd_center: DCDC_REG1 {
+ regulator-name = "vdd_center";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_l: DCDC_REG2 {
+ regulator-name = "vdd_cpu_l";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG4 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc1v8_apio2: LDO_REG1 {
+ regulator-name = "vcc1v8_apio2";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_vldo2: LDO_REG2 {
+ regulator-name = "vcc_vldo2";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc1v8_pmupll: LDO_REG3 {
+ regulator-name = "vcc1v8_pmupll";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vccio_sd: LDO_REG4 {
+ regulator-name = "vccio_sd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3000000>;
+ };
+ };
+
+ vcc_vldo5: LDO_REG5 {
+ regulator-name = "vcc_vldo5";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v5: LDO_REG6 {
+ regulator-name = "vcc_1v5";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1500000>;
+ };
+ };
+
+ vcc1v8_codec: LDO_REG7 {
+ regulator-name = "vcc1v8_codec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v0: LDO_REG8 {
+ regulator-name = "vcc_3v0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3000000>;
+ };
+ };
+
+ vcc3v3_s3: vcc_lan: SWITCH_REG1 {
+ regulator-name = "vcc3v3_s3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_s0: SWITCH_REG2 {
+ regulator-name = "vcc3v3_s0";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+
+ vdd_cpu_b: regulator@40 {
+ compatible = "silergy,syr827";
+ reg = <0x40>;
+ fcs,suspend-voltage-selector = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpu_b_sleep>;
+ regulator-name = "vdd_cpu_b";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1500000>;
+ regulator-ramp-delay = <1000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vsys_3v3>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: regulator@41 {
+ compatible = "silergy,syr828";
+ reg = <0x41>;
+ fcs,suspend-voltage-selector = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpu_sleep>;
+ regulator-name = "vdd_gpu";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1500000>;
+ regulator-ramp-delay = <1000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vsys_3v3>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c8 {
+ clock-frequency = <400000>;
+ i2c-scl-rising-time-ns = <160>;
+ i2c-scl-falling-time-ns = <30>;
+ status = "okay";
+};
+
+&i2s0 {
+ rockchip,playback-channels = <8>;
+ rockchip,capture-channels = <8>;
+ status = "okay";
+};
+
+&i2s1 {
+ rockchip,playback-channels = <2>;
+ rockchip,capture-channels = <2>;
+ status = "okay";
+};
+
+&i2s2 {
+ status = "okay";
+};
+
+&io_domains {
+ bt656-supply = <&vcc1v8_apio2>;
+ audio-supply = <&vcc1v8_codec>;
+ sdmmc-supply = <&vccio_sd>;
+ gpio1830-supply = <&vcc_3v0>;
+ status = "okay";
+};
+
+&pmu_io_domains {
+ pmu1830-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&pinctrl {
+ bt {
+ bt_host_wake_l: bt-host-wake-l {
+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_reg_on_h: bt-reg-on-h {
+ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_wake_l: bt-wake-l {
+ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ buttons {
+ pwrbtn: pwrbtn {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ leds {
+ sys_led_gpio: sys_led-gpio {
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ user_led_gpio: user_led-gpio {
+ rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ cpu_b_sleep: cpu-b-sleep {
+ rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ gpu_sleep: gpu-sleep {
+ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb2 {
+ vcc5v0_host_en: vcc5v0-host-en {
+ rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ wifi {
+ wifi_host_wake_l: wifi-host-wake-l {
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pwm0 {
+ status = "okay";
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcca1v8_s3>;
+ status = "okay";
+};
+
+&sdio0 {
+ /* WiFi & BT combo module Ampak AP6356S */
+ bus-width = <4>;
+ cap-sdio-irq;
+ cap-sd-highspeed;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+ sd-uhs-sdr104;
+ vqmmc-supply = <&vcc1v8_s3>;
+ vmmc-supply = <&vccio_sd>;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
+ interrupt-names = "host-wake";
+ brcm,drive-strength = <5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_host_wake_l>;
+ };
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ max-frequency = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ non-removable;
+ status = "okay";
+};
+
+&tcphy0 {
+ status = "okay";
+};
+
+&tcphy1 {
+ status = "okay";
+};
+
+&tsadc {
+ /* tshut mode 0:CRU 1:GPIO */
+ rockchip,hw-tshut-mode = <1>;
+ /* tshut polarity 0:LOW 1:HIGH */
+ rockchip,hw-tshut-polarity = <1>;
+ status = "okay";
+};
+
+&u2phy0 {
+ status = "okay";
+
+ u2phy0_otg: otg-port {
+ status = "okay";
+ };
+
+ u2phy0_host: host-port {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+ };
+};
+
+&u2phy1 {
+ status = "okay";
+
+ u2phy1_otg: otg-port {
+ status = "okay";
+ };
+
+ u2phy1_host: host-port {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ clocks = <&rk808 1>;
+ clock-names = "lpo";
+ device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
+ max-speed = <4000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>;
+ vbat-supply = <&vsys_3v3>;
+ vddio-supply = <&vcc_1v8>;
+ };
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&usbdrd3_0 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+ status = "okay";
+ dr_mode = "otg";
+};
+
+&usbdrd3_1 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&vopl {
+ status = "okay";
+};
+
+&vopl_mmu {
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi
new file mode 100644
index 0000000..77d5cf5
--- /dev/null
+++ b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Levin Du <djw@t-chip.com.cn>
+ */
+
+#include "rk3399-u-boot.dtsi"
+#include "rk3399-sdram-lpddr4-100.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
+ };
+};
+
+&vdd_log {
+ regulator-min-microvolt = <430000>;
+ regulator-init-microvolt = <950000>;
+};
diff --git a/arch/arm/dts/rk3399-roc-pc.dts b/arch/arm/dts/rk3399-roc-pc.dts
new file mode 100644
index 0000000..19f7732
--- /dev/null
+++ b/arch/arm/dts/rk3399-roc-pc.dts
@@ -0,0 +1,680 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
+ */
+
+/dts-v1/;
+#include <dt-bindings/pwm/pwm.h>
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+ model = "Firefly ROC-RK3399-PC Board";
+ compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399";
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm0 0 25000 0>;
+ };
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk808 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+
+ /*
+ * On the module itself this is one of these (depending
+ * on the actual card populated):
+ * - SDIO_RESET_L_WL_REG_ON
+ * - PDN (power down when low)
+ */
+ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+ };
+
+ vcc_vbus_typec0: vcc-vbus-typec0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_vbus_typec0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ /*
+ * should be placed inside mp8859, but not until mp8859 has
+ * its own dt-binding.
+ */
+ vcc12v_sys: mp8859-dcdc1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ vin-supply = <&vcc_vbus_typec0>;
+ };
+
+ /* switched by pmic_sleep */
+ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc1v8_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_1v8>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc12v_sys>;
+ };
+
+ /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */
+ vcc5v0_host: vcc5v0-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_host_en &hub_rst>;
+ regulator-name = "vcc5v0_host";
+ regulator-always-on;
+ vin-supply = <&vcc_sys>;
+ };
+
+ vcc_vbus_typec1: vcc-vbus-typec1 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc_vbus_typec1_en>;
+ regulator-name = "vcc_vbus_typec1";
+ regulator-always-on;
+ vin-supply = <&vcc_sys>;
+ };
+
+ vcc_sys: vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_sys>;
+ };
+
+ vdd_log: vdd-log {
+ compatible = "pwm-regulator";
+ pwms = <&pwm2 0 25000 1>;
+ regulator-name = "vdd_log";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_b>;
+};
+
+&emmc_phy {
+ status = "okay";
+};
+
+&gmac {
+ assigned-clocks = <&cru SCLK_RMII_SRC>;
+ assigned-clock-parents = <&clkin_gmac>;
+ clock_in_out = "input";
+ phy-supply = <&vcc_lan>;
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 50000>;
+ tx_delay = <0x28>;
+ rx_delay = <0x11>;
+ status = "okay";
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_cec>;
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ i2c-scl-rising-time-ns = <168>;
+ i2c-scl-falling-time-ns = <4>;
+ status = "okay";
+
+ rk808: pmic@1b {
+ compatible = "rockchip,rk808";
+ reg = <0x1b>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk808-clkout2";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+ vcc10-supply = <&vcc3v3_sys>;
+ vcc11-supply = <&vcc3v3_sys>;
+ vcc12-supply = <&vcc3v3_sys>;
+ vddio-supply = <&vcc1v8_pmu>;
+
+ regulators {
+ vdd_center: DCDC_REG1 {
+ regulator-name = "vdd_center";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_l: DCDC_REG2 {
+ regulator-name = "vdd_cpu_l";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG4 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca1v8_codec: LDO_REG1 {
+ regulator-name = "vcca1v8_codec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc1v8_hdmi: LDO_REG2 {
+ regulator-name = "vcc1v8_hdmi";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc1v8_pmu: LDO_REG3 {
+ regulator-name = "vcc1v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_sdio: LDO_REG4 {
+ regulator-name = "vcc_sdio";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3000000>;
+ };
+ };
+
+ vcca3v0_codec: LDO_REG5 {
+ regulator-name = "vcca3v0_codec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v5: LDO_REG6 {
+ regulator-name = "vcc_1v5";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1500000>;
+ };
+ };
+
+ vcca0v9_hdmi: LDO_REG7 {
+ regulator-name = "vcca0v9_hdmi";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v0: LDO_REG8 {
+ regulator-name = "vcc_3v0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3000000>;
+ };
+ };
+
+ vcc3v3_s3: vcc_lan: SWITCH_REG1 {
+ regulator-name = "vcc3v3_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_s0: SWITCH_REG2 {
+ regulator-name = "vcc3v3_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+
+ vdd_cpu_b: regulator@40 {
+ compatible = "silergy,syr827";
+ reg = <0x40>;
+ fcs,suspend-voltage-selector = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vsel1_gpio>;
+ regulator-name = "vdd_cpu_b";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1500000>;
+ regulator-ramp-delay = <1000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc3v3_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: regulator@41 {
+ compatible = "silergy,syr828";
+ reg = <0x41>;
+ fcs,suspend-voltage-selector = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vsel2_gpio>;
+ regulator-name = "vdd_gpu";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1500000>;
+ regulator-ramp-delay = <1000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc3v3_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c1 {
+ i2c-scl-rising-time-ns = <300>;
+ i2c-scl-falling-time-ns = <15>;
+ status = "okay";
+};
+
+&i2c3 {
+ i2c-scl-rising-time-ns = <450>;
+ i2c-scl-falling-time-ns = <15>;
+ status = "okay";
+};
+
+&i2c4 {
+ i2c-scl-rising-time-ns = <600>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+
+ fusb1: usb-typec@22 {
+ compatible = "fcs,fusb302";
+ reg = <0x22>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&fusb1_int>;
+ vbus-supply = <&vcc_vbus_typec1>;
+ status = "okay";
+ };
+};
+
+&i2c7 {
+ i2c-scl-rising-time-ns = <600>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+
+ fusb0: usb-typec@22 {
+ compatible = "fcs,fusb302";
+ reg = <0x22>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&fusb0_int>;
+ vbus-supply = <&vcc_vbus_typec0>;
+ status = "okay";
+ };
+};
+
+&i2s0 {
+ rockchip,playback-channels = <8>;
+ rockchip,capture-channels = <8>;
+ status = "okay";
+};
+
+&i2s1 {
+ rockchip,playback-channels = <2>;
+ rockchip,capture-channels = <2>;
+ status = "okay";
+};
+
+&i2s2 {
+ status = "okay";
+};
+
+&io_domains {
+ audio-supply = <&vcca1v8_codec>;
+ bt656-supply = <&vcc_3v0>;
+ gpio1830-supply = <&vcc_3v0>;
+ sdmmc-supply = <&vcc_sdio>;
+ status = "okay";
+};
+
+&pmu_io_domains {
+ pmu1830-supply = <&vcc_3v0>;
+ status = "okay";
+};
+
+&pinctrl {
+ lcd-panel {
+ lcd_panel_reset: lcd-panel-reset {
+ rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ pmic {
+ vsel1_gpio: vsel1-gpio {
+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ vsel2_gpio: vsel2-gpio {
+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ usb2 {
+ vcc5v0_host_en: vcc5v0-host-en {
+ rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ hub_rst: hub-rst {
+ rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_output_high>;
+ };
+ };
+
+ usb-typec {
+ vcc_vbus_typec1_en: vcc-vbus-typec1-en {
+ rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ fusb30x {
+ fusb0_int: fusb0-int {
+ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ fusb1_int: fusb1-int {
+ rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+&pwm0 {
+ status = "okay";
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcca1v8_s3>;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ max-frequency = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ non-removable;
+ status = "okay";
+};
+
+&tcphy0 {
+ status = "okay";
+};
+
+&tcphy1 {
+ status = "okay";
+};
+
+&tsadc {
+ /* tshut mode 0:CRU 1:GPIO */
+ rockchip,hw-tshut-mode = <1>;
+ /* tshut polarity 0:LOW 1:HIGH */
+ rockchip,hw-tshut-polarity = <1>;
+ status = "okay";
+};
+
+&u2phy0 {
+ status = "okay";
+
+ u2phy0_otg: otg-port {
+ phy-supply = <&vcc_vbus_typec0>;
+ status = "okay";
+ };
+
+ u2phy0_host: host-port {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+ };
+};
+
+&u2phy1 {
+ status = "okay";
+
+ u2phy1_otg: otg-port {
+ phy-supply = <&vcc_vbus_typec1>;
+ status = "okay";
+ };
+
+ u2phy1_host: host-port {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&usbdrd3_0 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+ status = "okay";
+};
+
+&usbdrd3_1 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&vopl {
+ status = "okay";
+};
+
+&vopl_mmu {
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
index dbfa4ba..1a83e5f 100644
--- a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
@@ -5,3 +5,9 @@
#include "rk3399-u-boot.dtsi"
#include "rk3399-sdram-lpddr4-100.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = &sdmmc, &sdhci;
+ };
+};
diff --git a/arch/arm/dts/rk3399-rock-pi-4.dts b/arch/arm/dts/rk3399-rock-pi-4.dts
index ea41b20..4a543f2 100644
--- a/arch/arm/dts/rk3399-rock-pi-4.dts
+++ b/arch/arm/dts/rk3399-rock-pi-4.dts
@@ -16,8 +16,6 @@
chosen {
stdout-path = "serial2:1500000n8";
- u-boot,spl-boot-order = \
- &sdmmc, &sdhci;
};
clkin_gmac: external-gmac-clock {
diff --git a/arch/arm/dts/rk3399-rock960-u-boot.dtsi b/arch/arm/dts/rk3399-rock960-u-boot.dtsi
index 5256f6d..4850deb 100644
--- a/arch/arm/dts/rk3399-rock960-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-rock960-u-boot.dtsi
@@ -3,4 +3,11 @@
* Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
*/
+#include "rk3399-u-boot.dtsi"
#include "rk3399-sdram-lpddr3-2GB-1600.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = &sdhci, &sdmmc;
+ };
+};
diff --git a/arch/arm/dts/rk3399-rock960.dts b/arch/arm/dts/rk3399-rock960.dts
index 7e06bc9..12285c5 100644
--- a/arch/arm/dts/rk3399-rock960.dts
+++ b/arch/arm/dts/rk3399-rock960.dts
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0+
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ * Copyright (c) 2018 Linaro Ltd.
*/
/dts-v1/;
@@ -13,6 +13,53 @@
chosen {
stdout-path = "serial2:1500000n8";
};
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&user_led1>, <&user_led2>, <&user_led3>,
+ <&user_led4>, <&wlan_led>, <&bt_led>;
+
+ user_led1 {
+ label = "green:user1";
+ gpios = <&gpio4 RK_PC2 0>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ user_led2 {
+ label = "green:user2";
+ gpios = <&gpio4 RK_PC6 0>;
+ linux,default-trigger = "mmc0";
+ };
+
+ user_led3 {
+ label = "green:user3";
+ gpios = <&gpio4 RK_PD0 0>;
+ linux,default-trigger = "mmc1";
+ };
+
+ user_led4 {
+ label = "green:user4";
+ gpios = <&gpio4 RK_PD4 0>;
+ panic-indicator;
+ linux,default-trigger = "none";
+ };
+
+ wlan_active_led {
+ label = "yellow:wlan";
+ gpios = <&gpio4 RK_PD5 0>;
+ linux,default-trigger = "phy0tx";
+ default-state = "off";
+ };
+
+ bt_active_led {
+ label = "blue:bt";
+ gpios = <&gpio4 RK_PD6 0>;
+ linux,default-trigger = "hci0-power";
+ default-state = "off";
+ };
+ };
+
};
&pcie0 {
@@ -20,6 +67,38 @@
};
&pinctrl {
+ leds {
+ user_led1: user_led1 {
+ rockchip,pins =
+ <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ user_led2: user_led2 {
+ rockchip,pins =
+ <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ user_led3: user_led3 {
+ rockchip,pins =
+ <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ user_led4: user_led4 {
+ rockchip,pins =
+ <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ wlan_led: wlan_led {
+ rockchip,pins =
+ <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_led: bt_led {
+ rockchip,pins =
+ <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
pcie {
pcie_drv: pcie-drv {
rockchip,pins =
@@ -35,6 +114,14 @@
};
};
+&usbdrd_dwc3_0 {
+ dr_mode = "otg";
+};
+
+&usbdrd_dwc3_1 {
+ dr_mode = "host";
+};
+
&vcc3v3_pcie {
gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>;
};
diff --git a/arch/arm/dts/rk3399-rock960.dtsi b/arch/arm/dts/rk3399-rock960.dtsi
index 51644d6..c7d48d4 100644
--- a/arch/arm/dts/rk3399-rock960.dtsi
+++ b/arch/arm/dts/rk3399-rock960.dtsi
@@ -1,13 +1,32 @@
-// SPDX-License-Identifier: GPL-2.0+
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
+ * Copyright (c) 2018 Collabora Ltd.
+ * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.
* Copyright (c) 2018 Linaro Ltd.
*/
-#include <dt-bindings/pwm/pwm.h>
-#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
/ {
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk808 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+ };
+
+ vcc12v_dcin: vcc12v-dcin {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
vcc1v8_s0: vcc1v8-s0 {
compatible = "regulator-fixed";
regulator-name = "vcc1v8_s0";
@@ -16,12 +35,13 @@
regulator-always-on;
};
- vcc_sys: vcc-sys {
+ vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
- regulator-name = "vcc_sys";
+ regulator-name = "vcc5v0_sys";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
+ vin-supply = <&vcc12v_dcin>;
};
vcc3v3_sys: vcc3v3-sys {
@@ -30,7 +50,7 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
- vin-supply = <&vcc_sys>;
+ vin-supply = <&vcc5v0_sys>;
};
vcc3v3_pcie: vcc3v3-pcie-regulator {
@@ -54,20 +74,8 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
- vin-supply = <&vcc_sys>;
+ vin-supply = <&vcc5v0_sys>;
};
-
- vdd_log: vdd-log {
- compatible = "pwm-regulator";
- pwms = <&pwm2 0 25000 0>;
- regulator-name = "vdd_log";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1400000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc_sys>;
- };
-
};
&cpu_l0 {
@@ -98,7 +106,19 @@
status = "okay";
};
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
&hdmi {
+ ddc-i2c-bus = <&i2c3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_cec>;
+ status = "okay";
+};
+
+&hdmi_sound {
status = "okay";
};
@@ -118,7 +138,7 @@
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
- vin-supply = <&vcc_sys>;
+ vin-supply = <&vcc5v0_sys>;
status = "okay";
regulator-state-mem {
@@ -136,7 +156,7 @@
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
- vin-supply = <&vcc_sys>;
+ vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
@@ -154,16 +174,16 @@
#clock-cells = <1>;
clock-output-names = "xin32k", "rk808-clkout2";
- vcc1-supply = <&vcc_sys>;
- vcc2-supply = <&vcc_sys>;
- vcc3-supply = <&vcc_sys>;
- vcc4-supply = <&vcc_sys>;
- vcc6-supply = <&vcc_sys>;
- vcc7-supply = <&vcc_sys>;
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc6-supply = <&vcc5v0_sys>;
+ vcc7-supply = <&vcc5v0_sys>;
vcc8-supply = <&vcc3v3_sys>;
- vcc9-supply = <&vcc_sys>;
- vcc10-supply = <&vcc_sys>;
- vcc11-supply = <&vcc_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+ vcc10-supply = <&vcc5v0_sys>;
+ vcc11-supply = <&vcc5v0_sys>;
vcc12-supply = <&vcc3v3_sys>;
vddio-supply = <&vcc_1v8>;
@@ -344,6 +364,10 @@
status = "okay";
};
+&i2s2 {
+ status = "okay";
+};
+
&io_domains {
bt656-supply = <&vcc1v8_s0>; /* bt656_gpio2ab_ms */
audio-supply = <&vcc1v8_s0>; /* audio_gpio3d4a_ms */
@@ -370,45 +394,92 @@
};
&pinctrl {
+ bt {
+ bt_enable_h: bt-enable-h {
+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_host_wake_l: bt-host-wake-l {
+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_wake_l: bt-wake-l {
+ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
sdmmc {
sdmmc_bus1: sdmmc-bus1 {
rockchip,pins =
- <4 8 RK_FUNC_1 &pcfg_pull_up_8ma>;
+ <4 RK_PB0 1 &pcfg_pull_up_8ma>;
};
sdmmc_bus4: sdmmc-bus4 {
rockchip,pins =
- <4 8 RK_FUNC_1 &pcfg_pull_up_8ma>,
- <4 9 RK_FUNC_1 &pcfg_pull_up_8ma>,
- <4 10 RK_FUNC_1 &pcfg_pull_up_8ma>,
- <4 11 RK_FUNC_1 &pcfg_pull_up_8ma>;
+ <4 RK_PB0 1 &pcfg_pull_up_8ma>,
+ <4 RK_PB1 1 &pcfg_pull_up_8ma>,
+ <4 RK_PB2 1 &pcfg_pull_up_8ma>,
+ <4 RK_PB3 1 &pcfg_pull_up_8ma>;
};
sdmmc_clk: sdmmc-clk {
rockchip,pins =
- <4 12 RK_FUNC_1 &pcfg_pull_none_18ma>;
+ <4 RK_PB4 1 &pcfg_pull_none_18ma>;
};
sdmmc_cmd: sdmmc-cmd {
rockchip,pins =
- <4 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
+ <4 RK_PB5 1 &pcfg_pull_up_8ma>;
+ };
+ };
+
+ sdio0 {
+ sdio0_bus4: sdio0-bus4 {
+ rockchip,pins =
+ <2 RK_PC4 1 &pcfg_pull_up_20ma>,
+ <2 RK_PC5 1 &pcfg_pull_up_20ma>,
+ <2 RK_PC6 1 &pcfg_pull_up_20ma>,
+ <2 RK_PC7 1 &pcfg_pull_up_20ma>;
+ };
+
+ sdio0_cmd: sdio0-cmd {
+ rockchip,pins =
+ <2 RK_PD0 1 &pcfg_pull_up_20ma>;
+ };
+
+ sdio0_clk: sdio0-clk {
+ rockchip,pins =
+ <2 RK_PD1 1 &pcfg_pull_none_20ma>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins =
- <1 21 RK_FUNC_GPIO &pcfg_pull_up>;
+ <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
};
vsel1_gpio: vsel1-gpio {
rockchip,pins =
- <1 17 RK_FUNC_GPIO &pcfg_pull_down>;
+ <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
};
vsel2_gpio: vsel2-gpio {
rockchip,pins =
- <1 14 RK_FUNC_GPIO &pcfg_pull_down>;
+ <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins =
+ <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ wifi {
+ wifi_host_wake_l: wifi-host-wake-l {
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
@@ -421,6 +492,32 @@
status = "okay";
};
+&sdio0 {
+ bus-width = <4>;
+ clock-frequency = <50000000>;
+ cap-sdio-irq;
+ cap-sd-highspeed;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+ sd-uhs-sdr104;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ compatible = "brcm,bcm4329-fmac";
+ reg = <1>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
+ interrupt-names = "host-wake";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_host_wake_l>;
+ };
+};
+
&sdhci {
bus-width = <8>;
mmc-hs400-1_8v;
@@ -445,16 +542,42 @@
status = "okay";
};
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer &uart0_cts>;
+&tsadc {
+ rockchip,hw-tshut-mode = <1>;
+ rockchip,hw-tshut-polarity = <1>;
+ rockchip,hw-tshut-temp = <110000>;
status = "okay";
};
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ clocks = <&rk808 1>;
+ clock-names = "ext_clock";
+ device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
+ };
+};
+
&uart2 {
status = "okay";
};
+&tcphy0 {
+ status = "okay";
+};
+
+&tcphy1 {
+ status = "okay";
+};
+
&u2phy0 {
status = "okay";
};
@@ -497,10 +620,34 @@
status = "okay";
};
+&usbdrd3_0 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+ status = "okay";
+};
+
+&usbdrd3_1 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+ status = "okay";
+};
+
&vopb {
status = "okay";
};
+&vopb_mmu {
+ status = "okay";
+};
+
&vopl {
status = "okay";
};
+
+&vopl_mmu {
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
index f7f26d5..a073ea2 100644
--- a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
@@ -5,6 +5,11 @@
#include "rk3399-u-boot.dtsi"
#include "rk3399-sdram-lpddr4-100.dtsi"
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
+ };
+};
&vdd_log {
regulator-init-microvolt = <950000>;
diff --git a/arch/arm/dts/salvator-common.dtsi b/arch/arm/dts/salvator-common.dtsi
index a225c24..2dba132 100644
--- a/arch/arm/dts/salvator-common.dtsi
+++ b/arch/arm/dts/salvator-common.dtsi
@@ -29,6 +29,7 @@
*/
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
/ {
aliases {
@@ -86,6 +87,63 @@
};
};
+ keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&keys_pins>;
+ pinctrl-names = "default";
+
+ key-1 {
+ gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_1>;
+ label = "SW4-1";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-2 {
+ gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_2>;
+ label = "SW4-2";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-3 {
+ gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_3>;
+ label = "SW4-3";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-4 {
+ gpios = <&gpio5 23 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_4>;
+ label = "SW4-4";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-a {
+ gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_A>;
+ label = "TSW0";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-b {
+ gpios = <&gpio6 12 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_B>;
+ label = "TSW1";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ key-c {
+ gpios = <&gpio6 13 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_C>;
+ label = "TSW2";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ };
+
reg_1p8v: regulator0 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
@@ -572,6 +630,11 @@
function = "intc_ex";
};
+ keys_pins: keys {
+ pins = "GP_5_17", "GP_5_20", "GP_5_22";
+ bias-pull-up;
+ };
+
pwm1_pins: pwm1 {
groups = "pwm1_a";
function = "pwm1";
@@ -719,6 +782,11 @@
};
};
+&rwdt {
+ timeout-sec = <60>;
+ status = "okay";
+};
+
&scif1 {
pinctrl-0 = <&scif1_pins>;
pinctrl-names = "default";
@@ -857,11 +925,6 @@
status = "okay";
};
-&rwdt {
- timeout-sec = <60>;
- status = "okay";
-};
-
&xhci0 {
pinctrl-0 = <&usb30_pins>;
pinctrl-names = "default";
diff --git a/arch/arm/dts/stih407-clock.dtsi b/arch/arm/dts/stih407-clock.dtsi
index 13029c0..1ab40db 100644
--- a/arch/arm/dts/stih407-clock.dtsi
+++ b/arch/arm/dts/stih407-clock.dtsi
@@ -1,39 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 STMicroelectronics R&D Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
*/
#include <dt-bindings/clock/stih407-clks.h>
/ {
+ /*
+ * Fixed 30MHz oscillator inputs to SoC
+ */
+ clk_sysin: clk-sysin {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <30000000>;
+ };
+
+ clk_tmdsout_hdmi: clk-tmdsout-hdmi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/*
- * Fixed 30MHz oscillator inputs to SoC
- */
- clk_sysin: clk-sysin {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <30000000>;
- };
-
- /*
- * ARM Peripheral clock for timers
- */
- arm_periph_clk: clk-m-a9-periphs {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
-
- clocks = <&clk_m_a9>;
- clock-div = <2>;
- clock-mult = <1>;
- };
-
- /*
* A9 PLL.
*/
clockgen-a9@92b0000 {
@@ -62,35 +53,22 @@
<&clockgen_a9_pll 0>,
<&clk_s_c0_flexgen 13>,
<&clk_m_a9_ext2f_div2>;
+
+
+ /*
+ * ARM Peripheral clock for timers
+ */
+ arm_periph_clk: clk-m-a9-periphs {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+
+ clocks = <&clk_m_a9>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
};
- /*
- * ARM Peripheral clock for timers
- */
- clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
-
- clocks = <&clk_s_c0_flexgen 13>;
-
- clock-output-names = "clk-m-a9-ext2f-div2";
-
- clock-div = <2>;
- clock-mult = <1>;
- };
-
- /*
- * Bootloader initialized system infrastructure clock for
- * serial devices.
- */
- clk_ext2f_a9: clockgen-c0@13 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <200000000>;
- clock-output-names = "clk-s-icn-reg-0";
- };
-
- clockgen-a@090ff000 {
+ clockgen-a@90ff000 {
compatible = "st,clkgen-c32";
reg = <0x90ff000 0x1000>;
@@ -101,6 +79,7 @@
clocks = <&clk_sysin>;
clock-output-names = "clk-s-a0-pll-ofd-0";
+ clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
};
clk_s_a0_flexgen: clk-s-a0-flexgen {
@@ -112,6 +91,7 @@
<&clk_sysin>;
clock-output-names = "clk-ic-lmi0";
+ clock-critical = <CLK_IC_LMI0>;
};
};
@@ -126,9 +106,10 @@
"clk-s-c0-fs0-ch1",
"clk-s-c0-fs0-ch2",
"clk-s-c0-fs0-ch3";
+ clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
};
- clk_s_c0: clockgen-c@09103000 {
+ clk_s_c0: clockgen-c@9103000 {
compatible = "st,clkgen-c32";
reg = <0x9103000 0x1000>;
@@ -139,6 +120,7 @@
clocks = <&clk_sysin>;
clock-output-names = "clk-s-c0-pll0-odf-0";
+ clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
};
clk_s_c0_pll1: clk-s-c0-pll1 {
@@ -194,6 +176,27 @@
"clk-main-disp",
"clk-aux-disp",
"clk-compo-dvp";
+ clock-critical = <CLK_PROC_STFE>,
+ <CLK_ICN_CPU>,
+ <CLK_TX_ICN_DMU>,
+ <CLK_EXT2F_A9>,
+ <CLK_ICN_LMI>,
+ <CLK_ICN_SBC>;
+
+ /*
+ * ARM Peripheral clock for timers
+ */
+ clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+
+ clocks = <&clk_s_c0_flexgen 13>;
+
+ clock-output-names = "clk-m-a9-ext2f-div2";
+
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
};
};
@@ -210,7 +213,7 @@
"clk-s-d0-fs0-ch3";
};
- clockgen-d0@09104000 {
+ clockgen-d0@9104000 {
compatible = "st,clkgen-c32";
reg = <0x9104000 0x1000>;
@@ -244,13 +247,7 @@
"clk-s-d2-fs0-ch3";
};
- clk_tmdsout_hdmi: clk-tmdsout-hdmi {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
-
- clockgen-d2@x9106000 {
+ clockgen-d2@9106000 {
compatible = "st,clkgen-c32";
reg = <0x9106000 0x1000>;
diff --git a/arch/arm/dts/stih407-family.dtsi b/arch/arm/dts/stih407-family.dtsi
index 6c6de58..7c36c37 100644
--- a/arch/arm/dts/stih407-family.dtsi
+++ b/arch/arm/dts/stih407-family.dtsi
@@ -1,10 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 STMicroelectronics Limited.
* Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * publishhed by the Free Software Foundation.
*/
#include "stih407-pinctrl.dtsi"
#include <dt-bindings/mfd/st-lpc.h>
@@ -20,7 +17,13 @@
#size-cells = <1>;
ranges;
- dmu_reserved: rproc@44000000 {
+ gp0_reserved: rproc@45000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x45000000 0x00400000>;
+ no-map;
+ };
+
+ delta_reserved: rproc@44000000 {
compatible = "shared-dma-pool";
reg = <0x44000000 0x01000000>;
no-map;
@@ -47,6 +50,7 @@
clocks = <&clk_m_a9>;
clock-names = "cpu";
clock-latency = <100000>;
+ cpu0-supply = <&pwm_regulator>;
st,syscfg = <&syscfg_core 0x8e0>;
};
cpu@1 {
@@ -65,19 +69,19 @@
};
};
- intc: interrupt-controller@08761000 {
+ intc: interrupt-controller@8761000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x08761000 0x1000>, <0x08760100 0x100>;
};
- scu@08760000 {
+ scu@8760000 {
compatible = "arm,cortex-a9-scu";
reg = <0x08760000 0x1000>;
};
- timer@08760200 {
+ timer@8760200 {
interrupt-parent = <&intc>;
compatible = "arm,cortex-a9-global-timer";
reg = <0x08760200 0x100>;
@@ -85,7 +89,7 @@
clocks = <&arm_periph_clk>;
};
- l2: cache-controller {
+ l2: cache-controller@8762000 {
compatible = "arm,pl310-cache";
reg = <0x08762000 0x1000>;
arm,data-latency = <3 3 3>;
@@ -118,24 +122,28 @@
ranges;
compatible = "simple-bus";
- restart {
+ restart: restart-controller@0 {
compatible = "st,stih407-restart";
+ reg = <0 0>;
st,syscfg = <&syscfg_sbc_reg>;
status = "okay";
};
- powerdown: powerdown-controller {
+ powerdown: powerdown-controller@0 {
compatible = "st,stih407-powerdown";
+ reg = <0 0>;
#reset-cells = <1>;
};
- softreset: softreset-controller {
+ softreset: softreset-controller@0 {
compatible = "st,stih407-softreset";
+ reg = <0 0>;
#reset-cells = <1>;
};
- picophyreset: picophyreset-controller {
+ picophyreset: picophyreset-controller@0 {
compatible = "st,stih407-picophyreset";
+ reg = <0 0>;
#reset-cells = <1>;
};
@@ -167,6 +175,13 @@
syscfg_core: core-syscfg@92b0000 {
compatible = "st,stih407-core-syscfg", "syscon";
reg = <0x92b0000 0x1000>;
+
+ sti_sasg_codec: sti-sasg-codec {
+ compatible = "st,stih407-sas-codec";
+ #sound-dai-cells = <1>;
+ status = "disabled";
+ st,syscfg = <&syscfg_core>;
+ };
};
syscfg_lpm: lpm-syscfg@94b5100 {
@@ -174,8 +189,9 @@
reg = <0x94b5100 0x1000>;
};
- irq-syscfg {
+ irq-syscfg@0 {
compatible = "st,stih407-irq-syscfg";
+ reg = <0 0>;
st,syscfg = <&syscfg_core>;
st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
<ST_IRQ_SYSCFG_PMU_1>;
@@ -187,22 +203,21 @@
vtg_main: sti-vtg-main@8d02800 {
compatible = "st,vtg";
reg = <0x8d02800 0x200>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
};
vtg_aux: sti-vtg-aux@8d00200 {
compatible = "st,vtg";
reg = <0x8d00200 0x100>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
};
serial@9830000 {
compatible = "st,asc";
reg = <0x9830000 0x2c>;
- interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_serial0>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
+ /* Pinctrl moved out to a per-board configuration */
status = "disabled";
};
@@ -210,7 +225,7 @@
serial@9831000 {
compatible = "st,asc";
reg = <0x9831000 0x2c>;
- interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_serial1>;
clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
@@ -221,7 +236,7 @@
serial@9832000 {
compatible = "st,asc";
reg = <0x9832000 0x2c>;
- interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_serial2>;
clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
@@ -233,7 +248,7 @@
sbc_serial0: serial@9530000 {
compatible = "st,asc";
reg = <0x9530000 0x2c>;
- interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sbc_serial0>;
clocks = <&clk_sysin>;
@@ -244,7 +259,7 @@
serial@9531000 {
compatible = "st,asc";
reg = <0x9531000 0x2c>;
- interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sbc_serial1>;
clocks = <&clk_sysin>;
@@ -374,8 +389,9 @@
status = "disabled";
};
- usb2_picophy0: phy1 {
+ usb2_picophy0: phy1@0 {
compatible = "st,stih407-usb2-phy";
+ reg = <0 0>;
#phy-cells = <0>;
st,syscfg = <&syscfg_core 0x100 0xf4>;
resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
@@ -383,12 +399,13 @@
reset-names = "global", "port";
};
- miphy28lp_phy: miphy28lp@9b22000 {
+ miphy28lp_phy: miphy28lp@0 {
compatible = "st,miphy28lp-phy";
st,syscfg = <&syscfg_core>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
+ reg = <0 0>;
phy_port0: port@9b22000 {
reg = <0x9b22000 0xff>,
@@ -458,6 +475,8 @@
clock-names = "ssc";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1_default>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
};
@@ -470,6 +489,8 @@
clock-names = "ssc";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2_default>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
};
@@ -482,6 +503,8 @@
clock-names = "ssc";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi3_default>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
};
@@ -494,6 +517,8 @@
clock-names = "ssc";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi4_default>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
};
@@ -507,6 +532,8 @@
clock-names = "ssc";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi10_default>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
};
@@ -519,6 +546,8 @@
clock-names = "ssc";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi11_default>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
};
@@ -531,16 +560,18 @@
clock-names = "ssc";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi12_default>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
};
- mmc0: sdhci@09060000 {
+ mmc0: sdhci@9060000 {
compatible = "st,sdhci-stih407", "st,sdhci";
status = "disabled";
reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
reg-names = "mmc", "top-mmc-delay";
- interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mmcirq";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc0>;
@@ -550,12 +581,12 @@
bus-width = <8>;
};
- mmc1: sdhci@09080000 {
+ mmc1: sdhci@9080000 {
compatible = "st,sdhci-stih407", "st,sdhci";
status = "disabled";
reg = <0x09080000 0x7ff>;
reg-names = "mmc";
- interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mmcirq";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sd1>;
@@ -563,7 +594,6 @@
clocks = <&clk_s_c0_flexgen CLK_MMC_1>,
<&clk_s_c0_flexgen CLK_RX_ICN_HVA>;
resets = <&softreset STIH407_MMC1_SOFTRESET>;
- reset-names = "softreset";
bus-width = <4>;
};
@@ -590,7 +620,7 @@
compatible = "st,ahci";
reg = <0x9b20000 0x1000>;
- interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hostc";
phys = <&phy_port0 PHY_TYPE_SATA>;
@@ -613,7 +643,7 @@
compatible = "st,ahci";
reg = <0x9b28000 0x1000>;
- interrupts = <GIC_SPI 170 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hostc";
phys = <&phy_port1 PHY_TYPE_SATA>;
@@ -654,11 +684,12 @@
dwc3: dwc3@9900000 {
compatible = "snps,dwc3";
reg = <0x09900000 0x100000>;
- interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>;
- dr_mode = "peripheral";
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
phy-names = "usb2-phy", "usb3-phy";
phys = <&usb2_picophy0>,
<&phy_port2 PHY_TYPE_USB3>;
+ snps,dis_u3_susphy_quirk;
};
};
@@ -667,7 +698,7 @@
compatible = "st,sti-pwm";
#pwm-cells = <2>;
reg = <0x9810000 0x68>;
- interrupts = <GIC_SPI 128 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_chan0_default>;
clock-names = "pwm";
@@ -682,6 +713,7 @@
compatible = "st,sti-pwm";
#pwm-cells = <2>;
reg = <0x9510000 0x68>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1_chan0_default
&pinctrl_pwm1_chan1_default
@@ -694,14 +726,14 @@
status = "disabled";
};
- rng10: rng@08a89000 {
+ rng10: rng@8a89000 {
compatible = "st,rng";
reg = <0x08a89000 0x1000>;
clocks = <&clk_sysin>;
status = "okay";
};
- rng11: rng@08a8a000 {
+ rng11: rng@8a8a000 {
compatible = "st,rng";
reg = <0x08a8a000 0x1000>;
clocks = <&clk_sysin>;
@@ -720,8 +752,8 @@
resets = <&softreset STIH407_ETH1_SOFTRESET>;
reset-names = "stmmaceth";
- interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>,
- <GIC_SPI 99 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_wake_irq";
/* DMA Bus Mode */
@@ -735,26 +767,14 @@
<&clk_s_c0_flexgen CLK_ETH_PHY>;
};
- cec: sti-cec@094a087c {
- compatible = "st,stih-cec";
- reg = <0x94a087c 0x64>;
- clocks = <&clk_sysin>;
- clock-names = "cec-clk";
- interrupts = <GIC_SPI 140 IRQ_TYPE_NONE>;
- interrupt-names = "cec-irq";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_cec0_default>;
- resets = <&softreset STIH407_LPM_SOFTRESET>;
- };
-
- rng10: rng@08a89000 {
+ rng10: rng@8a89000 {
compatible = "st,rng";
reg = <0x08a89000 0x1000>;
clocks = <&clk_sysin>;
status = "okay";
};
- rng11: rng@08a8a000 {
+ rng11: rng@8a8a000 {
compatible = "st,rng";
reg = <0x08a8a000 0x1000>;
clocks = <&clk_sysin>;
@@ -764,7 +784,7 @@
mailbox0: mailbox@8f00000 {
compatible = "st,stih407-mailbox";
reg = <0x8f00000 0x1000>;
- interrupts = <GIC_SPI 1 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
mbox-name = "a9";
status = "okay";
@@ -794,9 +814,24 @@
status = "okay";
};
- st231_delta: st231-delta@44000000 {
+ st231_gp0: st231-gp0@0 {
compatible = "st,st231-rproc";
- memory-region = <&dmu_reserved>;
+ reg = <0 0>;
+ memory-region = <&gp0_reserved>;
+ resets = <&softreset STIH407_ST231_GP0_SOFTRESET>;
+ reset-names = "sw_reset";
+ clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>;
+ clock-frequency = <600000000>;
+ st,syscfg = <&syscfg_core 0x22c>;
+ #mbox-cells = <1>;
+ mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
+ mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>;
+ };
+
+ st231_delta: st231-delta@0 {
+ compatible = "st,st231-rproc";
+ reg = <0 0>;
+ memory-region = <&delta_reserved>;
resets = <&softreset STIH407_ST231_DMU_SOFTRESET>;
reset-names = "sw_reset";
clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>;
@@ -819,7 +854,7 @@
<&clk_s_c0_flexgen CLK_EXT2F_A9>,
<&clk_s_c0_flexgen CLK_EXT2F_A9>,
<&clk_s_c0_flexgen CLK_EXT2F_A9>;
- interrupts = <GIC_SPI 5 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <16>;
#dma-cells = <3>;
};
@@ -837,9 +872,11 @@
<&clk_s_c0_flexgen CLK_TX_ICN_DMU>,
<&clk_s_c0_flexgen CLK_EXT2F_A9>;
- interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <16>;
#dma-cells = <3>;
+
+ status = "disabled";
};
/* fdma free running */
@@ -850,20 +887,15 @@
<0x8e77000 0x1000>,
<0x8e78000 0x8000>;
reg-names = "slimcore", "dmem", "peripherals", "imem";
- interrupts = <GIC_SPI 9 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <16>;
#dma-cells = <3>;
clocks = <&clk_s_c0_flexgen CLK_FDMA>,
<&clk_s_c0_flexgen CLK_EXT2F_A9>,
<&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
<&clk_s_c0_flexgen CLK_EXT2F_A9>;
- };
- sti_sasg_codec: sti-sasg-codec {
- compatible = "st,stih407-sas-codec";
- #sound-dai-cells = <1>;
status = "disabled";
- st,syscfg = <&syscfg_core>;
};
sti_uni_player0: sti-uni-player@8d80000 {
@@ -875,7 +907,7 @@
assigned-clock-parents = <0>, <&clk_s_d0_quadfs 0>;
assigned-clock-rates = <50000000>;
reg = <0x8d80000 0x158>;
- interrupts = <GIC_SPI 84 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&fdma0 2 0 1>;
dma-names = "tx";
@@ -891,7 +923,7 @@
assigned-clock-parents = <0>, <&clk_s_d0_quadfs 1>;
assigned-clock-rates = <50000000>;
reg = <0x8d81000 0x158>;
- interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&fdma0 3 0 1>;
dma-names = "tx";
@@ -907,7 +939,7 @@
assigned-clock-parents = <0>, <&clk_s_d0_quadfs 2>;
assigned-clock-rates = <50000000>;
reg = <0x8d82000 0x158>;
- interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&fdma0 4 0 1>;
dma-names = "tx";
@@ -923,7 +955,7 @@
assigned-clock-parents = <0>, <&clk_s_d0_quadfs 3>;
assigned-clock-rates = <50000000>;
reg = <0x8d85000 0x158>;
- interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&fdma0 7 0 1>;
dma-names = "tx";
@@ -935,7 +967,7 @@
#sound-dai-cells = <0>;
st,syscfg = <&syscfg_core>;
reg = <0x8d83000 0x158>;
- interrupts = <GIC_SPI 87 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&fdma0 5 0 1>;
dma-names = "rx";
@@ -947,32 +979,22 @@
#sound-dai-cells = <0>;
st,syscfg = <&syscfg_core>;
reg = <0x8d84000 0x158>;
- interrupts = <GIC_SPI 88 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&fdma0 6 0 1>;
dma-names = "rx";
status = "disabled";
};
- rc: rc@09518000 {
- compatible = "st,comms-irb";
- reg = <0x09518000 0x234>;
- interrupts = <GIC_SPI 132 IRQ_TYPE_NONE>;
- rx-mode = "infrared";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ir
- &pinctrl_uhf
- &pinctrl_tx
- &pinctrl_tx_od>;
- clocks = <&clk_sysin>;
- resets = <&softreset STIH407_IRB_SOFTRESET>;
-
- status = "disabled";
- };
-
- socinfo {
- compatible = "st,stih407-socinfo";
- st,syscfg = <&syscfg_core>;
+ delta0@0 {
+ compatible = "st,st-delta";
+ reg = <0 0>;
+ clock-names = "delta",
+ "delta-st231",
+ "delta-flash-promip";
+ clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
+ <&clk_s_c0_flexgen CLK_ST231_DMU>,
+ <&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
};
};
};
diff --git a/arch/arm/dts/stih407-pinctrl.dtsi b/arch/arm/dts/stih407-pinctrl.dtsi
index f27ae21..2cf3357 100644
--- a/arch/arm/dts/stih407-pinctrl.dtsi
+++ b/arch/arm/dts/stih407-pinctrl.dtsi
@@ -1,10 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 STMicroelectronics Limited.
* Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * publishhed by the Free Software Foundation.
*/
#include "st-pincfg.h"
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -45,18 +42,18 @@
};
soc {
- pin-controller-sbc {
+ pin-controller-sbc@961f080 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stih407-sbc-pinctrl";
st,syscfg = <&syscfg_sbc>;
reg = <0x0961f080 0x4>;
reg-names = "irqmux";
- interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irqmux";
ranges = <0 0x09610000 0x6000>;
- pio0: gpio@09610000 {
+ pio0: gpio@9610000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -64,7 +61,7 @@
reg = <0x0 0x100>;
st,bank-name = "PIO0";
};
- pio1: gpio@09611000 {
+ pio1: gpio@9611000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -72,7 +69,7 @@
reg = <0x1000 0x100>;
st,bank-name = "PIO1";
};
- pio2: gpio@09612000 {
+ pio2: gpio@9612000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -80,7 +77,7 @@
reg = <0x2000 0x100>;
st,bank-name = "PIO2";
};
- pio3: gpio@09613000 {
+ pio3: gpio@9613000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -88,7 +85,7 @@
reg = <0x3000 0x100>;
st,bank-name = "PIO3";
};
- pio4: gpio@09614000 {
+ pio4: gpio@9614000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -97,7 +94,7 @@
st,bank-name = "PIO4";
};
- pio5: gpio@09615000 {
+ pio5: gpio@9615000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -369,18 +366,18 @@
};
};
- pin-controller-front0 {
+ pin-controller-front0@920f080 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stih407-front-pinctrl";
st,syscfg = <&syscfg_front>;
reg = <0x0920f080 0x4>;
reg-names = "irqmux";
- interrupts = <GIC_SPI 189 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irqmux";
ranges = <0 0x09200000 0x10000>;
- pio10: pio@09200000 {
+ pio10: pio@9200000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -388,7 +385,7 @@
reg = <0x0 0x100>;
st,bank-name = "PIO10";
};
- pio11: pio@09201000 {
+ pio11: pio@9201000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -396,7 +393,7 @@
reg = <0x1000 0x100>;
st,bank-name = "PIO11";
};
- pio12: pio@09202000 {
+ pio12: pio@9202000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -404,7 +401,7 @@
reg = <0x2000 0x100>;
st,bank-name = "PIO12";
};
- pio13: pio@09203000 {
+ pio13: pio@9203000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -412,7 +409,7 @@
reg = <0x3000 0x100>;
st,bank-name = "PIO13";
};
- pio14: pio@09204000 {
+ pio14: pio@9204000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -420,7 +417,7 @@
reg = <0x4000 0x100>;
st,bank-name = "PIO14";
};
- pio15: pio@09205000 {
+ pio15: pio@9205000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -428,7 +425,7 @@
reg = <0x5000 0x100>;
st,bank-name = "PIO15";
};
- pio16: pio@09206000 {
+ pio16: pio@9206000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -436,7 +433,7 @@
reg = <0x6000 0x100>;
st,bank-name = "PIO16";
};
- pio17: pio@09207000 {
+ pio17: pio@9207000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -444,7 +441,7 @@
reg = <0x7000 0x100>;
st,bank-name = "PIO17";
};
- pio18: pio@09208000 {
+ pio18: pio@9208000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -452,7 +449,7 @@
reg = <0x8000 0x100>;
st,bank-name = "PIO18";
};
- pio19: pio@09209000 {
+ pio19: pio@9209000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -465,19 +462,16 @@
serial0 {
pinctrl_serial0: serial0-0 {
st,pins {
- tx = <&pio17 0 ALT1 OUT>;
- rx = <&pio17 1 ALT1 IN>;
+ tx = <&pio17 0 ALT1 OUT>;
+ rx = <&pio17 1 ALT1 IN>;
};
};
- pinctrl_serial0_rts: serial0_rts {
+ pinctrl_serial0_hw_flowctrl: serial0-0_hw_flowctrl {
st,pins {
- rts = <&pio17 3 ALT1 OUT>;
- };
- };
-
- pinctrl_serial0_cts: serial0_cts {
- st,pins {
+ tx = <&pio17 0 ALT1 OUT>;
+ rx = <&pio17 1 ALT1 IN>;
cts = <&pio17 2 ALT1 IN>;
+ rts = <&pio17 3 ALT1 OUT>;
};
};
};
@@ -932,18 +926,18 @@
};
};
- pin-controller-front1 {
+ pin-controller-front1@921f080 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stih407-front-pinctrl";
st,syscfg = <&syscfg_front>;
reg = <0x0921f080 0x4>;
reg-names = "irqmux";
- interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irqmux";
ranges = <0 0x09210000 0x10000>;
- pio20: pio@09210000 {
+ pio20: pio@9210000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -965,18 +959,18 @@
};
};
- pin-controller-rear {
+ pin-controller-rear@922f080 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stih407-rear-pinctrl";
st,syscfg = <&syscfg_rear>;
reg = <0x0922f080 0x4>;
reg-names = "irqmux";
- interrupts = <GIC_SPI 191 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irqmux";
ranges = <0 0x09220000 0x6000>;
- pio30: gpio@09220000 {
+ pio30: gpio@9220000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -984,7 +978,7 @@
reg = <0x0 0x100>;
st,bank-name = "PIO30";
};
- pio31: gpio@09221000 {
+ pio31: gpio@9221000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -992,7 +986,7 @@
reg = <0x1000 0x100>;
st,bank-name = "PIO31";
};
- pio32: gpio@09222000 {
+ pio32: gpio@9222000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -1000,7 +994,7 @@
reg = <0x2000 0x100>;
st,bank-name = "PIO32";
};
- pio33: gpio@09223000 {
+ pio33: gpio@9223000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -1008,7 +1002,7 @@
reg = <0x3000 0x100>;
st,bank-name = "PIO33";
};
- pio34: gpio@09224000 {
+ pio34: gpio@9224000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -1016,7 +1010,7 @@
reg = <0x4000 0x100>;
st,bank-name = "PIO34";
};
- pio35: gpio@09225000 {
+ pio35: gpio@9225000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -1026,41 +1020,6 @@
st,retime-pin-mask = <0x7f>;
};
- dvo {
- pinctrl_dvo: dvo {
- st,pins {
- hs = <&pio30 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
- vs = <&pio30 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
- de = <&pio30 2 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
- ck = <&pio30 3 ALT2 (OE | CLKNOTDATA) 0>;
- d0 = <&pio30 4 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
- d1 = <&pio30 5 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
- d2 = <&pio30 6 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
- d3 = <&pio30 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
- d4 = <&pio31 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
- d5 = <&pio31 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
- d6 = <&pio31 2 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
- d7 = <&pio31 3 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
- d8 = <&pio31 4 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
- d9 = <&pio31 5 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
- d10 = <&pio31 6 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
- d11 = <&pio31 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
- d12 = <&pio32 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
- d13 = <&pio32 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
- d14 = <&pio32 2 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
- d15 = <&pio32 3 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
- d16 = <&pio32 4 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
- d17 = <&pio32 5 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
- d18 = <&pio32 6 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
- d19 = <&pio32 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
- d20 = <&pio33 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
- d21 = <&pio33 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
- d22 = <&pio33 2 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
- d23 = <&pio33 3 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
- };
- };
- };
-
i2c4 {
pinctrl_i2c4_default: i2c4-default {
st,pins {
@@ -1195,18 +1154,18 @@
};
};
- pin-controller-flash {
+ pin-controller-flash@923f080 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stih407-flash-pinctrl";
st,syscfg = <&syscfg_flash>;
reg = <0x0923f080 0x4>;
reg-names = "irqmux";
- interrupts = <GIC_SPI 192 IRQ_TYPE_NONE>;
- interrupts-names = "irqmux";
+ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irqmux";
ranges = <0 0x09230000 0x3000>;
- pio40: gpio@09230000 {
+ pio40: gpio@9230000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -1214,7 +1173,7 @@
reg = <0 0x100>;
st,bank-name = "PIO40";
};
- pio41: gpio@09231000 {
+ pio41: gpio@9231000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -1222,7 +1181,7 @@
reg = <0x1000 0x100>;
st,bank-name = "PIO41";
};
- pio42: gpio@09232000 {
+ pio42: gpio@9232000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
diff --git a/arch/arm/dts/stih410-b2260-u-boot.dtsi b/arch/arm/dts/stih410-b2260-u-boot.dtsi
index 8391631..897c421 100644
--- a/arch/arm/dts/stih410-b2260-u-boot.dtsi
+++ b/arch/arm/dts/stih410-b2260-u-boot.dtsi
@@ -9,8 +9,25 @@
soc {
st_dwc3: dwc3@8f94000 {
dwc3: dwc3@9900000 {
+ dr_mode = "peripheral";
phys = <&usb2_picophy0>;
};
};
+
+ ohci0: usb@9a03c00 {
+ compatible = "generic-ohci";
+ };
+
+ ehci0: usb@9a03e00 {
+ compatible = "generic-ehci";
+ };
+
+ ohci1: usb@9a83c00 {
+ compatible = "generic-ohci";
+ };
+
+ ehci1: usb@9a83e00 {
+ compatible = "generic-ehci";
+ };
};
};
diff --git a/arch/arm/dts/stih410-b2260.dts b/arch/arm/dts/stih410-b2260.dts
index 54250e2..4fbd8e9 100644
--- a/arch/arm/dts/stih410-b2260.dts
+++ b/arch/arm/dts/stih410-b2260.dts
@@ -1,10 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2016 STMicroelectronics (R&D) Limited.
* Author: Patrice Chotard <patrice.chotard@st.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
*/
/dts-v1/;
#include "stih410.dtsi"
@@ -15,68 +12,79 @@
compatible = "st,stih410-b2260", "st,stih410";
chosen {
- bootargs = "console=ttyAS1,115200";
- linux,stdout-path = &uart1;
+ bootargs = "clk_ignore_unused";
stdout-path = &uart1;
};
- memory {
+ memory@40000000 {
device_type = "memory";
reg = <0x40000000 0x40000000>;
};
aliases {
- ttyAS1 = &uart1;
+ serial1 = &uart1;
ethernet0 = ðernet0;
};
- soc {
-
- leds {
- compatible = "gpio-leds";
- user_green_1 {
- label = "User_green_1";
- gpios = <&pio1 3 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "heartbeat";
- default-state = "off";
- };
-
- user_green_2 {
- label = "User_green_2";
- gpios = <&pio4 1 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- user_green_3 {
- label = "User_green_3";
- gpios = <&pio2 1 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- user_green_4 {
- label = "User_green_4";
- gpios = <&pio2 5 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- wifi_yellow {
- label = "Wifi_yellow";
- gpios = <&pio4 0 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "wifi-activity";
- default-state = "off";
- };
-
- bt_blue {
- label = "Bluetooth_blue";
- gpios = <&pio3 3 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "hci0-power";
- default-state = "off";
- };
+ leds {
+ compatible = "gpio-leds";
+ user_green_1 {
+ label = "User_green_1";
+ gpios = <&pio1 3 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
};
+ user_green_2 {
+ label = "User_green_2";
+ gpios = <&pio4 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ user_green_3 {
+ label = "User_green_3";
+ gpios = <&pio2 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ user_green_4 {
+ label = "User_green_4";
+ gpios = <&pio2 5 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ };
+
+ sound: sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "STI-B2260";
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ simple-audio-card,dai-link@0 {
+ reg = <0>;
+ /* DAC */
+ format = "i2s";
+ mclk-fs = <128>;
+ cpu {
+ sound-dai = <&sti_uni_player0>;
+ };
+
+ codec {
+ sound-dai = <&sti_hdmi>;
+ };
+ };
+ };
+
+ soc {
/* Low speed expansion connector */
uart0: serial@9830000 {
label = "LS-UART0";
+ pinctrl-names = "default", "no-hw-flowctrl";
+ pinctrl-0 = <&pinctrl_serial0_hw_flowctrl>;
+ pinctrl-1 = <&pinctrl_serial0>;
+ rts-gpios = <&pio17 3 GPIO_ACTIVE_LOW>;
+ uart-has-rtscts;
status = "okay";
};
@@ -119,14 +127,14 @@
status = "okay";
};
- mmc0: sdhci@09060000 {
+ mmc0: sdhci@9060000 {
pinctrl-0 = <&pinctrl_sd0>;
bus-width = <4>;
status = "okay";
};
/* high speed expansion connector */
- mmc1: sdhci@09080000 {
+ mmc1: sdhci@9080000 {
status = "okay";
};
@@ -138,11 +146,11 @@
status = "okay";
};
- usb2_picophy1: phy2 {
+ usb2_picophy1: phy2@0 {
status = "okay";
};
- usb2_picophy2: phy3 {
+ usb2_picophy2: phy3@0 {
status = "okay";
};
@@ -183,17 +191,17 @@
sti_uni_player0: sti-uni-player@8d80000 {
status = "okay";
};
-
/* SSC11 to HDMI */
hdmiddc: i2c@9541000 {
/* HDMI V1.3a supports Standard mode only */
clock-frequency = <100000>;
st,i2c-min-scl-pulse-width-us = <0>;
- st,i2c-min-sda-pulse-width-us = <1>;
+ st,i2c-min-sda-pulse-width-us = <5>;
status = "okay";
};
- miphy28lp_phy: miphy28lp@9b22000 {
+ miphy28lp_phy: miphy28lp@0 {
+
phy_port1: port@9b2a000 {
st,osc-force-ext;
};
@@ -202,25 +210,5 @@
sata1: sata@9b28000 {
status = "okay";
};
-
- sound {
- compatible = "simple-audio-card";
- simple-audio-card,name = "STI-B2260";
- status = "okay";
-
- simple-audio-card,dai-link@0 {
- /* DAC */
- format = "i2s";
- mclk-fs = <128>;
- cpu {
- sound-dai = <&sti_uni_player0>;
- };
-
- codec {
- sound-dai = <&sti_hdmi>;
- };
- };
- };
-
};
};
diff --git a/arch/arm/dts/stih410-clock.dtsi b/arch/arm/dts/stih410-clock.dtsi
index 8598eff..81a8c25 100644
--- a/arch/arm/dts/stih410-clock.dtsi
+++ b/arch/arm/dts/stih410-clock.dtsi
@@ -1,12 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 STMicroelectronics R&D Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
*/
#include <dt-bindings/clock/stih410-clks.h>
/ {
+ /*
+ * Fixed 30MHz oscillator inputs to SoC
+ */
+ clk_sysin: clk-sysin {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <30000000>;
+ clock-output-names = "CLK_SYSIN";
+ };
+
+ clk_tmdsout_hdmi: clk-tmdsout-hdmi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
clocks {
#address-cells = <1>;
#size-cells = <1>;
@@ -15,27 +28,6 @@
compatible = "st,stih410-clk", "simple-bus";
/*
- * Fixed 30MHz oscillator inputs to SoC
- */
- clk_sysin: clk-sysin {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <30000000>;
- clock-output-names = "CLK_SYSIN";
- };
-
- /*
- * ARM Peripheral clock for timers
- */
- arm_periph_clk: clk-m-a9-periphs {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&clk_m_a9>;
- clock-div = <2>;
- clock-mult = <1>;
- };
-
- /*
* A9 PLL.
*/
clockgen-a9@92b0000 {
@@ -64,35 +56,19 @@
<&clockgen_a9_pll 0>,
<&clk_s_c0_flexgen 13>,
<&clk_m_a9_ext2f_div2>;
+ /*
+ * ARM Peripheral clock for timers
+ */
+ arm_periph_clk: clk-m-a9-periphs {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_m_a9>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
};
- /*
- * ARM Peripheral clock for timers
- */
- clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
-
- clocks = <&clk_s_c0_flexgen 13>;
-
- clock-output-names = "clk-m-a9-ext2f-div2";
-
- clock-div = <2>;
- clock-mult = <1>;
- };
-
- /*
- * Bootloader initialized system infrastructure clock for
- * serial devices.
- */
- clk_ext2f_a9: clockgen-c0@13 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <200000000>;
- clock-output-names = "clk-s-icn-reg-0";
- };
-
- clockgen-a@090ff000 {
+ clockgen-a@90ff000 {
compatible = "st,clkgen-c32";
reg = <0x90ff000 0x1000>;
@@ -134,7 +110,7 @@
clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
};
- clk_s_c0: clockgen-c@09103000 {
+ clk_s_c0: clockgen-c@9103000 {
compatible = "st,clkgen-c32";
reg = <0x9103000 0x1000>;
@@ -208,11 +184,27 @@
"clk-clust-hades",
"clk-hwpe-hades",
"clk-fc-hades";
- clock-critical = <CLK_ICN_CPU>,
+ clock-critical = <CLK_PROC_STFE>,
+ <CLK_ICN_CPU>,
<CLK_TX_ICN_DMU>,
<CLK_EXT2F_A9>,
<CLK_ICN_LMI>,
<CLK_ICN_SBC>;
+
+ /*
+ * ARM Peripheral clock for timers
+ */
+ clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+
+ clocks = <&clk_s_c0_flexgen 13>;
+
+ clock-output-names = "clk-m-a9-ext2f-div2";
+
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
};
};
@@ -229,7 +221,7 @@
"clk-s-d0-fs0-ch3";
};
- clockgen-d0@09104000 {
+ clockgen-d0@9104000 {
compatible = "st,clkgen-c32";
reg = <0x9104000 0x1000>;
@@ -265,13 +257,7 @@
"clk-s-d2-fs0-ch3";
};
- clk_tmdsout_hdmi: clk-tmdsout-hdmi {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
-
- clockgen-d2@x9106000 {
+ clockgen-d2@9106000 {
compatible = "st,clkgen-c32";
reg = <0x9106000 0x1000>;
diff --git a/arch/arm/dts/stih410-pinctrl.dtsi b/arch/arm/dts/stih410-pinctrl.dtsi
index b3e9dfc..e6eadd1 100644
--- a/arch/arm/dts/stih410-pinctrl.dtsi
+++ b/arch/arm/dts/stih410-pinctrl.dtsi
@@ -1,16 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 STMicroelectronics Limited.
* Author: Peter Griffin <peter.griffin@linaro.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * publishhed by the Free Software Foundation.
*/
#include "st-pincfg.h"
/ {
soc {
- pin-controller-rear {
+ pin-controller-rear@922f080 {
usb0 {
pinctrl_usb0: usb2-0 {
diff --git a/arch/arm/dts/stih410.dtsi b/arch/arm/dts/stih410.dtsi
index b59b110..6d84701 100644
--- a/arch/arm/dts/stih410.dtsi
+++ b/arch/arm/dts/stih410.dtsi
@@ -1,67 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 STMicroelectronics Limited.
* Author: Peter Griffin <peter.griffin@linaro.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * publishhed by the Free Software Foundation.
*/
#include "stih410-clock.dtsi"
#include "stih407-family.dtsi"
#include "stih410-pinctrl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
/ {
aliases {
bdisp0 = &bdisp0;
};
- cpus {
- cpu@0 {
- st,syscfg = <&syscfg_core 0x8e0>;
- st,syscfg-eng = <&syscfg_opp 0x4 0x0>;
- clocks = <&clk_m_a9>;
- operating-points-v2 = <&cpu0_opp_table>;
- };
- cpu@1 {
- clocks = <&clk_m_a9>;
- operating-points-v2 = <&cpu0_opp_table>;
- };
- };
-
- cpu0_opp_table: opp_table0 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp@1500000000 {
- opp-supported-hw = <0xffffffff 0xffffffff 0xffffffff>;
- opp-hz = /bits/ 64 <1500000000>;
- clock-latency-ns = <10000000>;
- opp-suspend;
- };
- opp@1200000000 {
- opp-supported-hw = <0xffffffff 0xffffffff 0xffffffff>;
- opp-hz = /bits/ 64 <1200000000>;
- clock-latency-ns = <10000000>;
- };
- opp@800000000 {
- opp-supported-hw = <0xffffffff 0xffffffff 0xffffffff>;
- opp-hz = /bits/ 64 <800000000>;
- clock-latency-ns = <10000000>;
- };
- opp@400000000 {
- opp-supported-hw = <0xffffffff 0xffffffff 0xffffffff>;
- opp-hz = /bits/ 64 <400000000>;
- clock-latency-ns = <10000000>;
- };
- };
-
soc {
- syscfg_opp: @08a6583c {
- compatible = "syscon";
- reg = <0x08a6583c 0x8>;
- };
-
- usb2_picophy1: phy2 {
+ usb2_picophy1: phy2@0 {
compatible = "st,stih407-usb2-phy";
+ reg = <0 0>;
#phy-cells = <0>;
st,syscfg = <&syscfg_core 0xf8 0xf4>;
resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
@@ -71,8 +25,9 @@
status = "disabled";
};
- usb2_picophy2: phy3 {
+ usb2_picophy2: phy3@0 {
compatible = "st,stih407-usb2-phy";
+ reg = <0 0>;
#phy-cells = <0>;
st,syscfg = <&syscfg_core 0xfc 0xf4>;
resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
@@ -83,15 +38,14 @@
};
ohci0: usb@9a03c00 {
- compatible = "generic-ohci";
+ compatible = "st,st-ohci-300x";
reg = <0x9a03c00 0x100>;
- interrupts = <GIC_SPI 180 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
<&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
<&softreset STIH407_USB2_PORT0_SOFTRESET>;
reset-names = "power", "softreset";
-
phys = <&usb2_picophy1>;
phy-names = "usb";
@@ -99,9 +53,9 @@
};
ehci0: usb@9a03e00 {
- compatible = "generic-ehci";
+ compatible = "st,st-ehci-300x";
reg = <0x9a03e00 0x100>;
- interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
@@ -116,15 +70,14 @@
};
ohci1: usb@9a83c00 {
- compatible = "generic-ohci";
+ compatible = "st,st-ohci-300x";
reg = <0x9a83c00 0x100>;
- interrupts = <GIC_SPI 181 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
<&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
<&softreset STIH407_USB2_PORT1_SOFTRESET>;
reset-names = "power", "softreset";
-
phys = <&usb2_picophy2>;
phy-names = "usb";
@@ -132,9 +85,9 @@
};
ehci1: usb@9a83e00 {
- compatible = "generic-ehci";
+ compatible = "st,st-ehci-300x";
reg = <0x9a83e00 0x100>;
- interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
@@ -142,18 +95,18 @@
resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
<&softreset STIH407_USB2_PORT1_SOFTRESET>;
reset-names = "power", "softreset";
-
phys = <&usb2_picophy2>;
phy-names = "usb";
status = "disabled";
};
- sti-display-subsystem {
+ sti-display-subsystem@0 {
compatible = "st,sti-display-subsystem";
#address-cells = <1>;
#size-cells = <1>;
+ reg = <0 0>;
assigned-clocks = <&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 1>,
<&clk_s_c0_pll1 0>,
@@ -243,10 +196,10 @@
sti_hdmi: sti-hdmi@8d04000 {
compatible = "st,stih407-hdmi";
- #sound-dai-cells = <0>;
reg = <0x8d04000 0x1000>;
reg-names = "hdmi-reg";
- interrupts = <GIC_SPI 106 IRQ_TYPE_NONE>;
+ #sound-dai-cells = <0>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq";
clock-names = "pix",
"tmds",
@@ -262,7 +215,7 @@
<&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 1>;
- hdmi,hpd-gpio = <&pio5 3>;
+ hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>;
reset-names = "hdmi";
resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
ddc = <&hdmiddc>;
@@ -283,24 +236,7 @@
<&clk_s_d2_quadfs 1>;
};
- sti-dvo@8d00400 {
- compatible = "st,stih407-dvo";
- status = "disabled";
- reg = <0x8d00400 0x200>;
- reg-names = "dvo-reg";
- clock-names = "dvo_pix",
- "dvo",
- "main_parent",
- "aux_parent";
- clocks = <&clk_s_d2_flexgen CLK_PIX_DVO>,
- <&clk_s_d2_flexgen CLK_DVO>,
- <&clk_s_d2_quadfs 0>,
- <&clk_s_d2_quadfs 1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_dvo>;
- };
-
- sti-hqvdp@9c000000 {
+ sti-hqvdp@9c00000 {
compatible = "st,stih407-hqvdp";
reg = <0x9C00000 0x100000>;
clock-names = "hqvdp", "pix_main";
@@ -315,7 +251,7 @@
bdisp0:bdisp@9f10000 {
compatible = "st,stih407-bdisp";
reg = <0x9f10000 0x1000>;
- interrupts = <GIC_SPI 38 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "bdisp";
clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>;
};
@@ -324,8 +260,8 @@
compatible = "st,st-hva";
reg = <0x8c85000 0x400>, <0x6000000 0x40000>;
reg-names = "hva_registers", "hva_esram";
- interrupts = <GIC_SPI 58 IRQ_TYPE_NONE>,
- <GIC_SPI 59 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "clk_hva";
clocks = <&clk_s_c0_flexgen CLK_HVA>;
};
@@ -338,66 +274,7 @@
interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
};
- g1@8c80000 {
- compatible = "st,g1";
- reg = <0x8c80000 0x194>;
- interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
- };
-
- temp0{
- compatible = "st,stih407-thermal";
- reg = <0x91a0000 0x28>;
- clock-names = "thermal";
- clocks = <&clk_sysin>;
- interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
- };
-
- delta0 {
- compatible = "st,delta";
- clock-names = "delta", "delta-st231", "delta-flash-promip";
- clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
- <&clk_s_c0_flexgen CLK_ST231_DMU>,
- <&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
- };
-
- h264pp0: h264pp@8c00000 {
- compatible = "st,h264pp";
- reg = <0x8c00000 0x20000>;
- interrupts = <GIC_SPI 53 IRQ_TYPE_NONE>;
- clock-names = "clk_h264pp_0";
- clocks = <&clk_s_c0_flexgen CLK_PP_DMU>;
- };
-
- mali: mali@09f00000 {
- compatible = "arm,mali-400";
- reg = <0x09f00000 0x10000>;
- interrupts = <GIC_SPI 49 IRQ_TYPE_NONE>,
- <GIC_SPI 50 IRQ_TYPE_NONE>,
- <GIC_SPI 41 IRQ_TYPE_NONE>,
- <GIC_SPI 45 IRQ_TYPE_NONE>,
- <GIC_SPI 42 IRQ_TYPE_NONE>,
- <GIC_SPI 46 IRQ_TYPE_NONE>,
- <GIC_SPI 43 IRQ_TYPE_NONE>,
- <GIC_SPI 47 IRQ_TYPE_NONE>,
- <GIC_SPI 44 IRQ_TYPE_NONE>,
- <GIC_SPI 48 IRQ_TYPE_NONE>;
- interrupt-names = "IRQGP",
- "IRQGPMMU",
- "IRQPP0",
- "IRQPPMMU0",
- "IRQPP1",
- "IRQPPMMU1",
- "IRQPP2",
- "IRQPPMMU2",
- "IRQPP3",
- "IRQPPMMU3";
- clock-names = "gpu-clk";
- clocks = <&clk_s_c0_flexgen CLK_ICN_GPU>;
- reset-names = "gpu";
- resets = <&softreset STIH407_GPU_SOFTRESET>;
- };
-
- delta0 {
+ delta0@0 {
compatible = "st,st-delta";
clock-names = "delta",
"delta-st231",
@@ -407,51 +284,17 @@
<&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
};
- h264pp0: h264pp@8c00000 {
- compatible = "st,h264pp";
- reg = <0x8c00000 0x20000>;
- interrupts = <GIC_SPI 53 IRQ_TYPE_NONE>;
- clock-names = "clk_h264pp_0";
- clocks = <&clk_s_c0_flexgen CLK_PP_DMU>;
- };
-
- mali: mali@09f00000 {
- compatible = "arm,mali-400";
- reg = <0x09f00000 0x10000>;
- interrupts = <GIC_SPI 49 IRQ_TYPE_NONE>,
- <GIC_SPI 50 IRQ_TYPE_NONE>,
- <GIC_SPI 41 IRQ_TYPE_NONE>,
- <GIC_SPI 45 IRQ_TYPE_NONE>,
- <GIC_SPI 42 IRQ_TYPE_NONE>,
- <GIC_SPI 46 IRQ_TYPE_NONE>,
- <GIC_SPI 43 IRQ_TYPE_NONE>,
- <GIC_SPI 47 IRQ_TYPE_NONE>,
- <GIC_SPI 44 IRQ_TYPE_NONE>,
- <GIC_SPI 48 IRQ_TYPE_NONE>;
- interrupt-names = "IRQGP",
- "IRQGPMMU",
- "IRQPP0",
- "IRQPPMMU0",
- "IRQPP1",
- "IRQPPMMU1",
- "IRQPP2",
- "IRQPPMMU2",
- "IRQPP3",
- "IRQPPMMU3";
- clock-names = "gpu-clk";
- clocks = <&clk_s_c0_flexgen CLK_ICN_GPU>;
- reset-names = "gpu";
- resets = <&softreset STIH407_GPU_SOFTRESET>;
- };
-
- hva@8c85000{
- compatible = "st,st-hva";
- reg = <0x8c85000 0x400>, <0x6000000 0x40000>;
- reg-names = "hva_registers", "hva_esram";
- interrupts = <GIC_SPI 58 IRQ_TYPE_NONE>,
- <GIC_SPI 59 IRQ_TYPE_NONE>;
- clock-names = "clk_hva";
- clocks = <&clk_s_c0_flexgen CLK_HVA>;
+ sti-cec@94a087c {
+ compatible = "st,stih-cec";
+ reg = <0x94a087c 0x64>;
+ clocks = <&clk_sysin>;
+ clock-names = "cec-clk";
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cec-irq";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_cec0_default>;
+ resets = <&softreset STIH407_LPM_SOFTRESET>;
+ hdmi-phandle = <&sti_hdmi>;
};
};
};
diff --git a/arch/arm/dts/stm32429i-eval-u-boot.dtsi b/arch/arm/dts/stm32429i-eval-u-boot.dtsi
index 6da0a63..fe437bb 100644
--- a/arch/arm/dts/stm32429i-eval-u-boot.dtsi
+++ b/arch/arm/dts/stm32429i-eval-u-boot.dtsi
@@ -92,57 +92,46 @@
};
&gpioa {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiob {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioc {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiod {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioe {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiof {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiog {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioh {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioi {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioj {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiok {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/stm32f429-disco-u-boot.dtsi b/arch/arm/dts/stm32f429-disco-u-boot.dtsi
index 0cc3100..52f8032 100644
--- a/arch/arm/dts/stm32f429-disco-u-boot.dtsi
+++ b/arch/arm/dts/stm32f429-disco-u-boot.dtsi
@@ -79,57 +79,46 @@
};
&gpioa {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiob {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioc {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiod {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioe {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiof {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiog {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioh {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioi {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioj {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiok {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/stm32f469-disco-u-boot.dtsi b/arch/arm/dts/stm32f469-disco-u-boot.dtsi
index 3da308e..5a89f13 100644
--- a/arch/arm/dts/stm32f469-disco-u-boot.dtsi
+++ b/arch/arm/dts/stm32f469-disco-u-boot.dtsi
@@ -67,7 +67,7 @@
};
qspi: quadspi@A0001000 {
- compatible = "st,stm32-qspi";
+ compatible = "st,stm32f469-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
@@ -94,57 +94,46 @@
};
&gpioa {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiob {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioc {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiod {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioe {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiof {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiog {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioh {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioi {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioj {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiok {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/stm32f7-u-boot.dtsi b/arch/arm/dts/stm32f7-u-boot.dtsi
index 29b1573..32613c9 100644
--- a/arch/arm/dts/stm32f7-u-boot.dtsi
+++ b/arch/arm/dts/stm32f7-u-boot.dtsi
@@ -44,7 +44,7 @@
};
qspi: quadspi@A0001000 {
- compatible = "st,stm32-qspi";
+ compatible = "st,stm32f469-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
@@ -65,58 +65,41 @@
};
&gpioa {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiob {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioc {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiod {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioe {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiof {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiog {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioh {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioi {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
-&gpioj {
- compatible = "st,stm32-gpio";
-};
-
-&gpiok {
- compatible = "st,stm32-gpio";
-};
-
&pinctrl {
u-boot,dm-pre-reloc;
diff --git a/arch/arm/dts/stm32mp15-ddr.dtsi b/arch/arm/dts/stm32mp15-ddr.dtsi
index 4172c02..479b700 100644
--- a/arch/arm/dts/stm32mp15-ddr.dtsi
+++ b/arch/arm/dts/stm32mp15-ddr.dtsi
@@ -5,7 +5,7 @@
/ {
soc {
- ddr: ddr@0x5A003000{
+ ddr: ddr@5A003000 {
u-boot,dm-pre-reloc;
compatible = "st,stm32mp1-ddr";
diff --git a/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi
index dc30360..11e8f2b 100644
--- a/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi
+++ b/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi
@@ -16,7 +16,7 @@
* address mapping : RBC
* Tc > + 85C : N
*/
-#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.44"
+#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.45"
#define DDR_MEM_SPEED 533000
#define DDR_MEM_SIZE 0x20000000
@@ -89,7 +89,7 @@
#define DDR_PTR2 0x042DA068
#define DDR_ACIOCR 0x10400812
#define DDR_DXCCR 0x00000C40
-#define DDR_DSGCR 0xF200001F
+#define DDR_DSGCR 0xF200011F
#define DDR_DCR 0x0000000B
#define DDR_DTPR0 0x38D488D0
#define DDR_DTPR1 0x098B00D8
diff --git a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
index 8158a56..4b70b60 100644
--- a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
+++ b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
@@ -16,8 +16,7 @@
* address mapping : RBC
* Tc > + 85C : N
*/
-
-#define DDR_MEM_NAME "DDR3-1066/888 bin G 2x4Gb 533MHz v1.44"
+#define DDR_MEM_NAME "DDR3-1066/888 bin G 2x4Gb 533MHz v1.45"
#define DDR_MEM_SPEED 533000
#define DDR_MEM_SIZE 0x40000000
@@ -90,7 +89,7 @@
#define DDR_PTR2 0x042DA068
#define DDR_ACIOCR 0x10400812
#define DDR_DXCCR 0x00000C40
-#define DDR_DSGCR 0xF200001F
+#define DDR_DSGCR 0xF200011F
#define DDR_DCR 0x0000000B
#define DDR_DTPR0 0x38D488D0
#define DDR_DTPR1 0x098B00D8
diff --git a/arch/arm/dts/stm32mp157-pinctrl.dtsi b/arch/arm/dts/stm32mp157-pinctrl.dtsi
index 4c424c4..4367e8d 100644
--- a/arch/arm/dts/stm32mp157-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp157-pinctrl.dtsi
@@ -14,6 +14,7 @@
ranges = <0 0x50002000 0xa400>;
interrupt-parent = <&exti>;
st,syscfg = <&exti 0x60 0xff>;
+ hwlocks = <&hwspinlock 0>;
pins-are-numbered;
gpioa: gpio@50002000 {
@@ -24,8 +25,7 @@
reg = <0x0 0x400>;
clocks = <&rcc GPIOA>;
st,bank-name = "GPIOA";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 0 16>;
+ status = "disabled";
};
gpiob: gpio@50003000 {
@@ -36,8 +36,7 @@
reg = <0x1000 0x400>;
clocks = <&rcc GPIOB>;
st,bank-name = "GPIOB";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 16 16>;
+ status = "disabled";
};
gpioc: gpio@50004000 {
@@ -48,8 +47,7 @@
reg = <0x2000 0x400>;
clocks = <&rcc GPIOC>;
st,bank-name = "GPIOC";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 32 16>;
+ status = "disabled";
};
gpiod: gpio@50005000 {
@@ -60,8 +58,7 @@
reg = <0x3000 0x400>;
clocks = <&rcc GPIOD>;
st,bank-name = "GPIOD";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 48 16>;
+ status = "disabled";
};
gpioe: gpio@50006000 {
@@ -72,8 +69,7 @@
reg = <0x4000 0x400>;
clocks = <&rcc GPIOE>;
st,bank-name = "GPIOE";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 64 16>;
+ status = "disabled";
};
gpiof: gpio@50007000 {
@@ -84,8 +80,7 @@
reg = <0x5000 0x400>;
clocks = <&rcc GPIOF>;
st,bank-name = "GPIOF";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 80 16>;
+ status = "disabled";
};
gpiog: gpio@50008000 {
@@ -96,8 +91,7 @@
reg = <0x6000 0x400>;
clocks = <&rcc GPIOG>;
st,bank-name = "GPIOG";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 96 16>;
+ status = "disabled";
};
gpioh: gpio@50009000 {
@@ -108,8 +102,7 @@
reg = <0x7000 0x400>;
clocks = <&rcc GPIOH>;
st,bank-name = "GPIOH";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 112 16>;
+ status = "disabled";
};
gpioi: gpio@5000a000 {
@@ -120,8 +113,7 @@
reg = <0x8000 0x400>;
clocks = <&rcc GPIOI>;
st,bank-name = "GPIOI";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 128 16>;
+ status = "disabled";
};
gpioj: gpio@5000b000 {
@@ -132,8 +124,7 @@
reg = <0x9000 0x400>;
clocks = <&rcc GPIOJ>;
st,bank-name = "GPIOJ";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 144 16>;
+ status = "disabled";
};
gpiok: gpio@5000c000 {
@@ -144,8 +135,7 @@
reg = <0xa000 0x400>;
clocks = <&rcc GPIOK>;
st,bank-name = "GPIOK";
- ngpios = <8>;
- gpio-ranges = <&pinctrl 0 160 8>;
+ status = "disabled";
};
adc12_usb_pwr_pins_a: adc12-usb-pwr-pins-0 {
@@ -164,6 +154,68 @@
};
};
+ cec_pins_sleep_a: cec-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */
+ };
+ };
+
+ cec_pins_b: cec-1 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 6, AF5)>;
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ cec_pins_sleep_b: cec-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */
+ };
+ };
+
+ dcmi_pins_a: dcmi-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */
+ <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
+ <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
+ <STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */
+ <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
+ <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
+ <STM32_PINMUX('H', 12, AF13)>,/* DCMI_D3 */
+ <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */
+ <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */
+ <STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */
+ <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */
+ <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */
+ <STM32_PINMUX('H', 7, AF13)>,/* DCMI_D9 */
+ <STM32_PINMUX('I', 3, AF13)>,/* DCMI_D10 */
+ <STM32_PINMUX('H', 15, AF13)>;/* DCMI_D11 */
+ bias-disable;
+ };
+ };
+
+ dcmi_sleep_pins_a: dcmi-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */
+ <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
+ <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
+ <STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */
+ <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
+ <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */
+ <STM32_PINMUX('H', 12, ANALOG)>,/* DCMI_D3 */
+ <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */
+ <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */
+ <STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */
+ <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */
+ <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */
+ <STM32_PINMUX('H', 7, ANALOG)>,/* DCMI_D9 */
+ <STM32_PINMUX('I', 3, ANALOG)>,/* DCMI_D10 */
+ <STM32_PINMUX('H', 15, ANALOG)>;/* DCMI_D11 */
+ };
+ };
+
ethernet0_rgmii_pins_a: rgmii-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
@@ -269,7 +321,14 @@
};
};
- i2c1_pins_b: i2c1-1 {
+ i2c1_pins_sleep_a: i2c1-1 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
+ <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
+ };
+ };
+
+ i2c1_pins_b: i2c1-2 {
pins {
pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */
<STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
@@ -279,6 +338,13 @@
};
};
+ i2c1_pins_sleep_b: i2c1-3 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */
+ <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
+ };
+ };
+
i2c2_pins_a: i2c2-0 {
pins {
pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
@@ -289,16 +355,28 @@
};
};
- i2c2_pins_b: i2c2-1 {
+ i2c2_pins_sleep_a: i2c2-1 {
pins {
- pinmux = <STM32_PINMUX('Z', 0, AF3)>, /* I2C2_SCL */
- <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
+ pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */
+ <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
+ };
+ };
+
+ i2c2_pins_b1: i2c2-2 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
bias-disable;
drive-open-drain;
slew-rate = <0>;
};
};
+ i2c2_pins_sleep_b1: i2c2-3 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
+ };
+ };
+
i2c5_pins_a: i2c5-0 {
pins {
pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
@@ -309,6 +387,171 @@
};
};
+ i2c5_pins_sleep_a: i2c5-1 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */
+ <STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */
+
+ };
+ };
+
+ i2s2_pins_a: i2s2-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */
+ <STM32_PINMUX('B', 9, AF5)>, /* I2S2_WS */
+ <STM32_PINMUX('A', 9, AF5)>; /* I2S2_CK */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ i2s2_pins_sleep_a: i2s2-1 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 3, ANALOG)>, /* I2S2_SDO */
+ <STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */
+ <STM32_PINMUX('A', 9, ANALOG)>; /* I2S2_CK */
+ };
+ };
+
+ ltdc_pins_a: ltdc-a-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */
+ <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */
+ <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
+ <STM32_PINMUX('F', 10, AF14)>, /* LCD_DE */
+ <STM32_PINMUX('H', 2, AF14)>, /* LCD_R0 */
+ <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */
+ <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */
+ <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */
+ <STM32_PINMUX('H', 10, AF14)>, /* LCD_R4 */
+ <STM32_PINMUX('C', 0, AF14)>, /* LCD_R5 */
+ <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */
+ <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */
+ <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */
+ <STM32_PINMUX('E', 6, AF14)>, /* LCD_G1 */
+ <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
+ <STM32_PINMUX('H', 14, AF14)>, /* LCD_G3 */
+ <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */
+ <STM32_PINMUX('I', 0, AF14)>, /* LCD_G5 */
+ <STM32_PINMUX('I', 1, AF14)>, /* LCD_G6 */
+ <STM32_PINMUX('I', 2, AF14)>, /* LCD_G7 */
+ <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */
+ <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */
+ <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */
+ <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */
+ <STM32_PINMUX('I', 4, AF14)>, /* LCD_B4 */
+ <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */
+ <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */
+ <STM32_PINMUX('D', 8, AF14)>; /* LCD_B7 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ ltdc_pins_sleep_a: ltdc-a-1 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */
+ <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */
+ <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */
+ <STM32_PINMUX('F', 10, ANALOG)>, /* LCD_DE */
+ <STM32_PINMUX('H', 2, ANALOG)>, /* LCD_R0 */
+ <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */
+ <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */
+ <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */
+ <STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R4 */
+ <STM32_PINMUX('C', 0, ANALOG)>, /* LCD_R5 */
+ <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */
+ <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */
+ <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */
+ <STM32_PINMUX('E', 6, ANALOG)>, /* LCD_G1 */
+ <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
+ <STM32_PINMUX('H', 14, ANALOG)>, /* LCD_G3 */
+ <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */
+ <STM32_PINMUX('I', 0, ANALOG)>, /* LCD_G5 */
+ <STM32_PINMUX('I', 1, ANALOG)>, /* LCD_G6 */
+ <STM32_PINMUX('I', 2, ANALOG)>, /* LCD_G7 */
+ <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */
+ <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */
+ <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */
+ <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */
+ <STM32_PINMUX('I', 4, ANALOG)>, /* LCD_B4 */
+ <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */
+ <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */
+ <STM32_PINMUX('D', 8, ANALOG)>; /* LCD_B7 */
+ };
+ };
+
+ ltdc_pins_b: ltdc-b-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
+ <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
+ <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
+ <STM32_PINMUX('K', 7, AF14)>, /* LCD_DE */
+ <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
+ <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
+ <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
+ <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
+ <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
+ <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
+ <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */
+ <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
+ <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
+ <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
+ <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
+ <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
+ <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
+ <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
+ <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
+ <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
+ <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
+ <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
+ <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
+ <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3 */
+ <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */
+ <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
+ <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
+ <STM32_PINMUX('K', 6, AF14)>; /* LCD_B7 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ ltdc_pins_sleep_b: ltdc-b-1 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */
+ <STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */
+ <STM32_PINMUX('I', 13, ANALOG)>, /* LCD_VSYNC */
+ <STM32_PINMUX('K', 7, ANALOG)>, /* LCD_DE */
+ <STM32_PINMUX('I', 15, ANALOG)>, /* LCD_R0 */
+ <STM32_PINMUX('J', 0, ANALOG)>, /* LCD_R1 */
+ <STM32_PINMUX('J', 1, ANALOG)>, /* LCD_R2 */
+ <STM32_PINMUX('J', 2, ANALOG)>, /* LCD_R3 */
+ <STM32_PINMUX('J', 3, ANALOG)>, /* LCD_R4 */
+ <STM32_PINMUX('J', 4, ANALOG)>, /* LCD_R5 */
+ <STM32_PINMUX('J', 5, ANALOG)>, /* LCD_R6 */
+ <STM32_PINMUX('J', 6, ANALOG)>, /* LCD_R7 */
+ <STM32_PINMUX('J', 7, ANALOG)>, /* LCD_G0 */
+ <STM32_PINMUX('J', 8, ANALOG)>, /* LCD_G1 */
+ <STM32_PINMUX('J', 9, ANALOG)>, /* LCD_G2 */
+ <STM32_PINMUX('J', 10, ANALOG)>, /* LCD_G3 */
+ <STM32_PINMUX('J', 11, ANALOG)>, /* LCD_G4 */
+ <STM32_PINMUX('K', 0, ANALOG)>, /* LCD_G5 */
+ <STM32_PINMUX('K', 1, ANALOG)>, /* LCD_G6 */
+ <STM32_PINMUX('K', 2, ANALOG)>, /* LCD_G7 */
+ <STM32_PINMUX('J', 12, ANALOG)>, /* LCD_B0 */
+ <STM32_PINMUX('J', 13, ANALOG)>, /* LCD_B1 */
+ <STM32_PINMUX('J', 14, ANALOG)>, /* LCD_B2 */
+ <STM32_PINMUX('J', 15, ANALOG)>, /* LCD_B3 */
+ <STM32_PINMUX('K', 3, ANALOG)>, /* LCD_B4 */
+ <STM32_PINMUX('K', 4, ANALOG)>, /* LCD_B5 */
+ <STM32_PINMUX('K', 5, ANALOG)>, /* LCD_B6 */
+ <STM32_PINMUX('K', 6, ANALOG)>; /* LCD_B7 */
+ };
+ };
+
m_can1_pins_a: m-can1-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
@@ -322,6 +565,13 @@
};
};
+ m_can1_sleep_pins_a: m_can1-sleep@0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */
+ <STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */
+ };
+ };
+
pwm2_pins_a: pwm2-0 {
pins {
pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
@@ -358,6 +608,12 @@
};
};
+ qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
+ };
+ };
+
qspi_bk1_pins_a: qspi-bk1-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
@@ -376,6 +632,16 @@
};
};
+ qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
+ <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
+ <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */
+ <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */
+ <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */
+ };
+ };
+
qspi_bk2_pins_a: qspi-bk2-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
@@ -393,7 +659,91 @@
slew-rate = <3>;
};
};
- sdmmc1_b4_pins_a: sdmmc1-b4@0 {
+
+ qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */
+ <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */
+ <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */
+ <STM32_PINMUX('G', 7, ANALOG)>, /* QSPI_BK2_IO3 */
+ <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */
+ };
+ };
+
+ sai2a_pins_a: sai2a-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */
+ <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */
+ <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */
+ <STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */
+ slew-rate = <0>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ sai2a_sleep_pins_a: sai2a-1 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */
+ <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */
+ <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */
+ <STM32_PINMUX('E', 0, ANALOG)>; /* SAI2_MCLK_A */
+ };
+ };
+
+ sai2b_pins_a: sai2b-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('E', 12, AF10)>, /* SAI2_SCK_B */
+ <STM32_PINMUX('E', 13, AF10)>, /* SAI2_FS_B */
+ <STM32_PINMUX('E', 14, AF10)>; /* SAI2_MCLK_B */
+ slew-rate = <0>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
+ bias-disable;
+ };
+ };
+
+ sai2b_sleep_pins_a: sai2b-1 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */
+ <STM32_PINMUX('E', 12, ANALOG)>, /* SAI2_SCK_B */
+ <STM32_PINMUX('E', 13, ANALOG)>, /* SAI2_FS_B */
+ <STM32_PINMUX('E', 14, ANALOG)>; /* SAI2_MCLK_B */
+ };
+ };
+
+ sai2b_pins_b: sai2b-2 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
+ bias-disable;
+ };
+ };
+
+ sai2b_sleep_pins_b: sai2b-3 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
+ };
+ };
+
+ sai4a_pins_a: sai4a-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */
+ slew-rate = <0>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ sai4a_sleep_pins_a: sai4a-1 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* SAI4_SD_A */
+ };
+ };
+
+ sdmmc1_b4_pins_a: sdmmc1-b4-0 {
pins {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
@@ -407,18 +757,61 @@
};
};
- sdmmc1_dir_pins_a: sdmmc1-dir@0 {
+ sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
+ slew-rate = <3>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2{
+ pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+ slew-rate = <3>;
+ drive-open-drain;
+ bias-disable;
+ };
+ };
+
+ sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
pins {
+ pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
+ <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
+ };
+ };
+
+ sdmmc1_dir_pins_a: sdmmc1-dir-0 {
+ pins1 {
pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
<STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
- <STM32_PINMUX('B', 9, AF11)>, /* SDMMC1_CDIR */
- <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
+ <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
slew-rate = <3>;
drive-push-pull;
bias-pull-up;
};
+ pins2{
+ pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
+ bias-pull-up;
+ };
};
- sdmmc2_b4_pins_a: sdmmc2-b4@0 {
+
+ sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */
+ <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
+ <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
+ <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */
+ };
+ };
+
+ sdmmc2_b4_pins_a: sdmmc2-b4-0 {
pins {
pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
<STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
@@ -432,7 +825,7 @@
};
};
- sdmmc2_d47_pins_a: sdmmc2-d47@0 {
+ sdmmc2_d47_pins_a: sdmmc2-d47-0 {
pins {
pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
<STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
@@ -444,6 +837,19 @@
};
};
+ spdifrx_pins_a: spdifrx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */
+ bias-disable;
+ };
+ };
+
+ spdifrx_sleep_pins_a: spdifrx-1 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */
+ };
+ };
+
spi2_pins_a: spi2-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI2_SCK */
@@ -506,12 +912,6 @@
bias-disable;
};
};
-
- usbotg_hs_pins_a: usbotg_hs-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
- };
- };
};
pinctrl_z: pin-controller-z@54004000 {
@@ -522,6 +922,7 @@
pins-are-numbered;
interrupt-parent = <&exti>;
st,syscfg = <&exti 0x60 0xff>;
+ hwlocks = <&hwspinlock 0>;
gpioz: gpio@54004000 {
gpio-controller;
@@ -532,8 +933,22 @@
clocks = <&rcc GPIOZ>;
st,bank-name = "GPIOZ";
st,bank-ioport = <11>;
- ngpios = <8>;
- gpio-ranges = <&pinctrl_z 0 400 8>;
+ status = "disabled";
+ };
+
+ i2c2_pins_b2: i2c2-0 {
+ pins {
+ pinmux = <STM32_PINMUX('Z', 0, AF3)>; /* I2C2_SCL */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c2_pins_sleep_b2: i2c2-1 {
+ pins {
+ pinmux = <STM32_PINMUX('Z', 0, ANALOG)>; /* I2C2_SCL */
+ };
};
i2c4_pins_a: i2c4-0 {
@@ -546,6 +961,13 @@
};
};
+ i2c4_pins_sleep_a: i2c4-1 {
+ pins {
+ pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */
+ <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */
+ };
+ };
+
spi1_pins_a: spi1-0 {
pins1 {
pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */
diff --git a/arch/arm/dts/stm32mp157-u-boot.dtsi b/arch/arm/dts/stm32mp157-u-boot.dtsi
index 09560e2..0d1d387 100644
--- a/arch/arm/dts/stm32mp157-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157-u-boot.dtsi
@@ -21,27 +21,29 @@
pinctrl1 = &pinctrl_z;
};
- config {
+ clocks {
u-boot,dm-pre-reloc;
};
- clocks {
+ /* need PSCI for sysreset during board_f */
+ psci {
+ u-boot,dm-pre-proper;
+ };
+
+ reboot {
u-boot,dm-pre-reloc;
};
soc {
u-boot,dm-pre-reloc;
-
- stgen: stgen@5C008000 {
- compatible = "st,stm32-stgen";
- reg = <0x5C008000 0x1000>;
- status = "okay";
- u-boot,dm-pre-reloc;
- };
};
};
&bsec {
+ u-boot,dm-pre-proper;
+};
+
+&clk_csi {
u-boot,dm-pre-reloc;
};
@@ -53,26 +55,71 @@
u-boot,dm-pre-reloc;
};
-&clk_lse {
- u-boot,dm-pre-reloc;
-};
-
&clk_lsi {
u-boot,dm-pre-reloc;
};
-&clk_csi {
+&clk_lse {
u-boot,dm-pre-reloc;
};
-&rcc {
+&gpioa {
u-boot,dm-pre-reloc;
};
-&rcc_reboot {
+&gpiob {
u-boot,dm-pre-reloc;
};
+&gpioc {
+ u-boot,dm-pre-reloc;
+};
+
+&gpiod {
+ u-boot,dm-pre-reloc;
+};
+
+&gpioe {
+ u-boot,dm-pre-reloc;
+};
+
+&gpiof {
+ u-boot,dm-pre-reloc;
+};
+
+&gpiog {
+ u-boot,dm-pre-reloc;
+};
+
+&gpioh {
+ u-boot,dm-pre-reloc;
+};
+
+&gpioi {
+ u-boot,dm-pre-reloc;
+};
+
+&gpioj {
+ u-boot,dm-pre-reloc;
+};
+
+&gpiok {
+ u-boot,dm-pre-reloc;
+};
+
+&gpioz {
+ u-boot,dm-pre-reloc;
+};
+
+&iwdg2 {
+ u-boot,dm-pre-reloc;
+};
+
+/* pre-reloc probe = reserve video frame buffer in video_reserve() */
+<dc {
+ u-boot,dm-pre-proper;
+};
+
&pinctrl {
u-boot,dm-pre-reloc;
};
@@ -81,66 +128,26 @@
u-boot,dm-pre-reloc;
};
-&gpioa {
- compatible = "st,stm32-gpio";
+&pwr {
u-boot,dm-pre-reloc;
};
-&gpiob {
- compatible = "st,stm32-gpio";
+&rcc {
u-boot,dm-pre-reloc;
};
-&gpioc {
- compatible = "st,stm32-gpio";
- u-boot,dm-pre-reloc;
+&sdmmc1 {
+ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
};
-&gpiod {
- compatible = "st,stm32-gpio";
- u-boot,dm-pre-reloc;
+&sdmmc2 {
+ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
};
-&gpioe {
- compatible = "st,stm32-gpio";
- u-boot,dm-pre-reloc;
+&sdmmc3 {
+ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
};
-&gpiof {
- compatible = "st,stm32-gpio";
- u-boot,dm-pre-reloc;
-};
-
-&gpiog {
- compatible = "st,stm32-gpio";
- u-boot,dm-pre-reloc;
-};
-
-&gpioh {
- compatible = "st,stm32-gpio";
- u-boot,dm-pre-reloc;
-};
-
-&gpioi {
- compatible = "st,stm32-gpio";
- u-boot,dm-pre-reloc;
-};
-
-&gpioj {
- compatible = "st,stm32-gpio";
- u-boot,dm-pre-reloc;
-};
-
-&gpiok {
- compatible = "st,stm32-gpio";
- u-boot,dm-pre-reloc;
-};
-
-&gpioz {
- compatible = "st,stm32-gpio";
- u-boot,dm-pre-reloc;
-};
-
-&iwdg2 {
- u-boot,dm-pre-reloc;
+&usbotg_hs {
+ compatible = "st,stm32mp1-hsotg", "snps,dwc2";
};
diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts
index dd08597..5b15a4a 100644
--- a/arch/arm/dts/stm32mp157a-avenger96.dts
+++ b/arch/arm/dts/stm32mp157a-avenger96.dts
@@ -1,8 +1,5 @@
// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
/*
- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
- *
* Copyright (C) Linaro Ltd 2019 - All Rights Reserved
* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
*/
@@ -10,17 +7,19 @@
/dts-v1/;
#include "stm32mp157c.dtsi"
-#include "stm32mp157-pinctrl.dtsi"
+#include "stm32mp157xac-pinctrl.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/mfd/st,stpmic1.h>
/ {
model = "Arrow Electronics STM32MP157A Avenger96 board";
- compatible = "st,stm32mp157a-avenger96", "st,stm32mp157";
+ compatible = "arrow,stm32mp157a-avenger96", "st,stm32mp157";
aliases {
ethernet0 = ðernet0;
+ mmc0 = &sdmmc1;
serial0 = &uart4;
+ serial1 = &uart7;
};
chosen {
@@ -28,6 +27,7 @@
};
memory@c0000000 {
+ device_type = "memory";
reg = <0xc0000000 0x40000000>;
};
@@ -109,7 +109,7 @@
&i2c2 {
pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_b>;
+ pinctrl-0 = <&i2c2_pins_b1 &i2c2_pins_b2>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
@@ -151,10 +151,10 @@
vddcore: buck1 {
regulator-name = "vddcore";
- regulator-min-microvolt = <800000>;
+ regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
- regulator-initial-mode = <2>;
+ regulator-initial-mode = <0>;
regulator-over-current-protection;
};
@@ -163,17 +163,17 @@
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
- regulator-initial-mode = <2>;
+ regulator-initial-mode = <0>;
regulator-over-current-protection;
};
vdd: buck3 {
regulator-name = "vdd";
- regulator-min-microvolt = <2500000>;
- regulator-max-microvolt = <2500000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
regulator-always-on;
st,mask_reset;
- regulator-initial-mode = <8>;
+ regulator-initial-mode = <0>;
regulator-over-current-protection;
};
@@ -183,7 +183,7 @@
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-over-current-protection;
- regulator-initial-mode = <8>;
+ regulator-initial-mode = <0>;
};
vdda: ldo1 {
@@ -204,8 +204,8 @@
vtt_ddr: ldo3 {
regulator-name = "vtt_ddr";
- regulator-min-microvolt = <0000000>;
- regulator-max-microvolt = <1000000>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <750000>;
regulator-always-on;
regulator-over-current-protection;
};
@@ -233,6 +233,7 @@
regulator-max-microvolt = <1800000>;
interrupts = <IT_CURLIM_LDO6 0>;
interrupt-parent = <&pmic>;
+ regulator-enable-ramp-delay = <300000>;
};
vref_ddr: vref_ddr {
@@ -282,7 +283,10 @@
};
&pwr {
- pwr-supply = <&vdd>;
+ pwr-regulators {
+ vdd-supply = <&vdd>;
+ vdd_3v3_usbfs-supply = <&vdd_usb>;
+ };
};
&rng1 {
@@ -294,8 +298,10 @@
};
&sdmmc1 {
- pinctrl-names = "default";
+ pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
+ pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
+ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
broken-cd;
st,sig-dir;
st,neg-edge;
@@ -325,12 +331,16 @@
};
&uart4 {
+ /* On Low speed expansion header */
+ label = "LS-UART1";
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins_b>;
status = "okay";
};
&uart7 {
+ /* On Low speed expansion header */
+ label = "LS-UART0";
pinctrl-names = "default";
pinctrl-0 = <&uart7_pins_a>;
status = "okay";
diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
index 0f32a38..dcaab3e 100644
--- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
@@ -17,6 +17,8 @@
u-boot,boot-led = "heartbeat";
u-boot,error-led = "error";
st,adc_usb_pd = <&adc1 18>, <&adc1 19>;
+ st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
+ st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
};
led {
red {
@@ -187,6 +189,8 @@
};
pins2 {
u-boot,dm-pre-reloc;
+ /* pull-up on rx to avoid floating level */
+ bias-pull-up;
};
};
@@ -194,7 +198,3 @@
u-boot,force-b-session-valid;
hnp-srp-disable;
};
-
-&v3v3 {
- regulator-always-on;
-};
diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts
index e36773d..c210acc 100644
--- a/arch/arm/dts/stm32mp157a-dk1.dts
+++ b/arch/arm/dts/stm32mp157a-dk1.dts
@@ -7,7 +7,7 @@
/dts-v1/;
#include "stm32mp157c.dtsi"
-#include "stm32mp157-pinctrl.dtsi"
+#include "stm32mp157xac-pinctrl.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/mfd/st,stpmic1.h>
@@ -28,6 +28,17 @@
reg = <0xc0000000 0x20000000>;
};
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gpu_reserved: gpu@d4000000 {
+ reg = <0xd4000000 0x4000000>;
+ no-map;
+ };
+ };
+
led {
compatible = "gpio-leds";
blue {
@@ -39,12 +50,19 @@
};
};
+&cec {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&cec_pins_b>;
+ pinctrl-1 = <&cec_pins_sleep_b>;
+ status = "okay";
+};
+
ðernet0 {
status = "okay";
pinctrl-0 = <ðernet0_rgmii_pins_a>;
pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>;
pinctrl-names = "default", "sleep";
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
max-speed = <1000>;
phy-handle = <&phy0>;
@@ -58,12 +76,55 @@
};
};
+&gpu {
+ contiguous-area = <&gpu_reserved>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c1_pins_a>;
+ pinctrl-1 = <&i2c1_pins_sleep_a>;
+ i2c-scl-rising-time-ns = <100>;
+ i2c-scl-falling-time-ns = <7>;
+ status = "okay";
+ /delete-property/dmas;
+ /delete-property/dma-names;
+
+ hdmi-transmitter@39 {
+ compatible = "sil,sii9022";
+ reg = <0x39>;
+ iovcc-supply = <&v3v3_hdmi>;
+ cvcc12-supply = <&v1v2_hdmi>;
+ reset-gpios = <&gpioa 10 GPIO_ACTIVE_LOW>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-parent = <&gpiog>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <<dc_pins_a>;
+ pinctrl-1 = <<dc_pins_sleep_a>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ sii9022_in: endpoint {
+ remote-endpoint = <<dc_ep0_out>;
+ };
+ };
+ };
+ };
+};
+
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&i2c4_pins_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
+ /* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
@@ -88,17 +149,13 @@
pmic: stpmic@33 {
compatible = "st,stpmic1";
reg = <0x33>;
+ interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
status = "okay";
- st,main-control-register = <0x04>;
- st,vin-control-register = <0xc0>;
- st,usb-control-register = <0x20>;
-
regulators {
compatible = "st,stpmic1-regulators";
-
ldo1-supply = <&v3v3>;
ldo3-supply = <&vdd_ddr>;
ldo6-supply = <&v3v3>;
@@ -107,7 +164,7 @@
vddcore: buck1 {
regulator-name = "vddcore";
- regulator-min-microvolt = <1200000>;
+ regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-initial-mode = <0>;
@@ -187,7 +244,6 @@
regulator-max-microvolt = <1200000>;
regulator-always-on;
interrupts = <IT_CURLIM_LDO6 0>;
-
};
vref_ddr: vref_ddr {
@@ -204,7 +260,6 @@
vbus_otg: pwr_sw1 {
regulator-name = "vbus_otg";
interrupts = <IT_OCP_OTG 0>;
- regulator-active-discharge;
};
vbus_sw: pwr_sw2 {
@@ -216,8 +271,9 @@
onkey {
compatible = "st,stpmic1-onkey";
- interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>;
+ interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
interrupt-names = "onkey-falling", "onkey-rising";
+ power-off-time-sec = <10>;
status = "okay";
};
@@ -228,13 +284,40 @@
};
};
+&ipcc {
+ status = "okay";
+};
+
&iwdg2 {
timeout-sec = <32>;
status = "okay";
};
+<dc {
+ status = "okay";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ltdc_ep0_out: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&sii9022_in>;
+ };
+ };
+};
+
+&m4_rproc {
+ mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
+ mbox-names = "vq0", "vq1", "shutdown";
+ status = "okay";
+};
+
&pwr {
- pwr-supply = <&vdd>;
+ pwr-regulators {
+ vdd-supply = <&vdd>;
+ vdd_3v3_usbfs-supply = <&vdd_usb>;
+ };
};
&rng1 {
@@ -246,8 +329,10 @@
};
&sdmmc1 {
- pinctrl-names = "default";
+ pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc1_b4_pins_a>;
+ pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
+ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
broken-cd;
st,neg-edge;
bus-width = <4>;
diff --git a/arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi b/arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi
index 06ef3a4..18ac1e3 100644
--- a/arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi
@@ -4,3 +4,9 @@
*/
#include "stm32mp157a-dk1-u-boot.dtsi"
+
+&i2c1 {
+ hdmi-transmitter@39 {
+ reset-gpios = <&gpioa 10 GPIO_ACTIVE_LOW>;
+ };
+};
diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts
index 9a81d2d..020ea0f 100644
--- a/arch/arm/dts/stm32mp157c-dk2.dts
+++ b/arch/arm/dts/stm32mp157c-dk2.dts
@@ -42,6 +42,7 @@
compatible = "orisetech,otm8009a";
reg = <0>;
reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
+ power-supply = <&v3v3>;
status = "okay";
port {
diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
index 55f9903..4953a0d 100644
--- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
@@ -15,31 +15,22 @@
};
config {
+ u-boot,boot-led = "heartbeat";
+ u-boot,error-led = "error";
st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
};
led {
- compatible = "gpio-leds";
-
red {
- label = "stm32mp:red:status";
+ label = "error";
gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
default-state = "off";
+ status = "okay";
};
- green {
- label = "stm32mp:green:user";
- gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
- default-state = "on";
- };
- orange {
- label = "stm32mp:orange:status";
- gpios = <&gpioh 7 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
+
blue {
- label = "stm32mp:blue:user";
- gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
};
};
};
@@ -156,6 +147,10 @@
};
};
+&sdmmc1 {
+ u-boot,dm-spl;
+};
+
&sdmmc1_b4_pins_a {
u-boot,dm-spl;
pins {
@@ -165,12 +160,15 @@
&sdmmc1_dir_pins_a {
u-boot,dm-spl;
- pins {
+ pins1 {
+ u-boot,dm-spl;
+ };
+ pins2 {
u-boot,dm-spl;
};
};
-&sdmmc1 {
+&sdmmc2 {
u-boot,dm-spl;
};
@@ -188,10 +186,6 @@
};
};
-&sdmmc2 {
- u-boot,dm-spl;
-};
-
&uart4 {
u-boot,dm-pre-reloc;
};
@@ -203,5 +197,7 @@
};
pins2 {
u-boot,dm-pre-reloc;
+ /* pull-up on rx to avoid floating level */
+ bias-pull-up;
};
};
diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts
index b10208f..1d9cc73 100644
--- a/arch/arm/dts/stm32mp157c-ed1.dts
+++ b/arch/arm/dts/stm32mp157c-ed1.dts
@@ -6,7 +6,7 @@
/dts-v1/;
#include "stm32mp157c.dtsi"
-#include "stm32mp157-pinctrl.dtsi"
+#include "stm32mp157xaa-pinctrl.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/mfd/st,stpmic1.h>
@@ -19,9 +19,21 @@
};
memory@c0000000 {
+ device_type = "memory";
reg = <0xC0000000 0x40000000>;
};
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gpu_reserved: gpu@e8000000 {
+ reg = <0xe8000000 0x8000000>;
+ no-map;
+ };
+ };
+
aliases {
serial0 = &uart4;
};
@@ -40,7 +52,12 @@
};
};
-&hwspinlock {
+&dts {
+ status = "okay";
+};
+
+&gpu {
+ contiguous-area = <&gpu_reserved>;
status = "okay";
};
@@ -50,23 +67,20 @@
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
- pmic: stpmic1@33 {
+ pmic: stpmic@33 {
compatible = "st,stpmic1";
reg = <0x33>;
- interrupts = <0 2>;
- interrupt-parent = <&gpioa>;
+ interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
status = "okay";
- st,main_control_register = <0x04>;
- st,vin_control_register = <0xc0>;
- st,usb_control_register = <0x30>;
-
regulators {
compatible = "st,stpmic1-regulators";
-
ldo1-supply = <&v3v3>;
ldo2-supply = <&v3v3>;
ldo3-supply = <&vdd_ddr>;
@@ -80,20 +94,8 @@
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
- regulator-initial-mode = <2>;
+ regulator-initial-mode = <0>;
regulator-over-current-protection;
-
- regulator-state-standby {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1200000>;
- regulator-mode = <8>;
- };
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- regulator-state-disk {
- regulator-off-in-suspend;
- };
};
vdd_ddr: buck2 {
@@ -101,22 +103,8 @@
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
- regulator-initial-mode = <2>;
+ regulator-initial-mode = <0>;
regulator-over-current-protection;
-
- regulator-state-standby {
- regulator-suspend-microvolt = <1350000>;
- regulator-on-in-suspend;
- regulator-mode = <8>;
- };
- regulator-state-mem {
- regulator-suspend-microvolt = <1350000>;
- regulator-on-in-suspend;
- regulator-mode = <8>;
- };
- regulator-state-disk {
- regulator-off-in-suspend;
- };
};
vdd: buck3 {
@@ -124,46 +112,18 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
- st,mask_reset;
- regulator-initial-mode = <8>;
+ st,mask-reset;
+ regulator-initial-mode = <0>;
regulator-over-current-protection;
-
- regulator-state-standby {
- regulator-suspend-microvolt = <3300000>;
- regulator-on-in-suspend;
- regulator-mode = <8>;
- };
- regulator-state-mem {
- regulator-suspend-microvolt = <3300000>;
- regulator-on-in-suspend;
- regulator-mode = <8>;
- };
- regulator-state-disk {
- regulator-suspend-microvolt = <3300000>;
- regulator-on-in-suspend;
- regulator-mode = <8>;
- };
};
v3v3: buck4 {
regulator-name = "v3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- regulator-boot-on;
+ regulator-always-on;
regulator-over-current-protection;
- regulator-initial-mode = <8>;
-
- regulator-state-standby {
- regulator-suspend-microvolt = <3300000>;
- regulator-unchanged-in-suspend;
- regulator-mode = <8>;
- };
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- regulator-state-disk {
- regulator-off-in-suspend;
- };
+ regulator-initial-mode = <0>;
};
vdda: ldo1 {
@@ -171,18 +131,6 @@
regulator-min-microvolt = <2900000>;
regulator-max-microvolt = <2900000>;
interrupts = <IT_CURLIM_LDO1 0>;
- interrupt-parent = <&pmic>;
-
- regulator-state-standby {
- regulator-suspend-microvolt = <2900000>;
- regulator-unchanged-in-suspend;
- };
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- regulator-state-disk {
- regulator-off-in-suspend;
- };
};
v2v8: ldo2 {
@@ -190,36 +138,14 @@
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
interrupts = <IT_CURLIM_LDO2 0>;
- interrupt-parent = <&pmic>;
-
- regulator-state-standby {
- regulator-suspend-microvolt = <2800000>;
- regulator-unchanged-in-suspend;
- };
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- regulator-state-disk {
- regulator-off-in-suspend;
- };
};
vtt_ddr: ldo3 {
regulator-name = "vtt_ddr";
- regulator-min-microvolt = <0000000>;
- regulator-max-microvolt = <1000000>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <750000>;
regulator-always-on;
regulator-over-current-protection;
-
- regulator-state-standby {
- regulator-off-in-suspend;
- };
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- regulator-state-disk {
- regulator-off-in-suspend;
- };
};
vdd_usb: ldo4 {
@@ -227,17 +153,6 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
interrupts = <IT_CURLIM_LDO4 0>;
- interrupt-parent = <&pmic>;
-
- regulator-state-standby {
- regulator-unchanged-in-suspend;
- };
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- regulator-state-disk {
- regulator-off-in-suspend;
- };
};
vdd_sd: ldo5 {
@@ -245,19 +160,7 @@
regulator-min-microvolt = <2900000>;
regulator-max-microvolt = <2900000>;
interrupts = <IT_CURLIM_LDO5 0>;
- interrupt-parent = <&pmic>;
regulator-boot-on;
-
- regulator-state-standby {
- regulator-suspend-microvolt = <2900000>;
- regulator-unchanged-in-suspend;
- };
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- regulator-state-disk {
- regulator-off-in-suspend;
- };
};
v1v8: ldo6 {
@@ -265,70 +168,66 @@
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
interrupts = <IT_CURLIM_LDO6 0>;
- interrupt-parent = <&pmic>;
-
- regulator-state-standby {
- regulator-suspend-microvolt = <1800000>;
- regulator-unchanged-in-suspend;
- };
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- regulator-state-disk {
- regulator-off-in-suspend;
- };
};
vref_ddr: vref_ddr {
regulator-name = "vref_ddr";
regulator-always-on;
regulator-over-current-protection;
-
- regulator-state-standby {
- regulator-on-in-suspend;
- };
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- regulator-state-disk {
- regulator-off-in-suspend;
- };
};
bst_out: boost {
regulator-name = "bst_out";
interrupts = <IT_OCP_BOOST 0>;
- interrupt-parent = <&pmic>;
};
vbus_otg: pwr_sw1 {
regulator-name = "vbus_otg";
interrupts = <IT_OCP_OTG 0>;
- interrupt-parent = <&pmic>;
- regulator-active-discharge;
};
vbus_sw: pwr_sw2 {
regulator-name = "vbus_sw";
interrupts = <IT_OCP_SWOUT 0>;
- interrupt-parent = <&pmic>;
regulator-active-discharge;
};
};
+
+ onkey {
+ compatible = "st,stpmic1-onkey";
+ interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
+ interrupt-names = "onkey-falling", "onkey-rising";
+ power-off-time-sec = <10>;
+ status = "okay";
+ };
+
+ watchdog {
+ compatible = "st,stpmic1-wdt";
+ status = "disabled";
+ };
};
};
+&ipcc {
+ status = "okay";
+};
+
&iwdg2 {
timeout-sec = <32>;
status = "okay";
};
-&pinctrl {
- hwlocks = <&hwspinlock 0>;
+&m4_rproc {
+ mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
+ mbox-names = "vq0", "vq1", "shutdown";
+ status = "okay";
};
&pwr {
- pwr-supply = <&vdd>;
+ pwr-regulators {
+ vdd-supply = <&vdd>;
+ vdd_3v3_usbfs-supply = <&vdd_usb>;
+ };
};
&rng1 {
@@ -340,7 +239,10 @@
};
&sdmmc1 {
+ pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
+ pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>;
+ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>;
broken-cd;
st,sig-dir;
st,neg-edge;
@@ -348,11 +250,6 @@
bus-width = <4>;
vmmc-supply = <&vdd_sd>;
vqmmc-supply = <&sd_switch>;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- sd-uhs-ddr50;
- sd-uhs-sdr104;
status = "okay";
};
@@ -371,6 +268,9 @@
&timers6 {
status = "okay";
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
timer@5 {
status = "okay";
};
@@ -382,6 +282,10 @@
status = "okay";
};
+&usbotg_hs {
+ vbus-supply = <&vbus_otg>;
+};
+
&usbphyc_port0 {
phy-supply = <&vdd_usb>;
};
diff --git a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
index 994092a..ec60486 100644
--- a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
@@ -17,14 +17,9 @@
};
&flash0 {
- compatible = "jedec,spi-nor";
u-boot,dm-spl;
};
-&flash1 {
- compatible = "jedec,spi-nor";
-};
-
&qspi {
u-boot,dm-spl;
};
@@ -56,6 +51,3 @@
};
};
-&v3v3 {
- regulator-always-on;
-};
diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts
index 663e52a..23de232 100644
--- a/arch/arm/dts/stm32mp157c-ev1.dts
+++ b/arch/arm/dts/stm32mp157c-ev1.dts
@@ -6,6 +6,8 @@
/dts-v1/;
#include "stm32mp157c-ed1.dts"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
/ {
model = "STMicroelectronics STM32MP157C eval daughter on eval mother";
@@ -20,6 +22,51 @@
ethernet0 = ðernet0;
};
+ clocks {
+ clk_ext_camera: clk-ext-camera {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+ };
+
+ joystick {
+ compatible = "gpio-keys";
+ #size-cells = <0>;
+ pinctrl-0 = <&joystick_pins>;
+ pinctrl-names = "default";
+ button-0 {
+ label = "JoySel";
+ linux,code = <KEY_ENTER>;
+ interrupt-parent = <&stmfx_pinctrl>;
+ interrupts = <0 IRQ_TYPE_EDGE_RISING>;
+ };
+ button-1 {
+ label = "JoyDown";
+ linux,code = <KEY_DOWN>;
+ interrupt-parent = <&stmfx_pinctrl>;
+ interrupts = <1 IRQ_TYPE_EDGE_RISING>;
+ };
+ button-2 {
+ label = "JoyLeft";
+ linux,code = <KEY_LEFT>;
+ interrupt-parent = <&stmfx_pinctrl>;
+ interrupts = <2 IRQ_TYPE_EDGE_RISING>;
+ };
+ button-3 {
+ label = "JoyRight";
+ linux,code = <KEY_RIGHT>;
+ interrupt-parent = <&stmfx_pinctrl>;
+ interrupts = <3 IRQ_TYPE_EDGE_RISING>;
+ };
+ button-4 {
+ label = "JoyUp";
+ linux,code = <KEY_UP>;
+ interrupt-parent = <&stmfx_pinctrl>;
+ interrupts = <4 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+
panel_backlight: panel-backlight {
compatible = "gpio-backlight";
gpios = <&gpiod 13 GPIO_ACTIVE_LOW>;
@@ -34,6 +81,23 @@
status = "okay";
};
+&dcmi {
+ status = "okay";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&dcmi_pins_a>;
+ pinctrl-1 = <&dcmi_sleep_pins_a>;
+
+ port {
+ dcmi_0: endpoint {
+ remote-endpoint = <&ov5640_0>;
+ bus-width = <8>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pclk-sample = <1>;
+ };
+ };
+};
+
&dsi {
#address-cells = <1>;
#size-cells = <0>;
@@ -63,6 +127,7 @@
reg = <0>;
reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
backlight = <&panel_backlight>;
+ power-supply = <&v3v3>;
status = "okay";
port {
@@ -115,6 +180,31 @@
i2c-scl-falling-time-ns = <20>;
status = "okay";
+ ov5640: camera@3c {
+ compatible = "ovti,ov5640";
+ pinctrl-names = "default";
+ pinctrl-0 = <&ov5640_pins>;
+ reg = <0x3c>;
+ clocks = <&clk_ext_camera>;
+ clock-names = "xclk";
+ DOVDD-supply = <&v2v8>;
+ powerdown-gpios = <&stmfx_pinctrl 18 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&stmfx_pinctrl 19 GPIO_ACTIVE_LOW>;
+ rotation = <180>;
+ status = "okay";
+
+ port {
+ ov5640_0: endpoint {
+ remote-endpoint = <&dcmi_0>;
+ bus-width = <8>;
+ data-shift = <2>; /* lines 9:2 are used */
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pclk-sample = <1>;
+ };
+ };
+ };
+
stmfx: stmfx@42 {
compatible = "st,stmfx-0300";
reg = <0x42>;
@@ -129,7 +219,18 @@
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&stmfx_pinctrl 0 0 24>;
- status = "disabled";
+
+ joystick_pins: joystick {
+ pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4";
+ drive-push-pull;
+ bias-pull-down;
+ };
+
+ ov5640_pins: camera {
+ pins = "agpio2", "agpio3"; /* stmfx pins 18 & 19 */
+ drive-push-pull;
+ output-low;
+ };
};
};
};
@@ -157,20 +258,23 @@
};
&m_can1 {
- pinctrl-names = "default";
+ pinctrl-names = "default", "sleep";
pinctrl-0 = <&m_can1_pins_a>;
+ pinctrl-1 = <&m_can1_sleep_pins_a>;
status = "okay";
};
&qspi {
- pinctrl-names = "default";
+ pinctrl-names = "default", "sleep";
pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
+ pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>;
reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash0: mx66l51235l@0 {
+ compatible = "jedec,spi-nor";
reg = <0>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>;
@@ -179,6 +283,7 @@
};
flash1: mx66l51235l@1 {
+ compatible = "jedec,spi-nor";
reg = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>;
@@ -194,6 +299,9 @@
};
&timers2 {
+ /* spare dmas for other usage (un-delete to enable pwm capture) */
+ /delete-property/dmas;
+ /delete-property/dma-names;
status = "disabled";
pwm {
pinctrl-0 = <&pwm2_pins_a>;
@@ -206,6 +314,8 @@
};
&timers8 {
+ /delete-property/dmas;
+ /delete-property/dma-names;
status = "disabled";
pwm {
pinctrl-0 = <&pwm8_pins_a>;
@@ -218,6 +328,8 @@
};
&timers12 {
+ /delete-property/dmas;
+ /delete-property/dma-names;
status = "disabled";
pwm {
pinctrl-0 = <&pwm12_pins_a>;
@@ -232,13 +344,10 @@
&usbh_ehci {
phys = <&usbphyc_port0>;
phy-names = "usb";
- vbus-supply = <&vbus_sw>;
status = "okay";
};
&usbotg_hs {
- pinctrl-names = "default";
- pinctrl-0 = <&usbotg_hs_pins_a>;
dr_mode = "peripheral";
phys = <&usbphyc_port1 0>;
phy-names = "usb2-phy";
diff --git a/arch/arm/dts/stm32mp157c.dtsi b/arch/arm/dts/stm32mp157c.dtsi
index 7321585..a6045dd 100644
--- a/arch/arm/dts/stm32mp157c.dtsi
+++ b/arch/arm/dts/stm32mp157c.dtsi
@@ -35,28 +35,6 @@
cpu_on = <0x84000003>;
};
- aliases {
- gpio0 = &gpioa;
- gpio1 = &gpiob;
- gpio2 = &gpioc;
- gpio3 = &gpiod;
- gpio4 = &gpioe;
- gpio5 = &gpiof;
- gpio6 = &gpiog;
- gpio7 = &gpioh;
- gpio8 = &gpioi;
- gpio9 = &gpioj;
- gpio10 = &gpiok;
- serial0 = &usart1;
- serial1 = &usart2;
- serial2 = &usart3;
- serial3 = &uart4;
- serial4 = &uart5;
- serial5 = &usart6;
- serial6 = &uart7;
- serial7 = &uart8;
- };
-
intc: interrupt-controller@a0021000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
@@ -106,6 +84,38 @@
};
};
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&dts>;
+
+ trips {
+ cpu_alert1: cpu-alert1 {
+ temperature = <85000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ cpu-crit {
+ temperature = <120000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ };
+ };
+ };
+
+ reboot {
+ compatible = "syscon-reboot";
+ regmap = <&rcc>;
+ offset = <0x404>;
+ mask = <0x1>;
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <1>;
@@ -120,6 +130,12 @@
reg = <0x40000000 0x400>;
clocks = <&rcc TIM2_K>;
clock-names = "int";
+ dmas = <&dmamux1 18 0x400 0x1>,
+ <&dmamux1 19 0x400 0x1>,
+ <&dmamux1 20 0x400 0x1>,
+ <&dmamux1 21 0x400 0x1>,
+ <&dmamux1 22 0x400 0x1>;
+ dma-names = "ch1", "ch2", "ch3", "ch4", "up";
status = "disabled";
pwm {
@@ -141,6 +157,13 @@
reg = <0x40001000 0x400>;
clocks = <&rcc TIM3_K>;
clock-names = "int";
+ dmas = <&dmamux1 23 0x400 0x1>,
+ <&dmamux1 24 0x400 0x1>,
+ <&dmamux1 25 0x400 0x1>,
+ <&dmamux1 26 0x400 0x1>,
+ <&dmamux1 27 0x400 0x1>,
+ <&dmamux1 28 0x400 0x1>;
+ dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
status = "disabled";
pwm {
@@ -162,6 +185,11 @@
reg = <0x40002000 0x400>;
clocks = <&rcc TIM4_K>;
clock-names = "int";
+ dmas = <&dmamux1 29 0x400 0x1>,
+ <&dmamux1 30 0x400 0x1>,
+ <&dmamux1 31 0x400 0x1>,
+ <&dmamux1 32 0x400 0x1>;
+ dma-names = "ch1", "ch2", "ch3", "ch4";
status = "disabled";
pwm {
@@ -183,6 +211,13 @@
reg = <0x40003000 0x400>;
clocks = <&rcc TIM5_K>;
clock-names = "int";
+ dmas = <&dmamux1 55 0x400 0x1>,
+ <&dmamux1 56 0x400 0x1>,
+ <&dmamux1 57 0x400 0x1>,
+ <&dmamux1 58 0x400 0x1>,
+ <&dmamux1 59 0x400 0x1>,
+ <&dmamux1 60 0x400 0x1>;
+ dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
status = "disabled";
pwm {
@@ -204,6 +239,8 @@
reg = <0x40004000 0x400>;
clocks = <&rcc TIM6_K>;
clock-names = "int";
+ dmas = <&dmamux1 69 0x400 0x1>;
+ dma-names = "up";
status = "disabled";
timer@5 {
@@ -220,6 +257,8 @@
reg = <0x40005000 0x400>;
clocks = <&rcc TIM7_K>;
clock-names = "int";
+ dmas = <&dmamux1 70 0x400 0x1>;
+ dma-names = "up";
status = "disabled";
timer@6 {
@@ -333,6 +372,17 @@
status = "disabled";
};
+ i2s2: audio-controller@4000b000 {
+ compatible = "st,stm32h7-i2s";
+ #sound-dai-cells = <0>;
+ reg = <0x4000b000 0x400>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmamux1 39 0x400 0x01>,
+ <&dmamux1 40 0x400 0x01>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
spi3: spi@4000c000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -347,6 +397,30 @@
status = "disabled";
};
+ i2s3: audio-controller@4000c000 {
+ compatible = "st,stm32h7-i2s";
+ #sound-dai-cells = <0>;
+ reg = <0x4000c000 0x400>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmamux1 61 0x400 0x01>,
+ <&dmamux1 62 0x400 0x01>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ spdifrx: audio-controller@4000d000 {
+ compatible = "st,stm32h7-spdifrx";
+ #sound-dai-cells = <0>;
+ reg = <0x4000d000 0x400>;
+ clocks = <&rcc SPDIF_K>;
+ clock-names = "kclk";
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmamux1 93 0x400 0x01>,
+ <&dmamux1 94 0x400 0x01>;
+ dma-names = "rx", "rx-ctrl";
+ status = "disabled";
+ };
+
usart2: serial@4000e000 {
compatible = "st,stm32h7-uart";
reg = <0x4000e000 0x400>;
@@ -487,6 +561,15 @@
reg = <0x44000000 0x400>;
clocks = <&rcc TIM1_K>;
clock-names = "int";
+ dmas = <&dmamux1 11 0x400 0x1>,
+ <&dmamux1 12 0x400 0x1>,
+ <&dmamux1 13 0x400 0x1>,
+ <&dmamux1 14 0x400 0x1>,
+ <&dmamux1 15 0x400 0x1>,
+ <&dmamux1 16 0x400 0x1>,
+ <&dmamux1 17 0x400 0x1>;
+ dma-names = "ch1", "ch2", "ch3", "ch4",
+ "up", "trig", "com";
status = "disabled";
pwm {
@@ -508,6 +591,15 @@
reg = <0x44001000 0x400>;
clocks = <&rcc TIM8_K>;
clock-names = "int";
+ dmas = <&dmamux1 47 0x400 0x1>,
+ <&dmamux1 48 0x400 0x1>,
+ <&dmamux1 49 0x400 0x1>,
+ <&dmamux1 50 0x400 0x1>,
+ <&dmamux1 51 0x400 0x1>,
+ <&dmamux1 52 0x400 0x1>,
+ <&dmamux1 53 0x400 0x1>;
+ dma-names = "ch1", "ch2", "ch3", "ch4",
+ "up", "trig", "com";
status = "disabled";
pwm {
@@ -544,6 +636,17 @@
status = "disabled";
};
+ i2s1: audio-controller@44004000 {
+ compatible = "st,stm32h7-i2s";
+ #sound-dai-cells = <0>;
+ reg = <0x44004000 0x400>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmamux1 37 0x400 0x01>,
+ <&dmamux1 38 0x400 0x01>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
spi4: spi@44005000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -565,6 +668,11 @@
reg = <0x44006000 0x400>;
clocks = <&rcc TIM15_K>;
clock-names = "int";
+ dmas = <&dmamux1 105 0x400 0x1>,
+ <&dmamux1 106 0x400 0x1>,
+ <&dmamux1 107 0x400 0x1>,
+ <&dmamux1 108 0x400 0x1>;
+ dma-names = "ch1", "up", "trig", "com";
status = "disabled";
pwm {
@@ -586,6 +694,9 @@
reg = <0x44007000 0x400>;
clocks = <&rcc TIM16_K>;
clock-names = "int";
+ dmas = <&dmamux1 109 0x400 0x1>,
+ <&dmamux1 110 0x400 0x1>;
+ dma-names = "ch1", "up";
status = "disabled";
pwm {
@@ -606,6 +717,9 @@
reg = <0x44008000 0x400>;
clocks = <&rcc TIM17_K>;
clock-names = "int";
+ dmas = <&dmamux1 111 0x400 0x1>,
+ <&dmamux1 112 0x400 0x1>;
+ dma-names = "ch1", "up";
status = "disabled";
pwm {
@@ -634,6 +748,100 @@
status = "disabled";
};
+ sai1: sai@4400a000 {
+ compatible = "st,stm32h7-sai";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x4400a000 0x400>;
+ reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rcc SAI1_R>;
+ status = "disabled";
+
+ sai1a: audio-controller@4400a004 {
+ #sound-dai-cells = <0>;
+
+ compatible = "st,stm32-sai-sub-a";
+ reg = <0x4 0x1c>;
+ clocks = <&rcc SAI1_K>;
+ clock-names = "sai_ck";
+ dmas = <&dmamux1 87 0x400 0x01>;
+ status = "disabled";
+ };
+
+ sai1b: audio-controller@4400a024 {
+ #sound-dai-cells = <0>;
+ compatible = "st,stm32-sai-sub-b";
+ reg = <0x24 0x1c>;
+ clocks = <&rcc SAI1_K>;
+ clock-names = "sai_ck";
+ dmas = <&dmamux1 88 0x400 0x01>;
+ status = "disabled";
+ };
+ };
+
+ sai2: sai@4400b000 {
+ compatible = "st,stm32h7-sai";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x4400b000 0x400>;
+ reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rcc SAI2_R>;
+ status = "disabled";
+
+ sai2a: audio-controller@4400b004 {
+ #sound-dai-cells = <0>;
+ compatible = "st,stm32-sai-sub-a";
+ reg = <0x4 0x1c>;
+ clocks = <&rcc SAI2_K>;
+ clock-names = "sai_ck";
+ dmas = <&dmamux1 89 0x400 0x01>;
+ status = "disabled";
+ };
+
+ sai2b: audio-controller@4400b024 {
+ #sound-dai-cells = <0>;
+ compatible = "st,stm32-sai-sub-b";
+ reg = <0x24 0x1c>;
+ clocks = <&rcc SAI2_K>;
+ clock-names = "sai_ck";
+ dmas = <&dmamux1 90 0x400 0x01>;
+ status = "disabled";
+ };
+ };
+
+ sai3: sai@4400c000 {
+ compatible = "st,stm32h7-sai";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x4400c000 0x400>;
+ reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rcc SAI3_R>;
+ status = "disabled";
+
+ sai3a: audio-controller@4400c004 {
+ #sound-dai-cells = <0>;
+ compatible = "st,stm32-sai-sub-a";
+ reg = <0x04 0x1c>;
+ clocks = <&rcc SAI3_K>;
+ clock-names = "sai_ck";
+ dmas = <&dmamux1 113 0x400 0x01>;
+ status = "disabled";
+ };
+
+ sai3b: audio-controller@4400c024 {
+ #sound-dai-cells = <0>;
+ compatible = "st,stm32-sai-sub-b";
+ reg = <0x24 0x1c>;
+ clocks = <&rcc SAI3_K>;
+ clock-names = "sai_ck";
+ dmas = <&dmamux1 114 0x400 0x01>;
+ status = "disabled";
+ };
+ };
+
dfsdm: dfsdm@4400d000 {
compatible = "st,stm32mp1-dfsdm";
reg = <0x4400d000 0x800>;
@@ -706,14 +914,14 @@
m_can1: can@4400e000 {
compatible = "bosch,m_can";
- reg = <0x4400e000 0x400>, <0x44011000 0x2800>;
+ reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
reg-names = "m_can", "message_ram";
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
clock-names = "hclk", "cclk";
- bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
+ bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
status = "disabled";
};
@@ -811,13 +1019,14 @@
};
sdmmc3: sdmmc@48004000 {
- compatible = "st,stm32-sdmmc2";
- reg = <0x48004000 0x400>, <0x48005000 0x400>;
- reg-names = "sdmmc", "delay";
+ compatible = "arm,pl18x", "arm,primecell";
+ arm,primecell-periphid = <0x10153180>;
+ reg = <0x48004000 0x400>;
+ reg-names = "sdmmc";
interrupts = <GIC_SPI 137 IRQ_TYPE_NONE>;
clocks = <&rcc SDMMC3_K>;
+ clock-names = "apb_pclk";
resets = <&rcc SDMMC3_R>;
- st,idma = <1>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <120000000>;
@@ -825,7 +1034,7 @@
};
usbotg_hs: usb-otg@49000000 {
- compatible = "st,stm32mp1-hsotg", "snps,dwc2";
+ compatible = "snps,dwc2";
reg = <0x49000000 0x10000>;
clocks = <&rcc USBO_K>;
clock-names = "otg";
@@ -846,6 +1055,32 @@
reg = <0x4c000000 0x400>;
clocks = <&rcc HSEM>;
clock-names = "hwspinlock";
+ };
+
+ ipcc: mailbox@4c001000 {
+ compatible = "st,stm32mp1-ipcc";
+ #mbox-cells = <1>;
+ reg = <0x4c001000 0x400>;
+ st,proc-id = <0>;
+ interrupts-extended =
+ <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <&exti 61 1>;
+ interrupt-names = "rx", "tx", "wakeup";
+ clocks = <&rcc IPCC>;
+ wakeup-source;
+ status = "disabled";
+ };
+
+ dcmi: dcmi@4c006000 {
+ compatible = "st,stm32-dcmi";
+ reg = <0x4c006000 0x400>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rcc CAMITF_R>;
+ clocks = <&rcc DCMI>;
+ clock-names = "mclk";
+ dmas = <&dmamux1 75 0x400 0x0d>;
+ dma-names = "tx";
status = "disabled";
};
@@ -856,13 +1091,6 @@
#reset-cells = <1>;
};
- rcc_reboot: rcc-reboot@50000000 {
- compatible = "syscon-reboot";
- regmap = <&rcc>;
- offset = <0x404>;
- mask = <0x1>;
- };
-
pwr: pwr@50001000 {
compatible = "st,stm32mp1-pwr", "st,stm32-pwr", "syscon", "simple-mfd";
reg = <0x50001000 0x400>;
@@ -872,7 +1100,7 @@
clocks = <&rcc PLL2_R>;
clock-names = "phyclk";
- pwr-regulators@c {
+ pwr-regulators {
compatible = "st,stm32mp1,pwr-reg";
st,tzcr = <&rcc 0x0 0x1>;
@@ -906,6 +1134,7 @@
syscfg: syscon@50020000 {
compatible = "st,stm32mp157-syscfg", "syscon";
reg = <0x50020000 0x400>;
+ clocks = <&rcc SYSCFG>;
};
lptimer2: timer@50021000 {
@@ -994,6 +1223,47 @@
status = "disabled";
};
+ sai4: sai@50027000 {
+ compatible = "st,stm32h7-sai";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x50027000 0x400>;
+ reg = <0x50027000 0x4>, <0x500273f0 0x10>;
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rcc SAI4_R>;
+ status = "disabled";
+
+ sai4a: audio-controller@50027004 {
+ #sound-dai-cells = <0>;
+ compatible = "st,stm32-sai-sub-a";
+ reg = <0x04 0x1c>;
+ clocks = <&rcc SAI4_K>;
+ clock-names = "sai_ck";
+ dmas = <&dmamux1 99 0x400 0x01>;
+ status = "disabled";
+ };
+
+ sai4b: audio-controller@50027024 {
+ #sound-dai-cells = <0>;
+ compatible = "st,stm32-sai-sub-b";
+ reg = <0x24 0x1c>;
+ clocks = <&rcc SAI4_K>;
+ clock-names = "sai_ck";
+ dmas = <&dmamux1 100 0x400 0x01>;
+ status = "disabled";
+ };
+ };
+
+ dts: thermal@50028000 {
+ compatible = "st,stm32-thermal";
+ reg = <0x50028000 0x100>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc TMPSENS>;
+ clock-names = "pclk";
+ #thermal-sensor-cells = <0>;
+ status = "disabled";
+ };
+
cryp1: cryp@54001000 {
compatible = "st,stm32mp1-cryp";
reg = <0x54001000 0x400>;
@@ -1059,26 +1329,27 @@
};
sdmmc1: sdmmc@58005000 {
- compatible = "st,stm32-sdmmc2";
- reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
- reg-names = "sdmmc", "delay";
+ compatible = "arm,pl18x", "arm,primecell";
+ arm,primecell-periphid = <0x10153180>;
+ reg = <0x58005000 0x1000>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cmd_irq";
clocks = <&rcc SDMMC1_K>;
+ clock-names = "apb_pclk";
resets = <&rcc SDMMC1_R>;
- st,idma = <1>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <120000000>;
- status = "disabled";
};
sdmmc2: sdmmc@58007000 {
- compatible = "st,stm32-sdmmc2";
- reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
- reg-names = "sdmmc", "delay";
+ compatible = "arm,pl18x", "arm,primecell";
+ arm,primecell-periphid = <0x10153180>;
+ reg = <0x58007000 0x1000>;
interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
clocks = <&rcc SDMMC2_K>;
+ clock-names = "apb_pclk";
resets = <&rcc SDMMC2_R>;
- st,idma = <1>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <120000000>;
@@ -1102,25 +1373,21 @@
compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
reg = <0x5800a000 0x2000>;
reg-names = "stmmaceth";
- interrupts-extended =
- <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
- <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
- <&exti 70 1>;
- interrupt-names = "macirq",
- "eth_wake_irq",
- "stm32_pwr_wakeup";
+ interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
clock-names = "stmmaceth",
"mac-clk-tx",
"mac-clk-rx",
- "ethstp";
+ "ethstp",
+ "syscfg-clk";
clocks = <&rcc ETHMAC>,
<&rcc ETHTX>,
<&rcc ETHRX>,
- <&rcc ETHSTP>;
+ <&rcc ETHSTP>,
+ <&rcc SYSCFG>;
st,syscon = <&syscfg 0x4>;
snps,mixed-burst;
snps,pbl = <2>;
- snps,en-tx-lpi-clockgating;
snps,axi-config = <&stmmac_axi_config_0>;
snps,tso;
status = "disabled";
@@ -1145,6 +1412,16 @@
status = "disabled";
};
+ gpu: gpu@59000000 {
+ compatible = "vivante,gc";
+ reg = <0x59000000 0x800>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc GPU>, <&rcc GPU_K>;
+ clock-names = "bus" ,"core";
+ resets = <&rcc GPU_R>;
+ status = "disabled";
+ };
+
dsi: dsi@5a000000 {
compatible = "st,stm32-dsi";
reg = <0x5a000000 0x800>;
@@ -1245,6 +1522,12 @@
reg = <0x5c005000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
+ ts_cal1: calib@5c {
+ reg = <0x5c 0x2>;
+ };
+ ts_cal2: calib@5e {
+ reg = <0x5e 0x2>;
+ };
};
i2c6: i2c@5c009000 {
@@ -1260,4 +1543,24 @@
status = "disabled";
};
};
+
+ mlahb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ dma-ranges = <0x00000000 0x38000000 0x10000>,
+ <0x10000000 0x10000000 0x60000>,
+ <0x30000000 0x30000000 0x60000>;
+
+ m4_rproc: m4@10000000 {
+ compatible = "st,stm32mp1-m4";
+ reg = <0x10000000 0x40000>,
+ <0x30000000 0x40000>,
+ <0x38000000 0x10000>;
+ resets = <&rcc MCU_R>;
+ st,syscfg-holdboot = <&rcc 0x10C 0x1>;
+ st,syscfg-tz = <&rcc 0x000 0x1>;
+ status = "disabled";
+ };
+ };
};
diff --git a/arch/arm/dts/stm32mp157xaa-pinctrl.dtsi b/arch/arm/dts/stm32mp157xaa-pinctrl.dtsi
new file mode 100644
index 0000000..875adf5e
--- /dev/null
+++ b/arch/arm/dts/stm32mp157xaa-pinctrl.dtsi
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com>
+ */
+
+#include "stm32mp157-pinctrl.dtsi"
+/ {
+ soc {
+ pinctrl: pin-controller@50002000 {
+ st,package = <STM32MP_PKG_AA>;
+
+ gpioa: gpio@50002000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@50003000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ gpioc: gpio@50004000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 32 16>;
+ };
+
+ gpiod: gpio@50005000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ gpioe: gpio@50006000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ gpiof: gpio@50007000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 80 16>;
+ };
+
+ gpiog: gpio@50008000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 96 16>;
+ };
+
+ gpioh: gpio@50009000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 112 16>;
+ };
+
+ gpioi: gpio@5000a000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 128 16>;
+ };
+
+ gpioj: gpio@5000b000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 144 16>;
+ };
+
+ gpiok: gpio@5000c000 {
+ status = "okay";
+ ngpios = <8>;
+ gpio-ranges = <&pinctrl 0 160 8>;
+ };
+ };
+
+ pinctrl_z: pin-controller-z@54004000 {
+ st,package = <STM32MP_PKG_AA>;
+
+ gpioz: gpio@54004000 {
+ status = "okay";
+ ngpios = <8>;
+ gpio-ranges = <&pinctrl_z 0 400 8>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/stm32mp157xab-pinctrl.dtsi b/arch/arm/dts/stm32mp157xab-pinctrl.dtsi
new file mode 100644
index 0000000..961fa12
--- /dev/null
+++ b/arch/arm/dts/stm32mp157xab-pinctrl.dtsi
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com>
+ */
+
+#include "stm32mp157-pinctrl.dtsi"
+/ {
+ soc {
+ pinctrl: pin-controller@50002000 {
+ st,package = <STM32MP_PKG_AB>;
+
+ gpioa: gpio@50002000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@50003000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ gpioc: gpio@50004000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 32 16>;
+ };
+
+ gpiod: gpio@50005000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ gpioe: gpio@50006000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ gpiof: gpio@50007000 {
+ status = "okay";
+ ngpios = <6>;
+ gpio-ranges = <&pinctrl 6 86 6>;
+ };
+
+ gpiog: gpio@50008000 {
+ status = "okay";
+ ngpios = <10>;
+ gpio-ranges = <&pinctrl 6 102 10>;
+ };
+
+ gpioh: gpio@50009000 {
+ status = "okay";
+ ngpios = <2>;
+ gpio-ranges = <&pinctrl 0 112 2>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/stm32mp157xac-pinctrl.dtsi b/arch/arm/dts/stm32mp157xac-pinctrl.dtsi
new file mode 100644
index 0000000..26600f1
--- /dev/null
+++ b/arch/arm/dts/stm32mp157xac-pinctrl.dtsi
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com>
+ */
+
+#include "stm32mp157-pinctrl.dtsi"
+/ {
+ soc {
+ pinctrl: pin-controller@50002000 {
+ st,package = <STM32MP_PKG_AC>;
+
+ gpioa: gpio@50002000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@50003000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ gpioc: gpio@50004000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 32 16>;
+ };
+
+ gpiod: gpio@50005000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ gpioe: gpio@50006000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ gpiof: gpio@50007000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 80 16>;
+ };
+
+ gpiog: gpio@50008000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 96 16>;
+ };
+
+ gpioh: gpio@50009000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 112 16>;
+ };
+
+ gpioi: gpio@5000a000 {
+ status = "okay";
+ ngpios = <12>;
+ gpio-ranges = <&pinctrl 0 128 12>;
+ };
+ };
+
+ pinctrl_z: pin-controller-z@54004000 {
+ st,package = <STM32MP_PKG_AC>;
+
+ gpioz: gpio@54004000 {
+ status = "okay";
+ ngpios = <8>;
+ gpio-ranges = <&pinctrl_z 0 400 8>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/stm32mp157xad-pinctrl.dtsi b/arch/arm/dts/stm32mp157xad-pinctrl.dtsi
new file mode 100644
index 0000000..910113f
--- /dev/null
+++ b/arch/arm/dts/stm32mp157xad-pinctrl.dtsi
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com>
+ */
+
+#include "stm32mp157-pinctrl.dtsi"
+/ {
+ soc {
+ pinctrl: pin-controller@50002000 {
+ st,package = <STM32MP_PKG_AD>;
+
+ gpioa: gpio@50002000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@50003000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ gpioc: gpio@50004000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 32 16>;
+ };
+
+ gpiod: gpio@50005000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ gpioe: gpio@50006000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ gpiof: gpio@50007000 {
+ status = "okay";
+ ngpios = <6>;
+ gpio-ranges = <&pinctrl 6 86 6>;
+ };
+
+ gpiog: gpio@50008000 {
+ status = "okay";
+ ngpios = <10>;
+ gpio-ranges = <&pinctrl 6 102 10>;
+ };
+
+ gpioh: gpio@50009000 {
+ status = "okay";
+ ngpios = <2>;
+ gpio-ranges = <&pinctrl 0 112 2>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/sun8i-h3-beelink-x2.dts b/arch/arm/dts/sun8i-h3-beelink-x2.dts
new file mode 100644
index 0000000..25540b7
--- /dev/null
+++ b/arch/arm/dts/sun8i-h3-beelink-x2.dts
@@ -0,0 +1,216 @@
+/*
+ * Copyright (C) 2017 Marcus Cooper <codekipper@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-h3.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Beelink X2";
+ compatible = "roofull,beelink-x2", "allwinner,sun8i-h3";
+
+ aliases {
+ serial0 = &uart0;
+ ethernet0 = &emac;
+ ethernet1 = &sdiowifi;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ blue {
+ label = "beelink-x2:blue:pwr";
+ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
+ default-state = "on";
+ };
+
+ red {
+ label = "beelink-x2:red:standby";
+ gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */
+ };
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
+ };
+
+ sound_spdif {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "On-board SPDIF";
+
+ simple-audio-card,cpu {
+ sound-dai = <&spdif>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&spdif_out>;
+ };
+ };
+
+ spdif_out: spdif-out {
+ #sound-dai-cells = <0>;
+ compatible = "linux,spdif-dit";
+ };
+};
+
+&de {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_pins_a>;
+ status = "okay";
+};
+
+&mmc0 {
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ /*
+ * Explicitly define the sdio device, so that we can add an ethernet
+ * alias for it (which e.g. makes u-boot set a mac-address).
+ */
+ sdiowifi: sdio_wifi@1 {
+ reg = <1>;
+ };
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+®_usb0_vbus {
+ gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
+ status = "okay";
+};
+
+&spdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spdif_tx_pins_a>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbphy {
+ /* USB VBUS is always on except for the OTG port */
+ status = "okay";
+ usb0_id_det-gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA07 */
+ usb0_vbus-supply = <®_usb0_vbus>;
+};
diff --git a/arch/arm/dts/tegra124-apalis.dts b/arch/arm/dts/tegra124-apalis.dts
index a962c0a..08184ab 100644
--- a/arch/arm/dts/tegra124-apalis.dts
+++ b/arch/arm/dts/tegra124-apalis.dts
@@ -1,5 +1,5 @@
/*
- * Copyright 2016 Toradex AG
+ * Copyright 2016-2019 Toradex AG
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@@ -230,19 +230,21 @@
};
/* Apalis GPIO */
- ddc_scl_pv4 {
- nvidia,pins = "ddc_scl_pv4";
+ usb_vbus_en0_pn4 {
+ nvidia,pins = "usb_vbus_en0_pn4";
nvidia,function = "rsvd2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
- ddc_sda_pv5 {
- nvidia,pins = "ddc_sda_pv5";
+ usb_vbus_en1_pn5 {
+ nvidia,pins = "usb_vbus_en1_pn5";
nvidia,function = "rsvd2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
pex_l0_rst_n_pdd1 {
nvidia,pins = "pex_l0_rst_n_pdd1";
@@ -333,24 +335,6 @@
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
};
- /* Apalis I2C2 (DDC) */
- gen2_i2c_scl_pt5 {
- nvidia,pins = "gen2_i2c_scl_pt5";
- nvidia,function = "i2c2";
- nvidia,pull = <TEGRA_PIN_PULL_NONE>;
- nvidia,tristate = <TEGRA_PIN_DISABLE>;
- nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,open-drain = <TEGRA_PIN_ENABLE>;
- };
- gen2_i2c_sda_pt6 {
- nvidia,pins = "gen2_i2c_sda_pt6";
- nvidia,function = "i2c2";
- nvidia,pull = <TEGRA_PIN_PULL_NONE>;
- nvidia,tristate = <TEGRA_PIN_DISABLE>;
- nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,open-drain = <TEGRA_PIN_ENABLE>;
- };
-
/* Apalis I2C3 (CAM) */
cam_i2c_scl_pbb1 {
nvidia,pins = "cam_i2c_scl_pbb1";
@@ -369,6 +353,24 @@
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
};
+ /* Apalis I2C4 (DDC) */
+ ddc_scl_pv4 {
+ nvidia,pins = "ddc_scl_pv4";
+ nvidia,function = "i2c4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+ };
+ ddc_sda_pv5 {
+ nvidia,pins = "ddc_sda_pv5";
+ nvidia,function = "i2c4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+ };
+
/* Apalis MMC1 */
sdmmc1_cd_n_pv3 { /* CD# GPIO */
nvidia,pins = "sdmmc1_wp_n_pv3";
@@ -470,12 +472,12 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
- /* PWM3 active on pu6 being Apalis BKL1_PWM */
+ /* PWM3 active on pu6 being Apalis BKL1_PWM as well */
ph3 {
nvidia,pins = "ph3";
- nvidia,function = "gmi";
- nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
- nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,function = "pwm3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
@@ -736,8 +738,8 @@
};
/* Apalis USBH_EN */
- usb_vbus_en1_pn5 {
- nvidia,pins = "usb_vbus_en1_pn5";
+ gen2_i2c_sda_pt6 {
+ nvidia,pins = "gen2_i2c_sda_pt6";
nvidia,function = "rsvd2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
@@ -755,8 +757,8 @@
};
/* Apalis USBO1_EN */
- usb_vbus_en0_pn4 {
- nvidia,pins = "usb_vbus_en0_pn4";
+ gen2_i2c_scl_pt5 {
+ nvidia,pins = "gen2_i2c_scl_pt5";
nvidia,function = "rsvd2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
@@ -1501,10 +1503,14 @@
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
- pv0 { /* NC */
+ /*
+ * PCB Version Indication: V1.2 and later have GPIO_PV0
+ * wired to GND, was NC before
+ */
+ pv0 {
nvidia,pins = "pv0";
nvidia,function = "rsvd1";
- nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
@@ -1630,13 +1636,7 @@
};
};
- /*
- * GEN2_I2C: I2C2_SDA/SCL (DDC) on MXM3 pin 205/207 (e.g. display EDID)
- */
- hdmi_ddc: i2c@7000c400 {
- status = "okay";
- clock-frequency = <10000>;
- };
+ /* GEN2_I2C: unused */
/*
* CAM_I2C: I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor
@@ -1647,7 +1647,14 @@
clock-frequency = <400000>;
};
- /* I2C4 (DDC): unused */
+ /*
+ * I2C4 (DDC): I2C4_SDA/SCL (DDC) on MXM3 pin 205/207
+ * (e.g. display EDID)
+ */
+ hdmi_ddc: i2c@7000c700 {
+ status = "okay";
+ clock-frequency = <10000>;
+ };
/* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */
i2c@7000d000 {
@@ -2112,7 +2119,7 @@
regulator-name = "VCC_USBO1";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <®_5v0>;
};
@@ -2123,7 +2130,7 @@
regulator-name = "VCC_USBH(2A|2C|2D|3|4)";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio TEGRA_GPIO(T, 6) GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <®_5v0>;
};
diff --git a/arch/arm/dts/uniphier-ld11.dtsi b/arch/arm/dts/uniphier-ld11.dtsi
index a3cd475..337a353 100644
--- a/arch/arm/dts/uniphier-ld11.dtsi
+++ b/arch/arm/dts/uniphier-ld11.dtsi
@@ -8,8 +8,6 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/uniphier-gpio.h>
-/memreserve/ 0x80000000 0x02000000;
-
/ {
compatible = "socionext,uniphier-ld11";
#address-cells = <2>;
@@ -110,6 +108,17 @@
<1 10 4>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ secure-memory@81000000 {
+ reg = <0x0 0x81000000 0x0 0x01000000>;
+ no-map;
+ };
+ };
+
soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
diff --git a/arch/arm/dts/uniphier-ld20.dtsi b/arch/arm/dts/uniphier-ld20.dtsi
index baf2326..3721110 100644
--- a/arch/arm/dts/uniphier-ld20.dtsi
+++ b/arch/arm/dts/uniphier-ld20.dtsi
@@ -9,8 +9,6 @@
#include <dt-bindings/gpio/uniphier-gpio.h>
#include <dt-bindings/thermal/thermal.h>
-/memreserve/ 0x80000000 0x02000000;
-
/ {
compatible = "socionext,uniphier-ld20";
#address-cells = <2>;
@@ -215,6 +213,17 @@
};
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ secure-memory@81000000 {
+ reg = <0x0 0x81000000 0x0 0x01000000>;
+ no-map;
+ };
+ };
+
soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
diff --git a/arch/arm/dts/uniphier-pxs3.dtsi b/arch/arm/dts/uniphier-pxs3.dtsi
index 961d4d3..b1aff28 100644
--- a/arch/arm/dts/uniphier-pxs3.dtsi
+++ b/arch/arm/dts/uniphier-pxs3.dtsi
@@ -8,8 +8,6 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/uniphier-gpio.h>
-/memreserve/ 0x80000000 0x02000000;
-
/ {
compatible = "socionext,uniphier-pxs3";
#address-cells = <2>;
@@ -138,6 +136,17 @@
<1 10 4>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ secure-memory@81000000 {
+ reg = <0x0 0x81000000 0x0 0x01000000>;
+ no-map;
+ };
+ };
+
soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
diff --git a/arch/arm/dts/vf-colibri-u-boot.dtsi b/arch/arm/dts/vf-colibri-u-boot.dtsi
index db86739..2294ee9 100644
--- a/arch/arm/dts/vf-colibri-u-boot.dtsi
+++ b/arch/arm/dts/vf-colibri-u-boot.dtsi
@@ -21,3 +21,7 @@
&uart0 {
u-boot,dm-pre-reloc;
};
+
+&dcu0 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/vf-colibri.dtsi b/arch/arm/dts/vf-colibri.dtsi
index 91ca4e4..9de4b28 100644
--- a/arch/arm/dts/vf-colibri.dtsi
+++ b/arch/arm/dts/vf-colibri.dtsi
@@ -14,6 +14,7 @@
aliases {
usb0 = &ehci0; /* required for ums */
+ display1 = &dcu0;
};
reg_usbh_vbus: regulator-usbh-vbus {
@@ -241,3 +242,7 @@
pinctrl-0 = <&pinctrl_uart0>;
status = "okay";
};
+
+&dcu0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/vf.dtsi b/arch/arm/dts/vf.dtsi
index 5e3b2c5..5f69d0f 100644
--- a/arch/arm/dts/vf.dtsi
+++ b/arch/arm/dts/vf.dtsi
@@ -145,6 +145,12 @@
#gpio-cells = <2>;
};
+ dcu0: dcu@40058000 {
+ compatible = "fsl,vf610-dcu";
+ reg = <0x40058000 0x1200>;
+ status = "disabled";
+ };
+
ehci0: ehci@40034000 {
compatible = "fsl,vf610-usb";
reg = <0x40034000 0x800>;
diff --git a/arch/arm/dts/zynqmp-zc1275-revA.dts b/arch/arm/dts/zynqmp-zc1275-revA.dts
deleted file mode 100644
index 82c30a3..0000000
--- a/arch/arm/dts/zynqmp-zc1275-revA.dts
+++ /dev/null
@@ -1,72 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * dts file for Xilinx ZynqMP ZC1275
- *
- * (C) Copyright 2017 - 2018, Xilinx, Inc.
- *
- * Michal Simek <michal.simek@xilinx.com>
- * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
- */
-
-/dts-v1/;
-
-#include "zynqmp.dtsi"
-#include "zynqmp-clk-ccf.dtsi"
-
-/ {
- model = "ZynqMP ZC1275 RevA";
- compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp";
-
- aliases {
- serial0 = &uart0;
- serial1 = &dcc;
- spi0 = &qspi;
- };
-
- chosen {
- bootargs = "earlycon";
- stdout-path = "serial0:115200n8";
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x80000000>;
- };
-};
-
-&dcc {
- status = "okay";
-};
-
-&qspi {
- status = "okay";
- flash@0 {
- compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x0>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
- spi-max-frequency = <108000000>; /* Based on DC1 spec */
- partition@qspi-fsbl-uboot { /* for testing purpose */
- label = "qspi-fsbl-uboot";
- reg = <0x0 0x100000>;
- };
- partition@qspi-linux { /* for testing purpose */
- label = "qspi-linux";
- reg = <0x100000 0x500000>;
- };
- partition@qspi-device-tree { /* for testing purpose */
- label = "qspi-device-tree";
- reg = <0x600000 0x20000>;
- };
- partition@qspi-rootfs { /* for testing purpose */
- label = "qspi-rootfs";
- reg = <0x620000 0x5E0000>;
- };
- };
-};
-
-&uart0 {
- status = "okay";
-};
diff --git a/arch/arm/dts/zynqmp-zc1275-revB.dts b/arch/arm/dts/zynqmp-zc1275-revB.dts
deleted file mode 100644
index 0473503..0000000
--- a/arch/arm/dts/zynqmp-zc1275-revB.dts
+++ /dev/null
@@ -1,79 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * dts file for Xilinx ZynqMP ZC1275 RevB
- *
- * (C) Copyright 2018, Xilinx, Inc.
- *
- * Michal Simek <michal.simek@xilinx.com>
- * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
- */
-
-/dts-v1/;
-
-#include "zynqmp.dtsi"
-#include "zynqmp-clk-ccf.dtsi"
-
-/ {
- model = "ZynqMP ZC1275 RevB";
- compatible = "xlnx,zynqmp-zc1275-revB", "xlnx,zynqmp-zc1275", "xlnx,zynqmp";
-
- aliases {
- serial0 = &uart0;
- serial1 = &dcc;
- spi0 = &qspi;
- mmc0 = &sdhci1;
- };
-
- chosen {
- bootargs = "earlycon";
- stdout-path = "serial0:115200n8";
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x80000000>;
- };
-};
-
-&dcc {
- status = "okay";
-};
-
-&qspi {
- status = "okay";
- flash@0 {
- compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x0>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <1>;
- spi-max-frequency = <108000000>; /* Based on DC1 spec */
- partition@qspi-fsbl-uboot { /* for testing purpose */
- label = "qspi-fsbl-uboot";
- reg = <0x0 0x100000>;
- };
- partition@qspi-linux { /* for testing purpose */
- label = "qspi-linux";
- reg = <0x100000 0x500000>;
- };
- partition@qspi-device-tree { /* for testing purpose */
- label = "qspi-device-tree";
- reg = <0x600000 0x20000>;
- };
- partition@qspi-rootfs { /* for testing purpose */
- label = "qspi-rootfs";
- reg = <0x620000 0x5E0000>;
- };
- };
-};
-
-&uart0 {
- status = "okay";
-};
-
-&sdhci1 {
- status = "okay";
- no-1-8-v;
- xlnx,mio_bank = <1>;
-};
diff --git a/arch/arm/dts/zynqmp-zcu1275-revA.dts b/arch/arm/dts/zynqmp-zcu1275-revA.dts
new file mode 100644
index 0000000..c22de57
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU1275
+ *
+ * (C) Copyright 2017 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+
+/ {
+ model = "ZynqMP ZCU1275 RevA";
+ compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275",
+ "xlnx,zynqmp";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &dcc;
+ spi0 = &qspi;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+&dcc {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+ flash@0 {
+ compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
+ spi-max-frequency = <108000000>; /* Based on DC1 spec */
+ partition@qspi-fsbl-uboot { /* for testing purpose */
+ label = "qspi-fsbl-uboot";
+ reg = <0x0 0x100000>;
+ };
+ partition@qspi-linux { /* for testing purpose */
+ label = "qspi-linux";
+ reg = <0x100000 0x500000>;
+ };
+ partition@qspi-device-tree { /* for testing purpose */
+ label = "qspi-device-tree";
+ reg = <0x600000 0x20000>;
+ };
+ partition@qspi-rootfs { /* for testing purpose */
+ label = "qspi-rootfs";
+ reg = <0x620000 0x5E0000>;
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/zynqmp-zcu1275-revB.dts b/arch/arm/dts/zynqmp-zcu1275-revB.dts
new file mode 100644
index 0000000..34c4bec
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zcu1275-revB.dts
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP ZCU1275 RevB
+ *
+ * (C) Copyright 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+
+/ {
+ model = "ZynqMP ZCU1275 RevB";
+ compatible = "xlnx,zynqmp-zcu1275-revB", "xlnx,zynqmp-zcu1275",
+ "xlnx,zynqmp";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &dcc;
+ spi0 = &qspi;
+ mmc0 = &sdhci1;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+&dcc {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+ flash@0 {
+ compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ spi-max-frequency = <108000000>; /* Based on DC1 spec */
+ partition@qspi-fsbl-uboot { /* for testing purpose */
+ label = "qspi-fsbl-uboot";
+ reg = <0x0 0x100000>;
+ };
+ partition@qspi-linux { /* for testing purpose */
+ label = "qspi-linux";
+ reg = <0x100000 0x500000>;
+ };
+ partition@qspi-device-tree { /* for testing purpose */
+ label = "qspi-device-tree";
+ reg = <0x600000 0x20000>;
+ };
+ partition@qspi-rootfs { /* for testing purpose */
+ label = "qspi-rootfs";
+ reg = <0x620000 0x5E0000>;
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&sdhci1 {
+ status = "okay";
+ no-1-8-v;
+ xlnx,mio_bank = <1>;
+};
diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
index 4988ced..8db4901 100644
--- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
+++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
@@ -22,6 +22,8 @@
#define SCU_MPLL_POST_MASK (0x3f << SCU_MPLL_POST_SHIFT)
#define SCU_PCLK_DIV_SHIFT 23
#define SCU_PCLK_DIV_MASK (7 << SCU_PCLK_DIV_SHIFT)
+#define SCU_SDCLK_DIV_SHIFT 12
+#define SCU_SDCLK_DIV_MASK (7 << SCU_SDCLK_DIV_SHIFT)
#define SCU_HPLL_DENUM_SHIFT 0
#define SCU_HPLL_DENUM_MASK 0x1f
#define SCU_HPLL_NUM_SHIFT 5
@@ -107,6 +109,7 @@
#define SCU_CLKSTOP_MAC1 (1 << 20)
#define SCU_CLKSTOP_MAC2 (1 << 21)
+#define SCU_CLKSTOP_SDCLK (1 << 27)
#define SCU_D2PLL_EXT1_OFF (1 << 0)
#define SCU_D2PLL_EXT1_BYPASS (1 << 1)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index eb21c09..a83c70e 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -178,8 +178,10 @@
#elif defined(CONFIG_ARCH_LX2160A)
#define TZPC_BASE 0x02200000
#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
+#if !defined(CONFIG_DM_I2C)
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_EARLY_INIT
+#endif
#define SRDS_MAX_LANES 8
#ifndef L1_CACHE_BYTES
#define L1_CACHE_SHIFT 6
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
index f971af8..37e2fe4 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
@@ -17,6 +17,7 @@
u32 reg;
phys_addr_t compat_addr;
phys_addr_t reg_addr;
+ bool le;
};
struct fman_icid_id_table {
@@ -30,18 +31,35 @@
void set_icids(void);
void fdt_fixup_icid(void *blob);
-#define SET_ICID_ENTRY(name, idA, regA, addr, compataddr) \
+#define SET_ICID_ENTRY(name, idA, regA, addr, compataddr, _le) \
{ .compat = name, \
.id = idA, \
.reg = regA, \
.compat_addr = compataddr, \
.reg_addr = addr, \
+ .le = _le \
}
+#ifdef CONFIG_SYS_FSL_SEC_LE
+#define SEC_IS_LE true
+#elif defined(CONFIG_SYS_FSL_SEC_BE)
+#define SEC_IS_LE false
+#endif
+
+#ifdef CONFIG_FSL_LSCH2
+
+#ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE
+#define SCFG_IS_LE true
+#elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE)
+#define SCFG_IS_LE false
+#endif
+
+#define QDMA_IS_LE false
+
#define SET_SCFG_ICID(compat, streamid, name, compataddr) \
SET_ICID_ENTRY(compat, streamid, (((streamid) << 24) | (1 << 23)), \
offsetof(struct ccsr_scfg, name) + CONFIG_SYS_FSL_SCFG_ADDR, \
- compataddr)
+ compataddr, SCFG_IS_LE)
#define SET_USB_ICID(usb_num, compat, streamid) \
SET_SCFG_ICID(compat, streamid, usb##usb_num##_icid,\
@@ -55,14 +73,6 @@
SET_SCFG_ICID("fsl,esdhc", streamid, sdhc_icid,\
CONFIG_SYS_FSL_ESDHC_ADDR)
-#define SET_QDMA_ICID(compat, streamid) \
- SET_ICID_ENTRY(compat, streamid, (1 << 31) | (streamid), \
- QDMA_BASE_ADDR + QMAN_CQSIDR_REG, \
- QDMA_BASE_ADDR), \
- SET_ICID_ENTRY(NULL, streamid, (1 << 31) | (streamid), \
- QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \
- QDMA_BASE_ADDR)
-
#define SET_EDMA_ICID(streamid) \
SET_SCFG_ICID("fsl,vf610-edma", streamid, edma_icid,\
EDMA_BASE_ADDR)
@@ -81,22 +91,78 @@
SET_ICID_ENTRY("fsl,qman", streamid, streamid, \
offsetof(struct ccsr_qman, liodnr) + \
CONFIG_SYS_FSL_QMAN_ADDR, \
- CONFIG_SYS_FSL_QMAN_ADDR)
+ CONFIG_SYS_FSL_QMAN_ADDR, false)
#define SET_BMAN_ICID(streamid) \
SET_ICID_ENTRY("fsl,bman", streamid, streamid, \
offsetof(struct ccsr_bman, liodnr) + \
CONFIG_SYS_FSL_BMAN_ADDR, \
- CONFIG_SYS_FSL_BMAN_ADDR)
+ CONFIG_SYS_FSL_BMAN_ADDR, false)
#define SET_FMAN_ICID_ENTRY(_port_id, streamid) \
{ .port_id = (_port_id), .icid = (streamid) }
+#define SEC_ICID_REG_VAL(streamid) (((streamid) << 16) | (streamid))
+
#define SET_SEC_QI_ICID(streamid) \
SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \
0, offsetof(ccsr_sec_t, qilcr_ls) + \
CONFIG_SYS_FSL_SEC_ADDR, \
- CONFIG_SYS_FSL_SEC_ADDR)
+ CONFIG_SYS_FSL_SEC_ADDR, SEC_IS_LE)
+
+extern struct fman_icid_id_table fman_icid_tbl[];
+extern int fman_icid_tbl_sz;
+
+#else /* CONFIG_FSL_LSCH2 */
+
+#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
+#define GUR_IS_LE true
+#elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE)
+#define GUR_IS_LE false
+#endif
+
+#define QDMA_IS_LE true
+
+#define SET_GUR_ICID(compat, streamid, name, compataddr) \
+ SET_ICID_ENTRY(compat, streamid, streamid, \
+ offsetof(struct ccsr_gur, name) + CONFIG_SYS_FSL_GUTS_ADDR, \
+ compataddr, GUR_IS_LE)
+
+#define SET_USB_ICID(usb_num, compat, streamid) \
+ SET_GUR_ICID(compat, streamid, usb##usb_num##_amqr,\
+ CONFIG_SYS_XHCI_USB##usb_num##_ADDR)
+
+#define SET_SATA_ICID(sata_num, compat, streamid) \
+ SET_GUR_ICID(compat, streamid, sata##sata_num##_amqr, \
+ AHCI_BASE_ADDR##sata_num)
+
+#define SET_SDHC_ICID(sdhc_num, streamid) \
+ SET_GUR_ICID("fsl,esdhc", streamid, sdmm##sdhc_num##_amqr,\
+ FSL_ESDHC##sdhc_num##_BASE_ADDR)
+
+#define SET_EDMA_ICID(streamid) \
+ SET_GUR_ICID("fsl,vf610-edma", streamid, spare3_amqr,\
+ EDMA_BASE_ADDR)
+
+#define SET_GPU_ICID(compat, streamid) \
+ SET_GUR_ICID(compat, streamid, misc1_amqr,\
+ GPU_BASE_ADDR)
+
+#define SET_DISPLAY_ICID(streamid) \
+ SET_GUR_ICID("arm,mali-dp500", streamid, spare2_amqr,\
+ DISPLAY_BASE_ADDR)
+
+#define SEC_ICID_REG_VAL(streamid) (streamid)
+
+#endif /* CONFIG_FSL_LSCH2 */
+
+#define SET_QDMA_ICID(compat, streamid) \
+ SET_ICID_ENTRY(compat, streamid, (1 << 31) | (streamid), \
+ QDMA_BASE_ADDR + QMAN_CQSIDR_REG, \
+ QDMA_BASE_ADDR, QDMA_IS_LE), \
+ SET_ICID_ENTRY(NULL, streamid, (1 << 31) | (streamid), \
+ QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \
+ QDMA_BASE_ADDR, QDMA_IS_LE)
#define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \
SET_ICID_ENTRY( \
@@ -106,24 +172,22 @@
? NULL \
: "fsl,sec-v4.0-job-ring"), \
streamid, \
- (((streamid) << 16) | (streamid)), \
+ SEC_ICID_REG_VAL(streamid), \
offsetof(ccsr_sec_t, jrliodnr[jr_num].ls) + \
CONFIG_SYS_FSL_SEC_ADDR, \
- FSL_SEC_JR##jr_num##_BASE_ADDR)
+ FSL_SEC_JR##jr_num##_BASE_ADDR, SEC_IS_LE)
#define SET_SEC_DECO_ICID_ENTRY(deco_num, streamid) \
- SET_ICID_ENTRY(NULL, streamid, (((streamid) << 16) | (streamid)), \
+ SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \
offsetof(ccsr_sec_t, decoliodnr[deco_num].ls) + \
- CONFIG_SYS_FSL_SEC_ADDR, 0)
+ CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
#define SET_SEC_RTIC_ICID_ENTRY(rtic_num, streamid) \
- SET_ICID_ENTRY(NULL, streamid, (((streamid) << 16) | (streamid)), \
+ SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \
offsetof(ccsr_sec_t, rticliodnr[rtic_num].ls) + \
- CONFIG_SYS_FSL_SEC_ADDR, 0)
+ CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
extern struct icid_id_table icid_tbl[];
-extern struct fman_icid_id_table fman_icid_tbl[];
extern int icid_tbl_sz;
-extern int fman_icid_tbl_sz;
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index b4b7c34..3a59abb 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -180,7 +180,7 @@
unsigned long freq_systembus;
unsigned long freq_ddrbus;
unsigned long freq_localbus;
- unsigned long freq_sdhc;
+ unsigned long freq_cga_m2;
#ifdef CONFIG_SYS_DPAA_FMAN
unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index ee9b33b..4f05047 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -25,6 +25,8 @@
#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000)
#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000)
+#define FSL_ESDHC1_BASE_ADDR CONFIG_SYS_FSL_ESDHC_ADDR
+#define FSL_ESDHC2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01150000)
#ifndef CONFIG_NXP_LSCH3_2
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
#endif
@@ -79,20 +81,41 @@
#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110)
#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114)
+/* EDMA */
+#define EDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x012c0000)
+
/* SATA */
#define AHCI_BASE_ADDR1 (CONFIG_SYS_IMMR + 0x02200000)
#define AHCI_BASE_ADDR2 (CONFIG_SYS_IMMR + 0x02210000)
+/* QDMA */
+#define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000)
+#define QMAN_CQSIDR_REG 0x20a80
+
+/* DISPLAY */
+#define DISPLAY_BASE_ADDR (CONFIG_SYS_IMMR + 0x0e080000)
+
+/* GPU */
+#define GPU_BASE_ADDR (CONFIG_SYS_IMMR + 0x0e0c0000)
+
/* SFP */
#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
/* SEC */
#define CONFIG_SYS_FSL_SEC_OFFSET 0x07000000ull
#define CONFIG_SYS_FSL_JR0_OFFSET 0x07010000ull
+#define FSL_SEC_JR0_OFFSET CONFIG_SYS_FSL_JR0_OFFSET
+#define FSL_SEC_JR1_OFFSET 0x07020000ull
+#define FSL_SEC_JR2_OFFSET 0x07030000ull
+#define FSL_SEC_JR3_OFFSET 0x07040000ull
#define CONFIG_SYS_FSL_SEC_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
#define CONFIG_SYS_FSL_JR0_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
+#define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET)
+#define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET)
+#define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET)
+#define FSL_SEC_JR3_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR3_OFFSET)
#ifdef CONFIG_TFABOOT
#ifdef CONFIG_NXP_LSCH3_2
@@ -255,6 +278,7 @@
/* frequency of platform PLL */
unsigned long freq_systembus;
unsigned long freq_ddrbus;
+ unsigned long freq_cga_m2;
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
unsigned long freq_ddrbus2;
#endif
@@ -417,7 +441,8 @@
u32 usb2_amqr;
u8 res_528[0x530-0x528]; /* add more registers when needed */
u32 sdmm1_amqr;
- u8 res_534[0x550-0x534]; /* add more registers when needed */
+ u32 sdmm2_amqr;
+ u8 res_538[0x550 - 0x538]; /* add more registers when needed */
u32 sata1_amqr;
u32 sata2_amqr;
u8 res_558[0x570-0x558]; /* add more registers when needed */
@@ -425,7 +450,8 @@
u8 res_574[0x590-0x574]; /* add more registers when needed */
u32 spare1_amqr;
u32 spare2_amqr;
- u8 res_598[0x620-0x598]; /* add more registers when needed */
+ u32 spare3_amqr;
+ u8 res_59c[0x620 - 0x59c]; /* add more registers when needed */
u32 gencr[7]; /* General Control Registers */
u8 res_63c[0x640-0x63c]; /* add more registers when needed */
u32 cgensr1; /* Core General Status Register */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
index c53cc57..93bdcc4 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
@@ -76,7 +76,7 @@
#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
#define FSL_DMA_STREAM_ID 6
-#elif defined(CONFIG_ARCH_LS1088A)
+#elif defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A)
#define FSL_DMA_STREAM_ID 5
#endif
@@ -98,4 +98,15 @@
#define FSL_DPAA2_STREAM_ID_START 23
#define FSL_DPAA2_STREAM_ID_END 63
+#define FSL_SEC_STREAM_ID 64
+#define FSL_SEC_JR1_STREAM_ID 65
+#define FSL_SEC_JR2_STREAM_ID 66
+#define FSL_SEC_JR3_STREAM_ID 67
+#define FSL_SEC_JR4_STREAM_ID 68
+
+#define FSL_SDMMC2_STREAM_ID 69
+#define FSL_EDMA_STREAM_ID 70
+#define FSL_GPU_STREAM_ID 71
+#define FSL_DISPLAY_STREAM_ID 72
+
#endif
diff --git a/arch/arm/include/asm/arch-hi3660/hi3660.h b/arch/arm/include/asm/arch-hi3660/hi3660.h
new file mode 100644
index 0000000..3ca0951
--- /dev/null
+++ b/arch/arm/include/asm/arch-hi3660/hi3660.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Linaro
+ * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ */
+
+#ifndef __HI3660_H__
+#define __HI3660_H__
+
+#define HI3660_UART6_BASE 0xfff32000
+
+#define PMU_REG_BASE 0xfff34000
+#define PMIC_HARDWARE_CTRL0 (PMU_REG_BASE + (0x0C5 << 2))
+
+#define SCTRL_REG_BASE 0xfff0a000
+#define SCTRL_SCFPLLCTRL0 (SCTRL_REG_BASE + 0x120)
+#define SCTRL_SCFPLLCTRL0_FPLL0_EN BIT(0)
+
+#define CRG_REG_BASE 0xfff35000
+#define CRG_PEREN2 (CRG_REG_BASE + 0x020)
+#define CRG_PERDIS2 (CRG_REG_BASE + 0x024)
+#define CRG_PERCLKEN2 (CRG_REG_BASE + 0x028)
+#define CRG_PERSTAT2 (CRG_REG_BASE + 0x02C)
+#define CRG_PEREN4 (CRG_REG_BASE + 0x040)
+#define CRG_PERDIS4 (CRG_REG_BASE + 0x044)
+#define CRG_PERCLKEN4 (CRG_REG_BASE + 0x048)
+#define CRG_PERSTAT4 (CRG_REG_BASE + 0x04C)
+#define CRG_PERRSTEN2 (CRG_REG_BASE + 0x078)
+#define CRG_PERRSTDIS2 (CRG_REG_BASE + 0x07C)
+#define CRG_PERRSTSTAT2 (CRG_REG_BASE + 0x080)
+#define CRG_PERRSTEN3 (CRG_REG_BASE + 0x084)
+#define CRG_PERRSTDIS3 (CRG_REG_BASE + 0x088)
+#define CRG_PERRSTSTAT3 (CRG_REG_BASE + 0x08C)
+#define CRG_PERRSTEN4 (CRG_REG_BASE + 0x090)
+#define CRG_PERRSTDIS4 (CRG_REG_BASE + 0x094)
+#define CRG_PERRSTSTAT4 (CRG_REG_BASE + 0x098)
+#define CRG_ISOEN (CRG_REG_BASE + 0x144)
+#define CRG_ISODIS (CRG_REG_BASE + 0x148)
+#define CRG_ISOSTAT (CRG_REG_BASE + 0x14C)
+
+#define PINMUX4_BASE 0xfff11000
+#define PINMUX4_SDDET (PINMUX4_BASE + 0x60)
+
+#define PINCONF3_BASE 0xff37e800
+#define PINCONF3_SDCLK (PINCONF3_BASE + 0x00)
+#define PINCONF3_SDCMD (PINCONF3_BASE + 0x04)
+#define PINCONF3_SDDATA0 (PINCONF3_BASE + 0x08)
+#define PINCONF3_SDDATA1 (PINCONF3_BASE + 0x0c)
+#define PINCONF3_SDDATA2 (PINCONF3_BASE + 0x10)
+#define PINCONF3_SDDATA3 (PINCONF3_BASE + 0x14)
+
+#endif /*__HI3660_H__*/
diff --git a/arch/arm/include/asm/arch-imx8/sci/sci.h b/arch/arm/include/asm/arch-imx8/sci/sci.h
index 9737769..901b90d 100644
--- a/arch/arm/include/asm/arch-imx8/sci/sci.h
+++ b/arch/arm/include/asm/arch-imx8/sci/sci.h
@@ -72,6 +72,8 @@
void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status);
void sc_misc_build_info(sc_ipc_t ipc, u32 *build, u32 *commit);
int sc_misc_otp_fuse_read(sc_ipc_t ipc, u32 word, u32 *val);
+int sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, sc_misc_temp_t temp,
+ s16 *celsius, s8 *tenths);
/* RM API */
sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr);
diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h
index 5d17b55..3629eb6 100644
--- a/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h
+++ b/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h
@@ -26,5 +26,6 @@
#define SC_MISC_REL_CONTAINER 2U /* Release container */
typedef u8 sc_misc_boot_status_t;
+typedef u8 sc_misc_temp_t;
#endif /* SC_MISC_API_H */
diff --git a/arch/arm/include/asm/arch-imx8/sys_proto.h b/arch/arm/include/asm/arch-imx8/sys_proto.h
index 73ffaba..b8d2a0b 100644
--- a/arch/arm/include/asm/arch-imx8/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8/sys_proto.h
@@ -3,6 +3,7 @@
* Copyright 2018 NXP
*/
+#include <asm/arch/sci/sci.h>
#include <asm/mach-imx/sys_proto.h>
#include <linux/types.h>
@@ -15,5 +16,7 @@
u32 g_ap_mu;
};
+void build_info(void);
enum boot_device get_boot_device(void);
int print_bootinfo(void);
+int sc_pm_setup_uart(sc_rsrc_t uart_rsrc, sc_pm_clock_rate_t clk_rate);
diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h
index 471a336..0836091 100644
--- a/arch/arm/include/asm/arch-lpc32xx/config.h
+++ b/arch/arm/include/asm/arch-lpc32xx/config.h
@@ -10,7 +10,6 @@
/* Basic CPU architecture */
-#define CONFIG_ARCH_CPU_INIT
/* UART configuration */
#if (CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \
diff --git a/arch/arm/include/asm/arch-meson/eth.h b/arch/arm/include/asm/arch-meson/eth.h
index 08acc5c..f765cd7 100644
--- a/arch/arm/include/asm/arch-meson/eth.h
+++ b/arch/arm/include/asm/arch-meson/eth.h
@@ -19,4 +19,7 @@
*/
void meson_eth_init(phy_interface_t mode, unsigned int flags);
+/* Generate an unique MAC address based on the HW serial */
+int meson_generate_serial_ethaddr(void);
+
#endif /* __MESON_ETH_H__ */
diff --git a/arch/arm/include/asm/arch-meson/sm.h b/arch/arm/include/asm/arch-meson/sm.h
index 83d6441..f3ae46a 100644
--- a/arch/arm/include/asm/arch-meson/sm.h
+++ b/arch/arm/include/asm/arch-meson/sm.h
@@ -8,4 +8,26 @@
ssize_t meson_sm_read_efuse(uintptr_t offset, void *buffer, size_t size);
+#define SM_SERIAL_SIZE 12
+
+int meson_sm_get_serial(void *buffer, size_t size);
+
+enum {
+ REBOOT_REASON_COLD = 0,
+ REBOOT_REASON_NORMAL = 1,
+ REBOOT_REASON_RECOVERY = 2,
+ REBOOT_REASON_UPDATE = 3,
+ REBOOT_REASON_FASTBOOT = 4,
+ REBOOT_REASON_SUSPEND_OFF = 5,
+ REBOOT_REASON_HIBERNATE = 6,
+ REBOOT_REASON_BOOTLOADER = 7,
+ REBOOT_REASON_SHUTDOWN_REBOOT = 8,
+ REBOOT_REASON_RPMBP = 9,
+ REBOOT_REASON_CRASH_DUMP = 11,
+ REBOOT_REASON_KERNEL_PANIC = 12,
+ REBOOT_REASON_WATCHDOG_REBOOT = 13,
+};
+
+int meson_sm_get_reboot_reason(void);
+
#endif /* __MESON_SM_H__ */
diff --git a/arch/arm/include/asm/arch-mvebu/spi.h b/arch/arm/include/asm/arch-mvebu/spi.h
index d6f6d1a..58b6c32 100644
--- a/arch/arm/include/asm/arch-mvebu/spi.h
+++ b/arch/arm/include/asm/arch-mvebu/spi.h
@@ -23,17 +23,6 @@
u32 dw_cfg; /* 0x10620 - Direct Write Configuration */
};
-/* They are used to define CONFIG_SYS_KW_SPI_MPP
- * each of the below #defines selects which mpp is
- * configured for each SPI signal in spi_claim_bus
- * bit 0: selects pin for MOSI (MPP1 if 0, MPP6 if 1)
- * bit 1: selects pin for SCK (MPP2 if 0, MPP10 if 1)
- * bit 2: selects pin for MISO (MPP3 if 0, MPP11 if 1)
- */
-#define MOSI_MPP6 (1 << 0)
-#define SCK_MPP10 (1 << 1)
-#define MISO_MPP11 (1 << 2)
-
/* Control Register */
#define KWSPI_CSN_ACT (1 << 0) /* Activates serial memory interface */
#define KWSPI_SMEMRDY (1 << 1) /* SerMem Data xfer ready */
diff --git a/arch/arm/include/asm/arch-rockchip/bootrom.h b/arch/arm/include/asm/arch-rockchip/bootrom.h
index d67f43f..0da78f3 100644
--- a/arch/arm/include/asm/arch-rockchip/bootrom.h
+++ b/arch/arm/include/asm/arch-rockchip/bootrom.h
@@ -52,9 +52,11 @@
BROM_LAST_BOOTSOURCE = BROM_BOOTSOURCE_USB
};
+extern const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1];
+
/**
* Locations of the boot-device identifier in SRAM
*/
-#define RK3399_BROM_BOOTSOURCE_ID_ADDR 0xff8c0010
+#define BROM_BOOTSOURCE_ID_ADDR (CONFIG_IRAM_BASE + 0x10)
#endif
diff --git a/arch/arm/include/asm/arch-rockchip/misc.h b/arch/arm/include/asm/arch-rockchip/misc.h
new file mode 100644
index 0000000..b6b03c9
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/misc.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * RK3399: Architecture common definitions
+ *
+ * Copyright (C) 2019 Collabora Inc - https://www.collabora.com/
+ * Rohan Garg <rohan.garg@collabora.com>
+ */
+
+int rockchip_cpuid_from_efuse(const u32 cpuid_offset,
+ const u32 cpuid_length,
+ u8 *cpuid);
+int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length);
+int rockchip_setup_macaddr(void);
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h
new file mode 100644
index 0000000..11411ea
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h
@@ -0,0 +1,441 @@
+/*
+ * Copyright (C) 2016-2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_SDRAM_RK3328_H
+#define _ASM_ARCH_SDRAM_RK3328_H
+
+#define SR_IDLE 93
+#define PD_IDLE 13
+#define SDRAM_ADDR 0x00000000
+#define PATTERN (0x5aa5f00f)
+
+/* ddr pctl registers define */
+#define DDR_PCTL2_MSTR 0x0
+#define DDR_PCTL2_STAT 0x4
+#define DDR_PCTL2_MSTR1 0x8
+#define DDR_PCTL2_MRCTRL0 0x10
+#define DDR_PCTL2_MRCTRL1 0x14
+#define DDR_PCTL2_MRSTAT 0x18
+#define DDR_PCTL2_MRCTRL2 0x1c
+#define DDR_PCTL2_DERATEEN 0x20
+#define DDR_PCTL2_DERATEINT 0x24
+#define DDR_PCTL2_PWRCTL 0x30
+#define DDR_PCTL2_PWRTMG 0x34
+#define DDR_PCTL2_HWLPCTL 0x38
+#define DDR_PCTL2_RFSHCTL0 0x50
+#define DDR_PCTL2_RFSHCTL1 0x54
+#define DDR_PCTL2_RFSHCTL2 0x58
+#define DDR_PCTL2_RFSHCTL4 0x5c
+#define DDR_PCTL2_RFSHCTL3 0x60
+#define DDR_PCTL2_RFSHTMG 0x64
+#define DDR_PCTL2_RFSHTMG1 0x68
+#define DDR_PCTL2_RFSHCTL5 0x6c
+#define DDR_PCTL2_INIT0 0xd0
+#define DDR_PCTL2_INIT1 0xd4
+#define DDR_PCTL2_INIT2 0xd8
+#define DDR_PCTL2_INIT3 0xdc
+#define DDR_PCTL2_INIT4 0xe0
+#define DDR_PCTL2_INIT5 0xe4
+#define DDR_PCTL2_INIT6 0xe8
+#define DDR_PCTL2_INIT7 0xec
+#define DDR_PCTL2_DIMMCTL 0xf0
+#define DDR_PCTL2_RANKCTL 0xf4
+#define DDR_PCTL2_CHCTL 0xfc
+#define DDR_PCTL2_DRAMTMG0 0x100
+#define DDR_PCTL2_DRAMTMG1 0x104
+#define DDR_PCTL2_DRAMTMG2 0x108
+#define DDR_PCTL2_DRAMTMG3 0x10c
+#define DDR_PCTL2_DRAMTMG4 0x110
+#define DDR_PCTL2_DRAMTMG5 0x114
+#define DDR_PCTL2_DRAMTMG6 0x118
+#define DDR_PCTL2_DRAMTMG7 0x11c
+#define DDR_PCTL2_DRAMTMG8 0x120
+#define DDR_PCTL2_DRAMTMG9 0x124
+#define DDR_PCTL2_DRAMTMG10 0x128
+#define DDR_PCTL2_DRAMTMG11 0x12c
+#define DDR_PCTL2_DRAMTMG12 0x130
+#define DDR_PCTL2_DRAMTMG13 0x134
+#define DDR_PCTL2_DRAMTMG14 0x138
+#define DDR_PCTL2_DRAMTMG15 0x13c
+#define DDR_PCTL2_DRAMTMG16 0x140
+#define DDR_PCTL2_ZQCTL0 0x180
+#define DDR_PCTL2_ZQCTL1 0x184
+#define DDR_PCTL2_ZQCTL2 0x188
+#define DDR_PCTL2_ZQSTAT 0x18c
+#define DDR_PCTL2_DFITMG0 0x190
+#define DDR_PCTL2_DFITMG1 0x194
+#define DDR_PCTL2_DFILPCFG0 0x198
+#define DDR_PCTL2_DFILPCFG1 0x19c
+#define DDR_PCTL2_DFIUPD0 0x1a0
+#define DDR_PCTL2_DFIUPD1 0x1a4
+#define DDR_PCTL2_DFIUPD2 0x1a8
+#define DDR_PCTL2_DFIMISC 0x1b0
+#define DDR_PCTL2_DFITMG2 0x1b4
+#define DDR_PCTL2_DFITMG3 0x1b8
+#define DDR_PCTL2_DFISTAT 0x1bc
+#define DDR_PCTL2_DBICTL 0x1c0
+#define DDR_PCTL2_ADDRMAP0 0x200
+#define DDR_PCTL2_ADDRMAP1 0x204
+#define DDR_PCTL2_ADDRMAP2 0x208
+#define DDR_PCTL2_ADDRMAP3 0x20c
+#define DDR_PCTL2_ADDRMAP4 0x210
+#define DDR_PCTL2_ADDRMAP5 0x214
+#define DDR_PCTL2_ADDRMAP6 0x218
+#define DDR_PCTL2_ADDRMAP7 0x21c
+#define DDR_PCTL2_ADDRMAP8 0x220
+#define DDR_PCTL2_ADDRMAP9 0x224
+#define DDR_PCTL2_ADDRMAP10 0x228
+#define DDR_PCTL2_ADDRMAP11 0x22c
+#define DDR_PCTL2_ODTCFG 0x240
+#define DDR_PCTL2_ODTMAP 0x244
+#define DDR_PCTL2_SCHED 0x250
+#define DDR_PCTL2_SCHED1 0x254
+#define DDR_PCTL2_PERFHPR1 0x25c
+#define DDR_PCTL2_PERFLPR1 0x264
+#define DDR_PCTL2_PERFWR1 0x26c
+#define DDR_PCTL2_DQMAP0 0x280
+#define DDR_PCTL2_DQMAP1 0x284
+#define DDR_PCTL2_DQMAP2 0x288
+#define DDR_PCTL2_DQMAP3 0x28c
+#define DDR_PCTL2_DQMAP4 0x290
+#define DDR_PCTL2_DQMAP5 0x294
+#define DDR_PCTL2_DBG0 0x300
+#define DDR_PCTL2_DBG1 0x304
+#define DDR_PCTL2_DBGCAM 0x308
+#define DDR_PCTL2_DBGCMD 0x30c
+#define DDR_PCTL2_DBGSTAT 0x310
+#define DDR_PCTL2_SWCTL 0x320
+#define DDR_PCTL2_SWSTAT 0x324
+#define DDR_PCTL2_POISONCFG 0x36c
+#define DDR_PCTL2_POISONSTAT 0x370
+#define DDR_PCTL2_ADVECCINDEX 0x374
+#define DDR_PCTL2_ADVECCSTAT 0x378
+#define DDR_PCTL2_PSTAT 0x3fc
+#define DDR_PCTL2_PCCFG 0x400
+#define DDR_PCTL2_PCFGR_n 0x404
+#define DDR_PCTL2_PCFGW_n 0x408
+#define DDR_PCTL2_PCTRL_n 0x490
+
+/* PCTL2_MRSTAT */
+#define MR_WR_BUSY BIT(0)
+
+/* PHY_REG0 */
+#define DIGITAL_DERESET BIT(3)
+#define ANALOG_DERESET BIT(2)
+#define DIGITAL_RESET (0 << 3)
+#define ANALOG_RESET (0 << 2)
+
+/* PHY_REG1 */
+#define PHY_DDR2 (0)
+#define PHY_LPDDR2 (1)
+#define PHY_DDR3 (2)
+#define PHY_LPDDR3 (3)
+#define PHY_DDR4 (4)
+#define PHY_BL_4 (0 << 2)
+#define PHY_BL_8 BIT(2)
+
+/* PHY_REG2 */
+#define PHY_DTT_EN BIT(0)
+#define PHY_DTT_DISB (0 << 0)
+#define PHY_WRITE_LEVELING_EN BIT(2)
+#define PHY_WRITE_LEVELING_DISB (0 << 2)
+#define PHY_SELECT_CS0 (2)
+#define PHY_SELECT_CS1 (1)
+#define PHY_SELECT_CS0_1 (0)
+#define PHY_WRITE_LEVELING_SELECTCS(n) (n << 6)
+#define PHY_DATA_TRAINING_SELECTCS(n) (n << 4)
+
+#define PHY_DDR3_RON_RTT_DISABLE (0)
+#define PHY_DDR3_RON_RTT_451ohm (1)
+#define PHY_DDR3_RON_RTT_225ohm (2)
+#define PHY_DDR3_RON_RTT_150ohm (3)
+#define PHY_DDR3_RON_RTT_112ohm (4)
+#define PHY_DDR3_RON_RTT_90ohm (5)
+#define PHY_DDR3_RON_RTT_75ohm (6)
+#define PHY_DDR3_RON_RTT_64ohm (7)
+#define PHY_DDR3_RON_RTT_56ohm (16)
+#define PHY_DDR3_RON_RTT_50ohm (17)
+#define PHY_DDR3_RON_RTT_45ohm (18)
+#define PHY_DDR3_RON_RTT_41ohm (19)
+#define PHY_DDR3_RON_RTT_37ohm (20)
+#define PHY_DDR3_RON_RTT_34ohm (21)
+#define PHY_DDR3_RON_RTT_33ohm (22)
+#define PHY_DDR3_RON_RTT_30ohm (23)
+#define PHY_DDR3_RON_RTT_28ohm (24)
+#define PHY_DDR3_RON_RTT_26ohm (25)
+#define PHY_DDR3_RON_RTT_25ohm (26)
+#define PHY_DDR3_RON_RTT_23ohm (27)
+#define PHY_DDR3_RON_RTT_22ohm (28)
+#define PHY_DDR3_RON_RTT_21ohm (29)
+#define PHY_DDR3_RON_RTT_20ohm (30)
+#define PHY_DDR3_RON_RTT_19ohm (31)
+
+#define PHY_DDR4_LPDDR3_RON_RTT_DISABLE (0)
+#define PHY_DDR4_LPDDR3_RON_RTT_480ohm (1)
+#define PHY_DDR4_LPDDR3_RON_RTT_240ohm (2)
+#define PHY_DDR4_LPDDR3_RON_RTT_160ohm (3)
+#define PHY_DDR4_LPDDR3_RON_RTT_120ohm (4)
+#define PHY_DDR4_LPDDR3_RON_RTT_96ohm (5)
+#define PHY_DDR4_LPDDR3_RON_RTT_80ohm (6)
+#define PHY_DDR4_LPDDR3_RON_RTT_68ohm (7)
+#define PHY_DDR4_LPDDR3_RON_RTT_60ohm (16)
+#define PHY_DDR4_LPDDR3_RON_RTT_53ohm (17)
+#define PHY_DDR4_LPDDR3_RON_RTT_48ohm (18)
+#define PHY_DDR4_LPDDR3_RON_RTT_43ohm (19)
+#define PHY_DDR4_LPDDR3_RON_RTT_40ohm (20)
+#define PHY_DDR4_LPDDR3_RON_RTT_37ohm (21)
+#define PHY_DDR4_LPDDR3_RON_RTT_34ohm (22)
+#define PHY_DDR4_LPDDR3_RON_RTT_32ohm (23)
+#define PHY_DDR4_LPDDR3_RON_RTT_30ohm (24)
+#define PHY_DDR4_LPDDR3_RON_RTT_28ohm (25)
+#define PHY_DDR4_LPDDR3_RON_RTT_26ohm (26)
+#define PHY_DDR4_LPDDR3_RON_RTT_25ohm (27)
+#define PHY_DDR4_LPDDR3_RON_RTT_24ohm (28)
+#define PHY_DDR4_LPDDR3_RON_RTT_22ohm (29)
+#define PHY_DDR4_LPDDR3_RON_RTT_21ohm (30)
+#define PHY_DDR4_LPDDR3_RON_RTT_20ohm (31)
+
+/* noc registers define */
+#define DDRCONF 0x8
+#define DDRTIMING 0xc
+#define DDRMODE 0x10
+#define READLATENCY 0x14
+#define AGING0 0x18
+#define AGING1 0x1c
+#define AGING2 0x20
+#define AGING3 0x24
+#define AGING4 0x28
+#define AGING5 0x2c
+#define ACTIVATE 0x38
+#define DEVTODEV 0x3c
+#define DDR4TIMING 0x40
+
+/* DDR GRF */
+#define DDR_GRF_CON(n) (0 + (n) * 4)
+#define DDR_GRF_STATUS_BASE (0X100)
+#define DDR_GRF_STATUS(n) (DDR_GRF_STATUS_BASE + (n) * 4)
+
+/* CRU_SOFTRESET_CON5 */
+#define ddrphy_psrstn_req(n) (((0x1 << 15) << 16) | (n << 15))
+#define ddrphy_srstn_req(n) (((0x1 << 14) << 16) | (n << 14))
+#define ddrctrl_psrstn_req(n) (((0x1 << 13) << 16) | (n << 13))
+#define ddrctrl_srstn_req(n) (((0x1 << 12) << 16) | (n << 12))
+#define ddrmsch_srstn_req(n) (((0x1 << 11) << 16) | (n << 11))
+#define msch_srstn_req(n) (((0x1 << 9) << 16) | (n << 9))
+#define dfimon_srstn_req(n) (((0x1 << 8) << 16) | (n << 8))
+#define grf_ddr_srstn_req(n) (((0x1 << 7) << 16) | (n << 7))
+/* CRU_SOFTRESET_CON9 */
+#define ddrctrl_asrstn_req(n) (((0x1 << 9) << 16) | (n << 9))
+
+/* CRU register */
+#define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4)
+#define CRU_MODE (0x80)
+#define CRU_GLB_CNT_TH (0x90)
+#define CRU_CLKSEL_CON_BASE 0x100
+#define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON_BASE + ((i) * 4))
+#define CRU_CLKGATE_CON_BASE 0x200
+#define CRU_CLKGATE_CON(i) (CRU_CLKGATE_CON_BASE + ((i) * 4))
+#define CRU_CLKSFTRST_CON_BASE 0x300
+#define CRU_CLKSFTRST_CON(i) (CRU_CLKSFTRST_CON_BASE + ((i) * 4))
+
+/* CRU_PLL_CON0 */
+#define PB(n) ((0x1 << (15 + 16)) | ((n) << 15))
+#define POSTDIV1(n) ((0x7 << (12 + 16)) | ((n) << 12))
+#define FBDIV(n) ((0xFFF << 16) | (n))
+
+/* CRU_PLL_CON1 */
+#define RSTMODE(n) ((0x1 << (15 + 16)) | ((n) << 15))
+#define RST(n) ((0x1 << (14 + 16)) | ((n) << 14))
+#define PD(n) ((0x1 << (13 + 16)) | ((n) << 13))
+#define DSMPD(n) ((0x1 << (12 + 16)) | ((n) << 12))
+#define LOCK(n) (((n) >> 10) & 0x1)
+#define POSTDIV2(n) ((0x7 << (6 + 16)) | ((n) << 6))
+#define REFDIV(n) ((0x3F << 16) | (n))
+
+union noc_ddrtiming {
+ u32 d32;
+ struct {
+ unsigned acttoact:6;
+ unsigned rdtomiss:6;
+ unsigned wrtomiss:6;
+ unsigned burstlen:3;
+ unsigned rdtowr:5;
+ unsigned wrtord:5;
+ unsigned bwratio:1;
+ } b;
+} NOC_TIMING_T;
+
+union noc_activate {
+ u32 d32;
+ struct {
+ unsigned rrd:4;
+ unsigned faw:6;
+ unsigned fawbank:1;
+ unsigned reserved1:21;
+ } b;
+};
+
+union noc_devtodev {
+ u32 d32;
+ struct {
+ unsigned busrdtord:2;
+ unsigned busrdtowr:2;
+ unsigned buswrtord:2;
+ unsigned reserved2:26;
+ } b;
+};
+
+union noc_ddr4timing {
+ u32 d32;
+ struct {
+ unsigned ccdl:3;
+ unsigned wrtordl:5;
+ unsigned rrdl:4;
+ unsigned reserved2:20;
+ } b;
+};
+
+union noc_ddrmode {
+ u32 d32;
+ struct {
+ unsigned autoprecharge:1;
+ unsigned bwratioextended:1;
+ unsigned reserved3:30;
+ } b;
+};
+
+u32 addrmap[21][9] = {
+ /* map0 map1 map2 map3 map4 map5 map6 map7 map8 */
+ {22, 0x00070707, 0x00000000, 0x1f000000, 0x00001f1f, 0x06060606,
+ 0x06060606, 0x00000f0f, 0x3f3f},
+ {23, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707,
+ 0x07070707, 0x00000f0f, 0x3f3f},
+ {23, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x08080808,
+ 0x0f080808, 0x00000f0f, 0x3f3f},
+ {24, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x08080808,
+ 0x08080808, 0x00000f0f, 0x3f3f},
+ {24, 0x000a0a0a, 0x00000000, 0x00000000, 0x00000000, 0x09090909,
+ 0x0f090909, 0x00000f0f, 0x3f3f},
+ {6, 0x00070707, 0x00000000, 0x1f000000, 0x00001f1f, 0x07070707,
+ 0x07070707, 0x00000f0f, 0x3f3f},
+ {7, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x08080808,
+ 0x08080808, 0x00000f0f, 0x3f3f},
+ {8, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x09090909,
+ 0x0f090909, 0x00000f0f, 0x3f3f},
+ {22, 0x001f0808, 0x00000000, 0x00000000, 0x00001f1f, 0x06060606,
+ 0x06060606, 0x00000f0f, 0x3f3f},
+ {23, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707,
+ 0x0f070707, 0x00000f0f, 0x3f3f},
+
+ {24, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808,
+ 0x08080808, 0x00000f0f, 0x0801},
+ {23, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808,
+ 0x0f080808, 0x00000f0f, 0x0801},
+ {24, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707,
+ 0x07070707, 0x00000f07, 0x0700},
+ {23, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707,
+ 0x07070707, 0x00000f0f, 0x0700},
+ {24, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x07070707,
+ 0x07070707, 0x00000f07, 0x3f01},
+ {23, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x07070707,
+ 0x07070707, 0x00000f0f, 0x3f01},
+ {24, 0x003f0808, 0x00000007, 0x1f000000, 0x00001f1f, 0x06060606,
+ 0x06060606, 0x00000f06, 0x3f00},
+ {8, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x09090909,
+ 0x0f090909, 0x00000f0f, 0x0801},
+ {7, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x08080808,
+ 0x08080808, 0x00000f0f, 0x0700},
+ {7, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808,
+ 0x08080808, 0x00000f0f, 0x3f01},
+
+ {6, 0x003f0808, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707,
+ 0x07070707, 0x00000f07, 0x3f00}
+};
+
+struct rk3328_msch_timings {
+ union noc_ddrtiming ddrtiming;
+ union noc_ddrmode ddrmode;
+ u32 readlatency;
+ union noc_activate activate;
+ union noc_devtodev devtodev;
+ union noc_ddr4timing ddr4timing;
+ u32 agingx0;
+};
+
+struct rk3328_msch_regs {
+ u32 coreid;
+ u32 revisionid;
+ u32 ddrconf;
+ u32 ddrtiming;
+ u32 ddrmode;
+ u32 readlatency;
+ u32 aging0;
+ u32 aging1;
+ u32 aging2;
+ u32 aging3;
+ u32 aging4;
+ u32 aging5;
+ u32 reserved[2];
+ u32 activate;
+ u32 devtodev;
+ u32 ddr4_timing;
+};
+
+struct rk3328_ddr_grf_regs {
+ u32 ddr_grf_con[4];
+ u32 reserved[(0x100 - 0x10) / 4];
+ u32 ddr_grf_status[11];
+};
+
+struct rk3328_ddr_pctl_regs {
+ u32 pctl[30][2];
+};
+
+struct rk3328_ddr_phy_regs {
+ u32 phy[5][2];
+};
+
+struct rk3328_ddr_skew {
+ u32 a0_a1_skew[15];
+ u32 cs0_dm0_skew[11];
+ u32 cs0_dm1_skew[11];
+ u32 cs0_dm2_skew[11];
+ u32 cs0_dm3_skew[11];
+ u32 cs1_dm0_skew[11];
+ u32 cs1_dm1_skew[11];
+ u32 cs1_dm2_skew[11];
+ u32 cs1_dm3_skew[11];
+};
+
+struct rk3328_sdram_channel {
+ unsigned int rank;
+ unsigned int col;
+ /* 3:8bank, 2:4bank */
+ unsigned int bk;
+ /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
+ unsigned int bw;
+ /* die buswidth, 2:32bit, 1:16bit, 0:8bit */
+ unsigned int dbw;
+ unsigned int row_3_4;
+ unsigned int cs0_row;
+ unsigned int cs1_row;
+ unsigned int ddrconfig;
+ struct rk3328_msch_timings noc_timings;
+};
+
+struct rk3328_sdram_params {
+ struct rk3328_sdram_channel ch;
+ unsigned int ddr_freq;
+ unsigned int dramtype;
+ unsigned int odt;
+ struct rk3328_ddr_pctl_regs pctl_regs;
+ struct rk3328_ddr_phy_regs phy_regs;
+ struct rk3328_ddr_skew skew;
+};
+
+#define PHY_REG(base, n) (base + 4 * (n))
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/sys_proto.h b/arch/arm/include/asm/arch-rockchip/sys_proto.h
index 928e4f2..de5a8f1 100644
--- a/arch/arm/include/asm/arch-rockchip/sys_proto.h
+++ b/arch/arm/include/asm/arch-rockchip/sys_proto.h
@@ -6,30 +6,4 @@
#ifndef _ASM_ARCH_SYS_PROTO_H
#define _ASM_ARCH_SYS_PROTO_H
-#ifdef CONFIG_ROCKCHIP_RK3288
-#include <asm/armv7.h>
-
-static void configure_l2ctlr(void)
-{
- uint32_t l2ctlr;
-
- l2ctlr = read_l2ctlr();
- l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
-
- /*
- * Data RAM write latency: 2 cycles
- * Data RAM read latency: 2 cycles
- * Data RAM setup latency: 1 cycle
- * Tag RAM write latency: 1 cycle
- * Tag RAM read latency: 1 cycle
- * Tag RAM setup latency: 1 cycle
- */
- l2ctlr |= (1 << 3 | 1 << 0);
- write_l2ctlr(l2ctlr);
-}
-#endif /* CONFIG_ROCKCHIP_RK3288 */
-
-/* provided to defeat compiler optimisation in board_init_f() */
-void gru_dummy_function(int i);
-
#endif /* _ASM_ARCH_SYS_PROTO_H */
diff --git a/arch/arm/include/asm/arch-rockchip/timer.h b/arch/arm/include/asm/arch-rockchip/timer.h
index a8379be..77b5422 100644
--- a/arch/arm/include/asm/arch-rockchip/timer.h
+++ b/arch/arm/include/asm/arch-rockchip/timer.h
@@ -15,7 +15,4 @@
u32 timer_int_status;
};
-void rockchip_timer_init(void);
-void rockchip_udelay(unsigned int usec);
-
#endif
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h
index eeb4da5..0a1da02 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h
@@ -9,6 +9,8 @@
#ifndef _SUNXI_DRAM_SUN50I_H6_H
#define _SUNXI_DRAM_SUN50I_H6_H
+#include <stdbool.h>
+
enum sunxi_dram_type {
SUNXI_DRAM_TYPE_DDR3 = 3,
SUNXI_DRAM_TYPE_DDR4,
@@ -16,6 +18,11 @@
SUNXI_DRAM_TYPE_LPDDR3,
};
+static inline bool sunxi_dram_is_lpddr(int type)
+{
+ return type >= SUNXI_DRAM_TYPE_LPDDR2;
+}
+
/*
* The following information is mainly retrieved by disassembly and some FPGA
* test code of sun50iw3 platform.
@@ -286,6 +293,32 @@
#define DCR_DDR3 (3 << 0)
#define DCR_DDR4 (4 << 0)
#define DCR_DDR8BANK BIT(3)
+#define DCR_DDR2T BIT(28)
+
+/*
+ * The delay parameters allow to allegedly specify delay times of some
+ * unknown unit for each individual bit trace in each of the four data bytes
+ * the 32-bit wide access consists of. Also three control signals can be
+ * adjusted individually.
+ */
+#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE)
+/* The eight data lines (DQn) plus DM, DQS, DQS/DM/DQ Output Enable and DQSN */
+#define WR_LINES_PER_BYTE_LANE (BITS_PER_BYTE + 4)
+/*
+ * The eight data lines (DQn) plus DM, DQS, DQS/DM/DQ Output Enable, DQSN,
+ * Termination and Power down
+ */
+#define RD_LINES_PER_BYTE_LANE (BITS_PER_BYTE + 6)
+struct dram_para {
+ u32 clk;
+ enum sunxi_dram_type type;
+ u8 cols;
+ u8 rows;
+ u8 ranks;
+ const u8 dx_read_delays[NR_OF_BYTE_LANES][RD_LINES_PER_BYTE_LANE];
+ const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE];
+};
+
static inline int ns_to_t(int nanoseconds)
{
@@ -294,4 +327,6 @@
return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
}
+void mctl_set_timing_params(struct dram_para *para);
+
#endif /* _SUNXI_DRAM_SUN50I_H6_H */
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index a81b106..1774014 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -9,7 +9,7 @@
/* Architecture-specific global data */
struct arch_global_data {
-#if defined(CONFIG_FSL_ESDHC)
+#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_FSL_ESDHC_IMX)
u32 sdhc_clk;
#endif
diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h
index 370031f..6ff5f42 100644
--- a/arch/arm/include/asm/gpio.h
+++ b/arch/arm/include/asm/gpio.h
@@ -1,6 +1,9 @@
#if !defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARCH_STI) && \
!defined(CONFIG_ARCH_K3) && !defined(CONFIG_ARCH_BCM6858) && \
- !defined(CONFIG_ARCH_BCM63158) && !defined(CONFIG_ARCH_ROCKCHIP)
+ !defined(CONFIG_ARCH_BCM63158) && !defined(CONFIG_ARCH_ROCKCHIP) && \
+ !defined(CONFIG_ARCH_LX2160A) && !defined(CONFIG_ARCH_LS1028A) && \
+ !defined(CONFIG_ARCH_LS2080A) && !defined(CONFIG_ARCH_LS1088A) && \
+ !defined(CONFIG_ARCH_ASPEED)
#include <asm/arch/gpio.h>
#endif
#include <asm-generic/gpio.h>
diff --git a/arch/arm/include/asm/mach-imx/imx-nandbcb.h b/arch/arm/include/asm/mach-imx/imx-nandbcb.h
new file mode 100644
index 0000000..033659a
--- /dev/null
+++ b/arch/arm/include/asm/mach-imx/imx-nandbcb.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright (C) 2017 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _IMX_NAND_BCB_H_
+#define _IMX_NAND_BCB_H_
+
+#define FCB_FINGERPRINT 0x20424346 /* 'FCB' */
+#define FCB_VERSION_1 0x01000000
+
+#define DBBT_FINGERPRINT2 0x54424244 /* 'DBBT' */
+#define DBBT_VERSION_1 0x01000000
+
+struct dbbt_block {
+ u32 checksum; /* reserved on i.MX6 */
+ u32 fingerprint;
+ u32 version;
+ u32 numberbb; /* reserved on i.MX6 */
+ u32 dbbtpages;
+};
+
+struct fcb_block {
+ u32 checksum; /* First fingerprint in first byte */
+ u32 fingerprint; /* 2nd fingerprint at byte 4 */
+ u32 version; /* 3rd fingerprint at byte 8 */
+ u8 datasetup;
+ u8 datahold;
+ u8 addr_setup;
+ u8 dsample_time;
+
+ /* These are for application use only and not for ROM. */
+ u8 nandtiming;
+ u8 rea;
+ u8 rloh;
+ u8 rhoh;
+ u32 pagesize; /* 2048 for 2K pages, 4096 for 4K pages */
+ u32 oob_pagesize; /* 2112 for 2K pages, 4314 for 4K pages */
+ u32 sectors; /* Number of 2K sections per block */
+ u32 nr_nand; /* Total Number of NANDs - not used by ROM */
+ u32 nr_die; /* Number of separate chips in this NAND */
+ u32 celltype; /* MLC or SLC */
+ u32 ecc_type; /* Type of ECC, can be one of BCH-0-20 */
+ u32 ecc_nr; /* Number of bytes for Block0 - BCH */
+
+ /* Block size in bytes for all blocks other than Block0 - BCH */
+ u32 ecc_size;
+ u32 ecc_level; /* Ecc level for Block 0 - BCH */
+ u32 meta_size; /* Metadata size - BCH */
+ /* Number of blocks per page for ROM use - BCH */
+ u32 nr_blocks;
+ u32 ecc_type_sdk; /* Type of ECC, can be one of BCH-0-20 */
+ u32 ecc_nr_sdk; /* Number of bytes for Block0 - BCH */
+ /* Block size in bytes for all blocks other than Block0 - BCH */
+ u32 ecc_size_sdk;
+ u32 ecc_level_sdk; /* Ecc level for Block 0 - BCH */
+ /* Number of blocks per page for SDK use - BCH */
+ u32 nr_blocks_sdk;
+ u32 meta_size_sdk; /* Metadata size - BCH */
+ u32 erase_th; /* To set into BCH_MODE register */
+
+ /*
+ * 0: normal boot
+ * 1: to load patch starting next to FCB
+ */
+ u32 bootpatch;
+ u32 patch_size; /* Size of patch in sectors */
+ u32 fw1_start; /* Firmware image starts on this sector */
+ u32 fw2_start; /* Secondary FW Image starting Sector */
+ u32 fw1_pages; /* Number of sectors in firmware image */
+ u32 fw2_pages; /* Number of sector in secondary FW image */
+ u32 dbbt_start; /* Page address where dbbt search area begins */
+
+ /*
+ * Byte in page data that have manufacturer marked bad block marker,
+ * this will be swapped with metadata[0] to complete page data.
+ */
+ u32 bb_byte;
+
+ /*
+ * For BCH ECC sizes other than 8 and 16 the bad block marker does not
+ * start at 0th bit of bb_byte. This field is used to get to
+ * the start bit of bad block marker byte with in bb_byte
+ */
+ u32 bb_start_bit;
+
+ /*
+ * FCB value that gives byte offset for
+ * bad block marker on physical NAND page
+ */
+ u32 phy_offset;
+ u32 bchtype;
+
+ u32 readlatency;
+ u32 predelay;
+ u32 cedelay;
+ u32 postdelay;
+ u32 cmdaddpause;
+ u32 datapause;
+ u32 tmspeed;
+ u32 busytimeout;
+
+ /* the flag to enable (1)/disable(0) bi swap */
+ u32 disbbm;
+
+ /* The swap position of main area in spare area */
+ u32 spare_offset;
+};
+
+#endif /* _IMX_NAND_BCB_H_ */
diff --git a/arch/arm/include/asm/mach-imx/mxc_i2c.h b/arch/arm/include/asm/mach-imx/mxc_i2c.h
index 8e1ea9a..81fd981 100644
--- a/arch/arm/include/asm/mach-imx/mxc_i2c.h
+++ b/arch/arm/include/asm/mach-imx/mxc_i2c.h
@@ -6,6 +6,9 @@
#define __ASM_ARCH_MXC_MXC_I2C_H__
#include <asm-generic/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
+#if CONFIG_IS_ENABLED(CLK)
+#include <clk.h>
+#endif
struct i2c_pin_ctrl {
iomux_v3_cfg_t i2c_mode;
@@ -47,6 +50,9 @@
ulong driver_data;
int speed;
struct i2c_pads_info *pads_info;
+#if CONFIG_IS_ENABLED(CLK)
+ struct clk per_clk;
+#endif
#ifndef CONFIG_DM_I2C
int (*idle_bus_fn)(void *p);
void *idle_bus_data;
diff --git a/arch/arm/include/asm/omap_i2c.h b/arch/arm/include/asm/omap_i2c.h
index c1695cb..a697540 100644
--- a/arch/arm/include/asm/omap_i2c.h
+++ b/arch/arm/include/asm/omap_i2c.h
@@ -3,8 +3,6 @@
#ifndef _OMAP_I2C_H
#define _OMAP_I2C_H
-#include <asm/arch/cpu.h>
-
#ifdef CONFIG_DM_I2C
/* Information about a GPIO bank */
diff --git a/arch/arm/include/asm/proc-armv/ptrace.h b/arch/arm/include/asm/proc-armv/ptrace.h
index 183b00a..e37ad8f 100644
--- a/arch/arm/include/asm/proc-armv/ptrace.h
+++ b/arch/arm/include/asm/proc-armv/ptrace.h
@@ -86,7 +86,7 @@
#define user_mode(regs) \
(((regs)->ARM_cpsr & 0xf) == 0)
-#ifdef CONFIG_ARM_THUMB
+#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
#define thumb_mode(regs) \
(((regs)->ARM_cpsr & T_BIT))
#else
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index aed2e3c..a1a5e35 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -516,6 +516,21 @@
*/
void mmu_page_table_flush(unsigned long start, unsigned long stop);
+#ifdef CONFIG_ARMV7_PSCI
+void psci_arch_cpu_entry(void);
+u32 psci_version(void);
+s32 psci_features(u32 function_id, u32 psci_fid);
+s32 psci_cpu_off(void);
+s32 psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc,
+ u32 context_id);
+s32 psci_affinity_info(u32 function_id, u32 target_affinity,
+ u32 lowest_affinity_level);
+u32 psci_migrate_info_type(void);
+void psci_system_off(void);
+void psci_system_reset(void);
+s32 psci_features(u32 function_id, u32 psci_fid);
+#endif
+
#endif /* __ASSEMBLY__ */
#define arch_align_stack(x) (x)
diff --git a/arch/arm/include/asm/ti-common/davinci_nand.h b/arch/arm/include/asm/ti-common/davinci_nand.h
index e26381c..28842c3 100644
--- a/arch/arm/include/asm/ti-common/davinci_nand.h
+++ b/arch/arm/include/asm/ti-common/davinci_nand.h
@@ -95,6 +95,4 @@
#define DAVINCI_ABCR_ASIZE_16BIT 1
#define DAVINCI_ABCR_ASIZE_8BIT 0
-void davinci_nand_init(struct nand_chip *nand);
-
#endif
diff --git a/arch/arm/include/asm/ti-common/omap_wdt.h b/arch/arm/include/asm/ti-common/omap_wdt.h
index 7d72e3a..fbc421b 100644
--- a/arch/arm/include/asm/ti-common/omap_wdt.h
+++ b/arch/arm/include/asm/ti-common/omap_wdt.h
@@ -56,4 +56,9 @@
unsigned int wdt_unfr; /* offset 0x100 */
};
+struct omap3_wdt_priv {
+ struct wd_timer *regs;
+ unsigned int wdt_trgr_pattern;
+};
+
#endif /* __OMAP_WDT_H__ */
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index bf68a5b..1638f1e 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -15,6 +15,7 @@
#include <command.h>
#include <dm.h>
#include <dm/root.h>
+#include <env.h>
#include <image.h>
#include <u-boot/zlib.h>
#include <asm/byteorder.h>
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index 449544d..463d283 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -77,6 +77,7 @@
phys_addr_t start, end;
size_t size;
+ /* If this calculation changes, update board_f.c:reserve_noncached() */
end = ALIGN(mem_malloc_start, MMU_SECTION_SIZE) - MMU_SECTION_SIZE;
size = ALIGN(CONFIG_SYS_NONCACHED_MEMORY, MMU_SECTION_SIZE);
start = end - size;
diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S
index 30fba20..c74641d 100644
--- a/arch/arm/lib/crt0.S
+++ b/arch/arm/lib/crt0.S
@@ -58,6 +58,33 @@
*/
/*
+ * Macro for clearing BSS during SPL execution. Usually called during the
+ * relocation process for most boards before entering board_init_r(), but
+ * can also be done early before entering board_init_f() on plaforms that
+ * can afford it due to sufficient memory being available early.
+ */
+
+.macro SPL_CLEAR_BSS
+ ldr r0, =__bss_start /* this is auto-relocated! */
+
+#ifdef CONFIG_USE_ARCH_MEMSET
+ ldr r3, =__bss_end /* this is auto-relocated! */
+ mov r1, #0x00000000 /* prepare zero to clear BSS */
+
+ subs r2, r3, r0 /* r2 = memset len */
+ bl memset
+#else
+ ldr r1, =__bss_end /* this is auto-relocated! */
+ mov r2, #0x00000000 /* prepare zero to clear BSS */
+
+clbss_l:cmp r0, r1 /* while not at end of BSS */
+ strlo r2, [r0] /* clear 32-bit BSS word */
+ addlo r0, r0, #4 /* move to next */
+ blo clbss_l
+#endif
+.endm
+
+/*
* entry point of crt0 sequence
*/
@@ -82,6 +109,10 @@
mov r9, r0
bl board_init_f_init_reserve
+#if defined(CONFIG_SPL_EARLY_BSS)
+ SPL_CLEAR_BSS
+#endif
+
mov r0, #0
bl board_init_f
@@ -119,6 +150,11 @@
bl c_runtime_cpu_setup /* we still call old routine here */
#endif
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_FRAMEWORK)
+
+#if !defined(CONFIG_SPL_EARLY_BSS)
+ SPL_CLEAR_BSS
+#endif
+
# ifdef CONFIG_SPL_BUILD
/* Use a DRAM stack for the rest of SPL, if requested */
bl spl_relocate_stack_gd
@@ -126,23 +162,6 @@
movne sp, r0
movne r9, r0
# endif
- ldr r0, =__bss_start /* this is auto-relocated! */
-
-#ifdef CONFIG_USE_ARCH_MEMSET
- ldr r3, =__bss_end /* this is auto-relocated! */
- mov r1, #0x00000000 /* prepare zero to clear BSS */
-
- subs r2, r3, r0 /* r2 = memset len */
- bl memset
-#else
- ldr r1, =__bss_end /* this is auto-relocated! */
- mov r2, #0x00000000 /* prepare zero to clear BSS */
-
-clbss_l:cmp r0, r1 /* while not at end of BSS */
- strlo r2, [r0] /* clear 32-bit BSS word */
- addlo r0, r0, #4 /* move to next */
- blo clbss_l
-#endif
#if ! defined(CONFIG_SPL_BUILD)
bl coloured_LED_init
diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S
index d6b632a..e76b25a 100644
--- a/arch/arm/lib/crt0_64.S
+++ b/arch/arm/lib/crt0_64.S
@@ -72,7 +72,7 @@
ldr x0, =(CONFIG_TPL_STACK)
#elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
ldr x0, =(CONFIG_SPL_STACK)
-#elif defined(CONFIG_SYS_INIT_SP_BSS_OFFSET)
+#elif defined(CONFIG_INIT_SP_RELATIVE)
adr x0, __bss_start
add x0, x0, #CONFIG_SYS_INIT_SP_BSS_OFFSET
#else
diff --git a/arch/arm/lib/crt0_aarch64_efi.S b/arch/arm/lib/crt0_aarch64_efi.S
index cb205fa..368933e 100644
--- a/arch/arm/lib/crt0_aarch64_efi.S
+++ b/arch/arm/lib/crt0_aarch64_efi.S
@@ -17,14 +17,13 @@
*/
.globl ImageBase
ImageBase:
- .ascii "MZ"
+ .short IMAGE_DOS_SIGNATURE /* 'MZ' */
.skip 58 /* 'MZ' + pad + offset == 64 */
.long pe_header - ImageBase /* Offset to the PE header */
pe_header:
- .ascii "PE"
- .short 0
+ .long IMAGE_NT_SIGNATURE /* 'PE' */
coff_header:
- .short 0xaa64 /* AArch64 */
+ .short IMAGE_FILE_MACHINE_ARM64 /* AArch64 */
.short 2 /* nr_sections */
.long 0 /* TimeDateStamp */
.long 0 /* PointerToSymbolTable */
@@ -36,7 +35,7 @@
IMAGE_FILE_LOCAL_SYMS_STRIPPED | \
IMAGE_FILE_DEBUG_STRIPPED)
optional_header:
- .short 0x20b /* PE32+ format */
+ .short IMAGE_NT_OPTIONAL_HDR64_MAGIC /* PE32+ format */
.byte 0x02 /* MajorLinkerVersion */
.byte 0x14 /* MinorLinkerVersion */
.long _edata - _start /* SizeOfCode */
diff --git a/arch/arm/lib/crt0_arm_efi.S b/arch/arm/lib/crt0_arm_efi.S
index 5470e2f..cc8a115 100644
--- a/arch/arm/lib/crt0_arm_efi.S
+++ b/arch/arm/lib/crt0_arm_efi.S
@@ -16,14 +16,13 @@
*/
.globl image_base
image_base:
- .ascii "MZ"
+ .short IMAGE_DOS_SIGNATURE /* 'MZ' */
.skip 58 /* 'MZ' + pad + offset == 64 */
.long pe_header - image_base /* Offset to the PE header */
pe_header:
- .ascii "PE"
- .short 0
+ .long IMAGE_NT_SIGNATURE /* 'PE' */
coff_header:
- .short 0x1c2 /* Mixed ARM/Thumb */
+ .short IMAGE_FILE_MACHINE_THUMB /* Mixed ARM/Thumb */
.short 2 /* nr_sections */
.long 0 /* TimeDateStamp */
.long 0 /* PointerToSymbolTable */
@@ -36,7 +35,7 @@
IMAGE_FILE_32BIT_MACHINE | \
IMAGE_FILE_DEBUG_STRIPPED)
optional_header:
- .short 0x10b /* PE32 format */
+ .short IMAGE_NT_OPTIONAL_HDR32_MAGIC /* PE32 format */
.byte 0x02 /* MajorLinkerVersion */
.byte 0x14 /* MinorLinkerVersion */
.long _edata - _start /* SizeOfCode */
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h
index d45343b..3412df0 100644
--- a/arch/arm/mach-at91/include/mach/at91rm9200.h
+++ b/arch/arm/mach-at91/include/mach/at91rm9200.h
@@ -5,7 +5,6 @@
#ifndef __AT91RM9200_H__
#define __AT91RM9200_H__
-#define CONFIG_ARCH_CPU_INIT /* we need arch_cpu_init() for hw timers */
#define CONFIG_AT91_GPIO /* and require always gpio features */
/* Periperial Identifiers */
diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
index 3eb5a9a..b08275f 100644
--- a/arch/arm/mach-bcm283x/Kconfig
+++ b/arch/arm/mach-bcm283x/Kconfig
@@ -26,6 +26,23 @@
select BCM2837
select ARM64
+config BCM2711
+ bool "Broadcom BCM2711 SoC support"
+ depends on ARCH_BCM283X
+
+config BCM2711_32B
+ bool "Broadcom BCM2711 SoC 32-bit support"
+ depends on ARCH_BCM283X
+ select BCM2711
+ select ARMV7_LPAE
+ select CPU_V7A
+
+config BCM2711_64B
+ bool "Broadcom BCM2711 SoC 64-bit support"
+ depends on ARCH_BCM283X
+ select BCM2711
+ select ARM64
+
menu "Broadcom BCM283X family"
depends on ARCH_BCM283X
@@ -127,6 +144,50 @@
This option creates a build targeting the ARMv8/AArch64 ISA.
select BCM2837_64B
+config TARGET_RPI_4_32B
+ bool "Raspberry Pi 4 32-bit build"
+ help
+ Support for all BCM2711-based Raspberry Pi variants, such as
+ the RPi 4 model B, in AArch32 (32-bit) mode.
+
+ This option assumes the VideoCore firmware is configured to use the
+ mini UART (rather than PL011) for the serial console. This is the
+ default on the RPi 4. To enable the UART console, the following non-
+ default option must be present in config.txt: enable_uart=1. This is
+ required for U-Boot to operate correctly, even if you only care
+ about the HDMI/usbkbd console.
+
+ Due to hardware incompatibilities, this can't be used with
+ BCM283/5/6/7.
+
+ This option creates a build targeting the ARMv7/AArch32 ISA.
+ select BCM2711_32B
+
+config TARGET_RPI_4
+ bool "Raspberry Pi 4 64-bit build"
+ help
+ Support for all BCM2711-based Raspberry Pi variants, such as
+ the RPi 4 model B, in AArch64 (64-bit) mode.
+
+ This option assumes the VideoCore firmware is configured to use the
+ mini UART (rather than PL011) for the serial console. This is the
+ default on the RPi 4. To enable the UART console, the following non-
+ default option must be present in config.txt: enable_uart=1. This is
+ required for U-Boot to operate correctly, even if you only care
+ about the HDMI/usbkbd console.
+
+ Due to hardware incompatibilities, this can't be used with
+ BCM283/5/6/7.
+
+ Also, due to a bug in firmware, switching to 64bit mode doesn't
+ happen automatically based on the kernel's image filename. See
+ https://github.com/raspberrypi/firmware/issues/1193 for more details.
+ Until that is resolved, the configuration (config.txt) needs to
+ explicitly set: arm_64bit=1.
+
+ This option creates a build targeting the ARMv8/AArch64 ISA.
+ select BCM2711_64B
+
endchoice
config SYS_BOARD
@@ -141,4 +202,10 @@
config SYS_CONFIG_NAME
default "rpi"
+config BCM283x_BASE
+ hex
+ default "0x20000000" if BCM2835
+ default "0x3f000000" if BCM2836 || BCM2837
+ default "0xfe000000" if BCM2711
+
endmenu
diff --git a/arch/arm/mach-bcm283x/include/mach/mbox.h b/arch/arm/mach-bcm283x/include/mach/mbox.h
index e3a893e..0b6c254 100644
--- a/arch/arm/mach-bcm283x/include/mach/mbox.h
+++ b/arch/arm/mach-bcm283x/include/mach/mbox.h
@@ -37,18 +37,17 @@
/* Raw mailbox HW */
-#ifndef CONFIG_BCM2835
-#define BCM2835_MBOX_PHYSADDR 0x3f00b880
-#else
-#define BCM2835_MBOX_PHYSADDR 0x2000b880
-#endif
+#define BCM2835_MBOX_PHYSADDR (CONFIG_BCM283x_BASE + 0x0000b880)
struct bcm2835_mbox_regs {
u32 read;
u32 rsvd0[5];
- u32 status;
- u32 config;
+ u32 mail0_status;
+ u32 mail0_config;
u32 write;
+ u32 rsvd1[5];
+ u32 mail1_status;
+ u32 mail1_config;
};
#define BCM2835_MBOX_STATUS_WR_FULL 0x80000000
@@ -234,6 +233,7 @@
#define BCM2835_MBOX_CLOCK_ID_SDRAM 8
#define BCM2835_MBOX_CLOCK_ID_PIXEL 9
#define BCM2835_MBOX_CLOCK_ID_PWM 10
+#define BCM2835_MBOX_CLOCK_ID_EMMC2 12
struct bcm2835_mbox_tag_get_clock_rate {
struct bcm2835_mbox_tag_hdr tag_hdr;
diff --git a/arch/arm/mach-bcm283x/include/mach/sdhci.h b/arch/arm/mach-bcm283x/include/mach/sdhci.h
index 5cb6ec3..b443c37 100644
--- a/arch/arm/mach-bcm283x/include/mach/sdhci.h
+++ b/arch/arm/mach-bcm283x/include/mach/sdhci.h
@@ -6,11 +6,7 @@
#ifndef _BCM2835_SDHCI_H_
#define _BCM2835_SDHCI_H_
-#ifndef CONFIG_BCM2835
-#define BCM2835_SDHCI_BASE 0x3f300000
-#else
-#define BCM2835_SDHCI_BASE 0x20300000
-#endif
+#define BCM2835_SDHCI_BASE (CONFIG_BCM283x_BASE + 0x00300000)
int bcm2835_sdhci_init(u32 regbase, u32 emmc_freq);
diff --git a/arch/arm/mach-bcm283x/include/mach/timer.h b/arch/arm/mach-bcm283x/include/mach/timer.h
index 56b0c35..014355e 100644
--- a/arch/arm/mach-bcm283x/include/mach/timer.h
+++ b/arch/arm/mach-bcm283x/include/mach/timer.h
@@ -6,11 +6,7 @@
#ifndef _BCM2835_TIMER_H
#define _BCM2835_TIMER_H
-#ifndef CONFIG_BCM2835
-#define BCM2835_TIMER_PHYSADDR 0x3f003000
-#else
-#define BCM2835_TIMER_PHYSADDR 0x20003000
-#endif
+#define BCM2835_TIMER_PHYSADDR (CONFIG_BCM283x_BASE + 0x00003000)
#define BCM2835_TIMER_CS_M3 (1 << 3)
#define BCM2835_TIMER_CS_M2 (1 << 2)
diff --git a/arch/arm/mach-bcm283x/include/mach/wdog.h b/arch/arm/mach-bcm283x/include/mach/wdog.h
index 99c88e5..8292b3c 100644
--- a/arch/arm/mach-bcm283x/include/mach/wdog.h
+++ b/arch/arm/mach-bcm283x/include/mach/wdog.h
@@ -6,11 +6,7 @@
#ifndef _BCM2835_WDOG_H
#define _BCM2835_WDOG_H
-#ifndef CONFIG_BCM2835
-#define BCM2835_WDOG_PHYSADDR 0x3f100000
-#else
-#define BCM2835_WDOG_PHYSADDR 0x20100000
-#endif
+#define BCM2835_WDOG_PHYSADDR (CONFIG_BCM283x_BASE + 0x00100000)
struct bcm2835_wdog_regs {
u32 unknown0[7];
diff --git a/arch/arm/mach-bcm283x/mbox.c b/arch/arm/mach-bcm283x/mbox.c
index 1642ebd..3c67f68 100644
--- a/arch/arm/mach-bcm283x/mbox.c
+++ b/arch/arm/mach-bcm283x/mbox.c
@@ -27,7 +27,7 @@
/* Drain any stale responses */
for (;;) {
- val = readl(®s->status);
+ val = readl(®s->mail0_status);
if (val & BCM2835_MBOX_STATUS_RD_EMPTY)
break;
if (get_timer(0) >= endtime) {
@@ -40,7 +40,7 @@
/* Wait for space to send */
for (;;) {
- val = readl(®s->status);
+ val = readl(®s->mail1_status);
if (!(val & BCM2835_MBOX_STATUS_WR_FULL))
break;
if (get_timer(0) >= endtime) {
@@ -58,7 +58,7 @@
/* Wait for the response */
for (;;) {
- val = readl(®s->status);
+ val = readl(®s->mail0_status);
if (!(val & BCM2835_MBOX_STATUS_RD_EMPTY))
break;
if (get_timer(0) >= endtime) {
diff --git a/arch/arm/mach-bcm283x/reset.c b/arch/arm/mach-bcm283x/reset.c
index 7712d46..b3da0c7 100644
--- a/arch/arm/mach-bcm283x/reset.c
+++ b/arch/arm/mach-bcm283x/reset.c
@@ -23,11 +23,7 @@
/* max ticks timeout */
#define BCM2835_WDOG_MAX_TIMEOUT 0x000fffff
-#ifdef CONFIG_BCM2835_WDT
-extern void hw_watchdog_disable(void);
-#else
void hw_watchdog_disable(void) {}
-#endif
__efi_runtime_data struct bcm2835_wdog_regs *wdog_regs =
(struct bcm2835_wdog_regs *)BCM2835_WDOG_PHYSADDR;
diff --git a/arch/arm/mach-davinci/cpu.c b/arch/arm/mach-davinci/cpu.c
index f97ad3f..9fd6564 100644
--- a/arch/arm/mach-davinci/cpu.c
+++ b/arch/arm/mach-davinci/cpu.c
@@ -5,7 +5,6 @@
*/
#include <common.h>
-#include <netdev.h>
#include <asm/arch/hardware.h>
#include <asm/io.h>
@@ -90,15 +89,3 @@
gd->bd->bi_dsp_freq = 0;
return 0;
}
-
-/*
- * Initializes on-chip ethernet controllers.
- * to override, implement board_eth_init()
- */
-int cpu_eth_init(bd_t *bis)
-{
-#if defined(CONFIG_DRIVER_TI_EMAC)
- davinci_emac_initialize();
-#endif
- return 0;
-}
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
index 3dca50f..c150240 100644
--- a/arch/arm/mach-davinci/include/mach/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -22,11 +22,7 @@
#define gpio_status() gpio_info()
#endif
#define GPIO_NAME_SIZE 20
-#if !defined(CONFIG_SOC_DA850)
-#define MAX_NUM_GPIOS 128
-#else
#define MAX_NUM_GPIOS 144
-#endif
#define GPIO_BANK(gp) (davinci_gpio_bank01 + ((gp) >> 5))
void gpio_info(void);
diff --git a/arch/arm/mach-davinci/misc.c b/arch/arm/mach-davinci/misc.c
index df500c8..80e9642 100644
--- a/arch/arm/mach-davinci/misc.c
+++ b/arch/arm/mach-davinci/misc.c
@@ -9,7 +9,7 @@
*/
#include <common.h>
-#include <environment.h>
+#include <env.h>
#include <i2c.h>
#include <net.h>
#include <asm/arch/hardware.h>
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index b6fd159..aeb5493 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -71,6 +71,17 @@
This enables the 'hdmidet' command which detects if an HDMI monitor
is connected.
+config CMD_NANDBCB
+ bool "i.MX6 NAND Boot Control Block(BCB) command"
+ depends on NAND && CMD_MTDPARTS
+ default y if ARCH_MX6 && NAND_MXS
+ help
+ Unlike normal 'nand write/erase' commands, this command update
+ Boot Control Block(BCB) for i.MX6 platform NAND IP's.
+
+ This is similar to kobs-ng, which is used in Linux as separate
+ rootfs package.
+
config NXP_BOARD_REVISION
bool "Read NXP board revision from fuses"
depends on ARCH_MX6 || ARCH_MX7
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 898478f..08ee52e 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -59,6 +59,7 @@
obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o
obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
obj-$(CONFIG_CMD_DEKBLOB) += cmd_dek.o
+obj-$(CONFIG_CMD_NANDBCB) += cmd_nandbcb.o
endif
PLUGIN = board/$(BOARDDIR)/plugin
diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c
index 463b869..1b111ba 100644
--- a/arch/arm/mach-imx/cmd_dek.c
+++ b/arch/arm/mach-imx/cmd_dek.c
@@ -7,7 +7,6 @@
#include <common.h>
#include <command.h>
-#include <environment.h>
#include <malloc.h>
#include <asm/byteorder.h>
#include <linux/compiler.h>
diff --git a/arch/arm/mach-imx/cmd_nandbcb.c b/arch/arm/mach-imx/cmd_nandbcb.c
new file mode 100644
index 0000000..065b814
--- /dev/null
+++ b/arch/arm/mach-imx/cmd_nandbcb.c
@@ -0,0 +1,369 @@
+/*
+ * i.MX6 nand boot control block(bcb).
+ *
+ * Based on the common/imx-bbu-nand-fcb.c from barebox and imx kobs-ng
+ *
+ * Copyright (C) 2017 Jagan Teki <jagan@amarulasolutions.com>
+ * Copyright (C) 2016 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <nand.h>
+
+#include <asm/io.h>
+#include <jffs2/jffs2.h>
+#include <linux/mtd/mtd.h>
+
+#include <asm/mach-imx/imx-nandbcb.h>
+#include <asm/mach-imx/imximage.cfg>
+#include <mxs_nand.h>
+#include <linux/mtd/mtd.h>
+#include <nand.h>
+
+#define BF_VAL(v, bf) (((v) & bf##_MASK) >> bf##_OFFSET)
+#define GETBIT(v, n) (((v) >> (n)) & 0x1)
+
+static u8 calculate_parity_13_8(u8 d)
+{
+ u8 p = 0;
+
+ p |= (GETBIT(d, 6) ^ GETBIT(d, 5) ^ GETBIT(d, 3) ^ GETBIT(d, 2)) << 0;
+ p |= (GETBIT(d, 7) ^ GETBIT(d, 5) ^ GETBIT(d, 4) ^ GETBIT(d, 2) ^
+ GETBIT(d, 1)) << 1;
+ p |= (GETBIT(d, 7) ^ GETBIT(d, 6) ^ GETBIT(d, 5) ^ GETBIT(d, 1) ^
+ GETBIT(d, 0)) << 2;
+ p |= (GETBIT(d, 7) ^ GETBIT(d, 4) ^ GETBIT(d, 3) ^ GETBIT(d, 0)) << 3;
+ p |= (GETBIT(d, 6) ^ GETBIT(d, 4) ^ GETBIT(d, 3) ^ GETBIT(d, 2) ^
+ GETBIT(d, 1) ^ GETBIT(d, 0)) << 4;
+
+ return p;
+}
+
+static void encode_hamming_13_8(void *_src, void *_ecc, size_t size)
+{
+ int i;
+ u8 *src = _src;
+ u8 *ecc = _ecc;
+
+ for (i = 0; i < size; i++)
+ ecc[i] = calculate_parity_13_8(src[i]);
+}
+
+static u32 calc_chksum(void *buf, size_t size)
+{
+ u32 chksum = 0;
+ u8 *bp = buf;
+ size_t i;
+
+ for (i = 0; i < size; i++)
+ chksum += bp[i];
+
+ return ~chksum;
+}
+
+static void fill_fcb(struct fcb_block *fcb, struct mtd_info *mtd)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
+
+ fcb->fingerprint = FCB_FINGERPRINT;
+ fcb->version = FCB_VERSION_1;
+ fcb->pagesize = mtd->writesize;
+ fcb->oob_pagesize = mtd->writesize + mtd->oobsize;
+ fcb->sectors = mtd->erasesize / mtd->writesize;
+
+ /* Divide ECC strength by two and save the value into FCB structure. */
+ fcb->ecc_level = nand_info->bch_geometry.ecc_strength >> 1;
+
+ fcb->ecc_type = fcb->ecc_level;
+
+ /* Also hardcoded in kobs-ng */
+ fcb->ecc_nr = 0x00000200;
+ fcb->ecc_size = 0x00000200;
+ fcb->datasetup = 80;
+ fcb->datahold = 60;
+ fcb->addr_setup = 25;
+ fcb->dsample_time = 6;
+ fcb->meta_size = 10;
+
+ /* DBBT search area starts at second page on first block */
+ fcb->dbbt_start = 1;
+
+ fcb->bb_byte = nand_info->bch_geometry.block_mark_byte_offset;
+ fcb->bb_start_bit = nand_info->bch_geometry.block_mark_bit_offset;
+
+ fcb->phy_offset = mtd->writesize;
+
+ fcb->nr_blocks = mtd->writesize / fcb->ecc_nr - 1;
+
+ fcb->checksum = calc_chksum((void *)fcb + 4, sizeof(*fcb) - 4);
+}
+
+static int dbbt_fill_data(struct mtd_info *mtd, void *buf, int num_blocks)
+{
+ int n, n_bad_blocks = 0;
+ u32 *bb = buf + 0x8;
+ u32 *n_bad_blocksp = buf + 0x4;
+
+ for (n = 0; n < num_blocks; n++) {
+ loff_t offset = n * mtd->erasesize;
+ if (mtd_block_isbad(mtd, offset)) {
+ n_bad_blocks++;
+ *bb = n;
+ bb++;
+ }
+ }
+
+ *n_bad_blocksp = n_bad_blocks;
+
+ return n_bad_blocks;
+}
+
+static int nandbcb_update(struct mtd_info *mtd, loff_t off, size_t size,
+ size_t maxsize, const u_char *buf)
+{
+ nand_erase_options_t opts;
+ struct fcb_block *fcb;
+ struct dbbt_block *dbbt;
+ loff_t fw1_off;
+ void *fwbuf, *fcb_raw_page, *dbbt_page, *dbbt_data_page;
+ int nr_blks, nr_blks_fcb, fw1_blk;
+ size_t fwsize, dummy;
+ int i, ret;
+
+ /* erase */
+ memset(&opts, 0, sizeof(opts));
+ opts.offset = off;
+ opts.length = maxsize - 1;
+ ret = nand_erase_opts(mtd, &opts);
+ if (ret) {
+ printf("%s: erase failed (ret = %d)\n", __func__, ret);
+ return ret;
+ }
+
+ /*
+ * Reference documentation from i.MX6DQRM section 8.5.2.2
+ *
+ * Nand Boot Control Block(BCB) contains two data structures,
+ * - Firmware Configuration Block(FCB)
+ * - Discovered Bad Block Table(DBBT)
+ *
+ * FCB contains,
+ * - nand timings
+ * - DBBT search page address,
+ * - start page address of primary firmware
+ * - start page address of secondary firmware
+ *
+ * setup fcb:
+ * - number of blocks = mtd partition size / mtd erasesize
+ * - two firmware blocks, primary and secondary
+ * - first 4 block for FCB/DBBT
+ * - rest split in half for primary and secondary firmware
+ * - same firmware will write two times
+ */
+ nr_blks_fcb = 2;
+ nr_blks = maxsize / mtd->erasesize;
+ fw1_blk = nr_blks_fcb;
+
+ /* write fw */
+ fwsize = ALIGN(size + FLASH_OFFSET_STANDARD + mtd->writesize,
+ mtd->writesize);
+ fwbuf = kzalloc(fwsize, GFP_KERNEL);
+ if (!fwbuf) {
+ debug("failed to allocate fwbuf\n");
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ memcpy(fwbuf + FLASH_OFFSET_STANDARD, buf, size);
+ fw1_off = fw1_blk * mtd->erasesize;
+ ret = nand_write_skip_bad(mtd, fw1_off, &fwsize, NULL, maxsize,
+ (u_char *)fwbuf, WITH_WR_VERIFY);
+ printf("NAND fw write: 0x%llx offset, 0x%x bytes written: %s\n",
+ fw1_off, fwsize, ret ? "ERROR" : "OK");
+ if (ret)
+ goto fwbuf_err;
+
+ /* fill fcb */
+ fcb = kzalloc(sizeof(*fcb), GFP_KERNEL);
+ if (!fcb) {
+ debug("failed to allocate fcb\n");
+ ret = -ENOMEM;
+ goto fwbuf_err;
+ }
+
+ fcb->fw1_start = (fw1_blk * mtd->erasesize) / mtd->writesize;
+ fcb->fw1_pages = size / mtd->writesize + 1;
+ fill_fcb(fcb, mtd);
+
+ /* fill dbbt */
+ dbbt_page = kzalloc(mtd->writesize, GFP_KERNEL);
+ if (!dbbt_page) {
+ debug("failed to allocate dbbt_page\n");
+ ret = -ENOMEM;
+ goto fcb_err;
+ }
+
+ dbbt_data_page = kzalloc(mtd->writesize, GFP_KERNEL);
+ if (!dbbt_data_page) {
+ debug("failed to allocate dbbt_data_page\n");
+ ret = -ENOMEM;
+ goto dbbt_page_err;
+ }
+
+ dbbt = dbbt_page;
+ dbbt->checksum = 0;
+ dbbt->fingerprint = DBBT_FINGERPRINT2;
+ dbbt->version = DBBT_VERSION_1;
+ ret = dbbt_fill_data(mtd, dbbt_data_page, nr_blks);
+ if (ret < 0)
+ goto dbbt_data_page_err;
+ else if (ret > 0)
+ dbbt->dbbtpages = 1;
+
+ /* write fcb/dbbt */
+ fcb_raw_page = kzalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL);
+ if (!fcb_raw_page) {
+ debug("failed to allocate fcb_raw_page\n");
+ ret = -ENOMEM;
+ goto dbbt_data_page_err;
+ }
+
+ memcpy(fcb_raw_page + 12, fcb, sizeof(struct fcb_block));
+ encode_hamming_13_8(fcb_raw_page + 12, fcb_raw_page + 12 + 512, 512);
+ /*
+ * Set the first and second byte of OOB data to 0xFF, not 0x00. These
+ * bytes are used as the Manufacturers Bad Block Marker (MBBM). Since
+ * the FCB is mostly written to the first page in a block, a scan for
+ * factory bad blocks will detect these blocks as bad, e.g. when
+ * function nand_scan_bbt() is executed to build a new bad block table.
+ */
+ memset(fcb_raw_page + mtd->writesize, 0xFF, 2);
+
+ for (i = 0; i < nr_blks_fcb; i++) {
+ if (mtd_block_isbad(mtd, off)) {
+ printf("Block %d is bad, skipped\n", i);
+ continue;
+ }
+
+ /* raw write */
+ mtd_oob_ops_t ops = {
+ .datbuf = (u8 *)fcb_raw_page,
+ .oobbuf = ((u8 *)fcb_raw_page) + mtd->writesize,
+ .len = mtd->writesize,
+ .ooblen = mtd->oobsize,
+ .mode = MTD_OPS_RAW
+ };
+
+ ret = mtd_write_oob(mtd, mtd->erasesize * i, &ops);
+ if (ret)
+ goto fcb_raw_page_err;
+ debug("NAND fcb write: 0x%x offset, 0x%x bytes written: %s\n",
+ mtd->erasesize * i, ops.len, ret ? "ERROR" : "OK");
+
+ ret = mtd_write(mtd, mtd->erasesize * i + mtd->writesize,
+ mtd->writesize, &dummy, dbbt_page);
+ if (ret)
+ goto fcb_raw_page_err;
+ debug("NAND dbbt write: 0x%x offset, 0x%x bytes written: %s\n",
+ mtd->erasesize * i + mtd->writesize, dummy,
+ ret ? "ERROR" : "OK");
+
+ /* dbbtpages == 0 if no bad blocks */
+ if (dbbt->dbbtpages > 0) {
+ loff_t to = (mtd->erasesize * i + mtd->writesize * 5);
+
+ ret = mtd_write(mtd, to, mtd->writesize, &dummy,
+ dbbt_data_page);
+ if (ret)
+ goto fcb_raw_page_err;
+ }
+ }
+
+fcb_raw_page_err:
+ kfree(fcb_raw_page);
+dbbt_data_page_err:
+ kfree(dbbt_data_page);
+dbbt_page_err:
+ kfree(dbbt_page);
+fcb_err:
+ kfree(fcb);
+fwbuf_err:
+ kfree(fwbuf);
+err:
+ return ret;
+}
+
+static int do_nandbcb_update(int argc, char * const argv[])
+{
+ struct mtd_info *mtd;
+ loff_t addr, offset, size, maxsize;
+ char *endp;
+ u_char *buf;
+ int dev;
+ int ret;
+
+ if (argc != 4)
+ return CMD_RET_USAGE;
+
+ dev = nand_curr_device;
+ if (dev < 0) {
+ printf("failed to get nand_curr_device, run nand device");
+ return CMD_RET_FAILURE;
+ }
+
+ addr = simple_strtoul(argv[1], &endp, 16);
+ if (*argv[1] == 0 || *endp != 0)
+ return CMD_RET_FAILURE;
+
+ mtd = get_nand_dev_by_index(dev);
+ if (mtd_arg_off_size(argc - 2, argv + 2, &dev, &offset, &size,
+ &maxsize, MTD_DEV_TYPE_NAND, mtd->size))
+ return CMD_RET_FAILURE;
+
+ buf = map_physmem(addr, size, MAP_WRBACK);
+ if (!buf) {
+ puts("failed to map physical memory\n");
+ return CMD_RET_FAILURE;
+ }
+
+ ret = nandbcb_update(mtd, offset, size, maxsize, buf);
+
+ return ret == 0 ? CMD_RET_SUCCESS : CMD_RET_FAILURE;
+}
+
+static int do_nandbcb(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ const char *cmd;
+ int ret = 0;
+
+ if (argc < 5)
+ goto usage;
+
+ cmd = argv[1];
+ --argc;
+ ++argv;
+
+ if (strcmp(cmd, "update") == 0) {
+ ret = do_nandbcb_update(argc, argv);
+ goto done;
+ }
+
+done:
+ if (ret != -1)
+ return ret;
+usage:
+ return CMD_RET_USAGE;
+}
+
+static char nandbcb_help_text[] =
+ "update addr off|partition len - update 'len' bytes starting at\n"
+ " 'off|part' to memory address 'addr', skipping bad blocks";
+
+U_BOOT_CMD(nandbcb, 5, 1, do_nandbcb,
+ "i.MX6 Nand BCB",
+ nandbcb_help_text
+);
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index d62ff6e..6e9a175 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -21,8 +21,8 @@
#include <thermal.h>
#include <sata.h>
-#ifdef CONFIG_FSL_ESDHC
-#include <fsl_esdhc.h>
+#ifdef CONFIG_FSL_ESDHC_IMX
+#include <fsl_esdhc_imx.h>
#endif
static u32 reset_cause = -1;
@@ -258,7 +258,7 @@
return rc;
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
/*
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()
@@ -289,10 +289,12 @@
imx_pcie_remove();
#endif
#if defined(CONFIG_SATA)
- sata_remove(0);
+ if (!is_mx6sdl()) {
+ sata_remove(0);
#if defined(CONFIG_MX6)
- disable_sata_clock();
+ disable_sata_clock();
#endif
+ }
#endif
#if defined(CONFIG_VIDEO_IPUV3)
/* disable video before launching O/S */
diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c
index 24d1629..ce50dbe 100644
--- a/arch/arm/mach-imx/hab.c
+++ b/arch/arm/mach-imx/hab.c
@@ -310,7 +310,7 @@
buf = map_sysmem(img_addr, 0);
switch (genimg_get_format(buf)) {
-#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
+#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
case IMAGE_FORMAT_LEGACY:
return (image_get_image_size((image_header_t *)img_addr)
+ 0x1000 - 1) & ~(0x1000 - 1);
diff --git a/arch/arm/mach-imx/imx8/Makefile b/arch/arm/mach-imx/imx8/Makefile
index 31ad169..92b5c56 100644
--- a/arch/arm/mach-imx/imx8/Makefile
+++ b/arch/arm/mach-imx/imx8/Makefile
@@ -4,4 +4,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += cpu.o iomux.o
+obj-y += cpu.o iomux.o misc.o
diff --git a/arch/arm/mach-imx/imx8/misc.c b/arch/arm/mach-imx/imx8/misc.c
new file mode 100644
index 0000000..fe73e29
--- /dev/null
+++ b/arch/arm/mach-imx/imx8/misc.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <common.h>
+#include <asm/arch/sci/sci.h>
+
+int sc_pm_setup_uart(sc_rsrc_t uart_rsrc, sc_pm_clock_rate_t clk_rate)
+{
+ sc_pm_clock_rate_t rate = clk_rate;
+ int ret;
+
+ /* Power up UARTn */
+ ret = sc_pm_set_resource_power_mode(-1, uart_rsrc, SC_PM_PW_MODE_ON);
+ if (ret)
+ return ret;
+
+ /* Set UARTn clock root to 'rate' MHz */
+ ret = sc_pm_set_clock_rate(-1, uart_rsrc, SC_PM_CLK_PER, &rate);
+ if (ret)
+ return ret;
+
+ /* Enable UARTn clock root */
+ ret = sc_pm_clock_enable(-1, uart_rsrc, SC_PM_CLK_PER, true, false);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+void build_info(void)
+{
+ u32 sc_build = 0, sc_commit = 0;
+
+ /* Get SCFW build and commit id */
+ sc_misc_build_info(-1, &sc_build, &sc_commit);
+ if (!sc_build) {
+ printf("SCFW does not support build info\n");
+ sc_commit = 0; /* Display 0 if build info not supported */
+ }
+ printf("Build: SCFW %x\n", sc_commit);
+}
diff --git a/arch/arm/mach-imx/mx6/litesom.c b/arch/arm/mach-imx/mx6/litesom.c
index c332d68..4f4df74 100644
--- a/arch/arm/mach-imx/mx6/litesom.c
+++ b/arch/arm/mach-imx/mx6/litesom.c
@@ -16,7 +16,7 @@
#include <asm/mach-imx/boot_mode.h>
#include <asm/io.h>
#include <common.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <linux/sizes.h>
#include <mmc.h>
@@ -49,7 +49,7 @@
MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
static struct fsl_esdhc_cfg emmc_cfg = {USDHC2_BASE_ADDR, 0, 8};
#define EMMC_PWR_GPIO IMX_GPIO_NR(4, 10)
diff --git a/arch/arm/mach-imx/mx6/opos6ul.c b/arch/arm/mach-imx/mx6/opos6ul.c
index 264fa8a..3ab9a3f 100644
--- a/arch/arm/mach-imx/mx6/opos6ul.c
+++ b/arch/arm/mach-imx/mx6/opos6ul.c
@@ -13,7 +13,7 @@
#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
#include <common.h>
-#include <environment.h>
+#include <env.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -127,7 +127,7 @@
/* In bootstrap don't use the env vars */
if (((reg & 0x3000000) >> 24) == 0x1) {
- set_default_env(NULL, 0);
+ env_set_default(NULL, 0);
env_set("preboot", "");
}
diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
index e80f1d4..075d246 100644
--- a/arch/arm/mach-imx/mx6/soc.c
+++ b/arch/arm/mach-imx/mx6/soc.c
@@ -95,6 +95,11 @@
type = MXC_CPU_MX6DP;
}
reg &= 0xff; /* mx6 silicon revision */
+
+ /* For 6DQ, the value 0x00630005 is Silicon revision 1.3*/
+ if (((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D)) && (reg == 0x5))
+ reg = 0x3;
+
return (type << 12) | (reg + (0x10 * (major + 1)));
}
@@ -549,7 +554,7 @@
void reset_misc(void)
{
#ifndef CONFIG_SPL_BUILD
-#ifdef CONFIG_VIDEO_MXS
+#if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
lcdif_power_down();
#endif
#endif
diff --git a/arch/arm/mach-imx/mx7/clock.c b/arch/arm/mach-imx/mx7/clock.c
index e364b16..4f9724c 100644
--- a/arch/arm/mach-imx/mx7/clock.c
+++ b/arch/arm/mach-imx/mx7/clock.c
@@ -19,13 +19,13 @@
ANATOP_BASE_ADDR;
struct mxc_ccm_reg *ccm_reg = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
DECLARE_GLOBAL_DATA_PTR;
#endif
int get_clocks(void)
{
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
diff --git a/arch/arm/mach-imx/mx7/psci-mx7.c b/arch/arm/mach-imx/mx7/psci-mx7.c
index 34ba0a9..c98d2e9 100644
--- a/arch/arm/mach-imx/mx7/psci-mx7.c
+++ b/arch/arm/mach-imx/mx7/psci-mx7.c
@@ -298,7 +298,7 @@
return psci_state[cpu];
}
-__secure s32 psci_migrate_info_type(u32 function_id)
+__secure u32 psci_migrate_info_type(void)
{
/* Trusted OS is either not present or does not require migration */
return 2;
diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c
index 1b4bbc5..3b8e1ba 100644
--- a/arch/arm/mach-imx/mx7/soc.c
+++ b/arch/arm/mach-imx/mx7/soc.c
@@ -14,6 +14,7 @@
#include <asm/arch/imx-rdc.h>
#include <asm/arch/crm_regs.h>
#include <dm.h>
+#include <env.h>
#include <imx_thermal.h>
#include <fsl_sec.h>
#include <asm/setup.h>
diff --git a/arch/arm/mach-imx/mx7ulp/clock.c b/arch/arm/mach-imx/mx7ulp/clock.c
index fac9011..dc317fe 100644
--- a/arch/arm/mach-imx/mx7ulp/clock.c
+++ b/arch/arm/mach-imx/mx7ulp/clock.c
@@ -14,7 +14,7 @@
int get_clocks(void)
{
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC0_RBASE
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC1_RBASE
diff --git a/arch/arm/mach-imx/speed.c b/arch/arm/mach-imx/speed.c
index ab134d0..f9e486c 100644
--- a/arch/arm/mach-imx/speed.c
+++ b/arch/arm/mach-imx/speed.c
@@ -11,13 +11,13 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
DECLARE_GLOBAL_DATA_PTR;
#endif
int get_clocks(void)
{
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
#ifdef CONFIG_FSL_USDHC
#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index 9f1e0f6..1f230ac 100644
--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c
@@ -24,6 +24,7 @@
{
unsigned int bmode = readl(&src_base->sbmr2);
u32 reg = imx6_src_get_boot_mode();
+ u32 mmc_index = ((reg >> 11) & 0x03);
/*
* Check for BMODE if serial downloader is enabled
@@ -84,11 +85,12 @@
/* SD/eSD: 8.5.3, Table 8-15 */
case IMX6_BMODE_SD:
case IMX6_BMODE_ESD:
- return BOOT_DEVICE_MMC1;
- /* MMC/eMMC: 8.5.3 */
case IMX6_BMODE_MMC:
case IMX6_BMODE_EMMC:
- return BOOT_DEVICE_MMC1;
+ if (mmc_index == 1)
+ return BOOT_DEVICE_MMC2;
+ else
+ return BOOT_DEVICE_MMC1;
/* NAND Flash: 8.5.2, Table 8-10 */
case IMX6_BMODE_NAND_MIN ... IMX6_BMODE_NAND_MAX:
return BOOT_DEVICE_NAND;
diff --git a/arch/arm/mach-imx/video.c b/arch/arm/mach-imx/video.c
index 22a371a..1bc9b7c 100644
--- a/arch/arm/mach-imx/video.c
+++ b/arch/arm/mach-imx/video.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
#include <common.h>
+#include <env.h>
#include <linux/errno.h>
#include <asm/mach-imx/video.h>
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index e677a2e..de1c1cc 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -7,6 +7,9 @@
config SOC_K3_AM6
bool "TI's K3 based AM6 SoC Family Support"
+config SOC_K3_J721E
+ bool "TI's K3 based J721E SoC Family Support"
+
endchoice
config SYS_SOC
@@ -14,7 +17,8 @@
config SYS_K3_NON_SECURE_MSRAM_SIZE
hex
- default 0x80000
+ default 0x80000 if SOC_K3_AM6
+ default 0x100000 if SOC_K3_J721E
help
Describes the total size of the MCU MSRAM. This doesn't
specify the total size of SPL as ROM can use some part
@@ -23,7 +27,8 @@
config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
hex
- default 0x58000
+ default 0x58000 if SOC_K3_AM6
+ default 0xc0000 if SOC_K3_J721E
help
Describes the maximum size of the image that ROM can download
from any boot media.
@@ -31,18 +36,21 @@
config SYS_K3_MCU_SCRATCHPAD_BASE
hex
default 0x40280000 if SOC_K3_AM6
+ default 0x40280000 if SOC_K3_J721E
help
Describes the base address of MCU Scratchpad RAM.
config SYS_K3_MCU_SCRATCHPAD_SIZE
hex
default 0x200 if SOC_K3_AM6
+ default 0x200 if SOC_K3_J721E
help
Describes the size of MCU Scratchpad RAM.
config SYS_K3_BOOT_PARAM_TABLE_INDEX
hex
default 0x41c7fbfc if SOC_K3_AM6
+ default 0x41cffc00 if SOC_K3_J721E
help
Address at which ROM stores the value which determines if SPL
is booted up by primary boot media or secondary boot media.
@@ -58,6 +66,45 @@
int
default 16
+config K3_LOAD_SYSFW
+ bool
+ depends on SPL
+
+config K3_SYSFW_IMAGE_NAME
+ string "File name of SYSFW firmware and configuration blob"
+ depends on K3_LOAD_SYSFW
+ default "sysfw.itb"
+ help
+ Filename of the combined System Firmware and configuration image tree
+ blob to be loaded when booting from a filesystem.
+
+config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_SECT
+ hex "MMC sector to load SYSFW firmware and configuration blob from"
+ depends on K3_LOAD_SYSFW && SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+ default 0x3600
+ help
+ Address on the MMC to load the combined System Firmware and
+ configuration image tree blob from, when the MMC is being used
+ in raw mode. Units: MMC sectors (1 sector = 512 bytes).
+
+config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_PART
+ hex "MMC partition to load SYSFW firmware and configuration blob from"
+ depends on K3_LOAD_SYSFW && SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
+ default 2
+ help
+ Partition on the MMC to the combined System Firmware and configuration
+ image tree blob from, when the MMC is being used in raw mode.
+
+config K3_SYSFW_IMAGE_SIZE_MAX
+ int "Amount of memory dynamically allocated for loading SYSFW blob"
+ depends on K3_LOAD_SYSFW
+ default 276000
+ help
+ Amount of memory (in bytes) reserved through dynamic allocation at
+ runtime for loading the combined System Firmware and configuration image
+ tree blob. Keep it as tight as possible, as this directly affects the
+ overall SPL memory footprint.
+
config SYS_K3_SPL_ATF
bool "Start Cortex-A from SPL"
depends on SPL && CPU_V7R
@@ -66,4 +113,5 @@
after SPL from R5.
source "board/ti/am65x/Kconfig"
+source "board/ti/j721e/Kconfig"
endif
diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index 0c3a4f7..028015e 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -4,7 +4,11 @@
# Lokesh Vutla <lokeshvutla@ti.com>
obj-$(CONFIG_SOC_K3_AM6) += am6_init.o
+obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o
obj-$(CONFIG_ARM64) += arm64-mmu.o
obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
obj-$(CONFIG_TI_SECURE_DEVICE) += security.o
+ifeq ($(CONFIG_SPL_BUILD),y)
+obj-$(CONFIG_K3_LOAD_SYSFW) += sysfw-loader.o
+endif
obj-y += common.o
diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c
index 60a5803..0b564f7 100644
--- a/arch/arm/mach-k3/am6_init.c
+++ b/arch/arm/mach-k3/am6_init.c
@@ -10,8 +10,13 @@
#include <asm/io.h>
#include <spl.h>
#include <asm/arch/hardware.h>
+#include <asm/arch/sysfw-loader.h>
+#include <asm/arch/sys_proto.h>
#include "common.h"
#include <dm.h>
+#include <dm/uclass-internal.h>
+#include <dm/pinctrl.h>
+#include <linux/soc/ti/ti_sci_protocol.h>
#ifdef CONFIG_SPL_BUILD
static void mmr_unlock(u32 base, u32 partition)
@@ -63,7 +68,7 @@
void board_init_f(ulong dummy)
{
-#if defined(CONFIG_K3_AM654_DDRSS)
+#if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS)
struct udevice *dev;
int ret;
#endif
@@ -83,8 +88,33 @@
/* Init DM early in-order to invoke system controller */
spl_early_init();
+#ifdef CONFIG_K3_LOAD_SYSFW
+ /*
+ * Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue
+ * regardless of the result of pinctrl. Do this without probing the
+ * device, but instead by searching the device that would request the
+ * given sequence number if probed. The UART will be used by the system
+ * firmware (SYSFW) image for various purposes and SYSFW depends on us
+ * to initialize its pin settings.
+ */
+ ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, true, &dev);
+ if (!ret)
+ pinctrl_select_state(dev, "default");
+
+ /*
+ * Load, start up, and configure system controller firmware. Provide
+ * the U-Boot console init function to the SYSFW post-PM configuration
+ * callback hook, effectively switching on (or over) the console
+ * output.
+ */
+ k3_sysfw_loader(preloader_console_init);
+#else
/* Prepare console output */
preloader_console_init();
+#endif
+
+ /* Perform EEPROM-based board detection */
+ do_board_detect();
#ifdef CONFIG_K3_AM654_DDRSS
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
@@ -180,8 +210,53 @@
}
#endif
-#ifndef CONFIG_SYSRESET
-void reset_cpu(ulong ignored)
+#ifdef CONFIG_SYS_K3_SPL_ATF
+
+#define AM6_DEV_MCU_RTI0 134
+#define AM6_DEV_MCU_RTI1 135
+#define AM6_DEV_MCU_ARMSS0_CPU0 159
+#define AM6_DEV_MCU_ARMSS0_CPU1 245
+
+void release_resources_for_core_shutdown(void)
{
+ struct ti_sci_handle *ti_sci = get_ti_sci_handle();
+ struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops;
+ struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
+ int ret;
+ u32 i;
+
+ const u32 put_device_ids[] = {
+ AM6_DEV_MCU_RTI0,
+ AM6_DEV_MCU_RTI1,
+ };
+
+ /* Iterate through list of devices to put (shutdown) */
+ for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
+ u32 id = put_device_ids[i];
+
+ ret = dev_ops->put_device(ti_sci, id);
+ if (ret)
+ panic("Failed to put device %u (%d)\n", id, ret);
+ }
+
+ const u32 put_core_ids[] = {
+ AM6_DEV_MCU_ARMSS0_CPU1,
+ AM6_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */
+ };
+
+ /* Iterate through list of cores to put (shutdown) */
+ for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
+ u32 id = put_core_ids[i];
+
+ /*
+ * Queue up the core shutdown request. Note that this call
+ * needs to be followed up by an actual invocation of an WFE
+ * or WFI CPU instruction.
+ */
+ ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
+ if (ret)
+ panic("Failed sending core %u shutdown message (%d)\n",
+ id, ret);
+ }
}
#endif
diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c
index a75ba1f..82778d2 100644
--- a/arch/arm/mach-k3/arm64-mmu.c
+++ b/arch/arm/mach-k3/arm64-mmu.c
@@ -12,6 +12,7 @@
#include <asm/system.h>
#include <asm/armv8/mmu.h>
+#ifdef CONFIG_SOC_K3_AM6
/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3)
@@ -43,3 +44,57 @@
};
struct mm_region *mem_map = am654_mem_map;
+#endif /* CONFIG_SOC_K3_AM6 */
+
+#ifdef CONFIG_SOC_K3_J721E
+/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
+#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5)
+
+/* ToDo: Add 64bit IO */
+struct mm_region j721e_mem_map[NR_MMU_REGIONS] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = 0x20000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xa0000000UL,
+ .phys = 0xa0000000UL,
+ .size = 0x0bc00000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
+ PTE_BLOCK_NON_SHARE
+ }, {
+ .virt = 0xabc00000UL,
+ .phys = 0xabc00000UL,
+ .size = 0x54400000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x880000000UL,
+ .phys = 0x880000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x500000000UL,
+ .phys = 0x500000000UL,
+ .size = 0x400000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = j721e_mem_map;
+#endif /* CONFIG_SOC_K3_J721E */
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index 03f01d0..c16afc6 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -13,13 +13,14 @@
#include <remoteproc.h>
#include <linux/soc/ti/ti_sci_protocol.h>
#include <fdt_support.h>
+#include <asm/arch/sys_proto.h>
struct ti_sci_handle *get_ti_sci_handle(void)
{
struct udevice *dev;
int ret;
- ret = uclass_get_device_by_name(UCLASS_FIRMWARE, "dmsc", &dev);
+ ret = uclass_get_device(UCLASS_FIRMWARE, 0, &dev);
if (ret)
panic("Failed to get SYSFW (%d)\n", ret);
@@ -29,8 +30,12 @@
#ifdef CONFIG_SYS_K3_SPL_ATF
void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
{
+ struct ti_sci_handle *ti_sci = get_ti_sci_handle();
int ret;
+ /* Release all the exclusive devices held by SPL before starting ATF */
+ ti_sci->ops.dev_ops.release_exclusive_devices(ti_sci);
+
/*
* It is assumed that remoteproc device 1 is the corresponding
* Cortex-A core which runs ATF. Make sure DT reflects the same.
@@ -51,7 +56,10 @@
if (ret)
panic("%s: ATF failed to start on rproc (%d)\n", __func__, ret);
- debug("ATF started. Waiting indefinitely...\n");
+ debug("Releasing resources...\n");
+ release_resources_for_core_shutdown();
+
+ debug("Finalizing core shutdown...\n");
while (1)
asm volatile("wfe");
}
@@ -129,4 +137,30 @@
return 0;
}
+
+int fdt_disable_node(void *blob, char *node_path)
+{
+ int offs;
+ int ret;
+
+ offs = fdt_path_offset(blob, node_path);
+ if (offs < 0) {
+ debug("Node %s not found.\n", node_path);
+ return 0;
+ }
+ ret = fdt_setprop_string(blob, offs, "status", "disabled");
+ if (ret < 0) {
+ printf("Could not add status property to node %s: %s\n",
+ node_path, fdt_strerror(ret));
+ return ret;
+ }
+ return 0;
+}
+
+#endif
+
+#ifndef CONFIG_SYSRESET
+void reset_cpu(ulong ignored)
+{
+}
#endif
diff --git a/arch/arm/mach-k3/include/mach/am6_hardware.h b/arch/arm/mach-k3/include/mach/am6_hardware.h
index 3343233..6df7631 100644
--- a/arch/arm/mach-k3/include/mach/am6_hardware.h
+++ b/arch/arm/mach-k3/include/mach/am6_hardware.h
@@ -44,4 +44,7 @@
#define CTRLMMR_LOCK_KICK1 0x0100c
#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
+/* MCU SCRATCHPAD usage */
+#define TI_SRAM_SCRATCH_BOARD_EEPROM_START CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE
+
#endif /* __ASM_ARCH_AM6_HARDWARE_H */
diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h
index b39f780..4e62982 100644
--- a/arch/arm/mach-k3/include/mach/hardware.h
+++ b/arch/arm/mach-k3/include/mach/hardware.h
@@ -9,4 +9,8 @@
#ifdef CONFIG_SOC_K3_AM6
#include "am6_hardware.h"
#endif
+
+#ifdef CONFIG_SOC_K3_J721E
+#include "j721e_hardware.h"
+#endif
#endif /* _ASM_ARCH_HARDWARE_H_ */
diff --git a/arch/arm/mach-k3/include/mach/j721e_hardware.h b/arch/arm/mach-k3/include/mach/j721e_hardware.h
new file mode 100644
index 0000000..8d42977
--- /dev/null
+++ b/arch/arm/mach-k3/include/mach/j721e_hardware.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * K3: J721E SoC definitions, structures etc.
+ *
+ * (C) Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#ifndef __ASM_ARCH_J721E_HARDWARE_H
+#define __ASM_ARCH_J721E_HARDWARE_H
+
+#include <config.h>
+
+#define CTRL_MMR0_BASE 0x00100000
+#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30)
+
+#define MAIN_DEVSTAT_BOOT_MODE_B_MASK BIT(0)
+#define MAIN_DEVSTAT_BOOT_MODE_B_SHIFT 0
+#define MAIN_DEVSTAT_BKUP_BOOTMODE_MASK GENMASK(3, 1)
+#define MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT 1
+#define MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK BIT(6)
+#define MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT 6
+
+#define WKUP_CTRL_MMR0_BASE 0x43000000
+#define MCU_CTRL_MMR0_BASE 0x40f00000
+
+#define CTRLMMR_WKUP_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30)
+#define WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(5, 3)
+#define WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3
+#define WKUP_DEVSTAT_MCU_OMLY_MASK BIT(6)
+#define WKUP_DEVSTAT_MCU_ONLY_SHIFT 6
+
+/*
+ * The CTRL_MMR0 memory space is divided into several equally-spaced
+ * partitions, so defining the partition size allows us to determine
+ * register addresses common to those partitions.
+ */
+#define CTRL_MMR0_PARTITION_SIZE 0x4000
+
+/*
+ * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTR_MMR0 lock/kick-mechanism
+ * shared register definitions.
+ */
+#define CTRLMMR_LOCK_KICK0 0x01008
+#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490
+#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0)
+#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0
+#define CTRLMMR_LOCK_KICK1 0x0100c
+#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
+
+#endif /* __ASM_ARCH_J721E_HARDWARE_H */
diff --git a/arch/arm/mach-k3/include/mach/j721e_spl.h b/arch/arm/mach-k3/include/mach/j721e_spl.h
new file mode 100644
index 0000000..2b52faf
--- /dev/null
+++ b/arch/arm/mach-k3/include/mach/j721e_spl.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Lokesh Vutla <lokeshvutla@ti.com>
+ */
+#ifndef _ASM_ARCH_J721E_SPL_H_
+#define _ASM_ARCH_J721E_SPL_H_
+
+/* With BootMode B = 0 */
+#define BOOT_DEVICE_HYPERFLASH 0x00
+#define BOOT_DEVICE_OSPI 0x01
+#define BOOT_DEVICE_QSPI 0x02
+#define BOOT_DEVICE_SPI 0x03
+#define BOOT_DEVICE_ETHERNET 0x04
+#define BOOT_DEVICE_I2C 0x06
+#define BOOT_DEVICE_UART 0x07
+
+/* With BootMode B = 1 */
+#define BOOT_DEVICE_MMC2 0x10
+#define BOOT_DEVICE_MMC1 0x11
+#define BOOT_DEVICE_USB 0x12
+#define BOOT_DEVICE_UFS 0x13
+#define BOOT_DEVIE_GPMC 0x14
+#define BOOT_DEVICE_PCIE 0x15
+#define BOOT_DEVICE_MMC2_2 0x16
+#define BOOT_DEVICE_RAM 0x17
+
+#define BOOT_MODE_B_SHIFT 4
+#define BOOT_MODE_B_MASK BIT(4)
+
+#endif
diff --git a/arch/arm/mach-k3/include/mach/spl.h b/arch/arm/mach-k3/include/mach/spl.h
index 2d435ae..a26c8ec 100644
--- a/arch/arm/mach-k3/include/mach/spl.h
+++ b/arch/arm/mach-k3/include/mach/spl.h
@@ -9,4 +9,8 @@
#ifdef CONFIG_SOC_K3_AM6
#include "am6_spl.h"
#endif
+
+#ifdef CONFIG_SOC_K3_J721E
+#include "j721e_spl.h"
+#endif
#endif /* _ASM_ARCH_SPL_H_ */
diff --git a/arch/arm/mach-k3/include/mach/sys_proto.h b/arch/arm/mach-k3/include/mach/sys_proto.h
index 018725b..3c825aa 100644
--- a/arch/arm/mach-k3/include/mach/sys_proto.h
+++ b/arch/arm/mach-k3/include/mach/sys_proto.h
@@ -12,4 +12,8 @@
u32 bound);
struct ti_sci_handle *get_ti_sci_handle(void);
int fdt_fixup_msmc_ram(void *blob, char *parent_path, char *node_name);
+int do_board_detect(void);
+void release_resources_for_core_shutdown(void);
+int fdt_disable_node(void *blob, char *node_path);
+
#endif
diff --git a/arch/arm/mach-k3/include/mach/sysfw-loader.h b/arch/arm/mach-k3/include/mach/sysfw-loader.h
new file mode 100644
index 0000000..36eb265
--- /dev/null
+++ b/arch/arm/mach-k3/include/mach/sysfw-loader.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Andreas Dannenberg <dannenberg@ti.com>
+ */
+
+#ifndef _SYSFW_LOADER_H_
+#define _SYSFW_LOADER_H_
+
+void k3_sysfw_loader(void (*config_pm_done_callback)(void));
+
+#endif
diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
new file mode 100644
index 0000000..733e414
--- /dev/null
+++ b/arch/arm/mach-k3/j721e_init.c
@@ -0,0 +1,228 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * J721E: SoC specific initialization
+ *
+ * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Lokesh Vutla <lokeshvutla@ti.com>
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/armv7_mpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sysfw-loader.h>
+#include "common.h"
+#include <asm/arch/sys_proto.h>
+#include <linux/soc/ti/ti_sci_protocol.h>
+#include <dm.h>
+#include <dm/uclass-internal.h>
+#include <dm/pinctrl.h>
+
+#ifdef CONFIG_SPL_BUILD
+static void mmr_unlock(u32 base, u32 partition)
+{
+ /* Translate the base address */
+ phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
+
+ /* Unlock the requested partition if locked using two-step sequence */
+ writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
+ writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
+}
+
+static void ctrl_mmr_unlock(void)
+{
+ /* Unlock all WKUP_CTRL_MMR0 module registers */
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 4);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
+
+ /* Unlock all MCU_CTRL_MMR0 module registers */
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
+
+ /* Unlock all CTRL_MMR0 module registers */
+ mmr_unlock(CTRL_MMR0_BASE, 0);
+ mmr_unlock(CTRL_MMR0_BASE, 1);
+ mmr_unlock(CTRL_MMR0_BASE, 2);
+ mmr_unlock(CTRL_MMR0_BASE, 3);
+ mmr_unlock(CTRL_MMR0_BASE, 4);
+ mmr_unlock(CTRL_MMR0_BASE, 5);
+ mmr_unlock(CTRL_MMR0_BASE, 6);
+ mmr_unlock(CTRL_MMR0_BASE, 7);
+}
+
+/*
+ * This uninitialized global variable would normal end up in the .bss section,
+ * but the .bss is cleared between writing and reading this variable, so move
+ * it to the .data section.
+ */
+u32 bootindex __attribute__((section(".data")));
+
+static void store_boot_index_from_rom(void)
+{
+ bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
+}
+
+void board_init_f(ulong dummy)
+{
+#if defined(CONFIG_K3_LOAD_SYSFW)
+ struct udevice *dev;
+ int ret;
+#endif
+ /*
+ * Cannot delay this further as there is a chance that
+ * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
+ */
+ store_boot_index_from_rom();
+
+ /* Make all control module registers accessible */
+ ctrl_mmr_unlock();
+
+#ifdef CONFIG_CPU_V7R
+ setup_k3_mpu_regions();
+#endif
+
+ /* Init DM early */
+ spl_early_init();
+
+#ifdef CONFIG_K3_LOAD_SYSFW
+ /*
+ * Process pinctrl for the serial0 a.k.a. MCU_UART0 module and continue
+ * regardless of the result of pinctrl. Do this without probing the
+ * device, but instead by searching the device that would request the
+ * given sequence number if probed. The UART will be used by the system
+ * firmware (SYSFW) image for various purposes and SYSFW depends on us
+ * to initialize its pin settings.
+ */
+ ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, true, &dev);
+ if (!ret)
+ pinctrl_select_state(dev, "default");
+
+ /*
+ * Load, start up, and configure system controller firmware. Provide
+ * the U-Boot console init function to the SYSFW post-PM configuration
+ * callback hook, effectively switching on (or over) the console
+ * output.
+ */
+ k3_sysfw_loader(preloader_console_init);
+#else
+ /* Prepare console output */
+ preloader_console_init();
+#endif
+}
+
+u32 spl_boot_mode(const u32 boot_device)
+{
+ switch (boot_device) {
+ case BOOT_DEVICE_MMC1:
+ return MMCSD_MODE_EMMCBOOT;
+ case BOOT_DEVICE_MMC2:
+ return MMCSD_MODE_FS;
+ default:
+ return MMCSD_MODE_RAW;
+ }
+}
+
+static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat)
+{
+
+ u32 bootmode = (wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
+ WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
+
+ bootmode |= (main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) <<
+ BOOT_MODE_B_SHIFT;
+
+ if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
+ bootmode = BOOT_DEVICE_SPI;
+
+ if (bootmode == BOOT_DEVICE_MMC2) {
+ u32 port = (main_devstat &
+ MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK) >>
+ MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT;
+ if (port == 0x0)
+ bootmode = BOOT_DEVICE_MMC1;
+ }
+
+ return bootmode;
+}
+
+u32 spl_boot_device(void)
+{
+ u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT);
+ u32 main_devstat;
+
+ if (wkup_devstat & WKUP_DEVSTAT_MCU_OMLY_MASK) {
+ printf("ERROR: MCU only boot is not yet supported\n");
+ return BOOT_DEVICE_RAM;
+ }
+
+ /* MAIN CTRL MMR can only be read if MCU ONLY is 0 */
+ main_devstat = readl(CTRLMMR_MAIN_DEVSTAT);
+
+ /* ToDo: Add support for backup boot media */
+ return __get_primary_bootmedia(main_devstat, wkup_devstat);
+}
+#endif
+
+#ifdef CONFIG_SYS_K3_SPL_ATF
+
+#define J721E_DEV_MCU_RTI0 262
+#define J721E_DEV_MCU_RTI1 263
+#define J721E_DEV_MCU_ARMSS0_CPU0 250
+#define J721E_DEV_MCU_ARMSS0_CPU1 251
+
+void release_resources_for_core_shutdown(void)
+{
+ struct ti_sci_handle *ti_sci;
+ struct ti_sci_dev_ops *dev_ops;
+ struct ti_sci_proc_ops *proc_ops;
+ int ret;
+ u32 i;
+
+ const u32 put_device_ids[] = {
+ J721E_DEV_MCU_RTI0,
+ J721E_DEV_MCU_RTI1,
+ };
+
+ ti_sci = get_ti_sci_handle();
+ dev_ops = &ti_sci->ops.dev_ops;
+ proc_ops = &ti_sci->ops.proc_ops;
+
+ /* Iterate through list of devices to put (shutdown) */
+ for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
+ u32 id = put_device_ids[i];
+
+ ret = dev_ops->put_device(ti_sci, id);
+ if (ret)
+ panic("Failed to put device %u (%d)\n", id, ret);
+ }
+
+ const u32 put_core_ids[] = {
+ J721E_DEV_MCU_ARMSS0_CPU1,
+ J721E_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */
+ };
+
+ /* Iterate through list of cores to put (shutdown) */
+ for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
+ u32 id = put_core_ids[i];
+
+ /*
+ * Queue up the core shutdown request. Note that this call
+ * needs to be followed up by an actual invocation of an WFE
+ * or WFI CPU instruction.
+ */
+ ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
+ if (ret)
+ panic("Failed sending core %u shutdown message (%d)\n",
+ id, ret);
+ }
+}
+#endif
diff --git a/arch/arm/mach-k3/security.c b/arch/arm/mach-k3/security.c
index 52f49bf..4e011ee 100644
--- a/arch/arm/mach-k3/security.c
+++ b/arch/arm/mach-k3/security.c
@@ -11,25 +11,16 @@
#include <linux/soc/ti/ti_sci_protocol.h>
#include <mach/spl.h>
#include <spl.h>
+#include <asm/arch/sys_proto.h>
void board_fit_image_post_process(void **p_image, size_t *p_size)
{
- struct udevice *dev;
- struct ti_sci_handle *ti_sci;
- struct ti_sci_proc_ops *proc_ops;
+ struct ti_sci_handle *ti_sci = get_ti_sci_handle();
+ struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
u64 image_addr;
u32 image_size;
int ret;
- /* Get handle to Device Management and Security Controller (SYSFW) */
- ret = uclass_get_device_by_name(UCLASS_FIRMWARE, "dmsc", &dev);
- if (ret) {
- printf("Failed to get handle to SYSFW (%d)\n", ret);
- hang();
- }
- ti_sci = (struct ti_sci_handle *)(ti_sci_get_handle_from_sysfw(dev));
- proc_ops = &ti_sci->ops.proc_ops;
-
image_addr = (uintptr_t)*p_image;
debug("Authenticating image at address 0x%016llx\n", image_addr);
diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c
new file mode 100644
index 0000000..7a482bd
--- /dev/null
+++ b/arch/arm/mach-k3/sysfw-loader.c
@@ -0,0 +1,271 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * K3: System Firmware Loader
+ *
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Andreas Dannenberg <dannenberg@ti.com>
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <malloc.h>
+#include <remoteproc.h>
+#include <linux/soc/ti/ti_sci_protocol.h>
+#include <asm/arch/sys_proto.h>
+
+/* Name of the FIT image nodes for SYSFW and its config data */
+#define SYSFW_FIRMWARE "sysfw.bin"
+#define SYSFW_CFG_BOARD "board-cfg.bin"
+#define SYSFW_CFG_PM "pm-cfg.bin"
+#define SYSFW_CFG_RM "rm-cfg.bin"
+#define SYSFW_CFG_SEC "sec-cfg.bin"
+
+static bool sysfw_loaded;
+static void *sysfw_load_address;
+
+/*
+ * Populate SPL hook to override the default load address used by the SPL
+ * loader function with a custom address for SYSFW loading.
+ */
+struct image_header *spl_get_load_buffer(ssize_t offset, size_t size)
+{
+ if (sysfw_loaded)
+ return (struct image_header *)(CONFIG_SYS_TEXT_BASE + offset);
+ else if (sysfw_load_address)
+ return sysfw_load_address;
+ else
+ panic("SYSFW load address not defined!");
+}
+
+/*
+ * Populate SPL hook to skip the default SPL loader FIT post-processing steps
+ * during SYSFW loading and return to the calling function so we can perform
+ * our own custom processing.
+ */
+bool spl_load_simple_fit_skip_processing(void)
+{
+ return !sysfw_loaded;
+}
+
+static int fit_get_data_by_name(const void *fit, int images, const char *name,
+ const void **addr, size_t *size)
+{
+ int node_offset;
+
+ node_offset = fdt_subnode_offset(fit, images, name);
+ if (node_offset < 0)
+ return -ENOENT;
+
+ return fit_image_get_data(fit, node_offset, addr, size);
+}
+
+static void k3_sysfw_load_using_fit(void *fit)
+{
+ int images;
+ const void *sysfw_addr;
+ size_t sysfw_size;
+ int ret;
+
+ /* Find the node holding the images information */
+ images = fdt_path_offset(fit, FIT_IMAGES_PATH);
+ if (images < 0)
+ panic("Cannot find /images node (%d)\n", images);
+
+ /* Extract System Firmware (SYSFW) image from FIT */
+ ret = fit_get_data_by_name(fit, images, SYSFW_FIRMWARE,
+ &sysfw_addr, &sysfw_size);
+ if (ret < 0)
+ panic("Error accessing %s node in FIT (%d)\n", SYSFW_FIRMWARE,
+ ret);
+
+ /*
+ * Start up system controller firmware
+ *
+ * It is assumed that remoteproc device 0 is the corresponding
+ * system-controller that runs SYSFW. Make sure DT reflects the same.
+ */
+ ret = rproc_dev_init(0);
+ if (ret)
+ panic("rproc failed to be initialized (%d)\n", ret);
+
+ ret = rproc_load(0, (ulong)sysfw_addr, (ulong)sysfw_size);
+ if (ret)
+ panic("Firmware failed to start on rproc (%d)\n", ret);
+
+ ret = rproc_start(0);
+ if (ret)
+ panic("Firmware init failed on rproc (%d)\n", ret);
+}
+
+static void k3_sysfw_configure_using_fit(void *fit,
+ struct ti_sci_handle *ti_sci)
+{
+ struct ti_sci_board_ops *board_ops = &ti_sci->ops.board_ops;
+ int images;
+ const void *cfg_fragment_addr;
+ size_t cfg_fragment_size;
+ int ret;
+
+ /* Find the node holding the images information */
+ images = fdt_path_offset(fit, FIT_IMAGES_PATH);
+ if (images < 0)
+ panic("Cannot find /images node (%d)\n", images);
+
+ /* Extract board configuration from FIT */
+ ret = fit_get_data_by_name(fit, images, SYSFW_CFG_BOARD,
+ &cfg_fragment_addr, &cfg_fragment_size);
+ if (ret < 0)
+ panic("Error accessing %s node in FIT (%d)\n", SYSFW_CFG_BOARD,
+ ret);
+
+ /* Apply board configuration to SYSFW */
+ ret = board_ops->board_config(ti_sci,
+ (u64)(u32)cfg_fragment_addr,
+ (u32)cfg_fragment_size);
+ if (ret)
+ panic("Failed to set board configuration (%d)\n", ret);
+
+ /* Extract power/clock (PM) specific configuration from FIT */
+ ret = fit_get_data_by_name(fit, images, SYSFW_CFG_PM,
+ &cfg_fragment_addr, &cfg_fragment_size);
+ if (ret < 0)
+ panic("Error accessing %s node in FIT (%d)\n", SYSFW_CFG_PM,
+ ret);
+
+ /* Apply power/clock (PM) specific configuration to SYSFW */
+ ret = board_ops->board_config_pm(ti_sci,
+ (u64)(u32)cfg_fragment_addr,
+ (u32)cfg_fragment_size);
+ if (ret)
+ panic("Failed to set board PM configuration (%d)\n", ret);
+
+ /* Extract resource management (RM) specific configuration from FIT */
+ ret = fit_get_data_by_name(fit, images, SYSFW_CFG_RM,
+ &cfg_fragment_addr, &cfg_fragment_size);
+ if (ret < 0)
+ panic("Error accessing %s node in FIT (%d)\n", SYSFW_CFG_RM,
+ ret);
+
+ /* Apply resource management (RM) configuration to SYSFW */
+ ret = board_ops->board_config_rm(ti_sci,
+ (u64)(u32)cfg_fragment_addr,
+ (u32)cfg_fragment_size);
+ if (ret)
+ panic("Failed to set board RM configuration (%d)\n", ret);
+
+ /* Extract security specific configuration from FIT */
+ ret = fit_get_data_by_name(fit, images, SYSFW_CFG_SEC,
+ &cfg_fragment_addr, &cfg_fragment_size);
+ if (ret < 0)
+ panic("Error accessing %s node in FIT (%d)\n", SYSFW_CFG_SEC,
+ ret);
+
+ /* Apply security configuration to SYSFW */
+ ret = board_ops->board_config_security(ti_sci,
+ (u64)(u32)cfg_fragment_addr,
+ (u32)cfg_fragment_size);
+ if (ret)
+ panic("Failed to set board security configuration (%d)\n",
+ ret);
+}
+
+void k3_sysfw_loader(void (*config_pm_done_callback)(void))
+{
+ struct spl_image_info spl_image = { 0 };
+ struct spl_boot_device bootdev = { 0 };
+ struct ti_sci_handle *ti_sci;
+ int ret;
+
+ /* Reserve a block of aligned memory for loading the SYSFW image */
+ sysfw_load_address = memalign(ARCH_DMA_MINALIGN,
+ CONFIG_K3_SYSFW_IMAGE_SIZE_MAX);
+ if (!sysfw_load_address)
+ panic("Error allocating %u bytes of memory for SYSFW image\n",
+ CONFIG_K3_SYSFW_IMAGE_SIZE_MAX);
+
+ debug("%s: allocated %u bytes at 0x%p\n", __func__,
+ CONFIG_K3_SYSFW_IMAGE_SIZE_MAX, sysfw_load_address);
+
+ /* Set load address for legacy modes that bypass spl_get_load_buffer */
+ spl_image.load_addr = (uintptr_t)sysfw_load_address;
+
+ bootdev.boot_device = spl_boot_device();
+
+ /* Load combined System Controller firmware and config data image */
+ switch (bootdev.boot_device) {
+#if CONFIG_IS_ENABLED(MMC_SUPPORT)
+ case BOOT_DEVICE_MMC1:
+ case BOOT_DEVICE_MMC2:
+ case BOOT_DEVICE_MMC2_2:
+ ret = spl_mmc_load(&spl_image, &bootdev,
+#ifdef CONFIG_K3_SYSFW_IMAGE_NAME
+ CONFIG_K3_SYSFW_IMAGE_NAME,
+#else
+ NULL,
+#endif
+#ifdef CONFIG_K3_SYSFW_IMAGE_MMCSD_RAW_MODE_PART
+ CONFIG_K3_SYSFW_IMAGE_MMCSD_RAW_MODE_PART,
+#else
+ 0,
+#endif
+#ifdef CONFIG_K3_SYSFW_IMAGE_MMCSD_RAW_MODE_SECT
+ CONFIG_K3_SYSFW_IMAGE_MMCSD_RAW_MODE_SECT);
+#else
+ 0);
+#endif
+ break;
+#endif
+ default:
+ panic("Loading SYSFW image from device %u not supported!\n",
+ bootdev.boot_device);
+ }
+
+ if (ret)
+ panic("Error %d occurred during loading SYSFW image!\n", ret);
+
+ /*
+ * Now that SYSFW got loaded set helper flag to restore regular SPL
+ * loader behavior so we can later boot into the next stage as expected.
+ */
+ sysfw_loaded = true;
+
+ /* Ensure the SYSFW image is in FIT format */
+ if (image_get_magic((const image_header_t *)sysfw_load_address) !=
+ FDT_MAGIC)
+ panic("SYSFW image not in FIT format!\n");
+
+ /* Extract and start SYSFW */
+ k3_sysfw_load_using_fit(sysfw_load_address);
+
+ /* Get handle for accessing SYSFW services */
+ ti_sci = get_ti_sci_handle();
+
+ /* Parse and apply the different SYSFW configuration fragments */
+ k3_sysfw_configure_using_fit(sysfw_load_address, ti_sci);
+
+ /*
+ * Now that all clocks and PM aspects are setup, invoke a user-
+ * provided callback function. Usually this callback would be used
+ * to setup or re-configure the U-Boot console UART.
+ */
+ if (config_pm_done_callback)
+ config_pm_done_callback();
+
+ /*
+ * Output System Firmware version info. Note that since the
+ * 'firmware_description' field is not guaranteed to be zero-
+ * terminated we manually add a \0 terminator if needed. Further
+ * note that we intentionally no longer rely on the extended
+ * printf() formatter '%.*s' to not having to require a more
+ * full-featured printf() implementation.
+ */
+ char fw_desc[sizeof(ti_sci->version.firmware_description) + 1];
+
+ strncpy(fw_desc, ti_sci->version.firmware_description,
+ sizeof(ti_sci->version.firmware_description));
+ fw_desc[sizeof(fw_desc) - 1] = '\0';
+
+ printf("SYSFW ABI: %d.%d (firmware rev 0x%04x '%s')\n",
+ ti_sci->version.abi_major, ti_sci->version.abi_minor,
+ ti_sci->version.firmware_revision, fw_desc);
+}
diff --git a/arch/arm/mach-keystone/mon.c b/arch/arm/mach-keystone/mon.c
index 51af028..cc2ec88 100644
--- a/arch/arm/mach-keystone/mon.c
+++ b/arch/arm/mach-keystone/mon.c
@@ -1,11 +1,11 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * K2HK: secure kernel command file
+ * K2x: Secure commands file
*
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, <www.ti.com>
+ * Copyright (C) 2012-2019 Texas Instruments Incorporated - http://www.ti.com/
*/
+#include <asm/unaligned.h>
#include <common.h>
#include <command.h>
#include <mach/mon.h>
@@ -120,9 +120,9 @@
/*
* Overwrite the image headers after authentication
* and decryption. Update size to reflect removal
- * of header.
+ * of header and restore original file size.
*/
- *p_size -= KS2_HS_SEC_HEADER_LEN;
+ *p_size = get_unaligned_le32(image + (*p_size - 4));
memcpy(image, image + KS2_HS_SEC_HEADER_LEN, *p_size);
/*
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 7c41703..2f68092 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -32,11 +32,8 @@
bool "iconnect Board"
config TARGET_KM_KIRKWOOD
- bool "KM_KIRKWOOD Board"
- select BOARD_LATE_INIT
- imply CMD_CRAMFS
- imply CMD_DIAG
- imply FS_CRAMFS
+ bool "KM Kirkwood Board"
+ select VENDOR_KM
config TARGET_NET2BIG_V2
bool "LaCie 2Big Network v2 NAS Board"
@@ -82,7 +79,7 @@
source "board/cloudengines/pogo_e02/Kconfig"
source "board/d-link/dns325/Kconfig"
source "board/iomega/iconnect/Kconfig"
-source "board/keymile/km_arm/Kconfig"
+source "board/keymile/Kconfig"
source "board/LaCie/net2big_v2/Kconfig"
source "board/LaCie/netspace_v2/Kconfig"
source "board/raidsonic/ib62x0/Kconfig"
diff --git a/arch/arm/mach-kirkwood/cpu.c b/arch/arm/mach-kirkwood/cpu.c
index 8f8e300..6ad2543 100644
--- a/arch/arm/mach-kirkwood/cpu.c
+++ b/arch/arm/mach-kirkwood/cpu.c
@@ -6,6 +6,7 @@
*/
#include <common.h>
+#include <env.h>
#include <netdev.h>
#include <asm/cache.h>
#include <asm/io.h>
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index 60aef15..25ef765 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -42,5 +42,6 @@
source "board/mediatek/mt7623/Kconfig"
source "board/mediatek/mt7629/Kconfig"
+source "board/mediatek/pumpkin/Kconfig"
endif
diff --git a/arch/arm/mach-mediatek/mt7629/lowlevel_init.S b/arch/arm/mach-mediatek/mt7629/lowlevel_init.S
index 3375796..0a0672c 100644
--- a/arch/arm/mach-mediatek/mt7629/lowlevel_init.S
+++ b/arch/arm/mach-mediatek/mt7629/lowlevel_init.S
@@ -4,6 +4,7 @@
*/
#include <linux/linkage.h>
+#include <asm/proc-armv/ptrace.h>
#define WAIT_CODE_SRAM_BASE 0x0010ff00
@@ -27,6 +28,18 @@
movt r0, #0x131
mcr p15, 0, r0, c14, c0, 0
+ cps #MON_MODE
+ mrc p15, 0, r1, c1, c1, 0 @ Get Secure Config
+ orr r0, r1, #1
+ mcr p15, 0, r0, c1, c1, 0 @ Set Non Secure bit
+ isb
+ mov r0, #0
+ mcrr p15, 4, r0, r0, c14 @ CNTVOFF = 0
+ isb
+ mcr p15, 0, r1, c1, c1, 0 @ Set Secure bit
+ isb
+ cps #SVC_MODE
+
/* enable SMP bit */
mrc p15, 0, r0, c1, c0, 1
orr r0, r0, #0x40
diff --git a/arch/arm/mach-meson/board-common.c b/arch/arm/mach-meson/board-common.c
index 8c41301..d261b4e 100644
--- a/arch/arm/mach-meson/board-common.c
+++ b/arch/arm/mach-meson/board-common.c
@@ -5,6 +5,7 @@
#include <common.h>
#include <asm/arch/boot.h>
+#include <env.h>
#include <linux/libfdt.h>
#include <linux/err.h>
#include <asm/arch/mem.h>
@@ -13,6 +14,11 @@
#include <asm/unaligned.h>
#include <efi_loader.h>
+#if CONFIG_IS_ENABLED(FASTBOOT)
+#include <asm/psci.h>
+#include <fastboot.h>
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
__weak int board_init(void)
@@ -67,6 +73,36 @@
}
}
+int meson_generate_serial_ethaddr(void)
+{
+ u8 mac_addr[ARP_HLEN];
+ char serial[SM_SERIAL_SIZE];
+ u32 sid;
+ u16 sid16;
+
+ if (!meson_sm_get_serial(serial, SM_SERIAL_SIZE)) {
+ sid = crc32(0, (unsigned char *)serial, SM_SERIAL_SIZE);
+ sid16 = crc16_ccitt(0, (unsigned char *)serial, SM_SERIAL_SIZE);
+
+ /* Ensure the NIC specific bytes of the mac are not all 0 */
+ if ((sid & 0xffffff) == 0)
+ sid |= 0x800000;
+
+ /* Non OUI / registered MAC address */
+ mac_addr[0] = ((sid16 >> 8) & 0xfc) | 0x02;
+ mac_addr[1] = (sid16 >> 0) & 0xff;
+ mac_addr[2] = (sid >> 24) & 0xff;
+ mac_addr[3] = (sid >> 16) & 0xff;
+ mac_addr[4] = (sid >> 8) & 0xff;
+ mac_addr[5] = (sid >> 0) & 0xff;
+
+ eth_env_set_enetaddr("ethaddr", mac_addr);
+ } else
+ return -EINVAL;
+
+ return 0;
+}
+
static void meson_set_boot_source(void)
{
const char *source;
@@ -111,7 +147,35 @@
return meson_board_late_init();
}
+#if CONFIG_IS_ENABLED(FASTBOOT)
+static unsigned int reboot_reason = REBOOT_REASON_NORMAL;
+
+int fastboot_set_reboot_flag()
+{
+ reboot_reason = REBOOT_REASON_BOOTLOADER;
+
+ printf("Using reboot reason: 0x%x\n", reboot_reason);
+
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+ struct pt_regs regs;
+
+ regs.regs[0] = ARM_PSCI_0_2_FN_SYSTEM_RESET;
+ regs.regs[1] = reboot_reason;
+
+ printf("Rebooting with reason: 0x%lx\n", regs.regs[1]);
+
+ smc_call(®s);
+
+ while (1)
+ ;
+}
+#else
void reset_cpu(ulong addr)
{
psci_system_reset();
}
+#endif
diff --git a/arch/arm/mach-meson/board-g12a.c b/arch/arm/mach-meson/board-g12a.c
index 1652970..546b9f6 100644
--- a/arch/arm/mach-meson/board-g12a.c
+++ b/arch/arm/mach-meson/board-g12a.c
@@ -62,21 +62,21 @@
phys_size_t get_effective_memsize(void)
{
/* Size is reported in MiB, convert it in bytes */
- return ((readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_MEM_SIZE_MASK)
- >> G12A_AO_MEM_SIZE_SHIFT) * SZ_1M;
+ return min(((readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_MEM_SIZE_MASK)
+ >> G12A_AO_MEM_SIZE_SHIFT) * SZ_1M, 0xf5000000);
}
static struct mm_region g12a_mem_map[] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
- .size = 0x80000000UL,
+ .size = 0xf5000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
- .virt = 0xf0000000UL,
- .phys = 0xf0000000UL,
- .size = 0x10000000UL,
+ .virt = 0xf5000000UL,
+ .phys = 0xf5000000UL,
+ .size = 0x0b000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
@@ -129,6 +129,7 @@
G12A_ETH_REG_0_TX_RATIO(4) |
G12A_ETH_REG_0_PHY_CLK_EN |
G12A_ETH_REG_0_CLK_EN);
+ g12a_enable_external_mdio();
break;
case PHY_INTERFACE_MODE_RMII:
diff --git a/arch/arm/mach-meson/sm.c b/arch/arm/mach-meson/sm.c
index a07b468..fabcb3b 100644
--- a/arch/arm/mach-meson/sm.c
+++ b/arch/arm/mach-meson/sm.c
@@ -6,12 +6,18 @@
*/
#include <common.h>
+#include <asm/arch/sm.h>
#include <linux/kernel.h>
+#include <dm.h>
+#include <linux/bitfield.h>
+#include <regmap.h>
+#include <syscon.h>
#define FN_GET_SHARE_MEM_INPUT_BASE 0x82000020
#define FN_GET_SHARE_MEM_OUTPUT_BASE 0x82000021
#define FN_EFUSE_READ 0x82000030
#define FN_EFUSE_WRITE 0x82000031
+#define FN_CHIP_ID 0x82000044
static void *shmem_input;
static void *shmem_output;
@@ -53,3 +59,154 @@
return regs.regs[0];
}
+
+#define SM_CHIP_ID_LENGTH 119
+#define SM_CHIP_ID_OFFSET 4
+#define SM_CHIP_ID_SIZE 12
+
+int meson_sm_get_serial(void *buffer, size_t size)
+{
+ struct pt_regs regs;
+
+ meson_init_shmem();
+
+ regs.regs[0] = FN_CHIP_ID;
+ regs.regs[1] = 0;
+ regs.regs[2] = 0;
+
+ smc_call(®s);
+
+ memcpy(buffer, shmem_output + SM_CHIP_ID_OFFSET,
+ min_t(size_t, size, SM_CHIP_ID_SIZE));
+
+ return 0;
+}
+
+#define AO_SEC_SD_CFG15 0xfc
+#define REBOOT_REASON_MASK GENMASK(15, 12)
+
+int meson_sm_get_reboot_reason(void)
+{
+ struct regmap *regmap;
+ int nodeoffset;
+ ofnode node;
+ unsigned int reason;
+
+ /* find the offset of compatible node */
+ nodeoffset = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
+ "amlogic,meson-gx-ao-secure");
+ if (nodeoffset < 0) {
+ printf("%s: failed to get amlogic,meson-gx-ao-secure\n",
+ __func__);
+ return -ENODEV;
+ }
+
+ /* get regmap from the syscon node */
+ node = offset_to_ofnode(nodeoffset);
+ regmap = syscon_node_to_regmap(node);
+ if (IS_ERR(regmap)) {
+ printf("%s: failed to get regmap\n", __func__);
+ return -EINVAL;
+ }
+
+ regmap_read(regmap, AO_SEC_SD_CFG15, &reason);
+
+ /* The SMC call is not used, we directly use AO_SEC_SD_CFG15 */
+ return FIELD_GET(REBOOT_REASON_MASK, reason);
+}
+
+static int do_sm_serial(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ ulong address;
+ int ret;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ address = simple_strtoul(argv[1], NULL, 0);
+
+ ret = meson_sm_get_serial((void *)address, SM_CHIP_ID_SIZE);
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ return CMD_RET_SUCCESS;
+}
+
+#define MAX_REBOOT_REASONS 14
+
+static const char *reboot_reasons[MAX_REBOOT_REASONS] = {
+ [REBOOT_REASON_COLD] = "cold_boot",
+ [REBOOT_REASON_NORMAL] = "normal",
+ [REBOOT_REASON_RECOVERY] = "recovery",
+ [REBOOT_REASON_UPDATE] = "update",
+ [REBOOT_REASON_FASTBOOT] = "fastboot",
+ [REBOOT_REASON_SUSPEND_OFF] = "suspend_off",
+ [REBOOT_REASON_HIBERNATE] = "hibernate",
+ [REBOOT_REASON_BOOTLOADER] = "bootloader",
+ [REBOOT_REASON_SHUTDOWN_REBOOT] = "shutdown_reboot",
+ [REBOOT_REASON_RPMBP] = "rpmbp",
+ [REBOOT_REASON_CRASH_DUMP] = "crash_dump",
+ [REBOOT_REASON_KERNEL_PANIC] = "kernel_panic",
+ [REBOOT_REASON_WATCHDOG_REBOOT] = "watchdog_reboot",
+};
+
+static int do_sm_reboot_reason(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ const char *reason_str;
+ char *destarg = NULL;
+ int reason;
+
+ if (argc > 1)
+ destarg = argv[1];
+
+ reason = meson_sm_get_reboot_reason();
+ if (reason < 0)
+ return CMD_RET_FAILURE;
+
+ if (reason >= MAX_REBOOT_REASONS ||
+ !reboot_reasons[reason])
+ reason_str = "unknown";
+ else
+ reason_str = reboot_reasons[reason];
+
+ if (destarg)
+ env_set(destarg, reason_str);
+ else
+ printf("reboot reason: %s (%x)\n", reason_str, reason);
+
+ return CMD_RET_SUCCESS;
+}
+
+static cmd_tbl_t cmd_sm_sub[] = {
+ U_BOOT_CMD_MKENT(serial, 2, 1, do_sm_serial, "", ""),
+ U_BOOT_CMD_MKENT(reboot_reason, 1, 1, do_sm_reboot_reason, "", ""),
+};
+
+static int do_sm(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ cmd_tbl_t *c;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ /* Strip off leading 'sm' command argument */
+ argc--;
+ argv++;
+
+ c = find_cmd_tbl(argv[0], &cmd_sm_sub[0], ARRAY_SIZE(cmd_sm_sub));
+
+ if (c)
+ return c->cmd(cmdtp, flag, argc, argv);
+ else
+ return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(
+ sm, 5, 0, do_sm,
+ "Secure Monitor Control",
+ "serial <address> - read chip unique id to memory address\n"
+ "sm reboot_reason [name] - get reboot reason and store to to environment"
+);
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 495c48e..fdd3968 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -239,6 +239,11 @@
bool "SDIO/MMC card"
select SPL_LIBDISK_SUPPORT
+config MVEBU_SPL_BOOT_DEVICE_SATA
+ bool "SATA"
+ select SPL_SATA_SUPPORT
+ select SPL_LIBDISK_SUPPORT
+
config MVEBU_SPL_BOOT_DEVICE_UART
bool "UART"
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index 02d3ce2..8228a17 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -37,6 +37,9 @@
ifneq ($(CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC),)
KWB_CFG_BOOT_FROM=sdio
endif
+ifneq ($(CONFIG_MVEBU_SPL_BOOT_DEVICE_SATA),)
+ KWB_CFG_BOOT_FROM=sata
+endif
ifneq ($(CONFIG_MVEBU_SPL_BOOT_DEVICE_UART),)
KWB_CFG_BOOT_FROM=uart
endif
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index f09e7b1..f4b7a4f 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -542,6 +542,10 @@
const struct mbus_dram_target_info *dram;
int i;
+ /* mbus is not initialized in SPL; keep the ROM settings */
+ if (IS_ENABLED(CONFIG_SPL_BUILD))
+ return;
+
dram = mvebu_mbus_dram_info();
for (i = 0; i < 4; i++) {
diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h
index e6140d6..2e2d72a 100644
--- a/arch/arm/mach-mvebu/include/mach/cpu.h
+++ b/arch/arm/mach-mvebu/include/mach/cpu.h
@@ -163,6 +163,13 @@
*/
int ddr3_init(void);
+/* Auto Voltage Scaling */
+#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
+void mv_avs_init(void);
+#else
+static inline void mv_avs_init(void) {}
+#endif
+
/*
* get_ref_clk
*
diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h
index f666ee2..acb9257 100644
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -159,7 +159,9 @@
#define BOOT_DEV_SEL_MASK (0x3f << BOOT_DEV_SEL_OFFS)
#define BOOT_FROM_NAND 0x0A
+#define BOOT_FROM_SATA 0x22
#define BOOT_FROM_UART 0x28
+#define BOOT_FROM_SATA_ALT 0x2A
#define BOOT_FROM_UART_ALT 0x3f
#define BOOT_FROM_SPI 0x32
#define BOOT_FROM_MMC 0x30
diff --git a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c
index d387893..e9dd096 100644
--- a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c
+++ b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c
@@ -256,3 +256,29 @@
value = reg_read(DEV_VERSION_ID_REG);
return (value & (REVISON_ID_MASK)) >> REVISON_ID_OFFS;
}
+
+void mv_avs_init(void)
+{
+ u32 sar_freq;
+
+ if (!(IS_ENABLED(CONFIG_ARMADA_38X) || IS_ENABLED(CONFIG_ARMADA_39X)))
+ return;
+
+ reg_write(AVS_DEBUG_CNTR_REG, AVS_DEBUG_CNTR_DEFAULT_VALUE);
+ reg_write(AVS_DEBUG_CNTR_REG, AVS_DEBUG_CNTR_DEFAULT_VALUE);
+
+ sar_freq = reg_read(DEVICE_SAMPLE_AT_RESET1_REG);
+ sar_freq = sar_freq >> SAR_FREQ_OFFSET & SAR_FREQ_MASK;
+
+ /* Set AVS value only for core frequency of 1600MHz or less.
+ * For higher frequency leave the default value.
+ */
+ if (sar_freq <= 0xd) {
+ u32 avs_reg_data = reg_read(AVS_ENABLED_CONTROL);
+
+ avs_reg_data &= ~(AVS_LOW_VDD_LIMIT_MASK
+ | AVS_HIGH_VDD_LIMIT_MASK);
+ avs_reg_data |= AVS_LOW_VDD_SLOW_VAL | AVS_HIGH_VDD_SLOW_VAL;
+ reg_write(AVS_ENABLED_CONTROL, avs_reg_data);
+ }
+}
diff --git a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h
index 365332d..1774a5b 100644
--- a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h
+++ b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h
@@ -33,6 +33,8 @@
#define DEV_ID_REG_DEVICE_ID_OFFS 16
#define DEV_ID_REG_DEVICE_ID_MASK 0xffff0000
+#define SAR_FREQ_OFFSET 10
+#define SAR_FREQ_MASK 0x1f
#define SAR_DEV_ID_OFFS 27
#define SAR_DEV_ID_MASK 0x7
@@ -155,10 +157,12 @@
#define AVS_LOW_VDD_LIMIT_OFFS 4
#define AVS_LOW_VDD_LIMIT_MASK (0xff << AVS_LOW_VDD_LIMIT_OFFS)
#define AVS_LOW_VDD_LIMIT_VAL (0x27 << AVS_LOW_VDD_LIMIT_OFFS)
+#define AVS_LOW_VDD_SLOW_VAL (0x23 << AVS_LOW_VDD_LIMIT_OFFS)
#define AVS_HIGH_VDD_LIMIT_OFFS 12
#define AVS_HIGH_VDD_LIMIT_MASK (0xff << AVS_HIGH_VDD_LIMIT_OFFS)
#define AVS_HIGH_VDD_LIMIT_VAL (0x27 << AVS_HIGH_VDD_LIMIT_OFFS)
+#define AVS_HIGH_VDD_SLOW_VAL (0x23 << AVS_HIGH_VDD_LIMIT_OFFS)
/* Board ID numbers */
#define MARVELL_BOARD_ID_MASK 0x10
diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c
index 530b98c1..3cb27b7 100644
--- a/arch/arm/mach-mvebu/spl.c
+++ b/arch/arm/mach-mvebu/spl.c
@@ -59,6 +59,11 @@
case BOOT_FROM_UART_ALT:
#endif
return BOOT_DEVICE_UART;
+#ifdef BOOT_FROM_SATA
+ case BOOT_FROM_SATA:
+ case BOOT_FROM_SATA_ALT:
+ return BOOT_DEVICE_SATA;
+#endif
case BOOT_FROM_SPI:
default:
return BOOT_DEVICE_SPI;
@@ -121,6 +126,9 @@
ddr3_init();
#endif
+ /* Initialize Auto Voltage Scaling */
+ mv_avs_init();
+
/*
* Return to the BootROM to continue the Marvell xmodem
* UART boot protocol. As initiated by the kwboot tool.
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index d29f1ca..ed8056e 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -11,7 +11,7 @@
select ARM_ERRATA_454179
select ARM_ERRATA_621766
select ARM_ERRATA_725233
- select USE_TINY_PRINTF
+ select USE_TINY_PRINTF if SPL
imply NAND_OMAP_GPMC
imply SPL_FS_EXT4
imply SPL_FS_FAT
@@ -176,6 +176,7 @@
source "arch/arm/mach-omap2/am33xx/Kconfig"
source "board/BuR/brxre1/Kconfig"
+source "board/BuR/brsmarc1/Kconfig"
source "board/BuR/brppt1/Kconfig"
source "board/siemens/draco/Kconfig"
source "board/siemens/pxm2/Kconfig"
@@ -186,6 +187,7 @@
source "board/ti/am335x/Kconfig"
source "board/compulab/cm_t335/Kconfig"
source "board/compulab/cm_t43/Kconfig"
+source "board/phytec/phycore_am335x_r2/Kconfig"
config SPL_LDSCRIPT
default "arch/arm/mach-omap2/u-boot-spl.lds"
diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig
index 500df1a..7f6b344 100644
--- a/arch/arm/mach-omap2/am33xx/Kconfig
+++ b/arch/arm/mach-omap2/am33xx/Kconfig
@@ -121,6 +121,10 @@
bool "Support BRXRE1"
select BOARD_LATE_INIT
+config TARGET_BRSMARC1
+ bool "Support BRSMARC1"
+ select BOARD_LATE_INIT
+
config TARGET_BRPPT1
bool "Support BRPPT1"
select BOARD_LATE_INIT
@@ -177,6 +181,13 @@
select DM_SERIAL
imply CMD_DM
+config TARGET_PHYCORE_AM335X_R2
+ bool "Support phyCORE AM335X R2"
+ select DM
+ select DM_GPIO
+ select DM_SERIAL
+ imply CMD_DM
+
config TARGET_PXM2
bool "Support pxm2"
select BOARD_LATE_INIT
diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c
index 5507348..03460c3 100644
--- a/arch/arm/mach-omap2/am33xx/board.c
+++ b/arch/arm/mach-omap2/am33xx/board.c
@@ -375,8 +375,8 @@
*/
int board_early_init_f(void)
{
- prcm_init();
set_mux_conf_regs();
+ prcm_init();
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
update_rtc_magic();
#endif
diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c
index c8b8ac6..734fa9d 100644
--- a/arch/arm/mach-omap2/boot-common.c
+++ b/arch/arm/mach-omap2/boot-common.c
@@ -9,7 +9,6 @@
#include <common.h>
#include <ahci.h>
-#include <environment.h>
#include <spl.h>
#include <asm/omap_common.h>
#include <asm/arch/omap.h>
@@ -208,7 +207,7 @@
#if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT)
arch_misc_init();
#endif
-#if defined(CONFIG_HW_WATCHDOG)
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
hw_watchdog_init();
#endif
#ifdef CONFIG_AM33XX
diff --git a/arch/arm/mach-omap2/omap3/clock.c b/arch/arm/mach-omap2/omap3/clock.c
index cb9e91e..71f7349 100644
--- a/arch/arm/mach-omap2/omap3/clock.c
+++ b/arch/arm/mach-omap2/omap3/clock.c
@@ -17,7 +17,6 @@
#include <asm/arch/clocks_omap3.h>
#include <asm/arch/mem.h>
#include <asm/arch/sys_proto.h>
-#include <environment.h>
#include <command.h>
/******************************************************************************
diff --git a/arch/arm/mach-omap2/omap3/emac.c b/arch/arm/mach-omap2/omap3/emac.c
index c79e870..fb0c918 100644
--- a/arch/arm/mach-omap2/omap3/emac.c
+++ b/arch/arm/mach-omap2/omap3/emac.c
@@ -7,7 +7,6 @@
*/
#include <common.h>
-#include <netdev.h>
#include <asm/io.h>
#include <asm/arch/am35x_def.h>
@@ -24,5 +23,5 @@
reset &= ~CPGMACSS_SW_RST;
writel(reset, &am35x_scm_general_regs->ip_sw_reset);
- return davinci_emac_initialize();
+ return 0;
}
diff --git a/arch/arm/mach-omap2/omap5/fdt.c b/arch/arm/mach-omap2/omap5/fdt.c
index 3626d79..8dee555 100644
--- a/arch/arm/mach-omap2/omap5/fdt.c
+++ b/arch/arm/mach-omap2/omap5/fdt.c
@@ -201,7 +201,9 @@
int offs, node_offs, ret, i;
uint32_t phandle;
- offs = fdt_path_offset(fdt, "/ocp/l4@4a000000/cm_core_aon@5000/clocks");
+ offs = fdt_path_offset(fdt, "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks");
+ if (offs < 0)
+ offs = fdt_path_offset(fdt, "/ocp/l4@4a000000/cm_core_aon@5000/clocks");
if (offs < 0) {
debug("Could not find cm_core_aon clocks node path offset : %s\n",
fdt_strerror(offs));
diff --git a/arch/arm/mach-omap2/utils.c b/arch/arm/mach-omap2/utils.c
index edf5edc..0d5ca20 100644
--- a/arch/arm/mach-omap2/utils.c
+++ b/arch/arm/mach-omap2/utils.c
@@ -4,7 +4,7 @@
* Aneesh V <aneesh@ti.com>
*/
#include <common.h>
-#include <environment.h>
+#include <env.h>
#include <asm/setup.h>
#include <asm/arch/sys_proto.h>
#include <asm/omap_common.h>
@@ -129,12 +129,25 @@
{
}
#endif /* CONFIG_FASTBOOT_FLASH_MMC */
+
+static void omap_set_fastboot_product(void)
+{
+ const char *board_name;
+
+ board_name = env_get("board_name");
+ if (board_name == NULL)
+ printf("Warning: fastboot.product: unknown board\n");
+
+ env_set("fastboot.product", board_name);
+}
+
void omap_set_fastboot_vars(void)
{
omap_set_fastboot_cpu();
omap_set_fastboot_secure();
omap_set_fastboot_board_rev();
omap_set_fastboot_userdata_size();
+ omap_set_fastboot_product();
}
#endif /* CONFIG_FASTBOOT_FLASH */
diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig
index aafeb35..52ab891 100644
--- a/arch/arm/mach-rmobile/Kconfig
+++ b/arch/arm/mach-rmobile/Kconfig
@@ -21,6 +21,7 @@
imply CMD_GPT
imply CMD_UUID
imply CMD_MMC_SWRITE if MMC
+ imply OF_BOARD_SETUP if PCI
imply SUPPORT_EMMC_RPMB if MMC
imply SPL
imply SPL_BOARD_INIT
diff --git a/arch/arm/mach-rmobile/Kconfig.32 b/arch/arm/mach-rmobile/Kconfig.32
index 67f669a..1441c80 100644
--- a/arch/arm/mach-rmobile/Kconfig.32
+++ b/arch/arm/mach-rmobile/Kconfig.32
@@ -57,7 +57,6 @@
bool "Blanche board"
select DM
select DM_SERIAL
- select USE_TINY_PRINTF
imply CMD_DM
config TARGET_GOSE
diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
index 27d29f7..c8f93c6 100644
--- a/arch/arm/mach-rmobile/Kconfig.64
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -22,6 +22,11 @@
imply CLK_R8A77970
imply PINCTRL_PFC_R8A77970
+config R8A77980
+ bool "Renesas SoC R8A77980"
+ imply CLK_R8A77980
+ imply PINCTRL_PFC_R8A77980
+
config R8A77990
bool "Renesas SoC R8A77990"
imply CLK_R8A77990
@@ -38,6 +43,12 @@
prompt "Renesas ARM64 SoCs board select"
optional
+config TARGET_CONDOR
+ bool "Condor board"
+ imply R8A77980
+ help
+ Support for Renesas R-Car Gen3 Condor platform
+
config TARGET_DRAAK
bool "Draak board"
imply R8A77995
@@ -83,6 +94,7 @@
config SYS_SOC
default "rmobile"
+source "board/renesas/condor/Kconfig"
source "board/renesas/draak/Kconfig"
source "board/renesas/eagle/Kconfig"
source "board/renesas/ebisu/Kconfig"
diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c
index 784a2a2..9ef94a4 100644
--- a/arch/arm/mach-rmobile/cpu_info.c
+++ b/arch/arm/mach-rmobile/cpu_info.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
#include <asm/io.h>
+#include <env.h>
#include <linux/ctype.h>
#ifdef CONFIG_ARCH_CPU_INIT
@@ -64,6 +65,7 @@
{ RMOBILE_CPU_TYPE_R8A7796, "R8A7796" },
{ RMOBILE_CPU_TYPE_R8A77965, "R8A77965" },
{ RMOBILE_CPU_TYPE_R8A77970, "R8A77970" },
+ { RMOBILE_CPU_TYPE_R8A77980, "R8A77980" },
{ RMOBILE_CPU_TYPE_R8A77990, "R8A77990" },
{ RMOBILE_CPU_TYPE_R8A77995, "R8A77995" },
{ 0x0, "CPU" },
diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h b/arch/arm/mach-rmobile/include/mach/rmobile.h
index aa8d43e..a50249d 100644
--- a/arch/arm/mach-rmobile/include/mach/rmobile.h
+++ b/arch/arm/mach-rmobile/include/mach/rmobile.h
@@ -36,6 +36,7 @@
#define RMOBILE_CPU_TYPE_R8A7796 0x52
#define RMOBILE_CPU_TYPE_R8A77965 0x55
#define RMOBILE_CPU_TYPE_R8A77970 0x54
+#define RMOBILE_CPU_TYPE_R8A77980 0x56
#define RMOBILE_CPU_TYPE_R8A77990 0x57
#define RMOBILE_CPU_TYPE_R8A77995 0x58
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 1090d21..f5a80b4 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -7,6 +7,7 @@
select SPL
imply USB_FUNCTION_ROCKUSB
imply CMD_ROCKUSB
+ imply ROCKCHIP_COMMON_BOARD
help
The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
including NEON and GPU, Mali-400 graphics, several DDR3 options
@@ -16,6 +17,7 @@
config ROCKCHIP_RK3128
bool "Support Rockchip RK3128"
select CPU_V7A
+ imply ROCKCHIP_COMMON_BOARD
help
The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
including NEON and GPU, Mali-400 graphics, several DDR3 options
@@ -34,8 +36,10 @@
select SPL_RAM
select SPL_DRIVERS_MISC_SUPPORT
select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
+ select SPL_ROCKCHIP_BACK_TO_BROM
select BOARD_LATE_INIT
- select ROCKCHIP_BROM_HELPER
+ imply ROCKCHIP_COMMON_BOARD
+ imply SPL_ROCKCHIP_COMMON_BOARD
help
The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
@@ -57,9 +61,11 @@
select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
select TPL_NEEDS_SEPARATE_STACK if TPL
select SPL_DRIVERS_MISC_SUPPORT
+ imply ROCKCHIP_COMMON_BOARD
imply SPL_SERIAL_SUPPORT
+ imply SPL_ROCKCHIP_COMMON_BOARD
imply TPL_SERIAL_SUPPORT
- select ROCKCHIP_BROM_HELPER
+ imply TPL_ROCKCHIP_COMMON_BOARD
select TPL_LIBCOMMON_SUPPORT
select TPL_LIBGENERIC_SUPPORT
help
@@ -68,27 +74,14 @@
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
-if ROCKCHIP_RK322X
-
-config TPL_TEXT_BASE
- default 0x10081000
-
-config TPL_MAX_SIZE
- default 28672
-
-config TPL_STACK
- default 0x10088000
-
-endif
-
config ROCKCHIP_RK3288
bool "Support Rockchip RK3288"
select CPU_V7A
- select SPL_BOARD_INIT if SPL
select SUPPORT_SPL
select SPL
select SUPPORT_TPL
- imply TPL_BOOTROM_SUPPORT
+ imply ROCKCHIP_COMMON_BOARD
+ imply SPL_ROCKCHIP_COMMON_BOARD
imply TPL_CLK
imply TPL_DM
imply TPL_DRIVERS_MISC_SUPPORT
@@ -100,6 +93,7 @@
imply TPL_OF_PLATDATA
imply TPL_RAM
imply TPL_REGMAP
+ imply TPL_ROCKCHIP_COMMON_BOARD
imply TPL_SERIAL_SUPPORT
imply TPL_SYSCON
imply USB_FUNCTION_ROCKUSB
@@ -111,25 +105,19 @@
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
-if ROCKCHIP_RK3288
-
-config TPL_TEXT_BASE
- default 0xff704000
-
-config TPL_MAX_SIZE
- default 32768
-
-config TPL_STACK
- default 0xff718000
-
-endif
-
config ROCKCHIP_RK3328
bool "Support Rockchip RK3328"
select ARM64
select SUPPORT_SPL
select SPL
+ select SUPPORT_TPL
+ select TPL
+ select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL
+ select TPL_NEEDS_SEPARATE_STACK if TPL
+ imply ROCKCHIP_COMMON_BOARD
+ imply SPL_ROCKCHIP_COMMON_BOARD
imply SPL_SERIAL_SUPPORT
+ imply TPL_SERIAL_SUPPORT
imply SPL_SEPARATE_BSS
select ENABLE_ARM_SOC_BOOT0_HOOK
select DEBUG_UART_BOARD_INIT
@@ -148,9 +136,12 @@
select SUPPORT_TPL
select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
select TPL_NEEDS_SEPARATE_STACK if TPL
+ imply ROCKCHIP_COMMON_BOARD
+ imply SPL_ROCKCHIP_COMMON_BOARD
imply SPL_SEPARATE_BSS
imply SPL_SERIAL_SUPPORT
imply TPL_SERIAL_SUPPORT
+ imply TPL_ROCKCHIP_COMMON_BOARD
help
The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
into a big and little cluster with 4 cores each) Cortex-A53 including
@@ -162,19 +153,6 @@
On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
I2S, UARTs, SPI, I2C and PWMs.
-if ROCKCHIP_RK3368
-
-config TPL_TEXT_BASE
- default 0xff8c1000
-
-config TPL_MAX_SIZE
- default 28672
-
-config TPL_STACK
- default 0xff8cffff
-
-endif
-
config ROCKCHIP_RK3399
bool "Support Rockchip RK3399"
select ARM64
@@ -204,13 +182,12 @@
select DM_PMIC
select DM_REGULATOR_FIXED
select BOARD_LATE_INIT
- select ROCKCHIP_BROM_HELPER
+ imply ROCKCHIP_COMMON_BOARD
+ imply SPL_ROCKCHIP_COMMON_BOARD
imply TPL_SERIAL_SUPPORT
imply TPL_LIBCOMMON_SUPPORT
imply TPL_LIBGENERIC_SUPPORT
imply TPL_SYS_MALLOC_SIMPLE
- imply TPL_BOARD_INIT
- imply TPL_BOOTROM_SUPPORT
imply TPL_DRIVERS_MISC_SUPPORT
imply TPL_OF_CONTROL
imply TPL_DM
@@ -219,6 +196,7 @@
imply TPL_RAM
imply TPL_CLK
imply TPL_TINY_MEMSET
+ imply TPL_ROCKCHIP_COMMON_BOARD
help
The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
and quad-core Cortex-A53.
@@ -227,25 +205,10 @@
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
-if ROCKCHIP_RK3399
-
-config TPL_LDSCRIPT
- default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
-
-config TPL_TEXT_BASE
- default 0xff8c2000
-
-config TPL_MAX_SIZE
- default 188416
-
-config TPL_STACK
- default 0xff8effff
-
-endif
-
config ROCKCHIP_RV1108
bool "Support Rockchip RV1108"
select CPU_V7A
+ imply ROCKCHIP_COMMON_BOARD
help
The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
and a DSP.
@@ -262,6 +225,7 @@
bool "SPL returns to bootrom"
default y if ROCKCHIP_RK3036
select ROCKCHIP_BROM_HELPER
+ select SPL_BOOTROM_SUPPORT
depends on SPL
help
Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
@@ -272,22 +236,39 @@
bool "TPL returns to bootrom"
default y
select ROCKCHIP_BROM_HELPER
+ select TPL_BOOTROM_SUPPORT
depends on TPL
help
Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
SPL will return to the boot rom, which will then load the U-Boot
binary to keep going on.
+config ROCKCHIP_COMMON_BOARD
+ bool "Rockchip common board file"
+ help
+ Rockchip SoCs have similar boot process, Common board file is mainly
+ in charge of common process of board_init() and board_late_init() for
+ U-Boot proper.
+
+config SPL_ROCKCHIP_COMMON_BOARD
+ bool "Rockchip SPL common board file"
+ depends on SPL
+ help
+ Rockchip SoCs have similar boot process, SPL is mainly in charge of
+ load and boot Trust ATF/U-Boot firmware, and DRAM init if there is
+ no TPL for the board.
+
+config TPL_ROCKCHIP_COMMON_BOARD
+ bool ""
+ depends on TPL
+ help
+ Rockchip SoCs have similar boot process, prefer to use TPL for DRAM
+ init and back to bootrom, and SPL as Trust ATF/U-Boot loader. TPL
+ common board is a basic TPL board init which can be shared for most
+ of SoCs to avoid copy-pase for different SoCs.
+
config ROCKCHIP_BOOT_MODE_REG
hex "Rockchip boot mode flag register address"
- default 0x200081c8 if ROCKCHIP_RK3036
- default 0x20004040 if ROCKCHIP_RK3188
- default 0x110005c8 if ROCKCHIP_RK322X
- default 0xff730094 if ROCKCHIP_RK3288
- default 0xff738200 if ROCKCHIP_RK3368
- default 0xff320300 if ROCKCHIP_RK3399
- default 0x10300580 if ROCKCHIP_RV1108
- default 0
help
The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h)
according to the value from this register.
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 23760a9..45d9b06 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -1,26 +1,18 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (c) 2014 Google, Inc
+# Copyright (c) 2019 Rockchip Electronics Co., Ltd.
# We don't want the bootrom-helper present in a full U-Boot build, as
# this may have entered from ATF with the stack-pointer pointing to
# inaccessible/protected memory (and the bootrom-helper assumes that
# the stack-pointer is valid before switching to the U-Boot stack).
obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
+obj-spl-$(CONFIG_SPL_ROCKCHIP_COMMON_BOARD) += spl.o spl-boot-order.o
obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
-
-obj-tpl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-tpl.o
-obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o
-obj-tpl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-tpl.o
-obj-tpl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-tpl.o
+obj-tpl-$(CONFIG_TPL_ROCKCHIP_COMMON_BOARD) += tpl.o
obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
-obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
-obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o spl-boot-order.o
-obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
-obj-spl-$(CONFIG_ROCKCHIP_RK3328) += rk3328-board-spl.o
-obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o spl-boot-order.o
-obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o
ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
@@ -29,29 +21,15 @@
# we can have the preprocessor correctly recognise both 0x0 and 0
# meaning "turn it off".
obj-y += boot_mode.o
-
-obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o
-obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128-board.o
-obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o
-obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o
-obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o
-obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board.o
-obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108-board.o
+obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o
+obj-$(CONFIG_MISC_INIT_R) += misc.o
endif
obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o
-ifndef CONFIG_ARM64
-ifndef CONFIG_ROCKCHIP_RK3188
-obj-y += rk_timer.o
-endif
-endif
-
obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/
-ifndef CONFIG_TPL_BUILD
obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/
-endif
obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x/
obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
new file mode 100644
index 0000000..8ca3463
--- /dev/null
+++ b/arch/arm/mach-rockchip/board.c
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd.
+ */
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <ram.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/boot_mode.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/periph.h>
+#include <asm/arch-rockchip/misc.h>
+#include <power/regulator.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+__weak int rk_board_late_init(void)
+{
+ return 0;
+}
+
+int board_late_init(void)
+{
+ setup_boot_mode();
+
+ return rk_board_late_init();
+}
+
+int board_init(void)
+{
+ int ret;
+
+#ifdef CONFIG_DM_REGULATOR
+ ret = regulators_enable_boot_on(false);
+ if (ret)
+ debug("%s: Cannot enable boot on regulator\n", __func__);
+#endif
+
+ return 0;
+}
+
+#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
+void enable_caches(void)
+{
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+}
+#endif
+
+#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
+#include <usb.h>
+#include <usb/dwc2_udc.h>
+
+static struct dwc2_plat_otg_data otg_data = {
+ .rx_fifo_sz = 512,
+ .np_tx_fifo_sz = 16,
+ .tx_fifo_sz = 128,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ int node;
+ const char *mode;
+ bool matched = false;
+ const void *blob = gd->fdt_blob;
+
+ /* find the usb_otg node */
+ node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2");
+
+ while (node > 0) {
+ mode = fdt_getprop(blob, node, "dr_mode", NULL);
+ if (mode && strcmp(mode, "otg") == 0) {
+ matched = true;
+ break;
+ }
+
+ node = fdt_node_offset_by_compatible(blob, node, "snps,dwc2");
+ }
+ if (!matched) {
+ debug("Not found usb_otg device\n");
+ return -ENODEV;
+ }
+ otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
+
+ return dwc2_udc_probe(&otg_data);
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ return 0;
+}
+#endif
+
+#if CONFIG_IS_ENABLED(FASTBOOT)
+int fastboot_set_reboot_flag(void)
+{
+ printf("Setting reboot to fastboot flag ...\n");
+ /* Set boot mode to fastboot */
+ writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_MISC_INIT_R
+__weak int misc_init_r(void)
+{
+ const u32 cpuid_offset = 0x7;
+ const u32 cpuid_length = 0x10;
+ u8 cpuid[cpuid_length];
+ int ret;
+
+ ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
+ if (ret)
+ return ret;
+
+ ret = rockchip_cpuid_set(cpuid, cpuid_length);
+ if (ret)
+ return ret;
+
+ ret = rockchip_setup_macaddr();
+
+ return ret;
+}
+#endif
diff --git a/arch/arm/mach-rockchip/fit_spl_optee.its b/arch/arm/mach-rockchip/fit_spl_optee.its
index 9be4b3c..6ed5d48 100644
--- a/arch/arm/mach-rockchip/fit_spl_optee.its
+++ b/arch/arm/mach-rockchip/fit_spl_optee.its
@@ -11,7 +11,7 @@
#address-cells = <1>;
images {
- uboot@1 {
+ uboot {
description = "U-Boot";
data = /incbin/("../../../u-boot-nodtb.bin");
type = "standalone";
@@ -20,7 +20,7 @@
compression = "none";
load = <0x61000000>;
};
- optee@1 {
+ optee {
description = "OP-TEE";
data = /incbin/("../../../tee.bin");
type = "firmware";
@@ -30,7 +30,7 @@
load = <0x68400000>;
entry = <0x68400000>;
};
- fdt@1 {
+ fdt {
description = "dtb";
data = /incbin/("../../../u-boot.dtb");
type = "flat_dt";
@@ -39,12 +39,12 @@
};
configurations {
- default = "conf@1";
- conf@1 {
+ default = "conf";
+ conf {
description = "Rockchip armv7 with OP-TEE";
- firmware = "optee@1";
- loadables = "uboot@1";
- fdt = "fdt@1";
+ firmware = "optee";
+ loadables = "uboot";
+ fdt = "fdt";
};
};
};
diff --git a/arch/arm/mach-rockchip/make_fit_atf.py b/arch/arm/mach-rockchip/make_fit_atf.py
index db0ae96..585edcf 100755
--- a/arch/arm/mach-rockchip/make_fit_atf.py
+++ b/arch/arm/mach-rockchip/make_fit_atf.py
@@ -13,16 +13,7 @@
import sys
import getopt
import logging
-
-# pip install pyelftools
-from elftools.elf.elffile import ELFFile
-
-ELF_SEG_P_TYPE = 'p_type'
-ELF_SEG_P_PADDR = 'p_paddr'
-ELF_SEG_P_VADDR = 'p_vaddr'
-ELF_SEG_P_OFFSET = 'p_offset'
-ELF_SEG_P_FILESZ = 'p_filesz'
-ELF_SEG_P_MEMSZ = 'p_memsz'
+import struct
DT_HEADER = """
/*
@@ -91,7 +82,7 @@
file.write('\t\t\tdescription = "%s";\n' % dtname)
file.write('\t\t\tfirmware = "atf_1";\n')
file.write('\t\t\tloadables = "uboot"')
- if segments != 0:
+ if segments > 1:
file.write(',')
for i in range(1, segments):
file.write('"atf_%d"' % (i + 1))
@@ -99,7 +90,7 @@
file.write(',')
else:
file.write(';\n')
- if segments == 0:
+ if segments <= 1:
file.write(';\n')
file.write('\t\t\tfdt = "fdt_1";\n')
file.write('\t\t};\n')
@@ -118,33 +109,19 @@
file.write('\n')
def generate_atf_fit_dts_uboot(fit_file, uboot_file_name):
- num_load_seg = 0
- p_paddr = 0xFFFFFFFF
- with open(uboot_file_name, 'rb') as uboot_file:
- uboot = ELFFile(uboot_file)
- for i in range(uboot.num_segments()):
- seg = uboot.get_segment(i)
- if seg.__getitem__(ELF_SEG_P_TYPE) == 'PT_LOAD':
- p_paddr = seg.__getitem__(ELF_SEG_P_PADDR)
- num_load_seg = num_load_seg + 1
-
- assert (p_paddr != 0xFFFFFFFF and num_load_seg == 1)
-
+ segments = unpack_elf(uboot_file_name)
+ if len(segments) != 1:
+ raise ValueError("Invalid u-boot ELF image '%s'" % uboot_file_name)
+ index, entry, p_paddr, data = segments[0]
fit_file.write(DT_UBOOT % p_paddr)
def generate_atf_fit_dts_bl31(fit_file, bl31_file_name, dtbs_file_name):
- with open(bl31_file_name, 'rb') as bl31_file:
- bl31 = ELFFile(bl31_file)
- elf_entry = bl31.header['e_entry']
- segments = bl31.num_segments()
- for i in range(segments):
- seg = bl31.get_segment(i)
- if seg.__getitem__(ELF_SEG_P_TYPE) == 'PT_LOAD':
- paddr = seg.__getitem__(ELF_SEG_P_PADDR)
- append_bl31_node(fit_file, i + 1, paddr, elf_entry)
+ segments = unpack_elf(bl31_file_name)
+ for index, entry, paddr, data in segments:
+ append_bl31_node(fit_file, index + 1, paddr, entry)
append_fdt_node(fit_file, dtbs_file_name)
fit_file.write(DT_IMAGES_NODE_END)
- append_conf_node(fit_file, dtbs_file_name, segments)
+ append_conf_node(fit_file, dtbs_file_name, len(segments))
def generate_atf_fit_dts(fit_file_name, bl31_file_name, uboot_file_name, dtbs_file_name):
# Generate FIT script for ATF image.
@@ -162,17 +139,29 @@
fit_file.close()
def generate_atf_binary(bl31_file_name):
- with open(bl31_file_name, 'rb') as bl31_file:
- bl31 = ELFFile(bl31_file)
+ for index, entry, paddr, data in unpack_elf(bl31_file_name):
+ file_name = 'bl31_0x%08x.bin' % paddr
+ with open(file_name, "wb") as atf:
+ atf.write(data)
- num = bl31.num_segments()
- for i in range(num):
- seg = bl31.get_segment(i)
- if seg.__getitem__(ELF_SEG_P_TYPE) == 'PT_LOAD':
- paddr = seg.__getitem__(ELF_SEG_P_PADDR)
- file_name = 'bl31_0x%08x.bin' % paddr
- with open(file_name, "wb") as atf:
- atf.write(seg.data())
+def unpack_elf(filename):
+ with open(filename, 'rb') as file:
+ elf = file.read()
+ if elf[0:7] != b'\x7fELF\x02\x01\x01' or elf[18:20] != b'\xb7\x00':
+ raise ValueError("Invalid arm64 ELF file '%s'" % filename)
+
+ e_entry, e_phoff = struct.unpack_from('<2Q', elf, 0x18)
+ e_phentsize, e_phnum = struct.unpack_from('<2H', elf, 0x36)
+ segments = []
+
+ for index in range(e_phnum):
+ offset = e_phoff + e_phentsize * index
+ p_type, p_flags, p_offset = struct.unpack_from('<LLQ', elf, offset)
+ if p_type == 1: # PT_LOAD
+ p_paddr, p_filesz = struct.unpack_from('<2Q', elf, offset + 0x18)
+ p_data = elf[p_offset:p_offset + p_filesz]
+ segments.append((index, e_entry, p_paddr, p_data))
+ return segments
def main():
uboot_elf = "./u-boot"
diff --git a/arch/arm/mach-rockchip/misc.c b/arch/arm/mach-rockchip/misc.c
new file mode 100644
index 0000000..c0e4fdb
--- /dev/null
+++ b/arch/arm/mach-rockchip/misc.c
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * RK3399: Architecture common definitions
+ *
+ * Copyright (C) 2019 Collabora Inc - https://www.collabora.com/
+ * Rohan Garg <rohan.garg@collabora.com>
+ *
+ * Based on puma-rk3399.c:
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ */
+
+#include <common.h>
+#include <env.h>
+#include <dm.h>
+#include <dm/uclass-internal.h>
+#include <misc.h>
+#include <u-boot/sha256.h>
+
+#include <asm/arch-rockchip/misc.h>
+
+int rockchip_setup_macaddr(void)
+{
+#if CONFIG_IS_ENABLED(CMD_NET)
+ int ret;
+ const char *cpuid = env_get("cpuid#");
+ u8 hash[SHA256_SUM_LEN];
+ int size = sizeof(hash);
+ u8 mac_addr[6];
+
+ /* Only generate a MAC address, if none is set in the environment */
+ if (env_get("ethaddr"))
+ return -1;
+
+ if (!cpuid) {
+ debug("%s: could not retrieve 'cpuid#'\n", __func__);
+ return -1;
+ }
+
+ ret = hash_block("sha256", (void *)cpuid, strlen(cpuid), hash, &size);
+ if (ret) {
+ debug("%s: failed to calculate SHA256\n", __func__);
+ return -1;
+ }
+
+ /* Copy 6 bytes of the hash to base the MAC address on */
+ memcpy(mac_addr, hash, 6);
+
+ /* Make this a valid MAC address and set it */
+ mac_addr[0] &= 0xfe; /* clear multicast bit */
+ mac_addr[0] |= 0x02; /* set local assignment bit (IEEE802) */
+ eth_env_set_enetaddr("ethaddr", mac_addr);
+#endif
+ return 0;
+}
+
+int rockchip_cpuid_from_efuse(const u32 cpuid_offset,
+ const u32 cpuid_length,
+ u8 *cpuid)
+{
+#if CONFIG_IS_ENABLED(ROCKCHIP_EFUSE)
+ struct udevice *dev;
+ int ret;
+
+ /* retrieve the device */
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_GET_DRIVER(rockchip_efuse), &dev);
+ if (ret) {
+ debug("%s: could not find efuse device\n", __func__);
+ return -1;
+ }
+
+ /* read the cpu_id range from the efuses */
+ ret = misc_read(dev, cpuid_offset, cpuid, cpuid_length);
+ if (ret) {
+ debug("%s: reading cpuid from the efuses failed\n",
+ __func__);
+ return -1;
+ }
+#endif
+ return 0;
+}
+
+int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length)
+{
+ u8 low[cpuid_length / 2], high[cpuid_length / 2];
+ char cpuid_str[cpuid_length * 2 + 1];
+ u64 serialno;
+ char serialno_str[17];
+ int i;
+
+ memset(cpuid_str, 0, sizeof(cpuid_str));
+ for (i = 0; i < 16; i++)
+ sprintf(&cpuid_str[i * 2], "%02x", cpuid[i]);
+
+ debug("cpuid: %s\n", cpuid_str);
+
+ /*
+ * Mix the cpuid bytes using the same rules as in
+ * ${linux}/drivers/soc/rockchip/rockchip-cpuinfo.c
+ */
+ for (i = 0; i < 8; i++) {
+ low[i] = cpuid[1 + (i << 1)];
+ high[i] = cpuid[i << 1];
+ }
+
+ serialno = crc32_no_comp(0, low, 8);
+ serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32;
+ snprintf(serialno_str, sizeof(serialno_str), "%016llx", serialno);
+
+ env_set("cpuid#", cpuid_str);
+ env_set("serial#", serialno_str);
+
+ return 0;
+}
diff --git a/arch/arm/mach-rockchip/rk3036-board-spl.c b/arch/arm/mach-rockchip/rk3036-board-spl.c
index 110d06d..fbc89b6 100644
--- a/arch/arm/mach-rockchip/rk3036-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3036-board-spl.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2015-2019 Rockchip Electronics Co., Ltd
*/
#include <common.h>
@@ -8,14 +8,37 @@
#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/sdram_rk3036.h>
-#include <asm/arch-rockchip/timer.h>
+
+#define TIMER_LOAD_COUNT_L 0x00
+#define TIMER_LOAD_COUNT_H 0x04
+#define TIMER_CONTROL_REG 0x10
+#define TIMER_EN 0x1
+#define TIMER_FMODE (0 << 1)
+#define TIMER_RMODE (1 << 1)
+
+void rockchip_stimer_init(void)
+{
+ asm volatile("mcr p15, 0, %0, c14, c0, 0"
+ : : "r"(COUNTER_FREQUENCY));
+
+ writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
+ writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
+ writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
+ writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE +
+ TIMER_CONTROL_REG);
+}
void board_init_f(ulong dummy)
{
#ifdef CONFIG_DEBUG_UART
debug_uart_init();
#endif
- rockchip_timer_init();
+
+ /* Init secure timer */
+ rockchip_stimer_init();
+ /* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */
+ timer_init();
+
sdram_init();
/* return to maskrom */
diff --git a/arch/arm/mach-rockchip/rk3036-board.c b/arch/arm/mach-rockchip/rk3036-board.c
deleted file mode 100644
index e6ea0e9..0000000
--- a/arch/arm/mach-rockchip/rk3036-board.c
+++ /dev/null
@@ -1,103 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2015 Rockchip Electronics Co., Ltd
- */
-
-#include <common.h>
-#include <clk.h>
-#include <dm.h>
-#include <ram.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/periph.h>
-#include <asm/arch-rockchip/grf_rk3036.h>
-#include <asm/arch-rockchip/boot_mode.h>
-#include <asm/arch-rockchip/sdram_rk3036.h>
-#include <dm/pinctrl.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-__weak int rk_board_late_init(void)
-{
- return 0;
-}
-
-int board_late_init(void)
-{
- setup_boot_mode();
-
- return rk_board_late_init();
-}
-
-int board_init(void)
-{
- return 0;
-}
-
-#if !CONFIG_IS_ENABLED(RAM)
-/*
- * When CONFIG_RAM is enabled, the dram_init() function is implemented
- * in sdram_common.c.
- */
-int dram_init(void)
-{
- gd->ram_size = sdram_size();
-
- return 0;
-}
-#endif
-
-#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
-void enable_caches(void)
-{
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
-}
-#endif
-
-#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
-#include <usb.h>
-#include <usb/dwc2_udc.h>
-
-static struct dwc2_plat_otg_data rk3036_otg_data = {
- .rx_fifo_sz = 512,
- .np_tx_fifo_sz = 16,
- .tx_fifo_sz = 128,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
- int node;
- const char *mode;
- bool matched = false;
- const void *blob = gd->fdt_blob;
-
- /* find the usb_otg node */
- node = fdt_node_offset_by_compatible(blob, -1,
- "rockchip,rk3288-usb");
-
- while (node > 0) {
- mode = fdt_getprop(blob, node, "dr_mode", NULL);
- if (mode && strcmp(mode, "otg") == 0) {
- matched = true;
- break;
- }
-
- node = fdt_node_offset_by_compatible(blob, node,
- "rockchip,rk3288-usb");
- }
- if (!matched) {
- debug("Not found usb_otg device\n");
- return -ENODEV;
- }
- rk3036_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
-
- return dwc2_udc_probe(&rk3036_otg_data);
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
- return 0;
-}
-#endif
diff --git a/arch/arm/mach-rockchip/rk3036/Kconfig b/arch/arm/mach-rockchip/rk3036/Kconfig
index 5e04d20..51cd43b 100644
--- a/arch/arm/mach-rockchip/rk3036/Kconfig
+++ b/arch/arm/mach-rockchip/rk3036/Kconfig
@@ -1,5 +1,8 @@
if ROCKCHIP_RK3036
+choice
+ prompt "RK3036 board select"
+
config TARGET_EVB_RK3036
bool "EVB_RK3036"
select BOARD_LATE_INIT
@@ -8,6 +11,11 @@
bool "KYLIN_RK3036"
select BOARD_LATE_INIT
+endchoice
+
+config ROCKCHIP_BOOT_MODE_REG
+ default 0x200081c8
+
config SYS_SOC
default "rk3036"
diff --git a/arch/arm/mach-rockchip/rk3036/rk3036.c b/arch/arm/mach-rockchip/rk3036/rk3036.c
index 481af8a..be458cf 100644
--- a/arch/arm/mach-rockchip/rk3036/rk3036.c
+++ b/arch/arm/mach-rockchip/rk3036/rk3036.c
@@ -5,6 +5,9 @@
#include <asm/io.h>
#include <asm/arch-rockchip/grf_rk3036.h>
#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/sdram_rk3036.h>
+
+DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_DEBUG_UART_BOARD_INIT
void board_debug_uart_init(void)
@@ -36,3 +39,16 @@
GPIO1C2_UART2_SIN << GPIO1C2_SHIFT);
}
#endif
+
+#if !CONFIG_IS_ENABLED(RAM)
+/*
+ * When CONFIG_RAM is enabled, the dram_init() function is implemented
+ * in sdram_common.c.
+ */
+int dram_init(void)
+{
+ gd->ram_size = sdram_size();
+
+ return 0;
+}
+#endif
diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
index 1d940a0..c39cbb8 100644
--- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
+++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
@@ -9,7 +9,6 @@
#include <asm/arch-rockchip/grf_rk3036.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/sdram_rk3036.h>
-#include <asm/arch-rockchip/timer.h>
#include <asm/arch-rockchip/uart.h>
/*
@@ -345,7 +344,7 @@
/* waiting for pll lock */
while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
- rockchip_udelay(1);
+ udelay(1);
/* PLL enter normal-mode */
rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK,
@@ -373,25 +372,25 @@
1 << DDRCTRL_PSRST_SHIFT | 1 << DDRCTRL_SRST_SHIFT |
1 << DDRPHY_PSRST_SHIFT | 1 << DDRPHY_SRST_SHIFT);
- rockchip_udelay(10);
+ udelay(10);
rk_clrreg(&priv->cru->cru_softrst_con[5], 1 << DDRPHY_PSRST_SHIFT |
1 << DDRPHY_SRST_SHIFT);
- rockchip_udelay(10);
+ udelay(10);
rk_clrreg(&priv->cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT |
1 << DDRCTRL_SRST_SHIFT);
- rockchip_udelay(10);
+ udelay(10);
clrsetbits_le32(&ddr_phy->ddrphy_reg1,
SOFT_RESET_MASK << SOFT_RESET_SHIFT,
0 << SOFT_RESET_SHIFT);
- rockchip_udelay(10);
+ udelay(10);
clrsetbits_le32(&ddr_phy->ddrphy_reg1,
SOFT_RESET_MASK << SOFT_RESET_SHIFT,
3 << SOFT_RESET_SHIFT);
- rockchip_udelay(1);
+ udelay(1);
}
void phy_dll_bypass_set(struct rk3036_sdram_priv *priv, unsigned int freq)
@@ -444,7 +443,7 @@
u32 rank, u32 cmd, u32 arg)
{
writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd);
- rockchip_udelay(1);
+ udelay(1);
while (readl(&pctl->mcmd) & START_CMD)
;
}
@@ -454,7 +453,7 @@
struct rk3036_ddr_pctl *pctl = priv->pctl;
send_command(pctl, 3, DESELECT_CMD, 0);
- rockchip_udelay(1);
+ udelay(1);
send_command(pctl, 3, PREA_CMD, 0);
send_command(pctl, 3, MRS_CMD,
(0x02 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |
@@ -492,7 +491,7 @@
clrsetbits_le32(&ddr_phy->ddrphy_reg2, 0x03,
DQS_SQU_CAL_NORMAL_MODE | DQS_SQU_CAL_START);
- rockchip_udelay(1);
+ udelay(1);
while ((readl(&ddr_phy->ddrphy_reg62) & CAL_DONE_MASK) !=
(HIGH_8BIT_CAL_DONE | LOW_8BIT_CAL_DONE)) {
;
diff --git a/arch/arm/mach-rockchip/rk3128-board.c b/arch/arm/mach-rockchip/rk3128-board.c
deleted file mode 100644
index fa71685..0000000
--- a/arch/arm/mach-rockchip/rk3128-board.c
+++ /dev/null
@@ -1,126 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
- */
-#include <common.h>
-#include <clk.h>
-#include <dm.h>
-#include <ram.h>
-#include <syscon.h>
-#include <asm/io.h>
-#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/periph.h>
-#include <asm/arch-rockchip/grf_rk3128.h>
-#include <asm/arch-rockchip/boot_mode.h>
-#include <asm/arch-rockchip/timer.h>
-#include <power/regulator.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-__weak int rk_board_late_init(void)
-{
- return 0;
-}
-
-int board_late_init(void)
-{
- setup_boot_mode();
-
- return rk_board_late_init();
-}
-
-int board_init(void)
-{
- int ret = 0;
-
- rockchip_timer_init();
-
- ret = regulators_enable_boot_on(false);
- if (ret) {
- debug("%s: Cannot enable boot on regulator\n", __func__);
- return ret;
- }
-
- return 0;
-}
-
-int dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = 0x8400000;
- /* Reserve 0xe00000(14MB) for OPTEE with TA enabled, otherwise 2MB */
- gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
- + gd->bd->bi_dram[0].size + 0xe00000;
- gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
- + gd->ram_size - gd->bd->bi_dram[1].start;
-
- return 0;
-}
-
-#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
-void enable_caches(void)
-{
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
-}
-#endif
-
-#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
-#include <usb.h>
-#include <usb/dwc2_udc.h>
-
-static struct dwc2_plat_otg_data rk3128_otg_data = {
- .rx_fifo_sz = 512,
- .np_tx_fifo_sz = 16,
- .tx_fifo_sz = 128,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
- int node;
- const char *mode;
- bool matched = false;
- const void *blob = gd->fdt_blob;
-
- /* find the usb_otg node */
- node = fdt_node_offset_by_compatible(blob, -1,
- "rockchip,rk3128-usb");
-
- while (node > 0) {
- mode = fdt_getprop(blob, node, "dr_mode", NULL);
- if (mode && strcmp(mode, "otg") == 0) {
- matched = true;
- break;
- }
-
- node = fdt_node_offset_by_compatible(blob, node,
- "rockchip,rk3128-usb");
- }
- if (!matched) {
- debug("Not found usb_otg device\n");
- return -ENODEV;
- }
- rk3128_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
-
- return dwc2_udc_probe(&rk3128_otg_data);
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
- return 0;
-}
-#endif
-
-#if CONFIG_IS_ENABLED(FASTBOOT)
-int fastboot_set_reboot_flag(void)
-{
- struct rk3128_grf *grf;
-
- printf("Setting reboot to fastboot flag ...\n");
- grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
- /* Set boot mode to fastboot */
- writel(BOOT_FASTBOOT, &grf->os_reg[0]);
-
- return 0;
-}
-#endif
diff --git a/arch/arm/mach-rockchip/rk3128/Kconfig b/arch/arm/mach-rockchip/rk3128/Kconfig
index a82b7dc..b867401 100644
--- a/arch/arm/mach-rockchip/rk3128/Kconfig
+++ b/arch/arm/mach-rockchip/rk3128/Kconfig
@@ -13,6 +13,9 @@
endchoice
+config ROCKCHIP_BOOT_MODE_REG
+ default 0x100a0038
+
config SYS_SOC
default "rk3128"
diff --git a/arch/arm/mach-rockchip/rk3128/rk3128.c b/arch/arm/mach-rockchip/rk3128/rk3128.c
index 11bba14..ee176de 100644
--- a/arch/arm/mach-rockchip/rk3128/rk3128.c
+++ b/arch/arm/mach-rockchip/rk3128/rk3128.c
@@ -2,6 +2,9 @@
/*
* Copyright (c) 2017 Rockchip Electronics Co., Ltd
*/
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
int arch_cpu_init(void)
{
diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c b/arch/arm/mach-rockchip/rk3188-board-spl.c
deleted file mode 100644
index 77b9b36..0000000
--- a/arch/arm/mach-rockchip/rk3188-board-spl.c
+++ /dev/null
@@ -1,195 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2015 Google, Inc
- */
-
-#include <clk.h>
-#include <common.h>
-#include <debug_uart.h>
-#include <dm.h>
-#include <fdtdec.h>
-#include <led.h>
-#include <malloc.h>
-#include <ram.h>
-#include <spl.h>
-#include <syscon.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/arch-rockchip/bootrom.h>
-#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/grf_rk3188.h>
-#include <asm/arch-rockchip/hardware.h>
-#include <asm/arch-rockchip/periph.h>
-#include <asm/arch-rockchip/pmu_rk3188.h>
-#include <asm/arch-rockchip/sdram.h>
-#include <asm/arch-rockchip/timer.h>
-#include <dm/pinctrl.h>
-#include <dm/root.h>
-#include <dm/test.h>
-#include <dm/util.h>
-#include <power/regulator.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-u32 spl_boot_device(void)
-{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- const void *blob = gd->fdt_blob;
- struct udevice *dev;
- const char *bootdev;
- int node;
- int ret;
-
- bootdev = fdtdec_get_config_string(blob, "u-boot,boot0");
- debug("Boot device %s\n", bootdev);
- if (!bootdev)
- goto fallback;
-
- node = fdt_path_offset(blob, bootdev);
- if (node < 0) {
- debug("node=%d\n", node);
- goto fallback;
- }
- ret = device_get_global_by_ofnode(offset_to_ofnode(node), &dev);
- if (ret) {
- debug("device at node %s/%d not found: %d\n", bootdev, node,
- ret);
- goto fallback;
- }
- debug("Found device %s\n", dev->name);
- switch (device_get_uclass_id(dev)) {
- case UCLASS_SPI_FLASH:
- return BOOT_DEVICE_SPI;
- case UCLASS_MMC:
- return BOOT_DEVICE_MMC1;
- default:
- debug("Booting from device uclass '%s' not supported\n",
- dev_get_uclass_name(dev));
- }
-
-fallback:
-#endif
- return BOOT_DEVICE_MMC1;
-}
-
-static int setup_arm_clock(void)
-{
- struct udevice *dev;
- struct clk clk;
- int ret;
-
- ret = rockchip_get_clk(&dev);
- if (ret)
- return ret;
-
- clk.id = CLK_ARM;
- ret = clk_request(dev, &clk);
- if (ret < 0)
- return ret;
-
- ret = clk_set_rate(&clk, 600000000);
-
- clk_free(&clk);
- return ret;
-}
-
-void board_init_f(ulong dummy)
-{
- struct udevice *dev;
- int ret;
-
-#ifdef CONFIG_DEBUG_UART
- /*
- * Debug UART can be used from here if required:
- *
- * debug_uart_init();
- * printch('a');
- * printhex8(0x1234);
- * printascii("string");
- */
- debug_uart_init();
- printascii("U-Boot SPL board init");
-#endif
-
-#ifdef CONFIG_ROCKCHIP_USB_UART
- rk_clrsetreg(&grf->uoc0_con[0],
- SIDDQ_MASK | UOC_DISABLE_MASK | COMMON_ON_N_MASK,
- 1 << SIDDQ_SHIFT | 1 << UOC_DISABLE_SHIFT |
- 1 << COMMON_ON_N_SHIFT);
- rk_clrsetreg(&grf->uoc0_con[2],
- SOFT_CON_SEL_MASK, 1 << SOFT_CON_SEL_SHIFT);
- rk_clrsetreg(&grf->uoc0_con[3],
- OPMODE_MASK | XCVRSELECT_MASK |
- TERMSEL_FULLSPEED_MASK | SUSPENDN_MASK,
- OPMODE_NODRIVING << OPMODE_SHIFT |
- XCVRSELECT_FSTRANSC << XCVRSELECT_SHIFT |
- 1 << TERMSEL_FULLSPEED_SHIFT |
- 1 << SUSPENDN_SHIFT);
- rk_clrsetreg(&grf->uoc0_con[0],
- BYPASSSEL_MASK | BYPASSDMEN_MASK,
- 1 << BYPASSSEL_SHIFT | 1 << BYPASSDMEN_SHIFT);
-#endif
-
- ret = spl_early_init();
- if (ret) {
- debug("spl_early_init() failed: %d\n", ret);
- hang();
- }
-
- ret = rockchip_get_clk(&dev);
- if (ret) {
- debug("CLK init failed: %d\n", ret);
- return;
- }
-
- ret = uclass_get_device(UCLASS_RAM, 0, &dev);
- if (ret) {
- debug("DRAM init failed: %d\n", ret);
- return;
- }
-
- setup_arm_clock();
-#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
- back_to_bootrom(BROM_BOOT_NEXTSTAGE);
-#endif
-}
-
-static int setup_led(void)
-{
-#ifdef CONFIG_SPL_LED
- struct udevice *dev;
- char *led_name;
- int ret;
-
- led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
- if (!led_name)
- return 0;
- ret = led_get_by_label(led_name, &dev);
- if (ret) {
- debug("%s: get=%d\n", __func__, ret);
- return ret;
- }
- ret = led_set_on(dev, 1);
- if (ret)
- return ret;
-#endif
-
- return 0;
-}
-
-void spl_board_init(void)
-{
- int ret;
-
- ret = setup_led();
- if (ret) {
- debug("LED ret=%d\n", ret);
- hang();
- }
-
- preloader_console_init();
-#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
- back_to_bootrom(BROM_BOOT_NEXTSTAGE);
-#endif
- return;
-}
diff --git a/arch/arm/mach-rockchip/rk3188-board.c b/arch/arm/mach-rockchip/rk3188-board.c
deleted file mode 100644
index 80d8c42..0000000
--- a/arch/arm/mach-rockchip/rk3188-board.c
+++ /dev/null
@@ -1,84 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2015 Google, Inc
- */
-
-#include <common.h>
-#include <clk.h>
-#include <dm.h>
-#include <ram.h>
-#include <syscon.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/grf_rk3188.h>
-#include <asm/arch-rockchip/periph.h>
-#include <asm/arch-rockchip/pmu_rk3288.h>
-#include <asm/arch-rockchip/boot_mode.h>
-#include <dm/pinctrl.h>
-
-__weak int rk_board_late_init(void)
-{
- return 0;
-}
-
-int board_late_init(void)
-{
- struct rk3188_grf *grf;
-
- setup_boot_mode();
- grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
- if (IS_ERR(grf)) {
- pr_err("grf syscon returned %ld\n", PTR_ERR(grf));
- } else {
- /* enable noc remap to mimic legacy loaders */
- rk_clrsetreg(&grf->soc_con0,
- NOC_REMAP_MASK << NOC_REMAP_SHIFT,
- NOC_REMAP_MASK << NOC_REMAP_SHIFT);
- }
-
- return rk_board_late_init();
-}
-
-int board_init(void)
-{
-#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
- struct udevice *pinctrl;
- int ret;
-
- /*
- * We need to implement sdcard iomux here for the further
- * initialization, otherwise, it'll hit sdcard command sending
- * timeout exception.
- */
- ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
- if (ret) {
- debug("%s: Cannot find pinctrl device\n", __func__);
- goto err;
- }
- ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
- if (ret) {
- debug("%s: Failed to set up SD card\n", __func__);
- goto err;
- }
-
- return 0;
-err:
- printf("board_init: Error %d\n", ret);
-
- /* No way to report error here */
- hang();
-
- return -1;
-#else
- return 0;
-#endif
-}
-
-#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
-void enable_caches(void)
-{
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
-}
-#endif
diff --git a/arch/arm/mach-rockchip/rk3188/Kconfig b/arch/arm/mach-rockchip/rk3188/Kconfig
index a6fc691..e24e68e 100644
--- a/arch/arm/mach-rockchip/rk3188/Kconfig
+++ b/arch/arm/mach-rockchip/rk3188/Kconfig
@@ -9,6 +9,9 @@
Expansion connectors provide access to display pins, I2C, SPI,
UART and GPIOs.
+config ROCKCHIP_BOOT_MODE_REG
+ default 0x20004040
+
config SYS_SOC
default "rk3188"
diff --git a/arch/arm/mach-rockchip/rk3188/rk3188.c b/arch/arm/mach-rockchip/rk3188/rk3188.c
index 933484e..95f0e3c 100644
--- a/arch/arm/mach-rockchip/rk3188/rk3188.c
+++ b/arch/arm/mach-rockchip/rk3188/rk3188.c
@@ -3,15 +3,25 @@
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
#include <common.h>
+#include <dm.h>
+#include <syscon.h>
#include <asm/io.h>
+#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/grf_rk3188.h>
#include <asm/arch-rockchip/hardware.h>
+#define GRF_BASE 0x20008000
+
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+ [BROM_BOOTSOURCE_EMMC] = "dwmmc@1021c000",
+ [BROM_BOOTSOURCE_SD] = "dwmmc@10214000",
+};
+
#ifdef CONFIG_DEBUG_UART_BOARD_INIT
void board_debug_uart_init(void)
{
/* Enable early UART on the RK3188 */
-#define GRF_BASE 0x20008000
struct rk3188_grf * const grf = (void *)GRF_BASE;
enum {
GPIO1B1_SHIFT = 2,
@@ -34,3 +44,77 @@
GPIO1B0_UART2_SIN << GPIO1B0_SHIFT);
}
#endif
+
+#ifdef CONFIG_SPL_BUILD
+int arch_cpu_init(void)
+{
+ struct rk3188_grf *grf;
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ if (IS_ERR(grf)) {
+ pr_err("grf syscon returned %ld\n", PTR_ERR(grf));
+ return 0;
+ }
+#ifdef CONFIG_ROCKCHIP_USB_UART
+ rk_clrsetreg(&grf->uoc0_con[0],
+ SIDDQ_MASK | UOC_DISABLE_MASK | COMMON_ON_N_MASK,
+ 1 << SIDDQ_SHIFT | 1 << UOC_DISABLE_SHIFT |
+ 1 << COMMON_ON_N_SHIFT);
+ rk_clrsetreg(&grf->uoc0_con[2],
+ SOFT_CON_SEL_MASK, 1 << SOFT_CON_SEL_SHIFT);
+ rk_clrsetreg(&grf->uoc0_con[3],
+ OPMODE_MASK | XCVRSELECT_MASK |
+ TERMSEL_FULLSPEED_MASK | SUSPENDN_MASK,
+ OPMODE_NODRIVING << OPMODE_SHIFT |
+ XCVRSELECT_FSTRANSC << XCVRSELECT_SHIFT |
+ 1 << TERMSEL_FULLSPEED_SHIFT |
+ 1 << SUSPENDN_SHIFT);
+ rk_clrsetreg(&grf->uoc0_con[0],
+ BYPASSSEL_MASK | BYPASSDMEN_MASK,
+ 1 << BYPASSSEL_SHIFT | 1 << BYPASSDMEN_SHIFT);
+#endif
+
+ /* enable noc remap to mimic legacy loaders */
+ rk_clrsetreg(&grf->soc_con0,
+ NOC_REMAP_MASK << NOC_REMAP_SHIFT,
+ NOC_REMAP_MASK << NOC_REMAP_SHIFT);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+static int setup_led(void)
+{
+#ifdef CONFIG_SPL_LED
+ struct udevice *dev;
+ char *led_name;
+ int ret;
+
+ led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
+ if (!led_name)
+ return 0;
+ ret = led_get_by_label(led_name, &dev);
+ if (ret) {
+ debug("%s: get=%d\n", __func__, ret);
+ return ret;
+ }
+ ret = led_set_on(dev, 1);
+ if (ret)
+ return ret;
+#endif
+
+ return 0;
+}
+
+void spl_board_init(void)
+{
+ int ret;
+
+ ret = setup_led();
+ if (ret) {
+ debug("LED ret=%d\n", ret);
+ hang();
+ }
+}
+#endif
diff --git a/arch/arm/mach-rockchip/rk322x-board-spl.c b/arch/arm/mach-rockchip/rk322x-board-spl.c
deleted file mode 100644
index c9b41c6..0000000
--- a/arch/arm/mach-rockchip/rk322x-board-spl.c
+++ /dev/null
@@ -1,46 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2017 Rockchip Electronics Co., Ltd
- */
-
-#include <common.h>
-#include <dm.h>
-#include <spl.h>
-#include <asm/io.h>
-#include <asm/arch-rockchip/hardware.h>
-
-u32 spl_boot_device(void)
-{
- return BOOT_DEVICE_MMC1;
-}
-
-u32 spl_boot_mode(const u32 boot_device)
-{
- return MMCSD_MODE_RAW;
-}
-
-#define SGRF_DDR_CON0 0x10150000
-void board_init_f(ulong dummy)
-{
- int ret;
-
- ret = spl_early_init();
- if (ret) {
- printf("spl_early_init() failed: %d\n", ret);
- hang();
- }
- preloader_console_init();
-
- /* Disable the ddr secure region setting to make it non-secure */
- rk_clrreg(SGRF_DDR_CON0, 0x4000);
-}
-
-#ifdef CONFIG_SPL_LOAD_FIT
-int board_fit_config_name_match(const char *name)
-{
- /* Just empty function now - can't decide what to choose */
- debug("%s: %s\n", __func__, name);
-
- return 0;
-}
-#endif
diff --git a/arch/arm/mach-rockchip/rk322x-board-tpl.c b/arch/arm/mach-rockchip/rk322x-board-tpl.c
deleted file mode 100644
index 92d40ee..0000000
--- a/arch/arm/mach-rockchip/rk322x-board-tpl.c
+++ /dev/null
@@ -1,53 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2019 Rockchip Electronics Co., Ltd
- */
-
-#include <common.h>
-#include <debug_uart.h>
-#include <dm.h>
-#include <ram.h>
-#include <spl.h>
-#include <asm/io.h>
-#include <asm/arch-rockchip/bootrom.h>
-#include <asm/arch-rockchip/timer.h>
-
-u32 spl_boot_device(void)
-{
- return BOOT_DEVICE_MMC1;
-}
-
-void board_init_f(ulong dummy)
-{
- struct udevice *dev;
- int ret;
-
- /*
- * Debug UART can be used from here if required:
- *
- * debug_uart_init();
- * printch('a');
- * printhex8(0x1234);
- * printascii("string");
- */
- debug_uart_init();
- printascii("TPL Init");
-
- ret = spl_early_init();
- if (ret) {
- debug("spl_early_init() failed: %d\n", ret);
- hang();
- }
-
- rockchip_timer_init();
- printf("timer init done\n");
- ret = uclass_get_device(UCLASS_RAM, 0, &dev);
- if (ret) {
- printf("DRAM init failed: %d\n", ret);
- return;
- }
-
-#if defined(CONFIG_TPL_ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_TPL_BOARD_INIT)
- back_to_bootrom(BROM_BOOT_NEXTSTAGE);
-#endif
-}
diff --git a/arch/arm/mach-rockchip/rk322x-board.c b/arch/arm/mach-rockchip/rk322x-board.c
deleted file mode 100644
index e7a1e54..0000000
--- a/arch/arm/mach-rockchip/rk322x-board.c
+++ /dev/null
@@ -1,127 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
- */
-#include <common.h>
-#include <clk.h>
-#include <dm.h>
-#include <ram.h>
-#include <syscon.h>
-#include <asm/io.h>
-#include <asm/arch-rockchip/boot_mode.h>
-#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/grf_rk322x.h>
-#include <asm/arch-rockchip/periph.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-__weak int rk_board_late_init(void)
-{
- return 0;
-}
-
-int board_late_init(void)
-{
- setup_boot_mode();
-
- return rk_board_late_init();
-}
-
-int board_init(void)
-{
-#include <asm/arch-rockchip/grf_rk322x.h>
- /* Enable early UART2 channel 1 on the RK322x */
-#define GRF_BASE 0x11000000
- static struct rk322x_grf * const grf = (void *)GRF_BASE;
-
- /*
- * The integrated macphy is enabled by default, disable it
- * for saving power consuming.
- */
- rk_clrsetreg(&grf->macphy_con[0],
- MACPHY_CFG_ENABLE_MASK,
- 0 << MACPHY_CFG_ENABLE_SHIFT);
-
- return 0;
-}
-
-int dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = 0x8400000;
- /* Reserve 0x200000 for OPTEE */
- gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
- + gd->bd->bi_dram[0].size + 0x200000;
- gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
- + gd->ram_size - gd->bd->bi_dram[1].start;
-
- return 0;
-}
-
-#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
-void enable_caches(void)
-{
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
-}
-#endif
-
-#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
-#include <usb.h>
-#include <usb/dwc2_udc.h>
-
-static struct dwc2_plat_otg_data rk322x_otg_data = {
- .rx_fifo_sz = 512,
- .np_tx_fifo_sz = 16,
- .tx_fifo_sz = 128,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
- int node;
- const char *mode;
- bool matched = false;
- const void *blob = gd->fdt_blob;
-
- /* find the usb_otg node */
- node = fdt_node_offset_by_compatible(blob, -1,
- "rockchip,rk3288-usb");
-
- while (node > 0) {
- mode = fdt_getprop(blob, node, "dr_mode", NULL);
- if (mode && strcmp(mode, "otg") == 0) {
- matched = true;
- break;
- }
-
- node = fdt_node_offset_by_compatible(blob, node,
- "rockchip,rk3288-usb");
- }
- if (!matched) {
- debug("Not found usb_otg device\n");
- return -ENODEV;
- }
- rk322x_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
-
- return dwc2_udc_probe(&rk322x_otg_data);
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
- return 0;
-}
-#endif
-
-#if CONFIG_IS_ENABLED(FASTBOOT)
-int fastboot_set_reboot_flag(void)
-{
- struct rk322x_grf *grf;
-
- printf("Setting reboot to fastboot flag ...\n");
- grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
- /* Set boot mode to fastboot */
- writel(BOOT_FASTBOOT, &grf->os_reg[0]);
-
- return 0;
-}
-#endif
diff --git a/arch/arm/mach-rockchip/rk322x/Kconfig b/arch/arm/mach-rockchip/rk322x/Kconfig
index 8a1f95f..2fc6f6e 100644
--- a/arch/arm/mach-rockchip/rk322x/Kconfig
+++ b/arch/arm/mach-rockchip/rk322x/Kconfig
@@ -1,18 +1,37 @@
if ROCKCHIP_RK322X
+
config TARGET_EVB_RK3229
bool "EVB_RK3229"
select BOARD_LATE_INIT
+config ROCKCHIP_BOOT_MODE_REG
+ default 0x110005c8
+
config SYS_SOC
default "rk322x"
config SYS_MALLOC_F_LEN
- default 0x400
+ default 0x800
+
+config SPL_LIBCOMMON_SUPPORT
+ default y
+
+config SPL_LIBGENERIC_SUPPORT
+ default y
config SPL_SERIAL_SUPPORT
default y
+config TPL_MAX_SIZE
+ default 28672
+
+config TPL_STACK
+ default 0x10088000
+
+config TPL_TEXT_BASE
+ default 0x10081000
+
source "board/rockchip/evb_rk3229/Kconfig"
endif
diff --git a/arch/arm/mach-rockchip/rk322x/rk322x.c b/arch/arm/mach-rockchip/rk322x/rk322x.c
index e5250bc..cd0bf8a 100644
--- a/arch/arm/mach-rockchip/rk322x/rk322x.c
+++ b/arch/arm/mach-rockchip/rk322x/rk322x.c
@@ -3,9 +3,15 @@
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
#include <asm/io.h>
+#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/grf_rk322x.h>
#include <asm/arch-rockchip/hardware.h>
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+ [BROM_BOOTSOURCE_EMMC] = "dwmmc@30020000",
+ [BROM_BOOTSOURCE_SD] = "dwmmc@30000000",
+};
+
#ifdef CONFIG_DEBUG_UART_BOARD_INIT
void board_debug_uart_init(void)
{
@@ -42,3 +48,26 @@
CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
}
#endif
+
+int arch_cpu_init(void)
+{
+#ifdef CONFIG_SPL_BUILD
+#define SGRF_BASE 0x10150000
+ static struct rk322x_sgrf * const sgrf = (void *)SGRF_BASE;
+
+ /* Disable the ddr secure region setting to make it non-secure */
+ rk_clrreg(&sgrf->soc_con[0], 0x4000);
+#else
+#define GRF_BASE 0x11000000
+ static struct rk322x_grf * const grf = (void *)GRF_BASE;
+ /*
+ * The integrated macphy is enabled by default, disable it
+ * for saving power consuming.
+ */
+ rk_clrsetreg(&grf->macphy_con[0],
+ MACPHY_CFG_ENABLE_MASK,
+ 0 << MACPHY_CFG_ENABLE_SHIFT);
+
+#endif
+ return 0;
+}
diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c
deleted file mode 100644
index d8d215d..0000000
--- a/arch/arm/mach-rockchip/rk3288-board-spl.c
+++ /dev/null
@@ -1,217 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2015 Google, Inc
- */
-
-#include <common.h>
-#include <debug_uart.h>
-#include <dm.h>
-#include <fdtdec.h>
-#include <i2c.h>
-#include <led.h>
-#include <malloc.h>
-#include <ram.h>
-#include <spl.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/arch-rockchip/bootrom.h>
-#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/hardware.h>
-#include <asm/arch-rockchip/periph.h>
-#include <asm/arch-rockchip/pmu_rk3288.h>
-#include <asm/arch-rockchip/sdram.h>
-#include <asm/arch-rockchip/sdram_common.h>
-#include <asm/arch-rockchip/sys_proto.h>
-#include <asm/arch-rockchip/timer.h>
-#include <dm/pinctrl.h>
-#include <dm/root.h>
-#include <dm/test.h>
-#include <dm/util.h>
-#include <power/regulator.h>
-#include <power/rk8xx_pmic.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-u32 spl_boot_device(void)
-{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- const void *blob = gd->fdt_blob;
- struct udevice *dev;
- const char *bootdev;
- int node;
- int ret;
-
- bootdev = fdtdec_get_config_string(blob, "u-boot,boot0");
- debug("Boot device %s\n", bootdev);
- if (!bootdev)
- goto fallback;
-
- node = fdt_path_offset(blob, bootdev);
- if (node < 0) {
- debug("node=%d\n", node);
- goto fallback;
- }
- ret = device_get_global_by_ofnode(offset_to_ofnode(node), &dev);
- if (ret) {
- debug("device at node %s/%d not found: %d\n", bootdev, node,
- ret);
- goto fallback;
- }
- debug("Found device %s\n", dev->name);
- switch (device_get_uclass_id(dev)) {
- case UCLASS_SPI_FLASH:
- return BOOT_DEVICE_SPI;
- case UCLASS_MMC:
- return BOOT_DEVICE_MMC1;
- default:
- debug("Booting from device uclass '%s' not supported\n",
- dev_get_uclass_name(dev));
- }
-
-fallback:
-#elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
- defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
- defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) || \
- defined(CONFIG_TARGET_CHROMEBOOK_SPEEDY)
- return BOOT_DEVICE_SPI;
-#endif
- return BOOT_DEVICE_MMC1;
-}
-
-#if !defined(CONFIG_SPL_OF_PLATDATA)
-static int phycore_init(void)
-{
- struct udevice *pmic;
- int ret;
-
- ret = uclass_first_device_err(UCLASS_PMIC, &pmic);
- if (ret)
- return ret;
-
-#if defined(CONFIG_SPL_POWER_SUPPORT)
- /* Increase USB input current to 2A */
- ret = rk818_spl_configure_usb_input_current(pmic, 2000);
- if (ret)
- return ret;
-
- /* Close charger when USB lower then 3.26V */
- ret = rk818_spl_configure_usb_chrg_shutdown(pmic, 3260000);
- if (ret)
- return ret;
-#endif
-
- return 0;
-}
-#endif
-
-void board_init_f(ulong dummy)
-{
- struct udevice *dev;
- int ret;
-
-#ifdef CONFIG_DEBUG_UART
- /*
- * Debug UART can be used from here if required:
- *
- * debug_uart_init();
- * printch('a');
- * printhex8(0x1234);
- * printascii("string");
- */
- debug_uart_init();
- debug("\nspl:debug uart enabled in %s\n", __func__);
-#endif
- ret = spl_early_init();
- if (ret) {
- debug("spl_early_init() failed: %d\n", ret);
- hang();
- }
-
- rockchip_timer_init();
- configure_l2ctlr();
-
- ret = rockchip_get_clk(&dev);
- if (ret) {
- debug("CLK init failed: %d\n", ret);
- return;
- }
-
-#if !defined(CONFIG_SPL_OF_PLATDATA)
- if (of_machine_is_compatible("phytec,rk3288-phycore-som")) {
- ret = phycore_init();
- if (ret) {
- debug("Failed to set up phycore power settings: %d\n",
- ret);
- return;
- }
- }
-#endif
-
-#if !defined(CONFIG_SUPPORT_TPL)
- debug("\nspl:init dram\n");
- ret = uclass_get_device(UCLASS_RAM, 0, &dev);
- if (ret) {
- debug("DRAM init failed: %d\n", ret);
- return;
- }
-#endif
-
-#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
- back_to_bootrom(BROM_BOOT_NEXTSTAGE);
-#endif
-}
-
-static int setup_led(void)
-{
-#ifdef CONFIG_SPL_LED
- struct udevice *dev;
- char *led_name;
- int ret;
-
- led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
- if (!led_name)
- return 0;
- ret = led_get_by_label(led_name, &dev);
- if (ret) {
- debug("%s: get=%d\n", __func__, ret);
- return ret;
- }
- ret = led_set_on(dev, 1);
- if (ret)
- return ret;
-#endif
-
- return 0;
-}
-
-void spl_board_init(void)
-{
- int ret;
-
- ret = setup_led();
- if (ret) {
- debug("LED ret=%d\n", ret);
- hang();
- }
-
- preloader_console_init();
-#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
- back_to_bootrom(BROM_BOOT_NEXTSTAGE);
-#endif
- return;
-}
-
-#ifdef CONFIG_SPL_OS_BOOT
-
-#define PMU_BASE 0xff730000
-int dram_init_banksize(void)
-{
- struct rk3288_pmu *const pmu = (void *)PMU_BASE;
- size_t size = rockchip_sdram_size((phys_addr_t)&pmu->sys_reg[2]);
-
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = size;
-
- return 0;
-}
-#endif
diff --git a/arch/arm/mach-rockchip/rk3288-board-tpl.c b/arch/arm/mach-rockchip/rk3288-board-tpl.c
deleted file mode 100644
index 787129b..0000000
--- a/arch/arm/mach-rockchip/rk3288-board-tpl.c
+++ /dev/null
@@ -1,70 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2017 Amarula Solutions
- */
-
-#include <common.h>
-#include <debug_uart.h>
-#include <dm.h>
-#include <ram.h>
-#include <spl.h>
-#include <version.h>
-#include <asm/io.h>
-#include <asm/arch-rockchip/bootrom.h>
-#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/sys_proto.h>
-#include <asm/arch-rockchip/timer.h>
-
-void board_init_f(ulong dummy)
-{
- struct udevice *dev;
- int ret;
-
-#ifdef CONFIG_DEBUG_UART
- /*
- * Debug UART can be used from here if required:
- *
- * debug_uart_init();
- * printch('a');
- * printhex8(0x1234);
- * printascii("string");
- */
- debug_uart_init();
-#endif
- ret = spl_early_init();
- if (ret) {
- debug("spl_early_init() failed: %d\n", ret);
- hang();
- }
-
- rockchip_timer_init();
- configure_l2ctlr();
-
- ret = rockchip_get_clk(&dev);
- if (ret) {
- debug("CLK init failed: %d\n", ret);
- return;
- }
-
- ret = uclass_get_device(UCLASS_RAM, 0, &dev);
- if (ret) {
- debug("DRAM init failed: %d\n", ret);
- return;
- }
-}
-
-void board_return_to_bootrom(void)
-{
- back_to_bootrom(BROM_BOOT_NEXTSTAGE);
-}
-
-u32 spl_boot_device(void)
-{
- return BOOT_DEVICE_BOOTROM;
-}
-
-void spl_board_init(void)
-{
- puts("\nU-Boot TPL " PLAIN_VERSION " (" U_BOOT_DATE " - " \
- U_BOOT_TIME ")\n");
-}
diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c
deleted file mode 100644
index e2de5b2..0000000
--- a/arch/arm/mach-rockchip/rk3288-board.c
+++ /dev/null
@@ -1,347 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2015 Google, Inc
- */
-
-#include <common.h>
-#include <clk.h>
-#include <dm.h>
-#include <ram.h>
-#include <syscon.h>
-#include <asm/io.h>
-#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/cru_rk3288.h>
-#include <asm/arch-rockchip/periph.h>
-#include <asm/arch-rockchip/pmu_rk3288.h>
-#include <asm/arch-rockchip/qos_rk3288.h>
-#include <asm/arch-rockchip/boot_mode.h>
-#include <asm/gpio.h>
-#include <dm/pinctrl.h>
-#include <dt-bindings/clock/rk3288-cru.h>
-#include <power/regulator.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-__weak int rk_board_late_init(void)
-{
- return 0;
-}
-
-int rk3288_qos_init(void)
-{
- int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT;
- /* set vop qos to higher priority */
- writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS);
- writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS);
-
- if (!fdt_node_check_compatible(gd->fdt_blob, 0,
- "rockchip,rk3288-tinker"))
- {
- /* set isp qos to higher priority */
- writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS);
- writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS);
- writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS);
- }
- return 0;
-}
-
-static void rk3288_detect_reset_reason(void)
-{
- struct rk3288_cru *cru = rockchip_get_cru();
- const char *reason;
-
- if (IS_ERR(cru))
- return;
-
- switch (cru->cru_glb_rst_st) {
- case GLB_POR_RST:
- reason = "POR";
- break;
- case FST_GLB_RST_ST:
- case SND_GLB_RST_ST:
- reason = "RST";
- break;
- case FST_GLB_TSADC_RST_ST:
- case SND_GLB_TSADC_RST_ST:
- reason = "THERMAL";
- break;
- case FST_GLB_WDT_RST_ST:
- case SND_GLB_WDT_RST_ST:
- reason = "WDOG";
- break;
- default:
- reason = "unknown reset";
- }
-
- env_set("reset_reason", reason);
-
- /*
- * Clear cru_glb_rst_st, so we can determine the last reset cause
- * for following resets.
- */
- rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK);
-}
-
-int board_late_init(void)
-{
- setup_boot_mode();
- rk3288_qos_init();
- rk3288_detect_reset_reason();
-
- return rk_board_late_init();
-}
-
-#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
-static int veyron_init(void)
-{
- struct udevice *dev;
- struct clk clk;
- int ret;
-
- ret = regulator_get_by_platname("vdd_arm", &dev);
- if (ret) {
- debug("Cannot set regulator name\n");
- return ret;
- }
-
- /* Slowly raise to max CPU voltage to prevent overshoot */
- ret = regulator_set_value(dev, 1200000);
- if (ret)
- return ret;
- udelay(175); /* Must wait for voltage to stabilize, 2mV/us */
- ret = regulator_set_value(dev, 1400000);
- if (ret)
- return ret;
- udelay(100); /* Must wait for voltage to stabilize, 2mV/us */
-
- ret = rockchip_get_clk(&clk.dev);
- if (ret)
- return ret;
- clk.id = PLL_APLL;
- ret = clk_set_rate(&clk, 1800000000);
- if (IS_ERR_VALUE(ret))
- return ret;
-
- ret = regulator_get_by_platname("vcc33_sd", &dev);
- if (ret) {
- debug("Cannot get regulator name\n");
- return ret;
- }
-
- ret = regulator_set_value(dev, 3300000);
- if (ret)
- return ret;
-
- ret = regulators_enable_boot_on(false);
- if (ret) {
- debug("%s: Cannot enable boot on regulators\n", __func__);
- return ret;
- }
-
- return 0;
-}
-#endif
-
-int board_init(void)
-{
-#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
- struct udevice *pinctrl;
- int ret;
-
- /*
- * We need to implement sdcard iomux here for the further
- * initlization, otherwise, it'll hit sdcard command sending
- * timeout exception.
- */
- ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
- if (ret) {
- debug("%s: Cannot find pinctrl device\n", __func__);
- goto err;
- }
- ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
- if (ret) {
- debug("%s: Failed to set up SD card\n", __func__);
- goto err;
- }
-
- return 0;
-err:
- printf("board_init: Error %d\n", ret);
-
- /* No way to report error here */
- hang();
-
- return -1;
-#else
- int ret;
-
- /* We do some SoC one time setting here */
- if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) {
- ret = veyron_init();
- if (ret)
- return ret;
- }
-
- return 0;
-#endif
-}
-
-#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
-void enable_caches(void)
-{
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
-}
-#endif
-
-#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
-#include <usb.h>
-#include <usb/dwc2_udc.h>
-
-static struct dwc2_plat_otg_data rk3288_otg_data = {
- .rx_fifo_sz = 512,
- .np_tx_fifo_sz = 16,
- .tx_fifo_sz = 128,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
- int node, phy_node;
- const char *mode;
- bool matched = false;
- const void *blob = gd->fdt_blob;
- u32 grf_phy_offset;
-
- /* find the usb_otg node */
- node = fdt_node_offset_by_compatible(blob, -1,
- "rockchip,rk3288-usb");
-
- while (node > 0) {
- mode = fdt_getprop(blob, node, "dr_mode", NULL);
- if (mode && strcmp(mode, "otg") == 0) {
- matched = true;
- break;
- }
-
- node = fdt_node_offset_by_compatible(blob, node,
- "rockchip,rk3288-usb");
- }
- if (!matched) {
- debug("Not found usb_otg device\n");
- return -ENODEV;
- }
- rk3288_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
-
- node = fdtdec_lookup_phandle(blob, node, "phys");
- if (node <= 0) {
- debug("Not found usb phy device\n");
- return -ENODEV;
- }
-
- phy_node = fdt_parent_offset(blob, node);
- if (phy_node <= 0) {
- debug("Not found usb phy device\n");
- return -ENODEV;
- }
-
- rk3288_otg_data.phy_of_node = phy_node;
- grf_phy_offset = fdtdec_get_addr(blob, node, "reg");
-
- /* find the grf node */
- node = fdt_node_offset_by_compatible(blob, -1,
- "rockchip,rk3288-grf");
- if (node <= 0) {
- debug("Not found grf device\n");
- return -ENODEV;
- }
- rk3288_otg_data.regs_phy = grf_phy_offset +
- fdtdec_get_addr(blob, node, "reg");
-
- return dwc2_udc_probe(&rk3288_otg_data);
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
- return 0;
-}
-#endif
-
-static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- static const struct {
- char *name;
- int id;
- } clks[] = {
- { "osc", CLK_OSC },
- { "apll", CLK_ARM },
- { "dpll", CLK_DDR },
- { "cpll", CLK_CODEC },
- { "gpll", CLK_GENERAL },
-#ifdef CONFIG_ROCKCHIP_RK3036
- { "mpll", CLK_NEW },
-#else
- { "npll", CLK_NEW },
-#endif
- };
- int ret, i;
- struct udevice *dev;
-
- ret = rockchip_get_clk(&dev);
- if (ret) {
- printf("clk-uclass not found\n");
- return 0;
- }
-
- for (i = 0; i < ARRAY_SIZE(clks); i++) {
- struct clk clk;
- ulong rate;
-
- clk.id = clks[i].id;
- ret = clk_request(dev, &clk);
- if (ret < 0)
- continue;
-
- rate = clk_get_rate(&clk);
- printf("%s: %lu\n", clks[i].name, rate);
-
- clk_free(&clk);
- }
-
- return 0;
-}
-
-U_BOOT_CMD(
- clock, 2, 1, do_clock,
- "display information about clocks",
- ""
-);
-
-int board_early_init_f(void)
-{
- const uintptr_t GRF_SOC_CON0 = 0xff770244;
- const uintptr_t GRF_SOC_CON2 = 0xff77024c;
- struct udevice *dev;
- int ret;
-
- /*
- * This init is done in SPL, but when chain-loading U-Boot SPL will
- * have been skipped. Allow the clock driver to check if it needs
- * setting up.
- */
- ret = rockchip_get_clk(&dev);
- if (ret) {
- debug("CLK init failed: %d\n", ret);
- return ret;
- }
-
- rk_setreg(GRF_SOC_CON2, 1 << 0);
-
- /*
- * Disable JTAG on sdmmc0 IO. The SDMMC won't work until this bit is
- * cleared
- */
- rk_clrreg(GRF_SOC_CON0, 1 << 12);
-
- return 0;
-}
diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig
index c5dcd06..4ebc079 100644
--- a/arch/arm/mach-rockchip/rk3288/Kconfig
+++ b/arch/arm/mach-rockchip/rk3288/Kconfig
@@ -1,5 +1,8 @@
if ROCKCHIP_RK3288
+choice
+ prompt "RK3288 board select"
+
config TARGET_CHROMEBOOK_JERRY
bool "Google/Rockchip Veyron-Jerry Chromebook"
select BOARD_LATE_INIT
@@ -44,6 +47,7 @@
config TARGET_EVB_RK3288
bool "Evb-RK3288"
select BOARD_LATE_INIT
+ select TPL
help
EVB-RK3288 is a RK3288-based development board with 2 USB ports,
HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet, It
@@ -62,6 +66,7 @@
config TARGET_FIREFLY_RK3288
bool "Firefly-RK3288"
select BOARD_LATE_INIT
+ select SPL_BOARD_INIT if SPL
help
Firefly is a RK3288-based development board with 2 USB ports,
HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet, It
@@ -80,6 +85,7 @@
config TARGET_PHYCORE_RK3288
bool "phyCORE-RK3288"
select BOARD_LATE_INIT
+ select SPL_BOARD_INIT if SPL
help
Add basic support for the PCM-947 carrier board, a RK3288 based
development board made by PHYTEC. This board works in a combination
@@ -98,7 +104,6 @@
config TARGET_VYASA_RK3288
bool "Vyasa-RK3288"
select BOARD_LATE_INIT
- select ROCKCHIP_BROM_HELPER
select TPL
help
Vyasa is a RK3288-based development board with 2 USB ports,
@@ -125,6 +130,8 @@
8GB eMMC and 2GB of SDRAM. Expansion connectors provide access to
I2C, SPI, UART, GPIOs.
+endchoice
+
config ROCKCHIP_FAST_SPL
bool "Change the CPU to full speed in SPL"
depends on TARGET_CHROMEBOOK_JERRY
@@ -134,11 +141,14 @@
voltage. This option is only available on boards which support it
and have the required PMIC code.
+config ROCKCHIP_BOOT_MODE_REG
+ default 0xff730094
+
config SYS_SOC
default "rk3288"
config SYS_MALLOC_F_LEN
- default 0x0800
+ default 0x2000
config SPL_DRIVERS_MISC_SUPPORT
default y
@@ -152,6 +162,18 @@
config SPL_SERIAL_SUPPORT
default y
+config TPL_LDSCRIPT
+ default "arch/arm/mach-rockchip/u-boot-tpl.lds"
+
+config TPL_MAX_SIZE
+ default 32768
+
+config TPL_STACK
+ default 0xff718000
+
+config TPL_TEXT_BASE
+ default 0xff704000
+
source "board/amarula/vyasa-rk3288/Kconfig"
source "board/chipspark/popmetal_rk3288/Kconfig"
@@ -168,8 +190,6 @@
source "board/rockchip/evb_rk3288/Kconfig"
-source "board/rockchip/fennec_rk3288/Kconfig"
-
source "board/rockchip/tinker_rk3288/Kconfig"
endif
diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c
index 7941ca6..057ce92 100644
--- a/arch/arm/mach-rockchip/rk3288/rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/rk3288.c
@@ -2,20 +2,89 @@
/*
* Copyright (c) 2016 Rockchip Electronics Co., Ltd
*/
+#include <common.h>
+#include <dm.h>
+#include <env.h>
+#include <clk.h>
+#include <asm/armv7.h>
#include <asm/io.h>
+#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3288.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/grf_rk3288.h>
+#include <asm/arch-rockchip/pmu_rk3288.h>
+#include <asm/arch-rockchip/qos_rk3288.h>
+#include <asm/arch-rockchip/sdram_common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
#define GRF_BASE 0xff770000
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+ [BROM_BOOTSOURCE_EMMC] = "dwmmc@ff0f0000",
+ [BROM_BOOTSOURCE_SD] = "dwmmc@ff0c0000",
+};
+
+#ifdef CONFIG_SPL_BUILD
+static void configure_l2ctlr(void)
+{
+ u32 l2ctlr;
+
+ l2ctlr = read_l2ctlr();
+ l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
+
+ /*
+ * Data RAM write latency: 2 cycles
+ * Data RAM read latency: 2 cycles
+ * Data RAM setup latency: 1 cycle
+ * Tag RAM write latency: 1 cycle
+ * Tag RAM read latency: 1 cycle
+ * Tag RAM setup latency: 1 cycle
+ */
+ l2ctlr |= (1 << 3 | 1 << 0);
+ write_l2ctlr(l2ctlr);
+}
+#endif
+
+int rk3288_qos_init(void)
+{
+ int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT;
+ /* set vop qos to higher priority */
+ writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS);
+ writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS);
+
+ if (!fdt_node_check_compatible(gd->fdt_blob, 0,
+ "rockchip,rk3288-tinker")) {
+ /* set isp qos to higher priority */
+ writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS);
+ writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS);
+ writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS);
+ }
+
+ return 0;
+}
+
int arch_cpu_init(void)
{
+#ifdef CONFIG_SPL_BUILD
+ configure_l2ctlr();
+#else
/* We do some SoC one time setting here. */
struct rk3288_grf * const grf = (void *)GRF_BASE;
/* Use rkpwm by default */
rk_setreg(&grf->soc_con2, 1 << 0);
+ /*
+ * Disable JTAG on sdmmc0 IO. The SDMMC won't work until this bit is
+ * cleared
+ */
+ rk_clrreg(&grf->soc_con0, 1 << 12);
+
+ rk3288_qos_init();
+#endif
+
return 0;
}
@@ -31,3 +100,103 @@
GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
}
#endif
+
+static void rk3288_detect_reset_reason(void)
+{
+ struct rk3288_cru *cru = rockchip_get_cru();
+ const char *reason;
+
+ if (IS_ERR(cru))
+ return;
+
+ switch (cru->cru_glb_rst_st) {
+ case GLB_POR_RST:
+ reason = "POR";
+ break;
+ case FST_GLB_RST_ST:
+ case SND_GLB_RST_ST:
+ reason = "RST";
+ break;
+ case FST_GLB_TSADC_RST_ST:
+ case SND_GLB_TSADC_RST_ST:
+ reason = "THERMAL";
+ break;
+ case FST_GLB_WDT_RST_ST:
+ case SND_GLB_WDT_RST_ST:
+ reason = "WDOG";
+ break;
+ default:
+ reason = "unknown reset";
+ }
+
+ env_set("reset_reason", reason);
+
+ /*
+ * Clear cru_glb_rst_st, so we can determine the last reset cause
+ * for following resets.
+ */
+ rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK);
+}
+
+__weak int rk3288_board_late_init(void)
+{
+ return 0;
+}
+
+int rk_board_late_init(void)
+{
+ rk3288_detect_reset_reason();
+
+ return rk3288_board_late_init();
+}
+
+static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ static const struct {
+ char *name;
+ int id;
+ } clks[] = {
+ { "osc", CLK_OSC },
+ { "apll", CLK_ARM },
+ { "dpll", CLK_DDR },
+ { "cpll", CLK_CODEC },
+ { "gpll", CLK_GENERAL },
+#ifdef CONFIG_ROCKCHIP_RK3036
+ { "mpll", CLK_NEW },
+#else
+ { "npll", CLK_NEW },
+#endif
+ };
+ int ret, i;
+ struct udevice *dev;
+
+ ret = rockchip_get_clk(&dev);
+ if (ret) {
+ printf("clk-uclass not found\n");
+ return 0;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(clks); i++) {
+ struct clk clk;
+ ulong rate;
+
+ clk.id = clks[i].id;
+ ret = clk_request(dev, &clk);
+ if (ret < 0)
+ continue;
+
+ rate = clk_get_rate(&clk);
+ printf("%s: %lu\n", clks[i].name, rate);
+
+ clk_free(&clk);
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ clock, 2, 1, do_clock,
+ "display information about clocks",
+ ""
+);
diff --git a/arch/arm/mach-rockchip/rk3328-board-spl.c b/arch/arm/mach-rockchip/rk3328-board-spl.c
deleted file mode 100644
index 7f49d05..0000000
--- a/arch/arm/mach-rockchip/rk3328-board-spl.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <debug_uart.h>
-#include <dm.h>
-#include <dm/pinctrl.h>
-#include <ram.h>
-#include <spl.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void board_debug_uart_init(void)
-{
-}
-
-void board_init_f(ulong dummy)
-{
- struct udevice *dev;
- int ret;
-
- ret = spl_early_init();
- if (ret) {
- debug("spl_early_init() failed: %d\n", ret);
- hang();
- }
-
- preloader_console_init();
-
- ret = uclass_get_device(UCLASS_RAM, 0, &dev);
- if (ret) {
- debug("DRAM init failed: %d\n", ret);
- return;
- }
-}
-
-u32 spl_boot_mode(const u32 boot_device)
-{
- return MMCSD_MODE_RAW;
-}
-
-u32 spl_boot_device(void)
-{
- return BOOT_DEVICE_MMC1;
-}
-
-#ifdef CONFIG_SPL_LOAD_FIT
-int board_fit_config_name_match(const char *name)
-{
- /* Just empty function now - can't decide what to choose */
- debug("%s: %s\n", __func__, name);
-
- return 0;
-}
-#endif
diff --git a/arch/arm/mach-rockchip/rk3328/Kconfig b/arch/arm/mach-rockchip/rk3328/Kconfig
index 6c5c430..d13a169 100644
--- a/arch/arm/mach-rockchip/rk3328/Kconfig
+++ b/arch/arm/mach-rockchip/rk3328/Kconfig
@@ -12,11 +12,32 @@
endchoice
+config ROCKCHIP_BOOT_MODE_REG
+ default 0xff1005c8
+
config SYS_SOC
default "rk3328"
config SYS_MALLOC_F_LEN
- default 0x0800
+ default 0x2000
+
+config SPL_LIBCOMMON_SUPPORT
+ default y
+
+config SPL_LIBGENERIC_SUPPORT
+ default y
+
+config TPL_LDSCRIPT
+ default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
+
+config TPL_TEXT_BASE
+ default 0xff091000
+
+config TPL_MAX_SIZE
+ default 28672
+
+config TPL_STACK
+ default 0xff098000
source "board/rockchip/evb_rk3328/Kconfig"
diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c
index 1cf829d..c2448d7 100644
--- a/arch/arm/mach-rockchip/rk3328/rk3328.c
+++ b/arch/arm/mach-rockchip/rk3328/rk3328.c
@@ -4,12 +4,25 @@
*/
#include <common.h>
+#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/grf_rk3328.h>
+#include <asm/arch-rockchip/uart.h>
#include <asm/armv8/mmu.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
+#define CRU_BASE 0xFF440000
+#define GRF_BASE 0xFF100000
+#define UART2_BASE 0xFF130000
+#define FW_DDR_CON_REG 0xFF7C0040
+
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+ [BROM_BOOTSOURCE_EMMC] = "rksdmmc@ff520000",
+ [BROM_BOOTSOURCE_SD] = "rksdmmc@ff500000",
+};
+
static struct mm_region rk3328_mem_map[] = {
{
.virt = 0x0UL,
@@ -32,20 +45,56 @@
struct mm_region *mem_map = rk3328_mem_map;
-int dram_init_banksize(void)
+int arch_cpu_init(void)
{
- size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);
+#ifdef CONFIG_SPL_BUILD
+ /* We do some SoC one time setting here. */
- /* Reserve 0x200000 for ATF bl31 */
- gd->bd->bi_dram[0].start = 0x200000;
- gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start;
-
+ /* Disable the ddr secure region setting to make it non-secure */
+ rk_setreg(FW_DDR_CON_REG, 0x200);
+#endif
return 0;
}
-int arch_cpu_init(void)
+void board_debug_uart_init(void)
{
- /* We do some SoC one time setting here. */
+ struct rk3328_grf_regs * const grf = (void *)GRF_BASE;
+ struct rk_uart * const uart = (void *)UART2_BASE;
+ enum{
+ GPIO2A0_SEL_SHIFT = 0,
+ GPIO2A0_SEL_MASK = 3 << GPIO2A0_SEL_SHIFT,
+ GPIO2A0_UART2_TX_M1 = 1,
- return 0;
+ GPIO2A1_SEL_SHIFT = 2,
+ GPIO2A1_SEL_MASK = 3 << GPIO2A1_SEL_SHIFT,
+ GPIO2A1_UART2_RX_M1 = 1,
+ };
+ enum {
+ IOMUX_SEL_UART2_SHIFT = 0,
+ IOMUX_SEL_UART2_MASK = 3 << IOMUX_SEL_UART2_SHIFT,
+ IOMUX_SEL_UART2_M0 = 0,
+ IOMUX_SEL_UART2_M1,
+ };
+
+ /* uart_sel_clk default select 24MHz */
+ writel((3 << (8 + 16)) | (2 << 8), CRU_BASE + 0x148);
+
+ /* init uart baud rate 1500000 */
+ writel(0x83, &uart->lcr);
+ writel(0x1, &uart->rbr);
+ writel(0x3, &uart->lcr);
+
+ /* Enable early UART2 */
+ rk_clrsetreg(&grf->com_iomux,
+ IOMUX_SEL_UART2_MASK,
+ IOMUX_SEL_UART2_M1 << IOMUX_SEL_UART2_SHIFT);
+ rk_clrsetreg(&grf->gpio2a_iomux,
+ GPIO2A0_SEL_MASK,
+ GPIO2A0_UART2_TX_M1 << GPIO2A0_SEL_SHIFT);
+ rk_clrsetreg(&grf->gpio2a_iomux,
+ GPIO2A1_SEL_MASK,
+ GPIO2A1_UART2_RX_M1 << GPIO2A1_SEL_SHIFT);
+
+ /* enable FIFO */
+ writel(0x1, &uart->sfe);
}
diff --git a/arch/arm/mach-rockchip/rk3368-board-spl.c b/arch/arm/mach-rockchip/rk3368-board-spl.c
deleted file mode 100644
index c651193..0000000
--- a/arch/arm/mach-rockchip/rk3368-board-spl.c
+++ /dev/null
@@ -1,47 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
- */
-
-#include <common.h>
-#include <debug_uart.h>
-#include <dm.h>
-#include <ram.h>
-#include <spl.h>
-#include <asm/io.h>
-#include <asm/arch-rockchip/periph.h>
-
-void board_init_f(ulong dummy)
-{
- struct udevice *dev;
- int ret;
-
- ret = spl_early_init();
- if (ret) {
- debug("spl_early_init() failed: %d\n", ret);
- hang();
- }
-
- preloader_console_init();
-
- ret = uclass_get_device(UCLASS_RAM, 0, &dev);
- if (ret) {
- debug("DRAM init failed: %d\n", ret);
- return;
- }
-}
-
-u32 spl_boot_device(void)
-{
- return BOOT_DEVICE_MMC1;
-}
-
-#ifdef CONFIG_SPL_LOAD_FIT
-int board_fit_config_name_match(const char *name)
-{
- /* Just empty function now - can't decide what to choose */
- debug("%s: %s\n", __func__, name);
-
- return 0;
-}
-#endif
diff --git a/arch/arm/mach-rockchip/rk3368-board-tpl.c b/arch/arm/mach-rockchip/rk3368-board-tpl.c
deleted file mode 100644
index dc65a02..0000000
--- a/arch/arm/mach-rockchip/rk3368-board-tpl.c
+++ /dev/null
@@ -1,123 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
- */
-
-#include <common.h>
-#include <debug_uart.h>
-#include <dm.h>
-#include <ram.h>
-#include <spl.h>
-#include <syscon.h>
-#include <asm/io.h>
-#include <asm/arch-rockchip/bootrom.h>
-#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/cru_rk3368.h>
-#include <asm/arch-rockchip/hardware.h>
-#include <asm/arch-rockchip/timer.h>
-
-/*
- * The SPL (and also the full U-Boot stage on the RK3368) will run in
- * secure mode (i.e. EL3) and an ATF will eventually be booted before
- * starting up the operating system... so we can initialize the SGRF
- * here and rely on the ATF installing the final (secure) policy
- * later.
- */
-static inline uintptr_t sgrf_soc_con_addr(unsigned no)
-{
- const uintptr_t SGRF_BASE =
- (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
-
- return SGRF_BASE + sizeof(u32) * no;
-}
-
-static inline uintptr_t sgrf_busdmac_addr(unsigned no)
-{
- const uintptr_t SGRF_BASE =
- (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
- const uintptr_t SGRF_BUSDMAC_OFFSET = 0x100;
- const uintptr_t SGRF_BUSDMAC_BASE = SGRF_BASE + SGRF_BUSDMAC_OFFSET;
-
- return SGRF_BUSDMAC_BASE + sizeof(u32) * no;
-}
-
-static void sgrf_init(void)
-{
- struct rk3368_cru * const cru =
- (struct rk3368_cru * const)rockchip_get_cru();
- const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0);
- const u16 SGRF_BUSDMAC_CON0_SEC = BIT(2);
- const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12);
-
- /* Set all configurable IP to 'non secure'-mode */
- rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC);
- rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC);
- rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC);
-
- /*
- * From rockchip-uboot/arch/arm/cpu/armv8/rk33xx/cpu.c
- * Original comment: "ddr space set no secure mode"
- */
- rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC);
- rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC);
- rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC);
-
- /* Set 'secure dma' to 'non secure'-mode */
- rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC);
- rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC);
-
- dsb(); /* barrier */
-
- rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ);
- rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ);
-
- dsb(); /* barrier */
- udelay(10);
-
- rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ);
- rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ);
-}
-
-void board_init_f(ulong dummy)
-{
- struct udevice *dev;
- int ret;
-
-#ifdef CONFIG_DEBUG_UART
- /*
- * Debug UART can be used from here if required:
- *
- * debug_uart_init();
- * printch('a');
- * printhex8(0x1234);
- * printascii("string");
- */
- debug_uart_init();
- printascii("U-Boot TPL board init\n");
-#endif
-
- ret = spl_early_init();
- if (ret) {
- debug("spl_early_init() failed: %d\n", ret);
- hang();
- }
-
- /* Reset security, so we can use DMA in the MMC drivers */
- sgrf_init();
-
- ret = uclass_get_device(UCLASS_RAM, 0, &dev);
- if (ret) {
- debug("DRAM init failed: %d\n", ret);
- return;
- }
-}
-
-void board_return_to_bootrom(void)
-{
- back_to_bootrom(BROM_BOOT_NEXTSTAGE);
-}
-
-u32 spl_boot_device(void)
-{
- return BOOT_DEVICE_BOOTROM;
-}
diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig
index 325572a..d6ca5f1 100644
--- a/arch/arm/mach-rockchip/rk3368/Kconfig
+++ b/arch/arm/mach-rockchip/rk3368/Kconfig
@@ -42,9 +42,21 @@
sensor STK3410.
endchoice
+config ROCKCHIP_BOOT_MODE_REG
+ default 0xff738200
+
config SYS_SOC
default "rk3368"
+config SYS_MALLOC_F_LEN
+ default 0x2000
+
+config SPL_LIBCOMMON_SUPPORT
+ default y
+
+config SPL_LIBGENERIC_SUPPORT
+ default y
+
source "board/theobroma-systems/lion_rk3368/Kconfig"
source "board/rockchip/sheep_rk3368/Kconfig"
source "board/geekbuying/geekbox/Kconfig"
@@ -53,4 +65,13 @@
config SPL_LDSCRIPT
default "arch/arm/cpu/armv8/u-boot-spl.lds"
+config TPL_MAX_SIZE
+ default 28672
+
+config TPL_STACK
+ default 0xff8cffff
+
+config TPL_TEXT_BASE
+ default 0xff8c1000
+
endif
diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c b/arch/arm/mach-rockchip/rk3368/rk3368.c
index f06d277..7ccd417 100644
--- a/arch/arm/mach-rockchip/rk3368/rk3368.c
+++ b/arch/arm/mach-rockchip/rk3368/rk3368.c
@@ -5,12 +5,14 @@
*/
#include <common.h>
+#include <syscon.h>
#include <asm/armv8/mmu.h>
#include <asm/io.h>
+#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rk3368.h>
#include <asm/arch-rockchip/grf_rk3368.h>
-#include <syscon.h>
+#include <asm/arch-rockchip/hardware.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -51,16 +53,10 @@
struct mm_region *mem_map = rk3368_mem_map;
-int dram_init_banksize(void)
-{
- size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);
-
- /* Reserve 0x200000 for ATF bl31 */
- gd->bd->bi_dram[0].start = 0x200000;
- gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start;
-
- return 0;
-}
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+ [BROM_BOOTSOURCE_EMMC] = "dwmmc@ff0f0000",
+ [BROM_BOOTSOURCE_SD] = "dwmmc@ff0c0000",
+};
#ifdef CONFIG_ARCH_EARLY_INIT_R
static int mcu_init(void)
@@ -97,6 +93,78 @@
}
#endif
+#ifdef CONFIG_SPL_BUILD
+/*
+ * The SPL (and also the full U-Boot stage on the RK3368) will run in
+ * secure mode (i.e. EL3) and an ATF will eventually be booted before
+ * starting up the operating system... so we can initialize the SGRF
+ * here and rely on the ATF installing the final (secure) policy
+ * later.
+ */
+static inline uintptr_t sgrf_soc_con_addr(unsigned int no)
+{
+ const uintptr_t SGRF_BASE =
+ (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
+
+ return SGRF_BASE + sizeof(u32) * no;
+}
+
+static inline uintptr_t sgrf_busdmac_addr(unsigned int no)
+{
+ const uintptr_t SGRF_BASE =
+ (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
+ const uintptr_t SGRF_BUSDMAC_OFFSET = 0x100;
+ const uintptr_t SGRF_BUSDMAC_BASE = SGRF_BASE + SGRF_BUSDMAC_OFFSET;
+
+ return SGRF_BUSDMAC_BASE + sizeof(u32) * no;
+}
+
+static void sgrf_init(void)
+{
+ struct rk3368_cru * const cru =
+ (struct rk3368_cru * const)rockchip_get_cru();
+ const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0);
+ const u16 SGRF_BUSDMAC_CON0_SEC = BIT(2);
+ const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12);
+
+ /* Set all configurable IP to 'non secure'-mode */
+ rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC);
+ rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC);
+ rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC);
+
+ /*
+ * From rockchip-uboot/arch/arm/cpu/armv8/rk33xx/cpu.c
+ * Original comment: "ddr space set no secure mode"
+ */
+ rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC);
+ rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC);
+ rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC);
+
+ /* Set 'secure dma' to 'non secure'-mode */
+ rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC);
+ rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC);
+
+ dsb(); /* barrier */
+
+ rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ);
+ rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ);
+
+ dsb(); /* barrier */
+ udelay(10);
+
+ rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ);
+ rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ);
+}
+
+int arch_cpu_init(void)
+{
+ /* Reset security, so we can use DMA in the MMC drivers */
+ sgrf_init();
+
+ return 0;
+}
+#endif
+
#ifdef CONFIG_DEBUG_UART_BOARD_INIT
void board_debug_uart_init(void)
{
diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c
deleted file mode 100644
index 890d800..0000000
--- a/arch/arm/mach-rockchip/rk3399-board-spl.c
+++ /dev/null
@@ -1,276 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
- */
-
-#include <common.h>
-#include <debug_uart.h>
-#include <dm.h>
-#include <ram.h>
-#include <spl.h>
-#include <spl_gpio.h>
-#include <syscon.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/arch-rockchip/bootrom.h>
-#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/cru_rk3399.h>
-#include <asm/arch-rockchip/grf_rk3399.h>
-#include <asm/arch-rockchip/hardware.h>
-#include <asm/arch-rockchip/periph.h>
-#include <asm/arch-rockchip/sys_proto.h>
-#include <power/regulator.h>
-#include <dm/pinctrl.h>
-
-void board_return_to_bootrom(void)
-{
- back_to_bootrom(BROM_BOOT_NEXTSTAGE);
-}
-
-static const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
- [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe330000",
- [BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d0000",
- [BROM_BOOTSOURCE_SD] = "/dwmmc@fe320000",
-};
-
-const char *board_spl_was_booted_from(void)
-{
- u32 bootdevice_brom_id = readl(RK3399_BROM_BOOTSOURCE_ID_ADDR);
- const char *bootdevice_ofpath = NULL;
-
- if (bootdevice_brom_id < ARRAY_SIZE(boot_devices))
- bootdevice_ofpath = boot_devices[bootdevice_brom_id];
-
- if (bootdevice_ofpath)
- debug("%s: brom_bootdevice_id %x maps to '%s'\n",
- __func__, bootdevice_brom_id, bootdevice_ofpath);
- else
- debug("%s: failed to resolve brom_bootdevice_id %x\n",
- __func__, bootdevice_brom_id);
-
- return bootdevice_ofpath;
-}
-
-u32 spl_boot_device(void)
-{
- u32 boot_device = BOOT_DEVICE_MMC1;
-
- if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM))
- return BOOT_DEVICE_BOOTROM;
-
- return boot_device;
-}
-
-const char *spl_decode_boot_device(u32 boot_device)
-{
- int i;
- static const struct {
- u32 boot_device;
- const char *ofpath;
- } spl_boot_devices_tbl[] = {
- { BOOT_DEVICE_MMC1, "/dwmmc@fe320000" },
- { BOOT_DEVICE_MMC2, "/sdhci@fe330000" },
- { BOOT_DEVICE_SPI, "/spi@ff1d0000" },
- };
-
- for (i = 0; i < ARRAY_SIZE(spl_boot_devices_tbl); ++i)
- if (spl_boot_devices_tbl[i].boot_device == boot_device)
- return spl_boot_devices_tbl[i].ofpath;
-
- return NULL;
-}
-
-void spl_perform_fixups(struct spl_image_info *spl_image)
-{
- void *blob = spl_image->fdt_addr;
- const char *boot_ofpath;
- int chosen;
-
- /*
- * Inject the ofpath of the device the full U-Boot (or Linux in
- * Falcon-mode) was booted from into the FDT, if a FDT has been
- * loaded at the same time.
- */
- if (!blob)
- return;
-
- boot_ofpath = spl_decode_boot_device(spl_image->boot_device);
- if (!boot_ofpath) {
- pr_err("%s: could not map boot_device to ofpath\n", __func__);
- return;
- }
-
- chosen = fdt_find_or_add_subnode(blob, 0, "chosen");
- if (chosen < 0) {
- pr_err("%s: could not find/create '/chosen'\n", __func__);
- return;
- }
- fdt_setprop_string(blob, chosen,
- "u-boot,spl-boot-device", boot_ofpath);
-}
-
-#define TIMER_CHN10_BASE 0xff8680a0
-#define TIMER_END_COUNT_L 0x00
-#define TIMER_END_COUNT_H 0x04
-#define TIMER_INIT_COUNT_L 0x10
-#define TIMER_INIT_COUNT_H 0x14
-#define TIMER_CONTROL_REG 0x1c
-
-#define TIMER_EN 0x1
-#define TIMER_FMODE (0 << 1)
-#define TIMER_RMODE (1 << 1)
-
-void secure_timer_init(void)
-{
- writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L);
- writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H);
- writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L);
- writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H);
- writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
-}
-
-
-void board_init_f(ulong dummy)
-{
- struct udevice *pinctrl;
- struct udevice *dev;
- struct rk3399_pmusgrf_regs *sgrf;
- struct rk3399_grf_regs *grf;
- int ret;
-
-#ifdef CONFIG_DEBUG_UART
- debug_uart_init();
-
-# ifdef CONFIG_TARGET_CHROMEBOOK_BOB
- int sum, i;
-
- /*
- * Add a delay and ensure that the compiler does not optimise this out.
- * This is needed since the power rails tail a while to turn on, and
- * we get garbage serial output otherwise.
- */
- sum = 0;
- for (i = 0; i < 150000; i++)
- sum += i;
- gru_dummy_function(sum);
-#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
-
- /*
- * Debug UART can be used from here if required:
- *
- * debug_uart_init();
- * printch('a');
- * printhex8(0x1234);
- * printascii("string");
- */
- debug("U-Boot SPL board init\n");
-#endif
-
- ret = spl_early_init();
- if (ret) {
- debug("spl_early_init() failed: %d\n", ret);
- hang();
- }
-
- /*
- * Disable DDR and SRAM security regions.
- *
- * As we are entered from the BootROM, the region from
- * 0x0 through 0xfffff (i.e. the first MB of memory) will
- * be protected. This will cause issues with the DW_MMC
- * driver, which tries to DMA from/to the stack (likely)
- * located in this range.
- */
- sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
- rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);
- rk_clrreg(&sgrf->slv_secure_con4, 0x2000);
-
- /* eMMC clock generator: disable the clock multipilier */
- grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
- rk_clrreg(&grf->emmccore_con[11], 0x0ff);
-
- secure_timer_init();
-
- ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
- if (ret) {
- pr_err("Pinctrl init failed: %d\n", ret);
- return;
- }
-
- ret = uclass_get_device(UCLASS_RAM, 0, &dev);
- if (ret) {
- pr_err("DRAM init failed: %d\n", ret);
- return;
- }
-}
-
-#if defined(SPL_GPIO_SUPPORT)
-static void rk3399_force_power_on_reset(void)
-{
- ofnode node;
- struct gpio_desc sysreset_gpio;
-
- debug("%s: trying to force a power-on reset\n", __func__);
-
- node = ofnode_path("/config");
- if (!ofnode_valid(node)) {
- debug("%s: no /config node?\n", __func__);
- return;
- }
-
- if (gpio_request_by_name_nodev(node, "sysreset-gpio", 0,
- &sysreset_gpio, GPIOD_IS_OUT)) {
- debug("%s: could not find a /config/sysreset-gpio\n", __func__);
- return;
- }
-
- dm_gpio_set_value(&sysreset_gpio, 1);
-}
-#endif
-
-void spl_board_init(void)
-{
-#if defined(SPL_GPIO_SUPPORT)
- struct rk3399_cru *cru = rockchip_get_cru();
-
- /*
- * The RK3399 resets only 'almost all logic' (see also in the TRM
- * "3.9.4 Global software reset"), when issuing a software reset.
- * This may cause issues during boot-up for some configurations of
- * the application software stack.
- *
- * To work around this, we test whether the last reset reason was
- * a power-on reset and (if not) issue an overtemp-reset to reset
- * the entire module.
- *
- * While this was previously fixed by modifying the various places
- * that could generate a software reset (e.g. U-Boot's sysreset
- * driver, the ATF or Linux), we now have it here to ensure that
- * we no longer have to track this through the various components.
- */
- if (cru->glb_rst_st != 0)
- rk3399_force_power_on_reset();
-#endif
-
-#if defined(SPL_DM_REGULATOR)
- /*
- * Turning the eMMC and SPI back on (if disabled via the Qseven
- * BIOS_ENABLE) signal is done through a always-on regulator).
- */
- if (regulators_enable_boot_on(false))
- debug("%s: Cannot enable boot on regulator\n", __func__);
-#endif
-
- preloader_console_init();
-}
-
-#ifdef CONFIG_SPL_LOAD_FIT
-int board_fit_config_name_match(const char *name)
-{
- /* Just empty function now - can't decide what to choose */
- debug("%s: %s\n", __func__, name);
-
- return 0;
-}
-#endif
diff --git a/arch/arm/mach-rockchip/rk3399-board-tpl.c b/arch/arm/mach-rockchip/rk3399-board-tpl.c
deleted file mode 100644
index 4a30124..0000000
--- a/arch/arm/mach-rockchip/rk3399-board-tpl.c
+++ /dev/null
@@ -1,91 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2019 Rockchip Electronics Co., Ltd
- */
-
-#include <common.h>
-#include <debug_uart.h>
-#include <dm.h>
-#include <ram.h>
-#include <spl.h>
-#include <version.h>
-#include <asm/io.h>
-#include <asm/arch-rockchip/bootrom.h>
-
-#define TIMER_CHN10_BASE 0xff8680a0
-#define TIMER_END_COUNT_L 0x00
-#define TIMER_END_COUNT_H 0x04
-#define TIMER_INIT_COUNT_L 0x10
-#define TIMER_INIT_COUNT_H 0x14
-#define TIMER_CONTROL_REG 0x1c
-
-#define TIMER_EN 0x1
-#define TIMER_FMODE (0 << 1)
-#define TIMER_RMODE (1 << 1)
-
-void secure_timer_init(void)
-{
- writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L);
- writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H);
- writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L);
- writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H);
- writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
-}
-
-void board_init_f(ulong dummy)
-{
- struct udevice *dev;
- int ret;
-
-#ifdef CONFIG_DEBUG_UART
- debug_uart_init();
- /*
- * Debug UART can be used from here if required:
- *
- * debug_uart_init();
- * printch('a');
- * printhex8(0x1234);
- * printascii("string");
- */
- debug("U-Boot TPL board init\n");
-#endif
- ret = spl_early_init();
- if (ret) {
- debug("spl_early_init() failed: %d\n", ret);
- hang();
- }
-
- secure_timer_init();
-
- ret = uclass_get_device(UCLASS_RAM, 0, &dev);
- if (ret) {
- pr_err("DRAM init failed: %d\n", ret);
- return;
- }
-}
-
-void board_return_to_bootrom(void)
-{
- back_to_bootrom(BROM_BOOT_NEXTSTAGE);
-}
-
-u32 spl_boot_device(void)
-{
- return BOOT_DEVICE_BOOTROM;
-}
-
-void spl_board_init(void)
-{
- puts("\nU-Boot TPL " PLAIN_VERSION " (" U_BOOT_DATE " - "
- U_BOOT_TIME " " U_BOOT_TZ ")\n");
-}
-
-#ifdef CONFIG_SPL_LOAD_FIT
-int board_fit_config_name_match(const char *name)
-{
- /* Just empty function now - can't decide what to choose */
- debug("%s: %s\n", __func__, name);
-
- return 0;
-}
-#endif
diff --git a/arch/arm/mach-rockchip/rk3399-board.c b/arch/arm/mach-rockchip/rk3399-board.c
deleted file mode 100644
index 443c87c..0000000
--- a/arch/arm/mach-rockchip/rk3399-board.c
+++ /dev/null
@@ -1,13 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2017 Rockchip Electronics Co., Ltd
- */
-
-#include <common.h>
-#include <asm/arch-rockchip/boot_mode.h>
-
-int board_late_init(void)
-{
- setup_boot_mode();
- return 0;
-}
diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig
index 2c5c93c..6660d05 100644
--- a/arch/arm/mach-rockchip/rk3399/Kconfig
+++ b/arch/arm/mach-rockchip/rk3399/Kconfig
@@ -64,11 +64,32 @@
endchoice
+config ROCKCHIP_BOOT_MODE_REG
+ default 0xff320300
+
config SYS_SOC
default "rk3399"
config SYS_MALLOC_F_LEN
- default 0x0800
+ default 0x4000
+
+config SPL_LIBCOMMON_SUPPORT
+ default y
+
+config SPL_LIBGENERIC_SUPPORT
+ default y
+
+config TPL_LDSCRIPT
+ default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
+
+config TPL_MAX_SIZE
+ default 188416
+
+config TPL_STACK
+ default 0xff8effff
+
+config TPL_TEXT_BASE
+ default 0xff8c2000
source "board/rockchip/evb_rk3399/Kconfig"
source "board/theobroma-systems/puma_rk3399/Kconfig"
diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c
index e1f9f8b..863024d 100644
--- a/arch/arm/mach-rockchip/rk3399/rk3399.c
+++ b/arch/arm/mach-rockchip/rk3399/rk3399.c
@@ -4,18 +4,29 @@
*/
#include <common.h>
+#include <spl.h>
#include <spl_gpio.h>
+#include <syscon.h>
#include <asm/armv8/mmu.h>
#include <asm/io.h>
+#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/gpio.h>
#include <asm/arch-rockchip/grf_rk3399.h>
#include <asm/arch-rockchip/hardware.h>
+#include <power/regulator.h>
DECLARE_GLOBAL_DATA_PTR;
#define GRF_EMMCCORE_CON11 0xff77f02c
#define GRF_BASE 0xff770000
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+ [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe330000",
+ [BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d0000",
+ [BROM_BOOTSOURCE_SD] = "/dwmmc@fe320000",
+};
+
static struct mm_region rk3399_mem_map[] = {
{
.virt = 0x0UL,
@@ -38,24 +49,59 @@
struct mm_region *mem_map = rk3399_mem_map;
-int dram_init_banksize(void)
+#ifdef CONFIG_SPL_BUILD
+
+#define TIMER_END_COUNT_L 0x00
+#define TIMER_END_COUNT_H 0x04
+#define TIMER_INIT_COUNT_L 0x10
+#define TIMER_INIT_COUNT_H 0x14
+#define TIMER_CONTROL_REG 0x1c
+
+#define TIMER_EN 0x1
+#define TIMER_FMODE BIT(0)
+#define TIMER_RMODE BIT(1)
+
+void rockchip_stimer_init(void)
{
- size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);
+ /* If Timer already enabled, don't re-init it */
+ u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
- /* Reserve 0x200000 for ATF bl31 */
- gd->bd->bi_dram[0].start = 0x200000;
- gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start;
+ if (reg & TIMER_EN)
+ return;
- return 0;
+ writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_END_COUNT_L);
+ writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_END_COUNT_H);
+ writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_INIT_COUNT_L);
+ writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_INIT_COUNT_H);
+ writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + \
+ TIMER_CONTROL_REG);
}
+#endif
int arch_cpu_init(void)
{
- /* We do some SoC one time setting here. */
- struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
- /* Emmc clock generator: disable the clock multipilier */
+#ifdef CONFIG_SPL_BUILD
+ struct rk3399_pmusgrf_regs *sgrf;
+ struct rk3399_grf_regs *grf;
+
+ /*
+ * Disable DDR and SRAM security regions.
+ *
+ * As we are entered from the BootROM, the region from
+ * 0x0 through 0xfffff (i.e. the first MB of memory) will
+ * be protected. This will cause issues with the DW_MMC
+ * driver, which tries to DMA from/to the stack (likely)
+ * located in this range.
+ */
+ sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
+ rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);
+ rk_clrreg(&sgrf->slv_secure_con4, 0x2000);
+
+ /* eMMC clock generator: disable the clock multipilier */
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
rk_clrreg(&grf->emmccore_con[11], 0x0ff);
+#endif
return 0;
}
@@ -117,3 +163,111 @@
#endif
}
#endif
+
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+const char *spl_decode_boot_device(u32 boot_device)
+{
+ int i;
+ static const struct {
+ u32 boot_device;
+ const char *ofpath;
+ } spl_boot_devices_tbl[] = {
+ { BOOT_DEVICE_MMC1, "/dwmmc@fe320000" },
+ { BOOT_DEVICE_MMC2, "/sdhci@fe330000" },
+ { BOOT_DEVICE_SPI, "/spi@ff1d0000" },
+ };
+
+ for (i = 0; i < ARRAY_SIZE(spl_boot_devices_tbl); ++i)
+ if (spl_boot_devices_tbl[i].boot_device == boot_device)
+ return spl_boot_devices_tbl[i].ofpath;
+
+ return NULL;
+}
+
+void spl_perform_fixups(struct spl_image_info *spl_image)
+{
+ void *blob = spl_image->fdt_addr;
+ const char *boot_ofpath;
+ int chosen;
+
+ /*
+ * Inject the ofpath of the device the full U-Boot (or Linux in
+ * Falcon-mode) was booted from into the FDT, if a FDT has been
+ * loaded at the same time.
+ */
+ if (!blob)
+ return;
+
+ boot_ofpath = spl_decode_boot_device(spl_image->boot_device);
+ if (!boot_ofpath) {
+ pr_err("%s: could not map boot_device to ofpath\n", __func__);
+ return;
+ }
+
+ chosen = fdt_find_or_add_subnode(blob, 0, "chosen");
+ if (chosen < 0) {
+ pr_err("%s: could not find/create '/chosen'\n", __func__);
+ return;
+ }
+ fdt_setprop_string(blob, chosen,
+ "u-boot,spl-boot-device", boot_ofpath);
+}
+
+#if defined(SPL_GPIO_SUPPORT)
+static void rk3399_force_power_on_reset(void)
+{
+ ofnode node;
+ struct gpio_desc sysreset_gpio;
+
+ debug("%s: trying to force a power-on reset\n", __func__);
+
+ node = ofnode_path("/config");
+ if (!ofnode_valid(node)) {
+ debug("%s: no /config node?\n", __func__);
+ return;
+ }
+
+ if (gpio_request_by_name_nodev(node, "sysreset-gpio", 0,
+ &sysreset_gpio, GPIOD_IS_OUT)) {
+ debug("%s: could not find a /config/sysreset-gpio\n", __func__);
+ return;
+ }
+
+ dm_gpio_set_value(&sysreset_gpio, 1);
+}
+#endif
+
+void spl_board_init(void)
+{
+#if defined(SPL_GPIO_SUPPORT)
+ struct rk3399_cru *cru = rockchip_get_cru();
+
+ /*
+ * The RK3399 resets only 'almost all logic' (see also in the TRM
+ * "3.9.4 Global software reset"), when issuing a software reset.
+ * This may cause issues during boot-up for some configurations of
+ * the application software stack.
+ *
+ * To work around this, we test whether the last reset reason was
+ * a power-on reset and (if not) issue an overtemp-reset to reset
+ * the entire module.
+ *
+ * While this was previously fixed by modifying the various places
+ * that could generate a software reset (e.g. U-Boot's sysreset
+ * driver, the ATF or Linux), we now have it here to ensure that
+ * we no longer have to track this through the various components.
+ */
+ if (cru->glb_rst_st != 0)
+ rk3399_force_power_on_reset();
+#endif
+
+#if defined(SPL_DM_REGULATOR)
+ /*
+ * Turning the eMMC and SPI back on (if disabled via the Qseven
+ * BIOS_ENABLE) signal is done through a always-on regulator).
+ */
+ if (regulators_enable_boot_on(false))
+ debug("%s: Cannot enable boot on regulator\n", __func__);
+#endif
+}
+#endif
diff --git a/arch/arm/mach-rockchip/rk_timer.c b/arch/arm/mach-rockchip/rk_timer.c
deleted file mode 100644
index 29d379f..0000000
--- a/arch/arm/mach-rockchip/rk_timer.c
+++ /dev/null
@@ -1,40 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2015 Rockchip Electronics Co., Ltd
- */
-
-#include <common.h>
-#include <asm/arch-rockchip/timer.h>
-#include <asm/io.h>
-#include <linux/types.h>
-
-struct rk_timer * const timer_ptr = (void *)CONFIG_SYS_TIMER_BASE;
-
-static uint64_t rockchip_get_ticks(void)
-{
- uint64_t timebase_h, timebase_l;
-
- timebase_l = readl(&timer_ptr->timer_curr_value0);
- timebase_h = readl(&timer_ptr->timer_curr_value1);
-
- return timebase_h << 32 | timebase_l;
-}
-
-void rockchip_udelay(unsigned int usec)
-{
- uint64_t tmp;
-
- /* get timestamp */
- tmp = rockchip_get_ticks() + usec_to_tick(usec);
-
- /* loop till event */
- while (rockchip_get_ticks() < tmp+1)
- ;
-}
-
-void rockchip_timer_init(void)
-{
- writel(0xffffffff, &timer_ptr->timer_load_count0);
- writel(0xffffffff, &timer_ptr->timer_load_count1);
- writel(1, &timer_ptr->timer_ctrl_reg);
-}
diff --git a/arch/arm/mach-rockchip/rv1108-board.c b/arch/arm/mach-rockchip/rv1108-board.c
deleted file mode 100644
index 3412f2c..0000000
--- a/arch/arm/mach-rockchip/rv1108-board.c
+++ /dev/null
@@ -1,81 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2015 Google, Inc
- */
-
-#include <common.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
-#include <usb.h>
-#include <usb/dwc2_udc.h>
-
-static struct dwc2_plat_otg_data rv1108_otg_data = {
- .rx_fifo_sz = 512,
- .np_tx_fifo_sz = 16,
- .tx_fifo_sz = 128,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
- const void *blob = gd->fdt_blob;
- bool matched = false;
- int node, phy_node;
- u32 grf_phy_offset;
- const char *mode;
-
- /* find the usb_otg node */
- node = fdt_node_offset_by_compatible(blob, -1, "rockchip,rk3066-usb");
- while (node > 0) {
- mode = fdt_getprop(blob, node, "dr_mode", NULL);
- if (mode && strcmp(mode, "otg") == 0) {
- matched = true;
- break;
- }
-
- node = fdt_node_offset_by_compatible(blob, node,
- "rockchip,rk3066-usb");
- }
-
- if (!matched) {
- debug("usb_otg device not found\n");
- return -ENODEV;
- }
-
- rv1108_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
-
- node = fdtdec_lookup_phandle(blob, node, "phys");
- if (node <= 0) {
- debug("phys node not found\n");
- return -ENODEV;
- }
-
- phy_node = fdt_parent_offset(blob, node);
- if (phy_node <= 0) {
- debug("usb phy node not found\n");
- return -ENODEV;
- }
-
- rv1108_otg_data.phy_of_node = phy_node;
- grf_phy_offset = fdtdec_get_addr(blob, node, "reg");
-
- /* find the grf node */
- node = fdt_node_offset_by_compatible(blob, -1,
- "rockchip,rv1108-grf");
- if (node <= 0) {
- debug("grf node not found\n");
- return -ENODEV;
- }
-
- rv1108_otg_data.regs_phy = grf_phy_offset + fdtdec_get_addr(blob, node,
- "reg");
-
- return dwc2_udc_probe(&rv1108_otg_data);
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
- return 0;
-}
-#endif
diff --git a/arch/arm/mach-rockchip/rv1108/Kconfig b/arch/arm/mach-rockchip/rv1108/Kconfig
index e3a63b8..a12216d 100644
--- a/arch/arm/mach-rockchip/rv1108/Kconfig
+++ b/arch/arm/mach-rockchip/rv1108/Kconfig
@@ -1,5 +1,8 @@
if ROCKCHIP_RV1108
+choice
+ prompt "RV1108 board select"
+
config TARGET_EVB_RV1108
bool "EVB_RV1108"
help
@@ -22,6 +25,11 @@
help
RV1108 ELGIN is a board based on the Rockchip RV1108.
+endchoice
+
+config ROCKCHIP_BOOT_MODE_REG
+ default 0x10300580
+
config SYS_SOC
default "rv1108"
diff --git a/arch/arm/mach-rockchip/rv1108/rv1108.c b/arch/arm/mach-rockchip/rv1108/rv1108.c
index 66aeb3f..6362af9 100644
--- a/arch/arm/mach-rockchip/rv1108/rv1108.c
+++ b/arch/arm/mach-rockchip/rv1108/rv1108.c
@@ -3,13 +3,3 @@
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
* Author: Andy Yan <andy.yan@rock-chips.com>
*/
-
-#include <common.h>
-
-#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
-void enable_caches(void)
-{
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
-}
-#endif
diff --git a/arch/arm/mach-rockchip/sdram_common.c b/arch/arm/mach-rockchip/sdram_common.c
index 8684dbd..22a4aca 100644
--- a/arch/arm/mach-rockchip/sdram_common.c
+++ b/arch/arm/mach-rockchip/sdram_common.c
@@ -11,6 +11,69 @@
#include <dm/uclass-internal.h>
DECLARE_GLOBAL_DATA_PTR;
+
+#define TRUST_PARAMETER_OFFSET (34 * 1024 * 1024)
+
+struct tos_parameter_t {
+ u32 version;
+ u32 checksum;
+ struct {
+ char name[8];
+ s64 phy_addr;
+ u32 size;
+ u32 flags;
+ } tee_mem;
+ struct {
+ char name[8];
+ s64 phy_addr;
+ u32 size;
+ u32 flags;
+ } drm_mem;
+ s64 reserve[8];
+};
+
+int dram_init_banksize(void)
+{
+ size_t top = min((unsigned long)(gd->ram_size + CONFIG_SYS_SDRAM_BASE),
+ gd->ram_top);
+
+#ifdef CONFIG_ARM64
+ /* Reserve 0x200000 for ATF bl31 */
+ gd->bd->bi_dram[0].start = 0x200000;
+ gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
+#else
+#ifdef CONFIG_SPL_OPTEE
+ struct tos_parameter_t *tos_parameter;
+
+ tos_parameter = (struct tos_parameter_t *)(CONFIG_SYS_SDRAM_BASE +
+ TRUST_PARAMETER_OFFSET);
+
+ if (tos_parameter->tee_mem.flags == 1) {
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr
+ - CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr +
+ tos_parameter->tee_mem.size;
+ gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
+ + top - gd->bd->bi_dram[1].start;
+ } else {
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = 0x8400000;
+ /* Reserve 32M for OPTEE with TA */
+ gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
+ + gd->bd->bi_dram[0].size + 0x2000000;
+ gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
+ + top - gd->bd->bi_dram[1].start;
+ }
+#else
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
+#endif
+#endif
+
+ return 0;
+}
+
size_t rockchip_sdram_size(phys_addr_t reg)
{
u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c
index 0e485de..fa8e096 100644
--- a/arch/arm/mach-rockchip/spl-boot-order.c
+++ b/arch/arm/mach-rockchip/spl-boot-order.c
@@ -8,7 +8,7 @@
#include <mmc.h>
#include <spl.h>
-#if CONFIG_IS_ENABLED(OF_CONTROL)
+#if CONFIG_IS_ENABLED(OF_LIBFDT)
/**
* spl_node_to_boot_device() - maps from a DT-node to a SPL boot device
* @node: of_offset of the node
@@ -134,7 +134,7 @@
/* Try to resolve the config item (or alias) as a path */
node = fdt_path_offset(blob, conf);
if (node < 0) {
- debug("%s: could not find %s in FDT", __func__, conf);
+ debug("%s: could not find %s in FDT\n", __func__, conf);
continue;
}
diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c
new file mode 100644
index 0000000..33137cc
--- /dev/null
+++ b/arch/arm/mach-rockchip/spl.c
@@ -0,0 +1,154 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <dm.h>
+#include <ram.h>
+#include <spl.h>
+#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/sdram.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_return_to_bootrom(void)
+{
+ back_to_bootrom(BROM_BOOT_NEXTSTAGE);
+}
+
+__weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+};
+
+const char *board_spl_was_booted_from(void)
+{
+ u32 bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR);
+ const char *bootdevice_ofpath = NULL;
+
+ if (bootdevice_brom_id < ARRAY_SIZE(boot_devices))
+ bootdevice_ofpath = boot_devices[bootdevice_brom_id];
+
+ if (bootdevice_ofpath)
+ debug("%s: brom_bootdevice_id %x maps to '%s'\n",
+ __func__, bootdevice_brom_id, bootdevice_ofpath);
+ else
+ debug("%s: failed to resolve brom_bootdevice_id %x\n",
+ __func__, bootdevice_brom_id);
+
+ return bootdevice_ofpath;
+}
+
+u32 spl_boot_device(void)
+{
+ u32 boot_device = BOOT_DEVICE_MMC1;
+
+#if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
+ defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
+ defined(CONFIG_TARGET_CHROMEBOOK_MINNIE)
+ return BOOT_DEVICE_SPI;
+#endif
+ if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM))
+ return BOOT_DEVICE_BOOTROM;
+
+ return boot_device;
+}
+
+u32 spl_boot_mode(const u32 boot_device)
+{
+ return MMCSD_MODE_RAW;
+}
+
+#if !defined(CONFIG_ROCKCHIP_RK3188)
+#define TIMER_LOAD_COUNT_L 0x00
+#define TIMER_LOAD_COUNT_H 0x04
+#define TIMER_CONTROL_REG 0x10
+#define TIMER_EN 0x1
+#define TIMER_FMODE BIT(0)
+#define TIMER_RMODE BIT(1)
+
+__weak void rockchip_stimer_init(void)
+{
+ /* If Timer already enabled, don't re-init it */
+ u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
+
+ if (reg & TIMER_EN)
+ return;
+#ifndef CONFIG_ARM64
+ asm volatile("mcr p15, 0, %0, c14, c0, 0"
+ : : "r"(COUNTER_FREQUENCY));
+#endif
+ writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
+ writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
+ writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
+ writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE +
+ TIMER_CONTROL_REG);
+}
+#endif
+
+__weak int board_early_init_f(void)
+{
+ return 0;
+}
+
+__weak int arch_cpu_init(void)
+{
+ return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+ int ret;
+#if !defined(CONFIG_SUPPORT_TPL) || defined(CONFIG_SPL_OS_BOOT)
+ struct udevice *dev;
+#endif
+
+#ifdef CONFIG_DEBUG_UART
+ /*
+ * Debug UART can be used from here if required:
+ *
+ * debug_uart_init();
+ * printch('a');
+ * printhex8(0x1234);
+ * printascii("string");
+ */
+ debug_uart_init();
+ debug("\nspl:debug uart enabled in %s\n", __func__);
+#endif
+
+ board_early_init_f();
+
+ ret = spl_early_init();
+ if (ret) {
+ printf("spl_early_init() failed: %d\n", ret);
+ hang();
+ }
+ arch_cpu_init();
+#if !defined(CONFIG_SUPPORT_TPL) || defined(CONFIG_SPL_OS_BOOT)
+ debug("\nspl:init dram\n");
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ printf("DRAM init failed: %d\n", ret);
+ return;
+ }
+#endif
+#if !defined(CONFIG_ROCKCHIP_RK3188)
+ rockchip_stimer_init();
+#endif
+#ifdef CONFIG_SYS_ARCH_TIMER
+ /* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */
+ timer_init();
+#endif
+ preloader_console_init();
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ /* Just empty function now - can't decide what to choose */
+ debug("%s: %s\n", __func__, name);
+
+ return 0;
+}
+#endif
diff --git a/arch/arm/mach-rockchip/tpl.c b/arch/arm/mach-rockchip/tpl.c
new file mode 100644
index 0000000..55f6e92
--- /dev/null
+++ b/arch/arm/mach-rockchip/tpl.c
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <dm.h>
+#include <ram.h>
+#include <spl.h>
+#include <version.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/bootrom.h>
+
+#define TIMER_LOAD_COUNT_L 0x00
+#define TIMER_LOAD_COUNT_H 0x04
+#define TIMER_CONTROL_REG 0x10
+#define TIMER_EN 0x1
+#define TIMER_FMODE BIT(0)
+#define TIMER_RMODE BIT(1)
+
+__weak void rockchip_stimer_init(void)
+{
+ /* If Timer already enabled, don't re-init it */
+ u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
+
+ if (reg & TIMER_EN)
+ return;
+
+#ifndef CONFIG_ARM64
+ asm volatile("mcr p15, 0, %0, c14, c0, 0"
+ : : "r"(COUNTER_FREQUENCY));
+#endif
+
+ writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
+ writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
+ writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
+ writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE +
+ TIMER_CONTROL_REG);
+}
+
+void board_init_f(ulong dummy)
+{
+ struct udevice *dev;
+ int ret;
+
+#if defined(CONFIG_DEBUG_UART) && defined(CONFIG_TPL_SERIAL_SUPPORT)
+ /*
+ * Debug UART can be used from here if required:
+ *
+ * debug_uart_init();
+ * printch('a');
+ * printhex8(0x1234);
+ * printascii("string");
+ */
+ debug_uart_init();
+#ifdef CONFIG_TPL_BANNER_PRINT
+ printascii("\nU-Boot TPL " PLAIN_VERSION " (" U_BOOT_DATE " - " \
+ U_BOOT_TIME ")\n");
+#endif
+#endif
+ ret = spl_early_init();
+ if (ret) {
+ debug("spl_early_init() failed: %d\n", ret);
+ hang();
+ }
+
+ /* Init secure timer */
+ rockchip_stimer_init();
+ /* Init ARM arch timer in arch/arm/cpu/ */
+ timer_init();
+
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ printf("DRAM init failed: %d\n", ret);
+ return;
+ }
+}
+
+void board_return_to_bootrom(void)
+{
+ back_to_bootrom(BROM_BOOT_NEXTSTAGE);
+}
+
+u32 spl_boot_device(void)
+{
+ return BOOT_DEVICE_BOOTROM;
+}
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index e667204..fc1181c 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -8,7 +8,6 @@
obj-y += board.o
obj-y += clock_manager.o
obj-y += misc.o
-obj-y += reset_manager.o
ifdef CONFIG_TARGET_SOCFPGA_GEN5
obj-y += clock_manager_gen5.o
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 42beaec..6ad037e 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -11,6 +11,7 @@
void socfpga_per_reset(u32 reset, int set);
void socfpga_per_reset_all(void);
+#define RSTMGR_CTRL_SWCOLDRSTREQ_LSB 0
#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
/*
diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
index 71547d8..31681b7 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -5,6 +5,7 @@
#include <common.h>
#include <asm/io.h>
+#include <env.h>
#include <errno.h>
#include <fdtdec.h>
#include <linux/libfdt.h>
diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
index 29abc4a..0a5fab1 100644
--- a/arch/arm/mach-socfpga/misc_s10.c
+++ b/arch/arm/mach-socfpga/misc_s10.c
@@ -6,6 +6,7 @@
#include <altera.h>
#include <common.h>
+#include <env.h>
#include <errno.h>
#include <fdtdec.h>
#include <miiphy.h>
diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c
deleted file mode 100644
index e0a01ed..0000000
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ /dev/null
@@ -1,41 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2013 Altera Corporation <www.altera.com>
- */
-
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/reset_manager.h>
-
-#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
-#include <asm/arch/mailbox_s10.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if !defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
-static const struct socfpga_reset_manager *reset_manager_base =
- (void *)SOCFPGA_RSTMGR_ADDRESS;
-#endif
-
-/*
- * Write the reset manager register to cause reset
- */
-void reset_cpu(ulong addr)
-{
- /* request a warm reset */
-#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
- puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n");
- mbox_reset_cold();
-#else
- writel(1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB,
- &reset_manager_base->ctrl);
-#endif
- /*
- * infinite loop here as watchdog will trigger and reset
- * the processor
- */
- while (1)
- ;
-}
diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index 87b76b4..47e6370 100644
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -79,8 +79,6 @@
writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN,
&sysmgr_regs->eccgrp_ocram);
- memset(__bss_start, 0, __bss_end - __bss_start);
-
socfpga_sdram_remap_zero();
socfpga_pl310_clear();
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
index d9ad6b4..c9bc084 100644
--- a/arch/arm/mach-stm32mp/Kconfig
+++ b/arch/arm/mach-stm32mp/Kconfig
@@ -16,8 +16,9 @@
select SPL_REGMAP
select SPL_DM_RESET
select SPL_SERIAL_SUPPORT
+ select SPL_SPI_LOAD
select SPL_SYSCON
- select SPL_WATCHDOG_SUPPORT
+ select SPL_WATCHDOG_SUPPORT if WATCHDOG
imply BOOTSTAGE_STASH if SPL_BOOTSTAGE
imply SPL_BOOTSTAGE if BOOTSTAGE
imply SPL_DISPLAY_PRINT
@@ -38,14 +39,19 @@
select CPU_V7A
select CPU_V7_HAS_NONSEC if !STM32MP1_TRUSTED
select CPU_V7_HAS_VIRT
+ select OF_BOARD_SETUP
select PINCTRL_STM32
select STM32_RCC
select STM32_RESET
+ select STM32_SERIAL
select SYS_ARCH_TIMER
imply BOOTCOUNT_LIMIT
imply BOOTSTAGE
imply CMD_BOOTCOUNT
imply CMD_BOOTSTAGE
+ imply DISABLE_CONSOLE
+ imply PRE_CONSOLE_BUFFER
+ imply SILENT_CONSOLE
imply SYSRESET_PSCI if STM32MP1_TRUSTED
imply SYSRESET_SYSCON if !STM32MP1_TRUSTED
help
@@ -62,7 +68,17 @@
Say Y here to enable boot with TF-A
Trusted boot chain is :
BootRom => TF-A.stm32 (clock & DDR) => U-Boot.stm32
- TF-A monitor provides proprietary smc to manage secure devices
+ TF-A monitor provides proprietary SMC to manage secure devices
+
+config STM32MP1_OPTEE
+ bool "Support trusted boot with TF-A and OP-TEE"
+ depends on STM32MP1_TRUSTED
+ default n
+ help
+ Say Y here to enable boot with TF-A and OP-TEE
+ Trusted boot chain is :
+ BootRom => TF-A.stm32 (clock & DDR) => OP-TEE => U-Boot.stm32
+ OP-TEE monitor provides ST SMC to access to secure resources
config SYS_TEXT_BASE
prompt "U-Boot base address"
@@ -83,6 +99,28 @@
Partition on the second MMC to load U-Boot from when the MMC is being
used in raw mode
+config STM32_ETZPC
+ bool "STM32 Extended TrustZone Protection"
+ depends on TARGET_STM32MP1
+ default y
+ help
+ Say y to enable STM32 Extended TrustZone Protection
+
+config CMD_STM32KEY
+ bool "command stm32key to fuse public key hash"
+ default y
+ depends on CMD_FUSE
+ help
+ fuse public key hash in corresponding fuse used to authenticate
+ binary.
+
+
+config PRE_CON_BUF_ADDR
+ default 0xC02FF000
+
+config PRE_CON_BUF_SZ
+ default 4096
+
config BOOTSTAGE_STASH_ADDR
default 0xC3000000
diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile
index 1493914..eee39c2 100644
--- a/arch/arm/mach-stm32mp/Makefile
+++ b/arch/arm/mach-stm32mp/Makefile
@@ -11,9 +11,9 @@
obj-y += spl.o
else
obj-y += bsec.o
-ifndef CONFIG_STM32MP1_TRUSTED
-obj-$(CONFIG_SYSRESET) += cmd_poweroff.o
-endif
-endif
+obj-$(CONFIG_CMD_STM32KEY) += cmd_stm32key.o
obj-$(CONFIG_ARMV7_PSCI) += psci.o
+endif
+
obj-$(CONFIG_$(SPL_)DM_REGULATOR) += pwr_regulator.o
+obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o
diff --git a/arch/arm/mach-stm32mp/bsec.c b/arch/arm/mach-stm32mp/bsec.c
index 0166649..a77c706 100644
--- a/arch/arm/mach-stm32mp/bsec.c
+++ b/arch/arm/mach-stm32mp/bsec.c
@@ -358,20 +358,19 @@
bool shadow = true;
int nb_otp = size / sizeof(u32);
int otp;
+ unsigned int offs = offset;
- if (offset >= STM32_BSEC_OTP_OFFSET) {
- offset -= STM32_BSEC_OTP_OFFSET;
+ if (offs >= STM32_BSEC_OTP_OFFSET) {
+ offs -= STM32_BSEC_OTP_OFFSET;
shadow = false;
}
- otp = offset / sizeof(u32);
- if (otp < 0 || (otp + nb_otp - 1) > BSEC_OTP_MAX_VALUE) {
- dev_err(dev, "wrong value for otp, max value : %i\n",
- BSEC_OTP_MAX_VALUE);
+ if (offs < 0 || (offs % 4) || (size % 4))
return -EINVAL;
- }
- for (i = otp; i < (otp + nb_otp); i++) {
+ otp = offs / sizeof(u32);
+
+ for (i = otp; i < (otp + nb_otp) && i <= BSEC_OTP_MAX_VALUE; i++) {
u32 *addr = &((u32 *)buf)[i - otp];
if (shadow)
@@ -382,7 +381,10 @@
if (ret)
break;
}
- return ret;
+ if (ret)
+ return ret;
+ else
+ return (i - otp) * 4;
}
static int stm32mp_bsec_write(struct udevice *dev, int offset,
@@ -393,20 +395,19 @@
bool shadow = true;
int nb_otp = size / sizeof(u32);
int otp;
+ unsigned int offs = offset;
- if (offset >= STM32_BSEC_OTP_OFFSET) {
- offset -= STM32_BSEC_OTP_OFFSET;
+ if (offs >= STM32_BSEC_OTP_OFFSET) {
+ offs -= STM32_BSEC_OTP_OFFSET;
shadow = false;
}
- otp = offset / sizeof(u32);
- if (otp < 0 || (otp + nb_otp - 1) > BSEC_OTP_MAX_VALUE) {
- dev_err(dev, "wrong value for otp, max value : %d\n",
- BSEC_OTP_MAX_VALUE);
+ if (offs < 0 || (offs % 4) || (size % 4))
return -EINVAL;
- }
- for (i = otp; i < otp + nb_otp; i++) {
+ otp = offs / sizeof(u32);
+
+ for (i = otp; i < otp + nb_otp && i <= BSEC_OTP_MAX_VALUE; i++) {
u32 *val = &((u32 *)buf)[i - otp];
if (shadow)
@@ -416,7 +417,10 @@
if (ret)
break;
}
- return ret;
+ if (ret)
+ return ret;
+ else
+ return (i - otp) * 4;
}
static const struct misc_ops stm32mp_bsec_ops = {
diff --git a/arch/arm/mach-stm32mp/cmd_poweroff.c b/arch/arm/mach-stm32mp/cmd_poweroff.c
deleted file mode 100644
index f54dd1d..0000000
--- a/arch/arm/mach-stm32mp/cmd_poweroff.c
+++ /dev/null
@@ -1,24 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
-/*
- * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
- */
-
-#include <common.h>
-#include <command.h>
-#include <sysreset.h>
-
-int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int ret;
-
- puts("poweroff ...\n");
- mdelay(100);
-
- ret = sysreset_walk(SYSRESET_POWER);
-
- if (ret == -EINPROGRESS)
- mdelay(1000);
-
- /*NOTREACHED when power off*/
- return CMD_RET_FAILURE;
-}
diff --git a/arch/arm/mach-stm32mp/cmd_stm32key.c b/arch/arm/mach-stm32mp/cmd_stm32key.c
new file mode 100644
index 0000000..f1f26e7
--- /dev/null
+++ b/arch/arm/mach-stm32mp/cmd_stm32key.c
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
+ */
+
+#include <common.h>
+#include <command.h>
+#include <console.h>
+#include <misc.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+
+#define STM32_OTP_HASH_KEY_START 24
+#define STM32_OTP_HASH_KEY_SIZE 8
+
+static void read_hash_value(u32 addr)
+{
+ int i;
+
+ for (i = 0; i < STM32_OTP_HASH_KEY_SIZE; i++) {
+ printf("OTP value %i: %x\n", STM32_OTP_HASH_KEY_START + i,
+ __be32_to_cpu(*(u32 *)addr));
+ addr += 4;
+ }
+}
+
+static void fuse_hash_value(u32 addr, bool print)
+{
+ struct udevice *dev;
+ u32 word, val;
+ int i, ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_GET_DRIVER(stm32mp_bsec),
+ &dev);
+ if (ret) {
+ pr_err("Can't find stm32mp_bsec driver\n");
+ return;
+ }
+
+ for (i = 0; i < STM32_OTP_HASH_KEY_SIZE; i++) {
+ if (print)
+ printf("Fuse OTP %i : %x\n",
+ STM32_OTP_HASH_KEY_START + i,
+ __be32_to_cpu(*(u32 *)addr));
+
+ word = STM32_OTP_HASH_KEY_START + i;
+ val = __be32_to_cpu(*(u32 *)addr);
+ misc_write(dev, STM32_BSEC_OTP(word), &val, 4);
+
+ addr += 4;
+ }
+}
+
+static int confirm_prog(void)
+{
+ puts("Warning: Programming fuses is an irreversible operation!\n"
+ " This may brick your system.\n"
+ " Use this command only if you are sure of what you are doing!\n"
+ "\nReally perform this fuse programming? <y/N>\n");
+
+ if (confirm_yesno())
+ return 1;
+
+ puts("Fuse programming aborted\n");
+ return 0;
+}
+
+static int do_stm32key(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ u32 addr;
+ const char *op = argc >= 2 ? argv[1] : NULL;
+ int confirmed = argc > 3 && !strcmp(argv[2], "-y");
+
+ argc -= 2 + confirmed;
+ argv += 2 + confirmed;
+
+ if (argc < 1)
+ return CMD_RET_USAGE;
+
+ addr = simple_strtoul(argv[0], NULL, 16);
+ if (!addr)
+ return CMD_RET_USAGE;
+
+ if (!strcmp(op, "read"))
+ read_hash_value(addr);
+
+ if (!strcmp(op, "fuse")) {
+ if (!confirmed && !confirm_prog())
+ return CMD_RET_FAILURE;
+ fuse_hash_value(addr, !confirmed);
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(stm32key, 4, 1, do_stm32key,
+ "Fuse ST Hash key",
+ "read <addr>: Read the hash store at addr in memory\n"
+ "stm32key fuse [-y] <addr> : Fuse hash store at addr in otp\n");
diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c
index e1a0a13..a46e843 100644
--- a/arch/arm/mach-stm32mp/cpu.c
+++ b/arch/arm/mach-stm32mp/cpu.c
@@ -5,7 +5,7 @@
#include <common.h>
#include <clk.h>
#include <debug_uart.h>
-#include <environment.h>
+#include <env.h>
#include <misc.h>
#include <asm/io.h>
#include <asm/arch/stm32.h>
@@ -78,11 +78,6 @@
#define PKG_SHIFT 27
#define PKG_MASK GENMASK(2, 0)
-#define PKG_AA_LBGA448 4
-#define PKG_AB_LBGA354 3
-#define PKG_AC_TFBGA361 2
-#define PKG_AD_TFBGA257 1
-
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
#ifndef CONFIG_STM32MP1_TRUSTED
static void security_init(void)
@@ -277,7 +272,7 @@
}
/* Get Package options from OTP */
-static u32 get_cpu_package(void)
+u32 get_cpu_package(void)
{
return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK);
}
@@ -366,7 +361,7 @@
u32 boot_ctx = readl(TAMP_BOOT_CONTEXT);
u32 boot_mode =
(boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT;
- int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
+ unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK);
struct udevice *dev;
int alias;
diff --git a/arch/arm/mach-stm32mp/fdt.c b/arch/arm/mach-stm32mp/fdt.c
new file mode 100644
index 0000000..82c430b
--- /dev/null
+++ b/arch/arm/mach-stm32mp/fdt.c
@@ -0,0 +1,223 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
+ */
+
+#include <common.h>
+#include <fdt_support.h>
+#include <asm/arch/sys_proto.h>
+#include <dt-bindings/pinctrl/stm32-pinfunc.h>
+#include <linux/io.h>
+
+#define ETZPC_DECPROT(n) (STM32_ETZPC_BASE + 0x10 + 4 * (n))
+#define ETZPC_DECPROT_NB 6
+
+#define DECPROT_MASK 0x03
+#define NB_PROT_PER_REG 0x10
+#define DECPROT_NB_BITS 2
+
+#define DECPROT_SECURED 0x00
+#define DECPROT_WRITE_SECURE 0x01
+#define DECPROT_MCU_ISOLATION 0x02
+#define DECPROT_NON_SECURED 0x03
+
+#define ETZPC_RESERVED 0xffffffff
+
+static const u32 stm32mp1_ip_addr[] = {
+ 0x5c008000, /* 00 stgenc */
+ 0x54000000, /* 01 bkpsram */
+ 0x5c003000, /* 02 iwdg1 */
+ 0x5c000000, /* 03 usart1 */
+ 0x5c001000, /* 04 spi6 */
+ 0x5c002000, /* 05 i2c4 */
+ ETZPC_RESERVED, /* 06 reserved */
+ 0x54003000, /* 07 rng1 */
+ 0x54002000, /* 08 hash1 */
+ 0x54001000, /* 09 cryp1 */
+ 0x5a003000, /* 0A ddrctrl */
+ 0x5a004000, /* 0B ddrphyc */
+ 0x5c009000, /* 0C i2c6 */
+ ETZPC_RESERVED, /* 0D reserved */
+ ETZPC_RESERVED, /* 0E reserved */
+ ETZPC_RESERVED, /* 0F reserved */
+ 0x40000000, /* 10 tim2 */
+ 0x40001000, /* 11 tim3 */
+ 0x40002000, /* 12 tim4 */
+ 0x40003000, /* 13 tim5 */
+ 0x40004000, /* 14 tim6 */
+ 0x40005000, /* 15 tim7 */
+ 0x40006000, /* 16 tim12 */
+ 0x40007000, /* 17 tim13 */
+ 0x40008000, /* 18 tim14 */
+ 0x40009000, /* 19 lptim1 */
+ 0x4000a000, /* 1A wwdg1 */
+ 0x4000b000, /* 1B spi2 */
+ 0x4000c000, /* 1C spi3 */
+ 0x4000d000, /* 1D spdifrx */
+ 0x4000e000, /* 1E usart2 */
+ 0x4000f000, /* 1F usart3 */
+ 0x40010000, /* 20 uart4 */
+ 0x40011000, /* 21 uart5 */
+ 0x40012000, /* 22 i2c1 */
+ 0x40013000, /* 23 i2c2 */
+ 0x40014000, /* 24 i2c3 */
+ 0x40015000, /* 25 i2c5 */
+ 0x40016000, /* 26 cec */
+ 0x40017000, /* 27 dac */
+ 0x40018000, /* 28 uart7 */
+ 0x40019000, /* 29 uart8 */
+ ETZPC_RESERVED, /* 2A reserved */
+ ETZPC_RESERVED, /* 2B reserved */
+ 0x4001c000, /* 2C mdios */
+ ETZPC_RESERVED, /* 2D reserved */
+ ETZPC_RESERVED, /* 2E reserved */
+ ETZPC_RESERVED, /* 2F reserved */
+ 0x44000000, /* 30 tim1 */
+ 0x44001000, /* 31 tim8 */
+ ETZPC_RESERVED, /* 32 reserved */
+ 0x44003000, /* 33 usart6 */
+ 0x44004000, /* 34 spi1 */
+ 0x44005000, /* 35 spi4 */
+ 0x44006000, /* 36 tim15 */
+ 0x44007000, /* 37 tim16 */
+ 0x44008000, /* 38 tim17 */
+ 0x44009000, /* 39 spi5 */
+ 0x4400a000, /* 3A sai1 */
+ 0x4400b000, /* 3B sai2 */
+ 0x4400c000, /* 3C sai3 */
+ 0x4400d000, /* 3D dfsdm */
+ 0x4400e000, /* 3E tt_fdcan */
+ ETZPC_RESERVED, /* 3F reserved */
+ 0x50021000, /* 40 lptim2 */
+ 0x50022000, /* 41 lptim3 */
+ 0x50023000, /* 42 lptim4 */
+ 0x50024000, /* 43 lptim5 */
+ 0x50027000, /* 44 sai4 */
+ 0x50025000, /* 45 vrefbuf */
+ 0x4c006000, /* 46 dcmi */
+ 0x4c004000, /* 47 crc2 */
+ 0x48003000, /* 48 adc */
+ 0x4c002000, /* 49 hash2 */
+ 0x4c003000, /* 4A rng2 */
+ 0x4c005000, /* 4B cryp2 */
+ ETZPC_RESERVED, /* 4C reserved */
+ ETZPC_RESERVED, /* 4D reserved */
+ ETZPC_RESERVED, /* 4E reserved */
+ ETZPC_RESERVED, /* 4F reserved */
+ ETZPC_RESERVED, /* 50 sram1 */
+ ETZPC_RESERVED, /* 51 sram2 */
+ ETZPC_RESERVED, /* 52 sram3 */
+ ETZPC_RESERVED, /* 53 sram4 */
+ ETZPC_RESERVED, /* 54 retram */
+ 0x49000000, /* 55 otg */
+ 0x48004000, /* 56 sdmmc3 */
+ 0x48005000, /* 57 dlybsd3 */
+ 0x48000000, /* 58 dma1 */
+ 0x48001000, /* 59 dma2 */
+ 0x48002000, /* 5A dmamux */
+ 0x58002000, /* 5B fmc */
+ 0x58003000, /* 5C qspi */
+ 0x58004000, /* 5D dlybq */
+ 0x5800a000, /* 5E eth */
+ ETZPC_RESERVED, /* 5F reserved */
+};
+
+/* fdt helper */
+static bool fdt_disable_subnode_by_address(void *fdt, int offset, u32 addr)
+{
+ int node;
+
+ for (node = fdt_first_subnode(fdt, offset);
+ node >= 0;
+ node = fdt_next_subnode(fdt, node)) {
+ if (addr == (u32)fdt_getprop(fdt, node, "reg", 0)) {
+ if (fdtdec_get_is_enabled(fdt, node)) {
+ fdt_status_disabled(fdt, node);
+
+ return true;
+ }
+ return false;
+ }
+ }
+
+ return false;
+}
+
+static int stm32_fdt_fixup_etzpc(void *fdt)
+{
+ const u32 *array;
+ int array_size, i;
+ int soc_node, offset, shift;
+ u32 addr, status, decprot[ETZPC_DECPROT_NB];
+
+ array = stm32mp1_ip_addr;
+ array_size = ARRAY_SIZE(stm32mp1_ip_addr);
+
+ for (i = 0; i < ETZPC_DECPROT_NB; i++)
+ decprot[i] = readl(ETZPC_DECPROT(i));
+
+ soc_node = fdt_path_offset(fdt, "/soc");
+ if (soc_node < 0)
+ return soc_node;
+
+ for (i = 0; i < array_size; i++) {
+ offset = i / NB_PROT_PER_REG;
+ shift = (i % NB_PROT_PER_REG) * DECPROT_NB_BITS;
+ status = (decprot[offset] >> shift) & DECPROT_MASK;
+ addr = array[i];
+
+ debug("ETZPC: 0x%08x decprot %d=%d\n", addr, i, status);
+
+ if (addr == ETZPC_RESERVED ||
+ status == DECPROT_NON_SECURED)
+ continue;
+
+ if (fdt_disable_subnode_by_address(fdt, soc_node, addr))
+ printf("ETZPC: 0x%08x node disabled, decprot %d=%d\n",
+ addr, i, status);
+ }
+
+ return 0;
+}
+
+/*
+ * This function is called right before the kernel is booted. "blob" is the
+ * device tree that will be passed to the kernel.
+ */
+int ft_system_setup(void *blob, bd_t *bd)
+{
+ int ret = 0;
+ u32 pkg;
+
+ if (CONFIG_IS_ENABLED(STM32_ETZPC)) {
+ ret = stm32_fdt_fixup_etzpc(blob);
+ if (ret)
+ return ret;
+ }
+
+ switch (get_cpu_package()) {
+ case PKG_AA_LBGA448:
+ pkg = STM32MP_PKG_AA;
+ break;
+ case PKG_AB_LBGA354:
+ pkg = STM32MP_PKG_AB;
+ break;
+ case PKG_AC_TFBGA361:
+ pkg = STM32MP_PKG_AC;
+ break;
+ case PKG_AD_TFBGA257:
+ pkg = STM32MP_PKG_AD;
+ break;
+ default:
+ pkg = 0;
+ break;
+ }
+ if (pkg) {
+ do_fixup_by_compat_u32(blob, "st,stm32mp157-pinctrl",
+ "st,package", pkg, false);
+ do_fixup_by_compat_u32(blob, "st,stm32mp157-z-pinctrl",
+ "st,package", pkg, false);
+ }
+
+ return ret;
+}
diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h
index 6795352..b3e9ccc 100644
--- a/arch/arm/mach-stm32mp/include/mach/stm32.h
+++ b/arch/arm/mach-stm32mp/include/mach/stm32.h
@@ -15,6 +15,7 @@
#define STM32_DBGMCU_BASE 0x50081000
#define STM32_TZC_BASE 0x5C006000
#define STM32_ETZPC_BASE 0x5C007000
+#define STM32_STGEN_BASE 0x5C008000
#define STM32_TAMP_BASE 0x5C00A000
#define STM32_USART1_BASE 0x5C000000
@@ -36,9 +37,7 @@
/* enumerated used to identify the SYSCON driver instance */
enum {
STM32MP_SYSCON_UNKNOWN,
- STM32MP_SYSCON_ETZPC,
STM32MP_SYSCON_PWR,
- STM32MP_SYSCON_STGEN,
STM32MP_SYSCON_SYSCFG,
};
@@ -95,6 +94,7 @@
#define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4)
#define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0)
#define TAMP_BOOT_FORCED_MASK GENMASK(7, 0)
+#define TAMP_BOOT_DEBUG_ON BIT(16)
enum forced_boot_mode {
BOOT_NORMAL = 0x00,
diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h
index 71a3ba7..99eefab 100644
--- a/arch/arm/mach-stm32mp/include/mach/sys_proto.h
+++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h
@@ -19,5 +19,14 @@
/* return CPU_REV constants */
u32 get_cpu_rev(void);
+
+/* Get Package options from OTP */
+u32 get_cpu_package(void);
+
+#define PKG_AA_LBGA448 4
+#define PKG_AB_LBGA354 3
+#define PKG_AC_TFBGA361 2
+#define PKG_AD_TFBGA257 1
+
/* return boot mode */
u32 get_bootmode(void);
diff --git a/arch/arm/mach-stm32mp/psci.c b/arch/arm/mach-stm32mp/psci.c
index 139bb09..1d91b2d 100644
--- a/arch/arm/mach-stm32mp/psci.c
+++ b/arch/arm/mach-stm32mp/psci.c
@@ -30,7 +30,7 @@
PSCI_AFFINITY_LEVEL_ON,
PSCI_AFFINITY_LEVEL_OFF};
-void __secure psci_set_state(int cpu, u8 state)
+static inline void psci_set_state(int cpu, u8 state)
{
psci_state[cpu] = state;
dsb();
@@ -67,7 +67,7 @@
writel(0xFFFFFFFF, TAMP_BACKUP_MAGIC_NUMBER);
}
-int __secure psci_features(u32 function_id, u32 psci_fid)
+s32 __secure psci_features(u32 function_id, u32 psci_fid)
{
switch (psci_fid) {
case ARM_PSCI_0_2_FN_PSCI_VERSION:
@@ -82,12 +82,12 @@
return ARM_PSCI_RET_NI;
}
-unsigned int __secure psci_version(u32 function_id)
+u32 __secure psci_version(void)
{
return ARM_PSCI_VER_1_0;
}
-int __secure psci_affinity_info(u32 function_id, u32 target_affinity,
+s32 __secure psci_affinity_info(u32 function_id, u32 target_affinity,
u32 lowest_affinity_level)
{
u32 cpu = target_affinity & MPIDR_AFF0;
@@ -104,7 +104,7 @@
return psci_state[cpu];
}
-int __secure psci_migrate_info_type(u32 function_id)
+u32 __secure psci_migrate_info_type(void)
{
/*
* in Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
@@ -116,7 +116,7 @@
return 2;
}
-int __secure psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc,
+s32 __secure psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc,
u32 context_id)
{
u32 cpu = target_cpu & MPIDR_AFF0;
@@ -161,7 +161,7 @@
return ARM_PSCI_RET_SUCCESS;
}
-int __secure psci_cpu_off(u32 function_id)
+s32 __secure psci_cpu_off(void)
{
u32 cpu;
@@ -181,7 +181,7 @@
wfi();
}
-void __secure psci_system_reset(u32 function_id)
+void __secure psci_system_reset(void)
{
/* System reset */
writel(RCC_MP_GRSTCSETR_MPSYSRST, RCC_MP_GRSTCSETR);
@@ -190,7 +190,7 @@
wfi();
}
-void __secure psci_system_off(u32 function_id)
+void __secure psci_system_off(void)
{
/* System Off is not managed, waiting user power off
* TODO: handle I2C write in PMIC Main Control register bit 0 = SWOFF
diff --git a/arch/arm/mach-stm32mp/syscon.c b/arch/arm/mach-stm32mp/syscon.c
index 242f834..6070837 100644
--- a/arch/arm/mach-stm32mp/syscon.c
+++ b/arch/arm/mach-stm32mp/syscon.c
@@ -9,9 +9,7 @@
#include <asm/arch/stm32.h>
static const struct udevice_id stm32mp_syscon_ids[] = {
- { .compatible = "st,stm32mp1-etzpc", .data = STM32MP_SYSCON_ETZPC },
{ .compatible = "st,stm32mp1-pwr", .data = STM32MP_SYSCON_PWR },
- { .compatible = "st,stm32-stgen", .data = STM32MP_SYSCON_STGEN },
{ .compatible = "st,stm32mp157-syscfg",
.data = STM32MP_SYSCON_SYSCFG },
{ }
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 1669e62..ffdf09f 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -300,6 +300,7 @@
select ARM64
select SUPPORT_SPL
select FIT
+ select PHY_SUN4I_USB
select SPL_LOAD_FIT
select DRAM_SUN50I_H6
@@ -340,7 +341,7 @@
This allows both the SPL and the U-Boot proper to be entered in
either mode and switch to AArch64 if needed.
-if SUNXI_DRAM_DW
+if SUNXI_DRAM_DW || DRAM_SUN50I_H6
config SUNXI_DRAM_DDR3
bool
@@ -370,6 +371,22 @@
This option is the LPDDR3 timing used by the stock boot0 by
Allwinner.
+config SUNXI_DRAM_H6_LPDDR3
+ bool "LPDDR3 DRAM chips on the H6 DRAM controller"
+ select SUNXI_DRAM_LPDDR3
+ depends on DRAM_SUN50I_H6
+ ---help---
+ This option is the LPDDR3 timing used by the stock boot0 by
+ Allwinner.
+
+config SUNXI_DRAM_H6_DDR3_1333
+ bool "DDR3-1333 boot0 timings on the H6 DRAM controller"
+ select SUNXI_DRAM_DDR3
+ depends on DRAM_SUN50I_H6
+ ---help---
+ This option is the DDR3 timing used by the boot0 on H6 TV boxes
+ which use a DDR3-1333 timing.
+
config SUNXI_DRAM_DDR2_V3S
bool "DDR2 found in V3s chip"
select SUNXI_DRAM_DDR2
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index 43a93e3..d129f33 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -39,4 +39,5 @@
obj-$(CONFIG_SUNXI_DRAM_DW) += dram_sunxi_dw.o
obj-$(CONFIG_SUNXI_DRAM_DW) += dram_timings/
obj-$(CONFIG_DRAM_SUN50I_H6) += dram_sun50i_h6.o
+obj-$(CONFIG_DRAM_SUN50I_H6) += dram_timings/
endif
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c
index 5da90a2..2a8275d 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c
@@ -32,33 +32,8 @@
* similar PHY is ZynqMP.
*/
-/*
- * The delay parameters below allow to allegedly specify delay times of some
- * unknown unit for each individual bit trace in each of the four data bytes
- * the 32-bit wide access consists of. Also three control signals can be
- * adjusted individually.
- */
-#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE)
-/* The eight data lines (DQn) plus DM, DQS, DQS/DM/DQ Output Enable and DQSN */
-#define WR_LINES_PER_BYTE_LANE (BITS_PER_BYTE + 4)
-/*
- * The eight data lines (DQn) plus DM, DQS, DQS/DM/DQ Output Enable, DQSN,
- * Termination and Power down
- */
-#define RD_LINES_PER_BYTE_LANE (BITS_PER_BYTE + 6)
-struct dram_para {
- u32 clk;
- enum sunxi_dram_type type;
- u8 cols;
- u8 rows;
- u8 ranks;
- const u8 dx_read_delays[NR_OF_BYTE_LANES][RD_LINES_PER_BYTE_LANE];
- const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE];
-};
-
static void mctl_sys_init(struct dram_para *para);
static void mctl_com_init(struct dram_para *para);
-static void mctl_set_timing_lpddr3(struct dram_para *para);
static void mctl_channel_init(struct dram_para *para);
static void mctl_core_init(struct dram_para *para)
@@ -67,7 +42,8 @@
mctl_com_init(para);
switch (para->type) {
case SUNXI_DRAM_TYPE_LPDDR3:
- mctl_set_timing_lpddr3(para);
+ case SUNXI_DRAM_TYPE_DDR3:
+ mctl_set_timing_params(para);
break;
default:
panic("Unsupported DRAM type!");
@@ -75,12 +51,14 @@
mctl_channel_init(para);
}
+/* PHY initialisation */
static void mctl_phy_pir_init(u32 val)
{
struct sunxi_mctl_phy_reg * const mctl_phy =
(struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
- writel(val | BIT(0), &mctl_phy->pir);
+ writel(val, &mctl_phy->pir);
+ writel(val | BIT(0), &mctl_phy->pir); /* Start initialisation. */
mctl_await_completion(&mctl_phy->pgsr[0], BIT(0), BIT(0));
}
@@ -169,125 +147,6 @@
MBUS_CONF(HDCP2, true, HIGH, 2, 100, 64, 32);
}
-static u32 mr_lpddr3[12] = {
- 0x00000000, 0x00000043, 0x0000001a, 0x00000001,
- 0x00000000, 0x00000000, 0x00000048, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000003,
-};
-
-/* TODO: flexible timing */
-static void mctl_set_timing_lpddr3(struct dram_para *para)
-{
- struct sunxi_mctl_ctl_reg * const mctl_ctl =
- (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
- struct sunxi_mctl_phy_reg * const mctl_phy =
- (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
-
- u8 tccd = 2;
- u8 tfaw = max(ns_to_t(50), 4);
- u8 trrd = max(ns_to_t(10), 2);
- u8 trcd = max(ns_to_t(24), 2);
- u8 trc = ns_to_t(70);
- u8 txp = max(ns_to_t(8), 2);
- u8 twtr = max(ns_to_t(8), 2);
- u8 trtp = max(ns_to_t(8), 2);
- u8 twr = max(ns_to_t(15), 2);
- u8 trp = ns_to_t(18);
- u8 tras = ns_to_t(42);
- u8 twtr_sa = ns_to_t(5);
- u8 tcksrea = ns_to_t(11);
- u16 trefi = ns_to_t(3900) / 32;
- u16 trfc = ns_to_t(210);
- u16 txsr = ns_to_t(220);
-
- if (CONFIG_DRAM_CLK % 400 == 0) {
- /* Round up these parameters */
- twtr_sa++;
- tcksrea++;
- }
-
- u8 tmrw = 5;
- u8 tmrd = 5;
- u8 tmod = 12;
- u8 tcke = 3;
- u8 tcksrx = 5;
- u8 tcksre = 5;
- u8 tckesr = 5;
- u8 trasmax = CONFIG_DRAM_CLK / 60;
- u8 txs = 4;
- u8 txsdll = 4;
- u8 txsabort = 4;
- u8 txsfast = 4;
-
- u8 tcl = 5; /* CL 10 */
- u8 tcwl = 3; /* CWL 6 */
- u8 t_rdata_en = twtr_sa + 8;
-
- u32 tdinit0 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
- u32 tdinit1 = (100 * CONFIG_DRAM_CLK) / 1000 + 1; /* 100ns */
- u32 tdinit2 = (11 * CONFIG_DRAM_CLK) + 1; /* 11us */
- u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
-
- u8 twtp = tcwl + 4 + twr + 1;
- /*
- * The code below for twr2rd and trd2wr follows the IP core's
- * document from ZynqMP and i.MX7. The BSP has both number
- * substracted by 2.
- */
- u8 twr2rd = tcwl + 4 + 1 + twtr;
- u8 trd2wr = tcl + 4 + (tcksrea >> 1) - tcwl + 1;
-
- /* set mode register */
- memcpy(mctl_phy->mr, mr_lpddr3, sizeof(mr_lpddr3));
-
- /* set DRAM timing */
- writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras,
- &mctl_ctl->dramtmg[0]);
- writel((txp << 16) | (trtp << 8) | trc, &mctl_ctl->dramtmg[1]);
- writel((tcwl << 24) | (tcl << 16) | (trd2wr << 8) | twr2rd,
- &mctl_ctl->dramtmg[2]);
- writel((tmrw << 20) | (tmrd << 12) | tmod, &mctl_ctl->dramtmg[3]);
- writel((trcd << 24) | (tccd << 16) | (trrd << 8) | trp,
- &mctl_ctl->dramtmg[4]);
- writel((tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | tcke,
- &mctl_ctl->dramtmg[5]);
- /* Value suggested by ZynqMP manual and used by libdram */
- writel((txp + 2) | 0x02020000, &mctl_ctl->dramtmg[6]);
- writel((txsfast << 24) | (txsabort << 16) | (txsdll << 8) | txs,
- &mctl_ctl->dramtmg[8]);
- writel(txsr, &mctl_ctl->dramtmg[14]);
-
- clrsetbits_le32(&mctl_ctl->init[0], (3 << 30), (1 << 30));
- writel(0, &mctl_ctl->dfimisc);
- clrsetbits_le32(&mctl_ctl->rankctl, 0xff0, 0x660);
-
- /*
- * Set timing registers of the PHY.
- * Note: the PHY is clocked 2x from the DRAM frequency.
- */
- writel((trrd << 25) | (tras << 17) | (trp << 9) | (trtp << 1),
- &mctl_phy->dtpr[0]);
- writel((tfaw << 17) | 0x28000400 | (tmrd << 1), &mctl_phy->dtpr[1]);
- writel(((txs << 6) - 1) | (tcke << 17), &mctl_phy->dtpr[2]);
- writel(((txsdll << 22) - (0x1 << 16)) | twtr_sa | (tcksrea << 8),
- &mctl_phy->dtpr[3]);
- writel((txp << 1) | (trfc << 17) | 0x800, &mctl_phy->dtpr[4]);
- writel((trc << 17) | (trcd << 9) | (twtr << 1), &mctl_phy->dtpr[5]);
- writel(0x0505, &mctl_phy->dtpr[6]);
-
- /* Configure DFI timing */
- writel(tcl | 0x2000200 | (t_rdata_en << 16) | 0x808000,
- &mctl_ctl->dfitmg0);
- writel(0x040201, &mctl_ctl->dfitmg1);
-
- /* Configure PHY timing */
- writel(tdinit0 | (tdinit1 << 20), &mctl_phy->ptr[3]);
- writel(tdinit2 | (tdinit3 << 18), &mctl_phy->ptr[4]);
-
- /* set refresh timing */
- writel((trefi << 16) | trfc, &mctl_ctl->rfshtmg);
-}
-
static void mctl_sys_init(struct dram_para *para)
{
struct sunxi_ccm_reg * const ccm =
@@ -426,14 +285,11 @@
mctl_set_addrmap(para);
setbits_le32(&mctl_com->cr, BIT(31));
- /*
- * This address is magic; it's in SID memory area, but there's no
- * known definition of it.
- * On my Pine H64 board it has content 7.
- */
- if (readl(0x03006100) == 7)
+
+ /* The bonding ID seems to be always 7. */
+ if (readl(SUNXI_SIDC_BASE + 0x100) == 7) /* bonding ID */
clrbits_le32(&mctl_com->cr, BIT(27));
- else if (readl(0x03006100) == 3)
+ else if (readl(SUNXI_SIDC_BASE + 0x100) == 3)
setbits_le32(&mctl_com->cr, BIT(27));
if (para->clk > 408)
@@ -444,22 +300,37 @@
reg_val = 0x3f00;
clrsetbits_le32(&mctl_com->unk_0x008, 0x3f00, reg_val);
- /* TODO: half DQ, non-LPDDR3 types */
- writel(MSTR_DEVICETYPE_LPDDR3 | MSTR_BUSWIDTH_FULL |
- MSTR_BURST_LENGTH(8) | MSTR_ACTIVE_RANKS(para->ranks) |
- 0x80000000, &mctl_ctl->mstr);
- writel(DCR_LPDDR3 | DCR_DDR8BANK | 0x400, &mctl_phy->dcr);
+ /* TODO: half DQ, DDR4 */
+ reg_val = MSTR_BUSWIDTH_FULL | MSTR_BURST_LENGTH(8) |
+ MSTR_ACTIVE_RANKS(para->ranks);
+ if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
+ reg_val |= MSTR_DEVICETYPE_LPDDR3;
+ if (para->type == SUNXI_DRAM_TYPE_DDR3)
+ reg_val |= MSTR_DEVICETYPE_DDR3 | MSTR_2TMODE;
+ writel(reg_val | BIT(31), &mctl_ctl->mstr);
+
+ if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
+ reg_val = DCR_LPDDR3 | DCR_DDR8BANK;
+ if (para->type == SUNXI_DRAM_TYPE_DDR3)
+ reg_val = DCR_DDR3 | DCR_DDR8BANK | DCR_DDR2T;
+ writel(reg_val | 0x400, &mctl_phy->dcr);
if (para->ranks == 2)
writel(0x0303, &mctl_ctl->odtmap);
else
writel(0x0201, &mctl_ctl->odtmap);
- /* TODO: non-LPDDR3 types */
- tmp = para->clk * 7 / 2000;
- reg_val = 0x0400;
- reg_val |= (tmp + 7) << 24;
- reg_val |= (((para->clk < 400) ? 3 : 4) - tmp) << 16;
+ /* TODO: DDR4 */
+ if (para->type == SUNXI_DRAM_TYPE_LPDDR3) {
+ tmp = para->clk * 7 / 2000;
+ reg_val = 0x0400;
+ reg_val |= (tmp + 7) << 24;
+ reg_val |= (((para->clk < 400) ? 3 : 4) - tmp) << 16;
+ } else if (para->type == SUNXI_DRAM_TYPE_DDR3) {
+ reg_val = 0x06000400; /* TODO?: Use CL - CWL value in [7:0] */
+ } else {
+ panic("Only (LP)DDR3 supported (type = %d)\n", para->type);
+ }
writel(reg_val, &mctl_ctl->odtcfg);
/* TODO: half DQ */
@@ -514,6 +385,9 @@
setbits_le32(&mctl_phy->pgcr[0], BIT(26));
udelay(1);
+ if (para->type != SUNXI_DRAM_TYPE_LPDDR3)
+ return;
+
for (i = 1; i < 14; i++) {
val = readl(&mctl_phy->acbdlr[i]);
val += 0x0a0a0a0a;
@@ -561,7 +435,8 @@
else
clrsetbits_le32(&mctl_phy->dtcr[1], 0x30000, 0x10000);
- clrbits_le32(&mctl_phy->dtcr[1], BIT(1));
+ if (sunxi_dram_is_lpddr(para->type))
+ clrbits_le32(&mctl_phy->dtcr[1], BIT(1));
if (para->ranks == 2) {
writel(0x00010001, &mctl_phy->rankidr);
writel(0x20000, &mctl_phy->odtcr);
@@ -570,8 +445,11 @@
writel(0x10000, &mctl_phy->odtcr);
}
- /* TODO: non-LPDDR3 types */
- clrsetbits_le32(&mctl_phy->dtcr[0], 0xF0000000, 0x10000040);
+ /* set bits [3:0] to 1? 0 not valid in ZynqMP d/s */
+ if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
+ clrsetbits_le32(&mctl_phy->dtcr[0], 0xF0000000, 0x10000040);
+ else
+ clrsetbits_le32(&mctl_phy->dtcr[0], 0xF0000000, 0x10000000);
if (para->clk <= 792) {
if (para->clk <= 672) {
if (para->clk <= 600)
@@ -601,12 +479,13 @@
writel(0x06060606, &mctl_phy->acbdlr[i]);
}
- /* TODO: non-LPDDR3 types */
- mctl_phy_pir_init(PIR_ZCAL | PIR_DCAL | PIR_PHYRST | PIR_DRAMINIT |
- PIR_QSGATE | PIR_RDDSKW | PIR_WRDSKW | PIR_RDEYE |
- PIR_WREYE);
+ val = PIR_ZCAL | PIR_DCAL | PIR_PHYRST | PIR_DRAMINIT | PIR_QSGATE |
+ PIR_RDDSKW | PIR_WRDSKW | PIR_RDEYE | PIR_WREYE;
+ if (para->type == SUNXI_DRAM_TYPE_DDR3)
+ val |= PIR_DRAMRST | PIR_WL;
+ mctl_phy_pir_init(val);
- /* TODO: non-LPDDR3 types */
+ /* TODO: DDR4 types ? */
for (i = 0; i < 4; i++)
writel(0x00000909, &mctl_phy->dx[i].gcr[5]);
@@ -662,7 +541,8 @@
panic("Error while initializing DRAM PHY!\n");
}
- clrsetbits_le32(&mctl_phy->dsgcr, 0xc0, 0x40);
+ if (sunxi_dram_is_lpddr(para->type))
+ clrsetbits_le32(&mctl_phy->dsgcr, 0xc0, 0x40);
clrbits_le32(&mctl_phy->pgcr[1], 0x40);
clrbits_le32(&mctl_ctl->dfimisc, BIT(0));
writel(1, &mctl_ctl->swctl);
@@ -714,29 +594,46 @@
return (1ULL << (para->cols + para->rows + 3)) * 4 * para->ranks;
}
-#define SUN50I_H6_DX_WRITE_DELAYS \
+#define SUN50I_H6_LPDDR3_DX_WRITE_DELAYS \
{{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 4, 0 }, \
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }}
-#define SUN50I_H6_DX_READ_DELAYS \
+#define SUN50I_H6_LPDDR3_DX_READ_DELAYS \
{{ 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \
{ 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \
{ 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \
{ 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }}
+#define SUN50I_H6_DDR3_DX_WRITE_DELAYS \
+ {{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }}
+#define SUN50I_H6_DDR3_DX_READ_DELAYS \
+ {{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
+ { 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }}
+
unsigned long sunxi_dram_init(void)
{
struct sunxi_mctl_com_reg * const mctl_com =
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
struct dram_para para = {
.clk = CONFIG_DRAM_CLK,
- .type = SUNXI_DRAM_TYPE_LPDDR3,
.ranks = 2,
.cols = 11,
.rows = 14,
- .dx_read_delays = SUN50I_H6_DX_READ_DELAYS,
- .dx_write_delays = SUN50I_H6_DX_WRITE_DELAYS,
+#ifdef CONFIG_SUNXI_DRAM_H6_LPDDR3
+ .type = SUNXI_DRAM_TYPE_LPDDR3,
+ .dx_read_delays = SUN50I_H6_LPDDR3_DX_READ_DELAYS,
+ .dx_write_delays = SUN50I_H6_LPDDR3_DX_WRITE_DELAYS,
+#elif defined(CONFIG_SUNXI_DRAM_H6_DDR3_1333)
+ .type = SUNXI_DRAM_TYPE_DDR3,
+ .dx_read_delays = SUN50I_H6_DDR3_DX_READ_DELAYS,
+ .dx_write_delays = SUN50I_H6_DDR3_DX_WRITE_DELAYS,
+#endif
};
unsigned long size;
diff --git a/arch/arm/mach-sunxi/dram_timings/Makefile b/arch/arm/mach-sunxi/dram_timings/Makefile
index 278a8a1..0deb991 100644
--- a/arch/arm/mach-sunxi/dram_timings/Makefile
+++ b/arch/arm/mach-sunxi/dram_timings/Makefile
@@ -1,3 +1,5 @@
obj-$(CONFIG_SUNXI_DRAM_DDR3_1333) += ddr3_1333.o
obj-$(CONFIG_SUNXI_DRAM_LPDDR3_STOCK) += lpddr3_stock.o
obj-$(CONFIG_SUNXI_DRAM_DDR2_V3S) += ddr2_v3s.o
+obj-$(CONFIG_SUNXI_DRAM_H6_LPDDR3) += h6_lpddr3.o
+obj-$(CONFIG_SUNXI_DRAM_H6_DDR3_1333) += h6_ddr3_1333.o
diff --git a/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c b/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c
new file mode 100644
index 0000000..611eaa3
--- /dev/null
+++ b/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c
@@ -0,0 +1,144 @@
+/*
+ * sun50i H6 DDR3-1333 timings, as programmed by Allwinner's boot0
+ * for some TV boxes with the H6 and DDR3 memory.
+ *
+ * The chips are probably able to be driven by a faster clock, but boot0
+ * uses a more conservative timing (as usual).
+ *
+ * (C) Copyright 2018,2019 Arm Ltd.
+ * based on previous work by:
+ * (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * References used:
+ * - JEDEC DDR3 SDRAM standard: JESD79-3F.pdf
+ * - Samsung K4B2G0446D datasheet
+ * - ZynqMP UG1087 register DDRC/PHY documentation
+ *
+ * Many thanks to Jernej Skrabec for contributing some fixes!
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+#include <asm/arch/cpu.h>
+
+/*
+ * Only the first four are used for DDR3(?)
+ * MR0: BL8, seq. read burst, no test, fast exit (DLL on), no DLL reset,
+ * CAS latency (CL): 11, write recovery (WR): 12
+ * MR1: DLL enabled, output strength RZQ/6, Rtt_norm RZQ/2,
+ * write levelling disabled, TDQS disabled, output buffer enabled
+ * MR2: manual full array self refresh, dynamic ODT off,
+ * CAS write latency (CWL): 8
+ */
+static u32 mr_ddr3[7] = {
+ 0x00001c70, 0x00000040, 0x00000018, 0x00000000,
+ 0x00000000, 0x00000400, 0x00000848,
+};
+
+/* TODO: flexible timing */
+void mctl_set_timing_params(struct dram_para *para)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+ struct sunxi_mctl_phy_reg * const mctl_phy =
+ (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
+ int i;
+
+ u8 tccd = 2; /* JEDEC: 4nCK */
+ u8 tfaw = ns_to_t(50); /* JEDEC: 30 ns w/ 1K pages */
+ u8 trrd = max(ns_to_t(6), 4); /* JEDEC: max(6 ns, 4nCK) */
+ u8 trcd = ns_to_t(15); /* JEDEC: 13.5 ns */
+ u8 trc = ns_to_t(53); /* JEDEC: 49.5 ns */
+ u8 txp = max(ns_to_t(6), 3); /* JEDEC: max(6 ns, 3nCK) */
+ u8 twtr = max(ns_to_t(8), 2); /* JEDEC: max(7.5 ns, 4nCK) */
+ u8 trtp = max(ns_to_t(8), 2); /* JEDEC: max(7.5 ns, 4nCK) */
+ u8 twr = ns_to_t(15); /* JEDEC: 15 ns */
+ u8 trp = ns_to_t(15); /* JEDEC: >= 13.75 ns */
+ u8 tras = ns_to_t(38); /* JEDEC >= 36 ns, <= 9*trefi */
+ u8 twtr_sa = 2; /* ? */
+ u8 tcksrea = 4; /* ? */
+ u16 trefi = ns_to_t(7800) / 32; /* JEDEC: 7.8us@Tcase <= 85C */
+ u16 trfc = ns_to_t(350); /* JEDEC: 160 ns for 2Gb */
+ u16 txsr = 4; /* ? */
+
+ u8 tmrw = 0; /* ? */
+ u8 tmrd = 4; /* JEDEC: 4nCK */
+ u8 tmod = max(ns_to_t(15), 12); /* JEDEC: max(15 ns, 12nCK) */
+ u8 tcke = max(ns_to_t(6), 3); /* JEDEC: max(5.625 ns, 3nCK) */
+ u8 tcksrx = max(ns_to_t(10), 5); /* JEDEC: max(10 ns, 5nCK) */
+ u8 tcksre = max(ns_to_t(10), 5); /* JEDEC: max(10 ns, 5nCK) */
+ u8 tckesr = tcke + 1; /* JEDEC: tCKE(min) + 1nCK */
+ u8 trasmax = 24; /* JEDEC: tREFI * 9 */
+ u8 txs = ns_to_t(360) / 32; /* JEDEC: max(5nCK,tRFC+10ns) */
+ u8 txsdll = 4; /* JEDEC: 512 nCK */
+ u8 txsabort = 4; /* ? */
+ u8 txsfast = 4; /* ? */
+ u8 tcl = 6; /* JEDEC: CL / 2 => 6 */
+ u8 tcwl = 4; /* JEDEC: 8 */
+ u8 t_rdata_en = 7; /* ? */
+
+ u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */
+ u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1;
+ u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1;
+ u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
+
+ u8 twtp = tcwl + 2 + twr; /* (WL + BL / 2 + tWR) / 2 */
+ u8 twr2rd = tcwl + 2 + twtr; /* (WL + BL / 2 + tWTR) / 2 */
+ u8 trd2wr = 5; /* (RL + BL / 2 + 2 - WL) / 2 */
+
+ if (tcl + 1 >= trtp + trp)
+ trtp = tcl + 2 - trp;
+
+ /* set mode registers */
+ for (i = 0; i < ARRAY_SIZE(mr_ddr3); i++)
+ writel(mr_ddr3[i], &mctl_phy->mr[i]);
+
+ /* set DRAM timing */
+ writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras,
+ &mctl_ctl->dramtmg[0]);
+ writel((txp << 16) | (trtp << 8) | trc, &mctl_ctl->dramtmg[1]);
+ writel((tcwl << 24) | (tcl << 16) | (trd2wr << 8) | twr2rd,
+ &mctl_ctl->dramtmg[2]);
+ writel((tmrw << 20) | (tmrd << 12) | tmod, &mctl_ctl->dramtmg[3]);
+ writel((trcd << 24) | (tccd << 16) | (trrd << 8) | trp,
+ &mctl_ctl->dramtmg[4]);
+ writel((tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | tcke,
+ &mctl_ctl->dramtmg[5]);
+ /* Value suggested by ZynqMP manual and used by libdram */
+ writel((txp + 2) | 0x02020000, &mctl_ctl->dramtmg[6]);
+ writel((txsfast << 24) | (txsabort << 16) | (txsdll << 8) | txs,
+ &mctl_ctl->dramtmg[8]);
+ writel(txsr, &mctl_ctl->dramtmg[14]);
+
+ clrsetbits_le32(&mctl_ctl->init[0], (3 << 30), (1 << 30));
+ writel(0, &mctl_ctl->dfimisc);
+ clrsetbits_le32(&mctl_ctl->rankctl, 0xff0, 0x660);
+
+ /*
+ * Set timing registers of the PHY.
+ * Note: the PHY is clocked 2x from the DRAM frequency.
+ */
+ writel((trrd << 25) | (tras << 17) | (trp << 9) | (trtp << 1),
+ &mctl_phy->dtpr[0]);
+ writel((tfaw << 17) | 0x28000400 | (tmrd << 1), &mctl_phy->dtpr[1]);
+ writel(((txs << 6) - 1) | (tcke << 17), &mctl_phy->dtpr[2]);
+ writel(((txsdll << 22) - (0x1 << 16)) | twtr_sa | (tcksrea << 8),
+ &mctl_phy->dtpr[3]);
+ writel((txp << 1) | (trfc << 17) | 0x800, &mctl_phy->dtpr[4]);
+ writel((trc << 17) | (trcd << 9) | (twtr << 1), &mctl_phy->dtpr[5]);
+ writel(0x0505, &mctl_phy->dtpr[6]);
+
+ /* Configure DFI timing */
+ writel(tcl | 0x2000200 | (t_rdata_en << 16) | 0x808000,
+ &mctl_ctl->dfitmg0);
+ writel(0x040201, &mctl_ctl->dfitmg1);
+
+ /* Configure PHY timing. Zynq uses different registers. */
+ writel(tdinit0 | (tdinit1 << 20), &mctl_phy->ptr[3]);
+ writel(tdinit2 | (tdinit3 << 18), &mctl_phy->ptr[4]);
+
+ /* set refresh timing */
+ writel((trefi << 16) | trfc, &mctl_ctl->rfshtmg);
+}
diff --git a/arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c b/arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c
new file mode 100644
index 0000000..1000860
--- /dev/null
+++ b/arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c
@@ -0,0 +1,132 @@
+/*
+ * sun50i H6 LPDDR3 timings
+ *
+ * (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+#include <asm/arch/cpu.h>
+
+static u32 mr_lpddr3[12] = {
+ 0x00000000, 0x00000043, 0x0000001a, 0x00000001,
+ 0x00000000, 0x00000000, 0x00000048, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000003,
+};
+
+/* TODO: flexible timing */
+void mctl_set_timing_params(struct dram_para *para)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+ struct sunxi_mctl_phy_reg * const mctl_phy =
+ (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
+ int i;
+
+ u8 tccd = 2;
+ u8 tfaw = max(ns_to_t(50), 4);
+ u8 trrd = max(ns_to_t(10), 2);
+ u8 trcd = max(ns_to_t(24), 2);
+ u8 trc = ns_to_t(70);
+ u8 txp = max(ns_to_t(8), 2);
+ u8 twtr = max(ns_to_t(8), 2);
+ u8 trtp = max(ns_to_t(8), 2);
+ u8 twr = max(ns_to_t(15), 2);
+ u8 trp = ns_to_t(18);
+ u8 tras = ns_to_t(42);
+ u8 twtr_sa = ns_to_t(5);
+ u8 tcksrea = ns_to_t(11);
+ u16 trefi = ns_to_t(3900) / 32;
+ u16 trfc = ns_to_t(210);
+ u16 txsr = ns_to_t(220);
+
+ if (CONFIG_DRAM_CLK % 400 == 0) {
+ /* Round up these parameters */
+ twtr_sa++;
+ tcksrea++;
+ }
+
+ u8 tmrw = 5;
+ u8 tmrd = 5;
+ u8 tmod = 12;
+ u8 tcke = 3;
+ u8 tcksrx = 5;
+ u8 tcksre = 5;
+ u8 tckesr = 5;
+ u8 trasmax = CONFIG_DRAM_CLK / 60;
+ u8 txs = 4;
+ u8 txsdll = 4;
+ u8 txsabort = 4;
+ u8 txsfast = 4;
+
+ u8 tcl = 5; /* CL 10 */
+ u8 tcwl = 3; /* CWL 6 */
+ u8 t_rdata_en = twtr_sa + 8;
+
+ u32 tdinit0 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
+ u32 tdinit1 = (100 * CONFIG_DRAM_CLK) / 1000 + 1; /* 100ns */
+ u32 tdinit2 = (11 * CONFIG_DRAM_CLK) + 1; /* 11us */
+ u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
+
+ u8 twtp = tcwl + 4 + twr + 1;
+ /*
+ * The code below for twr2rd and trd2wr follows the IP core's
+ * document from ZynqMP and i.MX7. The BSP has both number
+ * substracted by 2.
+ */
+ u8 twr2rd = tcwl + 4 + 1 + twtr;
+ u8 trd2wr = tcl + 4 + (tcksrea >> 1) - tcwl + 1;
+
+ /* set mode registers */
+ for (i = 0; i < ARRAY_SIZE(mr_lpddr3); i++)
+ writel(mr_lpddr3[i], &mctl_phy->mr[i]);
+
+ /* set DRAM timing */
+ writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras,
+ &mctl_ctl->dramtmg[0]);
+ writel((txp << 16) | (trtp << 8) | trc, &mctl_ctl->dramtmg[1]);
+ writel((tcwl << 24) | (tcl << 16) | (trd2wr << 8) | twr2rd,
+ &mctl_ctl->dramtmg[2]);
+ writel((tmrw << 20) | (tmrd << 12) | tmod, &mctl_ctl->dramtmg[3]);
+ writel((trcd << 24) | (tccd << 16) | (trrd << 8) | trp,
+ &mctl_ctl->dramtmg[4]);
+ writel((tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | tcke,
+ &mctl_ctl->dramtmg[5]);
+ /* Value suggested by ZynqMP manual and used by libdram */
+ writel((txp + 2) | 0x02020000, &mctl_ctl->dramtmg[6]);
+ writel((txsfast << 24) | (txsabort << 16) | (txsdll << 8) | txs,
+ &mctl_ctl->dramtmg[8]);
+ writel(txsr, &mctl_ctl->dramtmg[14]);
+
+ clrsetbits_le32(&mctl_ctl->init[0], (3 << 30), (1 << 30));
+ writel(0, &mctl_ctl->dfimisc);
+ clrsetbits_le32(&mctl_ctl->rankctl, 0xff0, 0x660);
+
+ /*
+ * Set timing registers of the PHY.
+ * Note: the PHY is clocked 2x from the DRAM frequency.
+ */
+ writel((trrd << 25) | (tras << 17) | (trp << 9) | (trtp << 1),
+ &mctl_phy->dtpr[0]);
+ writel((tfaw << 17) | 0x28000400 | (tmrd << 1), &mctl_phy->dtpr[1]);
+ writel(((txs << 6) - 1) | (tcke << 17), &mctl_phy->dtpr[2]);
+ writel(((txsdll << 22) - (0x1 << 16)) | twtr_sa | (tcksrea << 8),
+ &mctl_phy->dtpr[3]);
+ writel((txp << 1) | (trfc << 17) | 0x800, &mctl_phy->dtpr[4]);
+ writel((trc << 17) | (trcd << 9) | (twtr << 1), &mctl_phy->dtpr[5]);
+ writel(0x0505, &mctl_phy->dtpr[6]);
+
+ /* Configure DFI timing */
+ writel(tcl | 0x2000200 | (t_rdata_en << 16) | 0x808000,
+ &mctl_ctl->dfitmg0);
+ writel(0x040201, &mctl_ctl->dfitmg1);
+
+ /* Configure PHY timing */
+ writel(tdinit0 | (tdinit1 << 20), &mctl_phy->ptr[3]);
+ writel(tdinit2 | (tdinit3 << 18), &mctl_phy->ptr[4]);
+
+ /* set refresh timing */
+ writel((trefi << 16) | trfc, &mctl_ctl->rfshtmg);
+}
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 97e22ea..ff9f29f 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -86,6 +86,7 @@
config TEGRA_ARMV8_COMMON
bool "Tegra 64-bit common options"
select ARM64
+ select INIT_SP_RELATIVE
select LINUX_KERNEL_IMAGE_HEADER
select POSITION_INDEPENDENT
select TEGRA_COMMON
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index bbc487a..f13bd25 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <dm.h>
#include <efi_loader.h>
+#include <env.h>
#include <errno.h>
#include <ns16550.h>
#include <usb.h>
diff --git a/arch/arm/mach-tegra/cboot.c b/arch/arm/mach-tegra/cboot.c
index a829ef7..0433081 100644
--- a/arch/arm/mach-tegra/cboot.c
+++ b/arch/arm/mach-tegra/cboot.c
@@ -4,7 +4,7 @@
*/
#include <common.h>
-#include <environment.h>
+#include <env.h>
#include <fdt_support.h>
#include <fdtdec.h>
#include <stdlib.h>
diff --git a/arch/arm/mach-tegra/sys_info.c b/arch/arm/mach-tegra/sys_info.c
index 9975f33..5dc998a 100644
--- a/arch/arm/mach-tegra/sys_info.c
+++ b/arch/arm/mach-tegra/sys_info.c
@@ -6,24 +6,36 @@
#include <common.h>
#include <linux/ctype.h>
+#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA30)
+#include <asm/arch-tegra/pmc.h>
-static void upstring(char *s)
+static char *get_reset_cause(void)
{
- while (*s) {
- *s = toupper(*s);
- s++;
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+ switch (pmc->pmc_reset_status) {
+ case 0x00:
+ return "POR";
+ case 0x01:
+ return "WATCHDOG";
+ case 0x02:
+ return "SENSOR";
+ case 0x03:
+ return "SW_MAIN";
+ case 0x04:
+ return "LP0";
}
+ return "UNKNOWN";
}
+#endif
/* Print CPU information */
int print_cpuinfo(void)
{
- char soc_name[10];
-
- strncpy(soc_name, CONFIG_SYS_SOC, 10);
- upstring(soc_name);
- puts(soc_name);
- puts("\n");
+ printf("SoC: %s\n", CONFIG_SYS_SOC);
+#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA30)
+ printf("Reset cause: %s\n", get_reset_cause());
+#endif
/* TBD: Add printf of major/minor rev info, stepping, etc. */
return 0;
diff --git a/arch/arm/mach-tegra/tegra124/cpu.c b/arch/arm/mach-tegra/tegra124/cpu.c
index 992c0be..abc050c 100644
--- a/arch/arm/mach-tegra/tegra124/cpu.c
+++ b/arch/arm/mach-tegra/tegra124/cpu.c
@@ -238,6 +238,45 @@
return !!(reg & (1 << partid));
}
+static void unpower_partition(u32 partid)
+{
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+ debug("%s: part ID = %08X\n", __func__, partid);
+ /* Is the partition on? */
+ if (is_partition_powered(partid)) {
+ /* Yes, toggle the partition power state (ON -> OFF) */
+ debug("power_partition, toggling state\n");
+ writel(START_CP | partid, &pmc->pmc_pwrgate_toggle);
+
+ /* Wait for the power to come down */
+ while (is_partition_powered(partid))
+ ;
+
+ /* Give I/O signals time to stabilize */
+ udelay(IO_STABILIZATION_DELAY);
+ }
+}
+
+void unpower_cpus(void)
+{
+ debug("%s entry: G cluster\n", __func__);
+
+ /* Power down the fast cluster rail partition */
+ debug("%s: CRAIL\n", __func__);
+ unpower_partition(CRAIL);
+
+ /* Power down the fast cluster non-CPU partition */
+ debug("%s: C0NC\n", __func__);
+ unpower_partition(C0NC);
+
+ /* Power down the fast cluster CPU0 partition */
+ debug("%s: CE0\n", __func__);
+ unpower_partition(CE0);
+
+ debug("%s: done\n", __func__);
+}
+
static void power_partition(u32 partid)
{
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
@@ -284,6 +323,12 @@
debug("%s entry, reset_vector = %x\n", __func__, reset_vector);
+ /*
+ * High power clusters are on after software reset,
+ * it may interfere with tegra124_ram_repair.
+ * unpower them.
+ */
+ unpower_cpus();
tegra124_init_clocks();
/* Set power-gating timer multiplier */
diff --git a/arch/arm/mach-tegra/tegra186/Kconfig b/arch/arm/mach-tegra/tegra186/Kconfig
index 479c095..b2e53b5 100644
--- a/arch/arm/mach-tegra/tegra186/Kconfig
+++ b/arch/arm/mach-tegra/tegra186/Kconfig
@@ -21,9 +21,6 @@
config SYS_SOC
default "tegra186"
-config SYS_INIT_SP_BSS_OFFSET
- default 524288
-
source "board/nvidia/p2771-0000/Kconfig"
endif
diff --git a/arch/arm/mach-tegra/tegra210/Kconfig b/arch/arm/mach-tegra/tegra210/Kconfig
index 250738a..3637473 100644
--- a/arch/arm/mach-tegra/tegra210/Kconfig
+++ b/arch/arm/mach-tegra/tegra210/Kconfig
@@ -40,9 +40,6 @@
config SYS_SOC
default "tegra210"
-config SYS_INIT_SP_BSS_OFFSET
- default 524288
-
source "board/nvidia/e2220-1170/Kconfig"
source "board/nvidia/p2371-0000/Kconfig"
source "board/nvidia/p2371-2180/Kconfig"
diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile
index d0c39d42..115af24 100644
--- a/arch/arm/mach-uniphier/Makefile
+++ b/arch/arm/mach-uniphier/Makefile
@@ -13,18 +13,20 @@
obj-$(CONFIG_DISPLAY_CPUINFO) += cpu-info.o
obj-y += dram_init.o
obj-y += board_init.o
+obj-$(CONFIG_ARCH_UNIPHIER_V8_MULTI) += base-address.o
obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o
ifndef CONFIG_SYSRESET
obj-y += reset.o
endif
-obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/ micro-support-card.o
+obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o
obj-y += pinctrl-glue.o
obj-$(CONFIG_MMC) += mmc-first-dev.o
obj-y += fdt-fixup.o
endif
+obj-y += sbc/
obj-y += soc-info.o
obj-y += boot-device/
obj-y += clk/
diff --git a/arch/arm/mach-uniphier/arm32/debug_ll.S b/arch/arm/mach-uniphier/arm32/debug_ll.S
index e56e1f6..3fed798 100644
--- a/arch/arm/mach-uniphier/arm32/debug_ll.S
+++ b/arch/arm/mach-uniphier/arm32/debug_ll.S
@@ -22,7 +22,7 @@
#define DIV_ROUND(x, d) (((x) + ((d) / 2)) / (d))
.macro sg_set_pinsel, pin, muxval, mux_bits, reg_stride, ra, rd
- ldr \ra, =(SG_PINCTRL_BASE + \pin * \mux_bits / 32 * \reg_stride)
+ ldr \ra, =(SG_BASE + SG_PINCTRL_BASE + \pin * \mux_bits / 32 * \reg_stride)
ldr \rd, [\ra]
and \rd, \rd, #~(((1 << \mux_bits) - 1) << (\pin * \mux_bits % 32))
orr \rd, \rd, #(\muxval << (\pin * \mux_bits % 32))
@@ -30,7 +30,7 @@
.endm
ENTRY(debug_ll_init)
- ldr r0, =SG_REVISION
+ ldr r0, =(SG_BASE + SG_REVISION)
ldr r1, [r0]
and r1, r1, #SG_REVISION_TYPE_MASK
mov r1, r1, lsr #SG_REVISION_TYPE_SHIFT
@@ -40,7 +40,7 @@
cmp r1, #0x26
bne ld4_end
- ldr r0, =SG_IECTRL
+ ldr r0, =(SG_BASE + SG_IECTRL)
ldr r1, [r0]
orr r1, r1, #1
str r1, [r0]
@@ -59,11 +59,11 @@
sg_set_pinsel 128, 0, 4, 8, r0, r1 @ TXD0 -> TXD0
- ldr r0, =SG_LOADPINCTRL
+ ldr r0, =(SG_BASE + SG_LOADPINCTRL)
mov r1, #1
str r1, [r0]
- ldr r0, =SC_CLKCTRL
+ ldr r0, =(SC_BASE + SC_CLKCTRL)
ldr r1, [r0]
orr r1, r1, #SC_CLKCTRL_CEN_PERI
str r1, [r0]
@@ -78,7 +78,7 @@
cmp r1, #0x29
bne sld8_end
- ldr r0, =SG_IECTRL
+ ldr r0, =(SG_BASE + SG_IECTRL)
ldr r1, [r0]
orr r1, r1, #1
str r1, [r0]
@@ -100,11 +100,11 @@
sg_set_pinsel 51, 0, 4, 8, r0, r1 @ TXD2 -> TXD2
sg_set_pinsel 53, 0, 4, 8, r0, r1 @ TXD3 -> TXD3
- ldr r0, =SG_LOADPINCTRL
+ ldr r0, =(SG_BASE + SG_LOADPINCTRL)
mov r1, #1
str r1, [r0]
- ldr r0, =SC_CLKCTRL
+ ldr r0, =(SC_BASE + SC_CLKCTRL)
ldr r1, [r0]
orr r1, r1, #SC_CLKCTRL_CEN_PERI
str r1, [r0]
@@ -119,7 +119,7 @@
cmp r1, #0x2E
bne pxs2_end
- ldr r0, =SG_IECTRL
+ ldr r0, =(SG_BASE + SG_IECTRL)
ldr r1, [r0]
orr r1, r1, #1
str r1, [r0]
@@ -129,7 +129,7 @@
sg_set_pinsel 113, 8, 8, 4, r0, r1 @ TXD2 -> TXD2
sg_set_pinsel 219, 8, 8, 4, r0, r1 @ TXD3 -> TXD3
- ldr r0, =SC_CLKCTRL
+ ldr r0, =(SC_BASE + SC_CLKCTRL)
ldr r1, [r0]
orr r1, r1, #SC_CLKCTRL_CEN_PERI
str r1, [r0]
@@ -144,7 +144,7 @@
cmp r1, #0x2F
bne ld6b_end
- ldr r0, =SG_IECTRL
+ ldr r0, =(SG_BASE + SG_IECTRL)
ldr r1, [r0]
orr r1, r1, #1
str r1, [r0]
@@ -153,7 +153,7 @@
sg_set_pinsel 115, 0, 8, 4, r0, r1 @ TXD1 -> TXD1
sg_set_pinsel 113, 2, 8, 4, r0, r1 @ SBO0 -> TXD2
- ldr r0, =SC_CLKCTRL
+ ldr r0, =(SC_BASE + SC_CLKCTRL)
ldr r1, [r0]
orr r1, r1, #SC_CLKCTRL_CEN_PERI
str r1, [r0]
diff --git a/arch/arm/mach-uniphier/arm32/psci.c b/arch/arm/mach-uniphier/arm32/psci.c
index 3f67edf..ef35923 100644
--- a/arch/arm/mach-uniphier/arm32/psci.c
+++ b/arch/arm/mach-uniphier/arm32/psci.c
@@ -130,7 +130,7 @@
u32 uniphier_psci_holding_pen_release __secure_data = 0xffffffff;
-int __secure psci_cpu_on(u32 function_id, u32 cpuid, u32 entry_point,
+s32 __secure psci_cpu_on(u32 function_id, u32 cpuid, u32 entry_point,
u32 context_id)
{
u32 cpu = cpuid & 0xff;
@@ -155,7 +155,7 @@
return PSCI_RET_SUCCESS;
}
-void __secure psci_system_reset(u32 function_id)
+void __secure psci_system_reset(void)
{
reset_cpu(0);
}
diff --git a/arch/arm/mach-uniphier/arm64/mem_map.c b/arch/arm/mach-uniphier/arm64/mem_map.c
index 35e75e2..7653bd2 100644
--- a/arch/arm/mach-uniphier/arm64/mem_map.c
+++ b/arch/arm/mach-uniphier/arm64/mem_map.c
@@ -7,6 +7,8 @@
#include <linux/types.h>
#include <asm/armv8/mmu.h>
+#include "../init.h"
+
static struct mm_region uniphier_mem_map[] = {
{
.virt = 0x00000000,
@@ -27,3 +29,11 @@
};
struct mm_region *mem_map = uniphier_mem_map;
+
+void uniphier_mem_map_init(unsigned long dram_base, unsigned long dram_size)
+{
+ uniphier_mem_map[0].size = dram_base;
+ uniphier_mem_map[1].virt = dram_base;
+ uniphier_mem_map[1].phys = dram_base;
+ uniphier_mem_map[1].size = dram_size;
+}
diff --git a/arch/arm/mach-uniphier/base-address.c b/arch/arm/mach-uniphier/base-address.c
new file mode 100644
index 0000000..5ee742e
--- /dev/null
+++ b/arch/arm/mach-uniphier/base-address.c
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (C) 2019 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+
+#include <common.h>
+#include <dm/of.h>
+#include <fdt_support.h>
+#include <linux/io.h>
+#include <linux/libfdt.h>
+#include <linux/sizes.h>
+#include <asm/global_data.h>
+
+#include "base-address.h"
+#include "sc64-regs.h"
+#include "sg-regs.h"
+
+/*
+ * Dummy initializers are needed to allocate these to .data section instead of
+ * .bss section. The .bss section is unusable before relocation because the
+ * .bss section and DT share the same address. Without the initializers,
+ * DT would be broken.
+ */
+void __iomem *sc_base = (void *)0xdeadbeef;
+void __iomem *sg_base = (void *)0xdeadbeef;
+
+static u64 uniphier_base_address_get(const char *compat_tail)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ const void *fdt = gd->fdt_blob;
+ int offset, len, i;
+ const char *str;
+
+ for (offset = fdt_next_node(fdt, 0, NULL);
+ offset >= 0;
+ offset = fdt_next_node(fdt, offset, NULL)) {
+ for (i = 0;
+ (str = fdt_stringlist_get(fdt, offset, "compatible", i, &len));
+ i++) {
+ if (!memcmp(compat_tail,
+ str + len - strlen(compat_tail),
+ strlen(compat_tail)))
+ return fdt_get_base_address(fdt, offset);
+ }
+ }
+
+ return OF_BAD_ADDR;
+}
+
+int uniphier_base_address_init(void)
+{
+ u64 base;
+
+ base = uniphier_base_address_get("-soc-glue");
+ if (base == OF_BAD_ADDR)
+ return -EINVAL;
+
+ sg_base = ioremap(base, SZ_8K);
+
+ base = uniphier_base_address_get("-sysctrl");
+ if (base == OF_BAD_ADDR)
+ return -EINVAL;
+
+ sc_base = ioremap(base, SZ_64K);
+
+ return 0;
+}
diff --git a/arch/arm/mach-uniphier/base-address.h b/arch/arm/mach-uniphier/base-address.h
new file mode 100644
index 0000000..6158ce7
--- /dev/null
+++ b/arch/arm/mach-uniphier/base-address.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2019 Socionext Inc.
+ */
+
+#ifndef __UNIPHIER_BASE_ADDRESS_H
+#define __UNIPHIER_BASE_ADDRESS_H
+
+#ifdef CONFIG_ARCH_UNIPHIER_V8_MULTI
+int uniphier_base_address_init(void);
+#else
+static inline int uniphier_base_address_init(void)
+{
+ return 0;
+}
+#endif
+
+#endif /* __UNIPHIER_BASE_ADDRESS_H */
diff --git a/arch/arm/mach-uniphier/board_late_init.c b/arch/arm/mach-uniphier/board_late_init.c
index 972dbe8..14b61fc 100644
--- a/arch/arm/mach-uniphier/board_late_init.c
+++ b/arch/arm/mach-uniphier/board_late_init.c
@@ -6,6 +6,7 @@
*/
#include <common.h>
+#include <env.h>
#include <spl.h>
#include <linux/libfdt.h>
#include <nand.h>
@@ -31,24 +32,25 @@
#endif
}
-static int uniphier_set_fdt_file(void)
+static void uniphier_set_env_fdt_file(void)
{
DECLARE_GLOBAL_DATA_PTR;
const char *compat;
char dtb_name[256];
int buf_len = sizeof(dtb_name);
+ int ret;
if (env_get("fdtfile"))
- return 0; /* do nothing if it is already set */
+ return; /* do nothing if it is already set */
compat = fdt_stringlist_get(gd->fdt_blob, 0, "compatible", 0, NULL);
if (!compat)
- return -EINVAL;
+ goto fail;
/* rip off the vendor prefix "socionext," */
compat = strchr(compat, ',');
if (!compat)
- return -EINVAL;
+ goto fail;
compat++;
strncpy(dtb_name, compat, buf_len);
@@ -56,7 +58,43 @@
strncat(dtb_name, ".dtb", buf_len);
- return env_set("fdtfile", dtb_name);
+ ret = env_set("fdtfile", dtb_name);
+ if (ret)
+ goto fail;
+
+ return;
+fail:
+ pr_warn("\"fdt_file\" environment variable was not set correctly\n");
+}
+
+static void uniphier_set_env_addr(const char *env, const char *offset_env)
+{
+ unsigned long offset = 0;
+ const char *str;
+ char *end;
+ int ret;
+
+ if (env_get(env))
+ return; /* do nothing if it is already set */
+
+ if (offset_env) {
+ str = env_get(offset_env);
+ if (!str)
+ goto fail;
+
+ offset = simple_strtoul(str, &end, 16);
+ if (*end)
+ goto fail;
+ }
+
+ ret = env_set_hex(env, gd->ram_base + offset);
+ if (ret)
+ goto fail;
+
+ return;
+
+fail:
+ pr_warn("\"%s\" environment variable was not set correctly\n", env);
}
int board_late_init(void)
@@ -68,6 +106,10 @@
printf("eMMC Boot");
env_set("bootdev", "emmc");
break;
+ case BOOT_DEVICE_MMC2:
+ printf("SD Boot");
+ env_set("bootdev", "sd");
+ break;
case BOOT_DEVICE_NAND:
printf("NAND Boot");
env_set("bootdev", "nand");
@@ -92,8 +134,15 @@
printf("\n");
- if (uniphier_set_fdt_file())
- pr_warn("fdt_file environment was not set correctly\n");
+ uniphier_set_env_fdt_file();
+
+ uniphier_set_env_addr("dram_base", NULL);
+
+ uniphier_set_env_addr("loadaddr", "loadaddr_offset");
+
+ uniphier_set_env_addr("kernel_addr_r", "kernel_addr_r_offset");
+ uniphier_set_env_addr("ramdisk_addr_r", "ramdisk_addr_r_offset");
+ uniphier_set_env_addr("fdt_addr_r", "fdt_addr_r_offset");
return 0;
}
diff --git a/arch/arm/mach-uniphier/boot-device/boot-device-ld11.c b/arch/arm/mach-uniphier/boot-device/boot-device-ld11.c
index 10093be..11e70a9 100644
--- a/arch/arm/mach-uniphier/boot-device/boot-device-ld11.c
+++ b/arch/arm/mach-uniphier/boot-device/boot-device-ld11.c
@@ -58,11 +58,3 @@
{
return !!(~pinmon & 0x00000780);
}
-
-unsigned int uniphier_ld11_boot_device_fixup(unsigned int mode)
-{
- if (mode == BOOT_DEVICE_MMC1 || mode == BOOT_DEVICE_USB)
- mode = BOOT_DEVICE_BOARD;
-
- return mode;
-}
diff --git a/arch/arm/mach-uniphier/boot-device/boot-device-pxs3.c b/arch/arm/mach-uniphier/boot-device/boot-device-pxs3.c
index 01a72c0..2edf66d 100644
--- a/arch/arm/mach-uniphier/boot-device/boot-device-pxs3.c
+++ b/arch/arm/mach-uniphier/boot-device/boot-device-pxs3.c
@@ -36,5 +36,5 @@
int uniphier_pxs3_boot_device_is_usb(u32 pinmon)
{
- return !!(readl(SG_PINMON2) & BIT(31));
+ return !!(readl(sg_base + SG_PINMON2) & BIT(31));
}
diff --git a/arch/arm/mach-uniphier/boot-device/boot-device.c b/arch/arm/mach-uniphier/boot-device/boot-device.c
index 23be8cf..83f8c6a 100644
--- a/arch/arm/mach-uniphier/boot-device/boot-device.c
+++ b/arch/arm/mach-uniphier/boot-device/boot-device.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <spl.h>
#include <stdio.h>
+#include <linux/io.h>
#include <linux/log2.h>
#include "../init.h"
@@ -20,9 +21,11 @@
unsigned int boot_device_sel_shift;
const struct uniphier_boot_device *boot_device_table;
const unsigned int *boot_device_count;
+ int (*boot_device_is_sd)(u32 pinmon);
int (*boot_device_is_usb)(u32 pinmon);
unsigned int (*boot_device_fixup)(unsigned int mode);
- int have_internal_stm;
+ int (*boot_is_swapped)(void);
+ bool have_internal_stm;
};
static const struct uniphier_boot_device_info uniphier_boot_device_info[] = {
@@ -32,7 +35,8 @@
.boot_device_sel_shift = 1,
.boot_device_table = uniphier_ld4_boot_device_table,
.boot_device_count = &uniphier_ld4_boot_device_count,
- .have_internal_stm = 1,
+ .boot_is_swapped = uniphier_sbc_boot_is_swapped,
+ .have_internal_stm = true,
},
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
@@ -41,7 +45,8 @@
.boot_device_sel_shift = 1,
.boot_device_table = uniphier_ld4_boot_device_table,
.boot_device_count = &uniphier_ld4_boot_device_count,
- .have_internal_stm = 0,
+ .boot_is_swapped = uniphier_sbc_boot_is_swapped,
+ .have_internal_stm = false,
},
#endif
#if defined(CONFIG_ARCH_UNIPHIER_SLD8)
@@ -50,7 +55,8 @@
.boot_device_sel_shift = 1,
.boot_device_table = uniphier_ld4_boot_device_table,
.boot_device_count = &uniphier_ld4_boot_device_count,
- .have_internal_stm = 1,
+ .boot_is_swapped = uniphier_sbc_boot_is_swapped,
+ .have_internal_stm = true,
},
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
@@ -59,7 +65,8 @@
.boot_device_sel_shift = 1,
.boot_device_table = uniphier_pro5_boot_device_table,
.boot_device_count = &uniphier_pro5_boot_device_count,
- .have_internal_stm = 0,
+ .boot_is_swapped = uniphier_sbc_boot_is_swapped,
+ .have_internal_stm = false,
},
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PXS2)
@@ -70,7 +77,8 @@
.boot_device_count = &uniphier_pxs2_boot_device_count,
.boot_device_is_usb = uniphier_pxs2_boot_device_is_usb,
.boot_device_fixup = uniphier_pxs2_boot_device_fixup,
- .have_internal_stm = 0,
+ .boot_is_swapped = uniphier_sbc_boot_is_swapped,
+ .have_internal_stm = false,
},
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
@@ -81,7 +89,8 @@
.boot_device_count = &uniphier_pxs2_boot_device_count,
.boot_device_is_usb = uniphier_pxs2_boot_device_is_usb,
.boot_device_fixup = uniphier_pxs2_boot_device_fixup,
- .have_internal_stm = 1, /* STM on A-chip */
+ .boot_is_swapped = uniphier_sbc_boot_is_swapped,
+ .have_internal_stm = true, /* STM on A-chip */
},
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD11)
@@ -91,8 +100,8 @@
.boot_device_table = uniphier_ld11_boot_device_table,
.boot_device_count = &uniphier_ld11_boot_device_count,
.boot_device_is_usb = uniphier_ld11_boot_device_is_usb,
- .boot_device_fixup = uniphier_ld11_boot_device_fixup,
- .have_internal_stm = 1,
+ .boot_is_swapped = uniphier_sbc_boot_is_swapped,
+ .have_internal_stm = true,
},
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD20)
@@ -102,8 +111,8 @@
.boot_device_table = uniphier_ld11_boot_device_table,
.boot_device_count = &uniphier_ld11_boot_device_count,
.boot_device_is_usb = uniphier_ld20_boot_device_is_usb,
- .boot_device_fixup = uniphier_ld11_boot_device_fixup,
- .have_internal_stm = 1,
+ .boot_is_swapped = uniphier_sbc_boot_is_swapped,
+ .have_internal_stm = true,
},
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PXS3)
@@ -113,7 +122,8 @@
.boot_device_table = uniphier_pxs3_boot_device_table,
.boot_device_count = &uniphier_pxs3_boot_device_count,
.boot_device_is_usb = uniphier_pxs3_boot_device_is_usb,
- .have_internal_stm = 0,
+ .boot_is_swapped = uniphier_sbc_boot_is_swapped,
+ .have_internal_stm = false,
},
#endif
};
@@ -126,10 +136,13 @@
u32 pinmon;
unsigned int boot_sel;
- if (boot_is_swapped())
+ if (info->boot_is_swapped && info->boot_is_swapped())
return BOOT_DEVICE_NOR;
- pinmon = readl(SG_PINMON0);
+ pinmon = readl(sg_base + SG_PINMON0);
+
+ if (info->boot_device_is_sd && info->boot_device_is_sd(pinmon))
+ return BOOT_DEVICE_MMC2;
if (info->boot_device_is_usb && info->boot_device_is_usb(pinmon))
return BOOT_DEVICE_USB;
@@ -187,7 +200,7 @@
int uniphier_boot_from_backend(void)
{
- return !!(readl(SG_PINMON0) & BIT(27));
+ return !!(readl(sg_base + SG_PINMON0) & BIT(27));
}
#ifndef CONFIG_SPL_BUILD
@@ -209,9 +222,15 @@
printf("STB Micon: %s\n",
uniphier_boot_from_backend() ? "OFF" : "ON");
- printf("Boot Swap: %s\n", boot_is_swapped() ? "ON" : "OFF");
+ if (info->boot_is_swapped)
+ printf("Boot Swap: %s\n",
+ info->boot_is_swapped() ? "ON" : "OFF");
- pinmon = readl(SG_PINMON0);
+ pinmon = readl(sg_base + SG_PINMON0);
+
+ if (info->boot_device_is_sd)
+ printf("SD Boot: %s\n",
+ info->boot_device_is_sd(pinmon) ? "ON" : "OFF");
if (info->boot_device_is_usb)
printf("USB Boot: %s\n",
diff --git a/arch/arm/mach-uniphier/boot-device/boot-device.h b/arch/arm/mach-uniphier/boot-device/boot-device.h
index 44579f1..bbb6343 100644
--- a/arch/arm/mach-uniphier/boot-device/boot-device.h
+++ b/arch/arm/mach-uniphier/boot-device/boot-device.h
@@ -30,6 +30,5 @@
int uniphier_pxs3_boot_device_is_usb(u32 pinmon);
unsigned int uniphier_pxs2_boot_device_fixup(unsigned int mode);
-unsigned int uniphier_ld11_boot_device_fixup(unsigned int mode);
#endif /* _UNIPHIER_BOOT_DEVICE_H_ */
diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile
index 3d741b4..d12f49e 100644
--- a/arch/arm/mach-uniphier/clk/Makefile
+++ b/arch/arm/mach-uniphier/clk/Makefile
@@ -17,12 +17,8 @@
obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-pro5.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-pxs2.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD11) += clk-ld11.o pll-ld11.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD20) += clk-ld20.o pll-ld20.o
-obj-$(CONFIG_ARCH_UNIPHIER_PXS3) += clk-pxs3.o pll-pxs3.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11) += clk-ld11.o pll-base-ld20.o pll-ld11.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20) += clk-ld20.o pll-base-ld20.o pll-ld20.o
+obj-$(CONFIG_ARCH_UNIPHIER_PXS3) += clk-pxs3.o pll-base-ld20.o pll-pxs3.o
endif
-
-obj-$(CONFIG_ARCH_UNIPHIER_LD11) += pll-base-ld20.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD20) += pll-base-ld20.o
-obj-$(CONFIG_ARCH_UNIPHIER_PXS3) += pll-base-ld20.o
diff --git a/arch/arm/mach-uniphier/clk/clk-dram-ld4.c b/arch/arm/mach-uniphier/clk/clk-dram-ld4.c
index 39cde44..c796d36 100644
--- a/arch/arm/mach-uniphier/clk/clk-dram-ld4.c
+++ b/arch/arm/mach-uniphier/clk/clk-dram-ld4.c
@@ -16,14 +16,14 @@
u32 tmp;
/* deassert reset */
- tmp = readl(SC_RSTCTRL);
+ tmp = readl(sc_base + SC_RSTCTRL);
tmp |= SC_RSTCTRL_NRST_UMC1 | SC_RSTCTRL_NRST_UMC0;
- writel(tmp, SC_RSTCTRL);
- readl(SC_RSTCTRL); /* dummy read */
+ writel(tmp, sc_base + SC_RSTCTRL);
+ readl(sc_base + SC_RSTCTRL); /* dummy read */
/* provide clocks */
- tmp = readl(SC_CLKCTRL);
+ tmp = readl(sc_base + SC_CLKCTRL);
tmp |= SC_CLKCTRL_CEN_UMC;
- writel(tmp, SC_CLKCTRL);
- readl(SC_CLKCTRL); /* dummy read */
+ writel(tmp, sc_base + SC_CLKCTRL);
+ readl(sc_base + SC_CLKCTRL); /* dummy read */
}
diff --git a/arch/arm/mach-uniphier/clk/clk-dram-pro5.c b/arch/arm/mach-uniphier/clk/clk-dram-pro5.c
index 7674ceb..808d1eb 100644
--- a/arch/arm/mach-uniphier/clk/clk-dram-pro5.c
+++ b/arch/arm/mach-uniphier/clk/clk-dram-pro5.c
@@ -18,17 +18,17 @@
* UMCA1, UMC31: Ch0 (WIO1)
* UMCA0, UMC30: Ch0 (WIO0)
*/
- tmp = readl(SC_RSTCTRL4);
+ tmp = readl(sc_base + SC_RSTCTRL4);
tmp |= SC_RSTCTRL4_NRST_UMCSB | SC_RSTCTRL4_NRST_UMCA2 |
SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 |
SC_RSTCTRL4_NRST_UMC31 | SC_RSTCTRL4_NRST_UMC30;
- writel(tmp, SC_RSTCTRL4);
- readl(SC_RSTCTRL4); /* dummy read */
+ writel(tmp, sc_base + SC_RSTCTRL4);
+ readl(sc_base + SC_RSTCTRL4); /* dummy read */
/* provide clocks */
- tmp = readl(SC_CLKCTRL4);
+ tmp = readl(sc_base + SC_CLKCTRL4);
tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC1 |
SC_CLKCTRL4_CEN_UMC0;
- writel(tmp, SC_CLKCTRL4);
- readl(SC_CLKCTRL4); /* dummy read */
+ writel(tmp, sc_base + SC_CLKCTRL4);
+ readl(sc_base + SC_CLKCTRL4); /* dummy read */
}
diff --git a/arch/arm/mach-uniphier/clk/clk-dram-pxs2.c b/arch/arm/mach-uniphier/clk/clk-dram-pxs2.c
index ad4e83a..b78bd01 100644
--- a/arch/arm/mach-uniphier/clk/clk-dram-pxs2.c
+++ b/arch/arm/mach-uniphier/clk/clk-dram-pxs2.c
@@ -15,18 +15,18 @@
u32 tmp;
/* deassert reset */
- tmp = readl(SC_RSTCTRL4);
+ tmp = readl(sc_base + SC_RSTCTRL4);
tmp |= SC_RSTCTRL4_NRST_UMCSB | SC_RSTCTRL4_NRST_UMCA2 |
SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 |
SC_RSTCTRL4_NRST_UMC32 | SC_RSTCTRL4_NRST_UMC31 |
SC_RSTCTRL4_NRST_UMC30;
- writel(tmp, SC_RSTCTRL4);
- readl(SC_RSTCTRL4); /* dummy read */
+ writel(tmp, sc_base + SC_RSTCTRL4);
+ readl(sc_base + SC_RSTCTRL4); /* dummy read */
/* provide clocks */
- tmp = readl(SC_CLKCTRL4);
+ tmp = readl(sc_base + SC_CLKCTRL4);
tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC2 |
SC_CLKCTRL4_CEN_UMC1 | SC_CLKCTRL4_CEN_UMC0;
- writel(tmp, SC_CLKCTRL4);
- readl(SC_CLKCTRL4); /* dummy read */
+ writel(tmp, sc_base + SC_CLKCTRL4);
+ readl(sc_base + SC_CLKCTRL4); /* dummy read */
}
diff --git a/arch/arm/mach-uniphier/clk/clk-early-ld4.c b/arch/arm/mach-uniphier/clk/clk-early-ld4.c
index eb36a9e..f32f78d 100644
--- a/arch/arm/mach-uniphier/clk/clk-early-ld4.c
+++ b/arch/arm/mach-uniphier/clk/clk-early-ld4.c
@@ -17,14 +17,14 @@
/* deassert reset */
if (spl_boot_device() != BOOT_DEVICE_NAND) {
- tmp = readl(SC_RSTCTRL);
+ tmp = readl(sc_base + SC_RSTCTRL);
tmp &= ~SC_RSTCTRL_NRST_NAND;
- writel(tmp, SC_RSTCTRL);
+ writel(tmp, sc_base + SC_RSTCTRL);
};
/* provide clocks */
- tmp = readl(SC_CLKCTRL);
+ tmp = readl(sc_base + SC_CLKCTRL);
tmp |= SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
- writel(tmp, SC_CLKCTRL);
- readl(SC_CLKCTRL); /* dummy read */
+ writel(tmp, sc_base + SC_CLKCTRL);
+ readl(sc_base + SC_CLKCTRL); /* dummy read */
}
diff --git a/arch/arm/mach-uniphier/clk/clk-ld11.c b/arch/arm/mach-uniphier/clk/clk-ld11.c
index e997acf..0917b33 100644
--- a/arch/arm/mach-uniphier/clk/clk-ld11.c
+++ b/arch/arm/mach-uniphier/clk/clk-ld11.c
@@ -17,16 +17,16 @@
void uniphier_ld11_clk_init(void)
{
/* if booted from a device other than USB, without stand-by MPU */
- if ((readl(SG_PINMON0) & BIT(27)) &&
+ if ((readl(sg_base + SG_PINMON0) & BIT(27)) &&
uniphier_boot_device_raw() != BOOT_DEVICE_USB) {
- writel(1, SG_ETPHYPSHUT);
- writel(1, SG_ETPHYCNT);
+ writel(1, sg_base + SG_ETPHYPSHUT);
+ writel(1, sg_base + SG_ETPHYCNT);
udelay(1); /* wait for regulator level 1.1V -> 2.5V */
- writel(3, SG_ETPHYCNT);
- writel(3, SG_ETPHYPSHUT);
- writel(7, SG_ETPHYCNT);
+ writel(3, sg_base + SG_ETPHYCNT);
+ writel(3, sg_base + SG_ETPHYPSHUT);
+ writel(7, sg_base + SG_ETPHYCNT);
}
/* TODO: use "mmc-pwrseq-emmc" */
@@ -37,7 +37,7 @@
int ch;
for (ch = 0; ch < 3; ch++) {
- void __iomem *phyctrl = (void __iomem *)SG_USBPHYCTRL;
+ void __iomem *phyctrl = sg_base + SG_USBPHYCTRL;
writel(0x82280600, phyctrl + 8 * ch);
writel(0x00000106, phyctrl + 8 * ch + 4);
diff --git a/arch/arm/mach-uniphier/clk/clk-ld20.c b/arch/arm/mach-uniphier/clk/clk-ld20.c
index 02a14dd..397b2d7 100644
--- a/arch/arm/mach-uniphier/clk/clk-ld20.c
+++ b/arch/arm/mach-uniphier/clk/clk-ld20.c
@@ -15,13 +15,13 @@
{
u32 tmp;
- tmp = readl(SC_RSTCTRL6);
+ tmp = readl(sc_base + SC_RSTCTRL6);
tmp |= BIT(8); /* Mali */
- writel(tmp, SC_RSTCTRL6);
+ writel(tmp, sc_base + SC_RSTCTRL6);
- tmp = readl(SC_CLKCTRL6);
+ tmp = readl(sc_base + SC_CLKCTRL6);
tmp |= BIT(8); /* Mali */
- writel(tmp, SC_CLKCTRL6);
+ writel(tmp, sc_base + SC_CLKCTRL6);
/* TODO: use "mmc-pwrseq-emmc" */
writel(1, SDCTRL_EMMC_HW_RESET);
diff --git a/arch/arm/mach-uniphier/clk/clk-ld4.c b/arch/arm/mach-uniphier/clk/clk-ld4.c
index 9c88cde..0393942 100644
--- a/arch/arm/mach-uniphier/clk/clk-ld4.c
+++ b/arch/arm/mach-uniphier/clk/clk-ld4.c
@@ -15,18 +15,18 @@
u32 tmp;
/* deassert reset */
- tmp = readl(SC_RSTCTRL);
+ tmp = readl(sc_base + SC_RSTCTRL);
#ifdef CONFIG_NAND_DENALI
tmp |= SC_RSTCTRL_NRST_NAND;
#endif
- writel(tmp, SC_RSTCTRL);
- readl(SC_RSTCTRL); /* dummy read */
+ writel(tmp, sc_base + SC_RSTCTRL);
+ readl(sc_base + SC_RSTCTRL); /* dummy read */
/* provide clocks */
- tmp = readl(SC_CLKCTRL);
+ tmp = readl(sc_base + SC_CLKCTRL);
#ifdef CONFIG_NAND_DENALI
tmp |= SC_CLKCTRL_CEN_NAND;
#endif
- writel(tmp, SC_CLKCTRL);
- readl(SC_CLKCTRL); /* dummy read */
+ writel(tmp, sc_base + SC_CLKCTRL);
+ readl(sc_base + SC_CLKCTRL); /* dummy read */
}
diff --git a/arch/arm/mach-uniphier/clk/clk-pro4.c b/arch/arm/mach-uniphier/clk/clk-pro4.c
index 32d44c0..2b364dc 100644
--- a/arch/arm/mach-uniphier/clk/clk-pro4.c
+++ b/arch/arm/mach-uniphier/clk/clk-pro4.c
@@ -15,7 +15,7 @@
u32 tmp;
/* deassert reset */
- tmp = readl(SC_RSTCTRL);
+ tmp = readl(sc_base + SC_RSTCTRL);
#ifdef CONFIG_USB_DWC3_UNIPHIER
tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_USB3C0 |
SC_RSTCTRL_NRST_GIO;
@@ -23,18 +23,18 @@
#ifdef CONFIG_NAND_DENALI
tmp |= SC_RSTCTRL_NRST_NAND;
#endif
- writel(tmp, SC_RSTCTRL);
- readl(SC_RSTCTRL); /* dummy read */
+ writel(tmp, sc_base + SC_RSTCTRL);
+ readl(sc_base + SC_RSTCTRL); /* dummy read */
#ifdef CONFIG_USB_DWC3_UNIPHIER
- tmp = readl(SC_RSTCTRL2);
+ tmp = readl(sc_base + SC_RSTCTRL2);
tmp |= SC_RSTCTRL2_NRST_USB3B1 | SC_RSTCTRL2_NRST_USB3C1;
- writel(tmp, SC_RSTCTRL2);
- readl(SC_RSTCTRL2); /* dummy read */
+ writel(tmp, sc_base + SC_RSTCTRL2);
+ readl(sc_base + SC_RSTCTRL2); /* dummy read */
#endif
/* provide clocks */
- tmp = readl(SC_CLKCTRL);
+ tmp = readl(sc_base + SC_CLKCTRL);
#ifdef CONFIG_USB_DWC3_UNIPHIER
tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
SC_CLKCTRL_CEN_GIO;
@@ -42,6 +42,6 @@
#ifdef CONFIG_NAND_DENALI
tmp |= SC_CLKCTRL_CEN_NAND;
#endif
- writel(tmp, SC_CLKCTRL);
- readl(SC_CLKCTRL); /* dummy read */
+ writel(tmp, sc_base + SC_CLKCTRL);
+ readl(sc_base + SC_CLKCTRL); /* dummy read */
}
diff --git a/arch/arm/mach-uniphier/clk/clk-pro5.c b/arch/arm/mach-uniphier/clk/clk-pro5.c
index 338d73d..874964b 100644
--- a/arch/arm/mach-uniphier/clk/clk-pro5.c
+++ b/arch/arm/mach-uniphier/clk/clk-pro5.c
@@ -13,25 +13,25 @@
u32 tmp;
/* deassert reset */
- tmp = readl(SC_RSTCTRL);
+ tmp = readl(sc_base + SC_RSTCTRL);
#ifdef CONFIG_USB_DWC3_UNIPHIER
tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO;
#endif
#ifdef CONFIG_NAND_DENALI
tmp |= SC_RSTCTRL_NRST_NAND;
#endif
- writel(tmp, SC_RSTCTRL);
- readl(SC_RSTCTRL); /* dummy read */
+ writel(tmp, sc_base + SC_RSTCTRL);
+ readl(sc_base + SC_RSTCTRL); /* dummy read */
#ifdef CONFIG_USB_DWC3_UNIPHIER
- tmp = readl(SC_RSTCTRL2);
+ tmp = readl(sc_base + SC_RSTCTRL2);
tmp |= SC_RSTCTRL2_NRST_USB3B1;
- writel(tmp, SC_RSTCTRL2);
- readl(SC_RSTCTRL2); /* dummy read */
+ writel(tmp, sc_base + SC_RSTCTRL2);
+ readl(sc_base + SC_RSTCTRL2); /* dummy read */
#endif
/* provide clocks */
- tmp = readl(SC_CLKCTRL);
+ tmp = readl(sc_base + SC_CLKCTRL);
#ifdef CONFIG_USB_DWC3_UNIPHIER
tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
SC_CLKCTRL_CEN_GIO;
@@ -39,6 +39,6 @@
#ifdef CONFIG_NAND_DENALI
tmp |= SC_CLKCTRL_CEN_NAND;
#endif
- writel(tmp, SC_CLKCTRL);
- readl(SC_CLKCTRL); /* dummy read */
+ writel(tmp, sc_base + SC_CLKCTRL);
+ readl(sc_base + SC_CLKCTRL); /* dummy read */
}
diff --git a/arch/arm/mach-uniphier/clk/clk-pxs2.c b/arch/arm/mach-uniphier/clk/clk-pxs2.c
index afa12fa..8cb4f87 100644
--- a/arch/arm/mach-uniphier/clk/clk-pxs2.c
+++ b/arch/arm/mach-uniphier/clk/clk-pxs2.c
@@ -14,29 +14,29 @@
u32 tmp;
/* deassert reset */
- tmp = readl(SC_RSTCTRL);
+ tmp = readl(sc_base + SC_RSTCTRL);
#ifdef CONFIG_USB_DWC3_UNIPHIER
tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO;
#endif
#ifdef CONFIG_NAND_DENALI
tmp |= SC_RSTCTRL_NRST_NAND;
#endif
- writel(tmp, SC_RSTCTRL);
- readl(SC_RSTCTRL); /* dummy read */
+ writel(tmp, sc_base + SC_RSTCTRL);
+ readl(sc_base + SC_RSTCTRL); /* dummy read */
#ifdef CONFIG_USB_DWC3_UNIPHIER
- tmp = readl(SC_RSTCTRL2);
+ tmp = readl(sc_base + SC_RSTCTRL2);
tmp |= SC_RSTCTRL2_NRST_USB3B1;
- writel(tmp, SC_RSTCTRL2);
- readl(SC_RSTCTRL2); /* dummy read */
+ writel(tmp, sc_base + SC_RSTCTRL2);
+ readl(sc_base + SC_RSTCTRL2); /* dummy read */
- tmp = readl(SC_RSTCTRL6);
+ tmp = readl(sc_base + SC_RSTCTRL6);
tmp |= 0x37;
- writel(tmp, SC_RSTCTRL6);
+ writel(tmp, sc_base + SC_RSTCTRL6);
#endif
/* provide clocks */
- tmp = readl(SC_CLKCTRL);
+ tmp = readl(sc_base + SC_CLKCTRL);
#ifdef CONFIG_USB_DWC3_UNIPHIER
tmp |= BIT(20) | BIT(19) | SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
SC_CLKCTRL_CEN_GIO;
@@ -44,6 +44,6 @@
#ifdef CONFIG_NAND_DENALI
tmp |= SC_CLKCTRL_CEN_NAND;
#endif
- writel(tmp, SC_CLKCTRL);
- readl(SC_CLKCTRL); /* dummy read */
+ writel(tmp, sc_base + SC_CLKCTRL);
+ readl(sc_base + SC_CLKCTRL); /* dummy read */
}
diff --git a/arch/arm/mach-uniphier/clk/clk-pxs3.c b/arch/arm/mach-uniphier/clk/clk-pxs3.c
index 73824e9..33b9c5b 100644
--- a/arch/arm/mach-uniphier/clk/clk-pxs3.c
+++ b/arch/arm/mach-uniphier/clk/clk-pxs3.c
@@ -15,13 +15,13 @@
{
u32 tmp;
- tmp = readl(SC_RSTCTRL6);
+ tmp = readl(sc_base + SC_RSTCTRL6);
tmp |= BIT(8); /* Mali */
- writel(tmp, SC_RSTCTRL6);
+ writel(tmp, sc_base + SC_RSTCTRL6);
- tmp = readl(SC_CLKCTRL6);
+ tmp = readl(sc_base + SC_CLKCTRL6);
tmp |= BIT(8); /* Mali */
- writel(tmp, SC_CLKCTRL6);
+ writel(tmp, sc_base + SC_CLKCTRL6);
/* TODO: use "mmc-pwrseq-emmc" */
writel(1, SDCTRL_EMMC_HW_RESET);
diff --git a/arch/arm/mach-uniphier/clk/dpll-ld4.c b/arch/arm/mach-uniphier/clk/dpll-ld4.c
index 4b9ec07..72fe8db 100644
--- a/arch/arm/mach-uniphier/clk/dpll-ld4.c
+++ b/arch/arm/mach-uniphier/clk/dpll-ld4.c
@@ -23,7 +23,7 @@
* Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
* to FOUT (DPLLCTRL.bit[29:20])
*/
- tmp = readl(SC_DPLLCTRL);
+ tmp = readl(sc_base + SC_DPLLCTRL);
tmp &= ~0x000f0000;
switch (dram_freq) {
case 1333:
@@ -42,11 +42,11 @@
#else
tmp |= SC_DPLLCTRL_SSC_RATE;
#endif
- writel(tmp, SC_DPLLCTRL);
+ writel(tmp, sc_base + SC_DPLLCTRL);
- tmp = readl(SC_DPLLCTRL2);
+ tmp = readl(sc_base + SC_DPLLCTRL2);
tmp |= SC_DPLLCTRL2_NRSTDS;
- writel(tmp, SC_DPLLCTRL2);
+ writel(tmp, sc_base + SC_DPLLCTRL2);
/* Wait 500 usec until dpll gets stable */
udelay(500);
diff --git a/arch/arm/mach-uniphier/clk/dpll-pro4.c b/arch/arm/mach-uniphier/clk/dpll-pro4.c
index 2965946..6259495 100644
--- a/arch/arm/mach-uniphier/clk/dpll-pro4.c
+++ b/arch/arm/mach-uniphier/clk/dpll-pro4.c
@@ -23,7 +23,7 @@
* Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
* to FOUT ( DPLLCTRL.bit[29:20] )
*/
- tmp = readl(SC_DPLLCTRL);
+ tmp = readl(sc_base + SC_DPLLCTRL);
tmp &= ~(0x000f0000);
switch (dram_freq) {
case 1333:
@@ -46,11 +46,11 @@
#else
tmp |= 0x00008000;
#endif
- writel(tmp, SC_DPLLCTRL);
+ writel(tmp, sc_base + SC_DPLLCTRL);
- tmp = readl(SC_DPLLCTRL2);
+ tmp = readl(sc_base + SC_DPLLCTRL2);
tmp |= SC_DPLLCTRL2_NRSTDS;
- writel(tmp, SC_DPLLCTRL2);
+ writel(tmp, sc_base + SC_DPLLCTRL2);
/* Wait until dpll gets stable */
udelay(500);
diff --git a/arch/arm/mach-uniphier/clk/dpll-sld8.c b/arch/arm/mach-uniphier/clk/dpll-sld8.c
index 1d7b752..1ac52d1 100644
--- a/arch/arm/mach-uniphier/clk/dpll-sld8.c
+++ b/arch/arm/mach-uniphier/clk/dpll-sld8.c
@@ -22,10 +22,10 @@
* [4] ICPD_TEST 0x1
* [3:0] ICPD 0xb
*/
- tmp = readl(SC_DPLLCTRL3);
+ tmp = readl(sc_base + SC_DPLLCTRL3);
tmp &= ~0x00ff0717;
tmp |= 0x00d0061b;
- writel(tmp, SC_DPLLCTRL3);
+ writel(tmp, sc_base + SC_DPLLCTRL3);
/*
* Set DPLL SSC parameters for DPLLCTRL
@@ -33,14 +33,14 @@
* [29:20] SSC_UPCNT 132 (0x084) 132 (0x084)
* [14:0] SSC_dK 6335(0x18bf) 12710(0x31a6)
*/
- tmp = readl(SC_DPLLCTRL);
+ tmp = readl(sc_base + SC_DPLLCTRL);
tmp &= ~0x3ff07fff;
#ifdef DPLL_SSC_RATE_1PER
tmp |= 0x084018bf;
#else
tmp |= 0x084031a6;
#endif
- writel(tmp, SC_DPLLCTRL);
+ writel(tmp, sc_base + SC_DPLLCTRL);
/*
* Set DPLL SSC parameters for DPLLCTRL2
@@ -49,10 +49,10 @@
* [26:20] SSC_M 79 (0x4f)
* [19:0] SSC_K 964689 (0xeb851)
*/
- tmp = readl(SC_DPLLCTRL2);
+ tmp = readl(sc_base + SC_DPLLCTRL2);
tmp &= ~0xefffffff;
tmp |= 0x0cfeb851;
- writel(tmp, SC_DPLLCTRL2);
+ writel(tmp, sc_base + SC_DPLLCTRL2);
/* Wait 500 usec until dpll gets stable */
udelay(500);
diff --git a/arch/arm/mach-uniphier/clk/dpll-tail.c b/arch/arm/mach-uniphier/clk/dpll-tail.c
index 7f434f6..6ba5a36 100644
--- a/arch/arm/mach-uniphier/clk/dpll-tail.c
+++ b/arch/arm/mach-uniphier/clk/dpll-tail.c
@@ -14,7 +14,7 @@
{
u32 tmp;
- tmp = readl(SC_DPLLCTRL);
+ tmp = readl(sc_base + SC_DPLLCTRL);
tmp |= SC_DPLLCTRL_SSC_EN;
- writel(tmp, SC_DPLLCTRL);
+ writel(tmp, sc_base + SC_DPLLCTRL);
}
diff --git a/arch/arm/mach-uniphier/clk/pll-base-ld20.c b/arch/arm/mach-uniphier/clk/pll-base-ld20.c
index 67b8ee7..ea96d73 100644
--- a/arch/arm/mach-uniphier/clk/pll-base-ld20.c
+++ b/arch/arm/mach-uniphier/clk/pll-base-ld20.c
@@ -12,6 +12,7 @@
#include <linux/io.h>
#include <linux/sizes.h>
+#include "../sc64-regs.h"
#include "pll.h"
/* PLL type: SSC */
@@ -31,13 +32,9 @@
int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq,
unsigned int ssc_rate, unsigned int divn)
{
- void __iomem *base;
+ void __iomem *base = sc_base + reg_base;
u32 tmp;
- base = ioremap(reg_base, SZ_16);
- if (!base)
- return -ENOMEM;
-
if (freq != UNIPHIER_PLL_FREQ_DEFAULT) {
tmp = readl(base); /* SSCPLLCTRL */
tmp &= ~SC_PLLCTRL_SSC_DK_MASK;
@@ -60,57 +57,39 @@
tmp |= SC_PLLCTRL2_NRSTDS;
writel(tmp, base + 4);
- iounmap(base);
-
return 0;
}
int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base)
{
- void __iomem *base;
+ void __iomem *base = sc_base + reg_base;
u32 tmp;
- base = ioremap(reg_base, SZ_16);
- if (!base)
- return -ENOMEM;
-
tmp = readl(base); /* SSCPLLCTRL */
tmp |= SC_PLLCTRL_SSC_EN;
writel(tmp, base);
- iounmap(base);
-
return 0;
}
int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi)
{
- void __iomem *base;
+ void __iomem *base = sc_base + reg_base;
u32 tmp;
- base = ioremap(reg_base, SZ_16);
- if (!base)
- return -ENOMEM;
-
tmp = readl(base + 8); /* SSCPLLCTRL3 */
tmp &= ~SC_PLLCTRL3_REGI_MASK;
tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi);
writel(tmp, base + 8);
- iounmap(base);
-
return 0;
}
int uniphier_ld20_vpll27_init(unsigned long reg_base)
{
- void __iomem *base;
+ void __iomem *base = sc_base + reg_base;
u32 tmp;
- base = ioremap(reg_base, SZ_16);
- if (!base)
- return -ENOMEM;
-
tmp = readl(base); /* VPLL27CTRL */
tmp |= SC_VPLL27CTRL_WP; /* write protect off */
writel(tmp, base);
@@ -123,25 +102,17 @@
tmp &= ~SC_VPLL27CTRL_WP; /* write protect on */
writel(tmp, base);
- iounmap(base);
-
return 0;
}
int uniphier_ld20_dspll_init(unsigned long reg_base)
{
- void __iomem *base;
+ void __iomem *base = sc_base + reg_base;
u32 tmp;
- base = ioremap(reg_base, SZ_16);
- if (!base)
- return -ENOMEM;
-
tmp = readl(base + 4); /* DSPLLCTRL2 */
tmp |= SC_DSPLLCTRL2_K_LD;
writel(tmp, base + 4);
- iounmap(base);
-
return 0;
}
diff --git a/arch/arm/mach-uniphier/clk/pll-ld11.c b/arch/arm/mach-uniphier/clk/pll-ld11.c
index fd724f3..7f07e3e 100644
--- a/arch/arm/mach-uniphier/clk/pll-ld11.c
+++ b/arch/arm/mach-uniphier/clk/pll-ld11.c
@@ -11,15 +11,15 @@
#include "pll.h"
/* PLL type: SSC */
-#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */
-#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */
-#define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* DSP */
-#define SC_VSPLLCTRL (SC_BASE_ADDR | 0x1440) /* Video codec, VPE etc. */
-#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1460) /* DDR memory */
+#define SC_CPLLCTRL 0x1400 /* CPU/ARM */
+#define SC_SPLLCTRL 0x1410 /* misc */
+#define SC_MPLLCTRL 0x1430 /* DSP */
+#define SC_VSPLLCTRL 0x1440 /* Video codec, VPE etc. */
+#define SC_DPLLCTRL 0x1460 /* DDR memory */
/* PLL type: VPLL27 */
-#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500)
-#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520)
+#define SC_VPLL27FCTRL 0x1500
+#define SC_VPLL27ACTRL 0x1520
void uniphier_ld11_pll_init(void)
{
@@ -40,6 +40,6 @@
uniphier_ld20_vpll27_init(SC_VPLL27FCTRL);
uniphier_ld20_vpll27_init(SC_VPLL27ACTRL);
- writel(0, SC_CA53_GEARSET); /* Gear0: CPLL/2 */
- writel(SC_CA_GEARUPD, SC_CA53_GEARUPD);
+ writel(0, sc_base + SC_CA53_GEARSET); /* Gear0: CPLL/2 */
+ writel(SC_CA_GEARUPD, sc_base + SC_CA53_GEARUPD);
}
diff --git a/arch/arm/mach-uniphier/clk/pll-ld20.c b/arch/arm/mach-uniphier/clk/pll-ld20.c
index 682bd1e..04b3312 100644
--- a/arch/arm/mach-uniphier/clk/pll-ld20.c
+++ b/arch/arm/mach-uniphier/clk/pll-ld20.c
@@ -11,23 +11,23 @@
#include "pll.h"
/* PLL type: SSC */
-#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */
-#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */
-#define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* DSP */
-#define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* Video codec */
-#define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1440) /* VPE etc. */
-#define SC_GPPLLCTRL (SC_BASE_ADDR | 0x1450) /* GPU/Mali */
-#define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1460) /* DDR memory 0 */
-#define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1470) /* DDR memory 1 */
-#define SC_DPLL2CTRL (SC_BASE_ADDR | 0x1480) /* DDR memory 2 */
+#define SC_CPLLCTRL 0x1400 /* CPU/ARM */
+#define SC_SPLLCTRL 0x1410 /* misc */
+#define SC_SPLL2CTRL 0x1420 /* DSP */
+#define SC_MPLLCTRL 0x1430 /* Video codec */
+#define SC_VPPLLCTRL 0x1440 /* VPE etc. */
+#define SC_GPPLLCTRL 0x1450 /* GPU/Mali */
+#define SC_DPLL0CTRL 0x1460 /* DDR memory 0 */
+#define SC_DPLL1CTRL 0x1470 /* DDR memory 1 */
+#define SC_DPLL2CTRL 0x1480 /* DDR memory 2 */
/* PLL type: VPLL27 */
-#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500)
-#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520)
+#define SC_VPLL27FCTRL 0x1500
+#define SC_VPLL27ACTRL 0x1520
/* PLL type: DSPLL */
-#define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540)
-#define SC_A2PLLCTRL (SC_BASE_ADDR | 0x15C0)
+#define SC_VPLL8KCTRL 0x1540
+#define SC_A2PLLCTRL 0x15C0
void uniphier_ld20_pll_init(void)
{
diff --git a/arch/arm/mach-uniphier/clk/pll-ld4.c b/arch/arm/mach-uniphier/clk/pll-ld4.c
index 6a145a3..c66031b 100644
--- a/arch/arm/mach-uniphier/clk/pll-ld4.c
+++ b/arch/arm/mach-uniphier/clk/pll-ld4.c
@@ -16,14 +16,14 @@
{
u32 tmp, clk_mode_upll, clk_mode_axosel;
- tmp = readl(SG_PINMON0);
+ tmp = readl(sg_base + SG_PINMON0);
clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
/* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
- tmp = readl(SC_UPLLCTRL);
+ tmp = readl(sc_base + SC_UPLLCTRL);
tmp &= ~0x18000000;
- writel(tmp, SC_UPLLCTRL);
+ writel(tmp, sc_base + SC_UPLLCTRL);
if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
@@ -38,110 +38,110 @@
}
}
- writel(tmp, SC_UPLLCTRL);
+ writel(tmp, sc_base + SC_UPLLCTRL);
/* set 1 to K_LD(UPLLCTRL.bit[27]) */
tmp |= 0x08000000;
- writel(tmp, SC_UPLLCTRL);
+ writel(tmp, sc_base + SC_UPLLCTRL);
/* wait 10 usec */
udelay(10);
/* set 1 to SNRT(UPLLCTRL.bit[28]) */
tmp |= 0x10000000;
- writel(tmp, SC_UPLLCTRL);
+ writel(tmp, sc_base + SC_UPLLCTRL);
}
static void vpll_init(void)
{
u32 tmp, clk_mode_axosel;
- tmp = readl(SG_PINMON0);
+ tmp = readl(sg_base + SG_PINMON0);
clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
/* set 1 to VPLA27WP and VPLA27WP */
- tmp = readl(SC_VPLL27ACTRL);
+ tmp = readl(sc_base + SC_VPLL27ACTRL);
tmp |= 0x00000001;
- writel(tmp, SC_VPLL27ACTRL);
- tmp = readl(SC_VPLL27BCTRL);
+ writel(tmp, sc_base + SC_VPLL27ACTRL);
+ tmp = readl(sc_base + SC_VPLL27BCTRL);
tmp |= 0x00000001;
- writel(tmp, SC_VPLL27BCTRL);
+ writel(tmp, sc_base + SC_VPLL27BCTRL);
/* Set 0 to VPLA_K_LD and VPLB_K_LD */
- tmp = readl(SC_VPLL27ACTRL3);
+ tmp = readl(sc_base + SC_VPLL27ACTRL3);
tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
+ writel(tmp, sc_base + SC_VPLL27ACTRL3);
+ tmp = readl(sc_base + SC_VPLL27BCTRL3);
tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27BCTRL3);
+ writel(tmp, sc_base + SC_VPLL27BCTRL3);
/* Set 0 to VPLA_SNRST and VPLB_SNRST */
- tmp = readl(SC_VPLL27ACTRL2);
+ tmp = readl(sc_base + SC_VPLL27ACTRL2);
tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
+ writel(tmp, sc_base + SC_VPLL27ACTRL2);
+ tmp = readl(sc_base + SC_VPLL27BCTRL2);
tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27BCTRL2);
+ writel(tmp, sc_base + SC_VPLL27BCTRL2);
/* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
- tmp = readl(SC_VPLL27ACTRL2);
+ tmp = readl(sc_base + SC_VPLL27ACTRL2);
tmp &= ~0x0000007f;
tmp |= 0x00000020;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
+ writel(tmp, sc_base + SC_VPLL27ACTRL2);
+ tmp = readl(sc_base + SC_VPLL27BCTRL2);
tmp &= ~0x0000007f;
tmp |= 0x00000020;
- writel(tmp, SC_VPLL27BCTRL2);
+ writel(tmp, sc_base + SC_VPLL27BCTRL2);
if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
/* AXO: 25MHz */
- tmp = readl(SC_VPLL27ACTRL3);
+ tmp = readl(sc_base + SC_VPLL27ACTRL3);
tmp &= ~0x000fffff;
tmp |= 0x00066664;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
+ writel(tmp, sc_base + SC_VPLL27ACTRL3);
+ tmp = readl(sc_base + SC_VPLL27BCTRL3);
tmp &= ~0x000fffff;
tmp |= 0x00066664;
- writel(tmp, SC_VPLL27BCTRL3);
+ writel(tmp, sc_base + SC_VPLL27BCTRL3);
} else {
/* AXO: default 24.576MHz */
- tmp = readl(SC_VPLL27ACTRL3);
+ tmp = readl(sc_base + SC_VPLL27ACTRL3);
tmp &= ~0x000fffff;
tmp |= 0x000f5800;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
+ writel(tmp, sc_base + SC_VPLL27ACTRL3);
+ tmp = readl(sc_base + SC_VPLL27BCTRL3);
tmp &= ~0x000fffff;
tmp |= 0x000f5800;
- writel(tmp, SC_VPLL27BCTRL3);
+ writel(tmp, sc_base + SC_VPLL27BCTRL3);
}
/* Set 1 to VPLA_K_LD and VPLB_K_LD */
- tmp = readl(SC_VPLL27ACTRL3);
+ tmp = readl(sc_base + SC_VPLL27ACTRL3);
tmp |= 0x10000000;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
+ writel(tmp, sc_base + SC_VPLL27ACTRL3);
+ tmp = readl(sc_base + SC_VPLL27BCTRL3);
tmp |= 0x10000000;
- writel(tmp, SC_VPLL27BCTRL3);
+ writel(tmp, sc_base + SC_VPLL27BCTRL3);
/* wait 10 usec */
udelay(10);
/* Set 0 to VPLA_SNRST and VPLB_SNRST */
- tmp = readl(SC_VPLL27ACTRL2);
+ tmp = readl(sc_base + SC_VPLL27ACTRL2);
tmp |= 0x10000000;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
+ writel(tmp, sc_base + SC_VPLL27ACTRL2);
+ tmp = readl(sc_base + SC_VPLL27BCTRL2);
tmp |= 0x10000000;
- writel(tmp, SC_VPLL27BCTRL2);
+ writel(tmp, sc_base + SC_VPLL27BCTRL2);
/* set 0 to VPLA27WP and VPLA27WP */
- tmp = readl(SC_VPLL27ACTRL);
+ tmp = readl(sc_base + SC_VPLL27ACTRL);
tmp &= ~0x00000001;
- writel(tmp, SC_VPLL27ACTRL);
- tmp = readl(SC_VPLL27BCTRL);
+ writel(tmp, sc_base + SC_VPLL27ACTRL);
+ tmp = readl(sc_base + SC_VPLL27BCTRL);
tmp |= ~0x00000001;
- writel(tmp, SC_VPLL27BCTRL);
+ writel(tmp, sc_base + SC_VPLL27BCTRL);
}
void uniphier_ld4_pll_init(void)
diff --git a/arch/arm/mach-uniphier/clk/pll-pro4.c b/arch/arm/mach-uniphier/clk/pll-pro4.c
index 2ee2ed6..b7dc3e2 100644
--- a/arch/arm/mach-uniphier/clk/pll-pro4.c
+++ b/arch/arm/mach-uniphier/clk/pll-pro4.c
@@ -17,7 +17,7 @@
u32 tmp, clk_mode_axosel;
/* Set VPLL27A & VPLL27B */
- tmp = readl(SG_PINMON0);
+ tmp = readl(sg_base + SG_PINMON0);
clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
/* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */
@@ -26,80 +26,80 @@
return;
/* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
- tmp = readl(SC_VPLL27ACTRL);
+ tmp = readl(sc_base + SC_VPLL27ACTRL);
tmp |= 0x00000001;
- writel(tmp, SC_VPLL27ACTRL);
- tmp = readl(SC_VPLL27BCTRL);
+ writel(tmp, sc_base + SC_VPLL27ACTRL);
+ tmp = readl(sc_base + SC_VPLL27BCTRL);
tmp |= 0x00000001;
- writel(tmp, SC_VPLL27BCTRL);
+ writel(tmp, sc_base + SC_VPLL27BCTRL);
/* Unset VPLA_K_LD and VPLB_K_LD bit */
- tmp = readl(SC_VPLL27ACTRL3);
+ tmp = readl(sc_base + SC_VPLL27ACTRL3);
tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
+ writel(tmp, sc_base + SC_VPLL27ACTRL3);
+ tmp = readl(sc_base + SC_VPLL27BCTRL3);
tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27BCTRL3);
+ writel(tmp, sc_base + SC_VPLL27BCTRL3);
/* Set VPLA_M and VPLB_M to 0x20 */
- tmp = readl(SC_VPLL27ACTRL2);
+ tmp = readl(sc_base + SC_VPLL27ACTRL2);
tmp &= ~0x0000007f;
tmp |= 0x00000020;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
+ writel(tmp, sc_base + SC_VPLL27ACTRL2);
+ tmp = readl(sc_base + SC_VPLL27BCTRL2);
tmp &= ~0x0000007f;
tmp |= 0x00000020;
- writel(tmp, SC_VPLL27BCTRL2);
+ writel(tmp, sc_base + SC_VPLL27BCTRL2);
if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) {
/* Set VPLA_K and VPLB_K for AXO: 25MHz */
- tmp = readl(SC_VPLL27ACTRL3);
+ tmp = readl(sc_base + SC_VPLL27ACTRL3);
tmp &= ~0x000fffff;
tmp |= 0x00066666;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
+ writel(tmp, sc_base + SC_VPLL27ACTRL3);
+ tmp = readl(sc_base + SC_VPLL27BCTRL3);
tmp &= ~0x000fffff;
tmp |= 0x00066666;
- writel(tmp, SC_VPLL27BCTRL3);
+ writel(tmp, sc_base + SC_VPLL27BCTRL3);
} else {
/* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */
- tmp = readl(SC_VPLL27ACTRL3);
+ tmp = readl(sc_base + SC_VPLL27ACTRL3);
tmp &= ~0x000fffff;
tmp |= 0x000f5800;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
+ writel(tmp, sc_base + SC_VPLL27ACTRL3);
+ tmp = readl(sc_base + SC_VPLL27BCTRL3);
tmp &= ~0x000fffff;
tmp |= 0x000f5800;
- writel(tmp, SC_VPLL27BCTRL3);
+ writel(tmp, sc_base + SC_VPLL27BCTRL3);
}
/* wait 1 usec */
udelay(1);
/* Set VPLA_K_LD and VPLB_K_LD to load K parameters */
- tmp = readl(SC_VPLL27ACTRL3);
+ tmp = readl(sc_base + SC_VPLL27ACTRL3);
tmp |= 0x10000000;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
+ writel(tmp, sc_base + SC_VPLL27ACTRL3);
+ tmp = readl(sc_base + SC_VPLL27BCTRL3);
tmp |= 0x10000000;
- writel(tmp, SC_VPLL27BCTRL3);
+ writel(tmp, sc_base + SC_VPLL27BCTRL3);
/* Unset VPLA_SNRST and VPLB_SNRST bit */
- tmp = readl(SC_VPLL27ACTRL2);
+ tmp = readl(sc_base + SC_VPLL27ACTRL2);
tmp |= 0x10000000;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
+ writel(tmp, sc_base + SC_VPLL27ACTRL2);
+ tmp = readl(sc_base + SC_VPLL27BCTRL2);
tmp |= 0x10000000;
- writel(tmp, SC_VPLL27BCTRL2);
+ writel(tmp, sc_base + SC_VPLL27BCTRL2);
/* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
- tmp = readl(SC_VPLL27ACTRL);
+ tmp = readl(sc_base + SC_VPLL27ACTRL);
tmp &= ~0x00000001;
- writel(tmp, SC_VPLL27ACTRL);
- tmp = readl(SC_VPLL27BCTRL);
+ writel(tmp, sc_base + SC_VPLL27ACTRL);
+ tmp = readl(sc_base + SC_VPLL27BCTRL);
tmp &= ~0x00000001;
- writel(tmp, SC_VPLL27BCTRL);
+ writel(tmp, sc_base + SC_VPLL27BCTRL);
}
void uniphier_pro4_pll_init(void)
diff --git a/arch/arm/mach-uniphier/clk/pll-pxs3.c b/arch/arm/mach-uniphier/clk/pll-pxs3.c
index 5a1b1d2..278f530 100644
--- a/arch/arm/mach-uniphier/clk/pll-pxs3.c
+++ b/arch/arm/mach-uniphier/clk/pll-pxs3.c
@@ -10,25 +10,25 @@
#include "pll.h"
/* PLL type: SSC */
-#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */
-#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */
-#define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* DSP */
-#define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1430) /* VPE */
-#define SC_VGPLLCTRL (SC_BASE_ADDR | 0x1440)
-#define SC_DECPLLCTRL (SC_BASE_ADDR | 0x1450)
-#define SC_ENCPLLCTRL (SC_BASE_ADDR | 0x1460)
-#define SC_PXFPLLCTRL (SC_BASE_ADDR | 0x1470)
-#define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1480) /* DDR memory 0 */
-#define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1490) /* DDR memory 1 */
-#define SC_DPLL2CTRL (SC_BASE_ADDR | 0x14a0) /* DDR memory 2 */
-#define SC_VSPLLCTRL (SC_BASE_ADDR | 0x14c0)
+#define SC_CPLLCTRL 0x1400 /* CPU/ARM */
+#define SC_SPLLCTRL 0x1410 /* misc */
+#define SC_SPLL2CTRL 0x1420 /* DSP */
+#define SC_VPPLLCTRL 0x1430 /* VPE */
+#define SC_VGPLLCTRL 0x1440
+#define SC_DECPLLCTRL 0x1450
+#define SC_ENCPLLCTRL 0x1460
+#define SC_PXFPLLCTRL 0x1470
+#define SC_DPLL0CTRL 0x1480 /* DDR memory 0 */
+#define SC_DPLL1CTRL 0x1490 /* DDR memory 1 */
+#define SC_DPLL2CTRL 0x14a0 /* DDR memory 2 */
+#define SC_VSPLLCTRL 0x14c0
/* PLL type: VPLL27 */
-#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500)
-#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520)
+#define SC_VPLL27FCTRL 0x1500
+#define SC_VPLL27ACTRL 0x1520
/* PLL type: DSPLL */
-#define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540)
+#define SC_VPLL8KCTRL 0x1540
void uniphier_pxs3_pll_init(void)
{
diff --git a/arch/arm/mach-uniphier/cpu-info.c b/arch/arm/mach-uniphier/cpu-info.c
index 9f5f505..6a7b203 100644
--- a/arch/arm/mach-uniphier/cpu-info.c
+++ b/arch/arm/mach-uniphier/cpu-info.c
@@ -10,11 +10,17 @@
#include <linux/io.h>
#include <linux/printk.h>
+#include "base-address.h"
#include "soc-info.h"
int print_cpuinfo(void)
{
unsigned int id, model, rev, required_model = 1, required_rev = 1;
+ int ret;
+
+ ret = uniphier_base_address_init();
+ if (ret)
+ return ret;
id = uniphier_get_soc_id();
model = uniphier_get_soc_model();
diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart-ld6b.c b/arch/arm/mach-uniphier/debug-uart/debug-uart-ld6b.c
index 22d2caa..f64ff39 100644
--- a/arch/arm/mach-uniphier/debug-uart/debug-uart-ld6b.c
+++ b/arch/arm/mach-uniphier/debug-uart/debug-uart-ld6b.c
@@ -22,9 +22,9 @@
sg_set_pinsel(115, 0, 8, 4); /* TXD1 -> TXD1 */
sg_set_pinsel(113, 2, 8, 4); /* SBO0 -> TXD2 */
- tmp = readl(SC_CLKCTRL);
+ tmp = readl(sc_base + SC_CLKCTRL);
tmp |= SC_CLKCTRL_CEN_PERI;
- writel(tmp, SC_CLKCTRL);
+ writel(tmp, sc_base + SC_CLKCTRL);
return DIV_ROUND_CLOSEST(UNIPHIER_LD6B_UART_CLK, 16 * CONFIG_BAUDRATE);
}
diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart-pro4.c b/arch/arm/mach-uniphier/debug-uart/debug-uart-pro4.c
index 0d66299..79c6c10 100644
--- a/arch/arm/mach-uniphier/debug-uart/debug-uart-pro4.c
+++ b/arch/arm/mach-uniphier/debug-uart/debug-uart-pro4.c
@@ -20,11 +20,11 @@
sg_set_iectrl(0);
sg_set_pinsel(128, 0, 4, 8); /* TXD0 -> TXD0 */
- writel(1, SG_LOADPINCTRL);
+ writel(1, sg_base + SG_LOADPINCTRL);
- tmp = readl(SC_CLKCTRL);
+ tmp = readl(sc_base + SC_CLKCTRL);
tmp |= SC_CLKCTRL_CEN_PERI;
- writel(tmp, SC_CLKCTRL);
+ writel(tmp, sc_base + SC_CLKCTRL);
return DIV_ROUND_CLOSEST(UNIPHIER_PRO4_UART_CLK, 16 * CONFIG_BAUDRATE);
}
diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart-pro5.c b/arch/arm/mach-uniphier/debug-uart/debug-uart-pro5.c
index 1a0a942..ef3b383 100644
--- a/arch/arm/mach-uniphier/debug-uart/debug-uart-pro5.c
+++ b/arch/arm/mach-uniphier/debug-uart/debug-uart-pro5.c
@@ -23,11 +23,11 @@
sg_set_pinsel(51, 0, 4, 8); /* TXD2 -> TXD2 */
sg_set_pinsel(53, 0, 4, 8); /* TXD3 -> TXD3 */
- writel(1, SG_LOADPINCTRL);
+ writel(1, sg_base + SG_LOADPINCTRL);
- tmp = readl(SC_CLKCTRL);
+ tmp = readl(sc_base + SC_CLKCTRL);
tmp |= SC_CLKCTRL_CEN_PERI;
- writel(tmp, SC_CLKCTRL);
+ writel(tmp, sc_base + SC_CLKCTRL);
return DIV_ROUND_CLOSEST(UNIPHIER_PRO5_UART_CLK, 16 * CONFIG_BAUDRATE);
}
diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart-pxs2.c b/arch/arm/mach-uniphier/debug-uart/debug-uart-pxs2.c
index 5d50c4f..ee8caad 100644
--- a/arch/arm/mach-uniphier/debug-uart/debug-uart-pxs2.c
+++ b/arch/arm/mach-uniphier/debug-uart/debug-uart-pxs2.c
@@ -23,9 +23,9 @@
sg_set_pinsel(113, 8, 8, 4); /* TXD2 -> TXD2 */
sg_set_pinsel(219, 8, 8, 4); /* TXD3 -> TXD3 */
- tmp = readl(SC_CLKCTRL);
+ tmp = readl(sc_base + SC_CLKCTRL);
tmp |= SC_CLKCTRL_CEN_PERI;
- writel(tmp, SC_CLKCTRL);
+ writel(tmp, sc_base + SC_CLKCTRL);
return DIV_ROUND_CLOSEST(UNIPHIER_PXS2_UART_CLK, 16 * CONFIG_BAUDRATE);
}
diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart.c b/arch/arm/mach-uniphier/debug-uart/debug-uart.c
index bc96b2e..a70ce59 100644
--- a/arch/arm/mach-uniphier/debug-uart/debug-uart.c
+++ b/arch/arm/mach-uniphier/debug-uart/debug-uart.c
@@ -32,7 +32,8 @@
unsigned int mux_bits, unsigned int reg_stride)
{
unsigned int shift = pin * mux_bits % 32;
- unsigned long reg = SG_PINCTRL_BASE + pin * mux_bits / 32 * reg_stride;
+ void __iomem *reg = sg_base + SG_PINCTRL_BASE +
+ pin * mux_bits / 32 * reg_stride;
u32 mask = (1U << mux_bits) - 1;
u32 tmp;
@@ -45,7 +46,7 @@
void sg_set_iectrl(unsigned int pin)
{
unsigned int bit = pin % 32;
- unsigned long reg = SG_IECTRL + pin / 32 * 4;
+ void __iomem *reg = sg_base + SG_IECTRL + pin / 32 * 4;
u32 tmp;
tmp = readl(reg);
diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c
index fa4b3e3..13821a9 100644
--- a/arch/arm/mach-uniphier/dram_init.c
+++ b/arch/arm/mach-uniphier/dram_init.c
@@ -13,82 +13,27 @@
#include <linux/sizes.h>
#include <asm/global_data.h>
+#include "init.h"
#include "sg-regs.h"
#include "soc-info.h"
DECLARE_GLOBAL_DATA_PTR;
-struct uniphier_memif_data {
- unsigned int soc_id;
- unsigned long sparse_ch1_base;
- int have_ch2;
-};
-
-static const struct uniphier_memif_data uniphier_memif_data[] = {
- {
- .soc_id = UNIPHIER_LD4_ID,
- .sparse_ch1_base = 0xc0000000,
- },
- {
- .soc_id = UNIPHIER_PRO4_ID,
- .sparse_ch1_base = 0xa0000000,
- },
- {
- .soc_id = UNIPHIER_SLD8_ID,
- .sparse_ch1_base = 0xc0000000,
- },
- {
- .soc_id = UNIPHIER_PRO5_ID,
- .sparse_ch1_base = 0xc0000000,
- },
- {
- .soc_id = UNIPHIER_PXS2_ID,
- .sparse_ch1_base = 0xc0000000,
- .have_ch2 = 1,
- },
- {
- .soc_id = UNIPHIER_LD6B_ID,
- .sparse_ch1_base = 0xc0000000,
- .have_ch2 = 1,
- },
- {
- .soc_id = UNIPHIER_LD11_ID,
- .sparse_ch1_base = 0xc0000000,
- },
- {
- .soc_id = UNIPHIER_LD20_ID,
- .sparse_ch1_base = 0xc0000000,
- .have_ch2 = 1,
- },
- {
- .soc_id = UNIPHIER_PXS3_ID,
- .sparse_ch1_base = 0xc0000000,
- .have_ch2 = 1,
- },
-};
-UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_memif_data, uniphier_memif_data)
-
struct uniphier_dram_map {
unsigned long base;
unsigned long size;
};
-static int uniphier_memconf_decode(struct uniphier_dram_map *dram_map)
+static int uniphier_memconf_decode(struct uniphier_dram_map *dram_map,
+ unsigned long sparse_ch1_base, bool have_ch2)
{
- const struct uniphier_memif_data *data;
unsigned long size;
u32 val;
- data = uniphier_get_memif_data();
- if (!data) {
- pr_err("unsupported SoC\n");
- return -EINVAL;
- }
-
- val = readl(SG_MEMCONF);
+ val = readl(sg_base + SG_MEMCONF);
/* set up ch0 */
- dram_map[0].base = CONFIG_SYS_SDRAM_BASE;
+ dram_map[0].base = 0x80000000;
switch (val & SG_MEMCONF_CH0_SZ_MASK) {
case SG_MEMCONF_CH0_SZ_64M:
@@ -120,14 +65,14 @@
dram_map[1].base = dram_map[0].base + size;
if (val & SG_MEMCONF_SPARSEMEM) {
- if (dram_map[1].base > data->sparse_ch1_base) {
+ if (dram_map[1].base > sparse_ch1_base) {
pr_warn("Sparse mem is enabled, but ch0 and ch1 overlap\n");
pr_warn("Only ch0 is available\n");
dram_map[1].base = 0;
return 0;
}
- dram_map[1].base = data->sparse_ch1_base;
+ dram_map[1].base = sparse_ch1_base;
}
switch (val & SG_MEMCONF_CH1_SZ_MASK) {
@@ -156,7 +101,7 @@
dram_map[1].size = size;
- if (!data->have_ch2 || val & SG_MEMCONF_CH2_DISABLE)
+ if (!have_ch2 || val & SG_MEMCONF_CH2_DISABLE)
return 0;
/* set up ch2 */
@@ -191,14 +136,90 @@
return 0;
}
+static int uniphier_ld4_dram_map_get(struct uniphier_dram_map dram_map[])
+{
+ return uniphier_memconf_decode(dram_map, 0xc0000000, false);
+}
+
+static int uniphier_pro4_dram_map_get(struct uniphier_dram_map dram_map[])
+{
+ return uniphier_memconf_decode(dram_map, 0xa0000000, false);
+}
+
+static int uniphier_pxs2_dram_map_get(struct uniphier_dram_map dram_map[])
+{
+ return uniphier_memconf_decode(dram_map, 0xc0000000, true);
+}
+
+struct uniphier_dram_init_data {
+ unsigned int soc_id;
+ int (*dram_map_get)(struct uniphier_dram_map dram_map[]);
+};
+
+static const struct uniphier_dram_init_data uniphier_dram_init_data[] = {
+ {
+ .soc_id = UNIPHIER_LD4_ID,
+ .dram_map_get = uniphier_ld4_dram_map_get,
+ },
+ {
+ .soc_id = UNIPHIER_PRO4_ID,
+ .dram_map_get = uniphier_pro4_dram_map_get,
+ },
+ {
+ .soc_id = UNIPHIER_SLD8_ID,
+ .dram_map_get = uniphier_ld4_dram_map_get,
+ },
+ {
+ .soc_id = UNIPHIER_PRO5_ID,
+ .dram_map_get = uniphier_ld4_dram_map_get,
+ },
+ {
+ .soc_id = UNIPHIER_PXS2_ID,
+ .dram_map_get = uniphier_pxs2_dram_map_get,
+ },
+ {
+ .soc_id = UNIPHIER_LD6B_ID,
+ .dram_map_get = uniphier_pxs2_dram_map_get,
+ },
+ {
+ .soc_id = UNIPHIER_LD11_ID,
+ .dram_map_get = uniphier_ld4_dram_map_get,
+ },
+ {
+ .soc_id = UNIPHIER_LD20_ID,
+ .dram_map_get = uniphier_pxs2_dram_map_get,
+ },
+ {
+ .soc_id = UNIPHIER_PXS3_ID,
+ .dram_map_get = uniphier_pxs2_dram_map_get,
+ },
+};
+UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_dram_init_data,
+ uniphier_dram_init_data)
+
+static int uniphier_dram_map_get(struct uniphier_dram_map *dram_map)
+{
+ const struct uniphier_dram_init_data *data;
+
+ data = uniphier_get_dram_init_data();
+ if (!data) {
+ pr_err("unsupported SoC\n");
+ return -ENOTSUPP;
+ }
+
+ return data->dram_map_get(dram_map);
+}
+
int dram_init(void)
{
struct uniphier_dram_map dram_map[3] = {};
+ bool valid_bank_found = false;
+ unsigned long prev_top;
int ret, i;
gd->ram_size = 0;
- ret = uniphier_memconf_decode(dram_map);
+ ret = uniphier_dram_map_get(dram_map);
if (ret)
return ret;
@@ -206,15 +227,14 @@
unsigned long max_size;
if (!dram_map[i].size)
- break;
+ continue;
/*
* U-Boot relocates itself to the tail of the memory region,
* but it does not expect sparse memory. We use the first
* contiguous chunk here.
*/
- if (i > 0 && dram_map[i - 1].base + dram_map[i - 1].size <
- dram_map[i].base)
+ if (valid_bank_found && prev_top < dram_map[i].base)
break;
/*
@@ -234,6 +254,12 @@
}
gd->ram_size += dram_map[i].size;
+
+ if (!valid_bank_found)
+ gd->ram_base = dram_map[i].base;
+
+ prev_top = dram_map[i].base + dram_map[i].size;
+ valid_bank_found = true;
}
/*
@@ -249,17 +275,34 @@
int dram_init_banksize(void)
{
struct uniphier_dram_map dram_map[3] = {};
- int i;
+ unsigned long base, top;
+ bool valid_bank_found = false;
+ int ret, i;
- uniphier_memconf_decode(dram_map);
+ ret = uniphier_dram_map_get(dram_map);
+ if (ret)
+ return ret;
for (i = 0; i < ARRAY_SIZE(dram_map); i++) {
- if (i >= ARRAY_SIZE(gd->bd->bi_dram))
- break;
+ if (i < ARRAY_SIZE(gd->bd->bi_dram)) {
+ gd->bd->bi_dram[i].start = dram_map[i].base;
+ gd->bd->bi_dram[i].size = dram_map[i].size;
+ }
- gd->bd->bi_dram[i].start = dram_map[i].base;
- gd->bd->bi_dram[i].size = dram_map[i].size;
+ if (!dram_map[i].size)
+ continue;
+
+ if (!valid_bank_found)
+ base = dram_map[i].base;
+ top = dram_map[i].base + dram_map[i].size;
+ valid_bank_found = true;
}
+ if (!valid_bank_found)
+ return -EINVAL;
+
+ /* map all the DRAM regions */
+ uniphier_mem_map_init(base, top - base);
+
return 0;
}
diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h
index c6b3f36..b37ab2f 100644
--- a/arch/arm/mach-uniphier/init.h
+++ b/arch/arm/mach-uniphier/init.h
@@ -102,5 +102,13 @@
int uniphier_have_internal_stm(void);
int uniphier_boot_from_backend(void);
int uniphier_pin_init(const char *pinconfig_name);
+#ifdef CONFIG_ARM64
+void uniphier_mem_map_init(unsigned long dram_base, unsigned long dram_size);
+#else
+static inline void uniphier_mem_map_init(unsigned long dram_base,
+ unsigned long dram_size)
+{
+}
+#endif
#endif /* __MACH_INIT_H */
diff --git a/arch/arm/mach-uniphier/memconf.c b/arch/arm/mach-uniphier/memconf.c
index 8105368..f69b489 100644
--- a/arch/arm/mach-uniphier/memconf.c
+++ b/arch/arm/mach-uniphier/memconf.c
@@ -140,7 +140,7 @@
}
out:
- writel(val, SG_MEMCONF);
+ writel(val, sg_base + SG_MEMCONF);
return 0;
}
diff --git a/arch/arm/mach-uniphier/micro-support-card.c b/arch/arm/mach-uniphier/micro-support-card.c
index 1be5685..4687901 100644
--- a/arch/arm/mach-uniphier/micro-support-card.c
+++ b/arch/arm/mach-uniphier/micro-support-card.c
@@ -18,6 +18,25 @@
#define MICRO_SUPPORT_CARD_RESET ((MICRO_SUPPORT_CARD_BASE) + 0xd0034)
#define MICRO_SUPPORT_CARD_REVISION ((MICRO_SUPPORT_CARD_BASE) + 0xd00E0)
+static bool support_card_found;
+
+static void support_card_detect(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ const void *fdt = gd->fdt_blob;
+ int offset;
+
+ offset = fdt_node_offset_by_compatible(fdt, 0, "smsc,lan9118");
+ if (offset < 0)
+ return;
+
+ offset = fdt_node_offset_by_compatible(fdt, 0, "ns16550a");
+ if (offset < 0)
+ return;
+
+ support_card_found = true;
+}
+
/*
* 0: reset deassert, 1: reset
*
@@ -51,6 +70,11 @@
void support_card_init(void)
{
+ support_card_detect();
+
+ if (!support_card_found)
+ return;
+
support_card_reset();
/*
* After power on, we need to keep the LAN controller in reset state
@@ -67,6 +91,9 @@
int board_eth_init(bd_t *bis)
{
+ if (!support_card_found)
+ return 0;
+
return smc911x_initialize(0, SMC911X_BASE);
}
#endif
@@ -161,6 +188,9 @@
void support_card_late_init(void)
{
+ if (!support_card_found)
+ return;
+
detect_num_flash_banks();
}
@@ -221,6 +251,9 @@
int i;
u32 val = 0;
+ if (!support_card_found)
+ return;
+
if (!s)
return;
diff --git a/arch/arm/mach-uniphier/mmc-first-dev.c b/arch/arm/mach-uniphier/mmc-first-dev.c
index 2f1c109..149e662 100644
--- a/arch/arm/mach-uniphier/mmc-first-dev.c
+++ b/arch/arm/mach-uniphier/mmc-first-dev.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
+#include <env.h>
#include <mmc.h>
#include <linux/errno.h>
diff --git a/arch/arm/mach-uniphier/reset.c b/arch/arm/mach-uniphier/reset.c
index 28c95e2..31685d0 100644
--- a/arch/arm/mach-uniphier/reset.c
+++ b/arch/arm/mach-uniphier/reset.c
@@ -22,14 +22,14 @@
{
u32 tmp;
- writel(5, SC_IRQTIMSET); /* default value */
+ writel(5, sc_base + SC_IRQTIMSET); /* default value */
- tmp = readl(SC_SLFRSTSEL);
+ tmp = readl(sc_base + SC_SLFRSTSEL);
tmp &= ~0x3; /* mask [1:0] */
tmp |= 0x0; /* XRST reboot */
- writel(tmp, SC_SLFRSTSEL);
+ writel(tmp, sc_base + SC_SLFRSTSEL);
- tmp = readl(SC_SLFRSTCTL);
+ tmp = readl(sc_base + SC_SLFRSTCTL);
tmp |= 0x1;
- writel(tmp, SC_SLFRSTCTL);
+ writel(tmp, sc_base + SC_SLFRSTCTL);
}
diff --git a/arch/arm/mach-uniphier/sbc/Makefile b/arch/arm/mach-uniphier/sbc/Makefile
index 912e05a..6c698a3 100644
--- a/arch/arm/mach-uniphier/sbc/Makefile
+++ b/arch/arm/mach-uniphier/sbc/Makefile
@@ -1,5 +1,8 @@
# SPDX-License-Identifier: GPL-2.0+
+obj-y += sbc-boot.o
+
+ifndef CONFIG_SPL_BUILD
obj-y += sbc.o
obj-$(CONFIG_ARCH_UNIPHIER_LD4) += sbc-ld4.o
@@ -9,3 +12,4 @@
obj-$(CONFIG_ARCH_UNIPHIER_LD11) += sbc-ld11.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += sbc-ld11.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS3) += sbc-pxs2.o
+endif
diff --git a/arch/arm/mach-uniphier/sbc/sbc-boot.c b/arch/arm/mach-uniphier/sbc/sbc-boot.c
new file mode 100644
index 0000000..ec22b45
--- /dev/null
+++ b/arch/arm/mach-uniphier/sbc/sbc-boot.c
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright (C) 2011-2014 Panasonic Corporation
+// Copyright (C) 2015-2019 Socionext Inc.
+
+#include <linux/io.h>
+
+#include "sbc-regs.h"
+
+int uniphier_sbc_boot_is_swapped(void)
+{
+ return !(readl(SBBASE0) & SBBASE_BANK_ENABLE);
+}
diff --git a/arch/arm/mach-uniphier/sbc/sbc-ld11.c b/arch/arm/mach-uniphier/sbc/sbc-ld11.c
index 44d8a1e..21972ac 100644
--- a/arch/arm/mach-uniphier/sbc/sbc-ld11.c
+++ b/arch/arm/mach-uniphier/sbc/sbc-ld11.c
@@ -12,6 +12,9 @@
void uniphier_ld11_sbc_init(void)
{
+ if (!uniphier_sbc_is_enabled())
+ return;
+
uniphier_sbc_init_savepin();
/* necessary for ROM boot ?? */
diff --git a/arch/arm/mach-uniphier/sbc/sbc-ld4.c b/arch/arm/mach-uniphier/sbc/sbc-ld4.c
index d08b571..72e9743 100644
--- a/arch/arm/mach-uniphier/sbc/sbc-ld4.c
+++ b/arch/arm/mach-uniphier/sbc/sbc-ld4.c
@@ -13,6 +13,9 @@
{
u32 tmp;
+ if (!uniphier_sbc_is_enabled())
+ return;
+
uniphier_sbc_init_savepin();
/* system bus output enable */
diff --git a/arch/arm/mach-uniphier/sbc/sbc-pxs2.c b/arch/arm/mach-uniphier/sbc/sbc-pxs2.c
index 8c167ef..3275f22 100644
--- a/arch/arm/mach-uniphier/sbc/sbc-pxs2.c
+++ b/arch/arm/mach-uniphier/sbc/sbc-pxs2.c
@@ -10,6 +10,9 @@
void uniphier_pxs2_sbc_init(void)
{
+ if (!uniphier_sbc_is_enabled())
+ return;
+
uniphier_sbc_init_savepin();
/* necessary for ROM boot ?? */
diff --git a/arch/arm/mach-uniphier/sbc/sbc-regs.h b/arch/arm/mach-uniphier/sbc/sbc-regs.h
index 853015a..1e96186 100644
--- a/arch/arm/mach-uniphier/sbc/sbc-regs.h
+++ b/arch/arm/mach-uniphier/sbc/sbc-regs.h
@@ -76,12 +76,7 @@
#define PC0CTRL 0x598000c0
-#ifndef __ASSEMBLY__
-#include <linux/io.h>
-static inline int boot_is_swapped(void)
-{
- return !(readl(SBBASE0) & SBBASE_BANK_ENABLE);
-}
-#endif
+int uniphier_sbc_boot_is_swapped(void);
+int uniphier_sbc_is_enabled(void);
#endif /* ARCH_SBC_REGS_H */
diff --git a/arch/arm/mach-uniphier/sbc/sbc.c b/arch/arm/mach-uniphier/sbc/sbc.c
index df01e5c..af8d6f4 100644
--- a/arch/arm/mach-uniphier/sbc/sbc.c
+++ b/arch/arm/mach-uniphier/sbc/sbc.c
@@ -5,7 +5,9 @@
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*/
+#include <common.h>
#include <linux/io.h>
+#include <asm/global_data.h>
#include "../init.h"
#include "sbc-regs.h"
@@ -31,6 +33,20 @@
#define SBCTRL2_SAVEPIN_MEM_VALUE 0x34000009
#define SBCTRL4_SAVEPIN_MEM_VALUE 0x02110210
+int uniphier_sbc_is_enabled(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ const void *fdt = gd->fdt_blob;
+ int offset;
+
+ offset = fdt_node_offset_by_compatible(fdt, 0,
+ "socionext,uniphier-system-bus");
+ if (offset < 0)
+ return 0;
+
+ return fdtdec_get_is_enabled(fdt, offset);
+}
+
static void __uniphier_sbc_init(int savepin)
{
/*
@@ -48,7 +64,7 @@
writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12);
}
- if (boot_is_swapped()) {
+ if (uniphier_sbc_boot_is_swapped()) {
/*
* Boot Swap On: boot from external NOR/SRAM
* 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
diff --git a/arch/arm/mach-uniphier/sc-regs.h b/arch/arm/mach-uniphier/sc-regs.h
index 28de19c..e43116e 100644
--- a/arch/arm/mach-uniphier/sc-regs.h
+++ b/arch/arm/mach-uniphier/sc-regs.h
@@ -10,31 +10,36 @@
#ifndef ARCH_SC_REGS_H
#define ARCH_SC_REGS_H
-#define SC_BASE_ADDR 0x61840000
+#ifndef __ASSEMBLY__
+#include <linux/compiler.h>
+#define sc_base ((void __iomem *)SC_BASE)
+#endif
-#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1200)
+#define SC_BASE 0x61840000
+
+#define SC_DPLLCTRL 0x1200
#define SC_DPLLCTRL_SSC_EN (0x1 << 31)
#define SC_DPLLCTRL_FOUTMODE_MASK (0xf << 16)
#define SC_DPLLCTRL_SSC_RATE (0x1 << 15)
-#define SC_DPLLCTRL2 (SC_BASE_ADDR | 0x1204)
+#define SC_DPLLCTRL2 0x1204
#define SC_DPLLCTRL2_NRSTDS (0x1 << 28)
-#define SC_DPLLCTRL3 (SC_BASE_ADDR | 0x1208)
+#define SC_DPLLCTRL3 0x1208
#define SC_DPLLCTRL3_LPFSEL_COEF2 (0x0 << 31)
#define SC_DPLLCTRL3_LPFSEL_COEF3 (0x1 << 31)
-#define SC_UPLLCTRL (SC_BASE_ADDR | 0x1210)
+#define SC_UPLLCTRL 0x1210
-#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1270)
-#define SC_VPLL27ACTRL2 (SC_BASE_ADDR | 0x1274)
-#define SC_VPLL27ACTRL3 (SC_BASE_ADDR | 0x1278)
+#define SC_VPLL27ACTRL 0x1270
+#define SC_VPLL27ACTRL2 0x1274
+#define SC_VPLL27ACTRL3 0x1278
-#define SC_VPLL27BCTRL (SC_BASE_ADDR | 0x1290)
-#define SC_VPLL27BCTRL2 (SC_BASE_ADDR | 0x1294)
-#define SC_VPLL27BCTRL3 (SC_BASE_ADDR | 0x1298)
+#define SC_VPLL27BCTRL 0x1290
+#define SC_VPLL27BCTRL2 0x1294
+#define SC_VPLL27BCTRL3 0x1298
-#define SC_RSTCTRL (SC_BASE_ADDR | 0x2000)
+#define SC_RSTCTRL 0x2000
#define SC_RSTCTRL_NRST_USB3B0 (0x1 << 17) /* USB3 #0 bus */
#define SC_RSTCTRL_NRST_USB3C0 (0x1 << 16) /* USB3 #0 core */
#define SC_RSTCTRL_NRST_ETHER (0x1 << 12)
@@ -44,14 +49,14 @@
#define SC_RSTCTRL_NRST_UMC0 (0x1 << 4)
#define SC_RSTCTRL_NRST_NAND (0x1 << 2)
-#define SC_RSTCTRL2 (SC_BASE_ADDR | 0x2004)
+#define SC_RSTCTRL2 0x2004
#define SC_RSTCTRL2_NRST_USB3B1 (0x1 << 17) /* USB3 #1 bus */
#define SC_RSTCTRL2_NRST_USB3C1 (0x1 << 16) /* USB3 #1 core */
-#define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008)
+#define SC_RSTCTRL3 0x2008
/* Pro5 or newer */
-#define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c)
+#define SC_RSTCTRL4 0x200c
#define SC_RSTCTRL4_NRST_UMCSB (0x1 << 12) /* UMC system bus */
#define SC_RSTCTRL4_NRST_UMCA2 (0x1 << 10) /* UMC ch2 standby */
#define SC_RSTCTRL4_NRST_UMCA1 (0x1 << 9) /* UMC ch1 standby */
@@ -60,11 +65,11 @@
#define SC_RSTCTRL4_NRST_UMC31 (0x1 << 5) /* UMC ch1 */
#define SC_RSTCTRL4_NRST_UMC30 (0x1 << 4) /* UMC ch0 */
-#define SC_RSTCTRL5 (SC_BASE_ADDR | 0x2010)
+#define SC_RSTCTRL5 0x2010
-#define SC_RSTCTRL6 (SC_BASE_ADDR | 0x2014)
+#define SC_RSTCTRL6 0x2014
-#define SC_CLKCTRL (SC_BASE_ADDR | 0x2104)
+#define SC_CLKCTRL 0x2104
#define SC_CLKCTRL_CEN_USB31 (0x1 << 17) /* USB3 #1 */
#define SC_CLKCTRL_CEN_USB30 (0x1 << 16) /* USB3 #0 */
#define SC_CLKCTRL_CEN_ETHER (0x1 << 12)
@@ -76,15 +81,15 @@
#define SC_CLKCTRL_CEN_PERI (0x1 << 0)
/* Pro5 or newer */
-#define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c)
+#define SC_CLKCTRL4 0x210c
#define SC_CLKCTRL4_CEN_UMCSB (0x1 << 12) /* UMC system bus */
#define SC_CLKCTRL4_CEN_UMC2 (0x1 << 2) /* UMC ch2 */
#define SC_CLKCTRL4_CEN_UMC1 (0x1 << 1) /* UMC ch1 */
#define SC_CLKCTRL4_CEN_UMC0 (0x1 << 0) /* UMC ch0 */
/* System reset control register */
-#define SC_IRQTIMSET (SC_BASE_ADDR | 0x3000)
-#define SC_SLFRSTSEL (SC_BASE_ADDR | 0x3010)
-#define SC_SLFRSTCTL (SC_BASE_ADDR | 0x3014)
+#define SC_IRQTIMSET 0x3000
+#define SC_SLFRSTSEL 0x3010
+#define SC_SLFRSTCTL 0x3014
#endif /* ARCH_SC_REGS_H */
diff --git a/arch/arm/mach-uniphier/sc64-regs.h b/arch/arm/mach-uniphier/sc64-regs.h
index 83f34e3..fdcca23 100644
--- a/arch/arm/mach-uniphier/sc64-regs.h
+++ b/arch/arm/mach-uniphier/sc64-regs.h
@@ -9,28 +9,33 @@
#ifndef SC64_REGS_H
#define SC64_REGS_H
-#define SC_BASE_ADDR 0x61840000
+#ifndef __ASSEMBLY__
+#include <linux/compiler.h>
+extern void __iomem *sc_base;
+#endif
-#define SC_RSTCTRL (SC_BASE_ADDR | 0x2000)
-#define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008)
-#define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c)
-#define SC_RSTCTRL5 (SC_BASE_ADDR | 0x2010)
-#define SC_RSTCTRL6 (SC_BASE_ADDR | 0x2014)
-#define SC_RSTCTRL7 (SC_BASE_ADDR | 0x2018)
+#define SC_BASE 0x61840000
-#define SC_CLKCTRL (SC_BASE_ADDR | 0x2100)
-#define SC_CLKCTRL3 (SC_BASE_ADDR | 0x2108)
-#define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c)
-#define SC_CLKCTRL5 (SC_BASE_ADDR | 0x2110)
-#define SC_CLKCTRL6 (SC_BASE_ADDR | 0x2114)
-#define SC_CLKCTRL7 (SC_BASE_ADDR | 0x2118)
+#define SC_RSTCTRL 0x2000
+#define SC_RSTCTRL3 0x2008
+#define SC_RSTCTRL4 0x200c
+#define SC_RSTCTRL5 0x2010
+#define SC_RSTCTRL6 0x2014
+#define SC_RSTCTRL7 0x2018
-#define SC_CA72_GEARST (SC_BASE_ADDR | 0x8000)
-#define SC_CA72_GEARSET (SC_BASE_ADDR | 0x8004)
-#define SC_CA72_GEARUPD (SC_BASE_ADDR | 0x8008)
-#define SC_CA53_GEARST (SC_BASE_ADDR | 0x8080)
-#define SC_CA53_GEARSET (SC_BASE_ADDR | 0x8084)
-#define SC_CA53_GEARUPD (SC_BASE_ADDR | 0x8088)
+#define SC_CLKCTRL 0x2100
+#define SC_CLKCTRL3 0x2108
+#define SC_CLKCTRL4 0x210c
+#define SC_CLKCTRL5 0x2110
+#define SC_CLKCTRL6 0x2114
+#define SC_CLKCTRL7 0x2118
+
+#define SC_CA72_GEARST 0x8000
+#define SC_CA72_GEARSET 0x8004
+#define SC_CA72_GEARUPD 0x8008
+#define SC_CA53_GEARST 0x8080
+#define SC_CA53_GEARSET 0x8084
+#define SC_CA53_GEARUPD 0x8088
#define SC_CA_GEARUPD (1 << 0)
#endif /* SC64_REGS_H */
diff --git a/arch/arm/mach-uniphier/sg-regs.h b/arch/arm/mach-uniphier/sg-regs.h
index 39ffed5..f47d101 100644
--- a/arch/arm/mach-uniphier/sg-regs.h
+++ b/arch/arm/mach-uniphier/sg-regs.h
@@ -10,15 +10,23 @@
#ifndef UNIPHIER_SG_REGS_H
#define UNIPHIER_SG_REGS_H
+#ifndef __ASSEMBLY__
+#include <linux/compiler.h>
+#ifdef CONFIG_ARCH_UNIPHIER_V8_MULTI
+extern void __iomem *sg_base;
+#else
+#define sg_base ((void __iomem *)SG_BASE)
+#endif
+#endif /* __ASSEMBLY__ */
+
/* Base Address */
-#define SG_CTRL_BASE 0x5f800000
-#define SG_DBG_BASE 0x5f900000
+#define SG_BASE 0x5f800000
/* Revision */
-#define SG_REVISION (SG_CTRL_BASE | 0x0000)
+#define SG_REVISION 0x0000
/* Memory Configuration */
-#define SG_MEMCONF (SG_CTRL_BASE | 0x0400)
+#define SG_MEMCONF 0x0400
#define SG_MEMCONF_CH0_SZ_MASK ((0x1 << 10) | (0x03 << 0))
#define SG_MEMCONF_CH0_SZ_64M ((0x0 << 10) | (0x01 << 0))
@@ -54,22 +62,22 @@
#define SG_MEMCONF_SPARSEMEM (0x1 << 4)
-#define SG_USBPHYCTRL (SG_CTRL_BASE | 0x500)
-#define SG_ETPHYPSHUT (SG_CTRL_BASE | 0x554)
-#define SG_ETPHYCNT (SG_CTRL_BASE | 0x550)
+#define SG_USBPHYCTRL 0x0500
+#define SG_ETPHYPSHUT 0x0554
+#define SG_ETPHYCNT 0x0550
/* Pin Control */
-#define SG_PINCTRL_BASE (SG_CTRL_BASE | 0x1000)
+#define SG_PINCTRL_BASE 0x1000
/* PH1-Pro4, PH1-Pro5 */
-#define SG_LOADPINCTRL (SG_CTRL_BASE | 0x1700)
+#define SG_LOADPINCTRL 0x1700
/* Input Enable */
-#define SG_IECTRL (SG_CTRL_BASE | 0x1d00)
+#define SG_IECTRL 0x1d00
/* Pin Monitor */
-#define SG_PINMON0 (SG_DBG_BASE | 0x0100)
-#define SG_PINMON2 (SG_DBG_BASE | 0x0108)
+#define SG_PINMON0 0x00100100
+#define SG_PINMON2 0x00100108
#define SG_PINMON0_CLK_MODE_UPLLSRC_MASK (0x3 << 19)
#define SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT (0x0 << 19)
diff --git a/arch/arm/mach-uniphier/soc-info.c b/arch/arm/mach-uniphier/soc-info.c
index ce2d4b6..f021a8c 100644
--- a/arch/arm/mach-uniphier/soc-info.c
+++ b/arch/arm/mach-uniphier/soc-info.c
@@ -13,7 +13,7 @@
static unsigned int __uniphier_get_revision_field(unsigned int mask,
unsigned int shift)
{
- u32 revision = readl(SG_REVISION);
+ u32 revision = readl(sg_base + SG_REVISION);
return (revision >> shift) & mask;
}
diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig
index 9bb5a5c..6cf17eb 100644
--- a/arch/arm/mach-zynqmp/Kconfig
+++ b/arch/arm/mach-zynqmp/Kconfig
@@ -65,6 +65,24 @@
Include external PMUFW (Platform Management Unit FirmWare) to
a Xilinx bootable image (boot.bin).
+config ZYNQMP_SPL_PM_CFG_OBJ_FILE
+ string "PMU firmware configuration object to load at runtime by SPL"
+ depends on SPL
+ help
+ Path to a binary PMU firmware configuration object to be linked
+ into U-Boot SPL and loaded at runtime into the PMU firmware.
+
+ The ZynqMP Power Management Unit (PMU) needs a configuration
+ object for most SoC peripherals to work. To have it loaded by
+ U-Boot SPL set here the file name (absolute path or relative to
+ the top source tree) of your configuration, which must be a
+ binary blob. It will be linked in the SPL binary and loaded
+ into the PMU firmware by U-Boot SPL during board
+ initialization.
+
+ Leave this option empty if your PMU firmware has a hard-coded
+ configuration object or you are loading it by any other means.
+
config ZYNQMP_USB
bool "Configure ZynqMP USB"
diff --git a/arch/arm/mach-zynqmp/Makefile b/arch/arm/mach-zynqmp/Makefile
index 8a3b074..f3765e4 100644
--- a/arch/arm/mach-zynqmp/Makefile
+++ b/arch/arm/mach-zynqmp/Makefile
@@ -8,3 +8,7 @@
obj-$(CONFIG_MP) += mp.o
obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o
obj-$(CONFIG_ZYNQMP_PSU_INIT_ENABLED) += psu_spl_init.o
+
+ifneq ($(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE),"")
+obj-$(CONFIG_SPL_BUILD) += pmu_ipc.o
+endif
diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h
index 385c882..915badc 100644
--- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h
+++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h
@@ -72,4 +72,6 @@
void tcm_init(u8 mode);
#endif
+void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size);
+
#endif /* _ASM_ARCH_SYS_PROTO_H */
diff --git a/arch/arm/mach-zynqmp/pmu_ipc.c b/arch/arm/mach-zynqmp/pmu_ipc.c
new file mode 100644
index 0000000..d8858ea
--- /dev/null
+++ b/arch/arm/mach-zynqmp/pmu_ipc.c
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Inter-Processor Communication with the Platform Management Unit (PMU)
+ * firmware.
+ *
+ * (C) Copyright 2019 Luca Ceresoli
+ * Luca Ceresoli <luca@lucaceresoli.net>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+
+/* IPI bitmasks, register base and register offsets */
+#define IPI_BIT_MASK_APU 0x00001
+#define IPI_BIT_MASK_PMU0 0x10000
+#define IPI_REG_BASE_APU 0xFF300000
+#define IPI_REG_BASE_PMU0 0xFF330000
+#define IPI_REG_OFFSET_TRIG 0x00
+#define IPI_REG_OFFSET_OBR 0x04
+
+/* IPI mailbox buffer offsets */
+#define IPI_BUF_BASE_APU 0xFF990400
+#define IPI_BUF_OFFSET_TARGET_PMU 0x1C0
+#define IPI_BUF_OFFSET_REQ 0x00
+#define IPI_BUF_OFFSET_RESP 0x20
+
+#define PMUFW_PAYLOAD_ARG_CNT 8
+
+/* PMUFW commands */
+#define PMUFW_CMD_SET_CONFIGURATION 2
+
+static void pmu_ipc_send_request(const u32 *req, size_t req_len)
+{
+ u32 *mbx = (u32 *)(IPI_BUF_BASE_APU +
+ IPI_BUF_OFFSET_TARGET_PMU +
+ IPI_BUF_OFFSET_REQ);
+ size_t i;
+
+ for (i = 0; i < req_len; i++)
+ writel(req[i], &mbx[i]);
+}
+
+static void pmu_ipc_read_response(unsigned int *value, size_t count)
+{
+ u32 *mbx = (u32 *)(IPI_BUF_BASE_APU +
+ IPI_BUF_OFFSET_TARGET_PMU +
+ IPI_BUF_OFFSET_RESP);
+ size_t i;
+
+ for (i = 0; i < count; i++)
+ value[i] = readl(&mbx[i]);
+}
+
+/**
+ * Send request to PMU and get the response.
+ *
+ * @req: Request buffer. Byte 0 is the API ID, other bytes are optional
+ * parameters.
+ * @req_len: Request length in number of 32-bit words.
+ * @res: Response buffer. Byte 0 is the error code, other bytes are
+ * optional parameters. Optional, if @res_maxlen==0 the parameters
+ * will not be read.
+ * @res_maxlen: Space allocated for the response in number of 32-bit words.
+ *
+ * @return Error code returned by the PMU (i.e. the first word of the response)
+ */
+static int pmu_ipc_request(const u32 *req, size_t req_len,
+ u32 *res, size_t res_maxlen)
+{
+ u32 status;
+
+ if (req_len > PMUFW_PAYLOAD_ARG_CNT ||
+ res_maxlen > PMUFW_PAYLOAD_ARG_CNT)
+ return -EINVAL;
+
+ pmu_ipc_send_request(req, req_len);
+
+ /* Raise Inter-Processor Interrupt to PMU and wait for response */
+ writel(IPI_BIT_MASK_PMU0, IPI_REG_BASE_APU + IPI_REG_OFFSET_TRIG);
+ do {
+ status = readl(IPI_REG_BASE_APU + IPI_REG_OFFSET_OBR);
+ } while (status & IPI_BIT_MASK_PMU0);
+
+ pmu_ipc_read_response(res, res_maxlen);
+
+ return 0;
+}
+
+/**
+ * Send a configuration object to the PMU firmware.
+ *
+ * @cfg_obj: Pointer to the configuration object
+ * @size: Size of @cfg_obj in bytes
+ */
+void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size)
+{
+ const u32 request[] = {
+ PMUFW_CMD_SET_CONFIGURATION,
+ (u32)((u64)cfg_obj)
+ };
+ u32 response;
+ int err;
+
+ printf("Loading PMUFW cfg obj (%ld bytes)\n", size);
+
+ err = pmu_ipc_request(request, ARRAY_SIZE(request), &response, 1);
+ if (err)
+ panic("Cannot load PMUFW configuration object (%d)\n", err);
+ if (response != 0)
+ panic("PMUFW returned 0x%08x status!\n", response);
+}
diff --git a/arch/m68k/cpu/mcf5445x/cpu_init.c b/arch/m68k/cpu/mcf5445x/cpu_init.c
index 8f4991c..134510b 100644
--- a/arch/m68k/cpu/mcf5445x/cpu_init.c
+++ b/arch/m68k/cpu/mcf5445x/cpu_init.c
@@ -200,7 +200,7 @@
/* Lowest slew rate for UART0,1,2 */
out_8(&gpio->srcr_uart, 0x00);
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
/* eSDHC pin as faster speed */
out_8(&gpio->srcr_sdhc, 0x03);
diff --git a/arch/m68k/lib/bootm.c b/arch/m68k/lib/bootm.c
index 1b15430..19445b3 100644
--- a/arch/m68k/lib/bootm.c
+++ b/arch/m68k/lib/bootm.c
@@ -6,11 +6,11 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <image.h>
#include <u-boot/zlib.h>
#include <bzlib.h>
#include <watchdog.h>
-#include <environment.h>
#include <asm/byteorder.h>
#ifdef CONFIG_SHOW_BOOT_PROGRESS
# include <status_led.h>
diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c
index 083a43c..ec33294 100644
--- a/arch/microblaze/lib/bootm.c
+++ b/arch/microblaze/lib/bootm.c
@@ -9,6 +9,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <fdt_support.h>
#include <image.h>
#include <u-boot/zlib.h>
diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
index 6a462f3..8c0d767 100644
--- a/arch/mips/lib/bootm.c
+++ b/arch/mips/lib/bootm.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
+#include <env.h>
#include <image.h>
#include <fdt_support.h>
#include <asm/addrspace.h>
diff --git a/arch/nds32/include/asm/u-boot.h b/arch/nds32/include/asm/u-boot.h
index 68701d6..8c949e7 100644
--- a/arch/nds32/include/asm/u-boot.h
+++ b/arch/nds32/include/asm/u-boot.h
@@ -21,7 +21,6 @@
#include <asm/u-boot-nds32.h>
-#include <environment.h>
typedef struct bd_info {
unsigned long bi_arch_number; /* unique id for this board */
diff --git a/arch/nds32/lib/bootm.c b/arch/nds32/lib/bootm.c
index 0cfdc52..a472f6a 100644
--- a/arch/nds32/lib/bootm.c
+++ b/arch/nds32/lib/bootm.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <image.h>
#include <u-boot/zlib.h>
#include <asm/byteorder.h>
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index b99288a..72053ce 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -100,65 +100,39 @@
config TARGET_KMETER1
bool "Support kmeter1"
- select ARCH_MPC8360
- imply CMD_CRAMFS
- imply CMD_DIAG
- imply FS_CRAMFS
+ select VENDOR_KM
config TARGET_KMCOGE5NE
bool "Support kmcoge5ne"
- select ARCH_MPC8360
- imply CMD_CRAMFS
- imply CMD_DIAG
- imply FS_CRAMFS
+ select VENDOR_KM
config TARGET_SUVD3
bool "Support suvd3"
- select ARCH_MPC832X
- imply CMD_CRAMFS
- imply FS_CRAMFS
-
-config TARGET_KMVECT1
- bool "Support kmvect1"
- select ARCH_MPC8309
- imply CMD_CRAMFS
- imply FS_CRAMFS
+ select VENDOR_KM
config TARGET_KMTEGR1
bool "Support kmtegr1"
- select ARCH_MPC8309
- imply CMD_CRAMFS
- imply FS_CRAMFS
+ select VENDOR_KM
config TARGET_TUXX1
bool "Support tuxx1"
- select ARCH_MPC832X
- imply CMD_CRAMFS
- imply FS_CRAMFS
+ select VENDOR_KM
config TARGET_KMSUPX5
bool "Support kmsupx5"
- select ARCH_MPC832X
- imply CMD_CRAMFS
- imply FS_CRAMFS
+ select VENDOR_KM
config TARGET_TUGE1
bool "Support tuge1"
- select ARCH_MPC832X
- imply CMD_CRAMFS
- imply FS_CRAMFS
+ select VENDOR_KM
config TARGET_KMOPTI2
bool "Support kmopti2"
- select ARCH_MPC832X
- imply CMD_CRAMFS
- imply FS_CRAMFS
+ select VENDOR_KM
config TARGET_KMTEPR2
bool "Support kmtepr2"
- select ARCH_MPC832X
- imply CMD_CRAMFS
- imply FS_CRAMFS
+ select VENDOR_KM
config TARGET_TQM834X
bool "Support TQM834x"
@@ -354,7 +328,7 @@
source "board/freescale/mpc837xemds/Kconfig"
source "board/freescale/mpc837xerdb/Kconfig"
source "board/ids/ids8313/Kconfig"
-source "board/keymile/km83xx/Kconfig"
+source "board/keymile/Kconfig"
source "board/mpc8308_p1m/Kconfig"
source "board/sbc8349/Kconfig"
source "board/tqc/tqm834x/Kconfig"
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 7572404..c038a6d 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -412,11 +412,7 @@
config TARGET_KMP204X
bool "Support kmp204x"
- select ARCH_P2041
- select PHYS_64BIT
- select FSL_DDR_INTERACTIVE
- imply CMD_CRAMFS
- imply FS_CRAMFS
+ select VENDOR_KM
config TARGET_XPEDITE520X
bool "Support xpedite520x"
@@ -1620,7 +1616,7 @@
source "board/freescale/t4qds/Kconfig"
source "board/freescale/t4rdb/Kconfig"
source "board/gdsys/p1022/Kconfig"
-source "board/keymile/kmp204x/Kconfig"
+source "board/keymile/Kconfig"
source "board/sbc8548/Kconfig"
source "board/socrates/Kconfig"
source "board/varisys/cyrus/Kconfig"
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index cbcd62e..cac9280 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -10,6 +10,7 @@
*/
#include <common.h>
+#include <env.h>
#include <watchdog.h>
#include <asm/processor.h>
#include <ioports.h>
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 20ecca6..db12aef 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -7,7 +7,7 @@
*/
#include <common.h>
-#include <environment.h>
+#include <env.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <asm/processor.h>
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 2fab9aa..fcfa730 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -4,6 +4,7 @@
*/
#include <common.h>
+#include <env.h>
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
#include <hwconfig.h>
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c
index b0aa72e..3882c95 100644
--- a/arch/powerpc/cpu/mpc85xx/mp.c
+++ b/arch/powerpc/cpu/mpc85xx/mp.c
@@ -4,7 +4,9 @@
*/
#include <common.h>
+#include <env.h>
#include <asm/processor.h>
+#include <env.h>
#include <ioports.h>
#include <lmb.h>
#include <asm/io.h>
diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile
index 6a28f80..021c85f 100644
--- a/arch/powerpc/dts/Makefile
+++ b/arch/powerpc/dts/Makefile
@@ -1,6 +1,18 @@
# SPDX-License-Identifier: GPL-2.0+
+dtb-$(CONFIG_TARGET_MPC8548CDS) += mpc8548cds.dtb mpc8548cds_36b.dtb
+dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb
+dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb
+dtb-$(CONFIG_TARGET_P2020RDB) += p2020rdb-pc.dtb p2020rdb-pc_36b.dtb
+dtb-$(CONFIG_TARGET_P2041RDB) += p2041rdb.dtb
+dtb-$(CONFIG_TARGET_P3041DS) += p3041ds.dtb
+dtb-$(CONFIG_TARGET_P4080DS) += p4080ds.dtb
+dtb-$(CONFIG_TARGET_P5040DS) += p5040ds.dtb
+dtb-$(CONFIG_TARGET_T1024RDB) += t1024rdb.dtb
+dtb-$(CONFIG_TARGET_T1042D4RDB) += t1042d4rdb.dtb
dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb
+dtb-$(CONFIG_TARGET_T2080RDB) += t2080rdb.dtb
+dtb-$(CONFIG_TARGET_T4240RDB) += t4240rdb.dtb
dtb-$(CONFIG_TARGET_MCR3000) += mcr3000.dtb
dtb-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.dtb
diff --git a/arch/powerpc/dts/e500mc_power_isa.dtsi b/arch/powerpc/dts/e500mc_power_isa.dtsi
new file mode 100644
index 0000000..e486ae5
--- /dev/null
+++ b/arch/powerpc/dts/e500mc_power_isa.dtsi
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * e500mc Power ISA Device Tree Source (include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/ {
+ cpus {
+ power-isa-version = "2.06";
+ power-isa-b; // Base
+ power-isa-e; // Embedded
+ power-isa-atb; // Alternate Time Base
+ power-isa-cs; // Cache Specification
+ power-isa-ds; // Decorated Storage
+ power-isa-e.ed; // Embedded.Enhanced Debug
+ power-isa-e.pd; // Embedded.External PID
+ power-isa-e.hv; // Embedded.Hypervisor
+ power-isa-e.le; // Embedded.Little-Endian
+ power-isa-e.pm; // Embedded.Performance Monitor
+ power-isa-e.pc; // Embedded.Processor Control
+ power-isa-ecl; // Embedded Cache Locking
+ power-isa-exp; // External Proxy
+ power-isa-fp; // Floating Point
+ power-isa-fp.r; // Floating Point.Record
+ power-isa-mmc; // Memory Coherence
+ power-isa-scpm; // Store Conditional Page Mobility
+ power-isa-wt; // Wait
+ fsl,eref-deo; // Data Cache Extended Operations
+ mmu-type = "power-embedded";
+ };
+};
diff --git a/arch/powerpc/dts/e500v2_power_isa.dtsi b/arch/powerpc/dts/e500v2_power_isa.dtsi
new file mode 100644
index 0000000..010e8e5
--- /dev/null
+++ b/arch/powerpc/dts/e500v2_power_isa.dtsi
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * e500v2 Power ISA Device Tree Source (include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/ {
+ cpus {
+ power-isa-version = "2.03";
+ power-isa-b; // Base
+ power-isa-e; // Embedded
+ power-isa-atb; // Alternate Time Base
+ power-isa-cs; // Cache Specification
+ power-isa-e.le; // Embedded.Little-Endian
+ power-isa-e.pm; // Embedded.Performance Monitor
+ power-isa-ecl; // Embedded Cache Locking
+ power-isa-mmc; // Memory Coherence
+ power-isa-sp; // Signal Processing Engine
+ power-isa-sp.fd; // SPE.Embedded Float Scalar Double
+ power-isa-sp.fs; // SPE.Embedded Float Scalar Single
+ power-isa-sp.fv; // SPE.Embedded Float Vector
+ mmu-type = "power-embedded";
+ };
+};
diff --git a/arch/powerpc/dts/e5500_power_isa.dtsi b/arch/powerpc/dts/e5500_power_isa.dtsi
new file mode 100644
index 0000000..0a0943b0
--- /dev/null
+++ b/arch/powerpc/dts/e5500_power_isa.dtsi
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * e5500 Power ISA Device Tree Source (include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/ {
+ cpus {
+ power-isa-version = "2.06";
+ power-isa-b; // Base
+ power-isa-e; // Embedded
+ power-isa-atb; // Alternate Time Base
+ power-isa-cs; // Cache Specification
+ power-isa-ds; // Decorated Storage
+ power-isa-e.ed; // Embedded.Enhanced Debug
+ power-isa-e.pd; // Embedded.External PID
+ power-isa-e.hv; // Embedded.Hypervisor
+ power-isa-e.le; // Embedded.Little-Endian
+ power-isa-e.pm; // Embedded.Performance Monitor
+ power-isa-e.pc; // Embedded.Processor Control
+ power-isa-ecl; // Embedded Cache Locking
+ power-isa-exp; // External Proxy
+ power-isa-fp; // Floating Point
+ power-isa-fp.r; // Floating Point.Record
+ power-isa-mmc; // Memory Coherence
+ power-isa-scpm; // Store Conditional Page Mobility
+ power-isa-wt; // Wait
+ power-isa-64; // 64-bit
+ fsl,eref-deo; // Data Cache Extended Operations
+ mmu-type = "power-embedded";
+ };
+};
diff --git a/arch/powerpc/dts/mpc8548-post.dtsi b/arch/powerpc/dts/mpc8548-post.dtsi
new file mode 100644
index 0000000..2206f2d
--- /dev/null
+++ b/arch/powerpc/dts/mpc8548-post.dtsi
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * MPC8548 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+&soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "fsl,mpc8548-immr", "simple-bus";
+ bus-frequency = <0x0>;
+
+ mpic: pic@40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <4>;
+ reg = <0x40000 0x40000>;
+ compatible = "fsl,mpic";
+ device_type = "open-pic";
+ big-endian;
+ single-cpu-affinity;
+ last-interrupt-source = <255>;
+ };
+};
+
+&pcie {
+ compatible = "fsl,pcie-mpc8548", "fsl,pcie-fsl-qoriq";
+ law_trgt_if = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+};
diff --git a/arch/powerpc/dts/mpc8548.dtsi b/arch/powerpc/dts/mpc8548.dtsi
new file mode 100644
index 0000000..b24567d
--- /dev/null
+++ b/arch/powerpc/dts/mpc8548.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * MPC8548CDS Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e500v2_power_isa.dtsi"
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,8548@0 {
+ device_type = "cpu";
+ reg = <0>;
+ };
+ };
+};
diff --git a/arch/powerpc/dts/mpc8548cds.dts b/arch/powerpc/dts/mpc8548cds.dts
new file mode 100644
index 0000000..3b927bd
--- /dev/null
+++ b/arch/powerpc/dts/mpc8548cds.dts
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * MPC8548CDS Device Tree Source
+ *
+ * Copyright 2006 - 2012 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "mpc8548.dtsi"
+
+/ {
+ model = "fsl,MPC8548CDS";
+ compatible = "fsl,MPC8548CDS";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ soc: soc8548@e0000000 {
+ ranges = <0x0 0x0 0xe0000000 0x100000>;
+ };
+
+ pcie: pcie@e000a000 {
+ reg = <0x0 0xe000a000 0x0 0x1000>; /* registers */
+ ranges = <0x01000000 0x0 0x00000000 0x0 0xe3000000 0x0 0x00100000 /* downstream I/O */
+ 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+};
+
+/include/ "mpc8548-post.dtsi"
diff --git a/arch/powerpc/dts/mpc8548cds_36b.dts b/arch/powerpc/dts/mpc8548cds_36b.dts
new file mode 100644
index 0000000..98d7c24
--- /dev/null
+++ b/arch/powerpc/dts/mpc8548cds_36b.dts
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * MPC8548CDS (36-bit address map) Device Tree Source
+ *
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "mpc8548.dtsi"
+
+/ {
+ model = "fsl,MPC8548CDS";
+ compatible = "fsl,MPC8548CDS";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ soc: soc8548@fe0000000 {
+ ranges = <0x0 0xf 0xe0000000 0x100000>;
+ };
+
+ pcie: pcie@fe000a000 {
+ reg = <0xf 0xe000a000 0x0 0x1000>; /* registers */
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xe3000000 0x0 0x00100000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+};
+
+/include/ "mpc8548-post.dtsi"
diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi
new file mode 100644
index 0000000..1e5e678
--- /dev/null
+++ b/arch/powerpc/dts/p1020-post.dtsi
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1020 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+&soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "fsl,p1020-immr", "simple-bus";
+ bus-frequency = <0x0>;
+
+ mpic: pic@40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <4>;
+ reg = <0x40000 0x40000>;
+ compatible = "fsl,mpic";
+ device_type = "open-pic";
+ big-endian;
+ single-cpu-affinity;
+ last-interrupt-source = <255>;
+ };
+};
+
+/* PCIe controller base address 0x9000 */
+&pci1 {
+ compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+ law_trgt_if = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+};
+
+/* PCIe controller base address 0xa000 */
+&pci0 {
+ compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+ law_trgt_if = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+};
diff --git a/arch/powerpc/dts/p1020.dtsi b/arch/powerpc/dts/p1020.dtsi
new file mode 100644
index 0000000..ee2b6f4
--- /dev/null
+++ b/arch/powerpc/dts/p1020.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1020 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e500v2_power_isa.dtsi"
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: PowerPC,P1020@0 {
+ device_type = "cpu";
+ reg = <0>;
+ };
+ cpu1: PowerPC,P1020@1 {
+ device_type = "cpu";
+ reg = <1>;
+ };
+ };
+};
diff --git a/arch/powerpc/dts/p1020rdb-pc.dts b/arch/powerpc/dts/p1020rdb-pc.dts
new file mode 100644
index 0000000..7ebaa61
--- /dev/null
+++ b/arch/powerpc/dts/p1020rdb-pc.dts
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1020RDB-PC Device Tree Source
+ *
+ * Copyright 2013 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "p1020.dtsi"
+
+/ {
+ model = "fsl,P1020RDB-PC";
+ compatible = "fsl,P1020RDB-PC";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ soc: soc@ffe00000 {
+ ranges = <0x0 0x0 0xffe00000 0x100000>;
+ };
+
+ pci1: pcie@ffe09000 {
+ reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */
+ ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+
+ pci0: pcie@ffe0a000 {
+ reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */
+ ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+};
+
+/include/ "p1020-post.dtsi"
diff --git a/arch/powerpc/dts/p1020rdb-pc_36b.dts b/arch/powerpc/dts/p1020rdb-pc_36b.dts
new file mode 100644
index 0000000..c0e5ef4
--- /dev/null
+++ b/arch/powerpc/dts/p1020rdb-pc_36b.dts
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1020RDB-PC (36-bit address map) Device Tree Source
+ *
+ * Copyright 2013 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "p1020.dtsi"
+
+/ {
+ model = "fsl,P1020RDB-PC";
+ compatible = "fsl,P1020RDB-PC";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ soc: soc@fffe00000 {
+ ranges = <0x0 0xf 0xffe00000 0x100000>;
+ };
+
+ pci1: pcie@fffe09000 {
+ reg = <0xf 0xffe09000 0x0 0x1000>; /* registers */
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+
+ pci0: pcie@fffe0a000 {
+ reg = <0xf 0xffe0a000 0x0 0x1000>; /* registers */
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+};
+
+/include/ "p1020-post.dtsi"
diff --git a/arch/powerpc/dts/p1020rdb-pd.dts b/arch/powerpc/dts/p1020rdb-pd.dts
new file mode 100644
index 0000000..21174a0
--- /dev/null
+++ b/arch/powerpc/dts/p1020rdb-pd.dts
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1020RDB-PD Device Tree Source
+ *
+ * Copyright 2013 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "p1020.dtsi"
+
+/ {
+ model = "fsl,P1020RDB-PD";
+ compatible = "fsl,P1020RDB-PD";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ soc: soc@ffe00000 {
+ ranges = <0x0 0x0 0xffe00000 0x100000>;
+ };
+
+ pci1: pcie@ffe09000 {
+ reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */
+ ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+
+ pci0: pcie@ffe0a000 {
+ reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */
+ ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+};
+
+/include/ "p1020-post.dtsi"
diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi
new file mode 100644
index 0000000..f696f35
--- /dev/null
+++ b/arch/powerpc/dts/p2020-post.dtsi
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P2020 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+&soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "fsl,p2020-immr", "simple-bus";
+ bus-frequency = <0x0>;
+
+ mpic: pic@40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <4>;
+ reg = <0x40000 0x40000>;
+ compatible = "fsl,mpic";
+ device_type = "open-pic";
+ big-endian;
+ single-cpu-affinity;
+ last-interrupt-source = <255>;
+ };
+};
+
+/* PCIe controller base address 0x8000 */
+&pci2 {
+ compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+ law_trgt_if = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+};
+
+/* PCIe controller base address 0x9000 */
+&pci1 {
+ compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+ law_trgt_if = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+};
+
+/* PCIe controller base address 0xa000 */
+&pci0 {
+ compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+ law_trgt_if = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+};
diff --git a/arch/powerpc/dts/p2020.dtsi b/arch/powerpc/dts/p2020.dtsi
new file mode 100644
index 0000000..7c4c206
--- /dev/null
+++ b/arch/powerpc/dts/p2020.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P2020 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e500v2_power_isa.dtsi"
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: PowerPC,P2020@0 {
+ device_type = "cpu";
+ reg = <0>;
+ };
+ cpu1: PowerPC,P2020@1 {
+ device_type = "cpu";
+ reg = <1>;
+ };
+ };
+};
diff --git a/arch/powerpc/dts/p2020rdb-pc.dts b/arch/powerpc/dts/p2020rdb-pc.dts
new file mode 100644
index 0000000..08befd4
--- /dev/null
+++ b/arch/powerpc/dts/p2020rdb-pc.dts
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P2020RDB-PC Device Tree Source
+ *
+ * Copyright 2013 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "p2020.dtsi"
+
+/ {
+ model = "fsl,P2020RDB-PC";
+ compatible = "fsl,P2020RDB-PC";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ soc: soc@ffe00000 {
+ ranges = <0x0 0x0 0xffe00000 0x100000>;
+ };
+
+ pci2: pcie@ffe08000 {
+ reg = <0x0 0xffe08000 0x0 0x1000>; /* registers */
+ status = "disabled";
+ };
+
+ pci1: pcie@ffe09000 {
+ reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */
+ ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+
+ pci0: pcie@ffe0a000 {
+ reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */
+ ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+};
+
+/include/ "p2020-post.dtsi"
diff --git a/arch/powerpc/dts/p2020rdb-pc_36b.dts b/arch/powerpc/dts/p2020rdb-pc_36b.dts
new file mode 100644
index 0000000..04b2519
--- /dev/null
+++ b/arch/powerpc/dts/p2020rdb-pc_36b.dts
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P2020RDB-PC (36-bit address map) Device Tree Source
+ *
+ * Copyright 2013 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "p2020.dtsi"
+
+/ {
+ model = "fsl,P2020RDB-PC";
+ compatible = "fsl,P2020RDB-PC";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ soc: soc@fffe00000 {
+ ranges = <0x0 0xf 0xffe00000 0x100000>;
+ };
+
+ pci2: pcie@fffe08000 {
+ reg = <0xf 0xffe08000 0x0 0x1000>; /* registers */
+ status = "disabled";
+ };
+
+ pci1: pcie@fffe09000 {
+ reg = <0xf 0xffe09000 0x0 0x1000>; /* registers */
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+
+ pci0: pcie@fffe0a000 {
+ reg = <0xf 0xffe0a000 0x0 0x1000>; /* registers */
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+};
+
+/include/ "p2020-post.dtsi"
diff --git a/arch/powerpc/dts/p2041.dtsi b/arch/powerpc/dts/p2041.dtsi
new file mode 100644
index 0000000..55f7adc
--- /dev/null
+++ b/arch/powerpc/dts/p2041.dtsi
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P2041 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2011 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e500mc_power_isa.dtsi"
+
+/ {
+ compatible = "fsl,P2041";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: PowerPC,e500mc@0 {
+ device_type = "cpu";
+ reg = <0>;
+ fsl,portid-mapping = <0x80000000>;
+ };
+ cpu1: PowerPC,e500mc@1 {
+ device_type = "cpu";
+ reg = <1>;
+ fsl,portid-mapping = <0x40000000>;
+ };
+ cpu2: PowerPC,e500mc@2 {
+ device_type = "cpu";
+ reg = <2>;
+ fsl,portid-mapping = <0x20000000>;
+ };
+ cpu3: PowerPC,e500mc@3 {
+ device_type = "cpu";
+ reg = <3>;
+ fsl,portid-mapping = <0x10000000>;
+ };
+ };
+
+ soc: soc@ffe000000 {
+ ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+ reg = <0xf 0xfe000000 0 0x00001000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "simple-bus";
+
+ mpic: pic@40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <4>;
+ reg = <0x40000 0x40000>;
+ compatible = "fsl,mpic", "chrp,open-pic";
+ device_type = "open-pic";
+ clock-frequency = <0x0>;
+ };
+ };
+
+ pcie@ffe200000 {
+ compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */
+ law_trgt_if = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe201000 {
+ compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */
+ law_trgt_if = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe202000 {
+ compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */
+ law_trgt_if = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+};
diff --git a/arch/powerpc/dts/p2041rdb.dts b/arch/powerpc/dts/p2041rdb.dts
new file mode 100644
index 0000000..6e9d9c0
--- /dev/null
+++ b/arch/powerpc/dts/p2041rdb.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P2041RDB Device Tree Source
+ *
+ * Copyright 2011 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "p2041.dtsi"
+
+/ {
+ model = "fsl,P2041RDB";
+ compatible = "fsl,P2041RDB";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+};
diff --git a/arch/powerpc/dts/p3041.dtsi b/arch/powerpc/dts/p3041.dtsi
new file mode 100644
index 0000000..197896d
--- /dev/null
+++ b/arch/powerpc/dts/p3041.dtsi
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P3041 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2010 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e500mc_power_isa.dtsi"
+
+/ {
+ compatible = "fsl,P3041";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: PowerPC,e500mc@0 {
+ device_type = "cpu";
+ reg = <0>;
+ fsl,portid-mapping = <0x80000000>;
+ };
+ cpu1: PowerPC,e500mc@1 {
+ device_type = "cpu";
+ reg = <1>;
+ fsl,portid-mapping = <0x40000000>;
+ };
+ cpu2: PowerPC,e500mc@2 {
+ device_type = "cpu";
+ reg = <2>;
+ fsl,portid-mapping = <0x20000000>;
+ };
+ cpu3: PowerPC,e500mc@3 {
+ device_type = "cpu";
+ reg = <3>;
+ fsl,portid-mapping = <0x10000000>;
+ };
+ };
+
+ soc: soc@ffe000000 {
+ ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+ reg = <0xf 0xfe000000 0 0x00001000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "simple-bus";
+
+ mpic: pic@40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <4>;
+ reg = <0x40000 0x40000>;
+ compatible = "fsl,mpic", "chrp,open-pic";
+ device_type = "open-pic";
+ clock-frequency = <0x0>;
+ };
+ };
+
+ pcie@ffe200000 {
+ compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */
+ law_trgt_if = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe201000 {
+ compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */
+ law_trgt_if = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe202000 {
+ compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */
+ law_trgt_if = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe203000 {
+ compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe203000 0x0 0x1000>; /* registers */
+ law_trgt_if = <3>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x60000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+};
diff --git a/arch/powerpc/dts/p3041ds.dts b/arch/powerpc/dts/p3041ds.dts
new file mode 100644
index 0000000..c30bf7a
--- /dev/null
+++ b/arch/powerpc/dts/p3041ds.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P3041DS Device Tree Source
+ *
+ * Copyright 2010 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "p3041.dtsi"
+
+/ {
+ model = "fsl,P3041DS";
+ compatible = "fsl,P3041DS";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+};
diff --git a/arch/powerpc/dts/p4080.dtsi b/arch/powerpc/dts/p4080.dtsi
new file mode 100644
index 0000000..ab76680
--- /dev/null
+++ b/arch/powerpc/dts/p4080.dtsi
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P4080/P4040 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2011 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e500mc_power_isa.dtsi"
+
+/ {
+ compatible = "fsl,P4080";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: PowerPC,e500mc@0 {
+ device_type = "cpu";
+ reg = <0>;
+ fsl,portid-mapping = <0x80000000>;
+ };
+ cpu1: PowerPC,e500mc@1 {
+ device_type = "cpu";
+ reg = <1>;
+ fsl,portid-mapping = <0x40000000>;
+ };
+ cpu2: PowerPC,e500mc@2 {
+ device_type = "cpu";
+ reg = <2>;
+ fsl,portid-mapping = <0x20000000>;
+ };
+ cpu3: PowerPC,e500mc@3 {
+ device_type = "cpu";
+ reg = <3>;
+ fsl,portid-mapping = <0x10000000>;
+ };
+ cpu4: PowerPC,e500mc@4 {
+ device_type = "cpu";
+ reg = <4>;
+ fsl,portid-mapping = <0x08000000>;
+ };
+ cpu5: PowerPC,e500mc@5 {
+ device_type = "cpu";
+ reg = <5>;
+ fsl,portid-mapping = <0x04000000>;
+ };
+ cpu6: PowerPC,e500mc@6 {
+ device_type = "cpu";
+ reg = <6>;
+ fsl,portid-mapping = <0x02000000>;
+ };
+ cpu7: PowerPC,e500mc@7 {
+ device_type = "cpu";
+ reg = <7>;
+ fsl,portid-mapping = <0x01000000>;
+ };
+ };
+
+ soc: soc@ffe000000 {
+ ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+ reg = <0xf 0xfe000000 0 0x00001000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "simple-bus";
+
+ mpic: pic@40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <4>;
+ reg = <0x40000 0x40000>;
+ compatible = "fsl,mpic", "chrp,open-pic";
+ device_type = "open-pic";
+ clock-frequency = <0x0>;
+ };
+ };
+
+ pcie@ffe200000 {
+ compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */
+ law_trgt_if = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe201000 {
+ compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */
+ law_trgt_if = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe202000 {
+ compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */
+ law_trgt_if = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+};
diff --git a/arch/powerpc/dts/p4080ds.dts b/arch/powerpc/dts/p4080ds.dts
new file mode 100644
index 0000000..15a0f66
--- /dev/null
+++ b/arch/powerpc/dts/p4080ds.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P4080DS Device Tree Source
+ *
+ * Copyright 2011 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "p4080.dtsi"
+
+/ {
+ model = "fsl,P4080DS";
+ compatible = "fsl,P4080DS";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+};
diff --git a/arch/powerpc/dts/p5040.dtsi b/arch/powerpc/dts/p5040.dtsi
new file mode 100644
index 0000000..8ab123d
--- /dev/null
+++ b/arch/powerpc/dts/p5040.dtsi
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P5040 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e5500_power_isa.dtsi"
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: PowerPC,e5500@0 {
+ device_type = "cpu";
+ reg = <0>;
+ fsl,portid-mapping = <0x80000000>;
+ };
+ cpu1: PowerPC,e5500@1 {
+ device_type = "cpu";
+ reg = <1>;
+ fsl,portid-mapping = <0x40000000>;
+ };
+ cpu2: PowerPC,e5500@2 {
+ device_type = "cpu";
+ reg = <2>;
+ fsl,portid-mapping = <0x20000000>;
+ };
+ cpu3: PowerPC,e5500@3 {
+ device_type = "cpu";
+ reg = <3>;
+ fsl,portid-mapping = <0x10000000>;
+ };
+ };
+
+ soc: soc@ffe000000 {
+ ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+ reg = <0xf 0xfe000000 0 0x00001000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "simple-bus";
+
+ mpic: pic@40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <4>;
+ reg = <0x40000 0x40000>;
+ compatible = "fsl,mpic", "chrp,open-pic";
+ device_type = "open-pic";
+ clock-frequency = <0x0>;
+ };
+ };
+
+ pcie@ffe200000 {
+ compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */
+ law_trgt_if = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe201000 {
+ compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */
+ law_trgt_if = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe202000 {
+ compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */
+ law_trgt_if = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+};
diff --git a/arch/powerpc/dts/p5040ds.dts b/arch/powerpc/dts/p5040ds.dts
new file mode 100644
index 0000000..723d31d
--- /dev/null
+++ b/arch/powerpc/dts/p5040ds.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P5040DS Device Tree Source
+ *
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "p5040.dtsi"
+
+/ {
+ model = "fsl,P5040DS";
+ compatible = "fsl,P5040DS";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+};
diff --git a/arch/powerpc/dts/t1024rdb.dts b/arch/powerpc/dts/t1024rdb.dts
new file mode 100644
index 0000000..19a6652
--- /dev/null
+++ b/arch/powerpc/dts/t1024rdb.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * T1024RDB Device Tree Source
+ *
+ * Copyright 2013 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "t102x.dtsi"
+
+/ {
+ model = "fsl,T1024RDB";
+ compatible = "fsl,T1024RDB";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+};
diff --git a/arch/powerpc/dts/t102x.dtsi b/arch/powerpc/dts/t102x.dtsi
new file mode 100644
index 0000000..c49fd21
--- /dev/null
+++ b/arch/powerpc/dts/t102x.dtsi
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * T102X Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e5500_power_isa.dtsi"
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: PowerPC,e5500@0 {
+ device_type = "cpu";
+ reg = <0>;
+ #cooling-cells = <2>;
+ };
+ cpu1: PowerPC,e5500@1 {
+ device_type = "cpu";
+ reg = <1>;
+ #cooling-cells = <2>;
+ };
+ };
+
+ soc: soc@ffe000000 {
+ ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+ reg = <0xf 0xfe000000 0 0x00001000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "simple-bus";
+
+ mpic: pic@40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <4>;
+ reg = <0x40000 0x40000>;
+ compatible = "fsl,mpic", "chrp,open-pic";
+ device_type = "open-pic";
+ clock-frequency = <0x0>;
+ };
+ };
+
+ pcie@ffe240000 {
+ compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe240000 0x0 0x1000>; /* registers */
+ law_trgt_if = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe250000 {
+ compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe250000 0x0 0x1000>; /* registers */
+ law_trgt_if = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe260000 {
+ compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe260000 0x0 0x1000>; /* registers */
+ law_trgt_if = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */
+ };
+};
diff --git a/arch/powerpc/dts/t1042d4rdb.dts b/arch/powerpc/dts/t1042d4rdb.dts
new file mode 100644
index 0000000..16a8ed4
--- /dev/null
+++ b/arch/powerpc/dts/t1042d4rdb.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * T1042D4RDB Device Tree Source
+ *
+ * Copyright 2013 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "t104x.dtsi"
+
+/ {
+ model = "fsl,T1042D4RDB";
+ compatible = "fsl,T1042D4RDB";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+};
diff --git a/arch/powerpc/dts/t104x.dtsi b/arch/powerpc/dts/t104x.dtsi
new file mode 100644
index 0000000..5998967
--- /dev/null
+++ b/arch/powerpc/dts/t104x.dtsi
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * T104X Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e5500_power_isa.dtsi"
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: PowerPC,e5500@0 {
+ device_type = "cpu";
+ reg = <0>;
+ #cooling-cells = <2>;
+ };
+ cpu1: PowerPC,e5500@1 {
+ device_type = "cpu";
+ reg = <1>;
+ #cooling-cells = <2>;
+ };
+ cpu2: PowerPC,e5500@2 {
+ device_type = "cpu";
+ reg = <2>;
+ #cooling-cells = <2>;
+ };
+ cpu3: PowerPC,e5500@3 {
+ device_type = "cpu";
+ reg = <3>;
+ #cooling-cells = <2>;
+ };
+ };
+
+ soc: soc@ffe000000 {
+ ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+ reg = <0xf 0xfe000000 0 0x00001000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "simple-bus";
+
+ mpic: pic@40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <4>;
+ reg = <0x40000 0x40000>;
+ compatible = "fsl,mpic", "chrp,open-pic";
+ device_type = "open-pic";
+ clock-frequency = <0x0>;
+ };
+ };
+
+ pcie@ffe240000 {
+ compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe240000 0x0 0x1000>; /* registers */
+ law_trgt_if = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe250000 {
+ compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe250000 0x0 0x1000>; /* registers */
+ law_trgt_if = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe260000 {
+ compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe260000 0x0 0x1000>; /* registers */
+ law_trgt_if = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe270000 {
+ compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe270000 0x0 0x1000>; /* registers */
+ law_trgt_if = <3>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x30000000 0x0 0x10000000>; /* non-prefetchable memory */
+ };
+};
diff --git a/arch/powerpc/dts/t2080rdb.dts b/arch/powerpc/dts/t2080rdb.dts
new file mode 100644
index 0000000..49c1765
--- /dev/null
+++ b/arch/powerpc/dts/t2080rdb.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * T2080RDB Device Tree Source
+ *
+ * Copyright 2013 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "t2080.dtsi"
+
+/ {
+ model = "fsl,T2080RDB";
+ compatible = "fsl,T2080RDB";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+};
diff --git a/arch/powerpc/dts/t4240.dtsi b/arch/powerpc/dts/t4240.dtsi
new file mode 100644
index 0000000..fc34974
--- /dev/null
+++ b/arch/powerpc/dts/t4240.dtsi
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * T4240 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e6500_power_isa.dtsi"
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: PowerPC,e6500@0 {
+ device_type = "cpu";
+ reg = <0 1>;
+ fsl,portid-mapping = <0x80000000>;
+ };
+ cpu1: PowerPC,e6500@2 {
+ device_type = "cpu";
+ reg = <2 3>;
+ fsl,portid-mapping = <0x80000000>;
+ };
+ cpu2: PowerPC,e6500@4 {
+ device_type = "cpu";
+ reg = <4 5>;
+ fsl,portid-mapping = <0x80000000>;
+ };
+ cpu3: PowerPC,e6500@6 {
+ device_type = "cpu";
+ reg = <6 7>;
+ fsl,portid-mapping = <0x80000000>;
+ };
+ cpu4: PowerPC,e6500@8 {
+ device_type = "cpu";
+ reg = <8 9>;
+ fsl,portid-mapping = <0x80000000>;
+ };
+ cpu5: PowerPC,e6500@10 {
+ device_type = "cpu";
+ reg = <10 11>;
+ fsl,portid-mapping = <0x80000000>;
+ };
+ cpu6: PowerPC,e6500@12 {
+ device_type = "cpu";
+ reg = <12 13>;
+ fsl,portid-mapping = <0x80000000>;
+ };
+ cpu7: PowerPC,e6500@14 {
+ device_type = "cpu";
+ reg = <14 15>;
+ fsl,portid-mapping = <0x80000000>;
+ };
+ cpu8: PowerPC,e6500@16 {
+ device_type = "cpu";
+ reg = <16 17>;
+ fsl,portid-mapping = <0x80000000>;
+ };
+ cpu9: PowerPC,e6500@18 {
+ device_type = "cpu";
+ reg = <18 19>;
+ fsl,portid-mapping = <0x80000000>;
+ };
+ cpu10: PowerPC,e6500@20 {
+ device_type = "cpu";
+ reg = <20 21>;
+ fsl,portid-mapping = <0x80000000>;
+ };
+ cpu11: PowerPC,e6500@22 {
+ device_type = "cpu";
+ reg = <22 23>;
+ fsl,portid-mapping = <0x80000000>;
+ };
+ };
+
+ soc: soc@ffe000000 {
+ ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+ reg = <0xf 0xfe000000 0 0x00001000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "simple-bus";
+
+ mpic: pic@40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <4>;
+ reg = <0x40000 0x40000>;
+ compatible = "fsl,mpic";
+ device_type = "open-pic";
+ clock-frequency = <0x0>;
+ };
+ };
+
+ pcie@ffe240000 {
+ compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe240000 0x0 0x4000>; /* registers */
+ law_trgt_if = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe250000 {
+ compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe250000 0x0 0x4000>; /* registers */
+ law_trgt_if = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe260000 {
+ compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe260000 0x0 0x4000>; /* registers */
+ law_trgt_if = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe270000 {
+ compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe270000 0x0 0x4000>; /* registers */
+ law_trgt_if = <3>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x60000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+};
diff --git a/arch/powerpc/dts/t4240rdb.dts b/arch/powerpc/dts/t4240rdb.dts
new file mode 100644
index 0000000..f67d7ce
--- /dev/null
+++ b/arch/powerpc/dts/t4240rdb.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * T4240RDB Device Tree Source
+ *
+ * Copyright 2013 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "t4240.dtsi"
+
+/ {
+ model = "fsl,T4240RDB";
+ compatible = "fsl,T4240RDB";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+};
diff --git a/arch/powerpc/dts/u-boot.dtsi b/arch/powerpc/dts/u-boot.dtsi
index 213d543..9661f4d 100644
--- a/arch/powerpc/dts/u-boot.dtsi
+++ b/arch/powerpc/dts/u-boot.dtsi
@@ -24,6 +24,9 @@
#endif
};
#ifdef CONFIG_MPC85XX_HAVE_RESET_VECTOR
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#endif
powerpc-mpc85xx-bootpg-resetvec {
offset = <(CONFIG_RESET_VECTOR_ADDRESS - 0xffc)>;
};
diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c
index 15e9c2a..84691b7 100644
--- a/arch/powerpc/lib/bootm.c
+++ b/arch/powerpc/lib/bootm.c
@@ -8,13 +8,13 @@
#include <common.h>
+#include <env.h>
#include <watchdog.h>
#include <command.h>
#include <image.h>
#include <malloc.h>
#include <u-boot/zlib.h>
#include <bzlib.h>
-#include <environment.h>
#include <asm/byteorder.h>
#include <asm/mp.h>
#include <bootm.h>
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 8cfc7d0..01975d7 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -113,6 +113,23 @@
endchoice
+choice
+ prompt "SPL Run Mode"
+ default SPL_RISCV_MMODE
+ depends on SPL
+
+config SPL_RISCV_MMODE
+ bool "Machine"
+ help
+ Choose this option to build U-Boot SPL for RISC-V M-Mode.
+
+config SPL_RISCV_SMODE
+ bool "Supervisor"
+ help
+ Choose this option to build U-Boot SPL for RISC-V S-Mode.
+
+endchoice
+
config RISCV_ISA_C
bool "Emit compressed instructions"
default y
@@ -132,34 +149,40 @@
config SIFIVE_CLINT
bool
- depends on RISCV_MMODE
+ depends on RISCV_MMODE || SPL_RISCV_MMODE
select REGMAP
select SYSCON
+ select SPL_REGMAP if SPL
+ select SPL_SYSCON if SPL
help
The SiFive CLINT block holds memory-mapped control and status registers
associated with software and timer interrupts.
config ANDES_PLIC
bool
- depends on RISCV_MMODE
+ depends on RISCV_MMODE || SPL_RISCV_MMODE
select REGMAP
select SYSCON
+ select SPL_REGMAP if SPL
+ select SPL_SYSCON if SPL
help
The Andes PLIC block holds memory-mapped claim and pending registers
associated with software interrupt.
config ANDES_PLMT
bool
- depends on RISCV_MMODE
+ depends on RISCV_MMODE || SPL_RISCV_MMODE
select REGMAP
select SYSCON
+ select SPL_REGMAP if SPL
+ select SPL_SYSCON if SPL
help
The Andes PLMT block holds memory-mapped mtime register
associated with timer tick.
config RISCV_RDTIME
bool
- default y if RISCV_SMODE
+ default y if RISCV_SMODE || SPL_RISCV_SMODE
help
The provides the riscv_get_time() API that is implemented using the
standard rdtime instruction. This is the case for S-mode U-Boot, and
@@ -189,7 +212,7 @@
config SBI_IPI
bool
- default y if RISCV_SMODE
+ default y if RISCV_SMODE || SPL_RISCV_SMODE
depends on SMP
config XIP
@@ -203,4 +226,7 @@
int
default 13
+config SPL_LDSCRIPT
+ default "arch/riscv/cpu/u-boot-spl.lds"
+
endmenu
diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index 6b4b92e..d411a79 100644
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -4,8 +4,9 @@
imply CPU
imply CPU_RISCV
imply RISCV_TIMER
- imply ANDES_PLIC if RISCV_MMODE
- imply ANDES_PLMT if RISCV_MMODE
+ imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE)
+ imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE)
+ imply V5L2_CACHE
help
Run U-Boot on AndeStar V5 platforms and use some specific features
which are provided by Andes Technology AndeStar V5 families.
@@ -14,7 +15,7 @@
config RISCV_NDS_CACHE
bool "AndeStar V5 families specific cache support"
- depends on RISCV_MMODE
+ depends on RISCV_MMODE || SPL_RISCV_MMODE
help
Provide Andes Technology AndeStar V5 families specific cache support.
diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c
index cd95058..41de30c 100644
--- a/arch/riscv/cpu/ax25/cache.c
+++ b/arch/riscv/cpu/ax25/cache.c
@@ -5,17 +5,24 @@
*/
#include <common.h>
+#include <dm.h>
+#include <dm/uclass-internal.h>
+#include <cache.h>
+#include <asm/csr.h>
+
+#ifdef CONFIG_RISCV_NDS_CACHE
+/* mcctlcommand */
+#define CCTL_REG_MCCTLCOMMAND_NUM 0x7cc
+
+/* D-cache operation */
+#define CCTL_L1D_WBINVAL_ALL 6
+#endif
void flush_dcache_all(void)
{
- /*
- * Andes' AX25 does not have a coherence agent. U-Boot must use data
- * cache flush and invalidate functions to keep data in the system
- * coherent.
- * The implementation of the fence instruction in the AX25 flushes the
- * data cache and is used for this purpose.
- */
- asm volatile ("fence" ::: "memory");
+#ifdef CONFIG_RISCV_NDS_CACHE
+ csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
+#endif
}
void flush_dcache_range(unsigned long start, unsigned long end)
@@ -59,11 +66,18 @@
{
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#ifdef CONFIG_RISCV_NDS_CACHE
+ struct udevice *dev = NULL;
+
asm volatile (
"csrr t1, mcache_ctl\n\t"
"ori t0, t1, 0x2\n\t"
"csrw mcache_ctl, t0\n\t"
);
+
+ uclass_find_first_device(UCLASS_CACHE, &dev);
+
+ if (dev)
+ cache_enable(dev);
#endif
#endif
}
@@ -72,12 +86,19 @@
{
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#ifdef CONFIG_RISCV_NDS_CACHE
+ struct udevice *dev = NULL;
+
+ csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
asm volatile (
- "fence\n\t"
"csrr t1, mcache_ctl\n\t"
"andi t0, t1, ~0x2\n\t"
"csrw mcache_ctl, t0\n\t"
);
+
+ uclass_find_first_device(UCLASS_CACHE, &dev);
+
+ if (dev)
+ cache_disable(dev);
#endif
#endif
}
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index e9a8b43..e457f6a 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -7,7 +7,6 @@
#include <cpu.h>
#include <dm.h>
#include <log.h>
-#include <asm/csr.h>
#include <asm/encoding.h>
#include <dm/uclass-internal.h>
@@ -47,13 +46,13 @@
return false;
#else /* !CONFIG_CPU */
-#ifdef CONFIG_RISCV_MMODE
- return csr_read(misa) & (1 << (ext - 'a'));
-#else /* !CONFIG_RISCV_MMODE */
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+ return csr_read(CSR_MISA) & (1 << (ext - 'a'));
+#else /* !CONFIG_IS_ENABLED(RISCV_MMODE) */
#warning "There is no way to determine the available extensions in S-mode."
#warning "Please convert your board to use the RISC-V CPU driver."
return false;
-#endif /* CONFIG_RISCV_MMODE */
+#endif /* CONFIG_IS_ENABLED(RISCV_MMODE) */
#endif /* CONFIG_CPU */
}
@@ -82,7 +81,7 @@
/* Enable FPU */
if (supports_extension('d') || supports_extension('f')) {
csr_set(MODE_PREFIX(status), MSTATUS_FS);
- csr_write(fcsr, 0);
+ csr_write(CSR_FCSR, 0);
}
if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
@@ -90,11 +89,11 @@
* Enable perf counters for cycle, time,
* and instret counters only
*/
- csr_write(mcounteren, GENMASK(2, 0));
+ csr_write(CSR_MCOUNTEREN, GENMASK(2, 0));
/* Disable paging */
if (supports_extension('s'))
- csr_write(satp, 0);
+ csr_write(CSR_SATP, 0);
}
return 0;
diff --git a/arch/riscv/cpu/generic/Kconfig b/arch/riscv/cpu/generic/Kconfig
index 1d6ab50..b2cb155 100644
--- a/arch/riscv/cpu/generic/Kconfig
+++ b/arch/riscv/cpu/generic/Kconfig
@@ -8,5 +8,8 @@
imply CPU
imply CPU_RISCV
imply RISCV_TIMER
- imply SIFIVE_CLINT if RISCV_MMODE
+ imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE)
imply CMD_CPU
+ imply SPL_CPU_SUPPORT
+ imply SPL_OPENSBI
+ imply SPL_LOAD_FIT
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 60ac8c6..0a2ce6d 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -13,7 +13,6 @@
#include <config.h>
#include <common.h>
#include <elf.h>
-#include <asm/csr.h>
#include <asm/encoding.h>
#include <generated/asm-offsets.h>
@@ -40,8 +39,8 @@
.section .text
.globl _start
_start:
-#ifdef CONFIG_RISCV_MMODE
- csrr a0, mhartid
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+ csrr a0, CSR_MHARTID
#endif
/* save hart id and dtb pointer */
@@ -63,7 +62,7 @@
#ifdef CONFIG_SMP
/* set xSIE bit to receive IPIs */
-#ifdef CONFIG_RISCV_MMODE
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
li t0, MIE_MSIE
#else
li t0, SIE_SSIE
@@ -76,7 +75,11 @@
*/
call_board_init_f:
li t0, -16
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
+ li t1, CONFIG_SPL_STACK
+#else
li t1, CONFIG_SYS_INIT_SP_ADDR
+#endif
and sp, t1, t0 /* force 16 byte alignment */
call_board_init_f_0:
@@ -160,7 +163,57 @@
mv a0, zero /* a0 <-- boot_flags = 0 */
la t5, board_init_f
- jr t5 /* jump to board_init_f() */
+ jalr t5 /* jump to board_init_f() */
+
+#ifdef CONFIG_SPL_BUILD
+spl_clear_bss:
+ la t0, __bss_start
+ la t1, __bss_end
+ beq t0, t1, spl_stack_gd_setup
+
+spl_clear_bss_loop:
+ SREG zero, 0(t0)
+ addi t0, t0, REGBYTES
+ bne t0, t1, spl_clear_bss_loop
+
+spl_stack_gd_setup:
+ jal spl_relocate_stack_gd
+
+ /* skip setup if we did not relocate */
+ beqz a0, spl_call_board_init_r
+ mv s0, a0
+
+ /* setup stack on main hart */
+#ifdef CONFIG_SMP
+ /* tp: hart id */
+ slli t0, tp, CONFIG_STACK_SIZE_SHIFT
+ sub sp, s0, t0
+#else
+ mv sp, s0
+#endif
+
+ /* set new stack and global data pointer on secondary harts */
+spl_secondary_hart_stack_gd_setup:
+ la a0, secondary_hart_relocate
+ mv a1, s0
+ mv a2, s0
+ jal smp_call_function
+
+ /* hang if relocation of secondary harts has failed */
+ beqz a0, 1f
+ mv a1, a0
+ la a0, secondary_harts_relocation_error
+ jal printf
+ jal hang
+
+ /* set new global data pointer on main hart */
+1: mv gp, s0
+
+spl_call_board_init_r:
+ mv a0, zero
+ mv a1, zero
+ jal board_init_r
+#endif
/*
* void relocate_code (addr_sp, gd, addr_moni)
@@ -216,7 +269,7 @@
/*
* skip first reserved entry: address, type, addend
*/
- bne t1, t2, 7f
+ j 10f
6:
LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */
@@ -227,9 +280,7 @@
add t5, t5, t6 /* t5 <-- location to fix up in RAM */
add t3, t3, t6 /* t3 <-- location to fix up in RAM */
SREG t5, 0(t3)
-7:
- addi t1, t1, (REGBYTES*3)
- ble t1, t2, 6b
+ j 10f
8:
la t4, __dyn_sym_start
@@ -246,13 +297,15 @@
li t5, SYM_SIZE
mul t0, t0, t5
add s5, t4, t0
+ LREG t0, -(REGBYTES)(t1) /* t0 <-- addend */
LREG t5, REGBYTES(s5)
+ add t5, t5, t0
add t5, t5, t6 /* t5 <-- location to fix up in RAM */
add t3, t3, t6 /* t3 <-- location to fix up in RAM */
SREG t5, 0(t3)
10:
addi t1, t1, (REGBYTES*3)
- ble t1, t2, 9b
+ ble t1, t2, 6b
/*
* trap update
@@ -345,7 +398,7 @@
#ifdef CONFIG_SMP
csrr t0, MODE_PREFIX(ip)
-#ifdef CONFIG_RISCV_MMODE
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
andi t0, t0, MIE_MSIE
#else
andi t0, t0, SIE_SSIE
diff --git a/arch/riscv/cpu/u-boot-spl.lds b/arch/riscv/cpu/u-boot-spl.lds
new file mode 100644
index 0000000..32255d5
--- /dev/null
+++ b/arch/riscv/cpu/u-boot-spl.lds
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Based on arch/riscv/cpu/u-boot.lds, which is
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ *
+ * and arch/mips/cpu/u-boot-spl.lds.
+ */
+MEMORY { .spl_mem : ORIGIN = IMAGE_TEXT_BASE, LENGTH = IMAGE_MAX_SIZE }
+MEMORY { .bss_mem : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+ LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_ARCH("riscv")
+ENTRY(_start)
+
+SECTIONS
+{
+ . = ALIGN(4);
+ .text : {
+ arch/riscv/cpu/start.o (.text)
+ *(.text*)
+ } > .spl_mem
+
+ . = ALIGN(4);
+ .rodata : {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ } > .spl_mem
+
+ . = ALIGN(4);
+ .data : {
+ *(.data*)
+ } > .spl_mem
+ . = ALIGN(4);
+
+ .got : {
+ __got_start = .;
+ *(.got.plt) *(.got)
+ __got_end = .;
+ } > .spl_mem
+
+ . = ALIGN(4);
+
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ } > .spl_mem
+
+ . = ALIGN(4);
+
+ .binman_sym_table : {
+ __binman_sym_start = .;
+ KEEP(*(SORT(.binman_sym*)));
+ __binman_sym_end = .;
+ } > .spl_mem
+
+ . = ALIGN(4);
+
+ /DISCARD/ : { *(.rela.plt*) }
+ .rela.dyn : {
+ __rel_dyn_start = .;
+ *(.rela*)
+ __rel_dyn_end = .;
+ } > .spl_mem
+
+ . = ALIGN(4);
+
+ .dynsym : {
+ __dyn_sym_start = .;
+ *(.dynsym)
+ __dyn_sym_end = .;
+ } > .spl_mem
+
+ . = ALIGN(4);
+
+ _end = .;
+
+ .bss : {
+ __bss_start = .;
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_end = .;
+ } > .bss_mem
+}
diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index cb6ee13..97b7cee 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -62,13 +62,18 @@
compatible = "riscv,cpu-intc";
};
};
+ };
- L2: l2-cache@e0500000 {
- compatible = "cache";
- cache-level = <2>;
- cache-size = <0x40000>;
- reg = <0x0 0xe0500000 0x0 0x40000>;
- };
+ L2: l2-cache@e0500000 {
+ compatible = "v5l2cache";
+ cache-level = <2>;
+ cache-size = <0x40000>;
+ reg = <0xe0500000 0x40000>;
+ andes,inst-prefetch = <3>;
+ andes,data-prefetch = <3>;
+ /* The value format is <XRAMOCTL XRAMICTL> */
+ andes,tag-ram-ctl = <0 0>;
+ andes,data-ram-ctl = <0 0>;
};
memory@0 {
diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
index 705491a..d8f00f8 100644
--- a/arch/riscv/dts/ae350_64.dts
+++ b/arch/riscv/dts/ae350_64.dts
@@ -62,13 +62,18 @@
compatible = "riscv,cpu-intc";
};
};
+ };
- L2: l2-cache@e0500000 {
- compatible = "cache";
- cache-level = <2>;
- cache-size = <0x40000>;
- reg = <0x0 0xe0500000 0x0 0x40000>;
- };
+ L2: l2-cache@e0500000 {
+ compatible = "v5l2cache";
+ cache-level = <2>;
+ cache-size = <0x40000>;
+ reg = <0x0 0xe0500000 0x0 0x40000>;
+ andes,inst-prefetch = <3>;
+ andes,data-prefetch = <3>;
+ /* The value format is <XRAMOCTL XRAMICTL> */
+ andes,tag-ram-ctl = <0 0>;
+ andes,data-ram-ctl = <0 0>;
};
memory@0 {
diff --git a/arch/riscv/include/asm/asm.h b/arch/riscv/include/asm/asm.h
new file mode 100644
index 0000000..5a02b7d
--- /dev/null
+++ b/arch/riscv/include/asm/asm.h
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2015 Regents of the University of California
+ */
+
+#ifndef _ASM_RISCV_ASM_H
+#define _ASM_RISCV_ASM_H
+
+#ifdef __ASSEMBLY__
+#define __ASM_STR(x) x
+#else
+#define __ASM_STR(x) #x
+#endif
+
+#if __riscv_xlen == 64
+#define __REG_SEL(a, b) __ASM_STR(a)
+#elif __riscv_xlen == 32
+#define __REG_SEL(a, b) __ASM_STR(b)
+#else
+#error "Unexpected __riscv_xlen"
+#endif
+
+#define REG_L __REG_SEL(ld, lw)
+#define REG_S __REG_SEL(sd, sw)
+#define SZREG __REG_SEL(8, 4)
+#define LGREG __REG_SEL(3, 2)
+
+#if __SIZEOF_POINTER__ == 8
+#ifdef __ASSEMBLY__
+#define RISCV_PTR .dword
+#define RISCV_SZPTR 8
+#define RISCV_LGPTR 3
+#else
+#define RISCV_PTR ".dword"
+#define RISCV_SZPTR "8"
+#define RISCV_LGPTR "3"
+#endif
+#elif __SIZEOF_POINTER__ == 4
+#ifdef __ASSEMBLY__
+#define RISCV_PTR .word
+#define RISCV_SZPTR 4
+#define RISCV_LGPTR 2
+#else
+#define RISCV_PTR ".word"
+#define RISCV_SZPTR "4"
+#define RISCV_LGPTR "2"
+#endif
+#else
+#error "Unexpected __SIZEOF_POINTER__"
+#endif
+
+#if (__SIZEOF_INT__ == 4)
+#define RISCV_INT __ASM_STR(.word)
+#define RISCV_SZINT __ASM_STR(4)
+#define RISCV_LGINT __ASM_STR(2)
+#else
+#error "Unexpected __SIZEOF_INT__"
+#endif
+
+#if (__SIZEOF_SHORT__ == 2)
+#define RISCV_SHORT __ASM_STR(.half)
+#define RISCV_SZSHORT __ASM_STR(2)
+#define RISCV_LGSHORT __ASM_STR(1)
+#else
+#error "Unexpected __SIZEOF_SHORT__"
+#endif
+
+#endif /* _ASM_RISCV_ASM_H */
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 644e6ba..d152074 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2015 Regents of the University of California
*
@@ -8,13 +8,14 @@
#ifndef _ASM_RISCV_CSR_H
#define _ASM_RISCV_CSR_H
+#include <asm/asm.h>
#include <linux/const.h>
/* Status register flags */
#define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */
#define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */
#define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */
-#define SR_SUM _AC(0x00040000, UL) /* Supervisor access User Memory */
+#define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */
#define SR_FS _AC(0x00006000, UL) /* Floating-point Status */
#define SR_FS_OFF _AC(0x00000000, UL)
@@ -35,7 +36,7 @@
#endif
/* SATP flags */
-#if __riscv_xlen == 32
+#ifndef CONFIG_64BIT
#define SATP_PPN _AC(0x003FFFFF, UL)
#define SATP_MODE_32 _AC(0x80000000, UL)
#define SATP_MODE SATP_MODE_32
@@ -45,10 +46,18 @@
#define SATP_MODE SATP_MODE_39
#endif
-/* Interrupt Enable and Interrupt Pending flags */
-#define MIE_MSIE _AC(0x00000008, UL) /* Software Interrupt Enable */
-#define SIE_SSIE _AC(0x00000002, UL) /* Software Interrupt Enable */
-#define SIE_STIE _AC(0x00000020, UL) /* Timer Interrupt Enable */
+/* SCAUSE */
+#define SCAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1))
+
+#define IRQ_U_SOFT 0
+#define IRQ_S_SOFT 1
+#define IRQ_M_SOFT 3
+#define IRQ_U_TIMER 4
+#define IRQ_S_TIMER 5
+#define IRQ_M_TIMER 7
+#define IRQ_U_EXT 8
+#define IRQ_S_EXT 9
+#define IRQ_M_EXT 11
#define EXC_INST_MISALIGNED 0
#define EXC_INST_ACCESS 1
@@ -60,14 +69,47 @@
#define EXC_LOAD_PAGE_FAULT 13
#define EXC_STORE_PAGE_FAULT 15
-#ifndef __ASSEMBLY__
+/* SIE (Interrupt Enable) and SIP (Interrupt Pending) flags */
+#define MIE_MSIE (_AC(0x1, UL) << IRQ_M_SOFT)
+#define SIE_SSIE (_AC(0x1, UL) << IRQ_S_SOFT)
+#define SIE_STIE (_AC(0x1, UL) << IRQ_S_TIMER)
+#define SIE_SEIE (_AC(0x1, UL) << IRQ_S_EXT)
-#define xcsr(csr) #csr
+#define CSR_FCSR 0x003
+#define CSR_CYCLE 0xc00
+#define CSR_TIME 0xc01
+#define CSR_INSTRET 0xc02
+#define CSR_SSTATUS 0x100
+#define CSR_SIE 0x104
+#define CSR_STVEC 0x105
+#define CSR_SCOUNTEREN 0x106
+#define CSR_SSCRATCH 0x140
+#define CSR_SEPC 0x141
+#define CSR_SCAUSE 0x142
+#define CSR_STVAL 0x143
+#define CSR_SIP 0x144
+#define CSR_SATP 0x180
+#define CSR_MSTATUS 0x300
+#define CSR_MISA 0x301
+#define CSR_MIE 0x304
+#define CSR_MTVEC 0x305
+#define CSR_MCOUNTEREN 0x306
+#define CSR_MSCRATCH 0x340
+#define CSR_MEPC 0x341
+#define CSR_MCAUSE 0x342
+#define CSR_MTVAL 0x343
+#define CSR_MIP 0x344
+#define CSR_CYCLEH 0xc80
+#define CSR_TIMEH 0xc81
+#define CSR_INSTRETH 0xc82
+#define CSR_MHARTID 0xf14
+
+#ifndef __ASSEMBLY__
#define csr_swap(csr, val) \
({ \
unsigned long __v = (unsigned long)(val); \
- __asm__ __volatile__ ("csrrw %0, " xcsr(csr) ", %1" \
+ __asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\
: "=r" (__v) : "rK" (__v) \
: "memory"); \
__v; \
@@ -76,7 +118,7 @@
#define csr_read(csr) \
({ \
register unsigned long __v; \
- __asm__ __volatile__ ("csrr %0, " xcsr(csr) \
+ __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \
: "=r" (__v) : \
: "memory"); \
__v; \
@@ -85,7 +127,7 @@
#define csr_write(csr, val) \
({ \
unsigned long __v = (unsigned long)(val); \
- __asm__ __volatile__ ("csrw " xcsr(csr) ", %0" \
+ __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \
: : "rK" (__v) \
: "memory"); \
})
@@ -93,7 +135,7 @@
#define csr_read_set(csr, val) \
({ \
unsigned long __v = (unsigned long)(val); \
- __asm__ __volatile__ ("csrrs %0, " xcsr(csr) ", %1" \
+ __asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\
: "=r" (__v) : "rK" (__v) \
: "memory"); \
__v; \
@@ -102,7 +144,7 @@
#define csr_set(csr, val) \
({ \
unsigned long __v = (unsigned long)(val); \
- __asm__ __volatile__ ("csrs " xcsr(csr) ", %0" \
+ __asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \
: : "rK" (__v) \
: "memory"); \
})
@@ -110,7 +152,7 @@
#define csr_read_clear(csr, val) \
({ \
unsigned long __v = (unsigned long)(val); \
- __asm__ __volatile__ ("csrrc %0, " xcsr(csr) ", %1" \
+ __asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\
: "=r" (__v) : "rK" (__v) \
: "memory"); \
__v; \
@@ -119,7 +161,7 @@
#define csr_clear(csr, val) \
({ \
unsigned long __v = (unsigned long)(val); \
- __asm__ __volatile__ ("csrc " xcsr(csr) ", %0" \
+ __asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \
: : "rK" (__v) \
: "memory"); \
})
diff --git a/arch/riscv/include/asm/encoding.h b/arch/riscv/include/asm/encoding.h
index 772668c..a0695da 100644
--- a/arch/riscv/include/asm/encoding.h
+++ b/arch/riscv/include/asm/encoding.h
@@ -7,7 +7,9 @@
#ifndef RISCV_CSR_ENCODING_H
#define RISCV_CSR_ENCODING_H
-#ifdef CONFIG_RISCV_SMODE
+#include <asm/csr.h>
+
+#if CONFIG_IS_ENABLED(RISCV_SMODE)
#define MODE_PREFIX(__suffix) s##__suffix
#else
#define MODE_PREFIX(__suffix) m##__suffix
@@ -49,13 +51,10 @@
#define SSTATUS64_SD 0x8000000000000000
#define MIP_SSIP BIT(IRQ_S_SOFT)
-#define MIP_HSIP BIT(IRQ_H_SOFT)
#define MIP_MSIP BIT(IRQ_M_SOFT)
#define MIP_STIP BIT(IRQ_S_TIMER)
-#define MIP_HTIP BIT(IRQ_H_TIMER)
#define MIP_MTIP BIT(IRQ_M_TIMER)
#define MIP_SEIP BIT(IRQ_S_EXT)
-#define MIP_HEIP BIT(IRQ_H_EXT)
#define MIP_MEIP BIT(IRQ_M_EXT)
#define SIP_SSIP MIP_SSIP
@@ -73,18 +72,6 @@
#define VM_SV39 9
#define VM_SV48 10
-#define IRQ_S_SOFT 1
-#define IRQ_H_SOFT 2
-#define IRQ_M_SOFT 3
-#define IRQ_S_TIMER 5
-#define IRQ_H_TIMER 6
-#define IRQ_M_TIMER 7
-#define IRQ_S_EXT 9
-#define IRQ_H_EXT 10
-#define IRQ_M_EXT 11
-#define IRQ_COP 12
-#define IRQ_HOST 13
-
#define CAUSE_MISALIGNED_FETCH 0
#define CAUSE_FETCH_ACCESS 1
#define CAUSE_ILLEGAL_INSTRUCTION 2
@@ -167,227 +154,6 @@
#define RISCV_PGSHIFT 12
#define RISCV_PGSIZE BIT(RISCV_PGSHIFT)
-/* CSR numbers */
-#define CSR_FFLAGS 0x1
-#define CSR_FRM 0x2
-#define CSR_FCSR 0x3
-
-#define CSR_SSTATUS 0x100
-#define CSR_SEDELEG 0x102
-#define CSR_SIDELEG 0x103
-#define CSR_SIE 0x104
-#define CSR_STVEC 0x105
-#define CSR_SCOUNTEREN 0x106
-#define CSR_SSCRATCH 0x140
-#define CSR_SEPC 0x141
-#define CSR_SCAUSE 0x142
-#define CSR_STVAL 0x143
-#define CSR_SIP 0x144
-#define CSR_SATP 0x180
-
-#define CSR_MSTATUS 0x300
-#define CSR_MISA 0x301
-#define CSR_MEDELEG 0x302
-#define CSR_MIDELEG 0x303
-#define CSR_MIE 0x304
-#define CSR_MTVEC 0x305
-#define CSR_MCOUNTEREN 0x306
-#define CSR_MHPMEVENT3 0x323
-#define CSR_MHPMEVENT4 0x324
-#define CSR_MHPMEVENT5 0x325
-#define CSR_MHPMEVENT6 0x326
-#define CSR_MHPMEVENT7 0x327
-#define CSR_MHPMEVENT8 0x328
-#define CSR_MHPMEVENT9 0x329
-#define CSR_MHPMEVENT10 0x32a
-#define CSR_MHPMEVENT11 0x32b
-#define CSR_MHPMEVENT12 0x32c
-#define CSR_MHPMEVENT13 0x32d
-#define CSR_MHPMEVENT14 0x32e
-#define CSR_MHPMEVENT15 0x32f
-#define CSR_MHPMEVENT16 0x330
-#define CSR_MHPMEVENT17 0x331
-#define CSR_MHPMEVENT18 0x332
-#define CSR_MHPMEVENT19 0x333
-#define CSR_MHPMEVENT20 0x334
-#define CSR_MHPMEVENT21 0x335
-#define CSR_MHPMEVENT22 0x336
-#define CSR_MHPMEVENT23 0x337
-#define CSR_MHPMEVENT24 0x338
-#define CSR_MHPMEVENT25 0x339
-#define CSR_MHPMEVENT26 0x33a
-#define CSR_MHPMEVENT27 0x33b
-#define CSR_MHPMEVENT28 0x33c
-#define CSR_MHPMEVENT29 0x33d
-#define CSR_MHPMEVENT30 0x33e
-#define CSR_MHPMEVENT31 0x33f
-#define CSR_MSCRATCH 0x340
-#define CSR_MEPC 0x341
-#define CSR_MCAUSE 0x342
-#define CSR_MTVAL 0x343
-#define CSR_MIP 0x344
-#define CSR_PMPCFG0 0x3a0
-#define CSR_PMPCFG1 0x3a1
-#define CSR_PMPCFG2 0x3a2
-#define CSR_PMPCFG3 0x3a3
-#define CSR_PMPADDR0 0x3b0
-#define CSR_PMPADDR1 0x3b1
-#define CSR_PMPADDR2 0x3b2
-#define CSR_PMPADDR3 0x3b3
-#define CSR_PMPADDR4 0x3b4
-#define CSR_PMPADDR5 0x3b5
-#define CSR_PMPADDR6 0x3b6
-#define CSR_PMPADDR7 0x3b7
-#define CSR_PMPADDR8 0x3b8
-#define CSR_PMPADDR9 0x3b9
-#define CSR_PMPADDR10 0x3ba
-#define CSR_PMPADDR11 0x3bb
-#define CSR_PMPADDR12 0x3bc
-#define CSR_PMPADDR13 0x3bd
-#define CSR_PMPADDR14 0x3be
-#define CSR_PMPADDR15 0x3bf
-
-#define CSR_TSELECT 0x7a0
-#define CSR_TDATA1 0x7a1
-#define CSR_TDATA2 0x7a2
-#define CSR_TDATA3 0x7a3
-#define CSR_DCSR 0x7b0
-#define CSR_DPC 0x7b1
-#define CSR_DSCRATCH 0x7b2
-
-#define CSR_MCYCLE 0xb00
-#define CSR_MINSTRET 0xb02
-#define CSR_MHPMCOUNTER3 0xb03
-#define CSR_MHPMCOUNTER4 0xb04
-#define CSR_MHPMCOUNTER5 0xb05
-#define CSR_MHPMCOUNTER6 0xb06
-#define CSR_MHPMCOUNTER7 0xb07
-#define CSR_MHPMCOUNTER8 0xb08
-#define CSR_MHPMCOUNTER9 0xb09
-#define CSR_MHPMCOUNTER10 0xb0a
-#define CSR_MHPMCOUNTER11 0xb0b
-#define CSR_MHPMCOUNTER12 0xb0c
-#define CSR_MHPMCOUNTER13 0xb0d
-#define CSR_MHPMCOUNTER14 0xb0e
-#define CSR_MHPMCOUNTER15 0xb0f
-#define CSR_MHPMCOUNTER16 0xb10
-#define CSR_MHPMCOUNTER17 0xb11
-#define CSR_MHPMCOUNTER18 0xb12
-#define CSR_MHPMCOUNTER19 0xb13
-#define CSR_MHPMCOUNTER20 0xb14
-#define CSR_MHPMCOUNTER21 0xb15
-#define CSR_MHPMCOUNTER22 0xb16
-#define CSR_MHPMCOUNTER23 0xb17
-#define CSR_MHPMCOUNTER24 0xb18
-#define CSR_MHPMCOUNTER25 0xb19
-#define CSR_MHPMCOUNTER26 0xb1a
-#define CSR_MHPMCOUNTER27 0xb1b
-#define CSR_MHPMCOUNTER28 0xb1c
-#define CSR_MHPMCOUNTER29 0xb1d
-#define CSR_MHPMCOUNTER30 0xb1e
-#define CSR_MHPMCOUNTER31 0xb1f
-#define CSR_MCYCLEH 0xb80
-#define CSR_MINSTRETH 0xb82
-#define CSR_MHPMCOUNTER3H 0xb83
-#define CSR_MHPMCOUNTER4H 0xb84
-#define CSR_MHPMCOUNTER5H 0xb85
-#define CSR_MHPMCOUNTER6H 0xb86
-#define CSR_MHPMCOUNTER7H 0xb87
-#define CSR_MHPMCOUNTER8H 0xb88
-#define CSR_MHPMCOUNTER9H 0xb89
-#define CSR_MHPMCOUNTER10H 0xb8a
-#define CSR_MHPMCOUNTER11H 0xb8b
-#define CSR_MHPMCOUNTER12H 0xb8c
-#define CSR_MHPMCOUNTER13H 0xb8d
-#define CSR_MHPMCOUNTER14H 0xb8e
-#define CSR_MHPMCOUNTER15H 0xb8f
-#define CSR_MHPMCOUNTER16H 0xb90
-#define CSR_MHPMCOUNTER17H 0xb91
-#define CSR_MHPMCOUNTER18H 0xb92
-#define CSR_MHPMCOUNTER19H 0xb93
-#define CSR_MHPMCOUNTER20H 0xb94
-#define CSR_MHPMCOUNTER21H 0xb95
-#define CSR_MHPMCOUNTER22H 0xb96
-#define CSR_MHPMCOUNTER23H 0xb97
-#define CSR_MHPMCOUNTER24H 0xb98
-#define CSR_MHPMCOUNTER25H 0xb99
-#define CSR_MHPMCOUNTER26H 0xb9a
-#define CSR_MHPMCOUNTER27H 0xb9b
-#define CSR_MHPMCOUNTER28H 0xb9c
-#define CSR_MHPMCOUNTER29H 0xb9d
-#define CSR_MHPMCOUNTER30H 0xb9e
-#define CSR_MHPMCOUNTER31H 0xb9f
-
-#define CSR_CYCLE 0xc00
-#define CSR_TIME 0xc01
-#define CSR_INSTRET 0xc02
-#define CSR_HPMCOUNTER3 0xc03
-#define CSR_HPMCOUNTER4 0xc04
-#define CSR_HPMCOUNTER5 0xc05
-#define CSR_HPMCOUNTER6 0xc06
-#define CSR_HPMCOUNTER7 0xc07
-#define CSR_HPMCOUNTER8 0xc08
-#define CSR_HPMCOUNTER9 0xc09
-#define CSR_HPMCOUNTER10 0xc0a
-#define CSR_HPMCOUNTER11 0xc0b
-#define CSR_HPMCOUNTER12 0xc0c
-#define CSR_HPMCOUNTER13 0xc0d
-#define CSR_HPMCOUNTER14 0xc0e
-#define CSR_HPMCOUNTER15 0xc0f
-#define CSR_HPMCOUNTER16 0xc10
-#define CSR_HPMCOUNTER17 0xc11
-#define CSR_HPMCOUNTER18 0xc12
-#define CSR_HPMCOUNTER19 0xc13
-#define CSR_HPMCOUNTER20 0xc14
-#define CSR_HPMCOUNTER21 0xc15
-#define CSR_HPMCOUNTER22 0xc16
-#define CSR_HPMCOUNTER23 0xc17
-#define CSR_HPMCOUNTER24 0xc18
-#define CSR_HPMCOUNTER25 0xc19
-#define CSR_HPMCOUNTER26 0xc1a
-#define CSR_HPMCOUNTER27 0xc1b
-#define CSR_HPMCOUNTER28 0xc1c
-#define CSR_HPMCOUNTER29 0xc1d
-#define CSR_HPMCOUNTER30 0xc1e
-#define CSR_HPMCOUNTER31 0xc1f
-#define CSR_CYCLEH 0xc80
-#define CSR_TIMEH 0xc81
-#define CSR_INSTRETH 0xc82
-#define CSR_HPMCOUNTER3H 0xc83
-#define CSR_HPMCOUNTER4H 0xc84
-#define CSR_HPMCOUNTER5H 0xc85
-#define CSR_HPMCOUNTER6H 0xc86
-#define CSR_HPMCOUNTER7H 0xc87
-#define CSR_HPMCOUNTER8H 0xc88
-#define CSR_HPMCOUNTER9H 0xc89
-#define CSR_HPMCOUNTER10H 0xc8a
-#define CSR_HPMCOUNTER11H 0xc8b
-#define CSR_HPMCOUNTER12H 0xc8c
-#define CSR_HPMCOUNTER13H 0xc8d
-#define CSR_HPMCOUNTER14H 0xc8e
-#define CSR_HPMCOUNTER15H 0xc8f
-#define CSR_HPMCOUNTER16H 0xc90
-#define CSR_HPMCOUNTER17H 0xc91
-#define CSR_HPMCOUNTER18H 0xc92
-#define CSR_HPMCOUNTER19H 0xc93
-#define CSR_HPMCOUNTER20H 0xc94
-#define CSR_HPMCOUNTER21H 0xc95
-#define CSR_HPMCOUNTER22H 0xc96
-#define CSR_HPMCOUNTER23H 0xc97
-#define CSR_HPMCOUNTER24H 0xc98
-#define CSR_HPMCOUNTER25H 0xc99
-#define CSR_HPMCOUNTER26H 0xc9a
-#define CSR_HPMCOUNTER27H 0xc9b
-#define CSR_HPMCOUNTER28H 0xc9c
-#define CSR_HPMCOUNTER29H 0xc9d
-#define CSR_HPMCOUNTER30H 0xc9e
-#define CSR_HPMCOUNTER31H 0xc9f
-
-#define CSR_MVENDORID 0xf11
-#define CSR_MARCHID 0xf12
-#define CSR_MIMPID 0xf13
-#define CSR_MHARTID 0xf14
-
#endif /* __riscv */
#endif /* RISCV_CSR_ENCODING_H */
diff --git a/arch/riscv/include/asm/spl.h b/arch/riscv/include/asm/spl.h
new file mode 100644
index 0000000..45c03fb
--- /dev/null
+++ b/arch/riscv/include/asm/spl.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Based on arch/mips/include/asm/spl.h.
+ *
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ */
+#ifndef _ASM_RISCV_SPL_H_
+#define _ASM_RISCV_SPL_H_
+
+enum {
+ BOOT_DEVICE_RAM,
+ BOOT_DEVICE_MMC1,
+ BOOT_DEVICE_MMC2,
+ BOOT_DEVICE_MMC2_2,
+ BOOT_DEVICE_NAND,
+ BOOT_DEVICE_ONENAND,
+ BOOT_DEVICE_NOR,
+ BOOT_DEVICE_UART,
+ BOOT_DEVICE_SPI,
+ BOOT_DEVICE_USB,
+ BOOT_DEVICE_SATA,
+ BOOT_DEVICE_I2C,
+ BOOT_DEVICE_BOARD,
+ BOOT_DEVICE_DFU,
+ BOOT_DEVICE_XIP,
+ BOOT_DEVICE_BOOTROM,
+ BOOT_DEVICE_NONE
+};
+
+#endif
diff --git a/arch/riscv/include/asm/u-boot.h b/arch/riscv/include/asm/u-boot.h
index 3186835..5ba8e77 100644
--- a/arch/riscv/include/asm/u-boot.h
+++ b/arch/riscv/include/asm/u-boot.h
@@ -20,7 +20,6 @@
#include <asm/u-boot-riscv.h>
-#include <environment.h>
typedef struct bd_info {
unsigned long bi_boot_params; /* where this board expects params */
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 6ae6ebb..c9179a5 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -10,15 +10,19 @@
obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
obj-$(CONFIG_CMD_GO) += boot.o
obj-y += cache.o
-obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
+ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
obj-$(CONFIG_ANDES_PLMT) += andes_plmt.o
+else
+obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
+obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
+endif
obj-y += interrupts.o
obj-y += reset.o
-obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
obj-y += setjmp.o
obj-$(CONFIG_SMP) += smp.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
# For building EFI apps
CFLAGS_$(EFI_CRT0) := $(CFLAGS_EFI)
diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
index 2ffe49a..28568e4 100644
--- a/arch/riscv/lib/andes_plic.c
+++ b/arch/riscv/lib/andes_plic.c
@@ -44,15 +44,12 @@
} \
} while (0)
-static int enable_ipi(int harts)
+static int enable_ipi(int hart)
{
- int i;
- int en = ENABLE_HART_IPI;
+ int en;
- for (i = 0; i < harts; i++) {
- en = en >> i;
- writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, i));
- }
+ en = ENABLE_HART_IPI >> hart;
+ writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart));
return 0;
}
@@ -60,18 +57,35 @@
static int init_plic(void)
{
struct udevice *dev;
+ ofnode node;
int ret;
+ u32 reg;
ret = uclass_find_first_device(UCLASS_CPU, &dev);
if (ret)
return ret;
if (ret == 0 && dev) {
- ret = cpu_get_count(dev);
- if (ret < 0)
- return ret;
+ ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
+ const char *device_type;
- enable_ipi(ret);
+ device_type = ofnode_read_string(node, "device_type");
+ if (!device_type)
+ continue;
+
+ if (strcmp(device_type, "cpu"))
+ continue;
+
+ /* skip if hart is marked as not available */
+ if (!ofnode_is_available(node))
+ continue;
+
+ /* read hart ID of CPU */
+ ret = ofnode_read_u32(node, "reg", ®);
+ if (ret == 0)
+ enable_ipi(reg);
+ }
+
return 0;
}
diff --git a/arch/riscv/lib/crt0_riscv_efi.S b/arch/riscv/lib/crt0_riscv_efi.S
index b7b5329..87fe1e5 100644
--- a/arch/riscv/lib/crt0_riscv_efi.S
+++ b/arch/riscv/lib/crt0_riscv_efi.S
@@ -14,12 +14,12 @@
#define SIZE_LONG 8
#define SAVE_LONG(reg, idx) sd reg, (idx*SIZE_LONG)(sp)
#define LOAD_LONG(reg, idx) ld reg, (idx*SIZE_LONG)(sp)
-#define PE_MACHINE 0x5064
+#define PE_MACHINE IMAGE_FILE_MACHINE_RISCV64
#else
#define SIZE_LONG 4
#define SAVE_LONG(reg, idx) sw reg, (idx*SIZE_LONG)(sp)
#define LOAD_LONG(reg, idx) lw reg, (idx*SIZE_LONG)(sp)
-#define PE_MACHINE 0x5032
+#define PE_MACHINE IMAGE_FILE_MACHINE_RISCV32
#endif
@@ -30,12 +30,11 @@
*/
.globl ImageBase
ImageBase:
- .ascii "MZ"
+ .short IMAGE_DOS_SIGNATURE /* 'MZ' */
.skip 58 /* 'MZ' + pad + offset == 64 */
.long pe_header - ImageBase /* Offset to the PE header */
pe_header:
- .ascii "PE"
- .short 0
+ .long IMAGE_NT_SIGNATURE /* 'PE' */
coff_header:
.short PE_MACHINE /* RISC-V 64/32-bit */
.short 2 /* nr_sections */
@@ -49,7 +48,7 @@
IMAGE_FILE_LOCAL_SYMS_STRIPPED | \
IMAGE_FILE_DEBUG_STRIPPED)
optional_header:
- .short 0x20b /* PE32+ format */
+ .short IMAGE_NT_OPTIONAL_HDR64_MAGIC /* PE32+ format */
.byte 0x02 /* MajorLinkerVersion */
.byte 0x14 /* MinorLinkerVersion */
.long _edata - _start /* SizeOfCode */
diff --git a/arch/riscv/lib/mkimage_fit_opensbi.sh b/arch/riscv/lib/mkimage_fit_opensbi.sh
new file mode 100755
index 0000000..d6f95e5
--- /dev/null
+++ b/arch/riscv/lib/mkimage_fit_opensbi.sh
@@ -0,0 +1,100 @@
+#!/bin/sh
+# SPDX-License-Identifier: GPL-2.0+
+#
+# script to generate FIT image source for RISC-V boards with OpenSBI
+# and, optionally, multiple device trees (given on the command line).
+#
+# usage: $0 [<dt_name> [<dt_name] ...]
+
+[ -z "$OPENSBI" ] && OPENSBI="fw_dynamic.bin"
+
+if [ -z "$UBOOT_LOAD_ADDR" ]; then
+ UBOOT_LOAD_ADDR="$(grep "^CONFIG_SYS_TEXT_BASE=" .config | awk 'BEGIN{FS="="} {print $2}')"
+fi
+
+if [ -z "$OPENSBI_LOAD_ADDR" ]; then
+ OPENSBI_LOAD_ADDR="$(grep "^CONFIG_SPL_OPENSBI_LOAD_ADDR=" .config | awk 'BEGIN{FS="="} {print $2}')"
+fi
+
+if [ ! -f $OPENSBI ]; then
+ echo "WARNING: OpenSBI binary \"$OPENSBI\" not found, resulting binary is not functional." >&2
+ OPENSBI=/dev/null
+fi
+
+cat << __HEADER_EOF
+/dts-v1/;
+
+/ {
+ description = "Configuration to load OpenSBI before U-Boot";
+
+ images {
+ uboot {
+ description = "U-Boot";
+ data = /incbin/("u-boot-nodtb.bin");
+ type = "standalone";
+ os = "U-Boot";
+ arch = "riscv";
+ compression = "none";
+ load = <$UBOOT_LOAD_ADDR>;
+ };
+ opensbi {
+ description = "RISC-V OpenSBI";
+ data = /incbin/("$OPENSBI");
+ type = "firmware";
+ os = "opensbi";
+ arch = "riscv";
+ compression = "none";
+ load = <$OPENSBI_LOAD_ADDR>;
+ entry = <$OPENSBI_LOAD_ADDR>;
+ };
+__HEADER_EOF
+
+cnt=1
+for dtname in $*
+do
+ cat << __FDT_IMAGE_EOF
+ fdt_$cnt {
+ description = "$(basename $dtname .dtb)";
+ data = /incbin/("$dtname");
+ type = "flat_dt";
+ compression = "none";
+ };
+__FDT_IMAGE_EOF
+cnt=$((cnt+1))
+done
+
+cat << __CONF_HEADER_EOF
+ };
+ configurations {
+ default = "config_1";
+
+__CONF_HEADER_EOF
+
+if [ $# -eq 0 ]; then
+cat << __CONF_SECTION_EOF
+ config_1 {
+ description = "U-Boot FIT";
+ firmware = "opensbi";
+ loadables = "uboot";
+ };
+__CONF_SECTION_EOF
+else
+cnt=1
+for dtname in $*
+do
+cat << __CONF_SECTION_EOF
+ config_$cnt {
+ description = "$(basename $dtname .dtb)";
+ firmware = "opensbi";
+ loadables = "uboot";
+ fdt = "fdt_$cnt";
+ };
+__CONF_SECTION_EOF
+cnt=$((cnt+1))
+done
+fi
+
+cat << __ITS_EOF
+ };
+};
+__ITS_EOF
diff --git a/arch/riscv/lib/spl.c b/arch/riscv/lib/spl.c
new file mode 100644
index 0000000..bea8695
--- /dev/null
+++ b/arch/riscv/lib/spl.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Fraunhofer AISEC,
+ * Lukas Auer <lukas.auer@aisec.fraunhofer.de>
+ */
+#include <common.h>
+#include <spl.h>
+#include <asm/smp.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+__weak void board_init_f(ulong dummy)
+{
+ int ret;
+
+ ret = spl_early_init();
+ if (ret)
+ panic("spl_early_init() failed: %d\n", ret);
+
+ arch_cpu_init_dm();
+
+ preloader_console_init();
+}
+
+void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+{
+ typedef void __noreturn (*image_entry_riscv_t)(ulong hart, void *dtb);
+ void *fdt_blob;
+ int ret;
+
+#if CONFIG_IS_ENABLED(LOAD_FIT) || CONFIG_IS_ENABLED(LOAD_FIT_FULL)
+ fdt_blob = spl_image->fdt_addr;
+#else
+ fdt_blob = (void *)gd->fdt_blob;
+#endif
+
+ image_entry_riscv_t image_entry =
+ (image_entry_riscv_t)spl_image->entry_point;
+ invalidate_icache_all();
+
+ debug("image entry point: 0x%lX\n", spl_image->entry_point);
+#ifdef CONFIG_SMP
+ ret = smp_call_function(spl_image->entry_point, (ulong)fdt_blob, 0);
+ if (ret)
+ hang();
+#endif
+ image_entry(gd->arch.boot_hart, fdt_blob);
+}
diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk
index 31a12db..05fbbd7 100644
--- a/arch/sandbox/config.mk
+++ b/arch/sandbox/config.mk
@@ -5,14 +5,15 @@
PLATFORM_CPPFLAGS += -DCONFIG_ARCH_MAP_SYSMEM
PLATFORM_CPPFLAGS += -fPIC
PLATFORM_LIBS += -lrt
+SDL_CONFIG ?= sdl-config
# Define this to avoid linking with SDL, which requires SDL libraries
# This can solve 'sdl-config: Command not found' errors
ifneq ($(NO_SDL),)
PLATFORM_CPPFLAGS += -DSANDBOX_NO_SDL
else
-PLATFORM_LIBS += $(shell sdl-config --libs)
-PLATFORM_CPPFLAGS += $(shell sdl-config --cflags)
+PLATFORM_LIBS += $(shell $(SDL_CONFIG) --libs)
+PLATFORM_CPPFLAGS += $(shell $(SDL_CONFIG) --cflags)
endif
cmd_u-boot__ = $(CC) -o $@ -Wl,-T u-boot.lds $(u-boot-init) \
diff --git a/arch/sandbox/cpu/spl.c b/arch/sandbox/cpu/spl.c
index 2ca4cd6..4f415c7 100644
--- a/arch/sandbox/cpu/spl.c
+++ b/arch/sandbox/cpu/spl.c
@@ -12,6 +12,7 @@
DECLARE_GLOBAL_DATA_PTR;
+/* SPL / TPL init function */
void board_init_f(ulong flag)
{
struct sandbox_state *state = state_get_current();
@@ -44,7 +45,7 @@
return 0;
}
-SPL_LOAD_IMAGE_METHOD("sandbox", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
+SPL_LOAD_IMAGE_METHOD("sandbox", 9, BOOT_DEVICE_BOARD, spl_board_load_image);
void spl_board_init(void)
{
diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c
index d3b9c05..dee5fde 100644
--- a/arch/sandbox/cpu/state.c
+++ b/arch/sandbox/cpu/state.c
@@ -355,7 +355,7 @@
{
/* No reset yet, so mark it as such. Always allow power reset */
state->last_sysreset = SYSRESET_COUNT;
- state->sysreset_allowed[SYSRESET_POWER] = true;
+ state->sysreset_allowed[SYSRESET_POWER_OFF] = true;
memset(&state->wdt, '\0', sizeof(state->wdt));
memset(state->spi, '\0', sizeof(state->spi));
diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts
index a41b5f0..16a33db 100644
--- a/arch/sandbox/dts/sandbox.dts
+++ b/arch/sandbox/dts/sandbox.dts
@@ -1,6 +1,6 @@
/dts-v1/;
-#define USB_CLASS_HUB 9
+#include <config.h>
/ {
#address-cells = <1>;
@@ -12,46 +12,17 @@
pci0 = &pci;
rtc0 = &rtc_0;
axi0 = &axi;
+ spi0 = &spi;
};
- chosen {
- stdout-path = "/serial";
- };
-
- audio: audio-codec {
- compatible = "sandbox,audio-codec";
- #sound-dai-cells = <1>;
+ memory {
+ reg = <0 CONFIG_SYS_SDRAM_SIZE>;
};
cros_ec: cros-ec {
reg = <0 0>;
u-boot,dm-pre-reloc;
compatible = "google,cros-ec-sandbox";
-
- /*
- * This describes the flash memory within the EC. Note
- * that the STM32L flash erases to 0, not 0xff.
- */
- flash {
- u-boot,dm-pre-reloc;
- image-pos = <0x08000000>;
- size = <0x20000>;
- erase-value = <0>;
-
- /* Information for sandbox */
- ro {
- image-pos = <0>;
- size = <0xf000>;
- };
- wp-ro {
- image-pos = <0xf000>;
- size = <0x1000>;
- };
- rw {
- image-pos = <0x10000>;
- size = <0x10000>;
- };
- };
};
ethrawbus {
@@ -65,30 +36,6 @@
fake-host-hwaddr = [00 00 66 44 22 00];
};
- gpio_a: gpios@0 {
- u-boot,dm-pre-reloc;
- gpio-controller;
- compatible = "sandbox,gpio";
- #gpio-cells = <1>;
- gpio-bank-name = "a";
- sandbox,gpio-count = <20>;
- };
-
- gpio_b: gpios@1 {
- u-boot,dm-pre-reloc;
- gpio-controller;
- compatible = "sandbox,gpio";
- #gpio-cells = <2>;
- gpio-bank-name = "b";
- sandbox,gpio-count = <10>;
- };
-
- hexagon {
- compatible = "demo-simple";
- colour = "white";
- sides = <6>;
- };
-
i2c_0: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
@@ -97,63 +44,6 @@
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
- eeprom@2c {
- reg = <0x2c>;
- compatible = "i2c-eeprom";
- sandbox,emul = <&emul_eeprom>;
- };
-
- rtc_0: rtc@43 {
- reg = <0x43>;
- compatible = "sandbox-rtc";
- sandbox,emul = <&emul0>;
- };
- sandbox_pmic: sandbox_pmic {
- reg = <0x40>;
- };
-
- mc34708: pmic@41 {
- reg = <0x41>;
- };
-
- i2c_emul: emul {
- reg = <0xff>;
- compatible = "sandbox,i2c-emul-parent";
- emul_eeprom: emul-eeprom {
- compatible = "sandbox,i2c-eeprom";
- sandbox,filename = "i2c.bin";
- sandbox,size = <256>;
- };
- emul0: emul0 {
- compatible = "sandbox,i2c-rtc";
- };
- };
- };
-
- i2s: i2s {
- compatible = "sandbox,i2s";
- #sound-dai-cells = <1>;
- };
-
- lcd {
- u-boot,dm-pre-reloc;
- compatible = "sandbox,lcd-sdl";
- xres = <1366>;
- yres = <768>;
- };
-
- leds {
- compatible = "gpio-leds";
-
- iracibble {
- gpios = <&gpio_a 1 0>;
- label = "sandbox:red";
- };
-
- martinet {
- gpios = <&gpio_a 2 0>;
- label = "sandbox:green";
- };
};
pci: pci-controller {
@@ -163,233 +53,19 @@
#size-cells = <2>;
ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000
0x01000000 0 0x20000000 0x20000000 0 0x2000>;
- pci@1f,0 {
- compatible = "pci-generic";
- reg = <0xf800 0 0 0 0>;
- emul@1f,0 {
- compatible = "sandbox,swap-case";
- };
- };
};
- pinctrl {
- compatible = "sandbox,pinctrl";
- status = "okay";
-
- pinctrl_i2c0: i2c0 {
- groups = "i2c";
- function = "i2c";
- bias-pull-up;
- };
-
- pinctrl_serial0: uart0 {
- groups = "serial_a";
- function = "serial";
- };
-
- pinctrl_onewire0: onewire0 {
- groups = "w1";
- function = "w1";
- bias-pull-up;
- };
- };
-
- reset@1 {
- compatible = "sandbox,reset";
- };
-
- sound {
- compatible = "sandbox,sound";
- cpu {
- sound-dai = <&i2s 0>;
- };
-
- codec {
- sound-dai = <&audio 0>;
- };
- };
-
- spi@0 {
+ spi: spi@0 {
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0>;
compatible = "sandbox,spi";
cs-gpios = <0>, <&gpio_a 0>;
- firmware_storage_spi: flash@0 {
- u-boot,dm-pre-reloc;
- reg = <0>;
- compatible = "spansion,m25p16", "sandbox,spi-flash";
- spi-max-frequency = <40000000>;
- sandbox,filename = "spi.bin";
- };
};
- spl-test {
- u-boot,dm-pre-reloc;
- compatible = "sandbox,spl-test";
- boolval;
- intval = <1>;
- intarray = <2 3 4>;
- byteval = [05];
- bytearray = [06];
- longbytearray = [09 0a 0b 0c 0d 0e 0f 10 11];
- stringval = "message";
- stringarray = "multi-word", "message";
- };
-
- spl-test2 {
- u-boot,dm-pre-reloc;
- compatible = "sandbox,spl-test";
- intval = <3>;
- intarray = <5>;
- byteval = [08];
- bytearray = [01 23 34];
- longbytearray = [09 0a 0b 0c];
- stringval = "message2";
- stringarray = "another", "multi-word", "message";
- };
-
- spl-test3 {
- u-boot,dm-pre-reloc;
- compatible = "sandbox,spl-test";
- stringarray = "one";
- };
-
- spl-test4 {
- u-boot,dm-pre-reloc;
- compatible = "sandbox,spl-test.2";
- };
-
- square {
- compatible = "demo-shape";
- colour = "blue";
- sides = <4>;
- };
-
- timer {
- compatible = "sandbox,timer";
- clock-frequency = <1000000>;
- };
-
- tpm {
- u-boot,dm-pre-reloc;
- compatible = "google,sandbox-tpm";
- };
-
- tpm2 {
- compatible = "sandbox,tpm2";
- };
-
- triangle {
- compatible = "demo-shape";
- colour = "cyan";
- sides = <3>;
- character = <83>;
- light-gpios = <&gpio_a 2>, <&gpio_b 6 0>;
- };
-
- /* Needs to be available prior to relocation */
- uart0: serial {
- u-boot,dm-spl;
- compatible = "sandbox,serial";
- sandbox,text-colour = "cyan";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_serial0>;
- };
-
- usb@0 {
- compatible = "sandbox,usb";
- status = "disabled";
- hub {
- compatible = "sandbox,usb-hub";
- #address-cells = <1>;
- #size-cells = <0>;
- flash-stick {
- reg = <0>;
- compatible = "sandbox,usb-flash";
- };
- };
- };
-
- usb@1 {
- compatible = "sandbox,usb";
- hub {
- compatible = "usb-hub";
- usb,device-class = <USB_CLASS_HUB>;
- hub-emul {
- compatible = "sandbox,usb-hub";
- #address-cells = <1>;
- #size-cells = <0>;
- flash-stick {
- reg = <0>;
- compatible = "sandbox,usb-flash";
- sandbox,filepath = "flash.bin";
- };
- };
- };
- };
-
- usb@2 {
- compatible = "sandbox,usb";
- status = "disabled";
- };
-
- spmi: spmi@0 {
- compatible = "sandbox,spmi";
- #address-cells = <0x1>;
- #size-cells = <0x1>;
- pm8916@0 {
- compatible = "qcom,spmi-pmic";
- reg = <0x0 0x1>;
- #address-cells = <0x1>;
- #size-cells = <0x1>;
-
- spmi_gpios: gpios@c000 {
- compatible = "qcom,pm8916-gpio";
- reg = <0xc000 0x400>;
- gpio-controller;
- gpio-count = <4>;
- #gpio-cells = <2>;
- gpio-bank-name="spmi";
- };
- };
- };
-
- axi: axi@0 {
- compatible = "sandbox,axi";
- #address-cells = <0x1>;
- #size-cells = <0x1>;
- store@0 {
- compatible = "sandbox,sandbox_store";
- reg = <0x0 0x400>;
- };
- };
-
- onewire0: onewire {
- compatible = "w1-gpio";
- gpios = <&gpio_a 8>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_onewire0>;
- status = "okay";
-
- sandbox_eeprom0: sandbox_eeprom@0 {
- compatible = "sandbox,w1-eeprom";
- status = "okay";
- };
- };
-
- sandbox_tee {
- compatible = "sandbox,tee";
- };
};
+#include "sandbox.dtsi"
#include "cros-ec-keyboard.dtsi"
#include "sandbox_pmic.dtsi"
-
-&cros_ec {
- u-boot,dm-pre-reloc;
- keyboard-controller {
- u-boot,dm-pre-reloc;
- };
-};
diff --git a/arch/sandbox/dts/sandbox.dtsi b/arch/sandbox/dts/sandbox.dtsi
new file mode 100644
index 0000000..c6d5650
--- /dev/null
+++ b/arch/sandbox/dts/sandbox.dtsi
@@ -0,0 +1,364 @@
+/*
+ * This is the common sandbox device-tree nodes. This is shared between sandbox
+ * and sandbox64 builds.
+ */
+
+#define USB_CLASS_HUB 9
+
+/ {
+ chosen {
+ stdout-path = "/serial";
+ };
+
+ audio: audio-codec {
+ compatible = "sandbox,audio-codec";
+ #sound-dai-cells = <1>;
+ };
+
+ gpio_a: gpios@0 {
+ u-boot,dm-pre-reloc;
+ gpio-controller;
+ compatible = "sandbox,gpio";
+ #gpio-cells = <1>;
+ gpio-bank-name = "a";
+ sandbox,gpio-count = <20>;
+ };
+
+ gpio_b: gpios@1 {
+ u-boot,dm-pre-reloc;
+ gpio-controller;
+ compatible = "sandbox,gpio";
+ #gpio-cells = <2>;
+ gpio-bank-name = "b";
+ sandbox,gpio-count = <10>;
+ };
+
+ hexagon {
+ compatible = "demo-simple";
+ colour = "white";
+ sides = <6>;
+ };
+
+ i2c_0: i2c@0 {
+ eeprom@2c {
+ reg = <0x2c>;
+ compatible = "i2c-eeprom";
+ sandbox,emul = <&emul_eeprom>;
+ };
+
+ rtc_0: rtc@43 {
+ reg = <0x43>;
+ compatible = "sandbox-rtc";
+ sandbox,emul = <&emul0>;
+ };
+ sandbox_pmic: sandbox_pmic {
+ reg = <0x40>;
+ };
+
+ mc34708: pmic@41 {
+ reg = <0x41>;
+ };
+
+ i2c_emul: emul {
+ reg = <0xff>;
+ compatible = "sandbox,i2c-emul-parent";
+ emul_eeprom: emul-eeprom {
+ compatible = "sandbox,i2c-eeprom";
+ sandbox,filename = "i2c.bin";
+ sandbox,size = <256>;
+ };
+ emul0: emul0 {
+ compatible = "sandbox,i2c-rtc";
+ };
+ };
+ };
+
+ i2s: i2s {
+ compatible = "sandbox,i2s";
+ #sound-dai-cells = <1>;
+ };
+
+ lcd {
+ u-boot,dm-pre-reloc;
+ compatible = "sandbox,lcd-sdl";
+ xres = <1366>;
+ yres = <768>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ iracibble {
+ gpios = <&gpio_a 1 0>;
+ label = "sandbox:red";
+ };
+
+ martinet {
+ gpios = <&gpio_a 2 0>;
+ label = "sandbox:green";
+ };
+ };
+
+ pci-controller {
+ pci@1f,0 {
+ compatible = "pci-generic";
+ reg = <0xf800 0 0 0 0>;
+ emul@1f,0 {
+ compatible = "sandbox,swap-case";
+ };
+ };
+ };
+
+ pinctrl {
+ compatible = "sandbox,pinctrl";
+ status = "okay";
+
+ pinctrl_i2c0: i2c0 {
+ groups = "i2c";
+ function = "i2c";
+ bias-pull-up;
+ };
+
+ pinctrl_serial0: uart0 {
+ groups = "serial_a";
+ function = "serial";
+ };
+
+ pinctrl_onewire0: onewire0 {
+ groups = "w1";
+ function = "w1";
+ bias-pull-up;
+ };
+ };
+
+ reset@1 {
+ compatible = "sandbox,reset";
+ };
+
+ sound {
+ compatible = "sandbox,sound";
+ cpu {
+ sound-dai = <&i2s 0>;
+ };
+
+ codec {
+ sound-dai = <&audio 0>;
+ };
+ };
+
+ spi@0 {
+ firmware_storage_spi: flash@0 {
+ u-boot,dm-pre-reloc;
+ reg = <0>;
+ compatible = "spansion,m25p16", "jedec,spi-nor";
+ spi-max-frequency = <40000000>;
+ sandbox,filename = "spi.bin";
+ };
+ };
+
+ spl-test {
+ u-boot,dm-pre-reloc;
+ compatible = "sandbox,spl-test";
+ boolval;
+ intval = <1>;
+ intarray = <2 3 4>;
+ byteval = [05];
+ bytearray = [06];
+ longbytearray = [09 0a 0b 0c 0d 0e 0f 10 11];
+ stringval = "message";
+ stringarray = "multi-word", "message";
+ };
+
+ spl-test2 {
+ u-boot,dm-pre-reloc;
+ compatible = "sandbox,spl-test";
+ intval = <3>;
+ intarray = <5>;
+ byteval = [08];
+ bytearray = [01 23 34];
+ longbytearray = [09 0a 0b 0c];
+ stringval = "message2";
+ stringarray = "another", "multi-word", "message";
+ };
+
+ spl-test3 {
+ u-boot,dm-pre-reloc;
+ compatible = "sandbox,spl-test";
+ stringarray = "one";
+ };
+
+ spl-test4 {
+ u-boot,dm-pre-reloc;
+ compatible = "sandbox,spl-test.2";
+ };
+
+ spl-test5 {
+ u-boot,dm-tpl;
+ compatible = "sandbox,spl-test";
+ stringarray = "tpl";
+ };
+
+ spl-test6 {
+ u-boot,dm-pre-proper;
+ compatible = "sandbox,spl-test";
+ stringarray = "pre-proper";
+ };
+
+ spl-test7 {
+ u-boot,dm-spl;
+ compatible = "sandbox,spl-test";
+ stringarray = "spl";
+ };
+
+ square {
+ compatible = "demo-shape";
+ colour = "blue";
+ sides = <4>;
+ };
+
+ timer {
+ compatible = "sandbox,timer";
+ clock-frequency = <1000000>;
+ };
+
+ tpm {
+ u-boot,dm-pre-reloc;
+ compatible = "google,sandbox-tpm";
+ };
+
+ tpm2 {
+ compatible = "sandbox,tpm2";
+ };
+
+ triangle {
+ compatible = "demo-shape";
+ colour = "cyan";
+ sides = <3>;
+ character = <83>;
+ light-gpios = <&gpio_a 2>, <&gpio_b 6 0>;
+ };
+
+ /* Needs to be available prior to relocation */
+ uart0: serial {
+ u-boot,dm-spl;
+ compatible = "sandbox,serial";
+ sandbox,text-colour = "cyan";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_serial0>;
+ };
+
+ usb@0 {
+ compatible = "sandbox,usb";
+ status = "disabled";
+ hub {
+ compatible = "sandbox,usb-hub";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ flash-stick {
+ reg = <0>;
+ compatible = "sandbox,usb-flash";
+ };
+ };
+ };
+
+ usb@1 {
+ compatible = "sandbox,usb";
+ hub {
+ compatible = "usb-hub";
+ usb,device-class = <USB_CLASS_HUB>;
+ hub-emul {
+ compatible = "sandbox,usb-hub";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ flash-stick {
+ reg = <0>;
+ compatible = "sandbox,usb-flash";
+ sandbox,filepath = "flash.bin";
+ };
+ };
+ };
+ };
+
+ usb@2 {
+ compatible = "sandbox,usb";
+ status = "disabled";
+ };
+
+ spmi: spmi@0 {
+ compatible = "sandbox,spmi";
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ pm8916@0 {
+ compatible = "qcom,spmi-pmic";
+ reg = <0x0 0x1>;
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+
+ spmi_gpios: gpios@c000 {
+ compatible = "qcom,pm8916-gpio";
+ reg = <0xc000 0x400>;
+ gpio-controller;
+ gpio-count = <4>;
+ #gpio-cells = <2>;
+ gpio-bank-name="spmi";
+ };
+ };
+ };
+
+ axi: axi@0 {
+ compatible = "sandbox,axi";
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ store@0 {
+ compatible = "sandbox,sandbox_store";
+ reg = <0x0 0x400>;
+ };
+ };
+
+ onewire0: onewire {
+ compatible = "w1-gpio";
+ gpios = <&gpio_a 8>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_onewire0>;
+ status = "okay";
+
+ sandbox_eeprom0: sandbox_eeprom@0 {
+ compatible = "sandbox,w1-eeprom";
+ status = "okay";
+ };
+ };
+
+ sandbox_tee {
+ compatible = "sandbox,tee";
+ };
+};
+
+&cros_ec {
+ /*
+ * This describes the flash memory within the EC. Note
+ * that the STM32L flash erases to 0, not 0xff.
+ */
+ flash {
+ image-pos = <0x08000000>;
+ size = <0x20000>;
+ erase-value = <0>;
+
+ /* Information for sandbox */
+ ro {
+ image-pos = <0>;
+ size = <0xf000>;
+ };
+ wp-ro {
+ image-pos = <0xf000>;
+ size = <0x1000>;
+ };
+ rw {
+ image-pos = <0x10000>;
+ size = <0x10000>;
+ };
+ };
+
+ keyboard-controller {
+ u-boot,dm-pre-reloc;
+ };
+};
diff --git a/arch/sandbox/dts/sandbox64.dts b/arch/sandbox/dts/sandbox64.dts
index a3c95f2..37a5539 100644
--- a/arch/sandbox/dts/sandbox64.dts
+++ b/arch/sandbox/dts/sandbox64.dts
@@ -1,6 +1,6 @@
/dts-v1/;
-#define USB_CLASS_HUB 9
+#include <config.h>
/ {
#address-cells = <2>;
@@ -11,39 +11,18 @@
i2c0 = &i2c_0;
pci0 = &pci;
rtc0 = &rtc_0;
+ axi0 = &axi;
+ spi0 = &spi;
};
- chosen {
- stdout-path = "/serial";
+ memory {
+ reg = /bits/ 64 <0 CONFIG_SYS_SDRAM_SIZE>;
};
cros_ec: cros-ec {
reg = <0 0 0 0>;
+ u-boot,dm-pre-reloc;
compatible = "google,cros-ec-sandbox";
-
- /*
- * This describes the flash memory within the EC. Note
- * that the STM32L flash erases to 0, not 0xff.
- */
- flash {
- image-pos = <0x08000000>;
- size = <0x20000>;
- erase-value = <0>;
-
- /* Information for sandbox */
- ro {
- image-pos = <0>;
- size = <0xf000>;
- };
- wp-ro {
- image-pos = <0xf000>;
- size = <0x1000>;
- };
- rw {
- image-pos = <0x10000>;
- size = <0x10000>;
- };
- };
};
ethrawbus {
@@ -57,28 +36,6 @@
fake-host-hwaddr = [00 00 66 44 22 00];
};
- gpio_a: gpios@0 {
- gpio-controller;
- compatible = "sandbox,gpio";
- #gpio-cells = <1>;
- gpio-bank-name = "a";
- sandbox,gpio-count = <20>;
- };
-
- gpio_b: gpios@1 {
- gpio-controller;
- compatible = "sandbox,gpio";
- #gpio-cells = <2>;
- gpio-bank-name = "b";
- sandbox,gpio-count = <10>;
- };
-
- hexagon {
- compatible = "demo-simple";
- colour = "white";
- sides = <6>;
- };
-
i2c_0: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
@@ -87,58 +44,6 @@
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
- eeprom@2c {
- reg = <0x2c>;
- compatible = "i2c-eeprom";
- sandbox,emul = <&emul_eeprom>;
- };
-
- rtc_0: rtc@43 {
- reg = <0x43>;
- compatible = "sandbox-rtc";
- sandbox,emul = <&emul0>;
- };
- sandbox_pmic: sandbox_pmic {
- reg = <0x40>;
- };
-
- mc34708: pmic@41 {
- reg = <0x41>;
- };
-
- i2c_emul: emul {
- reg = <0xff>;
- compatible = "sandbox,i2c-emul-parent";
- emul_eeprom: emul-eeprom {
- compatible = "sandbox,i2c-eeprom";
- sandbox,filename = "i2c.bin";
- sandbox,size = <256>;
- };
- emul0: emul0 {
- compatible = "sandbox,i2c-rtc";
- };
- };
- };
-
- lcd {
- u-boot,dm-pre-reloc;
- compatible = "sandbox,lcd-sdl";
- xres = <1366>;
- yres = <768>;
- };
-
- leds {
- compatible = "gpio-leds";
-
- iracibble {
- gpios = <&gpio_a 1 0>;
- label = "sandbox:red";
- };
-
- martinet {
- gpios = <&gpio_a 2 0>;
- label = "sandbox:green";
- };
};
pci: pci-controller {
@@ -148,181 +53,19 @@
#size-cells = <2>;
ranges = <0x02000000 0 0x10000000 0 0x10000000 0 0x2000
0x01000000 0 0x20000000 0 0x20000000 0 0x2000>;
- pci@1f,0 {
- compatible = "pci-generic";
- reg = <0xf800 0 0 0 0>;
- emul@1f,0 {
- compatible = "sandbox,swap-case";
- };
- };
};
- pinctrl {
- compatible = "sandbox,pinctrl";
-
- pinctrl_i2c0: i2c0 {
- groups = "i2c";
- function = "i2c";
- bias-pull-up;
- };
-
- pinctrl_serial0: uart0 {
- groups = "serial_a";
- function = "serial";
- };
- };
-
- reset@1 {
- compatible = "sandbox,reset";
- };
-
- spi@0 {
+ spi: spi@0 {
+ u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0 0 0>;
compatible = "sandbox,spi";
cs-gpios = <0>, <&gpio_a 0>;
- firmware_storage_spi: flash@0 {
- reg = <0>;
- compatible = "spansion,m25p16", "sandbox,spi-flash";
- spi-max-frequency = <40000000>;
- sandbox,filename = "spi.bin";
- };
};
- spl-test {
- u-boot,dm-pre-reloc;
- compatible = "sandbox,spl-test";
- boolval;
- intval = <1>;
- intarray = <2 3 4>;
- byteval = [05];
- bytearray = [06];
- longbytearray = [09 0a 0b 0c 0d 0e 0f 10 11];
- stringval = "message";
- stringarray = "multi-word", "message";
- };
-
- spl-test2 {
- u-boot,dm-pre-reloc;
- compatible = "sandbox,spl-test";
- intval = <3>;
- intarray = <5>;
- byteval = [08];
- bytearray = [01 23 34];
- longbytearray = [09 0a 0b 0c];
- stringval = "message2";
- stringarray = "another", "multi-word", "message";
- };
-
- spl-test3 {
- u-boot,dm-pre-reloc;
- compatible = "sandbox,spl-test";
- stringarray = "one";
- };
-
- spl-test4 {
- u-boot,dm-pre-reloc;
- compatible = "sandbox,spl-test.2";
- };
-
- square {
- compatible = "demo-shape";
- colour = "blue";
- sides = <4>;
- };
-
- timer {
- compatible = "sandbox,timer";
- clock-frequency = <1000000>;
- };
-
- tpm {
- compatible = "google,sandbox-tpm";
- };
-
- tpm2 {
- compatible = "sandbox,tpm2";
- };
-
- triangle {
- compatible = "demo-shape";
- colour = "cyan";
- sides = <3>;
- character = <83>;
- light-gpios = <&gpio_a 2>, <&gpio_b 6 0>;
- };
-
- /* Needs to be available prior to relocation */
- uart0: serial {
- compatible = "sandbox,serial";
- sandbox,text-colour = "cyan";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_serial0>;
- };
-
- usb@0 {
- compatible = "sandbox,usb";
- status = "disabled";
- hub {
- compatible = "sandbox,usb-hub";
- #address-cells = <1>;
- #size-cells = <0>;
- flash-stick {
- reg = <0>;
- compatible = "sandbox,usb-flash";
- };
- };
- };
-
- usb@1 {
- compatible = "sandbox,usb";
- hub {
- compatible = "usb-hub";
- usb,device-class = <USB_CLASS_HUB>;
- hub-emul {
- compatible = "sandbox,usb-hub";
- #address-cells = <1>;
- #size-cells = <0>;
- flash-stick {
- reg = <0>;
- compatible = "sandbox,usb-flash";
- sandbox,filepath = "flash.bin";
- };
- };
- };
- };
-
- usb@2 {
- compatible = "sandbox,usb";
- status = "disabled";
- };
-
- spmi: spmi@0 {
- compatible = "sandbox,spmi";
- #address-cells = <0x1>;
- #size-cells = <0x1>;
- pm8916@0 {
- compatible = "qcom,spmi-pmic";
- reg = <0x0 0x1>;
- #address-cells = <0x1>;
- #size-cells = <0x1>;
-
- spmi_gpios: gpios@c000 {
- compatible = "qcom,pm8916-gpio";
- reg = <0xc000 0x400>;
- gpio-controller;
- gpio-count = <4>;
- #gpio-cells = <2>;
- gpio-bank-name="spmi";
- };
- };
- };
-
- sandbox_tee {
- compatible = "sandbox,tee";
- };
};
+#include "sandbox.dtsi"
#include "cros-ec-keyboard.dtsi"
#include "sandbox_pmic.dtsi"
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index c328258..27b0baa 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -211,6 +211,12 @@
clock-mult = <2>;
clocks = <&clk_fixed>;
};
+
+ osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <20000000>;
+ };
};
clk_sandbox: clk-sbox {
@@ -226,6 +232,10 @@
clock-names = "fixed", "i2c", "spi";
};
+ ccf: clk-ccf {
+ compatible = "sandbox,clk-ccf";
+ };
+
eth@10002000 {
compatible = "sandbox,eth";
reg = <0x10002000 0x1000>;
@@ -446,6 +456,14 @@
compatible = "sandbox,swap-case";
};
};
+ pci@1,0 {
+ compatible = "pci-generic";
+ reg = <0x0800 0 0 0 0>;
+ emul@0,0 {
+ compatible = "sandbox,swap-case";
+ use-ea;
+ };
+ };
pci@1f,0 {
compatible = "pci-generic";
reg = <0xf800 0 0 0 0>;
@@ -487,6 +505,10 @@
};
};
+ pci_ep: pci_ep {
+ compatible = "sandbox,pci_ep";
+ };
+
probing {
compatible = "simple-bus";
test1 {
@@ -744,6 +766,10 @@
3 0x300 0xB000 0x1000
>;
+ dma-ranges = <0 0x000 0x10000000 0x1000
+ 1 0x100 0x20000000 0x1000
+ >;
+
dev@0,0 {
compatible = "denx,u-boot-fdt-dummy";
reg = <0 0x0 0x1000>;
@@ -811,6 +837,31 @@
dmas = <&dma 0>, <&dma 1>, <&dma 2>;
dma-names = "m2m", "tx0", "rx0";
};
+
+ /*
+ * keep mdio-mux ahead of mdio so that the mux is removed first at the
+ * end of the test. If parent mdio is removed first, clean-up of the
+ * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
+ * active at the end of the test. That it turn doesn't allow the mdio
+ * class to be destroyed, triggering an error.
+ */
+ mdio-mux-test {
+ compatible = "sandbox,mdio-mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mdio-parent-bus = <&mdio>;
+
+ mdio-ch-test@0 {
+ reg = <0>;
+ };
+ mdio-ch-test@1 {
+ reg = <1>;
+ };
+ };
+
+ mdio: mdio-test {
+ compatible = "sandbox,mdio";
+ };
};
#include "sandbox_pmic.dtsi"
diff --git a/arch/sandbox/include/asm/spi.h b/arch/sandbox/include/asm/spi.h
index 9985e3c..98e1826 100644
--- a/arch/sandbox/include/asm/spi.h
+++ b/arch/sandbox/include/asm/spi.h
@@ -1,5 +1,5 @@
/*
- * Simulate a SPI port and clients (see README.sandbox for details)
+ * Simulate a SPI port and clients (see doc/arch/sandbox.rst for details)
*
* Copyright (c) 2011-2013 The Chromium OS Authors.
* See file CREDITS for list of people who contributed to this
diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h
index e956a05..cbf2096 100644
--- a/arch/sandbox/include/asm/test.h
+++ b/arch/sandbox/include/asm/test.h
@@ -19,6 +19,7 @@
#define PCI_CAP_ID_PM_OFFSET 0x50
#define PCI_CAP_ID_EXP_OFFSET 0x60
#define PCI_CAP_ID_MSIX_OFFSET 0x70
+#define PCI_CAP_ID_EA_OFFSET 0x80
#define PCI_EXT_CAP_ID_ERR_OFFSET 0x100
#define PCI_EXT_CAP_ID_VC_OFFSET 0x200
@@ -30,6 +31,18 @@
#define SANDBOX_CLK_RATE 32768
+/* Macros used to test PCI EA capability structure */
+#define PCI_CAP_EA_BASE_LO0 0x00100000
+#define PCI_CAP_EA_BASE_LO1 0x00110000
+#define PCI_CAP_EA_BASE_LO2 0x00120000
+#define PCI_CAP_EA_BASE_LO4 0x00140000
+#define PCI_CAP_EA_BASE_HI2 0x00020000ULL
+#define PCI_CAP_EA_BASE_HI4 0x00040000ULL
+#define PCI_CAP_EA_SIZE_LO 0x0000ffff
+#define PCI_CAP_EA_SIZE_HI 0x00000010ULL
+#define PCI_EA_BAR2_MAGIC 0x72727272
+#define PCI_EA_BAR4_MAGIC 0x74747474
+
/* System controller driver data */
enum {
SYSCON0 = 32,
@@ -177,4 +190,12 @@
*/
int sandbox_get_pch_spi_protect(struct udevice *dev);
+/**
+ * sandbox_get_pci_ep_irq_count() - Get the PCI EP IRQ count
+ *
+ * @dev: Device to check
+ * @return irq count
+ */
+int sandbox_get_pci_ep_irq_count(struct udevice *dev);
+
#endif
diff --git a/arch/sh/cpu/sh4/config.mk b/arch/sh/cpu/sh4/config.mk
index d62d285..23fec66 100644
--- a/arch/sh/cpu/sh4/config.mk
+++ b/arch/sh/cpu/sh4/config.mk
@@ -6,4 +6,4 @@
# (C) Copyright 2007
# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
#
-PLATFORM_CPPFLAGS += -m4-nofpu
+PLATFORM_CPPFLAGS += $(call cc-option,-m4-nofpu,-m4)
diff --git a/arch/sh/cpu/u-boot.lds b/arch/sh/cpu/u-boot.lds
index 7b225a6..4cc9773 100644
--- a/arch/sh/cpu/u-boot.lds
+++ b/arch/sh/cpu/u-boot.lds
@@ -25,6 +25,7 @@
SECTIONS
{
+ . = CONFIG_SYS_TEXT_BASE;
reloc_dst = .;
PROVIDE (_ftext = .);
@@ -75,6 +76,7 @@
PROVIDE (__init_end = .);
PROVIDE (reloc_dst_end = .);
+ PROVIDE (_end = .);
PROVIDE (bss_start = .);
PROVIDE (__bss_start = .);
diff --git a/arch/sh/dts/Makefile b/arch/sh/dts/Makefile
new file mode 100644
index 0000000..e423bfd
--- /dev/null
+++ b/arch/sh/dts/Makefile
@@ -0,0 +1,12 @@
+dtb-y += sh7751-r2dplus.dtb
+
+targets += $(dtb-y)
+
+# Add any required device tree compiler flags here
+DTC_FLAGS +=
+
+PHONY += dtbs
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+ @:
+
+clean-files := *.dtb *_HS
diff --git a/arch/sh/dts/sh7751-r2dplus.dts b/arch/sh/dts/sh7751-r2dplus.dts
new file mode 100644
index 0000000..efaeb33
--- /dev/null
+++ b/arch/sh/dts/sh7751-r2dplus.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the SH7751 R2Dplus
+ *
+ * Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
+ */
+
+/dts-v1/;
+/ {
+ model = "R2D";
+ compatible = "renesas,r2d", "renesas,sh7751";
+
+ pci@fe200000 {
+ compatible = "renesas,pci-sh7751";
+ device_type = "pci";
+ reg = <0 0xfe200000 0 0x1000>;
+ status = "okay";
+
+ bus-range = <0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x01000000 0 0xfe240000 0 0xfe240000 0 0x00040000
+ 0x02000000 0 0xfd000000 0 0xfd000000 0 0x01000000
+ 0x42000000 0 0x0c000000 0 0x8c000000 0 0x04000000>;
+ };
+};
diff --git a/arch/sh/include/asm/config.h b/arch/sh/include/asm/config.h
index df38c82..e1cd322 100644
--- a/arch/sh/include/asm/config.h
+++ b/arch/sh/include/asm/config.h
@@ -8,9 +8,11 @@
#include <asm/processor.h>
+#define CONFIG_LMB
+
/* Timer */
#define CONFIG_SYS_TIMER_COUNTS_DOWN
-#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0x8) /* TCNT0 */
+#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */
#define CONFIG_SYS_TIMER_RATE (CONFIG_SYS_CLK_FREQ / 4)
#endif
diff --git a/arch/sh/lib/start.S b/arch/sh/lib/start.S
index f5350b9..f9f26d3 100644
--- a/arch/sh/lib/start.S
+++ b/arch/sh/lib/start.S
@@ -22,6 +22,17 @@
mov.l ._reloc_dst, r4
add #(_start-1b), r5
mov.l ._reloc_dst_end, r6
+#ifdef CONFIG_OF_SEPARATE
+ mov.l ._reloc_size, r0
+ add r5, r0
+ add #4, r0
+ mov.l @r0, r0
+ swap.b r0, r0
+ swap.w r0, r0
+ swap.b r0, r0
+ add #4, r0
+ add r0, r6
+#endif
2: mov.l @r5+, r1
mov.l r1, @r4
@@ -29,6 +40,7 @@
cmp/hs r6, r4
bf 2b
+#ifndef CONFIG_OF_SEPARATE
mov.l ._bss_start, r4
mov.l ._bss_end, r5
mov #0, r1
@@ -37,6 +49,7 @@
add #4, r4
cmp/hs r5, r4
bf 3b
+#endif
mov.l ._gd_init, r13 /* global data */
mov.l ._stack_init, r15 /* stack */
@@ -53,6 +66,7 @@
._lowlevel_init: .long (lowlevel_init - (100b + 4))
._reloc_dst: .long _start
._reloc_dst_end: .long reloc_dst_end
+._reloc_size: .long (_end - _start)
._bss_start: .long bss_start
._bss_end: .long bss_end
._gd_init: .long (_start - GENERATED_GBL_DATA_SIZE)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 70f9398..218e817 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -115,6 +115,7 @@
source "arch/x86/cpu/qemu/Kconfig"
source "arch/x86/cpu/quark/Kconfig"
source "arch/x86/cpu/queensbay/Kconfig"
+source "arch/x86/cpu/slimbootloader/Kconfig"
source "arch/x86/cpu/tangier/Kconfig"
# architecture-specific options below
@@ -344,9 +345,17 @@
The filename of the file to use as Intel Management Engine in the
board directory.
+config USE_HOB
+ bool "Use HOB (Hand-Off Block)"
+ help
+ Select this option to access HOB (Hand-Off Block) data structures
+ and parse HOBs. This HOB infra structure can be reused with
+ different solutions across different platforms.
+
config HAVE_FSP
bool "Add an Firmware Support Package binary"
depends on !EFI
+ select USE_HOB
help
Select this option to add an Firmware Support Package binary to
the resulting U-Boot image. It is a binary blob which U-Boot uses
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 85fd5e6..3f1f62d 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -42,6 +42,7 @@
obj-$(CONFIG_INTEL_BRASWELL) += braswell/
obj-$(CONFIG_INTEL_BROADWELL) += broadwell/
obj-$(CONFIG_SYS_COREBOOT) += coreboot/
+obj-$(CONFIG_SYS_SLIMBOOTLOADER) += slimbootloader/
obj-$(CONFIG_EFI) += efi/
obj-$(CONFIG_QEMU) += qemu/
obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index 4c6ed0b..9686f8e 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -73,9 +73,6 @@
int last_stage_init(void)
{
- if (gd->flags & GD_FLG_COLD_BOOT)
- timestamp_add_to_bootstage();
-
/* start usb so that usb keyboard can be used as input device */
if (CONFIG_IS_ENABLED(USB_KEYBOARD))
usb_init();
diff --git a/arch/x86/cpu/i386/interrupt.c b/arch/x86/cpu/i386/interrupt.c
index 47df317..1445204 100644
--- a/arch/x86/cpu/i386/interrupt.c
+++ b/arch/x86/cpu/i386/interrupt.c
@@ -12,6 +12,7 @@
#include <common.h>
#include <dm.h>
+#include <efi_loader.h>
#include <asm/control_regs.h>
#include <asm/i8259.h>
#include <asm/interrupt.h>
@@ -64,6 +65,18 @@
"Reserved"
};
+/**
+ * show_efi_loaded_images() - show loaded UEFI images
+ *
+ * List all loaded UEFI images.
+ *
+ * @eip: instruction pointer
+ */
+static void show_efi_loaded_images(uintptr_t eip)
+{
+ efi_print_image_infos((void *)eip);
+}
+
static void dump_regs(struct irq_regs *regs)
{
unsigned long cs, eip, eflags;
@@ -144,6 +157,7 @@
printf("0x%8.8lx : 0x%8.8lx\n", sp, (ulong)readl(sp));
sp -= 4;
}
+ show_efi_loaded_images(eip);
}
static void do_exception(struct irq_regs *regs)
diff --git a/arch/x86/cpu/qemu/dram.c b/arch/x86/cpu/qemu/dram.c
index 736c4c3..6707b7b 100644
--- a/arch/x86/cpu/qemu/dram.c
+++ b/arch/x86/cpu/qemu/dram.c
@@ -9,7 +9,7 @@
DECLARE_GLOBAL_DATA_PTR;
-int dram_init(void)
+u32 qemu_get_low_memory_size(void)
{
u32 ram;
@@ -19,7 +19,27 @@
ram |= ((u32)inb(CMOS_DATA_PORT)) << 6;
ram += 16 * 1024;
- gd->ram_size = ram * 1024;
+ return ram * 1024;
+}
+
+u64 qemu_get_high_memory_size(void)
+{
+ u64 ram;
+
+ outb(HIGH_HIGHRAM_ADDR, CMOS_ADDR_PORT);
+ ram = ((u64)inb(CMOS_DATA_PORT)) << 22;
+ outb(MID_HIGHRAM_ADDR, CMOS_ADDR_PORT);
+ ram |= ((u64)inb(CMOS_DATA_PORT)) << 14;
+ outb(LOW_HIGHRAM_ADDR, CMOS_ADDR_PORT);
+ ram |= ((u64)inb(CMOS_DATA_PORT)) << 6;
+
+ return ram * 1024;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = qemu_get_low_memory_size();
+ gd->ram_size += qemu_get_high_memory_size();
post_code(POST_DRAM);
return 0;
@@ -27,8 +47,16 @@
int dram_init_banksize(void)
{
+ u64 high_mem_size;
+
gd->bd->bi_dram[0].start = 0;
- gd->bd->bi_dram[0].size = gd->ram_size;
+ gd->bd->bi_dram[0].size = qemu_get_low_memory_size();
+
+ high_mem_size = qemu_get_high_memory_size();
+ if (high_mem_size) {
+ gd->bd->bi_dram[1].start = SZ_4G;
+ gd->bd->bi_dram[1].size = high_mem_size;
+ }
return 0;
}
@@ -43,5 +71,5 @@
*/
ulong board_get_usable_ram_top(ulong total_size)
{
- return gd->ram_size;
+ return qemu_get_low_memory_size();
}
diff --git a/arch/x86/cpu/qemu/e820.c b/arch/x86/cpu/qemu/e820.c
index 0a690fd..a4136eb 100644
--- a/arch/x86/cpu/qemu/e820.c
+++ b/arch/x86/cpu/qemu/e820.c
@@ -1,45 +1,67 @@
// SPDX-License-Identifier: GPL-2.0+
/*
+ * QEMU x86 specific E820 table generation
+ *
* (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
+ * (C) Copyright 2019 Bin Meng <bmeng.cn@gmail.com>
*/
#include <common.h>
+#include <env_internal.h>
#include <asm/e820.h>
+#include <asm/arch/qemu.h>
DECLARE_GLOBAL_DATA_PTR;
unsigned int install_e820_map(unsigned int max_entries,
struct e820_entry *entries)
{
- entries[0].addr = 0;
- entries[0].size = ISA_START_ADDRESS;
- entries[0].type = E820_RAM;
+ u64 high_mem_size;
+ int n = 0;
- entries[1].addr = ISA_START_ADDRESS;
- entries[1].size = ISA_END_ADDRESS - ISA_START_ADDRESS;
- entries[1].type = E820_RESERVED;
+ entries[n].addr = 0;
+ entries[n].size = ISA_START_ADDRESS;
+ entries[n].type = E820_RAM;
+ n++;
+
+ entries[n].addr = ISA_START_ADDRESS;
+ entries[n].size = ISA_END_ADDRESS - ISA_START_ADDRESS;
+ entries[n].type = E820_RESERVED;
+ n++;
/*
* since we use memalign(malloc) to allocate high memory for
* storing ACPI tables, we need to reserve them in e820 tables,
* otherwise kernel will reclaim them and data will be corrupted
*/
- entries[2].addr = ISA_END_ADDRESS;
- entries[2].size = gd->relocaddr - TOTAL_MALLOC_LEN - ISA_END_ADDRESS;
- entries[2].type = E820_RAM;
+ entries[n].addr = ISA_END_ADDRESS;
+ entries[n].size = gd->relocaddr - TOTAL_MALLOC_LEN - ISA_END_ADDRESS;
+ entries[n].type = E820_RAM;
+ n++;
/* for simplicity, reserve entire malloc space */
- entries[3].addr = gd->relocaddr - TOTAL_MALLOC_LEN;
- entries[3].size = TOTAL_MALLOC_LEN;
- entries[3].type = E820_RESERVED;
+ entries[n].addr = gd->relocaddr - TOTAL_MALLOC_LEN;
+ entries[n].size = TOTAL_MALLOC_LEN;
+ entries[n].type = E820_RESERVED;
+ n++;
- entries[4].addr = gd->relocaddr;
- entries[4].size = gd->ram_size - gd->relocaddr;
- entries[4].type = E820_RESERVED;
+ entries[n].addr = gd->relocaddr;
+ entries[n].size = qemu_get_low_memory_size() - gd->relocaddr;
+ entries[n].type = E820_RESERVED;
+ n++;
- entries[5].addr = CONFIG_PCIE_ECAM_BASE;
- entries[5].size = CONFIG_PCIE_ECAM_SIZE;
- entries[5].type = E820_RESERVED;
+ entries[n].addr = CONFIG_PCIE_ECAM_BASE;
+ entries[n].size = CONFIG_PCIE_ECAM_SIZE;
+ entries[n].type = E820_RESERVED;
+ n++;
- return 6;
+ high_mem_size = qemu_get_high_memory_size();
+ if (high_mem_size) {
+ entries[n].addr = SZ_4G;
+ entries[n].size = high_mem_size;
+ entries[n].type = E820_RAM;
+ n++;
+ }
+
+ return n;
}
diff --git a/arch/x86/cpu/slimbootloader/Kconfig b/arch/x86/cpu/slimbootloader/Kconfig
new file mode 100644
index 0000000..3ea4c99
--- /dev/null
+++ b/arch/x86/cpu/slimbootloader/Kconfig
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2019 Intel Corporation <www.intel.com>
+
+config SYS_SLIMBOOTLOADER
+ bool
+ select USE_HOB
+ imply SYS_NS16550
+ imply AHCI_PCI
+ imply SCSI
+ imply SCSI_AHCI
+ imply MMC
+ imply MMC_PCI
+ imply MMC_SDHCI
+ imply MMC_SDHCI_SDMA
+ imply USB
+ imply USB_EHCI_HCD
+ imply USB_XHCI_HCD
+ imply E1000
diff --git a/arch/x86/cpu/slimbootloader/Makefile b/arch/x86/cpu/slimbootloader/Makefile
new file mode 100644
index 0000000..aac9fa3
--- /dev/null
+++ b/arch/x86/cpu/slimbootloader/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2019 Intel Corporation <www.intel.com>
+
+obj-y += car.o slimbootloader.o sdram.o serial.o
diff --git a/arch/x86/cpu/slimbootloader/car.S b/arch/x86/cpu/slimbootloader/car.S
new file mode 100644
index 0000000..6e03043
--- /dev/null
+++ b/arch/x86/cpu/slimbootloader/car.S
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#include <generated/asm-offsets.h>
+
+.section .text
+
+.globl car_init
+car_init:
+ /* Get hob pointer parameter from previous stage's stack */
+ mov 0x4(%esp), %esi
+ jmp car_init_ret
diff --git a/arch/x86/cpu/slimbootloader/sdram.c b/arch/x86/cpu/slimbootloader/sdram.c
new file mode 100644
index 0000000..05d40d1
--- /dev/null
+++ b/arch/x86/cpu/slimbootloader/sdram.c
@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#include <common.h>
+#include <linux/sizes.h>
+#include <asm/e820.h>
+#include <asm/arch/slimbootloader.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * This returns a data pointer of memory map info from the guid hob.
+ *
+ * @return: A data pointer of memory map info hob
+ */
+static struct sbl_memory_map_info *get_memory_map_info(void)
+{
+ struct sbl_memory_map_info *data;
+ const efi_guid_t guid = SBL_MEMORY_MAP_INFO_GUID;
+
+ if (!gd->arch.hob_list)
+ return NULL;
+
+ data = hob_get_guid_hob_data(gd->arch.hob_list, NULL, &guid);
+ if (!data)
+ panic("memory map info hob not found\n");
+ if (!data->count)
+ panic("invalid number of memory map entries\n");
+
+ return data;
+}
+
+#define for_each_if(condition) if (!(condition)) {} else
+
+#define for_each_memory_map_entry_reversed(iter, entries) \
+ for (iter = entries->count - 1; iter >= 0; iter--) \
+ for_each_if(entries->entry[iter].type == E820_RAM)
+
+/**
+ * This is to give usable memory region information for u-boot relocation.
+ * so search usable memory region lower than 4GB.
+ * The memory map entries from Slim Bootloader hob are already sorted.
+ *
+ * @total_size: The memory size that u-boot occupies
+ * @return : The top available memory address lower than 4GB
+ */
+ulong board_get_usable_ram_top(ulong total_size)
+{
+ struct sbl_memory_map_info *data;
+ int i;
+ u64 addr_start;
+ u64 addr_end;
+ ulong ram_top;
+
+ data = get_memory_map_info();
+
+ /**
+ * sorted memory map entries from Slim Bootloader based on physical
+ * start memory address, from low to high. So do reversed search to
+ * get highest usable, suitable size, 4KB aligned available memory
+ * under 4GB.
+ */
+ ram_top = 0;
+ for_each_memory_map_entry_reversed(i, data) {
+ addr_start = data->entry[i].addr;
+ addr_end = addr_start + data->entry[i].size;
+
+ if (addr_start > SZ_4G)
+ continue;
+
+ if (addr_end > SZ_4G)
+ addr_end = SZ_4G;
+
+ if (addr_end < total_size)
+ continue;
+
+ /* to relocate u-boot at 4K aligned memory */
+ addr_end = rounddown(addr_end - total_size, SZ_4K);
+ if (addr_end >= addr_start) {
+ ram_top = (ulong)addr_end + total_size;
+ break;
+ }
+ }
+
+ if (!ram_top)
+ panic("failed to find available memory for relocation!");
+
+ return ram_top;
+}
+
+/**
+ * The memory initialization has already been done in previous Slim Bootloader
+ * stage thru FSP-M. Instead, this sets the ram_size from the memory map info
+ * hob.
+ */
+int dram_init(void)
+{
+ struct sbl_memory_map_info *data;
+ int i;
+ u64 ram_size;
+
+ data = get_memory_map_info();
+
+ /**
+ * sorted memory map entries from Slim Bootloader based on physical
+ * start memory address, from low to high. So do reversed search to
+ * simply get highest usable memory address as RAM size
+ */
+ ram_size = 0;
+ for_each_memory_map_entry_reversed(i, data) {
+ /* simply use the highest usable memory address as RAM size */
+ ram_size = data->entry[i].addr + data->entry[i].size;
+ break;
+ }
+
+ if (!ram_size)
+ panic("failed to detect memory size");
+
+ gd->ram_size = ram_size;
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ if (!CONFIG_NR_DRAM_BANKS)
+ return 0;
+
+ /* simply use a single bank to have whole size for now */
+ gd->bd->bi_dram[0].start = 0;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+ return 0;
+}
+
+unsigned int install_e820_map(unsigned int max_entries,
+ struct e820_entry *entries)
+{
+ struct sbl_memory_map_info *data;
+ unsigned int i;
+
+ data = get_memory_map_info();
+
+ for (i = 0; i < data->count; i++) {
+ entries[i].addr = data->entry[i].addr;
+ entries[i].size = data->entry[i].size;
+ entries[i].type = data->entry[i].type;
+ }
+
+ return i;
+}
diff --git a/arch/x86/cpu/slimbootloader/serial.c b/arch/x86/cpu/slimbootloader/serial.c
new file mode 100644
index 0000000..7b44a59
--- /dev/null
+++ b/arch/x86/cpu/slimbootloader/serial.c
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <ns16550.h>
+#include <serial.h>
+#include <asm/arch/slimbootloader.h>
+
+/**
+ * The serial port info hob is generated by Slim Bootloader, so eligible for
+ * Slim Bootloader based boards only.
+ */
+static int slimbootloader_serial_ofdata_to_platdata(struct udevice *dev)
+{
+ const efi_guid_t guid = SBL_SERIAL_PORT_INFO_GUID;
+ struct sbl_serial_port_info *data;
+ struct ns16550_platdata *plat = dev->platdata;
+
+ if (!gd->arch.hob_list)
+ panic("hob list not found!");
+
+ data = hob_get_guid_hob_data(gd->arch.hob_list, NULL, &guid);
+ if (!data) {
+ debug("failed to get serial port information\n");
+ return -ENOENT;
+ }
+ debug("type:%d base=0x%08x baudrate=%d stride=%d clk=%d\n",
+ data->type,
+ data->base,
+ data->baud,
+ data->stride,
+ data->clk);
+
+ /*
+ * The data->type provides port io or mmio access type info,
+ * but the access type will be controlled by
+ * CONFIG_SYS_NS16550_PORT_MAPPED or CONFIG_SYS_NS16550_MEM32.
+ *
+ * TBD: ns16550 access type configuration in runtime.
+ * ex) plat->access_type = data->type
+ */
+ plat->base = data->base;
+ /* ns16550 uses reg_shift, then covert stride to shift */
+ plat->reg_shift = data->stride >> 1;
+ plat->clock = data->clk;
+
+ return 0;
+}
+
+static const struct udevice_id slimbootloader_serial_ids[] = {
+ { .compatible = "intel,slimbootloader-uart" },
+ {}
+};
+
+U_BOOT_DRIVER(serial_slimbootloader) = {
+ .name = "serial_slimbootloader",
+ .id = UCLASS_SERIAL,
+ .of_match = slimbootloader_serial_ids,
+ .ofdata_to_platdata = slimbootloader_serial_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
+ .priv_auto_alloc_size = sizeof(struct NS16550),
+ .probe = ns16550_serial_probe,
+ .ops = &ns16550_serial_ops,
+};
diff --git a/arch/x86/cpu/slimbootloader/slimbootloader.c b/arch/x86/cpu/slimbootloader/slimbootloader.c
new file mode 100644
index 0000000..e6b174c
--- /dev/null
+++ b/arch/x86/cpu/slimbootloader/slimbootloader.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#include <common.h>
+#include <asm/arch/slimbootloader.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * This sets tsc_base and clock_rate for early_timer and tsc_timer.
+ * The performance info guid hob has all performance timestamp data, but
+ * the only tsc frequency info is used for the timer driver for now.
+ *
+ * Slim Bootloader already calibrated TSC and provides it to U-Boot.
+ * Therefore, U-Boot does not have to re-calibrate TSC.
+ * Configuring tsc_base and clock_rate here makes x86 tsc_timer driver
+ * bypass TSC calibration and use the provided TSC frequency.
+ */
+static void tsc_init(void)
+{
+ struct sbl_performance_info *data;
+ const efi_guid_t guid = SBL_PERFORMANCE_INFO_GUID;
+
+ if (!gd->arch.hob_list)
+ panic("hob list not found!");
+
+ gd->arch.tsc_base = rdtsc();
+ debug("tsc_base=0x%llx\n", gd->arch.tsc_base);
+
+ data = hob_get_guid_hob_data(gd->arch.hob_list, NULL, &guid);
+ if (!data) {
+ debug("performance info hob not found\n");
+ return;
+ }
+
+ /* frequency is in KHz, so to Hz */
+ gd->arch.clock_rate = data->frequency * 1000;
+ debug("freq=0x%lx\n", gd->arch.clock_rate);
+}
+
+int arch_cpu_init(void)
+{
+ tsc_init();
+
+ return x86_cpu_init_f();
+}
+
+int checkcpu(void)
+{
+ return 0;
+}
+
+int print_cpuinfo(void)
+{
+ return default_print_cpuinfo();
+}
diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S
index 4a82add..3c9bdf2 100644
--- a/arch/x86/cpu/start.S
+++ b/arch/x86/cpu/start.S
@@ -40,9 +40,6 @@
movl %eax, %cr0
wbinvd
- /* Tell 32-bit code it is being entered from an in-RAM copy */
- movl $GD_FLG_WARM_BOOT, %ebx
-
/*
* Zero the BIST (Built-In Self Test) value since we don't have it.
* It must be 0 or the previous loader would have reported an error.
@@ -55,11 +52,7 @@
.align 4
.long 0x12345678
_start:
- /*
- * This is the 32-bit cold-reset entry point, coming from start16.
- * Set %ebx to GD_FLG_COLD_BOOT to indicate this.
- */
- movl $GD_FLG_COLD_BOOT, %ebx
+ /* This is the 32-bit cold-reset entry point, coming from start16 */
/* Save BIST */
movl %eax, %ebp
@@ -97,7 +90,7 @@
jmp car_init
.globl car_init_ret
car_init_ret:
-#ifndef CONFIG_HAVE_FSP
+#ifndef CONFIG_USE_HOB
/*
* We now have CONFIG_SYS_CAR_SIZE bytes of Cache-As-RAM (or SRAM,
* or fully initialised SDRAM - we really don't care which)
@@ -137,12 +130,13 @@
/* Get address of global_data */
mov %fs:0, %edx
-#ifdef CONFIG_HAVE_FSP
+#ifdef CONFIG_USE_HOB
/* Store the HOB list if we have one */
test %esi, %esi
jz skip_hob
movl %esi, GD_HOB_LIST(%edx)
+#ifdef CONFIG_HAVE_FSP
/*
* After fsp_init() returns, the stack has already been switched to a
* place within system memory as defined by CONFIG_FSP_TEMP_RAM_ADDR.
@@ -151,6 +145,7 @@
*/
subl $CONFIG_FSP_SYS_MALLOC_F_LEN, %esp
movl %esp, GD_MALLOC_BASE(%edx)
+#endif
skip_hob:
#else
/* Store table pointer */
diff --git a/arch/x86/cpu/start16.S b/arch/x86/cpu/start16.S
index dd65927..474efe4 100644
--- a/arch/x86/cpu/start16.S
+++ b/arch/x86/cpu/start16.S
@@ -23,9 +23,6 @@
/* Save BIST */
movl %eax, %ecx
- /* Set the Cold Boot / Hard Reset flag */
- movl $GD_FLG_COLD_BOOT, %ebx
-
xorl %eax, %eax
movl %eax, %cr3 /* Invalidate TLB */
diff --git a/arch/x86/cpu/tangier/acpi.c b/arch/x86/cpu/tangier/acpi.c
index 0e4f961..8b12813 100644
--- a/arch/x86/cpu/tangier/acpi.c
+++ b/arch/x86/cpu/tangier/acpi.c
@@ -14,6 +14,7 @@
#include <asm/mpspec.h>
#include <asm/tables.h>
#include <asm/arch/global_nvs.h>
+#include <asm/arch/iomap.h>
void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
void *dsdt)
@@ -63,7 +64,45 @@
/* TODO: Derive parameters from SFI MCFG table */
current += acpi_create_mcfg_mmconfig
((struct acpi_mcfg_mmconfig *)current,
- 0x3f500000, 0x0, 0x0, 0x0);
+ MCFG_BASE_ADDRESS, 0x0, 0x0, 0x0);
+
+ return current;
+}
+
+static u32 acpi_fill_csrt_dma(struct acpi_csrt_group *grp)
+{
+ struct acpi_csrt_shared_info *si = (struct acpi_csrt_shared_info *)&grp[1];
+
+ /* Fill the Resource Group with Shared Information attached */
+ memset(grp, 0, sizeof(*grp));
+ grp->shared_info_length = sizeof(struct acpi_csrt_shared_info);
+ grp->length = sizeof(struct acpi_csrt_group) + grp->shared_info_length;
+ /* TODO: All values below should come from U-Boot DT somehow */
+ sprintf((char *)&grp->vendor_id, "%04X", 0x8086);
+ grp->device_id = 0x11a2;
+
+ /* Fill the Resource Group Shared Information */
+ memset(si, 0, sizeof(*si));
+ si->major_version = 1;
+ si->minor_version = 0;
+ /* TODO: All values below should come from U-Boot DT somehow */
+ si->mmio_base_low = 0xff192000;
+ si->mmio_base_high = 0;
+ si->gsi_interrupt = 32;
+ si->interrupt_polarity = 1;
+ si->interrupt_mode = 0;
+ si->num_channels = 8;
+ si->dma_address_width = 32;
+ si->base_request_line = 0;
+ si->num_handshake_signals = 16;
+ si->max_block_size = 0x1ffff;
+
+ return grp->length;
+}
+
+u32 acpi_fill_csrt(u32 current)
+{
+ current += acpi_fill_csrt_dma((struct acpi_csrt_group *)current);
return current;
}
diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
index 8fe1a69..deb82cf 100644
--- a/arch/x86/dts/Makefile
+++ b/arch/x86/dts/Makefile
@@ -19,6 +19,7 @@
qemu-x86_i440fx.dtb \
qemu-x86_q35.dtb \
theadorable-x86-dfi-bt700.dtb \
+ slimbootloader.dtb \
baytrail_som-db5800-som-6867.dtb
targets += $(dtb-y)
diff --git a/arch/x86/dts/edison.dts b/arch/x86/dts/edison.dts
index c048765..df24aa0 100644
--- a/arch/x86/dts/edison.dts
+++ b/arch/x86/dts/edison.dts
@@ -84,15 +84,10 @@
reg = <0xff3fc000 0x1000>;
};
-/*
- * FIXME: For now U-Boot DM model doesn't allow to power up this controller.
- * Enabling it will make U-Boot hang.
- *
sdcard: mmc@ff3fa000 {
compatible = "intel,sdhci-tangier";
reg = <0xff3fa000 0x1000>;
};
- */
pmu: power@ff00b000 {
compatible = "intel,pmu-mid";
diff --git a/arch/x86/dts/slimbootloader.dts b/arch/x86/dts/slimbootloader.dts
new file mode 100644
index 0000000..d04095c
--- /dev/null
+++ b/arch/x86/dts/slimbootloader.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+/include/ "reset.dtsi"
+/include/ "tsc_timer.dtsi"
+
+/ {
+ model = "slimbootloader x86 payload";
+ compatible = "slimbootloader,x86-payload";
+
+ chosen {
+ stdout-path = &serial;
+ };
+
+ serial: serial {
+ compatible = "intel,slimbootloader-uart";
+ };
+
+ pci {
+ compatible = "pci-x86";
+ };
+};
diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h
index e3b65cf..7588913 100644
--- a/arch/x86/include/asm/acpi_table.h
+++ b/arch/x86/include/asm/acpi_table.h
@@ -34,7 +34,7 @@
};
/* Generic ACPI header, provided by (almost) all tables */
-struct acpi_table_header {
+struct __packed acpi_table_header {
char signature[4]; /* ACPI signature (4 ASCII characters) */
u32 length; /* Table length in bytes (incl. header) */
u8 revision; /* Table version (not ACPI version!) */
@@ -303,6 +303,37 @@
/* ACPI global NVS structure */
struct acpi_global_nvs;
+/* CSRT (Core System Resource Table) */
+struct acpi_csrt {
+ struct acpi_table_header header;
+};
+
+struct acpi_csrt_group {
+ u32 length;
+ u32 vendor_id;
+ u32 subvendor_id;
+ u16 device_id;
+ u16 subdevice_id;
+ u16 revision;
+ u16 reserved;
+ u32 shared_info_length;
+};
+
+struct acpi_csrt_shared_info {
+ u16 major_version;
+ u16 minor_version;
+ u32 mmio_base_low;
+ u32 mmio_base_high;
+ u32 gsi_interrupt;
+ u8 interrupt_polarity;
+ u8 interrupt_mode;
+ u8 num_channels;
+ u8 dma_address_width;
+ u16 base_request_line;
+ u16 num_handshake_signals;
+ u32 max_block_size;
+};
+
/* DBG2 definitions are partially used for SPCR interface_type */
/* Types for port_type field */
@@ -370,6 +401,7 @@
int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig, u32 base,
u16 seg_nr, u8 start, u8 end);
u32 acpi_fill_mcfg(u32 current);
+u32 acpi_fill_csrt(u32 current);
void acpi_create_gnvs(struct acpi_global_nvs *gnvs);
ulong write_acpi_tables(ulong start);
diff --git a/arch/x86/include/asm/arch-qemu/qemu.h b/arch/x86/include/asm/arch-qemu/qemu.h
index 100eb8e..061735b 100644
--- a/arch/x86/include/asm/arch-qemu/qemu.h
+++ b/arch/x86/include/asm/arch-qemu/qemu.h
@@ -32,9 +32,27 @@
#define LOW_RAM_ADDR 0x34
#define HIGH_RAM_ADDR 0x35
+#define LOW_HIGHRAM_ADDR 0x5b
+#define MID_HIGHRAM_ADDR 0x5c
+#define HIGH_HIGHRAM_ADDR 0x5d
+
/* PM registers */
#define PMBA 0x40
#define PMREGMISC 0x80
#define PMIOSE (1 << 0)
+/**
+ * qemu_get_low_memory_size() - Get low memory size
+ *
+ * @return: size of memory below 4GiB
+ */
+u32 qemu_get_low_memory_size(void);
+
+/**
+ * qemu_get_high_memory_size() - Get high memory size
+ *
+ * @return: size of memory above 4GiB
+ */
+u64 qemu_get_high_memory_size(void);
+
#endif /* _ARCH_QEMU_H_ */
diff --git a/arch/x86/include/asm/arch-slimbootloader/slimbootloader.h b/arch/x86/include/asm/arch-slimbootloader/slimbootloader.h
new file mode 100644
index 0000000..05dd1b2
--- /dev/null
+++ b/arch/x86/include/asm/arch-slimbootloader/slimbootloader.h
@@ -0,0 +1,115 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#ifndef __SLIMBOOTLOADER_ARCH_H__
+#define __SLIMBOOTLOADER_ARCH_H__
+
+#include <common.h>
+#include <asm/hob.h>
+
+/**
+ * A GUID to get MemoryMap info hob which is provided by Slim Bootloader
+ */
+#define SBL_MEMORY_MAP_INFO_GUID \
+ EFI_GUID(0xa1ff7424, 0x7a1a, 0x478e, \
+ 0xa9, 0xe4, 0x92, 0xf3, 0x57, 0xd1, 0x28, 0x32)
+
+/**
+ * A GUID to get SerialPort info hob which is provided by Slim Bootloader
+ */
+#define SBL_SERIAL_PORT_INFO_GUID \
+ EFI_GUID(0x6c6872fe, 0x56a9, 0x4403, \
+ 0xbb, 0x98, 0x95, 0x8d, 0x62, 0xde, 0x87, 0xf1)
+
+/**
+ * A GUID to get boot performance info hob which is provided by Slim Bootloader
+ */
+#define SBL_PERFORMANCE_INFO_GUID \
+ EFI_GUID(0x868204be, 0x23d0, 0x4ff9, \
+ 0xac, 0x34, 0xb9, 0x95, 0xac, 0x04, 0xb1, 0xb9)
+
+/**
+ * A single entry of memory map information
+ *
+ * @addr: start address of a memory map entry
+ * @size: size of a memory map entry
+ * @type: usable:1, reserved:2, acpi:3, nvs:4, unusable:5
+ * @flag: only used in Slim Bootloader
+ * @rsvd: padding for alignment
+ */
+struct sbl_memory_map_entry {
+ u64 addr;
+ u64 size;
+ u8 type;
+ u8 flag;
+ u8 rsvd[6];
+};
+
+/**
+ * This includes all memory map entries which is sorted based on physical start
+ * address, from low to high, and carved out reserved, acpi nvs, acpi reclaim
+ * and usable memory.
+ *
+ * @rev : revision of memory_map_info structure. currently 1.
+ * @rsvd : padding for alignment
+ * @count: the number of memory map entries
+ * @entry: array of all memory map entries
+ */
+struct sbl_memory_map_info {
+ u8 rev;
+ u8 rsvd[3];
+ u32 count;
+ struct sbl_memory_map_entry entry[0];
+};
+
+/**
+ * This includes serial port info which has already been initialized in previous
+ * Slim Bootloader stage.
+ * The Slim Bootloader initializes serial port regardless of debug/release build
+ * modes, and it passes the information to a payload thru hob. So, a payload can
+ * re-use the serial information without re-initializing serial port.
+ *
+ * @rev : revision of serial_port_info structure. currently 1.
+ * @rsvd : padding for alignment
+ * @type : port io: 1, mmio: 2
+ * @base : io base address. ex) 0x3f8, 0x80001000
+ * @baud : uart baud rate
+ * @stride: register stride in Bytes
+ * @clk : uart frequency in Hz
+ * @rsvd1 : reserved
+ */
+struct sbl_serial_port_info {
+ u8 rev;
+ u8 rsvd[3];
+ u32 type;
+ u32 base;
+ u32 baud;
+ u32 stride;
+ u32 clk;
+ u32 rsvd1;
+};
+
+/**
+ * This includes timestamp data which has been collected in Slim Bootloader
+ * stages from the reset vector. In addition, this has TSC frequency in KHz to
+ * calculate each timestamp.
+ *
+ * @rev : revision of performance_info structure. currently 1.
+ * @rsvd : padding for alignment
+ * @count : the number of collected timestamp data
+ * @flags : only used in Slim Bootloader
+ * @frequency: tsc frequency in KHz
+ * @timestamp: the array of timestamp data which has 64-bit tsc value
+ */
+struct sbl_performance_info {
+ u8 rev;
+ u8 rsvd[3];
+ u16 count;
+ u16 flags;
+ u32 frequency;
+ u64 timestamp[0];
+};
+
+#endif /* __SLIMBOOTLOADER_ARCH_H__ */
diff --git a/arch/x86/include/asm/arch-tangier/acpi/platform.asl b/arch/x86/include/asm/arch-tangier/acpi/platform.asl
index 353b879..cf75ca7 100644
--- a/arch/x86/include/asm/arch-tangier/acpi/platform.asl
+++ b/arch/x86/include/asm/arch-tangier/acpi/platform.asl
@@ -6,6 +6,7 @@
*/
#include <asm/acpi/statdef.asl>
+#include <asm/arch/iomap.h>
/*
* The _PTS method (Prepare To Sleep) is called before the OS is
@@ -18,7 +19,7 @@
/* The _WAK method is called on system wakeup */
Method(_WAK, 1)
{
- Return (Package() {0, 0})
+ Return (Package() { Zero, Zero })
}
Scope (_SB)
diff --git a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl
index 8b5b709..c622783 100644
--- a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl
+++ b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl
@@ -10,8 +10,8 @@
Name (_HID, EISAID("PNP0A08")) /* PCIe */
Name (_CID, EISAID("PNP0A03")) /* PCI */
- Name (_ADR, 0)
- Name (_BBN, 0)
+ Name (_ADR, Zero)
+ Name (_BBN, Zero)
Name (MCRS, ResourceTemplate()
{
@@ -66,6 +66,23 @@
Return (MCRS)
}
+ /* Device Resource Consumption */
+ Device (PDRC)
+ {
+ Name (_HID, EISAID("PNP0C02"))
+ Name (_UID, One)
+
+ Name (PDRS, ResourceTemplate()
+ {
+ Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE)
+ })
+
+ Method (_CRS, 0, Serialized)
+ {
+ Return (PDRS)
+ }
+ }
+
Method (_OSC, 4)
{
/* Check for proper GUID */
@@ -365,19 +382,19 @@
Name (RBUF, ResourceTemplate()
{
/*
- * Shadow registers in SRAM for PMIC:
- * SRAM PMIC register
- * --------------------
- * 0x00- Unknown
- * 0x03 THRMIRQ (0x04)
- * 0x04 BCUIRQ (0x05)
- * 0x05 ADCIRQ (0x06)
- * 0x06 CHGRIRQ0 (0x07)
- * 0x07 CHGRIRQ1 (0x08)
- * 0x08- Unknown
- * 0x0a PBSTATUS (0x27)
- * 0x0b- Unknown
- */
+ * Shadow registers in SRAM for PMIC:
+ * SRAM PMIC register
+ * --------------------
+ * 0x00- Unknown
+ * 0x03 THRMIRQ (0x04)
+ * 0x04 BCUIRQ (0x05)
+ * 0x05 ADCIRQ (0x06)
+ * 0x06 CHGRIRQ0 (0x07)
+ * 0x07 CHGRIRQ1 (0x08)
+ * 0x08- Unknown
+ * 0x0a PBSTATUS (0x27)
+ * 0x0b- Unknown
+ */
Memory32Fixed(ReadWrite, 0xFFFFF610, 0x00000010)
Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 30 }
Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 23 }
@@ -421,6 +438,28 @@
}
}
}
+
+ Device (GDMA)
+ {
+ Name (_ADR, 0x00150000)
+ Name (_HID, "808611A2")
+ Name (_UID, Zero)
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (STA_VISIBLE)
+ }
+
+ Method (_CRS, 0, Serialized)
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed(ReadWrite, 0xFF192000, 0x00001000)
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 32 }
+ })
+ Return (RBUF)
+ }
+ }
}
Device (FLIS)
diff --git a/arch/x86/include/asm/arch-tangier/iomap.h b/arch/x86/include/asm/arch-tangier/iomap.h
new file mode 100644
index 0000000..b0fc03e
--- /dev/null
+++ b/arch/x86/include/asm/arch-tangier/iomap.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/* Copyright (c) 2019 Intel Corporation */
+
+#ifndef _TANGIER_IOMAP_H
+#define _TANGIER_IOMAP_H
+
+#define MCFG_BASE_ADDRESS 0x3f500000
+#define MCFG_BASE_SIZE 0x00100000
+
+#endif /* _TANGIER_IOMAP_H */
diff --git a/arch/x86/include/asm/bootparam.h b/arch/x86/include/asm/bootparam.h
index dfbd4b4..d961ddd 100644
--- a/arch/x86/include/asm/bootparam.h
+++ b/arch/x86/include/asm/bootparam.h
@@ -94,7 +94,8 @@
__u8 _pad2[4]; /* 0x054 */
__u64 tboot_addr; /* 0x058 */
struct ist_info ist_info; /* 0x060 */
- __u8 _pad3[16]; /* 0x070 */
+ __u64 acpi_rsdp_addr; /* 0x070 */
+ __u8 _pad3[8]; /* 0x078 */
__u8 hd0_info[16]; /* obsolete! */ /* 0x080 */
__u8 hd1_info[16]; /* obsolete! */ /* 0x090 */
struct sys_desc_table sys_desc_table; /* 0x0a0 */
diff --git a/arch/x86/include/asm/coreboot_tables.h b/arch/x86/include/asm/coreboot_tables.h
index c42175b..2c54e24 100644
--- a/arch/x86/include/asm/coreboot_tables.h
+++ b/arch/x86/include/asm/coreboot_tables.h
@@ -8,6 +8,8 @@
#ifndef _COREBOOT_TABLES_H
#define _COREBOOT_TABLES_H
+struct memory_area;
+
struct cbuint64 {
u32 lo;
u32 hi;
diff --git a/arch/x86/include/asm/fsp/fsp_ffs.h b/arch/x86/include/asm/fsp/fsp_ffs.h
index 61ce63c..b7558e5 100644
--- a/arch/x86/include/asm/fsp/fsp_ffs.h
+++ b/arch/x86/include/asm/fsp/fsp_ffs.h
@@ -45,7 +45,7 @@
* This GUID is the file name.
* It is used to uniquely identify the file.
*/
- struct efi_guid name;
+ efi_guid_t name;
/* Used to verify the integrity of the file */
union ffs_integrity integrity;
/* Identifies the type of file */
@@ -68,7 +68,7 @@
* Name in any given firmware volume, except if the file type is
* EFI_FV_FILE_TYPE_FFS_PAD.
*/
- struct efi_guid name;
+ efi_guid_t name;
/* Used to verify the integrity of the file */
union ffs_integrity integrity;
/* Identifies the type of file */
diff --git a/arch/x86/include/asm/fsp/fsp_fv.h b/arch/x86/include/asm/fsp/fsp_fv.h
index 190aedc..511dfb7 100644
--- a/arch/x86/include/asm/fsp/fsp_fv.h
+++ b/arch/x86/include/asm/fsp/fsp_fv.h
@@ -80,7 +80,7 @@
* Declares the file system with which the firmware volume
* is formatted.
*/
- struct efi_guid fs_guid;
+ efi_guid_t fs_guid;
/*
* Length in bytes of the complete firmware volume, including
* the header.
@@ -128,7 +128,7 @@
/* Extension header pointed by ExtHeaderOffset of volume header */
struct fv_ext_header {
/* firmware volume name */
- struct efi_guid fv_name;
+ efi_guid_t fv_name;
/* Size of the rest of the extension header including this structure */
u32 ext_hdr_size;
};
diff --git a/arch/x86/include/asm/fsp/fsp_hob.h b/arch/x86/include/asm/fsp/fsp_hob.h
index 00657b6..3bb79c4 100644
--- a/arch/x86/include/asm/fsp/fsp_hob.h
+++ b/arch/x86/include/asm/fsp/fsp_hob.h
@@ -7,124 +7,7 @@
#ifndef __FSP_HOB_H__
#define __FSP_HOB_H__
-#include <efi.h>
-
-/* Type of HOB Header */
-#define HOB_TYPE_MEM_ALLOC 0x0002
-#define HOB_TYPE_RES_DESC 0x0003
-#define HOB_TYPE_GUID_EXT 0x0004
-#define HOB_TYPE_UNUSED 0xFFFE
-#define HOB_TYPE_EOH 0xFFFF
-
-/*
- * Describes the format and size of the data inside the HOB.
- * All HOBs must contain this generic HOB header.
- */
-struct hob_header {
- u16 type; /* HOB type */
- u16 len; /* HOB length */
- u32 reserved; /* always zero */
-};
-
-/*
- * Describes all memory ranges used during the HOB producer phase that
- * exist outside the HOB list. This HOB type describes how memory is used,
- * not the physical attributes of memory.
- */
-struct hob_mem_alloc {
- struct hob_header hdr;
- /*
- * A GUID that defines the memory allocation region's type and purpose,
- * as well as other fields within the memory allocation HOB. This GUID
- * is used to define the additional data within the HOB that may be
- * present for the memory allocation HOB. Type efi_guid is defined in
- * InstallProtocolInterface() in the UEFI 2.0 specification.
- */
- struct efi_guid name;
- /*
- * The base address of memory allocated by this HOB.
- * Type phys_addr_t is defined in AllocatePages() in the UEFI 2.0
- * specification.
- */
- phys_addr_t mem_base;
- /* The length in bytes of memory allocated by this HOB */
- phys_size_t mem_len;
- /*
- * Defines the type of memory allocated by this HOB.
- * The memory type definition follows the EFI_MEMORY_TYPE definition.
- * Type EFI_MEMORY_TYPE is defined in AllocatePages() in the UEFI 2.0
- * specification.
- */
- enum efi_mem_type mem_type;
- /* padding */
- u8 reserved[4];
-};
-
-/* Value of ResourceType in HOB_RES_DESC */
-#define RES_SYS_MEM 0x00000000
-#define RES_MMAP_IO 0x00000001
-#define RES_IO 0x00000002
-#define RES_FW_DEVICE 0x00000003
-#define RES_MMAP_IO_PORT 0x00000004
-#define RES_MEM_RESERVED 0x00000005
-#define RES_IO_RESERVED 0x00000006
-#define RES_MAX_MEM_TYPE 0x00000007
-
-/*
- * These types can be ORed together as needed.
- *
- * The first three enumerations describe settings
- * The rest of the settings describe capabilities
- */
-#define RES_ATTR_PRESENT 0x00000001
-#define RES_ATTR_INITIALIZED 0x00000002
-#define RES_ATTR_TESTED 0x00000004
-#define RES_ATTR_SINGLE_BIT_ECC 0x00000008
-#define RES_ATTR_MULTIPLE_BIT_ECC 0x00000010
-#define RES_ATTR_ECC_RESERVED_1 0x00000020
-#define RES_ATTR_ECC_RESERVED_2 0x00000040
-#define RES_ATTR_READ_PROTECTED 0x00000080
-#define RES_ATTR_WRITE_PROTECTED 0x00000100
-#define RES_ATTR_EXECUTION_PROTECTED 0x00000200
-#define RES_ATTR_UNCACHEABLE 0x00000400
-#define RES_ATTR_WRITE_COMBINEABLE 0x00000800
-#define RES_ATTR_WRITE_THROUGH_CACHEABLE 0x00001000
-#define RES_ATTR_WRITE_BACK_CACHEABLE 0x00002000
-#define RES_ATTR_16_BIT_IO 0x00004000
-#define RES_ATTR_32_BIT_IO 0x00008000
-#define RES_ATTR_64_BIT_IO 0x00010000
-#define RES_ATTR_UNCACHED_EXPORTED 0x00020000
-
-/*
- * Describes the resource properties of all fixed, nonrelocatable resource
- * ranges found on the processor host bus during the HOB producer phase.
- */
-struct hob_res_desc {
- struct hob_header hdr;
- /*
- * A GUID representing the owner of the resource. This GUID is
- * used by HOB consumer phase components to correlate device
- * ownership of a resource.
- */
- struct efi_guid owner;
- u32 type;
- u32 attr;
- /* The physical start address of the resource region */
- phys_addr_t phys_start;
- /* The number of bytes of the resource region */
- phys_size_t len;
-};
-
-/*
- * Allows writers of executable content in the HOB producer phase to
- * maintain and manage HOBs with specific GUID.
- */
-struct hob_guid {
- struct hob_header hdr;
- /* A GUID that defines the contents of this HOB */
- struct efi_guid name;
- /* GUID specific data goes here */
-};
+#include <asm/hob.h>
enum pixel_format {
pixel_rgbx_8bpc, /* RGB 8 bit per color */
@@ -146,70 +29,6 @@
u32 pixels_per_scanline;
};
-/**
- * get_next_hob() - return a pointer to the next HOB in the HOB list
- *
- * This macro returns a pointer to HOB that follows the HOB specified by hob
- * in the HOB List.
- *
- * @hdr: A pointer to a HOB.
- *
- * @return: A pointer to the next HOB in the HOB list.
- */
-static inline const struct hob_header *get_next_hob(const struct hob_header *hdr)
-{
- return (const struct hob_header *)((uintptr_t)hdr + hdr->len);
-}
-
-/**
- * end_of_hob() - determine if a HOB is the last HOB in the HOB list
- *
- * This macro determine if the HOB specified by hob is the last HOB in the
- * HOB list. If hob is last HOB in the HOB list, then true is returned.
- * Otherwise, false is returned.
- *
- * @hdr: A pointer to a HOB.
- *
- * @retval true: The HOB specified by hdr is the last HOB in the HOB list.
- * @retval false: The HOB specified by hdr is not the last HOB in the HOB list.
- */
-static inline bool end_of_hob(const struct hob_header *hdr)
-{
- return hdr->type == HOB_TYPE_EOH;
-}
-
-/**
- * get_guid_hob_data() - return a pointer to data buffer from a HOB of
- * type HOB_TYPE_GUID_EXT
- *
- * This macro returns a pointer to the data buffer in a HOB specified by hob.
- * hob is assumed to be a HOB of type HOB_TYPE_GUID_EXT.
- *
- * @hdr: A pointer to a HOB.
- *
- * @return: A pointer to the data buffer in a HOB.
- */
-static inline void *get_guid_hob_data(const struct hob_header *hdr)
-{
- return (void *)((uintptr_t)hdr + sizeof(struct hob_guid));
-}
-
-/**
- * get_guid_hob_data_size() - return the size of the data buffer from a HOB
- * of type HOB_TYPE_GUID_EXT
- *
- * This macro returns the size, in bytes, of the data buffer in a HOB
- * specified by hob. hob is assumed to be a HOB of type HOB_TYPE_GUID_EXT.
- *
- * @hdr: A pointer to a HOB.
- *
- * @return: The size of the data buffer.
- */
-static inline u16 get_guid_hob_data_size(const struct hob_header *hdr)
-{
- return hdr->len - sizeof(struct hob_guid);
-}
-
/* FSP specific GUID HOB definitions */
#define FSP_GUID_DATA1 0x912740be
#define FSP_GUID_DATA2 0x2284
@@ -223,56 +42,57 @@
#define FSP_GUID_DATA4_6 0x3f
#define FSP_GUID_DATA4_7 0x0c
+#define FSP_GUID_BYTE0 0xbe
+#define FSP_GUID_BYTE1 0x40
+#define FSP_GUID_BYTE2 0x27
+#define FSP_GUID_BYTE3 0x91
+#define FSP_GUID_BYTE4 0x84
+#define FSP_GUID_BYTE5 0x22
+#define FSP_GUID_BYTE6 0x34
+#define FSP_GUID_BYTE7 0x47
+#define FSP_GUID_BYTE8 FSP_GUID_DATA4_0
+#define FSP_GUID_BYTE9 FSP_GUID_DATA4_1
+#define FSP_GUID_BYTE10 FSP_GUID_DATA4_2
+#define FSP_GUID_BYTE11 FSP_GUID_DATA4_3
+#define FSP_GUID_BYTE12 FSP_GUID_DATA4_4
+#define FSP_GUID_BYTE13 FSP_GUID_DATA4_5
+#define FSP_GUID_BYTE14 FSP_GUID_DATA4_6
+#define FSP_GUID_BYTE15 FSP_GUID_DATA4_7
+
#define FSP_HEADER_GUID \
- { \
- FSP_GUID_DATA1, FSP_GUID_DATA2, FSP_GUID_DATA3, \
- { FSP_GUID_DATA4_0, FSP_GUID_DATA4_1, FSP_GUID_DATA4_2, \
- FSP_GUID_DATA4_3, FSP_GUID_DATA4_4, FSP_GUID_DATA4_5, \
- FSP_GUID_DATA4_6, FSP_GUID_DATA4_7 } \
- }
+ EFI_GUID(FSP_GUID_DATA1, FSP_GUID_DATA2, FSP_GUID_DATA3, \
+ FSP_GUID_DATA4_0, FSP_GUID_DATA4_1, FSP_GUID_DATA4_2, \
+ FSP_GUID_DATA4_3, FSP_GUID_DATA4_4, FSP_GUID_DATA4_5, \
+ FSP_GUID_DATA4_6, FSP_GUID_DATA4_7)
#define FSP_NON_VOLATILE_STORAGE_HOB_GUID \
- { \
- 0x721acf02, 0x4d77, 0x4c2a, \
- { 0xb3, 0xdc, 0x27, 0xb, 0x7b, 0xa9, 0xe4, 0xb0 } \
- }
+ EFI_GUID(0x721acf02, 0x4d77, 0x4c2a, \
+ 0xb3, 0xdc, 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0)
#define FSP_BOOTLOADER_TEMP_MEM_HOB_GUID \
- { \
- 0xbbcff46c, 0xc8d3, 0x4113, \
- { 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e } \
- }
+ EFI_GUID(0xbbcff46c, 0xc8d3, 0x4113, \
+ 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e)
#define FSP_HOB_RESOURCE_OWNER_FSP_GUID \
- { \
- 0x69a79759, 0x1373, 0x4367, \
- { 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e } \
- }
+ EFI_GUID(0x69a79759, 0x1373, 0x4367, \
+ 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e)
#define FSP_HOB_RESOURCE_OWNER_TSEG_GUID \
- { \
- 0xd038747c, 0xd00c, 0x4980, \
- { 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55 } \
- }
+ EFI_GUID(0xd038747c, 0xd00c, 0x4980, \
+ 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55)
#define FSP_HOB_RESOURCE_OWNER_GRAPHICS_GUID \
- { \
- 0x9c7c3aa7, 0x5332, 0x4917, \
- { 0x82, 0xb9, 0x56, 0xa5, 0xf3, 0xe6, 0x2a, 0x07 } \
- }
+ EFI_GUID(0x9c7c3aa7, 0x5332, 0x4917, \
+ 0x82, 0xb9, 0x56, 0xa5, 0xf3, 0xe6, 0x2a, 0x07)
/* The following GUIDs are newly introduced in FSP spec 1.1 */
#define FSP_HOB_RESOURCE_OWNER_BOOTLOADER_TOLUM_GUID \
- { \
- 0x73ff4f56, 0xaa8e, 0x4451, \
- { 0xb3, 0x16, 0x36, 0x35, 0x36, 0x67, 0xad, 0x44 } \
- }
+ EFI_GUID(0x73ff4f56, 0xaa8e, 0x4451, \
+ 0xb3, 0x16, 0x36, 0x35, 0x36, 0x67, 0xad, 0x44)
#define FSP_GRAPHICS_INFO_HOB_GUID \
- { \
- 0x39f62cce, 0x6825, 0x4669, \
- { 0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07 } \
- }
+ EFI_GUID(0x39f62cce, 0x6825, 0x4669, \
+ 0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07)
#endif
diff --git a/arch/x86/include/asm/fsp/fsp_support.h b/arch/x86/include/asm/fsp/fsp_support.h
index 7e51f24..7b92392 100644
--- a/arch/x86/include/asm/fsp/fsp_support.h
+++ b/arch/x86/include/asm/fsp/fsp_support.h
@@ -8,10 +8,10 @@
#define __FSP_SUPPORT_H__
#include "fsp_types.h"
+#include "fsp_hob.h"
#include "fsp_fv.h"
#include "fsp_ffs.h"
#include "fsp_api.h"
-#include "fsp_hob.h"
#include "fsp_infoheader.h"
#include "fsp_bootmode.h"
#include "fsp_azalia.h"
@@ -106,7 +106,7 @@
* 0 if this region does not exist.
*/
u64 fsp_get_reserved_mem_from_guid(const void *hob_list,
- u64 *len, struct efi_guid *guid);
+ u64 *len, const efi_guid_t *guid);
/**
* This function retrieves the FSP reserved normal memory.
@@ -132,41 +132,6 @@
u32 fsp_get_tseg_reserved_mem(const void *hob_list, u32 *len);
/**
- * Returns the next instance of a HOB type from the starting HOB.
- *
- * @type: HOB type to search
- * @hob_list: A pointer to the HOB list
- *
- * @retval: A HOB object with matching type; Otherwise NULL.
- */
-const struct hob_header *fsp_get_next_hob(uint type, const void *hob_list);
-
-/**
- * Returns the next instance of the matched GUID HOB from the starting HOB.
- *
- * @guid: GUID to search
- * @hob_list: A pointer to the HOB list
- *
- * @retval: A HOB object with matching GUID; Otherwise NULL.
- */
-const struct hob_header *fsp_get_next_guid_hob(const struct efi_guid *guid,
- const void *hob_list);
-
-/**
- * This function retrieves a GUID HOB data buffer and size.
- *
- * @hob_list: A HOB list pointer.
- * @len: A pointer to the GUID HOB data buffer length.
- * If the GUID HOB is located, the length will be updated.
- * @guid A pointer to HOB GUID.
- *
- * @retval NULL: Failed to find the GUID HOB.
- * @retval others: GUID HOB data buffer pointer.
- */
-void *fsp_get_guid_hob_data(const void *hob_list, u32 *len,
- struct efi_guid *guid);
-
-/**
* This function retrieves FSP Non-volatile Storage HOB buffer and size.
*
* @hob_list: A HOB list pointer.
diff --git a/arch/x86/include/asm/fsp/fsp_types.h b/arch/x86/include/asm/fsp/fsp_types.h
index 5247102..3d5b17e 100644
--- a/arch/x86/include/asm/fsp/fsp_types.h
+++ b/arch/x86/include/asm/fsp/fsp_types.h
@@ -7,14 +7,6 @@
#ifndef __FSP_TYPES_H__
#define __FSP_TYPES_H__
-/* 128 bit buffer containing a unique identifier value */
-struct efi_guid {
- u32 data1;
- u16 data2;
- u16 data3;
- u8 data4[8];
-};
-
/**
* Returns a 16-bit signature built from 2 ASCII characters.
*
diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h
index 9398ec3..17a4d34 100644
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -83,7 +83,7 @@
const struct pch_gpio_map *gpio_map; /* board GPIO map */
struct memory_info meminfo; /* Memory information */
struct pei_memory_info pei_meminfo; /* PEI memory information */
-#ifdef CONFIG_HAVE_FSP
+#ifdef CONFIG_USE_HOB
void *hob_list; /* FSP HOB list */
#endif
struct mtrr_request mtrr_req[MAX_MTRR_REQUESTS];
@@ -137,10 +137,4 @@
#endif
-/*
- * Our private Global Data Flags
- */
-#define GD_FLG_COLD_BOOT 0x10000 /* Cold Boot */
-#define GD_FLG_WARM_BOOT 0x20000 /* Warm Boot */
-
#endif /* __ASM_GBL_DATA_H */
diff --git a/arch/x86/include/asm/hob.h b/arch/x86/include/asm/hob.h
new file mode 100644
index 0000000..b423982
--- /dev/null
+++ b/arch/x86/include/asm/hob.h
@@ -0,0 +1,230 @@
+/* SPDX-License-Identifier: Intel */
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef __HOB_H__
+#define __HOB_H__
+
+#include <efi.h>
+#include <efi_loader.h>
+
+/* Type of HOB Header */
+#define HOB_TYPE_MEM_ALLOC 0x0002
+#define HOB_TYPE_RES_DESC 0x0003
+#define HOB_TYPE_GUID_EXT 0x0004
+#define HOB_TYPE_UNUSED 0xFFFE
+#define HOB_TYPE_EOH 0xFFFF
+
+/* Value of ResourceType in HOB_RES_DESC */
+#define RES_SYS_MEM 0x00000000
+#define RES_MMAP_IO 0x00000001
+#define RES_IO 0x00000002
+#define RES_FW_DEVICE 0x00000003
+#define RES_MMAP_IO_PORT 0x00000004
+#define RES_MEM_RESERVED 0x00000005
+#define RES_IO_RESERVED 0x00000006
+#define RES_MAX_MEM_TYPE 0x00000007
+
+/*
+ * These types can be ORed together as needed.
+ *
+ * The first three enumerations describe settings
+ * The rest of the settings describe capabilities
+ */
+#define RES_ATTR_PRESENT 0x00000001
+#define RES_ATTR_INITIALIZED 0x00000002
+#define RES_ATTR_TESTED 0x00000004
+#define RES_ATTR_SINGLE_BIT_ECC 0x00000008
+#define RES_ATTR_MULTIPLE_BIT_ECC 0x00000010
+#define RES_ATTR_ECC_RESERVED_1 0x00000020
+#define RES_ATTR_ECC_RESERVED_2 0x00000040
+#define RES_ATTR_READ_PROTECTED 0x00000080
+#define RES_ATTR_WRITE_PROTECTED 0x00000100
+#define RES_ATTR_EXECUTION_PROTECTED 0x00000200
+#define RES_ATTR_UNCACHEABLE 0x00000400
+#define RES_ATTR_WRITE_COMBINEABLE 0x00000800
+#define RES_ATTR_WRITE_THROUGH_CACHEABLE 0x00001000
+#define RES_ATTR_WRITE_BACK_CACHEABLE 0x00002000
+#define RES_ATTR_16_BIT_IO 0x00004000
+#define RES_ATTR_32_BIT_IO 0x00008000
+#define RES_ATTR_64_BIT_IO 0x00010000
+#define RES_ATTR_UNCACHED_EXPORTED 0x00020000
+
+/*
+ * Describes the format and size of the data inside the HOB.
+ * All HOBs must contain this generic HOB header.
+ */
+struct hob_header {
+ u16 type; /* HOB type */
+ u16 len; /* HOB length */
+ u32 reserved; /* always zero */
+};
+
+/*
+ * Describes all memory ranges used during the HOB producer phase that
+ * exist outside the HOB list. This HOB type describes how memory is used,
+ * not the physical attributes of memory.
+ */
+struct hob_mem_alloc {
+ struct hob_header hdr;
+ /*
+ * A GUID that defines the memory allocation region's type and purpose,
+ * as well as other fields within the memory allocation HOB. This GUID
+ * is used to define the additional data within the HOB that may be
+ * present for the memory allocation HOB. Type efi_guid_t is defined in
+ * InstallProtocolInterface() in the UEFI 2.0 specification.
+ */
+ efi_guid_t name;
+ /*
+ * The base address of memory allocated by this HOB.
+ * Type phys_addr_t is defined in AllocatePages() in the UEFI 2.0
+ * specification.
+ */
+ phys_addr_t mem_base;
+ /* The length in bytes of memory allocated by this HOB */
+ phys_size_t mem_len;
+ /*
+ * Defines the type of memory allocated by this HOB.
+ * The memory type definition follows the EFI_MEMORY_TYPE definition.
+ * Type EFI_MEMORY_TYPE is defined in AllocatePages() in the UEFI 2.0
+ * specification.
+ */
+ enum efi_mem_type mem_type;
+ /* padding */
+ u8 reserved[4];
+};
+
+/*
+ * Describes the resource properties of all fixed, nonrelocatable resource
+ * ranges found on the processor host bus during the HOB producer phase.
+ */
+struct hob_res_desc {
+ struct hob_header hdr;
+ /*
+ * A GUID representing the owner of the resource. This GUID is
+ * used by HOB consumer phase components to correlate device
+ * ownership of a resource.
+ */
+ efi_guid_t owner;
+ u32 type;
+ u32 attr;
+ /* The physical start address of the resource region */
+ phys_addr_t phys_start;
+ /* The number of bytes of the resource region */
+ phys_size_t len;
+};
+
+/*
+ * Allows writers of executable content in the HOB producer phase to
+ * maintain and manage HOBs with specific GUID.
+ */
+struct hob_guid {
+ struct hob_header hdr;
+ /* A GUID that defines the contents of this HOB */
+ efi_guid_t name;
+ /* GUID specific data goes here */
+};
+
+/**
+ * get_next_hob() - return a pointer to the next HOB in the HOB list
+ *
+ * This macro returns a pointer to HOB that follows the HOB specified by hob
+ * in the HOB List.
+ *
+ * @hdr: A pointer to a HOB.
+ *
+ * @return: A pointer to the next HOB in the HOB list.
+ */
+static inline const struct hob_header *get_next_hob(const struct hob_header
+ *hdr)
+{
+ return (const struct hob_header *)((uintptr_t)hdr + hdr->len);
+}
+
+/**
+ * end_of_hob() - determine if a HOB is the last HOB in the HOB list
+ *
+ * This macro determine if the HOB specified by hob is the last HOB in the
+ * HOB list. If hob is last HOB in the HOB list, then true is returned.
+ * Otherwise, false is returned.
+ *
+ * @hdr: A pointer to a HOB.
+ *
+ * @retval true: The HOB specified by hdr is the last HOB in the HOB list.
+ * @retval false: The HOB specified by hdr is not the last HOB in the HOB list.
+ */
+static inline bool end_of_hob(const struct hob_header *hdr)
+{
+ return hdr->type == HOB_TYPE_EOH;
+}
+
+/**
+ * get_guid_hob_data() - return a pointer to data buffer from a HOB of
+ * type HOB_TYPE_GUID_EXT
+ *
+ * This macro returns a pointer to the data buffer in a HOB specified by hob.
+ * hob is assumed to be a HOB of type HOB_TYPE_GUID_EXT.
+ *
+ * @hdr: A pointer to a HOB.
+ *
+ * @return: A pointer to the data buffer in a HOB.
+ */
+static inline void *get_guid_hob_data(const struct hob_header *hdr)
+{
+ return (void *)((uintptr_t)hdr + sizeof(struct hob_guid));
+}
+
+/**
+ * get_guid_hob_data_size() - return the size of the data buffer from a HOB
+ * of type HOB_TYPE_GUID_EXT
+ *
+ * This macro returns the size, in bytes, of the data buffer in a HOB
+ * specified by hob. hob is assumed to be a HOB of type HOB_TYPE_GUID_EXT.
+ *
+ * @hdr: A pointer to a HOB.
+ *
+ * @return: The size of the data buffer.
+ */
+static inline u16 get_guid_hob_data_size(const struct hob_header *hdr)
+{
+ return hdr->len - sizeof(struct hob_guid);
+}
+
+/**
+ * Returns the next instance of a HOB type from the starting HOB.
+ *
+ * @type: HOB type to search
+ * @hob_list: A pointer to the HOB list
+ *
+ * @retval: A HOB object with matching type; Otherwise NULL.
+ */
+const struct hob_header *hob_get_next_hob(uint type, const void *hob_list);
+
+/**
+ * Returns the next instance of the matched GUID HOB from the starting HOB.
+ *
+ * @guid: GUID to search
+ * @hob_list: A pointer to the HOB list
+ *
+ * @retval: A HOB object with matching GUID; Otherwise NULL.
+ */
+const struct hob_header *hob_get_next_guid_hob(const efi_guid_t *guid,
+ const void *hob_list);
+
+/**
+ * This function retrieves a GUID HOB data buffer and size.
+ *
+ * @hob_list: A HOB list pointer.
+ * @len: A pointer to the GUID HOB data buffer length.
+ * If the GUID HOB is located, the length will be updated.
+ * @guid A pointer to HOB GUID.
+ *
+ * @retval NULL: Failed to find the GUID HOB.
+ * @retval others: GUID HOB data buffer pointer.
+ */
+void *hob_get_guid_hob_data(const void *hob_list, u32 *len,
+ const efi_guid_t *guid);
+
+#endif /* __HOB_H__ */
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index 436252d..906be5e 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -42,6 +42,7 @@
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_CMD_ZBOOT) += zimage.o
endif
+obj-$(CONFIG_USE_HOB) += hob.o
obj-$(CONFIG_HAVE_FSP) += fsp/
ifdef CONFIG_SPL_BUILD
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index 270274f..0d69cf2 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -337,6 +337,30 @@
header->checksum = table_compute_checksum((void *)mcfg, header->length);
}
+__weak u32 acpi_fill_csrt(u32 current)
+{
+ return current;
+}
+
+static void acpi_create_csrt(struct acpi_csrt *csrt)
+{
+ struct acpi_table_header *header = &(csrt->header);
+ u32 current = (u32)csrt + sizeof(struct acpi_csrt);
+
+ memset((void *)csrt, 0, sizeof(struct acpi_csrt));
+
+ /* Fill out header fields */
+ acpi_fill_header(header, "CSRT");
+ header->length = sizeof(struct acpi_csrt);
+ header->revision = 0;
+
+ current = acpi_fill_csrt(current);
+
+ /* (Re)calculate length and checksum */
+ header->length = current - (u32)csrt;
+ header->checksum = table_compute_checksum((void *)csrt, header->length);
+}
+
static void acpi_create_spcr(struct acpi_spcr *spcr)
{
struct acpi_table_header *header = &(spcr->header);
@@ -464,6 +488,7 @@
struct acpi_fadt *fadt;
struct acpi_mcfg *mcfg;
struct acpi_madt *madt;
+ struct acpi_csrt *csrt;
struct acpi_spcr *spcr;
int i;
@@ -553,6 +578,13 @@
acpi_add_table(rsdp, mcfg);
current = ALIGN(current, 16);
+ debug("ACPI: * CSRT\n");
+ csrt = (struct acpi_csrt *)current;
+ acpi_create_csrt(csrt);
+ current += csrt->header.length;
+ acpi_add_table(rsdp, csrt);
+ current = ALIGN(current, 16);
+
debug("ACPI: * SPCR\n");
spcr = (struct acpi_spcr *)current;
acpi_create_spcr(spcr);
diff --git a/arch/x86/lib/asm-offsets.c b/arch/x86/lib/asm-offsets.c
index 90dce22..47b38cd 100644
--- a/arch/x86/lib/asm-offsets.c
+++ b/arch/x86/lib/asm-offsets.c
@@ -17,7 +17,7 @@
int main(void)
{
DEFINE(GD_BIST, offsetof(gd_t, arch.bist));
-#ifdef CONFIG_HAVE_FSP
+#ifdef CONFIG_USE_HOB
DEFINE(GD_HOB_LIST, offsetof(gd_t, arch.hob_list));
#endif
DEFINE(GD_TABLE, offsetof(gd_t, arch.table));
diff --git a/arch/x86/lib/e820.c b/arch/x86/lib/e820.c
index d6ae2c4..26da4d2 100644
--- a/arch/x86/lib/e820.c
+++ b/arch/x86/lib/e820.c
@@ -41,14 +41,17 @@
{
struct e820_entry e820[E820MAX];
unsigned int i, num;
- u64 start, pages;
+ u64 start, pages, ram_top;
int type;
num = install_e820_map(ARRAY_SIZE(e820), e820);
+ ram_top = (u64)gd->ram_top & ~EFI_PAGE_MASK;
+ if (!ram_top)
+ ram_top = 0x100000000ULL;
+
for (i = 0; i < num; ++i) {
start = e820[i].addr;
- pages = ALIGN(e820[i].size, EFI_PAGE_SIZE) >> EFI_PAGE_SHIFT;
switch (e820[i].type) {
case E820_RAM:
@@ -69,7 +72,15 @@
break;
}
- efi_add_memory_map(start, pages, type, false);
+ if (type == EFI_CONVENTIONAL_MEMORY) {
+ efi_add_conventional_memory_map(start,
+ start + e820[i].size,
+ ram_top);
+ } else {
+ pages = ALIGN(e820[i].size, EFI_PAGE_SIZE)
+ >> EFI_PAGE_SHIFT;
+ efi_add_memory_map(start, pages, type, false);
+ }
}
}
#endif /* CONFIG_IS_ENABLED(EFI_LOADER) */
diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c
index 90e4e7d..0eaa9b2 100644
--- a/arch/x86/lib/fsp/fsp_support.c
+++ b/arch/x86/lib/fsp/fsp_support.c
@@ -8,27 +8,6 @@
#include <asm/fsp/fsp_support.h>
#include <asm/post.h>
-/**
- * Compares two GUIDs
- *
- * If the GUIDs are identical then true is returned.
- * If there are any bit differences in the two GUIDs, then false is returned.
- *
- * @guid1: A pointer to a 128 bit GUID.
- * @guid2: A pointer to a 128 bit GUID.
- *
- * @retval true: guid1 and guid2 are identical.
- * @retval false: guid1 and guid2 are not identical.
- */
-static bool compare_guid(const struct efi_guid *guid1,
- const struct efi_guid *guid2)
-{
- if (memcmp(guid1, guid2, sizeof(struct efi_guid)) == 0)
- return true;
- else
- return false;
-}
-
struct fsp_header *__attribute__((optimize("O0"))) find_fsp_header(void)
{
/*
@@ -58,17 +37,22 @@
/* Check the FFS GUID */
if (fsp &&
- ((struct ffs_file_header *)fsp)->name.data1 == FSP_GUID_DATA1 &&
- ((struct ffs_file_header *)fsp)->name.data2 == FSP_GUID_DATA2 &&
- ((struct ffs_file_header *)fsp)->name.data3 == FSP_GUID_DATA3 &&
- ((struct ffs_file_header *)fsp)->name.data4[0] == FSP_GUID_DATA4_0 &&
- ((struct ffs_file_header *)fsp)->name.data4[1] == FSP_GUID_DATA4_1 &&
- ((struct ffs_file_header *)fsp)->name.data4[2] == FSP_GUID_DATA4_2 &&
- ((struct ffs_file_header *)fsp)->name.data4[3] == FSP_GUID_DATA4_3 &&
- ((struct ffs_file_header *)fsp)->name.data4[4] == FSP_GUID_DATA4_4 &&
- ((struct ffs_file_header *)fsp)->name.data4[5] == FSP_GUID_DATA4_5 &&
- ((struct ffs_file_header *)fsp)->name.data4[6] == FSP_GUID_DATA4_6 &&
- ((struct ffs_file_header *)fsp)->name.data4[7] == FSP_GUID_DATA4_7) {
+ ((struct ffs_file_header *)fsp)->name.b[0] == FSP_GUID_BYTE0 &&
+ ((struct ffs_file_header *)fsp)->name.b[1] == FSP_GUID_BYTE1 &&
+ ((struct ffs_file_header *)fsp)->name.b[2] == FSP_GUID_BYTE2 &&
+ ((struct ffs_file_header *)fsp)->name.b[3] == FSP_GUID_BYTE3 &&
+ ((struct ffs_file_header *)fsp)->name.b[4] == FSP_GUID_BYTE4 &&
+ ((struct ffs_file_header *)fsp)->name.b[5] == FSP_GUID_BYTE5 &&
+ ((struct ffs_file_header *)fsp)->name.b[6] == FSP_GUID_BYTE6 &&
+ ((struct ffs_file_header *)fsp)->name.b[7] == FSP_GUID_BYTE7 &&
+ ((struct ffs_file_header *)fsp)->name.b[8] == FSP_GUID_BYTE8 &&
+ ((struct ffs_file_header *)fsp)->name.b[9] == FSP_GUID_BYTE9 &&
+ ((struct ffs_file_header *)fsp)->name.b[10] == FSP_GUID_BYTE10 &&
+ ((struct ffs_file_header *)fsp)->name.b[11] == FSP_GUID_BYTE11 &&
+ ((struct ffs_file_header *)fsp)->name.b[12] == FSP_GUID_BYTE12 &&
+ ((struct ffs_file_header *)fsp)->name.b[13] == FSP_GUID_BYTE13 &&
+ ((struct ffs_file_header *)fsp)->name.b[14] == FSP_GUID_BYTE14 &&
+ ((struct ffs_file_header *)fsp)->name.b[15] == FSP_GUID_BYTE15) {
/* Add the FFS header size to find the raw section header */
fsp += sizeof(struct ffs_file_header);
} else {
@@ -305,7 +289,7 @@
}
u64 fsp_get_reserved_mem_from_guid(const void *hob_list, u64 *len,
- struct efi_guid *guid)
+ const efi_guid_t *guid)
{
const struct hob_header *hdr;
struct hob_res_desc *res_desc;
@@ -318,7 +302,7 @@
if (hdr->type == HOB_TYPE_RES_DESC) {
res_desc = (struct hob_res_desc *)hdr;
if (res_desc->type == RES_MEM_RESERVED) {
- if (compare_guid(&res_desc->owner, guid)) {
+ if (!guidcmp(&res_desc->owner, guid)) {
if (len)
*len = (u32)(res_desc->len);
@@ -334,12 +318,12 @@
u32 fsp_get_fsp_reserved_mem(const void *hob_list, u32 *len)
{
- const struct efi_guid guid = FSP_HOB_RESOURCE_OWNER_FSP_GUID;
+ const efi_guid_t guid = FSP_HOB_RESOURCE_OWNER_FSP_GUID;
u64 length;
u32 base;
base = (u32)fsp_get_reserved_mem_from_guid(hob_list,
- &length, (struct efi_guid *)&guid);
+ &length, &guid);
if ((len != 0) && (base != 0))
*len = (u32)length;
@@ -348,86 +332,35 @@
u32 fsp_get_tseg_reserved_mem(const void *hob_list, u32 *len)
{
- const struct efi_guid guid = FSP_HOB_RESOURCE_OWNER_TSEG_GUID;
+ const efi_guid_t guid = FSP_HOB_RESOURCE_OWNER_TSEG_GUID;
u64 length;
u32 base;
base = (u32)fsp_get_reserved_mem_from_guid(hob_list,
- &length, (struct efi_guid *)&guid);
+ &length, &guid);
if ((len != 0) && (base != 0))
*len = (u32)length;
return base;
}
-const struct hob_header *fsp_get_next_hob(uint type, const void *hob_list)
-{
- const struct hob_header *hdr;
-
- hdr = hob_list;
-
- /* Parse the HOB list until end of list or matching type is found */
- while (!end_of_hob(hdr)) {
- if (hdr->type == type)
- return hdr;
-
- hdr = get_next_hob(hdr);
- }
-
- return NULL;
-}
-
-const struct hob_header *fsp_get_next_guid_hob(const struct efi_guid *guid,
- const void *hob_list)
-{
- const struct hob_header *hdr;
- struct hob_guid *guid_hob;
-
- hdr = hob_list;
- while ((hdr = fsp_get_next_hob(HOB_TYPE_GUID_EXT,
- hdr)) != NULL) {
- guid_hob = (struct hob_guid *)hdr;
- if (compare_guid(guid, &(guid_hob->name)))
- break;
- hdr = get_next_hob(hdr);
- }
-
- return hdr;
-}
-
-void *fsp_get_guid_hob_data(const void *hob_list, u32 *len,
- struct efi_guid *guid)
-{
- const struct hob_header *guid_hob;
-
- guid_hob = fsp_get_next_guid_hob(guid, hob_list);
- if (guid_hob == NULL) {
- return NULL;
- } else {
- if (len)
- *len = get_guid_hob_data_size(guid_hob);
-
- return get_guid_hob_data(guid_hob);
- }
-}
-
void *fsp_get_nvs_data(const void *hob_list, u32 *len)
{
- const struct efi_guid guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID;
+ const efi_guid_t guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID;
- return fsp_get_guid_hob_data(hob_list, len, (struct efi_guid *)&guid);
+ return hob_get_guid_hob_data(hob_list, len, &guid);
}
void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len)
{
- const struct efi_guid guid = FSP_BOOTLOADER_TEMP_MEM_HOB_GUID;
+ const efi_guid_t guid = FSP_BOOTLOADER_TEMP_MEM_HOB_GUID;
- return fsp_get_guid_hob_data(hob_list, len, (struct efi_guid *)&guid);
+ return hob_get_guid_hob_data(hob_list, len, &guid);
}
void *fsp_get_graphics_info(const void *hob_list, u32 *len)
{
- const struct efi_guid guid = FSP_GRAPHICS_INFO_HOB_GUID;
+ const efi_guid_t guid = FSP_GRAPHICS_INFO_HOB_GUID;
- return fsp_get_guid_hob_data(hob_list, len, (struct efi_guid *)&guid);
+ return hob_get_guid_hob_data(hob_list, len, &guid);
}
diff --git a/arch/x86/lib/hob.c b/arch/x86/lib/hob.c
new file mode 100644
index 0000000..dcee29b
--- /dev/null
+++ b/arch/x86/lib/hob.c
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: Intel
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <asm/hob.h>
+
+/**
+ * Returns the next instance of a HOB type from the starting HOB.
+ *
+ * @type: HOB type to search
+ * @hob_list: A pointer to the HOB list
+ *
+ * @retval: A HOB object with matching type; Otherwise NULL.
+ */
+const struct hob_header *hob_get_next_hob(uint type, const void *hob_list)
+{
+ const struct hob_header *hdr;
+
+ hdr = hob_list;
+
+ /* Parse the HOB list until end of list or matching type is found */
+ while (!end_of_hob(hdr)) {
+ if (hdr->type == type)
+ return hdr;
+
+ hdr = get_next_hob(hdr);
+ }
+
+ return NULL;
+}
+
+/**
+ * Returns the next instance of the matched GUID HOB from the starting HOB.
+ *
+ * @guid: GUID to search
+ * @hob_list: A pointer to the HOB list
+ *
+ * @retval: A HOB object with matching GUID; Otherwise NULL.
+ */
+const struct hob_header *hob_get_next_guid_hob(const efi_guid_t *guid,
+ const void *hob_list)
+{
+ const struct hob_header *hdr;
+ struct hob_guid *guid_hob;
+
+ hdr = hob_list;
+ while ((hdr = hob_get_next_hob(HOB_TYPE_GUID_EXT, hdr))) {
+ guid_hob = (struct hob_guid *)hdr;
+ if (!guidcmp(guid, &guid_hob->name))
+ break;
+ hdr = get_next_hob(hdr);
+ }
+
+ return hdr;
+}
+
+/**
+ * This function retrieves a GUID HOB data buffer and size.
+ *
+ * @hob_list: A HOB list pointer.
+ * @len: A pointer to the GUID HOB data buffer length.
+ * If the GUID HOB is located, the length will be updated.
+ * @guid A pointer to HOB GUID.
+ *
+ * @retval NULL: Failed to find the GUID HOB.
+ * @retval others: GUID HOB data buffer pointer.
+ */
+void *hob_get_guid_hob_data(const void *hob_list, u32 *len,
+ const efi_guid_t *guid)
+{
+ const struct hob_header *guid_hob;
+
+ guid_hob = hob_get_next_guid_hob(guid, hob_list);
+ if (!guid_hob)
+ return NULL;
+
+ if (len)
+ *len = get_guid_hob_data_size(guid_hob);
+
+ return get_guid_hob_data(guid_hob);
+}
diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c
index 0481f45..4774a9b 100644
--- a/arch/x86/lib/init_helpers.c
+++ b/arch/x86/lib/init_helpers.c
@@ -10,15 +10,10 @@
DECLARE_GLOBAL_DATA_PTR;
-/* Get the top of usable RAM */
-__weak ulong board_get_usable_ram_top(ulong total_size)
-{
- return gd->ram_size;
-}
-
int init_cache_f_r(void)
{
-#if CONFIG_IS_ENABLED(X86_32BIT_INIT) && !defined(CONFIG_HAVE_FSP)
+#if CONFIG_IS_ENABLED(X86_32BIT_INIT) && !defined(CONFIG_HAVE_FSP) && \
+ !defined(CONFIG_SYS_SLIMBOOTLOADER)
int ret;
ret = mtrr_commit(false);
diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c
index 230b38e..d07041f 100644
--- a/arch/x86/lib/zimage.c
+++ b/arch/x86/lib/zimage.c
@@ -13,6 +13,7 @@
*/
#include <common.h>
+#include <env.h>
#include <malloc.h>
#include <asm/acpi_table.h>
#include <asm/io.h>
@@ -287,6 +288,10 @@
hdr->hardware_subarch = X86_SUBARCH_INTEL_MID;
#endif
+#ifdef CONFIG_GENERATE_ACPI_TABLE
+ setup_base->acpi_rsdp_addr = acpi_get_rsdp_addr();
+#endif
+
setup_device_tree(hdr, (const void *)env_get_hex("fdtaddr", 0));
setup_video(&setup_base->screen_info);
diff --git a/arch/xtensa/lib/bootm.c b/arch/xtensa/lib/bootm.c
index aceed15..93eea53 100644
--- a/arch/xtensa/lib/bootm.c
+++ b/arch/xtensa/lib/bootm.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <u-boot/zlib.h>
#include <asm/byteorder.h>
#include <asm/addrspace.h>
diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c b/board/AndesTech/ax25-ae350/ax25-ae350.c
index 3d65ce7..b43eebb 100644
--- a/board/AndesTech/ax25-ae350/ax25-ae350.c
+++ b/board/AndesTech/ax25-ae350/ax25-ae350.c
@@ -11,6 +11,7 @@
#include <linux/io.h>
#include <faraday/ftsmc020.h>
#include <fdtdec.h>
+#include <dm.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -93,10 +94,18 @@
return 0;
}
+static void v5l2_init(void)
+{
+ struct udevice *dev;
+
+ uclass_get_device(UCLASS_CACHE, 0, &dev);
+}
+
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
smc_init();
+ v5l2_init();
return 0;
}
diff --git a/board/Arcturus/ucp1020/cmd_arc.c b/board/Arcturus/ucp1020/cmd_arc.c
index 7a510c6..2e8477e 100644
--- a/board/Arcturus/ucp1020/cmd_arc.c
+++ b/board/Arcturus/ucp1020/cmd_arc.c
@@ -10,11 +10,11 @@
#include <common.h>
#include <div64.h>
+#include <env.h>
#include <malloc.h>
#include <spi_flash.h>
#include <mmc.h>
#include <version.h>
-#include <environment.h>
#include <asm/io.h>
static ulong fwenv_addr[MAX_FWENV_ADDR];
diff --git a/board/Arcturus/ucp1020/spl.c b/board/Arcturus/ucp1020/spl.c
index 451a9d7..9314fab 100644
--- a/board/Arcturus/ucp1020/spl.c
+++ b/board/Arcturus/ucp1020/spl.c
@@ -9,7 +9,8 @@
#include <common.h>
#include <console.h>
-#include <environment.h>
+#include <env.h>
+#include <env_internal.h>
#include <ns16550.h>
#include <malloc.h>
#include <mmc.h>
diff --git a/board/Arcturus/ucp1020/ucp1020.c b/board/Arcturus/ucp1020/ucp1020.c
index 54fd178..6a880c9 100644
--- a/board/Arcturus/ucp1020/ucp1020.c
+++ b/board/Arcturus/ucp1020/ucp1020.c
@@ -10,6 +10,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <hwconfig.h>
#include <pci.h>
#include <i2c.h>
diff --git a/board/BuR/brppt1/board.c b/board/BuR/brppt1/board.c
index b8ab19c..ef4f5c9 100644
--- a/board/BuR/brppt1/board.c
+++ b/board/BuR/brppt1/board.c
@@ -10,6 +10,7 @@
*/
#include <common.h>
+#include <env.h>
#include <errno.h>
#include <spl.h>
#include <asm/arch/cpu.h>
diff --git a/board/BuR/brsmarc1/Kconfig b/board/BuR/brsmarc1/Kconfig
new file mode 100644
index 0000000..6d3d7a2
--- /dev/null
+++ b/board/BuR/brsmarc1/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_BRSMARC1
+
+config SYS_BOARD
+ default "brsmarc1"
+
+config SYS_VENDOR
+ default "BuR"
+
+config SYS_SOC
+ default "am33xx"
+
+config SYS_CONFIG_NAME
+ default "brsmarc1"
+
+endif
diff --git a/board/BuR/brsmarc1/MAINTAINERS b/board/BuR/brsmarc1/MAINTAINERS
new file mode 100644
index 0000000..c6dfc20
--- /dev/null
+++ b/board/BuR/brsmarc1/MAINTAINERS
@@ -0,0 +1,6 @@
+BRSMARC1 BOARD
+M: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
+S: Maintained
+F: board/BuR/brsmarc1/
+F: include/configs/brsmarc1.h
+F: configs/brsmarc1_defconfig
diff --git a/board/BuR/brsmarc1/Makefile b/board/BuR/brsmarc1/Makefile
new file mode 100644
index 0000000..1c3f64d
--- /dev/null
+++ b/board/BuR/brsmarc1/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2019 Hannes Schmelzer <oe5hpm@oevsv.at> -
+# B&R Industrial Automation GmbH - http://www.br-automation.com/
+#
+
+obj-$(CONFIG_SPL_BUILD) += mux.o
+obj-y += ../common/br_resetc.o
+obj-y += ../common/common.o
+obj-y += board.o
diff --git a/board/BuR/brsmarc1/board.c b/board/BuR/brsmarc1/board.c
new file mode 100644
index 0000000..4c70346
--- /dev/null
+++ b/board/BuR/brsmarc1/board.c
@@ -0,0 +1,168 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * board.c
+ *
+ * Board functions for B&R BRSMARC1 Board
+ *
+ * Copyright (C) 2017 Hannes Schmelzer <oe5hpm@oevsv.at>
+ * B&R Industrial Automation GmbH - http://www.br-automation.com
+ *
+ */
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/emif.h>
+#include <power/tps65217.h>
+#include "../common/bur_common.h"
+#include "../common/br_resetc.h"
+
+/* -------------------------------------------------------------------------*/
+/* -- defines for used GPIO Hardware -- */
+#define PER_RESET (2 * 32 + 0)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SPL_BUILD)
+static const struct ddr_data ddr3_data = {
+ .datardsratio0 = MT41K256M16HA125E_RD_DQS,
+ .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+ .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+ .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+ .cmd0csratio = MT41K256M16HA125E_RATIO,
+ .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+ .cmd1csratio = MT41K256M16HA125E_RATIO,
+ .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+ .cmd2csratio = MT41K256M16HA125E_RATIO,
+ .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+ .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+ .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+ .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+ .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+ .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+ .zq_config = MT41K256M16HA125E_ZQ_CFG,
+ .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+static const struct ctrl_ioregs ddr3_ioregs = {
+ .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+#define OSC (V_OSCK / 1000000)
+const struct dpll_params dpll_ddr3 = { 400, OSC - 1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+ struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
+ struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
+
+ int rc;
+ /*
+ * enable additional clocks of modules which are accessed later from
+ * VxWorks OS
+ */
+ u32 *const clk_domains[] = { 0 };
+ u32 *const clk_modules_specific[] = {
+ &cmwkup->wkup_adctscctrl,
+ &cmper->spi1clkctrl,
+ &cmper->dcan0clkctrl,
+ &cmper->dcan1clkctrl,
+ &cmper->timer4clkctrl,
+ &cmper->timer5clkctrl,
+ &cmper->lcdclkctrl,
+ &cmper->lcdcclkstctrl,
+ 0
+ };
+ do_enable_clocks(clk_domains, clk_modules_specific, 1);
+
+ /* setup I2C */
+ enable_i2c_pin_mux();
+
+ /* peripheral reset */
+ rc = gpio_request(PER_RESET, "PER_RESET");
+ if (rc != 0)
+ printf("cannot request PER_RESET GPIO!\n");
+
+ rc = gpio_direction_output(PER_RESET, 0);
+ if (rc != 0)
+ printf("cannot set PER_RESET GPIO!\n");
+
+ /* setup pmic */
+ pmicsetup(0, 0);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+ return &dpll_ddr3;
+}
+
+void sdram_init(void)
+{
+ config_ddr(400, &ddr3_ioregs,
+ &ddr3_data,
+ &ddr3_cmd_ctrl_data,
+ &ddr3_emif_reg_data, 0);
+}
+#endif /* CONFIG_SPL_BUILD */
+#if !defined(CONFIG_SPL_BUILD)
+
+/* decision if backlight is switched on or not on powerup */
+int board_backlightstate(void)
+{
+ u8 bklmask, rstcause;
+ int rc = 0;
+
+ rc |= br_resetc_regget(RSTCTRL_SCRATCHREG1, &bklmask);
+ rc |= br_resetc_regget(RSTCTRL_ERSTCAUSE, &rstcause);
+
+ if (rc != 0) {
+ printf("%s: read rstctrl failed!\n", __func__);
+ return 1;
+ }
+
+ if ((rstcause & bklmask) != 0)
+ return 0;
+
+ return 1;
+}
+
+/* Basic board specific setup. run quite after relocation */
+int board_init(void)
+{
+ if (power_tps65217_init(0))
+ printf("WARN: cannot setup PMIC 0x24 @ bus #0, not found!.\n");
+
+ return 0;
+}
+
+#if defined(CONFIG_BOARD_LATE_INIT)
+
+int board_late_init(void)
+{
+ br_resetc_bmode();
+
+ return 0;
+}
+
+#endif /* CONFIG_BOARD_LATE_INIT */
+#endif /* !CONFIG_SPL_BUILD */
diff --git a/board/BuR/brsmarc1/config.mk b/board/BuR/brsmarc1/config.mk
new file mode 100644
index 0000000..0692988
--- /dev/null
+++ b/board/BuR/brsmarc1/config.mk
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2019 Hannes Schmelzer <oe5hpm@oevsv.at> -
+# B&R Industrial Automation GmbH - http://www.br-automation.com
+#
+
+hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE) | sed -e 's/am335x-//')
+
+payload_off :=$(shell printf "%d" $(CONFIG_SYS_SPI_U_BOOT_OFFS))
+
+quiet_cmd_prodbin = PRODBIN $@ $(payload_off)
+cmd_prodbin = \
+ dd if=/dev/zero ibs=1M count=2 2>/dev/null | tr "\000" "\377" >$@ && \
+ dd conv=notrunc bs=1 if=MLO.byteswap of=$@ seek=0 2>/dev/null && \
+ dd bs=1 if=u-boot-dtb.img of=$@ seek=$(payload_off) 2>/dev/null
+
+quiet_cmd_prodzip = SAPZIP $@
+cmd_prodzip = \
+ test -d misc && rm -r misc; \
+ mkdir misc && \
+ cp MLO.byteswap misc/ && \
+ cp spl/u-boot-spl.bin misc/ && \
+ cp u-boot-dtb.img misc/ && \
+ zip -9 -r $@ misc/* >/dev/null $<
+
+ALL-y += $(hw-platform-y)_prog.bin
+ALL-y += $(hw-platform-y)_prod.zip
+
+$(hw-platform-y)_prog.bin: u-boot-dtb.img spl/u-boot-spl.bin
+ $(call if_changed,prodbin)
+
+$(hw-platform-y)_prod.zip: $(hw-platform-y)_prog.bin
+ $(call if_changed,prodzip)
\ No newline at end of file
diff --git a/board/BuR/brsmarc1/mux.c b/board/BuR/brsmarc1/mux.c
new file mode 100644
index 0000000..33c214d
--- /dev/null
+++ b/board/BuR/brsmarc1/mux.c
@@ -0,0 +1,266 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * mux.c
+ *
+ * Pinmux Setting for B&R BRSMARC1 Board (HW-Rev. 1)
+ *
+ * Copyright (C) 2017 Hannes Schmelzer <hannes.schmelzer@br-automation.com>
+ * B&R Industrial Automation GmbH - http://www.br-automation.com
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+
+static struct module_pin_mux spi0_pin_mux[] = {
+ /* SPI0_SCLK */
+ {OFFSET(spi0_sclk), MODE(0) | PULLUDEN | RXACTIVE},
+ /* SPI0_D0 */
+ {OFFSET(spi0_d0), MODE(0) | PULLUDEN | RXACTIVE},
+ /* SPI0_D1 */
+ {OFFSET(spi0_d1), MODE(0) | PULLUDEN | RXACTIVE},
+ /* SPI0_CS0 */
+ {OFFSET(spi0_cs0), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
+ /* SPI0_CS1 */
+ {OFFSET(spi0_cs1), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
+ {-1},
+};
+
+static struct module_pin_mux spi1_pin_mux[] = {
+ /* SPI1_SCLK */
+ {OFFSET(mcasp0_aclkx), MODE(3) | PULLUDEN | RXACTIVE},
+ /* SPI1_D0 */
+ {OFFSET(mcasp0_fsx), MODE(3) | PULLUDEN | RXACTIVE},
+ /* SPI1_D1 */
+ {OFFSET(mcasp0_axr0), MODE(3) | PULLUDEN | RXACTIVE},
+ /* SPI1_CS0 */
+ {OFFSET(mcasp0_ahclkr), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
+ /* SPI1_CS1 */
+ {OFFSET(xdma_event_intr0), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
+ {-1},
+};
+
+static struct module_pin_mux dcan0_pin_mux[] = {
+ /* DCAN0 TX */
+ {OFFSET(uart1_ctsn), MODE(2) | PULLUDEN | PULLUP_EN},
+ /* DCAN0 RX */
+ {OFFSET(uart1_rtsn), MODE(2) | RXACTIVE},
+ {-1},
+};
+
+static struct module_pin_mux dcan1_pin_mux[] = {
+ /* DCAN1 TX */
+ {OFFSET(uart0_ctsn), MODE(2) | PULLUDEN | PULLUP_EN},
+ /* DCAN1 RX */
+ {OFFSET(uart0_rtsn), MODE(2) | RXACTIVE},
+ {-1},
+};
+
+static struct module_pin_mux gpios[] = {
+ /* GPIO0_7 - LVDS_EN */
+ {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
+ /* GPIO0_20 - BKLT_PWM (timer7) */
+ {OFFSET(xdma_event_intr1), (MODE(4) | PULLUDDIS | PULLDOWN_EN)},
+ /* GPIO2_4 - DISON */
+ {OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
+ /* GPIO1_24 - RGB_EN */
+ {OFFSET(gpmc_a8), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
+ /* GPIO1_28 - nPD */
+ {OFFSET(gpmc_be1n), (MODE(7) | PULLUDEN | PULLUP_EN)},
+ /* GPIO2_5 - Watchdog */
+ {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
+ /* GPIO2_0 - ResetOut */
+ {OFFSET(gpmc_csn3), (MODE(7) | PULLUDEN | PULLUP_EN)},
+ /* GPIO2_2 - BKLT_EN */
+ {OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
+ /* GPIO1_17 - GPIO0 */
+ {OFFSET(gpmc_a1), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO1_18 - GPIO1 */
+ {OFFSET(gpmc_a2), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO1_19 - GPIO2 */
+ {OFFSET(gpmc_a3), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO1_22 - GPIO3 */
+ {OFFSET(gpmc_a6), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO1_23 - GPIO4 */
+ {OFFSET(gpmc_a7), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO1_25 - GPIO5 */
+ {OFFSET(gpmc_a9), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO3_7 - GPIO6 */
+ {OFFSET(emu0), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO3_8 - GPIO7 */
+ {OFFSET(emu1), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO3_18 - GPIO8 */
+ {OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO3_19 - GPIO9 */
+ {OFFSET(mcasp0_fsr), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO3_20 - GPIO10 */
+ {OFFSET(mcasp0_axr1), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO3_21 - GPIO11 */
+ {OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO2_28 - DRAM-strapping */
+ {OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | PULLUP_EN)},
+ /* GPIO2_4 - not routed (Pin U6) */
+ {OFFSET(gpmc_wen), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+ /* GPIO2_5 - not routed (Pin T6) */
+ {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+ /* GPIO2_28 - not routed (Pin G15) */
+ {OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+ /* GPIO3_18 - not routed (Pin B12) */
+ {OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+ {-1},
+};
+
+static struct module_pin_mux uart0_pin_mux[] = {
+ /* UART0_RXD */
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+ /* UART0_TXD */
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
+ {-1},
+};
+
+static struct module_pin_mux uart234_pin_mux[] = {
+ /* UART2_RXD */
+ {OFFSET(mii1_txclk), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+ /* UART2_TXD */
+ {OFFSET(mii1_rxclk), (MODE(1) | PULLUDEN)},
+
+ /* UART3_RXD */
+ {OFFSET(mii1_rxd3), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+ /* UART3_TXD */
+ {OFFSET(mmc0_dat0), (MODE(3) | PULLUDEN)},
+ /* UART3_RTS */
+ {OFFSET(mmc0_cmd), (MODE(2) | PULLUDEN)},
+ /* UART3_CTS */
+ {OFFSET(mmc0_clk), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+
+ /* UART4_RXD */
+ {OFFSET(mii1_txd3), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+ /* UART4_TXD */
+ {OFFSET(mii1_txd2), (MODE(3) | PULLUDEN)},
+ /* UART4_RTS */
+ {OFFSET(mmc0_dat2), (MODE(3) | PULLUDEN)},
+ /* UART4_CTS */
+ {OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+
+ {-1},
+};
+
+static struct module_pin_mux i2c_pin_mux[] = {
+ /* I2C0_DATA */
+ {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+ /* I2C0_SCLK */
+ {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+ /* I2C1_DATA */
+ {OFFSET(uart1_rxd), (MODE(3) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+ /* I2C1_SCLK */
+ {OFFSET(uart1_txd), (MODE(3) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+ {-1},
+};
+
+static struct module_pin_mux eth_pin_mux[] = {
+ /* ETH1 */
+ {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* ETH1_REFCLK */
+ {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRSDV */
+ {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXER */
+ {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
+ {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
+ {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
+ {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */
+ {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
+
+ /* ETH2 */
+ {OFFSET(mii1_col), MODE(1) | RXACTIVE}, /* ETH2_REFCLK */
+ {OFFSET(gpmc_wait0), MODE(3) | RXACTIVE}, /* RMII2_CRSDV */
+ {OFFSET(gpmc_wpn), MODE(3) | RXACTIVE}, /* RMII2_RXER */
+ {OFFSET(gpmc_a0), MODE(3)}, /* RMII2_TXEN */
+ {OFFSET(gpmc_a11), MODE(3) | RXACTIVE}, /* RMII2_RXD0 */
+ {OFFSET(gpmc_a10), MODE(3) | RXACTIVE}, /* RMII2_RXD1 */
+ {OFFSET(gpmc_a5), MODE(3)}, /* RMII2_TXD0 */
+ {OFFSET(gpmc_a4), MODE(3)}, /* RMII2_TXD1 */
+
+ /* gpio2_19, gpio 3_4, not connected on board */
+ {OFFSET(mii1_rxd2), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
+ {OFFSET(mii1_rxdv), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
+
+ /* ETH Management */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+
+ {-1},
+};
+
+static struct module_pin_mux mmc1_pin_mux[] = {
+ {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */
+ {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */
+ {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */
+ {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */
+ {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
+ {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
+ {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
+ {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
+ {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
+ {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
+ {-1},
+};
+
+static struct module_pin_mux lcd_pin_mux[] = {
+ {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */
+ {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */
+ {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */
+ {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */
+ {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */
+ {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */
+ {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */
+ {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */
+ {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */
+ {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */
+ {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */
+ {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */
+ {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */
+ {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */
+ {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */
+ {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */
+
+ {OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */
+ {OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */
+ {OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */
+ {OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */
+ {OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */
+ {OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */
+ {OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */
+ {OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */
+
+ {OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */
+ {OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */
+ {OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
+ {OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */
+
+ {-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_i2c_pin_mux(void)
+{
+ configure_module_pin_mux(i2c_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+ configure_module_pin_mux(eth_pin_mux);
+ configure_module_pin_mux(spi0_pin_mux);
+ configure_module_pin_mux(spi1_pin_mux);
+ configure_module_pin_mux(dcan0_pin_mux);
+ configure_module_pin_mux(dcan1_pin_mux);
+ configure_module_pin_mux(uart234_pin_mux);
+ configure_module_pin_mux(mmc1_pin_mux);
+ configure_module_pin_mux(lcd_pin_mux);
+ configure_module_pin_mux(gpios);
+}
diff --git a/board/BuR/brxre1/board.c b/board/BuR/brxre1/board.c
index 0d1c6c4..873208c 100644
--- a/board/BuR/brxre1/board.c
+++ b/board/BuR/brxre1/board.c
@@ -9,6 +9,7 @@
*
*/
#include <common.h>
+#include <env.h>
#include <errno.h>
#include <spl.h>
#include <asm/arch/cpu.h>
diff --git a/board/BuR/common/br_resetc.c b/board/BuR/common/br_resetc.c
index c8cc73a..c0e7fb6 100644
--- a/board/BuR/common/br_resetc.c
+++ b/board/BuR/common/br_resetc.c
@@ -6,6 +6,7 @@
* B&R Industrial Automation GmbH - http://www.br-automation.com/ *
*/
#include <common.h>
+#include <env.h>
#include <errno.h>
#include <i2c.h>
#include <dm/uclass.h>
diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c
index 89087d7..148fc90 100644
--- a/board/BuR/common/common.c
+++ b/board/BuR/common/common.c
@@ -10,6 +10,7 @@
*/
#include <version.h>
#include <common.h>
+#include <env.h>
#include <fdtdec.h>
#include <i2c.h>
#include <lcd.h>
diff --git a/board/BuS/eb_cpu5282/eb_cpu5282.c b/board/BuS/eb_cpu5282/eb_cpu5282.c
index 3791948..0b916d2 100644
--- a/board/BuS/eb_cpu5282/eb_cpu5282.c
+++ b/board/BuS/eb_cpu5282/eb_cpu5282.c
@@ -11,6 +11,7 @@
#include <command.h>
#include "asm/m5282.h"
#include <bmp_layout.h>
+#include <env.h>
#include <status_led.h>
#include <bus_vcxk.h>
diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c
index 3818e37..946e20a 100644
--- a/board/CZ.NIC/turris_mox/turris_mox.c
+++ b/board/CZ.NIC/turris_mox/turris_mox.c
@@ -8,13 +8,13 @@
#include <asm/io.h>
#include <dm.h>
#include <clk.h>
+#include <env.h>
#include <spi.h>
#include <mvebu/comphy.h>
#include <miiphy.h>
#include <linux/string.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
-#include <environment.h>
#include "mox_sp.h"
diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c
index ad6e290..1d8d08a 100644
--- a/board/CZ.NIC/turris_omnia/turris_omnia.c
+++ b/board/CZ.NIC/turris_omnia/turris_omnia.c
@@ -8,7 +8,7 @@
*/
#include <common.h>
-#include <environment.h>
+#include <env.h>
#include <i2c.h>
#include <miiphy.h>
#include <netdev.h>
@@ -340,7 +340,8 @@
"i2c mw 0x2a.1 0x4 0x1c 1; " \
"mw.l 0x01000000 0x00ff000c; " \
"i2c write 0x01000000 0x2a.1 0x5 4 -s; " \
- "setenv bootargs \"$bootargs omniarescue=$omnia_reset\"; " \
+ "setenv bootargs \"earlyprintk console=ttyS0,115200" \
+ " omniarescue=$omnia_reset\"; " \
"sf probe; " \
"sf read 0x1000000 0x100000 0x700000; " \
"bootm 0x1000000; " \
@@ -412,6 +413,7 @@
set_regdomain();
handle_reset_button();
#endif
+ pci_init();
return 0;
}
@@ -514,11 +516,6 @@
mac[5] = mac1[3];
if (is_valid_ethaddr(mac))
- eth_env_set_enetaddr("ethaddr", mac);
-
- increment_mac(mac);
-
- if (is_valid_ethaddr(mac))
eth_env_set_enetaddr("eth1addr", mac);
increment_mac(mac);
@@ -526,6 +523,11 @@
if (is_valid_ethaddr(mac))
eth_env_set_enetaddr("eth2addr", mac);
+ increment_mac(mac);
+
+ if (is_valid_ethaddr(mac))
+ eth_env_set_enetaddr("ethaddr", mac);
+
out:
return 0;
}
diff --git a/board/CarMediaLab/flea3/flea3.c b/board/CarMediaLab/flea3/flea3.c
index 9eec1b7..be0bc22 100644
--- a/board/CarMediaLab/flea3/flea3.c
+++ b/board/CarMediaLab/flea3/flea3.c
@@ -9,6 +9,7 @@
#include <common.h>
#include <asm/io.h>
+#include <env.h>
#include <linux/errno.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
diff --git a/board/LaCie/net2big_v2/net2big_v2.c b/board/LaCie/net2big_v2/net2big_v2.c
index fb08e50..686608d 100644
--- a/board/LaCie/net2big_v2/net2big_v2.c
+++ b/board/LaCie/net2big_v2/net2big_v2.c
@@ -10,7 +10,7 @@
#include <common.h>
#include <command.h>
-#include <environment.h>
+#include <env.h>
#include <i2c.h>
#include <asm/mach-types.h>
#include <asm/arch/cpu.h>
diff --git a/board/LaCie/netspace_v2/netspace_v2.c b/board/LaCie/netspace_v2/netspace_v2.c
index 453c0dd..bd7ab22 100644
--- a/board/LaCie/netspace_v2/netspace_v2.c
+++ b/board/LaCie/netspace_v2/netspace_v2.c
@@ -10,7 +10,7 @@
#include <common.h>
#include <command.h>
-#include <environment.h>
+#include <env.h>
#include <asm/mach-types.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
diff --git a/board/Synology/ds414/cmd_syno.c b/board/Synology/ds414/cmd_syno.c
index 59e6fe0..777948f 100644
--- a/board/Synology/ds414/cmd_syno.c
+++ b/board/Synology/ds414/cmd_syno.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <div64.h>
+#include <env.h>
#include <spi.h>
#include <spi_flash.h>
#include <linux/mtd/mtd.h>
diff --git a/board/advantech/dms-ba16/dms-ba16.c b/board/advantech/dms-ba16/dms-ba16.c
index 0962043..2eccc05 100644
--- a/board/advantech/dms-ba16/dms-ba16.c
+++ b/board/advantech/dms-ba16/dms-ba16.c
@@ -16,7 +16,7 @@
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/video.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/mxc_hdmi.h>
@@ -221,7 +221,7 @@
imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg usdhc_cfg[3] = {
{USDHC2_BASE_ADDR},
{USDHC3_BASE_ADDR},
diff --git a/board/alliedtelesis/x530/x530.c b/board/alliedtelesis/x530/x530.c
index 97dbed7..e0fa806 100644
--- a/board/alliedtelesis/x530/x530.c
+++ b/board/alliedtelesis/x530/x530.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <command.h>
#include <dm.h>
+#include <env.h>
#include <i2c.h>
#include <wdt.h>
#include <asm/gpio.h>
diff --git a/board/amarula/vyasa-rk3288/vyasa-rk3288.c b/board/amarula/vyasa-rk3288/vyasa-rk3288.c
index 2b509f5..baf197c 100644
--- a/board/amarula/vyasa-rk3288/vyasa-rk3288.c
+++ b/board/amarula/vyasa-rk3288/vyasa-rk3288.c
@@ -6,14 +6,6 @@
#include <common.h>
#ifndef CONFIG_TPL_BUILD
-#include <spl.h>
-
-void board_boot_order(u32 *spl_boot_list)
-{
- /* eMMC prior to sdcard. */
- spl_boot_list[0] = BOOT_DEVICE_MMC2;
- spl_boot_list[1] = BOOT_DEVICE_MMC1;
-}
int spl_start_uboot(void)
{
diff --git a/board/amazon/kc1/kc1.c b/board/amazon/kc1/kc1.c
index 031fd11..9034c4f 100644
--- a/board/amazon/kc1/kc1.c
+++ b/board/amazon/kc1/kc1.c
@@ -7,6 +7,7 @@
#include <config.h>
#include <common.h>
+#include <env.h>
#include <linux/ctype.h>
#include <linux/usb/musb.h>
#include <asm/omap_musb.h>
diff --git a/board/amlogic/p200/p200.c b/board/amlogic/p200/p200.c
index 62f0f4c..41d331d 100644
--- a/board/amlogic/p200/p200.c
+++ b/board/amlogic/p200/p200.c
@@ -5,7 +5,7 @@
#include <common.h>
#include <dm.h>
-#include <environment.h>
+#include <env.h>
#include <asm/io.h>
#include <asm/arch/gx.h>
#include <asm/arch/sm.h>
diff --git a/board/amlogic/p201/p201.c b/board/amlogic/p201/p201.c
index ef0c65c..e46fcaea 100644
--- a/board/amlogic/p201/p201.c
+++ b/board/amlogic/p201/p201.c
@@ -5,7 +5,7 @@
#include <common.h>
#include <dm.h>
-#include <environment.h>
+#include <env.h>
#include <asm/io.h>
#include <asm/arch/gx.h>
#include <asm/arch/sm.h>
diff --git a/board/amlogic/p212/README.khadas-vim b/board/amlogic/p212/README.khadas-vim
index b194236..a2c7606 100644
--- a/board/amlogic/p212/README.khadas-vim
+++ b/board/amlogic/p212/README.khadas-vim
@@ -50,7 +50,7 @@
> git clone https://github.com/khadas/u-boot -b Vim vim-u-boot
> cd vim-u-boot
> make kvim_defconfig
- > make
+ > make CROSS_COMPILE=aarch64-none-elf-
> export FIPDIR=$PWD/fip
Go back to mainline U-Boot source tree then :
diff --git a/board/amlogic/p212/p212.c b/board/amlogic/p212/p212.c
index 546c4d9..094ab54 100644
--- a/board/amlogic/p212/p212.c
+++ b/board/amlogic/p212/p212.c
@@ -6,7 +6,7 @@
#include <common.h>
#include <dm.h>
-#include <environment.h>
+#include <env.h>
#include <asm/io.h>
#include <asm/arch/gx.h>
#include <asm/arch/sm.h>
@@ -32,6 +32,8 @@
mac_addr, EFUSE_MAC_SIZE);
if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
eth_env_set_enetaddr("ethaddr", mac_addr);
+ else
+ meson_generate_serial_ethaddr();
}
if (!env_get("serial#")) {
diff --git a/board/amlogic/q200/q200.c b/board/amlogic/q200/q200.c
index de97d6a..f1faa74 100644
--- a/board/amlogic/q200/q200.c
+++ b/board/amlogic/q200/q200.c
@@ -6,7 +6,7 @@
#include <common.h>
#include <dm.h>
-#include <environment.h>
+#include <env.h>
#include <asm/io.h>
#include <asm/arch/gx.h>
#include <asm/arch/mem.h>
@@ -31,6 +31,8 @@
mac_addr, EFUSE_MAC_SIZE);
if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
eth_env_set_enetaddr("ethaddr", mac_addr);
+ else
+ meson_generate_serial_ethaddr();
}
if (!env_get("serial#")) {
diff --git a/board/amlogic/s400/s400.c b/board/amlogic/s400/s400.c
index 02a0e92..bdb4eca 100644
--- a/board/amlogic/s400/s400.c
+++ b/board/amlogic/s400/s400.c
@@ -6,7 +6,6 @@
#include <common.h>
#include <dm.h>
-#include <environment.h>
#include <asm/io.h>
#include <asm/arch/axg.h>
#include <asm/arch/sm.h>
diff --git a/board/amlogic/sei510/MAINTAINERS b/board/amlogic/sei510/MAINTAINERS
new file mode 100644
index 0000000..8dc655e
--- /dev/null
+++ b/board/amlogic/sei510/MAINTAINERS
@@ -0,0 +1,7 @@
+SEI510
+M: Neil Armstrong <narmstrong@baylibre.com>
+S: Maintained
+L: u-boot-amlogic@groups.io
+F: board/amlogic/sei510/
+F: configs/sei510_defconfig
+F: include/configs/sei510.h
diff --git a/board/amlogic/sei510/Makefile b/board/amlogic/sei510/Makefile
new file mode 100644
index 0000000..03399a3
--- /dev/null
+++ b/board/amlogic/sei510/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2016 BayLibre, SAS
+# Author: Neil Armstrong <narmstrong@baylibre.com>
+
+obj-y := sei510.o
diff --git a/board/amlogic/sei510/README b/board/amlogic/sei510/README
new file mode 100644
index 0000000..e47ebc7
--- /dev/null
+++ b/board/amlogic/sei510/README
@@ -0,0 +1,123 @@
+U-Boot for Amlogic SEI510
+=======================
+
+SEI510 is a customer board manufactured by SEI Robotics with the following
+specifications:
+
+ - Amlogic S905X2 ARM Cortex-A53 quad-core SoC
+ - 2GB DDR4 SDRAM
+ - 10/100 Ethernet (Internal PHY)
+ - 1 x USB 3.0 Host
+ - eMMC
+ - SDcard
+ - Infrared receiver
+ - SDIO WiFi Module
+
+Currently the u-boot port supports the following devices:
+ - serial
+ - Ethernet
+ - Regulators
+ - Clock controller
+
+u-boot compilation
+==================
+
+ > export ARCH=arm
+ > export CROSS_COMPILE=aarch64-none-elf-
+ > make sei510_defconfig
+ > make
+
+Image creation
+==============
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+the git tree published by the board vendor:
+
+ > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+ > git clone https://github.com/BayLibre/u-boot.git -b buildroot-openlinux-20180418 amlogic-u-boot
+ > cd amlogic-u-boot
+ > make g12a_u200_v1_defconfig
+ > make
+ > export UBOOTDIR=$PWD
+
+Download the latest Amlogic Buildroot package, and extract it :
+ > wget http://openlinux2.amlogic.com:8000/ARM/filesystem/Linux_BSP/buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz
+ > tar xfz buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz buildroot_openlinux_kernel_4.9_fbdev_20180706/bootloader
+ > export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180706
+ > export FIPDIR=$BRDIR/bootloader/uboot-repo/fip
+
+Go back to mainline U-Boot source tree then :
+ > mkdir fip
+
+ > wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh
+ > cp $UBOOTDIR/build/scp_task/bl301.bin fip/
+ > cp $UBOOTDIR/build/board/amlogic/g12a_u200_v1/firmware/acs.bin fip/
+ > cp $BRDIR/bootloader/uboot-repo/bl2/bin/g12a/bl2.bin fip/
+ > cp $BRDIR/bootloader/uboot-repo/bl30/bin/g12a/bl30.bin fip/
+ > cp $BRDIR/bootloader/uboot-repo/bl31_1.3/bin/g12a/bl31.img fip/
+ > cp $FIPDIR/g12a/ddr3_1d.fw fip/
+ > cp $FIPDIR/g12a/ddr4_1d.fw fip/
+ > cp $FIPDIR/g12a/ddr4_2d.fw fip/
+ > cp $FIPDIR/g12a/diag_lpddr4.fw fip/
+ > cp $FIPDIR/g12a/lpddr4_1d.fw fip/
+ > cp $FIPDIR/g12a/lpddr4_2d.fw fip/
+ > cp $FIPDIR/g12a/piei.fw fip/
+ > cp u-boot.bin fip/bl33.bin
+
+ > sh fip/blx_fix.sh \
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
+
+ > sh fip/blx_fix.sh \
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
+ > $FIPDIR/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \
+ --output fip/bl30_new.bin.g12a.enc \
+ --level v3
+ > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
+ > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
+ > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33
+ > $FIPDIR/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \
+ --output fip/bl2.n.bin.sig
+ > $FIPDIR/g12a/aml_encrypt_g12a --bootmk \
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc \
+ --ddrfw1 fip/ddr4_1d.fw \
+ --ddrfw2 fip/ddr4_2d.fw \
+ --ddrfw3 fip/ddr3_1d.fw \
+ --ddrfw4 fip/piei.fw \
+ --ddrfw5 fip/lpddr4_1d.fw \
+ --ddrfw6 fip/lpddr4_2d.fw \
+ --ddrfw7 fip/diag_lpddr4.fw \
+ --level v3
+
+and then write the image to SD with:
+
+ > DEV=/dev/your_sd_device
+ > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
diff --git a/board/amlogic/sei510/sei510.c b/board/amlogic/sei510/sei510.c
new file mode 100644
index 0000000..5de610d
--- /dev/null
+++ b/board/amlogic/sei510/sei510.c
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <env_internal.h>
+#include <asm/io.h>
+#include <asm/arch/axg.h>
+#include <asm/arch/sm.h>
+#include <asm/arch/eth.h>
+#include <asm/arch/mem.h>
+
+int misc_init_r(void)
+{
+ meson_eth_init(PHY_INTERFACE_MODE_RMII,
+ MESON_USE_INTERNAL_RMII_PHY);
+
+ meson_generate_serial_ethaddr();
+
+ env_set("serial#", "AMLG12ASEI510");
+
+ return 0;
+}
diff --git a/board/amlogic/u200/u200.c b/board/amlogic/u200/u200.c
index 94ee3ce..69fd29d 100644
--- a/board/amlogic/u200/u200.c
+++ b/board/amlogic/u200/u200.c
@@ -6,7 +6,6 @@
#include <common.h>
#include <dm.h>
-#include <environment.h>
#include <asm/io.h>
#include <asm/arch/axg.h>
#include <asm/arch/sm.h>
diff --git a/board/amlogic/w400/MAINTAINERS b/board/amlogic/w400/MAINTAINERS
new file mode 100644
index 0000000..6e68fa7
--- /dev/null
+++ b/board/amlogic/w400/MAINTAINERS
@@ -0,0 +1,6 @@
+W400
+M: Neil Armstrong <narmstrong@baylibre.com>
+S: Maintained
+L: u-boot-amlogic@groups.io
+F: board/amlogic/w400/
+F: configs/odroid-n2_defconfig
diff --git a/board/amlogic/w400/Makefile b/board/amlogic/w400/Makefile
new file mode 100644
index 0000000..fac4a73
--- /dev/null
+++ b/board/amlogic/w400/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 BayLibre, SAS
+# Author: Neil Armstrong <narmstrong@baylibre.com>
+
+obj-y := w400.o
diff --git a/board/amlogic/w400/README.odroid-n2 b/board/amlogic/w400/README.odroid-n2
new file mode 100644
index 0000000..a8f2c3d
--- /dev/null
+++ b/board/amlogic/w400/README.odroid-n2
@@ -0,0 +1,130 @@
+U-Boot for ODROID-N2
+====================
+
+ODROID-N2 is a single board computer manufactured by Hardkernel
+Co. Ltd with the following specifications:
+
+ - Amlogic S922X ARM Cortex-A53 dual-core + Cortex-A73 quad-core SoC
+ - 4GB DDR4 SDRAM
+ - Gigabit Ethernet
+ - HDMI 2.1 4K/60Hz display
+ - 40-pin GPIO header
+ - 4 x USB 3.0 Host, 1 x USB OTG
+ - eMMC, microSD
+ - Infrared receiver
+
+Schematics are available on the manufacturer website.
+
+Currently the u-boot port supports the following devices:
+ - serial
+ - eMMC, microSD
+ - Ethernet
+ - I2C
+ - Regulators
+ - Reset controller
+ - Clock controller
+ - ADC
+
+u-boot compilation
+==================
+
+ > export ARCH=arm
+ > export CROSS_COMPILE=aarch64-none-elf-
+ > make odroid-n2_defconfig
+ > make
+
+Image creation
+==============
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+the git tree published by the board vendor:
+
+ > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+
+ > DIR=odroid-n2
+ > git clone --depth 1 \
+ https://github.com/hardkernel/u-boot.git -b odroidn2-v2015.01 \
+ $DIR
+
+ > cd odroid-n2
+ > make odroidn2_defconfig
+ > make
+ > export UBOOTDIR=$PWD
+
+ Go back to mainline U-Boot source tree then :
+ > mkdir fip
+
+ > wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh
+ > cp $UBOOTDIR/build/scp_task/bl301.bin fip/
+ > cp $UBOOTDIR/build/board/hardkernel/odroidn2/firmware/acs.bin fip/
+ > cp $UBOOTDIR/fip/g12b/bl2.bin fip/
+ > cp $UBOOTDIR/fip/g12b/bl30.bin fip/
+ > cp $UBOOTDIR/fip/g12b/bl31.img fip/
+ > cp $UBOOTDIR/fip/g12b/ddr3_1d.fw fip/
+ > cp $UBOOTDIR/fip/g12b/ddr4_1d.fw fip/
+ > cp $UBOOTDIR/fip/g12b/ddr4_2d.fw fip/
+ > cp $UBOOTDIR/fip/g12b/diag_lpddr4.fw fip/
+ > cp $UBOOTDIR/fip/g12b/lpddr4_1d.fw fip/
+ > cp $UBOOTDIR/fip/g12b/lpddr4_2d.fw fip/
+ > cp $UBOOTDIR/fip/g12b/piei.fw fip/
+ > cp $UBOOTDIR/fip/g12b/aml_ddr.fw fip/
+ > cp u-boot.bin fip/bl33.bin
+
+ > sh fip/blx_fix.sh \
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
+
+ > sh fip/blx_fix.sh \
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
+ > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \
+ --output fip/bl30_new.bin.g12a.enc \
+ --level v3
+ > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
+ > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl31.img \
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
+ > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33 --compress lz4
+ > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
+ --output fip/bl2.n.bin.sig
+ > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bootmk \
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc \
+ --ddrfw1 fip/ddr4_1d.fw \
+ --ddrfw2 fip/ddr4_2d.fw \
+ --ddrfw3 fip/ddr3_1d.fw \
+ --ddrfw4 fip/piei.fw \
+ --ddrfw5 fip/lpddr4_1d.fw \
+ --ddrfw6 fip/lpddr4_2d.fw \
+ --ddrfw7 fip/diag_lpddr4.fw \
+ --ddrfw8 fip/aml_ddr.fw \
+ --level v3
+
+and then write the image to SD with:
+
+ > DEV=/dev/your_sd_device
+ > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
diff --git a/board/amlogic/w400/README.w400 b/board/amlogic/w400/README.w400
new file mode 100644
index 0000000..25b786d
--- /dev/null
+++ b/board/amlogic/w400/README.w400
@@ -0,0 +1,130 @@
+U-Boot for Amlogic W400
+=======================
+
+U200 is a reference board manufactured by Amlogic with the following
+specifications:
+
+ - Amlogic S922X ARM Cortex-A53 dual-core + Cortex-A73 quad-core SoC
+ - 2GB DDR4 SDRAM
+ - 10/100 Ethernet (Internal PHY)
+ - 1 x USB 3.0 Host
+ - eMMC
+ - SDcard
+ - Infrared receiver
+ - SDIO WiFi Module
+ - MIPI DSI Connector
+ - Audio HAT Connector
+ - PCI-E M.2 Connector
+
+Schematics are available from Amlogic on demand.
+
+Currently the u-boot port supports the following devices:
+ - serial
+ - Ethernet
+ - Regulators
+ - Clock controller
+
+u-boot compilation
+==================
+
+ > export ARCH=arm
+ > export CROSS_COMPILE=aarch64-none-elf-
+ > make w400_defconfig
+ > make
+
+Image creation
+==============
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+the git tree published by the board vendor:
+
+ > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+ > git clone https://github.com/BayLibre/u-boot.git -b buildroot-openlinux-20180418 amlogic-u-boot
+ > cd amlogic-u-boot
+ > make g12b_w400_v1_defconfig
+ > make
+ > export UBOOTDIR=$PWD
+
+Download the latest Amlogic Buildroot package, and extract it :
+ > wget http://openlinux2.amlogic.com:8000/ARM/filesystem/Linux_BSP/buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz
+ > tar xfz buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz buildroot_openlinux_kernel_4.9_fbdev_20180706/bootloader
+ > export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180706
+ > export FIPDIR=$BRDIR/bootloader/uboot-repo/fip
+
+Go back to mainline U-Boot source tree then :
+ > mkdir fip
+
+ > wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh
+ > cp $UBOOTDIR/build/scp_task/bl301.bin fip/
+ > cp $UBOOTDIR/build/board/amlogic/g12b_w400_v1/firmware/acs.bin fip/
+ > cp $BRDIR/bootloader/uboot-repo/bl2/bin/g12b/bl2.bin fip/
+ > cp $BRDIR/bootloader/uboot-repo/bl30/bin/g12b/bl30.bin fip/
+ > cp $BRDIR/bootloader/uboot-repo/bl31_1.3/bin/g12b/bl31.img fip/
+ > cp $FIPDIR/g12b/ddr3_1d.fw fip/
+ > cp $FIPDIR/g12b/ddr4_1d.fw fip/
+ > cp $FIPDIR/g12b/ddr4_2d.fw fip/
+ > cp $FIPDIR/g12b/diag_lpddr4.fw fip/
+ > cp $FIPDIR/g12b/lpddr4_1d.fw fip/
+ > cp $FIPDIR/g12b/lpddr4_2d.fw fip/
+ > cp $FIPDIR/g12b/piei.fw fip/
+ > cp $FIPDIR/g12b/aml_ddr.fw fip/
+ > cp u-boot.bin fip/bl33.bin
+
+ > sh fip/blx_fix.sh \
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
+
+ > sh fip/blx_fix.sh \
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
+ > $FIPDIR/g12b/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \
+ --output fip/bl30_new.bin.g12a.enc \
+ --level v3
+ > $FIPDIR/g12b/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
+ > $FIPDIR/g12b/aml_encrypt_g12b --bl3sig --input fip/bl31.img \
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
+ > $FIPDIR/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33
+ > $FIPDIR/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
+ --output fip/bl2.n.bin.sig
+ > $FIPDIR/g12b/aml_encrypt_g12b --bootmk \
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc \
+ --ddrfw1 fip/ddr4_1d.fw \
+ --ddrfw2 fip/ddr4_2d.fw \
+ --ddrfw3 fip/ddr3_1d.fw \
+ --ddrfw4 fip/piei.fw \
+ --ddrfw5 fip/lpddr4_1d.fw \
+ --ddrfw6 fip/lpddr4_2d.fw \
+ --ddrfw7 fip/diag_lpddr4.fw \
+ --ddrfw8 fip/aml_ddr.fw \
+ --level v3
+
+and then write the image to SD with:
+
+ > DEV=/dev/your_sd_device
+ > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
diff --git a/board/amlogic/w400/w400.c b/board/amlogic/w400/w400.c
new file mode 100644
index 0000000..e60dc3a
--- /dev/null
+++ b/board/amlogic/w400/w400.c
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <env_internal.h>
+#include <asm/io.h>
+#include <asm/arch/eth.h>
+
+int misc_init_r(void)
+{
+ meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
+
+ return 0;
+}
diff --git a/board/aristainetos/aristainetos-v1.c b/board/aristainetos/aristainetos-v1.c
index 5231c2e..de1a018 100644
--- a/board/aristainetos/aristainetos-v1.c
+++ b/board/aristainetos/aristainetos-v1.c
@@ -20,7 +20,7 @@
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/video.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/mxc_hdmi.h>
diff --git a/board/aristainetos/aristainetos-v2.c b/board/aristainetos/aristainetos-v2.c
index 63b1057..c0a2e41 100644
--- a/board/aristainetos/aristainetos-v2.c
+++ b/board/aristainetos/aristainetos-v2.c
@@ -13,6 +13,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
+#include <env.h>
#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
@@ -20,7 +21,7 @@
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/video.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/mxc_hdmi.h>
diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c
index c88b9fc..9f744b3 100644
--- a/board/aristainetos/aristainetos.c
+++ b/board/aristainetos/aristainetos.c
@@ -20,7 +20,7 @@
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/video.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/mxc_hdmi.h>
@@ -107,7 +107,7 @@
return 0;
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC1_BASE_ADDR},
{USDHC2_BASE_ADDR},
diff --git a/board/armadeus/apf27/apf27.c b/board/armadeus/apf27/apf27.c
index bf2586d..20be0c3 100644
--- a/board/armadeus/apf27/apf27.c
+++ b/board/armadeus/apf27/apf27.c
@@ -7,7 +7,6 @@
*/
#include <common.h>
-#include <environment.h>
#include <jffs2/jffs2.h>
#include <nand.h>
#include <netdev.h>
diff --git a/board/armadeus/opos6uldev/board.c b/board/armadeus/opos6uldev/board.c
index aed334f..cbf40d5 100644
--- a/board/armadeus/opos6uldev/board.c
+++ b/board/armadeus/opos6uldev/board.c
@@ -70,27 +70,6 @@
}
#endif
-#ifdef CONFIG_USB_EHCI_MX6
-#define USB_OTHERREGS_OFFSET 0x800
-#define UCTRL_PWR_POL (1 << 9)
-
-int board_ehci_hcd_init(int port)
-{
- u32 *usbnc_usb_ctrl;
-
- if (port > 1)
- return -EINVAL;
-
- usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
- port * 4);
-
- /* Set Power polarity */
- setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
-
- return 0;
-}
-#endif
-
int opos6ul_board_late_init(void)
{
#ifdef CONFIG_VIDEO_MXS
diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c
index 69d92a3..0a2baa7 100644
--- a/board/armltd/integrator/integrator.c
+++ b/board/armltd/integrator/integrator.c
@@ -18,6 +18,7 @@
#include <common.h>
#include <dm.h>
+#include <env.h>
#include <netdev.h>
#include <asm/io.h>
#include <dm/platform_data/serial_pl01x.h>
diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig
index e05f353..9014418 100644
--- a/board/armltd/vexpress64/Kconfig
+++ b/board/armltd/vexpress64/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_VEXPRESS64_BASE_FVP || TARGET_VEXPRESS64_JUNO || TARGET_VEXPRESS64_BASE_FVP_DRAM
+if TARGET_VEXPRESS64_BASE_FVP || TARGET_VEXPRESS64_JUNO
config SYS_BOARD
default "vexpress64"
diff --git a/board/armltd/vexpress64/MAINTAINERS b/board/armltd/vexpress64/MAINTAINERS
index 15b0a08..0ba044d 100644
--- a/board/armltd/vexpress64/MAINTAINERS
+++ b/board/armltd/vexpress64/MAINTAINERS
@@ -10,11 +10,6 @@
S: Maintained
F: configs/vexpress_aemv8a_semi_defconfig
-VEXPRESS_AEMV8A_DRAM BOARD
-M: Ryan Harkin <ryan.harkin@linaro.org>
-S: Maintained
-F: configs/vexpress_aemv8a_dram_defconfig
-
JUNO DEVELOPMENT PLATFORM BOARD
M: Linus Walleij <linus.walleij@linaro.org>
S: Maintained
diff --git a/board/atmel/common/board.c b/board/atmel/common/board.c
index 20c3b8c..c41706c 100644
--- a/board/atmel/common/board.c
+++ b/board/atmel/common/board.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
+#include <env.h>
#include <w1.h>
#include <w1-eeprom.h>
#include <dm/device-internal.h>
diff --git a/board/atmel/common/mac_eeprom.c b/board/atmel/common/mac_eeprom.c
index 7ff1ec7..83a7778 100644
--- a/board/atmel/common/mac_eeprom.c
+++ b/board/atmel/common/mac_eeprom.c
@@ -6,7 +6,7 @@
#include <common.h>
#include <dm.h>
-#include <environment.h>
+#include <env.h>
#include <i2c_eeprom.h>
#include <netdev.h>
diff --git a/board/atmel/sama5d27_som1_ek/MAINTAINERS b/board/atmel/sama5d27_som1_ek/MAINTAINERS
index 74434e9..f2d2f49 100644
--- a/board/atmel/sama5d27_som1_ek/MAINTAINERS
+++ b/board/atmel/sama5d27_som1_ek/MAINTAINERS
@@ -5,3 +5,4 @@
F: include/configs/sama5d27_som1_ek.h
F: configs/sama5d27_som1_ek_mmc_defconfig
F: configs/sama5d27_som1_ek_mmc1_defconfig
+F: configs/sama5d27_som1_ek_qspiflash_defconfig
diff --git a/board/atmel/sama5d2_xplained/MAINTAINERS b/board/atmel/sama5d2_xplained/MAINTAINERS
index 08de5bb..88e327f 100644
--- a/board/atmel/sama5d2_xplained/MAINTAINERS
+++ b/board/atmel/sama5d2_xplained/MAINTAINERS
@@ -6,3 +6,4 @@
F: configs/sama5d2_xplained_mmc_defconfig
F: configs/sama5d2_xplained_spiflash_defconfig
F: configs/sama5d2_xplained_emmc_defconfig
+F: configs/sama5d2_xplained_qspiflash_defconfig
diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c
index e373f45..acf6148 100644
--- a/board/atmel/sama5d3xek/sama5d3xek.c
+++ b/board/atmel/sama5d3xek/sama5d3xek.c
@@ -12,6 +12,7 @@
#include <asm/arch/gpio.h>
#include <asm/arch/clk.h>
#include <debug_uart.h>
+#include <env.h>
#include <linux/ctype.h>
#include <phy.h>
#include <micrel.h>
diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c
index 2d73441..36f3708 100644
--- a/board/bachmann/ot1200/ot1200.c
+++ b/board/bachmann/ot1200/ot1200.c
@@ -9,6 +9,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
+#include <env.h>
#include <malloc.h>
#include <asm/arch/mx6-pins.h>
#include <asm/mach-imx/iomux-v3.h>
@@ -18,7 +19,7 @@
#include <asm/arch/crm_regs.h>
#include <asm/arch/sys_proto.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <netdev.h>
#include <i2c.h>
#include <pca953x.h>
diff --git a/board/barco/platinum/platinum.c b/board/barco/platinum/platinum.c
index b484ec2..1c6514a 100644
--- a/board/barco/platinum/platinum.c
+++ b/board/barco/platinum/platinum.c
@@ -6,7 +6,7 @@
#include <common.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/io.h>
diff --git a/board/barco/titanium/titanium.c b/board/barco/titanium/titanium.c
index e9955c8..407bfe9 100644
--- a/board/barco/titanium/titanium.c
+++ b/board/barco/titanium/titanium.c
@@ -16,7 +16,7 @@
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/boot_mode.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <micrel.h>
#include <miiphy.h>
#include <netdev.h>
@@ -215,7 +215,7 @@
#endif
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg usdhc_cfg[1] = {
{ USDHC3_BASE_ADDR },
};
diff --git a/board/birdland/bav335x/board.c b/board/birdland/bav335x/board.c
index b951860..8811583a 100644
--- a/board/birdland/bav335x/board.c
+++ b/board/birdland/bav335x/board.c
@@ -8,6 +8,7 @@
*/
#include <common.h>
+#include <env.h>
#include <errno.h>
#include <spl.h>
#include <asm/arch/cpu.h>
@@ -27,9 +28,8 @@
#include <cpsw.h>
#include <power/tps65217.h>
#include <power/tps65910.h>
-#include <environment.h>
+#include <env_internal.h>
#include <watchdog.h>
-#include <environment.h>
#include "board.h"
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/bluegiga/apx4devkit/apx4devkit.c b/board/bluegiga/apx4devkit/apx4devkit.c
index 9aa87f5..9268aa0 100644
--- a/board/bluegiga/apx4devkit/apx4devkit.c
+++ b/board/bluegiga/apx4devkit/apx4devkit.c
@@ -21,6 +21,7 @@
#include <asm/arch/iomux-mx28.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
+#include <env.h>
#include <linux/mii.h>
#include <miiphy.h>
#include <netdev.h>
diff --git a/board/bluewater/gurnard/gurnard.c b/board/bluewater/gurnard/gurnard.c
index 3cda2fa..48e31d9 100644
--- a/board/bluewater/gurnard/gurnard.c
+++ b/board/bluewater/gurnard/gurnard.c
@@ -12,6 +12,7 @@
#include <atmel_lcdc.h>
#include <atmel_mci.h>
#include <dm.h>
+#include <env.h>
#include <lcd.h>
#include <net.h>
#ifndef CONFIG_DM_ETH
diff --git a/board/bosch/guardian/board.c b/board/bosch/guardian/board.c
index 86ab180..ec0c4a17 100644
--- a/board/bosch/guardian/board.c
+++ b/board/bosch/guardian/board.c
@@ -11,8 +11,7 @@
#include <common.h>
#include <cpsw.h>
#include <dm.h>
-#include <environment.h>
-#include <environment.h>
+#include <env_internal.h>
#include <errno.h>
#include <i2c.h>
#include <miiphy.h>
diff --git a/board/bosch/shc/board.c b/board/bosch/shc/board.c
index feed63b..a96fdef 100644
--- a/board/bosch/shc/board.c
+++ b/board/bosch/shc/board.c
@@ -12,6 +12,7 @@
*/
#include <common.h>
+#include <env.h>
#include <errno.h>
#include <spl.h>
#include <asm/arch/cpu.h>
@@ -30,9 +31,8 @@
#include <miiphy.h>
#include <cpsw.h>
#include <power/tps65217.h>
-#include <environment.h>
+#include <env_internal.h>
#include <watchdog.h>
-#include <environment.h>
#include "mmc.h"
#include "board.h"
diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c
index 84d7cee..26af3f7 100644
--- a/board/boundary/nitrogen6x/nitrogen6x.c
+++ b/board/boundary/nitrogen6x/nitrogen6x.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
+#include <env.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
@@ -21,7 +22,7 @@
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/video.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <micrel.h>
#include <miiphy.h>
#include <netdev.h>
@@ -283,7 +284,7 @@
#endif
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
static struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC3_BASE_ADDR},
{USDHC4_BASE_ADDR},
diff --git a/board/broadcom/bcm23550_w1d/bcm23550_w1d.c b/board/broadcom/bcm23550_w1d/bcm23550_w1d.c
index 72a32a2..ce9f049 100644
--- a/board/broadcom/bcm23550_w1d/bcm23550_w1d.c
+++ b/board/broadcom/bcm23550_w1d/bcm23550_w1d.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/mach-types.h>
+#include <env.h>
#include <mmc.h>
#include <asm/kona-common/kona_sdhci.h>
#include <asm/kona-common/clk.h>
diff --git a/board/broadcom/bcm28155_ap/bcm28155_ap.c b/board/broadcom/bcm28155_ap/bcm28155_ap.c
index 6faeb6a..8761638 100644
--- a/board/broadcom/bcm28155_ap/bcm28155_ap.c
+++ b/board/broadcom/bcm28155_ap/bcm28155_ap.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/mach-types.h>
+#include <env.h>
#include <mmc.h>
#include <asm/kona-common/kona_sdhci.h>
#include <asm/kona-common/clk.h>
diff --git a/board/broadcom/bcmstb/bcmstb.c b/board/broadcom/bcmstb/bcmstb.c
index 7f8e0f9..5fc2c05 100644
--- a/board/broadcom/bcmstb/bcmstb.c
+++ b/board/broadcom/bcmstb/bcmstb.c
@@ -8,6 +8,7 @@
#include <linux/types.h>
#include <common.h>
+#include <env.h>
#include <asm/io.h>
#include <asm/bootm.h>
#include <mach/timer.h>
diff --git a/board/buffalo/lsxl/lsxl.c b/board/buffalo/lsxl/lsxl.c
index bf69a74..95d3a5e 100644
--- a/board/buffalo/lsxl/lsxl.c
+++ b/board/buffalo/lsxl/lsxl.c
@@ -8,7 +8,8 @@
*/
#include <common.h>
-#include <environment.h>
+#include <env.h>
+#include <env_internal.h>
#include <net.h>
#include <malloc.h>
#include <netdev.h>
diff --git a/board/cadence/xtfpga/xtfpga.c b/board/cadence/xtfpga/xtfpga.c
index bdda931..2566116 100644
--- a/board/cadence/xtfpga/xtfpga.c
+++ b/board/cadence/xtfpga/xtfpga.c
@@ -8,6 +8,7 @@
#include <command.h>
#include <dm.h>
#include <dm/platform_data/net_ethoc.h>
+#include <env.h>
#include <linux/ctype.h>
#include <linux/string.h>
#include <linux/stringify.h>
diff --git a/board/ccv/xpress/xpress.c b/board/ccv/xpress/xpress.c
index dcf5e144..05286e6 100644
--- a/board/ccv/xpress/xpress.c
+++ b/board/ccv/xpress/xpress.c
@@ -16,7 +16,8 @@
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/io.h>
#include <common.h>
-#include <fsl_esdhc.h>
+#include <env.h>
+#include <fsl_esdhc_imx.h>
#include <i2c.h>
#include <miiphy.h>
#include <mmc.h>
diff --git a/board/chipspark/popmetal_rk3288/popmetal-rk3288.c b/board/chipspark/popmetal_rk3288/popmetal-rk3288.c
index 355c78b..47b921a 100644
--- a/board/chipspark/popmetal_rk3288/popmetal-rk3288.c
+++ b/board/chipspark/popmetal_rk3288/popmetal-rk3288.c
@@ -4,19 +4,11 @@
*/
#include <common.h>
-#include <spl.h>
#include <asm/gpio.h>
-void board_boot_order(u32 *spl_boot_list)
-{
- /* eMMC prior to sdcard */
- spl_boot_list[0] = BOOT_DEVICE_MMC2;
- spl_boot_list[1] = BOOT_DEVICE_MMC1;
-}
-
#define GPIO7A3_HUB_RST 227
-int rk_board_late_init(void)
+int rk3288_board_late_init(void)
{
int ret;
diff --git a/board/compulab/cl-som-imx7/cl-som-imx7.c b/board/compulab/cl-som-imx7/cl-som-imx7.c
index 1bc33b0..395d5dc 100644
--- a/board/compulab/cl-som-imx7/cl-som-imx7.c
+++ b/board/compulab/cl-som-imx7/cl-som-imx7.c
@@ -8,11 +8,11 @@
*/
#include <common.h>
-#include <environment.h>
+#include <env.h>
#include <mmc.h>
#include <phy.h>
#include <netdev.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <power/pmic.h>
#include <power/pfuze3000_pmic.h>
#include <asm/mach-imx/mxc_i2c.h>
@@ -68,7 +68,7 @@
return 0;
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
#define CL_SOM_IMX7_GPIO_USDHC3_PWR IMX_GPIO_NR(6, 11)
@@ -116,7 +116,7 @@
return 0;
}
-#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_FSL_ESDHC_IMX */
#ifdef CONFIG_FEC_MXC
diff --git a/board/compulab/cl-som-imx7/common.c b/board/compulab/cl-som-imx7/common.c
index e0f90fd..40ba0f7 100644
--- a/board/compulab/cl-som-imx7/common.c
+++ b/board/compulab/cl-som-imx7/common.c
@@ -8,7 +8,7 @@
*/
#include <common.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <asm-generic/gpio.h>
#include "common.h"
@@ -23,7 +23,7 @@
#endif /* CONFIG_SPI */
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
int board_mmc_getcd(struct mmc *mmc)
{
@@ -42,4 +42,4 @@
return ret;
}
-#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_FSL_ESDHC_IMX */
diff --git a/board/compulab/cl-som-imx7/common.h b/board/compulab/cl-som-imx7/common.h
index 8b15a59..bc19867 100644
--- a/board/compulab/cl-som-imx7/common.h
+++ b/board/compulab/cl-som-imx7/common.h
@@ -9,19 +9,19 @@
#define PADS_SET_PROT(pads_array) void cl_som_imx7_##pads_array##_set(void)
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
#define CL_SOM_IMX7_GPIO_USDHC1_CD IMX_GPIO_NR(5, 0)
PADS_SET_PROT(usdhc1_pads);
-#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_FSL_ESDHC_IMX */
PADS_SET_PROT(uart1_pads);
#ifdef CONFIG_SPI
PADS_SET_PROT(espi1_pads);
#endif /* CONFIG_SPI */
#ifndef CONFIG_SPL_BUILD
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
PADS_SET_PROT(usdhc3_emmc_pads);
-#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_FSL_ESDHC_IMX */
#ifdef CONFIG_FEC_MXC
PADS_SET_PROT(phy1_rst_pads);
PADS_SET_PROT(fec1_pads);
diff --git a/board/compulab/cl-som-imx7/mux.c b/board/compulab/cl-som-imx7/mux.c
index e29d2de..18f16a4 100644
--- a/board/compulab/cl-som-imx7/mux.c
+++ b/board/compulab/cl-som-imx7/mux.c
@@ -17,7 +17,7 @@
imx_iomux_v3_setup_multiple_pads(pads_array, ARRAY_SIZE(pads_array)); \
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
PAD_CTL_HYS | PAD_CTL_PUE | \
@@ -36,7 +36,7 @@
PADS_SET(usdhc1_pads)
-#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_FSL_ESDHC_IMX */
#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
@@ -69,7 +69,7 @@
#ifndef CONFIG_SPL_BUILD
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@@ -89,7 +89,7 @@
PADS_SET(usdhc3_emmc_pads)
-#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_FSL_ESDHC_IMX */
#ifdef CONFIG_FEC_MXC
diff --git a/board/compulab/cl-som-imx7/spl.c b/board/compulab/cl-som-imx7/spl.c
index 76a4c8b..f9a19f0 100644
--- a/board/compulab/cl-som-imx7/spl.c
+++ b/board/compulab/cl-som-imx7/spl.c
@@ -9,14 +9,14 @@
#include <common.h>
#include <spl.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/arch-mx7/mx7-pins.h>
#include <asm/arch-mx7/clock.h>
#include <asm/arch-mx7/mx7-ddr.h>
#include "common.h"
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
static struct fsl_esdhc_cfg cl_som_imx7_spl_usdhc_cfg = {
USDHC1_BASE_ADDR, 0, 4};
@@ -27,7 +27,7 @@
cl_som_imx7_spl_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
return fsl_esdhc_initialize(bis, &cl_som_imx7_spl_usdhc_cfg);
}
-#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_FSL_ESDHC_IMX */
static iomux_v3_cfg_t const led_pads[] = {
MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 | MUX_PAD_CTRL(PAD_CTL_PUS_PU5KOHM |
diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c
index d42f57d..feb7a71 100644
--- a/board/compulab/cm_fx6/cm_fx6.c
+++ b/board/compulab/cm_fx6/cm_fx6.c
@@ -11,8 +11,8 @@
#include <ahci.h>
#include <dm.h>
#include <dwc_ahsata.h>
-#include <environment.h>
-#include <fsl_esdhc.h>
+#include <env.h>
+#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <mtd_node.h>
#include <netdev.h>
@@ -608,7 +608,7 @@
cm_fx6_setup_display();
/* This should be done in the MMC driver when MX6 has a clock driver */
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
if (IS_ENABLED(CONFIG_BLK)) {
int i;
diff --git a/board/compulab/cm_fx6/common.c b/board/compulab/cm_fx6/common.c
index e1e4a67..ed8c7a3 100644
--- a/board/compulab/cm_fx6/common.c
+++ b/board/compulab/cm_fx6/common.c
@@ -11,10 +11,10 @@
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/mach-imx/spi.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include "common.h"
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
diff --git a/board/compulab/cm_fx6/spl.c b/board/compulab/cm_fx6/spl.c
index acbb2ad..66186ec 100644
--- a/board/compulab/cm_fx6/spl.c
+++ b/board/compulab/cm_fx6/spl.c
@@ -16,7 +16,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/mach-imx/iomux-v3.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include "common.h"
enum ddr_config {
diff --git a/board/compulab/cm_t335/cm_t335.c b/board/compulab/cm_t335/cm_t335.c
index 95cbb77..6e38745 100644
--- a/board/compulab/cm_t335/cm_t335.c
+++ b/board/compulab/cm_t335/cm_t335.c
@@ -8,7 +8,7 @@
*/
#include <common.h>
-#include <environment.h>
+#include <env.h>
#include <errno.h>
#include <miiphy.h>
#include <cpsw.h>
diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c
index 4d171f49..b52358b 100644
--- a/board/compulab/cm_t35/cm_t35.c
+++ b/board/compulab/cm_t35/cm_t35.c
@@ -12,7 +12,7 @@
*/
#include <common.h>
-#include <environment.h>
+#include <env.h>
#include <status_led.h>
#include <netdev.h>
#include <net.h>
diff --git a/board/compulab/cm_t54/cm_t54.c b/board/compulab/cm_t54/cm_t54.c
index 504a537..811bbb5 100644
--- a/board/compulab/cm_t54/cm_t54.c
+++ b/board/compulab/cm_t54/cm_t54.c
@@ -8,7 +8,7 @@
*/
#include <common.h>
-#include <environment.h>
+#include <env.h>
#include <fdt_support.h>
#include <usb.h>
#include <mmc.h>
diff --git a/board/compulab/common/omap3_display.c b/board/compulab/common/omap3_display.c
index bc9f31a..cb9ebae 100644
--- a/board/compulab/common/omap3_display.c
+++ b/board/compulab/common/omap3_display.c
@@ -10,6 +10,7 @@
#include <common.h>
#include <asm/gpio.h>
#include <asm/io.h>
+#include <env.h>
#include <stdio_dev.h>
#include <asm/arch/dss.h>
#include <lcd.h>
diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c
index 50124f8..6b3d5b8 100644
--- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c
+++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c
@@ -20,8 +20,9 @@
#include <asm/arch/sys_proto.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
+#include <env.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <i2c.h>
#include <input.h>
#include <power/pmic.h>
@@ -411,7 +412,7 @@
}
#endif
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
static struct fsl_esdhc_cfg usdhc_cfg[] = {
{USDHC2_BASE_ADDR},
{USDHC3_BASE_ADDR},
diff --git a/board/cssi/MCR3000/MCR3000.c b/board/cssi/MCR3000/MCR3000.c
index d26ac35..445b84c 100644
--- a/board/cssi/MCR3000/MCR3000.c
+++ b/board/cssi/MCR3000/MCR3000.c
@@ -8,6 +8,7 @@
*/
#include <common.h>
+#include <env.h>
#include <hwconfig.h>
#include <mpc8xx.h>
#include <fdt_support.h>
diff --git a/board/davinci/da8xxevm/Kconfig b/board/davinci/da8xxevm/Kconfig
index e0df97c..bb1188b 100644
--- a/board/davinci/da8xxevm/Kconfig
+++ b/board/davinci/da8xxevm/Kconfig
@@ -33,8 +33,6 @@
endif
-source "board/ti/common/Kconfig"
-
endif
if TARGET_OMAPL138_LCDK
diff --git a/board/davinci/da8xxevm/MAINTAINERS b/board/davinci/da8xxevm/MAINTAINERS
index b77a5f6..42324a3 100644
--- a/board/davinci/da8xxevm/MAINTAINERS
+++ b/board/davinci/da8xxevm/MAINTAINERS
@@ -7,10 +7,6 @@
F: configs/da850evm_nand_defconfig
F: configs/da850evm_direct_nor_defconfig
-AM18XXEVM BOARD
-S: Orphan
-F: configs/da850_am18xxevm_defconfig
-
OMAPL138_LCDK BOARD
M: Peter Howard <phoward@gme.net.au>
S: Maintained
diff --git a/board/davinci/da8xxevm/README.da850 b/board/davinci/da8xxevm/README.da850
index 5775b7d..8cebdcc 100644
--- a/board/davinci/da8xxevm/README.da850
+++ b/board/davinci/da8xxevm/README.da850
@@ -29,9 +29,7 @@
===========
The exact build target you need will depend on the board you have. For
Logic PD boards, or other boards which store the ethernet MAC address at
-the end of SPI flash, run 'make da850evm'. For boards which store the
-ethernet MAC address in the i2c EEPROM located at 0x50, run
-'make da850_am18xxevm'. Once this build completes you will have a
+the end of SPI flash, run 'make da850evm'. Once this build completes you will have a
u-boot.ais file that needs to be written to the correct persistent
storage.
diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c
index a90b7a3..d9019de 100644
--- a/board/davinci/da8xxevm/da850evm.c
+++ b/board/davinci/da8xxevm/da850evm.c
@@ -10,10 +10,9 @@
#include <common.h>
#include <dm.h>
-#include <environment.h>
+#include <env.h>
#include <i2c.h>
#include <net.h>
-#include <netdev.h>
#include <spi.h>
#include <spi_flash.h>
#include <asm/arch/hardware.h>
@@ -291,9 +290,6 @@
rev = 2;
else if (maxcpuclk >= 372000000)
rev = 1;
-#ifdef CONFIG_DA850_AM18X_EVM
- rev |= REV_AM18X_EVM;
-#endif
return rev;
}
@@ -344,10 +340,6 @@
DAVINCI_SYSCFG_SUSPSRC_UART2),
&davinci_syscfg_regs->suspsrc);
- /* configure pinmux settings */
- if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
- return 1;
-
#ifdef CONFIG_USE_NOR
/* Set the GPIO direction as output */
clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
@@ -368,11 +360,6 @@
davinci_emac_mii_mode_sel(HAS_RMII);
#endif /* CONFIG_DRIVER_TI_EMAC */
- /* enable the console UART */
- writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
- DAVINCI_UART_PWREMU_MGMT_UTRST),
- &davinci_uart2_ctrl_regs->pwremu_mgmt);
-
return 0;
}
@@ -472,11 +459,6 @@
if (rmii_hw_init())
printf("RMII hardware init failed!!!\n");
#endif
- if (!davinci_emac_initialize()) {
- printf("Error: Ethernet init failed!\n");
- return -1;
- }
-
return 0;
}
#endif /* CONFIG_DRIVER_TI_EMAC */
diff --git a/board/davinci/da8xxevm/omapl138_lcdk.c b/board/davinci/da8xxevm/omapl138_lcdk.c
index fe1bf44..27a51d6 100644
--- a/board/davinci/da8xxevm/omapl138_lcdk.c
+++ b/board/davinci/da8xxevm/omapl138_lcdk.c
@@ -9,14 +9,14 @@
*/
#include <common.h>
+#include <env.h>
#include <i2c.h>
#include <net.h>
-#include <netdev.h>
-#include <spi.h>
-#include <spi_flash.h>
#include <asm/arch/hardware.h>
#include <asm/ti-common/davinci_nand.h>
#include <asm/io.h>
+#include <ns16550.h>
+#include <dm/platdata.h>
#include <linux/errno.h>
#include <asm/mach-types.h>
#include <asm/arch/davinci_misc.h>
@@ -227,23 +227,6 @@
return 0;
}
-#ifdef CONFIG_DRIVER_TI_EMAC
-
-/*
- * Initializes on-board ethernet controllers.
- */
-int board_eth_init(bd_t *bis)
-{
- if (!davinci_emac_initialize()) {
- printf("Error: Ethernet init failed!\n");
- return -1;
- }
-
- return 0;
-}
-
-#endif /* CONFIG_DRIVER_TI_EMAC */
-
#define CFG_MAC_ADDR_SPI_BUS 0
#define CFG_MAC_ADDR_SPI_CS 0
#define CFG_MAC_ADDR_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
@@ -371,3 +354,17 @@
}
#endif
#endif
+
+#ifdef CONFIG_SPL_BUILD
+static const struct ns16550_platdata serial_pdata = {
+ .base = DAVINCI_UART2_BASE,
+ .reg_shift = 2,
+ .clock = 228000000,
+ .fcr = UART_FCR_DEFVAL,
+};
+
+U_BOOT_DEVICE(omapl138_uart) = {
+ .name = "ns16550_serial",
+ .platdata = &serial_pdata,
+};
+#endif
diff --git a/board/dhelectronics/dh_imx6/dh_imx6.c b/board/dhelectronics/dh_imx6/dh_imx6.c
index 50e3cb5..2d0f78d 100644
--- a/board/dhelectronics/dh_imx6/dh_imx6.c
+++ b/board/dhelectronics/dh_imx6/dh_imx6.c
@@ -18,15 +18,14 @@
#include <asm/io.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/sata.h>
#include <ahci.h>
#include <dwc_ahsata.h>
-#include <environment.h>
+#include <env.h>
#include <errno.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <fuse.h>
-#include <i2c.h>
+#include <i2c_eeprom.h>
#include <miiphy.h>
#include <mmc.h>
#include <net.h>
@@ -36,92 +35,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#define I2C_PAD_CTRL \
- (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
- PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
-#define EEPROM_I2C_ADDRESS 0x50
-
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-
-static struct i2c_pads_info dh6sdl_i2c_pad_info0 = {
- .scl = {
- .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
- .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
- .gp = IMX_GPIO_NR(3, 21)
- },
- .sda = {
- .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
- .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
- .gp = IMX_GPIO_NR(3, 28)
- }
-};
-
-static struct i2c_pads_info dh6sdl_i2c_pad_info1 = {
- .scl = {
- .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
- .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
- .gp = IMX_GPIO_NR(4, 12)
- },
- .sda = {
- .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
- .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
- .gp = IMX_GPIO_NR(4, 13)
- }
-};
-
-static struct i2c_pads_info dh6sdl_i2c_pad_info2 = {
- .scl = {
- .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
- .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
- .gp = IMX_GPIO_NR(1, 3)
- },
- .sda = {
- .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
- .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC,
- .gp = IMX_GPIO_NR(1, 6)
- }
-};
-
-static struct i2c_pads_info dh6dq_i2c_pad_info0 = {
- .scl = {
- .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
- .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
- .gp = IMX_GPIO_NR(3, 21)
- },
- .sda = {
- .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
- .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
- .gp = IMX_GPIO_NR(3, 28)
- }
-};
-
-static struct i2c_pads_info dh6dq_i2c_pad_info1 = {
- .scl = {
- .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
- .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
- .gp = IMX_GPIO_NR(4, 12)
- },
- .sda = {
- .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
- .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
- .gp = IMX_GPIO_NR(4, 13)
- }
-};
-
-static struct i2c_pads_info dh6dq_i2c_pad_info2 = {
- .scl = {
- .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
- .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
- .gp = IMX_GPIO_NR(1, 3)
- },
- .sda = {
- .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
- .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
- .gp = IMX_GPIO_NR(1, 6)
- }
-};
-
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
@@ -196,7 +109,6 @@
#ifdef CONFIG_USB_EHCI_MX6
static void setup_usb(void)
{
- gpio_request(IMX_GPIO_NR(3, 31), "USB-VBUS");
/*
* Set daisy chain for otg_pin_id on MX6Q.
* For MX6DL, this bit is reserved.
@@ -211,26 +123,12 @@
else
return USB_INIT_DEVICE;
}
-
-int board_ehci_power(int port, int on)
-{
- switch (port) {
- case 0:
- break;
- case 1:
- gpio_direction_output(IMX_GPIO_NR(3, 31), !!on);
- break;
- default:
- printf("MXC USB port %d not yet supported\n", port);
- return -EINVAL;
- }
-
- return 0;
-}
#endif
static int setup_dhcom_mac_from_fuse(void)
{
+ struct udevice *dev;
+ ofnode eeprom;
unsigned char enetaddr[6];
int ret;
@@ -245,13 +143,19 @@
return 0;
}
- ret = i2c_set_bus_num(2);
+ eeprom = ofnode_path("/soc/aips-bus@2100000/i2c@21a8000/eeprom@50");
+ if (!ofnode_valid(eeprom)) {
+ printf("Invalid hardware path to EEPROM!\n");
+ return -ENODEV;
+ }
+
+ ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, &dev);
if (ret) {
- printf("Error switching I2C bus!\n");
+ printf("Cannot find EEPROM!\n");
return ret;
}
- ret = i2c_read(EEPROM_I2C_ADDRESS, 0xfa, 0x1, enetaddr, 0x6);
+ ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6);
if (ret) {
printf("Error reading configuration EEPROM!\n");
return ret;
@@ -282,18 +186,6 @@
/* Enable eim_slow clocks */
setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET);
-#ifdef CONFIG_SYS_I2C_MXC
- if (is_mx6dq()) {
- setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6dq_i2c_pad_info0);
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6dq_i2c_pad_info1);
- setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6dq_i2c_pad_info2);
- } else {
- setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6sdl_i2c_pad_info0);
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6sdl_i2c_pad_info1);
- setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6sdl_i2c_pad_info2);
- }
-#endif
-
setup_dhcom_mac_from_fuse();
return 0;
@@ -372,3 +264,18 @@
puts("Board: DHCOM i.MX6\n");
return 0;
}
+
+#ifdef CONFIG_MULTI_DTB_FIT
+int board_fit_config_name_match(const char *name)
+{
+ if (is_mx6dq()) {
+ if (!strcmp(name, "imx6q-dhcom-pdk2"))
+ return 0;
+ } else if (is_mx6sdl()) {
+ if (!strcmp(name, "imx6dl-dhcom-pdk2"))
+ return 0;
+ }
+
+ return -1;
+}
+#endif
diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
index 2939389..1b7acc8 100644
--- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c
+++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
@@ -20,7 +20,7 @@
#include <asm/io.h>
#include <errno.h>
#include <fuse.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <i2c.h>
#include <mmc.h>
#include <spl.h>
@@ -440,8 +440,13 @@
/* SPI */
static iomux_v3_cfg_t const ecspi1_pads[] = {
- /* SS0 */
- IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+ /* SS0 - SS of boot flash */
+ IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30 |
+ MUX_PAD_CTRL(SPI_PAD_CTRL | PAD_CTL_PUS_100K_UP)),
+ /* SS2 - SS of DHCOM SPI1 */
+ IOMUX_PADS(PAD_KEY_ROW2__GPIO4_IO11 |
+ MUX_PAD_CTRL(SPI_PAD_CTRL | PAD_CTL_PUS_100K_UP)),
+
IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
diff --git a/board/eets/pdu001/board.c b/board/eets/pdu001/board.c
index b857a5a..8a3d0ad 100644
--- a/board/eets/pdu001/board.c
+++ b/board/eets/pdu001/board.c
@@ -10,10 +10,10 @@
*/
#include <common.h>
+#include <env.h>
#include <errno.h>
#include <spl.h>
#include <i2c.h>
-#include <environment.h>
#include <watchdog.h>
#include <debug_uart.h>
#include <dm/ofnode.h>
diff --git a/board/el/el6x/el6x.c b/board/el/el6x/el6x.c
index dd0c112..18d69a7 100644
--- a/board/el/el6x/el6x.c
+++ b/board/el/el6x/el6x.c
@@ -9,6 +9,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
+#include <env.h>
#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
@@ -16,7 +17,7 @@
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/video.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/mxc_hdmi.h>
@@ -255,7 +256,7 @@
MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC2_BASE_ADDR},
{USDHC4_BASE_ADDR},
diff --git a/board/elgin/elgin_rv1108/elgin_rv1108.c b/board/elgin/elgin_rv1108/elgin_rv1108.c
index 0de1f42..607667a 100644
--- a/board/elgin/elgin_rv1108/elgin_rv1108.c
+++ b/board/elgin/elgin_rv1108/elgin_rv1108.c
@@ -50,7 +50,7 @@
#define MODEM_ENABLE_GPIO 111
-int board_init(void)
+int board_early_init_f(void)
{
gpio_request(MODEM_ENABLE_GPIO, "modem_enable");
gpio_direction_output(MODEM_ENABLE_GPIO, 0);
diff --git a/board/embest/mx6boards/mx6boards.c b/board/embest/mx6boards/mx6boards.c
index fed92aa..bcfe125 100644
--- a/board/embest/mx6boards/mx6boards.c
+++ b/board/embest/mx6boards/mx6boards.c
@@ -27,7 +27,7 @@
#include <i2c.h>
#include <input.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/mxc_hdmi.h>
@@ -181,7 +181,7 @@
MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg usdhc_cfg[3] = {
{USDHC2_BASE_ADDR},
{USDHC3_BASE_ADDR},
diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig
index 7f9a74d..7ce1201 100644
--- a/board/emulation/qemu-riscv/Kconfig
+++ b/board/emulation/qemu-riscv/Kconfig
@@ -13,17 +13,27 @@
default "qemu-riscv"
config SYS_TEXT_BASE
+ default 0x81200000 if SPL
default 0x80000000 if !RISCV_SMODE
default 0x80200000 if RISCV_SMODE && ARCH_RV64I
default 0x80400000 if RISCV_SMODE && ARCH_RV32I
+config SPL_TEXT_BASE
+ default 0x80000000
+
+config SPL_OPENSBI_LOAD_ADDR
+ hex
+ default 0x81000000
+
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select GENERIC_RISCV
+ select SUPPORT_SPL
imply SYS_NS16550
imply VIRTIO_MMIO
imply VIRTIO_NET
imply VIRTIO_BLK
+ imply VIRTIO_PCI
imply CMD_PING
imply CMD_FS_GENERIC
imply DOS_PARTITION
@@ -42,5 +52,7 @@
imply CMD_PCI
imply E1000
imply NVME
+ imply SPL_RAM_SUPPORT
+ imply SPL_RAM_DEVICE
endif
diff --git a/board/emulation/qemu-riscv/MAINTAINERS b/board/emulation/qemu-riscv/MAINTAINERS
index c701c83..78969ed 100644
--- a/board/emulation/qemu-riscv/MAINTAINERS
+++ b/board/emulation/qemu-riscv/MAINTAINERS
@@ -5,5 +5,7 @@
F: include/configs/qemu-riscv.h
F: configs/qemu-riscv32_defconfig
F: configs/qemu-riscv32_smode_defconfig
+F: configs/qemu-riscv32_spl_defconfig
F: configs/qemu-riscv64_defconfig
F: configs/qemu-riscv64_smode_defconfig
+F: configs/qemu-riscv64_spl_defconfig
diff --git a/board/emulation/qemu-riscv/qemu-riscv.c b/board/emulation/qemu-riscv/qemu-riscv.c
index d6167aa..37d48d0 100644
--- a/board/emulation/qemu-riscv/qemu-riscv.c
+++ b/board/emulation/qemu-riscv/qemu-riscv.c
@@ -5,7 +5,9 @@
#include <common.h>
#include <dm.h>
+#include <env.h>
#include <fdtdec.h>
+#include <spl.h>
#include <virtio_types.h>
#include <virtio.h>
@@ -87,3 +89,19 @@
return 0;
}
+
+#ifdef CONFIG_SPL
+u32 spl_boot_device(void)
+{
+ /* RISC-V QEMU only supports RAM as SPL boot device */
+ return BOOT_DEVICE_RAM;
+}
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ /* boot using first FIT config */
+ return 0;
+}
+#endif
diff --git a/board/engicam/common/board.c b/board/engicam/common/board.c
index 7486f0a..0c47afe 100644
--- a/board/engicam/common/board.c
+++ b/board/engicam/common/board.c
@@ -6,6 +6,7 @@
*/
#include <common.h>
+#include <env.h>
#include <mmc.h>
#include <asm/arch/sys_proto.h>
#include <watchdog.h>
@@ -53,8 +54,6 @@
env_set("fdt_file", "imx6dl-icore-rqs.dtb");
} else if (!strcmp(cmp_dtb, "imx6ul-geam"))
env_set("fdt_file", "imx6ul-geam.dtb");
- else if (!strcmp(cmp_dtb, "imx6ul-isiot-mmc"))
- env_set("fdt_file", "imx6ul-isiot-emmc.dtb");
else if (!strcmp(cmp_dtb, "imx6ul-isiot-emmc"))
env_set("fdt_file", "imx6ul-isiot-emmc.dtb");
else if (!strcmp(cmp_dtb, "imx6ul-isiot-nand"))
diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c
index 29b6341..b0d2f7b 100644
--- a/board/esd/meesc/meesc.c
+++ b/board/esd/meesc/meesc.c
@@ -10,6 +10,7 @@
*/
#include <common.h>
+#include <env.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/mach-types.h>
diff --git a/board/firefly/firefly-rk3288/firefly-rk3288.c b/board/firefly/firefly-rk3288/firefly-rk3288.c
index bdc02a6..a3f784f 100644
--- a/board/firefly/firefly-rk3288/firefly-rk3288.c
+++ b/board/firefly/firefly-rk3288/firefly-rk3288.c
@@ -4,3 +4,39 @@
*/
#include <common.h>
+
+#ifdef CONFIG_SPL_BUILD
+static int setup_led(void)
+{
+#ifdef CONFIG_SPL_LED
+ struct udevice *dev;
+ char *led_name;
+ int ret;
+
+ led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
+ if (!led_name)
+ return 0;
+ ret = led_get_by_label(led_name, &dev);
+ if (ret) {
+ debug("%s: get=%d\n", __func__, ret);
+ return ret;
+ }
+ ret = led_set_on(dev, 1);
+ if (ret)
+ return ret;
+#endif
+
+ return 0;
+}
+
+void spl_board_init(void)
+{
+ int ret;
+
+ ret = setup_led();
+ if (ret) {
+ debug("LED ret=%d\n", ret);
+ hang();
+ }
+}
+#endif
diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c
index 9eed95b..33cd4b4 100644
--- a/board/freescale/b4860qds/b4860qds.c
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -5,6 +5,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <i2c.h>
#include <netdev.h>
#include <linux/compiler.h>
diff --git a/board/freescale/b4860qds/spl.c b/board/freescale/b4860qds/spl.c
index 887fa04..6dfc0c7 100644
--- a/board/freescale/b4860qds/spl.c
+++ b/board/freescale/b4860qds/spl.c
@@ -4,7 +4,8 @@
#include <common.h>
#include <console.h>
-#include <environment.h>
+#include <env.h>
+#include <env_internal.h>
#include <asm/spl.h>
#include <malloc.h>
#include <ns16550.h>
diff --git a/board/freescale/bsc9131rdb/bsc9131rdb.c b/board/freescale/bsc9131rdb/bsc9131rdb.c
index 9d9c83f..30e7a1f 100644
--- a/board/freescale/bsc9131rdb/bsc9131rdb.c
+++ b/board/freescale/bsc9131rdb/bsc9131rdb.c
@@ -9,6 +9,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/io.h>
+#include <env.h>
#include <miiphy.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
diff --git a/board/freescale/bsc9132qds/bsc9132qds.c b/board/freescale/bsc9132qds/bsc9132qds.c
index 36a5528..dd9ad90 100644
--- a/board/freescale/bsc9132qds/bsc9132qds.c
+++ b/board/freescale/bsc9132qds/bsc9132qds.c
@@ -9,6 +9,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/io.h>
+#include <env.h>
#include <miiphy.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
diff --git a/board/freescale/c29xpcie/c29xpcie.c b/board/freescale/c29xpcie/c29xpcie.c
index 8ee3e14..6d103be 100644
--- a/board/freescale/c29xpcie/c29xpcie.c
+++ b/board/freescale/c29xpcie/c29xpcie.c
@@ -9,6 +9,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/io.h>
+#include <env.h>
#include <miiphy.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
diff --git a/board/freescale/c29xpcie/spl.c b/board/freescale/c29xpcie/spl.c
index 5db60d8..2904096 100644
--- a/board/freescale/c29xpcie/spl.c
+++ b/board/freescale/c29xpcie/spl.c
@@ -4,7 +4,7 @@
#include <common.h>
#include <console.h>
-#include <environment.h>
+#include <env_internal.h>
#include <ns16550.h>
#include <malloc.h>
#include <mmc.h>
diff --git a/board/freescale/common/cds_pci_ft.c b/board/freescale/common/cds_pci_ft.c
index 3ff2fa4..fb2e5c7 100644
--- a/board/freescale/common/cds_pci_ft.c
+++ b/board/freescale/common/cds_pci_ft.c
@@ -9,6 +9,7 @@
#include "cadmus.h"
#if defined(CONFIG_OF_BOARD_SETUP)
+#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
static void cds_pci_fixup(void *blob)
{
int node;
@@ -61,11 +62,12 @@
}
}
}
+#endif
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
+#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
ft_pci_setup(blob, bd);
cds_pci_fixup(blob);
#endif
diff --git a/board/freescale/common/cmd_esbc_validate.c b/board/freescale/common/cmd_esbc_validate.c
index b06235f..36b620c 100644
--- a/board/freescale/common/cmd_esbc_validate.c
+++ b/board/freescale/common/cmd_esbc_validate.c
@@ -5,6 +5,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <fsl_validate.h>
int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc,
diff --git a/board/freescale/common/emc2305.c b/board/freescale/common/emc2305.c
index 8523084..b1ca051 100644
--- a/board/freescale/common/emc2305.c
+++ b/board/freescale/common/emc2305.c
@@ -24,10 +24,22 @@
I2C_EMC2305_FAN5};
for (index = 0; index < NUM_OF_FANS; index++) {
+#ifndef CONFIG_DM_I2C
if (i2c_write(I2C_EMC2305_ADDR, Fan[index], 1, &data, 1) != 0) {
printf("Error: failed to change fan speed @%x\n",
Fan[index]);
}
+#else
+ struct udevice *dev;
+
+ if (i2c_get_chip_for_busnum(0, I2C_EMC2305_ADDR, 1, &dev))
+ continue;
+
+ if (dm_i2c_write(dev, Fan[index], &data, 1) != 0) {
+ printf("Error: failed to change fan speed @%x\n",
+ Fan[index]);
+ }
+#endif
}
}
@@ -36,6 +48,15 @@
u8 data;
data = I2C_EMC2305_CMD;
+#ifndef CONFIG_DM_I2C
if (i2c_write(I2C_EMC2305_ADDR, I2C_EMC2305_CONF, 1, &data, 1) != 0)
printf("Error: failed to configure EMC2305\n");
+#else
+ struct udevice *dev;
+
+ if (!i2c_get_chip_for_busnum(0, I2C_EMC2305_ADDR, 1, &dev))
+ if (dm_i2c_write(dev, I2C_EMC2305_CONF, &data, 1))
+ printf("Error: failed to configure EMC2305\n");
+#endif
+
}
diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c
index dddfd26..a024e72 100644
--- a/board/freescale/common/fsl_chain_of_trust.c
+++ b/board/freescale/common/fsl_chain_of_trust.c
@@ -5,6 +5,7 @@
#include <common.h>
#include <dm.h>
+#include <env.h>
#include <fsl_validate.h>
#include <fsl_secboot_err.h>
#include <fsl_sfp.h>
diff --git a/board/freescale/common/p_corenet/pci.c b/board/freescale/common/p_corenet/pci.c
index a2df928..a6abe66 100644
--- a/board/freescale/common/p_corenet/pci.c
+++ b/board/freescale/common/p_corenet/pci.c
@@ -11,6 +11,7 @@
#include <fdt_support.h>
#include <asm/fsl_serdes.h>
+#if !defined(CONFIG_DM_PCI)
void pci_init_board(void)
{
fsl_pcie_init_board(0);
@@ -20,3 +21,4 @@
{
FT_FSL_PCI_SETUP;
}
+#endif
diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
index f1b98bc..716c93b 100644
--- a/board/freescale/common/qixis.c
+++ b/board/freescale/common/qixis.c
@@ -21,16 +21,40 @@
#define QIXIS_LBMAP_BRDCFG_REG 0x00
#endif
+#ifndef QIXIS_RCFG_CTL_RECONFIG_IDLE
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
+#endif
+#ifndef QIXIS_RCFG_CTL_RECONFIG_START
+#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
+#endif
+
#ifdef CONFIG_SYS_I2C_FPGA_ADDR
u8 qixis_read_i2c(unsigned int reg)
{
+#ifndef CONFIG_DM_I2C
return i2c_reg_read(CONFIG_SYS_I2C_FPGA_ADDR, reg);
+#else
+ struct udevice *dev;
+
+ if (i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev))
+ return 0xff;
+
+ return dm_i2c_reg_read(dev, reg);
+#endif
}
void qixis_write_i2c(unsigned int reg, u8 value)
{
u8 val = value;
+#ifndef CONFIG_DM_I2C
i2c_reg_write(CONFIG_SYS_I2C_FPGA_ADDR, reg, val);
+#else
+ struct udevice *dev;
+
+ if (!i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev))
+ dm_i2c_reg_write(dev, reg, val);
+#endif
+
}
#endif
@@ -142,11 +166,13 @@
QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET);
}
+#ifdef QIXIS_LBMAP_ALTBANK
static void qixis_bank_reset(void)
{
QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
}
+#endif
static void __maybe_unused set_lbmap(int lbmap)
{
@@ -159,12 +185,16 @@
static void __maybe_unused set_rcw_src(int rcw_src)
{
+#ifdef CONFIG_NXP_LSCH3_2
+ QIXIS_WRITE(dutcfg[0], (rcw_src & 0xff));
+#else
u8 reg;
reg = QIXIS_READ(dutcfg[1]);
reg = (reg & ~1) | (rcw_src & 1);
QIXIS_WRITE(dutcfg[1], reg);
QIXIS_WRITE(dutcfg[0], (rcw_src >> 1) & 0xff);
+#endif
}
static void qixis_dump_regs(void)
@@ -210,16 +240,20 @@
set_lbmap(QIXIS_LBMAP_DFLTBANK);
qixis_reset();
} else if (strcmp(argv[1], "altbank") == 0) {
+#ifdef QIXIS_LBMAP_ALTBANK
set_lbmap(QIXIS_LBMAP_ALTBANK);
qixis_bank_reset();
+#else
+ printf("No Altbank!\n");
+#endif
} else if (strcmp(argv[1], "nand") == 0) {
#ifdef QIXIS_LBMAP_NAND
QIXIS_WRITE(rst_ctl, 0x30);
QIXIS_WRITE(rcfg_ctl, 0);
set_lbmap(QIXIS_LBMAP_NAND);
set_rcw_src(QIXIS_RCW_SRC_NAND);
- QIXIS_WRITE(rcfg_ctl, 0x20);
- QIXIS_WRITE(rcfg_ctl, 0x21);
+ QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
+ QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
#else
printf("Not implemented\n");
#endif
@@ -233,8 +267,8 @@
set_lbmap(QIXIS_LBMAP_SD);
set_rcw_src(QIXIS_RCW_SRC_SD);
#endif
- QIXIS_WRITE(rcfg_ctl, 0x20);
- QIXIS_WRITE(rcfg_ctl, 0x21);
+ QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
+ QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
#else
printf("Not implemented\n");
#endif
@@ -244,8 +278,8 @@
QIXIS_WRITE(rcfg_ctl, 0);
set_lbmap(QIXIS_LBMAP_IFC);
set_rcw_src(QIXIS_RCW_SRC_IFC);
- QIXIS_WRITE(rcfg_ctl, 0x20);
- QIXIS_WRITE(rcfg_ctl, 0x21);
+ QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
+ QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
#else
printf("Not implemented\n");
#endif
@@ -255,8 +289,8 @@
QIXIS_WRITE(rcfg_ctl, 0);
set_lbmap(QIXIS_LBMAP_EMMC);
set_rcw_src(QIXIS_RCW_SRC_EMMC);
- QIXIS_WRITE(rcfg_ctl, 0x20);
- QIXIS_WRITE(rcfg_ctl, 0x21);
+ QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
+ QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
#else
printf("Not implemented\n");
#endif
@@ -266,8 +300,10 @@
QIXIS_WRITE(rcfg_ctl, 0);
set_lbmap(QIXIS_LBMAP_SD_QSPI);
set_rcw_src(QIXIS_RCW_SRC_SD);
- qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20);
- qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21);
+ qixis_write_i2c(offsetof(struct qixis, rcfg_ctl),
+ QIXIS_RCFG_CTL_RECONFIG_IDLE);
+ qixis_write_i2c(offsetof(struct qixis, rcfg_ctl),
+ QIXIS_RCFG_CTL_RECONFIG_START);
#else
printf("Not implemented\n");
#endif
@@ -277,8 +313,10 @@
QIXIS_WRITE(rcfg_ctl, 0);
set_lbmap(QIXIS_LBMAP_QSPI);
set_rcw_src(QIXIS_RCW_SRC_QSPI);
- qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20);
- qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21);
+ qixis_write_i2c(offsetof(struct qixis, rcfg_ctl),
+ QIXIS_RCFG_CTL_RECONFIG_IDLE);
+ qixis_write_i2c(offsetof(struct qixis, rcfg_ctl),
+ QIXIS_RCFG_CTL_RECONFIG_START);
#else
printf("Not implemented\n");
#endif
diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c
index ab0fe0b..bb655ca 100644
--- a/board/freescale/common/sys_eeprom.c
+++ b/board/freescale/common/sys_eeprom.c
@@ -8,6 +8,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <i2c.h>
#include <linux/ctype.h>
@@ -148,23 +149,42 @@
{
int ret;
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+#ifndef CONFIG_DM_I2C
unsigned int bus;
#endif
+#endif
if (has_been_read)
return 0;
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+#ifndef CONFIG_DM_I2C
bus = i2c_get_bus_num();
i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
#endif
+#endif
- ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
- (void *)&e, sizeof(e));
+#ifndef CONFIG_DM_I2C
+ ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+ (void *)&e, sizeof(e));
+#else
+ struct udevice *dev;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
+ CONFIG_SYS_I2C_EEPROM_ADDR, 1, &dev);
+#else
+ ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR, 1, &dev);
+#endif
+ if (!ret)
+ ret = dm_i2c_read(dev, 0, (void *)&e, sizeof(e));
+#endif
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+#ifndef CONFIG_DM_I2C
i2c_set_bus_num(bus);
#endif
+#endif
#ifdef DEBUG
show_eeprom();
@@ -198,8 +218,10 @@
int i;
void *p;
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+#ifndef CONFIG_DM_I2C
unsigned int bus;
#endif
+#endif
/* Set the reserved values to 0xFF */
#ifdef CONFIG_SYS_I2C_EEPROM_NXID
@@ -210,10 +232,12 @@
#endif
update_crc();
+#ifndef CONFIG_DM_I2C
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
bus = i2c_get_bus_num();
i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
#endif
+#endif
/*
* The AT24C02 datasheet says that data can only be written in page
@@ -221,8 +245,26 @@
* complete a given write.
*/
for (i = 0, p = &e; i < sizeof(e); i += 8, p += 8) {
- ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+#ifndef CONFIG_DM_I2C
+ ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
p, min((int)(sizeof(e) - i), 8));
+#else
+ struct udevice *dev;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
+ CONFIG_SYS_I2C_EEPROM_ADDR,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+ &dev);
+#else
+ ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+ &dev);
+#endif
+ if (!ret)
+ ret = dm_i2c_write(dev, i, p, min((int)(sizeof(e) - i),
+ 8));
+#endif
if (ret)
break;
udelay(5000); /* 5ms write cycle timing */
@@ -232,15 +274,34 @@
/* Verify the write by reading back the EEPROM and comparing */
struct eeprom e2;
+#ifndef CONFIG_DM_I2C
ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
- CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (void *)&e2, sizeof(e2));
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+ (void *)&e2, sizeof(e2));
+#else
+ struct udevice *dev;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
+ CONFIG_SYS_I2C_EEPROM_ADDR,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+ &dev);
+#else
+ ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+ &dev);
+#endif
+ if (!ret)
+ ret = dm_i2c_read(dev, 0, (void *)&e2, sizeof(e2));
+#endif
if (!ret && memcmp(&e, &e2, sizeof(e)))
ret = -1;
}
+#ifndef CONFIG_DM_I2C
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
i2c_set_bus_num(bus);
#endif
+#endif
if (ret) {
printf("Programming failed.\n");
@@ -528,8 +589,24 @@
u8 minor; /* 0x05 Board revision, minor */
} be;
+#ifndef CONFIG_DM_I2C
i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
(void *)&be, sizeof(be));
+#else
+ struct udevice *dev;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
+ CONFIG_SYS_I2C_EEPROM_ADDR,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+ &dev);
+#else
+ ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+ &dev)
+#endif
+ if (!ret)
+ dm_i2c_read(dev, 0, (void *)&be, sizeof(be));
+#endif
if (be.id != (('C' << 24) | ('C' << 16) | ('I' << 8) | 'D'))
return MPC85XX_CPU_BOARD_REV(0, 0);
diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c
index 0ca389c..b37f3bf 100644
--- a/board/freescale/common/vid.c
+++ b/board/freescale/common/vid.c
@@ -5,6 +5,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <i2c.h>
#include <asm/io.h>
#ifdef CONFIG_FSL_LSCH2
@@ -60,13 +61,23 @@
u8 byte;
int i;
const int ir_i2c_addr[] = {0x38, 0x08, 0x09};
+#ifdef CONFIG_DM_I2C
+ struct udevice *dev;
+#endif
/* Check all the address */
for (i = 0; i < (sizeof(ir_i2c_addr)/sizeof(ir_i2c_addr[0])); i++) {
i2caddress = ir_i2c_addr[i];
+#ifndef CONFIG_DM_I2C
ret = i2c_read(i2caddress,
IR36021_MFR_ID_OFFSET, 1, (void *)&byte,
sizeof(byte));
+#else
+ ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);
+ if (!ret)
+ ret = dm_i2c_read(dev, IR36021_MFR_ID_OFFSET,
+ (void *)&byte, sizeof(byte));
+#endif
if ((ret >= 0) && (byte == IR36021_MFR_ID))
return i2caddress;
}
@@ -102,11 +113,21 @@
int i, ret, voltage_read = 0;
u16 vol_mon;
u8 buf[2];
+#ifdef CONFIG_DM_I2C
+ struct udevice *dev;
+#endif
for (i = 0; i < NUM_READINGS; i++) {
+#ifndef CONFIG_DM_I2C
ret = i2c_read(I2C_VOL_MONITOR_ADDR,
I2C_VOL_MONITOR_BUS_V_OFFSET, 1,
(void *)&buf, 2);
+#else
+ ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev);
+ if (!ret)
+ ret = dm_i2c_read(dev, I2C_VOL_MONITOR_BUS_V_OFFSET,
+ (void *)&buf, 2);
+#endif
if (ret) {
printf("VID: failed to read core voltage\n");
return ret;
@@ -135,11 +156,21 @@
int i, ret, voltage_read = 0;
u16 vol_mon;
u8 buf;
+#ifdef CONFIG_DM_I2C
+ struct udevice *dev;
+#endif
for (i = 0; i < NUM_READINGS; i++) {
+#ifndef CONFIG_DM_I2C
ret = i2c_read(i2caddress,
IR36021_LOOP1_VOUT_OFFSET,
1, (void *)&buf, 1);
+#else
+ ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);
+ if (!ret)
+ ret = dm_i2c_read(dev, IR36021_LOOP1_VOUT_OFFSET,
+ (void *)&buf, 1);
+#endif
if (ret) {
printf("VID: failed to read vcpu\n");
return ret;
@@ -178,17 +209,33 @@
int ret, vcode = 0;
u8 chan = PWM_CHANNEL0;
+#ifndef CONFIG_DM_I2C
/* select the PAGE 0 using PMBus commands PAGE for VDD*/
ret = i2c_write(I2C_VOL_MONITOR_ADDR,
PMBUS_CMD_PAGE, 1, &chan, 1);
+#else
+ struct udevice *dev;
+
+ ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev);
+ if (!ret)
+ ret = dm_i2c_write(dev, PMBUS_CMD_PAGE, &chan, 1);
+#endif
if (ret) {
printf("VID: failed to select VDD Page 0\n");
return ret;
}
+#ifndef CONFIG_DM_I2C
/*read the output voltage using PMBus command READ_VOUT*/
ret = i2c_read(I2C_VOL_MONITOR_ADDR,
PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
+#else
+ ret = dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2);
+ if (ret) {
+ printf("VID: failed to read the volatge\n");
+ return ret;
+ }
+#endif
if (ret) {
printf("VID: failed to read the volatge\n");
return ret;
@@ -293,8 +340,18 @@
vid = DIV_ROUND_UP(vdd - 245, 5);
#endif
+#ifndef CONFIG_DM_I2C
ret = i2c_write(i2caddress, IR36021_LOOP1_MANUAL_ID_OFFSET,
1, (void *)&vid, sizeof(vid));
+#else
+ struct udevice *dev;
+
+ ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);
+ if (!ret)
+ ret = dm_i2c_write(dev, IR36021_LOOP1_MANUAL_ID_OFFSET,
+ (void *)&vid, sizeof(vid));
+
+#endif
if (ret) {
printf("VID: failed to write VID\n");
return -1;
@@ -330,8 +387,17 @@
vdd & 0xFF, (vdd & 0xFF00) >> 8};
/* Write the desired voltage code to the regulator */
+#ifndef CONFIG_DM_I2C
ret = i2c_write(I2C_VOL_MONITOR_ADDR,
PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
+#else
+ struct udevice *dev;
+
+ ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev);
+ if (!ret)
+ ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE,
+ (void *)&buff, 5);
+#endif
if (ret) {
printf("VID: I2C failed to write to the volatge regulator\n");
return -1;
@@ -515,14 +581,24 @@
}
/* check IR chip work on Intel mode*/
+#ifndef CONFIG_DM_I2C
ret = i2c_read(i2caddress,
IR36021_INTEL_MODE_OOFSET,
1, (void *)&buf, 1);
+#else
+ struct udevice *dev;
+
+ ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);
+ if (!ret)
+ ret = dm_i2c_read(dev, IR36021_INTEL_MODE_OOFSET,
+ (void *)&buf, 1);
+#endif
if (ret) {
printf("VID: failed to read IR chip mode.\n");
ret = -1;
goto exit;
}
+
if ((buf & IR36021_MODE_MASK) != IR36021_INTEL_MODE) {
printf("VID: IR Chip is not used in Intel mode.\n");
ret = -1;
@@ -687,9 +763,18 @@
}
/* check IR chip work on Intel mode*/
+#ifndef CONFIG_DM_I2C
ret = i2c_read(i2caddress,
IR36021_INTEL_MODE_OOFSET,
1, (void *)&buf, 1);
+#else
+ struct udevice *dev;
+
+ ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);
+ if (!ret)
+ ret = dm_i2c_read(dev, IR36021_INTEL_MODE_OOFSET,
+ (void *)&buf, 1);
+#endif
if (ret) {
printf("VID: failed to read IR chip mode.\n");
ret = -1;
diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c
index b166faf..3ce9a76 100644
--- a/board/freescale/corenet_ds/corenet_ds.c
+++ b/board/freescale/corenet_ds/corenet_ds.c
@@ -5,6 +5,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <netdev.h>
#include <linux/compiler.h>
#include <asm/mmu.h>
diff --git a/board/freescale/imx8mq_evk/imx8mq_evk.c b/board/freescale/imx8mq_evk/imx8mq_evk.c
index 54e0c38..1463e6e 100644
--- a/board/freescale/imx8mq_evk/imx8mq_evk.c
+++ b/board/freescale/imx8mq_evk/imx8mq_evk.c
@@ -4,6 +4,7 @@
*/
#include <common.h>
+#include <env.h>
#include <malloc.h>
#include <errno.h>
#include <asm/io.h>
@@ -11,7 +12,7 @@
#include <netdev.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm-generic/gpio.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <mmc.h>
#include <asm/arch/imx8mq_pins.h>
#include <asm/arch/sys_proto.h>
diff --git a/board/freescale/imx8mq_evk/spl.c b/board/freescale/imx8mq_evk/spl.c
index 3c0ff0b..9164cfb 100644
--- a/board/freescale/imx8mq_evk/spl.c
+++ b/board/freescale/imx8mq_evk/spl.c
@@ -16,7 +16,7 @@
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <mmc.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
diff --git a/board/freescale/imx8qm_mek/imx8qm_mek.c b/board/freescale/imx8qm_mek/imx8qm_mek.c
index e69efc4..76634a3 100644
--- a/board/freescale/imx8qm_mek/imx8qm_mek.c
+++ b/board/freescale/imx8qm_mek/imx8qm_mek.c
@@ -4,9 +4,9 @@
*/
#include <common.h>
+#include <env.h>
#include <errno.h>
#include <linux/libfdt.h>
-#include <environment.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/clock.h>
@@ -34,21 +34,11 @@
int board_early_init_f(void)
{
+ sc_pm_clock_rate_t rate = SC_80MHZ;
int ret;
+
/* Set UART0 clock root to 80 MHz */
- sc_pm_clock_rate_t rate = 80000000;
-
- /* Power up UART0 */
- ret = sc_pm_set_resource_power_mode(-1, SC_R_UART_0, SC_PM_PW_MODE_ON);
- if (ret)
- return ret;
-
- ret = sc_pm_set_clock_rate(-1, SC_R_UART_0, 2, &rate);
- if (ret)
- return ret;
-
- /* Enable UART0 clock root */
- ret = sc_pm_clock_enable(-1, SC_R_UART_0, 2, true, false);
+ ret = sc_pm_setup_uart(SC_R_UART_0, rate);
if (ret)
return ret;
@@ -88,19 +78,6 @@
}
#endif
-void build_info(void)
-{
- u32 sc_build = 0, sc_commit = 0;
-
- /* Get SCFW build and commit id */
- sc_misc_build_info(-1, &sc_build, &sc_commit);
- if (!sc_build) {
- printf("SCFW does not support build info\n");
- sc_commit = 0; /* Display 0 when the build info is not supported*/
- }
- printf("Build: SCFW %x\n", sc_commit);
-}
-
int checkboard(void)
{
puts("Board: iMX8QM MEK\n");
diff --git a/board/freescale/imx8qxp_mek/imx8qxp_mek.c b/board/freescale/imx8qxp_mek/imx8qxp_mek.c
index 63cd605..4ba8314 100644
--- a/board/freescale/imx8qxp_mek/imx8qxp_mek.c
+++ b/board/freescale/imx8qxp_mek/imx8qxp_mek.c
@@ -4,10 +4,10 @@
*/
#include <common.h>
+#include <env.h>
#include <errno.h>
#include <linux/libfdt.h>
-#include <environment.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/clock.h>
@@ -40,21 +40,11 @@
int board_early_init_f(void)
{
+ sc_pm_clock_rate_t rate = SC_80MHZ;
int ret;
+
/* Set UART0 clock root to 80 MHz */
- sc_pm_clock_rate_t rate = 80000000;
-
- /* Power up UART0 */
- ret = sc_pm_set_resource_power_mode(-1, SC_R_UART_0, SC_PM_PW_MODE_ON);
- if (ret)
- return ret;
-
- ret = sc_pm_set_clock_rate(-1, SC_R_UART_0, 2, &rate);
- if (ret)
- return ret;
-
- /* Enable UART0 clock root */
- ret = sc_pm_clock_enable(-1, SC_R_UART_0, 2, true, false);
+ ret = sc_pm_setup_uart(SC_R_UART_0, rate);
if (ret)
return ret;
@@ -104,19 +94,6 @@
}
#endif
-void build_info(void)
-{
- u32 sc_build = 0, sc_commit = 0;
-
- /* Get SCFW build and commit id */
- sc_misc_build_info(-1, &sc_build, &sc_commit);
- if (!sc_build) {
- printf("SCFW does not support build info\n");
- sc_commit = 0; /* Display 0 when the build info is not supported */
- }
- printf("Build: SCFW %x\n", sc_commit);
-}
-
int checkboard(void)
{
puts("Board: iMX8QXP MEK\n");
diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
index b4c611e..31e41ce 100644
--- a/board/freescale/ls1012afrdm/ls1012afrdm.c
+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
@@ -15,7 +15,7 @@
#include <asm/arch/soc.h>
#include <fsl_esdhc.h>
#include <hwconfig.h>
-#include <environment.h>
+#include <env_internal.h>
#include <fsl_mmdc.h>
#include <netdev.h>
#include <fsl_sec.h>
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
index a862fe6..86c72ee 100644
--- a/board/freescale/ls1012aqds/ls1012aqds.c
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
@@ -18,7 +18,7 @@
#include <ahci.h>
#include <hwconfig.h>
#include <mmc.h>
-#include <environment.h>
+#include <env_internal.h>
#include <scsi.h>
#include <fm_eth.h>
#include <fsl_esdhc.h>
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
index f648a90..e4527c1 100644
--- a/board/freescale/ls1012ardb/ls1012ardb.c
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
@@ -18,7 +18,7 @@
#include <mmc.h>
#include <scsi.h>
#include <fsl_esdhc.h>
-#include <environment.h>
+#include <env_internal.h>
#include <fsl_mmdc.h>
#include <netdev.h>
#include <fsl_sec.h>
diff --git a/board/freescale/ls1021aiot/dcu.c b/board/freescale/ls1021aiot/dcu.c
index 9aeee0e..77732a6 100644
--- a/board/freescale/ls1021aiot/dcu.c
+++ b/board/freescale/ls1021aiot/dcu.c
@@ -23,9 +23,10 @@
return div;
}
-int platform_dcu_init(unsigned int xres, unsigned int yres,
- const char *port,
- struct fb_videomode *dcu_fb_videomode)
+int platform_dcu_init(struct fb_info *fbinfo,
+ unsigned int xres, unsigned int yres,
+ const char *port,
+ struct fb_videomode *dcu_fb_videomode)
{
const char *name;
unsigned int pixel_format;
@@ -40,7 +41,7 @@
printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
pixel_format = 32;
- fsl_dcu_init(xres, yres, pixel_format);
+ fsl_dcu_init(fbinfo, xres, yres, pixel_format);
return 0;
}
diff --git a/board/freescale/ls1021aqds/dcu.c b/board/freescale/ls1021aqds/dcu.c
index 14855ea..c4eac5e 100644
--- a/board/freescale/ls1021aqds/dcu.c
+++ b/board/freescale/ls1021aqds/dcu.c
@@ -39,7 +39,9 @@
return div;
}
-int platform_dcu_init(unsigned int xres, unsigned int yres,
+int platform_dcu_init(struct fb_info *fbinfo,
+ unsigned int xres,
+ unsigned int yres,
const char *port,
struct fb_videomode *dcu_fb_videomode)
{
@@ -85,7 +87,7 @@
printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
pixel_format = 32;
- fsl_dcu_init(xres, yres, pixel_format);
+ fsl_dcu_init(fbinfo, xres, yres, pixel_format);
return 0;
}
diff --git a/board/freescale/ls1021atsn/Kconfig b/board/freescale/ls1021atsn/Kconfig
new file mode 100644
index 0000000..d999fa4
--- /dev/null
+++ b/board/freescale/ls1021atsn/Kconfig
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0
+if TARGET_LS1021ATSN
+
+config SYS_BOARD
+ default "ls1021atsn"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "ls102xa"
+
+config SYS_CONFIG_NAME
+ default "ls1021atsn"
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/board/freescale/ls1021atsn/MAINTAINERS b/board/freescale/ls1021atsn/MAINTAINERS
new file mode 100644
index 0000000..560bb61
--- /dev/null
+++ b/board/freescale/ls1021atsn/MAINTAINERS
@@ -0,0 +1,8 @@
+NXP LS1021A-TSN Board
+M: Vladimir Oltean <olteanv@gmail.com>
+S: Maintained
+F: arch/arm/dts/ls1021a-tsn.dts
+F: board/freescale/ls1021atsn/
+F: include/configs/ls1021atsn.h
+F: configs/ls1021atsn_qspi_defconfig
+F: configs/ls1021atsn_sdcard_defconfig
diff --git a/board/freescale/ls1021atsn/Makefile b/board/freescale/ls1021atsn/Makefile
new file mode 100644
index 0000000..b4808f0
--- /dev/null
+++ b/board/freescale/ls1021atsn/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-y += ls1021atsn.o
+obj-$(CONFIG_ARMV7_PSCI) += ../ls1021atwr/psci.o
diff --git a/board/freescale/ls1021atsn/README.rst b/board/freescale/ls1021atsn/README.rst
new file mode 100644
index 0000000..cdec02f
--- /dev/null
+++ b/board/freescale/ls1021atsn/README.rst
@@ -0,0 +1,97 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+LS1021A-TSN Board Overview
+==========================
+
+ - 1GB DDR3 at 800 MHz
+ - Spansion/Cypress 64 MB (Rev. A) / 32 MB (Rev. B and C) QSPI NOR flash
+ - Ethernet
+ - 2 SGMII 10/100/1G Ethernet ports (Atheros AR8031)
+ - One SJA1105T switch with 4 Ethernet ports (Broadcom BCM5464R)
+ - One internal RGMII port connected to the switch
+ - SDHC
+ - microSDHC/SDXC connector
+ - Other I/O
+ - One Serial port
+ - Arduino and expansion headers
+ - mPCIE slot
+ - SATA port
+ - USB3.0 port
+
+LS1021A Memory map
+==================
+
+The addresses in brackets are physical addresses.
+
+============== ============== ============================== =======
+Start Address End Address Description Size
+============== ============== ============================== =======
+0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB
+0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB
+0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB
+0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB
+0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB
+0x00_4000_0000 0x00_5FFF_FFFF QSPI 512MB
+0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB
+0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB
+============== ============== ============================== =======
+
+Compiling and flashing
+======================
+
+The LS1021A-TSN board comes along with a microSD card with OpenIL U-Boot that
+can be used to update its internal QSPI flash (which is empty out of the
+factory).
+
+To compile and flash an SD card image::
+
+ make ls1021atsn_sdcard_defconfig && make -j 8 && sudo cp u-boot-with-spl-pbl.bin /srv/tftpboot/
+ => tftp 0x82000000 u-boot-with-spl-pbl.bin && mmc rescan && mmc erase 8 0x1100 && mmc write 0x82000000 8 0x1100
+
+For the QSPI flash, first obtain the Reset Configuration Word binary for
+bootimg from the QSPI flash from the rcw project
+(https://source.codeaurora.org/external/qoriq/qoriq-components/rcw)::
+
+ make -j 8 && sudo cp ls1021atsn/SSR_PNS_30/rcw_1200_qspiboot.bin.swapped /srv/tftpboot/
+
+The above RCW binary takes care of swapping the QSPI AMBA memory, so that the
+U-Boot binary does not need to be swapped when flashing it.
+
+To compile and flash a U-Boot image for QSPI::
+
+ make ls1021atsn_qspi_defconfig && make -j 8 && sudo cp u-boot.bin /srv/tftpboot/
+
+Then optionally create a custom uboot-env.txt file (although the default
+environment already supports distro boot) and convert it to binary format::
+
+ mkenvimage -s 2M -o /srv/tftpboot/uboot-env.bin uboot-env.txt
+
+To program the QSPI flash with the images::
+
+ => tftp 0x82000000 rcw_1200_qspiboot.bin.swapped && sf probe && sf erase 0x0 +${filesize} && sf write 0x82000000 0x0 ${filesize}
+ => tftp 0x82000000 u-boot.bin && sf probe && sf erase 0x100000 +${filesize} && sf write 0x82000000 0x100000 ${filesize}
+ => tftp 0x82000000 uboot-env.bin && sf probe && sf erase 0x400000 +${filesize} && sf write 0x82000000 0x400000 ${filesize}
+
+The boards contain an AT24 I2C EEPROM that is supposed to hold the MAC
+addresses of the Ethernet interfaces, however the EEPROM comes blank out of
+the factory, and the MAC addresses are printed on a label on the bottom of
+the boards.
+
+To write the MAC addresses to the EEPROM, the following needs to be done once::
+
+ => mac id
+ => mac 0 00:1F:7B:xx:xx:xx
+ => mac 1 00:1F:7B:xx:xx:xx
+ => mac 2 00:1F:7B:xx:xx:xx
+ => mac save
+
+The switch ports do not have their own MAC address - they inherit it from the
+master enet2 port.
+
+Known issues and limitations
+============================
+
+- The 4 SJA1105 switch ports are not functional in U-Boot for now.
+- Since the IFC pins are multiplexed with QSPI on LS1021A, currently there is
+ no way to talk to the CPLD for e.g. running the "qixis_reset" command, or
+ turning the fan on, etc.
diff --git a/board/freescale/ls1021atsn/ls1021atsn.c b/board/freescale/ls1021atsn/ls1021atsn.c
new file mode 100644
index 0000000..39e825c
--- /dev/null
+++ b/board/freescale/ls1021atsn/ls1021atsn.c
@@ -0,0 +1,260 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2016-2019 NXP Semiconductors
+ */
+#include <common.h>
+#include <asm/arch-ls102xa/ls102xa_soc.h>
+#include <asm/arch/ls102xa_devdis.h>
+#include <asm/arch/immap_ls102xa.h>
+#include <asm/arch/ls102xa_soc.h>
+#include <asm/arch/fsl_serdes.h>
+#include "../common/sleep.h"
+#include <fsl_validate.h>
+#include <fsl_immap.h>
+#include <fsl_csu.h>
+#include <netdev.h>
+#include <spl.h>
+#ifdef CONFIG_U_QE
+#include <fsl_qe.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void ddrmc_init(void)
+{
+#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
+ struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
+ u32 temp_sdram_cfg, tmp;
+
+ out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
+
+ out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
+ out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
+
+ out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
+ out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
+ out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
+ out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
+ out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
+ out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
+
+#ifdef CONFIG_DEEP_SLEEP
+ if (is_warm_boot()) {
+ out_be32(&ddr->sdram_cfg_2,
+ DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
+ out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
+ out_be32(&ddr->init_ext_addr, (1 << 31));
+
+ /* DRAM VRef will not be trained */
+ out_be32(&ddr->ddr_cdr2,
+ DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
+ } else
+#endif
+ {
+ out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
+ out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
+ }
+
+ out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
+ out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
+
+ out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
+
+ out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
+
+ out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
+ out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
+
+ out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
+
+ out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
+ out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
+
+ out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
+
+ /* DDR erratum A-009942 */
+ tmp = in_be32(&ddr->debug[28]);
+ out_be32(&ddr->debug[28], tmp | 0x0070006f);
+
+ udelay(1);
+
+#ifdef CONFIG_DEEP_SLEEP
+ if (is_warm_boot()) {
+ /* enter self-refresh */
+ temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
+ temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
+ out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
+
+ temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
+ } else
+#endif
+ temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
+
+ out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
+
+#ifdef CONFIG_DEEP_SLEEP
+ if (is_warm_boot()) {
+ /* exit self-refresh */
+ temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
+ temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
+ out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
+ }
+#endif
+#endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
+}
+
+int dram_init(void)
+{
+ ddrmc_init();
+
+ erratum_a008850_post();
+
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
+ fsl_dp_resume();
+#endif
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+
+int board_early_init_f(void)
+{
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+#ifdef CONFIG_TSEC_ENET
+ /*
+ * Clear BD & FR bits for big endian BD's and frame data (aka set
+ * correct eTSEC endianness). This is crucial in ensuring that it does
+ * not report Data Parity Errors in its RX/TX FIFOs when attempting to
+ * send traffic.
+ */
+ clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
+ /* EC3_GTX_CLK125 (of enet2) used for all RGMII interfaces */
+ out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
+#endif
+
+ arch_soc_init();
+
+#if defined(CONFIG_DEEP_SLEEP)
+ if (is_warm_boot()) {
+ timer_init();
+ dram_init();
+ }
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+ void (*second_uboot)(void);
+
+ /* Clear the BSS */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ get_clocks();
+
+#if defined(CONFIG_DEEP_SLEEP)
+ if (is_warm_boot())
+ fsl_dp_disable_console();
+#endif
+
+ preloader_console_init();
+
+ dram_init();
+
+ /* Allow OCRAM access permission as R/W */
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+ enable_layerscape_ns_access();
+ enable_layerscape_ns_access();
+#endif
+
+ /*
+ * if it is woken up from deep sleep, then jump to second
+ * stage U-Boot and continue executing without recopying
+ * it from SD since it has already been reserved in memory
+ * in last boot.
+ */
+ if (is_warm_boot()) {
+ second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
+ second_uboot();
+ }
+
+ board_init_r(NULL, 0);
+}
+#endif
+
+int board_init(void)
+{
+#ifndef CONFIG_SYS_FSL_NO_SERDES
+ fsl_serdes_init();
+#endif
+ ls102xa_smmu_stream_id_init();
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+ enable_layerscape_ns_access();
+#endif
+
+#ifdef CONFIG_U_QE
+ u_qe_init();
+#endif
+
+ return 0;
+}
+
+#if defined(CONFIG_SPL_BUILD)
+void spl_board_init(void)
+{
+ ls102xa_smmu_stream_id_init();
+}
+#endif
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_CHAIN_OF_TRUST
+ fsl_setenv_chain_of_trust();
+#endif
+
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_MISC_INIT_R)
+int misc_init_r(void)
+{
+#ifdef CONFIG_FSL_DEVICE_DISABLE
+ device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
+#endif
+
+#ifdef CONFIG_FSL_CAAM
+ return sec_init();
+#endif
+}
+#endif
+
+#if defined(CONFIG_DEEP_SLEEP)
+void board_sleep_prepare(void)
+{
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+ enable_layerscape_ns_access();
+#endif
+}
+#endif
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_PCI
+ ft_pci_setup(blob, bd);
+#endif
+
+ return 0;
+}
diff --git a/board/freescale/ls1021atsn/ls102xa_pbi.cfg b/board/freescale/ls1021atsn/ls102xa_pbi.cfg
new file mode 100644
index 0000000..ba1499b
--- /dev/null
+++ b/board/freescale/ls1021atsn/ls102xa_pbi.cfg
@@ -0,0 +1,15 @@
+# PBI commands
+
+09570200 ffffffff
+09570158 00000300
+8940007c 21f47300
+
+# Configure Scratch register
+09ee0200 10000000
+# Configure alternate space
+09570158 00001000
+# Flush PBL data
+096100c0 000FFFFF
+
+09ea085c 00502880
+09ea0560 80800000
diff --git a/board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg b/board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg
new file mode 100644
index 0000000..a6fc914
--- /dev/null
+++ b/board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg
@@ -0,0 +1,8 @@
+# PBL preamble and RCW header
+aa55aa55 01ee0100
+
+# Disable IFC, enable QSPI and DSPI
+0608000c 00000000 00000000 00000000
+30000000 08007900 40105a00 21046000
+00000000 00000000 00000000 10002000
+20124801 8804b340 00000000 00000000
diff --git a/board/freescale/ls1021atwr/dcu.c b/board/freescale/ls1021atwr/dcu.c
index e1191f1..bdf7f76 100644
--- a/board/freescale/ls1021atwr/dcu.c
+++ b/board/freescale/ls1021atwr/dcu.c
@@ -23,7 +23,8 @@
return div;
}
-int platform_dcu_init(unsigned int xres, unsigned int yres,
+int platform_dcu_init(struct fb_info *fbinfo,
+ unsigned int xres, unsigned int yres,
const char *port,
struct fb_videomode *dcu_fb_videomode)
{
@@ -40,7 +41,7 @@
printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
pixel_format = 32;
- fsl_dcu_init(xres, yres, pixel_format);
+ fsl_dcu_init(fbinfo, xres, yres, pixel_format);
return 0;
}
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index 01ba1bc..fcf2ec9 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -248,44 +248,6 @@
int board_eth_init(bd_t *bis)
{
-#ifdef CONFIG_TSEC_ENET
- struct fsl_pq_mdio_info mdio_info;
- struct tsec_info_struct tsec_info[4];
- int num = 0;
-
-#ifdef CONFIG_TSEC1
- SET_STD_TSEC_INFO(tsec_info[num], 1);
- if (is_serdes_configured(SGMII_TSEC1)) {
- puts("eTSEC1 is in sgmii mode.\n");
- tsec_info[num].flags |= TSEC_SGMII;
- }
- num++;
-#endif
-#ifdef CONFIG_TSEC2
- SET_STD_TSEC_INFO(tsec_info[num], 2);
- if (is_serdes_configured(SGMII_TSEC2)) {
- puts("eTSEC2 is in sgmii mode.\n");
- tsec_info[num].flags |= TSEC_SGMII;
- }
- num++;
-#endif
-#ifdef CONFIG_TSEC3
- SET_STD_TSEC_INFO(tsec_info[num], 3);
- tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
- num++;
-#endif
- if (!num) {
- printf("No TSECs initialized\n");
- return 0;
- }
-
- mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
- mdio_info.name = DEFAULT_MII_NAME;
- fsl_pq_mdio_init(bis, &mdio_info);
-
- tsec_eth_init(bis, tsec_info, num);
-#endif
-
return pci_eth_init(bis);
}
diff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c
index e5de4eb..0959714 100644
--- a/board/freescale/ls1028a/ls1028a.c
+++ b/board/freescale/ls1028a/ls1028a.c
@@ -11,8 +11,9 @@
#include <hwconfig.h>
#include <fdt_support.h>
#include <linux/libfdt.h>
-#include <environment.h>
+#include <env_internal.h>
#include <asm/arch-fsl-layerscape/soc.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include <i2c.h>
#include <asm/arch/soc.h>
#ifdef CONFIG_FSL_LS_PPA
@@ -73,7 +74,15 @@
#if defined(CONFIG_TARGET_LS1028ARDB)
u8 val = I2C_MUX_CH_DEFAULT;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1);
+#else
+ struct udevice *dev;
+
+ if (!i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev))
+ dm_i2c_write(dev, 0x0b, &val, 1);
+#endif
+
#endif
return 0;
}
@@ -135,6 +144,8 @@
fdt_fixup_memory_banks(blob, base, size, 2);
+ fdt_fixup_icid(blob);
+
return 0;
}
#endif
diff --git a/board/freescale/ls1088a/eth_ls1088aqds.c b/board/freescale/ls1088a/eth_ls1088aqds.c
index f16b78c..237088a 100644
--- a/board/freescale/ls1088a/eth_ls1088aqds.c
+++ b/board/freescale/ls1088a/eth_ls1088aqds.c
@@ -5,6 +5,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/arch/fsl_serdes.h>
@@ -80,11 +81,16 @@
struct mii_dev *realbus;
};
+struct reg_pair {
+ uint addr;
+ u8 *val;
+};
+
static void sgmii_configure_repeater(int dpmac)
{
struct mii_dev *bus;
uint8_t a = 0xf;
- int i, j, ret;
+ int i, j, k, ret;
unsigned short value;
const char *dev = "LS1088A_QDS_MDIO2";
int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
@@ -96,8 +102,28 @@
uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
+ u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
+ struct reg_pair reg_pair[10] = {
+ {6, ®_val[0]}, {4, ®_val[1]},
+ {8, ®_val[2]}, {0xf, NULL},
+ {0x11, NULL}, {0x16, NULL},
+ {0x18, NULL}, {0x23, ®_val[3]},
+ {0x2d, ®_val[4]}, {4, ®_val[5]},
+ };
+#ifdef CONFIG_DM_I2C
+ struct udevice *udev;
+#endif
+
/* Set I2c to Slot 1 */
- i2c_write(0x77, 0, 0, &a, 1);
+#ifndef CONFIG_DM_I2C
+ ret = i2c_write(0x77, 0, 0, &a, 1);
+#else
+ ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
+ if (!ret)
+ ret = dm_i2c_write(udev, 0, &a, 1);
+#endif
+ if (ret)
+ goto error;
switch (dpmac) {
case 1:
@@ -143,31 +169,34 @@
return;
}
+#ifdef CONFIG_DM_I2C
+ i2c_get_chip_for_busnum(0, i2c_phy_addr, 1, &udev);
+#endif
+
for (i = 0; i < 4; i++) {
for (j = 0; j < 4; j++) {
- a = 0x18;
- i2c_write(i2c_phy_addr, 6, 1, &a, 1);
- a = 0x38;
- i2c_write(i2c_phy_addr, 4, 1, &a, 1);
- a = 0x4;
- i2c_write(i2c_phy_addr, 8, 1, &a, 1);
+ reg_pair[3].val = &ch_a_eq[i];
+ reg_pair[4].val = &ch_a_ctl2[j];
+ reg_pair[5].val = &ch_b_eq[i];
+ reg_pair[6].val = &ch_b_ctl2[j];
+ for (k = 0; k < 10; k++) {
+#ifndef CONFIG_DM_I2C
+ ret = i2c_write(i2c_phy_addr,
+ reg_pair[k].addr,
+ 1, reg_pair[k].val, 1);
+#else
+ ret = i2c_get_chip_for_busnum(0,
+ i2c_phy_addr,
+ 1, &udev);
+ if (!ret)
+ ret = dm_i2c_write(udev,
+ reg_pair[k].addr,
+ reg_pair[k].val, 1);
+#endif
+ if (ret)
+ goto error;
+ }
- i2c_write(i2c_phy_addr, 0xf, 1,
- &ch_a_eq[i], 1);
- i2c_write(i2c_phy_addr, 0x11, 1,
- &ch_a_ctl2[j], 1);
-
- i2c_write(i2c_phy_addr, 0x16, 1,
- &ch_b_eq[i], 1);
- i2c_write(i2c_phy_addr, 0x18, 1,
- &ch_b_ctl2[j], 1);
-
- a = 0x14;
- i2c_write(i2c_phy_addr, 0x23, 1, &a, 1);
- a = 0xb5;
- i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);
- a = 0x20;
- i2c_write(i2c_phy_addr, 4, 1, &a, 1);
mdelay(100);
ret = miiphy_read(dev, phy_addr, 0x11, &value);
if (ret > 0)
@@ -202,7 +231,7 @@
static void qsgmii_configure_repeater(int dpmac)
{
uint8_t a = 0xf;
- int i, j;
+ int i, j, k;
int i2c_phy_addr = 0;
int phy_addr = 0;
int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
@@ -212,12 +241,32 @@
uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
+ u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
+ struct reg_pair reg_pair[10] = {
+ {6, ®_val[0]}, {4, ®_val[1]},
+ {8, ®_val[2]}, {0xf, NULL},
+ {0x11, NULL}, {0x16, NULL},
+ {0x18, NULL}, {0x23, ®_val[3]},
+ {0x2d, ®_val[4]}, {4, ®_val[5]},
+ };
+
const char *dev = mdio_names[EMI1_SLOT1];
int ret = 0;
unsigned short value;
+#ifdef CONFIG_DM_I2C
+ struct udevice *udev;
+#endif
/* Set I2c to Slot 1 */
- i2c_write(0x77, 0, 0, &a, 1);
+#ifndef CONFIG_DM_I2C
+ ret = i2c_write(0x77, 0, 0, &a, 1);
+#else
+ ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
+ if (!ret)
+ ret = dm_i2c_write(udev, 0, &a, 1);
+#endif
+ if (ret)
+ goto error;
switch (dpmac) {
case 7:
@@ -251,28 +300,35 @@
return;
}
+#ifdef CONFIG_DM_I2C
+ i2c_get_chip_for_busnum(0, i2c_phy_addr, 1, &udev);
+#endif
+
for (i = 0; i < 4; i++) {
for (j = 0; j < 4; j++) {
- a = 0x18;
- i2c_write(i2c_phy_addr, 6, 1, &a, 1);
- a = 0x38;
- i2c_write(i2c_phy_addr, 4, 1, &a, 1);
- a = 0x4;
- i2c_write(i2c_phy_addr, 8, 1, &a, 1);
+ reg_pair[3].val = &ch_a_eq[i];
+ reg_pair[4].val = &ch_a_ctl2[j];
+ reg_pair[5].val = &ch_b_eq[i];
+ reg_pair[6].val = &ch_b_ctl2[j];
- i2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1);
- i2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1);
+ for (k = 0; k < 10; k++) {
+#ifndef CONFIG_DM_I2C
+ ret = i2c_write(i2c_phy_addr,
+ reg_pair[k].addr,
+ 1, reg_pair[k].val, 1);
+#else
+ ret = i2c_get_chip_for_busnum(0,
+ i2c_addr[dpmac],
+ 1, &udev);
+ if (!ret)
+ ret = dm_i2c_write(udev,
+ reg_pair[k].addr,
+ reg_pair[k].val, 1);
+#endif
+ if (ret)
+ goto error;
+ }
- i2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1);
- i2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1);
-
- a = 0x14;
- i2c_write(i2c_phy_addr, 0x23, 1, &a, 1);
- a = 0xb5;
- i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);
- a = 0x20;
- i2c_write(i2c_phy_addr, 4, 1, &a, 1);
- mdelay(100);
ret = miiphy_read(dev, phy_addr, 0x11, &value);
if (ret > 0)
goto error;
diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c
index 6d11a13..f159298 100644
--- a/board/freescale/ls1088a/ls1088a.c
+++ b/board/freescale/ls1088a/ls1088a.c
@@ -3,6 +3,7 @@
* Copyright 2017-2018 NXP
*/
#include <common.h>
+#include <env.h>
#include <i2c.h>
#include <malloc.h>
#include <errno.h>
@@ -14,12 +15,13 @@
#include <fdt_support.h>
#include <linux/libfdt.h>
#include <fsl-mc/fsl_mc.h>
-#include <environment.h>
+#include <env_internal.h>
#include <asm/arch-fsl-layerscape/soc.h>
#include <asm/arch/ppa.h>
#include <hwconfig.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/soc.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include "../common/qixis.h"
#include "ls1088a_qixis.h"
@@ -373,7 +375,15 @@
{
int ret;
+#ifndef CONFIG_DM_I2C
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+#else
+ struct udevice *dev;
+
+ ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
+ if (!ret)
+ ret = dm_i2c_write(dev, 0, &ch, 1);
+#endif
if (ret) {
puts("PCA: failed to select proper channel\n");
return ret;
@@ -392,38 +402,89 @@
/* Access to Control/Shared register */
reg = 0x0;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
+#else
+ struct udevice *dev;
+
+ i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR, 1, &dev);
+ dm_i2c_write(dev, 0xff, ®, 1);
+#endif
/* Read device revision and ID */
+#ifndef CONFIG_DM_I2C
i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
+#else
+ dm_i2c_read(dev, 1, ®, 1);
+#endif
debug("Retimer version id = 0x%x\n", reg);
/* Enable Broadcast. All writes target all channel register sets */
reg = 0x0c;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
+#else
+ dm_i2c_write(dev, 0xff, ®, 1);
+#endif
/* Reset Channel Registers */
+#ifndef CONFIG_DM_I2C
i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
+#else
+ dm_i2c_read(dev, 0, ®, 1);
+#endif
reg |= 0x4;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
+#else
+ dm_i2c_write(dev, 0, ®, 1);
+#endif
/* Set data rate as 10.3125 Gbps */
reg = 0x90;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
+#else
+ dm_i2c_write(dev, 0x60, ®, 1);
+#endif
reg = 0xb3;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
+#else
+ dm_i2c_write(dev, 0x61, ®, 1);
+#endif
reg = 0x90;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
+#else
+ dm_i2c_write(dev, 0x62, ®, 1);
+#endif
reg = 0xb3;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
+#else
+ dm_i2c_write(dev, 0x63, ®, 1);
+#endif
reg = 0xcd;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
+#else
+ dm_i2c_write(dev, 0x64, ®, 1);
+#endif
/* Select VCO Divider to full rate (000) */
+#ifndef CONFIG_DM_I2C
i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
+#else
+ dm_i2c_read(dev, 0x2F, ®, 1);
+#endif
reg &= 0x0f;
reg |= 0x70;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
+#else
+ dm_i2c_write(dev, 0x2F, ®, 1);
+#endif
#ifdef CONFIG_TARGET_LS1088AQDS
/* Retimer is connected to I2C1_CH5 */
@@ -431,38 +492,88 @@
/* Access to Control/Shared register */
reg = 0x0;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
+#else
+ i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR2, 1, &dev);
+ dm_i2c_write(dev, 0xff, ®, 1);
+#endif
/* Read device revision and ID */
+#ifndef CONFIG_DM_I2C
i2c_read(I2C_RETIMER_ADDR2, 1, 1, ®, 1);
+#else
+ dm_i2c_read(dev, 1, ®, 1);
+#endif
debug("Retimer version id = 0x%x\n", reg);
/* Enable Broadcast. All writes target all channel register sets */
reg = 0x0c;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
+#else
+ dm_i2c_write(dev, 0xff, ®, 1);
+#endif
/* Reset Channel Registers */
+#ifndef CONFIG_DM_I2C
i2c_read(I2C_RETIMER_ADDR2, 0, 1, ®, 1);
+#else
+ dm_i2c_read(dev, 0, ®, 1);
+#endif
reg |= 0x4;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR2, 0, 1, ®, 1);
+#else
+ dm_i2c_write(dev, 0, ®, 1);
+#endif
/* Set data rate as 10.3125 Gbps */
reg = 0x90;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, ®, 1);
+#else
+ dm_i2c_write(dev, 0x60, ®, 1);
+#endif
reg = 0xb3;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, ®, 1);
+#else
+ dm_i2c_write(dev, 0x61, ®, 1);
+#endif
reg = 0x90;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, ®, 1);
+#else
+ dm_i2c_write(dev, 0x62, ®, 1);
+#endif
reg = 0xb3;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, ®, 1);
+#else
+ dm_i2c_write(dev, 0x63, ®, 1);
+#endif
reg = 0xcd;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, ®, 1);
+#else
+ dm_i2c_write(dev, 0x64, ®, 1);
+#endif
/* Select VCO Divider to full rate (000) */
+#ifndef CONFIG_DM_I2C
i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1);
+#else
+ dm_i2c_read(dev, 0x2F, ®, 1);
+#endif
reg &= 0x0f;
reg |= 0x70;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1);
+#else
+ dm_i2c_write(dev, 0x2F, ®, 1);
+#endif
+
#endif
/*return the default channel*/
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
@@ -481,6 +592,32 @@
QIXIS_WRITE(brdcfg[5], brdcfg5);
}
#endif
+
+#ifdef CONFIG_TARGET_LS1088AQDS
+ u8 brdcfg4, brdcfg5;
+
+ if (hwconfig("dspi-on-board")) {
+ brdcfg4 = QIXIS_READ(brdcfg[4]);
+ brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
+ brdcfg4 |= BRDCFG4_SPI;
+ QIXIS_WRITE(brdcfg[4], brdcfg4);
+
+ brdcfg5 = QIXIS_READ(brdcfg[5]);
+ brdcfg5 &= ~BRDCFG5_SPR_MASK;
+ brdcfg5 |= BRDCFG5_SPI_ON_BOARD;
+ QIXIS_WRITE(brdcfg[5], brdcfg5);
+ } else if (hwconfig("dspi-off-board")) {
+ brdcfg4 = QIXIS_READ(brdcfg[4]);
+ brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
+ brdcfg4 |= BRDCFG4_SPI;
+ QIXIS_WRITE(brdcfg[4], brdcfg4);
+
+ brdcfg5 = QIXIS_READ(brdcfg[5]);
+ brdcfg5 &= ~BRDCFG5_SPR_MASK;
+ brdcfg5 |= BRDCFG5_SPI_OFF_BOARD;
+ QIXIS_WRITE(brdcfg[5], brdcfg5);
+ }
+#endif
return 0;
}
#endif
@@ -499,16 +636,30 @@
u8 chan = PWM_CHANNEL0;
/* Select the PAGE 0 using PMBus commands PAGE for VDD */
+#ifndef CONFIG_DM_I2C
ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
PMBUS_CMD_PAGE, 1, &chan, 1);
+#else
+ struct udevice *dev;
+
+ ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
+ if (!ret)
+ ret = dm_i2c_write(dev, PMBUS_CMD_PAGE,
+ &chan, 1);
+#endif
+
if (ret) {
printf("VID: failed to select VDD Page 0\n");
return ret;
}
/* Read the output voltage using PMBus command READ_VOUT */
+#ifndef CONFIG_DM_I2C
ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
+#else
+ dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2);
+#endif
if (ret) {
printf("VID: failed to read the volatge\n");
return ret;
@@ -524,8 +675,17 @@
svdd & 0xFF, (svdd & 0xFF00) >> 8};
/* Write the desired voltage code to the SVDD regulator */
+#ifndef CONFIG_DM_I2C
ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
+#else
+ struct udevice *dev;
+
+ ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
+ if (!ret)
+ ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE,
+ (void *)&buff, 5);
+#endif
if (ret) {
printf("VID: I2C failed to write to the volatge regulator\n");
return -1;
@@ -556,8 +716,18 @@
printf("SVDD changing of RDB\n");
/* Read the BRDCFG54 via CLPD */
+#ifndef CONFIG_DM_I2C
ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
+#else
+ struct udevice *dev;
+
+ ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev);
+ if (!ret)
+ ret = dm_i2c_read(dev, QIXIS_BRDCFG4_OFFSET,
+ (void *)&brdcfg4, 1);
+#endif
+
if (ret) {
printf("VID: I2C failed to read the CPLD BRDCFG4\n");
return -1;
@@ -566,8 +736,14 @@
brdcfg4 = brdcfg4 | 0x08;
/* Write to the BRDCFG4 */
+#ifndef CONFIG_DM_I2C
ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
+#else
+ ret = dm_i2c_write(dev, QIXIS_BRDCFG4_OFFSET,
+ (void *)&brdcfg4, 1);
+#endif
+
if (ret) {
debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
return -1;
@@ -738,11 +914,26 @@
int ft_board_setup(void *blob, bd_t *bd)
{
int i;
- u64 base[CONFIG_NR_DRAM_BANKS];
- u64 size[CONFIG_NR_DRAM_BANKS];
+ u16 mc_memory_bank = 0;
+
+ u64 *base;
+ u64 *size;
+ u64 mc_memory_base = 0;
+ u64 mc_memory_size = 0;
+ u16 total_memory_banks;
ft_cpu_setup(blob, bd);
+ fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
+
+ if (mc_memory_base != 0)
+ mc_memory_bank++;
+
+ total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
+
+ base = calloc(total_memory_banks, sizeof(u64));
+ size = calloc(total_memory_banks, sizeof(u64));
+
/* fixup DT for the two GPP DDR banks */
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
base[i] = gd->bd->bi_dram[i].start;
@@ -759,7 +950,17 @@
size[1] = gd->arch.resv_ram - base[1];
#endif
- fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
+ if (mc_memory_base != 0) {
+ for (i = 0; i <= total_memory_banks; i++) {
+ if (base[i] == 0 && size[i] == 0) {
+ base[i] = mc_memory_base;
+ size[i] = mc_memory_size;
+ break;
+ }
+ }
+ }
+
+ fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
fdt_fsl_mc_fixup_iommu_map_entry(blob);
@@ -768,6 +969,9 @@
#ifdef CONFIG_FSL_MC_ENET
fdt_fixup_board_enet(blob);
#endif
+
+ fdt_fixup_icid(blob);
+
if (is_pb_board())
fixup_ls1088ardb_pb_banner(blob);
diff --git a/board/freescale/ls1088a/ls1088a_qixis.h b/board/freescale/ls1088a/ls1088a_qixis.h
index c588526..e3502eb 100644
--- a/board/freescale/ls1088a/ls1088a_qixis.h
+++ b/board/freescale/ls1088a/ls1088a_qixis.h
@@ -41,4 +41,15 @@
#define BRDCFG5_SPISDHC_MASK 0x0C
#define BRDCFG5_FORCE_SD 0x08
+/* Definitions of QIXIS Registers for LS1088AQDS */
+
+/* BRDCFG4 */
+#define BRDCFG4_USBOSC_MASK 0x01
+#define BRDCFG4_SPI 0x01
+
+/* BRDCFG5 */
+#define BRDCFG5_SPR_MASK 0x0f
+#define BRDCFG5_SPI_ON_BOARD 0x0a
+#define BRDCFG5_SPI_OFF_BOARD 0x0f
+
#endif
diff --git a/board/freescale/ls2080a/ls2080a.c b/board/freescale/ls2080a/ls2080a.c
index cc1822d..413a698 100644
--- a/board/freescale/ls2080a/ls2080a.c
+++ b/board/freescale/ls2080a/ls2080a.c
@@ -12,7 +12,7 @@
#include <fdt_support.h>
#include <linux/libfdt.h>
#include <fsl-mc/fsl_mc.h>
-#include <environment.h>
+#include <env_internal.h>
#include <asm/arch/soc.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c
index f706fd4..6a8788c 100644
--- a/board/freescale/ls2080aqds/eth.c
+++ b/board/freescale/ls2080aqds/eth.c
@@ -4,6 +4,7 @@
*/
#include <common.h>
+#include <env.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/arch/fsl_serdes.h>
@@ -89,11 +90,16 @@
struct mii_dev *realbus;
};
+struct reg_pair {
+ uint addr;
+ u8 *val;
+};
+
static void sgmii_configure_repeater(int serdes_port)
{
struct mii_dev *bus;
uint8_t a = 0xf;
- int i, j, ret;
+ int i, j, k, ret;
int dpmac_id = 0, dpmac, mii_bus = 0;
unsigned short value;
char dev[2][20] = {"LS2080A_QDS_MDIO0", "LS2080A_QDS_MDIO3"};
@@ -104,10 +110,30 @@
uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
+ u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
+ struct reg_pair reg_pair[10] = {
+ {6, ®_val[0]}, {4, ®_val[1]},
+ {8, ®_val[2]}, {0xf, NULL},
+ {0x11, NULL}, {0x16, NULL},
+ {0x18, NULL}, {0x23, ®_val[3]},
+ {0x2d, ®_val[4]}, {4, ®_val[5]},
+ };
+
int *riser_phy_addr = &xqsgii_riser_phy_addr[0];
+#ifdef CONFIG_DM_I2C
+ struct udevice *udev;
+#endif
/* Set I2c to Slot 1 */
- i2c_write(0x77, 0, 0, &a, 1);
+#ifndef CONFIG_DM_I2C
+ ret = i2c_write(0x77, 0, 0, &a, 1);
+#else
+ ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
+ if (!ret)
+ ret = dm_i2c_write(udev, 0, &a, 1);
+#endif
+ if (ret)
+ goto error;
for (dpmac = 0; dpmac < 8; dpmac++) {
/* Check the PHY status */
@@ -120,7 +146,15 @@
mii_bus = 1;
dpmac_id = dpmac + 9;
a = 0xb;
- i2c_write(0x76, 0, 0, &a, 1);
+#ifndef CONFIG_DM_I2C
+ ret = i2c_write(0x76, 0, 0, &a, 1);
+#else
+ ret = i2c_get_chip_for_busnum(0, 0x76, 1, &udev);
+ if (!ret)
+ ret = dm_i2c_write(udev, 0, &a, 1);
+#endif
+ if (ret)
+ goto error;
break;
}
@@ -153,29 +187,29 @@
for (i = 0; i < 4; i++) {
for (j = 0; j < 4; j++) {
- a = 0x18;
- i2c_write(i2c_addr[dpmac], 6, 1, &a, 1);
- a = 0x38;
- i2c_write(i2c_addr[dpmac], 4, 1, &a, 1);
- a = 0x4;
- i2c_write(i2c_addr[dpmac], 8, 1, &a, 1);
+ reg_pair[3].val = &ch_a_eq[i];
+ reg_pair[4].val = &ch_a_ctl2[j];
+ reg_pair[5].val = &ch_b_eq[i];
+ reg_pair[6].val = &ch_b_ctl2[j];
- i2c_write(i2c_addr[dpmac], 0xf, 1,
- &ch_a_eq[i], 1);
- i2c_write(i2c_addr[dpmac], 0x11, 1,
- &ch_a_ctl2[j], 1);
+ for (k = 0; k < 10; k++) {
+#ifndef CONFIG_DM_I2C
+ ret = i2c_write(i2c_addr[dpmac],
+ reg_pair[k].addr,
+ 1, reg_pair[k].val, 1);
+#else
+ ret = i2c_get_chip_for_busnum(0,
+ i2c_addr[dpmac],
+ 1, &udev);
+ if (!ret)
+ ret = dm_i2c_write(udev,
+ reg_pair[k].addr,
+ reg_pair[k].val, 1);
+#endif
+ if (ret)
+ goto error;
+ }
- i2c_write(i2c_addr[dpmac], 0x16, 1,
- &ch_b_eq[i], 1);
- i2c_write(i2c_addr[dpmac], 0x18, 1,
- &ch_b_ctl2[j], 1);
-
- a = 0x14;
- i2c_write(i2c_addr[dpmac], 0x23, 1, &a, 1);
- a = 0xb5;
- i2c_write(i2c_addr[dpmac], 0x2d, 1, &a, 1);
- a = 0x20;
- i2c_write(i2c_addr[dpmac], 4, 1, &a, 1);
mdelay(100);
ret = miiphy_read(dev[mii_bus],
riser_phy_addr[dpmac],
@@ -216,7 +250,7 @@
static void qsgmii_configure_repeater(int dpmac)
{
uint8_t a = 0xf;
- int i, j;
+ int i, j, k;
int i2c_phy_addr = 0;
int phy_addr = 0;
int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
@@ -226,12 +260,32 @@
uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
+ u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
+ struct reg_pair reg_pair[10] = {
+ {6, ®_val[0]}, {4, ®_val[1]},
+ {8, ®_val[2]}, {0xf, NULL},
+ {0x11, NULL}, {0x16, NULL},
+ {0x18, NULL}, {0x23, ®_val[3]},
+ {0x2d, ®_val[4]}, {4, ®_val[5]},
+ };
+
const char *dev = "LS2080A_QDS_MDIO0";
int ret = 0;
unsigned short value;
+#ifdef CONFIG_DM_I2C
+ struct udevice *udev;
+#endif
/* Set I2c to Slot 1 */
- i2c_write(0x77, 0, 0, &a, 1);
+#ifndef CONFIG_DM_I2C
+ ret = i2c_write(0x77, 0, 0, &a, 1);
+#else
+ ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
+ if (!ret)
+ ret = dm_i2c_write(udev, 0, &a, 1);
+#endif
+ if (ret)
+ goto error;
switch (dpmac) {
case 1:
@@ -282,25 +336,29 @@
for (i = 0; i < 4; i++) {
for (j = 0; j < 4; j++) {
- a = 0x18;
- i2c_write(i2c_phy_addr, 6, 1, &a, 1);
- a = 0x38;
- i2c_write(i2c_phy_addr, 4, 1, &a, 1);
- a = 0x4;
- i2c_write(i2c_phy_addr, 8, 1, &a, 1);
+ reg_pair[3].val = &ch_a_eq[i];
+ reg_pair[4].val = &ch_a_ctl2[j];
+ reg_pair[5].val = &ch_b_eq[i];
+ reg_pair[6].val = &ch_b_ctl2[j];
- i2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1);
- i2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1);
+ for (k = 0; k < 10; k++) {
+#ifndef CONFIG_DM_I2C
+ ret = i2c_write(i2c_phy_addr,
+ reg_pair[k].addr,
+ 1, reg_pair[k].val, 1);
+#else
+ ret = i2c_get_chip_for_busnum(0,
+ i2c_phy_addr,
+ 1, &udev);
+ if (!ret)
+ ret = dm_i2c_write(udev,
+ reg_pair[k].addr,
+ reg_pair[k].val, 1);
+#endif
+ if (ret)
+ goto error;
+ }
- i2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1);
- i2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1);
-
- a = 0x14;
- i2c_write(i2c_phy_addr, 0x23, 1, &a, 1);
- a = 0xb5;
- i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);
- a = 0x20;
- i2c_write(i2c_phy_addr, 4, 1, &a, 1);
mdelay(100);
ret = miiphy_read(dev, phy_addr, 0x11, &value);
if (ret > 0)
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c
index a0a3301..91c8035 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -3,6 +3,7 @@
* Copyright 2015 Freescale Semiconductor
*/
#include <common.h>
+#include <env.h>
#include <malloc.h>
#include <errno.h>
#include <netdev.h>
@@ -12,7 +13,7 @@
#include <fdt_support.h>
#include <linux/libfdt.h>
#include <fsl-mc/fsl_mc.h>
-#include <environment.h>
+#include <env_internal.h>
#include <i2c.h>
#include <rtc.h>
#include <asm/arch/soc.h>
@@ -160,8 +161,16 @@
int select_i2c_ch_pca9547(u8 ch)
{
int ret;
+#ifdef CONFIG_DM_I2C
+ struct udevice *dev;
+ ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
+ if (!ret)
+ ret = dm_i2c_write(dev, 0, &ch, 1);
+
+#else
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+#endif
if (ret) {
puts("PCA: failed to select proper channel\n");
return ret;
@@ -224,7 +233,15 @@
gd->env_addr = (ulong)&default_environment[0];
#endif
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+
+#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT
+#ifdef CONFIG_DM_I2C
+ rtc_enable_32khz_output(0, CONFIG_SYS_I2C_RTC_ADDR);
+#else
rtc_enable_32khz_output();
+#endif
+#endif
+
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index ce419df..e20267f 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -4,6 +4,7 @@
* Copyright 2017 NXP
*/
#include <common.h>
+#include <env.h>
#include <malloc.h>
#include <errno.h>
#include <netdev.h>
@@ -14,7 +15,7 @@
#include <fdt_support.h>
#include <linux/libfdt.h>
#include <fsl-mc/fsl_mc.h>
-#include <environment.h>
+#include <env_internal.h>
#include <efi_loader.h>
#include <i2c.h>
#include <asm/arch/mmu.h>
@@ -163,7 +164,16 @@
{
int ret;
+#ifndef CONFIG_DM_I2C
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+#else
+ struct udevice *dev;
+
+ ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
+ if (!ret)
+ ret = dm_i2c_write(dev, 0, &ch, 1);
+#endif
+
if (ret) {
puts("PCA: failed to select proper channel\n");
return ret;
@@ -409,11 +419,27 @@
int ft_board_setup(void *blob, bd_t *bd)
{
- u64 base[CONFIG_NR_DRAM_BANKS];
- u64 size[CONFIG_NR_DRAM_BANKS];
+ int i;
+ u16 mc_memory_bank = 0;
+
+ u64 *base;
+ u64 *size;
+ u64 mc_memory_base = 0;
+ u64 mc_memory_size = 0;
+ u16 total_memory_banks;
ft_cpu_setup(blob, bd);
+ fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
+
+ if (mc_memory_base != 0)
+ mc_memory_bank++;
+
+ total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
+
+ base = calloc(total_memory_banks, sizeof(u64));
+ size = calloc(total_memory_banks, sizeof(u64));
+
/* fixup DT for the two GPP DDR banks */
base[0] = gd->bd->bi_dram[0].start;
size[0] = gd->bd->bi_dram[0].size;
@@ -430,7 +456,17 @@
size[1] = gd->arch.resv_ram - base[1];
#endif
- fdt_fixup_memory_banks(blob, base, size, 2);
+ if (mc_memory_base != 0) {
+ for (i = 0; i <= total_memory_banks; i++) {
+ if (base[i] == 0 && size[i] == 0) {
+ base[i] = mc_memory_base;
+ size[i] = mc_memory_size;
+ break;
+ }
+ }
+ }
+
+ fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
fdt_fsl_mc_fixup_iommu_map_entry(blob);
diff --git a/board/freescale/lx2160a/eth_lx2160aqds.c b/board/freescale/lx2160a/eth_lx2160aqds.c
index f6e22d7..55e8a42 100644
--- a/board/freescale/lx2160a/eth_lx2160aqds.c
+++ b/board/freescale/lx2160a/eth_lx2160aqds.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
+#include <env.h>
#include <hwconfig.h>
#include <command.h>
#include <netdev.h>
@@ -104,6 +105,8 @@
EMI1, IO_SLOT_1},
{WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
EMI1, IO_SLOT_2} } },
+ {14, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+ EMI1, IO_SLOT_1} } },
{15, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
EMI1, IO_SLOT_1},
{WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
@@ -685,7 +688,7 @@
struct phy_device *phy_dev, int phandle)
{
char phy_node_name[] = "ethernet-phy@00";
- char phy_id_compatible_str[] = "ethernet-phy-id0000.0000";
+ char phy_id_compatible_str[] = "ethernet-phy-id0000.0000,";
int ret;
sprintf(phy_node_name, "ethernet-phy@%x", phyaddr);
@@ -699,7 +702,7 @@
return *subnodeoffset;
}
- sprintf(phy_id_compatible_str, "ethernet-phy-id%04x.%04x",
+ sprintf(phy_id_compatible_str, "ethernet-phy-id%04x.%04x,",
phy_dev->phy_id >> 16, phy_dev->phy_id & 0xFFFF);
debug("phy_id_compatible_str %s\n", phy_id_compatible_str);
diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c
index 3b4cb86..b509c03 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -16,10 +16,12 @@
#include <fdt_support.h>
#include <linux/libfdt.h>
#include <fsl-mc/fsl_mc.h>
-#include <environment.h>
+#include <env_internal.h>
#include <efi_loader.h>
#include <asm/arch/mmu.h>
#include <hwconfig.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/config.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/soc.h>
#include "../common/qixis.h"
@@ -74,7 +76,15 @@
{
int ret;
+#ifndef CONFIG_DM_I2C
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+#else
+ struct udevice *dev;
+
+ ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
+ if (!ret)
+ ret = dm_i2c_write(dev, 0, &ch, 1);
+#endif
if (ret) {
puts("PCA: failed to select proper channel\n");
return ret;
@@ -108,6 +118,72 @@
return 0;
}
+#ifdef CONFIG_OF_BOARD_FIXUP
+int board_fix_fdt(void *fdt)
+{
+ char *reg_names, *reg_name;
+ int names_len, old_name_len, new_name_len, remaining_names_len;
+ struct str_map {
+ char *old_str;
+ char *new_str;
+ } reg_names_map[] = {
+ { "ccsr", "dip" },
+ { "pf_ctrl", "ctrl" }
+ };
+ int off = -1, i;
+
+ if (IS_SVR_REV(get_svr(), 1, 0))
+ return 0;
+
+ off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie");
+ while (off != -FDT_ERR_NOTFOUND) {
+ fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie",
+ strlen("fsl,ls-pcie") + 1);
+
+ reg_names = (char *)fdt_getprop(fdt, off, "reg-names",
+ &names_len);
+ if (!reg_names)
+ continue;
+
+ reg_name = reg_names;
+ remaining_names_len = names_len - (reg_name - reg_names);
+ for (i = 0; (i < ARRAY_SIZE(reg_names_map)) && names_len; i++) {
+ old_name_len = strlen(reg_names_map[i].old_str);
+ new_name_len = strlen(reg_names_map[i].new_str);
+ if (memcmp(reg_name, reg_names_map[i].old_str,
+ old_name_len) == 0) {
+ /* first only leave required bytes for new_str
+ * and copy rest of the string after it
+ */
+ memcpy(reg_name + new_name_len,
+ reg_name + old_name_len,
+ remaining_names_len - old_name_len);
+ /* Now copy new_str */
+ memcpy(reg_name, reg_names_map[i].new_str,
+ new_name_len);
+ names_len -= old_name_len;
+ names_len += new_name_len;
+ }
+
+ reg_name = memchr(reg_name, '\0', remaining_names_len);
+ if (!reg_name)
+ break;
+
+ reg_name += 1;
+
+ remaining_names_len = names_len -
+ (reg_name - reg_names);
+ }
+
+ fdt_setprop(fdt, off, "reg-names", reg_names, names_len);
+ off = fdt_node_offset_by_compatible(fdt, off,
+ "fsl,lx2160a-pcie");
+ }
+
+ return 0;
+}
+#endif
+
#if defined(CONFIG_TARGET_LX2160AQDS)
void esdhc_dspi_status_fixup(void *blob)
{
@@ -275,7 +351,7 @@
puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
- puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100Hz\n");
+ puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
#endif
return 0;
}
@@ -402,6 +478,26 @@
return 0;
}
+#elif defined(CONFIG_TARGET_LX2160ARDB)
+int config_board_mux(void)
+{
+ u8 brdcfg;
+
+ brdcfg = QIXIS_READ(brdcfg[4]);
+ /* The BRDCFG4 register controls general board configuration.
+ *|-------------------------------------------|
+ *|Field | Function |
+ *|-------------------------------------------|
+ *|5 | CAN I/O Enable (net CFG_CAN_EN_B):|
+ *|CAN_EN | 0= CAN transceivers are disabled. |
+ *| | 1= CAN transceivers are enabled. |
+ *|-------------------------------------------|
+ */
+ brdcfg |= BIT_MASK(5);
+ QIXIS_WRITE(brdcfg[4], brdcfg);
+
+ return 0;
+}
#else
int config_board_mux(void)
{
@@ -529,11 +625,26 @@
int ft_board_setup(void *blob, bd_t *bd)
{
int i;
- u64 base[CONFIG_NR_DRAM_BANKS];
- u64 size[CONFIG_NR_DRAM_BANKS];
+ u16 mc_memory_bank = 0;
+
+ u64 *base;
+ u64 *size;
+ u64 mc_memory_base = 0;
+ u64 mc_memory_size = 0;
+ u16 total_memory_banks;
ft_cpu_setup(blob, bd);
+ fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
+
+ if (mc_memory_base != 0)
+ mc_memory_bank++;
+
+ total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
+
+ base = calloc(total_memory_banks, sizeof(u64));
+ size = calloc(total_memory_banks, sizeof(u64));
+
/* fixup DT for the three GPP DDR banks */
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
base[i] = gd->bd->bi_dram[i].start;
@@ -553,7 +664,17 @@
size[2] = gd->arch.resv_ram - base[2];
#endif
- fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
+ if (mc_memory_base != 0) {
+ for (i = 0; i <= total_memory_banks; i++) {
+ if (base[i] == 0 && size[i] == 0) {
+ base[i] = mc_memory_base;
+ size[i] = mc_memory_size;
+ break;
+ }
+ }
+ }
+
+ fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
#ifdef CONFIG_USB
fsl_fdt_fixup_dr_usb(blob, bd);
diff --git a/board/freescale/m54418twr/m54418twr.c b/board/freescale/m54418twr/m54418twr.c
index aa6f0e6..a4943e7 100644
--- a/board/freescale/m54418twr/m54418twr.c
+++ b/board/freescale/m54418twr/m54418twr.c
@@ -9,7 +9,7 @@
#include <asm/io.h>
#include <asm/immap.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c
index 2dc6d7f..e5aecc4 100644
--- a/board/freescale/mpc8323erdb/mpc8323erdb.c
+++ b/board/freescale/mpc8323erdb/mpc8323erdb.c
@@ -10,6 +10,7 @@
*/
#include <common.h>
+#include <env.h>
#include <ioports.h>
#include <mpc83xx.h>
#include <i2c.h>
diff --git a/board/freescale/mpc837xemds/pci.c b/board/freescale/mpc837xemds/pci.c
index 4217638..41b78cf 100644
--- a/board/freescale/mpc837xemds/pci.c
+++ b/board/freescale/mpc837xemds/pci.c
@@ -6,6 +6,7 @@
#include <asm/mmu.h>
#include <asm/io.h>
#include <common.h>
+#include <env.h>
#include <mpc83xx.h>
#include <pci.h>
#include <i2c.h>
diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c
index 18f396a..4ad62bc 100644
--- a/board/freescale/mpc837xerdb/mpc837xerdb.c
+++ b/board/freescale/mpc837xerdb/mpc837xerdb.c
@@ -6,6 +6,7 @@
*/
#include <common.h>
+#include <env.h>
#include <hwconfig.h>
#include <i2c.h>
#include <asm/io.h>
diff --git a/board/freescale/mpc8536ds/MAINTAINERS b/board/freescale/mpc8536ds/MAINTAINERS
index d640f89..5ce5164 100644
--- a/board/freescale/mpc8536ds/MAINTAINERS
+++ b/board/freescale/mpc8536ds/MAINTAINERS
@@ -1,5 +1,5 @@
MPC8536DS BOARD
-M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+M: Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
F: board/freescale/mpc8536ds/
F: include/configs/MPC8536DS.h
diff --git a/board/freescale/mpc8541cds/MAINTAINERS b/board/freescale/mpc8541cds/MAINTAINERS
index 1000776..cf3b9cf 100644
--- a/board/freescale/mpc8541cds/MAINTAINERS
+++ b/board/freescale/mpc8541cds/MAINTAINERS
@@ -1,5 +1,5 @@
MPC8541CDS BOARD
-M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+M: Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
F: board/freescale/mpc8541cds/
F: include/configs/MPC8541CDS.h
diff --git a/board/freescale/mpc8544ds/MAINTAINERS b/board/freescale/mpc8544ds/MAINTAINERS
index 78019fb..74e7249 100644
--- a/board/freescale/mpc8544ds/MAINTAINERS
+++ b/board/freescale/mpc8544ds/MAINTAINERS
@@ -1,5 +1,5 @@
MPC8544DS BOARD
-M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+M: Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
F: board/freescale/mpc8544ds/
F: include/configs/MPC8544DS.h
diff --git a/board/freescale/mpc8548cds/MAINTAINERS b/board/freescale/mpc8548cds/MAINTAINERS
index 385dc85..fbbedb1 100644
--- a/board/freescale/mpc8548cds/MAINTAINERS
+++ b/board/freescale/mpc8548cds/MAINTAINERS
@@ -1,5 +1,5 @@
MPC8548CDS BOARD
-M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+M: Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
F: board/freescale/mpc8548cds/
F: include/configs/MPC8548CDS.h
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index 7d819d8..2799b5b 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -164,7 +164,7 @@
#endif /* enable SDRAM init */
}
-#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
+#if (defined(CONFIG_PCI) || defined(CONFIG_PCI1)) && !defined(CONFIG_DM_PCI)
/* For some reason the Tundra PCI bridge shows up on itself as a
* different device. Work around that by refusing to configure it.
*/
@@ -189,6 +189,7 @@
static struct pci_controller pci1_hose;
#endif /* CONFIG_PCI */
+#if !defined(CONFIG_DM_PCI)
void pci_init_board(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@@ -268,6 +269,7 @@
fsl_pcie_init_board(first_free_busno);
}
+#endif
void configure_rgmii(void)
{
@@ -349,7 +351,7 @@
return pci_eth_init(bis);
}
-#if defined(CONFIG_OF_BOARD_SETUP)
+#if defined(CONFIG_OF_BOARD_SETUP) && !defined(CONFIG_DM_PCI)
void ft_pci_setup(void *blob, bd_t *bd)
{
FT_FSL_PCI_SETUP;
diff --git a/board/freescale/mpc8555cds/MAINTAINERS b/board/freescale/mpc8555cds/MAINTAINERS
index 815cffe..8f32feb 100644
--- a/board/freescale/mpc8555cds/MAINTAINERS
+++ b/board/freescale/mpc8555cds/MAINTAINERS
@@ -1,5 +1,5 @@
MPC8555CDS BOARD
-M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+M: Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
F: board/freescale/mpc8555cds/
F: include/configs/MPC8555CDS.h
diff --git a/board/freescale/mpc8568mds/MAINTAINERS b/board/freescale/mpc8568mds/MAINTAINERS
index 79f04d1..f474786 100644
--- a/board/freescale/mpc8568mds/MAINTAINERS
+++ b/board/freescale/mpc8568mds/MAINTAINERS
@@ -1,5 +1,5 @@
MPC8568MDS BOARD
-M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+M: Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
F: board/freescale/mpc8568mds/
F: include/configs/MPC8568MDS.h
diff --git a/board/freescale/mpc8569mds/MAINTAINERS b/board/freescale/mpc8569mds/MAINTAINERS
index b2e3bdf..9df3f3c 100644
--- a/board/freescale/mpc8569mds/MAINTAINERS
+++ b/board/freescale/mpc8569mds/MAINTAINERS
@@ -1,5 +1,5 @@
MPC8569MDS BOARD
-M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+M: Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
F: board/freescale/mpc8569mds/
F: include/configs/MPC8569MDS.h
diff --git a/board/freescale/mpc8572ds/MAINTAINERS b/board/freescale/mpc8572ds/MAINTAINERS
index 80a3096..d7e9b1f 100644
--- a/board/freescale/mpc8572ds/MAINTAINERS
+++ b/board/freescale/mpc8572ds/MAINTAINERS
@@ -1,5 +1,5 @@
MPC8572DS BOARD
-M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+M: Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
F: board/freescale/mpc8572ds/
F: include/configs/MPC8572DS.h
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
index 6abeeba..89f4d6c 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -5,6 +5,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
diff --git a/board/freescale/mpc8610hpcd/MAINTAINERS b/board/freescale/mpc8610hpcd/MAINTAINERS
index 633c5ed..9b1e0cd 100644
--- a/board/freescale/mpc8610hpcd/MAINTAINERS
+++ b/board/freescale/mpc8610hpcd/MAINTAINERS
@@ -1,5 +1,5 @@
MPC8610HPCD BOARD
-M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+M: Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
F: board/freescale/mpc8610hpcd/
F: include/configs/MPC8610HPCD.h
diff --git a/board/freescale/mpc8641hpcn/MAINTAINERS b/board/freescale/mpc8641hpcn/MAINTAINERS
index 827bb79..c957218 100644
--- a/board/freescale/mpc8641hpcn/MAINTAINERS
+++ b/board/freescale/mpc8641hpcn/MAINTAINERS
@@ -1,5 +1,5 @@
MPC8641HPCN BOARD
-M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+M: Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
F: board/freescale/mpc8641hpcn/
F: include/configs/MPC8641HPCN.h
diff --git a/board/freescale/mx25pdk/mx25pdk.c b/board/freescale/mx25pdk/mx25pdk.c
index 18922d8..c59f0fb 100644
--- a/board/freescale/mx25pdk/mx25pdk.c
+++ b/board/freescale/mx25pdk/mx25pdk.c
@@ -12,7 +12,7 @@
#include <asm/arch/iomux-mx25.h>
#include <asm/arch/clock.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <i2c.h>
#include <power/pmic.h>
#include <fsl_pmic.h>
@@ -24,7 +24,7 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg esdhc_cfg[1] = {
{IMX_MMC_SDHC1_BASE},
};
@@ -151,7 +151,7 @@
return 0;
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
int board_mmc_getcd(struct mmc *mmc)
{
/* Set up the Card Detect pin. */
diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c
index fa67230..aba17a6 100644
--- a/board/freescale/mx35pdk/mx35pdk.c
+++ b/board/freescale/mx35pdk/mx35pdk.c
@@ -16,7 +16,7 @@
#include <power/pmic.h>
#include <fsl_pmic.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <mc9sdz60.h>
#include <mc13892.h>
#include <linux/types.h>
@@ -261,7 +261,7 @@
return cpu_eth_init(bis);
}
-#if defined(CONFIG_FSL_ESDHC)
+#if defined(CONFIG_FSL_ESDHC_IMX)
struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};
diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c
index 68a9c77..d1bb852 100644
--- a/board/freescale/mx51evk/mx51evk.c
+++ b/board/freescale/mx51evk/mx51evk.c
@@ -16,7 +16,7 @@
#include <i2c.h>
#include <input.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <power/pmic.h>
#include <fsl_pmic.h>
#include <mc13892.h>
@@ -24,7 +24,7 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg esdhc_cfg[2] = {
{MMC_SDHC1_BASE_ADDR},
{MMC_SDHC2_BASE_ADDR},
@@ -262,7 +262,7 @@
gpio_set_value(IMX_GPIO_NR(2, 14), 1);
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
diff --git a/board/freescale/mx51evk/mx51evk_video.c b/board/freescale/mx51evk/mx51evk_video.c
index 995fb9a..3715c5d 100644
--- a/board/freescale/mx51evk/mx51evk_video.c
+++ b/board/freescale/mx51evk/mx51evk_video.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
+#include <env.h>
#include <linux/list.h>
#include <asm/gpio.h>
#include <asm/arch/iomux-mx51.h>
diff --git a/board/freescale/mx53ard/mx53ard.c b/board/freescale/mx53ard/mx53ard.c
index 9ed4668..e8fcccc 100644
--- a/board/freescale/mx53ard/mx53ard.c
+++ b/board/freescale/mx53ard/mx53ard.c
@@ -13,7 +13,7 @@
#include <linux/errno.h>
#include <netdev.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <asm/gpio.h>
#define ETHERNET_INT IMX_GPIO_NR(2, 31)
@@ -112,7 +112,7 @@
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg esdhc_cfg[2] = {
{MMC_SDHC1_BASE_ADDR},
{MMC_SDHC2_BASE_ADDR},
diff --git a/board/freescale/mx53evk/mx53evk.c b/board/freescale/mx53evk/mx53evk.c
index 5603658..56985c6 100644
--- a/board/freescale/mx53evk/mx53evk.c
+++ b/board/freescale/mx53evk/mx53evk.c
@@ -15,7 +15,7 @@
#include <netdev.h>
#include <i2c.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <power/pmic.h>
#include <fsl_pmic.h>
#include <asm/gpio.h>
@@ -137,7 +137,7 @@
imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg esdhc_cfg[2] = {
{MMC_SDHC1_BASE_ADDR},
{MMC_SDHC3_BASE_ADDR},
diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c
index b66cdcd..a177815 100644
--- a/board/freescale/mx53loco/mx53loco.c
+++ b/board/freescale/mx53loco/mx53loco.c
@@ -12,13 +12,14 @@
#include <asm/arch/clock.h>
#include <asm/arch/iomux-mx53.h>
#include <asm/arch/clock.h>
+#include <env.h>
#include <linux/errno.h>
#include <asm/mach-imx/mx5_video.h>
#include <netdev.h>
#include <i2c.h>
#include <input.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <asm/gpio.h>
#include <power/pmic.h>
#include <dialog_pmic.h>
@@ -92,7 +93,7 @@
imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg esdhc_cfg[2] = {
{MMC_SDHC1_BASE_ADDR},
{MMC_SDHC3_BASE_ADDR},
diff --git a/board/freescale/mx53loco/mx53loco_video.c b/board/freescale/mx53loco/mx53loco_video.c
index 160af1e..ff3fc8c 100644
--- a/board/freescale/mx53loco/mx53loco_video.c
+++ b/board/freescale/mx53loco/mx53loco_video.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
+#include <env.h>
#include <linux/list.h>
#include <asm/gpio.h>
#include <asm/arch/iomux-mx53.h>
diff --git a/board/freescale/mx53smd/mx53smd.c b/board/freescale/mx53smd/mx53smd.c
index 1a1a039..cab0e79 100644
--- a/board/freescale/mx53smd/mx53smd.c
+++ b/board/freescale/mx53smd/mx53smd.c
@@ -13,7 +13,7 @@
#include <linux/errno.h>
#include <netdev.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <asm/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -77,7 +77,7 @@
imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg esdhc_cfg[1] = {
{MMC_SDHC1_BASE_ADDR},
};
diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c
index f445f4b..3957c09 100644
--- a/board/freescale/mx6qarm2/mx6qarm2.c
+++ b/board/freescale/mx6qarm2/mx6qarm2.c
@@ -12,7 +12,7 @@
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <usb.h>
@@ -103,7 +103,7 @@
imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC3_BASE_ADDR},
{USDHC4_BASE_ADDR},
diff --git a/board/freescale/mx6sabreauto/mx6sabreauto.c b/board/freescale/mx6sabreauto/mx6sabreauto.c
index dd72de9..dc156ef 100644
--- a/board/freescale/mx6sabreauto/mx6sabreauto.c
+++ b/board/freescale/mx6sabreauto/mx6sabreauto.c
@@ -11,6 +11,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
+#include <env.h>
#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
@@ -18,7 +19,7 @@
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/spi.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/sys_proto.h>
@@ -282,7 +283,7 @@
SETUP_IOMUX_PADS(uart4_pads);
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
static struct fsl_esdhc_cfg usdhc_cfg[1] = {
{USDHC3_BASE_ADDR},
};
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index cdfc5ff..b0c0117 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -10,6 +10,7 @@
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/mach-imx/spi.h>
+#include <env.h>
#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
@@ -17,7 +18,7 @@
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/video.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/mxc_hdmi.h>
@@ -250,7 +251,7 @@
SETUP_IOMUX_PADS(uart1_pads);
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg usdhc_cfg[3] = {
{USDHC2_BASE_ADDR},
{USDHC3_BASE_ADDR},
diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
index e05aea6..4c48679 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -19,7 +19,7 @@
#include <asm/io.h>
#include <linux/sizes.h>
#include <common.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <i2c.h>
#include <mmc.h>
#include <netdev.h>
diff --git a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
index 6e606da..15e921a 100644
--- a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
+++ b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
@@ -17,7 +17,7 @@
#include <asm/io.h>
#include <linux/sizes.h>
#include <common.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <power/pmic.h>
diff --git a/board/freescale/mx6sxsabresd/imximage.cfg b/board/freescale/mx6sxsabresd/imximage.cfg
index 3e94f6a..0354bb3 100644
--- a/board/freescale/mx6sxsabresd/imximage.cfg
+++ b/board/freescale/mx6sxsabresd/imximage.cfg
@@ -18,6 +18,13 @@
BOOT_FROM sd
/*
+ * Secure boot support
+ */
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index 3e10c7f..1c10958 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -15,9 +15,10 @@
#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
#include <asm/mach-imx/mxc_i2c.h>
+#include <env.h>
#include <linux/sizes.h>
#include <common.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <mmc.h>
#include <i2c.h>
#include <miiphy.h>
diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
index 636c008..ccbe404 100644
--- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
+++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
@@ -16,7 +16,8 @@
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/io.h>
#include <common.h>
-#include <fsl_esdhc.h>
+#include <env.h>
+#include <fsl_esdhc_imx.h>
#include <i2c.h>
#include <miiphy.h>
#include <linux/sizes.h>
@@ -189,7 +190,7 @@
}
#endif
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
static struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC1_BASE_ADDR, 0, 4},
#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
diff --git a/board/freescale/mx6ullevk/mx6ullevk.c b/board/freescale/mx6ullevk/mx6ullevk.c
index ad83f36..e119347 100644
--- a/board/freescale/mx6ullevk/mx6ullevk.c
+++ b/board/freescale/mx6ullevk/mx6ullevk.c
@@ -14,7 +14,8 @@
#include <asm/mach-imx/boot_mode.h>
#include <asm/io.h>
#include <common.h>
-#include <fsl_esdhc.h>
+#include <env.h>
+#include <fsl_esdhc_imx.h>
#include <linux/sizes.h>
#include <mmc.h>
diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c
index 191b59a..86bf030 100644
--- a/board/freescale/mx7dsabresd/mx7dsabresd.c
+++ b/board/freescale/mx7dsabresd/mx7dsabresd.c
@@ -12,7 +12,7 @@
#include <asm/io.h>
#include <linux/sizes.h>
#include <common.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <mmc.h>
#include <miiphy.h>
#include <netdev.h>
diff --git a/board/freescale/mx7ulp_evk/imximage.cfg b/board/freescale/mx7ulp_evk/imximage.cfg
index a6e18d9..43ebc23 100644
--- a/board/freescale/mx7ulp_evk/imximage.cfg
+++ b/board/freescale/mx7ulp_evk/imximage.cfg
@@ -45,12 +45,12 @@
DATA 4 0x403e0040 0x01000020
DATA 4 0x403e0500 0x01000000
DATA 4 0x403e050c 0x80808080
-DATA 4 0x403e0508 0x00140000
-DATA 4 0x403E0510 0x00000004
-DATA 4 0x403E0514 0x00000002
+DATA 4 0x403e0508 0x00160002
+DATA 4 0x403E0510 0x00000001
+DATA 4 0x403E0514 0x00000014
DATA 4 0x403e0500 0x00000001
CHECK_BITS_SET 4 0x403e0500 0x01000000
-DATA 4 0x403e050c 0x8080801E
+DATA 4 0x403e050c 0x8080801B
CHECK_BITS_SET 4 0x403e050c 0x00000040
DATA 4 0x403E0030 0x00000001
DATA 4 0x403e0040 0x11000020
@@ -94,11 +94,6 @@
DATA 4 0x40AB0824 0x33333333
DATA 4 0x40AB0828 0x33333333
-DATA 4 0x40AB082C 0xf3333333
-DATA 4 0x40AB0830 0xf3333333
-DATA 4 0x40AB0834 0xf3333333
-DATA 4 0x40AB0838 0xf3333333
-
DATA 4 0x40AB08C0 0x24922492
DATA 4 0x40AB08B8 0x00000800
@@ -113,8 +108,8 @@
DATA 4 0x40AB0040 0x0000003F
DATA 4 0x40AB0000 0xC3190000
-DATA 4 0x40AB001C 0x00008050
-DATA 4 0x40AB001C 0x00008058
+DATA 4 0x40AB001C 0x00008010
+DATA 4 0x40AB001C 0x00008018
DATA 4 0x40AB001C 0x003F8030
DATA 4 0x40AB001C 0x003F8038
DATA 4 0x40AB001C 0xFF0A8030
diff --git a/board/freescale/mx7ulp_evk/plugin.S b/board/freescale/mx7ulp_evk/plugin.S
index 082b2be..2cc93db 100644
--- a/board/freescale/mx7ulp_evk/plugin.S
+++ b/board/freescale/mx7ulp_evk/plugin.S
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2019 NXP
*/
#include <config.h>
@@ -15,13 +16,14 @@
str r3, [r2, #0x40]
ldr r3, =0x01000000
str r3, [r2, #0x500]
+
ldr r3, =0x80808080
str r3, [r2, #0x50c]
- ldr r3, =0x00140000
+ ldr r3, =0x00160002
str r3, [r2, #0x508]
- ldr r3, =0x00000004
+ ldr r3, =0x00000001
str r3, [r2, #0x510]
- ldr r3, =0x00000002
+ ldr r3, =0x00000014
str r3, [r2, #0x514]
ldr r3, =0x00000001
str r3, [r2, #0x500]
@@ -33,7 +35,7 @@
cmp r4, r3
bne wait1
- ldr r3, =0x8080801E
+ ldr r3, =0x8080801B
str r3, [r2, #0x50c]
ldr r3, =0x00000040
@@ -132,15 +134,6 @@
ldr r1, =0x33333333
str r1, [r0, #0x828]
- ldr r1, =0xf3333333
- str r1, [r0, #0x82c]
- ldr r1, =0xf3333333
- str r1, [r0, #0x830]
- ldr r1, =0xf3333333
- str r1, [r0, #0x834]
- ldr r1, =0xf3333333
- str r1, [r0, #0x838]
-
ldr r1, =0x24922492
str r1, [r0, #0x8c0]
ldr r1, =0x00000800
@@ -168,9 +161,9 @@
ldr r1, =0xC3190000
str r1, [r0, #0x0]
- ldr r1, =0x00008050
+ ldr r1, =0x00008010
str r1, [r0, #0x1c]
- ldr r1, =0x00008058
+ ldr r1, =0x00008018
str r1, [r0, #0x1c]
ldr r1, =0x003F8030
str r1, [r0, #0x1c]
diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c
index b0db353..449df93 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -9,6 +9,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/io.h>
+#include <env.h>
#include <miiphy.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c
index e07640a..8f050b3 100644
--- a/board/freescale/p1010rdb/spl.c
+++ b/board/freescale/p1010rdb/spl.c
@@ -4,7 +4,8 @@
#include <common.h>
#include <console.h>
-#include <environment.h>
+#include <env.h>
+#include <env_internal.h>
#include <ns16550.h>
#include <malloc.h>
#include <mmc.h>
diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c
index 835ede5..9406e75 100644
--- a/board/freescale/p1022ds/p1022ds.c
+++ b/board/freescale/p1022ds/p1022ds.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
diff --git a/board/freescale/p1022ds/spl.c b/board/freescale/p1022ds/spl.c
index cfdd9fc..06273f1 100644
--- a/board/freescale/p1022ds/spl.c
+++ b/board/freescale/p1022ds/spl.c
@@ -5,7 +5,8 @@
#include <common.h>
#include <console.h>
-#include <environment.h>
+#include <env.h>
+#include <env_internal.h>
#include <ns16550.h>
#include <malloc.h>
#include <mmc.h>
diff --git a/board/freescale/p1023rdb/p1023rdb.c b/board/freescale/p1023rdb/p1023rdb.c
index d0012ea..7db0404 100644
--- a/board/freescale/p1023rdb/p1023rdb.c
+++ b/board/freescale/p1023rdb/p1023rdb.c
@@ -8,6 +8,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <pci.h>
#include <asm/io.h>
#include <asm/cache.h>
diff --git a/board/freescale/p1_p2_rdb_pc/README b/board/freescale/p1_p2_rdb_pc/README
index f4cc43f..b85cf02 100644
--- a/board/freescale/p1_p2_rdb_pc/README
+++ b/board/freescale/p1_p2_rdb_pc/README
@@ -45,3 +45,22 @@
'setenv hwconfig qe' to enable QE UEC/UART and disable Nor-Flash/CPLD.
'setenv hwconfig 'qe;tdm'' to enalbe QE TDM and disable Nor-Flash/CPLD.
+
+Device tree support and how to enable it for different configs
+--------------------------------------------------------------
+Device tree support is available for p1020rdb and p2020rdb for below mentioned boot,
+1. NOR Boot
+2. NAND Boot
+3. SD Boot
+4. SPIFLASH Boot
+
+To enable device tree support for other boot, below configs need to be
+enabled in relative defconfig file,
+1. CONFIG_DEFAULT_DEVICE_TREE="p1020rdb" (Change default device tree name if required)
+2. CONFIG_OF_CONTROL
+3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
+ CONFIG_RESET_VECTOR_ADDRESS - 0xffc
+
+If device tree support is enabled in defconfig,
+1. use 'u-boot-with-dtb.bin' for NOR boot.
+2. use 'u-boot-with-spl.bin' for other boot.
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 4b151e8..3649f16 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -5,6 +5,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <hwconfig.h>
#include <pci.h>
#include <i2c.h>
@@ -277,7 +278,7 @@
return 0;
}
-#ifdef CONFIG_PCI
+#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
void pci_init_board(void)
{
fsl_pcie_init_board(0);
@@ -443,7 +444,9 @@
fdt_fixup_memory(blob, (u64)base, (u64)size);
+#if !defined(CONFIG_DM_PCI)
FT_FSL_PCI_SETUP;
+#endif
#ifdef CONFIG_QE
do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c
index 48ab271..dbf9f73 100644
--- a/board/freescale/p1_p2_rdb_pc/spl.c
+++ b/board/freescale/p1_p2_rdb_pc/spl.c
@@ -5,7 +5,8 @@
#include <common.h>
#include <console.h>
-#include <environment.h>
+#include <env.h>
+#include <env_internal.h>
#include <ns16550.h>
#include <malloc.h>
#include <mmc.h>
diff --git a/board/freescale/p1_twr/p1_twr.c b/board/freescale/p1_twr/p1_twr.c
index fe99ebf..01cac18 100644
--- a/board/freescale/p1_twr/p1_twr.c
+++ b/board/freescale/p1_twr/p1_twr.c
@@ -5,6 +5,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <hwconfig.h>
#include <pci.h>
#include <i2c.h>
diff --git a/board/freescale/p2041rdb/README b/board/freescale/p2041rdb/README
index 9b5539f..79f77e4 100644
--- a/board/freescale/p2041rdb/README
+++ b/board/freescale/p2041rdb/README
@@ -85,6 +85,24 @@
SW1[1-5] = 10100
Note: 1 stands for 'on', 0 stands for 'off'
+Device tree support and how to enable it for different configs
+--------------------------------------------------------------
+Device tree support is available for p2041rdb for below mentioned boot,
+1. NOR Boot
+2. NAND Boot
+3. SD Boot
+4. SPIFLASH Boot
+
+To enable device tree support for other boot, below configs need to be
+enabled in relative defconfig file,
+1. CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" (Change default device tree name if required)
+2. CONFIG_OF_CONTROL
+3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
+ CONFIG_RESET_VECTOR_ADDRESS - 0xffc
+
+If device tree support is enabled in defconfig, use 'u-boot-with-dtb.bin'
+instead of u-boot.bin for all boot.
+
CPLD command
============
The CPLD is used to control the power sequence and some serdes lane
diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c
index 6324027..baf1506 100644
--- a/board/freescale/p2041rdb/p2041rdb.c
+++ b/board/freescale/p2041rdb/p2041rdb.c
@@ -5,6 +5,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <netdev.h>
#include <linux/compiler.h>
#include <asm/mmu.h>
diff --git a/board/freescale/qemu-ppce500/qemu-ppce500.c b/board/freescale/qemu-ppce500/qemu-ppce500.c
index 42a6b54..fb36d83 100644
--- a/board/freescale/qemu-ppce500/qemu-ppce500.c
+++ b/board/freescale/qemu-ppce500/qemu-ppce500.c
@@ -5,6 +5,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
diff --git a/board/freescale/s32v234evb/s32v234evb.c b/board/freescale/s32v234evb/s32v234evb.c
index 464be2b..9bc9ddf 100644
--- a/board/freescale/s32v234evb/s32v234evb.c
+++ b/board/freescale/s32v234evb/s32v234evb.c
@@ -10,7 +10,7 @@
#include <asm/arch/lpddr2.h>
#include <asm/arch/clock.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <i2c.h>
@@ -74,7 +74,7 @@
}
#endif
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg esdhc_cfg[1] = {
{USDHC_BASE_ADDR},
};
diff --git a/board/freescale/t102xqds/spl.c b/board/freescale/t102xqds/spl.c
index 1b58174..3008f09 100644
--- a/board/freescale/t102xqds/spl.c
+++ b/board/freescale/t102xqds/spl.c
@@ -4,7 +4,7 @@
#include <common.h>
#include <console.h>
-#include <environment.h>
+#include <env_internal.h>
#include <malloc.h>
#include <ns16550.h>
#include <nand.h>
diff --git a/board/freescale/t102xqds/t102xqds.c b/board/freescale/t102xqds/t102xqds.c
index d770aeb..6c75450 100644
--- a/board/freescale/t102xqds/t102xqds.c
+++ b/board/freescale/t102xqds/t102xqds.c
@@ -5,6 +5,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <i2c.h>
#include <netdev.h>
#include <linux/compiler.h>
diff --git a/board/freescale/t102xrdb/README b/board/freescale/t102xrdb/README
index a0af25a..dde3f8c 100644
--- a/board/freescale/t102xrdb/README
+++ b/board/freescale/t102xrdb/README
@@ -251,6 +251,25 @@
SW3[3] = '0' for eMMC (or 'switch emmc' by software)
+device tree support and how to enable it for different configs
+--------------------------------------------------------------
+device tree support is available for t1024rdb for below mentioned boot,
+1. nor boot
+2. nand boot
+3. sd boot
+4. spiflash boot
+
+to enable device tree support for other boot, below configs need to be
+enabled in relative defconfig file,
+1. config_default_device_tree="t1024rdb" (change default device tree name if required)
+2. config_of_control
+3. config_mpc85xx_have_reset_vector if reset vector is located at
+ config_reset_vector_address - 0xffc
+
+if device tree support is enabled in defconfig,
+1. use 'u-boot-with-dtb.bin' for nor boot.
+2. use 'u-boot-with-spl-pbl.bin' for other boot.
+
2-stage NAND/SPI/SD boot loader
-------------------------------
PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
diff --git a/board/freescale/t102xrdb/pci.c b/board/freescale/t102xrdb/pci.c
index 161b8cb..adc128d 100644
--- a/board/freescale/t102xrdb/pci.c
+++ b/board/freescale/t102xrdb/pci.c
@@ -11,6 +11,7 @@
#include <fdt_support.h>
#include <asm/fsl_serdes.h>
+#if !defined(CONFIG_DM_PCI)
void pci_init_board(void)
{
fsl_pcie_init_board(0);
@@ -20,3 +21,4 @@
{
FT_FSL_PCI_SETUP;
}
+#endif
diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c
index a226d4b..029e3d2 100644
--- a/board/freescale/t102xrdb/spl.c
+++ b/board/freescale/t102xrdb/spl.c
@@ -4,7 +4,7 @@
#include <common.h>
#include <console.h>
-#include <environment.h>
+#include <env_internal.h>
#include <malloc.h>
#include <ns16550.h>
#include <nand.h>
diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c
index acc0be0..793f54d 100644
--- a/board/freescale/t102xrdb/t102xrdb.c
+++ b/board/freescale/t102xrdb/t102xrdb.c
@@ -5,6 +5,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <i2c.h>
#include <netdev.h>
#include <linux/compiler.h>
diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c
index 911190b..55516b9 100644
--- a/board/freescale/t1040qds/t1040qds.c
+++ b/board/freescale/t1040qds/t1040qds.c
@@ -5,6 +5,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <i2c.h>
#include <netdev.h>
#include <linux/compiler.h>
diff --git a/board/freescale/t104xrdb/README b/board/freescale/t104xrdb/README
index 98b3f63..09cb98e 100644
--- a/board/freescale/t104xrdb/README
+++ b/board/freescale/t104xrdb/README
@@ -365,3 +365,22 @@
2. SPI does not support flush so remove flush from pbl, make changes in
tools/pblimage.c file, Update value of pbl_end_cmd[0] = 0x09138000
with 0x091380c0
+
+Device tree support and how to enable it for different configs
+--------------------------------------------------------------
+Device tree support is available for t1042d4rdb for below mentioned boot,
+1. NOR Boot
+2. NAND Boot
+3. SD Boot
+4. SPIFLASH Boot
+
+To enable device tree support for other boot, below configs need to be
+enabled in relative defconfig file,
+1. CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb" (Change default device tree name if required)
+2. CONFIG_OF_CONTROL
+3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
+ CONFIG_RESET_VECTOR_ADDRESS - 0xffc
+
+If device tree support is enabled in defconfig,
+1. use 'u-boot-with-dtb.bin' for NOR boot.
+2. use 'u-boot-with-spl-pbl.bin' for other boot.
diff --git a/board/freescale/t104xrdb/pci.c b/board/freescale/t104xrdb/pci.c
index 9fd6659..6b666ba 100644
--- a/board/freescale/t104xrdb/pci.c
+++ b/board/freescale/t104xrdb/pci.c
@@ -11,6 +11,7 @@
#include <fdt_support.h>
#include <asm/fsl_serdes.h>
+#if !defined(CONFIG_DM_PCI)
void pci_init_board(void)
{
fsl_pcie_init_board(0);
@@ -20,3 +21,4 @@
{
FT_FSL_PCI_SETUP;
}
+#endif
diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c
index 58a7376..7b0eb8e 100644
--- a/board/freescale/t104xrdb/spl.c
+++ b/board/freescale/t104xrdb/spl.c
@@ -4,7 +4,7 @@
#include <common.h>
#include <console.h>
-#include <environment.h>
+#include <env_internal.h>
#include <malloc.h>
#include <ns16550.h>
#include <nand.h>
diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c
index c9557b4..c7a6451 100644
--- a/board/freescale/t104xrdb/t104xrdb.c
+++ b/board/freescale/t104xrdb/t104xrdb.c
@@ -5,6 +5,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <hwconfig.h>
#include <netdev.h>
#include <linux/compiler.h>
diff --git a/board/freescale/t208xqds/spl.c b/board/freescale/t208xqds/spl.c
index 27f3c4c..9695dfc 100644
--- a/board/freescale/t208xqds/spl.c
+++ b/board/freescale/t208xqds/spl.c
@@ -4,7 +4,7 @@
#include <common.h>
#include <console.h>
-#include <environment.h>
+#include <env_internal.h>
#include <malloc.h>
#include <ns16550.h>
#include <nand.h>
diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c
index abd069f..86d6b1d 100644
--- a/board/freescale/t208xqds/t208xqds.c
+++ b/board/freescale/t208xqds/t208xqds.c
@@ -5,6 +5,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <i2c.h>
#include <netdev.h>
#include <linux/compiler.h>
diff --git a/board/freescale/t208xrdb/README b/board/freescale/t208xrdb/README
index 42b2b92..9e4b28f 100644
--- a/board/freescale/t208xrdb/README
+++ b/board/freescale/t208xrdb/README
@@ -262,3 +262,22 @@
For more details, please refer to T2080PCIe-RDB User Guide and access
website www.freescale.com and Freescale QorIQ SDK Infocenter document.
+
+Device tree support and how to enable it for different configs
+--------------------------------------------------------------
+Device tree support is available for t2080rdb for below mentioned boot,
+1. NOR Boot
+2. NAND Boot
+3. SD Boot
+4. SPIFLASH Boot
+
+To enable device tree support for other boot, below configs need to be
+enabled in relative defconfig file,
+1. CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" (Change default device tree name if required)
+2. CONFIG_OF_CONTROL
+3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
+ CONFIG_RESET_VECTOR_ADDRESS - 0xffc
+
+If device tree support is enabled in defconfig,
+1. use 'u-boot-with-dtb.bin' for NOR boot.
+2. use 'u-boot-with-spl-pbl.bin' for other boot.
diff --git a/board/freescale/t208xrdb/pci.c b/board/freescale/t208xrdb/pci.c
index 161b8cb..adc128d 100644
--- a/board/freescale/t208xrdb/pci.c
+++ b/board/freescale/t208xrdb/pci.c
@@ -11,6 +11,7 @@
#include <fdt_support.h>
#include <asm/fsl_serdes.h>
+#if !defined(CONFIG_DM_PCI)
void pci_init_board(void)
{
fsl_pcie_init_board(0);
@@ -20,3 +21,4 @@
{
FT_FSL_PCI_SETUP;
}
+#endif
diff --git a/board/freescale/t208xrdb/spl.c b/board/freescale/t208xrdb/spl.c
index ecb1e0d..ca7d6a2 100644
--- a/board/freescale/t208xrdb/spl.c
+++ b/board/freescale/t208xrdb/spl.c
@@ -4,7 +4,7 @@
#include <common.h>
#include <console.h>
-#include <environment.h>
+#include <env_internal.h>
#include <malloc.h>
#include <ns16550.h>
#include <nand.h>
diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c
index adae3f9..d03d48b 100644
--- a/board/freescale/t208xrdb/t208xrdb.c
+++ b/board/freescale/t208xrdb/t208xrdb.c
@@ -5,6 +5,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <i2c.h>
#include <netdev.h>
#include <linux/compiler.h>
diff --git a/board/freescale/t4qds/spl.c b/board/freescale/t4qds/spl.c
index 16cc29e..7666fe7 100644
--- a/board/freescale/t4qds/spl.c
+++ b/board/freescale/t4qds/spl.c
@@ -4,7 +4,7 @@
#include <common.h>
#include <console.h>
-#include <environment.h>
+#include <env_internal.h>
#include <asm/spl.h>
#include <malloc.h>
#include <ns16550.h>
diff --git a/board/freescale/t4qds/t4240emu.c b/board/freescale/t4qds/t4240emu.c
index 512229a..d9cb967 100644
--- a/board/freescale/t4qds/t4240emu.c
+++ b/board/freescale/t4qds/t4240emu.c
@@ -5,6 +5,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <i2c.h>
#include <netdev.h>
#include <linux/compiler.h>
diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c
index 125bfa3..bb18b97 100644
--- a/board/freescale/t4qds/t4240qds.c
+++ b/board/freescale/t4qds/t4240qds.c
@@ -5,6 +5,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <i2c.h>
#include <netdev.h>
#include <linux/compiler.h>
diff --git a/board/freescale/t4rdb/pci.c b/board/freescale/t4rdb/pci.c
index 4100370..7d670e1 100644
--- a/board/freescale/t4rdb/pci.c
+++ b/board/freescale/t4rdb/pci.c
@@ -11,6 +11,7 @@
#include <fdt_support.h>
#include <asm/fsl_serdes.h>
+#if !defined(CONFIG_DM_PCI)
void pci_init_board(void)
{
fsl_pcie_init_board(0);
@@ -20,3 +21,4 @@
{
FT_FSL_PCI_SETUP;
}
+#endif
diff --git a/board/freescale/t4rdb/spl.c b/board/freescale/t4rdb/spl.c
index cc2b2f9..a19558b 100644
--- a/board/freescale/t4rdb/spl.c
+++ b/board/freescale/t4rdb/spl.c
@@ -7,7 +7,7 @@
#include <common.h>
#include <console.h>
-#include <environment.h>
+#include <env_internal.h>
#include <asm/spl.h>
#include <malloc.h>
#include <ns16550.h>
diff --git a/board/freescale/t4rdb/t4240rdb.c b/board/freescale/t4rdb/t4240rdb.c
index 3bfebb6..0c95607 100644
--- a/board/freescale/t4rdb/t4240rdb.c
+++ b/board/freescale/t4rdb/t4240rdb.c
@@ -5,6 +5,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <i2c.h>
#include <netdev.h>
#include <linux/compiler.h>
diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c
index 63be3bd..f6cd7a4 100644
--- a/board/freescale/vf610twr/vf610twr.c
+++ b/board/freescale/vf610twr/vf610twr.c
@@ -11,7 +11,7 @@
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <i2c.h>
@@ -234,7 +234,7 @@
imx_iomux_v3_setup_multiple_pads(qspi0_pads, ARRAY_SIZE(qspi0_pads));
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg esdhc_cfg[1] = {
{ESDHC1_BASE_ADDR},
};
diff --git a/board/gardena/smart-gateway-at91sam/board.c b/board/gardena/smart-gateway-at91sam/board.c
index 6a1389e..3e2da0d 100644
--- a/board/gardena/smart-gateway-at91sam/board.c
+++ b/board/gardena/smart-gateway-at91sam/board.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <debug_uart.h>
+#include <env.h>
#include <led.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/clk.h>
diff --git a/board/gardena/smart-gateway-mt7688/board.c b/board/gardena/smart-gateway-mt7688/board.c
index 6e11077..bd494c8 100644
--- a/board/gardena/smart-gateway-mt7688/board.c
+++ b/board/gardena/smart-gateway-mt7688/board.c
@@ -4,7 +4,8 @@
*/
#include <common.h>
-#include <environment.h>
+#include <env.h>
+#include <env_internal.h>
#include <led.h>
#include <net.h>
#include <spi.h>
diff --git a/board/gateworks/gw_ventana/common.c b/board/gateworks/gw_ventana/common.c
index 8786a12..1240a9d 100644
--- a/board/gateworks/gw_ventana/common.c
+++ b/board/gateworks/gw_ventana/common.c
@@ -10,7 +10,8 @@
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
-#include <fsl_esdhc.h>
+#include <env.h>
+#include <fsl_esdhc_imx.h>
#include <hwconfig.h>
#include <power/pmic.h>
#include <power/ltc3676_pmic.h>
@@ -1656,7 +1657,7 @@
}
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
static struct fsl_esdhc_cfg usdhc_cfg[2];
int board_mmc_init(bd_t *bis)
@@ -1753,4 +1754,4 @@
return -1;
}
-#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_FSL_ESDHC_IMX */
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c
index c63fb41..8a694a7 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -21,11 +21,11 @@
#include <asm/setup.h>
#include <dm.h>
#include <dm/platform_data/serial_mxc.h>
-#include <environment.h>
+#include <env.h>
#include <hwconfig.h>
#include <i2c.h>
#include <fdt_support.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <jffs2/load_kernel.h>
#include <linux/ctype.h>
#include <miiphy.h>
diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c
index eaf7aa9..b089137 100644
--- a/board/gateworks/gw_ventana/gw_ventana_spl.c
+++ b/board/gateworks/gw_ventana/gw_ventana_spl.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
+#include <env.h>
#include <asm/io.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/mx6-ddr.h>
@@ -13,7 +14,7 @@
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
-#include <environment.h>
+#include <env.h>
#include <i2c.h>
#include <spl.h>
diff --git a/board/gdsys/a38x/keyprogram.c b/board/gdsys/a38x/keyprogram.c
index 291edc3..0008979 100644
--- a/board/gdsys/a38x/keyprogram.c
+++ b/board/gdsys/a38x/keyprogram.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
+#include <env.h>
#include <tpm-v1.h>
#include <malloc.h>
#include <linux/ctype.h>
diff --git a/board/gdsys/mpc8308/gazerbeam.c b/board/gdsys/mpc8308/gazerbeam.c
index cd62174..ddd6ee8 100644
--- a/board/gdsys/mpc8308/gazerbeam.c
+++ b/board/gdsys/mpc8308/gazerbeam.c
@@ -8,6 +8,7 @@
#include <common.h>
#include <board.h>
#include <dm.h>
+#include <env.h>
#include <fdt_support.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
diff --git a/board/gdsys/mpc8308/hrcon.c b/board/gdsys/mpc8308/hrcon.c
index d14a28e..60faa46 100644
--- a/board/gdsys/mpc8308/hrcon.c
+++ b/board/gdsys/mpc8308/hrcon.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
+#include <env.h>
#include <hwconfig.h>
#include <i2c.h>
#include <spi.h>
diff --git a/board/gdsys/mpc8308/strider.c b/board/gdsys/mpc8308/strider.c
index 1fdea67..886bc2b 100644
--- a/board/gdsys/mpc8308/strider.c
+++ b/board/gdsys/mpc8308/strider.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
+#include <env.h>
#include <hwconfig.h>
#include <i2c.h>
#include <spi.h>
diff --git a/board/gdsys/p1022/controlcenterd-id.c b/board/gdsys/p1022/controlcenterd-id.c
index 6ac956c..43f5404 100644
--- a/board/gdsys/p1022/controlcenterd-id.c
+++ b/board/gdsys/p1022/controlcenterd-id.c
@@ -12,6 +12,7 @@
#include <common.h>
#include <dm.h>
+#include <env.h>
#include <malloc.h>
#include <fs.h>
#include <i2c.h>
diff --git a/board/gdsys/p1022/controlcenterd.c b/board/gdsys/p1022/controlcenterd.c
index 7bdc924..6eb3d6c 100644
--- a/board/gdsys/p1022/controlcenterd.c
+++ b/board/gdsys/p1022/controlcenterd.c
@@ -23,6 +23,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
index f42d2ce..917ecc4 100644
--- a/board/ge/bx50v3/bx50v3.c
+++ b/board/ge/bx50v3/bx50v3.c
@@ -9,6 +9,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
+#include <env.h>
#include <linux/errno.h>
#include <linux/libfdt.h>
#include <asm/gpio.h>
@@ -17,7 +18,7 @@
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/video.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <net.h>
#include <netdev.h>
diff --git a/board/ge/common/ge_common.c b/board/ge/common/ge_common.c
index 4e6ef9c..501c8b2 100644
--- a/board/ge/common/ge_common.c
+++ b/board/ge/common/ge_common.c
@@ -4,6 +4,7 @@
*/
#include <common.h>
+#include <env.h>
#include <i2c.h>
#include <rtc.h>
diff --git a/board/ge/mx53ppd/mx53ppd.c b/board/ge/mx53ppd/mx53ppd.c
index 5411e42..5448567 100644
--- a/board/ge/mx53ppd/mx53ppd.c
+++ b/board/ge/mx53ppd/mx53ppd.c
@@ -16,15 +16,15 @@
#include <asm/arch/clock.h>
#include <asm/arch/iomux-mx53.h>
#include <asm/arch/clock.h>
+#include <env.h>
#include <linux/errno.h>
#include <linux/libfdt.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/mx5_video.h>
-#include <environment.h>
#include <netdev.h>
#include <i2c.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <asm/gpio.h>
#include <power/pmic.h>
#include <dialog_pmic.h>
diff --git a/board/geekbuying/geekbox/geekbox.c b/board/geekbuying/geekbox/geekbox.c
index 10b04a1..b0f9a5f 100644
--- a/board/geekbuying/geekbox/geekbox.c
+++ b/board/geekbuying/geekbox/geekbox.c
@@ -4,8 +4,3 @@
*/
#include <common.h>
-
-int board_init(void)
-{
- return 0;
-}
diff --git a/board/google/gru/gru.c b/board/google/gru/gru.c
index b116b1a..b6b4f19 100644
--- a/board/google/gru/gru.c
+++ b/board/google/gru/gru.c
@@ -5,12 +5,28 @@
#include <common.h>
-int board_init(void)
-{
- return 0;
-}
-
+#ifdef CONFIG_SPL_BUILD
/* provided to defeat compiler optimisation in board_init_f() */
void gru_dummy_function(int i)
{
}
+
+int board_early_init_f(void)
+{
+# ifdef CONFIG_TARGET_CHROMEBOOK_BOB
+ int sum, i;
+
+ /*
+ * Add a delay and ensure that the compiler does not optimise this out.
+ * This is needed since the power rails tail a while to turn on, and
+ * we get garbage serial output otherwise.
+ */
+ sum = 0;
+ for (i = 0; i < 150000; i++)
+ sum += i;
+ gru_dummy_function(sum);
+#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
+
+ return 0;
+}
+#endif
diff --git a/board/google/veyron/veyron.c b/board/google/veyron/veyron.c
index 19edb18..dd2c014 100644
--- a/board/google/veyron/veyron.c
+++ b/board/google/veyron/veyron.c
@@ -3,10 +3,93 @@
* (C) Copyright 2015 Google, Inc
*/
+#include <clk.h>
#include <common.h>
+#include <dm.h>
+#include <asm/arch-rockchip/clock.h>
+#include <dt-bindings/clock/rk3288-cru.h>
+#include <power/regulator.h>
/*
* We should increase the DDR voltage to 1.2V using the PWM regulator.
* There is a U-Boot driver for this but it may need to add support for the
* 'voltage-table' property.
*/
+#ifndef CONFIG_SPL_BUILD
+#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
+static int veyron_init(void)
+{
+ struct udevice *dev;
+ struct clk clk;
+ int ret;
+
+ ret = regulator_get_by_platname("vdd_arm", &dev);
+ if (ret) {
+ debug("Cannot set regulator name\n");
+ return ret;
+ }
+
+ /* Slowly raise to max CPU voltage to prevent overshoot */
+ ret = regulator_set_value(dev, 1200000);
+ if (ret)
+ return ret;
+ udelay(175); /* Must wait for voltage to stabilize, 2mV/us */
+ ret = regulator_set_value(dev, 1400000);
+ if (ret)
+ return ret;
+ udelay(100); /* Must wait for voltage to stabilize, 2mV/us */
+
+ ret = rockchip_get_clk(&clk.dev);
+ if (ret)
+ return ret;
+ clk.id = PLL_APLL;
+ ret = clk_set_rate(&clk, 1800000000);
+ if (IS_ERR_VALUE(ret))
+ return ret;
+
+ ret = regulator_get_by_platname("vcc33_sd", &dev);
+ if (ret) {
+ debug("Cannot get regulator name\n");
+ return ret;
+ }
+
+ ret = regulator_set_value(dev, 3300000);
+ if (ret)
+ return ret;
+
+ ret = regulators_enable_boot_on(false);
+ if (ret) {
+ debug("%s: Cannot enable boot on regulators\n", __func__);
+ return ret;
+ }
+
+ return 0;
+}
+#endif
+
+int board_early_init_f(void)
+{
+ struct udevice *dev;
+ int ret;
+
+#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
+ if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) {
+ ret = veyron_init();
+ if (ret)
+ return ret;
+ }
+#endif
+ /*
+ * This init is done in SPL, but when chain-loading U-Boot SPL will
+ * have been skipped. Allow the clock driver to check if it needs
+ * setting up.
+ */
+ ret = rockchip_get_clk(&dev);
+ if (ret) {
+ debug("CLK init failed: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+#endif
diff --git a/board/grinn/chiliboard/board.c b/board/grinn/chiliboard/board.c
index dc0de62..c6d5360 100644
--- a/board/grinn/chiliboard/board.c
+++ b/board/grinn/chiliboard/board.c
@@ -16,7 +16,7 @@
#include <asm/emif.h>
#include <asm/io.h>
#include <cpsw.h>
-#include <environment.h>
+#include <env.h>
#include <errno.h>
#include <miiphy.h>
#include <spl.h>
diff --git a/board/grinn/liteboard/board.c b/board/grinn/liteboard/board.c
index 80910e4..1558ea4 100644
--- a/board/grinn/liteboard/board.c
+++ b/board/grinn/liteboard/board.c
@@ -17,7 +17,8 @@
#include <asm/mach-imx/boot_mode.h>
#include <asm/io.h>
#include <common.h>
-#include <fsl_esdhc.h>
+#include <env.h>
+#include <fsl_esdhc_imx.h>
#include <linux/sizes.h>
#include <linux/fb.h>
#include <miiphy.h>
@@ -66,7 +67,7 @@
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
static struct fsl_esdhc_cfg sd_cfg = {USDHC1_BASE_ADDR, 0, 4};
#define SD_CD_GPIO IMX_GPIO_NR(1, 19)
diff --git a/board/gumstix/pepper/board.c b/board/gumstix/pepper/board.c
index ea29dcd..f5beb8c 100644
--- a/board/gumstix/pepper/board.c
+++ b/board/gumstix/pepper/board.c
@@ -7,6 +7,7 @@
*/
#include <common.h>
+#include <env.h>
#include <errno.h>
#include <spl.h>
#include <asm/arch/cpu.h>
@@ -25,7 +26,6 @@
#include <miiphy.h>
#include <cpsw.h>
#include <power/tps65217.h>
-#include <environment.h>
#include <watchdog.h>
#include "board.h"
diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c
index 996daff..9563763 100644
--- a/board/highbank/highbank.c
+++ b/board/highbank/highbank.c
@@ -5,6 +5,7 @@
#include <common.h>
#include <ahci.h>
+#include <env.h>
#include <netdev.h>
#include <scsi.h>
diff --git a/board/hisilicon/hikey960/Kconfig b/board/hisilicon/hikey960/Kconfig
new file mode 100644
index 0000000..89f096d
--- /dev/null
+++ b/board/hisilicon/hikey960/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_HIKEY960
+
+config SYS_BOARD
+ default "hikey960"
+
+config SYS_VENDOR
+ default "hisilicon"
+
+config SYS_SOC
+ default "hi3660"
+
+config SYS_CONFIG_NAME
+ default "hikey960"
+
+endif
diff --git a/board/hisilicon/hikey960/MAINTAINERS b/board/hisilicon/hikey960/MAINTAINERS
new file mode 100644
index 0000000..2c98932
--- /dev/null
+++ b/board/hisilicon/hikey960/MAINTAINERS
@@ -0,0 +1,6 @@
+HIKEY960 BOARD
+M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+S: Maintained
+F: board/hisilicon/hikey960
+F: include/configs/hikey960.h
+F: configs/hikey960_defconfig
diff --git a/board/hisilicon/hikey960/Makefile b/board/hisilicon/hikey960/Makefile
new file mode 100644
index 0000000..ea5a709
--- /dev/null
+++ b/board/hisilicon/hikey960/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y := hikey960.o
diff --git a/board/hisilicon/hikey960/README b/board/hisilicon/hikey960/README
new file mode 100644
index 0000000..e1e330d
--- /dev/null
+++ b/board/hisilicon/hikey960/README
@@ -0,0 +1,247 @@
+Introduction
+============
+
+HiKey960 is one of the 96Boards Consumer Edition board from HiSilicon.
+The board/SoC has: -
+* HiSilicon Kirin960 (HI3660) SoC with 4xCortex-A73 and 4xCortex-A53
+* ARM Mali G71 MP8 GPU
+* 3GB LPDDR4 SDRAM
+* 32GB UFS Flash Storage
+* microSD
+* 802.11a/b/g/n WiFi, Bluetooth
+
+More information about this board can be found in 96Boards website:
+https://www.96boards.org/product/hikey960/
+
+Currently the u-boot port supports: -
+* SD card
+
+Compile from source
+===================
+
+First get all the sources
+
+ > mkdir -p ~/hikey960/src ~/hikey960/bin
+ > cd ~/hikey960/src
+ > git clone https://github.com/ARM-software/arm-trusted-firmware
+ > git clone https://github.com/96boards-hikey/OpenPlatformPkg -b testing/hikey960_v1.3.4
+ > git clone https://github.com/96boards-hikey/l-loader -b testing/hikey960_v1.2
+ > wget http://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey960/release/config
+ > wget http://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey960/release/hisi-sec_usb_xloader.img
+ > wget http://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey960/release/hisi-sec_uce_boot.img
+ > wget http://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey960/release/sec_xloader.img
+ > wget http://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey960/release/recovery.bin
+ > wget http://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey960/release/hikey_idt
+
+Get the SCP_BL2 lpm3.img binary. It is shipped as part of the UEFI source.
+The latest version can be obtained from the OpenPlatformPkg repo.
+
+ > cp OpenPlatformPkg/Platforms/Hisilicon/HiKey960/Binary/lpm3.img ~/hikey960/bin/
+
+Compile U-Boot
+==============
+
+ > cd ~/hikey960/src/u-boot
+ > make CROSS_COMPILE=aarch64-linux-gnu- hikey960_defconfig
+ > make CROSS_COMPILE=aarch64-linux-gnu-
+ > cp u-boot.bin ~/hikey960/bin/
+
+Compile ARM Trusted Firmware (ATF)
+==================================
+
+ > cd ~/hikey960/src/arm-trusted-firmware
+ > make CROSS_COMPILE=aarch64-linux-gnu- all fip \
+ SCP_BL2=~/hikey960/bin/lpm3.img \
+ BL33=~/hikey960/bin/u-boot.bin DEBUG=1 PLAT=hikey960
+
+Copy the resulting FIP binary
+ > cp build/hikey960/debug/fip.bin ~/hikey960/bin
+
+Compile l-loader
+================
+ > cd ~/hikey960/src/l-loader
+ > ln -sf ~/hikey960/src/arm-trusted-firmware/build/hikey960/debug/bl1.bin
+ > ln -sf ~/hikey960/src/arm-trusted-firmware/build/hikey960/debug/bl2.bin
+ > ln -sf ~/hikey960/src/arm-trusted-firmware/build/hikey960/debug/fip.bin
+ > ln -sf ~/hikey960/bin/u-boot.bin
+ > make hikey960 PTABLE_LST=linux-32g NS_BL1U=u-boot.bin
+
+Copy the resulting binaries
+ > cp *.img ~/hikey960/bin
+ > cp l-loader.bin ~/hikey960/bin
+
+These instructions are adapted from
+https://github.com/ARM-software/arm-trusted-firmware/blob/master/docs/plat/hikey960.rst
+
+Setup Console
+=============
+
+Install ser2net. Use telnet as the console since UEFI in recovery mode
+output window fails to display in minicom.
+
+ > sudo apt-get install ser2net
+
+Configure ser2net
+
+ > sudo vi /etc/ser2net.conf
+
+Append one line for serial-over-USB in #ser2net.conf
+
+ > 2004:telnet:0:/dev/ttyUSB0:115200 8DATABITS NONE 1STOPBIT banner
+
+Start ser2net
+
+ > sudo killall ser2net
+ > sudo ser2net -u
+
+Open the console.
+
+ > telnet localhost 2004
+
+And you could open the console remotely, too.
+
+Flashing
+========
+
+1. Boot Hikey960 into recovery mode as per the below document:
+https://github.com/96boards/documentation/blob/master/consumer/hikey/hikey960/installation/board-recovery.md
+
+Once Hikey960 is in recovery mode, flash the recovery binary:
+
+ > cd ~/hikey960/src
+ > chmod +x ./hikey_idt
+ > sudo ./hikey_idt -c config -p /dev/ttyUSB1
+
+Now move to the Hikey960 console and press `f` during UEFI boot. This
+will allow the board to boot into fastboot mode. Once the board is in
+fastboot mode, you should see the ID of the HiKey960 board using the
+following command
+
+ > sudo fastboot devices
+
+1ED3822A018E3372 fastboot
+
+3. Flash the images
+
+Now, the images can be flashed using fastboot:
+
+ > sudo fastboot flash ptable ~/hikey960/bin/prm_ptable.img
+ > sudo fastboot flash xloader ~/hikey960/bin/sec_xloader.img
+ > sudo fastboot flash fastboot ~/hikey960/bin/l-loader.bin
+ > sudo fastboot flash fip ~/hikey960/bin/fip.bin
+
+4. Set the "Boot Mode" switch to OFF position for normal boot mode.
+Then power on HiKey960
+
+Observe the console traces using UART6 on the Low Speed Expansion header:
+
+NOTICE: BL2: v2.1(debug):v2.1-531-g3ee48f40
+NOTICE: BL2: Built : 18:15:58, Aug 2 2019
+INFO: BL2: Doing platform setup
+INFO: UFS LUN0 contains 1024 blocks with 4096-byte size
+INFO: UFS LUN1 contains 1024 blocks with 4096-byte size
+INFO: UFS LUN2 contains 2048 blocks with 4096-byte size
+INFO: UFS LUN3 contains 7805952 blocks with 4096-byte size
+INFO: ufs: change power mode success
+INFO: BL2: Loading image id 2
+INFO: Loading image id=2 at address 0x89c80000
+INFO: Image id=2 loaded: 0x89c80000 - 0x89cb5088
+INFO: BL2: Initiating SCP_BL2 transfer to SCP
+INFO: BL2: SCP_BL2: 0x89c80000@0x35088
+INFO: BL2: SCP_BL2 HEAD:
+INFO: BL2: SCP_BL2 0x7000 0x179 0x159 0x149
+INFO: BL2: SCP_BL2 0x189 0x18b 0x18d 0x0
+INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x18f
+INFO: BL2: SCP_BL2 0x191 0x0 0x193 0x195
+INFO: BL2: SCP_BL2 0x18fd 0x18fd 0x18fd 0x18fd
+INFO: BL2: SCP_BL2 0x18fd 0x18fd 0x18fd 0x18fd
+INFO: BL2: SCP_BL2 0x18fd 0x18fd 0x18fd 0x18fd
+INFO: BL2: SCP_BL2 0x4d454355 0x43494741 0x424d554e 0x21215245
+INFO: BL2: SCP_BL2 0x4a054904 0x42912000 0xf841bfbc 0xe7fa0b04
+INFO: BL2: SCP_BL2 0xb88cf000 0x3b18 0x3d1c 0x6809493e
+INFO: BL2: SCP_BL2 0x4613680a 0x201f102 0xf0002a04 0x600a804c
+INFO: BL2: SCP_BL2 0x204f04f 0xf203fb02 0xf102440a 0x60100204
+INFO: BL2: SCP_BL2 0x160f04f 0xf103fb01 0x68004834 0x61044408
+INFO: BL2: SCP_BL2 0x61866145 0xf8c061c7 0xf8c08020 0xf8c09024
+INFO: BL2: SCP_BL2 0xf8c0a028 0xf3efb02c 0xf3ef8208 0x68118309
+INFO: BL2: SCP_BL2 0xf1026401 0xf0110204 0xbf070f04 0x46113220
+INFO: BL2: SCP_BL2 TAIL:
+INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO: BL2: SCP_BL2 0x0 0x19cad151 0x19b80040 0x0
+INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+INFO: BL2: SCP_BL2 transferred to SCP
+INFO: start fw loading
+INFO: fw load success
+WARNING: BL2: Platform setup already done!!
+INFO: BL2: Loading image id 3
+INFO: Loading image id=3 at address 0x1ac58000
+INFO: Image id=3 loaded: 0x1ac58000 - 0x1ac63024
+INFO: BL2: Loading image id 5
+INFO: Loading image id=5 at address 0x1ac98000
+INFO: Image id=5 loaded: 0x1ac98000 - 0x1ad0819c
+NOTICE: BL2: Booting BL31
+INFO: Entry point address = 0x1ac58000
+INFO: SPSR = 0x3cd
+NOTICE: BL31: v2.1(debug):v2.1-531-g3ee48f40
+NOTICE: BL31: Built : 18:16:01, Aug 2 2019
+INFO: ARM GICv2 driver initialized
+INFO: BL31: Initializing runtime services
+INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
+INFO: plat_setup_psci_ops: sec_entrypoint=0x1ac580fc
+INFO: BL31: Preparing for EL3 exit to normal world
+INFO: Entry point address = 0x1ac98000
+INFO: SPSR = 0x3c9
+
+
+U-Boot 2019.07-00628-g286f05a6fc-dirty (Aug 02 2019 - 17:14:05 +0530)
+Hikey960
+
+DRAM: 3 GiB
+PSCI: v1.1
+MMC: dwmmc1@ff37f000: 0
+Loading Environment from EXT4... ** File not found /uboot.env **
+
+** Unable to read "/uboot.env" from mmc0:2 **
+In: serial@fff32000
+Out: serial@fff32000
+Err: serial@fff32000
+Net: Net Initialization Skipped
+No ethernet found.
+Hit any key to stop autoboot: 0
+switch to partitions #0, OK
+mmc0 is current device
+Scanning mmc 0:1...
+Found /extlinux/extlinux.conf
+Retrieving file: /extlinux/extlinux.conf
+201 bytes read in 12 ms (15.6 KiB/s)
+1: hikey960-kernel
+Retrieving file: /Image
+24689152 bytes read in 4377 ms (5.4 MiB/s)
+append: earlycon=pl011,mmio32,0xfff32000 console=ttyAMA6,115200 rw root=/dev/mmcblk0p2 rot
+Retrieving file: /hi3660-hikey960.dtb
+35047 bytes read in 14 ms (2.4 MiB/s)
+## Flattened Device Tree blob at 10000000
+ Booting using the fdt blob at 0x10000000
+ Using Device Tree in place at 0000000010000000, end 000000001000b8e6
+
+Starting kernel ...
+
+[ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
+[ 0.000000] Linux version 5.2.0-03138-gd75da80dce39 (mani@Mani-XPS-13-9360) (gcc versi9
+[ 0.000000] Machine model: HiKey960
+[ 0.000000] earlycon: pl11 at MMIO32 0x00000000fff32000 (options '')
+[ 0.000000] printk: bootconsole [pl11] enabled
+[ 0.000000] efi: Getting EFI parameters from FDT:
diff --git a/board/hisilicon/hikey960/hikey960.c b/board/hisilicon/hikey960/hikey960.c
new file mode 100644
index 0000000..eb9b99e
--- /dev/null
+++ b/board/hisilicon/hikey960/hikey960.c
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Linaro
+ * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/hi3660.h>
+#include <asm/armv8/mmu.h>
+#include <asm/psci.h>
+#include <linux/arm-smccc.h>
+#include <linux/psci.h>
+
+#define PMIC_REG_TO_BUS_ADDR(x) (x << 2)
+#define PMIC_VSEL_MASK 0x7
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if !CONFIG_IS_ENABLED(OF_CONTROL)
+#include <dm/platform_data/serial_pl01x.h>
+
+static const struct pl01x_serial_platdata serial_platdata = {
+ .base = HI3660_UART6_BASE,
+ .type = TYPE_PL011,
+ .clock = 19200000
+};
+
+U_BOOT_DEVICE(hikey960_serial0) = {
+ .name = "serial_pl01x",
+ .platdata = &serial_platdata,
+};
+#endif
+
+static struct mm_region hikey_mem_map[] = {
+ {
+ .virt = 0x0UL, /* DDR */
+ .phys = 0x0UL,
+ .size = 0xC0000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xE0000000UL, /* Peripheral block */
+ .phys = 0xE0000000UL,
+ .size = 0x20000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = hikey_mem_map;
+
+int board_early_init_f(void)
+{
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+
+ return 0;
+}
+
+void hikey960_sd_init(void)
+{
+ u32 data;
+
+ /* Enable FPLL0 */
+ data = readl(SCTRL_SCFPLLCTRL0);
+ data |= SCTRL_SCFPLLCTRL0_FPLL0_EN;
+ writel(data, SCTRL_SCFPLLCTRL0);
+
+ /* Configure LDO16 */
+ data = readl(PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x79)) &
+ PMIC_VSEL_MASK;
+ data |= 6;
+ writel(data, PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x79));
+
+ data = readl(PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x78));
+ data |= 2;
+ writel(data, PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x78));
+
+ udelay(100);
+
+ /* Configure LDO9 */
+ data = readl(PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x6b)) &
+ PMIC_VSEL_MASK;
+ data |= 5;
+ writel(data, PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x6b));
+
+ data = readl(PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x6a));
+ data |= 2;
+ writel(data, PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x6a));
+
+ udelay(100);
+
+ /* GPIO CD */
+ writel(0, PINMUX4_SDDET);
+
+ /* SD Pinconf */
+ writel(15 << 4, PINCONF3_SDCLK);
+ writel((1 << 0) | (8 << 4), PINCONF3_SDCMD);
+ writel((1 << 0) | (8 << 4), PINCONF3_SDDATA0);
+ writel((1 << 0) | (8 << 4), PINCONF3_SDDATA1);
+ writel((1 << 0) | (8 << 4), PINCONF3_SDDATA2);
+ writel((1 << 0) | (8 << 4), PINCONF3_SDDATA3);
+
+ /* Set SD clock mux */
+ do {
+ data = readl(CRG_REG_BASE + 0xb8);
+ data |= ((1 << 6) | (1 << 6 << 16) | (0 << 4) | (3 << 4 << 16));
+ writel(data, CRG_REG_BASE + 0xb8);
+
+ data = readl(CRG_REG_BASE + 0xb8);
+ } while ((data & ((1 << 6) | (3 << 4))) != ((1 << 6) | (0 << 4)));
+
+ /* Take SD out of reset */
+ writel(1 << 18, CRG_PERRSTDIS4);
+ do {
+ data = readl(CRG_PERRSTSTAT4);
+ } while ((data & (1 << 18)) == (1 << 18));
+
+ /* Enable hclk_gate_sd */
+ data = readl(CRG_REG_BASE + 0);
+ data |= (1 << 30);
+ writel(data, CRG_REG_BASE + 0);
+
+ /* Enable clk_andgt_mmc */
+ data = readl(CRG_REG_BASE + 0xf4);
+ data |= ((1 << 3) | (1 << 3 << 16));
+ writel(data, CRG_REG_BASE + 0xf4);
+
+ /* Enable clk_gate_sd */
+ data = readl(CRG_PEREN4);
+ data |= (1 << 17);
+ writel(data, CRG_PEREN4);
+ do {
+ data = readl(CRG_PERCLKEN4);
+ } while ((data & (1 << 17)) != (1 << 17));
+}
+
+static void show_psci_version(void)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
+
+ printf("PSCI: v%ld.%ld\n",
+ PSCI_VERSION_MAJOR(res.a0),
+ PSCI_VERSION_MINOR(res.a0));
+}
+
+int board_init(void)
+{
+ /* Init SD */
+ hikey960_sd_init();
+
+ show_psci_version();
+
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+ psci_system_reset();
+}
diff --git a/board/hisilicon/poplar/poplar.c b/board/hisilicon/poplar/poplar.c
index 7794844..4926419 100644
--- a/board/hisilicon/poplar/poplar.c
+++ b/board/hisilicon/poplar/poplar.c
@@ -155,6 +155,7 @@
}
#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
+#include <env.h>
#include <usb.h>
#include <usb/dwc2_udc.h>
#include <g_dnl.h>
diff --git a/board/imgtec/ci20/ci20.c b/board/imgtec/ci20/ci20.c
index 9811ef5..5368b67 100644
--- a/board/imgtec/ci20/ci20.c
+++ b/board/imgtec/ci20/ci20.c
@@ -7,7 +7,7 @@
*/
#include <common.h>
-#include <environment.h>
+#include <env.h>
#include <net.h>
#include <netdev.h>
#include <asm/io.h>
diff --git a/board/intel/Kconfig b/board/intel/Kconfig
index 5131836..7b16ec4 100644
--- a/board/intel/Kconfig
+++ b/board/intel/Kconfig
@@ -73,6 +73,19 @@
Note that PCIE_ECAM_BASE is set up by the FSP so the value used
by U-Boot matches that value.
+config TARGET_SLIMBOOTLOADER
+ bool "slimbootloader"
+ help
+ This target is used for running U-Boot on top of Slim Bootloader
+ boot firmware as a payload. Slim Bootloader does memory initialization
+ and silicon initialization, and it passes necessary information in
+ HOB (Hand Off Block) to a payload. The payload consumes HOB data
+ which is generated by Slim Bootloader for its driver initialization.
+ Slim Bootloader consumes FSP and its HOB, but FSP HOB is cleared
+ Before launching a payload. Instead, Slim Bootloader generates its
+ HOB data such as memory info, serial port info and so on.
+ Refer to doc/board/intel/slimbootloader.rst for the details.
+
endchoice
source "board/intel/bayleybay/Kconfig"
@@ -82,5 +95,6 @@
source "board/intel/edison/Kconfig"
source "board/intel/galileo/Kconfig"
source "board/intel/minnowmax/Kconfig"
+source "board/intel/slimbootloader/Kconfig"
endif
diff --git a/board/intel/edison/edison.c b/board/intel/edison/edison.c
index 5faf3c5..f56b5b1 100644
--- a/board/intel/edison/edison.c
+++ b/board/intel/edison/edison.c
@@ -4,7 +4,7 @@
*/
#include <common.h>
#include <dwc3-uboot.h>
-#include <environment.h>
+#include <env.h>
#include <mmc.h>
#include <u-boot/md5.h>
#include <usb.h>
@@ -13,9 +13,19 @@
#include <linux/usb/gadget.h>
#include <asm/cache.h>
+#include <asm/pmu.h>
#include <asm/scu.h>
#include <asm/u-boot-x86.h>
+/* List of Intel Tangier LSSs */
+#define PMU_LSS_TANGIER_SDIO0_01 1
+
+int board_early_init_r(void)
+{
+ pmu_turn_power(PMU_LSS_TANGIER_SDIO0_01, true);
+ return 0;
+}
+
static struct dwc3_device dwc3_device_data = {
.maximum_speed = USB_SPEED_HIGH,
.base = CONFIG_SYS_USB_OTG_BASE,
diff --git a/board/intel/slimbootloader/Kconfig b/board/intel/slimbootloader/Kconfig
new file mode 100644
index 0000000..8c7e22c
--- /dev/null
+++ b/board/intel/slimbootloader/Kconfig
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2019 Intel Corporation <www.intel.com>
+
+if TARGET_SLIMBOOTLOADER
+
+config SYS_BOARD
+ default "slimbootloader"
+
+config SYS_VENDOR
+ default "intel"
+
+config SYS_SOC
+ default "slimbootloader"
+
+config SYS_CONFIG_NAME
+ default "slimbootloader"
+
+config SYS_TEXT_BASE
+ default 0x00100000
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select SYS_SLIMBOOTLOADER
+ select USB_STORAGE
+ select USB_KEYBOARD
+
+endif
diff --git a/board/intel/slimbootloader/MAINTAINERS b/board/intel/slimbootloader/MAINTAINERS
new file mode 100644
index 0000000..e693551
--- /dev/null
+++ b/board/intel/slimbootloader/MAINTAINERS
@@ -0,0 +1,6 @@
+Intel Slim Bootloader Payload
+M: Aiden Park <aiden.park@intel.com>
+S: Maintained
+F: board/intel/slimbootloader
+F: include/configs/slimbootloader.h
+F: configs/slimbootloader_defconfig
diff --git a/board/intel/slimbootloader/Makefile b/board/intel/slimbootloader/Makefile
new file mode 100644
index 0000000..fd8fa98
--- /dev/null
+++ b/board/intel/slimbootloader/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2019 Intel Corporation <www.intel.com>
+
+obj-y += start.o slimbootloader.o
diff --git a/board/intel/slimbootloader/slimbootloader.c b/board/intel/slimbootloader/slimbootloader.c
new file mode 100644
index 0000000..f50eeb8
--- /dev/null
+++ b/board/intel/slimbootloader/slimbootloader.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#include <common.h>
+
+int board_early_init_r(void)
+{
+ /*
+ * Make sure PCI bus is enumerated so that peripherals on the PCI bus
+ * can be discovered by their drivers.
+ *
+ * Slim Bootloader has already done PCI bus enumeration before loading
+ * U-Boot, so U-Boot needs to preserve PCI configuration.
+ * Therefore, '# CONFIG_PCI_PNP is not set' is included in defconfig.
+ */
+ pci_init();
+
+ return 0;
+}
diff --git a/board/intel/slimbootloader/start.S b/board/intel/slimbootloader/start.S
new file mode 100644
index 0000000..5c3f3df
--- /dev/null
+++ b/board/intel/slimbootloader/start.S
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+/* board early initialization */
+.globl early_board_init
+early_board_init:
+ jmp early_board_init_ret
diff --git a/board/inversepath/usbarmory/usbarmory.c b/board/inversepath/usbarmory/usbarmory.c
index a490aa8..de4ad83 100644
--- a/board/inversepath/usbarmory/usbarmory.c
+++ b/board/inversepath/usbarmory/usbarmory.c
@@ -17,7 +17,7 @@
#include <linux/errno.h>
#include <i2c.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <asm/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/isee/igep003x/board.c b/board/isee/igep003x/board.c
index 965a009..a8c2b12 100644
--- a/board/isee/igep003x/board.c
+++ b/board/isee/igep003x/board.c
@@ -6,6 +6,7 @@
*/
#include <common.h>
+#include <env.h>
#include <errno.h>
#include <spl.h>
#include <asm/arch/cpu.h>
@@ -25,7 +26,6 @@
#include <fdt_support.h>
#include <mtd_node.h>
#include <jffs2/load_kernel.h>
-#include <environment.h>
#include "board.h"
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c
index 367af82..74fc5f0 100644
--- a/board/isee/igep00x0/igep00x0.c
+++ b/board/isee/igep00x0/igep00x0.c
@@ -4,6 +4,7 @@
* ISEE 2007 SL, <www.iseebcn.com>
*/
#include <common.h>
+#include <env.h>
#include <status_led.h>
#include <dm.h>
#include <ns16550.h>
diff --git a/board/k+p/kp_imx53/kp_id_rev.c b/board/k+p/kp_imx53/kp_id_rev.c
index e8f5176..9dae54d 100644
--- a/board/k+p/kp_imx53/kp_id_rev.c
+++ b/board/k+p/kp_imx53/kp_id_rev.c
@@ -10,7 +10,7 @@
*/
#include <common.h>
-#include <environment.h>
+#include <env.h>
#include <i2c.h>
#include "kp_id_rev.h"
diff --git a/board/k+p/kp_imx53/kp_imx53.c b/board/k+p/kp_imx53/kp_imx53.c
index b447e13..84cddd4 100644
--- a/board/k+p/kp_imx53/kp_imx53.c
+++ b/board/k+p/kp_imx53/kp_imx53.c
@@ -13,6 +13,7 @@
#include <asm/arch/iomux-mx53.h>
#include <asm/arch/clock.h>
#include <asm/gpio.h>
+#include <env.h>
#include <power/pmic.h>
#include <fsl_pmic.h>
#include "kp_id_rev.h"
diff --git a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c
index ace986f..2c541ac 100644
--- a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c
+++ b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c
@@ -17,8 +17,9 @@
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
+#include <env.h>
#include <errno.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <fuse.h>
#include <i2c.h>
#include <miiphy.h>
@@ -166,7 +167,7 @@
}
#endif
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
static struct fsl_esdhc_cfg usdhc_cfg[] = {
diff --git a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c
index d89e112..e284d5e 100644
--- a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c
+++ b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c
@@ -20,7 +20,7 @@
#include <asm/io.h>
#include <errno.h>
#include <fuse.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <i2c.h>
#include <mmc.h>
#include <spl.h>
diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig
new file mode 100644
index 0000000..acaa928
--- /dev/null
+++ b/board/keymile/Kconfig
@@ -0,0 +1,117 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2019, Pascal Linder <pascal.linder@edu.hefr.ch>
+
+config VENDOR_KM
+ bool
+ help
+ Selected by any KM board to have additional configurations.
+
+if VENDOR_KM
+
+menu "KM Board Setup"
+
+config KM_PNVRAM
+ hex "Pseudo RAM"
+ default 0x80000
+ help
+ Start address of the pseudo non-volatile RAM for application.
+
+config KM_PHRAM
+ hex "Physical RAM"
+ default 0x17F000 if ARM
+ default 0x100000 if PPC
+ help
+ Start address of the physical RAM, which is the mounted /var folder.
+
+config KM_RESERVED_PRAM
+ hex "Reserved RAM"
+ default 0x801000 if KIRKWOOD
+ default 0x0 if MPC83xx
+ default 0x1000 if MPC85xx
+ help
+ Reserved physical RAM area at the end of memory for special purposes.
+
+config KM_CRAMFS_ADDR
+ hex "CRAMFS Address"
+ default 0x2400000 if KIRKWOOD
+ default 0xC00000 if MPC83xx
+ default 0x2000000 if MPC85xx
+ help
+ Start address of the CRAMFS containing the Linux kernel.
+
+config KM_KERNEL_ADDR
+ hex "Kernel Load Address"
+ default 0x2000000 if KIRKWOOD
+ default 0x400000 if MPC83xx
+ default 0x1000000 if MPC85xx
+ help
+ Address where to load Linux kernel in RAM.
+
+config KM_FDT_ADDR
+ hex "FDT Load Address"
+ default 0x23E0000 if KIRKWOOD
+ default 0xB80000 if MPC83xx
+ default 0x1F80000 if MPC85xx
+ help
+ Address where to load flattened device tree in RAM.
+
+config KM_CONSOLE_TTY
+ string "KM Console"
+ default "ttyS0"
+ help
+ TTY console to use on board.
+
+config KM_COMMON_ETH_INIT
+ bool "Common Ethernet Initialization"
+ default y if KIRKWOOD || MPC83xx
+ default n if MPC85xx
+ help
+ Use the Ethernet initialization implemented in common code, which
+ detects if a Piggy board is present.
+
+config PIGGY_MAC_ADRESS_OFFSET
+ int "Piggy Address Offset"
+ default 0
+ help
+ MAC address offset for the Piggy board.
+
+config KM_MVEXTSW_ADDR
+ hex "Marvell Switch Address"
+ depends on MV88E6352_SWITCH
+ default 0x10
+ help
+ Address of external Marvell switch.
+
+config KM_IVM_BUS
+ int "IVM I2C Bus"
+ default 1 if KIRKWOOD || MPC85xx
+ default 2 if MPC83xx
+ help
+ Identifier number of I2C bus, where the inventory EEPROM is connected to.
+
+config SYS_IVM_EEPROM_ADR
+ hex "IVM I2C Address"
+ default 0x50
+ help
+ I2C address of the EEPROM containing the inventory.
+
+config SYS_IVM_EEPROM_MAX_LEN
+ hex "IVM Length"
+ default 0x400
+ help
+ Maximum length of inventory in EEPROM.
+
+config SYS_IVM_EEPROM_PAGE_LEN
+ hex "IVM Page Size"
+ default 0x100
+ help
+ Page size of inventory in EEPROM.
+
+source "board/keymile/km83xx/Kconfig"
+source "board/keymile/kmp204x/Kconfig"
+source "board/keymile/km_arm/Kconfig"
+
+endmenu
+
+endif
diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c
index 92d4a6f..08f7f8d 100644
--- a/board/keymile/common/common.c
+++ b/board/keymile/common/common.c
@@ -8,6 +8,7 @@
*/
#include <common.h>
+#include <env.h>
#include <ioports.h>
#include <command.h>
#include <malloc.h>
diff --git a/board/keymile/common/common.h b/board/keymile/common/common.h
index 859d913..42b760d 100644
--- a/board/keymile/common/common.h
+++ b/board/keymile/common/common.h
@@ -120,10 +120,6 @@
u8 pb_dbug;
};
-#if !defined(CONFIG_PIGGY_MAC_ADRESS_OFFSET)
-#define CONFIG_PIGGY_MAC_ADRESS_OFFSET 0
-#endif
-
int ethernet_present(void);
int ivm_read_eeprom(unsigned char *buf, int len);
int ivm_analyze_eeprom(unsigned char *buf, int len);
diff --git a/board/keymile/common/ivm.c b/board/keymile/common/ivm.c
index 23bd21c..50df44d 100644
--- a/board/keymile/common/ivm.c
+++ b/board/keymile/common/ivm.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <cli_hush.h>
+#include <env.h>
#include <i2c.h>
#include "common.h"
@@ -310,11 +311,6 @@
/* if an offset is defined, add it */
process_mac(valbuf, page2, CONFIG_PIGGY_MAC_ADRESS_OFFSET, true);
env_set((char *)"ethaddr", (char *)valbuf);
-#ifdef CONFIG_KMVECT1
-/* KMVECT1 has two ethernet interfaces */
- process_mac(valbuf, page2, 1, true);
- env_set((char *)"eth1addr", (char *)valbuf);
-#endif
#else
/* KMTEGR1 has a special setup. eth0 has no connection to the outside and
* gets an locally administred MAC address, eth1 is the debug interface and
diff --git a/board/keymile/km83xx/Kconfig b/board/keymile/km83xx/Kconfig
index fbbbb17..1011cc8 100644
--- a/board/keymile/km83xx/Kconfig
+++ b/board/keymile/km83xx/Kconfig
@@ -9,6 +9,13 @@
config SYS_CONFIG_NAME
default "kmeter1"
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_MPC8360
+ imply CMD_CRAMFS
+ imply CMD_DIAG
+ imply FS_CRAMFS
+
endif
if TARGET_KMCOGE5NE
@@ -22,18 +29,12 @@
config SYS_CONFIG_NAME
default "kmcoge5ne"
-endif
-
-if TARGET_KMVECT1
-
-config SYS_BOARD
- default "km83xx"
-
-config SYS_VENDOR
- default "keymile"
-
-config SYS_CONFIG_NAME
- default "kmvect1"
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_MPC8360
+ imply CMD_CRAMFS
+ imply CMD_DIAG
+ imply FS_CRAMFS
endif
@@ -48,6 +49,12 @@
config SYS_CONFIG_NAME
default "kmtegr1"
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_MPC8309
+ imply CMD_CRAMFS
+ imply FS_CRAMFS
+
endif
if TARGET_SUVD3
@@ -61,6 +68,12 @@
config SYS_CONFIG_NAME
default "suvd3"
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_MPC832X
+ imply CMD_CRAMFS
+ imply FS_CRAMFS
+
endif
if TARGET_TUXX1
@@ -74,6 +87,12 @@
config SYS_CONFIG_NAME
default "tuxx1"
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_MPC832X
+ imply CMD_CRAMFS
+ imply FS_CRAMFS
+
endif
if TARGET_KMSUPX5
@@ -87,6 +106,12 @@
config SYS_CONFIG_NAME
default "kmsupx5"
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_MPC832X
+ imply CMD_CRAMFS
+ imply FS_CRAMFS
+
endif
if TARGET_TUGE1
@@ -100,6 +125,12 @@
config SYS_CONFIG_NAME
default "tuge1"
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_MPC832X
+ imply CMD_CRAMFS
+ imply FS_CRAMFS
+
endif
if TARGET_KMOPTI2
@@ -113,6 +144,12 @@
config SYS_CONFIG_NAME
default "kmopti2"
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_MPC832X
+ imply CMD_CRAMFS
+ imply FS_CRAMFS
+
endif
if TARGET_KMTEPR2
@@ -126,4 +163,10 @@
config SYS_CONFIG_NAME
default "kmtepr2"
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_MPC832X
+ imply CMD_CRAMFS
+ imply FS_CRAMFS
+
endif
diff --git a/board/keymile/km83xx/MAINTAINERS b/board/keymile/km83xx/MAINTAINERS
index 94e0d57..d2af983 100644
--- a/board/keymile/km83xx/MAINTAINERS
+++ b/board/keymile/km83xx/MAINTAINERS
@@ -10,7 +10,6 @@
F: configs/kmtepr2_defconfig
F: include/configs/suvd3.h
F: configs/kmtegr1_defconfig
-F: configs/kmvect1_defconfig
F: configs/suvd3_defconfig
F: configs/tuge1_defconfig
F: configs/tuxx1_defconfig
diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c
index 880ce67..8846b64 100644
--- a/board/keymile/km83xx/km83xx.c
+++ b/board/keymile/km83xx/km83xx.c
@@ -14,6 +14,7 @@
*/
#include <common.h>
+#include <env.h>
#include <ioports.h>
#include <mpc83xx.h>
#include <i2c.h>
@@ -124,19 +125,10 @@
return in_8(&base->bprth) & PIGGY_PRESENT;
}
-#if defined(CONFIG_KMVECT1)
-int ethernet_present(void)
-{
- /* ethernet port connected to simple switch without piggy */
- return 1;
-}
-#else
int ethernet_present(void)
{
return piggy_present();
}
-#endif
-
int board_early_init_r(void)
{
@@ -197,80 +189,8 @@
return 0;
}
-#if defined(CONFIG_KMVECT1)
-#include <mv88e6352.h>
-/* Marvell MV88E6122 switch configuration */
-static struct mv88e_sw_reg extsw_conf[] = {
- /* port 1, FRONT_MDI, autoneg */
- { PORT(1), PORT_PHY, NO_SPEED_FOR },
- { PORT(1), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
- { PHY(1), PHY_1000_CTRL, NO_ADV },
- { PHY(1), PHY_SPEC_CTRL, AUTO_MDIX_EN },
- { PHY(1), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
- FULL_DUPLEX },
- /* port 2, unused */
- { PORT(2), PORT_CTRL, PORT_DIS },
- { PHY(2), PHY_CTRL, PHY_PWR_DOWN },
- { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
- /* port 3, BP_MII (CPU), PHY mode, 100BASE */
- { PORT(3), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
- /* port 4, ESTAR to slot 11, SerDes, 1000BASE-X */
- { PORT(4), PORT_STATUS, NO_PHY_DETECT },
- { PORT(4), PORT_PHY, SPEED_1000_FOR },
- { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
- /* port 5, ESTAR to slot 13, SerDes, 1000BASE-X */
- { PORT(5), PORT_STATUS, NO_PHY_DETECT },
- { PORT(5), PORT_PHY, SPEED_1000_FOR },
- { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
- /*
- * Errata Fix: 1.9V Output from Internal 1.8V Regulator,
- * acc . MV-S300889-00D.pdf , clause 4.5
- */
- { PORT(5), 0x1A, 0xADB1 },
- /* port 6, unused, this port has no phy */
- { PORT(6), PORT_CTRL, PORT_DIS },
- /*
- * Errata Fix: 1.9V Output from Internal 1.8V Regulator,
- * acc . MV-S300889-00D.pdf , clause 4.5
- */
- { PORT(5), 0x1A, 0xADB1 },
-};
-#endif
-
int last_stage_init(void)
{
-#if defined(CONFIG_KMVECT1)
- struct km_bec_fpga __iomem *base =
- (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE;
- u8 tmp_reg;
-
- /* Release mv88e6122 from reset */
- tmp_reg = in_8(&base->res1[0]) | 0x10; /* DIRECT3 register */
- out_8(&base->res1[0], tmp_reg); /* GP28 as output */
- tmp_reg = in_8(&base->gprt3) | 0x10; /* GP28 to high */
- out_8(&base->gprt3, tmp_reg);
-
- /* configure MV88E6122 switch */
- char *name = "UEC2";
-
- if (miiphy_set_current_dev(name))
- return 0;
-
- mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf,
- ARRAY_SIZE(extsw_conf));
-
- mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR);
-
- if (piggy_present()) {
- env_set("ethact", "UEC2");
- env_set("netdev", "eth1");
- puts("using PIGGY for network boot\n");
- } else {
- env_set("netdev", "eth0");
- puts("using frontport for network boot\n");
- }
-#endif
-
#if defined(CONFIG_TARGET_KMCOGE5NE)
struct bfticu_iomap *base =
(struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE;
diff --git a/board/keymile/km_arm/Kconfig b/board/keymile/km_arm/Kconfig
index 3476780..be6b162 100644
--- a/board/keymile/km_arm/Kconfig
+++ b/board/keymile/km_arm/Kconfig
@@ -1,3 +1,32 @@
+menu "KM ARM Options"
+ depends on ARM
+
+config KM_FPGA_CONFIG
+ bool "FPGA Configuration"
+ default n
+ help
+ Include capability to change FPGA configuration.
+
+config KM_ENV_IS_IN_SPI_NOR
+ bool "Environment in SPI NOR"
+ default n
+ help
+ Put the U-Boot environment in the SPI NOR flash.
+
+config KM_PIGGY4_88E6061
+ bool "Piggy via Switch 88E6061"
+ default n
+ help
+ The Piggy4 board is connected via a Marvell 88E6061 switch.
+
+config KM_PIGGY4_88E6352
+ bool "Piggy via Switch 88E6352"
+ default n
+ help
+ The Piggy4 board is connected via a Marvell 88E6352 switch.
+
+endmenu
+
if TARGET_KM_KIRKWOOD
config SYS_BOARD
@@ -9,4 +38,16 @@
config SYS_CONFIG_NAME
default "km_kirkwood"
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select BOARD_LATE_INIT
+ select DM
+ select DM_ETH
+ select DM_SERIAL
+ select DM_SPI
+ select DM_SPI_FLASH
+ imply CMD_CRAMFS
+ imply CMD_DIAG
+ imply FS_CRAMFS
+
endif
diff --git a/board/keymile/km_arm/MAINTAINERS b/board/keymile/km_arm/MAINTAINERS
index d156e85..d80589d 100644
--- a/board/keymile/km_arm/MAINTAINERS
+++ b/board/keymile/km_arm/MAINTAINERS
@@ -11,4 +11,3 @@
F: configs/kmsugp1_defconfig
F: configs/kmsuv31_defconfig
F: configs/mgcoge3un_defconfig
-F: configs/portl2_defconfig
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index ea03be9..922cc62 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -12,6 +12,7 @@
*/
#include <common.h>
+#include <env.h>
#include <i2c.h>
#include <nand.h>
#include <netdev.h>
@@ -310,16 +311,35 @@
return 0;
}
-int board_spi_claim_bus(struct spi_slave *slave)
+static const u32 spi_mpp_config[] = {
+ MPP1_SPI_MOSI,
+ MPP2_SPI_SCK,
+ MPP3_SPI_MISO,
+ 0
+};
+
+static u32 spi_mpp_backup[4];
+
+int mvebu_board_spi_claim_bus(struct udevice *dev)
{
+ spi_mpp_backup[3] = 0;
+
+ /* set new spi mpp config and save current one */
+ kirkwood_mpp_conf(spi_mpp_config, spi_mpp_backup);
+
kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0);
return 0;
}
-void board_spi_release_bus(struct spi_slave *slave)
+int mvebu_board_spi_release_bus(struct udevice *dev)
{
+ /* restore saved mpp config */
+ kirkwood_mpp_conf(spi_mpp_backup, NULL);
+
kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1);
+
+ return 0;
}
#if (defined(CONFIG_KM_PIGGY4_88E6061))
diff --git a/board/keymile/kmp204x/Kconfig b/board/keymile/kmp204x/Kconfig
index 7b45a13..f74d429 100644
--- a/board/keymile/kmp204x/Kconfig
+++ b/board/keymile/kmp204x/Kconfig
@@ -9,4 +9,12 @@
config SYS_CONFIG_NAME
default "kmp204x"
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_P2041
+ select FSL_DDR_INTERACTIVE
+ select PHYS_64BIT
+ imply CMD_CRAMFS
+ imply FS_CRAMFS
+
endif
diff --git a/board/keymile/kmp204x/MAINTAINERS b/board/keymile/kmp204x/MAINTAINERS
index c5170c9..fb3aefd 100644
--- a/board/keymile/kmp204x/MAINTAINERS
+++ b/board/keymile/kmp204x/MAINTAINERS
@@ -4,4 +4,3 @@
F: board/keymile/kmp204x/
F: include/configs/kmp204x.h
F: configs/kmcoge4_defconfig
-F: configs/kmlion1_defconfig
diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c
index e7dcefa..4d1e38a 100644
--- a/board/keymile/kmp204x/kmp204x.c
+++ b/board/keymile/kmp204x/kmp204x.c
@@ -8,6 +8,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <netdev.h>
#include <linux/compiler.h>
#include <asm/mmu.h>
diff --git a/board/kosagi/novena/novena.c b/board/kosagi/novena/novena.c
index 78294b8..b7b747d 100644
--- a/board/kosagi/novena/novena.c
+++ b/board/kosagi/novena/novena.c
@@ -9,6 +9,7 @@
#include <dm.h>
#include <dm/device-internal.h>
#include <ahci.h>
+#include <env.h>
#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/io.h>
@@ -24,8 +25,7 @@
#include <asm/mach-imx/sata.h>
#include <asm/mach-imx/video.h>
#include <dwc_ahsata.h>
-#include <environment.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <i2c.h>
#include <input.h>
#include <ipu_pixfmt.h>
diff --git a/board/kosagi/novena/novena_spl.c b/board/kosagi/novena/novena_spl.c
index b2d670e..00210ab 100644
--- a/board/kosagi/novena/novena_spl.c
+++ b/board/kosagi/novena/novena_spl.c
@@ -19,7 +19,7 @@
#include <asm/arch/crm_regs.h>
#include <i2c.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <spl.h>
#include <asm/arch/mx6-ddr.h>
@@ -404,7 +404,7 @@
/*
* SPL boots from uSDHC card
*/
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
static struct fsl_esdhc_cfg usdhc_cfg = {
USDHC3_BASE_ADDR, 0, 4
};
@@ -566,7 +566,7 @@
#ifdef CONFIG_BOARD_POSTCLK_INIT
board_postclk_init();
#endif
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
get_clocks();
#endif
diff --git a/board/laird/wb50n/wb50n.c b/board/laird/wb50n/wb50n.c
index 89d3795..a2f8eaf 100644
--- a/board/laird/wb50n/wb50n.c
+++ b/board/laird/wb50n/wb50n.c
@@ -11,6 +11,7 @@
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/clk.h>
+#include <env.h>
#include <micrel.h>
#include <net.h>
#include <netdev.h>
diff --git a/board/lego/ev3/README b/board/lego/ev3/README
index da62a64..9ad93e8 100644
--- a/board/lego/ev3/README
+++ b/board/lego/ev3/README
@@ -50,3 +50,6 @@
If you are booting from the microSD card, it is enough to just write uboot.bin
to the flash. If you are not using a microSD card, you will need to create an
image file using the layout described above.
+
+IMPORTANT: The EEPROM bootloader only copies 256k, so u-boot.img must not
+exceed that size!
diff --git a/board/lego/ev3/legoev3.c b/board/lego/ev3/legoev3.c
index 423c2fa..fa099e9 100644
--- a/board/lego/ev3/legoev3.c
+++ b/board/lego/ev3/legoev3.c
@@ -25,11 +25,6 @@
#include <asm/mach-types.h>
#include <asm/setup.h>
-#ifdef CONFIG_MMC_DAVINCI
-#include <mmc.h>
-#include <asm/arch/sdmmc_defs.h>
-#endif
-
DECLARE_GLOBAL_DATA_PTR;
u8 board_rev;
@@ -38,23 +33,6 @@
#define EEPROM_REV_OFFSET 0x3F00
#define EEPROM_MAC_OFFSET 0x3F06
-#ifdef CONFIG_MMC_DAVINCI
-static struct davinci_mmc mmc_sd0 = {
- .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
- .host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */
- .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
- .version = MMC_CTLR_VERSION_2,
-};
-
-int board_mmc_init(bd_t *bis)
-{
- mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID);
-
- /* Add slot-0 to mmc subsystem */
- return davinci_mmc_init(bis, &mmc_sd0);
-}
-#endif
-
const struct pinmux_resource pinmuxes[] = {
PINMUX_ITEM(spi0_pins_base),
PINMUX_ITEM(spi0_pins_scs0),
diff --git a/board/lg/sniper/sniper.c b/board/lg/sniper/sniper.c
index a7de4c2..b4205d6 100644
--- a/board/lg/sniper/sniper.c
+++ b/board/lg/sniper/sniper.c
@@ -8,6 +8,7 @@
#include <config.h>
#include <common.h>
#include <dm.h>
+#include <env.h>
#include <linux/ctype.h>
#include <linux/usb/musb.h>
#include <asm/omap_musb.h>
diff --git a/board/liebherr/display5/common.c b/board/liebherr/display5/common.c
index 4eb86d8..8390d9a 100644
--- a/board/liebherr/display5/common.c
+++ b/board/liebherr/display5/common.c
@@ -68,7 +68,7 @@
int board_spi_cs_gpio(unsigned int bus, unsigned int cs)
{
- if (bus != 1 || cs != (IMX_GPIO_NR(5, 29) << 8))
+ if (bus != 1 || cs != 0)
return -EINVAL;
return IMX_GPIO_NR(5, 29);
@@ -89,7 +89,7 @@
void displ5_set_iomux_ecspi(void) {}
#endif
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
iomux_v3_cfg_t const usdhc4_pads[] = {
MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
diff --git a/board/liebherr/display5/display5.c b/board/liebherr/display5/display5.c
index d838317..037c4e6 100644
--- a/board/liebherr/display5/display5.c
+++ b/board/liebherr/display5/display5.c
@@ -13,6 +13,7 @@
#include <asm/arch/mx6-pins.h>
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/sys_proto.h>
+#include <env.h>
#include <errno.h>
#include <asm/gpio.h>
#include <malloc.h>
@@ -21,11 +22,10 @@
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/spi.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <i2c.h>
-#include <environment.h>
#include <dm.h>
#include <dm/platform_data/serial_mxc.h>
@@ -186,7 +186,7 @@
MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg usdhc_cfg[1] = {
{ USDHC4_BASE_ADDR, 0, 8, },
};
@@ -204,7 +204,7 @@
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
}
-#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_FSL_ESDHC_IMX */
static void displ5_setup_ecspi(void)
{
@@ -413,12 +413,3 @@
return 0;
}
-
-static struct mxc_serial_platdata mxc_serial_plat = {
- .reg = (struct mxc_uart *)UART5_BASE,
-};
-
-U_BOOT_DEVICE(mxc_serial) = {
- .name = "serial_mxc",
- .platdata = &mxc_serial_plat,
-};
diff --git a/board/liebherr/display5/spl.c b/board/liebherr/display5/spl.c
index 0c0172e..354b63e 100644
--- a/board/liebherr/display5/spl.c
+++ b/board/liebherr/display5/spl.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
+#include <env.h>
#include <spl.h>
#include <linux/libfdt.h>
#include <asm/io.h>
@@ -17,8 +18,7 @@
#include "asm/arch/iomux.h"
#include <asm/mach-imx/iomux-v3.h>
#include <asm/gpio.h>
-#include <environment.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <netdev.h>
#include <bootcount.h>
#include <watchdog.h>
diff --git a/board/liebherr/mccmon6/mccmon6.c b/board/liebherr/mccmon6/mccmon6.c
index 946b91f..7d2751a 100644
--- a/board/liebherr/mccmon6/mccmon6.c
+++ b/board/liebherr/mccmon6/mccmon6.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
+#include <env.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux.h>
#include <asm/arch/imx-regs.h>
@@ -16,7 +17,7 @@
#include <asm/mach-imx/spi.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/io.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <mmc.h>
#include <netdev.h>
#include <micrel.h>
diff --git a/board/liebherr/mccmon6/spl.c b/board/liebherr/mccmon6/spl.c
index acfc490..f0ed78c 100644
--- a/board/liebherr/mccmon6/spl.c
+++ b/board/liebherr/mccmon6/spl.c
@@ -14,7 +14,7 @@
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/video.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c
index 10031a4..95c4cfc 100644
--- a/board/logicpd/am3517evm/am3517evm.c
+++ b/board/logicpd/am3517evm/am3517evm.c
@@ -28,7 +28,6 @@
#include <linux/usb/gadget.h>
#include <linux/usb/musb.h>
#include <i2c.h>
-#include <netdev.h>
#include "am3517evm.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -114,47 +113,16 @@
*/
int misc_init_r(void)
{
- volatile unsigned int ctr;
u32 reset;
-#if !defined(CONFIG_DM_I2C)
-#ifdef CONFIG_SYS_I2C_OMAP24XX
- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
-#endif
-#endif
omap_die_id_display();
am3517_evm_musb_init();
- if (gpio_request(PHY_GPIO, "gpio_30") == 0) {
- /* activate PHY reset */
- gpio_direction_output(PHY_GPIO, 0);
- gpio_set_value(PHY_GPIO, 0);
-
- ctr = 0;
- do {
- udelay(1000);
- ctr++;
- } while (ctr < 300);
-
- /* deactivate PHY reset */
- gpio_set_value(PHY_GPIO, 1);
-
- /* allow the PHY to stabilize and settle down */
- ctr = 0;
- do {
- udelay(1000);
- ctr++;
- } while (ctr < 300);
-
- /* ensure that the module is out of reset */
- reset = readl(AM3517_IP_SW_RESET);
- reset &= (~CPGMACSS_SW_RST);
- writel(reset, AM3517_IP_SW_RESET);
-
- /* Free requested GPIO */
- gpio_free(PHY_GPIO);
- }
+ /* ensure that the Ethernet module is out of reset */
+ reset = readl(AM3517_IP_SW_RESET);
+ reset &= (~CPGMACSS_SW_RST);
+ writel(reset, AM3517_IP_SW_RESET);
return 0;
}
@@ -170,12 +138,6 @@
MUX_AM3517EVM();
}
-#if defined(CONFIG_MMC)
-int board_mmc_init(bd_t *bis)
-{
- return omap_mmc_init(0, 0, 0, -1, -1);
-}
-#endif
#if defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)
int board_eth_init(bd_t *bis)
diff --git a/board/logicpd/am3517evm/am3517evm.h b/board/logicpd/am3517evm/am3517evm.h
index 99a0803..0e5b832 100644
--- a/board/logicpd/am3517evm/am3517evm.h
+++ b/board/logicpd/am3517evm/am3517evm.h
@@ -111,7 +111,7 @@
MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | DIS | M4)) \
MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
@@ -339,18 +339,18 @@
MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) \
/* ETK (ES2 onwards) */\
- MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_STP*/\
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA0*/\
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA1*/\
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA2*/\
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA7*/\
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA4*/\
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA5*/\
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA6*/\
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA3*/\
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_NXT*/\
MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)) \
diff --git a/board/logicpd/imx6/MAINTAINERS b/board/logicpd/imx6/MAINTAINERS
index 20ec591..4280315 100644
--- a/board/logicpd/imx6/MAINTAINERS
+++ b/board/logicpd/imx6/MAINTAINERS
@@ -7,3 +7,4 @@
F: arch/arm/dts/imx6-logicpd-baseboard.dtsi
F: arch/arm/dts/imx6-logicpd-som.dtsi
F: arch/arm/dts/imx6q-logicpd.dts
+F: arch/arm/dts/imx6q-logicpd-u-boot.dtsi
diff --git a/board/logicpd/imx6/imx6logic.c b/board/logicpd/imx6/imx6logic.c
index 53e609e..7a59b89 100644
--- a/board/logicpd/imx6/imx6logic.c
+++ b/board/logicpd/imx6/imx6logic.c
@@ -9,10 +9,11 @@
*/
#include <common.h>
+#include <env.h>
#include <miiphy.h>
#include <input.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <linux/sizes.h>
@@ -200,7 +201,7 @@
MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg usdhc_cfg[] = {
{USDHC1_BASE_ADDR}, /* SOM */
{USDHC2_BASE_ADDR} /* Baseboard */
@@ -223,25 +224,15 @@
switch (reg) {
case 0:
SETUP_IOMUX_PADS(usdhc1_pads);
- usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
- gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
break;
case 1:
SETUP_IOMUX_PADS(usdhc2_pads);
- usdhc_cfg[1].esdhc_base = USDHC2_BASE_ADDR;
- usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
- gd->arch.sdhc_clk = usdhc_cfg[1].sdhc_clk;
break;
}
- return fsl_esdhc_initialize(bis, &usdhc_cfg[reg]);
+ return 0;
}
-int board_mmc_getcd(struct mmc *mmc)
-{
- return 1;
-}
#endif
static void ccgr_init(void)
diff --git a/board/logicpd/omap3som/omap3logic.h b/board/logicpd/omap3som/omap3logic.h
index aeb26b9..63c2141 100644
--- a/board/logicpd/omap3som/omap3logic.h
+++ b/board/logicpd/omap3som/omap3logic.h
@@ -161,12 +161,14 @@
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)); /*ETK_D7*/
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)); /*ETK_D8*/
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)); /*ETK_D9*/
+#ifndef CONFIG_USB_EHCI_OMAP /* Torpedo does not use EHCI_OMAP */
MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)); /*ETK_D10*/
MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)); /*ETK_D11*/
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)); /*ETK_D12*/
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)); /*ETK_D13*/
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)); /*ETK_D14*/
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)); /*ETK_D15*/
+#endif
MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)); /*d2d_mcad1*/
MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)); /*d2d_mcad2*/
@@ -231,6 +233,23 @@
MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)); /*d2d_sread*/
MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)); /*d2d_mbusflag*/
MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)); /*d2d_sbusflag*/
+
+#ifdef CONFIG_USB_EHCI_OMAP /* SOM-LV Uses EHCI-OMAP */
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M3)); /*HSUSB2_DATA0*/
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M3)); /*HSUSB2_DATA1*/
+ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)); /*HSUSB2_DATA2*/
+ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)); /*HSUSB2_DATA3*/
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)); /*HSUSB2_DATA4*/
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)); /*HSUSB2_DATA5*/
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)); /*HSUSB2_DATA6*/
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)); /*HSUSB2_DATA7*/
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */
+ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_CLK*/
+ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)); /*HSUSB2_DIR*/
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)); /*HSUSB2_NXT*/
+#endif
+
}
#endif
diff --git a/board/logicpd/zoom1/zoom1.c b/board/logicpd/zoom1/zoom1.c
index 5e32077..6bfa417 100644
--- a/board/logicpd/zoom1/zoom1.c
+++ b/board/logicpd/zoom1/zoom1.c
@@ -15,7 +15,7 @@
*/
#include <common.h>
#include <dm.h>
-#include <environment.h>
+#include <env.h>
#include <ns16550.h>
#include <netdev.h>
#include <twl4030.h>
diff --git a/board/mediatek/pumpkin/Kconfig b/board/mediatek/pumpkin/Kconfig
new file mode 100644
index 0000000..34b1c0b
--- /dev/null
+++ b/board/mediatek/pumpkin/Kconfig
@@ -0,0 +1,13 @@
+if TARGET_MT8516
+
+config SYS_BOARD
+ default "pumpkin"
+
+config SYS_CONFIG_NAME
+ default "pumpkin"
+
+config MTK_BROM_HEADER_INFO
+ string
+ default "media=emmc"
+
+endif
diff --git a/board/mediatek/pumpkin/MAINTAINERS b/board/mediatek/pumpkin/MAINTAINERS
new file mode 100644
index 0000000..16beadc
--- /dev/null
+++ b/board/mediatek/pumpkin/MAINTAINERS
@@ -0,0 +1,6 @@
+Pumpkin
+M: Fabien Parent <fparent@baylibre.com>
+S: Maintained
+F: board/mediatek/pumpkin
+F: include/configs/pumpkin.h
+F: configs/pumpkin_defconfig
diff --git a/board/mediatek/pumpkin/Makefile b/board/mediatek/pumpkin/Makefile
new file mode 100644
index 0000000..75fce4a
--- /dev/null
+++ b/board/mediatek/pumpkin/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += pumpkin.o
diff --git a/board/mediatek/pumpkin/pumpkin.c b/board/mediatek/pumpkin/pumpkin.c
new file mode 100644
index 0000000..666e4d6
--- /dev/null
+++ b/board/mediatek/pumpkin/pumpkin.c
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 BayLibre SAS
+ */
+
+#include <common.h>
+
+int board_init(void)
+{
+ return 0;
+}
diff --git a/board/menlo/m53menlo/m53menlo.c b/board/menlo/m53menlo/m53menlo.c
index 31ba44e..bda5f0d 100644
--- a/board/menlo/m53menlo/m53menlo.c
+++ b/board/menlo/m53menlo/m53menlo.c
@@ -18,8 +18,10 @@
#include <asm/mach-imx/video.h>
#include <asm/gpio.h>
#include <asm/spl.h>
+#include <env.h>
#include <fdt_support.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
+#include <gzip.h>
#include <i2c.h>
#include <ipu_pixfmt.h>
#include <linux/errno.h>
@@ -125,6 +127,43 @@
imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}
+#ifdef CONFIG_FSL_ESDHC_IMX
+struct fsl_esdhc_cfg esdhc_cfg = {
+ MMC_SDHC1_BASE_ADDR,
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
+ gpio_direction_input(IMX_GPIO_NR(1, 1));
+
+ return !gpio_get_value(IMX_GPIO_NR(1, 1));
+}
+
+#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP)
+#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_DSE_HIGH)
+
+int board_mmc_init(bd_t *bis)
+{
+ static const iomux_v3_cfg_t sd1_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
+ };
+
+ esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+ imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
+
+ return fsl_esdhc_initialize(bis, &esdhc_cfg);
+}
+#endif
+
static void enable_lvds_clock(struct display_info_t const *dev, const u8 hclk)
{
static struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
diff --git a/board/micronas/vct/vct.c b/board/micronas/vct/vct.c
index af3f11e..e73d16d 100644
--- a/board/micronas/vct/vct.c
+++ b/board/micronas/vct/vct.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <netdev.h>
#include <asm/mipsregs.h>
#include "vct.h"
diff --git a/board/mqmaker/miqi_rk3288/miqi-rk3288.c b/board/mqmaker/miqi_rk3288/miqi-rk3288.c
index d6992a2..779bc64 100644
--- a/board/mqmaker/miqi_rk3288/miqi-rk3288.c
+++ b/board/mqmaker/miqi_rk3288/miqi-rk3288.c
@@ -3,12 +3,3 @@
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
*/
-#include <common.h>
-#include <spl.h>
-
-void board_boot_order(u32 *spl_boot_list)
-{
- /* eMMC prior to sdcard. */
- spl_boot_list[0] = BOOT_DEVICE_MMC2;
- spl_boot_list[1] = BOOT_DEVICE_MMC1;
-}
diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c
index bcae8fa..91d0395 100644
--- a/board/mscc/ocelot/ocelot.c
+++ b/board/mscc/ocelot/ocelot.c
@@ -7,7 +7,6 @@
#include <asm/io.h>
#include <asm/addrspace.h>
#include <asm/types.h>
-#include <environment.h>
#include <spi.h>
#include <led.h>
#include <wait_bit.h>
diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c
index 76f6ede..71ca79d 100644
--- a/board/nokia/rx51/rx51.c
+++ b/board/nokia/rx51/rx51.c
@@ -22,6 +22,7 @@
*/
#include <common.h>
+#include <env.h>
#include <watchdog.h>
#include <malloc.h>
#include <twl4030.h>
diff --git a/board/nvidia/p2371-2180/p2371-2180.c b/board/nvidia/p2371-2180/p2371-2180.c
index 4985302..fa5288b 100644
--- a/board/nvidia/p2371-2180/p2371-2180.c
+++ b/board/nvidia/p2371-2180/p2371-2180.c
@@ -5,7 +5,7 @@
*/
#include <common.h>
-#include <environment.h>
+#include <env.h>
#include <fdtdec.h>
#include <i2c.h>
#include <linux/libfdt.h>
diff --git a/board/nvidia/p2771-0000/p2771-0000.c b/board/nvidia/p2771-0000/p2771-0000.c
index d294c7a..63cdb3a 100644
--- a/board/nvidia/p2771-0000/p2771-0000.c
+++ b/board/nvidia/p2771-0000/p2771-0000.c
@@ -4,7 +4,7 @@
*/
#include <common.h>
-#include <environment.h>
+#include <env.h>
#include <fdtdec.h>
#include <i2c.h>
#include <linux/libfdt.h>
diff --git a/board/overo/common.c b/board/overo/common.c
index fc02d66..2c4f412 100644
--- a/board/overo/common.c
+++ b/board/overo/common.c
@@ -17,6 +17,7 @@
#include <asm/arch/mux.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
+#include <asm/omap_mmc.h>
#include <asm/mach-types.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -38,6 +39,31 @@
return 0;
}
+#if defined(CONFIG_MMC)
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(0, 0, 0, -1, -1);
+}
+#endif
+
+#if defined(CONFIG_MMC)
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
+
+#if defined(CONFIG_SPL_OS_BOOT)
+int spl_start_uboot(void)
+{
+ /* break into full u-boot on 'c' */
+ if (serial_tstc() && serial_getc() == 'c')
+ return 1;
+
+ return 0;
+}
+#endif /* CONFIG_SPL_OS_BOOT */
+
#define MUX_OVERO() \
/*SDRC*/\
MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
diff --git a/board/overo/overo.c b/board/overo/overo.c
index 8fa41f8..442028a 100644
--- a/board/overo/overo.c
+++ b/board/overo/overo.c
@@ -13,6 +13,7 @@
*/
#include <common.h>
#include <dm.h>
+#include <env.h>
#include <ns16550.h>
#include <netdev.h>
#include <twl4030.h>
@@ -376,20 +377,6 @@
}
#endif
-#if defined(CONFIG_MMC)
-int board_mmc_init(bd_t *bis)
-{
- return omap_mmc_init(0, 0, 0, -1, -1);
-}
-#endif
-
-#if defined(CONFIG_MMC)
-void board_mmc_power_init(void)
-{
- twl4030_power_mmc_init(0);
-}
-#endif
-
#if defined(CONFIG_USB_EHCI_HCD)
static struct omap_usbhs_board_data usbhs_bdata = {
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
diff --git a/board/phytec/pcl063/pcl063.c b/board/phytec/pcl063/pcl063.c
index 17012df..f8cbd1c 100644
--- a/board/phytec/pcl063/pcl063.c
+++ b/board/phytec/pcl063/pcl063.c
@@ -12,7 +12,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <linux/bitops.h>
#include <miiphy.h>
#include <netdev.h>
diff --git a/board/phytec/pcl063/spl.c b/board/phytec/pcl063/spl.c
index 73a7746..6d4c827 100644
--- a/board/phytec/pcl063/spl.c
+++ b/board/phytec/pcl063/spl.c
@@ -14,7 +14,7 @@
#include <asm/arch/mx6-pins.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/sys_proto.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
/* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x 16 x 8 -> 256MiB */
@@ -101,7 +101,7 @@
mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
@@ -205,7 +205,7 @@
spl_boot_list[0] = boot_dev;
}
-#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_FSL_ESDHC_IMX */
void board_init_f(ulong dummy)
{
diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c
index e720fdc..43f6c5a 100644
--- a/board/phytec/pcm051/board.c
+++ b/board/phytec/pcm051/board.c
@@ -9,7 +9,7 @@
*/
#include <common.h>
-#include <environment.h>
+#include <env.h>
#include <errno.h>
#include <spl.h>
#include <asm/arch/cpu.h>
diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c
index c30df5d..e1ebe8e 100644
--- a/board/phytec/pcm052/pcm052.c
+++ b/board/phytec/pcm052/pcm052.c
@@ -13,8 +13,8 @@
#include <asm/arch/ddrmc-vf610.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
+#include <env.h>
#include <led.h>
-#include <environment.h>
#include <miiphy.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -376,7 +376,7 @@
if ((reg & SRC_SBMR1_BOOTCFG1_SDMMC) &&
!(reg & SRC_SBMR1_BOOTCFG1_MMC)) {
printf("------ SD card boot -------\n");
- set_default_env("!LVFBootloader", 0);
+ env_set_default("!LVFBootloader", 0);
env_set("bootcmd",
"run prepare_install_bk4r1_envs; run install_bk4r1rs");
}
diff --git a/board/phytec/pcm058/pcm058.c b/board/phytec/pcm058/pcm058.c
index 5ecaf00..ac5e3a2 100644
--- a/board/phytec/pcm058/pcm058.c
+++ b/board/phytec/pcm058/pcm058.c
@@ -25,7 +25,7 @@
#include <asm/gpio.h>
#include <mmc.h>
#include <i2c.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <nand.h>
#include <miiphy.h>
#include <netdev.h>
diff --git a/board/phytec/pfla02/pfla02.c b/board/phytec/pfla02/pfla02.c
index aae23a3..ae9ffe0 100644
--- a/board/phytec/pfla02/pfla02.c
+++ b/board/phytec/pfla02/pfla02.c
@@ -15,11 +15,12 @@
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/spi.h>
+#include <env.h>
#include <linux/errno.h>
#include <asm/gpio.h>
#include <mmc.h>
#include <i2c.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <nand.h>
#include <miiphy.h>
#include <netdev.h>
diff --git a/board/phytec/phycore_am335x_r2/Kconfig b/board/phytec/phycore_am335x_r2/Kconfig
new file mode 100644
index 0000000..77055e0
--- /dev/null
+++ b/board/phytec/phycore_am335x_r2/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_PHYCORE_AM335X_R2
+
+config SYS_BOARD
+ default "phycore_am335x_r2"
+
+config SYS_VENDOR
+ default "phytec"
+
+config SYS_SOC
+ default "am33xx"
+
+config SYS_CONFIG_NAME
+ default "phycore_am335x_r2"
+
+endif
diff --git a/board/phytec/phycore_am335x_r2/MAINTAINERS b/board/phytec/phycore_am335x_r2/MAINTAINERS
new file mode 100644
index 0000000..e56f30f
--- /dev/null
+++ b/board/phytec/phycore_am335x_r2/MAINTAINERS
@@ -0,0 +1,7 @@
+phyCORE AM335x R2 WEGA BOARD
+M: Niel Fourie <lusus@denx.de>
+M: Parthiban Nallathambi <pn@denx.de>
+S: Maintained
+F: board/phytec/phycore_am335x_r2
+F: include/configs/phycore_am335x_r2.h
+F: configs/phycore-am335x-r2-wega_defconfig
diff --git a/board/phytec/phycore_am335x_r2/Makefile b/board/phytec/phycore_am335x_r2/Makefile
new file mode 100644
index 0000000..ff6f8b4
--- /dev/null
+++ b/board/phytec/phycore_am335x_r2/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+
+ifdef CONFIG_SPL_BUILD
+obj-y += mux.o
+endif
+
+obj-y += board.o
diff --git a/board/phytec/phycore_am335x_r2/board.c b/board/phytec/phycore_am335x_r2/board.c
new file mode 100644
index 0000000..02d6c27
--- /dev/null
+++ b/board/phytec/phycore_am335x_r2/board.c
@@ -0,0 +1,260 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * board.c
+ *
+ * Board functions for Phytec phyCORE-AM335x R2 (PCL060 / PCM060) based boards
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH
+ * Copyright (C) 2015 Wadim Egorov, PHYTEC Messtechnik GmbH
+ * Copyright (C) 2019 DENX Software Engineering GmbH
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <power/tps65910.h>
+#include <jffs2/load_kernel.h>
+#include <mtd_node.h>
+#include <fdt_support.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SPL_BUILD
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+/* DDR RAM defines */
+#define DDR_CLK_MHZ 400 /* DDR_DPLL_MULT value */
+
+#define OSC (V_OSCK / 1000000)
+const struct dpll_params dpll_ddr = {
+ DDR_CLK_MHZ, OSC - 1, 1, -1, -1, -1, -1};
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+ return &dpll_ddr;
+}
+
+const struct ctrl_ioregs ioregs = {
+ .cm0ioctl = 0x18B,
+ .cm1ioctl = 0x18B,
+ .cm2ioctl = 0x18B,
+ .dt0ioctl = 0x18B,
+ .dt1ioctl = 0x18B,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+ .cmd0csratio = 0x80,
+ .cmd0iclkout = 0x0,
+
+ .cmd1csratio = 0x80,
+ .cmd1iclkout = 0x0,
+
+ .cmd2csratio = 0x80,
+ .cmd2iclkout = 0x0,
+};
+
+enum {
+ PHYCORE_R2_MT41K128M16JT_256MB,
+ PHYCORE_R2_MT41K256M16TW107IT_512MB,
+ PHYCORE_R2_MT41K512M16HA125IT_1024MB,
+};
+
+struct am335x_sdram_timings {
+ struct emif_regs ddr3_emif_reg_data;
+ struct ddr_data ddr3_data;
+};
+
+static struct am335x_sdram_timings physom_timings[] = {
+ [PHYCORE_R2_MT41K128M16JT_256MB] = {
+ .ddr3_emif_reg_data = {
+ .sdram_config = 0x61C052B2,
+ .ref_ctrl = 0x00000C30,
+ .sdram_tim1 = 0x0AAAD4DB,
+ .sdram_tim2 = 0x26437FDA,
+ .sdram_tim3 = 0x501F83FF,
+ .zq_config = 0x50074BE4,
+ .emif_ddr_phy_ctlr_1 = 0x7,
+ .ocp_config = 0x003d3d3d,
+ },
+ .ddr3_data = {
+ .datardsratio0 = 0x36,
+ .datawdsratio0 = 0x38,
+ .datafwsratio0 = 0x99,
+ .datawrsratio0 = 0x73,
+ },
+ },
+ [PHYCORE_R2_MT41K256M16TW107IT_512MB] = {
+ .ddr3_emif_reg_data = {
+ .sdram_config = 0x61C05332,
+ .ref_ctrl = 0x00000C30,
+ .sdram_tim1 = 0x0AAAD4DB,
+ .sdram_tim2 = 0x266B7FDA,
+ .sdram_tim3 = 0x501F867F,
+ .zq_config = 0x50074BE4,
+ .emif_ddr_phy_ctlr_1 = 0x7,
+ .ocp_config = 0x003d3d3d,
+ },
+ .ddr3_data = {
+ .datardsratio0 = 0x37,
+ .datawdsratio0 = 0x38,
+ .datafwsratio0 = 0x92,
+ .datawrsratio0 = 0x72,
+ },
+ },
+ [PHYCORE_R2_MT41K512M16HA125IT_1024MB] = {
+ .ddr3_emif_reg_data = {
+ .sdram_config = 0x61C053B2,
+ .ref_ctrl = 0x00000C30,
+ .sdram_tim1 = 0x0AAAD4DB,
+ .sdram_tim2 = 0x268F7FDA,
+ .sdram_tim3 = 0x501F88BF,
+ .zq_config = 0x50074BE4,
+ .emif_ddr_phy_ctlr_1 = 0x7,
+ .ocp_config = 0x003d3d3d,
+ },
+ .ddr3_data = {
+ .datardsratio0 = 0x38,
+ .datawdsratio0 = 0x4d,
+ .datafwsratio0 = 0x9d,
+ .datawrsratio0 = 0x82,
+ },
+ },
+};
+
+void sdram_init(void)
+{
+ /* Configure memory to maximum supported size for detection */
+ int ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
+
+ config_ddr(DDR_CLK_MHZ, &ioregs,
+ &physom_timings[ram_type_index].ddr3_data,
+ &ddr3_cmd_ctrl_data,
+ &physom_timings[ram_type_index].ddr3_emif_reg_data,
+ 0);
+
+ /* Detect memory physically present */
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_MAX_RAM_BANK_SIZE);
+
+ /* Reconfigure memory for actual detected size */
+ switch (gd->ram_size) {
+ case SZ_1G:
+ ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
+ break;
+ case SZ_512M:
+ ram_type_index = PHYCORE_R2_MT41K256M16TW107IT_512MB;
+ break;
+ case SZ_256M:
+ default:
+ ram_type_index = PHYCORE_R2_MT41K128M16JT_256MB;
+ break;
+ }
+ config_ddr(DDR_CLK_MHZ, &ioregs,
+ &physom_timings[ram_type_index].ddr3_data,
+ &ddr3_cmd_ctrl_data,
+ &physom_timings[ram_type_index].ddr3_emif_reg_data,
+ 0);
+}
+
+const struct dpll_params *get_dpll_mpu_params(void)
+{
+ int ind = get_sys_clk_index();
+ int freq = am335x_get_efuse_mpu_max_freq(cdev);
+
+ switch (freq) {
+ case MPUPLL_M_1000:
+ return &dpll_mpu_opp[ind][5];
+ case MPUPLL_M_800:
+ return &dpll_mpu_opp[ind][4];
+ case MPUPLL_M_720:
+ return &dpll_mpu_opp[ind][3];
+ case MPUPLL_M_600:
+ return &dpll_mpu_opp[ind][2];
+ case MPUPLL_M_500:
+ return &dpll_mpu_opp100;
+ case MPUPLL_M_300:
+ return &dpll_mpu_opp[ind][0];
+ }
+
+ return &dpll_mpu_opp[ind][0];
+}
+
+static void scale_vcores_generic(int freq)
+{
+ int sil_rev, mpu_vdd;
+
+ /*
+ * We use a TPS65910 PMIC. For all MPU frequencies we support we use a
+ * CORE voltage of 1.10V. For MPU voltage we need to switch based on
+ * the frequency we are running at.
+ */
+ if (power_tps65910_init(0))
+ return;
+
+ /*
+ * Depending on MPU clock and PG we will need a different
+ * VDD to drive at that speed.
+ */
+ sil_rev = readl(&cdev->deviceid) >> 28;
+ mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);
+
+ /* Tell the TPS65910 to use i2c */
+ tps65910_set_i2c_control();
+
+ /* First update MPU voltage. */
+ if (tps65910_voltage_update(MPU, mpu_vdd))
+ return;
+
+ /* Second, update the CORE voltage. */
+ if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0))
+ return;
+}
+
+void scale_vcores(void)
+{
+ int freq;
+
+ freq = am335x_get_efuse_mpu_max_freq(cdev);
+ scale_vcores_generic(freq);
+}
+
+void set_uart_mux_conf(void)
+{
+ enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+ enable_i2c0_pin_mux();
+ enable_board_pin_mux();
+}
+#endif
+
+/*
+ * Basic board specific setup. Pinmux has been handled already.
+ */
+int board_init(void)
+{
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+ static const struct node_info nodes[] = {
+ { "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
+ };
+
+ fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+#endif
+ return 0;
+}
+#endif
diff --git a/board/phytec/phycore_am335x_r2/board.h b/board/phytec/phycore_am335x_r2/board.h
new file mode 100644
index 0000000..1b90861
--- /dev/null
+++ b/board/phytec/phycore_am335x_r2/board.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * board.h
+ *
+ * Phytec phyCORE-AM335x (PCL060 / PCM060) boards information header
+ *
+ * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH
+ * Copyright (C) 2019 DENX Software Engineering GmbH
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * We have three pin mux functions that must exist. We must be able to enable
+ * uart0, for initial output and i2c0 to access the PMIC. We then have a main
+ * pinmux function that can be overridden to enable all other pinmux that
+ * is required on the board.
+ */
+void enable_uart0_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_board_pin_mux(void);
+void enable_cbmux_pin_mux(void);
+#endif
diff --git a/board/phytec/phycore_am335x_r2/mux.c b/board/phytec/phycore_am335x_r2/mux.c
new file mode 100644
index 0000000..5fd452e
--- /dev/null
+++ b/board/phytec/phycore_am335x_r2/mux.c
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * mux.c
+ *
+ * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH
+ * Copyright (C) 2019 DENX Software Engineering GmbH
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
+ {-1},
+};
+
+#ifdef CONFIG_MMC
+static struct module_pin_mux mmc0_pin_mux[] = {
+ {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
+ {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
+ {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
+ {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
+ {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
+ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
+ {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
+ {-1},
+};
+#endif
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+ {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
+ {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
+ {-1},
+};
+
+#ifdef CONFIG_SPI
+static struct module_pin_mux spi0_pin_mux[] = {
+ {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */
+ {OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
+ PULLUDEN | PULLUP_EN)}, /* SPI0_D0 */
+ {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */
+ {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
+ PULLUDEN | PULLUP_EN)}, /* SPI0_CS0 */
+ {-1},
+};
+#endif
+
+static struct module_pin_mux rmii1_pin_mux[] = {
+ {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS */
+ {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
+ {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
+ {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
+ {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */
+ {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
+ {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */
+ {-1},
+};
+
+static struct module_pin_mux cbmux_pin_mux[] = {
+ {OFFSET(uart0_ctsn), MODE(7) | RXACTIVE | PULLDOWN_EN}, /* JP3 */
+ {OFFSET(uart0_rtsn), MODE(7) | RXACTIVE | PULLUP_EN}, /* JP4 */
+ {-1},
+};
+
+#ifdef CONFIG_NAND
+static struct module_pin_mux nand_pin_mux[] = {
+ {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
+ {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
+ {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
+ {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
+ {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
+ {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
+ {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
+ {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
+ {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+ {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
+ {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
+ {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
+ {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
+ {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
+ {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
+ {-1},
+};
+#endif
+
+void enable_uart0_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+ configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+ configure_module_pin_mux(rmii1_pin_mux);
+ configure_module_pin_mux(mmc0_pin_mux);
+ configure_module_pin_mux(cbmux_pin_mux);
+#ifdef CONFIG_NAND
+ configure_module_pin_mux(nand_pin_mux);
+#endif
+#ifdef CONFIG_SPI
+ configure_module_pin_mux(spi0_pin_mux);
+#endif
+}
diff --git a/board/phytec/phycore_rk3288/phycore-rk3288.c b/board/phytec/phycore_rk3288/phycore-rk3288.c
index ffe1833..5fcbf65 100644
--- a/board/phytec/phycore_rk3288/phycore-rk3288.c
+++ b/board/phytec/phycore_rk3288/phycore-rk3288.c
@@ -7,11 +7,14 @@
#include <asm/io.h>
#include <common.h>
#include <dm.h>
-#include <environment.h>
+#include <env.h>
+#include <env_internal.h>
#include <i2c.h>
#include <i2c_eeprom.h>
#include <netdev.h>
#include "som.h"
+#include <power/regulator.h>
+#include <power/rk8xx_pmic.h>
static int valid_rk3288_som(struct rk3288_som *som)
{
@@ -27,7 +30,7 @@
return hw == som->bs;
}
-int rk_board_late_init(void)
+int rk3288_board_late_init(void)
{
int ret;
struct udevice *dev;
@@ -68,3 +71,47 @@
return 0;
}
+
+#ifdef CONFIG_SPL_BUILD
+#if !defined(CONFIG_SPL_OF_PLATDATA)
+static int phycore_init(void)
+{
+ struct udevice *pmic;
+ int ret;
+
+ ret = uclass_first_device_err(UCLASS_PMIC, &pmic);
+ if (ret)
+ return ret;
+
+#if defined(CONFIG_SPL_POWER_SUPPORT)
+ /* Increase USB input current to 2A */
+ ret = rk818_spl_configure_usb_input_current(pmic, 2000);
+ if (ret)
+ return ret;
+
+ /* Close charger when USB lower then 3.26V */
+ ret = rk818_spl_configure_usb_chrg_shutdown(pmic, 3260000);
+ if (ret)
+ return ret;
+#endif
+
+ return 0;
+}
+#endif
+
+void spl_board_init(void)
+{
+#if !defined(CONFIG_SPL_OF_PLATDATA)
+ int ret;
+
+ if (of_machine_is_compatible("phytec,rk3288-phycore-som")) {
+ ret = phycore_init();
+ if (ret) {
+ debug("Failed to set up phycore power settings: %d\n",
+ ret);
+ return;
+ }
+ }
+#endif
+}
+#endif
diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c b/board/qualcomm/dragonboard410c/dragonboard410c.c
index 9ceed3a..d7f0f93 100644
--- a/board/qualcomm/dragonboard410c/dragonboard410c.c
+++ b/board/qualcomm/dragonboard410c/dragonboard410c.c
@@ -7,10 +7,10 @@
#include <common.h>
#include <dm.h>
+#include <env.h>
#include <usb.h>
#include <asm/gpio.h>
#include <fdt_support.h>
-#include <environment.h>
#include <asm/arch/dram.h>
#include <asm/arch/misc.h>
diff --git a/board/qualcomm/dragonboard820c/dragonboard820c.c b/board/qualcomm/dragonboard820c/dragonboard820c.c
index ff69035..7a88964 100644
--- a/board/qualcomm/dragonboard820c/dragonboard820c.c
+++ b/board/qualcomm/dragonboard820c/dragonboard820c.c
@@ -6,6 +6,7 @@
*/
#include <asm/arch/sysmap-apq8096.h>
+#include <env.h>
#include <linux/arm-smccc.h>
#include <linux/psci.h>
#include <common.h>
diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
index 617c892..9e0abdd 100644
--- a/board/raspberrypi/rpi/rpi.c
+++ b/board/raspberrypi/rpi/rpi.c
@@ -6,7 +6,7 @@
#include <common.h>
#include <config.h>
#include <dm.h>
-#include <environment.h>
+#include <env.h>
#include <efi_loader.h>
#include <fdt_support.h>
#include <fdt_simplefb.h>
@@ -148,6 +148,11 @@
DTB_DIR "bcm2837-rpi-cm3.dtb",
false,
},
+ [0x11] = {
+ "4 Model B",
+ DTB_DIR "bcm2711-rpi-4-b.dtb",
+ true,
+ },
};
static const struct rpi_model rpi_models_old_scheme[] = {
@@ -244,7 +249,8 @@
static const struct rpi_model *model;
#ifdef CONFIG_ARM64
-static struct mm_region bcm2837_mem_map[] = {
+#ifndef CONFIG_BCM2711
+static struct mm_region bcm283x_mem_map[] = {
{
.virt = 0x00000000UL,
.phys = 0x00000000UL,
@@ -263,8 +269,28 @@
0,
}
};
-
-struct mm_region *mem_map = bcm2837_mem_map;
+#else
+static struct mm_region bcm283x_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0xfe000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xfe000000UL,
+ .phys = 0xfe000000UL,
+ .size = 0x01800000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+#endif
+struct mm_region *mem_map = bcm283x_mem_map;
#endif
int dram_init(void)
@@ -286,6 +312,16 @@
return 0;
}
+#ifdef CONFIG_OF_BOARD
+#ifdef CONFIG_BCM2711
+int dram_init_banksize(void)
+{
+ return fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,
+ (phys_size_t *)&gd->ram_size, gd->bd);
+}
+#endif
+#endif
+
static void set_fdtfile(void)
{
const char *fdtfile;
diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c
index 0726776..10ef7f9 100644
--- a/board/renesas/alt/alt.c
+++ b/board/renesas/alt/alt.c
@@ -6,10 +6,11 @@
*/
#include <common.h>
+#include <env.h>
#include <malloc.h>
#include <dm.h>
#include <dm/platform_data/serial_sh.h>
-#include <environment.h>
+#include <env_internal.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
diff --git a/board/renesas/blanche/blanche.c b/board/renesas/blanche/blanche.c
index f5ada6e..08c5448 100644
--- a/board/renesas/blanche/blanche.c
+++ b/board/renesas/blanche/blanche.c
@@ -18,7 +18,7 @@
#include <asm/processor.h>
#include <dm.h>
#include <dm/platform_data/serial_sh.h>
-#include <environment.h>
+#include <env.h>
#include <i2c.h>
#include <linux/errno.h>
#include <malloc.h>
diff --git a/board/renesas/condor/Kconfig b/board/renesas/condor/Kconfig
new file mode 100644
index 0000000..2286d88
--- /dev/null
+++ b/board/renesas/condor/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_CONDOR
+
+config SYS_SOC
+ default "rmobile"
+
+config SYS_BOARD
+ default "condor"
+
+config SYS_VENDOR
+ default "renesas"
+
+config SYS_CONFIG_NAME
+ default "condor"
+
+endif
diff --git a/board/renesas/condor/MAINTAINERS b/board/renesas/condor/MAINTAINERS
new file mode 100644
index 0000000..73b010b
--- /dev/null
+++ b/board/renesas/condor/MAINTAINERS
@@ -0,0 +1,6 @@
+CONDOR BOARD
+M: Marek Vasut <marek.vasut+renesas@gmail.com>
+S: Maintained
+F: board/renesas/condor/
+F: include/configs/condor.h
+F: configs/r8a77980_condor_defconfig
diff --git a/board/renesas/condor/Makefile b/board/renesas/condor/Makefile
new file mode 100644
index 0000000..cf6d566
--- /dev/null
+++ b/board/renesas/condor/Makefile
@@ -0,0 +1,13 @@
+#
+# board/renesas/condor/Makefile
+#
+# Copyright (C) 2019 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y := ../rcar-common/gen3-spl.o
+else
+obj-y := condor.o ../rcar-common/common.o
+endif
diff --git a/board/renesas/condor/condor.c b/board/renesas/condor/condor.c
new file mode 100644
index 0000000..d1cbbc3
--- /dev/null
+++ b/board/renesas/condor/condor.c
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * board/renesas/condor/condor.c
+ * This file is Condor board support.
+ *
+ * Copyright (C) 2019 Marek Vasut <marek.vasut+renesas@gmail.com>
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void s_init(void)
+{
+}
+
+int board_early_init_f(void)
+{
+ return 0;
+}
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
+
+ return 0;
+}
+
+#define RST_BASE 0xE6160000
+#define RST_CA57RESCNT (RST_BASE + 0x40)
+#define RST_CA53RESCNT (RST_BASE + 0x44)
+#define RST_RSTOUTCR (RST_BASE + 0x58)
+#define RST_CA57_CODE 0xA5A5000F
+#define RST_CA53_CODE 0x5A5A000F
+
+void reset_cpu(ulong addr)
+{
+ unsigned long midr, cputype;
+
+ asm volatile("mrs %0, midr_el1" : "=r" (midr));
+ cputype = (midr >> 4) & 0xfff;
+
+ if (cputype == 0xd03)
+ writel(RST_CA53_CODE, RST_CA53RESCNT);
+ else if (cputype == 0xd07)
+ writel(RST_CA57_CODE, RST_CA57RESCNT);
+ else
+ hang();
+}
diff --git a/board/renesas/gose/gose.c b/board/renesas/gose/gose.c
index 7c61008..f86c9f1 100644
--- a/board/renesas/gose/gose.c
+++ b/board/renesas/gose/gose.c
@@ -6,10 +6,11 @@
*/
#include <common.h>
+#include <env.h>
#include <malloc.h>
#include <dm.h>
#include <dm/platform_data/serial_sh.h>
-#include <environment.h>
+#include <env_internal.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c
index d07a7ca..841d337 100644
--- a/board/renesas/koelsch/koelsch.c
+++ b/board/renesas/koelsch/koelsch.c
@@ -7,10 +7,11 @@
*/
#include <common.h>
+#include <env.h>
#include <malloc.h>
#include <dm.h>
#include <dm/platform_data/serial_sh.h>
-#include <environment.h>
+#include <env_internal.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c
index f062bb0..3cb1a56 100644
--- a/board/renesas/lager/lager.c
+++ b/board/renesas/lager/lager.c
@@ -8,7 +8,8 @@
*/
#include <common.h>
-#include <environment.h>
+#include <env.h>
+#include <env_internal.h>
#include <malloc.h>
#include <netdev.h>
#include <dm.h>
diff --git a/board/renesas/porter/porter.c b/board/renesas/porter/porter.c
index 2e15a4c..86f79da 100644
--- a/board/renesas/porter/porter.c
+++ b/board/renesas/porter/porter.c
@@ -7,10 +7,11 @@
*/
#include <common.h>
+#include <env.h>
#include <malloc.h>
#include <dm.h>
#include <dm/platform_data/serial_sh.h>
-#include <environment.h>
+#include <env_internal.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
diff --git a/board/renesas/r2dplus/r2dplus.c b/board/renesas/r2dplus/r2dplus.c
index f077326..6eff987 100644
--- a/board/renesas/r2dplus/r2dplus.c
+++ b/board/renesas/r2dplus/r2dplus.c
@@ -9,7 +9,6 @@
#include <netdev.h>
#include <asm/processor.h>
#include <asm/io.h>
-#include <asm/pci.h>
int checkboard(void)
{
@@ -45,12 +44,6 @@
}
}
-static struct pci_controller hose;
-void pci_init_board(void)
-{
- pci_sh7751_init(&hose);
-}
-
int board_eth_init(bd_t *bis)
{
return pci_eth_init(bis);
diff --git a/board/renesas/rcar-common/common.c b/board/renesas/rcar-common/common.c
index 292867e..37f8a46 100644
--- a/board/renesas/rcar-common/common.c
+++ b/board/renesas/rcar-common/common.c
@@ -8,6 +8,8 @@
*/
#include <common.h>
+#include <dm.h>
+#include <dm/uclass-internal.h>
#include <asm/arch/rmobile.h>
#ifdef CONFIG_RCAR_GEN3
@@ -46,4 +48,51 @@
return 0;
}
+
+#if CONFIG_IS_ENABLED(OF_BOARD_SETUP) && CONFIG_IS_ENABLED(PCI)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ struct udevice *dev;
+ struct uclass *uc;
+ fdt_addr_t regs_addr;
+ int i, off, ret;
+
+ ret = uclass_get(UCLASS_PCI, &uc);
+ if (ret)
+ return ret;
+
+ uclass_foreach_dev(dev, uc) {
+ struct pci_controller hose = { 0 };
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ if (hose.region_count == MAX_PCI_REGIONS) {
+ printf("maximum number of regions parsed, aborting\n");
+ break;
+ }
+
+ if (bd->bi_dram[i].size) {
+ pci_set_region(&hose.regions[hose.region_count++],
+ bd->bi_dram[i].start,
+ bd->bi_dram[i].start,
+ bd->bi_dram[i].size,
+ PCI_REGION_MEM |
+ PCI_REGION_PREFETCH |
+ PCI_REGION_SYS_MEMORY);
+ }
+ }
+
+ regs_addr = devfdt_get_addr_index(dev, 0);
+ off = fdt_node_offset_by_compat_reg(blob,
+ "renesas,pcie-rcar-gen3", regs_addr);
+ if (off < 0) {
+ printf("Failed to find PCIe node@%llx\n", regs_addr);
+ return off;
+ }
+
+ fdt_pci_dma_ranges(blob, off, &hose);
+ }
+
+ return 0;
+}
+#endif
#endif
diff --git a/board/renesas/sh7752evb/sh7752evb.c b/board/renesas/sh7752evb/sh7752evb.c
index da33a0b..d0b850f 100644
--- a/board/renesas/sh7752evb/sh7752evb.c
+++ b/board/renesas/sh7752evb/sh7752evb.c
@@ -4,7 +4,7 @@
*/
#include <common.h>
-#include <environment.h>
+#include <env.h>
#include <malloc.h>
#include <asm/processor.h>
#include <asm/io.h>
diff --git a/board/renesas/sh7753evb/sh7753evb.c b/board/renesas/sh7753evb/sh7753evb.c
index 5ddddb6..e1bed7d 100644
--- a/board/renesas/sh7753evb/sh7753evb.c
+++ b/board/renesas/sh7753evb/sh7753evb.c
@@ -4,7 +4,7 @@
*/
#include <common.h>
-#include <environment.h>
+#include <env.h>
#include <malloc.h>
#include <asm/processor.h>
#include <asm/io.h>
diff --git a/board/renesas/sh7757lcr/sh7757lcr.c b/board/renesas/sh7757lcr/sh7757lcr.c
index 3222701..d267120 100644
--- a/board/renesas/sh7757lcr/sh7757lcr.c
+++ b/board/renesas/sh7757lcr/sh7757lcr.c
@@ -4,7 +4,7 @@
*/
#include <common.h>
-#include <environment.h>
+#include <env.h>
#include <malloc.h>
#include <asm/processor.h>
#include <asm/io.h>
diff --git a/board/renesas/silk/silk.c b/board/renesas/silk/silk.c
index 59ba262..25221e3 100644
--- a/board/renesas/silk/silk.c
+++ b/board/renesas/silk/silk.c
@@ -7,10 +7,11 @@
*/
#include <common.h>
+#include <env.h>
#include <malloc.h>
#include <dm.h>
#include <dm/platform_data/serial_sh.h>
-#include <environment.h>
+#include <env_internal.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
diff --git a/board/renesas/stout/stout.c b/board/renesas/stout/stout.c
index 7c51595..0a0ff5f 100644
--- a/board/renesas/stout/stout.c
+++ b/board/renesas/stout/stout.c
@@ -9,11 +9,12 @@
*/
#include <common.h>
+#include <env.h>
#include <malloc.h>
#include <netdev.h>
#include <dm.h>
#include <dm/platform_data/serial_sh.h>
-#include <environment.h>
+#include <env_internal.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
diff --git a/board/rockchip/evb_px5/evb-px5.c b/board/rockchip/evb_px5/evb-px5.c
index 53e753f..b81f970 100644
--- a/board/rockchip/evb_px5/evb-px5.c
+++ b/board/rockchip/evb_px5/evb-px5.c
@@ -2,9 +2,3 @@
/*
* Copyright (c) 2017 Andy Yan
*/
-#include <common.h>
-
-int board_init(void)
-{
- return 0;
-}
diff --git a/board/rockchip/evb_rk3288/evb-rk3288.c b/board/rockchip/evb_rk3288/evb-rk3288.c
index d6992a2..779bc64 100644
--- a/board/rockchip/evb_rk3288/evb-rk3288.c
+++ b/board/rockchip/evb_rk3288/evb-rk3288.c
@@ -3,12 +3,3 @@
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
*/
-#include <common.h>
-#include <spl.h>
-
-void board_boot_order(u32 *spl_boot_list)
-{
- /* eMMC prior to sdcard. */
- spl_boot_list[0] = BOOT_DEVICE_MMC2;
- spl_boot_list[1] = BOOT_DEVICE_MMC1;
-}
diff --git a/board/rockchip/evb_rk3328/evb-rk3328.c b/board/rockchip/evb_rk3328/evb-rk3328.c
index bc9ef5e..779bc64 100644
--- a/board/rockchip/evb_rk3328/evb-rk3328.c
+++ b/board/rockchip/evb_rk3328/evb-rk3328.c
@@ -3,68 +3,3 @@
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
*/
-#include <common.h>
-#include <asm/armv8/mmu.h>
-#include <dwc3-uboot.h>
-#include <power/regulator.h>
-#include <usb.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
- int ret;
-
- ret = regulators_enable_boot_on(false);
- if (ret)
- debug("%s: Cannot enable boot on regulator\n", __func__);
-
- return ret;
-}
-
-#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
-#include <usb.h>
-#include <usb/dwc2_udc.h>
-
-static struct dwc2_plat_otg_data rk3328_otg_data = {
- .rx_fifo_sz = 512,
- .np_tx_fifo_sz = 16,
- .tx_fifo_sz = 128,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
- int node;
- const char *mode;
- bool matched = false;
- const void *blob = gd->fdt_blob;
-
- /* find the usb_otg node */
- node = fdt_node_offset_by_compatible(blob, -1,
- "rockchip,rk3328-usb");
-
- while (node > 0) {
- mode = fdt_getprop(blob, node, "dr_mode", NULL);
- if (mode && strcmp(mode, "otg") == 0) {
- matched = true;
- break;
- }
-
- node = fdt_node_offset_by_compatible(blob, node,
- "rockchip,rk3328-usb");
- }
- if (!matched) {
- debug("Not found usb_otg device\n");
- return -ENODEV;
- }
-
- rk3328_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
-
- return dwc2_udc_probe(&rk3328_otg_data);
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
- return 0;
-}
-#endif
diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS
index 3308b35..f8299d9 100644
--- a/board/rockchip/evb_rk3399/MAINTAINERS
+++ b/board/rockchip/evb_rk3399/MAINTAINERS
@@ -6,6 +6,24 @@
F: configs/evb-rk3399_defconfig
F: configs/firefly-rk3399_defconfig
+KHADAS-EDGE
+M: Nick Xie <nick@khadas.com>
+S: Maintained
+F: configs/khadas-edge-rk3399_defconfig
+F: arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi
+
+KHADAS-EDGE-CAPTAIN
+M: Nick Xie <nick@khadas.com>
+S: Maintained
+F: configs/khadas-edge-captain-rk3399_defconfig
+F: arch/arm/dts/rk3399-khadas-edge-captain-u-boot.dtsi
+
+KHADAS-EDGE-V
+M: Nick Xie <nick@khadas.com>
+S: Maintained
+F: configs/khadas-edge-v-rk3399_defconfig
+F: arch/arm/dts/rk3399-khadas-edge-v-u-boot.dtsi
+
NANOPC-T4
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
@@ -31,6 +49,12 @@
F: arch/arm/dts/rk3399-u-boot.dtsi
F: arch/arm/dts/rk3399-orangepi-u-boot.dtsi
+ROC-RK3399-PC
+M: Levin Du <djw@t-chip.com.cn>
+S: Maintained
+F: configs/roc-rk3399-pc_defconfig
+F: arch/arm/dts/rk3399-roc-pc-u-boot.dtsi
+
ROCK-PI-4
M: Akash Gajjar <akash@openedev.com>
M: Jagan Teki <jagan@amarulasolutions.com>
diff --git a/board/rockchip/evb_rk3399/README b/board/rockchip/evb_rk3399/README
index 6469821..ea3258c 100644
--- a/board/rockchip/evb_rk3399/README
+++ b/board/rockchip/evb_rk3399/README
@@ -35,12 +35,6 @@
> git clone https://github.com/rockchip-linux/rkbin.git
> git clone https://github.com/rockchip-linux/rkdeveloptool.git
-Get some prerequisites
-======================
-
-You need the Python elftools.elf.elffile library for make_fit_atf.py to work:
-
- > sudo apt-get install python-pyelftools
Compile ATF
===========
diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/rockchip/evb_rk3399/evb-rk3399.c
index eb1b832..b9049ab 100644
--- a/board/rockchip/evb_rk3399/evb-rk3399.c
+++ b/board/rockchip/evb_rk3399/evb-rk3399.c
@@ -5,19 +5,15 @@
#include <common.h>
#include <dm.h>
-#include <dm/pinctrl.h>
#include <asm/arch-rockchip/periph.h>
#include <power/regulator.h>
-int board_init(void)
+#ifndef CONFIG_SPL_BUILD
+int board_early_init_f(void)
{
struct udevice *regulator;
int ret;
- ret = regulators_enable_boot_on(false);
- if (ret)
- debug("%s: Cannot enable boot on regulator\n", __func__);
-
ret = regulator_get_by_platname("vcc5v0_host", ®ulator);
if (ret) {
debug("%s vcc5v0_host init fail! ret %d\n", __func__, ret);
@@ -25,11 +21,10 @@
}
ret = regulator_set_enable(regulator, true);
- if (ret) {
- debug("%s vcc5v0-host-en set fail!\n", __func__);
- goto out;
- }
+ if (ret)
+ debug("%s vcc5v0-host-en set fail! ret %d\n", __func__, ret);
out:
return 0;
}
+#endif
diff --git a/board/rockchip/evb_rv1108/evb_rv1108.c b/board/rockchip/evb_rv1108/evb_rv1108.c
index 457b110..733f293 100644
--- a/board/rockchip/evb_rv1108/evb_rv1108.c
+++ b/board/rockchip/evb_rv1108/evb_rv1108.c
@@ -47,23 +47,9 @@
return 0;
}
-
-int board_init(void)
-{
- return 0;
-}
-
int dram_init(void)
{
gd->ram_size = 0x8000000;
return 0;
}
-
-int dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = 0x60000000;
- gd->bd->bi_dram[0].size = 0x8000000;
-
- return 0;
-}
diff --git a/board/rockchip/fennec_rk3288/Kconfig b/board/rockchip/fennec_rk3288/Kconfig
deleted file mode 100644
index 1dcfcf0..0000000
--- a/board/rockchip/fennec_rk3288/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_FENNEC_RK3288
-
-config SYS_BOARD
- default "fennec_rk3288"
-
-config SYS_VENDOR
- default "rockchip"
-
-config SYS_CONFIG_NAME
- default "fennec_rk3288"
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
-endif
diff --git a/board/rockchip/fennec_rk3288/MAINTAINERS b/board/rockchip/fennec_rk3288/MAINTAINERS
deleted file mode 100644
index 78a389b..0000000
--- a/board/rockchip/fennec_rk3288/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-FENNEC-RK3288
-M: Lin Huang <hl@rock-chips.com>
-S: Maintained
-F: board/rockchip/fennec_rk3288
-F: include/configs/fennec_rk3288.h
-F: configs/fennec-rk3288_defconfig
diff --git a/board/rockchip/fennec_rk3288/Makefile b/board/rockchip/fennec_rk3288/Makefile
deleted file mode 100644
index b287db6..0000000
--- a/board/rockchip/fennec_rk3288/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# (C) Copyright 2016 Rockchip Electronics Co., Ltd
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += fennec-rk3288.o
diff --git a/board/rockchip/fennec_rk3288/fennec-rk3288.c b/board/rockchip/fennec_rk3288/fennec-rk3288.c
deleted file mode 100644
index ce45544..0000000
--- a/board/rockchip/fennec_rk3288/fennec-rk3288.c
+++ /dev/null
@@ -1,14 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- */
-
-#include <common.h>
-#include <spl.h>
-
-void board_boot_order(u32 *spl_boot_list)
-{
- /* eMMC prior to sdcard */
- spl_boot_list[0] = BOOT_DEVICE_MMC2;
- spl_boot_list[1] = BOOT_DEVICE_MMC1;
-}
diff --git a/board/rockchip/sheep_rk3368/sheep_rk3368.c b/board/rockchip/sheep_rk3368/sheep_rk3368.c
index 9bb93c7..b81f970 100644
--- a/board/rockchip/sheep_rk3368/sheep_rk3368.c
+++ b/board/rockchip/sheep_rk3368/sheep_rk3368.c
@@ -2,18 +2,3 @@
/*
* Copyright (c) 2017 Andy Yan
*/
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/grf_rk3368.h>
-#include <syscon.h>
-
-int mach_cpu_init(void)
-{
- return 0;
-}
-
-int board_init(void)
-{
- return 0;
-}
diff --git a/board/rockchip/tinker_rk3288/tinker-rk3288.c b/board/rockchip/tinker_rk3288/tinker-rk3288.c
index 44f1318..6c76c3c 100644
--- a/board/rockchip/tinker_rk3288/tinker-rk3288.c
+++ b/board/rockchip/tinker_rk3288/tinker-rk3288.c
@@ -5,7 +5,7 @@
#include <common.h>
#include <dm.h>
-#include <environment.h>
+#include <env.h>
#include <i2c_eeprom.h>
#include <netdev.h>
@@ -21,7 +21,7 @@
return i2c_eeprom_read(dev, 0, addr, 6);
}
-int rk_board_late_init(void)
+int rk3288_board_late_init(void)
{
u8 ethaddr[6];
diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c
index 0c7b4ee..f1e7aab 100644
--- a/board/ronetix/pm9261/pm9261.c
+++ b/board/ronetix/pm9261/pm9261.c
@@ -17,9 +17,6 @@
#include <asm/arch/at91_matrix.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
-
-#include <lcd.h>
-#include <atmel_lcdc.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
#include <net.h>
#endif
@@ -110,105 +107,6 @@
}
#endif
-#ifdef CONFIG_LCD
-vidinfo_t panel_info = {
- .vl_col = 240,
- .vl_row = 320,
- .vl_clk = 4965000,
- .vl_sync = ATMEL_LCDC_INVLINE_INVERTED |
- ATMEL_LCDC_INVFRAME_INVERTED,
- .vl_bpix = 3,
- .vl_tft = 1,
- .vl_hsync_len = 5,
- .vl_left_margin = 1,
- .vl_right_margin = 33,
- .vl_vsync_len = 1,
- .vl_upper_margin = 1,
- .vl_lower_margin = 0,
- .mmio = ATMEL_BASE_LCDC,
-};
-
-void lcd_enable(void)
-{
- at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power up */
-}
-
-void lcd_disable(void)
-{
- at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power down */
-}
-
-static void pm9261_lcd_hw_init(void)
-{
- at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* LCDHSYNC */
- at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* LCDDOTCK */
- at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* LCDDEN */
- at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* LCDCC */
- at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* LCDD2 */
- at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* LCDD3 */
- at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* LCDD4 */
- at91_set_a_periph(AT91_PIO_PORTB, 10, 0); /* LCDD5 */
- at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* LCDD6 */
- at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* LCDD7 */
- at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* LCDD10 */
- at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* LCDD11 */
- at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* LCDD12 */
- at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* LCDD13 */
- at91_set_a_periph(AT91_PIO_PORTB, 19, 0); /* LCDD14 */
- at91_set_a_periph(AT91_PIO_PORTB, 20, 0); /* LCDD15 */
- at91_set_b_periph(AT91_PIO_PORTB, 23, 0); /* LCDD18 */
- at91_set_b_periph(AT91_PIO_PORTB, 24, 0); /* LCDD19 */
- at91_set_b_periph(AT91_PIO_PORTB, 25, 0); /* LCDD20 */
- at91_set_b_periph(AT91_PIO_PORTB, 26, 0); /* LCDD21 */
- at91_set_b_periph(AT91_PIO_PORTB, 27, 0); /* LCDD22 */
- at91_set_b_periph(AT91_PIO_PORTB, 28, 0); /* LCDD23 */
-
- at91_system_clk_enable(AT91_PMC_HCK1);
-
- gd->fb_base = ATMEL_BASE_SRAM;
-}
-
-#ifdef CONFIG_LCD_INFO
-#include <nand.h>
-#include <version.h>
-
-extern flash_info_t flash_info[];
-
-void lcd_show_board_info(void)
-{
- ulong dram_size, nand_size, flash_size;
- int i;
- char temp[32];
-
- lcd_printf ("%s\n", U_BOOT_VERSION);
- lcd_printf ("(C) 2009 Ronetix GmbH\n");
- lcd_printf ("support@ronetix.at\n");
- lcd_printf ("%s CPU at %s MHz",
- CONFIG_SYS_AT91_CPU_NAME,
- strmhz(temp, get_cpu_clk_rate()));
-
- dram_size = 0;
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
- dram_size += gd->bd->bi_dram[i].size;
-
- nand_size = 0;
- for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += get_nand_dev_by_index(i)->size;
-
- flash_size = 0;
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
- flash_size += flash_info[i].size;
-
- lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
- "%ld MB DataFlash\n",
- dram_size >> 20,
- nand_size >> 20,
- flash_size >> 20);
-}
-#endif /* CONFIG_LCD_INFO */
-
-#endif /* CONFIG_LCD */
-
int board_early_init_f(void)
{
return 0;
@@ -228,9 +126,6 @@
#ifdef CONFIG_DRIVER_DM9000
pm9261_dm9000_hw_init();
#endif
-#ifdef CONFIG_LCD
- pm9261_lcd_hw_init();
-#endif
return 0;
}
diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c
index 692288d..2da39c4 100644
--- a/board/ronetix/pm9263/pm9263.c
+++ b/board/ronetix/pm9263/pm9263.c
@@ -17,8 +17,6 @@
#include <asm/arch/at91_matrix.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
-#include <lcd.h>
-#include <atmel_lcdc.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
#include <net.h>
#endif
@@ -109,32 +107,6 @@
#endif
#ifdef CONFIG_LCD
-vidinfo_t panel_info = {
- .vl_col = 240,
- .vl_row = 320,
- .vl_clk = 4965000,
- .vl_sync = ATMEL_LCDC_INVLINE_INVERTED |
- ATMEL_LCDC_INVFRAME_INVERTED,
- .vl_bpix = 3,
- .vl_tft = 1,
- .vl_hsync_len = 5,
- .vl_left_margin = 1,
- .vl_right_margin = 33,
- .vl_vsync_len = 1,
- .vl_upper_margin = 1,
- .vl_lower_margin = 0,
- .mmio = ATMEL_BASE_LCDC,
-};
-
-void lcd_enable(void)
-{
- at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power up */
-}
-
-void lcd_disable(void)
-{
- at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */
-}
#ifdef CONFIG_LCD_IN_PSRAM
@@ -226,32 +198,6 @@
static void pm9263_lcd_hw_init(void)
{
- at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */
- at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
- at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
- at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
- at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
- at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
- at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
- at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
- at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
- at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
- at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
- at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
- at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
- at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
- at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
- at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
- at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
- at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
- at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
- at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
- at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
- at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
- at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
-
- at91_periph_clk_enable(ATMEL_ID_LCDC);
-
/* Power Control */
at91_set_pio_output(AT91_PIO_PORTA, 22, 1);
at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */
@@ -267,45 +213,6 @@
}
-#ifdef CONFIG_LCD_INFO
-#include <nand.h>
-#include <version.h>
-
-extern flash_info_t flash_info[];
-
-void lcd_show_board_info(void)
-{
- ulong dram_size, nand_size, flash_size;
- int i;
- char temp[32];
-
- lcd_printf ("%s\n", U_BOOT_VERSION);
- lcd_printf ("(C) 2009 Ronetix GmbH\n");
- lcd_printf ("support@ronetix.at\n");
- lcd_printf ("%s CPU at %s MHz",
- CONFIG_SYS_AT91_CPU_NAME,
- strmhz(temp, get_cpu_clk_rate()));
-
- dram_size = 0;
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
- dram_size += gd->bd->bi_dram[i].size;
-
- nand_size = 0;
- for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += get_nand_dev_by_index(i)->size;
-
- flash_size = 0;
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
- flash_size += flash_info[i].size;
-
- lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
- "4 MB PSRAM\n",
- dram_size >> 20,
- nand_size >> 20,
- flash_size >> 20);
-}
-#endif /* CONFIG_LCD_INFO */
-
#endif /* CONFIG_LCD */
int board_early_init_f(void)
diff --git a/board/samsung/common/exynos5-dt.c b/board/samsung/common/exynos5-dt.c
index 87eb381..387d1b9 100644
--- a/board/samsung/common/exynos5-dt.c
+++ b/board/samsung/common/exynos5-dt.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <dm.h>
#include <dwc3-uboot.h>
+#include <env.h>
#include <fdtdec.h>
#include <asm/io.h>
#include <errno.h>
diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c
index 53cd1b2..3ef1e79 100644
--- a/board/samsung/common/misc.c
+++ b/board/samsung/common/misc.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
+#include <env.h>
#include <lcd.h>
#include <libtizen.h>
#include <samsung/misc.h>
diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c
index 3e594fd..9aa97f0 100644
--- a/board/samsung/odroid/odroid.c
+++ b/board/samsung/odroid/odroid.c
@@ -12,6 +12,7 @@
#include <asm/gpio.h>
#include <asm/arch/cpu.h>
#include <dm.h>
+#include <env.h>
#include <power/pmic.h>
#include <power/regulator.h>
#include <power/max77686_pmic.h>
diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c
index e0846bc..ec85f70 100644
--- a/board/samsung/trats/trats.c
+++ b/board/samsung/trats/trats.c
@@ -7,6 +7,7 @@
*/
#include <common.h>
+#include <env.h>
#include <lcd.h>
#include <asm/io.h>
#include <asm/gpio.h>
diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c
index f8281f2..ed9c5b5 100644
--- a/board/samsung/universal_c210/universal.c
+++ b/board/samsung/universal_c210/universal.c
@@ -6,6 +6,7 @@
*/
#include <common.h>
+#include <env.h>
#include <spi.h>
#include <lcd.h>
#include <asm/io.h>
diff --git a/board/samtec/vining_fpga/socfpga.c b/board/samtec/vining_fpga/socfpga.c
index efc8ddf..1e095a4 100644
--- a/board/samtec/vining_fpga/socfpga.c
+++ b/board/samtec/vining_fpga/socfpga.c
@@ -4,7 +4,7 @@
*/
#include <common.h>
-#include <environment.h>
+#include <env.h>
#include <asm/arch/reset_manager.h>
#include <asm/io.h>
#include <asm/gpio.h>
diff --git a/board/sandbox/README.sandbox b/board/sandbox/README.sandbox
deleted file mode 100644
index 48c1e2b..0000000
--- a/board/sandbox/README.sandbox
+++ /dev/null
@@ -1,487 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2014 The Chromium OS Authors.
- */
-
-Native Execution of U-Boot
-==========================
-
-The 'sandbox' architecture is designed to allow U-Boot to run under Linux on
-almost any hardware. To achieve this it builds U-Boot (so far as possible)
-as a normal C application with a main() and normal C libraries.
-
-All of U-Boot's architecture-specific code therefore cannot be built as part
-of the sandbox U-Boot. The purpose of running U-Boot under Linux is to test
-all the generic code, not specific to any one architecture. The idea is to
-create unit tests which we can run to test this upper level code.
-
-CONFIG_SANDBOX is defined when building a native board.
-
-The board name is 'sandbox' but the vendor name is unset, so there is a
-single board in board/sandbox.
-
-CONFIG_SANDBOX_BIG_ENDIAN should be defined when running on big-endian
-machines.
-
-There are two versions of the sandbox: One using 32-bit-wide integers, and one
-using 64-bit-wide integers. The 32-bit version can be build and run on either
-32 or 64-bit hosts by either selecting or deselecting CONFIG_SANDBOX_32BIT; by
-default, the sandbox it built for a 32-bit host. The sandbox using 64-bit-wide
-integers can only be built on 64-bit hosts.
-
-Note that standalone/API support is not available at present.
-
-
-Basic Operation
----------------
-
-To run sandbox U-Boot use something like:
-
- make sandbox_defconfig all
- ./u-boot
-
-Note:
- If you get errors about 'sdl-config: Command not found' you may need to
- install libsdl1.2-dev or similar to get SDL support. Alternatively you can
- build sandbox without SDL (i.e. no display/keyboard support) by removing
- the CONFIG_SANDBOX_SDL line in include/configs/sandbox.h or using:
-
- make sandbox_defconfig all NO_SDL=1
- ./u-boot
-
-U-Boot will start on your computer, showing a sandbox emulation of the serial
-console:
-
-
-U-Boot 2014.04 (Mar 20 2014 - 19:06:00)
-
-DRAM: 128 MiB
-Using default environment
-
-In: serial
-Out: lcd
-Err: lcd
-=>
-
-You can issue commands as your would normally. If the command you want is
-not supported you can add it to include/configs/sandbox.h.
-
-To exit, type 'reset' or press Ctrl-C.
-
-
-Console / LCD support
----------------------
-
-Assuming that CONFIG_SANDBOX_SDL is defined when building, you can run the
-sandbox with LCD and keyboard emulation, using something like:
-
- ./u-boot -d u-boot.dtb -l
-
-This will start U-Boot with a window showing the contents of the LCD. If
-that window has the focus then you will be able to type commands as you
-would on the console. You can adjust the display settings in the device
-tree file - see arch/sandbox/dts/sandbox.dts.
-
-
-Command-line Options
---------------------
-
-Various options are available, mostly for test purposes. Use -h to see
-available options. Some of these are described below.
-
-The terminal is normally in what is called 'raw-with-sigs' mode. This means
-that you can use arrow keys for command editing and history, but if you
-press Ctrl-C, U-Boot will exit instead of handling this as a keypress.
-
-Other options are 'raw' (so Ctrl-C is handled within U-Boot) and 'cooked'
-(where the terminal is in cooked mode and cursor keys will not work, Ctrl-C
-will exit).
-
-As mentioned above, -l causes the LCD emulation window to be shown.
-
-A device tree binary file can be provided with -d. If you edit the source
-(it is stored at arch/sandbox/dts/sandbox.dts) you must rebuild U-Boot to
-recreate the binary file.
-
-To execute commands directly, use the -c option. You can specify a single
-command, or multiple commands separated by a semicolon, as is normal in
-U-Boot. Be careful with quoting as the shell will normally process and
-swallow quotes. When -c is used, U-Boot exits after the command is complete,
-but you can force it to go to interactive mode instead with -i.
-
-
-Memory Emulation
-----------------
-
-Memory emulation is supported, with the size set by CONFIG_SYS_SDRAM_SIZE.
-The -m option can be used to read memory from a file on start-up and write
-it when shutting down. This allows preserving of memory contents across
-test runs. You can tell U-Boot to remove the memory file after it is read
-(on start-up) with the --rm_memory option.
-
-To access U-Boot's emulated memory within the code, use map_sysmem(). This
-function is used throughout U-Boot to ensure that emulated memory is used
-rather than the U-Boot application memory. This provides memory starting
-at 0 and extending to the size of the emulation.
-
-
-Storing State
--------------
-
-With sandbox you can write drivers which emulate the operation of drivers on
-real devices. Some of these drivers may want to record state which is
-preserved across U-Boot runs. This is particularly useful for testing. For
-example, the contents of a SPI flash chip should not disappear just because
-U-Boot exits.
-
-State is stored in a device tree file in a simple format which is driver-
-specific. You then use the -s option to specify the state file. Use -r to
-make U-Boot read the state on start-up (otherwise it starts empty) and -w
-to write it on exit (otherwise the stored state is left unchanged and any
-changes U-Boot made will be lost). You can also use -n to tell U-Boot to
-ignore any problems with missing state. This is useful when first running
-since the state file will be empty.
-
-The device tree file has one node for each driver - the driver can store
-whatever properties it likes in there. See 'Writing Sandbox Drivers' below
-for more details on how to get drivers to read and write their state.
-
-
-Running and Booting
--------------------
-
-Since there is no machine architecture, sandbox U-Boot cannot actually boot
-a kernel, but it does support the bootm command. Filesystems, memory
-commands, hashing, FIT images, verified boot and many other features are
-supported.
-
-When 'bootm' runs a kernel, sandbox will exit, as U-Boot does on a real
-machine. Of course in this case, no kernel is run.
-
-It is also possible to tell U-Boot that it has jumped from a temporary
-previous U-Boot binary, with the -j option. That binary is automatically
-removed by the U-Boot that gets the -j option. This allows you to write
-tests which emulate the action of chain-loading U-Boot, typically used in
-a situation where a second 'updatable' U-Boot is stored on your board. It
-is very risky to overwrite or upgrade the only U-Boot on a board, since a
-power or other failure will brick the board and require return to the
-manufacturer in the case of a consumer device.
-
-
-Supported Drivers
------------------
-
-U-Boot sandbox supports these emulations:
-
-- Block devices
-- Chrome OS EC
-- GPIO
-- Host filesystem (access files on the host from within U-Boot)
-- I2C
-- Keyboard (Chrome OS)
-- LCD
-- Network
-- Serial (for console only)
-- Sound (incomplete - see sandbox_sdl_sound_init() for details)
-- SPI
-- SPI flash
-- TPM (Trusted Platform Module)
-
-A wide range of commands are implemented. Filesystems which use a block
-device are supported.
-
-Also sandbox supports driver model (CONFIG_DM) and associated commands.
-
-
-Sandbox Variants
-----------------
-
-There are unfortunately quite a few variants at present:
-
-sandbox - should be used for most tests
-sandbox64 - special build that forces a 64-bit host
-sandbox_flattree - builds with dev_read_...() functions defined as inline.
- We need this build so that we can test those inline functions, and we
- cannot build with both the inline functions and the non-inline functions
- since they are named the same.
-sandbox_noblk - builds without CONFIG_BLK, which means the legacy block
- drivers are used. We cannot use both the legacy and driver-model block
- drivers since they implement the same functions
-sandbox_spl - builds sandbox with SPL support, so you can run spl/u-boot-spl
- and it will start up and then load ./u-boot. It is also possible to
- run ./u-boot directly.
-
-Of these sandbox_noblk can be removed once CONFIG_BLK is used everwhere, and
-sandbox_spl can probably be removed since it is a superset of sandbox.
-
-Most of the config options should be identical between these variants.
-
-
-Linux RAW Networking Bridge
----------------------------
-
-The sandbox_eth_raw driver bridges traffic between the bottom of the network
-stack and the RAW sockets API in Linux. This allows much of the U-Boot network
-functionality to be tested in sandbox against real network traffic.
-
-For Ethernet network adapters, the bridge utilizes the RAW AF_PACKET API. This
-is needed to get access to the lowest level of the network stack in Linux. This
-means that all of the Ethernet frame is included. This allows the U-Boot network
-stack to be fully used. In other words, nothing about the Linux network stack is
-involved in forming the packets that end up on the wire. To receive the
-responses to packets sent from U-Boot the network interface has to be set to
-promiscuous mode so that the network card won't filter out packets not destined
-for its configured (on Linux) MAC address.
-
-The RAW sockets Ethernet API requires elevated privileges in Linux. You can
-either run as root, or you can add the capability needed like so:
-
-sudo /sbin/setcap "CAP_NET_RAW+ep" /path/to/u-boot
-
-The default device tree for sandbox includes an entry for eth0 on the sandbox
-host machine whose alias is "eth1". The following are a few examples of network
-operations being tested on the eth0 interface.
-
-sudo /path/to/u-boot -D
-
-DHCP
-....
-
-setenv autoload no
-setenv ethrotate no
-setenv ethact eth1
-dhcp
-
-PING
-....
-
-setenv autoload no
-setenv ethrotate no
-setenv ethact eth1
-dhcp
-ping $gatewayip
-
-TFTP
-....
-
-setenv autoload no
-setenv ethrotate no
-setenv ethact eth1
-dhcp
-setenv serverip WWW.XXX.YYY.ZZZ
-tftpboot u-boot.bin
-
-The bridge also supports (to a lesser extent) the localhost interface, 'lo'.
-
-The 'lo' interface cannot use the RAW AF_PACKET API because the lo interface
-doesn't support Ethernet-level traffic. It is a higher-level interface that is
-expected only to be used at the AF_INET level of the API. As such, the most raw
-we can get on that interface is the RAW AF_INET API on UDP. This allows us to
-set the IP_HDRINCL option to include everything except the Ethernet header in
-the packets we send and receive.
-
-Because only UDP is supported, ICMP traffic will not work, so expect that ping
-commands will time out.
-
-The default device tree for sandbox includes an entry for lo on the sandbox
-host machine whose alias is "eth5". The following is an example of a network
-operation being tested on the lo interface.
-
-TFTP
-....
-
-setenv ethrotate no
-setenv ethact eth5
-tftpboot u-boot.bin
-
-
-SPI Emulation
--------------
-
-Sandbox supports SPI and SPI flash emulation.
-
-This is controlled by the spi_sf argument, the format of which is:
-
- bus:cs:device:file
-
- bus - SPI bus number
- cs - SPI chip select number
- device - SPI device emulation name
- file - File on disk containing the data
-
-For example:
-
- dd if=/dev/zero of=spi.bin bs=1M count=4
- ./u-boot --spi_sf 0:0:M25P16:spi.bin
-
-With this setup you can issue SPI flash commands as normal:
-
-=>sf probe
-SF: Detected M25P16 with page size 64 KiB, total 2 MiB
-=>sf read 0 0 10000
-SF: 65536 bytes @ 0x0 Read: OK
-=>
-
-Since this is a full SPI emulation (rather than just flash), you can
-also use low-level SPI commands:
-
-=>sspi 0:0 32 9f
-FF202015
-
-This is issuing a READ_ID command and getting back 20 (ST Micro) part
-0x2015 (the M25P16).
-
-Drivers are connected to a particular bus/cs using sandbox's state
-structure (see the 'spi' member). A set of operations must be provided
-for each driver.
-
-
-Configuration settings for the curious are:
-
-CONFIG_SANDBOX_SPI_MAX_BUS
- The maximum number of SPI buses supported by the driver (default 1).
-
-CONFIG_SANDBOX_SPI_MAX_CS
- The maximum number of chip selects supported by the driver
- (default 10).
-
-CONFIG_SPI_IDLE_VAL
- The idle value on the SPI bus
-
-
-Block Device Emulation
-----------------------
-
-U-Boot can use raw disk images for block device emulation. To e.g. list
-the contents of the root directory on the second partion of the image
-"disk.raw", you can use the following commands:
-
-=>host bind 0 ./disk.raw
-=>ls host 0:2
-
-A disk image can be created using the following commands:
-
-$> truncate -s 1200M ./disk.raw
-$> echo -e "label: gpt\n,64M,U\n,,L" | /usr/sbin/sgdisk ./disk.raw
-$> lodev=`sudo losetup -P -f --show ./disk.raw`
-$> sudo mkfs.vfat -n EFI -v ${lodev}p1
-$> sudo mkfs.ext4 -L ROOT -v ${lodev}p2
-
-or utilize the device described in test/py/make_test_disk.py:
-
- #!/usr/bin/python
- import make_test_disk
- make_test_disk.makeDisk()
-
-Writing Sandbox Drivers
------------------------
-
-Generally you should put your driver in a file containing the word 'sandbox'
-and put it in the same directory as other drivers of its type. You can then
-implement the same hooks as the other drivers.
-
-To access U-Boot's emulated memory, use map_sysmem() as mentioned above.
-
-If your driver needs to store configuration or state (such as SPI flash
-contents or emulated chip registers), you can use the device tree as
-described above. Define handlers for this with the SANDBOX_STATE_IO macro.
-See arch/sandbox/include/asm/state.h for documentation. In short you provide
-a node name, compatible string and functions to read and write the state.
-Since writing the state can expand the device tree, you may need to use
-state_setprop() which does this automatically and avoids running out of
-space. See existing code for examples.
-
-
-Debugging the init sequence
----------------------------
-
-If you get a failure in the initcall sequence, like this:
-
- initcall sequence 0000560775957c80 failed at call 0000000000048134 (err=-96)
-
-Then you use can use grep to see which init call failed, e.g.:
-
- $ grep 0000000000048134 u-boot.map
- stdio_add_devices
-
-Of course another option is to run it with a debugger such as gdb:
-
- $ gdb u-boot
- ...
- (gdb) br initcall.h:41
- Breakpoint 1 at 0x4db9d: initcall.h:41. (2 locations)
-
-Note that two locations are reported, since this function is used in both
-board_init_f() and board_init_r().
-
- (gdb) r
- Starting program: /tmp/b/sandbox/u-boot
- [Thread debugging using libthread_db enabled]
- Using host libthread_db library "/lib/x86_64-linux-gnu/libthread_db.so.1".
-
- U-Boot 2018.09-00264-ge0c2ba9814-dirty (Sep 22 2018 - 12:21:46 -0600)
-
- DRAM: 128 MiB
- MMC:
-
- Breakpoint 1, initcall_run_list (init_sequence=0x5555559619e0 <init_sequence_f>)
- at /scratch/sglass/cosarm/src/third_party/u-boot/files/include/initcall.h:41
- 41 printf("initcall sequence %p failed at call %p (err=%d)\n",
- (gdb) print *init_fnc_ptr
- $1 = (const init_fnc_t) 0x55555559c114 <stdio_add_devices>
- (gdb)
-
-
-This approach can be used on normal boards as well as sandbox.
-
-
-Testing
--------
-
-U-Boot sandbox can be used to run various tests, mostly in the test/
-directory. These include:
-
- command_ut
- - Unit tests for command parsing and handling
- compression
- - Unit tests for U-Boot's compression algorithms, useful for
- security checking. It supports gzip, bzip2, lzma and lzo.
- driver model
- - Run this pytest
- ./test/py/test.py --bd sandbox --build -k ut_dm -v
- image
- - Unit tests for images:
- test/image/test-imagetools.sh - multi-file images
- test/image/test-fit.py - FIT images
- tracing
- - test/trace/test-trace.sh tests the tracing system (see README.trace)
- verified boot
- - See test/vboot/vboot_test.sh for this
-
-If you change or enhance any of the above subsystems, you shold write or
-expand a test and include it with your patch series submission. Test
-coverage in U-Boot is limited, as we need to work to improve it.
-
-Note that many of these tests are implemented as commands which you can
-run natively on your board if desired (and enabled).
-
-To run all tests use "make check".
-
-
-Memory Map
-----------
-
-Sandbox has its own emulated memory starting at 0. Here are some of the things
-that are mapped into that memory:
-
- 0 CONFIG_SYS_FDT_LOAD_ADDR Device tree
- e000 CONFIG_BLOBLIST_ADDR Blob list
- 10000 CONFIG_MALLOC_F_ADDR Early memory allocation
- f0000 CONFIG_PRE_CON_BUF_ADDR Pre-console buffer
- 100000 CONFIG_TRACE_EARLY_ADDR Early trace buffer (if enabled)
-=
-
-
---
-Simon Glass <sjg@chromium.org>
-Updated 22-Mar-14
diff --git a/board/seco/common/mx6.c b/board/seco/common/mx6.c
index fd7008a..51832b9 100644
--- a/board/seco/common/mx6.c
+++ b/board/seco/common/mx6.c
@@ -16,7 +16,7 @@
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/boot_mode.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/mxc_hdmi.h>
diff --git a/board/seco/mx6quq7/mx6quq7.c b/board/seco/mx6quq7/mx6quq7.c
index 094a210..c1e36b6 100644
--- a/board/seco/mx6quq7/mx6quq7.c
+++ b/board/seco/mx6quq7/mx6quq7.c
@@ -17,7 +17,7 @@
#include <asm/mach-imx/boot_mode.h>
#include <malloc.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/mxc_hdmi.h>
diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c
index 622bde5..75462d1 100644
--- a/board/siemens/common/board.c
+++ b/board/siemens/common/board.c
@@ -10,6 +10,7 @@
*/
#include <common.h>
+#include <env.h>
#include <errno.h>
#include <spl.h>
#include <asm/arch/cpu.h>
@@ -188,14 +189,11 @@
{
char *ptr_env;
char str_tmp[5]; /* must contain "ledX"*/
- char num[1];
unsigned char i, idx, pos1, pos2, ccount;
unsigned char gpio_n, gpio_s0, gpio_s1;
for (i = 0; i < MAX_NR_LEDS; i++) {
- strcpy(str_tmp, "led");
- sprintf(num, "%d", i);
- strcat(str_tmp, num);
+ sprintf(str_tmp, "led%d", i);
/* If env var is not found we stop */
ptr_env = env_get(str_tmp);
diff --git a/board/siemens/common/factoryset.c b/board/siemens/common/factoryset.c
index 9661542..7715ddf 100644
--- a/board/siemens/common/factoryset.c
+++ b/board/siemens/common/factoryset.c
@@ -8,7 +8,9 @@
#if !defined(CONFIG_SPL_BUILD)
#include <common.h>
-#include <environment.h>
+#include <env.h>
+#include <dm.h>
+#include <env_internal.h>
#include <i2c.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
@@ -143,16 +145,39 @@
int i, pages = 0, size = 0;
unsigned char eeprom_buf[0x3c00], hdr[4], buf[MAX_STRING_LENGTH];
unsigned char *cp, *cp1;
+#if CONFIG_IS_ENABLED(DM_I2C)
+ struct udevice *bus, *dev;
+ int ret;
+#endif
#if defined(CONFIG_DFU_OVER_USB)
factory_dat.usb_vendor_id = CONFIG_USB_GADGET_VENDOR_NUM;
factory_dat.usb_product_id = CONFIG_USB_GADGET_PRODUCT_NUM;
#endif
+
+#if CONFIG_IS_ENABLED(DM_I2C)
+ ret = uclass_get_device_by_seq(UCLASS_I2C, EEPROM_I2C_BUS, &bus);
+ if (ret)
+ goto err;
+
+ ret = dm_i2c_probe(bus, i2c_addr, 0, &dev);
+ if (ret)
+ goto err;
+
+ ret = i2c_set_chip_offset_len(dev, 2);
+ if (ret)
+ goto err;
+
+ ret = dm_i2c_read(dev, EEPROM_FATORYSET_OFFSET, hdr, sizeof(hdr));
+ if (ret)
+ goto err;
+#else
if (i2c_probe(i2c_addr))
goto err;
if (i2c_read(i2c_addr, EEPROM_FATORYSET_OFFSET, 2, hdr, sizeof(hdr)))
goto err;
+#endif
if ((hdr[0] != 0x99) || (hdr[1] != 0x80)) {
printf("FactorySet is not right in eeprom.\n");
@@ -173,16 +198,33 @@
* data after every time we got a record from eeprom
*/
debug("Read eeprom page :\n");
- for (i = 0; i < pages; i++)
+ for (i = 0; i < pages; i++) {
+#if CONFIG_IS_ENABLED(DM_I2C)
+ ret = dm_i2c_read(dev, (OFF_PG + i) * EEPR_PG_SZ,
+ eeprom_buf + (i * EEPR_PG_SZ), EEPR_PG_SZ);
+ if (ret)
+ goto err;
+#else
if (i2c_read(i2c_addr, (OFF_PG + i) * EEPR_PG_SZ, 2,
eeprom_buf + (i * EEPR_PG_SZ), EEPR_PG_SZ))
goto err;
+#endif
+ }
- if (size % EEPR_PG_SZ)
+ if (size % EEPR_PG_SZ) {
+#if CONFIG_IS_ENABLED(DM_I2C)
+ ret = dm_i2c_read(dev, (OFF_PG + pages) * EEPR_PG_SZ,
+ eeprom_buf + (pages * EEPR_PG_SZ),
+ size % EEPR_PG_SZ);
+ if (ret)
+ goto err;
+#else
if (i2c_read(i2c_addr, (OFF_PG + pages) * EEPR_PG_SZ, 2,
eeprom_buf + (pages * EEPR_PG_SZ),
(size % EEPR_PG_SZ)))
goto err;
+#endif
+ }
/* we do below just for eeprom align */
for (i = 0; i < size; i++)
@@ -202,6 +244,20 @@
cp1 += 3;
}
+#if CONFIG_IS_ENABLED(TARGET_GIEDI) || CONFIG_IS_ENABLED(TARGET_DENEB)
+ /* get mac address for WLAN */
+ ret = get_factory_record_val(cp, size, (uchar *)"WLAN1", (uchar *)"mac",
+ buf, MAX_STRING_LENGTH);
+ if (ret > 0) {
+ cp1 = buf;
+ for (i = 0; i < 6; i++) {
+ factory_dat.mac_wlan[i] = simple_strtoul((char *)cp1,
+ NULL, 16);
+ cp1 += 3;
+ }
+ }
+#endif
+
#if defined(CONFIG_DFU_OVER_USB)
/* read vid and pid for dfu mode */
if (0 <= get_factory_record_val(cp, size, (uchar *)"USBD1",
@@ -264,42 +320,76 @@
return 1;
}
-static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+static int get_mac_from_efuse(uint8_t mac[6])
+{
+#ifdef CONFIG_AM33XX
+ struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+ uint32_t mac_hi, mac_lo;
+
+ mac_lo = readl(&cdev->macid0l);
+ mac_hi = readl(&cdev->macid0h);
+
+ mac[0] = mac_hi & 0xFF;
+ mac[1] = (mac_hi & 0xFF00) >> 8;
+ mac[2] = (mac_hi & 0xFF0000) >> 16;
+ mac[3] = (mac_hi & 0xFF000000) >> 24;
+ mac[4] = mac_lo & 0xFF;
+ mac[5] = (mac_lo & 0xFF00) >> 8;
+#else
+ /* unhandled */
+ memset(mac, 0, 6);
+#endif
+ if (!is_valid_ethaddr(mac)) {
+ puts("Warning: ethaddr not set by FactorySet or E-fuse. ");
+ puts("Set <ethaddr> variable to overcome this.\n");
+ return -1;
+ }
+ return 0;
+}
static int factoryset_mac_env_set(void)
{
uint8_t mac_addr[6];
+ /* Set mac from factoryset or try reading E-fuse */
debug("FactorySet: Set mac address\n");
if (is_valid_ethaddr(factory_dat.mac)) {
memcpy(mac_addr, factory_dat.mac, 6);
} else {
- uint32_t mac_hi, mac_lo;
-
debug("Warning: FactorySet: <ethaddr> not set. Fallback to E-fuse\n");
- mac_lo = readl(&cdev->macid0l);
- mac_hi = readl(&cdev->macid0h);
-
- mac_addr[0] = mac_hi & 0xFF;
- mac_addr[1] = (mac_hi & 0xFF00) >> 8;
- mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
- mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
- mac_addr[4] = mac_lo & 0xFF;
- mac_addr[5] = (mac_lo & 0xFF00) >> 8;
- if (!is_valid_ethaddr(mac_addr)) {
- printf("Warning: ethaddr not set by FactorySet or E-fuse. Set <ethaddr> variable to overcome this.\n");
+ if (get_mac_from_efuse(mac_addr) < 0)
return -1;
- }
}
eth_env_set_enetaddr("ethaddr", mac_addr);
+
+#if CONFIG_IS_ENABLED(TARGET_GIEDI) || CONFIG_IS_ENABLED(TARGET_DENEB)
+ eth_env_set_enetaddr("eth1addr", mac_addr);
+
+ /* wlan mac */
+ if (is_valid_ethaddr(factory_dat.mac_wlan))
+ eth_env_set_enetaddr("eth2addr", factory_dat.mac_wlan);
+#endif
return 0;
}
+static void factoryset_dtb_env_set(void)
+{
+ /* Set ASN in environment*/
+ if (factory_dat.asn[0] != 0) {
+ env_set("dtb_name", (char *)factory_dat.asn);
+ } else {
+ /* dtb suffix gets added in load script */
+ env_set("dtb_name", "default");
+ }
+}
+
int factoryset_env_set(void)
{
int ret = 0;
+ factoryset_dtb_env_set();
+
if (factoryset_mac_env_set() < 0)
ret = -1;
diff --git a/board/siemens/common/factoryset.h b/board/siemens/common/factoryset.h
index d4e8353..261a217 100644
--- a/board/siemens/common/factoryset.h
+++ b/board/siemens/common/factoryset.h
@@ -11,6 +11,9 @@
struct factorysetcontainer {
uchar mac[6];
+#if CONFIG_IS_ENABLED(TARGET_GIEDI) || CONFIG_IS_ENABLED(TARGET_DENEB)
+ uchar mac_wlan[6];
+#endif
int usb_vendor_id;
int usb_product_id;
int pxm50;
diff --git a/board/siemens/draco/MAINTAINERS b/board/siemens/draco/MAINTAINERS
index e9107f0..c73f18c 100644
--- a/board/siemens/draco/MAINTAINERS
+++ b/board/siemens/draco/MAINTAINERS
@@ -1,5 +1,5 @@
DRACO BOARD
-M: Roger Meier <r.meier@siemens.com>
+M: Samuel Egli <samuel.egli@siemens.com>
S: Maintained
F: board/siemens/draco/
F: include/configs/draco.h
diff --git a/board/siemens/draco/board.c b/board/siemens/draco/board.c
index 95b89da..a6840b8 100644
--- a/board/siemens/draco/board.c
+++ b/board/siemens/draco/board.c
@@ -13,6 +13,7 @@
*/
#include <common.h>
+#include <env.h>
#include <errno.h>
#include <spl.h>
#include <asm/arch/cpu.h>
diff --git a/board/siemens/pxm2/MAINTAINERS b/board/siemens/pxm2/MAINTAINERS
index fa734c9..dc02fe8 100644
--- a/board/siemens/pxm2/MAINTAINERS
+++ b/board/siemens/pxm2/MAINTAINERS
@@ -1,5 +1,5 @@
PXM2 BOARD
-M: Roger Meier <r.meier@siemens.com>
+M: Samuel Egli <samuel.egli@siemens.com>
S: Maintained
F: board/siemens/pxm2/
F: include/configs/pxm2.h
diff --git a/board/siemens/pxm2/board.c b/board/siemens/pxm2/board.c
index 1b9e83e..30f0902 100644
--- a/board/siemens/pxm2/board.c
+++ b/board/siemens/pxm2/board.c
@@ -13,7 +13,7 @@
*/
#include <common.h>
-#include <environment.h>
+#include <env.h>
#include <errno.h>
#include <spl.h>
#include <asm/arch/cpu.h>
diff --git a/board/siemens/rut/MAINTAINERS b/board/siemens/rut/MAINTAINERS
index 8c1b770..1e92710 100644
--- a/board/siemens/rut/MAINTAINERS
+++ b/board/siemens/rut/MAINTAINERS
@@ -1,5 +1,5 @@
RUT BOARD
-M: Roger Meier <r.meier@siemens.com>
+M: Samuel Egli <samuel.egli@siemens.com>
S: Maintained
F: board/siemens/rut/
F: include/configs/rut.h
diff --git a/board/siemens/rut/board.c b/board/siemens/rut/board.c
index 25e2ed2..539ecef 100644
--- a/board/siemens/rut/board.c
+++ b/board/siemens/rut/board.c
@@ -11,6 +11,7 @@
*/
#include <common.h>
+#include <env.h>
#include <errno.h>
#include <spi.h>
#include <spl.h>
diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c
index 6ea97eb..1cf1f9e 100644
--- a/board/siemens/taurus/taurus.c
+++ b/board/siemens/taurus/taurus.c
@@ -14,7 +14,7 @@
#include <command.h>
#include <common.h>
#include <dm.h>
-#include <environment.h>
+#include <env.h>
#include <asm/io.h>
#include <asm/arch/at91sam9260_matrix.h>
#include <asm/arch/at91sam9_smc.h>
diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
index 8eb5e30..5d65080 100644
--- a/board/sifive/fu540/Kconfig
+++ b/board/sifive/fu540/Kconfig
@@ -28,7 +28,6 @@
imply CMD_PING
imply CLK_SIFIVE
imply CLK_SIFIVE_FU540_PRCI
- imply CLK_SIFIVE_GEMGXL_MGMT
imply DOS_PARTITION
imply EFI_PARTITION
imply IP_DYN
@@ -39,6 +38,12 @@
imply PHY_LIB
imply PHY_MSCC
imply SIFIVE_SERIAL
+ imply SPI
+ imply SPI_SIFIVE
+ imply MMC
+ imply MMC_SPI
+ imply MMC_BROKEN_CD
+ imply CMD_MMC
imply SMP
endif
diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
index 5adc4a3..47a2090 100644
--- a/board/sifive/fu540/fu540.c
+++ b/board/sifive/fu540/fu540.c
@@ -8,6 +8,138 @@
#include <common.h>
#include <dm.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+
+#ifdef CONFIG_MISC_INIT_R
+
+#define FU540_OTP_BASE_ADDR 0x10070000
+
+struct fu540_otp_regs {
+ u32 pa; /* Address input */
+ u32 paio; /* Program address input */
+ u32 pas; /* Program redundancy cell selection input */
+ u32 pce; /* OTP Macro enable input */
+ u32 pclk; /* Clock input */
+ u32 pdin; /* Write data input */
+ u32 pdout; /* Read data output */
+ u32 pdstb; /* Deep standby mode enable input (active low) */
+ u32 pprog; /* Program mode enable input */
+ u32 ptc; /* Test column enable input */
+ u32 ptm; /* Test mode enable input */
+ u32 ptm_rep;/* Repair function test mode enable input */
+ u32 ptr; /* Test row enable input */
+ u32 ptrim; /* Repair function enable input */
+ u32 pwe; /* Write enable input (defines program cycle) */
+} __packed;
+
+#define BYTES_PER_FUSE 4
+#define NUM_FUSES 0x1000
+
+static int fu540_otp_read(int offset, void *buf, int size)
+{
+ struct fu540_otp_regs *regs = (void __iomem *)FU540_OTP_BASE_ADDR;
+ unsigned int i;
+ int fuseidx = offset / BYTES_PER_FUSE;
+ int fusecount = size / BYTES_PER_FUSE;
+ u32 fusebuf[fusecount];
+
+ /* check bounds */
+ if (offset < 0 || size < 0)
+ return -EINVAL;
+ if (fuseidx >= NUM_FUSES)
+ return -EINVAL;
+ if ((fuseidx + fusecount) > NUM_FUSES)
+ return -EINVAL;
+
+ /* init OTP */
+ writel(0x01, ®s->pdstb); /* wake up from stand-by */
+ writel(0x01, ®s->ptrim); /* enable repair function */
+ writel(0x01, ®s->pce); /* enable input */
+
+ /* read all requested fuses */
+ for (i = 0; i < fusecount; i++, fuseidx++) {
+ writel(fuseidx, ®s->pa);
+
+ /* cycle clock to read */
+ writel(0x01, ®s->pclk);
+ mdelay(1);
+ writel(0x00, ®s->pclk);
+ mdelay(1);
+
+ /* read the value */
+ fusebuf[i] = readl(®s->pdout);
+ }
+
+ /* shut down */
+ writel(0, ®s->pce);
+ writel(0, ®s->ptrim);
+ writel(0, ®s->pdstb);
+
+ /* copy out */
+ memcpy(buf, fusebuf, size);
+
+ return 0;
+}
+
+static u32 fu540_read_serialnum(void)
+{
+ int ret;
+ u32 serial[2] = {0};
+
+ for (int i = 0xfe * 4; i > 0; i -= 8) {
+ ret = fu540_otp_read(i, serial, sizeof(serial));
+ if (ret) {
+ printf("%s: error reading from OTP\n", __func__);
+ break;
+ }
+ if (serial[0] == ~serial[1])
+ return serial[0];
+ }
+
+ return 0;
+}
+
+static void fu540_setup_macaddr(u32 serialnum)
+{
+ /* Default MAC address */
+ unsigned char mac[6] = { 0x70, 0xb3, 0xd5, 0x92, 0xf0, 0x00 };
+
+ /*
+ * We derive our board MAC address by ORing last three bytes
+ * of board serial number to above default MAC address.
+ *
+ * This logic of deriving board MAC address is taken from
+ * SiFive FSBL and is kept unchanged.
+ */
+ mac[5] |= (serialnum >> 0) & 0xff;
+ mac[4] |= (serialnum >> 8) & 0xff;
+ mac[3] |= (serialnum >> 16) & 0xff;
+
+ /* Update environment variable */
+ eth_env_set_enetaddr("ethaddr", mac);
+}
+
+int misc_init_r(void)
+{
+ u32 serial_num;
+ char buf[9] = {0};
+
+ /* Set ethaddr environment variable from board serial number */
+ if (!env_get("serial#")) {
+ serial_num = fu540_read_serialnum();
+ if (!serial_num) {
+ WARN(true, "Board serial number should not be 0 !!\n");
+ return 0;
+ }
+ snprintf(buf, sizeof(buf), "%08x", serial_num);
+ env_set("serial#", buf);
+ fu540_setup_macaddr(serial_num);
+ }
+ return 0;
+}
+
+#endif
int board_init(void)
{
diff --git a/board/silica/pengwyn/board.c b/board/silica/pengwyn/board.c
index 90ea8c6..345701f 100644
--- a/board/silica/pengwyn/board.c
+++ b/board/silica/pengwyn/board.c
@@ -6,7 +6,7 @@
*/
#include <common.h>
-#include <environment.h>
+#include <env.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/ddr_defs.h>
diff --git a/board/sks-kinkel/sksimx6/sksimx6.c b/board/sks-kinkel/sksimx6/sksimx6.c
index f6e3d4d..59a07a9 100644
--- a/board/sks-kinkel/sksimx6/sksimx6.c
+++ b/board/sks-kinkel/sksimx6/sksimx6.c
@@ -12,7 +12,7 @@
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/video.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c
index ff465a8..da9ae5b 100644
--- a/board/socrates/socrates.c
+++ b/board/socrates/socrates.c
@@ -11,6 +11,7 @@
*/
#include <common.h>
+#include <env.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
diff --git a/board/softing/vining_2000/vining_2000.c b/board/softing/vining_2000/vining_2000.c
index 19b9b37..51985b9 100644
--- a/board/softing/vining_2000/vining_2000.c
+++ b/board/softing/vining_2000/vining_2000.c
@@ -16,10 +16,10 @@
#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
#include <asm/mach-imx/mxc_i2c.h>
+#include <env.h>
#include <linux/sizes.h>
#include <common.h>
-#include <environment.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <mmc.h>
#include <i2c.h>
#include <miiphy.h>
diff --git a/board/solidrun/clearfog/README b/board/solidrun/clearfog/README
index 0b0e98d..6171ce6 100644
--- a/board/solidrun/clearfog/README
+++ b/board/solidrun/clearfog/README
@@ -40,6 +40,12 @@
Note that the SD card is not accessible when the Clearfog SOM has eMMC.
Consider initial boot from UART (see below).
+Install U-Boot on SATA:
+-----------------------
+
+When loading the main U-Boot image from raw SATA sector, set
+CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR to 0x141.
+
Boot selection:
---------------
diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index cf63427..f82fb07 100644
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -18,13 +18,14 @@
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/mxc_hdmi.h>
+#include <env.h>
#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/sata.h>
#include <asm/mach-imx/video.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <malloc.h>
#include <miiphy.h>
#include <netdev.h>
diff --git a/board/st/stm32f429-discovery/led.c b/board/st/stm32f429-discovery/led.c
index 8320ad4..ae6df78 100644
--- a/board/st/stm32f429-discovery/led.c
+++ b/board/st/stm32f429-discovery/led.c
@@ -9,7 +9,9 @@
void coloured_LED_init(void)
{
+ gpio_request(CONFIG_RED_LED, "red led");
gpio_direction_output(CONFIG_RED_LED, 0);
+ gpio_request(CONFIG_GREEN_LED, "green led");
gpio_direction_output(CONFIG_GREEN_LED, 0);
}
diff --git a/board/st/stm32mp1/Kconfig b/board/st/stm32mp1/Kconfig
index 5ab9415..4fa2360 100644
--- a/board/st/stm32mp1/Kconfig
+++ b/board/st/stm32mp1/Kconfig
@@ -9,4 +9,21 @@
config SYS_CONFIG_NAME
default "stm32mp1"
+config ENV_SECT_SIZE
+ default 0x40000 if ENV_IS_IN_SPI_FLASH
+
+config ENV_OFFSET
+ default 0x280000 if ENV_IS_IN_SPI_FLASH
+
+config CMD_STBOARD
+ bool "stboard - command for OTP board information"
+ default y
+ help
+ This compile the stboard command to
+ read and write the board in the OTP.
+
+config TARGET_STM32MP157C_DK2
+ bool "support of STMicroelectronics STM32MP157C-DK2 Discovery Board"
+ default y
+
endif
diff --git a/board/st/stm32mp1/MAINTAINERS b/board/st/stm32mp1/MAINTAINERS
index 0a2eddb..2930947 100644
--- a/board/st/stm32mp1/MAINTAINERS
+++ b/board/st/stm32mp1/MAINTAINERS
@@ -1,9 +1,11 @@
STM32MP1 BOARD
M: Patrick Delaunay <patrick.delaunay@st.com>
L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers)
+T: git https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git
S: Maintained
-F: arch/arm/dts/stm32mp157*
-F: board/st/stm32mp1
+F: arch/arm/dts/stm32mp15*
+F: board/st/stm32mp1/
F: configs/stm32mp15_basic_defconfig
+F: configs/stm32mp15_optee_defconfig
F: configs/stm32mp15_trusted_defconfig
F: include/configs/stm32mp1.h
diff --git a/board/st/stm32mp1/Makefile b/board/st/stm32mp1/Makefile
index 8188075..3c6c035 100644
--- a/board/st/stm32mp1/Makefile
+++ b/board/st/stm32mp1/Makefile
@@ -7,6 +7,7 @@
obj-y += spl.o
else
obj-y += stm32mp1.o
+obj-$(CONFIG_CMD_STBOARD) += cmd_stboard.o
endif
obj-y += board.o
diff --git a/board/st/stm32mp1/README b/board/st/stm32mp1/README
index b0c8325..c807e08 100644
--- a/board/st/stm32mp1/README
+++ b/board/st/stm32mp1/README
@@ -25,6 +25,10 @@
Everything is supported in Linux but U-Boot is limited to:
1. UART
2. SDCard/MMC controller (SDMMC)
+3. NAND controller (FMC)
+4. NOR controller (QSPI)
+5. USB controller (OTG DWC2)
+6. Ethernet controller
And the necessary drivers
1. I2C
@@ -47,20 +51,28 @@
with FSBL = First Stage Bootloader
SSBL = Second Stage Bootloader
-2 boot configurations are supported:
+3 boot configurations are supported:
1) The "Trusted" boot chain (defconfig_file : stm32mp15_trusted_defconfig)
BootRom => FSBL = Trusted Firmware-A (TF-A) => SSBL = U-Boot
TF-A performs a full initialization of Secure peripherals and installs a
secure monitor.
U-Boot is running in normal world and uses TF-A monitor
- to access to secure resources
+ to access to secure resources.
-2) The "Basic" boot chain (defconfig_file : stm32mp15_basic_defconfig)
+2) The "Trusted" boot chain with OP-TEE
+ (defconfig_file : stm32mp15_optee_defconfig)
+ BootRom => FSBL = Trusted Firmware-A (TF-A) => SSBL = U-Boot
+ TF-A performs a full initialization of Secure peripherals and installs OP-TEE
+ from specific partitions (teeh, teed, teex).
+ U-Boot is running in normal world and uses OP-TEE monitor to access
+ to secure resources.
+
+3) The "Basic" boot chain (defconfig_file : stm32mp15_basic_defconfig)
BootRom => FSBL = U-Boot SPL => SSBL = U-Boot
SPL has limited security initialisation
U-Boot is running in secure mode and provide a secure monitor to the kernel
- with only PSCI support (Power State Coordination Interface defined by ARM)
+ with only PSCI support (Power State Coordination Interface defined by ARM).
All the STM32MP1 boards supported by U-Boot use the same generic board
stm32mp1 which support all the bootable devices.
@@ -109,42 +121,51 @@
for example: use one output directory for each configuration
# export KBUILD_OUTPUT=stm32mp15_trusted
+ # export KBUILD_OUTPUT=stm32mp15_optee
# export KBUILD_OUTPUT=stm32mp15_basic
+ you can build outside of code directory:
+ # export KBUILD_OUTPUT=../build/stm32mp15_trusted
+
4. Configure U-Boot:
# make <defconfig_file>
- For trusted boot mode : "stm32mp15_trusted_defconfig"
+ - For trusted with OP-TEE boot mode : "stm32mp15_optee_defconfig"
- For basic boot mode: "stm32mp15_basic_defconfig"
5. Configure the device-tree and build the U-Boot image:
# make DEVICE_TREE=<name> all
-
example:
a) trusted boot on ev1
# export KBUILD_OUTPUT=stm32mp15_trusted
# make stm32mp15_trusted_defconfig
# make DEVICE_TREE=stm32mp157c-ev1 all
- b) basic boot on ev1
+ b) trusted with OP-TEE boot on dk2
+ # export KBUILD_OUTPUT=stm32mp15_optee
+ # make stm32mp15_optee_defconfig
+ # make DEVICE_TREE=stm32mp157c-dk2 all
+
+ c) basic boot on ev1
# export KBUILD_OUTPUT=stm32mp15_basic
# make stm32mp15_basic_defconfig
# make DEVICE_TREE=stm32mp157c-ev1 all
- c) basic boot on ed1
+ d) basic boot on ed1
# export KBUILD_OUTPUT=stm32mp15_basic
# make stm32mp15_basic_defconfig
# make DEVICE_TREE=stm32mp157c-ed1 all
- d) basic boot on dk2
+ e) basic boot on dk1
# export KBUILD_OUTPUT=stm32mp15_basic
# make stm32mp15_basic_defconfig
- # make DEVICE_TREE=stm32mp157c-dk2 all
+ # make DEVICE_TREE=stm32mp157a-dk1 all
- d) basic boot on avenger96
+ f) basic boot on avenger96
# export KBUILD_OUTPUT=stm32mp15_basic
# make stm32mp15_basic_defconfig
# make DEVICE_TREE=stm32mp157a-avenger96 all
@@ -157,7 +178,7 @@
So in the output directory (selected by KBUILD_OUTPUT),
you can found the needed files:
- a) For Trusted boot
+ a) For Trusted boot (with or without OP-TEE)
+ FSBL = tf-a.stm32 (provided by TF-A compilation)
+ SSBL = u-boot.stm32
@@ -168,7 +189,9 @@
6. Switch Setting for Boot Mode
===============================
-You can select the boot mode, on the board ed1 with the switch SW1
+You can select the boot mode, on the board with one switch :
+
+- on the daugther board ed1 with the switch SW1 : BOOT0, BOOT1, BOOT2
-----------------------------------
Boot Mode BOOT2 BOOT1 BOOT0
@@ -267,7 +290,7 @@
# dd if=tf-a.stm32 of=/dev/mmcblk0p2
# dd if=u-boot.stm32 of=/dev/mmcblk0p3
-To boot from SDCard, select BootPinMode = 1 1 1 and reset.
+To boot from SDCard, select BootPinMode = 1 0 1 and reset.
8. Prepare eMMC
===============
@@ -334,3 +357,36 @@
4 check env update
STM32MP> print ethaddr
ethaddr=12:34:56:78:9a:bc
+
+10. Coprocessor firmware
+========================
+
+U-Boot can boot the coprocessor before the kernel (coprocessor early boot).
+
+A/ Manuallly by using rproc commands (update the bootcmd)
+ Configurations
+ # env set name_copro "rproc-m4-fw.elf"
+ # env set dev_copro 0
+ # env set loadaddr_copro 0xC1000000
+
+ Load binary from bootfs partition (number 4) on SDCard (mmc 0)
+ # ext4load mmc 0:4 ${loadaddr_copro} ${name_copro}
+ => ${filesize} updated with the size of the loaded file
+
+ Start M4 firmware with remote proc command
+ # rproc init
+ # rproc load ${dev_copro} ${loadaddr_copro} ${filesize}
+ # rproc start ${dev_copro}
+
+B/ Automatically by using FIT feature and generic DISTRO bootcmd
+
+ see examples in this directory :
+
+ Generate FIT including kernel + device tree + M4 firmware
+ with cfg with M4 boot
+ $> mkimage -f fit_copro_kernel_dtb.its fit_copro_kernel_dtb.itb
+
+ Then using DISTRO configuration file: see extlinux.conf to select
+ the correct configuration
+ => stm32mp157c-ev1-m4
+ => stm32mp157c-dk2-m4
diff --git a/board/st/stm32mp1/cmd_stboard.c b/board/st/stm32mp1/cmd_stboard.c
new file mode 100644
index 0000000..04352ae
--- /dev/null
+++ b/board/st/stm32mp1/cmd_stboard.c
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
+ */
+
+#include <common.h>
+#include <console.h>
+#include <misc.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+
+static bool check_stboard(u16 board)
+{
+ unsigned int i;
+ const u16 st_board_id[] = {
+ 0x1272,
+ 0x1263,
+ 0x1264,
+ 0x1298,
+ 0x1341,
+ 0x1497,
+ };
+
+ for (i = 0; i < ARRAY_SIZE(st_board_id); i++)
+ if (board == st_board_id[i])
+ return true;
+
+ return false;
+}
+
+static void display_stboard(u32 otp)
+{
+ printf("Board: MB%04x Var%d Rev.%c-%02d\n",
+ otp >> 16,
+ (otp >> 12) & 0xF,
+ ((otp >> 8) & 0xF) - 1 + 'A',
+ otp & 0xF);
+}
+
+static int do_stboard(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ int ret;
+ u32 otp;
+ u8 revision;
+ unsigned long board, variant, bom;
+ struct udevice *dev;
+ int confirmed = argc == 6 && !strcmp(argv[1], "-y");
+
+ argc -= 1 + confirmed;
+ argv += 1 + confirmed;
+
+ if (argc != 0 && argc != 4)
+ return CMD_RET_USAGE;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_GET_DRIVER(stm32mp_bsec),
+ &dev);
+
+ ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_BOARD),
+ &otp, sizeof(otp));
+
+ if (ret < 0) {
+ puts("OTP read error");
+ return CMD_RET_FAILURE;
+ }
+
+ if (argc == 0) {
+ if (!otp)
+ puts("Board : OTP board FREE\n");
+ else
+ display_stboard(otp);
+ return CMD_RET_SUCCESS;
+ }
+
+ if (otp) {
+ display_stboard(otp);
+ printf("ERROR: OTP board not FREE\n");
+ return CMD_RET_FAILURE;
+ }
+
+ if (strict_strtoul(argv[0], 16, &board) < 0 ||
+ board == 0 || board > 0xFFFF) {
+ printf("argument %d invalid: %s\n", 1, argv[0]);
+ return CMD_RET_USAGE;
+ }
+
+ if (strict_strtoul(argv[1], 10, &variant) < 0 ||
+ variant == 0 || variant > 15) {
+ printf("argument %d invalid: %s\n", 2, argv[1]);
+ return CMD_RET_USAGE;
+ }
+
+ revision = argv[2][0] - 'A' + 1;
+ if (strlen(argv[2]) > 1 || revision == 0 || revision > 15) {
+ printf("argument %d invalid: %s\n", 3, argv[2]);
+ return CMD_RET_USAGE;
+ }
+
+ if (strict_strtoul(argv[3], 10, &bom) < 0 ||
+ bom == 0 || bom > 15) {
+ printf("argument %d invalid: %s\n", 4, argv[3]);
+ return CMD_RET_USAGE;
+ }
+
+ otp = (board << 16) | (variant << 12) | (revision << 8) | bom;
+ display_stboard(otp);
+ printf("=> OTP[%d] = %08X\n", BSEC_OTP_BOARD, otp);
+
+ if (!check_stboard((u16)board)) {
+ printf("Unknown board MB%04x\n", (u16)board);
+ return CMD_RET_FAILURE;
+ }
+ if (!confirmed) {
+ printf("Warning: Programming BOARD in OTP is irreversible!\n");
+ printf("Really perform this OTP programming? <y/N>\n");
+
+ if (!confirm_yesno()) {
+ puts("BOARD programming aborted\n");
+ return CMD_RET_FAILURE;
+ }
+ }
+
+ ret = misc_write(dev, STM32_BSEC_OTP(BSEC_OTP_BOARD),
+ &otp, sizeof(otp));
+
+ if (ret) {
+ puts("BOARD programming error\n");
+ return CMD_RET_FAILURE;
+ }
+ puts("BOARD programming done\n");
+
+ return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(stboard, 6, 0, do_stboard,
+ "read/write board reference in OTP",
+ "\n"
+ " Print current board information\n"
+ "stboard [-y] <Board> <Variant> <Revision> <BOM>\n"
+ " Write board information\n"
+ " - Board: xxxx, example 1264 for MB1264\n"
+ " - Variant: 1 ... 15\n"
+ " - Revision: A...O\n"
+ " - BOM: 1...15\n");
diff --git a/board/st/stm32mp1/extlinux.conf b/board/st/stm32mp1/extlinux.conf
new file mode 100644
index 0000000..2b46328
--- /dev/null
+++ b/board/st/stm32mp1/extlinux.conf
@@ -0,0 +1,20 @@
+# Generic Distro Configuration for STM32MP157
+menu title Select the boot mode
+TIMEOUT 20
+DEFAULT stm32mp157c-ev1
+
+LABEL stm32mp157c-ev1
+ KERNEL /fit_kernel_dtb.itb#ev1
+ APPEND root=/dev/mmcblk0p6 rootwait rw earlyprintk console=ttyS3,115200
+
+LABEL stm32mp157c-ev1-m4
+ KERNEL /fit_copro_kernel_dtb.itb#ev1-m4
+ APPEND root=/dev/mmcblk0p6 rootwait rw earlyprintk console=ttyS3,115200
+
+LABEL stm32mp157c-dk2
+ KERNEL /fit_kernel_dtb.itb#dk2
+ APPEND root=/dev/mmcblk0p6 rootwait rw earlyprintk console=ttyS3,115200
+
+LABEL stm32mp157c-dk2-m4
+ KERNEL /fit_copro_kernel_dtb.itb#dk2-m4
+ APPEND root=/dev/mmcblk0p6 rootwait rw earlyprintk console=ttyS3,115200
diff --git a/board/st/stm32mp1/fit_copro_kernel_dtb.its b/board/st/stm32mp1/fit_copro_kernel_dtb.its
new file mode 100644
index 0000000..3e08fd9
--- /dev/null
+++ b/board/st/stm32mp1/fit_copro_kernel_dtb.its
@@ -0,0 +1,103 @@
+/*
+ * Compilation:
+ * mkimage -f fit_copro_kernel_dtb.its fit_copro_kernel_dtb.itb
+ */
+
+/dts-v1/;
+/ {
+ description = "U-Boot fitImage for stm32mp157";
+ #address-cells = <1>;
+
+ images {
+
+ copro {
+ description = "M4 copro";
+ data = /incbin/("rproc-m4-fw.elf");
+ type = "copro";
+ arch = "arm";
+ compression = "none";
+ load = <0xC0800000>;
+ hash-1 {
+ algo = "sha1";
+ };
+ };
+
+ kernel {
+ description = "Linux kernel";
+ data = /incbin/("zImage");
+ type = "kernel";
+ arch = "arm";
+ os = "linux";
+ compression = "none";
+ load = <0xC0008000>;
+ entry = <0xC0008000>;
+ hash-1 {
+ algo = "sha1";
+ };
+ };
+
+ fdt-dk2 {
+ description = "FDT dk2";
+ data = /incbin/("stm32mp157c-dk2.dtb");
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ hash-1 {
+ algo = "sha1";
+ };
+ };
+
+ fdt-ev1 {
+ description = "FDT ev1";
+ data = /incbin/("stm32mp157c-ev1.dtb");
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ hash-1 {
+ algo = "sha1";
+ };
+ };
+ };
+
+ configurations {
+ default = "dk2-m4";
+
+ dk2-m4 {
+ description = "dk2-m4";
+ loadables = "copro";
+ kernel = "kernel";
+ fdt = "fdt-dk2";
+ hash-1 {
+ algo = "sha1";
+ };
+ };
+
+ dk2 {
+ description = "dk2";
+ kernel = "kernel";
+ fdt = "fdt-dk2";
+ hash-1 {
+ algo = "sha1";
+ };
+ };
+
+ ev1-m4 {
+ description = "ev1-m4";
+ loadables = "copro";
+ kernel = "kernel";
+ fdt = "fdt-ev1";
+ hash-1 {
+ algo = "sha1";
+ };
+ };
+
+ ev1 {
+ description = "ev1";
+ kernel = "kernel";
+ fdt = "fdt-ev1";
+ hash-1 {
+ algo = "sha1";
+ };
+ };
+ };
+};
diff --git a/board/st/stm32mp1/fit_kernel_dtb.its b/board/st/stm32mp1/fit_kernel_dtb.its
new file mode 100644
index 0000000..18d03eb
--- /dev/null
+++ b/board/st/stm32mp1/fit_kernel_dtb.its
@@ -0,0 +1,82 @@
+/*
+ * Compilation:
+ * mkimage -f fit_kernel_dtb.its fit_kernel_dtb.itb
+ *
+ * Files in linux build dir:
+ * - arch/arm/boot/zImage
+ * - arch/arm/boot/dts/stm32mp157c-dk2.dtb
+ * - arch/arm/boot/dts/stm32mp157c-ev1.dtb
+ *
+ * load mmc 0:4 $kernel_addr_r fit_kernel_dtb.itb
+ * bootm $kernel_addr_r
+ * bootm $kernel_addr_r#dk2
+ * bootm $kernel_addr_r#ev1
+ *
+ * or use extlinux.conf in this directory
+ */
+
+/dts-v1/;
+/ {
+ description = "U-Boot fitImage for stm32mp157";
+ #address-cells = <1>;
+
+ images {
+ kernel {
+ description = "Linux kernel";
+ data = /incbin/("zImage");
+ type = "kernel";
+ arch = "arm";
+ os = "linux";
+ compression = "none";
+ load = <0xC0008000>;
+ entry = <0xC0008000>;
+ hash-1 {
+ algo = "sha1";
+ };
+ };
+
+ fdt-dk2 {
+ description = "FDT dk2";
+ data = /incbin/("stm32mp157c-dk2.dtb");
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ hash-1 {
+ algo = "sha1";
+ };
+ };
+
+ fdt-ev1 {
+ description = "FDT ev1";
+ data = /incbin/("stm32mp157c-ev1.dtb");
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ hash-1 {
+ algo = "sha1";
+ };
+ };
+ };
+
+ configurations {
+ default = "dk2";
+
+ dk2 {
+ description = "dk2";
+ kernel = "kernel";
+ fdt = "fdt-dk2";
+ hash-1 {
+ algo = "sha1";
+ };
+ };
+
+ ev1 {
+ description = "ev1";
+ kernel = "kernel";
+ fdt = "fdt-ev1";
+ hash-1 {
+ algo = "sha1";
+ };
+ };
+ };
+};
diff --git a/board/st/stm32mp1/spl.c b/board/st/stm32mp1/spl.c
index a7844f2..e65ff28 100644
--- a/board/st/stm32mp1/spl.c
+++ b/board/st/stm32mp1/spl.c
@@ -9,7 +9,6 @@
#include <dm.h>
#include <ram.h>
#include <asm/io.h>
-#include <post.h>
#include <power/pmic.h>
#include <power/stpmic1.h>
#include <asm/arch/ddr.h>
@@ -28,5 +27,19 @@
STPMIC1_BUCKS_MRST_CR,
STPMIC1_MRST_BUCK(STPMIC1_BUCK3),
STPMIC1_MRST_BUCK(STPMIC1_BUCK3));
+
+ /* Check if debug is enabled to program PMIC according to the bit */
+ if ((readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_DEBUG_ON) && !ret) {
+ printf("Keep debug unit ON\n");
+
+ pmic_clrsetbits(dev, STPMIC1_BUCKS_MRST_CR,
+ STPMIC1_MRST_BUCK_DEBUG,
+ STPMIC1_MRST_BUCK_DEBUG);
+
+ if (STPMIC1_MRST_LDO_DEBUG)
+ pmic_clrsetbits(dev, STPMIC1_LDOS_MRST_CR,
+ STPMIC1_MRST_LDO_DEBUG,
+ STPMIC1_MRST_LDO_DEBUG);
+ }
#endif
}
diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
index 7769293..18f9b84 100644
--- a/board/st/stm32mp1/stm32mp1.c
+++ b/board/st/stm32mp1/stm32mp1.c
@@ -4,23 +4,31 @@
*/
#include <common.h>
#include <adc.h>
-#include <config.h>
+#include <bootm.h>
#include <clk.h>
+#include <config.h>
#include <dm.h>
-#include <environment.h>
+#include <env.h>
+#include <env_internal.h>
#include <g_dnl.h>
#include <generic-phy.h>
#include <i2c.h>
#include <led.h>
#include <misc.h>
+#include <mtd.h>
+#include <mtd_node.h>
+#include <netdev.h>
#include <phy.h>
+#include <remoteproc.h>
#include <reset.h>
#include <syscon.h>
#include <usb.h>
+#include <watchdog.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/stm32.h>
#include <asm/arch/sys_proto.h>
+#include <jffs2/load_kernel.h>
#include <power/regulator.h>
#include <usb/dwc2_udc.h>
@@ -76,7 +84,9 @@
const char *fdt_compat;
int fdt_compat_len;
- if (IS_ENABLED(CONFIG_STM32MP1_TRUSTED))
+ if (IS_ENABLED(CONFIG_STM32MP1_OPTEE))
+ mode = "trusted with OP-TEE";
+ else if (IS_ENABLED(CONFIG_STM32MP1_TRUSTED))
mode = "trusted";
else
mode = "basic";
@@ -95,7 +105,7 @@
if (!ret)
ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_BOARD),
&otp, sizeof(otp));
- if (!ret && otp) {
+ if (ret > 0 && otp) {
printf("Board: MB%04x Var%d Rev.%c-%02d\n",
otp >> 16,
(otp >> 12) & 0xF,
@@ -225,6 +235,7 @@
}
#endif /* CONFIG_USB_GADGET */
+#ifdef CONFIG_LED
static int get_led(struct udevice **dev, char *led_string)
{
char *led_name;
@@ -257,12 +268,42 @@
ret = led_set_state(dev, cmd);
return ret;
}
+#endif
+static void __maybe_unused led_error_blink(u32 nb_blink)
+{
+#ifdef CONFIG_LED
+ int ret;
+ struct udevice *led;
+ u32 i;
+#endif
+
+ if (!nb_blink)
+ return;
+
+#ifdef CONFIG_LED
+ ret = get_led(&led, "u-boot,error-led");
+ if (!ret) {
+ /* make u-boot,error-led blinking */
+ /* if U32_MAX and 125ms interval, for 17.02 years */
+ for (i = 0; i < 2 * nb_blink; i++) {
+ led_set_state(led, LEDST_TOGGLE);
+ mdelay(125);
+ WATCHDOG_RESET();
+ }
+ }
+#endif
+
+ /* infinite: the boot process must be stopped */
+ if (nb_blink == U32_MAX)
+ hang();
+}
+
+#ifdef CONFIG_ADC
static int board_check_usb_power(void)
{
struct ofnode_phandle_args adc_args;
struct udevice *adc;
- struct udevice *led;
ofnode node;
unsigned int raw;
int max_uV = 0;
@@ -388,23 +429,11 @@
pr_err("****************************************************\n\n");
}
- ret = get_led(&led, "u-boot,error-led");
- if (ret) {
- /* in unattached case, the boot process must be stopped */
- if (nb_blink == U32_MAX)
- hang();
- return ret;
- }
-
- /* make u-boot,error-led blinking */
- for (i = 0; i < nb_blink * 2; i++) {
- led_set_state(led, LEDST_TOGGLE);
- mdelay(125);
- }
- led_set_state(led, LEDST_ON);
+ led_error_blink(nb_blink);
return 0;
}
+#endif /* CONFIG_ADC */
static void sysconf_init(void)
{
@@ -447,7 +476,9 @@
* => U-Boot set the register only if VDD < 2.7V (in DT)
* but this value need to be consistent with board design
*/
- ret = syscon_get_by_driver_data(STM32MP_SYSCON_PWR, &pwr_dev);
+ ret = uclass_get_device_by_driver(UCLASS_PMIC,
+ DM_GET_DRIVER(stm32mp_pwr_pmic),
+ &pwr_dev);
if (!ret) {
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_GET_DRIVER(stm32mp_bsec),
@@ -458,11 +489,11 @@
}
ret = misc_read(dev, STM32_BSEC_SHADOW(18), &otp, 4);
- if (!ret)
+ if (ret > 0)
otp = otp & BIT(13);
- /* get VDD = pwr-supply */
- ret = device_get_supply_regulator(pwr_dev, "pwr-supply",
+ /* get VDD = vdd-supply */
+ ret = device_get_supply_regulator(pwr_dev, "vdd-supply",
&pwr_reg);
/* check if VDD is Low Voltage */
@@ -498,6 +529,73 @@
#endif
}
+#ifdef CONFIG_DM_REGULATOR
+/* Fix to make I2C1 usable on DK2 for touchscreen usage in kernel */
+static int dk2_i2c1_fix(void)
+{
+ ofnode node;
+ struct gpio_desc hdmi, audio;
+ int ret = 0;
+
+ node = ofnode_path("/soc/i2c@40012000/hdmi-transmitter@39");
+ if (!ofnode_valid(node)) {
+ pr_debug("%s: no hdmi-transmitter@39 ?\n", __func__);
+ return -ENOENT;
+ }
+
+ if (gpio_request_by_name_nodev(node, "reset-gpios", 0,
+ &hdmi, GPIOD_IS_OUT)) {
+ pr_debug("%s: could not find reset-gpios\n",
+ __func__);
+ return -ENOENT;
+ }
+
+ node = ofnode_path("/soc/i2c@40012000/cs42l51@4a");
+ if (!ofnode_valid(node)) {
+ pr_debug("%s: no cs42l51@4a ?\n", __func__);
+ return -ENOENT;
+ }
+
+ if (gpio_request_by_name_nodev(node, "reset-gpios", 0,
+ &audio, GPIOD_IS_OUT)) {
+ pr_debug("%s: could not find reset-gpios\n",
+ __func__);
+ return -ENOENT;
+ }
+
+ /* before power up, insure that HDMI and AUDIO IC is under reset */
+ ret = dm_gpio_set_value(&hdmi, 1);
+ if (ret) {
+ pr_err("%s: can't set_value for hdmi_nrst gpio", __func__);
+ goto error;
+ }
+ ret = dm_gpio_set_value(&audio, 1);
+ if (ret) {
+ pr_err("%s: can't set_value for audio_nrst gpio", __func__);
+ goto error;
+ }
+
+ /* power-up audio IC */
+ regulator_autoset_by_name("v1v8_audio", NULL);
+
+ /* power-up HDMI IC */
+ regulator_autoset_by_name("v1v2_hdmi", NULL);
+ regulator_autoset_by_name("v3v3_hdmi", NULL);
+
+error:
+ return ret;
+}
+
+static bool board_is_dk2(void)
+{
+ if (CONFIG_IS_ENABLED(TARGET_STM32MP157C_DK2) &&
+ of_machine_is_compatible("st,stm32mp157c-dk2"))
+ return true;
+
+ return false;
+}
+#endif
+
/* board dependent setup after realloc */
int board_init(void)
{
@@ -515,9 +613,16 @@
board_key_check();
+#ifdef CONFIG_DM_REGULATOR
+ if (board_is_dk2())
+ dk2_i2c1_fix();
+
+ regulators_enable_boot_on(_DEBUG);
+#endif
+
sysconf_init();
- if (IS_ENABLED(CONFIG_LED))
+ if (CONFIG_IS_ENABLED(CONFIG_LED))
led_default_state();
return 0;
@@ -525,9 +630,14 @@
int board_late_init(void)
{
+ char *boot_device;
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
const void *fdt_compat;
int fdt_compat_len;
+ int ret;
+ u32 otp;
+ struct udevice *dev;
+ char buf[10];
fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
&fdt_compat_len);
@@ -537,26 +647,58 @@
else
env_set("board_name", fdt_compat + 3);
}
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_GET_DRIVER(stm32mp_bsec),
+ &dev);
+
+ if (!ret)
+ ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_BOARD),
+ &otp, sizeof(otp));
+ if (!ret && otp) {
+ snprintf(buf, sizeof(buf), "0x%04x", otp >> 16);
+ env_set("board_id", buf);
+
+ snprintf(buf, sizeof(buf), "0x%04x",
+ ((otp >> 8) & 0xF) - 1 + 0xA);
+ env_set("board_rev", buf);
+ }
#endif
+#ifdef CONFIG_ADC
/* for DK1/DK2 boards */
board_check_usb_power();
+#endif /* CONFIG_ADC */
+
+ /* Check the boot-source to disable bootdelay */
+ boot_device = env_get("boot_device");
+ if (!strcmp(boot_device, "serial") || !strcmp(boot_device, "usb"))
+ env_set("bootdelay", "0");
return 0;
}
void board_quiesce_devices(void)
{
+#ifdef CONFIG_LED
setup_led(LEDST_OFF);
+#endif
}
-/* board interface eth init */
-/* this is a weak define that we are overriding */
-int board_interface_eth_init(phy_interface_t interface_type,
- bool eth_clk_sel_reg, bool eth_ref_clk_sel_reg)
+/* eth init function : weak called in eqos driver */
+int board_interface_eth_init(struct udevice *dev,
+ phy_interface_t interface_type)
{
u8 *syscfg;
u32 value;
+ bool eth_clk_sel_reg = false;
+ bool eth_ref_clk_sel_reg = false;
+
+ /* Gigabit Ethernet 125MHz clock selection. */
+ eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel");
+
+ /* Ethernet 50Mhz RMII clock selection */
+ eth_ref_clk_sel_reg =
+ dev_read_bool(dev, "st,eth_ref_clk_sel");
syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
@@ -745,3 +887,41 @@
debug("%s:mtdids=%s & mtdparts=%s\n", __func__, ids, parts);
}
#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+ struct node_info nodes[] = {
+ { "st,stm32f469-qspi", MTD_DEV_TYPE_NOR, },
+ { "st,stm32mp15-fmc2", MTD_DEV_TYPE_NAND, },
+ };
+ fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+#endif
+
+ return 0;
+}
+#endif
+
+static void board_copro_image_process(ulong fw_image, size_t fw_size)
+{
+ int ret, id = 0; /* Copro id fixed to 0 as only one coproc on mp1 */
+
+ if (!rproc_is_initialized())
+ if (rproc_init()) {
+ printf("Remote Processor %d initialization failed\n",
+ id);
+ return;
+ }
+
+ ret = rproc_load(id, fw_image, fw_size);
+ printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
+ id, fw_image, fw_size, ret ? " Failed!" : " Success!");
+
+ if (!ret) {
+ rproc_start(id);
+ env_set("copro_state", "booted");
+ }
+}
+
+U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_COPRO, board_copro_image_process);
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index bdd1854..88f1353 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -151,7 +151,7 @@
F: arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts
BANANAPI M2 MAGIC BOARD
-M: Maxime Ripard <maxime.ripard@bootlin.com>
+M: Maxime Ripard <mripard@kernel.org>
S: Maintained
F: configs/Bananapi_m2m_defconfig
F: arch/arm/dts/sun8i-r16-bananapi-m2m.dts
@@ -172,8 +172,14 @@
F: configs/beelink_gs1_defconfig
F: arch/arm/dts/sun50i-h6-beelink-gs1.dts
+BEELINK X2 BOARD
+M: Marcus Cooper <codekipper@gmail.com>
+S: Maintained
+F: configs/beelink_x2_defconfig
+F: arch/arm/dts/sun8i-h3-beelink-x2.dts
+
COLOMBUS BOARD
-M: Maxime Ripard <maxime.ripard@bootlin.com>
+M: Maxime Ripard <mripard@kernel.org>
S: Maintained
F: configs/Colombus_defconfig
@@ -459,7 +465,7 @@
W: https://linux-sunxi.org/Sunchip_CX-A99
TBS A711 BOARD
-M: Maxime Ripard <maxime.ripard@bootlin.com>
+M: Maxime Ripard <mripard@kernel.org>
S: Maintained
F: configs/tbs_a711_defconfig
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 98bc3cd..e3b2d13 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -12,6 +12,7 @@
#include <common.h>
#include <dm.h>
+#include <env.h>
#include <mmc.h>
#include <axp_pmic.h>
#include <generic-phy.h>
@@ -29,7 +30,7 @@
#include <asm/gpio.h>
#include <asm/io.h>
#include <u-boot/crc.h>
-#include <environment.h>
+#include <env_internal.h>
#include <linux/libfdt.h>
#include <nand.h>
#include <net.h>
diff --git a/board/synopsys/emsdp/config.mk b/board/synopsys/emsdp/config.mk
new file mode 100644
index 0000000..67fd7bf
--- /dev/null
+++ b/board/synopsys/emsdp/config.mk
@@ -0,0 +1,2 @@
+PLATFORM_CPPFLAGS += -mlittle-endian -mnorm -mswap -mmpy-option=3 \
+ -mbarrel-shifter -mfpu=fpuda_all -mcode-density
diff --git a/board/synopsys/emsdp/emsdp.c b/board/synopsys/emsdp/emsdp.c
index c0770b5..7a3fd5b 100644
--- a/board/synopsys/emsdp/emsdp.c
+++ b/board/synopsys/emsdp/emsdp.c
@@ -48,6 +48,43 @@
return 0;
}
+int board_early_init_r(void)
+{
+#define EMSDP_PSRAM_BASE 0xf2001000
+#define PSRAM_FLASH_CONFIG_REG_0 (void *)(EMSDP_PSRAM_BASE + 0x10)
+#define PSRAM_FLASH_CONFIG_REG_1 (void *)(EMSDP_PSRAM_BASE + 0x14)
+#define CRE_ENABLE BIT(31)
+#define CRE_DRIVE_CMD BIT(6)
+
+#define PSRAM_RCR_DPD BIT(1)
+#define PSRAM_RCR_PAGE_MODE BIT(7)
+
+/*
+ * PSRAM_FLASH_CONFIG_REG_x[30:15] to the address lines[16:1] of flash,
+ * thus "<< 1".
+ */
+#define PSRAM_RCR_SETUP ((PSRAM_RCR_DPD | PSRAM_RCR_PAGE_MODE) << 1)
+
+ // Switch PSRAM controller to command mode
+ writel(CRE_ENABLE | CRE_DRIVE_CMD, PSRAM_FLASH_CONFIG_REG_0);
+ // Program Refresh Configuration Register (RCR) for BANK0
+ writew(0, (void *)(0x10000000 + PSRAM_RCR_SETUP));
+ // Switch PSRAM controller back to memory mode
+ writel(0, PSRAM_FLASH_CONFIG_REG_0);
+
+
+ // Switch PSRAM controller to command mode
+ writel(CRE_ENABLE | CRE_DRIVE_CMD, PSRAM_FLASH_CONFIG_REG_1);
+ // Program Refresh Configuration Register (RCR) for BANK1
+ writew(0, (void *)(0x10800000 + PSRAM_RCR_SETUP));
+ // Switch PSRAM controller back to memory mode
+ writel(0, PSRAM_FLASH_CONFIG_REG_1);
+
+ printf("PSRAM initialized.\n");
+
+ return 0;
+}
+
int board_mmc_init(bd_t *bis)
{
struct dwmci_host *host = NULL;
diff --git a/board/synopsys/hsdk/env-lib.c b/board/synopsys/hsdk/env-lib.c
index 66e4581..f443c21 100644
--- a/board/synopsys/hsdk/env-lib.c
+++ b/board/synopsys/hsdk/env-lib.c
@@ -5,6 +5,7 @@
*/
#include "env-lib.h"
+#include <env.h>
#define MAX_CMD_LEN 25
diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c
index ac4d980..8a7642a 100644
--- a/board/synopsys/hsdk/hsdk.c
+++ b/board/synopsys/hsdk/hsdk.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <config.h>
+#include <env.h>
#include <linux/printk.h>
#include <linux/kernel.h>
#include <linux/io.h>
diff --git a/board/tbs/tbs2910/tbs2910.c b/board/tbs/tbs2910/tbs2910.c
index fb0e773..d8db7a8 100644
--- a/board/tbs/tbs2910/tbs2910.c
+++ b/board/tbs/tbs2910/tbs2910.c
@@ -13,7 +13,7 @@
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/video.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/mxc_hdmi.h>
@@ -98,7 +98,7 @@
imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
/* set environment device to boot device when booting from SD */
int board_mmc_get_env_dev(int devno)
{
@@ -109,7 +109,7 @@
{
return (devno == 3) ? 1 : 0; /* part 0 for SD2 / SD3, part 1 for eMMC */
}
-#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_FSL_ESDHC_IMX */
#ifdef CONFIG_VIDEO_IPUV3
static void do_enable_hdmi(struct display_info_t const *dev)
diff --git a/board/tcl/sl50/board.c b/board/tcl/sl50/board.c
index 6bb6482..c7eed31 100644
--- a/board/tcl/sl50/board.c
+++ b/board/tcl/sl50/board.c
@@ -8,6 +8,7 @@
*/
#include <common.h>
+#include <env.h>
#include <errno.h>
#include <spl.h>
#include <asm/arch/cpu.h>
@@ -27,9 +28,8 @@
#include <cpsw.h>
#include <power/tps65217.h>
#include <power/tps65910.h>
-#include <environment.h>
+#include <env_internal.h>
#include <watchdog.h>
-#include <environment.h>
#include "board.h"
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/technexion/pico-imx6ul/spl.c b/board/technexion/pico-imx6ul/spl.c
index f972cc9..284aa40 100644
--- a/board/technexion/pico-imx6ul/spl.c
+++ b/board/technexion/pico-imx6ul/spl.c
@@ -10,7 +10,7 @@
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/boot_mode.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <linux/libfdt.h>
#include <spl.h>
diff --git a/board/technexion/pico-imx7d/pico-imx7d.c b/board/technexion/pico-imx7d/pico-imx7d.c
index e3d75e5..216475c 100644
--- a/board/technexion/pico-imx7d/pico-imx7d.c
+++ b/board/technexion/pico-imx7d/pico-imx7d.c
@@ -16,7 +16,6 @@
#include <i2c.h>
#include <miiphy.h>
#include <netdev.h>
-#include <usb.h>
#include <power/pmic.h>
#include <power/pfuze3000_pmic.h>
#include "../../freescale/common/pfuze.h"
@@ -328,15 +327,3 @@
return 0;
}
-int board_usb_phy_mode(int port)
-{
- switch (port) {
- case 0:
- return USB_INIT_DEVICE;
- case 1:
- return USB_INIT_HOST;
- default:
- return -EINVAL;
- }
- return 0;
-}
diff --git a/board/technexion/pico-imx7d/spl.c b/board/technexion/pico-imx7d/spl.c
index 92a4646..c55a35d 100644
--- a/board/technexion/pico-imx7d/spl.c
+++ b/board/technexion/pico-imx7d/spl.c
@@ -13,7 +13,7 @@
#include <asm/arch-mx7/mx7-ddr.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/gpio.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <spl.h>
#if defined(CONFIG_SPL_BUILD)
diff --git a/board/technologic/ts4800/ts4800.c b/board/technologic/ts4800/ts4800.c
index a0e021e..82eb0c2 100644
--- a/board/technologic/ts4800/ts4800.c
+++ b/board/technologic/ts4800/ts4800.c
@@ -11,15 +11,15 @@
#include <asm/gpio.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux-mx51.h>
+#include <env.h>
#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/mach-imx/mx5_video.h>
-#include <environment.h>
#include <mmc.h>
#include <input.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <mc13892.h>
#include <malloc.h>
@@ -29,7 +29,7 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg esdhc_cfg[2] = {
{MMC_SDHC1_BASE_ADDR},
{MMC_SDHC2_BASE_ADDR},
@@ -96,7 +96,7 @@
imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
diff --git a/board/theobroma-systems/lion_rk3368/README b/board/theobroma-systems/lion_rk3368/README
index 83e4332..ad3ac93 100644
--- a/board/theobroma-systems/lion_rk3368/README
+++ b/board/theobroma-systems/lion_rk3368/README
@@ -18,8 +18,6 @@
=======================
> make CROSS_COMPILE=aarch64-unknown-elf- ARCH=arm
- > tools/mkimage -n rk3368 -T rksd -d tpl/u-boot-tpl.bin spl-3368.img
- > cat spl/u-boot-spl-dtb.bin >> spl-3368.img
Build the full U-Boot and a FIT image including the ATF
=======================================================
@@ -35,7 +33,7 @@
SD-Card
-------
- > dd if=spl-3368.img of=/dev/sdb seek=64
+ > dd if=idbloader.img of=/dev/sdb seek=64
> dd if=u-boot.itb of=/dev/sdb seek=512
eMMC
diff --git a/board/theobroma-systems/lion_rk3368/lion_rk3368.c b/board/theobroma-systems/lion_rk3368/lion_rk3368.c
index 6cd5a5f..1b0d504 100644
--- a/board/theobroma-systems/lion_rk3368/lion_rk3368.c
+++ b/board/theobroma-systems/lion_rk3368/lion_rk3368.c
@@ -2,21 +2,3 @@
/*
* Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
*/
-#include <common.h>
-#include <dm.h>
-#include <ram.h>
-#include <asm/io.h>
-#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/grf_rk3368.h>
-#include <asm/arch-rockchip/timer.h>
-#include <syscon.h>
-
-int mach_cpu_init(void)
-{
- return 0;
-}
-
-int board_init(void)
-{
- return 0;
-}
diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c b/board/theobroma-systems/puma_rk3399/puma-rk3399.c
index 251cd2d..47259b7 100644
--- a/board/theobroma-systems/puma_rk3399/puma-rk3399.c
+++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c
@@ -5,7 +5,7 @@
#include <common.h>
#include <dm.h>
-#include <environment.h>
+#include <env.h>
#include <misc.h>
#include <spl.h>
#include <syscon.h>
@@ -18,112 +18,10 @@
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/grf_rk3399.h>
#include <asm/arch-rockchip/periph.h>
+#include <asm/arch-rockchip/misc.h>
#include <power/regulator.h>
#include <u-boot/sha256.h>
-int board_init(void)
-{
- int ret;
-
- /*
- * We need to call into regulators_enable_boot_on() again, as the call
- * during SPL may have not included all regulators.
- */
- ret = regulators_enable_boot_on(false);
- if (ret)
- debug("%s: Cannot enable boot on regulator\n", __func__);
-
- return 0;
-}
-
-static void setup_macaddr(void)
-{
-#if CONFIG_IS_ENABLED(CMD_NET)
- int ret;
- const char *cpuid = env_get("cpuid#");
- u8 hash[SHA256_SUM_LEN];
- int size = sizeof(hash);
- u8 mac_addr[6];
-
- /* Only generate a MAC address, if none is set in the environment */
- if (env_get("ethaddr"))
- return;
-
- if (!cpuid) {
- debug("%s: could not retrieve 'cpuid#'\n", __func__);
- return;
- }
-
- ret = hash_block("sha256", (void *)cpuid, strlen(cpuid), hash, &size);
- if (ret) {
- debug("%s: failed to calculate SHA256\n", __func__);
- return;
- }
-
- /* Copy 6 bytes of the hash to base the MAC address on */
- memcpy(mac_addr, hash, 6);
-
- /* Make this a valid MAC address and set it */
- mac_addr[0] &= 0xfe; /* clear multicast bit */
- mac_addr[0] |= 0x02; /* set local assignment bit (IEEE802) */
- eth_env_set_enetaddr("ethaddr", mac_addr);
-#endif
-}
-
-static void setup_serial(void)
-{
-#if CONFIG_IS_ENABLED(ROCKCHIP_EFUSE)
- const u32 cpuid_offset = 0x7;
- const u32 cpuid_length = 0x10;
-
- struct udevice *dev;
- int ret, i;
- u8 cpuid[cpuid_length];
- u8 low[cpuid_length/2], high[cpuid_length/2];
- char cpuid_str[cpuid_length * 2 + 1];
- u64 serialno;
- char serialno_str[17];
-
- /* retrieve the device */
- ret = uclass_get_device_by_driver(UCLASS_MISC,
- DM_GET_DRIVER(rockchip_efuse), &dev);
- if (ret) {
- debug("%s: could not find efuse device\n", __func__);
- return;
- }
-
- /* read the cpu_id range from the efuses */
- ret = misc_read(dev, cpuid_offset, &cpuid, sizeof(cpuid));
- if (ret) {
- debug("%s: reading cpuid from the efuses failed\n",
- __func__);
- return;
- }
-
- memset(cpuid_str, 0, sizeof(cpuid_str));
- for (i = 0; i < 16; i++)
- sprintf(&cpuid_str[i * 2], "%02x", cpuid[i]);
-
- debug("cpuid: %s\n", cpuid_str);
-
- /*
- * Mix the cpuid bytes using the same rules as in
- * ${linux}/drivers/soc/rockchip/rockchip-cpuinfo.c
- */
- for (i = 0; i < 8; i++) {
- low[i] = cpuid[1 + (i << 1)];
- high[i] = cpuid[i << 1];
- }
-
- serialno = crc32_no_comp(0, low, 8);
- serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32;
- snprintf(serialno_str, sizeof(serialno_str), "%016llx", serialno);
-
- env_set("cpuid#", cpuid_str);
- env_set("serial#", serialno_str);
-#endif
-}
-
static void setup_iodomain(void)
{
const u32 GRF_IO_VSEL_GPIO4CD_SHIFT = 3;
@@ -213,8 +111,23 @@
int misc_init_r(void)
{
- setup_serial();
- setup_macaddr();
+ const u32 cpuid_offset = 0x7;
+ const u32 cpuid_length = 0x10;
+ u8 cpuid[cpuid_length];
+ int ret;
+
+ ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
+ if (ret)
+ return ret;
+
+ ret = rockchip_cpuid_set(cpuid, cpuid_length);
+ if (ret)
+ return ret;
+
+ ret = rockchip_setup_macaddr();
+ if (ret)
+ return ret;
+
setup_iodomain();
setup_boottargets();
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 2c32b92..7eaa6cd 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -9,6 +9,7 @@
#include <common.h>
#include <dm.h>
+#include <env.h>
#include <errno.h>
#include <spl.h>
#include <serial.h>
@@ -33,9 +34,8 @@
#include <cpsw.h>
#include <power/tps65217.h>
#include <power/tps65910.h>
-#include <environment.h>
+#include <env_internal.h>
#include <watchdog.h>
-#include <environment.h>
#include "../common/board_detect.h"
#include "board.h"
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index d29a22c..2e09cc2 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -8,7 +8,7 @@
*/
#include <common.h>
-#include <environment.h>
+#include <env.h>
#include <i2c.h>
#include <linux/errno.h>
#include <spl.h>
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 1a903f1..f78e6c2 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -8,6 +8,7 @@
*/
#include <common.h>
+#include <env.h>
#include <palmas.h>
#include <sata.h>
#include <usb.h>
@@ -23,7 +24,6 @@
#include <asm/arch/sata.h>
#include <asm/arch/gpio.h>
#include <asm/arch/omap.h>
-#include <environment.h>
#include <usb.h>
#include <linux/usb/gadget.h>
#include <dwc3-uboot.h>
diff --git a/board/ti/am65x/Kconfig b/board/ti/am65x/Kconfig
index 98172c2..47b41cd 100644
--- a/board/ti/am65x/Kconfig
+++ b/board/ti/am65x/Kconfig
@@ -12,14 +12,18 @@
select ARM64
select SOC_K3_AM6
select SYS_DISABLE_DCACHE_OPS
+ select BOARD_LATE_INIT
+ imply TI_I2C_BOARD_DETECT
config TARGET_AM654_R5_EVM
bool "TI K3 based AM654 EVM running on R5"
select CPU_V7R
select SYS_THUMB_BUILD
select SOC_K3_AM6
+ select K3_LOAD_SYSFW
select K3_AM654_DDRSS
imply SYS_K3_SPL_ATF
+ imply TI_I2C_BOARD_DETECT
endchoice
@@ -34,6 +38,8 @@
config SYS_CONFIG_NAME
default "am65x_evm"
+source "board/ti/common/Kconfig"
+
endif
if TARGET_AM654_R5_EVM
@@ -50,4 +56,6 @@
config SPL_LDSCRIPT
default "arch/arm/mach-omap2/u-boot-spl.lds"
+source "board/ti/common/Kconfig"
+
endif
diff --git a/board/ti/am65x/README b/board/ti/am65x/README
index 0b82bd5..16384e0 100644
--- a/board/ti/am65x/README
+++ b/board/ti/am65x/README
@@ -209,3 +209,55 @@
| | Secure config | |
| +-------------------+ |
+-----------------------+
+
+eMMC:
+-----
+ROM supports booting from eMMC from boot0 partition offset 0x0
+
+Flashing images to eMMC:
+
+The following commands can be used to download tiboot3.bin, tispl.bin,
+u-boot.img, and sysfw.itb from an SD card and write them to the eMMC boot0
+partition at respective addresses.
+
+=> mmc dev 0 1
+=> fatload mmc 1 ${loadaddr} tiboot3.bin
+=> mmc write ${loadaddr} 0x0 0x400
+=> fatload mmc 1 ${loadaddr} tispl.bin
+=> mmc write ${loadaddr} 0x400 0x1000
+=> fatload mmc 1 ${loadaddr} u-boot.img
+=> mmc write ${loadaddr} 0x1400 0x2000
+=> fatload mmc 1 ${loadaddr} sysfw.itb
+=> mmc write ${loadaddr} 0x3600 0x800
+
+To give the ROM access to the boot partition, the following commands must be
+used for the first time:
+=> mmc partconf 0 1 1 1
+=> mmc bootbus 0 1 0 0
+
+To create a software partition for the rootfs, the following command can be
+used:
+=> gpt write mmc 0 ${partitions}
+
+eMMC layout:
+
+ boot0 partition (8 MB) user partition
+ 0x0+----------------------------------+ 0x0+-------------------------+
+ | tiboot3.bin (512 KB) | | |
+ 0x400+----------------------------------+ | |
+ | tispl.bin (2 MB) | | |
+0x1400+----------------------------------+ | rootfs |
+ | u-boot.img (4 MB) | | |
+0x3400+----------------------------------+ | |
+ | environment (128 KB) | | |
+0x3500+----------------------------------+ | |
+ | backup environment (128 KB) | | |
+0x3600+----------------------------------+ | |
+ | sysfw (1 MB) | | |
+0x3E00+----------------------------------+ +-------------------------+
+
+Kernel image and DT are expected to be present in the /boot folder of rootfs.
+To boot kernel from eMMC, use the following commands:
+=> setenv mmcdev 0
+=> setenv bootpart 0
+=> boot
diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c
index 52f5d6b..ad333ad 100644
--- a/board/ti/am65x/evm.c
+++ b/board/ti/am65x/evm.c
@@ -8,10 +8,32 @@
*/
#include <common.h>
+#include <dm.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/gpio.h>
#include <asm/io.h>
+#include <asm/omap_common.h>
+#include <env.h>
#include <spl.h>
#include <asm/arch/sys_proto.h>
+#include "../common/board_detect.h"
+
+#define board_is_am65x_base_board() board_ti_is("AM6-COMPROCEVM")
+
+/* Daughter card presence detection signals */
+enum {
+ AM65X_EVM_APP_BRD_DET,
+ AM65X_EVM_LCD_BRD_DET,
+ AM65X_EVM_SERDES_BRD_DET,
+ AM65X_EVM_HDMI_GPMC_BRD_DET,
+ AM65X_EVM_BRD_DET_COUNT,
+};
+
+/* Max number of MAC addresses that are parsed/processed per daughter card */
+#define DAUGHTER_CARD_NO_OF_MAC_ADDR 8
+
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
@@ -74,9 +96,240 @@
int ret;
ret = fdt_fixup_msmc_ram(blob, "/interconnect@100000", "sram@70000000");
- if (ret)
+ if (ret) {
printf("%s: fixing up msmc ram failed %d\n", __func__, ret);
+ return ret;
+ }
+
+#if defined(CONFIG_TI_SECURE_DEVICE)
+ /* Make HW RNG reserved for secure world use */
+ ret = fdt_disable_node(blob, "/interconnect@100000/trng@4e10000");
+ if (ret) {
+ printf("%s: disabling TRGN failed %d\n", __func__, ret);
+ return ret;
+ }
+#endif
+
+ return 0;
+}
+#endif
+
+int do_board_detect(void)
+{
+ int ret;
+
+ ret = ti_i2c_eeprom_am6_get_base(CONFIG_EEPROM_BUS_ADDRESS,
+ CONFIG_EEPROM_CHIP_ADDRESS);
+ if (ret)
+ pr_err("Reading on-board EEPROM at 0x%02x failed %d\n",
+ CONFIG_EEPROM_CHIP_ADDRESS, ret);
return ret;
}
-#endif
+
+static void setup_board_eeprom_env(void)
+{
+ char *name = "am65x";
+
+ if (do_board_detect())
+ goto invalid_eeprom;
+
+ if (board_is_am65x_base_board())
+ name = "am65x";
+ else
+ printf("Unidentified board claims %s in eeprom header\n",
+ board_ti_get_name());
+
+invalid_eeprom:
+ set_board_info_env_am6(name);
+}
+
+static int init_daughtercard_det_gpio(char *gpio_name, struct gpio_desc *desc)
+{
+ int ret;
+
+ memset(desc, 0, sizeof(*desc));
+
+ ret = dm_gpio_lookup_name(gpio_name, desc);
+ if (ret < 0)
+ return ret;
+
+ /* Request GPIO, simply re-using the name as label */
+ ret = dm_gpio_request(desc, gpio_name);
+ if (ret < 0)
+ return ret;
+
+ return dm_gpio_set_dir_flags(desc, GPIOD_IS_IN);
+}
+
+static int probe_daughtercards(void)
+{
+ struct ti_am6_eeprom ep;
+ struct gpio_desc board_det_gpios[AM65X_EVM_BRD_DET_COUNT];
+ char mac_addr[DAUGHTER_CARD_NO_OF_MAC_ADDR][TI_EEPROM_HDR_ETH_ALEN];
+ u8 mac_addr_cnt;
+ char name_overlays[1024] = { 0 };
+ int i, j;
+ int ret;
+
+ /*
+ * Daughter card presence detection signal name to GPIO (via I2C I/O
+ * expander @ address 0x38) name and EEPROM I2C address mapping.
+ */
+ const struct {
+ char *gpio_name;
+ u8 i2c_addr;
+ } slot_map[AM65X_EVM_BRD_DET_COUNT] = {
+ { "gpio@38_0", 0x52, }, /* AM65X_EVM_APP_BRD_DET */
+ { "gpio@38_1", 0x55, }, /* AM65X_EVM_LCD_BRD_DET */
+ { "gpio@38_2", 0x54, }, /* AM65X_EVM_SERDES_BRD_DET */
+ { "gpio@38_3", 0x53, }, /* AM65X_EVM_HDMI_GPMC_BRD_DET */
+ };
+
+ /* Declaration of daughtercards to probe */
+ const struct {
+ u8 slot_index; /* Slot the card is installed */
+ char *card_name; /* EEPROM-programmed card name */
+ char *dtbo_name; /* Device tree overlay to apply */
+ u8 eth_offset; /* ethXaddr MAC address index offset */
+ } cards[] = {
+ {
+ AM65X_EVM_APP_BRD_DET,
+ "AM6-GPAPPEVM",
+ "k3-am654-gp.dtbo",
+ 0,
+ },
+ {
+ AM65X_EVM_APP_BRD_DET,
+ "AM6-IDKAPPEVM",
+ "k3-am654-idk.dtbo",
+ 3,
+ },
+ {
+ AM65X_EVM_SERDES_BRD_DET,
+ "SER-PCIE2LEVM",
+ "k3-am654-pcie-usb2.dtbo",
+ 0,
+ },
+ {
+ AM65X_EVM_SERDES_BRD_DET,
+ "SER-PCIEUSBEVM",
+ "k3-am654-pcie-usb3.dtbo",
+ 0,
+ },
+ {
+ AM65X_EVM_LCD_BRD_DET,
+ "OLDI-LCD1EVM",
+ "k3-am654-evm-oldi-lcd1evm.dtbo",
+ 0,
+ },
+ };
+
+ /*
+ * Initialize GPIO used for daughtercard slot presence detection and
+ * keep the resulting handles in local array for easier access.
+ */
+ for (i = 0; i < AM65X_EVM_BRD_DET_COUNT; i++) {
+ ret = init_daughtercard_det_gpio(slot_map[i].gpio_name,
+ &board_det_gpios[i]);
+ if (ret < 0)
+ return ret;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(cards); i++) {
+ /* Obtain card-specific slot index and associated I2C address */
+ u8 slot_index = cards[i].slot_index;
+ u8 i2c_addr = slot_map[slot_index].i2c_addr;
+
+ /*
+ * The presence detection signal is active-low, hence skip
+ * over this card slot if anything other than 0 is returned.
+ */
+ ret = dm_gpio_get_value(&board_det_gpios[slot_index]);
+ if (ret < 0)
+ return ret;
+ else if (ret)
+ continue;
+
+ /* Get and parse the daughter card EEPROM record */
+ ret = ti_i2c_eeprom_am6_get(CONFIG_EEPROM_BUS_ADDRESS, i2c_addr,
+ &ep,
+ (char **)mac_addr,
+ DAUGHTER_CARD_NO_OF_MAC_ADDR,
+ &mac_addr_cnt);
+ if (ret) {
+ pr_err("Reading daughtercard EEPROM at 0x%02x failed %d\n",
+ i2c_addr, ret);
+ /*
+ * Even this is pretty serious let's just skip over
+ * this particular daughtercard, rather than ending
+ * the probing process altogether.
+ */
+ continue;
+ }
+
+ /* Only process the parsed data if we found a match */
+ if (strncmp(ep.name, cards[i].card_name, sizeof(ep.name)))
+ continue;
+
+ printf("detected %s\n", cards[i].card_name);
+
+ /*
+ * Populate any MAC addresses from daughtercard into the U-Boot
+ * environment, starting with a card-specific offset so we can
+ * have multiple cards contribute to the MAC pool in a well-
+ * defined manner.
+ */
+ for (j = 0; j < mac_addr_cnt; j++) {
+ if (!is_valid_ethaddr((u8 *)mac_addr[j]))
+ continue;
+
+ eth_env_set_enetaddr_by_index("eth",
+ cards[i].eth_offset + j,
+ (uchar *)mac_addr[j]);
+ }
+
+ /* Skip if no overlays are to be added */
+ if (!strlen(cards[i].dtbo_name))
+ continue;
+
+ /*
+ * Make sure we are not running out of buffer space by checking
+ * if we can fit the new overlay, a trailing space to be used
+ * as a separator, plus the terminating zero.
+ */
+ if (strlen(name_overlays) + strlen(cards[i].dtbo_name) + 2 >
+ sizeof(name_overlays))
+ return -ENOMEM;
+
+ /* Append to our list of overlays */
+ strcat(name_overlays, cards[i].dtbo_name);
+ strcat(name_overlays, " ");
+ }
+
+ /* Apply device tree overlay(s) to the U-Boot environment, if any */
+ if (strlen(name_overlays))
+ return env_set("name_overlays", name_overlays);
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
+
+ setup_board_eeprom_env();
+
+ /*
+ * The first MAC address for ethernet a.k.a. ethernet0 comes from
+ * efuse populated via the am654 gigabit eth switch subsystem driver.
+ * All the other ones are populated via EEPROM, hence continue with
+ * an index of 1.
+ */
+ board_ti_am6_set_ethaddr(1, ep->mac_addr_cnt);
+
+ /* Check for and probe any plugged-in daughtercards */
+ probe_daughtercards();
+
+ return 0;
+}
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
index 91e0a4c..0138fc9 100644
--- a/board/ti/beagle/beagle.c
+++ b/board/ti/beagle/beagle.c
@@ -14,6 +14,7 @@
*/
#include <common.h>
#include <dm.h>
+#include <env.h>
#include <ns16550.h>
#ifdef CONFIG_LED_STATUS
#include <status_led.h>
diff --git a/board/ti/common/board_detect.c b/board/ti/common/board_detect.c
index e258e22..bc89cc5 100644
--- a/board/ti/common/board_detect.c
+++ b/board/ti/common/board_detect.c
@@ -8,8 +8,10 @@
*/
#include <common.h>
+#include <asm/arch/hardware.h>
#include <asm/omap_common.h>
#include <dm/uclass.h>
+#include <env.h>
#include <i2c.h>
#include "board_detect.h"
@@ -284,6 +286,191 @@
return 0;
}
+static int ti_i2c_eeprom_am6_parse_record(struct ti_am6_eeprom_record *record,
+ struct ti_am6_eeprom *ep,
+ char **mac_addr,
+ u8 mac_addr_max_cnt,
+ u8 *mac_addr_cnt)
+{
+ switch (record->header.id) {
+ case TI_AM6_EEPROM_RECORD_BOARD_INFO:
+ if (record->header.len != sizeof(record->data.board_info))
+ return -EINVAL;
+
+ if (!ep)
+ break;
+
+ /* Populate (and clean, if needed) the board name */
+ strlcpy(ep->name, record->data.board_info.name,
+ sizeof(ep->name));
+ ti_eeprom_string_cleanup(ep->name);
+
+ /* Populate selected other fields from the board info record */
+ strlcpy(ep->version, record->data.board_info.version,
+ sizeof(ep->version));
+ strlcpy(ep->software_revision,
+ record->data.board_info.software_revision,
+ sizeof(ep->software_revision));
+ strlcpy(ep->serial, record->data.board_info.serial,
+ sizeof(ep->serial));
+ break;
+ case TI_AM6_EEPROM_RECORD_MAC_INFO:
+ if (record->header.len != sizeof(record->data.mac_info))
+ return -EINVAL;
+
+ if (!mac_addr || !mac_addr_max_cnt)
+ break;
+
+ *mac_addr_cnt = ((record->data.mac_info.mac_control &
+ TI_AM6_EEPROM_MAC_ADDR_COUNT_MASK) >>
+ TI_AM6_EEPROM_MAC_ADDR_COUNT_SHIFT) + 1;
+
+ /*
+ * The EEPROM can (but may not) hold a very large amount
+ * of MAC addresses, by far exceeding what we want/can store
+ * in the common memory array, so only grab what we can fit.
+ * Note that a value of 0 means 1 MAC address, and so on.
+ */
+ *mac_addr_cnt = min(*mac_addr_cnt, mac_addr_max_cnt);
+
+ memcpy(mac_addr, record->data.mac_info.mac_addr,
+ *mac_addr_cnt * TI_EEPROM_HDR_ETH_ALEN);
+ break;
+ case 0x00:
+ /* Illegal value... Fall through... */
+ case 0xFF:
+ /* Illegal value... Something went horribly wrong... */
+ return -EINVAL;
+ default:
+ pr_warn("%s: Ignoring record id %u\n", __func__,
+ record->header.id);
+ }
+
+ return 0;
+}
+
+int __maybe_unused ti_i2c_eeprom_am6_get(int bus_addr, int dev_addr,
+ struct ti_am6_eeprom *ep,
+ char **mac_addr,
+ u8 mac_addr_max_cnt,
+ u8 *mac_addr_cnt)
+{
+ struct udevice *dev;
+ struct udevice *bus;
+ unsigned int eeprom_addr;
+ struct ti_am6_eeprom_record_board_id board_id;
+ struct ti_am6_eeprom_record record;
+ int rc;
+
+ /* Initialize with a known bad marker for i2c fails.. */
+ memset(ep, 0, sizeof(*ep));
+ ep->header = TI_DEAD_EEPROM_MAGIC;
+
+ /* Read the board ID record which is always the first EEPROM record */
+ rc = ti_i2c_eeprom_get(bus_addr, dev_addr, TI_EEPROM_HEADER_MAGIC,
+ sizeof(board_id), (uint8_t *)&board_id);
+ if (rc)
+ return rc;
+
+ if (board_id.header.id != TI_AM6_EEPROM_RECORD_BOARD_ID) {
+ pr_err("%s: Invalid board ID record!\n", __func__);
+ return -EINVAL;
+ }
+
+ /* Establish DM handle to board config EEPROM */
+ rc = uclass_get_device_by_seq(UCLASS_I2C, bus_addr, &bus);
+ if (rc)
+ return rc;
+ rc = i2c_get_chip(bus, dev_addr, 1, &dev);
+ if (rc)
+ return rc;
+
+ ep->header = TI_EEPROM_HEADER_MAGIC;
+
+ /* Ready to parse TLV structure. Initialize variables... */
+ *mac_addr_cnt = 0;
+
+ /*
+ * After the all-encompassing board ID record all other records follow
+ * a TLV-type scheme. Point to the first such record and then start
+ * parsing those one by one.
+ */
+ eeprom_addr = sizeof(board_id);
+
+ while (true) {
+ rc = dm_i2c_read(dev, eeprom_addr, (uint8_t *)&record.header,
+ sizeof(record.header));
+ if (rc)
+ return rc;
+
+ /*
+ * Check for end of list marker. If we reached it don't go
+ * any further and stop parsing right here.
+ */
+ if (record.header.id == TI_AM6_EEPROM_RECORD_END_LIST)
+ break;
+
+ eeprom_addr += sizeof(record.header);
+
+ debug("%s: dev_addr=0x%02x header.id=%u header.len=%u\n",
+ __func__, dev_addr, record.header.id,
+ record.header.len);
+
+ /* Read record into memory if it fits */
+ if (record.header.len <= sizeof(record.data)) {
+ rc = dm_i2c_read(dev, eeprom_addr,
+ (uint8_t *)&record.data,
+ record.header.len);
+ if (rc)
+ return rc;
+
+ /* Process record */
+ rc = ti_i2c_eeprom_am6_parse_record(&record, ep,
+ mac_addr,
+ mac_addr_max_cnt,
+ mac_addr_cnt);
+ if (rc) {
+ pr_err("%s: EEPROM parsing error!\n", __func__);
+ return rc;
+ }
+ } else {
+ /*
+ * We may get here in case of larger records which
+ * are not yet understood.
+ */
+ pr_err("%s: Ignoring record id %u\n", __func__,
+ record.header.id);
+ }
+
+ eeprom_addr += record.header.len;
+ }
+
+ return 0;
+}
+
+int __maybe_unused ti_i2c_eeprom_am6_get_base(int bus_addr, int dev_addr)
+{
+ struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
+ int ret;
+
+ /*
+ * Always execute EEPROM read by not allowing to bypass it during the
+ * first invocation of SPL which happens on the R5 core.
+ */
+#if !(defined(CONFIG_SPL_BUILD) && defined(CONFIG_CPU_V7R))
+ if (ep->header == TI_EEPROM_HEADER_MAGIC) {
+ debug("%s: EEPROM has already been read\n", __func__);
+ return 0;
+ }
+#endif
+
+ ret = ti_i2c_eeprom_am6_get(bus_addr, dev_addr, ep,
+ (char **)ep->mac_addr,
+ AM6_EEPROM_HDR_NO_OF_MAC_ADDR,
+ &ep->mac_addr_cnt);
+ return ret;
+}
+
bool __maybe_unused board_ti_is(char *name_tag)
{
struct ti_common_eeprom *ep = TI_EEPROM_DATA;
@@ -348,6 +535,25 @@
memset(mac_addr, 0, TI_EEPROM_HDR_ETH_ALEN);
}
+void __maybe_unused
+board_ti_am6_get_eth_mac_addr(int index,
+ u8 mac_addr[TI_EEPROM_HDR_ETH_ALEN])
+{
+ struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
+
+ if (ep->header == TI_DEAD_EEPROM_MAGIC)
+ goto fail;
+
+ if (index < 0 || index >= ep->mac_addr_cnt)
+ goto fail;
+
+ memcpy(mac_addr, ep->mac_addr[index], TI_EEPROM_HDR_ETH_ALEN);
+ return;
+
+fail:
+ memset(mac_addr, 0, TI_EEPROM_HDR_ETH_ALEN);
+}
+
u64 __maybe_unused board_ti_get_emif1_size(void)
{
struct ti_common_eeprom *ep = TI_EEPROM_DATA;
@@ -391,6 +597,34 @@
env_set("board_serial", unknown);
}
+void __maybe_unused set_board_info_env_am6(char *name)
+{
+ char *unknown = "unknown";
+ struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
+
+ if (name)
+ env_set("board_name", name);
+ else if (ep->name)
+ env_set("board_name", ep->name);
+ else
+ env_set("board_name", unknown);
+
+ if (ep->version)
+ env_set("board_rev", ep->version);
+ else
+ env_set("board_rev", unknown);
+
+ if (ep->software_revision)
+ env_set("board_software_revision", ep->software_revision);
+ else
+ env_set("board_software_revision", unknown);
+
+ if (ep->serial)
+ env_set("board_serial", ep->serial);
+ else
+ env_set("board_serial", unknown);
+}
+
static u64 mac_to_u64(u8 mac[6])
{
int i;
@@ -453,6 +687,19 @@
}
}
+void board_ti_am6_set_ethaddr(int index, int count)
+{
+ u8 mac_addr[6];
+ int i;
+
+ for (i = 0; i < count; i++) {
+ board_ti_am6_get_eth_mac_addr(i, mac_addr);
+ if (is_valid_ethaddr(mac_addr))
+ eth_env_set_enetaddr_by_index("eth", i + index,
+ mac_addr);
+ }
+}
+
bool __maybe_unused board_ti_was_eeprom_read(void)
{
struct ti_common_eeprom *ep = TI_EEPROM_DATA;
diff --git a/board/ti/common/board_detect.h b/board/ti/common/board_detect.h
index f8495a7..a45d896 100644
--- a/board/ti/common/board_detect.h
+++ b/board/ti/common/board_detect.h
@@ -43,6 +43,133 @@
char mac_addr[TI_EEPROM_HDR_NO_OF_MAC_ADDR][TI_EEPROM_HDR_ETH_ALEN];
} __attribute__ ((__packed__));
+/* AM6x TI EVM EEPROM Definitions */
+#define TI_AM6_EEPROM_RECORD_BOARD_ID 0x01
+#define TI_AM6_EEPROM_RECORD_BOARD_INFO 0x10
+#define TI_AM6_EEPROM_RECORD_DDR_INFO 0x11
+#define TI_AM6_EEPROM_RECORD_DDR_SPD 0x12
+#define TI_AM6_EEPROM_RECORD_MAC_INFO 0x13
+#define TI_AM6_EEPROM_RECORD_END_LIST 0xFE
+
+/*
+ * Common header for AM6x TI EVM EEPROM records. Used to encapsulate the config
+ * EEPROM in its entirety as well as for individual records contained within.
+ */
+struct ti_am6_eeprom_record_header {
+ u8 id;
+ u16 len;
+} __attribute__ ((__packed__));
+
+/* AM6x TI EVM EEPROM board ID structure */
+struct ti_am6_eeprom_record_board_id {
+ u32 magic_number;
+ struct ti_am6_eeprom_record_header header;
+} __attribute__ ((__packed__));
+
+/* AM6x TI EVM EEPROM board info structure */
+#define AM6_EEPROM_HDR_NAME_LEN 16
+#define AM6_EEPROM_HDR_VERSION_LEN 2
+#define AM6_EEPROM_HDR_PROC_NR_LEN 4
+#define AM6_EEPROM_HDR_VARIANT_LEN 2
+#define AM6_EEPROM_HDR_PCB_REV_LEN 2
+#define AM6_EEPROM_HDR_SCH_BOM_REV_LEN 2
+#define AM6_EEPROM_HDR_SW_REV_LEN 2
+#define AM6_EEPROM_HDR_VID_LEN 2
+#define AM6_EEPROM_HDR_BLD_WK_LEN 2
+#define AM6_EEPROM_HDR_BLD_YR_LEN 2
+#define AM6_EEPROM_HDR_4P_NR_LEN 6
+#define AM6_EEPROM_HDR_SERIAL_LEN 4
+
+struct ti_am6_eeprom_record_board_info {
+ char name[AM6_EEPROM_HDR_NAME_LEN];
+ char version[AM6_EEPROM_HDR_VERSION_LEN];
+ char proc_number[AM6_EEPROM_HDR_PROC_NR_LEN];
+ char variant[AM6_EEPROM_HDR_VARIANT_LEN];
+ char pcb_revision[AM6_EEPROM_HDR_PCB_REV_LEN];
+ char schematic_bom_revision[AM6_EEPROM_HDR_SCH_BOM_REV_LEN];
+ char software_revision[AM6_EEPROM_HDR_SW_REV_LEN];
+ char vendor_id[AM6_EEPROM_HDR_VID_LEN];
+ char build_week[AM6_EEPROM_HDR_BLD_WK_LEN];
+ char build_year[AM6_EEPROM_HDR_BLD_YR_LEN];
+ char board_4p_number[AM6_EEPROM_HDR_4P_NR_LEN];
+ char serial[AM6_EEPROM_HDR_SERIAL_LEN];
+} __attribute__ ((__packed__));
+
+/* Memory location to keep a copy of the AM6 board info record */
+#define TI_AM6_EEPROM_BD_INFO_DATA ((struct ti_am6_eeprom_record_board_info *) \
+ TI_SRAM_SCRATCH_BOARD_EEPROM_START)
+
+/* AM6x TI EVM EEPROM DDR info structure */
+#define TI_AM6_EEPROM_DDR_CTRL_INSTANCE_MASK GENMASK(1, 0)
+#define TI_AM6_EEPROM_DDR_CTRL_INSTANCE_SHIFT 0
+#define TI_AM6_EEPROM_DDR_CTRL_SPD_DATA_LOC_MASK GENMASK(3, 2)
+#define TI_AM6_EEPROM_DDR_CTRL_SPD_DATA_LOC_NA (0 << 2)
+#define TI_AM6_EEPROM_DDR_CTRL_SPD_DATA_LOC_BOARDID (2 << 2)
+#define TI_AM6_EEPROM_DDR_CTRL_SPD_DATA_LOC_I2C51 (3 << 2)
+#define TI_AM6_EEPROM_DDR_CTRL_MEM_TYPE_MASK GENMASK(5, 4)
+#define TI_AM6_EEPROM_DDR_CTRL_MEM_TYPE_DDR3 (0 << 4)
+#define TI_AM6_EEPROM_DDR_CTRL_MEM_TYPE_DDR4 (1 << 4)
+#define TI_AM6_EEPROM_DDR_CTRL_MEM_TYPE_LPDDR4 (2 << 4)
+#define TI_AM6_EEPROM_DDR_CTRL_IF_DATA_WIDTH_MASK GENMASK(7, 6)
+#define TI_AM6_EEPROM_DDR_CTRL_IF_DATA_WIDTH_16 (0 << 6)
+#define TI_AM6_EEPROM_DDR_CTRL_IF_DATA_WIDTH_32 (1 << 6)
+#define TI_AM6_EEPROM_DDR_CTRL_IF_DATA_WIDTH_64 (2 << 6)
+#define TI_AM6_EEPROM_DDR_CTRL_DEV_DATA_WIDTH_MASK GENMASK(9, 8)
+#define TI_AM6_EEPROM_DDR_CTRL_DEV_DATA_WIDTH_8 (0 << 8)
+#define TI_AM6_EEPROM_DDR_CTRL_DEV_DATA_WIDTH_16 (1 << 8)
+#define TI_AM6_EEPROM_DDR_CTRL_DEV_DATA_WIDTH_32 (2 << 8)
+#define TI_AM6_EEPROM_DDR_CTRL_RANKS_2 BIT(10)
+#define TI_AM6_EEPROM_DDR_CTRL_DENS_MASK GENMASK(13, 11)
+#define TI_AM6_EEPROM_DDR_CTRL_DENS_1GB (0 << 11)
+#define TI_AM6_EEPROM_DDR_CTRL_DENS_2GB (1 << 11)
+#define TI_AM6_EEPROM_DDR_CTRL_DENS_4GB (2 << 11)
+#define TI_AM6_EEPROM_DDR_CTRL_DENS_8GB (3 << 11)
+#define TI_AM6_EEPROM_DDR_CTRL_DENS_12GB (4 << 11)
+#define TI_AM6_EEPROM_DDR_CTRL_DENS_16GB (5 << 11)
+#define TI_AM6_EEPROM_DDR_CTRL_DENS_24GB (6 << 11)
+#define TI_AM6_EEPROM_DDR_CTRL_DENS_32GB (7 << 11)
+#define TI_AM6_EEPROM_DDR_CTRL_ECC BIT(14)
+
+struct ti_am6_eeprom_record_ddr_info {
+ u16 ddr_control;
+} __attribute__ ((__packed__));
+
+/* AM6x TI EVM EEPROM DDR SPD structure */
+#define TI_AM6_EEPROM_DDR_SPD_INSTANCE_MASK GENMASK(1, 0)
+#define TI_AM6_EEPROM_DDR_SPD_INSTANCE_SHIFT 0
+#define TI_AM6_EEPROM_DDR_SPD_MEM_TYPE_MASK GENMASK(4, 3)
+#define TI_AM6_EEPROM_DDR_SPD_MEM_TYPE_DDR3 (0 << 3)
+#define TI_AM6_EEPROM_DDR_SPD_MEM_TYPE_DDR4 (1 << 3)
+#define TI_AM6_EEPROM_DDR_SPD_MEM_TYPE_LPDDR4 (2 << 3)
+#define TI_AM6_EEPROM_DDR_SPD_DATA_LEN 512
+
+struct ti_am6_eeprom_record_ddr_spd {
+ u16 spd_control;
+ u8 data[TI_AM6_EEPROM_DDR_SPD_DATA_LEN];
+} __attribute__ ((__packed__));
+
+/* AM6x TI EVM EEPROM MAC info structure */
+#define TI_AM6_EEPROM_MAC_INFO_INSTANCE_MASK GENMASK(2, 0)
+#define TI_AM6_EEPROM_MAC_INFO_INSTANCE_SHIFT 0
+#define TI_AM6_EEPROM_MAC_ADDR_COUNT_MASK GENMASK(7, 3)
+#define TI_AM6_EEPROM_MAC_ADDR_COUNT_SHIFT 3
+#define TI_AM6_EEPROM_MAC_ADDR_MAX_COUNT 32
+
+struct ti_am6_eeprom_record_mac_info {
+ u16 mac_control;
+ u8 mac_addr[TI_AM6_EEPROM_MAC_ADDR_MAX_COUNT][TI_EEPROM_HDR_ETH_ALEN];
+} __attribute__ ((__packed__));
+
+struct ti_am6_eeprom_record {
+ struct ti_am6_eeprom_record_header header;
+ union {
+ struct ti_am6_eeprom_record_board_info board_info;
+ struct ti_am6_eeprom_record_ddr_info ddr_info;
+ struct ti_am6_eeprom_record_ddr_spd ddr_spd;
+ struct ti_am6_eeprom_record_mac_info mac_info;
+ } data;
+} __attribute__ ((__packed__));
+
/* DRA7 EEPROM MAGIC Header identifier */
#define DRA7_EEPROM_HEADER_MAGIC 0xAA5533EE
#define DRA7_EEPROM_HDR_NAME_LEN 16
@@ -99,6 +226,37 @@
#define TI_EEPROM_DATA ((struct ti_common_eeprom *)\
TI_SRAM_SCRATCH_BOARD_EEPROM_START)
+/*
+ * Maximum number of Ethernet MAC addresses extracted from the AM6x on-board
+ * EEPROM during the initial probe and carried forward in SRAM.
+ */
+#define AM6_EEPROM_HDR_NO_OF_MAC_ADDR 8
+
+/**
+ * struct ti_am6_eeprom - Null terminated, usable EEPROM contents, as extracted
+ * from the AM6 on-board EEPROM. Note that we only carry a subset of data
+ * at this time to be considerate about memory consumption.
+ * @header: Magic number for data validity indication
+ * @name: NULL terminated name
+ * @version: NULL terminated version
+ * @software_revision: NULL terminated software revision
+ * @serial: Board serial number
+ * @mac_addr_cnt: Number of MAC addresses stored in this object
+ * @mac_addr: MAC addresses
+ */
+struct ti_am6_eeprom {
+ u32 header;
+ char name[AM6_EEPROM_HDR_NAME_LEN + 1];
+ char version[AM6_EEPROM_HDR_VERSION_LEN + 1];
+ char software_revision[AM6_EEPROM_HDR_SW_REV_LEN + 1];
+ char serial[AM6_EEPROM_HDR_SERIAL_LEN + 1];
+ u8 mac_addr_cnt;
+ char mac_addr[AM6_EEPROM_HDR_NO_OF_MAC_ADDR][TI_EEPROM_HDR_ETH_ALEN];
+};
+
+#define TI_AM6_EEPROM_DATA ((struct ti_am6_eeprom *) \
+ TI_SRAM_SCRATCH_BOARD_EEPROM_START)
+
/**
* ti_i2c_eeprom_am_get() - Consolidated eeprom data collection for AM* TI EVMs
* @bus_addr: I2C bus address
@@ -117,6 +275,33 @@
int ti_i2c_eeprom_dra7_get(int bus_addr, int dev_addr);
/**
+ * ti_i2c_eeprom_am6_get() - Consolidated eeprom data for AM6x TI EVMs and
+ * associated daughter cards, parsed into user-
+ * provided data structures
+ * @bus_addr: I2C bus address
+ * @dev_addr: I2C slave address
+ * @ep: Pointer to structure receiving AM6-specific header data
+ * @mac_addr: Pointer to memory receiving parsed MAC addresses. May be
+ * NULL to skip MAC parsing.
+ * @mac_addr_max_cnt: Maximum number of MAC addresses that can be stored into
+ * mac_addr. May be NULL to skip MAC parsing.
+ * @mac_addr_cnt: Pointer to a location returning how many MAC addressed got
+ * actually parsed.
+ */
+int __maybe_unused ti_i2c_eeprom_am6_get(int bus_addr, int dev_addr,
+ struct ti_am6_eeprom *ep,
+ char **mac_addr,
+ u8 mac_addr_max_cnt,
+ u8 *mac_addr_cnt);
+
+/**
+ * ti_i2c_eeprom_am6_get_base() - Consolidated eeprom data for AM6x TI EVMs
+ * @bus_addr: I2C bus address
+ * @dev_addr: I2C slave address
+ */
+int __maybe_unused ti_i2c_eeprom_am6_get_base(int bus_addr, int dev_addr);
+
+/**
* board_ti_is() - Board detection logic for TI EVMs
* @name_tag: Tag used in eeprom for the board
*
@@ -193,6 +378,15 @@
void set_board_info_env(char *name);
/**
+ * set_board_info_env_am6() - Setup commonly used board information environment
+ * vars for AM6-type boards
+ * @name: Name of the board
+ *
+ * If name is NULL, default_name is used.
+ */
+void set_board_info_env_am6(char *name);
+
+/**
* board_ti_set_ethaddr- Sets the ethaddr environment from EEPROM
* @index: The first eth<index>addr environment variable to set
*
@@ -205,6 +399,18 @@
void board_ti_set_ethaddr(int index);
/**
+ * board_ti_am6_set_ethaddr- Sets the ethaddr environment from EEPROM
+ * @index: The first eth<index>addr environment variable to set
+ * @count: The number of MAC addresses to process
+ *
+ * EEPROM should be already read before calling this function. The EEPROM
+ * contains n dedicated MAC addresses. This function sets the ethaddr
+ * environment variable for all the available MAC addresses starting
+ * from eth<index>addr.
+ */
+void board_ti_am6_set_ethaddr(int index, int count);
+
+/**
* board_ti_was_eeprom_read() - Check to see if the eeprom contents have been read
*
* This function is useful to determine if the eeprom has already been read and
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 179adc2..74d04bb 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -10,6 +10,7 @@
* Steve Sakoman <steve@sakoman.com>
*/
#include <common.h>
+#include <env.h>
#include <palmas.h>
#include <sata.h>
#include <linux/string.h>
@@ -24,7 +25,6 @@
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sata.h>
-#include <environment.h>
#include <dwc3-uboot.h>
#include <dwc3-omap-uboot.h>
#include <i2c.h>
diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c
index daecb4a..d0b9baf 100644
--- a/board/ti/evm/evm.c
+++ b/board/ti/evm/evm.c
@@ -12,6 +12,7 @@
*/
#include <common.h>
#include <dm.h>
+#include <env.h>
#include <ns16550.h>
#include <netdev.h>
#include <asm/io.h>
@@ -30,11 +31,6 @@
#include <linux/usb/musb.h>
#include "evm.h"
-#ifdef CONFIG_USB_EHCI_HCD
-#include <usb.h>
-#include <asm/ehci-omap.h>
-#endif
-
#define OMAP3EVM_GPIO_ETH_RST_GEN1 64
#define OMAP3EVM_GPIO_ETH_RST_GEN2 7
@@ -307,32 +303,6 @@
}
#endif /* CONFIG_MMC */
-#if defined(CONFIG_USB_EHCI_HCD) && !defined(CONFIG_SPL_BUILD)
-/* Call usb_stop() before starting the kernel */
-void show_boot_progress(int val)
-{
- if (val == BOOTSTAGE_ID_RUN_OS)
- usb_stop();
-}
-
-static struct omap_usbhs_board_data usbhs_bdata = {
- .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
- .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
- .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED
-};
-
-int ehci_hcd_init(int index, enum usb_init_type init,
- struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
- return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
-}
-
-int ehci_hcd_stop(int index)
-{
- return omap_ehci_hcd_stop();
-}
-#endif /* CONFIG_USB_EHCI_HCD */
-
#if defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET) && !defined(CONFIG_CMD_NET)
int board_eth_init(bd_t *bis)
{
diff --git a/board/ti/j721e/Kconfig b/board/ti/j721e/Kconfig
new file mode 100644
index 0000000..c2deb69
--- /dev/null
+++ b/board/ti/j721e/Kconfig
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+# Lokesh Vutla <lokeshvutla@ti.com>
+
+choice
+ prompt "K3 J721E based boards"
+ optional
+
+config TARGET_J721E_A72_EVM
+ bool "TI K3 based J721E EVM running on A72"
+ select ARM64
+ select SOC_K3_J721E
+ select SYS_DISABLE_DCACHE_OPS
+
+config TARGET_J721E_R5_EVM
+ bool "TI K3 based J721E EVM running on R5"
+ select CPU_V7R
+ select SYS_THUMB_BUILD
+ select SOC_K3_J721E
+ select K3_LOAD_SYSFW
+ select RAM
+ select SPL_RAM
+ imply SYS_K3_SPL_ATF
+
+endchoice
+
+if TARGET_J721E_A72_EVM
+
+config SYS_BOARD
+ default "j721e"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_CONFIG_NAME
+ default "j721e_evm"
+
+endif
+
+if TARGET_J721E_R5_EVM
+
+config SYS_BOARD
+ default "j721e"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_CONFIG_NAME
+ default "j721e_evm"
+
+config SPL_LDSCRIPT
+ default "arch/arm/mach-omap2/u-boot-spl.lds"
+
+endif
diff --git a/board/ti/j721e/MAINTAINERS b/board/ti/j721e/MAINTAINERS
new file mode 100644
index 0000000..d51e899
--- /dev/null
+++ b/board/ti/j721e/MAINTAINERS
@@ -0,0 +1,7 @@
+J721E BOARD
+M: Lokesh Vutla <lokeshvutla@ti.com>
+S: Maintained
+F: board/ti/j721e
+F: include/configs/j721e_evm.h
+F: configs/j721e_evm_r5_defconfig
+F: configs/j721e_evm_a72_defconfig
diff --git a/board/ti/j721e/Makefile b/board/ti/j721e/Makefile
new file mode 100644
index 0000000..97535f5
--- /dev/null
+++ b/board/ti/j721e/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+# Lokesh Vutla <lokeshvutla@ti.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += evm.o
diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
new file mode 100644
index 0000000..db5d7b8
--- /dev/null
+++ b/board/ti/j721e/evm.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board specific initialization for J721E EVM
+ *
+ * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Lokesh Vutla <lokeshvutla@ti.com>
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <spl.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+#ifdef CONFIG_PHYS_64BIT
+ gd->ram_size = 0x100000000;
+#else
+ gd->ram_size = 0x80000000;
+#endif
+
+ return 0;
+}
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+#ifdef CONFIG_PHYS_64BIT
+ /* Limit RAM used by U-Boot to the DDR low region */
+ if (gd->ram_top > 0x100000000)
+ return 0x100000000;
+#endif
+
+ return gd->ram_top;
+}
+
+int dram_init_banksize(void)
+{
+ /* Bank 0 declares the memory available in the DDR low region */
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = 0x80000000;
+ gd->ram_size = 0x80000000;
+
+#ifdef CONFIG_PHYS_64BIT
+ /* Bank 1 declares the memory available in the DDR high region */
+ gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1;
+ gd->bd->bi_dram[1].size = 0x80000000;
+ gd->ram_size = 0x100000000;
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ if (!strcmp(name, "k3-j721e-common-proc-board"))
+ return 0;
+
+ return -1;
+}
+#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ int ret;
+
+ ret = fdt_fixup_msmc_ram(blob, "/interconnect@100000", "sram@70000000");
+ if (ret)
+ printf("%s: fixing up msmc ram failed %d\n", __func__, ret);
+
+ return ret;
+}
+#endif
diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index eed62e9..e9bc680 100644
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -8,6 +8,7 @@
#include <common.h>
#include "board.h"
+#include <env.h>
#include <spl.h>
#include <exports.h>
#include <fdt_support.h>
diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c
index 6d0fc21..4ff9a44 100644
--- a/board/ti/ks2_evm/board_k2g.c
+++ b/board/ti/ks2_evm/board_k2g.c
@@ -6,6 +6,7 @@
* Texas Instruments Incorporated, <www.ti.com>
*/
#include <common.h>
+#include <env.h>
#include <asm/arch/clock.h>
#include <asm/ti-common/keystone_net.h>
#include <asm/arch/psc_defs.h>
diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c
index f88aa4d..20199da 100644
--- a/board/ti/panda/panda.c
+++ b/board/ti/panda/panda.c
@@ -11,6 +11,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/gpio.h>
+#include <env.h>
#include <twl6030.h>
#include "panda_mux_data.h"
diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c
index d8ee51b..2b9385d 100644
--- a/board/ti/ti814x/evm.c
+++ b/board/ti/ti814x/evm.c
@@ -9,7 +9,7 @@
#include <common.h>
#include <cpsw.h>
-#include <environment.h>
+#include <env.h>
#include <errno.h>
#include <spl.h>
#include <asm/arch/cpu.h>
diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c
index 07a084b..8f7b591 100644
--- a/board/ti/ti816x/evm.c
+++ b/board/ti/ti816x/evm.c
@@ -7,9 +7,8 @@
*/
#include <common.h>
-#include <environment.h>
+#include <env.h>
#include <spl.h>
-#include <netdev.h>
#include <asm/cache.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
@@ -56,7 +55,7 @@
printf("Unable to read MAC address. Set <ethaddr>\n");
}
- return davinci_emac_initialize();
+ return 0;
}
#ifdef CONFIG_SPL_BUILD
diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c
index 50b70a5..490d8cb 100644
--- a/board/timll/devkit8000/devkit8000.c
+++ b/board/timll/devkit8000/devkit8000.c
@@ -17,7 +17,7 @@
*/
#include <common.h>
#include <dm.h>
-#include <environment.h>
+#include <env.h>
#include <ns16550.h>
#include <twl4030.h>
#include <asm/io.h>
diff --git a/board/toradex/apalis-imx8/apalis-imx8.c b/board/toradex/apalis-imx8/apalis-imx8.c
index f516e54..af48b56 100644
--- a/board/toradex/apalis-imx8/apalis-imx8.c
+++ b/board/toradex/apalis-imx8/apalis-imx8.c
@@ -12,7 +12,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/io.h>
-#include <environment.h>
+#include <env.h>
#include <errno.h>
#include <linux/libfdt.h>
@@ -37,22 +37,11 @@
int board_early_init_f(void)
{
- sc_pm_clock_rate_t rate;
+ sc_pm_clock_rate_t rate = SC_80MHZ;
sc_err_t err = 0;
- /* Power up UART1 */
- err = sc_pm_set_resource_power_mode(-1, SC_R_UART_1, SC_PM_PW_MODE_ON);
- if (err != SC_ERR_NONE)
- return 0;
-
- /* Set UART3 clock root to 80 MHz */
- rate = 80000000;
- err = sc_pm_set_clock_rate(-1, SC_R_UART_1, SC_PM_CLK_PER, &rate);
- if (err != SC_ERR_NONE)
- return 0;
-
- /* Enable UART1 clock root */
- err = sc_pm_clock_enable(-1, SC_R_UART_1, SC_PM_CLK_PER, true, false);
+ /* Set UART1 clock root to 80 MHz and enable it */
+ err = sc_pm_setup_uart(SC_R_UART_1, rate);
if (err != SC_ERR_NONE)
return 0;
@@ -82,19 +71,6 @@
}
#endif
-void build_info(void)
-{
- u32 sc_build = 0, sc_commit = 0;
-
- /* Get SCFW build and commit id */
- sc_misc_build_info(-1, &sc_build, &sc_commit);
- if (!sc_build) {
- printf("SCFW does not support build info\n");
- sc_commit = 0; /* Display 0 if build info not supported */
- }
- printf("Build: SCFW %x\n", sc_commit);
-}
-
int checkboard(void)
{
puts("Model: Toradex Apalis iMX8\n");
diff --git a/board/toradex/apalis-tk1/apalis-tk1.c b/board/toradex/apalis-tk1/apalis-tk1.c
index b87e9e7..bc98858 100644
--- a/board/toradex/apalis-tk1/apalis-tk1.c
+++ b/board/toradex/apalis-tk1/apalis-tk1.c
@@ -10,6 +10,7 @@
#include <asm/io.h>
#include <asm/arch/gpio.h>
#include <asm/arch/pinmux.h>
+#include <env_internal.h>
#include <pci_tegra.h>
#include <power/as3722.h>
#include <power/pmic.h>
@@ -19,11 +20,16 @@
#define LAN_DEV_OFF_N TEGRA_GPIO(O, 6)
#define LAN_RESET_N TEGRA_GPIO(S, 2)
+#define FAN_EN TEGRA_GPIO(DD, 2)
#define LAN_WAKE_N TEGRA_GPIO(O, 5)
#ifdef CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT
#define PEX_PERST_N TEGRA_GPIO(DD, 1) /* Apalis GPIO7 */
#define RESET_MOCI_CTRL TEGRA_GPIO(U, 4)
#endif /* CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT */
+#define VCC_USBH TEGRA_GPIO(T, 6)
+#define VCC_USBH_V1_0 TEGRA_GPIO(N, 5)
+#define VCC_USBO1 TEGRA_GPIO(T, 5)
+#define VCC_USBO1_V1_0 TEGRA_GPIO(N, 4)
int arch_misc_init(void)
{
@@ -31,6 +37,38 @@
NVBOOTTYPE_RECOVERY)
printf("USB recovery mode\n");
+ /* PCB Version Indication: V1.2 and later have GPIO_PV0 wired to GND */
+ gpio_request(TEGRA_GPIO(V, 0), "PCB Version Indication");
+ gpio_direction_input(TEGRA_GPIO(V, 0));
+ if (gpio_get_value(TEGRA_GPIO(V, 0))) {
+ /*
+ * if using the default device tree for new V1.2 and later HW,
+ * use version for older V1.0 and V1.1 HW
+ */
+ char *fdt_env = env_get("fdt_module");
+
+ if (fdt_env && !strcmp(FDT_MODULE, fdt_env)) {
+ env_set("fdt_module", FDT_MODULE_V1_0);
+ printf("patching fdt_module to " FDT_MODULE_V1_0
+ " for older V1.0 and V1.1 HW\n");
+#ifndef CONFIG_ENV_IS_NOWHERE
+ env_save();
+#endif
+ }
+
+ /* activate USB power enable GPIOs */
+ gpio_request(VCC_USBH_V1_0, "VCC_USBH");
+ gpio_direction_output(VCC_USBH_V1_0, 1);
+ gpio_request(VCC_USBO1_V1_0, "VCC_USBO1");
+ gpio_direction_output(VCC_USBO1_V1_0, 1);
+ } else {
+ /* activate USB power enable GPIOs */
+ gpio_request(VCC_USBH, "VCC_USBH");
+ gpio_direction_output(VCC_USBH, 1);
+ gpio_request(VCC_USBO1, "VCC_USBO1");
+ gpio_direction_output(VCC_USBO1, 1);
+ }
+
return 0;
}
@@ -242,6 +280,15 @@
#endif /* CONFIG_PCI_TEGRA */
/*
+ * Enable/start PWM CPU fan
+ */
+void start_cpu_fan(void)
+{
+ gpio_request(FAN_EN, "FAN_EN");
+ gpio_direction_output(FAN_EN, 1);
+}
+
+/*
* Backlight off before OS handover
*/
void board_preboot_os(void)
diff --git a/board/toradex/apalis-tk1/as3722_init.c b/board/toradex/apalis-tk1/as3722_init.c
index bd754e5..15f8dce 100644
--- a/board/toradex/apalis-tk1/as3722_init.c
+++ b/board/toradex/apalis-tk1/as3722_init.c
@@ -43,6 +43,29 @@
udelay(10 * 1000);
#endif
+ /*
+ * Make sure all non-fused regulators are down.
+ * That way we're in known state after software reboot from linux
+ */
+ tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+ tegra_i2c_ll_write_data(0x0003, I2C_SEND_2_BYTES);
+ udelay(10 * 1000);
+ tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+ tegra_i2c_ll_write_data(0x0004, I2C_SEND_2_BYTES);
+ udelay(10 * 1000);
+ tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+ tegra_i2c_ll_write_data(0x001b, I2C_SEND_2_BYTES);
+ udelay(10 * 1000);
+ tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+ tegra_i2c_ll_write_data(0x0014, I2C_SEND_2_BYTES);
+ udelay(10 * 1000);
+ tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+ tegra_i2c_ll_write_data(0x001a, I2C_SEND_2_BYTES);
+ udelay(10 * 1000);
+ tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+ tegra_i2c_ll_write_data(0x0019, I2C_SEND_2_BYTES);
+ udelay(10 * 1000);
+
debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__);
/*
* Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.
diff --git a/board/toradex/apalis-tk1/pinmux-config-apalis-tk1.h b/board/toradex/apalis-tk1/pinmux-config-apalis-tk1.h
index 1584d9b..6778a41 100644
--- a/board/toradex/apalis-tk1/pinmux-config-apalis-tk1.h
+++ b/board/toradex/apalis-tk1/pinmux-config-apalis-tk1.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (c) 2016, Toradex, Inc.
+ * Copyright (c) 2016-2019, Toradex, Inc.
*/
#ifndef _PINMUX_CONFIG_APALIS_TK1_H_
@@ -24,8 +24,6 @@
GPIO_INIT(K, 2, IN),
GPIO_INIT(K, 7, IN),
GPIO_INIT(N, 2, OUT1),
- GPIO_INIT(N, 4, OUT1),
- GPIO_INIT(N, 5, OUT1),
GPIO_INIT(N, 7, IN),
GPIO_INIT(O, 5, IN),
GPIO_INIT(Q, 0, OUT0), /* Shift_CTRL_OE[0] */
@@ -39,7 +37,8 @@
GPIO_INIT(R, 1, OUT0), /* Shift_CTRL_Dir_In[1] */
GPIO_INIT(R, 2, OUT0), /* Shift_CTRL_OE[3] */
GPIO_INIT(S, 3, OUT0), /* Shift_CTRL_Dir_In[2] */
- GPIO_INIT(U, 4, OUT1),
+ GPIO_INIT(U, 4, OUT0), /* RESET_MOCI_CTRL */
+ GPIO_INIT(V, 0, IN),
GPIO_INIT(W, 3, IN),
GPIO_INIT(W, 5, IN),
GPIO_INIT(BB, 0, IN),
@@ -130,8 +129,8 @@
PINCFG(DAP1_DIN_PN1, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP1_DOUT_PN2, SATA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP1_SCLK_PN3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(USB_VBUS_EN0_PN4, RSVD2, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
- PINCFG(USB_VBUS_EN1_PN5, RSVD2, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(USB_VBUS_EN0_PN4, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(USB_VBUS_EN1_PN5, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(HDMI_INT_PN7, RSVD1, DOWN, TRISTATE, INPUT, DEFAULT, NORMAL),
PINCFG(ULPI_DATA7_PO0, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA0_PO1, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
@@ -175,8 +174,8 @@
PINCFG(KB_ROW15_PS7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW16_PT0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW17_PT1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
- PINCFG(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(GEN2_I2C_SCL_PT5, RSVD2, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(GEN2_I2C_SDA_PT6, RSVD2, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PU0, UARTA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PU1, UARTA, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
@@ -185,12 +184,12 @@
PINCFG(PU4, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PU5, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PU6, PWM3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
- PINCFG(PV0, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PV0, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PV1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_CD_N_PV2, RSVD3, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC1_WP_N_PV3, SDMMC1, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
- PINCFG(DDC_SCL_PV4, RSVD2, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
- PINCFG(DDC_SDA_PV5, RSVD2, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
+ PINCFG(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
PINCFG(GPIO_W2_AUD_PW2, SPI2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_W3_AUD_PW3, SPI6, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c
index b502d4e..6421a22 100644
--- a/board/toradex/apalis_imx6/apalis_imx6.c
+++ b/board/toradex/apalis_imx6/apalis_imx6.c
@@ -26,8 +26,8 @@
#include <dm/device-internal.h>
#include <dm/platform_data/serial_mxc.h>
#include <dwc_ahsata.h>
-#include <environment.h>
-#include <fsl_esdhc.h>
+#include <env.h>
+#include <fsl_esdhc_imx.h>
#include <imx_thermal.h>
#include <micrel.h>
#include <miiphy.h>
@@ -131,7 +131,7 @@
MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
};
-#endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */
+#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
int mx6_rgmii_rework(struct phy_device *phydev)
{
@@ -355,7 +355,7 @@
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
}
-#endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */
+#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
int board_phy_config(struct phy_device *phydev)
{
diff --git a/board/toradex/colibri-imx6ull/colibri-imx6ull.c b/board/toradex/colibri-imx6ull/colibri-imx6ull.c
index 21addaf..d1ae463 100644
--- a/board/toradex/colibri-imx6ull/colibri-imx6ull.c
+++ b/board/toradex/colibri-imx6ull/colibri-imx6ull.c
@@ -17,6 +17,7 @@
#include <asm/io.h>
#include <dm.h>
#include <dm/platform_data/serial_mxc.h>
+#include <env.h>
#include <fdt_support.h>
#include <imx_thermal.h>
#include <jffs2/load_kernel.h>
diff --git a/board/toradex/colibri-imx8x/colibri-imx8x.c b/board/toradex/colibri-imx8x/colibri-imx8x.c
index aa8eaa0..eae3c59 100644
--- a/board/toradex/colibri-imx8x/colibri-imx8x.c
+++ b/board/toradex/colibri-imx8x/colibri-imx8x.c
@@ -12,7 +12,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/io.h>
-#include <environment.h>
+#include <env.h>
#include <errno.h>
#include <linux/libfdt.h>
@@ -51,19 +51,9 @@
if (err != SC_ERR_NONE)
return 0;
- /* Power up UART3 */
- err = sc_pm_set_resource_power_mode(-1, SC_R_UART_3, SC_PM_PW_MODE_ON);
- if (err != SC_ERR_NONE)
- return 0;
-
- /* Set UART3 clock root to 80 MHz */
- rate = 80000000;
- err = sc_pm_set_clock_rate(-1, SC_R_UART_3, SC_PM_CLK_PER, &rate);
- if (err != SC_ERR_NONE)
- return 0;
-
- /* Enable UART3 clock root */
- err = sc_pm_clock_enable(-1, SC_R_UART_3, SC_PM_CLK_PER, true, false);
+ /* Set UART3 clock root to 80 MHz and enable it */
+ rate = SC_80MHZ;
+ err = sc_pm_setup_uart(SC_R_UART_3, rate);
if (err != SC_ERR_NONE)
return 0;
@@ -93,19 +83,6 @@
}
#endif
-void build_info(void)
-{
- u32 sc_build = 0, sc_commit = 0;
-
- /* Get SCFW build and commit id */
- sc_misc_build_info(-1, &sc_build, &sc_commit);
- if (!sc_build) {
- printf("SCFW does not support build info\n");
- sc_commit = 0; /* Display 0 if build info not supported */
- }
- printf("Build: SCFW %x\n", sc_commit);
-}
-
int checkboard(void)
{
puts("Model: Toradex Colibri iMX8X\n");
diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c
index c634e32..ad40b58 100644
--- a/board/toradex/colibri_imx6/colibri_imx6.c
+++ b/board/toradex/colibri_imx6/colibri_imx6.c
@@ -8,6 +8,7 @@
#include <common.h>
#include <dm.h>
+#include <env.h>
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
@@ -24,8 +25,7 @@
#include <asm/mach-imx/video.h>
#include <cpu.h>
#include <dm/platform_data/serial_mxc.h>
-#include <environment.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <imx_thermal.h>
#include <micrel.h>
#include <miiphy.h>
@@ -110,7 +110,7 @@
MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
-#endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */
+#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
iomux_v3_cfg_t const enet_pads[] = {
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
@@ -361,7 +361,7 @@
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
}
-#endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */
+#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
int board_phy_config(struct phy_device *phydev)
{
diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c
index 61bf8bf..0eb8347 100644
--- a/board/toradex/colibri_imx7/colibri_imx7.c
+++ b/board/toradex/colibri_imx7/colibri_imx7.c
@@ -15,7 +15,7 @@
#include <dm.h>
#include <dm/platform_data/serial_mxc.h>
#include <fdt_support.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <jffs2/load_kernel.h>
#include <linux/sizes.h>
#include <mmc.h>
diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c
index 9d63fbf..04d8ffd 100644
--- a/board/toradex/colibri_vf/colibri_vf.c
+++ b/board/toradex/colibri_vf/colibri_vf.c
@@ -15,6 +15,7 @@
#include <asm/arch/iomux-vf610.h>
#include <asm/gpio.h>
#include <asm/io.h>
+#include <env.h>
#include <fdt_support.h>
#include <fsl_dcu_fb.h>
#include <g_dnl.h>
@@ -430,7 +431,9 @@
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, bd_t *bd)
{
+#ifndef CONFIG_DM_VIDEO
int ret = 0;
+#endif
#ifdef CONFIG_FDT_FIXUP_PARTITIONS
static const struct node_info nodes[] = {
{ "fsl,vf610-nfc", MTD_DEV_TYPE_NAND, }, /* NAND flash */
@@ -440,7 +443,7 @@
puts(" Updating MTD partitions...\n");
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
#endif
-#ifdef CONFIG_VIDEO_FSL_DCU_FB
+#if defined(CONFIG_VIDEO_FSL_DCU_FB) && !defined(CONFIG_DM_VIDEO)
ret = fsl_dcu_fixedfb_setup(blob);
if (ret)
return ret;
diff --git a/board/toradex/colibri_vf/dcu.c b/board/toradex/colibri_vf/dcu.c
index c36e90c..c688ed7 100644
--- a/board/toradex/colibri_vf/dcu.c
+++ b/board/toradex/colibri_vf/dcu.c
@@ -26,11 +26,13 @@
return div;
}
-int platform_dcu_init(unsigned int xres, unsigned int yres,
+int platform_dcu_init(struct fb_info *fbinfo,
+ unsigned int xres,
+ unsigned int yres,
const char *port,
struct fb_videomode *dcu_fb_videomode)
{
- fsl_dcu_init(xres, yres, 32);
+ fsl_dcu_init(fbinfo, xres, yres, 32);
return 0;
}
diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c
index f69c443..9c86230 100644
--- a/board/toradex/common/tdx-cfg-block.c
+++ b/board/toradex/common/tdx-cfg-block.c
@@ -7,8 +7,9 @@
#include "tdx-cfg-block.h"
#if defined(CONFIG_TARGET_APALIS_IMX6) || \
+ defined(CONFIG_TARGET_APALIS_IMX8) || \
defined(CONFIG_TARGET_COLIBRI_IMX6) || \
- defined(CONFIG_TARGET_COLIBRI_IMX8QXP)
+ defined(CONFIG_TARGET_COLIBRI_IMX8X)
#include <asm/arch/sys_proto.h>
#else
#define is_cpu_type(cpu) (0)
@@ -20,6 +21,7 @@
#endif
#include <cli.h>
#include <console.h>
+#include <env.h>
#include <flash.h>
#include <malloc.h>
#include <mmc.h>
@@ -129,6 +131,10 @@
ret = -ENODEV;
goto out;
}
+ if (mmc_init(mmc)) {
+ puts("MMC init failed\n");
+ return -EINVAL;
+ }
if (part != mmc_get_blk_desc(mmc)->hwpart) {
if (blk_select_hwpart_devnum(IF_TYPE_MMC, dev, part)) {
puts("MMC partition switch failed\n");
@@ -287,6 +293,7 @@
char message[CONFIG_SYS_CBSIZE];
char *soc;
char it = 'n';
+ char wb = 'n';
int len;
/* Unknown module by default */
@@ -296,10 +303,17 @@
sprintf(message, "Is the module the 312 MHz version? [y/N] ");
else
sprintf(message, "Is the module an IT version? [y/N] ");
-
len = cli_readline(message);
it = console_buffer[0];
+#if defined(CONFIG_TARGET_APALIS_IMX8) || \
+ defined(CONFIG_TARGET_COLIBRI_IMX6ULL) || \
+ defined(CONFIG_TARGET_COLIBRI_IMX8X)
+ sprintf(message, "Does the module have Wi-Fi / Bluetooth? [y/N] ");
+ len = cli_readline(message);
+ wb = console_buffer[0];
+#endif
+
soc = env_get("soc");
if (!strcmp("mx6", soc)) {
#ifdef CONFIG_TARGET_APALIS_IMX6
@@ -327,12 +341,6 @@
tdx_hw_tag.prodid = COLIBRI_IMX6S;
}
#elif CONFIG_TARGET_COLIBRI_IMX6ULL
- char wb = 'n';
-
- sprintf(message, "Does the module have Wi-Fi / Bluetooth? " \
- "[y/N] ");
- len = cli_readline(message);
- wb = console_buffer[0];
if (it == 'y' || it == 'Y') {
if (wb == 'y' || wb == 'Y')
tdx_hw_tag.prodid = COLIBRI_IMX6ULL_WIFI_BT_IT;
@@ -349,9 +357,31 @@
tdx_hw_tag.prodid = COLIBRI_IMX7D;
else if (!strcmp("imx7s", soc))
tdx_hw_tag.prodid = COLIBRI_IMX7S;
- else if (is_cpu_type(MXC_CPU_IMX8QXP))
- tdx_hw_tag.prodid = COLIBRI_IMX8QXP_WIFI_BT_IT;
- else if (!strcmp("tegra20", soc)) {
+ else if (is_cpu_type(MXC_CPU_IMX8QM)) {
+ if (it == 'y' || it == 'Y') {
+ if (wb == 'y' || wb == 'Y')
+ tdx_hw_tag.prodid = APALIS_IMX8QM_WIFI_BT_IT;
+ else
+ tdx_hw_tag.prodid = APALIS_IMX8QM_IT;
+ } else {
+ if (wb == 'y' || wb == 'Y')
+ tdx_hw_tag.prodid = APALIS_IMX8QP_WIFI_BT;
+ else
+ tdx_hw_tag.prodid = APALIS_IMX8QP;
+ }
+ } else if (is_cpu_type(MXC_CPU_IMX8QXP)) {
+ if (it == 'y' || it == 'Y') {
+ if (wb == 'y' || wb == 'Y')
+ tdx_hw_tag.prodid = COLIBRI_IMX8QXP_WIFI_BT_IT;
+ else
+ tdx_hw_tag.prodid = COLIBRI_IMX8QXP_IT;
+ } else {
+ if (wb == 'y' || wb == 'Y')
+ tdx_hw_tag.prodid = COLIBRI_IMX8DX_WIFI_BT;
+ else
+ tdx_hw_tag.prodid = COLIBRI_IMX8DX;
+ }
+ } else if (!strcmp("tegra20", soc)) {
if (it == 'y' || it == 'Y')
if (gd->ram_size == 0x10000000)
tdx_hw_tag.prodid = COLIBRI_T20_256MB_IT;
@@ -482,8 +512,7 @@
* On NAND devices, recreation is only allowed if the page is
* empty (config block invalid...)
*/
- printf("NAND erase block %d need to be erased before creating" \
- " a Toradex config block\n",
+ printf("NAND erase block %d need to be erased before creating a Toradex config block\n",
CONFIG_TDX_CFG_BLOCK_OFFSET /
get_nand_dev_by_index(0)->erasesize);
goto out;
@@ -492,8 +521,7 @@
* On NOR devices, recreation is only allowed if the sector is
* empty and write protection is off (config block invalid...)
*/
- printf("NOR sector at offset 0x%02x need to be erased and " \
- "unprotected before creating a Toradex config block\n",
+ printf("NOR sector at offset 0x%02x need to be erased and unprotected before creating a Toradex config block\n",
CONFIG_TDX_CFG_BLOCK_OFFSET);
goto out;
#else
@@ -604,9 +632,8 @@
return CMD_RET_USAGE;
}
-U_BOOT_CMD(
- cfgblock, 4, 0, do_cfgblock,
- "Toradex config block handling commands",
- "create [-y] [barcode] - (Re-)create Toradex config block\n"
- "cfgblock reload - Reload Toradex config block from flash"
+U_BOOT_CMD(cfgblock, 4, 0, do_cfgblock,
+ "Toradex config block handling commands",
+ "create [-y] [barcode] - (Re-)create Toradex config block\n"
+ "cfgblock reload - Reload Toradex config block from flash"
);
diff --git a/board/toradex/common/tdx-common.c b/board/toradex/common/tdx-common.c
index 2d560cc..e9441a7 100644
--- a/board/toradex/common/tdx-common.c
+++ b/board/toradex/common/tdx-common.c
@@ -4,7 +4,7 @@
*/
#include <common.h>
-#include <environment.h>
+#include <env.h>
#include <g_dnl.h>
#include <linux/libfdt.h>
diff --git a/board/tqc/tqma6/tqma6.c b/board/tqc/tqma6/tqma6.c
index 372a17c..5b20afd 100644
--- a/board/tqc/tqma6/tqma6.c
+++ b/board/tqc/tqma6/tqma6.c
@@ -12,13 +12,14 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/sys_proto.h>
+#include <env.h>
#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/spi.h>
#include <common.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <linux/libfdt.h>
#include <i2c.h>
#include <mmc.h>
diff --git a/board/tqc/tqma6/tqma6_mba6.c b/board/tqc/tqma6/tqma6_mba6.c
index f7072b8..8a2431e 100644
--- a/board/tqc/tqma6/tqma6_mba6.c
+++ b/board/tqc/tqma6/tqma6_mba6.c
@@ -18,7 +18,7 @@
#include <asm/mach-imx/mxc_i2c.h>
#include <common.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <linux/libfdt.h>
#include <malloc.h>
#include <i2c.h>
diff --git a/board/tqc/tqma6/tqma6_wru4.c b/board/tqc/tqma6/tqma6_wru4.c
index aaee9bf..99196ad 100644
--- a/board/tqc/tqma6/tqma6_wru4.c
+++ b/board/tqc/tqma6/tqma6_wru4.c
@@ -21,7 +21,7 @@
#include <asm/mach-imx/mxc_i2c.h>
#include <common.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <linux/libfdt.h>
#include <malloc.h>
#include <i2c.h>
diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c
index 8281613..5c468a6 100644
--- a/board/udoo/neo/neo.c
+++ b/board/udoo/neo/neo.c
@@ -15,8 +15,9 @@
#include <asm/arch/mx6-pins.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
+#include <env.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
#include <asm/mach-imx/mxc_i2c.h>
diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c
index 491e9be..f2c2bf4 100644
--- a/board/udoo/udoo.c
+++ b/board/udoo/udoo.c
@@ -8,6 +8,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
+#include <env.h>
#include <malloc.h>
#include <asm/arch/mx6-pins.h>
#include <linux/errno.h>
@@ -15,7 +16,7 @@
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/sata.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
diff --git a/board/udoo/udoo_spl.c b/board/udoo/udoo_spl.c
index 30663e2..b287fbf 100644
--- a/board/udoo/udoo_spl.c
+++ b/board/udoo/udoo_spl.c
@@ -15,7 +15,7 @@
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/video.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
diff --git a/board/vamrs/rock960_rk3399/MAINTAINERS b/board/vamrs/rock960_rk3399/MAINTAINERS
index 22b2db9..5ee5256 100644
--- a/board/vamrs/rock960_rk3399/MAINTAINERS
+++ b/board/vamrs/rock960_rk3399/MAINTAINERS
@@ -1,11 +1,11 @@
ROCK960-RK3399
-M: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
+M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
S: Maintained
F: board/rockchip/rock960_rk3399
F: include/configs/rock960_rk3399.h
F: configs/rock960-rk3399_defconfig
FICUS EE
-M: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
+M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
S: Maintained
F: configs/ficus-rk3399_defconfig
diff --git a/board/vamrs/rock960_rk3399/rock960-rk3399.c b/board/vamrs/rock960_rk3399/rock960-rk3399.c
index 2eb7120..68a127b 100644
--- a/board/vamrs/rock960_rk3399/rock960-rk3399.c
+++ b/board/vamrs/rock960_rk3399/rock960-rk3399.c
@@ -2,18 +2,3 @@
/*
* Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
*/
-
-#include <common.h>
-#include <dm.h>
-#include <power/regulator.h>
-
-int board_init(void)
-{
- int ret;
-
- ret = regulators_enable_boot_on(false);
- if (ret)
- debug("%s: Cannot enable boot on regulator\n", __func__);
-
- return 0;
-}
diff --git a/board/variscite/dart_6ul/dart_6ul.c b/board/variscite/dart_6ul/dart_6ul.c
index 4765595..2d0b760 100644
--- a/board/variscite/dart_6ul/dart_6ul.c
+++ b/board/variscite/dart_6ul/dart_6ul.c
@@ -10,7 +10,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <linux/bitops.h>
#include <miiphy.h>
#include <netdev.h>
diff --git a/board/variscite/dart_6ul/spl.c b/board/variscite/dart_6ul/spl.c
index f7e6ab6..798523d 100644
--- a/board/variscite/dart_6ul/spl.c
+++ b/board/variscite/dart_6ul/spl.c
@@ -11,7 +11,7 @@
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/crm_regs.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
diff --git a/board/varisys/common/sys_eeprom.c b/board/varisys/common/sys_eeprom.c
index dea9af9..77772a6 100644
--- a/board/varisys/common/sys_eeprom.c
+++ b/board/varisys/common/sys_eeprom.c
@@ -12,6 +12,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <i2c.h>
#include <linux/ctype.h>
diff --git a/board/varisys/cyrus/cyrus.c b/board/varisys/cyrus/cyrus.c
index 4ccce8a..fa02fef 100644
--- a/board/varisys/cyrus/cyrus.c
+++ b/board/varisys/cyrus/cyrus.c
@@ -5,6 +5,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <netdev.h>
#include <linux/compiler.h>
#include <asm/mmu.h>
diff --git a/board/vscom/baltos/board.c b/board/vscom/baltos/board.c
index c5949ad..1ba58d0 100644
--- a/board/vscom/baltos/board.c
+++ b/board/vscom/baltos/board.c
@@ -8,6 +8,7 @@
*/
#include <common.h>
+#include <env.h>
#include <errno.h>
#include <linux/libfdt.h>
#include <spl.h>
@@ -28,7 +29,6 @@
#include <miiphy.h>
#include <cpsw.h>
#include <power/tps65910.h>
-#include <environment.h>
#include <watchdog.h>
#include "board.h"
@@ -288,15 +288,15 @@
mac_addr[5] = header.MAC1[5];
- node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100200");
+ node = fdt_path_offset(blob, "ethernet0");
if (node < 0) {
- printf("no /soc/fman/ethernet path offset\n");
+ printf("no ethernet0 path offset\n");
return -ENODEV;
}
ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
if (ret) {
- printf("error setting local-mac-address property\n");
+ printf("error setting mac-address property\n");
return -ENODEV;
}
@@ -308,15 +308,15 @@
mac_addr[4] = header.MAC2[4];
mac_addr[5] = header.MAC2[5];
- node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100300");
+ node = fdt_path_offset(blob, "ethernet1");
if (node < 0) {
- printf("no /soc/fman/ethernet path offset\n");
+ printf("no ethernet1 path offset\n");
return -ENODEV;
}
ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
if (ret) {
- printf("error setting local-mac-address property\n");
+ printf("error setting mac-address property\n");
return -ENODEV;
}
diff --git a/board/wandboard/spl.c b/board/wandboard/spl.c
index 7b0f15a..dbd9d02 100644
--- a/board/wandboard/spl.c
+++ b/board/wandboard/spl.c
@@ -14,7 +14,7 @@
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/video.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index 74d7a17..69cdf3e 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -20,6 +20,7 @@
#include <asm/mach-imx/video.h>
#include <asm/mach-imx/sata.h>
#include <asm/io.h>
+#include <env.h>
#include <linux/sizes.h>
#include <common.h>
#include <miiphy.h>
diff --git a/board/warp/warp.c b/board/warp/warp.c
index f346b92..a44a578 100644
--- a/board/warp/warp.c
+++ b/board/warp/warp.c
@@ -19,7 +19,7 @@
#include <linux/sizes.h>
#include <common.h>
#include <watchdog.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <i2c.h>
#include <mmc.h>
#include <usb.h>
diff --git a/board/warp7/warp7.c b/board/warp7/warp7.c
index 134a6c9..39ae982 100644
--- a/board/warp7/warp7.c
+++ b/board/warp7/warp7.c
@@ -13,6 +13,7 @@
#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
#include <common.h>
+#include <env.h>
#include <asm/arch/crm_regs.h>
#include <netdev.h>
#include <power/pmic.h>
diff --git a/board/woodburn/woodburn.c b/board/woodburn/woodburn.c
index 42633ed..5cab3f4 100644
--- a/board/woodburn/woodburn.c
+++ b/board/woodburn/woodburn.c
@@ -17,7 +17,7 @@
#include <fsl_pmic.h>
#include <mc13892.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <linux/types.h>
#include <asm/gpio.h>
#include <asm/arch/sys_proto.h>
@@ -206,7 +206,7 @@
return 0;
}
-#if defined(CONFIG_FSL_ESDHC)
+#if defined(CONFIG_FSL_ESDHC_IMX)
struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};
int board_mmc_init(bd_t *bis)
diff --git a/board/work-microwave/work_92105/work_92105_display.c b/board/work-microwave/work_92105/work_92105_display.c
index ffa0fcf..db04dca 100644
--- a/board/work-microwave/work_92105/work_92105_display.c
+++ b/board/work-microwave/work_92105/work_92105_display.c
@@ -15,6 +15,7 @@
#include <asm/arch/cpu.h>
#include <asm/arch/emc.h>
#include <asm/gpio.h>
+#include <env.h>
#include <spi.h>
#include <i2c.h>
#include <version.h>
diff --git a/board/xes/common/board.c b/board/xes/common/board.c
index 66467c6..43575bc 100644
--- a/board/xes/common/board.c
+++ b/board/xes/common/board.c
@@ -4,6 +4,7 @@
*/
#include <common.h>
+#include <env.h>
#include "fsl_8xxx_misc.h"
int checkboard(void)
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 6857f2c..35191b2 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <dm/uclass.h>
+#include <env.h>
#include <fdtdec.h>
#include <fpga.h>
#include <malloc.h>
diff --git a/board/xilinx/zynq/zynq-zturn/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zturn/ps7_init_gpl.c
new file mode 100644
index 0000000..d4f0ee7
--- /dev/null
+++ b/board/xilinx/zynq/zynq-zturn/ps7_init_gpl.c
@@ -0,0 +1,281 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) Xilinx, Inc.
+ */
+
+#include <asm/arch/ps7_init_gpl.h>
+
+static unsigned long ps7_pll_init_data[] = {
+ EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+ EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+ EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+ EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+ EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+ EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+ EMIT_WRITE(0xF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data[] = {
+ EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+ EMIT_MASKWRITE(0xF8000138, 0x00000011U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000140, 0x03F03F71U, 0x00100801U),
+ EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0xF8000150, 0x00003F33U, 0x00001401U),
+ EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00000A03U),
+ EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00200501U),
+ EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00200500U),
+ EMIT_MASKWRITE(0xF8000180, 0x03F03F30U, 0x00400500U),
+ EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01FD044DU),
+ EMIT_WRITE(0xF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data[] = {
+ EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001082U),
+ EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+ EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+ EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004285BU),
+ EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E458D3U),
+ EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x7282BCE5U),
+ EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x270872D0U),
+ EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+ EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+ EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040B30U),
+ EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+ EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+ EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+ EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U),
+ EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+ EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U),
+ EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+ EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+ EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+ EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+ EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+ EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+ EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+ EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+ EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U),
+ EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+ EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+ EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x0002A81FU),
+ EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00029822U),
+ EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x00026C10U),
+ EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00026013U),
+ EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000009FU),
+ EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000A2U),
+ EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x00000090U),
+ EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x00000093U),
+ EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x000000FFU),
+ EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x000000FBU),
+ EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x000000F0U),
+ EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x000000EDU),
+ EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000DFU),
+ EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000E2U),
+ EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000D0U),
+ EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000D3U),
+ EMIT_MASKWRITE(0xF8006190, 0x6FFFFEFEU, 0x00040080U),
+ EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+ EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+ EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+ EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+ EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+ EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data[] = {
+ EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+ EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000260U),
+ EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+ EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U),
+ EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x000016E1U),
+ EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x000016E0U),
+ EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00001640U),
+ EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00001640U),
+ EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00001621U),
+ EMIT_MASKWRITE(0xF800073C, 0x00003FFFU, 0x00001620U),
+ EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0xF80007B8, 0x00003F01U, 0x00000201U),
+ EMIT_MASKWRITE(0xF80007BC, 0x00003F01U, 0x00000201U),
+ EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x000012E0U),
+ EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x000012E1U),
+ EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000200U),
+ EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000200U),
+ EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0xF8000830, 0x003F003FU, 0x002E002FU),
+ EMIT_WRITE(0xF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data[] = {
+ EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+ EMIT_WRITE(0xF8000004, 0x0000767BU),
+ EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU),
+ EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
+ EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000007CU),
+ EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0xE0000004, 0x000003FFU, 0x00000020U),
+ EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+ EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+ EMIT_MASKWRITE(0xE000A244, 0x003FFFFFU, 0x00080000U),
+ EMIT_MASKWRITE(0xE000A00C, 0x003F003FU, 0x00370008U),
+ EMIT_MASKWRITE(0xE000A248, 0x003FFFFFU, 0x00080000U),
+ EMIT_MASKWRITE(0xE000A00C, 0x003F003FU, 0x00370000U),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKWRITE(0xE000A00C, 0x003F003FU, 0x00370008U),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_0[] = {
+ EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+ EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_WRITE(0xF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+int ps7_post_config(void)
+{
+ return ps7_config(ps7_post_config_0);
+}
+
+int ps7_init(void)
+{
+ int ret;
+
+ ret = ps7_config(ps7_mio_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_pll_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_clock_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_ddr_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_peripherals_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ return PS7_INIT_SUCCESS;
+}
diff --git a/board/xilinx/zynqmp/MAINTAINERS b/board/xilinx/zynqmp/MAINTAINERS
index efc1d35..04fc7f3 100644
--- a/board/xilinx/zynqmp/MAINTAINERS
+++ b/board/xilinx/zynqmp/MAINTAINERS
@@ -7,3 +7,9 @@
F: include/configs/xilinx_zynqmp*
F: configs/xilinx_zynqmp*
F: configs/avnet_ultra96_rev1_defconfig
+
+ARM ZYNQMP AVNET ULTRAZED EV BOARD
+M: Luca Ceresoli <luca@lucaceresoli.net>
+S: Maintained
+F: arch/arm/dts/avnet-ultrazedev-*
+F: configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig
diff --git a/board/xilinx/zynqmp/Makefile b/board/xilinx/zynqmp/Makefile
index 80f8ca7..5ace6cc 100644
--- a/board/xilinx/zynqmp/Makefile
+++ b/board/xilinx/zynqmp/Makefile
@@ -33,6 +33,13 @@
obj-y += $(init-objs)
endif
+ifdef CONFIG_SPL_BUILD
+ifneq ($(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE),"")
+obj-$(CONFIG_SPL_BUILD) += pm_cfg_obj.o
+$(obj)/pm_cfg_obj.o: $(shell cd $(srctree); readlink -f $(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE)) FORCE
+endif
+endif
+
obj-$(CONFIG_MMC_SDHCI_ZYNQ) += tap_delays.o
ifndef CONFIG_SPL_BUILD
diff --git a/board/xilinx/zynqmp/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0/psu_init_gpl.c b/board/xilinx/zynqmp/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0/psu_init_gpl.c
new file mode 100644
index 0000000..ac3f716
--- /dev/null
+++ b/board/xilinx/zynqmp/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0/psu_init_gpl.c
@@ -0,0 +1,663 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+ psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014800U);
+ psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+ mask_poll(0xFF5E0040, 0x00000002U);
+ psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
+ psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
+ psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U);
+ psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+ mask_poll(0xFF5E0040, 0x00000001U);
+ psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014200U);
+ psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000001U);
+ psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014800U);
+ psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000002U);
+ psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U);
+ psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U);
+ psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000004U);
+ psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+
+ return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+ psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U);
+ psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+ psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+ psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U);
+ psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
+ psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010602U);
+ psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010602U);
+ psu_mask_write(0xFF18030C, 0x00020003U, 0x00000000U);
+ psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+ psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+ psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+ psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+ psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U);
+ psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+ psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A00B4, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U);
+ psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011003U);
+ psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010F03U);
+ psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+ psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+ psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+ psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000303U);
+ psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+ psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+ psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+ psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U);
+ psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+ psu_mask_write(0xFD070020, 0x000003F3U, 0x00000300U);
+ psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+ psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+ psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00409410U);
+ psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+ psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+ psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+ psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x009280D2U);
+ psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+ psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+ psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0048051FU);
+ psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020126U);
+ psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+ psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002705U);
+ psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x09340301U);
+ psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00280200U);
+ psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+ psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+ psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+ psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+ psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+ psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x131C2813U);
+ psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0004041CU);
+ psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0808050FU);
+ psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+ psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U);
+ psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+ psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+ psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+ psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x05050D08U);
+ psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002040CU);
+ psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1308010EU);
+ psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+ psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+ psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x0201C9C2U);
+ psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048C820DU);
+ psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+ psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+ psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+ psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+ psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
+ psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000A0BU);
+ psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+ psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+ psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U);
+ psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+ psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
+ psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+ psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U);
+ psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x07070707U);
+ psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+ psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F08U);
+ psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U);
+ psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U);
+ psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U);
+ psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U);
+ psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+ psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+ psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+ psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+ psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+ psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+ psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+ psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+ psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+ psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+ psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+ psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+ psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+ psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+ psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+ psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+ psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F12090U);
+ psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+ psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+ psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x4B025810U);
+ psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xEA601518U);
+ psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x000E0000U);
+ psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+ psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000DDU);
+ psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+ psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x08261009U);
+ psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28380008U);
+ psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U);
+ psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+ psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01A42B08U);
+ psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00371009U);
+ psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00001010U);
+ psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+ psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+ psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000300U);
+ psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000834U);
+ psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+ psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000028U);
+ psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+ psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+ psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+ psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+ psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+ psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+ psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+ psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+ psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+ psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+ psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+ psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+ psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+ psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+ psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+ psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+ psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+ psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+ psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+ psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AEA58U);
+ psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+ psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+ psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+ psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+ psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
+ psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
+ psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
+ psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
+ psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U);
+ psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U);
+ psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U);
+ psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U);
+ psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U);
+ psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U);
+ psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
+ psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
+ psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+ psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
+ psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U);
+ psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x000E0000U);
+ psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x000E0000U);
+ psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x000E0000U);
+ psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x000E0000U);
+ psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
+ psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x200E0000U);
+ psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
+ psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
+ psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x000E0000U);
+ psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_qos_init_data(void)
+{
+ return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+ psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180034, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180038, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180040, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180044, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180048, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180050, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180054, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180058, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180060, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF180064, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U);
+ psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U);
+ psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U);
+ psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U);
+ psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180080, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180084, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180088, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF18008C, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180090, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x50000000U);
+ psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02006U);
+ psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
+ psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_peripherals_pre_init_data(void)
+{
+ psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
+
+ return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+ psu_mask_write(0xFD1A0100, 0x000F807EU, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+ psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
+ psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000060U, 0x00000000U);
+ psu_mask_write(0xFF180310, 0x00008001U, 0x00000001U);
+ psu_mask_write(0xFF180320, 0x33843384U, 0x00801284U);
+ psu_mask_write(0xFF18031C, 0x00007FFEU, 0x00006450U);
+ psu_mask_write(0xFF180358, 0x00080000U, 0x00080000U);
+ psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
+ psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF180324, 0x000003C0U, 0x00000000U);
+ psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000400U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+ psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
+ psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
+ psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
+ psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
+ psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
+ psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
+ psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
+ psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
+ psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+ psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+ psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+ psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+ psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U);
+ psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+
+ mask_delay(1);
+ psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U);
+
+ mask_delay(5);
+ psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+ psu_mask_write(0xFF0A0244, 0x03FFFFFFU, 0x00000020U);
+ psu_mask_write(0xFF0A0248, 0x03FFFFFFU, 0x00000020U);
+ psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0020U);
+ mask_delay(1);
+ psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0000U);
+ mask_delay(5);
+
+ return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+ psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+ psu_mask_write(0xFD615000, 0x00000F00U, 0x00000A00U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+ unsigned int regval = 0;
+ unsigned int pll_retry = 10;
+ unsigned int pll_locked = 0;
+
+ while ((pll_retry > 0) && (!pll_locked)) {
+ Xil_Out32(0xFD080004, 0x00040010);
+ Xil_Out32(0xFD080004, 0x00040011);
+
+ while ((Xil_In32(0xFD080030) & 0x1) != 1)
+ ;
+ pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
+ >> 31;
+ pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
+ >> 16;
+ pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000)
+ >> 16;
+ pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000)
+ >> 16;
+ pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000)
+ >> 16;
+ pll_retry--;
+ }
+ Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
+ if (!pll_locked)
+ return 0;
+
+ Xil_Out32(0xFD080004U, 0x00040063U);
+
+ while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+ ;
+ prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+ while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+ ;
+ Xil_Out32(0xFD0701B0U, 0x00000001U);
+ Xil_Out32(0xFD070320U, 0x00000001U);
+ while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+ ;
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+ Xil_Out32(0xFD080004, 0x0004FE01);
+ regval = Xil_In32(0xFD080030);
+ while (regval != 0x80000FFF)
+ regval = Xil_In32(0xFD080030);
+ regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
+ if (regval != 0)
+ return 0;
+
+ Xil_Out32(0xFD080200U, 0x100091C7U);
+ int cur_R006_tREFPRD;
+
+ cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U;
+ prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+ prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+ prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+ Xil_Out32(0xFD080004, 0x00060001);
+ regval = Xil_In32(0xFD080030);
+ while ((regval & 0x80004001) != 0x80004001)
+ regval = Xil_In32(0xFD080030);
+
+ prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+ prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+ Xil_Out32(0xFD080200U, 0x800091C7U);
+ prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+ Xil_Out32(0xFD080004, 0x0000C001);
+ regval = Xil_In32(0xFD080030);
+ while ((regval & 0x80000C01) != 0x80000C01)
+ regval = Xil_In32(0xFD080030);
+
+ Xil_Out32(0xFD070180U, 0x01000040U);
+ Xil_Out32(0xFD070060U, 0x00000000U);
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+ return 1;
+}
+
+static void init_peripheral(void)
+{
+ psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+int psu_init(void)
+{
+ int status = 1;
+
+ status &= psu_mio_init_data();
+ status &= psu_peripherals_pre_init_data();
+ status &= psu_pll_init_data();
+ status &= psu_clock_init_data();
+ status &= psu_ddr_init_data();
+ status &= psu_ddr_phybringup_data();
+ status &= psu_peripherals_init_data();
+ init_peripheral();
+
+ status &= psu_afi_config();
+ psu_ddr_qos_init_data();
+
+ if (status == 0)
+ return 1;
+ return 0;
+}
diff --git a/board/xilinx/zynqmp/cmds.c b/board/xilinx/zynqmp/cmds.c
index 321670d..ed7ba58 100644
--- a/board/xilinx/zynqmp/cmds.c
+++ b/board/xilinx/zynqmp/cmds.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
+#include <env.h>
#include <malloc.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
diff --git a/board/xilinx/zynqmp/pm_cfg_obj.S b/board/xilinx/zynqmp/pm_cfg_obj.S
new file mode 100644
index 0000000..c4ca77e
--- /dev/null
+++ b/board/xilinx/zynqmp/pm_cfg_obj.S
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+.section .rodata
+
+.global zynqmp_pm_cfg_obj
+.type zynqmp_pm_cfg_obj, @object
+.global zynqmp_pm_cfg_obj_size
+.type zynqmp_pm_cfg_obj_size, @object
+
+zynqmp_pm_cfg_obj:
+.align 4
+.incbin CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE
+
+zynqmp_pm_cfg_obj_end:
+
+zynqmp_pm_cfg_obj_size:
+.int zynqmp_pm_cfg_obj_end - zynqmp_pm_cfg_obj
diff --git a/board/xilinx/zynqmp/pm_cfg_obj.h b/board/xilinx/zynqmp/pm_cfg_obj.h
new file mode 100644
index 0000000..86e7854
--- /dev/null
+++ b/board/xilinx/zynqmp/pm_cfg_obj.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Luca Ceresoli <luca@lucaceresoli.net>
+ *
+ * Declaration of PMU config object binary blob linked in at build time.
+ */
+
+extern const u32 zynqmp_pm_cfg_obj[];
+extern const int zynqmp_pm_cfg_obj_size;
diff --git a/board/xilinx/zynqmp/xil_io.h b/board/xilinx/zynqmp/xil_io.h
index c476c90..1c1bf32 100644
--- a/board/xilinx/zynqmp/xil_io.h
+++ b/board/xilinx/zynqmp/xil_io.h
@@ -9,17 +9,17 @@
#define xil_printf(...)
-void Xil_Out32(unsigned long addr, unsigned long val)
+static void Xil_Out32(unsigned long addr, unsigned long val)
{
writel(val, addr);
}
-int Xil_In32(unsigned long addr)
+static int Xil_In32(unsigned long addr)
{
return readl(addr);
}
-void usleep(u32 sleep)
+static void __maybe_unused usleep(u32 sleep)
{
udelay(sleep);
}
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index c840e92..d649dab 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
+#include <env.h>
#include <sata.h>
#include <ahci.h>
#include <scsi.h>
@@ -22,6 +23,8 @@
#include <zynqmppl.h>
#include <g_dnl.h>
+#include "pm_cfg_obj.h"
+
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
@@ -327,6 +330,13 @@
int board_init(void)
{
+#if defined(CONFIG_SPL_BUILD)
+ /* Check *at build time* if the filename is an non-empty string */
+ if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
+ zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
+ zynqmp_pm_cfg_obj_size);
+#endif
+
printf("EL Level:\tEL%d\n", current_el());
#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 8de3be4..4e61565 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -101,7 +101,14 @@
config AUTOBOOT_ENCRYPTION
bool "Enable encryption in autoboot stopping"
depends on AUTOBOOT_KEYED
- default n
+ help
+ This option allows a string to be entered into U-Boot to stop the
+ autoboot. The string itself is hashed and compared against the hash
+ in the environment variable 'bootstopkeysha256'. If it matches then
+ boot stops and a command-line prompt is presented.
+
+ This provides a way to ship a secure production device which can also
+ be accessed at the U-Boot command line.
config AUTOBOOT_DELAY_STR
string "Delay autobooting via specific input key / string"
@@ -146,6 +153,32 @@
string / password matches a values that is encypted via
a SHA256 hash and saved in the environment.
+config AUTOBOOT_USE_MENUKEY
+ bool "Allow a specify key to run a menu from the environment"
+ depends on !AUTOBOOT_KEYED
+ help
+ If a specific key is pressed to stop autoboot, then the commands in
+ the environment variable 'menucmd' are executed before boot starts.
+
+config AUTOBOOT_MENUKEY
+ int "ASCII value of boot key to show a menu"
+ default 0
+ depends on AUTOBOOT_USE_MENUKEY
+ help
+ If this key is pressed to stop autoboot, then the commands in the
+ environment variable 'menucmd' will be executed before boot starts.
+ For example, 33 means "!" in ASCII, so pressing ! at boot would take
+ this action.
+
+config AUTOBOOT_MENU_SHOW
+ bool "Show a menu on boot"
+ depends on CMD_BOOTMENU
+ help
+ This enables the boot menu, controlled by environment variables
+ defined by the board. The menu starts after running the 'preboot'
+ environmnent variable (if enabled) and before handling the boot delay.
+ See README.bootmenu for more details.
+
endmenu
config BUILD_BIN2C
@@ -235,6 +268,54 @@
help
Boot an EFI image from memory.
+config BOOTM_LINUX
+ bool "Support booting Linux OS images"
+ depends on CMD_BOOTM || CMD_BOOTZ || CMD_BOOTI
+ default y
+ help
+ Support booting the Linux kernel directly via a command such as bootm
+ or booti or bootz.
+
+config BOOTM_NETBSD
+ bool "Support booting NetBSD (non-EFI) loader images"
+ depends on CMD_BOOTM
+ default y
+ help
+ Support booting NetBSD via the bootm command.
+
+config BOOTM_OPENRTOS
+ bool "Support booting OPENRTOS / FreeRTOS images"
+ depends on CMD_BOOTM
+ help
+ Support booting OPENRTOS / FreeRTOS via the bootm command.
+
+config BOOTM_OSE
+ bool "Support booting Enea OSE images"
+ depends on CMD_BOOTM
+ help
+ Support booting Enea OSE images via the bootm command.
+
+config BOOTM_PLAN9
+ bool "Support booting Plan9 OS images"
+ depends on CMD_BOOTM
+ default y
+ help
+ Support booting Plan9 images via the bootm command.
+
+config BOOTM_RTEMS
+ bool "Support booting RTEMS OS images"
+ depends on CMD_BOOTM
+ default y
+ help
+ Support booting RTEMS images via the bootm command.
+
+config BOOTM_VXWORKS
+ bool "Support booting VxWorks OS images"
+ depends on CMD_BOOTM
+ default y
+ help
+ Support booting VxWorks images via the bootm command.
+
config CMD_BOOTEFI_HELLO_COMPILE
bool "Compile a standard EFI hello world binary for testing"
depends on CMD_BOOTEFI && !CPU_V7M && !SANDBOX
@@ -325,8 +406,8 @@
command.
config CMD_SPL_NAND_OFS
- hex "Offset of OS command line args for Falcon-mode NAND boot"
- depends on CMD_SPL
+ hex "Offset of OS args or dtb for Falcon-mode NAND boot"
+ depends on CMD_SPL && (TPL_NAND_SUPPORT || SPL_NAND_SUPPORT)
default 0
help
This provides the offset of the command line arguments for Linux
@@ -334,6 +415,14 @@
for full information about how to use this option (and also see
board/gateworks/gw_ventana/README for an example).
+config CMD_SPL_NOR_OFS
+ hex "Offset of OS args or dtb for Falcon-mode NOR boot"
+ depends on CMD_SPL && SPL_NOR_SUPPORT
+ default 0
+ help
+ This provides the offset of the command line arguments or dtb for
+ Linux when booting from NOR in Falcon mode.
+
config CMD_SPL_WRITE_SIZE
hex "Size of argument area"
depends on CMD_SPL
@@ -408,6 +497,14 @@
Save all environment variables into the compiled-in persistent
storage.
+config CMD_ERASEENV
+ bool "eraseenv"
+ default n
+ depends on CMD_SAVEENV
+ help
+ Erase environment variables from the compiled-in persistent
+ storage.
+
config CMD_ENV_EXISTS
bool "env exists"
default y
@@ -441,6 +538,19 @@
If enabled, we are allowed to set/print UEFI variables using
"env" command with "-e" option without knowing details.
+config CMD_NVEDIT_INFO
+ bool "env info - print or evaluate environment information"
+ help
+ Print environment information:
+ - env_valid : is environment valid
+ - env_ready : is environment imported into hash table
+ - env_use_default : is default environment used
+
+ This command can be optionally used for evaluation in scripts:
+ [-d] : evaluate whether default environment is used
+ [-p] : evaluate whether environment can be persisted
+ The result of multiple evaluations will be combined with AND.
+
endmenu
menu "Memory commands"
@@ -550,6 +660,27 @@
base - print or set address offset
loop - initialize loop on address range
+config MX_CYCLIC
+ bool "Enable cyclic md/mw commands"
+ depends on CMD_MEMORY
+ help
+ Add the "mdc" and "mwc" memory commands. These are cyclic
+ "md/mw" commands.
+ Examples:
+
+ => mdc.b 10 4 500
+ This command will print 4 bytes (10,11,12,13) each 500 ms.
+
+ => mwc.l 100 12345678 10
+ This command will write 12345678 to address 100 all 10 ms.
+
+config CMD_RANDOM
+ bool "random"
+ default y
+ depends on CMD_MEMORY && (LIB_RAND || LIB_HW_RAND)
+ help
+ random - fill memory with random data
+
config CMD_MEMTEST
bool "memtest"
help
@@ -942,15 +1073,6 @@
help
NVM Express device support
-config CMD_MMC_SPI
- bool "mmc_spi - Set up MMC SPI device"
- help
- Provides a way to set up an MMC (Multimedia Card) SPI (Serial
- Peripheral Interface) device. The device provides a means of
- accessing an MMC device via SPI using a single data line, limited
- to 20MHz. It is useful since it reduces the amount of protocol code
- required.
-
config CMD_ONENAND
bool "onenand - access to onenand device"
help
@@ -983,14 +1105,6 @@
peripherals. Sub-commands allow bus enumeration, displaying and
changing configuration space and a few other features.
-config CMD_PCMCIA
- bool "pinit - Set up PCMCIA device"
- help
- Provides a means to initialise a PCMCIA (Personal Computer Memory
- Card International Association) device. This is an old standard from
- about 1990. These devices are typically removable memory or network
- cards using a standard 68-pin connector.
-
config CMD_PINMUX
bool "pinmux - show pins muxing"
default y if PINCTRL
@@ -1274,6 +1388,13 @@
bool "Request & store 'ntpserverip' from BOOTP/DHCP server"
depends on CMD_BOOTP
+config CMD_PCAP
+ bool "pcap capture"
+ help
+ Selecting this will allow capturing all Ethernet packets and store
+ them in physical memory in a PCAP formated file,
+ later to be analyzed by PCAP reader application (IE. WireShark).
+
config BOOTP_PXE
bool "Send PXE client arch to BOOTP/DHCP server"
default y
@@ -1396,7 +1517,7 @@
bool "Enable 'bmp' command"
depends on LCD || DM_VIDEO || VIDEO
help
- This provides a way to obtain information about a BMP-format iamge
+ This provides a way to obtain information about a BMP-format image
and to display it. BMP (which presumably stands for BitMaP) is a
file format defined by Microsoft which supports images of various
depths, formats and compression methods. Headers on the file
diff --git a/cmd/Makefile b/cmd/Makefile
index 500147a..ac843b4 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -94,7 +94,6 @@
endif
obj-$(CONFIG_CMD_MISC) += misc.o
obj-$(CONFIG_CMD_MMC) += mmc.o
-obj-$(CONFIG_CMD_MMC_SPI) += mmc_spi.o
obj-$(CONFIG_MP) += mp.o
obj-$(CONFIG_CMD_MTD) += mtd.o
obj-$(CONFIG_CMD_MTDPARTS) += mtdparts.o
@@ -104,10 +103,10 @@
obj-$(CONFIG_CMD_ONENAND) += onenand.o
obj-$(CONFIG_CMD_OSD) += osd.o
obj-$(CONFIG_CMD_PART) += part.o
+obj-$(CONFIG_CMD_PCAP) += pcap.o
ifdef CONFIG_PCI
obj-$(CONFIG_CMD_PCI) += pci.o
endif
-obj-$(CONFIG_CMD_PCMCIA) += pcmcia.o
obj-$(CONFIG_CMD_PINMUX) += pinmux.o
obj-$(CONFIG_CMD_PXE) += pxe.o
obj-$(CONFIG_CMD_WOL) += wol.o
diff --git a/cmd/aes.c b/cmd/aes.c
index 25efb96..7ff4a71 100644
--- a/cmd/aes.c
+++ b/cmd/aes.c
@@ -7,7 +7,6 @@
#include <common.h>
#include <command.h>
-#include <environment.h>
#include <uboot_aes.h>
#include <malloc.h>
#include <asm/byteorder.h>
diff --git a/cmd/avb.c b/cmd/avb.c
index c5af4a2..5bc1582 100644
--- a/cmd/avb.c
+++ b/cmd/avb.c
@@ -7,6 +7,7 @@
#include <avb_verify.h>
#include <command.h>
+#include <env.h>
#include <image.h>
#include <malloc.h>
#include <mmc.h>
@@ -368,7 +369,7 @@
if (avb_ops->read_persistent_value(avb_ops, name, bytes, buffer,
&bytes_read) == AVB_IO_RESULT_OK) {
- printf("Read %ld bytes, value = %s\n", bytes_read,
+ printf("Read %zu bytes, value = %s\n", bytes_read,
(char *)buffer);
free(buffer);
return CMD_RET_SUCCESS;
@@ -401,7 +402,7 @@
if (avb_ops->write_persistent_value(avb_ops, name, strlen(value) + 1,
(const uint8_t *)value) ==
AVB_IO_RESULT_OK) {
- printf("Wrote %ld bytes\n", strlen(value) + 1);
+ printf("Wrote %zu bytes\n", strlen(value) + 1);
return CMD_RET_SUCCESS;
}
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index f576e22..ae6006f 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -9,6 +9,7 @@
*/
#include <common.h>
#include <command.h>
+#include <env.h>
#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -328,7 +329,7 @@
print_num("reloc off", gd->reloc_off);
print_num("irq_sp", gd->irq_sp); /* irq stack pointer */
print_num("sp start ", gd->start_addr_sp);
-#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
+#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO) || defined(CONFIG_DM_VIDEO)
print_num("FB base ", gd->fb_base);
#endif
/*
diff --git a/cmd/binop.c b/cmd/binop.c
index 116a2c0..6d2df5f 100644
--- a/cmd/binop.c
+++ b/cmd/binop.c
@@ -2,6 +2,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <hexdump.h>
#include <malloc.h>
#include <mapmem.h>
diff --git a/cmd/blob.c b/cmd/blob.c
index d3b6e45..80478b8 100644
--- a/cmd/blob.c
+++ b/cmd/blob.c
@@ -6,7 +6,6 @@
#include <common.h>
#include <command.h>
-#include <environment.h>
#include <malloc.h>
#include <asm/byteorder.h>
#include <linux/compiler.h>
diff --git a/cmd/bmp.c b/cmd/bmp.c
index 00f0256..d2a39f6 100644
--- a/cmd/bmp.c
+++ b/cmd/bmp.c
@@ -9,16 +9,16 @@
*/
#include <common.h>
-#include <dm.h>
-#include <lcd.h>
-#include <mapmem.h>
#include <bmp_layout.h>
#include <command.h>
-#include <asm/byteorder.h>
+#include <dm.h>
+#include <gzip.h>
+#include <lcd.h>
#include <malloc.h>
#include <mapmem.h>
#include <splash.h>
#include <video.h>
+#include <asm/byteorder.h>
static int bmp_info (ulong addr);
diff --git a/cmd/bootefi.c b/cmd/bootefi.c
index c19256e..f613cce 100644
--- a/cmd/bootefi.c
+++ b/cmd/bootefi.c
@@ -11,6 +11,7 @@
#include <dm.h>
#include <efi_loader.h>
#include <efi_selftest.h>
+#include <env.h>
#include <errno.h>
#include <linux/libfdt.h>
#include <linux/libfdt_env.h>
@@ -24,7 +25,7 @@
static struct efi_device_path *bootefi_image_path;
static struct efi_device_path *bootefi_device_path;
-/*
+/**
* Set the load options of an image from an environment variable.
*
* @handle: the image handle
@@ -143,7 +144,7 @@
return ret;
}
-/*
+/**
* efi_carve_out_dt_rsv() - Carve out DT reserved memory ranges
*
* The mem_rsv entries of the FDT are added to the memory map. Any failures are
@@ -169,8 +170,8 @@
pages = efi_size_in_pages(size + (addr & EFI_PAGE_MASK));
addr &= ~EFI_PAGE_MASK;
- if (!efi_add_memory_map(addr, pages, EFI_RESERVED_MEMORY_TYPE,
- false))
+ if (efi_add_memory_map(addr, pages, EFI_RESERVED_MEMORY_TYPE,
+ false) != EFI_SUCCESS)
printf("FDT memrsv map %d: Failed to add to map\n", i);
}
}
@@ -342,7 +343,7 @@
return CMD_RET_SUCCESS;
}
-/*
+/**
* do_bootefi_image() - execute EFI binary
*
* Set up memory image for the binary to be loaded, prepare device path, and
@@ -612,6 +613,16 @@
bootefi_help_text
);
+/**
+ * efi_set_bootdev() - set boot device
+ *
+ * This function is called when a file is loaded, e.g. via the 'load' command.
+ * We use the path to this file to inform the UEFI binary about the boot device.
+ *
+ * @dev: device, e.g. "MMC"
+ * @devnr: number of the device, e.g. "1:2"
+ * @path: path to file loaded
+ */
void efi_set_bootdev(const char *dev, const char *devnr, const char *path)
{
struct efi_device_path *device, *image;
diff --git a/cmd/bootm.c b/cmd/bootm.c
index c3a0634..8279f2b 100644
--- a/cmd/bootm.c
+++ b/cmd/bootm.c
@@ -10,7 +10,7 @@
#include <common.h>
#include <bootm.h>
#include <command.h>
-#include <environment.h>
+#include <env.h>
#include <errno.h>
#include <image.h>
#include <malloc.h>
@@ -249,7 +249,7 @@
printf("\n## Checking Image at %08lx ...\n", addr);
switch (genimg_get_format(hdr)) {
-#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
+#if defined(CONFIG_LEGACY_IMAGE_FORMAT)
case IMAGE_FORMAT_LEGACY:
puts(" Legacy image found\n");
if (!image_check_magic(hdr)) {
@@ -337,7 +337,7 @@
goto next_sector;
switch (genimg_get_format(hdr)) {
-#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
+#if defined(CONFIG_LEGACY_IMAGE_FORMAT)
case IMAGE_FORMAT_LEGACY:
if (!image_check_hcrc(hdr))
goto next_sector;
@@ -485,7 +485,7 @@
}
switch (genimg_get_format(buffer)) {
-#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
+#if defined(CONFIG_LEGACY_IMAGE_FORMAT)
case IMAGE_FORMAT_LEGACY:
header = (const image_header_t *)buffer;
diff --git a/cmd/bootmenu.c b/cmd/bootmenu.c
index 7f88c1e..3dc2c85 100644
--- a/cmd/bootmenu.c
+++ b/cmd/bootmenu.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <command.h>
#include <ansi.h>
+#include <env.h>
#include <menu.h>
#include <watchdog.h>
#include <malloc.h>
@@ -472,7 +473,7 @@
puts(ANSI_CLEAR_LINE);
}
-#ifdef CONFIG_MENU_SHOW
+#ifdef CONFIG_AUTOBOOT_MENU_SHOW
int menu_show(int bootdelay)
{
bootmenu_show(bootdelay);
diff --git a/cmd/cache.c b/cmd/cache.c
index 233f428..2c68717 100644
--- a/cmd/cache.c
+++ b/cmd/cache.c
@@ -22,7 +22,7 @@
static int do_icache(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
switch (argc) {
- case 2: /* on / off */
+ case 2: /* on / off / flush */
switch (parse_argv(argv[1])) {
case 0:
icache_disable();
@@ -33,6 +33,8 @@
case 2:
invalidate_icache_all();
break;
+ default:
+ return CMD_RET_USAGE;
}
break;
case 1: /* get status */
@@ -54,7 +56,7 @@
static int do_dcache(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
switch (argc) {
- case 2: /* on / off */
+ case 2: /* on / off / flush */
switch (parse_argv(argv[1])) {
case 0:
dcache_disable();
@@ -65,6 +67,8 @@
case 2:
flush_dcache_all();
break;
+ default:
+ return CMD_RET_USAGE;
}
break;
case 1: /* get status */
diff --git a/cmd/cbfs.c b/cmd/cbfs.c
index c118a95..98e652a 100644
--- a/cmd/cbfs.c
+++ b/cmd/cbfs.c
@@ -8,6 +8,7 @@
*/
#include <common.h>
#include <command.h>
+#include <env.h>
#include <cbfs.h>
static int do_cbfs_init(cmd_tbl_t *cmdtp, int flag, int argc,
@@ -28,7 +29,7 @@
}
}
file_cbfs_init(end_of_rom);
- if (file_cbfs_result != CBFS_SUCCESS) {
+ if (cbfs_get_result() != CBFS_SUCCESS) {
printf("%s.\n", file_cbfs_error());
return 1;
}
@@ -66,7 +67,7 @@
file = file_cbfs_find(argv[2]);
if (!file) {
- if (file_cbfs_result == CBFS_FILE_NOT_FOUND)
+ if (cbfs_get_result() == CBFS_FILE_NOT_FOUND)
printf("%s: %s\n", file_cbfs_error(), argv[2]);
else
printf("%s.\n", file_cbfs_error());
diff --git a/cmd/clk.c b/cmd/clk.c
index 5402c87..74ad868 100644
--- a/cmd/clk.c
+++ b/cmd/clk.c
@@ -7,51 +7,70 @@
#include <clk.h>
#if defined(CONFIG_DM) && defined(CONFIG_CLK)
#include <dm.h>
+#include <dm/device.h>
+#include <dm/root.h>
#include <dm/device-internal.h>
+#include <linux/clk-provider.h>
#endif
+#if defined(CONFIG_DM) && defined(CONFIG_CLK)
+static void show_clks(struct udevice *dev, int depth, int last_flag)
+{
+ int i, is_last;
+ struct udevice *child;
+ struct clk *clkp;
+ u32 rate;
+
+ clkp = dev_get_clk_ptr(dev);
+ if (device_get_uclass_id(dev) == UCLASS_CLK && clkp) {
+ rate = clk_get_rate(clkp);
+
+ printf(" %-12u %8d ", rate, clkp->enable_count);
+
+ for (i = depth; i >= 0; i--) {
+ is_last = (last_flag >> i) & 1;
+ if (i) {
+ if (is_last)
+ printf(" ");
+ else
+ printf("| ");
+ } else {
+ if (is_last)
+ printf("`-- ");
+ else
+ printf("|-- ");
+ }
+ }
+
+ printf("%s\n", dev->name);
+ }
+
+ list_for_each_entry(child, &dev->child_head, sibling_node) {
+ is_last = list_is_last(&child->sibling_node, &dev->child_head);
+ show_clks(child, depth + 1, (last_flag << 1) | is_last);
+ }
+}
+
int __weak soc_clk_dump(void)
{
-#if defined(CONFIG_DM) && defined(CONFIG_CLK)
- struct udevice *dev;
- struct uclass *uc;
- struct clk clk;
- int ret;
- ulong rate;
+ struct udevice *root;
- /* Device addresses start at 1 */
- ret = uclass_get(UCLASS_CLK, &uc);
- if (ret)
- return ret;
-
- uclass_foreach_dev(dev, uc) {
- memset(&clk, 0, sizeof(clk));
- ret = device_probe(dev);
- if (ret)
- goto noclk;
-
- ret = clk_request(dev, &clk);
- if (ret)
- goto noclk;
-
- rate = clk_get_rate(&clk);
- clk_free(&clk);
-
- if (rate == -ENODEV)
- goto noclk;
-
- printf("%-30.30s : %lu Hz\n", dev->name, rate);
- continue;
- noclk:
- printf("%-30.30s : ? Hz\n", dev->name);
+ root = dm_root();
+ if (root) {
+ printf(" Rate Usecnt Name\n");
+ printf("------------------------------------------\n");
+ show_clks(root, -1, 0);
}
return 0;
+}
#else
+int __weak soc_clk_dump(void)
+{
puts("Not implemented\n");
return 1;
-#endif
}
+#endif
static int do_clk_dump(cmd_tbl_t *cmdtp, int flag, int argc,
char *const argv[])
diff --git a/cmd/config.c b/cmd/config.c
index fcc9116..d2810d5 100644
--- a/cmd/config.c
+++ b/cmd/config.c
@@ -5,6 +5,7 @@
#include <common.h>
#include <command.h>
+#include <gzip.h>
#include <malloc.h>
#include "config_data_gz.h"
diff --git a/cmd/cramfs.c b/cmd/cramfs.c
index 598028c..2188910 100644
--- a/cmd/cramfs.c
+++ b/cmd/cramfs.c
@@ -12,6 +12,7 @@
*/
#include <common.h>
#include <command.h>
+#include <env.h>
#include <malloc.h>
#include <mapmem.h>
#include <linux/list.h>
diff --git a/cmd/disk.c b/cmd/disk.c
index dcc36a6..9e635c1 100644
--- a/cmd/disk.c
+++ b/cmd/disk.c
@@ -15,7 +15,7 @@
ulong addr = CONFIG_SYS_LOAD_ADDR;
ulong cnt;
disk_partition_t info;
-#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
+#if defined(CONFIG_LEGACY_IMAGE_FORMAT)
image_header_t *hdr;
#endif
struct blk_desc *dev_desc;
@@ -62,7 +62,7 @@
bootstage_mark(BOOTSTAGE_ID_IDE_PART_READ);
switch (genimg_get_format((void *) addr)) {
-#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
+#if defined(CONFIG_LEGACY_IMAGE_FORMAT)
case IMAGE_FORMAT_LEGACY:
hdr = (image_header_t *) addr;
diff --git a/cmd/dtimg.c b/cmd/dtimg.c
index ae7d82f..6c5d53c 100644
--- a/cmd/dtimg.c
+++ b/cmd/dtimg.c
@@ -4,6 +4,7 @@
* Sam Protsenko <semen.protsenko@linaro.org>
*/
+#include <env.h>
#include <image-android-dt.h>
#include <common.h>
diff --git a/cmd/eeprom.c b/cmd/eeprom.c
index 7b1f814..19953df 100644
--- a/cmd/eeprom.c
+++ b/cmd/eeprom.c
@@ -108,7 +108,7 @@
/*
* For a FRAM device there is no limit on the number of the
- * bytes that can be ccessed with the single read or write
+ * bytes that can be accessed with the single read or write
* operation.
*/
#if !defined(CONFIG_SYS_I2C_FRAM)
diff --git a/cmd/efidebug.c b/cmd/efidebug.c
index cb152b3..ef97e19 100644
--- a/cmd/efidebug.c
+++ b/cmd/efidebug.c
@@ -9,7 +9,6 @@
#include <common.h>
#include <command.h>
#include <efi_loader.h>
-#include <environment.h>
#include <exports.h>
#include <hexdump.h>
#include <malloc.h>
@@ -394,6 +393,7 @@
/**
* print_memory_attributes() - print memory map attributes
+ *
* @attributes: Attribute value
*
* Print memory map attributes
@@ -487,9 +487,9 @@
* Return: CMD_RET_SUCCESS on success,
* CMD_RET_USAGE or CMD_RET_RET_FAILURE on failure
*
- * Implement efidebug "boot add" sub-command.
- * Create or change UEFI load option.
- * - boot add <id> <label> <interface> <devnum>[:<part>] <file> <options>
+ * Implement efidebug "boot add" sub-command. Create or change UEFI load option.
+ *
+ * efidebug boot add <id> <label> <interface> <devnum>[:<part>] <file> <options>
*/
static int do_efi_boot_add(cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
@@ -587,7 +587,8 @@
*
* Implement efidebug "boot rm" sub-command.
* Delete UEFI load options.
- * - boot rm <id> ...
+ *
+ * efidebug boot rm <id> ...
*/
static int do_efi_boot_rm(cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
@@ -727,7 +728,8 @@
*
* Implement efidebug "boot dump" sub-command.
* Dump information of all UEFI load options defined.
- * - boot dump
+ *
+ * efidebug boot dump
*/
static int do_efi_boot_dump(cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
@@ -890,7 +892,8 @@
*
* Implement efidebug "boot next" sub-command.
* Set BootNext variable.
- * - boot next <id>
+ *
+ * efidebug boot next <id>
*/
static int do_efi_boot_next(cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
@@ -938,7 +941,8 @@
*
* Implement efidebug "boot order" sub-command.
* Show order of UEFI load options, or change it in BootOrder variable.
- * - boot order [<id> ...]
+ *
+ * efidebug boot order [<id> ...]
*/
static int do_efi_boot_order(cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
@@ -1009,7 +1013,6 @@
* CMD_RET_USAGE or CMD_RET_RET_FAILURE on failure
*
* Implement efidebug "boot" sub-command.
- * See above for details of sub-commands.
*/
static int do_efi_boot_opt(cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
@@ -1055,7 +1058,6 @@
*
* Implement efidebug command which allows us to display and
* configure UEFI environment.
- * See above for details of sub-commands.
*/
static int do_efidebug(cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
diff --git a/cmd/elf.c b/cmd/elf.c
index d883be4..538562f 100644
--- a/cmd/elf.c
+++ b/cmd/elf.c
@@ -16,7 +16,7 @@
#include <common.h>
#include <command.h>
#include <elf.h>
-#include <environment.h>
+#include <env.h>
#include <net.h>
#include <vxworks.h>
#ifdef CONFIG_X86
diff --git a/cmd/ethsw.c b/cmd/ethsw.c
index 473324f..8846805 100644
--- a/cmd/ethsw.c
+++ b/cmd/ethsw.c
@@ -7,7 +7,7 @@
#include <common.h>
#include <command.h>
-#include <environment.h>
+#include <env.h>
#include <errno.h>
#include <env_flags.h>
#include <ethsw.h>
diff --git a/cmd/fdc.c b/cmd/fdc.c
index 906845d..7bfaae0 100644
--- a/cmd/fdc.c
+++ b/cmd/fdc.c
@@ -634,7 +634,7 @@
FD_GEO_STRUCT *pFG = (FD_GEO_STRUCT *)floppy_type;
FDC_COMMAND_STRUCT *pCMD = &cmd;
unsigned long addr,imsize;
-#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
+#if defined(CONFIG_LEGACY_IMAGE_FORMAT)
image_header_t *hdr; /* used for fdc boot */
#endif
unsigned char boot_drive;
@@ -690,7 +690,7 @@
}
switch (genimg_get_format ((void *)addr)) {
-#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
+#if defined(CONFIG_LEGACY_IMAGE_FORMAT)
case IMAGE_FORMAT_LEGACY:
hdr = (image_header_t *)addr;
image_print_contents (hdr);
diff --git a/cmd/fdt.c b/cmd/fdt.c
index 10d8f32..25a6ed4 100644
--- a/cmd/fdt.c
+++ b/cmd/fdt.c
@@ -9,6 +9,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <linux/ctype.h>
#include <linux/types.h>
#include <asm/global_data.h>
diff --git a/cmd/fpga.c b/cmd/fpga.c
index b1f224b..b1c7b54 100644
--- a/cmd/fpga.c
+++ b/cmd/fpga.c
@@ -9,8 +9,10 @@
*/
#include <common.h>
#include <command.h>
+#include <env.h>
#include <fpga.h>
#include <fs.h>
+#include <gzip.h>
#include <malloc.h>
static long do_fpga_get_device(char *arg)
@@ -280,7 +282,7 @@
}
switch (genimg_get_format(fpga_data)) {
-#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
+#if defined(CONFIG_LEGACY_IMAGE_FORMAT)
case IMAGE_FORMAT_LEGACY:
{
image_header_t *hdr = (image_header_t *)fpga_data;
@@ -458,7 +460,7 @@
"0-device key, 1-user key, 2-no encryption.\n"
"The optional Userkey address specifies from which address key\n"
"has to be used for decryption if user key is selected.\n"
- "NOTE: the sceure bitstream has to be created using xilinx\n"
+ "NOTE: the secure bitstream has to be created using Xilinx\n"
"bootgen tool only.\n"
#endif
);
diff --git a/cmd/gpio.c b/cmd/gpio.c
index 53366f3..eff36ab 100644
--- a/cmd/gpio.c
+++ b/cmd/gpio.c
@@ -91,7 +91,7 @@
if (!gpio_name || !bank_name ||
!strncasecmp(gpio_name, bank_name, banklen)) {
- const char *p = NULL;
+ const char *p;
int offset;
p = gpio_name + banklen;
diff --git a/cmd/gpt.c b/cmd/gpt.c
index 33cda51..0c4349f 100644
--- a/cmd/gpt.c
+++ b/cmd/gpt.c
@@ -11,6 +11,7 @@
*/
#include <common.h>
+#include <env.h>
#include <malloc.h>
#include <command.h>
#include <part_efi.h>
diff --git a/cmd/help.c b/cmd/help.c
index fa2010c..a1a0b99 100644
--- a/cmd/help.c
+++ b/cmd/help.c
@@ -27,6 +27,7 @@
" - print detailed usage of 'command'"
);
+#ifdef CONFIG_CMDLINE
/* This does not use the U_BOOT_CMD macro as ? can't be used in symbol names */
ll_entry_declare(cmd_tbl_t, question_mark, cmd) = {
"?", CONFIG_SYS_MAXARGS, cmd_always_repeatable, do_help,
@@ -35,3 +36,4 @@
""
#endif /* CONFIG_SYS_LONGHELP */
};
+#endif
diff --git a/cmd/host.c b/cmd/host.c
index f7d3eae..98c4d2a 100644
--- a/cmd/host.c
+++ b/cmd/host.c
@@ -89,7 +89,7 @@
struct host_block_dev *host_dev;
#ifdef CONFIG_BLK
- host_dev = dev_get_priv(blk_dev->bdev);
+ host_dev = dev_get_platdata(blk_dev->bdev);
#else
host_dev = blk_dev->priv;
#endif
diff --git a/cmd/i2c.c b/cmd/i2c.c
index 09c4ba9..e0f8ece 100644
--- a/cmd/i2c.c
+++ b/cmd/i2c.c
@@ -71,7 +71,6 @@
#include <console.h>
#include <dm.h>
#include <edid.h>
-#include <environment.h>
#include <errno.h>
#include <i2c.h>
#include <malloc.h>
diff --git a/cmd/ide.c b/cmd/ide.c
index 1c58efc..2f93ba7 100644
--- a/cmd/ide.c
+++ b/cmd/ide.c
@@ -17,10 +17,6 @@
#include <asm/byteorder.h>
#include <asm/io.h>
-#if defined(CONFIG_IDE_PCMCIA)
-# include <pcmcia.h>
-#endif
-
#include <ide.h>
#include <ata.h>
diff --git a/cmd/ini.c b/cmd/ini.c
index 8c28fa6..0c42526 100644
--- a/cmd/ini.c
+++ b/cmd/ini.c
@@ -13,7 +13,7 @@
#include <common.h>
#include <command.h>
-#include <environment.h>
+#include <env.h>
#include <linux/ctype.h>
#include <linux/string.h>
diff --git a/cmd/itest.c b/cmd/itest.c
index fd6f416..8b630d7 100644
--- a/cmd/itest.c
+++ b/cmd/itest.c
@@ -14,6 +14,7 @@
#include <common.h>
#include <config.h>
#include <command.h>
+#include <env.h>
#include <mapmem.h>
#include <asm/io.h>
diff --git a/cmd/jffs2.c b/cmd/jffs2.c
index 64621f2..b47cd3d 100644
--- a/cmd/jffs2.c
+++ b/cmd/jffs2.c
@@ -72,6 +72,7 @@
*/
#include <common.h>
#include <command.h>
+#include <env.h>
#include <malloc.h>
#include <jffs2/jffs2.h>
#include <linux/list.h>
diff --git a/cmd/license.c b/cmd/license.c
index 1c0794f..c5b04c3 100644
--- a/cmd/license.c
+++ b/cmd/license.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <command.h>
+#include <gzip.h>
#include <malloc.h>
#include "license_data_gz.h"
diff --git a/cmd/load.c b/cmd/load.c
index dd1e8da..713fe56 100644
--- a/cmd/load.c
+++ b/cmd/load.c
@@ -10,6 +10,7 @@
#include <common.h>
#include <command.h>
#include <console.h>
+#include <env.h>
#include <s_record.h>
#include <net.h>
#include <exports.h>
diff --git a/cmd/lzmadec.c b/cmd/lzmadec.c
index 6860b5f..e3b9cc7 100644
--- a/cmd/lzmadec.c
+++ b/cmd/lzmadec.c
@@ -11,6 +11,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <mapmem.h>
#include <asm/io.h>
diff --git a/cmd/md5sum.c b/cmd/md5sum.c
index 9d2d418..63cbae0 100644
--- a/cmd/md5sum.c
+++ b/cmd/md5sum.c
@@ -9,6 +9,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <mapmem.h>
#include <u-boot/md5.h>
#include <asm/io.h>
diff --git a/cmd/mdio.c b/cmd/mdio.c
index 5e219f6..22c8fbe 100644
--- a/cmd/mdio.c
+++ b/cmd/mdio.c
@@ -203,6 +203,11 @@
if (argc < 2)
return CMD_RET_USAGE;
+#ifdef CONFIG_DM_MDIO
+ /* probe DM MII device before any operation so they are all accesible */
+ dm_mdio_probe_devices();
+#endif
+
/*
* We use the last specified parameters, unless new ones are
* entered.
@@ -248,12 +253,13 @@
case 'w':
if (pos > 1)
data = simple_strtoul(argv[pos--], NULL, 16);
+ /* Intentional fall-through - Get reg for read and write */
case 'r':
if (pos > 1)
if (extract_reg_range(argv[pos--], &devadlo, &devadhi,
®lo, ®hi))
return CMD_RET_FAILURE;
-
+ /* Intentional fall-through - Get phy for all commands */
default:
if (pos > 1)
if (extract_phy_range(&argv[2], pos - 1, &bus,
@@ -263,6 +269,11 @@
break;
}
+ if (!bus) {
+ puts("No MDIO bus found\n");
+ return CMD_RET_FAILURE;
+ }
+
if (op[0] == 'l') {
mdio_list_devices();
diff --git a/cmd/mem.c b/cmd/mem.c
index 392ed17..c6b8038 100644
--- a/cmd/mem.c
+++ b/cmd/mem.c
@@ -1082,6 +1082,49 @@
#endif
+#ifdef CONFIG_CMD_RANDOM
+static int do_random(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned long addr, len;
+ unsigned long seed; // NOT INITIALIZED ON PURPOSE
+ unsigned int *buf, *start;
+ unsigned char *buf8;
+ unsigned int i;
+
+ if (argc < 3 || argc > 4) {
+ printf("usage: %s <addr> <len> [<seed>]\n", argv[0]);
+ return 0;
+ }
+
+ len = simple_strtoul(argv[2], NULL, 16);
+ addr = simple_strtoul(argv[1], NULL, 16);
+
+ if (argc == 4) {
+ seed = simple_strtoul(argv[3], NULL, 16);
+ if (seed == 0) {
+ printf("The seed cannot be 0. Using 0xDEADBEEF.\n");
+ seed = 0xDEADBEEF;
+ }
+ } else {
+ seed = get_timer(0) ^ rand();
+ }
+
+ srand(seed);
+ start = map_sysmem(addr, len);
+ buf = start;
+ for (i = 0; i < (len / 4); i++)
+ *buf++ = rand();
+
+ buf8 = (unsigned char *)buf;
+ for (i = 0; i < (len % 4); i++)
+ *buf8++ = rand() & 0xFF;
+
+ unmap_sysmem(start);
+ printf("%lu bytes filled with random data\n", len);
+ return 1;
+}
+#endif
+
/**************************************************/
U_BOOT_CMD(
md, 3, 1, do_mem_md,
@@ -1250,3 +1293,12 @@
""
);
#endif
+
+#ifdef CONFIG_CMD_RANDOM
+U_BOOT_CMD(
+ random, 4, 0, do_random,
+ "fill memory with random pattern",
+ "<addr> <len> [<seed>]\n"
+ " - Fill 'len' bytes of memory starting at 'addr' with random data\n"
+);
+#endif
diff --git a/cmd/mii.c b/cmd/mii.c
index c0c42a8..23ee1e6 100644
--- a/cmd/mii.c
+++ b/cmd/mii.c
@@ -12,25 +12,11 @@
#include <command.h>
#include <miiphy.h>
-typedef struct _MII_reg_desc_t {
- ushort regno;
- char * name;
-} MII_reg_desc_t;
-
-static const MII_reg_desc_t reg_0_5_desc_tbl[] = {
- { MII_BMCR, "PHY control register" },
- { MII_BMSR, "PHY status register" },
- { MII_PHYSID1, "PHY ID 1 register" },
- { MII_PHYSID2, "PHY ID 2 register" },
- { MII_ADVERTISE, "Autonegotiation advertisement register" },
- { MII_LPA, "Autonegotiation partner abilities register" },
-};
-
typedef struct _MII_field_desc_t {
ushort hi;
ushort lo;
ushort mask;
- char * name;
+ const char *name;
} MII_field_desc_t;
static const MII_field_desc_t reg_0_desc_tbl[] = {
@@ -87,7 +73,7 @@
{ 7, 7, 0x01, "100BASE-TX able" },
{ 6, 6, 0x01, "10BASE-T full duplex able" },
{ 5, 5, 0x01, "10BASE-T able" },
- { 4, 0, 0x1f, "xxx to do" },
+ { 4, 0, 0x1f, "selector" },
};
static const MII_field_desc_t reg_5_desc_tbl[] = {
@@ -102,50 +88,91 @@
{ 7, 7, 0x01, "100BASE-TX able" },
{ 6, 6, 0x01, "10BASE-T full duplex able" },
{ 5, 5, 0x01, "10BASE-T able" },
- { 4, 0, 0x1f, "xxx to do" },
+ { 4, 0, 0x1f, "partner selector" },
};
-typedef struct _MII_field_desc_and_len_t {
+
+static const MII_field_desc_t reg_9_desc_tbl[] = {
+ { 15, 13, 0x07, "test mode" },
+ { 12, 12, 0x01, "manual master/slave enable" },
+ { 11, 11, 0x01, "manual master/slave value" },
+ { 10, 10, 0x01, "multi/single port" },
+ { 9, 9, 0x01, "1000BASE-T full duplex able" },
+ { 8, 8, 0x01, "1000BASE-T half duplex able" },
+ { 7, 7, 0x01, "automatic TDR on link down" },
+ { 6, 6, 0x7f, "(reserved)" },
+};
+
+static const MII_field_desc_t reg_10_desc_tbl[] = {
+ { 15, 15, 0x01, "master/slave config fault" },
+ { 14, 14, 0x01, "master/slave config result" },
+ { 13, 13, 0x01, "local receiver status OK" },
+ { 12, 12, 0x01, "remote receiver status OK" },
+ { 11, 11, 0x01, "1000BASE-T full duplex able" },
+ { 10, 10, 0x01, "1000BASE-T half duplex able" },
+ { 9, 8, 0x03, "(reserved)" },
+ { 7, 0, 0xff, "1000BASE-T idle error counter"},
+};
+
+typedef struct _MII_reg_desc_t {
+ ushort regno;
const MII_field_desc_t *pdesc;
ushort len;
-} MII_field_desc_and_len_t;
+ const char *name;
+} MII_reg_desc_t;
-static const MII_field_desc_and_len_t desc_and_len_tbl[] = {
- { reg_0_desc_tbl, ARRAY_SIZE(reg_0_desc_tbl) },
- { reg_1_desc_tbl, ARRAY_SIZE(reg_1_desc_tbl) },
- { reg_2_desc_tbl, ARRAY_SIZE(reg_2_desc_tbl) },
- { reg_3_desc_tbl, ARRAY_SIZE(reg_3_desc_tbl) },
- { reg_4_desc_tbl, ARRAY_SIZE(reg_4_desc_tbl) },
- { reg_5_desc_tbl, ARRAY_SIZE(reg_5_desc_tbl) },
+static const MII_reg_desc_t mii_reg_desc_tbl[] = {
+ { MII_BMCR, reg_0_desc_tbl, ARRAY_SIZE(reg_0_desc_tbl),
+ "PHY control register" },
+ { MII_BMSR, reg_1_desc_tbl, ARRAY_SIZE(reg_1_desc_tbl),
+ "PHY status register" },
+ { MII_PHYSID1, reg_2_desc_tbl, ARRAY_SIZE(reg_2_desc_tbl),
+ "PHY ID 1 register" },
+ { MII_PHYSID2, reg_3_desc_tbl, ARRAY_SIZE(reg_3_desc_tbl),
+ "PHY ID 2 register" },
+ { MII_ADVERTISE, reg_4_desc_tbl, ARRAY_SIZE(reg_4_desc_tbl),
+ "Autonegotiation advertisement register" },
+ { MII_LPA, reg_5_desc_tbl, ARRAY_SIZE(reg_5_desc_tbl),
+ "Autonegotiation partner abilities register" },
+ { MII_CTRL1000, reg_9_desc_tbl, ARRAY_SIZE(reg_9_desc_tbl),
+ "1000BASE-T control register" },
+ { MII_STAT1000, reg_10_desc_tbl, ARRAY_SIZE(reg_10_desc_tbl),
+ "1000BASE-T status register" },
};
static void dump_reg(
ushort regval,
- const MII_reg_desc_t *prd,
- const MII_field_desc_and_len_t *pdl);
+ const MII_reg_desc_t *prd);
-static int special_field(
- ushort regno,
- const MII_field_desc_t *pdesc,
- ushort regval);
+static bool special_field(ushort regno, const MII_field_desc_t *pdesc,
+ ushort regval);
-static void MII_dump_0_to_5(
- ushort regvals[6],
- uchar reglo,
- uchar reghi)
+static void MII_dump(const ushort *regvals, uchar reglo, uchar reghi)
{
ulong i;
- for (i = 0; i < 6; i++) {
- if ((reglo <= i) && (i <= reghi))
- dump_reg(regvals[i], ®_0_5_desc_tbl[i],
- &desc_and_len_tbl[i]);
+ for (i = 0; i < ARRAY_SIZE(mii_reg_desc_tbl); i++) {
+ const uchar reg = mii_reg_desc_tbl[i].regno;
+
+ if (reg >= reglo && reg <= reghi)
+ dump_reg(regvals[reg - reglo], &mii_reg_desc_tbl[i]);
}
}
+/* Print out field position, value, name */
+static void dump_field(const MII_field_desc_t *pdesc, ushort regval)
+{
+ if (pdesc->hi == pdesc->lo)
+ printf("%2u ", pdesc->lo);
+ else
+ printf("%2u-%2u", pdesc->hi, pdesc->lo);
+
+ printf(" = %5u %s", (regval >> pdesc->lo) & pdesc->mask,
+ pdesc->name);
+}
+
static void dump_reg(
ushort regval,
- const MII_reg_desc_t *prd,
- const MII_field_desc_and_len_t *pdl)
+ const MII_reg_desc_t *prd)
{
ulong i;
ushort mask_in_place;
@@ -154,8 +181,8 @@
printf("%u. (%04hx) -- %s --\n",
prd->regno, regval, prd->name);
- for (i = 0; i < pdl->len; i++) {
- pdesc = &pdl->pdesc[i];
+ for (i = 0; i < prd->len; i++) {
+ pdesc = &prd->pdesc[i];
mask_in_place = pdesc->mask << pdesc->lo;
@@ -164,17 +191,8 @@
regval & mask_in_place,
prd->regno);
- if (special_field(prd->regno, pdesc, regval)) {
- }
- else {
- if (pdesc->hi == pdesc->lo)
- printf("%2u ", pdesc->lo);
- else
- printf("%2u-%2u", pdesc->hi, pdesc->lo);
- printf(" = %5u %s",
- (regval & mask_in_place) >> pdesc->lo,
- pdesc->name);
- }
+ if (!special_field(prd->regno, pdesc, regval))
+ dump_field(pdesc, regval);
printf("\n");
}
@@ -190,11 +208,11 @@
** 5.4-0
*/
-static int special_field(
- ushort regno,
- const MII_field_desc_t *pdesc,
- ushort regval)
+static bool special_field(ushort regno, const MII_field_desc_t *pdesc,
+ ushort regval)
{
+ const ushort sel_bits = (regval >> pdesc->lo) & pdesc->mask;
+
if ((regno == MII_BMCR) && (pdesc->lo == 6)) {
ushort speed_bits = regval & (BMCR_SPEED1000 | BMCR_SPEED100);
printf("%2u,%2u = b%u%u speed selection = %s Mbps",
@@ -208,34 +226,26 @@
}
else if ((regno == MII_BMCR) && (pdesc->lo == 8)) {
- printf("%2u = %5u duplex = %s",
- pdesc->lo,
- (regval >> pdesc->lo) & 1,
- ((regval >> pdesc->lo) & 1) ? "full" : "half");
+ dump_field(pdesc, regval);
+ printf(" = %s", ((regval >> pdesc->lo) & 1) ? "full" : "half");
return 1;
}
else if ((regno == MII_ADVERTISE) && (pdesc->lo == 0)) {
- ushort sel_bits = (regval >> pdesc->lo) & pdesc->mask;
- printf("%2u-%2u = %5u selector = %s",
- pdesc->hi, pdesc->lo, sel_bits,
- sel_bits == PHY_ANLPAR_PSB_802_3 ?
- "IEEE 802.3" :
- sel_bits == PHY_ANLPAR_PSB_802_9 ?
- "IEEE 802.9 ISLAN-16T" :
- "???");
+ dump_field(pdesc, regval);
+ printf(" = %s",
+ sel_bits == PHY_ANLPAR_PSB_802_3 ? "IEEE 802.3 CSMA/CD" :
+ sel_bits == PHY_ANLPAR_PSB_802_9 ?
+ "IEEE 802.9 ISLAN-16T" : "???");
return 1;
}
else if ((regno == MII_LPA) && (pdesc->lo == 0)) {
- ushort sel_bits = (regval >> pdesc->lo) & pdesc->mask;
- printf("%2u-%2u = %u selector = %s",
- pdesc->hi, pdesc->lo, sel_bits,
- sel_bits == PHY_ANLPAR_PSB_802_3 ?
- "IEEE 802.3" :
- sel_bits == PHY_ANLPAR_PSB_802_9 ?
- "IEEE 802.9 ISLAN-16T" :
- "???");
+ dump_field(pdesc, regval);
+ printf(" = %s",
+ sel_bits == PHY_ANLPAR_PSB_802_3 ? "IEEE 802.3 CSMA/CD" :
+ sel_bits == PHY_ANLPAR_PSB_802_9 ?
+ "IEEE 802.9 ISLAN-16T" : "???");
return 1;
}
@@ -406,17 +416,16 @@
}
}
} else if (strncmp(op, "du", 2) == 0) {
- ushort regs[6];
+ ushort regs[MII_STAT1000 + 1]; /* Last reg is 0x0a */
int ok = 1;
- if ((reglo > 5) || (reghi > 5)) {
- printf(
- "The MII dump command only formats the "
- "standard MII registers, 0-5.\n");
+ if (reglo > MII_STAT1000 || reghi > MII_STAT1000) {
+ printf("The MII dump command only formats the standard MII registers, 0-5, 9-a.\n");
return 1;
}
for (addr = addrlo; addr <= addrhi; addr++) {
- for (reg = reglo; reg < reghi + 1; reg++) {
- if (miiphy_read(devname, addr, reg, ®s[reg]) != 0) {
+ for (reg = reglo; reg <= reghi; reg++) {
+ if (miiphy_read(devname, addr, reg,
+ ®s[reg - reglo]) != 0) {
ok = 0;
printf(
"Error reading from the PHY addr=%02x reg=%02x\n",
@@ -425,7 +434,7 @@
}
}
if (ok)
- MII_dump_0_to_5(regs, reglo, reghi);
+ MII_dump(regs, reglo, reghi);
printf("\n");
}
} else if (strncmp(op, "de", 2) == 0) {
diff --git a/cmd/mmc_spi.c b/cmd/mmc_spi.c
deleted file mode 100644
index 0c44d06..0000000
--- a/cmd/mmc_spi.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * Command for mmc_spi setup.
- *
- * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <mmc.h>
-#include <spi.h>
-
-#ifndef CONFIG_MMC_SPI_BUS
-# define CONFIG_MMC_SPI_BUS 0
-#endif
-#ifndef CONFIG_MMC_SPI_CS
-# define CONFIG_MMC_SPI_CS 1
-#endif
-/* in SPI mode, MMC speed limit is 20MHz, while SD speed limit is 25MHz */
-#ifndef CONFIG_MMC_SPI_SPEED
-# define CONFIG_MMC_SPI_SPEED 25000000
-#endif
-/* MMC and SD specs only seem to care that sampling is on the
- * rising edge ... meaning SPI modes 0 or 3. So either SPI mode
- * should be legit. We'll use mode 0 since the steady state is 0,
- * which is appropriate for hotplugging, unless the platform data
- * specify mode 3 (if hardware is not compatible to mode 0).
- */
-#ifndef CONFIG_MMC_SPI_MODE
-# define CONFIG_MMC_SPI_MODE SPI_MODE_0
-#endif
-
-static int do_mmc_spi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- uint bus = CONFIG_MMC_SPI_BUS;
- uint cs = CONFIG_MMC_SPI_CS;
- uint speed = CONFIG_MMC_SPI_SPEED;
- uint mode = CONFIG_MMC_SPI_MODE;
- char *endp;
- struct mmc *mmc;
-
- if (argc < 2)
- goto usage;
-
- cs = simple_strtoul(argv[1], &endp, 0);
- if (*argv[1] == 0 || (*endp != 0 && *endp != ':'))
- goto usage;
- if (*endp == ':') {
- if (endp[1] == 0)
- goto usage;
- bus = cs;
- cs = simple_strtoul(endp + 1, &endp, 0);
- if (*endp != 0)
- goto usage;
- }
- if (argc >= 3) {
- speed = simple_strtoul(argv[2], &endp, 0);
- if (*argv[2] == 0 || *endp != 0)
- goto usage;
- }
- if (argc >= 4) {
- mode = simple_strtoul(argv[3], &endp, 16);
- if (*argv[3] == 0 || *endp != 0)
- goto usage;
- }
- if (!spi_cs_is_valid(bus, cs)) {
- printf("Invalid SPI bus %u cs %u\n", bus, cs);
- return 1;
- }
-
- mmc = mmc_spi_init(bus, cs, speed, mode);
- if (!mmc) {
- printf("Failed to create MMC Device\n");
- return 1;
- }
- printf("%s: %d at %u:%u hz %u mode %u\n", mmc->cfg->name,
- mmc->block_dev.devnum, bus, cs, speed, mode);
- mmc_init(mmc);
- return 0;
-
-usage:
- return CMD_RET_USAGE;
-}
-
-U_BOOT_CMD(
- mmc_spi, 4, 0, do_mmc_spi,
- "mmc_spi setup",
- "[bus:]cs [hz] [mode] - setup mmc_spi device"
-);
diff --git a/cmd/mtdparts.c b/cmd/mtdparts.c
index f7ed1a0..46155ca 100644
--- a/cmd/mtdparts.c
+++ b/cmd/mtdparts.c
@@ -72,6 +72,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <malloc.h>
#include <jffs2/load_kernel.h>
#include <linux/list.h>
diff --git a/cmd/mvebu/bubt.c b/cmd/mvebu/bubt.c
index b4d371f..84d2d53 100644
--- a/cmd/mvebu/bubt.c
+++ b/cmd/mvebu/bubt.c
@@ -7,6 +7,7 @@
#include <config.h>
#include <common.h>
#include <command.h>
+#include <env.h>
#include <vsprintf.h>
#include <errno.h>
#include <dm.h>
diff --git a/cmd/nand.c b/cmd/nand.c
index a22945d..27efef2 100644
--- a/cmd/nand.c
+++ b/cmd/nand.c
@@ -23,6 +23,7 @@
#include <linux/mtd/mtd.h>
#include <command.h>
#include <console.h>
+#include <env.h>
#include <watchdog.h>
#include <malloc.h>
#include <asm/byteorder.h>
@@ -846,7 +847,7 @@
int r;
char *s;
size_t cnt;
-#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
+#if defined(CONFIG_LEGACY_IMAGE_FORMAT)
image_header_t *hdr;
#endif
#if defined(CONFIG_FIT)
@@ -874,7 +875,7 @@
bootstage_mark(BOOTSTAGE_ID_NAND_HDR_READ);
switch (genimg_get_format ((void *)addr)) {
-#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
+#if defined(CONFIG_LEGACY_IMAGE_FORMAT)
case IMAGE_FORMAT_LEGACY:
hdr = (image_header_t *)addr;
diff --git a/cmd/net.c b/cmd/net.c
index 89721b8..2374039 100644
--- a/cmd/net.c
+++ b/cmd/net.c
@@ -9,6 +9,7 @@
*/
#include <common.h>
#include <command.h>
+#include <env.h>
#include <net.h>
static int netboot_common(enum proto_t, cmd_tbl_t *, int, char * const []);
diff --git a/cmd/nvedit.c b/cmd/nvedit.c
index 1b20d47..c1ae9ad 100644
--- a/cmd/nvedit.c
+++ b/cmd/nvedit.c
@@ -27,7 +27,8 @@
#include <cli.h>
#include <command.h>
#include <console.h>
-#include <environment.h>
+#include <env.h>
+#include <env_internal.h>
#include <search.h>
#include <errno.h>
#include <malloc.h>
@@ -70,14 +71,14 @@
/*
* This variable is incremented on each do_env_set(), so it can
- * be used via get_env_id() as an indication, if the environment
+ * be used via env_get_id() as an indication, if the environment
* has changed or not. So it is possible to reread an environment
* variable only if the environment was changed ... done so for
* example in NetInitLoop()
*/
static int env_id = 1;
-int get_env_id(void)
+int env_get_id(void)
{
return env_id;
}
@@ -94,11 +95,11 @@
ssize_t len;
if (name) { /* print a single name */
- ENTRY e, *ep;
+ struct env_entry e, *ep;
e.key = name;
e.data = NULL;
- hsearch_r(e, FIND, &ep, &env_htab, flag);
+ hsearch_r(e, ENV_FIND, &ep, &env_htab, flag);
if (ep == NULL)
return 0;
len = printf("%s=%s\n", ep->key, ep->data);
@@ -225,7 +226,7 @@
{
int i, len;
char *name, *value, *s;
- ENTRY e, *ep;
+ struct env_entry e, *ep;
debug("Initial value for argc=%d\n", argc);
@@ -288,7 +289,7 @@
e.key = name;
e.data = value;
- hsearch_r(e, ENTER, &ep, &env_htab, env_flag);
+ hsearch_r(e, ENV_ENTER, &ep, &env_htab, env_flag);
free(value);
if (!ep) {
printf("## Error inserting \"%s\" variable, errno=%d\n",
@@ -358,18 +359,6 @@
return value;
}
-void eth_parse_enetaddr(const char *addr, uint8_t *enetaddr)
-{
- char *end;
- int i;
-
- for (i = 0; i < 6; ++i) {
- enetaddr[i] = addr ? simple_strtoul(addr, &end, 16) : 0;
- if (addr)
- addr = (*end) ? end + 1 : end;
- }
-}
-
int eth_env_get_enetaddr(const char *name, uint8_t *enetaddr)
{
eth_parse_enetaddr(env_get(name), enetaddr);
@@ -485,7 +474,7 @@
return 0;
}
-static int print_active_callback(ENTRY *entry)
+static int print_active_callback(struct env_entry *entry)
{
struct env_clbk_tbl *clbkp;
int i;
@@ -566,7 +555,7 @@
return 0;
}
-static int print_active_flags(ENTRY *entry)
+static int print_active_flags(struct env_entry *entry)
{
enum env_flags_vartype type;
enum env_flags_varaccess access;
@@ -674,13 +663,13 @@
char *env_get(const char *name)
{
if (gd->flags & GD_FLG_ENV_READY) { /* after import into hashtable */
- ENTRY e, *ep;
+ struct env_entry e, *ep;
WATCHDOG_RESET();
e.key = name;
e.data = NULL;
- hsearch_r(e, FIND, &ep, &env_htab, 0);
+ hsearch_r(e, ENV_FIND, &ep, &env_htab, 0);
return ep ? ep->data : NULL;
}
@@ -709,7 +698,7 @@
return -1;
}
- val = envmatch((uchar *)name, i);
+ val = env_match((uchar *)name, i);
if (val < 0)
continue;
@@ -768,18 +757,24 @@
"save environment variables to persistent storage",
""
);
+
+#if defined(CONFIG_CMD_ERASEENV)
+static int do_env_erase(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ return env_erase() ? 1 : 0;
+}
+
+U_BOOT_CMD(
+ eraseenv, 1, 0, do_env_erase,
+ "erase environment variables from persistent storage",
+ ""
+);
+#endif
#endif
#endif /* CONFIG_SPL_BUILD */
-
-/*
- * Match a name / name=value pair
- *
- * s1 is either a simple 'name', or a 'name=value' pair.
- * i2 is the environment index for a 'name2=value2' pair.
- * If the names match, return the index for the value2, else -1.
- */
-int envmatch(uchar *s1, int i2)
+int env_match(uchar *s1, int i2)
{
if (s1 == NULL)
return -1;
@@ -820,13 +815,13 @@
debug("Final value for argc=%d\n", argc);
if (all && (argc == 0)) {
/* Reset the whole environment */
- set_default_env("## Resetting to default environment\n",
+ env_set_default("## Resetting to default environment\n",
env_flag);
return 0;
}
if (!all && (argc > 0)) {
/* Reset individual variables */
- set_default_vars(argc, argv, env_flag);
+ env_set_default_vars(argc, argv, env_flag);
return 0;
}
@@ -1008,7 +1003,7 @@
envp->crc = crc32(0, envp->data,
size ? size - offsetof(env_t, data) : ENV_SIZE);
#ifdef CONFIG_ENV_ADDR_REDUND
- envp->flags = ACTIVE_FLAG;
+ envp->flags = ENV_REDUND_ACTIVE;
#endif
}
env_set_hex("filesize", len + offsetof(env_t, data));
@@ -1164,18 +1159,118 @@
}
#endif
+#if defined(CONFIG_CMD_NVEDIT_INFO)
+/*
+ * print_env_info - print environment information
+ */
+static int print_env_info(void)
+{
+ const char *value;
+
+ /* print environment validity value */
+ switch (gd->env_valid) {
+ case ENV_INVALID:
+ value = "invalid";
+ break;
+ case ENV_VALID:
+ value = "valid";
+ break;
+ case ENV_REDUND:
+ value = "redundant";
+ break;
+ default:
+ value = "unknown";
+ break;
+ }
+ printf("env_valid = %s\n", value);
+
+ /* print environment ready flag */
+ value = gd->flags & GD_FLG_ENV_READY ? "true" : "false";
+ printf("env_ready = %s\n", value);
+
+ /* print environment using default flag */
+ value = gd->flags & GD_FLG_ENV_DEFAULT ? "true" : "false";
+ printf("env_use_default = %s\n", value);
+
+ return CMD_RET_SUCCESS;
+}
+
+#define ENV_INFO_IS_DEFAULT BIT(0) /* default environment bit mask */
+#define ENV_INFO_IS_PERSISTED BIT(1) /* environment persistence bit mask */
+
+/*
+ * env info - display environment information
+ * env info [-d] - evaluate whether default environment is used
+ * env info [-p] - evaluate whether environment can be persisted
+ */
+static int do_env_info(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ int eval_flags = 0;
+ int eval_results = 0;
+
+ /* display environment information */
+ if (argc <= 1)
+ return print_env_info();
+
+ /* process options */
+ while (--argc > 0 && **++argv == '-') {
+ char *arg = *argv;
+
+ while (*++arg) {
+ switch (*arg) {
+ case 'd':
+ eval_flags |= ENV_INFO_IS_DEFAULT;
+ break;
+ case 'p':
+ eval_flags |= ENV_INFO_IS_PERSISTED;
+ break;
+ default:
+ return CMD_RET_USAGE;
+ }
+ }
+ }
+
+ /* evaluate whether default environment is used */
+ if (eval_flags & ENV_INFO_IS_DEFAULT) {
+ if (gd->flags & GD_FLG_ENV_DEFAULT) {
+ printf("Default environment is used\n");
+ eval_results |= ENV_INFO_IS_DEFAULT;
+ } else {
+ printf("Environment was loaded from persistent storage\n");
+ }
+ }
+
+ /* evaluate whether environment can be persisted */
+ if (eval_flags & ENV_INFO_IS_PERSISTED) {
+#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE)
+ printf("Environment can be persisted\n");
+ eval_results |= ENV_INFO_IS_PERSISTED;
+#else
+ printf("Environment cannot be persisted\n");
+#endif
+ }
+
+ /* The result of evaluations is combined with AND */
+ if (eval_flags != eval_results)
+ return CMD_RET_FAILURE;
+
+ return CMD_RET_SUCCESS;
+}
+#endif
+
#if defined(CONFIG_CMD_ENV_EXISTS)
static int do_env_exists(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
- ENTRY e, *ep;
+ struct env_entry e, *ep;
if (argc < 2)
return CMD_RET_USAGE;
e.key = argv[1];
e.data = NULL;
- hsearch_r(e, FIND, &ep, &env_htab, 0);
+ hsearch_r(e, ENV_FIND, &ep, &env_htab, 0);
return (ep == NULL) ? 1 : 0;
}
@@ -1208,12 +1303,18 @@
#if defined(CONFIG_CMD_IMPORTENV)
U_BOOT_CMD_MKENT(import, 5, 0, do_env_import, "", ""),
#endif
+#if defined(CONFIG_CMD_NVEDIT_INFO)
+ U_BOOT_CMD_MKENT(info, 2, 0, do_env_info, "", ""),
+#endif
U_BOOT_CMD_MKENT(print, CONFIG_SYS_MAXARGS, 1, do_env_print, "", ""),
#if defined(CONFIG_CMD_RUN)
U_BOOT_CMD_MKENT(run, CONFIG_SYS_MAXARGS, 1, do_run, "", ""),
#endif
#if defined(CONFIG_CMD_SAVEENV) && defined(ENV_IS_IN_DEVICE)
U_BOOT_CMD_MKENT(save, 1, 0, do_env_save, "", ""),
+#if defined(CONFIG_CMD_ERASEENV)
+ U_BOOT_CMD_MKENT(erase, 1, 0, do_env_erase, "", ""),
+#endif
#endif
U_BOOT_CMD_MKENT(set, CONFIG_SYS_MAXARGS, 0, do_env_set, "", ""),
#if defined(CONFIG_CMD_ENV_EXISTS)
@@ -1280,6 +1381,11 @@
#if defined(CONFIG_CMD_IMPORTENV)
"env import [-d] [-t [-r] | -b | -c] addr [size] [var ...] - import environment\n"
#endif
+#if defined(CONFIG_CMD_NVEDIT_INFO)
+ "env info - display environment information\n"
+ "env info [-d] - whether default environment is used\n"
+ "env info [-p] - whether environment can be persisted\n"
+#endif
"env print [-a | name ...] - print environment\n"
#if defined(CONFIG_CMD_NVEDIT_EFI)
"env print -e [name ...] - print UEFI environment\n"
@@ -1289,6 +1395,9 @@
#endif
#if defined(CONFIG_CMD_SAVEENV) && defined(ENV_IS_IN_DEVICE)
"env save - save environment\n"
+#if defined(CONFIG_CMD_ERASEENV)
+ "env erase - erase environment\n"
+#endif
#endif
#if defined(CONFIG_CMD_NVEDIT_EFI)
"env set -e name [arg ...] - set UEFI variable; unset if 'arg' not specified\n"
diff --git a/cmd/nvedit_efi.c b/cmd/nvedit_efi.c
index 60a8ac8..ed6d09a 100644
--- a/cmd/nvedit_efi.c
+++ b/cmd/nvedit_efi.c
@@ -9,6 +9,7 @@
#include <common.h>
#include <command.h>
#include <efi_loader.h>
+#include <env.h>
#include <exports.h>
#include <hexdump.h>
#include <malloc.h>
diff --git a/cmd/part.c b/cmd/part.c
index bfb6488..5e4e45c 100644
--- a/cmd/part.c
+++ b/cmd/part.c
@@ -18,12 +18,14 @@
#include <common.h>
#include <config.h>
#include <command.h>
+#include <env.h>
#include <part.h>
#include <vsprintf.h>
enum cmd_part_info {
CMD_PART_INFO_START = 0,
CMD_PART_INFO_SIZE,
+ CMD_PART_INFO_NUMBER
};
static int do_part_uuid(int argc, char * const argv[])
@@ -149,6 +151,9 @@
case CMD_PART_INFO_SIZE:
snprintf(buf, sizeof(buf), LBAF, info.size);
break;
+ case CMD_PART_INFO_NUMBER:
+ snprintf(buf, sizeof(buf), "0x%x", part);
+ break;
default:
printf("** Unknown cmd_part_info value: %d\n", param);
return 1;
@@ -172,6 +177,11 @@
return do_part_info(argc, argv, CMD_PART_INFO_SIZE);
}
+static int do_part_number(int argc, char * const argv[])
+{
+ return do_part_info(argc, argv, CMD_PART_INFO_NUMBER);
+}
+
static int do_part(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
if (argc < 2)
@@ -185,6 +195,8 @@
return do_part_start(argc - 2, argv + 2);
else if (!strcmp(argv[1], "size"))
return do_part_size(argc - 2, argv + 2);
+ else if (!strcmp(argv[1], "number"))
+ return do_part_number(argc - 2, argv + 2);
return CMD_RET_USAGE;
}
@@ -206,5 +218,8 @@
" part can be either partition number or partition name\n"
"part size <interface> <dev> <part> <varname>\n"
" - set environment variable to the size of the partition (in blocks)\n"
- " part can be either partition number or partition name"
+ " part can be either partition number or partition name\n"
+ "part number <interface> <dev> <part> <varname>\n"
+ " - set environment variable to the partition number using the partition name\n"
+ " part must be specified as partition name"
);
diff --git a/cmd/pcap.c b/cmd/pcap.c
new file mode 100644
index 0000000..980603f
--- /dev/null
+++ b/cmd/pcap.c
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019
+ * Ramon Fried <rfried.dev@gmail.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <net.h>
+#include <net/pcap.h>
+
+static int do_pcap_init(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ phys_addr_t addr;
+ unsigned int size;
+
+ if (argc != 3)
+ return CMD_RET_USAGE;
+
+ addr = simple_strtoul(argv[1], NULL, 16);
+ size = simple_strtoul(argv[2], NULL, 10);
+
+ return pcap_init(addr, size) ? CMD_RET_FAILURE : CMD_RET_SUCCESS;
+}
+
+static int do_pcap_start(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ return pcap_start_stop(true) ? CMD_RET_FAILURE : CMD_RET_SUCCESS;
+}
+
+static int do_pcap_stop(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ return pcap_start_stop(false) ? CMD_RET_FAILURE : CMD_RET_SUCCESS;
+}
+
+static int do_pcap_status(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ return pcap_print_status() ? CMD_RET_FAILURE : CMD_RET_SUCCESS;
+}
+
+static int do_pcap_clear(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ return pcap_clear() ? CMD_RET_FAILURE : CMD_RET_SUCCESS;
+}
+
+static char pcap_help_text[] =
+ "- network packet capture\n\n"
+ "pcap\n"
+ "pcap init\t\t\t<addr> <max_size>\n"
+ "pcap start\t\t\tstart capture\n"
+ "pcap stop\t\t\tstop capture\n"
+ "pcap status\t\t\tprint status\n"
+ "pcap clear\t\t\tclear capture buffer\n"
+ "\n"
+ "With:\n"
+ "\t<addr>: user address to which pcap will be stored (hexedcimal)\n"
+ "\t<max_size>: Maximum size of pcap file (decimal)\n"
+ "\n";
+
+U_BOOT_CMD_WITH_SUBCMDS(pcap, "pcap", pcap_help_text,
+ U_BOOT_SUBCMD_MKENT(init, 3, 0, do_pcap_init),
+ U_BOOT_SUBCMD_MKENT(start, 1, 0, do_pcap_start),
+ U_BOOT_SUBCMD_MKENT(stop, 1, 0, do_pcap_stop),
+ U_BOOT_SUBCMD_MKENT(status, 1, 0, do_pcap_status),
+ U_BOOT_SUBCMD_MKENT(clear, 1, 0, do_pcap_clear),
+);
diff --git a/cmd/pci.c b/cmd/pci.c
index 2c5ee2a..0043471 100644
--- a/cmd/pci.c
+++ b/cmd/pci.c
@@ -148,7 +148,7 @@
if ((!is_64 && size_low) || (is_64 && size)) {
size = ~size + 1;
- printf(" %d %#016llx %#016llx %d %s %s\n",
+ printf(" %d %#018llx %#018llx %d %s %s\n",
bar_id, (unsigned long long)base,
(unsigned long long)size, is_64 ? 64 : 32,
is_io ? "I/O" : "MEM",
@@ -629,10 +629,10 @@
return;
}
- printf("# %-16s %-16s %-16s %s\n", "Bus start", "Phys start", "Size",
+ printf("# %-18s %-18s %-18s %s\n", "Bus start", "Phys start", "Size",
"Flags");
for (i = 0, reg = hose->regions; i < hose->region_count; i++, reg++) {
- printf("%d %#016llx %#016llx %#016llx ", i,
+ printf("%d %#018llx %#018llx %#018llx ", i,
(unsigned long long)reg->bus_start,
(unsigned long long)reg->phys_start,
(unsigned long long)reg->size);
diff --git a/cmd/pcmcia.c b/cmd/pcmcia.c
deleted file mode 100644
index 3b7537b..0000000
--- a/cmd/pcmcia.c
+++ /dev/null
@@ -1,341 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2000-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- ********************************************************************
- *
- * Lots of code copied from:
- *
- * m8xx_pcmcia.c - Linux PCMCIA socket driver for the mpc8xx series.
- * (C) 1999-2000 Magnus Damm <damm@bitsmart.com>
- *
- * "The ExCA standard specifies that socket controllers should provide
- * two IO and five memory windows per socket, which can be independently
- * configured and positioned in the host address space and mapped to
- * arbitrary segments of card address space. " - David A Hinds. 1999
- *
- * This controller does _not_ meet the ExCA standard.
- *
- * m8xx pcmcia controller brief info:
- * + 8 windows (attrib, mem, i/o)
- * + up to two slots (SLOT_A and SLOT_B)
- * + inputpins, outputpins, event and mask registers.
- * - no offset register. sigh.
- *
- * Because of the lacking offset register we must map the whole card.
- * We assign each memory window PCMCIA_MEM_WIN_SIZE address space.
- * Make sure there is (PCMCIA_MEM_WIN_SIZE * PCMCIA_MEM_WIN_NO
- * * PCMCIA_SOCKETS_NO) bytes at PCMCIA_MEM_WIN_BASE.
- * The i/o windows are dynamically allocated at PCMCIA_IO_WIN_BASE.
- * They are maximum 64KByte each...
- */
-
-/* #define DEBUG 1 */
-
-/*
- * PCMCIA support
- */
-#include <common.h>
-#include <command.h>
-#include <config.h>
-#include <pcmcia.h>
-#include <asm/io.h>
-
-/* -------------------------------------------------------------------- */
-
-#if defined(CONFIG_CMD_PCMCIA)
-
-extern int pcmcia_on (void);
-extern int pcmcia_off (void);
-
-int do_pinit (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int rcode = 0;
-
- if (argc != 2) {
- printf ("Usage: pinit {on | off}\n");
- return 1;
- }
- if (strcmp(argv[1],"on") == 0) {
- rcode = pcmcia_on ();
- } else if (strcmp(argv[1],"off") == 0) {
- rcode = pcmcia_off ();
- } else {
- printf ("Usage: pinit {on | off}\n");
- return 1;
- }
-
- return rcode;
-}
-
-U_BOOT_CMD(
- pinit, 2, 0, do_pinit,
- "PCMCIA sub-system",
- "on - power on PCMCIA socket\n"
- "pinit off - power off PCMCIA socket"
-);
-
-#endif
-
-/* -------------------------------------------------------------------- */
-
-#undef CHECK_IDE_DEVICE
-
-#if defined(CONFIG_PXA_PCMCIA)
-#define CHECK_IDE_DEVICE
-#endif
-
-#ifdef CHECK_IDE_DEVICE
-
-int ide_devices_found;
-static uchar *known_cards[] = {
- (uchar *)"ARGOSY PnPIDE D5",
- NULL
-};
-
-#define MAX_TUPEL_SZ 512
-#define MAX_FEATURES 4
-
-#define MAX_IDENT_CHARS 64
-#define MAX_IDENT_FIELDS 4
-
-#define indent "\t "
-
-static void print_funcid (int func)
-{
- puts (indent);
- switch (func) {
- case CISTPL_FUNCID_MULTI:
- puts (" Multi-Function");
- break;
- case CISTPL_FUNCID_MEMORY:
- puts (" Memory");
- break;
- case CISTPL_FUNCID_SERIAL:
- puts (" Serial Port");
- break;
- case CISTPL_FUNCID_PARALLEL:
- puts (" Parallel Port");
- break;
- case CISTPL_FUNCID_FIXED:
- puts (" Fixed Disk");
- break;
- case CISTPL_FUNCID_VIDEO:
- puts (" Video Adapter");
- break;
- case CISTPL_FUNCID_NETWORK:
- puts (" Network Adapter");
- break;
- case CISTPL_FUNCID_AIMS:
- puts (" AIMS Card");
- break;
- case CISTPL_FUNCID_SCSI:
- puts (" SCSI Adapter");
- break;
- default:
- puts (" Unknown");
- break;
- }
- puts (" Card\n");
-}
-
-static void print_fixed (volatile uchar *p)
-{
- if (p == NULL)
- return;
-
- puts(indent);
-
- switch (*p) {
- case CISTPL_FUNCE_IDE_IFACE:
- { uchar iface = *(p+2);
-
- puts ((iface == CISTPL_IDE_INTERFACE) ? " IDE" : " unknown");
- puts (" interface ");
- break;
- }
- case CISTPL_FUNCE_IDE_MASTER:
- case CISTPL_FUNCE_IDE_SLAVE:
- { uchar f1 = *(p+2);
- uchar f2 = *(p+4);
-
- puts ((f1 & CISTPL_IDE_SILICON) ? " [silicon]" : " [rotating]");
-
- if (f1 & CISTPL_IDE_UNIQUE)
- puts (" [unique]");
-
- puts ((f1 & CISTPL_IDE_DUAL) ? " [dual]" : " [single]");
-
- if (f2 & CISTPL_IDE_HAS_SLEEP)
- puts (" [sleep]");
-
- if (f2 & CISTPL_IDE_HAS_STANDBY)
- puts (" [standby]");
-
- if (f2 & CISTPL_IDE_HAS_IDLE)
- puts (" [idle]");
-
- if (f2 & CISTPL_IDE_LOW_POWER)
- puts (" [low power]");
-
- if (f2 & CISTPL_IDE_REG_INHIBIT)
- puts (" [reg inhibit]");
-
- if (f2 & CISTPL_IDE_HAS_INDEX)
- puts (" [index]");
-
- if (f2 & CISTPL_IDE_IOIS16)
- puts (" [IOis16]");
-
- break;
- }
- }
- putc ('\n');
-}
-
-static int identify (volatile uchar *p)
-{
- uchar id_str[MAX_IDENT_CHARS];
- uchar data;
- uchar *t;
- uchar **card;
- int i, done;
-
- if (p == NULL)
- return (0); /* Don't know */
-
- t = id_str;
- done =0;
-
- for (i=0; i<=4 && !done; ++i, p+=2) {
- while ((data = *p) != '\0') {
- if (data == 0xFF) {
- done = 1;
- break;
- }
- *t++ = data;
- if (t == &id_str[MAX_IDENT_CHARS-1]) {
- done = 1;
- break;
- }
- p += 2;
- }
- if (!done)
- *t++ = ' ';
- }
- *t = '\0';
- while (--t > id_str) {
- if (*t == ' ')
- *t = '\0';
- else
- break;
- }
- puts ((char *)id_str);
- putc ('\n');
-
- for (card=known_cards; *card; ++card) {
- debug ("## Compare against \"%s\"\n", *card);
- if (strcmp((char *)*card, (char *)id_str) == 0) { /* found! */
- debug ("## CARD FOUND ##\n");
- return (1);
- }
- }
-
- return (0); /* don't know */
-}
-
-int check_ide_device (int slot)
-{
- volatile uchar *ident = NULL;
- volatile uchar *feature_p[MAX_FEATURES];
- volatile uchar *p, *start, *addr;
- int n_features = 0;
- uchar func_id = ~0;
- uchar code, len;
- ushort config_base = 0;
- int found = 0;
- int i;
-
- addr = (volatile uchar *)(CONFIG_SYS_PCMCIA_MEM_ADDR +
- CONFIG_SYS_PCMCIA_MEM_SIZE * (slot * 4));
- debug ("PCMCIA MEM: %08lX\n", (ulong)addr);
-
- start = p = (volatile uchar *) addr;
-
- while ((p - start) < MAX_TUPEL_SZ) {
-
- code = *p; p += 2;
-
- if (code == 0xFF) { /* End of chain */
- break;
- }
-
- len = *p; p += 2;
-#if defined(DEBUG) && (DEBUG > 1)
- { volatile uchar *q = p;
- printf ("\nTuple code %02x length %d\n\tData:",
- code, len);
-
- for (i = 0; i < len; ++i) {
- printf (" %02x", *q);
- q+= 2;
- }
- }
-#endif /* DEBUG */
- switch (code) {
- case CISTPL_VERS_1:
- ident = p + 4;
- break;
- case CISTPL_FUNCID:
- /* Fix for broken SanDisk which may have 0x80 bit set */
- func_id = *p & 0x7F;
- break;
- case CISTPL_FUNCE:
- if (n_features < MAX_FEATURES)
- feature_p[n_features++] = p;
- break;
- case CISTPL_CONFIG:
- config_base = (*(p+6) << 8) + (*(p+4));
- debug ("\n## Config_base = %04x ###\n", config_base);
- default:
- break;
- }
- p += 2 * len;
- }
-
- found = identify (ident);
-
- if (func_id != ((uchar)~0)) {
- print_funcid (func_id);
-
- if (func_id == CISTPL_FUNCID_FIXED)
- found = 1;
- else
- return (1); /* no disk drive */
- }
-
- for (i=0; i<n_features; ++i) {
- print_fixed (feature_p[i]);
- }
-
- if (!found) {
- printf ("unknown card type\n");
- return (1);
- }
-
- ide_devices_found |= (1 << slot);
-
- /* set I/O area in config reg -> only valid for ARGOSY D5!!! */
- *((uchar *)(addr + config_base)) = 1;
-#if 0
- printf("\n## Config_base = %04x ###\n", config_base);
- printf("Configuration Option Register: %02x @ %x\n", readb(addr + config_base), addr + config_base);
- printf("Card Configuration and Status Register: %02x\n", readb(addr + config_base + 2));
- printf("Pin Replacement Register Register: %02x\n", readb(addr + config_base + 4));
- printf("Socket and Copy Register: %02x\n", readb(addr + config_base + 6));
-#endif
- return (0);
-}
-
-#endif /* CHECK_IDE_DEVICE */
diff --git a/cmd/pinmux.c b/cmd/pinmux.c
index 6c8ec51..de909a1 100644
--- a/cmd/pinmux.c
+++ b/cmd/pinmux.c
@@ -27,6 +27,7 @@
printf("Can't get the pin-controller: %s!\n", name);
return CMD_RET_FAILURE;
}
+ /* fall through */
case 1:
if (!currdev) {
printf("Pin-controller device is not set!\n");
diff --git a/cmd/pxe.c b/cmd/pxe.c
index 1dd0a74..2059975 100644
--- a/cmd/pxe.c
+++ b/cmd/pxe.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <malloc.h>
#include <mapmem.h>
#include <lcd.h>
diff --git a/cmd/qfw.c b/cmd/qfw.c
index 7bf7005..af82662 100644
--- a/cmd/qfw.c
+++ b/cmd/qfw.c
@@ -5,6 +5,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <errno.h>
#include <qfw.h>
diff --git a/cmd/reiser.c b/cmd/reiser.c
index 2c0bca1..7f51b92 100644
--- a/cmd/reiser.c
+++ b/cmd/reiser.c
@@ -11,6 +11,7 @@
#include <common.h>
#include <config.h>
#include <command.h>
+#include <env.h>
#include <image.h>
#include <linux/ctype.h>
#include <asm/byteorder.h>
diff --git a/cmd/remoteproc.c b/cmd/remoteproc.c
index 81463f3..da6f3fc 100644
--- a/cmd/remoteproc.c
+++ b/cmd/remoteproc.c
@@ -34,6 +34,10 @@
uc_pdata = dev_get_uclass_platdata(dev);
+ /* Do not print if rproc is not probed */
+ if (!(dev->flags & DM_FLAG_ACTIVATED))
+ continue;
+
switch (uc_pdata->mem_type) {
case RPROC_INTERNAL_MEMORY_MAPPED:
type = "internal memory mapped";
@@ -68,12 +72,22 @@
static int do_rproc_init(cmd_tbl_t *cmdtp, int flag, int argc,
char *const argv[])
{
+ int id;
+
if (rproc_is_initialized()) {
printf("\tRemote Processors are already initialized\n");
- } else {
+ return CMD_RET_FAILURE;
+ }
+
+ if (argc == 1) {
if (!rproc_init())
return 0;
- printf("Few Remote Processors failed to be initalized\n");
+ printf("Few Remote Processors failed to be initialized\n");
+ } else if (argc == 2) {
+ id = (int)simple_strtoul(argv[1], NULL, 10);
+ if (!rproc_dev_init(id))
+ return 0;
+ printf("Remote Processor %d failed to be initialized\n", id);
}
return CMD_RET_FAILURE;
@@ -91,11 +105,6 @@
static int do_remoteproc_list(cmd_tbl_t *cmdtp, int flag, int argc,
char *const argv[])
{
- if (!rproc_is_initialized()) {
- printf("\t Remote Processors is not initialized\n");
- return CMD_RET_USAGE;
- }
-
if (print_remoteproc_list())
return CMD_RET_FAILURE;
@@ -130,11 +139,6 @@
return CMD_RET_USAGE;
}
- if (!rproc_is_initialized()) {
- printf("\tRemote Processors are not initialized\n");
- return CMD_RET_USAGE;
- }
-
ret = rproc_load(id, addr, size);
printf("Load Remote Processor %d with data@addr=0x%08lx %lu bytes:%s\n",
id, addr, size, ret ? " Failed!" : " Success!");
@@ -165,11 +169,6 @@
id = (int)simple_strtoul(argv[1], NULL, 10);
- if (!rproc_is_initialized()) {
- printf("\tRemote Processors are not initialized\n");
- return CMD_RET_USAGE;
- }
-
if (!strcmp(argv[0], "start")) {
ret = rproc_start(id);
} else if (!strcmp(argv[0], "stop")) {
@@ -203,8 +202,10 @@
}
static cmd_tbl_t cmd_remoteproc_sub[] = {
- U_BOOT_CMD_MKENT(init, 0, 1, do_rproc_init,
- "Enumerate and initialize all processors", ""),
+ U_BOOT_CMD_MKENT(init, 1, 1, do_rproc_init,
+ "Enumerate and initialize the remote processor(s)",
+ "id - ID of the remote processor\n"
+ "If id is not passed, initialize all the remote processors"),
U_BOOT_CMD_MKENT(list, 0, 1, do_remoteproc_list,
"list remote processors", ""),
U_BOOT_CMD_MKENT(load, 5, 1, do_remoteproc_load,
@@ -270,7 +271,8 @@
"\t\tNote: Services are dependent on the driver capability\n"
"\t\t 'list' command shows the capability of each device\n"
"\n\tSubcommands:\n"
- "\tinit - Enumerate and initalize the remote processors\n"
+ "\tinit <id> - Enumerate and initalize the remote processor.\n"
+ "\t if id is not passed, initialize all the remote prcessors\n"
"\tlist - list available remote processors\n"
"\tload <id> [addr] [size]- Load the remote processor with binary\n"
"\t image stored at address [addr] in memory\n"
diff --git a/cmd/setexpr.c b/cmd/setexpr.c
index 1a6cecd..0182f19 100644
--- a/cmd/setexpr.c
+++ b/cmd/setexpr.c
@@ -11,6 +11,7 @@
#include <common.h>
#include <config.h>
#include <command.h>
+#include <env.h>
#include <mapmem.h>
static ulong get_arg(char *s, int w)
diff --git a/cmd/source.c b/cmd/source.c
index 6d98a1c..3a51ebf 100644
--- a/cmd/source.c
+++ b/cmd/source.c
@@ -16,6 +16,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <image.h>
#include <malloc.h>
#include <mapmem.h>
@@ -44,7 +45,7 @@
source (ulong addr, const char *fit_uname)
{
ulong len;
-#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
+#if defined(CONFIG_LEGACY_IMAGE_FORMAT)
const image_header_t *hdr;
#endif
u32 *data;
@@ -61,7 +62,7 @@
buf = map_sysmem(addr, 0);
switch (genimg_get_format(buf)) {
-#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
+#if defined(CONFIG_LEGACY_IMAGE_FORMAT)
case IMAGE_FORMAT_LEGACY:
hdr = buf;
diff --git a/cmd/spl.c b/cmd/spl.c
index 038f488..56051b8 100644
--- a/cmd/spl.c
+++ b/cmd/spl.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <command.h>
#include <cmd_spl.h>
+#include <env.h>
#include <linux/libfdt.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/cmd/thordown.c b/cmd/thordown.c
index 19ae672..dd0544d 100644
--- a/cmd/thordown.c
+++ b/cmd/thordown.c
@@ -37,7 +37,11 @@
goto exit;
}
- g_dnl_register("usb_dnl_thor");
+ ret = g_dnl_register("usb_dnl_thor");
+ if (ret) {
+ pr_err("g_dnl_register failed %d\n", ret);
+ return ret;
+ }
ret = thor_init();
if (ret) {
diff --git a/cmd/tpm-common.c b/cmd/tpm-common.c
index 89f2aa0..38900fb 100644
--- a/cmd/tpm-common.c
+++ b/cmd/tpm-common.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <command.h>
#include <dm.h>
+#include <env.h>
#include <asm/unaligned.h>
#include <linux/string.h>
#include <tpm-common.h>
diff --git a/cmd/tpm-v1.c b/cmd/tpm-v1.c
index b75e093..2807331 100644
--- a/cmd/tpm-v1.c
+++ b/cmd/tpm-v1.c
@@ -4,6 +4,7 @@
*/
#include <common.h>
+#include <env.h>
#include <malloc.h>
#include <asm/unaligned.h>
#include <tpm-common.h>
diff --git a/cmd/tpm_test.c b/cmd/tpm_test.c
index 56a5aa4..c14dd75 100644
--- a/cmd/tpm_test.c
+++ b/cmd/tpm_test.c
@@ -5,7 +5,6 @@
#include <common.h>
#include <command.h>
-#include <environment.h>
#include <tpm-v1.h>
#include "tpm-user-utils.h"
diff --git a/cmd/trace.c b/cmd/trace.c
index 26bf096..392b129 100644
--- a/cmd/trace.c
+++ b/cmd/trace.c
@@ -5,6 +5,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <mapmem.h>
#include <trace.h>
#include <asm/io.h>
@@ -30,8 +31,7 @@
static int create_func_list(int argc, char * const argv[])
{
- size_t buff_size, avail, buff_ptr, used;
- unsigned int needed;
+ size_t buff_size, avail, buff_ptr, needed, used;
char *buff;
int err;
@@ -41,7 +41,7 @@
avail = buff_size - buff_ptr;
err = trace_list_functions(buff + buff_ptr, avail, &needed);
if (err)
- printf("Error: truncated (%#x bytes needed)\n", needed);
+ printf("Error: truncated (%#zx bytes needed)\n", needed);
used = min(avail, (size_t)needed);
printf("Function trace dumped to %08lx, size %#zx\n",
(ulong)map_to_sysmem(buff + buff_ptr), used);
@@ -54,8 +54,7 @@
static int create_call_list(int argc, char * const argv[])
{
- size_t buff_size, avail, buff_ptr, used;
- unsigned int needed;
+ size_t buff_size, avail, buff_ptr, needed, used;
char *buff;
int err;
@@ -65,7 +64,7 @@
avail = buff_size - buff_ptr;
err = trace_list_calls(buff + buff_ptr, avail, &needed);
if (err)
- printf("Error: truncated (%#x bytes needed)\n", needed);
+ printf("Error: truncated (%#zx bytes needed)\n", needed);
used = min(avail, (size_t)needed);
printf("Call list dumped to %08lx, size %#zx\n",
(ulong)map_to_sysmem(buff + buff_ptr), used);
diff --git a/cmd/ubi.c b/cmd/ubi.c
index c511a2f..ca5dc90 100644
--- a/cmd/ubi.c
+++ b/cmd/ubi.c
@@ -13,6 +13,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <exports.h>
#include <memalign.h>
#include <mtd.h>
diff --git a/cmd/unzip.c b/cmd/unzip.c
index 6c0f97c..afd58e7 100644
--- a/cmd/unzip.c
+++ b/cmd/unzip.c
@@ -6,6 +6,8 @@
#include <common.h>
#include <command.h>
+#include <env.h>
+#include <gzip.h>
static int do_unzip(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
diff --git a/cmd/x86/Makefile b/cmd/x86/Makefile
index 7071614..144b1cf 100644
--- a/cmd/x86/Makefile
+++ b/cmd/x86/Makefile
@@ -2,4 +2,5 @@
obj-y += mtrr.o
obj-$(CONFIG_CMD_EXCEPTION) += exception.o
+obj-$(CONFIG_USE_HOB) += hob.o
obj-$(CONFIG_HAVE_FSP) += fsp.o
diff --git a/cmd/x86/fsp.c b/cmd/x86/fsp.c
index 9f94ca9..efa1838 100644
--- a/cmd/x86/fsp.c
+++ b/cmd/x86/fsp.c
@@ -9,21 +9,6 @@
DECLARE_GLOBAL_DATA_PTR;
-static char *hob_type[] = {
- "reserved",
- "Hand-off",
- "Mem Alloc",
- "Res Desc",
- "GUID Ext",
- "FV",
- "CPU",
- "Mem Pool",
- "reserved",
- "FV2",
- "Load PEIM",
- "Capsule",
-};
-
static int do_hdr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
struct fsp_header *hdr = find_fsp_header();
@@ -72,57 +57,8 @@
return 0;
}
-static int do_hob(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- const struct hob_header *hdr;
- uint type;
- char *desc;
- int i = 0;
-
- hdr = gd->arch.hob_list;
-
- printf("HOB list address: 0x%08x\n\n", (unsigned int)hdr);
-
- printf("# | Address | Type | Len | ");
- printf("%42s\n", "GUID");
- printf("---|----------|-----------|------|-");
- printf("------------------------------------------\n");
- while (!end_of_hob(hdr)) {
- printf("%02x | %08x | ", i, (unsigned int)hdr);
- type = hdr->type;
- if (type == HOB_TYPE_UNUSED)
- desc = "*Unused*";
- else if (type == HOB_TYPE_EOH)
- desc = "*EOH*";
- else if (type >= 0 && type <= ARRAY_SIZE(hob_type))
- desc = hob_type[type];
- else
- desc = "*Invalid*";
- printf("%-9s | %04x | ", desc, hdr->len);
-
- if (type == HOB_TYPE_MEM_ALLOC || type == HOB_TYPE_RES_DESC ||
- type == HOB_TYPE_GUID_EXT) {
- struct efi_guid *guid = (struct efi_guid *)(hdr + 1);
- int j;
-
- printf("%08x-%04x-%04x", guid->data1,
- guid->data2, guid->data3);
- for (j = 0; j < ARRAY_SIZE(guid->data4); j++)
- printf("-%02x", guid->data4[j]);
- } else {
- printf("%42s", "Not Available");
- }
- printf("\n");
- hdr = get_next_hob(hdr);
- i++;
- }
-
- return 0;
-}
-
static cmd_tbl_t fsp_commands[] = {
U_BOOT_CMD_MKENT(hdr, 0, 1, do_hdr, "", ""),
- U_BOOT_CMD_MKENT(hob, 0, 1, do_hob, "", ""),
};
static int do_fsp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
@@ -146,6 +82,5 @@
U_BOOT_CMD(
fsp, 2, 1, do_fsp,
"Show Intel Firmware Support Package (FSP) related information",
- "hdr - Print FSP header information\n"
- "fsp hob - Print FSP Hand-Off Block (HOB) information"
+ "hdr - Print FSP header information"
);
diff --git a/cmd/x86/hob.c b/cmd/x86/hob.c
new file mode 100644
index 0000000..3967a7c
--- /dev/null
+++ b/cmd/x86/hob.c
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014-2015, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <efi.h>
+#include <asm/hob.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static char *hob_type[] = {
+ "reserved",
+ "Hand-off",
+ "Mem Alloc",
+ "Res Desc",
+ "GUID Ext",
+ "FV",
+ "CPU",
+ "Mem Pool",
+ "reserved",
+ "FV2",
+ "Load PEIM",
+ "Capsule",
+};
+
+static int do_hob(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ const struct hob_header *hdr;
+ uint type;
+ char *desc;
+ int i = 0;
+ efi_guid_t *guid;
+ char uuid[UUID_STR_LEN + 1];
+
+ hdr = gd->arch.hob_list;
+
+ printf("HOB list address: 0x%08x\n\n", (unsigned int)hdr);
+
+ printf("# | Address | Type | Len | ");
+ printf("%36s\n", "GUID");
+ printf("---|----------|-----------|------|-");
+ printf("------------------------------------\n");
+ while (!end_of_hob(hdr)) {
+ printf("%02x | %08x | ", i, (unsigned int)hdr);
+ type = hdr->type;
+ if (type == HOB_TYPE_UNUSED)
+ desc = "*Unused*";
+ else if (type == HOB_TYPE_EOH)
+ desc = "*EOH*";
+ else if (type >= 0 && type <= ARRAY_SIZE(hob_type))
+ desc = hob_type[type];
+ else
+ desc = "*Invalid*";
+ printf("%-9s | %04x | ", desc, hdr->len);
+
+ if (type == HOB_TYPE_MEM_ALLOC || type == HOB_TYPE_RES_DESC ||
+ type == HOB_TYPE_GUID_EXT) {
+ guid = (efi_guid_t *)(hdr + 1);
+ uuid_bin_to_str(guid->b, uuid, UUID_STR_FORMAT_GUID);
+ printf("%s", uuid);
+ } else {
+ printf("%36s", "Not Available");
+ }
+ printf("\n");
+ hdr = get_next_hob(hdr);
+ i++;
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(hob, 1, 1, do_hob,
+ "Print Hand-Off Block (HOB) information",
+ ""
+);
diff --git a/cmd/ximg.c b/cmd/ximg.c
index 32bfae8..a948100 100644
--- a/cmd/ximg.c
+++ b/cmd/ximg.c
@@ -13,6 +13,8 @@
*/
#include <common.h>
#include <command.h>
+#include <env.h>
+#include <gzip.h>
#include <image.h>
#include <mapmem.h>
#include <watchdog.h>
@@ -35,7 +37,7 @@
ulong data, len;
int verify;
int part = 0;
-#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
+#if defined(CONFIG_LEGACY_IMAGE_FORMAT)
ulong count;
image_header_t *hdr = NULL;
#endif
@@ -67,7 +69,7 @@
}
switch (genimg_get_format((void *)addr)) {
-#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
+#if defined(CONFIG_LEGACY_IMAGE_FORMAT)
case IMAGE_FORMAT_LEGACY:
printf("## Copying part %d from legacy image "
@@ -217,7 +219,7 @@
}
break;
#endif
-#if defined(CONFIG_BZIP2) && defined(CONFIG_IMAGE_FORMAT_LEGACY)
+#if defined(CONFIG_BZIP2) && defined(CONFIG_LEGACY_IMAGE_FORMAT)
case IH_COMP_BZIP2:
{
int i;
diff --git a/cmd/zfs.c b/cmd/zfs.c
index 384ac4c..ed5402b 100644
--- a/cmd/zfs.c
+++ b/cmd/zfs.c
@@ -12,6 +12,7 @@
#include <part.h>
#include <config.h>
#include <command.h>
+#include <env.h>
#include <image.h>
#include <linux/ctype.h>
#include <asm/byteorder.h>
diff --git a/cmd/zip.c b/cmd/zip.c
index 9cd400a..8ef46e9 100644
--- a/cmd/zip.c
+++ b/cmd/zip.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
static int do_zip(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
diff --git a/common/Kconfig b/common/Kconfig
index 6328786..28d5e9a 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -69,6 +69,13 @@
This is the size of the bootstage record list and is the maximum
number of bootstage records that can be recorded.
+config TPL_BOOTSTAGE_RECORD_COUNT
+ int "Number of boot stage records to store for TPL"
+ default 5
+ help
+ This is the size of the bootstage record list and is the maximum
+ number of bootstage records that can be recorded.
+
config BOOTSTAGE_FDT
bool "Store boot timing information in the OS device tree"
depends on BOOTSTAGE
@@ -118,6 +125,168 @@
This should be large enough to hold the bootstage stash. A value of
4096 (4KiB) is normally plenty.
+config SHOW_BOOT_PROGRESS
+ bool "Show boot progress in a board-specific manner"
+ help
+ Defining this option allows to add some board-specific code (calling
+ a user-provided function show_boot_progress(int) that enables you to
+ show the system's boot progress on some display (for example, some
+ LEDs) on your board. At the moment, the following checkpoints are
+ implemented:
+
+ Legacy uImage format:
+
+ Arg Where When
+ 1 common/cmd_bootm.c before attempting to boot an image
+ -1 common/cmd_bootm.c Image header has bad magic number
+ 2 common/cmd_bootm.c Image header has correct magic number
+ -2 common/cmd_bootm.c Image header has bad checksum
+ 3 common/cmd_bootm.c Image header has correct checksum
+ -3 common/cmd_bootm.c Image data has bad checksum
+ 4 common/cmd_bootm.c Image data has correct checksum
+ -4 common/cmd_bootm.c Image is for unsupported architecture
+ 5 common/cmd_bootm.c Architecture check OK
+ -5 common/cmd_bootm.c Wrong Image Type (not kernel, multi)
+ 6 common/cmd_bootm.c Image Type check OK
+ -6 common/cmd_bootm.c gunzip uncompression error
+ -7 common/cmd_bootm.c Unimplemented compression type
+ 7 common/cmd_bootm.c Uncompression OK
+ 8 common/cmd_bootm.c No uncompress/copy overwrite error
+ -9 common/cmd_bootm.c Unsupported OS (not Linux, BSD, VxWorks, QNX)
+
+ 9 common/image.c Start initial ramdisk verification
+ -10 common/image.c Ramdisk header has bad magic number
+ -11 common/image.c Ramdisk header has bad checksum
+ 10 common/image.c Ramdisk header is OK
+ -12 common/image.c Ramdisk data has bad checksum
+ 11 common/image.c Ramdisk data has correct checksum
+ 12 common/image.c Ramdisk verification complete, start loading
+ -13 common/image.c Wrong Image Type (not PPC Linux ramdisk)
+ 13 common/image.c Start multifile image verification
+ 14 common/image.c No initial ramdisk, no multifile, continue.
+
+ 15 arch/<arch>/lib/bootm.c All preparation done, transferring control to OS
+
+ -30 arch/powerpc/lib/board.c Fatal error, hang the system
+ -31 post/post.c POST test failed, detected by post_output_backlog()
+ -32 post/post.c POST test failed, detected by post_run_single()
+
+ 34 common/cmd_doc.c before loading a Image from a DOC device
+ -35 common/cmd_doc.c Bad usage of "doc" command
+ 35 common/cmd_doc.c correct usage of "doc" command
+ -36 common/cmd_doc.c No boot device
+ 36 common/cmd_doc.c correct boot device
+ -37 common/cmd_doc.c Unknown Chip ID on boot device
+ 37 common/cmd_doc.c correct chip ID found, device available
+ -38 common/cmd_doc.c Read Error on boot device
+ 38 common/cmd_doc.c reading Image header from DOC device OK
+ -39 common/cmd_doc.c Image header has bad magic number
+ 39 common/cmd_doc.c Image header has correct magic number
+ -40 common/cmd_doc.c Error reading Image from DOC device
+ 40 common/cmd_doc.c Image header has correct magic number
+ 41 common/cmd_ide.c before loading a Image from a IDE device
+ -42 common/cmd_ide.c Bad usage of "ide" command
+ 42 common/cmd_ide.c correct usage of "ide" command
+ -43 common/cmd_ide.c No boot device
+ 43 common/cmd_ide.c boot device found
+ -44 common/cmd_ide.c Device not available
+ 44 common/cmd_ide.c Device available
+ -45 common/cmd_ide.c wrong partition selected
+ 45 common/cmd_ide.c partition selected
+ -46 common/cmd_ide.c Unknown partition table
+ 46 common/cmd_ide.c valid partition table found
+ -47 common/cmd_ide.c Invalid partition type
+ 47 common/cmd_ide.c correct partition type
+ -48 common/cmd_ide.c Error reading Image Header on boot device
+ 48 common/cmd_ide.c reading Image Header from IDE device OK
+ -49 common/cmd_ide.c Image header has bad magic number
+ 49 common/cmd_ide.c Image header has correct magic number
+ -50 common/cmd_ide.c Image header has bad checksum
+ 50 common/cmd_ide.c Image header has correct checksum
+ -51 common/cmd_ide.c Error reading Image from IDE device
+ 51 common/cmd_ide.c reading Image from IDE device OK
+ 52 common/cmd_nand.c before loading a Image from a NAND device
+ -53 common/cmd_nand.c Bad usage of "nand" command
+ 53 common/cmd_nand.c correct usage of "nand" command
+ -54 common/cmd_nand.c No boot device
+ 54 common/cmd_nand.c boot device found
+ -55 common/cmd_nand.c Unknown Chip ID on boot device
+ 55 common/cmd_nand.c correct chip ID found, device available
+ -56 common/cmd_nand.c Error reading Image Header on boot device
+ 56 common/cmd_nand.c reading Image Header from NAND device OK
+ -57 common/cmd_nand.c Image header has bad magic number
+ 57 common/cmd_nand.c Image header has correct magic number
+ -58 common/cmd_nand.c Error reading Image from NAND device
+ 58 common/cmd_nand.c reading Image from NAND device OK
+
+ -60 common/env_common.c Environment has a bad CRC, using default
+
+ 64 net/eth.c starting with Ethernet configuration.
+ -64 net/eth.c no Ethernet found.
+ 65 net/eth.c Ethernet found.
+
+ -80 common/cmd_net.c usage wrong
+ 80 common/cmd_net.c before calling net_loop()
+ -81 common/cmd_net.c some error in net_loop() occurred
+ 81 common/cmd_net.c net_loop() back without error
+ -82 common/cmd_net.c size == 0 (File with size 0 loaded)
+ 82 common/cmd_net.c trying automatic boot
+ 83 common/cmd_net.c running "source" command
+ -83 common/cmd_net.c some error in automatic boot or "source" command
+ 84 common/cmd_net.c end without errors
+
+ FIT uImage format:
+
+ Arg Where When
+ 100 common/cmd_bootm.c Kernel FIT Image has correct format
+ -100 common/cmd_bootm.c Kernel FIT Image has incorrect format
+ 101 common/cmd_bootm.c No Kernel subimage unit name, using configuration
+ -101 common/cmd_bootm.c Can't get configuration for kernel subimage
+ 102 common/cmd_bootm.c Kernel unit name specified
+ -103 common/cmd_bootm.c Can't get kernel subimage node offset
+ 103 common/cmd_bootm.c Found configuration node
+ 104 common/cmd_bootm.c Got kernel subimage node offset
+ -104 common/cmd_bootm.c Kernel subimage hash verification failed
+ 105 common/cmd_bootm.c Kernel subimage hash verification OK
+ -105 common/cmd_bootm.c Kernel subimage is for unsupported architecture
+ 106 common/cmd_bootm.c Architecture check OK
+ -106 common/cmd_bootm.c Kernel subimage has wrong type
+ 107 common/cmd_bootm.c Kernel subimage type OK
+ -107 common/cmd_bootm.c Can't get kernel subimage data/size
+ 108 common/cmd_bootm.c Got kernel subimage data/size
+ -108 common/cmd_bootm.c Wrong image type (not legacy, FIT)
+ -109 common/cmd_bootm.c Can't get kernel subimage type
+ -110 common/cmd_bootm.c Can't get kernel subimage comp
+ -111 common/cmd_bootm.c Can't get kernel subimage os
+ -112 common/cmd_bootm.c Can't get kernel subimage load address
+ -113 common/cmd_bootm.c Image uncompress/copy overwrite error
+
+ 120 common/image.c Start initial ramdisk verification
+ -120 common/image.c Ramdisk FIT image has incorrect format
+ 121 common/image.c Ramdisk FIT image has correct format
+ 122 common/image.c No ramdisk subimage unit name, using configuration
+ -122 common/image.c Can't get configuration for ramdisk subimage
+ 123 common/image.c Ramdisk unit name specified
+ -124 common/image.c Can't get ramdisk subimage node offset
+ 125 common/image.c Got ramdisk subimage node offset
+ -125 common/image.c Ramdisk subimage hash verification failed
+ 126 common/image.c Ramdisk subimage hash verification OK
+ -126 common/image.c Ramdisk subimage for unsupported architecture
+ 127 common/image.c Architecture check OK
+ -127 common/image.c Can't get ramdisk subimage data/size
+ 128 common/image.c Got ramdisk subimage data/size
+ 129 common/image.c Can't get ramdisk load address
+ -129 common/image.c Got ramdisk load address
+
+ -130 common/cmd_doc.c Incorrect FIT image format
+ 131 common/cmd_doc.c FIT image format OK
+
+ -140 common/cmd_ide.c Incorrect FIT image format
+ 141 common/cmd_ide.c FIT image format OK
+
+ -150 common/cmd_nand.c Incorrect FIT image format
+ 151 common/cmd_nand.c FIT image format OK
+
endmenu
menu "Boot media"
diff --git a/common/autoboot.c b/common/autoboot.c
index 94133ea..b28bd68 100644
--- a/common/autoboot.c
+++ b/common/autoboot.c
@@ -9,7 +9,10 @@
#include <bootretry.h>
#include <cli.h>
#include <console.h>
+#include <env.h>
#include <fdtdec.h>
+#include <hash.h>
+#include <memalign.h>
#include <menu.h>
#include <post.h>
#include <u-boot/sha256.h>
@@ -27,9 +30,19 @@
/* Stored value of bootdelay, used by autoboot_command() */
static int stored_bootdelay;
+static int menukey;
-#if defined(CONFIG_AUTOBOOT_KEYED)
-#if defined(CONFIG_AUTOBOOT_STOP_STR_SHA256)
+#ifdef CONFIG_AUTOBOOT_ENCRYPTION
+#define AUTOBOOT_STOP_STR_SHA256 CONFIG_AUTOBOOT_STOP_STR_SHA256
+#else
+#define AUTOBOOT_STOP_STR_SHA256 ""
+#endif
+
+#ifdef CONFIG_USE_AUTOBOOT_MENUKEY
+#define AUTOBOOT_MENUKEY CONFIG_USE_AUTOBOOT_MENUKEY
+#else
+#define AUTOBOOT_MENUKEY 0
+#endif
/*
* Use a "constant-length" time compare function for this
@@ -48,12 +61,20 @@
return diff == 0;
}
-static int passwd_abort(uint64_t etime)
+/**
+ * passwd_abort_sha256() - check for a hashed key sequence to abort booting
+ *
+ * This checks for the user entering a SHA256 hash within a given time.
+ *
+ * @etime: Timeout value ticks (stop when get_ticks() reachs this)
+ * @return 0 if autoboot should continue, 1 if it should stop
+ */
+static int passwd_abort_sha256(uint64_t etime)
{
const char *sha_env_str = env_get("bootstopkeysha256");
u8 sha_env[SHA256_SUM_LEN];
- u8 sha[SHA256_SUM_LEN];
- char presskey[MAX_DELAY_STOP_STR];
+ u8 *sha;
+ char *presskey;
const char *algo_name = "sha256";
u_int presskey_len = 0;
int abort = 0;
@@ -61,7 +82,7 @@
int ret;
if (sha_env_str == NULL)
- sha_env_str = CONFIG_AUTOBOOT_STOP_STR_SHA256;
+ sha_env_str = AUTOBOOT_STOP_STR_SHA256;
/*
* Generate the binary value from the environment hash value
@@ -74,6 +95,9 @@
return 0;
}
+ presskey = malloc_cache_aligned(MAX_DELAY_STOP_STR);
+ sha = malloc_cache_aligned(SHA256_SUM_LEN);
+ size = SHA256_SUM_LEN;
/*
* We don't know how long the stop-string is, so we need to
* generate the sha256 hash upon each input character and
@@ -82,8 +106,11 @@
do {
if (tstc()) {
/* Check for input string overflow */
- if (presskey_len >= MAX_DELAY_STOP_STR)
+ if (presskey_len >= MAX_DELAY_STOP_STR) {
+ free(presskey);
+ free(sha);
return 0;
+ }
presskey[presskey_len++] = getc();
@@ -97,10 +124,20 @@
}
} while (!abort && get_ticks() <= etime);
+ free(presskey);
+ free(sha);
return abort;
}
-#else
-static int passwd_abort(uint64_t etime)
+
+/**
+ * passwd_abort_key() - check for a key sequence to aborted booting
+ *
+ * This checks for the user entering a string within a given time.
+ *
+ * @etime: Timeout value ticks (stop when get_ticks() reachs this)
+ * @return 0 if autoboot should continue, 1 if it should stop
+ */
+static int passwd_abort_key(uint64_t etime)
{
int abort = 0;
struct {
@@ -176,13 +213,12 @@
return abort;
}
-#endif
/***************************************************************************
* Watch for 'delay' seconds for autoboot stop or autoboot delay string.
* returns: 0 - no key string, allow autoboot 1 - got key string, abort
*/
-static int __abortboot(int bootdelay)
+static int abortboot_key_sequence(int bootdelay)
{
int abort;
uint64_t etime = endtick(bootdelay);
@@ -195,29 +231,22 @@
printf(CONFIG_AUTOBOOT_PROMPT, bootdelay);
# endif
- abort = passwd_abort(etime);
+ if (IS_ENABLED(CONFIG_AUTOBOOT_ENCRYPTION))
+ abort = passwd_abort_sha256(etime);
+ else
+ abort = passwd_abort_key(etime);
if (!abort)
debug_bootkeys("key timeout\n");
return abort;
}
-# else /* !defined(CONFIG_AUTOBOOT_KEYED) */
-
-#ifdef CONFIG_MENUKEY
-static int menukey;
-#endif
-
-static int __abortboot(int bootdelay)
+static int abortboot_single_key(int bootdelay)
{
int abort = 0;
unsigned long ts;
-#ifdef CONFIG_MENUPROMPT
- printf(CONFIG_MENUPROMPT);
-#else
printf("Hit any key to stop autoboot: %2d ", bootdelay);
-#endif
/*
* Check if key already pressed
@@ -234,13 +263,13 @@
ts = get_timer(0);
do {
if (tstc()) { /* we got a key press */
+ int key;
+
abort = 1; /* don't auto boot */
bootdelay = 0; /* no more delay */
-# ifdef CONFIG_MENUKEY
- menukey = getc();
-# else
- (void) getc(); /* consume input */
-# endif
+ key = getc(); /* consume input */
+ if (IS_ENABLED(CONFIG_USE_AUTOBOOT_MENUKEY))
+ menukey = key;
break;
}
udelay(10000);
@@ -253,26 +282,27 @@
return abort;
}
-# endif /* CONFIG_AUTOBOOT_KEYED */
static int abortboot(int bootdelay)
{
int abort = 0;
- if (bootdelay >= 0)
- abort = __abortboot(bootdelay);
+ if (bootdelay >= 0) {
+ if (IS_ENABLED(CONFIG_AUTOBOOT_KEYED))
+ abort = abortboot_key_sequence(bootdelay);
+ else
+ abort = abortboot_single_key(bootdelay);
+ }
-#ifdef CONFIG_SILENT_CONSOLE
- if (abort)
+ if (IS_ENABLED(CONFIG_SILENT_CONSOLE) && abort)
gd->flags &= ~GD_FLG_SILENT;
-#endif
return abort;
}
static void process_fdt_options(const void *blob)
{
-#if defined(CONFIG_OF_CONTROL) && defined(CONFIG_SYS_TEXT_BASE)
+#ifdef CONFIG_SYS_TEXT_BASE
ulong addr;
/* Add an env variable to point to a kernel payload, if available */
@@ -284,7 +314,7 @@
addr = fdtdec_get_config_int(gd->fdt_blob, "rootdisk-offset", 0);
if (addr)
env_set_addr("rootaddr", (void *)(CONFIG_SYS_TEXT_BASE + addr));
-#endif /* CONFIG_OF_CONTROL && CONFIG_SYS_TEXT_BASE */
+#endif /* CONFIG_SYS_TEXT_BASE */
}
const char *bootdelay_process(void)
@@ -297,16 +327,14 @@
s = env_get("bootdelay");
bootdelay = s ? (int)simple_strtol(s, NULL, 10) : CONFIG_BOOTDELAY;
-#ifdef CONFIG_OF_CONTROL
- bootdelay = fdtdec_get_config_int(gd->fdt_blob, "bootdelay",
- bootdelay);
-#endif
+ if (IS_ENABLED(CONFIG_OF_CONTROL))
+ bootdelay = fdtdec_get_config_int(gd->fdt_blob, "bootdelay",
+ bootdelay);
debug("### main_loop entered: bootdelay=%d\n\n", bootdelay);
-#if defined(CONFIG_MENU_SHOW)
- bootdelay = menu_show(bootdelay);
-#endif
+ if (IS_ENABLED(CONFIG_AUTOBOOT_MENU_SHOW))
+ bootdelay = menu_show(bootdelay);
bootretry_init_cmd_timeout();
#ifdef CONFIG_POST
@@ -319,7 +347,8 @@
else
s = env_get("bootcmd");
- process_fdt_options(gd->fdt_blob);
+ if (IS_ENABLED(CONFIG_OF_CONTROL))
+ process_fdt_options(gd->fdt_blob);
stored_bootdelay = bootdelay;
return s;
@@ -330,22 +359,24 @@
debug("### main_loop: bootcmd=\"%s\"\n", s ? s : "<UNDEFINED>");
if (stored_bootdelay != -1 && s && !abortboot(stored_bootdelay)) {
-#if defined(CONFIG_AUTOBOOT_KEYED) && !defined(CONFIG_AUTOBOOT_KEYED_CTRLC)
- int prev = disable_ctrlc(1); /* disable Control C checking */
-#endif
+ bool lock;
+ int prev;
+
+ lock = IS_ENABLED(CONFIG_AUTOBOOT_KEYED) &&
+ !IS_ENABLED(CONFIG_AUTOBOOT_KEYED_CTRLC);
+ if (lock)
+ prev = disable_ctrlc(1); /* disable Ctrl-C checking */
run_command_list(s, -1, 0);
-#if defined(CONFIG_AUTOBOOT_KEYED) && !defined(CONFIG_AUTOBOOT_KEYED_CTRLC)
- disable_ctrlc(prev); /* restore Control C checking */
-#endif
+ if (lock)
+ disable_ctrlc(prev); /* restore Ctrl-C checking */
}
-#ifdef CONFIG_MENUKEY
- if (menukey == CONFIG_MENUKEY) {
+ if (IS_ENABLED(CONFIG_USE_AUTOBOOT_MENUKEY) &&
+ menukey == AUTOBOOT_MENUKEY) {
s = env_get("menucmd");
if (s)
run_command_list(s, -1, 0);
}
-#endif /* CONFIG_MENUKEY */
}
diff --git a/common/avb_verify.c b/common/avb_verify.c
index 32034d9..36898a6 100644
--- a/common/avb_verify.c
+++ b/common/avb_verify.c
@@ -851,6 +851,7 @@
return AVB_IO_RESULT_OK;
}
+#ifdef CONFIG_OPTEE_TA_AVB
static AvbIOResult read_persistent_value(AvbOps *ops,
const char *name,
size_t buffer_size,
@@ -968,6 +969,8 @@
return rc;
}
+#endif
+
/**
* ============================================================================
* AVB2.0 AvbOps alloc/initialisation/free
diff --git a/common/board_f.c b/common/board_f.c
index c25eb18..591f18f 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -14,11 +14,13 @@
#include <console.h>
#include <cpu.h>
#include <dm.h>
-#include <environment.h>
+#include <env.h>
+#include <env_internal.h>
#include <fdtdec.h>
#include <fs.h>
#include <i2c.h>
#include <initcall.h>
+#include <lcd.h>
#include <malloc.h>
#include <mapmem.h>
#include <os.h>
@@ -425,13 +427,6 @@
gd->relocaddr = lcd_setmem(gd->relocaddr);
gd->fb_base = gd->relocaddr;
# endif /* CONFIG_FB_ADDR */
-#elif defined(CONFIG_VIDEO) && \
- (!defined(CONFIG_PPC)) && \
- !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \
- !defined(CONFIG_M68K)
- /* reserve memory for video display (always full pages) */
- gd->relocaddr = video_setmem(gd->relocaddr);
- gd->fb_base = gd->relocaddr;
#endif
return 0;
@@ -442,8 +437,8 @@
#ifdef CONFIG_TRACE
gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE;
gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE);
- debug("Reserving %dk for trace data at: %08lx\n",
- CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr);
+ debug("Reserving %luk for trace data at: %08lx\n",
+ (unsigned long)CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr);
#endif
return 0;
@@ -472,12 +467,38 @@
return 0;
}
+#ifdef CONFIG_SYS_NONCACHED_MEMORY
+static int reserve_noncached(void)
+{
+ /*
+ * The value of gd->start_addr_sp must match the value of malloc_start
+ * calculated in boatrd_f.c:initr_malloc(), which is passed to
+ * board_r.c:mem_malloc_init() and then used by
+ * cache.c:noncached_init()
+ *
+ * These calculations must match the code in cache.c:noncached_init()
+ */
+ gd->start_addr_sp = ALIGN(gd->start_addr_sp, MMU_SECTION_SIZE) -
+ MMU_SECTION_SIZE;
+ gd->start_addr_sp -= ALIGN(CONFIG_SYS_NONCACHED_MEMORY,
+ MMU_SECTION_SIZE);
+ debug("Reserving %dM for noncached_alloc() at: %08lx\n",
+ CONFIG_SYS_NONCACHED_MEMORY >> 20, gd->start_addr_sp);
+
+ return 0;
+}
+#endif
+
/* reserve memory for malloc() area */
static int reserve_malloc(void)
{
gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN;
debug("Reserving %dk for malloc() at: %08lx\n",
TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp);
+#ifdef CONFIG_SYS_NONCACHED_MEMORY
+ reserve_noncached();
+#endif
+
return 0;
}
@@ -839,7 +860,7 @@
#ifdef CONFIG_OF_CONTROL
fdtdec_setup,
#endif
-#ifdef CONFIG_TRACE
+#ifdef CONFIG_TRACE_EARLY
trace_early_init,
#endif
initf_malloc,
diff --git a/common/board_r.c b/common/board_r.c
index df24021..d6fb504 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -18,7 +18,8 @@
#include <command.h>
#include <console.h>
#include <dm.h>
-#include <environment.h>
+#include <env.h>
+#include <env_internal.h>
#include <fdtdec.h>
#include <ide.h>
#include <initcall.h>
@@ -49,6 +50,9 @@
#include <linux/err.h>
#include <efi_loader.h>
#include <wdt.h>
+#if defined(CONFIG_GPIO_HOG)
+#include <asm/gpio.h>
+#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -243,6 +247,10 @@
gd->malloc_ptr / 1024);
#endif
/* The malloc area is immediately below the monitor copy in DRAM */
+ /*
+ * This value MUST match the value of gd->start_addr_sp in board_f.c:
+ * reserve_noncached().
+ */
malloc_start = gd->relocaddr - TOTAL_MALLOC_LEN;
mem_malloc_init((ulong)map_sysmem(malloc_start, TOTAL_MALLOC_LEN),
TOTAL_MALLOC_LEN);
@@ -444,7 +452,7 @@
if (should_load_env())
env_relocate();
else
- set_default_env(NULL, 0);
+ env_set_default(NULL, 0);
#ifdef CONFIG_OF_CONTROL
env_set_hex("fdtcontroladdr",
(unsigned long)map_to_sysmem(gd->fdt_blob));
@@ -579,15 +587,6 @@
}
#endif
-#if defined(CONFIG_CMD_PCMCIA) && !defined(CONFIG_IDE)
-static int initr_pcmcia(void)
-{
- puts("PCMCIA:");
- pcmcia_init();
- return 0;
-}
-#endif
-
#if defined(CONFIG_IDE) && !defined(CONFIG_BLK)
static int initr_ide(void)
{
@@ -697,7 +696,7 @@
stdio_init_tables,
initr_serial,
initr_announce,
-#if defined(CONFIG_WDT)
+#if CONFIG_IS_ENABLED(WDT)
initr_watchdog,
#endif
INIT_FUNC_WATCHDOG_RESET
@@ -796,6 +795,9 @@
#ifdef CONFIG_CMD_NET
initr_ethaddr,
#endif
+#if defined(CONFIG_GPIO_HOG)
+ gpio_hog_probe_all,
+#endif
#ifdef CONFIG_BOARD_LATE_INIT
board_late_init,
#endif
@@ -813,9 +815,6 @@
#ifdef CONFIG_POST
initr_post,
#endif
-#if defined(CONFIG_CMD_PCMCIA) && !defined(CONFIG_IDE)
- initr_pcmcia,
-#endif
#if defined(CONFIG_IDE) && !defined(CONFIG_BLK)
initr_ide,
#endif
diff --git a/common/bootm.c b/common/bootm.c
index d193751..02295da 100644
--- a/common/bootm.c
+++ b/common/bootm.c
@@ -7,17 +7,13 @@
#ifndef USE_HOSTCC
#include <common.h>
#include <bootstage.h>
-#include <bzlib.h>
+#include <env.h>
#include <errno.h>
#include <fdt_support.h>
#include <lmb.h>
#include <malloc.h>
#include <mapmem.h>
#include <asm/io.h>
-#include <linux/lzo.h>
-#include <lzma/LzmaTypes.h>
-#include <lzma/LzmaDec.h>
-#include <lzma/LzmaTools.h>
#if defined(CONFIG_CMD_USB)
#include <usb.h>
#endif
@@ -98,7 +94,7 @@
/* get image parameters */
switch (genimg_get_format(os_hdr)) {
-#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
+#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
case IMAGE_FORMAT_LEGACY:
images.os.type = image_get_type(os_hdr);
images.os.comp = image_get_comp(os_hdr);
@@ -299,23 +295,7 @@
}
#endif /* USE_HOSTC */
-/**
- * print_decomp_msg() - Print a suitable decompression/loading message
- *
- * @type: OS type (IH_OS_...)
- * @comp_type: Compression type being used (IH_COMP_...)
- * @is_xip: true if the load address matches the image start
- */
-static void print_decomp_msg(int comp_type, int type, bool is_xip)
-{
- const char *name = genimg_get_type_name(type);
-
- if (comp_type == IH_COMP_NONE)
- printf(" %s %s ... ", is_xip ? "XIP" : "Loading", name);
- else
- printf(" Uncompressing %s ... ", name);
-}
-
+#if !defined(USE_HOSTCC) || defined(CONFIG_FIT_SIGNATURE)
/**
* handle_decomp_error() - display a decompression error
*
@@ -325,16 +305,18 @@
*
* @comp_type: Compression type being used (IH_COMP_...)
* @uncomp_size: Number of bytes uncompressed
- * @unc_len: Amount of space available for decompression
- * @ret: Error code to report
- * @return BOOTM_ERR_RESET, indicating that the board must be reset
+ * @ret: errno error code received from compression library
+ * @return Appropriate BOOTM_ERR_ error code
*/
-static int handle_decomp_error(int comp_type, size_t uncomp_size,
- size_t unc_len, int ret)
+static int handle_decomp_error(int comp_type, size_t uncomp_size, int ret)
{
const char *name = genimg_get_comp_name(comp_type);
- if (uncomp_size >= unc_len)
+ /* ENOSYS means unimplemented compression type, don't reset. */
+ if (ret == -ENOSYS)
+ return BOOTM_ERR_UNIMPLEMENTED;
+
+ if (uncomp_size >= CONFIG_SYS_BOOTM_LEN)
printf("Image too large: increase CONFIG_SYS_BOOTM_LEN\n");
else
printf("%s: uncompress error %d\n", name, ret);
@@ -351,93 +333,7 @@
return BOOTM_ERR_RESET;
}
-
-int bootm_decomp_image(int comp, ulong load, ulong image_start, int type,
- void *load_buf, void *image_buf, ulong image_len,
- uint unc_len, ulong *load_end)
-{
- int ret = 0;
-
- *load_end = load;
- print_decomp_msg(comp, type, load == image_start);
-
- /*
- * Load the image to the right place, decompressing if needed. After
- * this, image_len will be set to the number of uncompressed bytes
- * loaded, ret will be non-zero on error.
- */
- switch (comp) {
- case IH_COMP_NONE:
- if (load == image_start)
- break;
- if (image_len <= unc_len)
- memmove_wd(load_buf, image_buf, image_len, CHUNKSZ);
- else
- ret = 1;
- break;
-#ifdef CONFIG_GZIP
- case IH_COMP_GZIP: {
- ret = gunzip(load_buf, unc_len, image_buf, &image_len);
- break;
- }
-#endif /* CONFIG_GZIP */
-#ifdef CONFIG_BZIP2
- case IH_COMP_BZIP2: {
- uint size = unc_len;
-
- /*
- * If we've got less than 4 MB of malloc() space,
- * use slower decompression algorithm which requires
- * at most 2300 KB of memory.
- */
- ret = BZ2_bzBuffToBuffDecompress(load_buf, &size,
- image_buf, image_len,
- CONFIG_SYS_MALLOC_LEN < (4096 * 1024), 0);
- image_len = size;
- break;
- }
-#endif /* CONFIG_BZIP2 */
-#ifdef CONFIG_LZMA
- case IH_COMP_LZMA: {
- SizeT lzma_len = unc_len;
-
- ret = lzmaBuffToBuffDecompress(load_buf, &lzma_len,
- image_buf, image_len);
- image_len = lzma_len;
- break;
- }
-#endif /* CONFIG_LZMA */
-#ifdef CONFIG_LZO
- case IH_COMP_LZO: {
- size_t size = unc_len;
-
- ret = lzop_decompress(image_buf, image_len, load_buf, &size);
- image_len = size;
- break;
- }
-#endif /* CONFIG_LZO */
-#ifdef CONFIG_LZ4
- case IH_COMP_LZ4: {
- size_t size = unc_len;
-
- ret = ulz4fn(image_buf, image_len, load_buf, &size);
- image_len = size;
- break;
- }
-#endif /* CONFIG_LZ4 */
- default:
- printf("Unimplemented compression type %d\n", comp);
- return BOOTM_ERR_UNIMPLEMENTED;
- }
-
- if (ret)
- return handle_decomp_error(comp, image_len, unc_len, ret);
- *load_end = load + image_len;
-
- puts("OK\n");
-
- return 0;
-}
+#endif
#ifndef USE_HOSTCC
static int bootm_load_os(bootm_headers_t *images, int boot_progress)
@@ -456,10 +352,11 @@
load_buf = map_sysmem(load, 0);
image_buf = map_sysmem(os.image_start, image_len);
- err = bootm_decomp_image(os.comp, load, os.image_start, os.type,
- load_buf, image_buf, image_len,
- CONFIG_SYS_BOOTM_LEN, &load_end);
+ err = image_decomp(os.comp, load, os.image_start, os.type,
+ load_buf, image_buf, image_len,
+ CONFIG_SYS_BOOTM_LEN, &load_end);
if (err) {
+ err = handle_decomp_error(os.comp, load_end - load, err);
bootstage_error(BOOTSTAGE_ID_DECOMP_IMAGE);
return err;
}
@@ -738,7 +635,7 @@
return ret;
}
-#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
+#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
/**
* image_get_kernel - verify legacy format kernel image
* @img_addr: in RAM address of the legacy format image to be verified
@@ -807,7 +704,7 @@
char * const argv[], bootm_headers_t *images,
ulong *os_data, ulong *os_len)
{
-#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
+#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
image_header_t *hdr;
#endif
ulong img_addr;
@@ -828,7 +725,7 @@
*os_data = *os_len = 0;
buf = map_sysmem(img_addr, 0);
switch (genimg_get_format(buf)) {
-#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
+#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
case IMAGE_FORMAT_LEGACY:
printf("## Booting kernel from Legacy Image at %08lx ...\n",
img_addr);
@@ -919,11 +816,6 @@
#else /* USE_HOSTCC */
-void memmove_wd(void *to, void *from, size_t len, ulong chunksz)
-{
- memmove(to, from, len);
-}
-
#if defined(CONFIG_FIT_SIGNATURE)
static int bootm_host_load_image(const void *fit, int req_image_type)
{
@@ -957,13 +849,16 @@
/* Allow the image to expand by a factor of 4, should be safe */
load_buf = malloc((1 << 20) + len * 4);
- ret = bootm_decomp_image(imape_comp, 0, data, image_type, load_buf,
- (void *)data, len, CONFIG_SYS_BOOTM_LEN,
- &load_end);
+ ret = image_decomp(imape_comp, 0, data, image_type, load_buf,
+ (void *)data, len, CONFIG_SYS_BOOTM_LEN,
+ &load_end);
free(load_buf);
- if (ret && ret != BOOTM_ERR_UNIMPLEMENTED)
- return ret;
+ if (ret) {
+ ret = handle_decomp_error(imape_comp, load_end - 0, ret);
+ if (ret != BOOTM_ERR_UNIMPLEMENTED)
+ return ret;
+ }
return 0;
}
diff --git a/common/bootm_os.c b/common/bootm_os.c
index 855c471..6fb7d65 100644
--- a/common/bootm_os.c
+++ b/common/bootm_os.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <bootm.h>
+#include <env.h>
#include <fdt_support.h>
#include <linux/libfdt.h>
#include <malloc.h>
diff --git a/common/bootretry.c b/common/bootretry.c
index 072055b..47aaaa8 100644
--- a/common/bootretry.c
+++ b/common/bootretry.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <bootretry.h>
#include <cli.h>
+#include <env.h>
#include <errno.h>
#include <watchdog.h>
diff --git a/common/cli.c b/common/cli.c
index f4054fb..49b9106 100644
--- a/common/cli.c
+++ b/common/cli.c
@@ -12,6 +12,7 @@
#include <cli.h>
#include <cli_hush.h>
#include <console.h>
+#include <env.h>
#include <fdtdec.h>
#include <malloc.h>
diff --git a/common/cli_hush.c b/common/cli_hush.c
index 955e8fe..8f86e4a 100644
--- a/common/cli_hush.c
+++ b/common/cli_hush.c
@@ -75,6 +75,7 @@
#define __U_BOOT__
#ifdef __U_BOOT__
+#include <env.h>
#include <malloc.h> /* malloc, free, realloc*/
#include <linux/ctype.h> /* isalpha, isdigit */
#include <common.h> /* readline */
diff --git a/common/cli_simple.c b/common/cli_simple.c
index 311880a..6c881c1 100644
--- a/common/cli_simple.c
+++ b/common/cli_simple.c
@@ -12,6 +12,7 @@
#include <bootretry.h>
#include <cli.h>
#include <console.h>
+#include <env.h>
#include <linux/ctype.h>
#define DEBUG_PARSER 0 /* set to 1 to debug */
diff --git a/common/command.c b/common/command.c
index e192bb2..4b887a2 100644
--- a/common/command.c
+++ b/common/command.c
@@ -11,6 +11,7 @@
#include <common.h>
#include <command.h>
#include <console.h>
+#include <env.h>
#include <linux/ctype.h>
/*
@@ -356,8 +357,13 @@
int i, j, k, len, seplen, argc;
int cnt;
char last_char;
+#ifdef CONFIG_CMDLINE_PS_SUPPORT
+ const char *ps_prompt = env_get("PS1");
+#else
+ const char *ps_prompt = CONFIG_SYS_PROMPT;
+#endif
- if (strcmp(prompt, CONFIG_SYS_PROMPT) != 0)
+ if (strcmp(prompt, ps_prompt) != 0)
return 0; /* not in normal console */
cnt = strlen(buf);
diff --git a/common/console.c b/common/console.c
index 0b0dd76..89b1e95 100644
--- a/common/console.c
+++ b/common/console.c
@@ -8,6 +8,7 @@
#include <console.h>
#include <debug_uart.h>
#include <dm.h>
+#include <env.h>
#include <stdarg.h>
#include <iomux.h>
#include <malloc.h>
@@ -16,7 +17,7 @@
#include <serial.h>
#include <stdio_dev.h>
#include <exports.h>
-#include <environment.h>
+#include <env_internal.h>
#include <watchdog.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -463,6 +464,11 @@
char buf_out[CONFIG_PRE_CON_BUF_SZ + 1];
char *buf_in;
+#ifdef CONFIG_SILENT_CONSOLE
+ if (gd->flags & GD_FLG_SILENT)
+ return;
+#endif
+
buf_in = map_sysmem(CONFIG_PRE_CON_BUF_ADDR, CONFIG_PRE_CON_BUF_SZ);
if (gd->precon_buf_idx > CONFIG_PRE_CON_BUF_SZ)
in = gd->precon_buf_idx - CONFIG_PRE_CON_BUF_SZ;
@@ -511,8 +517,11 @@
membuff_putbyte(&gd->console_out, c);
#endif
#ifdef CONFIG_SILENT_CONSOLE
- if (gd->flags & GD_FLG_SILENT)
+ if (gd->flags & GD_FLG_SILENT) {
+ if (!(gd->flags & GD_FLG_DEVINIT))
+ pre_console_putc(c);
return;
+ }
#endif
#ifdef CONFIG_DISABLE_CONSOLE
@@ -559,8 +568,11 @@
membuff_put(&gd->console_out, s, strlen(s));
#endif
#ifdef CONFIG_SILENT_CONSOLE
- if (gd->flags & GD_FLG_SILENT)
+ if (gd->flags & GD_FLG_SILENT) {
+ if (!(gd->flags & GD_FLG_DEVINIT))
+ pre_console_puts(s);
return;
+ }
#endif
#ifdef CONFIG_DISABLE_CONSOLE
@@ -720,14 +732,22 @@
return -1;
}
-static void console_update_silent(void)
+/* return true if the 'silent' flag is removed */
+static bool console_update_silent(void)
{
#ifdef CONFIG_SILENT_CONSOLE
- if (env_get("silent") != NULL)
+ if (env_get("silent")) {
gd->flags |= GD_FLG_SILENT;
- else
+ } else {
+ unsigned long flags = gd->flags;
+
gd->flags &= ~GD_FLG_SILENT;
+
+ return !!(flags & GD_FLG_SILENT);
+ }
#endif
+
+ return false;
}
int console_announce_r(void)
@@ -792,6 +812,13 @@
#if CONFIG_IS_ENABLED(CONSOLE_MUX)
int iomux_err = 0;
#endif
+ int flushpoint;
+
+ /* update silent for env loaded from flash (initr_env) */
+ if (console_update_silent())
+ flushpoint = PRE_CONSOLE_FLUSHPOINT1_SERIAL;
+ else
+ flushpoint = PRE_CONSOLE_FLUSHPOINT2_EVERYTHING_BUT_SERIAL;
/* set default handlers at first */
gd->jt->getc = serial_getc;
@@ -869,7 +896,7 @@
if ((stdio_devices[stdin] == NULL) && (stdio_devices[stdout] == NULL))
return 0;
#endif
- print_pre_console_buffer(PRE_CONSOLE_FLUSHPOINT2_EVERYTHING_BUT_SERIAL);
+ print_pre_console_buffer(flushpoint);
return 0;
}
@@ -883,8 +910,13 @@
struct list_head *list = stdio_get_list();
struct list_head *pos;
struct stdio_dev *dev;
+ int flushpoint;
- console_update_silent();
+ /* update silent for env loaded from flash (initr_env) */
+ if (console_update_silent())
+ flushpoint = PRE_CONSOLE_FLUSHPOINT1_SERIAL;
+ else
+ flushpoint = PRE_CONSOLE_FLUSHPOINT2_EVERYTHING_BUT_SERIAL;
#ifdef CONFIG_SPLASH_SCREEN
/*
@@ -947,7 +979,7 @@
if ((stdio_devices[stdin] == NULL) && (stdio_devices[stdout] == NULL))
return 0;
#endif
- print_pre_console_buffer(PRE_CONSOLE_FLUSHPOINT2_EVERYTHING_BUT_SERIAL);
+ print_pre_console_buffer(flushpoint);
return 0;
}
diff --git a/common/edid.c b/common/edid.c
index 90d1167..f99f42d 100644
--- a/common/edid.c
+++ b/common/edid.c
@@ -168,8 +168,12 @@
return false;
}
-int edid_get_timing(u8 *buf, int buf_size, struct display_timing *timing,
- int *panel_bits_per_colourp)
+int edid_get_timing_validate(u8 *buf, int buf_size,
+ struct display_timing *timing,
+ int *panel_bits_per_colourp,
+ bool (*mode_valid)(void *priv,
+ const struct display_timing *timing),
+ void *mode_valid_priv)
{
struct edid1_info *edid = (struct edid1_info *)buf;
bool timing_done;
@@ -193,8 +197,14 @@
desc = &edid->monitor_details.descriptor[i];
if (desc->zero_flag_1 != 0) {
decode_timing((u8 *)desc, timing);
- timing_done = true;
- break;
+ if (mode_valid)
+ timing_done = mode_valid(mode_valid_priv,
+ timing);
+ else
+ timing_done = true;
+
+ if (timing_done)
+ break;
}
}
if (!timing_done)
@@ -225,6 +235,14 @@
return 0;
}
+int edid_get_timing(u8 *buf, int buf_size, struct display_timing *timing,
+ int *panel_bits_per_colourp)
+{
+ return edid_get_timing_validate(buf, buf_size, timing,
+ panel_bits_per_colourp, NULL, NULL);
+}
+
+
/**
* Snip the tailing whitespace/return of a string.
*
diff --git a/common/fdt_support.c b/common/fdt_support.c
index f31e9b0..baf7924 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -7,6 +7,7 @@
*/
#include <common.h>
+#include <env.h>
#include <mapmem.h>
#include <stdio_dev.h>
#include <linux/ctype.h>
@@ -671,30 +672,33 @@
dma_range[0] = 0;
if (size >= 0x100000000ull)
- dma_range[0] |= FDT_PCI_MEM64;
+ dma_range[0] |= cpu_to_fdt32(FDT_PCI_MEM64);
else
- dma_range[0] |= FDT_PCI_MEM32;
+ dma_range[0] |= cpu_to_fdt32(FDT_PCI_MEM32);
if (hose->regions[r].flags & PCI_REGION_PREFETCH)
- dma_range[0] |= FDT_PCI_PREFETCH;
+ dma_range[0] |= cpu_to_fdt32(FDT_PCI_PREFETCH);
#ifdef CONFIG_SYS_PCI_64BIT
- dma_range[1] = bus_start >> 32;
+ dma_range[1] = cpu_to_fdt32(bus_start >> 32);
#else
dma_range[1] = 0;
#endif
- dma_range[2] = bus_start & 0xffffffff;
+ dma_range[2] = cpu_to_fdt32(bus_start & 0xffffffff);
if (addrcell == 2) {
- dma_range[3] = phys_start >> 32;
- dma_range[4] = phys_start & 0xffffffff;
+ dma_range[3] = cpu_to_fdt32(phys_start >> 32);
+ dma_range[4] = cpu_to_fdt32(phys_start & 0xffffffff);
} else {
- dma_range[3] = phys_start & 0xffffffff;
+ dma_range[3] = cpu_to_fdt32(phys_start & 0xffffffff);
}
if (sizecell == 2) {
- dma_range[3 + addrcell + 0] = size >> 32;
- dma_range[3 + addrcell + 1] = size & 0xffffffff;
+ dma_range[3 + addrcell + 0] =
+ cpu_to_fdt32(size >> 32);
+ dma_range[3 + addrcell + 1] =
+ cpu_to_fdt32(size & 0xffffffff);
} else {
- dma_range[3 + addrcell + 0] = size & 0xffffffff;
+ dma_range[3 + addrcell + 0] =
+ cpu_to_fdt32(size & 0xffffffff);
}
dma_range += (3 + addrcell + sizecell);
@@ -1292,6 +1296,12 @@
return __of_translate_address(blob, node_offset, in_addr, "ranges");
}
+u64 fdt_translate_dma_address(const void *blob, int node_offset,
+ const fdt32_t *in_addr)
+{
+ return __of_translate_address(blob, node_offset, in_addr, "dma-ranges");
+}
+
/**
* fdt_node_offset_by_compat_reg: Find a node that matches compatiable and
* who's reg property matches a physical cpu address
@@ -1546,7 +1556,7 @@
prop = fdt_getprop(fdt, node, "reg", &size);
- return prop ? fdt_translate_address(fdt, node, prop) : 0;
+ return prop ? fdt_translate_address(fdt, node, prop) : OF_BAD_ADDR;
}
/*
diff --git a/common/hash.c b/common/hash.c
index 413a5bf..d33e329 100644
--- a/common/hash.c
+++ b/common/hash.c
@@ -12,6 +12,7 @@
#ifndef USE_HOSTCC
#include <common.h>
#include <command.h>
+#include <env.h>
#include <malloc.h>
#include <mapmem.h>
#include <hw_sha.h>
diff --git a/common/hwconfig.c b/common/hwconfig.c
index e9e956a..72f3c4e 100644
--- a/common/hwconfig.c
+++ b/common/hwconfig.c
@@ -11,6 +11,7 @@
#ifndef HWCONFIG_TEST
#include <config.h>
#include <common.h>
+#include <env.h>
#include <exports.h>
#include <hwconfig.h>
#include <linux/types.h>
diff --git a/common/image-android-dt.c b/common/image-android-dt.c
index 6916826..a2d52df 100644
--- a/common/image-android-dt.c
+++ b/common/image-android-dt.c
@@ -78,17 +78,18 @@
{
u32 fdt_size;
int root_node_off;
- const char *compatible = NULL;
+ const char *compatible;
- fdt_size = fdt_totalsize(fdt);
root_node_off = fdt_path_offset(fdt, "/");
if (root_node_off < 0) {
printf("Error: Root node not found\n");
- } else {
- compatible = fdt_getprop(fdt, root_node_off, "compatible",
- NULL);
+ return;
}
+ fdt_size = fdt_totalsize(fdt);
+ compatible = fdt_getprop(fdt, root_node_off, "compatible",
+ NULL);
+
printf(" (FDT)size = %d\n", fdt_size);
printf(" (FDT)compatible = %s\n",
compatible ? compatible : "(unknown)");
diff --git a/common/image-android.c b/common/image-android.c
index 8b0f6b3..264bf90 100644
--- a/common/image-android.c
+++ b/common/image-android.c
@@ -4,6 +4,7 @@
*/
#include <common.h>
+#include <env.h>
#include <image.h>
#include <android_image.h>
#include <malloc.h>
@@ -52,6 +53,8 @@
ulong *os_data, ulong *os_len)
{
u32 kernel_addr = android_image_get_kernel_addr(hdr);
+ const struct image_header *ihdr = (const struct image_header *)
+ ((uintptr_t)hdr + hdr->page_size);
/*
* Not all Android tools use the id field for signing the image with
@@ -93,11 +96,19 @@
env_set("bootargs", newbootargs);
if (os_data) {
- *os_data = (ulong)hdr;
- *os_data += hdr->page_size;
+ if (image_get_magic(ihdr) == IH_MAGIC) {
+ *os_data = image_get_data(ihdr);
+ } else {
+ *os_data = (ulong)hdr;
+ *os_data += hdr->page_size;
+ }
}
- if (os_len)
- *os_len = hdr->kernel_size;
+ if (os_len) {
+ if (image_get_magic(ihdr) == IH_MAGIC)
+ *os_len = image_get_data_size(ihdr);
+ else
+ *os_len = hdr->kernel_size;
+ }
return 0;
}
@@ -131,7 +142,9 @@
{
const void *p = (void *)((uintptr_t)hdr + hdr->page_size);
- if (get_unaligned_le32(p) == LZ4F_MAGIC)
+ if (image_get_magic((image_header_t *)p) == IH_MAGIC)
+ return image_get_comp((image_header_t *)p);
+ else if (get_unaligned_le32(p) == LZ4F_MAGIC)
return IH_COMP_LZ4;
else
return IH_COMP_NONE;
diff --git a/common/image-fdt.c b/common/image-fdt.c
index eb552ca..4247dce 100644
--- a/common/image-fdt.c
+++ b/common/image-fdt.c
@@ -11,6 +11,7 @@
#include <common.h>
#include <fdt_support.h>
#include <fdtdec.h>
+#include <env.h>
#include <errno.h>
#include <image.h>
#include <linux/libfdt.h>
@@ -33,7 +34,7 @@
puts(" - must RESET the board to recover.\n");
}
-#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
+#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
static const image_header_t *image_get_fdt(ulong fdt_addr)
{
const image_header_t *fdt_hdr = map_sysmem(fdt_addr, 0);
@@ -263,7 +264,7 @@
int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch,
bootm_headers_t *images, char **of_flat_tree, ulong *of_size)
{
-#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
+#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
const image_header_t *fdt_hdr;
ulong load, load_end;
ulong image_start, image_data, image_end;
@@ -344,7 +345,7 @@
*/
buf = map_sysmem(fdt_addr, 0);
switch (genimg_get_format(buf)) {
-#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
+#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
case IMAGE_FORMAT_LEGACY:
/* verify fdt_addr points to a valid image header */
printf("## Flattened Device Tree from Legacy Image at %08lx\n",
diff --git a/common/image-fit.c b/common/image-fit.c
index a74b44f..5c63c76 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -22,6 +22,7 @@
DECLARE_GLOBAL_DATA_PTR;
#endif /* !USE_HOSTCC*/
+#include <bootm.h>
#include <image.h>
#include <bootstage.h>
#include <u-boot/crc.h>
@@ -1521,6 +1522,10 @@
* compatible list, "foo,bar", matches a compatible string in the root of fdt1.
* "bim,bam" in fdt2 matches the second string which isn't as good as fdt1.
*
+ * As an optimization, the compatible property from the FDT's root node can be
+ * copied into the configuration node in the FIT image. This is required to
+ * match configurations with compressed FDTs.
+ *
* returns:
* offset to the configuration to use if one was found
* -1 otherwise
@@ -1553,48 +1558,62 @@
for (noffset = fdt_next_node(fit, confs_noffset, &ndepth);
(noffset >= 0) && (ndepth > 0);
noffset = fdt_next_node(fit, noffset, &ndepth)) {
- const void *kfdt;
+ const void *fdt;
const char *kfdt_name;
- int kfdt_noffset;
+ int kfdt_noffset, compat_noffset;
const char *cur_fdt_compat;
int len;
- size_t size;
+ size_t sz;
int i;
if (ndepth > 1)
continue;
- kfdt_name = fdt_getprop(fit, noffset, "fdt", &len);
- if (!kfdt_name) {
- debug("No fdt property found.\n");
- continue;
- }
- kfdt_noffset = fdt_subnode_offset(fit, images_noffset,
- kfdt_name);
- if (kfdt_noffset < 0) {
- debug("No image node named \"%s\" found.\n",
- kfdt_name);
- continue;
- }
- /*
- * Get a pointer to this configuration's fdt.
- */
- if (fit_image_get_data(fit, kfdt_noffset, &kfdt, &size)) {
- debug("Failed to get fdt \"%s\".\n", kfdt_name);
- continue;
+ /* If there's a compat property in the config node, use that. */
+ if (fdt_getprop(fit, noffset, "compatible", NULL)) {
+ fdt = fit; /* search in FIT image */
+ compat_noffset = noffset; /* search under config node */
+ } else { /* Otherwise extract it from the kernel FDT. */
+ kfdt_name = fdt_getprop(fit, noffset, "fdt", &len);
+ if (!kfdt_name) {
+ debug("No fdt property found.\n");
+ continue;
+ }
+ kfdt_noffset = fdt_subnode_offset(fit, images_noffset,
+ kfdt_name);
+ if (kfdt_noffset < 0) {
+ debug("No image node named \"%s\" found.\n",
+ kfdt_name);
+ continue;
+ }
+
+ if (!fit_image_check_comp(fit, kfdt_noffset,
+ IH_COMP_NONE)) {
+ debug("Can't extract compat from \"%s\" "
+ "(compressed)\n", kfdt_name);
+ continue;
+ }
+
+ /* search in this config's kernel FDT */
+ if (fit_image_get_data(fit, kfdt_noffset, &fdt, &sz)) {
+ debug("Failed to get fdt \"%s\".\n", kfdt_name);
+ continue;
+ }
+
+ compat_noffset = 0; /* search kFDT under root node */
}
len = fdt_compat_len;
cur_fdt_compat = fdt_compat;
/*
* Look for a match for each U-Boot compatibility string in
- * turn in this configuration's fdt.
+ * turn in the compat string property.
*/
for (i = 0; len > 0 &&
(!best_match_offset || best_match_pos > i); i++) {
int cur_len = strlen(cur_fdt_compat) + 1;
- if (!fdt_node_check_compatible(kfdt, 0,
+ if (!fdt_node_check_compatible(fdt, compat_noffset,
cur_fdt_compat)) {
best_match_offset = noffset;
best_match_pos = i;
@@ -1795,11 +1814,12 @@
const char *fit_uname_config;
const char *fit_base_uname_config;
const void *fit;
- const void *buf;
+ void *buf;
+ void *loadbuf;
size_t size;
int type_ok, os_ok;
- ulong load, data, len;
- uint8_t os;
+ ulong load, load_end, data, len;
+ uint8_t os, comp;
#ifndef USE_HOSTCC
uint8_t os_arch;
#endif
@@ -1895,12 +1915,6 @@
images->os.arch = os_arch;
#endif
- if (image_type == IH_TYPE_FLATDT &&
- !fit_image_check_comp(fit, noffset, IH_COMP_NONE)) {
- puts("FDT image is compressed");
- return -EPROTONOSUPPORT;
- }
-
bootstage_mark(bootstage_id + BOOTSTAGE_SUB_CHECK_ALL);
type_ok = fit_image_check_type(fit, noffset, image_type) ||
fit_image_check_type(fit, noffset, IH_TYPE_FIRMWARE) ||
@@ -1931,7 +1945,8 @@
bootstage_mark(bootstage_id + BOOTSTAGE_SUB_CHECK_ALL_OK);
/* get image data address and length */
- if (fit_image_get_data_and_size(fit, noffset, &buf, &size)) {
+ if (fit_image_get_data_and_size(fit, noffset,
+ (const void **)&buf, &size)) {
printf("Could not find %s subimage data!\n", prop_name);
bootstage_error(bootstage_id + BOOTSTAGE_SUB_GET_DATA);
return -ENOENT;
@@ -1939,30 +1954,15 @@
#if !defined(USE_HOSTCC) && defined(CONFIG_FIT_IMAGE_POST_PROCESS)
/* perform any post-processing on the image data */
- board_fit_image_post_process((void **)&buf, &size);
+ board_fit_image_post_process(&buf, &size);
#endif
len = (ulong)size;
- /* verify that image data is a proper FDT blob */
- if (image_type == IH_TYPE_FLATDT && fdt_check_header(buf)) {
- puts("Subimage data is not a FDT");
- return -ENOEXEC;
- }
-
bootstage_mark(bootstage_id + BOOTSTAGE_SUB_GET_DATA_OK);
- /*
- * Work-around for eldk-4.2 which gives this warning if we try to
- * cast in the unmap_sysmem() call:
- * warning: initialization discards qualifiers from pointer target type
- */
- {
- void *vbuf = (void *)buf;
-
- data = map_to_sysmem(vbuf);
- }
-
+ data = map_to_sysmem(buf);
+ load = data;
if (load_op == FIT_LOAD_IGNORED) {
/* Don't load */
} else if (fit_image_get_load(fit, noffset, &load)) {
@@ -1974,8 +1974,6 @@
}
} else if (load_op != FIT_LOAD_OPTIONAL_NON_ZERO || load) {
ulong image_start, image_end;
- ulong load_end;
- void *dst;
/*
* move image data to the load address,
@@ -1993,14 +1991,50 @@
printf(" Loading %s from 0x%08lx to 0x%08lx\n",
prop_name, data, load);
-
- dst = map_sysmem(load, len);
- memmove(dst, buf, len);
- data = load;
+ } else {
+ load = data; /* No load address specified */
}
+
+ comp = IH_COMP_NONE;
+ loadbuf = buf;
+ /* Kernel images get decompressed later in bootm_load_os(). */
+ if (!fit_image_get_comp(fit, noffset, &comp) &&
+ comp != IH_COMP_NONE &&
+ !(image_type == IH_TYPE_KERNEL ||
+ image_type == IH_TYPE_KERNEL_NOLOAD ||
+ image_type == IH_TYPE_RAMDISK)) {
+ ulong max_decomp_len = len * 20;
+ if (load == data) {
+ loadbuf = malloc(max_decomp_len);
+ load = map_to_sysmem(loadbuf);
+ } else {
+ loadbuf = map_sysmem(load, max_decomp_len);
+ }
+ if (image_decomp(comp, load, data, image_type,
+ loadbuf, buf, len, max_decomp_len, &load_end)) {
+ printf("Error decompressing %s\n", prop_name);
+
+ return -ENOEXEC;
+ }
+ len = load_end - load;
+ } else if (load != data) {
+ loadbuf = map_sysmem(load, len);
+ memcpy(loadbuf, buf, len);
+ }
+
+ if (image_type == IH_TYPE_RAMDISK && comp != IH_COMP_NONE)
+ puts("WARNING: 'compression' nodes for ramdisks are deprecated,"
+ " please fix your .its file!\n");
+
+ /* verify that image data is a proper FDT blob */
+ if (image_type == IH_TYPE_FLATDT && fdt_check_header(loadbuf)) {
+ puts("Subimage data is not a FDT");
+ return -ENOEXEC;
+ }
+
bootstage_mark(bootstage_id + BOOTSTAGE_SUB_LOAD);
- *datap = data;
+ *datap = load;
*lenp = len;
if (fit_unamep)
*fit_unamep = (char *)fit_uname;
diff --git a/common/image.c b/common/image.c
index 75b84d5..179eef0 100644
--- a/common/image.c
+++ b/common/image.c
@@ -8,6 +8,7 @@
#ifndef USE_HOSTCC
#include <common.h>
+#include <env.h>
#include <watchdog.h>
#ifdef CONFIG_SHOW_BOOT_PROGRESS
@@ -16,7 +17,7 @@
#include <rtc.h>
-#include <environment.h>
+#include <gzip.h>
#include <image.h>
#include <mapmem.h>
@@ -32,13 +33,19 @@
#include <linux/errno.h>
#include <asm/io.h>
+#include <bzlib.h>
+#include <linux/lzo.h>
+#include <lzma/LzmaTypes.h>
+#include <lzma/LzmaDec.h>
+#include <lzma/LzmaTools.h>
+
#ifdef CONFIG_CMD_BDI
extern int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
#endif
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
+#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
static const image_header_t *image_get_ramdisk(ulong rd_addr, uint8_t arch,
int verify);
#endif
@@ -125,6 +132,7 @@
#if defined(CONFIG_BOOTM_OPENRTOS) || defined(USE_HOSTCC)
{ IH_OS_OPENRTOS, "openrtos", "OpenRTOS", },
#endif
+ { IH_OS_OPENSBI, "opensbi", "RISC-V OpenSBI", },
{ -1, "", "", },
};
@@ -168,6 +176,7 @@
{ IH_TYPE_PMMC, "pmmc", "TI Power Management Micro-Controller Firmware",},
{ IH_TYPE_STM32IMAGE, "stm32image", "STMicroelectronics STM32 Image" },
{ IH_TYPE_MTKIMAGE, "mtk_image", "MediaTek BootROM loadable Image" },
+ { IH_TYPE_COPRO, "copro", "Coprocessor Image"},
{ -1, "", "", },
};
@@ -375,9 +384,109 @@
}
}
+/**
+ * print_decomp_msg() - Print a suitable decompression/loading message
+ *
+ * @type: OS type (IH_OS_...)
+ * @comp_type: Compression type being used (IH_COMP_...)
+ * @is_xip: true if the load address matches the image start
+ */
+static void print_decomp_msg(int comp_type, int type, bool is_xip)
+{
+ const char *name = genimg_get_type_name(type);
+
+ if (comp_type == IH_COMP_NONE)
+ printf(" %s %s\n", is_xip ? "XIP" : "Loading", name);
+ else
+ printf(" Uncompressing %s\n", name);
+}
+
+int image_decomp(int comp, ulong load, ulong image_start, int type,
+ void *load_buf, void *image_buf, ulong image_len,
+ uint unc_len, ulong *load_end)
+{
+ int ret = 0;
+
+ *load_end = load;
+ print_decomp_msg(comp, type, load == image_start);
+
+ /*
+ * Load the image to the right place, decompressing if needed. After
+ * this, image_len will be set to the number of uncompressed bytes
+ * loaded, ret will be non-zero on error.
+ */
+ switch (comp) {
+ case IH_COMP_NONE:
+ if (load == image_start)
+ break;
+ if (image_len <= unc_len)
+ memmove_wd(load_buf, image_buf, image_len, CHUNKSZ);
+ else
+ ret = -ENOSPC;
+ break;
+#ifdef CONFIG_GZIP
+ case IH_COMP_GZIP: {
+ ret = gunzip(load_buf, unc_len, image_buf, &image_len);
+ break;
+ }
+#endif /* CONFIG_GZIP */
+#ifdef CONFIG_BZIP2
+ case IH_COMP_BZIP2: {
+ uint size = unc_len;
+
+ /*
+ * If we've got less than 4 MB of malloc() space,
+ * use slower decompression algorithm which requires
+ * at most 2300 KB of memory.
+ */
+ ret = BZ2_bzBuffToBuffDecompress(load_buf, &size,
+ image_buf, image_len,
+ CONFIG_SYS_MALLOC_LEN < (4096 * 1024), 0);
+ image_len = size;
+ break;
+ }
+#endif /* CONFIG_BZIP2 */
+#ifdef CONFIG_LZMA
+ case IH_COMP_LZMA: {
+ SizeT lzma_len = unc_len;
+
+ ret = lzmaBuffToBuffDecompress(load_buf, &lzma_len,
+ image_buf, image_len);
+ image_len = lzma_len;
+ break;
+ }
+#endif /* CONFIG_LZMA */
+#ifdef CONFIG_LZO
+ case IH_COMP_LZO: {
+ size_t size = unc_len;
+
+ ret = lzop_decompress(image_buf, image_len, load_buf, &size);
+ image_len = size;
+ break;
+ }
+#endif /* CONFIG_LZO */
+#ifdef CONFIG_LZ4
+ case IH_COMP_LZ4: {
+ size_t size = unc_len;
+
+ ret = ulz4fn(image_buf, image_len, load_buf, &size);
+ image_len = size;
+ break;
+ }
+#endif /* CONFIG_LZ4 */
+ default:
+ printf("Unimplemented compression type %d\n", comp);
+ return -ENOSYS;
+ }
+
+ *load_end = load + image_len;
+
+ return ret;
+}
+
#ifndef USE_HOSTCC
-#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
+#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
/**
* image_get_ramdisk - get and verify ramdisk image
* @rd_addr: ramdisk image start address
@@ -551,6 +660,11 @@
memmove(to, from, len);
#endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */
}
+#else /* USE_HOSTCC */
+void memmove_wd(void *to, void *from, size_t len, ulong chunksz)
+{
+ memmove(to, from, len);
+}
#endif /* !USE_HOSTCC */
void genimg_print_size(uint32_t size)
@@ -867,7 +981,7 @@
*/
int genimg_get_format(const void *img_addr)
{
-#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
+#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
const image_header_t *hdr;
hdr = (const image_header_t *)img_addr;
@@ -933,7 +1047,7 @@
{
ulong rd_addr, rd_load;
ulong rd_data, rd_len;
-#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
+#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
const image_header_t *rd_hdr;
#endif
void *buf;
@@ -1025,7 +1139,7 @@
*/
buf = map_sysmem(rd_addr, 0);
switch (genimg_get_format(buf)) {
-#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
+#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
case IMAGE_FORMAT_LEGACY:
printf("## Loading init Ramdisk from Legacy "
"Image at %08lx ...\n", rd_addr);
diff --git a/common/init/board_init.c b/common/init/board_init.c
index 526fee3..e521069 100644
--- a/common/init/board_init.c
+++ b/common/init/board_init.c
@@ -18,6 +18,23 @@
}
#endif /* !CONFIG_X86 && !CONFIG_ARM */
+/**
+ * This function is called after the position of the initial stack is
+ * determined in gd->start_addr_sp. Boards can override it to set up
+ * stack-checking markers.
+ */
+__weak void board_init_f_init_stack_protection(void)
+{
+#if CONFIG_IS_ENABLED(SYS_REPORT_STACK_F_USAGE)
+ ulong stack_bottom = gd->start_addr_sp -
+ CONFIG_VAL(SIZE_LIMIT_PROVIDE_STACK);
+
+ /* substact some safety margin (0x20) since stack is in use here */
+ memset((void *)stack_bottom, CONFIG_VAL(SYS_STACK_F_CHECK_BYTE),
+ CONFIG_VAL(SIZE_LIMIT_PROVIDE_STACK) - 0x20);
+#endif
+}
+
/*
* Allocate reserved space for use as 'globals' from 'top' address and
* return 'bottom' address of allocated space
@@ -126,6 +143,9 @@
/* next alloc will be higher by one 'early malloc arena' size */
base += CONFIG_VAL(SYS_MALLOC_F_LEN);
#endif
+
+ if (CONFIG_IS_ENABLED(SYS_REPORT_STACK_F_USAGE))
+ board_init_f_init_stack_protection();
}
/*
diff --git a/common/main.c b/common/main.c
index 07b34bf..3a657c3 100644
--- a/common/main.c
+++ b/common/main.c
@@ -10,6 +10,7 @@
#include <autoboot.h>
#include <cli.h>
#include <console.h>
+#include <env.h>
#include <version.h>
/*
@@ -19,7 +20,6 @@
static void run_preboot_environment_command(void)
{
-#ifdef CONFIG_PREBOOT
char *p;
p = env_get("preboot");
@@ -34,7 +34,6 @@
if (IS_ENABLED(CONFIG_AUTOBOOT_KEYED))
disable_ctrlc(prev); /* restore Ctrl-C checking */
}
-#endif /* CONFIG_PREBOOT */
}
/* We come here after U-Boot is initialised and ready to process commands */
@@ -49,7 +48,8 @@
cli_init();
- run_preboot_environment_command();
+ if (IS_ENABLED(CONFIG_USE_PREBOOT))
+ run_preboot_environment_command();
if (IS_ENABLED(CONFIG_UPDATE_TFTP))
update_tftp(0UL, NULL, NULL);
diff --git a/common/menu.c b/common/menu.c
index 0f0a29a..7b66d19 100644
--- a/common/menu.c
+++ b/common/menu.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2010-2011 Calxeda, Inc.
+ * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
*/
#include <common.h>
@@ -39,6 +40,7 @@
char *(*item_choice)(void *);
void *item_choice_data;
struct list_head items;
+ int item_cnt;
};
/*
@@ -271,7 +273,7 @@
if (!m || !choice)
return -EINVAL;
- if (!m->prompt)
+ if (!m->prompt || m->item_cnt == 1)
return menu_default_choice(m, choice);
return menu_interactive_choice(m, choice);
@@ -323,6 +325,7 @@
item->data = item_data;
list_add_tail(&item->list, &m->items);
+ m->item_cnt++;
return 1;
}
@@ -374,6 +377,7 @@
m->item_data_print = item_data_print;
m->item_choice = item_choice;
m->item_choice_data = item_choice_data;
+ m->item_cnt = 0;
if (title) {
m->title = strdup(title);
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 142753f..f467eca 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -62,6 +62,25 @@
of SRAM available for SPL when the stack required before reolcation
uses this SRAM, too.
+config SPL_SYS_STACK_F_CHECK_BYTE
+ hex
+ default 0xaa
+ help
+ Constant used to check the stack
+
+config SPL_SYS_REPORT_STACK_F_USAGE
+ depends on SPL_SIZE_LIMIT_PROVIDE_STACK != 0
+ bool "Check and report stack usage in SPL before relocation"
+ help
+ If this option is enabled, the initial SPL stack is filled with 0xaa
+ very early, up to the size configured with
+ SPL_SIZE_LIMIT_PROVIDE_STACK.
+ Later when SPL is done using this initial stack and switches to a
+ stack in DRAM, the actually used size of this initial stack is
+ reported by examining the memory and searching for the lowest
+ occurrence of non 0xaa bytes.
+ This default implementation works for stacks growing down only.
+
menu "PowerPC SPL Boot options"
depends on PPC && (SUPPORT_SPL && !SPL_FRAMEWORK)
@@ -116,6 +135,9 @@
config SPL_TEXT_BASE
hex "SPL Text Base"
default ISW_ENTRY_ADDR if AM43XX || AM33XX || OMAP54XX || ARCH_KEYSTONE
+ default 0x10060 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN9I
+ default 0x20060 if MACH_SUN50I_H6
+ default 0x00060 if ARCH_SUNXI
default 0x0
help
The address in memory that SPL will be running from.
@@ -158,7 +180,7 @@
config SPL_LEGACY_IMAGE_SUPPORT
bool "Support SPL loading and booting of Legacy images"
- default y if !TI_SECURE_DEVICE
+ default y if !TI_SECURE_DEVICE && !SPL_LOAD_FIT
help
SPL will support loading and booting Legacy images when this option
is y. If this is not set, SPL will move on to other available
@@ -186,6 +208,7 @@
config TPL_SYS_MALLOC_SIMPLE
bool
prompt "Only use malloc_simple functions in the TPL"
+ depends on TPL
help
Say Y here to only use the *_simple malloc functions from
malloc_simple.c, rather then using the versions from dlmalloc.c;
@@ -239,12 +262,23 @@
config TPL_BANNER_PRINT
bool "Enable output of the TPL banner 'U-Boot TPL ...'"
+ depends on TPL
default y
help
If this option is enabled, SPL will not print the banner with version
info. Disabling this option could be useful to reduce SPL boot time
(e.g. approx. 6 ms faster, when output on i.MX6 with 115200 baud).
+config SPL_EARLY_BSS
+ depends on ARM && !ARM64
+ bool "Allows initializing BSS early before entering board_init_f"
+ help
+ On some platform we have sufficient memory available early on to
+ allow setting up and using a basic BSS prior to entering
+ board_init_f. Activating this option will also de-activate the
+ clearing of BSS during the SPL relocation process, thus allowing
+ to carry state from board_init_f to board_init_r by way of BSS.
+
config SPL_DISPLAY_PRINT
bool "Display a board-specific message in SPL"
help
@@ -401,6 +435,7 @@
config TPL_HASH_SUPPORT
bool "Support hashing drivers in TPL"
+ depends on TPL
select SHA1
select SHA256
help
@@ -572,6 +607,23 @@
this option to build the drivers in drivers/mmc as part of an SPL
build.
+config SPL_MMC_TINY
+ bool "Tiny MMC framework in SPL"
+ depends on SPL_MMC_SUPPORT
+ default n
+ help
+ Enable MMC framework tinification support. This option is useful if
+ if your SPL is extremely size constrained. Heed the warning, enable
+ this option if and only if you know exactly what you are doing, if
+ you are reading this help text, you most likely have no idea :-)
+
+ The MMC framework is reduced to bare minimum to be useful. No malloc
+ support is needed for the MMC framework operation with this option
+ enabled. The framework supports exactly one MMC device and exactly
+ one MMC driver. The MMC driver can be adjusted to avoid any malloc
+ operations too, which can remove the need for malloc support in SPL
+ and thus further reduce footprint.
+
config SPL_MMC_WRITE
bool "MMC/SD/SDIO card support for write operations in SPL"
depends on SPL_MMC_SUPPORT
@@ -613,6 +665,104 @@
This enables the drivers in drivers/mtd/nand/raw as part of an SPL
build.
+config SPL_UBI
+ bool "Support UBI"
+ help
+ Enable support for loading payloads from UBI. See
+ README.ubispl for more info.
+
+if SPL_UBI
+config SPL_UBI_LOAD_BY_VOLNAME
+ bool "Support loading volumes by name"
+ help
+ This enables support for loading UBI volumes by name. When this
+ is set, CONFIG_SPL_UBI_LOAD_MONITOR_VOLNAME can be used to
+ configure the volume name from which to load U-Boot.
+
+config SPL_UBI_MAX_VOL_LEBS
+ int "Maximum number of LEBs per volume"
+ depends on SPL_UBI
+ help
+ The maximum number of logical eraseblocks which a static volume
+ to load can contain. Used for sizing the scan data structure.
+
+config SPL_UBI_MAX_PEB_SIZE
+ int "Maximum PEB size"
+ depends on SPL_UBI
+ help
+ The maximum physical erase block size.
+
+config SPL_UBI_MAX_PEBS
+ int "Maximum number of PEBs"
+ depends on SPL_UBI
+ help
+ The maximum physical erase block size. If not overridden by
+ board code, this value will be used as the actual number of PEBs.
+
+config SPL_UBI_PEB_OFFSET
+ int "Offset to first UBI PEB"
+ depends on SPL_UBI
+ help
+ The offset in number of PEBs from the start of flash to the first
+ PEB part of the UBI image.
+
+config SPL_UBI_VID_OFFSET
+ int "Offset to VID header"
+ depends on SPL_UBI
+
+config SPL_UBI_LEB_START
+ int "Offset to LEB in PEB"
+ depends on SPL_UBI
+ help
+ The offset in bytes to the LEB within a PEB.
+
+config SPL_UBI_INFO_ADDR
+ hex "Address to place UBI scan info"
+ depends on SPL_UBI
+ help
+ Address for ubispl to place the scan info. Read README.ubispl to
+ determine the required size
+
+config SPL_UBI_VOL_IDS
+ int "Maximum volume id"
+ depends on SPL_UBI
+ help
+ The maximum volume id which can be loaded. Used for sizing the
+ scan data structure.
+
+config SPL_UBI_LOAD_MONITOR_ID
+ int "id of U-Boot volume"
+ depends on SPL_UBI
+ help
+ The UBI volume id from which to load U-Boot
+
+config SPL_UBI_LOAD_MONITOR_VOLNAME
+ string "volume name of U-Boot volume"
+ depends on SPL_UBI_LOAD_BY_VOLNAME
+ help
+ The UBI volume name from which to load U-Boot
+
+config SPL_UBI_LOAD_KERNEL_ID
+ int "id of kernel volume"
+ depends on SPL_OS_BOOT && SPL_UBI
+ help
+ The UBI volume id from which to load the kernel
+
+config SPL_UBI_LOAD_ARGS_ID
+ int "id of kernel args volume"
+ depends on SPL_OS_BOOT && SPL_UBI
+ help
+ The UBI volume id from which to load the device tree
+
+config UBI_SPL_SILENCE_MSG
+ bool "silence UBI SPL messages"
+ default n
+ help
+ Disable messages from UBI SPL. This leaves warnings
+ and errors enabled.
+
+endif # if SPL_UBI
+
config SPL_NET_SUPPORT
bool "Support networking"
help
@@ -790,6 +940,20 @@
expense and power consumption. This enables loading from SATA
using a configured device.
+config SPL_SATA_RAW_U_BOOT_USE_SECTOR
+ bool "SATA raw mode: by sector"
+ depends on SPL_SATA_SUPPORT
+ help
+ Use sector number for specifying U-Boot location on SATA disk in
+ raw mode.
+
+config SPL_SATA_RAW_U_BOOT_SECTOR
+ hex "Sector on the SATA disk to load U-Boot from"
+ depends on SPL_SATA_RAW_U_BOOT_USE_SECTOR
+ help
+ Sector on the SATA disk to load U-Boot from, when the SATA disk is being
+ used in raw mode. Units: SATA disk sectors (1 sector = 512 bytes).
+
config SPL_SERIAL_SUPPORT
bool "Support serial"
select SPL_PRINTF
@@ -839,6 +1003,14 @@
endif # SPL_SPI_FLASH_SUPPORT
+config SYS_SPI_U_BOOT_OFFS
+ hex "address of u-boot payload in SPI flash"
+ default 0x0
+ depends on SPL_SPI_LOAD || SPL_SPI_SUNXI
+ help
+ Address within SPI-Flash from where the u-boot payload is fetched
+ from.
+
config SPL_SPI_SUPPORT
bool "Support SPI drivers"
help
@@ -933,6 +1105,7 @@
config SPL_WATCHDOG_SUPPORT
bool "Support watchdog drivers"
+ imply SPL_WDT if !HW_WATCHDOG
help
Enable support for watchdog drivers in SPL. A watchdog is
typically a hardware peripheral which can reset the system when it
@@ -984,6 +1157,23 @@
OP-TEE is an open source Trusted OS which is loaded by SPL.
More detail at: https://github.com/OP-TEE/optee_os
+config SPL_OPENSBI
+ bool "Support RISC-V OpenSBI"
+ depends on RISCV && SPL_RISCV_MMODE && RISCV_SMODE
+ help
+ OpenSBI is an open-source implementation of the RISC-V Supervisor Binary
+ Interface (SBI) specification. U-Boot supports the OpenSBI FW_DYNAMIC
+ firmware. It is loaded and started by U-Boot SPL.
+
+ More details are available at https://github.com/riscv/opensbi and
+ https://github.com/riscv/riscv-sbi-doc
+
+config SPL_OPENSBI_LOAD_ADDR
+ hex "OpenSBI load address"
+ depends on SPL_OPENSBI
+ help
+ Load address of the OpenSBI binary.
+
config TPL
bool
depends on SUPPORT_TPL
diff --git a/common/spl/Makefile b/common/spl/Makefile
index d28de69..5ce6f4a 100644
--- a/common/spl/Makefile
+++ b/common/spl/Makefile
@@ -22,6 +22,7 @@
obj-$(CONFIG_$(SPL_TPL_)MMC_SUPPORT) += spl_mmc.o
obj-$(CONFIG_$(SPL_TPL_)ATF) += spl_atf.o
obj-$(CONFIG_$(SPL_TPL_)OPTEE) += spl_optee.o
+obj-$(CONFIG_$(SPL_TPL_)OPENSBI) += spl_opensbi.o
obj-$(CONFIG_$(SPL_TPL_)USB_STORAGE) += spl_usb.o
obj-$(CONFIG_$(SPL_TPL_)FS_FAT) += spl_fat.o
obj-$(CONFIG_$(SPL_TPL_)FS_EXT4) += spl_ext.o
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 4ddeff9..082fa2b 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -535,7 +535,7 @@
}
/**
- * boot_from_devices() - Try loading an booting U-Boot from a list of devices
+ * boot_from_devices() - Try loading a booting U-Boot from a list of devices
*
* @spl_image: Place to put the image details if successful
* @spl_boot_list: List of boot devices to try
@@ -603,7 +603,7 @@
spl_board_init();
#endif
-#if defined(CONFIG_SPL_WATCHDOG_SUPPORT) && defined(CONFIG_WDT)
+#if defined(CONFIG_SPL_WATCHDOG_SUPPORT) && CONFIG_IS_ENABLED(WDT)
initr_watchdog();
#endif
@@ -659,6 +659,12 @@
(void *)spl_image.entry_point);
break;
#endif
+#if CONFIG_IS_ENABLED(OPENSBI)
+ case IH_OS_OPENSBI:
+ debug("Jumping to U-Boot via RISC-V OpenSBI\n");
+ spl_invoke_opensbi(&spl_image);
+ break;
+#endif
#ifdef CONFIG_SPL_OS_BOOT
case IH_OS_LINUX:
debug("Jumping to Linux\n");
@@ -710,6 +716,28 @@
#endif
/**
+ * This function is called before the stack is changed from initial stack to
+ * relocated stack. It tries to dump the stack size used
+ */
+__weak void spl_relocate_stack_check(void)
+{
+#if CONFIG_IS_ENABLED(SYS_REPORT_STACK_F_USAGE)
+ ulong init_sp = gd->start_addr_sp;
+ ulong stack_bottom = init_sp - CONFIG_VAL(SIZE_LIMIT_PROVIDE_STACK);
+ u8 *ptr = (u8 *)stack_bottom;
+ ulong i;
+
+ for (i = 0; i < CONFIG_VAL(SIZE_LIMIT_PROVIDE_STACK); i++) {
+ if (*ptr != CONFIG_VAL(SYS_STACK_F_CHECK_BYTE))
+ break;
+ ptr++;
+ }
+ printf("SPL initial stack usage: %lu bytes\n",
+ CONFIG_VAL(SIZE_LIMIT_PROVIDE_STACK) - i);
+#endif
+}
+
+/**
* spl_relocate_stack_gd() - Relocate stack ready for board_init_r() execution
*
* Sometimes board_init_f() runs with a stack in SRAM but we want to use SDRAM
@@ -733,6 +761,9 @@
gd_t *new_gd;
ulong ptr = CONFIG_SPL_STACK_R_ADDR;
+ if (CONFIG_IS_ENABLED(SYS_REPORT_STACK_F_USAGE))
+ spl_relocate_stack_check();
+
#if defined(CONFIG_SPL_SYS_MALLOC_SIMPLE) && CONFIG_VAL(SYS_MALLOC_F_LEN)
if (CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN) {
debug("SPL malloc() before relocation used 0x%lx bytes (%ld KB)\n",
@@ -750,7 +781,7 @@
#if CONFIG_IS_ENABLED(DM)
dm_fixup_for_gd_move(new_gd);
#endif
-#if !defined(CONFIG_ARM)
+#if !defined(CONFIG_ARM) && !defined(CONFIG_RISCV)
gd = new_gd;
#endif
return ptr;
diff --git a/common/spl/spl_dfu.c b/common/spl/spl_dfu.c
index c0225dc..5728d43 100644
--- a/common/spl/spl_dfu.c
+++ b/common/spl/spl_dfu.c
@@ -6,6 +6,7 @@
* Ravi B <ravibabu@ti.com>
*/
#include <common.h>
+#include <env.h>
#include <spl.h>
#include <linux/compiler.h>
#include <errno.h>
@@ -14,7 +15,6 @@
#include <g_dnl.h>
#include <usb.h>
#include <dfu.h>
-#include <environment.h>
static int run_dfu(int usb_index, char *interface, char *devstring)
{
@@ -38,7 +38,7 @@
int ret;
/* set default environment */
- set_default_env(NULL, 0);
+ env_set_default(NULL, 0);
str_env = env_get(dfu_alt_info);
if (!str_env) {
pr_err("\"%s\" env variable not defined!\n", dfu_alt_info);
diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c
index fe05223..2a62522 100644
--- a/common/spl/spl_ext.c
+++ b/common/spl/spl_ext.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
#include <common.h>
+#include <env.h>
#include <spl.h>
#include <asm/u-boot.h>
#include <ext4fs.h>
diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c
index 163e540..aa371ab 100644
--- a/common/spl/spl_fat.c
+++ b/common/spl/spl_fat.c
@@ -9,6 +9,7 @@
*/
#include <common.h>
+#include <env.h>
#include <spl.h>
#include <asm/u-boot.h>
#include <fat.h>
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 87ecf0b..b3e3ccd 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -7,10 +7,13 @@
#include <common.h>
#include <errno.h>
#include <fpga.h>
+#include <gzip.h>
#include <image.h>
#include <linux/libfdt.h>
#include <spl.h>
+DECLARE_GLOBAL_DATA_PTR;
+
#ifndef CONFIG_SYS_BOOTM_LEN
#define CONFIG_SYS_BOOTM_LEN (64 << 20)
#endif
@@ -278,26 +281,35 @@
void *fit, int images, ulong base_offset)
{
struct spl_image_info image_info;
- int node, ret;
+ int node, ret = 0;
+
+ /*
+ * Use the address following the image as target address for the
+ * device tree.
+ */
+ image_info.load_addr = spl_image->load_addr + spl_image->size;
/* Figure out which device tree the board wants to use */
node = spl_fit_get_image_node(fit, images, FIT_FDT_PROP, 0);
if (node < 0) {
debug("%s: cannot find FDT node\n", __func__);
- return node;
+
+ /*
+ * U-Boot did not find a device tree inside the FIT image. Use
+ * the U-Boot device tree instead.
+ */
+ if (gd->fdt_blob)
+ memcpy((void *)image_info.load_addr, gd->fdt_blob,
+ fdt_totalsize(gd->fdt_blob));
+ else
+ return node;
+ } else {
+ ret = spl_load_fit_image(info, sector, fit, base_offset, node,
+ &image_info);
+ if (ret < 0)
+ return ret;
}
- /*
- * Read the device tree and place it after the image.
- * Align the destination address to ARCH_DMA_MINALIGN.
- */
- image_info.load_addr = spl_image->load_addr + spl_image->size;
- ret = spl_load_fit_image(info, sector, fit, base_offset, node,
- &image_info);
-
- if (ret < 0)
- return ret;
-
/* Make the load-address of the FDT available for the SPL framework */
spl_image->fdt_addr = (void *)image_info.load_addr;
#if !CONFIG_IS_ENABLED(FIT_IMAGE_TINY)
@@ -340,6 +352,16 @@
#endif
}
+/*
+ * Weak default function to allow customizing SPL fit loading for load-only
+ * use cases by allowing to skip the parsing/processing of the FIT contents
+ * (so that this can be done separately in a more customized fashion)
+ */
+__weak bool spl_load_simple_fit_skip_processing(void)
+{
+ return false;
+}
+
int spl_load_simple_fit(struct spl_image_info *spl_image,
struct spl_load_info *info, ulong sector, void *fit)
{
@@ -389,6 +411,10 @@
if (count == 0)
return -EIO;
+ /* skip further processing if requested to enable load-only use cases */
+ if (spl_load_simple_fit_skip_processing())
+ return 0;
+
/* find the node holding the images information */
images = fdt_path_offset(fit, FIT_IMAGES_PATH);
if (images < 0) {
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index 324d91c..b361988 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -151,7 +151,8 @@
#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
static int mmc_load_image_raw_partition(struct spl_image_info *spl_image,
- struct mmc *mmc, int partition)
+ struct mmc *mmc, int partition,
+ unsigned long sector)
{
disk_partition_t info;
int err;
@@ -180,8 +181,7 @@
}
#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
- return mmc_load_image_raw_sector(spl_image, mmc,
- info.start + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR);
+ return mmc_load_image_raw_sector(spl_image, mmc, info.start + sector);
#else
return mmc_load_image_raw_sector(spl_image, mmc, info.start);
#endif
@@ -234,7 +234,8 @@
#endif
#ifdef CONFIG_SYS_MMCSD_FS_BOOT_PARTITION
-static int spl_mmc_do_fs_boot(struct spl_image_info *spl_image, struct mmc *mmc)
+static int spl_mmc_do_fs_boot(struct spl_image_info *spl_image, struct mmc *mmc,
+ const char *filename)
{
int err = -ENOSYS;
@@ -248,7 +249,7 @@
#ifdef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
err = spl_load_image_fat(spl_image, mmc_get_blk_desc(mmc),
CONFIG_SYS_MMCSD_FS_BOOT_PARTITION,
- CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
+ filename);
if (!err)
return err;
#endif
@@ -263,7 +264,7 @@
#ifdef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
err = spl_load_image_ext(spl_image, mmc_get_blk_desc(mmc),
CONFIG_SYS_MMCSD_FS_BOOT_PARTITION,
- CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
+ filename);
if (!err)
return err;
#endif
@@ -276,7 +277,8 @@
return err;
}
#else
-static int spl_mmc_do_fs_boot(struct spl_image_info *spl_image, struct mmc *mmc)
+static int spl_mmc_do_fs_boot(struct spl_image_info *spl_image, struct mmc *mmc,
+ const char *filename)
{
return -ENOSYS;
}
@@ -301,24 +303,31 @@
}
#endif
-int spl_mmc_load_image(struct spl_image_info *spl_image,
- struct spl_boot_device *bootdev)
+int spl_mmc_load(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev,
+ const char *filename,
+ int raw_part,
+ unsigned long raw_sect)
{
- struct mmc *mmc = NULL;
+ static struct mmc *mmc;
u32 boot_mode;
int err = 0;
__maybe_unused int part;
- err = spl_mmc_find_device(&mmc, bootdev->boot_device);
- if (err)
- return err;
+ /* Perform peripheral init only once */
+ if (!mmc) {
+ err = spl_mmc_find_device(&mmc, bootdev->boot_device);
+ if (err)
+ return err;
- err = mmc_init(mmc);
- if (err) {
+ err = mmc_init(mmc);
+ if (err) {
+ mmc = NULL;
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
- printf("spl: mmc init failed with error: %d\n", err);
+ printf("spl: mmc init failed with error: %d\n", err);
#endif
- return err;
+ return err;
+ }
}
boot_mode = spl_boot_mode(bootdev->boot_device);
@@ -356,17 +365,13 @@
return err;
}
#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
- err = spl_boot_partition(bootdev->boot_device);
- if (!err)
- return err;
-
- err = mmc_load_image_raw_partition(spl_image, mmc, err);
+ err = mmc_load_image_raw_partition(spl_image, mmc, raw_part,
+ raw_sect);
if (!err)
return err;
#endif
#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
- err = mmc_load_image_raw_sector(spl_image, mmc,
- CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR);
+ err = mmc_load_image_raw_sector(spl_image, mmc, raw_sect);
if (!err)
return err;
#endif
@@ -374,7 +379,7 @@
case MMCSD_MODE_FS:
debug("spl: mmc boot mode: fs\n");
- err = spl_mmc_do_fs_boot(spl_image, mmc);
+ err = spl_mmc_do_fs_boot(spl_image, mmc, filename);
if (!err)
return err;
@@ -388,6 +393,27 @@
return err;
}
+int spl_mmc_load_image(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
+{
+ return spl_mmc_load(spl_image, bootdev,
+#ifdef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
+ CONFIG_SPL_FS_LOAD_PAYLOAD_NAME,
+#else
+ NULL,
+#endif
+#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
+ spl_boot_partition(bootdev->boot_device),
+#else
+ 0,
+#endif
+#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
+ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR);
+#else
+ 0);
+#endif
+}
+
SPL_LOAD_IMAGE_METHOD("MMC1", 0, BOOT_DEVICE_MMC1, spl_mmc_load_image);
SPL_LOAD_IMAGE_METHOD("MMC2", 0, BOOT_DEVICE_MMC2, spl_mmc_load_image);
SPL_LOAD_IMAGE_METHOD("MMC2_2", 0, BOOT_DEVICE_MMC2_2, spl_mmc_load_image);
diff --git a/common/spl/spl_net.c b/common/spl/spl_net.c
index c91ad2b..8033032 100644
--- a/common/spl/spl_net.c
+++ b/common/spl/spl_net.c
@@ -7,6 +7,7 @@
* Ilya Yanok <ilya.yanok@gmail.com>
*/
#include <common.h>
+#include <env.h>
#include <errno.h>
#include <spl.h>
#include <net.h>
diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c
new file mode 100644
index 0000000..a6b4480
--- /dev/null
+++ b/common/spl/spl_opensbi.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Fraunhofer AISEC,
+ * Lukas Auer <lukas.auer@aisec.fraunhofer.de>
+ *
+ * Based on common/spl/spl_atf.c
+ */
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/smp.h>
+#include <opensbi.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct fw_dynamic_info opensbi_info;
+
+static int spl_opensbi_find_uboot_node(void *blob, int *uboot_node)
+{
+ int fit_images_node, node;
+ const char *fit_os;
+
+ fit_images_node = fdt_path_offset(blob, "/fit-images");
+ if (fit_images_node < 0)
+ return -ENODEV;
+
+ fdt_for_each_subnode(node, blob, fit_images_node) {
+ fit_os = fdt_getprop(blob, node, FIT_OS_PROP, NULL);
+ if (!fit_os)
+ continue;
+
+ if (genimg_get_os_id(fit_os) == IH_OS_U_BOOT) {
+ *uboot_node = node;
+ return 0;
+ }
+ }
+
+ return -ENODEV;
+}
+
+void spl_invoke_opensbi(struct spl_image_info *spl_image)
+{
+ int ret, uboot_node;
+ ulong uboot_entry;
+ void (*opensbi_entry)(ulong hartid, ulong dtb, ulong info);
+
+ if (!spl_image->fdt_addr) {
+ pr_err("No device tree specified in SPL image\n");
+ hang();
+ }
+
+ /* Find U-Boot image in /fit-images */
+ ret = spl_opensbi_find_uboot_node(spl_image->fdt_addr, &uboot_node);
+ if (ret) {
+ pr_err("Can't find U-Boot node, %d", ret);
+ hang();
+ }
+
+ /* Get U-Boot entry point */
+ uboot_entry = fdt_getprop_u32(spl_image->fdt_addr, uboot_node,
+ "entry-point");
+ if (uboot_entry == FDT_ERROR)
+ uboot_entry = fdt_getprop_u32(spl_image->fdt_addr, uboot_node,
+ "load-addr");
+
+ /* Prepare obensbi_info object */
+ opensbi_info.magic = FW_DYNAMIC_INFO_MAGIC_VALUE;
+ opensbi_info.version = FW_DYNAMIC_INFO_VERSION;
+ opensbi_info.next_addr = uboot_entry;
+ opensbi_info.next_mode = FW_DYNAMIC_INFO_NEXT_MODE_S;
+ opensbi_info.options = SBI_SCRATCH_NO_BOOT_PRINTS;
+
+ opensbi_entry = (void (*)(ulong, ulong, ulong))spl_image->entry_point;
+ invalidate_icache_all();
+
+#ifdef CONFIG_SMP
+ ret = smp_call_function((ulong)spl_image->entry_point,
+ (ulong)spl_image->fdt_addr,
+ (ulong)&opensbi_info);
+ if (ret)
+ hang();
+#endif
+ opensbi_entry(gd->arch.boot_hart, (ulong)spl_image->fdt_addr,
+ (ulong)&opensbi_info);
+}
diff --git a/common/spl/spl_sata.c b/common/spl/spl_sata.c
index adfce1d..e108af0 100644
--- a/common/spl/spl_sata.c
+++ b/common/spl/spl_sata.c
@@ -17,13 +17,54 @@
#include <fat.h>
#include <image.h>
+#ifndef CONFIG_SYS_SATA_FAT_BOOT_PARTITION
+#define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1
+#endif
+
+#ifndef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
+#endif
+
+#ifndef CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR
+/* Dummy value to make the compiler happy */
+#define CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR 0x100
+#endif
+
+static int spl_sata_load_image_raw(struct spl_image_info *spl_image,
+ struct blk_desc *stor_dev, unsigned long sector)
+{
+ struct image_header *header;
+ unsigned long count;
+ u32 image_size_sectors;
+ int ret;
+
+ header = spl_get_load_buffer(-sizeof(*header), stor_dev->blksz);
+ count = blk_dread(stor_dev, sector, 1, header);
+ if (count == 0)
+ return -EIO;
+
+ ret = spl_parse_image_header(spl_image, header);
+ if (ret)
+ return ret;
+
+ image_size_sectors = DIV_ROUND_UP(spl_image->size, stor_dev->blksz);
+ count = blk_dread(stor_dev, sector, image_size_sectors,
+ (void *)spl_image->load_addr);
+ if (count != image_size_sectors)
+ return -EIO;
+
+ return 0;
+}
+
static int spl_sata_load_image(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
{
- int err;
+ int err = 0;
struct blk_desc *stor_dev;
+#if !defined(CONFIG_DM_SCSI) && !defined(CONFIG_AHCI)
err = init_sata(CONFIG_SPL_SATA_BOOT_DEVICE);
+#endif
if (err) {
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
printf("spl: sata init failed: err - %d\n", err);
@@ -43,9 +84,16 @@
CONFIG_SYS_SATA_FAT_BOOT_PARTITION))
#endif
{
- err = spl_load_image_fat(spl_image, stor_dev,
+ err = -ENOSYS;
+
+ if (IS_ENABLED(CONFIG_SPL_FS_FAT)) {
+ err = spl_load_image_fat(spl_image, stor_dev,
CONFIG_SYS_SATA_FAT_BOOT_PARTITION,
- CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
+ CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
+ } else if (IS_ENABLED(CONFIG_SPL_SATA_RAW_U_BOOT_USE_SECTOR)) {
+ err = spl_sata_load_image_raw(spl_image, stor_dev,
+ CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR);
+ }
}
if (err) {
puts("Error loading sata device\n");
diff --git a/common/spl/spl_ubi.c b/common/spl/spl_ubi.c
index 67e5fad..0cb5080 100644
--- a/common/spl/spl_ubi.c
+++ b/common/spl/spl_ubi.c
@@ -62,7 +62,14 @@
}
#endif
header = spl_get_load_buffer(-sizeof(*header), sizeof(header));
+#ifdef CONFIG_SPL_UBI_LOAD_BY_VOLNAME
+ volumes[0].vol_id = -1;
+ strncpy(volumes[0].name,
+ CONFIG_SPL_UBI_LOAD_MONITOR_VOLNAME,
+ UBI_VOL_NAME_MAX + 1);
+#else
volumes[0].vol_id = CONFIG_SPL_UBI_LOAD_MONITOR_ID;
+#endif
volumes[0].load_addr = (void *)header;
ret = ubispl_load_volumes(&info, volumes, 1);
diff --git a/common/spl/spl_ymodem.c b/common/spl/spl_ymodem.c
index fa539ec..20f4260 100644
--- a/common/spl/spl_ymodem.c
+++ b/common/spl/spl_ymodem.c
@@ -9,6 +9,7 @@
* Matt Porter <mporter@ti.com>
*/
#include <common.h>
+#include <gzip.h>
#include <spl.h>
#include <xyzModem.h>
#include <asm/u-boot.h>
diff --git a/common/splash.c b/common/splash.c
index 79d5057..0bcedbb 100644
--- a/common/splash.c
+++ b/common/splash.c
@@ -21,6 +21,7 @@
*/
#include <common.h>
+#include <env.h>
#include <splash.h>
#include <lcd.h>
@@ -51,10 +52,41 @@
},
};
+#if defined(CONFIG_DM_VIDEO) && defined(CONFIG_VIDEO_LOGO)
+
+#include <bmp_logo_data.h>
+
+static int splash_video_logo_load(void)
+{
+ char *splashimage;
+ u32 bmp_load_addr;
+
+ splashimage = env_get("splashimage");
+ if (!splashimage)
+ return -ENOENT;
+
+ bmp_load_addr = simple_strtoul(splashimage, 0, 16);
+ if (!bmp_load_addr) {
+ printf("Error: bad 'splashimage' address\n");
+ return -EFAULT;
+ }
+
+ memcpy((void *)bmp_load_addr, bmp_logo_bitmap,
+ ARRAY_SIZE(bmp_logo_bitmap));
+
+ return 0;
+}
+#else
+static inline int splash_video_logo_load(void) { return -ENOSYS; }
+#endif
+
__weak int splash_screen_prepare(void)
{
- return splash_source_load(default_splash_locations,
- ARRAY_SIZE(default_splash_locations));
+ if (CONFIG_IS_ENABLED(SPLASH_SOURCE))
+ return splash_source_load(default_splash_locations,
+ ARRAY_SIZE(default_splash_locations));
+
+ return splash_video_logo_load();
}
#ifdef CONFIG_SPLASH_SCREEN_ALIGN
@@ -80,6 +112,42 @@
}
#endif /* CONFIG_SPLASH_SCREEN_ALIGN */
+#if defined(CONFIG_DM_VIDEO) && !defined(CONFIG_HIDE_LOGO_VERSION)
+
+#ifdef CONFIG_VIDEO_LOGO
+#include <bmp_logo.h>
+#endif
+#include <dm.h>
+#include <video_console.h>
+#include <video_font.h>
+
+void splash_display_banner(void)
+{
+ struct udevice *dev;
+ char buf[DISPLAY_OPTIONS_BANNER_LENGTH];
+ int col, row, ret;
+
+ ret = uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &dev);
+ if (ret)
+ return;
+
+#ifdef CONFIG_VIDEO_LOGO
+ col = BMP_LOGO_WIDTH / VIDEO_FONT_WIDTH + 1;
+ row = BMP_LOGO_HEIGHT / VIDEO_FONT_HEIGHT + 1;
+#else
+ col = 0;
+ row = 0;
+#endif
+
+ display_options_get_banner(false, buf, sizeof(buf));
+ vidconsole_position_cursor(dev, col, 1);
+ vidconsole_put_string(dev, buf);
+ vidconsole_position_cursor(dev, 0, row);
+}
+#else
+static inline void splash_display_banner(void) { }
+#endif /* CONFIG_DM_VIDEO && !CONFIG_HIDE_LOGO_VERSION */
+
/*
* Common function to show a splash image if env("splashimage") is set.
* Is used for both dm_video and lcd video stacks. For additional
@@ -103,6 +171,14 @@
splash_get_pos(&x, &y);
- return bmp_display(addr, x, y);
+ ret = bmp_display(addr, x, y);
+
+ /* Skip banner output on video console if the logo is not at 0,0 */
+ if (x || y)
+ goto end;
+
+ splash_display_banner();
+end:
+ return ret;
}
#endif
diff --git a/common/splash_source.c b/common/splash_source.c
index 8f276a3..d37b4b3 100644
--- a/common/splash_source.c
+++ b/common/splash_source.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <bmp_layout.h>
+#include <env.h>
#include <errno.h>
#include <fs.h>
#include <fdt_support.h>
diff --git a/common/update.c b/common/update.c
index f237ea5..457b29f 100644
--- a/common/update.c
+++ b/common/update.c
@@ -17,6 +17,7 @@
#endif
#include <command.h>
+#include <env.h>
#include <flash.h>
#include <net.h>
#include <net/tftp.h>
diff --git a/common/usb.c b/common/usb.c
index b70f614..d9bcb5a 100644
--- a/common/usb.c
+++ b/common/usb.c
@@ -192,12 +192,15 @@
*/
/*
- * submits an Interrupt Message
+ * submits an Interrupt Message. Some drivers may implement non-blocking
+ * polling: when non-block is true and the device is not responding return
+ * -EAGAIN instead of waiting for device to respond.
*/
-int usb_submit_int_msg(struct usb_device *dev, unsigned long pipe,
- void *buffer, int transfer_len, int interval)
+int usb_int_msg(struct usb_device *dev, unsigned long pipe,
+ void *buffer, int transfer_len, int interval, bool nonblock)
{
- return submit_int_msg(dev, pipe, buffer, transfer_len, interval);
+ return submit_int_msg(dev, pipe, buffer, transfer_len, interval,
+ nonblock);
}
/*
diff --git a/common/usb_hub.c b/common/usb_hub.c
index 9069f4b..25c2ac4 100644
--- a/common/usb_hub.c
+++ b/common/usb_hub.c
@@ -24,6 +24,7 @@
#include <common.h>
#include <command.h>
#include <dm.h>
+#include <env.h>
#include <errno.h>
#include <memalign.h>
#include <asm/processor.h>
diff --git a/common/usb_kbd.c b/common/usb_kbd.c
index cc99c6b..d178af2 100644
--- a/common/usb_kbd.c
+++ b/common/usb_kbd.c
@@ -9,6 +9,7 @@
#include <common.h>
#include <console.h>
#include <dm.h>
+#include <env.h>
#include <errno.h>
#include <malloc.h>
#include <memalign.h>
@@ -339,10 +340,9 @@
struct usb_kbd_pdata *data = dev->privptr;
/* Submit a interrupt transfer request */
- usb_submit_int_msg(dev, data->intpipe, &data->new[0], data->intpktsize,
- data->intinterval);
-
- usb_kbd_irq_worker(dev);
+ if (usb_int_msg(dev, data->intpipe, &data->new[0],
+ data->intpktsize, data->intinterval, true) >= 0)
+ usb_kbd_irq_worker(dev);
#elif defined(CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP) || \
defined(CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE)
#if defined(CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP)
@@ -504,8 +504,8 @@
if (usb_get_report(dev, iface->desc.bInterfaceNumber,
1, 0, data->new, USB_KBD_BOOT_REPORT_SIZE) < 0) {
#else
- if (usb_submit_int_msg(dev, data->intpipe, data->new, data->intpktsize,
- data->intinterval) < 0) {
+ if (usb_int_msg(dev, data->intpipe, data->new, data->intpktsize,
+ data->intinterval, false) < 0) {
#endif
printf("Failed to get keyboard state from device %04x:%04x\n",
dev->descriptor.idVendor, dev->descriptor.idProduct);
diff --git a/common/usb_storage.c b/common/usb_storage.c
index 8c889bb..54f8e53 100644
--- a/common/usb_storage.c
+++ b/common/usb_storage.c
@@ -650,8 +650,8 @@
int timeout;
us->ip_wanted = 1;
- submit_int_msg(us->pusb_dev, us->irqpipe,
- (void *) &us->ip_data, us->irqmaxp, us->irqinterval);
+ usb_int_msg(us->pusb_dev, us->irqpipe,
+ (void *)&us->ip_data, us->irqmaxp, us->irqinterval, false);
timeout = 1000;
while (timeout--) {
if (us->ip_wanted == 0)
diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig
index 61b38b6..9eea922 100644
--- a/configs/A10-OLinuXino-Lime_defconfig
+++ b/configs/A10-OLinuXino-Lime_defconfig
@@ -11,7 +11,7 @@
CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/A10s-OLinuXino-M_defconfig b/configs/A10s-OLinuXino-M_defconfig
index 7cc8b83..d92a70e 100644
--- a/configs/A10s-OLinuXino-M_defconfig
+++ b/configs/A10s-OLinuXino-M_defconfig
@@ -9,7 +9,7 @@
CONFIG_MMC_SUNXI_SLOT_EXTRA=1
CONFIG_USB1_VBUS_PIN="PB10"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/A13-OLinuXinoM_defconfig b/configs/A13-OLinuXinoM_defconfig
index 1f8023e..da80d35 100644
--- a/configs/A13-OLinuXinoM_defconfig
+++ b/configs/A13-OLinuXinoM_defconfig
@@ -13,7 +13,7 @@
CONFIG_VIDEO_LCD_POWER="PB10"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig
index 0010d09..dfd439a 100644
--- a/configs/A13-OLinuXino_defconfig
+++ b/configs/A13-OLinuXino_defconfig
@@ -15,7 +15,7 @@
CONFIG_VIDEO_LCD_POWER="AXP0-0"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
index ed270f0..7e48328 100644
--- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig
+++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
@@ -13,8 +13,9 @@
CONFIG_SPL_SPI_SUNXI=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_USB_MASS_STORAGE=y
diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig
index ec702ce..084dab0 100644
--- a/configs/A20-OLinuXino-Lime2_defconfig
+++ b/configs/A20-OLinuXino-Lime2_defconfig
@@ -11,7 +11,7 @@
CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/A20-OLinuXino-Lime_defconfig b/configs/A20-OLinuXino-Lime_defconfig
index 87badd6..ffeeda4 100644
--- a/configs/A20-OLinuXino-Lime_defconfig
+++ b/configs/A20-OLinuXino-Lime_defconfig
@@ -9,7 +9,7 @@
CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/A20-OLinuXino_MICRO-eMMC_defconfig b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
index 39d3d7f..f4c6c54 100644
--- a/configs/A20-OLinuXino_MICRO-eMMC_defconfig
+++ b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
@@ -11,7 +11,7 @@
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig
index 3967303..440eebb 100644
--- a/configs/A20-OLinuXino_MICRO_defconfig
+++ b/configs/A20-OLinuXino_MICRO_defconfig
@@ -12,7 +12,7 @@
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig
index bad6911..48c4c3e 100644
--- a/configs/A20-Olimex-SOM-EVB_defconfig
+++ b/configs/A20-Olimex-SOM-EVB_defconfig
@@ -13,7 +13,7 @@
CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
index f343bb6..193e20a 100644
--- a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
+++ b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
@@ -13,7 +13,7 @@
CONFIG_GMAC_TX_DELAY=4
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/A20-Olimex-SOM204-EVB_defconfig b/configs/A20-Olimex-SOM204-EVB_defconfig
index 8f9d350..42a73c8 100644
--- a/configs/A20-Olimex-SOM204-EVB_defconfig
+++ b/configs/A20-Olimex-SOM204-EVB_defconfig
@@ -12,7 +12,7 @@
CONFIG_GMAC_TX_DELAY=4
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/A33-OLinuXino_defconfig b/configs/A33-OLinuXino_defconfig
index 893a5f2..6ea4238 100644
--- a/configs/A33-OLinuXino_defconfig
+++ b/configs/A33-OLinuXino_defconfig
@@ -16,7 +16,7 @@
CONFIG_VIDEO_LCD_BL_EN="PB2"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/Ainol_AW1_defconfig b/configs/Ainol_AW1_defconfig
index f2db707..9b7f197 100644
--- a/configs/Ainol_AW1_defconfig
+++ b/configs/Ainol_AW1_defconfig
@@ -14,7 +14,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Ampe_A76_defconfig b/configs/Ampe_A76_defconfig
index f1c3b2e..1810d48 100644
--- a/configs/Ampe_A76_defconfig
+++ b/configs/Ampe_A76_defconfig
@@ -15,7 +15,7 @@
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Auxtek-T003_defconfig b/configs/Auxtek-T003_defconfig
index 5d55ccf..2dc6c8d 100644
--- a/configs/Auxtek-T003_defconfig
+++ b/configs/Auxtek-T003_defconfig
@@ -8,7 +8,7 @@
CONFIG_USB1_VBUS_PIN="PB10"
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Auxtek-T004_defconfig b/configs/Auxtek-T004_defconfig
index be2a94a..4395d5b 100644
--- a/configs/Auxtek-T004_defconfig
+++ b/configs/Auxtek-T004_defconfig
@@ -6,7 +6,7 @@
CONFIG_DRAM_CLK=432
CONFIG_USB1_VBUS_PIN="PG13"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/B4420QDS_NAND_defconfig b/configs/B4420QDS_NAND_defconfig
index 2afce5e..863389e 100644
--- a/configs/B4420QDS_NAND_defconfig
+++ b/configs/B4420QDS_NAND_defconfig
@@ -7,6 +7,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_B4420QDS=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_FIT=y
@@ -20,7 +21,6 @@
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/B4860QDS_NAND_defconfig b/configs/B4860QDS_NAND_defconfig
index 8e0fb2b..b1922c1 100644
--- a/configs/B4860QDS_NAND_defconfig
+++ b/configs/B4860QDS_NAND_defconfig
@@ -7,6 +7,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_B4860QDS=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_FIT=y
@@ -20,7 +21,6 @@
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/BSC9131RDB_NAND_SYSCLK100_defconfig b/configs/BSC9131RDB_NAND_SYSCLK100_defconfig
index b221db1..e2c7cf3 100644
--- a/configs/BSC9131RDB_NAND_SYSCLK100_defconfig
+++ b/configs/BSC9131RDB_NAND_SYSCLK100_defconfig
@@ -4,6 +4,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9131RDB=y
+CONFIG_SPL_TEXT_BASE=0xFFFFE000
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_FIT=y
@@ -16,7 +17,6 @@
# CONFIG_MISC_INIT_R is not set
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xFFFFE000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/BSC9131RDB_NAND_defconfig b/configs/BSC9131RDB_NAND_defconfig
index 921c90f..cf715e5 100644
--- a/configs/BSC9131RDB_NAND_defconfig
+++ b/configs/BSC9131RDB_NAND_defconfig
@@ -4,6 +4,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9131RDB=y
+CONFIG_SPL_TEXT_BASE=0xFFFFE000
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_FIT=y
@@ -15,7 +16,6 @@
# CONFIG_MISC_INIT_R is not set
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xFFFFE000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/BSC9132QDS_NAND_DDRCLK100_defconfig b/configs/BSC9132QDS_NAND_DDRCLK100_defconfig
index a82544d..f0c9288 100644
--- a/configs/BSC9132QDS_NAND_DDRCLK100_defconfig
+++ b/configs/BSC9132QDS_NAND_DDRCLK100_defconfig
@@ -4,6 +4,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9132QDS=y
+CONFIG_SPL_TEXT_BASE=0xFFFFE000
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_FIT=y
@@ -16,7 +17,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xFFFFE000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
diff --git a/configs/BSC9132QDS_NAND_DDRCLK133_defconfig b/configs/BSC9132QDS_NAND_DDRCLK133_defconfig
index 0373372..3f29e82 100644
--- a/configs/BSC9132QDS_NAND_DDRCLK133_defconfig
+++ b/configs/BSC9132QDS_NAND_DDRCLK133_defconfig
@@ -4,6 +4,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9132QDS=y
+CONFIG_SPL_TEXT_BASE=0xFFFFE000
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_FIT=y
@@ -16,7 +17,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xFFFFE000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
diff --git a/configs/Bananapi_M2_Ultra_defconfig b/configs/Bananapi_M2_Ultra_defconfig
index 278e54f..40b6059 100644
--- a/configs/Bananapi_M2_Ultra_defconfig
+++ b/configs/Bananapi_M2_Ultra_defconfig
@@ -9,7 +9,7 @@
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
CONFIG_DEFAULT_DEVICE_TREE="sun8i-r40-bananapi-m2-ultra"
diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig
index 5be660a..abd7d3d 100644
--- a/configs/Bananapi_defconfig
+++ b/configs/Bananapi_defconfig
@@ -9,7 +9,7 @@
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Bananapi_m2m_defconfig b/configs/Bananapi_m2m_defconfig
index 7daaaa0..b4f3794 100644
--- a/configs/Bananapi_m2m_defconfig
+++ b/configs/Bananapi_m2m_defconfig
@@ -10,7 +10,7 @@
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB0_ID_DET="PH8"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_PARTITION_UUIDS is not set
diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig
index 5de48ae..c5d33a2 100644
--- a/configs/Bananapro_defconfig
+++ b/configs/Bananapro_defconfig
@@ -11,7 +11,7 @@
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/C29XPCIE_NAND_defconfig b/configs/C29XPCIE_NAND_defconfig
index 1a0666f..2a01b52 100644
--- a/configs/C29XPCIE_NAND_defconfig
+++ b/configs/C29XPCIE_NAND_defconfig
@@ -7,6 +7,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_C29XPCIE=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_FIT=y
@@ -18,7 +19,6 @@
# CONFIG_MISC_INIT_R is not set
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_TPL=y
CONFIG_TPL_ENV_SUPPORT=y
diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig
index f94de1f..7868108 100644
--- a/configs/CHIP_defconfig
+++ b/configs/CHIP_defconfig
@@ -6,7 +6,7 @@
CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y
CONFIG_USB0_VBUS_PIN="PB10"
CONFIG_VIDEO_COMPOSITE=y
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
diff --git a/configs/CHIP_pro_defconfig b/configs/CHIP_pro_defconfig
index 5fd7998..8299421 100644
--- a/configs/CHIP_pro_defconfig
+++ b/configs/CHIP_pro_defconfig
@@ -5,7 +5,7 @@
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y
CONFIG_USB0_VBUS_PIN="PB10"
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MTDPARTS=y
diff --git a/configs/CSQ_CS908_defconfig b/configs/CSQ_CS908_defconfig
index d5e9ae5..65b6777 100644
--- a/configs/CSQ_CS908_defconfig
+++ b/configs/CSQ_CS908_defconfig
@@ -7,7 +7,7 @@
CONFIG_USB1_VBUS_PIN=""
CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/Chuwi_V7_CW0825_defconfig b/configs/Chuwi_V7_CW0825_defconfig
index efe45c1..39caa75 100644
--- a/configs/Chuwi_V7_CW0825_defconfig
+++ b/configs/Chuwi_V7_CW0825_defconfig
@@ -14,7 +14,7 @@
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_VIDEO_LCD_PANEL_HITACHI_TX18D42VM=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig
index 64c7f81..9065792 100644
--- a/configs/Colombus_defconfig
+++ b/configs/Colombus_defconfig
@@ -17,7 +17,7 @@
CONFIG_VIDEO_LCD_PANEL_I2C_SCL="PA24"
CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig
index c9bc1a8..ee5412c 100644
--- a/configs/Cubieboard2_defconfig
+++ b/configs/Cubieboard2_defconfig
@@ -8,7 +8,7 @@
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Cubieboard4_defconfig b/configs/Cubieboard4_defconfig
index 2abbd33..e44d79e 100644
--- a/configs/Cubieboard4_defconfig
+++ b/configs/Cubieboard4_defconfig
@@ -12,7 +12,7 @@
CONFIG_USB1_VBUS_PIN="PH14"
CONFIG_USB3_VBUS_PIN="PH15"
CONFIG_AXP_GPIO=y
-CONFIG_SPL_TEXT_BASE=0x10060
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig
index 36b1a89..593dbe8 100644
--- a/configs/Cubieboard_defconfig
+++ b/configs/Cubieboard_defconfig
@@ -8,7 +8,7 @@
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig
index 6088549..fe92f64 100644
--- a/configs/Cubietruck_defconfig
+++ b/configs/Cubietruck_defconfig
@@ -13,7 +13,7 @@
CONFIG_GMAC_TX_DELAY=1
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/Cubietruck_plus_defconfig b/configs/Cubietruck_plus_defconfig
index ef6a9d5..9748805 100644
--- a/configs/Cubietruck_plus_defconfig
+++ b/configs/Cubietruck_plus_defconfig
@@ -15,8 +15,8 @@
CONFIG_I2C0_ENABLE=y
CONFIG_AXP_GPIO=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
-CONFIG_SPL_TEXT_BASE=0x60
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/Empire_electronix_d709_defconfig b/configs/Empire_electronix_d709_defconfig
index 07f32e2..ff6562d 100644
--- a/configs/Empire_electronix_d709_defconfig
+++ b/configs/Empire_electronix_d709_defconfig
@@ -16,7 +16,7 @@
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Empire_electronix_m712_defconfig b/configs/Empire_electronix_m712_defconfig
index 82a4a06..767d497 100644
--- a/configs/Empire_electronix_m712_defconfig
+++ b/configs/Empire_electronix_m712_defconfig
@@ -15,7 +15,7 @@
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Hummingbird_A31_defconfig b/configs/Hummingbird_A31_defconfig
index 6d8a9a3..44a6602 100644
--- a/configs/Hummingbird_A31_defconfig
+++ b/configs/Hummingbird_A31_defconfig
@@ -9,7 +9,7 @@
CONFIG_VIDEO_VGA_VIA_LCD=y
CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN="PH25"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/Hyundai_A7HD_defconfig b/configs/Hyundai_A7HD_defconfig
index 89ae241..0fe7c11 100644
--- a/configs/Hyundai_A7HD_defconfig
+++ b/configs/Hyundai_A7HD_defconfig
@@ -15,7 +15,7 @@
# CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW is not set
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Itead_Ibox_A20_defconfig b/configs/Itead_Ibox_A20_defconfig
index a5c7d62..01f259f 100644
--- a/configs/Itead_Ibox_A20_defconfig
+++ b/configs/Itead_Ibox_A20_defconfig
@@ -8,7 +8,7 @@
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Lamobo_R1_defconfig b/configs/Lamobo_R1_defconfig
index da8a835..974ff1c 100644
--- a/configs/Lamobo_R1_defconfig
+++ b/configs/Lamobo_R1_defconfig
@@ -10,7 +10,7 @@
CONFIG_GMAC_TX_DELAY=4
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/LicheePi_Zero_defconfig b/configs/LicheePi_Zero_defconfig
index e71f06b..ca0bcc0 100644
--- a/configs/LicheePi_Zero_defconfig
+++ b/configs/LicheePi_Zero_defconfig
@@ -4,7 +4,7 @@
CONFIG_SPL=y
CONFIG_MACH_SUN8I_V3S=y
CONFIG_DRAM_CLK=360
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/Linksprite_pcDuino3_Nano_defconfig b/configs/Linksprite_pcDuino3_Nano_defconfig
index 5fce2b1..23651ec 100644
--- a/configs/Linksprite_pcDuino3_Nano_defconfig
+++ b/configs/Linksprite_pcDuino3_Nano_defconfig
@@ -10,7 +10,7 @@
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig
index 1208237..6cb3663 100644
--- a/configs/Linksprite_pcDuino3_defconfig
+++ b/configs/Linksprite_pcDuino3_defconfig
@@ -8,7 +8,7 @@
CONFIG_SATAPWR="PH2"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Linksprite_pcDuino_defconfig b/configs/Linksprite_pcDuino_defconfig
index 7b73413..dd2b280 100644
--- a/configs/Linksprite_pcDuino_defconfig
+++ b/configs/Linksprite_pcDuino_defconfig
@@ -6,7 +6,7 @@
CONFIG_USB1_VBUS_PIN=""
CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/M5249EVB_defconfig b/configs/M5249EVB_defconfig
index c39818b..b93f127 100644
--- a/configs/M5249EVB_defconfig
+++ b/configs/M5249EVB_defconfig
@@ -7,6 +7,7 @@
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_IMLS=y
CONFIG_LOOPW=y
+CONFIG_MX_CYCLIC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_DEFAULT_DEVICE_TREE="M5249EVB"
diff --git a/configs/MK808C_defconfig b/configs/MK808C_defconfig
index 23da4da..7f23f9e 100644
--- a/configs/MK808C_defconfig
+++ b/configs/MK808C_defconfig
@@ -5,7 +5,7 @@
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig
index 48c1977..4c30f75 100644
--- a/configs/MPC8313ERDB_NAND_33_defconfig
+++ b/configs/MPC8313ERDB_NAND_33_defconfig
@@ -125,6 +125,7 @@
CONFIG_ACR_RPTCNT_4=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_4=y
+CONFIG_SPL_TEXT_BASE=0xFFF00000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ"
@@ -132,7 +133,6 @@
CONFIG_MISC_INIT_R=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_TEXT_BASE=0xFFF00000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig
index eee9227..1c7c72d 100644
--- a/configs/MPC8313ERDB_NAND_66_defconfig
+++ b/configs/MPC8313ERDB_NAND_66_defconfig
@@ -124,6 +124,7 @@
CONFIG_ACR_RPTCNT_4=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_4=y
+CONFIG_SPL_TEXT_BASE=0xFFF00000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ"
@@ -131,7 +132,6 @@
CONFIG_MISC_INIT_R=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_TEXT_BASE=0xFFF00000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
diff --git a/configs/MPC8349EMDS_PCI64_defconfig b/configs/MPC8349EMDS_PCI64_defconfig
index f99aaec..00dc72d 100644
--- a/configs/MPC8349EMDS_PCI64_defconfig
+++ b/configs/MPC8349EMDS_PCI64_defconfig
@@ -84,6 +84,8 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
diff --git a/configs/MPC8349EMDS_SLAVE_defconfig b/configs/MPC8349EMDS_SLAVE_defconfig
index 3a1268a..7550aa3 100644
--- a/configs/MPC8349EMDS_SLAVE_defconfig
+++ b/configs/MPC8349EMDS_SLAVE_defconfig
@@ -84,6 +84,8 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE"
CONFIG_BOOTDELAY=6
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig
index a446bb9..ba00a27 100644
--- a/configs/MPC8349EMDS_defconfig
+++ b/configs/MPC8349EMDS_defconfig
@@ -85,6 +85,8 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig
index 672dc78..1c37624 100644
--- a/configs/MPC8548CDS_36BIT_defconfig
+++ b/configs/MPC8548CDS_36BIT_defconfig
@@ -3,6 +3,7 @@
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_MPC8548CDS=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_PHYS_64BIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
@@ -16,6 +17,9 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
# CONFIG_CMD_HASH is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds_36b"
+CONFIG_DM=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
@@ -25,6 +29,8 @@
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig
index 09726d2..ef82aa8 100644
--- a/configs/MPC8548CDS_defconfig
+++ b/configs/MPC8548CDS_defconfig
@@ -3,6 +3,7 @@
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_MPC8548CDS=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
@@ -15,6 +16,9 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
# CONFIG_CMD_HASH is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds"
+CONFIG_DM=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
@@ -24,6 +28,8 @@
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig
index 4a2d11f..e36fcf8 100644
--- a/configs/MPC8548CDS_legacy_defconfig
+++ b/configs/MPC8548CDS_legacy_defconfig
@@ -3,6 +3,7 @@
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_MPC8548CDS=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="LEGACY"
@@ -15,6 +16,9 @@
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
# CONFIG_CMD_HASH is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds"
+CONFIG_DM=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
@@ -24,6 +28,8 @@
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/MSI_Primo73_defconfig b/configs/MSI_Primo73_defconfig
index e48e1a1..a4d137c 100644
--- a/configs/MSI_Primo73_defconfig
+++ b/configs/MSI_Primo73_defconfig
@@ -10,7 +10,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/MSI_Primo81_defconfig b/configs/MSI_Primo81_defconfig
index 1396784..12f8bd9 100644
--- a/configs/MSI_Primo81_defconfig
+++ b/configs/MSI_Primo81_defconfig
@@ -13,7 +13,7 @@
CONFIG_VIDEO_LCD_BL_PWM="PH13"
CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/Marsboard_A10_defconfig b/configs/Marsboard_A10_defconfig
index b0d0c35..d4cdcb7 100644
--- a/configs/Marsboard_A10_defconfig
+++ b/configs/Marsboard_A10_defconfig
@@ -5,7 +5,7 @@
CONFIG_MACH_SUN4I=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/Mele_A1000G_quad_defconfig b/configs/Mele_A1000G_quad_defconfig
index d321e94..08d8479 100644
--- a/configs/Mele_A1000G_quad_defconfig
+++ b/configs/Mele_A1000G_quad_defconfig
@@ -8,7 +8,7 @@
CONFIG_USB1_VBUS_PIN="PC27"
CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/Mele_A1000_defconfig b/configs/Mele_A1000_defconfig
index 672f4fe..d1cd98d 100644
--- a/configs/Mele_A1000_defconfig
+++ b/configs/Mele_A1000_defconfig
@@ -8,7 +8,7 @@
CONFIG_VIDEO_COMPOSITE=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Mele_I7_defconfig b/configs/Mele_I7_defconfig
index e1e628d..3b3b35d 100644
--- a/configs/Mele_I7_defconfig
+++ b/configs/Mele_I7_defconfig
@@ -7,7 +7,7 @@
CONFIG_USB1_VBUS_PIN="PC27"
CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/Mele_M3_defconfig b/configs/Mele_M3_defconfig
index c400f13..8f03d1e 100644
--- a/configs/Mele_M3_defconfig
+++ b/configs/Mele_M3_defconfig
@@ -9,7 +9,7 @@
CONFIG_VIDEO_VGA=y
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Mele_M5_defconfig b/configs/Mele_M5_defconfig
index f565dbc..d455a56 100644
--- a/configs/Mele_M5_defconfig
+++ b/configs/Mele_M5_defconfig
@@ -9,7 +9,7 @@
CONFIG_VIDEO_COMPOSITE=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig
index 7202bfd..9865e83 100644
--- a/configs/Mele_M9_defconfig
+++ b/configs/Mele_M9_defconfig
@@ -7,7 +7,7 @@
CONFIG_USB1_VBUS_PIN="PC27"
CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/Merrii_A80_Optimus_defconfig b/configs/Merrii_A80_Optimus_defconfig
index cc09533..b45b6cd 100644
--- a/configs/Merrii_A80_Optimus_defconfig
+++ b/configs/Merrii_A80_Optimus_defconfig
@@ -12,7 +12,7 @@
CONFIG_USB1_VBUS_PIN="PH4"
CONFIG_USB3_VBUS_PIN="PH5"
CONFIG_AXP_GPIO=y
-CONFIG_SPL_TEXT_BASE=0x10060
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/Mini-X_defconfig b/configs/Mini-X_defconfig
index 03fa81e..7d440d1 100644
--- a/configs/Mini-X_defconfig
+++ b/configs/Mini-X_defconfig
@@ -6,7 +6,7 @@
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Nintendo_NES_Classic_Edition_defconfig b/configs/Nintendo_NES_Classic_Edition_defconfig
index 099a2bd..2a75804 100644
--- a/configs/Nintendo_NES_Classic_Edition_defconfig
+++ b/configs/Nintendo_NES_Classic_Edition_defconfig
@@ -9,7 +9,7 @@
CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
CONFIG_AXP_GPIO=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MTDPARTS=y
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig
index b1a7cbd..1ff40a0 100644
--- a/configs/Orangepi_defconfig
+++ b/configs/Orangepi_defconfig
@@ -12,7 +12,7 @@
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig
index 35f1b34..af98dc8 100644
--- a/configs/Orangepi_mini_defconfig
+++ b/configs/Orangepi_mini_defconfig
@@ -14,7 +14,7 @@
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig
index f8effe8..99c7288 100644
--- a/configs/P1010RDB-PA_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig
@@ -7,6 +7,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_PHYS_64BIT=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
@@ -20,7 +21,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_TPL=y
CONFIG_TPL_DRIVERS_MISC_SUPPORT=y
diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
index 5fea3ed..73c22ef 100644
--- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
+CONFIG_SPL_TEXT_BASE=0xD0001000
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -20,7 +21,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xD0001000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
index 73bcdc1..d5a2ffa 100644
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
@@ -9,6 +9,7 @@
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
+CONFIG_SPL_TEXT_BASE=0xD0001000
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -21,7 +22,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xD0001000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig
index 0b8b67a..c2b9af5 100644
--- a/configs/P1010RDB-PA_NAND_defconfig
+++ b/configs/P1010RDB-PA_NAND_defconfig
@@ -7,6 +7,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_FIT=y
@@ -19,7 +20,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_TPL=y
CONFIG_TPL_DRIVERS_MISC_SUPPORT=y
diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig
index 3e4088b..628f900 100644
--- a/configs/P1010RDB-PA_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_SDCARD_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
+CONFIG_SPL_TEXT_BASE=0xD0001000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -19,7 +20,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xD0001000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig
index adc4da1..f14051b 100644
--- a/configs/P1010RDB-PA_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_SPIFLASH_defconfig
@@ -9,6 +9,7 @@
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
+CONFIG_SPL_TEXT_BASE=0xD0001000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -20,7 +21,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xD0001000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig
index a6ff616..b2ffe4a 100644
--- a/configs/P1010RDB-PB_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig
@@ -7,6 +7,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_PHYS_64BIT=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
@@ -20,7 +21,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_TPL=y
CONFIG_TPL_DRIVERS_MISC_SUPPORT=y
diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
index 9b8a1e2..e73cc4c 100644
--- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
+CONFIG_SPL_TEXT_BASE=0xD0001000
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -20,7 +21,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xD0001000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
index 0f10bf9..754355b 100644
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
@@ -9,6 +9,7 @@
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
+CONFIG_SPL_TEXT_BASE=0xD0001000
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -21,7 +22,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xD0001000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig
index bc8dce2..b35bf6d 100644
--- a/configs/P1010RDB-PB_NAND_defconfig
+++ b/configs/P1010RDB-PB_NAND_defconfig
@@ -7,6 +7,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_FIT=y
@@ -19,7 +20,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_TPL=y
CONFIG_TPL_DRIVERS_MISC_SUPPORT=y
diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig
index 9441988..afdb173 100644
--- a/configs/P1010RDB-PB_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_SDCARD_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
+CONFIG_SPL_TEXT_BASE=0xD0001000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -19,7 +20,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xD0001000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig
index b8695ec..1e0a28b 100644
--- a/configs/P1010RDB-PB_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_SPIFLASH_defconfig
@@ -9,6 +9,7 @@
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
+CONFIG_SPL_TEXT_BASE=0xD0001000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -20,7 +21,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xD0001000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig
index bb21c60..9ddcb43 100644
--- a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig
@@ -8,6 +8,7 @@
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020MBG=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -20,7 +21,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/P1020MBG-PC_SDCARD_defconfig b/configs/P1020MBG-PC_SDCARD_defconfig
index 4b9ec4d..df5fa991 100644
--- a/configs/P1020MBG-PC_SDCARD_defconfig
+++ b/configs/P1020MBG-PC_SDCARD_defconfig
@@ -8,6 +8,7 @@
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020MBG=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -19,7 +20,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig
index e4c565e..ba4229e 100644
--- a/configs/P1020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig
@@ -7,6 +7,7 @@
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_PHYS_64BIT=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
@@ -20,7 +21,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_TPL=y
CONFIG_TPL_ENV_SUPPORT=y
@@ -42,7 +42,10 @@
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b"
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
@@ -58,9 +61,11 @@
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
index 0d92bb2..883c4d9 100644
--- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
@@ -8,6 +8,7 @@
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -20,7 +21,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
@@ -38,7 +38,10 @@
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b"
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
@@ -53,9 +56,11 @@
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
index 95000db..4ec953a 100644
--- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -9,6 +9,7 @@
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -21,7 +22,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
@@ -39,7 +39,10 @@
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b"
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
@@ -54,9 +57,11 @@
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig
index 8ada9bb..9ce12c5 100644
--- a/configs/P1020RDB-PC_36BIT_defconfig
+++ b/configs/P1020RDB-PC_36BIT_defconfig
@@ -3,6 +3,7 @@
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -26,7 +27,10 @@
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b"
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
@@ -41,9 +45,11 @@
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig
index 2ea2f00..705bc71 100644
--- a/configs/P1020RDB-PC_NAND_defconfig
+++ b/configs/P1020RDB-PC_NAND_defconfig
@@ -7,6 +7,7 @@
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_FIT=y
@@ -19,7 +20,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_TPL=y
CONFIG_TPL_ENV_SUPPORT=y
@@ -41,7 +41,10 @@
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
@@ -57,9 +60,11 @@
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig
index a139fe8..e7407aa 100644
--- a/configs/P1020RDB-PC_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_SDCARD_defconfig
@@ -8,6 +8,7 @@
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -19,7 +20,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
@@ -37,7 +37,10 @@
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
@@ -52,9 +55,11 @@
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig
index 8b46b08..99457cb 100644
--- a/configs/P1020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_SPIFLASH_defconfig
@@ -9,6 +9,7 @@
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -20,7 +21,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
@@ -38,7 +38,10 @@
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
@@ -53,9 +56,11 @@
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig
index dec97c4..9158fef 100644
--- a/configs/P1020RDB-PC_defconfig
+++ b/configs/P1020RDB-PC_defconfig
@@ -3,6 +3,7 @@
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -25,7 +26,10 @@
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
@@ -40,9 +44,11 @@
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig
index 0327e5a..835cbd8 100644
--- a/configs/P1020RDB-PD_NAND_defconfig
+++ b/configs/P1020RDB-PD_NAND_defconfig
@@ -7,6 +7,7 @@
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PD=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_FIT=y
@@ -19,7 +20,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_TPL=y
CONFIG_TPL_ENV_SUPPORT=y
@@ -44,7 +44,10 @@
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=ec000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ec000000.nor:128k(dtb),6016k(kernel),57088k(fs),1m(vsc7385-firmware),1280k(u-boot)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
@@ -61,9 +64,11 @@
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig
index 49d8fc7..a07c46d 100644
--- a/configs/P1020RDB-PD_SDCARD_defconfig
+++ b/configs/P1020RDB-PD_SDCARD_defconfig
@@ -8,6 +8,7 @@
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PD=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -19,7 +20,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
@@ -40,7 +40,10 @@
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=ec000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ec000000.nor:128k(dtb),6016k(kernel),57088k(fs),1m(vsc7385-firmware),1280k(u-boot)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
@@ -56,9 +59,11 @@
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig
index 28a2c40..591c4ebf 100644
--- a/configs/P1020RDB-PD_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PD_SPIFLASH_defconfig
@@ -9,6 +9,7 @@
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PD=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -20,7 +21,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
@@ -41,7 +41,10 @@
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=ec000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ec000000.nor:128k(dtb),6016k(kernel),57088k(fs),1m(vsc7385-firmware),1280k(u-boot)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
@@ -57,9 +60,11 @@
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig
index 0f25faf..a29f811 100644
--- a/configs/P1020RDB-PD_defconfig
+++ b/configs/P1020RDB-PD_defconfig
@@ -3,6 +3,7 @@
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PD=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -28,7 +29,10 @@
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=ec000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ec000000.nor:128k(dtb),6016k(kernel),57088k(fs),1m(vsc7385-firmware),1280k(u-boot)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
@@ -44,9 +48,11 @@
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig
index 04aa24d..c0ce9ed 100644
--- a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig
@@ -8,6 +8,7 @@
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020UTM=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -20,7 +21,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/P1020UTM-PC_SDCARD_defconfig b/configs/P1020UTM-PC_SDCARD_defconfig
index 571889a..537e7b6 100644
--- a/configs/P1020UTM-PC_SDCARD_defconfig
+++ b/configs/P1020UTM-PC_SDCARD_defconfig
@@ -8,6 +8,7 @@
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020UTM=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -19,7 +20,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/P1021RDB-PC_36BIT_NAND_defconfig b/configs/P1021RDB-PC_36BIT_NAND_defconfig
index cd73bdd..b52ae95 100644
--- a/configs/P1021RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1021RDB-PC_36BIT_NAND_defconfig
@@ -7,6 +7,7 @@
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1021RDB=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_PHYS_64BIT=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
@@ -20,7 +21,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_TPL=y
CONFIG_TPL_ENV_SUPPORT=y
diff --git a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig
index d30d4df..18f326c 100644
--- a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig
@@ -8,6 +8,7 @@
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1021RDB=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -20,7 +21,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
index e11be02..6f5ff78 100644
--- a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
@@ -9,6 +9,7 @@
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1021RDB=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -21,7 +22,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/P1021RDB-PC_NAND_defconfig b/configs/P1021RDB-PC_NAND_defconfig
index ada720a..ee88894 100644
--- a/configs/P1021RDB-PC_NAND_defconfig
+++ b/configs/P1021RDB-PC_NAND_defconfig
@@ -7,6 +7,7 @@
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1021RDB=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_FIT=y
@@ -19,7 +20,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_TPL=y
CONFIG_TPL_ENV_SUPPORT=y
diff --git a/configs/P1021RDB-PC_SDCARD_defconfig b/configs/P1021RDB-PC_SDCARD_defconfig
index 28830f9..c7f4306 100644
--- a/configs/P1021RDB-PC_SDCARD_defconfig
+++ b/configs/P1021RDB-PC_SDCARD_defconfig
@@ -8,6 +8,7 @@
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1021RDB=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -19,7 +20,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/P1021RDB-PC_SPIFLASH_defconfig b/configs/P1021RDB-PC_SPIFLASH_defconfig
index 19d2b0f..2832638 100644
--- a/configs/P1021RDB-PC_SPIFLASH_defconfig
+++ b/configs/P1021RDB-PC_SPIFLASH_defconfig
@@ -9,6 +9,7 @@
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1021RDB=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -20,7 +21,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/P1022DS_36BIT_NAND_defconfig b/configs/P1022DS_36BIT_NAND_defconfig
index 62072dc..d69e527 100644
--- a/configs/P1022DS_36BIT_NAND_defconfig
+++ b/configs/P1022DS_36BIT_NAND_defconfig
@@ -6,6 +6,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1022DS=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_PHYS_64BIT=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
@@ -18,7 +19,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_TPL=y
CONFIG_TPL_ENV_SUPPORT=y
diff --git a/configs/P1022DS_36BIT_SDCARD_defconfig b/configs/P1022DS_36BIT_SDCARD_defconfig
index aadc417..9d45489 100644
--- a/configs/P1022DS_36BIT_SDCARD_defconfig
+++ b/configs/P1022DS_36BIT_SDCARD_defconfig
@@ -7,6 +7,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1022DS=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -18,7 +19,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/P1022DS_36BIT_SPIFLASH_defconfig b/configs/P1022DS_36BIT_SPIFLASH_defconfig
index e5b7cff..2eea528 100644
--- a/configs/P1022DS_36BIT_SPIFLASH_defconfig
+++ b/configs/P1022DS_36BIT_SPIFLASH_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1022DS=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -19,7 +20,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/P1022DS_NAND_defconfig b/configs/P1022DS_NAND_defconfig
index 8089012..92b95c0 100644
--- a/configs/P1022DS_NAND_defconfig
+++ b/configs/P1022DS_NAND_defconfig
@@ -6,6 +6,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1022DS=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_FIT=y
@@ -17,7 +18,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_TPL=y
CONFIG_TPL_ENV_SUPPORT=y
diff --git a/configs/P1022DS_SDCARD_defconfig b/configs/P1022DS_SDCARD_defconfig
index 71e0daa..daee4dd 100644
--- a/configs/P1022DS_SDCARD_defconfig
+++ b/configs/P1022DS_SDCARD_defconfig
@@ -7,6 +7,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1022DS=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -17,7 +18,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/P1022DS_SPIFLASH_defconfig b/configs/P1022DS_SPIFLASH_defconfig
index 7696298..ce522f5 100644
--- a/configs/P1022DS_SPIFLASH_defconfig
+++ b/configs/P1022DS_SPIFLASH_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1022DS=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -18,7 +19,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/P1024RDB_NAND_defconfig b/configs/P1024RDB_NAND_defconfig
index a08f5d9..f1c9d3d 100644
--- a/configs/P1024RDB_NAND_defconfig
+++ b/configs/P1024RDB_NAND_defconfig
@@ -7,6 +7,7 @@
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1024RDB=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_FIT=y
@@ -19,7 +20,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_TPL=y
CONFIG_TPL_ENV_SUPPORT=y
diff --git a/configs/P1024RDB_SDCARD_defconfig b/configs/P1024RDB_SDCARD_defconfig
index d09e71d..5f0c4b2 100644
--- a/configs/P1024RDB_SDCARD_defconfig
+++ b/configs/P1024RDB_SDCARD_defconfig
@@ -8,6 +8,7 @@
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1024RDB=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -19,7 +20,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/P1024RDB_SPIFLASH_defconfig b/configs/P1024RDB_SPIFLASH_defconfig
index da09d21..fe052b2 100644
--- a/configs/P1024RDB_SPIFLASH_defconfig
+++ b/configs/P1024RDB_SPIFLASH_defconfig
@@ -9,6 +9,7 @@
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1024RDB=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -20,7 +21,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/P1025RDB_NAND_defconfig b/configs/P1025RDB_NAND_defconfig
index 5259a2f..af5012b 100644
--- a/configs/P1025RDB_NAND_defconfig
+++ b/configs/P1025RDB_NAND_defconfig
@@ -7,6 +7,7 @@
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1025RDB=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_FIT=y
@@ -19,7 +20,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_TPL=y
CONFIG_TPL_ENV_SUPPORT=y
diff --git a/configs/P1025RDB_SDCARD_defconfig b/configs/P1025RDB_SDCARD_defconfig
index 485750c9..35fc471 100644
--- a/configs/P1025RDB_SDCARD_defconfig
+++ b/configs/P1025RDB_SDCARD_defconfig
@@ -8,6 +8,7 @@
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1025RDB=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -19,7 +20,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/P1025RDB_SPIFLASH_defconfig b/configs/P1025RDB_SPIFLASH_defconfig
index af6c7b4..f05d73e 100644
--- a/configs/P1025RDB_SPIFLASH_defconfig
+++ b/configs/P1025RDB_SPIFLASH_defconfig
@@ -9,6 +9,7 @@
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1025RDB=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -20,7 +21,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig
index 10c27e9..aa47e89 100644
--- a/configs/P2020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig
@@ -7,6 +7,7 @@
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_PHYS_64BIT=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
@@ -20,7 +21,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_TPL=y
CONFIG_TPL_ENV_SUPPORT=y
@@ -46,7 +46,10 @@
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=fef000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
@@ -63,9 +66,11 @@
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
index c0f3774..96ea15f 100644
--- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
@@ -8,6 +8,7 @@
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -20,7 +21,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
@@ -42,7 +42,10 @@
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=fef000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
@@ -58,9 +61,11 @@
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
index 160878f..d0103b2 100644
--- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -9,6 +9,7 @@
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -21,7 +22,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
@@ -43,7 +43,10 @@
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=fef000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
@@ -59,9 +62,11 @@
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig
index a9c21fb..c99c25f 100644
--- a/configs/P2020RDB-PC_36BIT_defconfig
+++ b/configs/P2020RDB-PC_36BIT_defconfig
@@ -3,6 +3,7 @@
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -30,7 +31,10 @@
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=fef000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
@@ -46,9 +50,11 @@
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig
index 8938503..ee13ac2 100644
--- a/configs/P2020RDB-PC_NAND_defconfig
+++ b/configs/P2020RDB-PC_NAND_defconfig
@@ -7,6 +7,7 @@
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_FIT=y
@@ -19,7 +20,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_TPL=y
CONFIG_TPL_ENV_SUPPORT=y
@@ -45,7 +45,10 @@
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=ef000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
@@ -62,9 +65,11 @@
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig
index b2b7841..7c43b95 100644
--- a/configs/P2020RDB-PC_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_SDCARD_defconfig
@@ -8,6 +8,7 @@
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -19,7 +20,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
@@ -41,7 +41,10 @@
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=ef000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
@@ -57,9 +60,11 @@
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig
index aeff863..cddef3e 100644
--- a/configs/P2020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_SPIFLASH_defconfig
@@ -9,6 +9,7 @@
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
+CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -20,7 +21,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
@@ -42,7 +42,10 @@
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=ef000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
@@ -58,9 +61,11 @@
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig
index 706a27d..a0a69ca 100644
--- a/configs/P2020RDB-PC_defconfig
+++ b/configs/P2020RDB-PC_defconfig
@@ -3,6 +3,7 @@
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -29,7 +30,10 @@
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=ef000000.nor"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
@@ -45,9 +49,11 @@
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig
index e42fac3..7ed8abf 100644
--- a/configs/P2041RDB_NAND_defconfig
+++ b/configs/P2041RDB_NAND_defconfig
@@ -2,6 +2,7 @@
CONFIG_SYS_TEXT_BASE=0xFFF40000
CONFIG_MPC85xx=y
CONFIG_TARGET_P2041RDB=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -23,7 +24,10 @@
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
@@ -40,10 +44,12 @@
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig
index c339f1b..4d64d08 100644
--- a/configs/P2041RDB_SDCARD_defconfig
+++ b/configs/P2041RDB_SDCARD_defconfig
@@ -2,6 +2,7 @@
CONFIG_SYS_TEXT_BASE=0xFFF40000
CONFIG_MPC85xx=y
CONFIG_TARGET_P2041RDB=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -23,7 +24,10 @@
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
@@ -39,10 +43,12 @@
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig
index f164b1f..ec22c95 100644
--- a/configs/P2041RDB_SPIFLASH_defconfig
+++ b/configs/P2041RDB_SPIFLASH_defconfig
@@ -2,6 +2,7 @@
CONFIG_SYS_TEXT_BASE=0xFFF40000
CONFIG_MPC85xx=y
CONFIG_TARGET_P2041RDB=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -23,7 +24,10 @@
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
@@ -39,10 +43,12 @@
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig
index f322c93..e757330 100644
--- a/configs/P2041RDB_defconfig
+++ b/configs/P2041RDB_defconfig
@@ -2,6 +2,7 @@
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_MPC85xx=y
CONFIG_TARGET_P2041RDB=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -22,7 +23,10 @@
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
@@ -38,10 +42,12 @@
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig
index 6a31ce9..0bdd2ab 100644
--- a/configs/P3041DS_NAND_defconfig
+++ b/configs/P3041DS_NAND_defconfig
@@ -2,6 +2,7 @@
CONFIG_SYS_TEXT_BASE=0xFFF40000
CONFIG_MPC85xx=y
CONFIG_TARGET_P3041DS=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -23,7 +24,10 @@
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p3041ds"
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
@@ -40,10 +44,12 @@
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig
index c6b2291..4d76efd 100644
--- a/configs/P3041DS_SDCARD_defconfig
+++ b/configs/P3041DS_SDCARD_defconfig
@@ -2,6 +2,7 @@
CONFIG_SYS_TEXT_BASE=0xFFF40000
CONFIG_MPC85xx=y
CONFIG_TARGET_P3041DS=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -23,7 +24,10 @@
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p3041ds"
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
@@ -39,10 +43,12 @@
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig
index 0aebf86..8b5e13d 100644
--- a/configs/P3041DS_SPIFLASH_defconfig
+++ b/configs/P3041DS_SPIFLASH_defconfig
@@ -2,6 +2,7 @@
CONFIG_SYS_TEXT_BASE=0xFFF40000
CONFIG_MPC85xx=y
CONFIG_TARGET_P3041DS=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -23,7 +24,10 @@
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p3041ds"
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
@@ -39,10 +43,12 @@
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig
index a44c1b4..96297df 100644
--- a/configs/P3041DS_defconfig
+++ b/configs/P3041DS_defconfig
@@ -2,6 +2,7 @@
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_MPC85xx=y
CONFIG_TARGET_P3041DS=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -22,7 +23,10 @@
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p3041ds"
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
@@ -38,10 +42,12 @@
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig
index 36884a8..b412e4f 100644
--- a/configs/P4080DS_SDCARD_defconfig
+++ b/configs/P4080DS_SDCARD_defconfig
@@ -2,6 +2,7 @@
CONFIG_SYS_TEXT_BASE=0xFFF40000
CONFIG_MPC85xx=y
CONFIG_TARGET_P4080DS=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -23,7 +24,10 @@
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p4080ds"
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
@@ -39,10 +43,12 @@
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig
index 5155657..e5e0eb2 100644
--- a/configs/P4080DS_SPIFLASH_defconfig
+++ b/configs/P4080DS_SPIFLASH_defconfig
@@ -2,6 +2,7 @@
CONFIG_SYS_TEXT_BASE=0xFFF40000
CONFIG_MPC85xx=y
CONFIG_TARGET_P4080DS=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -23,7 +24,10 @@
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p4080ds"
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
@@ -39,10 +43,12 @@
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig
index 995248d..a9a90e4 100644
--- a/configs/P4080DS_defconfig
+++ b/configs/P4080DS_defconfig
@@ -2,6 +2,7 @@
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_MPC85xx=y
CONFIG_TARGET_P4080DS=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -22,7 +23,10 @@
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p4080ds"
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
@@ -38,10 +42,12 @@
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig
index 5368f40..47a230c 100644
--- a/configs/P5040DS_NAND_defconfig
+++ b/configs/P5040DS_NAND_defconfig
@@ -2,6 +2,7 @@
CONFIG_SYS_TEXT_BASE=0xFFF40000
CONFIG_MPC85xx=y
CONFIG_TARGET_P5040DS=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -24,7 +25,10 @@
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p5040ds"
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
@@ -41,10 +45,12 @@
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig
index f1aa187..719c8b4 100644
--- a/configs/P5040DS_SDCARD_defconfig
+++ b/configs/P5040DS_SDCARD_defconfig
@@ -2,6 +2,7 @@
CONFIG_SYS_TEXT_BASE=0xFFF40000
CONFIG_MPC85xx=y
CONFIG_TARGET_P5040DS=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -24,7 +25,10 @@
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p5040ds"
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
@@ -40,10 +44,12 @@
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig
index 7f31813..3912dc9 100644
--- a/configs/P5040DS_SPIFLASH_defconfig
+++ b/configs/P5040DS_SPIFLASH_defconfig
@@ -2,6 +2,7 @@
CONFIG_SYS_TEXT_BASE=0xFFF40000
CONFIG_MPC85xx=y
CONFIG_TARGET_P5040DS=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -24,7 +25,10 @@
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p5040ds"
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
@@ -40,10 +44,12 @@
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig
index 40d04e9..f922521 100644
--- a/configs/P5040DS_defconfig
+++ b/configs/P5040DS_defconfig
@@ -2,6 +2,7 @@
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_MPC85xx=y
CONFIG_TARGET_P5040DS=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -23,7 +24,10 @@
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="p5040ds"
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
@@ -39,10 +43,12 @@
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/SBx81LIFKW_defconfig b/configs/SBx81LIFKW_defconfig
index 8cb397c..db843db 100644
--- a/configs/SBx81LIFKW_defconfig
+++ b/configs/SBx81LIFKW_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x00600000
CONFIG_TARGET_SBx81LIFKW=y
@@ -10,6 +11,7 @@
CONFIG_SILENT_U_BOOT_ONLY=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
+CONFIG_CMD_DM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_SF=y
@@ -40,6 +42,8 @@
CONFIG_MV88E61XX_CPU_PORT=10
CONFIG_MV88E61XX_PHY_PORTS=0x003
CONFIG_MV88E61XX_FIXED_PORTS=0x300
+CONFIG_PHY_FIXED=y
+CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_DM_RTC=y
CONFIG_RTC_MV=y
diff --git a/configs/SBx81LIFXCAT_defconfig b/configs/SBx81LIFXCAT_defconfig
index 1f7ff81..c06ad6e 100644
--- a/configs/SBx81LIFXCAT_defconfig
+++ b/configs/SBx81LIFXCAT_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x00600000
CONFIG_TARGET_SBx81LIFXCAT=y
@@ -10,6 +11,7 @@
CONFIG_SILENT_U_BOOT_ONLY=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
+CONFIG_CMD_DM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
@@ -44,6 +46,8 @@
CONFIG_MV88E61XX_CPU_PORT=10
CONFIG_MV88E61XX_PHY_PORTS=0x003
CONFIG_MV88E61XX_FIXED_PORTS=0x300
+CONFIG_PHY_FIXED=y
+CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
diff --git a/configs/Sinlinx_SinA31s_defconfig b/configs/Sinlinx_SinA31s_defconfig
index 31aa768..3588a2c 100644
--- a/configs/Sinlinx_SinA31s_defconfig
+++ b/configs/Sinlinx_SinA31s_defconfig
@@ -11,7 +11,7 @@
CONFIG_USB1_VBUS_PIN=""
CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig
index 586be35..a7383f1 100644
--- a/configs/Sinlinx_SinA33_defconfig
+++ b/configs/Sinlinx_SinA33_defconfig
@@ -13,7 +13,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Sinovoip_BPI_M2_defconfig b/configs/Sinovoip_BPI_M2_defconfig
index d1ee98b..691fd85 100644
--- a/configs/Sinovoip_BPI_M2_defconfig
+++ b/configs/Sinovoip_BPI_M2_defconfig
@@ -7,7 +7,7 @@
CONFIG_USB1_VBUS_PIN=""
CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/Sinovoip_BPI_M3_defconfig b/configs/Sinovoip_BPI_M3_defconfig
index 5174e28..6ded24e 100644
--- a/configs/Sinovoip_BPI_M3_defconfig
+++ b/configs/Sinovoip_BPI_M3_defconfig
@@ -16,8 +16,8 @@
CONFIG_AXP_GPIO=y
CONFIG_SATAPWR="PD25"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
-CONFIG_SPL_TEXT_BASE=0x60
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/Sunchip_CX-A99_defconfig b/configs/Sunchip_CX-A99_defconfig
index 8a9a072..8bc3531 100644
--- a/configs/Sunchip_CX-A99_defconfig
+++ b/configs/Sunchip_CX-A99_defconfig
@@ -12,7 +12,7 @@
CONFIG_USB1_VBUS_PIN="PL7"
CONFIG_USB3_VBUS_PIN="PL8"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x10060
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/T1023RDB_NAND_defconfig b/configs/T1023RDB_NAND_defconfig
index 858d998..1902197 100644
--- a/configs/T1023RDB_NAND_defconfig
+++ b/configs/T1023RDB_NAND_defconfig
@@ -7,6 +7,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1023RDB=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_FIT=y
@@ -20,7 +21,6 @@
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/T1023RDB_SDCARD_defconfig b/configs/T1023RDB_SDCARD_defconfig
index 4d97fda..8f1caae 100644
--- a/configs/T1023RDB_SDCARD_defconfig
+++ b/configs/T1023RDB_SDCARD_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1023RDB=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -19,7 +20,6 @@
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/T1023RDB_SPIFLASH_defconfig b/configs/T1023RDB_SPIFLASH_defconfig
index a367911..49df352 100644
--- a/configs/T1023RDB_SPIFLASH_defconfig
+++ b/configs/T1023RDB_SPIFLASH_defconfig
@@ -9,6 +9,7 @@
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1023RDB=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -20,7 +21,6 @@
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_SPI_BOOT=y
CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/T1024QDS_NAND_defconfig b/configs/T1024QDS_NAND_defconfig
index 5dccb0f..cf010f1 100644
--- a/configs/T1024QDS_NAND_defconfig
+++ b/configs/T1024QDS_NAND_defconfig
@@ -7,6 +7,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1024QDS=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_FIT=y
@@ -23,7 +24,6 @@
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/T1024QDS_SDCARD_defconfig b/configs/T1024QDS_SDCARD_defconfig
index 7b56c0d..df896b3 100644
--- a/configs/T1024QDS_SDCARD_defconfig
+++ b/configs/T1024QDS_SDCARD_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1024QDS=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -22,7 +23,6 @@
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/T1024QDS_SPIFLASH_defconfig b/configs/T1024QDS_SPIFLASH_defconfig
index 34cd506..1a0915b 100644
--- a/configs/T1024QDS_SPIFLASH_defconfig
+++ b/configs/T1024QDS_SPIFLASH_defconfig
@@ -9,6 +9,7 @@
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1024QDS=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -23,7 +24,6 @@
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_SPI_BOOT=y
CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig
index dec0044..af65615 100644
--- a/configs/T1024RDB_NAND_defconfig
+++ b/configs/T1024RDB_NAND_defconfig
@@ -7,6 +7,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1024RDB=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_FIT=y
@@ -22,7 +23,6 @@
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
@@ -45,7 +45,10 @@
CONFIG_CMD_FAT=y
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_FSL_ESDHC=y
@@ -64,10 +67,12 @@
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig
index 5143046..43817be 100644
--- a/configs/T1024RDB_SDCARD_defconfig
+++ b/configs/T1024RDB_SDCARD_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1024RDB=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -21,7 +22,6 @@
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
@@ -43,7 +43,10 @@
CONFIG_CMD_FAT=y
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_FSL_ESDHC=y
@@ -61,10 +64,12 @@
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig
index ff45291..9ffd5d6 100644
--- a/configs/T1024RDB_SPIFLASH_defconfig
+++ b/configs/T1024RDB_SPIFLASH_defconfig
@@ -9,6 +9,7 @@
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1024RDB=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -22,7 +23,6 @@
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_SPI_BOOT=y
CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
@@ -44,7 +44,10 @@
CONFIG_CMD_FAT=y
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_FSL_ESDHC=y
@@ -62,10 +65,12 @@
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig
index 9059329..08a6225 100644
--- a/configs/T1024RDB_defconfig
+++ b/configs/T1024RDB_defconfig
@@ -2,6 +2,7 @@
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_MPC85xx=y
CONFIG_TARGET_T1024RDB=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -29,7 +30,10 @@
CONFIG_CMD_FAT=y
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_FSL_ESDHC=y
@@ -47,10 +51,12 @@
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040D4RDB_NAND_defconfig b/configs/T1040D4RDB_NAND_defconfig
index 3087cf6..ab5a9b7 100644
--- a/configs/T1040D4RDB_NAND_defconfig
+++ b/configs/T1040D4RDB_NAND_defconfig
@@ -7,6 +7,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1040D4RDB=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_FIT=y
@@ -22,7 +23,6 @@
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/T1040D4RDB_SDCARD_defconfig b/configs/T1040D4RDB_SDCARD_defconfig
index 608c09a..edbedf8 100644
--- a/configs/T1040D4RDB_SDCARD_defconfig
+++ b/configs/T1040D4RDB_SDCARD_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1040D4RDB=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -21,7 +22,6 @@
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/T1040D4RDB_SPIFLASH_defconfig b/configs/T1040D4RDB_SPIFLASH_defconfig
index 8c603c8..1f08ee8 100644
--- a/configs/T1040D4RDB_SPIFLASH_defconfig
+++ b/configs/T1040D4RDB_SPIFLASH_defconfig
@@ -9,6 +9,7 @@
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1040D4RDB=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -22,7 +23,6 @@
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_SPI_BOOT=y
CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/T1040RDB_NAND_defconfig b/configs/T1040RDB_NAND_defconfig
index 82cec34..c00c850 100644
--- a/configs/T1040RDB_NAND_defconfig
+++ b/configs/T1040RDB_NAND_defconfig
@@ -7,6 +7,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1040RDB=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_FIT=y
@@ -22,7 +23,6 @@
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/T1040RDB_SDCARD_defconfig b/configs/T1040RDB_SDCARD_defconfig
index be0f262..369b08d4 100644
--- a/configs/T1040RDB_SDCARD_defconfig
+++ b/configs/T1040RDB_SDCARD_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1040RDB=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -21,7 +22,6 @@
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/T1040RDB_SPIFLASH_defconfig b/configs/T1040RDB_SPIFLASH_defconfig
index a3ad573..a19d506 100644
--- a/configs/T1040RDB_SPIFLASH_defconfig
+++ b/configs/T1040RDB_SPIFLASH_defconfig
@@ -9,6 +9,7 @@
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1040RDB=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -22,7 +23,6 @@
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_SPI_BOOT=y
CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig
index fefa5ca..2fcd9e1 100644
--- a/configs/T1042D4RDB_NAND_defconfig
+++ b/configs/T1042D4RDB_NAND_defconfig
@@ -7,6 +7,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1042D4RDB=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_FIT=y
@@ -23,7 +24,6 @@
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
@@ -44,7 +44,10 @@
CONFIG_CMD_FAT=y
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb"
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
@@ -62,6 +65,9 @@
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
@@ -70,4 +76,3 @@
CONFIG_USB_STORAGE=y
CONFIG_VIDEO=y
CONFIG_CFB_CONSOLE_ANSI=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig
index 9fdfb4e..04372fd 100644
--- a/configs/T1042D4RDB_SDCARD_defconfig
+++ b/configs/T1042D4RDB_SDCARD_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1042D4RDB=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -22,7 +23,6 @@
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
@@ -42,7 +42,10 @@
CONFIG_CMD_FAT=y
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb"
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
@@ -59,6 +62,9 @@
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
@@ -67,4 +73,3 @@
CONFIG_USB_STORAGE=y
CONFIG_VIDEO=y
CONFIG_CFB_CONSOLE_ANSI=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig
index 84e0b50..2c869cd 100644
--- a/configs/T1042D4RDB_SPIFLASH_defconfig
+++ b/configs/T1042D4RDB_SPIFLASH_defconfig
@@ -9,6 +9,7 @@
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1042D4RDB=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -23,7 +24,6 @@
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_SPI_BOOT=y
CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
@@ -43,7 +43,10 @@
CONFIG_CMD_FAT=y
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb"
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
@@ -60,6 +63,9 @@
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
@@ -68,4 +74,3 @@
CONFIG_USB_STORAGE=y
CONFIG_VIDEO=y
CONFIG_CFB_CONSOLE_ANSI=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig
index 749baf6..5d8a25f 100644
--- a/configs/T1042D4RDB_defconfig
+++ b/configs/T1042D4RDB_defconfig
@@ -2,6 +2,7 @@
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_MPC85xx=y
CONFIG_TARGET_T1042D4RDB=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -28,7 +29,10 @@
CONFIG_CMD_FAT=y
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb"
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
@@ -45,6 +49,9 @@
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
@@ -53,4 +60,3 @@
CONFIG_USB_STORAGE=y
CONFIG_VIDEO=y
CONFIG_CFB_CONSOLE_ANSI=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig b/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
index ae81f93..7216412 100644
--- a/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
+++ b/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1042RDB_PI=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_FIT=y
@@ -24,7 +25,6 @@
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_CRYPTO_SUPPORT=y
CONFIG_SPL_HASH_SUPPORT=y
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/T1042RDB_PI_NAND_defconfig b/configs/T1042RDB_PI_NAND_defconfig
index f3ec5e6..a32fa4c 100644
--- a/configs/T1042RDB_PI_NAND_defconfig
+++ b/configs/T1042RDB_PI_NAND_defconfig
@@ -7,6 +7,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1042RDB_PI=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_FIT=y
@@ -23,7 +24,6 @@
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/T1042RDB_PI_SDCARD_defconfig b/configs/T1042RDB_PI_SDCARD_defconfig
index e5bd44e..ad145b6 100644
--- a/configs/T1042RDB_PI_SDCARD_defconfig
+++ b/configs/T1042RDB_PI_SDCARD_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1042RDB_PI=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -22,7 +23,6 @@
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/T1042RDB_PI_SPIFLASH_defconfig b/configs/T1042RDB_PI_SPIFLASH_defconfig
index 07e75aa..120fc14 100644
--- a/configs/T1042RDB_PI_SPIFLASH_defconfig
+++ b/configs/T1042RDB_PI_SPIFLASH_defconfig
@@ -9,6 +9,7 @@
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1042RDB_PI=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -23,7 +24,6 @@
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_SPI_BOOT=y
CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig
index 0db930f..4d80bae 100644
--- a/configs/T2080QDS_NAND_defconfig
+++ b/configs/T2080QDS_NAND_defconfig
@@ -8,6 +8,7 @@
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_FIT=y
@@ -20,7 +21,6 @@
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig
index f5cca80..786f154 100644
--- a/configs/T2080QDS_SDCARD_defconfig
+++ b/configs/T2080QDS_SDCARD_defconfig
@@ -9,6 +9,7 @@
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -19,7 +20,6 @@
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig
index 60539f4..066a83b 100644
--- a/configs/T2080QDS_SPIFLASH_defconfig
+++ b/configs/T2080QDS_SPIFLASH_defconfig
@@ -10,6 +10,7 @@
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -20,7 +21,6 @@
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_SPI_BOOT=y
CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig
index 3a34df3..692d01c 100644
--- a/configs/T2080RDB_NAND_defconfig
+++ b/configs/T2080RDB_NAND_defconfig
@@ -7,6 +7,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_FIT=y
@@ -19,7 +20,6 @@
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
@@ -42,7 +42,10 @@
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:1m(uboot),5m(kernel),128k(dtb),-(user)"
# CONFIG_CMD_IRQ is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
@@ -60,10 +63,12 @@
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig
index d40ae38..247cc31 100644
--- a/configs/T2080RDB_SDCARD_defconfig
+++ b/configs/T2080RDB_SDCARD_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -18,7 +19,6 @@
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
@@ -40,7 +40,10 @@
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:1m(uboot),5m(kernel),128k(dtb),-(user)"
# CONFIG_CMD_IRQ is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
@@ -57,10 +60,12 @@
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig
index 3cbf4a0..1370e16 100644
--- a/configs/T2080RDB_SPIFLASH_defconfig
+++ b/configs/T2080RDB_SPIFLASH_defconfig
@@ -9,6 +9,7 @@
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -19,7 +20,6 @@
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_SPI_BOOT=y
CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
@@ -41,7 +41,10 @@
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:1m(uboot),5m(kernel),128k(dtb),-(user)"
# CONFIG_CMD_IRQ is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
@@ -58,10 +61,12 @@
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig
index f1f0f13..bc4a026 100644
--- a/configs/T2080RDB_defconfig
+++ b/configs/T2080RDB_defconfig
@@ -2,6 +2,7 @@
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -26,7 +27,10 @@
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:1m(uboot),5m(kernel),128k(dtb),-(user)"
# CONFIG_CMD_IRQ is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
@@ -43,10 +47,12 @@
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T2081QDS_NAND_defconfig b/configs/T2081QDS_NAND_defconfig
index da722a8..f793e2a 100644
--- a/configs/T2081QDS_NAND_defconfig
+++ b/configs/T2081QDS_NAND_defconfig
@@ -7,6 +7,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2081QDS=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_FIT=y
@@ -19,7 +20,6 @@
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/T2081QDS_SDCARD_defconfig b/configs/T2081QDS_SDCARD_defconfig
index 1769b55..7d4c147 100644
--- a/configs/T2081QDS_SDCARD_defconfig
+++ b/configs/T2081QDS_SDCARD_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2081QDS=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -18,7 +19,6 @@
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/T2081QDS_SPIFLASH_defconfig b/configs/T2081QDS_SPIFLASH_defconfig
index 5093fa3..eb752cd 100644
--- a/configs/T2081QDS_SPIFLASH_defconfig
+++ b/configs/T2081QDS_SPIFLASH_defconfig
@@ -9,6 +9,7 @@
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2081QDS=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -19,7 +20,6 @@
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_SPI_BOOT=y
CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/T4160QDS_NAND_defconfig b/configs/T4160QDS_NAND_defconfig
index f880a46..1a47bbc 100644
--- a/configs/T4160QDS_NAND_defconfig
+++ b/configs/T4160QDS_NAND_defconfig
@@ -7,6 +7,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T4160QDS=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_FIT=y
@@ -19,7 +20,6 @@
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/T4160QDS_SDCARD_defconfig b/configs/T4160QDS_SDCARD_defconfig
index edf39f1..f04c34d 100644
--- a/configs/T4160QDS_SDCARD_defconfig
+++ b/configs/T4160QDS_SDCARD_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T4160QDS=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -18,7 +19,6 @@
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/T4240QDS_NAND_defconfig b/configs/T4240QDS_NAND_defconfig
index 2a98f96..031cdc2 100644
--- a/configs/T4240QDS_NAND_defconfig
+++ b/configs/T4240QDS_NAND_defconfig
@@ -7,6 +7,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T4240QDS=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_FIT=y
@@ -19,7 +20,6 @@
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/T4240QDS_SDCARD_defconfig b/configs/T4240QDS_SDCARD_defconfig
index 83815e5..579d4f4 100644
--- a/configs/T4240QDS_SDCARD_defconfig
+++ b/configs/T4240QDS_SDCARD_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T4240QDS=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -18,7 +19,6 @@
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig
index 9405755..df308d4 100644
--- a/configs/T4240RDB_SDCARD_defconfig
+++ b/configs/T4240RDB_SDCARD_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T4240RDB=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -18,7 +19,6 @@
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
@@ -35,7 +35,10 @@
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="t4240rdb"
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
@@ -51,10 +54,12 @@
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig
index 446c141..9cf2c6a 100644
--- a/configs/T4240RDB_defconfig
+++ b/configs/T4240RDB_defconfig
@@ -2,6 +2,7 @@
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_MPC85xx=y
CONFIG_TARGET_T4240RDB=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -21,7 +22,10 @@
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="t4240rdb"
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
@@ -37,10 +41,12 @@
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig
index 65ab07e..d2e85c9 100644
--- a/configs/TQM834x_defconfig
+++ b/configs/TQM834x_defconfig
@@ -119,6 +119,8 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
diff --git a/configs/UCP1020_SPIFLASH_defconfig b/configs/UCP1020_SPIFLASH_defconfig
deleted file mode 100644
index a2d7e66..0000000
--- a/configs/UCP1020_SPIFLASH_defconfig
+++ /dev/null
@@ -1,60 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_UCP1020=y
-CONFIG_TARGET_UCP1020_SPIFLASH=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_LAST_STAGE_INIT=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc>\" to stop\n"
-CONFIG_AUTOBOOT_STOP_STR="\x1b"
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-# CONFIG_CMD_NAND is not set
-CONFIG_CMD_MMC_SPI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_CRAMFS=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_FS_CRAMFS=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/UTOO_P66_defconfig b/configs/UTOO_P66_defconfig
index 78cd62c..2b10629 100644
--- a/configs/UTOO_P66_defconfig
+++ b/configs/UTOO_P66_defconfig
@@ -20,7 +20,7 @@
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_VIDEO_LCD_TL059WV5C0=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Wexler_TAB7200_defconfig b/configs/Wexler_TAB7200_defconfig
index f75606e..6413fab 100644
--- a/configs/Wexler_TAB7200_defconfig
+++ b/configs/Wexler_TAB7200_defconfig
@@ -13,7 +13,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Wits_Pro_A20_DKT_defconfig b/configs/Wits_Pro_A20_DKT_defconfig
index 4e37650..437c867 100644
--- a/configs/Wits_Pro_A20_DKT_defconfig
+++ b/configs/Wits_Pro_A20_DKT_defconfig
@@ -12,7 +12,7 @@
CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Wobo_i5_defconfig b/configs/Wobo_i5_defconfig
index 92d851f..e21e4e0 100644
--- a/configs/Wobo_i5_defconfig
+++ b/configs/Wobo_i5_defconfig
@@ -7,7 +7,7 @@
CONFIG_MMC0_CD_PIN="PB3"
CONFIG_USB1_VBUS_PIN="PG12"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Yones_Toptech_BD1078_defconfig b/configs/Yones_Toptech_BD1078_defconfig
index 376fc2f..0f8c8af 100644
--- a/configs/Yones_Toptech_BD1078_defconfig
+++ b/configs/Yones_Toptech_BD1078_defconfig
@@ -19,7 +19,7 @@
# CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW is not set
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/Yones_Toptech_BS1078_V2_defconfig b/configs/Yones_Toptech_BS1078_V2_defconfig
index b8c923e..9c8107c 100644
--- a/configs/Yones_Toptech_BS1078_V2_defconfig
+++ b/configs/Yones_Toptech_BS1078_V2_defconfig
@@ -16,7 +16,7 @@
CONFIG_VIDEO_LCD_BL_PWM="PH13"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/a64-olinuxino_defconfig b/configs/a64-olinuxino_defconfig
index afc8cff..8a3561b 100644
--- a/configs/a64-olinuxino_defconfig
+++ b/configs/a64-olinuxino_defconfig
@@ -6,7 +6,7 @@
CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x10060
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/alt_defconfig b/configs/alt_defconfig
index a86ff90..0284d80 100644
--- a/configs/alt_defconfig
+++ b/configs/alt_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
@@ -16,15 +17,16 @@
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0xe6300000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_TEXT_BASE=0xe6300000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig
index aa8fee5..d6db96c 100644
--- a/configs/am335x_baltos_defconfig
+++ b/configs/am335x_baltos_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
@@ -69,4 +70,5 @@
CONFIG_USB_FUNCTION_MASS_STORAGE=y
CONFIG_USB_ETHER=y
CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00"
+CONFIG_WDT=y
CONFIG_FAT_WRITE=y
diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig
index ffe013f..47c4e99 100644
--- a/configs/am335x_boneblack_vboot_defconfig
+++ b/configs/am335x_boneblack_vboot_defconfig
@@ -1,4 +1,7 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_AM33XX=y
@@ -29,7 +32,7 @@
CONFIG_DEFAULT_DEVICE_TREE="am335x-boneblack"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-# CONFIG_BLK is not set
+# CONFIG_SPL_BLK is not set
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
@@ -37,7 +40,9 @@
CONFIG_DM_I2C=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
+# CONFIG_SPL_DM_MMC is not set
CONFIG_MMC_OMAP_HS=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SPI_FLASH_WINBOND=y
@@ -46,6 +51,7 @@
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index ff96f19..2aa9b65 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_AM33XX=y
@@ -70,6 +71,8 @@
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
CONFIG_USB_ETHER=y
+CONFIG_WDT=y
+# CONFIG_SPL_WDT is not set
CONFIG_DYNAMIC_CRC_TABLE=y
CONFIG_RSA=y
CONFIG_LZO=y
diff --git a/configs/am335x_guardian_defconfig b/configs/am335x_guardian_defconfig
index 3a57946..3cada51 100644
--- a/configs/am335x_guardian_defconfig
+++ b/configs/am335x_guardian_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -8,6 +9,8 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_ENV_SIZE=0x040000
+CONFIG_ENV_OFFSET=0x300000
CONFIG_SPL=y
CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_SPL_LIBDISK_SUPPORT=y
diff --git a/configs/am335x_hs_evm_defconfig b/configs/am335x_hs_evm_defconfig
index 42e7fc9..f5da7f6 100644
--- a/configs/am335x_hs_evm_defconfig
+++ b/configs/am335x_hs_evm_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_ISW_ENTRY_ADDR=0x40300350
diff --git a/configs/am335x_hs_evm_uart_defconfig b/configs/am335x_hs_evm_uart_defconfig
index ba1b8a1..3708a6f 100644
--- a/configs/am335x_hs_evm_uart_defconfig
+++ b/configs/am335x_hs_evm_uart_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_ISW_ENTRY_ADDR=0x40301950
diff --git a/configs/am335x_igep003x_defconfig b/configs/am335x_igep003x_defconfig
index ea2a68f..8ed52a5 100644
--- a/configs/am335x_igep003x_defconfig
+++ b/configs/am335x_igep003x_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -8,6 +9,7 @@
CONFIG_TARGET_AM335X_IGEP003X=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x18000
CONFIG_SPL=y
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
@@ -20,6 +22,18 @@
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_UBI=y
+CONFIG_SPL_UBI_MAX_VOL_LEBS=256
+CONFIG_SPL_UBI_MAX_PEB_SIZE=262144
+CONFIG_SPL_UBI_MAX_PEBS=4096
+CONFIG_SPL_UBI_PEB_OFFSET=4
+CONFIG_SPL_UBI_VID_OFFSET=512
+CONFIG_SPL_UBI_LEB_START=2048
+CONFIG_SPL_UBI_INFO_ADDR=0x88080000
+CONFIG_SPL_UBI_VOL_IDS=8
+CONFIG_SPL_UBI_LOAD_MONITOR_ID=0
+CONFIG_SPL_UBI_LOAD_KERNEL_ID=3
+CONFIG_SPL_UBI_LOAD_ARGS_ID=4
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
@@ -42,6 +56,9 @@
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-base0033"
CONFIG_ENV_IS_IN_UBI=y
+CONFIG_ENV_UBI_PART="UBI"
+CONFIG_ENV_UBI_VOLUME="config"
+CONFIG_ENV_UBI_VOLUME_REDUND="config_r"
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
diff --git a/configs/am335x_pdu001_defconfig b/configs/am335x_pdu001_defconfig
index a0a4aba..e69f81b 100644
--- a/configs/am335x_pdu001_defconfig
+++ b/configs/am335x_pdu001_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
@@ -6,6 +7,7 @@
CONFIG_TARGET_PDU001=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
CONFIG_SPL=y
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
@@ -49,6 +51,5 @@
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_TPS65910=y
CONFIG_CONS_INDEX=4
-# CONFIG_OMAP_WATCHDOG is not set
# CONFIG_USE_TINY_PRINTF is not set
# CONFIG_EFI_LOADER is not set
diff --git a/configs/am335x_shc_defconfig b/configs/am335x_shc_defconfig
index 98efb6f..5698208 100644
--- a/configs/am335x_shc_defconfig
+++ b/configs/am335x_shc_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -7,11 +8,14 @@
CONFIG_TARGET_AM335X_SHC=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x7000
CONFIG_SPL=y
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SERIES=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SHOW_BOOT_PROGRESS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DEFAULT_FDT_FILE="am335x-shc"
diff --git a/configs/am335x_shc_ict_defconfig b/configs/am335x_shc_ict_defconfig
index 94672f6..3f8a6ba 100644
--- a/configs/am335x_shc_ict_defconfig
+++ b/configs/am335x_shc_ict_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -7,12 +8,15 @@
CONFIG_TARGET_AM335X_SHC=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x7000
CONFIG_SPL=y
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SHC_ICT=y
CONFIG_SERIES=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SHOW_BOOT_PROGRESS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DEFAULT_FDT_FILE="am335x-shc"
diff --git a/configs/am335x_shc_netboot_defconfig b/configs/am335x_shc_netboot_defconfig
index ab7afdd..d0a7d62 100644
--- a/configs/am335x_shc_netboot_defconfig
+++ b/configs/am335x_shc_netboot_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -7,12 +8,15 @@
CONFIG_TARGET_AM335X_SHC=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x7000
CONFIG_SPL=y
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SHC_NETBOOT=y
CONFIG_SERIES=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SHOW_BOOT_PROGRESS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DEFAULT_FDT_FILE="am335x-shc"
diff --git a/configs/am335x_shc_sdboot_defconfig b/configs/am335x_shc_sdboot_defconfig
index ea77f4e..30fa40a 100644
--- a/configs/am335x_shc_sdboot_defconfig
+++ b/configs/am335x_shc_sdboot_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -7,12 +8,15 @@
CONFIG_TARGET_AM335X_SHC=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x7000
CONFIG_SPL=y
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SHC_SDBOOT=y
CONFIG_SERIES=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SHOW_BOOT_PROGRESS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DEFAULT_FDT_FILE="am335x-shc"
diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig
index 678ead9..01fc52b 100644
--- a/configs/am335x_sl50_defconfig
+++ b/configs/am335x_sl50_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -7,6 +8,7 @@
CONFIG_TARGET_AM335X_SL50=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_OFFSET=0x0
CONFIG_SPL=y
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
diff --git a/configs/am3517_crane_defconfig b/configs/am3517_crane_defconfig
index 07067a5..921b9ba 100644
--- a/configs/am3517_crane_defconfig
+++ b/configs/am3517_crane_defconfig
@@ -7,8 +7,8 @@
CONFIG_EMIF4=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
-CONFIG_BOOTDELAY=10
CONFIG_SPL_TEXT_BASE=0x40200800
+CONFIG_BOOTDELAY=10
# CONFIG_SPL_FS_EXT4 is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMDLINE_EDITING is not set
diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig
index b9f59f3..9612bba 100644
--- a/configs/am3517_evm_defconfig
+++ b/configs/am3517_evm_defconfig
@@ -1,22 +1,28 @@
CONFIG_ARM=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80100000
CONFIG_TI_COMMON_CMD_OPTIONS=y
-# CONFIG_SPL_GPIO_SUPPORT is not set
-CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_TARGET_AM3517_EVM=y
CONFIG_EMIF4=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x3000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=10
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SEPARATE_BSS=y
+# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
# CONFIG_SPL_FS_EXT4 is not set
+# CONFIG_SPL_I2C_SUPPORT is not set
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
+# CONFIG_SPL_POWER_SUPPORT is not set
CONFIG_SYS_PROMPT="AM3517_EVM # "
# CONFIG_CMD_IMI is not set
CONFIG_CMD_SPL=y
@@ -34,9 +40,13 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1920k(u-boot),256k(u-boot-env),8m(kernel),512k(dtb),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="am3517-evm"
# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_OF_TRANSLATE=y
CONFIG_DM_PCA953X=y
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
@@ -44,12 +54,17 @@
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
CONFIG_SPL_NAND_SIMPLE=y
+CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_DRIVER_TI_EMAC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_SINGLE=y
+CONFIG_DM_PMIC=y
+# CONFIG_SPL_PMIC_CHILDREN is not set
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
# CONFIG_TWL4030_POWER is not set
-CONFIG_CONS_INDEX=3
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
@@ -59,3 +74,4 @@
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_AM35X=y
CONFIG_BCH=y
+CONFIG_SPL_TINY_MEMSET=y
diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index 526dda2..7c74047 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -1,9 +1,11 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_AM43XX=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_ENV_SIZE=0x10000
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_LOAD_FIT=y
@@ -36,7 +38,6 @@
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
-# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig
index b644273..b1bf670 100644
--- a/configs/am43xx_evm_qspiboot_defconfig
+++ b/configs/am43xx_evm_qspiboot_defconfig
@@ -1,8 +1,12 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x30000000
CONFIG_AM43XX=y
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x110000
+CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1,QSPI,QSPI_BOOT"
CONFIG_QSPI_BOOT=y
@@ -31,7 +35,6 @@
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
-# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
@@ -47,6 +50,7 @@
CONFIG_SPI=y
CONFIG_TI_QSPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
diff --git a/configs/am43xx_evm_rtconly_defconfig b/configs/am43xx_evm_rtconly_defconfig
index c855705..3064f31 100644
--- a/configs/am43xx_evm_rtconly_defconfig
+++ b/configs/am43xx_evm_rtconly_defconfig
@@ -1,9 +1,11 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_AM43XX=y
CONFIG_SPL_RTC_DDR_SUPPORT=y
+CONFIG_ENV_SIZE=0x10000
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_LOAD_FIT=y
@@ -28,7 +30,6 @@
CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm"
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
-# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
@@ -48,6 +49,7 @@
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index 6a47c66..f1a1a48 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -1,8 +1,10 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_ISW_ENTRY_ADDR=0x40300350
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_AM43XX=y
+CONFIG_ENV_SIZE=0x10000
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_LOAD_FIT=y
@@ -14,7 +16,8 @@
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_USB_HOST_SUPPORT=y
-CONFIG_SPL_USB_STORAGE=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_ETHER=y
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_NAND_OFS=0x00100000
CONFIG_CMD_SPL_WRITE_SIZE=0x40000
@@ -40,7 +43,6 @@
CONFIG_ENV_IS_IN_FAT=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
-# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
@@ -60,6 +62,7 @@
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig
index ff7f815..0b32568 100644
--- a/configs/am43xx_hs_evm_defconfig
+++ b/configs/am43xx_hs_evm_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_ISW_ENTRY_ADDR=0x403018e0
@@ -8,7 +9,9 @@
CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000
+CONFIG_ENV_SIZE=0x10000
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x403018E0
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_IMAGE_POST_PROCESS=y
CONFIG_SPL_LOAD_FIT=y
@@ -19,13 +22,11 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_MISC_INIT_R is not set
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_TEXT_BASE=0x403018E0
CONFIG_SPL_ETH_SUPPORT=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_NET_SUPPORT=y
CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
CONFIG_SPL_USB_HOST_SUPPORT=y
-CONFIG_SPL_USB_STORAGE=y
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_USB_ETHER=y
# CONFIG_CMD_FLASH is not set
@@ -39,7 +40,6 @@
CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm"
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
-# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
@@ -59,6 +59,7 @@
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index a3de7a4..3b613e1 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -10,6 +10,7 @@
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ARMV7_LPAE=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0x40300000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_OF_BOARD_SETUP=y
@@ -20,15 +21,17 @@
# CONFIG_MISC_INIT_R is not set
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x40300000
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_DMA_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_CMD_DTIMG=y
CONFIG_CMD_SPL=y
+CONFIG_CMD_BCB=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_PMIC is not set
diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index d2548ff..7b56df8 100644
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -31,6 +31,9 @@
CONFIG_SPL_DMA_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_CMD_DTIMG=y
+CONFIG_CMD_BCB=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_PMIC is not set
diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig
index b52d321..0b47df6 100644
--- a/configs/am57xx_hs_evm_usb_defconfig
+++ b/configs/am57xx_hs_evm_usb_defconfig
@@ -14,6 +14,7 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ARMV7_LPAE=y
+CONFIG_SPL_TEXT_BASE=0x40306D50
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_IMAGE_POST_PROCESS=y
CONFIG_SPL_LOAD_FIT=y
@@ -26,16 +27,18 @@
# CONFIG_MISC_INIT_R is not set
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x40306D50
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_DMA_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_DFU=y
CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_CMD_DTIMG=y
+CONFIG_CMD_BCB=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_PMIC is not set
diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig
index 41cf010..e5b127c 100644
--- a/configs/am65x_evm_a53_defconfig
+++ b/configs/am65x_evm_a53_defconfig
@@ -2,7 +2,7 @@
CONFIG_ARCH_K3=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SOC_K3_AM6=y
CONFIG_TARGET_AM654_A53_EVM=y
CONFIG_SPL_MMC_SUPPORT=y
@@ -12,52 +12,70 @@
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run run_kern"
+CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_POWER_DOMAIN=y
-CONFIG_SPL_REMOTEPROC=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_REMOTEPROC=y
+CONFIG_CMD_PCI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am654-base-board"
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
-CONFIG_ENV_IS_IN_FAT=y
-CONFIG_ENV_FAT_INTERFACE="mmc"
-CONFIG_ENV_FAT_DEVICE_AND_PART="1:1"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CLK_TI_SCI=y
CONFIG_DMA_CHANNELS=y
CONFIG_TI_K3_NAVSS_UDMA=y
CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_K3_ARASAN=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_PHY_TI=y
+CONFIG_PHY_FIXED=y
+CONFIG_DM_ETH=y
+CONFIG_E1000=y
+CONFIG_CMD_E1000=y
+CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_KEYSTONE=y
+CONFIG_PHY=y
+CONFIG_AM654_PHY=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
CONFIG_SPL_PINCTRL=y
@@ -65,8 +83,6 @@
CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
CONFIG_TI_SCI_POWER_DOMAIN=y
-CONFIG_K3_SYSTEM_CONTROLLER=y
-CONFIG_REMOTEPROC_K3=y
CONFIG_DM_RESET=y
CONFIG_RESET_TI_SCI=y
CONFIG_DM_SERIAL=y
@@ -74,3 +90,5 @@
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
+CONFIG_FAT_WRITE=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig
index 3814872..077aa37 100644
--- a/configs/am65x_evm_r5_defconfig
+++ b/configs/am65x_evm_r5_defconfig
@@ -3,7 +3,7 @@
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_MALLOC_F_LEN=0x55000
CONFIG_SOC_K3_AM6=y
CONFIG_TARGET_AM654_R5_EVM=y
CONFIG_SPL_MMC_SUPPORT=y
@@ -13,14 +13,16 @@
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0x41c00000
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_USE_BOOTCOMMAND=y
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_TEXT_BASE=0x41c00000
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_EARLY_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_DM_RESET=y
@@ -35,6 +37,7 @@
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_REMOTEPROC=y
# CONFIG_CMD_SETEXPR is not set
@@ -51,6 +54,8 @@
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
@@ -58,12 +63,15 @@
CONFIG_TI_SCI_PROTOCOL=y
CONFIG_DM_GPIO=y
CONFIG_DA8XX_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_K3_ARASAN=y
+CONFIG_MMC_SDHCI_AM654=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
CONFIG_SPL_PINCTRL=y
@@ -78,7 +86,7 @@
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_K3_SYSTEM_CONTROLLER=y
-CONFIG_REMOTEPROC_K3=y
+CONFIG_REMOTEPROC_TI_K3_ARM64=y
CONFIG_DM_RESET=y
CONFIG_RESET_TI_SCI=y
CONFIG_DM_SERIAL=y
@@ -88,3 +96,4 @@
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_OMAP_TIMER=y
+CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
diff --git a/configs/am65x_hs_evm_a53_defconfig b/configs/am65x_hs_evm_a53_defconfig
index 9c55cd3..e9fceea 100644
--- a/configs/am65x_hs_evm_a53_defconfig
+++ b/configs/am65x_hs_evm_a53_defconfig
@@ -3,7 +3,7 @@
CONFIG_TI_SECURE_DEVICE=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SOC_K3_AM6=y
CONFIG_TARGET_AM654_A53_EVM=y
CONFIG_SPL_MMC_SUPPORT=y
@@ -13,28 +13,29 @@
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_FIT_IMAGE_POST_PROCESS=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run run_kern"
+CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_fit_${boot}; run get_overlaystring; run run_fit"
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_POWER_DOMAIN=y
-CONFIG_SPL_REMOTEPROC=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_REMOTEPROC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
# CONFIG_ISO_PARTITION is not set
@@ -56,11 +57,15 @@
CONFIG_DMA_CHANNELS=y
CONFIG_TI_K3_NAVSS_UDMA=y
CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_K3_ARASAN=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
CONFIG_SPL_PINCTRL=y
@@ -68,8 +73,6 @@
CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
CONFIG_TI_SCI_POWER_DOMAIN=y
-CONFIG_K3_SYSTEM_CONTROLLER=y
-CONFIG_REMOTEPROC_K3=y
CONFIG_DM_RESET=y
CONFIG_RESET_TI_SCI=y
CONFIG_DM_SERIAL=y
@@ -77,3 +80,4 @@
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/am65x_hs_evm_r5_defconfig b/configs/am65x_hs_evm_r5_defconfig
index 0b12f15..6a3110d 100644
--- a/configs/am65x_hs_evm_r5_defconfig
+++ b/configs/am65x_hs_evm_r5_defconfig
@@ -4,7 +4,7 @@
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_MALLOC_F_LEN=0x55000
CONFIG_SOC_K3_AM6=y
CONFIG_TARGET_AM654_R5_EVM=y
CONFIG_SPL_MMC_SUPPORT=y
@@ -14,15 +14,17 @@
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0x41c00000
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
CONFIG_USE_BOOTCOMMAND=y
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_TEXT_BASE=0x41c00000
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_EARLY_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_DM_RESET=y
@@ -37,6 +39,7 @@
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_REMOTEPROC=y
# CONFIG_CMD_SETEXPR is not set
@@ -60,12 +63,14 @@
CONFIG_TI_SCI_PROTOCOL=y
CONFIG_DM_GPIO=y
CONFIG_DA8XX_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_K3_ARASAN=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
CONFIG_SPL_PINCTRL=y
@@ -80,7 +85,7 @@
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_K3_SYSTEM_CONTROLLER=y
-CONFIG_REMOTEPROC_K3=y
+CONFIG_REMOTEPROC_TI_K3_ARM64=y
CONFIG_DM_RESET=y
CONFIG_RESET_TI_SCI=y
CONFIG_DM_SERIAL=y
@@ -90,3 +95,4 @@
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_OMAP_TIMER=y
+CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
diff --git a/configs/amarula_a64_relic_defconfig b/configs/amarula_a64_relic_defconfig
index 4d546af..9eda731 100644
--- a/configs/amarula_a64_relic_defconfig
+++ b/configs/amarula_a64_relic_defconfig
@@ -7,7 +7,7 @@
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_VIDEO_DE2 is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x10060
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/amcore_defconfig b/configs/amcore_defconfig
index 6a00ea2..d68d522 100644
--- a/configs/amcore_defconfig
+++ b/configs/amcore_defconfig
@@ -12,6 +12,7 @@
CONFIG_CMD_IMLS=y
# CONFIG_CMD_XIMG is not set
CONFIG_LOOPW=y
+CONFIG_MX_CYCLIC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIMER=y
diff --git a/configs/apalis-imx8qm_defconfig b/configs/apalis-imx8qm_defconfig
index 7f6ccc9..071e470 100644
--- a/configs/apalis-imx8qm_defconfig
+++ b/configs/apalis-imx8qm_defconfig
@@ -12,6 +12,7 @@
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
CONFIG_CMD_ASKENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
@@ -35,6 +36,7 @@
CONFIG_SYS_I2C_IMX_LPI2C=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_MICREL=y
diff --git a/configs/apalis-tk1_defconfig b/configs/apalis-tk1_defconfig
index 41f3aff..759d8eb 100644
--- a/configs/apalis-tk1_defconfig
+++ b/configs/apalis-tk1_defconfig
@@ -5,19 +5,18 @@
CONFIG_NR_DRAM_BANKS=2
CONFIG_TEGRA124=y
CONFIG_TARGET_APALIS_TK1=y
+CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_FIT=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTDELAY=1
-CONFIG_BOOTCOMMAND="run emmcboot; setenv fdtfile ${soc}-apalis-${fdt_board}.dtb && run distro_bootcmd"
+CONFIG_BOOTCOMMAND="run emmcboot; setenv fdtfile ${soc}-${fdt-module}-${fdt_board}.dtb && run distro_bootcmd"
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_SYS_PROMPT="Apalis TK1 # "
# CONFIG_CMD_IMI is not set
-CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
@@ -34,8 +33,6 @@
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_BLOCKSIZE=16352
CONFIG_SPL_DM=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_RAM=y
CONFIG_SYS_I2C_TEGRA=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK=y
@@ -56,7 +53,7 @@
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Toradex"
CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
-CONFIG_USB_GADGET_PRODUCT_NUM=0xffff
+CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig
index 248922c..797bbb0 100644
--- a/configs/apalis_imx6_defconfig
+++ b/configs/apalis_imx6_defconfig
@@ -11,6 +11,7 @@
CONFIG_SPL=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
@@ -23,7 +24,6 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_USB_HOST_SUPPORT=y
@@ -37,7 +37,6 @@
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
@@ -56,12 +55,11 @@
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_BLOCKSIZE=4096
CONFIG_DWC_AHSATA=y
-CONFIG_DFU_MMC=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig
index cf4d144..b0ebf64 100644
--- a/configs/apalis_t30_defconfig
+++ b/configs/apalis_t30_defconfig
@@ -5,16 +5,15 @@
CONFIG_NR_DRAM_BANKS=2
CONFIG_TEGRA30=y
CONFIG_TARGET_APALIS_T30=y
+CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_SYS_PROMPT="Apalis T30 # "
# CONFIG_CMD_IMI is not set
-CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
@@ -31,8 +30,6 @@
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_BLOCKSIZE=16352
CONFIG_SPL_DM=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_RAM=y
CONFIG_SYS_I2C_TEGRA=y
CONFIG_E1000=y
CONFIG_PCI=y
diff --git a/configs/apf27_defconfig b/configs/apf27_defconfig
index 0f5123a..2b82f05 100644
--- a/configs/apf27_defconfig
+++ b/configs/apf27_defconfig
@@ -6,13 +6,15 @@
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
CONFIG_IDENT_STRING=" apf27 patch 3.10"
+CONFIG_SPL_TEXT_BASE=0xA0000000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttySMX0,115200 mtdparts=mxc_nand.0:1M(u-boot)ro,512K(env),512K(env2),512K(firmware),512K(dtb),5M(kernel),-(rootfs) ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs "
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="run check_flash check_env;"
CONFIG_VERSION_VARIABLE=y
# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_TEXT_BASE=0xA0000000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="BIOS> "
diff --git a/configs/apx4devkit_defconfig b/configs/apx4devkit_defconfig
index c5eb53e..89f58e5 100644
--- a/configs/apx4devkit_defconfig
+++ b/configs/apx4devkit_defconfig
@@ -8,13 +8,13 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x00001000
CONFIG_BOOTDELAY=1
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_TEXT_BASE=0x00001000
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
@@ -31,6 +31,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:128k(bootstrap),1024k(boot),768k(env),-(root)"
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_MXS_GPIO=y
CONFIG_MMC_MXS=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig
index 87a8678..18ef5d2 100644
--- a/configs/aristainetos2_defconfig
+++ b/configs/aristainetos2_defconfig
@@ -35,7 +35,7 @@
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_SPI_FLASH=y
@@ -50,6 +50,7 @@
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_MII=y
+CONFIG_PWM_IMX=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
diff --git a/configs/aristainetos2b_defconfig b/configs/aristainetos2b_defconfig
index 256d722..1054c05 100644
--- a/configs/aristainetos2b_defconfig
+++ b/configs/aristainetos2b_defconfig
@@ -35,7 +35,7 @@
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_SPI_FLASH=y
@@ -48,6 +48,7 @@
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_MII=y
+CONFIG_PWM_IMX=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
diff --git a/configs/aristainetos_defconfig b/configs/aristainetos_defconfig
index 44b30e3..4080a7b 100644
--- a/configs/aristainetos_defconfig
+++ b/configs/aristainetos_defconfig
@@ -35,7 +35,7 @@
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_SPI_FLASH=y
@@ -49,6 +49,7 @@
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_MII=y
+CONFIG_PWM_IMX=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
diff --git a/configs/armadillo-800eva_defconfig b/configs/armadillo-800eva_defconfig
index 8168c3a..6eefabd 100644
--- a/configs/armadillo-800eva_defconfig
+++ b/configs/armadillo-800eva_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0xE80C0000
diff --git a/configs/arndale_defconfig b/configs/arndale_defconfig
index c1b727e..2718d0c 100644
--- a/configs/arndale_defconfig
+++ b/configs/arndale_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x43E00000
CONFIG_ARCH_EXYNOS5=y
@@ -6,13 +7,14 @@
CONFIG_NR_DRAM_BANKS=8
CONFIG_SPL=y
CONFIG_IDENT_STRING=" for ARNDALE"
+CONFIG_SPL_TEXT_BASE=0x02023400
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
+CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_TEXT_BASE=0x02023400
CONFIG_SYS_PROMPT="ARNDALE # "
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
diff --git a/configs/aspenite_defconfig b/configs/aspenite_defconfig
index 68b68f8..8e67717 100644
--- a/configs/aspenite_defconfig
+++ b/configs/aspenite_defconfig
@@ -1,9 +1,11 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_TARGET_ASPENITE=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_NR_DRAM_BANKS=2
CONFIG_IDENT_STRING="\nMarvell-Aspenite DB"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/at91rm9200ek_defconfig b/configs/at91rm9200ek_defconfig
index 7ebbdac..834457c 100644
--- a/configs/at91rm9200ek_defconfig
+++ b/configs/at91rm9200ek_defconfig
@@ -1,8 +1,12 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x10000000
CONFIG_TARGET_AT91RM9200EK=y
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x40000
CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/at91rm9200ek_ram_defconfig b/configs/at91rm9200ek_ram_defconfig
index 87fd7a3..9317191 100644
--- a/configs/at91rm9200ek_ram_defconfig
+++ b/configs/at91rm9200ek_ram_defconfig
@@ -1,8 +1,12 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x20100000
CONFIG_TARGET_AT91RM9200EK=y
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x40000
CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_CPUINFO is not set
diff --git a/configs/at91sam9260ek_dataflash_cs0_defconfig b/configs/at91sam9260ek_dataflash_cs0_defconfig
index 137ecd9..ef1b3b4 100644
--- a/configs/at91sam9260ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9260ek_dataflash_cs0_defconfig
@@ -1,12 +1,16 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4200
+CONFIG_ENV_OFFSET=0x4200
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
+CONFIG_ENV_SECT_SIZE=0x210
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS0"
CONFIG_BOOTDELAY=3
@@ -38,6 +42,7 @@
CONFIG_AT91_GPIO=y
# CONFIG_MMC is not set
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/at91sam9260ek_dataflash_cs1_defconfig b/configs/at91sam9260ek_dataflash_cs1_defconfig
index 2547f2d..89129ce 100644
--- a/configs/at91sam9260ek_dataflash_cs1_defconfig
+++ b/configs/at91sam9260ek_dataflash_cs1_defconfig
@@ -1,12 +1,16 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4200
+CONFIG_ENV_OFFSET=0x4200
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
+CONFIG_ENV_SECT_SIZE=0x210
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS1"
CONFIG_BOOTDELAY=3
@@ -38,6 +42,7 @@
CONFIG_AT91_GPIO=y
# CONFIG_MMC is not set
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/at91sam9260ek_nandflash_defconfig b/configs/at91sam9260ek_nandflash_defconfig
index b9bad09..79ef08c 100644
--- a/configs/at91sam9260ek_nandflash_defconfig
+++ b/configs/at91sam9260ek_nandflash_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_TARGET_AT91SAM9260EK=y
@@ -36,6 +37,7 @@
CONFIG_AT91_GPIO=y
# CONFIG_MMC is not set
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/at91sam9261ek_dataflash_cs0_defconfig b/configs/at91sam9261ek_dataflash_cs0_defconfig
index 8eab764..410f711 100644
--- a/configs/at91sam9261ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9261ek_dataflash_cs0_defconfig
@@ -3,10 +3,13 @@
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_TARGET_AT91SAM9261EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4200
+CONFIG_ENV_OFFSET=0x4200
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_ENV_SECT_SIZE=0x210
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_DATAFLASH_CS0"
CONFIG_BOOTDELAY=3
@@ -39,6 +42,7 @@
CONFIG_AT91_GPIO=y
# CONFIG_MMC is not set
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/at91sam9261ek_dataflash_cs3_defconfig b/configs/at91sam9261ek_dataflash_cs3_defconfig
index dfafdfa..8343758 100644
--- a/configs/at91sam9261ek_dataflash_cs3_defconfig
+++ b/configs/at91sam9261ek_dataflash_cs3_defconfig
@@ -3,10 +3,13 @@
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_TARGET_AT91SAM9261EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4200
+CONFIG_ENV_OFFSET=0x4200
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_ENV_SECT_SIZE=0x210
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_DATAFLASH_CS3"
CONFIG_BOOTDELAY=3
@@ -39,6 +42,7 @@
CONFIG_AT91_GPIO=y
# CONFIG_MMC is not set
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/at91sam9261ek_nandflash_defconfig b/configs/at91sam9261ek_nandflash_defconfig
index d94f930..471715a 100644
--- a/configs/at91sam9261ek_nandflash_defconfig
+++ b/configs/at91sam9261ek_nandflash_defconfig
@@ -37,6 +37,7 @@
CONFIG_AT91_GPIO=y
# CONFIG_MMC is not set
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/at91sam9263ek_dataflash_cs0_defconfig b/configs/at91sam9263ek_dataflash_cs0_defconfig
index b768a32..ce30dbb 100644
--- a/configs/at91sam9263ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9263ek_dataflash_cs0_defconfig
@@ -1,12 +1,16 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21F00000
CONFIG_TARGET_AT91SAM9263EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4200
+CONFIG_ENV_OFFSET=0x4200
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_ENV_SECT_SIZE=0x210
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
CONFIG_BOOTDELAY=3
@@ -43,6 +47,7 @@
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/at91sam9263ek_dataflash_defconfig b/configs/at91sam9263ek_dataflash_defconfig
index b768a32..ce30dbb 100644
--- a/configs/at91sam9263ek_dataflash_defconfig
+++ b/configs/at91sam9263ek_dataflash_defconfig
@@ -1,12 +1,16 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21F00000
CONFIG_TARGET_AT91SAM9263EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4200
+CONFIG_ENV_OFFSET=0x4200
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_ENV_SECT_SIZE=0x210
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
CONFIG_BOOTDELAY=3
@@ -43,6 +47,7 @@
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/at91sam9263ek_nandflash_defconfig b/configs/at91sam9263ek_nandflash_defconfig
index b1cf749..5149b34 100644
--- a/configs/at91sam9263ek_nandflash_defconfig
+++ b/configs/at91sam9263ek_nandflash_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21F00000
CONFIG_TARGET_AT91SAM9263EK=y
@@ -41,6 +42,7 @@
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/at91sam9263ek_norflash_boot_defconfig b/configs/at91sam9263ek_norflash_boot_defconfig
index 270d2e6..6e7ab93 100644
--- a/configs/at91sam9263ek_norflash_boot_defconfig
+++ b/configs/at91sam9263ek_norflash_boot_defconfig
@@ -1,12 +1,16 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x0000000
CONFIG_TARGET_AT91SAM9263EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x7e0000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_BOOT_NORFLASH"
CONFIG_BOOTDELAY=3
@@ -42,6 +46,7 @@
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/at91sam9263ek_norflash_defconfig b/configs/at91sam9263ek_norflash_defconfig
index ad86956..03c5562 100644
--- a/configs/at91sam9263ek_norflash_defconfig
+++ b/configs/at91sam9263ek_norflash_defconfig
@@ -1,12 +1,16 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21F00000
CONFIG_TARGET_AT91SAM9263EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x7e0000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NORFLASH"
CONFIG_BOOTDELAY=3
@@ -42,6 +46,7 @@
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/at91sam9g10ek_dataflash_cs0_defconfig b/configs/at91sam9g10ek_dataflash_cs0_defconfig
index a20f461..8a3cf11 100644
--- a/configs/at91sam9g10ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9g10ek_dataflash_cs0_defconfig
@@ -3,10 +3,13 @@
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_TARGET_AT91SAM9261EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4200
+CONFIG_ENV_OFFSET=0x4200
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_ENV_SECT_SIZE=0x210
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_DATAFLASH_CS0"
CONFIG_BOOTDELAY=3
@@ -39,6 +42,7 @@
CONFIG_AT91_GPIO=y
# CONFIG_MMC is not set
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/at91sam9g10ek_dataflash_cs3_defconfig b/configs/at91sam9g10ek_dataflash_cs3_defconfig
index 5ea03c5..89466b0 100644
--- a/configs/at91sam9g10ek_dataflash_cs3_defconfig
+++ b/configs/at91sam9g10ek_dataflash_cs3_defconfig
@@ -3,10 +3,13 @@
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_TARGET_AT91SAM9261EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4200
+CONFIG_ENV_OFFSET=0x4200
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_ENV_SECT_SIZE=0x210
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_DATAFLASH_CS3"
CONFIG_BOOTDELAY=3
@@ -39,6 +42,7 @@
CONFIG_AT91_GPIO=y
# CONFIG_MMC is not set
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/at91sam9g10ek_nandflash_defconfig b/configs/at91sam9g10ek_nandflash_defconfig
index f498def..029cc9b 100644
--- a/configs/at91sam9g10ek_nandflash_defconfig
+++ b/configs/at91sam9g10ek_nandflash_defconfig
@@ -37,6 +37,7 @@
CONFIG_AT91_GPIO=y
# CONFIG_MMC is not set
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/at91sam9g20ek_2mmc_defconfig b/configs/at91sam9g20ek_2mmc_defconfig
index abc7661..1c9cc0c 100644
--- a/configs/at91sam9g20ek_2mmc_defconfig
+++ b/configs/at91sam9g20ek_2mmc_defconfig
@@ -1,8 +1,11 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
@@ -38,6 +41,7 @@
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/at91sam9g20ek_2mmc_nandflash_defconfig b/configs/at91sam9g20ek_2mmc_nandflash_defconfig
index cf44706..a0a1499 100644
--- a/configs/at91sam9g20ek_2mmc_nandflash_defconfig
+++ b/configs/at91sam9g20ek_2mmc_nandflash_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_TARGET_AT91SAM9260EK=y
@@ -38,6 +39,7 @@
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/at91sam9g20ek_dataflash_cs0_defconfig b/configs/at91sam9g20ek_dataflash_cs0_defconfig
index 73146fd..86c7116 100644
--- a/configs/at91sam9g20ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9g20ek_dataflash_cs0_defconfig
@@ -1,12 +1,16 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4200
+CONFIG_ENV_OFFSET=0x4200
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
+CONFIG_ENV_SECT_SIZE=0x210
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS0"
CONFIG_BOOTDELAY=3
@@ -38,6 +42,7 @@
CONFIG_AT91_GPIO=y
# CONFIG_MMC is not set
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/at91sam9g20ek_dataflash_cs1_defconfig b/configs/at91sam9g20ek_dataflash_cs1_defconfig
index 127e3ad..c1c7b21 100644
--- a/configs/at91sam9g20ek_dataflash_cs1_defconfig
+++ b/configs/at91sam9g20ek_dataflash_cs1_defconfig
@@ -1,12 +1,16 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4200
+CONFIG_ENV_OFFSET=0x4200
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
+CONFIG_ENV_SECT_SIZE=0x210
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS1"
CONFIG_BOOTDELAY=3
@@ -38,6 +42,7 @@
CONFIG_AT91_GPIO=y
# CONFIG_MMC is not set
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/at91sam9g20ek_nandflash_defconfig b/configs/at91sam9g20ek_nandflash_defconfig
index 73a967d..d8535b6 100644
--- a/configs/at91sam9g20ek_nandflash_defconfig
+++ b/configs/at91sam9g20ek_nandflash_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_TARGET_AT91SAM9260EK=y
@@ -36,6 +37,7 @@
CONFIG_AT91_GPIO=y
# CONFIG_MMC is not set
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/at91sam9m10g45ek_mmc_defconfig b/configs/at91sam9m10g45ek_mmc_defconfig
index 039f4c1..a5b6f45 100644
--- a/configs/at91sam9m10g45ek_mmc_defconfig
+++ b/configs/at91sam9m10g45ek_mmc_defconfig
@@ -3,6 +3,7 @@
CONFIG_SYS_TEXT_BASE=0x73f00000
CONFIG_TARGET_AT91SAM9M10G45EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xffffee00
@@ -40,6 +41,7 @@
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_ETH=y
CONFIG_MACB=y
diff --git a/configs/at91sam9m10g45ek_nandflash_defconfig b/configs/at91sam9m10g45ek_nandflash_defconfig
index 21fb3f0..44c5073 100644
--- a/configs/at91sam9m10g45ek_nandflash_defconfig
+++ b/configs/at91sam9m10g45ek_nandflash_defconfig
@@ -39,6 +39,7 @@
CONFIG_AT91_GPIO=y
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_ETH=y
CONFIG_MACB=y
diff --git a/configs/at91sam9n12ek_mmc_defconfig b/configs/at91sam9n12ek_mmc_defconfig
index a20f575b..aad6ee4 100644
--- a/configs/at91sam9n12ek_mmc_defconfig
+++ b/configs/at91sam9n12ek_mmc_defconfig
@@ -3,6 +3,7 @@
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_AT91SAM9N12EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
@@ -40,6 +41,7 @@
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/at91sam9n12ek_nandflash_defconfig b/configs/at91sam9n12ek_nandflash_defconfig
index a54e8f0..a2cb37e 100644
--- a/configs/at91sam9n12ek_nandflash_defconfig
+++ b/configs/at91sam9n12ek_nandflash_defconfig
@@ -39,6 +39,7 @@
CONFIG_AT91_GPIO=y
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig
index a1caaeb..e49a90d 100644
--- a/configs/at91sam9n12ek_spiflash_defconfig
+++ b/configs/at91sam9n12ek_spiflash_defconfig
@@ -3,10 +3,13 @@
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_AT91SAM9N12EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x3000
+CONFIG_ENV_OFFSET=0x5000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
+CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DEBUG_UART=y
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
@@ -40,6 +43,7 @@
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/at91sam9rlek_dataflash_defconfig b/configs/at91sam9rlek_dataflash_defconfig
index 4f2818f..85130d7 100644
--- a/configs/at91sam9rlek_dataflash_defconfig
+++ b/configs/at91sam9rlek_dataflash_defconfig
@@ -1,12 +1,16 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21F00000
CONFIG_TARGET_AT91SAM9RLEK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4200
+CONFIG_ENV_OFFSET=0x4200
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_ENV_SECT_SIZE=0x210
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_DATAFLASH"
CONFIG_BOOTDELAY=3
@@ -41,6 +45,7 @@
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/at91sam9rlek_mmc_defconfig b/configs/at91sam9rlek_mmc_defconfig
index 807a47b..3835763 100644
--- a/configs/at91sam9rlek_mmc_defconfig
+++ b/configs/at91sam9rlek_mmc_defconfig
@@ -1,8 +1,10 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21F00000
CONFIG_TARGET_AT91SAM9RLEK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
@@ -39,6 +41,7 @@
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/at91sam9rlek_nandflash_defconfig b/configs/at91sam9rlek_nandflash_defconfig
index 1666592..41a5989 100644
--- a/configs/at91sam9rlek_nandflash_defconfig
+++ b/configs/at91sam9rlek_nandflash_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21F00000
CONFIG_TARGET_AT91SAM9RLEK=y
@@ -39,6 +40,7 @@
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/at91sam9x5ek_dataflash_defconfig b/configs/at91sam9x5ek_dataflash_defconfig
index c45970b..10df644 100644
--- a/configs/at91sam9x5ek_dataflash_defconfig
+++ b/configs/at91sam9x5ek_dataflash_defconfig
@@ -3,10 +3,13 @@
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_AT91SAM9X5EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4200
+CONFIG_ENV_OFFSET=0x4200
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
+CONFIG_ENV_SECT_SIZE=0x210
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_USE_DATAFLASH"
@@ -42,6 +45,7 @@
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/at91sam9x5ek_mmc_defconfig b/configs/at91sam9x5ek_mmc_defconfig
index 63ddf75..158c1ec 100644
--- a/configs/at91sam9x5ek_mmc_defconfig
+++ b/configs/at91sam9x5ek_mmc_defconfig
@@ -3,6 +3,7 @@
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_AT91SAM9X5EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
@@ -42,6 +43,7 @@
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/at91sam9x5ek_nandflash_defconfig b/configs/at91sam9x5ek_nandflash_defconfig
index 7d51725..b5c282d 100644
--- a/configs/at91sam9x5ek_nandflash_defconfig
+++ b/configs/at91sam9x5ek_nandflash_defconfig
@@ -41,6 +41,7 @@
CONFIG_AT91_GPIO=y
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig
index 65f3175..1fe37f9 100644
--- a/configs/at91sam9x5ek_spiflash_defconfig
+++ b/configs/at91sam9x5ek_spiflash_defconfig
@@ -3,10 +3,13 @@
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_AT91SAM9X5EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x3000
+CONFIG_ENV_OFFSET=0x5000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
+CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SPI_BOOT=y
@@ -42,6 +45,7 @@
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/at91sam9xeek_dataflash_cs0_defconfig b/configs/at91sam9xeek_dataflash_cs0_defconfig
index 80cbb9e..c713735 100644
--- a/configs/at91sam9xeek_dataflash_cs0_defconfig
+++ b/configs/at91sam9xeek_dataflash_cs0_defconfig
@@ -1,12 +1,16 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4200
+CONFIG_ENV_OFFSET=0x4200
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
+CONFIG_ENV_SECT_SIZE=0x210
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS0"
CONFIG_BOOTDELAY=3
@@ -38,6 +42,7 @@
CONFIG_AT91_GPIO=y
# CONFIG_MMC is not set
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/at91sam9xeek_dataflash_cs1_defconfig b/configs/at91sam9xeek_dataflash_cs1_defconfig
index 4f19edc..1862fc4 100644
--- a/configs/at91sam9xeek_dataflash_cs1_defconfig
+++ b/configs/at91sam9xeek_dataflash_cs1_defconfig
@@ -1,12 +1,16 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4200
+CONFIG_ENV_OFFSET=0x4200
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=132000000
+CONFIG_ENV_SECT_SIZE=0x210
CONFIG_DEBUG_UART=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS1"
CONFIG_BOOTDELAY=3
@@ -38,6 +42,7 @@
CONFIG_AT91_GPIO=y
# CONFIG_MMC is not set
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/at91sam9xeek_nandflash_defconfig b/configs/at91sam9xeek_nandflash_defconfig
index c566904..110b179 100644
--- a/configs/at91sam9xeek_nandflash_defconfig
+++ b/configs/at91sam9xeek_nandflash_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_TARGET_AT91SAM9260EK=y
@@ -36,6 +37,7 @@
CONFIG_AT91_GPIO=y
# CONFIG_MMC is not set
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/avnet_ultra96_rev1_defconfig b/configs/avnet_ultra96_rev1_defconfig
index b504332..feffcc0 100644
--- a/configs/avnet_ultra96_rev1_defconfig
+++ b/configs/avnet_ultra96_rev1_defconfig
@@ -8,12 +8,12 @@
CONFIG_ZYNQ_SDHCI_MAX_FREQ=15000000
CONFIG_ZYNQMP_USB=y
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
diff --git a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig
new file mode 100644
index 0000000..31e1bda
--- /dev/null
+++ b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig
@@ -0,0 +1,64 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_ZYNQMP_TWO_SDHCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0xfffc0000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_BOOTDELAY=0
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SYS_PROMPT="ZynqMP> "
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK_ZYNQMP=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xfa
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_SPI=y
+CONFIG_ZYNQMP_GQSPI=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/axm_defconfig b/configs/axm_defconfig
index 73febdf..a1d374a 100644
--- a/configs/axm_defconfig
+++ b/configs/axm_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_SYS_THUMB_BUILD=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
@@ -11,6 +12,7 @@
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_OFFSET=0x100000
CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
@@ -19,7 +21,6 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x1000
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2068"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
@@ -28,7 +29,6 @@
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-# CONFIG_TPL_BANNER_PRINT is not set
CONFIG_SPL_CRC32_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
@@ -58,6 +58,7 @@
CONFIG_CLK_AT91=y
# CONFIG_MMC is not set
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
@@ -70,6 +71,5 @@
CONFIG_ATMEL_USART=y
CONFIG_WDT=y
CONFIG_WDT_AT91=y
-CONFIG_USE_TINY_PRINTF=y
CONFIG_HEXDUMP=y
# CONFIG_EFI_LOADER is not set
diff --git a/configs/ba10_tv_box_defconfig b/configs/ba10_tv_box_defconfig
index 49aa22c..a384399 100644
--- a/configs/ba10_tv_box_defconfig
+++ b/configs/ba10_tv_box_defconfig
@@ -9,7 +9,7 @@
CONFIG_USB2_VBUS_PIN="PH12"
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/bananapi_m1_plus_defconfig b/configs/bananapi_m1_plus_defconfig
index 96c3023..549d13e 100644
--- a/configs/bananapi_m1_plus_defconfig
+++ b/configs/bananapi_m1_plus_defconfig
@@ -9,7 +9,7 @@
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/bananapi_m2_berry_defconfig b/configs/bananapi_m2_berry_defconfig
index 36a2fce..75fd0b1 100644
--- a/configs/bananapi_m2_berry_defconfig
+++ b/configs/bananapi_m2_berry_defconfig
@@ -7,7 +7,7 @@
CONFIG_MMC0_CD_PIN="PH13"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
CONFIG_DEFAULT_DEVICE_TREE="sun8i-v40-bananapi-m2-berry"
diff --git a/configs/bananapi_m2_plus_h3_defconfig b/configs/bananapi_m2_plus_h3_defconfig
index f45fd5e..fbfa273 100644
--- a/configs/bananapi_m2_plus_h3_defconfig
+++ b/configs/bananapi_m2_plus_h3_defconfig
@@ -7,7 +7,7 @@
CONFIG_MACPWR="PD6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/bananapi_m2_plus_h5_defconfig b/configs/bananapi_m2_plus_h5_defconfig
index f7e23d4..3bc8313 100644
--- a/configs/bananapi_m2_plus_h5_defconfig
+++ b/configs/bananapi_m2_plus_h5_defconfig
@@ -7,7 +7,7 @@
CONFIG_MACPWR="PD6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x10060
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/bananapi_m2_zero_defconfig b/configs/bananapi_m2_zero_defconfig
index 93d4880..933ec4d 100644
--- a/configs/bananapi_m2_zero_defconfig
+++ b/configs/bananapi_m2_zero_defconfig
@@ -5,7 +5,7 @@
CONFIG_DRAM_CLK=408
CONFIG_MMC0_CD_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/bananapi_m64_defconfig b/configs/bananapi_m64_defconfig
index 06d90dd..498b660 100644
--- a/configs/bananapi_m64_defconfig
+++ b/configs/bananapi_m64_defconfig
@@ -7,7 +7,7 @@
CONFIG_MMC0_CD_PIN="PH13"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x10060
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig
index 5292ef9..a125f78 100644
--- a/configs/bayleybay_defconfig
+++ b/configs/bayleybay_defconfig
@@ -14,6 +14,7 @@
CONFIG_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
diff --git a/configs/bcm11130_defconfig b/configs/bcm11130_defconfig
index f13c277..dc7d723 100644
--- a/configs/bcm11130_defconfig
+++ b/configs/bcm11130_defconfig
@@ -11,6 +11,7 @@
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_ASKENV=y
+CONFIG_MX_CYCLIC=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
diff --git a/configs/bcm11130_nand_defconfig b/configs/bcm11130_nand_defconfig
index 2d941f3..aa4105d 100644
--- a/configs/bcm11130_nand_defconfig
+++ b/configs/bcm11130_nand_defconfig
@@ -10,6 +10,7 @@
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_ASKENV=y
+CONFIG_MX_CYCLIC=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
diff --git a/configs/bcm23550_w1d_defconfig b/configs/bcm23550_w1d_defconfig
index baffb2d..b94b2db 100644
--- a/configs/bcm23550_w1d_defconfig
+++ b/configs/bcm23550_w1d_defconfig
@@ -13,6 +13,7 @@
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_ASKENV=y
+CONFIG_MX_CYCLIC=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
diff --git a/configs/bcm28155_ap_defconfig b/configs/bcm28155_ap_defconfig
index d64c7b0..f04e364 100644
--- a/configs/bcm28155_ap_defconfig
+++ b/configs/bcm28155_ap_defconfig
@@ -12,6 +12,7 @@
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_ASKENV=y
+CONFIG_MX_CYCLIC=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
diff --git a/configs/bcm28155_w1d_defconfig b/configs/bcm28155_w1d_defconfig
index 7972e27..9f3020c 100644
--- a/configs/bcm28155_w1d_defconfig
+++ b/configs/bcm28155_w1d_defconfig
@@ -11,6 +11,7 @@
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_ASKENV=y
+CONFIG_MX_CYCLIC=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
diff --git a/configs/bcm7260_defconfig b/configs/bcm7260_defconfig
index 6e0266b..2c18d36 100644
--- a/configs/bcm7260_defconfig
+++ b/configs/bcm7260_defconfig
@@ -6,6 +6,8 @@
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_BOOTDELAY=1
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="fdt addr ${fdtcontroladdr};fdt move ${fdtcontroladdr} ${fdtsaveaddr};fdt addr ${fdtsaveaddr};"
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot>"
CONFIG_EFI_PARTITION=y
diff --git a/configs/bcm7445_defconfig b/configs/bcm7445_defconfig
index f22b06e..c79de19 100644
--- a/configs/bcm7445_defconfig
+++ b/configs/bcm7445_defconfig
@@ -6,6 +6,8 @@
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_BOOTDELAY=1
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="fdt addr ${fdtcontroladdr};fdt move ${fdtcontroladdr} ${fdtsaveaddr};fdt addr ${fdtsaveaddr};"
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot>"
CONFIG_CMD_SF=y
diff --git a/configs/bcm911360_entphn-ns_defconfig b/configs/bcm911360_entphn-ns_defconfig
index be8a90e..673c0f2 100644
--- a/configs/bcm911360_entphn-ns_defconfig
+++ b/configs/bcm911360_entphn-ns_defconfig
@@ -11,6 +11,7 @@
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_ASKENV=y
+CONFIG_MX_CYCLIC=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
diff --git a/configs/bcm911360_entphn_defconfig b/configs/bcm911360_entphn_defconfig
index ba81847..723482e 100644
--- a/configs/bcm911360_entphn_defconfig
+++ b/configs/bcm911360_entphn_defconfig
@@ -11,6 +11,7 @@
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_ASKENV=y
+CONFIG_MX_CYCLIC=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
diff --git a/configs/bcm911360k_defconfig b/configs/bcm911360k_defconfig
index 132234c..dfb9f84 100644
--- a/configs/bcm911360k_defconfig
+++ b/configs/bcm911360k_defconfig
@@ -11,6 +11,7 @@
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_ASKENV=y
+CONFIG_MX_CYCLIC=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
diff --git a/configs/bcm958300k-ns_defconfig b/configs/bcm958300k-ns_defconfig
index d95ef15..cc51053 100644
--- a/configs/bcm958300k-ns_defconfig
+++ b/configs/bcm958300k-ns_defconfig
@@ -11,6 +11,7 @@
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_ASKENV=y
+CONFIG_MX_CYCLIC=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
diff --git a/configs/bcm958300k_defconfig b/configs/bcm958300k_defconfig
index 132234c..dfb9f84 100644
--- a/configs/bcm958300k_defconfig
+++ b/configs/bcm958300k_defconfig
@@ -11,6 +11,7 @@
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_ASKENV=y
+CONFIG_MX_CYCLIC=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
diff --git a/configs/bcm958305k_defconfig b/configs/bcm958305k_defconfig
index 132234c..dfb9f84 100644
--- a/configs/bcm958305k_defconfig
+++ b/configs/bcm958305k_defconfig
@@ -11,6 +11,7 @@
# CONFIG_AUTOBOOT is not set
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_ASKENV=y
+CONFIG_MX_CYCLIC=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
diff --git a/configs/bcm958622hr_defconfig b/configs/bcm958622hr_defconfig
index d5cb7f6..5ee8c69 100644
--- a/configs/bcm958622hr_defconfig
+++ b/configs/bcm958622hr_defconfig
@@ -12,6 +12,7 @@
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_ASKENV=y
CONFIG_CRC32_VERIFY=y
+CONFIG_MX_CYCLIC=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
diff --git a/configs/bcm963158_ram_defconfig b/configs/bcm963158_ram_defconfig
index dfd6906..1d8a81e 100644
--- a/configs/bcm963158_ram_defconfig
+++ b/configs/bcm963158_ram_defconfig
@@ -3,16 +3,14 @@
CONFIG_ARCH_BCM63158=y
CONFIG_SYS_TEXT_BASE=0x10000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
CONFIG_NR_DRAM_BANKS=1
CONFIG_TARGET_BCM963158=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x400
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
@@ -41,7 +39,6 @@
CONFIG_NAND_BRCMNAND=y
CONFIG_NAND_BRCMNAND_63158=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
-# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_CONS_INDEX=0
CONFIG_DM_SERIAL=y
CONFIG_SERIAL_SEARCH_ALL=y
diff --git a/configs/bcm968380gerg_ram_defconfig b/configs/bcm968380gerg_ram_defconfig
index ae9c681..368f674 100644
--- a/configs/bcm968380gerg_ram_defconfig
+++ b/configs/bcm968380gerg_ram_defconfig
@@ -48,7 +48,6 @@
CONFIG_BCM6328_POWER_DOMAIN=y
CONFIG_DM_RESET=y
CONFIG_RESET_BCM6345=y
-# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DM_SERIAL=y
CONFIG_BCM6345_SERIAL=y
CONFIG_SYSRESET_WATCHDOG=y
diff --git a/configs/bcm968580xref_ram_defconfig b/configs/bcm968580xref_ram_defconfig
index d331e4e..62f9077 100644
--- a/configs/bcm968580xref_ram_defconfig
+++ b/configs/bcm968580xref_ram_defconfig
@@ -2,15 +2,13 @@
CONFIG_ARCH_BCM6858=y
CONFIG_SYS_TEXT_BASE=0x10000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
CONFIG_NR_DRAM_BANKS=1
CONFIG_TARGET_BCM968580XREF=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x400
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
@@ -36,7 +34,6 @@
CONFIG_NAND_BRCMNAND=y
CONFIG_NAND_BRCMNAND_6858=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
-# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_CONS_INDEX=0
CONFIG_DM_SERIAL=y
CONFIG_SERIAL_SEARCH_ALL=y
diff --git a/configs/beaver_defconfig b/configs/beaver_defconfig
index ec0850d..2af8e2c 100644
--- a/configs/beaver_defconfig
+++ b/configs/beaver_defconfig
@@ -4,10 +4,10 @@
CONFIG_NR_DRAM_BANKS=2
CONFIG_TEGRA30=y
CONFIG_TARGET_BEAVER=y
+CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
-CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_SYS_PROMPT="Tegra30 (Beaver) # "
# CONFIG_CMD_IMI is not set
CONFIG_CMD_DFU=y
diff --git a/configs/beelink_gs1_defconfig b/configs/beelink_gs1_defconfig
index f16d0fe..c89fba5 100644
--- a/configs/beelink_gs1_defconfig
+++ b/configs/beelink_gs1_defconfig
@@ -3,14 +3,17 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_MACH_SUN50I_H6=y
+CONFIG_SUNXI_DRAM_H6_LPDDR3=y
CONFIG_MMC0_CD_PIN="PF6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_PSCI_RESET is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x20060
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-beelink-gs1"
CONFIG_LED=y
CONFIG_LED_GPIO=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
diff --git a/configs/beelink_x2_defconfig b/configs/beelink_x2_defconfig
new file mode 100644
index 0000000..7c62944
--- /dev/null
+++ b/configs/beelink_x2_defconfig
@@ -0,0 +1,15 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_SPL=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=567
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
+# CONFIG_CMD_FLASH is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-beelink-x2"
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/bg0900_defconfig b/configs/bg0900_defconfig
index 353790f..32dcb25 100644
--- a/configs/bg0900_defconfig
+++ b/configs/bg0900_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x00001000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200"
@@ -16,7 +17,6 @@
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_TEXT_BASE=0x00001000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
@@ -27,6 +27,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_DOS_PARTITION=y
+CONFIG_MXS_GPIO=y
# CONFIG_MMC is not set
CONFIG_NAND=y
CONFIG_NAND_MXS=y
diff --git a/configs/birdland_bav335a_defconfig b/configs/birdland_bav335a_defconfig
index eea1223..422d093 100644
--- a/configs/birdland_bav335a_defconfig
+++ b/configs/birdland_bav335a_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
diff --git a/configs/birdland_bav335b_defconfig b/configs/birdland_bav335b_defconfig
index 7358fe5..5b4f9b7 100644
--- a/configs/birdland_bav335b_defconfig
+++ b/configs/birdland_bav335b_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
diff --git a/configs/bitmain_antminer_s9_defconfig b/configs/bitmain_antminer_s9_defconfig
index 7f432e5..14f8d76 100644
--- a/configs/bitmain_antminer_s9_defconfig
+++ b/configs/bitmain_antminer_s9_defconfig
@@ -18,6 +18,7 @@
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/bk4r1_defconfig b/configs/bk4r1_defconfig
index 7c455d2..20d3e33 100644
--- a/configs/bk4r1_defconfig
+++ b/configs/bk4r1_defconfig
@@ -10,6 +10,7 @@
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_ELF is not set
@@ -52,7 +53,7 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_NAND_VF610_NFC=y
CONFIG_NAND_VF610_NFC_DT=y
@@ -71,8 +72,6 @@
CONFIG_PINCTRL_VYBRID=y
CONFIG_DM_RTC=y
CONFIG_RTC_M41T62=y
-# CONFIG_SPL_SERIAL_PRESENT is not set
-# CONFIG_TPL_SERIAL_PRESENT is not set
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_SPI=y
diff --git a/configs/blanche_defconfig b/configs/blanche_defconfig
index c2d53a3..58ee355 100644
--- a/configs/blanche_defconfig
+++ b/configs/blanche_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0x00000000
diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig
index b5d7b7c..d0ee619 100644
--- a/configs/brppt1_mmc_defconfig
+++ b/configs/brppt1_mmc_defconfig
@@ -8,15 +8,18 @@
CONFIG_TARGET_BRPPT1=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x40000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x0
# CONFIG_EXPERT is not set
# CONFIG_FIT is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=0
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run b_default"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="run cfgscr; run brdefaultip"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
diff --git a/configs/brppt1_nand_defconfig b/configs/brppt1_nand_defconfig
index 2d93c89..ff227de 100644
--- a/configs/brppt1_nand_defconfig
+++ b/configs/brppt1_nand_defconfig
@@ -7,15 +7,18 @@
CONFIG_AM33XX=y
CONFIG_TARGET_BRPPT1=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x60000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x0
# CONFIG_EXPERT is not set
# CONFIG_FIT is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=0
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run b_default"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="run cfgscr; run brdefaultip"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
diff --git a/configs/brppt1_spi_defconfig b/configs/brppt1_spi_defconfig
index 28856ab..a29dc03 100644
--- a/configs/brppt1_spi_defconfig
+++ b/configs/brppt1_spi_defconfig
@@ -7,11 +7,13 @@
CONFIG_AM33XX=y
CONFIG_TARGET_BRPPT1=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x20000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
+CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x0
# CONFIG_EXPERT is not set
# CONFIG_FIT is not set
CONFIG_OF_BOARD_SETUP=y
@@ -19,6 +21,8 @@
CONFIG_BOOTDELAY=0
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run b_default"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="run cfgscr; run brdefaultip"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
@@ -33,6 +37,7 @@
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/brsmarc1_defconfig b/configs/brsmarc1_defconfig
new file mode 100644
index 0000000..d0faa40
--- /dev/null
+++ b/configs/brsmarc1_defconfig
@@ -0,0 +1,111 @@
+CONFIG_ARM=y
+CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_AM33XX=y
+CONFIG_SYS_MPUCLK=600
+CONFIG_TARGET_BRSMARC1=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x20000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000
+CONFIG_SPL=y
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+# CONFIG_EXPERT is not set
+# CONFIG_FIT is not set
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=0
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run b_default"
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_ARCH_MISC_INIT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SEPARATE_BSS=y
+# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+CONFIG_SPL_I2C_SUPPORT=y
+# CONFIG_SPL_NAND_SUPPORT is not set
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_BOOTD is not set
+CONFIG_CMD_BOOTZ=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_ITEST is not set
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="am335x-brsmarc1"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+# CONFIG_OF_TRANSLATE is not set
+# CONFIG_SPL_BLK is not set
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_OMAP_HS=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=24000000
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHY_NATSEMI=y
+CONFIG_DM_ETH=y
+CONFIG_DRIVER_TI_CPSW=y
+CONFIG_DM_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_OMAP3_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_TI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_SHA1=y
+CONFIG_SHA256=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/brxre1_defconfig b/configs/brxre1_defconfig
index c35c73f..d9b0e32 100644
--- a/configs/brxre1_defconfig
+++ b/configs/brxre1_defconfig
@@ -9,15 +9,18 @@
CONFIG_TARGET_BRXRE1=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x40000
CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000
CONFIG_SPL=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x0
# CONFIG_EXPERT is not set
# CONFIG_FIT is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=0
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev 1; run b_default"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="run cfgscr; run brdefaultip"
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
@@ -26,7 +29,6 @@
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
-# CONFIG_TPL_BANNER_PRINT is not set
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_POWER_SUPPORT=y
@@ -34,6 +36,9 @@
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BOOTD is not set
CONFIG_CMD_BOOTZ=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
@@ -83,7 +88,6 @@
CONFIG_USB_GADGET=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_LCD=y
-# CONFIG_OMAP_WATCHDOG is not set
CONFIG_SPL_TINY_MEMSET=y
# CONFIG_OF_LIBFDT_OVERLAY is not set
# CONFIG_EFI_LOADER is not set
diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig
index 33253b1..51c37e2 100644
--- a/configs/caddy2_defconfig
+++ b/configs/caddy2_defconfig
@@ -111,6 +111,7 @@
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_E1000=y
+CONFIG_RTC_RX8025=y
CONFIG_BAUDRATE=9600
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/cairo_defconfig b/configs/cairo_defconfig
index f26f2c9..21f4aae 100644
--- a/configs/cairo_defconfig
+++ b/configs/cairo_defconfig
@@ -4,12 +4,12 @@
CONFIG_TARGET_OMAP3_CAIRO=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x40200800
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=-2
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_TEXT_BASE=0x40200800
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="Cairo # "
diff --git a/configs/cardhu_defconfig b/configs/cardhu_defconfig
index cc519d0..452ac90 100644
--- a/configs/cardhu_defconfig
+++ b/configs/cardhu_defconfig
@@ -4,10 +4,10 @@
CONFIG_NR_DRAM_BANKS=2
CONFIG_TEGRA30=y
CONFIG_TARGET_CARDHU=y
+CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
-CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_SYS_PROMPT="Tegra30 (Cardhu) # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/cei-tk1-som_defconfig b/configs/cei-tk1-som_defconfig
index 6770140..95a4a6a 100644
--- a/configs/cei-tk1-som_defconfig
+++ b/configs/cei-tk1-som_defconfig
@@ -4,10 +4,10 @@
CONFIG_NR_DRAM_BANKS=2
CONFIG_TEGRA124=y
CONFIG_TARGET_CEI_TK1_SOM=y
+CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
-CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_SYS_PROMPT="Tegra124 (TK1-SOM) # "
# CONFIG_CMD_IMI is not set
CONFIG_CMD_DFU=y
diff --git a/configs/cgtqmx6eval_defconfig b/configs/cgtqmx6eval_defconfig
index 0a6ff20..0973411 100644
--- a/configs/cgtqmx6eval_defconfig
+++ b/configs/cgtqmx6eval_defconfig
@@ -12,6 +12,7 @@
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
@@ -21,10 +22,10 @@
CONFIG_MISC_INIT_R=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="CGT-QMX6-Quad U-Boot > "
@@ -55,7 +56,7 @@
CONFIG_DFU_SF=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
diff --git a/configs/cherryhill_defconfig b/configs/cherryhill_defconfig
index 3cbc949..6ab336f 100644
--- a/configs/cherryhill_defconfig
+++ b/configs/cherryhill_defconfig
@@ -8,6 +8,7 @@
CONFIG_DEBUG_UART=y
CONFIG_SMP=y
CONFIG_GENERATE_MP_TABLE=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
diff --git a/configs/chiliboard_defconfig b/configs/chiliboard_defconfig
index 944dd0d..f275d21 100644
--- a/configs/chiliboard_defconfig
+++ b/configs/chiliboard_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
@@ -6,6 +7,8 @@
CONFIG_TARGET_CHILIBOARD=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x20000
CONFIG_SPL=y
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig
index 1a34309..6a1ea04 100644
--- a/configs/chromebit_mickey_defconfig
+++ b/configs/chromebit_mickey_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARM=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00100000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3288=y
# CONFIG_SPL_MMC_SUPPORT is not set
CONFIG_TARGET_CHROMEBIT_MICKEY=y
@@ -12,14 +12,19 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
-# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_SPL_TEXT_BASE=0xff704000
+CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-mickey.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0xff704000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_CRC32_SUPPORT is not set
+CONFIG_SPL_PAYLOAD="u-boot.img"
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
@@ -39,16 +44,15 @@
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-mickey"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_OF_PLATDATA=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
# CONFIG_SPL_SIMPLE_BUS is not set
+# CONFIG_SPL_BLK is not set
CONFIG_CLK=y
CONFIG_SPL_CLK=y
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_I2C_CROS_EC_TUNNEL=y
CONFIG_SYS_I2C_ROCKCHIP=y
@@ -58,12 +62,18 @@
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_PWRSEQ=y
+# CONFIG_SPL_DM_MMC is not set
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=2
CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINMUX is not set
+CONFIG_SPL_PINCONF=y
CONFIG_DM_PMIC=y
# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_PMIC_RK8XX=y
@@ -77,17 +87,14 @@
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
+CONFIG_USB_DWC2=y
CONFIG_ROCKCHIP_USB2_PHY=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
-CONFIG_USB_GADGET_VENDOR_NUM=0x2207
-CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
-CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USB_FUNCTION_MASS_STORAGE=y
CONFIG_DM_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
-CONFIG_USE_TINY_PRINTF=y
+CONFIG_SPL_TINY_MEMSET=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig
index e61e27c..8059c63 100644
--- a/configs/chromebook_bob_defconfig
+++ b/configs/chromebook_bob_defconfig
@@ -2,9 +2,6 @@
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_BOOT_MODE_REG=0
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
@@ -17,13 +14,15 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0xff8c2000
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0xff8c2000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
@@ -79,6 +78,5 @@
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig
index 7c7986e..1b7751c 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -1,10 +1,9 @@
CONFIG_ARM=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00100000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3288=y
# CONFIG_SPL_MMC_SUPPORT is not set
-CONFIG_TARGET_CHROMEBOOK_JERRY=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEBUG_UART_BASE=0xff690000
@@ -12,17 +11,22 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
-# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_SPL_TEXT_BASE=0xff704000
+CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_LOG=y
CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-jerry.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0xff704000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_CRC32_SUPPORT is not set
+CONFIG_SPL_PAYLOAD="u-boot.img"
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
@@ -43,16 +47,15 @@
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-jerry"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_OF_PLATDATA=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
# CONFIG_SPL_SIMPLE_BUS is not set
+# CONFIG_SPL_BLK is not set
CONFIG_CLK=y
CONFIG_SPL_CLK=y
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_I2C_CROS_EC_TUNNEL=y
CONFIG_SYS_I2C_ROCKCHIP=y
@@ -62,12 +65,18 @@
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_PWRSEQ=y
+# CONFIG_SPL_DM_MMC is not set
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=2
CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINMUX is not set
+CONFIG_SPL_PINCONF=y
CONFIG_DM_PMIC=y
# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_PMIC_RK8XX=y
@@ -83,20 +92,17 @@
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
+CONFIG_USB_DWC2=y
CONFIG_ROCKCHIP_USB2_PHY=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
-CONFIG_USB_GADGET_VENDOR_NUM=0x2207
-CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
-CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USB_FUNCTION_MASS_STORAGE=y
CONFIG_DM_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
CONFIG_CONSOLE_TRUETYPE=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_EDP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
# CONFIG_USE_PRIVATE_LIBGCC is not set
-CONFIG_USE_TINY_PRINTF=y
+CONFIG_SPL_TINY_MEMSET=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig
index 67526e8..34805f7 100644
--- a/configs/chromebook_link64_defconfig
+++ b/configs/chromebook_link64_defconfig
@@ -11,17 +11,18 @@
CONFIG_HAVE_MRC=y
CONFIG_SMP=y
CONFIG_HAVE_VGA_BIOS=y
+CONFIG_SPL_TEXT_BASE=0xfffd0000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_MISC_INIT_R=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
-CONFIG_SPL_TEXT_BASE=0xfffd0000
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_CPU_SUPPORT=y
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig
index c3c29d3..340ab15 100644
--- a/configs/chromebook_link_defconfig
+++ b/configs/chromebook_link_defconfig
@@ -14,6 +14,7 @@
CONFIG_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig
index 17c1ea6..28ae618 100644
--- a/configs/chromebook_minnie_defconfig
+++ b/configs/chromebook_minnie_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARM=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00100000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3288=y
# CONFIG_SPL_MMC_SUPPORT is not set
CONFIG_TARGET_CHROMEBOOK_MINNIE=y
@@ -12,15 +12,20 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
-# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_SPL_TEXT_BASE=0xff704000
+CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-minnie.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0xff704000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_CRC32_SUPPORT is not set
+CONFIG_SPL_PAYLOAD="u-boot.img"
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
@@ -41,16 +46,15 @@
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-minnie"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_OF_PLATDATA=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
# CONFIG_SPL_SIMPLE_BUS is not set
+# CONFIG_SPL_BLK is not set
CONFIG_CLK=y
CONFIG_SPL_CLK=y
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_I2C_CROS_EC_TUNNEL=y
CONFIG_SYS_I2C_ROCKCHIP=y
@@ -60,12 +64,18 @@
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_PWRSEQ=y
+# CONFIG_SPL_DM_MMC is not set
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=2
CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINMUX is not set
+CONFIG_SPL_PINCONF=y
CONFIG_DM_PMIC=y
# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_PMIC_RK8XX=y
@@ -82,19 +92,16 @@
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
+CONFIG_USB_DWC2=y
CONFIG_ROCKCHIP_USB2_PHY=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
-CONFIG_USB_GADGET_VENDOR_NUM=0x2207
-CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
-CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USB_FUNCTION_MASS_STORAGE=y
CONFIG_DM_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_EDP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
CONFIG_CONSOLE_SCROLL_LINES=10
-CONFIG_USE_TINY_PRINTF=y
+CONFIG_SPL_TINY_MEMSET=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
diff --git a/configs/chromebook_samus_defconfig b/configs/chromebook_samus_defconfig
index 522e60b..43264ab 100644
--- a/configs/chromebook_samus_defconfig
+++ b/configs/chromebook_samus_defconfig
@@ -14,6 +14,7 @@
CONFIG_HAVE_VGA_BIOS=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
diff --git a/configs/chromebook_samus_tpl_defconfig b/configs/chromebook_samus_tpl_defconfig
index 3b2cbdc..28f23cf 100644
--- a/configs/chromebook_samus_tpl_defconfig
+++ b/configs/chromebook_samus_tpl_defconfig
@@ -12,8 +12,10 @@
CONFIG_HAVE_REFCODE=y
CONFIG_SMP=y
CONFIG_HAVE_VGA_BIOS=y
+CONFIG_SPL_TEXT_BASE=0xffe70000
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
@@ -24,7 +26,6 @@
CONFIG_BLOBLIST_SIZE=0x1000
CONFIG_BLOBLIST_ADDR=0xff7c0000
CONFIG_HANDOFF=y
-CONFIG_SPL_TEXT_BASE=0xffe70000
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_NET_SUPPORT=y
CONFIG_SPL_PCI=y
diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig
index 0cc1eb6..0284e31 100644
--- a/configs/chromebook_speedy_defconfig
+++ b/configs/chromebook_speedy_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARM=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00100000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3288=y
# CONFIG_SPL_MMC_SUPPORT is not set
CONFIG_TARGET_CHROMEBOOK_SPEEDY=y
@@ -12,16 +12,21 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
-# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_SPL_TEXT_BASE=0xff704000
+CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-speedy.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0xff704000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_CRC32_SUPPORT is not set
+CONFIG_SPL_PAYLOAD="u-boot.img"
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
@@ -47,11 +52,9 @@
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
# CONFIG_SPL_SIMPLE_BUS is not set
+# CONFIG_SPL_BLK is not set
CONFIG_CLK=y
CONFIG_SPL_CLK=y
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_I2C_CROS_EC_TUNNEL=y
CONFIG_SYS_I2C_ROCKCHIP=y
@@ -61,12 +64,16 @@
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_PWRSEQ=y
+# CONFIG_SPL_DM_MMC is not set
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=2
CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
CONFIG_SPL_PINCTRL=y
-# CONFIG_SPL_PINCTRL_FULL is not set
CONFIG_DM_PMIC=y
# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_PMIC_RK8XX=y
@@ -80,21 +87,17 @@
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
+CONFIG_USB_DWC2=y
CONFIG_ROCKCHIP_USB2_PHY=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
-CONFIG_USB_GADGET_VENDOR_NUM=0x2207
-CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
-CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USB_FUNCTION_MASS_STORAGE=y
CONFIG_DM_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
CONFIG_CONSOLE_TRUETYPE=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_EDP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
# CONFIG_USE_PRIVATE_LIBGCC is not set
-CONFIG_USE_TINY_PRINTF=y
+CONFIG_SPL_TINY_MEMSET=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
-# CONFIG_SPL_OF_LIBFDT is not set
diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig
index a42d726..a37661b 100644
--- a/configs/chromebox_panther_defconfig
+++ b/configs/chromebox_panther_defconfig
@@ -8,6 +8,7 @@
CONFIG_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
diff --git a/configs/ci20_mmc_defconfig b/configs/ci20_mmc_defconfig
index 8a81517..7b2be63 100644
--- a/configs/ci20_mmc_defconfig
+++ b/configs/ci20_mmc_defconfig
@@ -7,6 +7,7 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_ARCH_JZ47XX=y
+CONFIG_SPL_TEXT_BASE=0xf4000a00
CONFIG_FIT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS4,115200 rw rootwait root=/dev/mmcblk0p1"
@@ -15,9 +16,8 @@
CONFIG_MISC_INIT_R=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0xf4000a00
# CONFIG_SPL_BANNER_PRINT is not set
-# CONFIG_TPL_BANNER_PRINT is not set
+CONFIG_SPL_MMC_TINY=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_DM=y
# CONFIG_CMD_FLASH is not set
@@ -39,10 +39,8 @@
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
# CONFIG_MMC_VERBOSE is not set
-CONFIG_SPL_MMC_TINY=y
CONFIG_JZ47XX_MMC=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
-CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_LZO=y
diff --git a/configs/cl-som-imx7_defconfig b/configs/cl-som-imx7_defconfig
index 73c78e2..5914bbd 100644
--- a/configs/cl-som-imx7_defconfig
+++ b/configs/cl-som-imx7_defconfig
@@ -14,11 +14,11 @@
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
+CONFIG_SPL_TEXT_BASE=0x00911000
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_BOUNCE_BUFFER=y
-CONFIG_SPL_TEXT_BASE=0x00911000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80
CONFIG_SPL_I2C_SUPPORT=y
@@ -26,6 +26,9 @@
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="CL-SOM-iMX7 # "
CONFIG_CMD_BOOTZ=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EXPORTENV is not set
@@ -51,7 +54,7 @@
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig
index b7b886b..ebfe3cf 100644
--- a/configs/clearfog_defconfig
+++ b/configs/clearfog_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
@@ -16,12 +17,13 @@
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0x40000030
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0x40000030
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x141
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/clearfog_gt_8k_defconfig b/configs/clearfog_gt_8k_defconfig
index 2f919b5..40f86e5 100644
--- a/configs/clearfog_gt_8k_defconfig
+++ b/configs/clearfog_gt_8k_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
@@ -11,6 +12,7 @@
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
@@ -61,7 +63,6 @@
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ARMADA_8K=y
CONFIG_DM_REGULATOR_FIXED=y
-# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_SYS_NS16550=y
diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig
index ce3f9de..eed0558 100644
--- a/configs/cm_fx6_defconfig
+++ b/configs/cm_fx6_defconfig
@@ -13,17 +13,20 @@
CONFIG_SPL_SPI_SUPPORT=y
# CONFIG_CMD_BMODE is not set
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run legacy_bootcmd"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="usb start;sf probe"
CONFIG_MISC_INIT_R=y
CONFIG_BOUNCE_BUFFER=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SYS_PROMPT="CM-FX6 # "
# CONFIG_CMD_XIMG is not set
@@ -55,7 +58,7 @@
# CONFIG_DWC_AHSATA_AHCI is not set
CONFIG_DM_KEYBOARD=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_SPI_FLASH=y
diff --git a/configs/cm_t335_defconfig b/configs/cm_t335_defconfig
index 3df94d2..ab9f1fd 100644
--- a/configs/cm_t335_defconfig
+++ b/configs/cm_t335_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -7,6 +8,8 @@
CONFIG_TARGET_CM_T335=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x300000
CONFIG_SPL=y
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
diff --git a/configs/cm_t35_defconfig b/configs/cm_t35_defconfig
index f363914..918a848 100644
--- a/configs/cm_t35_defconfig
+++ b/configs/cm_t35_defconfig
@@ -3,12 +3,13 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80008000
CONFIG_TARGET_CM_T35=y
+CONFIG_ENV_SIZE=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x40200800
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SPL_TEXT_BASE=0x40200800
# CONFIG_SPL_FS_EXT4 is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="CM-T3x # "
diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig
index 72b7d36..933c1c5 100644
--- a/configs/cm_t43_defconfig
+++ b/configs/cm_t43_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
@@ -6,11 +7,15 @@
CONFIG_TARGET_CM_T43=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0xc0000
CONFIG_SPL=y
+CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0x40300350
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
@@ -18,7 +23,6 @@
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_TEXT_BASE=0x40300350
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x480
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -26,6 +30,7 @@
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_SYS_PROMPT="CM-T43 # "
CONFIG_CMD_ASKENV=y
CONFIG_CMD_EEPROM=y
@@ -43,12 +48,16 @@
# CONFIG_CMD_NFS is not set
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="am437x-cm-t43"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
CONFIG_DM_GPIO=y
+CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=48000000
CONFIG_SPI_FLASH_ATMEL=y
@@ -63,10 +72,11 @@
CONFIG_DRIVER_TI_CPSW=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_OMAP_USB_PHY=y
CONFIG_FAT_WRITE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/cm_t54_defconfig b/configs/cm_t54_defconfig
index dedc8b5..09c0a36 100644
--- a/configs/cm_t54_defconfig
+++ b/configs/cm_t54_defconfig
@@ -3,7 +3,10 @@
CONFIG_OMAP54XX=y
CONFIG_TARGET_CM_T54=y
CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC=16296
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0xc0000
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x40300000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
@@ -11,7 +14,6 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_MISC_INIT_R is not set
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_TEXT_BASE=0x40300000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_SATA_SUPPORT=y
diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig
index 1c02729..99b3deb 100644
--- a/configs/colibri-imx6ull_defconfig
+++ b/configs/colibri-imx6ull_defconfig
@@ -16,6 +16,8 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_SYS_PROMPT="Colibri iMX6ULL # "
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
@@ -47,15 +49,15 @@
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_BLOCKSIZE=16352
-CONFIG_DFU_MMC=y
CONFIG_DFU_NAND=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_NAND=y
+CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_MXS=y
CONFIG_NAND_MXS_DT=y
CONFIG_MTD_UBI_FASTMAP=y
@@ -68,7 +70,6 @@
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
-# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_USB=y
@@ -79,6 +80,6 @@
CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_VIDEO=y
+CONFIG_DM_VIDEO=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/colibri-imx8qxp_defconfig b/configs/colibri-imx8qxp_defconfig
index 8d6c078..b809905 100644
--- a/configs/colibri-imx8qxp_defconfig
+++ b/configs/colibri-imx8qxp_defconfig
@@ -12,6 +12,7 @@
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
CONFIG_CMD_ASKENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
@@ -34,6 +35,7 @@
CONFIG_SYS_I2C_IMX_LPI2C=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_MICREL=y
diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig
index 56e512d..4f7ca7b 100644
--- a/configs/colibri_imx6_defconfig
+++ b/configs/colibri_imx6_defconfig
@@ -10,6 +10,7 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_CMD_HDMIDETECT=y
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6DL"
@@ -22,7 +23,6 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_USB_HOST_SUPPORT=y
@@ -36,7 +36,6 @@
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
@@ -55,12 +54,11 @@
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_BLOCKSIZE=16352
-CONFIG_DFU_MMC=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig
index e5e4168..a9149dd 100644
--- a/configs/colibri_imx7_defconfig
+++ b/configs/colibri_imx7_defconfig
@@ -19,6 +19,8 @@
CONFIG_BOUNCE_BUFFER=y
CONFIG_SYS_PROMPT="Colibri iMX7 # "
# CONFIG_CMD_BOOTD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
CONFIG_CMD_ASKENV=y
@@ -52,7 +54,7 @@
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_NAND=y
CONFIG_NAND_MXS_DT=y
@@ -74,6 +76,6 @@
CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_VIDEO=y
+CONFIG_DM_VIDEO=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/colibri_imx7_emmc_defconfig b/configs/colibri_imx7_emmc_defconfig
index 06902b6..c5de2e7 100644
--- a/configs/colibri_imx7_emmc_defconfig
+++ b/configs/colibri_imx7_emmc_defconfig
@@ -5,6 +5,7 @@
CONFIG_SECURE_BOOT=y
CONFIG_TARGET_COLIBRI_IMX7=y
CONFIG_TARGET_COLIBRI_IMX7_EMMC=y
+CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
# CONFIG_CMD_DEKBLOB is not set
@@ -19,15 +20,15 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SYS_PROMPT="Colibri iMX7 # "
# CONFIG_CMD_BOOTD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
CONFIG_CMD_ASKENV=y
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
-# CONFIG_RANDOM_UUID is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
@@ -43,7 +44,6 @@
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_BLOCKSIZE=16352
CONFIG_FSL_CAAM=y
-CONFIG_DFU_MMC=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x82000000
CONFIG_FASTBOOT_BUF_SIZE=0x10000000
@@ -54,7 +54,7 @@
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
diff --git a/configs/colibri_pxa270_defconfig b/configs/colibri_pxa270_defconfig
index 7c42058..ab2d185 100644
--- a/configs/colibri_pxa270_defconfig
+++ b/configs/colibri_pxa270_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_TARGET_COLIBRI_PXA270=y
CONFIG_SYS_TEXT_BASE=0x0
CONFIG_SYS_MALLOC_F_LEN=0x2000
diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig
index 170a1b0..262ff9e 100644
--- a/configs/colibri_t20_defconfig
+++ b/configs/colibri_t20_defconfig
@@ -5,15 +5,14 @@
CONFIG_NR_DRAM_BANKS=2
CONFIG_TEGRA20=y
CONFIG_TARGET_COLIBRI_T20=y
+CONFIG_SPL_TEXT_BASE=0x00108000
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_SYS_STDIO_DEREGISTER=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL_TEXT_BASE=0x00108000
CONFIG_SYS_PROMPT="Colibri T20 # "
# CONFIG_CMD_IMI is not set
-CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
@@ -39,8 +38,6 @@
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_BLOCKSIZE=1536
CONFIG_SPL_DM=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_RAM=y
CONFIG_SYS_I2C_TEGRA=y
CONFIG_MTD=y
CONFIG_MTD_UBI_FASTMAP=y
diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig
index 769f6f3..350f717 100644
--- a/configs/colibri_t30_defconfig
+++ b/configs/colibri_t30_defconfig
@@ -5,16 +5,15 @@
CONFIG_NR_DRAM_BANKS=2
CONFIG_TEGRA30=y
CONFIG_TARGET_COLIBRI_T30=y
+CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_SYS_PROMPT="Colibri T30 # "
# CONFIG_CMD_IMI is not set
-CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
@@ -30,8 +29,6 @@
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_BLOCKSIZE=16352
CONFIG_SPL_DM=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_RAM=y
CONFIG_SYS_I2C_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig
index 75498fd..c21efa2 100644
--- a/configs/colibri_vf_defconfig
+++ b/configs/colibri_vf_defconfig
@@ -58,7 +58,7 @@
CONFIG_VYBRID_GPIO=y
CONFIG_DM_MMC=y
# CONFIG_MMC_HW_PARTITIONING is not set
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_NAND_VF610_NFC=y
CONFIG_NAND_VF610_NFC_DT=y
@@ -74,8 +74,6 @@
CONFIG_PINCTRL_VYBRID=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
-# CONFIG_SPL_SERIAL_PRESENT is not set
-# CONFIG_TPL_SERIAL_PRESENT is not set
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_USB=y
@@ -88,9 +86,8 @@
CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_FSL_DCU_FB=y
-CONFIG_VIDEO=y
-CONFIG_SYS_CONSOLE_FG_COL=0x00
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_FDT_FIXUP_PARTITIONS=y
# CONFIG_EFI_UNICODE_CAPITALIZATION is not set
diff --git a/configs/colorfly_e708_q1_defconfig b/configs/colorfly_e708_q1_defconfig
index 7d6cd30..4565308 100644
--- a/configs/colorfly_e708_q1_defconfig
+++ b/configs/colorfly_e708_q1_defconfig
@@ -16,7 +16,7 @@
CONFIG_VIDEO_LCD_BL_PWM="PH13"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/comtrend_ar5315u_ram_defconfig b/configs/comtrend_ar5315u_ram_defconfig
index 940e603..0f26c89 100644
--- a/configs/comtrend_ar5315u_ram_defconfig
+++ b/configs/comtrend_ar5315u_ram_defconfig
@@ -50,7 +50,6 @@
CONFIG_BCM6328_POWER_DOMAIN=y
CONFIG_DM_RESET=y
CONFIG_RESET_BCM6345=y
-# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DM_SERIAL=y
CONFIG_BCM6345_SERIAL=y
CONFIG_SPI=y
diff --git a/configs/comtrend_ar5387un_ram_defconfig b/configs/comtrend_ar5387un_ram_defconfig
index 07aa8dd..3bd6ea7 100644
--- a/configs/comtrend_ar5387un_ram_defconfig
+++ b/configs/comtrend_ar5387un_ram_defconfig
@@ -51,7 +51,6 @@
CONFIG_BCM6328_POWER_DOMAIN=y
CONFIG_DM_RESET=y
CONFIG_RESET_BCM6345=y
-# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DM_SERIAL=y
CONFIG_BCM6345_SERIAL=y
CONFIG_SPI=y
diff --git a/configs/comtrend_ct5361_ram_defconfig b/configs/comtrend_ct5361_ram_defconfig
index 58a721b..41ce399 100644
--- a/configs/comtrend_ct5361_ram_defconfig
+++ b/configs/comtrend_ct5361_ram_defconfig
@@ -49,7 +49,6 @@
CONFIG_BCM6348_USBH_PHY=y
CONFIG_DM_RESET=y
CONFIG_RESET_BCM6345=y
-# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DM_SERIAL=y
CONFIG_BCM6345_SERIAL=y
CONFIG_USB=y
diff --git a/configs/comtrend_vr3032u_ram_defconfig b/configs/comtrend_vr3032u_ram_defconfig
index 013c9ee..34a1502 100644
--- a/configs/comtrend_vr3032u_ram_defconfig
+++ b/configs/comtrend_vr3032u_ram_defconfig
@@ -45,7 +45,6 @@
CONFIG_BCM6328_POWER_DOMAIN=y
CONFIG_DM_RESET=y
CONFIG_RESET_BCM6345=y
-# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DM_SERIAL=y
CONFIG_BCM6345_SERIAL=y
CONFIG_USB=y
diff --git a/configs/comtrend_wap5813n_ram_defconfig b/configs/comtrend_wap5813n_ram_defconfig
index 6e0a645..f466cab 100644
--- a/configs/comtrend_wap5813n_ram_defconfig
+++ b/configs/comtrend_wap5813n_ram_defconfig
@@ -49,7 +49,6 @@
CONFIG_BCM6368_USBH_PHY=y
CONFIG_DM_RESET=y
CONFIG_RESET_BCM6345=y
-# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DM_SERIAL=y
CONFIG_BCM6345_SERIAL=y
CONFIG_USB=y
diff --git a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
index 3383172..3e193ed 100644
--- a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
+++ b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
@@ -19,8 +19,10 @@
CONFIG_FIT_SIGNATURE=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sda2 ro quiet"
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig
index 4fdee99..2e71156 100644
--- a/configs/conga-qeval20-qa3-e3845_defconfig
+++ b/configs/conga-qeval20-qa3-e3845_defconfig
@@ -15,8 +15,10 @@
CONFIG_FIT_SIGNATURE=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sda2 ro quiet"
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
diff --git a/configs/controlcenterdc_defconfig b/configs/controlcenterdc_defconfig
index 326668d..b61982e 100644
--- a/configs/controlcenterdc_defconfig
+++ b/configs/controlcenterdc_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
CONFIG_SPL_GPIO_SUPPORT=y
@@ -13,16 +14,18 @@
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0x40000030
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
-CONFIG_SPL_TEXT_BASE=0x40000030
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x30000
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_GO is not set
diff --git a/configs/coreboot_defconfig b/configs/coreboot_defconfig
index 7fba44f..21ad700 100644
--- a/configs/coreboot_defconfig
+++ b/configs/coreboot_defconfig
@@ -1,14 +1,15 @@
CONFIG_X86=y
CONFIG_SYS_TEXT_BASE=0x1110000
CONFIG_NR_DRAM_BANKS=8
+CONFIG_PRE_CON_BUF_ADDR=0x100000
CONFIG_VENDOR_COREBOOT=y
CONFIG_TARGET_COREBOOT=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_PRE_CONSOLE_BUFFER=y
-CONFIG_PRE_CON_BUF_ADDR=0x100000
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig
index 68c7bec..56c6123 100644
--- a/configs/corvus_defconfig
+++ b/configs/corvus_defconfig
@@ -10,15 +10,16 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_OFFSET=0x100000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x300000
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,MACH_TYPE=2066,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) root=/dev/mtdblock7 rw rootfstype=jffs2"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x300000
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
@@ -46,6 +47,7 @@
CONFIG_DFU_NAND=y
# CONFIG_MMC is not set
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_PHYLIB=y
CONFIG_ATMEL_USART=y
diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig
index b05da76..2fd2b89 100644
--- a/configs/cougarcanyon2_defconfig
+++ b/configs/cougarcanyon2_defconfig
@@ -8,6 +8,7 @@
CONFIG_SMP=y
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_MP_TABLE=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig
index e575040..7beb1ca 100644
--- a/configs/crownbay_defconfig
+++ b/configs/crownbay_defconfig
@@ -9,6 +9,7 @@
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_MP_TABLE=y
CONFIG_FIT=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
diff --git a/configs/crs305-1g-4s_defconfig b/configs/crs305-1g-4s_defconfig
index 26e1c91..c396a7c 100644
--- a/configs/crs305-1g-4s_defconfig
+++ b/configs/crs305-1g-4s_defconfig
@@ -1,10 +1,13 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_CRS305_1G_4S=y
CONFIG_BUILD_TARGET="u-boot.kwb"
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/d2net_v2_defconfig b/configs/d2net_v2_defconfig
index 845565d..b4cf22c 100644
--- a/configs/d2net_v2_defconfig
+++ b/configs/d2net_v2_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NET2BIG_V2=y
@@ -9,6 +10,7 @@
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/da850_am18xxevm_defconfig b/configs/da850_am18xxevm_defconfig
deleted file mode 100644
index 7ecdc36..0000000
--- a/configs/da850_am18xxevm_defconfig
+++ /dev/null
@@ -1,60 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_DAVINCI=y
-CONFIG_SYS_TEXT_BASE=0xc1080000
-CONFIG_TARGET_DA850EVM=y
-CONFIG_MAC_ADDR_IN_EEPROM=y
-CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x800
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SYS_EXTRA_OPTIONS="DA850_AM18X_EVM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50"
-CONFIG_BOOTDELAY=3
-CONFIG_MISC_INIT_R=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x80000000
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="U-Boot > "
-CONFIG_CRC32_VERIFY=y
-# CONFIG_CMD_EEPROM is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_GPIO is not set
-# CONFIG_CMD_GPT is not set
-# CONFIG_CMD_PART is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_TIME is not set
-# CONFIG_CMD_EXT4 is not set
-# CONFIG_CMD_FS_GENERIC is not set
-CONFIG_CMD_DIAG=y
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="da850-evm"
-CONFIG_SPL_OF_PLATDATA=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_DM=y
-CONFIG_SPL_DM=y
-CONFIG_DA8XX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_DM_I2C_COMPAT=y
-CONFIG_SYS_I2C_DAVINCI=y
-CONFIG_MTD_DEVICE=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_MII=y
-CONFIG_DRIVER_TI_EMAC=y
-CONFIG_DM_SERIAL=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_DAVINCI_SPI=y
-# CONFIG_FAT_WRITE is not set
diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig
index c095058..5eb0150 100644
--- a/configs/da850evm_defconfig
+++ b/configs/da850evm_defconfig
@@ -12,6 +12,7 @@
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0x80000000
CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH"
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="da850-evm.dtb"
@@ -20,23 +21,26 @@
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x80000000
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_CRC32_VERIFY=y
+CONFIG_MX_CYCLIC=y
CONFIG_CMD_DM=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPT is not set
+CONFIG_CMD_MTD=y
+# CONFIG_CMD_SF is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_TIME is not set
# CONFIG_CMD_EXT4 is not set
CONFIG_CMD_FS_UUID=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=spi0.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:512k(u-boot.ais),64k(u-boot-env),7552k(kernel-spare),64k(MAC-Address)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:32k(SPL),480k(u-boot),64k(u-boot-env),7552k(kernel-spare),64k(MAC-Address)"
CONFIG_CMD_DIAG=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
@@ -52,6 +56,7 @@
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DAVINCI=y
CONFIG_DM_MMC=y
+CONFIG_MTD=y
CONFIG_MTD_DEVICE=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
@@ -59,8 +64,11 @@
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
+CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_DRIVER_TI_EMAC=y
+CONFIG_PHY=y
+CONFIG_PHY_DA8XX_USB=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_SINGLE=y
CONFIG_DM_SERIAL=y
@@ -73,5 +81,8 @@
# CONFIG_SPL_DM_USB is not set
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_DA8XX=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_DA8XX=y
+CONFIG_USB_MUSB_PIO_ONLY=y
+CONFIG_USB_STORAGE=y
# CONFIG_FAT_WRITE is not set
-CONFIG_USE_TINY_PRINTF=y
diff --git a/configs/da850evm_direct_nor_defconfig b/configs/da850evm_direct_nor_defconfig
index 166e77b..698ac13 100644
--- a/configs/da850evm_direct_nor_defconfig
+++ b/configs/da850evm_direct_nor_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_DAVINCI=y
CONFIG_SYS_TEXT_BASE=0x60000000
CONFIG_TARGET_DA850EVM=y
@@ -20,38 +21,46 @@
# CONFIG_CMD_BOOTZ is not set
CONFIG_CMD_IMLS=y
CONFIG_CRC32_VERIFY=y
+CONFIG_MX_CYCLIC=y
CONFIG_CMD_DM=y
-# CONFIG_CMD_GPIO is not set
# CONFIG_CMD_GPT is not set
# CONFIG_CMD_MMC is not set
+CONFIG_CMD_MTD=y
# CONFIG_CMD_PART is not set
+# CONFIG_CMD_SF is not set
# CONFIG_CMD_SPI is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_TIME is not set
-# CONFIG_CMD_EXT2 is not set
-# CONFIG_CMD_EXT4 is not set
-# CONFIG_CMD_FAT is not set
-# CONFIG_CMD_FS_GENERIC is not set
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nor0=physmap-flash.2"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=physmap-flash.2:1m(u-boot),128k(u-boot-env),-(spare)"
CONFIG_CMD_DIAG=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="da850-evm"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_DM=y
CONFIG_BLK=y
+CONFIG_DM_GPIO=y
CONFIG_DA8XX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DAVINCI=y
# CONFIG_MMC is not set
+CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_DRIVER_TI_EMAC=y
+CONFIG_PHY=y
+CONFIG_PHY_DA8XX_USB=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_SINGLE=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
@@ -60,3 +69,11 @@
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_DAVINCI_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_DA8XX=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_DA8XX=y
+CONFIG_USB_MUSB_PIO_ONLY=y
+CONFIG_USB_STORAGE=y
diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig
index 7271016..063b5b8 100644
--- a/configs/da850evm_nand_defconfig
+++ b/configs/da850evm_nand_defconfig
@@ -11,6 +11,7 @@
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0x80000000
CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH"
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="da850-evm.dtb"
@@ -18,14 +19,15 @@
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x80000000
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_CRC32_VERIFY=y
+CONFIG_MX_CYCLIC=y
CONFIG_CMD_DM=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPT is not set
@@ -49,7 +51,9 @@
CONFIG_DA8XX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+CONFIG_MTD=y
CONFIG_NAND=y
+CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_DAVINCI=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x28000
@@ -59,6 +63,11 @@
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
+CONFIG_DM_ETH=y
+CONFIG_MII=y
+CONFIG_DRIVER_TI_EMAC=y
+CONFIG_PHY=y
+CONFIG_PHY_DA8XX_USB=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_SINGLE=y
CONFIG_DM_SERIAL=y
@@ -66,5 +75,13 @@
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_DAVINCI_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+# CONFIG_SPL_DM_USB is not set
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_DA8XX=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_DA8XX=y
+CONFIG_USB_MUSB_PIO_ONLY=y
+CONFIG_USB_STORAGE=y
# CONFIG_FAT_WRITE is not set
-CONFIG_USE_TINY_PRINTF=y
diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig
index 4802e2d..f660d38 100644
--- a/configs/dalmore_defconfig
+++ b/configs/dalmore_defconfig
@@ -4,10 +4,10 @@
CONFIG_NR_DRAM_BANKS=2
CONFIG_TEGRA114=y
CONFIG_TARGET_DALMORE=y
+CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
-CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_SYS_PROMPT="Tegra114 (Dalmore) # "
# CONFIG_CMD_IMI is not set
CONFIG_CMD_DFU=y
diff --git a/configs/db-88f6281-bp-nand_defconfig b/configs/db-88f6281-bp-nand_defconfig
index ffb24ea..0d04683 100644
--- a/configs/db-88f6281-bp-nand_defconfig
+++ b/configs/db-88f6281-bp-nand_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
diff --git a/configs/db-88f6281-bp-spi_defconfig b/configs/db-88f6281-bp-spi_defconfig
index 4b1b158..01ef497 100644
--- a/configs/db-88f6281-bp-spi_defconfig
+++ b/configs/db-88f6281-bp-spi_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
diff --git a/configs/db-88f6720_defconfig b/configs/db-88f6720_defconfig
index c1a430c..78c0255 100644
--- a/configs/db-88f6720_defconfig
+++ b/configs/db-88f6720_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -13,14 +14,16 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0x40004030
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0x40004030
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_SF=y
diff --git a/configs/db-88f6820-amc_defconfig b/configs/db-88f6820-amc_defconfig
index d55dfc0..3d23c12 100644
--- a/configs/db-88f6820-amc_defconfig
+++ b/configs/db-88f6820-amc_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -13,15 +14,17 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0x40000030
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0x40000030
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x24000
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_PCI=y
@@ -54,6 +57,7 @@
CONFIG_SYS_I2C_MVTWSI=y
# CONFIG_MMC is not set
CONFIG_NAND=y
+CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_PXA3XX=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=1
diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig
index b8f036e..04bfbc4 100644
--- a/configs/db-88f6820-gp_defconfig
+++ b/configs/db-88f6820-gp_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -14,14 +15,16 @@
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0x40000030
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0x40000030
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x24000
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
diff --git a/configs/db-mv784mp-gp_defconfig b/configs/db-mv784mp-gp_defconfig
index 65995b2..265f254 100644
--- a/configs/db-mv784mp-gp_defconfig
+++ b/configs/db-mv784mp-gp_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -13,14 +14,16 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0x40004030
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0x40004030
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_PCI=y
@@ -50,6 +53,7 @@
CONFIG_BLK=y
# CONFIG_MMC is not set
CONFIG_NAND=y
+CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_PXA3XX=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
diff --git a/configs/db-xc3-24g4xg_defconfig b/configs/db-xc3-24g4xg_defconfig
index 6264df0..de34d1f 100644
--- a/configs/db-xc3-24g4xg_defconfig
+++ b/configs/db-xc3-24g4xg_defconfig
@@ -1,9 +1,14 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_DB_XC3_24G4XG=y
CONFIG_BUILD_TARGET="u-boot.kwb"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_FIT_BEST_MATCH=y
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
@@ -33,6 +38,7 @@
CONFIG_MTD=y
CONFIG_MTD_DEVICE=y
CONFIG_NAND=y
+CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_PXA3XX=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig
index a47cf02..bc07eab 100644
--- a/configs/devkit3250_defconfig
+++ b/configs/devkit3250_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_SYS_ICACHE_OFF=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_LPC32XX=y
CONFIG_SYS_TEXT_BASE=0x83F00000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -8,13 +9,13 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x00000000
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200n8"
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x00000000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_NAND_SUPPORT=y
@@ -37,6 +38,7 @@
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_NAND=y
+CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_LPC32XX_SLC=y
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_PHYLIB=y
diff --git a/configs/devkit8000_defconfig b/configs/devkit8000_defconfig
index da09b3a..962cdee 100644
--- a/configs/devkit8000_defconfig
+++ b/configs/devkit8000_defconfig
@@ -4,11 +4,11 @@
CONFIG_TARGET_DEVKIT8000=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_SPL_OS_BOOT=y
# CONFIG_CMD_IMI is not set
CONFIG_CMD_SPL=y
diff --git a/configs/dfi-bt700-q7x-151_defconfig b/configs/dfi-bt700-q7x-151_defconfig
index 111011c..13c5883 100644
--- a/configs/dfi-bt700-q7x-151_defconfig
+++ b/configs/dfi-bt700-q7x-151_defconfig
@@ -14,8 +14,10 @@
CONFIG_FIT_SIGNATURE=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sda1 ro quiet"
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig
index d71bbce..f459af0 100644
--- a/configs/dh_imx6_defconfig
+++ b/configs/dh_imx6_defconfig
@@ -13,17 +13,18 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
+CONFIG_SPL_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_BOUNCE_BUFFER=y
-CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_UNZIP=y
@@ -41,12 +42,18 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-dhcom-pdk2"
+CONFIG_OF_LIST="imx6q-dhcom-pdk2 imx6dl-dhcom-pdk2"
+CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DWC_AHSATA=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
@@ -64,6 +71,8 @@
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_SCSI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
diff --git a/configs/difrnce_dit4350_defconfig b/configs/difrnce_dit4350_defconfig
index 02d233e..7e28dec 100644
--- a/configs/difrnce_dit4350_defconfig
+++ b/configs/difrnce_dit4350_defconfig
@@ -15,7 +15,7 @@
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/display5_defconfig b/configs/display5_defconfig
index 3b793f4..e48b646 100644
--- a/configs/display5_defconfig
+++ b/configs/display5_defconfig
@@ -4,16 +4,19 @@
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x1000
CONFIG_MX6_DDRCAL=y
CONFIG_TARGET_DISPLAY5=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
CONFIG_SYS_BOOTCOUNT_ADDR=0x020CC068
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_OF_BOARD_SETUP=y
@@ -21,7 +24,6 @@
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
CONFIG_BOUNCE_BUFFER=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_BOOTCOUNT_LIMIT=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_DMA_SUPPORT=y
@@ -30,6 +32,7 @@
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="display5 > "
@@ -64,7 +67,7 @@
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_MTD_DEVICE=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=1
diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig
index 0d9eed3..5b79057 100644
--- a/configs/display5_factory_defconfig
+++ b/configs/display5_factory_defconfig
@@ -10,6 +10,7 @@
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
@@ -19,13 +20,13 @@
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
CONFIG_BOUNCE_BUFFER=y
-CONFIG_SPL_TEXT_BASE=0x00908000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_SPL_USB_HOST_SUPPORT=y
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_USB_SDP_SUPPORT=y
@@ -65,7 +66,7 @@
CONFIG_DFU_MMC=y
CONFIG_DFU_SF=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_MTD_DEVICE=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=1
diff --git a/configs/dms-ba16-1g_defconfig b/configs/dms-ba16-1g_defconfig
index 980f7b4..fe23657 100644
--- a/configs/dms-ba16-1g_defconfig
+++ b/configs/dms-ba16-1g_defconfig
@@ -33,7 +33,7 @@
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DWC_AHSATA=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
@@ -41,6 +41,7 @@
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHYLIB=y
CONFIG_MII=y
+CONFIG_PWM_IMX=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
diff --git a/configs/dms-ba16_defconfig b/configs/dms-ba16_defconfig
index bea75b5..a4c93a5 100644
--- a/configs/dms-ba16_defconfig
+++ b/configs/dms-ba16_defconfig
@@ -32,7 +32,7 @@
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DWC_AHSATA=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
@@ -40,6 +40,7 @@
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHYLIB=y
CONFIG_MII=y
+CONFIG_PWM_IMX=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
diff --git a/configs/dns325_defconfig b/configs/dns325_defconfig
index aca8abb..6e95fb2 100644
--- a/configs/dns325_defconfig
+++ b/configs/dns325_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_DNS325=y
@@ -7,6 +8,7 @@
CONFIG_IDENT_STRING="\nD-Link DNS-325"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
diff --git a/configs/dockstar_defconfig b/configs/dockstar_defconfig
index 679c182..18df663 100644
--- a/configs/dockstar_defconfig
+++ b/configs/dockstar_defconfig
@@ -1,11 +1,13 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_DOCKSTAR=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_IDENT_STRING="\nSeagate FreeAgent DockStar"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="DockStar> "
# CONFIG_CMD_FLASH is not set
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 682e301..868030d 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -10,6 +10,7 @@
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ARMV7_LPAE=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0x40300000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_OF_BOARD_SETUP=y
@@ -20,12 +21,12 @@
# CONFIG_MISC_INIT_R is not set
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x40300000
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_CMD_SPL=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
index 7b50d2c..7a5c3e7 100644
--- a/configs/dra7xx_hs_evm_defconfig
+++ b/configs/dra7xx_hs_evm_defconfig
@@ -31,6 +31,7 @@
CONFIG_SPL_DMA_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
CONFIG_CMD_MTDPARTS=y
diff --git a/configs/dra7xx_hs_evm_usb_defconfig b/configs/dra7xx_hs_evm_usb_defconfig
index 6d6bfbc..0a376e0 100644
--- a/configs/dra7xx_hs_evm_usb_defconfig
+++ b/configs/dra7xx_hs_evm_usb_defconfig
@@ -15,6 +15,7 @@
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ARMV7_LPAE=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0x40306D50
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_IMAGE_POST_PROCESS=y
CONFIG_SPL_LOAD_FIT=y
@@ -27,13 +28,13 @@
# CONFIG_MISC_INIT_R is not set
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x40306D50
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_DMA_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_DFU=y
CONFIG_SPL_YMODEM_SUPPORT=y
diff --git a/configs/draco_defconfig b/configs/draco_defconfig
index 5f9e84a..4ba3bde 100644
--- a/configs/draco_defconfig
+++ b/configs/draco_defconfig
@@ -10,6 +10,7 @@
CONFIG_TARGET_DRACO=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_SPL_FS_FAT=y
@@ -18,11 +19,13 @@
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
diff --git a/configs/dreamplug_defconfig b/configs/dreamplug_defconfig
index e148208..206539d 100644
--- a/configs/dreamplug_defconfig
+++ b/configs/dreamplug_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_DREAMPLUG=y
@@ -7,6 +8,7 @@
CONFIG_IDENT_STRING="\nMarvell-DreamPlug"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/ds109_defconfig b/configs/ds109_defconfig
index 671572b..8f332a0 100644
--- a/configs/ds109_defconfig
+++ b/configs/ds109_defconfig
@@ -1,10 +1,12 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_DS109=y
CONFIG_NR_DRAM_BANKS=2
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_USE_PREBOOT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_IDE=y
diff --git a/configs/ds414_defconfig b/configs/ds414_defconfig
index 9abfae5..408904d 100644
--- a/configs/ds414_defconfig
+++ b/configs/ds414_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -13,14 +14,17 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0x40004030
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="usb start; sf probe"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0x40004030
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x24000
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_PCI=y
diff --git a/configs/dserve_dsrv9703c_defconfig b/configs/dserve_dsrv9703c_defconfig
index e4f9d41..c664bf5 100644
--- a/configs/dserve_dsrv9703c_defconfig
+++ b/configs/dserve_dsrv9703c_defconfig
@@ -14,7 +14,7 @@
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/duovero_defconfig b/configs/duovero_defconfig
index 419ed7a..11c95b4 100644
--- a/configs/duovero_defconfig
+++ b/configs/duovero_defconfig
@@ -3,12 +3,12 @@
CONFIG_OMAP44XX=y
CONFIG_TARGET_DUOVERO=y
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x40300000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_TEXT_BASE=0x40300000
# CONFIG_SPL_I2C_SUPPORT is not set
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SYS_PROMPT="duovero # "
diff --git a/configs/edison_defconfig b/configs/edison_defconfig
index 4687544..cac6e42 100644
--- a/configs/edison_defconfig
+++ b/configs/edison_defconfig
@@ -4,6 +4,7 @@
CONFIG_VENDOR_INTEL=y
CONFIG_TARGET_EDISON=y
CONFIG_SMP=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMDLINE_EDITING is not set
diff --git a/configs/edminiv2_defconfig b/configs/edminiv2_defconfig
index fae0874..9630d15 100644
--- a/configs/edminiv2_defconfig
+++ b/configs/edminiv2_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ORION5X=y
CONFIG_SYS_TEXT_BASE=0x00800000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -8,10 +9,10 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_IDENT_STRING=" EDMiniV2"
+CONFIG_SPL_TEXT_BASE=0xffff0000
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL_TEXT_BASE=0xffff0000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/efi-x86_app_defconfig b/configs/efi-x86_app_defconfig
index ea3743d..e732ec0 100644
--- a/configs/efi-x86_app_defconfig
+++ b/configs/efi-x86_app_defconfig
@@ -6,6 +6,7 @@
CONFIG_TARGET_EFI_APP=y
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
diff --git a/configs/efi-x86_payload32_defconfig b/configs/efi-x86_payload32_defconfig
index 01fe5c8..dc398c1 100644
--- a/configs/efi-x86_payload32_defconfig
+++ b/configs/efi-x86_payload32_defconfig
@@ -1,13 +1,14 @@
CONFIG_X86=y
CONFIG_NR_DRAM_BANKS=8
+CONFIG_PRE_CON_BUF_ADDR=0x100000
CONFIG_VENDOR_EFI=y
CONFIG_TARGET_EFI_PAYLOAD=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_PRE_CONSOLE_BUFFER=y
-CONFIG_PRE_CON_BUF_ADDR=0x100000
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
diff --git a/configs/efi-x86_payload64_defconfig b/configs/efi-x86_payload64_defconfig
index c4071ec..6e79cba 100644
--- a/configs/efi-x86_payload64_defconfig
+++ b/configs/efi-x86_payload64_defconfig
@@ -1,13 +1,14 @@
CONFIG_X86=y
CONFIG_NR_DRAM_BANKS=8
+CONFIG_PRE_CON_BUF_ADDR=0x100000
CONFIG_VENDOR_EFI=y
CONFIG_TARGET_EFI_PAYLOAD=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_PRE_CONSOLE_BUFFER=y
-CONFIG_PRE_CON_BUF_ADDR=0x100000
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
diff --git a/configs/elgin-rv1108_defconfig b/configs/elgin-rv1108_defconfig
index bcca040..b3d8d28 100644
--- a/configs/elgin-rv1108_defconfig
+++ b/configs/elgin-rv1108_defconfig
@@ -40,7 +40,6 @@
CONFIG_PINCTRL_ROCKCHIP_RV1108=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_BAUDRATE=1500000
-# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
CONFIG_USB=y
diff --git a/configs/emlid_neutis_n5_devboard_defconfig b/configs/emlid_neutis_n5_devboard_defconfig
index 3eb1ded..e85287e 100644
--- a/configs/emlid_neutis_n5_devboard_defconfig
+++ b/configs/emlid_neutis_n5_devboard_defconfig
@@ -8,7 +8,7 @@
# CONFIG_DRAM_ODT_EN is not set
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x10060
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/emsdp_defconfig b/configs/emsdp_defconfig
index 64281d0..5e55e3e 100644
--- a/configs/emsdp_defconfig
+++ b/configs/emsdp_defconfig
@@ -7,6 +7,7 @@
CONFIG_SYS_CLK_FREQ=40000000
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_VERSION_VARIABLE=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="emsdp# "
# CONFIG_CMD_BOOTD is not set
diff --git a/configs/espresso7420_defconfig b/configs/espresso7420_defconfig
index 2031f18..1b35881 100644
--- a/configs/espresso7420_defconfig
+++ b/configs/espresso7420_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x43E00000
CONFIG_ARCH_EXYNOS7=y
diff --git a/configs/etamin_defconfig b/configs/etamin_defconfig
index 8996858..31e711d 100644
--- a/configs/etamin_defconfig
+++ b/configs/etamin_defconfig
@@ -10,6 +10,8 @@
CONFIG_TARGET_ETAMIN=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x980000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_SPL_FS_FAT=y
@@ -18,11 +20,13 @@
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
diff --git a/configs/ethernut5_defconfig b/configs/ethernut5_defconfig
index 2ec3aae..45a9175 100644
--- a/configs/ethernut5_defconfig
+++ b/configs/ethernut5_defconfig
@@ -1,9 +1,13 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x27000000
CONFIG_TARGET_ETHERNUT5=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x21000
+CONFIG_ENV_OFFSET=0x3DE000
CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SECT_SIZE=0x21000
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
@@ -54,6 +58,7 @@
CONFIG_AT91_GPIO=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig
index b73da72..477ccbf 100644
--- a/configs/evb-ast2500_defconfig
+++ b/configs/evb-ast2500_defconfig
@@ -6,21 +6,28 @@
CONFIG_TARGET_EVB_AST2500=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
+CONFIG_PRE_CON_BUF_ADDR=0x1e720000
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS4,115200n8 root=/dev/ram rw"
CONFIG_PRE_CONSOLE_BUFFER=y
-CONFIG_PRE_CON_BUF_ADDR=0x1e720000
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="ast2500-evb"
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_REGMAP=y
CONFIG_CLK=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_ASPEED=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ASPEED=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_FTGMAC100=y
diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig
index 9601b12..5a06b2a 100644
--- a/configs/evb-px5_defconfig
+++ b/configs/evb-px5_defconfig
@@ -1,15 +1,12 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3368=y
-CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x40000
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
CONFIG_TARGET_EVB_PX5=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL_STACK_R_ADDR=0x600000
@@ -32,13 +29,12 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_ARCH_EARLY_INIT_R=y
CONFIG_SPL_BOOTROM_SUPPORT=y
-# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_TPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
-CONFIG_TPL_BOOTROM_SUPPORT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_CACHE=y
CONFIG_SPL_OF_CONTROL=y
@@ -70,11 +66,6 @@
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_SYSRESET=y
-CONFIG_TIMER=y
-CONFIG_SPL_TIMER=y
-CONFIG_TPL_TIMER=y
-CONFIG_ROCKCHIP_TIMER=y
-CONFIG_USE_TINY_PRINTF=y
CONFIG_PANIC_HANG=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_TPL_TINY_MEMSET=y
diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig
index 5e6bb54..2e7f57a 100644
--- a/configs/evb-rk3036_defconfig
+++ b/configs/evb-rk3036_defconfig
@@ -5,25 +5,26 @@
CONFIG_SYS_TEXT_BASE=0x60000000
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ROCKCHIP_RK3036=y
-CONFIG_TARGET_EVB_RK3036=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x0
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEBUG_UART_BASE=0x20068000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0x10081000
# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3036-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_TEXT_BASE=0x10081000
CONFIG_SPL_STACK_R=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
+CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
@@ -45,17 +46,18 @@
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_PINCTRL=y
# CONFIG_SPL_DM_SERIAL is not set
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
+# CONFIG_SPL_SYSRESET is not set
CONFIG_USB=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
CONFIG_USB_GADGET_VENDOR_NUM=0x2207
CONFIG_USB_GADGET_PRODUCT_NUM=0x310a
CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USB_FUNCTION_MASS_STORAGE=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
diff --git a/configs/evb-rk3128_defconfig b/configs/evb-rk3128_defconfig
index 030e5e4..a318963 100644
--- a/configs/evb-rk3128_defconfig
+++ b/configs/evb-rk3128_defconfig
@@ -47,5 +47,4 @@
CONFIG_USB_DWC2=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USE_TINY_PRINTF=y
CONFIG_ERRNO_STR=y
diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig
index 31c1b17..9c8c084 100644
--- a/configs/evb-rk3229_defconfig
+++ b/configs/evb-rk3229_defconfig
@@ -1,33 +1,31 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x61000000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_ROCKCHIP_RK322X=y
-CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl.lds"
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
CONFIG_TARGET_EVB_RK3229=y
+CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl.lds"
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL_STACK_R_ADDR=0x60600000
CONFIG_DEBUG_UART_BASE=0x11030000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0x60000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_SOURCE="arch/arm/mach-rockchip/fit_spl_optee.its"
+CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3229-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0x60000000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_SPL_OPTEE=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
@@ -70,7 +68,5 @@
CONFIG_USB_GADGET_VENDOR_NUM=0x2207
CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USB_FUNCTION_MASS_STORAGE=y
-CONFIG_USE_TINY_PRINTF=y
CONFIG_TPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig
index 843c59d..7b0e908 100644
--- a/configs/evb-rk3288_defconfig
+++ b/configs/evb-rk3288_defconfig
@@ -1,21 +1,20 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_SYS_TEXT_BASE=0x00000000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_TEXT_BASE=0x01000000
CONFIG_ROCKCHIP_RK3288=y
-CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
CONFIG_TARGET_EVB_RK3288=y
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL_SIZE_LIMIT=307200
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_DEFAULT_FDT_FILE="rk3288-evb-rk808.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0xff704000
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_CMD_GPIO=y
@@ -25,6 +24,7 @@
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
@@ -77,12 +77,10 @@
CONFIG_USB_GADGET_VENDOR_NUM=0x2207
CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USB_FUNCTION_MASS_STORAGE=y
CONFIG_DM_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1200
CONFIG_DISPLAY_ROCKCHIP_MIPI=y
-CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig
index 92d6817..3761077 100644
--- a/configs/evb-rk3328_defconfig
+++ b/configs/evb-rk3328_defconfig
@@ -1,36 +1,52 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_ROCKCHIP_RK3328=y
+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x40000
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_TPL_DRIVERS_MISC_SUPPORT=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
-CONFIG_DEFAULT_DEVICE_TREE="rk3328-evb"
CONFIG_SPL_OF_CONTROL=y
+CONFIG_TPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-evb"
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_TPL_OF_PLATDATA=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TPL_DM=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
+CONFIG_TPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
+CONFIG_TPL_SYSCON=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
+CONFIG_TPL_CLK=y
CONFIG_FASTBOOT_BUF_ADDR=0x800800
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=1
@@ -46,6 +62,7 @@
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY=y
CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
@@ -53,8 +70,12 @@
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
@@ -70,5 +91,6 @@
CONFIG_USB_GADGET_VENDOR_NUM=0x2207
CONFIG_USB_GADGET_PRODUCT_NUM=0x330a
CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USE_TINY_PRINTF=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_TPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index f10502c..a0d215a 100644
--- a/configs/evb-rk3399_defconfig
+++ b/configs/evb-rk3399_defconfig
@@ -1,9 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
CONFIG_NR_DRAM_BANKS=1
@@ -14,6 +11,7 @@
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_TPL=y
@@ -61,6 +59,5 @@
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1200
CONFIG_DISPLAY_ROCKCHIP_MIPI=y
-CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
diff --git a/configs/evb-rv1108_defconfig b/configs/evb-rv1108_defconfig
index 3a5d101..2e28871 100644
--- a/configs/evb-rv1108_defconfig
+++ b/configs/evb-rv1108_defconfig
@@ -2,7 +2,6 @@
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x60000000
CONFIG_ROCKCHIP_RV1108=y
-CONFIG_TARGET_EVB_RV1108=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0x10210000
CONFIG_DEBUG_UART_CLOCK=24000000
@@ -38,7 +37,6 @@
CONFIG_PINCTRL=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_BAUDRATE=1500000
-# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
CONFIG_USB=y
diff --git a/configs/fennec-rk3288_defconfig b/configs/fennec-rk3288_defconfig
deleted file mode 100644
index 6dfaff5..0000000
--- a/configs/fennec-rk3288_defconfig
+++ /dev/null
@@ -1,85 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_ROCKCHIP=y
-CONFIG_SYS_TEXT_BASE=0x00000000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_ROCKCHIP_RK3288=y
-CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
-CONFIG_TARGET_FENNEC_RK3288=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SPL_STACK_R_ADDR=0x80000
-CONFIG_DEBUG_UART_BASE=0xff690000
-CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
-# CONFIG_ANDROID_BOOT_IMAGE is not set
-CONFIG_SILENT_CONSOLE=y
-CONFIG_CONSOLE_MUX=y
-CONFIG_DEFAULT_FDT_FILE="rk3288-fennec.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0xff704000
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_PMIC=y
-CONFIG_CMD_REGULATOR=y
-# CONFIG_SPL_DOS_PARTITION is not set
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_SPL_PARTITION_UUIDS=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="rk3288-fennec"
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_REGMAP=y
-CONFIG_SPL_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_SPL_SYSCON=y
-# CONFIG_SPL_SIMPLE_BUS is not set
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-CONFIG_ROCKCHIP_GPIO=y
-CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_MMC_DW=y
-CONFIG_MMC_DW_ROCKCHIP=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=20000000
-CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_GMAC_ROCKCHIP=y
-CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
-CONFIG_DM_PMIC=y
-CONFIG_PMIC_RK8XX=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_REGULATOR_RK8XX=y
-CONFIG_PWM_ROCKCHIP=y
-CONFIG_RAM=y
-CONFIG_SPL_RAM=y
-CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYSRESET=y
-CONFIG_USB=y
-CONFIG_USB_DWC2=y
-CONFIG_ROCKCHIP_USB2_PHY=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
-CONFIG_USB_GADGET_VENDOR_NUM=0x2207
-CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
-CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USB_FUNCTION_MASS_STORAGE=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_ASIX=y
-CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_USE_TINY_PRINTF=y
-CONFIG_CMD_DHRYSTONE=y
-CONFIG_ERRNO_STR=y
diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig
index 6a1b279..05bbfbf 100644
--- a/configs/ficus-rk3399_defconfig
+++ b/configs/ficus-rk3399_defconfig
@@ -1,9 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
CONFIG_TARGET_ROCK960_RK3399=y
@@ -11,9 +8,10 @@
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0xff8c2000
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0xff8c2000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
CONFIG_CMD_BOOTZ=y
@@ -50,5 +48,4 @@
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
-CONFIG_USE_TINY_PRINTF=y
CONFIG_ERRNO_STR=y
diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index 4cedb28..29935d8 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -1,7 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00000000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3288=y
CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
CONFIG_TARGET_FIREFLY_RK3288=y
@@ -10,12 +9,13 @@
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0xff704000
# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_DEFAULT_FDT_FILE="rk3288-firefly.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0xff704000
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_CMD_GPIO=y
@@ -25,6 +25,7 @@
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
@@ -81,7 +82,6 @@
CONFIG_USB_GADGET_VENDOR_NUM=0x2207
CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USB_FUNCTION_MASS_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_SMSC95XX=y
@@ -90,6 +90,5 @@
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
CONFIG_CONSOLE_SCROLL_LINES=10
-CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig
index 61f05b7..d022631 100644
--- a/configs/firefly-rk3399_defconfig
+++ b/configs/firefly-rk3399_defconfig
@@ -1,9 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
CONFIG_NR_DRAM_BANKS=1
@@ -14,6 +11,7 @@
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_TPL=y
@@ -56,6 +54,5 @@
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
diff --git a/configs/ga10h_v1_1_defconfig b/configs/ga10h_v1_1_defconfig
index ba86f48..b82325d 100644
--- a/configs/ga10h_v1_1_defconfig
+++ b/configs/ga10h_v1_1_defconfig
@@ -17,7 +17,7 @@
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig
index ba5a501..f8d12e1 100644
--- a/configs/galileo_defconfig
+++ b/configs/galileo_defconfig
@@ -7,6 +7,7 @@
CONFIG_GENERATE_MP_TABLE=y
CONFIG_GENERATE_ACPI_TABLE=y
CONFIG_FIT=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
diff --git a/configs/gardena-smart-gateway-at91sam_defconfig b/configs/gardena-smart-gateway-at91sam_defconfig
index a25d378..4a2cc33 100644
--- a/configs/gardena-smart-gateway-at91sam_defconfig
+++ b/configs/gardena-smart-gateway-at91sam_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x10000
CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
@@ -16,6 +17,7 @@
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_SMBIOS_PRODUCT_NAME="at91sam9x5ek"
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0x300000
CONFIG_FIT=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
@@ -23,10 +25,8 @@
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256k(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs rw"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_SPL_TEXT_BASE=0x300000
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
-# CONFIG_TPL_BANNER_PRINT is not set
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
@@ -52,6 +52,9 @@
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g25-gardena-smart-gateway"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupts interrupt-parent interrupts-extended dmas dma-names"
CONFIG_ENV_IS_IN_UBI=y
+CONFIG_ENV_UBI_PART="ubi"
+CONFIG_ENV_UBI_VOLUME="env"
+CONFIG_ENV_UBI_VOLUME_REDUND="env_r"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SPL_DM=y
@@ -65,7 +68,6 @@
# CONFIG_MMC is not set
CONFIG_NAND_ATMEL=y
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
-# CONFIG_CONFIG_UBI_SILENCE_MSG is not set
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
@@ -80,4 +82,3 @@
CONFIG_WDT=y
CONFIG_WDT_AT91=y
# CONFIG_UBIFS_SILENCE_MSG is not set
-CONFIG_USE_TINY_PRINTF=y
diff --git a/configs/gardena-smart-gateway-mt7688-ram_defconfig b/configs/gardena-smart-gateway-mt7688-ram_defconfig
index 4edade4..03f9d99 100644
--- a/configs/gardena-smart-gateway-mt7688-ram_defconfig
+++ b/configs/gardena-smart-gateway-mt7688-ram_defconfig
@@ -9,7 +9,7 @@
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
-CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="cp.b 83000000 84000000 10000 && dhcp uEnv.txt && env import -t ${fileaddr} ${filesize} && run do_u_boot_init; reset"
@@ -67,7 +67,6 @@
CONFIG_POWER_DOMAIN=y
CONFIG_RAM=y
CONFIG_DM_RESET=y
-# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_MT7621_SPI=y
diff --git a/configs/gardena-smart-gateway-mt7688_defconfig b/configs/gardena-smart-gateway-mt7688_defconfig
index 707d270..6cb8fc0 100644
--- a/configs/gardena-smart-gateway-mt7688_defconfig
+++ b/configs/gardena-smart-gateway-mt7688_defconfig
@@ -12,7 +12,7 @@
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
-CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="cp.b 83000000 84000000 10000 && dhcp uEnv.txt && env import -t ${fileaddr} ${filesize} && run do_u_boot_init; reset"
@@ -70,7 +70,6 @@
CONFIG_POWER_DOMAIN=y
CONFIG_RAM=y
CONFIG_DM_RESET=y
-# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_MT7621_SPI=y
diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig
index 8be881b..7351659 100644
--- a/configs/ge_bx50v3_defconfig
+++ b/configs/ge_bx50v3_defconfig
@@ -43,7 +43,7 @@
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
@@ -55,6 +55,7 @@
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
+CONFIG_PWM_IMX=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MXC_SPI=y
diff --git a/configs/goflexhome_defconfig b/configs/goflexhome_defconfig
index b5d31db..5fa8b4d 100644
--- a/configs/goflexhome_defconfig
+++ b/configs/goflexhome_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_GOFLEXHOME=y
@@ -7,6 +8,7 @@
CONFIG_IDENT_STRING="\nSeagate GoFlex Home"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="GoFlexHome> "
diff --git a/configs/gose_defconfig b/configs/gose_defconfig
index f591bd8..15a9c5c 100644
--- a/configs/gose_defconfig
+++ b/configs/gose_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
@@ -16,15 +17,16 @@
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0xe6300000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_TEXT_BASE=0xe6300000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
diff --git a/configs/gplugd_defconfig b/configs/gplugd_defconfig
index fe2e00a..4766be0 100644
--- a/configs/gplugd_defconfig
+++ b/configs/gplugd_defconfig
@@ -1,10 +1,12 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_TARGET_GPLUGD=y
CONFIG_SYS_TEXT_BASE=0x00f00000
CONFIG_NR_DRAM_BANKS=2
CONFIG_IDENT_STRING="\nMarvell-gplugD"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/grpeach_defconfig b/configs/grpeach_defconfig
index 32254b3..4a243d6 100644
--- a/configs/grpeach_defconfig
+++ b/configs/grpeach_defconfig
@@ -1,5 +1,5 @@
CONFIG_ARM=y
-# CONFIG_SPL_SYS_THUMB_BUILD is not set
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0x18000000
CONFIG_RZA1=y
@@ -10,6 +10,7 @@
# CONFIG_CMD_ELF is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
@@ -30,7 +31,7 @@
CONFIG_USE_ENV_SPI_MODE=y
CONFIG_ENV_SPI_MODE=0x0
CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_HAVE_BLOCK_DEVICE=y
+CONFIG_BLK=y
CONFIG_DM_GPIO=y
CONFIG_RZA1_GPIO=y
CONFIG_LED=y
@@ -43,11 +44,17 @@
CONFIG_DM_ETH=y
CONFIG_SH_ETHER=y
CONFIG_PINCTRL=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
CONFIG_SCIF_CONSOLE=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_RENESAS_RPC_SPI=y
CONFIG_TIMER=y
CONFIG_RENESAS_OSTM_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_R8A66597_HCD=y
+CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT_OVERLAY=y
# CONFIG_EFI_LOADER is not set
diff --git a/configs/gt90h_v4_defconfig b/configs/gt90h_v4_defconfig
index c440504..b317d4d 100644
--- a/configs/gt90h_v4_defconfig
+++ b/configs/gt90h_v4_defconfig
@@ -16,7 +16,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/gurnard_defconfig b/configs/gurnard_defconfig
index d19f485..f461d92 100644
--- a/configs/gurnard_defconfig
+++ b/configs/gurnard_defconfig
@@ -2,6 +2,8 @@
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x73f00000
CONFIG_TARGET_GURNARD=y
+CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_OFFSET=0x80000
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G45"
@@ -26,6 +28,7 @@
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g45-gurnard"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_ATMEL_NAND_HWECC=y
CONFIG_PHYLIB=y
diff --git a/configs/guruplug_defconfig b/configs/guruplug_defconfig
index 787ba6c..12ca8b3 100644
--- a/configs/guruplug_defconfig
+++ b/configs/guruplug_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_GURUPLUG=y
@@ -7,6 +8,7 @@
CONFIG_IDENT_STRING="\nMarvell-GuruPlug"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig
index f9857d1..8c79cba 100644
--- a/configs/gwventana_emmc_defconfig
+++ b/configs/gwventana_emmc_defconfig
@@ -13,18 +13,19 @@
CONFIG_SPL_STACK_R_ADDR=0x18000000
CONFIG_SPL=y
CONFIG_CMD_HDMIDETECT=y
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_DMA_SUPPORT=y
@@ -35,7 +36,6 @@
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Ventana > "
CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_SPL_NAND_OFS=0x1100000
CONFIG_CMD_SPL_WRITE_SIZE=0x20000
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
@@ -63,7 +63,7 @@
CONFIG_DWC_AHSATA=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_MTD_DEVICE=y
CONFIG_PHYLIB=y
CONFIG_E1000=y
diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig
index 27ef264..6b2e0c7 100644
--- a/configs/gwventana_gw5904_defconfig
+++ b/configs/gwventana_gw5904_defconfig
@@ -13,18 +13,19 @@
CONFIG_SPL_STACK_R_ADDR=0x18000000
CONFIG_SPL=y
CONFIG_CMD_HDMIDETECT=y
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_DMA_SUPPORT=y
@@ -35,7 +36,6 @@
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Ventana > "
CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_SPL_NAND_OFS=0x1100000
CONFIG_CMD_SPL_WRITE_SIZE=0x20000
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
@@ -63,7 +63,7 @@
CONFIG_DWC_AHSATA=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_MTD_DEVICE=y
CONFIG_PHYLIB=y
CONFIG_MV88E61XX_SWITCH=y
diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig
index 25af087..a485fc9 100644
--- a/configs/gwventana_nand_defconfig
+++ b/configs/gwventana_nand_defconfig
@@ -13,18 +13,19 @@
CONFIG_SPL_STACK_R_ADDR=0x18000000
CONFIG_SPL=y
CONFIG_CMD_HDMIDETECT=y
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_DMA_SUPPORT=y
@@ -65,7 +66,7 @@
CONFIG_DWC_AHSATA=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_PHYLIB=y
diff --git a/configs/h8_homlet_v2_defconfig b/configs/h8_homlet_v2_defconfig
index d60576d..70c566d 100644
--- a/configs/h8_homlet_v2_defconfig
+++ b/configs/h8_homlet_v2_defconfig
@@ -10,8 +10,8 @@
CONFIG_USB1_VBUS_PIN="PL6"
CONFIG_AXP_GPIO=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
-CONFIG_SPL_TEXT_BASE=0x60
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig
index 04212c9..519da65 100644
--- a/configs/harmony_defconfig
+++ b/configs/harmony_defconfig
@@ -4,9 +4,9 @@
CONFIG_NR_DRAM_BANKS=2
CONFIG_TEGRA20=y
CONFIG_TARGET_HARMONY=y
+CONFIG_SPL_TEXT_BASE=0x00108000
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_SYS_STDIO_DEREGISTER=y
-CONFIG_SPL_TEXT_BASE=0x00108000
CONFIG_SYS_PROMPT="Tegra20 (Harmony) # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/helios4_defconfig b/configs/helios4_defconfig
index 3b1737b..ed488cb 100644
--- a/configs/helios4_defconfig
+++ b/configs/helios4_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -13,12 +14,13 @@
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0x40000030
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0x40000030
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x141
# CONFIG_CMD_FLASH is not set
diff --git a/configs/hikey960_defconfig b/configs/hikey960_defconfig
new file mode 100644
index 0000000..99f8712
--- /dev/null
+++ b/configs/hikey960_defconfig
@@ -0,0 +1,30 @@
+CONFIG_ARM=y
+CONFIG_TARGET_HIKEY960=y
+CONFIG_SYS_TEXT_BASE=0x1ac98000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_IDENT_STRING="\nHikey960"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyAMA6,115200n8 root=/dev/mmcblk0p2 rw"
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SYS_PROMPT="U-Boot => "
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_DEFAULT_DEVICE_TREE="hi3660-hikey960"
+CONFIG_ENV_IS_IN_EXT4=y
+CONFIG_ENV_EXT4_INTERFACE="mmc"
+CONFIG_ENV_EXT4_DEVICE_AND_PART="0:2"
+CONFIG_ENV_EXT4_FILE="/uboot.env"
+CONFIG_DM_MMC=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_K3=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig
index abb409d..6afd647 100644
--- a/configs/hrcon_defconfig
+++ b/configs/hrcon_defconfig
@@ -100,6 +100,7 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=5
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig
index 6f221a3..544a98c 100644
--- a/configs/hrcon_dh_defconfig
+++ b/configs/hrcon_dh_defconfig
@@ -101,6 +101,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="HRCON_DH"
CONFIG_BOOTDELAY=5
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/huawei_hg556a_ram_defconfig b/configs/huawei_hg556a_ram_defconfig
index b8da32e..8c4f87a 100644
--- a/configs/huawei_hg556a_ram_defconfig
+++ b/configs/huawei_hg556a_ram_defconfig
@@ -49,7 +49,6 @@
CONFIG_BCM6358_USBH_PHY=y
CONFIG_DM_RESET=y
CONFIG_RESET_BCM6345=y
-# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DM_SERIAL=y
CONFIG_BCM6345_SERIAL=y
CONFIG_USB=y
diff --git a/configs/i12-tvbox_defconfig b/configs/i12-tvbox_defconfig
index 259bf4e..c512d36 100644
--- a/configs/i12-tvbox_defconfig
+++ b/configs/i12-tvbox_defconfig
@@ -7,7 +7,7 @@
CONFIG_MACPWR="PH21"
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/iNet_3F_defconfig b/configs/iNet_3F_defconfig
index 935a11e..6c047ca 100644
--- a/configs/iNet_3F_defconfig
+++ b/configs/iNet_3F_defconfig
@@ -14,7 +14,7 @@
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/iNet_3W_defconfig b/configs/iNet_3W_defconfig
index a829401..3b4ffe4 100644
--- a/configs/iNet_3W_defconfig
+++ b/configs/iNet_3W_defconfig
@@ -14,7 +14,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/iNet_86VS_defconfig b/configs/iNet_86VS_defconfig
index 93bdddc..5fff4ad 100644
--- a/configs/iNet_86VS_defconfig
+++ b/configs/iNet_86VS_defconfig
@@ -13,7 +13,7 @@
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/iNet_D978_rev2_defconfig b/configs/iNet_D978_rev2_defconfig
index 1a8ee6b..d36c3ee 100644
--- a/configs/iNet_D978_rev2_defconfig
+++ b/configs/iNet_D978_rev2_defconfig
@@ -17,7 +17,7 @@
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/ib62x0_defconfig b/configs/ib62x0_defconfig
index 979f724..13a2e83 100644
--- a/configs/ib62x0_defconfig
+++ b/configs/ib62x0_defconfig
@@ -1,11 +1,13 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_IB62X0=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_IDENT_STRING=" RaidSonic ICY BOX IB-NAS62x0"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ib62x0 => "
diff --git a/configs/icnova-a20-swac_defconfig b/configs/icnova-a20-swac_defconfig
index ed54700..1372c76 100644
--- a/configs/icnova-a20-swac_defconfig
+++ b/configs/icnova-a20-swac_defconfig
@@ -13,7 +13,7 @@
CONFIG_VIDEO_LCD_POWER="PH22"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_CMD_UNZIP=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/iconnect_defconfig b/configs/iconnect_defconfig
index eb0e8a9..aa67a6c 100644
--- a/configs/iconnect_defconfig
+++ b/configs/iconnect_defconfig
@@ -1,11 +1,13 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_ICONNECT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_IDENT_STRING=" Iomega iConnect"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="iconnect => "
# CONFIG_CMD_FLASH is not set
diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig
index 154a075..418a4b3 100644
--- a/configs/ids8313_defconfig
+++ b/configs/ids8313_defconfig
@@ -117,10 +117,12 @@
CONFIG_LCRR_CLKDIV_2=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
-CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=1
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="echo;echo Type \"run nfsboot\" to mount root filesystem over NFS;echo"
CONFIG_MISC_INIT_R=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/igep00x0_defconfig b/configs/igep00x0_defconfig
index bc77069..04e9c95 100644
--- a/configs/igep00x0_defconfig
+++ b/configs/igep00x0_defconfig
@@ -2,8 +2,10 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_TARGET_OMAP3_IGEP00X0=y
+CONFIG_ENV_SIZE=0x8000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
@@ -12,10 +14,21 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
# CONFIG_SPL_FS_EXT4 is not set
CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_UBI=y
+CONFIG_SPL_UBI_MAX_VOL_LEBS=256
+CONFIG_SPL_UBI_MAX_PEB_SIZE=262144
+CONFIG_SPL_UBI_MAX_PEBS=4096
+CONFIG_SPL_UBI_PEB_OFFSET=4
+CONFIG_SPL_UBI_VID_OFFSET=512
+CONFIG_SPL_UBI_LEB_START=2048
+CONFIG_SPL_UBI_INFO_ADDR=0x88080000
+CONFIG_SPL_UBI_VOL_IDS=8
+CONFIG_SPL_UBI_LOAD_MONITOR_ID=0
+CONFIG_SPL_UBI_LOAD_KERNEL_ID=3
+CONFIG_SPL_UBI_LOAD_ARGS_ID=4
CONFIG_SPL_ONENAND_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_CMD_SPL=y
@@ -29,6 +42,10 @@
# CONFIG_CMD_UBIFS is not set
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="omap3-igep0020"
+CONFIG_ENV_IS_IN_UBI=y
+CONFIG_ENV_UBI_PART="UBI"
+CONFIG_ENV_UBI_VOLUME="config"
+CONFIG_ENV_UBI_VOLUME_REDUND="config_r"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
@@ -42,6 +59,5 @@
CONFIG_CONS_INDEX=3
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
-CONFIG_UBIFS_SILENCE_MSG=y
CONFIG_BCH=y
CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/imx6dl_icore_nand_defconfig b/configs/imx6dl_icore_nand_defconfig
index 3db7082..36c52b0 100644
--- a/configs/imx6dl_icore_nand_defconfig
+++ b/configs/imx6dl_icore_nand_defconfig
@@ -9,14 +9,14 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_BOUNCE_BUFFER=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
@@ -27,6 +27,7 @@
CONFIG_CMD_MMC=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
@@ -39,7 +40,7 @@
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-icore"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_PHYLIB=y
@@ -51,4 +52,5 @@
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_VIDEO_IPUV3=y
diff --git a/configs/imx6dl_mamoj_defconfig b/configs/imx6dl_mamoj_defconfig
index c27c5cc..b568dfd 100644
--- a/configs/imx6dl_mamoj_defconfig
+++ b/configs/imx6dl_mamoj_defconfig
@@ -5,11 +5,11 @@
CONFIG_TARGET_MX6DL_MAMOJ=y
CONFIG_NR_DRAM_BANKS=1
# CONFIG_CMD_BMODE is not set
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_BOUNCE_BUFFER=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_OS_BOOT=y
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_MEMTEST=y
@@ -32,7 +32,7 @@
CONFIG_FASTBOOT_FLASH_MMC_DEV=2
CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
diff --git a/configs/imx6q_icore_nand_defconfig b/configs/imx6q_icore_nand_defconfig
index ad4b930..eb19ae2 100644
--- a/configs/imx6q_icore_nand_defconfig
+++ b/configs/imx6q_icore_nand_defconfig
@@ -9,15 +9,15 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOUNCE_BUFFER=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
@@ -28,6 +28,7 @@
CONFIG_CMD_MMC=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
@@ -40,7 +41,7 @@
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_PHYLIB=y
@@ -52,4 +53,5 @@
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_VIDEO_IPUV3=y
diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig
index 0bb2fc6..ec14b8e 100644
--- a/configs/imx6q_logic_defconfig
+++ b/configs/imx6q_logic_defconfig
@@ -10,6 +10,7 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
@@ -17,10 +18,8 @@
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_BOUNCE_BUFFER=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_SEPARATE_BSS=y
-# CONFIG_TPL_BANNER_PRINT is not set
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -54,18 +53,23 @@
CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:2m(spl),2m(uboot),1m(env),16m(kernel),1m(dtb),-(fs)"
CONFIG_CMD_UBI=y
+CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-logicpd"
CONFIG_ENV_IS_IN_FAT=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_ENV_FAT_INTERFACE="mmc"
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_OF_TRANSLATE=y
CONFIG_PCF8575_GPIO=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_NAND=y
+CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_MXS=y
CONFIG_NAND_MXS_DT=y
CONFIG_PHYLIB=y
@@ -82,6 +86,7 @@
CONFIG_MXC_UART=y
CONFIG_USB=y
CONFIG_DM_USB=y
+# CONFIG_SPL_DM_USB is not set
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
diff --git a/configs/imx6qdl_icore_mipi_defconfig b/configs/imx6qdl_icore_mipi_defconfig
index f6fc59f..fca565b 100644
--- a/configs/imx6qdl_icore_mipi_defconfig
+++ b/configs/imx6qdl_icore_mipi_defconfig
@@ -13,16 +13,16 @@
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_CMD_BMODE is not set
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOUNCE_BUFFER=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
@@ -44,7 +44,7 @@
CONFIG_OF_LIST="imx6q-icore-mipi imx6dl-icore-mipi"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_SMSC=y
CONFIG_FEC_MXC=y
diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig
index 5ab932d..6f4f712 100644
--- a/configs/imx6qdl_icore_mmc_defconfig
+++ b/configs/imx6qdl_icore_mmc_defconfig
@@ -15,16 +15,16 @@
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_CMD_BMODE is not set
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOUNCE_BUFFER=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
@@ -36,6 +36,7 @@
CONFIG_CMD_MMC=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
CONFIG_CMD_BOOTCOUNT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
@@ -54,7 +55,7 @@
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_MAGIC=0x0B01C041
CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_PHYLIB=y
@@ -67,5 +68,6 @@
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_VIDEO_IPUV3=y
CONFIG_IMX_WATCHDOG=y
diff --git a/configs/imx6qdl_icore_nand_defconfig b/configs/imx6qdl_icore_nand_defconfig
index ad4b930..eb19ae2 100644
--- a/configs/imx6qdl_icore_nand_defconfig
+++ b/configs/imx6qdl_icore_nand_defconfig
@@ -9,15 +9,15 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOUNCE_BUFFER=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
@@ -28,6 +28,7 @@
CONFIG_CMD_MMC=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
@@ -40,7 +41,7 @@
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_PHYLIB=y
@@ -52,4 +53,5 @@
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_VIDEO_IPUV3=y
diff --git a/configs/imx6qdl_icore_rqs_defconfig b/configs/imx6qdl_icore_rqs_defconfig
index 4b89981..016cfa2 100644
--- a/configs/imx6qdl_icore_rqs_defconfig
+++ b/configs/imx6qdl_icore_rqs_defconfig
@@ -10,16 +10,16 @@
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_CMD_BMODE is not set
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOUNCE_BUFFER=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
@@ -41,7 +41,7 @@
CONFIG_OF_LIST="imx6q-icore-rqs imx6dl-icore-rqs"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
diff --git a/configs/imx6ul_geam_mmc_defconfig b/configs/imx6ul_geam_mmc_defconfig
index d5fdc43..6c8de48 100644
--- a/configs/imx6ul_geam_mmc_defconfig
+++ b/configs/imx6ul_geam_mmc_defconfig
@@ -10,15 +10,15 @@
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_CMD_BMODE is not set
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOUNCE_BUFFER=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="geam6ul> "
@@ -38,7 +38,7 @@
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-geam"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_SMSC=y
CONFIG_FEC_MXC=y
diff --git a/configs/imx6ul_geam_nand_defconfig b/configs/imx6ul_geam_nand_defconfig
index ea4d7ad..77cd1f2 100644
--- a/configs/imx6ul_geam_nand_defconfig
+++ b/configs/imx6ul_geam_nand_defconfig
@@ -9,15 +9,15 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOUNCE_BUFFER=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
@@ -41,7 +41,7 @@
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-geam"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_PHYLIB=y
diff --git a/configs/imx6ul_isiot_emmc_defconfig b/configs/imx6ul_isiot_emmc_defconfig
index 88b9b49..4ad77a8 100644
--- a/configs/imx6ul_isiot_emmc_defconfig
+++ b/configs/imx6ul_isiot_emmc_defconfig
@@ -10,15 +10,15 @@
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_CMD_BMODE is not set
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOUNCE_BUFFER=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="isiotmx6ul> "
@@ -38,7 +38,7 @@
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-isiot-emmc"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_SMSC=y
CONFIG_FEC_MXC=y
diff --git a/configs/imx6ul_isiot_nand_defconfig b/configs/imx6ul_isiot_nand_defconfig
index c60bde7..60327d3 100644
--- a/configs/imx6ul_isiot_nand_defconfig
+++ b/configs/imx6ul_isiot_nand_defconfig
@@ -9,15 +9,15 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOUNCE_BUFFER=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
@@ -41,7 +41,7 @@
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-isiot-nand"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_PHYLIB=y
diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig
index f02b5e2..59ba4bc 100644
--- a/configs/imx8mq_evk_defconfig
+++ b/configs/imx8mq_evk_defconfig
@@ -6,14 +6,15 @@
CONFIG_TARGET_IMX8MQ_EVK=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg"
-CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_SPL_BOARD_INIT=y
CONFIG_HUSH_PARSER=y
+# CONFIG_BOOTM_NETBSD is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_CACHE=y
@@ -31,6 +32,7 @@
CONFIG_SYS_I2C_MXC=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
CONFIG_DM_ETH=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig
index 6db0669..42591c7 100644
--- a/configs/imx8qm_mek_defconfig
+++ b/configs/imx8qm_mek_defconfig
@@ -24,6 +24,7 @@
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
# CONFIG_CMD_IMPORTENV is not set
CONFIG_CMD_CLK=y
CONFIG_CMD_DM=y
@@ -51,6 +52,7 @@
CONFIG_I2C_MUX_PCA954x=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig
index d735d34..f4cc86e 100644
--- a/configs/imx8qxp_mek_defconfig
+++ b/configs/imx8qxp_mek_defconfig
@@ -27,6 +27,7 @@
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
# CONFIG_CMD_IMPORTENV is not set
CONFIG_CMD_CLK=y
CONFIG_CMD_DM=y
@@ -56,6 +57,7 @@
CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_ATHEROS=y
@@ -77,5 +79,7 @@
CONFIG_SPL_DM_REGULATOR_GPIO=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
CONFIG_SPL_TINY_MEMSET=y
# CONFIG_EFI_LOADER is not set
diff --git a/configs/inet1_defconfig b/configs/inet1_defconfig
index 25a907b..3cb6664 100644
--- a/configs/inet1_defconfig
+++ b/configs/inet1_defconfig
@@ -14,7 +14,7 @@
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/inet86dz_defconfig b/configs/inet86dz_defconfig
index c007af9..9038811 100644
--- a/configs/inet86dz_defconfig
+++ b/configs/inet86dz_defconfig
@@ -16,7 +16,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/inet97fv2_defconfig b/configs/inet97fv2_defconfig
index bc89a76..2b43142 100644
--- a/configs/inet97fv2_defconfig
+++ b/configs/inet97fv2_defconfig
@@ -13,7 +13,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/inet98v_rev2_defconfig b/configs/inet98v_rev2_defconfig
index b39c5f3..76baeec 100644
--- a/configs/inet98v_rev2_defconfig
+++ b/configs/inet98v_rev2_defconfig
@@ -15,7 +15,7 @@
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/inet9f_rev03_defconfig b/configs/inet9f_rev03_defconfig
index d46c99f..771dc1f 100644
--- a/configs/inet9f_rev03_defconfig
+++ b/configs/inet9f_rev03_defconfig
@@ -13,7 +13,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/inet_q972_defconfig b/configs/inet_q972_defconfig
index 19a3c4c..4b26a92 100644
--- a/configs/inet_q972_defconfig
+++ b/configs/inet_q972_defconfig
@@ -15,7 +15,7 @@
CONFIG_VIDEO_LCD_BL_EN="PA25"
CONFIG_VIDEO_LCD_BL_PWM="PH13"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/inetspace_v2_defconfig b/configs/inetspace_v2_defconfig
index 53898a1..95dfa9c 100644
--- a/configs/inetspace_v2_defconfig
+++ b/configs/inetspace_v2_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NETSPACE_V2=y
@@ -9,6 +10,7 @@
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
new file mode 100644
index 0000000..5cb933d
--- /dev/null
+++ b/configs/j721e_evm_a72_defconfig
@@ -0,0 +1,84 @@
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SOC_K3_J721E=y
+CONFIG_TARGET_J721E_A72_EVM=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0x80080000
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-common-proc-board"
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_TI_SCI=y
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_GENERIC is not set
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_GENERIC is not set
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_TI_SCI=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig
new file mode 100644
index 0000000..b7168ec
--- /dev/null
+++ b/configs/j721e_evm_r5_defconfig
@@ -0,0 +1,94 @@
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x55000
+CONFIG_SOC_K3_J721E=y
+CONFIG_TARGET_J721E_R5_EVM=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0x41c00000
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_USE_BOOTCOMMAND=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_REMOTEPROC=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_REMOTEPROC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-r5-common-proc-board"
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_TI_SCI=y
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DM_GPIO=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_MISC=y
+CONFIG_FS_LOADER=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_GENERIC is not set
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_GENERIC is not set
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_K3_SYSTEM_CONTROLLER=y
+CONFIG_REMOTEPROC_TI_K3_ARM64=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_TI_SCI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_FS_EXT4=y
+CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
diff --git a/configs/jesurun_q5_defconfig b/configs/jesurun_q5_defconfig
index 3bd4a18..ab4a271 100644
--- a/configs/jesurun_q5_defconfig
+++ b/configs/jesurun_q5_defconfig
@@ -8,7 +8,7 @@
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig
index 14351bb..a4e6f9f 100644
--- a/configs/jetson-tk1_defconfig
+++ b/configs/jetson-tk1_defconfig
@@ -4,10 +4,10 @@
CONFIG_NR_DRAM_BANKS=2
CONFIG_TEGRA124=y
CONFIG_TARGET_JETSON_TK1=y
+CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
-CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_SYS_PROMPT="Tegra124 (Jetson TK1) # "
# CONFIG_CMD_IMI is not set
CONFIG_CMD_DFU=y
diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig
index 78864f2..2606055 100644
--- a/configs/k2e_evm_defconfig
+++ b/configs/k2e_evm_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_ISW_ENTRY_ADDR=0xC100000
CONFIG_SYS_TEXT_BASE=0xC000000
@@ -21,6 +22,8 @@
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
+CONFIG_MX_CYCLIC=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPIO is not set
# CONFIG_CMD_GPT is not set
@@ -42,6 +45,7 @@
CONFIG_MISC=y
# CONFIG_MMC is not set
CONFIG_NAND=y
+CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_DAVINCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/k2e_hs_evm_defconfig b/configs/k2e_hs_evm_defconfig
index 5fabbb4..98e3cde 100644
--- a/configs/k2e_hs_evm_defconfig
+++ b/configs/k2e_hs_evm_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_ISW_ENTRY_ADDR=0xC100000
@@ -14,6 +15,7 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_MX_CYCLIC=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPIO is not set
# CONFIG_CMD_GPT is not set
@@ -35,6 +37,7 @@
CONFIG_MISC=y
# CONFIG_MMC is not set
CONFIG_NAND=y
+CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_DAVINCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
index 48d7fdc..2780451 100644
--- a/configs/k2g_evm_defconfig
+++ b/configs/k2g_evm_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_ISW_ENTRY_ADDR=0xC0A0000
CONFIG_SYS_TEXT_BASE=0xC000000
@@ -21,6 +22,8 @@
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
+CONFIG_MX_CYCLIC=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPIO is not set
# CONFIG_CMD_GPT is not set
@@ -42,6 +45,7 @@
CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
+CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_DAVINCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/k2g_hs_evm_defconfig b/configs/k2g_hs_evm_defconfig
index 05f535b..f5f3678 100644
--- a/configs/k2g_hs_evm_defconfig
+++ b/configs/k2g_hs_evm_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_ISW_ENTRY_ADDR=0xC0A0000
@@ -14,6 +15,7 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_MX_CYCLIC=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPIO is not set
# CONFIG_CMD_GPT is not set
@@ -36,6 +38,7 @@
CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
+CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_DAVINCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig
index 12358d1..2d5f193 100644
--- a/configs/k2hk_evm_defconfig
+++ b/configs/k2hk_evm_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_ISW_ENTRY_ADDR=0xC200000
CONFIG_SYS_TEXT_BASE=0xC000000
@@ -21,6 +22,8 @@
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
+CONFIG_MX_CYCLIC=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPIO is not set
# CONFIG_CMD_GPT is not set
@@ -42,6 +45,7 @@
CONFIG_MISC=y
# CONFIG_MMC is not set
CONFIG_NAND=y
+CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_DAVINCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig
index 64537ce..8d67920 100644
--- a/configs/k2hk_hs_evm_defconfig
+++ b/configs/k2hk_hs_evm_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_ISW_ENTRY_ADDR=0xC200000
@@ -14,6 +15,7 @@
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_MX_CYCLIC=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPIO is not set
# CONFIG_CMD_GPT is not set
@@ -35,6 +37,7 @@
CONFIG_MISC=y
# CONFIG_MMC is not set
CONFIG_NAND=y
+CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_DAVINCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
index 1eef7f8..b0898b0 100644
--- a/configs/k2l_evm_defconfig
+++ b/configs/k2l_evm_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_ISW_ENTRY_ADDR=0xC100000
CONFIG_SYS_TEXT_BASE=0xC000000
@@ -21,6 +22,8 @@
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
+CONFIG_MX_CYCLIC=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPIO is not set
# CONFIG_CMD_GPT is not set
@@ -42,6 +45,7 @@
CONFIG_MISC=y
# CONFIG_MMC is not set
CONFIG_NAND=y
+CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_DAVINCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/k2l_hs_evm_defconfig b/configs/k2l_hs_evm_defconfig
index c412c6f..8b7089b 100644
--- a/configs/k2l_hs_evm_defconfig
+++ b/configs/k2l_hs_evm_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_ISW_ENTRY_ADDR=0xC100000
@@ -13,6 +14,7 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
+CONFIG_MX_CYCLIC=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPIO is not set
# CONFIG_CMD_GPT is not set
@@ -34,6 +36,7 @@
CONFIG_MISC=y
# CONFIG_MMC is not set
CONFIG_NAND=y
+CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_DAVINCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/kc1_defconfig b/configs/kc1_defconfig
index 0b21df1..37aa61c 100644
--- a/configs/kc1_defconfig
+++ b/configs/kc1_defconfig
@@ -5,10 +5,10 @@
CONFIG_TARGET_KC1=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x40300000
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SPL_TEXT_BASE=0x40300000
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=2
diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig
new file mode 100644
index 0000000..acfd91d
--- /dev/null
+++ b/configs/khadas-edge-captain-rk3399_defconfig
@@ -0,0 +1,61 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL_STACK_R_ADDR=0x80000
+CONFIG_DEBUG_UART_BASE=0xFF1A0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-captain.dtbi"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_TPL=y
+CONFIG_SYS_PROMPT="kedge# "
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-khadas-edge-captain"
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM_RK3399_LPDDR4=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig
new file mode 100644
index 0000000..b71fd3a
--- /dev/null
+++ b/configs/khadas-edge-rk3399_defconfig
@@ -0,0 +1,60 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL_STACK_R_ADDR=0x80000
+CONFIG_DEBUG_UART_BASE=0xFF1A0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_TPL=y
+CONFIG_SYS_PROMPT="kedge# "
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-khadas-edge"
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM_RK3399_LPDDR4=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig
new file mode 100644
index 0000000..0a78987
--- /dev/null
+++ b/configs/khadas-edge-v-rk3399_defconfig
@@ -0,0 +1,61 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL_STACK_R_ADDR=0x80000
+CONFIG_DEBUG_UART_BASE=0xFF1A0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-v.dtbi"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_TPL=y
+CONFIG_SYS_PROMPT="kedge# "
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-khadas-edge-v"
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM_RK3399_LPDDR4=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/km_kirkwood_128m16_defconfig b/configs/km_kirkwood_128m16_defconfig
index 0bd9a7f..1ba69fc 100644
--- a/configs/km_kirkwood_128m16_defconfig
+++ b/configs/km_kirkwood_128m16_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
diff --git a/configs/km_kirkwood_defconfig b/configs/km_kirkwood_defconfig
index 08b8825..df0c9d3 100644
--- a/configs/km_kirkwood_defconfig
+++ b/configs/km_kirkwood_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
diff --git a/configs/km_kirkwood_pci_defconfig b/configs/km_kirkwood_pci_defconfig
index 5abf543..c5020ca 100644
--- a/configs/km_kirkwood_pci_defconfig
+++ b/configs/km_kirkwood_pci_defconfig
@@ -1,8 +1,10 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
+CONFIG_KM_FPGA_CONFIG=y
CONFIG_IDENT_STRING="\nKeymile Kirkwood PCI"
CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_PCI"
CONFIG_MISC_INIT_R=y
diff --git a/configs/kmcoge5un_defconfig b/configs/kmcoge5un_defconfig
index b6ac31e..c3510c4 100644
--- a/configs/kmcoge5un_defconfig
+++ b/configs/kmcoge5un_defconfig
@@ -1,8 +1,12 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
+CONFIG_PIGGY_MAC_ADRESS_OFFSET=3
+CONFIG_KM_ENV_IS_IN_SPI_NOR=y
+CONFIG_KM_PIGGY4_88E6352=y
CONFIG_IDENT_STRING="\nKeymile COGE5UN"
CONFIG_SYS_EXTRA_OPTIONS="KM_COGE5UN"
CONFIG_MISC_INIT_R=y
diff --git a/configs/kmlion1_defconfig b/configs/kmlion1_defconfig
deleted file mode 100644
index 6675c31..0000000
--- a/configs/kmlion1_defconfig
+++ /dev/null
@@ -1,57 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xfff40000
-CONFIG_SYS_BOOTCOUNT_ADDR=0xFB000020
-CONFIG_MPC85xx=y
-CONFIG_TARGET_KMP204X=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="KMLION1"
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_LAST_STAGE_INIT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
-CONFIG_AUTOBOOT_STOP_STR=" "
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=fsl_elbc_nand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fsl_elbc_nand:-(ubi0);"
-# CONFIG_CMD_IRQ is not set
-CONFIG_CMD_UBI=y
-# CONFIG_CMD_UBIFS is not set
-CONFIG_DOS_PARTITION=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_BOOTCOUNT_BOOTLIMIT=3
-# CONFIG_MMC is not set
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=20000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_BCH=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/kmnusa_defconfig b/configs/kmnusa_defconfig
index 08e9b75..bcdf97c 100644
--- a/configs/kmnusa_defconfig
+++ b/configs/kmnusa_defconfig
@@ -1,8 +1,12 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
+CONFIG_KM_FPGA_CONFIG=y
+CONFIG_KM_ENV_IS_IN_SPI_NOR=y
+CONFIG_KM_PIGGY4_88E6352=y
CONFIG_IDENT_STRING="\nKeymile NUSA"
CONFIG_SYS_EXTRA_OPTIONS="KM_NUSA"
CONFIG_MISC_INIT_R=y
@@ -38,6 +42,7 @@
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=8100000
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_MV88E6352_SWITCH=y
CONFIG_MVGBE=y
CONFIG_MII=y
CONFIG_SYS_NS16550=y
diff --git a/configs/kmsugp1_defconfig b/configs/kmsugp1_defconfig
index cafc1f9..2f123bd 100644
--- a/configs/kmsugp1_defconfig
+++ b/configs/kmsugp1_defconfig
@@ -1,8 +1,12 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
+CONFIG_KM_FPGA_CONFIG=y
+CONFIG_KM_ENV_IS_IN_SPI_NOR=y
+CONFIG_KM_PIGGY4_88E6352=y
CONFIG_IDENT_STRING="\nKeymile SUGP1"
CONFIG_SYS_EXTRA_OPTIONS="KM_SUGP1"
CONFIG_MISC_INIT_R=y
@@ -38,6 +42,7 @@
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=8100000
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_MV88E6352_SWITCH=y
CONFIG_MVGBE=y
CONFIG_MII=y
CONFIG_SYS_NS16550=y
diff --git a/configs/kmsuv31_defconfig b/configs/kmsuv31_defconfig
index 14c1c16..2c9c9bb 100644
--- a/configs/kmsuv31_defconfig
+++ b/configs/kmsuv31_defconfig
@@ -1,8 +1,11 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
+CONFIG_KM_FPGA_CONFIG=y
+CONFIG_KM_ENV_IS_IN_SPI_NOR=y
CONFIG_IDENT_STRING="\nKeymile SUV31"
CONFIG_SYS_EXTRA_OPTIONS="KM_SUV31"
CONFIG_MISC_INIT_R=y
diff --git a/configs/kmvect1_defconfig b/configs/kmvect1_defconfig
deleted file mode 100644
index 6f2f732..0000000
--- a/configs/kmvect1_defconfig
+++ /dev/null
@@ -1,180 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xF0000000
-CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
-CONFIG_SYS_CLK_FREQ=66000000
-CONFIG_MPC83xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_KMVECT1=y
-CONFIG_SYSTEM_PLL_VCO_DIV_2=y
-CONFIG_CORE_PLL_RATIO_2_1=y
-CONFIG_QUICC_MULT_FACTOR_3=y
-CONFIG_BOOT_MEMORY_SPACE_LOW=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="SDRAM"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_256_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_ICACHE_INHIBITED=y
-CONFIG_BAT0_ICACHE_GUARDED=y
-CONFIG_BAT0_DCACHE_INHIBITED=y
-CONFIG_BAT0_DCACHE_GUARDED=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT1=y
-CONFIG_BAT1_NAME="IMMR"
-CONFIG_BAT1_BASE=0xE0000000
-CONFIG_BAT1_LENGTH_4_MBYTES=y
-CONFIG_BAT1_ACCESS_RW=y
-CONFIG_BAT1_ICACHE_INHIBITED=y
-CONFIG_BAT1_ICACHE_GUARDED=y
-CONFIG_BAT1_DCACHE_INHIBITED=y
-CONFIG_BAT1_DCACHE_GUARDED=y
-CONFIG_BAT1_USER_MODE_VALID=y
-CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT2=y
-CONFIG_BAT2_NAME="KMBEC_FPGA"
-CONFIG_BAT2_BASE=0xE8000000
-CONFIG_BAT2_LENGTH_128_MBYTES=y
-CONFIG_BAT2_ACCESS_RW=y
-CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT2_DCACHE_INHIBITED=y
-CONFIG_BAT2_DCACHE_GUARDED=y
-CONFIG_BAT2_USER_MODE_VALID=y
-CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT3=y
-CONFIG_BAT3_NAME="FLASH"
-CONFIG_BAT3_BASE=0xF0000000
-CONFIG_BAT3_LENGTH_256_MBYTES=y
-CONFIG_BAT3_ACCESS_RW=y
-CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT3_DCACHE_INHIBITED=y
-CONFIG_BAT3_DCACHE_GUARDED=y
-CONFIG_BAT3_USER_MODE_VALID=y
-CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT4=y
-CONFIG_BAT4_NAME="STACK_IN_DCACHE"
-CONFIG_BAT4_BASE=0xE6000000
-CONFIG_BAT4_ACCESS_RW=y
-CONFIG_BAT4_USER_MODE_VALID=y
-CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT5=y
-CONFIG_BAT5_NAME="APP1"
-CONFIG_BAT5_BASE=0xA0000000
-CONFIG_BAT5_LENGTH_256_MBYTES=y
-CONFIG_BAT5_ACCESS_RW=y
-CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT5_DCACHE_INHIBITED=y
-CONFIG_BAT5_DCACHE_GUARDED=y
-CONFIG_BAT5_USER_MODE_VALID=y
-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT6=y
-CONFIG_BAT6_NAME="APP2"
-CONFIG_BAT6_BASE=0xB0000000
-CONFIG_BAT6_LENGTH_256_MBYTES=y
-CONFIG_BAT6_ACCESS_RW=y
-CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_DCACHE_INHIBITED=y
-CONFIG_BAT6_DCACHE_GUARDED=y
-CONFIG_BAT6_USER_MODE_VALID=y
-CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xF0000000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_256_MBYTES=y
-CONFIG_LBLAW1=y
-CONFIG_LBLAW1_BASE=0xE8000000
-CONFIG_LBLAW1_NAME="KMBEC_FPGA"
-CONFIG_LBLAW1_LENGTH_128_MBYTES=y
-CONFIG_LBLAW2=y
-CONFIG_LBLAW2_BASE=0xA0000000
-CONFIG_LBLAW2_NAME="APP1"
-CONFIG_LBLAW2_LENGTH_256_MBYTES=y
-CONFIG_LBLAW3=y
-CONFIG_LBLAW3_BASE=0xB0000000
-CONFIG_LBLAW3_NAME="APP2"
-CONFIG_LBLAW3_LENGTH_256_MBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xF0000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_256_MBYTES=y
-CONFIG_OR0_SCY_5=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
-CONFIG_BR1_OR1_BASE=0xE8000000
-CONFIG_OR1_AM_128_MBYTES=y
-CONFIG_OR1_SCY_2=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="APP1"
-CONFIG_BR2_OR2_BASE=0xA0000000
-CONFIG_BR2_PORTSIZE_16BIT=y
-CONFIG_BR2_MACHINE_UPMA=y
-CONFIG_OR2_AM_256_MBYTES=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="APP2"
-CONFIG_BR3_OR3_BASE=0xB0000000
-CONFIG_BR3_PORTSIZE_16BIT=y
-CONFIG_OR3_AM_256_MBYTES=y
-CONFIG_OR3_SCY_3=y
-CONFIG_OR3_CSNT_EARLIER=y
-CONFIG_OR3_ACS_QUARTER_CYCLE_EARLIER=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_HID0_FINAL_EMCP=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_ACR_PIPE_DEP_4=y
-CONFIG_ACR_RPTCNT_4=y
-CONFIG_ACR_APARK_MASTER=y
-CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
-CONFIG_LCRR_EADC_1=y
-CONFIG_LCRR_CLKDIV_2=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="KMVECT1"
-CONFIG_MISC_INIT_R=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_LAST_STAGE_INIT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
-CONFIG_AUTOBOOT_STOP_STR=" "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=boot"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);"
-CONFIG_CMD_DIAG=y
-CONFIG_CMD_UBI=y
-# CONFIG_CMD_UBIFS is not set
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_BOOTCOUNT_BOOTLIMIT=3
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_MTD_DEVICE=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-# CONFIG_PCI is not set
-CONFIG_QE=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig
index 23d11df..393a1c6 100644
--- a/configs/koelsch_defconfig
+++ b/configs/koelsch_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
@@ -16,15 +17,16 @@
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0xe6300000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_TEXT_BASE=0xe6300000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
diff --git a/configs/kp_imx53_defconfig b/configs/kp_imx53_defconfig
index a6a727b..ea6f8f6 100644
--- a/configs/kp_imx53_defconfig
+++ b/configs/kp_imx53_defconfig
@@ -31,7 +31,7 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_DEFAULT_BUS_NUMBER=0x1
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_PHY_SMSC=y
CONFIG_FEC_MXC=y
@@ -47,3 +47,5 @@
CONFIG_USB=y
CONFIG_USB_EHCI_MX5=y
CONFIG_USB_STORAGE=y
+CONFIG_HEXDUMP=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/kp_imx6q_tpc_defconfig b/configs/kp_imx6q_tpc_defconfig
index 0ca83cb..75dd9d7 100644
--- a/configs/kp_imx6q_tpc_defconfig
+++ b/configs/kp_imx6q_tpc_defconfig
@@ -10,6 +10,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
@@ -17,7 +18,6 @@
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_BOUNCE_BUFFER=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_AUTOBOOT_KEYED=y
@@ -34,6 +34,7 @@
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
CONFIG_FEC_MXC=y
diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig
index 921af0d..dc58707 100644
--- a/configs/kylin-rk3036_defconfig
+++ b/configs/kylin-rk3036_defconfig
@@ -12,12 +12,13 @@
CONFIG_DEBUG_UART_BASE=0x20068000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0x10081000
# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3036-kylin.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_TEXT_BASE=0x10081000
CONFIG_SPL_STACK_R=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
@@ -25,6 +26,7 @@
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
@@ -46,11 +48,13 @@
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_PINCTRL=y
CONFIG_DM_REGULATOR_FIXED=y
# CONFIG_SPL_DM_SERIAL is not set
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
+# CONFIG_SPL_SYSRESET is not set
CONFIG_USB=y
CONFIG_USB_DWC2=y
CONFIG_USB_GADGET=y
@@ -58,7 +62,6 @@
CONFIG_USB_GADGET_VENDOR_NUM=0x2207
CONFIG_USB_GADGET_PRODUCT_NUM=0x310a
CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USB_FUNCTION_MASS_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_SMSC95XX=y
diff --git a/configs/kzm9g_defconfig b/configs/kzm9g_defconfig
index 032246a..94f77cf 100644
--- a/configs/kzm9g_defconfig
+++ b/configs/kzm9g_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0x00000000
diff --git a/configs/lager_defconfig b/configs/lager_defconfig
index c056054..c3a9647 100644
--- a/configs/lager_defconfig
+++ b/configs/lager_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
@@ -16,15 +17,16 @@
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0xe6300000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_TEXT_BASE=0xe6300000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
diff --git a/configs/legoev3_defconfig b/configs/legoev3_defconfig
index 32cd52c..0f9f624 100644
--- a/configs/legoev3_defconfig
+++ b/configs/legoev3_defconfig
@@ -14,6 +14,7 @@
CONFIG_AUTOBOOT_STOP_STR="l"
CONFIG_CMD_ASKENV=y
CONFIG_CRC32_VERIFY=y
+CONFIG_MX_CYCLIC=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@@ -23,12 +24,19 @@
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_DIAG=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="da850-lego-ev3"
+CONFIG_DM=y
+# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_SYS_I2C_DAVINCI=y
+CONFIG_DM_MMC=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_DAVINCI_SPI=y
-CONFIG_OF_LIBFDT=y
# CONFIG_EFI_LOADER is not set
diff --git a/configs/libretech-ac_defconfig b/configs/libretech-ac_defconfig
index 55785a3..f4f7b06 100644
--- a/configs/libretech-ac_defconfig
+++ b/configs/libretech-ac_defconfig
@@ -9,6 +9,8 @@
CONFIG_IDENT_STRING=" libretech-ac"
CONFIG_DEBUG_UART=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="usb start"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/libretech_all_h3_cc_h2_plus_defconfig b/configs/libretech_all_h3_cc_h2_plus_defconfig
index 7d7f542..d9c9b6d 100644
--- a/configs/libretech_all_h3_cc_h2_plus_defconfig
+++ b/configs/libretech_all_h3_cc_h2_plus_defconfig
@@ -6,7 +6,7 @@
CONFIG_DRAM_CLK=672
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/libretech_all_h3_cc_h3_defconfig b/configs/libretech_all_h3_cc_h3_defconfig
index be82721..e99dc5c 100644
--- a/configs/libretech_all_h3_cc_h3_defconfig
+++ b/configs/libretech_all_h3_cc_h3_defconfig
@@ -6,7 +6,7 @@
CONFIG_DRAM_CLK=672
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/libretech_all_h3_cc_h5_defconfig b/configs/libretech_all_h3_cc_h5_defconfig
index ed2c6d5..088246d 100644
--- a/configs/libretech_all_h3_cc_h5_defconfig
+++ b/configs/libretech_all_h3_cc_h5_defconfig
@@ -6,7 +6,7 @@
CONFIG_DRAM_CLK=672
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x10060
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/linkit-smart-7688-ram_defconfig b/configs/linkit-smart-7688-ram_defconfig
index 7d7cdf0..8402147 100644
--- a/configs/linkit-smart-7688-ram_defconfig
+++ b/configs/linkit-smart-7688-ram_defconfig
@@ -7,7 +7,7 @@
CONFIG_MIPS_BOOT_FDT=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
-CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
@@ -54,7 +54,6 @@
CONFIG_POWER_DOMAIN=y
CONFIG_RAM=y
CONFIG_DM_RESET=y
-# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_MT7621_SPI=y
diff --git a/configs/linkit-smart-7688_defconfig b/configs/linkit-smart-7688_defconfig
index b3acbbc..5d80051 100644
--- a/configs/linkit-smart-7688_defconfig
+++ b/configs/linkit-smart-7688_defconfig
@@ -10,7 +10,7 @@
CONFIG_MIPS_BOOT_FDT=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
-CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
@@ -58,7 +58,6 @@
CONFIG_POWER_DOMAIN=y
CONFIG_RAM=y
CONFIG_DM_RESET=y
-# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_MT7621_SPI=y
diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig
index 75e8583..1c87416 100644
--- a/configs/lion-rk3368_defconfig
+++ b/configs/lion-rk3368_defconfig
@@ -1,9 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3368=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
CONFIG_TPL_LIBCOMMON_SUPPORT=y
@@ -18,6 +15,7 @@
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SMBIOS_PRODUCT_NAME="sheep_rk3368"
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0x00000000
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -31,16 +29,13 @@
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_ARCH_EARLY_INIT_R=y
-CONFIG_SPL_TEXT_BASE=0x00000000
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_TPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
CONFIG_SPL_ATF=y
CONFIG_TPL=y
-CONFIG_TPL_BOOTROM_SUPPORT=y
CONFIG_TPL_DRIVERS_MISC_SUPPORT=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
@@ -91,11 +86,6 @@
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
-CONFIG_TIMER=y
-CONFIG_SPL_TIMER=y
-CONFIG_TPL_TIMER=y
-CONFIG_ROCKCHIP_TIMER=y
-CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_LZO=y
CONFIG_ERRNO_STR=y
diff --git a/configs/liteboard_defconfig b/configs/liteboard_defconfig
index a439631..0edfa09 100644
--- a/configs/liteboard_defconfig
+++ b/configs/liteboard_defconfig
@@ -9,13 +9,13 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=1
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="imx6ul-liteboard.dtb"
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@@ -39,7 +39,7 @@
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_DM_ETH=y
CONFIG_MII=y
diff --git a/configs/ls1012a2g5rdb_tfa_defconfig b/configs/ls1012a2g5rdb_tfa_defconfig
index 5428357..852cc56 100644
--- a/configs/ls1012a2g5rdb_tfa_defconfig
+++ b/configs/ls1012a2g5rdb_tfa_defconfig
@@ -1,8 +1,8 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1012A2G5RDB=y
+CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_QSPI_AHB_INIT=y
-CONFIG_TFABOOT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
diff --git a/configs/ls1012afrdm_tfa_defconfig b/configs/ls1012afrdm_tfa_defconfig
index 3de0a98..0e1d152 100644
--- a/configs/ls1012afrdm_tfa_defconfig
+++ b/configs/ls1012afrdm_tfa_defconfig
@@ -1,8 +1,8 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1012AFRDM=y
+CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_QSPI_AHB_INIT=y
-CONFIG_TFABOOT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
index a4ae87b..3b1568f 100644
--- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
@@ -31,6 +31,7 @@
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
diff --git a/configs/ls1012afrwy_qspi_defconfig b/configs/ls1012afrwy_qspi_defconfig
index aa3256f..08eedec 100644
--- a/configs/ls1012afrwy_qspi_defconfig
+++ b/configs/ls1012afrwy_qspi_defconfig
@@ -32,6 +32,7 @@
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
index 827d4ec..640a462 100644
--- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
@@ -1,8 +1,8 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1012AFRWY=y
+CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SECURE_BOOT=y
-CONFIG_TFABOOT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
@@ -31,6 +31,7 @@
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig
index cbeb9ca..65ed34e 100644
--- a/configs/ls1012afrwy_tfa_defconfig
+++ b/configs/ls1012afrwy_tfa_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1012AFRWY=y
-CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_TFABOOT=y
+CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
@@ -32,6 +32,7 @@
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
index ebd3eea..f011aa0 100644
--- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
@@ -1,9 +1,9 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1012AQDS=y
+CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SECURE_BOOT=y
CONFIG_QSPI_AHB_INIT=y
-CONFIG_TFABOOT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig
index 3a99037..0379b61 100644
--- a/configs/ls1012aqds_tfa_defconfig
+++ b/configs/ls1012aqds_tfa_defconfig
@@ -1,8 +1,8 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1012AQDS=y
+CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_QSPI_AHB_INIT=y
-CONFIG_TFABOOT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
index 8e2ff1f..f3a2a13 100644
--- a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
@@ -1,9 +1,9 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1012ARDB=y
+CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SECURE_BOOT=y
CONFIG_QSPI_AHB_INIT=y
-CONFIG_TFABOOT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig
index 8acc07d..d3b38ce 100644
--- a/configs/ls1012ardb_tfa_defconfig
+++ b/configs/ls1012ardb_tfa_defconfig
@@ -1,8 +1,8 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1012ARDB=y
+CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_QSPI_AHB_INIT=y
-CONFIG_TFABOOT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
@@ -34,6 +34,7 @@
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DM_MMC=y
+CONFIG_MMC_HS200_SUPPORT=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig
index 93eb834..1e8d49a 100644
--- a/configs/ls1021aiot_sdcard_defconfig
+++ b/configs/ls1021aiot_sdcard_defconfig
@@ -5,10 +5,10 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT,SD_BOOT_QSPI"
CONFIG_MISC_INIT_R=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_CMD_BOOTZ=y
diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig
index 3e0075d..f2aafa9 100644
--- a/configs/ls1021aqds_nand_defconfig
+++ b/configs/ls1021aqds_nand_defconfig
@@ -8,6 +8,7 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -19,7 +20,6 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y
-CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig
index daabf76..445eb04 100644
--- a/configs/ls1021aqds_sdcard_ifc_defconfig
+++ b/configs/ls1021aqds_sdcard_ifc_defconfig
@@ -9,6 +9,7 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT"
@@ -18,7 +19,6 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y
-CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig
index cc71c28..d12c427 100644
--- a/configs/ls1021aqds_sdcard_qspi_defconfig
+++ b/configs/ls1021aqds_sdcard_qspi_defconfig
@@ -9,6 +9,7 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SD_BOOT,SD_BOOT_QSPI"
@@ -18,7 +19,6 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y
-CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls1021atsn_qspi_defconfig b/configs/ls1021atsn_qspi_defconfig
new file mode 100644
index 0000000..0565d44
--- /dev/null
+++ b/configs/ls1021atsn_qspi_defconfig
@@ -0,0 +1,56 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1021ATSN=y
+CONFIG_SYS_TEXT_BASE=0x40100000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_QSPI_BOOT=y
+CONFIG_BOOTDELAY=3
+CONFIG_SILENT_CONSOLE=y
+CONFIG_MISC_INIT_R=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_FS_UUID=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="ls1021a-tsn"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DM=y
+CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_FIXED=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_MII=y
+CONFIG_TSEC_ENET=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig
new file mode 100644
index 0000000..f28967c
--- /dev/null
+++ b/configs/ls1021atsn_sdcard_defconfig
@@ -0,0 +1,68 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1021ATSN=y
+CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0x10000000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
+CONFIG_SD_BOOT=y
+CONFIG_BOOTDELAY=3
+CONFIG_SILENT_CONSOLE=y
+CONFIG_MISC_INIT_R=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_FS_UUID=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="ls1021a-tsn"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DM=y
+CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_FIXED=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_MII=y
+CONFIG_TSEC_ENET=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
index 6c4bb9a..8871c61 100644
--- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
@@ -37,6 +37,8 @@
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig
index 9d8c202..a5aaa9a 100644
--- a/configs/ls1021atwr_nor_defconfig
+++ b/configs/ls1021atwr_nor_defconfig
@@ -37,6 +37,8 @@
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig
index b9cfdb6..fe0f6c4 100644
--- a/configs/ls1021atwr_nor_lpuart_defconfig
+++ b/configs/ls1021atwr_nor_lpuart_defconfig
@@ -39,6 +39,8 @@
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig
index 8c27c59..0e2525f 100644
--- a/configs/ls1021atwr_qspi_defconfig
+++ b/configs/ls1021atwr_qspi_defconfig
@@ -39,6 +39,8 @@
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
index 979878d..8277d6a 100644
--- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
@@ -9,6 +9,7 @@
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -22,7 +23,6 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y
-CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_CRYPTO_SUPPORT=y
@@ -50,6 +50,8 @@
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig
index 59af172..f07820a 100644
--- a/configs/ls1021atwr_sdcard_ifc_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_defconfig
@@ -8,6 +8,7 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -22,7 +23,6 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y
-CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
@@ -51,6 +51,8 @@
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig
index d7fec5e..7a9c877 100644
--- a/configs/ls1021atwr_sdcard_qspi_defconfig
+++ b/configs/ls1021atwr_sdcard_qspi_defconfig
@@ -8,6 +8,7 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -22,7 +23,6 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y
-CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
@@ -50,6 +50,8 @@
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
index 7cd2f59..3170d81 100644
--- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
@@ -1,14 +1,14 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1028AQDS=y
+CONFIG_TFABOOT=y
+CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_SECURE_BOOT=y
CONFIG_SYS_FSL_SDHC_CLK_DIV=1
-CONFIG_TFABOOT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
@@ -31,21 +31,34 @@
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_I2C_DEFAULT_BUS_NUMBER=0
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
+CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
-CONFIG_PHY_GIGE=y
+CONFIG_DM_MDIO=y
CONFIG_E1000=y
+CONFIG_FSL_ENETC=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_PCF2127=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig
index 7982ce4..2da7b1d 100644
--- a/configs/ls1028aqds_tfa_defconfig
+++ b/configs/ls1028aqds_tfa_defconfig
@@ -1,13 +1,13 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1028AQDS=y
-CONFIG_SYS_FSL_SDHC_CLK_DIV=1
CONFIG_TFABOOT=y
+CONFIG_SYS_MALLOC_F_LEN=0x6000
+CONFIG_SYS_FSL_SDHC_CLK_DIV=1
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
@@ -34,22 +34,34 @@
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_I2C_DEFAULT_BUS_NUMBER=0
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
+CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
-CONFIG_PHY_GIGE=y
+CONFIG_DM_MDIO=y
CONFIG_E1000=y
+CONFIG_FSL_ENETC=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_PCF2127=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
index 3432f90..c1e88b5 100644
--- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
@@ -1,14 +1,14 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1028ARDB=y
+CONFIG_TFABOOT=y
+CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_SECURE_BOOT=y
CONFIG_SYS_FSL_SDHC_CLK_DIV=1
-CONFIG_TFABOOT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
@@ -31,7 +31,14 @@
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_I2C_DEFAULT_BUS_NUMBER=0
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
@@ -39,13 +46,19 @@
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FSL_ENETC=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_PCF2127=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig
index c65e37d..5ff3404 100644
--- a/configs/ls1028ardb_tfa_defconfig
+++ b/configs/ls1028ardb_tfa_defconfig
@@ -1,13 +1,13 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1028ARDB=y
-CONFIG_SYS_FSL_SDHC_CLK_DIV=1
CONFIG_TFABOOT=y
+CONFIG_SYS_MALLOC_F_LEN=0x6000
+CONFIG_SYS_FSL_SDHC_CLK_DIV=1
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
@@ -34,7 +34,15 @@
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_I2C_DEFAULT_BUS_NUMBER=0
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
CONFIG_DM_MMC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
@@ -42,14 +50,19 @@
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FSL_ENETC=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_PCF2127=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig
index 10d08f8..551176f 100644
--- a/configs/ls1043aqds_nand_defconfig
+++ b/configs/ls1043aqds_nand_defconfig
@@ -9,6 +9,7 @@
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -19,7 +20,6 @@
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_MISC_INIT_R=y
-CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig
index ff37969..cc99877 100644
--- a/configs/ls1043aqds_qspi_defconfig
+++ b/configs/ls1043aqds_qspi_defconfig
@@ -35,6 +35,7 @@
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
CONFIG_PHYLIB=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
@@ -47,6 +48,7 @@
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig
index 5ab5ef6..3506b31 100644
--- a/configs/ls1043aqds_sdcard_ifc_defconfig
+++ b/configs/ls1043aqds_sdcard_ifc_defconfig
@@ -10,6 +10,7 @@
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -20,7 +21,6 @@
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_MISC_INIT_R=y
-CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig
index 3f5af93..4343eb5 100644
--- a/configs/ls1043aqds_sdcard_qspi_defconfig
+++ b/configs/ls1043aqds_sdcard_qspi_defconfig
@@ -10,6 +10,7 @@
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -20,7 +21,6 @@
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_MISC_INIT_R=y
-CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
CONFIG_SPL_ENV_SUPPORT=y
@@ -49,6 +49,7 @@
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
CONFIG_PHYLIB=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
@@ -61,6 +62,7 @@
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
index 16ba82d..472786a 100644
--- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
@@ -1,8 +1,8 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1043AQDS=y
+CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SECURE_BOOT=y
-CONFIG_TFABOOT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig
index 19529f5..b49ac2c 100644
--- a/configs/ls1043aqds_tfa_defconfig
+++ b/configs/ls1043aqds_tfa_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1043AQDS=y
-CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_TFABOOT=y
+CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
@@ -47,6 +47,7 @@
CONFIG_SYS_FLASH_CFI=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=1
+# CONFIG_SPI_FLASH_BAR is not set
CONFIG_PHYLIB=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
@@ -58,6 +59,7 @@
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
index a336dc1..7aa8c54 100644
--- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
@@ -9,6 +9,7 @@
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -19,7 +20,6 @@
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_MISC_INIT_R=y
-CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
CONFIG_SPL_CRYPTO_SUPPORT=y
@@ -67,6 +67,7 @@
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+# CONFIG_USE_TINY_PRINTF is not set
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig
index 41b94d3..22ccf52 100644
--- a/configs/ls1043ardb_nand_defconfig
+++ b/configs/ls1043ardb_nand_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -18,7 +19,6 @@
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_MISC_INIT_R=y
-CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
@@ -67,4 +67,5 @@
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+# CONFIG_USE_TINY_PRINTF is not set
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
index 05898d8..486a2e0 100644
--- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
@@ -10,6 +10,7 @@
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -19,7 +20,6 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
CONFIG_MISC_INIT_R=y
-CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
CONFIG_SPL_CRYPTO_SUPPORT=y
@@ -65,6 +65,7 @@
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+# CONFIG_USE_TINY_PRINTF is not set
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig
index 71709bc..b3c2970 100644
--- a/configs/ls1043ardb_sdcard_defconfig
+++ b/configs/ls1043ardb_sdcard_defconfig
@@ -9,6 +9,7 @@
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -18,7 +19,6 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
CONFIG_MISC_INIT_R=y
-CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
@@ -65,4 +65,5 @@
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+# CONFIG_USE_TINY_PRINTF is not set
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
index 2f80e71..5c8257d 100644
--- a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
@@ -1,8 +1,8 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1043ARDB=y
+CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SECURE_BOOT=y
-CONFIG_TFABOOT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig
index 80cc2b9..75bb52a 100644
--- a/configs/ls1043ardb_tfa_defconfig
+++ b/configs/ls1043ardb_tfa_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1043ARDB=y
-CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_TFABOOT=y
+CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig
index 0b94b01..1d27408 100644
--- a/configs/ls1046afrwy_tfa_defconfig
+++ b/configs/ls1046afrwy_tfa_defconfig
@@ -1,8 +1,8 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1046AFRWY=y
+CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_QSPI_AHB_INIT=y
-CONFIG_TFABOOT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig
index a6b6866..75f9ebf 100644
--- a/configs/ls1046aqds_nand_defconfig
+++ b/configs/ls1046aqds_nand_defconfig
@@ -6,6 +6,7 @@
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -16,7 +17,6 @@
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_MISC_INIT_R=y
-CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig
index 77dc0b0..3e537ec 100644
--- a/configs/ls1046aqds_sdcard_ifc_defconfig
+++ b/configs/ls1046aqds_sdcard_ifc_defconfig
@@ -10,6 +10,7 @@
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -20,7 +21,6 @@
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_MISC_INIT_R=y
-CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig
index 723a04f..7adaf6b 100644
--- a/configs/ls1046aqds_sdcard_qspi_defconfig
+++ b/configs/ls1046aqds_sdcard_qspi_defconfig
@@ -10,6 +10,7 @@
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -20,7 +21,6 @@
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:2m(uboot),14m(free)"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_MISC_INIT_R=y
-CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
index 0dbc770..2b4f72f 100644
--- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
@@ -1,8 +1,8 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1046AQDS=y
+CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SECURE_BOOT=y
-CONFIG_TFABOOT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig
index 17f3ba1..6449d3a 100644
--- a/configs/ls1046aqds_tfa_defconfig
+++ b/configs/ls1046aqds_tfa_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1046AQDS=y
-CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_TFABOOT=y
+CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig
index 855edc7..4467239 100644
--- a/configs/ls1046ardb_emmc_defconfig
+++ b/configs/ls1046ardb_emmc_defconfig
@@ -10,6 +10,7 @@
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -20,7 +21,6 @@
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_MISC_INIT_R=y
-CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
diff --git a/configs/ls1046ardb_qspi_spl_defconfig b/configs/ls1046ardb_qspi_spl_defconfig
index 6326c47..41c9988 100644
--- a/configs/ls1046ardb_qspi_spl_defconfig
+++ b/configs/ls1046ardb_qspi_spl_defconfig
@@ -11,6 +11,7 @@
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
@@ -20,7 +21,6 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
CONFIG_MISC_INIT_R=y
-CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
index 7bf23ad..fcc3632 100644
--- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
@@ -10,6 +10,7 @@
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -19,7 +20,6 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
CONFIG_MISC_INIT_R=y
-CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
CONFIG_SPL_CRYPTO_SUPPORT=y
diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig
index 829861b..f3b2f61 100644
--- a/configs/ls1046ardb_sdcard_defconfig
+++ b/configs/ls1046ardb_sdcard_defconfig
@@ -10,6 +10,7 @@
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -19,7 +20,6 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
CONFIG_MISC_INIT_R=y
-CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
diff --git a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
index 1365725..9423d7d 100644
--- a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
@@ -1,9 +1,9 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1046ARDB=y
+CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SECURE_BOOT=y
CONFIG_QSPI_AHB_INIT=y
-CONFIG_TFABOOT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig
index 816c628..1aca8ef 100644
--- a/configs/ls1046ardb_tfa_defconfig
+++ b/configs/ls1046ardb_tfa_defconfig
@@ -1,8 +1,8 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1046ARDB=y
+CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_QSPI_AHB_INIT=y
-CONFIG_TFABOOT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
diff --git a/configs/ls1088aqds_sdcard_ifc_defconfig b/configs/ls1088aqds_sdcard_ifc_defconfig
index 58a6795..2293081 100644
--- a/configs/ls1088aqds_sdcard_ifc_defconfig
+++ b/configs/ls1088aqds_sdcard_ifc_defconfig
@@ -10,6 +10,7 @@
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0x1800a000
# CONFIG_SYS_MALLOC_F is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
@@ -18,7 +19,6 @@
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0x1800a000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig
index 5b5cbfa..5fd9b94 100644
--- a/configs/ls1088aqds_sdcard_qspi_defconfig
+++ b/configs/ls1088aqds_sdcard_qspi_defconfig
@@ -10,6 +10,7 @@
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0x1800a000
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
@@ -21,7 +22,6 @@
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0x1800a000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig
index ff820a5..145beea 100644
--- a/configs/ls1088aqds_tfa_defconfig
+++ b/configs/ls1088aqds_tfa_defconfig
@@ -1,14 +1,14 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1088AQDS=y
-CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_QSPI_AHB_INIT=y
CONFIG_TFABOOT=y
+CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_F_LEN=0x6000
+CONFIG_QSPI_AHB_INIT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
@@ -36,6 +36,12 @@
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_I2C_DEFAULT_BUS_NUMBER=0
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
@@ -53,6 +59,8 @@
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_PCF2127=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
index 3d53129..079ef9d 100644
--- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
@@ -10,6 +10,7 @@
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x1800a000
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
@@ -22,7 +23,6 @@
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0x1800a000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
CONFIG_SPL_CRYPTO_SUPPORT=y
diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig
index 51b74e7..9dbaae6 100644
--- a/configs/ls1088ardb_sdcard_qspi_defconfig
+++ b/configs/ls1088ardb_sdcard_qspi_defconfig
@@ -10,6 +10,7 @@
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0x1800a000
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
@@ -22,7 +23,6 @@
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0x1800a000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
index 3c4437d..45df134 100644
--- a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
@@ -1,15 +1,15 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1088ARDB=y
+CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_SECURE_BOOT=y
CONFIG_QSPI_AHB_INIT=y
-CONFIG_TFABOOT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
@@ -34,6 +34,12 @@
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_I2C_DEFAULT_BUS_NUMBER=0
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
@@ -47,6 +53,8 @@
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_PCF2127=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig
index 8cea8c7..b7c40a4 100644
--- a/configs/ls1088ardb_tfa_defconfig
+++ b/configs/ls1088ardb_tfa_defconfig
@@ -1,14 +1,14 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1088ARDB=y
-CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_QSPI_AHB_INIT=y
CONFIG_TFABOOT=y
+CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_F_LEN=0x6000
+CONFIG_QSPI_AHB_INIT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
@@ -35,6 +35,12 @@
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_I2C_DEFAULT_BUS_NUMBER=0
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
@@ -48,6 +54,8 @@
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_PCF2127=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig
index 3a36941..33a75ac 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -8,6 +8,7 @@
CONFIG_NR_DRAM_BANKS=3
CONFIG_SPL=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0x1800a000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -17,7 +18,6 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SPL_TEXT_BASE=0x1800a000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig
index 9d1715f..4e392a8 100644
--- a/configs/ls2080aqds_sdcard_defconfig
+++ b/configs/ls2080aqds_sdcard_defconfig
@@ -10,6 +10,7 @@
CONFIG_NR_DRAM_BANKS=3
CONFIG_SPL=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0x1800a000
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
@@ -19,7 +20,6 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SPL_TEXT_BASE=0x1800a000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig
index 56b78fe..9201ccb 100644
--- a/configs/ls2080ardb_nand_defconfig
+++ b/configs/ls2080ardb_nand_defconfig
@@ -8,6 +8,7 @@
CONFIG_NR_DRAM_BANKS=3
CONFIG_SPL=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0x1800a000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -18,7 +19,6 @@
CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_MISC_INIT_R=y
-CONFIG_SPL_TEXT_BASE=0x1800a000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig
index e798c59..f0ebe7b 100644
--- a/configs/ls2088aqds_tfa_defconfig
+++ b/configs/ls2088aqds_tfa_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_TARGET_LS2080AQDS=y
-CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_TFABOOT=y
+CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_NR_DRAM_BANKS=3
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
@@ -26,7 +26,6 @@
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
CONFIG_MP=y
# CONFIG_ISO_PARTITION is not set
CONFIG_OF_CONTROL=y
@@ -38,6 +37,12 @@
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_I2C_DEFAULT_BUS_NUMBER=0
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
@@ -53,6 +58,7 @@
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
index d3312c6..0f84055 100644
--- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
@@ -1,14 +1,14 @@
CONFIG_ARM=y
CONFIG_TARGET_LS2080ARDB=y
+CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_SECURE_BOOT=y
CONFIG_QSPI_AHB_INIT=y
-CONFIG_TFABOOT=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
@@ -29,13 +29,18 @@
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
CONFIG_MP=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_I2C_DEFAULT_BUS_NUMBER=0
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
@@ -54,6 +59,7 @@
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig
index 1aa8dd9..014acc5 100644
--- a/configs/ls2088ardb_tfa_defconfig
+++ b/configs/ls2088ardb_tfa_defconfig
@@ -1,13 +1,13 @@
CONFIG_ARM=y
CONFIG_TARGET_LS2080ARDB=y
-CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_QSPI_AHB_INIT=y
CONFIG_TFABOOT=y
+CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_F_LEN=0x6000
+CONFIG_QSPI_AHB_INIT=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
@@ -28,7 +28,6 @@
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
CONFIG_MP=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi"
@@ -39,6 +38,12 @@
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_I2C_DEFAULT_BUS_NUMBER=0
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
@@ -58,6 +63,7 @@
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
diff --git a/configs/lschlv2_defconfig b/configs/lschlv2_defconfig
index f02776d..0349848 100644
--- a/configs/lschlv2_defconfig
+++ b/configs/lschlv2_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_LSXL=y
@@ -8,10 +9,12 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="LSCHLV2"
CONFIG_API=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/sda2"
CONFIG_BOOTCOMMAND="run bootcmd_${bootsource}"
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_MISC_INIT_R=y
diff --git a/configs/lsxhl_defconfig b/configs/lsxhl_defconfig
index daeecb5..a066281 100644
--- a/configs/lsxhl_defconfig
+++ b/configs/lsxhl_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_LSXL=y
@@ -8,10 +9,12 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="LSXHL"
CONFIG_API=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/sda2"
CONFIG_BOOTCOMMAND="run bootcmd_${bootsource}"
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_MISC_INIT_R=y
diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
index a6a253f..3d4506b 100644
--- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
@@ -1,9 +1,9 @@
CONFIG_ARM=y
CONFIG_TARGET_LX2160AQDS=y
+CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_SECURE_BOOT=y
-CONFIG_TFABOOT=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
@@ -29,6 +29,12 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_I2C_DEFAULT_BUS_NUMBER=0
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
@@ -48,6 +54,8 @@
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_GEN4=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_PCF2127=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig
index d68b40d..ef774af 100644
--- a/configs/lx2160aqds_tfa_defconfig
+++ b/configs/lx2160aqds_tfa_defconfig
@@ -1,8 +1,8 @@
CONFIG_ARM=y
CONFIG_TARGET_LX2160AQDS=y
+CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SYS_MALLOC_F_LEN=0x6000
-CONFIG_TFABOOT=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
@@ -25,12 +25,19 @@
CONFIG_CMD_CACHE=y
CONFIG_MP=y
CONFIG_OF_CONTROL=y
+CONFIG_OF_BOARD_FIXUP=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-qds"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_I2C_DEFAULT_BUS_NUMBER=0
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
@@ -48,6 +55,8 @@
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_GEN4=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_PCF2127=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
index 5cb29fd..ede4e0f 100644
--- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
@@ -1,10 +1,10 @@
CONFIG_ARM=y
CONFIG_TARGET_LX2160ARDB=y
+CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_SECURE_BOOT=y
CONFIG_EMC2305=y
-CONFIG_TFABOOT=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
@@ -30,6 +30,10 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
@@ -46,6 +50,8 @@
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_GEN4=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_PCF2127=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig
index 94f58a8..1ad4ad7 100644
--- a/configs/lx2160ardb_tfa_defconfig
+++ b/configs/lx2160ardb_tfa_defconfig
@@ -1,9 +1,9 @@
CONFIG_ARM=y
CONFIG_TARGET_LX2160ARDB=y
+CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_EMC2305=y
-CONFIG_TFABOOT=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
@@ -26,13 +26,19 @@
CONFIG_CMD_CACHE=y
CONFIG_MP=y
CONFIG_OF_CONTROL=y
+CONFIG_OF_BOARD_FIXUP=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-rdb"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_DM_MMC=y
+CONFIG_MMC_HS200_SUPPORT=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
@@ -48,6 +54,8 @@
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_GEN4=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_PCF2127=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig
index 5a1fbf5..5004795 100644
--- a/configs/m53menlo_defconfig
+++ b/configs/m53menlo_defconfig
@@ -12,15 +12,17 @@
CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
CONFIG_SYS_BOOTCOUNT_ADDR=0x53FA401C
# CONFIG_CMD_BMODE is not set
+CONFIG_SPL_TEXT_BASE=0x70008000
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/menlo/m53menlo/imximage.cfg"
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttymxc0,115200"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="run try_bootscript"
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_LATE_INIT=y
-CONFIG_SPL_TEXT_BASE=0x70008000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
@@ -60,8 +62,9 @@
CONFIG_SYS_BOOTCOUNT_MAGIC=0x0B01C041
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_NAND=y
+CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_MXC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
@@ -72,6 +75,8 @@
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_RTC_M41T62=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_MX5=y
diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig
index 8607760..27f1e09 100644
--- a/configs/marsboard_defconfig
+++ b/configs/marsboard_defconfig
@@ -21,7 +21,7 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
diff --git a/configs/maxbcm_defconfig b/configs/maxbcm_defconfig
index 0d4b626..6b5363d 100644
--- a/configs/maxbcm_defconfig
+++ b/configs/maxbcm_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -13,13 +14,15 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0x40004030
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0x40004030
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_SF=y
diff --git a/configs/mccmon6_nor_defconfig b/configs/mccmon6_nor_defconfig
index af2a106..a738ddb 100644
--- a/configs/mccmon6_nor_defconfig
+++ b/configs/mccmon6_nor_defconfig
@@ -8,11 +8,11 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_nor.cfg"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_BOUNCE_BUFFER=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_NOR_SUPPORT=y
@@ -20,7 +20,6 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
@@ -29,7 +28,7 @@
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_MTD_DEVICE=y
@@ -50,5 +49,4 @@
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_DM_THERMAL=y
-CONFIG_USB=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/mccmon6_sd_defconfig b/configs/mccmon6_sd_defconfig
index aac433c..377c52a 100644
--- a/configs/mccmon6_sd_defconfig
+++ b/configs/mccmon6_sd_defconfig
@@ -9,11 +9,11 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
# CONFIG_CMD_BMODE is not set
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_sd.cfg"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_BOUNCE_BUFFER=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_NOR_SUPPORT=y
@@ -21,7 +21,6 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
@@ -30,7 +29,7 @@
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_MTD_DEVICE=y
@@ -51,5 +50,4 @@
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_DM_THERMAL=y
-CONFIG_USB=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/medcom-wide_defconfig b/configs/medcom-wide_defconfig
index ee9044e..c927418 100644
--- a/configs/medcom-wide_defconfig
+++ b/configs/medcom-wide_defconfig
@@ -4,10 +4,10 @@
CONFIG_NR_DRAM_BANKS=2
CONFIG_TEGRA20=y
CONFIG_TARGET_MEDCOM_WIDE=y
+CONFIG_SPL_TEXT_BASE=0x00108000
CONFIG_FIT=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_SYS_STDIO_DEREGISTER=y
-CONFIG_SPL_TEXT_BASE=0x00108000
CONFIG_SYS_PROMPT="Tegra20 (Medcom-Wide) # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/meesc_dataflash_defconfig b/configs/meesc_dataflash_defconfig
index 476700c..5d0f247 100644
--- a/configs/meesc_dataflash_defconfig
+++ b/configs/meesc_dataflash_defconfig
@@ -1,12 +1,17 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21F00000
CONFIG_TARGET_MEESC=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4200
+CONFIG_ENV_OFFSET=0x4200
CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SECT_SIZE=0x210
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_MISC_INIT_R=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/meesc_defconfig b/configs/meesc_defconfig
index 0e49d82..5312974 100644
--- a/configs/meesc_defconfig
+++ b/configs/meesc_defconfig
@@ -1,12 +1,15 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21F00000
CONFIG_TARGET_MEESC=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_OFFSET=0xC0000
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_MISC_INIT_R=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
@@ -28,6 +31,7 @@
CONFIG_AT91_GPIO=y
# CONFIG_MMC is not set
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/mgcoge3un_defconfig b/configs/mgcoge3un_defconfig
index 6b36cf9..15a6dd5 100644
--- a/configs/mgcoge3un_defconfig
+++ b/configs/mgcoge3un_defconfig
@@ -1,8 +1,11 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
+CONFIG_PIGGY_MAC_ADRESS_OFFSET=3
+CONFIG_KM_PIGGY4_88E6061=y
CONFIG_IDENT_STRING="\nKeymile COGE3UN"
CONFIG_SYS_EXTRA_OPTIONS="KM_MGCOGE3UN"
CONFIG_MISC_INIT_R=y
diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig
index e875626..94b9c78 100644
--- a/configs/microblaze-generic_defconfig
+++ b/configs/microblaze-generic_defconfig
@@ -15,6 +15,8 @@
CONFIG_BOOTDELAY=-1
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=romfs"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="echo U-BOOT for ${hostname};setenv preboot;echo"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_SPL_BOARD_INIT=y
diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig
index 446c2f2..0b317bc 100644
--- a/configs/minnowmax_defconfig
+++ b/configs/minnowmax_defconfig
@@ -19,6 +19,7 @@
CONFIG_FIT_SIGNATURE=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig
index 936192f..7b4e3f7 100644
--- a/configs/miqi-rk3288_defconfig
+++ b/configs/miqi-rk3288_defconfig
@@ -1,7 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00000000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3288=y
CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
CONFIG_TARGET_MIQI_RK3288=y
@@ -10,12 +9,13 @@
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0xff704000
# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_DEFAULT_FDT_FILE="rk3288-miqi.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0xff704000
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_CMD_GPIO=y
@@ -25,6 +25,7 @@
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
@@ -76,7 +77,6 @@
CONFIG_USB_GADGET_VENDOR_NUM=0x2207
CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USB_FUNCTION_MASS_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_SMSC95XX=y
@@ -85,6 +85,5 @@
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
CONFIG_CONSOLE_SCROLL_LINES=10
-CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
diff --git a/configs/mixtile_loftq_defconfig b/configs/mixtile_loftq_defconfig
index 8d286a2..04d2426 100644
--- a/configs/mixtile_loftq_defconfig
+++ b/configs/mixtile_loftq_defconfig
@@ -9,7 +9,7 @@
CONFIG_USB1_VBUS_PIN="PH24"
CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/mk802_a10s_defconfig b/configs/mk802_a10s_defconfig
index c9dfa04..3968790 100644
--- a/configs/mk802_a10s_defconfig
+++ b/configs/mk802_a10s_defconfig
@@ -7,7 +7,7 @@
CONFIG_DRAM_EMR1=0
CONFIG_USB1_VBUS_PIN="PB10"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/mk802_defconfig b/configs/mk802_defconfig
index 6ecabce..416cb9a 100644
--- a/configs/mk802_defconfig
+++ b/configs/mk802_defconfig
@@ -5,7 +5,7 @@
CONFIG_MACH_SUN4I=y
CONFIG_USB2_VBUS_PIN="PH12"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/mk802ii_defconfig b/configs/mk802ii_defconfig
index 4474d03..221c2bc 100644
--- a/configs/mk802ii_defconfig
+++ b/configs/mk802ii_defconfig
@@ -4,7 +4,7 @@
CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/mt7623n_bpir2_defconfig b/configs/mt7623n_bpir2_defconfig
index ae82098..f79850f 100644
--- a/configs/mt7623n_bpir2_defconfig
+++ b/configs/mt7623n_bpir2_defconfig
@@ -31,7 +31,6 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
-# CONFIG_BLOCK_CACHE is not set
CONFIG_CLK=y
CONFIG_DM_MMC=y
# CONFIG_MMC_QUIRKS is not set
diff --git a/configs/mt7629_rfb_defconfig b/configs/mt7629_rfb_defconfig
index 0dceafd..de438a8 100644
--- a/configs/mt7629_rfb_defconfig
+++ b/configs/mt7629_rfb_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_ARCH_TIMER=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_MEDIATEK=y
CONFIG_SYS_TEXT_BASE=0x41e00000
@@ -7,13 +8,13 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL_TEXT_BASE=0x201000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_DEFAULT_FDT_FILE="mt7629-rfb"
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_TEXT_BASE=0x201000
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
@@ -63,13 +64,10 @@
CONFIG_MTK_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
-CONFIG_MTK_QSPI=y
+CONFIG_MTK_SNFI_SPI=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_WATCHDOG=y
-CONFIG_TIMER=y
-CONFIG_SPL_TIMER=y
-CONFIG_MTK_TIMER=y
CONFIG_WDT_MTK=y
CONFIG_LZMA=y
# CONFIG_EFI_LOADER is not set
diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig
index 209349b..f6bc97f 100644
--- a/configs/mvebu_db-88f3720_defconfig
+++ b/configs/mvebu_db-88f3720_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
@@ -10,6 +11,7 @@
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
@@ -59,7 +61,6 @@
CONFIG_MVEBU_COMPHY_SUPPORT=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ARMADA_37XX=y
-# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DEBUG_MVEBU_A3700_UART=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_ANNOUNCE=y
diff --git a/configs/mvebu_db_armada8k_defconfig b/configs/mvebu_db_armada8k_defconfig
index 7697d75..97077e1 100644
--- a/configs/mvebu_db_armada8k_defconfig
+++ b/configs/mvebu_db_armada8k_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
@@ -11,6 +12,7 @@
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
@@ -55,7 +57,6 @@
CONFIG_MVEBU_COMPHY_SUPPORT=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ARMADA_8K=y
-# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_SYS_NS16550=y
diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig
index cdfa091..9375daf 100644
--- a/configs/mvebu_espressobin-88f3720_defconfig
+++ b/configs/mvebu_espressobin-88f3720_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
@@ -10,6 +11,7 @@
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
@@ -59,7 +61,6 @@
CONFIG_MVEBU_COMPHY_SUPPORT=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ARMADA_37XX=y
-# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DEBUG_MVEBU_A3700_UART=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_ANNOUNCE=y
diff --git a/configs/mvebu_mcbin-88f8040_defconfig b/configs/mvebu_mcbin-88f8040_defconfig
index 39a49d5..7ce24b0 100644
--- a/configs/mvebu_mcbin-88f8040_defconfig
+++ b/configs/mvebu_mcbin-88f8040_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
@@ -10,6 +11,7 @@
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
@@ -60,7 +62,6 @@
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ARMADA_8K=y
CONFIG_DM_REGULATOR_FIXED=y
-# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_SYS_NS16550=y
diff --git a/configs/mx23_olinuxino_defconfig b/configs/mx23_olinuxino_defconfig
index 3e4b7ab..e70c8fc 100644
--- a/configs/mx23_olinuxino_defconfig
+++ b/configs/mx23_olinuxino_defconfig
@@ -8,12 +8,12 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x00001000
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_TEXT_BASE=0x00001000
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BOOTEFI is not set
# CONFIG_CMD_FLASH is not set
@@ -26,6 +26,7 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_MXS_GPIO=y
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS_GPIO=y
CONFIG_LED_STATUS0=y
diff --git a/configs/mx23evk_defconfig b/configs/mx23evk_defconfig
index 773aff4..02043ba 100644
--- a/configs/mx23evk_defconfig
+++ b/configs/mx23evk_defconfig
@@ -8,13 +8,13 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x00001000
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_TEXT_BASE=0x00001000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
@@ -28,6 +28,7 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
# CONFIG_NET is not set
+CONFIG_MXS_GPIO=y
CONFIG_MMC_MXS=y
CONFIG_CONS_INDEX=0
CONFIG_USB=y
diff --git a/configs/mx25pdk_defconfig b/configs/mx25pdk_defconfig
index c024d79..a6ee105 100644
--- a/configs/mx25pdk_defconfig
+++ b/configs/mx25pdk_defconfig
@@ -19,7 +19,7 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_DOS_PARTITION=y
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_MII=y
CONFIG_FS_EXT4=y
CONFIG_FS_FAT=y
diff --git a/configs/mx28evk_auart_console_defconfig b/configs/mx28evk_auart_console_defconfig
index 27c1525..ce3e77a 100644
--- a/configs/mx28evk_auart_console_defconfig
+++ b/configs/mx28evk_auart_console_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x00001000
CONFIG_SYS_EXTRA_OPTIONS="MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
@@ -15,7 +16,6 @@
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_TEXT_BASE=0x00001000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
@@ -38,6 +38,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:3m(bootloader)ro,512k(environment),512k(redundant-environment),4m(kernel),512k(fdt),8m(ramdisk),-(filesystem)"
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_MXS_GPIO=y
CONFIG_MMC_MXS=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig
index 4cee901..361375c 100644
--- a/configs/mx28evk_defconfig
+++ b/configs/mx28evk_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x00001000
CONFIG_FIT=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
@@ -15,7 +16,6 @@
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_TEXT_BASE=0x00001000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
@@ -38,6 +38,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:3m(bootloader)ro,512k(environment),512k(redundant-environment),4m(kernel),512k(fdt),8m(ramdisk),-(filesystem)"
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_MXS_GPIO=y
CONFIG_MMC_MXS=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
diff --git a/configs/mx28evk_nand_defconfig b/configs/mx28evk_nand_defconfig
index 3875da7..d34d50a 100644
--- a/configs/mx28evk_nand_defconfig
+++ b/configs/mx28evk_nand_defconfig
@@ -8,13 +8,13 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x00001000
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_TEXT_BASE=0x00001000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
@@ -37,6 +37,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:3m(bootloader)ro,512k(environment),512k(redundant-environment),4m(kernel),512k(fdt),8m(ramdisk),-(filesystem)"
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_MXS_GPIO=y
CONFIG_MMC_MXS=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
diff --git a/configs/mx28evk_spi_defconfig b/configs/mx28evk_spi_defconfig
index 37477b3..6e06571 100644
--- a/configs/mx28evk_spi_defconfig
+++ b/configs/mx28evk_spi_defconfig
@@ -8,13 +8,13 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x00001000
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_TEXT_BASE=0x00001000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
@@ -36,6 +36,7 @@
CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:3m(bootloader)ro,512k(environment),512k(redundant-environment),4m(kernel),512k(fdt),8m(ramdisk),-(filesystem)"
CONFIG_CMD_UBI=y
+CONFIG_MXS_GPIO=y
CONFIG_MMC_MXS=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
diff --git a/configs/mx31pdk_defconfig b/configs/mx31pdk_defconfig
index 7eb07e6..bdeb6b2 100644
--- a/configs/mx31pdk_defconfig
+++ b/configs/mx31pdk_defconfig
@@ -8,8 +8,8 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
-# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_TEXT_BASE=0x87dc0000
+# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_SUPPORT=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_BOOTZ=y
diff --git a/configs/mx35pdk_defconfig b/configs/mx35pdk_defconfig
index 7fec4b6..3d36045 100644
--- a/configs/mx35pdk_defconfig
+++ b/configs/mx35pdk_defconfig
@@ -26,7 +26,7 @@
# CONFIG_PARTITION_UUIDS is not set
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_MXC_GPIO=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
diff --git a/configs/mx51evk_defconfig b/configs/mx51evk_defconfig
index ffb821e..d30687a 100644
--- a/configs/mx51evk_defconfig
+++ b/configs/mx51evk_defconfig
@@ -5,6 +5,7 @@
CONFIG_NR_DRAM_BANKS=1
# CONFIG_CMD_BMODE is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx51evk/imximage.cfg"
+CONFIG_USE_PREBOOT=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
@@ -21,7 +22,7 @@
CONFIG_CMD_DATE=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_MII=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
diff --git a/configs/mx53ard_defconfig b/configs/mx53ard_defconfig
index ea1d3f6..429a78f 100644
--- a/configs/mx53ard_defconfig
+++ b/configs/mx53ard_defconfig
@@ -15,8 +15,9 @@
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_NAND=y
+CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_MXC=y
CONFIG_MII=y
CONFIG_SMC911X=y
diff --git a/configs/mx53cx9020_defconfig b/configs/mx53cx9020_defconfig
index bf48966..4ed3825 100644
--- a/configs/mx53cx9020_defconfig
+++ b/configs/mx53cx9020_defconfig
@@ -6,6 +6,7 @@
# CONFIG_CMD_BMODE is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/beckhoff/mx53cx9020/imximage.cfg"
CONFIG_BOOTDELAY=1
+CONFIG_USE_PREBOOT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@@ -26,7 +27,7 @@
CONFIG_FPGA_CYCLON2=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
diff --git a/configs/mx53evk_defconfig b/configs/mx53evk_defconfig
index 67582b5..ab9e485 100644
--- a/configs/mx53evk_defconfig
+++ b/configs/mx53evk_defconfig
@@ -14,6 +14,6 @@
CONFIG_CMD_DATE=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_MII=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/mx53loco_defconfig b/configs/mx53loco_defconfig
index a7adeff..b4c3b0e 100644
--- a/configs/mx53loco_defconfig
+++ b/configs/mx53loco_defconfig
@@ -5,6 +5,7 @@
CONFIG_NR_DRAM_BANKS=2
# CONFIG_CMD_BMODE is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53loco/imximage.cfg"
+CONFIG_USE_PREBOOT=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
@@ -23,7 +24,7 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DWC_AHSATA=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_MII=y
CONFIG_USB=y
CONFIG_USB_EHCI_MX5=y
diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig
index 19ebab7..cad798a 100644
--- a/configs/mx53ppd_defconfig
+++ b/configs/mx53ppd_defconfig
@@ -39,10 +39,11 @@
CONFIG_BOOTCOUNT_BOOTLIMIT=10
CONFIG_SYS_BOOTCOUNT_EXT_DEVPART="0:5"
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX5=y
+CONFIG_PWM_IMX=y
CONFIG_RTC_S35392A=y
CONFIG_USB=y
CONFIG_USB_EHCI_MX5=y
diff --git a/configs/mx53smd_defconfig b/configs/mx53smd_defconfig
index 8c3e40f..2454956 100644
--- a/configs/mx53smd_defconfig
+++ b/configs/mx53smd_defconfig
@@ -14,6 +14,6 @@
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_MII=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig
index f13e688..a13243f 100644
--- a/configs/mx6cuboxi_defconfig
+++ b/configs/mx6cuboxi_defconfig
@@ -12,12 +12,14 @@
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_CMD_BMODE is not set
CONFIG_CMD_HDMIDETECT=y
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="if hdmidet; then usb start; setenv stdin serial,usbkbd; setenv stdout serial,vga; setenv stderr serial,vga; else setenv stdin serial; setenv stdout serial; setenv stderr serial; fi;"
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
@@ -33,7 +35,7 @@
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
CONFIG_DWC_AHSATA=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_DM_THERMAL=y
diff --git a/configs/mx6dlarm2_defconfig b/configs/mx6dlarm2_defconfig
index 35f8183..4675c9d 100644
--- a/configs/mx6dlarm2_defconfig
+++ b/configs/mx6dlarm2_defconfig
@@ -26,7 +26,7 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_MII=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/mx6dlarm2_lpddr2_defconfig b/configs/mx6dlarm2_lpddr2_defconfig
index 0e68df0..cdca47e 100644
--- a/configs/mx6dlarm2_lpddr2_defconfig
+++ b/configs/mx6dlarm2_lpddr2_defconfig
@@ -26,7 +26,7 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_MII=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/mx6memcal_defconfig b/configs/mx6memcal_defconfig
index ebb48c3..7ffd3b4 100644
--- a/configs/mx6memcal_defconfig
+++ b/configs/mx6memcal_defconfig
@@ -8,10 +8,10 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SPL,MX6QDL"
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOUNCE_BUFFER=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_USB_HOST_SUPPORT=y
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_USB_ETHER=y
@@ -36,6 +36,7 @@
CONFIG_CMD_CACHE=y
# CONFIG_NET is not set
# CONFIG_MMC is not set
+CONFIG_FSL_USDHC=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
diff --git a/configs/mx6qarm2_defconfig b/configs/mx6qarm2_defconfig
index 304d1dc..5f2b40f 100644
--- a/configs/mx6qarm2_defconfig
+++ b/configs/mx6qarm2_defconfig
@@ -26,7 +26,7 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_MII=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/mx6qarm2_lpddr2_defconfig b/configs/mx6qarm2_lpddr2_defconfig
index bbdc771..3ca42d7 100644
--- a/configs/mx6qarm2_lpddr2_defconfig
+++ b/configs/mx6qarm2_lpddr2_defconfig
@@ -26,7 +26,7 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_MII=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig
index 03bddda..379407a 100644
--- a/configs/mx6qsabrelite_defconfig
+++ b/configs/mx6qsabrelite_defconfig
@@ -8,6 +8,7 @@
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE"
CONFIG_BOOTDELAY=3
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_MISC_INIT_R=y
CONFIG_BOUNCE_BUFFER=y
@@ -34,7 +35,7 @@
CONFIG_DWC_AHSATA=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=25000000
diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig
index 558b1cd..c2c4ca2 100644
--- a/configs/mx6sabreauto_defconfig
+++ b/configs/mx6sabreauto_defconfig
@@ -12,6 +12,7 @@
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_NXP_BOARD_REVISION=y
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_FIT=y
CONFIG_SPL_FIT_PRINT=y
CONFIG_SPL_LOAD_FIT=y
@@ -21,7 +22,6 @@
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOUNCE_BUFFER=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_FIT_IMAGE_TINY=y
CONFIG_SPL_FS_EXT4=y
@@ -44,6 +44,7 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
@@ -62,7 +63,7 @@
CONFIG_DFU_SF=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_DM_SPI_FLASH=y
@@ -90,4 +91,5 @@
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_VIDEO_IPUV3=y
diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig
index 0739c58..73cb32e 100644
--- a/configs/mx6sabresd_defconfig
+++ b/configs/mx6sabresd_defconfig
@@ -11,6 +11,7 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_FIT=y
CONFIG_SPL_FIT_PRINT=y
CONFIG_SPL_LOAD_FIT=y
@@ -20,7 +21,6 @@
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOUNCE_BUFFER=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_FIT_IMAGE_TINY=y
CONFIG_SPL_FS_EXT4=y
@@ -47,6 +47,7 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
@@ -74,7 +75,7 @@
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
@@ -99,4 +100,5 @@
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_VIDEO_IPUV3=y
diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig
index 50cc225..e614ef2 100644
--- a/configs/mx6slevk_defconfig
+++ b/configs/mx6slevk_defconfig
@@ -34,7 +34,7 @@
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
diff --git a/configs/mx6slevk_spinor_defconfig b/configs/mx6slevk_spinor_defconfig
index d2be52f..6ade0ef 100644
--- a/configs/mx6slevk_spinor_defconfig
+++ b/configs/mx6slevk_spinor_defconfig
@@ -34,7 +34,7 @@
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig
index 4841dc6..22bd5c3 100644
--- a/configs/mx6slevk_spl_defconfig
+++ b/configs/mx6slevk_spl_defconfig
@@ -11,11 +11,11 @@
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_CMD_BMODE is not set
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
@@ -43,7 +43,7 @@
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
diff --git a/configs/mx6sllevk_defconfig b/configs/mx6sllevk_defconfig
index 4dcac21..7efe321 100644
--- a/configs/mx6sllevk_defconfig
+++ b/configs/mx6sllevk_defconfig
@@ -30,7 +30,7 @@
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
diff --git a/configs/mx6sllevk_plugin_defconfig b/configs/mx6sllevk_plugin_defconfig
index 090ab06..4e6f1ed 100644
--- a/configs/mx6sllevk_plugin_defconfig
+++ b/configs/mx6sllevk_plugin_defconfig
@@ -31,7 +31,7 @@
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig
index f7ae29e..fa9853d 100644
--- a/configs/mx6sxsabreauto_defconfig
+++ b/configs/mx6sxsabreauto_defconfig
@@ -34,7 +34,7 @@
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig
index 4e516c5..c5fabf9 100644
--- a/configs/mx6sxsabresd_defconfig
+++ b/configs/mx6sxsabresd_defconfig
@@ -38,7 +38,7 @@
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=1
diff --git a/configs/mx6sxsabresd_spl_defconfig b/configs/mx6sxsabresd_spl_defconfig
index 159f079..bd5a7d6 100644
--- a/configs/mx6sxsabresd_spl_defconfig
+++ b/configs/mx6sxsabresd_spl_defconfig
@@ -12,12 +12,12 @@
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_CMD_BMODE is not set
CONFIG_NXP_BOARD_REVISION=y
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOUNCE_BUFFER=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
@@ -47,7 +47,7 @@
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_PCI=y
diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig
index 2fc7119..dacc294 100644
--- a/configs/mx6ul_14x14_evk_defconfig
+++ b/configs/mx6ul_14x14_evk_defconfig
@@ -10,13 +10,13 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
@@ -44,7 +44,7 @@
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig
index 8816f6a..b9fb2ec 100644
--- a/configs/mx6ul_9x9_evk_defconfig
+++ b/configs/mx6ul_9x9_evk_defconfig
@@ -10,13 +10,13 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
@@ -44,7 +44,7 @@
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig
index 7902465..2528ba8 100644
--- a/configs/mx6ull_14x14_evk_defconfig
+++ b/configs/mx6ull_14x14_evk_defconfig
@@ -30,7 +30,7 @@
CONFIG_DM_74X164=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig b/configs/mx6ull_14x14_evk_plugin_defconfig
index c52de80..f71a495 100644
--- a/configs/mx6ull_14x14_evk_plugin_defconfig
+++ b/configs/mx6ull_14x14_evk_plugin_defconfig
@@ -31,7 +31,7 @@
CONFIG_DM_74X164=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig
index b2ca4f9..b412358 100644
--- a/configs/mx7dsabresd_defconfig
+++ b/configs/mx7dsabresd_defconfig
@@ -14,6 +14,9 @@
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BOOTD is not set
CONFIG_CMD_BOOTZ=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EXPORTENV is not set
@@ -48,7 +51,7 @@
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_PHYLIB=y
diff --git a/configs/mx7dsabresd_qspi_defconfig b/configs/mx7dsabresd_qspi_defconfig
index 27a8387..7223290 100644
--- a/configs/mx7dsabresd_qspi_defconfig
+++ b/configs/mx7dsabresd_qspi_defconfig
@@ -13,6 +13,9 @@
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BOOTD is not set
CONFIG_CMD_BOOTZ=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EXPORTENV is not set
@@ -48,7 +51,7 @@
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
diff --git a/configs/mx7ulp_evk_defconfig b/configs/mx7ulp_evk_defconfig
index d125ccc..df85443 100644
--- a/configs/mx7ulp_evk_defconfig
+++ b/configs/mx7ulp_evk_defconfig
@@ -22,7 +22,7 @@
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7ULP=y
CONFIG_DM_REGULATOR=y
diff --git a/configs/mx7ulp_evk_plugin_defconfig b/configs/mx7ulp_evk_plugin_defconfig
index fcead94..b2451ad 100644
--- a/configs/mx7ulp_evk_plugin_defconfig
+++ b/configs/mx7ulp_evk_plugin_defconfig
@@ -21,7 +21,7 @@
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7ULP=y
CONFIG_DM_REGULATOR=y
diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig
index 7863e45..1d4c8f8 100644
--- a/configs/nanopc-t4-rk3399_defconfig
+++ b/configs/nanopc-t4-rk3399_defconfig
@@ -1,9 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
CONFIG_NR_DRAM_BANKS=1
@@ -14,6 +11,7 @@
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopc-t4.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_TPL=y
@@ -55,6 +53,5 @@
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig
index 8b9237c..7375b75 100644
--- a/configs/nanopi-m4-rk3399_defconfig
+++ b/configs/nanopi-m4-rk3399_defconfig
@@ -1,9 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
CONFIG_NR_DRAM_BANKS=1
@@ -14,6 +11,7 @@
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_TPL=y
@@ -55,6 +53,5 @@
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig
index 5799ab3..874ee5e 100644
--- a/configs/nanopi-neo4-rk3399_defconfig
+++ b/configs/nanopi-neo4-rk3399_defconfig
@@ -1,9 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
CONFIG_NR_DRAM_BANKS=1
@@ -14,6 +11,7 @@
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-neo4.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_TPL=y
@@ -55,6 +53,5 @@
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
diff --git a/configs/nanopi_a64_defconfig b/configs/nanopi_a64_defconfig
index 0845a5c..95a9c96 100644
--- a/configs/nanopi_a64_defconfig
+++ b/configs/nanopi_a64_defconfig
@@ -5,7 +5,7 @@
CONFIG_MACH_SUN50I=y
CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x10060
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/nanopi_m1_defconfig b/configs/nanopi_m1_defconfig
index 1dc2538..7568fb1 100644
--- a/configs/nanopi_m1_defconfig
+++ b/configs/nanopi_m1_defconfig
@@ -5,7 +5,7 @@
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=408
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/nanopi_m1_plus_defconfig b/configs/nanopi_m1_plus_defconfig
index 90edbd9..a359de8 100644
--- a/configs/nanopi_m1_plus_defconfig
+++ b/configs/nanopi_m1_plus_defconfig
@@ -8,7 +8,7 @@
CONFIG_MMC0_CD_PIN="PH13"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/nanopi_neo2_defconfig b/configs/nanopi_neo2_defconfig
index 953fe23..cfda325 100644
--- a/configs/nanopi_neo2_defconfig
+++ b/configs/nanopi_neo2_defconfig
@@ -7,7 +7,7 @@
CONFIG_DRAM_ZQ=3881977
# CONFIG_DRAM_ODT_EN is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x10060
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/nanopi_neo_air_defconfig b/configs/nanopi_neo_air_defconfig
index 5ad90dd..246658b 100644
--- a/configs/nanopi_neo_air_defconfig
+++ b/configs/nanopi_neo_air_defconfig
@@ -6,8 +6,8 @@
CONFIG_DRAM_CLK=408
# CONFIG_VIDEO_DE2 is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
-CONFIG_SPL_TEXT_BASE=0x60
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/nanopi_neo_defconfig b/configs/nanopi_neo_defconfig
index e7d6ce4..fba6ff5 100644
--- a/configs/nanopi_neo_defconfig
+++ b/configs/nanopi_neo_defconfig
@@ -6,8 +6,8 @@
CONFIG_DRAM_CLK=408
# CONFIG_VIDEO_DE2 is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
-CONFIG_SPL_TEXT_BASE=0x60
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/nanopi_neo_plus2_defconfig b/configs/nanopi_neo_plus2_defconfig
index 4096a61..5f78a8b 100644
--- a/configs/nanopi_neo_plus2_defconfig
+++ b/configs/nanopi_neo_plus2_defconfig
@@ -9,7 +9,7 @@
CONFIG_MACPWR="PD6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x10060
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/nas220_defconfig b/configs/nas220_defconfig
index 80b122d..9b5d594 100644
--- a/configs/nas220_defconfig
+++ b/configs/nas220_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NAS220=y
@@ -7,6 +8,7 @@
CONFIG_IDENT_STRING="\nNAS 220"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="nas220> "
diff --git a/configs/net2big_v2_defconfig b/configs/net2big_v2_defconfig
index 9ae774a..2a309f5 100644
--- a/configs/net2big_v2_defconfig
+++ b/configs/net2big_v2_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NET2BIG_V2=y
@@ -9,6 +10,7 @@
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/netgear_cg3100d_ram_defconfig b/configs/netgear_cg3100d_ram_defconfig
index 8f50750..754a03e 100644
--- a/configs/netgear_cg3100d_ram_defconfig
+++ b/configs/netgear_cg3100d_ram_defconfig
@@ -42,7 +42,6 @@
CONFIG_SPI_FLASH_MTD=y
CONFIG_DM_RESET=y
CONFIG_RESET_BCM6345=y
-# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DM_SERIAL=y
CONFIG_BCM6345_SERIAL=y
CONFIG_SPI=y
diff --git a/configs/netgear_dgnd3700v2_ram_defconfig b/configs/netgear_dgnd3700v2_ram_defconfig
index 72572f1..f7961ec 100644
--- a/configs/netgear_dgnd3700v2_ram_defconfig
+++ b/configs/netgear_dgnd3700v2_ram_defconfig
@@ -49,7 +49,6 @@
CONFIG_BCM6328_POWER_DOMAIN=y
CONFIG_DM_RESET=y
CONFIG_RESET_BCM6345=y
-# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DM_SERIAL=y
CONFIG_BCM6345_SERIAL=y
CONFIG_USB=y
diff --git a/configs/netspace_lite_v2_defconfig b/configs/netspace_lite_v2_defconfig
index 6611046..ee58114 100644
--- a/configs/netspace_lite_v2_defconfig
+++ b/configs/netspace_lite_v2_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NETSPACE_V2=y
@@ -9,6 +10,7 @@
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/netspace_max_v2_defconfig b/configs/netspace_max_v2_defconfig
index 41eeab8..2a95a55 100644
--- a/configs/netspace_max_v2_defconfig
+++ b/configs/netspace_max_v2_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NETSPACE_V2=y
@@ -9,6 +10,7 @@
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/netspace_mini_v2_defconfig b/configs/netspace_mini_v2_defconfig
index fd56ae0..6933a9b 100644
--- a/configs/netspace_mini_v2_defconfig
+++ b/configs/netspace_mini_v2_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NETSPACE_V2=y
@@ -9,6 +10,7 @@
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/netspace_v2_defconfig b/configs/netspace_v2_defconfig
index ffb60da..fc806e4 100644
--- a/configs/netspace_v2_defconfig
+++ b/configs/netspace_v2_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NETSPACE_V2=y
@@ -9,6 +10,7 @@
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig
index dff3770..11bee9b 100644
--- a/configs/nitrogen6dl2g_defconfig
+++ b/configs/nitrogen6dl2g_defconfig
@@ -6,6 +6,7 @@
CONFIG_CMD_HDMIDETECT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
@@ -36,7 +37,7 @@
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=25000000
diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig
index 95fdb4a..141289f 100644
--- a/configs/nitrogen6dl_defconfig
+++ b/configs/nitrogen6dl_defconfig
@@ -6,6 +6,7 @@
CONFIG_CMD_HDMIDETECT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
@@ -36,7 +37,7 @@
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=25000000
diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig
index 05f0a21..8414183 100644
--- a/configs/nitrogen6q2g_defconfig
+++ b/configs/nitrogen6q2g_defconfig
@@ -6,6 +6,7 @@
CONFIG_CMD_HDMIDETECT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
@@ -38,7 +39,7 @@
CONFIG_DWC_AHSATA=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=25000000
diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig
index 5ac4a33..e0af34c 100644
--- a/configs/nitrogen6q_defconfig
+++ b/configs/nitrogen6q_defconfig
@@ -6,6 +6,7 @@
CONFIG_CMD_HDMIDETECT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
@@ -38,7 +39,7 @@
CONFIG_DWC_AHSATA=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=25000000
diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig
index 69cd12d..53eb96a 100644
--- a/configs/nitrogen6s1g_defconfig
+++ b/configs/nitrogen6s1g_defconfig
@@ -6,6 +6,7 @@
CONFIG_CMD_HDMIDETECT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
@@ -36,7 +37,7 @@
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=25000000
diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig
index 2e3d62f..e60c237 100644
--- a/configs/nitrogen6s_defconfig
+++ b/configs/nitrogen6s_defconfig
@@ -6,6 +6,7 @@
CONFIG_CMD_HDMIDETECT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
@@ -36,7 +37,7 @@
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=25000000
diff --git a/configs/nokia_rx51_defconfig b/configs/nokia_rx51_defconfig
index fe2ecf6..ab5bb2d 100644
--- a/configs/nokia_rx51_defconfig
+++ b/configs/nokia_rx51_defconfig
@@ -5,11 +5,14 @@
CONFIG_TARGET_NOKIA_RX51=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_BOOTDELAY=30
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="setenv mmcnum 1; setenv mmcpart 1;setenv mmcscriptfile bootmenu.scr;if run switchmmc; then setenv mmcdone true;setenv mmctype fat;if run scriptload; then true; else setenv mmctype ext2;if run scriptload; then true; else setenv mmctype ext4;if run scriptload; then true; else setenv mmcdone false;fi;fi;fi;if ${mmcdone}; then run scriptboot;fi;fi;if run slide; then true; else setenv bootmenu_delay 0;setenv bootdelay 0;fi"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Nokia RX-51 # "
CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_MENU_SHOW=y
CONFIG_CMD_BOOTMENU=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_SAVEENV is not set
diff --git a/configs/novena_defconfig b/configs/novena_defconfig
index 2a7807d..f9fc289 100644
--- a/configs/novena_defconfig
+++ b/configs/novena_defconfig
@@ -14,6 +14,7 @@
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
@@ -24,7 +25,6 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
@@ -49,7 +49,7 @@
CONFIG_DWC_AHSATA=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig
index a428d76..064ea05 100644
--- a/configs/nsa310s_defconfig
+++ b/configs/nsa310s_defconfig
@@ -1,10 +1,12 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NSA310S=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="nsa310s => "
diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig
index ac7b505..443e27b 100644
--- a/configs/nyan-big_defconfig
+++ b/configs/nyan-big_defconfig
@@ -8,6 +8,7 @@
CONFIG_TEGRA124=y
CONFIG_TARGET_NYAN_BIG=y
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_OF_SYSTEM_SETUP=y
@@ -17,7 +18,6 @@
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_LOG_DEFAULT_LEVEL=7
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_SYS_PROMPT="Tegra124 (Nyan-big) # "
# CONFIG_CMD_IMI is not set
CONFIG_CMD_DFU=y
diff --git a/configs/oceanic_5205_5inmfd_defconfig b/configs/oceanic_5205_5inmfd_defconfig
index 645e02a..854ada3 100644
--- a/configs/oceanic_5205_5inmfd_defconfig
+++ b/configs/oceanic_5205_5inmfd_defconfig
@@ -10,7 +10,8 @@
CONFIG_MMC0_CD_PIN=""
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x10060
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/odroid-n2_defconfig b/configs/odroid-n2_defconfig
new file mode 100644
index 0000000..abd945a
--- /dev/null
+++ b/configs/odroid-n2_defconfig
@@ -0,0 +1,54 @@
+CONFIG_ARM=y
+CONFIG_SYS_BOARD="w400"
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_MESON_G12A=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEBUG_UART_BASE=0xff803000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" odroid-n2"
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-odroid-n2"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_MESON_G12A_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_G12A=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_MESON_G12A=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig
index b8ebd56..8493312 100644
--- a/configs/odroid-xu3_defconfig
+++ b/configs/odroid-xu3_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x43E00000
CONFIG_ARCH_EXYNOS5=y
diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig
index cdf0147..95d77b7 100644
--- a/configs/odroid_defconfig
+++ b/configs/odroid_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x43e00000
CONFIG_ARCH_EXYNOS4=y
diff --git a/configs/omap35_logic_defconfig b/configs/omap35_logic_defconfig
index 3a529e8..78fcbaa 100644
--- a/configs/omap35_logic_defconfig
+++ b/configs/omap35_logic_defconfig
@@ -9,13 +9,15 @@
# CONFIG_SPL_OMAP3_ID_NAND is not set
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ANDROID_BOOT_IMAGE=y
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="setenv preboot;saveenv;"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DEFAULT_FDT_FILE="logicpd-torpedo-35xx-devkit.dtb"
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
# CONFIG_SPL_FS_EXT4 is not set
@@ -41,7 +43,6 @@
# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
@@ -69,6 +70,7 @@
CONFIG_DM_USB=y
# CONFIG_SPL_DM_USB is not set
CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_OMAP is not set
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_OMAP2PLUS=y
CONFIG_TWL4030_USB=y
diff --git a/configs/omap35_logic_somlv_defconfig b/configs/omap35_logic_somlv_defconfig
index fb7e714..9eaccfb 100644
--- a/configs/omap35_logic_somlv_defconfig
+++ b/configs/omap35_logic_somlv_defconfig
@@ -9,13 +9,15 @@
# CONFIG_SPL_OMAP3_ID_NAND is not set
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ANDROID_BOOT_IMAGE=y
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="setenv preboot;saveenv;"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DEFAULT_FDT_FILE="logicpd-som-lv-35xx-devkit.dtb"
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
# CONFIG_SPL_FS_EXT4 is not set
diff --git a/configs/omap3_beagle_defconfig b/configs/omap3_beagle_defconfig
index b389d1d..bf49de4 100644
--- a/configs/omap3_beagle_defconfig
+++ b/configs/omap3_beagle_defconfig
@@ -7,13 +7,14 @@
CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x400
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="usb start"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DEFAULT_FDT_FILE="omap3-beagle.dtb"
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
# CONFIG_SPL_FS_EXT4 is not set
diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig
index a3b662d..b005522 100644
--- a/configs/omap3_evm_defconfig
+++ b/configs/omap3_evm_defconfig
@@ -7,12 +7,12 @@
CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x400
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DEFAULT_FDT_FILE="omap3-evm.dtb"
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
# CONFIG_SPL_FS_EXT4 is not set
@@ -66,7 +66,10 @@
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
+# CONFIG_SPL_DM_USB is not set
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OMAP3=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_OMAP2PLUS=y
CONFIG_USB_GADGET=y
diff --git a/configs/omap3_ha_defconfig b/configs/omap3_ha_defconfig
index 49229ec..c2d2a31 100644
--- a/configs/omap3_ha_defconfig
+++ b/configs/omap3_ha_defconfig
@@ -5,9 +5,9 @@
CONFIG_TARGET_TAO3530=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x40200800
CONFIG_SYS_EXTRA_OPTIONS="SYS_BOARD_OMAP3_HA"
CONFIG_BOOTDELAY=3
-CONFIG_SPL_TEXT_BASE=0x40200800
# CONFIG_SPL_FS_EXT4 is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMI is not set
diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
index 0868e33..81b57a8 100644
--- a/configs/omap3_logic_defconfig
+++ b/configs/omap3_logic_defconfig
@@ -9,12 +9,14 @@
# CONFIG_SPL_OMAP3_ID_NAND is not set
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ANDROID_BOOT_IMAGE=y
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="setenv preboot;saveenv;"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
# CONFIG_SPL_FS_EXT4 is not set
@@ -40,7 +42,6 @@
# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
@@ -68,6 +69,7 @@
CONFIG_DM_USB=y
# CONFIG_SPL_DM_USB is not set
CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_OMAP is not set
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_OMAP2PLUS=y
CONFIG_TWL4030_USB=y
diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig
index f8dd7f3..656a2d5 100644
--- a/configs/omap3_logic_somlv_defconfig
+++ b/configs/omap3_logic_somlv_defconfig
@@ -9,13 +9,15 @@
# CONFIG_SPL_OMAP3_ID_NAND is not set
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ANDROID_BOOT_IMAGE=y
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="setenv preboot;saveenv;"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DEFAULT_FDT_FILE="logicpd-som-lv-37xx-devkit.dtb"
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
# CONFIG_SPL_FS_EXT4 is not set
diff --git a/configs/omap3_overo_defconfig b/configs/omap3_overo_defconfig
index ff968b3..be604fd 100644
--- a/configs/omap3_overo_defconfig
+++ b/configs/omap3_overo_defconfig
@@ -2,13 +2,14 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_OMAP3_OVERO=y
+CONFIG_ENV_OFFSET=0x240000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
diff --git a/configs/omap4_panda_defconfig b/configs/omap4_panda_defconfig
index 806b7a5..6624ef6 100644
--- a/configs/omap4_panda_defconfig
+++ b/configs/omap4_panda_defconfig
@@ -3,12 +3,12 @@
CONFIG_OMAP44XX=y
CONFIG_TARGET_OMAP4_PANDA=y
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x40300000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_TEXT_BASE=0x40300000
# CONFIG_SPL_FS_EXT4 is not set
# CONFIG_SPL_I2C_SUPPORT is not set
# CONFIG_SPL_NAND_SUPPORT is not set
diff --git a/configs/omap4_sdp4430_defconfig b/configs/omap4_sdp4430_defconfig
index 1d7f21a..9363b7a 100644
--- a/configs/omap4_sdp4430_defconfig
+++ b/configs/omap4_sdp4430_defconfig
@@ -5,13 +5,14 @@
CONFIG_OMAP44XX=y
CONFIG_TARGET_OMAP4_SDP4430=y
CONFIG_CMD_BAT=y
+CONFIG_ENV_OFFSET=0xE0000
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x40300000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_TEXT_BASE=0x40300000
# CONFIG_SPL_I2C_SUPPORT is not set
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_CMD_ASKENV=y
diff --git a/configs/omap5_uevm_defconfig b/configs/omap5_uevm_defconfig
index 719ab8d..3231ff7 100644
--- a/configs/omap5_uevm_defconfig
+++ b/configs/omap5_uevm_defconfig
@@ -5,11 +5,11 @@
CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC=16296
CONFIG_SPL=y
CONFIG_ARMV7_LPAE=y
+CONFIG_SPL_TEXT_BASE=0x40300000
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_TEXT_BASE=0x40300000
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_OS_BOOT=y
CONFIG_CMD_SPL=y
diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig
index 48f251e..9821df9 100644
--- a/configs/omapl138_lcdk_defconfig
+++ b/configs/omapl138_lcdk_defconfig
@@ -11,47 +11,66 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x80000000
CONFIG_BOOTDELAY=3
CONFIG_LOGLEVEL=3
CONFIG_MISC_INIT_R=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x80000000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xb5
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CRC32_VERIFY=y
# CONFIG_CMD_EEPROM is not set
+CONFIG_MX_CYCLIC=y
+CONFIG_CMD_DM=y
# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_GPIO is not set
CONFIG_CMD_NAND=y
+# CONFIG_CMD_PINMUX is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_DIAG=y
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="da850-lcdk"
+CONFIG_SPL_OF_PLATDATA=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_DA8XX_GPIO=y
CONFIG_DM_I2C=y
-CONFIG_DM_I2C_COMPAT=y
CONFIG_SYS_I2C_DAVINCI=y
CONFIG_DM_MMC=y
+CONFIG_MTD=y
CONFIG_NAND=y
+CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_DAVINCI=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x28000
CONFIG_SPL_NAND_SIMPLE=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=30000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_DRIVER_TI_EMAC=y
+CONFIG_PHY=y
+CONFIG_PHY_DA8XX_USB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DAVINCI_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+# CONFIG_SPL_DM_USB is not set
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_DA8XX=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_DA8XX=y
+CONFIG_USB_MUSB_PIO_ONLY=y
+CONFIG_USB_STORAGE=y
+# CONFIG_SPL_OF_LIBFDT is not set
diff --git a/configs/openrd_base_defconfig b/configs/openrd_base_defconfig
index 23521b2..43dc6c5 100644
--- a/configs/openrd_base_defconfig
+++ b/configs/openrd_base_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
@@ -8,6 +9,7 @@
CONFIG_IDENT_STRING="\nOpenRD-Base"
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_BASE"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_LOGLEVEL=2
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/openrd_client_defconfig b/configs/openrd_client_defconfig
index ea53231..71c4475 100644
--- a/configs/openrd_client_defconfig
+++ b/configs/openrd_client_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
@@ -8,6 +9,7 @@
CONFIG_IDENT_STRING="\nOpenRD-Client"
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_CLIENT"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_LOGLEVEL=2
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/openrd_ultimate_defconfig b/configs/openrd_ultimate_defconfig
index 589e248..bdfa4ac 100644
--- a/configs/openrd_ultimate_defconfig
+++ b/configs/openrd_ultimate_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
@@ -8,6 +9,7 @@
CONFIG_IDENT_STRING="\nOpenRD-Ultimate"
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_ULTIMATE"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_LOGLEVEL=2
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig
index b0ec120..5eef652 100644
--- a/configs/opos6uldev_defconfig
+++ b/configs/opos6uldev_defconfig
@@ -12,17 +12,18 @@
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_CMD_BMODE is not set
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x400
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttymxc0,115200"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="run check_env"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="imx6ul-opos6uldev.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_BOUNCE_BUFFER=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
@@ -68,7 +69,7 @@
CONFIG_SYS_I2C_MXC=y
CONFIG_PWRSEQ=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig
index 82ec242..7b02c59 100644
--- a/configs/orangepi-rk3399_defconfig
+++ b/configs/orangepi-rk3399_defconfig
@@ -1,9 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
CONFIG_NR_DRAM_BANKS=1
@@ -14,6 +11,7 @@
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_TPL=y
@@ -55,6 +53,5 @@
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig
index 803c061..664b4b3 100644
--- a/configs/orangepi_2_defconfig
+++ b/configs/orangepi_2_defconfig
@@ -7,7 +7,7 @@
CONFIG_DRAM_CLK=672
CONFIG_USB1_VBUS_PIN="PG13"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/orangepi_lite2_defconfig b/configs/orangepi_lite2_defconfig
index e5c2846..0d6101f 100644
--- a/configs/orangepi_lite2_defconfig
+++ b/configs/orangepi_lite2_defconfig
@@ -3,11 +3,14 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_MACH_SUN50I_H6=y
+CONFIG_SUNXI_DRAM_H6_LPDDR3=y
CONFIG_MMC0_CD_PIN="PF6"
# CONFIG_PSCI_RESET is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x20060
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-orangepi-lite2"
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
diff --git a/configs/orangepi_lite_defconfig b/configs/orangepi_lite_defconfig
index 8621ca3..5638c4a 100644
--- a/configs/orangepi_lite_defconfig
+++ b/configs/orangepi_lite_defconfig
@@ -5,7 +5,7 @@
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig
index d51491d..4fe81f8 100644
--- a/configs/orangepi_one_defconfig
+++ b/configs/orangepi_one_defconfig
@@ -5,7 +5,7 @@
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/orangepi_one_plus_defconfig b/configs/orangepi_one_plus_defconfig
index 65537c4..890e6ab 100644
--- a/configs/orangepi_one_plus_defconfig
+++ b/configs/orangepi_one_plus_defconfig
@@ -3,11 +3,14 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_MACH_SUN50I_H6=y
+CONFIG_SUNXI_DRAM_H6_LPDDR3=y
CONFIG_MMC0_CD_PIN="PF6"
# CONFIG_PSCI_RESET is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x20060
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-orangepi-one-plus"
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig
index 1069cc7..ba0f2d5 100644
--- a/configs/orangepi_pc2_defconfig
+++ b/configs/orangepi_pc2_defconfig
@@ -9,7 +9,8 @@
CONFIG_MACPWR="PD6"
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x10060
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig
index e4626f0..6ac4664 100644
--- a/configs/orangepi_pc_defconfig
+++ b/configs/orangepi_pc_defconfig
@@ -5,7 +5,7 @@
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=624
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/orangepi_pc_plus_defconfig b/configs/orangepi_pc_plus_defconfig
index a9e00fc..685b577 100644
--- a/configs/orangepi_pc_plus_defconfig
+++ b/configs/orangepi_pc_plus_defconfig
@@ -6,7 +6,7 @@
CONFIG_DRAM_CLK=624
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/orangepi_plus2e_defconfig b/configs/orangepi_plus2e_defconfig
index 592fb9d..79da5ce 100644
--- a/configs/orangepi_plus2e_defconfig
+++ b/configs/orangepi_plus2e_defconfig
@@ -7,7 +7,7 @@
CONFIG_MACPWR="PD6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig
index 6433d0b..808f937 100644
--- a/configs/orangepi_plus_defconfig
+++ b/configs/orangepi_plus_defconfig
@@ -9,7 +9,7 @@
CONFIG_USB1_VBUS_PIN="PG13"
CONFIG_SATAPWR="PG11"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/orangepi_prime_defconfig b/configs/orangepi_prime_defconfig
index d862674..d7b8004 100644
--- a/configs/orangepi_prime_defconfig
+++ b/configs/orangepi_prime_defconfig
@@ -7,7 +7,7 @@
CONFIG_DRAM_ZQ=3881977
# CONFIG_DRAM_ODT_EN is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x10060
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/orangepi_r1_defconfig b/configs/orangepi_r1_defconfig
index 2b2d6f2..e0a530d 100644
--- a/configs/orangepi_r1_defconfig
+++ b/configs/orangepi_r1_defconfig
@@ -7,8 +7,9 @@
# CONFIG_VIDEO_DE2 is not set
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000
# CONFIG_CMD_FLASH is not set
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-orangepi-r1"
CONFIG_SUN8I_EMAC=y
diff --git a/configs/orangepi_win_defconfig b/configs/orangepi_win_defconfig
index 59e9639..2839503 100644
--- a/configs/orangepi_win_defconfig
+++ b/configs/orangepi_win_defconfig
@@ -6,7 +6,8 @@
CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x10060
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/orangepi_zero_defconfig b/configs/orangepi_zero_defconfig
index c354c8b..f8dda05 100644
--- a/configs/orangepi_zero_defconfig
+++ b/configs/orangepi_zero_defconfig
@@ -7,8 +7,9 @@
# CONFIG_VIDEO_DE2 is not set
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_CONSOLE_MUX=y
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000
# CONFIG_CMD_FLASH is not set
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-orangepi-zero"
CONFIG_SUN8I_EMAC=y
diff --git a/configs/orangepi_zero_plus2_defconfig b/configs/orangepi_zero_plus2_defconfig
index 7610179..7cfb39d 100644
--- a/configs/orangepi_zero_plus2_defconfig
+++ b/configs/orangepi_zero_plus2_defconfig
@@ -9,7 +9,7 @@
CONFIG_MMC0_CD_PIN="PH13"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x10060
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/orangepi_zero_plus_defconfig b/configs/orangepi_zero_plus_defconfig
index 671d871..c63b70f 100644
--- a/configs/orangepi_zero_plus_defconfig
+++ b/configs/orangepi_zero_plus_defconfig
@@ -7,7 +7,7 @@
CONFIG_DRAM_ZQ=3881977
# CONFIG_DRAM_ODT_EN is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x10060
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/origen_defconfig b/configs/origen_defconfig
index e7d2f45..d7c3ea5 100644
--- a/configs/origen_defconfig
+++ b/configs/origen_defconfig
@@ -1,17 +1,18 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x43E00000
CONFIG_ARCH_EXYNOS4=y
CONFIG_TARGET_ORIGEN=y
CONFIG_SPL=y
CONFIG_IDENT_STRING=" for ORIGEN"
+CONFIG_SPL_TEXT_BASE=0x02021410
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_TEXT_BASE=0x02021410
CONFIG_SYS_PROMPT="ORIGEN # "
# CONFIG_CMD_XIMG is not set
CONFIG_CMD_THOR_DOWNLOAD=y
diff --git a/configs/ot1200_defconfig b/configs/ot1200_defconfig
index f0fe375..0fbfc61 100644
--- a/configs/ot1200_defconfig
+++ b/configs/ot1200_defconfig
@@ -5,6 +5,7 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/bachmann/ot1200/mx6q_4x_mt41j128.cfg,MX6Q"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
CONFIG_BOUNCE_BUFFER=y
@@ -31,7 +32,7 @@
CONFIG_DM=y
CONFIG_DWC_AHSATA=y
CONFIG_CMD_PCA953X=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=2
CONFIG_SF_DEFAULT_MODE=0
diff --git a/configs/ot1200_spl_defconfig b/configs/ot1200_spl_defconfig
index 9bc22fe..989d00c 100644
--- a/configs/ot1200_spl_defconfig
+++ b/configs/ot1200_spl_defconfig
@@ -10,15 +10,17 @@
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@@ -41,7 +43,7 @@
CONFIG_DM=y
CONFIG_DWC_AHSATA=y
CONFIG_CMD_PCA953X=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=2
CONFIG_SF_DEFAULT_MODE=0
diff --git a/configs/parrot_r16_defconfig b/configs/parrot_r16_defconfig
index 56b476b..d0ef1b6 100644
--- a/configs/parrot_r16_defconfig
+++ b/configs/parrot_r16_defconfig
@@ -12,7 +12,7 @@
CONFIG_USB1_VBUS_PIN="PD12"
CONFIG_AXP_GPIO=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_PARTITION_UUIDS is not set
diff --git a/configs/paz00_defconfig b/configs/paz00_defconfig
index 3b0ca3b..0b769d4 100644
--- a/configs/paz00_defconfig
+++ b/configs/paz00_defconfig
@@ -4,9 +4,9 @@
CONFIG_NR_DRAM_BANKS=2
CONFIG_TEGRA20=y
CONFIG_TARGET_PAZ00=y
+CONFIG_SPL_TEXT_BASE=0x00108000
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_SYS_STDIO_DEREGISTER=y
-CONFIG_SPL_TEXT_BASE=0x00108000
CONFIG_SYS_PROMPT="Tegra20 (Paz00) MOD # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/pcm051_rev1_defconfig b/configs/pcm051_rev1_defconfig
index 718c33f..1743376 100644
--- a/configs/pcm051_rev1_defconfig
+++ b/configs/pcm051_rev1_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig
index 05ebe66..d85e3fc 100644
--- a/configs/pcm051_rev3_defconfig
+++ b/configs/pcm051_rev3_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
diff --git a/configs/pcm052_defconfig b/configs/pcm052_defconfig
index 171341b..b7e3d04 100644
--- a/configs/pcm052_defconfig
+++ b/configs/pcm052_defconfig
@@ -39,7 +39,7 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_NAND_VF610_NFC=y
CONFIG_NAND_VF610_NFC_DT=y
diff --git a/configs/pcm058_defconfig b/configs/pcm058_defconfig
index c461459..879f993 100644
--- a/configs/pcm058_defconfig
+++ b/configs/pcm058_defconfig
@@ -13,6 +13,7 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_CMD_HDMIDETECT=y
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
@@ -21,11 +22,11 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
# CONFIG_CMD_FLASH is not set
@@ -43,9 +44,10 @@
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_NAND=y
+CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_MXS=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig
index c1904f1..a3da90f 100644
--- a/configs/peach-pi_defconfig
+++ b/configs/peach-pi_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x23E00000
CONFIG_ARCH_EXYNOS5=y
@@ -6,12 +7,12 @@
CONFIG_NR_DRAM_BANKS=7
CONFIG_SPL=y
CONFIG_IDENT_STRING=" for Peach-Pi"
+CONFIG_SPL_TEXT_BASE=0x02024410
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SILENT_CONSOLE=y
# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_TEXT_BASE=0x02024410
CONFIG_SYS_PROMPT="Peach-Pi # "
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig
index da4155b..df7ce5b 100644
--- a/configs/peach-pit_defconfig
+++ b/configs/peach-pit_defconfig
@@ -1,16 +1,17 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x23E00000
CONFIG_ARCH_EXYNOS5=y
CONFIG_TARGET_PEACH_PIT=y
CONFIG_SPL=y
CONFIG_IDENT_STRING=" for Peach-Pit"
+CONFIG_SPL_TEXT_BASE=0x02024410
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SILENT_CONSOLE=y
# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_TEXT_BASE=0x02024410
CONFIG_SYS_PROMPT="Peach-Pit # "
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
diff --git a/configs/pengwyn_defconfig b/configs/pengwyn_defconfig
index b0c0520..bd7d0a6 100644
--- a/configs/pengwyn_defconfig
+++ b/configs/pengwyn_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -7,6 +8,7 @@
CONFIG_TARGET_PENGWYN=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
CONFIG_SPL=y
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
diff --git a/configs/pepper_defconfig b/configs/pepper_defconfig
index a1dbf5f..85349f4 100644
--- a/configs/pepper_defconfig
+++ b/configs/pepper_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
diff --git a/configs/pfla02_defconfig b/configs/pfla02_defconfig
index aeab883..7bd146d 100644
--- a/configs/pfla02_defconfig
+++ b/configs/pfla02_defconfig
@@ -13,6 +13,7 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_CMD_HDMIDETECT=y
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
@@ -21,11 +22,11 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
# CONFIG_CMD_FLASH is not set
@@ -42,7 +43,7 @@
CONFIG_CMD_UBI=y
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
diff --git a/configs/phycore-am335x-r2-wega_defconfig b/configs/phycore-am335x-r2-wega_defconfig
new file mode 100644
index 0000000..43acb55
--- /dev/null
+++ b/configs/phycore-am335x-r2-wega_defconfig
@@ -0,0 +1,82 @@
+CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_AM33XX=y
+CONFIG_SYS_MPUCLK=1000
+CONFIG_TARGET_PHYCORE_AM335X_R2=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_OFFSET=0x000a0000
+CONFIG_SPL=y
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+# CONFIG_FIT is not set
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DEFAULT_FDT_FILE="am335x-wega-rdk.dtb"
+CONFIG_VERSION_VARIABLE=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_PAYLOAD="u-boot.img"
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_SPL=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),512k(NAND.u-boot),512k(NAND.u-boot.backup1),256k(NAND.u-boot-env),-(NAND.UBI)"
+CONFIG_CMD_UBI=y
+CONFIG_DOS_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="am335x-wega-rdk"
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_ENV_FAT_INTERFACE="mmc"
+CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DM_I2C=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_OMAP_HS=y
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
+CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x100000
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_ETH=y
+CONFIG_MII=y
+CONFIG_DRIVER_TI_CPSW=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_OMAP3_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_TI=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_ETHER=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig
index 2e6a4a7..2914ede 100644
--- a/configs/phycore-rk3288_defconfig
+++ b/configs/phycore-rk3288_defconfig
@@ -1,7 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00000000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3288=y
CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
CONFIG_TARGET_PHYCORE_RK3288=y
@@ -10,13 +9,14 @@
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0xff704000
# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
CONFIG_DEFAULT_FDT_FILE="rk3288-phycore-rdk.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0xff704000
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_SPL_I2C_SUPPORT=y
@@ -28,6 +28,7 @@
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
@@ -80,10 +81,8 @@
CONFIG_USB_GADGET_VENDOR_NUM=0x2207
CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USB_FUNCTION_MASS_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
diff --git a/configs/phycore_pcl063_defconfig b/configs/phycore_pcl063_defconfig
index a051a8d..be16f48 100644
--- a/configs/phycore_pcl063_defconfig
+++ b/configs/phycore_pcl063_defconfig
@@ -8,12 +8,12 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=8
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x00909000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x00909000
CONFIG_SPL_USB_HOST_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_MEMTEST=y
@@ -35,7 +35,7 @@
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-phycore-segin"
CONFIG_DM_I2C_GPIO=y
CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
diff --git a/configs/phycore_pcl063_ull_defconfig b/configs/phycore_pcl063_ull_defconfig
index 5c07b95..4b9bb36 100644
--- a/configs/phycore_pcl063_ull_defconfig
+++ b/configs/phycore_pcl063_ull_defconfig
@@ -30,7 +30,7 @@
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-phycore-segin"
CONFIG_DM_I2C_GPIO=y
CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_FEC_MXC=y
diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig
index d411031..1194d2d 100644
--- a/configs/pic32mzdask_defconfig
+++ b/configs/pic32mzdask_defconfig
@@ -41,5 +41,4 @@
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_PIC32=y
CONFIG_FAT_WRITE=y
-CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
diff --git a/configs/pico-hobbit-imx6ul_defconfig b/configs/pico-hobbit-imx6ul_defconfig
index bb6a9e4..dda8ef4 100644
--- a/configs/pico-hobbit-imx6ul_defconfig
+++ b/configs/pico-hobbit-imx6ul_defconfig
@@ -10,6 +10,7 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
@@ -17,7 +18,6 @@
CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-hobbit.dtb"
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_USB_HOST_SUPPORT=y
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_USB_SDP_SUPPORT=y
@@ -46,7 +46,7 @@
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig
index 9545d6b..62a9423 100644
--- a/configs/pico-hobbit-imx7d_defconfig
+++ b/configs/pico-hobbit-imx7d_defconfig
@@ -12,12 +12,12 @@
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
+CONFIG_SPL_TEXT_BASE=0x00911000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx7d-pico-hobbit.dtb"
CONFIG_BOUNCE_BUFFER=y
-CONFIG_SPL_TEXT_BASE=0x00911000
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_USB_HOST_SUPPORT=y
CONFIG_SPL_USB_GADGET=y
@@ -52,12 +52,13 @@
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
CONFIG_USB_GADGET=y
diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig
index 3284680..a0ac01d 100644
--- a/configs/pico-imx6ul_defconfig
+++ b/configs/pico-imx6ul_defconfig
@@ -10,6 +10,7 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
@@ -17,7 +18,6 @@
CONFIG_DEFAULT_FDT_FILE="ask"
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_USB_HOST_SUPPORT=y
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_USB_SDP_SUPPORT=y
@@ -48,7 +48,7 @@
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
diff --git a/configs/pico-imx7d_bl33_defconfig b/configs/pico-imx7d_bl33_defconfig
index 932ed4c..a2cddfc 100644
--- a/configs/pico-imx7d_bl33_defconfig
+++ b/configs/pico-imx7d_bl33_defconfig
@@ -43,13 +43,14 @@
CONFIG_DFU_MMC=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
CONFIG_CONS_INDEX=4
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
CONFIG_USB_GADGET=y
@@ -63,4 +64,3 @@
CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00"
CONFIG_VIDEO=y
CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_OPTEE_TZDRAM_SIZE=0x2000000
diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig
index 92ab9c5..3785477 100644
--- a/configs/pico-imx7d_defconfig
+++ b/configs/pico-imx7d_defconfig
@@ -12,12 +12,12 @@
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
+CONFIG_SPL_TEXT_BASE=0x00911000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="ask"
CONFIG_BOUNCE_BUFFER=y
-CONFIG_SPL_TEXT_BASE=0x00911000
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_USB_HOST_SUPPORT=y
CONFIG_SPL_USB_GADGET=y
@@ -52,12 +52,13 @@
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
CONFIG_USB_GADGET=y
diff --git a/configs/pico-pi-imx6ul_defconfig b/configs/pico-pi-imx6ul_defconfig
index d52c09e..7463b3f 100644
--- a/configs/pico-pi-imx6ul_defconfig
+++ b/configs/pico-pi-imx6ul_defconfig
@@ -10,6 +10,7 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
@@ -17,7 +18,6 @@
CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-pi.dtb"
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_USB_HOST_SUPPORT=y
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_USB_SDP_SUPPORT=y
@@ -46,7 +46,7 @@
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig
index 042affe..cf20fd2 100644
--- a/configs/pico-pi-imx7d_defconfig
+++ b/configs/pico-pi-imx7d_defconfig
@@ -12,12 +12,12 @@
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
+CONFIG_SPL_TEXT_BASE=0x00911000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx7d-pico-pi.dtb"
CONFIG_BOUNCE_BUFFER=y
-CONFIG_SPL_TEXT_BASE=0x00911000
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_USB_HOST_SUPPORT=y
CONFIG_SPL_USB_GADGET=y
@@ -52,12 +52,13 @@
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
CONFIG_USB_GADGET=y
diff --git a/configs/picosam9g45_defconfig b/configs/picosam9g45_defconfig
index 6a087b4..537d422 100644
--- a/configs/picosam9g45_defconfig
+++ b/configs/picosam9g45_defconfig
@@ -8,10 +8,12 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0x300000
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
@@ -20,7 +22,6 @@
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x300000
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/pine64-lts_defconfig b/configs/pine64-lts_defconfig
index 0ee1e05..283c1dc 100644
--- a/configs/pine64-lts_defconfig
+++ b/configs/pine64-lts_defconfig
@@ -10,7 +10,8 @@
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x10060
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig
index c112ea0..a7ea1bc 100644
--- a/configs/pine64_plus_defconfig
+++ b/configs/pine64_plus_defconfig
@@ -6,7 +6,7 @@
CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
CONFIG_PINE64_DT_SELECTION=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x10060
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/pine_h64_defconfig b/configs/pine_h64_defconfig
index 5ac89b4..c840ca0 100644
--- a/configs/pine_h64_defconfig
+++ b/configs/pine_h64_defconfig
@@ -3,12 +3,16 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_MACH_SUN50I_H6=y
+CONFIG_SUNXI_DRAM_H6_LPDDR3=y
CONFIG_MMC0_CD_PIN="PF6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_USB3_VBUS_PIN="PL5"
# CONFIG_PSCI_RESET is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x20060
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-pine-h64"
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
diff --git a/configs/pinebook_defconfig b/configs/pinebook_defconfig
index 75cb056..1ed907d 100644
--- a/configs/pinebook_defconfig
+++ b/configs/pinebook_defconfig
@@ -7,7 +7,7 @@
CONFIG_DRAM_ZQ=3881949
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_R_I2C_ENABLE=y
-CONFIG_SPL_TEXT_BASE=0x10060
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/platinum_picon_defconfig b/configs/platinum_picon_defconfig
index 786f6a4..fc0768a 100644
--- a/configs/platinum_picon_defconfig
+++ b/configs/platinum_picon_defconfig
@@ -10,13 +10,14 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6DL"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -47,7 +48,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:14M(spl),2M(uboot),512k(env1),512k(env2),495M(ubi0),14M(res0),2M(res1),512k(res2),512k(res3),-(ubi1)"
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_NAND=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_PHYLIB=y
diff --git a/configs/platinum_titanium_defconfig b/configs/platinum_titanium_defconfig
index c45abb0..8ab916e 100644
--- a/configs/platinum_titanium_defconfig
+++ b/configs/platinum_titanium_defconfig
@@ -10,13 +10,14 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -47,7 +48,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:14M(spl),2M(uboot),512k(env1),512k(env2),-(ubi)"
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_NAND=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_PHYLIB=y
diff --git a/configs/plutux_defconfig b/configs/plutux_defconfig
index 8ac0d40..5648953 100644
--- a/configs/plutux_defconfig
+++ b/configs/plutux_defconfig
@@ -4,11 +4,11 @@
CONFIG_NR_DRAM_BANKS=2
CONFIG_TEGRA20=y
CONFIG_TARGET_PLUTUX=y
+CONFIG_SPL_TEXT_BASE=0x00108000
CONFIG_FIT=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
-CONFIG_SPL_TEXT_BASE=0x00108000
CONFIG_SYS_PROMPT="Tegra20 (Plutux) # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/pm9261_defconfig b/configs/pm9261_defconfig
index d2c4c25..d087699 100644
--- a/configs/pm9261_defconfig
+++ b/configs/pm9261_defconfig
@@ -1,9 +1,13 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0
CONFIG_TARGET_PM9261=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x40000
CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
@@ -30,6 +34,7 @@
CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_DM=y
+CONFIG_BLK=y
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_DM_GPIO=y
@@ -39,6 +44,7 @@
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
@@ -51,5 +57,7 @@
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_DM_VIDEO=y
CONFIG_LCD=y
diff --git a/configs/pm9263_defconfig b/configs/pm9263_defconfig
index ceb7efe..76476e3 100644
--- a/configs/pm9263_defconfig
+++ b/configs/pm9263_defconfig
@@ -1,9 +1,13 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0
CONFIG_TARGET_PM9263=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x40000
CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
@@ -30,6 +34,7 @@
CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_DM=y
+CONFIG_BLK=y
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_DM_GPIO=y
@@ -39,6 +44,7 @@
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
@@ -49,5 +55,7 @@
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
+CONFIG_DM_VIDEO=y
CONFIG_LCD=y
diff --git a/configs/pm9g45_defconfig b/configs/pm9g45_defconfig
index ecfa417..b5304b9 100644
--- a/configs/pm9g45_defconfig
+++ b/configs/pm9g45_defconfig
@@ -40,6 +40,7 @@
CONFIG_AT91_GPIO=y
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_ETH=y
CONFIG_MACB=y
diff --git a/configs/pogo_e02_defconfig b/configs/pogo_e02_defconfig
index 5878060..08c52ff 100644
--- a/configs/pogo_e02_defconfig
+++ b/configs/pogo_e02_defconfig
@@ -1,11 +1,13 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_POGO_E02=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_IDENT_STRING="\nPogo E02"
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="PogoE02> "
# CONFIG_CMD_FLASH is not set
diff --git a/configs/polaroid_mid2407pxe03_defconfig b/configs/polaroid_mid2407pxe03_defconfig
index a2be518..012e1f2 100644
--- a/configs/polaroid_mid2407pxe03_defconfig
+++ b/configs/polaroid_mid2407pxe03_defconfig
@@ -16,7 +16,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/polaroid_mid2809pxe04_defconfig b/configs/polaroid_mid2809pxe04_defconfig
index 6ab4e4e..3564ddc 100644
--- a/configs/polaroid_mid2809pxe04_defconfig
+++ b/configs/polaroid_mid2809pxe04_defconfig
@@ -16,7 +16,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig
index 902294b..67dd3f3 100644
--- a/configs/popmetal-rk3288_defconfig
+++ b/configs/popmetal-rk3288_defconfig
@@ -1,7 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00000000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3288=y
CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
CONFIG_TARGET_POPMETAL_RK3288=y
@@ -10,13 +9,14 @@
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0xff704000
# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
CONFIG_DEFAULT_FDT_FILE="rk3288-popmetal.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0xff704000
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_CMD_GPIO=y
@@ -26,6 +26,7 @@
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
@@ -76,10 +77,8 @@
CONFIG_USB_GADGET_VENDOR_NUM=0x2207
CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USB_FUNCTION_MASS_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
diff --git a/configs/porter_defconfig b/configs/porter_defconfig
index c42754b..f3f5105 100644
--- a/configs/porter_defconfig
+++ b/configs/porter_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
@@ -16,15 +17,16 @@
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0xe6300000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_TEXT_BASE=0xe6300000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
diff --git a/configs/portl2_defconfig b/configs/portl2_defconfig
deleted file mode 100644
index fa546aa..0000000
--- a/configs/portl2_defconfig
+++ /dev/null
@@ -1,45 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SYS_DCACHE_OFF=y
-CONFIG_KIRKWOOD=y
-CONFIG_SYS_TEXT_BASE=0x07d00000
-CONFIG_TARGET_KM_KIRKWOOD=y
-CONFIG_IDENT_STRING="\nKeymile Port-L2"
-CONFIG_SYS_EXTRA_OPTIONS="KM_PORTL2"
-CONFIG_MISC_INIT_R=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
-CONFIG_AUTOBOOT_STOP_STR=" "
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);"
-CONFIG_CMD_UBI=y
-# CONFIG_CMD_UBIFS is not set
-CONFIG_ENV_IS_IN_EEPROM=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_BOOTCOUNT_RAM=y
-CONFIG_BOOTCOUNT_BOOTLIMIT=3
-# CONFIG_MMC is not set
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=8100000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_MVGBE=y
-CONFIG_MII=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_KIRKWOOD_SPI=y
-CONFIG_BCH=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/pov_protab2_ips9_defconfig b/configs/pov_protab2_ips9_defconfig
index d94b316..0b6bf6d 100644
--- a/configs/pov_protab2_ips9_defconfig
+++ b/configs/pov_protab2_ips9_defconfig
@@ -14,7 +14,7 @@
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig
index 5cb2273..30b0f4a 100644
--- a/configs/puma-rk3399_defconfig
+++ b/configs/puma-rk3399_defconfig
@@ -2,9 +2,6 @@
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_BOOT_MODE_REG=0x0
CONFIG_TARGET_PUMA_RK3399=y
@@ -15,20 +12,20 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0xff8c2000
CONFIG_SPL_FIT_GENERATOR="board/theobroma-systems/puma_rk3399/fit_spl_atf.sh"
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0xff8c2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
diff --git a/configs/pumpkin_defconfig b/configs/pumpkin_defconfig
new file mode 100644
index 0000000..a4c215f
--- /dev/null
+++ b/configs/pumpkin_defconfig
@@ -0,0 +1,64 @@
+CONFIG_ARM=y
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_SYS_TEXT_BASE=0x4C000000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_TARGET_MT8516=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEBUG_UART_BASE=0x11005000
+CONFIG_DEBUG_UART_CLOCK=26000000
+# CONFIG_PSCI_RESET is not set
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+# CONFIG_FIT_ENABLE_SHA256_SUPPORT is not set
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_DEFAULT_FDT_FILE="mt8516-pumpkin"
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTI is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_GO is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_MEMORY is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_BLOCK_CACHE is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_DEFAULT_DEVICE_TREE="mt8516-pumpkin"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+# CONFIG_NET is not set
+CONFIG_CLK=y
+CONFIG_DM_GPIO=y
+# CONFIG_INPUT is not set
+CONFIG_DM_MMC=y
+# CONFIG_MMC_QUIRKS is not set
+CONFIG_MMC_MTK=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MT8516=y
+CONFIG_RAM=y
+CONFIG_BAUDRATE=921600
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_MTK=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_MTK_SERIAL=y
+CONFIG_WDT=y
+CONFIG_WDT_MTK=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig
index 1a5955a..201b9c9 100644
--- a/configs/pxm2_defconfig
+++ b/configs/pxm2_defconfig
@@ -10,6 +10,7 @@
CONFIG_TARGET_PXM2=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_SPL_FS_FAT=y
@@ -18,6 +19,7 @@
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
@@ -25,6 +27,7 @@
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/q8_a13_tablet_defconfig b/configs/q8_a13_tablet_defconfig
index 6607a48..4933e6f 100644
--- a/configs/q8_a13_tablet_defconfig
+++ b/configs/q8_a13_tablet_defconfig
@@ -15,7 +15,7 @@
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/q8_a23_tablet_800x480_defconfig b/configs/q8_a23_tablet_800x480_defconfig
index c2eb17f..5968319 100644
--- a/configs/q8_a23_tablet_800x480_defconfig
+++ b/configs/q8_a23_tablet_800x480_defconfig
@@ -16,7 +16,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/q8_a33_tablet_1024x600_defconfig b/configs/q8_a33_tablet_1024x600_defconfig
index 2ceda4e..05a82c4 100644
--- a/configs/q8_a33_tablet_1024x600_defconfig
+++ b/configs/q8_a33_tablet_1024x600_defconfig
@@ -16,7 +16,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/q8_a33_tablet_800x480_defconfig b/configs/q8_a33_tablet_800x480_defconfig
index 3cd7f8f..94a680c 100644
--- a/configs/q8_a33_tablet_800x480_defconfig
+++ b/configs/q8_a33_tablet_800x480_defconfig
@@ -16,7 +16,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig
index d5b33b5..fe09a0d 100644
--- a/configs/qemu-riscv32_defconfig
+++ b/configs/qemu-riscv32_defconfig
@@ -5,5 +5,6 @@
CONFIG_FIT=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_CMD_BOOTEFI_SELFTEST=y
# CONFIG_CMD_MII is not set
CONFIG_OF_PRIOR_STAGE=y
diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig
index a80e68b..7103324 100644
--- a/configs/qemu-riscv32_smode_defconfig
+++ b/configs/qemu-riscv32_smode_defconfig
@@ -6,5 +6,6 @@
CONFIG_FIT=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_CMD_BOOTEFI_SELFTEST=y
# CONFIG_CMD_MII is not set
CONFIG_OF_PRIOR_STAGE=y
diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig
new file mode 100644
index 0000000..78e755b
--- /dev/null
+++ b/configs/qemu-riscv32_spl_defconfig
@@ -0,0 +1,11 @@
+CONFIG_RISCV=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_TARGET_QEMU_VIRT=y
+CONFIG_RISCV_SMODE=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_CMD_MII is not set
+CONFIG_OF_PRIOR_STAGE=y
diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig
index 19a5849..ef84dfd 100644
--- a/configs/qemu-riscv64_defconfig
+++ b/configs/qemu-riscv64_defconfig
@@ -6,5 +6,6 @@
CONFIG_FIT=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_CMD_BOOTEFI_SELFTEST=y
# CONFIG_CMD_MII is not set
CONFIG_OF_PRIOR_STAGE=y
diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig
index 74743a5..1c7a2d1 100644
--- a/configs/qemu-riscv64_smode_defconfig
+++ b/configs/qemu-riscv64_smode_defconfig
@@ -7,5 +7,6 @@
CONFIG_FIT=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_CMD_BOOTEFI_SELFTEST=y
# CONFIG_CMD_MII is not set
CONFIG_OF_PRIOR_STAGE=y
diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig
new file mode 100644
index 0000000..a3f5e29
--- /dev/null
+++ b/configs/qemu-riscv64_spl_defconfig
@@ -0,0 +1,12 @@
+CONFIG_RISCV=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_TARGET_QEMU_VIRT=y
+CONFIG_ARCH_RV64I=y
+CONFIG_RISCV_SMODE=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_CMD_MII is not set
+CONFIG_OF_PRIOR_STAGE=y
diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig
index d89cd44..05ff001 100644
--- a/configs/qemu-x86_64_defconfig
+++ b/configs/qemu-x86_64_defconfig
@@ -12,17 +12,19 @@
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_MP_TABLE=y
CONFIG_GENERATE_ACPI_TABLE=y
+CONFIG_SPL_TEXT_BASE=0xfffd0000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_BUILD_ROM=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
-CONFIG_SPL_TEXT_BASE=0xfffd0000
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_CPU_SUPPORT=y
CONFIG_SPL_ENV_SUPPORT=y
@@ -30,7 +32,6 @@
CONFIG_SPL_PCI=y
CONFIG_SPL_PCH_SUPPORT=y
CONFIG_SPL_RTC_SUPPORT=y
-CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
CONFIG_CMD_BOOTEFI_SELFTEST=y
# CONFIG_CMD_FLASH is not set
@@ -38,17 +39,11 @@
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
CONFIG_CMD_QFW=y
CONFIG_CMD_BOOTSTAGE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx"
CONFIG_REGMAP=y
CONFIG_SYSCON=y
@@ -56,7 +51,6 @@
CONFIG_NVME=y
CONFIG_SPL_DM_RTC=y
CONFIG_SPI=y
-CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_USER=y
diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig
index 898d656..e71b8a0 100644
--- a/configs/qemu-x86_defconfig
+++ b/configs/qemu-x86_defconfig
@@ -6,45 +6,36 @@
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_MP_TABLE=y
CONFIG_GENERATE_ACPI_TABLE=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_BUILD_ROM=y
CONFIG_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
-CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
CONFIG_CMD_BOOTEFI_SELFTEST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_IDE=y
-CONFIG_CMD_PART=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
CONFIG_CMD_QFW=y
CONFIG_CMD_BOOTSTAGE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_MAC_PARTITION=y
-CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx"
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
CONFIG_NVME=y
CONFIG_SPI=y
-CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_USER=y
diff --git a/configs/qemu_arm64_defconfig b/configs/qemu_arm64_defconfig
index b47e256..7237819 100644
--- a/configs/qemu_arm64_defconfig
+++ b/configs/qemu_arm64_defconfig
@@ -4,6 +4,8 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="pci enum"
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_BOOTEFI_SELFTEST=y
diff --git a/configs/qemu_arm_defconfig b/configs/qemu_arm_defconfig
index 19d572a..7c95892 100644
--- a/configs/qemu_arm_defconfig
+++ b/configs/qemu_arm_defconfig
@@ -5,6 +5,8 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="pci enum"
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_BOOTEFI_SELFTEST=y
diff --git a/configs/r2dplus_defconfig b/configs/r2dplus_defconfig
index 4c1912c..e10ac93 100644
--- a/configs/r2dplus_defconfig
+++ b/configs/r2dplus_defconfig
@@ -1,24 +1,32 @@
CONFIG_SH=y
CONFIG_SYS_TEXT_BASE=0x8FE00000
CONFIG_TARGET_R2DPLUS=y
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=-1
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttySC0,115200"
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
+CONFIG_CMD_DM=y
CONFIG_CMD_IDE=y
CONFIG_CMD_PCI=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_DOS_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="sh7751-r2dplus"
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_DM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_RTL8139=y
CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
CONFIG_SCIF_CONSOLE=y
CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/r7-tv-dongle_defconfig b/configs/r7-tv-dongle_defconfig
index 7fbe541..b7d7385 100644
--- a/configs/r7-tv-dongle_defconfig
+++ b/configs/r7-tv-dongle_defconfig
@@ -6,7 +6,7 @@
CONFIG_DRAM_CLK=384
CONFIG_USB1_VBUS_PIN="PG13"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/r8a7795_salvator-x_defconfig b/configs/r8a7795_salvator-x_defconfig
index dfe993a..3098004 100644
--- a/configs/r8a7795_salvator-x_defconfig
+++ b/configs/r8a7795_salvator-x_defconfig
@@ -1,9 +1,11 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0x50000000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_SALVATOR_X=y
CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_SPL_TEXT_BASE=0xe6338000
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
@@ -11,7 +13,6 @@
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a7795-salvator-x.dtb"
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_TEXT_BASE=0xe6338000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
diff --git a/configs/r8a7795_ulcb_defconfig b/configs/r8a7795_ulcb_defconfig
index f85d37c..d241a92 100644
--- a/configs/r8a7795_ulcb_defconfig
+++ b/configs/r8a7795_ulcb_defconfig
@@ -1,10 +1,12 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0x50000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_ULCB=y
CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_SPL_TEXT_BASE=0xe6338000
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
@@ -12,7 +14,6 @@
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a7795-h3ulcb.dtb"
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_TEXT_BASE=0xe6338000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
diff --git a/configs/r8a77965_salvator-x_defconfig b/configs/r8a77965_salvator-x_defconfig
index dc2d495..363e482 100644
--- a/configs/r8a77965_salvator-x_defconfig
+++ b/configs/r8a77965_salvator-x_defconfig
@@ -1,10 +1,12 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0x50000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_SALVATOR_X=y
CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_SPL_TEXT_BASE=0xe6338000
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
@@ -12,7 +14,6 @@
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a77965-salvator-x.dtb"
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_TEXT_BASE=0xe6338000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
diff --git a/configs/r8a77965_ulcb_defconfig b/configs/r8a77965_ulcb_defconfig
index d8d915b..70fee78 100644
--- a/configs/r8a77965_ulcb_defconfig
+++ b/configs/r8a77965_ulcb_defconfig
@@ -1,10 +1,12 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0x50000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_ULCB=y
CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_SPL_TEXT_BASE=0xe6338000
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
@@ -12,7 +14,6 @@
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a77965-m3nulcb.dtb"
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_TEXT_BASE=0xe6338000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
diff --git a/configs/r8a7796_salvator-x_defconfig b/configs/r8a7796_salvator-x_defconfig
index c6f713a..4355659 100644
--- a/configs/r8a7796_salvator-x_defconfig
+++ b/configs/r8a7796_salvator-x_defconfig
@@ -1,10 +1,12 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0x50000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_SALVATOR_X=y
CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_SPL_TEXT_BASE=0xe6338000
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
@@ -12,7 +14,6 @@
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a7796-salvator-x.dtb"
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_TEXT_BASE=0xe6338000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
diff --git a/configs/r8a7796_ulcb_defconfig b/configs/r8a7796_ulcb_defconfig
index 5c11d5c..3f47778 100644
--- a/configs/r8a7796_ulcb_defconfig
+++ b/configs/r8a7796_ulcb_defconfig
@@ -1,10 +1,12 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0x50000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_ULCB=y
CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_SPL_TEXT_BASE=0xe6338000
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
@@ -12,7 +14,6 @@
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a7796-m3ulcb.dtb"
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_TEXT_BASE=0xe6338000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
diff --git a/configs/r8a77970_eagle_defconfig b/configs/r8a77970_eagle_defconfig
index d9e2342..40da71e 100644
--- a/configs/r8a77970_eagle_defconfig
+++ b/configs/r8a77970_eagle_defconfig
@@ -1,10 +1,12 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0x50000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_EAGLE=y
CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_SPL_TEXT_BASE=0xe6318000
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
@@ -12,7 +14,6 @@
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a77970-eagle.dtb"
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_TEXT_BASE=0xe6318000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
diff --git a/configs/r8a77980_condor_defconfig b/configs/r8a77980_condor_defconfig
new file mode 100644
index 0000000..546329d
--- /dev/null
+++ b/configs/r8a77980_condor_defconfig
@@ -0,0 +1,70 @@
+CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_RMOBILE=y
+CONFIG_SYS_TEXT_BASE=0x50000000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_RCAR_GEN3=y
+CONFIG_TARGET_CONDOR=y
+CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_SPL_TEXT_BASE=0xe6318000
+CONFIG_FIT=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_DEFAULT_FDT_FILE="r8a77980-condor.dtb"
+CONFIG_VERSION_VARIABLE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="r8a77980-condor-u-boot"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_BLK=y
+CONFIG_CLK=y
+CONFIG_CLK_RENESAS=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_DM_GPIO=y
+CONFIG_RCAR_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_RCAR_IIC=y
+# CONFIG_MMC is not set
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
+CONFIG_SH_ETHER=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SCIF_CONSOLE=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_RENESAS_RPC_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_STORAGE=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_SMBIOS_MANUFACTURER=""
diff --git a/configs/r8a77990_ebisu_defconfig b/configs/r8a77990_ebisu_defconfig
index edc7478..aec5092 100644
--- a/configs/r8a77990_ebisu_defconfig
+++ b/configs/r8a77990_ebisu_defconfig
@@ -1,10 +1,12 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0x50000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_EBISU=y
CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_SPL_TEXT_BASE=0xe6318000
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
@@ -12,7 +14,6 @@
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a77990-ebisu.dtb"
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_TEXT_BASE=0xe6318000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
diff --git a/configs/r8a77995_draak_defconfig b/configs/r8a77995_draak_defconfig
index 39daf98..1f6add9 100644
--- a/configs/r8a77995_draak_defconfig
+++ b/configs/r8a77995_draak_defconfig
@@ -1,10 +1,12 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0x50000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_DRAAK=y
CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_SPL_TEXT_BASE=0xe6318000
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
@@ -12,7 +14,6 @@
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a77995-draak.dtb"
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_TEXT_BASE=0xe6318000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig
index e5052bb..452e761 100644
--- a/configs/rastaban_defconfig
+++ b/configs/rastaban_defconfig
@@ -10,6 +10,7 @@
CONFIG_TARGET_RASTABAN=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_SPL_FS_FAT=y
@@ -18,11 +19,13 @@
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig
index 6b0d7e5..8938b39 100644
--- a/configs/riotboard_defconfig
+++ b/configs/riotboard_defconfig
@@ -22,7 +22,7 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
diff --git a/configs/riotboard_spl_defconfig b/configs/riotboard_spl_defconfig
index 1b61232..67a15bb 100644
--- a/configs/riotboard_spl_defconfig
+++ b/configs/riotboard_spl_defconfig
@@ -10,6 +10,7 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,SPL,MX6S,DDR_MB=1024"
CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd"
@@ -17,7 +18,6 @@
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_OS_BOOT=y
@@ -32,7 +32,7 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
diff --git a/configs/roc-rk3399-pc_defconfig b/configs/roc-rk3399-pc_defconfig
new file mode 100644
index 0000000..28b1833
--- /dev/null
+++ b/configs/roc-rk3399-pc_defconfig
@@ -0,0 +1,58 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL_STACK_R_ADDR=0x80000
+CONFIG_DEBUG_UART_BASE=0xFF1A0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_TPL=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-roc-pc"
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM_RK3399_LPDDR4=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig
index a9860e4..03c2fe8 100644
--- a/configs/rock-pi-4-rk3399_defconfig
+++ b/configs/rock-pi-4-rk3399_defconfig
@@ -1,9 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
CONFIG_NR_DRAM_BANKS=1
@@ -12,8 +9,10 @@
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4.dtb"
+CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_TPL=y
@@ -43,6 +42,7 @@
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM_RK3399_LPDDR4=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
@@ -57,6 +57,5 @@
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig
index 7639b55..80d6db5 100644
--- a/configs/rock2_defconfig
+++ b/configs/rock2_defconfig
@@ -1,7 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00000000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3288=y
CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
CONFIG_TARGET_ROCK2=y
@@ -10,12 +9,13 @@
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0xff704000
# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_DEFAULT_FDT_FILE="rk3288-rock2-square.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0xff704000
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_CMD_GPIO=y
@@ -25,6 +25,7 @@
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
@@ -77,12 +78,10 @@
CONFIG_USB_GADGET_VENDOR_NUM=0x2207
CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USB_FUNCTION_MASS_STORAGE=y
CONFIG_DM_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
CONFIG_CONSOLE_SCROLL_LINES=10
-CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig
index 6529ded..3ab0af1 100644
--- a/configs/rock64-rk3328_defconfig
+++ b/configs/rock64-rk3328_defconfig
@@ -1,33 +1,31 @@
-CONFIG_SMBIOS_MANUFACTURER="pine64"
-CONFIG_SMBIOS_PRODUCT_NAME="rock64_rk3328"
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_ROCKCHIP_RK3328=y
+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x40000
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SMBIOS_PRODUCT_NAME="rock64_rk3328"
CONFIG_DEBUG_UART=y
-CONFIG_NR_DRAM_BANKS=1
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py"
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock64.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
-CONFIG_FASTBOOT_BUF_ADDR=0x800800
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=1
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
@@ -35,17 +33,26 @@
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
-CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64"
CONFIG_SPL_OF_CONTROL=y
+CONFIG_TPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_TPL_OF_PLATDATA=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TPL_DM=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
+CONFIG_TPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
+CONFIG_TPL_SYSCON=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
+CONFIG_TPL_CLK=y
+CONFIG_FASTBOOT_BUF_ADDR=0x800800
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
@@ -59,7 +66,6 @@
CONFIG_PHY=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
-CONFIG_PINCTRL_ROCKCHIP_RK3328=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
@@ -68,6 +74,7 @@
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
CONFIG_DM_RESET=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
@@ -86,6 +93,7 @@
CONFIG_USB_GADGET_VENDOR_NUM=0x2207
CONFIG_USB_GADGET_PRODUCT_NUM=0x330a
CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL_TINY_MEMSET=y
+CONFIG_TPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
+CONFIG_SMBIOS_MANUFACTURER="pine64"
diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig
index 1958b7e..cb3c68d 100644
--- a/configs/rock960-rk3399_defconfig
+++ b/configs/rock960-rk3399_defconfig
@@ -1,9 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
CONFIG_TARGET_ROCK960_RK3399=y
@@ -11,20 +8,22 @@
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0xff8c2000
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0xff8c2000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
CONFIG_SYS_PROMPT="rock960 => "
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock960"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
@@ -34,8 +33,9 @@
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
-CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_DM_ETH=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
@@ -44,8 +44,16 @@
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+# CONFIG_USB_XHCI_ROCKCHIP is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_ROCKCHIP_USB2_PHY=y
-CONFIG_USE_TINY_PRINTF=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_ERRNO_STR=y
diff --git a/configs/rock_defconfig b/configs/rock_defconfig
index 5c29548..4b02556 100644
--- a/configs/rock_defconfig
+++ b/configs/rock_defconfig
@@ -5,17 +5,17 @@
CONFIG_SYS_TEXT_BASE=0x60000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3188=y
-CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
CONFIG_TARGET_ROCK=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL_STACK_R_ADDR=0x60080000
CONFIG_DEBUG_UART_BASE=0x20064000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0x10080800
+CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3188-radxarock.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0x10080800
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_RANDOM_UUID=y
diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig
index 39e68aa..22b8bc5 100644
--- a/configs/rockpro64-rk3399_defconfig
+++ b/configs/rockpro64-rk3399_defconfig
@@ -1,9 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
CONFIG_NR_DRAM_BANKS=1
@@ -12,8 +9,10 @@
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb"
+CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_TPL=y
@@ -28,9 +27,10 @@
CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpro64"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_RAM_RK3399_LPDDR4=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_ROCKCHIP_EFUSE=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
@@ -42,6 +42,7 @@
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM_RK3399_LPDDR4=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
@@ -56,6 +57,5 @@
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
diff --git a/configs/rpi_0_w_defconfig b/configs/rpi_0_w_defconfig
index 1ab35f1..fe5a776 100644
--- a/configs/rpi_0_w_defconfig
+++ b/configs/rpi_0_w_defconfig
@@ -1,10 +1,13 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_BCM283X=y
CONFIG_SYS_TEXT_BASE=0x00008000
CONFIG_TARGET_RPI_0_W=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="usb start"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig
index 53aa554..bf331c0 100644
--- a/configs/rpi_2_defconfig
+++ b/configs/rpi_2_defconfig
@@ -1,10 +1,13 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_BCM283X=y
CONFIG_SYS_TEXT_BASE=0x00008000
CONFIG_TARGET_RPI_2=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="usb start"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig
index c33ea58..c2417a0 100644
--- a/configs/rpi_3_32b_defconfig
+++ b/configs/rpi_3_32b_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_BCM283X=y
CONFIG_SYS_TEXT_BASE=0x00008000
CONFIG_TARGET_RPI_3_32B=y
@@ -6,6 +7,8 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="usb start"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/rpi_3_b_plus_defconfig b/configs/rpi_3_b_plus_defconfig
index 2ae7b6d..a7904ff 100644
--- a/configs/rpi_3_b_plus_defconfig
+++ b/configs/rpi_3_b_plus_defconfig
@@ -1,11 +1,14 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_BCM283X=y
CONFIG_SYS_TEXT_BASE=0x00080000
CONFIG_TARGET_RPI_3=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=1
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="usb start"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig
index 98573bb..4fa6825 100644
--- a/configs/rpi_3_defconfig
+++ b/configs/rpi_3_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_BCM283X=y
CONFIG_SYS_TEXT_BASE=0x00080000
CONFIG_TARGET_RPI_3=y
@@ -6,6 +7,8 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="usb start"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig
new file mode 100644
index 0000000..dc69690
--- /dev/null
+++ b/configs/rpi_4_32b_defconfig
@@ -0,0 +1,33 @@
+CONFIG_ARM=y
+CONFIG_ARCH_BCM283X=y
+CONFIG_SYS_TEXT_BASE=0x00008000
+CONFIG_TARGET_RPI_4_32B=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="U-Boot> "
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_FS_UUID=y
+CONFIG_OF_BOARD=y
+CONFIG_ENV_FAT_INTERFACE="mmc"
+CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_KEYBOARD=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_BCM2835=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_GENERIC is not set
+# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_CONSOLE_SCROLL_LINES=10
+CONFIG_PHYS_TO_BUS=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig
new file mode 100644
index 0000000..2954e17
--- /dev/null
+++ b/configs/rpi_4_defconfig
@@ -0,0 +1,33 @@
+CONFIG_ARM=y
+CONFIG_ARCH_BCM283X=y
+CONFIG_SYS_TEXT_BASE=0x00080000
+CONFIG_TARGET_RPI_4=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="U-Boot> "
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_FS_UUID=y
+CONFIG_OF_BOARD=y
+CONFIG_ENV_FAT_INTERFACE="mmc"
+CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_KEYBOARD=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_BCM2835=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_GENERIC is not set
+# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_CONSOLE_SCROLL_LINES=10
+CONFIG_PHYS_TO_BUS=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig
index bd15c98..2c04b33 100644
--- a/configs/rpi_defconfig
+++ b/configs/rpi_defconfig
@@ -1,10 +1,13 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_BCM283X=y
CONFIG_SYS_TEXT_BASE=0x00008000
CONFIG_TARGET_RPI=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="usb start"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/rut_defconfig b/configs/rut_defconfig
index 50387d5..ec31d52 100644
--- a/configs/rut_defconfig
+++ b/configs/rut_defconfig
@@ -10,6 +10,7 @@
CONFIG_TARGET_RUT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_SPL_FS_FAT=y
@@ -18,6 +19,7 @@
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
@@ -26,6 +28,7 @@
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
@@ -88,4 +91,3 @@
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_SYS_CONSOLE_BG_COL=0xff
CONFIG_SYS_CONSOLE_FG_COL=0x00
-# CONFIG_OMAP_WATCHDOG is not set
diff --git a/configs/s32v234evb_defconfig b/configs/s32v234evb_defconfig
index deb8c04..7ccb9f1 100644
--- a/configs/s32v234evb_defconfig
+++ b/configs/s32v234evb_defconfig
@@ -11,7 +11,7 @@
CONFIG_CMD_MEMTEST=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LINFLEXUART=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/s5p_goni_defconfig b/configs/s5p_goni_defconfig
index 22c7f9f..edcb24c 100644
--- a/configs/s5p_goni_defconfig
+++ b/configs/s5p_goni_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_S5PC1XX=y
CONFIG_SYS_TEXT_BASE=0x34800000
CONFIG_TARGET_S5P_GONI=y
diff --git a/configs/s5pc210_universal_defconfig b/configs/s5pc210_universal_defconfig
index f7ae484..ad52e3a 100644
--- a/configs/s5pc210_universal_defconfig
+++ b/configs/s5pc210_universal_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x44800000
CONFIG_ARCH_EXYNOS4=y
diff --git a/configs/sagem_f@st1704_ram_defconfig b/configs/sagem_f@st1704_ram_defconfig
index eb6efa2..b146330 100644
--- a/configs/sagem_f@st1704_ram_defconfig
+++ b/configs/sagem_f@st1704_ram_defconfig
@@ -47,7 +47,6 @@
CONFIG_BCM6348_ETH=y
CONFIG_DM_RESET=y
CONFIG_RESET_BCM6345=y
-# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DM_SERIAL=y
CONFIG_BCM6345_SERIAL=y
CONFIG_SPI=y
diff --git a/configs/sama5d27_som1_ek_mmc1_defconfig b/configs/sama5d27_som1_ek_mmc1_defconfig
index 205a439..3d877f7 100644
--- a/configs/sama5d27_som1_ek_mmc1_defconfig
+++ b/configs/sama5d27_som1_ek_mmc1_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x23f00000
CONFIG_TARGET_SAMA5D27_SOM1_EK=y
@@ -9,6 +10,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
CONFIG_SPL=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xf8020000
@@ -16,6 +18,7 @@
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0x200000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2"
@@ -25,7 +28,6 @@
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk1p2 rw rootwait"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_TEXT_BASE=0x200000
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@@ -67,6 +69,7 @@
CONFIG_SF_DEFAULT_SPEED=66000000
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_DM_ETH=y
@@ -80,6 +83,7 @@
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
+CONFIG_ATMEL_QSPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
diff --git a/configs/sama5d27_som1_ek_mmc_defconfig b/configs/sama5d27_som1_ek_mmc_defconfig
index 0a07800..cadaa93 100644
--- a/configs/sama5d27_som1_ek_mmc_defconfig
+++ b/configs/sama5d27_som1_ek_mmc_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x23f00000
CONFIG_TARGET_SAMA5D27_SOM1_EK=y
@@ -9,6 +10,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_DEBUG_UART_BOARD_INIT=y
@@ -17,6 +19,7 @@
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0x200000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2"
@@ -26,7 +29,6 @@
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_TEXT_BASE=0x200000
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@@ -67,6 +69,7 @@
CONFIG_SF_DEFAULT_SPEED=66000000
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_DM_ETH=y
@@ -80,6 +83,7 @@
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
+CONFIG_ATMEL_QSPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
diff --git a/configs/sama5d27_som1_ek_qspiflash_defconfig b/configs/sama5d27_som1_ek_qspiflash_defconfig
new file mode 100644
index 0000000..97f1efc
--- /dev/null
+++ b/configs/sama5d27_som1_ek_qspiflash_defconfig
@@ -0,0 +1,103 @@
+CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_AT91=y
+CONFIG_SYS_TEXT_BASE=0x23f00000
+CONFIG_TARGET_SAMA5D27_SOM1_EK=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_BASE=0xf8020000
+CONFIG_DEBUG_UART_CLOCK=82000000
+CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0x200000
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2"
+CONFIG_QSPI_BOOT=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_som1_ek"
+CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_AT91_GENERIC_CLK=y
+CONFIG_DM_GPIO=y
+CONFIG_ATMEL_PIO4=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_AT91=y
+CONFIG_I2C_EEPROM=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ATMEL=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=66000000
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_DM_ETH=y
+CONFIG_MACB=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_QSPI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
+CONFIG_DM_VIDEO=y
+CONFIG_ATMEL_HLCD=y
+CONFIG_W1=y
+CONFIG_W1_GPIO=y
+CONFIG_W1_EEPROM=y
+CONFIG_W1_EEPROM_DS24XXX=y
+CONFIG_FAT_WRITE=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/sama5d2_icp_mmc_defconfig b/configs/sama5d2_icp_mmc_defconfig
index e047108..535aab5 100644
--- a/configs/sama5d2_icp_mmc_defconfig
+++ b/configs/sama5d2_icp_mmc_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_SAMA5D2_ICP=y
@@ -9,6 +10,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
CONFIG_SPL=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xf801c000
diff --git a/configs/sama5d2_ptc_ek_mmc_defconfig b/configs/sama5d2_ptc_ek_mmc_defconfig
index 25b3aaf..e1ff84f 100644
--- a/configs/sama5d2_ptc_ek_mmc_defconfig
+++ b/configs/sama5d2_ptc_ek_mmc_defconfig
@@ -1,8 +1,10 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_SAMA5D2_PTC_EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xf801c000
@@ -34,7 +36,6 @@
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_ptc_ek"
CONFIG_ENV_IS_IN_FAT=y
CONFIG_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_UTMI=y
@@ -49,6 +50,7 @@
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ATMEL=y
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_ATMEL_NAND_HW_PMECC=y
CONFIG_PMECC_CAP=4
diff --git a/configs/sama5d2_ptc_ek_nandflash_defconfig b/configs/sama5d2_ptc_ek_nandflash_defconfig
index 3f7e627..4210a52 100644
--- a/configs/sama5d2_ptc_ek_nandflash_defconfig
+++ b/configs/sama5d2_ptc_ek_nandflash_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_SAMA5D2_PTC_EK=y
@@ -34,7 +35,6 @@
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_ptc_ek"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_UTMI=y
@@ -48,6 +48,7 @@
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ATMEL=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_ATMEL_NAND_HW_PMECC=y
CONFIG_PMECC_CAP=4
diff --git a/configs/sama5d2_xplained_emmc_defconfig b/configs/sama5d2_xplained_emmc_defconfig
index f643b5a..41c4ef1 100644
--- a/configs/sama5d2_xplained_emmc_defconfig
+++ b/configs/sama5d2_xplained_emmc_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_SAMA5D2_XPLAINED=y
@@ -9,6 +10,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
CONFIG_SPL=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xf8020000
@@ -16,6 +18,7 @@
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0x200000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC"
@@ -24,7 +27,6 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_TEXT_BASE=0x200000
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@@ -65,6 +67,10 @@
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
@@ -76,6 +82,7 @@
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
+CONFIG_ATMEL_QSPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig
index c25d67b..a0db2e4 100644
--- a/configs/sama5d2_xplained_mmc_defconfig
+++ b/configs/sama5d2_xplained_mmc_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_SAMA5D2_XPLAINED=y
@@ -9,6 +10,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_DEBUG_UART_BOARD_INIT=y
@@ -17,6 +19,7 @@
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0x200000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC"
@@ -26,7 +29,6 @@
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk1p2 rw rootwait"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_TEXT_BASE=0x200000
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@@ -67,6 +69,10 @@
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
@@ -78,6 +84,7 @@
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
+CONFIG_ATMEL_QSPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
diff --git a/configs/sama5d2_xplained_qspiflash_defconfig b/configs/sama5d2_xplained_qspiflash_defconfig
new file mode 100644
index 0000000..0dff5d4
--- /dev/null
+++ b/configs/sama5d2_xplained_qspiflash_defconfig
@@ -0,0 +1,103 @@
+CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_AT91=y
+CONFIG_SYS_TEXT_BASE=0x26f00000
+CONFIG_TARGET_SAMA5D2_XPLAINED=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_BASE=0xf8020000
+CONFIG_DEBUG_UART_CLOCK=83000000
+CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0x200000
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC"
+CONFIG_QSPI_BOOT=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p1 rw rootwait"
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained"
+CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_AT91_GENERIC_CLK=y
+CONFIG_DM_GPIO=y
+CONFIG_ATMEL_PIO4=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_AT91=y
+CONFIG_I2C_EEPROM=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ATMEL=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=30000000
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_DM_ETH=y
+CONFIG_MACB=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_QSPI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
+CONFIG_DM_VIDEO=y
+CONFIG_ATMEL_HLCD=y
+CONFIG_W1=y
+CONFIG_W1_GPIO=y
+CONFIG_W1_EEPROM=y
+CONFIG_W1_EEPROM_DS24XXX=y
+CONFIG_FAT_WRITE=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig
index ac5ae51..1592e93 100644
--- a/configs/sama5d2_xplained_spiflash_defconfig
+++ b/configs/sama5d2_xplained_spiflash_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_SAMA5D2_XPLAINED=y
@@ -8,14 +9,18 @@
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x6000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xf8020000
CONFIG_DEBUG_UART_CLOCK=83000000
+CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0x200000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
CONFIG_SPI_BOOT=y
@@ -24,8 +29,8 @@
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p1 rw rootwait"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_TEXT_BASE=0x200000
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
@@ -64,6 +69,10 @@
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
@@ -75,6 +84,7 @@
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
+CONFIG_ATMEL_QSPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
diff --git a/configs/sama5d36ek_cmp_mmc_defconfig b/configs/sama5d36ek_cmp_mmc_defconfig
index e61f897..2f0415d 100644
--- a/configs/sama5d36ek_cmp_mmc_defconfig
+++ b/configs/sama5d36ek_cmp_mmc_defconfig
@@ -1,8 +1,10 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_SAMA5D3XEK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xffffee00
@@ -42,6 +44,7 @@
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/sama5d36ek_cmp_nandflash_defconfig b/configs/sama5d36ek_cmp_nandflash_defconfig
index 9c4ce29..3bcfbf0 100644
--- a/configs/sama5d36ek_cmp_nandflash_defconfig
+++ b/configs/sama5d36ek_cmp_nandflash_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_SAMA5D3XEK=y
@@ -41,6 +42,7 @@
CONFIG_AT91_GPIO=y
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/sama5d36ek_cmp_spiflash_defconfig b/configs/sama5d36ek_cmp_spiflash_defconfig
index 4a876e3..3fbdd54 100644
--- a/configs/sama5d36ek_cmp_spiflash_defconfig
+++ b/configs/sama5d36ek_cmp_spiflash_defconfig
@@ -1,12 +1,16 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_SAMA5D3XEK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x6000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=132000000
+CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
@@ -42,6 +46,7 @@
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig
index d5021eb..0270472 100644
--- a/configs/sama5d3_xplained_mmc_defconfig
+++ b/configs/sama5d3_xplained_mmc_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_SAMA5D3_XPLAINED=y
@@ -9,6 +10,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_DEBUG_UART_BOARD_INIT=y
@@ -17,6 +19,7 @@
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0x300000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
CONFIG_SD_BOOT=y
@@ -24,7 +27,6 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_TEXT_BASE=0x300000
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@@ -61,6 +63,7 @@
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_ETH=y
CONFIG_MACB=y
diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig
index eaeb000..8a2b01f 100644
--- a/configs/sama5d3_xplained_nandflash_defconfig
+++ b/configs/sama5d3_xplained_nandflash_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_SAMA5D3_XPLAINED=y
@@ -14,6 +15,7 @@
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0x300000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
CONFIG_NAND_BOOT=y
@@ -21,7 +23,6 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256K(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_TEXT_BASE=0x300000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@@ -56,6 +57,7 @@
CONFIG_AT91_GPIO=y
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_PMECC_CAP=4
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig
index b770ac4..934d020 100644
--- a/configs/sama5d3xek_mmc_defconfig
+++ b/configs/sama5d3xek_mmc_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_SAMA5D3XEK=y
@@ -9,6 +10,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_DEBUG_UART_BOARD_INIT=y
@@ -17,6 +19,7 @@
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0x300000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
CONFIG_SD_BOOT=y
@@ -26,7 +29,6 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_TEXT_BASE=0x300000
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@@ -67,6 +69,7 @@
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig
index dc8aaeb..3cf365b 100644
--- a/configs/sama5d3xek_nandflash_defconfig
+++ b/configs/sama5d3xek_nandflash_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_SAMA5D3XEK=y
@@ -14,6 +15,7 @@
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=132000000
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0x300000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
CONFIG_NAND_BOOT=y
@@ -23,7 +25,6 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_TEXT_BASE=0x300000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@@ -61,6 +62,7 @@
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_PMECC_CAP=4
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig
index 84bbf9c..ed9d806 100644
--- a/configs/sama5d3xek_spiflash_defconfig
+++ b/configs/sama5d3xek_spiflash_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_SAMA5D3XEK=y
@@ -8,14 +9,18 @@
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x6000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xffffee00
CONFIG_DEBUG_UART_CLOCK=132000000
+CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0x300000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
CONFIG_SPI_BOOT=y
@@ -23,8 +28,8 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256K(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_TEXT_BASE=0x300000
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
@@ -62,6 +67,7 @@
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig
index 0504b4e..58b4bd1 100644
--- a/configs/sama5d4_xplained_mmc_defconfig
+++ b/configs/sama5d4_xplained_mmc_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_SAMA5D4_XPLAINED=y
@@ -9,6 +10,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_DEBUG_UART_BOARD_INIT=y
@@ -17,6 +19,7 @@
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0x200000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
CONFIG_SD_BOOT=y
@@ -25,7 +28,6 @@
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_TEXT_BASE=0x200000
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@@ -58,6 +60,7 @@
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_ATMEL_NAND_HW_PMECC=y
CONFIG_PMECC_CAP=8
diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig
index 1a48121..efdf0a4 100644
--- a/configs/sama5d4_xplained_nandflash_defconfig
+++ b/configs/sama5d4_xplained_nandflash_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_SAMA5D4_XPLAINED=y
@@ -14,6 +15,7 @@
CONFIG_DEBUG_UART_BASE=0xfc00c000
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0x200000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
CONFIG_NAND_BOOT=y
@@ -22,7 +24,6 @@
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256K(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_TEXT_BASE=0x200000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@@ -54,6 +55,7 @@
CONFIG_I2C_EEPROM=y
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_PMECC_CAP=8
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig
index f108689..82458be 100644
--- a/configs/sama5d4_xplained_spiflash_defconfig
+++ b/configs/sama5d4_xplained_spiflash_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_SAMA5D4_XPLAINED=y
@@ -8,14 +9,18 @@
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x6000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfc00c000
CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0x200000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
CONFIG_SPI_BOOT=y
@@ -24,8 +29,8 @@
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256K(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_TEXT_BASE=0x200000
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
@@ -58,6 +63,7 @@
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig
index d7e1701..48f9db4 100644
--- a/configs/sama5d4ek_mmc_defconfig
+++ b/configs/sama5d4ek_mmc_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_SAMA5D4EK=y
@@ -9,6 +10,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_DEBUG_UART_BOARD_INIT=y
@@ -17,6 +19,7 @@
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0x200000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
CONFIG_SD_BOOT=y
@@ -26,7 +29,6 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_TEXT_BASE=0x200000
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@@ -58,6 +60,7 @@
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig
index e3b3f86..a5a151c 100644
--- a/configs/sama5d4ek_nandflash_defconfig
+++ b/configs/sama5d4ek_nandflash_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_SAMA5D4EK=y
@@ -14,6 +15,7 @@
CONFIG_DEBUG_UART_BASE=0xfc00c000
CONFIG_DEBUG_UART_CLOCK=88000000
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0x200000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
CONFIG_NAND_BOOT=y
@@ -23,7 +25,6 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_TEXT_BASE=0x200000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@@ -54,6 +55,7 @@
CONFIG_AT91_GPIO=y
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_PMECC_CAP=8
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig
index 8db517d..e23d6cb 100644
--- a/configs/sama5d4ek_spiflash_defconfig
+++ b/configs/sama5d4ek_spiflash_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_SAMA5D4EK=y
@@ -8,14 +9,18 @@
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x6000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfc00c000
CONFIG_DEBUG_UART_CLOCK=88000000
+CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0x200000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
CONFIG_SPI_BOOT=y
@@ -23,8 +28,8 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256K(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_TEXT_BASE=0x200000
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
@@ -55,6 +60,7 @@
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig
index 29a9df8..7aa2d38 100644
--- a/configs/sandbox64_defconfig
+++ b/configs/sandbox64_defconfig
@@ -1,5 +1,6 @@
CONFIG_SYS_TEXT_BASE=0
CONFIG_NR_DRAM_BANKS=1
+CONFIG_PRE_CON_BUF_ADDR=0x100000
CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_SANDBOX64=y
CONFIG_DISTRO_DEFAULTS=y
@@ -15,7 +16,6 @@
CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
CONFIG_SILENT_CONSOLE=y
CONFIG_PRE_CONSOLE_BUFFER=y
-CONFIG_PRE_CON_BUF_ADDR=0x100000
CONFIG_LOG_MAX_LEVEL=6
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_CPU=y
@@ -89,7 +89,6 @@
CONFIG_BOARD_SANDBOX=y
CONFIG_PM8916_GPIO=y
CONFIG_SANDBOX_GPIO=y
-CONFIG_DM_I2C_COMPAT=y
CONFIG_I2C_CROS_EC_TUNNEL=y
CONFIG_I2C_CROS_EC_LDO=y
CONFIG_DM_I2C_GPIO=y
@@ -163,6 +162,7 @@
CONFIG_DM_RESET=y
CONFIG_SANDBOX_RESET=y
CONFIG_DM_RTC=y
+CONFIG_RTC_RV8803=y
CONFIG_SANDBOX_SERIAL=y
CONFIG_SMEM=y
CONFIG_SANDBOX_SMEM=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index fd51a75..f77b9e8 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -1,5 +1,6 @@
CONFIG_SYS_TEXT_BASE=0
CONFIG_NR_DRAM_BANKS=1
+CONFIG_PRE_CON_BUF_ADDR=0xf0000
CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
@@ -16,7 +17,6 @@
CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
CONFIG_SILENT_CONSOLE=y
CONFIG_PRE_CONSOLE_BUFFER=y
-CONFIG_PRE_CON_BUF_ADDR=0xf0000
CONFIG_LOG_MAX_LEVEL=6
CONFIG_LOG_ERROR_RETURN=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
@@ -49,6 +49,7 @@
CONFIG_CMD_USB=y
CONFIG_CMD_AXI=y
CONFIG_CMD_AB_SELECT=y
+CONFIG_CMD_PCAP=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_TFTPSRV=y
CONFIG_CMD_RARP=y
@@ -93,6 +94,8 @@
CONFIG_DM_BOOTCOUNT=y
CONFIG_DM_BOOTCOUNT_RTC=y
CONFIG_CLK=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SANDBOX_CLK_CCF=y
CONFIG_CPU=y
CONFIG_DM_DEMO=y
CONFIG_DM_DEMO_SIMPLE=y
@@ -106,7 +109,6 @@
CONFIG_SANDBOX_GPIO=y
CONFIG_DM_HWSPINLOCK=y
CONFIG_HWSPINLOCK_SANDBOX=y
-CONFIG_DM_I2C_COMPAT=y
CONFIG_I2C_CROS_EC_TUNNEL=y
CONFIG_I2C_CROS_EC_LDO=y
CONFIG_DM_I2C_GPIO=y
@@ -181,6 +183,7 @@
CONFIG_DM_RESET=y
CONFIG_SANDBOX_RESET=y
CONFIG_DM_RTC=y
+CONFIG_RTC_RV8803=y
CONFIG_DEBUG_UART_SANDBOX=y
CONFIG_SANDBOX_SERIAL=y
CONFIG_SMEM=y
diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig
index af33528..898815f 100644
--- a/configs/sandbox_flattree_defconfig
+++ b/configs/sandbox_flattree_defconfig
@@ -66,6 +66,8 @@
CONFIG_ADC=y
CONFIG_ADC_SANDBOX=y
CONFIG_CLK=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SANDBOX_CLK_CCF=y
CONFIG_CPU=y
CONFIG_DM_DEMO=y
CONFIG_DM_DEMO_SIMPLE=y
@@ -74,7 +76,6 @@
CONFIG_BOARD_SANDBOX=y
CONFIG_PM8916_GPIO=y
CONFIG_SANDBOX_GPIO=y
-CONFIG_DM_I2C_COMPAT=y
CONFIG_I2C_CROS_EC_TUNNEL=y
CONFIG_I2C_CROS_EC_LDO=y
CONFIG_DM_I2C_GPIO=y
diff --git a/configs/sandbox_noblk_defconfig b/configs/sandbox_noblk_defconfig
index da9229f..381bad2 100644
--- a/configs/sandbox_noblk_defconfig
+++ b/configs/sandbox_noblk_defconfig
@@ -81,7 +81,6 @@
CONFIG_BOARD_SANDBOX=y
CONFIG_PM8916_GPIO=y
CONFIG_SANDBOX_GPIO=y
-CONFIG_DM_I2C_COMPAT=y
CONFIG_I2C_CROS_EC_TUNNEL=y
CONFIG_I2C_CROS_EC_LDO=y
CONFIG_DM_I2C_GPIO=y
diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig
index d355cc3..0b3391a 100644
--- a/configs/sandbox_spl_defconfig
+++ b/configs/sandbox_spl_defconfig
@@ -93,9 +93,9 @@
CONFIG_DM_DEMO_SHAPE=y
CONFIG_BOARD=y
CONFIG_BOARD_SANDBOX=y
+CONFIG_SPL_FIRMWARE=y
CONFIG_PM8916_GPIO=y
CONFIG_SANDBOX_GPIO=y
-CONFIG_DM_I2C_COMPAT=y
CONFIG_I2C_CROS_EC_TUNNEL=y
CONFIG_I2C_CROS_EC_LDO=y
CONFIG_DM_I2C_GPIO=y
@@ -191,6 +191,7 @@
CONFIG_SANDBOX_OSD=y
CONFIG_FS_CBFS=y
CONFIG_FS_CRAMFS=y
+# CONFIG_USE_TINY_PRINTF is not set
CONFIG_CMD_DHRYSTONE=y
CONFIG_TPM=y
CONFIG_LZ4=y
diff --git a/configs/sansa_fuze_plus_defconfig b/configs/sansa_fuze_plus_defconfig
index 9d2b28d..eec58c6 100644
--- a/configs/sansa_fuze_plus_defconfig
+++ b/configs/sansa_fuze_plus_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x00001000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200n8 "
@@ -18,7 +19,6 @@
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_TEXT_BASE=0x00001000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MEMTEST=y
# CONFIG_CMD_FLASH is not set
@@ -30,6 +30,7 @@
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MXS_GPIO=y
CONFIG_MMC_MXS=y
CONFIG_CONS_INDEX=0
CONFIG_USB=y
diff --git a/configs/sc_sps_1_defconfig b/configs/sc_sps_1_defconfig
index c7cdc3c..818113b 100644
--- a/configs/sc_sps_1_defconfig
+++ b/configs/sc_sps_1_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x00001000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200"
@@ -16,7 +17,6 @@
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_TEXT_BASE=0x00001000
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
@@ -29,6 +29,7 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_MXS_GPIO=y
CONFIG_MMC_MXS=y
CONFIG_PHYLIB=y
CONFIG_MII=y
diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig
index 47c4540..0dd0a38 100644
--- a/configs/seaboard_defconfig
+++ b/configs/seaboard_defconfig
@@ -4,8 +4,10 @@
CONFIG_NR_DRAM_BANKS=2
CONFIG_TEGRA20=y
CONFIG_TARGET_SEABOARD=y
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_SPL_TEXT_BASE=0x00108000
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="usb start"
CONFIG_SYS_PROMPT="Tegra20 (SeaBoard) # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/secomx6quq7_defconfig b/configs/secomx6quq7_defconfig
index 8526f05..0b690f1 100644
--- a/configs/secomx6quq7_defconfig
+++ b/configs/secomx6quq7_defconfig
@@ -26,7 +26,7 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
diff --git a/configs/sei510_defconfig b/configs/sei510_defconfig
new file mode 100644
index 0000000..5aea81d
--- /dev/null
+++ b/configs/sei510_defconfig
@@ -0,0 +1,64 @@
+CONFIG_ARM=y
+CONFIG_SYS_BOARD="sei510"
+CONFIG_SYS_CONFIG_NAME="sei510"
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_MESON_G12A=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEBUG_UART_BASE=0xff803000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" sei510"
+# CONFIG_PSCI_RESET is not set
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-g12a-sei510"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x6000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=2
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ADDR=8
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_MESON_G12A_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_G12A=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_MESON_G12A=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x18d1
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
+CONFIG_LZ4=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/sfr_nb4-ser_ram_defconfig b/configs/sfr_nb4-ser_ram_defconfig
index 07ad515..db12ce8 100644
--- a/configs/sfr_nb4-ser_ram_defconfig
+++ b/configs/sfr_nb4-ser_ram_defconfig
@@ -51,7 +51,6 @@
CONFIG_BCM6358_USBH_PHY=y
CONFIG_DM_RESET=y
CONFIG_RESET_BCM6345=y
-# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DM_SERIAL=y
CONFIG_BCM6345_SERIAL=y
CONFIG_USB=y
diff --git a/configs/sheep-rk3368_defconfig b/configs/sheep-rk3368_defconfig
index cff1905..4883f59 100644
--- a/configs/sheep-rk3368_defconfig
+++ b/configs/sheep-rk3368_defconfig
@@ -1,7 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
-CONFIG_SYS_MALLOC_F_LEN=0x1000
CONFIG_ROCKCHIP_RK3368=y
CONFIG_TARGET_SHEEP=y
CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig
index 74a52e6..734e894 100644
--- a/configs/sheevaplug_defconfig
+++ b/configs/sheevaplug_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
@@ -8,6 +9,7 @@
CONFIG_IDENT_STRING="\nMarvell-Sheevaplug"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
diff --git a/configs/sifive_fu540_defconfig b/configs/sifive_fu540_defconfig
index f784123..48865e5 100644
--- a/configs/sifive_fu540_defconfig
+++ b/configs/sifive_fu540_defconfig
@@ -5,6 +5,7 @@
CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
+CONFIG_MISC_INIT_R=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_OF_PRIOR_STAGE=y
diff --git a/configs/silk_defconfig b/configs/silk_defconfig
index e38f634..db63b14 100644
--- a/configs/silk_defconfig
+++ b/configs/silk_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
@@ -16,15 +17,16 @@
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0xe6300000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_TEXT_BASE=0xe6300000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
diff --git a/configs/sksimx6_defconfig b/configs/sksimx6_defconfig
index 164614d..5fbc94a 100644
--- a/configs/sksimx6_defconfig
+++ b/configs/sksimx6_defconfig
@@ -12,6 +12,7 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -23,7 +24,6 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
@@ -33,7 +33,7 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
diff --git a/configs/slimbootloader_defconfig b/configs/slimbootloader_defconfig
new file mode 100644
index 0000000..f9fecff
--- /dev/null
+++ b/configs/slimbootloader_defconfig
@@ -0,0 +1,20 @@
+CONFIG_X86=y
+CONFIG_VENDOR_INTEL=y
+CONFIG_TARGET_SLIMBOOTLOADER=y
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_BOOTDELAY=10
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_LAST_STAGE_INIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_DEFAULT_DEVICE_TREE="slimbootloader"
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+# CONFIG_PCI_PNP is not set
+CONFIG_CONSOLE_SCROLL_LINES=5
diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig
index 656188f..9e73051 100644
--- a/configs/smartweb_defconfig
+++ b/configs/smartweb_defconfig
@@ -11,6 +11,7 @@
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_OFFSET=0x100000
CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
@@ -47,6 +48,7 @@
CONFIG_DFU_NAND=y
# CONFIG_MMC is not set
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_PHYLIB=y
CONFIG_USB=y
diff --git a/configs/smdk5250_defconfig b/configs/smdk5250_defconfig
index 1bdcc47..adec9b7 100644
--- a/configs/smdk5250_defconfig
+++ b/configs/smdk5250_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_EXYNOS=y
@@ -8,13 +9,13 @@
CONFIG_NR_DRAM_BANKS=8
CONFIG_SPL=y
CONFIG_IDENT_STRING=" for SMDK5250"
+CONFIG_SPL_TEXT_BASE=0x02023400
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_TEXT_BASE=0x02023400
CONFIG_SYS_PROMPT="SMDK5250 # "
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
diff --git a/configs/smdk5420_defconfig b/configs/smdk5420_defconfig
index 7510f80..3523f4b 100644
--- a/configs/smdk5420_defconfig
+++ b/configs/smdk5420_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x23E00000
CONFIG_ARCH_EXYNOS5=y
@@ -6,13 +7,13 @@
CONFIG_NR_DRAM_BANKS=7
CONFIG_SPL=y
CONFIG_IDENT_STRING=" for SMDK5420"
+CONFIG_SPL_TEXT_BASE=0x02024410
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_TEXT_BASE=0x02024410
CONFIG_SYS_PROMPT="SMDK5420 # "
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
diff --git a/configs/smdkc100_defconfig b/configs/smdkc100_defconfig
index 3e21616..88b56cb 100644
--- a/configs/smdkc100_defconfig
+++ b/configs/smdkc100_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_S5PC1XX=y
CONFIG_SYS_TEXT_BASE=0x34800000
CONFIG_TARGET_SMDKC100=y
diff --git a/configs/smdkv310_defconfig b/configs/smdkv310_defconfig
index 1725769..7d15aed 100644
--- a/configs/smdkv310_defconfig
+++ b/configs/smdkv310_defconfig
@@ -1,13 +1,14 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x43E00000
CONFIG_ARCH_EXYNOS4=y
CONFIG_SPL=y
CONFIG_IDENT_STRING=" for SMDKC210/V310"
+CONFIG_SPL_TEXT_BASE=0x02021410
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_TEXT_BASE=0x02021410
CONFIG_SYS_PROMPT="SMDKV310 # "
# CONFIG_CMD_XIMG is not set
CONFIG_CMD_GPT=y
diff --git a/configs/snapper9260_defconfig b/configs/snapper9260_defconfig
index 7ce29bf..d3d51c5 100644
--- a/configs/snapper9260_defconfig
+++ b/configs/snapper9260_defconfig
@@ -1,7 +1,10 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_TARGET_SNAPPER9260=y
+CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_OFFSET=0x80000
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260"
@@ -29,6 +32,7 @@
CONFIG_CMD_PCA953X=y
# CONFIG_MMC is not set
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/snapper9g20_defconfig b/configs/snapper9g20_defconfig
index 2773c6b..6466ee8 100644
--- a/configs/snapper9g20_defconfig
+++ b/configs/snapper9g20_defconfig
@@ -1,7 +1,10 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_TARGET_SNAPPER9260=y
+CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_OFFSET=0x80000
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20"
@@ -28,6 +31,7 @@
CONFIG_CMD_PCA953X=y
# CONFIG_MMC is not set
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/sniper_defconfig b/configs/sniper_defconfig
index deaad35..8b35b2e 100644
--- a/configs/sniper_defconfig
+++ b/configs/sniper_defconfig
@@ -5,10 +5,10 @@
CONFIG_TARGET_SNIPER=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SPL_TEXT_BASE=0x40200000
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=2
diff --git a/configs/snow_defconfig b/configs/snow_defconfig
index f474409..209e41f 100644
--- a/configs/snow_defconfig
+++ b/configs/snow_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_EXYNOS=y
@@ -11,12 +12,12 @@
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_IDENT_STRING=" for snow"
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0x02023400
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SILENT_CONSOLE=y
# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_TEXT_BASE=0x02023400
CONFIG_SYS_PROMPT="snow # "
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig
index 69e492a..7cb214d 100644
--- a/configs/socfpga_arria10_defconfig
+++ b/configs/socfpga_arria10_defconfig
@@ -4,6 +4,7 @@
CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
CONFIG_IDENT_STRING="socfpga_arria10"
CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_TEXT_BASE=0xFFE00000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPL_FIT=y
@@ -16,7 +17,6 @@
CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0xFFE00000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_FPGA_SUPPORT=y
CONFIG_CMD_ASKENV=y
@@ -46,3 +46,4 @@
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_DESIGNWARE_APB_TIMER=y
+# CONFIG_SPL_WDT is not set
diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index 3ab3cc4..9325467 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK=y
+CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
@@ -11,8 +12,8 @@
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DFU=y
@@ -64,3 +65,4 @@
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
+# CONFIG_SPL_WDT is not set
diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
index a309e5b..8e5b2e2 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y
+CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
@@ -11,8 +12,8 @@
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DFU=y
@@ -65,3 +66,4 @@
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
+# CONFIG_SPL_WDT is not set
diff --git a/configs/socfpga_dbm_soc1_defconfig b/configs/socfpga_dbm_soc1_defconfig
index dd14be4..c73f382 100644
--- a/configs/socfpga_dbm_soc1_defconfig
+++ b/configs/socfpga_dbm_soc1_defconfig
@@ -1,17 +1,20 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1=y
+CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_FIT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="run try_bootscript"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_ASKENV=y
@@ -59,3 +62,4 @@
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
+# CONFIG_SPL_WDT is not set
diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig
index ebaf247..80ccb33 100644
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ b/configs/socfpga_de0_nano_soc_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_TARGET_SOCFPGA_TERASIC_DE0_NANO=y
+CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
@@ -11,9 +12,9 @@
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0xFFFF0000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DFU=y
@@ -60,3 +61,4 @@
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
+# CONFIG_SPL_WDT is not set
diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig
index 0ac97c7..98e80b7 100644
--- a/configs/socfpga_de10_nano_defconfig
+++ b/configs/socfpga_de10_nano_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_TARGET_SOCFPGA_TERASIC_DE10_NANO=y
+CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
@@ -11,8 +12,8 @@
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DFU=y
@@ -56,3 +57,4 @@
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
+# CONFIG_SPL_WDT is not set
diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig
index cb52b6a..efa128a 100644
--- a/configs/socfpga_de1_soc_defconfig
+++ b/configs/socfpga_de1_soc_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_TARGET_SOCFPGA_TERASIC_DE1_SOC=y
+CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
@@ -11,7 +12,6 @@
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0xFFFF0000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_CMD_ASKENV=y
@@ -47,4 +47,5 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_DWC2=y
+# CONFIG_SPL_WDT is not set
# CONFIG_EFI_LOADER is not set
diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig
index f369301..99cdb26 100644
--- a/configs/socfpga_is1_defconfig
+++ b/configs/socfpga_is1_defconfig
@@ -2,6 +2,7 @@
CONFIG_ARCH_SOCFPGA=y
CONFIG_TARGET_SOCFPGA_IS1=y
CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
+CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_USE_BOOTARGS=y
@@ -13,8 +14,8 @@
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
# CONFIG_CMD_FLASH is not set
@@ -50,3 +51,4 @@
CONFIG_DM_RESET=y
CONFIG_SPI=y
CONFIG_CADENCE_QSPI=y
+# CONFIG_SPL_WDT is not set
diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig
index 7feedbe..e977cd7 100644
--- a/configs/socfpga_mcvevk_defconfig
+++ b/configs/socfpga_mcvevk_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_TARGET_SOCFPGA_ARIES_MCVEVK=y
+CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_USE_BOOTARGS=y
@@ -12,8 +13,8 @@
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DFU=y
@@ -57,3 +58,4 @@
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
+# CONFIG_SPL_WDT is not set
diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index dd03bc6..b570b9d 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_TARGET_SOCFPGA_TERASIC_SOCKIT=y
+CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
@@ -11,8 +12,8 @@
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DFU=y
@@ -65,3 +66,4 @@
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
+# CONFIG_SPL_WDT is not set
diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
index 9e93281..9eac00e 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_TARGET_SOCFPGA_EBV_SOCRATES=y
+CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
@@ -11,8 +12,8 @@
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DFU=y
@@ -67,3 +68,4 @@
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
+# CONFIG_SPL_WDT is not set
diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index 741525f..092347a 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -2,6 +2,7 @@
CONFIG_ARCH_SOCFPGA=y
CONFIG_TARGET_SOCFPGA_SR1500=y
CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
+CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
@@ -14,8 +15,8 @@
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
@@ -56,3 +57,4 @@
CONFIG_DM_RESET=y
CONFIG_SPI=y
CONFIG_CADENCE_QSPI=y
+# CONFIG_SPL_WDT is not set
diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
index fbab388..5ae53a4 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -6,9 +6,10 @@
CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
CONFIG_IDENT_STRING="socfpga_stratix10"
CONFIG_SPL_FS_FAT=y
-CONFIG_BOOTDELAY=5
CONFIG_SPL_TEXT_BASE=0xFFE00000
+CONFIG_BOOTDELAY=5
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x3C00000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # "
CONFIG_CMD_MEMTEST=y
diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig
index 958f146..c52afdd 100644
--- a/configs/socfpga_vining_fpga_defconfig
+++ b/configs/socfpga_vining_fpga_defconfig
@@ -1,12 +1,15 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_TARGET_SOCFPGA_SAMTEC_VINING_FPGA=y
+CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="setenv hostname vining-${unit_serial} ; setenv PS1 \"${unit_ident} (${unit_serial}) => \" ; if gpio input 78 ; then setenv bootdelay 10 ; setenv boottype rcvr ; else setenv bootdelay 5 ; setenv boottype norm ; fi"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
@@ -14,8 +17,8 @@
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0xFFFF0000
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
@@ -88,3 +91,4 @@
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
+# CONFIG_SPL_WDT is not set
diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig
index 2d5e158..58d135b 100644
--- a/configs/socrates_defconfig
+++ b/configs/socrates_defconfig
@@ -7,6 +7,8 @@
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=1
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="echo;echo Welcome on the ABB Socrates Board;echo"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_R=y
@@ -37,6 +39,7 @@
CONFIG_PHY_MARVELL=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_RTC_RX8025=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
# CONFIG_USB_EHCI_HCD is not set
diff --git a/configs/som-db5800-som-6867_defconfig b/configs/som-db5800-som-6867_defconfig
index fe1aa82..5d13e55 100644
--- a/configs/som-db5800-som-6867_defconfig
+++ b/configs/som-db5800-som-6867_defconfig
@@ -16,6 +16,7 @@
CONFIG_FIT_SIGNATURE=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
diff --git a/configs/sopine_baseboard_defconfig b/configs/sopine_baseboard_defconfig
index acd6dd6..5833234 100644
--- a/configs/sopine_baseboard_defconfig
+++ b/configs/sopine_baseboard_defconfig
@@ -11,7 +11,8 @@
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x10060
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/spear300_defconfig b/configs/spear300_defconfig
index 78da2a6..8e22c1e 100644
--- a/configs/spear300_defconfig
+++ b/configs/spear300_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_TARGET_SPEAR300=y
CONFIG_SYS_TEXT_BASE=0x00700000
CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/spear300_nand_defconfig b/configs/spear300_nand_defconfig
index 7ef97ce..154a5ca 100644
--- a/configs/spear300_nand_defconfig
+++ b/configs/spear300_nand_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_TARGET_SPEAR300=y
CONFIG_SYS_TEXT_BASE=0x00700000
CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/spear300_usbtty_defconfig b/configs/spear300_usbtty_defconfig
index 1b0034d..fbdd4a3 100644
--- a/configs/spear300_usbtty_defconfig
+++ b/configs/spear300_usbtty_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_TARGET_SPEAR300=y
CONFIG_SYS_TEXT_BASE=0x00700000
CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/spear300_usbtty_nand_defconfig b/configs/spear300_usbtty_nand_defconfig
index d37f6f4..77926c1 100644
--- a/configs/spear300_usbtty_nand_defconfig
+++ b/configs/spear300_usbtty_nand_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_TARGET_SPEAR300=y
CONFIG_SYS_TEXT_BASE=0x00700000
CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/spear310_defconfig b/configs/spear310_defconfig
index 615f995..423e1ff 100644
--- a/configs/spear310_defconfig
+++ b/configs/spear310_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_TARGET_SPEAR310=y
CONFIG_SYS_TEXT_BASE=0x00700000
CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/spear310_nand_defconfig b/configs/spear310_nand_defconfig
index 3c19898..29cf8f8 100644
--- a/configs/spear310_nand_defconfig
+++ b/configs/spear310_nand_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_TARGET_SPEAR310=y
CONFIG_SYS_TEXT_BASE=0x00700000
CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/spear310_pnor_defconfig b/configs/spear310_pnor_defconfig
index 8ec758e..dea51b9 100644
--- a/configs/spear310_pnor_defconfig
+++ b/configs/spear310_pnor_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_TARGET_SPEAR310=y
CONFIG_SYS_TEXT_BASE=0x00700000
CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/spear310_usbtty_defconfig b/configs/spear310_usbtty_defconfig
index fb23855..722c848 100644
--- a/configs/spear310_usbtty_defconfig
+++ b/configs/spear310_usbtty_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_TARGET_SPEAR310=y
CONFIG_SYS_TEXT_BASE=0x00700000
CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/spear310_usbtty_nand_defconfig b/configs/spear310_usbtty_nand_defconfig
index 33599e9..87baf30 100644
--- a/configs/spear310_usbtty_nand_defconfig
+++ b/configs/spear310_usbtty_nand_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_TARGET_SPEAR310=y
CONFIG_SYS_TEXT_BASE=0x00700000
CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/spear310_usbtty_pnor_defconfig b/configs/spear310_usbtty_pnor_defconfig
index 75cdfaf..7fd7dda 100644
--- a/configs/spear310_usbtty_pnor_defconfig
+++ b/configs/spear310_usbtty_pnor_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_TARGET_SPEAR310=y
CONFIG_SYS_TEXT_BASE=0x00700000
CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/spear320_defconfig b/configs/spear320_defconfig
index 07a2fc2..979bf04 100644
--- a/configs/spear320_defconfig
+++ b/configs/spear320_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_TARGET_SPEAR320=y
CONFIG_SYS_TEXT_BASE=0x00700000
CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/spear320_nand_defconfig b/configs/spear320_nand_defconfig
index b6b666c..86addcc 100644
--- a/configs/spear320_nand_defconfig
+++ b/configs/spear320_nand_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_TARGET_SPEAR320=y
CONFIG_SYS_TEXT_BASE=0x00700000
CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/spear320_pnor_defconfig b/configs/spear320_pnor_defconfig
index c5cc465..f7dd487 100644
--- a/configs/spear320_pnor_defconfig
+++ b/configs/spear320_pnor_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_TARGET_SPEAR320=y
CONFIG_SYS_TEXT_BASE=0x00700000
CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/spear320_usbtty_defconfig b/configs/spear320_usbtty_defconfig
index 0d0001e..9fab406 100644
--- a/configs/spear320_usbtty_defconfig
+++ b/configs/spear320_usbtty_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_TARGET_SPEAR320=y
CONFIG_SYS_TEXT_BASE=0x00700000
CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/spear320_usbtty_nand_defconfig b/configs/spear320_usbtty_nand_defconfig
index c16de53..694c51b 100644
--- a/configs/spear320_usbtty_nand_defconfig
+++ b/configs/spear320_usbtty_nand_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_TARGET_SPEAR320=y
CONFIG_SYS_TEXT_BASE=0x00700000
CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/spear320_usbtty_pnor_defconfig b/configs/spear320_usbtty_pnor_defconfig
index b033a50..1dfac11 100644
--- a/configs/spear320_usbtty_pnor_defconfig
+++ b/configs/spear320_usbtty_pnor_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_TARGET_SPEAR320=y
CONFIG_SYS_TEXT_BASE=0x00700000
CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/spear600_defconfig b/configs/spear600_defconfig
index b9a4c66..eeb2746 100644
--- a/configs/spear600_defconfig
+++ b/configs/spear600_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_TARGET_SPEAR600=y
CONFIG_SYS_TEXT_BASE=0x00700000
CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/spear600_nand_defconfig b/configs/spear600_nand_defconfig
index a489270..978204e 100644
--- a/configs/spear600_nand_defconfig
+++ b/configs/spear600_nand_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_TARGET_SPEAR600=y
CONFIG_SYS_TEXT_BASE=0x00700000
CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/spear600_usbtty_defconfig b/configs/spear600_usbtty_defconfig
index 5618505..2e6f3f1 100644
--- a/configs/spear600_usbtty_defconfig
+++ b/configs/spear600_usbtty_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_TARGET_SPEAR600=y
CONFIG_SYS_TEXT_BASE=0x00700000
CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/spear600_usbtty_nand_defconfig b/configs/spear600_usbtty_nand_defconfig
index 5add352..cc490f0 100644
--- a/configs/spear600_usbtty_nand_defconfig
+++ b/configs/spear600_usbtty_nand_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_TARGET_SPEAR600=y
CONFIG_SYS_TEXT_BASE=0x00700000
CONFIG_NR_DRAM_BANKS=1
diff --git a/configs/spring_defconfig b/configs/spring_defconfig
index bfc7495..5d8b629 100644
--- a/configs/spring_defconfig
+++ b/configs/spring_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_EXYNOS=y
@@ -11,12 +12,12 @@
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_IDENT_STRING=" for spring"
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0x02023400
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SILENT_CONSOLE=y
# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_TEXT_BASE=0x02023400
CONFIG_SYS_PROMPT="spring # "
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig
index 5fa892f..3c43d2a 100644
--- a/configs/stm32f746-disco_defconfig
+++ b/configs/stm32f746-disco_defconfig
@@ -5,6 +5,7 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_STM32F7=y
CONFIG_TARGET_STM32F746_DISCO=y
+CONFIG_SPL_TEXT_BASE=0x8000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
@@ -13,7 +14,6 @@
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x8000000
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
diff --git a/configs/stm32h743-disco_defconfig b/configs/stm32h743-disco_defconfig
index 1691c2e..1053dbc 100644
--- a/configs/stm32h743-disco_defconfig
+++ b/configs/stm32h743-disco_defconfig
@@ -27,6 +27,5 @@
CONFIG_DM_MMC=y
CONFIG_STM32_SDMMC2=y
# CONFIG_PINCTRL_FULL is not set
-# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_OF_LIBFDT_OVERLAY=y
# CONFIG_EFI_LOADER is not set
diff --git a/configs/stm32h743-eval_defconfig b/configs/stm32h743-eval_defconfig
index e1c6cbf..4d88ed3 100644
--- a/configs/stm32h743-eval_defconfig
+++ b/configs/stm32h743-eval_defconfig
@@ -27,6 +27,5 @@
CONFIG_DM_MMC=y
CONFIG_STM32_SDMMC2=y
# CONFIG_PINCTRL_FULL is not set
-# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_OF_LIBFDT_OVERLAY=y
# CONFIG_EFI_LOADER is not set
diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig
index 4aa184f..f6c68fe 100644
--- a/configs/stm32mp15_basic_defconfig
+++ b/configs/stm32mp15_basic_defconfig
@@ -4,14 +4,19 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL=y
CONFIG_TARGET_STM32MP1=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+# CONFIG_ARMV7_VIRT is not set
+CONFIG_SPL_TEXT_BASE=0x2FFC2500
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
-CONFIG_SPL_TEXT_BASE=0x2FFC2500
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3
CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
CONFIG_SYS_PROMPT="STM32MP> "
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_ELF is not set
@@ -29,10 +34,12 @@
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_REMOTEPROC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
@@ -43,6 +50,7 @@
CONFIG_CMD_UBI=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1"
+CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks"
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_EXT4=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
@@ -52,6 +60,7 @@
CONFIG_ENV_EXT4_FILE="/uboot.env"
CONFIG_ENV_UBI_PART="UBI"
CONFIG_ENV_UBI_VOLUME="uboot_config"
+CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r"
CONFIG_STM32_ADC=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0xC0000000
@@ -65,6 +74,8 @@
CONFIG_SYS_I2C_STM32F7=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
+CONFIG_DM_MAILBOX=y
+CONFIG_STM32_IPCC=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_STM32_SDMMC2=y
@@ -73,7 +84,6 @@
CONFIG_NAND_STM32_FMC2=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
@@ -94,8 +104,10 @@
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_REGULATOR_STM32_VREFBUF=y
CONFIG_DM_REGULATOR_STPMIC1=y
+CONFIG_REMOTEPROC_STM32_COPRO=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_STM32=y
CONFIG_SERIAL_RX_BUFFER=y
-CONFIG_STM32_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_STM32_QSPI=y
@@ -110,5 +122,6 @@
CONFIG_USB_GADGET_VENDOR_NUM=0x0483
CONFIG_USB_GADGET_PRODUCT_NUM=0x5720
CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_WDT=y
-CONFIG_WDT_STM32MP=y
+CONFIG_DM_VIDEO=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/stm32mp15_optee_defconfig b/configs/stm32mp15_optee_defconfig
new file mode 100644
index 0000000..177cbc7
--- /dev/null
+++ b/configs/stm32mp15_optee_defconfig
@@ -0,0 +1,112 @@
+CONFIG_ARM=y
+CONFIG_ARCH_STM32MP=y
+CONFIG_SYS_MALLOC_F_LEN=0x3000
+CONFIG_TARGET_STM32MP1=y
+CONFIG_STM32MP1_OPTEE=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
+CONFIG_SYS_PROMPT="STM32MP> "
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_ADC=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_REMOTEPROC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_UBI=y
+CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1"
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_EXT4=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_IS_IN_UBI=y
+CONFIG_ENV_EXT4_INTERFACE="mmc"
+CONFIG_ENV_EXT4_DEVICE_AND_PART="0:auto"
+CONFIG_ENV_EXT4_FILE="/uboot.env"
+CONFIG_ENV_UBI_PART="UBI"
+CONFIG_ENV_UBI_VOLUME="uboot_config"
+CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r"
+CONFIG_STM32_ADC=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0xC0000000
+CONFIG_FASTBOOT_BUF_SIZE=0x02000000
+CONFIG_FASTBOOT_USB_DEV=1
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_DM_HWSPINLOCK=y
+CONFIG_HWSPINLOCK_STM32=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_STM32F7=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_DM_MAILBOX=y
+CONFIG_STM32_IPCC=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_STM32_SDMMC2=y
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_STM32_FMC2=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_DM_ETH=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_PHY=y
+CONFIG_PHY_STM32_USBPHYC=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_STMFX=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_STPMIC1=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_REGULATOR_STM32_VREFBUF=y
+CONFIG_DM_REGULATOR_STPMIC1=y
+CONFIG_REMOTEPROC_STM32_COPRO=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_STM32=y
+CONFIG_SERIAL_RX_BUFFER=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_STM32_QSPI=y
+CONFIG_STM32_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0483
+CONFIG_USB_GADGET_PRODUCT_NUM=0x5720
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_DM_VIDEO=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig
index 5fe9477..71ad115 100644
--- a/configs/stm32mp15_trusted_defconfig
+++ b/configs/stm32mp15_trusted_defconfig
@@ -22,10 +22,12 @@
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_REMOTEPROC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
@@ -44,6 +46,7 @@
CONFIG_ENV_EXT4_FILE="/uboot.env"
CONFIG_ENV_UBI_PART="UBI"
CONFIG_ENV_UBI_VOLUME="uboot_config"
+CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r"
CONFIG_STM32_ADC=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0xC0000000
@@ -57,6 +60,8 @@
CONFIG_SYS_I2C_STM32F7=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
+CONFIG_DM_MAILBOX=y
+CONFIG_STM32_IPCC=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_STM32_SDMMC2=y
@@ -65,7 +70,6 @@
CONFIG_NAND_STM32_FMC2=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
@@ -84,8 +88,10 @@
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_REGULATOR_STM32_VREFBUF=y
CONFIG_DM_REGULATOR_STPMIC1=y
+CONFIG_REMOTEPROC_STM32_COPRO=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_STM32=y
CONFIG_SERIAL_RX_BUFFER=y
-CONFIG_STM32_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_STM32_QSPI=y
@@ -100,5 +106,6 @@
CONFIG_USB_GADGET_VENDOR_NUM=0x0483
CONFIG_USB_GADGET_PRODUCT_NUM=0x5720
CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_WDT=y
-CONFIG_WDT_STM32MP=y
+CONFIG_DM_VIDEO=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/stout_defconfig b/configs/stout_defconfig
index d6d9e69..f32c005 100644
--- a/configs/stout_defconfig
+++ b/configs/stout_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
@@ -16,15 +17,16 @@
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0xe6300000
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_TEXT_BASE=0xe6300000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig
index 1bdbe9e..6a561d0 100644
--- a/configs/strider_con_defconfig
+++ b/configs/strider_con_defconfig
@@ -95,6 +95,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CON"
CONFIG_BOOTDELAY=5
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig
index 424c915..eb4ad77 100644
--- a/configs/strider_con_dp_defconfig
+++ b/configs/strider_con_dp_defconfig
@@ -95,6 +95,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CON_DP"
CONFIG_BOOTDELAY=5
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig
index 1149b13..8a48df2 100644
--- a/configs/strider_cpu_defconfig
+++ b/configs/strider_cpu_defconfig
@@ -95,6 +95,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CPU"
CONFIG_BOOTDELAY=5
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig
index ec68d3d..26793db 100644
--- a/configs/strider_cpu_dp_defconfig
+++ b/configs/strider_cpu_dp_defconfig
@@ -95,6 +95,7 @@
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CPU,STRIDER_CPU_DP"
CONFIG_BOOTDELAY=5
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/sun8i_a23_evb_defconfig b/configs/sun8i_a23_evb_defconfig
index ef1bd21..34cbb1e 100644
--- a/configs/sun8i_a23_evb_defconfig
+++ b/configs/sun8i_a23_evb_defconfig
@@ -9,7 +9,7 @@
CONFIG_USB0_VBUS_DET="axp_vbus_detect"
CONFIG_USB1_VBUS_PIN="PH7"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/sunxi_Gemei_G9_defconfig b/configs/sunxi_Gemei_G9_defconfig
index 4bd6099..f3d77f1 100644
--- a/configs/sunxi_Gemei_G9_defconfig
+++ b/configs/sunxi_Gemei_G9_defconfig
@@ -11,7 +11,7 @@
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig
index 075045b..8b72983 100644
--- a/configs/syzygy_hub_defconfig
+++ b/configs/syzygy_hub_defconfig
@@ -15,7 +15,8 @@
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="Zynq> "
diff --git a/configs/tao3530_defconfig b/configs/tao3530_defconfig
index f752e92..ab3590c 100644
--- a/configs/tao3530_defconfig
+++ b/configs/tao3530_defconfig
@@ -5,8 +5,8 @@
CONFIG_TARGET_TAO3530=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
-CONFIG_BOOTDELAY=3
CONFIG_SPL_TEXT_BASE=0x40200800
+CONFIG_BOOTDELAY=3
# CONFIG_SPL_FS_EXT4 is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="TAO-3530 # "
diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig
index ee21811..3676ecd 100644
--- a/configs/taurus_defconfig
+++ b/configs/taurus_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_SPL_SYS_ICACHE_OFF=y
CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_SYS_THUMB_BUILD=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
@@ -13,6 +14,7 @@
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_OFFSET=0x100000
CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
@@ -21,7 +23,6 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x1000
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2067"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
@@ -32,7 +33,6 @@
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-# CONFIG_TPL_BANNER_PRINT is not set
CONFIG_SPL_CRC32_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
@@ -66,6 +66,7 @@
CONFIG_DFU_NAND=y
# CONFIG_MMC is not set
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
@@ -87,6 +88,5 @@
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_WDT=y
CONFIG_WDT_AT91=y
-CONFIG_USE_TINY_PRINTF=y
CONFIG_HEXDUMP=y
# CONFIG_EFI_LOADER is not set
diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig
index ba42603..3148a32 100644
--- a/configs/tbs2910_defconfig
+++ b/configs/tbs2910_defconfig
@@ -4,11 +4,13 @@
CONFIG_SYS_TEXT_BASE=0x17800000
CONFIG_TARGET_TBS2910=y
CONFIG_NR_DRAM_BANKS=1
+CONFIG_PRE_CON_BUF_ADDR=0x7c000000
CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="usb start; if hdmidet; then run set_con_hdmi; else run set_con_serial; fi"
CONFIG_PRE_CONSOLE_BUFFER=y
-CONFIG_PRE_CON_BUF_ADDR=0x7c000000
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
@@ -48,7 +50,7 @@
CONFIG_SYS_I2C_MXC=y
CONFIG_DM_KEYBOARD=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_PCI=y
diff --git a/configs/tbs_a711_defconfig b/configs/tbs_a711_defconfig
index 5d6ffab..196c4ce 100644
--- a/configs/tbs_a711_defconfig
+++ b/configs/tbs_a711_defconfig
@@ -13,7 +13,7 @@
CONFIG_USB0_ID_DET="PH11"
CONFIG_AXP_GPIO=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_TEXT_BASE=0x60
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/tec-ng_defconfig b/configs/tec-ng_defconfig
index 513e301..7727e75 100644
--- a/configs/tec-ng_defconfig
+++ b/configs/tec-ng_defconfig
@@ -4,11 +4,11 @@
CONFIG_NR_DRAM_BANKS=2
CONFIG_TEGRA30=y
CONFIG_TARGET_TEC_NG=y
+CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_FIT=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
-CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_SYS_PROMPT="Tegra30 (TEC-NG) # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/tec_defconfig b/configs/tec_defconfig
index ab92b84..45902ff 100644
--- a/configs/tec_defconfig
+++ b/configs/tec_defconfig
@@ -4,10 +4,10 @@
CONFIG_NR_DRAM_BANKS=2
CONFIG_TEGRA20=y
CONFIG_TARGET_TEC=y
+CONFIG_SPL_TEXT_BASE=0x00108000
CONFIG_FIT=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_SYS_STDIO_DEREGISTER=y
-CONFIG_SPL_TEXT_BASE=0x00108000
CONFIG_SYS_PROMPT="Tegra20 (TEC) # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/teres_i_defconfig b/configs/teres_i_defconfig
index 1b57a48..cfd696f 100644
--- a/configs/teres_i_defconfig
+++ b/configs/teres_i_defconfig
@@ -7,7 +7,7 @@
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB1_VBUS_PIN="PL7"
CONFIG_I2C0_ENABLE=y
-CONFIG_SPL_TEXT_BASE=0x10060
+CONFIG_USE_PREBOOT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig
index 2653f71..770804f 100644
--- a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig
+++ b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig
@@ -17,6 +17,8 @@
CONFIG_FIT_SIGNATURE=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SHOW_BOOT_PROGRESS=y
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
diff --git a/configs/theadorable-x86-conga-qa3-e3845_defconfig b/configs/theadorable-x86-conga-qa3-e3845_defconfig
index ee9189a..d69c2a9 100644
--- a/configs/theadorable-x86-conga-qa3-e3845_defconfig
+++ b/configs/theadorable-x86-conga-qa3-e3845_defconfig
@@ -16,6 +16,8 @@
CONFIG_FIT_SIGNATURE=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SHOW_BOOT_PROGRESS=y
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
diff --git a/configs/theadorable-x86-dfi-bt700_defconfig b/configs/theadorable-x86-dfi-bt700_defconfig
index 7da1bea..d53aff0 100644
--- a/configs/theadorable-x86-dfi-bt700_defconfig
+++ b/configs/theadorable-x86-dfi-bt700_defconfig
@@ -15,6 +15,8 @@
CONFIG_FIT_SIGNATURE=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SHOW_BOOT_PROGRESS=y
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
diff --git a/configs/theadorable_debug_defconfig b/configs/theadorable_debug_defconfig
index 50f9df0..34b740c 100644
--- a/configs/theadorable_debug_defconfig
+++ b/configs/theadorable_debug_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -13,16 +14,18 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0x40004030
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0x40004030
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x1a000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig
index 67012f8..ade82c8 100644
--- a/configs/thuban_defconfig
+++ b/configs/thuban_defconfig
@@ -10,6 +10,7 @@
CONFIG_TARGET_THUBAN=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_SPL_FS_FAT=y
@@ -18,11 +19,13 @@
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
diff --git a/configs/ti814x_evm_defconfig b/configs/ti814x_evm_defconfig
index e171ff8..9a06985 100644
--- a/configs/ti814x_evm_defconfig
+++ b/configs/ti814x_evm_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -11,6 +12,7 @@
CONFIG_SPL=y
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0x40300000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
@@ -18,7 +20,6 @@
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_TEXT_BASE=0x40300000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_YMODEM_SUPPORT=y
diff --git a/configs/ti816x_evm_defconfig b/configs/ti816x_evm_defconfig
index bf877f5..2a817ed 100644
--- a/configs/ti816x_evm_defconfig
+++ b/configs/ti816x_evm_defconfig
@@ -7,9 +7,12 @@
CONFIG_TARGET_TI816X_EVM=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x001c0000
CONFIG_SPL=y
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0x40400000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
@@ -19,7 +22,6 @@
# CONFIG_MISC_INIT_R is not set
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_TEXT_BASE=0x40400000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_NAND_SUPPORT=y
@@ -45,6 +47,7 @@
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
+CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_DRIVER_TI_EMAC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig
index 482ee7d..9328608 100644
--- a/configs/tinker-rk3288_defconfig
+++ b/configs/tinker-rk3288_defconfig
@@ -1,22 +1,26 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x01000000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_ROCKCHIP_RK3288=y
-CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl.lds"
CONFIG_TARGET_TINKER_RK3288=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL_SIZE_LIMIT=307200
+CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
CONFIG_DEFAULT_FDT_FILE="rk3288-tinker.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
@@ -24,6 +28,7 @@
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
@@ -61,7 +66,9 @@
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
@@ -76,10 +83,8 @@
CONFIG_USB_GADGET_VENDOR_NUM=0x2207
CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USB_FUNCTION_MASS_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
diff --git a/configs/titanium_defconfig b/configs/titanium_defconfig
index 1e19240..86d1da3 100644
--- a/configs/titanium_defconfig
+++ b/configs/titanium_defconfig
@@ -34,7 +34,7 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:16M(uboot),512k(env1),512k(env2),-(ubi)"
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_NAND=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_PHYLIB=y
diff --git a/configs/tools-only_defconfig b/configs/tools-only_defconfig
index aa73661..4808b49 100644
--- a/configs/tools-only_defconfig
+++ b/configs/tools-only_defconfig
@@ -12,7 +12,6 @@
CONFIG_IP_DEFRAG=y
# CONFIG_UDP_FUNCTION_FASTBOOT is not set
CONFIG_SANDBOX_GPIO=y
-CONFIG_DM_I2C_COMPAT=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_PCI_SANDBOX=y
diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig
index 6b126c5..ddd43fa 100644
--- a/configs/topic_miami_defconfig
+++ b/configs/topic_miami_defconfig
@@ -14,8 +14,10 @@
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
CONFIG_BOOTDELAY=0
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_SYS_PROMPT="zynq-uboot> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_MEMTEST=y
diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig
index a0b016c..17cc15d 100644
--- a/configs/topic_miamilite_defconfig
+++ b/configs/topic_miamilite_defconfig
@@ -14,8 +14,10 @@
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
CONFIG_BOOTDELAY=0
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_SYS_PROMPT="zynq-uboot> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_MEMTEST=y
diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig
index c34b034..3d0699d 100644
--- a/configs/topic_miamiplus_defconfig
+++ b/configs/topic_miamiplus_defconfig
@@ -14,8 +14,10 @@
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
CONFIG_BOOTDELAY=0
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_SYS_PROMPT="zynq-uboot> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_MEMTEST=y
diff --git a/configs/tqma6dl_mba6_mmc_defconfig b/configs/tqma6dl_mba6_mmc_defconfig
index bc54005..4f2d414 100644
--- a/configs/tqma6dl_mba6_mmc_defconfig
+++ b/configs/tqma6dl_mba6_mmc_defconfig
@@ -32,7 +32,7 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
diff --git a/configs/tqma6dl_mba6_spi_defconfig b/configs/tqma6dl_mba6_spi_defconfig
index 58d08bf..9ad9ea3 100644
--- a/configs/tqma6dl_mba6_spi_defconfig
+++ b/configs/tqma6dl_mba6_spi_defconfig
@@ -33,7 +33,7 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
diff --git a/configs/tqma6q_mba6_mmc_defconfig b/configs/tqma6q_mba6_mmc_defconfig
index b57cb81..36b4b3c 100644
--- a/configs/tqma6q_mba6_mmc_defconfig
+++ b/configs/tqma6q_mba6_mmc_defconfig
@@ -31,7 +31,7 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
diff --git a/configs/tqma6q_mba6_spi_defconfig b/configs/tqma6q_mba6_spi_defconfig
index c713fac..21bc3fa 100644
--- a/configs/tqma6q_mba6_spi_defconfig
+++ b/configs/tqma6q_mba6_spi_defconfig
@@ -32,7 +32,7 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
diff --git a/configs/tqma6s_mba6_mmc_defconfig b/configs/tqma6s_mba6_mmc_defconfig
index d9d3ce9..0a8cc6d 100644
--- a/configs/tqma6s_mba6_mmc_defconfig
+++ b/configs/tqma6s_mba6_mmc_defconfig
@@ -32,7 +32,7 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
diff --git a/configs/tqma6s_mba6_spi_defconfig b/configs/tqma6s_mba6_spi_defconfig
index f793658..e02b8a5 100644
--- a/configs/tqma6s_mba6_spi_defconfig
+++ b/configs/tqma6s_mba6_spi_defconfig
@@ -33,7 +33,7 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
diff --git a/configs/tqma6s_wru4_mmc_defconfig b/configs/tqma6s_wru4_mmc_defconfig
index 57f2221..03e8930 100644
--- a/configs/tqma6s_wru4_mmc_defconfig
+++ b/configs/tqma6s_wru4_mmc_defconfig
@@ -59,7 +59,7 @@
CONFIG_LED_STATUS_STATE5=2
CONFIG_LED_STATUS_CMD=y
CONFIG_PCA9551_LED=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_USB=y
diff --git a/configs/trats2_defconfig b/configs/trats2_defconfig
index 7907849..8607594 100644
--- a/configs/trats2_defconfig
+++ b/configs/trats2_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x43e00000
CONFIG_ARCH_EXYNOS4=y
diff --git a/configs/trats_defconfig b/configs/trats_defconfig
index b289b82..c8f1e29 100644
--- a/configs/trats_defconfig
+++ b/configs/trats_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x63300000
CONFIG_ARCH_EXYNOS4=y
diff --git a/configs/tricorder_defconfig b/configs/tricorder_defconfig
index 973c5ac..730fd7f 100644
--- a/configs/tricorder_defconfig
+++ b/configs/tricorder_defconfig
@@ -2,11 +2,13 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80100000
CONFIG_TARGET_TRICORDER=y
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x120000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_BOOTDELAY=0
CONFIG_SILENT_CONSOLE=y
-CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="OMAP3 Tricorder # "
# CONFIG_CMD_IMI is not set
diff --git a/configs/tricorder_flash_defconfig b/configs/tricorder_flash_defconfig
index 1dc2992..3a7061e 100644
--- a/configs/tricorder_flash_defconfig
+++ b/configs/tricorder_flash_defconfig
@@ -2,12 +2,13 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80100000
CONFIG_TARGET_TRICORDER=y
+CONFIG_ENV_SIZE=0x4000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_SYS_EXTRA_OPTIONS="FLASHCARD"
CONFIG_BOOTDELAY=0
CONFIG_SILENT_CONSOLE=y
-CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMI is not set
CONFIG_CMD_EEPROM=y
diff --git a/configs/trimslice_defconfig b/configs/trimslice_defconfig
index d8ce65f..7ebdec4 100644
--- a/configs/trimslice_defconfig
+++ b/configs/trimslice_defconfig
@@ -4,10 +4,10 @@
CONFIG_NR_DRAM_BANKS=2
CONFIG_TEGRA20=y
CONFIG_TARGET_TRIMSLICE=y
+CONFIG_SPL_TEXT_BASE=0x00108000
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
-CONFIG_SPL_TEXT_BASE=0x00108000
CONFIG_SYS_PROMPT="Tegra20 (TrimSlice) # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/ts4600_defconfig b/configs/ts4600_defconfig
index d5816f7..3c9395c 100644
--- a/configs/ts4600_defconfig
+++ b/configs/ts4600_defconfig
@@ -6,13 +6,13 @@
CONFIG_TARGET_TS4600=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x00001000
CONFIG_FIT=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_TEXT_BASE=0x00001000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
@@ -22,6 +22,7 @@
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_MXS_GPIO=y
CONFIG_MMC_MXS=y
CONFIG_CONS_INDEX=0
CONFIG_OF_LIBFDT=y
diff --git a/configs/ts4800_defconfig b/configs/ts4800_defconfig
index 68404e3..208366e 100644
--- a/configs/ts4800_defconfig
+++ b/configs/ts4800_defconfig
@@ -15,7 +15,7 @@
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_SPI=y
diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig
index d26cb3c..25c4fc1 100644
--- a/configs/turris_mox_defconfig
+++ b/configs/turris_mox_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
@@ -9,6 +10,7 @@
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
@@ -63,7 +65,6 @@
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_RTC=y
CONFIG_RTC_DS1307=y
-# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DEBUG_MVEBU_A3700_UART=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_ANNOUNCE=y
diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig
index e041563..a8619d4 100644
--- a/configs/turris_omnia_defconfig
+++ b/configs/turris_omnia_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_SPL_SYS_THUMB_BUILD=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
@@ -16,17 +17,21 @@
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0x40000030
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0x40000030
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x24000
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_SHA1SUM=y
CONFIG_CMD_LZMADEC=y
# CONFIG_CMD_FLASH is not set
@@ -59,6 +64,7 @@
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_MV=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
diff --git a/configs/uDPU_defconfig b/configs/uDPU_defconfig
index 2209330..ec0b731 100644
--- a/configs/uDPU_defconfig
+++ b/configs/uDPU_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
@@ -12,6 +13,7 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_FIT=y
CONFIG_SPI_BOOT=y
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
@@ -76,7 +78,6 @@
CONFIG_PINCTRL_ARMADA_37XX=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
-# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DEBUG_MVEBU_A3700_UART=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_ANNOUNCE=y
diff --git a/configs/udoo_defconfig b/configs/udoo_defconfig
index 317592b..6387d33 100644
--- a/configs/udoo_defconfig
+++ b/configs/udoo_defconfig
@@ -10,13 +10,13 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
@@ -29,7 +29,7 @@
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
CONFIG_DWC_AHSATA=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig
index e8df11d..11fd5b1 100644
--- a/configs/udoo_neo_defconfig
+++ b/configs/udoo_neo_defconfig
@@ -11,12 +11,12 @@
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_CMD_BMODE is not set
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
@@ -28,7 +28,7 @@
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig
index 2cc30e0..7a1010d 100644
--- a/configs/uniphier_ld4_sld8_defconfig
+++ b/configs/uniphier_ld4_sld8_defconfig
@@ -8,12 +8,12 @@
CONFIG_SPL=y
CONFIG_ARCH_UNIPHIER_LD4_SLD8=y
CONFIG_MICRO_SUPPORT_CARD=y
+CONFIG_SPL_TEXT_BASE=0x00040000
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="env exist ${bootdev}preboot && run ${bootdev}preboot"
CONFIG_LOGLEVEL=6
-CONFIG_SPL_TEXT_BASE=0x00040000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_CMD_CONFIG=y
diff --git a/configs/uniphier_v7_defconfig b/configs/uniphier_v7_defconfig
index 61007a6..9224201 100644
--- a/configs/uniphier_v7_defconfig
+++ b/configs/uniphier_v7_defconfig
@@ -7,12 +7,12 @@
CONFIG_NR_DRAM_BANKS=3
CONFIG_SPL=y
CONFIG_MICRO_SUPPORT_CARD=y
+CONFIG_SPL_TEXT_BASE=0x00100000
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="env exist ${bootdev}preboot && run ${bootdev}preboot"
CONFIG_LOGLEVEL=6
-CONFIG_SPL_TEXT_BASE=0x00100000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_CMD_CONFIG=y
diff --git a/configs/uniphier_v8_defconfig b/configs/uniphier_v8_defconfig
index 83f7877..3908ff8 100644
--- a/configs/uniphier_v8_defconfig
+++ b/configs/uniphier_v8_defconfig
@@ -1,7 +1,9 @@
CONFIG_ARM=y
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_INIT_SP_RELATIVE=y
CONFIG_ARM_SMCCC=y
CONFIG_ARCH_UNIPHIER=y
-CONFIG_SYS_TEXT_BASE=0x84000000
+CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=3
CONFIG_ARCH_UNIPHIER_V8_MULTI=y
diff --git a/configs/usb_a9263_dataflash_defconfig b/configs/usb_a9263_dataflash_defconfig
index 3b9e4a5..5779aeb 100644
--- a/configs/usb_a9263_dataflash_defconfig
+++ b/configs/usb_a9263_dataflash_defconfig
@@ -1,9 +1,13 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x23f00000
CONFIG_TARGET_USB_A9263=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x2000
CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SECT_SIZE=0x2000
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
@@ -34,6 +38,7 @@
CONFIG_AT91_GPIO=y
# CONFIG_MMC is not set
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
diff --git a/configs/usbarmory_defconfig b/configs/usbarmory_defconfig
index 3c1eaf6..77a3a23 100644
--- a/configs/usbarmory_defconfig
+++ b/configs/usbarmory_defconfig
@@ -13,7 +13,7 @@
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_USB=y
CONFIG_USB_EHCI_MX5=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/variscite_dart6ul_defconfig b/configs/variscite_dart6ul_defconfig
index f55c386..cb1b17c 100644
--- a/configs/variscite_dart6ul_defconfig
+++ b/configs/variscite_dart6ul_defconfig
@@ -30,7 +30,7 @@
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-dart-6ul"
CONFIG_DM_I2C_GPIO=y
CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_FEC_MXC=y
diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig
index 7f7befb..ae0f4cb 100644
--- a/configs/venice2_defconfig
+++ b/configs/venice2_defconfig
@@ -4,10 +4,10 @@
CONFIG_NR_DRAM_BANKS=2
CONFIG_TEGRA124=y
CONFIG_TARGET_VENICE2=y
+CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
-CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_SYS_PROMPT="Tegra124 (Venice2) # "
# CONFIG_CMD_IMI is not set
CONFIG_CMD_DFU=y
diff --git a/configs/ventana_defconfig b/configs/ventana_defconfig
index c33862c..3197004 100644
--- a/configs/ventana_defconfig
+++ b/configs/ventana_defconfig
@@ -4,8 +4,10 @@
CONFIG_NR_DRAM_BANKS=2
CONFIG_TEGRA20=y
CONFIG_TARGET_VENTANA=y
-CONFIG_OF_SYSTEM_SETUP=y
CONFIG_SPL_TEXT_BASE=0x00108000
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="usb start"
CONFIG_SYS_PROMPT="Tegra20 (Ventana) # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/vexpress_aemv8a_dram_defconfig b/configs/vexpress_aemv8a_dram_defconfig
deleted file mode 100644
index 2ff9e4b..0000000
--- a/configs/vexpress_aemv8a_dram_defconfig
+++ /dev/null
@@ -1,39 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM=y
-CONFIG_SYS_TEXT_BASE=0x88000000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_IDENT_STRING=" vexpress_aemv8a"
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTDELAY=1
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyAMA0 earlyprintk=pl011,0x1c090000 debug user_debug=31 androidboot.hardware=fvpbase root=/dev/vda2 rw rootwait loglevel=9"
-# CONFIG_USE_BOOTCOMMAND is not set
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SYS_PROMPT="VExpress64# "
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_ARMFLASH=y
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_CACHE=y
-# CONFIG_CMD_MISC is not set
-CONFIG_CMD_UBI=y
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_DM=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_MTD_DEVICE=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_DM_SERIAL=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig
index fd306f9..0823d17 100644
--- a/configs/vexpress_aemv8a_juno_defconfig
+++ b/configs/vexpress_aemv8a_juno_defconfig
@@ -7,7 +7,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyAMA0,115200n8 root=/dev/sda2 rw rootwait earlyprintk=pl011,0x7ff80000 debug user_debug=31 androidboot.hardware=juno loglevel=9"
+CONFIG_BOOTARGS="console=ttyAMA0,115200n8 root=/dev/sda2 rw rootwait earlycon=pl011,0x7ff80000 debug user_debug=31 androidboot.hardware=juno loglevel=9"
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/vexpress_aemv8a_semi_defconfig b/configs/vexpress_aemv8a_semi_defconfig
index bff52f7..db5ad3d 100644
--- a/configs/vexpress_aemv8a_semi_defconfig
+++ b/configs/vexpress_aemv8a_semi_defconfig
@@ -7,7 +7,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyAMA0 earlyprintk=pl011,0x1c090000 debug user_debug=31 loglevel=9"
+CONFIG_BOOTARGS="console=ttyAMA0 earlycon=pl011,0x1c090000 debug user_debug=31 loglevel=9"
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/vf610twr_defconfig b/configs/vf610twr_defconfig
index dc67ddc..f3e55b8 100644
--- a/configs/vf610twr_defconfig
+++ b/configs/vf610twr_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_SYS_THUMB_BUILD=y
-# CONFIG_SPL_SYS_THUMB_BUILD is not set
CONFIG_ARCH_VF610=y
CONFIG_SYS_TEXT_BASE=0x3f401000
CONFIG_NR_DRAM_BANKS=1
@@ -32,7 +31,7 @@
CONFIG_DM=y
CONFIG_DM_GPIO=y
CONFIG_VYBRID_GPIO=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_NAND_VF610_NFC=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_PHYLIB=y
diff --git a/configs/vf610twr_nand_defconfig b/configs/vf610twr_nand_defconfig
index 7fcb630..64b108d 100644
--- a/configs/vf610twr_nand_defconfig
+++ b/configs/vf610twr_nand_defconfig
@@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_SYS_THUMB_BUILD=y
-# CONFIG_SPL_SYS_THUMB_BUILD is not set
CONFIG_ARCH_VF610=y
CONFIG_SYS_TEXT_BASE=0x3f401000
CONFIG_NR_DRAM_BANKS=1
@@ -32,7 +31,7 @@
CONFIG_DM=y
CONFIG_DM_GPIO=y
CONFIG_VYBRID_GPIO=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_NAND_VF610_NFC=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_PHYLIB=y
diff --git a/configs/vinco_defconfig b/configs/vinco_defconfig
index 745aa85..4ab62e7 100644
--- a/configs/vinco_defconfig
+++ b/configs/vinco_defconfig
@@ -1,8 +1,12 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x20f00000
CONFIG_TARGET_VINCO=y
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x10000
CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig
index 9e8326e..b007a76 100644
--- a/configs/vining_2000_defconfig
+++ b/configs/vining_2000_defconfig
@@ -3,10 +3,8 @@
CONFIG_SYS_TEXT_BASE=0x87800000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_TARGET_SOFTING_VINING_2000=y
-CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
CONFIG_NR_DRAM_BANKS=1
# CONFIG_CMD_BMODE is not set
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x400
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/softing/vining_2000/imximage.cfg"
CONFIG_BOOTDELAY=0
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
@@ -42,13 +40,14 @@
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
+CONFIG_PWM_IMX=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig
index 77c7904..f6b9eb6 100644
--- a/configs/vme8349_defconfig
+++ b/configs/vme8349_defconfig
@@ -114,6 +114,7 @@
CONFIG_SYS_FLASH_CFI=y
CONFIG_PHY_MARVELL=y
CONFIG_TSEC_ENET=y
+CONFIG_RTC_RX8025=y
CONFIG_BAUDRATE=9600
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig
index 1108c6a..89921e6 100644
--- a/configs/vyasa-rk3288_defconfig
+++ b/configs/vyasa-rk3288_defconfig
@@ -3,7 +3,6 @@
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00100000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3288=y
CONFIG_TARGET_VYASA_RK3288=y
CONFIG_NR_DRAM_BANKS=1
@@ -11,11 +10,11 @@
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_DEFAULT_FDT_FILE="rk3288-vyasa.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0xff704000
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_CMD_GPIO=y
@@ -85,6 +84,5 @@
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
CONFIG_CONSOLE_SCROLL_LINES=10
-CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig
index f1d6cc5..a8b6b41 100644
--- a/configs/wandboard_defconfig
+++ b/configs/wandboard_defconfig
@@ -12,6 +12,7 @@
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPL_FIT_PRINT=y
@@ -25,7 +26,6 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_FIT_IMAGE_TINY=y
CONFIG_SPL_FS_EXT4=y
@@ -37,6 +37,7 @@
CONFIG_CMD_MMC=y
CONFIG_CMD_SATA=y
CONFIG_CMD_USB=y
+CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
@@ -54,7 +55,7 @@
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_PINCTRL=y
@@ -66,4 +67,5 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_VIDEO_IPUV3=y
diff --git a/configs/warp7_bl33_defconfig b/configs/warp7_bl33_defconfig
index a79f670..80accfb 100644
--- a/configs/warp7_bl33_defconfig
+++ b/configs/warp7_bl33_defconfig
@@ -4,6 +4,9 @@
CONFIG_SECURE_BOOT=y
CONFIG_TARGET_WARP7=y
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp7/imximage.cfg"
CONFIG_BOUNCE_BUFFER=y
CONFIG_HUSH_PARSER=y
@@ -30,7 +33,7 @@
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
CONFIG_DM_PMIC=y
@@ -41,6 +44,7 @@
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
+CONFIG_OPTEE=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
@@ -54,4 +58,6 @@
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00"
-CONFIG_OPTEE_TZDRAM_SIZE=0x2000000
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_OPTEE_TZDRAM_SIZE=0x02000000
+CONFIG_OPTEE_TZDRAM_BASE=0x9e000000
diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig
index 5b35113..a022454 100644
--- a/configs/warp7_defconfig
+++ b/configs/warp7_defconfig
@@ -39,7 +39,7 @@
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
CONFIG_DM_PMIC=y
diff --git a/configs/warp_defconfig b/configs/warp_defconfig
index a37d769..7a6ea6f 100644
--- a/configs/warp_defconfig
+++ b/configs/warp_defconfig
@@ -30,7 +30,7 @@
# CONFIG_NET is not set
CONFIG_DFU_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
diff --git a/configs/wb45n_defconfig b/configs/wb45n_defconfig
index 8da284a..0f22a1e 100644
--- a/configs/wb45n_defconfig
+++ b/configs/wb45n_defconfig
@@ -7,13 +7,14 @@
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_OFFSET=0xa0000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x300000
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x300000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@@ -28,6 +29,7 @@
CONFIG_CMD_MTDPARTS=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_PMECC_CAP=4
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
diff --git a/configs/wb50n_defconfig b/configs/wb50n_defconfig
index 71a95b3..3e7f03a 100644
--- a/configs/wb50n_defconfig
+++ b/configs/wb50n_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x23f00000
CONFIG_TARGET_WB50N=y
@@ -6,12 +7,13 @@
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_OFFSET=0xA0000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x300000
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
-CONFIG_SPL_TEXT_BASE=0x300000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@@ -27,6 +29,7 @@
CONFIG_ENV_IS_IN_NAND=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_NAND=y
+# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_PMECC_CAP=8
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
diff --git a/configs/woodburn_defconfig b/configs/woodburn_defconfig
index ebc12ab..73b76aa 100644
--- a/configs/woodburn_defconfig
+++ b/configs/woodburn_defconfig
@@ -28,7 +28,7 @@
# CONFIG_PARTITION_UUIDS is not set
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_MXC_GPIO=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
diff --git a/configs/woodburn_sd_defconfig b/configs/woodburn_sd_defconfig
index 7182aff..b26b084 100644
--- a/configs/woodburn_sd_defconfig
+++ b/configs/woodburn_sd_defconfig
@@ -10,10 +10,10 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0x10002300
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/woodburn/imximage.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_TEXT_BASE=0x10002300
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
@@ -40,7 +40,7 @@
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_MXC_GPIO=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig
index 01c8884..a5d76e8 100644
--- a/configs/work_92105_defconfig
+++ b/configs/work_92105_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_SYS_ICACHE_OFF=y
CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_LPC32XX=y
CONFIG_SYS_TEXT_BASE=0x80100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -11,6 +12,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x00000000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS2,115200n8"
@@ -18,7 +20,6 @@
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_SPL_TEXT_BASE=0x00000000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_NAND_SUPPORT=y
diff --git a/configs/x530_defconfig b/configs/x530_defconfig
index 7db8de4..6d272ad 100644
--- a/configs/x530_defconfig
+++ b/configs/x530_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -13,14 +14,16 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0x40000030
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SILENT_CONSOLE=y
CONFIG_SILENT_U_BOOT_ONLY=y
CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC=y
CONFIG_MISC_INIT_R=y
-CONFIG_SPL_TEXT_BASE=0x40000030
CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x24000
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_MEMINFO=y
# CONFIG_CMD_FLASH is not set
@@ -51,6 +54,7 @@
CONFIG_I2C_MUX_PCA954x=y
# CONFIG_MMC is not set
CONFIG_NAND=y
+CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_PXA3XX=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=1
diff --git a/configs/x600_defconfig b/configs/x600_defconfig
index 03574d0..62ca1d6 100644
--- a/configs/x600_defconfig
+++ b/configs/x600_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
CONFIG_SYS_THUMB_BUILD=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
@@ -11,11 +12,11 @@
CONFIG_SPL=y
CONFIG_SYS_BOOTCOUNT_ADDR=0xD2801FF8
CONFIG_IDENT_STRING="-SPEAr"
+CONFIG_SPL_TEXT_BASE=0xd2800b00
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_TEXT_BASE=0xd2800b00
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="X600> "
@@ -24,6 +25,7 @@
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_CMD_IMLS=y
CONFIG_LOOPW=y
+CONFIG_MX_CYCLIC=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_NAND=y
@@ -59,6 +61,5 @@
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_BCH=y
-CONFIG_USE_TINY_PRINTF=y
CONFIG_OF_LIBFDT=y
# CONFIG_EFI_LOADER is not set
diff --git a/configs/xfi3_defconfig b/configs/xfi3_defconfig
index 054e3a7..6e89299 100644
--- a/configs/xfi3_defconfig
+++ b/configs/xfi3_defconfig
@@ -8,6 +8,7 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x00001000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200n8 "
@@ -18,7 +19,6 @@
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_TEXT_BASE=0x00001000
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
@@ -29,6 +29,7 @@
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MXS_GPIO=y
CONFIG_MMC_MXS=y
CONFIG_CONS_INDEX=0
CONFIG_USB=y
diff --git a/configs/xilinx_versal_mini_defconfig b/configs/xilinx_versal_mini_defconfig
index 19fac90..012ba3e 100644
--- a/configs/xilinx_versal_mini_defconfig
+++ b/configs/xilinx_versal_mini_defconfig
@@ -8,7 +8,7 @@
CONFIG_SYS_MALLOC_LEN=0x2000
CONFIG_SYS_MEM_RSVD_FOR_MMU=y
CONFIG_COUNTER_FREQUENCY=2720000
-# CONFIG_IMAGE_FORMAT_LEGACY is not set
+# CONFIG_LEGACY_IMAGE_FORMAT is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
diff --git a/configs/xilinx_versal_mini_emmc0_defconfig b/configs/xilinx_versal_mini_emmc0_defconfig
index 60c368c..440035f 100644
--- a/configs/xilinx_versal_mini_emmc0_defconfig
+++ b/configs/xilinx_versal_mini_emmc0_defconfig
@@ -47,7 +47,6 @@
# CONFIG_NET is not set
# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
-CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
# CONFIG_EFI_LOADER is not set
diff --git a/configs/xilinx_versal_mini_emmc1_defconfig b/configs/xilinx_versal_mini_emmc1_defconfig
index cbbf75f..07ec6eb 100644
--- a/configs/xilinx_versal_mini_emmc1_defconfig
+++ b/configs/xilinx_versal_mini_emmc1_defconfig
@@ -47,7 +47,6 @@
# CONFIG_NET is not set
# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
-CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
# CONFIG_EFI_LOADER is not set
diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig
index 3ce6c03..3b07545 100644
--- a/configs/xilinx_versal_virt_defconfig
+++ b/configs/xilinx_versal_virt_defconfig
@@ -44,7 +44,6 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_BLOCKSIZE=4096
-CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
diff --git a/configs/xilinx_zynqmp_mini_defconfig b/configs/xilinx_zynqmp_mini_defconfig
index aa9dd23..93fa7d8 100644
--- a/configs/xilinx_zynqmp_mini_defconfig
+++ b/configs/xilinx_zynqmp_mini_defconfig
@@ -7,7 +7,7 @@
CONFIG_SYS_MEM_RSVD_FOR_MMU=y
CONFIG_ZYNQMP_PSU_INIT_ENABLED=y
# CONFIG_CMD_ZYNQMP is not set
-# CONFIG_IMAGE_FORMAT_LEGACY is not set
+# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_BOARD_LATE_INIT is not set
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_CMDLINE_EDITING is not set
diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig
index 0faa332..f15c093 100644
--- a/configs/xilinx_zynqmp_mini_emmc0_defconfig
+++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig
@@ -7,12 +7,12 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
# CONFIG_CMD_ZYNQMP is not set
+CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
# CONFIG_BOARD_LATE_INIT is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="ZynqMP> "
diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig
index 867d2e5..fb9a182 100644
--- a/configs/xilinx_zynqmp_mini_emmc1_defconfig
+++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig
@@ -7,12 +7,12 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
# CONFIG_CMD_ZYNQMP is not set
+CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
# CONFIG_BOARD_LATE_INIT is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="ZynqMP> "
diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig
index d3cc851..bc63c08 100644
--- a/configs/xilinx_zynqmp_mini_qspi_defconfig
+++ b/configs/xilinx_zynqmp_mini_qspi_defconfig
@@ -10,11 +10,11 @@
CONFIG_ZYNQMP_NO_DDR=y
# CONFIG_PSCI_RESET is not set
# CONFIG_CMD_ZYNQMP is not set
+CONFIG_SPL_TEXT_BASE=0xfffc0000
# CONFIG_EXPERT is not set
-# CONFIG_IMAGE_FORMAT_LEGACY is not set
+# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_BOARD_LATE_INIT is not set
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_TEXT_BASE=0xfffc0000
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
# CONFIG_SYS_LONGHELP is not set
diff --git a/configs/xilinx_zynqmp_zc1232_revA_defconfig b/configs/xilinx_zynqmp_zc1232_revA_defconfig
index aa2165f..beb6d43 100644
--- a/configs/xilinx_zynqmp_zc1232_revA_defconfig
+++ b/configs/xilinx_zynqmp_zc1232_revA_defconfig
@@ -8,12 +8,12 @@
# CONFIG_SPL_FS_FAT is not set
# CONFIG_SPL_LIBDISK_SUPPORT is not set
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
diff --git a/configs/xilinx_zynqmp_zc1254_revA_defconfig b/configs/xilinx_zynqmp_zc1254_revA_defconfig
index 1ab0639..849a398 100644
--- a/configs/xilinx_zynqmp_zc1254_revA_defconfig
+++ b/configs/xilinx_zynqmp_zc1254_revA_defconfig
@@ -8,12 +8,12 @@
# CONFIG_SPL_FS_FAT is not set
# CONFIG_SPL_LIBDISK_SUPPORT is not set
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
diff --git a/configs/xilinx_zynqmp_zc1275_revA_defconfig b/configs/xilinx_zynqmp_zc1275_revA_defconfig
deleted file mode 100644
index ed6c1b8..0000000
--- a/configs/xilinx_zynqmp_zc1275_revA_defconfig
+++ /dev/null
@@ -1,52 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_ZYNQMP=y
-CONFIG_SYS_TEXT_BASE=0x8000000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL=y
-CONFIG_DEBUG_UART_BASE=0xff000000
-CONFIG_DEBUG_UART_CLOCK=100000000
-# CONFIG_SPL_FS_FAT is not set
-# CONFIG_SPL_LIBDISK_SUPPORT is not set
-CONFIG_DEBUG_UART=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_TEXT_BASE=0xfffc0000
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_ATF=y
-CONFIG_SYS_PROMPT="ZynqMP> "
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_CLK=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_FPGA_LOADBP=y
-CONFIG_CMD_FPGA_LOADP=y
-CONFIG_CMD_FPGA_LOAD_SECURE=y
-CONFIG_CMD_SF=y
-# CONFIG_CMD_NET is not set
-CONFIG_CMD_TIME=y
-CONFIG_CMD_TIMER=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1275-revA"
-CONFIG_SPL_DM=y
-CONFIG_CLK_ZYNQMP=y
-CONFIG_FPGA_XILINX=y
-CONFIG_FPGA_ZYNQMPPL=y
-CONFIG_MISC=y
-# CONFIG_MMC is not set
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_ISSI=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_DEBUG_UART_ZYNQ=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_ZYNQ_SERIAL=y
-CONFIG_SPI=y
-CONFIG_ZYNQMP_GQSPI=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zc1275_revB_defconfig b/configs/xilinx_zynqmp_zc1275_revB_defconfig
deleted file mode 100644
index 0c2491a..0000000
--- a/configs/xilinx_zynqmp_zc1275_revB_defconfig
+++ /dev/null
@@ -1,57 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_ZYNQMP=y
-CONFIG_SYS_TEXT_BASE=0x8000000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL=y
-CONFIG_DEBUG_UART_BASE=0xff000000
-CONFIG_DEBUG_UART_CLOCK=100000000
-# CONFIG_SPL_FS_FAT is not set
-# CONFIG_SPL_LIBDISK_SUPPORT is not set
-CONFIG_DEBUG_UART=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_TEXT_BASE=0xfffc0000
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_ATF=y
-CONFIG_SYS_PROMPT="ZynqMP> "
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_CLK=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_FPGA_LOADBP=y
-CONFIG_CMD_FPGA_LOADP=y
-CONFIG_CMD_FPGA_LOAD_SECURE=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-# CONFIG_CMD_NET is not set
-CONFIG_CMD_TIME=y
-CONFIG_CMD_TIMER=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1275-revB"
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_CLK_ZYNQMP=y
-CONFIG_FPGA_XILINX=y
-CONFIG_FPGA_ZYNQMPPL=y
-CONFIG_MISC=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_ISSI=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHY_MARVELL=y
-CONFIG_ZYNQ_GEM=y
-CONFIG_DEBUG_UART_ZYNQ=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_ZYNQ_SERIAL=y
-CONFIG_SPI=y
-CONFIG_ZYNQMP_GQSPI=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
index 7b1f5e9..a1e69b2 100644
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -9,13 +9,13 @@
CONFIG_SPL_ZYNQMP_TWO_SDHCI=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
index ae2554a..02f6d4a 100644
--- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
@@ -9,13 +9,13 @@
# CONFIG_SPL_LIBDISK_SUPPORT is not set
CONFIG_ZYNQMP_USB=y
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig
index 559a61e..c243064 100644
--- a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig
@@ -8,12 +8,12 @@
CONFIG_ZYNQMP_USB=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
index cc2af6d..e964fab 100644
--- a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
@@ -6,13 +6,13 @@
CONFIG_DEBUG_UART_BASE=0xff000000
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
index bf66171..5856d95 100644
--- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
@@ -6,13 +6,13 @@
CONFIG_DEBUG_UART_BASE=0xff000000
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
diff --git a/configs/xilinx_zynqmp_zcu100_revC_defconfig b/configs/xilinx_zynqmp_zcu100_revC_defconfig
index 4b3f72d..1ec1bdc 100644
--- a/configs/xilinx_zynqmp_zcu100_revC_defconfig
+++ b/configs/xilinx_zynqmp_zcu100_revC_defconfig
@@ -8,12 +8,12 @@
CONFIG_ZYNQ_SDHCI_MAX_FREQ=15000000
CONFIG_ZYNQMP_USB=y
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
index ef291a7..b27887e 100644
--- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
@@ -10,13 +10,13 @@
CONFIG_ZYNQMP_USB=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig b/configs/xilinx_zynqmp_zcu102_revA_defconfig
index 975e9f5..7746305 100644
--- a/configs/xilinx_zynqmp_zcu102_revA_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig
@@ -10,13 +10,13 @@
CONFIG_ZYNQMP_USB=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index 34918aa..3d58c01 100644
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -10,13 +10,13 @@
CONFIG_ZYNQMP_USB=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
diff --git a/configs/xilinx_zynqmp_zcu104_revA_defconfig b/configs/xilinx_zynqmp_zcu104_revA_defconfig
index e4090dc..e21c34c 100644
--- a/configs/xilinx_zynqmp_zcu104_revA_defconfig
+++ b/configs/xilinx_zynqmp_zcu104_revA_defconfig
@@ -8,12 +8,12 @@
CONFIG_ZYNQMP_USB=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
diff --git a/configs/xilinx_zynqmp_zcu104_revC_defconfig b/configs/xilinx_zynqmp_zcu104_revC_defconfig
index 25a2515..3d66d0a 100644
--- a/configs/xilinx_zynqmp_zcu104_revC_defconfig
+++ b/configs/xilinx_zynqmp_zcu104_revC_defconfig
@@ -8,12 +8,12 @@
CONFIG_ZYNQMP_USB=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
diff --git a/configs/xilinx_zynqmp_zcu106_revA_defconfig b/configs/xilinx_zynqmp_zcu106_revA_defconfig
index 212de92..300d3b2 100644
--- a/configs/xilinx_zynqmp_zcu106_revA_defconfig
+++ b/configs/xilinx_zynqmp_zcu106_revA_defconfig
@@ -10,12 +10,12 @@
CONFIG_ZYNQMP_USB=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
diff --git a/configs/xilinx_zynqmp_zcu111_revA_defconfig b/configs/xilinx_zynqmp_zcu111_revA_defconfig
index dec8947..a4caaff 100644
--- a/configs/xilinx_zynqmp_zcu111_revA_defconfig
+++ b/configs/xilinx_zynqmp_zcu111_revA_defconfig
@@ -8,12 +8,12 @@
CONFIG_ZYNQMP_USB=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
+CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
diff --git a/configs/xilinx_zynqmp_zcu1275_revA_defconfig b/configs/xilinx_zynqmp_zcu1275_revA_defconfig
new file mode 100644
index 0000000..4790061
--- /dev/null
+++ b/configs/xilinx_zynqmp_zcu1275_revA_defconfig
@@ -0,0 +1,52 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+# CONFIG_SPL_FS_FAT is not set
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
+CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0xfffc0000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
+CONFIG_SYS_PROMPT="ZynqMP> "
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
+CONFIG_CMD_SF=y
+# CONFIG_CMD_NET is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu1275-revA"
+CONFIG_SPL_DM=y
+CONFIG_CLK_ZYNQMP=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_MISC=y
+# CONFIG_MMC is not set
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_SPI=y
+CONFIG_ZYNQMP_GQSPI=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zcu1275_revB_defconfig b/configs/xilinx_zynqmp_zcu1275_revB_defconfig
new file mode 100644
index 0000000..ce2aa24
--- /dev/null
+++ b/configs/xilinx_zynqmp_zcu1275_revB_defconfig
@@ -0,0 +1,57 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+# CONFIG_SPL_FS_FAT is not set
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
+CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0xfffc0000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
+CONFIG_SYS_PROMPT="ZynqMP> "
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+# CONFIG_CMD_NET is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu1275-revB"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_CLK_ZYNQMP=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_MISC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHY_MARVELL=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_SPI=y
+CONFIG_ZYNQMP_GQSPI=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xpedite517x_defconfig b/configs/xpedite517x_defconfig
index cad95d3..8681942 100644
--- a/configs/xpedite517x_defconfig
+++ b/configs/xpedite517x_defconfig
@@ -8,6 +8,7 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
diff --git a/configs/xpedite520x_defconfig b/configs/xpedite520x_defconfig
index 1c0bd95..81689a4 100644
--- a/configs/xpedite520x_defconfig
+++ b/configs/xpedite520x_defconfig
@@ -8,6 +8,7 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
# CONFIG_MISC_INIT_R is not set
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/xpedite537x_defconfig b/configs/xpedite537x_defconfig
index e009aab..72a2a42 100644
--- a/configs/xpedite537x_defconfig
+++ b/configs/xpedite537x_defconfig
@@ -8,6 +8,7 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
# CONFIG_MISC_INIT_R is not set
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/xpedite550x_defconfig b/configs/xpedite550x_defconfig
index 5d3569b..f86d1bd 100644
--- a/configs/xpedite550x_defconfig
+++ b/configs/xpedite550x_defconfig
@@ -8,6 +8,7 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
# CONFIG_MISC_INIT_R is not set
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/xpress_defconfig b/configs/xpress_defconfig
index 709a7ef..70cdd79 100644
--- a/configs/xpress_defconfig
+++ b/configs/xpress_defconfig
@@ -26,7 +26,7 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_USB=y
diff --git a/configs/xpress_spl_defconfig b/configs/xpress_spl_defconfig
index e79a038..9e6dce0 100644
--- a/configs/xpress_spl_defconfig
+++ b/configs/xpress_spl_defconfig
@@ -10,13 +10,13 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
@@ -37,7 +37,7 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_USB=y
diff --git a/configs/xtfpga_defconfig b/configs/xtfpga_defconfig
index e95b664..051bba0 100644
--- a/configs/xtfpga_defconfig
+++ b/configs/xtfpga_defconfig
@@ -1,6 +1,7 @@
CONFIG_XTENSA=y
CONFIG_SYS_CPU="dc233c"
CONFIG_XTFPGA_KC705=y
+CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_BOOTDELAY=10
CONFIG_MISC_INIT_R=y
CONFIG_VERSION_VARIABLE=y
@@ -12,6 +13,7 @@
CONFIG_CMD_IMLS=y
CONFIG_CMD_ASKENV=y
CONFIG_CRC32_VERIFY=y
+CONFIG_MX_CYCLIC=y
CONFIG_CMD_SAVES=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
diff --git a/configs/zc5202_defconfig b/configs/zc5202_defconfig
index ae3a6b3..9ca2af2 100644
--- a/configs/zc5202_defconfig
+++ b/configs/zc5202_defconfig
@@ -12,6 +12,7 @@
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
CONFIG_BOOTDELAY=3
@@ -19,10 +20,10 @@
CONFIG_DEFAULT_FDT_FILE="imx6q-zc5202.dtb"
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
@@ -35,7 +36,7 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=3
CONFIG_SF_DEFAULT_MODE=0
diff --git a/configs/zc5601_defconfig b/configs/zc5601_defconfig
index 65a1915..0b73f7e 100644
--- a/configs/zc5601_defconfig
+++ b/configs/zc5601_defconfig
@@ -12,6 +12,7 @@
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
CONFIG_BOOTDELAY=3
@@ -19,10 +20,10 @@
CONFIG_DEFAULT_FDT_FILE="imx6q-zc5601.dtb"
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
@@ -34,7 +35,7 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_USDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=3
CONFIG_SF_DEFAULT_MODE=0
diff --git a/configs/zmx25_defconfig b/configs/zmx25_defconfig
index 60f0efd..3bba1ec 100644
--- a/configs/zmx25_defconfig
+++ b/configs/zmx25_defconfig
@@ -4,6 +4,7 @@
CONFIG_TARGET_ZMX25=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_BOOTDELAY=5
+CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
diff --git a/configs/zynq_cc108_defconfig b/configs/zynq_cc108_defconfig
index 35ebd14..9bfe5ce 100644
--- a/configs/zynq_cc108_defconfig
+++ b/configs/zynq_cc108_defconfig
@@ -13,9 +13,11 @@
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig
index fca0382..0910d3b 100644
--- a/configs/zynq_cse_nand_defconfig
+++ b/configs/zynq_cse_nand_defconfig
@@ -10,6 +10,7 @@
CONFIG_SYS_MALLOC_LEN=0x1000
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
+CONFIG_USE_PREBOOT=y
# CONFIG_BOARD_LATE_INIT is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig
index 21d7dd5..0a6b172 100644
--- a/configs/zynq_cse_nor_defconfig
+++ b/configs/zynq_cse_nor_defconfig
@@ -10,6 +10,7 @@
CONFIG_SYS_MALLOC_LEN=0x1000
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
+CONFIG_USE_PREBOOT=y
# CONFIG_BOARD_LATE_INIT is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig
index 8f9ba07..4972d70 100644
--- a/configs/zynq_cse_qspi_defconfig
+++ b/configs/zynq_cse_qspi_defconfig
@@ -16,11 +16,13 @@
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_USE_PREBOOT=y
# CONFIG_BOARD_LATE_INIT is not set
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_ARCH_EARLY_INIT_R is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
# CONFIG_SYS_LONGHELP is not set
diff --git a/configs/zynq_dlc20_rev1_0_defconfig b/configs/zynq_dlc20_rev1_0_defconfig
index 944c113..b6751ad 100644
--- a/configs/zynq_dlc20_rev1_0_defconfig
+++ b/configs/zynq_dlc20_rev1_0_defconfig
@@ -14,11 +14,13 @@
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_USE_PREBOOT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_DFU=y
diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig
index a48f203..d30581b 100644
--- a/configs/zynq_microzed_defconfig
+++ b/configs/zynq_microzed_defconfig
@@ -10,10 +10,12 @@
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_DFU=y
diff --git a/configs/zynq_minized_defconfig b/configs/zynq_minized_defconfig
index 60fe72f..3c95f0a 100644
--- a/configs/zynq_minized_defconfig
+++ b/configs/zynq_minized_defconfig
@@ -13,6 +13,7 @@
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="Zynq> "
diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig
index 453cd54..6457876 100644
--- a/configs/zynq_picozed_defconfig
+++ b/configs/zynq_picozed_defconfig
@@ -7,6 +7,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="Zynq> "
diff --git a/configs/zynq_z_turn_defconfig b/configs/zynq_z_turn_defconfig
index d105b71..d133fea 100644
--- a/configs/zynq_z_turn_defconfig
+++ b/configs/zynq_z_turn_defconfig
@@ -13,10 +13,12 @@
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_DFU=y
diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig
index 3c4103f..6b670ae 100644
--- a/configs/zynq_zc702_defconfig
+++ b/configs/zynq_zc702_defconfig
@@ -14,10 +14,12 @@
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_MEMTEST=y
diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig
index 3124de9..3d0cd31 100644
--- a/configs/zynq_zc706_defconfig
+++ b/configs/zynq_zc706_defconfig
@@ -16,11 +16,13 @@
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_PRINT=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_FPGA_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_DFU=y
diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig
index 3b59cf2..53108ff 100644
--- a/configs/zynq_zc770_xm010_defconfig
+++ b/configs/zynq_zc770_xm010_defconfig
@@ -14,10 +14,12 @@
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig
index 6d377e9..feedb32 100644
--- a/configs/zynq_zc770_xm011_defconfig
+++ b/configs/zynq_zc770_xm011_defconfig
@@ -15,7 +15,8 @@
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="Zynq> "
diff --git a/configs/zynq_zc770_xm011_x16_defconfig b/configs/zynq_zc770_xm011_x16_defconfig
index fc2d3f3..28d63c9 100644
--- a/configs/zynq_zc770_xm011_x16_defconfig
+++ b/configs/zynq_zc770_xm011_x16_defconfig
@@ -15,7 +15,8 @@
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="Zynq> "
diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig
index 0767e91..01e3d5f 100644
--- a/configs/zynq_zc770_xm012_defconfig
+++ b/configs/zynq_zc770_xm012_defconfig
@@ -12,7 +12,8 @@
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="Zynq> "
diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig
index 9eb67cf..30bb0ef 100644
--- a/configs/zynq_zc770_xm013_defconfig
+++ b/configs/zynq_zc770_xm013_defconfig
@@ -12,10 +12,12 @@
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig
index b5dbe40..9b6d754 100644
--- a/configs/zynq_zed_defconfig
+++ b/configs/zynq_zed_defconfig
@@ -13,10 +13,12 @@
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_DFU=y
diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig
index 0ad9284..2abc6db 100644
--- a/configs/zynq_zybo_defconfig
+++ b/configs/zynq_zybo_defconfig
@@ -13,10 +13,12 @@
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_DFU=y
diff --git a/configs/zynq_zybo_z7_defconfig b/configs/zynq_zybo_z7_defconfig
index d434982..eda1416 100644
--- a/configs/zynq_zybo_z7_defconfig
+++ b/configs/zynq_zybo_z7_defconfig
@@ -13,10 +13,12 @@
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_DFU=y
diff --git a/disk/part.c b/disk/part.c
index 7e84214..8982ef3 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <errno.h>
#include <ide.h>
#include <malloc.h>
diff --git a/disk/part_amiga.c b/disk/part_amiga.c
index 86d008d..5a2bb71 100644
--- a/disk/part_amiga.c
+++ b/disk/part_amiga.c
@@ -6,6 +6,7 @@
*/
#include <common.h>
#include <command.h>
+#include <env.h>
#include <ide.h>
#include "part_amiga.h"
diff --git a/disk/part_dos.c b/disk/part_dos.c
index 936cee0..8ddc13b 100644
--- a/disk/part_dos.c
+++ b/disk/part_dos.c
@@ -23,6 +23,10 @@
#define DOS_PART_DEFAULT_SECTOR 512
+/* should this be configurable? It looks like it's not very common at all
+ * to use large numbers of partitions */
+#define MAX_EXT_PARTS 256
+
/* Convert char[4] in little endian format to the host format integer
*/
static inline unsigned int le32_to_int(unsigned char *le32)
@@ -89,7 +93,8 @@
static int part_test_dos(struct blk_desc *dev_desc)
{
#ifndef CONFIG_SPL_BUILD
- ALLOC_CACHE_ALIGN_BUFFER(legacy_mbr, mbr, 1);
+ ALLOC_CACHE_ALIGN_BUFFER(legacy_mbr, mbr,
+ DIV_ROUND_UP(dev_desc->blksz, sizeof(legacy_mbr)));
if (blk_dread(dev_desc, 0, 1, (ulong *)mbr) != 1)
return -1;
@@ -126,6 +131,13 @@
dos_partition_t *pt;
int i;
+ /* set a maximum recursion level */
+ if (part_num > MAX_EXT_PARTS)
+ {
+ printf("** Nested DOS partitions detected, stopping **\n");
+ return;
+ }
+
if (blk_dread(dev_desc, ext_part_sector, 1, (ulong *)buffer) != 1) {
printf ("** Can't read partition table on %d:" LBAFU " **\n",
dev_desc->devnum, ext_part_sector);
@@ -191,6 +203,13 @@
int i;
int dos_type;
+ /* set a maximum recursion level */
+ if (part_num > MAX_EXT_PARTS)
+ {
+ printf("** Nested DOS partitions detected, stopping **\n");
+ return -1;
+ }
+
if (blk_dread(dev_desc, ext_part_sector, 1, (ulong *)buffer) != 1) {
printf ("** Can't read partition table on %d:" LBAFU " **\n",
dev_desc->devnum, ext_part_sector);
diff --git a/disk/part_efi.c b/disk/part_efi.c
index c0fa753..51fa4a7 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -51,6 +51,8 @@
static gpt_entry *alloc_read_gpt_entries(struct blk_desc *dev_desc,
gpt_header *pgpt_head);
static int is_pte_valid(gpt_entry * pte);
+static int find_valid_gpt(struct blk_desc *dev_desc, gpt_header *gpt_head,
+ gpt_entry **pgpt_pte);
static char *print_efiname(gpt_entry *pte)
{
@@ -192,19 +194,8 @@
unsigned char *guid_bin;
/* This function validates AND fills in the GPT header and PTE */
- if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA,
- gpt_head, &gpt_pte) != 1) {
- printf("%s: *** ERROR: Invalid GPT ***\n", __func__);
- if (is_gpt_valid(dev_desc, dev_desc->lba - 1,
- gpt_head, &gpt_pte) != 1) {
- printf("%s: *** ERROR: Invalid Backup GPT ***\n",
- __func__);
- return -EINVAL;
- } else {
- printf("%s: *** Using Backup GPT ***\n",
- __func__);
- }
- }
+ if (find_valid_gpt(dev_desc, gpt_head, &gpt_pte) != 1)
+ return -EINVAL;
guid_bin = gpt_head->disk_guid.b;
uuid_bin_to_str(guid_bin, guid, UUID_STR_FORMAT_GUID);
@@ -223,19 +214,8 @@
unsigned char *uuid_bin;
/* This function validates AND fills in the GPT header and PTE */
- if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA,
- gpt_head, &gpt_pte) != 1) {
- printf("%s: *** ERROR: Invalid GPT ***\n", __func__);
- if (is_gpt_valid(dev_desc, (dev_desc->lba - 1),
- gpt_head, &gpt_pte) != 1) {
- printf("%s: *** ERROR: Invalid Backup GPT ***\n",
- __func__);
- return;
- } else {
- printf("%s: *** Using Backup GPT ***\n",
- __func__);
- }
- }
+ if (find_valid_gpt(dev_desc, gpt_head, &gpt_pte) != 1)
+ return;
debug("%s: gpt-entry at %p\n", __func__, gpt_pte);
@@ -284,19 +264,8 @@
}
/* This function validates AND fills in the GPT header and PTE */
- if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA,
- gpt_head, &gpt_pte) != 1) {
- printf("%s: *** ERROR: Invalid GPT ***\n", __func__);
- if (is_gpt_valid(dev_desc, (dev_desc->lba - 1),
- gpt_head, &gpt_pte) != 1) {
- printf("%s: *** ERROR: Invalid Backup GPT ***\n",
- __func__);
- return -1;
- } else {
- printf("%s: *** Using Backup GPT ***\n",
- __func__);
- }
- }
+ if (find_valid_gpt(dev_desc, gpt_head, &gpt_pte) != 1)
+ return -1;
if (part > le32_to_cpu(gpt_head->num_partition_entries) ||
!is_pte_valid(&gpt_pte[part - 1])) {
@@ -313,8 +282,8 @@
- info->start;
info->blksz = dev_desc->blksz;
- sprintf((char *)info->name, "%s",
- print_efiname(&gpt_pte[part - 1]));
+ snprintf((char *)info->name, sizeof(info->name), "%s",
+ print_efiname(&gpt_pte[part - 1]));
strcpy((char *)info->type, "U-Boot");
info->bootable = is_bootable(&gpt_pte[part - 1]);
#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
@@ -670,9 +639,18 @@
return ret;
}
-static void gpt_convert_efi_name_to_char(char *s, efi_char16_t *es, int n)
+/**
+ * gpt_convert_efi_name_to_char() - convert u16 string to char string
+ *
+ * TODO: this conversion only supports ANSI characters
+ *
+ * @s: target buffer
+ * @es: u16 string to be converted
+ * @n: size of target buffer
+ */
+static void gpt_convert_efi_name_to_char(char *s, void *es, int n)
{
- char *ess = (char *)es;
+ char *ess = es;
int i, j;
memset(s, '\0', n);
@@ -930,7 +908,7 @@
* gpt is a GPT header ptr, filled on return.
* ptes is a PTEs ptr, filled on return.
*
- * Description: returns 1 if valid, 0 on error.
+ * Description: returns 1 if valid, 0 on error, 2 if ignored header
* If valid, returns pointers to PTEs.
*/
static int is_gpt_valid(struct blk_desc *dev_desc, u64 lba,
@@ -956,6 +934,12 @@
return 0;
}
+ /* Invalid but nothing to yell about. */
+ if (le64_to_cpu(pgpt_head->signature) == GPT_HEADER_CHROMEOS_IGNORE) {
+ debug("ChromeOS 'IGNOREME' GPT header found and ignored\n");
+ return 2;
+ }
+
if (validate_gpt_header(pgpt_head, (lbaint_t)lba, dev_desc->lba))
return 0;
@@ -988,6 +972,40 @@
}
/**
+ * find_valid_gpt() - finds a valid GPT header and PTEs
+ *
+ * gpt is a GPT header ptr, filled on return.
+ * ptes is a PTEs ptr, filled on return.
+ *
+ * Description: returns 1 if found a valid gpt, 0 on error.
+ * If valid, returns pointers to PTEs.
+ */
+static int find_valid_gpt(struct blk_desc *dev_desc, gpt_header *gpt_head,
+ gpt_entry **pgpt_pte)
+{
+ int r;
+
+ r = is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA, gpt_head,
+ pgpt_pte);
+
+ if (r != 1) {
+ if (r != 2)
+ printf("%s: *** ERROR: Invalid GPT ***\n", __func__);
+
+ if (is_gpt_valid(dev_desc, (dev_desc->lba - 1), gpt_head,
+ pgpt_pte) != 1) {
+ printf("%s: *** ERROR: Invalid Backup GPT ***\n",
+ __func__);
+ return 0;
+ }
+ if (r != 2)
+ printf("%s: *** Using Backup GPT ***\n",
+ __func__);
+ }
+ return 1;
+}
+
+/**
* alloc_read_gpt_entries(): reads partition entries from disk
* @dev_desc
* @gpt - GPT header
diff --git a/doc/.gitignore b/doc/.gitignore
new file mode 100644
index 0000000..53752db
--- /dev/null
+++ b/doc/.gitignore
@@ -0,0 +1 @@
+output
diff --git a/doc/README.ARC b/doc/README.ARC
deleted file mode 100644
index 5f414fb..0000000
--- a/doc/README.ARC
+++ /dev/null
@@ -1,27 +0,0 @@
-Synopsys' DesignWare(r) ARC(r) Processors are a family of 32-bit CPUs
-that SoC designers can optimize for a wide range of uses, from deeply embedded
-to high-performance host applications.
-
-More information on ARC cores avaialble here:
-http://www.synopsys.com/IP/ProcessorIP/ARCProcessors/Pages/default.aspx
-
-Designers can differentiate their products by using patented configuration
-technology to tailor each ARC processor instance to meet specific performance,
-power and area requirements.
-
-The DesignWare ARC processors are also extendable, allowing designers to add
-their own custom instructions that dramatically increase performance.
-
-Synopsys' ARC processors have been used by over 170 customers worldwide who
-collectively ship more than 1 billion ARC-based chips annually.
-
-All DesignWare ARC processors utilize a 16-/32-bit ISA that provides excellent
-performance and code density for embedded and host SoC applications.
-
-The RISC microprocessors are synthesizable and can be implemented in any foundry
-or process, and are supported by a complete suite of development tools.
-
-The ARC GNU toolchain with support for all ARC Processors can be downloaded
-from here (available pre-built toolchains as well):
-
-https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases
diff --git a/doc/README.AX25 b/doc/README.AX25
deleted file mode 100644
index 7a607dd..0000000
--- a/doc/README.AX25
+++ /dev/null
@@ -1,46 +0,0 @@
-AX25 is Andes CPU IP to adopt RISC-V architecture.
-
-Features
-========
-
-CPU Core
- - 5-stage in-order execution pipeline
- - Hardware Multiplier
- - radix-2/radix-4/radix-16/radix-256/fast
- - Hardware Divider
- - Optional branch prediction
- - Machine mode and optional user mode
- - Optional performance monitoring
-
-ISA
- - RV64I base integer instructions
- - RVC for 16-bit compressed instructions
- - RVM for multiplication and division instructions
-
-Memory subsystem
- - I & D local memory
- - Size: 4KB to 16MB
- - Memory subsyetem soft-error protection
- - Protection scheme: parity-checking or error-checking-and-correction (ECC)
- - Automatic hardware error correction
-
-Bus
- - Interface Protocol
- - Synchronous AHB (32-bit/64-bit data-width), or
- - Synchronous AXI4 (64-bit data-width)
-
-Power management
- - Wait for interrupt (WFI) mode
-
-Debug
- - Configurable number of breakpoints: 2/4/8
- - External Debug Module
- - AHB slave port
- - External JTAG debug transport module
-
-Platform Level Interrupt Controller (PLIC)
- - AHB slave port
- - Configurable number of interrupts: 1-1023
- - Configurable number of interrupt priorities: 3/7/15/63/127/255
- - Configurable number of targets: 1-16
- - Preempted interrupt priority stack
diff --git a/doc/README.N1213 b/doc/README.N1213
deleted file mode 100644
index e107166..0000000
--- a/doc/README.N1213
+++ /dev/null
@@ -1,55 +0,0 @@
-N1213 is a configurable hard/soft core of NDS32's N12 CPU family.
-
-Features
-========
-
-CPU Core
- - 16-/32-bit mixable instruction format.
- - 32 general-purpose 32-bit registers.
- - 8-stage pipeline.
- - Dynamic branch prediction.
- - 32/64/128/256 BTB.
- - Return address stack (RAS).
- - Vector interrupts for internal/external.
- interrupt controller with 6 hardware interrupt signals.
- - 3 HW-level nested interruptions.
- - User and super-user mode support.
- - Memory-mapped I/O.
- - Address space up to 4GB.
-
-Memory Management Unit
- - TLB
- - 4/8-entry fully associative iTLB/dTLB.
- - 32/64/128-entry 4-way set-associati.ve main TLB.
- - TLB locking support
- - Optional hardware page table walker.
- - Two groups of page size support.
- - 4KB & 1MB.
- - 8KB & 1MB.
-
-Memory Subsystem
- - I & D cache.
- - Virtually indexed and physically tagged.
- - Cache size: 8KB/16KB/32KB/64KB.
- - Cache line size: 16B/32B.
- - Set associativity: 2-way, 4-way or direct-mapped.
- - Cache locking support.
- - I & D local memory (LM).
- - Size: 4KB to 1MB.
- - Bank numbers: 1 or 2.
- - Optional 1D/2D DMA engine.
- - Internal or external to CPU core.
-
-Bus Interface
- - Synchronous/Asynchronous AHB bus: 0, 1 or 2 ports.
- - Synchronous High speed memory port.
- (HSMP): 0, 1 or 2 ports.
-
-Debug
- - JTAG debug interface.
- - Embedded debug module (EDM).
- - Optional embedded program tracer interface.
-
-Miscellaneous
- - Programmable data endian control.
- - Performance monitoring mechanism.
diff --git a/doc/README.NDS32 b/doc/README.NDS32
deleted file mode 100644
index b2b58fc..0000000
--- a/doc/README.NDS32
+++ /dev/null
@@ -1,41 +0,0 @@
-NDS32 is a new high-performance 32-bit RISC microprocessor core.
-
-http://www.andestech.com/
-
-AndeStar ISA
-============
-AndeStar is a patent-pending 16-bit/32-bit mixed-length instruction set to
-achieve optimal system performance, code density, and power efficiency.
-
-It contains the following features:
- - Intermixable 32-bit and 16-bit instruction sets without the need for
- mode switch.
- - 16-bit instructions as a frequently used subset of 32-bit instructions.
- - RISC-style register-based instruction set.
- - 32 32-bit General Purpose Registers (GPR).
- - Upto 1024 User Special Registers (USR) for existing and extension
- instructions.
- - Rich load/store instructions for...
- - Single memory access with base address update.
- - Multiple aligned and unaligned memory accesses for memory copy and stack
- operations.
- - Data prefetch to improve data cache performance.
- - Non-bus locking synchronization instructions.
- - PC relative jump and PC read instructions for efficient position independent
- code.
- - Multiply-add and multiple-sub with 64-bit accumulator.
- - Instruction for efficient power management.
- - Bi-endian support.
- - Three instruction extension space for application acceleration:
- - Performance extension.
- - Andes future extensions (for floating-point, multimedia, etc.)
- - Customer extensions.
-
-AndesCore CPU
-=============
-Andes Technology has 4 families of CPU cores: N12, N10, N9, N8.
-
-For details about N12 CPU family, please check doc/README.N1213.
-
-The NDS32 ports of u-boot, the Linux kernel, the GNU toolchain and
-other associated software are actively supported by Andes Technology Corporation.
diff --git a/doc/README.SPL b/doc/README.SPL
index 7a30fef..6eed83f 100644
--- a/doc/README.SPL
+++ b/doc/README.SPL
@@ -66,6 +66,22 @@
CONFIG_SPL_RAM_DEVICE (common/spl/spl.c)
CONFIG_SPL_WATCHDOG_SUPPORT (drivers/watchdog/libwatchdog.o)
+Device tree
+-----------
+The U-Boot device tree is filtered by the fdtgrep tools during the build
+process to generate a much smaller device tree used in SPL (spl/u-boot-spl.dtb)
+with:
+- the mandatory nodes (/alias, /chosen, /config)
+- the nodes with one pre-relocation property:
+ 'u-boot,dm-pre-reloc' or 'u-boot,dm-spl'
+
+ftgrep is also used to remove:
+- the properties defined in CONFIG_OF_SPL_REMOVE_PROPS
+- all the pre-relocation properties
+ ('u-boot,dm-pre-reloc', 'u-boot,dm-spl' and 'u-boot,dm-tpl')
+
+All the nodes remaining in the SPL devicetree are bound
+(see driver-model/README.txt).
Debugging
---------
diff --git a/doc/README.TPL b/doc/README.TPL
index 980debe..c94129f 100644
--- a/doc/README.TPL
+++ b/doc/README.TPL
@@ -34,6 +34,10 @@
is set. Source files can be compiled for TPL with options choosed in the
board config file.
+TPL use a small device tree (u-boot-tpl.dtb), containing only the nodes with
+the pre-relocation properties: 'u-boot,dm-pre-reloc' and 'u-boot,dm-tpl'
+(see README.SPL for details).
+
For example:
spl/Makefile:
diff --git a/doc/README.ae350 b/doc/README.ae350
deleted file mode 100644
index 189a6b7..0000000
--- a/doc/README.ae350
+++ /dev/null
@@ -1,275 +0,0 @@
-Andes Technology SoC AE350
-===========================
-
-AE350 is the mainline SoC produced by Andes Technology using AX25 CPU core
-base on RISC-V architecture.
-
-AE350 has integrated both AHB and APB bus and many periphals for application
-and product development.
-
-AX25-AE350
-=========
-
-AX25-AE350 is the SoC with AE350 hardcore CPU.
-
-Configurations
-==============
-
-CONFIG_SKIP_LOWLEVEL_INIT:
- If you want to boot this system from SPI ROM and bypass e-bios (the
- other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT
- in "include/configs/ax25-ae350.h".
-
-Build and boot steps
-====================
-
-build:
-1. Prepare the toolchains and make sure the $PATH to toolchains is correct.
-2. Use `make ae350_rv[32|64]_defconfig` in u-boot root to build the image for 32 or 64 bit.
-
-Verification
-====================
-
-Target
-====================
-1. startup
-2. relocation
-3. timer driver
-4. uart driver
-5. mac driver
-6. mmc driver
-7. spi driver
-
-Steps
-====================
-1. Define CONFIG_SKIP_LOWLEVEL_INIT to build u-boot which is loaded via gdb from ram.
-2. Undefine CONFIG_SKIP_LOWLEVEL_INIT to build u-boot which is booted from spi rom.
-3. Ping a server by mac driver
-4. Scan sd card and copy u-boot image which is booted from flash to ram by sd driver.
-5. Burn this u-boot image to spi rom by spi driver
-6. Re-boot u-boot from spi flash with power off and power on.
-
-Messages of U-Boot boot on AE350 board
-======================================
-U-Boot 2018.01-rc2-00033-g824f89a (Dec 21 2017 - 16:51:26 +0800)
-
-DRAM: 1 GiB
-MMC: mmc@f0e00000: 0
-SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB
-In: serial@f0300000
-Out: serial@f0300000
-Err: serial@f0300000
-Net:
-Warning: mac@e0100000 (eth0) using random MAC address - be:dd:d7:e4:e8:10
-eth0: mac@e0100000
-
-RISC-V # version
-U-Boot 2018.01-rc2-00033-gb265b91-dirty (Dec 22 2017 - 13:54:21 +0800)
-
-riscv32-unknown-linux-gnu-gcc (GCC) 7.2.0
-GNU ld (GNU Binutils) 2.29
-
-RISC-V # setenv ipaddr 10.0.4.200 ;
-RISC-V # setenv serverip 10.0.4.97 ;
-RISC-V # ping 10.0.4.97 ;
-Using mac@e0100000 device
-host 10.0.4.97 is alive
-
-RISC-V # mmc rescan
-RISC-V # fatls mmc 0:1
- 318907 u-boot-ae350-64.bin
- 1252 hello_world_ae350_32.bin
- 328787 u-boot-ae350-32.bin
-
-3 file(s), 0 dir(s)
-
-RISC-V # sf probe 0:0 50000000 0
-SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB
-
-RISC-V # sf test 0x100000 0x1000
-SPI flash test:
-0 erase: 36 ticks, 111 KiB/s 0.888 Mbps
-1 check: 29 ticks, 137 KiB/s 1.096 Mbps
-2 write: 40 ticks, 100 KiB/s 0.800 Mbps
-3 read: 20 ticks, 200 KiB/s 1.600 Mbps
-Test passed
-0 erase: 36 ticks, 111 KiB/s 0.888 Mbps
-1 check: 29 ticks, 137 KiB/s 1.096 Mbps
-2 write: 40 ticks, 100 KiB/s 0.800 Mbps
-3 read: 20 ticks, 200 KiB/s 1.600 Mbps
-
-RISC-V # fatload mmc 0:1 0x600000 u-boot-ae350-32.bin
-reading u-boot-ae350-32.bin
-328787 bytes read in 324 ms (990.2 KiB/s)
-
-RISC-V # sf erase 0x0 0x51000
-SF: 331776 bytes @ 0x0 Erased: OK
-
-RISC-V # sf write 0x600000 0x0 0x50453
-device 0 offset 0x0, size 0x50453
-SF: 328787 bytes @ 0x0 Written: OK
-
-RISC-V # crc32 0x600000 0x50453
-crc32 for 00600000 ... 00650452 ==> 692dc44a
-
-RISC-V # crc32 0x80000000 0x50453
-crc32 for 80000000 ... 80050452 ==> 692dc44a
-RISC-V #
-
-*** power-off and power-on, this U-Boot is booted from spi flash ***
-
-U-Boot 2018.01-rc2-00032-gf67dd47-dirty (Dec 21 2017 - 13:56:03 +0800)
-
-DRAM: 1 GiB
-MMC: mmc@f0e00000: 0
-SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB
-In: serial@f0300000
-Out: serial@f0300000
-Err: serial@f0300000
-Net:
-Warning: mac@e0100000 (eth0) using random MAC address - ee:4c:58:29:32:f5
-eth0: mac@e0100000
-RISC-V #
-
-
-Boot bbl and riscv-linux via U-Boot on QEMU
-===========================================
-1. Build riscv-linux
-2. Build bbl and riscv-linux with --with-payload
-3. Prepare ae350.dtb
-4. Creating OS-kernel images
- ./mkimage -A riscv -O linux -T kernel -C none -a 0x0000 -e 0x0000 -d bbl.bin bootmImage-bbl.bin
- Image Name:
- Created: Tue Mar 13 10:06:42 2018
- Image Type: RISC-V Linux Kernel Image (uncompressed)
- Data Size: 17901204 Bytes = 17481.64 KiB = 17.07 MiB
- Load Address: 00000000
- Entry Point: 00000000
-
-4. Copy bootmImage-bbl.bin and ae350.dtb to qemu sd card image
-5. Message of booting riscv-linux from bbl via u-boot on qemu
-
-U-Boot 2018.03-rc4-00031-g2631273 (Mar 13 2018 - 15:02:55 +0800)
-
-DRAM: 1 GiB
-main-loop: WARNING: I/O thread spun for 1000 iterations
-MMC: mmc@f0e00000: 0
-Loading Environment from SPI Flash... *** Warning - spi_flash_probe_bus_cs() failed, using default environment
-
-Failed (-22)
-In: serial@f0300000
-Out: serial@f0300000
-Err: serial@f0300000
-Net:
-Warning: mac@e0100000 (eth0) using random MAC address - 02:00:00:00:00:00
-eth0: mac@e0100000
-RISC-V # mmc rescan
-RISC-V # mmc part
-
-Partition Map for MMC device 0 -- Partition Type: DOS
-
-Part Start Sector Num Sectors UUID Type
-RISC-V # fatls mmc 0:0
- 17901268 bootmImage-bbl.bin
- 1954 ae2xx.dtb
-
-2 file(s), 0 dir(s)
-
-RISC-V # fatload mmc 0:0 0x00600000 bootmImage-bbl.bin
-17901268 bytes read in 4642 ms (3.7 MiB/s)
-RISC-V # fatload mmc 0:0 0x2000000 ae350.dtb
-1954 bytes read in 1 ms (1.9 MiB/s)
-RISC-V # setenv bootm_size 0x2000000
-RISC-V # setenv fdt_high 0x1f00000
-RISC-V # bootm 0x00600000 - 0x2000000
-## Booting kernel from Legacy Image at 00600000 ...
- Image Name:
- Image Type: RISC-V Linux Kernel Image (uncompressed)
- Data Size: 17901204 Bytes = 17.1 MiB
- Load Address: 00000000
- Entry Point: 00000000
- Verifying Checksum ... OK
-## Flattened Device Tree blob at 02000000
- Booting using the fdt blob at 0x2000000
- Loading Kernel Image ... OK
- Loading Device Tree to 0000000001efc000, end 0000000001eff7a1 ... OK
-[ 0.000000] OF: fdt: Ignoring memory range 0x0 - 0x200000
-[ 0.000000] Linux version 4.14.0-00046-gf3e439f-dirty (rick@atcsqa06) (gcc version 7.1.1 20170509 (GCC)) #1 Tue Jan 9 16:34:25 CST 2018
-[ 0.000000] bootconsole [early0] enabled
-[ 0.000000] Initial ramdisk at: 0xffffffe000016a98 (12267008 bytes)
-[ 0.000000] Zone ranges:
-[ 0.000000] DMA [mem 0x0000000000200000-0x000000007fffffff]
-[ 0.000000] Normal empty
-[ 0.000000] Movable zone start for each node
-[ 0.000000] Early memory node ranges
-[ 0.000000] node 0: [mem 0x0000000000200000-0x000000007fffffff]
-[ 0.000000] Initmem setup node 0 [mem 0x0000000000200000-0x000000007fffffff]
-[ 0.000000] elf_hwcap is 0x112d
-[ 0.000000] random: fast init done
-[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 516615
-[ 0.000000] Kernel command line: console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7
-[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
-[ 0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)
-[ 0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)
-[ 0.000000] Sorting __ex_table...
-[ 0.000000] Memory: 2047832K/2095104K available (1856K kernel code, 204K rwdata, 532K rodata, 12076K init, 756K bss, 47272K reserved, 0K cma-reserved)
-[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
-[ 0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0
-[ 0.000000] riscv,cpu_intc,0: 64 local interrupts mapped
-[ 0.000000] riscv,plic0,e4000000: mapped 31 interrupts to 1/2 handlers
-[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x24e6a1710, max_idle_ns: 440795202120 ns
-[ 0.000000] Calibrating delay loop (skipped), value calculated using timer frequency.. 20.00 BogoMIPS (lpj=40000)
-[ 0.000000] pid_max: default: 32768 minimum: 301
-[ 0.004000] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes)
-[ 0.004000] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes)
-[ 0.056000] devtmpfs: initialized
-[ 0.060000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
-[ 0.064000] futex hash table entries: 256 (order: 0, 6144 bytes)
-[ 0.068000] NET: Registered protocol family 16
-[ 0.080000] vgaarb: loaded
-[ 0.084000] clocksource: Switched to clocksource riscv_clocksource
-[ 0.088000] NET: Registered protocol family 2
-[ 0.092000] TCP established hash table entries: 16384 (order: 5, 131072 bytes)
-[ 0.096000] TCP bind hash table entries: 16384 (order: 5, 131072 bytes)
-[ 0.096000] TCP: Hash tables configured (established 16384 bind 16384)
-[ 0.100000] UDP hash table entries: 1024 (order: 3, 32768 bytes)
-[ 0.100000] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes)
-[ 0.104000] NET: Registered protocol family 1
-[ 0.616000] Unpacking initramfs...
-[ 1.220000] workingset: timestamp_bits=62 max_order=19 bucket_order=0
-[ 1.244000] io scheduler noop registered
-[ 1.244000] io scheduler cfq registered (default)
-[ 1.244000] io scheduler mq-deadline registered
-[ 1.248000] io scheduler kyber registered
-[ 1.360000] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[ 1.368000] console [ttyS0] disabled
-[ 1.372000] f0300000.serial: ttyS0 at MMIO 0xf0300020 (irq = 10, base_baud = 1228800) is a 16550A
-[ 1.392000] console [ttyS0] enabled
-[ 1.392000] ftmac100: Loading version 0.2 ...
-[ 1.396000] ftmac100 e0100000.mac eth0: irq 8, mapped at ffffffd002005000
-[ 1.400000] ftmac100 e0100000.mac eth0: generated random MAC address 6e:ac:c3:92:36:c0
-[ 1.404000] IR NEC protocol handler initialized
-[ 1.404000] IR RC5(x/sz) protocol handler initialized
-[ 1.404000] IR RC6 protocol handler initialized
-[ 1.404000] IR JVC protocol handler initialized
-[ 1.408000] IR Sony protocol handler initialized
-[ 1.408000] IR SANYO protocol handler initialized
-[ 1.408000] IR Sharp protocol handler initialized
-[ 1.408000] IR MCE Keyboard/mouse protocol handler initialized
-[ 1.412000] IR XMP protocol handler initialized
-[ 1.456000] ftsdc010 f0e00000.mmc: mmc0 - using hw SDIO IRQ
-[ 1.464000] bootconsole [early0] uses init memory and must be disabled even before the real one is ready
-[ 1.464000] bootconsole [early0] disabled
-[ 1.508000] Freeing unused kernel memory: 12076K
-[ 1.512000] This architecture does not have kernel memory protection.
-[ 1.520000] mmc0: new SD card at address 4567
-[ 1.524000] mmcblk0: mmc0:4567 QEMU! 20.0 MiB
-[ 1.844000] mmcblk0:
-Wed Dec 1 10:00:00 CST 2010
-/ #
-
-
-
-TODO
-==================================================
-Boot bbl and riscv-linux via U-Boot on AE350 board
diff --git a/doc/README.ag101p b/doc/README.ag101p
deleted file mode 100644
index 8fc0ac5..0000000
--- a/doc/README.ag101p
+++ /dev/null
@@ -1,36 +0,0 @@
-Andes Technology SoC AG101P
-===========================
-
-AG101P is the mainline SoC produced by Andes Technology using N1213 CPU core
-with FPU and DDR contoller support.
-AG101P has integrated both AHB and APB bus and many periphals for application
-and product development.
-
-ADP-AG101P
-=========
-
-ADP-AG101P is the SoC with AG101 hardcore CPU.
-
-Configurations
-==============
-
-CONFIG_MEM_REMAP:
- Doing memory remap is essential for preparing some non-OS or RTOS
- applications.
-
-CONFIG_SKIP_LOWLEVEL_INIT:
- If you want to boot this system from SPI ROM and bypass e-bios (the
- other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT
- in "include/configs/adp-ag101p.h".
-
-Build and boot steps
-====================
-
-build:
-1. Prepare the toolchains and make sure the $PATH to toolchains is correct.
-2. Use `make adp-ag101p_defconfig` in u-boot root to build the image.
-
-Burn u-boot to SPI ROM:
-====================
-
-This section will be added later.
diff --git a/doc/README.arm64 b/doc/README.arm64
deleted file mode 100644
index b0bba0f..0000000
--- a/doc/README.arm64
+++ /dev/null
@@ -1,56 +0,0 @@
-U-Boot for arm64
-
-Summary
-=======
-The initial arm64 U-Boot port was developed before hardware was available,
-so the first supported platforms were the Foundation and Fast Model for ARMv8.
-These days U-Boot runs on a variety of 64-bit capable ARM hardware, from
-embedded development boards to servers.
-
-Notes
-=====
-
-1. U-Boot can run at any exception level it is entered in, it is
- recommened to enter it in EL3 if U-Boot takes some responsibilities of a
- classical firmware (like initial hardware setup, CPU errata workarounds
- or SMP bringup). U-Boot can be entered in EL2 when its main purpose is
- that of a boot loader. It can drop to lower exception levels before
- entering the OS.
-
-2. U-Boot for arm64 is compiled with AArch64-gcc. AArch64-gcc
- use rela relocation format, a tool(tools/relocate-rela) by Scott Wood
- is used to encode the initial addend of rela to u-boot.bin. After running,
- the U-Boot will be relocated to destination again.
-
-3. Earlier Linux kernel versions required the FDT to be placed at a
- 2 MB boundary and within the same 512 MB section as the kernel image,
- resulting in fdt_high to be defined specially.
- Since kernel version 4.2 Linux is more relaxed about the DT location, so it
- can be placed anywhere in memory.
- Please reference linux/Documentation/arm64/booting.txt for detail.
-
-4. Spin-table is used to wake up secondary processors. One location
- (or per processor location) is defined to hold the kernel entry point
- for secondary processors. It must be ensured that the location is
- accessible and zero immediately after secondary processor
- enter slave_cpu branch execution in start.S. The location address
- is encoded in cpu node of DTS. Linux kernel store the entry point
- of secondary processors to it and send event to wakeup secondary
- processors.
- Please reference linux/Documentation/arm64/booting.txt for detail.
-
-5. Generic board is supported.
-
-6. CONFIG_ARM64 instead of CONFIG_ARMV8 is used to distinguish aarch64 and
- aarch32 specific codes.
-
-
-Contributors
-============
- Tom Rini <trini@ti.com>
- Scott Wood <scottwood@freescale.com>
- York Sun <yorksun@freescale.com>
- Simon Glass <sjg@chromium.org>
- Sharma Bhupesh <bhupesh.sharma@freescale.com>
- Rob Herring <robherring2@gmail.com>
- Sergey Temerkhanov <s.temerkhanov@gmail.com>
diff --git a/doc/README.at91 b/doc/README.at91
deleted file mode 100644
index 39dd563..0000000
--- a/doc/README.at91
+++ /dev/null
@@ -1,174 +0,0 @@
-Atmel AT91 Evaluation kits
-
-Index
- - I. Board mapping & boot media
- - II. NAND partition table
- - III. watchdog support
-
-I. Board mapping & boot media
-------------------------------------------------------------------------------
-AT91SAM9260EK, AT91SAM9G20EK & AT91SAM9XEEK
-------------------------------------------------------------------------------
-
-Memory map
- 0x20000000 - 23FFFFFF SDRAM (64 MB)
- 0xC0000000 - Cxxxxxxx Atmel Dataflash card (J13)
- 0xD0000000 - D07FFFFF Soldered Atmel Dataflash (AT45DB642)
-
-Environment variables
-
- U-Boot environment variables can be stored at different places:
- - Dataflash on SPI chip select 1 (default)
- - Dataflash on SPI chip select 0 (dataflash card)
- - Nand flash.
-
- You can choose your storage location at config step (here for at91sam9260ek) :
- make at91sam9260ek_nandflash_config - use nand flash
- make at91sam9260ek_dataflash_cs0_config - use data flash (spi cs0)
- make at91sam9260ek_dataflash_cs1_config - use data flash (spi cs1)
-
-
-------------------------------------------------------------------------------
-AT91SAM9261EK, AT91SAM9G10EK
-------------------------------------------------------------------------------
-
-Memory map
- 0x20000000 - 23FFFFFF SDRAM (64 MB)
- 0xC0000000 - C07FFFFF Soldered Atmel Dataflash (AT45DB642)
- 0xD0000000 - Dxxxxxxx Atmel Dataflash card (J22)
-
-Environment variables
-
- U-Boot environment variables can be stored at different places:
- - Dataflash on SPI chip select 0 (default)
- - Dataflash on SPI chip select 3 (dataflash card)
- - Nand flash.
-
- You can choose your storage location at config step (here for at91sam9260ek) :
- make at91sam9261ek_nandflash_config - use nand flash
- make at91sam9261ek_dataflash_cs0_config - use data flash (spi cs0)
- make at91sam9261ek_dataflash_cs3_config - use data flash (spi cs3)
-
-
-------------------------------------------------------------------------------
-AT91SAM9263EK
-------------------------------------------------------------------------------
-
-Memory map
- 0x20000000 - 23FFFFFF SDRAM (64 MB)
- 0xC0000000 - Cxxxxxxx Atmel Dataflash card (J9)
-
-Environment variables
-
- U-Boot environment variables can be stored at different places:
- - Dataflash on SPI chip select 0 (dataflash card)
- - Nand flash.
- - Nor flash (not populate by default)
-
- You can choose your storage location at config step (here for at91sam9260ek) :
- make at91sam9263ek_nandflash_config - use nand flash
- make at91sam9263ek_dataflash_cs0_config - use data flash (spi cs0)
- make at91sam9263ek_norflash_config - use nor flash
-
- You can choose to boot directly from U-Boot at config step
- make at91sam9263ek_norflash_boot_config - boot from nor flash
-
-
-------------------------------------------------------------------------------
-AT91SAM9M10G45EK
-------------------------------------------------------------------------------
-
-Memory map
- 0x70000000 - 77FFFFFF SDRAM (128 MB)
-
-Environment variables
-
- U-Boot environment variables can be stored at different places:
- - Nand flash.
-
- You can choose your storage location at config step (here for at91sam9m10g45ek) :
- make at91sam9m10g45ek_nandflash_config - use nand flash
-
-
-------------------------------------------------------------------------------
-AT91SAM9RLEK
-------------------------------------------------------------------------------
-
-Memory map
- 0x20000000 - 23FFFFFF SDRAM (64 MB)
- 0xC0000000 - C07FFFFF Soldered Atmel Dataflash (AT45DB642)
-
-Environment variables
-
- U-Boot environment variables can be stored at different places:
- - Dataflash on SPI chip select 0
- - Nand flash.
-
- You can choose your storage location at config step (here for at91sam9rlek) :
- make at91sam9rlek_nandflash_config - use nand flash
-
-
-------------------------------------------------------------------------------
-AT91SAM9N12EK, AT91SAM9X5EK
-------------------------------------------------------------------------------
-
-Memory map
- 0x20000000 - 27FFFFFF SDRAM (128 MB)
-
-Environment variables
-
- U-Boot environment variables can be stored at different places:
- - Nand flash.
- - SD/MMC card
- - Serialflash/Dataflash on SPI chip select 0
-
- You can choose your storage location at config step (here for at91sam9x5ek) :
- make at91sam9x5ek_dataflash_config - use data flash
- make at91sam9x5ek_mmc_config - use sd/mmc card
- make at91sam9x5ek_nandflash_config - use nand flash
- make at91sam9x5ek_spiflash_config - use serial flash
-
-
-------------------------------------------------------------------------------
-SAMA5D3XEK
-------------------------------------------------------------------------------
-
-Memory map
- 0x20000000 - 3FFFFFFF SDRAM (512 MB)
-
-Environment variables
-
- U-Boot environment variables can be stored at different places:
- - Nand flash.
- - SD/MMC card
- - Serialflash on SPI chip select 0
-
- You can choose your storage location at config step (here for sama5d3xek) :
- make sama5d3xek_mmc_config - use SD/MMC card
- make sama5d3xek_nandflash_config - use nand flash
- make sama5d3xek_serialflash_config - use serial flash
-
-
-II. NAND partition table
-
- All the board support boot from NAND flash will use the following NAND
- partition table
-
- 0x00000000 - 0x0003FFFF bootstrap (256 KiB)
- 0x00040000 - 0x000BFFFF u-boot (512 KiB)
- 0x000C0000 - 0x000FFFFF env (256 KiB)
- 0x00100000 - 0x0013FFFF env_redundant (256 KiB)
- 0x00140000 - 0x0017FFFF spare (256 KiB)
- 0x00180000 - 0x001FFFFF dtb (512 KiB)
- 0x00200000 - 0x007FFFFF kernel (6 MiB)
- 0x00800000 - 0xxxxxxxxx rootfs (All left)
-
-III. Watchdog support
-
- For security reasons, the at91 watchdog is running at boot time and,
- if deactivated, cannot be used anymore.
- If you want to use the watchdog, you will need to keep it running in
- your code (make sure not to disable it in AT91Bootstrap for instance).
-
- In the U-Boot configuration, the AT91 watchdog support is enabled using
- the CONFIG_WDT and CONFIG_WDT_AT91 options.
diff --git a/doc/README.autoboot b/doc/README.autoboot
index eeb7e4c..5e9a5e1 100644
--- a/doc/README.autoboot
+++ b/doc/README.autoboot
@@ -132,8 +132,31 @@
provides an escape sequence from the limited "password"
strings.
+ CONFIG_AUTOBOOT_ENCRYPTION
+
+ "bootstopkeysha256" environment variable
+
+ - Hash value of the input which unlocks the device and
+ stops autoboot.
+
+ This option allows a string to be entered into U-Boot to stop the
+ autoboot. The string itself is hashed and compared against the hash
+ in the environment variable 'bootstopkeysha256'. If it matches then
+ boot stops and a command-line prompt is presented.
+
+ This provides a way to ship a secure production device which can also
+ be accessed at the U-Boot command line.
+
CONFIG_RESET_TO_RETRY
(Only effective when CONFIG_BOOT_RETRY_TIME is also set)
After the countdown timed out, the board will be reset to restart
again.
+
+ CONFIG_AUTOBOOT_USE_MENUKEY
+ CONFIG_AUTOBOOT_MENUKEY
+
+ If this key is pressed to stop autoboot, then the commands in the
+ environment variable 'menucmd' will be executed before boot starts.
+ For example, 33 means "!" in ASCII, so pressing ! at boot would take
+ this action.
diff --git a/doc/README.b4860qds b/doc/README.b4860qds
deleted file mode 100644
index 889c8a9..0000000
--- a/doc/README.b4860qds
+++ /dev/null
@@ -1,366 +0,0 @@
-Overview
---------
-The B4860QDS is a Freescale reference board that hosts the B4860 SoC (and variants).
-
-B4860 Overview
--------------
-The B4860 QorIQ Qonverge device is a Freescale high-end, multicore SoC based on
-StarCore and Power Architecture® cores. It targets the broadband wireless
-infrastructure and builds upon the proven success of the existing multicore
-DSPs and Power CPUs. It is designed to bolster the rapidly changing and
-expanding wireless markets, such as 3GLTE (FDD and TDD), LTE-Advanced, and UMTS.
-
-The B4860 is a highly-integrated StarCore and Power Architecture processor that
-contains:
-. Six fully-programmable StarCore SC3900 FVP subsystems, divided into three
-clusters-each core runs up to 1.2 GHz, with an architecture highly optimized for
-wireless base station applications
-. Four dual-thread e6500 Power Architecture processors organized in one cluster-each
-core runs up to 1.8 GHz
-. Two DDR3/3L controllers for high-speed, industry-standard memory interface each
-runs at up to 1866.67 MHz
-. MAPLE-B3 hardware acceleration-for forward error correction schemes including
-Turbo or Viterbi decoding, Turbo encoding and rate matching, MIMO MMSE
-equalization scheme, matrix operations, CRC insertion and check, DFT/iDFT and
-FFT/iFFT calculations, PUSCH/PDSCH acceleration, and UMTS chip rate
-acceleration
-. CoreNet fabric that fully supports coherency using MESI protocol between the
- e6500 cores, SC3900 FVP cores, memories and external interfaces.
- CoreNet fabric interconnect runs at 667 MHz and supports coherent and
- non-coherent out of order transactions with prioritization and bandwidth
- allocation amongst CoreNet endpoints.
-. Data Path Acceleration Architecture, which includes the following:
-. Frame Manager (FMan), which supports in-line packet parsing and general
- classification to enable policing and QoS-based packet distribution
-. Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading
- of queue management, task management, load distribution, flow ordering, buffer
- management, and allocation tasks from the cores
-. Security engine (SEC 5.3)-crypto-acceleration for protocols such as IPsec,
- SSL, and 802.16
-. RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and
- outbound). Supports types 5, 6 (outbound only)
-. Large internal cache memory with snooping and stashing capabilities for
- bandwidth saving and high utilization of processor elements. The 9856-Kbyte
- internal memory space includes the following:
-. 32 Kbyte L1 ICache per e6500/SC3900 core
-. 32 Kbyte L1 DCache per e6500/SC3900 core
-. 2048 Kbyte unified L2 cache for each SC3900 FVP cluster
-. 2048 Kbyte unified L2 cache for the e6500 cluster
-. Two 512 Kbyte shared L3 CoreNet platform caches (CPC)
-. Sixteen 10-GHz SerDes lanes serving:
-. Two Serial RapidIO interfaces.
- - Each supports up to 4 lanes and a total of up to 8 lanes
-. Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue-less
- antenna connection
-. Two 10-Gbit Ethernet controllers (10GEC)
-. Six 1G/2.5-Gbit Ethernet controllers for network communications
-. PCI Express controller
-. Debug (Aurora)
-. Two OCeaN DMAs
-. Various system peripherals
-. 182 32-bit timers
-
-B4860QDS Overview
-------------------
-- DDRC1: Ten separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s, ECC, 4 GB
- of memory in two ranks of 2 GB.
-- DDRC2: Five separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s, ECC, 2 GB
- of memory. Single rank.
-- SerDes 1 multiplexing: Two Vitesse (transmit and receive path) cross-point 16x16 switch
- VSC3316
-- SerDes 2 multiplexing: Two Vitesse (transmit and receive path) cross-point 8x8 switch VSC3308
-- USB 2.0 ULPI PHY USB3315 by SMSC supports USB port in host mode.
- B4860 UART port is available over USB-to-UART translator USB2SER or over RS232 flat cable.
-- A Vitesse dual SGMII phy VSC8662 links the B4860 SGMII lines to 2xRJ-45 copper connectors
- for Stand-alone mode and to the 1000Base-X over AMC MicroTCA connector ports 0 and 2 for
- AMC mode.
-- The B4860 configuration may be loaded from nine bits coded reset configuration reset source. The
- RCW source is set by appropriate DIP-switches:
-- 16-bit NOR Flash / PROMJet
-- QIXIS 8-bit NOR Flash Emulator
-- 8-bit NAND Flash
-- 24-bit SPI Flash
-- Long address I2C EEPROM
-- Available debug interfaces are:
- - On-board eCWTAP controller with ETH and USB I/F
- - JTAG/COP 16-pin header for any external TAP controller
- - External JTAG source over AMC to support B2B configuration
- - 70-pin Aurora debug connector
-- QIXIS (FPGA) logic:
- - 2 KB internal memory space including
-- IDT840NT4 clock synthesizer provides B4860 essential clocks : SYSCLK, DDRCLK1,2 and
- RTCCLK.
-- Two 8T49N222A SerDes ref clock devices support two SerDes port clock frequency - total four
- refclk, including CPRI clock scheme.
-
-B4420 Personality
---------------------
-
-B4420 Personality
---------------------
-B4420 is a reduced personality of B4860 with less core/clusters(both SC3900 and e6500), less DDR
-controllers, less serdes lanes, less SGMII interfaces and reduced target frequencies.
-
-Key differences between B4860 and B4420
-----------------------------------------
-
-B4420 has:
-1. Less e6500 cores: 1 cluster with 2 e6500 cores
-2. Less SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster.
-3. Single DDRC
-4. 2X 4 lane serdes
-5. 3 SGMII interfaces
-6. no sRIO
-7. no 10G
-
-B4860QDS Default Settings
--------------------------
-
-Switch Settings
-----------------
-
-SW1 OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0]
-SW2 ON ON ON ON ON ON OFF OFF
-SW3 OFF OFF OFF ON OFF OFF ON OFF
-SW5 OFF OFF OFF OFF OFF OFF ON ON
-
-Note: PCIe slots modes: All the PCIe devices work as Root Complex.
-Note: Boot location: NOR flash.
-
-SysClk/Core(e6500)/CCB/DDR/FMan/DDRCLK/StarCore/CPRI-Maple/eTVPE-Maple/ULB-Maple
-66MHz/1.6GHz/667MHz/1.6GHz data rate/667MHz/133MHz/1200MHz/500MHz/800MHz/667MHz
-
-a) NAND boot
- SW1 [1.1] = 0
- SW2 [1.1] = 1
- SW3 [1:4] = 0001
-b) NOR boot
- SW1 [1.1] = 1
- SW2 [1.1] = 0
- SW3 [1:4] = 1000.
-
-B4420QDS Default Settings
--------------------------
-
-Switch Settings
-----------------
-SW1 OFF[0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0]
-SW2 ON OFF ON OFF ON ON OFF OFF
-SW3 OFF OFF OFF ON OFF OFF ON OFF
-SW5 OFF OFF OFF OFF OFF OFF ON ON
-
-Note: PCIe slots modes: All the PCIe devices work as Root Complex.
-Note: Boot location: NOR flash.
-
-SysClk/Core(e6500)/CCB/DDR/FMan/DDRCLK/StarCore/CPRI-Maple/eTVPE-Maple/ULB-Maple
-66MHz/1.6GHz/667MHz/1.6GHz data rate/667MHz/133MHz/1200MHz/500MHz/800MHz/667MHz
-
-a) NAND boot
- SW1 [1.1] = 0
- SW2 [1.1] = 1
- SW3 [1:4] = 0001
-b) NOR boot
- SW1 [1.1] = 1
- SW2 [1.1] = 0
- SW3 [1:4] = 1000.
-
-Memory map on B4860QDS
-----------------------
-The addresses in brackets are physical addresses.
-
-Start Address End Address Description Size
-0xF_FFDF_1000 0xF_FFFF_FFFF Free 2 MB
-0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4 KB
-0xF_FF81_0000 0xF_FFDE_FFFF Free 5 MB
-0xF_FF80_0000 0xF_FF80_FFFF IFC NAND Flash 64 KB
-0xF_FF00_0000 0xF_FF7F_FFFF Free 8 MB
-0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16 MB
-0xF_F801_0000 0xF_FDFF_FFFF Free 95 MB
-0xF_F800_0000 0xF_F800_FFFF PCIe I/O Space 64 KB
-0xF_F600_0000 0xF_F7FF_FFFF QMAN s/w portal 32 MB
-0xF_F400_0000 0xF_F5FF_FFFF BMAN s/w portal 32 MB
-0xF_F000_0000 0xF_F3FF_FFFF Free 64 MB
-0xF_E800_0000 0xF_EFFF_FFFF IFC NOR Flash 128 MB
-0xF_E000_0000 0xF_E7FF_FFFF Promjet 128 MB
-0xF_A0C0_0000 0xF_DFFF_FFFF Free 1012 MB
-0xF_A000_0000 0xF_A0BF_FFFF MAPLE0/1/2 12 MB
-0xF_0040_0000 0xF_9FFF_FFFF Free 12 GB
-0xF_0000_0000 0xF_01FF_FFFF DCSR 32 MB
-0xC_4000_0000 0xE_FFFF_FFFF Free 11 GB
-0xC_3000_0000 0xC_3FFF_FFFF sRIO-2 I/O 256 MB
-0xC_2000_0000 0xC_2FFF_FFFF sRIO-1 I/O 256 MB
-0xC_0000_0000 0xC_1FFF_FFFF PCIe Mem Space 512 MB
-0x1_0000_0000 0xB_FFFF_FFFF Free 44 GB
-0x0_8000_0000 0x0_FFFF_FFFF DDRC1 2 GB
-0x0_0000_0000 0x0_7FFF_FFFF DDRC2 2 GB
-
-Memory map on B4420QDS
-----------------------
-The addresses in brackets are physical addresses.
-
-Start Address End Address Description Size
-0xF_FFDF_1000 0xF_FFFF_FFFF Free 2 MB
-0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4 KB
-0xF_FF81_0000 0xF_FFDE_FFFF Free 5 MB
-0xF_FF80_0000 0xF_FF80_FFFF IFC NAND Flash 64 KB
-0xF_FF00_0000 0xF_FF7F_FFFF Free 8 MB
-0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16 MB
-0xF_F801_0000 0xF_FDFF_FFFF Free 95 MB
-0xF_F800_0000 0xF_F800_FFFF PCIe I/O Space 64 KB
-0xF_F600_0000 0xF_F7FF_FFFF QMAN s/w portal 32 MB
-0xF_F400_0000 0xF_F5FF_FFFF BMAN s/w portal 32 MB
-0xF_F000_0000 0xF_F3FF_FFFF Free 64 MB
-0xF_E800_0000 0xF_EFFF_FFFF IFC NOR Flash 128 MB
-0xF_E000_0000 0xF_E7FF_FFFF Promjet 128 MB
-0xF_A0C0_0000 0xF_DFFF_FFFF Free 1012 MB
-0xF_A000_0000 0xF_A0BF_FFFF MAPLE0/1/2 12 MB
-0xF_0040_0000 0xF_9FFF_FFFF Free 12 GB
-0xF_0000_0000 0xF_01FF_FFFF DCSR 32 MB
-0xC_4000_0000 0xE_FFFF_FFFF Free 11 GB
-0xC_3000_0000 0xC_3FFF_FFFF sRIO-2 I/O 256 MB
-0xC_2000_0000 0xC_2FFF_FFFF sRIO-1 I/O 256 MB
-0xC_0000_0000 0xC_1FFF_FFFF PCIe Mem Space 512 MB
-0x1_0000_0000 0xB_FFFF_FFFF Free 44 GB
-0x0_0000_0000 0x0_FFFF_FFFF DDRC1 4 GB
-
-
-NOR Flash memory Map on B4860 and B4420QDS
-------------------------------------------
- Start End Definition Size
-0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB
-0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB
-0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
-0xEF300000 0xEFEFFFFF rootfs (alternate bank) 12MB
-0xEE800000 0xEE8FFFFF device tree (alternate bank) 1MB
-0xEE020000 0xEE6FFFFF Linux.uImage (alternate bank) 6MB+896KB
-0xEE000000 0xEE01FFFF RCW (alternate bank) 128KB
-0xEDF40000 0xEDFFFFFF U-Boot (alternate bank) 768KB
-0xEDF20000 0xEDF3FFFF U-Boot env (alternate bank) 128KB
-0xEDF00000 0xEDF1FFFF FMAN ucode (alternate bank) 128KB
-0xED300000 0xEDEFFFFF rootfs (current bank) 12MB
-0xEC800000 0xEC8FFFFF device tree (current bank) 1MB
-0xEC020000 0xEC6FFFFF Linux.uImage (current bank) 6MB+896KB
-0xEC000000 0xEC01FFFF RCW (current bank) 128KB
-
-Various Software configurations/environment variables/commands
---------------------------------------------------------------
-The below commands apply to both B4860QDS and B4420QDS.
-
-1. U-Boot environment variable hwconfig
- The default hwconfig is:
- hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1:
- dr_mode=host,phy_type=ulpi
- Note: For USB gadget set "dr_mode=peripheral"
-
-2. FMAN Ucode versions
- fsl_fman_ucode_B4860_106_3_6.bin
-
-3. Switching to alternate bank
- Commands for switching to alternate bank.
-
- 1. To change from vbank0 to vbank2
- => qixis_reset altbank (it will boot using vbank2)
-
- 2.To change from vbank2 to vbank0
- => qixis reset (it will boot using vbank0)
-
-4. To change personality of board
- For changing personality from B4860 to B4420
- 1)Boot from vbank0
- 2)Flash vbank2 with b4420 rcw and U-Boot
- 3)Give following commands to uboot prompt
- => mw.b ffdf0040 0x30;
- => mw.b ffdf0010 0x00;
- => mw.b ffdf0062 0x02;
- => mw.b ffdf0050 0x02;
- => mw.b ffdf0010 0x30;
- => reset
-
- Note: Power off cycle will lead to default switch settings.
- Note: 0xffdf0000 is the address of the QIXIS FPGA.
-
-5. Switching between NOR and NAND boot(RCW src changed from NOR <-> NAND)
-
- To change from NOR to NAND boot give following command on uboot prompt
- => mw.b ffdf0040 0x30
- => mw.b ffdf0010 0x00
- => mw.b 0xffdf0050 0x08
- => mw.b 0xffdf0060 0x82
- => mw.b ffdf0061 0x00
- => mw.b ffdf0010 0x30
- => reset
-
- To change from NAND to NOR boot give following command on uboot prompt:
- => mw.b ffdf0040 0x30
- => mw.b ffdf0010 0x00
- => mw.b 0xffdf0050 0x00(for vbank0) or (mw.b 0xffdf0050 0x02 for vbank2)
- => mw.b 0xffdf0060 0x12
- => mw.b ffdf0061 0x01
- => mw.b ffdf0010 0x30
- => reset
-
- Note: Power off cycle will lead to default switch settings.
- Note: 0xffdf0000 is the address of the QIXIS FPGA.
-
-6. Ethernet interfaces for B4860QDS
- Serdes protocosl tested:
- 0x2a, 0x8d (serdes1, serdes2) [DEFAULT]
- 0x2a, 0xb2 (serdes1, serdes2)
-
- When using [DEFAULT] RCW, which including 2 * 1G SGMII on board and 2 * 1G
- SGMII on SGMII riser card.
- Under U-Boot these network interfaces are recognized as:
- FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5 and FM1@DTSEC6.
-
- On Linux the interfaces are renamed as:
- . eth2 -> fm1-gb2
- . eth3 -> fm1-gb3
- . eth4 -> fm1-gb4
- . eth5 -> fm1-gb5
-
-7. RCW and Ethernet interfaces for B4420QDS
- Serdes protocosl tested:
- 0x18, 0x9e (serdes1, serdes2)
-
- Under U-Boot these network interfaces are recognized as:
- FM1@DTSEC3, FM1@DTSEC4 and e1000#0.
-
- On Linux the interfaces are renamed as:
- . eth2 -> fm1-gb2
- . eth3 -> fm1-gb3
-
-NAND boot with 2 Stage boot loader
-----------------------------------
-PBL initialise the internal SRAM and copy SPL(160KB) in SRAM.
-SPL further initialise DDR using SPD and environment variables and copy
-U-Boot(768 KB) from flash to DDR.
-Finally SPL transer control to U-Boot for futher booting.
-
-SPL has following features:
- - Executes within 256K
- - No relocation required
-
- Run time view of SPL framework during boot :-
- -----------------------------------------------
- Area | Address |
------------------------------------------------
- Secure boot | 0xFFFC0000 (32KB) |
- headers | |
- -----------------------------------------------
- GD, BD | 0xFFFC8000 (4KB) |
- -----------------------------------------------
- ENV | 0xFFFC9000 (8KB) |
- -----------------------------------------------
- HEAP | 0xFFFCB000 (30KB) |
- -----------------------------------------------
- STACK | 0xFFFD8000 (22KB) |
- -----------------------------------------------
- U-Boot SPL | 0xFFFD8000 (160KB) |
- -----------------------------------------------
-
-NAND Flash memory Map on B4860 and B4420QDS
-------------------------------------------
- Start End Definition Size
-0x000000 0x0FFFFF U-Boot 1MB
-0x140000 0x15FFFF U-Boot env 128KB
-0x1A0000 0x1BFFFF FMAN Ucode 128KB
diff --git a/doc/README.blackfin b/doc/README.blackfin
deleted file mode 100644
index a837d90..0000000
--- a/doc/README.blackfin
+++ /dev/null
@@ -1,46 +0,0 @@
-Notes for the Blackfin architecture port of Das U-Boot
-
- =========
- ! ABOUT !
- =========
-
-<marketing blurb>
-Blackfin Processors embody a new breed of 16/32-bit embedded processor, ideally
-suited for products where a convergence of capabilities are necessary -
-multi-format audio, video, voice and image processing; multi-mode baseband and
-packet processing; control processing; and real-time security. The Blackfin's
-unique combination of software flexibility and scalability has gained it
-widespread adoption in convergent applications.
-</marketing blurb>
-
-The Blackfin processor is wholly developed by Analog Devices Inc.
-
- ===========
- ! SUPPORT !
- ===========
-
-All open source code for the Blackfin processors are being handled via our
-collaborative website:
-http://blackfin.uclinux.org/
-
-In particular, bug reports, feature requests, help etc... for Das U-Boot are
-handled in the Das U-Boot sub project:
-http://blackfin.uclinux.org/gf/project/u-boot
-
-This website is backed both by an open source community as well as a dedicated
-team from Analog Devices Inc.
-
- =============
- ! TOOLCHAIN !
- =============
-
-To compile the Blackfin aspects, you'll need the GNU toolchain configured for
-the Blackfin processor. You can obtain such a cross-compiler here:
-http://blackfin.uclinux.org/gf/project/toolchain
-
- =================
- ! DOCUMENTATION !
- =================
-
-For Blackfin specific documentation, you can visit our dedicated doc wiki:
-http://docs.blackfin.uclinux.org/doku.php?id=bootloaders:u-boot
diff --git a/doc/README.bootmenu b/doc/README.bootmenu
index 34ff8d5..ca50990 100644
--- a/doc/README.bootmenu
+++ b/doc/README.bootmenu
@@ -91,7 +91,7 @@
#define CONFIG_AUTOBOOT_KEYED
#define CONFIG_BOOTDELAY 30
- #define CONFIG_MENU_SHOW
+ #define CONFIG_AUTOBOOT_MENU_SHOW
When you intend to use the bootmenu on color frame buffer console,
make sure to additionally define CONFIG_CFB_CONSOLE_ANSI in the
diff --git a/doc/README.chromium b/doc/README.chromium
index 096bc4f..8f67da6 100644
--- a/doc/README.chromium
+++ b/doc/README.chromium
@@ -33,12 +33,18 @@
cd u-boot
git checkout cros-master
+ cd ..
+ git clone https://chromium.googlesource.com/chromiumos/platform/vboot_reference
+ cd vboot_reference
+ git checkout 45964294
+ # futility: updater: Correct output version for Snow
+
To build for sandbox:
UB=/tmp/b/chromeos_sandbox # U-Boot build directory
- CROS=/home/sglass/cosarm # Chromium OS directory
- make O=$UB/chromeos_sandbox_defconfig
- make O=$UB -j20 -s VBOOT_SOURCE=$CROS/src/platform/vboot_reference \
+ cd u-boot
+ make O=$UB chromeos_sandbox_defconfig
+ make O=$UB -j20 -s VBOOT_SOURCE=/path/to/vboot_reference \
MAKEFLAGS_VBOOT=DEBUG=1 QUIET=1
Replace sandbox with another supported target.
diff --git a/doc/README.falcon b/doc/README.falcon
index 9a7f0bc..713d706 100644
--- a/doc/README.falcon
+++ b/doc/README.falcon
@@ -67,6 +67,8 @@
CONFIG_CMD_SPL_NAND_OFS Offset in NAND where the parameters area was saved.
+CONFIG_CMD_SPL_NOR_OFS Offset in NOR where the parameters area was saved.
+
CONFIG_CMD_SPL_WRITE_SIZE Size of the parameters area to be copied
CONFIG_SPL_OS_BOOT Activate Falcon Mode.
diff --git a/doc/README.gpt b/doc/README.gpt
index 62013a3..facd7af 100644
--- a/doc/README.gpt
+++ b/doc/README.gpt
@@ -229,7 +229,7 @@
The GPT functionality may be tested with the 'sandbox' board by
creating a disk image as described under 'Block Device Emulation' in
-board/sandbox/README.sandbox:
+doc/arch/index.rst:
=>host bind 0 ./disk.raw
=> gpt read host 0
diff --git a/doc/README.iscsi b/doc/README.iscsi
deleted file mode 100644
index 3a12438..0000000
--- a/doc/README.iscsi
+++ /dev/null
@@ -1,170 +0,0 @@
-# iSCSI booting with U-Boot and iPXE
-
-## Motivation
-
-U-Boot has only a reduced set of supported network protocols. The focus for
-network booting has been on UDP based protocols. A TCP stack and HTTP support
-are expected to be integrated in 2018 together with a wget command.
-
-For booting a diskless computer this leaves us with BOOTP or DHCP to get the
-address of a boot script. TFTP or NFS can be used to load the boot script, the
-operating system kernel and the initial file system (initrd).
-
-These protocols are insecure. The client cannot validate the authenticity
-of the contacted servers. And the server cannot verify the identity of the
-client.
-
-Furthermore the services providing the operating system loader or kernel are
-not the ones that the operating system typically will use. Especially in a SAN
-environment this makes updating the operating system a hassle. After installing
-a new kernel version the boot files have to be copied to the TFTP server
-directory.
-
-The HTTPS protocol provides certificate based validation of servers. Sensitive
-data like passwords can be securely transmitted.
-
-The iSCSI protocol is used for connecting storage attached networks. It
-provides mutual authentication using the CHAP protocol. It typically runs on
-a TCP transport.
-
-Thus a better solution than DHCP/TFTP/NFS boot would be to load a boot script
-via HTTPS and to download any other files needed for booting via iSCSI from the
-same target where the operating system is installed.
-
-An alternative to implementing these protocols in U-Boot is to use an existing
-software that can run on top of U-Boot. iPXE[1] is the "swiss army knife" of
-network booting. It supports both HTTPS and iSCSI. It has a scripting engine for
-fine grained control of the boot process and can provide a command shell.
-
-iPXE can be built as an EFI application (named snp.efi) which can be loaded and
-run by U-Boot.
-
-## Boot sequence
-
-U-Boot loads the EFI application iPXE snp.efi using the bootefi command. This
-application has network access via the simple network protocol offered by
-U-Boot.
-
-iPXE executes its internal script. This script may optionally chain load a
-secondary boot script via HTTPS or open a shell.
-
-For the further boot process iPXE connects to the iSCSI server. This includes
-the mutual authentication using the CHAP protocol. After the authentication iPXE
-has access to the iSCSI targets.
-
-For a selected iSCSI target iPXE sets up a handle with the block IO protocol. It
-uses the ConnectController boot service of U-Boot to request U-Boot to connect a
-file system driver. U-Boot reads from the iSCSI drive via the block IO protocol
-offered by iPXE. It creates the partition handles and installs the simple file
-protocol. Now iPXE can call the simple file protocol to load GRUB[2]. U-Boot
-uses the block IO protocol offered by iPXE to fulfill the request.
-
-Once GRUB is started it uses the same block IO protocol to load Linux. Via
-the EFI stub Linux is called as an EFI application::
-
- +--------+ +--------+
- | | Runs | |
- | U-Boot |========>| iPXE |
- | EFI | | snp.efi|
- +--------+ | | DHCP | |
- | |<===|********|<========| |
- | DHCP | | | Get IP | |
- | Server | | | Address | |
- | |===>|********|========>| |
- +--------+ | | Response| |
- | | | |
- | | | |
- +--------+ | | HTTPS | |
- | |<===|********|<========| |
- | HTTPS | | | Load | |
- | Server | | | Script | |
- | |===>|********|========>| |
- +--------+ | | | |
- | | | |
- | | | |
- +--------+ | | iSCSI | |
- | |<===|********|<========| |
- | iSCSI | | | Auth | |
- | Server |===>|********|========>| |
- | | | | | |
- | | | | Loads | |
- | |<===|********|<========| | +--------+
- | | | | GRUB | | Runs | |
- | |===>|********|========>| |======>| GRUB |
- | | | | | | | |
- | | | | | | | |
- | | | | | | Loads | |
- | |<===|********|<========|********|<======| | +--------+
- | | | | | | Linux | | Runs | |
- | |===>|********|========>|********|======>| |=====>| Linux |
- | | | | | | | | | |
- +--------+ +--------+ +--------+ +--------+ | |
- | |
- | |
- | ~ ~ ~ ~|
-
-## Security
-
-The iSCSI protocol is not encrypted. The traffic could be secured using IPsec
-but neither U-Boot nor iPXE does support this. So we should at least separate
-the iSCSI traffic from all other network traffic. This can be achieved using a
-virtual local area network (VLAN).
-
-## Configuration
-
-### iPXE
-
-For running iPXE on arm64 the bin-arm64-efi/snp.efi build target is needed::
-
- git clone http://git.ipxe.org/ipxe.git
- cd ipxe/src
- make bin-arm64-efi/snp.efi -j6 EMBED=myscript.ipxe
-
-The available commands for the boot script are documented at:
-
-http://ipxe.org/cmd
-
-Credentials are managed as environment variables. These are described here:
-
-http://ipxe.org/cfg
-
-iPXE by default will put the CPU to rest when waiting for input. U-Boot does
-not wake it up due to missing interrupt support. To avoid this behavior create
-file src/config/local/nap.h::
-
- /* nap.h */
- #undef NAP_EFIX86
- #undef NAP_EFIARM
- #define NAP_NULL
-
-The supported commands in iPXE are controlled by an include, too. Putting the
-following into src/config/local/general.h is sufficient for most use cases::
-
- /* general.h */
- #define NSLOOKUP_CMD /* Name resolution command */
- #define PING_CMD /* Ping command */
- #define NTP_CMD /* NTP commands */
- #define VLAN_CMD /* VLAN commands */
- #define IMAGE_EFI /* EFI image support */
- #define DOWNLOAD_PROTO_HTTPS /* Secure Hypertext Transfer Protocol */
- #define DOWNLOAD_PROTO_FTP /* File Transfer Protocol */
- #define DOWNLOAD_PROTO_NFS /* Network File System Protocol */
- #define DOWNLOAD_PROTO_FILE /* Local file system access */
-
-### Open-iSCSI
-
-When the root file system is on an iSCSI drive you should disable pings and set
-the replacement timer to a high value [3]:
-
- node.conn[0].timeo.noop_out_interval = 0
- node.conn[0].timeo.noop_out_timeout = 0
- node.session.timeo.replacement_timeout = 86400
-
-## Links
-
-* [1](https://ipxe.org) https://ipxe.org - iPXE open source boot firmware
-* [2](https://www.gnu.org/software/grub/) https://www.gnu.org/software/grub/ -
- GNU GRUB (Grand Unified Bootloader)
-* [3](https://github.com/open-iscsi/open-iscsi/blob/master/README)
- https://github.com/open-iscsi/open-iscsi/blob/master/README -
- Open-iSCSI README
diff --git a/doc/README.m68k b/doc/README.m68k
deleted file mode 100644
index f867ca1..0000000
--- a/doc/README.m68k
+++ /dev/null
@@ -1,150 +0,0 @@
-
-U-Boot for Motorola (or Freescale/NXP) ColdFire processors
-
-===============================================================================
-History
-
-November 02, 2017 Angelo Dureghello <angelo@sysam.it>
-August 08, 2005 Jens Scharsig <esw@bus-elektronik.de>
- MCF5282 implementation without preloader
-January 12, 2004 <josef.baumgartner@telex.de>
-===============================================================================
-
-
-This file contains status information for the port of U-Boot to the
-Motorola ColdFire series of CPUs.
-
-
-1. Overview
-
-The ColdFire instruction set is "assembly source" compatible but an evolution
-of the original 68000 instruction set. Some not much used instructions has
-been removed. The instructions are only 16, 32, or 48 bits long, a
-simplification compared to the 68000 series.
-
-Bernhard Kuhn ported U-Boot 0.4.0 to the Motorola ColdFire architecture.
-The patches of Bernhard support the MCF5272 and MCF5282. A great disadvantage
-of these patches was that they needed a pre-bootloader to start U-Boot.
-Because of this, a new port was created which no longer needs a first stage
-booter.
-
-Thanks mainly to Freescale but also to several other contributors, U-Boot now
-supports nearly the entire range of ColdFire processors and their related
-development boards.
-
-
-2. Supported CPU families
-
-Please "make menuconfig" with ARCH=m68k, or check arch/m68k/cpu to see the
-currently supported processor and families.
-
-
-3. Supported boards
-
-U-Boot supports actually more than 40 ColdFire based boards.
-Board configuration can be done trough include/configs/<boardname>.h but the
-current recommended method is to use the new and more friendly approach as
-the "make menuconfig" way, very similar to the Linux way.
-
-To know details as memory map, build targets, default setup, etc, of a
-specific board please check:
-
-include/configs/<boardname>.h
-and/or
-configs/<boardname>_defconfig
-
-It is possible to build all ColdFire boards in a single command-line command,
-from u-boot root directory, as:
-
-./tools/buildman/buildman m68k
-
-
-3.1. Build U-Boot for a specific board
-
-A bash script similar to the one below may be used:
-
-#!/bin/bash
-
-export CROSS_COMPILE=/opt/toolchains/m68k/gcc-4.9.0-nolibc/bin/m68k-linux-
-
-board=M5475DFE
-
-make distclean
-make ARCH=m68k ${board}_defconfig
-make ARCH=m68k KBUILD_VERBOSE=1
-
-
-4. Adopted toolchains
-
-Please check:
-https://www.denx.de/wiki/U-Boot/ColdFireNotes
-
-
-5. ColdFire specific configuration options/settings
-
-
-5.1. Configuration to use a pre-loader
-
-If U-Boot should be loaded to RAM and started by a pre-loader
-CONFIG_MONITOR_IS_IN_RAM must be defined. If it is defined the
-initial vector table and basic processor initialization will not
-be compiled in. The start address of U-Boot must be adjusted in
-the boards config header file (CONFIG_SYS_MONITOR_BASE) and Makefile
-(CONFIG_SYS_TEXT_BASE) to the load address.
-
-
-5.2 ColdFire CPU specific options/settings
-
-To specify a CPU model, some defines shoudl be used, i.e.:
-
-CONFIG_MCF52x2 -- defined for all MCF52x2 CPUs
-CONFIG_M5272 -- defined for all Motorola MCF5272 CPUs
-
-Other options, generally set inside include/configs/<boardname>.h, they may
-apply to one or more cpu for the ColdFire family:
-
-CONFIG_SYS_MBAR -- defines the base address of the MCF5272 configuration
- registers
-CONFIG_SYS_ENET_BD_BASE
- -- defines the base address of the FEC buffer descriptors
-CONFIG_SYS_SCR -- defines the contents of the System Configuration Register
-CONFIG_SYS_SPR -- defines the contents of the System Protection Register
-CONFIG_SYS_MFD -- defines the PLL Multiplication Factor Divider
- (see table 9-4 of MCF user manual)
-CONFIG_SYS_RFD -- defines the PLL Reduce Frequency Devider
- (see table 9-4 of MCF user manual)
-CONFIG_SYS_CSx_BASE
- -- defines the base address of chip select x
-CONFIG_SYS_CSx_SIZE
- -- defines the memory size (address range) of chip select x
-CONFIG_SYS_CSx_WIDTH
- -- defines the bus with of chip select x
-CONFIG_SYS_CSx_MASK
- -- defines the mask for the related chip select x
-CONFIG_SYS_CSx_RO
- -- if set to 0 chip select x is read/write else chip select
- is read only
-CONFIG_SYS_CSx_WS
- -- defines the number of wait states of chip select x
-CONFIG_SYS_CACHE_ICACR
-CONFIG_SYS_CACHE_DCACR
-CONFIG_SYS_CACHE_ACRX
- -- cache-related registers config
-CONFIG_SYS_SDRAM_BASE
-CONFIG_SYS_SDRAM_SIZE
-CONFIG_SYS_SDRAM_BASEX
-CONFIG_SYS_SDRAM_CFG1
-CONFIG_SYS_SDRAM_CFG2
-CONFIG_SYS_SDRAM_CTRL
-CONFIG_SYS_SDRAM_MODE
-CONFIG_SYS_SDRAM_EMOD
- -- SDRAM config for SDRAM controller-specific registers, please
- see arch/m68k/cpu/<specific_cpu>/start.S files to see how
- these options are used.
-CONFIG_MCFUART
- -- defines enabling of ColdFire UART driver
-CONFIG_SYS_UART_PORT
- -- defines the UART port to be used (only a single UART can be
- actually enabled)
-CONFIG_SYS_SBFHDR_SIZE
- -- size of the prepended SBF header, if any
diff --git a/doc/README.marubun-pcmcia b/doc/README.marubun-pcmcia
deleted file mode 100644
index 0a363b2..0000000
--- a/doc/README.marubun-pcmcia
+++ /dev/null
@@ -1,65 +0,0 @@
-
-U-Boot MARUBUN MR-SHPC-01 PCMCIA controller driver
- Last update 21/11/2007 by Nobuhiro Iwamatsu
-
-========================================================================================
-
-0. What's this?
- This driver supports MARUBUN MR-SHPC-01.
- url: http://www.marubun.co.jp/product/semicon/devices/qgc18e0000002n2z.html
- (Sorry Japanese only.)
-
- This chip is used with SuperH well, and adopted by the
- reference board.
- ex. * MS7750SE01
- * MS7722SE01
- * other
-
- This chip doesn't support CardBus.
-
-1. base source code
- The code is based on sources from the Linux kernel
- ( arch/sh/kernel/cf-enabler.c ).
-
-2. How to use
- The options you have to specify in the config file are (with the
- value for my board as an example):
-
- * CONFIG_MARUBUN_PCCARD
- If you want to use this device driver, should define CONFIG_MARUBUN_PCCARD.
- ex. #define CONFIG_MARUBUN_PCCARD
-
- * CONFIG_PCMCIA_SLOT_A
- Most devices have only one slot. You should define CONFIG_PCMCIA_SLOT_A .
- ex. #define CONFIG_PCMCIA_SLOT_A 1
-
- * CONFIG_SYS_MARUBUN_MRSHPC
- This is MR-SHPC-01 PCMCIA controller base address.
- You should do the setting matched to your environment.
- ex. #define CONFIG_SYS_MARUBUN_MRSHPC 0xb03fffe0
- ( for MS7722SE01 environment )
-
- * CONFIG_SYS_MARUBUN_MW1
- This is MR-SHPC-01 memory window base address.
- You should do the setting matched to your environment.
- ex. #define CONFIG_SYS_MARUBUN_MW1 0xb0400000
- ( for MS7722SE01 environment )
-
- * CONFIG_SYS_MARUBUN_MW1
- This is MR-SHPC-01 attribute window base address.
- You should do the setting matched to your environment.
- ex. #define CONFIG_SYS_MARUBUN_MW2 0xb0500000
- ( for MS7722SE01 environment )
-
- * CONFIG_SYS_MARUBUN_MW1
- This is MR-SHPC-01 I/O window base address.
- You should do the setting matched to your environment.
- ex. #define CONFIG_SYS_MARUBUN_IO 0xb0600000
- ( for MS7722SE01 environment )
-
-3. Other
- * Check Compact Flash only.
- * Maybe, NE2000 compatible NIC is sure to move.
-
-Copyright (c) 2007
- Nobuhiro Iwamatsu <iwamatsu@nigaur.org>
diff --git a/doc/README.menu b/doc/README.menu
index 450c6a8..0f3d741 100644
--- a/doc/README.menu
+++ b/doc/README.menu
@@ -14,7 +14,7 @@
the menu, and an opaque pointer to data controlled by the consumer.
If you want to show a menu, instead starting the shell, define
-CONFIG_MENU_SHOW. You have to code the int menu_show(int bootdelay)
+CONFIG_AUTOBOOT_MENU_SHOW. You have to code the int menu_show(int bootdelay)
function, which handle your menu. This function returns the remaining
bootdelay.
diff --git a/doc/README.mips b/doc/README.mips
deleted file mode 100644
index b28f628..0000000
--- a/doc/README.mips
+++ /dev/null
@@ -1,54 +0,0 @@
-
-Notes for the MIPS architecture port of U-Boot
-
-Toolchains
-----------
-
- http://www.denx.de/wiki/DULG/ELDK
- ELDK < DULG < DENX
-
- http://www.emdebian.org/crosstools.html
- Embedded Debian -- Cross-development toolchains
-
- http://buildroot.uclibc.org/
- Buildroot
-
-Known Issues
-------------
-
- * Cache incoherency issue caused by do_bootelf_exec() at cmd_elf.c
-
- Cache will be disabled before entering the loaded ELF image without
- writing back and invalidating cache lines. This leads to cache
- incoherency in most cases, unless the code gets loaded after U-Boot
- re-initializes the cache. The more common uImage 'bootm' command does
- not suffer this problem.
-
- [workaround] To avoid this cache incoherency,
- 1) insert flush_cache(all) before calling dcache_disable(), or
- 2) fix dcache_disable() to do both flushing and disabling cache.
-
- * Note that Linux users need to kill dcache_disable() in do_bootelf_exec()
- or override do_bootelf_exec() not to disable I-/D-caches, because most
- Linux/MIPS ports don't re-enable caches after entering kernel_entry.
-
-TODOs
------
-
- * Probe CPU types, I-/D-cache and TLB size etc. automatically
-
- * Secondary cache support missing
-
- * Initialize TLB entries redardless of their use
-
- * R2000/R3000 class parts are not supported
-
- * Limited testing across different MIPS variants
-
- * Due to cache initialization issues, the DRAM on board must be
- initialized in board specific assembler language before the cache init
- code is run -- that is, initialize the DRAM in lowlevel_init().
-
- * centralize/share more CPU code of MIPS32, MIPS64 and XBurst
-
- * support Qemu Malta
diff --git a/doc/README.ne2000 b/doc/README.ne2000
index d5ae9a9..0f6a2e0 100644
--- a/doc/README.ne2000
+++ b/doc/README.ne2000
@@ -21,17 +21,6 @@
- Address where the board is mapped
-#define CONFIG_DRIVER_NE2000_CCR (0x28000000+0x3f8)
-
-- Address of the CCR (card configuration register). It could be found
-by enabling DEBUG in cmd_pcmcia.c. If this is not defined nothing is
-done as far as PCMCIA support is concerned.
-
-#define CONFIG_DRIVER_NE2000_VAL (0x20)
-
-- The value to be written in the CCR. It selects among different I/O
-spaces that could be used by the card.
-
Enjoy!
diff --git a/doc/README.nios2 b/doc/README.nios2
deleted file mode 100644
index 46c704e..0000000
--- a/doc/README.nios2
+++ /dev/null
@@ -1,95 +0,0 @@
-Nios II is a 32-bit embedded-processor architecture designed
-specifically for the Altera family of FPGAs.
-
-Please refer to the link for more information on Nios II,
-https://www.altera.com/products/processors/overview.html
-
-Please refer to the link for Linux port and toolchains,
-http://rocketboards.org/foswiki/view/Documentation/NiosIILinuxUserManual
-
-The Nios II port of u-boot is controlled by device tree. Please check
-out doc/README.fdt-control.
-
-To add a new board/configuration (eg, mysystem) to u-boot, you will need
-three files.
-
-1. The device tree source which describes the hardware, dts file.
- arch/nios2/dts/mysystem.dts
-
-2. Default configuration of Kconfig, defconfig file.
- configs/mysystem_defconfig
-
-3. The legacy board header file.
- include/configs/mysystem.h
-
-The device tree source must be generated from your qsys/sopc design
-using the sopc2dts tool. Then modified to fit your configuration. Please
-find the sopc2dts download and usage at the wiki,
-http://www.alterawiki.com/wiki/Sopc2dts
-
-$ java -jar sopc2dts.jar --force-altr -i mysystem.sopcinfo -o mysystem.dts
-
-You will need to add additional properties to the dts. Please find an
-example at, arch/nios2/dts/10m50_devboard.dts.
-
-1. Add "stdout-path=..." property with your serial path to the chosen
-node, like this,
- chosen {
- stdout-path = &uart_0;
- };
-
-2. If you use SPI/EPCS or I2C, you will need to add aliases to number
-the sequence of these devices, like this,
- aliases {
- spi0 = &epcs_controller;
- };
-
-Next, you will need a default config file. You may start with
-10m50_defconfig, modify the options and save it.
-
-$ make 10m50_defconfig
-$ make menuconfig
-$ make savedefconfig
-$ cp defconfig configs/mysystem_defconfig
-
-You will need to change the names of board header file and device tree,
-and select the drivers with menuconfig.
-
-Nios II architecture --->
- (mysystem) Board header file
-Device Tree Control --->
- (mysystem) Default Device Tree for DT control
-
-There is a selection of "Provider of DTB for DT control" in the Device
-Tree Control menu.
-
-( ) Separate DTB for DT control, will cat the dtb to end of u-boot
-binary, output u-boot-dtb.bin. This should be used for production.
-If you use boot copier, like EPCS boot copier, make sure the copier
-copies all the u-boot-dtb.bin, not just u-boot.bin.
-
-( ) Embedded DTB for DT control, will include the dtb inside the u-boot
-binary. This is handy for development, eg, using gdb or nios2-download.
-
-The last thing, legacy board header file describes those config options
-not covered in Kconfig yet. You may copy it from 10m50_devboard.h.
-
-$ cp include/configs/10m50_devboard.h include/configs/mysystem.h
-
-Please change the SDRAM base and size to match your board. The base
-should be cached virtual address, for Nios II with MMU it is 0xCxxx_xxxx
-to 0xDxxx_xxxx.
-
-#define CONFIG_SYS_SDRAM_BASE 0xc8000000
-#define CONFIG_SYS_SDRAM_SIZE 0x08000000
-
-You will need to change the environment variables location and setting,
-too. You may change other configs to fit your board.
-
-After all these changes, you may build and test.
-
-$ export CROSS_COMPILE=nios2-elf- (or nios2-linux-gnu-)
-$ make mysystem_defconfig
-$ make
-
-Enjoy!
diff --git a/doc/README.pcap b/doc/README.pcap
new file mode 100644
index 0000000..97b3e55
--- /dev/null
+++ b/doc/README.pcap
@@ -0,0 +1,62 @@
+PCAP:
+
+U-boot supports live Ethernet packet capture in PCAP(2.4) format.
+This is enabled by CONFIG_CMD_PCAP.
+
+The capture is stored on physical memory, and should be copied to
+a machine capable of parsing and displaying PCAP files (IE. wireshark)
+If networking works properly one can copy the capture file from physical memory
+using tftpput, or save it to local storage with (sf write, mmc write, fatwrite, etc)
+
+the pcap capturing requires maximum buffer size.
+when the buffer is full an error message will be displayed and then packets
+will silently drop.
+the actual capture file size is populate in the environment variable "pcapsize".
+
+Usage example:
+
+# Initialize pcap capture to physical address (0x100000) with maximum size of
+# 100000 bytes.
+
+# Start capture
+pcap start
+
+# Initialize network activity
+env set ipaddr 10.0.2.15; env set serverip 10.0.2.2; tftp uImage64
+
+# Stop capture
+pcap stop
+
+# pcap init 0x100000 100000
+PCAP capture initialized: addr: 0xffffffff80100000 max length: 100000
+
+# pcap start
+# env set ipaddr 10.0.2.15; env set serverip 10.0.2.2; tftp uImage64
+eth0@10000000: PHY present at 0
+eth0@10000000: link up, 1000Mbps full-duplex (lpa: 0x7c00)
+Using eth0@10000000 device
+TFTP from server 10.0.2.2; our IP address is 10.0.2.15
+Filename 'uImage64'.
+Load address: 0xffffffff88000000
+Loading: #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+!!! Buffer is full, consider increasing buffer size !!!
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #
+ 18.2 MiB/s
+done
+Bytes transferred = 8359376 (7f8dd0 hex)
+PCAP status:
+ Initialized addr: 0xffffffff80100000 max length: 100000
+ Status: Active. file size: 99991
+ Incoming packets: 66 Outgoing packets: 67
+
+# pcap stop
+# tftpput 0xffffffff80100000 $pcapsize 10.0.2.2:capture.pcap
+
diff --git a/doc/README.qemu-arm b/doc/README.qemu-arm
deleted file mode 100644
index e67bc13..0000000
--- a/doc/README.qemu-arm
+++ /dev/null
@@ -1,68 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2017, Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
-
-U-Boot on QEMU's 'virt' machine on ARM & AArch64
-================================================
-
-QEMU for ARM supports a special 'virt' machine designed for emulation and
-virtualization purposes. This document describes how to run U-Boot under it.
-Both 32-bit ARM and AArch64 are supported.
-
-The 'virt' platform provides the following as the basic functionality:
-
- - A freely configurable amount of CPU cores
- - U-Boot loaded and executing in the emulated flash at address 0x0
- - A generated device tree blob placed at the start of RAM
- - A freely configurable amount of RAM, described by the DTB
- - A PL011 serial port, discoverable via the DTB
- - An ARMv7/ARMv8 architected timer
- - PSCI for rebooting the system
- - A generic ECAM-based PCI host controller, discoverable via the DTB
-
-Additionally, a number of optional peripherals can be added to the PCI bus.
-
-Building U-Boot
----------------
-Set the CROSS_COMPILE environment variable as usual, and run:
-
-- For ARM:
- make qemu_arm_defconfig
- make
-
-- For AArch64:
- make qemu_arm64_defconfig
- make
-
-Running U-Boot
---------------
-The minimal QEMU command line to get U-Boot up and running is:
-
-- For ARM:
- qemu-system-arm -machine virt -bios u-boot.bin
-
-- For AArch64:
- qemu-system-aarch64 -machine virt -cpu cortex-a57 -bios u-boot.bin
-
-Note that for some odd reason qemu-system-aarch64 needs to be explicitly
-told to use a 64-bit CPU or it will boot in 32-bit mode.
-
-Additional persistent U-boot environment support can be added as follows:
-- Create envstore.img using qemu-img:
- qemu-img create -f raw envstore.img 64M
-- Add a pflash drive parameter to the command line:
- -drive if=pflash,format=raw,index=1,file=envstore.img
-
-Additional peripherals that have been tested to work in both U-Boot and Linux
-can be enabled with the following command line parameters:
-
-- To add a Serial ATA disk via an Intel ICH9 AHCI controller, pass e.g.:
- -drive if=none,file=disk.img,id=mydisk -device ich9-ahci,id=ahci -device ide-drive,drive=mydisk,bus=ahci.0
-- To add an Intel E1000 network adapter, pass e.g.:
- -netdev user,id=net0 -device e1000,netdev=net0
-- To add an EHCI-compliant USB host controller, pass e.g.:
- -device usb-ehci,id=ehci
-- To add a NVMe disk, pass e.g.:
- -drive if=none,file=disk.img,id=mydisk -device nvme,drive=mydisk,serial=foo
-
-These have been tested in QEMU 2.9.0 but should work in at least 2.5.0 as well.
diff --git a/doc/README.qemu-mips b/doc/README.qemu-mips
deleted file mode 100644
index 3940fac..0000000
--- a/doc/README.qemu-mips
+++ /dev/null
@@ -1,195 +0,0 @@
-By Vlad Lungu vlad.lungu@windriver.com 2007-Oct-01
-----------------------------------------
-Qemu is a full system emulator. See
-
-http://www.nongnu.org/qemu/
-
-Limitations & comments
-----------------------
-Supports the "-M mips" configuration of qemu: serial,NE2000,IDE.
-Supports little and big endian as well as 32 bit and 64 bit.
-Derived from au1x00 with a lot of things cut out.
-
-Supports emulated flash (patch Jean-Christophe PLAGNIOL-VILLARD) with
-recent qemu versions. When using emulated flash, launch with
--pflash <filename> and erase mips_bios.bin.
-
-
-Notes for the Qemu MIPS port
-----------------------------
-
-I) Example usage:
-
-Using u-boot.bin as ROM (replaces Qemu monitor):
-
-32 bit, big endian:
-# make qemu_mips
-# qemu-system-mips -M mips -bios u-boot.bin -nographic
-
-32 bit, little endian:
-# make qemu_mipsel
-# qemu-system-mipsel -M mips -bios u-boot.bin -nographic
-
-64 bit, big endian:
-# make qemu_mips64
-# qemu-system-mips64 -cpu MIPS64R2-generic -M mips -bios u-boot.bin -nographic
-
-64 bit, little endian:
-# make qemu_mips64el
-# qemu-system-mips64el -cpu MIPS64R2-generic -M mips -bios u-boot.bin -nographic
-
-or using u-boot.bin from emulated flash:
-
-if you use a qemu version after commit 4224
-
-create image:
-# dd of=flash bs=1k count=4k if=/dev/zero
-# dd of=flash bs=1k conv=notrunc if=u-boot.bin
-start it (see above):
-# qemu-system-mips[64][el] [-cpu MIPS64R2-generic] -M mips -pflash flash -nographic
-
-2) Download kernel + initrd
-
-On ftp://ftp.denx.de/pub/contrib/Jean-Christophe_Plagniol-Villard/qemu_mips/
-you can downland
-
-#config to build the kernel
-qemu_mips_defconfig
-#patch to fix mips interrupt init on 2.6.24.y kernel
-qemu_mips_kernel.patch
-initrd.gz
-vmlinux
-vmlinux.bin
-System.map
-
-4) Generate uImage
-
-# tools/mkimage -A mips -O linux -T kernel -C gzip -a 0x80010000 -e 0x80245650 -n "Linux 2.6.24.y" -d vmlinux.bin.gz uImage
-
-5) Copy uImage to Flash
-# dd if=uImage bs=1k conv=notrunc seek=224 of=flash
-
-6) Generate Ide Disk
-
-# dd of=ide bs=1k cout=100k if=/dev/zero
-
-# sfdisk -C 261 -d ide
-# partition table of ide
-unit: sectors
-
- ide1 : start= 63, size= 32067, Id=83
- ide2 : start= 32130, size= 32130, Id=83
- ide3 : start= 64260, size= 4128705, Id=83
- ide4 : start= 0, size= 0, Id= 0
-
-7) Copy to ide
-
-# dd if=uImage bs=512 conv=notrunc seek=63 of=ide
-
-8) Generate ext2 on part 2 on Copy uImage and initrd.gz
-
-# Attached as loop device ide offset = 32130 * 512
-# losetup -o 16450560 -f ide
-# Format as ext2 ( arg2 : nb blocks)
-# mke2fs /dev/loop0 16065
-# losetup -d /dev/loop0
-# Mount and copy uImage and initrd.gz to it
-# mount -o loop,offset=16450560 -t ext2 ide /mnt
-# mkdir /mnt/boot
-# cp {initrd.gz,uImage} /mnt/boot/
-# Umount it
-# umount /mnt
-
-9) Set Environment
-
-setenv rd_start 0x80800000
-setenv rd_size 2663940
-setenv kernel BFC38000
-setenv oad_addr 80500000
-setenv load_addr2 80F00000
-setenv kernel_flash BFC38000
-setenv load_addr_hello 80200000
-setenv bootargs 'root=/dev/ram0 init=/bin/sh'
-setenv load_rd_ext2 'ide res; ext2load ide 0:2 ${rd_start} /boot/initrd.gz'
-setenv load_rd_tftp 'tftp ${rd_start} /initrd.gz'
-setenv load_kernel_hda 'ide res; diskboot ${load_addr} 0:2'
-setenv load_kernel_ext2 'ide res; ext2load ide 0:2 ${load_addr} /boot/uImage'
-setenv load_kernel_tftp 'tftp ${load_addr} /qemu_mips/uImage'
-setenv boot_ext2_ext2 'run load_rd_ext2; run load_kernel_ext2; run addmisc; bootm ${load_addr}'
-setenv boot_ext2_flash 'run load_rd_ext2; run addmisc; bootm ${kernel_flash}'
-setenv boot_ext2_hda 'run load_rd_ext2; run load_kernel_hda; run addmisc; bootm ${load_addr}'
-setenv boot_ext2_tftp 'run load_rd_ext2; run load_kernel_tftp; run addmisc; bootm ${load_addr}'
-setenv boot_tftp_hda 'run load_rd_tftp; run load_kernel_hda; run addmisc; bootm ${load_addr}'
-setenv boot_tftp_ext2 'run load_rd_tftp; run load_kernel_ext2; run addmisc; bootm ${load_addr}'
-setenv boot_tftp_flash 'run load_rd_tftp; run addmisc; bootm ${kernel_flash}'
-setenv boot_tftp_tftp 'run load_rd_tftp; run load_kernel_tftp; run addmisc; bootm ${load_addr}'
-setenv load_hello_tftp 'tftp ${load_addr_hello} /examples/hello_world.bin'
-setenv go_tftp 'run load_hello_tftp; go ${load_addr_hello}'
-setenv addmisc 'setenv bootargs ${bootargs} console=ttyS0,${baudrate} rd_start=${rd_start} rd_size=${rd_size} ethaddr=${ethaddr}'
-setenv bootcmd 'run boot_tftp_flash'
-
-10) Now you can boot from flash, ide, ide+ext2 and tfp
-
-# qemu-system-mips -M mips -pflash flash -monitor null -nographic -net nic -net user -tftp `pwd` -hda ide
-
-II) How to debug U-Boot
-
-In order to debug U-Boot you need to start qemu with gdb server support (-s)
-and waiting the connection to start the CPU (-S)
-
-# qemu-system-mips -S -s -M mips -pflash flash -monitor null -nographic -net nic -net user -tftp `pwd` -hda ide
-
-in an other console you start gdb
-
-1) Debugging of U-Boot Before Relocation
-
-Before relocation, the addresses in the ELF file can be used without any problems
-by connecting to the gdb server localhost:1234
-
-# mipsel-unknown-linux-gnu-gdb u-boot
-GNU gdb 6.6
-Copyright (C) 2006 Free Software Foundation, Inc.
-GDB is free software, covered by the GNU General Public License, and you are
-welcome to change it and/or distribute copies of it under certain conditions.
-Type "show copying" to see the conditions.
-There is absolutely no warranty for GDB. Type "show warranty" for details.
-This GDB was configured as "--host=i486-linux-gnu --target=mipsel-unknown-linux-gnu"...
-(gdb) target remote localhost:1234
-Remote debugging using localhost:1234
-_start () at start.S:64
-64 RVECENT(reset,0) /* U-Boot entry point */
-Current language: auto; currently asm
-(gdb) b board.c:289
-Breakpoint 1 at 0xbfc00cc8: file board.c, line 289.
-(gdb) c
-Continuing.
-
-Breakpoint 1, board_init_f (bootflag=<value optimized out>) at board.c:290
-290 relocate_code (addr_sp, id, addr);
-Current language: auto; currently c
-(gdb) p/x addr
-$1 = 0x87fa0000
-
-2) Debugging of U-Boot After Relocation
-
-For debugging U-Boot after relocation we need to know the address to which
-U-Boot relocates itself to 0x87fa0000 by default.
-And replace the symbol table to this offset.
-
-(gdb) symbol-file
-Discard symbol table from `/private/u-boot-arm/u-boot'? (y or n) y
-Error in re-setting breakpoint 1:
-No symbol table is loaded. Use the "file" command.
-No symbol file now.
-(gdb) add-symbol-file u-boot 0x87fa0000
-add symbol table from file "u-boot" at
- .text_addr = 0x87fa0000
-(y or n) y
-Reading symbols from /private/u-boot-arm/u-boot...done.
-Breakpoint 1 at 0x87fa0cc8: file board.c, line 289.
-(gdb) c
-Continuing.
-
-Program received signal SIGINT, Interrupt.
-0xffffffff87fa0de4 in udelay (usec=<value optimized out>) at time.c:78
-78 while ((tmo - read_c0_count()) < 0x7fffffff)
diff --git a/doc/README.qemu-riscv b/doc/README.qemu-riscv
deleted file mode 100644
index e2e4804..0000000
--- a/doc/README.qemu-riscv
+++ /dev/null
@@ -1,46 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
-
-U-Boot on QEMU's 'virt' machine on RISC-V
-=========================================
-
-QEMU for RISC-V supports a special 'virt' machine designed for emulation and
-virtualization purposes. This document describes how to run U-Boot under it.
-Both 32-bit 64-bit targets are supported.
-
-The QEMU virt machine models a generic RISC-V virtual machine with support for
-the VirtIO standard networking and block storage devices. It has CLINT, PLIC,
-16550A UART devices in addition to VirtIO and it also uses device-tree to pass
-configuration information to guest software. It implements RISC-V privileged
-architecture spec v1.10.
-
-Building U-Boot
----------------
-Set the CROSS_COMPILE environment variable as usual, and run:
-
-- For 32-bit RISC-V:
- make qemu-riscv32_defconfig
- make
-
-- For 64-bit RISC-V:
- make qemu-riscv64_defconfig
- make
-
-Running U-Boot
---------------
-The minimal QEMU command line to get U-Boot up and running is:
-
-- For 32-bit RISC-V:
- qemu-system-riscv32 -nographic -machine virt -kernel u-boot
-
-- For 64-bit RISC-V:
- qemu-system-riscv64 -nographic -machine virt -kernel u-boot
-
-The commands above create targets with 128MiB memory by default.
-A freely configurable amount of RAM can be created via the '-m'
-parameter. For example, '-m 2G' creates 2GiB memory for the target,
-and the memory node in the embedded DTB created by QEMU reflects
-the new setting.
-
-These have been tested in QEMU 3.0.0.
diff --git a/doc/README.rockchip b/doc/README.rockchip
index 02e2497..d17afea 100644
--- a/doc/README.rockchip
+++ b/doc/README.rockchip
@@ -28,10 +28,9 @@
Building
========
-At present 12 RK3288 boards are supported:
+At present 11 RK3288 boards are supported:
- EVB RK3288 - use evb-rk3288 configuration
- - Fennec RK3288 - use fennec-rk3288 configuration
- Firefly RK3288 - use firefly-rk3288 configuration
- Hisense Chromebook - use chromebook_jerry configuration
- Asus C100P Chromebook - use chromebook_minnie configuration
@@ -123,10 +122,6 @@
Option 2: Package the image with SPL:
- - We need the Python elftools.elf.elffile library for make_fit_atf.py to work
-
- => sudo apt-get install python-pyelftools
-
- Export cross compiler path for aarch64
- Compile ATF
@@ -280,9 +275,7 @@
To write an image that boots from an SD card (assumed to be /dev/mmcblk0):
- ./tools/mkimage -n rk3288 -T rksd -d ./tpl/u-boot-tpl.bin out &&
- cat ./spl/u-boot-spl-dtb.bin >> out &&
- sudo dd if=out of=/dev/mmcblk0 seek=64 &&
+ sudo dd if=idbloader.img of=/dev/mmcblk0 seek=64 &&
sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 seek=16384
Booting from an SD card on RK3188
@@ -313,18 +306,7 @@
=================================================
For Rock64 rk3328 board the following three parts are required:
-TPL, SPL, and the u-boot image tree blob. While u-boot-spl.bin and
-u-boot.itb are to be compiled as usual, TPL is currently not
-implemented in u-boot, so you need to pick one from rkbin:
-
- - Get the rkbin
-
- => git clone https://github.com/rockchip-linux/rkbin.git
-
- - Create TPL/SPL image
-
- => tools/mkimage -n rk3328 -T rksd -d rkbin/bin/rk33/rk3328_ddr_333MHz_v1.16.bin idbloader.img
- => cat spl/u-boot-spl.bin >> idbloader.img
+TPL, SPL, and the u-boot image tree blob.
- Write TPL/SPL image at 64 sector
@@ -484,19 +466,9 @@
Option 3: Package the image with TPL:
- - Prefix rk3399 header to TPL image
-
- => cd /path/to/u-boot
- => ./tools/mkimage -n rk3399 -T rksd -d tpl/u-boot-tpl-dtb.bin out
-
- - Concatinate tpl with spl
-
- => cd /path/to/u-boot
- => cat ./spl/u-boot-spl-dtb.bin >> out
-
- Write tpl+spl at 64th sector
- => sudo dd if=out of=/dev/sdc seek=64
+ => sudo dd if=idbloader.img of=/dev/sdc seek=64
- Write U-Boot proper at 16384 sector
@@ -570,7 +542,7 @@
offset 128KB and the whole image is padded to 4MB which is the SPI flash size.
The position of U-Boot is controlled with this setting in U-Boot:
- #define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10)
+ #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
If you have a Dediprog em100pro connected then you can write the image with:
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index fc08734..24a6c1b 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -4,355 +4,8 @@
by unnoticed, but often build errors will result. If nobody cares any
more to resolve such problems, then the code is really dead and will
be removed from the U-Boot source tree. The remainders rest in peace
-in the imperishable depths of the git history. This document tries to
-maintain a list of such former fellows, so archaeologists can check
-easily if there is something they might want to dig for...
-The list should be sorted in reverse chronological order.
-
-
-Board Arch CPU Commit Removed Last known maintainer/contact
-=================================================================================================
-ocotea powerpc ppc4xx 29155e73 2015-10-27 Stefan Roese <sr@denx.de>
-taishan powerpc ppc4xx bb5553c6 2015-10-27 Stefan Roese <sr@denx.de>
-ebony powerpc ppc4xx 9d9e2f5d 2015-10-27 Stefan Roese <sr@denx.de>
-taihu powerpc ppc4xx 123b6cd7 2015-10-27 John Otken <jotken@softadvances.com>
-lcd4_lwmon5 powerpc ppc4xx b6b5e394 2015-10-02 Stefan Roese <sr@denx.de>
-da830evm arm arm926ejs d7e8b2b9 2015-09-12 Nick Thompson <nick.thompson@gefanuc.com>
-wireless_space arm arm926ejs b352182a 2015-09-12 Albert ARIBAUD <albert.u.boot@aribaud.net>
-stxgp3 powerpc mpc85xx 2ec69b88 2015-09-02 Dan Malek <dan@embeddedalley.com>
-stxssa powerpc mpc85xx 2ec69b88 2015-09-02 Dan Malek <dan@embeddedalley.com>
-cmi_mpc5xx powerpc mpc5xx 972f5320 2015-09-02
-zeus powerpc ppc4xx eb5d1dc7 2015-09-02 Stefan Roese <sr@denx.de>
-sbc405 powerpc ppc4xx 0e030593 2015-09-02
-pcs440ep powerpc ppc4xx 242836a8 2015-09-02 Stefan Roese <sr@denx.de>
-p3p440 powerpc ppc4xx c6999e5f 2015-09-02 Stefan Roese <sr@denx.de>
-csb272/csb472 powerpc ppc4xx 54a3f260 2015-09-02 Tolunay Orkun <torkun@nextio.com>
-alpr powerpc ppc4xx 0d2fc811 2015-09-02 Stefan Roese <sr@denx.de>
-balloon3 arm pxa 679d4456 2015-08-30 Marek Vasut <marex@denx.de>
-cpu9260_128M arm arm926ejs af7f884b 2015-08-30 Eric Benard <eric@eukrea.com>
-cpu9260 arm arm926ejs af7f884b 2015-08-30 Eric Benard <eric@eukrea.com>
-cpu9260_nand_128M arm arm926ejs af7f884b 2015-08-30 Eric Benard <eric@eukrea.com>
-cpu9260_nand arm arm926ejs af7f884b 2015-08-30 Eric Benard <eric@eukrea.com>
-cpu9G20_128M arm arm926ejs af7f884b 2015-08-30 Eric Benard <eric@eukrea.com>
-cpu9G20 arm arm926ejs af7f884b 2015-08-30 Eric Benard <eric@eukrea.com>
-cpuat91 arm arm920t af7f884b 2015-08-30 Eric Benard <eric@eukrea.com>
-cpuat91_ram arm arm920t af7f884b 2015-08-30 Eric Benard <eric@eukrea.com>
-davinci_dm355evm arm arm926ejs 6761946f 2015-08-30
-davinci_dm355leopard arm arm926ejs 6761946f 2015-08-30
-davinci_dm365evm arm arm926ejs 6761946f 2015-08-30
-davinci_dm6467evm arm arm926ejs 6761946f 2015-08-30
-davinci_dm6467Tevm arm arm926ejs 6761946f 2015-08-30
-davinci_dvevm arm arm926ejs 6761946f 2015-08-30
-davinci_schmoogie arm arm926ejs 6761946f 2015-08-30
-davinci_sffsdr arm arm926ejs 6761946f 2015-08-30
-davinci_sonata arm arm926ejs 6761946f 2015-08-30
-dig297 arm armv7 5ff33d04 2015-08-30 Luca Ceresoli <luca.ceresoli@comelit.it>
-ea20 arm arm926ejs 6761946f 2015-08-30
-eb_cpux9k2 arm arm920t 5522f12b 2015-08-30 Jens Scharsig <esw@bus-elektronik.de>
-eb_cpux9k2_ram arm arm920t 5522f12b 2015-08-30 Jens Scharsig <esw@bus-elektronik.de>
-enbw_cmc arm arm926ejs a6f7f787 2015-08-30 Heiko Schocher <hs@denx.de>
-ima3-mx53 arm armv7 3eb8f58d 2015-08-30
-imx27lite arm arm926ejs bc0840bc 2015-08-30 Wolfgang Denk <wd@denx.de>
-imx31_litekit arm arm1136 36d14178 2015-08-30
-jornada arm sa1100 df0b116d 2015-08-30 Kristoffer Ericson <kristoffer.ericson@gmail.com>
-lp8x4x arm pxa 9f840b8d 2015-08-30 Sergey Yanovich <ynvich@gmail.com>
-magnesium arm arm926ejs bc0840bc 2015-08-30 Heiko Schocher <hs@denx.de>
-mv88f6281gtw_ge arm arm926ejs 7cd768cf 2015-08-30 Prafulla Wadaskar <prafulla@marvell.com>
-mx51_efikamx arm armv7 b6073fd2 2015-08-30
-mx51_efikasb arm armv7 b6073fd2 2015-08-30
-nhk8815 arm arm926ejs 0abdd9d0 2015-08-30 Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>
-nhk8815_onenand arm arm926ejs 0abdd9d0 2015-08-30 Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>
-omap3_mvblx arm armv7 8dc372f9 2015-08-30 Michael Jones <michael.jones@matrix-vision.de>
-omap3_sdp3430 arm armv7 93b25c08 2015-08-30 Nishanth Menon <nm@ti.com>
-otc570 arm arm926ejs 819216dd 2015-08-30 Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
-otc570_dataflash arm arm926ejs 819216dd 2015-08-30 Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
-palmld arm pxa 35782e9c 2015-08-30 Marek Vasut <marex@denx.de>
-palmtc arm pxa 8896325d 2015-08-30 Marek Vasut <marex@denx.de>
-palmtreo680 arm pxa ad4f54ea 2015-08-30 Mike Dunn <mikedunn@newsguy.com>
-polaris arm pxa f6eac00a 2015-08-30 Stefano Babic <sbabic@denx.de>
-portuxg20 arm arm926ejs 79d19734 2015-08-30 Markus Hubig <mhubig@imko.de>
-pxa255_idp arm pxa 49d8899b 2015-08-30 Marek Vasut <marex@denx.de>
-qong arm arm1136 daf77086 2015-08-30 Wolfgang Denk <wd@denx.de>
-rd6281a arm arm926ejs 47b87d2e 2015-08-30 Prafulla Wadaskar <prafulla@marvell.com>
-scb9328 arm arm920t 7650beb7 2015-08-30 Torsten Koschorrek <koschorrek@synertronixx.de>
-snowball arm armv7 7495e41b 2015-08-30 Mathieu Poirier <mathieu.poirier@linaro.org>
-stamp9g20 arm arm926ejs 79d19734 2015-08-30 Markus Hubig <mhubig@imko.de>
-tk71 arm arm926ejs f73db66d 2015-08-30
-trizepsiv arm pxa f6eac00a 2015-08-30 Stefano Babic <sbabic@denx.de>
-tt01 arm arm1136 0c81f37d 2015-08-30 Helmut Raiger <helmut.raiger@hale.at>
-tx25 arm arm926ejs b9599dd8 2015-08-30 John Rigby <jcrigby@gmail.com>
-u8500_href arm armv7 7495e41b 2015-08-30
-versatileab arm arm926ejs b928e658 2015-08-30
-versatilepb arm arm926ejs b928e658 2015-08-30
-versatileqemu arm arm926ejs b928e658 2015-08-30
-vision2 arm armv7 bee2b99d 2015-08-30 Stefano Babic <sbabic@denx.de>
-vl_ma2sc arm arm926ejs 6e830dfc 2015-08-30 Jens Scharsig <esw@bus-elektronik.de>
-vl_ma2sc_ram arm arm926ejs 6e830dfc 2015-08-30 Jens Scharsig <esw@bus-elektronik.de>
-vpac270_nor_128 arm pxa 452ef830 2015-08-30 Marek Vasut <marex@denx.de>
-vpac270_nor_256 arm pxa 452ef830 2015-08-30 Marek Vasut <marex@denx.de>
-vpac270_ond_256 arm pxa 452ef830 2015-08-30 Marek Vasut <marex@denx.de>
-xaeniax arm pxa 1c87dd76 2015-08-30
-zipitz2 arm pxa 49d8899b 2015-08-30 Cliff Brake <cliff.brake@gmail.com>
-cam_enc_4xx arm arm926ejs 8d775763 2015-08-20 Heiko Schocher <hs@denx.de>
-afeb9260 arm arm926ejs f6b42c14 2015-05-13 Sergey Lapin <slapin@ossfans.org>
-tny_a9260 arm arm926ejs f6b42c14 2015-05-13 Albin Tonnerre <albin.tonnerre@free-electrons.com>
-sbc35_a9g20 arm arm926ejs f6b42c14 2015-05-13 Albin Tonnerre <albin.tonnerre@free-electrons.com>
-sc3 powerpc ppc4xx 27e72156 2015-05-10 Heiko Schocher <hs@denx.de>
-T4240EMU powerpc mpc85xx 7fc63cca 2015-05-05 York Sun <yorksun@freescale.com>
-korat powerpc ppc4xx 5043045d 2015-03-17 Larry Johnson <lrj@acm.org>
-W7OLMC powerpc ppc4xx 6beecd5d 2015-03-17 Erik Theisen <etheisen@mindspring.com>
-W7OLMG powerpc ppc4xx 6beecd5d 2015-03-17 Erik Theisen <etheisen@mindspring.com>
-JSE powerpc ppc4xx 2da8137b 2015-03-17 Stephen Williams <steve@icarus.com>
-hawkboard arm arm926ejs cb957cda 2015-02-24 Syed Mohammed Khasim <sm.khasim@gmail.com>:Sughosh Ganu <urwithsughosh@gmail.com>
-tnetv107x arm arm1176 50b82c4b 2015-02-24 Chan-Taek Park <c-park@ti.com>
-a320evb arm arm920t 29fc6f24 2015-02-24 Po-Yu Chuang <ratbert@faraday-tech.com>
-cm4008 arm arm920t a2f39e83 2015-02-24 Greg Ungerer <greg.ungerer@opengear.com>
-cm41xx arm arm920t a2f39e83 2015-02-24
-dkb arm arm926ejs 346cfba4 2015-02-24 Lei Wen <leiwen@marvell.com>
-jadecpu arm arm926ejs 41fbbbbc 2015-02-24 Matthias Weisser <weisserm@arcor.de>
-CATcenter powerpc ppc4xx 5344cc1a 2015-01-23
-PPChameleonEVB powerpc ppc4xx 5344cc1a 2015-01-23 Andrea "llandre" Marson <andrea.marson@dave-tech.it>
-P2020DS powerpc mpc85xx 168dcc6c 2015-01-23
-P2020COME powerpc mpc85xx 89123536 2015-01-23 Ira W. Snyder <iws@ovro.caltech.edu>
-P2020RDB powerpc mpc85xx 743d4815 2015-01-23 Poonam Aggrwal <poonam.aggrwal@freescale.com>
-P2010RDB powerpc mpc85xx 743d4815 2015-01-23
-P1020RDB powerpc mpc85xx 743d4815 2015-01-23
-P1011RDB powerpc mpc85xx 743d4815 2015-01-23
-MPC8360EMDS powerpc mpc83xx 8d1e3cb1 2015-01-23 Dave Liu <daveliu@freescale.com>
-MPC8360ERDK powerpc mpc83xx 8d1e3cb1 2015-01-23 Anton Vorontsov <avorontsov@ru.mvista.com>
-P3G4 powerpc 74xx_7xx d928664f 2015-01-16 Wolfgang Denk <wd@denx.de>
-ZUMA powerpc 74xx_7xx d928664f 2015-01-16 Nye Liu <nyet@zumanetworks.com>
-ppmc7xx powerpc 74xx_7xx d928664f 2015-01-16
-ELPPC powerpc 74xx_7xx d928664f 2015-01-16
-mpc7448hpc2 powerpc 74xx_7xx d928664f 2015-01-16 Roy Zang <tie-fei.zang@freescale.com>
-CPCI405 ppc4xx 405gp 5f1459dc 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
-CPCI405DT ppc4xx 405gpr 5f1459dc 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
-CPCI405AB ppc4xx 405gpr 5f1459dc 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
-G2000 ppc4xx 405ep 5f8f6294 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
-WUH405 ppc4xx 405ep fc88a5bf 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
-VOH405 ppc4xx 405ep 807db88b 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
-PMC405 ppc4xx 405gp d5263304 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
-PCI405 ppc4xx 405gp dbe7bb0d 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
-OCRTC ppc4xx 405gpr cc6e715f 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
-HUB405 ppc4xx 405ep e434d5d7 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
-HH405 ppc4xx 405ep 843125da 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
-DU440 ppc4xx 440epx 7ac9d47a 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
-DU405 ppc4xx 405gpr bc114076 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
-DP405 ppc4xx 405ep 9a4018e0 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
-CPCIISER4 ppc4xx 405gp 37057260 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
-CMS700 ppc4xx 405ep 2404124c 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
-ASH405 ppc4xx 405ep b5e7c84f 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
-AR405 ppc4xx 405gpr 61b57c4a 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
-APC405 ppc4xx 405gpr 2b8a04e5 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
-TASREG m68k mcf52x2 cbdc662a 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
-A3000 powerpc mpc824x d622ac39 2015-01-05
-CPC45 powerpc mpc824x d622ac39 2015-01-05 Josef Wagner <Wagner@Microsys.de>
-CU824 powerpc mpc824x d622ac39 2015-01-05 Wolfgang Denk <wd@denx.de>
-eXalion powerpc mpc824x d622ac39 2015-01-05 Torsten Demke <torsten.demke@fci.com>
-MVBLUE powerpc mpc824x d622ac39 2015-01-05
-MUSENKI powerpc mpc824x d622ac39 2015-01-05 Jim Thompson <jim@musenki.com>
-Sandpoint8240 powerpc mpc824x d622ac39 2015-01-05 Wolfgang Denk <wd@denx.de>
-Sandpoint8245 powerpc mpc824x d622ac39 2015-01-05 Jim Thompson <jim@musenki.com>
-utx8245 powerpc mpc824x d622ac39 2015-01-05 Greg Allen <gallen@arlut.utexas.edu>
-atc powerpc mpc8260 9067b300 2015-01-05 Wolfgang Denk <wd@denx.de>
-CPU86 powerpc mpc8260 f7e1af86 2015-01-05 Wolfgang Denk <wd@denx.de>
-CPU87 powerpc mpc8260 f7e1af86 2015-01-05
-ep82xxm powerpc mpc8260 e2b19629 2015-01-05
-gw8260 powerpc mpc8260 8eecbaf3 2015-01-05 Oliver Brown <obrown@adventnetworks.com>
-IPHASE4539 powerpc mpc8260 87882f57 2015-01-05 Wolfgang Grandegger <wg@denx.de>
-muas3001 powerpc mpc8260 d2fd1d66 2015-01-05 Heiko Schocher <hs@denx.de>
-PM825 powerpc mpc8260 dc0b2fb4 2015-01-05 Wolfgang Denk <wd@denx.de>
-PM826 powerpc mpc8260 dc0b2fb4 2015-01-05 Wolfgang Denk <wd@denx.de>
-PM828 powerpc mpc8260 dc0b2fb4 2015-01-05
-MPC8266ADS powerpc mpc8260 b3a2bbe1 2015-01-05 Rune Torgersen <runet@innovsys.com>
-VoVPN-GW powerpc mpc8260 cc90905f 2015-01-05
-ep8260 powerpc mpc8260 4ad015ba 2015-01-05 Frank Panno <fpanno@delphintech.com>
-ppmc8260 powerpc mpc8260 793116d2 2015-01-05 Brad Kemp <Brad.Kemp@seranoa.com>
-sacsng powerpc mpc8260 b35c0ad6 2015-01-05 Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
-cogent_mpc8260 powerpc mpc8260 d19f6a60 2015-01-05 Murray Jensen <Murray.Jensen@csiro.au>
-cogent_8xx powerpc mpc8xx d19f6a60 2015-01-05 Murray Jensen <Murray.Jensen@csiro.au>
-ESTEEM192E powerpc mpc8xx af0e3514 2015-01-05 Conn Clark <clark@esteem.com>
-IP860 powerpc mpc8xx 5ec71100 2015-01-05 Wolfgang Denk <wd@denx.de>
-IVML24 powerpc mpc8xx ca620cd1 2015-01-05 Wolfgang Denk <wd@denx.de>
-IVMS8 powerpc mpc8xx ca620cd1 2015-01-05 Wolfgang Denk <wd@denx.de>
-lwmon powerpc mpc8xx acc2372d 2015-01-05 Wolfgang Denk <wd@denx.de>
-NETVIA powerpc mpc8xx f017cd7f 2015-01-05 Pantelis Antoniou <panto@intracom.gr>
-R360MPI powerpc mpc8xx 79cbecb8 2015-01-05 Wolfgang Denk <wd@denx.de>
-RRvision powerpc mpc8xx 8737fc75 2015-01-05 Wolfgang Denk <wd@denx.de>
-SPD823TS powerpc mpc8xx 72ba368f 2015-01-05 Wolfgang Denk <wd@denx.de>
-KUP4K powerpc mpc8xx 4317d070 2015-01-05 Klaus Heydeck <heydeck@kieback-peter.de>
-KUP4X powerpc mpc8xx 4317d070 2015-01-05 Klaus Heydeck <heydeck@kieback-peter.de>
-ELPT860 powerpc mpc8xx 3c5b20f1 2015-01-05 The LEOX team <team@leox.org>
-uc100 powerpc mpc8xx ceaf499b 2015-01-05 Stefan Roese <sr@denx.de>
-FPS850L powerpc mpc8xx 5d2a5ef7 2015-01-05 Wolfgang Denk <wd@denx.de>
-FPS860L powerpc mpc8xx 5d2a5ef7 2015-01-05 Wolfgang Denk <wd@denx.de>
-NSCU powerpc mpc8xx 5d2a5ef7 2015-01-05
-SM850 powerpc mpc8xx 5d2a5ef7 2015-01-05 Wolfgang Denk <wd@denx.de>
-TK885D powerpc mpc8xx 5d2a5ef7 2015-01-05
-virtlab2 powerpc mpc8xx 5d2a5ef7 2015-01-05 Wolfgang Denk <wd@denx.de>
-hermes powerpc mpc8xx 36da51e 2014-12-08 Wolfgang Denk <wd@denx.de>
-TOP860 powerpc mpc860 d58a945 2014-10-28 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
-TOP9000 arm at91sam9xeXXX d58a945 2014-10-28 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
-TQM8272 powerpc mpc8260 f06f9a1 2014-10-27 Wolfgang Denk <wd@denx.de>
-TQM8260 powerpc mpc8260 ccc1950 2014-10-27 Wolfgang Denk <wd@denx.de>
-IDS8247 powerpc mpc8260 6afb357 2014-10-27 Heiko Schocher <hs@denx.de>
-HWW1U1A powerpc mpc85xx 4109cb0 2014-10-27 Kyle Moffett <Kyle.D.Moffett@boeing.com>
-hymod powerpc mpc8260 5038d7f 2014-10-27 Murray Jensen <Murray.Jensen@csiro.au>
-MHPC powerpc mpc8xx 1655f9f 2014-10-27 Frank Gottschling <fgottschling@eltec.de>
-ICU862 powerpc mpc8xx 4af5f0f 2014-10-27 Wolfgang Denk <wd@denx.de>
-CPCI750 powerpc 74xx_7xx 03b0040 2014-10-27 Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-DB64360 powerpc 74xx_7xx 03b0040 2014-10-27
-DB64460 powerpc 74xx_7xx 03b0040 2014-10-27
-p3m750 powerpc 74xx_7xx 03b0040 2014-10-27 Stefan Roese <sr@denx.de>
-p3m7448 powerpc 74xx_7xx 03b0040 2014-10-27 Stefan Roese <sr@denx.de>
-MERGERBOX powerpc mpc83xx e7a5656 2014-10-10 Andre Schwarz <andre.schwarz@matrix-vision.de>
-MVBLM7 powerpc mpc83xx e7a5656 2014-10-10 Andre Schwarz <andre.schwarz@matrix-vision.de>
-bluestone powerpc ppc4xx 9ed3246 2014-10-10 Tirumala Marri <tmarri@apm.com>
-CRAYL1 powerpc ppc4xx 1521cdc 2014-10-10 David Updegraff <dave@cray.com>
-KAREF powerpc ppc4xx dc9617e 2014-10-10 Travis Sawyer <travis.sawyer@sandburst.com>
-METROBOX powerpc ppc4xx dc9617e 2014-10-10 Travis Sawyer <travis.sawyer@sandburst.com>
-PK1C20 nios2 - 70fbc461 2014-08-24 Scott McNutt <smcnutt@psyent.com>
-PCI5441 nios2 - 70fbc461 2014-08-24 Scott McNutt <smcnutt@psyent.com>
-flagadm powerpc mpc8xx aec6f8c5 2014-08-22 Kári Davíðsson <kd@flaga.is>
-gen860t powerpc mpc8xx 6bde1ec1 2014-08-22 Keith Outwater <Keith_Outwater@mvis.com>
-sixnet powerpc mpc8xx 4723ce49 2014-08-22 Dave Ellis <DGE@sixnetio.com>
-svm_sc8xx powerpc mpc8xx d1a4aafd 2014-08-22 John Zhan <zhanz@sinovee.com>
-stxxtc powerpc mpc8xx 0ace4d9d 2014-08-22 Dan Malek <dan@embeddedalley.com>
-omap5912osk arm arm926ejs 62d636aa 2014-08-22 Rishi Bhattacharya <rishi@ti.com>
-p1023rds powerpc mpc85xx d0bc5140 2014-07-22 Roy Zang <tie-fei.zang@freescale.com>
-spc1920 powerpc mpc8xx 98ad54be 2014-07-07
-v37 powerpc mpc8xx b8c1438a 2014-07-07
-fads powerpc mpc8xx 03f9d7d1 2014-07-07
-netphone powerpc mpc8xx c51c1c9a 2014-07-07
-netta2 powerpc mpc8xx c51c1c9a 2014-07-07
-netta powerpc mpc8xx c51c1c9a 2014-07-07
-rbc823 powerpc mpc8xx c750b9c0 2014-07-07
-quantum powerpc mpc8xx 0657e46e 2014-07-07
-RPXlite_dw powerpc mpc8xx 0657e46e 2014-07-07
-qs850 powerpc mpc8xx dab0f762 2014-07-07
-qs860t powerpc mpc8xx dab0f762 2014-07-07
-simpc8313 powerpc mpc83xx 7445207f 2014-06-05 Ron Madrid <info@sheldoninst.com>
-hidden_dragon powerpc mpc824x 3fe1a854 2014-05-30 Yusdi Santoso <yusdi_santoso@adaptec.com>
-debris powerpc mpc824x 7edb1f7b 2014-05-30 Sangmoon Kim <dogoil@etinsys.com>
-kvme080 powerpc mpc824x 2868f862 2014-05-30 Sangmoon Kim <dogoil@etinsys.com>
-ep8248 powerpc mpc8260 49ad566d 2014-05-30 Yuli Barcohen <yuli@arabellasw.com>
-ispan powerpc mpc8260 80bae39a 2014-05-30 Yuli Barcohen <yuli@arabellasw.com>
-rattler powerpc mpc8260 d0664db4 2014-05-30 Yuli Barcohen <yuli@arabellasw.com>
-zpc1900 powerpc mpc8260 6f80bb48 2014-05-30 Yuli Barcohen <yuli@arabellasw.com>
-mpc8260ads powerpc mpc8260 facb6725 2014-05-30 Yuli Barcohen <yuli@arabellasw.com>
-adder powerpc mpc8xx 373a9788 2014-05-30 Yuli Barcohen <yuli@arabellasw.com>
-quad100hd powerpc ppc405ep 3569571d 2014-05-30 Gary Jennejohn <gljennjohn@googlemail.com>
-incaip mips mips32 538cf92c 2014-04-20 Wolfgang Denk <wd@denx.de>
-lubbock arm pxa 36bf57b 2014-04-18 Kyle Harris <kharris@nexus-tech.net>
-EVB64260 powerpc mpc824x bb3aef9 2014-04-18
-MOUSSE powerpc mpc824x 03f2ecc 2014-04-18
-rsdproto powerpc mpc8260 8b043e6 2014-04-18
-RPXsuper powerpc mpc8260 0ebf5f5 2014-04-18
-RPXClassic powerpc mpc8xx 4fb3925 2014-04-18
-RPXlite powerpc mpc8xx 4fb3925 2014-04-18
-FADS powerpc mpc8xx aa6e1e4 2014-04-18
-genietv powerpc mpc8xx b8a49bd 2014-04-18
-mbx8xx powerpc mpc8xx d6b11fd 2014-04-18
-nx823 powerpc mpc8xx a146e8b 2014-04-18
-idmr m68k mcf52x2 ba650e9b 2014-01-28
-M5271EVB m68k mcf52x2 ba650e9b 2014-01-28
-dvl_host arm ixp e317de6b 2014-01-28 Michael Schwingen <michael@schwingen.org>
-actux4 arm ixp 6ff7aafa 2014-01-28 Michael Schwingen <michael@schwingen.org>
-actux3 arm ixp 38da33f3 2014-01-28 Michael Schwingen <michael@schwingen.org>
-actux2 arm ixp 13e0ee7f 2014-01-28 Michael Schwingen <michael@schwingen.org>
-actux1 arm ixp 373ee048 2014-01-28 Michael Schwingen <michael@schwingen.org>
-mx1ads arm arm920t e570aca9 2014-01-13
-mini2440 arm arm920t af5b9b1f 2014-01-13 Gabriel Huau <contact@huau-gabriel.fr>
-omap730p2 arm arm926ejs 79c5c08d 2013-11-11
-pn62 powerpc mpc824x 649acfe1 2013-11-11 Wolfgang Grandegger <wg@grandegger.com>
-pdnb3 arm ixp 304db0b 2013-09-24 Stefan Roese <sr@denx.de>
-scpu arm ixp 304db0b 2013-09-24 Stefan Roese <sr@denx.de>
-omap1510inn arm arm925t 0610a16 2013-09-23 Kshitij Gupta <kshitij@ti.com>
-CANBT powerpc 405CR fb8f4fd 2013-08-07 Matthias Fuchs <matthias.fuchs@esd.eu>
-omap2420h4 arm omap24xx 7f5eef9 2013-06-04 Richard Woodruff <r-woodruff2@ti.com>
-Alaska8220 powerpc mpc8220 d6ed322 2013-05-11
-Yukon8220 powerpc mpc8220 d6ed322 2013-05-11
-sorcery powerpc mpc8220 d6ed322 2013-05-11
-smdk6400 arm arm1176 52587f1 2013-04-12 Zhong Hongbo <bocui107@gmail.com>
-ns9750dev arm arm926ejs 4cfc611 2013-02-28 Markus Pietrek <mpietrek@fsforth.de>
-eNET x86 x86 7e8c53d 2013-02-14 Graeme Russ <graeme.russ@gmail.com>
-PCIPPC2 powerpc MPC740/MPC750 7c9e89b 2013-02-07 Wolfgang Denk <wd@denx.de>
-PCIPPC6 powerpc MPC740/MPC750 7c9e89b 2013-02-07 Wolfgang Denk <wd@denx.de>
-AMX860 powerpc mpc860 1b0757e 2012-10-28 Wolfgang Denk <wd@denx.de>
-c2mon powerpc mpc855 1b0757e 2012-10-28 Wolfgang Denk <wd@denx.de>
-EP88x powerpc mpc885 1b0757e 2012-10-28
-ETX094 powerpc mpc850 1b0757e 2012-10-28 Wolfgang Denk <wd@denx.de>
-IAD210 powerpc mpc860 1b0757e 2012-10-28 -
-LANTEC powerpc mpc850 1b0757e 2012-10-28 Wolfgang Denk <wd@denx.de>
-SCM powerpc mpc8260 1b0757e 2012-10-28 Wolfgang Grandegger <wg@denx.de>
-SX1 arm arm925t 53c4154 2012-10-26
-TQM85xx powerpc MPC85xx d923a5d 2012-10-04 Stefan Roese <sr@denx.de>
-ADCIOP powerpc ppc4xx 99bcad1 2012-09-19 Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-DASA_SIM powerpc ppc4xx 99bcad1 2012-09-19 Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-apollon arm omap24xx 535c74f 2012-09-18 Kyungmin Park <kyungmin.park@samsung.com>
-tb0229 mips mips32 3f3110d 2011-12-12
-OXC powerpc MPC8240 309a292 2011-12-07
-BAB7xx powerpc MPC740/MPC750 c53043b 2011-12-07 Frank Gottschling <fgottschling@eltec.de>
-xm250 arm pxa c477d72 2011-11-25
-pleb2 arm pxa d299173 2011-11-25
-cradle arm pxa 00c4aca 2011-11-25 Kyle Harris <kharris@nexus-tech.net>
-cerf250 arm pxa f13eba6 2011-11-25 Prakash Kumar <prakash@embedx.com>
-mpq101 powerpc mpc85xx e877fab 2011-10-23 Alex Dubov <oakad@yahoo.com>
-ixdpg425 arm ixp 0ca8eb7 2011-09-22 Stefan Roese <sr@denx.de>
-ixdp425 arm ixp 0ca8eb7 2011-09-22 Kyle Harris <kharris@nexus-tech.net>
-zylonite arm pxa b66521a 2011-09-05
-shannon arm sa1100 5df092d 2011-09-05 Rolf Offermanns <rof@sysgo.de>
-modnet50 arm arm720t 9c62815 2011-09-05 Thomas Elste <info@elste.org>
-lpc2292sodimm arm arm720t d1a067a 2011-09-05
-lart arm sa1100 3d57573 2011-09-05 Alex Züpke <azu@sysgo.de>
-impa7 arm arm720t c1f8750 2011-09-05 Marius Gröger <mag@sysgo.de>
-gcplus arm sa1100 2c650e2 2011-09-05 George G. Davis <gdavis@mvista.com>
-evb4510 arm arm720t 26e670e 2011-09-05 Curt Brune <curt@cucy.com>
-ep7312 arm arm720t c8f63b4 2011-09-05 Marius Gröger <mag@sysgo.de>
-dnp1110 arm sa1100 fc5e5ce 2011-09-05 Alex Züpke <azu@sysgo.de>
-SMN42 arm arm720t 6aac646 2011-09-05
-at91rm9200dk arm arm920t 1c85752 2011-07-17
-m501sk arm arm920t b1a2bd4 2011-07-17
-kb9202 arm arm920t 5bd3814 2011-07-17
-csb637 arm arm920t d14af08 2011-07-17
-cmc_pu2 arm arm920t 37a9b4d 2011-07-17
-at91cap9adk arm arm926ejs b550834 2011-07-17 Stelian Pop <stelian@popies.net>
-voiceblue arm arm925t 1b793a4 2011-07-17
-smdk2400 arm arm920t ad218a8 2011-07-17 Gary Jennejohn <garyj@denx.de>
-sbc2410x arm arm920t 1f7f0ed 2011-07-17
-netstar arm arm925t 6ea2405 2011-07-17
-mx1fs2 arm arm920t 6962419 2011-07-17
-lpd7a404 arm lh7a40x 957731e 2011-07-17
-edb9301 arm arm920t 716f7ad 2011-07-17
-edb9302 arm arm920t 716f7ad 2011-07-17
-edb9302a arm arm920t 716f7ad 2011-07-17
-edb9307 arm arm920t 716f7ad 2011-07-17
-edb9307a arm arm920t 716f7ad 2011-07-17
-edb9312 arm arm920t 716f7ad 2011-07-17
-edb9315 arm arm920t 716f7ad 2011-07-17
-edb9315a arm arm920t 716f7ad 2011-07-17
-B2 arm s3c44b0 5dcf536 2011-07-16 Andrea Scian <andrea.scian@dave-tech.it>
-armadillo arm arm720t be28857 2011-07-16 Rowel Atienza <rowel@diwalabs.com>
-assabet arm sa1100 c91e90d 2011-07-16 George G. Davis <gdavis@mvista.com>
-trab arm S3C2400 566e5cf 2011-05-01 Gary Jennejohn <garyj@denx.de>
-mp2usb ARM AT91RM2900 ee986e2 2011-01-25 Eric Bénard <eric@eukrea.com>
-barco powerpc MPC8245 afaa27b 2010-11-23 Marc Leeman <marc.leeman@barco.com>
-ERIC powerpc 405GP d9ba451 2010-11-21 Swen Anderson <sand@peppercon.de>
-VoVPN-GW_100MHz powerpc MPC8260 26fe3d2 2010-10-24 Juergen Selent <j.selent@elmeg.de>
-xsengine ARM PXA2xx 4262a7c 2010-10-20
-wepep250 ARM PXA2xx 7369478 2010-10-20 Peter Figuli <peposh@etc.sk>
-delta ARM PXA2xx 75e2035 2010-10-20
-NC650 powerpc MPC852 333d86d 2010-10-19 Wolfgang Denk <wd@denx.de>
-CP850 powerpc MPC852 333d86d 2010-10-19 Wolfgang Denk <wd@denx.de>
-logodl ARM PXA2xx 059e778 2010-10-18 August Hoeraendl <august.hoerandl@gmx.at>
-CCM powerpc MPC860 dff07e1 2010-10-06 Wolfgang Grandegger <wg@denx.de>
-PCU_E powerpc MPC860T 544d97e 2010-10-06 Wolfgang Denk <wd@denx.de>
-HMI10 powerpc MPC823 77efe35 2010-09-19 Wolfgang Denk <wd@denx.de>
-GTH powerpc MPC860 0fe247b 2010-07-17 Thomas Lange <thomas@corelatus.se>
-AmigaOneG3SE powerpc 74xx_7xx 953b7e6 2010-06-23
-suzaku microblaze - 4f18060 2009-10-03 Yasushi Shoji <yashi@atmark-techno.com>
-XUPV2P microblaze - 8fab49e 2008-12-10 Michal Simek <monstr@monstr.eu>
-MVS1 powerpc MPC823 306620b 2008-08-26 Andre Schwarz <andre.schwarz@matrix-vision.de>
-adsvix ARM PXA27x 7610db1 2008-07-30 Adrian Filipi <adrian.filipi@eurotech.com>
-R5200 ColdFire - 48ead7a 2008-03-31 Zachary P. Landau <zachary.landau@labxtechnologies.com>
-CPCI440 powerpc 440GP b568fd2 2007-12-27 Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+in the imperishable depths of the git history. Please use the tools
+git provides to read through this history. A common example would be:
+$ git log -p --follow -- board/technexion/twister
+to see the history and changes made to the Technexion "twister" board
+from introduction to removal.
diff --git a/doc/README.sh b/doc/README.sh
deleted file mode 100644
index 766a8c8..0000000
--- a/doc/README.sh
+++ /dev/null
@@ -1,97 +0,0 @@
-
-U-Boot for Renesas SuperH
- Last update 01/18/2008 by Nobuhiro Iwamatsu
-
-================================================================================
-0. What's this?
- This file contains status information for the port of U-Boot to the
- Renesas SuperH series of CPUs.
-
-================================================================================
-1. Overview
- SuperH has an original boot loader. However, source code is dirty, and
- maintenance is not done.
- To improve sharing and the maintenance of the code, Nobuhiro Iwamatsu
- started the porting to u-boot in 2007.
-
-================================================================================
-2. Supported CPUs
-
- 2.1. Renesas SH7750/SH7750R
- This CPU has the SH4 core.
-
- 2.2. Renesas SH7722
- This CPU has the SH4AL-DSP core.
-
- 2.3. Renesas SH7780
- This CPU has the SH4A core.
-
-================================================================================
-3. Supported Boards
-
- 3.1. Hitachi UL MS7750SE01/MS7750RSE01
- Board specific code is in board/ms7750se
- To use this board, type "make ms7750se_config".
- Support devices are :
- - SCIF
- - SDRAM
- - NOR Flash
- - Marubun PCMCIA
-
- 3.2. Hitachi UL MS7722SE01
- Board specific code is in board/ms7722se
- To use this board, type "make ms7722se_config".
- Support devices are :
- - SCIF
- - SDRAM
- - NOR Flash
- - Marubun PCMCIA
- - SMC91x ethernet
-
- 3.2. Hitachi UL MS7720ERP01
- Board specific code is in board/ms7720se
- To use this board, type "make ms7720se_config".
- Support devices are :
- - SCIF
- - SDRAM
- - NOR Flash
- - Marubun PCMCIA
-
- 3.3. Renesas R7780MP
- Board specific code is in board/r7780mp
- To use this board, type "make r7780mp_config".
- Support devices are :
- - SCIF
- - DDR-SDRAM
- - NOR Flash
- - Compact Flash
- - ASIX ethernet
- - SH7780 PCI bridge
- - RTL8110 ethernet
-
- ** README **
- In SuperH, S-record and binary of made u-boot work on the memory.
- When u-boot is written in the flash, it is necessary to change the
- address by using 'objcopy'.
- ex) shX-linux-objcopy -Ibinary -Osrec u-boot.bin u-boot.flash.srec
-
-================================================================================
-4. Compiler
- You can use the following of u-boot to compile.
- - SuperH Linux Open site
- http://www.superh-linux.org/
- - KPIT GNU tools
- http://www.kpitgnutools.com/
-
-================================================================================
-5. Future
- I plan to support the following CPUs and boards.
- 5.1. CPUs
- - SH7751R(SH4)
-
- 5.2. Boards
- - Many boards ;-)
-
-================================================================================
-Copyright (c) 2007,2008
- Nobuhiro Iwamatsu <iwamatsu@nigaur.org>
diff --git a/doc/README.sh7752evb b/doc/README.sh7752evb
deleted file mode 100644
index c1fb54c..0000000
--- a/doc/README.sh7752evb
+++ /dev/null
@@ -1,67 +0,0 @@
-========================================
-Renesas R0P7752C00000RZ board
-========================================
-
-This board specification:
-=========================
-
-The R0P7752C00000RZ(board config name:sh7752evb) has the following device:
-
- - SH7752 (SH-4A)
- - DDR3-SDRAM 512MB
- - SPI ROM 8MB
- - Gigabit Ethernet controllers
- - eMMC 4GB
-
-
-Configuration for This board:
-=============================
-
-You can select the configuration as follows:
-
- - make sh7752evb_config
-
-
-This board specific command:
-============================
-
-This board has the following its specific command:
-
- - write_mac
-
-
-1. write_mac
-
-You can write MAC address to SPI ROM.
-
- Usage 1) Write MAC address
-
- write_mac [GETHERC ch0] [GETHERC ch1]
-
- For example)
- => write_mac 74:90:50:00:33:9e 74:90:50:00:33:9f
- *) We have to input the command as a single line
- (without carriage return)
- *) We have to reset after input the command.
-
- Usage 2) Show current data
-
- write_mac
-
- For example)
- => write_mac
- GETHERC ch0 = 74:90:50:00:33:9e
- GETHERC ch1 = 74:90:50:00:33:9f
-
-
-Update SPI ROM:
-============================
-
-1. Copy u-boot image to RAM area.
-2. Probe SPI device.
- => sf probe 0
- SF: Detected MX25L6405D with page size 64KiB, total 8 MiB
-3. Erase SPI ROM.
- => sf erase 0 80000
-4. Write u-boot image to SPI ROM.
- => sf write 0x48000000 0 80000
diff --git a/doc/README.sh7753evb b/doc/README.sh7753evb
deleted file mode 100644
index 5fe178c..0000000
--- a/doc/README.sh7753evb
+++ /dev/null
@@ -1,67 +0,0 @@
-========================================
-Renesas SH7753 EVB board
-========================================
-
-This board specification:
-=========================
-
-The SH7753 EVB (board config name:sh7753evb) has the following device:
-
- - SH7753 (SH-4A)
- - DDR3-SDRAM 512MB
- - SPI ROM 8MB
- - Gigabit Ethernet controllers
- - eMMC 4GB
-
-
-Configuration for This board:
-=============================
-
-You can select the configuration as follows:
-
- - make sh7753evb_config
-
-
-This board specific command:
-============================
-
-This board has the following its specific command:
-
- - write_mac
-
-
-1. write_mac
-
-You can write MAC address to SPI ROM.
-
- Usage 1) Write MAC address
-
- write_mac [GETHERC ch0] [GETHERC ch1]
-
- For example)
- => write_mac 74:90:50:00:33:9e 74:90:50:00:33:9f
- *) We have to input the command as a single line
- (without carriage return)
- *) We have to reset after input the command.
-
- Usage 2) Show current data
-
- write_mac
-
- For example)
- => write_mac
- GETHERC ch0 = 74:90:50:00:33:9e
- GETHERC ch1 = 74:90:50:00:33:9f
-
-
-Update SPI ROM:
-============================
-
-1. Copy u-boot image to RAM area.
-2. Probe SPI device.
- => sf probe 0
- SF: Detected MX25L6405D with page size 64KiB, total 8 MiB
-3. Erase SPI ROM.
- => sf erase 0 80000
-4. Write u-boot image to SPI ROM.
- => sf write 0x48000000 0 80000
diff --git a/doc/README.sifive-fu540 b/doc/README.sifive-fu540
deleted file mode 100644
index fd9f2a8..0000000
--- a/doc/README.sifive-fu540
+++ /dev/null
@@ -1,303 +0,0 @@
-FU540-C000 RISC-V SoC
-=====================
-The FU540-C000 is the world’s first 4+1 64-bit RISC‑V SoC from SiFive.
-
-The HiFive Unleashed development platform is based on FU540-C000 and capable
-of running Linux.
-
-Mainline support
-================
-The support for following drivers are already enabled:
-1. SiFive UART Driver.
-2. SiFive PRCI Driver for clock.
-3. Cadence MACB ethernet driver for networking support.
-
-TODO:
-1. SPI driver is still missing. So MMC card can't be used in U-Boot as of now.
-2. U-Boot expects the serial console device entry to be present under /chosen
- DT node. Example:
- chosen {
- stdout-path = "/soc/serial@10010000:115200";
- };
-
- Without a serial console U-Boot will panic.
-
-Building
-========
-1. Add the RISC-V toolchain to your PATH.
-2. Setup ARCH & cross compilation enviornment variable.
- a. export ARCH=riscv
- b. export CROSS_COMPILE=<riscv64 toolchain prefix>
-3. make sifive_fu540_defconfig
-4. make
-
-Flashing
-========
-The current U-Boot port is supported in S-mode only and loaded from DRAM.
-
-A prior stage (M-mode) firmware/bootloader (e.g OpenSBI or BBL) is required to
-load the u-boot.bin into memory and provide runtime services. The u-boot.bin
-can be given as a payload to the prior stage (M-mode) firmware/bootloader.
-
-The description of steps required to build the firmware is beyond the scope of
-this document. Please refer OpenSBI or BBL documenation.
-(Note: OpenSBI git repo is at https://github.com/riscv/opensbi.git)
-(Note: BBL git repo is at https://github.com/riscv/riscv-pk.git)
-
-Once the prior stage firmware/bootloader binary is generated, it should be
-copied to the first partition of the sdcard.
-
-sudo dd if=<prior_stage_firmware_binary> of=/dev/disk2s1 bs=1024
-
-Booting
-=======
-Once you plugin the sdcard and power up, you should see the U-Boot prompt.
-
-Sample boot log from HiFive Unleashed board
-===========================================
-U-Boot 2019.01-00019-gc7953536-dirty (Jan 22 2019 - 11:05:40 -0800)
-
-CPU: rv64imafdc
-Model: sifive,hifive-unleashed-a00
-DRAM: 8 GiB
-In: serial@10010000
-Out: serial@10010000
-Err: serial@10010000
-Net:
-Warning: ethernet@10090000 (eth0) using random MAC address - b6:75:4d:48:50:94
-eth0: ethernet@10090000
-Hit any key to stop autoboot: 0
-=> version
-U-Boot 2019.01-00019-gc7953536-dirty (Jan 22 2019 - 11:05:40 -0800)
-
-riscv64-linux-gcc.br_real (Buildroot 2018.11-rc2-00003-ga0787e9) 8.2.0
-GNU ld (GNU Binutils) 2.31.1
-=>
-===============================================================================
-
-Now you can configure your networking, tftp server and use tftp boot method to
-load uImage.
-
-==========================================================================
-=> setenv ethaddr 70:B3:D5:92:F0:C2
-=> setenv ipaddr 10.196.157.189
-=> setenv serverip 10.11.143.218
-=> setenv gatewayip 10.196.156.1
-=> setenv netmask 255.255.252.0
-=> bdinfo
-boot_params = 0x0000000000000000
-DRAM bank = 0x0000000000000000
--> start = 0x0000000080000000
--> size = 0x0000000200000000
-relocaddr = 0x00000000fff90000
-reloc off = 0x000000007fd90000
-ethaddr = 70:B3:D5:92:F0:C2
-IP addr = 10.196.157.189
-baudrate = 115200 bps
-=> tftpboot uImage
-ethernet@10090000: PHY present at 0
-ethernet@10090000: Starting autonegotiation...
-ethernet@10090000: Autonegotiation complete
-ethernet@10090000: link up, 1000Mbps full-duplex (lpa: 0x3800)
-Using ethernet@10090000 device
-TFTP from server 10.11.143.218; our IP address is 10.196.157.189; sending through gateway 10.196.156.1
-Filename 'uImage'.
-Load address: 0x80200000
-Loading: #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- ##########################################################
- 2.5 MiB/s
-done
-Bytes transferred = 14939132 (e3f3fc hex)
-=> bootm 0x80200000 - 0x82200000
-## Booting kernel from Legacy Image at 80200000 ...
- Image Name: Linux
- Image Type: RISC-V Linux Kernel Image (uncompressed)
- Data Size: 14939068 Bytes = 14.2 MiB
- Load Address: 80200000
- Entry Point: 80200000
- Verifying Checksum ... OK
-## Flattened Device Tree blob at 82200000
- Booting using the fdt blob at 0x82200000
- Loading Kernel Image ... OK
- Using Device Tree in place at 0000000082200000, end 0000000082205c69
-
-Starting kernel ...
-
-[ 0.000000] OF: fdt: Ignoring memory range 0x80000000 - 0x80200000
-[ 0.000000] Linux version 5.0.0-rc1-00020-g4b51f736 (atish@jedi-01) (gcc version 7.2.0 (GCC)) #262 SMP Mon Jan 21 17:39:27 PST 2019
-[ 0.000000] initrd not found or empty - disabling initrd
-[ 0.000000] Zone ranges:
-[ 0.000000] DMA32 [mem 0x0000000080200000-0x00000000ffffffff]
-[ 0.000000] Normal [mem 0x0000000100000000-0x000027ffffffffff]
-[ 0.000000] Movable zone start for each node
-[ 0.000000] Early memory node ranges
-[ 0.000000] node 0: [mem 0x0000000080200000-0x000000027fffffff]
-[ 0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x000000027fffffff]
-[ 0.000000] software IO TLB: mapped [mem 0xfbfff000-0xfffff000] (64MB)
-[ 0.000000] CPU with hartid=0 has a non-okay status of "masked"
-[ 0.000000] CPU with hartid=0 has a non-okay status of "masked"
-[ 0.000000] elf_hwcap is 0x112d
-[ 0.000000] percpu: Embedded 15 pages/cpu @(____ptrval____) s29720 r0 d31720 u61440
-[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2067975
-[ 0.000000] Kernel command line: earlyprintk
-[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes)
-[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes)
-[ 0.000000] Sorting __ex_table...
-[ 0.000000] Memory: 8178760K/8386560K available (3309K kernel code, 248K rwdata, 872K rodata, 9381K init, 763K bss, 207800K reserved, 0K cma-reserved)
-[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
-[ 0.000000] rcu: Hierarchical RCU implementation.
-[ 0.000000] rcu: RCU event tracing is enabled.
-[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
-[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
-[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
-[ 0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0
-[ 0.000000] plic: mapped 53 interrupts to 4 (out of 9) handlers.
-[ 0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [1]
-[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 3526361616960 ns
-[ 0.000008] sched_clock: 64 bits at 1000kHz, resolution 1000ns, wraps every 2199023255500ns
-[ 0.000221] Console: colour dummy device 80x25
-[ 0.000902] printk: console [tty0] enabled
-[ 0.000963] Calibrating delay loop (skipped), value calculated using timer frequency.. 2.00 BogoMIPS (lpj=10000)
-[ 0.001034] pid_max: default: 32768 minimum: 301
-[ 0.001541] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes)
-[ 0.001912] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes)
-[ 0.003542] rcu: Hierarchical SRCU implementation.
-[ 0.004347] smp: Bringing up secondary CPUs ...
-[ 1.040259] CPU1: failed to come online
-[ 2.080483] CPU2: failed to come online
-[ 3.120699] CPU3: failed to come online
-[ 3.120765] smp: Brought up 1 node, 1 CPU
-[ 3.121923] devtmpfs: initialized
-[ 3.124649] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
-[ 3.124727] futex hash table entries: 1024 (order: 4, 65536 bytes)
-[ 3.125346] random: get_random_u32 called from bucket_table_alloc+0x72/0x172 with crng_init=0
-[ 3.125578] NET: Registered protocol family 16
-[ 3.126400] sifive-u54-prci 10000000.prci: Registered U54 core clocks
-[ 3.126649] sifive-gemgxl-mgmt 100a0000.cadence-gemgxl-mgmt: Registered clock switch 'cadence-gemgxl-mgmt'
-[ 3.135572] vgaarb: loaded
-[ 3.135858] SCSI subsystem initialized
-[ 3.136193] usbcore: registered new interface driver usbfs
-[ 3.136266] usbcore: registered new interface driver hub
-[ 3.136348] usbcore: registered new device driver usb
-[ 3.136446] pps_core: LinuxPPS API ver. 1 registered
-[ 3.136484] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-[ 3.136575] PTP clock support registered
-[ 3.137256] clocksource: Switched to clocksource riscv_clocksource
-[ 3.142711] NET: Registered protocol family 2
-[ 3.143322] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes)
-[ 3.143634] TCP established hash table entries: 65536 (order: 7, 524288 bytes)
-[ 3.145799] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes)
-[ 3.149121] TCP: Hash tables configured (established 65536 bind 65536)
-[ 3.149591] UDP hash table entries: 4096 (order: 5, 131072 bytes)
-[ 3.150094] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes)
-[ 3.150781] NET: Registered protocol family 1
-[ 3.230693] workingset: timestamp_bits=62 max_order=21 bucket_order=0
-[ 3.241224] io scheduler mq-deadline registered
-[ 3.241269] io scheduler kyber registered
-[ 3.242143] sifive_gpio 10060000.gpio: SiFive GPIO chip registered 16 GPIOs
-[ 3.242357] pwm-sifivem 10020000.pwm: Unable to find controller clock
-[ 3.242439] pwm-sifivem 10021000.pwm: Unable to find controller clock
-[ 3.243228] xilinx-pcie 2000000000.pci: PCIe Link is DOWN
-[ 3.243289] xilinx-pcie 2000000000.pci: host bridge /soc/pci@2000000000 ranges:
-[ 3.243360] xilinx-pcie 2000000000.pci: No bus range found for /soc/pci@2000000000, using [bus 00-ff]
-[ 3.243447] xilinx-pcie 2000000000.pci: MEM 0x40000000..0x5fffffff -> 0x40000000
-[ 3.243591] xilinx-pcie 2000000000.pci: PCI host bridge to bus 0000:00
-[ 3.243636] pci_bus 0000:00: root bus resource [bus 00-ff]
-[ 3.243676] pci_bus 0000:00: root bus resource [mem 0x40000000-0x5fffffff]
-[ 3.276547] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[ 3.277689] 10010000.serial: ttySIF0 at MMIO 0x10010000 (irq = 39, base_baud = 0) is a SiFive UART v0
-[ 3.786963] printk: console [ttySIF0] enabled
-[ 3.791504] 10011000.serial: ttySIF1 at MMIO 0x10011000 (irq = 40, base_baud = 0) is a SiFive UART v0
-[ 3.801251] sifive_spi 10040000.spi: mapped; irq=41, cs=1
-[ 3.806362] m25p80 spi0.0: unrecognized JEDEC id bytes: 9d, 70, 19
-[ 3.812084] m25p80: probe of spi0.0 failed with error -2
-[ 3.817453] sifive_spi 10041000.spi: mapped; irq=42, cs=4
-[ 3.823027] sifive_spi 10050000.spi: mapped; irq=43, cs=1
-[ 3.828604] libphy: Fixed MDIO Bus: probed
-[ 3.832623] macb: GEM doesn't support hardware ptp.
-[ 3.837196] libphy: MACB_mii_bus: probed
-[ 4.041156] Microsemi VSC8541 SyncE 10090000.ethernet-ffffffff:00: attached PHY driver [Microsemi VSC8541 SyncE] (mii_bus:phy_addr=10090000.ethernet-ffffffff:00, irq=POLL)
-[ 4.055779] macb 10090000.ethernet eth0: Cadence GEM rev 0x10070109 at 0x10090000 irq 12 (70:b3:d5:92:f0:c2)
-[ 4.065780] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
-[ 4.072033] ehci-pci: EHCI PCI platform driver
-[ 4.076521] usbcore: registered new interface driver usb-storage
-[ 4.082843] softdog: initialized. soft_noboot=0 soft_margin=60 sec soft_panic=0 (nowayout=0)
-[ 4.127465] mmc_spi spi2.0: SD/MMC host mmc0, no DMA, no WP, no poweroff
-[ 4.133645] usbcore: registered new interface driver usbhid
-[ 4.138980] usbhid: USB HID core driver
-[ 4.143017] NET: Registered protocol family 17
-[ 4.147885] pwm-sifivem 10020000.pwm: SiFive PWM chip registered 4 PWMs
-[ 4.153945] pwm-sifivem 10021000.pwm: SiFive PWM chip registered 4 PWMs
-[ 4.186407] Freeing unused kernel memory: 9380K
-[ 4.190224] This architecture does not have kernel memory protection.
-[ 4.196609] Run /init as init process
-Starting logging: OK
-Starting mdev...
-[ 4.303785] mmc0: host does not support reading read-only switch, assuming write-enable
-[ 4.311109] mmc0: new SDHC card on SPI
-[ 4.317103] mmcblk0: mmc0:0000 SS08G 7.40 GiB
-[ 4.386471] mmcblk0: p1 p2
-sort: /sys/devices/platform/Fixed: No such file or directory
-modprobe: can't change directory to '/lib/modules': No such file or directory
-Initializing random[ 4.759075] random: dd: uninitialized urandom read (512 bytes read)
- number generator... done.
-Starting network...
-udhcpc (v1.24.2) started
-Sending discover...
-Sending discover...
-[ 7.927510] macb 10090000.ethernet eth0: link up (1000/Full)
-Sending discover...
-Sending select for 10.196.157.190...
-Lease of 10.196.157.190 obtained, lease time 499743
-deleting routers
-adding dns 10.86.1.1
-adding dns 10.86.2.1
-/etc/init.d/S50dropbear
-Starting dropbear sshd: [ 12.772393] random: dropbear: uninitialized urandom read (32 bytes read)
-OK
-
-Welcome to Buildroot
-buildroot login:
diff --git a/doc/README.u-boot_on_efi b/doc/README.u-boot_on_efi
deleted file mode 100644
index e12dd4e..0000000
--- a/doc/README.u-boot_on_efi
+++ /dev/null
@@ -1,252 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2015 Google, Inc
-
-U-Boot on EFI
-=============
-This document provides information about U-Boot running on top of EFI, either
-as an application or just as a means of getting U-Boot onto a new platform.
-
-
-=========== Table of Contents ===========
-
-Motivation
-Status
-Build Instructions
-Trying it out
-Inner workings
-EFI Application
-EFI Payload
-Tables
-Interrupts
-32/64-bit
-Future work
-Where is the code?
-
-
-Motivation
-----------
-Running U-Boot on EFI is useful in several situations:
-
-- You have EFI running on a board but U-Boot does not natively support it
-fully yet. You can boot into U-Boot from EFI and use that until U-Boot is
-fully ported
-
-- You need to use an EFI implementation (e.g. UEFI) because your vendor
-requires it in order to provide support
-
-- You plan to use coreboot to boot into U-Boot but coreboot support does
-not currently exist for your platform. In the meantime you can use U-Boot
-on EFI and then move to U-Boot on coreboot when ready
-
-- You use EFI but want to experiment with a simpler alternative like U-Boot
-
-
-Status
-------
-Only x86 is supported at present. If you are using EFI on another architecture
-you may want to reconsider. However, much of the code is generic so could be
-ported.
-
-U-Boot supports running as an EFI application for 32-bit EFI only. This is
-not very useful since only a serial port is provided. You can look around at
-memory and type 'help' but that is about it.
-
-More usefully, U-Boot supports building itself as a payload for either 32-bit
-or 64-bit EFI. U-Boot is packaged up and loaded in its entirety by EFI. Once
-started, U-Boot changes to 32-bit mode (currently) and takes over the
-machine. You can use devices, boot a kernel, etc.
-
-
-Build Instructions
-------------------
-First choose a board that has EFI support and obtain an EFI implementation
-for that board. It will be either 32-bit or 64-bit. Alternatively, you can
-opt for using QEMU [1] and the OVMF [2], as detailed below.
-
-To build U-Boot as an EFI application (32-bit EFI required), enable CONFIG_EFI
-and CONFIG_EFI_APP. The efi-x86_app config (efi-x86_app_defconfig) is set up
-for this. Just build U-Boot as normal, e.g.
-
- make efi-x86_app_defconfig
- make
-
-To build U-Boot as an EFI payload (32-bit or 64-bit EFI can be used), enable
-CONFIG_EFI, CONFIG_EFI_STUB, and select either CONFIG_EFI_STUB_32BIT or
-CONFIG_EFI_STUB_64BIT. The efi-x86_payload configs (efi-x86_payload32_defconfig
-and efi-x86_payload32_defconfig) are set up for this. Then build U-Boot as
-normal, e.g.
-
- make efi-x86_payload32_defconfig (or efi-x86_payload64_defconfig)
- make
-
-You will end up with one of these files depending on what you build for:
-
- u-boot-app.efi - U-Boot EFI application
- u-boot-payload.efi - U-Boot EFI payload application
-
-
-Trying it out
--------------
-QEMU is an emulator and it can emulate an x86 machine. Please make sure your
-QEMU version is 2.3.0 or above to test this. You can run the payload with
-something like this:
-
- mkdir /tmp/efi
- cp /path/to/u-boot*.efi /tmp/efi
- qemu-system-x86_64 -bios bios.bin -hda fat:/tmp/efi/
-
-Add -nographic if you want to use the terminal for output. Once it starts
-type 'fs0:u-boot-payload.efi' to run the payload or 'fs0:u-boot-app.efi' to
-run the application. 'bios.bin' is the EFI 'BIOS'. Check [2] to obtain a
-prebuilt EFI BIOS for QEMU or you can build one from source as well.
-
-To try it on real hardware, put u-boot-app.efi on a suitable boot medium,
-such as a USB stick. Then you can type something like this to start it:
-
- fs0:u-boot-payload.efi
-
-(or fs0:u-boot-app.efi for the application)
-
-This will start the payload, copy U-Boot into RAM and start U-Boot. Note
-that EFI does not support booting a 64-bit application from a 32-bit
-EFI (or vice versa). Also it will often fail to print an error message if
-you get this wrong.
-
-
-Inner workings
-==============
-Here follow a few implementation notes for those who want to fiddle with
-this and perhaps contribute patches.
-
-The application and payload approaches sound similar but are in fact
-implemented completely differently.
-
-EFI Application
----------------
-For the application the whole of U-Boot is built as a shared library. The
-efi_main() function is in lib/efi/efi_app.c. It sets up some basic EFI
-functions with efi_init(), sets up U-Boot global_data, allocates memory for
-U-Boot's malloc(), etc. and enters the normal init sequence (board_init_f()
-and board_init_r()).
-
-Since U-Boot limits its memory access to the allocated regions very little
-special code is needed. The CONFIG_EFI_APP option controls a few things
-that need to change so 'git grep CONFIG_EFI_APP' may be instructive.
-The CONFIG_EFI option controls more general EFI adjustments.
-
-The only available driver is the serial driver. This calls back into EFI
-'boot services' to send and receive characters. Although it is implemented
-as a serial driver the console device is not necessarilly serial. If you
-boot EFI with video output then the 'serial' device will operate on your
-target devices's display instead and the device's USB keyboard will also
-work if connected. If you have both serial and video output, then both
-consoles will be active. Even though U-Boot does the same thing normally,
-These are features of EFI, not U-Boot.
-
-Very little code is involved in implementing the EFI application feature.
-U-Boot is highly portable. Most of the difficulty is in modifying the
-Makefile settings to pass the right build flags. In particular there is very
-little x86-specific code involved - you can find most of it in
-arch/x86/cpu. Porting to ARM (which can also use EFI if you are brave
-enough) should be straightforward.
-
-Use the 'reset' command to get back to EFI.
-
-EFI Payload
------------
-The payload approach is a different kettle of fish. It works by building
-U-Boot exactly as normal for your target board, then adding the entire
-image (including device tree) into a small EFI stub application responsible
-for booting it. The stub application is built as a normal EFI application
-except that it has a lot of data attached to it.
-
-The stub application is implemented in lib/efi/efi_stub.c. The efi_main()
-function is called by EFI. It is responsible for copying U-Boot from its
-original location into memory, disabling EFI boot services and starting
-U-Boot. U-Boot then starts as normal, relocates, starts all drivers, etc.
-
-The stub application is architecture-dependent. At present it has some
-x86-specific code and a comment at the top of efi_stub.c describes this.
-
-While the stub application does allocate some memory from EFI this is not
-used by U-Boot (the payload). In fact when U-Boot starts it has all of the
-memory available to it and can operate as it pleases (but see the next
-section).
-
-Tables
-------
-The payload can pass information to U-Boot in the form of EFI tables. At
-present this feature is used to pass the EFI memory map, an inordinately
-large list of memory regions. You can use the 'efi mem all' command to
-display this list. U-Boot uses the list to work out where to relocate
-itself.
-
-Although U-Boot can use any memory it likes, EFI marks some memory as used
-by 'run-time services', code that hangs around while U-Boot is running and
-is even present when Linux is running. This is common on x86 and provides
-a way for Linux to call back into the firmware to control things like CPU
-fan speed. U-Boot uses only 'conventional' memory, in EFI terminology. It
-will relocate itself to the top of the largest block of memory it can find
-below 4GB.
-
-Interrupts
-----------
-U-Boot drivers typically don't use interrupts. Since EFI enables interrupts
-it is possible that an interrupt will fire that U-Boot cannot handle. This
-seems to cause problems. For this reason the U-Boot payload runs with
-interrupts disabled at present.
-
-32/64-bit
----------
-While the EFI application can in principle be built as either 32- or 64-bit,
-only 32-bit is currently supported. This means that the application can only
-be used with 32-bit EFI.
-
-The payload stub can be build as either 32- or 64-bits. Only a small amount
-of code is built this way (see the extra- line in lib/efi/Makefile).
-Everything else is built as a normal U-Boot, so is always 32-bit on x86 at
-present.
-
-Future work
------------
-This work could be extended in a number of ways:
-
-- Add ARM support
-
-- Add 64-bit application support
-
-- Figure out how to solve the interrupt problem
-
-- Add more drivers to the application side (e.g. video, block devices, USB,
-environment access). This would mostly be an academic exercise as a strong
-use case is not readily apparent, but it might be fun.
-
-- Avoid turning off boot services in the stub. Instead allow U-Boot to make
-use of boot services in case it wants to. It is unclear what it might want
-though.
-
-Where is the code?
-------------------
-lib/efi
- payload stub, application, support code. Mostly arch-neutral
-
-arch/x86/cpu/efi
- x86 support code for running as an EFI application and payload
-
-board/efi/efi-x86_app/efi.c
- x86 board code for running as an EFI application
-
-board/efi/efi-x86_payload
- generic x86 EFI payload board support code
-
-common/cmd_efi.c
- the 'efi' command
-
---
-Ben Stoltz, Simon Glass
-Google, Inc
-July 2015
-
-[1] http://www.qemu.org
-[2] http://www.tianocore.org/ovmf/
diff --git a/doc/README.uefi b/doc/README.uefi
deleted file mode 100644
index 1d1039a..0000000
--- a/doc/README.uefi
+++ /dev/null
@@ -1,352 +0,0 @@
-<!--
-SPDX-License-Identifier: GPL-2.0+
-
-Copyright (c) 2018 Heinrich Schuchardt
--->
-
-# UEFI on U-Boot
-
-The Unified Extensible Firmware Interface Specification (UEFI) [1] has become
-the default for booting on AArch64 and x86 systems. It provides a stable API for
-the interaction of drivers and applications with the firmware. The API comprises
-access to block storage, network, and console to name a few. The Linux kernel
-and boot loaders like GRUB or the FreeBSD loader can be executed.
-
-## Development target
-
-The implementation of UEFI in U-Boot strives to reach the requirements described
-in the "Embedded Base Boot Requirements (EBBR) Specification - Release v1.0"
-[4]. The "Server Base Boot Requirements System Software on ARM Platforms" [5]
-describes a superset of the EBBR specification and may be used as further
-reference.
-
-A full blown UEFI implementation would contradict the U-Boot design principle
-"keep it small".
-
-## Building for UEFI
-
-The UEFI standard supports only little-endian systems. The UEFI support can be
-activated for ARM and x86 by specifying
-
- CONFIG_CMD_BOOTEFI=y
- CONFIG_EFI_LOADER=y
-
-in the .config file.
-
-Support for attaching virtual block devices, e.g. iSCSI drives connected by the
-loaded UEFI application [3], requires
-
- CONFIG_BLK=y
- CONFIG_PARTITIONS=y
-
-### Executing a UEFI binary
-
-The bootefi command is used to start UEFI applications or to install UEFI
-drivers. It takes two parameters
-
- bootefi <image address> [fdt address]
-
-* image address - the memory address of the UEFI binary
-* fdt address - the memory address of the flattened device tree
-
-Below you find the output of an example session starting GRUB.
-
- => load mmc 0:2 ${fdt_addr_r} boot/dtb
- 29830 bytes read in 14 ms (2 MiB/s)
- => load mmc 0:1 ${kernel_addr_r} efi/debian/grubaa64.efi
- reading efi/debian/grubaa64.efi
- 120832 bytes read in 7 ms (16.5 MiB/s)
- => bootefi ${kernel_addr_r} ${fdt_addr_r}
-
-The environment variable 'bootargs' is passed as load options in the UEFI system
-table. The Linux kernel EFI stub uses the load options as command line
-arguments.
-
-### Executing the boot manager
-
-The UEFI specification foresees to define boot entries and boot sequence via UEFI
-variables. Booting according to these variables is possible via
-
- bootefi bootmgr [fdt address]
-
-As of U-Boot v2018.03 UEFI variables are not persisted and cannot be set at
-runtime.
-
-### Executing the built in hello world application
-
-A hello world UEFI application can be built with
-
- CONFIG_CMD_BOOTEFI_HELLO_COMPILE=y
-
-It can be embedded into the U-Boot binary with
-
- CONFIG_CMD_BOOTEFI_HELLO=y
-
-The bootefi command is used to start the embedded hello world application.
-
- bootefi hello [fdt address]
-
-Below you find the output of an example session.
-
- => bootefi hello ${fdtcontroladdr}
- ## Starting EFI application at 01000000 ...
- WARNING: using memory device/image path, this may confuse some payloads!
- Hello, world!
- Running on UEFI 2.7
- Have SMBIOS table
- Have device tree
- Load options: root=/dev/sdb3 init=/sbin/init rootwait ro
- ## Application terminated, r = 0
-
-The environment variable fdtcontroladdr points to U-Boot's internal device tree
-(if available).
-
-### Executing the built-in self-test
-
-An UEFI self-test suite can be embedded in U-Boot by building with
-
- CONFIG_CMD_BOOTEFI_SELFTEST=y
-
-For testing the UEFI implementation the bootefi command can be used to start the
-self-test.
-
- bootefi selftest [fdt address]
-
-The environment variable 'efi_selftest' can be used to select a single test. If
-it is not provided all tests are executed except those marked as 'on request'.
-If the environment variable is set to 'list' a list of all tests is shown.
-
-Below you can find the output of an example session.
-
- => setenv efi_selftest simple network protocol
- => bootefi selftest
- Testing EFI API implementation
- Selected test: 'simple network protocol'
- Setting up 'simple network protocol'
- Setting up 'simple network protocol' succeeded
- Executing 'simple network protocol'
- DHCP Discover
- DHCP reply received from 192.168.76.2 (52:55:c0:a8:4c:02)
- as broadcast message.
- Executing 'simple network protocol' succeeded
- Tearing down 'simple network protocol'
- Tearing down 'simple network protocol' succeeded
- Boot services terminated
- Summary: 0 failures
- Preparing for reset. Press any key.
-
-## The UEFI life cycle
-
-After the U-Boot platform has been initialized the UEFI API provides two kinds
-of services
-
-* boot services and
-* runtime services.
-
-The API can be extended by loading UEFI drivers which come in two variants
-
-* boot drivers and
-* runtime drivers.
-
-UEFI drivers are installed with U-Boot's bootefi command. With the same command
-UEFI applications can be executed.
-
-Loaded images of UEFI drivers stay in memory after returning to U-Boot while
-loaded images of applications are removed from memory.
-
-An UEFI application (e.g. an operating system) that wants to take full control
-of the system calls ExitBootServices. After a UEFI application calls
-ExitBootServices
-
-* boot services are not available anymore
-* timer events are stopped
-* the memory used by U-Boot except for runtime services is released
-* the memory used by boot time drivers is released
-
-So this is a point of no return. Afterwards the UEFI application can only return
-to U-Boot by rebooting.
-
-## The UEFI object model
-
-UEFI offers a flexible and expandable object model. The objects in the UEFI API
-are devices, drivers, and loaded images. These objects are referenced by
-handles.
-
-The interfaces implemented by the objects are referred to as protocols. These
-are identified by GUIDs. They can be installed and uninstalled by calling the
-appropriate boot services.
-
-Handles are created by the InstallProtocolInterface or the
-InstallMultipleProtocolinterfaces service if NULL is passed as handle.
-
-Handles are deleted when the last protocol has been removed with the
-UninstallProtocolInterface or the UninstallMultipleProtocolInterfaces service.
-
-Devices offer the EFI_DEVICE_PATH_PROTOCOL. A device path is the concatenation
-of device nodes. By their device paths all devices of a system are arranged in a
-tree.
-
-Drivers offer the EFI_DRIVER_BINDING_PROTOCOL. This protocol is used to connect
-a driver to devices (which are referenced as controllers in this context).
-
-Loaded images offer the EFI_LOADED_IMAGE_PROTOCOL. This protocol provides meta
-information about the image and a pointer to the unload callback function.
-
-## The UEFI events
-
-In the UEFI terminology an event is a data object referencing a notification
-function which is queued for calling when the event is signaled. The following
-types of events exist:
-
-* periodic and single shot timer events
-* exit boot services events, triggered by calling the ExitBootServices() service
-* virtual address change events
-* memory map change events
-* read to boot events
-* reset system events
-* system table events
-* events that are only triggered programmatically
-
-Events can be created with the CreateEvent service and deleted with CloseEvent
-service.
-
-Events can be assigned to an event group. If any of the events in a group is
-signaled, all other events in the group are also set to the signaled state.
-
-## The UEFI driver model
-
-A driver is specific for a single protocol installed on a device. To install a
-driver on a device the ConnectController service is called. In this context
-controller refers to the device for which the driver is installed.
-
-The relevant drivers are identified using the EFI_DRIVER_BINDING_PROTOCOL. This
-protocol has has three functions:
-
-* supported - determines if the driver is compatible with the device
-* start - installs the driver by opening the relevant protocol with
- attribute EFI_OPEN_PROTOCOL_BY_DRIVER
-* stop - uninstalls the driver
-
-The driver may create child controllers (child devices). E.g. a driver for block
-IO devices will create the device handles for the partitions. The child
-controllers will open the supported protocol with the attribute
-EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER.
-
-A driver can be detached from a device using the DisconnectController service.
-
-## U-Boot devices mapped as UEFI devices
-
-Some of the U-Boot devices are mapped as UEFI devices
-
-* block IO devices
-* console
-* graphical output
-* network adapter
-
-As of U-Boot 2018.03 the logic for doing this is hard coded.
-
-The development target is to integrate the setup of these UEFI devices with the
-U-Boot driver model. So when a U-Boot device is discovered a handle should be
-created and the device path protocol and the relevant IO protocol should be
-installed. The UEFI driver then would be attached by calling ConnectController.
-When a U-Boot device is removed DisconnectController should be called.
-
-## UEFI devices mapped as U-Boot devices
-
-UEFI drivers binaries and applications may create new (virtual) devices, install
-a protocol and call the ConnectController service. Now the matching UEFI driver
-is determined by iterating over the implementations of the
-EFI_DRIVER_BINDING_PROTOCOL.
-
-It is the task of the UEFI driver to create a corresponding U-Boot device and to
-proxy calls for this U-Boot device to the controller.
-
-In U-Boot 2018.03 this has only been implemented for block IO devices.
-
-### UEFI uclass
-
-An UEFI uclass driver (lib/efi_driver/efi_uclass.c) has been created that
-takes care of initializing the UEFI drivers and providing the
-EFI_DRIVER_BINDING_PROTOCOL implementation for the UEFI drivers.
-
-A linker created list is used to keep track of the UEFI drivers. To create an
-entry in the list the UEFI driver uses the U_BOOT_DRIVER macro specifying
-UCLASS_EFI as the ID of its uclass, e.g.
-
- /* Identify as UEFI driver */
- U_BOOT_DRIVER(efi_block) = {
- .name = "EFI block driver",
- .id = UCLASS_EFI,
- .ops = &driver_ops,
- };
-
-The available operations are defined via the structure struct efi_driver_ops.
-
- struct efi_driver_ops {
- const efi_guid_t *protocol;
- const efi_guid_t *child_protocol;
- int (*bind)(efi_handle_t handle, void *interface);
- };
-
-When the supported() function of the EFI_DRIVER_BINDING_PROTOCOL is called the
-uclass checks if the protocol GUID matches the protocol GUID of the UEFI driver.
-In the start() function the bind() function of the UEFI driver is called after
-checking the GUID.
-The stop() function of the EFI_DRIVER_BINDING_PROTOCOL disconnects the child
-controllers created by the UEFI driver and the UEFI driver. (In U-Boot v2013.03
-this is not yet completely implemented.)
-
-### UEFI block IO driver
-
-The UEFI block IO driver supports devices exposing the EFI_BLOCK_IO_PROTOCOL.
-
-When connected it creates a new U-Boot block IO device with interface type
-IF_TYPE_EFI, adds child controllers mapping the partitions, and installs the
-EFI_SIMPLE_FILE_SYSTEM_PROTOCOL on these. This can be used together with the
-software iPXE to boot from iSCSI network drives [3].
-
-This driver is only available if U-Boot is configured with
-
- CONFIG_BLK=y
- CONFIG_PARTITIONS=y
-
-## TODOs as of U-Boot 2019.04
-
-* unimplemented or incompletely implemented boot services
- * Exit - call unload function, unload applications only
- * ProtocolRegisterNotify
- * UnloadImage
-
-* unimplemented or incompletely implemented runtime services
- * SetVariable() ignores attribute EFI_VARIABLE_APPEND_WRITE
- * QueryVariableInfo is not implemented
-
-* unimplemented events
- * EVT_RUNTIME
- * EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE
-
-* data model
- * manage configuration tables in a linked list
-
-* UEFI drivers
- * support DisconnectController for UEFI block devices.
-
-* support for CONFIG_EFI_LOADER in the sandbox (CONFIG_SANDBOX=y)
-
-* UEFI variables
- * persistence
- * runtime support
-
-* incompletely implemented protocols
- * support version 0x00020000 of the EFI file protocol
-
-## Links
-
-* [1](http://uefi.org/specifications)
- http://uefi.org/specifications - UEFI specifications
-* [2](./driver-model/README.txt) doc/driver-model/README.txt - Driver model
-* [3](./README.iscsi) doc/README.iscsi - iSCSI booting with U-Boot and iPXE
-* [4](https://github.com/ARM-software/ebbr/releases/download/v1.0/ebbr-v1.0.pdf)
- Embedded Base Boot Requirements (EBBR) Specification - Release v1.0
-* [5](https://developer.arm.com/docs/den0044/latest/server-base-boot-requirements-system-software-on-arm-platforms-version-11)
- Server Base Boot Requirements System Software on ARM Platforms - Version 1.1
diff --git a/doc/README.x86 b/doc/README.x86
deleted file mode 100644
index 8e0a3f3..0000000
--- a/doc/README.x86
+++ /dev/null
@@ -1,1202 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2014, Simon Glass <sjg@chromium.org>
-# Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
-
-U-Boot on x86
-=============
-
-This document describes the information about U-Boot running on x86 targets,
-including supported boards, build instructions, todo list, etc.
-
-Status
-------
-U-Boot supports running as a coreboot [1] payload on x86. So far only Link
-(Chromebook Pixel) and QEMU [2] x86 targets have been tested, but it should
-work with minimal adjustments on other x86 boards since coreboot deals with
-most of the low-level details.
-
-U-Boot is a main bootloader on Intel Edison board.
-
-U-Boot also supports booting directly from x86 reset vector, without coreboot.
-In this case, known as bare mode, from the fact that it runs on the
-'bare metal', U-Boot acts like a BIOS replacement. The following platforms
-are supported:
-
- - Bayley Bay CRB
- - Cherry Hill CRB
- - Congatec QEVAL 2.0 & conga-QA3/E3845
- - Cougar Canyon 2 CRB
- - Crown Bay CRB
- - Galileo
- - Link (Chromebook Pixel)
- - Minnowboard MAX
- - Samus (Chromebook Pixel 2015)
- - QEMU x86 (32-bit & 64-bit)
-
-As for loading an OS, U-Boot supports directly booting a 32-bit or 64-bit
-Linux kernel as part of a FIT image. It also supports a compressed zImage.
-U-Boot supports loading an x86 VxWorks kernel. Please check README.vxworks
-for more details.
-
-Build Instructions for U-Boot as coreboot payload
--------------------------------------------------
-Building U-Boot as a coreboot payload is just like building U-Boot for targets
-on other architectures, like below:
-
-$ make coreboot_defconfig
-$ make all
-
-Build Instructions for U-Boot as main bootloader
-------------------------------------------------
-
-Intel Edison instructions:
-
-Simple you can build U-Boot and obtain u-boot.bin
-
-$ make edison_defconfig
-$ make all
-
-Build Instructions for U-Boot as BIOS replacement (bare mode)
--------------------------------------------------------------
-Building a ROM version of U-Boot (hereafter referred to as u-boot.rom) is a
-little bit tricky, as generally it requires several binary blobs which are not
-shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is
-not turned on by default in the U-Boot source tree. Firstly, you need turn it
-on by enabling the ROM build either via an environment variable
-
- $ export BUILD_ROM=y
-
-or via configuration
-
- CONFIG_BUILD_ROM=y
-
-Both tell the Makefile to build u-boot.rom as a target.
-
----
-
-Chromebook Link specific instructions for bare mode:
-
-First, you need the following binary blobs:
-
-* descriptor.bin - Intel flash descriptor
-* me.bin - Intel Management Engine
-* mrc.bin - Memory Reference Code, which sets up SDRAM
-* video ROM - sets up the display
-
-You can get these binary blobs by:
-
-$ git clone http://review.coreboot.org/p/blobs.git
-$ cd blobs
-
-Find the following files:
-
-* ./mainboard/google/link/descriptor.bin
-* ./mainboard/google/link/me.bin
-* ./northbridge/intel/sandybridge/systemagent-r6.bin
-
-The 3rd one should be renamed to mrc.bin.
-As for the video ROM, you can get it here [3] and rename it to vga.bin.
-Make sure all these binary blobs are put in the board directory.
-
-Now you can build U-Boot and obtain u-boot.rom:
-
-$ make chromebook_link_defconfig
-$ make all
-
----
-
-Chromebook Samus (2015 Pixel) instructions for bare mode:
-
-First, you need the following binary blobs:
-
-* descriptor.bin - Intel flash descriptor
-* me.bin - Intel Management Engine
-* mrc.bin - Memory Reference Code, which sets up SDRAM
-* refcode.elf - Additional Reference code
-* vga.bin - video ROM, which sets up the display
-
-If you have a samus you can obtain them from your flash, for example, in
-developer mode on the Chromebook (use Ctrl-Alt-F2 to obtain a terminal and
-log in as 'root'):
-
- cd /tmp
- flashrom -w samus.bin
- scp samus.bin username@ip_address:/path/to/somewhere
-
-If not see the coreboot tree [4] where you can use:
-
- bash crosfirmware.sh samus
-
-to get the image. There is also an 'extract_blobs.sh' scripts that you can use
-on the 'coreboot-Google_Samus.*' file to short-circuit some of the below.
-
-Then 'ifdtool -x samus.bin' on your development machine will produce:
-
- flashregion_0_flashdescriptor.bin
- flashregion_1_bios.bin
- flashregion_2_intel_me.bin
-
-Rename flashregion_0_flashdescriptor.bin to descriptor.bin
-Rename flashregion_2_intel_me.bin to me.bin
-You can ignore flashregion_1_bios.bin - it is not used.
-
-To get the rest, use 'cbfstool samus.bin print':
-
-samus.bin: 8192 kB, bootblocksize 2864, romsize 8388608, offset 0x700000
-alignment: 64 bytes, architecture: x86
-
-Name Offset Type Size
-cmos_layout.bin 0x700000 cmos_layout 1164
-pci8086,0406.rom 0x7004c0 optionrom 65536
-spd.bin 0x710500 (unknown) 4096
-cpu_microcode_blob.bin 0x711540 microcode 70720
-fallback/romstage 0x722a00 stage 54210
-fallback/ramstage 0x72fe00 stage 96382
-config 0x7476c0 raw 6075
-fallback/vboot 0x748ec0 stage 15980
-fallback/refcode 0x74cd80 stage 75578
-fallback/payload 0x75f500 payload 62878
-u-boot.dtb 0x76eb00 (unknown) 5318
-(empty) 0x770000 null 196504
-mrc.bin 0x79ffc0 (unknown) 222876
-(empty) 0x7d66c0 null 167320
-
-You can extract what you need:
-
- cbfstool samus.bin extract -n pci8086,0406.rom -f vga.bin
- cbfstool samus.bin extract -n fallback/refcode -f refcode.rmod
- cbfstool samus.bin extract -n mrc.bin -f mrc.bin
- cbfstool samus.bin extract -n fallback/refcode -f refcode.bin -U
-
-Note that the -U flag is only supported by the latest cbfstool. It unpacks
-and decompresses the stage to produce a coreboot rmodule. This is a simple
-representation of an ELF file. You need the patch "Support decoding a stage
-with compression".
-
-Put all 5 files into board/google/chromebook_samus.
-
-Now you can build U-Boot and obtain u-boot.rom:
-
-$ make chromebook_link_defconfig
-$ make all
-
-If you are using em100, then this command will flash write -Boot:
-
- em100 -s -d filename.rom -c W25Q64CV -r
-
-Flash map for samus / broadwell:
-
- fffff800 SYS_X86_START16
- ffff0000 RESET_SEG_START
- fffd8000 TPL_TEXT_BASE
- fffa0000 X86_MRC_ADDR
- fff90000 VGA_BIOS_ADDR
- ffed0000 SYS_TEXT_BASE
- ffea0000 X86_REFCODE_ADDR
- ffe70000 SPL_TEXT_BASE
- ffbf8000 CONFIG_ENV_OFFSET (environemnt offset)
- ffbe0000 rw-mrc-cache (Memory-reference-code cache)
- ffa00000 <spare>
- ff801000 intel-me (address set by descriptor.bin)
- ff800000 intel-descriptor
-
----
-
-Intel Crown Bay specific instructions for bare mode:
-
-U-Boot support of Intel Crown Bay board [4] relies on a binary blob called
-Firmware Support Package [5] to perform all the necessary initialization steps
-as documented in the BIOS Writer Guide, including initialization of the CPU,
-memory controller, chipset and certain bus interfaces.
-
-Download the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T,
-install it on your host and locate the FSP binary blob. Note this platform
-also requires a Chipset Micro Code (CMC) state machine binary to be present in
-the SPI flash where u-boot.rom resides, and this CMC binary blob can be found
-in this FSP package too.
-
-* ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd
-* ./Microcode/C0_22211.BIN
-
-Rename the first one to fsp.bin and second one to cmc.bin and put them in the
-board directory.
-
-Note the FSP release version 001 has a bug which could cause random endless
-loop during the FspInit call. This bug was published by Intel although Intel
-did not describe any details. We need manually apply the patch to the FSP
-binary using any hex editor (eg: bvi). Go to the offset 0x1fcd8 of the FSP
-binary, change the following five bytes values from orginally E8 42 FF FF FF
-to B8 00 80 0B 00.
-
-As for the video ROM, you need manually extract it from the Intel provided
-BIOS for Crown Bay here [6], using the AMI MMTool [7]. Check PCI option ROM
-ID 8086:4108, extract and save it as vga.bin in the board directory.
-
-Now you can build U-Boot and obtain u-boot.rom
-
-$ make crownbay_defconfig
-$ make all
-
----
-
-Intel Cougar Canyon 2 specific instructions for bare mode:
-
-This uses Intel FSP for 3rd generation Intel Core and Intel Celeron processors
-with mobile Intel HM76 and QM77 chipsets platform. Download it from Intel FSP
-website and put the .fd file (CHIEFRIVER_FSP_GOLD_001_09-OCTOBER-2013.fd at the
-time of writing) in the board directory and rename it to fsp.bin.
-
-Now build U-Boot and obtain u-boot.rom
-
-$ make cougarcanyon2_defconfig
-$ make all
-
-The board has two 8MB SPI flashes mounted, which are called SPI-0 and SPI-1 in
-the board manual. The SPI-0 flash should have flash descriptor plus ME firmware
-and SPI-1 flash is used to store U-Boot. For convenience, the complete 8MB SPI-0
-flash image is included in the FSP package (named Rom00_8M_MB_PPT.bin). Program
-this image to the SPI-0 flash according to the board manual just once and we are
-all set. For programming U-Boot we just need to program SPI-1 flash. Since the
-default u-boot.rom image for this board is set to 2MB, it should be programmed
-to the last 2MB of the 8MB chip, address range [600000, 7FFFFF].
-
----
-
-Intel Bay Trail based board instructions for bare mode:
-
-This uses as FSP as with Crown Bay, except it is for the Atom E3800 series.
-Two boards that use this configuration are Bayley Bay and Minnowboard MAX.
-Download this and get the .fd file (BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd at
-the time of writing). Put it in the corresponding board directory and rename
-it to fsp.bin.
-
-Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same
-board directory as vga.bin.
-
-You still need two more binary blobs. For Bayley Bay, they can be extracted
-from the sample SPI image provided in the FSP (SPI.bin at the time of writing).
-
- $ ./tools/ifdtool -x BayleyBay/SPI.bin
- $ cp flashregion_0_flashdescriptor.bin board/intel/bayleybay/descriptor.bin
- $ cp flashregion_2_intel_me.bin board/intel/bayleybay/me.bin
-
-For Minnowboard MAX, we can reuse the same ME firmware above, but for flash
-descriptor, we need get that somewhere else, as the one above does not seem to
-work, probably because it is not designed for the Minnowboard MAX. Now download
-the original firmware image for this board from:
-
-http://firmware.intel.com/sites/default/files/2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip
-
-Unzip it:
-
- $ unzip 2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip
-
-Use ifdtool in the U-Boot tools directory to extract the images from that
-file, for example:
-
- $ ./tools/ifdtool -x MNW2MAX1.X64.0073.R02.1409160934.bin
-
-This will provide the descriptor file - copy this into the correct place:
-
- $ cp flashregion_0_flashdescriptor.bin board/intel/minnowmax/descriptor.bin
-
-Now you can build U-Boot and obtain u-boot.rom
-Note: below are examples/information for Minnowboard MAX.
-
-$ make minnowmax_defconfig
-$ make all
-
-Checksums are as follows (but note that newer versions will invalidate this):
-
-$ md5sum -b board/intel/minnowmax/*.bin
-ffda9a3b94df5b74323afb328d51e6b4 board/intel/minnowmax/descriptor.bin
-69f65b9a580246291d20d08cbef9d7c5 board/intel/minnowmax/fsp.bin
-894a97d371544ec21de9c3e8e1716c4b board/intel/minnowmax/me.bin
-a2588537da387da592a27219d56e9962 board/intel/minnowmax/vga.bin
-
-The ROM image is broken up into these parts:
-
-Offset Description Controlling config
-------------------------------------------------------------
-000000 descriptor.bin Hard-coded to 0 in ifdtool
-001000 me.bin Set by the descriptor
-500000 <spare>
-6ef000 Environment CONFIG_ENV_OFFSET
-6f0000 MRC cache CONFIG_ENABLE_MRC_CACHE
-700000 u-boot-dtb.bin CONFIG_SYS_TEXT_BASE
-7b0000 vga.bin CONFIG_VGA_BIOS_ADDR
-7c0000 fsp.bin CONFIG_FSP_ADDR
-7f8000 <spare> (depends on size of fsp.bin)
-7ff800 U-Boot 16-bit boot CONFIG_SYS_X86_START16
-
-Overall ROM image size is controlled by CONFIG_ROM_SIZE.
-
-Note that the debug version of the FSP is bigger in size. If this version
-is used, CONFIG_FSP_ADDR needs to be configured to 0xfffb0000 instead of
-the default value 0xfffc0000.
-
----
-
-Intel Cherry Hill specific instructions for bare mode:
-
-This uses Intel FSP for Braswell platform. Download it from Intel FSP website,
-put the .fd file to the board directory and rename it to fsp.bin.
-
-Extract descriptor.bin and me.bin from the original BIOS on the board using
-ifdtool and put them to the board directory as well.
-
-Note the FSP package for Braswell does not ship a traditional legacy VGA BIOS
-image for the integrated graphics device. Instead a new binary called Video
-BIOS Table (VBT) is shipped. Put it to the board directory and rename it to
-vbt.bin if you want graphics support in U-Boot.
-
-Now you can build U-Boot and obtain u-boot.rom
-
-$ make cherryhill_defconfig
-$ make all
-
-An important note for programming u-boot.rom to the on-board SPI flash is that
-you need make sure the SPI flash's 'quad enable' bit in its status register
-matches the settings in the descriptor.bin, otherwise the board won't boot.
-
-For the on-board SPI flash MX25U6435F, this can be done by writing 0x40 to the
-status register by DediProg in: Config > Modify Status Register > Write Status
-Register(s) > Register1 Value(Hex). This is is a one-time change. Once set, it
-persists in SPI flash part regardless of the u-boot.rom image burned.
-
----
-
-Intel Galileo instructions for bare mode:
-
-Only one binary blob is needed for Remote Management Unit (RMU) within Intel
-Quark SoC. Not like FSP, U-Boot does not call into the binary. The binary is
-needed by the Quark SoC itself.
-
-You can get the binary blob from Quark Board Support Package from Intel website:
-
-* ./QuarkSocPkg/QuarkNorthCluster/Binary/QuarkMicrocode/RMU.bin
-
-Rename the file and put it to the board directory by:
-
- $ cp RMU.bin board/intel/galileo/rmu.bin
-
-Now you can build U-Boot and obtain u-boot.rom
-
-$ make galileo_defconfig
-$ make all
-
----
-
-QEMU x86 target instructions for bare mode:
-
-To build u-boot.rom for QEMU x86 targets, just simply run
-
-$ make qemu-x86_defconfig (for 32-bit)
-or
-$ make qemu-x86_64_defconfig (for 64-bit)
-$ make all
-
-Note this default configuration will build a U-Boot for the QEMU x86 i440FX
-board. To build a U-Boot against QEMU x86 Q35 board, you can change the build
-configuration during the 'make menuconfig' process like below:
-
-Device Tree Control --->
- ...
- (qemu-x86_q35) Default Device Tree for DT control
-
-Test with coreboot
-------------------
-For testing U-Boot as the coreboot payload, there are things that need be paid
-attention to. coreboot supports loading an ELF executable and a 32-bit plain
-binary, as well as other supported payloads. With the default configuration,
-U-Boot is set up to use a separate Device Tree Blob (dtb). As of today, the
-generated u-boot-dtb.bin needs to be packaged by the cbfstool utility (a tool
-provided by coreboot) manually as coreboot's 'make menuconfig' does not provide
-this capability yet. The command is as follows:
-
-# in the coreboot root directory
-$ ./build/util/cbfstool/cbfstool build/coreboot.rom add-flat-binary \
- -f u-boot-dtb.bin -n fallback/payload -c lzma -l 0x1110000 -e 0x1110000
-
-Make sure 0x1110000 matches CONFIG_SYS_TEXT_BASE, which is the symbol address
-of _x86boot_start (in arch/x86/cpu/start.S).
-
-If you want to use ELF as the coreboot payload, change U-Boot configuration to
-use CONFIG_OF_EMBED instead of CONFIG_OF_SEPARATE.
-
-To enable video you must enable these options in coreboot:
-
- - Set framebuffer graphics resolution (1280x1024 32k-color (1:5:5))
- - Keep VESA framebuffer
-
-At present it seems that for Minnowboard Max, coreboot does not pass through
-the video information correctly (it always says the resolution is 0x0). This
-works correctly for link though.
-
-Test with QEMU for bare mode
-----------------------------
-QEMU is a fancy emulator that can enable us to test U-Boot without access to
-a real x86 board. Please make sure your QEMU version is 2.3.0 or above test
-U-Boot. To launch QEMU with u-boot.rom, call QEMU as follows:
-
-$ qemu-system-i386 -nographic -bios path/to/u-boot.rom
-
-This will instantiate an emulated x86 board with i440FX and PIIX chipset. QEMU
-also supports emulating an x86 board with Q35 and ICH9 based chipset, which is
-also supported by U-Boot. To instantiate such a machine, call QEMU with:
-
-$ qemu-system-i386 -nographic -bios path/to/u-boot.rom -M q35
-
-Note by default QEMU instantiated boards only have 128 MiB system memory. But
-it is enough to have U-Boot boot and function correctly. You can increase the
-system memory by pass '-m' parameter to QEMU if you want more memory:
-
-$ qemu-system-i386 -nographic -bios path/to/u-boot.rom -m 1024
-
-This creates a board with 1 GiB system memory. Currently U-Boot for QEMU only
-supports 3 GiB maximum system memory and reserves the last 1 GiB address space
-for PCI device memory-mapped I/O and other stuff, so the maximum value of '-m'
-would be 3072.
-
-QEMU emulates a graphic card which U-Boot supports. Removing '-nographic' will
-show QEMU's VGA console window. Note this will disable QEMU's serial output.
-If you want to check both consoles, use '-serial stdio'.
-
-Multicore is also supported by QEMU via '-smp n' where n is the number of cores
-to instantiate. Note, the maximum supported CPU number in QEMU is 255.
-
-The fw_cfg interface in QEMU also provides information about kernel data,
-initrd, command-line arguments and more. U-Boot supports directly accessing
-these informtion from fw_cfg interface, which saves the time of loading them
-from hard disk or network again, through emulated devices. To use it , simply
-providing them in QEMU command line:
-
-$ qemu-system-i386 -nographic -bios path/to/u-boot.rom -m 1024 -kernel /path/to/bzImage
- -append 'root=/dev/ram console=ttyS0' -initrd /path/to/initrd -smp 8
-
-Note: -initrd and -smp are both optional
-
-Then start QEMU, in U-Boot command line use the following U-Boot command to
-setup kernel:
-
- => qfw
-qfw - QEMU firmware interface
-
-Usage:
-qfw <command>
- - list : print firmware(s) currently loaded
- - cpus : print online cpu number
- - load <kernel addr> <initrd addr> : load kernel and initrd (if any) and setup for zboot
-
-=> qfw load
-loading kernel to address 01000000 size 5d9d30 initrd 04000000 size 1b1ab50
-
-Here the kernel (bzImage) is loaded to 01000000 and initrd is to 04000000. Then,
-'zboot' can be used to boot the kernel:
-
-=> zboot 01000000 - 04000000 1b1ab50
-
-To run 64-bit U-Boot, qemu-system-x86_64 should be used instead, e.g.:
-$ qemu-system-x86_64 -nographic -bios path/to/u-boot.rom
-
-A specific CPU can be specified via the '-cpu' parameter but please make
-sure the specified CPU supports 64-bit like '-cpu core2duo'. Conversely
-'-cpu pentium' won't work for obvious reasons that the processor only
-supports 32-bit.
-
-Note 64-bit support is very preliminary at this point. Lots of features
-are missing in the 64-bit world. One notable feature is the VGA console
-support which is currently missing, so that you must specify '-nographic'
-to get 64-bit U-Boot up and running.
-
-Updating U-Boot on Edison
--------------------------
-By default Intel Edison boards are shipped with preinstalled heavily
-patched U-Boot v2014.04. Though it supports DFU which we may be able to
-use.
-
-1. Prepare u-boot.bin as described in chapter above. You still need one
-more step (if and only if you have original U-Boot), i.e. run the
-following command:
-
-$ truncate -s %4096 u-boot.bin
-
-2. Run your board and interrupt booting to U-Boot console. In the console
-call:
-
- => run do_force_flash_os
-
-3. Wait for few seconds, it will prepare environment variable and runs
-DFU. Run DFU command from the host system:
-
-$ dfu-util -v -d 8087:0a99 --alt u-boot0 -D u-boot.bin
-
-4. Return to U-Boot console and following hint. i.e. push Ctrl+C, and
-reset the board:
-
- => reset
-
-CPU Microcode
--------------
-Modern CPUs usually require a special bit stream called microcode [8] to be
-loaded on the processor after power up in order to function properly. U-Boot
-has already integrated these as hex dumps in the source tree.
-
-SMP Support
------------
-On a multicore system, U-Boot is executed on the bootstrap processor (BSP).
-Additional application processors (AP) can be brought up by U-Boot. In order to
-have an SMP kernel to discover all of the available processors, U-Boot needs to
-prepare configuration tables which contain the multi-CPUs information before
-loading the OS kernel. Currently U-Boot supports generating two types of tables
-for SMP, called Simple Firmware Interface (SFI) [9] and Multi-Processor (MP)
-[10] tables. The writing of these two tables are controlled by two Kconfig
-options GENERATE_SFI_TABLE and GENERATE_MP_TABLE.
-
-Driver Model
-------------
-x86 has been converted to use driver model for serial, GPIO, SPI, SPI flash,
-keyboard, real-time clock, USB. Video is in progress.
-
-Device Tree
------------
-x86 uses device tree to configure the board thus requires CONFIG_OF_CONTROL to
-be turned on. Not every device on the board is configured via device tree, but
-more and more devices will be added as time goes by. Check out the directory
-arch/x86/dts/ for these device tree source files.
-
-Useful Commands
----------------
-In keeping with the U-Boot philosophy of providing functions to check and
-adjust internal settings, there are several x86-specific commands that may be
-useful:
-
-fsp - Display information about Intel Firmware Support Package (FSP).
- This is only available on platforms which use FSP, mostly Atom.
-iod - Display I/O memory
-iow - Write I/O memory
-mtrr - List and set the Memory Type Range Registers (MTRR). These are used to
- tell the CPU whether memory is cacheable and if so the cache write
- mode to use. U-Boot sets up some reasonable values but you can
- adjust then with this command.
-
-Booting Ubuntu
---------------
-As an example of how to set up your boot flow with U-Boot, here are
-instructions for starting Ubuntu from U-Boot. These instructions have been
-tested on Minnowboard MAX with a SATA drive but are equally applicable on
-other platforms and other media. There are really only four steps and it's a
-very simple script, but a more detailed explanation is provided here for
-completeness.
-
-Note: It is possible to set up U-Boot to boot automatically using syslinux.
-It could also use the grub.cfg file (/efi/ubuntu/grub.cfg) to obtain the
-GUID. If you figure these out, please post patches to this README.
-
-Firstly, you will need Ubuntu installed on an available disk. It should be
-possible to make U-Boot start a USB start-up disk but for now let's assume
-that you used another boot loader to install Ubuntu.
-
-Use the U-Boot command line to find the UUID of the partition you want to
-boot. For example our disk is SCSI device 0:
-
-=> part list scsi 0
-
-Partition Map for SCSI device 0 -- Partition Type: EFI
-
- Part Start LBA End LBA Name
- Attributes
- Type GUID
- Partition GUID
- 1 0x00000800 0x001007ff ""
- attrs: 0x0000000000000000
- type: c12a7328-f81f-11d2-ba4b-00a0c93ec93b
- guid: 9d02e8e4-4d59-408f-a9b0-fd497bc9291c
- 2 0x00100800 0x037d8fff ""
- attrs: 0x0000000000000000
- type: 0fc63daf-8483-4772-8e79-3d69d8477de4
- guid: 965c59ee-1822-4326-90d2-b02446050059
- 3 0x037d9000 0x03ba27ff ""
- attrs: 0x0000000000000000
- type: 0657fd6d-a4ab-43c4-84e5-0933c84b4f4f
- guid: 2c4282bd-1e82-4bcf-a5ff-51dedbf39f17
- =>
-
-This shows that your SCSI disk has three partitions. The really long hex
-strings are called Globally Unique Identifiers (GUIDs). You can look up the
-'type' ones here [11]. On this disk the first partition is for EFI and is in
-VFAT format (DOS/Windows):
-
- => fatls scsi 0:1
- efi/
-
- 0 file(s), 1 dir(s)
-
-
-Partition 2 is 'Linux filesystem data' so that will be our root disk. It is
-in ext2 format:
-
- => ext2ls scsi 0:2
- <DIR> 4096 .
- <DIR> 4096 ..
- <DIR> 16384 lost+found
- <DIR> 4096 boot
- <DIR> 12288 etc
- <DIR> 4096 media
- <DIR> 4096 bin
- <DIR> 4096 dev
- <DIR> 4096 home
- <DIR> 4096 lib
- <DIR> 4096 lib64
- <DIR> 4096 mnt
- <DIR> 4096 opt
- <DIR> 4096 proc
- <DIR> 4096 root
- <DIR> 4096 run
- <DIR> 12288 sbin
- <DIR> 4096 srv
- <DIR> 4096 sys
- <DIR> 4096 tmp
- <DIR> 4096 usr
- <DIR> 4096 var
- <SYM> 33 initrd.img
- <SYM> 30 vmlinuz
- <DIR> 4096 cdrom
- <SYM> 33 initrd.img.old
- =>
-
-and if you look in the /boot directory you will see the kernel:
-
- => ext2ls scsi 0:2 /boot
- <DIR> 4096 .
- <DIR> 4096 ..
- <DIR> 4096 efi
- <DIR> 4096 grub
- 3381262 System.map-3.13.0-32-generic
- 1162712 abi-3.13.0-32-generic
- 165611 config-3.13.0-32-generic
- 176500 memtest86+.bin
- 178176 memtest86+.elf
- 178680 memtest86+_multiboot.bin
- 5798112 vmlinuz-3.13.0-32-generic
- 165762 config-3.13.0-58-generic
- 1165129 abi-3.13.0-58-generic
- 5823136 vmlinuz-3.13.0-58-generic
- 19215259 initrd.img-3.13.0-58-generic
- 3391763 System.map-3.13.0-58-generic
- 5825048 vmlinuz-3.13.0-58-generic.efi.signed
- 28304443 initrd.img-3.13.0-32-generic
- =>
-
-The 'vmlinuz' files contain a packaged Linux kernel. The format is a kind of
-self-extracting compressed file mixed with some 'setup' configuration data.
-Despite its size (uncompressed it is >10MB) this only includes a basic set of
-device drivers, enough to boot on most hardware types.
-
-The 'initrd' files contain a RAM disk. This is something that can be loaded
-into RAM and will appear to Linux like a disk. Ubuntu uses this to hold lots
-of drivers for whatever hardware you might have. It is loaded before the
-real root disk is accessed.
-
-The numbers after the end of each file are the version. Here it is Linux
-version 3.13. You can find the source code for this in the Linux tree with
-the tag v3.13. The '.0' allows for additional Linux releases to fix problems,
-but normally this is not needed. The '-58' is used by Ubuntu. Each time they
-release a new kernel they increment this number. New Ubuntu versions might
-include kernel patches to fix reported bugs. Stable kernels can exist for
-some years so this number can get quite high.
-
-The '.efi.signed' kernel is signed for EFI's secure boot. U-Boot has its own
-secure boot mechanism - see [12] [13] and cannot read .efi files at present.
-
-To boot Ubuntu from U-Boot the steps are as follows:
-
-1. Set up the boot arguments. Use the GUID for the partition you want to
-boot:
-
- => setenv bootargs root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro
-
-Here root= tells Linux the location of its root disk. The disk is specified
-by its GUID, using '/dev/disk/by-partuuid/', a Linux path to a 'directory'
-containing all the GUIDs Linux has found. When it starts up, there will be a
-file in that directory with this name in it. It is also possible to use a
-device name here, see later.
-
-2. Load the kernel. Since it is an ext2/4 filesystem we can do:
-
- => ext2load scsi 0:2 03000000 /boot/vmlinuz-3.13.0-58-generic
-
-The address 30000000 is arbitrary, but there seem to be problems with using
-small addresses (sometimes Linux cannot find the ramdisk). This is 48MB into
-the start of RAM (which is at 0 on x86).
-
-3. Load the ramdisk (to 64MB):
-
- => ext2load scsi 0:2 04000000 /boot/initrd.img-3.13.0-58-generic
-
-4. Start up the kernel. We need to know the size of the ramdisk, but can use
-a variable for that. U-Boot sets 'filesize' to the size of the last file it
-loaded.
-
- => zboot 03000000 0 04000000 ${filesize}
-
-Type 'help zboot' if you want to see what the arguments are. U-Boot on x86 is
-quite verbose when it boots a kernel. You should see these messages from
-U-Boot:
-
- Valid Boot Flag
- Setup Size = 0x00004400
- Magic signature found
- Using boot protocol version 2.0c
- Linux kernel version 3.13.0-58-generic (buildd@allspice) #97-Ubuntu SMP Wed Jul 8 02:56:15 UTC 2015
- Building boot_params at 0x00090000
- Loading bzImage at address 100000 (5805728 bytes)
- Magic signature found
- Initial RAM disk at linear address 0x04000000, size 19215259 bytes
- Kernel command line: "root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro"
-
- Starting kernel ...
-
-U-Boot prints out some bootstage timing. This is more useful if you put the
-above commands into a script since then it will be faster.
-
- Timer summary in microseconds:
- Mark Elapsed Stage
- 0 0 reset
- 241,535 241,535 board_init_r
- 2,421,611 2,180,076 id=64
- 2,421,790 179 id=65
- 2,428,215 6,425 main_loop
- 48,860,584 46,432,369 start_kernel
-
- Accumulated time:
- 240,329 ahci
- 1,422,704 vesa display
-
-Now the kernel actually starts: (if you want to examine kernel boot up message
-on the serial console, append "console=ttyS0,115200" to the kernel command line)
-
- [ 0.000000] Initializing cgroup subsys cpuset
- [ 0.000000] Initializing cgroup subsys cpu
- [ 0.000000] Initializing cgroup subsys cpuacct
- [ 0.000000] Linux version 3.13.0-58-generic (buildd@allspice) (gcc version 4.8.2 (Ubuntu 4.8.2-19ubuntu1) ) #97-Ubuntu SMP Wed Jul 8 02:56:15 UTC 2015 (Ubuntu 3.13.0-58.97-generic 3.13.11-ckt22)
- [ 0.000000] Command line: root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro console=ttyS0,115200
-
-It continues for a long time. Along the way you will see it pick up your
-ramdisk:
-
- [ 0.000000] RAMDISK: [mem 0x04000000-0x05253fff]
-...
- [ 0.788540] Trying to unpack rootfs image as initramfs...
- [ 1.540111] Freeing initrd memory: 18768K (ffff880004000000 - ffff880005254000)
-...
-
-Later it actually starts using it:
-
- Begin: Running /scripts/local-premount ... done.
-
-You should also see your boot disk turn up:
-
- [ 4.357243] scsi 1:0:0:0: Direct-Access ATA ADATA SP310 5.2 PQ: 0 ANSI: 5
- [ 4.366860] sd 1:0:0:0: [sda] 62533296 512-byte logical blocks: (32.0 GB/29.8 GiB)
- [ 4.375677] sd 1:0:0:0: Attached scsi generic sg0 type 0
- [ 4.381859] sd 1:0:0:0: [sda] Write Protect is off
- [ 4.387452] sd 1:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
- [ 4.399535] sda: sda1 sda2 sda3
-
-Linux has found the three partitions (sda1-3). Mercifully it doesn't print out
-the GUIDs. In step 1 above we could have used:
-
- setenv bootargs root=/dev/sda2 ro
-
-instead of the GUID. However if you add another drive to your board the
-numbering may change whereas the GUIDs will not. So if your boot partition
-becomes sdb2, it will still boot. For embedded systems where you just want to
-boot the first disk, you have that option.
-
-The last thing you will see on the console is mention of plymouth (which
-displays the Ubuntu start-up screen) and a lot of 'Starting' messages:
-
- * Starting Mount filesystems on boot [ OK ]
-
-After a pause you should see a login screen on your display and you are done.
-
-If you want to put this in a script you can use something like this:
-
- setenv bootargs root=UUID=b2aaf743-0418-4d90-94cc-3e6108d7d968 ro
- setenv boot zboot 03000000 0 04000000 \${filesize}
- setenv bootcmd "ext2load scsi 0:2 03000000 /boot/vmlinuz-3.13.0-58-generic; ext2load scsi 0:2 04000000 /boot/initrd.img-3.13.0-58-generic; run boot"
- saveenv
-
-The \ is to tell the shell not to evaluate ${filesize} as part of the setenv
-command.
-
-You can also bake this behaviour into your build by hard-coding the
-environment variables if you add this to minnowmax.h:
-
-#undef CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTCOMMAND \
- "ext2load scsi 0:2 03000000 /boot/vmlinuz-3.13.0-58-generic; " \
- "ext2load scsi 0:2 04000000 /boot/initrd.img-3.13.0-58-generic; " \
- "run boot"
-
-#undef CONFIG_EXTRA_ENV_SETTINGS
-#define CONFIG_EXTRA_ENV_SETTINGS "boot=zboot 03000000 0 04000000 ${filesize}"
-
-and change CONFIG_BOOTARGS value in configs/minnowmax_defconfig to:
-
-CONFIG_BOOTARGS="root=/dev/sda2 ro"
-
-Test with SeaBIOS
------------------
-SeaBIOS [14] is an open source implementation of a 16-bit x86 BIOS. It can run
-in an emulator or natively on x86 hardware with the use of U-Boot. With its
-help, we can boot some OSes that require 16-bit BIOS services like Windows/DOS.
-
-As U-Boot, we have to manually create a table where SeaBIOS gets various system
-information (eg: E820) from. The table unfortunately has to follow the coreboot
-table format as SeaBIOS currently supports booting as a coreboot payload.
-
-To support loading SeaBIOS, U-Boot should be built with CONFIG_SEABIOS on.
-Booting SeaBIOS is done via U-Boot's bootelf command, like below:
-
- => tftp bios.bin.elf;bootelf
- Using e1000#0 device
- TFTP from server 10.10.0.100; our IP address is 10.10.0.108
- ...
- Bytes transferred = 122124 (1dd0c hex)
- ## Starting application at 0x000ff06e ...
- SeaBIOS (version rel-1.9.0)
- ...
-
-bios.bin.elf is the SeaBIOS image built from SeaBIOS source tree.
-Make sure it is built as follows:
-
- $ make menuconfig
-
-Inside the "General Features" menu, select "Build for coreboot" as the
-"Build Target". Inside the "Debugging" menu, turn on "Serial port debugging"
-so that we can see something as soon as SeaBIOS boots. Leave other options
-as in their default state. Then,
-
- $ make
- ...
- Total size: 121888 Fixed: 66496 Free: 9184 (used 93.0% of 128KiB rom)
- Creating out/bios.bin.elf
-
-Currently this is tested on QEMU x86 target with U-Boot chain-loading SeaBIOS
-to install/boot a Windows XP OS (below for example command to install Windows).
-
- # Create a 10G disk.img as the virtual hard disk
- $ qemu-img create -f qcow2 disk.img 10G
-
- # Install a Windows XP OS from an ISO image 'winxp.iso'
- $ qemu-system-i386 -serial stdio -bios u-boot.rom -hda disk.img -cdrom winxp.iso -smp 2 -m 512
-
- # Boot a Windows XP OS installed on the virutal hard disk
- $ qemu-system-i386 -serial stdio -bios u-boot.rom -hda disk.img -smp 2 -m 512
-
-This is also tested on Intel Crown Bay board with a PCIe graphics card, booting
-SeaBIOS then chain-loading a GRUB on a USB drive, then Linux kernel finally.
-
-If you are using Intel Integrated Graphics Device (IGD) as the primary display
-device on your board, SeaBIOS needs to be patched manually to get its VGA ROM
-loaded and run by SeaBIOS. SeaBIOS locates VGA ROM via the PCI expansion ROM
-register, but IGD device does not have its VGA ROM mapped by this register.
-Its VGA ROM is packaged as part of u-boot.rom at a configurable flash address
-which is unknown to SeaBIOS. An example patch is needed for SeaBIOS below:
-
-diff --git a/src/optionroms.c b/src/optionroms.c
-index 65f7fe0..c7b6f5e 100644
---- a/src/optionroms.c
-+++ b/src/optionroms.c
-@@ -324,6 +324,8 @@ init_pcirom(struct pci_device *pci, int isvga, u64 *sources)
- rom = deploy_romfile(file);
- else if (RunPCIroms > 1 || (RunPCIroms == 1 && isvga))
- rom = map_pcirom(pci);
-+ if (pci->bdf == pci_to_bdf(0, 2, 0))
-+ rom = (struct rom_header *)0xfff90000;
- if (! rom)
- // No ROM present.
- return;
-
-Note: the patch above expects IGD device is at PCI b.d.f 0.2.0 and its VGA ROM
-is at 0xfff90000 which corresponds to CONFIG_VGA_BIOS_ADDR on Minnowboard MAX.
-Change these two accordingly if this is not the case on your board.
-
-Development Flow
-----------------
-These notes are for those who want to port U-Boot to a new x86 platform.
-
-Since x86 CPUs boot from SPI flash, a SPI flash emulator is a good investment.
-The Dediprog em100 can be used on Linux. The em100 tool is available here:
-
- http://review.coreboot.org/p/em100.git
-
-On Minnowboard Max the following command line can be used:
-
- sudo em100 -s -p LOW -d u-boot.rom -c W25Q64DW -r
-
-A suitable clip for connecting over the SPI flash chip is here:
-
- http://www.dediprog.com/pd/programmer-accessories/EM-TC-8
-
-This allows you to override the SPI flash contents for development purposes.
-Typically you can write to the em100 in around 1200ms, considerably faster
-than programming the real flash device each time. The only important
-limitation of the em100 is that it only supports SPI bus speeds up to 20MHz.
-This means that images must be set to boot with that speed. This is an
-Intel-specific feature - e.g. tools/ifttool has an option to set the SPI
-speed in the SPI descriptor region.
-
-If your chip/board uses an Intel Firmware Support Package (FSP) it is fairly
-easy to fit it in. You can follow the Minnowboard Max implementation, for
-example. Hopefully you will just need to create new files similar to those
-in arch/x86/cpu/baytrail which provide Bay Trail support.
-
-If you are not using an FSP you have more freedom and more responsibility.
-The ivybridge support works this way, although it still uses a ROM for
-graphics and still has binary blobs containing Intel code. You should aim to
-support all important peripherals on your platform including video and storage.
-Use the device tree for configuration where possible.
-
-For the microcode you can create a suitable device tree file using the
-microcode tool:
-
- ./tools/microcode-tool -d microcode.dat -m <model> create
-
-or if you only have header files and not the full Intel microcode.dat database:
-
- ./tools/microcode-tool -H BAY_TRAIL_FSP_KIT/Microcode/M0130673322.h \
- -H BAY_TRAIL_FSP_KIT/Microcode/M0130679901.h \
- -m all create
-
-These are written to arch/x86/dts/microcode/ by default.
-
-Note that it is possible to just add the micrcode for your CPU if you know its
-model. U-Boot prints this information when it starts
-
- CPU: x86_64, vendor Intel, device 30673h
-
-so here we can use the M0130673322 file.
-
-If you platform can display POST codes on two little 7-segment displays on
-the board, then you can use post_code() calls from C or assembler to monitor
-boot progress. This can be good for debugging.
-
-If not, you can try to get serial working as early as possible. The early
-debug serial port may be useful here. See setup_internal_uart() for an example.
-
-During the U-Boot porting, one of the important steps is to write correct PIRQ
-routing information in the board device tree. Without it, device drivers in the
-Linux kernel won't function correctly due to interrupt is not working. Please
-refer to U-Boot doc [15] for the device tree bindings of Intel interrupt router.
-Here we have more details on the intel,pirq-routing property below.
-
- intel,pirq-routing = <
- PCI_BDF(0, 2, 0) INTA PIRQA
- ...
- >;
-
-As you see each entry has 3 cells. For the first one, we need describe all pci
-devices mounted on the board. For SoC devices, normally there is a chapter on
-the chipset datasheet which lists all the available PCI devices. For example on
-Bay Trail, this is chapter 4.3 (PCI configuration space). For the second one, we
-can get the interrupt pin either from datasheet or hardware via U-Boot shell.
-The reliable source is the hardware as sometimes chipset datasheet is not 100%
-up-to-date. Type 'pci header' plus the device's pci bus/device/function number
-from U-Boot shell below.
-
- => pci header 0.1e.1
- vendor ID = 0x8086
- device ID = 0x0f08
- ...
- interrupt line = 0x09
- interrupt pin = 0x04
- ...
-
-It shows this PCI device is using INTD pin as it reports 4 in the interrupt pin
-register. Repeat this until you get interrupt pins for all the devices. The last
-cell is the PIRQ line which a particular interrupt pin is mapped to. On Intel
-chipset, the power-up default mapping is INTA/B/C/D maps to PIRQA/B/C/D. This
-can be changed by registers in LPC bridge. So far Intel FSP does not touch those
-registers so we can write down the PIRQ according to the default mapping rule.
-
-Once we get the PIRQ routing information in the device tree, the interrupt
-allocation and assignment will be done by U-Boot automatically. Now you can
-enable CONFIG_GENERATE_PIRQ_TABLE for testing Linux kernel using i8259 PIC and
-CONFIG_GENERATE_MP_TABLE for testing Linux kernel using local APIC and I/O APIC.
-
-This script might be useful. If you feed it the output of 'pci long' from
-U-Boot then it will generate a device tree fragment with the interrupt
-configuration for each device (note it needs gawk 4.0.0):
-
- $ cat console_output |awk '/PCI/ {device=$4} /interrupt line/ {line=$4} \
- /interrupt pin/ {pin = $4; if (pin != "0x00" && pin != "0xff") \
- {patsplit(device, bdf, "[0-9a-f]+"); \
- printf "PCI_BDF(%d, %d, %d) INT%c PIRQ%c\n", strtonum("0x" bdf[1]), \
- strtonum("0x" bdf[2]), bdf[3], strtonum(pin) + 64, 64 + strtonum(pin)}}'
-
-Example output:
- PCI_BDF(0, 2, 0) INTA PIRQA
- PCI_BDF(0, 3, 0) INTA PIRQA
-...
-
-Porting Hints
--------------
-
-Quark-specific considerations:
-
-To port U-Boot to other boards based on the Intel Quark SoC, a few things need
-to be taken care of. The first important part is the Memory Reference Code (MRC)
-parameters. Quark MRC supports memory-down configuration only. All these MRC
-parameters are supplied via the board device tree. To get started, first copy
-the MRC section of arch/x86/dts/galileo.dts to your board's device tree, then
-change these values by consulting board manuals or your hardware vendor.
-Available MRC parameter values are listed in include/dt-bindings/mrc/quark.h.
-The other tricky part is with PCIe. Quark SoC integrates two PCIe root ports,
-but by default they are held in reset after power on. In U-Boot, PCIe
-initialization is properly handled as per Quark's firmware writer guide.
-In your board support codes, you need provide two routines to aid PCIe
-initialization, which are board_assert_perst() and board_deassert_perst().
-The two routines need implement a board-specific mechanism to assert/deassert
-PCIe PERST# pin. Care must be taken that in those routines that any APIs that
-may trigger PCI enumeration process are strictly forbidden, as any access to
-PCIe root port's configuration registers will cause system hang while it is
-held in reset. For more details, check how they are implemented by the Intel
-Galileo board support codes in board/intel/galileo/galileo.c.
-
-coreboot:
-
-See scripts/coreboot.sed which can assist with porting coreboot code into
-U-Boot drivers. It will not resolve all build errors, but will perform common
-transformations. Remember to add attribution to coreboot for new files added
-to U-Boot. This should go at the top of each file and list the coreboot
-filename where the code originated.
-
-Debugging ACPI issues with Windows:
-
-Windows might cache system information and only detect ACPI changes if you
-modify the ACPI table versions. So tweak them liberally when debugging ACPI
-issues with Windows.
-
-ACPI Support Status
--------------------
-Advanced Configuration and Power Interface (ACPI) [16] aims to establish
-industry-standard interfaces enabling OS-directed configuration, power
-management, and thermal management of mobile, desktop, and server platforms.
-
-Linux can boot without ACPI with "acpi=off" command line parameter, but
-with ACPI the kernel gains the capabilities to handle power management.
-For Windows, ACPI is a must-have firmware feature since Windows Vista.
-CONFIG_GENERATE_ACPI_TABLE is the config option to turn on ACPI support in
-U-Boot. This requires Intel ACPI compiler to be installed on your host to
-compile ACPI DSDT table written in ASL format to AML format. You can get
-the compiler via "apt-get install iasl" if you are on Ubuntu or download
-the source from [17] to compile one by yourself.
-
-Current ACPI support in U-Boot is basically complete. More optional features
-can be added in the future. The status as of today is:
-
- * Support generating RSDT, XSDT, FACS, FADT, MADT, MCFG tables.
- * Support one static DSDT table only, compiled by Intel ACPI compiler.
- * Support S0/S3/S4/S5, reboot and shutdown from OS.
- * Support booting a pre-installed Ubuntu distribution via 'zboot' command.
- * Support installing and booting Ubuntu 14.04 (or above) from U-Boot with
- the help of SeaBIOS using legacy interface (non-UEFI mode).
- * Support installing and booting Windows 8.1/10 from U-Boot with the help
- of SeaBIOS using legacy interface (non-UEFI mode).
- * Support ACPI interrupts with SCI only.
-
-Features that are optional:
- * Dynamic AML bytecodes insertion at run-time. We may need this to support
- SSDT table generation and DSDT fix up.
- * SMI support. Since U-Boot is a modern bootloader, we don't want to bring
- those legacy stuff into U-Boot. ACPI spec allows a system that does not
- support SMI (a legacy-free system).
-
-ACPI was initially enabled on BayTrail based boards. Testing was done by booting
-a pre-installed Ubuntu 14.04 from a SATA drive. Installing Ubuntu 14.04 and
-Windows 8.1/10 to a SATA drive and booting from there is also tested. Most
-devices seem to work correctly and the board can respond a reboot/shutdown
-command from the OS.
-
-For other platform boards, ACPI support status can be checked by examining their
-board defconfig files to see if CONFIG_GENERATE_ACPI_TABLE is set to y.
-
-The S3 sleeping state is a low wake latency sleeping state defined by ACPI
-spec where all system context is lost except system memory. To test S3 resume
-with a Linux kernel, simply run "echo mem > /sys/power/state" and kernel will
-put the board to S3 state where the power is off. So when the power button is
-pressed again, U-Boot runs as it does in cold boot and detects the sleeping
-state via ACPI register to see if it is S3, if yes it means we are waking up.
-U-Boot is responsible for restoring the machine state as it is before sleep.
-When everything is done, U-Boot finds out the wakeup vector provided by OSes
-and jump there. To determine whether ACPI S3 resume is supported, check to
-see if CONFIG_HAVE_ACPI_RESUME is set for that specific board.
-
-Note for testing S3 resume with Windows, correct graphics driver must be
-installed for your platform, otherwise you won't find "Sleep" option in
-the "Power" submenu from the Windows start menu.
-
-EFI Support
------------
-U-Boot supports booting as a 32-bit or 64-bit EFI payload, e.g. with UEFI.
-This is enabled with CONFIG_EFI_STUB to boot from both 32-bit and 64-bit
-UEFI BIOS. U-Boot can also run as an EFI application, with CONFIG_EFI_APP.
-The CONFIG_EFI_LOADER option, where U-Boot provides an EFI environment to
-the kernel (i.e. replaces UEFI completely but provides the same EFI run-time
-services) is supported too. For example, we can even use 'bootefi' command
-to load a 'u-boot-payload.efi', see below test logs on QEMU.
-
- => load ide 0 3000000 u-boot-payload.efi
- 489787 bytes read in 138 ms (3.4 MiB/s)
- => bootefi 3000000
- Scanning disk ide.blk#0...
- Found 2 disks
- WARNING: booting without device tree
- ## Starting EFI application at 03000000 ...
- U-Boot EFI Payload
-
-
- U-Boot 2018.07-rc2 (Jun 23 2018 - 17:12:58 +0800)
-
- CPU: x86_64, vendor AMD, device 663h
- DRAM: 2 GiB
- MMC:
- Video: 1024x768x32
- Model: EFI x86 Payload
- Net: e1000: 52:54:00:12:34:56
-
- Warning: e1000#0 using MAC address from ROM
- eth0: e1000#0
- No controllers found
- Hit any key to stop autoboot: 0
-
-See README.u-boot_on_efi and README.uefi for details of EFI support in U-Boot.
-
-TODO List
----------
-- Audio
-- Chrome OS verified boot
-
-References
-----------
-[1] http://www.coreboot.org
-[2] http://www.qemu.org
-[3] http://www.coreboot.org/~stepan/pci8086,0166.rom
-[4] http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html
-[5] http://www.intel.com/fsp
-[6] http://www.intel.com/content/www/us/en/secure/intelligent-systems/privileged/e6xx-35-b1-cmc22211.html
-[7] http://www.ami.com/products/bios-uefi-tools-and-utilities/bios-uefi-utilities/
-[8] http://en.wikipedia.org/wiki/Microcode
-[9] http://simplefirmware.org
-[10] http://www.intel.com/design/archives/processors/pro/docs/242016.htm
-[11] https://en.wikipedia.org/wiki/GUID_Partition_Table
-[12] http://events.linuxfoundation.org/sites/events/files/slides/chromeos_and_diy_vboot_0.pdf
-[13] http://events.linuxfoundation.org/sites/events/files/slides/elce-2014.pdf
-[14] http://www.seabios.org/SeaBIOS
-[15] doc/device-tree-bindings/misc/intel,irq-router.txt
-[16] http://www.acpi.info
-[17] https://www.acpica.org/downloads
diff --git a/doc/README.xtensa b/doc/README.xtensa
deleted file mode 100644
index 4068582..0000000
--- a/doc/README.xtensa
+++ /dev/null
@@ -1,97 +0,0 @@
-U-Boot for the Xtensa Architecture
-==================================
-
-Xtensa Architecture and Diamond Cores
--------------------------------------
-
-Xtensa is a configurable processor architecture from Tensilica, Inc.
-Diamond Cores are pre-configured instances available for license and
-SoC cores in the same manner as ARM, MIPS, etc.
-
-Xtensa licensees create their own Xtensa cores with selected features
-and custom instructions, registers and co-processors. The custom core
-is configured with Tensilica tools and built with Tensilica's Xtensa
-Processor Generator.
-
-There are an effectively infinite number of CPUs in the Xtensa
-architecture family. It is, however, not feasible to support individual
-Xtensa CPUs in U-Boot. Therefore, there is only a single 'xtensa' CPU
-in the cpu tree of U-Boot.
-
-In the same manner as the Linux port to Xtensa, U-Boot adapts to an
-individual Xtensa core configuration using a set of macros provided with
-the particular core. This is part of what is known as the hardware
-abstraction layer (HAL). For the purpose of U-Boot, the HAL consists only
-of a few header files. These provide CPP macros that customize sources,
-Makefiles, and the linker script.
-
-
-Adding support for an additional processor configuration
---------------------------------------------------------
-
-The header files for one particular processor configuration are inside
-a variant-specific directory located in the arch/xtensa/include/asm
-directory. The name of that directory starts with 'arch-' followed by
-the name for the processor configuration, for example, arch-dc233c for
-the Diamond DC233 processor.
-
- core.h Definitions for the core itself.
-
-The following files are part of the overlay but not used by U-Boot.
-
- tie.h Co-processors and custom extensions defined
- in the Tensilica Instruction Extension (TIE)
- language.
- tie-asm.h Assembly macros to access custom-defined registers
- and states.
-
-
-Global Data Pointer, Exported Function Stubs, and the ABI
----------------------------------------------------------
-
-To support standalone applications launched with the "go" command,
-U-Boot provides a jump table of entrypoints to exported functions
-(grep for EXPORT_FUNC). The implementation for Xtensa depends on
-which ABI (or function calling convention) is used.
-
-Windowed ABI presents unique difficulties with the approach based on
-keeping global data pointer in dedicated register. Because the register
-window rotates during a call, there is no register that is constantly
-available for the gd pointer. Therefore, on xtensa gd is a simple
-global variable. Another difficulty arises from the requirement to have
-an 'entry' at the beginning of a function, which rotates the register
-file and reserves a stack frame. This is an integral part of the
-windowed ABI implemented in hardware. It makes using a jump table to an
-arbitrary (separately compiled) function a bit tricky. Use of a simple
-wrapper is also very tedious due to the need to move all possible
-register arguments and adjust the stack to handle arguments that cannot
-be passed in registers. The most efficient approach is to have the jump
-table perform the 'entry' so as to pretend it's the start of the real
-function. This requires decoding the target function's 'entry'
-instruction to determine the stack frame size, and adjusting the stack
-pointer accordingly, then jumping into the target function just after
-the 'entry'. Decoding depends on the processor's endianness so uses the
-HAL. The implementation (12 instructions) is in examples/stubs.c.
-
-
-Access to Invalid Memory Addresses
-----------------------------------
-
-U-Boot does not check if memory addresses given as arguments to commands
-such as "md" are valid. There are two possible types of invalid
-addresses: an area of physical address space may not be mapped to RAM
-or peripherals, or in the presence of MMU an area of virtual address
-space may not be mapped to physical addresses.
-
-Accessing first type of invalid addresses may result in hardware lockup,
-reading of meaningless data, written data being ignored or an exception,
-depending on the CPU wiring to the system. Accessing second type of
-invalid addresses always ends with an exception.
-
-U-Boot for Xtensa provides a special memory exception handler that
-reports such access attempts and resets the board.
-
-
-------------------------------------------------------------------------------
-Chris Zankel
-Ross Morley
diff --git a/doc/README.zynq b/doc/README.zynq
deleted file mode 100644
index da977b2..0000000
--- a/doc/README.zynq
+++ /dev/null
@@ -1,83 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Xilinx ZYNQ U-Boot
-#
-# (C) Copyright 2013 Xilinx, Inc.
-
-1. About this
-
-This document describes the information about Xilinx Zynq U-Boot -
-like supported boards, ML status and TODO list.
-
-2. Zynq boards
-
-Xilinx Zynq-7000 All Programmable SoCs enable extensive system level
-differentiation, integration, and flexibility through hardware, software,
-and I/O programmability.
-
-* zc702 (single qspi, gem0, mmc) [1]
-* zc706 (dual parallel qspi, gem0, mmc) [2]
-* zed (single qspi, gem0, mmc) [3]
-* microzed (single qspi, gem0, mmc) [4]
-* zc770
- - zc770-xm010 (single qspi, gem0, mmc)
- - zc770-xm011 (8 or 16 bit nand)
- - zc770-xm012 (nor)
- - zc770-xm013 (dual parallel qspi, gem1)
-
-3. Building
-
- ex. configure and build for zc702 board
- $ make zynq_zc702_config
- $ make
-
-4. Bootmode
-
-Zynq has a facility to read the bootmode from the slcr bootmode register
-once user is setting through jumpers on the board - see page no:1546 on [5]
-
-All possible bootmode values are defined in Table 6-2:Boot_Mode MIO Pins
-on [5].
-
-board_late_init() will read the bootmode values using slcr bootmode register
-at runtime and assign the modeboot variable to specific bootmode string which
-is intern used in autoboot.
-
-SLCR bootmode register Bit[3:0] values
-#define ZYNQ_BM_NOR 0x02
-#define ZYNQ_BM_SD 0x05
-#define ZYNQ_BM_JTAG 0x0
-
-"modeboot" variable can assign any of "norboot", "sdboot" or "jtagboot"
-bootmode strings at runtime.
-
-5. Mainline status
-
-- Added basic board configurations support.
-- Added zynq u-boot bsp code - arch/arm/cpu/armv7/zynq
-- Added zynq boards named - zc70x, zed, microzed, zc770_xm010/xm011/xm012/xm013
-- Added zynq drivers:
- serial - drivers/serial/serial_zynq.c
- net - drivers/net/zynq_gem.c
- mmc - drivers/mmc/zynq_sdhci.c
- spi - drivers/spi/zynq_spi.c
- qspi - drivers/spi/zynq_qspi.c
- i2c - drivers/i2c/zynq_i2c.c
- nand - drivers/mtd/nand/raw/zynq_nand.c
-- Done proper cleanups on board configurations
-- Added basic FDT support for zynq boards
-- d-cache support for zynq_gem.c
-
-6. TODO
-
-- Add FDT support on individual drivers
-
-[1] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC702-G.htm
-[2] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC706-G.htm
-[3] http://zedboard.org/product/zedboard
-[4] http://zedboard.org/product/microzed
-[5] http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
-
---
-Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
-Sun Dec 15 14:52:41 IST 2013
diff --git a/doc/android/fastboot.txt b/doc/android/fastboot.txt
index dcf8247..9de1322 100644
--- a/doc/android/fastboot.txt
+++ b/doc/android/fastboot.txt
@@ -5,8 +5,8 @@
Overview
========
-The protocol that is used over USB and UDP is described in the
-``fastboot-protocol.txt`` file in the same directory.
+The protocol that is used over USB and UDP is described in
+``doc/android/fastboot-protocol.txt``.
The current implementation supports the following standard commands:
@@ -169,9 +169,9 @@
::
- $ fastboot getvar bootloader-version
- bootloader-version: U-Boot 2014.04-00005-gd24cabc
- finished. total time: 0.000s
+ $ fastboot getvar version-bootloader
+ version-bootloader: U-Boot 2019.07-rc4-00240-g00c9f2a2ec
+ Finished. Total time: 0.005s
or initiate a reboot:
diff --git a/doc/api/efi.rst b/doc/api/efi.rst
new file mode 100644
index 0000000..2ca3449
--- /dev/null
+++ b/doc/api/efi.rst
@@ -0,0 +1,138 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+UEFI subsystem
+==============
+
+Lauching UEFI images
+--------------------
+
+Bootefi command
+~~~~~~~~~~~~~~~
+
+The bootefi command is used to start UEFI applications or to install UEFI
+drivers. It takes two parameters
+
+ bootefi <image address> [fdt address]
+
+* image address - the memory address of the UEFI binary
+* fdt address - the memory address of the flattened device tree
+
+The environment variable 'bootargs' is passed as load options in the UEFI system
+table. The Linux kernel EFI stub uses the load options as command line
+arguments.
+
+.. kernel-doc:: cmd/bootefi.c
+ :internal:
+
+Boot manager
+~~~~~~~~~~~~
+
+The UEFI specification foresees to define boot entries and boot sequence via UEFI
+variables. Booting according to these variables is possible via
+
+ bootefi bootmgr [fdt address]
+
+* fdt address - the memory address of the flattened device tree
+
+The relevant variables are:
+
+* Boot0000-BootFFFF define boot entries
+* BootNext specifies next boot option to be booted
+* BootOrder specifies in which sequence the boot options shall be tried if
+ BootNext is not defined or booting via BootNext fails
+
+.. kernel-doc:: lib/efi_loader/efi_bootmgr.c
+ :internal:
+
+Efidebug command
+~~~~~~~~~~~~~~~~
+
+The efidebug command is used to set and display boot options as well as to
+display information about internal data of the UEFI subsystem (devices,
+drivers, handles, loaded images, and the memory map).
+
+.. kernel-doc:: cmd/efidebug.c
+ :internal:
+
+Initialization of the UEFI sub-system
+-------------------------------------
+
+.. kernel-doc:: lib/efi_loader/efi_setup.c
+ :internal:
+
+Boot services
+-------------
+
+.. kernel-doc:: lib/efi_loader/efi_boottime.c
+ :internal:
+
+Image relocation
+~~~~~~~~~~~~~~~~
+
+.. kernel-doc:: lib/efi_loader/efi_image_loader.c
+ :internal:
+
+Memory services
+~~~~~~~~~~~~~~~
+
+.. kernel-doc:: lib/efi_loader/efi_memory.c
+ :internal:
+
+Runtime services
+----------------
+
+.. kernel-doc:: lib/efi_loader/efi_runtime.c
+ :internal:
+
+Variable services
+~~~~~~~~~~~~~~~~~
+
+.. kernel-doc:: lib/efi_loader/efi_variable.c
+ :internal:
+
+UEFI drivers
+------------
+
+UEFI driver uclass
+~~~~~~~~~~~~~~~~~~
+.. kernel-doc:: lib/efi_driver/efi_uclass.c
+ :internal:
+
+Block device driver
+~~~~~~~~~~~~~~~~~~~
+
+.. kernel-doc:: lib/efi_driver/efi_block_device.c
+ :internal:
+
+Protocols
+---------
+
+Block IO protocol
+~~~~~~~~~~~~~~~~~
+
+.. kernel-doc:: lib/efi_loader/efi_disk.c
+ :internal:
+
+File protocol
+~~~~~~~~~~~~~
+
+.. kernel-doc:: lib/efi_loader/efi_file.c
+ :internal:
+
+Graphical output protocol
+~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. kernel-doc:: lib/efi_loader/efi_gop.c
+ :internal:
+
+Network protocols
+~~~~~~~~~~~~~~~~~
+
+.. kernel-doc:: lib/efi_loader/efi_net.c
+ :internal:
+
+Text IO protocols
+~~~~~~~~~~~~~~~~~
+
+.. kernel-doc:: lib/efi_loader/efi_console.c
+ :internal:
diff --git a/doc/api/index.rst b/doc/api/index.rst
new file mode 100644
index 0000000..d484c06
--- /dev/null
+++ b/doc/api/index.rst
@@ -0,0 +1,11 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot API documentation
+========================
+
+.. toctree::
+ :maxdepth: 2
+
+ efi
+ linker_lists
+ serial
diff --git a/doc/linker_lists.rst b/doc/api/linker_lists.rst
similarity index 100%
rename from doc/linker_lists.rst
rename to doc/api/linker_lists.rst
diff --git a/doc/serial.rst b/doc/api/serial.rst
similarity index 100%
rename from doc/serial.rst
rename to doc/api/serial.rst
diff --git a/doc/arch/arc.rst b/doc/arch/arc.rst
new file mode 100644
index 0000000..f8e04a3
--- /dev/null
+++ b/doc/arch/arc.rst
@@ -0,0 +1,32 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+ARC
+===
+
+Synopsys' DesignWare(r) ARC(r) Processors are a family of 32-bit CPUs
+that SoC designers can optimize for a wide range of uses, from deeply embedded
+to high-performance host applications.
+
+More information on ARC cores avaialble here:
+http://www.synopsys.com/IP/ProcessorIP/ARCProcessors/Pages/default.aspx
+
+Designers can differentiate their products by using patented configuration
+technology to tailor each ARC processor instance to meet specific performance,
+power and area requirements.
+
+The DesignWare ARC processors are also extendable, allowing designers to add
+their own custom instructions that dramatically increase performance.
+
+Synopsys' ARC processors have been used by over 170 customers worldwide who
+collectively ship more than 1 billion ARC-based chips annually.
+
+All DesignWare ARC processors utilize a 16-/32-bit ISA that provides excellent
+performance and code density for embedded and host SoC applications.
+
+The RISC microprocessors are synthesizable and can be implemented in any foundry
+or process, and are supported by a complete suite of development tools.
+
+The ARC GNU toolchain with support for all ARC Processors can be downloaded
+from here (available pre-built toolchains as well):
+
+https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases
diff --git a/doc/arch/arm64.rst b/doc/arch/arm64.rst
new file mode 100644
index 0000000..80498f6
--- /dev/null
+++ b/doc/arch/arm64.rst
@@ -0,0 +1,59 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+ARM64
+=====
+
+Summary
+-------
+The initial arm64 U-Boot port was developed before hardware was available,
+so the first supported platforms were the Foundation and Fast Model for ARMv8.
+These days U-Boot runs on a variety of 64-bit capable ARM hardware, from
+embedded development boards to servers.
+
+Notes
+-----
+
+1. U-Boot can run at any exception level it is entered in, it is
+ recommened to enter it in EL3 if U-Boot takes some responsibilities of a
+ classical firmware (like initial hardware setup, CPU errata workarounds
+ or SMP bringup). U-Boot can be entered in EL2 when its main purpose is
+ that of a boot loader. It can drop to lower exception levels before
+ entering the OS.
+
+2. U-Boot for arm64 is compiled with AArch64-gcc. AArch64-gcc
+ use rela relocation format, a tool(tools/relocate-rela) by Scott Wood
+ is used to encode the initial addend of rela to u-boot.bin. After running,
+ the U-Boot will be relocated to destination again.
+
+3. Earlier Linux kernel versions required the FDT to be placed at a
+ 2 MB boundary and within the same 512 MB section as the kernel image,
+ resulting in fdt_high to be defined specially.
+ Since kernel version 4.2 Linux is more relaxed about the DT location, so it
+ can be placed anywhere in memory.
+ Please reference linux/Documentation/arm64/booting.txt for detail.
+
+4. Spin-table is used to wake up secondary processors. One location
+ (or per processor location) is defined to hold the kernel entry point
+ for secondary processors. It must be ensured that the location is
+ accessible and zero immediately after secondary processor
+ enter slave_cpu branch execution in start.S. The location address
+ is encoded in cpu node of DTS. Linux kernel store the entry point
+ of secondary processors to it and send event to wakeup secondary
+ processors.
+ Please reference linux/Documentation/arm64/booting.txt for detail.
+
+5. Generic board is supported.
+
+6. CONFIG_ARM64 instead of CONFIG_ARMV8 is used to distinguish aarch64 and
+ aarch32 specific codes.
+
+
+Contributors
+------------
+ * Tom Rini <trini@ti.com>
+ * Scott Wood <scottwood@freescale.com>
+ * York Sun <yorksun@freescale.com>
+ * Simon Glass <sjg@chromium.org>
+ * Sharma Bhupesh <bhupesh.sharma@freescale.com>
+ * Rob Herring <robherring2@gmail.com>
+ * Sergey Temerkhanov <s.temerkhanov@gmail.com>
diff --git a/doc/arch/index.rst b/doc/arch/index.rst
new file mode 100644
index 0000000..369d8ee
--- /dev/null
+++ b/doc/arch/index.rst
@@ -0,0 +1,18 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Architecture-specific doc
+=========================
+
+.. toctree::
+ :maxdepth: 2
+
+ arc
+ arm64
+ m68k
+ mips
+ nds32
+ nios2
+ sandbox
+ sh
+ x86
+ xtensa
diff --git a/doc/arch/m68k.rst b/doc/arch/m68k.rst
new file mode 100644
index 0000000..34b2593
--- /dev/null
+++ b/doc/arch/m68k.rst
@@ -0,0 +1,170 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+M68K / ColdFire
+===============
+
+History
+-------
+* November 02, 2017 Angelo Dureghello <angelo@sysam.it>
+* August 08, 2005 Jens Scharsig <esw@bus-elektronik.de>
+ MCF5282 implementation without preloader
+* January 12, 2004 <josef.baumgartner@telex.de>
+
+This file contains status information for the port of U-Boot to the
+Motorola ColdFire series of CPUs.
+
+Overview
+--------
+
+The ColdFire instruction set is "assembly source" compatible but an evolution
+of the original 68000 instruction set. Some not much used instructions has
+been removed. The instructions are only 16, 32, or 48 bits long, a
+simplification compared to the 68000 series.
+
+Bernhard Kuhn ported U-Boot 0.4.0 to the Motorola ColdFire architecture.
+The patches of Bernhard support the MCF5272 and MCF5282. A great disadvantage
+of these patches was that they needed a pre-bootloader to start U-Boot.
+Because of this, a new port was created which no longer needs a first stage
+booter.
+
+Thanks mainly to Freescale but also to several other contributors, U-Boot now
+supports nearly the entire range of ColdFire processors and their related
+development boards.
+
+
+Supported CPU families
+----------------------
+
+Please "make menuconfig" with ARCH=m68k, or check arch/m68k/cpu to see the
+currently supported processor and families.
+
+
+Supported boards
+----------------
+
+U-Boot supports actually more than 40 ColdFire based boards.
+Board configuration can be done trough include/configs/<boardname>.h but the
+current recommended method is to use the new and more friendly approach as
+the "make menuconfig" way, very similar to the Linux way.
+
+To know details as memory map, build targets, default setup, etc, of a
+specific board please check:
+
+* include/configs/<boardname>.h
+
+and/or
+
+* configs/<boardname>_defconfig
+
+It is possible to build all ColdFire boards in a single command-line command,
+from u-boot root directory, as::
+
+ ./tools/buildman/buildman m68k
+
+Build U-Boot for a specific board
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+A bash script similar to the one below may be used:
+
+.. code-block:: shell
+
+ #!/bin/bash
+
+ export CROSS_COMPILE=/opt/toolchains/m68k/gcc-4.9.0-nolibc/bin/m68k-linux-
+
+ board=M5475DFE
+
+ make distclean
+ make ARCH=m68k ${board}_defconfig
+ make ARCH=m68k KBUILD_VERBOSE=1
+
+
+Adopted toolchains
+------------------
+
+Please check:
+https://www.denx.de/wiki/U-Boot/ColdFireNotes
+
+
+ColdFire specific configuration options/settings
+------------------------------------------------
+
+Configuration to use a pre-loader
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+If U-Boot should be loaded to RAM and started by a pre-loader
+CONFIG_MONITOR_IS_IN_RAM must be defined. If it is defined the
+initial vector table and basic processor initialization will not
+be compiled in. The start address of U-Boot must be adjusted in
+the boards config header file (CONFIG_SYS_MONITOR_BASE) and Makefile
+(CONFIG_SYS_TEXT_BASE) to the load address.
+
+ColdFire CPU specific options/settings
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+To specify a CPU model, some defines shoudl be used, i.e.:
+
+CONFIG_MCF52x2:
+ defined for all MCF52x2 CPUs
+CONFIG_M5272:
+ defined for all Motorola MCF5272 CPUs
+
+Other options, generally set inside include/configs/<boardname>.h, they may
+apply to one or more cpu for the ColdFire family:
+
+CONFIG_SYS_MBAR:
+ defines the base address of the MCF5272 configuration registers
+CONFIG_SYS_ENET_BD_BASE:
+ defines the base address of the FEC buffer descriptors
+CONFIG_SYS_SCR:
+ defines the contents of the System Configuration Register
+CONFIG_SYS_SPR:
+ defines the contents of the System Protection Register
+CONFIG_SYS_MFD:
+ defines the PLL Multiplication Factor Divider
+ (see table 9-4 of MCF user manual)
+CONFIG_SYS_RFD:
+ defines the PLL Reduce Frequency Devider
+ (see table 9-4 of MCF user manual)
+CONFIG_SYS_CSx_BASE:
+ defines the base address of chip select x
+CONFIG_SYS_CSx_SIZE:
+ defines the memory size (address range) of chip select x
+CONFIG_SYS_CSx_WIDTH:
+ defines the bus with of chip select x
+CONFIG_SYS_CSx_MASK:
+ defines the mask for the related chip select x
+CONFIG_SYS_CSx_RO:
+ if set to 0 chip select x is read/write else chip select is read only
+CONFIG_SYS_CSx_WS:
+ defines the number of wait states of chip select x
+CONFIG_SYS_CACHE_ICACR:
+ cache-related registers config
+CONFIG_SYS_CACHE_DCACR:
+ cache-related registers config
+CONFIG_SYS_CACHE_ACRX:
+ cache-related registers config
+CONFIG_SYS_SDRAM_BASE:
+ SDRAM config for SDRAM controller-specific registers
+CONFIG_SYS_SDRAM_SIZE:
+ SDRAM config for SDRAM controller-specific registers
+CONFIG_SYS_SDRAM_BASEX:
+ SDRAM config for SDRAM controller-specific registers
+CONFIG_SYS_SDRAM_CFG1:
+ SDRAM config for SDRAM controller-specific registers
+CONFIG_SYS_SDRAM_CFG2:
+ SDRAM config for SDRAM controller-specific registers
+CONFIG_SYS_SDRAM_CTRL:
+ SDRAM config for SDRAM controller-specific registers
+CONFIG_SYS_SDRAM_MODE:
+ SDRAM config for SDRAM controller-specific registers
+CONFIG_SYS_SDRAM_EMOD:
+ SDRAM config for SDRAM controller-specific registers, please
+ see arch/m68k/cpu/<specific_cpu>/start.S files to see how
+ these options are used.
+CONFIG_MCFUART:
+ defines enabling of ColdFire UART driver
+CONFIG_SYS_UART_PORT:
+ defines the UART port to be used (only a single UART can be actually enabled)
+CONFIG_SYS_SBFHDR_SIZE:
+ size of the prepended SBF header, if any
diff --git a/doc/arch/mips.rst b/doc/arch/mips.rst
new file mode 100644
index 0000000..b816608
--- /dev/null
+++ b/doc/arch/mips.rst
@@ -0,0 +1,46 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+MIPS
+====
+
+Notes for the MIPS architecture port of U-Boot
+
+Toolchains
+----------
+
+ * `ELDK < DULG < DENX <http://www.denx.de/wiki/DULG/ELDK>`_
+ * `Embedded Debian -- Cross-development toolchains <http://www.emdebian.org/crosstools.html>`_
+ * `Buildroot <http://buildroot.uclibc.org/>`_
+
+Known Issues
+------------
+
+ * Cache incoherency issue caused by do_bootelf_exec() at cmd_elf.c
+
+ Cache will be disabled before entering the loaded ELF image without
+ writing back and invalidating cache lines. This leads to cache
+ incoherency in most cases, unless the code gets loaded after U-Boot
+ re-initializes the cache. The more common uImage 'bootm' command does
+ not suffer this problem.
+
+ [workaround] To avoid this cache incoherency:
+ - insert flush_cache(all) before calling dcache_disable(), or
+ - fix dcache_disable() to do both flushing and disabling cache.
+
+ * Note that Linux users need to kill dcache_disable() in do_bootelf_exec()
+ or override do_bootelf_exec() not to disable I-/D-caches, because most
+ Linux/MIPS ports don't re-enable caches after entering kernel_entry.
+
+TODOs
+-----
+
+ * Probe CPU types, I-/D-cache and TLB size etc. automatically
+ * Secondary cache support missing
+ * Initialize TLB entries redardless of their use
+ * R2000/R3000 class parts are not supported
+ * Limited testing across different MIPS variants
+ * Due to cache initialization issues, the DRAM on board must be
+ initialized in board specific assembler language before the cache init
+ code is run -- that is, initialize the DRAM in lowlevel_init().
+ * centralize/share more CPU code of MIPS32, MIPS64 and XBurst
+ * support Qemu Malta
diff --git a/doc/arch/nds32.rst b/doc/arch/nds32.rst
new file mode 100644
index 0000000..502397c
--- /dev/null
+++ b/doc/arch/nds32.rst
@@ -0,0 +1,101 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+NDS32
+=====
+
+NDS32 is a new high-performance 32-bit RISC microprocessor core.
+
+http://www.andestech.com/
+
+AndeStar ISA
+------------
+AndeStar is a patent-pending 16-bit/32-bit mixed-length instruction set to
+achieve optimal system performance, code density, and power efficiency.
+
+It contains the following features:
+ - Intermixable 32-bit and 16-bit instruction sets without the need for
+ mode switch.
+ - 16-bit instructions as a frequently used subset of 32-bit instructions.
+ - RISC-style register-based instruction set.
+ - 32 32-bit General Purpose Registers (GPR).
+ - Upto 1024 User Special Registers (USR) for existing and extension
+ instructions.
+ - Rich load/store instructions for...
+ - Single memory access with base address update.
+ - Multiple aligned and unaligned memory accesses for memory copy and stack
+ operations.
+ - Data prefetch to improve data cache performance.
+ - Non-bus locking synchronization instructions.
+ - PC relative jump and PC read instructions for efficient position independent
+ code.
+ - Multiply-add and multiple-sub with 64-bit accumulator.
+ - Instruction for efficient power management.
+ - Bi-endian support.
+ - Three instruction extension space for application acceleration:
+ - Performance extension.
+ - Andes future extensions (for floating-point, multimedia, etc.)
+ - Customer extensions.
+
+AndesCore CPU
+-------------
+Andes Technology has 4 families of CPU cores: N12, N10, N9, N8.
+
+For details about N12 CPU family, please check below N1213 features.
+N1213 is a configurable hard/soft core of NDS32's N12 CPU family.
+
+N1213 Features
+^^^^^^^^^^^^^^
+
+CPU Core
+ - 16-/32-bit mixable instruction format.
+ - 32 general-purpose 32-bit registers.
+ - 8-stage pipeline.
+ - Dynamic branch prediction.
+ - 32/64/128/256 BTB.
+ - Return address stack (RAS).
+ - Vector interrupts for internal/external.
+ interrupt controller with 6 hardware interrupt signals.
+ - 3 HW-level nested interruptions.
+ - User and super-user mode support.
+ - Memory-mapped I/O.
+ - Address space up to 4GB.
+
+Memory Management Unit
+ - TLB
+ - 4/8-entry fully associative iTLB/dTLB.
+ - 32/64/128-entry 4-way set-associati.ve main TLB.
+ - TLB locking support
+ - Optional hardware page table walker.
+ - Two groups of page size support.
+ - 4KB & 1MB.
+ - 8KB & 1MB.
+
+Memory Subsystem
+ - I & D cache.
+ - Virtually indexed and physically tagged.
+ - Cache size: 8KB/16KB/32KB/64KB.
+ - Cache line size: 16B/32B.
+ - Set associativity: 2-way, 4-way or direct-mapped.
+ - Cache locking support.
+ - I & D local memory (LM).
+ - Size: 4KB to 1MB.
+ - Bank numbers: 1 or 2.
+ - Optional 1D/2D DMA engine.
+ - Internal or external to CPU core.
+
+Bus Interface
+ - Synchronous/Asynchronous AHB bus: 0, 1 or 2 ports.
+ - Synchronous High speed memory port.
+ (HSMP): 0, 1 or 2 ports.
+
+Debug
+ - JTAG debug interface.
+ - Embedded debug module (EDM).
+ - Optional embedded program tracer interface.
+
+Miscellaneous
+ - Programmable data endian control.
+ - Performance monitoring mechanism.
+
+The NDS32 ports of u-boot, the Linux kernel, the GNU toolchain and other
+associated software are actively supported by Andes Technology Corporation.
diff --git a/doc/arch/nios2.rst b/doc/arch/nios2.rst
new file mode 100644
index 0000000..35defb0
--- /dev/null
+++ b/doc/arch/nios2.rst
@@ -0,0 +1,111 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Nios II
+=======
+
+Nios II is a 32-bit embedded-processor architecture designed
+specifically for the Altera family of FPGAs.
+
+Please refer to the link for more information on Nios II:
+https://www.altera.com/products/processors/overview.html
+
+Please refer to the link for Linux port and toolchains:
+http://rocketboards.org/foswiki/view/Documentation/NiosIILinuxUserManual
+
+The Nios II port of u-boot is controlled by device tree. Please check
+out doc/README.fdt-control.
+
+To add a new board/configuration (eg, mysystem) to u-boot, you will need
+three files.
+
+1. The device tree source which describes the hardware, dts file:
+ arch/nios2/dts/mysystem.dts
+
+2. Default configuration of Kconfig, defconfig file:
+ configs/mysystem_defconfig
+
+3. The legacy board header file:
+ include/configs/mysystem.h
+
+The device tree source must be generated from your qsys/sopc design
+using the sopc2dts tool. Then modified to fit your configuration.
+
+Please find the sopc2dts download and usage at the wiki:
+http://www.alterawiki.com/wiki/Sopc2dts
+
+.. code-block:: none
+
+ $ java -jar sopc2dts.jar --force-altr -i mysystem.sopcinfo -o mysystem.dts
+
+You will need to add additional properties to the dts. Please find an
+example at, arch/nios2/dts/10m50_devboard.dts.
+
+1. Add "stdout-path=..." property with your serial path to the chosen
+ node, like this::
+
+ chosen {
+ stdout-path = &uart_0;
+ };
+
+2. If you use SPI/EPCS or I2C, you will need to add aliases to number
+ the sequence of these devices, like this::
+
+ aliases {
+ spi0 = &epcs_controller;
+ };
+
+Next, you will need a default config file. You may start with
+10m50_defconfig, modify the options and save it.
+
+.. code-block:: none
+
+ $ make 10m50_defconfig
+ $ make menuconfig
+ $ make savedefconfig
+ $ cp defconfig configs/mysystem_defconfig
+
+You will need to change the names of board header file and device tree,
+and select the drivers with menuconfig.
+
+.. code-block:: none
+
+ Nios II architecture --->
+ (mysystem) Board header file
+ Device Tree Control --->
+ (mysystem) Default Device Tree for DT control
+
+There is a selection of "Provider of DTB for DT control" in the Device
+Tree Control menu.
+
+ * Separate DTB for DT control, will cat the dtb to end of u-boot
+ binary, output u-boot-dtb.bin. This should be used for production.
+ If you use boot copier, like EPCS boot copier, make sure the copier
+ copies all the u-boot-dtb.bin, not just u-boot.bin.
+
+ * Embedded DTB for DT control, will include the dtb inside the u-boot
+ binary. This is handy for development, eg, using gdb or nios2-download.
+
+The last thing, legacy board header file describes those config options
+not covered in Kconfig yet. You may copy it from 10m50_devboard.h::
+
+ $ cp include/configs/10m50_devboard.h include/configs/mysystem.h
+
+Please change the SDRAM base and size to match your board. The base
+should be cached virtual address, for Nios II with MMU it is 0xCxxx_xxxx
+to 0xDxxx_xxxx.
+
+.. code-block:: c
+
+ #define CONFIG_SYS_SDRAM_BASE 0xc8000000
+ #define CONFIG_SYS_SDRAM_SIZE 0x08000000
+
+You will need to change the environment variables location and setting,
+too. You may change other configs to fit your board.
+
+After all these changes, you may build and test::
+
+ $ export CROSS_COMPILE=nios2-elf- (or nios2-linux-gnu-)
+ $ make mysystem_defconfig
+ $ make
+
+Enjoy!
diff --git a/doc/arch/sandbox.rst b/doc/arch/sandbox.rst
new file mode 100644
index 0000000..5c0caeb
--- /dev/null
+++ b/doc/arch/sandbox.rst
@@ -0,0 +1,517 @@
+.. SPDX-License-Identifier: GPL-2.0+ */
+.. Copyright (c) 2014 The Chromium OS Authors.
+.. sectionauthor:: Simon Glass <sjg@chromium.org>
+
+Sandbox
+=======
+
+Native Execution of U-Boot
+--------------------------
+
+The 'sandbox' architecture is designed to allow U-Boot to run under Linux on
+almost any hardware. To achieve this it builds U-Boot (so far as possible)
+as a normal C application with a main() and normal C libraries.
+
+All of U-Boot's architecture-specific code therefore cannot be built as part
+of the sandbox U-Boot. The purpose of running U-Boot under Linux is to test
+all the generic code, not specific to any one architecture. The idea is to
+create unit tests which we can run to test this upper level code.
+
+CONFIG_SANDBOX is defined when building a native board.
+
+The board name is 'sandbox' but the vendor name is unset, so there is a
+single board in board/sandbox.
+
+CONFIG_SANDBOX_BIG_ENDIAN should be defined when running on big-endian
+machines.
+
+There are two versions of the sandbox: One using 32-bit-wide integers, and one
+using 64-bit-wide integers. The 32-bit version can be build and run on either
+32 or 64-bit hosts by either selecting or deselecting CONFIG_SANDBOX_32BIT; by
+default, the sandbox it built for a 32-bit host. The sandbox using 64-bit-wide
+integers can only be built on 64-bit hosts.
+
+Note that standalone/API support is not available at present.
+
+
+Basic Operation
+---------------
+
+To run sandbox U-Boot use something like::
+
+ make sandbox_defconfig all
+ ./u-boot
+
+Note: If you get errors about 'sdl-config: Command not found' you may need to
+install libsdl1.2-dev or similar to get SDL support. Alternatively you can
+build sandbox without SDL (i.e. no display/keyboard support) by removing
+the CONFIG_SANDBOX_SDL line in include/configs/sandbox.h or using::
+
+ make sandbox_defconfig all NO_SDL=1
+ ./u-boot
+
+U-Boot will start on your computer, showing a sandbox emulation of the serial
+console::
+
+ U-Boot 2014.04 (Mar 20 2014 - 19:06:00)
+
+ DRAM: 128 MiB
+ Using default environment
+
+ In: serial
+ Out: lcd
+ Err: lcd
+ =>
+
+You can issue commands as your would normally. If the command you want is
+not supported you can add it to include/configs/sandbox.h.
+
+To exit, type 'reset' or press Ctrl-C.
+
+
+Console / LCD support
+---------------------
+
+Assuming that CONFIG_SANDBOX_SDL is defined when building, you can run the
+sandbox with LCD and keyboard emulation, using something like::
+
+ ./u-boot -d u-boot.dtb -l
+
+This will start U-Boot with a window showing the contents of the LCD. If
+that window has the focus then you will be able to type commands as you
+would on the console. You can adjust the display settings in the device
+tree file - see arch/sandbox/dts/sandbox.dts.
+
+
+Command-line Options
+--------------------
+
+Various options are available, mostly for test purposes. Use -h to see
+available options. Some of these are described below.
+
+The terminal is normally in what is called 'raw-with-sigs' mode. This means
+that you can use arrow keys for command editing and history, but if you
+press Ctrl-C, U-Boot will exit instead of handling this as a keypress.
+
+Other options are 'raw' (so Ctrl-C is handled within U-Boot) and 'cooked'
+(where the terminal is in cooked mode and cursor keys will not work, Ctrl-C
+will exit).
+
+As mentioned above, -l causes the LCD emulation window to be shown.
+
+A device tree binary file can be provided with -d. If you edit the source
+(it is stored at arch/sandbox/dts/sandbox.dts) you must rebuild U-Boot to
+recreate the binary file.
+
+To execute commands directly, use the -c option. You can specify a single
+command, or multiple commands separated by a semicolon, as is normal in
+U-Boot. Be careful with quoting as the shell will normally process and
+swallow quotes. When -c is used, U-Boot exits after the command is complete,
+but you can force it to go to interactive mode instead with -i.
+
+
+Memory Emulation
+----------------
+
+Memory emulation is supported, with the size set by CONFIG_SYS_SDRAM_SIZE.
+The -m option can be used to read memory from a file on start-up and write
+it when shutting down. This allows preserving of memory contents across
+test runs. You can tell U-Boot to remove the memory file after it is read
+(on start-up) with the --rm_memory option.
+
+To access U-Boot's emulated memory within the code, use map_sysmem(). This
+function is used throughout U-Boot to ensure that emulated memory is used
+rather than the U-Boot application memory. This provides memory starting
+at 0 and extending to the size of the emulation.
+
+
+Storing State
+-------------
+
+With sandbox you can write drivers which emulate the operation of drivers on
+real devices. Some of these drivers may want to record state which is
+preserved across U-Boot runs. This is particularly useful for testing. For
+example, the contents of a SPI flash chip should not disappear just because
+U-Boot exits.
+
+State is stored in a device tree file in a simple format which is driver-
+specific. You then use the -s option to specify the state file. Use -r to
+make U-Boot read the state on start-up (otherwise it starts empty) and -w
+to write it on exit (otherwise the stored state is left unchanged and any
+changes U-Boot made will be lost). You can also use -n to tell U-Boot to
+ignore any problems with missing state. This is useful when first running
+since the state file will be empty.
+
+The device tree file has one node for each driver - the driver can store
+whatever properties it likes in there. See 'Writing Sandbox Drivers' below
+for more details on how to get drivers to read and write their state.
+
+
+Running and Booting
+-------------------
+
+Since there is no machine architecture, sandbox U-Boot cannot actually boot
+a kernel, but it does support the bootm command. Filesystems, memory
+commands, hashing, FIT images, verified boot and many other features are
+supported.
+
+When 'bootm' runs a kernel, sandbox will exit, as U-Boot does on a real
+machine. Of course in this case, no kernel is run.
+
+It is also possible to tell U-Boot that it has jumped from a temporary
+previous U-Boot binary, with the -j option. That binary is automatically
+removed by the U-Boot that gets the -j option. This allows you to write
+tests which emulate the action of chain-loading U-Boot, typically used in
+a situation where a second 'updatable' U-Boot is stored on your board. It
+is very risky to overwrite or upgrade the only U-Boot on a board, since a
+power or other failure will brick the board and require return to the
+manufacturer in the case of a consumer device.
+
+
+Supported Drivers
+-----------------
+
+U-Boot sandbox supports these emulations:
+
+- Block devices
+- Chrome OS EC
+- GPIO
+- Host filesystem (access files on the host from within U-Boot)
+- I2C
+- Keyboard (Chrome OS)
+- LCD
+- Network
+- Serial (for console only)
+- Sound (incomplete - see sandbox_sdl_sound_init() for details)
+- SPI
+- SPI flash
+- TPM (Trusted Platform Module)
+
+A wide range of commands are implemented. Filesystems which use a block
+device are supported.
+
+Also sandbox supports driver model (CONFIG_DM) and associated commands.
+
+
+Sandbox Variants
+----------------
+
+There are unfortunately quite a few variants at present:
+
+sandbox:
+ should be used for most tests
+sandbox64:
+ special build that forces a 64-bit host
+sandbox_flattree:
+ builds with dev_read\_...() functions defined as inline.
+ We need this build so that we can test those inline functions, and we
+ cannot build with both the inline functions and the non-inline functions
+ since they are named the same.
+sandbox_noblk:
+ builds without CONFIG_BLK, which means the legacy block
+ drivers are used. We cannot use both the legacy and driver-model block
+ drivers since they implement the same functions
+sandbox_spl:
+ builds sandbox with SPL support, so you can run spl/u-boot-spl
+ and it will start up and then load ./u-boot. It is also possible to
+ run ./u-boot directly.
+
+Of these sandbox_noblk can be removed once CONFIG_BLK is used everwhere, and
+sandbox_spl can probably be removed since it is a superset of sandbox.
+
+Most of the config options should be identical between these variants.
+
+
+Linux RAW Networking Bridge
+---------------------------
+
+The sandbox_eth_raw driver bridges traffic between the bottom of the network
+stack and the RAW sockets API in Linux. This allows much of the U-Boot network
+functionality to be tested in sandbox against real network traffic.
+
+For Ethernet network adapters, the bridge utilizes the RAW AF_PACKET API. This
+is needed to get access to the lowest level of the network stack in Linux. This
+means that all of the Ethernet frame is included. This allows the U-Boot network
+stack to be fully used. In other words, nothing about the Linux network stack is
+involved in forming the packets that end up on the wire. To receive the
+responses to packets sent from U-Boot the network interface has to be set to
+promiscuous mode so that the network card won't filter out packets not destined
+for its configured (on Linux) MAC address.
+
+The RAW sockets Ethernet API requires elevated privileges in Linux. You can
+either run as root, or you can add the capability needed like so::
+
+ sudo /sbin/setcap "CAP_NET_RAW+ep" /path/to/u-boot
+
+The default device tree for sandbox includes an entry for eth0 on the sandbox
+host machine whose alias is "eth1". The following are a few examples of network
+operations being tested on the eth0 interface.
+
+.. code-block:: none
+
+ sudo /path/to/u-boot -D
+
+ DHCP
+ ....
+
+ setenv autoload no
+ setenv ethrotate no
+ setenv ethact eth1
+ dhcp
+
+ PING
+ ....
+
+ setenv autoload no
+ setenv ethrotate no
+ setenv ethact eth1
+ dhcp
+ ping $gatewayip
+
+ TFTP
+ ....
+
+ setenv autoload no
+ setenv ethrotate no
+ setenv ethact eth1
+ dhcp
+ setenv serverip WWW.XXX.YYY.ZZZ
+ tftpboot u-boot.bin
+
+The bridge also supports (to a lesser extent) the localhost interface, 'lo'.
+
+The 'lo' interface cannot use the RAW AF_PACKET API because the lo interface
+doesn't support Ethernet-level traffic. It is a higher-level interface that is
+expected only to be used at the AF_INET level of the API. As such, the most raw
+we can get on that interface is the RAW AF_INET API on UDP. This allows us to
+set the IP_HDRINCL option to include everything except the Ethernet header in
+the packets we send and receive.
+
+Because only UDP is supported, ICMP traffic will not work, so expect that ping
+commands will time out.
+
+The default device tree for sandbox includes an entry for lo on the sandbox
+host machine whose alias is "eth5". The following is an example of a network
+operation being tested on the lo interface.
+
+.. code-block:: none
+
+ TFTP
+ ....
+
+ setenv ethrotate no
+ setenv ethact eth5
+ tftpboot u-boot.bin
+
+
+SPI Emulation
+-------------
+
+Sandbox supports SPI and SPI flash emulation.
+
+This is controlled by the spi_sf argument, the format of which is::
+
+ bus:cs:device:file
+
+ bus - SPI bus number
+ cs - SPI chip select number
+ device - SPI device emulation name
+ file - File on disk containing the data
+
+For example::
+
+ dd if=/dev/zero of=spi.bin bs=1M count=4
+ ./u-boot --spi_sf 0:0:M25P16:spi.bin
+
+With this setup you can issue SPI flash commands as normal::
+
+ =>sf probe
+ SF: Detected M25P16 with page size 64 KiB, total 2 MiB
+ =>sf read 0 0 10000
+ SF: 65536 bytes @ 0x0 Read: OK
+
+Since this is a full SPI emulation (rather than just flash), you can
+also use low-level SPI commands::
+
+ =>sspi 0:0 32 9f
+ FF202015
+
+This is issuing a READ_ID command and getting back 20 (ST Micro) part
+0x2015 (the M25P16).
+
+Drivers are connected to a particular bus/cs using sandbox's state
+structure (see the 'spi' member). A set of operations must be provided
+for each driver.
+
+
+Configuration settings for the curious are:
+
+CONFIG_SANDBOX_SPI_MAX_BUS:
+ The maximum number of SPI buses supported by the driver (default 1).
+
+CONFIG_SANDBOX_SPI_MAX_CS:
+ The maximum number of chip selects supported by the driver (default 10).
+
+CONFIG_SPI_IDLE_VAL:
+ The idle value on the SPI bus
+
+
+Block Device Emulation
+----------------------
+
+U-Boot can use raw disk images for block device emulation. To e.g. list
+the contents of the root directory on the second partion of the image
+"disk.raw", you can use the following commands::
+
+ =>host bind 0 ./disk.raw
+ =>ls host 0:2
+
+A disk image can be created using the following commands::
+
+ $> truncate -s 1200M ./disk.raw
+ $> echo -e "label: gpt\n,64M,U\n,,L" | /usr/sbin/sgdisk ./disk.raw
+ $> lodev=`sudo losetup -P -f --show ./disk.raw`
+ $> sudo mkfs.vfat -n EFI -v ${lodev}p1
+ $> sudo mkfs.ext4 -L ROOT -v ${lodev}p2
+
+or utilize the device described in test/py/make_test_disk.py::
+
+ #!/usr/bin/python
+ import make_test_disk
+ make_test_disk.makeDisk()
+
+Writing Sandbox Drivers
+-----------------------
+
+Generally you should put your driver in a file containing the word 'sandbox'
+and put it in the same directory as other drivers of its type. You can then
+implement the same hooks as the other drivers.
+
+To access U-Boot's emulated memory, use map_sysmem() as mentioned above.
+
+If your driver needs to store configuration or state (such as SPI flash
+contents or emulated chip registers), you can use the device tree as
+described above. Define handlers for this with the SANDBOX_STATE_IO macro.
+See arch/sandbox/include/asm/state.h for documentation. In short you provide
+a node name, compatible string and functions to read and write the state.
+Since writing the state can expand the device tree, you may need to use
+state_setprop() which does this automatically and avoids running out of
+space. See existing code for examples.
+
+
+Debugging the init sequence
+---------------------------
+
+If you get a failure in the initcall sequence, like this::
+
+ initcall sequence 0000560775957c80 failed at call 0000000000048134 (err=-96)
+
+Then you use can use grep to see which init call failed, e.g.::
+
+ $ grep 0000000000048134 u-boot.map
+ stdio_add_devices
+
+Of course another option is to run it with a debugger such as gdb::
+
+ $ gdb u-boot
+ ...
+ (gdb) br initcall.h:41
+ Breakpoint 1 at 0x4db9d: initcall.h:41. (2 locations)
+
+Note that two locations are reported, since this function is used in both
+board_init_f() and board_init_r().
+
+.. code-block:: none
+
+ (gdb) r
+ Starting program: /tmp/b/sandbox/u-boot
+ [Thread debugging using libthread_db enabled]
+ Using host libthread_db library "/lib/x86_64-linux-gnu/libthread_db.so.1".
+
+ U-Boot 2018.09-00264-ge0c2ba9814-dirty (Sep 22 2018 - 12:21:46 -0600)
+
+ DRAM: 128 MiB
+ MMC:
+
+ Breakpoint 1, initcall_run_list (init_sequence=0x5555559619e0 <init_sequence_f>)
+ at /scratch/sglass/cosarm/src/third_party/u-boot/files/include/initcall.h:41
+ 41 printf("initcall sequence %p failed at call %p (err=%d)\n",
+ (gdb) print *init_fnc_ptr
+ $1 = (const init_fnc_t) 0x55555559c114 <stdio_add_devices>
+ (gdb)
+
+
+This approach can be used on normal boards as well as sandbox.
+
+
+SDL_CONFIG
+----------
+
+If sdl-config is on a different path from the default, set the SDL_CONFIG
+environment variable to the correct pathname before building U-Boot.
+
+
+Using valgrind / memcheck
+-------------------------
+
+It is possible to run U-Boot under valgrind to check memory allocations::
+
+ valgrind u-boot
+
+If you are running sandbox SPL or TPL, then valgrind will not by default
+notice when U-Boot jumps from TPL to SPL, or from SPL to U-Boot proper. To
+fix this, use::
+
+ valgrind --trace-children=yes u-boot
+
+
+Testing
+-------
+
+U-Boot sandbox can be used to run various tests, mostly in the test/
+directory. These include:
+
+command_ut:
+ Unit tests for command parsing and handling
+compression:
+ Unit tests for U-Boot's compression algorithms, useful for
+ security checking. It supports gzip, bzip2, lzma and lzo.
+driver model:
+ Run this pytest::
+
+ ./test/py/test.py --bd sandbox --build -k ut_dm -v
+
+image:
+ Unit tests for images:
+ test/image/test-imagetools.sh - multi-file images
+ test/image/test-fit.py - FIT images
+tracing:
+ test/trace/test-trace.sh tests the tracing system (see README.trace)
+verified boot:
+ See test/vboot/vboot_test.sh for this
+
+If you change or enhance any of the above subsystems, you shold write or
+expand a test and include it with your patch series submission. Test
+coverage in U-Boot is limited, as we need to work to improve it.
+
+Note that many of these tests are implemented as commands which you can
+run natively on your board if desired (and enabled).
+
+To run all tests use "make check".
+
+
+Memory Map
+----------
+
+Sandbox has its own emulated memory starting at 0. Here are some of the things
+that are mapped into that memory:
+
+======= ======================== ===============================
+Addr Config Usage
+======= ======================== ===============================
+ 0 CONFIG_SYS_FDT_LOAD_ADDR Device tree
+ e000 CONFIG_BLOBLIST_ADDR Blob list
+ 10000 CONFIG_MALLOC_F_ADDR Early memory allocation
+ f0000 CONFIG_PRE_CON_BUF_ADDR Pre-console buffer
+ 100000 CONFIG_TRACE_EARLY_ADDR Early trace buffer (if enabled)
+======= ======================== ===============================
diff --git a/doc/arch/sh.rst b/doc/arch/sh.rst
new file mode 100644
index 0000000..3a3f92d
--- /dev/null
+++ b/doc/arch/sh.rst
@@ -0,0 +1,106 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (c) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigaur.org>
+
+SuperH
+======
+
+What's this?
+------------
+This file contains status information for the port of U-Boot to the
+Renesas SuperH series of CPUs.
+
+Overview
+--------
+SuperH has an original boot loader. However, source code is dirty, and
+maintenance is not done. To improve sharing and the maintenance of the code,
+Nobuhiro Iwamatsu started the porting to U-Boot in 2007.
+
+Supported CPUs
+--------------
+
+Renesas SH7750/SH7750R
+^^^^^^^^^^^^^^^^^^^^^^
+This CPU has the SH4 core.
+
+Renesas SH7722
+^^^^^^^^^^^^^^
+This CPU has the SH4AL-DSP core.
+
+Renesas SH7780
+^^^^^^^^^^^^^^
+This CPU has the SH4A core.
+
+Supported Boards
+----------------
+
+Hitachi UL MS7750SE01/MS7750RSE01
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+Board specific code is in board/ms7750se
+To use this board, type "make ms7750se_config".
+Support devices are:
+
+ - SCIF
+ - SDRAM
+ - NOR Flash
+ - Marubun PCMCIA
+
+Hitachi UL MS7722SE01
+^^^^^^^^^^^^^^^^^^^^^
+Board specific code is in board/ms7722se
+To use this board, type "make ms7722se_config".
+Support devices are:
+
+ - SCIF
+ - SDRAM
+ - NOR Flash
+ - Marubun PCMCIA
+ - SMC91x ethernet
+
+Hitachi UL MS7720ERP01
+^^^^^^^^^^^^^^^^^^^^^^
+Board specific code is in board/ms7720se
+To use this board, type "make ms7720se_config".
+Support devices are:
+
+ - SCIF
+ - SDRAM
+ - NOR Flash
+ - Marubun PCMCIA
+
+Renesas R7780MP
+^^^^^^^^^^^^^^^
+Board specific code is in board/r7780mp
+To use this board, type "make r7780mp_config".
+Support devices are:
+
+ - SCIF
+ - DDR-SDRAM
+ - NOR Flash
+ - Compact Flash
+ - ASIX ethernet
+ - SH7780 PCI bridge
+ - RTL8110 ethernet
+
+In SuperH, S-record and binary of made u-boot work on the memory.
+When u-boot is written in the flash, it is necessary to change the
+address by using 'objcopy'::
+
+ ex) shX-linux-objcopy -Ibinary -Osrec u-boot.bin u-boot.flash.srec
+
+Compiler
+--------
+You can use the following of u-boot to compile.
+ - `SuperH Linux Open site <http://www.superh-linux.org/>`_
+ - `KPIT GNU tools <http://www.kpitgnutools.com/>`_
+
+Future
+------
+I plan to support the following CPUs and boards.
+
+CPUs
+^^^^
+- SH7751R(SH4)
+
+Boards
+^^^^^^
+Many boards ;-)
diff --git a/doc/arch/x86.rst b/doc/arch/x86.rst
new file mode 100644
index 0000000..a441738
--- /dev/null
+++ b/doc/arch/x86.rst
@@ -0,0 +1,729 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (C) 2014, Simon Glass <sjg@chromium.org>
+.. Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+
+x86
+===
+
+This document describes the information about U-Boot running on x86 targets,
+including supported boards, build instructions, todo list, etc.
+
+Status
+------
+U-Boot supports running as a `coreboot`_ payload on x86. So far only Link
+(Chromebook Pixel) and `QEMU`_ x86 targets have been tested, but it should
+work with minimal adjustments on other x86 boards since coreboot deals with
+most of the low-level details.
+
+U-Boot is a main bootloader on Intel Edison board.
+
+U-Boot also supports booting directly from x86 reset vector, without coreboot.
+In this case, known as bare mode, from the fact that it runs on the
+'bare metal', U-Boot acts like a BIOS replacement. The following platforms
+are supported:
+
+ - Bayley Bay CRB
+ - Cherry Hill CRB
+ - Congatec QEVAL 2.0 & conga-QA3/E3845
+ - Cougar Canyon 2 CRB
+ - Crown Bay CRB
+ - Galileo
+ - Link (Chromebook Pixel)
+ - Minnowboard MAX
+ - Samus (Chromebook Pixel 2015)
+ - QEMU x86 (32-bit & 64-bit)
+
+As for loading an OS, U-Boot supports directly booting a 32-bit or 64-bit
+Linux kernel as part of a FIT image. It also supports a compressed zImage.
+U-Boot supports loading an x86 VxWorks kernel. Please check README.vxworks
+for more details.
+
+Build Instructions for U-Boot as BIOS replacement (bare mode)
+-------------------------------------------------------------
+Building a ROM version of U-Boot (hereafter referred to as u-boot.rom) is a
+little bit tricky, as generally it requires several binary blobs which are not
+shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is
+not turned on by default in the U-Boot source tree. Firstly, you need turn it
+on by enabling the ROM build either via an environment variable::
+
+ $ export BUILD_ROM=y
+
+or via configuration::
+
+ CONFIG_BUILD_ROM=y
+
+Both tell the Makefile to build u-boot.rom as a target.
+
+CPU Microcode
+-------------
+Modern CPUs usually require a special bit stream called `microcode`_ to be
+loaded on the processor after power up in order to function properly. U-Boot
+has already integrated these as hex dumps in the source tree.
+
+SMP Support
+-----------
+On a multicore system, U-Boot is executed on the bootstrap processor (BSP).
+Additional application processors (AP) can be brought up by U-Boot. In order to
+have an SMP kernel to discover all of the available processors, U-Boot needs to
+prepare configuration tables which contain the multi-CPUs information before
+loading the OS kernel. Currently U-Boot supports generating two types of tables
+for SMP, called Simple Firmware Interface (`SFI`_) and Multi-Processor (`MP`_)
+tables. The writing of these two tables are controlled by two Kconfig
+options GENERATE_SFI_TABLE and GENERATE_MP_TABLE.
+
+Driver Model
+------------
+x86 has been converted to use driver model for serial, GPIO, SPI, SPI flash,
+keyboard, real-time clock, USB. Video is in progress.
+
+Device Tree
+-----------
+x86 uses device tree to configure the board thus requires CONFIG_OF_CONTROL to
+be turned on. Not every device on the board is configured via device tree, but
+more and more devices will be added as time goes by. Check out the directory
+arch/x86/dts/ for these device tree source files.
+
+Useful Commands
+---------------
+In keeping with the U-Boot philosophy of providing functions to check and
+adjust internal settings, there are several x86-specific commands that may be
+useful:
+
+fsp
+ Display information about Intel Firmware Support Package (FSP).
+ This is only available on platforms which use FSP, mostly Atom.
+iod
+ Display I/O memory
+iow
+ Write I/O memory
+mtrr
+ List and set the Memory Type Range Registers (MTRR). These are used to
+ tell the CPU whether memory is cacheable and if so the cache write
+ mode to use. U-Boot sets up some reasonable values but you can
+ adjust then with this command.
+
+Booting Ubuntu
+--------------
+As an example of how to set up your boot flow with U-Boot, here are
+instructions for starting Ubuntu from U-Boot. These instructions have been
+tested on Minnowboard MAX with a SATA drive but are equally applicable on
+other platforms and other media. There are really only four steps and it's a
+very simple script, but a more detailed explanation is provided here for
+completeness.
+
+Note: It is possible to set up U-Boot to boot automatically using syslinux.
+It could also use the grub.cfg file (/efi/ubuntu/grub.cfg) to obtain the
+GUID. If you figure these out, please post patches to this README.
+
+Firstly, you will need Ubuntu installed on an available disk. It should be
+possible to make U-Boot start a USB start-up disk but for now let's assume
+that you used another boot loader to install Ubuntu.
+
+Use the U-Boot command line to find the UUID of the partition you want to
+boot. For example our disk is SCSI device 0::
+
+ => part list scsi 0
+
+ Partition Map for SCSI device 0 -- Partition Type: EFI
+
+ Part Start LBA End LBA Name
+ Attributes
+ Type GUID
+ Partition GUID
+ 1 0x00000800 0x001007ff ""
+ attrs: 0x0000000000000000
+ type: c12a7328-f81f-11d2-ba4b-00a0c93ec93b
+ guid: 9d02e8e4-4d59-408f-a9b0-fd497bc9291c
+ 2 0x00100800 0x037d8fff ""
+ attrs: 0x0000000000000000
+ type: 0fc63daf-8483-4772-8e79-3d69d8477de4
+ guid: 965c59ee-1822-4326-90d2-b02446050059
+ 3 0x037d9000 0x03ba27ff ""
+ attrs: 0x0000000000000000
+ type: 0657fd6d-a4ab-43c4-84e5-0933c84b4f4f
+ guid: 2c4282bd-1e82-4bcf-a5ff-51dedbf39f17
+ =>
+
+This shows that your SCSI disk has three partitions. The really long hex
+strings are called Globally Unique Identifiers (GUIDs). You can look up the
+'type' ones `here`_. On this disk the first partition is for EFI and is in
+VFAT format (DOS/Windows)::
+
+ => fatls scsi 0:1
+ efi/
+
+ 0 file(s), 1 dir(s)
+
+
+Partition 2 is 'Linux filesystem data' so that will be our root disk. It is
+in ext2 format::
+
+ => ext2ls scsi 0:2
+ <DIR> 4096 .
+ <DIR> 4096 ..
+ <DIR> 16384 lost+found
+ <DIR> 4096 boot
+ <DIR> 12288 etc
+ <DIR> 4096 media
+ <DIR> 4096 bin
+ <DIR> 4096 dev
+ <DIR> 4096 home
+ <DIR> 4096 lib
+ <DIR> 4096 lib64
+ <DIR> 4096 mnt
+ <DIR> 4096 opt
+ <DIR> 4096 proc
+ <DIR> 4096 root
+ <DIR> 4096 run
+ <DIR> 12288 sbin
+ <DIR> 4096 srv
+ <DIR> 4096 sys
+ <DIR> 4096 tmp
+ <DIR> 4096 usr
+ <DIR> 4096 var
+ <SYM> 33 initrd.img
+ <SYM> 30 vmlinuz
+ <DIR> 4096 cdrom
+ <SYM> 33 initrd.img.old
+ =>
+
+and if you look in the /boot directory you will see the kernel::
+
+ => ext2ls scsi 0:2 /boot
+ <DIR> 4096 .
+ <DIR> 4096 ..
+ <DIR> 4096 efi
+ <DIR> 4096 grub
+ 3381262 System.map-3.13.0-32-generic
+ 1162712 abi-3.13.0-32-generic
+ 165611 config-3.13.0-32-generic
+ 176500 memtest86+.bin
+ 178176 memtest86+.elf
+ 178680 memtest86+_multiboot.bin
+ 5798112 vmlinuz-3.13.0-32-generic
+ 165762 config-3.13.0-58-generic
+ 1165129 abi-3.13.0-58-generic
+ 5823136 vmlinuz-3.13.0-58-generic
+ 19215259 initrd.img-3.13.0-58-generic
+ 3391763 System.map-3.13.0-58-generic
+ 5825048 vmlinuz-3.13.0-58-generic.efi.signed
+ 28304443 initrd.img-3.13.0-32-generic
+ =>
+
+The 'vmlinuz' files contain a packaged Linux kernel. The format is a kind of
+self-extracting compressed file mixed with some 'setup' configuration data.
+Despite its size (uncompressed it is >10MB) this only includes a basic set of
+device drivers, enough to boot on most hardware types.
+
+The 'initrd' files contain a RAM disk. This is something that can be loaded
+into RAM and will appear to Linux like a disk. Ubuntu uses this to hold lots
+of drivers for whatever hardware you might have. It is loaded before the
+real root disk is accessed.
+
+The numbers after the end of each file are the version. Here it is Linux
+version 3.13. You can find the source code for this in the Linux tree with
+the tag v3.13. The '.0' allows for additional Linux releases to fix problems,
+but normally this is not needed. The '-58' is used by Ubuntu. Each time they
+release a new kernel they increment this number. New Ubuntu versions might
+include kernel patches to fix reported bugs. Stable kernels can exist for
+some years so this number can get quite high.
+
+The '.efi.signed' kernel is signed for EFI's secure boot. U-Boot has its own
+secure boot mechanism - see `this`_ & `that`_. It cannot read .efi files
+at present.
+
+To boot Ubuntu from U-Boot the steps are as follows:
+
+1. Set up the boot arguments. Use the GUID for the partition you want to boot::
+
+ => setenv bootargs root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro
+
+Here root= tells Linux the location of its root disk. The disk is specified
+by its GUID, using '/dev/disk/by-partuuid/', a Linux path to a 'directory'
+containing all the GUIDs Linux has found. When it starts up, there will be a
+file in that directory with this name in it. It is also possible to use a
+device name here, see later.
+
+2. Load the kernel. Since it is an ext2/4 filesystem we can do::
+
+ => ext2load scsi 0:2 03000000 /boot/vmlinuz-3.13.0-58-generic
+
+The address 30000000 is arbitrary, but there seem to be problems with using
+small addresses (sometimes Linux cannot find the ramdisk). This is 48MB into
+the start of RAM (which is at 0 on x86).
+
+3. Load the ramdisk (to 64MB)::
+
+ => ext2load scsi 0:2 04000000 /boot/initrd.img-3.13.0-58-generic
+
+4. Start up the kernel. We need to know the size of the ramdisk, but can use
+ a variable for that. U-Boot sets 'filesize' to the size of the last file it
+ loaded::
+
+ => zboot 03000000 0 04000000 ${filesize}
+
+Type 'help zboot' if you want to see what the arguments are. U-Boot on x86 is
+quite verbose when it boots a kernel. You should see these messages from
+U-Boot::
+
+ Valid Boot Flag
+ Setup Size = 0x00004400
+ Magic signature found
+ Using boot protocol version 2.0c
+ Linux kernel version 3.13.0-58-generic (buildd@allspice) #97-Ubuntu SMP Wed Jul 8 02:56:15 UTC 2015
+ Building boot_params at 0x00090000
+ Loading bzImage at address 100000 (5805728 bytes)
+ Magic signature found
+ Initial RAM disk at linear address 0x04000000, size 19215259 bytes
+ Kernel command line: "root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro"
+
+ Starting kernel ...
+
+U-Boot prints out some bootstage timing. This is more useful if you put the
+above commands into a script since then it will be faster::
+
+ Timer summary in microseconds:
+ Mark Elapsed Stage
+ 0 0 reset
+ 241,535 241,535 board_init_r
+ 2,421,611 2,180,076 id=64
+ 2,421,790 179 id=65
+ 2,428,215 6,425 main_loop
+ 48,860,584 46,432,369 start_kernel
+
+ Accumulated time:
+ 240,329 ahci
+ 1,422,704 vesa display
+
+Now the kernel actually starts (if you want to examine kernel boot up message on
+the serial console, append "console=ttyS0,115200" to the kernel command line)::
+
+ [ 0.000000] Initializing cgroup subsys cpuset
+ [ 0.000000] Initializing cgroup subsys cpu
+ [ 0.000000] Initializing cgroup subsys cpuacct
+ [ 0.000000] Linux version 3.13.0-58-generic (buildd@allspice) (gcc version 4.8.2 (Ubuntu 4.8.2-19ubuntu1) ) #97-Ubuntu SMP Wed Jul 8 02:56:15 UTC 2015 (Ubuntu 3.13.0-58.97-generic 3.13.11-ckt22)
+ [ 0.000000] Command line: root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro console=ttyS0,115200
+
+It continues for a long time. Along the way you will see it pick up your
+ramdisk::
+
+ [ 0.000000] RAMDISK: [mem 0x04000000-0x05253fff]
+ ...
+ [ 0.788540] Trying to unpack rootfs image as initramfs...
+ [ 1.540111] Freeing initrd memory: 18768K (ffff880004000000 - ffff880005254000)
+ ...
+
+Later it actually starts using it::
+
+ Begin: Running /scripts/local-premount ... done.
+
+You should also see your boot disk turn up::
+
+ [ 4.357243] scsi 1:0:0:0: Direct-Access ATA ADATA SP310 5.2 PQ: 0 ANSI: 5
+ [ 4.366860] sd 1:0:0:0: [sda] 62533296 512-byte logical blocks: (32.0 GB/29.8 GiB)
+ [ 4.375677] sd 1:0:0:0: Attached scsi generic sg0 type 0
+ [ 4.381859] sd 1:0:0:0: [sda] Write Protect is off
+ [ 4.387452] sd 1:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
+ [ 4.399535] sda: sda1 sda2 sda3
+
+Linux has found the three partitions (sda1-3). Mercifully it doesn't print out
+the GUIDs. In step 1 above we could have used::
+
+ setenv bootargs root=/dev/sda2 ro
+
+instead of the GUID. However if you add another drive to your board the
+numbering may change whereas the GUIDs will not. So if your boot partition
+becomes sdb2, it will still boot. For embedded systems where you just want to
+boot the first disk, you have that option.
+
+The last thing you will see on the console is mention of plymouth (which
+displays the Ubuntu start-up screen) and a lot of 'Starting' messages::
+
+ * Starting Mount filesystems on boot [ OK ]
+
+After a pause you should see a login screen on your display and you are done.
+
+If you want to put this in a script you can use something like this::
+
+ setenv bootargs root=UUID=b2aaf743-0418-4d90-94cc-3e6108d7d968 ro
+ setenv boot zboot 03000000 0 04000000 \${filesize}
+ setenv bootcmd "ext2load scsi 0:2 03000000 /boot/vmlinuz-3.13.0-58-generic; ext2load scsi 0:2 04000000 /boot/initrd.img-3.13.0-58-generic; run boot"
+ saveenv
+
+The \ is to tell the shell not to evaluate ${filesize} as part of the setenv
+command.
+
+You can also bake this behaviour into your build by hard-coding the
+environment variables if you add this to minnowmax.h:
+
+.. code-block:: c
+
+ #undef CONFIG_BOOTCOMMAND
+ #define CONFIG_BOOTCOMMAND \
+ "ext2load scsi 0:2 03000000 /boot/vmlinuz-3.13.0-58-generic; " \
+ "ext2load scsi 0:2 04000000 /boot/initrd.img-3.13.0-58-generic; " \
+ "run boot"
+
+ #undef CONFIG_EXTRA_ENV_SETTINGS
+ #define CONFIG_EXTRA_ENV_SETTINGS "boot=zboot 03000000 0 04000000 ${filesize}"
+
+and change CONFIG_BOOTARGS value in configs/minnowmax_defconfig to::
+
+ CONFIG_BOOTARGS="root=/dev/sda2 ro"
+
+Test with SeaBIOS
+-----------------
+`SeaBIOS`_ is an open source implementation of a 16-bit x86 BIOS. It can run
+in an emulator or natively on x86 hardware with the use of U-Boot. With its
+help, we can boot some OSes that require 16-bit BIOS services like Windows/DOS.
+
+As U-Boot, we have to manually create a table where SeaBIOS gets various system
+information (eg: E820) from. The table unfortunately has to follow the coreboot
+table format as SeaBIOS currently supports booting as a coreboot payload.
+
+To support loading SeaBIOS, U-Boot should be built with CONFIG_SEABIOS on.
+Booting SeaBIOS is done via U-Boot's bootelf command, like below::
+
+ => tftp bios.bin.elf;bootelf
+ Using e1000#0 device
+ TFTP from server 10.10.0.100; our IP address is 10.10.0.108
+ ...
+ Bytes transferred = 122124 (1dd0c hex)
+ ## Starting application at 0x000ff06e ...
+ SeaBIOS (version rel-1.9.0)
+ ...
+
+bios.bin.elf is the SeaBIOS image built from SeaBIOS source tree.
+Make sure it is built as follows::
+
+ $ make menuconfig
+
+Inside the "General Features" menu, select "Build for coreboot" as the
+"Build Target". Inside the "Debugging" menu, turn on "Serial port debugging"
+so that we can see something as soon as SeaBIOS boots. Leave other options
+as in their default state. Then::
+
+ $ make
+ ...
+ Total size: 121888 Fixed: 66496 Free: 9184 (used 93.0% of 128KiB rom)
+ Creating out/bios.bin.elf
+
+Currently this is tested on QEMU x86 target with U-Boot chain-loading SeaBIOS
+to install/boot a Windows XP OS (below for example command to install Windows).
+
+.. code-block:: none
+
+ # Create a 10G disk.img as the virtual hard disk
+ $ qemu-img create -f qcow2 disk.img 10G
+
+ # Install a Windows XP OS from an ISO image 'winxp.iso'
+ $ qemu-system-i386 -serial stdio -bios u-boot.rom -hda disk.img -cdrom winxp.iso -smp 2 -m 512
+
+ # Boot a Windows XP OS installed on the virutal hard disk
+ $ qemu-system-i386 -serial stdio -bios u-boot.rom -hda disk.img -smp 2 -m 512
+
+This is also tested on Intel Crown Bay board with a PCIe graphics card, booting
+SeaBIOS then chain-loading a GRUB on a USB drive, then Linux kernel finally.
+
+If you are using Intel Integrated Graphics Device (IGD) as the primary display
+device on your board, SeaBIOS needs to be patched manually to get its VGA ROM
+loaded and run by SeaBIOS. SeaBIOS locates VGA ROM via the PCI expansion ROM
+register, but IGD device does not have its VGA ROM mapped by this register.
+Its VGA ROM is packaged as part of u-boot.rom at a configurable flash address
+which is unknown to SeaBIOS. An example patch is needed for SeaBIOS below:
+
+.. code-block:: none
+
+ diff --git a/src/optionroms.c b/src/optionroms.c
+ index 65f7fe0..c7b6f5e 100644
+ --- a/src/optionroms.c
+ +++ b/src/optionroms.c
+ @@ -324,6 +324,8 @@ init_pcirom(struct pci_device *pci, int isvga, u64 *sources)
+ rom = deploy_romfile(file);
+ else if (RunPCIroms > 1 || (RunPCIroms == 1 && isvga))
+ rom = map_pcirom(pci);
+ + if (pci->bdf == pci_to_bdf(0, 2, 0))
+ + rom = (struct rom_header *)0xfff90000;
+ if (! rom)
+ // No ROM present.
+ return;
+
+Note: the patch above expects IGD device is at PCI b.d.f 0.2.0 and its VGA ROM
+is at 0xfff90000 which corresponds to CONFIG_VGA_BIOS_ADDR on Minnowboard MAX.
+Change these two accordingly if this is not the case on your board.
+
+Development Flow
+----------------
+These notes are for those who want to port U-Boot to a new x86 platform.
+
+Since x86 CPUs boot from SPI flash, a SPI flash emulator is a good investment.
+The Dediprog em100 can be used on Linux.
+
+The em100 tool is available here: http://review.coreboot.org/p/em100.git
+
+On Minnowboard Max the following command line can be used::
+
+ sudo em100 -s -p LOW -d u-boot.rom -c W25Q64DW -r
+
+A suitable clip for connecting over the SPI flash chip is here:
+http://www.dediprog.com/pd/programmer-accessories/EM-TC-8.
+
+This allows you to override the SPI flash contents for development purposes.
+Typically you can write to the em100 in around 1200ms, considerably faster
+than programming the real flash device each time. The only important
+limitation of the em100 is that it only supports SPI bus speeds up to 20MHz.
+This means that images must be set to boot with that speed. This is an
+Intel-specific feature - e.g. tools/ifttool has an option to set the SPI
+speed in the SPI descriptor region.
+
+If your chip/board uses an Intel Firmware Support Package (FSP) it is fairly
+easy to fit it in. You can follow the Minnowboard Max implementation, for
+example. Hopefully you will just need to create new files similar to those
+in arch/x86/cpu/baytrail which provide Bay Trail support.
+
+If you are not using an FSP you have more freedom and more responsibility.
+The ivybridge support works this way, although it still uses a ROM for
+graphics and still has binary blobs containing Intel code. You should aim to
+support all important peripherals on your platform including video and storage.
+Use the device tree for configuration where possible.
+
+For the microcode you can create a suitable device tree file using the
+microcode tool::
+
+ ./tools/microcode-tool -d microcode.dat -m <model> create
+
+or if you only have header files and not the full Intel microcode.dat database::
+
+ ./tools/microcode-tool -H BAY_TRAIL_FSP_KIT/Microcode/M0130673322.h \
+ -H BAY_TRAIL_FSP_KIT/Microcode/M0130679901.h -m all create
+
+These are written to arch/x86/dts/microcode/ by default.
+
+Note that it is possible to just add the micrcode for your CPU if you know its
+model. U-Boot prints this information when it starts::
+
+ CPU: x86_64, vendor Intel, device 30673h
+
+so here we can use the M0130673322 file.
+
+If you platform can display POST codes on two little 7-segment displays on
+the board, then you can use post_code() calls from C or assembler to monitor
+boot progress. This can be good for debugging.
+
+If not, you can try to get serial working as early as possible. The early
+debug serial port may be useful here. See setup_internal_uart() for an example.
+
+During the U-Boot porting, one of the important steps is to write correct PIRQ
+routing information in the board device tree. Without it, device drivers in the
+Linux kernel won't function correctly due to interrupt is not working. Please
+refer to U-Boot `doc <doc/device-tree-bindings/misc/intel,irq-router.txt>`_ for
+the device tree bindings of Intel interrupt router. Here we have more details
+on the intel,pirq-routing property below.
+
+.. code-block:: none
+
+ intel,pirq-routing = <
+ PCI_BDF(0, 2, 0) INTA PIRQA
+ ...
+ >;
+
+As you see each entry has 3 cells. For the first one, we need describe all pci
+devices mounted on the board. For SoC devices, normally there is a chapter on
+the chipset datasheet which lists all the available PCI devices. For example on
+Bay Trail, this is chapter 4.3 (PCI configuration space). For the second one, we
+can get the interrupt pin either from datasheet or hardware via U-Boot shell.
+The reliable source is the hardware as sometimes chipset datasheet is not 100%
+up-to-date. Type 'pci header' plus the device's pci bus/device/function number
+from U-Boot shell below::
+
+ => pci header 0.1e.1
+ vendor ID = 0x8086
+ device ID = 0x0f08
+ ...
+ interrupt line = 0x09
+ interrupt pin = 0x04
+ ...
+
+It shows this PCI device is using INTD pin as it reports 4 in the interrupt pin
+register. Repeat this until you get interrupt pins for all the devices. The last
+cell is the PIRQ line which a particular interrupt pin is mapped to. On Intel
+chipset, the power-up default mapping is INTA/B/C/D maps to PIRQA/B/C/D. This
+can be changed by registers in LPC bridge. So far Intel FSP does not touch those
+registers so we can write down the PIRQ according to the default mapping rule.
+
+Once we get the PIRQ routing information in the device tree, the interrupt
+allocation and assignment will be done by U-Boot automatically. Now you can
+enable CONFIG_GENERATE_PIRQ_TABLE for testing Linux kernel using i8259 PIC and
+CONFIG_GENERATE_MP_TABLE for testing Linux kernel using local APIC and I/O APIC.
+
+This script might be useful. If you feed it the output of 'pci long' from
+U-Boot then it will generate a device tree fragment with the interrupt
+configuration for each device (note it needs gawk 4.0.0)::
+
+ $ cat console_output |awk '/PCI/ {device=$4} /interrupt line/ {line=$4} \
+ /interrupt pin/ {pin = $4; if (pin != "0x00" && pin != "0xff") \
+ {patsplit(device, bdf, "[0-9a-f]+"); \
+ printf "PCI_BDF(%d, %d, %d) INT%c PIRQ%c\n", strtonum("0x" bdf[1]), \
+ strtonum("0x" bdf[2]), bdf[3], strtonum(pin) + 64, 64 + strtonum(pin)}}'
+
+Example output::
+
+ PCI_BDF(0, 2, 0) INTA PIRQA
+ PCI_BDF(0, 3, 0) INTA PIRQA
+ ...
+
+Porting Hints
+-------------
+
+Quark-specific considerations
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+To port U-Boot to other boards based on the Intel Quark SoC, a few things need
+to be taken care of. The first important part is the Memory Reference Code (MRC)
+parameters. Quark MRC supports memory-down configuration only. All these MRC
+parameters are supplied via the board device tree. To get started, first copy
+the MRC section of arch/x86/dts/galileo.dts to your board's device tree, then
+change these values by consulting board manuals or your hardware vendor.
+Available MRC parameter values are listed in include/dt-bindings/mrc/quark.h.
+The other tricky part is with PCIe. Quark SoC integrates two PCIe root ports,
+but by default they are held in reset after power on. In U-Boot, PCIe
+initialization is properly handled as per Quark's firmware writer guide.
+In your board support codes, you need provide two routines to aid PCIe
+initialization, which are board_assert_perst() and board_deassert_perst().
+The two routines need implement a board-specific mechanism to assert/deassert
+PCIe PERST# pin. Care must be taken that in those routines that any APIs that
+may trigger PCI enumeration process are strictly forbidden, as any access to
+PCIe root port's configuration registers will cause system hang while it is
+held in reset. For more details, check how they are implemented by the Intel
+Galileo board support codes in board/intel/galileo/galileo.c.
+
+coreboot
+^^^^^^^^
+
+See scripts/coreboot.sed which can assist with porting coreboot code into
+U-Boot drivers. It will not resolve all build errors, but will perform common
+transformations. Remember to add attribution to coreboot for new files added
+to U-Boot. This should go at the top of each file and list the coreboot
+filename where the code originated.
+
+Debugging ACPI issues with Windows
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Windows might cache system information and only detect ACPI changes if you
+modify the ACPI table versions. So tweak them liberally when debugging ACPI
+issues with Windows.
+
+ACPI Support Status
+-------------------
+Advanced Configuration and Power Interface (`ACPI`_) aims to establish
+industry-standard interfaces enabling OS-directed configuration, power
+management, and thermal management of mobile, desktop, and server platforms.
+
+Linux can boot without ACPI with "acpi=off" command line parameter, but
+with ACPI the kernel gains the capabilities to handle power management.
+For Windows, ACPI is a must-have firmware feature since Windows Vista.
+CONFIG_GENERATE_ACPI_TABLE is the config option to turn on ACPI support in
+U-Boot. This requires Intel ACPI compiler to be installed on your host to
+compile ACPI DSDT table written in ASL format to AML format. You can get
+the compiler via "apt-get install iasl" if you are on Ubuntu or download
+the source from https://www.acpica.org/downloads to compile one by yourself.
+
+Current ACPI support in U-Boot is basically complete. More optional features
+can be added in the future. The status as of today is:
+
+ * Support generating RSDT, XSDT, FACS, FADT, MADT, MCFG tables.
+ * Support one static DSDT table only, compiled by Intel ACPI compiler.
+ * Support S0/S3/S4/S5, reboot and shutdown from OS.
+ * Support booting a pre-installed Ubuntu distribution via 'zboot' command.
+ * Support installing and booting Ubuntu 14.04 (or above) from U-Boot with
+ the help of SeaBIOS using legacy interface (non-UEFI mode).
+ * Support installing and booting Windows 8.1/10 from U-Boot with the help
+ of SeaBIOS using legacy interface (non-UEFI mode).
+ * Support ACPI interrupts with SCI only.
+
+Features that are optional:
+
+ * Dynamic AML bytecodes insertion at run-time. We may need this to support
+ SSDT table generation and DSDT fix up.
+ * SMI support. Since U-Boot is a modern bootloader, we don't want to bring
+ those legacy stuff into U-Boot. ACPI spec allows a system that does not
+ support SMI (a legacy-free system).
+
+ACPI was initially enabled on BayTrail based boards. Testing was done by booting
+a pre-installed Ubuntu 14.04 from a SATA drive. Installing Ubuntu 14.04 and
+Windows 8.1/10 to a SATA drive and booting from there is also tested. Most
+devices seem to work correctly and the board can respond a reboot/shutdown
+command from the OS.
+
+For other platform boards, ACPI support status can be checked by examining their
+board defconfig files to see if CONFIG_GENERATE_ACPI_TABLE is set to y.
+
+The S3 sleeping state is a low wake latency sleeping state defined by ACPI
+spec where all system context is lost except system memory. To test S3 resume
+with a Linux kernel, simply run "echo mem > /sys/power/state" and kernel will
+put the board to S3 state where the power is off. So when the power button is
+pressed again, U-Boot runs as it does in cold boot and detects the sleeping
+state via ACPI register to see if it is S3, if yes it means we are waking up.
+U-Boot is responsible for restoring the machine state as it is before sleep.
+When everything is done, U-Boot finds out the wakeup vector provided by OSes
+and jump there. To determine whether ACPI S3 resume is supported, check to
+see if CONFIG_HAVE_ACPI_RESUME is set for that specific board.
+
+Note for testing S3 resume with Windows, correct graphics driver must be
+installed for your platform, otherwise you won't find "Sleep" option in
+the "Power" submenu from the Windows start menu.
+
+EFI Support
+-----------
+U-Boot supports booting as a 32-bit or 64-bit EFI payload, e.g. with UEFI.
+This is enabled with CONFIG_EFI_STUB to boot from both 32-bit and 64-bit
+UEFI BIOS. U-Boot can also run as an EFI application, with CONFIG_EFI_APP.
+The CONFIG_EFI_LOADER option, where U-Boot provides an EFI environment to
+the kernel (i.e. replaces UEFI completely but provides the same EFI run-time
+services) is supported too. For example, we can even use 'bootefi' command
+to load a 'u-boot-payload.efi', see below test logs on QEMU.
+
+.. code-block:: none
+
+ => load ide 0 3000000 u-boot-payload.efi
+ 489787 bytes read in 138 ms (3.4 MiB/s)
+ => bootefi 3000000
+ Scanning disk ide.blk#0...
+ Found 2 disks
+ WARNING: booting without device tree
+ ## Starting EFI application at 03000000 ...
+ U-Boot EFI Payload
+
+
+ U-Boot 2018.07-rc2 (Jun 23 2018 - 17:12:58 +0800)
+
+ CPU: x86_64, vendor AMD, device 663h
+ DRAM: 2 GiB
+ MMC:
+ Video: 1024x768x32
+ Model: EFI x86 Payload
+ Net: e1000: 52:54:00:12:34:56
+
+ Warning: e1000#0 using MAC address from ROM
+ eth0: e1000#0
+ No controllers found
+ Hit any key to stop autoboot: 0
+
+See :doc:`../uefi/u-boot_on_efi` and :doc:`../uefi/uefi` for details of
+EFI support in U-Boot.
+
+TODO List
+---------
+- Audio
+- Chrome OS verified boot
+
+.. _coreboot: http://www.coreboot.org
+.. _QEMU: http://www.qemu.org
+.. _microcode: http://en.wikipedia.org/wiki/Microcode
+.. _SFI: http://simplefirmware.org
+.. _MP: http://www.intel.com/design/archives/processors/pro/docs/242016.htm
+.. _here: https://en.wikipedia.org/wiki/GUID_Partition_Table
+.. _this: http://events.linuxfoundation.org/sites/events/files/slides/chromeos_and_diy_vboot_0.pdf
+.. _that: http://events.linuxfoundation.org/sites/events/files/slides/elce-2014.pdf
+.. _SeaBIOS: http://www.seabios.org/SeaBIOS
+.. _ACPI: http://www.acpi.info
diff --git a/doc/arch/xtensa.rst b/doc/arch/xtensa.rst
new file mode 100644
index 0000000..176410d
--- /dev/null
+++ b/doc/arch/xtensa.rst
@@ -0,0 +1,99 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Xtensa
+======
+
+Xtensa Architecture and Diamond Cores
+-------------------------------------
+
+Xtensa is a configurable processor architecture from Tensilica, Inc.
+Diamond Cores are pre-configured instances available for license and
+SoC cores in the same manner as ARM, MIPS, etc.
+
+Xtensa licensees create their own Xtensa cores with selected features
+and custom instructions, registers and co-processors. The custom core
+is configured with Tensilica tools and built with Tensilica's Xtensa
+Processor Generator.
+
+There are an effectively infinite number of CPUs in the Xtensa
+architecture family. It is, however, not feasible to support individual
+Xtensa CPUs in U-Boot. Therefore, there is only a single 'xtensa' CPU
+in the cpu tree of U-Boot.
+
+In the same manner as the Linux port to Xtensa, U-Boot adapts to an
+individual Xtensa core configuration using a set of macros provided with
+the particular core. This is part of what is known as the hardware
+abstraction layer (HAL). For the purpose of U-Boot, the HAL consists only
+of a few header files. These provide CPP macros that customize sources,
+Makefiles, and the linker script.
+
+
+Adding support for an additional processor configuration
+--------------------------------------------------------
+
+The header files for one particular processor configuration are inside
+a variant-specific directory located in the arch/xtensa/include/asm
+directory. The name of that directory starts with 'arch-' followed by
+the name for the processor configuration, for example, arch-dc233c for
+the Diamond DC233 processor.
+
+core.h:
+ Definitions for the core itself.
+
+The following files are part of the overlay but not used by U-Boot.
+
+tie.h:
+ Co-processors and custom extensions defined in the Tensilica Instruction
+ Extension (TIE) language.
+tie-asm.h:
+ Assembly macros to access custom-defined registers and states.
+
+
+Global Data Pointer, Exported Function Stubs, and the ABI
+---------------------------------------------------------
+
+To support standalone applications launched with the "go" command,
+U-Boot provides a jump table of entrypoints to exported functions
+(grep for EXPORT_FUNC). The implementation for Xtensa depends on
+which ABI (or function calling convention) is used.
+
+Windowed ABI presents unique difficulties with the approach based on
+keeping global data pointer in dedicated register. Because the register
+window rotates during a call, there is no register that is constantly
+available for the gd pointer. Therefore, on xtensa gd is a simple
+global variable. Another difficulty arises from the requirement to have
+an 'entry' at the beginning of a function, which rotates the register
+file and reserves a stack frame. This is an integral part of the
+windowed ABI implemented in hardware. It makes using a jump table to an
+arbitrary (separately compiled) function a bit tricky. Use of a simple
+wrapper is also very tedious due to the need to move all possible
+register arguments and adjust the stack to handle arguments that cannot
+be passed in registers. The most efficient approach is to have the jump
+table perform the 'entry' so as to pretend it's the start of the real
+function. This requires decoding the target function's 'entry'
+instruction to determine the stack frame size, and adjusting the stack
+pointer accordingly, then jumping into the target function just after
+the 'entry'. Decoding depends on the processor's endianness so uses the
+HAL. The implementation (12 instructions) is in examples/stubs.c.
+
+
+Access to Invalid Memory Addresses
+----------------------------------
+
+U-Boot does not check if memory addresses given as arguments to commands
+such as "md" are valid. There are two possible types of invalid
+addresses: an area of physical address space may not be mapped to RAM
+or peripherals, or in the presence of MMU an area of virtual address
+space may not be mapped to physical addresses.
+
+Accessing first type of invalid addresses may result in hardware lockup,
+reading of meaningless data, written data being ignored or an exception,
+depending on the CPU wiring to the system. Accessing second type of
+invalid addresses always ends with an exception.
+
+U-Boot for Xtensa provides a special memory exception handler that
+reports such access attempts and resets the board.
+
+
+.. Chris Zankel
+.. Ross Morley
diff --git a/doc/board/AndesTech/adp-ag101p.rst b/doc/board/AndesTech/adp-ag101p.rst
new file mode 100644
index 0000000..879eba0
--- /dev/null
+++ b/doc/board/AndesTech/adp-ag101p.rst
@@ -0,0 +1,40 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+ADP-AG101P
+==========
+
+ADP-AG101P is the SoC with AG101 hardcore CPU.
+
+AG101P SoC
+----------
+
+AG101P is the mainline SoC produced by Andes Technology using N1213 CPU core
+with FPU and DDR contoller support.
+AG101P has integrated both AHB and APB bus and many periphals for application
+and product development.
+
+
+Configurations
+--------------
+
+CONFIG_MEM_REMAP:
+ Doing memory remap is essential for preparing some non-OS or RTOS
+ applications.
+
+CONFIG_SKIP_LOWLEVEL_INIT:
+ If you want to boot this system from SPI ROM and bypass e-bios (the
+ other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT
+ in "include/configs/adp-ag101p.h".
+
+Build and boot steps
+--------------------
+
+Build:
+
+1. Prepare the toolchains and make sure the $PATH to toolchains is correct.
+2. Use `make adp-ag101p_defconfig` in u-boot root to build the image.
+
+Burn U-Boot to SPI ROM
+----------------------
+
+This section will be added later.
diff --git a/doc/board/AndesTech/ax25-ae350.rst b/doc/board/AndesTech/ax25-ae350.rst
new file mode 100644
index 0000000..7a01893
--- /dev/null
+++ b/doc/board/AndesTech/ax25-ae350.rst
@@ -0,0 +1,329 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+AX25-AE350
+==========
+
+AE350 is the mainline SoC produced by Andes Technology using AX25 CPU core
+base on RISC-V architecture.
+
+AE350 has integrated both AHB and APB bus and many periphals for application
+and product development.
+
+AX25-AE350 is the SoC with AE350 hardcore CPU.
+
+AX25 is Andes CPU IP to adopt RISC-V architecture.
+
+AX25 Features
+-------------
+
+CPU Core
+ - 5-stage in-order execution pipeline
+ - Hardware Multiplier
+ - radix-2/radix-4/radix-16/radix-256/fast
+ - Hardware Divider
+ - Optional branch prediction
+ - Machine mode and optional user mode
+ - Optional performance monitoring
+
+ISA
+ - RV64I base integer instructions
+ - RVC for 16-bit compressed instructions
+ - RVM for multiplication and division instructions
+
+Memory subsystem
+ - I & D local memory
+ - Size: 4KB to 16MB
+ - Memory subsyetem soft-error protection
+ - Protection scheme: parity-checking or error-checking-and-correction (ECC)
+ - Automatic hardware error correction
+
+Bus
+ - Interface Protocol
+ - Synchronous AHB (32-bit/64-bit data-width), or
+ - Synchronous AXI4 (64-bit data-width)
+
+Power management
+ - Wait for interrupt (WFI) mode
+
+Debug
+ - Configurable number of breakpoints: 2/4/8
+ - External Debug Module
+ - AHB slave port
+ - External JTAG debug transport module
+
+Platform Level Interrupt Controller (PLIC)
+ - AHB slave port
+ - Configurable number of interrupts: 1-1023
+ - Configurable number of interrupt priorities: 3/7/15/63/127/255
+ - Configurable number of targets: 1-16
+ - Preempted interrupt priority stack
+
+Configurations
+--------------
+
+CONFIG_SKIP_LOWLEVEL_INIT:
+ If you want to boot this system from SPI ROM and bypass e-bios (the
+ other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT
+ in "include/configs/ax25-ae350.h".
+
+Build and boot steps
+--------------------
+
+Build:
+
+1. Prepare the toolchains and make sure the $PATH to toolchains is correct.
+2. Use `make ae350_rv[32|64]_defconfig` in u-boot root to build the image for
+ 32 or 64 bit.
+
+Verification:
+
+1. startup
+2. relocation
+3. timer driver
+4. uart driver
+5. mac driver
+6. mmc driver
+7. spi driver
+
+Steps
+-----
+
+1. Define CONFIG_SKIP_LOWLEVEL_INIT to build u-boot which is loaded via gdb from ram.
+2. Undefine CONFIG_SKIP_LOWLEVEL_INIT to build u-boot which is booted from spi rom.
+3. Ping a server by mac driver
+4. Scan sd card and copy u-boot image which is booted from flash to ram by sd driver.
+5. Burn this u-boot image to spi rom by spi driver
+6. Re-boot u-boot from spi flash with power off and power on.
+
+Messages of U-Boot boot on AE350 board
+--------------------------------------
+
+.. code-block:: none
+
+ U-Boot 2018.01-rc2-00033-g824f89a (Dec 21 2017 - 16:51:26 +0800)
+
+ DRAM: 1 GiB
+ MMC: mmc@f0e00000: 0
+ SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB
+ In: serial@f0300000
+ Out: serial@f0300000
+ Err: serial@f0300000
+ Net:
+ Warning: mac@e0100000 (eth0) using random MAC address - be:dd:d7:e4:e8:10
+ eth0: mac@e0100000
+
+ RISC-V # version
+ U-Boot 2018.01-rc2-00033-gb265b91-dirty (Dec 22 2017 - 13:54:21 +0800)
+
+ riscv32-unknown-linux-gnu-gcc (GCC) 7.2.0
+ GNU ld (GNU Binutils) 2.29
+
+ RISC-V # setenv ipaddr 10.0.4.200 ;
+ RISC-V # setenv serverip 10.0.4.97 ;
+ RISC-V # ping 10.0.4.97 ;
+ Using mac@e0100000 device
+ host 10.0.4.97 is alive
+
+ RISC-V # mmc rescan
+ RISC-V # fatls mmc 0:1
+ 318907 u-boot-ae350-64.bin
+ 1252 hello_world_ae350_32.bin
+ 328787 u-boot-ae350-32.bin
+
+ 3 file(s), 0 dir(s)
+
+ RISC-V # sf probe 0:0 50000000 0
+ SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB
+
+ RISC-V # sf test 0x100000 0x1000
+ SPI flash test:
+ 0 erase: 36 ticks, 111 KiB/s 0.888 Mbps
+ 1 check: 29 ticks, 137 KiB/s 1.096 Mbps
+ 2 write: 40 ticks, 100 KiB/s 0.800 Mbps
+ 3 read: 20 ticks, 200 KiB/s 1.600 Mbps
+ Test passed
+ 0 erase: 36 ticks, 111 KiB/s 0.888 Mbps
+ 1 check: 29 ticks, 137 KiB/s 1.096 Mbps
+ 2 write: 40 ticks, 100 KiB/s 0.800 Mbps
+ 3 read: 20 ticks, 200 KiB/s 1.600 Mbps
+
+ RISC-V # fatload mmc 0:1 0x600000 u-boot-ae350-32.bin
+ reading u-boot-ae350-32.bin
+ 328787 bytes read in 324 ms (990.2 KiB/s)
+
+ RISC-V # sf erase 0x0 0x51000
+ SF: 331776 bytes @ 0x0 Erased: OK
+
+ RISC-V # sf write 0x600000 0x0 0x50453
+ device 0 offset 0x0, size 0x50453
+ SF: 328787 bytes @ 0x0 Written: OK
+
+ RISC-V # crc32 0x600000 0x50453
+ crc32 for 00600000 ... 00650452 ==> 692dc44a
+
+ RISC-V # crc32 0x80000000 0x50453
+ crc32 for 80000000 ... 80050452 ==> 692dc44a
+ RISC-V #
+
+ *** power-off and power-on, this U-Boot is booted from spi flash ***
+
+ U-Boot 2018.01-rc2-00032-gf67dd47-dirty (Dec 21 2017 - 13:56:03 +0800)
+
+ DRAM: 1 GiB
+ MMC: mmc@f0e00000: 0
+ SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB
+ In: serial@f0300000
+ Out: serial@f0300000
+ Err: serial@f0300000
+ Net:
+ Warning: mac@e0100000 (eth0) using random MAC address - ee:4c:58:29:32:f5
+ eth0: mac@e0100000
+ RISC-V #
+
+
+Boot bbl and riscv-linux via U-Boot on QEMU
+-------------------------------------------
+
+1. Build riscv-linux
+2. Build bbl and riscv-linux with --with-payload
+3. Prepare ae350.dtb
+4. Creating OS-kernel images
+
+.. code-block:: none
+
+ ./mkimage -A riscv -O linux -T kernel -C none -a 0x0000 -e 0x0000 -d bbl.bin bootmImage-bbl.bin
+ Image Name:
+ Created: Tue Mar 13 10:06:42 2018
+ Image Type: RISC-V Linux Kernel Image (uncompressed)
+ Data Size: 17901204 Bytes = 17481.64 KiB = 17.07 MiB
+ Load Address: 00000000
+ Entry Point: 00000000
+
+5. Copy bootmImage-bbl.bin and ae350.dtb to qemu sd card image
+6. Message of booting riscv-linux from bbl via u-boot on qemu
+
+.. code-block:: none
+
+ U-Boot 2018.03-rc4-00031-g2631273 (Mar 13 2018 - 15:02:55 +0800)
+
+ DRAM: 1 GiB
+ main-loop: WARNING: I/O thread spun for 1000 iterations
+ MMC: mmc@f0e00000: 0
+ Loading Environment from SPI Flash... *** Warning - spi_flash_probe_bus_cs() failed, using default environment
+
+ Failed (-22)
+ In: serial@f0300000
+ Out: serial@f0300000
+ Err: serial@f0300000
+ Net:
+ Warning: mac@e0100000 (eth0) using random MAC address - 02:00:00:00:00:00
+ eth0: mac@e0100000
+ RISC-V # mmc rescan
+ RISC-V # mmc part
+
+ Partition Map for MMC device 0 -- Partition Type: DOS
+
+ Part Start Sector Num Sectors UUID Type
+ RISC-V # fatls mmc 0:0
+ 17901268 bootmImage-bbl.bin
+ 1954 ae2xx.dtb
+
+ 2 file(s), 0 dir(s)
+
+ RISC-V # fatload mmc 0:0 0x00600000 bootmImage-bbl.bin
+ 17901268 bytes read in 4642 ms (3.7 MiB/s)
+ RISC-V # fatload mmc 0:0 0x2000000 ae350.dtb
+ 1954 bytes read in 1 ms (1.9 MiB/s)
+ RISC-V # setenv bootm_size 0x2000000
+ RISC-V # setenv fdt_high 0x1f00000
+ RISC-V # bootm 0x00600000 - 0x2000000
+ ## Booting kernel from Legacy Image at 00600000 ...
+ Image Name:
+ Image Type: RISC-V Linux Kernel Image (uncompressed)
+ Data Size: 17901204 Bytes = 17.1 MiB
+ Load Address: 00000000
+ Entry Point: 00000000
+ Verifying Checksum ... OK
+ ## Flattened Device Tree blob at 02000000
+ Booting using the fdt blob at 0x2000000
+ Loading Kernel Image ... OK
+ Loading Device Tree to 0000000001efc000, end 0000000001eff7a1 ... OK
+ [ 0.000000] OF: fdt: Ignoring memory range 0x0 - 0x200000
+ [ 0.000000] Linux version 4.14.0-00046-gf3e439f-dirty (rick@atcsqa06) (gcc version 7.1.1 20170509 (GCC)) #1 Tue Jan 9 16:34:25 CST 2018
+ [ 0.000000] bootconsole [early0] enabled
+ [ 0.000000] Initial ramdisk at: 0xffffffe000016a98 (12267008 bytes)
+ [ 0.000000] Zone ranges:
+ [ 0.000000] DMA [mem 0x0000000000200000-0x000000007fffffff]
+ [ 0.000000] Normal empty
+ [ 0.000000] Movable zone start for each node
+ [ 0.000000] Early memory node ranges
+ [ 0.000000] node 0: [mem 0x0000000000200000-0x000000007fffffff]
+ [ 0.000000] Initmem setup node 0 [mem 0x0000000000200000-0x000000007fffffff]
+ [ 0.000000] elf_hwcap is 0x112d
+ [ 0.000000] random: fast init done
+ [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 516615
+ [ 0.000000] Kernel command line: console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7
+ [ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
+ [ 0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)
+ [ 0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)
+ [ 0.000000] Sorting __ex_table...
+ [ 0.000000] Memory: 2047832K/2095104K available (1856K kernel code, 204K rwdata, 532K rodata, 12076K init, 756K bss, 47272K reserved, 0K cma-reserved)
+ [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
+ [ 0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0
+ [ 0.000000] riscv,cpu_intc,0: 64 local interrupts mapped
+ [ 0.000000] riscv,plic0,e4000000: mapped 31 interrupts to 1/2 handlers
+ [ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x24e6a1710, max_idle_ns: 440795202120 ns
+ [ 0.000000] Calibrating delay loop (skipped), value calculated using timer frequency.. 20.00 BogoMIPS (lpj=40000)
+ [ 0.000000] pid_max: default: 32768 minimum: 301
+ [ 0.004000] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes)
+ [ 0.004000] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes)
+ [ 0.056000] devtmpfs: initialized
+ [ 0.060000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
+ [ 0.064000] futex hash table entries: 256 (order: 0, 6144 bytes)
+ [ 0.068000] NET: Registered protocol family 16
+ [ 0.080000] vgaarb: loaded
+ [ 0.084000] clocksource: Switched to clocksource riscv_clocksource
+ [ 0.088000] NET: Registered protocol family 2
+ [ 0.092000] TCP established hash table entries: 16384 (order: 5, 131072 bytes)
+ [ 0.096000] TCP bind hash table entries: 16384 (order: 5, 131072 bytes)
+ [ 0.096000] TCP: Hash tables configured (established 16384 bind 16384)
+ [ 0.100000] UDP hash table entries: 1024 (order: 3, 32768 bytes)
+ [ 0.100000] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes)
+ [ 0.104000] NET: Registered protocol family 1
+ [ 0.616000] Unpacking initramfs...
+ [ 1.220000] workingset: timestamp_bits=62 max_order=19 bucket_order=0
+ [ 1.244000] io scheduler noop registered
+ [ 1.244000] io scheduler cfq registered (default)
+ [ 1.244000] io scheduler mq-deadline registered
+ [ 1.248000] io scheduler kyber registered
+ [ 1.360000] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+ [ 1.368000] console [ttyS0] disabled
+ [ 1.372000] f0300000.serial: ttyS0 at MMIO 0xf0300020 (irq = 10, base_baud = 1228800) is a 16550A
+ [ 1.392000] console [ttyS0] enabled
+ [ 1.392000] ftmac100: Loading version 0.2 ...
+ [ 1.396000] ftmac100 e0100000.mac eth0: irq 8, mapped at ffffffd002005000
+ [ 1.400000] ftmac100 e0100000.mac eth0: generated random MAC address 6e:ac:c3:92:36:c0
+ [ 1.404000] IR NEC protocol handler initialized
+ [ 1.404000] IR RC5(x/sz) protocol handler initialized
+ [ 1.404000] IR RC6 protocol handler initialized
+ [ 1.404000] IR JVC protocol handler initialized
+ [ 1.408000] IR Sony protocol handler initialized
+ [ 1.408000] IR SANYO protocol handler initialized
+ [ 1.408000] IR Sharp protocol handler initialized
+ [ 1.408000] IR MCE Keyboard/mouse protocol handler initialized
+ [ 1.412000] IR XMP protocol handler initialized
+ [ 1.456000] ftsdc010 f0e00000.mmc: mmc0 - using hw SDIO IRQ
+ [ 1.464000] bootconsole [early0] uses init memory and must be disabled even before the real one is ready
+ [ 1.464000] bootconsole [early0] disabled
+ [ 1.508000] Freeing unused kernel memory: 12076K
+ [ 1.512000] This architecture does not have kernel memory protection.
+ [ 1.520000] mmc0: new SD card at address 4567
+ [ 1.524000] mmcblk0: mmc0:4567 QEMU! 20.0 MiB
+ [ 1.844000] mmcblk0:
+ Wed Dec 1 10:00:00 CST 2010
+ / #
+
+
+TODO
+----
+Boot bbl and riscv-linux via U-Boot on AE350 board
diff --git a/doc/board/AndesTech/index.rst b/doc/board/AndesTech/index.rst
new file mode 100644
index 0000000..d8f7d15
--- /dev/null
+++ b/doc/board/AndesTech/index.rst
@@ -0,0 +1,10 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Andes Tech
+==========
+
+.. toctree::
+ :maxdepth: 2
+
+ adp-ag101p
+ ax25-ae350
diff --git a/doc/board/atmel/at91ek.rst b/doc/board/atmel/at91ek.rst
new file mode 100644
index 0000000..6185b1d
--- /dev/null
+++ b/doc/board/atmel/at91ek.rst
@@ -0,0 +1,192 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+AT91 Evaluation kits
+====================
+
+Board mapping & boot media
+--------------------------
+
+AT91SAM9260EK, AT91SAM9G20EK & AT91SAM9XEEK
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Memory map::
+
+ 0x20000000 - 23FFFFFF SDRAM (64 MB)
+ 0xC0000000 - Cxxxxxxx Atmel Dataflash card (J13)
+ 0xD0000000 - D07FFFFF Soldered Atmel Dataflash (AT45DB642)
+
+Environment variables
+
+U-Boot environment variables can be stored at different places:
+
+ - Dataflash on SPI chip select 1 (default)
+ - Dataflash on SPI chip select 0 (dataflash card)
+ - Nand flash
+
+You can choose your storage location at config step (here for at91sam9260ek)::
+
+ make at91sam9260ek_nandflash_config - use nand flash
+ make at91sam9260ek_dataflash_cs0_config - use data flash (spi cs0)
+ make at91sam9260ek_dataflash_cs1_config - use data flash (spi cs1)
+
+
+AT91SAM9261EK, AT91SAM9G10EK
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Memory map::
+
+ 0x20000000 - 23FFFFFF SDRAM (64 MB)
+ 0xC0000000 - C07FFFFF Soldered Atmel Dataflash (AT45DB642)
+ 0xD0000000 - Dxxxxxxx Atmel Dataflash card (J22)
+
+Environment variables
+
+U-Boot environment variables can be stored at different places:
+
+ - Dataflash on SPI chip select 0 (default)
+ - Dataflash on SPI chip select 3 (dataflash card)
+ - Nand flash
+
+You can choose your storage location at config step (here for at91sam9260ek)::
+
+ make at91sam9261ek_nandflash_config - use nand flash
+ make at91sam9261ek_dataflash_cs0_config - use data flash (spi cs0)
+ make at91sam9261ek_dataflash_cs3_config - use data flash (spi cs3)
+
+
+AT91SAM9263EK
+^^^^^^^^^^^^^
+
+Memory map::
+
+ 0x20000000 - 23FFFFFF SDRAM (64 MB)
+ 0xC0000000 - Cxxxxxxx Atmel Dataflash card (J9)
+
+Environment variables
+
+U-Boot environment variables can be stored at different places:
+
+ - Dataflash on SPI chip select 0 (dataflash card)
+ - Nand flash
+ - Nor flash (not populate by default)
+
+You can choose your storage location at config step (here for at91sam9260ek)::
+
+ make at91sam9263ek_nandflash_config - use nand flash
+ make at91sam9263ek_dataflash_cs0_config - use data flash (spi cs0)
+ make at91sam9263ek_norflash_config - use nor flash
+
+You can choose to boot directly from U-Boot at config step::
+
+ make at91sam9263ek_norflash_boot_config - boot from nor flash
+
+
+AT91SAM9M10G45EK
+^^^^^^^^^^^^^^^^
+
+Memory map::
+
+ 0x70000000 - 77FFFFFF SDRAM (128 MB)
+
+Environment variables
+
+U-Boot environment variables can be stored at different places:
+
+ - Nand flash
+
+You can choose your storage location at config step (here for at91sam9m10g45ek)::
+
+ make at91sam9m10g45ek_nandflash_config - use nand flash
+
+
+AT91SAM9RLEK
+^^^^^^^^^^^^
+
+Memory map::
+
+ 0x20000000 - 23FFFFFF SDRAM (64 MB)
+ 0xC0000000 - C07FFFFF Soldered Atmel Dataflash (AT45DB642)
+
+Environment variables
+
+U-Boot environment variables can be stored at different places:
+
+ - Dataflash on SPI chip select 0
+ - Nand flash.
+
+You can choose your storage location at config step (here for at91sam9rlek)::
+
+ make at91sam9rlek_nandflash_config - use nand flash
+
+
+AT91SAM9N12EK, AT91SAM9X5EK
+^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Memory map::
+
+ 0x20000000 - 27FFFFFF SDRAM (128 MB)
+
+Environment variables
+
+U-Boot environment variables can be stored at different places:
+
+ - Nand flash
+ - SD/MMC card
+ - Serialflash/Dataflash on SPI chip select 0
+
+You can choose your storage location at config step (here for at91sam9x5ek)::
+
+ make at91sam9x5ek_dataflash_config - use data flash
+ make at91sam9x5ek_mmc_config - use sd/mmc card
+ make at91sam9x5ek_nandflash_config - use nand flash
+ make at91sam9x5ek_spiflash_config - use serial flash
+
+
+SAMA5D3XEK
+^^^^^^^^^^
+
+Memory map::
+
+ 0x20000000 - 3FFFFFFF SDRAM (512 MB)
+
+Environment variables
+
+U-Boot environment variables can be stored at different places:
+
+ - Nand flash
+ - SD/MMC card
+ - Serialflash on SPI chip select 0
+
+You can choose your storage location at config step (here for sama5d3xek)::
+
+ make sama5d3xek_mmc_config - use SD/MMC card
+ make sama5d3xek_nandflash_config - use nand flash
+ make sama5d3xek_serialflash_config - use serial flash
+
+
+NAND partition table
+--------------------
+
+All the board support boot from NAND flash will use the following NAND
+partition table::
+
+ 0x00000000 - 0x0003FFFF bootstrap (256 KiB)
+ 0x00040000 - 0x000BFFFF u-boot (512 KiB)
+ 0x000C0000 - 0x000FFFFF env (256 KiB)
+ 0x00100000 - 0x0013FFFF env_redundant (256 KiB)
+ 0x00140000 - 0x0017FFFF spare (256 KiB)
+ 0x00180000 - 0x001FFFFF dtb (512 KiB)
+ 0x00200000 - 0x007FFFFF kernel (6 MiB)
+ 0x00800000 - 0xxxxxxxxx rootfs (All left)
+
+
+Watchdog support
+----------------
+
+For security reasons, the at91 watchdog is running at boot time and,
+if deactivated, cannot be used anymore.
+If you want to use the watchdog, you will need to keep it running in
+your code (make sure not to disable it in AT91Bootstrap for instance).
+
+In the U-Boot configuration, the AT91 watchdog support is enabled using
+the CONFIG_WDT and CONFIG_WDT_AT91 options.
diff --git a/doc/board/atmel/index.rst b/doc/board/atmel/index.rst
new file mode 100644
index 0000000..8ba00fc
--- /dev/null
+++ b/doc/board/atmel/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Atmel
+=====
+
+.. toctree::
+ :maxdepth: 2
+
+ at91ek
diff --git a/doc/board/coreboot/coreboot.rst b/doc/board/coreboot/coreboot.rst
new file mode 100644
index 0000000..fd97422
--- /dev/null
+++ b/doc/board/coreboot/coreboot.rst
@@ -0,0 +1,42 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Bin Meng <bmeng.cn@gmail.com>
+
+Coreboot
+========
+
+Build Instructions for U-Boot as coreboot payload
+-------------------------------------------------
+Building U-Boot as a coreboot payload is just like building U-Boot for targets
+on other architectures, like below::
+
+ $ make coreboot_defconfig
+ $ make all
+
+Test with coreboot
+------------------
+For testing U-Boot as the coreboot payload, there are things that need be paid
+attention to. coreboot supports loading an ELF executable and a 32-bit plain
+binary, as well as other supported payloads. With the default configuration,
+U-Boot is set up to use a separate Device Tree Blob (dtb). As of today, the
+generated u-boot-dtb.bin needs to be packaged by the cbfstool utility (a tool
+provided by coreboot) manually as coreboot's 'make menuconfig' does not provide
+this capability yet. The command is as follows::
+
+ # in the coreboot root directory
+ $ ./build/util/cbfstool/cbfstool build/coreboot.rom add-flat-binary \
+ -f u-boot-dtb.bin -n fallback/payload -c lzma -l 0x1110000 -e 0x1110000
+
+Make sure 0x1110000 matches CONFIG_SYS_TEXT_BASE, which is the symbol address
+of _x86boot_start (in arch/x86/cpu/start.S).
+
+If you want to use ELF as the coreboot payload, change U-Boot configuration to
+use CONFIG_OF_EMBED instead of CONFIG_OF_SEPARATE.
+
+To enable video you must enable these options in coreboot:
+
+ - Set framebuffer graphics resolution (1280x1024 32k-color (1:5:5))
+ - Keep VESA framebuffer
+
+At present it seems that for Minnowboard Max, coreboot does not pass through
+the video information correctly (it always says the resolution is 0x0). This
+works correctly for link though.
diff --git a/doc/board/coreboot/index.rst b/doc/board/coreboot/index.rst
new file mode 100644
index 0000000..d148db9
--- /dev/null
+++ b/doc/board/coreboot/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Coreboot
+========
+
+.. toctree::
+ :maxdepth: 2
+
+ coreboot
diff --git a/doc/board/emulation/index.rst b/doc/board/emulation/index.rst
new file mode 100644
index 0000000..1adefee
--- /dev/null
+++ b/doc/board/emulation/index.rst
@@ -0,0 +1,12 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Emulation
+=========
+
+.. toctree::
+ :maxdepth: 2
+
+ qemu-arm
+ qemu-mips
+ qemu-riscv
+ qemu-x86
diff --git a/doc/board/emulation/qemu-arm.rst b/doc/board/emulation/qemu-arm.rst
new file mode 100644
index 0000000..ca751d4
--- /dev/null
+++ b/doc/board/emulation/qemu-arm.rst
@@ -0,0 +1,82 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (C) 2017, Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
+
+QEMU ARM
+========
+
+QEMU for ARM supports a special 'virt' machine designed for emulation and
+virtualization purposes. This document describes how to run U-Boot under it.
+Both 32-bit ARM and AArch64 are supported.
+
+The 'virt' platform provides the following as the basic functionality:
+
+ - A freely configurable amount of CPU cores
+ - U-Boot loaded and executing in the emulated flash at address 0x0
+ - A generated device tree blob placed at the start of RAM
+ - A freely configurable amount of RAM, described by the DTB
+ - A PL011 serial port, discoverable via the DTB
+ - An ARMv7/ARMv8 architected timer
+ - PSCI for rebooting the system
+ - A generic ECAM-based PCI host controller, discoverable via the DTB
+
+Additionally, a number of optional peripherals can be added to the PCI bus.
+
+Building U-Boot
+---------------
+Set the CROSS_COMPILE environment variable as usual, and run:
+
+- For ARM::
+
+ make qemu_arm_defconfig
+ make
+
+- For AArch64::
+
+ make qemu_arm64_defconfig
+ make
+
+Running U-Boot
+--------------
+The minimal QEMU command line to get U-Boot up and running is:
+
+- For ARM::
+
+ qemu-system-arm -machine virt -bios u-boot.bin
+
+- For AArch64::
+
+ qemu-system-aarch64 -machine virt -cpu cortex-a57 -bios u-boot.bin
+
+Note that for some odd reason qemu-system-aarch64 needs to be explicitly
+told to use a 64-bit CPU or it will boot in 32-bit mode.
+
+Additional persistent U-boot environment support can be added as follows:
+
+- Create envstore.img using qemu-img::
+
+ qemu-img create -f raw envstore.img 64M
+
+- Add a pflash drive parameter to the command line::
+
+ -drive if=pflash,format=raw,index=1,file=envstore.img
+
+Additional peripherals that have been tested to work in both U-Boot and Linux
+can be enabled with the following command line parameters:
+
+- To add a Serial ATA disk via an Intel ICH9 AHCI controller, pass e.g.::
+
+ -drive if=none,file=disk.img,id=mydisk -device ich9-ahci,id=ahci -device ide-drive,drive=mydisk,bus=ahci.0
+
+- To add an Intel E1000 network adapter, pass e.g.::
+
+ -netdev user,id=net0 -device e1000,netdev=net0
+
+- To add an EHCI-compliant USB host controller, pass e.g.::
+
+ -device usb-ehci,id=ehci
+
+- To add a NVMe disk, pass e.g.::
+
+ -drive if=none,file=disk.img,id=mydisk -device nvme,drive=mydisk,serial=foo
+
+These have been tested in QEMU 2.9.0 but should work in at least 2.5.0 as well.
diff --git a/doc/board/emulation/qemu-mips.rst b/doc/board/emulation/qemu-mips.rst
new file mode 100644
index 0000000..529a908
--- /dev/null
+++ b/doc/board/emulation/qemu-mips.rst
@@ -0,0 +1,234 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Vlad Lungu <vlad.lungu@windriver.com>
+
+QEMU MIPS
+=========
+
+Qemu is a full system emulator. See http://www.nongnu.org/qemu/
+
+Limitations & comments
+----------------------
+Supports the "-M mips" configuration of qemu: serial,NE2000,IDE.
+Supports little and big endian as well as 32 bit and 64 bit.
+Derived from au1x00 with a lot of things cut out.
+
+Supports emulated flash (patch Jean-Christophe PLAGNIOL-VILLARD) with
+recent qemu versions. When using emulated flash, launch with
+-pflash <filename> and erase mips_bios.bin.
+
+
+Notes for the Qemu MIPS port
+----------------------------
+
+Example usage
+^^^^^^^^^^^^^
+
+Using u-boot.bin as ROM (replaces Qemu monitor):
+
+32 bit, big endian::
+
+ # make qemu_mips
+ # qemu-system-mips -M mips -bios u-boot.bin -nographic
+
+32 bit, little endian::
+
+ # make qemu_mipsel
+ # qemu-system-mipsel -M mips -bios u-boot.bin -nographic
+
+64 bit, big endian::
+
+ # make qemu_mips64
+ # qemu-system-mips64 -cpu MIPS64R2-generic -M mips -bios u-boot.bin -nographic
+
+64 bit, little endian::
+
+ # make qemu_mips64el
+ # qemu-system-mips64el -cpu MIPS64R2-generic -M mips -bios u-boot.bin -nographic
+
+or using u-boot.bin from emulated flash:
+
+if you use a qemu version after commit 4224
+
+.. code-block:: none
+
+ create image:
+ # dd of=flash bs=1k count=4k if=/dev/zero
+ # dd of=flash bs=1k conv=notrunc if=u-boot.bin
+ start it (see above):
+ # qemu-system-mips[64][el] [-cpu MIPS64R2-generic] -M mips -pflash flash -nographic
+
+Download kernel + initrd
+^^^^^^^^^^^^^^^^^^^^^^^^
+
+On ftp://ftp.denx.de/pub/contrib/Jean-Christophe_Plagniol-Villard/qemu_mips/
+you can downland::
+
+ #config to build the kernel
+ qemu_mips_defconfig
+ #patch to fix mips interrupt init on 2.6.24.y kernel
+ qemu_mips_kernel.patch
+ initrd.gz
+ vmlinux
+ vmlinux.bin
+ System.map
+
+Generate uImage
+^^^^^^^^^^^^^^^
+
+.. code-block:: none
+
+ # tools/mkimage -A mips -O linux -T kernel -C gzip -a 0x80010000 -e 0x80245650 -n "Linux 2.6.24.y" -d vmlinux.bin.gz uImage
+
+Copy uImage to Flash
+^^^^^^^^^^^^^^^^^^^^
+
+.. code-block:: none
+
+ # dd if=uImage bs=1k conv=notrunc seek=224 of=flash
+
+Generate Ide Disk
+^^^^^^^^^^^^^^^^^
+
+.. code-block:: none
+
+ # dd of=ide bs=1k cout=100k if=/dev/zero
+
+ # sfdisk -C 261 -d ide
+ # partition table of ide
+ unit: sectors
+
+ ide1 : start= 63, size= 32067, Id=83
+ ide2 : start= 32130, size= 32130, Id=83
+ ide3 : start= 64260, size= 4128705, Id=83
+ ide4 : start= 0, size= 0, Id= 0
+
+Copy to ide
+^^^^^^^^^^^
+
+.. code-block:: none
+
+ # dd if=uImage bs=512 conv=notrunc seek=63 of=ide
+
+Generate ext2 on part 2 on Copy uImage and initrd.gz
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+.. code-block:: none
+
+ # Attached as loop device ide offset = 32130 * 512
+ # losetup -o 16450560 -f ide
+ # Format as ext2 ( arg2 : nb blocks)
+ # mke2fs /dev/loop0 16065
+ # losetup -d /dev/loop0
+ # Mount and copy uImage and initrd.gz to it
+ # mount -o loop,offset=16450560 -t ext2 ide /mnt
+ # mkdir /mnt/boot
+ # cp {initrd.gz,uImage} /mnt/boot/
+ # Umount it
+ # umount /mnt
+
+Set Environment
+^^^^^^^^^^^^^^^
+
+.. code-block:: none
+
+ setenv rd_start 0x80800000
+ setenv rd_size 2663940
+ setenv kernel BFC38000
+ setenv oad_addr 80500000
+ setenv load_addr2 80F00000
+ setenv kernel_flash BFC38000
+ setenv load_addr_hello 80200000
+ setenv bootargs 'root=/dev/ram0 init=/bin/sh'
+ setenv load_rd_ext2 'ide res; ext2load ide 0:2 ${rd_start} /boot/initrd.gz'
+ setenv load_rd_tftp 'tftp ${rd_start} /initrd.gz'
+ setenv load_kernel_hda 'ide res; diskboot ${load_addr} 0:2'
+ setenv load_kernel_ext2 'ide res; ext2load ide 0:2 ${load_addr} /boot/uImage'
+ setenv load_kernel_tftp 'tftp ${load_addr} /qemu_mips/uImage'
+ setenv boot_ext2_ext2 'run load_rd_ext2; run load_kernel_ext2; run addmisc; bootm ${load_addr}'
+ setenv boot_ext2_flash 'run load_rd_ext2; run addmisc; bootm ${kernel_flash}'
+ setenv boot_ext2_hda 'run load_rd_ext2; run load_kernel_hda; run addmisc; bootm ${load_addr}'
+ setenv boot_ext2_tftp 'run load_rd_ext2; run load_kernel_tftp; run addmisc; bootm ${load_addr}'
+ setenv boot_tftp_hda 'run load_rd_tftp; run load_kernel_hda; run addmisc; bootm ${load_addr}'
+ setenv boot_tftp_ext2 'run load_rd_tftp; run load_kernel_ext2; run addmisc; bootm ${load_addr}'
+ setenv boot_tftp_flash 'run load_rd_tftp; run addmisc; bootm ${kernel_flash}'
+ setenv boot_tftp_tftp 'run load_rd_tftp; run load_kernel_tftp; run addmisc; bootm ${load_addr}'
+ setenv load_hello_tftp 'tftp ${load_addr_hello} /examples/hello_world.bin'
+ setenv go_tftp 'run load_hello_tftp; go ${load_addr_hello}'
+ setenv addmisc 'setenv bootargs ${bootargs} console=ttyS0,${baudrate} rd_start=${rd_start} rd_size=${rd_size} ethaddr=${ethaddr}'
+ setenv bootcmd 'run boot_tftp_flash'
+
+Now you can boot from flash, ide, ide+ext2 and tfp::
+
+ # qemu-system-mips -M mips -pflash flash -monitor null -nographic -net nic -net user -tftp `pwd` -hda ide
+
+
+How to debug U-Boot
+-------------------
+
+In order to debug U-Boot you need to start qemu with gdb server support (-s)
+and waiting the connection to start the CPU (-S)
+
+.. code-block:: none
+
+ # qemu-system-mips -S -s -M mips -pflash flash -monitor null -nographic -net nic -net user -tftp `pwd` -hda ide
+
+in an other console you start gdb
+
+Debugging of U-Boot Before Relocation
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Before relocation, the addresses in the ELF file can be used without any problems
+by connecting to the gdb server localhost:1234
+
+.. code-block:: none
+
+ # mipsel-unknown-linux-gnu-gdb u-boot
+ GNU gdb 6.6
+ Copyright (C) 2006 Free Software Foundation, Inc.
+ GDB is free software, covered by the GNU General Public License, and you are
+ welcome to change it and/or distribute copies of it under certain conditions.
+ Type "show copying" to see the conditions.
+ There is absolutely no warranty for GDB. Type "show warranty" for details.
+ This GDB was configured as "--host=i486-linux-gnu --target=mipsel-unknown-linux-gnu"...
+ (gdb) target remote localhost:1234
+ Remote debugging using localhost:1234
+ _start () at start.S:64
+ 64 RVECENT(reset,0) /* U-Boot entry point */
+ Current language: auto; currently asm
+ (gdb) b board.c:289
+ Breakpoint 1 at 0xbfc00cc8: file board.c, line 289.
+ (gdb) c
+ Continuing.
+
+ Breakpoint 1, board_init_f (bootflag=<value optimized out>) at board.c:290
+ 290 relocate_code (addr_sp, id, addr);
+ Current language: auto; currently c
+ (gdb) p/x addr
+ $1 = 0x87fa0000
+
+Debugging of U-Boot After Relocation
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+For debugging U-Boot after relocation we need to know the address to which
+U-Boot relocates itself to 0x87fa0000 by default.
+And replace the symbol table to this offset.
+
+.. code-block:: none
+
+ (gdb) symbol-file
+ Discard symbol table from `/private/u-boot-arm/u-boot'? (y or n) y
+ Error in re-setting breakpoint 1:
+ No symbol table is loaded. Use the "file" command.
+ No symbol file now.
+ (gdb) add-symbol-file u-boot 0x87fa0000
+ add symbol table from file "u-boot" at
+ .text_addr = 0x87fa0000
+ (y or n) y
+ Reading symbols from /private/u-boot-arm/u-boot...done.
+ Breakpoint 1 at 0x87fa0cc8: file board.c, line 289.
+ (gdb) c
+ Continuing.
+
+ Program received signal SIGINT, Interrupt.
+ 0xffffffff87fa0de4 in udelay (usec=<value optimized out>) at time.c:78
+ 78 while ((tmo - read_c0_count()) < 0x7fffffff)
diff --git a/doc/board/emulation/qemu-riscv.rst b/doc/board/emulation/qemu-riscv.rst
new file mode 100644
index 0000000..fe7505e
--- /dev/null
+++ b/doc/board/emulation/qemu-riscv.rst
@@ -0,0 +1,107 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+
+QEMU RISC-V
+===========
+
+QEMU for RISC-V supports a special 'virt' machine designed for emulation and
+virtualization purposes. This document describes how to run U-Boot under it.
+Both 32-bit and 64-bit targets are supported, running in either machine or
+supervisor mode.
+
+The QEMU virt machine models a generic RISC-V virtual machine with support for
+the VirtIO standard networking and block storage devices. It has CLINT, PLIC,
+16550A UART devices in addition to VirtIO and it also uses device-tree to pass
+configuration information to guest software. It implements RISC-V privileged
+architecture spec v1.10.
+
+Building U-Boot
+---------------
+Set the CROSS_COMPILE environment variable as usual, and run:
+
+- For 32-bit RISC-V::
+
+ make qemu-riscv32_defconfig
+ make
+
+- For 64-bit RISC-V::
+
+ make qemu-riscv64_defconfig
+ make
+
+This will compile U-Boot for machine mode. To build supervisor mode binaries,
+use the configurations qemu-riscv32_smode_defconfig and
+qemu-riscv64_smode_defconfig instead. Note that U-Boot running in supervisor
+mode requires a supervisor binary interface (SBI), such as RISC-V OpenSBI.
+
+Running U-Boot
+--------------
+The minimal QEMU command line to get U-Boot up and running is:
+
+- For 32-bit RISC-V::
+
+ qemu-system-riscv32 -nographic -machine virt -kernel u-boot
+
+- For 64-bit RISC-V::
+
+ qemu-system-riscv64 -nographic -machine virt -kernel u-boot
+
+The commands above create targets with 128MiB memory by default.
+A freely configurable amount of RAM can be created via the '-m'
+parameter. For example, '-m 2G' creates 2GiB memory for the target,
+and the memory node in the embedded DTB created by QEMU reflects
+the new setting.
+
+For instructions on how to run U-Boot in supervisor mode on QEMU
+with OpenSBI, see the documentation available with OpenSBI:
+https://github.com/riscv/opensbi/blob/master/docs/platform/qemu_virt.md
+
+These have been tested in QEMU 3.0.0.
+
+Running U-Boot SPL
+------------------
+In the default SPL configuration, U-Boot SPL starts in machine mode. U-Boot
+proper and OpenSBI (FW_DYNAMIC firmware) are bundled as FIT image and made
+available to U-Boot SPL. Both are then loaded by U-Boot SPL and the location
+of U-Boot proper is passed to OpenSBI. After initialization, U-Boot proper is
+started in supervisor mode by OpenSBI.
+
+OpenSBI must be compiled before compiling U-Boot. Version 0.4 and higher is
+supported by U-Boot. Clone the OpenSBI repository and run the following command.
+
+.. code-block:: console
+
+ git clone https://github.com/riscv/opensbi.git
+ cd opensbi
+ make PLATFORM=qemu/virt
+
+See the OpenSBI documentation for full details:
+https://github.com/riscv/opensbi/blob/master/docs/platform/qemu_virt.md
+
+To make the FW_DYNAMIC binary (build/platform/qemu/virt/firmware/fw_dynamic.bin)
+available to U-Boot, either copy it into the U-Boot root directory or specify
+its location with the OPENSBI environment variable. Afterwards, compile U-Boot
+with the following commands.
+
+- For 32-bit RISC-V::
+
+ make qemu-riscv32_spl_defconfig
+ make
+
+- For 64-bit RISC-V::
+
+ make qemu-riscv64_spl_defconfig
+ make
+
+The minimal QEMU commands to run U-Boot SPL in both 32-bit and 64-bit
+configurations are:
+
+- For 32-bit RISC-V::
+
+ qemu-system-riscv32 -nographic -machine virt -kernel spl/u-boot-spl \
+ -device loader,file=u-boot.itb,addr=0x80200000
+
+- For 64-bit RISC-V::
+
+ qemu-system-riscv64 -nographic -machine virt -kernel spl/u-boot-spl \
+ -device loader,file=u-boot.itb,addr=0x80200000
diff --git a/doc/board/emulation/qemu-x86.rst b/doc/board/emulation/qemu-x86.rst
new file mode 100644
index 0000000..db842f2
--- /dev/null
+++ b/doc/board/emulation/qemu-x86.rst
@@ -0,0 +1,118 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Bin Meng <bmeng.cn@gmail.com>
+
+QEMU x86
+========
+
+Build instructions for bare mode
+--------------------------------
+
+To build u-boot.rom for QEMU x86 targets, just simply run::
+
+ $ make qemu-x86_defconfig (for 32-bit)
+ $ make qemu-x86_64_defconfig (for 64-bit)
+ $ make all
+
+Note this default configuration will build a U-Boot for the QEMU x86 i440FX
+board. To build a U-Boot against QEMU x86 Q35 board, you can change the build
+configuration during the 'make menuconfig' process like below::
+
+ Device Tree Control --->
+ ...
+ (qemu-x86_q35) Default Device Tree for DT control
+
+Test with QEMU for bare mode
+----------------------------
+
+QEMU is a fancy emulator that can enable us to test U-Boot without access to
+a real x86 board. Please make sure your QEMU version is 2.3.0 or above test
+U-Boot. To launch QEMU with u-boot.rom, call QEMU as follows::
+
+ $ qemu-system-i386 -nographic -bios path/to/u-boot.rom
+
+This will instantiate an emulated x86 board with i440FX and PIIX chipset. QEMU
+also supports emulating an x86 board with Q35 and ICH9 based chipset, which is
+also supported by U-Boot. To instantiate such a machine, call QEMU with::
+
+ $ qemu-system-i386 -nographic -bios path/to/u-boot.rom -M q35
+
+Note by default QEMU instantiated boards only have 128 MiB system memory. But
+it is enough to have U-Boot boot and function correctly. You can increase the
+system memory by pass '-m' parameter to QEMU if you want more memory::
+
+ $ qemu-system-i386 -nographic -bios path/to/u-boot.rom -m 1024
+
+This creates a board with 1 GiB system memory. Currently U-Boot for QEMU only
+supports 3 GiB maximum system memory and reserves the last 1 GiB address space
+for PCI device memory-mapped I/O and other stuff, so the maximum value of '-m'
+would be 3072.
+
+QEMU emulates a graphic card which U-Boot supports. Removing '-nographic' will
+show QEMU's VGA console window. Note this will disable QEMU's serial output.
+If you want to check both consoles, use '-serial stdio'.
+
+Multicore is also supported by QEMU via '-smp n' where n is the number of cores
+to instantiate. Note, the maximum supported CPU number in QEMU is 255.
+
+U-Boot uses 'distro_bootcmd' by default when booting on x86 QEMU. This tries to
+load a boot script, kernel, and ramdisk from several different interfaces. For
+the default boot order, see 'qemu-x86.h'. For more information, see
+'README.distro'. Most Linux distros can be booted by writing a uboot script.
+For example, Debian (stretch) can be booted by creating a script file named
+'boot.txt' with the contents::
+
+ setenv bootargs root=/dev/sda1 ro
+ load ${devtype} ${devnum}:${distro_bootpart} ${kernel_addr_r} /vmlinuz
+ load ${devtype} ${devnum}:${distro_bootpart} ${ramdisk_addr_r} /initrd.img
+ zboot ${kernel_addr_r} - ${ramdisk_addr_r} ${filesize}
+
+Then compile and install it with::
+
+ $ apt install u-boot-tools && \
+ mkimage -T script -C none -n "Boot script" -d boot.txt /boot/boot.scr
+
+The fw_cfg interface in QEMU also provides information about kernel data,
+initrd, command-line arguments and more. U-Boot supports directly accessing
+these informtion from fw_cfg interface, which saves the time of loading them
+from hard disk or network again, through emulated devices. To use it , simply
+providing them in QEMU command line::
+
+ $ qemu-system-i386 -nographic -bios path/to/u-boot.rom -m 1024 \
+ -kernel /path/to/bzImage -append 'root=/dev/ram console=ttyS0' \
+ -initrd /path/to/initrd -smp 8
+
+Note: -initrd and -smp are both optional
+
+Then start QEMU, in U-Boot command line use the following U-Boot command to
+setup kernel::
+
+ => qfw
+ qfw - QEMU firmware interface
+
+ Usage:
+ qfw <command>
+ - list : print firmware(s) currently loaded
+ - cpus : print online cpu number
+ - load <kernel addr> <initrd addr> : load kernel and initrd (if any) and setup for zboot
+
+ => qfw load
+ loading kernel to address 01000000 size 5d9d30 initrd 04000000 size 1b1ab50
+
+Here the kernel (bzImage) is loaded to 01000000 and initrd is to 04000000. Then,
+'zboot' can be used to boot the kernel::
+
+ => zboot 01000000 - 04000000 1b1ab50
+
+To run 64-bit U-Boot, qemu-system-x86_64 should be used instead, e.g.::
+
+ $ qemu-system-x86_64 -nographic -bios path/to/u-boot.rom
+
+A specific CPU can be specified via the '-cpu' parameter but please make
+sure the specified CPU supports 64-bit like '-cpu core2duo'. Conversely
+'-cpu pentium' won't work for obvious reasons that the processor only
+supports 32-bit.
+
+Note 64-bit support is very preliminary at this point. Lots of features
+are missing in the 64-bit world. One notable feature is the VGA console
+support which is currently missing, so that you must specify '-nographic'
+to get 64-bit U-Boot up and running.
diff --git a/doc/board/freescale/b4860qds.rst b/doc/board/freescale/b4860qds.rst
new file mode 100644
index 0000000..37d7d08
--- /dev/null
+++ b/doc/board/freescale/b4860qds.rst
@@ -0,0 +1,453 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+B4860QDS
+========
+
+The B4860QDS is a Freescale reference board that hosts the B4860 SoC
+(and variants).
+
+B4860 Overview
+--------------
+The B4860 QorIQ Qonverge device is a Freescale high-end, multicore SoC based on
+StarCore and Power Architecture® cores. It targets the broadband wireless
+infrastructure and builds upon the proven success of the existing multicore
+DSPs and Power CPUs. It is designed to bolster the rapidly changing and
+expanding wireless markets, such as 3GLTE (FDD and TDD), LTE-Advanced, and UMTS.
+
+The B4860 is a highly-integrated StarCore and Power Architecture processor that
+contains:
+
+* Six fully-programmable StarCore SC3900 FVP subsystems, divided into three
+ clusters-each core runs up to 1.2 GHz, with an architecture highly optimized
+ for wireless base station applications
+* Four dual-thread e6500 Power Architecture processors organized in one
+ cluster-each core runs up to 1.8 GHz
+* Two DDR3/3L controllers for high-speed, industry-standard memory interface
+ each runs at up to 1866.67 MHz
+* MAPLE-B3 hardware acceleration-for forward error correction schemes including
+ Turbo or Viterbi decoding, Turbo encoding and rate matching, MIMO MMSE
+ equalization scheme, matrix operations, CRC insertion and check, DFT/iDFT and
+ FFT/iFFT calculations, PUSCH/PDSCH acceleration, and UMTS chip rate
+ acceleration
+* CoreNet fabric that fully supports coherency using MESI protocol between the
+ e6500 cores, SC3900 FVP cores, memories and external interfaces.
+ CoreNet fabric interconnect runs at 667 MHz and supports coherent and
+ non-coherent out of order transactions with prioritization and bandwidth
+ allocation amongst CoreNet endpoints.
+* Data Path Acceleration Architecture, which includes the following:
+
+ * Frame Manager (FMan), which supports in-line packet parsing and general
+ classification to enable policing and QoS-based packet distribution
+ * Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading
+ of queue management, task management, load distribution, flow ordering,
+ buffer management, and allocation tasks from the cores
+ * Security engine (SEC 5.3)-crypto-acceleration for protocols such as
+ IPsec, SSL, and 802.16
+ * RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound
+ and outbound). Supports types 5, 6 (outbound only)
+
+* Large internal cache memory with snooping and stashing capabilities for
+ bandwidth saving and high utilization of processor elements. The 9856-Kbyte
+ internal memory space includes the following:
+
+ * 32 Kbyte L1 ICache per e6500/SC3900 core
+ * 32 Kbyte L1 DCache per e6500/SC3900 core
+ * 2048 Kbyte unified L2 cache for each SC3900 FVP cluster
+ * 2048 Kbyte unified L2 cache for the e6500 cluster
+ * Two 512 Kbyte shared L3 CoreNet platform caches (CPC)
+
+* Sixteen 10-GHz SerDes lanes serving:
+
+ * Two Serial RapidIO interfaces
+ * Each supports up to 4 lanes and a total of up to 8 lanes
+
+* Up to 8-lanes Common Public Radio Interface (CPRI) controller for
+ glue-less antenna connection
+* Two 10-Gbit Ethernet controllers (10GEC)
+* Six 1G/2.5-Gbit Ethernet controllers for network communications
+* PCI Express controller
+* Debug (Aurora)
+* Two OCeaN DMAs
+* Various system peripherals
+* 182 32-bit timers
+
+B4860QDS Overview
+-----------------
+- DDRC1: Ten separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s,
+ ECC, 4 GB of memory in two ranks of 2 GB.
+- DDRC2: Five separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s,
+ ECC, 2 GB of memory. Single rank.
+- SerDes 1 multiplexing: Two Vitesse (transmit and receive path) cross-point
+ 16x16 switch VSC3316
+- SerDes 2 multiplexing: Two Vitesse (transmit and receive path) cross-point
+ 8x8 switch VSC3308
+- USB 2.0 ULPI PHY USB3315 by SMSC supports USB port in host mode.
+ B4860 UART port is available over USB-to-UART translator USB2SER or over
+ RS232 flat cable.
+- A Vitesse dual SGMII phy VSC8662 links the B4860 SGMII lines to 2xRJ-45
+ copper connectors for Stand-alone mode and to the 1000Base-X over AMC
+ MicroTCA connector ports 0 and 2 for AMC mode.
+- The B4860 configuration may be loaded from nine bits coded reset configuration
+ reset source. The RCW source is set by appropriate DIP-switches.
+- 16-bit NOR Flash / PROMJet
+- QIXIS 8-bit NOR Flash Emulator
+- 8-bit NAND Flash
+- 24-bit SPI Flash
+- Long address I2C EEPROM
+- Available debug interfaces are:
+
+ - On-board eCWTAP controller with ETH and USB I/F
+ - JTAG/COP 16-pin header for any external TAP controller
+ - External JTAG source over AMC to support B2B configuration
+ - 70-pin Aurora debug connector
+
+- QIXIS (FPGA) logic:
+ - 2 KB internal memory space including
+
+- IDT840NT4 clock synthesizer provides B4860 essential clocks : SYSCLK,
+ DDRCLK1,2 and RTCCLK.
+- Two 8T49N222A SerDes ref clock devices support two SerDes port clock
+ frequency - total four refclk, including CPRI clock scheme.
+
+
+B4420 Personality
+-----------------
+
+B4420 is a reduced personality of B4860 with less core/clusters(both SC3900
+and e6500), less DDR controllers, less serdes lanes, less SGMII interfaces
+and reduced target frequencies.
+
+Key differences between B4860 and B4420
+---------------------------------------
+
+B4420 has:
+
+1. Less e6500 cores: 1 cluster with 2 e6500 cores
+2. Less SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster
+3. Single DDRC
+4. 2X 4 lane serdes
+5. 3 SGMII interfaces
+6. no sRIO
+7. no 10G
+
+B4860QDS Default Settings
+-------------------------
+
+Switch Settings
+---------------
+
+.. code-block:: none
+
+ SW1 OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0]
+ SW2 ON ON ON ON ON ON OFF OFF
+ SW3 OFF OFF OFF ON OFF OFF ON OFF
+ SW5 OFF OFF OFF OFF OFF OFF ON ON
+
+Note:
+
+- PCIe slots modes: All the PCIe devices work as Root Complex.
+- Boot location: NOR flash.
+
+SysClk/Core(e6500)/CCB/DDR/FMan/DDRCLK/StarCore/CPRI-Maple/eTVPE-Maple/ULB-Maple
+66MHz/1.6GHz/667MHz/1.6GHz data rate/667MHz/133MHz/1200MHz/500MHz/800MHz/667MHz
+
+NAND boot::
+
+ SW1 [1.1] = 0
+ SW2 [1.1] = 1
+ SW3 [1:4] = 0001
+
+NOR boot::
+
+ SW1 [1.1] = 1
+ SW2 [1.1] = 0
+ SW3 [1:4] = 1000
+
+B4420QDS Default Settings
+-------------------------
+
+Switch Settings
+---------------
+
+.. code-block:: none
+
+ SW1 OFF[0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0]
+ SW2 ON OFF ON OFF ON ON OFF OFF
+ SW3 OFF OFF OFF ON OFF OFF ON OFF
+ SW5 OFF OFF OFF OFF OFF OFF ON ON
+
+Note:
+
+- PCIe slots modes: All the PCIe devices work as Root Complex.
+- Boot location: NOR flash.
+
+SysClk/Core(e6500)/CCB/DDR/FMan/DDRCLK/StarCore/CPRI-Maple/eTVPE-Maple/ULB-Maple
+66MHz/1.6GHz/667MHz/1.6GHz data rate/667MHz/133MHz/1200MHz/500MHz/800MHz/667MHz
+
+NAND boot::
+
+ SW1 [1.1] = 0
+ SW2 [1.1] = 1
+ SW3 [1:4] = 0001
+
+NOR boot::
+
+ SW1 [1.1] = 1
+ SW2 [1.1] = 0
+ SW3 [1:4] = 1000
+
+Memory map on B4860QDS
+----------------------
+The addresses in brackets are physical addresses.
+
+============= ============= =============== =======
+Start Address End Address Description Size
+============= ============= =============== =======
+0xF_FFDF_1000 0xF_FFFF_FFFF Free 2 MB
+0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4 KB
+0xF_FF81_0000 0xF_FFDE_FFFF Free 5 MB
+0xF_FF80_0000 0xF_FF80_FFFF IFC NAND Flash 64 KB
+0xF_FF00_0000 0xF_FF7F_FFFF Free 8 MB
+0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16 MB
+0xF_F801_0000 0xF_FDFF_FFFF Free 95 MB
+0xF_F800_0000 0xF_F800_FFFF PCIe I/O Space 64 KB
+0xF_F600_0000 0xF_F7FF_FFFF QMAN s/w portal 32 MB
+0xF_F400_0000 0xF_F5FF_FFFF BMAN s/w portal 32 MB
+0xF_F000_0000 0xF_F3FF_FFFF Free 64 MB
+0xF_E800_0000 0xF_EFFF_FFFF IFC NOR Flash 128 MB
+0xF_E000_0000 0xF_E7FF_FFFF Promjet 128 MB
+0xF_A0C0_0000 0xF_DFFF_FFFF Free 1012 MB
+0xF_A000_0000 0xF_A0BF_FFFF MAPLE0/1/2 12 MB
+0xF_0040_0000 0xF_9FFF_FFFF Free 12 GB
+0xF_0000_0000 0xF_01FF_FFFF DCSR 32 MB
+0xC_4000_0000 0xE_FFFF_FFFF Free 11 GB
+0xC_3000_0000 0xC_3FFF_FFFF sRIO-2 I/O 256 MB
+0xC_2000_0000 0xC_2FFF_FFFF sRIO-1 I/O 256 MB
+0xC_0000_0000 0xC_1FFF_FFFF PCIe Mem Space 512 MB
+0x1_0000_0000 0xB_FFFF_FFFF Free 44 GB
+0x0_8000_0000 0x0_FFFF_FFFF DDRC1 2 GB
+0x0_0000_0000 0x0_7FFF_FFFF DDRC2 2 GB
+============= ============= =============== =======
+
+Memory map on B4420QDS
+----------------------
+The addresses in brackets are physical addresses.
+
+============= ============= =============== =======
+Start Address End Address Description Size
+============= ============= =============== =======
+0xF_FFDF_1000 0xF_FFFF_FFFF Free 2 MB
+0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4 KB
+0xF_FF81_0000 0xF_FFDE_FFFF Free 5 MB
+0xF_FF80_0000 0xF_FF80_FFFF IFC NAND Flash 64 KB
+0xF_FF00_0000 0xF_FF7F_FFFF Free 8 MB
+0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16 MB
+0xF_F801_0000 0xF_FDFF_FFFF Free 95 MB
+0xF_F800_0000 0xF_F800_FFFF PCIe I/O Space 64 KB
+0xF_F600_0000 0xF_F7FF_FFFF QMAN s/w portal 32 MB
+0xF_F400_0000 0xF_F5FF_FFFF BMAN s/w portal 32 MB
+0xF_F000_0000 0xF_F3FF_FFFF Free 64 MB
+0xF_E800_0000 0xF_EFFF_FFFF IFC NOR Flash 128 MB
+0xF_E000_0000 0xF_E7FF_FFFF Promjet 128 MB
+0xF_A0C0_0000 0xF_DFFF_FFFF Free 1012 MB
+0xF_A000_0000 0xF_A0BF_FFFF MAPLE0/1/2 12 MB
+0xF_0040_0000 0xF_9FFF_FFFF Free 12 GB
+0xF_0000_0000 0xF_01FF_FFFF DCSR 32 MB
+0xC_4000_0000 0xE_FFFF_FFFF Free 11 GB
+0xC_3000_0000 0xC_3FFF_FFFF sRIO-2 I/O 256 MB
+0xC_2000_0000 0xC_2FFF_FFFF sRIO-1 I/O 256 MB
+0xC_0000_0000 0xC_1FFF_FFFF PCIe Mem Space 512 MB
+0x1_0000_0000 0xB_FFFF_FFFF Free 44 GB
+0x0_0000_0000 0x0_FFFF_FFFF DDRC1 4 GB
+============= ============= =============== =======
+
+NOR Flash memory Map on B4860 and B4420QDS
+------------------------------------------
+
+============= ============= ============================== =========
+ Start End Definition Size
+============= ============= ============================== =========
+0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB
+0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB
+0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
+0xEF300000 0xEFEFFFFF rootfs (alternate bank) 12MB
+0xEE800000 0xEE8FFFFF device tree (alternate bank) 1MB
+0xEE020000 0xEE6FFFFF Linux.uImage (alternate bank) 6MB+896KB
+0xEE000000 0xEE01FFFF RCW (alternate bank) 128KB
+0xEDF40000 0xEDFFFFFF U-Boot (alternate bank) 768KB
+0xEDF20000 0xEDF3FFFF U-Boot env (alternate bank) 128KB
+0xEDF00000 0xEDF1FFFF FMAN ucode (alternate bank) 128KB
+0xED300000 0xEDEFFFFF rootfs (current bank) 12MB
+0xEC800000 0xEC8FFFFF device tree (current bank) 1MB
+0xEC020000 0xEC6FFFFF Linux.uImage (current bank) 6MB+896KB
+0xEC000000 0xEC01FFFF RCW (current bank) 128KB
+============= ============= ============================== =========
+
+Various Software configurations/environment variables/commands
+--------------------------------------------------------------
+The below commands apply to both B4860QDS and B4420QDS.
+
+U-Boot environment variable hwconfig
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The default hwconfig is:
+
+.. code-block:: none
+
+ hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1:dr_mode=host,phy_type=ulpi
+
+Note: For USB gadget set "dr_mode=peripheral"
+
+FMAN Ucode versions
+^^^^^^^^^^^^^^^^^^^
+
+fsl_fman_ucode_B4860_106_3_6.bin
+
+Switching to alternate bank
+^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Commands for switching to alternate bank.
+
+1. To change from vbank0 to vbank2
+
+.. code-block:: none
+
+ => qixis_reset altbank (it will boot using vbank2)
+
+2. To change from vbank2 to vbank0
+
+.. code-block:: none
+
+ => qixis reset (it will boot using vbank0)
+
+To change personality of board
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+For changing personality from B4860 to B4420
+
+1. Boot from vbank0
+2. Flash vbank2 with b4420 rcw and U-Boot
+3. Give following commands to uboot prompt
+
+.. code-block:: none
+
+ => mw.b ffdf0040 0x30;
+ => mw.b ffdf0010 0x00;
+ => mw.b ffdf0062 0x02;
+ => mw.b ffdf0050 0x02;
+ => mw.b ffdf0010 0x30;
+ => reset
+
+Note:
+
+- Power off cycle will lead to default switch settings.
+- 0xffdf0000 is the address of the QIXIS FPGA.
+
+Switching between NOR and NAND boot(RCW src changed from NOR <-> NAND)
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+To change from NOR to NAND boot give following command on uboot prompt
+
+.. code-block:: none
+
+ => mw.b ffdf0040 0x30
+ => mw.b ffdf0010 0x00
+ => mw.b 0xffdf0050 0x08
+ => mw.b 0xffdf0060 0x82
+ => mw.b ffdf0061 0x00
+ => mw.b ffdf0010 0x30
+ => reset
+
+To change from NAND to NOR boot give following command on uboot prompt:
+
+.. code-block:: none
+
+ => mw.b ffdf0040 0x30
+ => mw.b ffdf0010 0x00
+ => mw.b 0xffdf0050 0x00(for vbank0) or (mw.b 0xffdf0050 0x02 for vbank2)
+ => mw.b 0xffdf0060 0x12
+ => mw.b ffdf0061 0x01
+ => mw.b ffdf0010 0x30
+ => reset
+
+Note:
+
+- Power off cycle will lead to default switch settings.
+- 0xffdf0000 is the address of the QIXIS FPGA.
+
+Ethernet interfaces for B4860QDS
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Serdes protocosl tested:
+* 0x2a, 0x8d (serdes1, serdes2) [DEFAULT]
+* 0x2a, 0xb2 (serdes1, serdes2)
+
+When using [DEFAULT] RCW, which including 2 * 1G SGMII on board and 2 * 1G
+SGMII on SGMII riser card.
+
+Under U-Boot these network interfaces are recognized as::
+
+ FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5 and FM1@DTSEC6.
+
+On Linux the interfaces are renamed as::
+
+ eth2 -> fm1-gb2
+ eth3 -> fm1-gb3
+ eth4 -> fm1-gb4
+ eth5 -> fm1-gb5
+
+RCW and Ethernet interfaces for B4420QDS
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Serdes protocosl tested:
+* 0x18, 0x9e (serdes1, serdes2)
+
+Under U-Boot these network interfaces are recognized as::
+
+ FM1@DTSEC3, FM1@DTSEC4 and e1000#0.
+
+On Linux the interfaces are renamed as::
+
+ eth2 -> fm1-gb2
+ eth3 -> fm1-gb3
+
+NAND boot with 2 Stage boot loader
+----------------------------------
+PBL initialise the internal SRAM and copy SPL(160KB) in SRAM.
+SPL further initialise DDR using SPD and environment variables and copy
+U-Boot(768 KB) from flash to DDR.
+Finally SPL transer control to U-Boot for futher booting.
+
+SPL has following features:
+ - Executes within 256K
+ - No relocation required
+
+Run time view of SPL framework during boot:
+
++----------------------------------------------+
+|Area | Address |
++----------------------------------------------+
+|Secure boot | 0xFFFC0000 (32KB) |
+|headers | |
++----------------------------------------------+
+|GD, BD | 0xFFFC8000 (4KB) |
++----------------------------------------------+
+|ENV | 0xFFFC9000 (8KB) |
++----------------------------------------------+
+|HEAP | 0xFFFCB000 (30KB) |
++----------------------------------------------+
+|STACK | 0xFFFD8000 (22KB) |
++----------------------------------------------+
+|U-Boot SPL | 0xFFFD8000 (160KB) |
++----------------------------------------------+
+
+NAND Flash memory Map on B4860 and B4420QDS
+-------------------------------------------
+
+============= ============= ============================= =====
+Start End Definition Size
+============= ============= ============================= =====
+0x000000 0x0FFFFF U-Boot 1MB
+0x140000 0x15FFFF U-Boot env 128KB
+0x1A0000 0x1BFFFF FMAN Ucode 128KB
+============= ============= ============================= =====
diff --git a/doc/board/freescale/index.rst b/doc/board/freescale/index.rst
new file mode 100644
index 0000000..8d42b35
--- /dev/null
+++ b/doc/board/freescale/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Freescale
+=========
+
+.. toctree::
+ :maxdepth: 2
+
+ b4860qds
diff --git a/doc/board/google/chromebook_link.rst b/doc/board/google/chromebook_link.rst
new file mode 100644
index 0000000..1608030
--- /dev/null
+++ b/doc/board/google/chromebook_link.rst
@@ -0,0 +1,34 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Simon Glass <sjg@chromium.org>
+
+Chromebook Link
+===============
+
+First, you need the following binary blobs:
+
+ * descriptor.bin - Intel flash descriptor
+ * me.bin - Intel Management Engine
+ * mrc.bin - Memory Reference Code, which sets up SDRAM
+ * video ROM - sets up the display
+
+You can get these binary blobs by::
+
+ $ git clone http://review.coreboot.org/p/blobs.git
+ $ cd blobs
+
+Find the following files:
+
+ * ./mainboard/google/link/descriptor.bin
+ * ./mainboard/google/link/me.bin
+ * ./northbridge/intel/sandybridge/systemagent-r6.bin
+
+The 3rd one should be renamed to mrc.bin.
+As for the video ROM, you can get it `here`_ and rename it to vga.bin.
+Make sure all these binary blobs are put in the board directory.
+
+Now you can build U-Boot and obtain u-boot.rom::
+
+ $ make chromebook_link_defconfig
+ $ make all
+
+.. _here: http://www.coreboot.org/~stepan/pci8086,0166.rom
diff --git a/doc/board/google/chromebook_samus.rst b/doc/board/google/chromebook_samus.rst
new file mode 100644
index 0000000..eab1128
--- /dev/null
+++ b/doc/board/google/chromebook_samus.rst
@@ -0,0 +1,101 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Simon Glass <sjg@chromium.org>
+
+Chromebook Samus
+================
+
+First, you need the following binary blobs:
+
+ * descriptor.bin - Intel flash descriptor
+ * me.bin - Intel Management Engine
+ * mrc.bin - Memory Reference Code, which sets up SDRAM
+ * refcode.elf - Additional Reference code
+ * vga.bin - video ROM, which sets up the display
+
+If you have a samus you can obtain them from your flash, for example, in
+developer mode on the Chromebook (use Ctrl-Alt-F2 to obtain a terminal and
+log in as 'root')::
+
+ cd /tmp
+ flashrom -w samus.bin
+ scp samus.bin username@ip_address:/path/to/somewhere
+
+If not see the coreboot tree where you can use::
+
+ bash crosfirmware.sh samus
+
+to get the image. There is also an 'extract_blobs.sh' scripts that you can use
+on the 'coreboot-Google_Samus.*' file to short-circuit some of the below.
+
+Then 'ifdtool -x samus.bin' on your development machine will produce::
+
+ flashregion_0_flashdescriptor.bin
+ flashregion_1_bios.bin
+ flashregion_2_intel_me.bin
+
+Rename flashregion_0_flashdescriptor.bin to descriptor.bin
+Rename flashregion_2_intel_me.bin to me.bin
+You can ignore flashregion_1_bios.bin - it is not used.
+
+To get the rest, use 'cbfstool samus.bin print'::
+
+ samus.bin: 8192 kB, bootblocksize 2864, romsize 8388608, offset 0x700000
+ alignment: 64 bytes, architecture: x86
+
+============================ ======== =========== ======
+Name Offset Type Size
+============================ ======== =========== ======
+cmos_layout.bin 0x700000 cmos_layout 1164
+pci8086,0406.rom 0x7004c0 optionrom 65536
+spd.bin 0x710500 (unknown) 4096
+cpu_microcode_blob.bin 0x711540 microcode 70720
+fallback/romstage 0x722a00 stage 54210
+fallback/ramstage 0x72fe00 stage 96382
+config 0x7476c0 raw 6075
+fallback/vboot 0x748ec0 stage 15980
+fallback/refcode 0x74cd80 stage 75578
+fallback/payload 0x75f500 payload 62878
+u-boot.dtb 0x76eb00 (unknown) 5318
+(empty) 0x770000 null 196504
+mrc.bin 0x79ffc0 (unknown) 222876
+(empty) 0x7d66c0 null 167320
+============================ ======== =========== ======
+
+You can extract what you need::
+
+ cbfstool samus.bin extract -n pci8086,0406.rom -f vga.bin
+ cbfstool samus.bin extract -n fallback/refcode -f refcode.rmod
+ cbfstool samus.bin extract -n mrc.bin -f mrc.bin
+ cbfstool samus.bin extract -n fallback/refcode -f refcode.bin -U
+
+Note that the -U flag is only supported by the latest cbfstool. It unpacks
+and decompresses the stage to produce a coreboot rmodule. This is a simple
+representation of an ELF file. You need the patch "Support decoding a stage
+with compression".
+
+Put all 5 files into board/google/chromebook_samus.
+
+Now you can build U-Boot and obtain u-boot.rom::
+
+ $ make chromebook_samus_defconfig
+ $ make all
+
+If you are using em100, then this command will flash write -Boot::
+
+ em100 -s -d filename.rom -c W25Q64CV -r
+
+Flash map for samus / broadwell:
+
+ :fffff800: SYS_X86_START16
+ :ffff0000: RESET_SEG_START
+ :fffd8000: TPL_TEXT_BASE
+ :fffa0000: X86_MRC_ADDR
+ :fff90000: VGA_BIOS_ADDR
+ :ffed0000: SYS_TEXT_BASE
+ :ffea0000: X86_REFCODE_ADDR
+ :ffe70000: SPL_TEXT_BASE
+ :ffbf8000: CONFIG_ENV_OFFSET (environemnt offset)
+ :ffbe0000: rw-mrc-cache (Memory-reference-code cache)
+ :ffa00000: <spare>
+ :ff801000: intel-me (address set by descriptor.bin)
+ :ff800000: intel-descriptor
diff --git a/doc/board/google/index.rst b/doc/board/google/index.rst
new file mode 100644
index 0000000..7f557fe
--- /dev/null
+++ b/doc/board/google/index.rst
@@ -0,0 +1,10 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Google
+======
+
+.. toctree::
+ :maxdepth: 2
+
+ chromebook_link
+ chromebook_samus
diff --git a/doc/board/index.rst b/doc/board/index.rst
new file mode 100644
index 0000000..00e72f5
--- /dev/null
+++ b/doc/board/index.rst
@@ -0,0 +1,18 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Board-specific doc
+==================
+
+.. toctree::
+ :maxdepth: 2
+
+ AndesTech/index
+ atmel/index
+ coreboot/index
+ emulation/index
+ freescale/index
+ google/index
+ intel/index
+ renesas/index
+ sifive/index
+ xilinx/index
diff --git a/doc/board/intel/bayleybay.rst b/doc/board/intel/bayleybay.rst
new file mode 100644
index 0000000..db97f64
--- /dev/null
+++ b/doc/board/intel/bayleybay.rst
@@ -0,0 +1,29 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Bin Meng <bmeng.cn@gmail.com>
+
+Bayley Bay CRB
+==============
+
+This uses as FSP as with Crown Bay, except it is for the Atom E3800 series.
+Download this and get the .fd file (BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd at
+the time of writing). Put it in the corresponding board directory and rename
+it to fsp.bin.
+
+Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same
+board directory as vga.bin.
+
+You still need two more binary blobs. For Bayley Bay, they can be extracted
+from the sample SPI image provided in the FSP (SPI.bin at the time of writing)::
+
+ $ ./tools/ifdtool -x BayleyBay/SPI.bin
+ $ cp flashregion_0_flashdescriptor.bin board/intel/bayleybay/descriptor.bin
+ $ cp flashregion_2_intel_me.bin board/intel/bayleybay/me.bin
+
+Now you can build U-Boot and obtain u-boot.rom::
+
+ $ make bayleybay_defconfig
+ $ make all
+
+Note that the debug version of the FSP is bigger in size. If this version
+is used, CONFIG_FSP_ADDR needs to be configured to 0xfffb0000 instead of
+the default value 0xfffc0000.
diff --git a/doc/board/intel/cherryhill.rst b/doc/board/intel/cherryhill.rst
new file mode 100644
index 0000000..151f061
--- /dev/null
+++ b/doc/board/intel/cherryhill.rst
@@ -0,0 +1,30 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Bin Meng <bmeng.cn@gmail.com>
+
+Cherry Hill CRB
+===============
+
+This uses Intel FSP for Braswell platform. Download it from Intel FSP website,
+put the .fd file to the board directory and rename it to fsp.bin.
+
+Extract descriptor.bin and me.bin from the original BIOS on the board using
+ifdtool and put them to the board directory as well.
+
+Note the FSP package for Braswell does not ship a traditional legacy VGA BIOS
+image for the integrated graphics device. Instead a new binary called Video
+BIOS Table (VBT) is shipped. Put it to the board directory and rename it to
+vbt.bin if you want graphics support in U-Boot.
+
+Now you can build U-Boot and obtain u-boot.rom::
+
+ $ make cherryhill_defconfig
+ $ make all
+
+An important note for programming u-boot.rom to the on-board SPI flash is that
+you need make sure the SPI flash's 'quad enable' bit in its status register
+matches the settings in the descriptor.bin, otherwise the board won't boot.
+
+For the on-board SPI flash MX25U6435F, this can be done by writing 0x40 to the
+status register by DediProg in: Config > Modify Status Register > Write Status
+Register(s) > Register1 Value(Hex). This is is a one-time change. Once set, it
+persists in SPI flash part regardless of the u-boot.rom image burned.
diff --git a/doc/board/intel/cougarcanyon2.rst b/doc/board/intel/cougarcanyon2.rst
new file mode 100644
index 0000000..5e3e7a1
--- /dev/null
+++ b/doc/board/intel/cougarcanyon2.rst
@@ -0,0 +1,24 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Bin Meng <bmeng.cn@gmail.com>
+
+Cougar Canyon 2 CRB
+===================
+
+This uses Intel FSP for 3rd generation Intel Core and Intel Celeron processors
+with mobile Intel HM76 and QM77 chipsets platform. Download it from Intel FSP
+website and put the .fd file (CHIEFRIVER_FSP_GOLD_001_09-OCTOBER-2013.fd at the
+time of writing) in the board directory and rename it to fsp.bin.
+
+Now build U-Boot and obtain u-boot.rom::
+
+ $ make cougarcanyon2_defconfig
+ $ make all
+
+The board has two 8MB SPI flashes mounted, which are called SPI-0 and SPI-1 in
+the board manual. The SPI-0 flash should have flash descriptor plus ME firmware
+and SPI-1 flash is used to store U-Boot. For convenience, the complete 8MB SPI-0
+flash image is included in the FSP package (named Rom00_8M_MB_PPT.bin). Program
+this image to the SPI-0 flash according to the board manual just once and we are
+all set. For programming U-Boot we just need to program SPI-1 flash. Since the
+default u-boot.rom image for this board is set to 2MB, it should be programmed
+to the last 2MB of the 8MB chip, address range [600000, 7FFFFF].
diff --git a/doc/board/intel/crownbay.rst b/doc/board/intel/crownbay.rst
new file mode 100644
index 0000000..4fcf981
--- /dev/null
+++ b/doc/board/intel/crownbay.rst
@@ -0,0 +1,43 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Bin Meng <bmeng.cn@gmail.com>
+
+Crown Bay CRB
+=============
+
+U-Boot support of Intel `Crown Bay`_ board relies on a binary blob called
+Firmware Support Package (`FSP`_) to perform all the necessary initialization
+steps as documented in the BIOS Writer Guide, including initialization of the
+CPU, memory controller, chipset and certain bus interfaces.
+
+Download the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T,
+install it on your host and locate the FSP binary blob. Note this platform
+also requires a Chipset Micro Code (CMC) state machine binary to be present in
+the SPI flash where u-boot.rom resides, and this CMC binary blob can be found
+in this FSP package too.
+
+ * ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd
+ * ./Microcode/C0_22211.BIN
+
+Rename the first one to fsp.bin and second one to cmc.bin and put them in the
+board directory.
+
+Note the FSP release version 001 has a bug which could cause random endless
+loop during the FspInit call. This bug was published by Intel although Intel
+did not describe any details. We need manually apply the patch to the FSP
+binary using any hex editor (eg: bvi). Go to the offset 0x1fcd8 of the FSP
+binary, change the following five bytes values from orginally E8 42 FF FF FF
+to B8 00 80 0B 00.
+
+As for the video ROM, you need manually extract it from the Intel provided
+BIOS for Crown Bay `here`_, using the AMI `MMTool`_. Check PCI option
+ROM ID 8086:4108, extract and save it as vga.bin in the board directory.
+
+Now you can build U-Boot and obtain u-boot.rom::
+
+ $ make crownbay_defconfig
+ $ make all
+
+.. _`Crown Bay`: http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html
+.. _`FSP`: http://www.intel.com/fsp
+.. _`here`: http://www.intel.com/content/www/us/en/secure/intelligent-systems/privileged/e6xx-35-b1-cmc22211.html
+.. _`MMTool`: http://www.ami.com/products/bios-uefi-tools-and-utilities/bios-uefi-utilities/
diff --git a/doc/board/intel/edison.rst b/doc/board/intel/edison.rst
new file mode 100644
index 0000000..1aee2a1
--- /dev/null
+++ b/doc/board/intel/edison.rst
@@ -0,0 +1,41 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+
+Edison
+======
+
+Build Instructions for U-Boot as main bootloader
+------------------------------------------------
+
+Simple you can build U-Boot and obtain u-boot.bin::
+
+ $ make edison_defconfig
+ $ make all
+
+Updating U-Boot on Edison
+-------------------------
+
+By default Intel Edison boards are shipped with preinstalled heavily
+patched U-Boot v2014.04. Though it supports DFU which we may be able to
+use.
+
+1. Prepare u-boot.bin as described in chapter above. You still need one
+ more step (if and only if you have original U-Boot), i.e. run the
+ following command::
+
+ $ truncate -s %4096 u-boot.bin
+
+2. Run your board and interrupt booting to U-Boot console. In the console
+ call::
+
+ => run do_force_flash_os
+
+3. Wait for few seconds, it will prepare environment variable and runs
+ DFU. Run DFU command from the host system::
+
+ $ dfu-util -v -d 8087:0a99 --alt u-boot0 -D u-boot.bin
+
+4. Return to U-Boot console and following hint. i.e. push Ctrl+C, and
+ reset the board::
+
+ => reset
diff --git a/doc/board/intel/galileo.rst b/doc/board/intel/galileo.rst
new file mode 100644
index 0000000..f51a06b
--- /dev/null
+++ b/doc/board/intel/galileo.rst
@@ -0,0 +1,22 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Bin Meng <bmeng.cn@gmail.com>
+
+Galileo
+=======
+
+Only one binary blob is needed for Remote Management Unit (RMU) within Intel
+Quark SoC. Not like FSP, U-Boot does not call into the binary. The binary is
+needed by the Quark SoC itself.
+
+You can get the binary blob from Quark Board Support Package from Intel website:
+
+ * ./QuarkSocPkg/QuarkNorthCluster/Binary/QuarkMicrocode/RMU.bin
+
+Rename the file and put it to the board directory by::
+
+ $ cp RMU.bin board/intel/galileo/rmu.bin
+
+Now you can build U-Boot and obtain u-boot.rom::
+
+ $ make galileo_defconfig
+ $ make all
diff --git a/doc/board/intel/index.rst b/doc/board/intel/index.rst
new file mode 100644
index 0000000..f545dee
--- /dev/null
+++ b/doc/board/intel/index.rst
@@ -0,0 +1,16 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Intel
+=====
+
+.. toctree::
+ :maxdepth: 2
+
+ bayleybay
+ cherryhill
+ cougarcanyon2
+ crownbay
+ edison
+ galileo
+ minnowmax
+ slimbootloader
diff --git a/doc/board/intel/minnowmax.rst b/doc/board/intel/minnowmax.rst
new file mode 100644
index 0000000..0281217
--- /dev/null
+++ b/doc/board/intel/minnowmax.rst
@@ -0,0 +1,70 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Simon Glass <sjg@chromium.org>
+
+Minnowboard MAX
+===============
+
+This uses as FSP as with Crown Bay, except it is for the Atom E3800 series.
+Download this and get the .fd file (BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd at
+the time of writing). Put it in the corresponding board directory and rename
+it to fsp.bin.
+
+Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same
+board directory as vga.bin.
+
+You still need two more binary blobs. For Minnowboard MAX, we can reuse the
+same ME firmware above, but for flash descriptor, we need get that somewhere
+else, as the one above does not seem to work, probably because it is not
+designed for the Minnowboard MAX. Now download the original firmware image
+for this board from:
+
+ * http://firmware.intel.com/sites/default/files/2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip
+
+Unzip it::
+
+ $ unzip 2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip
+
+Use ifdtool in the U-Boot tools directory to extract the images from that
+file, for example::
+
+ $ ./tools/ifdtool -x MNW2MAX1.X64.0073.R02.1409160934.bin
+
+This will provide the descriptor file - copy this into the correct place::
+
+ $ cp flashregion_0_flashdescriptor.bin board/intel/minnowmax/descriptor.bin
+
+Now you can build U-Boot and obtain u-boot.rom::
+
+ $ make minnowmax_defconfig
+ $ make all
+
+Checksums are as follows (but note that newer versions will invalidate this)::
+
+ $ md5sum -b board/intel/minnowmax/*.bin
+ ffda9a3b94df5b74323afb328d51e6b4 board/intel/minnowmax/descriptor.bin
+ 69f65b9a580246291d20d08cbef9d7c5 board/intel/minnowmax/fsp.bin
+ 894a97d371544ec21de9c3e8e1716c4b board/intel/minnowmax/me.bin
+ a2588537da387da592a27219d56e9962 board/intel/minnowmax/vga.bin
+
+The ROM image is broken up into these parts:
+
+====== ================== ============================
+Offset Description Controlling config
+====== ================== ============================
+000000 descriptor.bin Hard-coded to 0 in ifdtool
+001000 me.bin Set by the descriptor
+500000 <spare>
+6ef000 Environment CONFIG_ENV_OFFSET
+6f0000 MRC cache CONFIG_ENABLE_MRC_CACHE
+700000 u-boot-dtb.bin CONFIG_SYS_TEXT_BASE
+7b0000 vga.bin CONFIG_VGA_BIOS_ADDR
+7c0000 fsp.bin CONFIG_FSP_ADDR
+7f8000 <spare> (depends on size of fsp.bin)
+7ff800 U-Boot 16-bit boot CONFIG_SYS_X86_START16
+====== ================== ============================
+
+Overall ROM image size is controlled by CONFIG_ROM_SIZE.
+
+Note that the debug version of the FSP is bigger in size. If this version
+is used, CONFIG_FSP_ADDR needs to be configured to 0xfffb0000 instead of
+the default value 0xfffc0000.
diff --git a/doc/board/intel/slimbootloader.rst b/doc/board/intel/slimbootloader.rst
new file mode 100644
index 0000000..375e676
--- /dev/null
+++ b/doc/board/intel/slimbootloader.rst
@@ -0,0 +1,196 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Aiden Park <aiden.park@intel.com>
+
+Slim Bootloader
+===============
+
+Introduction
+------------
+
+This target is to enable U-Boot_ as a payload of `Slim Bootloader`_ (a.k.a SBL)
+boot firmware which currently supports QEMU, Apollolake, Whiskeylake,
+Coffeelake-R platforms.
+
+The `Slim Bootloader`_ is designed with multi-stages (Stage1A/B, Stage2, Payload)
+architecture to cover from reset vector to OS booting and it consumes
+`Intel FSP`_ for silicon initialization.
+
+* Stage1A: Reset vector, CAR init with FSP-T
+* Stage1B: Memory init with FSP-M, CAR teardown, Continue execution in memory
+* Stage2 : Rest of Silicon init with FSP-S, Create HOB, Hand-off to Payload
+* Payload: Payload init with HOB, Load OS from media, Booting OS
+
+The Slim Bootloader stages (Stage1A/B, Stage2) focus on chipset, hardware and
+platform specific initialization, and it provides useful information to a
+payload in a HOB (Hand-Off Block) which has serial port, memory map, performance
+data info and so on. This is Slim Bootloader architectural design to make a
+payload light-weight, platform independent and more generic across different
+boot solutions or payloads, and to minimize hardware re-initialization in a
+payload.
+
+Build Instruction for U-Boot as a Slim Bootloader payload
+---------------------------------------------------------
+
+Build U-Boot and obtain u-boot-dtb.bin::
+
+ $ make distclean
+ $ make slimbootloader_defconfig
+ $ make all
+
+Prepare Slim Bootloader
+-----------------------
+
+1. Setup Build Environment for Slim Bootloader.
+
+ Refer to `Getting Started`_ page in `Slim Bootloader`_ document site.
+
+2. Get source code. Let's simply clone the repo::
+
+ $ git clone https://github.com/slimbootloader/slimbootloader.git
+
+3. Copy u-boot-dtb.bin to Slim Bootloader.
+ Slim Bootloader looks for a payload from the specific location.
+ Copy the build u-boot-dtb.bin to the expected location::
+
+ $ mkdir -p <Slim Bootloader Dir>/PayloadPkg/PayloadBins/
+ $ cp <U-Boot Dir>/u-boot-dtb.bin <Slim Bootloader Dir>/PayloadPkg/PayloadBins/u-boot-dtb.bin
+
+Build Instruction for Slim Bootloader for QEMU target
+-----------------------------------------------------
+
+Slim Bootloader supports multiple payloads, and a board of Slim Bootloader
+detects its target payload by PayloadId in board configuration.
+The PayloadId can be any 4 Bytes value.
+
+1. Update PayloadId. Let's use 'U-BT' as an example::
+
+ $ vi Platform/QemuBoardPkg/CfgData/CfgDataExt_Brd1.dlt
+ -GEN_CFG_DATA.PayloadId | 'AUTO'
+ +GEN_CFG_DATA.PayloadId | 'U-BT'
+
+2. Update payload text base. PAYLOAD_EXE_BASE must be the same as U-Boot
+ CONFIG_SYS_TEXT_BASE in board/intel/slimbootloader/Kconfig.
+ PAYLOAD_LOAD_HIGH must be 0::
+
+ $ vi Platform/QemuBoardPkg/BoardConfig.py
+ + self.PAYLOAD_LOAD_HIGH = 0
+ + self.PAYLOAD_EXE_BASE = 0x00100000
+
+3. Build QEMU target. Make sure u-boot-dtb.bin and U-BT PayloadId
+ in build command. The output is Outputs/qemu/SlimBootloader.bin::
+
+ $ python BuildLoader.py build qemu -p "OsLoader.efi:LLDR:Lz4;u-boot-dtb.bin:U-BT:Lzma"
+
+4. Launch Slim Bootloader on QEMU.
+ You should reach at U-Boot serial console::
+
+ $ qemu-system-x86_64 -machine q35 -nographic -serial mon:stdio -pflash Outputs/qemu/SlimBootloader.bin
+
+Test Linux booting on QEMU target
+---------------------------------
+
+Let's use LeafHill (APL) Yocto image for testing.
+Download it from http://downloads.yoctoproject.org/releases/yocto/yocto-2.0/machines/leafhill/.
+
+1. Prepare Yocto hard disk image::
+
+ $ wget http://downloads.yoctoproject.org/releases/yocto/yocto-2.0/machines/leafhill/leafhill-4.0-jethro-2.0.tar.bz2
+ $ tar -xvf leafhill-4.0-jethro-2.0.tar.bz2
+ $ ls -l leafhill-4.0-jethro-2.0/binary/core-image-sato-intel-corei7-64.hddimg
+
+2. Launch Slim Bootloader on QEMU with disk image::
+
+ $ qemu-system-x86_64 -machine q35 -nographic -serial mon:stdio -pflash Outputs/qemu/SlimBootloader.bin -drive id=mydrive,if=none,file=/path/to/core-image-sato-intel-corei7-64.hddimg,format=raw -device ide-hd,drive=mydrive
+
+3. Update boot environment values on shell::
+
+ => setenv bootfile vmlinuz
+ => setenv bootdev scsi
+ => boot
+
+Build Instruction for Slim Bootloader for LeafHill (APL) target
+---------------------------------------------------------------
+
+LeafHill is using PCI UART2 device as a serial port.
+For MEM32 serial port, CONFIG_SYS_NS16550_MEM32 needs to be enabled in U-Boot.
+
+1. Enable CONFIG_SYS_NS16550_MEM32 in U-Boot::
+
+ $ vi include/configs/slimbootloader.h
+ +#define CONFIG_SYS_NS16550_MEM32
+ #ifdef CONFIG_SYS_NS16550_MEM3
+
+2. Build U-Boot::
+
+ $ make disclean
+ $ make slimbootloader_defconfig
+ $ make all
+
+3. Copy u-boot-dtb.bin to Slim Bootloader.
+ Slim Bootloader looks for a payload from the specific location.
+ Copy the build u-boot-dtb.bin to the expected location::
+
+ $ mkdir -p <Slim Bootloader Dir>/PayloadPkg/PayloadBins/
+ $ cp <U-Boot Dir>/u-boot-dtb.bin <Slim Bootloader Dir>/PayloadPkg/PayloadBins/u-boot-dtb.bin
+
+4. Update PayloadId. Let's use 'U-BT' as an example::
+
+ $ vi Platform/ApollolakeBoardPkg/CfgData/CfgData_Int_LeafHill.dlt
+ -GEN_CFG_DATA.PayloadId | 'AUTO
+ +GEN_CFG_DATA.PayloadId | 'U-BT'
+
+5. Update payload text base.
+
+* PAYLOAD_EXE_BASE must be the same as U-Boot CONFIG_SYS_TEXT_BASE
+ in board/intel/slimbootloader/Kconfig.
+* PAYLOAD_LOAD_HIGH must be 0::
+
+ $ vi Platform/ApollolakeBoardPkg/BoardConfig.py
+ + self.PAYLOAD_LOAD_HIGH = 0
+ + self.PAYLOAD_EXE_BASE = 0x00100000
+
+6. Build APL target. Make sure u-boot-dtb.bin and U-BT PayloadId
+ in build command. The output is Outputs/apl/Stitch_Components.zip::
+
+ $ python BuildLoader.py build apl -p "OsLoader.efi:LLDR:Lz4;u-boot-dtb.bin:U-BT:Lzma"
+
+7. Stitch IFWI.
+
+ Refer to Apollolake_ page in Slim Bootloader document site::
+
+ $ python Platform/ApollolakeBoardPkg/Script/StitchLoader.py -i <Existing IFWI> -s Outputs/apl/Stitch_Components.zip -o <Output IFWI>
+
+8. Flash IFWI.
+
+ Use DediProg to flash IFWI. You should reach at U-Boot serial console.
+
+
+Build Instruction to use ELF U-Boot
+-----------------------------------
+
+1. Enable CONFIG_OF_EMBED::
+
+ $ vi configs/slimbootloader_defconfig
+ +CONFIG_OF_EMBED=y
+
+2. Build U-Boot::
+
+ $ make disclean
+ $ make slimbootloader_defconfig
+ $ make all
+ $ strip u-boot (removing symbol for reduced size)
+
+3. Do same steps as above
+
+* Copy u-boot (ELF) to PayloadBins directory
+* Update PayloadId 'U-BT' as above.
+* No need to set PAYLOAD_LOAD_HIGH and PAYLOAD_EXE_BASE.
+* Build Slim Bootloader. Use u-boot instead of u-boot-dtb.bin::
+
+ $ python BuildLoader.py build <qemu or apl> -p "OsLoader.efi:LLDR:Lz4;u-boot:U-BT:Lzma"
+
+.. _U-Boot: https://gitlab.denx.de/
+.. _`Slim Bootloader`: https://github.com/slimbootloader/
+.. _`Intel FSP`: https://github.com/IntelFsp/
+.. _`Getting Started`: https://slimbootloader.github.io/getting-started/
+.. _Apollolake: https://slimbootloader.github.io/supported-hardware/apollo-lake-crb.html#stitching
diff --git a/doc/board/renesas/index.rst b/doc/board/renesas/index.rst
new file mode 100644
index 0000000..34e62ba
--- /dev/null
+++ b/doc/board/renesas/index.rst
@@ -0,0 +1,10 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Renesas
+=======
+
+.. toctree::
+ :maxdepth: 2
+
+ sh7752evb
+ sh7753evb
diff --git a/doc/board/renesas/sh7752evb.rst b/doc/board/renesas/sh7752evb.rst
new file mode 100644
index 0000000..272d6dd
--- /dev/null
+++ b/doc/board/renesas/sh7752evb.rst
@@ -0,0 +1,79 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+R0P7752C00000RZ board
+=====================
+
+This board specification
+------------------------
+
+The R0P7752C00000RZ(board config name:sh7752evb) has the following device:
+
+ - SH7752 (SH-4A)
+ - DDR3-SDRAM 512MB
+ - SPI ROM 8MB
+ - Gigabit Ethernet controllers
+ - eMMC 4GB
+
+
+Configuration for This board
+----------------------------
+
+You can select the configuration as follows:
+
+ - make sh7752evb_config
+
+
+This board specific command
+---------------------------
+
+This board has the following its specific command:
+
+write_mac:
+ You can write MAC address to SPI ROM.
+
+Usage 1: Write MAC address
+
+.. code-block:: none
+
+ write_mac [GETHERC ch0] [GETHERC ch1]
+
+ For example:
+ => write_mac 74:90:50:00:33:9e 74:90:50:00:33:9f
+
+* We have to input the command as a single line (without carriage return)
+* We have to reset after input the command.
+
+Usage 2: Show current data
+
+.. code-block:: none
+
+ write_mac
+
+ For example:
+ => write_mac
+ GETHERC ch0 = 74:90:50:00:33:9e
+ GETHERC ch1 = 74:90:50:00:33:9f
+
+
+Update SPI ROM
+--------------
+
+1. Copy u-boot image to RAM area.
+2. Probe SPI device.
+
+.. code-block:: none
+
+ => sf probe 0
+ SF: Detected MX25L6405D with page size 64KiB, total 8 MiB
+
+3. Erase SPI ROM.
+
+.. code-block:: none
+
+ => sf erase 0 80000
+
+4. Write u-boot image to SPI ROM.
+
+.. code-block:: none
+
+ => sf write 0x48000000 0 80000
diff --git a/doc/board/renesas/sh7753evb.rst b/doc/board/renesas/sh7753evb.rst
new file mode 100644
index 0000000..c62a824
--- /dev/null
+++ b/doc/board/renesas/sh7753evb.rst
@@ -0,0 +1,79 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+SH7753 EVB board
+================
+
+This board specification
+------------------------
+
+The SH7753 EVB (board config name:sh7753evb) has the following device:
+
+ - SH7753 (SH-4A)
+ - DDR3-SDRAM 512MB
+ - SPI ROM 8MB
+ - Gigabit Ethernet controllers
+ - eMMC 4GB
+
+
+Configuration for This board
+----------------------------
+
+You can select the configuration as follows:
+
+ - make sh7753evb_config
+
+
+This board specific command
+---------------------------
+
+This board has the following its specific command:
+
+write_mac:
+ You can write MAC address to SPI ROM.
+
+Usage 1: Write MAC address
+
+.. code-block:: none
+
+ write_mac [GETHERC ch0] [GETHERC ch1]
+
+ For example:
+ => write_mac 74:90:50:00:33:9e 74:90:50:00:33:9f
+
+* We have to input the command as a single line (without carriage return)
+* We have to reset after input the command.
+
+Usage 2: Show current data
+
+.. code-block:: none
+
+ write_mac
+
+ For example:
+ => write_mac
+ GETHERC ch0 = 74:90:50:00:33:9e
+ GETHERC ch1 = 74:90:50:00:33:9f
+
+
+Update SPI ROM
+--------------
+
+1. Copy u-boot image to RAM area.
+2. Probe SPI device.
+
+.. code-block:: none
+
+ => sf probe 0
+ SF: Detected MX25L6405D with page size 64KiB, total 8 MiB
+
+3. Erase SPI ROM.
+
+.. code-block:: none
+
+ => sf erase 0 80000
+
+4. Write u-boot image to SPI ROM.
+
+.. code-block:: none
+
+ => sf write 0x48000000 0 80000
diff --git a/doc/board/sifive/fu540.rst b/doc/board/sifive/fu540.rst
new file mode 100644
index 0000000..7807f5b
--- /dev/null
+++ b/doc/board/sifive/fu540.rst
@@ -0,0 +1,368 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+HiFive Unleashed
+================
+
+FU540-C000 RISC-V SoC
+---------------------
+The FU540-C000 is the world’s first 4+1 64-bit RISC-V SoC from SiFive.
+
+The HiFive Unleashed development platform is based on FU540-C000 and capable
+of running Linux.
+
+Mainline support
+----------------
+The support for following drivers are already enabled:
+
+1. SiFive UART Driver.
+2. SiFive PRCI Driver for clock.
+3. Cadence MACB ethernet driver for networking support.
+4. SiFive SPI Driver.
+5. MMC SPI Driver for MMC/SD support.
+
+TODO:
+
+1. U-Boot expects the serial console device entry to be present under /chosen
+ DT node. Without a serial console U-Boot will panic. Example:
+
+.. code-block:: none
+
+ chosen {
+ stdout-path = "/soc/serial@10010000:115200";
+ };
+
+Building
+--------
+
+1. Add the RISC-V toolchain to your PATH.
+2. Setup ARCH & cross compilation enviornment variable:
+
+.. code-block:: none
+
+ export ARCH=riscv
+ export CROSS_COMPILE=<riscv64 toolchain prefix>
+
+3. make sifive_fu540_defconfig
+4. make
+
+Flashing
+--------
+
+The current U-Boot port is supported in S-mode only and loaded from DRAM.
+
+A prior stage M-mode firmware/bootloader (e.g OpenSBI) is required to
+boot the u-boot.bin in S-mode and provide M-mode runtime services.
+
+Currently, the u-boot.bin is used as a payload of the OpenSBI FW_PAYLOAD
+firmware. We need to compile OpenSBI with below command:
+
+.. code-block:: none
+
+ make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH=<path to u-boot.bin> FW_PAYLOAD_FDT_PATH=<path to hifive-unleashed-a00.dtb from Linux>
+
+(Note: Prefer hifive-unleashed-a00.dtb from Linux-5.3 or higher)
+(Note: Linux-5.2 is also fine but it does not have ethernet DT node)
+
+More detailed description of steps required to build FW_PAYLOAD firmware
+is beyond the scope of this document. Please refer OpenSBI documenation.
+(Note: OpenSBI git repo is at https://github.com/riscv/opensbi.git)
+
+Once the prior stage firmware/bootloader binary is generated, it should be
+copied to the first partition of the sdcard.
+
+.. code-block:: none
+
+ sudo dd if=<prior_stage_firmware_binary> of=/dev/disk2s1 bs=1024
+
+Booting
+-------
+Once you plugin the sdcard and power up, you should see the U-Boot prompt.
+
+Sample boot log from HiFive Unleashed board
+-------------------------------------------
+
+.. code-block:: none
+
+ U-Boot 2019.07-00024-g350ff02f5b (Jul 22 2019 - 11:45:02 +0530)
+
+ CPU: rv64imafdc
+ Model: SiFive HiFive Unleashed A00
+ DRAM: 8 GiB
+ MMC: spi@10050000:mmc@0: 0
+ In: serial@10010000
+ Out: serial@10010000
+ Err: serial@10010000
+ Net: eth0: ethernet@10090000
+ Hit any key to stop autoboot: 0
+ => version
+ U-Boot 2019.07-00024-g350ff02f5b (Jul 22 2019 - 11:45:02 +0530)
+
+ riscv64-linux-gcc.br_real (Buildroot 2018.11-rc2-00003-ga0787e9) 8.2.0
+ GNU ld (GNU Binutils) 2.31.1
+ => mmc info
+ Device: spi@10050000:mmc@0
+ Manufacturer ID: 3
+ OEM: 5344
+ Name: SU08G
+ Bus Speed: 20000000
+ Mode: SD Legacy
+ Rd Block Len: 512
+ SD version 2.0
+ High Capacity: Yes
+ Capacity: 7.4 GiB
+ Bus Width: 1-bit
+ Erase Group Size: 512 Bytes
+ => mmc part
+
+ Partition Map for MMC device 0 -- Partition Type: EFI
+
+ Part Start LBA End LBA Name
+ Attributes
+ Type GUID
+ Partition GUID
+ 1 0x00000800 0x000107ff "bootloader"
+ attrs: 0x0000000000000000
+ type: 2e54b353-1271-4842-806f-e436d6af6985
+ guid: 393bbd36-7111-491c-9869-ce24008f6403
+ 2 0x00040800 0x00ecdfde ""
+ attrs: 0x0000000000000000
+ type: 0fc63daf-8483-4772-8e79-3d69d8477de4
+ guid: 7fc9a949-5480-48c7-b623-04923080757f
+
+Now you can configure your networking, tftp server and use tftp boot method to
+load uImage.
+
+.. code-block:: none
+
+ => setenv ipaddr 10.206.7.133
+ => setenv netmask 255.255.252.0
+ => setenv serverip 10.206.4.143
+ => setenv gateway 10.206.4.1
+ => tftpboot ${kernel_addr_r} /sifive/fu540/Image
+ ethernet@10090000: PHY present at 0
+ ethernet@10090000: Starting autonegotiation...
+ ethernet@10090000: Autonegotiation complete
+ ethernet@10090000: link up, 1000Mbps full-duplex (lpa: 0x3c00)
+ Using ethernet@10090000 device
+ TFTP from server 10.206.4.143; our IP address is 10.206.7.133
+ Filename '/sifive/fu540/Image'.
+ Load address: 0x84000000
+ Loading: #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ ##########################################
+ 1.2 MiB/s
+ done
+ Bytes transferred = 8867100 (874d1c hex)
+ => tftpboot ${ramdisk_addr_r} /sifive/fu540/uRamdisk
+ ethernet@10090000: PHY present at 0
+ ethernet@10090000: Starting autonegotiation...
+ ethernet@10090000: Autonegotiation complete
+ ethernet@10090000: link up, 1000Mbps full-duplex (lpa: 0x3c00)
+ Using ethernet@10090000 device
+ TFTP from server 10.206.4.143; our IP address is 10.206.7.133
+ Filename '/sifive/fu540/uRamdisk'.
+ Load address: 0x88300000
+ Loading: #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ ##############
+ 418.9 KiB/s
+ done
+ Bytes transferred = 2398272 (249840 hex)
+ => tftpboot ${fdt_addr_r} /sifive/fu540/hifive-unleashed-a00.dtb
+ ethernet@10090000: PHY present at 0
+ ethernet@10090000: Starting autonegotiation...
+ ethernet@10090000: Autonegotiation complete
+ ethernet@10090000: link up, 1000Mbps full-duplex (lpa: 0x7c00)
+ Using ethernet@10090000 device
+ TFTP from server 10.206.4.143; our IP address is 10.206.7.133
+ Filename '/sifive/fu540/hifive-unleashed-a00.dtb'.
+ Load address: 0x88000000
+ Loading: ##
+ 1000 Bytes/s
+ done
+ Bytes transferred = 5614 (15ee hex)
+ => setenv bootargs "root=/dev/ram rw console=ttySIF0 ip=dhcp earlycon=sbi"
+ => booti ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}
+ ## Loading init Ramdisk from Legacy Image at 88300000 ...
+ Image Name: Linux RootFS
+ Image Type: RISC-V Linux RAMDisk Image (uncompressed)
+ Data Size: 2398208 Bytes = 2.3 MiB
+ Load Address: 00000000
+ Entry Point: 00000000
+ Verifying Checksum ... OK
+ ## Flattened Device Tree blob at 88000000
+ Booting using the fdt blob at 0x88000000
+ Using Device Tree in place at 0000000088000000, end 00000000880045ed
+
+ Starting kernel ...
+
+ [ 0.000000] OF: fdt: Ignoring memory range 0x80000000 - 0x80200000
+ [ 0.000000] Linux version 5.3.0-rc1-00003-g460ac558152f (anup@anup-lab-machine) (gcc version 8.2.0 (Buildroot 2018.11-rc2-00003-ga0787e9)) #6 SMP Mon Jul 22 10:01:01 IST 2019
+ [ 0.000000] earlycon: sbi0 at I/O port 0x0 (options '')
+ [ 0.000000] printk: bootconsole [sbi0] enabled
+ [ 0.000000] Initial ramdisk at: 0x(____ptrval____) (2398208 bytes)
+ [ 0.000000] Zone ranges:
+ [ 0.000000] DMA32 [mem 0x0000000080200000-0x00000000ffffffff]
+ [ 0.000000] Normal [mem 0x0000000100000000-0x000000027fffffff]
+ [ 0.000000] Movable zone start for each node
+ [ 0.000000] Early memory node ranges
+ [ 0.000000] node 0: [mem 0x0000000080200000-0x000000027fffffff]
+ [ 0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x000000027fffffff]
+ [ 0.000000] software IO TLB: mapped [mem 0xfbfff000-0xfffff000] (64MB)
+ [ 0.000000] CPU with hartid=0 is not available
+ [ 0.000000] CPU with hartid=0 is not available
+ [ 0.000000] elf_hwcap is 0x112d
+ [ 0.000000] percpu: Embedded 18 pages/cpu s34584 r8192 d30952 u73728
+ [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2067975
+ [ 0.000000] Kernel command line: root=/dev/ram rw console=ttySIF0 ip=dhcp earlycon=sbi
+ [ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
+ [ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
+ [ 0.000000] Sorting __ex_table...
+ [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
+ [ 0.000000] Memory: 8182308K/8386560K available (5916K kernel code, 368K rwdata, 1840K rodata, 213K init, 304K bss, 204252K reserved, 0K cma-reserved)
+ [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
+ [ 0.000000] rcu: Hierarchical RCU implementation.
+ [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
+ [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
+ [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
+ [ 0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0
+ [ 0.000000] plic: mapped 53 interrupts with 4 handlers for 9 contexts.
+ [ 0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [1]
+ [ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 3526361616960 ns
+ [ 0.000006] sched_clock: 64 bits at 1000kHz, resolution 1000ns, wraps every 2199023255500ns
+ [ 0.008559] Console: colour dummy device 80x25
+ [ 0.012989] Calibrating delay loop (skipped), value calculated using timer frequency.. 2.00 BogoMIPS (lpj=4000)
+ [ 0.023104] pid_max: default: 32768 minimum: 301
+ [ 0.028273] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
+ [ 0.035765] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
+ [ 0.045307] rcu: Hierarchical SRCU implementation.
+ [ 0.049875] smp: Bringing up secondary CPUs ...
+ [ 0.055729] smp: Brought up 1 node, 4 CPUs
+ [ 0.060599] devtmpfs: initialized
+ [ 0.064819] random: get_random_u32 called from bucket_table_alloc.isra.10+0x4e/0x160 with crng_init=0
+ [ 0.073720] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
+ [ 0.083176] futex hash table entries: 1024 (order: 4, 65536 bytes, linear)
+ [ 0.090721] NET: Registered protocol family 16
+ [ 0.106319] vgaarb: loaded
+ [ 0.108670] SCSI subsystem initialized
+ [ 0.112515] usbcore: registered new interface driver usbfs
+ [ 0.117758] usbcore: registered new interface driver hub
+ [ 0.123167] usbcore: registered new device driver usb
+ [ 0.128905] clocksource: Switched to clocksource riscv_clocksource
+ [ 0.141239] NET: Registered protocol family 2
+ [ 0.145506] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
+ [ 0.153754] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
+ [ 0.163466] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes, linear)
+ [ 0.173468] TCP: Hash tables configured (established 65536 bind 65536)
+ [ 0.179739] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
+ [ 0.186627] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
+ [ 0.194117] NET: Registered protocol family 1
+ [ 0.198417] RPC: Registered named UNIX socket transport module.
+ [ 0.203887] RPC: Registered udp transport module.
+ [ 0.208664] RPC: Registered tcp transport module.
+ [ 0.213429] RPC: Registered tcp NFSv4.1 backchannel transport module.
+ [ 0.219944] PCI: CLS 0 bytes, default 64
+ [ 0.224170] Unpacking initramfs...
+ [ 0.262347] Freeing initrd memory: 2336K
+ [ 0.266531] workingset: timestamp_bits=62 max_order=21 bucket_order=0
+ [ 0.280406] NFS: Registering the id_resolver key type
+ [ 0.284798] Key type id_resolver registered
+ [ 0.289048] Key type id_legacy registered
+ [ 0.293114] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
+ [ 0.300262] NET: Registered protocol family 38
+ [ 0.304432] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 254)
+ [ 0.311862] io scheduler mq-deadline registered
+ [ 0.316461] io scheduler kyber registered
+ [ 0.356421] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+ [ 0.363004] 10010000.serial: ttySIF0 at MMIO 0x10010000 (irq = 4, base_baud = 0) is a SiFive UART v0
+ [ 0.371468] printk: console [ttySIF0] enabled
+ [ 0.371468] printk: console [ttySIF0] enabled
+ [ 0.380223] printk: bootconsole [sbi0] disabled
+ [ 0.380223] printk: bootconsole [sbi0] disabled
+ [ 0.389589] 10011000.serial: ttySIF1 at MMIO 0x10011000 (irq = 1, base_baud = 0) is a SiFive UART v0
+ [ 0.398680] [drm] radeon kernel modesetting enabled.
+ [ 0.412395] loop: module loaded
+ [ 0.415214] sifive_spi 10040000.spi: mapped; irq=3, cs=1
+ [ 0.420628] sifive_spi 10050000.spi: mapped; irq=5, cs=1
+ [ 0.425897] libphy: Fixed MDIO Bus: probed
+ [ 0.429964] macb 10090000.ethernet: Registered clk switch 'sifive-gemgxl-mgmt'
+ [ 0.436743] macb: GEM doesn't support hardware ptp.
+ [ 0.441621] libphy: MACB_mii_bus: probed
+ [ 0.601316] Microsemi VSC8541 SyncE 10090000.ethernet-ffffffff:00: attached PHY driver [Microsemi VSC8541 SyncE] (mii_bus:phy_addr=10090000.ethernet-ffffffff:00, irq=POLL)
+ [ 0.615857] macb 10090000.ethernet eth0: Cadence GEM rev 0x10070109 at 0x10090000 irq 6 (70:b3:d5:92:f2:f3)
+ [ 0.625634] e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k
+ [ 0.631381] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
+ [ 0.637382] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
+ [ 0.643799] ehci-pci: EHCI PCI platform driver
+ [ 0.648261] ehci-platform: EHCI generic platform driver
+ [ 0.653497] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
+ [ 0.659599] ohci-pci: OHCI PCI platform driver
+ [ 0.664055] ohci-platform: OHCI generic platform driver
+ [ 0.669448] usbcore: registered new interface driver uas
+ [ 0.674575] usbcore: registered new interface driver usb-storage
+ [ 0.680642] mousedev: PS/2 mouse device common for all mice
+ [ 0.709493] mmc_spi spi1.0: SD/MMC host mmc0, no DMA, no WP, no poweroff, cd polling
+ [ 0.716615] usbcore: registered new interface driver usbhid
+ [ 0.722023] usbhid: USB HID core driver
+ [ 0.726738] NET: Registered protocol family 10
+ [ 0.731359] Segment Routing with IPv6
+ [ 0.734332] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
+ [ 0.740687] NET: Registered protocol family 17
+ [ 0.744660] Key type dns_resolver registered
+ [ 0.806775] mmc0: host does not support reading read-only switch, assuming write-enable
+ [ 0.814020] mmc0: new SDHC card on SPI
+ [ 0.820137] mmcblk0: mmc0:0000 SU08G 7.40 GiB
+ [ 0.850220] mmcblk0: p1 p2
+ [ 3.821524] macb 10090000.ethernet eth0: link up (1000/Full)
+ [ 3.828938] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
+ [ 3.848919] Sending DHCP requests .., OK
+ [ 6.252076] IP-Config: Got DHCP answer from 10.206.4.1, my address is 10.206.7.133
+ [ 6.259624] IP-Config: Complete:
+ [ 6.262831] device=eth0, hwaddr=70:b3:d5:92:f2:f3, ipaddr=10.206.7.133, mask=255.255.252.0, gw=10.206.4.1
+ [ 6.272809] host=dhcp-10-206-7-133, domain=sdcorp.global.sandisk.com, nis-domain=(none)
+ [ 6.281228] bootserver=10.206.126.11, rootserver=10.206.126.11, rootpath=
+ [ 6.281232] nameserver0=10.86.1.1, nameserver1=10.86.2.1
+ [ 6.294179] ntpserver0=10.86.1.1, ntpserver1=10.86.2.1
+ [ 6.301026] Freeing unused kernel memory: 212K
+ [ 6.304683] This architecture does not have kernel memory protection.
+ [ 6.311121] Run /init as init process
+ _ _
+ | ||_|
+ | | _ ____ _ _ _ _
+ | || | _ \| | | |\ \/ /
+ | || | | | | |_| |/ \
+ |_||_|_| |_|\____|\_/\_/
+
+ Busybox Rootfs
+
+ Please press Enter to activate this console.
+ / #
diff --git a/doc/board/sifive/index.rst b/doc/board/sifive/index.rst
new file mode 100644
index 0000000..ad614c9
--- /dev/null
+++ b/doc/board/sifive/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+SiFive
+======
+
+.. toctree::
+ :maxdepth: 2
+
+ fu540
diff --git a/doc/board/xilinx/index.rst b/doc/board/xilinx/index.rst
new file mode 100644
index 0000000..2416fbd
--- /dev/null
+++ b/doc/board/xilinx/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Xilinx
+======
+
+.. toctree::
+ :maxdepth: 2
+
+ zynq
diff --git a/doc/board/xilinx/zynq.rst b/doc/board/xilinx/zynq.rst
new file mode 100644
index 0000000..3f0513e
--- /dev/null
+++ b/doc/board/xilinx/zynq.rst
@@ -0,0 +1,95 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. (C) Copyright 2013 Xilinx, Inc.
+
+ZYNQ
+====
+
+About this
+----------
+
+This document describes the information about Xilinx Zynq U-Boot -
+like supported boards, ML status and TODO list.
+
+Zynq boards
+-----------
+
+Xilinx Zynq-7000 All Programmable SoCs enable extensive system level
+differentiation, integration, and flexibility through hardware, software,
+and I/O programmability.
+
+* zc702 (single qspi, gem0, mmc) [1]
+* zc706 (dual parallel qspi, gem0, mmc) [2]
+* zed (single qspi, gem0, mmc) [3]
+* microzed (single qspi, gem0, mmc) [4]
+* zc770
+ - zc770-xm010 (single qspi, gem0, mmc)
+ - zc770-xm011 (8 or 16 bit nand)
+ - zc770-xm012 (nor)
+ - zc770-xm013 (dual parallel qspi, gem1)
+
+Building
+--------
+
+configure and build for zc702 board::
+
+ $ make zynq_zc702_config
+ $ make
+
+Bootmode
+--------
+
+Zynq has a facility to read the bootmode from the slcr bootmode register
+once user is setting through jumpers on the board - see page no:1546 on [5]
+
+All possible bootmode values are defined in Table 6-2:Boot_Mode MIO Pins
+on [5].
+
+board_late_init() will read the bootmode values using slcr bootmode register
+at runtime and assign the modeboot variable to specific bootmode string which
+is intern used in autoboot.
+
+SLCR bootmode register Bit[3:0] values
+
+.. code-block:: c
+
+ #define ZYNQ_BM_NOR 0x02
+ #define ZYNQ_BM_SD 0x05
+ #define ZYNQ_BM_JTAG 0x0
+
+"modeboot" variable can assign any of "norboot", "sdboot" or "jtagboot"
+bootmode strings at runtime.
+
+Mainline status
+---------------
+
+- Added basic board configurations support.
+- Added zynq u-boot bsp code - arch/arm/cpu/armv7/zynq
+- Added zynq boards named - zc70x, zed, microzed, zc770_xm010/xm011/xm012/xm013
+- Added zynq drivers:
+
+ :serial: drivers/serial/serial_zynq.c
+ :net: drivers/net/zynq_gem.c
+ :mmc: drivers/mmc/zynq_sdhci.c
+ :spi: drivers/spi/zynq_spi.c
+ :qspi: drivers/spi/zynq_qspi.c
+ :i2c: drivers/i2c/zynq_i2c.c
+ :nand: drivers/mtd/nand/raw/zynq_nand.c
+
+- Done proper cleanups on board configurations
+- Added basic FDT support for zynq boards
+- d-cache support for zynq_gem.c
+
+TODO
+----
+
+Add FDT support on individual drivers
+
+* [1] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC702-G.htm
+* [2] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC706-G.htm
+* [3] http://zedboard.org/product/zedboard
+* [4] http://zedboard.org/product/microzed
+* [5] http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
+
+
+.. Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
+.. Sun Dec 15 14:52:41 IST 2013
diff --git a/doc/conf.py b/doc/conf.py
index 168c313..0772fb6 100644
--- a/doc/conf.py
+++ b/doc/conf.py
@@ -170,7 +170,7 @@
# The name of an image file (relative to this directory) to place at the top
# of the sidebar.
-#html_logo = None
+html_logo = '../tools/logos/u-boot_logo.svg'
# The name of an image file (within the static path) to use as favicon of the
# docs. This file should be a Windows icon file (.ico) being 16x16 or 32x32
diff --git a/doc/device-tree-bindings/clock/st,stm32mp1.txt b/doc/device-tree-bindings/clock/st,stm32mp1.txt
index 02e1460..ec1d703 100644
--- a/doc/device-tree-bindings/clock/st,stm32mp1.txt
+++ b/doc/device-tree-bindings/clock/st,stm32mp1.txt
@@ -164,8 +164,10 @@
- clk-csi
At boot the clock tree initialization will
- - enable oscillators present in device tree
+ - enable oscillators present in device tree and not disabled
+ (node with status="disabled"),
- disable HSI oscillator if the node is absent (always activated by bootrom)
+ and not disabled (node with status="disabled").
Optional properties :
diff --git a/doc/device-tree-bindings/gpio/gpio.txt b/doc/device-tree-bindings/gpio/gpio.txt
index f7a158d..e146917 100644
--- a/doc/device-tree-bindings/gpio/gpio.txt
+++ b/doc/device-tree-bindings/gpio/gpio.txt
@@ -210,3 +210,63 @@
Here, three GPIO ranges are defined wrt. two pin controllers. pinctrl1 GPIO
ranges are defined using pin numbers whereas the GPIO ranges wrt. pinctrl2
are named "foo" and "bar".
+
+3) GPIO hog definitions
+-----------------------
+
+The GPIO chip may contain GPIO hog definitions. GPIO hogging is a mechanism
+providing automatic GPIO request and configuration as part of the
+gpio-controller's driver probe function.
+
+Each GPIO hog definition is represented as a child node of the GPIO controller.
+Required properties:
+- gpio-hog: A property specifying that this child node represents a GPIO hog.
+- gpios: Store the GPIO information (id, flags) for the GPIO to
+ affect.
+
+ ! Not yet support more than one gpio !
+
+Only one of the following properties scanned in the order shown below.
+- input: A property specifying to set the GPIO direction as input.
+- output-low A property specifying to set the GPIO direction as output with
+ the value low.
+- output-high A property specifying to set the GPIO direction as output with
+ the value high.
+
+Optional properties:
+- line-name: The GPIO label name. If not present the node name is used.
+
+Example:
+
+ tca6416@20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ env_reset {
+ gpio-hog;
+ input;
+ gpios = <6 GPIO_ACTIVE_LOW>;
+ };
+ boot_rescue {
+ gpio-hog;
+ input;
+ line-name = "foo-bar-gpio";
+ gpios = <7 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+For the above Example you can than access the gpio in your boardcode
+with:
+
+ struct gpio_desc *desc;
+ int ret;
+
+ ret = gpio_hog_lookup_name("boot_rescue", &desc);
+ if (ret)
+ return;
+ if (dm_gpio_get_value(desc) == 1)
+ printf("\nBooting into Rescue System\n");
+ else if (dm_gpio_get_value(desc) == 0)
+ printf("\nBoot normal\n");
diff --git a/doc/device-tree-bindings/net/fsl-tsec-phy.txt b/doc/device-tree-bindings/net/fsl-tsec-phy.txt
index c5bf48c..59989e3 100644
--- a/doc/device-tree-bindings/net/fsl-tsec-phy.txt
+++ b/doc/device-tree-bindings/net/fsl-tsec-phy.txt
@@ -28,13 +28,13 @@
Required properties:
- compatible : Should define the compatible device type for the
- mdio. Currently supported string/device is "fsl,tsec-mdio".
+ mdio. Currently supported string/device is "fsl,etsec2-mdio".
- reg : Offset and length of the register set for the device
Example:
mdio@24520 {
- compatible = "fsl,tsec-mdio";
+ compatible = "fsl,etsec2-mdio";
reg = <0x24520 0x20>;
ethernet-phy@0 {
diff --git a/doc/device-tree-bindings/net/marvell-mdio.txt b/doc/device-tree-bindings/net/marvell-mdio.txt
new file mode 100644
index 0000000..e2038e2
--- /dev/null
+++ b/doc/device-tree-bindings/net/marvell-mdio.txt
@@ -0,0 +1,15 @@
+* Marvell MDIO Ethernet Controller interface
+
+The Ethernet controllers of the Marvel Armada 3700 and Armada 7k/8k
+have an identical unit that provides an interface with the MDIO bus.
+This driver handles this MDIO interface.
+
+Mandatory properties:
+SoC specific:
+ - #address-cells: Must be <1>.
+ - #size-cells: Must be <0>.
+ - compatible: Should be "marvell,orion-mdio" (for SMI)
+ "marvell,xmdio" (for XSMI)
+ - reg: Base address and size SMI/XMSI bus.
+
+Please refer to "mdio.txt" for generic MDIO bus bindings.
diff --git a/doc/device-tree-bindings/net/mdio-mux-reg.txt b/doc/device-tree-bindings/net/mdio-mux-reg.txt
new file mode 100644
index 0000000..0ac34dc
--- /dev/null
+++ b/doc/device-tree-bindings/net/mdio-mux-reg.txt
@@ -0,0 +1,82 @@
+Device tree structures used by register based MDIO muxes is described here.
+This binding is based on reg-mux.txt binding in Linux and is currently used by
+mdio-mux-i2creg driver in U-Boot.
+
+Required properties:
+#mux-control-cells = <1> indicates how many registers are used for mux
+ selection. mux-reg-mask property described below must
+ include this number of pairs.
+mux-reg-masks = <reg mask> describes pairs of register offset and register mask.
+ Register bits enabled in mask are set to the selection
+ value defined in reg property of child MDIOs to control
+ selection.
+Properties described in mdio-mux.txt also apply.
+
+Example structure, used on Freescale LS1028A QDS board:
+
+&i2c0 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+
+ fpga@66 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "simple-mfd";
+ reg = <0x66>;
+
+ mux-mdio@54 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mdio-mux-i2creg";
+ reg = <0x54>;
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x54 0xf0>;
+ mdio-parent-bus = <&mdio0>;
+
+ /* on-board MDIO with a single RGMII PHY */
+ mdio@00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x00>;
+
+ /* on-board 1G RGMII PHY */
+ qds_phy0: phy@5 {
+ reg = <5>;
+ };
+ };
+ /* card slot 1 */
+ mdio@40 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x40>;
+ /* VSC8234 1G SGMII card */
+ sgmii_port0: phy@1c {
+ reg = <0x1c>;
+ };
+ };
+ /* card slot 2 */
+ mdio@50 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x50>;
+ };
+ /* card slot 3 */
+ mdio@60 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x60>;
+ };
+ /* card slot 4 */
+ mdio@70 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x70>;
+ };
+ };
+ };
+};
+
+/* Parent MDIO, defined in SoC .dtsi file, just enabled here */
+&mdio0 {
+ status = "okay";
+};
diff --git a/doc/device-tree-bindings/net/mdio-mux.txt b/doc/device-tree-bindings/net/mdio-mux.txt
new file mode 100644
index 0000000..eaa31ef
--- /dev/null
+++ b/doc/device-tree-bindings/net/mdio-mux.txt
@@ -0,0 +1,138 @@
+The expected structure of an MDIO MUX device tree node is described here. This
+is heavily based on current Linux specification.
+One notable difference to Linux is that mdio-parent-bus is currently required
+by U-Boot, not optional as is in Linux. Current U-Boot MDIO MUX udevice class
+implementation does not have specific support for MDIOs with an integrated MUX,
+the property should be made optional if such support is added.
+
+The MDIO buses downstream of the MUX should be described in the device tree as
+child nodes as indicated below.
+
+Required properties:
+mdio-parent-bus = a phandle to the MDIO bus used to perform actual I/O. This is
+ typically a real MDIO device, unless there are cascaded MUXes.
+#address-cells = <1>, each MDIO group is identified by one 32b value.
+#size-cells = <0>
+
+Other properties:
+The properties described here are sufficient for MDIO MUX DM class code, but
+MUX drivers may define additional properties, either required or optional.
+
+Required properties in child nodes:
+reg = value to be configured on the MUX to select the respective downstream
+ MDIO.
+
+Child nodes should normally contain PHY nodes, referenced by phandle from
+ethernet nodes of the eth interfaces using these PHYs.
+
+Example structure, extracted from Linux bindings document:
+
+ /* The parent MDIO bus. */
+ smi1: mdio@1180000001900 {
+ compatible = "cavium,octeon-3860-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x11800 0x00001900 0x0 0x40>;
+ };
+ /*
+ * An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a
+ * pair of GPIO lines. Child busses 2 and 3 populated with 4
+ * PHYs each.
+ */
+ mdio-mux {
+ compatible = "mdio-mux-gpio";
+ gpios = <&gpio1 3 0>, <&gpio1 4 0>;
+ mdio-parent-bus = <&smi1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mdio@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy11: ethernet-phy@1 {
+ reg = <1>;
+ compatible = "marvell,88e1149r";
+ marvell,reg-init = <3 0x10 0 0x5777>,
+ <3 0x11 0 0x00aa>,
+ <3 0x12 0 0x4105>,
+ <3 0x13 0 0x0a60>;
+ interrupt-parent = <&gpio>;
+ interrupts = <10 8>; /* Pin 10, active low */
+ };
+ phy12: ethernet-phy@2 {
+ reg = <2>;
+ compatible = "marvell,88e1149r";
+ marvell,reg-init = <3 0x10 0 0x5777>,
+ <3 0x11 0 0x00aa>,
+ <3 0x12 0 0x4105>,
+ <3 0x13 0 0x0a60>;
+ interrupt-parent = <&gpio>;
+ interrupts = <10 8>; /* Pin 10, active low */
+ };
+ phy13: ethernet-phy@3 {
+ reg = <3>;
+ compatible = "marvell,88e1149r";
+ marvell,reg-init = <3 0x10 0 0x5777>,
+ <3 0x11 0 0x00aa>,
+ <3 0x12 0 0x4105>,
+ <3 0x13 0 0x0a60>;
+ interrupt-parent = <&gpio>;
+ interrupts = <10 8>; /* Pin 10, active low */
+ };
+ phy14: ethernet-phy@4 {
+ reg = <4>;
+ compatible = "marvell,88e1149r";
+ marvell,reg-init = <3 0x10 0 0x5777>,
+ <3 0x11 0 0x00aa>,
+ <3 0x12 0 0x4105>,
+ <3 0x13 0 0x0a60>;
+ interrupt-parent = <&gpio>;
+ interrupts = <10 8>; /* Pin 10, active low */
+ };
+ };
+ mdio@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy21: ethernet-phy@1 {
+ reg = <1>;
+ compatible = "marvell,88e1149r";
+ marvell,reg-init = <3 0x10 0 0x5777>,
+ <3 0x11 0 0x00aa>,
+ <3 0x12 0 0x4105>,
+ <3 0x13 0 0x0a60>;
+ interrupt-parent = <&gpio>;
+ interrupts = <12 8>; /* Pin 12, active low */
+ };
+ phy22: ethernet-phy@2 {
+ reg = <2>;
+ compatible = "marvell,88e1149r";
+ marvell,reg-init = <3 0x10 0 0x5777>,
+ <3 0x11 0 0x00aa>,
+ <3 0x12 0 0x4105>,
+ <3 0x13 0 0x0a60>;
+ interrupt-parent = <&gpio>;
+ interrupts = <12 8>; /* Pin 12, active low */
+ };
+ phy23: ethernet-phy@3 {
+ reg = <3>;
+ compatible = "marvell,88e1149r";
+ marvell,reg-init = <3 0x10 0 0x5777>,
+ <3 0x11 0 0x00aa>,
+ <3 0x12 0 0x4105>,
+ <3 0x13 0 0x0a60>;
+ interrupt-parent = <&gpio>;
+ interrupts = <12 8>; /* Pin 12, active low */
+ };
+ phy24: ethernet-phy@4 {
+ reg = <4>;
+ compatible = "marvell,88e1149r";
+ marvell,reg-init = <3 0x10 0 0x5777>,
+ <3 0x11 0 0x00aa>,
+ <3 0x12 0 0x4105>,
+ <3 0x13 0 0x0a60>;
+ interrupt-parent = <&gpio>;
+ interrupts = <12 8>; /* Pin 12, active low */
+ };
+ };
+ };
diff --git a/doc/device-tree-bindings/net/mdio.txt b/doc/device-tree-bindings/net/mdio.txt
new file mode 100644
index 0000000..1595325
--- /dev/null
+++ b/doc/device-tree-bindings/net/mdio.txt
@@ -0,0 +1,36 @@
+Common MDIO bus properties.
+
+These are generic properties that can apply to any MDIO bus.
+
+Optional properties:
+ - device-name - If present it is used to name the device and MDIO bus.
+ The name must be unique and must not contain spaces.
+
+A list of child nodes, one per device on the bus is expected. These could be
+PHYs, switches or similar devices and child nodes should follow the specific
+binding for the device type.
+
+Example :
+This example shows the structure used for the external MDIO bus on NXP LS1028A
+RDB board. Note that this MDIO device is an integrated PCI function and
+requires no compatible property for probing.
+
+/* definition in SoC dtsi file */
+ pcie@1f0000000 {
+
+ mdio0: pci@0,3 {
+ #address-cells=<0>;
+ #size-cells=<1>;
+ reg = <0x000300 0 0 0 0>;
+ status = "disabled";
+ device-name = "emdio";
+ };
+ };
+/* definition of PHYs in RDB dts file */
+&mdio0 {
+ status = "okay";
+ rdb_phy0: phy@2 {
+ reg = <2>;
+ };
+};
+
diff --git a/doc/device-tree-bindings/pci_endpoint/cdns,cdns-pcie-ep.txt b/doc/device-tree-bindings/pci_endpoint/cdns,cdns-pcie-ep.txt
new file mode 100644
index 0000000..7705430
--- /dev/null
+++ b/doc/device-tree-bindings/pci_endpoint/cdns,cdns-pcie-ep.txt
@@ -0,0 +1,18 @@
+* Cadence PCIe endpoint controller
+
+Required properties:
+- compatible: Should contain "cdns,cdns-pcie-ep" to identify the IP used.
+- reg: Should contain the controller register base address.
+
+Optional properties:
+- max-functions: Maximum number of functions that can be configured (default 1).
+- cdns,max-outbound-regions: Set to maximum number of outbound regions (default 8)
+
+Example:
+
+pcie_ep@fc000000 {
+ compatible = "cdns,cdns-pcie-ep";
+ reg = <0x0 0xfc000000 0x0 0x01000000>;
+ cdns,max-outbound-regions = <16>;
+ max-functions = /bits/ 8 <8>;
+};
diff --git a/doc/device-tree-bindings/pinctrl/st,stm32-pinctrl.txt b/doc/device-tree-bindings/pinctrl/st,stm32-pinctrl.txt
index c41ae91..0016925 100644
--- a/doc/device-tree-bindings/pinctrl/st,stm32-pinctrl.txt
+++ b/doc/device-tree-bindings/pinctrl/st,stm32-pinctrl.txt
@@ -8,8 +8,13 @@
Pin controller node:
Required properies:
- compatible: value should be one of the following:
- (a) "st,stm32f429-pinctrl"
- (b) "st,stm32f746-pinctrl"
+ "st,stm32f429-pinctrl"
+ "st,stm32f469-pinctrl"
+ "st,stm32f746-pinctrl"
+ "st,stm32f769-pinctrl"
+ "st,stm32h743-pinctrl"
+ "st,stm32mp157-pinctrl"
+ "st,stm32mp157-z-pinctrl"
- #address-cells: The value of this property must be 1
- #size-cells : The value of this property must be 1
- ranges : defines mapping between pin controller node (parent) to
@@ -32,13 +37,30 @@
Optional properties:
- reset: : Reference to the reset controller
- - interrupt-parent: phandle of the interrupt parent to which the external
- GPIO interrupts are forwarded to.
- - st,syscfg: Should be phandle/offset pair. The phandle to the syscon node
- which includes IRQ mux selection register, and the offset of the IRQ mux
- selection register.
+ - st,syscfg: Should be phandle/offset/mask.
+ -The phandle to the syscon node which includes IRQ mux selection register.
+ -The offset of the IRQ mux selection register
+ -The field mask of IRQ mux, needed if different of 0xf.
+ - gpio-ranges: Define a dedicated mapping between a pin-controller and
+ a gpio controller. Format is <&phandle a b c> with:
+ -(phandle): phandle of pin-controller.
+ -(a): gpio base offset in range.
+ -(b): pin base offset in range.
+ -(c): gpio count in range
+ This entry has to be used either if there are holes inside a bank:
+ GPIOB0/B1/B2/B14/B15 (see example 2)
+ or if banks are not contiguous:
+ GPIOA/B/C/E...
+ NOTE: If "gpio-ranges" is used for a gpio controller, all gpio-controller
+ have to use a "gpio-ranges" entry.
+ More details in Documentation/devicetree/bindings/gpio/gpio.txt.
+ - st,bank-ioport: should correspond to the EXTI IOport selection (EXTI line
+ used to select GPIOs as interrupts).
+ - hwlocks: reference to a phandle of a hardware spinlock provider node.
+ - st,package: Indicates the SOC package used.
+ More details in include/dt-bindings/pinctrl/stm32-pinfunc.h
-Example:
+Example 1:
#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
...
@@ -60,6 +82,43 @@
pin-functions nodes follow...
};
+Example 2:
+#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
+...
+
+ pinctrl: pin-controller {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stm32f429-pinctrl";
+ ranges = <0 0x40020000 0x3000>;
+ pins-are-numbered;
+
+ gpioa: gpio@40020000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x0 0x400>;
+ resets = <&reset_ahb1 0>;
+ st,bank-name = "GPIOA";
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@40020400 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x0 0x400>;
+ resets = <&reset_ahb1 0>;
+ st,bank-name = "GPIOB";
+ ngpios = 4;
+ gpio-ranges = <&pinctrl 0 16 3>,
+ <&pinctrl 14 30 2>;
+ };
+
+
+ ...
+ pin-functions nodes follow...
+ };
+
+
Contents of function subnode node:
----------------------------------
Subnode format
@@ -83,14 +142,31 @@
- port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
- line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
- function: The function number, can be:
- * 0 : GPIO IN
+ * 0 : GPIO
* 1 : Alternate Function 0
* 2 : Alternate Function 1
* 3 : Alternate Function 2
* ...
* 16 : Alternate Function 15
* 17 : Analog
- * 18 : GPIO OUT
+
+ To simplify the usage, macro is available to generate "pinmux" field.
+ This macro is available here:
+ - include/dt-bindings/pinctrl/stm32-pinfunc.h
+
+ Some examples of using macro:
+ /* GPIO A9 set as alernate function 2 */
+ ... {
+ pinmux = <STM32_PINMUX('A', 9, AF2)>;
+ };
+ /* GPIO A9 set as GPIO */
+ ... {
+ pinmux = <STM32_PINMUX('A', 9, GPIO)>;
+ };
+ /* GPIO A9 set as analog */
+ ... {
+ pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+ };
Optional properties:
- GENERIC_PINCONFIG: is the generic pinconfig options to use.
@@ -114,13 +190,13 @@
...
usart1_pins_a: usart1@0 {
pins1 {
- pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
+ pinmux = <STM32_PINMUX('A', 9, AF7)>;
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
- pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
+ pinmux = <STM32_PINMUX('A', 10, AF7)>;
bias-disable;
};
};
@@ -129,5 +205,4 @@
&usart1 {
pinctrl-0 = <&usart1_pins_a>;
pinctrl-names = "default";
- status = "okay";
};
diff --git a/doc/device-tree-bindings/power/ti,sci-pm-domain.txt b/doc/device-tree-bindings/power/ti,sci-pm-domain.txt
index 0e190e2..72d9fbc 100644
--- a/doc/device-tree-bindings/power/ti,sci-pm-domain.txt
+++ b/doc/device-tree-bindings/power/ti,sci-pm-domain.txt
@@ -17,8 +17,15 @@
Required Properties:
--------------------
- compatible: Must be "ti,sci-pm-domain"
-- #power-domain-cells: Must be 1 so that an id can be provided in each
- device node.
+- #power-domain-cells: Can be one of the following:
+ 1: Containing the device id of each node
+ 2: First entry should be device id
+ Second entry should be one of the floowing:
+ TI_SCI_PD_EXCLUSIVE: To allow device to be
+ exclusively controlled by
+ the requesting hosts.
+ TI_SCI_PD_SHARED: To allow device to be shared
+ by multiple hosts.
Example (AM65x):
----------------
diff --git a/doc/device-tree-bindings/sound/intel-hda.txt b/doc/device-tree-bindings/sound/intel-hda.txt
index fb2ce55..aa96be0 100644
--- a/doc/device-tree-bindings/sound/intel-hda.txt
+++ b/doc/device-tree-bindings/sound/intel-hda.txt
@@ -12,6 +12,7 @@
Optional properties
- intel,beep-nid: Node ID to use for beep (will be detected if not provided)
+- codec-enable-gpio : The GPIO used to enable the audio codec
Required subnodes:
- codecs: Contains a list of codec nodes
diff --git a/doc/device-tree-bindings/sound/nvidia,tegra-audio-max98090.txt b/doc/device-tree-bindings/sound/nvidia,tegra-audio-max98090.txt
new file mode 100644
index 0000000..25c63ea
--- /dev/null
+++ b/doc/device-tree-bindings/sound/nvidia,tegra-audio-max98090.txt
@@ -0,0 +1,54 @@
+NVIDIA Tegra audio complex, with MAX98090 CODEC
+
+Required properties:
+- compatible : "nvidia,tegra-audio-max98090"
+- clocks : Must contain an entry for each entry in clock-names.
+ See ../clocks/clock-bindings.txt for details.
+- clock-names : Must include the following entries:
+ - pll_a
+ - pll_a_out0
+ - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
+- nvidia,model : The user-visible name of this sound complex.
+- nvidia,audio-routing : A list of the connections between audio components.
+ Each entry is a pair of strings, the first being the connection's sink,
+ the second being the connection's source. Valid names for sources and
+ sinks are the MAX98090's pins (as documented in its binding), and the jacks
+ on the board:
+
+ * Headphones
+ * Speakers
+ * Mic Jack
+ * Int Mic
+
+- nvidia,i2s-controller : The phandle of the Tegra I2S controller that's
+ connected to the CODEC.
+- nvidia,audio-codec : The phandle of the MAX98090 audio codec.
+
+Optional properties:
+- nvidia,hp-det-gpios : The GPIO that detect headphones are plugged in
+- nvidia,mic-det-gpios : The GPIO that detect microphones are plugged in
+- codec-enable-gpio : The GPIO used to enable the audio codec
+
+Example:
+
+sound {
+ compatible = "nvidia,tegra-audio-max98090-venice2",
+ "nvidia,tegra-audio-max98090";
+ nvidia,model = "NVIDIA Tegra Venice2";
+
+ nvidia,audio-routing =
+ "Headphones", "HPR",
+ "Headphones", "HPL",
+ "Speakers", "SPKR",
+ "Speakers", "SPKL",
+ "Mic Jack", "MICBIAS",
+ "IN34", "Mic Jack";
+
+ nvidia,i2s-controller = <&tegra_i2s1>;
+ nvidia,audio-codec = <&acodec>;
+
+ clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
+ <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA124_CLK_EXTERN1>;
+ clock-names = "pll_a", "pll_a_out0", "mclk";
+};
diff --git a/doc/device-tree-bindings/sound/snow.txt b/doc/device-tree-bindings/sound/snow.txt
new file mode 100644
index 0000000..fa06956
--- /dev/null
+++ b/doc/device-tree-bindings/sound/snow.txt
@@ -0,0 +1,32 @@
+Audio Binding for Snow boards
+
+Required properties:
+- compatible : Can be one of the following,
+ "google,snow-audio-max98090" or
+ "google,snow-audio-max98091" or
+ "google,snow-audio-max98095"
+- samsung,i2s-controller (deprecated): The phandle of the Samsung I2S controller
+- samsung,audio-codec (deprecated): The phandle of the audio codec
+
+Required sub-nodes:
+
+ - 'cpu' subnode with a 'sound-dai' property containing the phandle of the I2S
+ controller
+ - 'codec' subnode with a 'sound-dai' property containing list of phandles
+ to the CODEC nodes, first entry must be the phandle of the MAX98090,
+ MAX98091 or MAX98095 CODEC (exact device type is indicated by the compatible
+ string) and the second entry must be the phandle of the HDMI IP block node
+
+Optional:
+- samsung,model: The name of the sound-card
+- codec-enable-gpio : The GPIO used to enable the audio codec
+
+Example:
+
+sound {
+ compatible = "google,snow-audio-max98095";
+
+ samsung,model = "Snow-I2S-MAX98095";
+ samsung,i2s-controller = <&i2s0>;
+ samsung,audio-codec = <&max98095>;
+};
diff --git a/doc/device-tree-bindings/spi/spi-stm32-qspi.txt b/doc/device-tree-bindings/spi/spi-stm32-qspi.txt
index cec3e12..adeeb63 100644
--- a/doc/device-tree-bindings/spi/spi-stm32-qspi.txt
+++ b/doc/device-tree-bindings/spi/spi-stm32-qspi.txt
@@ -1,39 +1,44 @@
-STM32 QSPI controller device tree bindings
---------------------------------------------
+* STMicroelectronics Quad Serial Peripheral Interface(QSPI)
Required properties:
-- compatible : should be "st,stm32-qspi".
-- reg : 1. Physical base address and size of SPI registers map.
- 2. Physical base address & size of mapped NOR Flash.
-- spi-max-frequency : Max supported spi frequency.
-- status : enable in requried dts.
+- compatible: should be "st,stm32f469-qspi"
+- reg: the first contains the register location and length.
+ the second contains the memory mapping address and length
+- reg-names: should contain the reg names "qspi" "qspi_mm"
+- interrupts: should contain the interrupt for the device
+- clocks: the phandle of the clock needed by the QSPI controller
+- A pinctrl must be defined to set pins in mode of operation for QSPI transfer
-Connected flash properties
---------------------------
-- spi-max-frequency : Max supported spi frequency.
-- spi-tx-bus-width : Bus width (number of lines) for writing (1-4)
-- spi-rx-bus-width : Bus width (number of lines) for reading (1-4)
-- memory-map : Address and size for memory-mapping the flash
+Optional properties:
+- resets: must contain the phandle to the reset controller.
+
+A spi flash (NOR/NAND) must be a child of spi node and could have some
+properties. Also see jedec,spi-nor.txt.
+
+Required properties:
+- reg: chip-Select number (QSPI controller may connect 2 flashes)
+- spi-max-frequency: max frequency of spi bus
+
+Optional property:
+- spi-rx-bus-width: see ./spi-bus.txt for the description
Example:
- qspi: quadspi@A0001000 {
- compatible = "st,stm32-qspi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
- reg-names = "QuadSPI", "QuadSPI-memory";
- interrupts = <92>;
- spi-max-frequency = <108000000>;
- status = "okay";
- qflash0: n25q128a {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "micron,n25q128a13", "jedec,spi-nor";
- spi-max-frequency = <108000000>;
- spi-tx-bus-width = <4>;
- spi-rx-bus-width = <4>;
- memory-map = <0x90000000 0x1000000>;
- reg = <0>;
- };
+qspi: spi@a0001000 {
+ compatible = "st,stm32f469-qspi";
+ reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>;
+ reg-names = "qspi", "qspi_mm";
+ interrupts = <91>;
+ resets = <&rcc STM32F4_AHB3_RESET(QSPI)>;
+ clocks = <&rcc 0 STM32F4_AHB3_CLOCK(QSPI)>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi0>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <108000000>;
+ ...
};
+};
diff --git a/doc/driver-model/MIGRATION.txt b/doc/driver-model/MIGRATION.txt
deleted file mode 100644
index d38be35..0000000
--- a/doc/driver-model/MIGRATION.txt
+++ /dev/null
@@ -1,101 +0,0 @@
-Migration Schedule
-====================
-
-U-Boot has been migrating to a new driver model since its introduction in
-2014. This file describes the schedule for deprecation of pre-driver-model
-features.
-
-CONFIG_DM_MMC
--------------
-
-Status: In progress
-Deadline: 2019.04
-
-The subsystem itself has been converted and maintainers should submit patches
-switching over to using CONFIG_DM_MMC and other base driver model options in
-time for inclusion in the 2019.04 rerelease.
-
-CONFIG_DM_USB
--------------
-
-Status: In progress
-Deadline: 2019.07
-
-The subsystem itself has been converted along with many of the host controller
-and maintainers should submit patches switching over to using CONFIG_DM_USB and
-other base driver model options in time for inclusion in the 2019.07 rerelease.
-
-CONFIG_SATA
------------
-
-Status: In progress
-Deadline: 2019.07
-
-The subsystem itself has been converted along with many of the host controller
-and maintainers should submit patches switching over to using CONFIG_AHCI and
-other base driver model options in time for inclusion in the 2019.07 rerelease.
-
-CONFIG_BLK
-----------
-
-Status: In progress
-Deadline: 2019.07
-
-In concert with maintainers migrating their block device usage to the
-appropriate DM driver, CONFIG_BLK needs to be set as well. The final deadline
-here coincides with the final deadline for migration of the various block
-subsystems. At this point we will be able to audit and correct the logic in
-Kconfig around using CONFIG_PARTITIONS and CONFIG_HAVE_BLOCK_DEVICE and make
-use of CONFIG_BLK / CONFIG_SPL_BLK as needed.
-
-CONFIG_DM_SPI
-CONFIG_DM_SPI_FLASH
--------------------
-
-Board Maintainers should submit the patches for enabling DM_SPI and DM_SPI_FLASH
-to move the migration with in the deadline.
-
-No dm conversion yet:
- drivers/spi/cf_spi.c
- drivers/spi/fsl_espi.c
- drivers/spi/lpc32xx_ssp.c
- drivers/spi/mxs_spi.c
- drivers/spi/sh_spi.c
- drivers/spi/soft_spi_legacy.c
-
- Status: In progress
- Deadline: 2019.04
-
-Partially converted:
- drivers/spi/davinci_spi.c
- drivers/spi/fsl_dspi.c
- drivers/spi/kirkwood_spi.c
- drivers/spi/mxc_spi.c
- drivers/spi/omap3_spi.c
- drivers/spi/sh_qspi.c
-
- Status: In progress
- Deadline: 2019.07
-
---
-Jagan Teki <jagan@openedev.com>
-12/24/2018
-03/14/2018
-
-
-CONFIG_DM_PCI
--------------
-Deadline: 2019.07
-
-The PCI subsystem has supported driver model since mid 2015. Maintainers should
-submit patches switching over to using CONFIG_DM_PCI and other base driver
-model options in time for inclusion in the 2019.07 release.
-
-
-CONFIG_DM_VIDEO
----------------
-Deadline: 2019.07
-
-The video subsystem has supported driver model since early 2016. Maintainers
-should submit patches switching over to using CONFIG_DM_VIDEO and other base
-driver model options in time for inclusion in the 2019.07 release.
diff --git a/doc/driver-model/README.txt b/doc/driver-model/README.txt
deleted file mode 100644
index 07b120d..0000000
--- a/doc/driver-model/README.txt
+++ /dev/null
@@ -1,910 +0,0 @@
-Driver Model
-============
-
-This README contains high-level information about driver model, a unified
-way of declaring and accessing drivers in U-Boot. The original work was done
-by:
-
- Marek Vasut <marex@denx.de>
- Pavel Herrmann <morpheus.ibis@gmail.com>
- Viktor KÅ™ivák <viktor.krivak@gmail.com>
- Tomas Hlavacek <tmshlvck@gmail.com>
-
-This has been both simplified and extended into the current implementation
-by:
-
- Simon Glass <sjg@chromium.org>
-
-
-Terminology
------------
-
-Uclass - a group of devices which operate in the same way. A uclass provides
- a way of accessing individual devices within the group, but always
- using the same interface. For example a GPIO uclass provides
- operations for get/set value. An I2C uclass may have 10 I2C ports,
- 4 with one driver, and 6 with another.
-
-Driver - some code which talks to a peripheral and presents a higher-level
- interface to it.
-
-Device - an instance of a driver, tied to a particular port or peripheral.
-
-
-How to try it
--------------
-
-Build U-Boot sandbox and run it:
-
- make sandbox_defconfig
- make
- ./u-boot -d u-boot.dtb
-
- (type 'reset' to exit U-Boot)
-
-
-There is a uclass called 'demo'. This uclass handles
-saying hello, and reporting its status. There are two drivers in this
-uclass:
-
- - simple: Just prints a message for hello, doesn't implement status
- - shape: Prints shapes and reports number of characters printed as status
-
-The demo class is pretty simple, but not trivial. The intention is that it
-can be used for testing, so it will implement all driver model features and
-provide good code coverage of them. It does have multiple drivers, it
-handles parameter data and platdata (data which tells the driver how
-to operate on a particular platform) and it uses private driver data.
-
-To try it, see the example session below:
-
-=>demo hello 1
-Hello '@' from 07981110: red 4
-=>demo status 2
-Status: 0
-=>demo hello 2
-g
-r@
-e@@
-e@@@
-n@@@@
-g@@@@@
-=>demo status 2
-Status: 21
-=>demo hello 4 ^
- y^^^
- e^^^^^
-l^^^^^^^
-l^^^^^^^
- o^^^^^
- w^^^
-=>demo status 4
-Status: 36
-=>
-
-
-Running the tests
------------------
-
-The intent with driver model is that the core portion has 100% test coverage
-in sandbox, and every uclass has its own test. As a move towards this, tests
-are provided in test/dm. To run them, try:
-
- ./test/py/test.py --bd sandbox --build -k ut_dm -v
-
-You should see something like this:
-
-(venv)$ ./test/py/test.py --bd sandbox --build -k ut_dm -v
-+make O=/root/u-boot/build-sandbox -s sandbox_defconfig
-+make O=/root/u-boot/build-sandbox -s -j8
-============================= test session starts ==============================
-platform linux2 -- Python 2.7.5, pytest-2.9.0, py-1.4.31, pluggy-0.3.1 -- /root/u-boot/venv/bin/python
-cachedir: .cache
-rootdir: /root/u-boot, inifile:
-collected 199 items
-
-test/py/tests/test_ut.py::test_ut_dm_init PASSED
-test/py/tests/test_ut.py::test_ut[ut_dm_adc_bind] PASSED
-test/py/tests/test_ut.py::test_ut[ut_dm_adc_multi_channel_conversion] PASSED
-test/py/tests/test_ut.py::test_ut[ut_dm_adc_multi_channel_shot] PASSED
-test/py/tests/test_ut.py::test_ut[ut_dm_adc_single_channel_conversion] PASSED
-test/py/tests/test_ut.py::test_ut[ut_dm_adc_single_channel_shot] PASSED
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-test/py/tests/test_ut.py::test_ut[ut_dm_autobind] PASSED
-test/py/tests/test_ut.py::test_ut[ut_dm_autobind_uclass_pdata_alloc] PASSED
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-test/py/tests/test_ut.py::test_ut[ut_dm_autoprobe] PASSED
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-test/py/tests/test_ut.py::test_ut[ut_dm_bus_child_pre_probe_uclass] PASSED
-test/py/tests/test_ut.py::test_ut[ut_dm_bus_children] PASSED
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-test/py/tests/test_ut.py::test_ut[ut_dm_bus_parent_data] PASSED
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-test/py/tests/test_ut.py::test_ut[ut_dm_bus_parent_platdata] PASSED
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-test/py/tests/test_ut.py::test_ut[ut_dm_children] PASSED
-test/py/tests/test_ut.py::test_ut[ut_dm_clk_base] PASSED
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-test/py/tests/test_ut.py::test_ut[ut_dm_device_get_uclass_id] PASSED
-test/py/tests/test_ut.py::test_ut[ut_dm_eth] PASSED
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-test/py/tests/test_ut.py::test_ut[ut_dm_led_gpio] PASSED
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-test/py/tests/test_ut.py::test_ut[ut_dm_power_regulator_set_get_voltage] PASSED
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-test/py/tests/test_ut.py::test_ut[ut_dm_ram_base] PASSED
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-test/py/tests/test_ut.py::test_ut[ut_dm_usb_remove] PASSED
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-
-======================= 84 tests deselected by '-kut_dm' =======================
-================== 115 passed, 84 deselected in 3.77 seconds ===================
-
-What is going on?
------------------
-
-Let's start at the top. The demo command is in common/cmd_demo.c. It does
-the usual command processing and then:
-
- struct udevice *demo_dev;
-
- ret = uclass_get_device(UCLASS_DEMO, devnum, &demo_dev);
-
-UCLASS_DEMO means the class of devices which implement 'demo'. Other
-classes might be MMC, or GPIO, hashing or serial. The idea is that the
-devices in the class all share a particular way of working. The class
-presents a unified view of all these devices to U-Boot.
-
-This function looks up a device for the demo uclass. Given a device
-number we can find the device because all devices have registered with
-the UCLASS_DEMO uclass.
-
-The device is automatically activated ready for use by uclass_get_device().
-
-Now that we have the device we can do things like:
-
- return demo_hello(demo_dev, ch);
-
-This function is in the demo uclass. It takes care of calling the 'hello'
-method of the relevant driver. Bearing in mind that there are two drivers,
-this particular device may use one or other of them.
-
-The code for demo_hello() is in drivers/demo/demo-uclass.c:
-
-int demo_hello(struct udevice *dev, int ch)
-{
- const struct demo_ops *ops = device_get_ops(dev);
-
- if (!ops->hello)
- return -ENOSYS;
-
- return ops->hello(dev, ch);
-}
-
-As you can see it just calls the relevant driver method. One of these is
-in drivers/demo/demo-simple.c:
-
-static int simple_hello(struct udevice *dev, int ch)
-{
- const struct dm_demo_pdata *pdata = dev_get_platdata(dev);
-
- printf("Hello from %08x: %s %d\n", map_to_sysmem(dev),
- pdata->colour, pdata->sides);
-
- return 0;
-}
-
-
-So that is a trip from top (command execution) to bottom (driver action)
-but it leaves a lot of topics to address.
-
-
-Declaring Drivers
------------------
-
-A driver declaration looks something like this (see
-drivers/demo/demo-shape.c):
-
-static const struct demo_ops shape_ops = {
- .hello = shape_hello,
- .status = shape_status,
-};
-
-U_BOOT_DRIVER(demo_shape_drv) = {
- .name = "demo_shape_drv",
- .id = UCLASS_DEMO,
- .ops = &shape_ops,
- .priv_data_size = sizeof(struct shape_data),
-};
-
-
-This driver has two methods (hello and status) and requires a bit of
-private data (accessible through dev_get_priv(dev) once the driver has
-been probed). It is a member of UCLASS_DEMO so will register itself
-there.
-
-In U_BOOT_DRIVER it is also possible to specify special methods for bind
-and unbind, and these are called at appropriate times. For many drivers
-it is hoped that only 'probe' and 'remove' will be needed.
-
-The U_BOOT_DRIVER macro creates a data structure accessible from C,
-so driver model can find the drivers that are available.
-
-The methods a device can provide are documented in the device.h header.
-Briefly, they are:
-
- bind - make the driver model aware of a device (bind it to its driver)
- unbind - make the driver model forget the device
- ofdata_to_platdata - convert device tree data to platdata - see later
- probe - make a device ready for use
- remove - remove a device so it cannot be used until probed again
-
-The sequence to get a device to work is bind, ofdata_to_platdata (if using
-device tree) and probe.
-
-
-Platform Data
--------------
-
-*** Note: platform data is the old way of doing things. It is
-*** basically a C structure which is passed to drivers to tell them about
-*** platform-specific settings like the address of its registers, bus
-*** speed, etc. Device tree is now the preferred way of handling this.
-*** Unless you have a good reason not to use device tree (the main one
-*** being you need serial support in SPL and don't have enough SRAM for
-*** the cut-down device tree and libfdt libraries) you should stay away
-*** from platform data.
-
-Platform data is like Linux platform data, if you are familiar with that.
-It provides the board-specific information to start up a device.
-
-Why is this information not just stored in the device driver itself? The
-idea is that the device driver is generic, and can in principle operate on
-any board that has that type of device. For example, with modern
-highly-complex SoCs it is common for the IP to come from an IP vendor, and
-therefore (for example) the MMC controller may be the same on chips from
-different vendors. It makes no sense to write independent drivers for the
-MMC controller on each vendor's SoC, when they are all almost the same.
-Similarly, we may have 6 UARTs in an SoC, all of which are mostly the same,
-but lie at different addresses in the address space.
-
-Using the UART example, we have a single driver and it is instantiated 6
-times by supplying 6 lots of platform data. Each lot of platform data
-gives the driver name and a pointer to a structure containing information
-about this instance - e.g. the address of the register space. It may be that
-one of the UARTS supports RS-485 operation - this can be added as a flag in
-the platform data, which is set for this one port and clear for the rest.
-
-Think of your driver as a generic piece of code which knows how to talk to
-a device, but needs to know where it is, any variant/option information and
-so on. Platform data provides this link between the generic piece of code
-and the specific way it is bound on a particular board.
-
-Examples of platform data include:
-
- - The base address of the IP block's register space
- - Configuration options, like:
- - the SPI polarity and maximum speed for a SPI controller
- - the I2C speed to use for an I2C device
- - the number of GPIOs available in a GPIO device
-
-Where does the platform data come from? It is either held in a structure
-which is compiled into U-Boot, or it can be parsed from the Device Tree
-(see 'Device Tree' below).
-
-For an example of how it can be compiled in, see demo-pdata.c which
-sets up a table of driver names and their associated platform data.
-The data can be interpreted by the drivers however they like - it is
-basically a communication scheme between the board-specific code and
-the generic drivers, which are intended to work on any board.
-
-Drivers can access their data via dev->info->platdata. Here is
-the declaration for the platform data, which would normally appear
-in the board file.
-
- static const struct dm_demo_cdata red_square = {
- .colour = "red",
- .sides = 4.
- };
- static const struct driver_info info[] = {
- {
- .name = "demo_shape_drv",
- .platdata = &red_square,
- },
- };
-
- demo1 = driver_bind(root, &info[0]);
-
-
-Device Tree
------------
-
-While platdata is useful, a more flexible way of providing device data is
-by using device tree. In U-Boot you should use this where possible. Avoid
-sending patches which make use of the U_BOOT_DEVICE() macro unless strictly
-necessary.
-
-With device tree we replace the above code with the following device tree
-fragment:
-
- red-square {
- compatible = "demo-shape";
- colour = "red";
- sides = <4>;
- };
-
-This means that instead of having lots of U_BOOT_DEVICE() declarations in
-the board file, we put these in the device tree. This approach allows a lot
-more generality, since the same board file can support many types of boards
-(e,g. with the same SoC) just by using different device trees. An added
-benefit is that the Linux device tree can be used, thus further simplifying
-the task of board-bring up either for U-Boot or Linux devs (whoever gets to
-the board first!).
-
-The easiest way to make this work it to add a few members to the driver:
-
- .platdata_auto_alloc_size = sizeof(struct dm_test_pdata),
- .ofdata_to_platdata = testfdt_ofdata_to_platdata,
-
-The 'auto_alloc' feature allowed space for the platdata to be allocated
-and zeroed before the driver's ofdata_to_platdata() method is called. The
-ofdata_to_platdata() method, which the driver write supplies, should parse
-the device tree node for this device and place it in dev->platdata. Thus
-when the probe method is called later (to set up the device ready for use)
-the platform data will be present.
-
-Note that both methods are optional. If you provide an ofdata_to_platdata
-method then it will be called first (during activation). If you provide a
-probe method it will be called next. See Driver Lifecycle below for more
-details.
-
-If you don't want to have the platdata automatically allocated then you
-can leave out platdata_auto_alloc_size. In this case you can use malloc
-in your ofdata_to_platdata (or probe) method to allocate the required memory,
-and you should free it in the remove method.
-
-The driver model tree is intended to mirror that of the device tree. The
-root driver is at device tree offset 0 (the root node, '/'), and its
-children are the children of the root node.
-
-In order for a device tree to be valid, the content must be correct with
-respect to either device tree specification
-(https://www.devicetree.org/specifications/) or the device tree bindings that
-are found in the doc/device-tree-bindings directory. When not U-Boot specific
-the bindings in this directory tend to come from the Linux Kernel. As such
-certain design decisions may have been made already for us in terms of how
-specific devices are described and bound. In most circumstances we wish to
-retain compatibility without additional changes being made to the device tree
-source files.
-
-Declaring Uclasses
-------------------
-
-The demo uclass is declared like this:
-
-U_BOOT_CLASS(demo) = {
- .id = UCLASS_DEMO,
-};
-
-It is also possible to specify special methods for probe, etc. The uclass
-numbering comes from include/dm/uclass.h. To add a new uclass, add to the
-end of the enum there, then declare your uclass as above.
-
-
-Device Sequence Numbers
------------------------
-
-U-Boot numbers devices from 0 in many situations, such as in the command
-line for I2C and SPI buses, and the device names for serial ports (serial0,
-serial1, ...). Driver model supports this numbering and permits devices
-to be locating by their 'sequence'. This numbering uniquely identifies a
-device in its uclass, so no two devices within a particular uclass can have
-the same sequence number.
-
-Sequence numbers start from 0 but gaps are permitted. For example, a board
-may have I2C buses 1, 4, 5 but no 0, 2 or 3. The choice of how devices are
-numbered is up to a particular board, and may be set by the SoC in some
-cases. While it might be tempting to automatically renumber the devices
-where there are gaps in the sequence, this can lead to confusion and is
-not the way that U-Boot works.
-
-Each device can request a sequence number. If none is required then the
-device will be automatically allocated the next available sequence number.
-
-To specify the sequence number in the device tree an alias is typically
-used. Make sure that the uclass has the DM_UC_FLAG_SEQ_ALIAS flag set.
-
-aliases {
- serial2 = "/serial@22230000";
-};
-
-This indicates that in the uclass called "serial", the named node
-("/serial@22230000") will be given sequence number 2. Any command or driver
-which requests serial device 2 will obtain this device.
-
-More commonly you can use node references, which expand to the full path:
-
-aliases {
- serial2 = &serial_2;
-};
-...
-serial_2: serial@22230000 {
-...
-};
-
-The alias resolves to the same string in this case, but this version is
-easier to read.
-
-Device sequence numbers are resolved when a device is probed. Before then
-the sequence number is only a request which may or may not be honoured,
-depending on what other devices have been probed. However the numbering is
-entirely under the control of the board author so a conflict is generally
-an error.
-
-
-Bus Drivers
------------
-
-A common use of driver model is to implement a bus, a device which provides
-access to other devices. Example of buses include SPI and I2C. Typically
-the bus provides some sort of transport or translation that makes it
-possible to talk to the devices on the bus.
-
-Driver model provides some useful features to help with implementing buses.
-Firstly, a bus can request that its children store some 'parent data' which
-can be used to keep track of child state. Secondly, the bus can define
-methods which are called when a child is probed or removed. This is similar
-to the methods the uclass driver provides. Thirdly, per-child platform data
-can be provided to specify things like the child's address on the bus. This
-persists across child probe()/remove() cycles.
-
-For consistency and ease of implementation, the bus uclass can specify the
-per-child platform data, so that it can be the same for all children of buses
-in that uclass. There are also uclass methods which can be called when
-children are bound and probed.
-
-Here an explanation of how a bus fits with a uclass may be useful. Consider
-a USB bus with several devices attached to it, each from a different (made
-up) uclass:
-
- xhci_usb (UCLASS_USB)
- eth (UCLASS_ETHERNET)
- camera (UCLASS_CAMERA)
- flash (UCLASS_FLASH_STORAGE)
-
-Each of the devices is connected to a different address on the USB bus.
-The bus device wants to store this address and some other information such
-as the bus speed for each device.
-
-To achieve this, the bus device can use dev->parent_platdata in each of its
-three children. This can be auto-allocated if the bus driver (or bus uclass)
-has a non-zero value for per_child_platdata_auto_alloc_size. If not, then
-the bus device or uclass can allocate the space itself before the child
-device is probed.
-
-Also the bus driver can define the child_pre_probe() and child_post_remove()
-methods to allow it to do some processing before the child is activated or
-after it is deactivated.
-
-Similarly the bus uclass can define the child_post_bind() method to obtain
-the per-child platform data from the device tree and set it up for the child.
-The bus uclass can also provide a child_pre_probe() method. Very often it is
-the bus uclass that controls these features, since it avoids each driver
-having to do the same processing. Of course the driver can still tweak and
-override these activities.
-
-Note that the information that controls this behaviour is in the bus's
-driver, not the child's. In fact it is possible that child has no knowledge
-that it is connected to a bus. The same child device may even be used on two
-different bus types. As an example. the 'flash' device shown above may also
-be connected on a SATA bus or standalone with no bus:
-
- xhci_usb (UCLASS_USB)
- flash (UCLASS_FLASH_STORAGE) - parent data/methods defined by USB bus
-
- sata (UCLASS_SATA)
- flash (UCLASS_FLASH_STORAGE) - parent data/methods defined by SATA bus
-
- flash (UCLASS_FLASH_STORAGE) - no parent data/methods (not on a bus)
-
-Above you can see that the driver for xhci_usb/sata controls the child's
-bus methods. In the third example the device is not on a bus, and therefore
-will not have these methods at all. Consider the case where the flash
-device defines child methods. These would be used for *its* children, and
-would be quite separate from the methods defined by the driver for the bus
-that the flash device is connetced to. The act of attaching a device to a
-parent device which is a bus, causes the device to start behaving like a
-bus device, regardless of its own views on the matter.
-
-The uclass for the device can also contain data private to that uclass.
-But note that each device on the bus may be a memeber of a different
-uclass, and this data has nothing to do with the child data for each child
-on the bus. It is the bus' uclass that controls the child with respect to
-the bus.
-
-
-Driver Lifecycle
-----------------
-
-Here are the stages that a device goes through in driver model. Note that all
-methods mentioned here are optional - e.g. if there is no probe() method for
-a device then it will not be called. A simple device may have very few
-methods actually defined.
-
-1. Bind stage
-
-U-Boot discovers devices using one of these two methods:
-
- - Scan the U_BOOT_DEVICE() definitions. U-Boot looks up the name specified
-by each, to find the appropriate U_BOOT_DRIVER() definition. In this case,
-there is no path by which driver_data may be provided, but the U_BOOT_DEVICE()
-may provide platdata.
-
- - Scan through the device tree definitions. U-Boot looks at top-level
-nodes in the the device tree. It looks at the compatible string in each node
-and uses the of_match table of the U_BOOT_DRIVER() structure to find the
-right driver for each node. In this case, the of_match table may provide a
-driver_data value, but platdata cannot be provided until later.
-
-For each device that is discovered, U-Boot then calls device_bind() to create a
-new device, initializes various core fields of the device object such as name,
-uclass & driver, initializes any optional fields of the device object that are
-applicable such as of_offset, driver_data & platdata, and finally calls the
-driver's bind() method if one is defined.
-
-At this point all the devices are known, and bound to their drivers. There
-is a 'struct udevice' allocated for all devices. However, nothing has been
-activated (except for the root device). Each bound device that was created
-from a U_BOOT_DEVICE() declaration will hold the platdata pointer specified
-in that declaration. For a bound device created from the device tree,
-platdata will be NULL, but of_offset will be the offset of the device tree
-node that caused the device to be created. The uclass is set correctly for
-the device.
-
-The device's bind() method is permitted to perform simple actions, but
-should not scan the device tree node, not initialise hardware, nor set up
-structures or allocate memory. All of these tasks should be left for
-the probe() method.
-
-Note that compared to Linux, U-Boot's driver model has a separate step of
-probe/remove which is independent of bind/unbind. This is partly because in
-U-Boot it may be expensive to probe devices and we don't want to do it until
-they are needed, or perhaps until after relocation.
-
-2. Activation/probe
-
-When a device needs to be used, U-Boot activates it, by following these
-steps (see device_probe()):
-
- a. If priv_auto_alloc_size is non-zero, then the device-private space
- is allocated for the device and zeroed. It will be accessible as
- dev->priv. The driver can put anything it likes in there, but should use
- it for run-time information, not platform data (which should be static
- and known before the device is probed).
-
- b. If platdata_auto_alloc_size is non-zero, then the platform data space
- is allocated. This is only useful for device tree operation, since
- otherwise you would have to specific the platform data in the
- U_BOOT_DEVICE() declaration. The space is allocated for the device and
- zeroed. It will be accessible as dev->platdata.
-
- c. If the device's uclass specifies a non-zero per_device_auto_alloc_size,
- then this space is allocated and zeroed also. It is allocated for and
- stored in the device, but it is uclass data. owned by the uclass driver.
- It is possible for the device to access it.
-
- d. If the device's immediate parent specifies a per_child_auto_alloc_size
- then this space is allocated. This is intended for use by the parent
- device to keep track of things related to the child. For example a USB
- flash stick attached to a USB host controller would likely use this
- space. The controller can hold information about the USB state of each
- of its children.
-
- e. All parent devices are probed. It is not possible to activate a device
- unless its predecessors (all the way up to the root device) are activated.
- This means (for example) that an I2C driver will require that its bus
- be activated.
-
- f. The device's sequence number is assigned, either the requested one
- (assuming no conflicts) or the next available one if there is a conflict
- or nothing particular is requested.
-
- g. If the driver provides an ofdata_to_platdata() method, then this is
- called to convert the device tree data into platform data. This should
- do various calls like fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), ...)
- to access the node and store the resulting information into dev->platdata.
- After this point, the device works the same way whether it was bound
- using a device tree node or U_BOOT_DEVICE() structure. In either case,
- the platform data is now stored in the platdata structure. Typically you
- will use the platdata_auto_alloc_size feature to specify the size of the
- platform data structure, and U-Boot will automatically allocate and zero
- it for you before entry to ofdata_to_platdata(). But if not, you can
- allocate it yourself in ofdata_to_platdata(). Note that it is preferable
- to do all the device tree decoding in ofdata_to_platdata() rather than
- in probe(). (Apart from the ugliness of mixing configuration and run-time
- data, one day it is possible that U-Boot will cache platform data for
- devices which are regularly de/activated).
-
- h. The device's probe() method is called. This should do anything that
- is required by the device to get it going. This could include checking
- that the hardware is actually present, setting up clocks for the
- hardware and setting up hardware registers to initial values. The code
- in probe() can access:
-
- - platform data in dev->platdata (for configuration)
- - private data in dev->priv (for run-time state)
- - uclass data in dev->uclass_priv (for things the uclass stores
- about this device)
-
- Note: If you don't use priv_auto_alloc_size then you will need to
- allocate the priv space here yourself. The same applies also to
- platdata_auto_alloc_size. Remember to free them in the remove() method.
-
- i. The device is marked 'activated'
-
- j. The uclass's post_probe() method is called, if one exists. This may
- cause the uclass to do some housekeeping to record the device as
- activated and 'known' by the uclass.
-
-3. Running stage
-
-The device is now activated and can be used. From now until it is removed
-all of the above structures are accessible. The device appears in the
-uclass's list of devices (so if the device is in UCLASS_GPIO it will appear
-as a device in the GPIO uclass). This is the 'running' state of the device.
-
-4. Removal stage
-
-When the device is no-longer required, you can call device_remove() to
-remove it. This performs the probe steps in reverse:
-
- a. The uclass's pre_remove() method is called, if one exists. This may
- cause the uclass to do some housekeeping to record the device as
- deactivated and no-longer 'known' by the uclass.
-
- b. All the device's children are removed. It is not permitted to have
- an active child device with a non-active parent. This means that
- device_remove() is called for all the children recursively at this point.
-
- c. The device's remove() method is called. At this stage nothing has been
- deallocated so platform data, private data and the uclass data will all
- still be present. This is where the hardware can be shut down. It is
- intended that the device be completely inactive at this point, For U-Boot
- to be sure that no hardware is running, it should be enough to remove
- all devices.
-
- d. The device memory is freed (platform data, private data, uclass data,
- parent data).
-
- Note: Because the platform data for a U_BOOT_DEVICE() is defined with a
- static pointer, it is not de-allocated during the remove() method. For
- a device instantiated using the device tree data, the platform data will
- be dynamically allocated, and thus needs to be deallocated during the
- remove() method, either:
-
- 1. if the platdata_auto_alloc_size is non-zero, the deallocation
- happens automatically within the driver model core; or
-
- 2. when platdata_auto_alloc_size is 0, both the allocation (in probe()
- or preferably ofdata_to_platdata()) and the deallocation in remove()
- are the responsibility of the driver author.
-
- e. The device sequence number is set to -1, meaning that it no longer
- has an allocated sequence. If the device is later reactivated and that
- sequence number is still free, it may well receive the name sequence
- number again. But from this point, the sequence number previously used
- by this device will no longer exist (think of SPI bus 2 being removed
- and bus 2 is no longer available for use).
-
- f. The device is marked inactive. Note that it is still bound, so the
- device structure itself is not freed at this point. Should the device be
- activated again, then the cycle starts again at step 2 above.
-
-5. Unbind stage
-
-The device is unbound. This is the step that actually destroys the device.
-If a parent has children these will be destroyed first. After this point
-the device does not exist and its memory has be deallocated.
-
-
-Data Structures
----------------
-
-Driver model uses a doubly-linked list as the basic data structure. Some
-nodes have several lists running through them. Creating a more efficient
-data structure might be worthwhile in some rare cases, once we understand
-what the bottlenecks are.
-
-
-Changes since v1
-----------------
-
-For the record, this implementation uses a very similar approach to the
-original patches, but makes at least the following changes:
-
-- Tried to aggressively remove boilerplate, so that for most drivers there
-is little or no 'driver model' code to write.
-- Moved some data from code into data structure - e.g. store a pointer to
-the driver operations structure in the driver, rather than passing it
-to the driver bind function.
-- Rename some structures to make them more similar to Linux (struct udevice
-instead of struct instance, struct platdata, etc.)
-- Change the name 'core' to 'uclass', meaning U-Boot class. It seems that
-this concept relates to a class of drivers (or a subsystem). We shouldn't
-use 'class' since it is a C++ reserved word, so U-Boot class (uclass) seems
-better than 'core'.
-- Remove 'struct driver_instance' and just use a single 'struct udevice'.
-This removes a level of indirection that doesn't seem necessary.
-- Built in device tree support, to avoid the need for platdata
-- Removed the concept of driver relocation, and just make it possible for
-the new driver (created after relocation) to access the old driver data.
-I feel that relocation is a very special case and will only apply to a few
-drivers, many of which can/will just re-init anyway. So the overhead of
-dealing with this might not be worth it.
-- Implemented a GPIO system, trying to keep it simple
-
-
-Pre-Relocation Support
-----------------------
-
-For pre-relocation we simply call the driver model init function. Only
-drivers marked with DM_FLAG_PRE_RELOC or the device tree 'u-boot,dm-pre-reloc'
-property are initialised prior to relocation. This helps to reduce the driver
-model overhead. This flag applies to SPL and TPL as well, if device tree is
-enabled (CONFIG_OF_CONTROL) there.
-
-Note when device tree is enabled, the device tree 'u-boot,dm-pre-reloc'
-property can provide better control granularity on which device is bound
-before relocation. While with DM_FLAG_PRE_RELOC flag of the driver all
-devices with the same driver are bound, which requires allocation a large
-amount of memory. When device tree is not used, DM_FLAG_PRE_RELOC is the
-only way for statically declared devices via U_BOOT_DEVICE() to be bound
-prior to relocation.
-
-It is possible to limit this to specific relocation steps, by using
-the more specialized 'u-boot,dm-spl' and 'u-boot,dm-tpl' flags
-in the device tree node. For U-Boot proper you can use 'u-boot,dm-pre-proper'
-which means that it will be processed (and a driver bound) in U-Boot proper
-prior to relocation, but will not be available in SPL or TPL.
-
-Then post relocation we throw that away and re-init driver model again.
-For drivers which require some sort of continuity between pre- and
-post-relocation devices, we can provide access to the pre-relocation
-device pointers, but this is not currently implemented (the root device
-pointer is saved but not made available through the driver model API).
-
-
-SPL Support
------------
-
-Driver model can operate in SPL. Its efficient implementation and small code
-size provide for a small overhead which is acceptable for all but the most
-constrained systems.
-
-To enable driver model in SPL, define CONFIG_SPL_DM. You might want to
-consider the following option also. See the main README for more details.
-
- - CONFIG_SYS_MALLOC_SIMPLE
- - CONFIG_DM_WARN
- - CONFIG_DM_DEVICE_REMOVE
- - CONFIG_DM_STDIO
-
-
-Enabling Driver Model
----------------------
-
-Driver model is being brought into U-Boot gradually. As each subsystems gets
-support, a uclass is created and a CONFIG to enable use of driver model for
-that subsystem.
-
-For example CONFIG_DM_SERIAL enables driver model for serial. With that
-defined, the old serial support is not enabled, and your serial driver must
-conform to driver model. With that undefined, the old serial support is
-enabled and driver model is not available for serial. This means that when
-you convert a driver, you must either convert all its boards, or provide for
-the driver to be compiled both with and without driver model (generally this
-is not very hard).
-
-See the main README for full details of the available driver model CONFIG
-options.
-
-
-Things to punt for later
-------------------------
-
-Uclasses are statically numbered at compile time. It would be possible to
-change this to dynamic numbering, but then we would require some sort of
-lookup service, perhaps searching by name. This is slightly less efficient
-so has been left out for now. One small advantage of dynamic numbering might
-be fewer merge conflicts in uclass-id.h.
-
-
-Simon Glass
-sjg@chromium.org
-April 2013
-Updated 7-May-13
-Updated 14-Jun-13
-Updated 18-Oct-13
-Updated 5-Nov-13
diff --git a/doc/driver-model/design.rst b/doc/driver-model/design.rst
new file mode 100644
index 0000000..8fd28c0
--- /dev/null
+++ b/doc/driver-model/design.rst
@@ -0,0 +1,939 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Simon Glass <sjg@chromium.org>
+
+Design Details
+==============
+
+This README contains high-level information about driver model, a unified
+way of declaring and accessing drivers in U-Boot. The original work was done
+by:
+
+ * Marek Vasut <marex@denx.de>
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ * Viktor KÅ™ivák <viktor.krivak@gmail.com>
+ * Tomas Hlavacek <tmshlvck@gmail.com>
+
+This has been both simplified and extended into the current implementation
+by:
+
+ * Simon Glass <sjg@chromium.org>
+
+
+Terminology
+-----------
+
+Uclass
+ a group of devices which operate in the same way. A uclass provides
+ a way of accessing individual devices within the group, but always
+ using the same interface. For example a GPIO uclass provides
+ operations for get/set value. An I2C uclass may have 10 I2C ports,
+ 4 with one driver, and 6 with another.
+
+Driver
+ some code which talks to a peripheral and presents a higher-level
+ interface to it.
+
+Device
+ an instance of a driver, tied to a particular port or peripheral.
+
+
+How to try it
+-------------
+
+Build U-Boot sandbox and run it::
+
+ make sandbox_defconfig
+ make
+ ./u-boot -d u-boot.dtb
+
+ (type 'reset' to exit U-Boot)
+
+
+There is a uclass called 'demo'. This uclass handles
+saying hello, and reporting its status. There are two drivers in this
+uclass:
+
+ - simple: Just prints a message for hello, doesn't implement status
+ - shape: Prints shapes and reports number of characters printed as status
+
+The demo class is pretty simple, but not trivial. The intention is that it
+can be used for testing, so it will implement all driver model features and
+provide good code coverage of them. It does have multiple drivers, it
+handles parameter data and platdata (data which tells the driver how
+to operate on a particular platform) and it uses private driver data.
+
+To try it, see the example session below::
+
+ =>demo hello 1
+ Hello '@' from 07981110: red 4
+ =>demo status 2
+ Status: 0
+ =>demo hello 2
+ g
+ r@
+ e@@
+ e@@@
+ n@@@@
+ g@@@@@
+ =>demo status 2
+ Status: 21
+ =>demo hello 4 ^
+ y^^^
+ e^^^^^
+ l^^^^^^^
+ l^^^^^^^
+ o^^^^^
+ w^^^
+ =>demo status 4
+ Status: 36
+ =>
+
+
+Running the tests
+-----------------
+
+The intent with driver model is that the core portion has 100% test coverage
+in sandbox, and every uclass has its own test. As a move towards this, tests
+are provided in test/dm. To run them, try::
+
+ ./test/py/test.py --bd sandbox --build -k ut_dm -v
+
+You should see something like this::
+
+ (venv)$ ./test/py/test.py --bd sandbox --build -k ut_dm -v
+ +make O=/root/u-boot/build-sandbox -s sandbox_defconfig
+ +make O=/root/u-boot/build-sandbox -s -j8
+ ============================= test session starts ==============================
+ platform linux2 -- Python 2.7.5, pytest-2.9.0, py-1.4.31, pluggy-0.3.1 -- /root/u-boot/venv/bin/python
+ cachedir: .cache
+ rootdir: /root/u-boot, inifile:
+ collected 199 items
+
+ test/py/tests/test_ut.py::test_ut_dm_init PASSED
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+ test/py/tests/test_ut.py::test_ut[ut_dm_adc_multi_channel_conversion] PASSED
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+ test/py/tests/test_ut.py::test_ut[ut_dm_adc_single_channel_conversion] PASSED
+ test/py/tests/test_ut.py::test_ut[ut_dm_adc_single_channel_shot] PASSED
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+ test/py/tests/test_ut.py::test_ut[ut_dm_autobind] PASSED
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+ test/py/tests/test_ut.py::test_ut[ut_dm_bus_parent_platdata_uclass] PASSED
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+ test/py/tests/test_ut.py::test_ut[ut_dm_clk_periph] PASSED
+ test/py/tests/test_ut.py::test_ut[ut_dm_device_get_uclass_id] PASSED
+ test/py/tests/test_ut.py::test_ut[ut_dm_eth] PASSED
+ test/py/tests/test_ut.py::test_ut[ut_dm_eth_act] PASSED
+ test/py/tests/test_ut.py::test_ut[ut_dm_eth_alias] PASSED
+ test/py/tests/test_ut.py::test_ut[ut_dm_eth_prime] PASSED
+ test/py/tests/test_ut.py::test_ut[ut_dm_eth_rotate] PASSED
+ test/py/tests/test_ut.py::test_ut[ut_dm_fdt] PASSED
+ test/py/tests/test_ut.py::test_ut[ut_dm_fdt_offset] PASSED
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+ test/py/tests/test_ut.py::test_ut[ut_dm_gpio] PASSED
+ test/py/tests/test_ut.py::test_ut[ut_dm_gpio_anon] PASSED
+ test/py/tests/test_ut.py::test_ut[ut_dm_gpio_copy] PASSED
+ test/py/tests/test_ut.py::test_ut[ut_dm_gpio_leak] PASSED
+ test/py/tests/test_ut.py::test_ut[ut_dm_gpio_phandles] PASSED
+ test/py/tests/test_ut.py::test_ut[ut_dm_gpio_requestf] PASSED
+ test/py/tests/test_ut.py::test_ut[ut_dm_i2c_bytewise] PASSED
+ test/py/tests/test_ut.py::test_ut[ut_dm_i2c_find] PASSED
+ test/py/tests/test_ut.py::test_ut[ut_dm_i2c_offset] PASSED
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+ test/py/tests/test_ut.py::test_ut[ut_dm_power_pmic_get] PASSED
+ test/py/tests/test_ut.py::test_ut[ut_dm_power_pmic_io] PASSED
+ test/py/tests/test_ut.py::test_ut[ut_dm_power_regulator_autoset] PASSED
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+ test/py/tests/test_ut.py::test_ut[ut_dm_spi_xfer] PASSED
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+ test/py/tests/test_ut.py::test_ut[ut_dm_uclass_devices_get_by_name] PASSED
+ test/py/tests/test_ut.py::test_ut[ut_dm_usb_base] PASSED
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+ test/py/tests/test_ut.py::test_ut[ut_dm_usb_tree] PASSED
+ test/py/tests/test_ut.py::test_ut[ut_dm_usb_tree_remove] PASSED
+ test/py/tests/test_ut.py::test_ut[ut_dm_usb_tree_reorder] PASSED
+ test/py/tests/test_ut.py::test_ut[ut_dm_video_base] PASSED
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+ test/py/tests/test_ut.py::test_ut[ut_dm_video_bmp_comp] PASSED
+ test/py/tests/test_ut.py::test_ut[ut_dm_video_chars] PASSED
+ test/py/tests/test_ut.py::test_ut[ut_dm_video_context] PASSED
+ test/py/tests/test_ut.py::test_ut[ut_dm_video_rotation1] PASSED
+ test/py/tests/test_ut.py::test_ut[ut_dm_video_rotation2] PASSED
+ test/py/tests/test_ut.py::test_ut[ut_dm_video_rotation3] PASSED
+ test/py/tests/test_ut.py::test_ut[ut_dm_video_text] PASSED
+ test/py/tests/test_ut.py::test_ut[ut_dm_video_truetype] PASSED
+ test/py/tests/test_ut.py::test_ut[ut_dm_video_truetype_bs] PASSED
+ test/py/tests/test_ut.py::test_ut[ut_dm_video_truetype_scroll] PASSED
+
+ ======================= 84 tests deselected by '-kut_dm' =======================
+ ================== 115 passed, 84 deselected in 3.77 seconds ===================
+
+What is going on?
+-----------------
+
+Let's start at the top. The demo command is in common/cmd_demo.c. It does
+the usual command processing and then:
+
+.. code-block:: c
+
+ struct udevice *demo_dev;
+
+ ret = uclass_get_device(UCLASS_DEMO, devnum, &demo_dev);
+
+UCLASS_DEMO means the class of devices which implement 'demo'. Other
+classes might be MMC, or GPIO, hashing or serial. The idea is that the
+devices in the class all share a particular way of working. The class
+presents a unified view of all these devices to U-Boot.
+
+This function looks up a device for the demo uclass. Given a device
+number we can find the device because all devices have registered with
+the UCLASS_DEMO uclass.
+
+The device is automatically activated ready for use by uclass_get_device().
+
+Now that we have the device we can do things like:
+
+.. code-block:: c
+
+ return demo_hello(demo_dev, ch);
+
+This function is in the demo uclass. It takes care of calling the 'hello'
+method of the relevant driver. Bearing in mind that there are two drivers,
+this particular device may use one or other of them.
+
+The code for demo_hello() is in drivers/demo/demo-uclass.c:
+
+.. code-block:: c
+
+ int demo_hello(struct udevice *dev, int ch)
+ {
+ const struct demo_ops *ops = device_get_ops(dev);
+
+ if (!ops->hello)
+ return -ENOSYS;
+
+ return ops->hello(dev, ch);
+ }
+
+As you can see it just calls the relevant driver method. One of these is
+in drivers/demo/demo-simple.c:
+
+.. code-block:: c
+
+ static int simple_hello(struct udevice *dev, int ch)
+ {
+ const struct dm_demo_pdata *pdata = dev_get_platdata(dev);
+
+ printf("Hello from %08x: %s %d\n", map_to_sysmem(dev),
+ pdata->colour, pdata->sides);
+
+ return 0;
+ }
+
+
+So that is a trip from top (command execution) to bottom (driver action)
+but it leaves a lot of topics to address.
+
+
+Declaring Drivers
+-----------------
+
+A driver declaration looks something like this (see
+drivers/demo/demo-shape.c):
+
+.. code-block:: c
+
+ static const struct demo_ops shape_ops = {
+ .hello = shape_hello,
+ .status = shape_status,
+ };
+
+ U_BOOT_DRIVER(demo_shape_drv) = {
+ .name = "demo_shape_drv",
+ .id = UCLASS_DEMO,
+ .ops = &shape_ops,
+ .priv_data_size = sizeof(struct shape_data),
+ };
+
+
+This driver has two methods (hello and status) and requires a bit of
+private data (accessible through dev_get_priv(dev) once the driver has
+been probed). It is a member of UCLASS_DEMO so will register itself
+there.
+
+In U_BOOT_DRIVER it is also possible to specify special methods for bind
+and unbind, and these are called at appropriate times. For many drivers
+it is hoped that only 'probe' and 'remove' will be needed.
+
+The U_BOOT_DRIVER macro creates a data structure accessible from C,
+so driver model can find the drivers that are available.
+
+The methods a device can provide are documented in the device.h header.
+Briefly, they are:
+
+ * bind - make the driver model aware of a device (bind it to its driver)
+ * unbind - make the driver model forget the device
+ * ofdata_to_platdata - convert device tree data to platdata - see later
+ * probe - make a device ready for use
+ * remove - remove a device so it cannot be used until probed again
+
+The sequence to get a device to work is bind, ofdata_to_platdata (if using
+device tree) and probe.
+
+
+Platform Data
+-------------
+
+Note: platform data is the old way of doing things. It is
+basically a C structure which is passed to drivers to tell them about
+platform-specific settings like the address of its registers, bus
+speed, etc. Device tree is now the preferred way of handling this.
+Unless you have a good reason not to use device tree (the main one
+being you need serial support in SPL and don't have enough SRAM for
+the cut-down device tree and libfdt libraries) you should stay away
+from platform data.
+
+Platform data is like Linux platform data, if you are familiar with that.
+It provides the board-specific information to start up a device.
+
+Why is this information not just stored in the device driver itself? The
+idea is that the device driver is generic, and can in principle operate on
+any board that has that type of device. For example, with modern
+highly-complex SoCs it is common for the IP to come from an IP vendor, and
+therefore (for example) the MMC controller may be the same on chips from
+different vendors. It makes no sense to write independent drivers for the
+MMC controller on each vendor's SoC, when they are all almost the same.
+Similarly, we may have 6 UARTs in an SoC, all of which are mostly the same,
+but lie at different addresses in the address space.
+
+Using the UART example, we have a single driver and it is instantiated 6
+times by supplying 6 lots of platform data. Each lot of platform data
+gives the driver name and a pointer to a structure containing information
+about this instance - e.g. the address of the register space. It may be that
+one of the UARTS supports RS-485 operation - this can be added as a flag in
+the platform data, which is set for this one port and clear for the rest.
+
+Think of your driver as a generic piece of code which knows how to talk to
+a device, but needs to know where it is, any variant/option information and
+so on. Platform data provides this link between the generic piece of code
+and the specific way it is bound on a particular board.
+
+Examples of platform data include:
+
+ - The base address of the IP block's register space
+ - Configuration options, like:
+ - the SPI polarity and maximum speed for a SPI controller
+ - the I2C speed to use for an I2C device
+ - the number of GPIOs available in a GPIO device
+
+Where does the platform data come from? It is either held in a structure
+which is compiled into U-Boot, or it can be parsed from the Device Tree
+(see 'Device Tree' below).
+
+For an example of how it can be compiled in, see demo-pdata.c which
+sets up a table of driver names and their associated platform data.
+The data can be interpreted by the drivers however they like - it is
+basically a communication scheme between the board-specific code and
+the generic drivers, which are intended to work on any board.
+
+Drivers can access their data via dev->info->platdata. Here is
+the declaration for the platform data, which would normally appear
+in the board file.
+
+.. code-block:: c
+
+ static const struct dm_demo_cdata red_square = {
+ .colour = "red",
+ .sides = 4.
+ };
+
+ static const struct driver_info info[] = {
+ {
+ .name = "demo_shape_drv",
+ .platdata = &red_square,
+ },
+ };
+
+ demo1 = driver_bind(root, &info[0]);
+
+
+Device Tree
+-----------
+
+While platdata is useful, a more flexible way of providing device data is
+by using device tree. In U-Boot you should use this where possible. Avoid
+sending patches which make use of the U_BOOT_DEVICE() macro unless strictly
+necessary.
+
+With device tree we replace the above code with the following device tree
+fragment:
+
+.. code-block:: c
+
+ red-square {
+ compatible = "demo-shape";
+ colour = "red";
+ sides = <4>;
+ };
+
+This means that instead of having lots of U_BOOT_DEVICE() declarations in
+the board file, we put these in the device tree. This approach allows a lot
+more generality, since the same board file can support many types of boards
+(e,g. with the same SoC) just by using different device trees. An added
+benefit is that the Linux device tree can be used, thus further simplifying
+the task of board-bring up either for U-Boot or Linux devs (whoever gets to
+the board first!).
+
+The easiest way to make this work it to add a few members to the driver:
+
+.. code-block:: c
+
+ .platdata_auto_alloc_size = sizeof(struct dm_test_pdata),
+ .ofdata_to_platdata = testfdt_ofdata_to_platdata,
+
+The 'auto_alloc' feature allowed space for the platdata to be allocated
+and zeroed before the driver's ofdata_to_platdata() method is called. The
+ofdata_to_platdata() method, which the driver write supplies, should parse
+the device tree node for this device and place it in dev->platdata. Thus
+when the probe method is called later (to set up the device ready for use)
+the platform data will be present.
+
+Note that both methods are optional. If you provide an ofdata_to_platdata
+method then it will be called first (during activation). If you provide a
+probe method it will be called next. See Driver Lifecycle below for more
+details.
+
+If you don't want to have the platdata automatically allocated then you
+can leave out platdata_auto_alloc_size. In this case you can use malloc
+in your ofdata_to_platdata (or probe) method to allocate the required memory,
+and you should free it in the remove method.
+
+The driver model tree is intended to mirror that of the device tree. The
+root driver is at device tree offset 0 (the root node, '/'), and its
+children are the children of the root node.
+
+In order for a device tree to be valid, the content must be correct with
+respect to either device tree specification
+(https://www.devicetree.org/specifications/) or the device tree bindings that
+are found in the doc/device-tree-bindings directory. When not U-Boot specific
+the bindings in this directory tend to come from the Linux Kernel. As such
+certain design decisions may have been made already for us in terms of how
+specific devices are described and bound. In most circumstances we wish to
+retain compatibility without additional changes being made to the device tree
+source files.
+
+Declaring Uclasses
+------------------
+
+The demo uclass is declared like this:
+
+.. code-block:: c
+
+ U_BOOT_CLASS(demo) = {
+ .id = UCLASS_DEMO,
+ };
+
+It is also possible to specify special methods for probe, etc. The uclass
+numbering comes from include/dm/uclass.h. To add a new uclass, add to the
+end of the enum there, then declare your uclass as above.
+
+
+Device Sequence Numbers
+-----------------------
+
+U-Boot numbers devices from 0 in many situations, such as in the command
+line for I2C and SPI buses, and the device names for serial ports (serial0,
+serial1, ...). Driver model supports this numbering and permits devices
+to be locating by their 'sequence'. This numbering uniquely identifies a
+device in its uclass, so no two devices within a particular uclass can have
+the same sequence number.
+
+Sequence numbers start from 0 but gaps are permitted. For example, a board
+may have I2C buses 1, 4, 5 but no 0, 2 or 3. The choice of how devices are
+numbered is up to a particular board, and may be set by the SoC in some
+cases. While it might be tempting to automatically renumber the devices
+where there are gaps in the sequence, this can lead to confusion and is
+not the way that U-Boot works.
+
+Each device can request a sequence number. If none is required then the
+device will be automatically allocated the next available sequence number.
+
+To specify the sequence number in the device tree an alias is typically
+used. Make sure that the uclass has the DM_UC_FLAG_SEQ_ALIAS flag set.
+
+.. code-block:: none
+
+ aliases {
+ serial2 = "/serial@22230000";
+ };
+
+This indicates that in the uclass called "serial", the named node
+("/serial@22230000") will be given sequence number 2. Any command or driver
+which requests serial device 2 will obtain this device.
+
+More commonly you can use node references, which expand to the full path:
+
+.. code-block:: none
+
+ aliases {
+ serial2 = &serial_2;
+ };
+ ...
+ serial_2: serial@22230000 {
+ ...
+ };
+
+The alias resolves to the same string in this case, but this version is
+easier to read.
+
+Device sequence numbers are resolved when a device is probed. Before then
+the sequence number is only a request which may or may not be honoured,
+depending on what other devices have been probed. However the numbering is
+entirely under the control of the board author so a conflict is generally
+an error.
+
+
+Bus Drivers
+-----------
+
+A common use of driver model is to implement a bus, a device which provides
+access to other devices. Example of buses include SPI and I2C. Typically
+the bus provides some sort of transport or translation that makes it
+possible to talk to the devices on the bus.
+
+Driver model provides some useful features to help with implementing buses.
+Firstly, a bus can request that its children store some 'parent data' which
+can be used to keep track of child state. Secondly, the bus can define
+methods which are called when a child is probed or removed. This is similar
+to the methods the uclass driver provides. Thirdly, per-child platform data
+can be provided to specify things like the child's address on the bus. This
+persists across child probe()/remove() cycles.
+
+For consistency and ease of implementation, the bus uclass can specify the
+per-child platform data, so that it can be the same for all children of buses
+in that uclass. There are also uclass methods which can be called when
+children are bound and probed.
+
+Here an explanation of how a bus fits with a uclass may be useful. Consider
+a USB bus with several devices attached to it, each from a different (made
+up) uclass::
+
+ xhci_usb (UCLASS_USB)
+ eth (UCLASS_ETHERNET)
+ camera (UCLASS_CAMERA)
+ flash (UCLASS_FLASH_STORAGE)
+
+Each of the devices is connected to a different address on the USB bus.
+The bus device wants to store this address and some other information such
+as the bus speed for each device.
+
+To achieve this, the bus device can use dev->parent_platdata in each of its
+three children. This can be auto-allocated if the bus driver (or bus uclass)
+has a non-zero value for per_child_platdata_auto_alloc_size. If not, then
+the bus device or uclass can allocate the space itself before the child
+device is probed.
+
+Also the bus driver can define the child_pre_probe() and child_post_remove()
+methods to allow it to do some processing before the child is activated or
+after it is deactivated.
+
+Similarly the bus uclass can define the child_post_bind() method to obtain
+the per-child platform data from the device tree and set it up for the child.
+The bus uclass can also provide a child_pre_probe() method. Very often it is
+the bus uclass that controls these features, since it avoids each driver
+having to do the same processing. Of course the driver can still tweak and
+override these activities.
+
+Note that the information that controls this behaviour is in the bus's
+driver, not the child's. In fact it is possible that child has no knowledge
+that it is connected to a bus. The same child device may even be used on two
+different bus types. As an example. the 'flash' device shown above may also
+be connected on a SATA bus or standalone with no bus::
+
+ xhci_usb (UCLASS_USB)
+ flash (UCLASS_FLASH_STORAGE) - parent data/methods defined by USB bus
+
+ sata (UCLASS_SATA)
+ flash (UCLASS_FLASH_STORAGE) - parent data/methods defined by SATA bus
+
+ flash (UCLASS_FLASH_STORAGE) - no parent data/methods (not on a bus)
+
+Above you can see that the driver for xhci_usb/sata controls the child's
+bus methods. In the third example the device is not on a bus, and therefore
+will not have these methods at all. Consider the case where the flash
+device defines child methods. These would be used for *its* children, and
+would be quite separate from the methods defined by the driver for the bus
+that the flash device is connetced to. The act of attaching a device to a
+parent device which is a bus, causes the device to start behaving like a
+bus device, regardless of its own views on the matter.
+
+The uclass for the device can also contain data private to that uclass.
+But note that each device on the bus may be a memeber of a different
+uclass, and this data has nothing to do with the child data for each child
+on the bus. It is the bus' uclass that controls the child with respect to
+the bus.
+
+
+Driver Lifecycle
+----------------
+
+Here are the stages that a device goes through in driver model. Note that all
+methods mentioned here are optional - e.g. if there is no probe() method for
+a device then it will not be called. A simple device may have very few
+methods actually defined.
+
+Bind stage
+^^^^^^^^^^
+
+U-Boot discovers devices using one of these two methods:
+
+- Scan the U_BOOT_DEVICE() definitions. U-Boot looks up the name specified
+ by each, to find the appropriate U_BOOT_DRIVER() definition. In this case,
+ there is no path by which driver_data may be provided, but the U_BOOT_DEVICE()
+ may provide platdata.
+
+- Scan through the device tree definitions. U-Boot looks at top-level
+ nodes in the the device tree. It looks at the compatible string in each node
+ and uses the of_match table of the U_BOOT_DRIVER() structure to find the
+ right driver for each node. In this case, the of_match table may provide a
+ driver_data value, but platdata cannot be provided until later.
+
+For each device that is discovered, U-Boot then calls device_bind() to create a
+new device, initializes various core fields of the device object such as name,
+uclass & driver, initializes any optional fields of the device object that are
+applicable such as of_offset, driver_data & platdata, and finally calls the
+driver's bind() method if one is defined.
+
+At this point all the devices are known, and bound to their drivers. There
+is a 'struct udevice' allocated for all devices. However, nothing has been
+activated (except for the root device). Each bound device that was created
+from a U_BOOT_DEVICE() declaration will hold the platdata pointer specified
+in that declaration. For a bound device created from the device tree,
+platdata will be NULL, but of_offset will be the offset of the device tree
+node that caused the device to be created. The uclass is set correctly for
+the device.
+
+The device's bind() method is permitted to perform simple actions, but
+should not scan the device tree node, not initialise hardware, nor set up
+structures or allocate memory. All of these tasks should be left for
+the probe() method.
+
+Note that compared to Linux, U-Boot's driver model has a separate step of
+probe/remove which is independent of bind/unbind. This is partly because in
+U-Boot it may be expensive to probe devices and we don't want to do it until
+they are needed, or perhaps until after relocation.
+
+Activation/probe
+^^^^^^^^^^^^^^^^
+
+When a device needs to be used, U-Boot activates it, by following these
+steps (see device_probe()):
+
+ 1. If priv_auto_alloc_size is non-zero, then the device-private space
+ is allocated for the device and zeroed. It will be accessible as
+ dev->priv. The driver can put anything it likes in there, but should use
+ it for run-time information, not platform data (which should be static
+ and known before the device is probed).
+
+ 2. If platdata_auto_alloc_size is non-zero, then the platform data space
+ is allocated. This is only useful for device tree operation, since
+ otherwise you would have to specific the platform data in the
+ U_BOOT_DEVICE() declaration. The space is allocated for the device and
+ zeroed. It will be accessible as dev->platdata.
+
+ 3. If the device's uclass specifies a non-zero per_device_auto_alloc_size,
+ then this space is allocated and zeroed also. It is allocated for and
+ stored in the device, but it is uclass data. owned by the uclass driver.
+ It is possible for the device to access it.
+
+ 4. If the device's immediate parent specifies a per_child_auto_alloc_size
+ then this space is allocated. This is intended for use by the parent
+ device to keep track of things related to the child. For example a USB
+ flash stick attached to a USB host controller would likely use this
+ space. The controller can hold information about the USB state of each
+ of its children.
+
+ 5. All parent devices are probed. It is not possible to activate a device
+ unless its predecessors (all the way up to the root device) are activated.
+ This means (for example) that an I2C driver will require that its bus
+ be activated.
+
+ 6. The device's sequence number is assigned, either the requested one
+ (assuming no conflicts) or the next available one if there is a conflict
+ or nothing particular is requested.
+
+ 7. If the driver provides an ofdata_to_platdata() method, then this is
+ called to convert the device tree data into platform data. This should
+ do various calls like fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), ...)
+ to access the node and store the resulting information into dev->platdata.
+ After this point, the device works the same way whether it was bound
+ using a device tree node or U_BOOT_DEVICE() structure. In either case,
+ the platform data is now stored in the platdata structure. Typically you
+ will use the platdata_auto_alloc_size feature to specify the size of the
+ platform data structure, and U-Boot will automatically allocate and zero
+ it for you before entry to ofdata_to_platdata(). But if not, you can
+ allocate it yourself in ofdata_to_platdata(). Note that it is preferable
+ to do all the device tree decoding in ofdata_to_platdata() rather than
+ in probe(). (Apart from the ugliness of mixing configuration and run-time
+ data, one day it is possible that U-Boot will cache platform data for
+ devices which are regularly de/activated).
+
+ 8. The device's probe() method is called. This should do anything that
+ is required by the device to get it going. This could include checking
+ that the hardware is actually present, setting up clocks for the
+ hardware and setting up hardware registers to initial values. The code
+ in probe() can access:
+
+ - platform data in dev->platdata (for configuration)
+ - private data in dev->priv (for run-time state)
+ - uclass data in dev->uclass_priv (for things the uclass stores
+ about this device)
+
+ Note: If you don't use priv_auto_alloc_size then you will need to
+ allocate the priv space here yourself. The same applies also to
+ platdata_auto_alloc_size. Remember to free them in the remove() method.
+
+ 9. The device is marked 'activated'
+
+ 10. The uclass's post_probe() method is called, if one exists. This may
+ cause the uclass to do some housekeeping to record the device as
+ activated and 'known' by the uclass.
+
+Running stage
+^^^^^^^^^^^^^
+
+The device is now activated and can be used. From now until it is removed
+all of the above structures are accessible. The device appears in the
+uclass's list of devices (so if the device is in UCLASS_GPIO it will appear
+as a device in the GPIO uclass). This is the 'running' state of the device.
+
+Removal stage
+^^^^^^^^^^^^^
+
+When the device is no-longer required, you can call device_remove() to
+remove it. This performs the probe steps in reverse:
+
+ 1. The uclass's pre_remove() method is called, if one exists. This may
+ cause the uclass to do some housekeeping to record the device as
+ deactivated and no-longer 'known' by the uclass.
+
+ 2. All the device's children are removed. It is not permitted to have
+ an active child device with a non-active parent. This means that
+ device_remove() is called for all the children recursively at this point.
+
+ 3. The device's remove() method is called. At this stage nothing has been
+ deallocated so platform data, private data and the uclass data will all
+ still be present. This is where the hardware can be shut down. It is
+ intended that the device be completely inactive at this point, For U-Boot
+ to be sure that no hardware is running, it should be enough to remove
+ all devices.
+
+ 4. The device memory is freed (platform data, private data, uclass data,
+ parent data).
+
+ Note: Because the platform data for a U_BOOT_DEVICE() is defined with a
+ static pointer, it is not de-allocated during the remove() method. For
+ a device instantiated using the device tree data, the platform data will
+ be dynamically allocated, and thus needs to be deallocated during the
+ remove() method, either:
+
+ - if the platdata_auto_alloc_size is non-zero, the deallocation
+ happens automatically within the driver model core; or
+
+ - when platdata_auto_alloc_size is 0, both the allocation (in probe()
+ or preferably ofdata_to_platdata()) and the deallocation in remove()
+ are the responsibility of the driver author.
+
+ 5. The device sequence number is set to -1, meaning that it no longer
+ has an allocated sequence. If the device is later reactivated and that
+ sequence number is still free, it may well receive the name sequence
+ number again. But from this point, the sequence number previously used
+ by this device will no longer exist (think of SPI bus 2 being removed
+ and bus 2 is no longer available for use).
+
+ 6. The device is marked inactive. Note that it is still bound, so the
+ device structure itself is not freed at this point. Should the device be
+ activated again, then the cycle starts again at step 2 above.
+
+Unbind stage
+^^^^^^^^^^^^
+
+The device is unbound. This is the step that actually destroys the device.
+If a parent has children these will be destroyed first. After this point
+the device does not exist and its memory has be deallocated.
+
+
+Data Structures
+---------------
+
+Driver model uses a doubly-linked list as the basic data structure. Some
+nodes have several lists running through them. Creating a more efficient
+data structure might be worthwhile in some rare cases, once we understand
+what the bottlenecks are.
+
+
+Changes since v1
+----------------
+
+For the record, this implementation uses a very similar approach to the
+original patches, but makes at least the following changes:
+
+- Tried to aggressively remove boilerplate, so that for most drivers there
+ is little or no 'driver model' code to write.
+- Moved some data from code into data structure - e.g. store a pointer to
+ the driver operations structure in the driver, rather than passing it
+ to the driver bind function.
+- Rename some structures to make them more similar to Linux (struct udevice
+ instead of struct instance, struct platdata, etc.)
+- Change the name 'core' to 'uclass', meaning U-Boot class. It seems that
+ this concept relates to a class of drivers (or a subsystem). We shouldn't
+ use 'class' since it is a C++ reserved word, so U-Boot class (uclass) seems
+ better than 'core'.
+- Remove 'struct driver_instance' and just use a single 'struct udevice'.
+ This removes a level of indirection that doesn't seem necessary.
+- Built in device tree support, to avoid the need for platdata
+- Removed the concept of driver relocation, and just make it possible for
+ the new driver (created after relocation) to access the old driver data.
+ I feel that relocation is a very special case and will only apply to a few
+ drivers, many of which can/will just re-init anyway. So the overhead of
+ dealing with this might not be worth it.
+- Implemented a GPIO system, trying to keep it simple
+
+
+Pre-Relocation Support
+----------------------
+
+For pre-relocation we simply call the driver model init function. Only
+drivers marked with DM_FLAG_PRE_RELOC or the device tree 'u-boot,dm-pre-reloc'
+property are initialised prior to relocation. This helps to reduce the driver
+model overhead. This flag applies to SPL and TPL as well, if device tree is
+enabled (CONFIG_OF_CONTROL) there.
+
+Note when device tree is enabled, the device tree 'u-boot,dm-pre-reloc'
+property can provide better control granularity on which device is bound
+before relocation. While with DM_FLAG_PRE_RELOC flag of the driver all
+devices with the same driver are bound, which requires allocation a large
+amount of memory. When device tree is not used, DM_FLAG_PRE_RELOC is the
+only way for statically declared devices via U_BOOT_DEVICE() to be bound
+prior to relocation.
+
+It is possible to limit this to specific relocation steps, by using
+the more specialized 'u-boot,dm-spl' and 'u-boot,dm-tpl' flags
+in the device tree node. For U-Boot proper you can use 'u-boot,dm-pre-proper'
+which means that it will be processed (and a driver bound) in U-Boot proper
+prior to relocation, but will not be available in SPL or TPL.
+
+To reduce the size of SPL and TPL, only the nodes with pre-relocation properties
+('u-boot,dm-pre-reloc', 'u-boot,dm-spl' or 'u-boot,dm-tpl') are keept in their
+device trees (see README.SPL for details); the remaining nodes are always bound.
+
+Then post relocation we throw that away and re-init driver model again.
+For drivers which require some sort of continuity between pre- and
+post-relocation devices, we can provide access to the pre-relocation
+device pointers, but this is not currently implemented (the root device
+pointer is saved but not made available through the driver model API).
+
+
+SPL Support
+-----------
+
+Driver model can operate in SPL. Its efficient implementation and small code
+size provide for a small overhead which is acceptable for all but the most
+constrained systems.
+
+To enable driver model in SPL, define CONFIG_SPL_DM. You might want to
+consider the following option also. See the main README for more details.
+
+ - CONFIG_SYS_MALLOC_SIMPLE
+ - CONFIG_DM_WARN
+ - CONFIG_DM_DEVICE_REMOVE
+ - CONFIG_DM_STDIO
+
+
+Enabling Driver Model
+---------------------
+
+Driver model is being brought into U-Boot gradually. As each subsystems gets
+support, a uclass is created and a CONFIG to enable use of driver model for
+that subsystem.
+
+For example CONFIG_DM_SERIAL enables driver model for serial. With that
+defined, the old serial support is not enabled, and your serial driver must
+conform to driver model. With that undefined, the old serial support is
+enabled and driver model is not available for serial. This means that when
+you convert a driver, you must either convert all its boards, or provide for
+the driver to be compiled both with and without driver model (generally this
+is not very hard).
+
+See the main README for full details of the available driver model CONFIG
+options.
+
+
+Things to punt for later
+------------------------
+
+Uclasses are statically numbered at compile time. It would be possible to
+change this to dynamic numbering, but then we would require some sort of
+lookup service, perhaps searching by name. This is slightly less efficient
+so has been left out for now. One small advantage of dynamic numbering might
+be fewer merge conflicts in uclass-id.h.
diff --git a/doc/driver-model/fdt-fixup.rst b/doc/driver-model/fdt-fixup.rst
new file mode 100644
index 0000000..974c090
--- /dev/null
+++ b/doc/driver-model/fdt-fixup.rst
@@ -0,0 +1,132 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. 2017-01-06, Mario Six <mario.six@gdsys.cc>
+
+Pre-relocation device tree manipulation
+=======================================
+
+Purpose
+-------
+
+In certain markets, it is beneficial for manufacturers of embedded devices to
+offer certain ranges of products, where the functionality of the devices within
+one series either don't differ greatly from another, or can be thought of as
+"extensions" of each other, where one device only differs from another in the
+addition of a small number of features (e.g. an additional output connector).
+
+To realize this in hardware, one method is to have a motherboard, and several
+possible daughter boards that can be attached to this mother board. Different
+daughter boards then either offer the slightly different functionality, or the
+addition of the daughter board to the device realizes the "extension" of
+functionality to the device described previously.
+
+For the software, we obviously want to reuse components for all these
+variations of the device. This means that the software somehow needs to cope
+with the situation that certain ICs may or may not be present on any given
+system, depending on which daughter boards are connected to the motherboard.
+
+In the Linux kernel, one possible solution to this problem is to employ the
+device tree overlay mechanism: There exists one "base" device tree, which
+features only the components guaranteed to exist in all varieties of the
+device. At the start of the kernel, the presence and type of the daughter
+boards is then detected, and the corresponding device tree overlays are applied
+to support the components on the daughter boards.
+
+Note that the components present on every variety of the board must, of course,
+provide a way to find out if and which daughter boards are installed for this
+mechanism to work.
+
+In the U-Boot boot loader, support for device tree overlays has recently been
+integrated, and is used on some boards to alter the device tree that is later
+passed to Linux. But since U-Boot's driver model, which is device tree-based as
+well, is being used in more and more drivers, the same problem of altering the
+device tree starts cropping up in U-Boot itself as well.
+
+An additional problem with the device tree in U-Boot is that it is read-only,
+and the current mechanisms don't allow easy manipulation of the device tree
+after the driver model has been initialized. While migrating to a live device
+tree (at least after the relocation) would greatly simplify the solution of
+this problem, it is a non-negligible task to implement it, an a interim
+solution is needed to address the problem at least in the medium-term.
+
+Hence, we propose a solution to this problem by offering a board-specific
+call-back function, which is passed a writeable pointer to the device tree.
+This function is called before the device tree is relocated, and specifically
+before the main U-Boot's driver model is instantiated, hence the main U-Boot
+"sees" all modifications to the device tree made in this function. Furthermore,
+we have the pre-relocation driver model at our disposal at this stage, which
+means that we can query the hardware for the existence and variety of the
+components easily.
+
+Implementation
+--------------
+
+To take advantage of the pre-relocation device tree manipulation mechanism,
+boards have to implement the function board_fix_fdt, which has the following
+signature:
+
+.. code-block:: c
+
+ int board_fix_fdt (void *rw_fdt_blob)
+
+The passed-in void pointer is a writeable pointer to the device tree, which can
+be used to manipulate the device tree using e.g. functions from
+include/fdt_support.h. The return value should either be 0 in case of
+successful execution of the device tree manipulation or something else for a
+failure. Note that returning a non-null value from the function will
+unrecoverably halt the boot process, as with any function from init_sequence_f
+(in common/board_f.c).
+
+Furthermore, the Kconfig option OF_BOARD_FIXUP has to be set for the function
+to be called::
+
+ Device Tree Control
+ -> [*] Board-specific manipulation of Device Tree
+
++----------------------------------------------------------+
+| WARNING: The actual manipulation of the device tree has |
+| to be the _last_ set of operations in board_fix_fdt! |
+| Since the pre-relocation driver model does not adapt to |
+| changes made to the device tree either, its references |
+| into the device tree will be invalid after manipulating |
+| it, and unpredictable behavior might occur when |
+| functions that rely on them are executed! |
++----------------------------------------------------------+
+
+Hence, the recommended layout of the board_fixup_fdt call-back function is the
+following:
+
+.. code-block:: c
+
+ int board_fix_fdt(void *rw_fdt_blob)
+ {
+ /*
+ * Collect information about device's hardware and store
+ * them in e.g. local variables
+ */
+
+ /* Do device tree manipulation using the values previously collected */
+
+ /* Return 0 on successful manipulation and non-zero otherwise */
+ }
+
+If this convention is kept, both an "additive" approach, meaning that nodes for
+detected components are added to the device tree, as well as a "subtractive"
+approach, meaning that nodes for absent components are removed from the tree,
+as well as a combination of both approaches should work.
+
+Example
+-------
+
+The controlcenterdc board (board/gdsys/a38x/controlcenterdc.c) features a
+board_fix_fdt function, in which six GPIO expanders (which might be present or
+not, since they are on daughter boards) on a I2C bus are queried for, and
+subsequently deactivated in the device tree if they are not present.
+
+Note that the dm_i2c_simple_probe function does not use the device tree, hence
+it is safe to call it after the tree has already been manipulated.
+
+Work to be done
+---------------
+
+* The application of device tree overlay should be possible in board_fixup_fdt,
+ but has not been tested at this stage.
diff --git a/doc/driver-model/fdt-fixup.txt b/doc/driver-model/fdt-fixup.txt
deleted file mode 100644
index 70344bd..0000000
--- a/doc/driver-model/fdt-fixup.txt
+++ /dev/null
@@ -1,132 +0,0 @@
-Pre-relocation device tree manipulation
-=======================================
-
-Contents:
-
-1. Purpose
-2. Implementation
-3. Example
-4. Work to be done
-
-1. Purpose
-----------
-
-In certain markets, it is beneficial for manufacturers of embedded devices to
-offer certain ranges of products, where the functionality of the devices within
-one series either don't differ greatly from another, or can be thought of as
-"extensions" of each other, where one device only differs from another in the
-addition of a small number of features (e.g. an additional output connector).
-
-To realize this in hardware, one method is to have a motherboard, and several
-possible daughter boards that can be attached to this mother board. Different
-daughter boards then either offer the slightly different functionality, or the
-addition of the daughter board to the device realizes the "extension" of
-functionality to the device described previously.
-
-For the software, we obviously want to reuse components for all these
-variations of the device. This means that the software somehow needs to cope
-with the situation that certain ICs may or may not be present on any given
-system, depending on which daughter boards are connected to the motherboard.
-
-In the Linux kernel, one possible solution to this problem is to employ the
-device tree overlay mechanism: There exists one "base" device tree, which
-features only the components guaranteed to exist in all varieties of the
-device. At the start of the kernel, the presence and type of the daughter
-boards is then detected, and the corresponding device tree overlays are applied
-to support the components on the daughter boards.
-
-Note that the components present on every variety of the board must, of course,
-provide a way to find out if and which daughter boards are installed for this
-mechanism to work.
-
-In the U-Boot boot loader, support for device tree overlays has recently been
-integrated, and is used on some boards to alter the device tree that is later
-passed to Linux. But since U-Boot's driver model, which is device tree-based as
-well, is being used in more and more drivers, the same problem of altering the
-device tree starts cropping up in U-Boot itself as well.
-
-An additional problem with the device tree in U-Boot is that it is read-only,
-and the current mechanisms don't allow easy manipulation of the device tree
-after the driver model has been initialized. While migrating to a live device
-tree (at least after the relocation) would greatly simplify the solution of
-this problem, it is a non-negligible task to implement it, an a interim
-solution is needed to address the problem at least in the medium-term.
-
-Hence, we propose a solution to this problem by offering a board-specific
-call-back function, which is passed a writeable pointer to the device tree.
-This function is called before the device tree is relocated, and specifically
-before the main U-Boot's driver model is instantiated, hence the main U-Boot
-"sees" all modifications to the device tree made in this function. Furthermore,
-we have the pre-relocation driver model at our disposal at this stage, which
-means that we can query the hardware for the existence and variety of the
-components easily.
-
-2. Implementation
------------------
-
-To take advantage of the pre-relocation device tree manipulation mechanism,
-boards have to implement the function board_fix_fdt, which has the following
-signature:
-
-int board_fix_fdt (void *rw_fdt_blob)
-
-The passed-in void pointer is a writeable pointer to the device tree, which can
-be used to manipulate the device tree using e.g. functions from
-include/fdt_support.h. The return value should either be 0 in case of
-successful execution of the device tree manipulation or something else for a
-failure. Note that returning a non-null value from the function will
-unrecoverably halt the boot process, as with any function from init_sequence_f
-(in common/board_f.c).
-
-Furthermore, the Kconfig option OF_BOARD_FIXUP has to be set for the function
-to be called:
-
-Device Tree Control
--> [*] Board-specific manipulation of Device Tree
-
-+----------------------------------------------------------+
-| WARNING: The actual manipulation of the device tree has |
-| to be the _last_ set of operations in board_fix_fdt! |
-| Since the pre-relocation driver model does not adapt to |
-| changes made to the device tree either, its references |
-| into the device tree will be invalid after manipulating |
-| it, and unpredictable behavior might occur when |
-| functions that rely on them are executed! |
-+----------------------------------------------------------+
-
-Hence, the recommended layout of the board_fixup_fdt call-back function is the
-following:
-
-int board_fix_fdt(void *rw_fdt_blob)
-{
- /* Collect information about device's hardware and store them in e.g.
- local variables */
-
- /* Do device tree manipulation using the values previously collected */
-
- /* Return 0 on successful manipulation and non-zero otherwise */
-}
-
-If this convention is kept, both an "additive" approach, meaning that nodes for
-detected components are added to the device tree, as well as a "subtractive"
-approach, meaning that nodes for absent components are removed from the tree,
-as well as a combination of both approaches should work.
-
-3. Example
-----------
-
-The controlcenterdc board (board/gdsys/a38x/controlcenterdc.c) features a
-board_fix_fdt function, in which six GPIO expanders (which might be present or
-not, since they are on daughter boards) on a I2C bus are queried for, and
-subsequently deactivated in the device tree if they are not present.
-
-Note that the dm_i2c_simple_probe function does not use the device tree, hence
-it is safe to call it after the tree has already been manipulated.
-
-4. Work to be done
-------------------
-
-* The application of device tree overlay should be possible in board_fixup_fdt,
- but has not been tested at this stage.
-
-2017-01-06, Mario Six <mario.six@gdsys.cc>
diff --git a/doc/driver-model/fs_firmware_loader.rst b/doc/driver-model/fs_firmware_loader.rst
new file mode 100644
index 0000000..a44708c
--- /dev/null
+++ b/doc/driver-model/fs_firmware_loader.rst
@@ -0,0 +1,154 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (C) 2018-2019 Intel Corporation <www.intel.com>
+
+File System Firmware Loader
+===========================
+
+This is file system firmware loader for U-Boot framework, which has very close
+to some Linux Firmware API. For the details of Linux Firmware API, you can refer
+to https://01.org/linuxgraphics/gfx-docs/drm/driver-api/firmware/index.html.
+
+File system firmware loader can be used to load whatever(firmware, image,
+and binary) from the storage device in file system format into target location
+such as memory, then consumer driver such as FPGA driver can program FPGA image
+from the target location into FPGA.
+
+To enable firmware loader, CONFIG_FS_LOADER need to be set at
+<board_name>_defconfig such as "CONFIG_FS_LOADER=y".
+
+Firmware Loader API core features
+---------------------------------
+
+Firmware storage device described in device tree source
+-------------------------------------------------------
+For passing data like storage device phandle and partition where the
+firmware loading from to the firmware loader driver, those data could be
+defined in fs-loader node as shown in below:
+
+Example for block device::
+
+ fs_loader0: fs-loader {
+ u-boot,dm-pre-reloc;
+ compatible = "u-boot,fs-loader";
+ phandlepart = <&mmc 1>;
+ };
+
+<&mmc 1> means block storage device pointer and its partition.
+
+Above example is a description for block storage, but for UBI storage
+device, it can be described in FDT as shown in below:
+
+Example for ubi::
+
+ fs_loader1: fs-loader {
+ u-boot,dm-pre-reloc;
+ compatible = "u-boot,fs-loader";
+ mtdpart = "UBI",
+ ubivol = "ubi0";
+ };
+
+Then, firmware-loader property can be added with any device node, which
+driver would use the firmware loader for loading.
+
+The value of the firmware-loader property should be set with phandle
+of the fs-loader node. For example::
+
+ firmware-loader = <&fs_loader0>;
+
+If there are majority of devices using the same fs-loader node, then
+firmware-loader property can be added under /chosen node instead of
+adding to each of device node.
+
+For example::
+
+ /{
+ chosen {
+ firmware-loader = <&fs_loader0>;
+ };
+ };
+
+In each respective driver of devices using firmware loader, the firmware
+loaded instance should be created by DT phandle.
+
+For example of getting DT phandle from /chosen and creating instance:
+
+.. code-block:: c
+
+ chosen_node = ofnode_path("/chosen");
+ if (!ofnode_valid(chosen_node)) {
+ debug("/chosen node was not found.\n");
+ return -ENOENT;
+ }
+
+ phandle_p = ofnode_get_property(chosen_node, "firmware-loader", &size);
+ if (!phandle_p) {
+ debug("firmware-loader property was not found.\n");
+ return -ENOENT;
+ }
+
+ phandle = fdt32_to_cpu(*phandle_p);
+ ret = uclass_get_device_by_phandle_id(UCLASS_FS_FIRMWARE_LOADER,
+ phandle, &dev);
+ if (ret)
+ return ret;
+
+Firmware loader driver is also designed to support U-boot environment
+variables, so all these data from FDT can be overwritten
+through the U-boot environment variable during run time.
+
+For examples:
+
+storage_interface:
+ Storage interface, it can be "mmc", "usb", "sata" or "ubi".
+fw_dev_part:
+ Block device number and its partition, it can be "0:1".
+fw_ubi_mtdpart:
+ UBI device mtd partition, it can be "UBI".
+fw_ubi_volume:
+ UBI volume, it can be "ubi0".
+
+When above environment variables are set, environment values would be
+used instead of data from FDT.
+The benefit of this design allows user to change storage attribute data
+at run time through U-boot console and saving the setting as default
+environment values in the storage for the next power cycle, so no
+compilation is required for both driver and FDT.
+
+File system firmware Loader API
+-------------------------------
+
+.. code-block:: c
+
+ int request_firmware_into_buf(struct udevice *dev,
+ const char *name,
+ void *buf, size_t size, u32 offset)
+
+Load firmware into a previously allocated buffer
+
+Parameters:
+
+* struct udevice \*dev: An instance of a driver
+* const char \*name: name of firmware file
+* void \*buf: address of buffer to load firmware into
+* size_t size: size of buffer
+* u32 offset: offset of a file for start reading into buffer
+
+Returns:
+ size of total read
+ -ve when error
+
+Description:
+ The firmware is loaded directly into the buffer pointed to by buf
+
+Example of calling request_firmware_into_buf API after creating firmware loader
+instance:
+
+.. code-block:: c
+
+ ret = uclass_get_device_by_phandle_id(UCLASS_FS_FIRMWARE_LOADER,
+ phandle, &dev);
+ if (ret)
+ return ret;
+
+ request_firmware_into_buf(dev, filename, buffer_location, buffer_size,
+ offset_ofreading);
diff --git a/doc/driver-model/fs_firmware_loader.txt b/doc/driver-model/fs_firmware_loader.txt
deleted file mode 100644
index 8be6185..0000000
--- a/doc/driver-model/fs_firmware_loader.txt
+++ /dev/null
@@ -1,148 +0,0 @@
-# Copyright (C) 2018-2019 Intel Corporation <www.intel.com>
-#
-# SPDX-License-Identifier: GPL-2.0
-
-Introduction
-============
-
-This is file system firmware loader for U-Boot framework, which has very close
-to some Linux Firmware API. For the details of Linux Firmware API, you can refer
-to https://01.org/linuxgraphics/gfx-docs/drm/driver-api/firmware/index.html.
-
-File system firmware loader can be used to load whatever(firmware, image,
-and binary) from the storage device in file system format into target location
-such as memory, then consumer driver such as FPGA driver can program FPGA image
-from the target location into FPGA.
-
-To enable firmware loader, CONFIG_FS_LOADER need to be set at
-<board_name>_defconfig such as "CONFIG_FS_LOADER=y".
-
-Firmware Loader API core features
----------------------------------
-
-Firmware storage device described in device tree source
--------------------------------------------------------
- For passing data like storage device phandle and partition where the
- firmware loading from to the firmware loader driver, those data could be
- defined in fs-loader node as shown in below:
-
- Example for block device:
- fs_loader0: fs-loader {
- u-boot,dm-pre-reloc;
- compatible = "u-boot,fs-loader";
- phandlepart = <&mmc 1>;
- };
-
- <&mmc 1> means block storage device pointer and its partition.
-
- Above example is a description for block storage, but for UBI storage
- device, it can be described in FDT as shown in below:
-
- Example for ubi:
- fs_loader1: fs-loader {
- u-boot,dm-pre-reloc;
- compatible = "u-boot,fs-loader";
- mtdpart = "UBI",
- ubivol = "ubi0";
- };
-
- Then, firmware-loader property can be added with any device node, which
- driver would use the firmware loader for loading.
-
- The value of the firmware-loader property should be set with phandle
- of the fs-loader node.
- For example:
- firmware-loader = <&fs_loader0>;
-
- If there are majority of devices using the same fs-loader node, then
- firmware-loader property can be added under /chosen node instead of
- adding to each of device node.
-
- For example:
- /{
- chosen {
- firmware-loader = <&fs_loader0>;
- };
- };
-
- In each respective driver of devices using firmware loader, the firmware
- loaded instance should be created by DT phandle.
-
- For example of getting DT phandle from /chosen and creating instance:
- chosen_node = ofnode_path("/chosen");
- if (!ofnode_valid(chosen_node)) {
- debug("/chosen node was not found.\n");
- return -ENOENT;
- }
-
- phandle_p = ofnode_get_property(chosen_node, "firmware-loader", &size);
- if (!phandle_p) {
- debug("firmware-loader property was not found.\n");
- return -ENOENT;
- }
-
- phandle = fdt32_to_cpu(*phandle_p);
- ret = uclass_get_device_by_phandle_id(UCLASS_FS_FIRMWARE_LOADER,
- phandle, &dev);
- if (ret)
- return ret;
-
- Firmware loader driver is also designed to support U-boot environment
- variables, so all these data from FDT can be overwritten
- through the U-boot environment variable during run time.
- For examples:
- "storage_interface" - Storage interface, it can be "mmc", "usb", "sata"
- or "ubi".
- "fw_dev_part" - Block device number and its partition, it can be "0:1".
- "fw_ubi_mtdpart" - UBI device mtd partition, it can be "UBI".
- "fw_ubi_volume" - UBI volume, it can be "ubi0".
-
- When above environment variables are set, environment values would be
- used instead of data from FDT.
- The benefit of this design allows user to change storage attribute data
- at run time through U-boot console and saving the setting as default
- environment values in the storage for the next power cycle, so no
- compilation is required for both driver and FDT.
-
-File system firmware Loader API
--------------------------------
-
-int request_firmware_into_buf(struct udevice *dev,
- const char *name,
- void *buf, size_t size, u32 offset)
---------------------------------------------------------------------
-Load firmware into a previously allocated buffer
-
-Parameters:
-
-1. struct udevice *dev
- An instance of a driver
-
-2. const char *name
- name of firmware file
-
-3. void *buf
- address of buffer to load firmware into
-
-4. size_t size
- size of buffer
-
-5. u32 offset
- offset of a file for start reading into buffer
-
-return:
- size of total read
- -ve when error
-
-Description:
- The firmware is loaded directly into the buffer pointed to by buf
-
-Example of calling request_firmware_into_buf API after creating firmware loader
-instance:
- ret = uclass_get_device_by_phandle_id(UCLASS_FS_FIRMWARE_LOADER,
- phandle, &dev);
- if (ret)
- return ret;
-
- request_firmware_into_buf(dev, filename, buffer_location, buffer_size,
- offset_ofreading);
diff --git a/doc/driver-model/i2c-howto.rst b/doc/driver-model/i2c-howto.rst
new file mode 100644
index 0000000..938b707
--- /dev/null
+++ b/doc/driver-model/i2c-howto.rst
@@ -0,0 +1,56 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+How to port an I2C driver to driver model
+=========================================
+
+Over half of the I2C drivers have been converted as at November 2016. These
+ones remain:
+
+ * adi_i2c
+ * davinci_i2c
+ * fti2c010
+ * ihs_i2c
+ * kona_i2c
+ * lpc32xx_i2c
+ * pca9564_i2c
+ * ppc4xx_i2c
+ * rcar_i2c
+ * sh_i2c
+ * soft_i2c
+ * zynq_i2c
+
+The deadline for this work is the end of June 2017. If no one steps
+forward to convert these, at some point there may come a patch to remove them!
+
+Here is a suggested approach for converting your I2C driver over to driver
+model. Please feel free to update this file with your ideas and suggestions.
+
+- #ifdef out all your own I2C driver code (#ifndef CONFIG_DM_I2C)
+- Define CONFIG_DM_I2C for your board, vendor or architecture
+- If the board does not already use driver model, you need CONFIG_DM also
+- Your board should then build, but will not work fully since there will be
+ no I2C driver
+- Add the U_BOOT_DRIVER piece at the end (e.g. copy tegra_i2c.c for example)
+- Add a private struct for the driver data - avoid using static variables
+- Implement each of the driver methods, perhaps by calling your old methods
+- You may need to adjust the function parameters so that the old and new
+ implementations can share most of the existing code
+- If you convert all existing users of the driver, remove the pre-driver-model
+ code
+
+In terms of patches a conversion series typically has these patches:
+- clean up / prepare the driver for conversion
+- add driver model code
+- convert at least one existing board to use driver model serial
+- (if no boards remain that don't use driver model) remove the old code
+
+This may be a good time to move your board to use device tree also. Mostly
+this involves these steps:
+
+- define CONFIG_OF_CONTROL and CONFIG_OF_SEPARATE
+- add your device tree files to arch/<arch>/dts
+- update the Makefile there
+- Add stdout-path to your /chosen device tree node if it is not already there
+- build and get u-boot-dtb.bin so you can test it
+- Your drivers can now use device tree
+- For device tree in SPL, define CONFIG_SPL_OF_CONTROL
diff --git a/doc/driver-model/i2c-howto.txt b/doc/driver-model/i2c-howto.txt
deleted file mode 100644
index 8ba2f6e..0000000
--- a/doc/driver-model/i2c-howto.txt
+++ /dev/null
@@ -1,54 +0,0 @@
-How to port a serial driver to driver model
-===========================================
-
-Over half of the I2C drivers have been converted as at November 2016. These
-ones remain:
-
- adi_i2c
- davinci_i2c
- fti2c010
- ihs_i2c
- kona_i2c
- lpc32xx_i2c
- pca9564_i2c
- ppc4xx_i2c
- rcar_i2c
- sh_i2c
- soft_i2c
- zynq_i2c
-
-The deadline for this work is the end of June 2017. If no one steps
-forward to convert these, at some point there may come a patch to remove them!
-
-Here is a suggested approach for converting your I2C driver over to driver
-model. Please feel free to update this file with your ideas and suggestions.
-
-- #ifdef out all your own I2C driver code (#ifndef CONFIG_DM_I2C)
-- Define CONFIG_DM_I2C for your board, vendor or architecture
-- If the board does not already use driver model, you need CONFIG_DM also
-- Your board should then build, but will not work fully since there will be
- no I2C driver
-- Add the U_BOOT_DRIVER piece at the end (e.g. copy tegra_i2c.c for example)
-- Add a private struct for the driver data - avoid using static variables
-- Implement each of the driver methods, perhaps by calling your old methods
-- You may need to adjust the function parameters so that the old and new
- implementations can share most of the existing code
-- If you convert all existing users of the driver, remove the pre-driver-model
- code
-
-In terms of patches a conversion series typically has these patches:
-- clean up / prepare the driver for conversion
-- add driver model code
-- convert at least one existing board to use driver model serial
-- (if no boards remain that don't use driver model) remove the old code
-
-This may be a good time to move your board to use device tree also. Mostly
-this involves these steps:
-
-- define CONFIG_OF_CONTROL and CONFIG_OF_SEPARATE
-- add your device tree files to arch/<arch>/dts
-- update the Makefile there
-- Add stdout-path to your /chosen device tree node if it is not already there
-- build and get u-boot-dtb.bin so you can test it
-- Your drivers can now use device tree
-- For device tree in SPL, define CONFIG_SPL_OF_CONTROL
diff --git a/doc/driver-model/index.rst b/doc/driver-model/index.rst
new file mode 100644
index 0000000..ea32c36
--- /dev/null
+++ b/doc/driver-model/index.rst
@@ -0,0 +1,21 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Driver Model
+============
+
+.. toctree::
+ :maxdepth: 2
+
+ design
+ fdt-fixup
+ fs_firmware_loader
+ i2c-howto
+ livetree
+ migration
+ of-plat
+ pci-info
+ pmic-framework
+ remoteproc-framework
+ serial-howto
+ spi-howto
+ usb-info
diff --git a/doc/driver-model/livetree.rst b/doc/driver-model/livetree.rst
new file mode 100644
index 0000000..9f654f3
--- /dev/null
+++ b/doc/driver-model/livetree.rst
@@ -0,0 +1,286 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Simon Glass <sjg@chromium.org>
+
+Live Device Tree
+================
+
+
+Introduction
+------------
+
+Traditionally U-Boot has used a 'flat' device tree. This means that it
+reads directly from the device tree binary structure. It is called a flat
+device tree because nodes are listed one after the other, with the
+hierarchy detected by tags in the format.
+
+This document describes U-Boot's support for a 'live' device tree, meaning
+that the tree is loaded into a hierarchical data structure within U-Boot.
+
+
+Motivation
+----------
+
+The flat device tree has several advantages:
+
+- it is the format produced by the device tree compiler, so no translation
+ is needed
+
+- it is fairly compact (e.g. there is no need for pointers)
+
+- it is accessed by the libfdt library, which is well tested and stable
+
+
+However the flat device tree does have some limitations. Adding new
+properties can involve copying large amounts of data around to make room.
+The overall tree has a fixed maximum size so sometimes the tree must be
+rebuilt in a new location to create more space. Even if not adding new
+properties or nodes, scanning the tree can be slow. For example, finding
+the parent of a node is a slow process. Reading from nodes involves a
+small amount parsing which takes a little time.
+
+Driver model scans the entire device tree sequentially on start-up which
+avoids the worst of the flat tree's limitations. But if the tree is to be
+modified at run-time, a live tree is much faster. Even if no modification
+is necessary, parsing the tree once and using a live tree from then on
+seems to save a little time.
+
+
+Implementation
+--------------
+
+In U-Boot a live device tree ('livetree') is currently supported only
+after relocation. Therefore we need a mechanism to specify a device
+tree node regardless of whether it is in the flat tree or livetree.
+
+The 'ofnode' type provides this. An ofnode can point to either a flat tree
+node (when the live tree node is not yet set up) or a livetree node. The
+caller of an ofnode function does not need to worry about these details.
+
+The main users of the information in a device tree are drivers. These have
+a 'struct udevice \*' which is attached to a device tree node. Therefore it
+makes sense to be able to read device tree properties using the
+'struct udevice \*', rather than having to obtain the ofnode first.
+
+The 'dev_read\_...()' interface provides this. It allows properties to be
+easily read from the device tree using only a device pointer. Under the
+hood it uses ofnode so it works with both flat and live device trees.
+
+
+Enabling livetree
+-----------------
+
+CONFIG_OF_LIVE enables livetree. When this option is enabled, the flat
+tree will be used in SPL and before relocation in U-Boot proper. Just
+before relocation a livetree is built, and this is used for U-Boot proper
+after relocation.
+
+Most checks for livetree use CONFIG_IS_ENABLED(OF_LIVE). This means that
+for SPL, the CONFIG_SPL_OF_LIVE option is checked. At present this does
+not exist, since SPL does not support livetree.
+
+
+Porting drivers
+---------------
+
+Many existing drivers use the fdtdec interface to read device tree
+properties. This only works with a flat device tree. The drivers should be
+converted to use the dev_read_() interface.
+
+For example, the old code may be like this:
+
+.. code-block:: c
+
+ struct udevice *bus;
+ const void *blob = gd->fdt_blob;
+ int node = dev_of_offset(bus);
+
+ i2c_bus->regs = (struct i2c_ctlr *)devfdt_get_addr(dev);
+ plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", 500000);
+
+The new code is:
+
+.. code-block:: c
+
+ struct udevice *bus;
+
+ i2c_bus->regs = (struct i2c_ctlr *)dev_read_addr(dev);
+ plat->frequency = dev_read_u32_default(bus, "spi-max-frequency", 500000);
+
+The dev_read\_...() interface is more convenient and works with both the
+flat and live device trees. See include/dm/read.h for a list of functions.
+
+Where properties must be read from sub-nodes or other nodes, you must fall
+back to using ofnode. For example, for old code like this:
+
+.. code-block:: c
+
+ const void *blob = gd->fdt_blob;
+ int subnode;
+
+ fdt_for_each_subnode(subnode, blob, dev_of_offset(dev)) {
+ freq = fdtdec_get_int(blob, node, "spi-max-frequency", 500000);
+ ...
+ }
+
+you should use:
+
+.. code-block:: c
+
+ ofnode subnode;
+
+ ofnode_for_each_subnode(subnode, dev_ofnode(dev)) {
+ freq = ofnode_read_u32(node, "spi-max-frequency", 500000);
+ ...
+ }
+
+
+Useful ofnode functions
+-----------------------
+
+The internal data structures of the livetree are defined in include/dm/of.h :
+
+ :struct device_node: holds information about a device tree node
+ :struct property: holds information about a property within a node
+
+Nodes have pointers to their first property, their parent, their first child
+and their sibling. This allows nodes to be linked together in a hierarchical
+tree.
+
+Properties have pointers to the next property. This allows all properties of
+a node to be linked together in a chain.
+
+It should not be necessary to use these data structures in normal code. In
+particular, you should refrain from using functions which access the livetree
+directly, such as of_read_u32(). Use ofnode functions instead, to allow your
+code to work with a flat tree also.
+
+Some conversion functions are used internally. Generally these are not needed
+for driver code. Note that they will not work if called in the wrong context.
+For example it is invalid to call ofnode_to_no() when a flat tree is being
+used. Similarly it is not possible to call ofnode_to_offset() on a livetree
+node.
+
+ofnode_to_np():
+ converts ofnode to struct device_node *
+ofnode_to_offset():
+ converts ofnode to offset
+
+no_to_ofnode():
+ converts node pointer to ofnode
+offset_to_ofnode():
+ converts offset to ofnode
+
+
+Other useful functions:
+
+of_live_active():
+ returns true if livetree is in use, false if flat tree
+ofnode_valid():
+ return true if a given node is valid
+ofnode_is_np():
+ returns true if a given node is a livetree node
+ofnode_equal():
+ compares two ofnodes
+ofnode_null():
+ returns a null ofnode (for which ofnode_valid() returns false)
+
+
+Phandles
+--------
+
+There is full phandle support for live tree. All functions make use of
+struct ofnode_phandle_args, which has an ofnode within it. This supports both
+livetree and flat tree transparently. See for example
+ofnode_parse_phandle_with_args().
+
+
+Reading addresses
+-----------------
+
+You should use dev_read_addr() and friends to read addresses from device-tree
+nodes.
+
+
+fdtdec
+------
+
+The existing fdtdec interface will eventually be retired. Please try to avoid
+using it in new code.
+
+
+Modifying the livetree
+----------------------
+
+This is not currently supported. Once implemented it should provide a much
+more efficient implementation for modification of the device tree than using
+the flat tree.
+
+
+Internal implementation
+-----------------------
+
+The dev_read\_...() functions have two implementations. When
+CONFIG_DM_DEV_READ_INLINE is enabled, these functions simply call the ofnode
+functions directly. This is useful when livetree is not enabled. The ofnode
+functions call ofnode_is_np(node) which will always return false if livetree
+is disabled, just falling back to flat tree code.
+
+This optimisation means that without livetree enabled, the dev_read\_...() and
+ofnode interfaces do not noticeably add to code size.
+
+The CONFIG_DM_DEV_READ_INLINE option defaults to enabled when livetree is
+disabled.
+
+Most livetree code comes directly from Linux and is modified as little as
+possible. This is deliberate since this code is fairly stable and does what
+we want. Some features (such as get/put) are not supported. Internal macros
+take care of removing these features silently.
+
+Within the of_access.c file there are pointers to the alias node, the chosen
+node and the stdout-path alias.
+
+
+Errors
+------
+
+With a flat device tree, libfdt errors are returned (e.g. -FDT_ERR_NOTFOUND).
+For livetree normal 'errno' errors are returned (e.g. -ENOTFOUND). At present
+the ofnode and dev_read\_...() functions return either one or other type of
+error. This is clearly not desirable. Once tests are added for all the
+functions this can be tidied up.
+
+
+Adding new access functions
+---------------------------
+
+Adding a new function for device-tree access involves the following steps:
+
+ - Add two dev_read() functions:
+ - inline version in the read.h header file, which calls an ofnode function
+ - standard version in the read.c file (or perhaps another file), which
+ also calls an ofnode function
+
+ The implementations of these functions can be the same. The purpose
+ of the inline version is purely to reduce code size impact.
+
+ - Add an ofnode function. This should call ofnode_is_np() to work out
+ whether a livetree or flat tree is used. For the livetree it should
+ call an of\_...() function. For the flat tree it should call an
+ fdt\_...() function. The livetree version will be optimised out at
+ compile time if livetree is not enabled.
+
+ - Add an of\_...() function for the livetree implementation. If a similar
+ function is available in Linux, the implementation should be taken
+ from there and modified as little as possible (generally not at all).
+
+
+Future work
+-----------
+
+Live tree support was introduced in U-Boot 2017.07. There is still quite a bit
+of work to do to flesh this out:
+
+- tests for all access functions
+- support for livetree modification
+- addition of more access functions as needed
+- support for livetree in SPL and before relocation (if desired)
diff --git a/doc/driver-model/livetree.txt b/doc/driver-model/livetree.txt
deleted file mode 100644
index 01d4488..0000000
--- a/doc/driver-model/livetree.txt
+++ /dev/null
@@ -1,272 +0,0 @@
-Driver Model with Live Device Tree
-==================================
-
-
-Introduction
-------------
-
-Traditionally U-Boot has used a 'flat' device tree. This means that it
-reads directly from the device tree binary structure. It is called a flat
-device tree because nodes are listed one after the other, with the
-hierarchy detected by tags in the format.
-
-This document describes U-Boot's support for a 'live' device tree, meaning
-that the tree is loaded into a hierarchical data structure within U-Boot.
-
-
-Motivation
-----------
-
-The flat device tree has several advantages:
-
-- it is the format produced by the device tree compiler, so no translation
-is needed
-
-- it is fairly compact (e.g. there is no need for pointers)
-
-- it is accessed by the libfdt library, which is well tested and stable
-
-
-However the flat device tree does have some limitations. Adding new
-properties can involve copying large amounts of data around to make room.
-The overall tree has a fixed maximum size so sometimes the tree must be
-rebuilt in a new location to create more space. Even if not adding new
-properties or nodes, scanning the tree can be slow. For example, finding
-the parent of a node is a slow process. Reading from nodes involves a
-small amount parsing which takes a little time.
-
-Driver model scans the entire device tree sequentially on start-up which
-avoids the worst of the flat tree's limitations. But if the tree is to be
-modified at run-time, a live tree is much faster. Even if no modification
-is necessary, parsing the tree once and using a live tree from then on
-seems to save a little time.
-
-
-Implementation
---------------
-
-In U-Boot a live device tree ('livetree') is currently supported only
-after relocation. Therefore we need a mechanism to specify a device
-tree node regardless of whether it is in the flat tree or livetree.
-
-The 'ofnode' type provides this. An ofnode can point to either a flat tree
-node (when the live tree node is not yet set up) or a livetree node. The
-caller of an ofnode function does not need to worry about these details.
-
-The main users of the information in a device tree are drivers. These have
-a 'struct udevice *' which is attached to a device tree node. Therefore it
-makes sense to be able to read device tree properties using the
-'struct udevice *', rather than having to obtain the ofnode first.
-
-The 'dev_read_...()' interface provides this. It allows properties to be
-easily read from the device tree using only a device pointer. Under the
-hood it uses ofnode so it works with both flat and live device trees.
-
-
-Enabling livetree
------------------
-
-CONFIG_OF_LIVE enables livetree. When this option is enabled, the flat
-tree will be used in SPL and before relocation in U-Boot proper. Just
-before relocation a livetree is built, and this is used for U-Boot proper
-after relocation.
-
-Most checks for livetree use CONFIG_IS_ENABLED(OF_LIVE). This means that
-for SPL, the CONFIG_SPL_OF_LIVE option is checked. At present this does
-not exist, since SPL does not support livetree.
-
-
-Porting drivers
----------------
-
-Many existing drivers use the fdtdec interface to read device tree
-properties. This only works with a flat device tree. The drivers should be
-converted to use the dev_read_() interface.
-
-For example, the old code may be like this:
-
- struct udevice *bus;
- const void *blob = gd->fdt_blob;
- int node = dev_of_offset(bus);
-
- i2c_bus->regs = (struct i2c_ctlr *)devfdt_get_addr(dev);
- plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", 500000);
-
-The new code is:
-
- struct udevice *bus;
-
- i2c_bus->regs = (struct i2c_ctlr *)dev_read_addr(dev);
- plat->frequency = dev_read_u32_default(bus, "spi-max-frequency", 500000);
-
-The dev_read_...() interface is more convenient and works with both the
-flat and live device trees. See include/dm/read.h for a list of functions.
-
-Where properties must be read from sub-nodes or other nodes, you must fall
-back to using ofnode. For example, for old code like this:
-
- const void *blob = gd->fdt_blob;
- int subnode;
-
- fdt_for_each_subnode(subnode, blob, dev_of_offset(dev)) {
- freq = fdtdec_get_int(blob, node, "spi-max-frequency", 500000);
- ...
- }
-
-you should use:
-
- ofnode subnode;
-
- ofnode_for_each_subnode(subnode, dev_ofnode(dev)) {
- freq = ofnode_read_u32(node, "spi-max-frequency", 500000);
- ...
- }
-
-
-Useful ofnode functions
------------------------
-
-The internal data structures of the livetree are defined in include/dm/of.h :
-
- struct device_node - holds information about a device tree node
- struct property - holds information about a property within a node
-
-Nodes have pointers to their first property, their parent, their first child
-and their sibling. This allows nodes to be linked together in a hierarchical
-tree.
-
-Properties have pointers to the next property. This allows all properties of
-a node to be linked together in a chain.
-
-It should not be necessary to use these data structures in normal code. In
-particular, you should refrain from using functions which access the livetree
-directly, such as of_read_u32(). Use ofnode functions instead, to allow your
-code to work with a flat tree also.
-
-Some conversion functions are used internally. Generally these are not needed
-for driver code. Note that they will not work if called in the wrong context.
-For example it is invalid to call ofnode_to_no() when a flat tree is being
-used. Similarly it is not possible to call ofnode_to_offset() on a livetree
-node.
-
- ofnode_to_np() - converts ofnode to struct device_node *
- ofnode_to_offset() - converts ofnode to offset
-
- no_to_ofnode() - converts node pointer to ofnode
- offset_to_ofnode() - converts offset to ofnode
-
-
-Other useful functions:
-
- of_live_active() returns true if livetree is in use, false if flat tree
- ofnode_valid() return true if a given node is valid
- ofnode_is_np() returns true if a given node is a livetree node
- ofnode_equal() compares two ofnodes
- ofnode_null() returns a null ofnode (for which ofnode_valid() returns false)
-
-
-Phandles
---------
-
-There is full phandle support for live tree. All functions make use of
-struct ofnode_phandle_args, which has an ofnode within it. This supports both
-livetree and flat tree transparently. See for example
-ofnode_parse_phandle_with_args().
-
-
-Reading addresses
------------------
-
-You should use dev_read_addr() and friends to read addresses from device-tree
-nodes.
-
-
-fdtdec
-------
-
-The existing fdtdec interface will eventually be retired. Please try to avoid
-using it in new code.
-
-
-Modifying the livetree
-----------------------
-
-This is not currently supported. Once implemented it should provide a much
-more efficient implementation for modification of the device tree than using
-the flat tree.
-
-
-Internal implementation
------------------------
-
-The dev_read_...() functions have two implementations. When
-CONFIG_DM_DEV_READ_INLINE is enabled, these functions simply call the ofnode
-functions directly. This is useful when livetree is not enabled. The ofnode
-functions call ofnode_is_np(node) which will always return false if livetree
-is disabled, just falling back to flat tree code.
-
-This optimisation means that without livetree enabled, the dev_read_...() and
-ofnode interfaces do not noticeably add to code size.
-
-The CONFIG_DM_DEV_READ_INLINE option defaults to enabled when livetree is
-disabled.
-
-Most livetree code comes directly from Linux and is modified as little as
-possible. This is deliberate since this code is fairly stable and does what
-we want. Some features (such as get/put) are not supported. Internal macros
-take care of removing these features silently.
-
-Within the of_access.c file there are pointers to the alias node, the chosen
-node and the stdout-path alias.
-
-
-Errors
-------
-
-With a flat device tree, libfdt errors are returned (e.g. -FDT_ERR_NOTFOUND).
-For livetree normal 'errno' errors are returned (e.g. -ENOTFOUND). At present
-the ofnode and dev_read_...() functions return either one or other type of
-error. This is clearly not desirable. Once tests are added for all the
-functions this can be tidied up.
-
-
-Adding new access functions
----------------------------
-
-Adding a new function for device-tree access involves the following steps:
-
- - Add two dev_read() functions:
- - inline version in the read.h header file, which calls an ofnode
- function
- - standard version in the read.c file (or perhaps another file), which
- also calls an ofnode function
-
- The implementations of these functions can be the same. The purpose
- of the inline version is purely to reduce code size impact.
-
- - Add an ofnode function. This should call ofnode_is_np() to work out
- whether a livetree or flat tree is used. For the livetree it should
- call an of_...() function. For the flat tree it should call an
- fdt_...() function. The livetree version will be optimised out at
- compile time if livetree is not enabled.
-
- - Add an of_...() function for the livetree implementation. If a similar
- function is available in Linux, the implementation should be taken
- from there and modified as little as possible (generally not at all).
-
-
-Future work
------------
-
-Live tree support was introduced in U-Boot 2017.07. There is still quite a bit
-of work to do to flesh this out:
-
-- tests for all access functions
-- support for livetree modification
-- addition of more access functions as needed
-- support for livetree in SPL and before relocation (if desired)
-
-
---
-Simon Glass <sjg@chromium.org>
-5-Aug-17
diff --git a/doc/driver-model/migration.rst b/doc/driver-model/migration.rst
new file mode 100644
index 0000000..d1fc0e6
--- /dev/null
+++ b/doc/driver-model/migration.rst
@@ -0,0 +1,116 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Migration Schedule
+==================
+
+U-Boot has been migrating to a new driver model since its introduction in
+2014. This file describes the schedule for deprecation of pre-driver-model
+features.
+
+CONFIG_DM
+---------
+
+* Status: In progress
+* Deadline: 2020.01
+
+Starting with the 2010.01 release CONFIG_DM will be enabled for all boards.
+This does not concern CONFIG_DM_SPL and CONFIG_DM_TPL. The conversion date for
+these configuration items still needs to be defined.
+
+CONFIG_DM_MMC
+-------------
+
+* Status: In progress
+* Deadline: 2019.04
+
+The subsystem itself has been converted and maintainers should submit patches
+switching over to using CONFIG_DM_MMC and other base driver model options in
+time for inclusion in the 2019.04 rerelease.
+
+CONFIG_DM_USB
+-------------
+
+* Status: In progress
+* Deadline: 2019.07
+
+The subsystem itself has been converted along with many of the host controller
+and maintainers should submit patches switching over to using CONFIG_DM_USB and
+other base driver model options in time for inclusion in the 2019.07 rerelease.
+
+CONFIG_SATA
+-----------
+
+* Status: In progress
+* Deadline: 2019.07
+
+The subsystem itself has been converted along with many of the host controller
+and maintainers should submit patches switching over to using CONFIG_AHCI and
+other base driver model options in time for inclusion in the 2019.07 rerelease.
+
+CONFIG_BLK
+----------
+
+* Status: In progress
+* Deadline: 2019.07
+
+In concert with maintainers migrating their block device usage to the
+appropriate DM driver, CONFIG_BLK needs to be set as well. The final deadline
+here coincides with the final deadline for migration of the various block
+subsystems. At this point we will be able to audit and correct the logic in
+Kconfig around using CONFIG_PARTITIONS and CONFIG_HAVE_BLOCK_DEVICE and make
+use of CONFIG_BLK / CONFIG_SPL_BLK as needed.
+
+CONFIG_DM_SPI / CONFIG_DM_SPI_FLASH
+-----------------------------------
+
+Board Maintainers should submit the patches for enabling DM_SPI and DM_SPI_FLASH
+to move the migration with in the deadline.
+
+No dm conversion yet::
+
+ drivers/spi/fsl_espi.c
+ drivers/spi/lpc32xx_ssp.c
+ drivers/spi/sh_spi.c
+ drivers/spi/soft_spi_legacy.c
+
+* Status: In progress
+* Deadline: 2019.04
+
+Partially converted::
+
+ drivers/spi/davinci_spi.c
+ drivers/spi/fsl_dspi.c
+ drivers/spi/kirkwood_spi.c
+ drivers/spi/mxc_spi.c
+ drivers/spi/mxs_spi.c
+ drivers/spi/omap3_spi.c
+ drivers/spi/sh_qspi.c
+
+* Status: In progress
+* Deadline: 2019.07
+
+
+CONFIG_DM_PCI
+-------------
+Deadline: 2019.07
+
+The PCI subsystem has supported driver model since mid 2015. Maintainers should
+submit patches switching over to using CONFIG_DM_PCI and other base driver
+model options in time for inclusion in the 2019.07 release.
+
+
+CONFIG_DM_VIDEO
+---------------
+Deadline: 2019.07
+
+The video subsystem has supported driver model since early 2016. Maintainers
+should submit patches switching over to using CONFIG_DM_VIDEO and other base
+driver model options in time for inclusion in the 2019.07 release.
+
+CONFIG_DM_ETH
+-------------
+Deadline: 2020.07
+
+The network subsystem has supported the driver model since early 2015.
+Maintainers should submit patches switching over to using CONFIG_DM_ETH and
+other base driver model options in time for inclusion in the 2020.07 release.
diff --git a/doc/driver-model/of-plat.rst b/doc/driver-model/of-plat.rst
new file mode 100644
index 0000000..a38e58e
--- /dev/null
+++ b/doc/driver-model/of-plat.rst
@@ -0,0 +1,341 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Compiled-in Device Tree / Platform Data
+=======================================
+
+
+Introduction
+------------
+
+Device tree is the standard configuration method in U-Boot. It is used to
+define what devices are in the system and provide configuration information
+to these devices.
+
+The overhead of adding device tree access to U-Boot is fairly modest,
+approximately 3KB on Thumb 2 (plus the size of the DT itself). This means
+that in most cases it is best to use device tree for configuration.
+
+However there are some very constrained environments where U-Boot needs to
+work. These include SPL with severe memory limitations. For example, some
+SoCs require a 16KB SPL image which must include a full MMC stack. In this
+case the overhead of device tree access may be too great.
+
+It is possible to create platform data manually by defining C structures
+for it, and reference that data in a U_BOOT_DEVICE() declaration. This
+bypasses the use of device tree completely, effectively creating a parallel
+configuration mechanism. But it is an available option for SPL.
+
+As an alternative, a new 'of-platdata' feature is provided. This converts the
+device tree contents into C code which can be compiled into the SPL binary.
+This saves the 3KB of code overhead and perhaps a few hundred more bytes due
+to more efficient storage of the data.
+
+Note: Quite a bit of thought has gone into the design of this feature.
+However it still has many rough edges and comments and suggestions are
+strongly encouraged! Quite possibly there is a much better approach.
+
+
+Caveats
+-------
+
+There are many problems with this features. It should only be used when
+strictly necessary. Notable problems include:
+
+ - Device tree does not describe data types. But the C code must define a
+ type for each property. These are guessed using heuristics which
+ are wrong in several fairly common cases. For example an 8-byte value
+ is considered to be a 2-item integer array, and is byte-swapped. A
+ boolean value that is not present means 'false', but cannot be
+ included in the structures since there is generally no mention of it
+ in the device tree file.
+
+ - Naming of nodes and properties is automatic. This means that they follow
+ the naming in the device tree, which may result in C identifiers that
+ look a bit strange.
+
+ - It is not possible to find a value given a property name. Code must use
+ the associated C member variable directly in the code. This makes
+ the code less robust in the face of device-tree changes. It also
+ makes it very unlikely that your driver code will be useful for more
+ than one SoC. Even if the code is common, each SoC will end up with
+ a different C struct name, and a likely a different format for the
+ platform data.
+
+ - The platform data is provided to drivers as a C structure. The driver
+ must use the same structure to access the data. Since a driver
+ normally also supports device tree it must use #ifdef to separate
+ out this code, since the structures are only available in SPL.
+
+ - Correct relations between nodes are not implemented. This means that
+ parent/child relations (like bus device iteration) do not work yet.
+ Some phandles (those that are recognised as such) are converted into
+ a pointer to platform data. This pointer can potentially be used to
+ access the referenced device (by searching for the pointer value).
+ This feature is not yet implemented, however.
+
+
+How it works
+------------
+
+The feature is enabled by CONFIG OF_PLATDATA. This is only available in
+SPL/TPL and should be tested with:
+
+.. code-block:: c
+
+ #if CONFIG_IS_ENABLED(OF_PLATDATA)
+
+A new tool called 'dtoc' converts a device tree file either into a set of
+struct declarations, one for each compatible node, and a set of
+U_BOOT_DEVICE() declarations along with the actual platform data for each
+device. As an example, consider this MMC node:
+
+.. code-block:: none
+
+ sdmmc: dwmmc@ff0c0000 {
+ compatible = "rockchip,rk3288-dw-mshc";
+ clock-freq-min-max = <400000 150000000>;
+ clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
+ <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xff0c0000 0x4000>;
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ card-detect-delay = <200>;
+ disable-wp;
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
+ vmmc-supply = <&vcc_sd>;
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ };
+
+
+Some of these properties are dropped by U-Boot under control of the
+CONFIG_OF_SPL_REMOVE_PROPS option. The rest are processed. This will produce
+the following C struct declaration:
+
+.. code-block:: c
+
+ struct dtd_rockchip_rk3288_dw_mshc {
+ fdt32_t bus_width;
+ bool cap_mmc_highspeed;
+ bool cap_sd_highspeed;
+ fdt32_t card_detect_delay;
+ fdt32_t clock_freq_min_max[2];
+ struct phandle_1_arg clocks[4];
+ bool disable_wp;
+ fdt32_t fifo_depth;
+ fdt32_t interrupts[3];
+ fdt32_t num_slots;
+ fdt32_t reg[2];
+ fdt32_t vmmc_supply;
+ };
+
+and the following device declaration:
+
+.. code-block:: c
+
+ static struct dtd_rockchip_rk3288_dw_mshc dtv_dwmmc_at_ff0c0000 = {
+ .fifo_depth = 0x100,
+ .cap_sd_highspeed = true,
+ .interrupts = {0x0, 0x20, 0x4},
+ .clock_freq_min_max = {0x61a80, 0x8f0d180},
+ .vmmc_supply = 0xb,
+ .num_slots = 0x1,
+ .clocks = {{&dtv_clock_controller_at_ff760000, 456},
+ {&dtv_clock_controller_at_ff760000, 68},
+ {&dtv_clock_controller_at_ff760000, 114},
+ {&dtv_clock_controller_at_ff760000, 118}},
+ .cap_mmc_highspeed = true,
+ .disable_wp = true,
+ .bus_width = 0x4,
+ .u_boot_dm_pre_reloc = true,
+ .reg = {0xff0c0000, 0x4000},
+ .card_detect_delay = 0xc8,
+ };
+
+ U_BOOT_DEVICE(dwmmc_at_ff0c0000) = {
+ .name = "rockchip_rk3288_dw_mshc",
+ .platdata = &dtv_dwmmc_at_ff0c0000,
+ .platdata_size = sizeof(dtv_dwmmc_at_ff0c0000),
+ };
+
+The device is then instantiated at run-time and the platform data can be
+accessed using:
+
+.. code-block:: c
+
+ struct udevice *dev;
+ struct dtd_rockchip_rk3288_dw_mshc *plat = dev_get_platdata(dev);
+
+This avoids the code overhead of converting the device tree data to
+platform data in the driver. The ofdata_to_platdata() method should
+therefore do nothing in such a driver.
+
+Note that for the platform data to be matched with a driver, the 'name'
+property of the U_BOOT_DEVICE() declaration has to match a driver declared
+via U_BOOT_DRIVER(). This effectively means that a U_BOOT_DRIVER() with a
+'name' corresponding to the devicetree 'compatible' string (after converting
+it to a valid name for C) is needed, so a dedicated driver is required for
+each 'compatible' string.
+
+Where a node has multiple compatible strings, a #define is used to make them
+equivalent, e.g.:
+
+.. code-block:: c
+
+ #define dtd_rockchip_rk3299_dw_mshc dtd_rockchip_rk3288_dw_mshc
+
+
+Converting of-platdata to a useful form
+---------------------------------------
+
+Of course it would be possible to use the of-platdata directly in your driver
+whenever configuration information is required. However this means that the
+driver will not be able to support device tree, since the of-platdata
+structure is not available when device tree is used. It would make no sense
+to use this structure if device tree were available, since the structure has
+all the limitations metioned in caveats above.
+
+Therefore it is recommended that the of-platdata structure should be used
+only in the probe() method of your driver. It cannot be used in the
+ofdata_to_platdata() method since this is not called when platform data is
+already present.
+
+
+How to structure your driver
+----------------------------
+
+Drivers should always support device tree as an option. The of-platdata
+feature is intended as a add-on to existing drivers.
+
+Your driver should convert the platdata struct in its probe() method. The
+existing device tree decoding logic should be kept in the
+ofdata_to_platdata() method and wrapped with #if.
+
+For example:
+
+.. code-block:: c
+
+ #include <dt-structs.h>
+
+ struct mmc_platdata {
+ #if CONFIG_IS_ENABLED(OF_PLATDATA)
+ /* Put this first since driver model will copy the data here */
+ struct dtd_mmc dtplat;
+ #endif
+ /*
+ * Other fields can go here, to be filled in by decoding from
+ * the device tree (or the C structures when of-platdata is used).
+ */
+ int fifo_depth;
+ };
+
+ static int mmc_ofdata_to_platdata(struct udevice *dev)
+ {
+ #if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ /* Decode the device tree data */
+ struct mmc_platdata *plat = dev_get_platdata(dev);
+ const void *blob = gd->fdt_blob;
+ int node = dev_of_offset(dev);
+
+ plat->fifo_depth = fdtdec_get_int(blob, node, "fifo-depth", 0);
+ #endif
+
+ return 0;
+ }
+
+ static int mmc_probe(struct udevice *dev)
+ {
+ struct mmc_platdata *plat = dev_get_platdata(dev);
+
+ #if CONFIG_IS_ENABLED(OF_PLATDATA)
+ /* Decode the of-platdata from the C structures */
+ struct dtd_mmc *dtplat = &plat->dtplat;
+
+ plat->fifo_depth = dtplat->fifo_depth;
+ #endif
+ /* Set up the device from the plat data */
+ writel(plat->fifo_depth, ...)
+ }
+
+ static const struct udevice_id mmc_ids[] = {
+ { .compatible = "vendor,mmc" },
+ { }
+ };
+
+ U_BOOT_DRIVER(mmc_drv) = {
+ .name = "mmc",
+ .id = UCLASS_MMC,
+ .of_match = mmc_ids,
+ .ofdata_to_platdata = mmc_ofdata_to_platdata,
+ .probe = mmc_probe,
+ .priv_auto_alloc_size = sizeof(struct mmc_priv),
+ .platdata_auto_alloc_size = sizeof(struct mmc_platdata),
+ };
+
+
+In the case where SPL_OF_PLATDATA is enabled, platdata_auto_alloc_size is
+still used to allocate space for the platform data. This is different from
+the normal behaviour and is triggered by the use of of-platdata (strictly
+speaking it is a non-zero platdata_size which triggers this).
+
+The of-platdata struct contents is copied from the C structure data to the
+start of the newly allocated area. In the case where device tree is used,
+the platform data is allocated, and starts zeroed. In this case the
+ofdata_to_platdata() method should still set up the platform data (and the
+of-platdata struct will not be present).
+
+SPL must use either of-platdata or device tree. Drivers cannot use both at
+the same time, but they must support device tree. Supporting of-platdata is
+optional.
+
+The device tree becomes in accessible when CONFIG_SPL_OF_PLATDATA is enabled,
+since the device-tree access code is not compiled in. A corollary is that
+a board can only move to using of-platdata if all the drivers it uses support
+it. There would be little point in having some drivers require the device
+tree data, since then libfdt would still be needed for those drivers and
+there would be no code-size benefit.
+
+Internals
+---------
+
+The dt-structs.h file includes the generated file
+(include/generated//dt-structs.h) if CONFIG_SPL_OF_PLATDATA is enabled.
+Otherwise (such as in U-Boot proper) these structs are not available. This
+prevents them being used inadvertently. All usage must be bracketed with
+#if CONFIG_IS_ENABLED(OF_PLATDATA).
+
+The dt-platdata.c file contains the device declarations and is is built in
+spl/dt-platdata.c.
+
+The beginnings of a libfdt Python module are provided. So far this only
+implements a subset of the features.
+
+The 'swig' tool is needed to build the libfdt Python module. If this is not
+found then the Python model is not used and a fallback is used instead, which
+makes use of fdtget.
+
+
+Credits
+-------
+
+This is an implementation of an idea by Tom Rini <trini@konsulko.com>.
+
+
+Future work
+-----------
+- Consider programmatically reading binding files instead of device tree
+ contents
+- Complete the phandle feature
+- Move to using a full Python libfdt module
+
+
+.. Simon Glass <sjg@chromium.org>
+.. Google, Inc
+.. 6/6/16
+.. Updated Independence Day 2016
diff --git a/doc/driver-model/of-plat.txt b/doc/driver-model/of-plat.txt
deleted file mode 100644
index 0109ec5..0000000
--- a/doc/driver-model/of-plat.txt
+++ /dev/null
@@ -1,324 +0,0 @@
-Driver Model Compiled-in Device Tree / Platform Data
-====================================================
-
-
-Introduction
-------------
-
-Device tree is the standard configuration method in U-Boot. It is used to
-define what devices are in the system and provide configuration information
-to these devices.
-
-The overhead of adding device tree access to U-Boot is fairly modest,
-approximately 3KB on Thumb 2 (plus the size of the DT itself). This means
-that in most cases it is best to use device tree for configuration.
-
-However there are some very constrained environments where U-Boot needs to
-work. These include SPL with severe memory limitations. For example, some
-SoCs require a 16KB SPL image which must include a full MMC stack. In this
-case the overhead of device tree access may be too great.
-
-It is possible to create platform data manually by defining C structures
-for it, and reference that data in a U_BOOT_DEVICE() declaration. This
-bypasses the use of device tree completely, effectively creating a parallel
-configuration mechanism. But it is an available option for SPL.
-
-As an alternative, a new 'of-platdata' feature is provided. This converts the
-device tree contents into C code which can be compiled into the SPL binary.
-This saves the 3KB of code overhead and perhaps a few hundred more bytes due
-to more efficient storage of the data.
-
-Note: Quite a bit of thought has gone into the design of this feature.
-However it still has many rough edges and comments and suggestions are
-strongly encouraged! Quite possibly there is a much better approach.
-
-
-Caveats
--------
-
-There are many problems with this features. It should only be used when
-strictly necessary. Notable problems include:
-
- - Device tree does not describe data types. But the C code must define a
- type for each property. These are guessed using heuristics which
- are wrong in several fairly common cases. For example an 8-byte value
- is considered to be a 2-item integer array, and is byte-swapped. A
- boolean value that is not present means 'false', but cannot be
- included in the structures since there is generally no mention of it
- in the device tree file.
-
- - Naming of nodes and properties is automatic. This means that they follow
- the naming in the device tree, which may result in C identifiers that
- look a bit strange.
-
- - It is not possible to find a value given a property name. Code must use
- the associated C member variable directly in the code. This makes
- the code less robust in the face of device-tree changes. It also
- makes it very unlikely that your driver code will be useful for more
- than one SoC. Even if the code is common, each SoC will end up with
- a different C struct name, and a likely a different format for the
- platform data.
-
- - The platform data is provided to drivers as a C structure. The driver
- must use the same structure to access the data. Since a driver
- normally also supports device tree it must use #ifdef to separate
- out this code, since the structures are only available in SPL.
-
- - Correct relations between nodes are not implemented. This means that
- parent/child relations (like bus device iteration) do not work yet.
- Some phandles (those that are recognised as such) are converted into
- a pointer to platform data. This pointer can potentially be used to
- access the referenced device (by searching for the pointer value).
- This feature is not yet implemented, however.
-
-
-How it works
-------------
-
-The feature is enabled by CONFIG OF_PLATDATA. This is only available in
-SPL/TPL and should be tested with:
-
- #if CONFIG_IS_ENABLED(OF_PLATDATA)
-
-A new tool called 'dtoc' converts a device tree file either into a set of
-struct declarations, one for each compatible node, and a set of
-U_BOOT_DEVICE() declarations along with the actual platform data for each
-device. As an example, consider this MMC node:
-
- sdmmc: dwmmc@ff0c0000 {
- compatible = "rockchip,rk3288-dw-mshc";
- clock-freq-min-max = <400000 150000000>;
- clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
- <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
- clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
- fifo-depth = <0x100>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0xff0c0000 0x4000>;
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- card-detect-delay = <200>;
- disable-wp;
- num-slots = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
- vmmc-supply = <&vcc_sd>;
- status = "okay";
- u-boot,dm-pre-reloc;
- };
-
-
-Some of these properties are dropped by U-Boot under control of the
-CONFIG_OF_SPL_REMOVE_PROPS option. The rest are processed. This will produce
-the following C struct declaration:
-
-struct dtd_rockchip_rk3288_dw_mshc {
- fdt32_t bus_width;
- bool cap_mmc_highspeed;
- bool cap_sd_highspeed;
- fdt32_t card_detect_delay;
- fdt32_t clock_freq_min_max[2];
- struct phandle_1_arg clocks[4];
- bool disable_wp;
- fdt32_t fifo_depth;
- fdt32_t interrupts[3];
- fdt32_t num_slots;
- fdt32_t reg[2];
- fdt32_t vmmc_supply;
-};
-
-and the following device declaration:
-
-static struct dtd_rockchip_rk3288_dw_mshc dtv_dwmmc_at_ff0c0000 = {
- .fifo_depth = 0x100,
- .cap_sd_highspeed = true,
- .interrupts = {0x0, 0x20, 0x4},
- .clock_freq_min_max = {0x61a80, 0x8f0d180},
- .vmmc_supply = 0xb,
- .num_slots = 0x1,
- .clocks = {{&dtv_clock_controller_at_ff760000, 456},
- {&dtv_clock_controller_at_ff760000, 68},
- {&dtv_clock_controller_at_ff760000, 114},
- {&dtv_clock_controller_at_ff760000, 118}},
- .cap_mmc_highspeed = true,
- .disable_wp = true,
- .bus_width = 0x4,
- .u_boot_dm_pre_reloc = true,
- .reg = {0xff0c0000, 0x4000},
- .card_detect_delay = 0xc8,
-};
-U_BOOT_DEVICE(dwmmc_at_ff0c0000) = {
- .name = "rockchip_rk3288_dw_mshc",
- .platdata = &dtv_dwmmc_at_ff0c0000,
- .platdata_size = sizeof(dtv_dwmmc_at_ff0c0000),
-};
-
-The device is then instantiated at run-time and the platform data can be
-accessed using:
-
- struct udevice *dev;
- struct dtd_rockchip_rk3288_dw_mshc *plat = dev_get_platdata(dev);
-
-This avoids the code overhead of converting the device tree data to
-platform data in the driver. The ofdata_to_platdata() method should
-therefore do nothing in such a driver.
-
-Note that for the platform data to be matched with a driver, the 'name'
-property of the U_BOOT_DEVICE() declaration has to match a driver declared
-via U_BOOT_DRIVER(). This effectively means that a U_BOOT_DRIVER() with a
-'name' corresponding to the devicetree 'compatible' string (after converting
-it to a valid name for C) is needed, so a dedicated driver is required for
-each 'compatible' string.
-
-Where a node has multiple compatible strings, a #define is used to make them
-equivalent, e.g.:
-
-#define dtd_rockchip_rk3299_dw_mshc dtd_rockchip_rk3288_dw_mshc
-
-
-Converting of-platdata to a useful form
----------------------------------------
-
-Of course it would be possible to use the of-platdata directly in your driver
-whenever configuration information is required. However this means that the
-driver will not be able to support device tree, since the of-platdata
-structure is not available when device tree is used. It would make no sense
-to use this structure if device tree were available, since the structure has
-all the limitations metioned in caveats above.
-
-Therefore it is recommended that the of-platdata structure should be used
-only in the probe() method of your driver. It cannot be used in the
-ofdata_to_platdata() method since this is not called when platform data is
-already present.
-
-
-How to structure your driver
-----------------------------
-
-Drivers should always support device tree as an option. The of-platdata
-feature is intended as a add-on to existing drivers.
-
-Your driver should convert the platdata struct in its probe() method. The
-existing device tree decoding logic should be kept in the
-ofdata_to_platdata() method and wrapped with #if.
-
-For example:
-
- #include <dt-structs.h>
-
- struct mmc_platdata {
- #if CONFIG_IS_ENABLED(SPL_OF_PLATDATA)
- /* Put this first since driver model will copy the data here */
- struct dtd_mmc dtplat;
- #endif
- /*
- * Other fields can go here, to be filled in by decoding from
- * the device tree (or the C structures when of-platdata is used).
- */
- int fifo_depth;
- };
-
- static int mmc_ofdata_to_platdata(struct udevice *dev)
- {
- #if !CONFIG_IS_ENABLED(SPL_OF_PLATDATA)
- /* Decode the device tree data */
- struct mmc_platdata *plat = dev_get_platdata(dev);
- const void *blob = gd->fdt_blob;
- int node = dev_of_offset(dev);
-
- plat->fifo_depth = fdtdec_get_int(blob, node, "fifo-depth", 0);
- #endif
-
- return 0;
- }
-
- static int mmc_probe(struct udevice *dev)
- {
- struct mmc_platdata *plat = dev_get_platdata(dev);
-
- #if CONFIG_IS_ENABLED(SPL_OF_PLATDATA)
- /* Decode the of-platdata from the C structures */
- struct dtd_mmc *dtplat = &plat->dtplat;
-
- plat->fifo_depth = dtplat->fifo_depth;
- #endif
- /* Set up the device from the plat data */
- writel(plat->fifo_depth, ...)
- }
-
- static const struct udevice_id mmc_ids[] = {
- { .compatible = "vendor,mmc" },
- { }
- };
-
- U_BOOT_DRIVER(mmc_drv) = {
- .name = "mmc",
- .id = UCLASS_MMC,
- .of_match = mmc_ids,
- .ofdata_to_platdata = mmc_ofdata_to_platdata,
- .probe = mmc_probe,
- .priv_auto_alloc_size = sizeof(struct mmc_priv),
- .platdata_auto_alloc_size = sizeof(struct mmc_platdata),
- };
-
-
-In the case where SPL_OF_PLATDATA is enabled, platdata_auto_alloc_size is
-still used to allocate space for the platform data. This is different from
-the normal behaviour and is triggered by the use of of-platdata (strictly
-speaking it is a non-zero platdata_size which triggers this).
-
-The of-platdata struct contents is copied from the C structure data to the
-start of the newly allocated area. In the case where device tree is used,
-the platform data is allocated, and starts zeroed. In this case the
-ofdata_to_platdata() method should still set up the platform data (and the
-of-platdata struct will not be present).
-
-SPL must use either of-platdata or device tree. Drivers cannot use both at
-the same time, but they must support device tree. Supporting of-platdata is
-optional.
-
-The device tree becomes in accessible when CONFIG_SPL_OF_PLATDATA is enabled,
-since the device-tree access code is not compiled in. A corollary is that
-a board can only move to using of-platdata if all the drivers it uses support
-it. There would be little point in having some drivers require the device
-tree data, since then libfdt would still be needed for those drivers and
-there would be no code-size benefit.
-
-Internals
----------
-
-The dt-structs.h file includes the generated file
-(include/generated//dt-structs.h) if CONFIG_SPL_OF_PLATDATA is enabled.
-Otherwise (such as in U-Boot proper) these structs are not available. This
-prevents them being used inadvertently. All usage must be bracketed with
-#if CONFIG_IS_ENABLED(SPL_OF_PLATDATA).
-
-The dt-platdata.c file contains the device declarations and is is built in
-spl/dt-platdata.c.
-
-The beginnings of a libfdt Python module are provided. So far this only
-implements a subset of the features.
-
-The 'swig' tool is needed to build the libfdt Python module. If this is not
-found then the Python model is not used and a fallback is used instead, which
-makes use of fdtget.
-
-
-Credits
--------
-
-This is an implementation of an idea by Tom Rini <trini@konsulko.com>.
-
-
-Future work
------------
-- Consider programmatically reading binding files instead of device tree
- contents
-- Complete the phandle feature
-- Move to using a full Python libfdt module
-
---
-Simon Glass <sjg@chromium.org>
-Google, Inc
-6/6/16
-Updated Independence Day 2016
diff --git a/doc/driver-model/pci-info.rst b/doc/driver-model/pci-info.rst
new file mode 100644
index 0000000..d93ab8b
--- /dev/null
+++ b/doc/driver-model/pci-info.rst
@@ -0,0 +1,170 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+PCI with Driver Model
+=====================
+
+How busses are scanned
+----------------------
+
+Any config read will end up at pci_read_config(). This uses
+uclass_get_device_by_seq() to get the PCI bus for a particular bus number.
+Bus number 0 will need to be requested first, and the alias in the device
+tree file will point to the correct device::
+
+ aliases {
+ pci0 = &pci;
+ };
+
+ pci: pci-controller {
+ compatible = "sandbox,pci";
+ ...
+ };
+
+
+If there is no alias the devices will be numbered sequentially in the device
+tree.
+
+The call to uclass_get_device() will cause the PCI bus to be probed.
+This does a scan of the bus to locate available devices. These devices are
+bound to their appropriate driver if available. If there is no driver, then
+they are bound to a generic PCI driver which does nothing.
+
+After probing a bus, the available devices will appear in the device tree
+under that bus.
+
+Note that this is all done on a lazy basis, as needed, so until something is
+touched on PCI (eg: a call to pci_find_devices()) it will not be probed.
+
+PCI devices can appear in the flattened device tree. If they do, their node
+often contains extra information which cannot be derived from the PCI IDs or
+PCI class of the device. Each PCI device node must have a <reg> property, as
+defined by the IEEE Std 1275-1994 PCI bus binding document v2.1. Compatible
+string list is optional and generally not needed, since PCI is discoverable
+bus, albeit there are justified exceptions. If the compatible string is
+present, matching on it takes precedence over PCI IDs and PCI classes.
+
+Note we must describe PCI devices with the same bus hierarchy as the
+hardware, otherwise driver model cannot detect the correct parent/children
+relationship during PCI bus enumeration thus PCI devices won't be bound to
+their drivers accordingly. A working example like below::
+
+ pci {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ compatible = "pci-x86";
+ u-boot,dm-pre-reloc;
+ ranges = <0x02000000 0x0 0x40000000 0x40000000 0 0x80000000
+ 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
+ 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
+
+ pcie@17,0 {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ compatible = "pci-bridge";
+ u-boot,dm-pre-reloc;
+ reg = <0x0000b800 0x0 0x0 0x0 0x0>;
+
+ topcliff@0,0 {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ compatible = "pci-bridge";
+ u-boot,dm-pre-reloc;
+ reg = <0x00010000 0x0 0x0 0x0 0x0>;
+
+ pciuart0: uart@a,1 {
+ compatible = "pci8086,8811.00",
+ "pci8086,8811",
+ "pciclass,070002",
+ "pciclass,0700",
+ "x86-uart";
+ u-boot,dm-pre-reloc;
+ reg = <0x00025100 0x0 0x0 0x0 0x0
+ 0x01025110 0x0 0x0 0x0 0x0>;
+ ......
+ };
+
+ ......
+ };
+ };
+
+ ......
+ };
+
+In this example, the root PCI bus node is the "/pci" which matches "pci-x86"
+driver. It has a subnode "pcie@17,0" with driver "pci-bridge". "pcie@17,0"
+also has subnode "topcliff@0,0" which is a "pci-bridge" too. Under that bridge,
+a PCI UART device "uart@a,1" is described. This exactly reflects the hardware
+bus hierarchy: on the root PCI bus, there is a PCIe root port which connects
+to a downstream device Topcliff chipset. Inside Topcliff chipset, it has a
+PCIe-to-PCI bridge and all the chipset integrated devices like the PCI UART
+device are on the PCI bus. Like other devices in the device tree, if we want
+to bind PCI devices before relocation, "u-boot,dm-pre-reloc" must be declared
+in each of these nodes.
+
+If PCI devices are not listed in the device tree, U_BOOT_PCI_DEVICE can be used
+to specify the driver to use for the device. The device tree takes precedence
+over U_BOOT_PCI_DEVICE. Plese note with U_BOOT_PCI_DEVICE, only drivers with
+DM_FLAG_PRE_RELOC will be bound before relocation. If neither device tree nor
+U_BOOT_PCI_DEVICE is provided, the built-in driver (either pci_bridge_drv or
+pci_generic_drv) will be used.
+
+
+Sandbox
+-------
+
+With sandbox we need a device emulator for each device on the bus since there
+is no real PCI bus. This works by looking in the device tree node for a
+driver. For example::
+
+
+ pci@1f,0 {
+ compatible = "pci-generic";
+ reg = <0xf800 0 0 0 0>;
+ emul@1f,0 {
+ compatible = "sandbox,swap-case";
+ };
+ };
+
+This means that there is a 'sandbox,swap-case' driver at that bus position.
+Note that the first cell in the 'reg' value is the bus/device/function. See
+PCI_BDF() for the encoding (it is also specified in the IEEE Std 1275-1994
+PCI bus binding document, v2.1)
+
+When this bus is scanned we will end up with something like this::
+
+ `- * pci-controller @ 05c660c8, 0
+ `- pci@1f,0 @ 05c661c8, 63488
+ `- emul@1f,0 @ 05c662c8
+
+When accesses go to the pci@1f,0 device they are forwarded to its child, the
+emulator.
+
+The sandbox PCI drivers also support dynamic driver binding, allowing device
+driver to declare the driver binding information via U_BOOT_PCI_DEVICE(),
+eliminating the need to provide any device tree node under the host controller
+node. It is required a "sandbox,dev-info" property must be provided in the
+host controller node for this functionality to work.
+
+.. code-block:: none
+
+ pci1: pci-controller1 {
+ compatible = "sandbox,pci";
+ ...
+ sandbox,dev-info = <0x08 0x00 0x1234 0x5678
+ 0x0c 0x00 0x1234 0x5678>;
+ };
+
+The "sandbox,dev-info" property specifies all dynamic PCI devices on this bus.
+Each dynamic PCI device is encoded as 4 cells a group. The first and second
+cells are PCI device number and function number respectively. The third and
+fourth cells are PCI vendor ID and device ID respectively.
+
+When this bus is scanned we will end up with something like this::
+
+ pci [ + ] pci_sandbo |-- pci-controller1
+ pci_emul [ ] sandbox_sw | |-- sandbox_swap_case_emul
+ pci_emul [ ] sandbox_sw | `-- sandbox_swap_case_emul
+
+Note the difference from the statically declared device nodes is that the
+device is directly attached to the host controller, instead of via a container
+device like pci@1f,0.
diff --git a/doc/driver-model/pci-info.txt b/doc/driver-model/pci-info.txt
deleted file mode 100644
index 14364c5..0000000
--- a/doc/driver-model/pci-info.txt
+++ /dev/null
@@ -1,167 +0,0 @@
-PCI with Driver Model
-=====================
-
-How busses are scanned
-----------------------
-
-Any config read will end up at pci_read_config(). This uses
-uclass_get_device_by_seq() to get the PCI bus for a particular bus number.
-Bus number 0 will need to be requested first, and the alias in the device
-tree file will point to the correct device:
-
-
- aliases {
- pci0 = &pci;
- };
-
- pci: pci-controller {
- compatible = "sandbox,pci";
- ...
- };
-
-
-If there is no alias the devices will be numbered sequentially in the device
-tree.
-
-The call to uclass_get_device() will cause the PCI bus to be probed.
-This does a scan of the bus to locate available devices. These devices are
-bound to their appropriate driver if available. If there is no driver, then
-they are bound to a generic PCI driver which does nothing.
-
-After probing a bus, the available devices will appear in the device tree
-under that bus.
-
-Note that this is all done on a lazy basis, as needed, so until something is
-touched on PCI (eg: a call to pci_find_devices()) it will not be probed.
-
-PCI devices can appear in the flattened device tree. If they do, their node
-often contains extra information which cannot be derived from the PCI IDs or
-PCI class of the device. Each PCI device node must have a <reg> property, as
-defined by the IEEE Std 1275-1994 PCI bus binding document v2.1. Compatible
-string list is optional and generally not needed, since PCI is discoverable
-bus, albeit there are justified exceptions. If the compatible string is
-present, matching on it takes precedence over PCI IDs and PCI classes.
-
-Note we must describe PCI devices with the same bus hierarchy as the
-hardware, otherwise driver model cannot detect the correct parent/children
-relationship during PCI bus enumeration thus PCI devices won't be bound to
-their drivers accordingly. A working example like below:
-
- pci {
- #address-cells = <3>;
- #size-cells = <2>;
- compatible = "pci-x86";
- u-boot,dm-pre-reloc;
- ranges = <0x02000000 0x0 0x40000000 0x40000000 0 0x80000000
- 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
- 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
-
- pcie@17,0 {
- #address-cells = <3>;
- #size-cells = <2>;
- compatible = "pci-bridge";
- u-boot,dm-pre-reloc;
- reg = <0x0000b800 0x0 0x0 0x0 0x0>;
-
- topcliff@0,0 {
- #address-cells = <3>;
- #size-cells = <2>;
- compatible = "pci-bridge";
- u-boot,dm-pre-reloc;
- reg = <0x00010000 0x0 0x0 0x0 0x0>;
-
- pciuart0: uart@a,1 {
- compatible = "pci8086,8811.00",
- "pci8086,8811",
- "pciclass,070002",
- "pciclass,0700",
- "x86-uart";
- u-boot,dm-pre-reloc;
- reg = <0x00025100 0x0 0x0 0x0 0x0
- 0x01025110 0x0 0x0 0x0 0x0>;
- ......
- };
-
- ......
- };
- };
-
- ......
- };
-
-In this example, the root PCI bus node is the "/pci" which matches "pci-x86"
-driver. It has a subnode "pcie@17,0" with driver "pci-bridge". "pcie@17,0"
-also has subnode "topcliff@0,0" which is a "pci-bridge" too. Under that bridge,
-a PCI UART device "uart@a,1" is described. This exactly reflects the hardware
-bus hierarchy: on the root PCI bus, there is a PCIe root port which connects
-to a downstream device Topcliff chipset. Inside Topcliff chipset, it has a
-PCIe-to-PCI bridge and all the chipset integrated devices like the PCI UART
-device are on the PCI bus. Like other devices in the device tree, if we want
-to bind PCI devices before relocation, "u-boot,dm-pre-reloc" must be declared
-in each of these nodes.
-
-If PCI devices are not listed in the device tree, U_BOOT_PCI_DEVICE can be used
-to specify the driver to use for the device. The device tree takes precedence
-over U_BOOT_PCI_DEVICE. Plese note with U_BOOT_PCI_DEVICE, only drivers with
-DM_FLAG_PRE_RELOC will be bound before relocation. If neither device tree nor
-U_BOOT_PCI_DEVICE is provided, the built-in driver (either pci_bridge_drv or
-pci_generic_drv) will be used.
-
-
-Sandbox
--------
-
-With sandbox we need a device emulator for each device on the bus since there
-is no real PCI bus. This works by looking in the device tree node for a
-driver. For example:
-
-
- pci@1f,0 {
- compatible = "pci-generic";
- reg = <0xf800 0 0 0 0>;
- emul@1f,0 {
- compatible = "sandbox,swap-case";
- };
- };
-
-This means that there is a 'sandbox,swap-case' driver at that bus position.
-Note that the first cell in the 'reg' value is the bus/device/function. See
-PCI_BDF() for the encoding (it is also specified in the IEEE Std 1275-1994
-PCI bus binding document, v2.1)
-
-When this bus is scanned we will end up with something like this:
-
-`- * pci-controller @ 05c660c8, 0
- `- pci@1f,0 @ 05c661c8, 63488
- `- emul@1f,0 @ 05c662c8
-
-When accesses go to the pci@1f,0 device they are forwarded to its child, the
-emulator.
-
-The sandbox PCI drivers also support dynamic driver binding, allowing device
-driver to declare the driver binding information via U_BOOT_PCI_DEVICE(),
-eliminating the need to provide any device tree node under the host controller
-node. It is required a "sandbox,dev-info" property must be provided in the
-host controller node for this functionality to work.
-
- pci1: pci-controller1 {
- compatible = "sandbox,pci";
- ...
- sandbox,dev-info = <0x08 0x00 0x1234 0x5678
- 0x0c 0x00 0x1234 0x5678>;
- };
-
-The "sandbox,dev-info" property specifies all dynamic PCI devices on this bus.
-Each dynamic PCI device is encoded as 4 cells a group. The first and second
-cells are PCI device number and function number respectively. The third and
-fourth cells are PCI vendor ID and device ID respectively.
-
-When this bus is scanned we will end up with something like this:
-
- pci [ + ] pci_sandbo |-- pci-controller1
- pci_emul [ ] sandbox_sw | |-- sandbox_swap_case_emul
- pci_emul [ ] sandbox_sw | `-- sandbox_swap_case_emul
-
-Note the difference from the statically declared device nodes is that the
-device is directly attached to the host controller, instead of via a container
-device like pci@1f,0.
diff --git a/doc/driver-model/pmic-framework.rst b/doc/driver-model/pmic-framework.rst
new file mode 100644
index 0000000..d24a1ba
--- /dev/null
+++ b/doc/driver-model/pmic-framework.rst
@@ -0,0 +1,143 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. (C) Copyright 2014-2015 Samsung Electronics
+.. sectionauthor:: Przemyslaw Marczak <p.marczak@samsung.com>
+
+PMIC framework based on Driver Model
+====================================
+
+Introduction
+------------
+This is an introduction to driver-model multi uclass PMIC IC's support.
+At present it's based on two uclass types:
+
+UCLASS_PMIC:
+ basic uclass type for PMIC I/O, which provides common
+ read/write interface.
+UCLASS_REGULATOR:
+ additional uclass type for specific PMIC features, which are
+ Voltage/Current regulators.
+
+New files:
+
+UCLASS_PMIC:
+ - drivers/power/pmic/pmic-uclass.c
+ - include/power/pmic.h
+UCLASS_REGULATOR:
+ - drivers/power/regulator/regulator-uclass.c
+ - include/power/regulator.h
+
+Commands:
+- common/cmd_pmic.c
+- common/cmd_regulator.c
+
+How doees it work
+-----------------
+The Power Management Integrated Circuits (PMIC) are used in embedded systems
+to provide stable, precise and specific voltage power source with over-voltage
+and thermal protection circuits.
+
+The single PMIC can provide various functions by single or multiple interfaces,
+like in the example below::
+
+ -- SoC
+ |
+ | ______________________________________
+ | BUS 0 | Multi interface PMIC IC |--> LDO out 1
+ | e.g.I2C0 | |--> LDO out N
+ |-----------|---- PMIC device 0 (READ/WRITE ops) |
+ | or SPI0 | |_ REGULATOR device (ldo/... ops) |--> BUCK out 1
+ | | |_ CHARGER device (charger ops) |--> BUCK out M
+ | | |_ MUIC device (microUSB con ops) |
+ | BUS 1 | |_ ... |---> BATTERY
+ | e.g.I2C1 | |
+ |-----------|---- PMIC device 1 (READ/WRITE ops) |---> USB in 1
+ . or SPI1 | |_ RTC device (rtc ops) |---> USB in 2
+ . |______________________________________|---> USB out
+ .
+
+Since U-Boot provides driver model features for I2C and SPI bus drivers,
+the PMIC devices should also support this. By the pmic and regulator API's,
+PMIC drivers can simply provide a common functions, for multi-interface and
+and multi-instance device support.
+
+Basic design assumptions:
+
+- Common I/O API:
+ UCLASS_PMIC. For the multi-function PMIC devices, this can be used as
+ parent I/O device for each IC's interface. Then, each children uses the
+ same dev for read/write.
+
+- Common regulator API:
+ UCLASS_REGULATOR. For driving the regulator attributes, auto setting
+ function or command line interface, based on kernel-style regulator device
+ tree constraints.
+
+For simple implementations, regulator drivers are not required, so the code can
+use pmic read/write directly.
+
+Pmic uclass
+-----------
+The basic information:
+
+* Uclass: 'UCLASS_PMIC'
+* Header: 'include/power/pmic.h'
+* Core: 'drivers/power/pmic/pmic-uclass.c' (config 'CONFIG_DM_PMIC')
+* Command: 'common/cmd_pmic.c' (config 'CONFIG_CMD_PMIC')
+* Example: 'drivers/power/pmic/max77686.c'
+
+For detailed API description, please refer to the header file.
+
+As an example of the pmic driver, please refer to the MAX77686 driver.
+
+Please pay attention for the driver's bind() method. Exactly the function call:
+'pmic_bind_children()', which is used to bind the regulators by using the array
+of regulator's node, compatible prefixes.
+
+The 'pmic; command also supports the new API. So the pmic command can be enabled
+by adding CONFIG_CMD_PMIC.
+The new pmic command allows to:
+- list pmic devices
+- choose the current device (like the mmc command)
+- read or write the pmic register
+- dump all pmic registers
+
+This command can use only UCLASS_PMIC devices, since this uclass is designed
+for pmic I/O operations only.
+
+For more information, please refer to the core file.
+
+Regulator uclass
+----------------
+The basic information:
+
+* Uclass: 'UCLASS_REGULATOR'
+
+* Header: 'include/power/regulator.h'
+
+* Core: 'drivers/power/regulator/regulator-uclass.c'
+ (config 'CONFIG_DM_REGULATOR')
+
+* Binding: 'doc/device-tree-bindings/regulator/regulator.txt'
+
+* Command: 'common/cmd_regulator.c' (config 'CONFIG_CMD_REGULATOR')
+
+* Example: 'drivers/power/regulator/max77686.c'
+ 'drivers/power/pmic/max77686.c' (required I/O driver for the above)
+
+* Example: 'drivers/power/regulator/fixed.c'
+ (config 'CONFIG_DM_REGULATOR_FIXED')
+
+For detailed API description, please refer to the header file.
+
+For the example regulator driver, please refer to the MAX77686 regulator driver,
+but this driver can't operate without pmic's example driver, which provides an
+I/O interface for MAX77686 regulator.
+
+The second example is a fixed Voltage/Current regulator for a common use.
+
+The 'regulator' command also supports the new API. The command allow:
+- list regulator devices
+- choose the current device (like the mmc command)
+- do all regulator-specific operations
+
+For more information, please refer to the command file.
diff --git a/doc/driver-model/pmic-framework.txt b/doc/driver-model/pmic-framework.txt
deleted file mode 100644
index 95b1a66..0000000
--- a/doc/driver-model/pmic-framework.txt
+++ /dev/null
@@ -1,140 +0,0 @@
-#
-# (C) Copyright 2014-2015 Samsung Electronics
-# Przemyslaw Marczak <p.marczak@samsung.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PMIC framework based on Driver Model
-====================================
-TOC:
-1. Introduction
-2. How does it work
-3. Pmic uclass
-4. Regulator uclass
-
-1. Introduction
-===============
-This is an introduction to driver-model multi uclass PMIC IC's support.
-At present it's based on two uclass types:
-- UCLASS_PMIC - basic uclass type for PMIC I/O, which provides common
- read/write interface.
-- UCLASS_REGULATOR - additional uclass type for specific PMIC features,
- which are Voltage/Current regulators.
-
-New files:
-UCLASS_PMIC:
-- drivers/power/pmic/pmic-uclass.c
-- include/power/pmic.h
-UCLASS_REGULATOR:
-- drivers/power/regulator/regulator-uclass.c
-- include/power/regulator.h
-
-Commands:
-- common/cmd_pmic.c
-- common/cmd_regulator.c
-
-2. How doees it work
-====================
-The Power Management Integrated Circuits (PMIC) are used in embedded systems
-to provide stable, precise and specific voltage power source with over-voltage
-and thermal protection circuits.
-
-The single PMIC can provide various functions by single or multiple interfaces,
-like in the example below.
-
--- SoC
- |
- | ______________________________________
- | BUS 0 | Multi interface PMIC IC |--> LDO out 1
- | e.g.I2C0 | |--> LDO out N
- |-----------|---- PMIC device 0 (READ/WRITE ops) |
- | or SPI0 | |_ REGULATOR device (ldo/... ops) |--> BUCK out 1
- | | |_ CHARGER device (charger ops) |--> BUCK out M
- | | |_ MUIC device (microUSB con ops) |
- | BUS 1 | |_ ... |---> BATTERY
- | e.g.I2C1 | |
- |-----------|---- PMIC device 1 (READ/WRITE ops) |---> USB in 1
- . or SPI1 | |_ RTC device (rtc ops) |---> USB in 2
- . |______________________________________|---> USB out
- .
-
-Since U-Boot provides driver model features for I2C and SPI bus drivers,
-the PMIC devices should also support this. By the pmic and regulator API's,
-PMIC drivers can simply provide a common functions, for multi-interface and
-and multi-instance device support.
-
-Basic design assumptions:
-
-- Common I/O API - UCLASS_PMIC
-For the multi-function PMIC devices, this can be used as parent I/O device
-for each IC's interface. Then, each children uses the same dev for read/write.
-
-- Common regulator API - UCLASS_REGULATOR
-For driving the regulator attributes, auto setting function or command line
-interface, based on kernel-style regulator device tree constraints.
-
-For simple implementations, regulator drivers are not required, so the code can
-use pmic read/write directly.
-
-3. Pmic uclass
-==============
-The basic information:
-* Uclass: 'UCLASS_PMIC'
-* Header: 'include/power/pmic.h'
-* Core: 'drivers/power/pmic/pmic-uclass.c'
- config: 'CONFIG_DM_PMIC'
-* Command: 'common/cmd_pmic.c'
- config: 'CONFIG_CMD_PMIC'
-* Example: 'drivers/power/pmic/max77686.c'
-
-For detailed API description, please refer to the header file.
-
-As an example of the pmic driver, please refer to the MAX77686 driver.
-
-Please pay attention for the driver's bind() method. Exactly the function call:
-'pmic_bind_children()', which is used to bind the regulators by using the array
-of regulator's node, compatible prefixes.
-
-The 'pmic; command also supports the new API. So the pmic command can be enabled
-by adding CONFIG_CMD_PMIC.
-The new pmic command allows to:
-- list pmic devices
-- choose the current device (like the mmc command)
-- read or write the pmic register
-- dump all pmic registers
-
-This command can use only UCLASS_PMIC devices, since this uclass is designed
-for pmic I/O operations only.
-
-For more information, please refer to the core file.
-
-4. Regulator uclass
-===================
-The basic information:
-* Uclass: 'UCLASS_REGULATOR'
-* Header: 'include/power/regulator.h'
-* Core: 'drivers/power/regulator/regulator-uclass.c'
- config: 'CONFIG_DM_REGULATOR'
- binding: 'doc/device-tree-bindings/regulator/regulator.txt'
-* Command: 'common/cmd_regulator.c'
- config: 'CONFIG_CMD_REGULATOR'
-* Example: 'drivers/power/regulator/max77686.c'
- 'drivers/power/pmic/max77686.c' (required I/O driver for the above)
-* Example: 'drivers/power/regulator/fixed.c'
- config" 'CONFIG_DM_REGULATOR_FIXED'
-
-For detailed API description, please refer to the header file.
-
-For the example regulator driver, please refer to the MAX77686 regulator driver,
-but this driver can't operate without pmic's example driver, which provides an
-I/O interface for MAX77686 regulator.
-
-The second example is a fixed Voltage/Current regulator for a common use.
-
-The 'regulator' command also supports the new API. The command allow:
-- list regulator devices
-- choose the current device (like the mmc command)
-- do all regulator-specific operations
-
-For more information, please refer to the command file.
diff --git a/doc/driver-model/remoteproc-framework.rst b/doc/driver-model/remoteproc-framework.rst
new file mode 100644
index 0000000..f21de0a
--- /dev/null
+++ b/doc/driver-model/remoteproc-framework.rst
@@ -0,0 +1,169 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. (C) Copyright 2015
+.. Texas Instruments Incorporated - http://www.ti.com/
+
+Remote Processor Framework
+==========================
+
+Introduction
+------------
+
+This is an introduction to driver-model for Remote Processors found
+on various System on Chip(SoCs). The term remote processor is used to
+indicate that this is not the processor on which U-Boot is operating
+on, instead is yet another processing entity that may be controlled by
+the processor on which we are functional.
+
+The simplified model depends on a single UCLASS - UCLASS_REMOTEPROC
+
+UCLASS_REMOTEPROC:
+ - drivers/remoteproc/rproc-uclass.c
+ - include/remoteproc.h
+
+Commands:
+ - common/cmd_remoteproc.c
+
+Configuration:
+ - CONFIG_REMOTEPROC is selected by drivers as needed
+ - CONFIG_CMD_REMOTEPROC for the commands if required.
+
+How does it work - The driver
+-----------------------------
+
+Overall, the driver statemachine transitions are typically as follows::
+
+ (entry)
+ +-------+
+ +---+ init |
+ | | | <---------------------+
+ | +-------+ |
+ | |
+ | |
+ | +--------+ |
+ Load| | reset | |
+ | | | <----------+ |
+ | +--------+ | |
+ | |Load | |
+ | | | |
+ | +----v----+ reset | |
+ +-> | | (opt) | |
+ | Loaded +-----------+ |
+ | | |
+ +----+----+ |
+ | Start |
+ +---v-----+ (opt) |
+ +->| Running | Stop |
+ Ping +- | +--------------------+
+ (opt) +---------+
+
+(is_running does not change state)
+opt: Optional state transition implemented by driver.
+
+NOTE: It depends on the remote processor as to the exact behavior
+of the statemachine, remoteproc core does not intent to implement
+statemachine logic. Certain processors may allow start/stop without
+reloading the image in the middle, certain other processors may only
+allow us to start the processor(image from a EEPROM/OTP) etc.
+
+It is hence the responsibility of the driver to handle the requisite
+state transitions of the device as necessary.
+
+Basic design assumptions:
+
+Remote processor can operate on a certain firmware that maybe loaded
+and released from reset.
+
+The driver follows a standard UCLASS DM.
+
+in the bare minimum form:
+
+.. code-block:: c
+
+ static const struct dm_rproc_ops sandbox_testproc_ops = {
+ .load = sandbox_testproc_load,
+ .start = sandbox_testproc_start,
+ };
+
+ static const struct udevice_id sandbox_ids[] = {
+ {.compatible = "sandbox,test-processor"},
+ {}
+ };
+
+ U_BOOT_DRIVER(sandbox_testproc) = {
+ .name = "sandbox_test_proc",
+ .of_match = sandbox_ids,
+ .id = UCLASS_REMOTEPROC,
+ .ops = &sandbox_testproc_ops,
+ .probe = sandbox_testproc_probe,
+ };
+
+This allows for the device to be probed as part of the "init" command
+or invocation of 'rproc_init()' function as the system dependencies define.
+
+The driver is expected to maintain it's own statemachine which is
+appropriate for the device it maintains. It must, at the very least
+provide a load and start function. We assume here that the device
+needs to be loaded and started, else, there is no real purpose of
+using the remoteproc framework.
+
+Describing the device using platform data
+-----------------------------------------
+
+*IMPORTANT* NOTE: THIS SUPPORT IS NOT MEANT FOR USE WITH NEWER PLATFORM
+SUPPORT. THIS IS ONLY FOR LEGACY DEVICES. THIS MODE OF INITIALIZATION
+*WILL* BE EVENTUALLY REMOVED ONCE ALL NECESSARY PLATFORMS HAVE MOVED
+TO DM/FDT.
+
+Considering that many platforms are yet to move to device-tree model,
+a simplified definition of a device is as follows:
+
+.. code-block:: c
+
+ struct dm_rproc_uclass_pdata proc_3_test = {
+ .name = "proc_3_legacy",
+ .mem_type = RPROC_INTERNAL_MEMORY_MAPPED,
+ .driver_plat_data = &mydriver_data;
+ };
+
+ U_BOOT_DEVICE(proc_3_demo) = {
+ .name = "sandbox_test_proc",
+ .platdata = &proc_3_test,
+ };
+
+There can be additional data that may be desired depending on the
+remoteproc driver specific needs (for example: SoC integration
+details such as clock handle or something similar). See appropriate
+documentation for specific remoteproc driver for further details.
+These are passed via driver_plat_data.
+
+Describing the device using device tree
+---------------------------------------
+
+.. code-block: none
+
+ / {
+ ...
+ aliases {
+ ...
+ remoteproc0 = &rproc_1;
+ remoteproc1 = &rproc_2;
+
+ };
+ ...
+
+ rproc_1: rproc@1 {
+ compatible = "sandbox,test-processor";
+ remoteproc-name = "remoteproc-test-dev1";
+ };
+
+ rproc_2: rproc@2 {
+ compatible = "sandbox,test-processor";
+ internal-memory-mapped;
+ remoteproc-name = "remoteproc-test-dev2";
+ };
+ ...
+ };
+
+aliases usage is optional, but it is usually recommended to ensure the
+users have a consistent usage model for a platform.
+the compatible string used here is specific to the remoteproc driver involved.
diff --git a/doc/driver-model/remoteproc-framework.txt b/doc/driver-model/remoteproc-framework.txt
deleted file mode 100644
index c6dc00d..0000000
--- a/doc/driver-model/remoteproc-framework.txt
+++ /dev/null
@@ -1,168 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2015
-# Texas Instruments Incorporated - http://www.ti.com/
-#
-
-Remote Processor Framework
-==========================
-TOC:
-1. Introduction
-2. How does it work - The driver
-3. Describing the device using platform data
-4. Describing the device using device tree
-
-1. Introduction
-===============
-
-This is an introduction to driver-model for Remote Processors found
-on various System on Chip(SoCs). The term remote processor is used to
-indicate that this is not the processor on which U-Boot is operating
-on, instead is yet another processing entity that may be controlled by
-the processor on which we are functional.
-
-The simplified model depends on a single UCLASS - UCLASS_REMOTEPROC
-
-UCLASS_REMOTEPROC:
-- drivers/remoteproc/rproc-uclass.c
-- include/remoteproc.h
-
-Commands:
-- common/cmd_remoteproc.c
-
-Configuration:
-CONFIG_REMOTEPROC is selected by drivers as needed
-CONFIG_CMD_REMOTEPROC for the commands if required.
-
-2. How does it work - The driver
-=================================
-
-Overall, the driver statemachine transitions are typically as follows:
- (entry)
- +-------+
- +---+ init |
- | | | <---------------------+
- | +-------+ |
- | |
- | |
- | +--------+ |
-Load| | reset | |
- | | | <----------+ |
- | +--------+ | |
- | |Load | |
- | | | |
- | +----v----+ reset | |
- +-> | | (opt) | |
- | Loaded +-----------+ |
- | | |
- +----+----+ |
- | Start |
- +---v-----+ (opt) |
- +->| Running | Stop |
-Ping +- | +--------------------+
-(opt) +---------+
-
-(is_running does not change state)
-opt: Optional state transition implemented by driver.
-
-NOTE: It depends on the remote processor as to the exact behavior
-of the statemachine, remoteproc core does not intent to implement
-statemachine logic. Certain processors may allow start/stop without
-reloading the image in the middle, certain other processors may only
-allow us to start the processor(image from a EEPROM/OTP) etc.
-
-It is hence the responsibility of the driver to handle the requisite
-state transitions of the device as necessary.
-
-Basic design assumptions:
-
-Remote processor can operate on a certain firmware that maybe loaded
-and released from reset.
-
-The driver follows a standard UCLASS DM.
-
-in the bare minimum form:
-
-static const struct dm_rproc_ops sandbox_testproc_ops = {
- .load = sandbox_testproc_load,
- .start = sandbox_testproc_start,
-};
-
-static const struct udevice_id sandbox_ids[] = {
- {.compatible = "sandbox,test-processor"},
- {}
-};
-
-U_BOOT_DRIVER(sandbox_testproc) = {
- .name = "sandbox_test_proc",
- .of_match = sandbox_ids,
- .id = UCLASS_REMOTEPROC,
- .ops = &sandbox_testproc_ops,
- .probe = sandbox_testproc_probe,
-};
-
-This allows for the device to be probed as part of the "init" command
-or invocation of 'rproc_init()' function as the system dependencies define.
-
-The driver is expected to maintain it's own statemachine which is
-appropriate for the device it maintains. It must, at the very least
-provide a load and start function. We assume here that the device
-needs to be loaded and started, else, there is no real purpose of
-using the remoteproc framework.
-
-3. Describing the device using platform data
-============================================
-
-*IMPORTANT* NOTE: THIS SUPPORT IS NOT MEANT FOR USE WITH NEWER PLATFORM
-SUPPORT. THIS IS ONLY FOR LEGACY DEVICES. THIS MODE OF INITIALIZATION
-*WILL* BE EVENTUALLY REMOVED ONCE ALL NECESSARY PLATFORMS HAVE MOVED
-TO DM/FDT.
-
-Considering that many platforms are yet to move to device-tree model,
-a simplified definition of a device is as follows:
-
-struct dm_rproc_uclass_pdata proc_3_test = {
- .name = "proc_3_legacy",
- .mem_type = RPROC_INTERNAL_MEMORY_MAPPED,
- .driver_plat_data = &mydriver_data;
-};
-
-U_BOOT_DEVICE(proc_3_demo) = {
- .name = "sandbox_test_proc",
- .platdata = &proc_3_test,
-};
-
-There can be additional data that may be desired depending on the
-remoteproc driver specific needs (for example: SoC integration
-details such as clock handle or something similar). See appropriate
-documentation for specific remoteproc driver for further details.
-These are passed via driver_plat_data.
-
-3. Describing the device using device tree
-==========================================
-/ {
- ...
- aliases {
- ...
- remoteproc0 = &rproc_1;
- remoteproc1 = &rproc_2;
-
- };
- ...
-
- rproc_1: rproc@1 {
- compatible = "sandbox,test-processor";
- remoteproc-name = "remoteproc-test-dev1";
- };
-
- rproc_2: rproc@2 {
- compatible = "sandbox,test-processor";
- internal-memory-mapped;
- remoteproc-name = "remoteproc-test-dev2";
- };
- ...
-};
-
-aliases usage is optional, but it is usually recommended to ensure the
-users have a consistent usage model for a platform.
-the compatible string used here is specific to the remoteproc driver involved.
diff --git a/doc/driver-model/serial-howto.rst b/doc/driver-model/serial-howto.rst
new file mode 100644
index 0000000..1469131
--- /dev/null
+++ b/doc/driver-model/serial-howto.rst
@@ -0,0 +1,46 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+How to port a serial driver to driver model
+===========================================
+
+Almost all of the serial drivers have been converted as at January 2016. These
+ones remain:
+
+ * serial_bfin.c
+ * serial_pxa.c
+
+The deadline for this work was the end of January 2016. If no one steps
+forward to convert these, at some point there may come a patch to remove them!
+
+Here is a suggested approach for converting your serial driver over to driver
+model. Please feel free to update this file with your ideas and suggestions.
+
+- #ifdef out all your own serial driver code (#ifndef CONFIG_DM_SERIAL)
+- Define CONFIG_DM_SERIAL for your board, vendor or architecture
+- If the board does not already use driver model, you need CONFIG_DM also
+- Your board should then build, but will not boot since there will be no serial
+ driver
+- Add the U_BOOT_DRIVER piece at the end (e.g. copy serial_s5p.c for example)
+- Add a private struct for the driver data - avoid using static variables
+- Implement each of the driver methods, perhaps by calling your old methods
+- You may need to adjust the function parameters so that the old and new
+ implementations can share most of the existing code
+- If you convert all existing users of the driver, remove the pre-driver-model
+ code
+
+In terms of patches a conversion series typically has these patches:
+- clean up / prepare the driver for conversion
+- add driver model code
+- convert at least one existing board to use driver model serial
+- (if no boards remain that don't use driver model) remove the old code
+
+This may be a good time to move your board to use device tree also. Mostly
+this involves these steps:
+
+- define CONFIG_OF_CONTROL and CONFIG_OF_SEPARATE
+- add your device tree files to arch/<arch>/dts
+- update the Makefile there
+- Add stdout-path to your /chosen device tree node if it is not already there
+- build and get u-boot-dtb.bin so you can test it
+- Your drivers can now use device tree
+- For device tree in SPL, define CONFIG_SPL_OF_CONTROL
diff --git a/doc/driver-model/serial-howto.txt b/doc/driver-model/serial-howto.txt
deleted file mode 100644
index a0df9a7..0000000
--- a/doc/driver-model/serial-howto.txt
+++ /dev/null
@@ -1,44 +0,0 @@
-How to port a serial driver to driver model
-===========================================
-
-Almost all of the serial drivers have been converted as at January 2016. These
-ones remain:
-
- serial_bfin.c
- serial_pxa.c
-
-The deadline for this work was the end of January 2016. If no one steps
-forward to convert these, at some point there may come a patch to remove them!
-
-Here is a suggested approach for converting your serial driver over to driver
-model. Please feel free to update this file with your ideas and suggestions.
-
-- #ifdef out all your own serial driver code (#ifndef CONFIG_DM_SERIAL)
-- Define CONFIG_DM_SERIAL for your board, vendor or architecture
-- If the board does not already use driver model, you need CONFIG_DM also
-- Your board should then build, but will not boot since there will be no serial
- driver
-- Add the U_BOOT_DRIVER piece at the end (e.g. copy serial_s5p.c for example)
-- Add a private struct for the driver data - avoid using static variables
-- Implement each of the driver methods, perhaps by calling your old methods
-- You may need to adjust the function parameters so that the old and new
- implementations can share most of the existing code
-- If you convert all existing users of the driver, remove the pre-driver-model
- code
-
-In terms of patches a conversion series typically has these patches:
-- clean up / prepare the driver for conversion
-- add driver model code
-- convert at least one existing board to use driver model serial
-- (if no boards remain that don't use driver model) remove the old code
-
-This may be a good time to move your board to use device tree also. Mostly
-this involves these steps:
-
-- define CONFIG_OF_CONTROL and CONFIG_OF_SEPARATE
-- add your device tree files to arch/<arch>/dts
-- update the Makefile there
-- Add stdout-path to your /chosen device tree node if it is not already there
-- build and get u-boot-dtb.bin so you can test it
-- Your drivers can now use device tree
-- For device tree in SPL, define CONFIG_SPL_OF_CONTROL
diff --git a/doc/driver-model/spi-howto.rst b/doc/driver-model/spi-howto.rst
new file mode 100644
index 0000000..a538fdc
--- /dev/null
+++ b/doc/driver-model/spi-howto.rst
@@ -0,0 +1,692 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+How to port a SPI driver to driver model
+========================================
+
+Here is a rough step-by-step guide. It is based around converting the
+exynos SPI driver to driver model (DM) and the example code is based
+around U-Boot v2014.10-rc2 (commit be9f643). This has been updated for
+v2015.04.
+
+It is quite long since it includes actual code examples.
+
+Before driver model, SPI drivers have their own private structure which
+contains 'struct spi_slave'. With driver model, 'struct spi_slave' still
+exists, but now it is 'per-child data' for the SPI bus. Each child of the
+SPI bus is a SPI slave. The information that was stored in the
+driver-specific slave structure can now be port in private data for the
+SPI bus.
+
+For example, struct tegra_spi_slave looks like this:
+
+.. code-block:: c
+
+ struct tegra_spi_slave {
+ struct spi_slave slave;
+ struct tegra_spi_ctrl *ctrl;
+ };
+
+In this case 'slave' will be in per-child data, and 'ctrl' will be in the
+SPI's buses private data.
+
+
+How long does this take?
+------------------------
+
+You should be able to complete this within 2 hours, including testing but
+excluding preparing the patches. The API is basically the same as before
+with only minor changes:
+
+- methods to set speed and mode are separated out
+- cs_info is used to get information on a chip select
+
+
+Enable driver mode for SPI and SPI flash
+----------------------------------------
+
+Add these to your board config:
+
+* CONFIG_DM_SPI
+* CONFIG_DM_SPI_FLASH
+
+
+Add the skeleton
+----------------
+
+Put this code at the bottom of your existing driver file:
+
+.. code-block:: c
+
+ struct spi_slave *spi_setup_slave(unsigned int busnum, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+ {
+ return NULL;
+ }
+
+ struct spi_slave *spi_setup_slave_fdt(const void *blob, int slave_node,
+ int spi_node)
+ {
+ return NULL;
+ }
+
+ static int exynos_spi_ofdata_to_platdata(struct udevice *dev)
+ {
+ return -ENODEV;
+ }
+
+ static int exynos_spi_probe(struct udevice *dev)
+ {
+ return -ENODEV;
+ }
+
+ static int exynos_spi_remove(struct udevice *dev)
+ {
+ return -ENODEV;
+ }
+
+ static int exynos_spi_claim_bus(struct udevice *dev)
+ {
+
+ return -ENODEV;
+ }
+
+ static int exynos_spi_release_bus(struct udevice *dev)
+ {
+
+ return -ENODEV;
+ }
+
+ static int exynos_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+ {
+
+ return -ENODEV;
+ }
+
+ static int exynos_spi_set_speed(struct udevice *dev, uint speed)
+ {
+ return -ENODEV;
+ }
+
+ static int exynos_spi_set_mode(struct udevice *dev, uint mode)
+ {
+ return -ENODEV;
+ }
+
+ static int exynos_cs_info(struct udevice *bus, uint cs,
+ struct spi_cs_info *info)
+ {
+ return -ENODEV;
+ }
+
+ static const struct dm_spi_ops exynos_spi_ops = {
+ .claim_bus = exynos_spi_claim_bus,
+ .release_bus = exynos_spi_release_bus,
+ .xfer = exynos_spi_xfer,
+ .set_speed = exynos_spi_set_speed,
+ .set_mode = exynos_spi_set_mode,
+ .cs_info = exynos_cs_info,
+ };
+
+ static const struct udevice_id exynos_spi_ids[] = {
+ { .compatible = "samsung,exynos-spi" },
+ { }
+ };
+
+ U_BOOT_DRIVER(exynos_spi) = {
+ .name = "exynos_spi",
+ .id = UCLASS_SPI,
+ .of_match = exynos_spi_ids,
+ .ops = &exynos_spi_ops,
+ .ofdata_to_platdata = exynos_spi_ofdata_to_platdata,
+ .probe = exynos_spi_probe,
+ .remove = exynos_spi_remove,
+ };
+
+
+Replace 'exynos' in the above code with your driver name
+--------------------------------------------------------
+
+
+#ifdef out all of the code in your driver except for the above
+--------------------------------------------------------------
+
+This will allow you to get it building, which means you can work
+incrementally. Since all the methods return an error initially, there is
+less chance that you will accidentally leave something in.
+
+Also, even though your conversion is basically a rewrite, it might help
+reviewers if you leave functions in the same place in the file,
+particularly for large drivers.
+
+
+Add some includes
+-----------------
+
+Add these includes to your driver:
+
+.. code-block:: c
+
+ #include <dm.h>
+ #include <errno.h>
+
+
+Build
+-----
+
+At this point you should be able to build U-Boot for your board with the
+empty SPI driver. You still have empty methods in your driver, but we will
+write these one by one.
+
+Set up your platform data structure
+-----------------------------------
+
+This will hold the information your driver to operate, like its hardware
+address or maximum frequency.
+
+You may already have a struct like this, or you may need to create one
+from some of the #defines or global variables in the driver.
+
+Note that this information is not the run-time information. It should not
+include state that changes. It should be fixed throughout the live of
+U-Boot. Run-time information comes later.
+
+Here is what was in the exynos spi driver:
+
+.. code-block:: c
+
+ struct spi_bus {
+ enum periph_id periph_id;
+ s32 frequency; /* Default clock frequency, -1 for none */
+ struct exynos_spi *regs;
+ int inited; /* 1 if this bus is ready for use */
+ int node;
+ uint deactivate_delay_us; /* Delay to wait after deactivate */
+ };
+
+Of these, inited is handled by DM and node is the device tree node, which
+DM tells you. The name is not quite right. So in this case we would use:
+
+.. code-block:: c
+
+ struct exynos_spi_platdata {
+ enum periph_id periph_id;
+ s32 frequency; /* Default clock frequency, -1 for none */
+ struct exynos_spi *regs;
+ uint deactivate_delay_us; /* Delay to wait after deactivate */
+ };
+
+
+Write ofdata_to_platdata() [for device tree only]
+-------------------------------------------------
+
+This method will convert information in the device tree node into a C
+structure in your driver (called platform data). If you are not using
+device tree, go to 8b.
+
+DM will automatically allocate the struct for us when we are using device
+tree, but we need to tell it the size:
+
+.. code-block:: c
+
+ U_BOOT_DRIVER(spi_exynos) = {
+ ...
+ .platdata_auto_alloc_size = sizeof(struct exynos_spi_platdata),
+
+
+Here is a sample function. It gets a pointer to the platform data and
+fills in the fields from device tree.
+
+.. code-block:: c
+
+ static int exynos_spi_ofdata_to_platdata(struct udevice *bus)
+ {
+ struct exynos_spi_platdata *plat = bus->platdata;
+ const void *blob = gd->fdt_blob;
+ int node = dev_of_offset(bus);
+
+ plat->regs = (struct exynos_spi *)fdtdec_get_addr(blob, node, "reg");
+ plat->periph_id = pinmux_decode_periph_id(blob, node);
+
+ if (plat->periph_id == PERIPH_ID_NONE) {
+ debug("%s: Invalid peripheral ID %d\n", __func__,
+ plat->periph_id);
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ /* Use 500KHz as a suitable default */
+ plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
+ 500000);
+ plat->deactivate_delay_us = fdtdec_get_int(blob, node,
+ "spi-deactivate-delay", 0);
+ debug("%s: regs=%p, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
+ __func__, plat->regs, plat->periph_id, plat->frequency,
+ plat->deactivate_delay_us);
+
+ return 0;
+ }
+
+
+Add the platform data [non-device-tree only]
+--------------------------------------------
+
+Specify this data in a U_BOOT_DEVICE() declaration in your board file:
+
+.. code-block:: c
+
+ struct exynos_spi_platdata platdata_spi0 = {
+ .periph_id = ...
+ .frequency = ...
+ .regs = ...
+ .deactivate_delay_us = ...
+ };
+
+ U_BOOT_DEVICE(board_spi0) = {
+ .name = "exynos_spi",
+ .platdata = &platdata_spi0,
+ };
+
+You will unfortunately need to put the struct definition into a header file
+in this case so that your board file can use it.
+
+
+Add the device private data
+---------------------------
+
+Most devices have some private data which they use to keep track of things
+while active. This is the run-time information and needs to be stored in
+a structure. There is probably a structure in the driver that includes a
+'struct spi_slave', so you can use that.
+
+.. code-block:: c
+
+ struct exynos_spi_slave {
+ struct spi_slave slave;
+ struct exynos_spi *regs;
+ unsigned int freq; /* Default frequency */
+ unsigned int mode;
+ enum periph_id periph_id; /* Peripheral ID for this device */
+ unsigned int fifo_size;
+ int skip_preamble;
+ struct spi_bus *bus; /* Pointer to our SPI bus info */
+ ulong last_transaction_us; /* Time of last transaction end */
+ };
+
+
+We should rename this to make its purpose more obvious, and get rid of
+the slave structure, so we have:
+
+.. code-block:: c
+
+ struct exynos_spi_priv {
+ struct exynos_spi *regs;
+ unsigned int freq; /* Default frequency */
+ unsigned int mode;
+ enum periph_id periph_id; /* Peripheral ID for this device */
+ unsigned int fifo_size;
+ int skip_preamble;
+ ulong last_transaction_us; /* Time of last transaction end */
+ };
+
+
+DM can auto-allocate this also:
+
+.. code-block:: c
+
+ U_BOOT_DRIVER(spi_exynos) = {
+ ...
+ .priv_auto_alloc_size = sizeof(struct exynos_spi_priv),
+
+
+Note that this is created before the probe method is called, and destroyed
+after the remove method is called. It will be zeroed when the probe
+method is called.
+
+
+Add the probe() and remove() methods
+------------------------------------
+
+Note: It's a good idea to build repeatedly as you are working, to avoid a
+huge amount of work getting things compiling at the end.
+
+The probe method is supposed to set up the hardware. U-Boot used to use
+spi_setup_slave() to do this. So take a look at this function and see
+what you can copy out to set things up.
+
+.. code-block:: c
+
+ static int exynos_spi_probe(struct udevice *bus)
+ {
+ struct exynos_spi_platdata *plat = dev_get_platdata(bus);
+ struct exynos_spi_priv *priv = dev_get_priv(bus);
+
+ priv->regs = plat->regs;
+ if (plat->periph_id == PERIPH_ID_SPI1 ||
+ plat->periph_id == PERIPH_ID_SPI2)
+ priv->fifo_size = 64;
+ else
+ priv->fifo_size = 256;
+
+ priv->skip_preamble = 0;
+ priv->last_transaction_us = timer_get_us();
+ priv->freq = plat->frequency;
+ priv->periph_id = plat->periph_id;
+
+ return 0;
+ }
+
+This implementation doesn't actually touch the hardware, which is somewhat
+unusual for a driver. In this case we will do that when the device is
+claimed by something that wants to use the SPI bus.
+
+For remove we could shut down the clocks, but in this case there is
+nothing to do. DM frees any memory that it allocated, so we can just
+remove exynos_spi_remove() and its reference in U_BOOT_DRIVER.
+
+
+Implement set_speed()
+---------------------
+
+This should set up clocks so that the SPI bus is running at the right
+speed. With the old API spi_claim_bus() would normally do this and several
+of the following functions, so let's look at that function:
+
+.. code-block:: c
+
+ int spi_claim_bus(struct spi_slave *slave)
+ {
+ struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
+ struct exynos_spi *regs = spi_slave->regs;
+ u32 reg = 0;
+ int ret;
+
+ ret = set_spi_clk(spi_slave->periph_id,
+ spi_slave->freq);
+ if (ret < 0) {
+ debug("%s: Failed to setup spi clock\n", __func__);
+ return ret;
+ }
+
+ exynos_pinmux_config(spi_slave->periph_id, PINMUX_FLAG_NONE);
+
+ spi_flush_fifo(slave);
+
+ reg = readl(®s->ch_cfg);
+ reg &= ~(SPI_CH_CPHA_B | SPI_CH_CPOL_L);
+
+ if (spi_slave->mode & SPI_CPHA)
+ reg |= SPI_CH_CPHA_B;
+
+ if (spi_slave->mode & SPI_CPOL)
+ reg |= SPI_CH_CPOL_L;
+
+ writel(reg, ®s->ch_cfg);
+ writel(SPI_FB_DELAY_180, ®s->fb_clk);
+
+ return 0;
+ }
+
+
+It sets up the speed, mode, pinmux, feedback delay and clears the FIFOs.
+With DM these will happen in separate methods.
+
+
+Here is an example for the speed part:
+
+.. code-block:: c
+
+ static int exynos_spi_set_speed(struct udevice *bus, uint speed)
+ {
+ struct exynos_spi_platdata *plat = bus->platdata;
+ struct exynos_spi_priv *priv = dev_get_priv(bus);
+ int ret;
+
+ if (speed > plat->frequency)
+ speed = plat->frequency;
+ ret = set_spi_clk(priv->periph_id, speed);
+ if (ret)
+ return ret;
+ priv->freq = speed;
+ debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
+
+ return 0;
+ }
+
+
+Implement set_mode()
+--------------------
+
+This should adjust the SPI mode (polarity, etc.). Again this code probably
+comes from the old spi_claim_bus(). Here is an example:
+
+.. code-block:: c
+
+ static int exynos_spi_set_mode(struct udevice *bus, uint mode)
+ {
+ struct exynos_spi_priv *priv = dev_get_priv(bus);
+ uint32_t reg;
+
+ reg = readl(&priv->regs->ch_cfg);
+ reg &= ~(SPI_CH_CPHA_B | SPI_CH_CPOL_L);
+
+ if (mode & SPI_CPHA)
+ reg |= SPI_CH_CPHA_B;
+
+ if (mode & SPI_CPOL)
+ reg |= SPI_CH_CPOL_L;
+
+ writel(reg, &priv->regs->ch_cfg);
+ priv->mode = mode;
+ debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
+
+ return 0;
+ }
+
+
+Implement claim_bus()
+---------------------
+
+This is where a client wants to make use of the bus, so claims it first.
+At this point we need to make sure everything is set up ready for data
+transfer. Note that this function is wholly internal to the driver - at
+present the SPI uclass never calls it.
+
+Here again we look at the old claim function and see some code that is
+needed. It is anything unrelated to speed and mode:
+
+.. code-block:: c
+
+ static int exynos_spi_claim_bus(struct udevice *bus)
+ {
+ struct exynos_spi_priv *priv = dev_get_priv(bus);
+
+ exynos_pinmux_config(priv->periph_id, PINMUX_FLAG_NONE);
+ spi_flush_fifo(priv->regs);
+
+ writel(SPI_FB_DELAY_180, &priv->regs->fb_clk);
+
+ return 0;
+ }
+
+The spi_flush_fifo() function is in the removed part of the code, so we
+need to expose it again (perhaps with an #endif before it and '#if 0'
+after it). It only needs access to priv->regs which is why we have
+passed that in:
+
+.. code-block:: c
+
+ /**
+ * Flush spi tx, rx fifos and reset the SPI controller
+ *
+ * @param regs Pointer to SPI registers
+ */
+ static void spi_flush_fifo(struct exynos_spi *regs)
+ {
+ clrsetbits_le32(®s->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
+ clrbits_le32(®s->ch_cfg, SPI_CH_RST);
+ setbits_le32(®s->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
+ }
+
+
+Implement release_bus()
+-----------------------
+
+This releases the bus - in our example the old code in spi_release_bus()
+is a call to spi_flush_fifo, so we add:
+
+.. code-block:: c
+
+ static int exynos_spi_release_bus(struct udevice *bus)
+ {
+ struct exynos_spi_priv *priv = dev_get_priv(bus);
+
+ spi_flush_fifo(priv->regs);
+
+ return 0;
+ }
+
+
+Implement xfer()
+----------------
+
+This is the final method that we need to create, and it is where all the
+work happens. The method parameters are the same as the old spi_xfer() with
+the addition of a 'struct udevice' so conversion is pretty easy. Start
+by copying the contents of spi_xfer() to your new xfer() method and proceed
+from there.
+
+If (flags & SPI_XFER_BEGIN) is non-zero then xfer() normally calls an
+activate function, something like this:
+
+.. code-block:: c
+
+ void spi_cs_activate(struct spi_slave *slave)
+ {
+ struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
+
+ /* If it's too soon to do another transaction, wait */
+ if (spi_slave->bus->deactivate_delay_us &&
+ spi_slave->last_transaction_us) {
+ ulong delay_us; /* The delay completed so far */
+ delay_us = timer_get_us() - spi_slave->last_transaction_us;
+ if (delay_us < spi_slave->bus->deactivate_delay_us)
+ udelay(spi_slave->bus->deactivate_delay_us - delay_us);
+ }
+
+ clrbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT);
+ debug("Activate CS, bus %d\n", spi_slave->slave.bus);
+ spi_slave->skip_preamble = spi_slave->mode & SPI_PREAMBLE;
+ }
+
+The new version looks like this:
+
+.. code-block:: c
+
+ static void spi_cs_activate(struct udevice *dev)
+ {
+ struct udevice *bus = dev->parent;
+ struct exynos_spi_platdata *pdata = dev_get_platdata(bus);
+ struct exynos_spi_priv *priv = dev_get_priv(bus);
+
+ /* If it's too soon to do another transaction, wait */
+ if (pdata->deactivate_delay_us &&
+ priv->last_transaction_us) {
+ ulong delay_us; /* The delay completed so far */
+ delay_us = timer_get_us() - priv->last_transaction_us;
+ if (delay_us < pdata->deactivate_delay_us)
+ udelay(pdata->deactivate_delay_us - delay_us);
+ }
+
+ clrbits_le32(&priv->regs->cs_reg, SPI_SLAVE_SIG_INACT);
+ debug("Activate CS, bus '%s'\n", bus->name);
+ priv->skip_preamble = priv->mode & SPI_PREAMBLE;
+ }
+
+All we have really done here is change the pointers and print the device name
+instead of the bus number. Other local static functions can be treated in
+the same way.
+
+
+Set up the per-child data and child pre-probe function
+------------------------------------------------------
+
+To minimise the pain and complexity of the SPI subsystem while the driver
+model change-over is in place, struct spi_slave is used to reference a
+SPI bus slave, even though that slave is actually a struct udevice. In fact
+struct spi_slave is the device's child data. We need to make sure this space
+is available. It is possible to allocate more space that struct spi_slave
+needs, but this is the minimum.
+
+.. code-block:: c
+
+ U_BOOT_DRIVER(exynos_spi) = {
+ ...
+ .per_child_auto_alloc_size = sizeof(struct spi_slave),
+ }
+
+
+Optional: Set up cs_info() if you want it
+-----------------------------------------
+
+Sometimes it is useful to know whether a SPI chip select is valid, but this
+is not obvious from outside the driver. In this case you can provide a
+method for cs_info() to deal with this. If you don't provide it, then the
+device tree will be used to determine what chip selects are valid.
+
+Return -ENODEV if the supplied chip select is invalid, or 0 if it is valid.
+If you don't provide the cs_info() method, -ENODEV is assumed for all
+chip selects that do not appear in the device tree.
+
+
+Test it
+-------
+
+Now that you have the code written and it compiles, try testing it using
+the 'sf test' command. You may need to enable CONFIG_CMD_SF_TEST for your
+board.
+
+
+Prepare patches and send them to the mailing lists
+--------------------------------------------------
+
+You can use 'tools/patman/patman' to prepare, check and send patches for
+your work. See the README for details.
+
+A little note about SPI uclass features
+---------------------------------------
+
+The SPI uclass keeps some information about each device 'dev' on the bus:
+
+ struct dm_spi_slave_platdata:
+ This is device_get_parent_platdata(dev).
+ This is where the chip select number is stored, along with
+ the default bus speed and mode. It is automatically read
+ from the device tree in spi_child_post_bind(). It must not
+ be changed at run-time after being set up because platform
+ data is supposed to be immutable at run-time.
+ struct spi_slave:
+ This is device_get_parentdata(dev).
+ Already mentioned above. It holds run-time information about
+ the device.
+
+There are also some SPI uclass methods that get called behind the scenes:
+
+ spi_post_bind():
+ Called when a new bus is bound.
+ This scans the device tree for devices on the bus, and binds
+ each one. This in turn causes spi_child_post_bind() to be
+ called for each, which reads the device tree information
+ into the parent (per-child) platform data.
+ spi_child_post_bind():
+ Called when a new child is bound.
+ As mentioned above this reads the device tree information
+ into the per-child platform data
+ spi_child_pre_probe():
+ Called before a new child is probed.
+ This sets up the mode and speed in struct spi_slave by
+ copying it from the parent's platform data for this child.
+ It also sets the 'dev' pointer, needed to permit passing
+ 'struct spi_slave' around the place without needing a
+ separate 'struct udevice' pointer.
+
+The above housekeeping makes it easier to write your SPI driver.
diff --git a/doc/driver-model/spi-howto.txt b/doc/driver-model/spi-howto.txt
deleted file mode 100644
index 38c26f6..0000000
--- a/doc/driver-model/spi-howto.txt
+++ /dev/null
@@ -1,623 +0,0 @@
-How to port a SPI driver to driver model
-========================================
-
-Here is a rough step-by-step guide. It is based around converting the
-exynos SPI driver to driver model (DM) and the example code is based
-around U-Boot v2014.10-rc2 (commit be9f643). This has been updated for
-v2015.04.
-
-It is quite long since it includes actual code examples.
-
-Before driver model, SPI drivers have their own private structure which
-contains 'struct spi_slave'. With driver model, 'struct spi_slave' still
-exists, but now it is 'per-child data' for the SPI bus. Each child of the
-SPI bus is a SPI slave. The information that was stored in the
-driver-specific slave structure can now be port in private data for the
-SPI bus.
-
-For example, struct tegra_spi_slave looks like this:
-
-struct tegra_spi_slave {
- struct spi_slave slave;
- struct tegra_spi_ctrl *ctrl;
-};
-
-In this case 'slave' will be in per-child data, and 'ctrl' will be in the
-SPI's buses private data.
-
-
-0. How long does this take?
-
-You should be able to complete this within 2 hours, including testing but
-excluding preparing the patches. The API is basically the same as before
-with only minor changes:
-
-- methods to set speed and mode are separated out
-- cs_info is used to get information on a chip select
-
-
-1. Enable driver mode for SPI and SPI flash
-
-Add these to your board config:
-
-CONFIG_DM_SPI
-CONFIG_DM_SPI_FLASH
-
-
-2. Add the skeleton
-
-Put this code at the bottom of your existing driver file:
-
-struct spi_slave *spi_setup_slave(unsigned int busnum, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- return NULL;
-}
-
-struct spi_slave *spi_setup_slave_fdt(const void *blob, int slave_node,
- int spi_node)
-{
- return NULL;
-}
-
-static int exynos_spi_ofdata_to_platdata(struct udevice *dev)
-{
- return -ENODEV;
-}
-
-static int exynos_spi_probe(struct udevice *dev)
-{
- return -ENODEV;
-}
-
-static int exynos_spi_remove(struct udevice *dev)
-{
- return -ENODEV;
-}
-
-static int exynos_spi_claim_bus(struct udevice *dev)
-{
-
- return -ENODEV;
-}
-
-static int exynos_spi_release_bus(struct udevice *dev)
-{
-
- return -ENODEV;
-}
-
-static int exynos_spi_xfer(struct udevice *dev, unsigned int bitlen,
- const void *dout, void *din, unsigned long flags)
-{
-
- return -ENODEV;
-}
-
-static int exynos_spi_set_speed(struct udevice *dev, uint speed)
-{
- return -ENODEV;
-}
-
-static int exynos_spi_set_mode(struct udevice *dev, uint mode)
-{
- return -ENODEV;
-}
-
-static int exynos_cs_info(struct udevice *bus, uint cs,
- struct spi_cs_info *info)
-{
- return -ENODEV;
-}
-
-static const struct dm_spi_ops exynos_spi_ops = {
- .claim_bus = exynos_spi_claim_bus,
- .release_bus = exynos_spi_release_bus,
- .xfer = exynos_spi_xfer,
- .set_speed = exynos_spi_set_speed,
- .set_mode = exynos_spi_set_mode,
- .cs_info = exynos_cs_info,
-};
-
-static const struct udevice_id exynos_spi_ids[] = {
- { .compatible = "samsung,exynos-spi" },
- { }
-};
-
-U_BOOT_DRIVER(exynos_spi) = {
- .name = "exynos_spi",
- .id = UCLASS_SPI,
- .of_match = exynos_spi_ids,
- .ops = &exynos_spi_ops,
- .ofdata_to_platdata = exynos_spi_ofdata_to_platdata,
- .probe = exynos_spi_probe,
- .remove = exynos_spi_remove,
-};
-
-
-3. Replace 'exynos' in the above code with your driver name
-
-
-4. #ifdef out all of the code in your driver except for the above
-
-This will allow you to get it building, which means you can work
-incrementally. Since all the methods return an error initially, there is
-less chance that you will accidentally leave something in.
-
-Also, even though your conversion is basically a rewrite, it might help
-reviewers if you leave functions in the same place in the file,
-particularly for large drivers.
-
-
-5. Add some includes
-
-Add these includes to your driver:
-
-#include <dm.h>
-#include <errno.h>
-
-
-6. Build
-
-At this point you should be able to build U-Boot for your board with the
-empty SPI driver. You still have empty methods in your driver, but we will
-write these one by one.
-
-7. Set up your platform data structure
-
-This will hold the information your driver to operate, like its hardware
-address or maximum frequency.
-
-You may already have a struct like this, or you may need to create one
-from some of the #defines or global variables in the driver.
-
-Note that this information is not the run-time information. It should not
-include state that changes. It should be fixed throughout the live of
-U-Boot. Run-time information comes later.
-
-Here is what was in the exynos spi driver:
-
-struct spi_bus {
- enum periph_id periph_id;
- s32 frequency; /* Default clock frequency, -1 for none */
- struct exynos_spi *regs;
- int inited; /* 1 if this bus is ready for use */
- int node;
- uint deactivate_delay_us; /* Delay to wait after deactivate */
-};
-
-Of these, inited is handled by DM and node is the device tree node, which
-DM tells you. The name is not quite right. So in this case we would use:
-
-struct exynos_spi_platdata {
- enum periph_id periph_id;
- s32 frequency; /* Default clock frequency, -1 for none */
- struct exynos_spi *regs;
- uint deactivate_delay_us; /* Delay to wait after deactivate */
-};
-
-
-8a. Write ofdata_to_platdata() [for device tree only]
-
-This method will convert information in the device tree node into a C
-structure in your driver (called platform data). If you are not using
-device tree, go to 8b.
-
-DM will automatically allocate the struct for us when we are using device
-tree, but we need to tell it the size:
-
-U_BOOT_DRIVER(spi_exynos) = {
-...
- .platdata_auto_alloc_size = sizeof(struct exynos_spi_platdata),
-
-
-Here is a sample function. It gets a pointer to the platform data and
-fills in the fields from device tree.
-
-static int exynos_spi_ofdata_to_platdata(struct udevice *bus)
-{
- struct exynos_spi_platdata *plat = bus->platdata;
- const void *blob = gd->fdt_blob;
- int node = dev_of_offset(bus);
-
- plat->regs = (struct exynos_spi *)fdtdec_get_addr(blob, node, "reg");
- plat->periph_id = pinmux_decode_periph_id(blob, node);
-
- if (plat->periph_id == PERIPH_ID_NONE) {
- debug("%s: Invalid peripheral ID %d\n", __func__,
- plat->periph_id);
- return -FDT_ERR_NOTFOUND;
- }
-
- /* Use 500KHz as a suitable default */
- plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
- 500000);
- plat->deactivate_delay_us = fdtdec_get_int(blob, node,
- "spi-deactivate-delay", 0);
- debug("%s: regs=%p, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
- __func__, plat->regs, plat->periph_id, plat->frequency,
- plat->deactivate_delay_us);
-
- return 0;
-}
-
-
-8b. Add the platform data [non-device-tree only]
-
-Specify this data in a U_BOOT_DEVICE() declaration in your board file:
-
-struct exynos_spi_platdata platdata_spi0 = {
- .periph_id = ...
- .frequency = ...
- .regs = ...
- .deactivate_delay_us = ...
-};
-
-U_BOOT_DEVICE(board_spi0) = {
- .name = "exynos_spi",
- .platdata = &platdata_spi0,
-};
-
-You will unfortunately need to put the struct definition into a header file
-in this case so that your board file can use it.
-
-
-9. Add the device private data
-
-Most devices have some private data which they use to keep track of things
-while active. This is the run-time information and needs to be stored in
-a structure. There is probably a structure in the driver that includes a
-'struct spi_slave', so you can use that.
-
-struct exynos_spi_slave {
- struct spi_slave slave;
- struct exynos_spi *regs;
- unsigned int freq; /* Default frequency */
- unsigned int mode;
- enum periph_id periph_id; /* Peripheral ID for this device */
- unsigned int fifo_size;
- int skip_preamble;
- struct spi_bus *bus; /* Pointer to our SPI bus info */
- ulong last_transaction_us; /* Time of last transaction end */
-};
-
-
-We should rename this to make its purpose more obvious, and get rid of
-the slave structure, so we have:
-
-struct exynos_spi_priv {
- struct exynos_spi *regs;
- unsigned int freq; /* Default frequency */
- unsigned int mode;
- enum periph_id periph_id; /* Peripheral ID for this device */
- unsigned int fifo_size;
- int skip_preamble;
- ulong last_transaction_us; /* Time of last transaction end */
-};
-
-
-DM can auto-allocate this also:
-
-U_BOOT_DRIVER(spi_exynos) = {
-...
- .priv_auto_alloc_size = sizeof(struct exynos_spi_priv),
-
-
-Note that this is created before the probe method is called, and destroyed
-after the remove method is called. It will be zeroed when the probe
-method is called.
-
-
-10. Add the probe() and remove() methods
-
-Note: It's a good idea to build repeatedly as you are working, to avoid a
-huge amount of work getting things compiling at the end.
-
-The probe method is supposed to set up the hardware. U-Boot used to use
-spi_setup_slave() to do this. So take a look at this function and see
-what you can copy out to set things up.
-
-
-static int exynos_spi_probe(struct udevice *bus)
-{
- struct exynos_spi_platdata *plat = dev_get_platdata(bus);
- struct exynos_spi_priv *priv = dev_get_priv(bus);
-
- priv->regs = plat->regs;
- if (plat->periph_id == PERIPH_ID_SPI1 ||
- plat->periph_id == PERIPH_ID_SPI2)
- priv->fifo_size = 64;
- else
- priv->fifo_size = 256;
-
- priv->skip_preamble = 0;
- priv->last_transaction_us = timer_get_us();
- priv->freq = plat->frequency;
- priv->periph_id = plat->periph_id;
-
- return 0;
-}
-
-This implementation doesn't actually touch the hardware, which is somewhat
-unusual for a driver. In this case we will do that when the device is
-claimed by something that wants to use the SPI bus.
-
-For remove we could shut down the clocks, but in this case there is
-nothing to do. DM frees any memory that it allocated, so we can just
-remove exynos_spi_remove() and its reference in U_BOOT_DRIVER.
-
-
-11. Implement set_speed()
-
-This should set up clocks so that the SPI bus is running at the right
-speed. With the old API spi_claim_bus() would normally do this and several
-of the following functions, so let's look at that function:
-
-int spi_claim_bus(struct spi_slave *slave)
-{
- struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
- struct exynos_spi *regs = spi_slave->regs;
- u32 reg = 0;
- int ret;
-
- ret = set_spi_clk(spi_slave->periph_id,
- spi_slave->freq);
- if (ret < 0) {
- debug("%s: Failed to setup spi clock\n", __func__);
- return ret;
- }
-
- exynos_pinmux_config(spi_slave->periph_id, PINMUX_FLAG_NONE);
-
- spi_flush_fifo(slave);
-
- reg = readl(®s->ch_cfg);
- reg &= ~(SPI_CH_CPHA_B | SPI_CH_CPOL_L);
-
- if (spi_slave->mode & SPI_CPHA)
- reg |= SPI_CH_CPHA_B;
-
- if (spi_slave->mode & SPI_CPOL)
- reg |= SPI_CH_CPOL_L;
-
- writel(reg, ®s->ch_cfg);
- writel(SPI_FB_DELAY_180, ®s->fb_clk);
-
- return 0;
-}
-
-
-It sets up the speed, mode, pinmux, feedback delay and clears the FIFOs.
-With DM these will happen in separate methods.
-
-
-Here is an example for the speed part:
-
-static int exynos_spi_set_speed(struct udevice *bus, uint speed)
-{
- struct exynos_spi_platdata *plat = bus->platdata;
- struct exynos_spi_priv *priv = dev_get_priv(bus);
- int ret;
-
- if (speed > plat->frequency)
- speed = plat->frequency;
- ret = set_spi_clk(priv->periph_id, speed);
- if (ret)
- return ret;
- priv->freq = speed;
- debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
-
- return 0;
-}
-
-
-12. Implement set_mode()
-
-This should adjust the SPI mode (polarity, etc.). Again this code probably
-comes from the old spi_claim_bus(). Here is an example:
-
-
-static int exynos_spi_set_mode(struct udevice *bus, uint mode)
-{
- struct exynos_spi_priv *priv = dev_get_priv(bus);
- uint32_t reg;
-
- reg = readl(&priv->regs->ch_cfg);
- reg &= ~(SPI_CH_CPHA_B | SPI_CH_CPOL_L);
-
- if (mode & SPI_CPHA)
- reg |= SPI_CH_CPHA_B;
-
- if (mode & SPI_CPOL)
- reg |= SPI_CH_CPOL_L;
-
- writel(reg, &priv->regs->ch_cfg);
- priv->mode = mode;
- debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
-
- return 0;
-}
-
-
-13. Implement claim_bus()
-
-This is where a client wants to make use of the bus, so claims it first.
-At this point we need to make sure everything is set up ready for data
-transfer. Note that this function is wholly internal to the driver - at
-present the SPI uclass never calls it.
-
-Here again we look at the old claim function and see some code that is
-needed. It is anything unrelated to speed and mode:
-
-static int exynos_spi_claim_bus(struct udevice *bus)
-{
- struct exynos_spi_priv *priv = dev_get_priv(bus);
-
- exynos_pinmux_config(priv->periph_id, PINMUX_FLAG_NONE);
- spi_flush_fifo(priv->regs);
-
- writel(SPI_FB_DELAY_180, &priv->regs->fb_clk);
-
- return 0;
-}
-
-The spi_flush_fifo() function is in the removed part of the code, so we
-need to expose it again (perhaps with an #endif before it and '#if 0'
-after it). It only needs access to priv->regs which is why we have
-passed that in:
-
-/**
- * Flush spi tx, rx fifos and reset the SPI controller
- *
- * @param regs Pointer to SPI registers
- */
-static void spi_flush_fifo(struct exynos_spi *regs)
-{
- clrsetbits_le32(®s->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
- clrbits_le32(®s->ch_cfg, SPI_CH_RST);
- setbits_le32(®s->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
-}
-
-
-14. Implement release_bus()
-
-This releases the bus - in our example the old code in spi_release_bus()
-is a call to spi_flush_fifo, so we add:
-
-static int exynos_spi_release_bus(struct udevice *bus)
-{
- struct exynos_spi_priv *priv = dev_get_priv(bus);
-
- spi_flush_fifo(priv->regs);
-
- return 0;
-}
-
-
-15. Implement xfer()
-
-This is the final method that we need to create, and it is where all the
-work happens. The method parameters are the same as the old spi_xfer() with
-the addition of a 'struct udevice' so conversion is pretty easy. Start
-by copying the contents of spi_xfer() to your new xfer() method and proceed
-from there.
-
-If (flags & SPI_XFER_BEGIN) is non-zero then xfer() normally calls an
-activate function, something like this:
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
-
- /* If it's too soon to do another transaction, wait */
- if (spi_slave->bus->deactivate_delay_us &&
- spi_slave->last_transaction_us) {
- ulong delay_us; /* The delay completed so far */
- delay_us = timer_get_us() - spi_slave->last_transaction_us;
- if (delay_us < spi_slave->bus->deactivate_delay_us)
- udelay(spi_slave->bus->deactivate_delay_us - delay_us);
- }
-
- clrbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT);
- debug("Activate CS, bus %d\n", spi_slave->slave.bus);
- spi_slave->skip_preamble = spi_slave->mode & SPI_PREAMBLE;
-}
-
-The new version looks like this:
-
-static void spi_cs_activate(struct udevice *dev)
-{
- struct udevice *bus = dev->parent;
- struct exynos_spi_platdata *pdata = dev_get_platdata(bus);
- struct exynos_spi_priv *priv = dev_get_priv(bus);
-
- /* If it's too soon to do another transaction, wait */
- if (pdata->deactivate_delay_us &&
- priv->last_transaction_us) {
- ulong delay_us; /* The delay completed so far */
- delay_us = timer_get_us() - priv->last_transaction_us;
- if (delay_us < pdata->deactivate_delay_us)
- udelay(pdata->deactivate_delay_us - delay_us);
- }
-
- clrbits_le32(&priv->regs->cs_reg, SPI_SLAVE_SIG_INACT);
- debug("Activate CS, bus '%s'\n", bus->name);
- priv->skip_preamble = priv->mode & SPI_PREAMBLE;
-}
-
-All we have really done here is change the pointers and print the device name
-instead of the bus number. Other local static functions can be treated in
-the same way.
-
-
-16. Set up the per-child data and child pre-probe function
-
-To minimise the pain and complexity of the SPI subsystem while the driver
-model change-over is in place, struct spi_slave is used to reference a
-SPI bus slave, even though that slave is actually a struct udevice. In fact
-struct spi_slave is the device's child data. We need to make sure this space
-is available. It is possible to allocate more space that struct spi_slave
-needs, but this is the minimum.
-
-U_BOOT_DRIVER(exynos_spi) = {
-...
- .per_child_auto_alloc_size = sizeof(struct spi_slave),
-}
-
-
-17. Optional: Set up cs_info() if you want it
-
-Sometimes it is useful to know whether a SPI chip select is valid, but this
-is not obvious from outside the driver. In this case you can provide a
-method for cs_info() to deal with this. If you don't provide it, then the
-device tree will be used to determine what chip selects are valid.
-
-Return -ENODEV if the supplied chip select is invalid, or 0 if it is valid.
-If you don't provide the cs_info() method, -ENODEV is assumed for all
-chip selects that do not appear in the device tree.
-
-
-18. Test it
-
-Now that you have the code written and it compiles, try testing it using
-the 'sf test' command. You may need to enable CONFIG_CMD_SF_TEST for your
-board.
-
-
-19. Prepare patches and send them to the mailing lists
-
-You can use 'tools/patman/patman' to prepare, check and send patches for
-your work. See the README for details.
-
-20. A little note about SPI uclass features:
-
-The SPI uclass keeps some information about each device 'dev' on the bus:
-
- struct dm_spi_slave_platdata - this is device_get_parent_platdata(dev)
- This is where the chip select number is stored, along with
- the default bus speed and mode. It is automatically read
- from the device tree in spi_child_post_bind(). It must not
- be changed at run-time after being set up because platform
- data is supposed to be immutable at run-time.
- struct spi_slave - this is device_get_parentdata(dev)
- Already mentioned above. It holds run-time information about
- the device.
-
-There are also some SPI uclass methods that get called behind the scenes:
-
- spi_post_bind() - called when a new bus is bound
- This scans the device tree for devices on the bus, and binds
- each one. This in turn causes spi_child_post_bind() to be
- called for each, which reads the device tree information
- into the parent (per-child) platform data.
- spi_child_post_bind() - called when a new child is bound
- As mentioned above this reads the device tree information
- into the per-child platform data
- spi_child_pre_probe() - called before a new child is probed
- This sets up the mode and speed in struct spi_slave by
- copying it from the parent's platform data for this child.
- It also sets the 'dev' pointer, needed to permit passing
- 'struct spi_slave' around the place without needing a
- separate 'struct udevice' pointer.
-
-The above housekeeping makes it easier to write your SPI driver.
diff --git a/doc/driver-model/usb-info.rst b/doc/driver-model/usb-info.rst
new file mode 100644
index 0000000..1817df4
--- /dev/null
+++ b/doc/driver-model/usb-info.rst
@@ -0,0 +1,423 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+How USB works with driver model
+===============================
+
+Introduction
+------------
+
+Driver model USB support makes use of existing features but changes how
+drivers are found. This document provides some information intended to help
+understand how things work with USB in U-Boot when driver model is enabled.
+
+
+Enabling driver model for USB
+-----------------------------
+
+A new CONFIG_DM_USB option is provided to enable driver model for USB. This
+causes the USB uclass to be included, and drops the equivalent code in
+usb.c. In particular the usb_init() function is then implemented by the
+uclass.
+
+
+Support for EHCI and XHCI
+-------------------------
+
+So far OHCI is not supported. Both EHCI and XHCI drivers should be declared
+as drivers in the USB uclass. For example:
+
+.. code-block:: c
+
+ static const struct udevice_id ehci_usb_ids[] = {
+ { .compatible = "nvidia,tegra20-ehci", .data = USB_CTLR_T20 },
+ { .compatible = "nvidia,tegra30-ehci", .data = USB_CTLR_T30 },
+ { .compatible = "nvidia,tegra114-ehci", .data = USB_CTLR_T114 },
+ { }
+ };
+
+ U_BOOT_DRIVER(usb_ehci) = {
+ .name = "ehci_tegra",
+ .id = UCLASS_USB,
+ .of_match = ehci_usb_ids,
+ .ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
+ .probe = tegra_ehci_usb_probe,
+ .remove = tegra_ehci_usb_remove,
+ .ops = &ehci_usb_ops,
+ .platdata_auto_alloc_size = sizeof(struct usb_platdata),
+ .priv_auto_alloc_size = sizeof(struct fdt_usb),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+ };
+
+Here ehci_usb_ids is used to list the controllers that the driver supports.
+Each has its own data value. Controllers must be in the UCLASS_USB uclass.
+
+The ofdata_to_platdata() method allows the controller driver to grab any
+necessary settings from the device tree.
+
+The ops here are ehci_usb_ops. All EHCI drivers will use these same ops in
+most cases, since they are all EHCI-compatible. For EHCI there are also some
+special operations that can be overridden when calling ehci_register().
+
+The driver can use priv_auto_alloc_size to set the size of its private data.
+This can hold run-time information needed by the driver for operation. It
+exists when the device is probed (not when it is bound) and is removed when
+the driver is removed.
+
+Note that usb_platdata is currently only used to deal with setting up a bus
+in USB device mode (OTG operation). It can be omitted if that is not
+supported.
+
+The driver's probe() method should do the basic controller init and then
+call ehci_register() to register itself as an EHCI device. It should call
+ehci_deregister() in the remove() method. Registering a new EHCI device
+does not by itself cause the bus to be scanned.
+
+The old ehci_hcd_init() function is no-longer used. Nor is it necessary to
+set up the USB controllers from board init code. When 'usb start' is used,
+each controller will be probed and its bus scanned.
+
+XHCI works in a similar way.
+
+
+Data structures
+---------------
+
+The following primary data structures are in use:
+
+- struct usb_device:
+ This holds information about a device on the bus. All devices have
+ this structure, even the root hub. The controller itself does not
+ have this structure. You can access it for a device 'dev' with
+ dev_get_parent_priv(dev). It matches the old structure except that the
+ parent and child information is not present (since driver model
+ handles that). Once the device is set up, you can find the device
+ descriptor and current configuration descriptor in this structure.
+
+- struct usb_platdata:
+ This holds platform data for a controller. So far this is only used
+ as a work-around for controllers which can act as USB devices in OTG
+ mode, since the gadget framework does not use driver model.
+
+- struct usb_dev_platdata:
+ This holds platform data for a device. You can access it for a
+ device 'dev' with dev_get_parent_platdata(dev). It holds the device
+ address and speed - anything that can be determined before the device
+ driver is actually set up. When probing the bus this structure is
+ used to provide essential information to the device driver.
+
+- struct usb_bus_priv:
+ This is private information for each controller, maintained by the
+ controller uclass. It is mostly used to keep track of the next
+ device address to use.
+
+Of these, only struct usb_device was used prior to driver model.
+
+
+USB buses
+---------
+
+Given a controller, you know the bus - it is the one attached to the
+controller. Each controller handles exactly one bus. Every controller has a
+root hub attached to it. This hub, which is itself a USB device, can provide
+one or more 'ports' to which additional devices can be attached. It is
+possible to power up a hub and find out which of its ports have devices
+attached.
+
+Devices are given addresses starting at 1. The root hub is always address 1,
+and from there the devices are numbered in sequence. The USB uclass takes
+care of this numbering automatically during enumeration.
+
+USB devices are enumerated by finding a device on a particular hub, and
+setting its address to the next available address. The USB bus stretches out
+in a tree structure, potentially with multiple hubs each with several ports
+and perhaps other hubs. Some hubs will have their own power since otherwise
+the 5V 500mA power supplied by the controller will not be sufficient to run
+very many devices.
+
+Enumeration in U-Boot takes a long time since devices are probed one at a
+time, and each is given sufficient time to wake up and announce itself. The
+timeouts are set for the slowest device.
+
+Up to 127 devices can be on each bus. USB has four bus speeds: low
+(1.5Mbps), full (12Mbps), high (480Mbps) which is only available with USB2
+and newer (EHCI), and super (5Gbps) which is only available with USB3 and
+newer (XHCI). If you connect a super-speed device to a high-speed hub, you
+will only get high-speed.
+
+
+USB operations
+--------------
+
+As before driver model, messages can be sent using submit_bulk_msg() and the
+like. These are now implemented by the USB uclass and route through the
+controller drivers. Note that messages are not sent to the driver of the
+device itself - i.e. they don't pass down the stack to the controller.
+U-Boot simply finds the controller to which the device is attached, and sends
+the message there with an appropriate 'pipe' value so it can be addressed
+properly. Having said that, the USB device which should receive the message
+is passed in to the driver methods, for use by sandbox. This design decision
+is open for review and the code impact of changing it is small since the
+methods are typically implemented by the EHCI and XHCI stacks.
+
+Controller drivers (in UCLASS_USB) themselves provide methods for sending
+each message type. For XHCI an additional alloc_device() method is provided
+since XHCI needs to allocate a device context before it can even read the
+device's descriptor.
+
+These methods use a 'pipe' which is a collection of bit fields used to
+describe the type of message, direction of transfer and the intended
+recipient (device number).
+
+
+USB Devices
+-----------
+
+USB devices are found using a simple algorithm which works through the
+available hubs in a depth-first search. Devices can be in any uclass, but
+are attached to a parent hub (or controller in the case of the root hub) and
+so have parent data attached to them (this is struct usb_device).
+
+By the time the device's probe() method is called, it is enumerated and is
+ready to talk to the host.
+
+The enumeration process needs to work out which driver to attach to each USB
+device. It does this by examining the device class, interface class, vendor
+ID, product ID, etc. See struct usb_driver_entry for how drivers are matched
+with USB devices - you can use the USB_DEVICE() macro to declare a USB
+driver. For example, usb_storage.c defines a USB_DEVICE() to handle storage
+devices, and it will be used for all USB devices which match.
+
+
+
+Technical details on enumeration flow
+-------------------------------------
+
+It is useful to understand precisely how a USB bus is enumerating to avoid
+confusion when dealing with USB devices.
+
+Device initialisation happens roughly like this:
+
+- At some point the 'usb start' command is run
+- This calls usb_init() which works through each controller in turn
+- The controller is probed(). This does no enumeration.
+- Then usb_scan_bus() is called. This calls usb_scan_device() to scan the
+ (only) device that is attached to the controller - a root hub
+- usb_scan_device() sets up a fake struct usb_device and calls
+ usb_setup_device(), passing the port number to be scanned, in this case
+ port 0
+- usb_setup_device() first calls usb_prepare_device() to set the device
+ address, then usb_select_config() to select the first configuration
+- at this point the device is enumerated but we do not have a real struct
+ udevice for it. But we do have the descriptor in struct usb_device so we can
+ use this to figure out what driver to use
+- back in usb_scan_device(), we call usb_find_child() to try to find an
+ existing device which matches the one we just found on the bus. This can
+ happen if the device is mentioned in the device tree, or if we previously
+ scanned the bus and so the device was created before
+- if usb_find_child() does not find an existing device, we call
+ usb_find_and_bind_driver() which tries to bind one
+- usb_find_and_bind_driver() searches all available USB drivers (declared
+ with USB_DEVICE()). If it finds a match it binds that driver to create a
+ new device.
+- If it does not, it binds a generic driver. A generic driver is good enough
+ to allow access to the device (sending it packets, etc.) but all
+ functionality will need to be implemented outside the driver model.
+- in any case, when usb_find_child() and/or usb_find_and_bind_driver() are
+ done, we have a device with the correct uclass. At this point we want to
+ probe the device
+- first we store basic information about the new device (address, port,
+ speed) in its parent platform data. We cannot store it its private data
+ since that will not exist until the device is probed.
+- then we call device_probe() which probes the device
+- the first probe step is actually the USB controller's (or USB hubs's)
+ child_pre_probe() method. This gets called before anything else and is
+ intended to set up a child device ready to be used with its parent bus. For
+ USB this calls usb_child_pre_probe() which grabs the information that was
+ stored in the parent platform data and stores it in the parent private data
+ (which is struct usb_device, a real one this time). It then calls
+ usb_select_config() again to make sure that everything about the device is
+ set up
+- note that we have called usb_select_config() twice. This is inefficient
+ but the alternative is to store additional information in the platform data.
+ The time taken is minimal and this way is simpler
+- at this point the device is set up and ready for use so far as the USB
+ subsystem is concerned
+- the device's probe() method is then called. It can send messages and do
+ whatever else it wants to make the device work.
+
+Note that the first device is always a root hub, and this must be scanned to
+find any devices. The above steps will have created a hub (UCLASS_USB_HUB),
+given it address 1 and set the configuration.
+
+For hubs, the hub uclass has a post_probe() method. This means that after
+any hub is probed, the uclass gets to do some processing. In this case
+usb_hub_post_probe() is called, and the following steps take place:
+
+- usb_hub_post_probe() calls usb_hub_scan() to scan the hub, which in turn
+ calls usb_hub_configure()
+- hub power is enabled
+- we loop through each port on the hub, performing the same steps for each
+- first, check if there is a device present. This happens in
+ usb_hub_port_connect_change(). If so, then usb_scan_device() is called to
+ scan the device, passing the appropriate port number.
+- you will recognise usb_scan_device() from the steps above. It sets up the
+ device ready for use. If it is a hub, it will scan that hub before it
+ continues here (recursively, depth-first)
+- once all hub ports are scanned in this way, the hub is ready for use and
+ all of its downstream devices also
+- additional controllers are scanned in the same way
+
+The above method has some nice properties:
+
+- the bus enumeration happens by virtue of driver model's natural device flow
+- most logic is in the USB controller and hub uclasses; the actual device
+ drivers do not need to know they are on a USB bus, at least so far as
+ enumeration goes
+- hub scanning happens automatically after a hub is probed
+
+
+Hubs
+----
+
+USB hubs are scanned as in the section above. While hubs have their own
+uclass, they share some common elements with controllers:
+
+- they both attach private data to their children (struct usb_device,
+ accessible for a child with dev_get_parent_priv(child))
+- they both use usb_child_pre_probe() to set up their children as proper USB
+ devices
+
+
+Example - Mass Storage
+----------------------
+
+As an example of a USB device driver, see usb_storage.c. It uses its own
+uclass and declares itself as follows:
+
+.. code-block:: c
+
+ U_BOOT_DRIVER(usb_mass_storage) = {
+ .name = "usb_mass_storage",
+ .id = UCLASS_MASS_STORAGE,
+ .of_match = usb_mass_storage_ids,
+ .probe = usb_mass_storage_probe,
+ };
+
+ static const struct usb_device_id mass_storage_id_table[] = {
+ { .match_flags = USB_DEVICE_ID_MATCH_INT_CLASS,
+ .bInterfaceClass = USB_CLASS_MASS_STORAGE},
+ { } /* Terminating entry */
+ };
+
+ USB_DEVICE(usb_mass_storage, mass_storage_id_table);
+
+The USB_DEVICE() macro attaches the given table of matching information to
+the given driver. Note that the driver is declared in U_BOOT_DRIVER() as
+'usb_mass_storage' and this must match the first parameter of USB_DEVICE.
+
+When usb_find_and_bind_driver() is called on a USB device with the
+bInterfaceClass value of USB_CLASS_MASS_STORAGE, it will automatically find
+this driver and use it.
+
+
+Counter-example: USB Ethernet
+-----------------------------
+
+As an example of the old way of doing things, see usb_ether.c. When the bus
+is scanned, all Ethernet devices will be created as generic USB devices (in
+uclass UCLASS_USB_DEV_GENERIC). Then, when the scan is completed,
+usb_host_eth_scan() will be called. This looks through all the devices on
+each bus and manually figures out which are Ethernet devices in the ways of
+yore.
+
+In fact, usb_ether should be moved to driver model. Each USB Ethernet driver
+(e.g drivers/usb/eth/asix.c) should include a USB_DEVICE() declaration, so
+that it will be found as part of normal USB enumeration. Then, instead of a
+generic USB driver, a real (driver-model-aware) driver will be used. Since
+Ethernet now supports driver model, this should be fairly easy to achieve,
+and then usb_ether.c and the usb_host_eth_scan() will melt away.
+
+
+Sandbox
+-------
+
+All driver model uclasses must have tests and USB is no exception. To
+achieve this, a sandbox USB controller is provided. This can make use of
+emulation drivers which pretend to be USB devices. Emulations are provided
+for a hub and a flash stick. These are enough to create a pretend USB bus
+(defined by the sandbox device tree sandbox.dts) which can be scanned and
+used.
+
+Tests in test/dm/usb.c make use of this feature. It allows much of the USB
+stack to be tested without real hardware being needed.
+
+Here is an example device tree fragment:
+
+.. code-block:: none
+
+ usb@1 {
+ compatible = "sandbox,usb";
+ hub {
+ compatible = "usb-hub";
+ usb,device-class = <USB_CLASS_HUB>;
+ hub-emul {
+ compatible = "sandbox,usb-hub";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ flash-stick {
+ reg = <0>;
+ compatible = "sandbox,usb-flash";
+ sandbox,filepath = "flash.bin";
+ };
+ };
+ };
+ };
+
+This defines a single controller, containing a root hub (which is required).
+The hub is emulated by a hub emulator, and the emulated hub has a single
+flash stick to emulate on one of its ports.
+
+When 'usb start' is used, the following 'dm tree' output will be available::
+
+ usb [ + ] `-- usb@1
+ usb_hub [ + ] `-- hub
+ usb_emul [ + ] |-- hub-emul
+ usb_emul [ + ] | `-- flash-stick
+ usb_mass_st [ + ] `-- usb_mass_storage
+
+
+This may look confusing. Most of it mirrors the device tree, but the
+'usb_mass_storage' device is not in the device tree. This is created by
+usb_find_and_bind_driver() based on the USB_DRIVER in usb_storage.c. While
+'flash-stick' is the emulation device, 'usb_mass_storage' is the real U-Boot
+USB device driver that talks to it.
+
+
+Future work
+-----------
+
+It is pretty uncommon to have a large USB bus with lots of hubs on an
+embedded system. In fact anything other than a root hub is uncommon. Still
+it would be possible to speed up enumeration in two ways:
+
+- breadth-first search would allow devices to be reset and probed in
+ parallel to some extent
+- enumeration could be lazy, in the sense that we could enumerate just the
+ root hub at first, then only progress to the next 'level' when a device is
+ used that we cannot find. This could be made easier if the devices were
+ statically declared in the device tree (which is acceptable for production
+ boards where the same, known, things are on each bus).
+
+But in common cases the current algorithm is sufficient.
+
+Other things that need doing:
+- Convert usb_ether to use driver model as described above
+- Test that keyboards work (and convert to driver model)
+- Move the USB gadget framework to driver model
+- Implement OHCI in driver model
+- Implement USB PHYs in driver model
+- Work out a clever way to provide lazy init for USB devices
+
+
+.. Simon Glass <sjg@chromium.org>
+.. 23-Mar-15
diff --git a/doc/driver-model/usb-info.txt b/doc/driver-model/usb-info.txt
deleted file mode 100644
index e07e5ba..0000000
--- a/doc/driver-model/usb-info.txt
+++ /dev/null
@@ -1,415 +0,0 @@
-How USB works with driver model
-===============================
-
-Introduction
-------------
-
-Driver model USB support makes use of existing features but changes how
-drivers are found. This document provides some information intended to help
-understand how things work with USB in U-Boot when driver model is enabled.
-
-
-Enabling driver model for USB
------------------------------
-
-A new CONFIG_DM_USB option is provided to enable driver model for USB. This
-causes the USB uclass to be included, and drops the equivalent code in
-usb.c. In particular the usb_init() function is then implemented by the
-uclass.
-
-
-Support for EHCI and XHCI
--------------------------
-
-So far OHCI is not supported. Both EHCI and XHCI drivers should be declared
-as drivers in the USB uclass. For example:
-
-static const struct udevice_id ehci_usb_ids[] = {
- { .compatible = "nvidia,tegra20-ehci", .data = USB_CTLR_T20 },
- { .compatible = "nvidia,tegra30-ehci", .data = USB_CTLR_T30 },
- { .compatible = "nvidia,tegra114-ehci", .data = USB_CTLR_T114 },
- { }
-};
-
-U_BOOT_DRIVER(usb_ehci) = {
- .name = "ehci_tegra",
- .id = UCLASS_USB,
- .of_match = ehci_usb_ids,
- .ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
- .probe = tegra_ehci_usb_probe,
- .remove = tegra_ehci_usb_remove,
- .ops = &ehci_usb_ops,
- .platdata_auto_alloc_size = sizeof(struct usb_platdata),
- .priv_auto_alloc_size = sizeof(struct fdt_usb),
- .flags = DM_FLAG_ALLOC_PRIV_DMA,
-};
-
-Here ehci_usb_ids is used to list the controllers that the driver supports.
-Each has its own data value. Controllers must be in the UCLASS_USB uclass.
-
-The ofdata_to_platdata() method allows the controller driver to grab any
-necessary settings from the device tree.
-
-The ops here are ehci_usb_ops. All EHCI drivers will use these same ops in
-most cases, since they are all EHCI-compatible. For EHCI there are also some
-special operations that can be overridden when calling ehci_register().
-
-The driver can use priv_auto_alloc_size to set the size of its private data.
-This can hold run-time information needed by the driver for operation. It
-exists when the device is probed (not when it is bound) and is removed when
-the driver is removed.
-
-Note that usb_platdata is currently only used to deal with setting up a bus
-in USB device mode (OTG operation). It can be omitted if that is not
-supported.
-
-The driver's probe() method should do the basic controller init and then
-call ehci_register() to register itself as an EHCI device. It should call
-ehci_deregister() in the remove() method. Registering a new EHCI device
-does not by itself cause the bus to be scanned.
-
-The old ehci_hcd_init() function is no-longer used. Nor is it necessary to
-set up the USB controllers from board init code. When 'usb start' is used,
-each controller will be probed and its bus scanned.
-
-XHCI works in a similar way.
-
-
-Data structures
----------------
-
-The following primary data structures are in use:
-
-- struct usb_device
- This holds information about a device on the bus. All devices have
- this structure, even the root hub. The controller itself does not
- have this structure. You can access it for a device 'dev' with
- dev_get_parent_priv(dev). It matches the old structure except that the
- parent and child information is not present (since driver model
- handles that). Once the device is set up, you can find the device
- descriptor and current configuration descriptor in this structure.
-
-- struct usb_platdata
- This holds platform data for a controller. So far this is only used
- as a work-around for controllers which can act as USB devices in OTG
- mode, since the gadget framework does not use driver model.
-
-- struct usb_dev_platdata
- This holds platform data for a device. You can access it for a
- device 'dev' with dev_get_parent_platdata(dev). It holds the device
- address and speed - anything that can be determined before the device
- driver is actually set up. When probing the bus this structure is
- used to provide essential information to the device driver.
-
-- struct usb_bus_priv
- This is private information for each controller, maintained by the
- controller uclass. It is mostly used to keep track of the next
- device address to use.
-
-Of these, only struct usb_device was used prior to driver model.
-
-
-USB buses
----------
-
-Given a controller, you know the bus - it is the one attached to the
-controller. Each controller handles exactly one bus. Every controller has a
-root hub attached to it. This hub, which is itself a USB device, can provide
-one or more 'ports' to which additional devices can be attached. It is
-possible to power up a hub and find out which of its ports have devices
-attached.
-
-Devices are given addresses starting at 1. The root hub is always address 1,
-and from there the devices are numbered in sequence. The USB uclass takes
-care of this numbering automatically during enumeration.
-
-USB devices are enumerated by finding a device on a particular hub, and
-setting its address to the next available address. The USB bus stretches out
-in a tree structure, potentially with multiple hubs each with several ports
-and perhaps other hubs. Some hubs will have their own power since otherwise
-the 5V 500mA power supplied by the controller will not be sufficient to run
-very many devices.
-
-Enumeration in U-Boot takes a long time since devices are probed one at a
-time, and each is given sufficient time to wake up and announce itself. The
-timeouts are set for the slowest device.
-
-Up to 127 devices can be on each bus. USB has four bus speeds: low
-(1.5Mbps), full (12Mbps), high (480Mbps) which is only available with USB2
-and newer (EHCI), and super (5Gbps) which is only available with USB3 and
-newer (XHCI). If you connect a super-speed device to a high-speed hub, you
-will only get high-speed.
-
-
-USB operations
---------------
-
-As before driver model, messages can be sent using submit_bulk_msg() and the
-like. These are now implemented by the USB uclass and route through the
-controller drivers. Note that messages are not sent to the driver of the
-device itself - i.e. they don't pass down the stack to the controller.
-U-Boot simply finds the controller to which the device is attached, and sends
-the message there with an appropriate 'pipe' value so it can be addressed
-properly. Having said that, the USB device which should receive the message
-is passed in to the driver methods, for use by sandbox. This design decision
-is open for review and the code impact of changing it is small since the
-methods are typically implemented by the EHCI and XHCI stacks.
-
-Controller drivers (in UCLASS_USB) themselves provide methods for sending
-each message type. For XHCI an additional alloc_device() method is provided
-since XHCI needs to allocate a device context before it can even read the
-device's descriptor.
-
-These methods use a 'pipe' which is a collection of bit fields used to
-describe the type of message, direction of transfer and the intended
-recipient (device number).
-
-
-USB Devices
------------
-
-USB devices are found using a simple algorithm which works through the
-available hubs in a depth-first search. Devices can be in any uclass, but
-are attached to a parent hub (or controller in the case of the root hub) and
-so have parent data attached to them (this is struct usb_device).
-
-By the time the device's probe() method is called, it is enumerated and is
-ready to talk to the host.
-
-The enumeration process needs to work out which driver to attach to each USB
-device. It does this by examining the device class, interface class, vendor
-ID, product ID, etc. See struct usb_driver_entry for how drivers are matched
-with USB devices - you can use the USB_DEVICE() macro to declare a USB
-driver. For example, usb_storage.c defines a USB_DEVICE() to handle storage
-devices, and it will be used for all USB devices which match.
-
-
-
-Technical details on enumeration flow
--------------------------------------
-
-It is useful to understand precisely how a USB bus is enumerating to avoid
-confusion when dealing with USB devices.
-
-Device initialisation happens roughly like this:
-
-- At some point the 'usb start' command is run
-- This calls usb_init() which works through each controller in turn
-- The controller is probed(). This does no enumeration.
-- Then usb_scan_bus() is called. This calls usb_scan_device() to scan the
-(only) device that is attached to the controller - a root hub
-- usb_scan_device() sets up a fake struct usb_device and calls
-usb_setup_device(), passing the port number to be scanned, in this case port
-0
-- usb_setup_device() first calls usb_prepare_device() to set the device
-address, then usb_select_config() to select the first configuration
-- at this point the device is enumerated but we do not have a real struct
-udevice for it. But we do have the descriptor in struct usb_device so we can
-use this to figure out what driver to use
-- back in usb_scan_device(), we call usb_find_child() to try to find an
-existing device which matches the one we just found on the bus. This can
-happen if the device is mentioned in the device tree, or if we previously
-scanned the bus and so the device was created before
-- if usb_find_child() does not find an existing device, we call
-usb_find_and_bind_driver() which tries to bind one
-- usb_find_and_bind_driver() searches all available USB drivers (declared
-with USB_DEVICE()). If it finds a match it binds that driver to create a new
-device.
-- If it does not, it binds a generic driver. A generic driver is good enough
-to allow access to the device (sending it packets, etc.) but all
-functionality will need to be implemented outside the driver model.
-- in any case, when usb_find_child() and/or usb_find_and_bind_driver() are
-done, we have a device with the correct uclass. At this point we want to
-probe the device
-- first we store basic information about the new device (address, port,
-speed) in its parent platform data. We cannot store it its private data
-since that will not exist until the device is probed.
-- then we call device_probe() which probes the device
-- the first probe step is actually the USB controller's (or USB hubs's)
-child_pre_probe() method. This gets called before anything else and is
-intended to set up a child device ready to be used with its parent bus. For
-USB this calls usb_child_pre_probe() which grabs the information that was
-stored in the parent platform data and stores it in the parent private data
-(which is struct usb_device, a real one this time). It then calls
-usb_select_config() again to make sure that everything about the device is
-set up
-- note that we have called usb_select_config() twice. This is inefficient
-but the alternative is to store additional information in the platform data.
-The time taken is minimal and this way is simpler
-- at this point the device is set up and ready for use so far as the USB
-subsystem is concerned
-- the device's probe() method is then called. It can send messages and do
-whatever else it wants to make the device work.
-
-Note that the first device is always a root hub, and this must be scanned to
-find any devices. The above steps will have created a hub (UCLASS_USB_HUB),
-given it address 1 and set the configuration.
-
-For hubs, the hub uclass has a post_probe() method. This means that after
-any hub is probed, the uclass gets to do some processing. In this case
-usb_hub_post_probe() is called, and the following steps take place:
-
-- usb_hub_post_probe() calls usb_hub_scan() to scan the hub, which in turn
-calls usb_hub_configure()
-- hub power is enabled
-- we loop through each port on the hub, performing the same steps for each
-- first, check if there is a device present. This happens in
-usb_hub_port_connect_change(). If so, then usb_scan_device() is called to
-scan the device, passing the appropriate port number.
-- you will recognise usb_scan_device() from the steps above. It sets up the
-device ready for use. If it is a hub, it will scan that hub before it
-continues here (recursively, depth-first)
-- once all hub ports are scanned in this way, the hub is ready for use and
-all of its downstream devices also
-- additional controllers are scanned in the same way
-
-The above method has some nice properties:
-
-- the bus enumeration happens by virtue of driver model's natural device flow
-- most logic is in the USB controller and hub uclasses; the actual device
-drivers do not need to know they are on a USB bus, at least so far as
-enumeration goes
-- hub scanning happens automatically after a hub is probed
-
-
-Hubs
-----
-
-USB hubs are scanned as in the section above. While hubs have their own
-uclass, they share some common elements with controllers:
-
-- they both attach private data to their children (struct usb_device,
-accessible for a child with dev_get_parent_priv(child))
-- they both use usb_child_pre_probe() to set up their children as proper USB
-devices
-
-
-Example - Mass Storage
-----------------------
-
-As an example of a USB device driver, see usb_storage.c. It uses its own
-uclass and declares itself as follows:
-
-U_BOOT_DRIVER(usb_mass_storage) = {
- .name = "usb_mass_storage",
- .id = UCLASS_MASS_STORAGE,
- .of_match = usb_mass_storage_ids,
- .probe = usb_mass_storage_probe,
-};
-
-static const struct usb_device_id mass_storage_id_table[] = {
- { .match_flags = USB_DEVICE_ID_MATCH_INT_CLASS,
- .bInterfaceClass = USB_CLASS_MASS_STORAGE},
- { } /* Terminating entry */
-};
-
-USB_DEVICE(usb_mass_storage, mass_storage_id_table);
-
-The USB_DEVICE() macro attaches the given table of matching information to
-the given driver. Note that the driver is declared in U_BOOT_DRIVER() as
-'usb_mass_storage' and this must match the first parameter of USB_DEVICE.
-
-When usb_find_and_bind_driver() is called on a USB device with the
-bInterfaceClass value of USB_CLASS_MASS_STORAGE, it will automatically find
-this driver and use it.
-
-
-Counter-example: USB Ethernet
------------------------------
-
-As an example of the old way of doing things, see usb_ether.c. When the bus
-is scanned, all Ethernet devices will be created as generic USB devices (in
-uclass UCLASS_USB_DEV_GENERIC). Then, when the scan is completed,
-usb_host_eth_scan() will be called. This looks through all the devices on
-each bus and manually figures out which are Ethernet devices in the ways of
-yore.
-
-In fact, usb_ether should be moved to driver model. Each USB Ethernet driver
-(e.g drivers/usb/eth/asix.c) should include a USB_DEVICE() declaration, so
-that it will be found as part of normal USB enumeration. Then, instead of a
-generic USB driver, a real (driver-model-aware) driver will be used. Since
-Ethernet now supports driver model, this should be fairly easy to achieve,
-and then usb_ether.c and the usb_host_eth_scan() will melt away.
-
-
-Sandbox
--------
-
-All driver model uclasses must have tests and USB is no exception. To
-achieve this, a sandbox USB controller is provided. This can make use of
-emulation drivers which pretend to be USB devices. Emulations are provided
-for a hub and a flash stick. These are enough to create a pretend USB bus
-(defined by the sandbox device tree sandbox.dts) which can be scanned and
-used.
-
-Tests in test/dm/usb.c make use of this feature. It allows much of the USB
-stack to be tested without real hardware being needed.
-
-Here is an example device tree fragment:
-
- usb@1 {
- compatible = "sandbox,usb";
- hub {
- compatible = "usb-hub";
- usb,device-class = <USB_CLASS_HUB>;
- hub-emul {
- compatible = "sandbox,usb-hub";
- #address-cells = <1>;
- #size-cells = <0>;
- flash-stick {
- reg = <0>;
- compatible = "sandbox,usb-flash";
- sandbox,filepath = "flash.bin";
- };
- };
- };
- };
-
-This defines a single controller, containing a root hub (which is required).
-The hub is emulated by a hub emulator, and the emulated hub has a single
-flash stick to emulate on one of its ports.
-
-When 'usb start' is used, the following 'dm tree' output will be available:
-
- usb [ + ] `-- usb@1
- usb_hub [ + ] `-- hub
- usb_emul [ + ] |-- hub-emul
- usb_emul [ + ] | `-- flash-stick
- usb_mass_st [ + ] `-- usb_mass_storage
-
-
-This may look confusing. Most of it mirrors the device tree, but the
-'usb_mass_storage' device is not in the device tree. This is created by
-usb_find_and_bind_driver() based on the USB_DRIVER in usb_storage.c. While
-'flash-stick' is the emulation device, 'usb_mass_storage' is the real U-Boot
-USB device driver that talks to it.
-
-
-Future work
------------
-
-It is pretty uncommon to have a large USB bus with lots of hubs on an
-embedded system. In fact anything other than a root hub is uncommon. Still
-it would be possible to speed up enumeration in two ways:
-
-- breadth-first search would allow devices to be reset and probed in
-parallel to some extent
-- enumeration could be lazy, in the sense that we could enumerate just the
-root hub at first, then only progress to the next 'level' when a device is
-used that we cannot find. This could be made easier if the devices were
-statically declared in the device tree (which is acceptable for production
-boards where the same, known, things are on each bus).
-
-But in common cases the current algorithm is sufficient.
-
-Other things that need doing:
-- Convert usb_ether to use driver model as described above
-- Test that keyboards work (and convert to driver model)
-- Move the USB gadget framework to driver model
-- Implement OHCI in driver model
-- Implement USB PHYs in driver model
-- Work out a clever way to provide lazy init for USB devices
-
---
-Simon Glass <sjg@chromium.org>
-23-Mar-15
diff --git a/doc/efi.rst b/doc/efi.rst
deleted file mode 100644
index 5337a55..0000000
--- a/doc/efi.rst
+++ /dev/null
@@ -1,22 +0,0 @@
-.. SPDX-License-Identifier: GPL-2.0+
-
-EFI subsystem
-=============
-
-Boot services
--------------
-
-.. kernel-doc:: lib/efi_loader/efi_boottime.c
- :internal:
-
-Image relocation
-~~~~~~~~~~~~~~~~
-
-.. kernel-doc:: lib/efi_loader/efi_image_loader.c
- :internal:
-
-Runtime services
-----------------
-
-.. kernel-doc:: lib/efi_loader/efi_runtime.c
- :internal:
diff --git a/doc/git-mailrc b/doc/git-mailrc
index a63b76b..fdfec85 100644
--- a/doc/git-mailrc
+++ b/doc/git-mailrc
@@ -28,6 +28,7 @@
alias jagan Jagan Teki <jagan@amarulasolutions.com>
alias jhersh Joe Hershberger <joe.hershberger@ni.com>
alias kevery Kever Yang <kever.yang@rock-chips.com>
+alias leyfoon Ley Foon Tan <ley.foon.tan@intel.com>
alias lukma Lukasz Majewski <lukma@denx.de>
alias macpaul Macpaul Lin <macpaul@andestech.com>
alias marex Marek Vasut <marex@denx.de>
@@ -35,6 +36,7 @@
alias masahiro Masahiro Yamada <yamada.masahiro@socionext.com>
alias mateusz Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
alias maxime Maxime Ripard <maxime.ripard@free-electrons.com>
+alias mbrugger Matthias Brugger <mbrugger@suse.com>
alias monstr Michal Simek <monstr@monstr.eu>
alias prom Minkyu Kang <mk7.kang@samsung.com>
alias ptomsich Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
@@ -45,7 +47,7 @@
alias stroese Stefan Roese <sr@denx.de>
alias trini Tom Rini <trini@konsulko.com>
alias wd Wolfgang Denk <wd@denx.de>
-alias prabhu_kush Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+alias priyankajain Priyanka Jain <priyanka.jain@nxp.com>
# Architecture aliases
alias arch arc, arm, m68k, microblaze, mips, nds32, nios2, powerpc, sandbox, superh, x86
@@ -65,7 +67,7 @@
alias s5pc samsung
alias samsung uboot, prom
alias snapdragon uboot, mateusz
-alias socfpga uboot, marex, dinh, simongoldschmidt
+alias socfpga uboot, marex, dinh, simongoldschmidt, leyfoon
alias sunxi uboot, jagan, maxime
alias tegra uboot, sjg, Tom Warren <twarren@nvidia.com>, Stephen Warren <swarren@nvidia.com>
alias tegra2 tegra
@@ -74,6 +76,9 @@
alias zynq uboot, monstr
alias rockchip uboot, sjg, kevery, ptomsich
+alias bcm283x uboot, mbrugger
+alias rpi uboot, mbrugger
+
alias m68k uboot, alisonwang, angelo_ts
alias coldfire m68k
@@ -87,12 +92,12 @@
alias nios uboot, Thomas Chou <thomas@wytron.com.tw>, smcnutt
alias nios2 nios
-alias powerpc uboot, afleming, stroese, wd, prabhu_kush, mariosix
+alias powerpc uboot, afleming, stroese, wd, priyankajain, mariosix
alias ppc powerpc
alias mpc8xx uboot, wd, Christophe Leroy <christophe.leroy@c-s.fr>
alias mpc83xx uboot, mariosix
-alias mpc85xx uboot, afleming, prabhu_kush
-alias mpc86xx uboot, afleming, prabhu_kush
+alias mpc85xx uboot, afleming, priyankajain
+alias mpc86xx uboot, afleming, priyankajain
alias sandbox sjg
alias sb sandbox
diff --git a/doc/imx/clk/ccf.txt b/doc/imx/clk/ccf.txt
new file mode 100644
index 0000000..36b60dc
--- /dev/null
+++ b/doc/imx/clk/ccf.txt
@@ -0,0 +1,101 @@
+Introduction:
+=============
+
+This documentation entry describes the Common Clock Framework [CCF]
+port from Linux kernel (v5.1.12) to U-Boot.
+
+This code is supposed to bring CCF to IMX based devices (imx6q, imx7
+imx8). Moreover, it also provides some common clock code, which would
+allow easy porting of CCF Linux code to other platforms.
+
+Design decisions:
+=================
+
+* U-Boot's driver model [DM] for clk differs from Linux CCF. The most
+ notably difference is the lack of support for hierarchical clocks and
+ "clock as a manager driver" (single clock DTS node acts as a starting
+ point for all other clocks).
+
+* The clk_get_rate() caches the previously read data if CLK_GET_RATE_NOCACHE
+ is not set (no need for recursive access).
+
+* On purpose the "manager" clk driver (clk-imx6q.c) is not using large
+ table to store pointers to clocks - e.g. clk[IMX6QDL_CLK_USDHC2_SEL] = ....
+ Instead we use udevice's linked list for the same class (UCLASS_CLK).
+
+ Rationale:
+ ----------
+ When porting the code as is from Linux, one would need ~1KiB of RAM to
+ store it. This is way too much if we do plan to use this driver in SPL.
+
+* The "central" structure of this patch series is struct udevice and its
+ uclass_priv field contains the struct clk pointer (to the originally created
+ one).
+
+* Up till now U-Boot's driver model (DM) CLK operates on udevice (main
+ access to clock is by udevice ops)
+ In the CCF the access to struct clk (embodying pointer to *dev) is
+ possible via dev_get_clk_ptr() (it is a wrapper on dev_get_uclass_priv()).
+
+* To keep things simple the struct udevice's uclass_priv pointer is used to
+ store back pointer to corresponding struct clk. However, it is possible to
+ modify clk-uclass.c file and add there struct uc_clk_priv, which would have
+ clock related members (like pointer to clk). As of this writing there is no
+ such need, so to avoid extra allocations (as it can be auto allocated by
+ setting .per_device_auto_alloc_size = sizeof(struct uc_clk_priv)) the
+ uclass_priv stores the pointer to struct clk.
+
+* It is advised to add common clock code (like already added rate and flags) to
+ the struct clk, which is a top level description of the clock.
+
+* U-Boot's driver model already provides the facility to automatically allocate
+ (via private_alloc_size) device private data (accessible via dev->priv).
+ It may look appealing to use this feature to allocate private structures for
+ CCF clk devices e.g. divider (struct clk_divider *divider) for IMX6Q clock.
+
+ The above feature had not been used for following reasons:
+ - The original CCF Linux kernel driver is the "manager" for clocks - it
+ decides when clock is instantiated (and when memory for it is allocated).
+
+ - Using it would change the original structure of the CCF code.
+
+ - To bind (via clk_register()) the clock device with U-Boot driver model we
+ first need udevice for it (the "chicken and egg problem").
+
+* I've added the clk_get_parent(), which reads parent's dev->uclass_priv to
+ provide parent's struct clk pointer. This seems the easiest way to get
+ child/parent relationship for struct clk in U-Boot's udevice based clocks.
+
+* Linux's CCF 'struct clk_core' corresponds to U-Boot's udevice in 'struct clk'.
+ Clock IP block agnostic flags from 'struct clk_core' (e.g. NOCACHE) have been
+ moved from this struct one level up to 'struct clk'.
+
+* For tests the new ./test/dm/clk_ccf.c and ./drivers/clk/clk_sandbox_ccf.c
+ files have been introduced. The latter setups the CCF clock structure for
+ sandbox by reusing, if possible, generic clock primitives - like divier
+ and mux. The former file provides code to tests this setup.
+
+ For sandbox new CONFIG_SANDBOX_CLK_CCF Kconfig define has been introduced.
+ All new primitives added for new architectures must have corresponding test
+ in the two aforementioned files.
+
+
+Testing (sandbox):
+==================
+
+make mrproper; make sandbox_defconfig; make -j4
+./u-boot -i -d arch/sandbox/dts/test.dtb
+=> ut dm clk
+
+or in a more "scriptable" way (with -v to print debug output):
+./u-boot --fdt arch/sandbox/dts/test.dtb --command "ut dm clk_ccf" -v
+
+To do:
+------
+
+* Use of OF_PLATDATA in the SPL setup for CCF - as it is now - the SPL grows
+ considerably and using CCF in boards with tiny resources (OCRAM) is
+ problematic.
+
+* On demand port other parts of CCF to U-Boot - as now only features _really_
+ needed by DM/DTS converted drivers are used.
diff --git a/doc/imx/common/imx6.txt b/doc/imx/common/imx6.txt
index eab8835..0b50611 100644
--- a/doc/imx/common/imx6.txt
+++ b/doc/imx/common/imx6.txt
@@ -88,3 +88,77 @@
Word 0x00000002: 9f027772 00000004
+NAND Boot on i.MX6 with SPL support
+--------------------------------------
+
+Writing/updating boot image in nand device is not straight forward in
+i.MX6 platform and it requires boot control block(BCB) to be configured.
+
+BCB contains two data structures, Firmware Configuration Block(FCB) and
+Discovered Bad Block Table(DBBT). FCB has nand timings, DBBT search area,
+and firmware. See IMX6DQRM Section 8.5.2.2
+for more information.
+
+We can't use 'nand write' command to write SPL/firmware image directly
+like other platforms does. So we need special setup to write BCB block
+as per IMX6QDL reference manual 'nandbcb update' command do that job.
+
+for nand boot, up on reset bootrom look for FCB structure in
+first block's if FCB found the nand timings are loaded for
+further reads. once FCB read done, DTTB will be loaded and
+finally firmware will be loaded which is boot image.
+
+cmd_nandbcb will create FCB these structures
+by taking mtd partition as an example.
+- initial code will erase entire partition
+- followed by FCB setup, like first 2 blocks for FCB/DBBT write,
+ and next block for FW1/SPL
+- write firmware at FW1 block and
+- finally write fcb/dttb in first 2 block.
+
+Typical NAND BCB layout:
+=======================
+
+ no.of blocks = partition size / erasesize
+ no.of fcb/dbbt blocks = 2
+ FW1 offset = no.of fcb/dbbt
+
+block 0 1 2
+ -------------------------------
+ |FCB/DBBT 0|FCB/DBBT 1| FW 1 |
+ --------------------------------
+
+On summary, nandbcb update will
+- erase the entire partition
+- create BCB by creating 2 FCB/BDDT block followed by
+ 1 FW blocks based on partition size and erasesize.
+- fill FCB/DBBT structures
+- write FW/SPL in FW1
+- write FCB/DBBT in first 2 blocks
+
+step-1: write SPL
+
+icorem6qdl> ext4load mmc 0:1 $loadaddr SPL
+39936 bytes read in 10 ms (3.8 MiB/s)
+
+icorem6qdl> nandbcb update $loadaddr spl $filesize
+device 0 offset 0x0, size 0x9c00
+Erasing at 0x1c0000 -- 100% complete.
+NAND fw write: 0x80000 offset, 0xb000 bytes written: OK
+
+step-2: write u-boot-dtb.img
+
+icorem6qdl> nand erase.part uboot
+
+NAND erase.part: device 0 offset 0x200000, size 0x200000
+Erasing at 0x3c0000 -- 100% complete.
+OK
+
+icorem6qdl> ext4load mmc 0:1 $loadaddr u-boot-dtb.img
+589094 bytes read in 37 ms (15.2 MiB/s)
+
+icorem6qdl> nand write ${loadaddr} uboot ${filesize}
+
+NAND write: device 0 offset 0x200000, size 0x8fd26
+ 589094 bytes written: OK
+icorem6qdl>
diff --git a/doc/index.rst b/doc/index.rst
index 0353c10..458f0d2 100644
--- a/doc/index.rst
+++ b/doc/index.rst
@@ -1,11 +1,81 @@
.. SPDX-License-Identifier: GPL-2.0+
-#######################
-U-Boot Developer Manual
-#######################
+.. _u-boot_doc:
+
+The U-Boot Documentation
+========================
+
+This is the top level of the U-Boot's documentation tree. U-Boot
+documentation, like the U-Boot itself, is very much a work in progress;
+that is especially true as we work to integrate our many scattered
+documents into a coherent whole. Please note that improvements to the
+documentation are welcome; join the U-Boot list at http://lists.denx.de
+if you want to help out.
.. toctree::
+ :maxdepth: 2
- efi
- linker_lists
- serial
+Unified Extensible Firmware (UEFI)
+----------------------------------
+
+U-Boot provides an implementation of the UEFI API allowing to run UEFI
+compliant software like Linux, GRUB, and iPXE. Furthermore U-Boot itself
+can be run an UEFI payload.
+
+.. toctree::
+ :maxdepth: 2
+
+ uefi/index
+
+Driver-Model documentation
+--------------------------
+
+The following holds information on the U-Boot device driver framework:
+driver-model, including the design details of itself and several driver
+subsystems.
+
+.. toctree::
+ :maxdepth: 2
+
+ driver-model/index
+
+U-Boot API documentation
+------------------------
+
+These books get into the details of how specific U-Boot subsystems work
+from the point of view of a U-Boot developer. Much of the information here
+is taken directly from the U-Boot source, with supplemental material added
+as needed (or at least as we managed to add it - probably *not* all that is
+needed).
+
+.. toctree::
+ :maxdepth: 2
+
+ api/index
+
+Architecture-specific doc
+-------------------------
+
+These books provide programming details about architecture-specific
+implementation.
+
+.. toctree::
+ :maxdepth: 2
+
+ arch/index
+
+Board-specific doc
+------------------
+
+These books provide details about board-specific information. They are
+organized in a vendor subdirectory.
+
+.. toctree::
+ :maxdepth: 2
+
+ board/index
+
+Indices and tables
+==================
+
+* :ref:`genindex`
diff --git a/doc/sphinx/kerneldoc.py b/doc/sphinx/kerneldoc.py
index fbedcc3..e536360 100644
--- a/doc/sphinx/kerneldoc.py
+++ b/doc/sphinx/kerneldoc.py
@@ -39,6 +39,8 @@
from docutils.parsers.rst import directives, Directive
from sphinx.ext.autodoc import AutodocReporter
+import kernellog
+
__version__ = '1.0'
class KernelDocDirective(Directive):
@@ -86,7 +88,8 @@
cmd += [filename]
try:
- env.app.verbose('calling kernel-doc \'%s\'' % (" ".join(cmd)))
+ kernellog.verbose(env.app,
+ 'calling kernel-doc \'%s\'' % (" ".join(cmd)))
p = subprocess.Popen(cmd, stdout=subprocess.PIPE, stderr=subprocess.PIPE)
out, err = p.communicate()
@@ -96,7 +99,8 @@
if p.returncode != 0:
sys.stderr.write(err)
- env.app.warn('kernel-doc \'%s\' failed with return code %d' % (" ".join(cmd), p.returncode))
+ kernellog.warn(env.app,
+ 'kernel-doc \'%s\' failed with return code %d' % (" ".join(cmd), p.returncode))
return [nodes.error(None, nodes.paragraph(text = "kernel-doc missing"))]
elif env.config.kerneldoc_verbosity > 0:
sys.stderr.write(err)
@@ -128,8 +132,8 @@
return node.children
except Exception as e: # pylint: disable=W0703
- env.app.warn('kernel-doc \'%s\' processing failed with: %s' %
- (" ".join(cmd), str(e)))
+ kernellog.warn(env.app, 'kernel-doc \'%s\' processing failed with: %s' %
+ (" ".join(cmd), str(e)))
return [nodes.error(None, nodes.paragraph(text = "kernel-doc missing"))]
def setup(app):
diff --git a/doc/sphinx/kernellog.py b/doc/sphinx/kernellog.py
new file mode 100644
index 0000000..af924f5
--- /dev/null
+++ b/doc/sphinx/kernellog.py
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Sphinx has deprecated its older logging interface, but the replacement
+# only goes back to 1.6. So here's a wrapper layer to keep around for
+# as long as we support 1.4.
+#
+import sphinx
+
+if sphinx.__version__[:3] >= '1.6':
+ UseLogging = True
+ from sphinx.util import logging
+ logger = logging.getLogger('kerneldoc')
+else:
+ UseLogging = False
+
+def warn(app, message):
+ if UseLogging:
+ logger.warning(message)
+ else:
+ app.warn(message)
+
+def verbose(app, message):
+ if UseLogging:
+ logger.verbose(message)
+ else:
+ app.verbose(message)
+
+
diff --git a/doc/sphinx/kfigure.py b/doc/sphinx/kfigure.py
index b97228d..fbfe669 100644
--- a/doc/sphinx/kfigure.py
+++ b/doc/sphinx/kfigure.py
@@ -60,6 +60,8 @@
from sphinx.util.nodes import clean_astext
from six import iteritems
+import kernellog
+
PY3 = sys.version_info[0] == 3
if PY3:
@@ -171,20 +173,20 @@
This function is called once, when the builder is initiated.
"""
global dot_cmd, convert_cmd # pylint: disable=W0603
- app.verbose("kfigure: check installed tools ...")
+ kernellog.verbose(app, "kfigure: check installed tools ...")
dot_cmd = which('dot')
convert_cmd = which('convert')
if dot_cmd:
- app.verbose("use dot(1) from: " + dot_cmd)
+ kernellog.verbose(app, "use dot(1) from: " + dot_cmd)
else:
- app.warn("dot(1) not found, for better output quality install "
- "graphviz from http://www.graphviz.org")
+ kernellog.warn(app, "dot(1) not found, for better output quality install "
+ "graphviz from http://www.graphviz.org")
if convert_cmd:
- app.verbose("use convert(1) from: " + convert_cmd)
+ kernellog.verbose(app, "use convert(1) from: " + convert_cmd)
else:
- app.warn(
+ kernellog.warn(app,
"convert(1) not found, for SVG to PDF conversion install "
"ImageMagick (https://www.imagemagick.org)")
@@ -220,12 +222,13 @@
# in kernel builds, use 'make SPHINXOPTS=-v' to see verbose messages
- app.verbose('assert best format for: ' + img_node['uri'])
+ kernellog.verbose(app, 'assert best format for: ' + img_node['uri'])
if in_ext == '.dot':
if not dot_cmd:
- app.verbose("dot from graphviz not available / include DOT raw.")
+ kernellog.verbose(app,
+ "dot from graphviz not available / include DOT raw.")
img_node.replace_self(file2literal(src_fname))
elif translator.builder.format == 'latex':
@@ -252,7 +255,8 @@
if translator.builder.format == 'latex':
if convert_cmd is None:
- app.verbose("no SVG to PDF conversion available / include SVG raw.")
+ kernellog.verbose(app,
+ "no SVG to PDF conversion available / include SVG raw.")
img_node.replace_self(file2literal(src_fname))
else:
dst_fname = path.join(translator.builder.outdir, fname + '.pdf')
@@ -265,18 +269,19 @@
_name = dst_fname[len(translator.builder.outdir) + 1:]
if isNewer(dst_fname, src_fname):
- app.verbose("convert: {out}/%s already exists and is newer" % _name)
+ kernellog.verbose(app,
+ "convert: {out}/%s already exists and is newer" % _name)
else:
ok = False
mkdir(path.dirname(dst_fname))
if in_ext == '.dot':
- app.verbose('convert DOT to: {out}/' + _name)
+ kernellog.verbose(app, 'convert DOT to: {out}/' + _name)
ok = dot2format(app, src_fname, dst_fname)
elif in_ext == '.svg':
- app.verbose('convert SVG to: {out}/' + _name)
+ kernellog.verbose(app, 'convert SVG to: {out}/' + _name)
ok = svg2pdf(app, src_fname, dst_fname)
if not ok:
@@ -305,7 +310,8 @@
with open(out_fname, "w") as out:
exit_code = subprocess.call(cmd, stdout = out)
if exit_code != 0:
- app.warn("Error #%d when calling: %s" % (exit_code, " ".join(cmd)))
+ kernellog.warn(app,
+ "Error #%d when calling: %s" % (exit_code, " ".join(cmd)))
return bool(exit_code == 0)
def svg2pdf(app, svg_fname, pdf_fname):
@@ -322,7 +328,7 @@
# use stdout and stderr from parent
exit_code = subprocess.call(cmd)
if exit_code != 0:
- app.warn("Error #%d when calling: %s" % (exit_code, " ".join(cmd)))
+ kernellog.warn(app, "Error #%d when calling: %s" % (exit_code, " ".join(cmd)))
return bool(exit_code == 0)
@@ -415,15 +421,15 @@
app = self.builder.app
srclang = node.get('srclang')
- app.verbose('visit kernel-render node lang: "%s"' % (srclang))
+ kernellog.verbose(app, 'visit kernel-render node lang: "%s"' % (srclang))
tmp_ext = RENDER_MARKUP_EXT.get(srclang, None)
if tmp_ext is None:
- app.warn('kernel-render: "%s" unknown / include raw.' % (srclang))
+ kernellog.warn(app, 'kernel-render: "%s" unknown / include raw.' % (srclang))
return
if not dot_cmd and tmp_ext == '.dot':
- app.verbose("dot from graphviz not available / include raw.")
+ kernellog.verbose(app, "dot from graphviz not available / include raw.")
return
literal_block = node[0]
diff --git a/doc/uImage.FIT/kernel_fdts_compressed.its b/doc/uImage.FIT/kernel_fdts_compressed.its
new file mode 100644
index 0000000..8f81106
--- /dev/null
+++ b/doc/uImage.FIT/kernel_fdts_compressed.its
@@ -0,0 +1,73 @@
+/*
+ * U-Boot uImage source file with a kernel and multiple compressed FDT blobs.
+ * Since the FDTs are compressed, configurations must provide a compatible
+ * string to match directly.
+ */
+
+/dts-v1/;
+
+/ {
+ description = "Image with single Linux kernel and compressed FDT blobs";
+ #address-cells = <1>;
+
+ images {
+ kernel {
+ description = "Vanilla Linux kernel";
+ data = /incbin/("./vmlinux.bin.gz");
+ type = "kernel";
+ arch = "ppc";
+ os = "linux";
+ compression = "gzip";
+ load = <00000000>;
+ entry = <00000000>;
+ hash-1 {
+ algo = "crc32";
+ };
+ hash-2 {
+ algo = "sha1";
+ };
+ };
+ fdt@1 {
+ description = "Flattened Device Tree blob 1";
+ data = /incbin/("./myboard-var1.dtb");
+ type = "flat_dt";
+ arch = "ppc";
+ compression = "gzip";
+ hash-1 {
+ algo = "crc32";
+ };
+ hash-2 {
+ algo = "sha1";
+ };
+ };
+ fdt@2 {
+ description = "Flattened Device Tree blob 2";
+ data = /incbin/("./myboard-var2.dtb");
+ type = "flat_dt";
+ arch = "ppc";
+ compression = "lzma";
+ hash-1 {
+ algo = "crc32";
+ };
+ hash-2 {
+ algo = "sha1";
+ };
+ };
+ };
+
+ configurations {
+ default = "conf@1";
+ conf@1 {
+ description = "Boot Linux kernel with FDT blob 1";
+ kernel = "kernel";
+ fdt = "fdt@1";
+ compatible = "myvendor,myboard-variant1";
+ };
+ conf@2 {
+ description = "Boot Linux kernel with FDT blob 2";
+ kernel = "kernel";
+ fdt = "fdt@2";
+ compatible = "myvendor,myboard-variant2";
+ };
+ };
+};
diff --git a/doc/uImage.FIT/signature.txt b/doc/uImage.FIT/signature.txt
index bfff6fd..eee0651 100644
--- a/doc/uImage.FIT/signature.txt
+++ b/doc/uImage.FIT/signature.txt
@@ -216,7 +216,7 @@
kernel = "kernel-1";
fdt = "fdt-1";
};
- conf-1 {
+ conf-2 {
kernel = "kernel-2";
fdt = "fdt-2";
};
@@ -232,7 +232,7 @@
kernel = "kernel-1";
fdt = "fdt-1";
};
- conf-1 {
+ conf-2 {
kernel = "kernel-2";
fdt = "fdt-2";
};
@@ -335,7 +335,8 @@
WARNING: When relying on signed FIT images with required signature check
the legacy image format is default disabled by not defining
-CONFIG_IMAGE_FORMAT_LEGACY
+CONFIG_LEGACY_IMAGE_FORMAT
+
Testing
-------
@@ -349,6 +350,8 @@
$ make O=sandbox sandbox_config
$ make O=sandbox
$ O=sandbox ./test/vboot/vboot_test.sh
+
+
Simple Verified Boot Test
=========================
@@ -388,8 +391,8 @@
Test passed
-Hardware Signing with PKCS#11
------------------------------
+Hardware Signing with PKCS#11 or with HSM
+-----------------------------------------
Securely managing private signing keys can challenging, especially when the
keys are stored on the file system of a computer that is connected to the
@@ -402,14 +405,43 @@
device.
Requirements:
-Smartcard/USB token/HSM which can work with the pkcs11 engine
+Smartcard/USB token/HSM which can work with some openssl engine
openssl
+
+For pkcs11 engine usage:
libp11 (provides pkcs11 engine)
p11-kit (recommended to simplify setup)
opensc (for smartcards and smartcard like USB devices)
gnutls (recommended for key generation, p11tool)
-The following examples use the Nitrokey Pro. Instructions for other devices may vary.
+For generic HSMs respective openssl engine must be installed and locateable by
+openssl. This may require setting up LD_LIBRARY_PATH if engine is not installed
+to openssl's default search paths.
+
+PKCS11 engine support forms "key id" based on "keydir" and with
+"key-name-hint". "key-name-hint" is used as "object" name and "keydir" if
+defined is used to define (prefix for) which PKCS11 source is being used for
+lookup up for the key.
+
+PKCS11 engine key ids:
+ "pkcs11:<keydir>;object=<key-name-hint>;type=<public|private>"
+or
+ "pkcs11:object=<key-name-hint>;type=<public|private>",
+
+Generic HSM engine support forms "key id" based on "keydir" and with
+"key-name-hint". If "keydir" is specified for mkimage it is used as a prefix in
+"key id" and is appended with "key-name-hint".
+
+Generic engine key ids:
+ "<keydir><key-name-hint>"
+or
+ "<key-name-hint>"
+
+As mkimage does not at this time support prompting for passwords HSM may need
+key preloading wrapper to be used when invoking mkimage.
+
+The following examples use the Nitrokey Pro using pkcs11 engine. Instructions
+for other devices may vary.
Notes on pkcs11 engine setup:
diff --git a/doc/uImage.FIT/source_file_format.txt b/doc/uImage.FIT/source_file_format.txt
index d701b9b..f8e27ed 100644
--- a/doc/uImage.FIT/source_file_format.txt
+++ b/doc/uImage.FIT/source_file_format.txt
@@ -240,6 +240,7 @@
|- fdt = "fdt sub-node unit-name" [, "fdt overlay sub-node unit-name", ...]
|- fpga = "fpga sub-node unit-name"
|- loadables = "loadables sub-node unit-name"
+ |- compatible = "vendor,board-style device tree compatible string"
Mandatory properties:
@@ -263,6 +264,12 @@
of strings. U-Boot will load each binary at its given start-address and
may optionaly invoke additional post-processing steps on this binary based
on its component image node type.
+ - compatible : The root compatible string of the U-Boot device tree that
+ this configuration shall automatically match when CONFIG_FIT_BEST_MATCH is
+ enabled. If this property is not provided, the compatible string will be
+ extracted from the fdt blob instead. This is only possible if the fdt is
+ not compressed, so images with compressed fdts that want to use compatible
+ string matching must always provide this property.
The FDT blob is required to properly boot FDT based kernel, so the minimal
configuration for 2.6 FDT kernel is (kernel, fdt) pair.
diff --git a/doc/uefi/index.rst b/doc/uefi/index.rst
new file mode 100644
index 0000000..b790a91
--- /dev/null
+++ b/doc/uefi/index.rst
@@ -0,0 +1,11 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Unified Extensible Firmware (UEFI)
+==================================
+
+.. toctree::
+ :maxdepth: 2
+
+ uefi.rst
+ u-boot_on_efi.rst
+ iscsi.rst
diff --git a/doc/uefi/iscsi.rst b/doc/uefi/iscsi.rst
new file mode 100644
index 0000000..51d38cd
--- /dev/null
+++ b/doc/uefi/iscsi.rst
@@ -0,0 +1,184 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (c) 2018 Heinrich Schuchardt
+
+iSCSI booting with U-Boot and iPXE
+==================================
+
+Motivation
+----------
+
+U-Boot has only a reduced set of supported network protocols. The focus for
+network booting has been on UDP based protocols. A TCP stack and HTTP support
+are expected to be integrated in 2018 together with a wget command.
+
+For booting a diskless computer this leaves us with BOOTP or DHCP to get the
+address of a boot script. TFTP or NFS can be used to load the boot script, the
+operating system kernel and the initial file system (initrd).
+
+These protocols are insecure. The client cannot validate the authenticity
+of the contacted servers. And the server cannot verify the identity of the
+client.
+
+Furthermore the services providing the operating system loader or kernel are
+not the ones that the operating system typically will use. Especially in a SAN
+environment this makes updating the operating system a hassle. After installing
+a new kernel version the boot files have to be copied to the TFTP server
+directory.
+
+The HTTPS protocol provides certificate based validation of servers. Sensitive
+data like passwords can be securely transmitted.
+
+The iSCSI protocol is used for connecting storage attached networks. It
+provides mutual authentication using the CHAP protocol. It typically runs on
+a TCP transport.
+
+Thus a better solution than DHCP/TFTP/NFS boot would be to load a boot script
+via HTTPS and to download any other files needed for booting via iSCSI from the
+same target where the operating system is installed.
+
+An alternative to implementing these protocols in U-Boot is to use an existing
+software that can run on top of U-Boot. iPXE[1] is the "swiss army knife" of
+network booting. It supports both HTTPS and iSCSI. It has a scripting engine for
+fine grained control of the boot process and can provide a command shell.
+
+iPXE can be built as an EFI application (named snp.efi) which can be loaded and
+run by U-Boot.
+
+Boot sequence
+-------------
+
+U-Boot loads the EFI application iPXE snp.efi using the bootefi command. This
+application has network access via the simple network protocol offered by
+U-Boot.
+
+iPXE executes its internal script. This script may optionally chain load a
+secondary boot script via HTTPS or open a shell.
+
+For the further boot process iPXE connects to the iSCSI server. This includes
+the mutual authentication using the CHAP protocol. After the authentication iPXE
+has access to the iSCSI targets.
+
+For a selected iSCSI target iPXE sets up a handle with the block IO protocol. It
+uses the ConnectController boot service of U-Boot to request U-Boot to connect a
+file system driver. U-Boot reads from the iSCSI drive via the block IO protocol
+offered by iPXE. It creates the partition handles and installs the simple file
+protocol. Now iPXE can call the simple file protocol to load GRUB[2]. U-Boot
+uses the block IO protocol offered by iPXE to fulfill the request.
+
+Once GRUB is started it uses the same block IO protocol to load Linux. Via
+the EFI stub Linux is called as an EFI application::
+
+ +--------+ +--------+
+ | | Runs | |
+ | U-Boot |========>| iPXE |
+ | EFI | | snp.efi|
+ +--------+ | | DHCP | |
+ | |<===|********|<========| |
+ | DHCP | | | Get IP | |
+ | Server | | | Address | |
+ | |===>|********|========>| |
+ +--------+ | | Response| |
+ | | | |
+ | | | |
+ +--------+ | | HTTPS | |
+ | |<===|********|<========| |
+ | HTTPS | | | Load | |
+ | Server | | | Script | |
+ | |===>|********|========>| |
+ +--------+ | | | |
+ | | | |
+ | | | |
+ +--------+ | | iSCSI | |
+ | |<===|********|<========| |
+ | iSCSI | | | Auth | |
+ | Server |===>|********|========>| |
+ | | | | | |
+ | | | | Loads | |
+ | |<===|********|<========| | +--------+
+ | | | | GRUB | | Runs | |
+ | |===>|********|========>| |======>| GRUB |
+ | | | | | | | |
+ | | | | | | | |
+ | | | | | | Loads | |
+ | |<===|********|<========|********|<======| | +--------+
+ | | | | | | Linux | | Runs | |
+ | |===>|********|========>|********|======>| |=====>| Linux |
+ | | | | | | | | | |
+ +--------+ +--------+ +--------+ +--------+ | |
+ | |
+ | |
+ | ~ ~ ~ ~|
+
+Security
+--------
+
+The iSCSI protocol is not encrypted. The traffic could be secured using IPsec
+but neither U-Boot nor iPXE does support this. So we should at least separate
+the iSCSI traffic from all other network traffic. This can be achieved using a
+virtual local area network (VLAN).
+
+Configuration
+-------------
+
+iPXE
+~~~~
+
+For running iPXE on arm64 the bin-arm64-efi/snp.efi build target is needed::
+
+ git clone http://git.ipxe.org/ipxe.git
+ cd ipxe/src
+ make bin-arm64-efi/snp.efi -j6 EMBED=myscript.ipxe
+
+The available commands for the boot script are documented at:
+
+http://ipxe.org/cmd
+
+Credentials are managed as environment variables. These are described here:
+
+http://ipxe.org/cfg
+
+iPXE by default will put the CPU to rest when waiting for input. U-Boot does
+not wake it up due to missing interrupt support. To avoid this behavior create
+file src/config/local/nap.h:
+
+.. code-block:: c
+
+ /* nap.h */
+ #undef NAP_EFIX86
+ #undef NAP_EFIARM
+ #define NAP_NULL
+
+The supported commands in iPXE are controlled by an include, too. Putting the
+following into src/config/local/general.h is sufficient for most use cases:
+
+.. code-block:: c
+
+ /* general.h */
+ #define NSLOOKUP_CMD /* Name resolution command */
+ #define PING_CMD /* Ping command */
+ #define NTP_CMD /* NTP commands */
+ #define VLAN_CMD /* VLAN commands */
+ #define IMAGE_EFI /* EFI image support */
+ #define DOWNLOAD_PROTO_HTTPS /* Secure Hypertext Transfer Protocol */
+ #define DOWNLOAD_PROTO_FTP /* File Transfer Protocol */
+ #define DOWNLOAD_PROTO_NFS /* Network File System Protocol */
+ #define DOWNLOAD_PROTO_FILE /* Local file system access */
+
+Open-iSCSI
+~~~~~~~~~~
+
+When the root file system is on an iSCSI drive you should disable pings and set
+the replacement timer to a high value in the configuration file [3]::
+
+ node.conn[0].timeo.noop_out_interval = 0
+ node.conn[0].timeo.noop_out_timeout = 0
+ node.session.timeo.replacement_timeout = 86400
+
+Links
+-----
+
+* [1] https://ipxe.org - iPXE open source boot firmware
+* [2] https://www.gnu.org/software/grub/ -
+ GNU GRUB (Grand Unified Bootloader)
+* [3] https://github.com/open-iscsi/open-iscsi/blob/master/README -
+ Open-iSCSI README
diff --git a/doc/uefi/u-boot_on_efi.rst b/doc/uefi/u-boot_on_efi.rst
new file mode 100644
index 0000000..c9a41bc
--- /dev/null
+++ b/doc/uefi/u-boot_on_efi.rst
@@ -0,0 +1,235 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (C) 2015 Google, Inc
+
+U-Boot on EFI
+=============
+This document provides information about U-Boot running on top of EFI, either
+as an application or just as a means of getting U-Boot onto a new platform.
+
+
+Motivation
+----------
+Running U-Boot on EFI is useful in several situations:
+
+- You have EFI running on a board but U-Boot does not natively support it
+ fully yet. You can boot into U-Boot from EFI and use that until U-Boot is
+ fully ported
+
+- You need to use an EFI implementation (e.g. UEFI) because your vendor
+ requires it in order to provide support
+
+- You plan to use coreboot to boot into U-Boot but coreboot support does
+ not currently exist for your platform. In the meantime you can use U-Boot
+ on EFI and then move to U-Boot on coreboot when ready
+
+- You use EFI but want to experiment with a simpler alternative like U-Boot
+
+
+Status
+------
+Only x86 is supported at present. If you are using EFI on another architecture
+you may want to reconsider. However, much of the code is generic so could be
+ported.
+
+U-Boot supports running as an EFI application for 32-bit EFI only. This is
+not very useful since only a serial port is provided. You can look around at
+memory and type 'help' but that is about it.
+
+More usefully, U-Boot supports building itself as a payload for either 32-bit
+or 64-bit EFI. U-Boot is packaged up and loaded in its entirety by EFI. Once
+started, U-Boot changes to 32-bit mode (currently) and takes over the
+machine. You can use devices, boot a kernel, etc.
+
+
+Build Instructions
+------------------
+First choose a board that has EFI support and obtain an EFI implementation
+for that board. It will be either 32-bit or 64-bit. Alternatively, you can
+opt for using QEMU [1] and the OVMF [2], as detailed below.
+
+To build U-Boot as an EFI application (32-bit EFI required), enable CONFIG_EFI
+and CONFIG_EFI_APP. The efi-x86_app config (efi-x86_app_defconfig) is set up
+for this. Just build U-Boot as normal, e.g.::
+
+ make efi-x86_app_defconfig
+ make
+
+To build U-Boot as an EFI payload (32-bit or 64-bit EFI can be used), enable
+CONFIG_EFI, CONFIG_EFI_STUB, and select either CONFIG_EFI_STUB_32BIT or
+CONFIG_EFI_STUB_64BIT. The efi-x86_payload configs (efi-x86_payload32_defconfig
+and efi-x86_payload32_defconfig) are set up for this. Then build U-Boot as
+normal, e.g.::
+
+ make efi-x86_payload32_defconfig (or efi-x86_payload64_defconfig)
+ make
+
+You will end up with one of these files depending on what you build for:
+
+* u-boot-app.efi - U-Boot EFI application
+* u-boot-payload.efi - U-Boot EFI payload application
+
+
+Trying it out
+-------------
+QEMU is an emulator and it can emulate an x86 machine. Please make sure your
+QEMU version is 2.3.0 or above to test this. You can run the payload with
+something like this::
+
+ mkdir /tmp/efi
+ cp /path/to/u-boot*.efi /tmp/efi
+ qemu-system-x86_64 -bios bios.bin -hda fat:/tmp/efi/
+
+Add -nographic if you want to use the terminal for output. Once it starts
+type 'fs0:u-boot-payload.efi' to run the payload or 'fs0:u-boot-app.efi' to
+run the application. 'bios.bin' is the EFI 'BIOS'. Check [2] to obtain a
+prebuilt EFI BIOS for QEMU or you can build one from source as well.
+
+To try it on real hardware, put u-boot-app.efi on a suitable boot medium,
+such as a USB stick. Then you can type something like this to start it::
+
+ fs0:u-boot-payload.efi
+
+(or fs0:u-boot-app.efi for the application)
+
+This will start the payload, copy U-Boot into RAM and start U-Boot. Note
+that EFI does not support booting a 64-bit application from a 32-bit
+EFI (or vice versa). Also it will often fail to print an error message if
+you get this wrong.
+
+
+Inner workings
+--------------
+Here follow a few implementation notes for those who want to fiddle with
+this and perhaps contribute patches.
+
+The application and payload approaches sound similar but are in fact
+implemented completely differently.
+
+EFI Application
+~~~~~~~~~~~~~~~
+For the application the whole of U-Boot is built as a shared library. The
+efi_main() function is in lib/efi/efi_app.c. It sets up some basic EFI
+functions with efi_init(), sets up U-Boot global_data, allocates memory for
+U-Boot's malloc(), etc. and enters the normal init sequence (board_init_f()
+and board_init_r()).
+
+Since U-Boot limits its memory access to the allocated regions very little
+special code is needed. The CONFIG_EFI_APP option controls a few things
+that need to change so 'git grep CONFIG_EFI_APP' may be instructive.
+The CONFIG_EFI option controls more general EFI adjustments.
+
+The only available driver is the serial driver. This calls back into EFI
+'boot services' to send and receive characters. Although it is implemented
+as a serial driver the console device is not necessarilly serial. If you
+boot EFI with video output then the 'serial' device will operate on your
+target devices's display instead and the device's USB keyboard will also
+work if connected. If you have both serial and video output, then both
+consoles will be active. Even though U-Boot does the same thing normally,
+These are features of EFI, not U-Boot.
+
+Very little code is involved in implementing the EFI application feature.
+U-Boot is highly portable. Most of the difficulty is in modifying the
+Makefile settings to pass the right build flags. In particular there is very
+little x86-specific code involved - you can find most of it in
+arch/x86/cpu. Porting to ARM (which can also use EFI if you are brave
+enough) should be straightforward.
+
+Use the 'reset' command to get back to EFI.
+
+EFI Payload
+~~~~~~~~~~~
+The payload approach is a different kettle of fish. It works by building
+U-Boot exactly as normal for your target board, then adding the entire
+image (including device tree) into a small EFI stub application responsible
+for booting it. The stub application is built as a normal EFI application
+except that it has a lot of data attached to it.
+
+The stub application is implemented in lib/efi/efi_stub.c. The efi_main()
+function is called by EFI. It is responsible for copying U-Boot from its
+original location into memory, disabling EFI boot services and starting
+U-Boot. U-Boot then starts as normal, relocates, starts all drivers, etc.
+
+The stub application is architecture-dependent. At present it has some
+x86-specific code and a comment at the top of efi_stub.c describes this.
+
+While the stub application does allocate some memory from EFI this is not
+used by U-Boot (the payload). In fact when U-Boot starts it has all of the
+memory available to it and can operate as it pleases (but see the next
+section).
+
+Tables
+~~~~~~
+The payload can pass information to U-Boot in the form of EFI tables. At
+present this feature is used to pass the EFI memory map, an inordinately
+large list of memory regions. You can use the 'efi mem all' command to
+display this list. U-Boot uses the list to work out where to relocate
+itself.
+
+Although U-Boot can use any memory it likes, EFI marks some memory as used
+by 'run-time services', code that hangs around while U-Boot is running and
+is even present when Linux is running. This is common on x86 and provides
+a way for Linux to call back into the firmware to control things like CPU
+fan speed. U-Boot uses only 'conventional' memory, in EFI terminology. It
+will relocate itself to the top of the largest block of memory it can find
+below 4GB.
+
+Interrupts
+~~~~~~~~~~
+U-Boot drivers typically don't use interrupts. Since EFI enables interrupts
+it is possible that an interrupt will fire that U-Boot cannot handle. This
+seems to cause problems. For this reason the U-Boot payload runs with
+interrupts disabled at present.
+
+32/64-bit
+~~~~~~~~~
+While the EFI application can in principle be built as either 32- or 64-bit,
+only 32-bit is currently supported. This means that the application can only
+be used with 32-bit EFI.
+
+The payload stub can be build as either 32- or 64-bits. Only a small amount
+of code is built this way (see the extra- line in lib/efi/Makefile).
+Everything else is built as a normal U-Boot, so is always 32-bit on x86 at
+present.
+
+Future work
+-----------
+This work could be extended in a number of ways:
+
+- Add ARM support
+
+- Add 64-bit application support
+
+- Figure out how to solve the interrupt problem
+
+- Add more drivers to the application side (e.g. video, block devices, USB,
+ environment access). This would mostly be an academic exercise as a strong
+ use case is not readily apparent, but it might be fun.
+
+- Avoid turning off boot services in the stub. Instead allow U-Boot to make
+ use of boot services in case it wants to. It is unclear what it might want
+ though.
+
+Where is the code?
+------------------
+lib/efi
+ payload stub, application, support code. Mostly arch-neutral
+
+arch/x86/cpu/efi
+ x86 support code for running as an EFI application and payload
+
+board/efi/efi-x86_app/efi.c
+ x86 board code for running as an EFI application
+
+board/efi/efi-x86_payload
+ generic x86 EFI payload board support code
+
+common/cmd_efi.c
+ the 'efi' command
+
+--
+Ben Stoltz, Simon Glass
+Google, Inc
+July 2015
+
+* [1] http://www.qemu.org
+* [2] http://www.tianocore.org/ovmf/
diff --git a/doc/uefi/uefi.rst b/doc/uefi/uefi.rst
new file mode 100644
index 0000000..db942df
--- /dev/null
+++ b/doc/uefi/uefi.rst
@@ -0,0 +1,334 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (c) 2018 Heinrich Schuchardt
+
+UEFI on U-Boot
+==============
+
+The Unified Extensible Firmware Interface Specification (UEFI) [1] has become
+the default for booting on AArch64 and x86 systems. It provides a stable API for
+the interaction of drivers and applications with the firmware. The API comprises
+access to block storage, network, and console to name a few. The Linux kernel
+and boot loaders like GRUB or the FreeBSD loader can be executed.
+
+Development target
+------------------
+
+The implementation of UEFI in U-Boot strives to reach the requirements described
+in the "Embedded Base Boot Requirements (EBBR) Specification - Release v1.0"
+[2]. The "Server Base Boot Requirements System Software on ARM Platforms" [3]
+describes a superset of the EBBR specification and may be used as further
+reference.
+
+A full blown UEFI implementation would contradict the U-Boot design principle
+"keep it small".
+
+Building U-Boot for UEFI
+------------------------
+
+The UEFI standard supports only little-endian systems. The UEFI support can be
+activated for ARM and x86 by specifying::
+
+ CONFIG_CMD_BOOTEFI=y
+ CONFIG_EFI_LOADER=y
+
+in the .config file.
+
+Support for attaching virtual block devices, e.g. iSCSI drives connected by the
+loaded UEFI application [4], requires::
+
+ CONFIG_BLK=y
+ CONFIG_PARTITIONS=y
+
+Executing a UEFI binary
+~~~~~~~~~~~~~~~~~~~~~~~
+
+The bootefi command is used to start UEFI applications or to install UEFI
+drivers. It takes two parameters::
+
+ bootefi <image address> [fdt address]
+
+* image address - the memory address of the UEFI binary
+* fdt address - the memory address of the flattened device tree
+
+Below you find the output of an example session starting GRUB::
+
+ => load mmc 0:2 ${fdt_addr_r} boot/dtb
+ 29830 bytes read in 14 ms (2 MiB/s)
+ => load mmc 0:1 ${kernel_addr_r} efi/debian/grubaa64.efi
+ reading efi/debian/grubaa64.efi
+ 120832 bytes read in 7 ms (16.5 MiB/s)
+ => bootefi ${kernel_addr_r} ${fdt_addr_r}
+
+The environment variable 'bootargs' is passed as load options in the UEFI system
+table. The Linux kernel EFI stub uses the load options as command line
+arguments.
+
+Executing the boot manager
+~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The UEFI specification foresees to define boot entries and boot sequence via UEFI
+variables. Booting according to these variables is possible via::
+
+ bootefi bootmgr [fdt address]
+
+As of U-Boot v2018.03 UEFI variables are not persisted and cannot be set at
+runtime.
+
+Executing the built in hello world application
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+A hello world UEFI application can be built with::
+
+ CONFIG_CMD_BOOTEFI_HELLO_COMPILE=y
+
+It can be embedded into the U-Boot binary with::
+
+ CONFIG_CMD_BOOTEFI_HELLO=y
+
+The bootefi command is used to start the embedded hello world application::
+
+ bootefi hello [fdt address]
+
+Below you find the output of an example session::
+
+ => bootefi hello ${fdtcontroladdr}
+ ## Starting EFI application at 01000000 ...
+ WARNING: using memory device/image path, this may confuse some payloads!
+ Hello, world!
+ Running on UEFI 2.7
+ Have SMBIOS table
+ Have device tree
+ Load options: root=/dev/sdb3 init=/sbin/init rootwait ro
+ ## Application terminated, r = 0
+
+The environment variable fdtcontroladdr points to U-Boot's internal device tree
+(if available).
+
+Executing the built-in self-test
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+An UEFI self-test suite can be embedded in U-Boot by building with::
+
+ CONFIG_CMD_BOOTEFI_SELFTEST=y
+
+For testing the UEFI implementation the bootefi command can be used to start the
+self-test::
+
+ bootefi selftest [fdt address]
+
+The environment variable 'efi_selftest' can be used to select a single test. If
+it is not provided all tests are executed except those marked as 'on request'.
+If the environment variable is set to 'list' a list of all tests is shown.
+
+Below you can find the output of an example session::
+
+ => setenv efi_selftest simple network protocol
+ => bootefi selftest
+ Testing EFI API implementation
+ Selected test: 'simple network protocol'
+ Setting up 'simple network protocol'
+ Setting up 'simple network protocol' succeeded
+ Executing 'simple network protocol'
+ DHCP Discover
+ DHCP reply received from 192.168.76.2 (52:55:c0:a8:4c:02)
+ as broadcast message.
+ Executing 'simple network protocol' succeeded
+ Tearing down 'simple network protocol'
+ Tearing down 'simple network protocol' succeeded
+ Boot services terminated
+ Summary: 0 failures
+ Preparing for reset. Press any key.
+
+The UEFI life cycle
+-------------------
+
+After the U-Boot platform has been initialized the UEFI API provides two kinds
+of services:
+
+* boot services
+* runtime services
+
+The API can be extended by loading UEFI drivers which come in two variants:
+
+* boot drivers
+* runtime drivers
+
+UEFI drivers are installed with U-Boot's bootefi command. With the same command
+UEFI applications can be executed.
+
+Loaded images of UEFI drivers stay in memory after returning to U-Boot while
+loaded images of applications are removed from memory.
+
+An UEFI application (e.g. an operating system) that wants to take full control
+of the system calls ExitBootServices. After a UEFI application calls
+ExitBootServices
+
+* boot services are not available anymore
+* timer events are stopped
+* the memory used by U-Boot except for runtime services is released
+* the memory used by boot time drivers is released
+
+So this is a point of no return. Afterwards the UEFI application can only return
+to U-Boot by rebooting.
+
+The UEFI object model
+---------------------
+
+UEFI offers a flexible and expandable object model. The objects in the UEFI API
+are devices, drivers, and loaded images. These objects are referenced by
+handles.
+
+The interfaces implemented by the objects are referred to as protocols. These
+are identified by GUIDs. They can be installed and uninstalled by calling the
+appropriate boot services.
+
+Handles are created by the InstallProtocolInterface or the
+InstallMultipleProtocolinterfaces service if NULL is passed as handle.
+
+Handles are deleted when the last protocol has been removed with the
+UninstallProtocolInterface or the UninstallMultipleProtocolInterfaces service.
+
+Devices offer the EFI_DEVICE_PATH_PROTOCOL. A device path is the concatenation
+of device nodes. By their device paths all devices of a system are arranged in a
+tree.
+
+Drivers offer the EFI_DRIVER_BINDING_PROTOCOL. This protocol is used to connect
+a driver to devices (which are referenced as controllers in this context).
+
+Loaded images offer the EFI_LOADED_IMAGE_PROTOCOL. This protocol provides meta
+information about the image and a pointer to the unload callback function.
+
+The UEFI events
+---------------
+
+In the UEFI terminology an event is a data object referencing a notification
+function which is queued for calling when the event is signaled. The following
+types of events exist:
+
+* periodic and single shot timer events
+* exit boot services events, triggered by calling the ExitBootServices() service
+* virtual address change events
+* memory map change events
+* read to boot events
+* reset system events
+* system table events
+* events that are only triggered programmatically
+
+Events can be created with the CreateEvent service and deleted with CloseEvent
+service.
+
+Events can be assigned to an event group. If any of the events in a group is
+signaled, all other events in the group are also set to the signaled state.
+
+The UEFI driver model
+---------------------
+
+A driver is specific for a single protocol installed on a device. To install a
+driver on a device the ConnectController service is called. In this context
+controller refers to the device for which the driver is installed.
+
+The relevant drivers are identified using the EFI_DRIVER_BINDING_PROTOCOL. This
+protocol has has three functions:
+
+* supported - determines if the driver is compatible with the device
+* start - installs the driver by opening the relevant protocol with
+ attribute EFI_OPEN_PROTOCOL_BY_DRIVER
+* stop - uninstalls the driver
+
+The driver may create child controllers (child devices). E.g. a driver for block
+IO devices will create the device handles for the partitions. The child
+controllers will open the supported protocol with the attribute
+EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER.
+
+A driver can be detached from a device using the DisconnectController service.
+
+U-Boot devices mapped as UEFI devices
+-------------------------------------
+
+Some of the U-Boot devices are mapped as UEFI devices
+
+* block IO devices
+* console
+* graphical output
+* network adapter
+
+As of U-Boot 2018.03 the logic for doing this is hard coded.
+
+The development target is to integrate the setup of these UEFI devices with the
+U-Boot driver model [5]. So when a U-Boot device is discovered a handle should
+be created and the device path protocol and the relevant IO protocol should be
+installed. The UEFI driver then would be attached by calling ConnectController.
+When a U-Boot device is removed DisconnectController should be called.
+
+UEFI devices mapped as U-Boot devices
+-------------------------------------
+
+UEFI drivers binaries and applications may create new (virtual) devices, install
+a protocol and call the ConnectController service. Now the matching UEFI driver
+is determined by iterating over the implementations of the
+EFI_DRIVER_BINDING_PROTOCOL.
+
+It is the task of the UEFI driver to create a corresponding U-Boot device and to
+proxy calls for this U-Boot device to the controller.
+
+In U-Boot 2018.03 this has only been implemented for block IO devices.
+
+UEFI uclass
+~~~~~~~~~~~
+
+An UEFI uclass driver (lib/efi_driver/efi_uclass.c) has been created that
+takes care of initializing the UEFI drivers and providing the
+EFI_DRIVER_BINDING_PROTOCOL implementation for the UEFI drivers.
+
+A linker created list is used to keep track of the UEFI drivers. To create an
+entry in the list the UEFI driver uses the U_BOOT_DRIVER macro specifying
+UCLASS_EFI as the ID of its uclass, e.g::
+
+ /* Identify as UEFI driver */
+ U_BOOT_DRIVER(efi_block) = {
+ .name = "EFI block driver",
+ .id = UCLASS_EFI,
+ .ops = &driver_ops,
+ };
+
+The available operations are defined via the structure struct efi_driver_ops::
+
+ struct efi_driver_ops {
+ const efi_guid_t *protocol;
+ const efi_guid_t *child_protocol;
+ int (*bind)(efi_handle_t handle, void *interface);
+ };
+
+When the supported() function of the EFI_DRIVER_BINDING_PROTOCOL is called the
+uclass checks if the protocol GUID matches the protocol GUID of the UEFI driver.
+In the start() function the bind() function of the UEFI driver is called after
+checking the GUID.
+The stop() function of the EFI_DRIVER_BINDING_PROTOCOL disconnects the child
+controllers created by the UEFI driver and the UEFI driver. (In U-Boot v2013.03
+this is not yet completely implemented.)
+
+UEFI block IO driver
+~~~~~~~~~~~~~~~~~~~~
+
+The UEFI block IO driver supports devices exposing the EFI_BLOCK_IO_PROTOCOL.
+
+When connected it creates a new U-Boot block IO device with interface type
+IF_TYPE_EFI, adds child controllers mapping the partitions, and installs the
+EFI_SIMPLE_FILE_SYSTEM_PROTOCOL on these. This can be used together with the
+software iPXE to boot from iSCSI network drives [4].
+
+This driver is only available if U-Boot is configured with::
+
+ CONFIG_BLK=y
+ CONFIG_PARTITIONS=y
+
+Links
+-----
+
+* [1] http://uefi.org/specifications - UEFI specifications
+* [2] https://github.com/ARM-software/ebbr/releases/download/v1.0/ebbr-v1.0.pdf -
+ Embedded Base Boot Requirements (EBBR) Specification - Release v1.0
+* [3] https://developer.arm.com/docs/den0044/latest/server-base-boot-requirements-system-software-on-arm-platforms-version-11 -
+ Server Base Boot Requirements System Software on ARM Platforms - Version 1.1
+* [4] :doc:`iscsi`
+* [5] :doc:`../driver-model/index`
diff --git a/drivers/Kconfig b/drivers/Kconfig
index 96ff4f5..350acf8 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -66,9 +66,9 @@
source "drivers/pci/Kconfig"
-source "drivers/pch/Kconfig"
+source "drivers/pci_endpoint/Kconfig"
-source "drivers/pcmcia/Kconfig"
+source "drivers/pch/Kconfig"
source "drivers/phy/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 6635dab..a4bb5e4 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -4,7 +4,9 @@
obj-$(CONFIG_$(SPL_TPL_)DM) += core/
obj-$(CONFIG_$(SPL_TPL_)DFU) += dfu/
obj-$(CONFIG_$(SPL_TPL_)GPIO_SUPPORT) += gpio/
-obj-$(CONFIG_$(SPL_TPL_)DRIVERS_MISC_SUPPORT) += misc/ sysreset/ firmware/
+obj-$(CONFIG_$(SPL_TPL_)DRIVERS_MISC_SUPPORT) += misc/
+obj-$(CONFIG_$(SPL_TPL_)SYSRESET) += sysreset/
+obj-$(CONFIG_$(SPL_TPL_)FIRMWARE) +=firmware/
obj-$(CONFIG_$(SPL_TPL_)I2C_SUPPORT) += i2c/
obj-$(CONFIG_$(SPL_TPL_)INPUT) += input/
obj-$(CONFIG_$(SPL_TPL_)LED) += led/
@@ -81,12 +83,11 @@
obj-$(CONFIG_CPU) += cpu/
obj-y += crypto/
obj-$(CONFIG_FASTBOOT) += fastboot/
-obj-y += firmware/
obj-$(CONFIG_FPGA) += fpga/
obj-y += misc/
obj-$(CONFIG_MMC) += mmc/
obj-$(CONFIG_NVME) += nvme/
-obj-y += pcmcia/
+obj-$(CONFIG_PCI_ENDPOINT) += pci_endpoint/
obj-y += dfu/
obj-$(CONFIG_PCH) += pch/
obj-y += phy/allwinner/
@@ -95,7 +96,6 @@
obj-y += scsi/
obj-y += sound/
obj-y += spmi/
-obj-y += sysreset/
obj-y += video/
obj-y += watchdog/
obj-$(CONFIG_QE) += qe/
diff --git a/drivers/adc/stm32-adc-core.c b/drivers/adc/stm32-adc-core.c
index a9aa143..04b6a8a 100644
--- a/drivers/adc/stm32-adc-core.c
+++ b/drivers/adc/stm32-adc-core.c
@@ -60,7 +60,8 @@
{
u32 ckmode, presc;
unsigned long rate;
- int i, div;
+ unsigned int i;
+ int div;
/* stm32h7 bus clock is common for all ADC instances (mandatory) */
if (!clk_valid(&common->bclk)) {
diff --git a/drivers/adc/stm32-adc.c b/drivers/adc/stm32-adc.c
index e108062..029338e 100644
--- a/drivers/adc/stm32-adc.c
+++ b/drivers/adc/stm32-adc.c
@@ -163,15 +163,16 @@
struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
struct stm32_adc *adc = dev_get_priv(dev);
u32 chans[STM32_ADC_CH_MAX];
- int i, num_channels, ret;
+ unsigned int i, num_channels;
+ int ret;
/* Retrieve single ended channels listed in device tree */
- num_channels = dev_read_size(dev, "st,adc-channels");
- if (num_channels < 0) {
- dev_err(dev, "can't get st,adc-channels: %d\n", num_channels);
- return num_channels;
+ ret = dev_read_size(dev, "st,adc-channels");
+ if (ret < 0) {
+ dev_err(dev, "can't get st,adc-channels: %d\n", ret);
+ return ret;
}
- num_channels /= sizeof(u32);
+ num_channels = ret / sizeof(u32);
if (num_channels > adc->cfg->max_channels) {
dev_err(dev, "too many st,adc-channels: %d\n", num_channels);
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index e3135bb..9a08575 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -1167,6 +1167,14 @@
if (ret)
return ret;
+ /*
+ * scsi_scan_dev() scans devices up-to the number of max_id.
+ * Update max_id if the number of detected ports exceeds max_id.
+ * This allows SCSI to scan all detected ports.
+ */
+ uc_plat->max_id = max_t(unsigned long, uc_priv->n_ports,
+ uc_plat->max_id);
+
return 0;
}
diff --git a/drivers/bios_emulator/atibios.c b/drivers/bios_emulator/atibios.c
index 4f362d1..fb806b5 100644
--- a/drivers/bios_emulator/atibios.c
+++ b/drivers/bios_emulator/atibios.c
@@ -136,7 +136,6 @@
bool linear_ok;
int attr;
- break;
debug("Mode %x: ", mode);
memset(buffer, '\0', sizeof(struct vbe_mode_info));
regs->e.eax = VESA_GET_MODE_INFO;
diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig
index 33f4aa2..1e6dad8 100644
--- a/drivers/block/Kconfig
+++ b/drivers/block/Kconfig
@@ -56,6 +56,13 @@
help
This option enables the disk-block cache in SPL
+config TPL_BLOCK_CACHE
+ bool "Use block device cache in TPL"
+ depends on TPL_BLK
+ default n
+ help
+ This option enables the disk-block cache in TPL
+
config IDE
bool "Support IDE controllers"
select HAVE_BLOCK_DEVICE
diff --git a/drivers/bootcount/bootcount_env.c b/drivers/bootcount/bootcount_env.c
index 9084ca8..b75c900 100644
--- a/drivers/bootcount/bootcount_env.c
+++ b/drivers/bootcount/bootcount_env.c
@@ -5,7 +5,7 @@
*/
#include <common.h>
-#include <environment.h>
+#include <env.h>
void bootcount_store(ulong a)
{
diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index 24def7a..629039e 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -22,4 +22,13 @@
ARMv7(32-bit) devices. The driver configures the cache settings
found in the device tree.
+config V5L2_CACHE
+ bool "Andes V5L2 cache driver"
+ select CACHE
+ depends on RISCV_NDS_CACHE
+ help
+ Support Andes V5L2 cache controller in AE350 platform.
+ It will configure tag and data ram timing control from the
+ device tree and enable L2 cache.
+
endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
index 9deb961..4a6458c 100644
--- a/drivers/cache/Makefile
+++ b/drivers/cache/Makefile
@@ -2,3 +2,4 @@
obj-$(CONFIG_CACHE) += cache-uclass.o
obj-$(CONFIG_SANDBOX) += sandbox_cache.o
obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
+obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o
diff --git a/drivers/cache/cache-uclass.c b/drivers/cache/cache-uclass.c
index 97ce024..3b20a10 100644
--- a/drivers/cache/cache-uclass.c
+++ b/drivers/cache/cache-uclass.c
@@ -17,6 +17,26 @@
return ops->get_info(dev, info);
}
+int cache_enable(struct udevice *dev)
+{
+ struct cache_ops *ops = cache_get_ops(dev);
+
+ if (!ops->enable)
+ return -ENOSYS;
+
+ return ops->enable(dev);
+}
+
+int cache_disable(struct udevice *dev)
+{
+ struct cache_ops *ops = cache_get_ops(dev);
+
+ if (!ops->disable)
+ return -ENOSYS;
+
+ return ops->disable(dev);
+}
+
UCLASS_DRIVER(cache) = {
.id = UCLASS_CACHE,
.name = "cache",
diff --git a/drivers/cache/cache-v5l2.c b/drivers/cache/cache-v5l2.c
new file mode 100644
index 0000000..d367171
--- /dev/null
+++ b/drivers/cache/cache-v5l2.c
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <cache.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <dm/ofnode.h>
+
+struct l2cache {
+ volatile u64 configure;
+ volatile u64 control;
+ volatile u64 hpm0;
+ volatile u64 hpm1;
+ volatile u64 hpm2;
+ volatile u64 hpm3;
+ volatile u64 error_status;
+ volatile u64 ecc_error;
+ volatile u64 cctl_command0;
+ volatile u64 cctl_access_line0;
+ volatile u64 cctl_command1;
+ volatile u64 cctl_access_line1;
+ volatile u64 cctl_command2;
+ volatile u64 cctl_access_line2;
+ volatile u64 cctl_command3;
+ volatile u64 cctl_access_line4;
+ volatile u64 cctl_status;
+};
+
+/* Control Register */
+#define L2_ENABLE 0x1
+/* prefetch */
+#define IPREPETCH_OFF 3
+#define DPREPETCH_OFF 5
+#define IPREPETCH_MSK (3 << IPREPETCH_OFF)
+#define DPREPETCH_MSK (3 << DPREPETCH_OFF)
+/* tag ram */
+#define TRAMOCTL_OFF 8
+#define TRAMICTL_OFF 10
+#define TRAMOCTL_MSK (3 << TRAMOCTL_OFF)
+#define TRAMICTL_MSK BIT(TRAMICTL_OFF)
+/* data ram */
+#define DRAMOCTL_OFF 11
+#define DRAMICTL_OFF 13
+#define DRAMOCTL_MSK (3 << DRAMOCTL_OFF)
+#define DRAMICTL_MSK BIT(DRAMICTL_OFF)
+
+/* CCTL Command Register */
+#define CCTL_CMD_REG(base, hart) ((ulong)(base) + 0x40 + (hart) * 0x10)
+#define L2_WBINVAL_ALL 0x12
+
+/* CCTL Status Register */
+#define CCTL_STATUS_MSK(hart) (0xf << ((hart) * 4))
+#define CCTL_STATUS_IDLE(hart) (0 << ((hart) * 4))
+#define CCTL_STATUS_PROCESS(hart) (1 << ((hart) * 4))
+#define CCTL_STATUS_ILLEGAL(hart) (2 << ((hart) * 4))
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct v5l2_plat {
+ struct l2cache *regs;
+ u32 iprefetch;
+ u32 dprefetch;
+ u32 tram_ctl[2];
+ u32 dram_ctl[2];
+};
+
+static int v5l2_enable(struct udevice *dev)
+{
+ struct v5l2_plat *plat = dev_get_platdata(dev);
+ volatile struct l2cache *regs = plat->regs;
+
+ if (regs)
+ setbits_le32(®s->control, L2_ENABLE);
+
+ return 0;
+}
+
+static int v5l2_disable(struct udevice *dev)
+{
+ struct v5l2_plat *plat = dev_get_platdata(dev);
+ volatile struct l2cache *regs = plat->regs;
+ u8 hart = gd->arch.boot_hart;
+ void __iomem *cctlcmd = (void __iomem *)CCTL_CMD_REG(regs, hart);
+
+ if ((regs) && (readl(®s->control) & L2_ENABLE)) {
+ writel(L2_WBINVAL_ALL, cctlcmd);
+
+ while ((readl(®s->cctl_status) & CCTL_STATUS_MSK(hart))) {
+ if ((readl(®s->cctl_status) & CCTL_STATUS_ILLEGAL(hart))) {
+ printf("L2 flush illegal! hanging...");
+ hang();
+ }
+ }
+ clrbits_le32(®s->control, L2_ENABLE);
+ }
+
+ return 0;
+}
+
+static int v5l2_ofdata_to_platdata(struct udevice *dev)
+{
+ struct v5l2_plat *plat = dev_get_platdata(dev);
+ struct l2cache *regs;
+
+ regs = (struct l2cache *)dev_read_addr(dev);
+ plat->regs = regs;
+
+ plat->iprefetch = -EINVAL;
+ plat->dprefetch = -EINVAL;
+ plat->tram_ctl[0] = -EINVAL;
+ plat->dram_ctl[0] = -EINVAL;
+
+ /* Instruction and data fetch prefetch depth */
+ dev_read_u32(dev, "andes,inst-prefetch", &plat->iprefetch);
+ dev_read_u32(dev, "andes,data-prefetch", &plat->dprefetch);
+
+ /* Set tag RAM and data RAM setup and output cycle */
+ dev_read_u32_array(dev, "andes,tag-ram-ctl", plat->tram_ctl, 2);
+ dev_read_u32_array(dev, "andes,data-ram-ctl", plat->dram_ctl, 2);
+
+ return 0;
+}
+
+static int v5l2_probe(struct udevice *dev)
+{
+ struct v5l2_plat *plat = dev_get_platdata(dev);
+ struct l2cache *regs = plat->regs;
+ u32 ctl_val;
+
+ ctl_val = readl(®s->control);
+
+ if (!(ctl_val & L2_ENABLE))
+ ctl_val |= L2_ENABLE;
+
+ if (plat->iprefetch != -EINVAL) {
+ ctl_val &= ~(IPREPETCH_MSK);
+ ctl_val |= (plat->iprefetch << IPREPETCH_OFF);
+ }
+
+ if (plat->dprefetch != -EINVAL) {
+ ctl_val &= ~(DPREPETCH_MSK);
+ ctl_val |= (plat->dprefetch << DPREPETCH_OFF);
+ }
+
+ if (plat->tram_ctl[0] != -EINVAL) {
+ ctl_val &= ~(TRAMOCTL_MSK | TRAMICTL_MSK);
+ ctl_val |= plat->tram_ctl[0] << TRAMOCTL_OFF;
+ ctl_val |= plat->tram_ctl[1] << TRAMICTL_OFF;
+ }
+
+ if (plat->dram_ctl[0] != -EINVAL) {
+ ctl_val &= ~(DRAMOCTL_MSK | DRAMICTL_MSK);
+ ctl_val |= plat->dram_ctl[0] << DRAMOCTL_OFF;
+ ctl_val |= plat->dram_ctl[1] << DRAMICTL_OFF;
+ }
+
+ writel(ctl_val, ®s->control);
+
+ return 0;
+}
+
+static const struct udevice_id v5l2_cache_ids[] = {
+ { .compatible = "v5l2cache" },
+ {}
+};
+
+static const struct cache_ops v5l2_cache_ops = {
+ .enable = v5l2_enable,
+ .disable = v5l2_disable,
+};
+
+U_BOOT_DRIVER(v5l2_cache) = {
+ .name = "v5l2_cache",
+ .id = UCLASS_CACHE,
+ .of_match = v5l2_cache_ids,
+ .ofdata_to_platdata = v5l2_ofdata_to_platdata,
+ .probe = v5l2_probe,
+ .platdata_auto_alloc_size = sizeof(struct v5l2_plat),
+ .ops = &v5l2_cache_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/cache/sandbox_cache.c b/drivers/cache/sandbox_cache.c
index 14cc6b0..9050c4c 100644
--- a/drivers/cache/sandbox_cache.c
+++ b/drivers/cache/sandbox_cache.c
@@ -17,8 +17,21 @@
return 0;
}
+static int sandbox_enable(struct udevice *dev)
+{
+ return 0;
+}
+
+static int snadbox_disable(struct udevice *dev)
+{
+ return 0;
+}
+
+
static const struct cache_ops sandbox_cache_ops = {
.get_info = sandbox_get_info,
+ .enable = sandbox_enable,
+ .disable = snadbox_disable,
};
static const struct udevice_id sandbox_cache_ids[] = {
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 96969b9..95fe0ae 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -46,6 +46,33 @@
help
Enable this to support the clocks
+config SPL_CLK_CCF
+ bool "SPL Common Clock Framework [CCF] support "
+ depends on SPL
+ help
+ Enable this option if you want to (re-)use the Linux kernel's Common
+ Clock Framework [CCF] code in U-Boot's SPL.
+
+config SPL_CLK_COMPOSITE_CCF
+ bool "SPL Common Clock Framework [CCF] composite clk support "
+ depends on SPL_CLK_CCF
+ help
+ Enable this option if you want to (re-)use the Linux kernel's Common
+ Clock Framework [CCF] composite code in U-Boot's SPL.
+
+config CLK_CCF
+ bool "Common Clock Framework [CCF] support "
+ help
+ Enable this option if you want to (re-)use the Linux kernel's Common
+ Clock Framework [CCF] code in U-Boot's clock driver.
+
+config CLK_COMPOSITE_CCF
+ bool "Common Clock Framework [CCF] composite clk support "
+ depends on CLK_CCF
+ help
+ Enable this option if you want to (re-)use the Linux kernel's Common
+ Clock Framework [CCF] composite code in U-Boot's clock driver.
+
config CLK_STM32F
bool "Enable clock driver support for STM32F family"
depends on CLK && (STM32F7 || STM32F4)
@@ -98,6 +125,7 @@
Enable the STM32 clock (RCC) driver. Enable support for
manipulating STM32MP1's on-SoC clocks.
+source "drivers/clk/analogbits/Kconfig"
source "drivers/clk/at91/Kconfig"
source "drivers/clk/exynos/Kconfig"
source "drivers/clk/imx/Kconfig"
@@ -124,4 +152,12 @@
help
Support for the clock driver of the MPC83xx series of SoCs.
+config SANDBOX_CLK_CCF
+ bool "Sandbox Common Clock Framework [CCF] support "
+ depends on SANDBOX
+ select CLK_CCF
+ help
+ Enable this option if you want to test the Linux kernel's Common
+ Clock Framework [CCF] code in U-Boot's Sandbox clock driver.
+
endmenu
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 719b9b8..68aabe1 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -7,7 +7,11 @@
obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o
obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_rate.o
obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_factor.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk.o clk-divider.o clk-mux.o clk-gate.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk-fixed-factor.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_COMPOSITE_CCF) += clk-composite.o
+obj-y += analogbits/
obj-y += imx/
obj-y += tegra/
obj-$(CONFIG_ARCH_ASPEED) += aspeed/
@@ -36,5 +40,6 @@
obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
obj-$(CONFIG_SANDBOX) += clk_sandbox.o
obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
+obj-$(CONFIG_SANDBOX_CLK_CCF) += clk_sandbox_ccf.o
obj-$(CONFIG_STM32H7) += clk_stm32h7.o
obj-$(CONFIG_CLK_TI_SCI) += clk-ti-sci.o
diff --git a/drivers/clk/analogbits/Kconfig b/drivers/clk/analogbits/Kconfig
new file mode 100644
index 0000000..1d25e6f
--- /dev/null
+++ b/drivers/clk/analogbits/Kconfig
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+
+config CLK_ANALOGBITS_WRPLL_CLN28HPC
+ bool
diff --git a/drivers/clk/analogbits/Makefile b/drivers/clk/analogbits/Makefile
new file mode 100644
index 0000000..ec1bb40
--- /dev/null
+++ b/drivers/clk/analogbits/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-$(CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC) += wrpll-cln28hpc.o
diff --git a/drivers/clk/analogbits/wrpll-cln28hpc.c b/drivers/clk/analogbits/wrpll-cln28hpc.c
new file mode 100644
index 0000000..776ead3
--- /dev/null
+++ b/drivers/clk/analogbits/wrpll-cln28hpc.c
@@ -0,0 +1,364 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018-2019 SiFive, Inc.
+ * Wesley Terpstra
+ * Paul Walmsley
+ *
+ * This library supports configuration parsing and reprogramming of
+ * the CLN28HPC variant of the Analog Bits Wide Range PLL. The
+ * intention is for this library to be reusable for any device that
+ * integrates this PLL; thus the register structure and programming
+ * details are expected to be provided by a separate IP block driver.
+ *
+ * The bulk of this code is primarily useful for clock configurations
+ * that must operate at arbitrary rates, as opposed to clock configurations
+ * that are restricted by software or manufacturer guidance to a small,
+ * pre-determined set of performance points.
+ *
+ * References:
+ * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
+ * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
+ * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
+ */
+
+#include <linux/bug.h>
+#include <linux/err.h>
+#include <linux/log2.h>
+#include <linux/math64.h>
+#include <linux/clk/analogbits-wrpll-cln28hpc.h>
+
+/* MIN_INPUT_FREQ: minimum input clock frequency, in Hz (Fref_min) */
+#define MIN_INPUT_FREQ 7000000
+
+/* MAX_INPUT_FREQ: maximum input clock frequency, in Hz (Fref_max) */
+#define MAX_INPUT_FREQ 600000000
+
+/* MIN_POST_DIVIDE_REF_FREQ: minimum post-divider reference frequency, in Hz */
+#define MIN_POST_DIVR_FREQ 7000000
+
+/* MAX_POST_DIVIDE_REF_FREQ: maximum post-divider reference frequency, in Hz */
+#define MAX_POST_DIVR_FREQ 200000000
+
+/* MIN_VCO_FREQ: minimum VCO frequency, in Hz (Fvco_min) */
+#define MIN_VCO_FREQ 2400000000UL
+
+/* MAX_VCO_FREQ: maximum VCO frequency, in Hz (Fvco_max) */
+#define MAX_VCO_FREQ 4800000000ULL
+
+/* MAX_DIVQ_DIVISOR: maximum output divisor. Selected by DIVQ = 6 */
+#define MAX_DIVQ_DIVISOR 64
+
+/* MAX_DIVR_DIVISOR: maximum reference divisor. Selected by DIVR = 63 */
+#define MAX_DIVR_DIVISOR 64
+
+/* MAX_LOCK_US: maximum PLL lock time, in microseconds (tLOCK_max) */
+#define MAX_LOCK_US 70
+
+/*
+ * ROUND_SHIFT: number of bits to shift to avoid precision loss in the rounding
+ * algorithm
+ */
+#define ROUND_SHIFT 20
+
+/*
+ * Private functions
+ */
+
+/**
+ * __wrpll_calc_filter_range() - determine PLL loop filter bandwidth
+ * @post_divr_freq: input clock rate after the R divider
+ *
+ * Select the value to be presented to the PLL RANGE input signals, based
+ * on the input clock frequency after the post-R-divider @post_divr_freq.
+ * This code follows the recommendations in the PLL datasheet for filter
+ * range selection.
+ *
+ * Return: The RANGE value to be presented to the PLL configuration inputs,
+ * or a negative return code upon error.
+ */
+static int __wrpll_calc_filter_range(unsigned long post_divr_freq)
+{
+ if (post_divr_freq < MIN_POST_DIVR_FREQ ||
+ post_divr_freq > MAX_POST_DIVR_FREQ) {
+ WARN(1, "%s: post-divider reference freq out of range: %lu",
+ __func__, post_divr_freq);
+ return -ERANGE;
+ }
+
+ switch (post_divr_freq) {
+ case 0 ... 10999999:
+ return 1;
+ case 11000000 ... 17999999:
+ return 2;
+ case 18000000 ... 29999999:
+ return 3;
+ case 30000000 ... 49999999:
+ return 4;
+ case 50000000 ... 79999999:
+ return 5;
+ case 80000000 ... 129999999:
+ return 6;
+ }
+
+ return 7;
+}
+
+/**
+ * __wrpll_calc_fbdiv() - return feedback fixed divide value
+ * @c: ptr to a struct wrpll_cfg record to read from
+ *
+ * The internal feedback path includes a fixed by-two divider; the
+ * external feedback path does not. Return the appropriate divider
+ * value (2 or 1) depending on whether internal or external feedback
+ * is enabled. This code doesn't test for invalid configurations
+ * (e.g. both or neither of WRPLL_FLAGS_*_FEEDBACK are set); it relies
+ * on the caller to do so.
+ *
+ * Context: Any context. Caller must protect the memory pointed to by
+ * @c from simultaneous modification.
+ *
+ * Return: 2 if internal feedback is enabled or 1 if external feedback
+ * is enabled.
+ */
+static u8 __wrpll_calc_fbdiv(const struct wrpll_cfg *c)
+{
+ return (c->flags & WRPLL_FLAGS_INT_FEEDBACK_MASK) ? 2 : 1;
+}
+
+/**
+ * __wrpll_calc_divq() - determine DIVQ based on target PLL output clock rate
+ * @target_rate: target PLL output clock rate
+ * @vco_rate: pointer to a u64 to store the computed VCO rate into
+ *
+ * Determine a reasonable value for the PLL Q post-divider, based on the
+ * target output rate @target_rate for the PLL. Along with returning the
+ * computed Q divider value as the return value, this function stores the
+ * desired target VCO rate into the variable pointed to by @vco_rate.
+ *
+ * Context: Any context. Caller must protect the memory pointed to by
+ * @vco_rate from simultaneous access or modification.
+ *
+ * Return: a positive integer DIVQ value to be programmed into the hardware
+ * upon success, or 0 upon error (since 0 is an invalid DIVQ value)
+ */
+static u8 __wrpll_calc_divq(u32 target_rate, u64 *vco_rate)
+{
+ u64 s;
+ u8 divq = 0;
+
+ if (!vco_rate) {
+ WARN_ON(1);
+ goto wcd_out;
+ }
+
+ s = div_u64(MAX_VCO_FREQ, target_rate);
+ if (s <= 1) {
+ divq = 1;
+ *vco_rate = MAX_VCO_FREQ;
+ } else if (s > MAX_DIVQ_DIVISOR) {
+ divq = ilog2(MAX_DIVQ_DIVISOR);
+ *vco_rate = MIN_VCO_FREQ;
+ } else {
+ divq = ilog2(s);
+ *vco_rate = (u64)target_rate << divq;
+ }
+
+wcd_out:
+ return divq;
+}
+
+/**
+ * __wrpll_update_parent_rate() - update PLL data when parent rate changes
+ * @c: ptr to a struct wrpll_cfg record to write PLL data to
+ * @parent_rate: PLL input refclk rate (pre-R-divider)
+ *
+ * Pre-compute some data used by the PLL configuration algorithm when
+ * the PLL's reference clock rate changes. The intention is to avoid
+ * computation when the parent rate remains constant - expected to be
+ * the common case.
+ *
+ * Returns: 0 upon success or -ERANGE if the reference clock rate is
+ * out of range.
+ */
+static int __wrpll_update_parent_rate(struct wrpll_cfg *c,
+ unsigned long parent_rate)
+{
+ u8 max_r_for_parent;
+
+ if (parent_rate > MAX_INPUT_FREQ || parent_rate < MIN_POST_DIVR_FREQ)
+ return -ERANGE;
+
+ c->parent_rate = parent_rate;
+ max_r_for_parent = div_u64(parent_rate, MIN_POST_DIVR_FREQ);
+ c->max_r = min_t(u8, MAX_DIVR_DIVISOR, max_r_for_parent);
+
+ c->init_r = DIV_ROUND_UP_ULL(parent_rate, MAX_POST_DIVR_FREQ);
+
+ return 0;
+}
+
+/**
+ * wrpll_configure() - compute PLL configuration for a target rate
+ * @c: ptr to a struct wrpll_cfg record to write into
+ * @target_rate: target PLL output clock rate (post-Q-divider)
+ * @parent_rate: PLL input refclk rate (pre-R-divider)
+ *
+ * Compute the appropriate PLL signal configuration values and store
+ * in PLL context @c. PLL reprogramming is not glitchless, so the
+ * caller should switch any downstream logic to a different clock
+ * source or clock-gate it before presenting these values to the PLL
+ * configuration signals.
+ *
+ * The caller must pass this function a pre-initialized struct
+ * wrpll_cfg record: either initialized to zero (with the
+ * exception of the .name and .flags fields) or read from the PLL.
+ *
+ * Context: Any context. Caller must protect the memory pointed to by @c
+ * from simultaneous access or modification.
+ *
+ * Return: 0 upon success; anything else upon failure.
+ */
+int wrpll_configure_for_rate(struct wrpll_cfg *c, u32 target_rate,
+ unsigned long parent_rate)
+{
+ unsigned long ratio;
+ u64 target_vco_rate, delta, best_delta, f_pre_div, vco, vco_pre;
+ u32 best_f, f, post_divr_freq;
+ u8 fbdiv, divq, best_r, r;
+ int range;
+
+ if (c->flags == 0) {
+ WARN(1, "%s called with uninitialized PLL config", __func__);
+ return -EINVAL;
+ }
+
+ /* Initialize rounding data if it hasn't been initialized already */
+ if (parent_rate != c->parent_rate) {
+ if (__wrpll_update_parent_rate(c, parent_rate)) {
+ pr_err("%s: PLL input rate is out of range\n",
+ __func__);
+ return -ERANGE;
+ }
+ }
+
+ c->flags &= ~WRPLL_FLAGS_RESET_MASK;
+
+ /* Put the PLL into bypass if the user requests the parent clock rate */
+ if (target_rate == parent_rate) {
+ c->flags |= WRPLL_FLAGS_BYPASS_MASK;
+ return 0;
+ }
+
+ c->flags &= ~WRPLL_FLAGS_BYPASS_MASK;
+
+ /* Calculate the Q shift and target VCO rate */
+ divq = __wrpll_calc_divq(target_rate, &target_vco_rate);
+ if (!divq)
+ return -1;
+ c->divq = divq;
+
+ /* Precalculate the pre-Q divider target ratio */
+ ratio = div64_u64((target_vco_rate << ROUND_SHIFT), parent_rate);
+
+ fbdiv = __wrpll_calc_fbdiv(c);
+ best_r = 0;
+ best_f = 0;
+ best_delta = MAX_VCO_FREQ;
+
+ /*
+ * Consider all values for R which land within
+ * [MIN_POST_DIVR_FREQ, MAX_POST_DIVR_FREQ]; prefer smaller R
+ */
+ for (r = c->init_r; r <= c->max_r; ++r) {
+ f_pre_div = ratio * r;
+ f = (f_pre_div + (1 << ROUND_SHIFT)) >> ROUND_SHIFT;
+ f >>= (fbdiv - 1);
+
+ post_divr_freq = div_u64(parent_rate, r);
+ vco_pre = fbdiv * post_divr_freq;
+ vco = vco_pre * f;
+
+ /* Ensure rounding didn't take us out of range */
+ if (vco > target_vco_rate) {
+ --f;
+ vco = vco_pre * f;
+ } else if (vco < MIN_VCO_FREQ) {
+ ++f;
+ vco = vco_pre * f;
+ }
+
+ delta = abs(target_rate - vco);
+ if (delta < best_delta) {
+ best_delta = delta;
+ best_r = r;
+ best_f = f;
+ }
+ }
+
+ c->divr = best_r - 1;
+ c->divf = best_f - 1;
+
+ post_divr_freq = div_u64(parent_rate, best_r);
+
+ /* Pick the best PLL jitter filter */
+ range = __wrpll_calc_filter_range(post_divr_freq);
+ if (range < 0)
+ return range;
+ c->range = range;
+
+ return 0;
+}
+
+/**
+ * wrpll_calc_output_rate() - calculate the PLL's target output rate
+ * @c: ptr to a struct wrpll_cfg record to read from
+ * @parent_rate: PLL refclk rate
+ *
+ * Given a pointer to the PLL's current input configuration @c and the
+ * PLL's input reference clock rate @parent_rate (before the R
+ * pre-divider), calculate the PLL's output clock rate (after the Q
+ * post-divider).
+ *
+ * Context: Any context. Caller must protect the memory pointed to by @c
+ * from simultaneous modification.
+ *
+ * Return: the PLL's output clock rate, in Hz. The return value from
+ * this function is intended to be convenient to pass directly
+ * to the Linux clock framework; thus there is no explicit
+ * error return value.
+ */
+unsigned long wrpll_calc_output_rate(const struct wrpll_cfg *c,
+ unsigned long parent_rate)
+{
+ u8 fbdiv;
+ u64 n;
+
+ if (c->flags & WRPLL_FLAGS_EXT_FEEDBACK_MASK) {
+ WARN(1, "external feedback mode not yet supported");
+ return ULONG_MAX;
+ }
+
+ fbdiv = __wrpll_calc_fbdiv(c);
+ n = parent_rate * fbdiv * (c->divf + 1);
+ n = div_u64(n, c->divr + 1);
+ n >>= c->divq;
+
+ return n;
+}
+
+/**
+ * wrpll_calc_max_lock_us() - return the time for the PLL to lock
+ * @c: ptr to a struct wrpll_cfg record to read from
+ *
+ * Return the minimum amount of time (in microseconds) that the caller
+ * must wait after reprogramming the PLL to ensure that it is locked
+ * to the input frequency and stable. This is likely to depend on the DIVR
+ * value; this is under discussion with the manufacturer.
+ *
+ * Return: the minimum amount of time the caller must wait for the PLL
+ * to lock (in microseconds)
+ */
+unsigned int wrpll_calc_max_lock_us(const struct wrpll_cfg *c)
+{
+ return MAX_LOCK_US;
+}
diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index dbee13a..9249cf9 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -143,6 +143,17 @@
rate = rate / apb_div;
}
break;
+ case BCLK_SDCLK:
+ {
+ ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)
+ & SCU_SDCLK_DIV_MASK)
+ >> SCU_SDCLK_DIV_SHIFT);
+ rate = ast2500_get_hpll_rate(clkin,
+ readl(&priv->
+ scu->h_pll_param));
+ rate = rate / apb_div;
+ }
+ break;
case PCLK_UART1:
rate = ast2500_get_uart_clk_rate(priv->scu, 1);
break;
@@ -436,6 +447,22 @@
struct ast2500_clk_priv *priv = dev_get_priv(clk->dev);
switch (clk->id) {
+ case BCLK_SDCLK:
+ if (readl(&priv->scu->clk_stop_ctrl1) & SCU_CLKSTOP_SDCLK) {
+ ast_scu_unlock(priv->scu);
+
+ setbits_le32(&priv->scu->sysreset_ctrl1,
+ SCU_SYSRESET_SDIO);
+ udelay(100);
+ clrbits_le32(&priv->scu->clk_stop_ctrl1,
+ SCU_CLKSTOP_SDCLK);
+ mdelay(10);
+ clrbits_le32(&priv->scu->sysreset_ctrl1,
+ SCU_SYSRESET_SDIO);
+
+ ast_scu_lock(priv->scu);
+ }
+ break;
/*
* For MAC clocks the clock rate is
* configured based on whether RGMII or RMII mode has been selected
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
new file mode 100644
index 0000000..a5626c3
--- /dev/null
+++ b/drivers/clk/clk-composite.c
@@ -0,0 +1,160 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2013 NVIDIA CORPORATION. All rights reserved.
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <clk-uclass.h>
+#include <dm/device.h>
+#include <linux/clk-provider.h>
+#include <clk.h>
+
+#include "clk.h"
+
+#define UBOOT_DM_CLK_COMPOSITE "clk_composite"
+
+static u8 clk_composite_get_parent(struct clk *clk)
+{
+ struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?
+ (struct clk *)dev_get_clk_ptr(clk->dev) : clk);
+ struct clk *mux = composite->mux;
+
+ return clk_mux_get_parent(mux);
+}
+
+static int clk_composite_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?
+ (struct clk *)dev_get_clk_ptr(clk->dev) : clk);
+ const struct clk_ops *mux_ops = composite->mux_ops;
+ struct clk *mux = composite->mux;
+
+ return mux_ops->set_parent(mux, parent);
+}
+
+static unsigned long clk_composite_recalc_rate(struct clk *clk)
+{
+ struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?
+ (struct clk *)dev_get_clk_ptr(clk->dev) : clk);
+ const struct clk_ops *rate_ops = composite->rate_ops;
+ struct clk *rate = composite->rate;
+
+ return rate_ops->get_rate(rate);
+}
+
+static ulong clk_composite_set_rate(struct clk *clk, unsigned long rate)
+{
+ struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?
+ (struct clk *)dev_get_clk_ptr(clk->dev) : clk);
+ const struct clk_ops *rate_ops = composite->rate_ops;
+ struct clk *clk_rate = composite->rate;
+
+ return rate_ops->set_rate(clk_rate, rate);
+}
+
+static int clk_composite_enable(struct clk *clk)
+{
+ struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?
+ (struct clk *)dev_get_clk_ptr(clk->dev) : clk);
+ const struct clk_ops *gate_ops = composite->gate_ops;
+ struct clk *gate = composite->gate;
+
+ return gate_ops->enable(gate);
+}
+
+static int clk_composite_disable(struct clk *clk)
+{
+ struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?
+ (struct clk *)dev_get_clk_ptr(clk->dev) : clk);
+ const struct clk_ops *gate_ops = composite->gate_ops;
+ struct clk *gate = composite->gate;
+
+ gate_ops->disable(gate);
+
+ return 0;
+}
+
+struct clk_ops clk_composite_ops = {
+ /* This will be set according to clk_register_composite */
+};
+
+struct clk *clk_register_composite(struct device *dev, const char *name,
+ const char * const *parent_names,
+ int num_parents, struct clk *mux,
+ const struct clk_ops *mux_ops,
+ struct clk *rate,
+ const struct clk_ops *rate_ops,
+ struct clk *gate,
+ const struct clk_ops *gate_ops,
+ unsigned long flags)
+{
+ struct clk *clk;
+ struct clk_composite *composite;
+ int ret;
+ struct clk_ops *composite_ops = &clk_composite_ops;
+
+ composite = kzalloc(sizeof(*composite), GFP_KERNEL);
+ if (!composite)
+ return ERR_PTR(-ENOMEM);
+
+ if (mux && mux_ops) {
+ composite->mux = mux;
+ composite->mux_ops = mux_ops;
+ if (mux_ops->set_parent)
+ composite_ops->set_parent = clk_composite_set_parent;
+ mux->data = (ulong)composite;
+ }
+
+ if (rate && rate_ops) {
+ if (!rate_ops->get_rate) {
+ clk = ERR_PTR(-EINVAL);
+ goto err;
+ }
+ composite_ops->get_rate = clk_composite_recalc_rate;
+
+ /* .set_rate requires either .round_rate or .determine_rate */
+ if (rate_ops->set_rate)
+ composite_ops->set_rate = clk_composite_set_rate;
+
+ composite->rate = rate;
+ composite->rate_ops = rate_ops;
+ rate->data = (ulong)composite;
+ }
+
+ if (gate && gate_ops) {
+ if (!gate_ops->enable || !gate_ops->disable) {
+ clk = ERR_PTR(-EINVAL);
+ goto err;
+ }
+
+ composite->gate = gate;
+ composite->gate_ops = gate_ops;
+ composite_ops->enable = clk_composite_enable;
+ composite_ops->disable = clk_composite_disable;
+ gate->data = (ulong)composite;
+ }
+
+ clk = &composite->clk;
+ ret = clk_register(clk, UBOOT_DM_CLK_COMPOSITE, name,
+ parent_names[clk_composite_get_parent(clk)]);
+ if (ret) {
+ clk = ERR_PTR(ret);
+ goto err;
+ }
+
+ return clk;
+
+err:
+ kfree(composite);
+ return clk;
+}
+
+U_BOOT_DRIVER(clk_composite) = {
+ .name = UBOOT_DM_CLK_COMPOSITE,
+ .id = UCLASS_CLK,
+ .ops = &clk_composite_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
new file mode 100644
index 0000000..822e09b
--- /dev/null
+++ b/drivers/clk/clk-divider.c
@@ -0,0 +1,243 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
+ * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
+ * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <clk-uclass.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+#include <dm/lists.h>
+#include <dm/device-internal.h>
+#include <linux/clk-provider.h>
+#include <linux/log2.h>
+#include <div64.h>
+#include <clk.h>
+#include "clk.h"
+
+#define UBOOT_DM_CLK_CCF_DIVIDER "ccf_clk_divider"
+
+static unsigned int _get_table_div(const struct clk_div_table *table,
+ unsigned int val)
+{
+ const struct clk_div_table *clkt;
+
+ for (clkt = table; clkt->div; clkt++)
+ if (clkt->val == val)
+ return clkt->div;
+ return 0;
+}
+
+static unsigned int _get_div(const struct clk_div_table *table,
+ unsigned int val, unsigned long flags, u8 width)
+{
+ if (flags & CLK_DIVIDER_ONE_BASED)
+ return val;
+ if (flags & CLK_DIVIDER_POWER_OF_TWO)
+ return 1 << val;
+ if (flags & CLK_DIVIDER_MAX_AT_ZERO)
+ return val ? val : clk_div_mask(width) + 1;
+ if (table)
+ return _get_table_div(table, val);
+ return val + 1;
+}
+
+unsigned long divider_recalc_rate(struct clk *hw, unsigned long parent_rate,
+ unsigned int val,
+ const struct clk_div_table *table,
+ unsigned long flags, unsigned long width)
+{
+ unsigned int div;
+
+ div = _get_div(table, val, flags, width);
+ if (!div) {
+ WARN(!(flags & CLK_DIVIDER_ALLOW_ZERO),
+ "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
+ clk_hw_get_name(hw));
+ return parent_rate;
+ }
+
+ return DIV_ROUND_UP_ULL((u64)parent_rate, div);
+}
+
+static ulong clk_divider_recalc_rate(struct clk *clk)
+{
+ struct clk_divider *divider = to_clk_divider(clk_dev_binded(clk) ?
+ dev_get_clk_ptr(clk->dev) : clk);
+ unsigned long parent_rate = clk_get_parent_rate(clk);
+ unsigned int val;
+
+#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+ val = divider->io_divider_val;
+#else
+ val = readl(divider->reg);
+#endif
+ val >>= divider->shift;
+ val &= clk_div_mask(divider->width);
+
+ return divider_recalc_rate(clk, parent_rate, val, divider->table,
+ divider->flags, divider->width);
+}
+
+static bool _is_valid_table_div(const struct clk_div_table *table,
+ unsigned int div)
+{
+ const struct clk_div_table *clkt;
+
+ for (clkt = table; clkt->div; clkt++)
+ if (clkt->div == div)
+ return true;
+ return false;
+}
+
+static bool _is_valid_div(const struct clk_div_table *table, unsigned int div,
+ unsigned long flags)
+{
+ if (flags & CLK_DIVIDER_POWER_OF_TWO)
+ return is_power_of_2(div);
+ if (table)
+ return _is_valid_table_div(table, div);
+ return true;
+}
+
+static unsigned int _get_table_val(const struct clk_div_table *table,
+ unsigned int div)
+{
+ const struct clk_div_table *clkt;
+
+ for (clkt = table; clkt->div; clkt++)
+ if (clkt->div == div)
+ return clkt->val;
+ return 0;
+}
+
+static unsigned int _get_val(const struct clk_div_table *table,
+ unsigned int div, unsigned long flags, u8 width)
+{
+ if (flags & CLK_DIVIDER_ONE_BASED)
+ return div;
+ if (flags & CLK_DIVIDER_POWER_OF_TWO)
+ return __ffs(div);
+ if (flags & CLK_DIVIDER_MAX_AT_ZERO)
+ return (div == clk_div_mask(width) + 1) ? 0 : div;
+ if (table)
+ return _get_table_val(table, div);
+ return div - 1;
+}
+int divider_get_val(unsigned long rate, unsigned long parent_rate,
+ const struct clk_div_table *table, u8 width,
+ unsigned long flags)
+{
+ unsigned int div, value;
+
+ div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
+
+ if (!_is_valid_div(table, div, flags))
+ return -EINVAL;
+
+ value = _get_val(table, div, flags, width);
+
+ return min_t(unsigned int, value, clk_div_mask(width));
+}
+
+static ulong clk_divider_set_rate(struct clk *clk, unsigned long rate)
+{
+ struct clk_divider *divider = to_clk_divider(clk_dev_binded(clk) ?
+ dev_get_clk_ptr(clk->dev) : clk);
+ unsigned long parent_rate = clk_get_parent_rate(clk);
+ int value;
+ u32 val;
+
+ value = divider_get_val(rate, parent_rate, divider->table,
+ divider->width, divider->flags);
+ if (value < 0)
+ return value;
+
+ if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
+ val = clk_div_mask(divider->width) << (divider->shift + 16);
+ } else {
+ val = readl(divider->reg);
+ val &= ~(clk_div_mask(divider->width) << divider->shift);
+ }
+ val |= (u32)value << divider->shift;
+ writel(val, divider->reg);
+
+ return clk_get_rate(clk);
+}
+
+const struct clk_ops clk_divider_ops = {
+ .get_rate = clk_divider_recalc_rate,
+ .set_rate = clk_divider_set_rate,
+};
+
+static struct clk *_register_divider(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ void __iomem *reg, u8 shift, u8 width,
+ u8 clk_divider_flags, const struct clk_div_table *table)
+{
+ struct clk_divider *div;
+ struct clk *clk;
+ int ret;
+
+ if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
+ if (width + shift > 16) {
+ pr_warn("divider value exceeds LOWORD field\n");
+ return ERR_PTR(-EINVAL);
+ }
+ }
+
+ /* allocate the divider */
+ div = kzalloc(sizeof(*div), GFP_KERNEL);
+ if (!div)
+ return ERR_PTR(-ENOMEM);
+
+ /* struct clk_divider assignments */
+ div->reg = reg;
+ div->shift = shift;
+ div->width = width;
+ div->flags = clk_divider_flags;
+ div->table = table;
+#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+ div->io_divider_val = *(u32 *)reg;
+#endif
+
+ /* register the clock */
+ clk = &div->clk;
+
+ ret = clk_register(clk, UBOOT_DM_CLK_CCF_DIVIDER, name, parent_name);
+ if (ret) {
+ kfree(div);
+ return ERR_PTR(ret);
+ }
+
+ return clk;
+}
+
+struct clk *clk_register_divider(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ void __iomem *reg, u8 shift, u8 width,
+ u8 clk_divider_flags)
+{
+ struct clk *clk;
+
+ clk = _register_divider(dev, name, parent_name, flags, reg, shift,
+ width, clk_divider_flags, NULL);
+ if (IS_ERR(clk))
+ return ERR_CAST(clk);
+ return clk;
+}
+
+U_BOOT_DRIVER(ccf_clk_divider) = {
+ .name = UBOOT_DM_CLK_CCF_DIVIDER,
+ .id = UCLASS_CLK,
+ .ops = &clk_divider_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
new file mode 100644
index 0000000..711b058
--- /dev/null
+++ b/drivers/clk/clk-fixed-factor.c
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
+ */
+#include <common.h>
+#include <malloc.h>
+#include <clk-uclass.h>
+#include <dm/device.h>
+#include <linux/clk-provider.h>
+#include <div64.h>
+#include <clk.h>
+#include "clk.h"
+
+#define UBOOT_DM_CLK_IMX_FIXED_FACTOR "ccf_clk_fixed_factor"
+
+static ulong clk_factor_recalc_rate(struct clk *clk)
+{
+ struct clk_fixed_factor *fix =
+ to_clk_fixed_factor(dev_get_clk_ptr(clk->dev));
+ unsigned long parent_rate = clk_get_parent_rate(clk);
+ unsigned long long int rate;
+
+ rate = (unsigned long long int)parent_rate * fix->mult;
+ do_div(rate, fix->div);
+ return (ulong)rate;
+}
+
+const struct clk_ops ccf_clk_fixed_factor_ops = {
+ .get_rate = clk_factor_recalc_rate,
+};
+
+struct clk *clk_hw_register_fixed_factor(struct device *dev,
+ const char *name, const char *parent_name, unsigned long flags,
+ unsigned int mult, unsigned int div)
+{
+ struct clk_fixed_factor *fix;
+ struct clk *clk;
+ int ret;
+
+ fix = kzalloc(sizeof(*fix), GFP_KERNEL);
+ if (!fix)
+ return ERR_PTR(-ENOMEM);
+
+ /* struct clk_fixed_factor assignments */
+ fix->mult = mult;
+ fix->div = div;
+ clk = &fix->clk;
+
+ ret = clk_register(clk, UBOOT_DM_CLK_IMX_FIXED_FACTOR, name,
+ parent_name);
+ if (ret) {
+ kfree(fix);
+ return ERR_PTR(ret);
+ }
+
+ return clk;
+}
+
+struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ unsigned int mult, unsigned int div)
+{
+ struct clk *clk;
+
+ clk = clk_hw_register_fixed_factor(dev, name, parent_name, flags, mult,
+ div);
+ if (IS_ERR(clk))
+ return ERR_CAST(clk);
+ return clk;
+}
+
+U_BOOT_DRIVER(imx_clk_fixed_factor) = {
+ .name = UBOOT_DM_CLK_IMX_FIXED_FACTOR,
+ .id = UCLASS_CLK,
+ .ops = &ccf_clk_fixed_factor_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
new file mode 100644
index 0000000..70b8794
--- /dev/null
+++ b/drivers/clk/clk-gate.c
@@ -0,0 +1,159 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
+ * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
+ * Copyright 2019 NXP
+ *
+ * Gated clock implementation
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <clk-uclass.h>
+#include <dm/device.h>
+#include <linux/clk-provider.h>
+#include <clk.h>
+#include "clk.h"
+
+#define UBOOT_DM_CLK_GATE "clk_gate"
+
+/**
+ * DOC: basic gatable clock which can gate and ungate it's output
+ *
+ * Traits of this clock:
+ * prepare - clk_(un)prepare only ensures parent is (un)prepared
+ * enable - clk_enable and clk_disable are functional & control gating
+ * rate - inherits rate from parent. No clk_set_rate support
+ * parent - fixed parent. No clk_set_parent support
+ */
+
+/*
+ * It works on following logic:
+ *
+ * For enabling clock, enable = 1
+ * set2dis = 1 -> clear bit -> set = 0
+ * set2dis = 0 -> set bit -> set = 1
+ *
+ * For disabling clock, enable = 0
+ * set2dis = 1 -> set bit -> set = 1
+ * set2dis = 0 -> clear bit -> set = 0
+ *
+ * So, result is always: enable xor set2dis.
+ */
+static void clk_gate_endisable(struct clk *clk, int enable)
+{
+ struct clk_gate *gate = to_clk_gate(clk_dev_binded(clk) ?
+ dev_get_clk_ptr(clk->dev) : clk);
+ int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
+ u32 reg;
+
+ set ^= enable;
+
+ if (gate->flags & CLK_GATE_HIWORD_MASK) {
+ reg = BIT(gate->bit_idx + 16);
+ if (set)
+ reg |= BIT(gate->bit_idx);
+ } else {
+#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+ reg = gate->io_gate_val;
+#else
+ reg = readl(gate->reg);
+#endif
+
+ if (set)
+ reg |= BIT(gate->bit_idx);
+ else
+ reg &= ~BIT(gate->bit_idx);
+ }
+
+ writel(reg, gate->reg);
+}
+
+static int clk_gate_enable(struct clk *clk)
+{
+ clk_gate_endisable(clk, 1);
+
+ return 0;
+}
+
+static int clk_gate_disable(struct clk *clk)
+{
+ clk_gate_endisable(clk, 0);
+
+ return 0;
+}
+
+int clk_gate_is_enabled(struct clk *clk)
+{
+ struct clk_gate *gate = to_clk_gate(clk_dev_binded(clk) ?
+ dev_get_clk_ptr(clk->dev) : clk);
+ u32 reg;
+
+#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+ reg = gate->io_gate_val;
+#else
+ reg = readl(gate->reg);
+#endif
+
+ /* if a set bit disables this clk, flip it before masking */
+ if (gate->flags & CLK_GATE_SET_TO_DISABLE)
+ reg ^= BIT(gate->bit_idx);
+
+ reg &= BIT(gate->bit_idx);
+
+ return reg ? 1 : 0;
+}
+
+const struct clk_ops clk_gate_ops = {
+ .enable = clk_gate_enable,
+ .disable = clk_gate_disable,
+ .get_rate = clk_generic_get_rate,
+};
+
+struct clk *clk_register_gate(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ void __iomem *reg, u8 bit_idx,
+ u8 clk_gate_flags, spinlock_t *lock)
+{
+ struct clk_gate *gate;
+ struct clk *clk;
+ int ret;
+
+ if (clk_gate_flags & CLK_GATE_HIWORD_MASK) {
+ if (bit_idx > 15) {
+ pr_err("gate bit exceeds LOWORD field\n");
+ return ERR_PTR(-EINVAL);
+ }
+ }
+
+ /* allocate the gate */
+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+ if (!gate)
+ return ERR_PTR(-ENOMEM);
+
+ /* struct clk_gate assignments */
+ gate->reg = reg;
+ gate->bit_idx = bit_idx;
+ gate->flags = clk_gate_flags;
+#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+ gate->io_gate_val = *(u32 *)reg;
+#endif
+
+ clk = &gate->clk;
+
+ ret = clk_register(clk, UBOOT_DM_CLK_GATE, name, parent_name);
+ if (ret) {
+ kfree(gate);
+ return ERR_PTR(ret);
+ }
+
+ return clk;
+}
+
+U_BOOT_DRIVER(clk_gate) = {
+ .name = UBOOT_DM_CLK_GATE,
+ .id = UCLASS_CLK,
+ .ops = &clk_gate_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
new file mode 100644
index 0000000..5acc0b8
--- /dev/null
+++ b/drivers/clk/clk-mux.c
@@ -0,0 +1,240 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
+ * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
+ * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
+ *
+ * Simple multiplexer clock implementation
+ */
+
+/*
+ * U-Boot CCF porting node:
+ *
+ * The Linux kernel - as of tag: 5.0-rc3 is using also the imx_clk_fixup_mux()
+ * version of CCF mux. It is used on e.g. imx6q to provide fixes (like
+ * imx_cscmr1_fixup) for broken HW.
+ *
+ * At least for IMX6Q (but NOT IMX6QP) it is important when we set the parent
+ * clock.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <clk-uclass.h>
+#include <dm/device.h>
+#include <linux/clk-provider.h>
+#include <clk.h>
+#include "clk.h"
+
+#define UBOOT_DM_CLK_CCF_MUX "ccf_clk_mux"
+
+int clk_mux_val_to_index(struct clk *clk, u32 *table, unsigned int flags,
+ unsigned int val)
+{
+ struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
+ dev_get_clk_ptr(clk->dev) : clk);
+ int num_parents = mux->num_parents;
+
+ if (table) {
+ int i;
+
+ for (i = 0; i < num_parents; i++)
+ if (table[i] == val)
+ return i;
+ return -EINVAL;
+ }
+
+ if (val && (flags & CLK_MUX_INDEX_BIT))
+ val = ffs(val) - 1;
+
+ if (val && (flags & CLK_MUX_INDEX_ONE))
+ val--;
+
+ if (val >= num_parents)
+ return -EINVAL;
+
+ return val;
+}
+
+unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index)
+{
+ unsigned int val = index;
+
+ if (table) {
+ val = table[index];
+ } else {
+ if (flags & CLK_MUX_INDEX_BIT)
+ val = 1 << index;
+
+ if (flags & CLK_MUX_INDEX_ONE)
+ val++;
+ }
+
+ return val;
+}
+
+u8 clk_mux_get_parent(struct clk *clk)
+{
+ struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
+ dev_get_clk_ptr(clk->dev) : clk);
+ u32 val;
+
+#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+ val = mux->io_mux_val;
+#else
+ val = readl(mux->reg);
+#endif
+ val >>= mux->shift;
+ val &= mux->mask;
+
+ return clk_mux_val_to_index(clk, mux->table, mux->flags, val);
+}
+
+static int clk_fetch_parent_index(struct clk *clk,
+ struct clk *parent)
+{
+ struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
+ dev_get_clk_ptr(clk->dev) : clk);
+
+ int i;
+
+ if (!parent)
+ return -EINVAL;
+
+ for (i = 0; i < mux->num_parents; i++) {
+ if (!strcmp(parent->dev->name, mux->parent_names[i]))
+ return i;
+ }
+
+ return -EINVAL;
+}
+
+static int clk_mux_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
+ dev_get_clk_ptr(clk->dev) : clk);
+ int index;
+ u32 val;
+ u32 reg;
+
+ index = clk_fetch_parent_index(clk, parent);
+ if (index < 0) {
+ printf("Could not fetch index\n");
+ return index;
+ }
+
+ val = clk_mux_index_to_val(mux->table, mux->flags, index);
+
+ if (mux->flags & CLK_MUX_HIWORD_MASK) {
+ reg = mux->mask << (mux->shift + 16);
+ } else {
+ reg = readl(mux->reg);
+ reg &= ~(mux->mask << mux->shift);
+ }
+ val = val << mux->shift;
+ reg |= val;
+ writel(reg, mux->reg);
+
+ return 0;
+}
+
+const struct clk_ops clk_mux_ops = {
+ .get_rate = clk_generic_get_rate,
+ .set_parent = clk_mux_set_parent,
+};
+
+struct clk *clk_hw_register_mux_table(struct device *dev, const char *name,
+ const char * const *parent_names, u8 num_parents,
+ unsigned long flags,
+ void __iomem *reg, u8 shift, u32 mask,
+ u8 clk_mux_flags, u32 *table)
+{
+ struct clk_mux *mux;
+ struct clk *clk;
+ u8 width = 0;
+ int ret;
+
+ if (clk_mux_flags & CLK_MUX_HIWORD_MASK) {
+ width = fls(mask) - ffs(mask) + 1;
+ if (width + shift > 16) {
+ pr_err("mux value exceeds LOWORD field\n");
+ return ERR_PTR(-EINVAL);
+ }
+ }
+
+ /* allocate the mux */
+ mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+ if (!mux)
+ return ERR_PTR(-ENOMEM);
+
+ /* U-boot specific assignments */
+ mux->parent_names = parent_names;
+ mux->num_parents = num_parents;
+
+ /* struct clk_mux assignments */
+ mux->reg = reg;
+ mux->shift = shift;
+ mux->mask = mask;
+ mux->flags = clk_mux_flags;
+ mux->table = table;
+#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+ mux->io_mux_val = *(u32 *)reg;
+#endif
+
+ clk = &mux->clk;
+
+ /*
+ * Read the current mux setup - so we assign correct parent.
+ *
+ * Changing parent would require changing internals of udevice struct
+ * for the corresponding clock (to do that define .set_parent() method.
+ */
+ ret = clk_register(clk, UBOOT_DM_CLK_CCF_MUX, name,
+ parent_names[clk_mux_get_parent(clk)]);
+ if (ret) {
+ kfree(mux);
+ return ERR_PTR(ret);
+ }
+
+ return clk;
+}
+
+struct clk *clk_register_mux_table(struct device *dev, const char *name,
+ const char * const *parent_names, u8 num_parents,
+ unsigned long flags,
+ void __iomem *reg, u8 shift, u32 mask,
+ u8 clk_mux_flags, u32 *table)
+{
+ struct clk *clk;
+
+ clk = clk_hw_register_mux_table(dev, name, parent_names, num_parents,
+ flags, reg, shift, mask, clk_mux_flags,
+ table);
+ if (IS_ERR(clk))
+ return ERR_CAST(clk);
+ return clk;
+}
+
+struct clk *clk_register_mux(struct device *dev, const char *name,
+ const char * const *parent_names, u8 num_parents,
+ unsigned long flags,
+ void __iomem *reg, u8 shift, u8 width,
+ u8 clk_mux_flags)
+{
+ u32 mask = BIT(width) - 1;
+
+ return clk_register_mux_table(dev, name, parent_names, num_parents,
+ flags, reg, shift, mask, clk_mux_flags,
+ NULL);
+}
+
+U_BOOT_DRIVER(ccf_clk_mux) = {
+ .name = UBOOT_DM_CLK_CCF_MUX,
+ .id = UCLASS_CLK,
+ .ops = &clk_mux_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 79b3b04..64c181f 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -13,6 +13,7 @@
#include <dm/read.h>
#include <dt-structs.h>
#include <errno.h>
+#include <linux/clk-provider.h>
static inline const struct clk_ops *clk_dev_ops(struct udevice *dev)
{
@@ -51,6 +52,8 @@
else
clk->id = 0;
+ clk->data = 0;
+
return 0;
}
@@ -282,6 +285,9 @@
{
int ret;
+ if (!dev_of_valid(dev))
+ return 0;
+
/* If this not in SPL and pre-reloc state, don't take any action. */
if (!(IS_ENABLED(CONFIG_SPL_BUILD) || (gd->flags & GD_FLG_RELOC)))
return 0;
@@ -379,6 +385,43 @@
return ops->get_rate(clk);
}
+struct clk *clk_get_parent(struct clk *clk)
+{
+ struct udevice *pdev;
+ struct clk *pclk;
+
+ debug("%s(clk=%p)\n", __func__, clk);
+
+ pdev = dev_get_parent(clk->dev);
+ pclk = dev_get_clk_ptr(pdev);
+ if (!pclk)
+ return ERR_PTR(-ENODEV);
+
+ return pclk;
+}
+
+long long clk_get_parent_rate(struct clk *clk)
+{
+ const struct clk_ops *ops;
+ struct clk *pclk;
+
+ debug("%s(clk=%p)\n", __func__, clk);
+
+ pclk = clk_get_parent(clk);
+ if (IS_ERR(pclk))
+ return -ENODEV;
+
+ ops = clk_dev_ops(pclk->dev);
+ if (!ops->get_rate)
+ return -ENOSYS;
+
+ /* Read the 'rate' if not already set or if proper flag set*/
+ if (!pclk->rate || pclk->flags & CLK_GET_RATE_NOCACHE)
+ pclk->rate = clk_get_rate(pclk);
+
+ return pclk->rate;
+}
+
ulong clk_set_rate(struct clk *clk, ulong rate)
{
const struct clk_ops *ops = clk_dev_ops(clk->dev);
@@ -406,13 +449,45 @@
int clk_enable(struct clk *clk)
{
const struct clk_ops *ops = clk_dev_ops(clk->dev);
+ struct clk *clkp = NULL;
+ int ret;
debug("%s(clk=%p)\n", __func__, clk);
- if (!ops->enable)
- return -ENOSYS;
+ if (CONFIG_IS_ENABLED(CLK_CCF)) {
+ /* Take id 0 as a non-valid clk, such as dummy */
+ if (clk->id && !clk_get_by_id(clk->id, &clkp)) {
+ if (clkp->enable_count) {
+ clkp->enable_count++;
+ return 0;
+ }
+ if (clkp->dev->parent &&
+ device_get_uclass_id(clkp->dev) == UCLASS_CLK) {
+ ret = clk_enable(dev_get_clk_ptr(clkp->dev->parent));
+ if (ret) {
+ printf("Enable %s failed\n",
+ clkp->dev->parent->name);
+ return ret;
+ }
+ }
+ }
- return ops->enable(clk);
+ if (ops->enable) {
+ ret = ops->enable(clk);
+ if (ret) {
+ printf("Enable %s failed\n", clk->dev->name);
+ return ret;
+ }
+ }
+ if (clkp)
+ clkp->enable_count++;
+ } else {
+ if (!ops->enable)
+ return -ENOSYS;
+ return ops->enable(clk);
+ }
+
+ return 0;
}
int clk_enable_bulk(struct clk_bulk *bulk)
@@ -431,13 +506,46 @@
int clk_disable(struct clk *clk)
{
const struct clk_ops *ops = clk_dev_ops(clk->dev);
+ struct clk *clkp = NULL;
+ int ret;
debug("%s(clk=%p)\n", __func__, clk);
- if (!ops->disable)
- return -ENOSYS;
+ if (CONFIG_IS_ENABLED(CLK_CCF)) {
+ if (clk->id && !clk_get_by_id(clk->id, &clkp)) {
+ if (clkp->enable_count == 0) {
+ printf("clk %s already disabled\n",
+ clkp->dev->name);
+ return 0;
+ }
- return ops->disable(clk);
+ if (--clkp->enable_count > 0)
+ return 0;
+ }
+
+ if (ops->disable) {
+ ret = ops->disable(clk);
+ if (ret)
+ return ret;
+ }
+
+ if (clkp && clkp->dev->parent &&
+ device_get_uclass_id(clkp->dev) == UCLASS_CLK) {
+ ret = clk_disable(dev_get_clk_ptr(clkp->dev->parent));
+ if (ret) {
+ printf("Disable %s failed\n",
+ clkp->dev->parent->name);
+ return ret;
+ }
+ }
+ } else {
+ if (!ops->disable)
+ return -ENOSYS;
+
+ return ops->disable(clk);
+ }
+
+ return 0;
}
int clk_disable_bulk(struct clk_bulk *bulk)
@@ -453,6 +561,41 @@
return 0;
}
+int clk_get_by_id(ulong id, struct clk **clkp)
+{
+ struct udevice *dev;
+ struct uclass *uc;
+ int ret;
+
+ ret = uclass_get(UCLASS_CLK, &uc);
+ if (ret)
+ return ret;
+
+ uclass_foreach_dev(dev, uc) {
+ struct clk *clk = dev_get_clk_ptr(dev);
+
+ if (clk && clk->id == id) {
+ *clkp = clk;
+ return 0;
+ }
+ }
+
+ return -ENOENT;
+}
+
+bool clk_is_match(const struct clk *p, const struct clk *q)
+{
+ /* trivial case: identical struct clk's or both NULL */
+ if (p == q)
+ return true;
+
+ /* same device, id and data */
+ if (p->dev == q->dev && p->id == q->id && p->data == q->data)
+ return true;
+
+ return false;
+}
+
UCLASS_DRIVER(clk) = {
.id = UCLASS_CLK,
.name = "clk",
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
new file mode 100644
index 0000000..1cf9987
--- /dev/null
+++ b/drivers/clk/clk.c
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+#include <dm/lists.h>
+#include <dm/device-internal.h>
+#include <clk.h>
+
+int clk_register(struct clk *clk, const char *drv_name,
+ const char *name, const char *parent_name)
+{
+ struct udevice *parent;
+ struct driver *drv;
+ int ret;
+
+ ret = uclass_get_device_by_name(UCLASS_CLK, parent_name, &parent);
+ if (ret)
+ printf("%s: UCLASS parent: 0x%p\n", __func__, parent);
+
+ debug("%s: name: %s parent: %s [0x%p]\n", __func__, name, parent->name,
+ parent);
+
+ drv = lists_driver_lookup_name(drv_name);
+ if (!drv) {
+ printf("%s: %s is not a valid driver name\n",
+ __func__, drv_name);
+ return -ENOENT;
+ }
+
+ ret = device_bind(parent, drv, name, NULL, -1, &clk->dev);
+ if (ret) {
+ printf("%s: CLK: %s driver bind error [%d]!\n", __func__, name,
+ ret);
+ return ret;
+ }
+
+ clk->enable_count = 0;
+ /* Store back pointer to clk from udevice */
+ clk->dev->uclass_priv = clk;
+
+ return 0;
+}
+
+ulong clk_generic_get_rate(struct clk *clk)
+{
+ return clk_get_parent_rate(clk);
+}
+
+const char *clk_hw_get_name(const struct clk *hw)
+{
+ return hw->dev->name;
+}
+
+bool clk_dev_binded(struct clk *clk)
+{
+ if (clk->dev && (clk->dev->flags & DM_FLAG_BOUND))
+ return true;
+
+ return false;
+}
diff --git a/drivers/clk/clk_fixed_factor.c b/drivers/clk/clk_fixed_factor.c
index 5fa20a8..dcdb6dd 100644
--- a/drivers/clk/clk_fixed_factor.c
+++ b/drivers/clk/clk_fixed_factor.c
@@ -24,9 +24,6 @@
uint64_t rate;
struct clk_fixed_factor *ff = to_clk_fixed_factor(clk->dev);
- if (clk->id != 0)
- return -EINVAL;
-
rate = clk_get_rate(&ff->parent);
if (IS_ERR_VALUE(rate))
return rate;
diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c
index d8d9f86..f511267 100644
--- a/drivers/clk/clk_fixed_rate.c
+++ b/drivers/clk/clk_fixed_rate.c
@@ -6,18 +6,10 @@
#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
-
-struct clk_fixed_rate {
- unsigned long fixed_rate;
-};
-
-#define to_clk_fixed_rate(dev) ((struct clk_fixed_rate *)dev_get_platdata(dev))
+#include <linux/clk-provider.h>
static ulong clk_fixed_rate_get_rate(struct clk *clk)
{
- if (clk->id != 0)
- return -EINVAL;
-
return to_clk_fixed_rate(clk->dev)->fixed_rate;
}
@@ -27,10 +19,15 @@
static int clk_fixed_rate_ofdata_to_platdata(struct udevice *dev)
{
+ struct clk *clk = &to_clk_fixed_rate(dev)->clk;
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
to_clk_fixed_rate(dev)->fixed_rate =
dev_read_u32_default(dev, "clock-frequency", 0);
#endif
+ /* Make fixed rate clock accessible from higher level struct clk */
+ dev->uclass_priv = clk;
+ clk->dev = dev;
+ clk->enable_count = 0;
return 0;
}
diff --git a/drivers/clk/clk_sandbox_ccf.c b/drivers/clk/clk_sandbox_ccf.c
new file mode 100644
index 0000000..9fa2722
--- /dev/null
+++ b/drivers/clk/clk_sandbox_ccf.c
@@ -0,0 +1,280 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * Common Clock Framework [CCF] driver for Sandbox
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <clk.h>
+#include <asm/clk.h>
+#include <clk-uclass.h>
+#include <linux/clk-provider.h>
+#include <sandbox-clk.h>
+
+/*
+ * Sandbox implementation of CCF primitives necessary for clk-uclass testing
+ *
+ * --- Sandbox PLLv3 ---
+ */
+struct clk_pllv3 {
+ struct clk clk;
+ u32 div_mask;
+ u32 div_shift;
+};
+
+int sandbox_clk_enable_count(struct clk *clk)
+{
+ struct clk *clkp = NULL;
+ int ret;
+
+ ret = clk_get_by_id(clk->id, &clkp);
+ if (ret)
+ return 0;
+
+ return clkp->enable_count;
+}
+
+static ulong clk_pllv3_get_rate(struct clk *clk)
+{
+ unsigned long parent_rate = clk_get_parent_rate(clk);
+
+ return parent_rate * 24;
+}
+
+static const struct clk_ops clk_pllv3_generic_ops = {
+ .get_rate = clk_pllv3_get_rate,
+};
+
+struct clk *sandbox_clk_pllv3(enum sandbox_pllv3_type type, const char *name,
+ const char *parent_name, void __iomem *base,
+ u32 div_mask)
+{
+ struct clk_pllv3 *pll;
+ struct clk *clk;
+ char *drv_name = "sandbox_clk_pllv3";
+ int ret;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+
+ pll->div_mask = div_mask;
+ clk = &pll->clk;
+
+ ret = clk_register(clk, drv_name, name, parent_name);
+ if (ret) {
+ kfree(pll);
+ return ERR_PTR(ret);
+ }
+
+ return clk;
+}
+
+U_BOOT_DRIVER(sandbox_clk_pll_generic) = {
+ .name = "sandbox_clk_pllv3",
+ .id = UCLASS_CLK,
+ .ops = &clk_pllv3_generic_ops,
+};
+
+/* --- Sandbox PLLv3 --- */
+/* --- Sandbox Gate --- */
+struct clk_gate2 {
+ struct clk clk;
+ bool state;
+};
+
+#define to_clk_gate2(_clk) container_of(_clk, struct clk_gate2, clk)
+
+static int clk_gate2_enable(struct clk *clk)
+{
+ struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev));
+
+ gate->state = 1;
+ return 0;
+}
+
+static int clk_gate2_disable(struct clk *clk)
+{
+ struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev));
+
+ gate->state = 0;
+ return 0;
+}
+
+static const struct clk_ops clk_gate2_ops = {
+ .enable = clk_gate2_enable,
+ .disable = clk_gate2_disable,
+ .get_rate = clk_generic_get_rate,
+};
+
+struct clk *sandbox_clk_register_gate2(struct device *dev, const char *name,
+ const char *parent_name,
+ unsigned long flags, void __iomem *reg,
+ u8 bit_idx, u8 cgr_val,
+ u8 clk_gate2_flags)
+{
+ struct clk_gate2 *gate;
+ struct clk *clk;
+ int ret;
+
+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+ if (!gate)
+ return ERR_PTR(-ENOMEM);
+
+ gate->state = 0;
+ clk = &gate->clk;
+
+ ret = clk_register(clk, "sandbox_clk_gate2", name, parent_name);
+ if (ret) {
+ kfree(gate);
+ return ERR_PTR(ret);
+ }
+
+ return clk;
+}
+
+U_BOOT_DRIVER(sandbox_clk_gate2) = {
+ .name = "sandbox_clk_gate2",
+ .id = UCLASS_CLK,
+ .ops = &clk_gate2_ops,
+};
+
+static unsigned long sandbox_clk_composite_divider_recalc_rate(struct clk *clk)
+{
+ struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk);
+ struct clk_composite *composite = (struct clk_composite *)clk->data;
+ ulong parent_rate = clk_get_parent_rate(&composite->clk);
+ unsigned int val;
+
+ val = divider->io_divider_val;
+ val >>= divider->shift;
+ val &= clk_div_mask(divider->width);
+
+ return divider_recalc_rate(clk, parent_rate, val, divider->table,
+ divider->flags, divider->width);
+}
+
+static const struct clk_ops sandbox_clk_composite_divider_ops = {
+ .get_rate = sandbox_clk_composite_divider_recalc_rate,
+};
+
+struct clk *sandbox_clk_composite(const char *name,
+ const char * const *parent_names,
+ int num_parents, void __iomem *reg,
+ unsigned long flags)
+{
+ struct clk *clk = ERR_PTR(-ENOMEM);
+ struct clk_divider *div = NULL;
+ struct clk_gate *gate = NULL;
+ struct clk_mux *mux = NULL;
+
+ mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+ if (!mux)
+ goto fail;
+
+ mux->reg = reg;
+ mux->shift = 24;
+ mux->mask = 0x7;
+ mux->num_parents = num_parents;
+ mux->flags = flags;
+ mux->parent_names = parent_names;
+
+ div = kzalloc(sizeof(*div), GFP_KERNEL);
+ if (!div)
+ goto fail;
+
+ div->reg = reg;
+ div->shift = 16;
+ div->width = 3;
+ div->flags = CLK_DIVIDER_ROUND_CLOSEST | flags;
+
+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+ if (!gate)
+ goto fail;
+
+ gate->reg = reg;
+ gate->bit_idx = 28;
+ gate->flags = flags;
+
+ clk = clk_register_composite(NULL, name,
+ parent_names, num_parents,
+ &mux->clk, &clk_mux_ops, &div->clk,
+ &sandbox_clk_composite_divider_ops,
+ &gate->clk, &clk_gate_ops, flags);
+ if (IS_ERR(clk))
+ goto fail;
+
+ return clk;
+
+fail:
+ kfree(gate);
+ kfree(div);
+ kfree(mux);
+ return ERR_CAST(clk);
+}
+
+/* --- Sandbox Gate --- */
+/* The CCF core driver itself */
+static const struct udevice_id sandbox_clk_ccf_test_ids[] = {
+ { .compatible = "sandbox,clk-ccf" },
+ { }
+};
+
+static const char *const usdhc_sels[] = { "pll3_60m", "pll3_80m", };
+static const char *const i2c_sels[] = { "pll3_60m", "pll3_80m", };
+
+static int sandbox_clk_ccf_probe(struct udevice *dev)
+{
+ void *base = NULL;
+ u32 reg;
+
+ clk_dm(SANDBOX_CLK_PLL3,
+ sandbox_clk_pllv3(SANDBOX_PLLV3_USB, "pll3_usb_otg", "osc",
+ base + 0x10, 0x3));
+
+ clk_dm(SANDBOX_CLK_PLL3_60M,
+ sandbox_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8));
+
+ clk_dm(SANDBOX_CLK_PLL3_80M,
+ sandbox_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6));
+
+ /* The HW adds +1 to the divider value (2+1) is the divider */
+ reg = (2 << 19);
+ clk_dm(SANDBOX_CLK_ECSPI_ROOT,
+ sandbox_clk_divider("ecspi_root", "pll3_60m", ®, 19, 6));
+
+ clk_dm(SANDBOX_CLK_ECSPI1,
+ sandbox_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0));
+
+ /* Select 'pll3_60m' */
+ reg = 0;
+ clk_dm(SANDBOX_CLK_USDHC1_SEL,
+ sandbox_clk_mux("usdhc1_sel", ®, 16, 1, usdhc_sels,
+ ARRAY_SIZE(usdhc_sels)));
+
+ /* Select 'pll3_80m' */
+ reg = BIT(17);
+ clk_dm(SANDBOX_CLK_USDHC2_SEL,
+ sandbox_clk_mux("usdhc2_sel", ®, 17, 1, usdhc_sels,
+ ARRAY_SIZE(usdhc_sels)));
+
+ reg = BIT(28) | BIT(24) | BIT(16);
+ clk_dm(SANDBOX_CLK_I2C,
+ sandbox_clk_composite("i2c", i2c_sels, ARRAY_SIZE(i2c_sels),
+ ®, 0));
+
+ clk_dm(SANDBOX_CLK_I2C_ROOT,
+ sandbox_clk_gate2("i2c_root", "i2c", base + 0x7c, 0));
+
+ return 0;
+}
+
+U_BOOT_DRIVER(sandbox_clk_ccf) = {
+ .name = "sandbox_clk_ccf",
+ .id = UCLASS_CLK,
+ .probe = sandbox_clk_ccf_probe,
+ .of_match = sandbox_clk_ccf_test_ids,
+};
diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c
index f295e48..e87307f 100644
--- a/drivers/clk/clk_stm32mp1.c
+++ b/drivers/clk/clk_stm32mp1.c
@@ -15,6 +15,8 @@
#include <dt-bindings/clock/stm32mp1-clks.h>
#include <dt-bindings/clock/stm32mp1-clksrc.h>
+DECLARE_GLOBAL_DATA_PTR;
+
#ifndef CONFIG_STM32MP1_TRUSTED
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
/* activate clock tree initialization in the driver */
@@ -300,6 +302,7 @@
_DSI_SEL,
_ADC12_SEL,
_SPI1_SEL,
+ _RTC_SEL,
_PARENT_SEL_NB,
_UNKNOWN_SEL = 0xff,
};
@@ -534,6 +537,7 @@
STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5),
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB2ENSETR, 5, ADC12, _HCLK2),
@@ -569,6 +573,8 @@
STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
+
+ STM32MP1_CLK(RCC_BDCR, 20, RTC, _RTC_SEL),
};
static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
@@ -594,6 +600,7 @@
static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q};
static const u8 spi_parents[] = {_PLL4_P, _PLL3_Q, _I2S_CKIN, _CK_PER,
_PLL3_R};
+static const u8 rtc_parents[] = {_UNKNOWN_ID, _LSE, _LSI, _HSE};
static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
@@ -619,6 +626,9 @@
STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents),
STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x1, adc_parents),
STM32MP1_CLK_PARENT(_SPI1_SEL, RCC_SPI2S1CKSELR, 0, 0x7, spi_parents),
+ STM32MP1_CLK_PARENT(_RTC_SEL, RCC_BDCR, RCC_BDCR_RTCSRC_SHIFT,
+ (RCC_BDCR_RTCSRC_MASK >> RCC_BDCR_RTCSRC_SHIFT),
+ rtc_parents),
};
#ifdef STM32MP1_CLOCK_TREE_INIT
@@ -734,6 +744,7 @@
[_DSI_SEL] = "DSI",
[_ADC12_SEL] = "ADC12",
[_SPI1_SEL] = "SPI1",
+ [_RTC_SEL] = "RTC",
};
static const struct stm32mp1_clk_data stm32mp1_data = {
@@ -750,9 +761,6 @@
return 0;
}
- debug("%s: clk id %d = %x : %ld kHz\n", __func__, idx,
- (u32)priv->osc[idx], priv->osc[idx] / 1000);
-
return priv->osc[idx];
}
@@ -805,10 +813,11 @@
const struct stm32mp1_clk_sel *sel = priv->data->sel;
int i;
int s, p;
+ unsigned int idx;
- for (i = 0; i < ARRAY_SIZE(stm32mp1_clks); i++)
- if (stm32mp1_clks[i][0] == id)
- return stm32mp1_clks[i][1];
+ for (idx = 0; idx < ARRAY_SIZE(stm32mp1_clks); idx++)
+ if (stm32mp1_clks[idx][0] == id)
+ return stm32mp1_clks[idx][1];
i = stm32mp1_clk_get_id(priv, id);
if (i < 0)
@@ -853,8 +862,6 @@
src = selr & RCC_SELR_SRC_MASK;
refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
- debug("PLL%d : selr=%x refclk = %d kHz\n",
- pll_id, selr, (u32)(refclk / 1000));
return refclk;
}
@@ -879,9 +886,6 @@
divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
- debug("PLL%d : cfgr1=%x fracr=%x DIVN=%d DIVM=%d\n",
- pll_id, cfgr1, fracr, divn, divm);
-
refclk = pll_get_fref_ck(priv, pll_id);
/* with FRACV :
@@ -898,7 +902,6 @@
} else {
fvco = (ulong)(refclk * (divn + 1) / (divm + 1));
}
- debug("PLL%d : %s = %ld\n", pll_id, __func__, fvco);
return fvco;
}
@@ -911,17 +914,13 @@
ulong dfout;
u32 cfgr2;
- debug("%s(%d, %d)\n", __func__, pll_id, div_id);
if (div_id >= _DIV_NB)
return 0;
cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
divy = (cfgr2 >> RCC_PLLNCFGR2_SHIFT(div_id)) & RCC_PLLNCFGR2_DIVX_MASK;
- debug("PLL%d : cfgr2=%x DIVY=%d\n", pll_id, cfgr2, divy);
-
dfout = pll_get_fvco(priv, pll_id) / (divy + 1);
- debug(" => dfout = %d kHz\n", (u32)(dfout / 1000));
return dfout;
}
@@ -1542,8 +1541,7 @@
u32 stgenc, cntfid0;
ulong rate;
- stgenc = (u32)syscon_get_first_range(STM32MP_SYSCON_STGEN);
-
+ stgenc = STM32_STGEN_BASE;
cntfid0 = readl(stgenc + STGENC_CNTFID0);
p = stm32mp1_clk_get_parent(priv, STGEN_K);
rate = stm32mp1_clk_get(priv, p);
@@ -1565,9 +1563,6 @@
/* need to update gd->arch.timer_rate_hz with new frequency */
timer_init();
- pr_debug("gd->arch.timer_rate_hz = %x\n",
- (u32)gd->arch.timer_rate_hz);
- pr_debug("Tick = %x\n", (u32)(get_ticks()));
}
}
@@ -1873,7 +1868,6 @@
if (div > 128)
div = 128;
- debug("fvco = %ld, clk_rate = %ld, div=%d\n", fvco, clk_rate, div);
/* stop the requested output */
clrbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
/* change divider */
@@ -1906,6 +1900,9 @@
}
p = stm32mp1_clk_get_parent(priv, clk->id);
+#ifdef DEBUG
+ debug("%s: parent = %d:%s\n", __func__, p, stm32mp1_clk_parent_name[p]);
+#endif
if (p < 0)
return -EINVAL;
@@ -1923,6 +1920,7 @@
return result;
}
#endif
+
case _PLL4_Q:
/* for LTDC_PX and DSI_PX case */
return pll_set_output_rate(clk->dev, _PLL4, _DIV_Q, clk_rate);
@@ -2046,22 +2044,22 @@
stm32mp1_clk_dump(priv);
#endif
+ gd->cpu_clk = stm32mp1_clk_get(priv, _CK_MPU);
+ gd->bus_clk = stm32mp1_clk_get(priv, _ACLK);
+ /* DDRPHYC father */
+ gd->mem_clk = stm32mp1_clk_get(priv, _PLL2_R);
#if defined(CONFIG_DISPLAY_CPUINFO)
if (gd->flags & GD_FLG_RELOC) {
char buf[32];
printf("Clocks:\n");
- printf("- MPU : %s MHz\n",
- strmhz(buf, stm32mp1_clk_get(priv, _CK_MPU)));
+ printf("- MPU : %s MHz\n", strmhz(buf, gd->cpu_clk));
printf("- MCU : %s MHz\n",
strmhz(buf, stm32mp1_clk_get(priv, _CK_MCU)));
- printf("- AXI : %s MHz\n",
- strmhz(buf, stm32mp1_clk_get(priv, _ACLK)));
+ printf("- AXI : %s MHz\n", strmhz(buf, gd->bus_clk));
printf("- PER : %s MHz\n",
strmhz(buf, stm32mp1_clk_get(priv, _CK_PER)));
- /* DDRPHYC father */
- printf("- DDR : %s MHz\n",
- strmhz(buf, stm32mp1_clk_get(priv, _PLL2_R)));
+ printf("- DDR : %s MHz\n", strmhz(buf, gd->mem_clk));
}
#endif /* CONFIG_DISPLAY_CPUINFO */
#endif
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index a6fb58d..aae69cf 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -1,6 +1,38 @@
+config SPL_CLK_IMX6Q
+ bool "SPL clock support for i.MX6Q"
+ depends on ARCH_MX6 && SPL
+ select SPL_CLK
+ select SPL_CLK_CCF
+ help
+ This enables SPL DM/DTS support for clock driver in i.MX6Q platforms.
+
+config CLK_IMX6Q
+ bool "Clock support for i.MX6Q"
+ depends on ARCH_MX6
+ select CLK
+ select CLK_CCF
+ help
+ This enables DM/DTS support for clock driver in i.MX6Q platforms.
+
config CLK_IMX8
bool "Clock support for i.MX8"
depends on ARCH_IMX8
select CLK
help
This enables support clock driver for i.MX8 platforms.
+
+config SPL_CLK_IMX8MM
+ bool "SPL clock support for i.MX8MM"
+ depends on ARCH_IMX8M && SPL
+ select SPL_CLK
+ select SPL_CLK_CCF
+ help
+ This enables SPL DM/DTS support for clock driver in i.MX8MM
+
+config CLK_IMX8MM
+ bool "Clock support for i.MX8MM"
+ depends on ARCH_IMX8M
+ select CLK
+ select CLK_CCF
+ help
+ This enables support clock driver for i.MX8MM platforms.
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index eb379c1..5ad7967 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -2,9 +2,13 @@
#
# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk-gate2.o clk-pllv3.o clk-pfd.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_IMX6Q) += clk-imx6q.o
obj-$(CONFIG_CLK_IMX8) += clk-imx8.o
ifdef CONFIG_CLK_IMX8
obj-$(CONFIG_IMX8QXP) += clk-imx8qxp.o
obj-$(CONFIG_IMX8QM) += clk-imx8qm.o
endif
+obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MM) += clk-imx8mm.o clk-pll14xx.o \
+ clk-composite-8m.o
diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c
new file mode 100644
index 0000000..95120d6
--- /dev/null
+++ b/drivers/clk/imx/clk-composite-8m.c
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <clk-uclass.h>
+#include <dm/device.h>
+#include <linux/clk-provider.h>
+#include <clk.h>
+#include "clk.h"
+
+#define UBOOT_DM_CLK_IMX_COMPOSITE "imx_clk_composite"
+
+#define PCG_PREDIV_SHIFT 16
+#define PCG_PREDIV_WIDTH 3
+#define PCG_PREDIV_MAX 8
+
+#define PCG_DIV_SHIFT 0
+#define PCG_DIV_WIDTH 6
+#define PCG_DIV_MAX 64
+
+#define PCG_PCS_SHIFT 24
+#define PCG_PCS_MASK 0x7
+
+#define PCG_CGC_SHIFT 28
+
+static unsigned long imx8m_clk_composite_divider_recalc_rate(struct clk *clk)
+{
+ struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk);
+ struct clk_composite *composite = (struct clk_composite *)clk->data;
+ ulong parent_rate = clk_get_parent_rate(&composite->clk);
+ unsigned long prediv_rate;
+ unsigned int prediv_value;
+ unsigned int div_value;
+
+ debug("%s: name %s prate: %lu reg: %p\n", __func__,
+ (&composite->clk)->dev->name, parent_rate, divider->reg);
+ prediv_value = readl(divider->reg) >> divider->shift;
+ prediv_value &= clk_div_mask(divider->width);
+
+ prediv_rate = divider_recalc_rate(clk, parent_rate, prediv_value,
+ NULL, divider->flags,
+ divider->width);
+
+ div_value = readl(divider->reg) >> PCG_DIV_SHIFT;
+ div_value &= clk_div_mask(PCG_DIV_WIDTH);
+
+ return divider_recalc_rate(clk, prediv_rate, div_value, NULL,
+ divider->flags, PCG_DIV_WIDTH);
+}
+
+static int imx8m_clk_composite_compute_dividers(unsigned long rate,
+ unsigned long parent_rate,
+ int *prediv, int *postdiv)
+{
+ int div1, div2;
+ int error = INT_MAX;
+ int ret = -EINVAL;
+
+ *prediv = 1;
+ *postdiv = 1;
+
+ for (div1 = 1; div1 <= PCG_PREDIV_MAX; div1++) {
+ for (div2 = 1; div2 <= PCG_DIV_MAX; div2++) {
+ int new_error = ((parent_rate / div1) / div2) - rate;
+
+ if (abs(new_error) < abs(error)) {
+ *prediv = div1;
+ *postdiv = div2;
+ error = new_error;
+ ret = 0;
+ }
+ }
+ }
+ return ret;
+}
+
+/*
+ * The clk are bound to a dev, because it is part of composite clk
+ * use composite clk to get dev
+ */
+static ulong imx8m_clk_composite_divider_set_rate(struct clk *clk,
+ unsigned long rate)
+{
+ struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk);
+ struct clk_composite *composite = (struct clk_composite *)clk->data;
+ ulong parent_rate = clk_get_parent_rate(&composite->clk);
+ int prediv_value;
+ int div_value;
+ int ret;
+ u32 val;
+
+ ret = imx8m_clk_composite_compute_dividers(rate, parent_rate,
+ &prediv_value, &div_value);
+ if (ret)
+ return ret;
+
+ val = readl(divider->reg);
+ val &= ~((clk_div_mask(divider->width) << divider->shift) |
+ (clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT));
+
+ val |= (u32)(prediv_value - 1) << divider->shift;
+ val |= (u32)(div_value - 1) << PCG_DIV_SHIFT;
+ writel(val, divider->reg);
+
+ return clk_get_rate(&composite->clk);
+}
+
+static const struct clk_ops imx8m_clk_composite_divider_ops = {
+ .get_rate = imx8m_clk_composite_divider_recalc_rate,
+ .set_rate = imx8m_clk_composite_divider_set_rate,
+};
+
+struct clk *imx8m_clk_composite_flags(const char *name,
+ const char * const *parent_names,
+ int num_parents, void __iomem *reg,
+ unsigned long flags)
+{
+ struct clk *clk = ERR_PTR(-ENOMEM);
+ struct clk_divider *div = NULL;
+ struct clk_gate *gate = NULL;
+ struct clk_mux *mux = NULL;
+
+ mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+ if (!mux)
+ goto fail;
+
+ mux->reg = reg;
+ mux->shift = PCG_PCS_SHIFT;
+ mux->mask = PCG_PCS_MASK;
+ mux->num_parents = num_parents;
+ mux->flags = flags;
+ mux->parent_names = parent_names;
+
+ div = kzalloc(sizeof(*div), GFP_KERNEL);
+ if (!div)
+ goto fail;
+
+ div->reg = reg;
+ div->shift = PCG_PREDIV_SHIFT;
+ div->width = PCG_PREDIV_WIDTH;
+ div->flags = CLK_DIVIDER_ROUND_CLOSEST | flags;
+
+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+ if (!gate)
+ goto fail;
+
+ gate->reg = reg;
+ gate->bit_idx = PCG_CGC_SHIFT;
+ gate->flags = flags;
+
+ clk = clk_register_composite(NULL, name,
+ parent_names, num_parents,
+ &mux->clk, &clk_mux_ops, &div->clk,
+ &imx8m_clk_composite_divider_ops,
+ &gate->clk, &clk_gate_ops, flags);
+ if (IS_ERR(clk))
+ goto fail;
+
+ return clk;
+
+fail:
+ kfree(gate);
+ kfree(div);
+ kfree(mux);
+ return ERR_CAST(clk);
+}
diff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c
new file mode 100644
index 0000000..1b9db6e
--- /dev/null
+++ b/drivers/clk/imx/clk-gate2.c
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
+ * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Gated clock implementation
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <clk-uclass.h>
+#include <dm/device.h>
+#include <linux/clk-provider.h>
+#include <clk.h>
+#include "clk.h"
+
+#define UBOOT_DM_CLK_IMX_GATE2 "imx_clk_gate2"
+
+struct clk_gate2 {
+ struct clk clk;
+ void __iomem *reg;
+ u8 bit_idx;
+ u8 cgr_val;
+ u8 flags;
+};
+
+#define to_clk_gate2(_clk) container_of(_clk, struct clk_gate2, clk)
+
+static int clk_gate2_enable(struct clk *clk)
+{
+ struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev));
+ u32 reg;
+
+ reg = readl(gate->reg);
+ reg &= ~(3 << gate->bit_idx);
+ reg |= gate->cgr_val << gate->bit_idx;
+ writel(reg, gate->reg);
+
+ return 0;
+}
+
+static int clk_gate2_disable(struct clk *clk)
+{
+ struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev));
+ u32 reg;
+
+ reg = readl(gate->reg);
+ reg &= ~(3 << gate->bit_idx);
+ writel(reg, gate->reg);
+
+ return 0;
+}
+
+static ulong clk_gate2_set_rate(struct clk *clk, ulong rate)
+{
+ struct clk *parent = clk_get_parent(clk);
+
+ if (parent)
+ return clk_set_rate(parent, rate);
+
+ return -ENODEV;
+}
+
+static const struct clk_ops clk_gate2_ops = {
+ .set_rate = clk_gate2_set_rate,
+ .enable = clk_gate2_enable,
+ .disable = clk_gate2_disable,
+ .get_rate = clk_generic_get_rate,
+};
+
+struct clk *clk_register_gate2(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ void __iomem *reg, u8 bit_idx, u8 cgr_val,
+ u8 clk_gate2_flags)
+{
+ struct clk_gate2 *gate;
+ struct clk *clk;
+ int ret;
+
+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+ if (!gate)
+ return ERR_PTR(-ENOMEM);
+
+ gate->reg = reg;
+ gate->bit_idx = bit_idx;
+ gate->cgr_val = cgr_val;
+ gate->flags = clk_gate2_flags;
+
+ clk = &gate->clk;
+
+ ret = clk_register(clk, UBOOT_DM_CLK_IMX_GATE2, name, parent_name);
+ if (ret) {
+ kfree(gate);
+ return ERR_PTR(ret);
+ }
+
+ return clk;
+}
+
+U_BOOT_DRIVER(clk_gate2) = {
+ .name = UBOOT_DM_CLK_IMX_GATE2,
+ .id = UCLASS_CLK,
+ .ops = &clk_gate2_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
new file mode 100644
index 0000000..92e9337
--- /dev/null
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -0,0 +1,179 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <dt-bindings/clock/imx6qdl-clock.h>
+
+#include "clk.h"
+
+static int imx6q_check_id(ulong id)
+{
+ if (id < IMX6QDL_CLK_DUMMY || id >= IMX6QDL_CLK_END) {
+ printf("%s: Invalid clk ID #%lu\n", __func__, id);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static ulong imx6q_clk_get_rate(struct clk *clk)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu)\n", __func__, clk->id);
+
+ ret = imx6q_check_id(clk->id);
+ if (ret)
+ return ret;
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ return clk_get_rate(c);
+}
+
+static ulong imx6q_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
+
+ return rate;
+}
+
+static int __imx6q_clk_enable(struct clk *clk, bool enable)
+{
+ struct clk *c;
+ int ret = 0;
+
+ debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
+
+ ret = imx6q_check_id(clk->id);
+ if (ret)
+ return ret;
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ if (enable)
+ ret = clk_enable(c);
+ else
+ ret = clk_disable(c);
+
+ return ret;
+}
+
+static int imx6q_clk_disable(struct clk *clk)
+{
+ return __imx6q_clk_enable(clk, 0);
+}
+
+static int imx6q_clk_enable(struct clk *clk)
+{
+ return __imx6q_clk_enable(clk, 1);
+}
+
+static struct clk_ops imx6q_clk_ops = {
+ .set_rate = imx6q_clk_set_rate,
+ .get_rate = imx6q_clk_get_rate,
+ .enable = imx6q_clk_enable,
+ .disable = imx6q_clk_disable,
+};
+
+static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
+
+static int imx6q_clk_probe(struct udevice *dev)
+{
+ void *base;
+
+ /* Anatop clocks */
+ base = (void *)ANATOP_BASE_ADDR;
+
+ clk_dm(IMX6QDL_CLK_PLL2,
+ imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc",
+ base + 0x30, 0x1));
+ clk_dm(IMX6QDL_CLK_PLL3_USB_OTG,
+ imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc",
+ base + 0x10, 0x3));
+ clk_dm(IMX6QDL_CLK_PLL3_60M,
+ imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8));
+ clk_dm(IMX6QDL_CLK_PLL2_PFD0_352M,
+ imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0));
+ clk_dm(IMX6QDL_CLK_PLL2_PFD2_396M,
+ imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2));
+
+ /* CCM clocks */
+ base = dev_read_addr_ptr(dev);
+ if (base == (void *)FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ clk_dm(IMX6QDL_CLK_USDHC1_SEL,
+ imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1,
+ usdhc_sels, ARRAY_SIZE(usdhc_sels)));
+ clk_dm(IMX6QDL_CLK_USDHC2_SEL,
+ imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1,
+ usdhc_sels, ARRAY_SIZE(usdhc_sels)));
+ clk_dm(IMX6QDL_CLK_USDHC3_SEL,
+ imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1,
+ usdhc_sels, ARRAY_SIZE(usdhc_sels)));
+ clk_dm(IMX6QDL_CLK_USDHC4_SEL,
+ imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1,
+ usdhc_sels, ARRAY_SIZE(usdhc_sels)));
+
+ clk_dm(IMX6QDL_CLK_USDHC1_PODF,
+ imx_clk_divider("usdhc1_podf", "usdhc1_sel",
+ base + 0x24, 11, 3));
+ clk_dm(IMX6QDL_CLK_USDHC2_PODF,
+ imx_clk_divider("usdhc2_podf", "usdhc2_sel",
+ base + 0x24, 16, 3));
+ clk_dm(IMX6QDL_CLK_USDHC3_PODF,
+ imx_clk_divider("usdhc3_podf", "usdhc3_sel",
+ base + 0x24, 19, 3));
+ clk_dm(IMX6QDL_CLK_USDHC4_PODF,
+ imx_clk_divider("usdhc4_podf", "usdhc4_sel",
+ base + 0x24, 22, 3));
+
+ clk_dm(IMX6QDL_CLK_ECSPI_ROOT,
+ imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6));
+
+ clk_dm(IMX6QDL_CLK_ECSPI1,
+ imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0));
+ clk_dm(IMX6QDL_CLK_ECSPI2,
+ imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2));
+ clk_dm(IMX6QDL_CLK_ECSPI3,
+ imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4));
+ clk_dm(IMX6QDL_CLK_ECSPI4,
+ imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6));
+ clk_dm(IMX6QDL_CLK_USDHC1,
+ imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2));
+ clk_dm(IMX6QDL_CLK_USDHC2,
+ imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4));
+ clk_dm(IMX6QDL_CLK_USDHC3,
+ imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6));
+ clk_dm(IMX6QDL_CLK_USDHC4,
+ imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8));
+
+ return 0;
+}
+
+static const struct udevice_id imx6q_clk_ids[] = {
+ { .compatible = "fsl,imx6q-ccm" },
+ { },
+};
+
+U_BOOT_DRIVER(imx6q_clk) = {
+ .name = "clk_imx6q",
+ .id = UCLASS_CLK,
+ .of_match = imx6q_clk_ids,
+ .ops = &imx6q_clk_ops,
+ .probe = imx6q_clk_probe,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
new file mode 100644
index 0000000..f4913e7
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -0,0 +1,415 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 NXP
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <dt-bindings/clock/imx8mm-clock.h>
+
+#include "clk.h"
+
+#define PLL_1416X_RATE(_rate, _m, _p, _s) \
+ { \
+ .rate = (_rate), \
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ }
+
+#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
+ { \
+ .rate = (_rate), \
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ .kdiv = (_k), \
+ }
+
+static const struct imx_pll14xx_rate_table imx8mm_pll1416x_tbl[] = {
+ PLL_1416X_RATE(1800000000U, 225, 3, 0),
+ PLL_1416X_RATE(1600000000U, 200, 3, 0),
+ PLL_1416X_RATE(1200000000U, 300, 3, 1),
+ PLL_1416X_RATE(1000000000U, 250, 3, 1),
+ PLL_1416X_RATE(800000000U, 200, 3, 1),
+ PLL_1416X_RATE(750000000U, 250, 2, 2),
+ PLL_1416X_RATE(700000000U, 350, 3, 2),
+ PLL_1416X_RATE(600000000U, 300, 3, 2),
+};
+
+static const struct imx_pll14xx_rate_table imx8mm_drampll_tbl[] = {
+ PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
+};
+
+static struct imx_pll14xx_clk imx8mm_dram_pll __initdata = {
+ .type = PLL_1443X,
+ .rate_table = imx8mm_drampll_tbl,
+ .rate_count = ARRAY_SIZE(imx8mm_drampll_tbl),
+};
+
+static struct imx_pll14xx_clk imx8mm_arm_pll __initdata = {
+ .type = PLL_1416X,
+ .rate_table = imx8mm_pll1416x_tbl,
+ .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
+};
+
+static struct imx_pll14xx_clk imx8mm_sys_pll __initdata = {
+ .type = PLL_1416X,
+ .rate_table = imx8mm_pll1416x_tbl,
+ .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
+};
+
+static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
+static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
+static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
+static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
+static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
+static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
+
+static const char *imx8mm_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m",
+ "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", };
+
+static const char *imx8mm_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m",
+ "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", };
+
+static const char *imx8mm_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m",
+ "sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", };
+
+static const char *imx8mm_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
+ "sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", };
+
+static const char *imx8mm_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
+ "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
+
+static const char *imx8mm_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
+ "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
+
+static const char *imx8mm_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
+ "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
+
+static const char *imx8mm_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
+ "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
+
+static const char *imx8mm_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
+ "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
+
+static const char *imx8mm_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
+ "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
+
+static const char *imx8mm_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out",
+ "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", };
+
+static const char *imx8mm_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
+ "sys_pll3_out", "sys_pll1_266m", "audio_pll2_clk", "sys_pll1_100m", };
+
+static ulong imx8mm_clk_get_rate(struct clk *clk)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu)\n", __func__, clk->id);
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ return clk_get_rate(c);
+}
+
+static ulong imx8mm_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ return clk_set_rate(c, rate);
+}
+
+static int __imx8mm_clk_enable(struct clk *clk, bool enable)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ if (enable)
+ ret = clk_enable(c);
+ else
+ ret = clk_disable(c);
+
+ return ret;
+}
+
+static int imx8mm_clk_disable(struct clk *clk)
+{
+ return __imx8mm_clk_enable(clk, 0);
+}
+
+static int imx8mm_clk_enable(struct clk *clk)
+{
+ return __imx8mm_clk_enable(clk, 1);
+}
+
+static struct clk_ops imx8mm_clk_ops = {
+ .set_rate = imx8mm_clk_set_rate,
+ .get_rate = imx8mm_clk_get_rate,
+ .enable = imx8mm_clk_enable,
+ .disable = imx8mm_clk_disable,
+};
+
+static int imx8mm_clk_probe(struct udevice *dev)
+{
+ void __iomem *base;
+
+ base = (void *)ANATOP_BASE_ADDR;
+
+ clk_dm(IMX8MM_DRAM_PLL_REF_SEL,
+ imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+ clk_dm(IMX8MM_ARM_PLL_REF_SEL,
+ imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+ clk_dm(IMX8MM_SYS_PLL1_REF_SEL,
+ imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+ clk_dm(IMX8MM_SYS_PLL2_REF_SEL,
+ imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+ clk_dm(IMX8MM_SYS_PLL3_REF_SEL,
+ imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+
+ clk_dm(IMX8MM_DRAM_PLL,
+ imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel",
+ base + 0x50, &imx8mm_dram_pll));
+ clk_dm(IMX8MM_ARM_PLL,
+ imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel",
+ base + 0x84, &imx8mm_arm_pll));
+ clk_dm(IMX8MM_SYS_PLL1,
+ imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel",
+ base + 0x94, &imx8mm_sys_pll));
+ clk_dm(IMX8MM_SYS_PLL2,
+ imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel",
+ base + 0x104, &imx8mm_sys_pll));
+ clk_dm(IMX8MM_SYS_PLL3,
+ imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel",
+ base + 0x114, &imx8mm_sys_pll));
+
+ /* PLL bypass out */
+ clk_dm(IMX8MM_DRAM_PLL_BYPASS,
+ imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1,
+ dram_pll_bypass_sels,
+ ARRAY_SIZE(dram_pll_bypass_sels),
+ CLK_SET_RATE_PARENT));
+ clk_dm(IMX8MM_ARM_PLL_BYPASS,
+ imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1,
+ arm_pll_bypass_sels,
+ ARRAY_SIZE(arm_pll_bypass_sels),
+ CLK_SET_RATE_PARENT));
+ clk_dm(IMX8MM_SYS_PLL1_BYPASS,
+ imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1,
+ sys_pll1_bypass_sels,
+ ARRAY_SIZE(sys_pll1_bypass_sels),
+ CLK_SET_RATE_PARENT));
+ clk_dm(IMX8MM_SYS_PLL2_BYPASS,
+ imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1,
+ sys_pll2_bypass_sels,
+ ARRAY_SIZE(sys_pll2_bypass_sels),
+ CLK_SET_RATE_PARENT));
+ clk_dm(IMX8MM_SYS_PLL3_BYPASS,
+ imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1,
+ sys_pll3_bypass_sels,
+ ARRAY_SIZE(sys_pll3_bypass_sels),
+ CLK_SET_RATE_PARENT));
+
+ /* PLL out gate */
+ clk_dm(IMX8MM_DRAM_PLL_OUT,
+ imx_clk_gate("dram_pll_out", "dram_pll_bypass",
+ base + 0x50, 13));
+ clk_dm(IMX8MM_ARM_PLL_OUT,
+ imx_clk_gate("arm_pll_out", "arm_pll_bypass",
+ base + 0x84, 11));
+ clk_dm(IMX8MM_SYS_PLL1_OUT,
+ imx_clk_gate("sys_pll1_out", "sys_pll1_bypass",
+ base + 0x94, 11));
+ clk_dm(IMX8MM_SYS_PLL2_OUT,
+ imx_clk_gate("sys_pll2_out", "sys_pll2_bypass",
+ base + 0x104, 11));
+ clk_dm(IMX8MM_SYS_PLL3_OUT,
+ imx_clk_gate("sys_pll3_out", "sys_pll3_bypass",
+ base + 0x114, 11));
+
+ /* SYS PLL fixed output */
+ clk_dm(IMX8MM_SYS_PLL1_40M,
+ imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20));
+ clk_dm(IMX8MM_SYS_PLL1_80M,
+ imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10));
+ clk_dm(IMX8MM_SYS_PLL1_100M,
+ imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8));
+ clk_dm(IMX8MM_SYS_PLL1_133M,
+ imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6));
+ clk_dm(IMX8MM_SYS_PLL1_160M,
+ imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5));
+ clk_dm(IMX8MM_SYS_PLL1_200M,
+ imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4));
+ clk_dm(IMX8MM_SYS_PLL1_266M,
+ imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3));
+ clk_dm(IMX8MM_SYS_PLL1_400M,
+ imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2));
+ clk_dm(IMX8MM_SYS_PLL1_800M,
+ imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1));
+
+ clk_dm(IMX8MM_SYS_PLL2_50M,
+ imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20));
+ clk_dm(IMX8MM_SYS_PLL2_100M,
+ imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10));
+ clk_dm(IMX8MM_SYS_PLL2_125M,
+ imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8));
+ clk_dm(IMX8MM_SYS_PLL2_166M,
+ imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6));
+ clk_dm(IMX8MM_SYS_PLL2_200M,
+ imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5));
+ clk_dm(IMX8MM_SYS_PLL2_250M,
+ imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4));
+ clk_dm(IMX8MM_SYS_PLL2_333M,
+ imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3));
+ clk_dm(IMX8MM_SYS_PLL2_500M,
+ imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
+ clk_dm(IMX8MM_SYS_PLL2_1000M,
+ imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
+
+ base = dev_read_addr_ptr(dev);
+ if (base == (void *)FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ clk_dm(IMX8MM_CLK_A53_SRC,
+ imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3,
+ imx8mm_a53_sels, ARRAY_SIZE(imx8mm_a53_sels)));
+ clk_dm(IMX8MM_CLK_A53_CG,
+ imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
+ clk_dm(IMX8MM_CLK_A53_DIV,
+ imx_clk_divider2("arm_a53_div", "arm_a53_cg",
+ base + 0x8000, 0, 3));
+
+ clk_dm(IMX8MM_CLK_AHB,
+ imx8m_clk_composite_critical("ahb", imx8mm_ahb_sels,
+ base + 0x9000));
+ clk_dm(IMX8MM_CLK_IPG_ROOT,
+ imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1));
+
+ clk_dm(IMX8MM_CLK_ENET_AXI,
+ imx8m_clk_composite("enet_axi", imx8mm_enet_axi_sels,
+ base + 0x8880));
+ clk_dm(IMX8MM_CLK_NAND_USDHC_BUS,
+ imx8m_clk_composite_critical("nand_usdhc_bus",
+ imx8mm_nand_usdhc_sels,
+ base + 0x8900));
+
+ /* IP */
+ clk_dm(IMX8MM_CLK_USDHC1,
+ imx8m_clk_composite("usdhc1", imx8mm_usdhc1_sels,
+ base + 0xac00));
+ clk_dm(IMX8MM_CLK_USDHC2,
+ imx8m_clk_composite("usdhc2", imx8mm_usdhc2_sels,
+ base + 0xac80));
+ clk_dm(IMX8MM_CLK_I2C1,
+ imx8m_clk_composite("i2c1", imx8mm_i2c1_sels, base + 0xad00));
+ clk_dm(IMX8MM_CLK_I2C2,
+ imx8m_clk_composite("i2c2", imx8mm_i2c2_sels, base + 0xad80));
+ clk_dm(IMX8MM_CLK_I2C3,
+ imx8m_clk_composite("i2c3", imx8mm_i2c3_sels, base + 0xae00));
+ clk_dm(IMX8MM_CLK_I2C4,
+ imx8m_clk_composite("i2c4", imx8mm_i2c4_sels, base + 0xae80));
+ clk_dm(IMX8MM_CLK_WDOG,
+ imx8m_clk_composite("wdog", imx8mm_wdog_sels, base + 0xb900));
+ clk_dm(IMX8MM_CLK_USDHC3,
+ imx8m_clk_composite("usdhc3", imx8mm_usdhc3_sels,
+ base + 0xbc80));
+
+ clk_dm(IMX8MM_CLK_I2C1_ROOT,
+ imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
+ clk_dm(IMX8MM_CLK_I2C2_ROOT,
+ imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
+ clk_dm(IMX8MM_CLK_I2C3_ROOT,
+ imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
+ clk_dm(IMX8MM_CLK_I2C4_ROOT,
+ imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
+ clk_dm(IMX8MM_CLK_OCOTP_ROOT,
+ imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
+ clk_dm(IMX8MM_CLK_USDHC1_ROOT,
+ imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
+ clk_dm(IMX8MM_CLK_USDHC2_ROOT,
+ imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
+ clk_dm(IMX8MM_CLK_WDOG1_ROOT,
+ imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
+ clk_dm(IMX8MM_CLK_WDOG2_ROOT,
+ imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
+ clk_dm(IMX8MM_CLK_WDOG3_ROOT,
+ imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
+ clk_dm(IMX8MM_CLK_USDHC3_ROOT,
+ imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
+
+#ifdef CONFIG_SPL_BUILD
+ struct clk *clkp, *clkp1;
+
+ clk_get_by_id(IMX8MM_CLK_WDOG1_ROOT, &clkp);
+ clk_enable(clkp);
+ clk_get_by_id(IMX8MM_CLK_WDOG2_ROOT, &clkp);
+ clk_enable(clkp);
+ clk_get_by_id(IMX8MM_CLK_WDOG3_ROOT, &clkp);
+ clk_enable(clkp);
+
+ /* Configure SYS_PLL3 to 750MHz */
+ clk_get_by_id(IMX8MM_SYS_PLL3, &clkp);
+ clk_set_rate(clkp, 750000000UL);
+ clk_enable(clkp);
+
+ /* Configure ARM to sys_pll2_500m */
+ clk_get_by_id(IMX8MM_CLK_A53_SRC, &clkp);
+ clk_get_by_id(IMX8MM_SYS_PLL2_OUT, &clkp1);
+ clk_enable(clkp1);
+ clk_get_by_id(IMX8MM_SYS_PLL2_500M, &clkp1);
+ clk_set_parent(clkp, clkp1);
+
+ /* Configure ARM PLL to 1.2GHz */
+ clk_get_by_id(IMX8MM_ARM_PLL, &clkp1);
+ clk_set_rate(clkp1, 1200000000UL);
+ clk_get_by_id(IMX8MM_ARM_PLL_OUT, &clkp1);
+ clk_enable(clkp1);
+ clk_set_parent(clkp, clkp1);
+
+ /* Configure DIV to 1.2GHz */
+ clk_get_by_id(IMX8MM_CLK_A53_DIV, &clkp1);
+ clk_set_rate(clkp1, 1200000000UL);
+#endif
+
+ return 0;
+}
+
+static const struct udevice_id imx8mm_clk_ids[] = {
+ { .compatible = "fsl,imx8mm-ccm" },
+ { },
+};
+
+U_BOOT_DRIVER(imx8mm_clk) = {
+ .name = "clk_imx8mm",
+ .id = UCLASS_CLK,
+ .of_match = imx8mm_clk_ids,
+ .ops = &imx8mm_clk_ops,
+ .probe = imx8mm_clk_probe,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/imx/clk-pfd.c b/drivers/clk/imx/clk-pfd.c
new file mode 100644
index 0000000..188b2b3
--- /dev/null
+++ b/drivers/clk/imx/clk-pfd.c
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2012 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <clk-uclass.h>
+#include <dm/device.h>
+#include <linux/clk-provider.h>
+#include <div64.h>
+#include <clk.h>
+#include "clk.h"
+
+#define UBOOT_DM_CLK_IMX_PFD "imx_clk_pfd"
+
+struct clk_pfd {
+ struct clk clk;
+ void __iomem *reg;
+ u8 idx;
+};
+
+#define to_clk_pfd(_clk) container_of(_clk, struct clk_pfd, clk)
+
+#define SET 0x4
+#define CLR 0x8
+#define OTG 0xc
+
+static unsigned long clk_pfd_recalc_rate(struct clk *clk)
+{
+ struct clk_pfd *pfd =
+ to_clk_pfd(dev_get_clk_ptr(clk->dev));
+ unsigned long parent_rate = clk_get_parent_rate(clk);
+ u64 tmp = parent_rate;
+ u8 frac = (readl(pfd->reg) >> (pfd->idx * 8)) & 0x3f;
+
+ tmp *= 18;
+ do_div(tmp, frac);
+
+ return tmp;
+}
+
+static const struct clk_ops clk_pfd_ops = {
+ .get_rate = clk_pfd_recalc_rate,
+};
+
+struct clk *imx_clk_pfd(const char *name, const char *parent_name,
+ void __iomem *reg, u8 idx)
+{
+ struct clk_pfd *pfd;
+ struct clk *clk;
+ int ret;
+
+ pfd = kzalloc(sizeof(*pfd), GFP_KERNEL);
+ if (!pfd)
+ return ERR_PTR(-ENOMEM);
+
+ pfd->reg = reg;
+ pfd->idx = idx;
+
+ /* register the clock */
+ clk = &pfd->clk;
+
+ ret = clk_register(clk, UBOOT_DM_CLK_IMX_PFD, name, parent_name);
+ if (ret) {
+ kfree(pfd);
+ return ERR_PTR(ret);
+ }
+
+ return clk;
+}
+
+U_BOOT_DRIVER(clk_pfd) = {
+ .name = UBOOT_DM_CLK_IMX_PFD,
+ .id = UCLASS_CLK,
+ .ops = &clk_pfd_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c
new file mode 100644
index 0000000..2246beb
--- /dev/null
+++ b/drivers/clk/imx/clk-pll14xx.c
@@ -0,0 +1,381 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2017-2019 NXP.
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <clk-uclass.h>
+#include <dm/device.h>
+#include <linux/clk-provider.h>
+#include <linux/iopoll.h>
+#include <clk.h>
+#include <div64.h>
+
+#include "clk.h"
+
+#define UBOOT_DM_CLK_IMX_PLL1443X "imx_clk_pll1443x"
+#define UBOOT_DM_CLK_IMX_PLL1416X "imx_clk_pll1416x"
+
+#define GNRL_CTL 0x0
+#define DIV_CTL 0x4
+#define LOCK_STATUS BIT(31)
+#define LOCK_SEL_MASK BIT(29)
+#define CLKE_MASK BIT(11)
+#define RST_MASK BIT(9)
+#define BYPASS_MASK BIT(4)
+#define MDIV_SHIFT 12
+#define MDIV_MASK GENMASK(21, 12)
+#define PDIV_SHIFT 4
+#define PDIV_MASK GENMASK(9, 4)
+#define SDIV_SHIFT 0
+#define SDIV_MASK GENMASK(2, 0)
+#define KDIV_SHIFT 0
+#define KDIV_MASK GENMASK(15, 0)
+
+#define LOCK_TIMEOUT_US 10000
+
+struct clk_pll14xx {
+ struct clk clk;
+ void __iomem *base;
+ enum imx_pll14xx_type type;
+ const struct imx_pll14xx_rate_table *rate_table;
+ int rate_count;
+};
+
+#define to_clk_pll14xx(_clk) container_of(_clk, struct clk_pll14xx, clk)
+
+static const struct imx_pll14xx_rate_table *imx_get_pll_settings(
+ struct clk_pll14xx *pll, unsigned long rate)
+{
+ const struct imx_pll14xx_rate_table *rate_table = pll->rate_table;
+ int i;
+
+ for (i = 0; i < pll->rate_count; i++)
+ if (rate == rate_table[i].rate)
+ return &rate_table[i];
+
+ return NULL;
+}
+
+static unsigned long clk_pll1416x_recalc_rate(struct clk *clk)
+{
+ struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
+ u64 fvco = clk_get_parent_rate(clk);
+ u32 mdiv, pdiv, sdiv, pll_div;
+
+ pll_div = readl(pll->base + 4);
+ mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
+ pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
+ sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT;
+
+ fvco *= mdiv;
+ do_div(fvco, pdiv << sdiv);
+
+ return fvco;
+}
+
+static unsigned long clk_pll1443x_recalc_rate(struct clk *clk)
+{
+ struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
+ u64 fvco = clk_get_parent_rate(clk);
+ u32 mdiv, pdiv, sdiv, pll_div_ctl0, pll_div_ctl1;
+ short int kdiv;
+
+ pll_div_ctl0 = readl(pll->base + 4);
+ pll_div_ctl1 = readl(pll->base + 8);
+ mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
+ pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
+ sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT;
+ kdiv = pll_div_ctl1 & KDIV_MASK;
+
+ /* fvco = (m * 65536 + k) * Fin / (p * 65536) */
+ fvco *= (mdiv * 65536 + kdiv);
+ pdiv *= 65536;
+
+ do_div(fvco, pdiv << sdiv);
+
+ return fvco;
+}
+
+static inline bool clk_pll1416x_mp_change(const struct imx_pll14xx_rate_table *rate,
+ u32 pll_div)
+{
+ u32 old_mdiv, old_pdiv;
+
+ old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
+ old_pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
+
+ return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv;
+}
+
+static inline bool clk_pll1443x_mpk_change(const struct imx_pll14xx_rate_table *rate,
+ u32 pll_div_ctl0, u32 pll_div_ctl1)
+{
+ u32 old_mdiv, old_pdiv, old_kdiv;
+
+ old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
+ old_pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
+ old_kdiv = (pll_div_ctl1 & KDIV_MASK) >> KDIV_SHIFT;
+
+ return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
+ rate->kdiv != old_kdiv;
+}
+
+static inline bool clk_pll1443x_mp_change(const struct imx_pll14xx_rate_table *rate,
+ u32 pll_div_ctl0, u32 pll_div_ctl1)
+{
+ u32 old_mdiv, old_pdiv, old_kdiv;
+
+ old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
+ old_pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
+ old_kdiv = (pll_div_ctl1 & KDIV_MASK) >> KDIV_SHIFT;
+
+ return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
+ rate->kdiv != old_kdiv;
+}
+
+static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll)
+{
+ u32 val;
+
+ return readl_poll_timeout(pll->base, val, val & LOCK_TIMEOUT_US,
+ LOCK_TIMEOUT_US);
+}
+
+static ulong clk_pll1416x_set_rate(struct clk *clk, unsigned long drate)
+{
+ struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
+ const struct imx_pll14xx_rate_table *rate;
+ u32 tmp, div_val;
+ int ret;
+
+ rate = imx_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+ drate, "xxxx");
+ return -EINVAL;
+ }
+
+ tmp = readl(pll->base + 4);
+
+ if (!clk_pll1416x_mp_change(rate, tmp)) {
+ tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
+ tmp |= rate->sdiv << SDIV_SHIFT;
+ writel(tmp, pll->base + 4);
+
+ return clk_pll1416x_recalc_rate(clk);
+ }
+
+ /* Bypass clock and set lock to pll output lock */
+ tmp = readl(pll->base);
+ tmp |= LOCK_SEL_MASK;
+ writel(tmp, pll->base);
+
+ /* Enable RST */
+ tmp &= ~RST_MASK;
+ writel(tmp, pll->base);
+
+ /* Enable BYPASS */
+ tmp |= BYPASS_MASK;
+ writel(tmp, pll->base);
+
+
+ div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
+ (rate->sdiv << SDIV_SHIFT);
+ writel(div_val, pll->base + 0x4);
+
+ /*
+ * According to SPEC, t3 - t2 need to be greater than
+ * 1us and 1/FREF, respectively.
+ * FREF is FIN / Prediv, the prediv is [1, 63], so choose
+ * 3us.
+ */
+ udelay(3);
+
+ /* Disable RST */
+ tmp |= RST_MASK;
+ writel(tmp, pll->base);
+
+ /* Wait Lock */
+ ret = clk_pll14xx_wait_lock(pll);
+ if (ret)
+ return ret;
+
+ /* Bypass */
+ tmp &= ~BYPASS_MASK;
+ writel(tmp, pll->base);
+
+ return clk_pll1416x_recalc_rate(clk);
+}
+
+static ulong clk_pll1443x_set_rate(struct clk *clk, unsigned long drate)
+{
+ struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
+ const struct imx_pll14xx_rate_table *rate;
+ u32 tmp, div_val;
+ int ret;
+
+ rate = imx_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+ drate, "===");
+ return -EINVAL;
+ }
+
+ tmp = readl(pll->base + 4);
+ div_val = readl(pll->base + 8);
+
+ if (!clk_pll1443x_mpk_change(rate, tmp, div_val)) {
+ tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
+ tmp |= rate->sdiv << SDIV_SHIFT;
+ writel(tmp, pll->base + 4);
+
+ return clk_pll1443x_recalc_rate(clk);
+ }
+
+ tmp = readl(pll->base);
+
+ /* Enable RST */
+ tmp &= ~RST_MASK;
+ writel(tmp, pll->base);
+
+ /* Enable BYPASS */
+ tmp |= BYPASS_MASK;
+ writel(tmp, pll->base);
+
+ div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
+ (rate->sdiv << SDIV_SHIFT);
+ writel(div_val, pll->base + 0x4);
+ writel(rate->kdiv << KDIV_SHIFT, pll->base + 0x8);
+
+ /*
+ * According to SPEC, t3 - t2 need to be greater than
+ * 1us and 1/FREF, respectively.
+ * FREF is FIN / Prediv, the prediv is [1, 63], so choose
+ * 3us.
+ */
+ udelay(3);
+
+ /* Disable RST */
+ tmp |= RST_MASK;
+ writel(tmp, pll->base);
+
+ /* Wait Lock*/
+ ret = clk_pll14xx_wait_lock(pll);
+ if (ret)
+ return ret;
+
+ /* Bypass */
+ tmp &= ~BYPASS_MASK;
+ writel(tmp, pll->base);
+
+ return clk_pll1443x_recalc_rate(clk);
+}
+
+static int clk_pll14xx_prepare(struct clk *clk)
+{
+ struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
+ u32 val;
+
+ /*
+ * RESETB = 1 from 0, PLL starts its normal
+ * operation after lock time
+ */
+ val = readl(pll->base + GNRL_CTL);
+ val |= RST_MASK;
+ writel(val, pll->base + GNRL_CTL);
+
+ return clk_pll14xx_wait_lock(pll);
+}
+
+static int clk_pll14xx_unprepare(struct clk *clk)
+{
+ struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
+ u32 val;
+
+ /*
+ * Set RST to 0, power down mode is enabled and
+ * every digital block is reset
+ */
+ val = readl(pll->base + GNRL_CTL);
+ val &= ~RST_MASK;
+ writel(val, pll->base + GNRL_CTL);
+
+ return 0;
+}
+
+static const struct clk_ops clk_pll1416x_ops = {
+ .enable = clk_pll14xx_prepare,
+ .disable = clk_pll14xx_unprepare,
+ .set_rate = clk_pll1416x_set_rate,
+ .get_rate = clk_pll1416x_recalc_rate,
+};
+
+static const struct clk_ops clk_pll1443x_ops = {
+ .enable = clk_pll14xx_prepare,
+ .disable = clk_pll14xx_unprepare,
+ .set_rate = clk_pll1443x_set_rate,
+ .get_rate = clk_pll1443x_recalc_rate,
+};
+
+struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
+ void __iomem *base,
+ const struct imx_pll14xx_clk *pll_clk)
+{
+ struct clk_pll14xx *pll;
+ struct clk *clk;
+ char *type_name;
+ int ret;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+
+ switch (pll_clk->type) {
+ case PLL_1416X:
+ type_name = UBOOT_DM_CLK_IMX_PLL1416X;
+ break;
+ case PLL_1443X:
+ type_name = UBOOT_DM_CLK_IMX_PLL1443X;
+ break;
+ default:
+ pr_err("%s: Unknown pll type for pll clk %s\n",
+ __func__, name);
+ return ERR_PTR(-EINVAL);
+ };
+
+ pll->base = base;
+ pll->type = pll_clk->type;
+ pll->rate_table = pll_clk->rate_table;
+ pll->rate_count = pll_clk->rate_count;
+
+ clk = &pll->clk;
+
+ ret = clk_register(clk, type_name, name, parent_name);
+ if (ret) {
+ pr_err("%s: failed to register pll %s %d\n",
+ __func__, name, ret);
+ kfree(pll);
+ return ERR_PTR(ret);
+ }
+
+ return clk;
+}
+
+U_BOOT_DRIVER(clk_pll1443x) = {
+ .name = UBOOT_DM_CLK_IMX_PLL1443X,
+ .id = UCLASS_CLK,
+ .ops = &clk_pll1443x_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(clk_pll1416x) = {
+ .name = UBOOT_DM_CLK_IMX_PLL1416X,
+ .id = UCLASS_CLK,
+ .ops = &clk_pll1416x_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
new file mode 100644
index 0000000..fbb7b24
--- /dev/null
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <clk-uclass.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+#include <clk.h>
+#include "clk.h"
+
+#define UBOOT_DM_CLK_IMX_PLLV3 "imx_clk_pllv3"
+
+struct clk_pllv3 {
+ struct clk clk;
+ void __iomem *base;
+ u32 div_mask;
+ u32 div_shift;
+};
+
+#define to_clk_pllv3(_clk) container_of(_clk, struct clk_pllv3, clk)
+
+static ulong clk_pllv3_get_rate(struct clk *clk)
+{
+ struct clk_pllv3 *pll = to_clk_pllv3(dev_get_clk_ptr(clk->dev));
+ unsigned long parent_rate = clk_get_parent_rate(clk);
+
+ u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask;
+
+ return (div == 1) ? parent_rate * 22 : parent_rate * 20;
+}
+
+static const struct clk_ops clk_pllv3_generic_ops = {
+ .get_rate = clk_pllv3_get_rate,
+};
+
+struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
+ const char *parent_name, void __iomem *base,
+ u32 div_mask)
+{
+ struct clk_pllv3 *pll;
+ struct clk *clk;
+ char *drv_name;
+ int ret;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+
+ switch (type) {
+ case IMX_PLLV3_GENERIC:
+ case IMX_PLLV3_USB:
+ drv_name = UBOOT_DM_CLK_IMX_PLLV3;
+ break;
+ default:
+ kfree(pll);
+ return ERR_PTR(-ENOTSUPP);
+ }
+
+ pll->base = base;
+ pll->div_mask = div_mask;
+ clk = &pll->clk;
+
+ ret = clk_register(clk, drv_name, name, parent_name);
+ if (ret) {
+ kfree(pll);
+ return ERR_PTR(ret);
+ }
+
+ return clk;
+}
+
+U_BOOT_DRIVER(clk_pllv3_generic) = {
+ .name = UBOOT_DM_CLK_IMX_PLLV3,
+ .id = UCLASS_CLK,
+ .ops = &clk_pllv3_generic_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
new file mode 100644
index 0000000..4956e04
--- /dev/null
+++ b/drivers/clk/imx/clk.h
@@ -0,0 +1,175 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ */
+#ifndef __MACH_IMX_CLK_H
+#define __MACH_IMX_CLK_H
+
+#include <linux/clk-provider.h>
+
+enum imx_pllv3_type {
+ IMX_PLLV3_GENERIC,
+ IMX_PLLV3_SYS,
+ IMX_PLLV3_USB,
+ IMX_PLLV3_USB_VF610,
+ IMX_PLLV3_AV,
+ IMX_PLLV3_ENET,
+ IMX_PLLV3_ENET_IMX7,
+ IMX_PLLV3_SYS_VF610,
+ IMX_PLLV3_DDR_IMX7,
+};
+
+enum imx_pll14xx_type {
+ PLL_1416X,
+ PLL_1443X,
+};
+
+/* NOTE: Rate table should be kept sorted in descending order. */
+struct imx_pll14xx_rate_table {
+ unsigned int rate;
+ unsigned int pdiv;
+ unsigned int mdiv;
+ unsigned int sdiv;
+ unsigned int kdiv;
+};
+
+struct imx_pll14xx_clk {
+ enum imx_pll14xx_type type;
+ const struct imx_pll14xx_rate_table *rate_table;
+ int rate_count;
+ int flags;
+};
+
+struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
+ void __iomem *base,
+ const struct imx_pll14xx_clk *pll_clk);
+
+struct clk *clk_register_gate2(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ void __iomem *reg, u8 bit_idx, u8 cgr_val,
+ u8 clk_gate_flags);
+
+struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
+ const char *parent_name, void __iomem *base,
+ u32 div_mask);
+
+static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
+ void __iomem *reg, u8 shift)
+{
+ return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
+ shift, 0x3, 0);
+}
+
+static inline struct clk *imx_clk_gate4(const char *name, const char *parent,
+ void __iomem *reg, u8 shift)
+{
+ return clk_register_gate2(NULL, name, parent,
+ CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
+ reg, shift, 0x3, 0);
+}
+
+static inline struct clk *imx_clk_gate4_flags(const char *name,
+ const char *parent, void __iomem *reg, u8 shift,
+ unsigned long flags)
+{
+ return clk_register_gate2(NULL, name, parent,
+ flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
+ reg, shift, 0x3, 0);
+}
+
+static inline struct clk *imx_clk_fixed_factor(const char *name,
+ const char *parent, unsigned int mult, unsigned int div)
+{
+ return clk_register_fixed_factor(NULL, name, parent,
+ CLK_SET_RATE_PARENT, mult, div);
+}
+
+static inline struct clk *imx_clk_divider(const char *name, const char *parent,
+ void __iomem *reg, u8 shift, u8 width)
+{
+ return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
+ reg, shift, width, 0);
+}
+
+static inline struct clk *imx_clk_divider2(const char *name, const char *parent,
+ void __iomem *reg, u8 shift, u8 width)
+{
+ return clk_register_divider(NULL, name, parent,
+ CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
+ reg, shift, width, 0);
+}
+
+struct clk *imx_clk_pfd(const char *name, const char *parent_name,
+ void __iomem *reg, u8 idx);
+
+struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
+ u8 shift, u8 width, const char * const *parents,
+ int num_parents, void (*fixup)(u32 *val));
+
+static inline struct clk *imx_clk_mux_flags(const char *name,
+ void __iomem *reg, u8 shift, u8 width,
+ const char * const *parents, int num_parents,
+ unsigned long flags)
+{
+ return clk_register_mux(NULL, name, parents, num_parents,
+ flags | CLK_SET_RATE_NO_REPARENT, reg, shift,
+ width, 0);
+}
+
+static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
+ u8 shift, u8 width, const char * const *parents,
+ int num_parents)
+{
+ return clk_register_mux(NULL, name, parents, num_parents,
+ CLK_SET_RATE_NO_REPARENT, reg, shift,
+ width, 0);
+}
+
+static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg,
+ u8 shift, u8 width, const char * const *parents,
+ int num_parents)
+{
+ return clk_register_mux(NULL, name, parents, num_parents,
+ CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
+ reg, shift, width, 0);
+}
+
+static inline struct clk *imx_clk_gate(const char *name, const char *parent,
+ void __iomem *reg, u8 shift)
+{
+ return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
+ shift, 0, NULL);
+}
+
+static inline struct clk *imx_clk_gate_flags(const char *name, const char *parent,
+ void __iomem *reg, u8 shift, unsigned long flags)
+{
+ return clk_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
+ shift, 0, NULL);
+}
+
+static inline struct clk *imx_clk_gate3(const char *name, const char *parent,
+ void __iomem *reg, u8 shift)
+{
+ return clk_register_gate(NULL, name, parent,
+ CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
+ reg, shift, 0, NULL);
+}
+
+struct clk *imx8m_clk_composite_flags(const char *name,
+ const char * const *parent_names,
+ int num_parents, void __iomem *reg, unsigned long flags);
+
+#define __imx8m_clk_composite(name, parent_names, reg, flags) \
+ imx8m_clk_composite_flags(name, parent_names, \
+ ARRAY_SIZE(parent_names), reg, \
+ flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
+
+#define imx8m_clk_composite(name, parent_names, reg) \
+ __imx8m_clk_composite(name, parent_names, reg, 0)
+
+#define imx8m_clk_composite_critical(name, parent_names, reg) \
+ __imx8m_clk_composite(name, parent_names, reg, CLK_IS_CRITICAL)
+
+#endif /* __MACH_IMX_CLK_H */
diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c
index 87ad4f7..dfce32e 100644
--- a/drivers/clk/mediatek/clk-mt7623.c
+++ b/drivers/clk/mediatek/clk-mt7623.c
@@ -691,34 +691,42 @@
GATE_PERI1(CLK_PERI_FCI, CLK_TOP_MS_CARD_SEL, 11),
};
-/* ethsys */
-static const struct mtk_gate_regs eth_cg_regs = {
+/* ethsys and hifsys */
+static const struct mtk_gate_regs eth_hif_cg_regs = {
.sta_ofs = 0x30,
};
-#define GATE_ETH(_id, _parent, _shift, _flag) { \
+#define GATE_ETH_HIF(_id, _parent, _shift, _flag) { \
.id = _id, \
.parent = _parent, \
- .regs = ð_cg_regs, \
+ .regs = ð_hif_cg_regs, \
.shift = _shift, \
.flags = CLK_GATE_NO_SETCLR_INV | (_flag), \
}
-#define GATE_ETH0(_id, _parent, _shift) \
- GATE_ETH(_id, _parent, _shift, CLK_PARENT_APMIXED)
+#define GATE_ETH_HIF0(_id, _parent, _shift) \
+ GATE_ETH_HIF(_id, _parent, _shift, CLK_PARENT_APMIXED)
-#define GATE_ETH1(_id, _parent, _shift) \
- GATE_ETH(_id, _parent, _shift, CLK_PARENT_TOPCKGEN)
+#define GATE_ETH_HIF1(_id, _parent, _shift) \
+ GATE_ETH_HIF(_id, _parent, _shift, CLK_PARENT_TOPCKGEN)
static const struct mtk_gate eth_cgs[] = {
- GATE_ETH1(CLK_ETHSYS_HSDMA, CLK_TOP_ETHIF_SEL, 5),
- GATE_ETH1(CLK_ETHSYS_ESW, CLK_TOP_ETHPLL_500M, 6),
- GATE_ETH0(CLK_ETHSYS_GP2, CLK_APMIXED_TRGPLL, 7),
- GATE_ETH1(CLK_ETHSYS_GP1, CLK_TOP_ETHPLL_500M, 8),
- GATE_ETH1(CLK_ETHSYS_PCM, CLK_TOP_ETHIF_SEL, 11),
- GATE_ETH1(CLK_ETHSYS_GDMA, CLK_TOP_ETHIF_SEL, 14),
- GATE_ETH1(CLK_ETHSYS_I2S, CLK_TOP_ETHIF_SEL, 17),
- GATE_ETH1(CLK_ETHSYS_CRYPTO, CLK_TOP_ETHIF_SEL, 29),
+ GATE_ETH_HIF1(CLK_ETHSYS_HSDMA, CLK_TOP_ETHIF_SEL, 5),
+ GATE_ETH_HIF1(CLK_ETHSYS_ESW, CLK_TOP_ETHPLL_500M, 6),
+ GATE_ETH_HIF0(CLK_ETHSYS_GP2, CLK_APMIXED_TRGPLL, 7),
+ GATE_ETH_HIF1(CLK_ETHSYS_GP1, CLK_TOP_ETHPLL_500M, 8),
+ GATE_ETH_HIF1(CLK_ETHSYS_PCM, CLK_TOP_ETHIF_SEL, 11),
+ GATE_ETH_HIF1(CLK_ETHSYS_GDMA, CLK_TOP_ETHIF_SEL, 14),
+ GATE_ETH_HIF1(CLK_ETHSYS_I2S, CLK_TOP_ETHIF_SEL, 17),
+ GATE_ETH_HIF1(CLK_ETHSYS_CRYPTO, CLK_TOP_ETHIF_SEL, 29),
+};
+
+static const struct mtk_gate hif_cgs[] = {
+ GATE_ETH_HIF1(CLK_HIFSYS_USB0PHY, CLK_TOP_ETHPLL_500M, 21),
+ GATE_ETH_HIF1(CLK_HIFSYS_USB1PHY, CLK_TOP_ETHPLL_500M, 22),
+ GATE_ETH_HIF1(CLK_HIFSYS_PCIE0, CLK_TOP_ETHPLL_500M, 24),
+ GATE_ETH_HIF1(CLK_HIFSYS_PCIE1, CLK_TOP_ETHPLL_500M, 25),
+ GATE_ETH_HIF1(CLK_HIFSYS_PCIE2, CLK_TOP_ETHPLL_500M, 26),
};
static const struct mtk_clk_tree mt7623_clk_tree = {
@@ -778,19 +786,24 @@
return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, peri_cgs);
}
+static int mt7623_hifsys_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, hif_cgs);
+}
+
static int mt7623_ethsys_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, eth_cgs);
}
-static int mt7623_ethsys_bind(struct udevice *dev)
+static int mt7623_ethsys_hifsys_bind(struct udevice *dev)
{
int ret = 0;
#if CONFIG_IS_ENABLED(RESET_MEDIATEK)
- ret = mediatek_reset_bind(dev, ETHSYS_RST_CTRL_OFS, 1);
+ ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
if (ret)
- debug("Warning: failed to bind ethsys reset controller\n");
+ debug("Warning: failed to bind reset controller\n");
#endif
return ret;
@@ -821,6 +834,11 @@
{ }
};
+static const struct udevice_id mt7623_hifsys_compat[] = {
+ { .compatible = "mediatek,mt7623-hifsys" },
+ { }
+};
+
static const struct udevice_id mt7623_mcucfg_compat[] = {
{ .compatible = "mediatek,mt7623-mcucfg" },
{ }
@@ -874,12 +892,22 @@
.flags = DM_FLAG_PRE_RELOC,
};
+U_BOOT_DRIVER(mtk_clk_hifsys) = {
+ .name = "mt7623-clock-hifsys",
+ .id = UCLASS_CLK,
+ .of_match = mt7623_hifsys_compat,
+ .probe = mt7623_hifsys_probe,
+ .bind = mt7623_ethsys_hifsys_bind,
+ .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .ops = &mtk_clk_gate_ops,
+};
+
U_BOOT_DRIVER(mtk_clk_ethsys) = {
.name = "mt7623-clock-ethsys",
.id = UCLASS_CLK,
.of_match = mt7623_ethsys_compat,
.probe = mt7623_ethsys_probe,
- .bind = mt7623_ethsys_bind,
+ .bind = mt7623_ethsys_hifsys_bind,
.priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
};
diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c
index 6a9f601..30a919f 100644
--- a/drivers/clk/mediatek/clk-mt7629.c
+++ b/drivers/clk/mediatek/clk-mt7629.c
@@ -608,9 +608,9 @@
int ret = 0;
#if CONFIG_IS_ENABLED(RESET_MEDIATEK)
- ret = mediatek_reset_bind(dev, ETHSYS_RST_CTRL_OFS, 1);
+ ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
if (ret)
- debug("Warning: failed to bind ethsys reset controller\n");
+ debug("Warning: failed to bind reset controller\n");
#endif
return ret;
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index 7847388..dce9325 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -23,7 +23,7 @@
#define CLK_PARENT_TOPCKGEN BIT(5)
#define CLK_PARENT_MASK GENMASK(5, 4)
-#define ETHSYS_RST_CTRL_OFS 0x34
+#define ETHSYS_HIFSYS_RST_CTRL_OFS 0x34
/* struct mtk_pll_data - hardware-specific PLLs data */
struct mtk_pll_data {
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index 112326e..43dac1a 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -405,6 +405,7 @@
static const struct udevice_id meson_clk_ids[] = {
{ .compatible = "amlogic,g12a-clkc" },
+ { .compatible = "amlogic,g12b-clkc" },
{ }
};
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 2cb53fb..abb5337 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -823,10 +823,7 @@
case CLKID_MPLL1:
case CLKID_MPLL2:
case CLKID_CLK81:
- if (current_rate != rate)
- return -EINVAL;
-
- return 0;
+ return -EINVAL;
case CLKID_VPU:
return meson_clk_set_rate_by_id(clk,
meson_mux_get_parent(clk, CLKID_VPU), rate,
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 3862c1b..e788178 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -72,6 +72,12 @@
help
Enable this to support the clocks on Renesas R8A77970 SoC.
+config CLK_R8A77980
+ bool "Renesas R8A77980 clock driver"
+ depends on CLK_RCAR_GEN3
+ help
+ Enable this to support the clocks on Renesas R8A77980 SoC.
+
config CLK_R8A77990
bool "Renesas R8A77990 clock driver"
depends on CLK_RCAR_GEN3
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index 26b3439..88339e9 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -10,5 +10,6 @@
obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77965) += r8a77965-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
diff --git a/drivers/clk/renesas/r8a77980-cpg-mssr.c b/drivers/clk/renesas/r8a77980-cpg-mssr.c
new file mode 100644
index 0000000..c076ac7
--- /dev/null
+++ b/drivers/clk/renesas/r8a77980-cpg-mssr.c
@@ -0,0 +1,255 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * r8a77980 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
+ *
+ * Based on r8a7795-cpg-mssr.c
+ *
+ * Copyright (C) 2015 Glider bvba
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+
+#include <dt-bindings/clock/r8a77980-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen3-cpg.h"
+
+enum clk_ids {
+ /* Core Clock Outputs exported to DT */
+ LAST_DT_CORE_CLK = R8A77980_CLK_OSC,
+
+ /* External Input Clocks */
+ CLK_EXTAL,
+ CLK_EXTALR,
+
+ /* Internal Core Clocks */
+ CLK_MAIN,
+ CLK_PLL1,
+ CLK_PLL2,
+ CLK_PLL3,
+ CLK_PLL1_DIV2,
+ CLK_PLL1_DIV4,
+ CLK_S0,
+ CLK_S1,
+ CLK_S2,
+ CLK_S3,
+ CLK_SDSRC,
+ CLK_RPCSRC,
+ CLK_OCO,
+
+ /* Module Clocks */
+ MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a77980_core_clks[] = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+ DEF_INPUT("extalr", CLK_EXTALR),
+
+ /* Internal Core Clocks */
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
+ DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
+ DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
+
+ DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
+ DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
+ DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
+ DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
+ DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
+ DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
+ DEF_RATE(".oco", CLK_OCO, 32768),
+
+ DEF_BASE("rpc", R8A77980_CLK_RPC, CLK_TYPE_GEN3_RPC,
+ CLK_RPCSRC),
+ DEF_BASE("rpcd2", R8A77980_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
+ R8A77980_CLK_RPC),
+
+ /* Core Clock Outputs */
+ DEF_FIXED("ztr", R8A77980_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
+ DEF_FIXED("ztrd2", R8A77980_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
+ DEF_FIXED("zt", R8A77980_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
+ DEF_FIXED("zx", R8A77980_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED("s0d1", R8A77980_CLK_S0D1, CLK_S0, 1, 1),
+ DEF_FIXED("s0d2", R8A77980_CLK_S0D2, CLK_S0, 2, 1),
+ DEF_FIXED("s0d3", R8A77980_CLK_S0D3, CLK_S0, 3, 1),
+ DEF_FIXED("s0d4", R8A77980_CLK_S0D4, CLK_S0, 4, 1),
+ DEF_FIXED("s0d6", R8A77980_CLK_S0D6, CLK_S0, 6, 1),
+ DEF_FIXED("s0d12", R8A77980_CLK_S0D12, CLK_S0, 12, 1),
+ DEF_FIXED("s0d24", R8A77980_CLK_S0D24, CLK_S0, 24, 1),
+ DEF_FIXED("s1d1", R8A77980_CLK_S1D1, CLK_S1, 1, 1),
+ DEF_FIXED("s1d2", R8A77980_CLK_S1D2, CLK_S1, 2, 1),
+ DEF_FIXED("s1d4", R8A77980_CLK_S1D4, CLK_S1, 4, 1),
+ DEF_FIXED("s2d1", R8A77980_CLK_S2D1, CLK_S2, 1, 1),
+ DEF_FIXED("s2d2", R8A77980_CLK_S2D2, CLK_S2, 2, 1),
+ DEF_FIXED("s2d4", R8A77980_CLK_S2D4, CLK_S2, 4, 1),
+ DEF_FIXED("s3d1", R8A77980_CLK_S3D1, CLK_S3, 1, 1),
+ DEF_FIXED("s3d2", R8A77980_CLK_S3D2, CLK_S3, 2, 1),
+ DEF_FIXED("s3d4", R8A77980_CLK_S3D4, CLK_S3, 4, 1),
+
+ DEF_GEN3_SD("sd0", R8A77980_CLK_SD0, CLK_SDSRC, 0x0074),
+
+ DEF_FIXED("cl", R8A77980_CLK_CL, CLK_PLL1_DIV2, 48, 1),
+ DEF_FIXED("cp", R8A77980_CLK_CP, CLK_EXTAL, 2, 1),
+ DEF_FIXED("cpex", R8A77980_CLK_CPEX, CLK_EXTAL, 2, 1),
+
+ DEF_DIV6P1("canfd", R8A77980_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
+ DEF_DIV6P1("csi0", R8A77980_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
+ DEF_DIV6P1("mso", R8A77980_CLK_MSO, CLK_PLL1_DIV4, 0x014),
+
+ DEF_GEN3_OSC("osc", R8A77980_CLK_OSC, CLK_EXTAL, 8),
+ DEF_GEN3_MDSEL("r", R8A77980_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
+};
+
+static const struct mssr_mod_clk r8a77980_mod_clks[] = {
+ DEF_MOD("tmu4", 121, R8A77980_CLK_S0D6),
+ DEF_MOD("tmu3", 122, R8A77980_CLK_S0D6),
+ DEF_MOD("tmu2", 123, R8A77980_CLK_S0D6),
+ DEF_MOD("tmu1", 124, R8A77980_CLK_S0D6),
+ DEF_MOD("tmu0", 125, R8A77980_CLK_CP),
+ DEF_MOD("scif4", 203, R8A77980_CLK_S3D4),
+ DEF_MOD("scif3", 204, R8A77980_CLK_S3D4),
+ DEF_MOD("scif1", 206, R8A77980_CLK_S3D4),
+ DEF_MOD("scif0", 207, R8A77980_CLK_S3D4),
+ DEF_MOD("msiof3", 208, R8A77980_CLK_MSO),
+ DEF_MOD("msiof2", 209, R8A77980_CLK_MSO),
+ DEF_MOD("msiof1", 210, R8A77980_CLK_MSO),
+ DEF_MOD("msiof0", 211, R8A77980_CLK_MSO),
+ DEF_MOD("sys-dmac2", 217, R8A77980_CLK_S0D3),
+ DEF_MOD("sys-dmac1", 218, R8A77980_CLK_S0D3),
+ DEF_MOD("cmt3", 300, R8A77980_CLK_R),
+ DEF_MOD("cmt2", 301, R8A77980_CLK_R),
+ DEF_MOD("cmt1", 302, R8A77980_CLK_R),
+ DEF_MOD("cmt0", 303, R8A77980_CLK_R),
+ DEF_MOD("tpu0", 304, R8A77980_CLK_S3D4),
+ DEF_MOD("sdif", 314, R8A77980_CLK_SD0),
+ DEF_MOD("pciec0", 319, R8A77980_CLK_S2D2),
+ DEF_MOD("rwdt", 402, R8A77980_CLK_R),
+ DEF_MOD("intc-ex", 407, R8A77980_CLK_CP),
+ DEF_MOD("intc-ap", 408, R8A77980_CLK_S0D3),
+ DEF_MOD("hscif3", 517, R8A77980_CLK_S3D1),
+ DEF_MOD("hscif2", 518, R8A77980_CLK_S3D1),
+ DEF_MOD("hscif1", 519, R8A77980_CLK_S3D1),
+ DEF_MOD("hscif0", 520, R8A77980_CLK_S3D1),
+ DEF_MOD("imp4", 521, R8A77980_CLK_S1D1),
+ DEF_MOD("thermal", 522, R8A77980_CLK_CP),
+ DEF_MOD("pwm", 523, R8A77980_CLK_S0D12),
+ DEF_MOD("impdma1", 526, R8A77980_CLK_S1D1),
+ DEF_MOD("impdma0", 527, R8A77980_CLK_S1D1),
+ DEF_MOD("imp-ocv4", 528, R8A77980_CLK_S1D1),
+ DEF_MOD("imp-ocv3", 529, R8A77980_CLK_S1D1),
+ DEF_MOD("imp-ocv2", 531, R8A77980_CLK_S1D1),
+ DEF_MOD("fcpvd0", 603, R8A77980_CLK_S3D1),
+ DEF_MOD("vspd0", 623, R8A77980_CLK_S3D1),
+ DEF_MOD("csi41", 715, R8A77980_CLK_CSI0),
+ DEF_MOD("csi40", 716, R8A77980_CLK_CSI0),
+ DEF_MOD("du0", 724, R8A77980_CLK_S2D1),
+ DEF_MOD("lvds", 727, R8A77980_CLK_S2D1),
+ DEF_MOD("etheravb", 812, R8A77980_CLK_S3D2),
+ DEF_MOD("gether", 813, R8A77980_CLK_S3D2),
+ DEF_MOD("imp3", 824, R8A77980_CLK_S1D1),
+ DEF_MOD("imp2", 825, R8A77980_CLK_S1D1),
+ DEF_MOD("imp1", 826, R8A77980_CLK_S1D1),
+ DEF_MOD("imp0", 827, R8A77980_CLK_S1D1),
+ DEF_MOD("imp-ocv1", 828, R8A77980_CLK_S1D1),
+ DEF_MOD("imp-ocv0", 829, R8A77980_CLK_S1D1),
+ DEF_MOD("impram", 830, R8A77980_CLK_S1D1),
+ DEF_MOD("impcnn", 831, R8A77980_CLK_S1D1),
+ DEF_MOD("gpio5", 907, R8A77980_CLK_CP),
+ DEF_MOD("gpio4", 908, R8A77980_CLK_CP),
+ DEF_MOD("gpio3", 909, R8A77980_CLK_CP),
+ DEF_MOD("gpio2", 910, R8A77980_CLK_CP),
+ DEF_MOD("gpio1", 911, R8A77980_CLK_CP),
+ DEF_MOD("gpio0", 912, R8A77980_CLK_CP),
+ DEF_MOD("can-fd", 914, R8A77980_CLK_S3D2),
+ DEF_MOD("rpc-if", 917, R8A77980_CLK_RPCD2),
+ DEF_MOD("i2c4", 927, R8A77980_CLK_S0D6),
+ DEF_MOD("i2c3", 928, R8A77980_CLK_S0D6),
+ DEF_MOD("i2c2", 929, R8A77980_CLK_S3D2),
+ DEF_MOD("i2c1", 930, R8A77980_CLK_S3D2),
+ DEF_MOD("i2c0", 931, R8A77980_CLK_S3D2),
+};
+
+/*
+ * CPG Clock Data
+ */
+
+/*
+ * MD EXTAL PLL2 PLL1 PLL3 OSC
+ * 14 13 (MHz)
+ * --------------------------------------------------------
+ * 0 0 16.66 x 1 x240 x192 x192 /16
+ * 0 1 20 x 1 x200 x160 x160 /19
+ * 1 0 27 x 1 x148 x118 x118 /26
+ * 1 1 33.33 / 2 x240 x192 x192 /32
+ */
+#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
+ (((md) & BIT(13)) >> 13))
+
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] = {
+ /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
+ { 1, 192, 1, 192, 1, 16, },
+ { 1, 160, 1, 160, 1, 19, },
+ { 1, 118, 1, 118, 1, 26, },
+ { 2, 192, 1, 192, 1, 32, },
+};
+
+static const struct mstp_stop_table r8a77980_mstp_table[] = {
+ { 0x00230000, 0x0, 0x00230000, 0 },
+ { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
+ { 0x14062FD8, 0x2040, 0x14062FD8, 0 },
+ { 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 },
+ { 0x80000184, 0x180, 0x80000184, 0 },
+ { 0x83FFFFFF, 0x0, 0x83FFFFFF, 0 },
+ { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
+ { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
+ { 0x7FF3FFF4, 0x0, 0x7FF3FFF4, 0 },
+ { 0xFBF7FF97, 0x0, 0xFBF7FF97, 0 },
+ { 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
+ { 0x000000B7, 0x0, 0x000000B7, 0 },
+};
+
+static const void *r8a77980_get_pll_config(const u32 cpg_mode)
+{
+ return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+}
+
+static const struct cpg_mssr_info r8a77980_cpg_mssr_info = {
+ .core_clk = r8a77980_core_clks,
+ .core_clk_size = ARRAY_SIZE(r8a77980_core_clks),
+ .mod_clk = r8a77980_mod_clks,
+ .mod_clk_size = ARRAY_SIZE(r8a77980_mod_clks),
+ .mstp_table = r8a77980_mstp_table,
+ .mstp_table_size = ARRAY_SIZE(r8a77980_mstp_table),
+ .reset_node = "renesas,r8a77980-rst",
+ .extalr_node = "extalr",
+ .mod_clk_base = MOD_CLK_BASE,
+ .clk_extal_id = CLK_EXTAL,
+ .clk_extalr_id = CLK_EXTALR,
+ .get_pll_config = r8a77980_get_pll_config,
+};
+
+static const struct udevice_id r8a77980_clk_ids[] = {
+ {
+ .compatible = "renesas,r8a77980-cpg-mssr",
+ .data = (ulong)&r8a77980_cpg_mssr_info
+ },
+ { }
+};
+
+U_BOOT_DRIVER(clk_r8a77980) = {
+ .name = "clk_r8a77980",
+ .id = UCLASS_CLK,
+ .of_match = r8a77980_clk_ids,
+ .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
+ .ops = &gen3_clk_ops,
+ .probe = gen3_clk_probe,
+ .remove = gen3_clk_remove,
+};
diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c
index 9bb9959..dda686c 100644
--- a/drivers/clk/rockchip/clk_rk3188.c
+++ b/drivers/clk/rockchip/clk_rk3188.c
@@ -562,6 +562,9 @@
#endif
rkclk_init(priv->cru, priv->grf, priv->has_bwadj);
+
+ /* Init CPU frequency */
+ rkclk_configure_cpu(priv->cru, priv->grf, APLL_HZ, priv->has_bwadj);
#endif
return 0;
diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
index 375d7f8..0122381 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -940,35 +940,12 @@
return -ENOENT;
}
-static int rk3288_clk_enable(struct clk *clk)
-{
- switch (clk->id) {
- case HCLK_USBHOST0:
- case HCLK_HSIC:
- return 0;
-
- case SCLK_MAC:
- case SCLK_MAC_RX:
- case SCLK_MAC_TX:
- case SCLK_MACREF:
- case SCLK_MACREF_OUT:
- case ACLK_GMAC:
- case PCLK_GMAC:
- /* Required to successfully probe the Designware GMAC driver */
- return 0;
- }
-
- debug("%s: unsupported clk %ld\n", __func__, clk->id);
- return -ENOENT;
-}
-
static struct clk_ops rk3288_clk_ops = {
.get_rate = rk3288_clk_get_rate,
.set_rate = rk3288_clk_set_rate,
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.set_parent = rk3288_clk_set_parent,
#endif
- .enable = rk3288_clk_enable,
};
static int rk3288_clk_ofdata_to_platdata(struct udevice *dev)
diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c
index 89cbae5..c1a867b 100644
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -566,31 +566,12 @@
return -ENOENT;
}
-static int rk3368_clk_enable(struct clk *clk)
-{
- switch (clk->id) {
- case SCLK_MAC:
- case SCLK_MAC_RX:
- case SCLK_MAC_TX:
- case SCLK_MACREF:
- case SCLK_MACREF_OUT:
- case ACLK_GMAC:
- case PCLK_GMAC:
- /* Required to successfully probe the Designware GMAC driver */
- return 0;
- }
-
- debug("%s: unsupported clk %ld\n", __func__, clk->id);
- return -ENOENT;
-}
-
static struct clk_ops rk3368_clk_ops = {
.get_rate = rk3368_clk_get_rate,
.set_rate = rk3368_clk_set_rate,
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.set_parent = rk3368_clk_set_parent,
#endif
- .enable = rk3368_clk_enable,
};
static int rk3368_clk_probe(struct udevice *dev)
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 79007b8..a273bd1 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -1062,37 +1062,12 @@
return -ENOENT;
}
-static int rk3399_clk_enable(struct clk *clk)
-{
- switch (clk->id) {
- case HCLK_HOST0:
- case HCLK_HOST0_ARB:
- case HCLK_HOST1:
- case HCLK_HOST1_ARB:
- return 0;
-
- case SCLK_MAC:
- case SCLK_MAC_RX:
- case SCLK_MAC_TX:
- case SCLK_MACREF:
- case SCLK_MACREF_OUT:
- case ACLK_GMAC:
- case PCLK_GMAC:
- /* Required to successfully probe the Designware GMAC driver */
- return 0;
- }
-
- debug("%s: unsupported clk %ld\n", __func__, clk->id);
- return -ENOENT;
-}
-
static struct clk_ops rk3399_clk_ops = {
.get_rate = rk3399_clk_get_rate,
.set_rate = rk3399_clk_set_rate,
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.set_parent = rk3399_clk_set_parent,
#endif
- .enable = rk3399_clk_enable,
};
#ifdef CONFIG_SPL_BUILD
diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig
index 644881b..c4d0a1f 100644
--- a/drivers/clk/sifive/Kconfig
+++ b/drivers/clk/sifive/Kconfig
@@ -1,8 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
-config CLK_ANALOGBITS_WRPLL_CLN28HPC
- bool
-
config CLK_SIFIVE
bool "SiFive SoC driver support"
depends on CLK
@@ -17,10 +14,3 @@
Supports the Power Reset Clock interface (PRCI) IP block found in
FU540 SoCs. If this kernel is meant to run on a SiFive FU540 SoC,
enable this driver.
-
-config CLK_SIFIVE_GEMGXL_MGMT
- bool "GEMGXL management for SiFive FU540 SoCs"
- depends on CLK_SIFIVE
- help
- Supports the GEMGXL management IP block found in FU540 SoCs to
- control GEM TX clock operation mode for 10/100/1000 Mbps.
diff --git a/drivers/clk/sifive/Makefile b/drivers/clk/sifive/Makefile
index f8263e7..b224279 100644
--- a/drivers/clk/sifive/Makefile
+++ b/drivers/clk/sifive/Makefile
@@ -1,7 +1,3 @@
# SPDX-License-Identifier: GPL-2.0+
-obj-$(CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC) += wrpll-cln28hpc.o
-
obj-$(CONFIG_CLK_SIFIVE_FU540_PRCI) += fu540-prci.o
-
-obj-$(CONFIG_CLK_SIFIVE_GEMGXL_MGMT) += gemgxl-mgmt.o
diff --git a/drivers/clk/sifive/analogbits-wrpll-cln28hpc.h b/drivers/clk/sifive/analogbits-wrpll-cln28hpc.h
deleted file mode 100644
index 4432e24..0000000
--- a/drivers/clk/sifive/analogbits-wrpll-cln28hpc.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2019 Western Digital Corporation or its affiliates.
- *
- * Copyright (C) 2018 SiFive, Inc.
- * Wesley Terpstra
- * Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H
-#define __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H
-
-#include <linux/types.h>
-
-/* DIVQ_VALUES: number of valid DIVQ values */
-#define DIVQ_VALUES 6
-
-/*
- * Bit definitions for struct analogbits_wrpll_cfg.flags
- *
- * WRPLL_FLAGS_BYPASS_FLAG: if set, the PLL is either in bypass, or should be
- * programmed to enter bypass
- * WRPLL_FLAGS_RESET_FLAG: if set, the PLL is in reset
- * WRPLL_FLAGS_INT_FEEDBACK_FLAG: if set, the PLL is configured for internal
- * feedback mode
- * WRPLL_FLAGS_EXT_FEEDBACK_FLAG: if set, the PLL is configured for external
- * feedback mode (not yet supported by this driver)
- *
- * The flags WRPLL_FLAGS_INT_FEEDBACK_FLAG and WRPLL_FLAGS_EXT_FEEDBACK_FLAG are
- * mutually exclusive. If both bits are set, or both are zero, the struct
- * analogbits_wrpll_cfg record is uninitialized or corrupt.
- */
-#define WRPLL_FLAGS_BYPASS_SHIFT 0
-#define WRPLL_FLAGS_BYPASS_MASK BIT(WRPLL_FLAGS_BYPASS_SHIFT)
-#define WRPLL_FLAGS_RESET_SHIFT 1
-#define WRPLL_FLAGS_RESET_MASK BIT(WRPLL_FLAGS_RESET_SHIFT)
-#define WRPLL_FLAGS_INT_FEEDBACK_SHIFT 2
-#define WRPLL_FLAGS_INT_FEEDBACK_MASK BIT(WRPLL_FLAGS_INT_FEEDBACK_SHIFT)
-#define WRPLL_FLAGS_EXT_FEEDBACK_SHIFT 3
-#define WRPLL_FLAGS_EXT_FEEDBACK_MASK BIT(WRPLL_FLAGS_EXT_FEEDBACK_SHIFT)
-
-/**
- * struct analogbits_wrpll_cfg - WRPLL configuration values
- * @divr: reference divider value (6 bits), as presented to the PLL signals.
- * @divf: feedback divider value (9 bits), as presented to the PLL signals.
- * @divq: output divider value (3 bits), as presented to the PLL signals.
- * @flags: PLL configuration flags. See above for more information.
- * @range: PLL loop filter range. See below for more information.
- * @_output_rate_cache: cached output rates, swept across DIVQ.
- * @_parent_rate: PLL refclk rate for which values are valid
- * @_max_r: maximum possible R divider value, given @parent_rate
- * @_init_r: initial R divider value to start the search from
- *
- * @divr, @divq, @divq, @range represent what the PLL expects to see
- * on its input signals. Thus @divr and @divf are the actual divisors
- * minus one. @divq is a power-of-two divider; for example, 1 =
- * divide-by-2 and 6 = divide-by-64. 0 is an invalid @divq value.
- *
- * When initially passing a struct analogbits_wrpll_cfg record, the
- * record should be zero-initialized with the exception of the @flags
- * field. The only flag bits that need to be set are either
- * WRPLL_FLAGS_INT_FEEDBACK or WRPLL_FLAGS_EXT_FEEDBACK.
- *
- * Field names beginning with an underscore should be considered
- * private to the wrpll-cln28hpc.c code.
- */
-struct analogbits_wrpll_cfg {
- u8 divr;
- u8 divq;
- u8 range;
- u8 flags;
- u16 divf;
- u32 _output_rate_cache[DIVQ_VALUES];
- unsigned long _parent_rate;
- u8 _max_r;
- u8 _init_r;
-};
-
-/*
- * Function prototypes
- */
-
-int analogbits_wrpll_configure_for_rate(struct analogbits_wrpll_cfg *c,
- u32 target_rate,
- unsigned long parent_rate);
-
-unsigned int analogbits_wrpll_calc_max_lock_us(struct analogbits_wrpll_cfg *c);
-
-unsigned long analogbits_wrpll_calc_output_rate(struct analogbits_wrpll_cfg *c,
- unsigned long parent_rate);
-
-#endif /* __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H */
diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c
index 2d47ebc..ce0769f 100644
--- a/drivers/clk/sifive/fu540-prci.c
+++ b/drivers/clk/sifive/fu540-prci.c
@@ -37,9 +37,8 @@
#include <errno.h>
#include <linux/math64.h>
-#include <dt-bindings/clk/sifive-fu540-prci.h>
-
-#include "analogbits-wrpll-cln28hpc.h"
+#include <linux/clk/analogbits-wrpll-cln28hpc.h>
+#include <dt-bindings/clock/sifive-fu540-prci.h>
/*
* EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects:
@@ -159,30 +158,32 @@
* PRCI per-device instance data
*/
struct __prci_data {
- void *base;
- struct clk parent;
+ void *va;
+ struct clk parent_hfclk;
+ struct clk parent_rtcclk;
};
/**
* struct __prci_wrpll_data - WRPLL configuration and integration data
* @c: WRPLL current configuration record
- * @bypass: fn ptr to code to bypass the WRPLL (if applicable; else NULL)
- * @no_bypass: fn ptr to code to not bypass the WRPLL (if applicable; else NULL)
+ * @enable_bypass: fn ptr to code to bypass the WRPLL (if applicable; else NULL)
+ * @disable_bypass: fn ptr to code to not bypass the WRPLL (or NULL)
* @cfg0_offs: WRPLL CFG0 register offset (in bytes) from the PRCI base address
*
- * @bypass and @no_bypass are used for WRPLL instances that contain a separate
- * external glitchless clock mux downstream from the PLL. The WRPLL internal
- * bypass mux is not glitchless.
+ * @enable_bypass and @disable_bypass are used for WRPLL instances
+ * that contain a separate external glitchless clock mux downstream
+ * from the PLL. The WRPLL internal bypass mux is not glitchless.
*/
struct __prci_wrpll_data {
- struct analogbits_wrpll_cfg c;
- void (*bypass)(struct __prci_data *pd);
- void (*no_bypass)(struct __prci_data *pd);
+ struct wrpll_cfg c;
+ void (*enable_bypass)(struct __prci_data *pd);
+ void (*disable_bypass)(struct __prci_data *pd);
u8 cfg0_offs;
};
struct __prci_clock;
+/* struct __prci_clock_ops - clock operations */
struct __prci_clock_ops {
int (*set_rate)(struct __prci_clock *pc,
unsigned long rate,
@@ -198,8 +199,7 @@
* struct __prci_clock - describes a clock device managed by PRCI
* @name: user-readable clock name string - should match the manual
* @parent_name: parent name for this clock
- * @ops: struct clk_ops for the Linux clock framework to use for control
- * @hw: Linux-private clock data
+ * @ops: struct __prci_clock_ops for control
* @pwd: WRPLL-specific data, associated with this clock (if not NULL)
* @pd: PRCI-specific data associated with this clock (if not NULL)
*
@@ -233,19 +233,19 @@
*/
static u32 __prci_readl(struct __prci_data *pd, u32 offs)
{
- return readl(pd->base + offs);
+ return readl(pd->va + offs);
}
static void __prci_writel(u32 v, u32 offs, struct __prci_data *pd)
{
- return writel(v, pd->base + offs);
+ writel(v, pd->va + offs);
}
/* WRPLL-related private functions */
/**
* __prci_wrpll_unpack() - unpack WRPLL configuration registers into parameters
- * @c: ptr to a struct analogbits_wrpll_cfg record to write config into
+ * @c: ptr to a struct wrpll_cfg record to write config into
* @r: value read from the PRCI PLL configuration register
*
* Given a value @r read from an FU540 PRCI PLL configuration register,
@@ -257,7 +257,7 @@
*
* Context: Any context.
*/
-static void __prci_wrpll_unpack(struct analogbits_wrpll_cfg *c, u32 r)
+static void __prci_wrpll_unpack(struct wrpll_cfg *c, u32 r)
{
u32 v;
@@ -280,15 +280,13 @@
c->flags &= (WRPLL_FLAGS_INT_FEEDBACK_MASK |
WRPLL_FLAGS_EXT_FEEDBACK_MASK);
- if (r & PRCI_COREPLLCFG0_FSE_MASK)
- c->flags |= WRPLL_FLAGS_INT_FEEDBACK_MASK;
- else
- c->flags |= WRPLL_FLAGS_EXT_FEEDBACK_MASK;
+ /* external feedback mode not supported */
+ c->flags |= WRPLL_FLAGS_INT_FEEDBACK_MASK;
}
/**
* __prci_wrpll_pack() - pack PLL configuration parameters into a register value
- * @c: pointer to a struct analogbits_wrpll_cfg record containing the PLL's cfg
+ * @c: pointer to a struct wrpll_cfg record containing the PLL's cfg
*
* Using a set of WRPLL configuration values pointed to by @c,
* assemble a PRCI PLL configuration register value, and return it to
@@ -301,7 +299,7 @@
* Returns: a value suitable for writing into a PRCI PLL configuration
* register
*/
-static u32 __prci_wrpll_pack(struct analogbits_wrpll_cfg *c)
+static u32 __prci_wrpll_pack(const struct wrpll_cfg *c)
{
u32 r = 0;
@@ -309,8 +307,9 @@
r |= c->divf << PRCI_COREPLLCFG0_DIVF_SHIFT;
r |= c->divq << PRCI_COREPLLCFG0_DIVQ_SHIFT;
r |= c->range << PRCI_COREPLLCFG0_RANGE_SHIFT;
- if (c->flags & WRPLL_FLAGS_INT_FEEDBACK_MASK)
- r |= PRCI_COREPLLCFG0_FSE_MASK;
+
+ /* external feedback mode not supported */
+ r |= PRCI_COREPLLCFG0_FSE_MASK;
return r;
}
@@ -349,11 +348,11 @@
*/
static void __prci_wrpll_write_cfg(struct __prci_data *pd,
struct __prci_wrpll_data *pwd,
- struct analogbits_wrpll_cfg *c)
+ struct wrpll_cfg *c)
{
__prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd);
- memcpy(&pwd->c, c, sizeof(struct analogbits_wrpll_cfg));
+ memcpy(&pwd->c, c, sizeof(*c));
}
/* Core clock mux control */
@@ -404,7 +403,7 @@
{
struct __prci_wrpll_data *pwd = pc->pwd;
- return analogbits_wrpll_calc_output_rate(&pwd->c, parent_rate);
+ return wrpll_calc_output_rate(&pwd->c, parent_rate);
}
static unsigned long sifive_fu540_prci_wrpll_round_rate(
@@ -413,13 +412,13 @@
unsigned long *parent_rate)
{
struct __prci_wrpll_data *pwd = pc->pwd;
- struct analogbits_wrpll_cfg c;
+ struct wrpll_cfg c;
memcpy(&c, &pwd->c, sizeof(c));
- analogbits_wrpll_configure_for_rate(&c, rate, *parent_rate);
+ wrpll_configure_for_rate(&c, rate, *parent_rate);
- return analogbits_wrpll_calc_output_rate(&c, *parent_rate);
+ return wrpll_calc_output_rate(&c, *parent_rate);
}
static int sifive_fu540_prci_wrpll_set_rate(struct __prci_clock *pc,
@@ -430,19 +429,19 @@
struct __prci_data *pd = pc->pd;
int r;
- r = analogbits_wrpll_configure_for_rate(&pwd->c, rate, parent_rate);
+ r = wrpll_configure_for_rate(&pwd->c, rate, parent_rate);
if (r)
- return -ERANGE;
+ return r;
- if (pwd->bypass)
- pwd->bypass(pd);
+ if (pwd->enable_bypass)
+ pwd->enable_bypass(pd);
__prci_wrpll_write_cfg(pd, pwd, &pwd->c);
- udelay(analogbits_wrpll_calc_max_lock_us(&pwd->c));
+ udelay(wrpll_calc_max_lock_us(&pwd->c));
- if (pwd->no_bypass)
- pwd->no_bypass(pd);
+ if (pwd->disable_bypass)
+ pwd->disable_bypass(pd);
return 0;
}
@@ -484,8 +483,8 @@
static struct __prci_wrpll_data __prci_corepll_data = {
.cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
- .bypass = __prci_coreclksel_use_hfclk,
- .no_bypass = __prci_coreclksel_use_corepll,
+ .enable_bypass = __prci_coreclksel_use_hfclk,
+ .disable_bypass = __prci_coreclksel_use_corepll,
};
static struct __prci_wrpll_data __prci_ddrpll_data = {
@@ -526,6 +525,27 @@
},
};
+static ulong sifive_fu540_prci_parent_rate(struct __prci_clock *pc)
+{
+ ulong parent_rate;
+ struct __prci_clock *p;
+
+ if (strcmp(pc->parent_name, "corepll") == 0) {
+ p = &__prci_init_clocks[PRCI_CLK_COREPLL];
+ if (!p->pd || !p->ops->recalc_rate)
+ return -ENXIO;
+
+ return p->ops->recalc_rate(p, sifive_fu540_prci_parent_rate(p));
+ }
+
+ if (strcmp(pc->parent_name, "rtcclk") == 0)
+ parent_rate = clk_get_rate(&pc->pd->parent_rtcclk);
+ else
+ parent_rate = clk_get_rate(&pc->pd->parent_hfclk);
+
+ return parent_rate;
+}
+
static ulong sifive_fu540_prci_get_rate(struct clk *clk)
{
struct __prci_clock *pc;
@@ -537,7 +557,7 @@
if (!pc->pd || !pc->ops->recalc_rate)
return -ENXIO;
- return pc->ops->recalc_rate(pc, clk_get_rate(&pc->pd->parent));
+ return pc->ops->recalc_rate(pc, sifive_fu540_prci_parent_rate(pc));
}
static ulong sifive_fu540_prci_set_rate(struct clk *clk, ulong rate)
@@ -552,7 +572,7 @@
if (!pc->pd || !pc->ops->set_rate)
return -ENXIO;
- err = pc->ops->set_rate(pc, rate, clk_get_rate(&pc->pd->parent));
+ err = pc->ops->set_rate(pc, rate, sifive_fu540_prci_parent_rate(pc));
if (err)
return err;
@@ -565,11 +585,15 @@
struct __prci_clock *pc;
struct __prci_data *pd = dev_get_priv(dev);
- pd->base = (void *)dev_read_addr(dev);
- if (IS_ERR(pd->base))
- return PTR_ERR(pd->base);
+ pd->va = (void *)dev_read_addr(dev);
+ if (IS_ERR(pd->va))
+ return PTR_ERR(pd->va);
- err = clk_get_by_index(dev, 0, &pd->parent);
+ err = clk_get_by_index(dev, 0, &pd->parent_hfclk);
+ if (err)
+ return err;
+
+ err = clk_get_by_index(dev, 1, &pd->parent_rtcclk);
if (err)
return err;
@@ -589,8 +613,7 @@
};
static const struct udevice_id sifive_fu540_prci_ids[] = {
- { .compatible = "sifive,fu540-c000-prci0" },
- { .compatible = "sifive,aloeprci0" },
+ { .compatible = "sifive,fu540-c000-prci" },
{ }
};
diff --git a/drivers/clk/sifive/gemgxl-mgmt.c b/drivers/clk/sifive/gemgxl-mgmt.c
deleted file mode 100644
index eb37416..0000000
--- a/drivers/clk/sifive/gemgxl-mgmt.c
+++ /dev/null
@@ -1,60 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2019, Bin Meng <bmeng.cn@gmail.com>
- */
-
-#include <common.h>
-#include <clk-uclass.h>
-#include <dm.h>
-#include <asm/io.h>
-
-struct gemgxl_mgmt_regs {
- __u32 tx_clk_sel;
-};
-
-struct gemgxl_mgmt_platdata {
- struct gemgxl_mgmt_regs *regs;
-};
-
-static int gemgxl_mgmt_ofdata_to_platdata(struct udevice *dev)
-{
- struct gemgxl_mgmt_platdata *plat = dev_get_platdata(dev);
-
- plat->regs = (struct gemgxl_mgmt_regs *)dev_read_addr(dev);
-
- return 0;
-}
-
-static ulong gemgxl_mgmt_set_rate(struct clk *clk, ulong rate)
-{
- struct gemgxl_mgmt_platdata *plat = dev_get_platdata(clk->dev);
-
- /*
- * GEMGXL TX clock operation mode:
- *
- * 0 = GMII mode. Use 125 MHz gemgxlclk from PRCI in TX logic
- * and output clock on GMII output signal GTX_CLK
- * 1 = MII mode. Use MII input signal TX_CLK in TX logic
- */
- writel(rate != 125000000, &plat->regs->tx_clk_sel);
-
- return 0;
-}
-
-const struct clk_ops gemgxl_mgmt_ops = {
- .set_rate = gemgxl_mgmt_set_rate,
-};
-
-static const struct udevice_id gemgxl_mgmt_match[] = {
- { .compatible = "sifive,cadencegemgxlmgmt0", },
- { /* sentinel */ }
-};
-
-U_BOOT_DRIVER(sifive_gemgxl_mgmt) = {
- .name = "sifive-gemgxl-mgmt",
- .id = UCLASS_CLK,
- .of_match = gemgxl_mgmt_match,
- .ofdata_to_platdata = gemgxl_mgmt_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct gemgxl_mgmt_platdata),
- .ops = &gemgxl_mgmt_ops,
-};
diff --git a/drivers/clk/sifive/wrpll-cln28hpc.c b/drivers/clk/sifive/wrpll-cln28hpc.c
deleted file mode 100644
index d377849..0000000
--- a/drivers/clk/sifive/wrpll-cln28hpc.c
+++ /dev/null
@@ -1,390 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2019 Western Digital Corporation or its affiliates.
- *
- * Copyright (C) 2018 SiFive, Inc.
- * Wesley Terpstra
- * Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * This library supports configuration parsing and reprogramming of
- * the CLN28HPC variant of the Analog Bits Wide Range PLL. The
- * intention is for this library to be reusable for any device that
- * integrates this PLL; thus the register structure and programming
- * details are expected to be provided by a separate IP block driver.
- *
- * The bulk of this code is primarily useful for clock configurations
- * that must operate at arbitrary rates, as opposed to clock configurations
- * that are restricted by software or manufacturer guidance to a small,
- * pre-determined set of performance points.
- *
- * References:
- * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
- * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
- */
-
-#include <linux/bug.h>
-#include <linux/err.h>
-#include <linux/log2.h>
-#include <linux/math64.h>
-
-#include "analogbits-wrpll-cln28hpc.h"
-
-/* MIN_INPUT_FREQ: minimum input clock frequency, in Hz (Fref_min) */
-#define MIN_INPUT_FREQ 7000000
-
-/* MAX_INPUT_FREQ: maximum input clock frequency, in Hz (Fref_max) */
-#define MAX_INPUT_FREQ 600000000
-
-/* MIN_POST_DIVIDE_REF_FREQ: minimum post-divider reference frequency, in Hz */
-#define MIN_POST_DIVR_FREQ 7000000
-
-/* MAX_POST_DIVIDE_REF_FREQ: maximum post-divider reference frequency, in Hz */
-#define MAX_POST_DIVR_FREQ 200000000
-
-/* MIN_VCO_FREQ: minimum VCO frequency, in Hz (Fvco_min) */
-#define MIN_VCO_FREQ 2400000000UL
-
-/* MAX_VCO_FREQ: maximum VCO frequency, in Hz (Fvco_max) */
-#define MAX_VCO_FREQ 4800000000ULL
-
-/* MAX_DIVQ_DIVISOR: maximum output divisor. Selected by DIVQ = 6 */
-#define MAX_DIVQ_DIVISOR 64
-
-/* MAX_DIVR_DIVISOR: maximum reference divisor. Selected by DIVR = 63 */
-#define MAX_DIVR_DIVISOR 64
-
-/* MAX_LOCK_US: maximum PLL lock time, in microseconds (tLOCK_max) */
-#define MAX_LOCK_US 70
-
-/*
- * ROUND_SHIFT: number of bits to shift to avoid precision loss in the rounding
- * algorithm
- */
-#define ROUND_SHIFT 20
-
-/*
- * Private functions
- */
-
-/**
- * __wrpll_calc_filter_range() - determine PLL loop filter bandwidth
- * @post_divr_freq: input clock rate after the R divider
- *
- * Select the value to be presented to the PLL RANGE input signals, based
- * on the input clock frequency after the post-R-divider @post_divr_freq.
- * This code follows the recommendations in the PLL datasheet for filter
- * range selection.
- *
- * Return: The RANGE value to be presented to the PLL configuration inputs,
- * or -1 upon error.
- */
-static int __wrpll_calc_filter_range(unsigned long post_divr_freq)
-{
- u8 range;
-
- if (post_divr_freq < MIN_POST_DIVR_FREQ ||
- post_divr_freq > MAX_POST_DIVR_FREQ) {
- WARN(1, "%s: post-divider reference freq out of range: %lu",
- __func__, post_divr_freq);
- return -1;
- }
-
- if (post_divr_freq < 11000000)
- range = 1;
- else if (post_divr_freq < 18000000)
- range = 2;
- else if (post_divr_freq < 30000000)
- range = 3;
- else if (post_divr_freq < 50000000)
- range = 4;
- else if (post_divr_freq < 80000000)
- range = 5;
- else if (post_divr_freq < 130000000)
- range = 6;
- else
- range = 7;
-
- return range;
-}
-
-/**
- * __wrpll_calc_fbdiv() - return feedback fixed divide value
- * @c: ptr to a struct analogbits_wrpll_cfg record to read from
- *
- * The internal feedback path includes a fixed by-two divider; the
- * external feedback path does not. Return the appropriate divider
- * value (2 or 1) depending on whether internal or external feedback
- * is enabled. This code doesn't test for invalid configurations
- * (e.g. both or neither of WRPLL_FLAGS_*_FEEDBACK are set); it relies
- * on the caller to do so.
- *
- * Context: Any context. Caller must protect the memory pointed to by
- * @c from simultaneous modification.
- *
- * Return: 2 if internal feedback is enabled or 1 if external feedback
- * is enabled.
- */
-static u8 __wrpll_calc_fbdiv(struct analogbits_wrpll_cfg *c)
-{
- return (c->flags & WRPLL_FLAGS_INT_FEEDBACK_MASK) ? 2 : 1;
-}
-
-/**
- * __wrpll_calc_divq() - determine DIVQ based on target PLL output clock rate
- * @target_rate: target PLL output clock rate
- * @vco_rate: pointer to a u64 to store the computed VCO rate into
- *
- * Determine a reasonable value for the PLL Q post-divider, based on the
- * target output rate @target_rate for the PLL. Along with returning the
- * computed Q divider value as the return value, this function stores the
- * desired target VCO rate into the variable pointed to by @vco_rate.
- *
- * Context: Any context. Caller must protect the memory pointed to by
- * @vco_rate from simultaneous access or modification.
- *
- * Return: a positive integer DIVQ value to be programmed into the hardware
- * upon success, or 0 upon error (since 0 is an invalid DIVQ value)
- */
-static u8 __wrpll_calc_divq(u32 target_rate, u64 *vco_rate)
-{
- u64 s;
- u8 divq = 0;
-
- if (!vco_rate) {
- WARN_ON(1);
- goto wcd_out;
- }
-
- s = div_u64(MAX_VCO_FREQ, target_rate);
- if (s <= 1) {
- divq = 1;
- *vco_rate = MAX_VCO_FREQ;
- } else if (s > MAX_DIVQ_DIVISOR) {
- divq = ilog2(MAX_DIVQ_DIVISOR);
- *vco_rate = MIN_VCO_FREQ;
- } else {
- divq = ilog2(s);
- *vco_rate = target_rate << divq;
- }
-
-wcd_out:
- return divq;
-}
-
-/**
- * __wrpll_update_parent_rate() - update PLL data when parent rate changes
- * @c: ptr to a struct analogbits_wrpll_cfg record to write PLL data to
- * @parent_rate: PLL input refclk rate (pre-R-divider)
- *
- * Pre-compute some data used by the PLL configuration algorithm when
- * the PLL's reference clock rate changes. The intention is to avoid
- * computation when the parent rate remains constant - expected to be
- * the common case.
- *
- * Returns: 0 upon success or -1 if the reference clock rate is out of range.
- */
-static int __wrpll_update_parent_rate(struct analogbits_wrpll_cfg *c,
- unsigned long parent_rate)
-{
- u8 max_r_for_parent;
-
- if (parent_rate > MAX_INPUT_FREQ || parent_rate < MIN_POST_DIVR_FREQ)
- return -1;
-
- c->_parent_rate = parent_rate;
- max_r_for_parent = div_u64(parent_rate, MIN_POST_DIVR_FREQ);
- c->_max_r = min_t(u8, MAX_DIVR_DIVISOR, max_r_for_parent);
-
- /* Round up */
- c->_init_r = div_u64(parent_rate + MAX_POST_DIVR_FREQ - 1,
- MAX_POST_DIVR_FREQ);
-
- return 0;
-}
-
-/*
- * Public functions
- */
-
-/**
- * analogbits_wrpll_configure() - compute PLL configuration for a target rate
- * @c: ptr to a struct analogbits_wrpll_cfg record to write into
- * @target_rate: target PLL output clock rate (post-Q-divider)
- * @parent_rate: PLL input refclk rate (pre-R-divider)
- *
- * Given a pointer to a PLL context @c, a desired PLL target output
- * rate @target_rate, and a reference clock input rate @parent_rate,
- * compute the appropriate PLL signal configuration values. PLL
- * reprogramming is not glitchless, so the caller should switch any
- * downstream logic to a different clock source or clock-gate it
- * before presenting these values to the PLL configuration signals.
- *
- * The caller must pass this function a pre-initialized struct
- * analogbits_wrpll_cfg record: either initialized to zero (with the
- * exception of the .name and .flags fields) or read from the PLL.
- *
- * Context: Any context. Caller must protect the memory pointed to by @c
- * from simultaneous access or modification.
- *
- * Return: 0 upon success; anything else upon failure.
- */
-int analogbits_wrpll_configure_for_rate(struct analogbits_wrpll_cfg *c,
- u32 target_rate,
- unsigned long parent_rate)
-{
- unsigned long ratio;
- u64 target_vco_rate, delta, best_delta, f_pre_div, vco, vco_pre;
- u32 best_f, f, post_divr_freq, fbcfg;
- u8 fbdiv, divq, best_r, r;
-
- if (!c)
- return -1;
-
- if (c->flags == 0) {
- WARN(1, "%s called with uninitialized PLL config", __func__);
- return -1;
- }
-
- fbcfg = WRPLL_FLAGS_INT_FEEDBACK_MASK | WRPLL_FLAGS_EXT_FEEDBACK_MASK;
- if ((c->flags & fbcfg) == fbcfg) {
- WARN(1, "%s called with invalid PLL config", __func__);
- return -1;
- }
-
- if (c->flags == WRPLL_FLAGS_EXT_FEEDBACK_MASK) {
- WARN(1, "%s: external feedback mode not currently supported",
- __func__);
- return -1;
- }
-
- /* Initialize rounding data if it hasn't been initialized already */
- if (parent_rate != c->_parent_rate) {
- if (__wrpll_update_parent_rate(c, parent_rate)) {
- pr_err("%s: PLL input rate is out of range\n",
- __func__);
- return -1;
- }
- }
-
- c->flags &= ~WRPLL_FLAGS_RESET_MASK;
-
- /* Put the PLL into bypass if the user requests the parent clock rate */
- if (target_rate == parent_rate) {
- c->flags |= WRPLL_FLAGS_BYPASS_MASK;
- return 0;
- }
- c->flags &= ~WRPLL_FLAGS_BYPASS_MASK;
-
- /* Calculate the Q shift and target VCO rate */
- divq = __wrpll_calc_divq(target_rate, &target_vco_rate);
- if (divq == 0)
- return -1;
- c->divq = divq;
-
- /* Precalculate the pre-Q divider target ratio */
- ratio = div64_u64((target_vco_rate << ROUND_SHIFT), parent_rate);
-
- fbdiv = __wrpll_calc_fbdiv(c);
- best_r = 0;
- best_f = 0;
- best_delta = MAX_VCO_FREQ;
-
- /*
- * Consider all values for R which land within
- * [MIN_POST_DIVR_FREQ, MAX_POST_DIVR_FREQ]; prefer smaller R
- */
- for (r = c->_init_r; r <= c->_max_r; ++r) {
- /* What is the best F we can pick in this case? */
- f_pre_div = ratio * r;
- f = (f_pre_div + (1 << ROUND_SHIFT)) >> ROUND_SHIFT;
- f >>= (fbdiv - 1);
-
- post_divr_freq = div_u64(parent_rate, r);
- vco_pre = fbdiv * post_divr_freq;
- vco = vco_pre * f;
-
- /* Ensure rounding didn't take us out of range */
- if (vco > target_vco_rate) {
- --f;
- vco = vco_pre * f;
- } else if (vco < MIN_VCO_FREQ) {
- ++f;
- vco = vco_pre * f;
- }
-
- delta = abs(target_rate - vco);
- if (delta < best_delta) {
- best_delta = delta;
- best_r = r;
- best_f = f;
- }
- }
-
- c->divr = best_r - 1;
- c->divf = best_f - 1;
-
- post_divr_freq = div_u64(parent_rate, best_r);
-
- /* Pick the best PLL jitter filter */
- c->range = __wrpll_calc_filter_range(post_divr_freq);
-
- return 0;
-}
-
-/**
- * analogbits_wrpll_calc_output_rate() - calculate the PLL's target output rate
- * @c: ptr to a struct analogbits_wrpll_cfg record to read from
- * @parent_rate: PLL refclk rate
- *
- * Given a pointer to the PLL's current input configuration @c and the
- * PLL's input reference clock rate @parent_rate (before the R
- * pre-divider), calculate the PLL's output clock rate (after the Q
- * post-divider)
- *
- * Context: Any context. Caller must protect the memory pointed to by @c
- * from simultaneous modification.
- *
- * Return: the PLL's output clock rate, in Hz.
- */
-unsigned long analogbits_wrpll_calc_output_rate(struct analogbits_wrpll_cfg *c,
- unsigned long parent_rate)
-{
- u8 fbdiv;
- u64 n;
-
- WARN(c->flags & WRPLL_FLAGS_EXT_FEEDBACK_MASK,
- "external feedback mode not yet supported");
-
- fbdiv = __wrpll_calc_fbdiv(c);
- n = parent_rate * fbdiv * (c->divf + 1);
- n = div_u64(n, (c->divr + 1));
- n >>= c->divq;
-
- return n;
-}
-
-/**
- * analogbits_wrpll_calc_max_lock_us() - return the time for the PLL to lock
- * @c: ptr to a struct analogbits_wrpll_cfg record to read from
- *
- * Return the minimum amount of time (in microseconds) that the caller
- * must wait after reprogramming the PLL to ensure that it is locked
- * to the input frequency and stable. This is likely to depend on the DIVR
- * value; this is under discussion with the manufacturer.
- *
- * Return: the minimum amount of time the caller must wait for the PLL
- * to lock (in microseconds)
- */
-unsigned int analogbits_wrpll_calc_max_lock_us(struct analogbits_wrpll_cfg *c)
-{
- return MAX_LOCK_US;
-}
diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c
index 0bb00f4..105c15d 100644
--- a/drivers/clk/sunxi/clk_h6.c
+++ b/drivers/clk/sunxi/clk_h6.c
@@ -28,6 +28,22 @@
[CLK_BUS_SPI1] = GATE(0x96c, BIT(1)),
[CLK_BUS_EMAC] = GATE(0x97c, BIT(0)),
+
+ [CLK_USB_PHY0] = GATE(0xa70, BIT(29)),
+ [CLK_USB_OHCI0] = GATE(0xa70, BIT(31)),
+
+ [CLK_USB_PHY1] = GATE(0xa74, BIT(29)),
+
+ [CLK_USB_HSIC] = GATE(0xa7c, BIT(26)),
+ [CLK_USB_HSIC_12M] = GATE(0xa7c, BIT(27)),
+ [CLK_USB_PHY3] = GATE(0xa7c, BIT(29)),
+ [CLK_USB_OHCI3] = GATE(0xa7c, BIT(31)),
+
+ [CLK_BUS_OHCI0] = GATE(0xa8c, BIT(0)),
+ [CLK_BUS_OHCI3] = GATE(0xa8c, BIT(3)),
+ [CLK_BUS_EHCI0] = GATE(0xa8c, BIT(4)),
+ [CLK_BUS_EHCI3] = GATE(0xa8c, BIT(7)),
+ [CLK_BUS_OTG] = GATE(0xa8c, BIT(8)),
};
static struct ccu_reset h6_resets[] = {
@@ -43,6 +59,19 @@
[RST_BUS_SPI1] = RESET(0x96c, BIT(17)),
[RST_BUS_EMAC] = RESET(0x97c, BIT(16)),
+
+ [RST_USB_PHY0] = RESET(0xa70, BIT(30)),
+
+ [RST_USB_PHY1] = RESET(0xa74, BIT(30)),
+
+ [RST_USB_HSIC] = RESET(0xa7c, BIT(28)),
+ [RST_USB_PHY3] = RESET(0xa7c, BIT(30)),
+
+ [RST_BUS_OHCI0] = RESET(0xa8c, BIT(16)),
+ [RST_BUS_OHCI3] = RESET(0xa8c, BIT(19)),
+ [RST_BUS_EHCI0] = RESET(0xa8c, BIT(20)),
+ [RST_BUS_EHCI3] = RESET(0xa8c, BIT(23)),
+ [RST_BUS_OTG] = RESET(0xa8c, BIT(24)),
};
static const struct ccu_desc h6_ccu_desc = {
diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c
index 487b43e..c627a4b 100644
--- a/drivers/clk/uniphier/clk-uniphier-sys.c
+++ b/drivers/clk/uniphier/clk-uniphier-sys.c
@@ -18,8 +18,8 @@
#if defined(CONFIG_ARCH_UNIPHIER_LD4) || defined(CONFIG_ARCH_UNIPHIER_SLD8) ||\
defined(CONFIG_ARCH_UNIPHIER_PRO4) || defined(CONFIG_ARCH_UNIPHIER_PRO5) ||\
defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B)
- UNIPHIER_LD4_SYS_CLK_NAND(2),
- UNIPHIER_CLK_RATE(3, 200000000),
+ UNIPHIER_LD4_SYS_CLK_NAND(2), /* nand */
+ UNIPHIER_CLK_RATE(3, 200000000), /* nand-4x */
UNIPHIER_CLK_GATE_SIMPLE(6, 0x2104, 12), /* ether (Pro4, PXs2) */
UNIPHIER_CLK_GATE_SIMPLE(7, 0x2104, 5), /* ether-gb (Pro4) */
UNIPHIER_CLK_GATE_SIMPLE(8, 0x2104, 10), /* stdmac */
@@ -35,8 +35,9 @@
const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20)
- UNIPHIER_LD11_SYS_CLK_NAND(2),
- UNIPHIER_CLK_RATE(3, 200000000),
+ UNIPHIER_LD11_SYS_CLK_NAND(2), /* nand */
+ UNIPHIER_CLK_RATE(3, 200000000), /* nand-4x */
+ UNIPHIER_CLK_GATE_SIMPLE(4, 0x210c, 2), /* emmc */
UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 6), /* ether */
UNIPHIER_CLK_GATE_SIMPLE(8, 0x210c, 8), /* stdmac */
UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 14), /* usb30 (LD20) */
@@ -48,8 +49,9 @@
const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
#if defined(CONFIG_ARCH_UNIPHIER_PXS3)
- UNIPHIER_LD11_SYS_CLK_NAND(2),
- UNIPHIER_CLK_RATE(3, 200000000),
+ UNIPHIER_LD11_SYS_CLK_NAND(2), /* nand */
+ UNIPHIER_CLK_RATE(3, 200000000), /* nand-4x */
+ UNIPHIER_CLK_GATE_SIMPLE(4, 0x210c, 2), /* emmc */
UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 9), /* ether0 */
UNIPHIER_CLK_GATE_SIMPLE(7, 0x210c, 10), /* ether1 */
UNIPHIER_CLK_GATE_SIMPLE(12, 0x210c, 4), /* usb30 (gio0) */
diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index 2d195ae..3b95b53 100644
--- a/drivers/core/Kconfig
+++ b/drivers/core/Kconfig
@@ -92,7 +92,7 @@
config SPL_DM_SEQ_ALIAS
bool "Support numbered aliases in device tree in SPL"
- depends on DM
+ depends on SPL_DM
default n
help
Most boards will have a '/aliases' node containing the path to
diff --git a/drivers/core/device.c b/drivers/core/device.c
index 0d15e50..05dadf9 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -388,7 +388,8 @@
if (dev->parent && device_get_uclass_id(dev) != UCLASS_PINCTRL)
pinctrl_select_state(dev, "default");
- if (dev->parent && device_get_uclass_id(dev) != UCLASS_POWER_DOMAIN) {
+ if (CONFIG_IS_ENABLED(POWER_DOMAIN) && dev->parent &&
+ device_get_uclass_id(dev) != UCLASS_POWER_DOMAIN) {
if (!power_domain_get(dev, &pd))
power_domain_on(&pd);
}
@@ -409,10 +410,16 @@
goto fail;
}
- /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
- ret = clk_set_defaults(dev);
- if (ret)
- goto fail;
+ /* Only handle devices that have a valid ofnode */
+ if (dev_of_valid(dev)) {
+ /*
+ * Process 'assigned-{clocks/clock-parents/clock-rates}'
+ * properties
+ */
+ ret = clk_set_defaults(dev);
+ if (ret)
+ goto fail;
+ }
if (drv->probe) {
ret = drv->probe(dev);
@@ -519,6 +526,7 @@
return 0;
}
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
/**
* device_find_by_ofnode() - Return device associated with given ofnode
*
@@ -545,6 +553,7 @@
return -ENODEV;
}
+#endif
int device_get_child(struct udevice *parent, int index, struct udevice **devp)
{
@@ -810,6 +819,7 @@
return 0;
}
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
bool device_is_compatible(struct udevice *dev, const char *compat)
{
return ofnode_device_is_compatible(dev_ofnode(dev), compat);
@@ -872,3 +882,4 @@
return lists_bind_fdt(parent, node, NULL, false);
}
+#endif
diff --git a/drivers/core/fdtaddr.c b/drivers/core/fdtaddr.c
index c287386..6850003 100644
--- a/drivers/core/fdtaddr.c
+++ b/drivers/core/fdtaddr.c
@@ -129,6 +129,23 @@
#endif
}
+fdt_addr_t devfdt_get_addr_size_name(struct udevice *dev, const char *name,
+ fdt_size_t *size)
+{
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+ int index;
+
+ index = fdt_stringlist_search(gd->fdt_blob, dev_of_offset(dev),
+ "reg-names", name);
+ if (index < 0)
+ return index;
+
+ return devfdt_get_addr_size_index(dev, index, size);
+#else
+ return FDT_ADDR_T_NONE;
+#endif
+}
+
fdt_addr_t devfdt_get_addr(struct udevice *dev)
{
return devfdt_get_addr_index(dev, 0);
diff --git a/drivers/core/of_addr.c b/drivers/core/of_addr.c
index 1bfaaee..4e256d9 100644
--- a/drivers/core/of_addr.c
+++ b/drivers/core/of_addr.c
@@ -318,6 +318,10 @@
return __of_translate_address(dev, in_addr, "ranges");
}
+u64 of_translate_dma_address(const struct device_node *dev, const __be32 *in_addr)
+{
+ return __of_translate_address(dev, in_addr, "dma-ranges");
+}
static int __of_address_to_resource(const struct device_node *dev,
const __be32 *addrp, u64 size, unsigned int flags,
diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c
index c72c6e2..297f0a0 100644
--- a/drivers/core/ofnode.c
+++ b/drivers/core/ofnode.c
@@ -79,7 +79,7 @@
return 0;
}
-int ofnode_read_u64_default(ofnode node, const char *propname, u64 def)
+u64 ofnode_read_u64_default(ofnode node, const char *propname, u64 def)
{
assert(ofnode_valid(node));
ofnode_read_u64(node, propname, &def);
@@ -212,7 +212,11 @@
const char *ofnode_get_name(ofnode node)
{
- assert(ofnode_valid(node));
+ if (!ofnode_valid(node)) {
+ debug("%s node not valid\n", __func__);
+ return NULL;
+ }
+
if (ofnode_is_np(node))
return strrchr(node.np->full_name, '/') + 1;
@@ -257,12 +261,15 @@
if (ofnode_is_np(node)) {
const __be32 *prop_val;
+ u64 size64;
uint flags;
- prop_val = of_get_address(ofnode_to_np(node), index,
- (u64 *)size, &flags);
+ prop_val = of_get_address(ofnode_to_np(node), index, &size64,
+ &flags);
if (!prop_val)
return FDT_ADDR_T_NONE;
+ if (size)
+ *size = size64;
ns = of_n_size_cells(ofnode_to_np(node));
@@ -613,7 +620,7 @@
if ((fdt32_to_cpu(*cell) & type) == type) {
addr->phys_hi = fdt32_to_cpu(cell[0]);
addr->phys_mid = fdt32_to_cpu(cell[1]);
- addr->phys_lo = fdt32_to_cpu(cell[1]);
+ addr->phys_lo = fdt32_to_cpu(cell[2]);
break;
}
@@ -770,6 +777,14 @@
return fdt_translate_address(gd->fdt_blob, ofnode_to_offset(node), in_addr);
}
+u64 ofnode_translate_dma_address(ofnode node, const fdt32_t *in_addr)
+{
+ if (ofnode_is_np(node))
+ return of_translate_dma_address(ofnode_to_np(node), in_addr);
+ else
+ return fdt_translate_dma_address(gd->fdt_blob, ofnode_to_offset(node), in_addr);
+}
+
int ofnode_device_is_compatible(ofnode node, const char *compat)
{
if (ofnode_is_np(node))
@@ -876,5 +891,5 @@
if (value)
return ofnode_write_string(node, "status", "okay");
else
- return ofnode_write_string(node, "status", "disable");
+ return ofnode_write_string(node, "status", "disabled");
}
diff --git a/drivers/core/read.c b/drivers/core/read.c
index 6bda077..fb3dcd9 100644
--- a/drivers/core/read.c
+++ b/drivers/core/read.c
@@ -44,6 +44,16 @@
return 0;
}
+int dev_read_u64(struct udevice *dev, const char *propname, u64 *outp)
+{
+ return ofnode_read_u64(dev_ofnode(dev), propname, outp);
+}
+
+u64 dev_read_u64_default(struct udevice *dev, const char *propname, u64 def)
+{
+ return ofnode_read_u64_default(dev_ofnode(dev), propname, def);
+}
+
const char *dev_read_string(struct udevice *dev, const char *propname)
{
return ofnode_read_string(dev_ofnode(dev), propname);
@@ -82,6 +92,15 @@
return devfdt_get_addr_index(dev, index);
}
+fdt_addr_t dev_read_addr_size_index(struct udevice *dev, int index,
+ fdt_size_t *size)
+{
+ if (ofnode_is_np(dev_ofnode(dev)))
+ return ofnode_get_addr_size_index(dev_ofnode(dev), index, size);
+ else
+ return devfdt_get_addr_size_index(dev, index, size);
+}
+
void *dev_remap_addr_index(struct udevice *dev, int index)
{
fdt_addr_t addr = dev_read_addr_index(dev, index);
@@ -102,6 +121,17 @@
return dev_read_addr_index(dev, index);
}
+fdt_addr_t dev_read_addr_size_name(struct udevice *dev, const char *name,
+ fdt_size_t *size)
+{
+ int index = dev_read_stringlist_search(dev, "reg-names", name);
+
+ if (index < 0)
+ return FDT_ADDR_T_NONE;
+ else
+ return dev_read_addr_size_index(dev, index, size);
+}
+
void *dev_remap_addr_name(struct udevice *dev, const char *name)
{
fdt_addr_t addr = dev_read_addr_name(dev, name);
@@ -265,6 +295,11 @@
return ofnode_translate_address(dev_ofnode(dev), in_addr);
}
+u64 dev_translate_dma_address(struct udevice *dev, const fdt32_t *in_addr)
+{
+ return ofnode_translate_dma_address(dev_ofnode(dev), in_addr);
+}
+
int dev_read_alias_highest_id(const char *stem)
{
if (of_live_active())
diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c
index 5ef0f71..d1d12ee 100644
--- a/drivers/core/regmap.c
+++ b/drivers/core/regmap.c
@@ -108,6 +108,48 @@
return 0;
}
+int regmap_init_mem_index(ofnode node, struct regmap **mapp, int index)
+{
+ struct regmap *map;
+ int addr_len, size_len;
+ int ret;
+
+ addr_len = ofnode_read_simple_addr_cells(ofnode_get_parent(node));
+ if (addr_len < 0) {
+ debug("%s: Error while reading the addr length (ret = %d)\n",
+ ofnode_get_name(node), addr_len);
+ return addr_len;
+ }
+
+ size_len = ofnode_read_simple_size_cells(ofnode_get_parent(node));
+ if (size_len < 0) {
+ debug("%s: Error while reading the size length: (ret = %d)\n",
+ ofnode_get_name(node), size_len);
+ return size_len;
+ }
+
+ map = regmap_alloc(1);
+ if (!map)
+ return -ENOMEM;
+
+ ret = init_range(node, map->ranges, addr_len, size_len, index);
+ if (ret)
+ return ret;
+
+ if (ofnode_read_bool(node, "little-endian"))
+ map->endianness = REGMAP_LITTLE_ENDIAN;
+ else if (ofnode_read_bool(node, "big-endian"))
+ map->endianness = REGMAP_BIG_ENDIAN;
+ else if (ofnode_read_bool(node, "native-endian"))
+ map->endianness = REGMAP_NATIVE_ENDIAN;
+ else /* Default: native endianness */
+ map->endianness = REGMAP_NATIVE_ENDIAN;
+
+ *mapp = map;
+
+ return ret;
+}
+
int regmap_init_mem(ofnode node, struct regmap **mapp)
{
struct regmap_range *range;
diff --git a/drivers/core/root.c b/drivers/core/root.c
index aa5ca40..e856438 100644
--- a/drivers/core/root.c
+++ b/drivers/core/root.c
@@ -314,13 +314,6 @@
#endif
return dm_scan_fdt_node(gd->dm_root, blob, 0, pre_reloc_only);
}
-#else
-static int dm_scan_fdt_node(struct udevice *parent, const void *blob,
- int offset, bool pre_reloc_only)
-{
- return 0;
-}
-#endif
static int dm_scan_fdt_ofnode_path(const char *path, bool pre_reloc_only)
{
@@ -360,6 +353,7 @@
return ret;
}
+#endif
__weak int dm_scan_other(bool pre_reloc_only)
{
diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c
index dc9eb62..b332965 100644
--- a/drivers/core/uclass.c
+++ b/drivers/core/uclass.c
@@ -260,7 +260,7 @@
return ret;
uclass_foreach_dev(dev, uc) {
- if (!strncmp(dev->name, name, strlen(name))) {
+ if (!strcmp(dev->name, name)) {
*devp = dev;
return 0;
}
diff --git a/drivers/core/util.c b/drivers/core/util.c
index 96e47dc..7dc1a2a 100644
--- a/drivers/core/util.c
+++ b/drivers/core/util.c
@@ -31,6 +31,7 @@
return count;
}
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
bool dm_ofnode_pre_reloc(ofnode node)
{
#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_TPL_BUILD)
@@ -42,6 +43,8 @@
#else
if (ofnode_read_bool(node, "u-boot,dm-pre-reloc"))
return true;
+ if (ofnode_read_bool(node, "u-boot,dm-pre-proper"))
+ return true;
/*
* In regular builds individual spl and tpl handling both
@@ -54,3 +57,4 @@
return false;
#endif
}
+#endif
diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c
index f77c126..28ad0aa 100644
--- a/drivers/cpu/riscv_cpu.c
+++ b/drivers/cpu/riscv_cpu.c
@@ -46,6 +46,10 @@
ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
const char *device_type;
+ /* skip if hart is marked as not available in the device tree */
+ if (!ofnode_is_available(node))
+ continue;
+
device_type = ofnode_read_string(node, "device_type");
if (!device_type)
continue;
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 0e45262..b85b56e 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -9,31 +9,27 @@
#include <errno.h>
#include "sequencer.h"
-static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
+static const struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
(struct socfpga_sdr_rw_load_manager *)
(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
-static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
- (struct socfpga_sdr_rw_load_jump_manager *)
+static const struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs
+ = (struct socfpga_sdr_rw_load_jump_manager *)
(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
-static struct socfpga_sdr_reg_file *sdr_reg_file =
+static const struct socfpga_sdr_reg_file *sdr_reg_file =
(struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
-static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
+static const struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
(struct socfpga_sdr_scc_mgr *)
(SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
-static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
+static const struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
(struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
-static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
+static const struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
(struct socfpga_phy_mgr_cfg *)
(SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
-static struct socfpga_data_mgr *data_mgr =
+static const struct socfpga_data_mgr *data_mgr =
(struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
-static struct socfpga_sdr_ctrl *sdr_ctrl =
+static const struct socfpga_sdr_ctrl *sdr_ctrl =
(struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
-const struct socfpga_sdram_rw_mgr_config *rwcfg;
-const struct socfpga_sdram_io_config *iocfg;
-const struct socfpga_sdram_misc_config *misccfg;
-
#define DELTA_D 1
/*
@@ -55,37 +51,20 @@
#define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \
STATIC_SKIP_DELAY_LOOPS)
-/* calibration steps requested by the rtl */
-static u16 dyn_calib_steps;
-
-/*
- * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
- * instead of static, we use boolean logic to select between
- * non-skip and skip values
- *
- * The mask is set to include all bits when not-skipping, but is
- * zero when skipping
- */
-
-static u16 skip_delay_mask; /* mask off bits when skipping/not-skipping */
-
#define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
- ((non_skip_value) & skip_delay_mask)
+ ((non_skip_value) & seq->skip_delay_mask)
-static struct gbl_type *gbl;
-static struct param_type *param;
-
-static void set_failing_group_stage(u32 group, u32 stage,
- u32 substage)
+static void set_failing_group_stage(struct socfpga_sdrseq *seq,
+ u32 group, u32 stage, u32 substage)
{
/*
* Only set the global stage if there was not been any other
* failing group
*/
- if (gbl->error_stage == CAL_STAGE_NIL) {
- gbl->error_substage = substage;
- gbl->error_stage = stage;
- gbl->error_group = group;
+ if (seq->gbl.error_stage == CAL_STAGE_NIL) {
+ seq->gbl.error_substage = substage;
+ seq->gbl.error_stage = stage;
+ seq->gbl.error_group = group;
}
}
@@ -110,7 +89,7 @@
*
* Initialize PHY Manager.
*/
-static void phy_mgr_initialize(void)
+static void phy_mgr_initialize(struct socfpga_sdrseq *seq)
{
u32 ratio;
@@ -132,15 +111,17 @@
writel(0, &phy_mgr_cfg->cal_debug_info);
/* Init params only if we do NOT skip calibration. */
- if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL)
+ if ((seq->dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL)
return;
- ratio = rwcfg->mem_dq_per_read_dqs /
- rwcfg->mem_virtual_groups_per_read_dqs;
- param->read_correct_mask_vg = (1 << ratio) - 1;
- param->write_correct_mask_vg = (1 << ratio) - 1;
- param->read_correct_mask = (1 << rwcfg->mem_dq_per_read_dqs) - 1;
- param->write_correct_mask = (1 << rwcfg->mem_dq_per_write_dqs) - 1;
+ ratio = seq->rwcfg->mem_dq_per_read_dqs /
+ seq->rwcfg->mem_virtual_groups_per_read_dqs;
+ seq->param.read_correct_mask_vg = (1 << ratio) - 1;
+ seq->param.write_correct_mask_vg = (1 << ratio) - 1;
+ seq->param.read_correct_mask = (1 << seq->rwcfg->mem_dq_per_read_dqs)
+ - 1;
+ seq->param.write_correct_mask = (1 << seq->rwcfg->mem_dq_per_write_dqs)
+ - 1;
}
/**
@@ -150,7 +131,8 @@
*
* Set Rank and ODT mask (On-Die Termination).
*/
-static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode)
+static void set_rank_and_odt_mask(struct socfpga_sdrseq *seq,
+ const u32 rank, const u32 odt_mode)
{
u32 odt_mask_0 = 0;
u32 odt_mask_1 = 0;
@@ -160,14 +142,14 @@
odt_mask_0 = 0x0;
odt_mask_1 = 0x0;
} else { /* RW_MGR_ODT_MODE_READ_WRITE */
- switch (rwcfg->mem_number_of_ranks) {
+ switch (seq->rwcfg->mem_number_of_ranks) {
case 1: /* 1 Rank */
/* Read: ODT = 0 ; Write: ODT = 1 */
odt_mask_0 = 0x0;
odt_mask_1 = 0x1;
break;
case 2: /* 2 Ranks */
- if (rwcfg->mem_number_of_cs_per_dimm == 1) {
+ if (seq->rwcfg->mem_number_of_cs_per_dimm == 1) {
/*
* - Dual-Slot , Single-Rank (1 CS per DIMM)
* OR
@@ -307,16 +289,18 @@
scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
}
-static void scc_mgr_set_dqs_io_in_delay(u32 delay)
-{
- scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs,
- delay);
-}
-
-static void scc_mgr_set_dm_in_delay(u32 dm, u32 delay)
+static void scc_mgr_set_dqs_io_in_delay(struct socfpga_sdrseq *seq,
+ u32 delay)
{
scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET,
- rwcfg->mem_dq_per_write_dqs + 1 + dm,
+ seq->rwcfg->mem_dq_per_write_dqs, delay);
+}
+
+static void scc_mgr_set_dm_in_delay(struct socfpga_sdrseq *seq, u32 dm,
+ u32 delay)
+{
+ scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET,
+ seq->rwcfg->mem_dq_per_write_dqs + 1 + dm,
delay);
}
@@ -325,16 +309,18 @@
scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay);
}
-static void scc_mgr_set_dqs_out1_delay(u32 delay)
-{
- scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs,
- delay);
-}
-
-static void scc_mgr_set_dm_out1_delay(u32 dm, u32 delay)
+static void scc_mgr_set_dqs_out1_delay(struct socfpga_sdrseq *seq,
+ u32 delay)
{
scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
- rwcfg->mem_dq_per_write_dqs + 1 + dm,
+ seq->rwcfg->mem_dq_per_write_dqs, delay);
+}
+
+static void scc_mgr_set_dm_out1_delay(struct socfpga_sdrseq *seq, u32 dm,
+ u32 delay)
+{
+ scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
+ seq->rwcfg->mem_dq_per_write_dqs + 1 + dm,
delay);
}
@@ -372,12 +358,13 @@
* This function sets the SCC Manager (Scan Chain Control Manager) register
* and optionally triggers the SCC update for all ranks.
*/
-static void scc_mgr_set_all_ranks(const u32 off, const u32 grp, const u32 val,
+static void scc_mgr_set_all_ranks(struct socfpga_sdrseq *seq,
+ const u32 off, const u32 grp, const u32 val,
const int update)
{
u32 r;
- for (r = 0; r < rwcfg->mem_number_of_ranks;
+ for (r = 0; r < seq->rwcfg->mem_number_of_ranks;
r += NUM_RANKS_PER_SHADOW_REG) {
scc_mgr_set(off, grp, val);
@@ -388,7 +375,8 @@
}
}
-static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase)
+static void scc_mgr_set_dqs_en_phase_all_ranks(struct socfpga_sdrseq *seq,
+ u32 read_group, u32 phase)
{
/*
* USER although the h/w doesn't support different phases per
@@ -398,12 +386,12 @@
* for efficiency, the scan chain update should occur only
* once to sr0.
*/
- scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_PHASE_OFFSET,
+ scc_mgr_set_all_ranks(seq, SCC_MGR_DQS_EN_PHASE_OFFSET,
read_group, phase, 0);
}
-static void scc_mgr_set_dqdqs_output_phase_all_ranks(u32 write_group,
- u32 phase)
+static void scc_mgr_set_dqdqs_output_phase_all_ranks(struct socfpga_sdrseq *seq,
+ u32 write_group, u32 phase)
{
/*
* USER although the h/w doesn't support different phases per
@@ -413,12 +401,12 @@
* for efficiency, the scan chain update should occur only
* once to sr0.
*/
- scc_mgr_set_all_ranks(SCC_MGR_DQDQS_OUT_PHASE_OFFSET,
+ scc_mgr_set_all_ranks(seq, SCC_MGR_DQDQS_OUT_PHASE_OFFSET,
write_group, phase, 0);
}
-static void scc_mgr_set_dqs_en_delay_all_ranks(u32 read_group,
- u32 delay)
+static void scc_mgr_set_dqs_en_delay_all_ranks(struct socfpga_sdrseq *seq,
+ u32 read_group, u32 delay)
{
/*
* In shadow register mode, the T11 settings are stored in
@@ -428,7 +416,7 @@
* select_shadow_regs_for_update with update_scan_chains
* set to 0.
*/
- scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET,
+ scc_mgr_set_all_ranks(seq, SCC_MGR_DQS_EN_DELAY_OFFSET,
read_group, delay, 1);
}
@@ -439,10 +427,11 @@
*
* This function sets the OCT output delay in SCC manager.
*/
-static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay)
+static void scc_mgr_set_oct_out1_delay(struct socfpga_sdrseq *seq,
+ const u32 write_group, const u32 delay)
{
- const int ratio = rwcfg->mem_if_read_dqs_width /
- rwcfg->mem_if_write_dqs_width;
+ const int ratio = seq->rwcfg->mem_if_read_dqs_width /
+ seq->rwcfg->mem_if_write_dqs_width;
const int base = write_group * ratio;
int i;
/*
@@ -490,7 +479,7 @@
*
* Zero all DQS config.
*/
-static void scc_mgr_zero_all(void)
+static void scc_mgr_zero_all(struct socfpga_sdrseq *seq)
{
int i, r;
@@ -498,23 +487,26 @@
* USER Zero all DQS config settings, across all groups and all
* shadow registers
*/
- for (r = 0; r < rwcfg->mem_number_of_ranks;
+ for (r = 0; r < seq->rwcfg->mem_number_of_ranks;
r += NUM_RANKS_PER_SHADOW_REG) {
- for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) {
+ for (i = 0; i < seq->rwcfg->mem_if_read_dqs_width; i++) {
/*
* The phases actually don't exist on a per-rank basis,
* but there's no harm updating them several times, so
* let's keep the code simple.
*/
- scc_mgr_set_dqs_bus_in_delay(i, iocfg->dqs_in_reserve);
+ scc_mgr_set_dqs_bus_in_delay(i,
+ seq->iocfg->dqs_in_reserve
+ );
scc_mgr_set_dqs_en_phase(i, 0);
scc_mgr_set_dqs_en_delay(i, 0);
}
- for (i = 0; i < rwcfg->mem_if_write_dqs_width; i++) {
+ for (i = 0; i < seq->rwcfg->mem_if_write_dqs_width; i++) {
scc_mgr_set_dqdqs_output_phase(i, 0);
/* Arria V/Cyclone V don't have out2. */
- scc_mgr_set_oct_out1_delay(i, iocfg->dqs_out_reserve);
+ scc_mgr_set_oct_out1_delay(seq, i,
+ seq->iocfg->dqs_out_reserve);
}
}
@@ -551,10 +543,11 @@
*
* Load DQS settings for Write Group, do not trigger SCC update.
*/
-static void scc_mgr_load_dqs_for_write_group(const u32 write_group)
+static void scc_mgr_load_dqs_for_write_group(struct socfpga_sdrseq *seq,
+ const u32 write_group)
{
- const int ratio = rwcfg->mem_if_read_dqs_width /
- rwcfg->mem_if_write_dqs_width;
+ const int ratio = seq->rwcfg->mem_if_read_dqs_width /
+ seq->rwcfg->mem_if_write_dqs_width;
const int base = write_group * ratio;
int i;
/*
@@ -573,14 +566,15 @@
*
* Zero DQ, DM, DQS and OCT configs for a group.
*/
-static void scc_mgr_zero_group(const u32 write_group, const int out_only)
+static void scc_mgr_zero_group(struct socfpga_sdrseq *seq,
+ const u32 write_group, const int out_only)
{
int i, r;
- for (r = 0; r < rwcfg->mem_number_of_ranks;
+ for (r = 0; r < seq->rwcfg->mem_number_of_ranks;
r += NUM_RANKS_PER_SHADOW_REG) {
/* Zero all DQ config settings. */
- for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) {
+ for (i = 0; i < seq->rwcfg->mem_dq_per_write_dqs; i++) {
scc_mgr_set_dq_out1_delay(i, 0);
if (!out_only)
scc_mgr_set_dq_in_delay(i, 0);
@@ -592,8 +586,8 @@
/* Zero all DM config settings. */
for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
if (!out_only)
- scc_mgr_set_dm_in_delay(i, 0);
- scc_mgr_set_dm_out1_delay(i, 0);
+ scc_mgr_set_dm_in_delay(seq, i, 0);
+ scc_mgr_set_dm_out1_delay(seq, i, 0);
}
/* Multicast to all DM enables. */
@@ -601,12 +595,13 @@
/* Zero all DQS IO settings. */
if (!out_only)
- scc_mgr_set_dqs_io_in_delay(0);
+ scc_mgr_set_dqs_io_in_delay(seq, 0);
/* Arria V/Cyclone V don't have out2. */
- scc_mgr_set_dqs_out1_delay(iocfg->dqs_out_reserve);
- scc_mgr_set_oct_out1_delay(write_group, iocfg->dqs_out_reserve);
- scc_mgr_load_dqs_for_write_group(write_group);
+ scc_mgr_set_dqs_out1_delay(seq, seq->iocfg->dqs_out_reserve);
+ scc_mgr_set_oct_out1_delay(seq, write_group,
+ seq->iocfg->dqs_out_reserve);
+ scc_mgr_load_dqs_for_write_group(seq, write_group);
/* Multicast to all DQS IO enables (only 1 in total). */
writel(0, &sdr_scc_mgr->dqs_io_ena);
@@ -620,69 +615,76 @@
* apply and load a particular input delay for the DQ pins in a group
* group_bgn is the index of the first dq pin (in the write group)
*/
-static void scc_mgr_apply_group_dq_in_delay(u32 group_bgn, u32 delay)
+static void scc_mgr_apply_group_dq_in_delay(struct socfpga_sdrseq *seq,
+ u32 group_bgn, u32 delay)
{
u32 i, p;
- for (i = 0, p = group_bgn; i < rwcfg->mem_dq_per_read_dqs; i++, p++) {
+ for (i = 0, p = group_bgn; i < seq->rwcfg->mem_dq_per_read_dqs;
+ i++, p++) {
scc_mgr_set_dq_in_delay(p, delay);
scc_mgr_load_dq(p);
}
}
/**
- * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group
+ * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the
+ * DQ pins in a group
* @delay: Delay value
*
* Apply and load a particular output delay for the DQ pins in a group.
*/
-static void scc_mgr_apply_group_dq_out1_delay(const u32 delay)
+static void scc_mgr_apply_group_dq_out1_delay(struct socfpga_sdrseq *seq,
+ const u32 delay)
{
int i;
- for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) {
+ for (i = 0; i < seq->rwcfg->mem_dq_per_write_dqs; i++) {
scc_mgr_set_dq_out1_delay(i, delay);
scc_mgr_load_dq(i);
}
}
/* apply and load a particular output delay for the DM pins in a group */
-static void scc_mgr_apply_group_dm_out1_delay(u32 delay1)
+static void scc_mgr_apply_group_dm_out1_delay(struct socfpga_sdrseq *seq,
+ u32 delay1)
{
u32 i;
for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
- scc_mgr_set_dm_out1_delay(i, delay1);
+ scc_mgr_set_dm_out1_delay(seq, i, delay1);
scc_mgr_load_dm(i);
}
}
/* apply and load delay on both DQS and OCT out1 */
-static void scc_mgr_apply_group_dqs_io_and_oct_out1(u32 write_group,
- u32 delay)
+static void scc_mgr_apply_group_dqs_io_and_oct_out1(struct socfpga_sdrseq *seq,
+ u32 write_group, u32 delay)
{
- scc_mgr_set_dqs_out1_delay(delay);
+ scc_mgr_set_dqs_out1_delay(seq, delay);
scc_mgr_load_dqs_io();
- scc_mgr_set_oct_out1_delay(write_group, delay);
- scc_mgr_load_dqs_for_write_group(write_group);
+ scc_mgr_set_oct_out1_delay(seq, write_group, delay);
+ scc_mgr_load_dqs_for_write_group(seq, write_group);
}
/**
- * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side: DQ, DM, DQS, OCT
+ * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output
+ * side: DQ, DM, DQS, OCT
* @write_group: Write group
* @delay: Delay value
*
* Apply a delay to the entire output side: DQ, DM, DQS, OCT.
*/
-static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,
+static void scc_mgr_apply_group_all_out_delay_add(struct socfpga_sdrseq *seq,
+ const u32 write_group,
const u32 delay)
{
u32 i, new_delay;
/* DQ shift */
- for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++)
+ for (i = 0; i < seq->rwcfg->mem_dq_per_write_dqs; i++)
scc_mgr_load_dq(i);
/* DM shift */
@@ -691,49 +693,51 @@
/* DQS shift */
new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay;
- if (new_delay > iocfg->io_out2_delay_max) {
+ if (new_delay > seq->iocfg->io_out2_delay_max) {
debug_cond(DLEVEL >= 1,
"%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
__func__, __LINE__, write_group, delay, new_delay,
- iocfg->io_out2_delay_max,
- new_delay - iocfg->io_out2_delay_max);
- new_delay -= iocfg->io_out2_delay_max;
- scc_mgr_set_dqs_out1_delay(new_delay);
+ seq->iocfg->io_out2_delay_max,
+ new_delay - seq->iocfg->io_out2_delay_max);
+ new_delay -= seq->iocfg->io_out2_delay_max;
+ scc_mgr_set_dqs_out1_delay(seq, new_delay);
}
scc_mgr_load_dqs_io();
/* OCT shift */
new_delay = READ_SCC_OCT_OUT2_DELAY + delay;
- if (new_delay > iocfg->io_out2_delay_max) {
+ if (new_delay > seq->iocfg->io_out2_delay_max) {
debug_cond(DLEVEL >= 1,
"%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
__func__, __LINE__, write_group, delay,
- new_delay, iocfg->io_out2_delay_max,
- new_delay - iocfg->io_out2_delay_max);
- new_delay -= iocfg->io_out2_delay_max;
- scc_mgr_set_oct_out1_delay(write_group, new_delay);
+ new_delay, seq->iocfg->io_out2_delay_max,
+ new_delay - seq->iocfg->io_out2_delay_max);
+ new_delay -= seq->iocfg->io_out2_delay_max;
+ scc_mgr_set_oct_out1_delay(seq, write_group, new_delay);
}
- scc_mgr_load_dqs_for_write_group(write_group);
+ scc_mgr_load_dqs_for_write_group(seq, write_group);
}
/**
- * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side to all ranks
+ * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output
+ * side to all ranks
* @write_group: Write group
* @delay: Delay value
*
* Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks.
*/
static void
-scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group,
+scc_mgr_apply_group_all_out_delay_add_all_ranks(struct socfpga_sdrseq *seq,
+ const u32 write_group,
const u32 delay)
{
int r;
- for (r = 0; r < rwcfg->mem_number_of_ranks;
+ for (r = 0; r < seq->rwcfg->mem_number_of_ranks;
r += NUM_RANKS_PER_SHADOW_REG) {
- scc_mgr_apply_group_all_out_delay_add(write_group, delay);
+ scc_mgr_apply_group_all_out_delay_add(seq, write_group, delay);
writel(0, &sdr_scc_mgr->update);
}
}
@@ -744,7 +748,7 @@
* Optimization used to recover some slots in ddr3 inst_rom could be
* applied to other protocols if we wanted to
*/
-static void set_jump_as_return(void)
+static void set_jump_as_return(struct socfpga_sdrseq *seq)
{
/*
* To save space, we replace return with jump to special shared
@@ -752,7 +756,7 @@
* we always jump.
*/
writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
- writel(rwcfg->rreturn, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
+ writel(seq->rwcfg->rreturn, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
}
/**
@@ -761,7 +765,8 @@
*
* Delay for N memory clocks.
*/
-static void delay_for_n_mem_clocks(const u32 clocks)
+static void delay_for_n_mem_clocks(struct socfpga_sdrseq *seq,
+ const u32 clocks)
{
u32 afi_clocks;
u16 c_loop;
@@ -771,7 +776,7 @@
debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
/* Scale (rounding up) to get afi clocks. */
- afi_clocks = DIV_ROUND_UP(clocks, misccfg->afi_rate_ratio);
+ afi_clocks = DIV_ROUND_UP(clocks, seq->misccfg->afi_rate_ratio);
if (afi_clocks) /* Temporary underflow protection */
afi_clocks--;
@@ -807,10 +812,10 @@
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
&sdr_rw_load_mgr_regs->load_cntr1);
- writel(rwcfg->idle_loop1,
+ writel(seq->rwcfg->idle_loop1,
&sdr_rw_load_jump_mgr_regs->load_jump_add1);
- writel(rwcfg->idle_loop1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ writel(seq->rwcfg->idle_loop1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
RW_MGR_RUN_SINGLE_GROUP_OFFSET);
} else {
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
@@ -819,14 +824,14 @@
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
&sdr_rw_load_mgr_regs->load_cntr1);
- writel(rwcfg->idle_loop2,
+ writel(seq->rwcfg->idle_loop2,
&sdr_rw_load_jump_mgr_regs->load_jump_add0);
- writel(rwcfg->idle_loop2,
+ writel(seq->rwcfg->idle_loop2,
&sdr_rw_load_jump_mgr_regs->load_jump_add1);
do {
- writel(rwcfg->idle_loop2,
+ writel(seq->rwcfg->idle_loop2,
SDR_PHYGRP_RWMGRGRP_ADDRESS |
RW_MGR_RUN_SINGLE_GROUP_OFFSET);
} while (c_loop-- != 0);
@@ -843,7 +848,8 @@
*
* Load instruction registers.
*/
-static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump)
+static void rw_mgr_mem_init_load_regs(struct socfpga_sdrseq *seq,
+ u32 cntr0, u32 cntr1, u32 cntr2, u32 jump)
{
u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
RW_MGR_RUN_SINGLE_GROUP_OFFSET;
@@ -873,58 +879,59 @@
*
* Load user calibration values and optionally precharge the banks.
*/
-static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2,
+static void rw_mgr_mem_load_user(struct socfpga_sdrseq *seq,
+ const u32 fin1, const u32 fin2,
const int precharge)
{
u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
RW_MGR_RUN_SINGLE_GROUP_OFFSET;
u32 r;
- for (r = 0; r < rwcfg->mem_number_of_ranks; r++) {
+ for (r = 0; r < seq->rwcfg->mem_number_of_ranks; r++) {
/* set rank */
- set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
+ set_rank_and_odt_mask(seq, r, RW_MGR_ODT_MODE_OFF);
/* precharge all banks ... */
if (precharge)
- writel(rwcfg->precharge_all, grpaddr);
+ writel(seq->rwcfg->precharge_all, grpaddr);
/*
* USER Use Mirror-ed commands for odd ranks if address
* mirrorring is on
*/
- if ((rwcfg->mem_address_mirroring >> r) & 0x1) {
- set_jump_as_return();
- writel(rwcfg->mrs2_mirr, grpaddr);
- delay_for_n_mem_clocks(4);
- set_jump_as_return();
- writel(rwcfg->mrs3_mirr, grpaddr);
- delay_for_n_mem_clocks(4);
- set_jump_as_return();
- writel(rwcfg->mrs1_mirr, grpaddr);
- delay_for_n_mem_clocks(4);
- set_jump_as_return();
+ if ((seq->rwcfg->mem_address_mirroring >> r) & 0x1) {
+ set_jump_as_return(seq);
+ writel(seq->rwcfg->mrs2_mirr, grpaddr);
+ delay_for_n_mem_clocks(seq, 4);
+ set_jump_as_return(seq);
+ writel(seq->rwcfg->mrs3_mirr, grpaddr);
+ delay_for_n_mem_clocks(seq, 4);
+ set_jump_as_return(seq);
+ writel(seq->rwcfg->mrs1_mirr, grpaddr);
+ delay_for_n_mem_clocks(seq, 4);
+ set_jump_as_return(seq);
writel(fin1, grpaddr);
} else {
- set_jump_as_return();
- writel(rwcfg->mrs2, grpaddr);
- delay_for_n_mem_clocks(4);
- set_jump_as_return();
- writel(rwcfg->mrs3, grpaddr);
- delay_for_n_mem_clocks(4);
- set_jump_as_return();
- writel(rwcfg->mrs1, grpaddr);
- set_jump_as_return();
+ set_jump_as_return(seq);
+ writel(seq->rwcfg->mrs2, grpaddr);
+ delay_for_n_mem_clocks(seq, 4);
+ set_jump_as_return(seq);
+ writel(seq->rwcfg->mrs3, grpaddr);
+ delay_for_n_mem_clocks(seq, 4);
+ set_jump_as_return(seq);
+ writel(seq->rwcfg->mrs1, grpaddr);
+ set_jump_as_return(seq);
writel(fin2, grpaddr);
}
if (precharge)
continue;
- set_jump_as_return();
- writel(rwcfg->zqcl, grpaddr);
+ set_jump_as_return(seq);
+ writel(seq->rwcfg->zqcl, grpaddr);
/* tZQinit = tDLLK = 512 ck cycles */
- delay_for_n_mem_clocks(512);
+ delay_for_n_mem_clocks(seq, 512);
}
}
@@ -933,7 +940,7 @@
*
* Initialize RW Manager.
*/
-static void rw_mgr_mem_initialize(void)
+static void rw_mgr_mem_initialize(struct socfpga_sdrseq *seq)
{
debug("%s:%d\n", __func__, __LINE__);
@@ -964,10 +971,10 @@
* One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
* b = 6A
*/
- rw_mgr_mem_init_load_regs(misccfg->tinit_cntr0_val,
- misccfg->tinit_cntr1_val,
- misccfg->tinit_cntr2_val,
- rwcfg->init_reset_0_cke_0);
+ rw_mgr_mem_init_load_regs(seq, seq->misccfg->tinit_cntr0_val,
+ seq->misccfg->tinit_cntr1_val,
+ seq->misccfg->tinit_cntr2_val,
+ seq->rwcfg->init_reset_0_cke_0);
/* Indicate that memory is stable. */
writel(1, &phy_mgr_cfg->reset_mem_stbl);
@@ -986,18 +993,18 @@
* One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
* b = FF
*/
- rw_mgr_mem_init_load_regs(misccfg->treset_cntr0_val,
- misccfg->treset_cntr1_val,
- misccfg->treset_cntr2_val,
- rwcfg->init_reset_1_cke_0);
+ rw_mgr_mem_init_load_regs(seq, seq->misccfg->treset_cntr0_val,
+ seq->misccfg->treset_cntr1_val,
+ seq->misccfg->treset_cntr2_val,
+ seq->rwcfg->init_reset_1_cke_0);
/* Bring up clock enable. */
/* tXRP < 250 ck cycles */
- delay_for_n_mem_clocks(250);
+ delay_for_n_mem_clocks(seq, 250);
- rw_mgr_mem_load_user(rwcfg->mrs0_dll_reset_mirr, rwcfg->mrs0_dll_reset,
- 0);
+ rw_mgr_mem_load_user(seq, seq->rwcfg->mrs0_dll_reset_mirr,
+ seq->rwcfg->mrs0_dll_reset, 0);
}
/**
@@ -1006,9 +1013,10 @@
* At the end of calibration we have to program the user settings in
* and hand off the memory to the user.
*/
-static void rw_mgr_mem_handoff(void)
+static void rw_mgr_mem_handoff(struct socfpga_sdrseq *seq)
{
- rw_mgr_mem_load_user(rwcfg->mrs0_user_mirr, rwcfg->mrs0_user, 1);
+ rw_mgr_mem_load_user(seq, seq->rwcfg->mrs0_user_mirr,
+ seq->rwcfg->mrs0_user, 1);
/*
* Need to wait tMOD (12CK or 15ns) time before issuing other
* commands, but we will have plenty of NIOS cycles before actual
@@ -1024,12 +1032,12 @@
* Issue write test command. Two variants are provided, one that just tests
* a write pattern and another that tests datamask functionality.
*/
-static void rw_mgr_mem_calibrate_write_test_issue(u32 group,
- u32 test_dm)
+static void rw_mgr_mem_calibrate_write_test_issue(struct socfpga_sdrseq *seq,
+ u32 group, u32 test_dm)
{
const u32 quick_write_mode =
(STATIC_CALIB_STEPS & CALIB_SKIP_WRITES) &&
- misccfg->enable_super_quick_calibration;
+ seq->misccfg->enable_super_quick_calibration;
u32 mcc_instruction;
u32 rw_wl_nop_cycles;
@@ -1059,7 +1067,7 @@
* one counter left to issue this command in "multiple-group" mode
*/
- rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
+ rw_wl_nop_cycles = seq->gbl.rw_wl_nop_cycles;
if (rw_wl_nop_cycles == -1) {
/*
@@ -1072,16 +1080,16 @@
/* CNTR 3 - Not used */
if (test_dm) {
- mcc_instruction = rwcfg->lfsr_wr_rd_dm_bank_0_wl_1;
- writel(rwcfg->lfsr_wr_rd_dm_bank_0_data,
+ mcc_instruction = seq->rwcfg->lfsr_wr_rd_dm_bank_0_wl_1;
+ writel(seq->rwcfg->lfsr_wr_rd_dm_bank_0_data,
&sdr_rw_load_jump_mgr_regs->load_jump_add2);
- writel(rwcfg->lfsr_wr_rd_dm_bank_0_nop,
+ writel(seq->rwcfg->lfsr_wr_rd_dm_bank_0_nop,
&sdr_rw_load_jump_mgr_regs->load_jump_add3);
} else {
- mcc_instruction = rwcfg->lfsr_wr_rd_bank_0_wl_1;
- writel(rwcfg->lfsr_wr_rd_bank_0_data,
+ mcc_instruction = seq->rwcfg->lfsr_wr_rd_bank_0_wl_1;
+ writel(seq->rwcfg->lfsr_wr_rd_bank_0_data,
&sdr_rw_load_jump_mgr_regs->load_jump_add2);
- writel(rwcfg->lfsr_wr_rd_bank_0_nop,
+ writel(seq->rwcfg->lfsr_wr_rd_bank_0_nop,
&sdr_rw_load_jump_mgr_regs->load_jump_add3);
}
} else if (rw_wl_nop_cycles == 0) {
@@ -1094,12 +1102,12 @@
/* CNTR 3 - Not used */
if (test_dm) {
- mcc_instruction = rwcfg->lfsr_wr_rd_dm_bank_0;
- writel(rwcfg->lfsr_wr_rd_dm_bank_0_dqs,
+ mcc_instruction = seq->rwcfg->lfsr_wr_rd_dm_bank_0;
+ writel(seq->rwcfg->lfsr_wr_rd_dm_bank_0_dqs,
&sdr_rw_load_jump_mgr_regs->load_jump_add2);
} else {
- mcc_instruction = rwcfg->lfsr_wr_rd_bank_0;
- writel(rwcfg->lfsr_wr_rd_bank_0_dqs,
+ mcc_instruction = seq->rwcfg->lfsr_wr_rd_bank_0;
+ writel(seq->rwcfg->lfsr_wr_rd_bank_0_dqs,
&sdr_rw_load_jump_mgr_regs->load_jump_add2);
}
} else {
@@ -1117,12 +1125,12 @@
*/
writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
if (test_dm) {
- mcc_instruction = rwcfg->lfsr_wr_rd_dm_bank_0;
- writel(rwcfg->lfsr_wr_rd_dm_bank_0_nop,
+ mcc_instruction = seq->rwcfg->lfsr_wr_rd_dm_bank_0;
+ writel(seq->rwcfg->lfsr_wr_rd_dm_bank_0_nop,
&sdr_rw_load_jump_mgr_regs->load_jump_add3);
} else {
- mcc_instruction = rwcfg->lfsr_wr_rd_bank_0;
- writel(rwcfg->lfsr_wr_rd_bank_0_nop,
+ mcc_instruction = seq->rwcfg->lfsr_wr_rd_bank_0;
+ writel(seq->rwcfg->lfsr_wr_rd_bank_0_nop,
&sdr_rw_load_jump_mgr_regs->load_jump_add3);
}
}
@@ -1144,10 +1152,10 @@
writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
if (test_dm) {
- writel(rwcfg->lfsr_wr_rd_dm_bank_0_wait,
+ writel(seq->rwcfg->lfsr_wr_rd_dm_bank_0_wait,
&sdr_rw_load_jump_mgr_regs->load_jump_add1);
} else {
- writel(rwcfg->lfsr_wr_rd_bank_0_wait,
+ writel(seq->rwcfg->lfsr_wr_rd_bank_0_wait,
&sdr_rw_load_jump_mgr_regs->load_jump_add1);
}
@@ -1157,7 +1165,8 @@
}
/**
- * rw_mgr_mem_calibrate_write_test() - Test writes, check for single/multiple pass
+ * rw_mgr_mem_calibrate_write_test() - Test writes, check for single/multiple
+ * pass
* @rank_bgn: Rank number
* @write_group: Write Group
* @use_dm: Use DM
@@ -1168,36 +1177,38 @@
* Test writes, can check for a single bit pass or multiple bit pass.
*/
static int
-rw_mgr_mem_calibrate_write_test(const u32 rank_bgn, const u32 write_group,
+rw_mgr_mem_calibrate_write_test(struct socfpga_sdrseq *seq,
+ const u32 rank_bgn, const u32 write_group,
const u32 use_dm, const u32 all_correct,
u32 *bit_chk, const u32 all_ranks)
{
const u32 rank_end = all_ranks ?
- rwcfg->mem_number_of_ranks :
+ seq->rwcfg->mem_number_of_ranks :
(rank_bgn + NUM_RANKS_PER_SHADOW_REG);
- const u32 shift_ratio = rwcfg->mem_dq_per_write_dqs /
- rwcfg->mem_virtual_groups_per_write_dqs;
- const u32 correct_mask_vg = param->write_correct_mask_vg;
+ const u32 shift_ratio = seq->rwcfg->mem_dq_per_write_dqs /
+ seq->rwcfg->mem_virtual_groups_per_write_dqs;
+ const u32 correct_mask_vg = seq->param.write_correct_mask_vg;
- u32 tmp_bit_chk, base_rw_mgr;
+ u32 tmp_bit_chk, base_rw_mgr, group;
int vg, r;
- *bit_chk = param->write_correct_mask;
+ *bit_chk = seq->param.write_correct_mask;
for (r = rank_bgn; r < rank_end; r++) {
/* Set rank */
- set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
+ set_rank_and_odt_mask(seq, r, RW_MGR_ODT_MODE_READ_WRITE);
tmp_bit_chk = 0;
- for (vg = rwcfg->mem_virtual_groups_per_write_dqs - 1;
+ for (vg = seq->rwcfg->mem_virtual_groups_per_write_dqs - 1;
vg >= 0; vg--) {
/* Reset the FIFOs to get pointers to known state. */
writel(0, &phy_mgr_cmd->fifo_reset);
- rw_mgr_mem_calibrate_write_test_issue(
- write_group *
- rwcfg->mem_virtual_groups_per_write_dqs + vg,
- use_dm);
+ group = write_group *
+ seq->rwcfg->mem_virtual_groups_per_write_dqs
+ + vg;
+ rw_mgr_mem_calibrate_write_test_issue(seq, group,
+ use_dm);
base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
tmp_bit_chk <<= shift_ratio;
@@ -1207,14 +1218,14 @@
*bit_chk &= tmp_bit_chk;
}
- set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
+ set_rank_and_odt_mask(seq, 0, RW_MGR_ODT_MODE_OFF);
if (all_correct) {
debug_cond(DLEVEL >= 2,
"write_test(%u,%u,ALL) : %u == %u => %i\n",
write_group, use_dm, *bit_chk,
- param->write_correct_mask,
- *bit_chk == param->write_correct_mask);
- return *bit_chk == param->write_correct_mask;
+ seq->param.write_correct_mask,
+ *bit_chk == seq->param.write_correct_mask);
+ return *bit_chk == seq->param.write_correct_mask;
} else {
debug_cond(DLEVEL >= 2,
"write_test(%u,%u,ONE) : %u != %i => %i\n",
@@ -1233,47 +1244,49 @@
* read test to ensure memory works.
*/
static int
-rw_mgr_mem_calibrate_read_test_patterns(const u32 rank_bgn, const u32 group,
+rw_mgr_mem_calibrate_read_test_patterns(struct socfpga_sdrseq *seq,
+ const u32 rank_bgn, const u32 group,
const u32 all_ranks)
{
const u32 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
RW_MGR_RUN_SINGLE_GROUP_OFFSET;
const u32 addr_offset =
- (group * rwcfg->mem_virtual_groups_per_read_dqs) << 2;
+ (group * seq->rwcfg->mem_virtual_groups_per_read_dqs)
+ << 2;
const u32 rank_end = all_ranks ?
- rwcfg->mem_number_of_ranks :
+ seq->rwcfg->mem_number_of_ranks :
(rank_bgn + NUM_RANKS_PER_SHADOW_REG);
- const u32 shift_ratio = rwcfg->mem_dq_per_read_dqs /
- rwcfg->mem_virtual_groups_per_read_dqs;
- const u32 correct_mask_vg = param->read_correct_mask_vg;
+ const u32 shift_ratio = seq->rwcfg->mem_dq_per_read_dqs /
+ seq->rwcfg->mem_virtual_groups_per_read_dqs;
+ const u32 correct_mask_vg = seq->param.read_correct_mask_vg;
u32 tmp_bit_chk, base_rw_mgr, bit_chk;
int vg, r;
int ret = 0;
- bit_chk = param->read_correct_mask;
+ bit_chk = seq->param.read_correct_mask;
for (r = rank_bgn; r < rank_end; r++) {
/* Set rank */
- set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
+ set_rank_and_odt_mask(seq, r, RW_MGR_ODT_MODE_READ_WRITE);
/* Load up a constant bursts of read commands */
writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
- writel(rwcfg->guaranteed_read,
+ writel(seq->rwcfg->guaranteed_read,
&sdr_rw_load_jump_mgr_regs->load_jump_add0);
writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
- writel(rwcfg->guaranteed_read_cont,
+ writel(seq->rwcfg->guaranteed_read_cont,
&sdr_rw_load_jump_mgr_regs->load_jump_add1);
tmp_bit_chk = 0;
- for (vg = rwcfg->mem_virtual_groups_per_read_dqs - 1;
+ for (vg = seq->rwcfg->mem_virtual_groups_per_read_dqs - 1;
vg >= 0; vg--) {
/* Reset the FIFOs to get pointers to known state. */
writel(0, &phy_mgr_cmd->fifo_reset);
writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
RW_MGR_RESET_READ_DATAPATH_OFFSET);
- writel(rwcfg->guaranteed_read,
+ writel(seq->rwcfg->guaranteed_read,
addr + addr_offset + (vg << 2));
base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
@@ -1284,33 +1297,35 @@
bit_chk &= tmp_bit_chk;
}
- writel(rwcfg->clear_dqs_enable, addr + (group << 2));
+ writel(seq->rwcfg->clear_dqs_enable, addr + (group << 2));
- set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
+ set_rank_and_odt_mask(seq, 0, RW_MGR_ODT_MODE_OFF);
- if (bit_chk != param->read_correct_mask)
+ if (bit_chk != seq->param.read_correct_mask)
ret = -EIO;
debug_cond(DLEVEL >= 1,
"%s:%d test_load_patterns(%u,ALL) => (%u == %u) => %i\n",
__func__, __LINE__, group, bit_chk,
- param->read_correct_mask, ret);
+ seq->param.read_correct_mask, ret);
return ret;
}
/**
- * rw_mgr_mem_calibrate_read_load_patterns() - Load up the patterns for read test
+ * rw_mgr_mem_calibrate_read_load_patterns() - Load up the patterns for read
+ * test
* @rank_bgn: Rank number
* @all_ranks: Test all ranks
*
* Load up the patterns we are going to use during a read test.
*/
-static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn,
+static void rw_mgr_mem_calibrate_read_load_patterns(struct socfpga_sdrseq *seq,
+ const u32 rank_bgn,
const int all_ranks)
{
const u32 rank_end = all_ranks ?
- rwcfg->mem_number_of_ranks :
+ seq->rwcfg->mem_number_of_ranks :
(rank_bgn + NUM_RANKS_PER_SHADOW_REG);
u32 r;
@@ -1318,34 +1333,35 @@
for (r = rank_bgn; r < rank_end; r++) {
/* set rank */
- set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
+ set_rank_and_odt_mask(seq, r, RW_MGR_ODT_MODE_READ_WRITE);
/* Load up a constant bursts */
writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
- writel(rwcfg->guaranteed_write_wait0,
+ writel(seq->rwcfg->guaranteed_write_wait0,
&sdr_rw_load_jump_mgr_regs->load_jump_add0);
writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
- writel(rwcfg->guaranteed_write_wait1,
+ writel(seq->rwcfg->guaranteed_write_wait1,
&sdr_rw_load_jump_mgr_regs->load_jump_add1);
writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
- writel(rwcfg->guaranteed_write_wait2,
+ writel(seq->rwcfg->guaranteed_write_wait2,
&sdr_rw_load_jump_mgr_regs->load_jump_add2);
writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
- writel(rwcfg->guaranteed_write_wait3,
+ writel(seq->rwcfg->guaranteed_write_wait3,
&sdr_rw_load_jump_mgr_regs->load_jump_add3);
- writel(rwcfg->guaranteed_write, SDR_PHYGRP_RWMGRGRP_ADDRESS |
- RW_MGR_RUN_SINGLE_GROUP_OFFSET);
+ writel(seq->rwcfg->guaranteed_write,
+ SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET);
}
- set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
+ set_rank_and_odt_mask(seq, 0, RW_MGR_ODT_MODE_OFF);
}
/**
@@ -1363,36 +1379,37 @@
* checks than the regular read test.
*/
static int
-rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group,
+rw_mgr_mem_calibrate_read_test(struct socfpga_sdrseq *seq,
+ const u32 rank_bgn, const u32 group,
const u32 num_tries, const u32 all_correct,
u32 *bit_chk,
const u32 all_groups, const u32 all_ranks)
{
- const u32 rank_end = all_ranks ? rwcfg->mem_number_of_ranks :
+ const u32 rank_end = all_ranks ? seq->rwcfg->mem_number_of_ranks :
(rank_bgn + NUM_RANKS_PER_SHADOW_REG);
const u32 quick_read_mode =
((STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS) &&
- misccfg->enable_super_quick_calibration);
- u32 correct_mask_vg = param->read_correct_mask_vg;
+ seq->misccfg->enable_super_quick_calibration);
+ u32 correct_mask_vg = seq->param.read_correct_mask_vg;
u32 tmp_bit_chk;
u32 base_rw_mgr;
u32 addr;
int r, vg, ret;
- *bit_chk = param->read_correct_mask;
+ *bit_chk = seq->param.read_correct_mask;
for (r = rank_bgn; r < rank_end; r++) {
/* set rank */
- set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
+ set_rank_and_odt_mask(seq, r, RW_MGR_ODT_MODE_READ_WRITE);
writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
- writel(rwcfg->read_b2b_wait1,
+ writel(seq->rwcfg->read_b2b_wait1,
&sdr_rw_load_jump_mgr_regs->load_jump_add1);
writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
- writel(rwcfg->read_b2b_wait2,
+ writel(seq->rwcfg->read_b2b_wait2,
&sdr_rw_load_jump_mgr_regs->load_jump_add2);
if (quick_read_mode)
@@ -1403,21 +1420,21 @@
else
writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
- writel(rwcfg->read_b2b,
+ writel(seq->rwcfg->read_b2b,
&sdr_rw_load_jump_mgr_regs->load_jump_add0);
if (all_groups)
- writel(rwcfg->mem_if_read_dqs_width *
- rwcfg->mem_virtual_groups_per_read_dqs - 1,
+ writel(seq->rwcfg->mem_if_read_dqs_width *
+ seq->rwcfg->mem_virtual_groups_per_read_dqs - 1,
&sdr_rw_load_mgr_regs->load_cntr3);
else
writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
- writel(rwcfg->read_b2b,
+ writel(seq->rwcfg->read_b2b,
&sdr_rw_load_jump_mgr_regs->load_jump_add3);
tmp_bit_chk = 0;
- for (vg = rwcfg->mem_virtual_groups_per_read_dqs - 1; vg >= 0;
- vg--) {
+ for (vg = seq->rwcfg->mem_virtual_groups_per_read_dqs - 1;
+ vg >= 0; vg--) {
/* Reset the FIFOs to get pointers to known state. */
writel(0, &phy_mgr_cmd->fifo_reset);
writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
@@ -1431,14 +1448,15 @@
RW_MGR_RUN_SINGLE_GROUP_OFFSET;
}
- writel(rwcfg->read_b2b, addr +
+ writel(seq->rwcfg->read_b2b, addr +
((group *
- rwcfg->mem_virtual_groups_per_read_dqs +
+ seq->rwcfg->mem_virtual_groups_per_read_dqs +
vg) << 2));
base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
- tmp_bit_chk <<= rwcfg->mem_dq_per_read_dqs /
- rwcfg->mem_virtual_groups_per_read_dqs;
+ tmp_bit_chk <<=
+ seq->rwcfg->mem_dq_per_read_dqs /
+ seq->rwcfg->mem_virtual_groups_per_read_dqs;
tmp_bit_chk |= correct_mask_vg & ~(base_rw_mgr);
}
@@ -1446,16 +1464,16 @@
}
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(rwcfg->clear_dqs_enable, addr + (group << 2));
+ writel(seq->rwcfg->clear_dqs_enable, addr + (group << 2));
- set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
+ set_rank_and_odt_mask(seq, 0, RW_MGR_ODT_MODE_OFF);
if (all_correct) {
- ret = (*bit_chk == param->read_correct_mask);
+ ret = (*bit_chk == seq->param.read_correct_mask);
debug_cond(DLEVEL >= 2,
"%s:%d read_test(%u,ALL,%u) => (%u == %u) => %i\n",
__func__, __LINE__, group, all_groups, *bit_chk,
- param->read_correct_mask, ret);
+ seq->param.read_correct_mask, ret);
} else {
ret = (*bit_chk != 0x00);
debug_cond(DLEVEL >= 2,
@@ -1477,13 +1495,15 @@
* Perform a READ test across all memory ranks.
*/
static int
-rw_mgr_mem_calibrate_read_test_all_ranks(const u32 grp, const u32 num_tries,
+rw_mgr_mem_calibrate_read_test_all_ranks(struct socfpga_sdrseq *seq,
+ const u32 grp, const u32 num_tries,
const u32 all_correct,
const u32 all_groups)
{
u32 bit_chk;
- return rw_mgr_mem_calibrate_read_test(0, grp, num_tries, all_correct,
- &bit_chk, all_groups, 1);
+ return rw_mgr_mem_calibrate_read_test(seq, 0, grp, num_tries,
+ all_correct, &bit_chk, all_groups,
+ 1);
}
/**
@@ -1503,11 +1523,11 @@
*
* Decrease VFIFO value.
*/
-static void rw_mgr_decr_vfifo(const u32 grp)
+static void rw_mgr_decr_vfifo(struct socfpga_sdrseq *seq, const u32 grp)
{
u32 i;
- for (i = 0; i < misccfg->read_valid_fifo_size - 1; i++)
+ for (i = 0; i < seq->misccfg->read_valid_fifo_size - 1; i++)
rw_mgr_incr_vfifo(grp);
}
@@ -1517,15 +1537,16 @@
*
* Push VFIFO until a failing read happens.
*/
-static int find_vfifo_failing_read(const u32 grp)
+static int find_vfifo_failing_read(struct socfpga_sdrseq *seq,
+ const u32 grp)
{
u32 v, ret, fail_cnt = 0;
- for (v = 0; v < misccfg->read_valid_fifo_size; v++) {
+ for (v = 0; v < seq->misccfg->read_valid_fifo_size; v++) {
debug_cond(DLEVEL >= 2, "%s:%d: vfifo %u\n",
__func__, __LINE__, v);
- ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
- PASS_ONE_BIT, 0);
+ ret = rw_mgr_mem_calibrate_read_test_all_ranks(seq, grp, 1,
+ PASS_ONE_BIT, 0);
if (!ret) {
fail_cnt++;
@@ -1553,21 +1574,22 @@
*
* Find working or non-working DQS enable phase setting.
*/
-static int sdr_find_phase_delay(int working, int delay, const u32 grp,
- u32 *work, const u32 work_inc, u32 *pd)
+static int sdr_find_phase_delay(struct socfpga_sdrseq *seq, int working,
+ int delay, const u32 grp, u32 *work,
+ const u32 work_inc, u32 *pd)
{
- const u32 max = delay ? iocfg->dqs_en_delay_max :
- iocfg->dqs_en_phase_max;
+ const u32 max = delay ? seq->iocfg->dqs_en_delay_max :
+ seq->iocfg->dqs_en_phase_max;
u32 ret;
for (; *pd <= max; (*pd)++) {
if (delay)
- scc_mgr_set_dqs_en_delay_all_ranks(grp, *pd);
+ scc_mgr_set_dqs_en_delay_all_ranks(seq, grp, *pd);
else
- scc_mgr_set_dqs_en_phase_all_ranks(grp, *pd);
+ scc_mgr_set_dqs_en_phase_all_ranks(seq, grp, *pd);
- ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
- PASS_ONE_BIT, 0);
+ ret = rw_mgr_mem_calibrate_read_test_all_ranks(seq, grp, 1,
+ PASS_ONE_BIT, 0);
if (!working)
ret = !ret;
@@ -1590,22 +1612,22 @@
*
* Find working or non-working DQS enable phase setting.
*/
-static int sdr_find_phase(int working, const u32 grp, u32 *work,
- u32 *i, u32 *p)
+static int sdr_find_phase(struct socfpga_sdrseq *seq, int working,
+ const u32 grp, u32 *work, u32 *i, u32 *p)
{
- const u32 end = misccfg->read_valid_fifo_size + (working ? 0 : 1);
+ const u32 end = seq->misccfg->read_valid_fifo_size + (working ? 0 : 1);
int ret;
for (; *i < end; (*i)++) {
if (working)
*p = 0;
- ret = sdr_find_phase_delay(working, 0, grp, work,
- iocfg->delay_per_opa_tap, p);
+ ret = sdr_find_phase_delay(seq, working, 0, grp, work,
+ seq->iocfg->delay_per_opa_tap, p);
if (!ret)
return 0;
- if (*p > iocfg->dqs_en_phase_max) {
+ if (*p > seq->iocfg->dqs_en_phase_max) {
/* Fiddle with FIFO. */
rw_mgr_incr_vfifo(grp);
if (!working)
@@ -1626,22 +1648,22 @@
*
* Find working DQS enable phase setting.
*/
-static int sdr_working_phase(const u32 grp, u32 *work_bgn, u32 *d,
- u32 *p, u32 *i)
+static int sdr_working_phase(struct socfpga_sdrseq *seq, const u32 grp,
+ u32 *work_bgn, u32 *d, u32 *p, u32 *i)
{
- const u32 dtaps_per_ptap = iocfg->delay_per_opa_tap /
- iocfg->delay_per_dqs_en_dchain_tap;
+ const u32 dtaps_per_ptap = seq->iocfg->delay_per_opa_tap /
+ seq->iocfg->delay_per_dqs_en_dchain_tap;
int ret;
*work_bgn = 0;
for (*d = 0; *d <= dtaps_per_ptap; (*d)++) {
*i = 0;
- scc_mgr_set_dqs_en_delay_all_ranks(grp, *d);
- ret = sdr_find_phase(1, grp, work_bgn, i, p);
+ scc_mgr_set_dqs_en_delay_all_ranks(seq, grp, *d);
+ ret = sdr_find_phase(seq, 1, grp, work_bgn, i, p);
if (!ret)
return 0;
- *work_bgn += iocfg->delay_per_dqs_en_dchain_tap;
+ *work_bgn += seq->iocfg->delay_per_dqs_en_dchain_tap;
}
/* Cannot find working solution */
@@ -1658,43 +1680,44 @@
*
* Find DQS enable backup phase setting.
*/
-static void sdr_backup_phase(const u32 grp, u32 *work_bgn, u32 *p)
+static void sdr_backup_phase(struct socfpga_sdrseq *seq, const u32 grp,
+ u32 *work_bgn, u32 *p)
{
u32 tmp_delay, d;
int ret;
/* Special case code for backing up a phase */
if (*p == 0) {
- *p = iocfg->dqs_en_phase_max;
- rw_mgr_decr_vfifo(grp);
+ *p = seq->iocfg->dqs_en_phase_max;
+ rw_mgr_decr_vfifo(seq, grp);
} else {
(*p)--;
}
- tmp_delay = *work_bgn - iocfg->delay_per_opa_tap;
- scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
+ tmp_delay = *work_bgn - seq->iocfg->delay_per_opa_tap;
+ scc_mgr_set_dqs_en_phase_all_ranks(seq, grp, *p);
- for (d = 0; d <= iocfg->dqs_en_delay_max && tmp_delay < *work_bgn;
+ for (d = 0; d <= seq->iocfg->dqs_en_delay_max && tmp_delay < *work_bgn;
d++) {
- scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
+ scc_mgr_set_dqs_en_delay_all_ranks(seq, grp, d);
- ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
- PASS_ONE_BIT, 0);
+ ret = rw_mgr_mem_calibrate_read_test_all_ranks(seq, grp, 1,
+ PASS_ONE_BIT, 0);
if (ret) {
*work_bgn = tmp_delay;
break;
}
- tmp_delay += iocfg->delay_per_dqs_en_dchain_tap;
+ tmp_delay += seq->iocfg->delay_per_dqs_en_dchain_tap;
}
/* Restore VFIFO to old state before we decremented it (if needed). */
(*p)++;
- if (*p > iocfg->dqs_en_phase_max) {
+ if (*p > seq->iocfg->dqs_en_phase_max) {
*p = 0;
rw_mgr_incr_vfifo(grp);
}
- scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
+ scc_mgr_set_dqs_en_delay_all_ranks(seq, grp, 0);
}
/**
@@ -1706,19 +1729,20 @@
*
* Find non-working DQS enable phase setting.
*/
-static int sdr_nonworking_phase(const u32 grp, u32 *work_end, u32 *p, u32 *i)
+static int sdr_nonworking_phase(struct socfpga_sdrseq *seq,
+ const u32 grp, u32 *work_end, u32 *p, u32 *i)
{
int ret;
(*p)++;
- *work_end += iocfg->delay_per_opa_tap;
- if (*p > iocfg->dqs_en_phase_max) {
+ *work_end += seq->iocfg->delay_per_opa_tap;
+ if (*p > seq->iocfg->dqs_en_phase_max) {
/* Fiddle with FIFO. */
*p = 0;
rw_mgr_incr_vfifo(grp);
}
- ret = sdr_find_phase(0, grp, work_end, i, p);
+ ret = sdr_find_phase(seq, 0, grp, work_end, i, p);
if (ret) {
/* Cannot see edge of failing read. */
debug_cond(DLEVEL >= 2, "%s:%d: end: failed\n",
@@ -1736,7 +1760,8 @@
*
* Find center of the working DQS enable window.
*/
-static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
+static int sdr_find_window_center(struct socfpga_sdrseq *seq,
+ const u32 grp, const u32 work_bgn,
const u32 work_end)
{
u32 work_mid;
@@ -1748,37 +1773,41 @@
debug_cond(DLEVEL >= 2, "work_bgn=%d work_end=%d work_mid=%d\n",
work_bgn, work_end, work_mid);
/* Get the middle delay to be less than a VFIFO delay */
- tmp_delay = (iocfg->dqs_en_phase_max + 1) * iocfg->delay_per_opa_tap;
+ tmp_delay = (seq->iocfg->dqs_en_phase_max + 1)
+ * seq->iocfg->delay_per_opa_tap;
debug_cond(DLEVEL >= 2, "vfifo ptap delay %d\n", tmp_delay);
work_mid %= tmp_delay;
debug_cond(DLEVEL >= 2, "new work_mid %d\n", work_mid);
- tmp_delay = rounddown(work_mid, iocfg->delay_per_opa_tap);
- if (tmp_delay > iocfg->dqs_en_phase_max * iocfg->delay_per_opa_tap)
- tmp_delay = iocfg->dqs_en_phase_max * iocfg->delay_per_opa_tap;
- p = tmp_delay / iocfg->delay_per_opa_tap;
+ tmp_delay = rounddown(work_mid, seq->iocfg->delay_per_opa_tap);
+ if (tmp_delay > seq->iocfg->dqs_en_phase_max
+ * seq->iocfg->delay_per_opa_tap) {
+ tmp_delay = seq->iocfg->dqs_en_phase_max
+ * seq->iocfg->delay_per_opa_tap;
+ }
+ p = tmp_delay / seq->iocfg->delay_per_opa_tap;
debug_cond(DLEVEL >= 2, "new p %d, tmp_delay=%d\n", p, tmp_delay);
d = DIV_ROUND_UP(work_mid - tmp_delay,
- iocfg->delay_per_dqs_en_dchain_tap);
- if (d > iocfg->dqs_en_delay_max)
- d = iocfg->dqs_en_delay_max;
- tmp_delay += d * iocfg->delay_per_dqs_en_dchain_tap;
+ seq->iocfg->delay_per_dqs_en_dchain_tap);
+ if (d > seq->iocfg->dqs_en_delay_max)
+ d = seq->iocfg->dqs_en_delay_max;
+ tmp_delay += d * seq->iocfg->delay_per_dqs_en_dchain_tap;
debug_cond(DLEVEL >= 2, "new d %d, tmp_delay=%d\n", d, tmp_delay);
- scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
- scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
+ scc_mgr_set_dqs_en_phase_all_ranks(seq, grp, p);
+ scc_mgr_set_dqs_en_delay_all_ranks(seq, grp, d);
/*
* push vfifo until we can successfully calibrate. We can do this
* because the largest possible margin in 1 VFIFO cycle.
*/
- for (i = 0; i < misccfg->read_valid_fifo_size; i++) {
+ for (i = 0; i < seq->misccfg->read_valid_fifo_size; i++) {
debug_cond(DLEVEL >= 2, "find_dqs_en_phase: center\n");
- if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
+ if (rw_mgr_mem_calibrate_read_test_all_ranks(seq, grp, 1,
PASS_ONE_BIT,
0)) {
debug_cond(DLEVEL >= 2,
@@ -1797,12 +1826,15 @@
}
/**
- * rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() - Find a good DQS enable to use
+ * rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() - Find a good DQS enable to
+ * use
* @grp: Read/Write Group
*
* Find a good DQS enable to use.
*/
-static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp)
+static int
+rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(struct socfpga_sdrseq *seq,
+ const u32 grp)
{
u32 d, p, i;
u32 dtaps_per_ptap;
@@ -1814,19 +1846,19 @@
reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
- scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
- scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
+ scc_mgr_set_dqs_en_delay_all_ranks(seq, grp, 0);
+ scc_mgr_set_dqs_en_phase_all_ranks(seq, grp, 0);
/* Step 0: Determine number of delay taps for each phase tap. */
- dtaps_per_ptap = iocfg->delay_per_opa_tap /
- iocfg->delay_per_dqs_en_dchain_tap;
+ dtaps_per_ptap = seq->iocfg->delay_per_opa_tap /
+ seq->iocfg->delay_per_dqs_en_dchain_tap;
/* Step 1: First push vfifo until we get a failing read. */
- find_vfifo_failing_read(grp);
+ find_vfifo_failing_read(seq, grp);
/* Step 2: Find first working phase, increment in ptaps. */
work_bgn = 0;
- ret = sdr_working_phase(grp, &work_bgn, &d, &p, &i);
+ ret = sdr_working_phase(seq, grp, &work_bgn, &d, &p, &i);
if (ret)
return ret;
@@ -1842,13 +1874,13 @@
* Step 3a: If we have room, back off by one and
* increment in dtaps.
*/
- sdr_backup_phase(grp, &work_bgn, &p);
+ sdr_backup_phase(seq, grp, &work_bgn, &p);
/*
* Step 4a: go forward from working phase to non working
* phase, increment in ptaps.
*/
- ret = sdr_nonworking_phase(grp, &work_end, &p, &i);
+ ret = sdr_nonworking_phase(seq, grp, &work_end, &p, &i);
if (ret)
return ret;
@@ -1856,14 +1888,14 @@
/* Special case code for backing up a phase */
if (p == 0) {
- p = iocfg->dqs_en_phase_max;
- rw_mgr_decr_vfifo(grp);
+ p = seq->iocfg->dqs_en_phase_max;
+ rw_mgr_decr_vfifo(seq, grp);
} else {
p = p - 1;
}
- work_end -= iocfg->delay_per_opa_tap;
- scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
+ work_end -= seq->iocfg->delay_per_opa_tap;
+ scc_mgr_set_dqs_en_phase_all_ranks(seq, grp, p);
d = 0;
@@ -1872,12 +1904,12 @@
}
/* The dtap increment to find the failing edge is done here. */
- sdr_find_phase_delay(0, 1, grp, &work_end,
- iocfg->delay_per_dqs_en_dchain_tap, &d);
+ sdr_find_phase_delay(seq, 0, 1, grp, &work_end,
+ seq->iocfg->delay_per_dqs_en_dchain_tap, &d);
/* Go back to working dtap */
if (d != 0)
- work_end -= iocfg->delay_per_dqs_en_dchain_tap;
+ work_end -= seq->iocfg->delay_per_dqs_en_dchain_tap;
debug_cond(DLEVEL >= 2,
"%s:%d p/d: ptap=%u dtap=%u end=%u\n",
@@ -1903,8 +1935,8 @@
/* Special case code for backing up a phase */
if (p == 0) {
- p = iocfg->dqs_en_phase_max;
- rw_mgr_decr_vfifo(grp);
+ p = seq->iocfg->dqs_en_phase_max;
+ rw_mgr_decr_vfifo(seq, grp);
debug_cond(DLEVEL >= 2, "%s:%d backedup cycle/phase: p=%u\n",
__func__, __LINE__, p);
} else {
@@ -1913,7 +1945,7 @@
__func__, __LINE__, p);
}
- scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
+ scc_mgr_set_dqs_en_phase_all_ranks(seq, grp, p);
/*
* Increase dtap until we first see a passing read (in case the
@@ -1927,14 +1959,14 @@
initial_failing_dtap = d;
- found_passing_read = !sdr_find_phase_delay(1, 1, grp, NULL, 0, &d);
+ found_passing_read = !sdr_find_phase_delay(seq, 1, 1, grp, NULL, 0, &d);
if (found_passing_read) {
/* Find a failing read. */
debug_cond(DLEVEL >= 2, "%s:%d find failing read\n",
__func__, __LINE__);
d++;
- found_failing_read = !sdr_find_phase_delay(0, 1, grp, NULL, 0,
- &d);
+ found_failing_read = !sdr_find_phase_delay(seq, 0, 1, grp, NULL,
+ 0, &d);
} else {
debug_cond(DLEVEL >= 1,
"%s:%d failed to calculate dtaps per ptap. Fall back on static value\n",
@@ -1944,7 +1976,7 @@
/*
* The dynamically calculated dtaps_per_ptap is only valid if we
* found a passing/failing read. If we didn't, it means d hit the max
- * (iocfg->dqs_en_delay_max). Otherwise, dtaps_per_ptap retains its
+ * (seq->iocfg->dqs_en_delay_max). Otherwise, dtaps_per_ptap retains its
* statically calculated value.
*/
if (found_passing_read && found_failing_read)
@@ -1955,7 +1987,7 @@
__func__, __LINE__, d, initial_failing_dtap, dtaps_per_ptap);
/* Step 6: Find the centre of the window. */
- ret = sdr_find_window_center(grp, work_bgn, work_end);
+ ret = sdr_find_window_center(seq, grp, work_bgn, work_end);
return ret;
}
@@ -1973,33 +2005,35 @@
*
* Test if the found edge is valid.
*/
-static u32 search_stop_check(const int write, const int d, const int rank_bgn,
+static u32 search_stop_check(struct socfpga_sdrseq *seq, const int write,
+ const int d, const int rank_bgn,
const u32 write_group, const u32 read_group,
u32 *bit_chk, u32 *sticky_bit_chk,
const u32 use_read_test)
{
- const u32 ratio = rwcfg->mem_if_read_dqs_width /
- rwcfg->mem_if_write_dqs_width;
- const u32 correct_mask = write ? param->write_correct_mask :
- param->read_correct_mask;
- const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :
- rwcfg->mem_dq_per_read_dqs;
+ const u32 ratio = seq->rwcfg->mem_if_read_dqs_width /
+ seq->rwcfg->mem_if_write_dqs_width;
+ const u32 correct_mask = write ? seq->param.write_correct_mask :
+ seq->param.read_correct_mask;
+ const u32 per_dqs = write ? seq->rwcfg->mem_dq_per_write_dqs :
+ seq->rwcfg->mem_dq_per_read_dqs;
u32 ret;
/*
* Stop searching when the read test doesn't pass AND when
* we've seen a passing read on every bit.
*/
if (write) { /* WRITE-ONLY */
- ret = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
- 0, PASS_ONE_BIT,
- bit_chk, 0);
+ ret = !rw_mgr_mem_calibrate_write_test(seq, rank_bgn,
+ write_group, 0,
+ PASS_ONE_BIT, bit_chk,
+ 0);
} else if (use_read_test) { /* READ-ONLY */
- ret = !rw_mgr_mem_calibrate_read_test(rank_bgn, read_group,
+ ret = !rw_mgr_mem_calibrate_read_test(seq, rank_bgn, read_group,
NUM_READ_PB_TESTS,
PASS_ONE_BIT, bit_chk,
0, 0);
} else { /* READ-ONLY */
- rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 0,
+ rw_mgr_mem_calibrate_write_test(seq, rank_bgn, write_group, 0,
PASS_ONE_BIT, bit_chk, 0);
*bit_chk = *bit_chk >> (per_dqs *
(read_group - (write_group * ratio)));
@@ -2028,29 +2062,30 @@
*
* Find left edge of DQ/DQS working phase.
*/
-static void search_left_edge(const int write, const int rank_bgn,
- const u32 write_group, const u32 read_group, const u32 test_bgn,
- u32 *sticky_bit_chk,
- int *left_edge, int *right_edge, const u32 use_read_test)
+static void search_left_edge(struct socfpga_sdrseq *seq, const int write,
+ const int rank_bgn, const u32 write_group,
+ const u32 read_group, const u32 test_bgn,
+ u32 *sticky_bit_chk, int *left_edge,
+ int *right_edge, const u32 use_read_test)
{
- const u32 delay_max = write ? iocfg->io_out1_delay_max :
- iocfg->io_in_delay_max;
- const u32 dqs_max = write ? iocfg->io_out1_delay_max :
- iocfg->dqs_in_delay_max;
- const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :
- rwcfg->mem_dq_per_read_dqs;
+ const u32 delay_max = write ? seq->iocfg->io_out1_delay_max :
+ seq->iocfg->io_in_delay_max;
+ const u32 dqs_max = write ? seq->iocfg->io_out1_delay_max :
+ seq->iocfg->dqs_in_delay_max;
+ const u32 per_dqs = write ? seq->rwcfg->mem_dq_per_write_dqs :
+ seq->rwcfg->mem_dq_per_read_dqs;
u32 stop, bit_chk;
int i, d;
for (d = 0; d <= dqs_max; d++) {
if (write)
- scc_mgr_apply_group_dq_out1_delay(d);
+ scc_mgr_apply_group_dq_out1_delay(seq, d);
else
- scc_mgr_apply_group_dq_in_delay(test_bgn, d);
+ scc_mgr_apply_group_dq_in_delay(seq, test_bgn, d);
writel(0, &sdr_scc_mgr->update);
- stop = search_stop_check(write, d, rank_bgn, write_group,
+ stop = search_stop_check(seq, write, d, rank_bgn, write_group,
read_group, &bit_chk, sticky_bit_chk,
use_read_test);
if (stop == 1)
@@ -2080,9 +2115,9 @@
/* Reset DQ delay chains to 0 */
if (write)
- scc_mgr_apply_group_dq_out1_delay(0);
+ scc_mgr_apply_group_dq_out1_delay(seq, 0);
else
- scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
+ scc_mgr_apply_group_dq_in_delay(seq, test_bgn, 0);
*sticky_bit_chk = 0;
for (i = per_dqs - 1; i >= 0; i--) {
@@ -2138,31 +2173,33 @@
*
* Find right edge of DQ/DQS working phase.
*/
-static int search_right_edge(const int write, const int rank_bgn,
- const u32 write_group, const u32 read_group,
- const int start_dqs, const int start_dqs_en,
- u32 *sticky_bit_chk,
- int *left_edge, int *right_edge, const u32 use_read_test)
+static int search_right_edge(struct socfpga_sdrseq *seq, const int write,
+ const int rank_bgn, const u32 write_group,
+ const u32 read_group, const int start_dqs,
+ const int start_dqs_en, u32 *sticky_bit_chk,
+ int *left_edge, int *right_edge,
+ const u32 use_read_test)
{
- const u32 delay_max = write ? iocfg->io_out1_delay_max :
- iocfg->io_in_delay_max;
- const u32 dqs_max = write ? iocfg->io_out1_delay_max :
- iocfg->dqs_in_delay_max;
- const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :
- rwcfg->mem_dq_per_read_dqs;
+ const u32 delay_max = write ? seq->iocfg->io_out1_delay_max :
+ seq->iocfg->io_in_delay_max;
+ const u32 dqs_max = write ? seq->iocfg->io_out1_delay_max :
+ seq->iocfg->dqs_in_delay_max;
+ const u32 per_dqs = write ? seq->rwcfg->mem_dq_per_write_dqs :
+ seq->rwcfg->mem_dq_per_read_dqs;
u32 stop, bit_chk;
int i, d;
for (d = 0; d <= dqs_max - start_dqs; d++) {
if (write) { /* WRITE-ONLY */
- scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
+ scc_mgr_apply_group_dqs_io_and_oct_out1(seq,
+ write_group,
d + start_dqs);
} else { /* READ-ONLY */
scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
- if (iocfg->shift_dqs_en_when_shift_dqs) {
+ if (seq->iocfg->shift_dqs_en_when_shift_dqs) {
u32 delay = d + start_dqs_en;
- if (delay > iocfg->dqs_en_delay_max)
- delay = iocfg->dqs_en_delay_max;
+ if (delay > seq->iocfg->dqs_en_delay_max)
+ delay = seq->iocfg->dqs_en_delay_max;
scc_mgr_set_dqs_en_delay(read_group, delay);
}
scc_mgr_load_dqs(read_group);
@@ -2170,12 +2207,13 @@
writel(0, &sdr_scc_mgr->update);
- stop = search_stop_check(write, d, rank_bgn, write_group,
+ stop = search_stop_check(seq, write, d, rank_bgn, write_group,
read_group, &bit_chk, sticky_bit_chk,
use_read_test);
if (stop == 1) {
if (write && (d == 0)) { /* WRITE-ONLY */
- for (i = 0; i < rwcfg->mem_dq_per_write_dqs;
+ for (i = 0;
+ i < seq->rwcfg->mem_dq_per_write_dqs;
i++) {
/*
* d = 0 failed, but it passed when
@@ -2263,11 +2301,12 @@
*
* Find index and value of the middle of the DQ/DQS working phase.
*/
-static int get_window_mid_index(const int write, int *left_edge,
+static int get_window_mid_index(struct socfpga_sdrseq *seq,
+ const int write, int *left_edge,
int *right_edge, int *mid_min)
{
- const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :
- rwcfg->mem_dq_per_read_dqs;
+ const u32 per_dqs = write ? seq->rwcfg->mem_dq_per_write_dqs :
+ seq->rwcfg->mem_dq_per_read_dqs;
int i, mid, min_index;
/* Find middle of window for each DQ bit */
@@ -2310,15 +2349,16 @@
*
* Align the DQ/DQS windows in each group.
*/
-static void center_dq_windows(const int write, int *left_edge, int *right_edge,
+static void center_dq_windows(struct socfpga_sdrseq *seq,
+ const int write, int *left_edge, int *right_edge,
const int mid_min, const int orig_mid_min,
const int min_index, const int test_bgn,
int *dq_margin, int *dqs_margin)
{
- const s32 delay_max = write ? iocfg->io_out1_delay_max :
- iocfg->io_in_delay_max;
- const s32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :
- rwcfg->mem_dq_per_read_dqs;
+ const s32 delay_max = write ? seq->iocfg->io_out1_delay_max :
+ seq->iocfg->io_in_delay_max;
+ const s32 per_dqs = write ? seq->rwcfg->mem_dq_per_write_dqs :
+ seq->rwcfg->mem_dq_per_read_dqs;
const s32 delay_off = write ? SCC_MGR_IO_OUT1_DELAY_OFFSET :
SCC_MGR_IO_IN_DELAY_OFFSET;
const s32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | delay_off;
@@ -2385,9 +2425,12 @@
*
* Per-bit deskew DQ and centering.
*/
-static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn,
- const u32 rw_group, const u32 test_bgn,
- const int use_read_test, const int update_fom)
+static int rw_mgr_mem_calibrate_vfifo_center(struct socfpga_sdrseq *seq,
+ const u32 rank_bgn,
+ const u32 rw_group,
+ const u32 test_bgn,
+ const int use_read_test,
+ const int update_fom)
{
const u32 addr =
SDR_PHYGRP_SCCGRP_ADDRESS + SCC_MGR_DQS_IN_DELAY_OFFSET +
@@ -2397,36 +2440,36 @@
* signed numbers.
*/
u32 sticky_bit_chk;
- int32_t left_edge[rwcfg->mem_dq_per_read_dqs];
- int32_t right_edge[rwcfg->mem_dq_per_read_dqs];
- int32_t orig_mid_min, mid_min;
- int32_t new_dqs, start_dqs, start_dqs_en = 0, final_dqs_en;
- int32_t dq_margin, dqs_margin;
+ s32 left_edge[seq->rwcfg->mem_dq_per_read_dqs];
+ s32 right_edge[seq->rwcfg->mem_dq_per_read_dqs];
+ s32 orig_mid_min, mid_min;
+ s32 new_dqs, start_dqs, start_dqs_en = 0, final_dqs_en;
+ s32 dq_margin, dqs_margin;
int i, min_index;
int ret;
debug("%s:%d: %u %u", __func__, __LINE__, rw_group, test_bgn);
start_dqs = readl(addr);
- if (iocfg->shift_dqs_en_when_shift_dqs)
- start_dqs_en = readl(addr - iocfg->dqs_en_delay_offset);
+ if (seq->iocfg->shift_dqs_en_when_shift_dqs)
+ start_dqs_en = readl(addr - seq->iocfg->dqs_en_delay_offset);
/* set the left and right edge of each bit to an illegal value */
- /* use (iocfg->io_in_delay_max + 1) as an illegal value */
+ /* use (seq->iocfg->io_in_delay_max + 1) as an illegal value */
sticky_bit_chk = 0;
- for (i = 0; i < rwcfg->mem_dq_per_read_dqs; i++) {
- left_edge[i] = iocfg->io_in_delay_max + 1;
- right_edge[i] = iocfg->io_in_delay_max + 1;
+ for (i = 0; i < seq->rwcfg->mem_dq_per_read_dqs; i++) {
+ left_edge[i] = seq->iocfg->io_in_delay_max + 1;
+ right_edge[i] = seq->iocfg->io_in_delay_max + 1;
}
/* Search for the left edge of the window for each bit */
- search_left_edge(0, rank_bgn, rw_group, rw_group, test_bgn,
+ search_left_edge(seq, 0, rank_bgn, rw_group, rw_group, test_bgn,
&sticky_bit_chk,
left_edge, right_edge, use_read_test);
/* Search for the right edge of the window for each bit */
- ret = search_right_edge(0, rank_bgn, rw_group, rw_group,
+ ret = search_right_edge(seq, 0, rank_bgn, rw_group, rw_group,
start_dqs, start_dqs_en,
&sticky_bit_chk,
left_edge, right_edge, use_read_test);
@@ -2437,7 +2480,7 @@
* dqs/ck relationships.
*/
scc_mgr_set_dqs_bus_in_delay(rw_group, start_dqs);
- if (iocfg->shift_dqs_en_when_shift_dqs)
+ if (seq->iocfg->shift_dqs_en_when_shift_dqs)
scc_mgr_set_dqs_en_delay(rw_group, start_dqs_en);
scc_mgr_load_dqs(rw_group);
@@ -2447,26 +2490,27 @@
"%s:%d vfifo_center: failed to find edge [%u]: %d %d",
__func__, __LINE__, i, left_edge[i], right_edge[i]);
if (use_read_test) {
- set_failing_group_stage(rw_group *
- rwcfg->mem_dq_per_read_dqs + i,
+ set_failing_group_stage(seq, rw_group *
+ seq->rwcfg->mem_dq_per_read_dqs + i,
CAL_STAGE_VFIFO,
CAL_SUBSTAGE_VFIFO_CENTER);
} else {
- set_failing_group_stage(rw_group *
- rwcfg->mem_dq_per_read_dqs + i,
+ set_failing_group_stage(seq, rw_group *
+ seq->rwcfg->mem_dq_per_read_dqs + i,
CAL_STAGE_VFIFO_AFTER_WRITES,
CAL_SUBSTAGE_VFIFO_CENTER);
}
return -EIO;
}
- min_index = get_window_mid_index(0, left_edge, right_edge, &mid_min);
+ min_index = get_window_mid_index(seq, 0, left_edge, right_edge,
+ &mid_min);
/* Determine the amount we can change DQS (which is -mid_min) */
orig_mid_min = mid_min;
new_dqs = start_dqs - mid_min;
- if (new_dqs > iocfg->dqs_in_delay_max)
- new_dqs = iocfg->dqs_in_delay_max;
+ if (new_dqs > seq->iocfg->dqs_in_delay_max)
+ new_dqs = seq->iocfg->dqs_in_delay_max;
else if (new_dqs < 0)
new_dqs = 0;
@@ -2474,10 +2518,10 @@
debug_cond(DLEVEL >= 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
mid_min, new_dqs);
- if (iocfg->shift_dqs_en_when_shift_dqs) {
- if (start_dqs_en - mid_min > iocfg->dqs_en_delay_max)
+ if (seq->iocfg->shift_dqs_en_when_shift_dqs) {
+ if (start_dqs_en - mid_min > seq->iocfg->dqs_en_delay_max)
mid_min += start_dqs_en - mid_min -
- iocfg->dqs_en_delay_max;
+ seq->iocfg->dqs_en_delay_max;
else if (start_dqs_en - mid_min < 0)
mid_min += start_dqs_en - mid_min;
}
@@ -2486,15 +2530,15 @@
debug_cond(DLEVEL >= 1,
"vfifo_center: start_dqs=%d start_dqs_en=%d new_dqs=%d mid_min=%d\n",
start_dqs,
- iocfg->shift_dqs_en_when_shift_dqs ? start_dqs_en : -1,
+ seq->iocfg->shift_dqs_en_when_shift_dqs ? start_dqs_en : -1,
new_dqs, mid_min);
/* Add delay to bring centre of all DQ windows to the same "level". */
- center_dq_windows(0, left_edge, right_edge, mid_min, orig_mid_min,
+ center_dq_windows(seq, 0, left_edge, right_edge, mid_min, orig_mid_min,
min_index, test_bgn, &dq_margin, &dqs_margin);
/* Move DQS-en */
- if (iocfg->shift_dqs_en_when_shift_dqs) {
+ if (seq->iocfg->shift_dqs_en_when_shift_dqs) {
final_dqs_en = start_dqs_en - mid_min;
scc_mgr_set_dqs_en_delay(rw_group, final_dqs_en);
scc_mgr_load_dqs(rw_group);
@@ -2520,7 +2564,8 @@
}
/**
- * rw_mgr_mem_calibrate_guaranteed_write() - Perform guaranteed write into the device
+ * rw_mgr_mem_calibrate_guaranteed_write() - Perform guaranteed write into the
+ * device
* @rw_group: Read/Write Group
* @phase: DQ/DQS phase
*
@@ -2528,13 +2573,14 @@
* device, the sequencer uses a guaranteed write mechanism to write data into
* the memory device.
*/
-static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group,
+static int rw_mgr_mem_calibrate_guaranteed_write(struct socfpga_sdrseq *seq,
+ const u32 rw_group,
const u32 phase)
{
int ret;
/* Set a particular DQ/DQS phase. */
- scc_mgr_set_dqdqs_output_phase_all_ranks(rw_group, phase);
+ scc_mgr_set_dqdqs_output_phase_all_ranks(seq, rw_group, phase);
debug_cond(DLEVEL >= 1, "%s:%d guaranteed write: g=%u p=%u\n",
__func__, __LINE__, rw_group, phase);
@@ -2544,16 +2590,16 @@
* Load up the patterns used by read calibration using the
* current DQDQS phase.
*/
- rw_mgr_mem_calibrate_read_load_patterns(0, 1);
+ rw_mgr_mem_calibrate_read_load_patterns(seq, 0, 1);
- if (gbl->phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ)
+ if (seq->gbl.phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ)
return 0;
/*
* Altera EMI_RM 2015.05.04 :: Figure 1-26
* Back-to-Back reads of the patterns used for calibration.
*/
- ret = rw_mgr_mem_calibrate_read_test_patterns(0, rw_group, 1);
+ ret = rw_mgr_mem_calibrate_read_test_patterns(seq, 0, rw_group, 1);
if (ret)
debug_cond(DLEVEL >= 1,
"%s:%d Guaranteed read test failed: g=%u p=%u\n",
@@ -2569,8 +2615,10 @@
* DQS enable calibration ensures reliable capture of the DQ signal without
* glitches on the DQS line.
*/
-static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,
- const u32 test_bgn)
+static int
+rw_mgr_mem_calibrate_dqs_enable_calibration(struct socfpga_sdrseq *seq,
+ const u32 rw_group,
+ const u32 test_bgn)
{
/*
* Altera EMI_RM 2015.05.04 :: Figure 1-27
@@ -2578,18 +2626,18 @@
*/
/* We start at zero, so have one less dq to devide among */
- const u32 delay_step = iocfg->io_in_delay_max /
- (rwcfg->mem_dq_per_read_dqs - 1);
+ const u32 delay_step = seq->iocfg->io_in_delay_max /
+ (seq->rwcfg->mem_dq_per_read_dqs - 1);
int ret;
u32 i, p, d, r;
debug("%s:%d (%u,%u)\n", __func__, __LINE__, rw_group, test_bgn);
/* Try different dq_in_delays since the DQ path is shorter than DQS. */
- for (r = 0; r < rwcfg->mem_number_of_ranks;
+ for (r = 0; r < seq->rwcfg->mem_number_of_ranks;
r += NUM_RANKS_PER_SHADOW_REG) {
for (i = 0, p = test_bgn, d = 0;
- i < rwcfg->mem_dq_per_read_dqs;
+ i < seq->rwcfg->mem_dq_per_read_dqs;
i++, p++, d += delay_step) {
debug_cond(DLEVEL >= 1,
"%s:%d: g=%u r=%u i=%u p=%u d=%u\n",
@@ -2606,15 +2654,15 @@
* Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
* dq_in_delay values
*/
- ret = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(rw_group);
+ ret = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(seq, rw_group);
debug_cond(DLEVEL >= 1,
"%s:%d: g=%u found=%u; Reseting delay chain to zero\n",
__func__, __LINE__, rw_group, !ret);
- for (r = 0; r < rwcfg->mem_number_of_ranks;
+ for (r = 0; r < seq->rwcfg->mem_number_of_ranks;
r += NUM_RANKS_PER_SHADOW_REG) {
- scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
+ scc_mgr_apply_group_dq_in_delay(seq, test_bgn, 0);
writel(0, &sdr_scc_mgr->update);
}
@@ -2632,7 +2680,8 @@
* within a group.
*/
static int
-rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group, const u32 test_bgn,
+rw_mgr_mem_calibrate_dq_dqs_centering(struct socfpga_sdrseq *seq,
+ const u32 rw_group, const u32 test_bgn,
const int use_read_test,
const int update_fom)
@@ -2646,9 +2695,9 @@
*/
grp_calibrated = 1;
for (rank_bgn = 0, sr = 0;
- rank_bgn < rwcfg->mem_number_of_ranks;
+ rank_bgn < seq->rwcfg->mem_number_of_ranks;
rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
- ret = rw_mgr_mem_calibrate_vfifo_center(rank_bgn, rw_group,
+ ret = rw_mgr_mem_calibrate_vfifo_center(seq, rank_bgn, rw_group,
test_bgn,
use_read_test,
update_fom);
@@ -2679,7 +2728,8 @@
* - DQS input phase and DQS input delay (DQ/DQS Centering)
* - we also do a per-bit deskew on the DQ lines.
*/
-static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)
+static int rw_mgr_mem_calibrate_vfifo(struct socfpga_sdrseq *seq,
+ const u32 rw_group, const u32 test_bgn)
{
u32 p, d;
u32 dtaps_per_ptap;
@@ -2697,8 +2747,9 @@
failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
/* USER Determine number of delay taps for each phase tap. */
- dtaps_per_ptap = DIV_ROUND_UP(iocfg->delay_per_opa_tap,
- iocfg->delay_per_dqs_en_dchain_tap) - 1;
+ dtaps_per_ptap = DIV_ROUND_UP(seq->iocfg->delay_per_opa_tap,
+ seq->iocfg->delay_per_dqs_en_dchain_tap)
+ - 1;
for (d = 0; d <= dtaps_per_ptap; d += 2) {
/*
@@ -2708,18 +2759,22 @@
* output side yet.
*/
if (d > 0) {
- scc_mgr_apply_group_all_out_delay_add_all_ranks(
- rw_group, d);
+ scc_mgr_apply_group_all_out_delay_add_all_ranks(seq,
+ rw_group,
+ d);
}
- for (p = 0; p <= iocfg->dqdqs_out_phase_max; p++) {
+ for (p = 0; p <= seq->iocfg->dqdqs_out_phase_max; p++) {
/* 1) Guaranteed Write */
- ret = rw_mgr_mem_calibrate_guaranteed_write(rw_group, p);
+ ret = rw_mgr_mem_calibrate_guaranteed_write(seq,
+ rw_group,
+ p);
if (ret)
break;
/* 2) DQS Enable Calibration */
- ret = rw_mgr_mem_calibrate_dqs_enable_calibration(rw_group,
+ ret = rw_mgr_mem_calibrate_dqs_enable_calibration(seq,
+ rw_group,
test_bgn);
if (ret) {
failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
@@ -2731,8 +2786,10 @@
* If doing read after write calibration, do not update
* FOM now. Do it then.
*/
- ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group,
- test_bgn, 1, 0);
+ ret = rw_mgr_mem_calibrate_dq_dqs_centering(seq,
+ rw_group,
+ test_bgn,
+ 1, 0);
if (ret) {
failed_substage = CAL_SUBSTAGE_VFIFO_CENTER;
continue;
@@ -2744,7 +2801,8 @@
}
/* Calibration Stage 1 failed. */
- set_failing_group_stage(rw_group, CAL_STAGE_VFIFO, failed_substage);
+ set_failing_group_stage(seq, rw_group, CAL_STAGE_VFIFO,
+ failed_substage);
return 0;
/* Calibration Stage 1 completed OK. */
@@ -2755,7 +2813,7 @@
* first case).
*/
if (d > 2)
- scc_mgr_zero_group(rw_group, 1);
+ scc_mgr_zero_group(seq, rw_group, 1);
return 1;
}
@@ -2770,7 +2828,8 @@
* This function implements UniPHY calibration Stage 3, as explained in
* detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
*/
-static int rw_mgr_mem_calibrate_vfifo_end(const u32 rw_group,
+static int rw_mgr_mem_calibrate_vfifo_end(struct socfpga_sdrseq *seq,
+ const u32 rw_group,
const u32 test_bgn)
{
int ret;
@@ -2782,9 +2841,10 @@
reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES);
reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
- ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group, test_bgn, 0, 1);
+ ret = rw_mgr_mem_calibrate_dq_dqs_centering(seq, rw_group, test_bgn, 0,
+ 1);
if (ret)
- set_failing_group_stage(rw_group,
+ set_failing_group_stage(seq, rw_group,
CAL_STAGE_VFIFO_AFTER_WRITES,
CAL_SUBSTAGE_VFIFO_CENTER);
return ret;
@@ -2799,7 +2859,7 @@
* detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
* Calibrate LFIFO to find smallest read latency.
*/
-static u32 rw_mgr_mem_calibrate_lfifo(void)
+static u32 rw_mgr_mem_calibrate_lfifo(struct socfpga_sdrseq *seq)
{
int found_one = 0;
@@ -2810,14 +2870,15 @@
reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY);
/* Load up the patterns used by read calibration for all ranks */
- rw_mgr_mem_calibrate_read_load_patterns(0, 1);
+ rw_mgr_mem_calibrate_read_load_patterns(seq, 0, 1);
do {
- writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
+ writel(seq->gbl.curr_read_lat, &phy_mgr_cfg->phy_rlat);
debug_cond(DLEVEL >= 2, "%s:%d lfifo: read_lat=%u",
- __func__, __LINE__, gbl->curr_read_lat);
+ __func__, __LINE__, seq->gbl.curr_read_lat);
- if (!rw_mgr_mem_calibrate_read_test_all_ranks(0, NUM_READ_TESTS,
+ if (!rw_mgr_mem_calibrate_read_test_all_ranks(seq, 0,
+ NUM_READ_TESTS,
PASS_ALL_BITS, 1))
break;
@@ -2826,26 +2887,26 @@
* Reduce read latency and see if things are
* working correctly.
*/
- gbl->curr_read_lat--;
- } while (gbl->curr_read_lat > 0);
+ seq->gbl.curr_read_lat--;
+ } while (seq->gbl.curr_read_lat > 0);
/* Reset the fifos to get pointers to known state. */
writel(0, &phy_mgr_cmd->fifo_reset);
if (found_one) {
/* Add a fudge factor to the read latency that was determined */
- gbl->curr_read_lat += 2;
- writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
+ seq->gbl.curr_read_lat += 2;
+ writel(seq->gbl.curr_read_lat, &phy_mgr_cfg->phy_rlat);
debug_cond(DLEVEL >= 2,
"%s:%d lfifo: success: using read_lat=%u\n",
- __func__, __LINE__, gbl->curr_read_lat);
+ __func__, __LINE__, seq->gbl.curr_read_lat);
} else {
- set_failing_group_stage(0xff, CAL_STAGE_LFIFO,
+ set_failing_group_stage(seq, 0xff, CAL_STAGE_LFIFO,
CAL_SUBSTAGE_READ_LATENCY);
debug_cond(DLEVEL >= 2,
"%s:%d lfifo: failed at initial read_lat=%u\n",
- __func__, __LINE__, gbl->curr_read_lat);
+ __func__, __LINE__, seq->gbl.curr_read_lat);
}
return found_one;
@@ -2853,7 +2914,8 @@
/**
* search_window() - Search for the/part of the window with DM/DQS shift
- * @search_dm: If 1, search for the DM shift, if 0, search for DQS shift
+ * @search_dm: If 1, search for the DM shift, if 0, search for DQS
+ * shift
* @rank_bgn: Rank number
* @write_group: Write Group
* @bgn_curr: Current window begin
@@ -2865,20 +2927,21 @@
*
* Search for the/part of the window with DM/DQS shift.
*/
-static void search_window(const int search_dm,
- const u32 rank_bgn, const u32 write_group,
- int *bgn_curr, int *end_curr, int *bgn_best,
- int *end_best, int *win_best, int new_dqs)
+static void search_window(struct socfpga_sdrseq *seq,
+ const int search_dm, const u32 rank_bgn,
+ const u32 write_group, int *bgn_curr, int *end_curr,
+ int *bgn_best, int *end_best, int *win_best,
+ int new_dqs)
{
u32 bit_chk;
- const int max = iocfg->io_out1_delay_max - new_dqs;
+ const int max = seq->iocfg->io_out1_delay_max - new_dqs;
int d, di;
/* Search for the/part of the window with DM/DQS shift. */
for (di = max; di >= 0; di -= DELTA_D) {
if (search_dm) {
d = di;
- scc_mgr_apply_group_dm_out1_delay(d);
+ scc_mgr_apply_group_dm_out1_delay(seq, d);
} else {
/* For DQS, we go from 0...max */
d = max - di;
@@ -2886,14 +2949,15 @@
* Note: This only shifts DQS, so are we limiting
* ourselves to width of DQ unnecessarily.
*/
- scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
+ scc_mgr_apply_group_dqs_io_and_oct_out1(seq,
+ write_group,
d + new_dqs);
}
writel(0, &sdr_scc_mgr->update);
- if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
- PASS_ALL_BITS, &bit_chk,
+ if (rw_mgr_mem_calibrate_write_test(seq, rank_bgn, write_group,
+ 1, PASS_ALL_BITS, &bit_chk,
0)) {
/* Set current end of the window. */
*end_curr = search_dm ? -d : d;
@@ -2902,7 +2966,7 @@
* If a starting edge of our window has not been seen
* this is our current start of the DM window.
*/
- if (*bgn_curr == iocfg->io_out1_delay_max + 1)
+ if (*bgn_curr == seq->iocfg->io_out1_delay_max + 1)
*bgn_curr = search_dm ? -d : d;
/*
@@ -2916,8 +2980,8 @@
}
} else {
/* We just saw a failing test. Reset temp edge. */
- *bgn_curr = iocfg->io_out1_delay_max + 1;
- *end_curr = iocfg->io_out1_delay_max + 1;
+ *bgn_curr = seq->iocfg->io_out1_delay_max + 1;
+ *end_curr = seq->iocfg->io_out1_delay_max + 1;
/* Early exit is only applicable to DQS. */
if (search_dm)
@@ -2928,7 +2992,8 @@
* chain space is less than already seen largest
* window we can exit.
*/
- if (*win_best - 1 > iocfg->io_out1_delay_max - new_dqs - d)
+ if (*win_best - 1 > seq->iocfg->io_out1_delay_max
+ - new_dqs - d)
break;
}
}
@@ -2944,22 +3009,23 @@
* certain windows.
*/
static int
-rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group,
+rw_mgr_mem_calibrate_writes_center(struct socfpga_sdrseq *seq,
+ const u32 rank_bgn, const u32 write_group,
const u32 test_bgn)
{
int i;
u32 sticky_bit_chk;
u32 min_index;
- int left_edge[rwcfg->mem_dq_per_write_dqs];
- int right_edge[rwcfg->mem_dq_per_write_dqs];
+ int left_edge[seq->rwcfg->mem_dq_per_write_dqs];
+ int right_edge[seq->rwcfg->mem_dq_per_write_dqs];
int mid;
int mid_min, orig_mid_min;
int new_dqs, start_dqs;
int dq_margin, dqs_margin, dm_margin;
- int bgn_curr = iocfg->io_out1_delay_max + 1;
- int end_curr = iocfg->io_out1_delay_max + 1;
- int bgn_best = iocfg->io_out1_delay_max + 1;
- int end_best = iocfg->io_out1_delay_max + 1;
+ int bgn_curr = seq->iocfg->io_out1_delay_max + 1;
+ int end_curr = seq->iocfg->io_out1_delay_max + 1;
+ int bgn_best = seq->iocfg->io_out1_delay_max + 1;
+ int end_best = seq->iocfg->io_out1_delay_max + 1;
int win_best = 0;
int ret;
@@ -2970,37 +3036,39 @@
start_dqs = readl((SDR_PHYGRP_SCCGRP_ADDRESS |
SCC_MGR_IO_OUT1_DELAY_OFFSET) +
- (rwcfg->mem_dq_per_write_dqs << 2));
+ (seq->rwcfg->mem_dq_per_write_dqs << 2));
/* Per-bit deskew. */
/*
* Set the left and right edge of each bit to an illegal value.
- * Use (iocfg->io_out1_delay_max + 1) as an illegal value.
+ * Use (seq->iocfg->io_out1_delay_max + 1) as an illegal value.
*/
sticky_bit_chk = 0;
- for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) {
- left_edge[i] = iocfg->io_out1_delay_max + 1;
- right_edge[i] = iocfg->io_out1_delay_max + 1;
+ for (i = 0; i < seq->rwcfg->mem_dq_per_write_dqs; i++) {
+ left_edge[i] = seq->iocfg->io_out1_delay_max + 1;
+ right_edge[i] = seq->iocfg->io_out1_delay_max + 1;
}
/* Search for the left edge of the window for each bit. */
- search_left_edge(1, rank_bgn, write_group, 0, test_bgn,
+ search_left_edge(seq, 1, rank_bgn, write_group, 0, test_bgn,
&sticky_bit_chk,
left_edge, right_edge, 0);
/* Search for the right edge of the window for each bit. */
- ret = search_right_edge(1, rank_bgn, write_group, 0,
+ ret = search_right_edge(seq, 1, rank_bgn, write_group, 0,
start_dqs, 0,
&sticky_bit_chk,
left_edge, right_edge, 0);
if (ret) {
- set_failing_group_stage(test_bgn + ret - 1, CAL_STAGE_WRITES,
+ set_failing_group_stage(seq, test_bgn + ret - 1,
+ CAL_STAGE_WRITES,
CAL_SUBSTAGE_WRITES_CENTER);
return -EINVAL;
}
- min_index = get_window_mid_index(1, left_edge, right_edge, &mid_min);
+ min_index = get_window_mid_index(seq, 1, left_edge, right_edge,
+ &mid_min);
/* Determine the amount we can change DQS (which is -mid_min). */
orig_mid_min = mid_min;
@@ -3011,11 +3079,11 @@
__func__, __LINE__, start_dqs, new_dqs, mid_min);
/* Add delay to bring centre of all DQ windows to the same "level". */
- center_dq_windows(1, left_edge, right_edge, mid_min, orig_mid_min,
+ center_dq_windows(seq, 1, left_edge, right_edge, mid_min, orig_mid_min,
min_index, 0, &dq_margin, &dqs_margin);
/* Move DQS */
- scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
+ scc_mgr_apply_group_dqs_io_and_oct_out1(seq, write_group, new_dqs);
writel(0, &sdr_scc_mgr->update);
/* Centre DM */
@@ -3023,17 +3091,17 @@
/*
* Set the left and right edge of each bit to an illegal value.
- * Use (iocfg->io_out1_delay_max + 1) as an illegal value.
+ * Use (seq->iocfg->io_out1_delay_max + 1) as an illegal value.
*/
- left_edge[0] = iocfg->io_out1_delay_max + 1;
- right_edge[0] = iocfg->io_out1_delay_max + 1;
+ left_edge[0] = seq->iocfg->io_out1_delay_max + 1;
+ right_edge[0] = seq->iocfg->io_out1_delay_max + 1;
/* Search for the/part of the window with DM shift. */
- search_window(1, rank_bgn, write_group, &bgn_curr, &end_curr,
+ search_window(seq, 1, rank_bgn, write_group, &bgn_curr, &end_curr,
&bgn_best, &end_best, &win_best, 0);
/* Reset DM delay chains to 0. */
- scc_mgr_apply_group_dm_out1_delay(0);
+ scc_mgr_apply_group_dm_out1_delay(seq, 0);
/*
* Check to see if the current window nudges up aganist 0 delay.
@@ -3041,12 +3109,12 @@
* search begins as a new search.
*/
if (end_curr != 0) {
- bgn_curr = iocfg->io_out1_delay_max + 1;
- end_curr = iocfg->io_out1_delay_max + 1;
+ bgn_curr = seq->iocfg->io_out1_delay_max + 1;
+ end_curr = seq->iocfg->io_out1_delay_max + 1;
}
/* Search for the/part of the window with DQS shifts. */
- search_window(0, rank_bgn, write_group, &bgn_curr, &end_curr,
+ search_window(seq, 0, rank_bgn, write_group, &bgn_curr, &end_curr,
&bgn_best, &end_best, &win_best, new_dqs);
/* Assign left and right edge for cal and reporting. */
@@ -3057,7 +3125,7 @@
__func__, __LINE__, left_edge[0], right_edge[0]);
/* Move DQS (back to orig). */
- scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
+ scc_mgr_apply_group_dqs_io_and_oct_out1(seq, write_group, new_dqs);
/* Move DM */
@@ -3074,7 +3142,7 @@
else
dm_margin = left_edge[0] - mid;
- scc_mgr_apply_group_dm_out1_delay(mid);
+ scc_mgr_apply_group_dm_out1_delay(seq, mid);
writel(0, &sdr_scc_mgr->update);
debug_cond(DLEVEL >= 2,
@@ -3082,7 +3150,7 @@
__func__, __LINE__, left_edge[0], right_edge[0],
mid, dm_margin);
/* Export values. */
- gbl->fom_out += dq_margin + dqs_margin;
+ seq->gbl.fom_out += dq_margin + dqs_margin;
debug_cond(DLEVEL >= 2,
"%s:%d write_center: dq_margin=%d dqs_margin=%d dm_margin=%d\n",
@@ -3111,7 +3179,8 @@
* This function implements UniPHY calibration Stage 2, as explained in
* detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
*/
-static int rw_mgr_mem_calibrate_writes(const u32 rank_bgn, const u32 group,
+static int rw_mgr_mem_calibrate_writes(struct socfpga_sdrseq *seq,
+ const u32 rank_bgn, const u32 group,
const u32 test_bgn)
{
int ret;
@@ -3123,9 +3192,10 @@
reg_file_set_stage(CAL_STAGE_WRITES);
reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
- ret = rw_mgr_mem_calibrate_writes_center(rank_bgn, group, test_bgn);
+ ret = rw_mgr_mem_calibrate_writes_center(seq, rank_bgn, group,
+ test_bgn);
if (ret)
- set_failing_group_stage(group, CAL_STAGE_WRITES,
+ set_failing_group_stage(seq, group, CAL_STAGE_WRITES,
CAL_SUBSTAGE_WRITES_CENTER);
return ret;
@@ -3136,29 +3206,30 @@
*
* Precharge all banks and activate row 0 in bank "000..." and bank "111...".
*/
-static void mem_precharge_and_activate(void)
+static void mem_precharge_and_activate(struct socfpga_sdrseq *seq)
{
int r;
- for (r = 0; r < rwcfg->mem_number_of_ranks; r++) {
+ for (r = 0; r < seq->rwcfg->mem_number_of_ranks; r++) {
/* Set rank. */
- set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
+ set_rank_and_odt_mask(seq, r, RW_MGR_ODT_MODE_OFF);
/* Precharge all banks. */
- writel(rwcfg->precharge_all, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ writel(seq->rwcfg->precharge_all, SDR_PHYGRP_RWMGRGRP_ADDRESS |
RW_MGR_RUN_SINGLE_GROUP_OFFSET);
writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
- writel(rwcfg->activate_0_and_1_wait1,
+ writel(seq->rwcfg->activate_0_and_1_wait1,
&sdr_rw_load_jump_mgr_regs->load_jump_add0);
writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
- writel(rwcfg->activate_0_and_1_wait2,
+ writel(seq->rwcfg->activate_0_and_1_wait2,
&sdr_rw_load_jump_mgr_regs->load_jump_add1);
/* Activate rows. */
- writel(rwcfg->activate_0_and_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
- RW_MGR_RUN_SINGLE_GROUP_OFFSET);
+ writel(seq->rwcfg->activate_0_and_1,
+ SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET);
}
}
@@ -3167,14 +3238,15 @@
*
* Configure memory RLAT and WLAT parameters.
*/
-static void mem_init_latency(void)
+static void mem_init_latency(struct socfpga_sdrseq *seq)
{
/*
* For AV/CV, LFIFO is hardened and always runs at full rate
* so max latency in AFI clocks, used here, is correspondingly
* smaller.
*/
- const u32 max_latency = (1 << misccfg->max_latency_count_width) - 1;
+ const u32 max_latency = (1 << seq->misccfg->max_latency_count_width)
+ - 1;
u32 rlat, wlat;
debug("%s:%d\n", __func__, __LINE__);
@@ -3186,17 +3258,17 @@
wlat = readl(&data_mgr->t_wl_add);
wlat += readl(&data_mgr->mem_t_add);
- gbl->rw_wl_nop_cycles = wlat - 1;
+ seq->gbl.rw_wl_nop_cycles = wlat - 1;
/* Read in readl latency. */
rlat = readl(&data_mgr->t_rl_add);
/* Set a pretty high read latency initially. */
- gbl->curr_read_lat = rlat + 16;
- if (gbl->curr_read_lat > max_latency)
- gbl->curr_read_lat = max_latency;
+ seq->gbl.curr_read_lat = rlat + 16;
+ if (seq->gbl.curr_read_lat > max_latency)
+ seq->gbl.curr_read_lat = max_latency;
- writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
+ writel(seq->gbl.curr_read_lat, &phy_mgr_cfg->phy_rlat);
/* Advertise write latency. */
writel(wlat, &phy_mgr_cfg->afi_wlat);
@@ -3207,22 +3279,22 @@
*
* Set VFIFO and LFIFO to instant-on settings in skip calibration mode.
*/
-static void mem_skip_calibrate(void)
+static void mem_skip_calibrate(struct socfpga_sdrseq *seq)
{
u32 vfifo_offset;
u32 i, j, r;
debug("%s:%d\n", __func__, __LINE__);
/* Need to update every shadow register set used by the interface */
- for (r = 0; r < rwcfg->mem_number_of_ranks;
+ for (r = 0; r < seq->rwcfg->mem_number_of_ranks;
r += NUM_RANKS_PER_SHADOW_REG) {
/*
* Set output phase alignment settings appropriate for
* skip calibration.
*/
- for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) {
+ for (i = 0; i < seq->rwcfg->mem_if_read_dqs_width; i++) {
scc_mgr_set_dqs_en_phase(i, 0);
- if (iocfg->dll_chain_length == 6)
+ if (seq->iocfg->dll_chain_length == 6)
scc_mgr_set_dqdqs_output_phase(i, 6);
else
scc_mgr_set_dqdqs_output_phase(i, 7);
@@ -3245,20 +3317,22 @@
* Hence, to make DQS aligned to CK, we need to delay
* DQS by:
* (720 - 90 - 180 - 2) *
- * (360 / iocfg->dll_chain_length)
+ * (360 / seq->iocfg->dll_chain_length)
*
- * Dividing the above by (360 / iocfg->dll_chain_length)
+ * Dividing the above by
+ (360 / seq->iocfg->dll_chain_length)
* gives us the number of ptaps, which simplies to:
*
- * (1.25 * iocfg->dll_chain_length - 2)
+ * (1.25 * seq->iocfg->dll_chain_length - 2)
*/
scc_mgr_set_dqdqs_output_phase(i,
- ((125 * iocfg->dll_chain_length) / 100) - 2);
+ ((125 * seq->iocfg->dll_chain_length)
+ / 100) - 2);
}
writel(0xff, &sdr_scc_mgr->dqs_ena);
writel(0xff, &sdr_scc_mgr->dqs_io_ena);
- for (i = 0; i < rwcfg->mem_if_write_dqs_width; i++) {
+ for (i = 0; i < seq->rwcfg->mem_if_write_dqs_width; i++) {
writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
SCC_MGR_GROUP_COUNTER_OFFSET);
}
@@ -3268,7 +3342,7 @@
}
/* Compensate for simulation model behaviour */
- for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) {
+ for (i = 0; i < seq->rwcfg->mem_if_read_dqs_width; i++) {
scc_mgr_set_dqs_bus_in_delay(i, 10);
scc_mgr_load_dqs(i);
}
@@ -3278,7 +3352,7 @@
* ArriaV has hard FIFOs that can only be initialized by incrementing
* in sequencer.
*/
- vfifo_offset = misccfg->calib_vfifo_offset;
+ vfifo_offset = seq->misccfg->calib_vfifo_offset;
for (j = 0; j < vfifo_offset; j++)
writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
writel(0, &phy_mgr_cmd->fifo_reset);
@@ -3287,8 +3361,8 @@
* For Arria V and Cyclone V with hard LFIFO, we get the skip-cal
* setting from generation-time constant.
*/
- gbl->curr_read_lat = misccfg->calib_lfifo_offset;
- writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
+ seq->gbl.curr_read_lat = seq->misccfg->calib_lfifo_offset;
+ writel(seq->gbl.curr_read_lat, &phy_mgr_cfg->phy_rlat);
}
/**
@@ -3296,7 +3370,7 @@
*
* Perform memory calibration.
*/
-static u32 mem_calibrate(void)
+static u32 mem_calibrate(struct socfpga_sdrseq *seq)
{
u32 i;
u32 rank_bgn, sr;
@@ -3306,25 +3380,25 @@
u32 failing_groups = 0;
u32 group_failed = 0;
- const u32 rwdqs_ratio = rwcfg->mem_if_read_dqs_width /
- rwcfg->mem_if_write_dqs_width;
+ const u32 rwdqs_ratio = seq->rwcfg->mem_if_read_dqs_width /
+ seq->rwcfg->mem_if_write_dqs_width;
debug("%s:%d\n", __func__, __LINE__);
/* Initialize the data settings */
- gbl->error_substage = CAL_SUBSTAGE_NIL;
- gbl->error_stage = CAL_STAGE_NIL;
- gbl->error_group = 0xff;
- gbl->fom_in = 0;
- gbl->fom_out = 0;
+ seq->gbl.error_substage = CAL_SUBSTAGE_NIL;
+ seq->gbl.error_stage = CAL_STAGE_NIL;
+ seq->gbl.error_group = 0xff;
+ seq->gbl.fom_in = 0;
+ seq->gbl.fom_out = 0;
/* Initialize WLAT and RLAT. */
- mem_init_latency();
+ mem_init_latency(seq);
/* Initialize bit slips. */
- mem_precharge_and_activate();
+ mem_precharge_and_activate(seq);
- for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) {
+ for (i = 0; i < seq->rwcfg->mem_if_read_dqs_width; i++) {
writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
SCC_MGR_GROUP_COUNTER_OFFSET);
/* Only needed once to set all groups, pins, DQ, DQS, DM. */
@@ -3335,12 +3409,12 @@
}
/* Calibration is skipped. */
- if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
+ if ((seq->dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
/*
* Set VFIFO and LFIFO to instant-on settings in skip
* calibration mode.
*/
- mem_skip_calibrate();
+ mem_skip_calibrate(seq);
/*
* Do not remove this line as it makes sure all of our
@@ -3356,13 +3430,13 @@
* Zero all delay chain/phase settings for all
* groups and all shadow register sets.
*/
- scc_mgr_zero_all();
+ scc_mgr_zero_all(seq);
run_groups = ~0;
for (write_group = 0, write_test_bgn = 0; write_group
- < rwcfg->mem_if_write_dqs_width; write_group++,
- write_test_bgn += rwcfg->mem_dq_per_write_dqs) {
+ < seq->rwcfg->mem_if_write_dqs_width; write_group++,
+ write_test_bgn += seq->rwcfg->mem_dq_per_write_dqs) {
/* Initialize the group failure */
group_failed = 0;
@@ -3376,22 +3450,22 @@
writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
SCC_MGR_GROUP_COUNTER_OFFSET);
- scc_mgr_zero_group(write_group, 0);
+ scc_mgr_zero_group(seq, write_group, 0);
for (read_group = write_group * rwdqs_ratio,
read_test_bgn = 0;
read_group < (write_group + 1) * rwdqs_ratio;
read_group++,
- read_test_bgn += rwcfg->mem_dq_per_read_dqs) {
+ read_test_bgn += seq->rwcfg->mem_dq_per_read_dqs) {
if (STATIC_CALIB_STEPS & CALIB_SKIP_VFIFO)
continue;
/* Calibrate the VFIFO */
- if (rw_mgr_mem_calibrate_vfifo(read_group,
+ if (rw_mgr_mem_calibrate_vfifo(seq, read_group,
read_test_bgn))
continue;
- if (!(gbl->phy_debug_mode_flags &
+ if (!(seq->gbl.phy_debug_mode_flags &
PHY_DEBUG_SWEEP_ALL_GROUPS))
return 0;
@@ -3401,7 +3475,7 @@
/* Calibrate the output side */
for (rank_bgn = 0, sr = 0;
- rank_bgn < rwcfg->mem_number_of_ranks;
+ rank_bgn < seq->rwcfg->mem_number_of_ranks;
rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
continue;
@@ -3412,13 +3486,13 @@
continue;
/* Calibrate WRITEs */
- if (!rw_mgr_mem_calibrate_writes(rank_bgn,
+ if (!rw_mgr_mem_calibrate_writes(seq, rank_bgn,
write_group,
write_test_bgn))
continue;
group_failed = 1;
- if (!(gbl->phy_debug_mode_flags &
+ if (!(seq->gbl.phy_debug_mode_flags &
PHY_DEBUG_SWEEP_ALL_GROUPS))
return 0;
}
@@ -3431,15 +3505,16 @@
read_test_bgn = 0;
read_group < (write_group + 1) * rwdqs_ratio;
read_group++,
- read_test_bgn += rwcfg->mem_dq_per_read_dqs) {
+ read_test_bgn += seq->rwcfg->mem_dq_per_read_dqs) {
if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
continue;
- if (!rw_mgr_mem_calibrate_vfifo_end(read_group,
+ if (!rw_mgr_mem_calibrate_vfifo_end(seq,
+ read_group,
read_test_bgn))
continue;
- if (!(gbl->phy_debug_mode_flags &
+ if (!(seq->gbl.phy_debug_mode_flags &
PHY_DEBUG_SWEEP_ALL_GROUPS))
return 0;
@@ -3465,7 +3540,7 @@
continue;
/* Calibrate the LFIFO */
- if (!rw_mgr_mem_calibrate_lfifo())
+ if (!rw_mgr_mem_calibrate_lfifo(seq))
return 0;
}
@@ -3482,7 +3557,7 @@
*
* This function triggers the entire memory calibration procedure.
*/
-static int run_mem_calibrate(void)
+static int run_mem_calibrate(struct socfpga_sdrseq *seq)
{
int pass;
u32 ctrl_cfg;
@@ -3497,17 +3572,17 @@
writel(ctrl_cfg & ~SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK,
&sdr_ctrl->ctrl_cfg);
- phy_mgr_initialize();
- rw_mgr_mem_initialize();
+ phy_mgr_initialize(seq);
+ rw_mgr_mem_initialize(seq);
/* Perform the actual memory calibration. */
- pass = mem_calibrate();
+ pass = mem_calibrate(seq);
- mem_precharge_and_activate();
+ mem_precharge_and_activate(seq);
writel(0, &phy_mgr_cmd->fifo_reset);
/* Handoff. */
- rw_mgr_mem_handoff();
+ rw_mgr_mem_handoff(seq);
/*
* In Hard PHY this is a 2-bit control:
* 0: AFI Mux Select
@@ -3528,25 +3603,25 @@
* This function reports the results of the memory calibration
* and writes debug information into the register file.
*/
-static void debug_mem_calibrate(int pass)
+static void debug_mem_calibrate(struct socfpga_sdrseq *seq, int pass)
{
u32 debug_info;
if (pass) {
debug("%s: CALIBRATION PASSED\n", __FILE__);
- gbl->fom_in /= 2;
- gbl->fom_out /= 2;
+ seq->gbl.fom_in /= 2;
+ seq->gbl.fom_out /= 2;
- if (gbl->fom_in > 0xff)
- gbl->fom_in = 0xff;
+ if (seq->gbl.fom_in > 0xff)
+ seq->gbl.fom_in = 0xff;
- if (gbl->fom_out > 0xff)
- gbl->fom_out = 0xff;
+ if (seq->gbl.fom_out > 0xff)
+ seq->gbl.fom_out = 0xff;
/* Update the FOM in the register file */
- debug_info = gbl->fom_in;
- debug_info |= gbl->fom_out << 8;
+ debug_info = seq->gbl.fom_in;
+ debug_info |= seq->gbl.fom_out << 8;
writel(debug_info, &sdr_reg_file->fom);
writel(debug_info, &phy_mgr_cfg->cal_debug_info);
@@ -3554,18 +3629,18 @@
} else {
debug("%s: CALIBRATION FAILED\n", __FILE__);
- debug_info = gbl->error_stage;
- debug_info |= gbl->error_substage << 8;
- debug_info |= gbl->error_group << 16;
+ debug_info = seq->gbl.error_stage;
+ debug_info |= seq->gbl.error_substage << 8;
+ debug_info |= seq->gbl.error_group << 16;
writel(debug_info, &sdr_reg_file->failing_stage);
writel(debug_info, &phy_mgr_cfg->cal_debug_info);
writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status);
/* Update the failing group/stage in the register file */
- debug_info = gbl->error_stage;
- debug_info |= gbl->error_substage << 8;
- debug_info |= gbl->error_group << 16;
+ debug_info = seq->gbl.error_stage;
+ debug_info |= seq->gbl.error_substage << 8;
+ debug_info |= seq->gbl.error_group << 16;
writel(debug_info, &sdr_reg_file->failing_stage);
}
@@ -3599,10 +3674,11 @@
*
* Initialize SDR register file.
*/
-static void initialize_reg_file(void)
+static void initialize_reg_file(struct socfpga_sdrseq *seq)
{
/* Initialize the register file with the correct data */
- writel(misccfg->reg_file_init_seq_signature, &sdr_reg_file->signature);
+ writel(seq->misccfg->reg_file_init_seq_signature,
+ &sdr_reg_file->signature);
writel(0, &sdr_reg_file->debug_data_addr);
writel(0, &sdr_reg_file->cur_stage);
writel(0, &sdr_reg_file->fom);
@@ -3666,15 +3742,15 @@
*
* Initialize the register file with usable initial data.
*/
-static void initialize_tracking(void)
+static void initialize_tracking(struct socfpga_sdrseq *seq)
{
/*
* Initialize the register file with the correct data.
* Compute usable version of value in case we skip full
* computation later.
*/
- writel(DIV_ROUND_UP(iocfg->delay_per_opa_tap,
- iocfg->delay_per_dchain_tap) - 1,
+ writel(DIV_ROUND_UP(seq->iocfg->delay_per_opa_tap,
+ seq->iocfg->delay_per_dchain_tap) - 1,
&sdr_reg_file->dtaps_per_ptap);
/* trk_sample_count */
@@ -3693,23 +3769,22 @@
&sdr_reg_file->delays);
/* mux delay */
- writel((rwcfg->idle << 24) | (rwcfg->activate_1 << 16) |
- (rwcfg->sgle_read << 8) | (rwcfg->precharge_all << 0),
+ writel((seq->rwcfg->idle << 24) | (seq->rwcfg->activate_1 << 16) |
+ (seq->rwcfg->sgle_read << 8) | (seq->rwcfg->precharge_all << 0),
&sdr_reg_file->trk_rw_mgr_addr);
- writel(rwcfg->mem_if_read_dqs_width,
+ writel(seq->rwcfg->mem_if_read_dqs_width,
&sdr_reg_file->trk_read_dqs_width);
/* trefi [7:0] */
- writel((rwcfg->refresh_all << 24) | (1000 << 0),
+ writel((seq->rwcfg->refresh_all << 24) | (1000 << 0),
&sdr_reg_file->trk_rfsh);
}
int sdram_calibration_full(struct socfpga_sdr *sdr)
{
- struct param_type my_param;
- struct gbl_type my_gbl;
u32 pass;
+ struct socfpga_sdrseq seq;
/*
* For size reasons, this file uses hard coded addresses.
@@ -3718,60 +3793,61 @@
if (sdr != (struct socfpga_sdr *)SOCFPGA_SDR_ADDRESS)
return -ENODEV;
- memset(&my_param, 0, sizeof(my_param));
- memset(&my_gbl, 0, sizeof(my_gbl));
+ memset(&seq, 0, sizeof(seq));
- param = &my_param;
- gbl = &my_gbl;
-
- rwcfg = socfpga_get_sdram_rwmgr_config();
- iocfg = socfpga_get_sdram_io_config();
- misccfg = socfpga_get_sdram_misc_config();
+ seq.rwcfg = socfpga_get_sdram_rwmgr_config();
+ seq.iocfg = socfpga_get_sdram_io_config();
+ seq.misccfg = socfpga_get_sdram_misc_config();
/* Set the calibration enabled by default */
- gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
+ seq.gbl.phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
/*
* Only sweep all groups (regardless of fail state) by default
* Set enabled read test by default.
*/
#if DISABLE_GUARANTEED_READ
- gbl->phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ;
+ seq.gbl.phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ;
#endif
/* Initialize the register file */
- initialize_reg_file();
+ initialize_reg_file(&seq);
/* Initialize any PHY CSR */
initialize_hps_phy();
scc_mgr_initialize();
- initialize_tracking();
+ initialize_tracking(&seq);
debug("%s: Preparing to start memory calibration\n", __FILE__);
debug("%s:%d\n", __func__, __LINE__);
debug_cond(DLEVEL >= 1,
"DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
- rwcfg->mem_number_of_ranks, rwcfg->mem_number_of_cs_per_dimm,
- rwcfg->mem_dq_per_read_dqs, rwcfg->mem_dq_per_write_dqs,
- rwcfg->mem_virtual_groups_per_read_dqs,
- rwcfg->mem_virtual_groups_per_write_dqs);
+ seq.rwcfg->mem_number_of_ranks,
+ seq.rwcfg->mem_number_of_cs_per_dimm,
+ seq.rwcfg->mem_dq_per_read_dqs,
+ seq.rwcfg->mem_dq_per_write_dqs,
+ seq.rwcfg->mem_virtual_groups_per_read_dqs,
+ seq.rwcfg->mem_virtual_groups_per_write_dqs);
debug_cond(DLEVEL >= 1,
"dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
- rwcfg->mem_if_read_dqs_width, rwcfg->mem_if_write_dqs_width,
- rwcfg->mem_data_width, rwcfg->mem_data_mask_width,
- iocfg->delay_per_opa_tap, iocfg->delay_per_dchain_tap);
+ seq.rwcfg->mem_if_read_dqs_width,
+ seq.rwcfg->mem_if_write_dqs_width,
+ seq.rwcfg->mem_data_width, seq.rwcfg->mem_data_mask_width,
+ seq.iocfg->delay_per_opa_tap,
+ seq.iocfg->delay_per_dchain_tap);
debug_cond(DLEVEL >= 1, "dtap_dqsen_delay=%u, dll=%u",
- iocfg->delay_per_dqs_en_dchain_tap, iocfg->dll_chain_length);
+ seq.iocfg->delay_per_dqs_en_dchain_tap,
+ seq.iocfg->dll_chain_length);
debug_cond(DLEVEL >= 1,
"max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
- iocfg->dqs_en_phase_max, iocfg->dqdqs_out_phase_max,
- iocfg->dqs_en_delay_max, iocfg->dqs_in_delay_max);
+ seq.iocfg->dqs_en_phase_max, seq.iocfg->dqdqs_out_phase_max,
+ seq.iocfg->dqs_en_delay_max, seq.iocfg->dqs_in_delay_max);
debug_cond(DLEVEL >= 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
- iocfg->io_in_delay_max, iocfg->io_out1_delay_max,
- iocfg->io_out2_delay_max);
+ seq.iocfg->io_in_delay_max, seq.iocfg->io_out1_delay_max,
+ seq.iocfg->io_out2_delay_max);
debug_cond(DLEVEL >= 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
- iocfg->dqs_in_reserve, iocfg->dqs_out_reserve);
+ seq.iocfg->dqs_in_reserve, seq.iocfg->dqs_out_reserve);
hc_initialize_rom_data();
@@ -3783,17 +3859,17 @@
* Load global needed for those actions that require
* some dynamic calibration support.
*/
- dyn_calib_steps = STATIC_CALIB_STEPS;
+ seq.dyn_calib_steps = STATIC_CALIB_STEPS;
/*
* Load global to allow dynamic selection of delay loop settings
* based on calibration mode.
*/
- if (!(dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS))
- skip_delay_mask = 0xff;
+ if (!(seq.dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS))
+ seq.skip_delay_mask = 0xff;
else
- skip_delay_mask = 0x0;
+ seq.skip_delay_mask = 0x0;
- pass = run_mem_calibrate();
- debug_mem_calibrate(pass);
+ pass = run_mem_calibrate(&seq);
+ debug_mem_calibrate(&seq, pass);
return pass;
}
diff --git a/drivers/ddr/altera/sequencer.h b/drivers/ddr/altera/sequencer.h
index d7f6935..4a03c3f 100644
--- a/drivers/ddr/altera/sequencer.h
+++ b/drivers/ddr/altera/sequencer.h
@@ -6,14 +6,16 @@
#ifndef _SEQUENCER_H_
#define _SEQUENCER_H_
-#define RW_MGR_NUM_DM_PER_WRITE_GROUP (rwcfg->mem_data_mask_width \
- / rwcfg->mem_if_write_dqs_width)
-#define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP (rwcfg->true_mem_data_mask_width \
- / rwcfg->mem_if_write_dqs_width)
+#define RW_MGR_NUM_DM_PER_WRITE_GROUP (seq->rwcfg->mem_data_mask_width \
+ / seq->rwcfg->mem_if_write_dqs_width)
+#define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP ( \
+ seq->rwcfg->true_mem_data_mask_width \
+ / seq->rwcfg->mem_if_write_dqs_width)
-#define RW_MGR_NUM_DQS_PER_WRITE_GROUP (rwcfg->mem_if_read_dqs_width \
- / rwcfg->mem_if_write_dqs_width)
-#define NUM_RANKS_PER_SHADOW_REG (rwcfg->mem_number_of_ranks / NUM_SHADOW_REGS)
+#define RW_MGR_NUM_DQS_PER_WRITE_GROUP (seq->rwcfg->mem_if_read_dqs_width \
+ / seq->rwcfg->mem_if_write_dqs_width)
+#define NUM_RANKS_PER_SHADOW_REG (seq->rwcfg->mem_number_of_ranks \
+ / NUM_SHADOW_REGS)
#define RW_MGR_RUN_SINGLE_GROUP_OFFSET 0x0
#define RW_MGR_RUN_ALL_GROUPS_OFFSET 0x0400
@@ -256,6 +258,26 @@
u8 _align9[0xea4];
};
+struct socfpga_sdrseq {
+ const struct socfpga_sdram_rw_mgr_config *rwcfg;
+ const struct socfpga_sdram_io_config *iocfg;
+ const struct socfpga_sdram_misc_config *misccfg;
+ /* calibration steps requested by the rtl */
+ u16 dyn_calib_steps;
+ /*
+ * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
+ * instead of static, we use boolean logic to select between
+ * non-skip and skip values
+ *
+ * The mask is set to include all bits when not-skipping, but is
+ * zero when skipping
+ */
+
+ u16 skip_delay_mask; /* mask off bits when skipping/not-skipping */
+ struct gbl_type gbl;
+ struct param_type param;
+};
+
int sdram_calibration_full(struct socfpga_sdr *sdr);
#endif /* _SEQUENCER_H_ */
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index 30f7863..17a4a82 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -4,6 +4,7 @@
*/
#include <common.h>
+#include <env.h>
#include <asm/io.h>
#include <fsl_ddr_sdram.h>
#include <asm/processor.h>
diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c
index 4de0eae..8e171e6 100644
--- a/drivers/ddr/fsl/interactive.c
+++ b/drivers/ddr/fsl/interactive.c
@@ -13,6 +13,7 @@
#include <common.h>
#include <cli.h>
+#include <env.h>
#include <linux/ctype.h>
#include <asm/types.h>
#include <asm/io.h>
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index e1f69a1..0aa6aed 100644
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -10,6 +10,7 @@
*/
#include <common.h>
+#include <dm.h>
#include <i2c.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr.h>
@@ -82,17 +83,82 @@
#endif
+#if defined(CONFIG_DM_I2C)
+#define DEV_TYPE struct udevice
+#else
+/* Local udevice */
+struct ludevice {
+ u8 chip;
+};
+
+#define DEV_TYPE struct ludevice
+
+#endif
+
#define SPD_SPA0_ADDRESS 0x36
#define SPD_SPA1_ADDRESS 0x37
+static int ddr_i2c_read(DEV_TYPE *dev, unsigned int addr,
+ int alen, uint8_t *buf, int len)
+{
+ int ret;
+
+#ifdef CONFIG_DM_I2C
+ ret = dm_i2c_read(dev, 0, buf, len);
+#else
+ ret = i2c_read(dev->chip, addr, alen, buf, len);
+#endif
+
+ return ret;
+}
+
+#ifdef CONFIG_SYS_FSL_DDR4
+static int ddr_i2c_dummy_write(unsigned int chip_addr)
+{
+ uint8_t buf = 0;
+
+#ifdef CONFIG_DM_I2C
+ struct udevice *dev;
+ int ret;
+
+ ret = i2c_get_chip_for_busnum(CONFIG_SYS_SPD_BUS_NUM, chip_addr,
+ 1, &dev);
+ if (ret) {
+ printf("%s: Cannot find udev for a bus %d\n", __func__,
+ CONFIG_SYS_SPD_BUS_NUM);
+ return ret;
+ }
+
+ return dm_i2c_write(dev, 0, &buf, 1);
+#else
+ return i2c_write(chip_addr, 0, 1, &buf, 1);
+#endif
+
+ return 0;
+}
+#endif
+
static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
{
int ret;
-#ifdef CONFIG_SYS_FSL_DDR4
- uint8_t dummy = 0;
-#endif
+ DEV_TYPE *dev;
+
+#if defined(CONFIG_DM_I2C)
+ ret = i2c_get_chip_for_busnum(CONFIG_SYS_SPD_BUS_NUM, i2c_address,
+ 1, &dev);
+ if (ret) {
+ printf("%s: Cannot find udev for a bus %d\n", __func__,
+ CONFIG_SYS_SPD_BUS_NUM);
+ return;
+ }
+#else /* Non DM I2C support - will be removed */
+ struct ludevice ldev = {
+ .chip = i2c_address,
+ };
+ dev = &ldev;
i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
+#endif
#ifdef CONFIG_SYS_FSL_DDR4
/*
@@ -101,18 +167,19 @@
* To access the upper 256 bytes, we need to set EE page address to 1
* See Jedec standar No. 21-C for detail
*/
- i2c_write(SPD_SPA0_ADDRESS, 0, 1, &dummy, 1);
- ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, 256);
+ ddr_i2c_dummy_write(SPD_SPA0_ADDRESS);
+ ret = ddr_i2c_read(dev, 0, 1, (uchar *)spd, 256);
if (!ret) {
- i2c_write(SPD_SPA1_ADDRESS, 0, 1, &dummy, 1);
- ret = i2c_read(i2c_address, 0, 1,
- (uchar *)((ulong)spd + 256),
- min(256,
- (int)sizeof(generic_spd_eeprom_t) - 256));
+ ddr_i2c_dummy_write(SPD_SPA1_ADDRESS);
+ ret = ddr_i2c_read(dev, 0, 1, (uchar *)((ulong)spd + 256),
+ min(256,
+ (int)sizeof(generic_spd_eeprom_t)
+ - 256));
}
+
#else
- ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
- sizeof(generic_spd_eeprom_t));
+ ret = ddr_i2c_read(dev, 0, 1, (uchar *)spd,
+ sizeof(generic_spd_eeprom_t));
#endif
if (ret) {
diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c
index 4573ffa..b917931 100644
--- a/drivers/ddr/fsl/options.c
+++ b/drivers/ddr/fsl/options.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
+#include <env.h>
#include <hwconfig.h>
#include <fsl_ddr_sdram.h>
diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c
index 3189495..d2b67b1 100644
--- a/drivers/dfu/dfu.c
+++ b/drivers/dfu/dfu.c
@@ -7,6 +7,7 @@
*/
#include <common.h>
+#include <env.h>
#include <errno.h>
#include <malloc.h>
#include <mmc.h>
diff --git a/drivers/fastboot/fb_command.c b/drivers/fastboot/fb_command.c
index 200f991..4864344 100644
--- a/drivers/fastboot/fb_command.c
+++ b/drivers/fastboot/fb_command.c
@@ -4,6 +4,7 @@
*/
#include <common.h>
+#include <env.h>
#include <fastboot.h>
#include <fastboot-internal.h>
#include <fb_mmc.h>
diff --git a/drivers/fastboot/fb_common.c b/drivers/fastboot/fb_common.c
index 17eca73..e76af8e 100644
--- a/drivers/fastboot/fb_common.c
+++ b/drivers/fastboot/fb_common.c
@@ -11,6 +11,7 @@
*/
#include <common.h>
+#include <env.h>
#include <fastboot.h>
#include <net/fastboot.h>
diff --git a/drivers/fastboot/fb_getvar.c b/drivers/fastboot/fb_getvar.c
index bf957e8..95cb434 100644
--- a/drivers/fastboot/fb_getvar.c
+++ b/drivers/fastboot/fb_getvar.c
@@ -4,6 +4,7 @@
*/
#include <common.h>
+#include <env.h>
#include <fastboot.h>
#include <fastboot-internal.h>
#include <fb_mmc.h>
@@ -12,14 +13,13 @@
#include <version.h>
static void getvar_version(char *var_parameter, char *response);
-static void getvar_bootloader_version(char *var_parameter, char *response);
+static void getvar_version_bootloader(char *var_parameter, char *response);
static void getvar_downloadsize(char *var_parameter, char *response);
static void getvar_serialno(char *var_parameter, char *response);
static void getvar_version_baseband(char *var_parameter, char *response);
static void getvar_product(char *var_parameter, char *response);
static void getvar_platform(char *var_parameter, char *response);
static void getvar_current_slot(char *var_parameter, char *response);
-static void getvar_slot_suffixes(char *var_parameter, char *response);
#if CONFIG_IS_ENABLED(FASTBOOT_FLASH)
static void getvar_has_slot(char *var_parameter, char *response);
#endif
@@ -29,6 +29,7 @@
#if CONFIG_IS_ENABLED(FASTBOOT_FLASH)
static void getvar_partition_size(char *part_name, char *response);
#endif
+static void getvar_is_userspace(char *var_parameter, char *response);
static const struct {
const char *variable;
@@ -38,11 +39,8 @@
.variable = "version",
.dispatch = getvar_version
}, {
- .variable = "bootloader-version",
- .dispatch = getvar_bootloader_version
- }, {
.variable = "version-bootloader",
- .dispatch = getvar_bootloader_version
+ .dispatch = getvar_version_bootloader
}, {
.variable = "downloadsize",
.dispatch = getvar_downloadsize
@@ -64,9 +62,6 @@
}, {
.variable = "current-slot",
.dispatch = getvar_current_slot
- }, {
- .variable = "slot-suffixes",
- .dispatch = getvar_slot_suffixes
#if CONFIG_IS_ENABLED(FASTBOOT_FLASH)
}, {
.variable = "has-slot",
@@ -82,6 +77,9 @@
.variable = "partition-size",
.dispatch = getvar_partition_size
#endif
+ }, {
+ .variable = "is-userspace",
+ .dispatch = getvar_is_userspace
}
};
@@ -131,7 +129,7 @@
fastboot_okay(FASTBOOT_VERSION, response);
}
-static void getvar_bootloader_version(char *var_parameter, char *response)
+static void getvar_version_bootloader(char *var_parameter, char *response)
{
fastboot_okay(U_BOOT_VERSION, response);
}
@@ -182,11 +180,6 @@
fastboot_okay("a", response);
}
-static void getvar_slot_suffixes(char *var_parameter, char *response)
-{
- fastboot_okay("a,b", response);
-}
-
#if CONFIG_IS_ENABLED(FASTBOOT_FLASH)
static void getvar_has_slot(char *part_name, char *response)
{
@@ -252,6 +245,11 @@
}
#endif
+static void getvar_is_userspace(char *var_parameter, char *response)
+{
+ fastboot_okay("no", response);
+}
+
/**
* fastboot_getvar() - Writes variable indicated by cmd_parameter to response.
*
diff --git a/drivers/fastboot/fb_mmc.c b/drivers/fastboot/fb_mmc.c
index 0a335db..b0b19c5 100644
--- a/drivers/fastboot/fb_mmc.c
+++ b/drivers/fastboot/fb_mmc.c
@@ -6,6 +6,7 @@
#include <config.h>
#include <common.h>
#include <blk.h>
+#include <env.h>
#include <fastboot.h>
#include <fastboot-internal.h>
#include <fb_mmc.h>
diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig
index 7d8f161..873bc8c 100644
--- a/drivers/firmware/Kconfig
+++ b/drivers/firmware/Kconfig
@@ -1,9 +1,13 @@
config FIRMWARE
bool "Enable Firmware driver support"
+config SPL_FIRMWARE
+ bool "Enable Firmware driver support in SPL"
+ depends on FIRMWARE
+
config SPL_ARM_PSCI_FW
bool
- select FIRMWARE
+ select SPL_FIRMWARE
config ARM_PSCI_FW
bool
@@ -13,6 +17,7 @@
tristate "TI System Control Interface (TISCI) Message Protocol"
depends on K3_SEC_PROXY
select FIRMWARE
+ select SPL_FIRMWARE if SPL
help
TI System Control Interface (TISCI) Message Protocol is used to manage
compute systems such as ARM, DSP etc with the system controller in
diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
index 303aa6a..62b1dc2 100644
--- a/drivers/firmware/ti_sci.c
+++ b/drivers/firmware/ti_sci.c
@@ -87,11 +87,18 @@
struct mbox_chan chan_notify;
struct ti_sci_xfer xfer;
struct list_head list;
+ struct list_head dev_list;
bool is_secure;
u8 host_id;
u8 seq;
};
+struct ti_sci_exclusive_dev {
+ u32 id;
+ u32 count;
+ struct list_head list;
+};
+
#define handle_to_ti_sci_info(h) container_of(h, struct ti_sci_info, handle)
/**
@@ -101,7 +108,8 @@
* @msg_flags: Flag to set for the message
* @buf: Buffer to be send to mailbox channel
* @tx_message_size: transmit message size
- * @rx_message_size: receive message size
+ * @rx_message_size: receive message size. may be set to zero for send-only
+ * transactions.
*
* Helper function which is used by various command functions that are
* exposed to clients of this driver for allocating a message traffic event.
@@ -121,7 +129,8 @@
/* Ensure we have sane transfer sizes */
if (rx_message_size > info->desc->max_msg_size ||
tx_message_size > info->desc->max_msg_size ||
- rx_message_size < sizeof(*hdr) || tx_message_size < sizeof(*hdr))
+ (rx_message_size > 0 && rx_message_size < sizeof(*hdr)) ||
+ tx_message_size < sizeof(*hdr))
return ERR_PTR(-ERANGE);
info->seq = ~info->seq;
@@ -219,7 +228,9 @@
xfer->tx_message.buf = (u32 *)secure_buf;
xfer->tx_message.len += sizeof(secure_hdr);
- xfer->rx_len += sizeof(secure_hdr);
+
+ if (xfer->rx_len)
+ xfer->rx_len += sizeof(secure_hdr);
}
/* Send the message */
@@ -230,7 +241,11 @@
return ret;
}
- return ti_sci_get_response(info, xfer, &info->chan_rx);
+ /* Get response if requested */
+ if (xfer->rx_len)
+ ret = ti_sci_get_response(info, xfer, &info->chan_rx);
+
+ return ret;
}
/**
@@ -419,6 +434,47 @@
addr, size);
}
+static struct ti_sci_exclusive_dev
+*ti_sci_get_exclusive_dev(struct list_head *dev_list, u32 id)
+{
+ struct ti_sci_exclusive_dev *dev;
+
+ list_for_each_entry(dev, dev_list, list)
+ if (dev->id == id)
+ return dev;
+
+ return NULL;
+}
+
+static void ti_sci_add_exclusive_dev(struct ti_sci_info *info, u32 id)
+{
+ struct ti_sci_exclusive_dev *dev;
+
+ dev = ti_sci_get_exclusive_dev(&info->dev_list, id);
+ if (dev) {
+ dev->count++;
+ return;
+ }
+
+ dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+ dev->id = id;
+ dev->count = 1;
+ INIT_LIST_HEAD(&dev->list);
+ list_add_tail(&dev->list, &info->dev_list);
+}
+
+static void ti_sci_delete_exclusive_dev(struct ti_sci_info *info, u32 id)
+{
+ struct ti_sci_exclusive_dev *dev;
+
+ dev = ti_sci_get_exclusive_dev(&info->dev_list, id);
+ if (!dev)
+ return;
+
+ if (dev->count > 0)
+ dev->count--;
+}
+
/**
* ti_sci_set_device_state() - Set device state helper
* @handle: pointer to TI SCI handle
@@ -466,6 +522,54 @@
if (!ti_sci_is_response_ack(resp))
return -ENODEV;
+ if (state == MSG_DEVICE_SW_STATE_AUTO_OFF)
+ ti_sci_delete_exclusive_dev(info, id);
+ else if (flags & MSG_FLAG_DEVICE_EXCLUSIVE)
+ ti_sci_add_exclusive_dev(info, id);
+
+ return ret;
+}
+
+/**
+ * ti_sci_set_device_state_no_wait() - Set device state helper without
+ * requesting or waiting for a response.
+ * @handle: pointer to TI SCI handle
+ * @id: Device identifier
+ * @flags: flags to setup for the device
+ * @state: State to move the device to
+ *
+ * Return: 0 if all went well, else returns appropriate error value.
+ */
+static int ti_sci_set_device_state_no_wait(const struct ti_sci_handle *handle,
+ u32 id, u32 flags, u8 state)
+{
+ struct ti_sci_msg_req_set_device_state req;
+ struct ti_sci_info *info;
+ struct ti_sci_xfer *xfer;
+ int ret = 0;
+
+ if (IS_ERR(handle))
+ return PTR_ERR(handle);
+ if (!handle)
+ return -EINVAL;
+
+ info = handle_to_ti_sci_info(handle);
+
+ xfer = ti_sci_setup_one_xfer(info, TI_SCI_MSG_SET_DEVICE_STATE,
+ flags | TI_SCI_FLAG_REQ_GENERIC_NORESPONSE,
+ (u32 *)&req, sizeof(req), 0);
+ if (IS_ERR(xfer)) {
+ ret = PTR_ERR(xfer);
+ dev_err(info->dev, "Message alloc failed(%d)\n", ret);
+ return ret;
+ }
+ req.id = id;
+ req.state = state;
+
+ ret = ti_sci_do_xfer(info, xfer);
+ if (ret)
+ dev_err(info->dev, "Mbox send fail %d\n", ret);
+
return ret;
}
@@ -547,8 +651,14 @@
*/
static int ti_sci_cmd_get_device(const struct ti_sci_handle *handle, u32 id)
{
- return ti_sci_set_device_state(handle, id,
- MSG_FLAG_DEVICE_EXCLUSIVE,
+ return ti_sci_set_device_state(handle, id, 0,
+ MSG_DEVICE_SW_STATE_ON);
+}
+
+static int ti_sci_cmd_get_device_exclusive(const struct ti_sci_handle *handle,
+ u32 id)
+{
+ return ti_sci_set_device_state(handle, id, MSG_FLAG_DEVICE_EXCLUSIVE,
MSG_DEVICE_SW_STATE_ON);
}
@@ -566,7 +676,14 @@
static int ti_sci_cmd_idle_device(const struct ti_sci_handle *handle, u32 id)
{
return ti_sci_set_device_state(handle, id,
- MSG_FLAG_DEVICE_EXCLUSIVE,
+ 0,
+ MSG_DEVICE_SW_STATE_RETENTION);
+}
+
+static int ti_sci_cmd_idle_device_exclusive(const struct ti_sci_handle *handle,
+ u32 id)
+{
+ return ti_sci_set_device_state(handle, id, MSG_FLAG_DEVICE_EXCLUSIVE,
MSG_DEVICE_SW_STATE_RETENTION);
}
@@ -583,8 +700,27 @@
*/
static int ti_sci_cmd_put_device(const struct ti_sci_handle *handle, u32 id)
{
- return ti_sci_set_device_state(handle, id,
- 0, MSG_DEVICE_SW_STATE_AUTO_OFF);
+ return ti_sci_set_device_state(handle, id, 0,
+ MSG_DEVICE_SW_STATE_AUTO_OFF);
+}
+
+static
+int ti_sci_cmd_release_exclusive_devices(const struct ti_sci_handle *handle)
+{
+ struct ti_sci_exclusive_dev *dev, *tmp;
+ struct ti_sci_info *info;
+ int i, cnt;
+
+ info = handle_to_ti_sci_info(handle);
+
+ list_for_each_entry_safe(dev, tmp, &info->dev_list, list) {
+ cnt = dev->count;
+ debug("%s: id = %d, cnt = %d\n", __func__, dev->id, cnt);
+ for (i = 0; i < cnt; i++)
+ ti_sci_cmd_put_device(handle, dev->id);
+ }
+
+ return 0;
}
/**
@@ -2027,6 +2163,137 @@
}
/**
+ * ti_sci_proc_wait_boot_status_no_wait() - Helper function to wait for a
+ * processor boot status without requesting or
+ * waiting for a response.
+ * @proc_id: Processor ID this request is for
+ * @num_wait_iterations: Total number of iterations we will check before
+ * we will timeout and give up
+ * @num_match_iterations: How many iterations should we have continued
+ * status to account for status bits glitching.
+ * This is to make sure that match occurs for
+ * consecutive checks. This implies that the
+ * worst case should consider that the stable
+ * time should at the worst be num_wait_iterations
+ * num_match_iterations to prevent timeout.
+ * @delay_per_iteration_us: Specifies how long to wait (in micro seconds)
+ * between each status checks. This is the minimum
+ * duration, and overhead of register reads and
+ * checks are on top of this and can vary based on
+ * varied conditions.
+ * @delay_before_iterations_us: Specifies how long to wait (in micro seconds)
+ * before the very first check in the first
+ * iteration of status check loop. This is the
+ * minimum duration, and overhead of register
+ * reads and checks are.
+ * @status_flags_1_set_all_wait:If non-zero, Specifies that all bits of the
+ * status matching this field requested MUST be 1.
+ * @status_flags_1_set_any_wait:If non-zero, Specifies that at least one of the
+ * bits matching this field requested MUST be 1.
+ * @status_flags_1_clr_all_wait:If non-zero, Specifies that all bits of the
+ * status matching this field requested MUST be 0.
+ * @status_flags_1_clr_any_wait:If non-zero, Specifies that at least one of the
+ * bits matching this field requested MUST be 0.
+ *
+ * Return: 0 if all goes well, else appropriate error message
+ */
+static int
+ti_sci_proc_wait_boot_status_no_wait(const struct ti_sci_handle *handle,
+ u8 proc_id,
+ u8 num_wait_iterations,
+ u8 num_match_iterations,
+ u8 delay_per_iteration_us,
+ u8 delay_before_iterations_us,
+ u32 status_flags_1_set_all_wait,
+ u32 status_flags_1_set_any_wait,
+ u32 status_flags_1_clr_all_wait,
+ u32 status_flags_1_clr_any_wait)
+{
+ struct ti_sci_msg_req_wait_proc_boot_status req;
+ struct ti_sci_info *info;
+ struct ti_sci_xfer *xfer;
+ int ret = 0;
+
+ if (IS_ERR(handle))
+ return PTR_ERR(handle);
+ if (!handle)
+ return -EINVAL;
+
+ info = handle_to_ti_sci_info(handle);
+
+ xfer = ti_sci_setup_one_xfer(info, TISCI_MSG_WAIT_PROC_BOOT_STATUS,
+ TI_SCI_FLAG_REQ_GENERIC_NORESPONSE,
+ (u32 *)&req, sizeof(req), 0);
+ if (IS_ERR(xfer)) {
+ ret = PTR_ERR(xfer);
+ dev_err(info->dev, "Message alloc failed(%d)\n", ret);
+ return ret;
+ }
+ req.processor_id = proc_id;
+ req.num_wait_iterations = num_wait_iterations;
+ req.num_match_iterations = num_match_iterations;
+ req.delay_per_iteration_us = delay_per_iteration_us;
+ req.delay_before_iterations_us = delay_before_iterations_us;
+ req.status_flags_1_set_all_wait = status_flags_1_set_all_wait;
+ req.status_flags_1_set_any_wait = status_flags_1_set_any_wait;
+ req.status_flags_1_clr_all_wait = status_flags_1_clr_all_wait;
+ req.status_flags_1_clr_any_wait = status_flags_1_clr_any_wait;
+
+ ret = ti_sci_do_xfer(info, xfer);
+ if (ret)
+ dev_err(info->dev, "Mbox send fail %d\n", ret);
+
+ return ret;
+}
+
+/**
+ * ti_sci_cmd_proc_shutdown_no_wait() - Command to shutdown a core without
+ * requesting or waiting for a response. Note that this API call
+ * should be followed by placing the respective processor into
+ * either WFE or WFI mode.
+ * @handle: Pointer to TI SCI handle
+ * @proc_id: Processor ID this request is for
+ *
+ * Return: 0 if all went well, else returns appropriate error value.
+ */
+static int ti_sci_cmd_proc_shutdown_no_wait(const struct ti_sci_handle *handle,
+ u8 proc_id)
+{
+ int ret;
+
+ /*
+ * Send the core boot status wait message waiting for either WFE or
+ * WFI without requesting or waiting for a TISCI response with the
+ * maximum wait time to give us the best chance to get to the WFE/WFI
+ * command that should follow the invocation of this API before the
+ * DMSC-internal processing of this command times out. Note that
+ * waiting for the R5 WFE/WFI flags will also work on an ARMV8 type
+ * core as the related flag bit positions are the same.
+ */
+ ret = ti_sci_proc_wait_boot_status_no_wait(handle, proc_id,
+ U8_MAX, 100, U8_MAX, U8_MAX,
+ 0, PROC_BOOT_STATUS_FLAG_R5_WFE | PROC_BOOT_STATUS_FLAG_R5_WFI,
+ 0, 0);
+ if (ret) {
+ dev_err(info->dev, "Sending core %u wait message fail %d\n",
+ proc_id, ret);
+ return ret;
+ }
+
+ /*
+ * Release a processor managed by TISCI without requesting or waiting
+ * for a response.
+ */
+ ret = ti_sci_set_device_state_no_wait(handle, proc_id, 0,
+ MSG_DEVICE_SW_STATE_AUTO_OFF);
+ if (ret)
+ dev_err(info->dev, "Sending core %u shutdown message fail %d\n",
+ proc_id, ret);
+
+ return ret;
+}
+
+/**
* ti_sci_cmd_ring_config() - configure RA ring
* @handle: pointer to TI SCI handle
* @valid_params: Bitfield defining validity of ring configuration parameters.
@@ -2632,7 +2899,9 @@
bops->board_config_pm = ti_sci_cmd_set_board_config_pm;
dops->get_device = ti_sci_cmd_get_device;
+ dops->get_device_exclusive = ti_sci_cmd_get_device_exclusive;
dops->idle_device = ti_sci_cmd_idle_device;
+ dops->idle_device_exclusive = ti_sci_cmd_idle_device_exclusive;
dops->put_device = ti_sci_cmd_put_device;
dops->is_valid = ti_sci_cmd_dev_is_valid;
dops->get_context_loss_count = ti_sci_cmd_dev_get_clcnt;
@@ -2642,6 +2911,7 @@
dops->is_transitioning = ti_sci_cmd_dev_is_trans;
dops->set_device_resets = ti_sci_cmd_set_device_resets;
dops->get_device_resets = ti_sci_cmd_get_device_resets;
+ dops->release_exclusive_devices = ti_sci_cmd_release_exclusive_devices;
cops->get_clock = ti_sci_cmd_get_clock;
cops->idle_clock = ti_sci_cmd_idle_clock;
@@ -2672,6 +2942,7 @@
pops->set_proc_boot_ctrl = ti_sci_cmd_set_proc_boot_ctrl;
pops->proc_auth_boot_image = ti_sci_cmd_proc_auth_boot_image;
pops->get_proc_boot_status = ti_sci_cmd_get_proc_boot_status;
+ pops->proc_shutdown_no_wait = ti_sci_cmd_proc_shutdown_no_wait;
rops->config = ti_sci_cmd_ring_config;
rops->get_config = ti_sci_cmd_ring_get_config;
@@ -2835,6 +3106,8 @@
ret = ti_sci_cmd_get_revision(&info->handle);
+ INIT_LIST_HEAD(&info->dev_list);
+
return ret;
}
@@ -2897,6 +3170,7 @@
u32 resource_subtype;
u16 resource_type;
struct ti_sci_resource *res;
+ bool valid_set = false;
int sets, i, ret;
u32 *temp;
@@ -2936,12 +3210,15 @@
&res->desc[i].start,
&res->desc[i].num);
if (ret) {
- dev_err(dev, "type %d subtype %d not allocated for host %d\n",
+ dev_dbg(dev, "type %d subtype %d not allocated for host %d\n",
resource_type, resource_subtype,
handle_to_ti_sci_info(handle)->host_id);
- return ERR_PTR(ret);
+ res->desc[i].start = 0;
+ res->desc[i].num = 0;
+ continue;
}
+ valid_set = true;
dev_dbg(dev, "res type = %d, subtype = %d, start = %d, num = %d\n",
resource_type, resource_subtype, res->desc[i].start,
res->desc[i].num);
@@ -2953,7 +3230,10 @@
return ERR_PTR(-ENOMEM);
}
- return res;
+ if (valid_set)
+ return res;
+
+ return ERR_PTR(-EINVAL);
}
/* Description for K2G */
diff --git a/drivers/firmware/ti_sci.h b/drivers/firmware/ti_sci.h
index a484b1f..69ff74d 100644
--- a/drivers/firmware/ti_sci.h
+++ b/drivers/firmware/ti_sci.h
@@ -50,6 +50,7 @@
#define TISCI_MSG_SET_PROC_BOOT_CTRL 0xc101
#define TISCI_MSG_PROC_AUTH_BOOT_IMIAGE 0xc120
#define TISCI_MSG_GET_PROC_BOOT_STATUS 0xc400
+#define TISCI_MSG_WAIT_PROC_BOOT_STATUS 0xc401
/* Resource Management Requests */
#define TI_SCI_MSG_GET_RESOURCE_RANGE 0x1500
@@ -773,6 +774,55 @@
} __packed;
/**
+ * struct ti_sci_msg_req_wait_proc_boot_status - Wait for a processor
+ * boot status
+ * @hdr: Generic Header
+ * @processor_id: ID of processor
+ * @num_wait_iterations: Total number of iterations we will check before
+ * we will timeout and give up
+ * @num_match_iterations: How many iterations should we have continued
+ * status to account for status bits glitching.
+ * This is to make sure that match occurs for
+ * consecutive checks. This implies that the
+ * worst case should consider that the stable
+ * time should at the worst be num_wait_iterations
+ * num_match_iterations to prevent timeout.
+ * @delay_per_iteration_us: Specifies how long to wait (in micro seconds)
+ * between each status checks. This is the minimum
+ * duration, and overhead of register reads and
+ * checks are on top of this and can vary based on
+ * varied conditions.
+ * @delay_before_iterations_us: Specifies how long to wait (in micro seconds)
+ * before the very first check in the first
+ * iteration of status check loop. This is the
+ * minimum duration, and overhead of register
+ * reads and checks are.
+ * @status_flags_1_set_all_wait:If non-zero, Specifies that all bits of the
+ * status matching this field requested MUST be 1.
+ * @status_flags_1_set_any_wait:If non-zero, Specifies that at least one of the
+ * bits matching this field requested MUST be 1.
+ * @status_flags_1_clr_all_wait:If non-zero, Specifies that all bits of the
+ * status matching this field requested MUST be 0.
+ * @status_flags_1_clr_any_wait:If non-zero, Specifies that at least one of the
+ * bits matching this field requested MUST be 0.
+ *
+ * Request type is TISCI_MSG_WAIT_PROC_BOOT_STATUS, response is appropriate
+ * message, or NACK in case of inability to satisfy request.
+ */
+struct ti_sci_msg_req_wait_proc_boot_status {
+ struct ti_sci_msg_hdr hdr;
+ u8 processor_id;
+ u8 num_wait_iterations;
+ u8 num_match_iterations;
+ u8 delay_per_iteration_us;
+ u8 delay_before_iterations_us;
+ u32 status_flags_1_set_all_wait;
+ u32 status_flags_1_set_any_wait;
+ u32 status_flags_1_clr_all_wait;
+ u32 status_flags_1_clr_any_wait;
+} __packed;
+
+/**
* struct ti_sci_msg_rm_ring_cfg_req - Configure a Navigator Subsystem ring
*
* Configures the non-real-time registers of a Navigator Subsystem ring.
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 8f59193..105a299 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -58,9 +58,17 @@
config FPGA_SPARTAN3
bool "Enable Spartan3 FPGA driver"
+ depends on FPGA_XILINX
help
Enable Spartan3 FPGA driver for loading in BIT format.
+config FPGA_VIRTEX2
+ bool "Enable Xilinx Virtex-II and later FPGA driver"
+ depends on FPGA_XILINX
+ help
+ Enable Virtex-II FPGA driver for loading in BIT format. This driver
+ also supports many newer Xilinx FPGA families.
+
config FPGA_ZYNQPL
bool "Enable Xilinx FPGA for Zynq"
depends on ARCH_ZYNQ
diff --git a/drivers/fpga/cyclon2.c b/drivers/fpga/cyclon2.c
index 6755956..c929cd2 100644
--- a/drivers/fpga/cyclon2.c
+++ b/drivers/fpga/cyclon2.c
@@ -11,9 +11,9 @@
/* Define FPGA_DEBUG to get debug printf's */
#ifdef FPGA_DEBUG
-#define PRINTF(fmt,args...) printf (fmt ,##args)
+#define PRINTF(fmt, args...) printf(fmt, ##args)
#else
-#define PRINTF(fmt,args...)
+#define PRINTF(fmt, args...)
#endif
/* Note: The assumption is that we cannot possibly run fast enough to
@@ -26,7 +26,7 @@
#endif
#ifndef CONFIG_SYS_FPGA_WAIT
-#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10 /* 100 ms */
+#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ / 10 /* 100 ms */
#endif
static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize);
@@ -41,8 +41,8 @@
switch (desc->iface) {
case passive_serial:
- PRINTF ("%s: Launching Passive Serial Loader\n", __FUNCTION__);
- ret_val = CYC2_ps_load (desc, buf, bsize);
+ PRINTF("%s: Launching Passive Serial Loader\n", __func__);
+ ret_val = CYC2_ps_load(desc, buf, bsize);
break;
case fast_passive_parallel:
@@ -50,16 +50,16 @@
* done in the write() callback. Use the existing PS load
* function for FPP, too.
*/
- PRINTF ("%s: Launching Fast Passive Parallel Loader\n",
- __FUNCTION__);
+ PRINTF("%s: Launching Fast Passive Parallel Loader\n",
+ __func__);
ret_val = CYC2_ps_load(desc, buf, bsize);
break;
/* Add new interface types here */
default:
- printf ("%s: Unsupported interface type, %d\n",
- __FUNCTION__, desc->iface);
+ printf("%s: Unsupported interface type, %d\n",
+ __func__, desc->iface);
}
return ret_val;
@@ -71,59 +71,58 @@
switch (desc->iface) {
case passive_serial:
- PRINTF ("%s: Launching Passive Serial Dump\n", __FUNCTION__);
- ret_val = CYC2_ps_dump (desc, buf, bsize);
+ PRINTF("%s: Launching Passive Serial Dump\n", __func__);
+ ret_val = CYC2_ps_dump(desc, buf, bsize);
break;
/* Add new interface types here */
default:
- printf ("%s: Unsupported interface type, %d\n",
- __FUNCTION__, desc->iface);
+ printf("%s: Unsupported interface type, %d\n",
+ __func__, desc->iface);
}
return ret_val;
}
-int CYC2_info( Altera_desc *desc )
+int CYC2_info(Altera_desc *desc)
{
return FPGA_SUCCESS;
}
/* ------------------------------------------------------------------------- */
-/* CYCLON2 Passive Serial Generic Implementation */
+/* CYCLON2 Passive Serial Generic Implementation */
static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume the worst */
Altera_CYC2_Passive_Serial_fns *fn = desc->iface_fns;
int ret = 0;
- PRINTF ("%s: start with interface functions @ 0x%p\n",
- __FUNCTION__, fn);
+ PRINTF("%s: start with interface functions @ 0x%p\n",
+ __func__, fn);
if (fn) {
int cookie = desc->cookie; /* make a local copy */
unsigned long ts; /* timestamp */
- PRINTF ("%s: Function Table:\n"
+ PRINTF("%s: Function Table:\n"
"ptr:\t0x%p\n"
"struct: 0x%p\n"
"config:\t0x%p\n"
"status:\t0x%p\n"
"write:\t0x%p\n"
"done:\t0x%p\n\n",
- __FUNCTION__, &fn, fn, fn->config, fn->status,
+ __func__, &fn, fn, fn->config, fn->status,
fn->write, fn->done);
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
- printf ("Loading FPGA Device %d...", cookie);
+ printf("Loading FPGA Device %d...", cookie);
#endif
/*
* Run the pre configuration function if there is one.
*/
- if (*fn->pre) {
+ if (*fn->pre)
(*fn->pre) (cookie);
- }
/* Establish the initial state */
(*fn->config) (false, true, cookie); /* De-assert nCONFIG */
@@ -133,22 +132,23 @@
udelay(2); /* T_cfg > 2us */
/* Wait for nSTATUS to be asserted */
- ts = get_timer (0); /* get current time */
+ ts = get_timer(0); /* get current time */
do {
- CONFIG_FPGA_DELAY ();
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
- puts ("** Timeout waiting for STATUS to go high.\n");
+ CONFIG_FPGA_DELAY();
+ if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
+ /* check the time */
+ puts("** Timeout waiting for STATUS to go high.\n");
(*fn->abort) (cookie);
return FPGA_FAIL;
}
} while (!(*fn->status) (cookie));
/* Get ready for the burn */
- CONFIG_FPGA_DELAY ();
+ CONFIG_FPGA_DELAY();
ret = (*fn->write) (buf, bsize, true, cookie);
if (ret) {
- puts ("** Write failed.\n");
+ puts("** Write failed.\n");
(*fn->abort) (cookie);
return FPGA_FAIL;
}
@@ -156,39 +156,41 @@
puts(" OK? ...");
#endif
- CONFIG_FPGA_DELAY ();
+ CONFIG_FPGA_DELAY();
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
- putc (' '); /* terminate the dotted line */
+ putc(' '); /* terminate the dotted line */
#endif
- /*
- * Checking FPGA's CONF_DONE signal - correctly booted ?
- */
+ /*
+ * Checking FPGA's CONF_DONE signal - correctly booted ?
+ */
- if ( ! (*fn->done) (cookie) ) {
- puts ("** Booting failed! CONF_DONE is still deasserted.\n");
- (*fn->abort) (cookie);
- return (FPGA_FAIL);
- }
+ if (!(*fn->done) (cookie)) {
+ puts("** Booting failed! CONF_DONE is still deasserted.\n");
+ (*fn->abort) (cookie);
+ return FPGA_FAIL;
+ }
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
- puts(" OK\n");
+ puts(" OK\n");
#endif
- ret_val = FPGA_SUCCESS;
+ ret_val = FPGA_SUCCESS;
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
- if (ret_val == FPGA_SUCCESS) {
- puts ("Done.\n");
- }
- else {
- puts ("Fail.\n");
- }
+ if (ret_val == FPGA_SUCCESS)
+ puts("Done.\n");
+ else
+ puts("Fail.\n");
#endif
- (*fn->post) (cookie);
+ /*
+ * Run the post configuration function if there is one.
+ */
+ if (*fn->post)
+ (*fn->post) (cookie);
} else {
- printf ("%s: NULL Interface function table!\n", __FUNCTION__);
+ printf("%s: NULL Interface function table!\n", __func__);
}
return ret_val;
@@ -198,7 +200,6 @@
{
/* Readback is only available through the Slave Parallel and */
/* boundary-scan interfaces. */
- printf ("%s: Passive Serial Dumping is unavailable\n",
- __FUNCTION__);
+ printf("%s: Passive Serial Dumping is unavailable\n", __func__);
return FPGA_FAIL;
}
diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index 285280e..5fb9d6a 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -936,10 +936,11 @@
fpgamgr_program_write(rbf_data, rbf_size);
status = fpgamgr_program_finish();
- if (status) {
- config_pins(gd->fdt_blob, "fpga");
- puts("FPGA: Enter user mode.\n");
- }
+ if (status)
+ return status;
+
+ config_pins(gd->fdt_blob, "fpga");
+ puts("FPGA: Enter user mode.\n");
return status;
}
diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c
index 02773d6..3957368 100644
--- a/drivers/fpga/virtex2.c
+++ b/drivers/fpga/virtex2.c
@@ -3,6 +3,8 @@
* (C) Copyright 2002
* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
* Keith Outwater, keith_outwater@mvis.com
+ *
+ * Copyright (c) 2019 SED Systems, a division of Calian Ltd.
*/
/*
@@ -19,16 +21,16 @@
#endif
#ifdef FPGA_DEBUG
-#define PRINTF(fmt,args...) printf (fmt ,##args)
+#define PRINTF(fmt, args...) printf(fmt, ##args)
#else
-#define PRINTF(fmt,args...)
+#define PRINTF(fmt, args...)
#endif
/*
* If the SelectMap interface can be overrun by the processor, define
- * CONFIG_SYS_FPGA_CHECK_BUSY and/or CONFIG_FPGA_DELAY in the board configuration
- * file and add board-specific support for checking BUSY status. By default,
- * assume that the SelectMap interface cannot be overrun.
+ * CONFIG_SYS_FPGA_CHECK_BUSY and/or CONFIG_FPGA_DELAY in the board
+ * configuration file and add board-specific support for checking BUSY status.
+ * By default, assume that the SelectMap interface cannot be overrun.
*/
#ifndef CONFIG_SYS_FPGA_CHECK_BUSY
#undef CONFIG_SYS_FPGA_CHECK_BUSY
@@ -65,7 +67,7 @@
* an XC2V1000, if anyone can ever get ahold of one.
*/
#ifndef CONFIG_SYS_FPGA_WAIT_INIT
-#define CONFIG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ/2 /* 500 ms */
+#define CONFIG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ / 2 /* 500 ms */
#endif
/*
@@ -74,14 +76,14 @@
* clock frequencies (i.e. 66 MHz or less), BUSY monitoring is unnecessary.
*/
#ifndef CONFIG_SYS_FPGA_WAIT_BUSY
-#define CONFIG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ/200 /* 5 ms*/
+#define CONFIG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ / 200 /* 5 ms*/
#endif
/* Default timeout for waiting for FPGA to enter operational mode after
* configuration data has been written.
*/
#ifndef CONFIG_SYS_FPGA_WAIT_CONFIG
-#define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ/5 /* 200 ms */
+#define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ / 5 /* 200 ms */
#endif
static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize);
@@ -97,18 +99,18 @@
switch (desc->iface) {
case slave_serial:
- PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
+ PRINTF("%s: Launching Slave Serial Load\n", __func__);
ret_val = virtex2_ss_load(desc, buf, bsize);
break;
case slave_selectmap:
- PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
+ PRINTF("%s: Launching Slave Parallel Load\n", __func__);
ret_val = virtex2_ssm_load(desc, buf, bsize);
break;
default:
- printf ("%s: Unsupported interface type, %d\n",
- __FUNCTION__, desc->iface);
+ printf("%s: Unsupported interface type, %d\n",
+ __func__, desc->iface);
}
return ret_val;
}
@@ -119,18 +121,18 @@
switch (desc->iface) {
case slave_serial:
- PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
+ PRINTF("%s: Launching Slave Serial Dump\n", __func__);
ret_val = virtex2_ss_dump(desc, buf, bsize);
break;
case slave_parallel:
- PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
+ PRINTF("%s: Launching Slave Parallel Dump\n", __func__);
ret_val = virtex2_ssm_dump(desc, buf, bsize);
break;
default:
- printf ("%s: Unsupported interface type, %d\n",
- __FUNCTION__, desc->iface);
+ printf("%s: Unsupported interface type, %d\n",
+ __func__, desc->iface);
}
return ret_val;
}
@@ -141,8 +143,8 @@
}
/*
- * Virtex-II Slave SelectMap configuration loader. Configuration via
- * SelectMap is as follows:
+ * Virtex-II Slave SelectMap or Serial configuration loader. Configuration
+ * is as follows:
* 1. Set the FPGA's PROG_B line low.
* 2. Set the FPGA's PROG_B line high. Wait for INIT_B to go high.
* 3. Write data to the SelectMap port. If INIT_B goes low at any time
@@ -154,200 +156,236 @@
* INIT_B and DONE lines. If both are high, configuration has
* succeeded. Congratulations!
*/
+static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie)
+{
+ unsigned long ts;
+
+ PRINTF("%s:%d: Start with interface functions @ 0x%p\n",
+ __func__, __LINE__, fn);
+
+ if (!fn) {
+ printf("%s:%d: NULL Interface function table!\n",
+ __func__, __LINE__);
+ return FPGA_FAIL;
+ }
+
+ /* Gotta split this one up (so the stack won't blow??) */
+ PRINTF("%s:%d: Function Table:\n"
+ " base 0x%p\n"
+ " struct 0x%p\n"
+ " pre 0x%p\n"
+ " prog 0x%p\n"
+ " init 0x%p\n"
+ " error 0x%p\n",
+ __func__, __LINE__,
+ &fn, fn, fn->pre, fn->pgm, fn->init, fn->err);
+ PRINTF(" clock 0x%p\n"
+ " cs 0x%p\n"
+ " write 0x%p\n"
+ " rdata 0x%p\n"
+ " wdata 0x%p\n"
+ " busy 0x%p\n"
+ " abort 0x%p\n"
+ " post 0x%p\n\n",
+ fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata,
+ fn->busy, fn->abort, fn->post);
+
+#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+ printf("Initializing FPGA Device %d...\n", cookie);
+#endif
+ /*
+ * Run the pre configuration function if there is one.
+ */
+ if (*fn->pre)
+ (*fn->pre)(cookie);
+
+ /*
+ * Assert the program line. The minimum pulse width for
+ * Virtex II devices is 300 nS (Tprogram parameter in datasheet).
+ * There is no maximum value for the pulse width. Check to make
+ * sure that INIT_B goes low after assertion of PROG_B
+ */
+ (*fn->pgm)(true, true, cookie);
+ udelay(10);
+ ts = get_timer(0);
+ do {
+ if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
+ printf("%s:%d: ** Timeout after %d ticks waiting for INIT to assert.\n",
+ __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_INIT);
+ (*fn->abort)(cookie);
+ return FPGA_FAIL;
+ }
+ } while (!(*fn->init)(cookie));
+
+ (*fn->pgm)(false, true, cookie);
+ CONFIG_FPGA_DELAY();
+ if (fn->clk)
+ (*fn->clk)(true, true, cookie);
+
+ /*
+ * Start a timer and wait for INIT_B to go high
+ */
+ ts = get_timer(0);
+ do {
+ CONFIG_FPGA_DELAY();
+ if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
+ printf("%s:%d: ** Timeout after %d ticks waiting for INIT to deassert.\n",
+ __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_INIT);
+ (*fn->abort)(cookie);
+ return FPGA_FAIL;
+ }
+ } while ((*fn->init)(cookie) && (*fn->busy)(cookie));
+
+ if (fn->wr)
+ (*fn->wr)(true, true, cookie);
+ if (fn->cs)
+ (*fn->cs)(true, true, cookie);
+
+ mdelay(10);
+ return FPGA_SUCCESS;
+}
+
+static int virtex2_slave_post(xilinx_virtex2_slave_fns *fn,
+ int cookie)
+{
+ int ret_val = FPGA_SUCCESS;
+ int num_done = 0;
+ unsigned long ts;
+
+ /*
+ * Finished writing the data; deassert FPGA CS_B and WRITE_B signals.
+ */
+ CONFIG_FPGA_DELAY();
+ if (fn->cs)
+ (*fn->cs)(false, true, cookie);
+ if (fn->wr)
+ (*fn->wr)(false, true, cookie);
+
+#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+ putc('\n');
+#endif
+
+ /*
+ * Check for successful configuration. FPGA INIT_B and DONE
+ * should both be high upon successful configuration. Continue pulsing
+ * clock with data set to all ones until DONE is asserted and for 8
+ * clock cycles afterwards.
+ */
+ ts = get_timer(0);
+ while (true) {
+ if ((*fn->done)(cookie) == FPGA_SUCCESS &&
+ !((*fn->init)(cookie))) {
+ if (num_done++ >= 8)
+ break;
+ }
+
+ if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_CONFIG) {
+ printf("%s:%d: ** Timeout after %d ticks waiting for DONE to assert and INIT to deassert\n",
+ __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_CONFIG);
+ (*fn->abort)(cookie);
+ ret_val = FPGA_FAIL;
+ break;
+ }
+ if (fn->wbulkdata) {
+ unsigned char dummy = 0xff;
+ (*fn->wbulkdata)(&dummy, 1, true, cookie);
+ } else {
+ (*fn->wdata)(0xff, true, cookie);
+ CONFIG_FPGA_DELAY();
+ (*fn->clk)(false, true, cookie);
+ CONFIG_FPGA_DELAY();
+ (*fn->clk)(true, true, cookie);
+ }
+ }
+
+ if (ret_val == FPGA_SUCCESS) {
+#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+ printf("Initialization of FPGA device %d complete\n", cookie);
+#endif
+ /*
+ * Run the post configuration function if there is one.
+ */
+ if (*fn->post)
+ (*fn->post)(cookie);
+ } else {
+#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+ printf("** Initialization of FPGA device %d FAILED\n",
+ cookie);
+#endif
+ }
+ return ret_val;
+}
+
static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
- xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns;
+ xilinx_virtex2_slave_fns *fn = desc->iface_fns;
+ size_t bytecount = 0;
+ unsigned char *data = (unsigned char *)buf;
+ int cookie = desc->cookie;
- PRINTF ("%s:%d: Start with interface functions @ 0x%p\n",
- __FUNCTION__, __LINE__, fn);
+ ret_val = virtex2_slave_pre(fn, cookie);
+ if (ret_val != FPGA_SUCCESS)
+ return ret_val;
- if (fn) {
- size_t bytecount = 0;
- unsigned char *data = (unsigned char *) buf;
- int cookie = desc->cookie;
- unsigned long ts;
-
- /* Gotta split this one up (so the stack won't blow??) */
- PRINTF ("%s:%d: Function Table:\n"
- " base 0x%p\n"
- " struct 0x%p\n"
- " pre 0x%p\n"
- " prog 0x%p\n"
- " init 0x%p\n"
- " error 0x%p\n",
- __FUNCTION__, __LINE__,
- &fn, fn, fn->pre, fn->pgm, fn->init, fn->err);
- PRINTF (" clock 0x%p\n"
- " cs 0x%p\n"
- " write 0x%p\n"
- " rdata 0x%p\n"
- " wdata 0x%p\n"
- " busy 0x%p\n"
- " abort 0x%p\n"
- " post 0x%p\n\n",
- fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata,
- fn->busy, fn->abort, fn->post);
-
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
- printf ("Initializing FPGA Device %d...\n", cookie);
-#endif
- /*
- * Run the pre configuration function if there is one.
- */
- if (*fn->pre) {
- (*fn->pre) (cookie);
- }
-
- /*
- * Assert the program line. The minimum pulse width for
- * Virtex II devices is 300 nS (Tprogram parameter in datasheet).
- * There is no maximum value for the pulse width. Check to make
- * sure that INIT_B goes low after assertion of PROG_B
- */
- (*fn->pgm) (true, true, cookie);
- udelay (10);
- ts = get_timer (0);
- do {
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
- printf ("%s:%d: ** Timeout after %d ticks waiting for INIT"
- " to assert.\n", __FUNCTION__, __LINE__,
- CONFIG_SYS_FPGA_WAIT_INIT);
- (*fn->abort) (cookie);
- return FPGA_FAIL;
- }
- } while (!(*fn->init) (cookie));
-
- (*fn->pgm) (false, true, cookie);
- CONFIG_FPGA_DELAY ();
- (*fn->clk) (true, true, cookie);
-
- /*
- * Start a timer and wait for INIT_B to go high
- */
- ts = get_timer (0);
- do {
- CONFIG_FPGA_DELAY ();
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
- printf ("%s:%d: ** Timeout after %d ticks waiting for INIT"
- " to deassert.\n", __FUNCTION__, __LINE__,
- CONFIG_SYS_FPGA_WAIT_INIT);
- (*fn->abort) (cookie);
- return FPGA_FAIL;
- }
- } while ((*fn->init) (cookie) && (*fn->busy) (cookie));
-
- (*fn->wr) (true, true, cookie);
- (*fn->cs) (true, true, cookie);
-
- udelay (10000);
-
- /*
- * Load the data byte by byte
- */
- while (bytecount < bsize) {
+ /*
+ * Load the data byte by byte
+ */
+ while (bytecount < bsize) {
#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
- if (ctrlc ()) {
- (*fn->abort) (cookie);
- return FPGA_FAIL;
- }
+ if (ctrlc()) {
+ (*fn->abort)(cookie);
+ return FPGA_FAIL;
+ }
#endif
- if ((*fn->done) (cookie) == FPGA_SUCCESS) {
- PRINTF ("%s:%d:done went active early, bytecount = %d\n",
- __FUNCTION__, __LINE__, bytecount);
- break;
- }
+ if ((*fn->done)(cookie) == FPGA_SUCCESS) {
+ PRINTF("%s:%d:done went active early, bytecount = %d\n",
+ __func__, __LINE__, bytecount);
+ break;
+ }
#ifdef CONFIG_SYS_FPGA_CHECK_ERROR
- if ((*fn->init) (cookie)) {
- printf ("\n%s:%d: ** Error: INIT asserted during"
- " configuration\n", __FUNCTION__, __LINE__);
- printf ("%d = buffer offset, %d = buffer size\n",
- bytecount, bsize);
- (*fn->abort) (cookie);
- return FPGA_FAIL;
- }
+ if ((*fn->init)(cookie)) {
+ printf("\n%s:%d: ** Error: INIT asserted during configuration\n",
+ __func__, __LINE__);
+ printf("%zu = buffer offset, %zu = buffer size\n",
+ bytecount, bsize);
+ (*fn->abort)(cookie);
+ return FPGA_FAIL;
+ }
#endif
- (*fn->wdata) (data[bytecount++], true, cookie);
- CONFIG_FPGA_DELAY ();
+ (*fn->wdata)(data[bytecount++], true, cookie);
+ CONFIG_FPGA_DELAY();
- /*
- * Cycle the clock pin
- */
- (*fn->clk) (false, true, cookie);
- CONFIG_FPGA_DELAY ();
- (*fn->clk) (true, true, cookie);
+ /*
+ * Cycle the clock pin
+ */
+ (*fn->clk)(false, true, cookie);
+ CONFIG_FPGA_DELAY();
+ (*fn->clk)(true, true, cookie);
#ifdef CONFIG_SYS_FPGA_CHECK_BUSY
- ts = get_timer (0);
- while ((*fn->busy) (cookie)) {
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_BUSY) {
- printf ("%s:%d: ** Timeout after %d ticks waiting for"
- " BUSY to deassert\n",
- __FUNCTION__, __LINE__, CONFIG_SYS_FPGA_WAIT_BUSY);
- (*fn->abort) (cookie);
- return FPGA_FAIL;
- }
- }
-#endif
-
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
- if (bytecount % (bsize / 40) == 0)
- putc ('.');
-#endif
- }
-
- /*
- * Finished writing the data; deassert FPGA CS_B and WRITE_B signals.
- */
- CONFIG_FPGA_DELAY ();
- (*fn->cs) (false, true, cookie);
- (*fn->wr) (false, true, cookie);
-
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
- putc ('\n');
-#endif
-
- /*
- * Check for successful configuration. FPGA INIT_B and DONE should
- * both be high upon successful configuration.
- */
- ts = get_timer (0);
- ret_val = FPGA_SUCCESS;
- while (((*fn->done) (cookie) == FPGA_FAIL) || (*fn->init) (cookie)) {
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_CONFIG) {
- printf ("%s:%d: ** Timeout after %d ticks waiting for DONE to"
- "assert and INIT to deassert\n",
- __FUNCTION__, __LINE__, CONFIG_SYS_FPGA_WAIT_CONFIG);
- (*fn->abort) (cookie);
- ret_val = FPGA_FAIL;
- break;
+ ts = get_timer(0);
+ while ((*fn->busy)(cookie)) {
+ if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_BUSY) {
+ printf("%s:%d: ** Timeout after %d ticks waiting for BUSY to deassert\n",
+ __func__, __LINE__,
+ CONFIG_SYS_FPGA_WAIT_BUSY);
+ (*fn->abort)(cookie);
+ return FPGA_FAIL;
}
}
+#endif
- if (ret_val == FPGA_SUCCESS) {
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
- printf ("Initialization of FPGA device %d complete\n", cookie);
+ if (bytecount % (bsize / 40) == 0)
+ putc('.');
#endif
- /*
- * Run the post configuration function if there is one.
- */
- if (*fn->post) {
- (*fn->post) (cookie);
- }
- } else {
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
- printf ("** Initialization of FPGA device %d FAILED\n",
- cookie);
-#endif
- }
- } else {
- printf ("%s:%d: NULL Interface function table!\n",
- __FUNCTION__, __LINE__);
}
- return ret_val;
+
+ return virtex2_slave_post(fn, cookie);
}
/*
@@ -356,64 +394,127 @@
static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
- xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns;
+ xilinx_virtex2_slave_fns *fn = desc->iface_fns;
if (fn) {
- unsigned char *data = (unsigned char *) buf;
+ unsigned char *data = (unsigned char *)buf;
size_t bytecount = 0;
int cookie = desc->cookie;
- printf ("Starting Dump of FPGA Device %d...\n", cookie);
+ printf("Starting Dump of FPGA Device %d...\n", cookie);
- (*fn->cs) (true, true, cookie);
- (*fn->clk) (true, true, cookie);
+ (*fn->cs)(true, true, cookie);
+ (*fn->clk)(true, true, cookie);
while (bytecount < bsize) {
#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
- if (ctrlc ()) {
- (*fn->abort) (cookie);
+ if (ctrlc()) {
+ (*fn->abort)(cookie);
return FPGA_FAIL;
}
#endif
/*
* Cycle the clock and read the data
*/
- (*fn->clk) (false, true, cookie);
- (*fn->clk) (true, true, cookie);
- (*fn->rdata) (&(data[bytecount++]), cookie);
+ (*fn->clk)(false, true, cookie);
+ (*fn->clk)(true, true, cookie);
+ (*fn->rdata)(&data[bytecount++], cookie);
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
if (bytecount % (bsize / 40) == 0)
- putc ('.');
+ putc('.');
#endif
}
/*
* Deassert CS_B and cycle the clock to deselect the device.
*/
- (*fn->cs) (false, false, cookie);
- (*fn->clk) (false, true, cookie);
- (*fn->clk) (true, true, cookie);
+ (*fn->cs)(false, false, cookie);
+ (*fn->clk)(false, true, cookie);
+ (*fn->clk)(true, true, cookie);
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
- putc ('\n');
+ putc('\n');
#endif
- puts ("Done.\n");
+ puts("Done.\n");
} else {
- printf ("%s:%d: NULL Interface function table!\n",
- __FUNCTION__, __LINE__);
+ printf("%s:%d: NULL Interface function table!\n",
+ __func__, __LINE__);
}
return ret_val;
}
static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
{
- printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__);
- return FPGA_FAIL;
+ int ret_val = FPGA_FAIL;
+ xilinx_virtex2_slave_fns *fn = desc->iface_fns;
+ unsigned char *data = (unsigned char *)buf;
+ int cookie = desc->cookie;
+
+ ret_val = virtex2_slave_pre(fn, cookie);
+ if (ret_val != FPGA_SUCCESS)
+ return ret_val;
+
+ if (fn->wbulkdata) {
+ /* Load the data in a single chunk */
+ (*fn->wbulkdata)(data, bsize, true, cookie);
+ } else {
+ size_t bytecount = 0;
+
+ /*
+ * Load the data bit by bit
+ */
+ while (bytecount < bsize) {
+ unsigned char curr_data = data[bytecount++];
+ int bit;
+
+#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
+ if (ctrlc()) {
+ (*fn->abort) (cookie);
+ return FPGA_FAIL;
+ }
+#endif
+
+ if ((*fn->done)(cookie) == FPGA_SUCCESS) {
+ PRINTF("%s:%d:done went active early, bytecount = %d\n",
+ __func__, __LINE__, bytecount);
+ break;
+ }
+
+#ifdef CONFIG_SYS_FPGA_CHECK_ERROR
+ if ((*fn->init)(cookie)) {
+ printf("\n%s:%d: ** Error: INIT asserted during configuration\n",
+ __func__, __LINE__);
+ printf("%zu = buffer offset, %zu = buffer size\n",
+ bytecount, bsize);
+ (*fn->abort)(cookie);
+ return FPGA_FAIL;
+ }
+#endif
+
+ for (bit = 7; bit >= 0; --bit) {
+ unsigned char curr_bit = (curr_data >> bit) & 1;
+ (*fn->wdata)(curr_bit, true, cookie);
+ CONFIG_FPGA_DELAY();
+ (*fn->clk)(false, true, cookie);
+ CONFIG_FPGA_DELAY();
+ (*fn->clk)(true, true, cookie);
+ }
+
+ /* Slave serial never uses a busy pin */
+
+#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+ if (bytecount % (bsize / 40) == 0)
+ putc('.');
+#endif
+ }
+ }
+
+ return virtex2_slave_post(fn, cookie);
}
static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
- printf ("%s: Slave Serial Dumping is unsupported\n", __FUNCTION__);
+ printf("%s: Slave Serial Dumping is unsupported\n", __func__);
return FPGA_FAIL;
}
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index e36a8ab..f2dabb5 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -14,6 +14,16 @@
particular GPIOs that they provide. The uclass interface
is defined in include/asm-generic/gpio.h.
+config GPIO_HOG
+ bool "Enable GPIO hog support"
+ depends on DM_GPIO
+ default n
+ help
+ Enable gpio hog support
+ The GPIO chip may contain GPIO hog definitions. GPIO hogging
+ is a mechanism providing automatic GPIO request and config-
+ uration as part of the gpio-controller's driver probe function.
+
config ALTERA_PIO
bool "Altera PIO driver"
depends on DM_GPIO
@@ -129,6 +139,11 @@
help
Support GPIO controllers on various i.MX platforms
+config MXS_GPIO
+ bool "Freescale/NXP MXS GPIO driver"
+ help
+ Support GPIO controllers on i.MX23 and i.MX28 platforms
+
config OMAP_GPIO
bool "TI OMAP GPIO driver"
depends on ARCH_OMAP2PLUS
@@ -205,6 +220,12 @@
of 'anonymous' GPIOs that do not belong to any device or bank.
Select a suitable value depending on your needs.
+config SUNXI_GPIO
+ bool "Allwinner GPIO driver"
+ depends on ARCH_SUNXI
+ help
+ Support the GPIO device in Allwinner SoCs.
+
config XILINX_GPIO
bool "Xilinx GPIO driver"
depends on DM_GPIO
@@ -255,13 +276,13 @@
help
Say yes here to support Microchip PIC32 GPIOs.
-config STM32F7_GPIO
+config STM32_GPIO
bool "ST STM32 GPIO driver"
depends on DM_GPIO && (STM32 || ARCH_STM32MP)
default y
help
Device model driver support for STM32 GPIO controller. It should be
- usable on many stm32 families like stm32f4 & stm32H7.
+ usable on many stm32 families like stm32f4/f7/h7 and stm32mp1.
Tested on STM32F7.
config MVEBU_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 7337153..4a8aa0f 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -47,7 +47,7 @@
obj-$(CONFIG_TCA642X) += tca642x.o
obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o
obj-$(CONFIG_LPC32XX_GPIO) += lpc32xx_gpio.o
-obj-$(CONFIG_STM32F7_GPIO) += stm32f7_gpio.o
+obj-$(CONFIG_STM32_GPIO) += stm32_gpio.o
obj-$(CONFIG_GPIO_UNIPHIER) += gpio-uniphier.o
obj-$(CONFIG_ZYNQ_GPIO) += zynq_gpio.o
obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o
diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c
index da5e9ba..01cfa2f 100644
--- a/drivers/gpio/gpio-uclass.c
+++ b/drivers/gpio/gpio-uclass.c
@@ -5,6 +5,9 @@
#include <common.h>
#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/uclass-internal.h>
#include <dt-bindings/gpio/gpio.h>
#include <errno.h>
#include <fdtdec.h>
@@ -141,6 +144,129 @@
return gpio_xlate_offs_flags(desc->dev, desc, args);
}
+#if defined(CONFIG_GPIO_HOG)
+
+struct gpio_hog_priv {
+ struct gpio_desc gpiod;
+};
+
+struct gpio_hog_data {
+ int gpiod_flags;
+ int value;
+ u32 val[2];
+};
+
+static int gpio_hog_ofdata_to_platdata(struct udevice *dev)
+{
+ struct gpio_hog_data *plat = dev_get_platdata(dev);
+ const char *nodename;
+ int ret;
+
+ plat->value = 0;
+ if (dev_read_bool(dev, "input")) {
+ plat->gpiod_flags = GPIOD_IS_IN;
+ } else if (dev_read_bool(dev, "output-high")) {
+ plat->value = 1;
+ plat->gpiod_flags = GPIOD_IS_OUT;
+ } else if (dev_read_bool(dev, "output-low")) {
+ plat->gpiod_flags = GPIOD_IS_OUT;
+ } else {
+ printf("%s: missing gpio-hog state.\n", __func__);
+ return -EINVAL;
+ }
+ ret = dev_read_u32_array(dev, "gpios", plat->val, 2);
+ if (ret) {
+ printf("%s: wrong gpios property, 2 values needed %d\n",
+ __func__, ret);
+ return ret;
+ }
+ nodename = dev_read_string(dev, "line-name");
+ if (nodename)
+ device_set_name(dev, nodename);
+
+ return 0;
+}
+
+static int gpio_hog_probe(struct udevice *dev)
+{
+ struct gpio_hog_data *plat = dev_get_platdata(dev);
+ struct gpio_hog_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = gpio_dev_request_index(dev->parent, dev->name, "gpio-hog",
+ plat->val[0], plat->gpiod_flags,
+ plat->val[1], &priv->gpiod);
+ if (ret < 0) {
+ debug("%s: node %s could not get gpio.\n", __func__,
+ dev->name);
+ return ret;
+ }
+
+ if (plat->gpiod_flags == GPIOD_IS_OUT) {
+ ret = dm_gpio_set_value(&priv->gpiod, plat->value);
+ if (ret < 0) {
+ debug("%s: node %s could not set gpio.\n", __func__,
+ dev->name);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+int gpio_hog_probe_all(void)
+{
+ struct udevice *dev;
+ int ret;
+ int retval = 0;
+
+ for (uclass_first_device(UCLASS_NOP, &dev);
+ dev;
+ uclass_find_next_device(&dev)) {
+ if (dev->driver == DM_GET_DRIVER(gpio_hog)) {
+ ret = device_probe(dev);
+ if (ret) {
+ printf("Failed to probe device %s err: %d\n",
+ dev->name, ret);
+ retval = ret;
+ }
+ }
+ }
+
+ return retval;
+}
+
+int gpio_hog_lookup_name(const char *name, struct gpio_desc **desc)
+{
+ struct udevice *dev;
+
+ *desc = NULL;
+ gpio_hog_probe_all();
+ if (!uclass_get_device_by_name(UCLASS_NOP, name, &dev)) {
+ struct gpio_hog_priv *priv = dev_get_priv(dev);
+
+ *desc = &priv->gpiod;
+ return 0;
+ }
+
+ return -ENODEV;
+}
+
+U_BOOT_DRIVER(gpio_hog) = {
+ .name = "gpio_hog",
+ .id = UCLASS_NOP,
+ .ofdata_to_platdata = gpio_hog_ofdata_to_platdata,
+ .probe = gpio_hog_probe,
+ .priv_auto_alloc_size = sizeof(struct gpio_hog_priv),
+ .platdata_auto_alloc_size = sizeof(struct gpio_hog_data),
+};
+#else
+int gpio_hog_lookup_name(const char *name, struct gpio_desc **desc)
+{
+ return 0;
+}
+#endif
+
int dm_gpio_request(struct gpio_desc *desc, const char *label)
{
struct udevice *dev = desc->dev;
@@ -640,22 +766,58 @@
return vector;
}
-static int gpio_request_tail(int ret, ofnode node,
+/**
+ * gpio_request_tail: common work for requesting a gpio.
+ *
+ * ret: return value from previous work in function which calls
+ * this function.
+ * This seems bogus (why calling this function instead not
+ * calling it and end caller function instead?).
+ * Because on error in caller function we want to set some
+ * default values in gpio desc and have a common error
+ * debug message, which provides this function.
+ * nodename: Name of node for which gpio gets requested
+ * used for gpio label name.
+ * args: pointer to output arguments structure
+ * list_name: Name of GPIO list
+ * used for gpio label name.
+ * index: gpio index in gpio list
+ * used for gpio label name.
+ * desc: pointer to gpio descriptor, filled from this
+ * function.
+ * flags: gpio flags to use.
+ * add_index: should index added to gpio label name
+ * gpio_dev: pointer to gpio device from which the gpio
+ * will be requested. If NULL try to get the
+ * gpio device with uclass_get_device_by_ofnode()
+ *
+ * return: In error case this function sets default values in
+ * gpio descriptor, also emmits a debug message.
+ * On success it returns 0 else the error code from
+ * function calls, or the error code passed through
+ * ret to this function.
+ *
+ */
+static int gpio_request_tail(int ret, const char *nodename,
struct ofnode_phandle_args *args,
const char *list_name, int index,
- struct gpio_desc *desc, int flags, bool add_index)
+ struct gpio_desc *desc, int flags,
+ bool add_index, struct udevice *gpio_dev)
{
- desc->dev = NULL;
+ desc->dev = gpio_dev;
desc->offset = 0;
desc->flags = 0;
if (ret)
goto err;
- ret = uclass_get_device_by_ofnode(UCLASS_GPIO, args->node,
- &desc->dev);
- if (ret) {
- debug("%s: uclass_get_device_by_ofnode failed\n", __func__);
- goto err;
+ if (!desc->dev) {
+ ret = uclass_get_device_by_ofnode(UCLASS_GPIO, args->node,
+ &desc->dev);
+ if (ret) {
+ debug("%s: uclass_get_device_by_ofnode failed\n",
+ __func__);
+ goto err;
+ }
}
ret = gpio_find_and_xlate(desc, args);
if (ret) {
@@ -663,8 +825,7 @@
goto err;
}
ret = dm_gpio_requestf(desc, add_index ? "%s.%s%d" : "%s.%s",
- ofnode_get_name(node),
- list_name, index);
+ nodename, list_name, index);
if (ret) {
debug("%s: dm_gpio_requestf failed\n", __func__);
goto err;
@@ -678,7 +839,7 @@
return 0;
err:
debug("%s: Node '%s', property '%s', failed to request GPIO index %d: %d\n",
- __func__, ofnode_get_name(node), list_name, index, ret);
+ __func__, nodename, list_name, index, ret);
return ret;
}
@@ -692,8 +853,8 @@
ret = ofnode_parse_phandle_with_args(node, list_name, "#gpio-cells", 0,
index, &args);
- return gpio_request_tail(ret, node, &args, list_name, index, desc,
- flags, add_index);
+ return gpio_request_tail(ret, ofnode_get_name(node), &args, list_name,
+ index, desc, flags, add_index, NULL);
}
int gpio_request_by_name_nodev(ofnode node, const char *list_name, int index,
@@ -707,13 +868,14 @@
struct gpio_desc *desc, int flags)
{
struct ofnode_phandle_args args;
+ ofnode node;
int ret;
ret = dev_read_phandle_with_args(dev, list_name, "#gpio-cells", 0,
index, &args);
-
- return gpio_request_tail(ret, dev_ofnode(dev), &args, list_name,
- index, desc, flags, index > 0);
+ node = dev_ofnode(dev);
+ return gpio_request_tail(ret, ofnode_get_name(node), &args, list_name,
+ index, desc, flags, index > 0, NULL);
}
int gpio_request_list_by_name_nodev(ofnode node, const char *list_name,
@@ -854,8 +1016,26 @@
return gpio_renumber(dev);
}
+int gpio_dev_request_index(struct udevice *dev, const char *nodename,
+ char *list_name, int index, int flags,
+ int dtflags, struct gpio_desc *desc)
+{
+ struct ofnode_phandle_args args;
+
+ args.node = ofnode_null();
+ args.args_count = 2;
+ args.args[0] = index;
+ args.args[1] = dtflags;
+
+ return gpio_request_tail(0, nodename, &args, list_name, index, desc,
+ flags, 0, dev);
+}
+
static int gpio_post_bind(struct udevice *dev)
{
+ struct udevice *child;
+ ofnode node;
+
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
struct dm_gpio_ops *ops = (struct dm_gpio_ops *)device_get_ops(dev);
static int reloc_done;
@@ -885,6 +1065,22 @@
reloc_done++;
}
#endif
+
+ if (IS_ENABLED(CONFIG_GPIO_HOG)) {
+ dev_for_each_subnode(node, dev) {
+ if (ofnode_read_bool(node, "gpio-hog")) {
+ const char *name = ofnode_get_name(node);
+ int ret;
+
+ ret = device_bind_driver_to_node(dev,
+ "gpio_hog",
+ name, node,
+ &child);
+ if (ret)
+ return ret;
+ }
+ }
+ }
return 0;
}
diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
index 8bd30c7..64ab7a3 100644
--- a/drivers/gpio/mxc_gpio.c
+++ b/drivers/gpio/mxc_gpio.c
@@ -31,7 +31,7 @@
};
#ifndef CONFIG_DM_GPIO
-#define GPIO_TO_PORT(n) (n / 32)
+#define GPIO_TO_PORT(n) ((n) / 32)
/* GPIO port description */
static unsigned long gpio_ports[] = {
diff --git a/drivers/gpio/mxs_gpio.c b/drivers/gpio/mxs_gpio.c
index c2c8a25..b2451fd 100644
--- a/drivers/gpio/mxs_gpio.c
+++ b/drivers/gpio/mxs_gpio.c
@@ -51,6 +51,7 @@
}
}
+#if !CONFIG_IS_ENABLED(DM_GPIO)
int gpio_get_value(unsigned gpio)
{
uint32_t bank = PAD_BANK(gpio);
@@ -127,3 +128,150 @@
return (bank << MXS_PAD_BANK_SHIFT) | (pin << MXS_PAD_PIN_SHIFT);
}
+#else /* CONFIG_DM_GPIO */
+#include <dm.h>
+#include <asm/gpio.h>
+#include <asm/arch/gpio.h>
+#define MXS_MAX_GPIO_PER_BANK 32
+
+DECLARE_GLOBAL_DATA_PTR;
+/*
+ * According to i.MX28 Reference Manual:
+ * 'i.MX28 Applications Processor Reference Manual, Rev. 1, 2010'
+ * The i.MX28 has following number of GPIOs available:
+ * Bank 0: 0-28 -> 29 PINS
+ * Bank 1: 0-31 -> 32 PINS
+ * Bank 2: 0-27 -> 28 PINS
+ * Bank 3: 0-30 -> 31 PINS
+ * Bank 4: 0-20 -> 21 PINS
+ */
+
+struct mxs_gpio_priv {
+ unsigned int bank;
+};
+
+static int mxs_gpio_get_value(struct udevice *dev, unsigned offset)
+{
+ struct mxs_gpio_priv *priv = dev_get_priv(dev);
+ struct mxs_register_32 *reg =
+ (struct mxs_register_32 *)(MXS_PINCTRL_BASE +
+ PINCTRL_DIN(priv->bank));
+
+ return (readl(®->reg) >> offset) & 1;
+}
+
+static int mxs_gpio_set_value(struct udevice *dev, unsigned offset,
+ int value)
+{
+ struct mxs_gpio_priv *priv = dev_get_priv(dev);
+ struct mxs_register_32 *reg =
+ (struct mxs_register_32 *)(MXS_PINCTRL_BASE +
+ PINCTRL_DOUT(priv->bank));
+ if (value)
+ writel(BIT(offset), ®->reg_set);
+ else
+ writel(BIT(offset), ®->reg_clr);
+
+ return 0;
+}
+
+static int mxs_gpio_direction_input(struct udevice *dev, unsigned offset)
+{
+ struct mxs_gpio_priv *priv = dev_get_priv(dev);
+ struct mxs_register_32 *reg =
+ (struct mxs_register_32 *)(MXS_PINCTRL_BASE +
+ PINCTRL_DOE(priv->bank));
+
+ writel(BIT(offset), ®->reg_clr);
+
+ return 0;
+}
+
+static int mxs_gpio_direction_output(struct udevice *dev, unsigned offset,
+ int value)
+{
+ struct mxs_gpio_priv *priv = dev_get_priv(dev);
+ struct mxs_register_32 *reg =
+ (struct mxs_register_32 *)(MXS_PINCTRL_BASE +
+ PINCTRL_DOE(priv->bank));
+
+ mxs_gpio_set_value(dev, offset, value);
+
+ writel(BIT(offset), ®->reg_set);
+
+ return 0;
+}
+
+static int mxs_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+ struct mxs_gpio_priv *priv = dev_get_priv(dev);
+ struct mxs_register_32 *reg =
+ (struct mxs_register_32 *)(MXS_PINCTRL_BASE +
+ PINCTRL_DOE(priv->bank));
+ bool is_output = !!(readl(®->reg) >> offset);
+
+ return is_output ? GPIOF_OUTPUT : GPIOF_INPUT;
+}
+
+static const struct dm_gpio_ops gpio_mxs_ops = {
+ .direction_input = mxs_gpio_direction_input,
+ .direction_output = mxs_gpio_direction_output,
+ .get_value = mxs_gpio_get_value,
+ .set_value = mxs_gpio_set_value,
+ .get_function = mxs_gpio_get_function,
+};
+
+static int mxs_gpio_probe(struct udevice *dev)
+{
+ struct mxs_gpio_priv *priv = dev_get_priv(dev);
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct fdtdec_phandle_args args;
+ int node = dev_of_offset(dev);
+ char name[16], *str;
+ fdt_addr_t addr;
+ int ret;
+
+ addr = devfdt_get_addr(dev);
+ if (addr == FDT_ADDR_T_NONE) {
+ printf("%s: No 'reg' property defined!\n", __func__);
+ return -EINVAL;
+ }
+
+ priv->bank = (unsigned int)addr;
+
+ snprintf(name, sizeof(name), "GPIO%d_", priv->bank);
+ str = strdup(name);
+ if (!str)
+ return -ENOMEM;
+
+ uc_priv->bank_name = str;
+
+ ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, "gpio-ranges",
+ NULL, 3, 0, &args);
+ if (ret)
+ printf("%s: 'gpio-ranges' not defined - using default!\n",
+ __func__);
+
+ uc_priv->gpio_count = ret == 0 ? args.args[2] : MXS_MAX_GPIO_PER_BANK;
+
+ debug("%s: %s: %d pins\n", __func__, uc_priv->bank_name,
+ uc_priv->gpio_count);
+
+ return 0;
+}
+
+static const struct udevice_id mxs_gpio_ids[] = {
+ { .compatible = "fsl,imx23-gpio" },
+ { .compatible = "fsl,imx28-gpio" },
+ { }
+};
+
+U_BOOT_DRIVER(gpio_mxs) = {
+ .name = "gpio_mxs",
+ .id = UCLASS_GPIO,
+ .ops = &gpio_mxs_ops,
+ .probe = mxs_gpio_probe,
+ .priv_auto_alloc_size = sizeof(struct mxs_gpio_priv),
+ .of_match = mxs_gpio_ids,
+};
+#endif /* CONFIG_DM_GPIO */
diff --git a/drivers/gpio/pca953x_gpio.c b/drivers/gpio/pca953x_gpio.c
index 341527a..07a3356 100644
--- a/drivers/gpio/pca953x_gpio.c
+++ b/drivers/gpio/pca953x_gpio.c
@@ -363,6 +363,7 @@
{ .compatible = "ti,tca6408", .data = OF_953X(8, PCA_INT), },
{ .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
{ .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
+ { .compatible = "ti,tca9539", .data = OF_953X(16, PCA_INT), },
{ .compatible = "onsemi,pca9654", .data = OF_953X(8, PCA_INT), },
diff --git a/drivers/gpio/stm32_gpio.c b/drivers/gpio/stm32_gpio.c
new file mode 100644
index 0000000..302a434
--- /dev/null
+++ b/drivers/gpio/stm32_gpio.c
@@ -0,0 +1,222 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/stm32.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+
+#define MODE_BITS(gpio_pin) (gpio_pin * 2)
+#define MODE_BITS_MASK 3
+#define BSRR_BIT(gpio_pin, value) BIT(gpio_pin + (value ? 0 : 16))
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ * convert gpio offset to gpio index taking into account gpio holes
+ * into gpio bank
+ */
+int stm32_offset_to_index(struct udevice *dev, unsigned int offset)
+{
+ struct stm32_gpio_priv *priv = dev_get_priv(dev);
+ unsigned int idx = 0;
+ int i;
+
+ for (i = 0; i < STM32_GPIOS_PER_BANK; i++) {
+ if (priv->gpio_range & BIT(i)) {
+ if (idx == offset)
+ return idx;
+ idx++;
+ }
+ }
+ /* shouldn't happen */
+ return -EINVAL;
+}
+
+static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset)
+{
+ struct stm32_gpio_priv *priv = dev_get_priv(dev);
+ struct stm32_gpio_regs *regs = priv->regs;
+ int bits_index;
+ int mask;
+ int idx;
+
+ idx = stm32_offset_to_index(dev, offset);
+ if (idx < 0)
+ return idx;
+
+ bits_index = MODE_BITS(idx);
+ mask = MODE_BITS_MASK << bits_index;
+
+ clrsetbits_le32(®s->moder, mask, STM32_GPIO_MODE_IN << bits_index);
+
+ return 0;
+}
+
+static int stm32_gpio_direction_output(struct udevice *dev, unsigned offset,
+ int value)
+{
+ struct stm32_gpio_priv *priv = dev_get_priv(dev);
+ struct stm32_gpio_regs *regs = priv->regs;
+ int bits_index;
+ int mask;
+ int idx;
+
+ idx = stm32_offset_to_index(dev, offset);
+ if (idx < 0)
+ return idx;
+
+ bits_index = MODE_BITS(idx);
+ mask = MODE_BITS_MASK << bits_index;
+
+ clrsetbits_le32(®s->moder, mask, STM32_GPIO_MODE_OUT << bits_index);
+
+ writel(BSRR_BIT(idx, value), ®s->bsrr);
+
+ return 0;
+}
+
+static int stm32_gpio_get_value(struct udevice *dev, unsigned offset)
+{
+ struct stm32_gpio_priv *priv = dev_get_priv(dev);
+ struct stm32_gpio_regs *regs = priv->regs;
+ int idx;
+
+ idx = stm32_offset_to_index(dev, offset);
+ if (idx < 0)
+ return idx;
+
+ return readl(®s->idr) & BIT(idx) ? 1 : 0;
+}
+
+static int stm32_gpio_set_value(struct udevice *dev, unsigned offset, int value)
+{
+ struct stm32_gpio_priv *priv = dev_get_priv(dev);
+ struct stm32_gpio_regs *regs = priv->regs;
+ int idx;
+
+ idx = stm32_offset_to_index(dev, offset);
+ if (idx < 0)
+ return idx;
+
+ writel(BSRR_BIT(idx, value), ®s->bsrr);
+
+ return 0;
+}
+
+static int stm32_gpio_get_function(struct udevice *dev, unsigned int offset)
+{
+ struct stm32_gpio_priv *priv = dev_get_priv(dev);
+ struct stm32_gpio_regs *regs = priv->regs;
+ int bits_index;
+ int mask;
+ int idx;
+ u32 mode;
+
+ idx = stm32_offset_to_index(dev, offset);
+ if (idx < 0)
+ return idx;
+
+ bits_index = MODE_BITS(idx);
+ mask = MODE_BITS_MASK << bits_index;
+
+ mode = (readl(®s->moder) & mask) >> bits_index;
+ if (mode == STM32_GPIO_MODE_OUT)
+ return GPIOF_OUTPUT;
+ if (mode == STM32_GPIO_MODE_IN)
+ return GPIOF_INPUT;
+ if (mode == STM32_GPIO_MODE_AN)
+ return GPIOF_UNUSED;
+
+ return GPIOF_FUNC;
+}
+
+static const struct dm_gpio_ops gpio_stm32_ops = {
+ .direction_input = stm32_gpio_direction_input,
+ .direction_output = stm32_gpio_direction_output,
+ .get_value = stm32_gpio_get_value,
+ .set_value = stm32_gpio_set_value,
+ .get_function = stm32_gpio_get_function,
+};
+#endif
+
+static int gpio_stm32_probe(struct udevice *dev)
+{
+ struct stm32_gpio_priv *priv = dev_get_priv(dev);
+ struct clk clk;
+ fdt_addr_t addr;
+ int ret;
+
+ addr = dev_read_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->regs = (struct stm32_gpio_regs *)addr;
+
+#ifndef CONFIG_SPL_BUILD
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct ofnode_phandle_args args;
+ const char *name;
+ int i;
+
+ name = dev_read_string(dev, "st,bank-name");
+ if (!name)
+ return -EINVAL;
+ uc_priv->bank_name = name;
+
+ i = 0;
+ ret = dev_read_phandle_with_args(dev, "gpio-ranges",
+ NULL, 3, i, &args);
+
+ if (ret == -ENOENT) {
+ uc_priv->gpio_count = STM32_GPIOS_PER_BANK;
+ priv->gpio_range = GENMASK(STM32_GPIOS_PER_BANK - 1, 0);
+ }
+
+ while (ret != -ENOENT) {
+ priv->gpio_range |= GENMASK(args.args[2] + args.args[0] - 1,
+ args.args[0]);
+
+ uc_priv->gpio_count += args.args[2];
+
+ ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
+ ++i, &args);
+ }
+
+ dev_dbg(dev, "addr = 0x%p bank_name = %s gpio_count = %d gpio_range = 0x%x\n",
+ (u32 *)priv->regs, uc_priv->bank_name, uc_priv->gpio_count,
+ priv->gpio_range);
+#endif
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_enable(&clk);
+
+ if (ret) {
+ dev_err(dev, "failed to enable clock\n");
+ return ret;
+ }
+ debug("clock enabled for device %s\n", dev->name);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(gpio_stm32) = {
+ .name = "gpio_stm32",
+ .id = UCLASS_GPIO,
+ .probe = gpio_stm32_probe,
+#ifndef CONFIG_SPL_BUILD
+ .ops = &gpio_stm32_ops,
+#endif
+ .flags = DM_UC_FLAG_SEQ_ALIAS,
+ .priv_auto_alloc_size = sizeof(struct stm32_gpio_priv),
+};
diff --git a/drivers/gpio/stm32f7_gpio.c b/drivers/gpio/stm32f7_gpio.c
deleted file mode 100644
index 5c9f2fe..0000000
--- a/drivers/gpio/stm32f7_gpio.c
+++ /dev/null
@@ -1,228 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
- * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
- */
-
-#include <common.h>
-#include <clk.h>
-#include <dm.h>
-#include <fdtdec.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/stm32.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <linux/errno.h>
-#include <linux/io.h>
-
-#define MODE_BITS(gpio_pin) (gpio_pin * 2)
-#define MODE_BITS_MASK 3
-#define BSRR_BIT(gpio_pin, value) BIT(gpio_pin + (value ? 0 : 16))
-
-#ifndef CONFIG_SPL_BUILD
-/*
- * convert gpio offset to gpio index taking into account gpio holes
- * into gpio bank
- */
-int stm32_offset_to_index(struct udevice *dev, unsigned int offset)
-{
- struct stm32_gpio_priv *priv = dev_get_priv(dev);
- int idx = 0;
- int i;
-
- for (i = 0; i < STM32_GPIOS_PER_BANK; i++) {
- if (priv->gpio_range & BIT(i)) {
- if (idx == offset)
- return idx;
- idx++;
- }
- }
- /* shouldn't happen */
- return -EINVAL;
-}
-
-static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset)
-{
- struct stm32_gpio_priv *priv = dev_get_priv(dev);
- struct stm32_gpio_regs *regs = priv->regs;
- int bits_index;
- int mask;
- int idx;
-
- idx = stm32_offset_to_index(dev, offset);
- if (idx < 0)
- return idx;
-
- bits_index = MODE_BITS(idx);
- mask = MODE_BITS_MASK << bits_index;
-
- clrsetbits_le32(®s->moder, mask, STM32_GPIO_MODE_IN << bits_index);
-
- return 0;
-}
-
-static int stm32_gpio_direction_output(struct udevice *dev, unsigned offset,
- int value)
-{
- struct stm32_gpio_priv *priv = dev_get_priv(dev);
- struct stm32_gpio_regs *regs = priv->regs;
- int bits_index;
- int mask;
- int idx;
-
- idx = stm32_offset_to_index(dev, offset);
- if (idx < 0)
- return idx;
-
- bits_index = MODE_BITS(idx);
- mask = MODE_BITS_MASK << bits_index;
-
- clrsetbits_le32(®s->moder, mask, STM32_GPIO_MODE_OUT << bits_index);
-
- writel(BSRR_BIT(idx, value), ®s->bsrr);
-
- return 0;
-}
-
-static int stm32_gpio_get_value(struct udevice *dev, unsigned offset)
-{
- struct stm32_gpio_priv *priv = dev_get_priv(dev);
- struct stm32_gpio_regs *regs = priv->regs;
- int idx;
-
- idx = stm32_offset_to_index(dev, offset);
- if (idx < 0)
- return idx;
-
- return readl(®s->idr) & BIT(idx) ? 1 : 0;
-}
-
-static int stm32_gpio_set_value(struct udevice *dev, unsigned offset, int value)
-{
- struct stm32_gpio_priv *priv = dev_get_priv(dev);
- struct stm32_gpio_regs *regs = priv->regs;
- int idx;
-
- idx = stm32_offset_to_index(dev, offset);
- if (idx < 0)
- return idx;
-
- writel(BSRR_BIT(idx, value), ®s->bsrr);
-
- return 0;
-}
-
-static int stm32_gpio_get_function(struct udevice *dev, unsigned int offset)
-{
- struct stm32_gpio_priv *priv = dev_get_priv(dev);
- struct stm32_gpio_regs *regs = priv->regs;
- int bits_index;
- int mask;
- int idx;
- u32 mode;
-
- idx = stm32_offset_to_index(dev, offset);
- if (idx < 0)
- return idx;
-
- bits_index = MODE_BITS(idx);
- mask = MODE_BITS_MASK << bits_index;
-
- mode = (readl(®s->moder) & mask) >> bits_index;
- if (mode == STM32_GPIO_MODE_OUT)
- return GPIOF_OUTPUT;
- if (mode == STM32_GPIO_MODE_IN)
- return GPIOF_INPUT;
- if (mode == STM32_GPIO_MODE_AN)
- return GPIOF_UNUSED;
-
- return GPIOF_FUNC;
-}
-
-static const struct dm_gpio_ops gpio_stm32_ops = {
- .direction_input = stm32_gpio_direction_input,
- .direction_output = stm32_gpio_direction_output,
- .get_value = stm32_gpio_get_value,
- .set_value = stm32_gpio_set_value,
- .get_function = stm32_gpio_get_function,
-};
-#endif
-
-static int gpio_stm32_probe(struct udevice *dev)
-{
- struct stm32_gpio_priv *priv = dev_get_priv(dev);
- struct clk clk;
- fdt_addr_t addr;
- int ret;
-
- addr = dev_read_addr(dev);
- if (addr == FDT_ADDR_T_NONE)
- return -EINVAL;
-
- priv->regs = (struct stm32_gpio_regs *)addr;
-
-#ifndef CONFIG_SPL_BUILD
- struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
- struct ofnode_phandle_args args;
- const char *name;
- int i;
-
- name = dev_read_string(dev, "st,bank-name");
- if (!name)
- return -EINVAL;
- uc_priv->bank_name = name;
-
- i = 0;
- ret = dev_read_phandle_with_args(dev, "gpio-ranges",
- NULL, 3, i, &args);
-
- if (ret == -ENOENT) {
- uc_priv->gpio_count = STM32_GPIOS_PER_BANK;
- priv->gpio_range = GENMASK(STM32_GPIOS_PER_BANK - 1, 0);
- }
-
- while (ret != -ENOENT) {
- priv->gpio_range |= GENMASK(args.args[2] + args.args[0] - 1,
- args.args[0]);
-
- uc_priv->gpio_count += args.args[2];
-
- ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
- ++i, &args);
- }
-
- dev_dbg(dev, "addr = 0x%p bank_name = %s gpio_count = %d gpio_range = 0x%x\n",
- (u32 *)priv->regs, uc_priv->bank_name, uc_priv->gpio_count,
- priv->gpio_range);
-#endif
- ret = clk_get_by_index(dev, 0, &clk);
- if (ret < 0)
- return ret;
-
- ret = clk_enable(&clk);
-
- if (ret) {
- dev_err(dev, "failed to enable clock\n");
- return ret;
- }
- debug("clock enabled for device %s\n", dev->name);
-
- return 0;
-}
-
-static const struct udevice_id stm32_gpio_ids[] = {
- { .compatible = "st,stm32-gpio" },
- { }
-};
-
-U_BOOT_DRIVER(gpio_stm32) = {
- .name = "gpio_stm32",
- .id = UCLASS_GPIO,
- .of_match = stm32_gpio_ids,
- .probe = gpio_stm32_probe,
-#ifndef CONFIG_SPL_BUILD
- .ops = &gpio_stm32_ops,
-#endif
- .flags = DM_UC_FLAG_SEQ_ALIAS,
- .priv_auto_alloc_size = sizeof(struct stm32_gpio_priv),
-};
diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
index cbed8d4..719efc2 100644
--- a/drivers/gpio/sunxi_gpio.c
+++ b/drivers/gpio/sunxi_gpio.c
@@ -354,12 +354,14 @@
ID("allwinner,sun8i-v3s-pinctrl", a_all),
ID("allwinner,sun9i-a80-pinctrl", a_all),
ID("allwinner,sun50i-a64-pinctrl", a_all),
+ ID("allwinner,sun50i-h6-pinctrl", a_all),
ID("allwinner,sun6i-a31-r-pinctrl", l_2),
ID("allwinner,sun8i-a23-r-pinctrl", l_1),
ID("allwinner,sun8i-a83t-r-pinctrl", l_1),
ID("allwinner,sun8i-h3-r-pinctrl", l_1),
ID("allwinner,sun9i-a80-r-pinctrl", l_3),
ID("allwinner,sun50i-a64-r-pinctrl", l_1),
+ ID("allwinner,sun50i-h6-r-pinctrl", l_2),
{ }
};
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 095a9bc..03d2fed 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -12,18 +12,7 @@
write and speed, is implemented with the bus drivers operations,
which provide methods for bus setting and data transfer. Each chip
device (bus child) info is kept as parent platdata. The interface
- is defined in include/i2c.h. When i2c bus driver supports the i2c
- uclass, but the device drivers not, then DM_I2C_COMPAT config can
- be used as compatibility layer.
-
-config DM_I2C_COMPAT
- bool "Enable I2C compatibility layer"
- depends on DM
- help
- Enable old-style I2C functions for compatibility with existing code.
- This option can be enabled as a temporary measure to avoid needing
- to convert all code for a board in a single commit. It should not
- be enabled for any board in an official release.
+ is defined in include/i2c.h.
config I2C_CROS_EC_TUNNEL
tristate "Chrome OS EC tunnel I2C bus"
@@ -330,7 +319,7 @@
config SYS_I2C_OMAP24XX
bool "TI OMAP2+ I2C driver"
- depends on ARCH_OMAP2PLUS
+ depends on ARCH_OMAP2PLUS || ARCH_K3
help
Add support for the OMAP2+ I2C driver.
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index dc40055..c2f75d8 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -3,7 +3,6 @@
# (C) Copyright 2000-2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-$(CONFIG_DM_I2C) += i2c-uclass.o
-obj-$(CONFIG_DM_I2C_COMPAT) += i2c-uclass-compat.o
obj-$(CONFIG_DM_I2C_GPIO) += i2c-gpio.o
obj-$(CONFIG_$(SPL_)I2C_CROS_EC_TUNNEL) += cros_ec_tunnel.o
obj-$(CONFIG_$(SPL_)I2C_CROS_EC_LDO) += cros_ec_ldo.o
diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index 9ccc241..6daa90e 100644
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -4,6 +4,7 @@
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
*/
+#include <clk.h>
#include <common.h>
#include <dm.h>
#include <i2c.h>
@@ -35,6 +36,9 @@
struct i2c_regs *regs;
struct dw_scl_sda_cfg *scl_sda_cfg;
struct reset_ctl_bulk resets;
+#if CONFIG_IS_ENABLED(CLK)
+ struct clk clk;
+#endif
};
#ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
@@ -78,10 +82,12 @@
*/
static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base,
struct dw_scl_sda_cfg *scl_sda_cfg,
- unsigned int speed)
+ unsigned int speed,
+ unsigned int bus_mhz)
{
unsigned int cntl;
unsigned int hcnt, lcnt;
+ unsigned int ena;
int i2c_spd;
if (speed >= I2C_MAX_SPEED)
@@ -91,6 +97,9 @@
else
i2c_spd = IC_SPEED_MODE_STANDARD;
+ /* Get enable setting for restore later */
+ ena = readl(&i2c_base->ic_enable) & IC_ENABLE_0B;
+
/* to set speed cltr must be disabled */
dw_i2c_enable(i2c_base, false);
@@ -104,8 +113,8 @@
hcnt = scl_sda_cfg->fs_hcnt;
lcnt = scl_sda_cfg->fs_lcnt;
} else {
- hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
- lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
+ hcnt = (bus_mhz * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
+ lcnt = (bus_mhz * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
}
writel(hcnt, &i2c_base->ic_hs_scl_hcnt);
writel(lcnt, &i2c_base->ic_hs_scl_lcnt);
@@ -118,8 +127,8 @@
hcnt = scl_sda_cfg->ss_hcnt;
lcnt = scl_sda_cfg->ss_lcnt;
} else {
- hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
- lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
+ hcnt = (bus_mhz * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
+ lcnt = (bus_mhz * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
}
writel(hcnt, &i2c_base->ic_ss_scl_hcnt);
writel(lcnt, &i2c_base->ic_ss_scl_lcnt);
@@ -132,8 +141,8 @@
hcnt = scl_sda_cfg->fs_hcnt;
lcnt = scl_sda_cfg->fs_lcnt;
} else {
- hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
- lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
+ hcnt = (bus_mhz * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
+ lcnt = (bus_mhz * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
}
writel(hcnt, &i2c_base->ic_fs_scl_hcnt);
writel(lcnt, &i2c_base->ic_fs_scl_lcnt);
@@ -146,8 +155,9 @@
if (scl_sda_cfg)
writel(scl_sda_cfg->sda_hold, &i2c_base->ic_sda_hold);
- /* Enable back i2c now speed set */
- dw_i2c_enable(i2c_base, true);
+ /* Restore back i2c now speed set */
+ if (ena == IC_ENABLE_0B)
+ dw_i2c_enable(i2c_base, true);
return 0;
}
@@ -388,7 +398,7 @@
writel(IC_TX_TL, &i2c_base->ic_tx_tl);
writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
#ifndef CONFIG_DM_I2C
- __dw_i2c_set_bus_speed(i2c_base, NULL, speed);
+ __dw_i2c_set_bus_speed(i2c_base, NULL, speed, IC_CLK);
writel(slaveaddr, &i2c_base->ic_sar);
#endif
@@ -433,7 +443,7 @@
unsigned int speed)
{
adap->speed = speed;
- return __dw_i2c_set_bus_speed(i2c_get_base(adap), NULL, speed);
+ return __dw_i2c_set_bus_speed(i2c_get_base(adap), NULL, speed, IC_CLK);
}
static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
@@ -523,8 +533,20 @@
static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
{
struct dw_i2c *i2c = dev_get_priv(bus);
+ ulong rate;
- return __dw_i2c_set_bus_speed(i2c->regs, i2c->scl_sda_cfg, speed);
+#if CONFIG_IS_ENABLED(CLK)
+ rate = clk_get_rate(&i2c->clk);
+ if (IS_ERR_VALUE(rate))
+ return -EINVAL;
+
+ /* Convert to MHz */
+ rate /= 1000000;
+#else
+ rate = IC_CLK;
+#endif
+ return __dw_i2c_set_bus_speed(i2c->regs, i2c->scl_sda_cfg, speed,
+ rate);
}
static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
@@ -568,6 +590,19 @@
else
reset_deassert_bulk(&priv->resets);
+#if CONFIG_IS_ENABLED(CLK)
+ ret = clk_get_by_index(bus, 0, &priv->clk);
+ if (ret)
+ return ret;
+
+ ret = clk_enable(&priv->clk);
+ if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
+ clk_free(&priv->clk);
+ dev_err(bus, "failed to enable clock\n");
+ return ret;
+ }
+#endif
+
return __dw_i2c_init(priv->regs, 0, 0);
}
@@ -575,6 +610,11 @@
{
struct dw_i2c *priv = dev_get_priv(dev);
+#if CONFIG_IS_ENABLED(CLK)
+ clk_disable(&priv->clk);
+ clk_free(&priv->clk);
+#endif
+
return reset_release_bulk(&priv->resets);
}
diff --git a/drivers/i2c/i2c-uclass-compat.c b/drivers/i2c/i2c-uclass-compat.c
deleted file mode 100644
index b3ade88..0000000
--- a/drivers/i2c/i2c-uclass-compat.c
+++ /dev/null
@@ -1,128 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2014 Google, Inc
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <i2c.h>
-
-static int cur_busnum __attribute__((section(".data")));
-
-static int i2c_compat_get_device(uint chip_addr, int alen,
- struct udevice **devp)
-{
- struct dm_i2c_chip *chip;
- int ret;
-
- ret = i2c_get_chip_for_busnum(cur_busnum, chip_addr, alen, devp);
- if (ret)
- return ret;
- chip = dev_get_parent_platdata(*devp);
- if (chip->offset_len != alen) {
- printf("I2C chip %x: requested alen %d does not match chip offset_len %d\n",
- chip_addr, alen, chip->offset_len);
- return -EADDRNOTAVAIL;
- }
-
- return 0;
-}
-
-int i2c_probe(uint8_t chip_addr)
-{
- struct udevice *bus, *dev;
- int ret;
-
- ret = uclass_get_device_by_seq(UCLASS_I2C, cur_busnum, &bus);
- if (ret) {
- debug("Cannot find I2C bus %d: err=%d\n", cur_busnum, ret);
- return ret;
- }
-
- if (!bus)
- return -ENOENT;
-
- return dm_i2c_probe(bus, chip_addr, 0, &dev);
-}
-
-int i2c_read(uint8_t chip_addr, unsigned int addr, int alen, uint8_t *buffer,
- int len)
-{
- struct udevice *dev;
- int ret;
-
- ret = i2c_compat_get_device(chip_addr, alen, &dev);
- if (ret)
- return ret;
-
- return dm_i2c_read(dev, addr, buffer, len);
-}
-
-int i2c_write(uint8_t chip_addr, unsigned int addr, int alen, uint8_t *buffer,
- int len)
-{
- struct udevice *dev;
- int ret;
-
- ret = i2c_compat_get_device(chip_addr, alen, &dev);
- if (ret)
- return ret;
-
- return dm_i2c_write(dev, addr, buffer, len);
-}
-
-int i2c_get_bus_num_fdt(int node)
-{
- struct udevice *bus;
- int ret;
-
- ret = uclass_get_device_by_of_offset(UCLASS_I2C, node, &bus);
- if (ret)
- return ret;
-
- return bus->seq;
-}
-
-unsigned int i2c_get_bus_num(void)
-{
- return cur_busnum;
-}
-
-int i2c_set_bus_num(unsigned int bus)
-{
- cur_busnum = bus;
-
- return 0;
-}
-
-void i2c_init(int speed, int slaveaddr)
-{
- /* Nothing to do here - the init happens through driver model */
-}
-
-void board_i2c_init(const void *blob)
-{
- /* Nothing to do here - the init happens through driver model */
-}
-
-uint8_t i2c_reg_read(uint8_t chip_addr, uint8_t offset)
-{
- struct udevice *dev;
- int ret;
-
- ret = i2c_compat_get_device(chip_addr, 1, &dev);
- if (ret)
- return 0xff;
- return dm_i2c_reg_read(dev, offset);
-}
-
-void i2c_reg_write(uint8_t chip_addr, uint8_t offset, uint8_t val)
-{
- struct udevice *dev;
- int ret;
-
- ret = i2c_compat_get_device(chip_addr, 1, &dev);
- if (!ret)
- dm_i2c_reg_write(dev, offset, val);
-}
diff --git a/drivers/i2c/muxes/i2c-mux-gpio.c b/drivers/i2c/muxes/i2c-mux-gpio.c
index 28f6400..e8b124f 100644
--- a/drivers/i2c/muxes/i2c-mux-gpio.c
+++ b/drivers/i2c/muxes/i2c-mux-gpio.c
@@ -106,7 +106,7 @@
}
ret = gpio_request_list_by_name(dev, "mux-gpios", gpios, mux->n_gpios,
- GPIOD_IS_OUT_ACTIVE);
+ GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
if (ret <= 0) {
dev_err(dev, "Failed to request mux-gpios\n");
return ret;
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 23119cc..786b5a2 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -149,7 +149,12 @@
#endif
/* Divider value calculation */
+#if CONFIG_IS_ENABLED(CLK)
+ i2c_clk_rate = clk_get_rate(&i2c_bus->per_clk);
+#else
i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK);
+#endif
+
div = (i2c_clk_rate + rate - 1) / rate;
if (div < i2c_clk_div[0][0])
clk_div = 0;
@@ -558,6 +563,14 @@
return 0;
}
+int __enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
+{
+ return 1;
+}
+
+int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
+ __attribute__((weak, alias("__enable_i2c_clk")));
+
#ifndef CONFIG_DM_I2C
/*
* Read data from I2C device
@@ -723,13 +736,6 @@
return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0);
}
-int __enable_i2c_clk(unsigned char enable, unsigned i2c_num)
-{
- return 1;
-}
-int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
- __attribute__((weak, alias("__enable_i2c_clk")));
-
void bus_i2c_init(int index, int speed, int unused,
int (*idle_bus_fn)(void *p), void *idle_bus_data)
{
@@ -890,9 +896,22 @@
i2c_bus->bus = bus;
/* Enable clk */
+#if CONFIG_IS_ENABLED(CLK)
+ ret = clk_get_by_index(bus, 0, &i2c_bus->per_clk);
+ if (ret) {
+ printf("Failed to get i2c clk\n");
+ return ret;
+ }
+ ret = clk_enable(&i2c_bus->per_clk);
+ if (ret) {
+ printf("Failed to enable i2c clk\n");
+ return ret;
+ }
+#else
ret = enable_i2c_clk(1, bus->seq);
if (ret < 0)
return ret;
+#endif
/*
* See Documentation/devicetree/bindings/i2c/i2c-imx.txt
@@ -916,13 +935,6 @@
}
}
- ret = i2c_idle_bus(i2c_bus);
- if (ret < 0) {
- /* Disable clk */
- enable_i2c_clk(0, bus->seq);
- return ret;
- }
-
/*
* Pinmux settings are in board file now, until pinmux is supported,
* we can set pinmux here in probe function.
diff --git a/drivers/i2c/stm32f7_i2c.c b/drivers/i2c/stm32f7_i2c.c
index 50c4fd0..2b18735 100644
--- a/drivers/i2c/stm32f7_i2c.c
+++ b/drivers/i2c/stm32f7_i2c.c
@@ -519,13 +519,13 @@
/* Compute possible values for PRESC, SCLDEL and SDADEL */
for (p = 0; p < STM32_PRESC_MAX; p++) {
for (l = 0; l < STM32_SCLDEL_MAX; l++) {
- u32 scldel = (l + 1) * (p + 1) * i2cclk;
+ int scldel = (l + 1) * (p + 1) * i2cclk;
if (scldel < scldel_min)
continue;
for (a = 0; a < STM32_SDADEL_MAX; a++) {
- u32 sdadel = (a * (p + 1) + 1) * i2cclk;
+ int sdadel = (a * (p + 1) + 1) * i2cclk;
if (((sdadel >= sdadel_min) &&
(sdadel <= sdadel_max)) &&
@@ -613,10 +613,12 @@
if ((tscl >= clk_min) && (tscl <= clk_max) &&
(tscl_h >= i2c_specs[setup->speed].h_min) &&
(i2cclk < tscl_h)) {
- int clk_error = tscl - i2cbus;
+ u32 clk_error;
- if (clk_error < 0)
- clk_error = -clk_error;
+ if (tscl > i2cbus)
+ clk_error = tscl - i2cbus;
+ else
+ clk_error = i2cbus - tscl;
if (clk_error < clk_error_prev) {
clk_error_prev = clk_error;
diff --git a/drivers/i2c/xilinx_xiic.c b/drivers/i2c/xilinx_xiic.c
index 83114ed..5ce0f86 100644
--- a/drivers/i2c/xilinx_xiic.c
+++ b/drivers/i2c/xilinx_xiic.c
@@ -149,7 +149,7 @@
while (len--) {
u16 data = msg->buf[pos++];
- if (pos == len && nmsgs == 1) {
+ if ((msg->len - pos == 0) && nmsgs == 1) {
/* last message in transfer -> STOP */
data |= XIIC_TX_DYN_STOP_MASK;
}
@@ -266,8 +266,20 @@
static int xilinx_xiic_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
{
+ struct xilinx_xiic_priv *priv = dev_get_priv(dev);
int ret = 0;
+ ret = wait_for_bit_8(priv->base + XIIC_SR_REG_OFFSET,
+ XIIC_SR_BUS_BUSY_MASK, false, 1000, true);
+
+ if (ret == -ETIMEDOUT)
+ dev_err(dev, "timeout waiting for bus not busy condition\n");
+
+ if (ret)
+ return ret;
+
+ xiic_reinit(priv);
+
for (; nmsgs > 0; nmsgs--, msg++) {
if (msg->flags & I2C_M_RD)
ret = xilinx_xiic_read_common(dev, msg, nmsgs);
diff --git a/drivers/input/i8042.c b/drivers/input/i8042.c
index 9a5dc46..9801589 100644
--- a/drivers/input/i8042.c
+++ b/drivers/input/i8042.c
@@ -8,6 +8,7 @@
#include <common.h>
#include <dm.h>
+#include <env.h>
#include <errno.h>
#include <i8042.h>
#include <input.h>
diff --git a/drivers/input/input.c b/drivers/input/input.c
index 4f514db..6ab378b 100644
--- a/drivers/input/input.c
+++ b/drivers/input/input.c
@@ -9,6 +9,7 @@
#include <common.h>
#include <console.h>
#include <dm.h>
+#include <env.h>
#include <errno.h>
#include <stdio_dev.h>
#include <input.h>
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index 2836ee4..11bf552 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -24,6 +24,13 @@
This enables support for the NVIDIA Tegra HSP Hw module, which
implements doorbells, mailboxes, semaphores, and shared interrupts.
+config STM32_IPCC
+ bool "Enable STM32 IPCC controller support"
+ depends on DM_MAILBOX && ARCH_STM32MP
+ help
+ This enables support for the STM32MP IPCC Hw module, which
+ implements doorbells between 2 processors.
+
config K3_SEC_PROXY
bool "Texas Instruments K3 Secure Proxy Driver"
depends on DM_MAILBOX && ARCH_K3
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index cd23769..a753cc4 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -6,5 +6,6 @@
obj-$(CONFIG_$(SPL_)DM_MAILBOX) += mailbox-uclass.o
obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox.o
obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox-test.o
+obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o
obj-$(CONFIG_TEGRA_HSP) += tegra-hsp.o
obj-$(CONFIG_K3_SEC_PROXY) += k3-sec-proxy.o
diff --git a/drivers/mailbox/stm32-ipcc.c b/drivers/mailbox/stm32-ipcc.c
new file mode 100644
index 0000000..c3df967
--- /dev/null
+++ b/drivers/mailbox/stm32-ipcc.c
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <mailbox-uclass.h>
+#include <asm/io.h>
+
+/*
+ * IPCC has one set of registers per CPU
+ * IPCC_PROC_OFFST allows to define cpu registers set base address
+ * according to the assigned proc_id.
+ */
+
+#define IPCC_PROC_OFFST 0x010
+
+#define IPCC_XSCR 0x008
+#define IPCC_XTOYSR 0x00c
+
+#define IPCC_HWCFGR 0x3f0
+#define IPCFGR_CHAN_MASK GENMASK(7, 0)
+
+#define RX_BIT_CHAN(chan) BIT(chan)
+#define TX_BIT_SHIFT 16
+#define TX_BIT_CHAN(chan) BIT(TX_BIT_SHIFT + (chan))
+
+#define STM32_MAX_PROCS 2
+
+struct stm32_ipcc {
+ void __iomem *reg_base;
+ void __iomem *reg_proc;
+ u32 proc_id;
+ u32 n_chans;
+};
+
+static int stm32_ipcc_request(struct mbox_chan *chan)
+{
+ struct stm32_ipcc *ipcc = dev_get_priv(chan->dev);
+
+ debug("%s(chan=%p)\n", __func__, chan);
+
+ if (chan->id >= ipcc->n_chans) {
+ debug("%s failed to request channel: %ld\n",
+ __func__, chan->id);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int stm32_ipcc_free(struct mbox_chan *chan)
+{
+ debug("%s(chan=%p)\n", __func__, chan);
+
+ return 0;
+}
+
+static int stm32_ipcc_send(struct mbox_chan *chan, const void *data)
+{
+ struct stm32_ipcc *ipcc = dev_get_priv(chan->dev);
+
+ debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
+
+ if (readl(ipcc->reg_proc + IPCC_XTOYSR) & BIT(chan->id))
+ return -EBUSY;
+
+ /* set channel n occupied */
+ setbits_le32(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan->id));
+
+ return 0;
+}
+
+static int stm32_ipcc_recv(struct mbox_chan *chan, void *data)
+{
+ struct stm32_ipcc *ipcc = dev_get_priv(chan->dev);
+ u32 val;
+ int proc_offset;
+
+ debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
+
+ /* read 'channel occupied' status from other proc */
+ proc_offset = ipcc->proc_id ? -IPCC_PROC_OFFST : IPCC_PROC_OFFST;
+ val = readl(ipcc->reg_proc + proc_offset + IPCC_XTOYSR);
+
+ if (!(val & BIT(chan->id)))
+ return -ENODATA;
+
+ setbits_le32(ipcc->reg_proc + IPCC_XSCR, RX_BIT_CHAN(chan->id));
+
+ return 0;
+}
+
+static int stm32_ipcc_probe(struct udevice *dev)
+{
+ struct stm32_ipcc *ipcc = dev_get_priv(dev);
+ fdt_addr_t addr;
+ const fdt32_t *cell;
+ struct clk clk;
+ int len, ret;
+
+ debug("%s(dev=%p)\n", __func__, dev);
+
+ addr = dev_read_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ ipcc->reg_base = (void __iomem *)addr;
+
+ /* proc_id */
+ cell = dev_read_prop(dev, "st,proc_id", &len);
+ if (len < sizeof(fdt32_t)) {
+ dev_dbg(dev, "Missing st,proc_id\n");
+ return -EINVAL;
+ }
+
+ ipcc->proc_id = fdtdec_get_number(cell, 1);
+
+ if (ipcc->proc_id >= STM32_MAX_PROCS) {
+ dev_err(dev, "Invalid proc_id (%d)\n", ipcc->proc_id);
+ return -EINVAL;
+ }
+
+ ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST;
+
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret)
+ return ret;
+
+ ret = clk_enable(&clk);
+ if (ret)
+ goto clk_free;
+
+ /* get channel number */
+ ipcc->n_chans = readl(ipcc->reg_base + IPCC_HWCFGR);
+ ipcc->n_chans &= IPCFGR_CHAN_MASK;
+
+ return 0;
+
+clk_free:
+ clk_free(&clk);
+
+ return ret;
+}
+
+static const struct udevice_id stm32_ipcc_ids[] = {
+ { .compatible = "st,stm32mp1-ipcc" },
+ { }
+};
+
+struct mbox_ops stm32_ipcc_mbox_ops = {
+ .request = stm32_ipcc_request,
+ .free = stm32_ipcc_free,
+ .send = stm32_ipcc_send,
+ .recv = stm32_ipcc_recv,
+};
+
+U_BOOT_DRIVER(stm32_ipcc) = {
+ .name = "stm32_ipcc",
+ .id = UCLASS_MAILBOX,
+ .of_match = stm32_ipcc_ids,
+ .probe = stm32_ipcc_probe,
+ .priv_auto_alloc_size = sizeof(struct stm32_ipcc),
+ .ops = &stm32_ipcc_mbox_ops,
+};
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index cb8b5c0..8037b6e 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -88,6 +88,7 @@
config SPL_CROS_EC
bool "Enable Chrome OS EC in SPL"
+ depends on SPL
help
Enable access to the Chrome OS EC in SPL. This is a separate
microcontroller typically available on a SPI bus on Chromebooks. It
@@ -97,6 +98,7 @@
config TPL_CROS_EC
bool "Enable Chrome OS EC in TPL"
+ depends on TPL
help
Enable access to the Chrome OS EC in TPL. This is a separate
microcontroller typically available on a SPI bus on Chromebooks. It
diff --git a/drivers/misc/fs_loader.c b/drivers/misc/fs_loader.c
index f42eeff..88e486e 100644
--- a/drivers/misc/fs_loader.c
+++ b/drivers/misc/fs_loader.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
#include <dm.h>
+#include <env.h>
#include <errno.h>
#include <blk.h>
#include <fs.h>
diff --git a/drivers/misc/i2c_eeprom.c b/drivers/misc/i2c_eeprom.c
index f25d054..8f2349a 100644
--- a/drivers/misc/i2c_eeprom.c
+++ b/drivers/misc/i2c_eeprom.c
@@ -84,6 +84,14 @@
static int i2c_eeprom_std_probe(struct udevice *dev)
{
+ u8 test_byte;
+ int ret;
+
+ /* Verify that the chip is functional */
+ ret = i2c_eeprom_read(dev, 0, &test_byte, 1);
+ if (ret)
+ return -ENODEV;
+
return 0;
}
diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c
index d9c4d5d..031bc00 100644
--- a/drivers/misc/imx8/scu_api.c
+++ b/drivers/misc/imx8/scu_api.c
@@ -273,6 +273,34 @@
return 0;
}
+int sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, sc_misc_temp_t temp,
+ s16 *celsius, s8 *tenths)
+{
+ struct udevice *dev = gd->arch.scu_dev;
+ int size = sizeof(struct sc_rpc_msg_s);
+ struct sc_rpc_msg_s msg;
+ int ret;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (u8)SC_RPC_SVC_MISC;
+ RPC_FUNC(&msg) = (u8)MISC_FUNC_GET_TEMP;
+ RPC_U16(&msg, 0U) = (u16)resource;
+ RPC_U8(&msg, 2U) = (u8)temp;
+ RPC_SIZE(&msg) = 2U;
+
+ ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size);
+ if (ret < 0)
+ return ret;
+
+ if (celsius)
+ *celsius = RPC_I16(&msg, 0U);
+
+ if (tenths)
+ *tenths = RPC_I8(&msg, 2U);
+
+ return 0;
+}
+
/* RM */
sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr)
{
diff --git a/drivers/misc/stm32_rcc.c b/drivers/misc/stm32_rcc.c
index 13d7069..e7efcde 100644
--- a/drivers/misc/stm32_rcc.c
+++ b/drivers/misc/stm32_rcc.c
@@ -68,8 +68,6 @@
dev_ofnode(dev), &child);
}
-static const struct misc_ops stm32_rcc_ops = {
-};
static const struct udevice_id stm32_rcc_ids[] = {
{.compatible = "st,stm32f42xx-rcc", .data = (ulong)&stm32_rcc_clk_f42x },
@@ -82,8 +80,7 @@
U_BOOT_DRIVER(stm32_rcc) = {
.name = "stm32-rcc",
- .id = UCLASS_MISC,
+ .id = UCLASS_NOP,
.of_match = stm32_rcc_ids,
.bind = stm32_rcc_bind,
- .ops = &stm32_rcc_ops,
};
diff --git a/drivers/misc/stm32mp_fuse.c b/drivers/misc/stm32mp_fuse.c
index 8dc246b..0eed345 100644
--- a/drivers/misc/stm32mp_fuse.c
+++ b/drivers/misc/stm32mp_fuse.c
@@ -5,6 +5,7 @@
#include <common.h>
#include <command.h>
+#include <fuse.h>
#include <misc.h>
#include <errno.h>
#include <dm/device.h>
@@ -19,7 +20,7 @@
*/
int fuse_read(u32 bank, u32 word, u32 *val)
{
- int ret = 0;
+ int ret;
struct udevice *dev;
switch (bank) {
@@ -31,15 +32,25 @@
return ret;
ret = misc_read(dev, word * 4 + STM32_BSEC_SHADOW_OFFSET,
val, 4);
- if (ret < 0)
- return ret;
- ret = 0;
+ if (ret != 4)
+ ret = -EINVAL;
+ else
+ ret = 0;
break;
#ifdef CONFIG_PMIC_STPMIC1
case STM32MP_NVM_BANK:
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_GET_DRIVER(stpmic1_nvm),
+ &dev);
+ if (ret)
+ return ret;
*val = 0;
- ret = stpmic1_shadow_read_byte(word, (u8 *)val);
+ ret = misc_read(dev, -word, val, 1);
+ if (ret != 1)
+ ret = -EINVAL;
+ else
+ ret = 0;
break;
#endif /* CONFIG_PMIC_STPMIC1 */
@@ -66,14 +77,24 @@
return ret;
ret = misc_write(dev, word * 4 + STM32_BSEC_OTP_OFFSET,
&val, 4);
- if (ret < 0)
- return ret;
- ret = 0;
+ if (ret != 4)
+ ret = -EINVAL;
+ else
+ ret = 0;
break;
#ifdef CONFIG_PMIC_STPMIC1
case STM32MP_NVM_BANK:
- ret = stpmic1_nvm_write_byte(word, (u8 *)&val);
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_GET_DRIVER(stpmic1_nvm),
+ &dev);
+ if (ret)
+ return ret;
+ ret = misc_write(dev, word, &val, 1);
+ if (ret != 1)
+ ret = -EINVAL;
+ else
+ ret = 0;
break;
#endif /* CONFIG_PMIC_STPMIC1 */
@@ -99,15 +120,25 @@
if (ret)
return ret;
ret = misc_read(dev, word * 4 + STM32_BSEC_OTP_OFFSET, val, 4);
- if (ret < 0)
- return ret;
- ret = 0;
+ if (ret != 4)
+ ret = -EINVAL;
+ else
+ ret = 0;
break;
#ifdef CONFIG_PMIC_STPMIC1
case STM32MP_NVM_BANK:
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_GET_DRIVER(stpmic1_nvm),
+ &dev);
+ if (ret)
+ return ret;
*val = 0;
- ret = stpmic1_nvm_read_byte(word, (u8 *)val);
+ ret = misc_read(dev, word, val, 1);
+ if (ret != 1)
+ ret = -EINVAL;
+ else
+ ret = 0;
break;
#endif /* CONFIG_PMIC_STPMIC1 */
@@ -134,14 +165,24 @@
return ret;
ret = misc_write(dev, word * 4 + STM32_BSEC_SHADOW_OFFSET,
&val, 4);
- if (ret < 0)
- return ret;
- ret = 0;
+ if (ret != 4)
+ ret = -EINVAL;
+ else
+ ret = 0;
break;
#ifdef CONFIG_PMIC_STPMIC1
case STM32MP_NVM_BANK:
- ret = stpmic1_shadow_write_byte(word, (u8 *)&val);
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_GET_DRIVER(stpmic1_nvm),
+ &dev);
+ if (ret)
+ return ret;
+ ret = misc_write(dev, -word, &val, 1);
+ if (ret != 1)
+ ret = -EINVAL;
+ else
+ ret = 0;
break;
#endif /* CONFIG_PMIC_STPMIC1 */
diff --git a/drivers/misc/swap_case.c b/drivers/misc/swap_case.c
index fa608ce..6afc6d9 100644
--- a/drivers/misc/swap_case.c
+++ b/drivers/misc/swap_case.c
@@ -61,11 +61,63 @@
return plat->devfn;
}
+static int sandbox_swap_case_use_ea(struct udevice *dev)
+{
+ return !!ofnode_get_property(dev->node, "use-ea", NULL);
+}
+
+/* Please keep these macros in sync with ea_regs below */
+#define PCI_CAP_ID_EA_SIZE (sizeof(ea_regs) + 4)
+#define PCI_CAP_ID_EA_ENTRY_CNT 4
+/* Hardcoded EA structure, excluding 1st DW. */
+static const u32 ea_regs[] = {
+ /* BEI=0, ES=2, BAR0 32b Base + 32b MaxOffset, I/O space */
+ (2 << 8) | 2,
+ PCI_CAP_EA_BASE_LO0,
+ 0,
+ /* BEI=1, ES=2, BAR1 32b Base + 32b MaxOffset */
+ (1 << 4) | 2,
+ PCI_CAP_EA_BASE_LO1,
+ MEM_TEXT_SIZE - 1,
+ /* BEI=2, ES=3, BAR2 64b Base + 32b MaxOffset */
+ (2 << 4) | 3,
+ PCI_CAP_EA_BASE_LO2 | PCI_EA_IS_64,
+ PCI_CAP_EA_SIZE_LO,
+ PCI_CAP_EA_BASE_HI2,
+ /* BEI=4, ES=4, BAR4 64b Base + 64b MaxOffset */
+ (4 << 4) | 4,
+ PCI_CAP_EA_BASE_LO4 | PCI_EA_IS_64,
+ PCI_CAP_EA_SIZE_LO | PCI_EA_IS_64,
+ PCI_CAP_EA_BASE_HI4,
+ PCI_CAP_EA_SIZE_HI,
+};
+
+static int sandbox_swap_case_read_ea(struct udevice *emul, uint offset,
+ ulong *valuep, enum pci_size_t size)
+{
+ u32 reg;
+
+ offset = offset - PCI_CAP_ID_EA_OFFSET - 4;
+ reg = ea_regs[offset >> 2];
+ reg >>= (offset % 4) * 8;
+
+ *valuep = reg;
+ return 0;
+}
+
static int sandbox_swap_case_read_config(struct udevice *emul, uint offset,
ulong *valuep, enum pci_size_t size)
{
struct swap_case_platdata *plat = dev_get_platdata(emul);
+ /*
+ * The content of the EA capability structure is handled elsewhere to
+ * keep the switch/case below sane
+ */
+ if (offset > PCI_CAP_ID_EA_OFFSET + PCI_CAP_LIST_NEXT &&
+ offset < PCI_CAP_ID_EA_OFFSET + PCI_CAP_ID_EA_SIZE)
+ return sandbox_swap_case_read_ea(emul, offset, valuep, size);
+
switch (offset) {
case PCI_COMMAND:
*valuep = plat->command;
@@ -134,9 +186,21 @@
*valuep = PCI_CAP_ID_MSIX_OFFSET;
break;
case PCI_CAP_ID_MSIX_OFFSET:
- *valuep = PCI_CAP_ID_MSIX;
+ if (sandbox_swap_case_use_ea(emul))
+ *valuep = (PCI_CAP_ID_EA_OFFSET << 8) | PCI_CAP_ID_MSIX;
+ else
+ *valuep = PCI_CAP_ID_MSIX;
break;
case PCI_CAP_ID_MSIX_OFFSET + PCI_CAP_LIST_NEXT:
+ if (sandbox_swap_case_use_ea(emul))
+ *valuep = PCI_CAP_ID_EA_OFFSET;
+ else
+ *valuep = 0;
+ break;
+ case PCI_CAP_ID_EA_OFFSET:
+ *valuep = (PCI_CAP_ID_EA_ENTRY_CNT << 16) | PCI_CAP_ID_EA;
+ break;
+ case PCI_CAP_ID_EA_OFFSET + PCI_CAP_LIST_NEXT:
*valuep = 0;
break;
case PCI_EXT_CAP_ID_ERR_OFFSET:
@@ -257,6 +321,9 @@
return 0;
}
+static int pci_ea_bar2_magic = PCI_EA_BAR2_MAGIC;
+static int pci_ea_bar4_magic = PCI_EA_BAR4_MAGIC;
+
static int sandbox_swap_case_map_physmem(struct udevice *dev,
phys_addr_t addr, unsigned long *lenp, void **ptrp)
{
@@ -265,9 +332,42 @@
int barnum;
int ret;
+ if (sandbox_swap_case_use_ea(dev)) {
+ /*
+ * only support mapping base address in EA test for now, we
+ * don't handle mapping an offset inside a BAR. Seems good
+ * enough for the current test.
+ */
+ switch (addr) {
+ case (phys_addr_t)PCI_CAP_EA_BASE_LO0:
+ *ptrp = &priv->op;
+ *lenp = 4;
+ break;
+ case (phys_addr_t)PCI_CAP_EA_BASE_LO1:
+ *ptrp = priv->mem_text;
+ *lenp = barinfo[1].size - 1;
+ break;
+ case (phys_addr_t)((PCI_CAP_EA_BASE_HI2 << 32) |
+ PCI_CAP_EA_BASE_LO2):
+ *ptrp = &pci_ea_bar2_magic;
+ *lenp = PCI_CAP_EA_SIZE_LO;
+ break;
+ case (phys_addr_t)((PCI_CAP_EA_BASE_HI4 << 32) |
+ PCI_CAP_EA_BASE_LO4):
+ *ptrp = &pci_ea_bar4_magic;
+ *lenp = (PCI_CAP_EA_SIZE_HI << 32) |
+ PCI_CAP_EA_SIZE_LO;
+ break;
+ default:
+ return -ENOENT;
+ }
+ return 0;
+ }
+
ret = sandbox_swap_case_find_bar(dev, addr, &barnum, &offset);
if (ret)
return ret;
+
if (barnum == 1) {
*ptrp = priv->mem_text + offset;
avail = barinfo[1].size - offset;
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index c23299e..7361bca 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -46,6 +46,24 @@
if MMC
+config MMC_SPI
+ bool "Support for SPI-based MMC controller"
+ depends on DM_MMC && DM_SPI
+ help
+ This selects SPI-based MMC controllers.
+ If you have an MMC controller on a SPI bus, say Y here.
+
+ If unsure, say N.
+
+config MMC_SPI_CRC_ON
+ bool "Support CRC for SPI-based MMC controller"
+ depends on MMC_SPI
+ default y
+ help
+ This enables CRC for SPI-based MMC controllers.
+
+ If unsure, say N.
+
config ARM_PL180_MMCI
bool "ARM AMBA Multimedia Card Interface and compatible support"
depends on DM_MMC && OF_CONTROL
@@ -117,6 +135,18 @@
cards. The IO voltage must be switchable from 3.3v to 1.8v. The bus
frequency can go up to 208MHz (SDR104)
+config MMC_HS400_ES_SUPPORT
+ bool "enable HS400 Enhanced Strobe support"
+ help
+ The HS400 Enhanced Strobe mode is support by some eMMC. The bus
+ frequency is up to 200MHz. This mode does not tune the IO.
+
+config SPL_MMC_HS400_ES_SUPPORT
+ bool "enable HS400 Enhanced Strobe support in SPL"
+ help
+ The HS400 Enhanced Strobe mode is support by some eMMC. The bus
+ frequency is up to 200MHz. This mode does not tune the IO.
+
config MMC_HS400_SUPPORT
bool "enable HS400 support"
select MMC_HS200_SUPPORT
@@ -126,6 +156,7 @@
config SPL_MMC_HS400_SUPPORT
bool "enable HS400 support in SPL"
+ select SPL_MMC_HS200_SUPPORT
help
The HS400 mode is support by some eMMC. The bus frequency is up to
200MHz. This mode requires tuning the IO.
@@ -136,7 +167,6 @@
The HS200 mode is support by some eMMC. The bus frequency is up to
200MHz. This mode requires tuning the IO.
-
config SPL_MMC_HS200_SUPPORT
bool "enable HS200 support in SPL"
help
@@ -158,21 +188,6 @@
If you need to see the MMC core message, say Y.
-config SPL_MMC_TINY
- bool "Tiny MMC framework in SPL"
- help
- Enable MMC framework tinification support. This option is useful if
- if your SPL is extremely size constrained. Heed the warning, enable
- this option if and only if you know exactly what you are doing, if
- you are reading this help text, you most likely have no idea :-)
-
- The MMC framework is reduced to bare minimum to be useful. No malloc
- support is needed for the MMC framework operation with this option
- enabled. The framework supports exactly one MMC device and exactly
- one MMC driver. The MMC driver can be adjusted to avoid any malloc
- operations too, which can remove the need for malloc support in SPL
- and thus further reduce footprint.
-
config MMC_DAVINCI
bool "TI DAVINCI Multimedia Card Interface support"
depends on ARCH_DAVINCI
@@ -405,6 +420,17 @@
This enables support for the ADMA (Advanced DMA) defined
in the SD Host Controller Standard Specification Version 3.00 in SPL.
+config MMC_SDHCI_ASPEED
+ bool "Aspeed SDHCI controller"
+ depends on ARCH_ASPEED
+ depends on DM_MMC
+ depends on MMC_SDHCI
+ help
+ Enables support for the Aspeed SDHCI 2.0 controller present on Aspeed
+ SoCs. This device is compatible with SD 3.0 and/or MMC 4.3
+ specifications. On the AST2600, the device is also compatible with
+ MMC 5.1 and eMMC 3.0.
+
config MMC_SDHCI_ATMEL
bool "Atmel SDHCI controller support"
depends on ARCH_AT91
@@ -453,14 +479,15 @@
If unsure, say N.
-config MMC_SDHCI_K3_ARASAN
- bool "Arasan SDHCI controller for TI's K3 based SoCs"
+config MMC_SDHCI_AM654
+ bool "SDHCI Controller on TI's Am654 devices"
depends on ARCH_K3
depends on MMC_SDHCI
depends on DM_MMC && OF_CONTROL && BLK
+ depends on REGMAP
help
- Support for Arasan SDHCI host controller on Texas Instruments'
- K3 family based SoC platforms
+ Support for Secure Digital Host Controller Interface (SDHCI)
+ controllers present on TI's AM654 SOCs.
config MMC_SDHCI_KONA
bool "SDHCI support on Broadcom KONA platform"
@@ -575,6 +602,17 @@
If unsure, say N.
+config TEGRA124_MMC_DISABLE_EXT_LOOPBACK
+ bool "Disable external clock loopback"
+ depends on MMC_SDHCI_TEGRA && TEGRA124
+ help
+ Disable the external clock loopback and use the internal one on SDMMC3
+ as per the SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 bits
+ being set to 0xfffd according to the TRM.
+
+ TODO(marcel.ziswiler@toradex.com): Move to device tree controlled
+ approach once proper kernel integration made it mainline.
+
config MMC_SDHCI_ZYNQ
bool "Arasan SDHCI controller support"
depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL
@@ -654,22 +692,33 @@
endif
-config TEGRA124_MMC_DISABLE_EXT_LOOPBACK
- bool "Disable external clock loopback"
- depends on MMC_SDHCI_TEGRA && TEGRA124
- help
- Disable the external clock loopback and use the internal one on SDMMC3
- as per the SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 bits
- being set to 0xfffd according to the TRM.
-
- TODO(marcel.ziswiler@toradex.com): Move to device tree controlled
- approach once proper kernel integration made it mainline.
-
config FSL_ESDHC
bool "Freescale/NXP eSDHC controller support"
+ select FSL_ESDHC_USE_PERIPHERAL_CLK if MMC_HS200_SUPPORT || MMC_UHS_SUPPORT
help
- This selects support for the eSDHC (enhanced secure digital host
- controller) found on numerous Freescale/NXP SoCs.
+ This selects support for the eSDHC (Enhanced Secure Digital Host
+ Controller) found on numerous Freescale/NXP SoCs.
+
+config FSL_ESDHC_USE_PERIPHERAL_CLK
+ bool "enable ESDHC peripheral clock support"
+ depends on FSL_ESDHC
+ help
+ eSDHC supports two reference clocks (platform clock and peripheral clock).
+ Peripheral clock which could provide higher clock frequency is required to
+ be used for tuning of SD UHS mode and eMMC HS200/HS400 modes.
+
+config FSL_ESDHC_IMX
+ bool "Freescale/NXP i.MX eSDHC controller support"
+ help
+ This selects support for the i.MX eSDHC (Enhanced Secure Digital Host
+ Controller) found on numerous Freescale/NXP SoCs.
+
+config FSL_USDHC
+ bool "Freescale/NXP i.MX uSDHC controller support"
+ depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M || TARGET_S32V234EVB
+ select FSL_ESDHC_IMX
+ help
+ This enables the Ultra Secured Digital Host Controller enhancements
endmenu
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 0076fc3..5594195 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -26,6 +26,7 @@
obj-$(CONFIG_MMC_DW_SOCFPGA) += socfpga_dw_mmc.o
obj-$(CONFIG_MMC_DW_SNPS) += snps_dw_mmc.o
obj-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
+obj-$(CONFIG_FSL_ESDHC_IMX) += fsl_esdhc_imx.o
obj-$(CONFIG_FTSDC010) += ftsdc010_mci.o
obj-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o
obj-$(CONFIG_MMC_MESON_GX) += meson_gx_mmc.o
@@ -45,11 +46,12 @@
# SDHCI
obj-$(CONFIG_MMC_SDHCI) += sdhci.o
+obj-$(CONFIG_MMC_SDHCI_ASPEED) += aspeed_sdhci.o
obj-$(CONFIG_MMC_SDHCI_ATMEL) += atmel_sdhci.o
obj-$(CONFIG_MMC_SDHCI_BCM2835) += bcm2835_sdhci.o
obj-$(CONFIG_MMC_SDHCI_BCMSTB) += bcmstb_sdhci.o
obj-$(CONFIG_MMC_SDHCI_CADENCE) += sdhci-cadence.o
-obj-$(CONFIG_MMC_SDHCI_K3_ARASAN) += k3_arsan_sdhci.o
+obj-$(CONFIG_MMC_SDHCI_AM654) += am654_sdhci.o
obj-$(CONFIG_MMC_SDHCI_KONA) += kona_sdhci.o
obj-$(CONFIG_MMC_SDHCI_MSM) += msm_sdhci.o
obj-$(CONFIG_MMC_SDHCI_MV) += mv_sdhci.o
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
new file mode 100644
index 0000000..1793a3f
--- /dev/null
+++ b/drivers/mmc/am654_sdhci.c
@@ -0,0 +1,361 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Texas Instruments' K3 SD Host Controller Interface
+ */
+
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <malloc.h>
+#include <power-domain.h>
+#include <regmap.h>
+#include <sdhci.h>
+
+/* CTL_CFG Registers */
+#define CTL_CFG_2 0x14
+
+#define SLOTTYPE_MASK GENMASK(31, 30)
+#define SLOTTYPE_EMBEDDED BIT(30)
+
+/* PHY Registers */
+#define PHY_CTRL1 0x100
+#define PHY_CTRL2 0x104
+#define PHY_CTRL3 0x108
+#define PHY_CTRL4 0x10C
+#define PHY_CTRL5 0x110
+#define PHY_CTRL6 0x114
+#define PHY_STAT1 0x130
+#define PHY_STAT2 0x134
+
+#define IOMUX_ENABLE_SHIFT 31
+#define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT)
+#define OTAPDLYENA_SHIFT 20
+#define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT)
+#define OTAPDLYSEL_SHIFT 12
+#define OTAPDLYSEL_MASK GENMASK(15, 12)
+#define STRBSEL_SHIFT 24
+#define STRBSEL_MASK GENMASK(27, 24)
+#define SEL50_SHIFT 8
+#define SEL50_MASK BIT(SEL50_SHIFT)
+#define SEL100_SHIFT 9
+#define SEL100_MASK BIT(SEL100_SHIFT)
+#define DLL_TRIM_ICP_SHIFT 4
+#define DLL_TRIM_ICP_MASK GENMASK(7, 4)
+#define DR_TY_SHIFT 20
+#define DR_TY_MASK GENMASK(22, 20)
+#define ENDLL_SHIFT 1
+#define ENDLL_MASK BIT(ENDLL_SHIFT)
+#define DLLRDY_SHIFT 0
+#define DLLRDY_MASK BIT(DLLRDY_SHIFT)
+#define PDB_SHIFT 0
+#define PDB_MASK BIT(PDB_SHIFT)
+#define CALDONE_SHIFT 1
+#define CALDONE_MASK BIT(CALDONE_SHIFT)
+#define RETRIM_SHIFT 17
+#define RETRIM_MASK BIT(RETRIM_SHIFT)
+
+#define DRIVER_STRENGTH_50_OHM 0x0
+#define DRIVER_STRENGTH_33_OHM 0x1
+#define DRIVER_STRENGTH_66_OHM 0x2
+#define DRIVER_STRENGTH_100_OHM 0x3
+#define DRIVER_STRENGTH_40_OHM 0x4
+
+#define AM654_SDHCI_MIN_FREQ 400000
+
+struct am654_sdhci_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+ struct regmap *base;
+ bool non_removable;
+ u32 otap_del_sel;
+ u32 trm_icp;
+ u32 drv_strength;
+ u32 flags;
+#define DLL_PRESENT (1 << 0)
+ bool dll_on;
+};
+
+static void am654_sdhci_set_control_reg(struct sdhci_host *host)
+{
+ struct mmc *mmc = (struct mmc *)host->mmc;
+ u32 reg;
+
+ if (IS_SD(host->mmc) &&
+ mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
+ reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ reg |= SDHCI_CTRL_VDD_180;
+ sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
+ }
+
+ sdhci_set_uhs_timing(host);
+}
+
+static int am654_sdhci_set_ios_post(struct sdhci_host *host)
+{
+ struct udevice *dev = host->mmc->dev;
+ struct am654_sdhci_plat *plat = dev_get_platdata(dev);
+ unsigned int speed = host->mmc->clock;
+ int sel50, sel100;
+ u32 mask, val;
+ int ret;
+
+ /* Reset SD Clock Enable */
+ val = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+ val &= ~SDHCI_CLOCK_CARD_EN;
+ sdhci_writew(host, val, SDHCI_CLOCK_CONTROL);
+
+ /* power off phy */
+ if (plat->dll_on) {
+ regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK, 0);
+
+ plat->dll_on = false;
+ }
+
+ /* restart clock */
+ sdhci_set_clock(host->mmc, speed);
+
+ /* switch phy back on */
+ if (speed > AM654_SDHCI_MIN_FREQ) {
+ mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
+ val = (1 << OTAPDLYENA_SHIFT) |
+ (plat->otap_del_sel << OTAPDLYSEL_SHIFT);
+ regmap_update_bits(plat->base, PHY_CTRL4, mask, val);
+ switch (speed) {
+ case 200000000:
+ sel50 = 0;
+ sel100 = 0;
+ break;
+ case 100000000:
+ sel50 = 0;
+ sel100 = 1;
+ break;
+ default:
+ sel50 = 1;
+ sel100 = 0;
+ }
+
+ /* Configure PHY DLL frequency */
+ mask = SEL50_MASK | SEL100_MASK;
+ val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
+ regmap_update_bits(plat->base, PHY_CTRL5, mask, val);
+
+ /* Enable DLL */
+ regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK,
+ 0x1 << ENDLL_SHIFT);
+ /*
+ * Poll for DLL ready. Use a one second timeout.
+ * Works in all experiments done so far
+ */
+ ret = regmap_read_poll_timeout(plat->base, PHY_STAT1, val,
+ val & DLLRDY_MASK, 1000, 1000000);
+ if (ret)
+ return ret;
+
+ plat->dll_on = true;
+ }
+
+ return 0;
+}
+
+const struct sdhci_ops am654_sdhci_ops = {
+ .set_ios_post = &am654_sdhci_set_ios_post,
+ .set_control_reg = &am654_sdhci_set_control_reg,
+};
+
+const struct sdhci_ops j721e_4bit_sdhci_ops = {
+ .set_control_reg = &am654_sdhci_set_control_reg,
+};
+
+int am654_sdhci_init(struct am654_sdhci_plat *plat)
+{
+ u32 ctl_cfg_2 = 0;
+ u32 mask, val;
+ int ret;
+
+ /* Reset OTAP to default value */
+ mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
+ regmap_update_bits(plat->base, PHY_CTRL4, mask, 0x0);
+
+ if (plat->flags & DLL_PRESENT) {
+ regmap_read(plat->base, PHY_STAT1, &val);
+ if (~val & CALDONE_MASK) {
+ /* Calibrate IO lines */
+ regmap_update_bits(plat->base, PHY_CTRL1, PDB_MASK,
+ PDB_MASK);
+ ret = regmap_read_poll_timeout(plat->base, PHY_STAT1,
+ val, val & CALDONE_MASK,
+ 1, 20);
+ if (ret)
+ return ret;
+ }
+
+ /* Configure DLL TRIM */
+ mask = DLL_TRIM_ICP_MASK;
+ val = plat->trm_icp << DLL_TRIM_ICP_SHIFT;
+
+ /* Configure DLL driver strength */
+ mask |= DR_TY_MASK;
+ val |= plat->drv_strength << DR_TY_SHIFT;
+ regmap_update_bits(plat->base, PHY_CTRL1, mask, val);
+ }
+
+ /* Enable pins by setting IO mux to 0 */
+ regmap_update_bits(plat->base, PHY_CTRL1, IOMUX_ENABLE_MASK, 0);
+
+ /* Set slot type based on SD or eMMC */
+ if (plat->non_removable)
+ ctl_cfg_2 = SLOTTYPE_EMBEDDED;
+
+ regmap_update_bits(plat->base, CTL_CFG_2, SLOTTYPE_MASK, ctl_cfg_2);
+
+ return 0;
+}
+
+static int am654_sdhci_probe(struct udevice *dev)
+{
+ struct am654_sdhci_plat *plat = dev_get_platdata(dev);
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct sdhci_host *host = dev_get_priv(dev);
+ struct mmc_config *cfg = &plat->cfg;
+ struct power_domain sdhci_pwrdmn;
+ struct clk clk;
+ unsigned long clock;
+ int ret;
+
+ ret = power_domain_get_by_index(dev, &sdhci_pwrdmn, 0);
+ if (!ret) {
+ ret = power_domain_on(&sdhci_pwrdmn);
+ if (ret) {
+ dev_err(dev, "Power domain on failed (%d)\n", ret);
+ return ret;
+ }
+ } else if (ret != -ENOENT && ret != -ENODEV && ret != -ENOSYS) {
+ dev_err(dev, "failed to get power domain (%d)\n", ret);
+ return ret;
+ }
+
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret) {
+ dev_err(dev, "failed to get clock\n");
+ return ret;
+ }
+
+ clock = clk_get_rate(&clk);
+ if (IS_ERR_VALUE(clock)) {
+ dev_err(dev, "failed to get rate\n");
+ return clock;
+ }
+
+ host->max_clk = clock;
+ host->mmc = &plat->mmc;
+ host->mmc->dev = dev;
+ ret = sdhci_setup_cfg(cfg, host, cfg->f_max,
+ AM654_SDHCI_MIN_FREQ);
+ if (ret)
+ return ret;
+ host->ops = (struct sdhci_ops *)dev_get_driver_data(dev);
+ host->mmc->priv = host;
+ upriv->mmc = host->mmc;
+
+ regmap_init_mem_index(dev_ofnode(dev), &plat->base, 1);
+
+ am654_sdhci_init(plat);
+
+ return sdhci_probe(dev);
+}
+
+static int am654_sdhci_ofdata_to_platdata(struct udevice *dev)
+{
+ struct am654_sdhci_plat *plat = dev_get_platdata(dev);
+ struct sdhci_host *host = dev_get_priv(dev);
+ struct mmc_config *cfg = &plat->cfg;
+ u32 drv_strength;
+ int ret;
+
+ host->name = dev->name;
+ host->ioaddr = (void *)dev_read_addr(dev);
+ plat->non_removable = dev_read_bool(dev, "non-removable");
+
+ if (device_is_compatible(dev, "ti,am654-sdhci-5.1") ||
+ device_is_compatible(dev, "ti,j721e-sdhci-8bit"))
+ plat->flags |= DLL_PRESENT;
+
+ ret = dev_read_u32(dev, "ti,otap-del-sel", &plat->otap_del_sel);
+ if (ret)
+ return ret;
+
+ if (plat->flags & DLL_PRESENT) {
+ ret = dev_read_u32(dev, "ti,trm-icp", &plat->trm_icp);
+ if (ret)
+ return ret;
+
+ ret = dev_read_u32(dev, "ti,driver-strength-ohm",
+ &drv_strength);
+ if (ret)
+ return ret;
+
+ switch (drv_strength) {
+ case 50:
+ plat->drv_strength = DRIVER_STRENGTH_50_OHM;
+ break;
+ case 33:
+ plat->drv_strength = DRIVER_STRENGTH_33_OHM;
+ break;
+ case 66:
+ plat->drv_strength = DRIVER_STRENGTH_66_OHM;
+ break;
+ case 100:
+ plat->drv_strength = DRIVER_STRENGTH_100_OHM;
+ break;
+ case 40:
+ plat->drv_strength = DRIVER_STRENGTH_40_OHM;
+ break;
+ default:
+ dev_err(dev, "Invalid driver strength\n");
+ return -EINVAL;
+ }
+ }
+
+ ret = mmc_of_parse(dev, cfg);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int am654_sdhci_bind(struct udevice *dev)
+{
+ struct am654_sdhci_plat *plat = dev_get_platdata(dev);
+
+ return sdhci_bind(dev, &plat->mmc, &plat->cfg);
+}
+
+static const struct udevice_id am654_sdhci_ids[] = {
+ {
+ .compatible = "ti,am654-sdhci-5.1",
+ .data = (ulong)&am654_sdhci_ops,
+ },
+ {
+ .compatible = "ti,j721e-sdhci-8bit",
+ .data = (ulong)&am654_sdhci_ops,
+ },
+ {
+ .compatible = "ti,j721e-sdhci-4bit",
+ .data = (ulong)&j721e_4bit_sdhci_ops,
+ },
+ { }
+};
+
+U_BOOT_DRIVER(am654_sdhci_drv) = {
+ .name = "am654_sdhci",
+ .id = UCLASS_MMC,
+ .of_match = am654_sdhci_ids,
+ .ofdata_to_platdata = am654_sdhci_ofdata_to_platdata,
+ .ops = &sdhci_ops,
+ .bind = am654_sdhci_bind,
+ .probe = am654_sdhci_probe,
+ .priv_auto_alloc_size = sizeof(struct sdhci_host),
+ .platdata_auto_alloc_size = sizeof(struct am654_sdhci_plat),
+};
diff --git a/drivers/mmc/aspeed_sdhci.c b/drivers/mmc/aspeed_sdhci.c
new file mode 100644
index 0000000..1321ec3
--- /dev/null
+++ b/drivers/mmc/aspeed_sdhci.c
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 IBM Corp.
+ * Eddie James <eajames@linux.ibm.com>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <malloc.h>
+#include <sdhci.h>
+
+struct aspeed_sdhci_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
+static int aspeed_sdhci_probe(struct udevice *dev)
+{
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct aspeed_sdhci_plat *plat = dev_get_platdata(dev);
+ struct sdhci_host *host = dev_get_priv(dev);
+ u32 max_clk;
+ struct clk clk;
+ int ret;
+
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret)
+ return ret;
+
+ ret = clk_enable(&clk);
+ if (ret)
+ goto free;
+
+ host->name = dev->name;
+ host->ioaddr = (void *)devfdt_get_addr(dev);
+
+ max_clk = clk_get_rate(&clk);
+ if (IS_ERR_VALUE(max_clk)) {
+ ret = max_clk;
+ goto err;
+ }
+
+ host->max_clk = max_clk;
+ host->mmc = &plat->mmc;
+ host->mmc->dev = dev;
+ host->mmc->priv = host;
+ upriv->mmc = host->mmc;
+
+ ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
+ if (ret)
+ goto err;
+
+ ret = sdhci_probe(dev);
+ if (ret)
+ goto err;
+
+ return 0;
+
+err:
+ clk_disable(&clk);
+free:
+ clk_free(&clk);
+ return ret;
+}
+
+static int aspeed_sdhci_bind(struct udevice *dev)
+{
+ struct aspeed_sdhci_plat *plat = dev_get_platdata(dev);
+
+ return sdhci_bind(dev, &plat->mmc, &plat->cfg);
+}
+
+static const struct udevice_id aspeed_sdhci_ids[] = {
+ { .compatible = "aspeed,ast2400-sdhci" },
+ { .compatible = "aspeed,ast2500-sdhci" },
+ { .compatible = "aspeed,ast2600-sdhci" },
+ { }
+};
+
+U_BOOT_DRIVER(aspeed_sdhci_drv) = {
+ .name = "aspeed_sdhci",
+ .id = UCLASS_MMC,
+ .of_match = aspeed_sdhci_ids,
+ .ops = &sdhci_ops,
+ .bind = aspeed_sdhci_bind,
+ .probe = aspeed_sdhci_probe,
+ .priv_auto_alloc_size = sizeof(struct sdhci_host),
+ .platdata_auto_alloc_size = sizeof(struct aspeed_sdhci_plat),
+};
diff --git a/drivers/mmc/atmel_sdhci.c b/drivers/mmc/atmel_sdhci.c
index 4be47ba..d930ed8 100644
--- a/drivers/mmc/atmel_sdhci.c
+++ b/drivers/mmc/atmel_sdhci.c
@@ -88,13 +88,13 @@
return -EINVAL;
host->max_clk = max_clk;
+ host->mmc = &plat->mmc;
+ host->mmc->dev = dev;
ret = sdhci_setup_cfg(&plat->cfg, host, 0, ATMEL_SDHC_MIN_FREQ);
if (ret)
return ret;
- host->mmc = &plat->mmc;
- host->mmc->dev = dev;
host->mmc->priv = host;
upriv->mmc = host->mmc;
diff --git a/drivers/mmc/bcm2835_sdhci.c b/drivers/mmc/bcm2835_sdhci.c
index 08bddd4..bc9ee95 100644
--- a/drivers/mmc/bcm2835_sdhci.c
+++ b/drivers/mmc/bcm2835_sdhci.c
@@ -178,12 +178,13 @@
fdt_addr_t base;
int emmc_freq;
int ret;
+ int clock_id = (int)dev_get_driver_data(dev);
base = devfdt_get_addr(dev);
if (base == FDT_ADDR_T_NONE)
return -EINVAL;
- ret = bcm2835_get_mmc_clock(BCM2835_MBOX_CLOCK_ID_EMMC);
+ ret = bcm2835_get_mmc_clock(clock_id);
if (ret < 0) {
debug("%s: Failed to set MMC clock (err=%d)\n", __func__, ret);
return ret;
@@ -214,6 +215,9 @@
host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
host->ops = &bcm2835_ops;
+ host->mmc = &plat->mmc;
+ host->mmc->dev = dev;
+
ret = sdhci_setup_cfg(&plat->cfg, host, emmc_freq, MIN_FREQ);
if (ret) {
debug("%s: Failed to setup SDHCI (err=%d)\n", __func__, ret);
@@ -221,14 +225,20 @@
}
upriv->mmc = &plat->mmc;
- host->mmc = &plat->mmc;
host->mmc->priv = host;
return sdhci_probe(dev);
}
static const struct udevice_id bcm2835_sdhci_match[] = {
- { .compatible = "brcm,bcm2835-sdhci" },
+ {
+ .compatible = "brcm,bcm2835-sdhci",
+ .data = BCM2835_MBOX_CLOCK_ID_EMMC
+ },
+ {
+ .compatible = "brcm,bcm2711-emmc2",
+ .data = BCM2835_MBOX_CLOCK_ID_EMMC2
+ },
{ /* sentinel */ }
};
diff --git a/drivers/mmc/bcm2835_sdhost.c b/drivers/mmc/bcm2835_sdhost.c
index 1ce019a..7f70aca 100644
--- a/drivers/mmc/bcm2835_sdhost.c
+++ b/drivers/mmc/bcm2835_sdhost.c
@@ -234,7 +234,7 @@
static int bcm2835_wait_transfer_complete(struct bcm2835_host *host)
{
- int timediff = 0;
+ ulong tstart_ms = get_timer(0);
while (1) {
u32 edm, fsm;
@@ -254,11 +254,13 @@
break;
}
- /* Error out after 100000 register reads (~1s) */
- if (timediff++ == 100000) {
+ /* Error out after ~1s */
+ ulong tlapse_ms = get_timer(tstart_ms);
+ if ( tlapse_ms > 1000 /* ms */ ) {
+
dev_err(host->dev,
- "wait_transfer_complete - still waiting after %d retries\n",
- timediff);
+ "wait_transfer_complete - still waiting after %lu ms\n",
+ tlapse_ms);
bcm2835_dumpregs(host);
return -ETIMEDOUT;
}
diff --git a/drivers/mmc/bcmstb_sdhci.c b/drivers/mmc/bcmstb_sdhci.c
index eef46f3..c14f828 100644
--- a/drivers/mmc/bcmstb_sdhci.c
+++ b/drivers/mmc/bcmstb_sdhci.c
@@ -73,6 +73,8 @@
if (ret)
return ret;
+ host->mmc = &plat->mmc;
+ host->mmc->dev = dev;
ret = sdhci_setup_cfg(&plat->cfg, host,
BCMSTB_SDHCI_MAXIMUM_CLOCK_FREQUENCY,
BCMSTB_SDHCI_MINIMUM_CLOCK_FREQUENCY);
@@ -80,7 +82,6 @@
return ret;
upriv->mmc = &plat->mmc;
- host->mmc = &plat->mmc;
host->mmc->priv = host;
return sdhci_probe(dev);
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 1992d61..ebe7bcd 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -13,6 +13,7 @@
#include <mmc.h>
#include <dwmmc.h>
#include <wait_bit.h>
+#include <power/regulator.h>
#define PAGE_SIZE 4096
@@ -118,11 +119,12 @@
{
unsigned int timeout;
- timeout = size * 8 * 1000; /* counting in bits and msec */
- timeout *= 2; /* wait twice as long */
+ timeout = size * 8; /* counting in bits */
+ timeout *= 10; /* wait 10 times as long */
timeout /= mmc->clock;
timeout /= mmc->bus_width;
timeout /= mmc->ddr_mode ? 2 : 1;
+ timeout *= 1000; /* counting in msec */
timeout = (timeout < 1000) ? 1000 : timeout;
return timeout;
@@ -493,6 +495,21 @@
if (host->clksel)
host->clksel(host);
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ if (mmc->vqmmc_supply) {
+ int ret;
+
+ if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
+ regulator_set_value(mmc->vqmmc_supply, 1800000);
+ else
+ regulator_set_value(mmc->vqmmc_supply, 3300000);
+
+ ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, true);
+ if (ret)
+ return ret;
+ }
+#endif
+
return 0;
}
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 6a191a1..28d2312 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -17,14 +17,11 @@
#include <hwconfig.h>
#include <mmc.h>
#include <part.h>
-#include <power/regulator.h>
#include <malloc.h>
#include <fsl_esdhc.h>
#include <fdt_support.h>
#include <asm/io.h>
#include <dm.h>
-#include <asm-generic/gpio.h>
-#include <dm/pinctrl.h>
#if !CONFIG_IS_ENABLED(BLK)
#include "mmc_private.h"
@@ -38,7 +35,6 @@
IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
IRQSTATEN_DINT)
-#define MAX_TUNING_LOOP 40
#define ESDHC_DRIVER_STAGE_VALUE 0xffffffff
struct fsl_esdhc {
@@ -60,37 +56,20 @@
uint autoc12err; /* Auto CMD error status register */
uint hostcapblt; /* Host controller capabilities register */
uint wml; /* Watermark level register */
- uint mixctrl; /* For USDHC */
- char reserved1[4]; /* reserved */
+ char reserved1[8]; /* reserved */
uint fevt; /* Force event register */
uint admaes; /* ADMA error status register */
uint adsaddr; /* ADMA system address register */
- char reserved2[4];
- uint dllctrl;
- uint dllstat;
- uint clktunectrlstatus;
- char reserved3[4];
- uint strobe_dllctrl;
- uint strobe_dllstat;
- char reserved4[72];
- uint vendorspec;
- uint mmcboot;
- uint vendorspec2;
- uint tuning_ctrl; /* on i.MX6/7/8 */
- char reserved5[44];
+ char reserved2[160];
uint hostver; /* Host controller version register */
- char reserved6[4]; /* reserved */
+ char reserved3[4]; /* reserved */
uint dmaerraddr; /* DMA error address register */
- char reserved7[4]; /* reserved */
+ char reserved4[4]; /* reserved */
uint dmaerrattr; /* DMA error attribute register */
- char reserved8[4]; /* reserved */
+ char reserved5[4]; /* reserved */
uint hostcapblt2; /* Host controller capabilities register 2 */
- char reserved9[8]; /* reserved */
- uint tcr; /* Tuning control register */
- char reserved10[28]; /* reserved */
- uint sddirctl; /* SD direction control register */
- char reserved11[712];/* reserved */
- uint scr; /* eSDHC control register */
+ char reserved6[756]; /* reserved */
+ uint esdhcctl; /* eSDHC control register */
};
struct fsl_esdhc_plat {
@@ -98,11 +77,6 @@
struct mmc mmc;
};
-struct esdhc_soc_data {
- u32 flags;
- u32 caps;
-};
-
/**
* struct fsl_esdhc_priv
*
@@ -115,13 +89,6 @@
* @dev: pointer for the device
* @non_removable: 0: removable; 1: non-removable
* @wp_enable: 1: enable checking wp; 0: no check
- * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
- * @flags: ESDHC_FLAG_xx in include/fsl_esdhc.h
- * @caps: controller capabilities
- * @tuning_step: tuning step setting in tuning_ctrl register
- * @start_tuning_tap: the start point for tuning in tuning_ctrl register
- * @strobe_dll_delay_target: settings in strobe_dllctrl
- * @signal_voltage: indicating the current voltage
* @cd_gpio: gpio for card detection
* @wp_gpio: gpio for write protection
*/
@@ -130,7 +97,6 @@
unsigned int sdhc_clk;
struct clk per_clk;
unsigned int clock;
- unsigned int mode;
unsigned int bus_width;
#if !CONFIG_IS_ENABLED(BLK)
struct mmc *mmc;
@@ -138,21 +104,6 @@
struct udevice *dev;
int non_removable;
int wp_enable;
- int vs18_enable;
- u32 flags;
- u32 caps;
- u32 tuning_step;
- u32 tuning_start_tap;
- u32 strobe_dll_delay_target;
- u32 signal_voltage;
-#if IS_ENABLED(CONFIG_DM_REGULATOR)
- struct udevice *vqmmc_dev;
- struct udevice *vmmc_dev;
-#endif
-#ifdef CONFIG_DM_GPIO
- struct gpio_desc cd_gpio;
- struct gpio_desc wp_gpio;
-#endif
};
/* Return the XFERTYP flags for a given command and data packet */
@@ -264,8 +215,7 @@
{
int timeout;
struct fsl_esdhc *regs = priv->esdhc_regs;
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
- defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+#if defined(CONFIG_FSL_LAYERSCAPE)
dma_addr_t addr;
#endif
uint wml_value;
@@ -278,8 +228,7 @@
esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
- defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+#if defined(CONFIG_FSL_LAYERSCAPE)
addr = virt_to_phys((void *)(data->dest));
if (upper_32_bits(addr))
printf("Error found for upper 32 bits\n");
@@ -303,20 +252,12 @@
printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
return -ETIMEDOUT;
}
- } else {
-#ifdef CONFIG_DM_GPIO
- if (dm_gpio_is_valid(&priv->wp_gpio) && dm_gpio_get_value(&priv->wp_gpio)) {
- printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
- return -ETIMEDOUT;
- }
-#endif
}
esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
wml_value << 16);
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
- defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+#if defined(CONFIG_FSL_LAYERSCAPE)
addr = virt_to_phys((void *)(data->src));
if (upper_32_bits(addr))
printf("Error found for upper 32 bits\n");
@@ -381,8 +322,7 @@
unsigned end = 0;
unsigned size = roundup(ARCH_DMA_MINALIGN,
data->blocks*data->blocksize);
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
- defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+#if defined(CONFIG_FSL_LAYERSCAPE)
dma_addr_t addr;
addr = virt_to_phys((void *)(data->dest));
@@ -397,25 +337,6 @@
invalidate_dcache_range(start, end);
}
-#ifdef CONFIG_MCF5441x
-/*
- * Swaps 32-bit words to little-endian byte order.
- */
-static inline void sd_swap_dma_buff(struct mmc_data *data)
-{
- int i, size = data->blocksize >> 2;
- u32 *buffer = (u32 *)data->dest;
- u32 sw;
-
- while (data->blocks--) {
- for (i = 0; i < size; i++) {
- sw = __sw32(*buffer);
- *buffer++ = sw;
- }
- }
-}
-#endif
-
/*
* Sends a command out on the bus. Takes the mmc pointer,
* a command pointer, and an optional data pointer.
@@ -472,18 +393,7 @@
/* Send the command */
esdhc_write32(®s->cmdarg, cmd->cmdarg);
-#if defined(CONFIG_FSL_USDHC)
- esdhc_write32(®s->mixctrl,
- (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
- | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
- esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
-#else
esdhc_write32(®s->xfertyp, xfertyp);
-#endif
-
- if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
- (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))
- flags = IRQSTAT_BRR;
/* Wait for the command to complete */
start = get_timer(0);
@@ -506,15 +416,6 @@
goto out;
}
- /* Switch voltage to 1.8V if CMD11 succeeded */
- if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
- esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
-
- printf("Run CMD11 1.8V switch\n");
- /* Sleep for 5 ms - max time for card to switch to 1.8V */
- udelay(5000);
- }
-
/* Workaround for ESDHC errata ENGcm03648 */
if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
int timeout = 6000;
@@ -553,12 +454,6 @@
#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
esdhc_pio_read_write(priv, data);
#else
- flags = DATA_COMPLETE;
- if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
- (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) {
- flags = IRQSTAT_BRR;
- }
-
do {
irqstat = esdhc_read32(®s->irqstat);
@@ -571,7 +466,7 @@
err = -ECOMM;
goto out;
}
- } while ((irqstat & flags) != flags);
+ } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
/*
* Need invalidate the dcache here again to avoid any
@@ -580,9 +475,6 @@
*/
if (data->flags & MMC_DATA_READ) {
check_and_invalidate_dcache_range(cmd, data);
-#ifdef CONFIG_MCF5441x
- sd_swap_dma_buff(data);
-#endif
}
#endif
}
@@ -602,10 +494,6 @@
while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
;
}
-
- /* If this was CMD11, then notify that power cycle is needed */
- if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
- printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
}
esdhc_write32(®s->irqstat, -1);
@@ -617,18 +505,11 @@
{
struct fsl_esdhc *regs = priv->esdhc_regs;
int div = 1;
-#ifdef ARCH_MXC
-#ifdef CONFIG_MX53
- /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
- int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
-#else
- int pre_div = 1;
-#endif
-#else
int pre_div = 2;
-#endif
int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
- int sdhc_clk = priv->sdhc_clk;
+ unsigned int sdhc_clk = priv->sdhc_clk;
+ u32 time_out;
+ u32 value;
uint clk;
if (clock < mmc->cfg->f_min)
@@ -645,23 +526,22 @@
clk = (pre_div << 8) | (div << 4);
-#ifdef CONFIG_FSL_USDHC
- esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
-#else
esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
-#endif
esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
- udelay(10000);
+ time_out = 20;
+ value = PRSSTAT_SDSTB;
+ while (!(esdhc_read32(®s->prsstat) & value)) {
+ if (time_out == 0) {
+ printf("fsl_esdhc: Internal clock never stabilised.\n");
+ break;
+ }
+ time_out--;
+ mdelay(1);
+ }
-#ifdef CONFIG_FSL_USDHC
- esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
-#else
esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
-#endif
-
- priv->clock = clock;
}
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
@@ -693,317 +573,20 @@
}
#endif
-#ifdef MMC_SUPPORTS_TUNING
-static int esdhc_change_pinstate(struct udevice *dev)
-{
- struct fsl_esdhc_priv *priv = dev_get_priv(dev);
- int ret;
-
- switch (priv->mode) {
- case UHS_SDR50:
- case UHS_DDR50:
- ret = pinctrl_select_state(dev, "state_100mhz");
- break;
- case UHS_SDR104:
- case MMC_HS_200:
- case MMC_HS_400:
- ret = pinctrl_select_state(dev, "state_200mhz");
- break;
- default:
- ret = pinctrl_select_state(dev, "default");
- break;
- }
-
- if (ret)
- printf("%s %d error\n", __func__, priv->mode);
-
- return ret;
-}
-
-static void esdhc_reset_tuning(struct mmc *mmc)
-{
- struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
- struct fsl_esdhc *regs = priv->esdhc_regs;
-
- if (priv->flags & ESDHC_FLAG_USDHC) {
- if (priv->flags & ESDHC_FLAG_STD_TUNING) {
- esdhc_clrbits32(®s->autoc12err,
- MIX_CTRL_SMPCLK_SEL |
- MIX_CTRL_EXE_TUNE);
- }
- }
-}
-
-static void esdhc_set_strobe_dll(struct mmc *mmc)
-{
- struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
- struct fsl_esdhc *regs = priv->esdhc_regs;
- u32 val;
-
- if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
- writel(ESDHC_STROBE_DLL_CTRL_RESET, ®s->strobe_dllctrl);
-
- /*
- * enable strobe dll ctrl and adjust the delay target
- * for the uSDHC loopback read clock
- */
- val = ESDHC_STROBE_DLL_CTRL_ENABLE |
- (priv->strobe_dll_delay_target <<
- ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
- writel(val, ®s->strobe_dllctrl);
- /* wait 1us to make sure strobe dll status register stable */
- mdelay(1);
- val = readl(®s->strobe_dllstat);
- if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK))
- pr_warn("HS400 strobe DLL status REF not lock!\n");
- if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
- pr_warn("HS400 strobe DLL status SLV not lock!\n");
- }
-}
-
-static int esdhc_set_timing(struct mmc *mmc)
-{
- struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
- struct fsl_esdhc *regs = priv->esdhc_regs;
- u32 mixctrl;
-
- mixctrl = readl(®s->mixctrl);
- mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN);
-
- switch (mmc->selected_mode) {
- case MMC_LEGACY:
- case SD_LEGACY:
- esdhc_reset_tuning(mmc);
- writel(mixctrl, ®s->mixctrl);
- break;
- case MMC_HS_400:
- mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN;
- writel(mixctrl, ®s->mixctrl);
- esdhc_set_strobe_dll(mmc);
- break;
- case MMC_HS:
- case MMC_HS_52:
- case MMC_HS_200:
- case SD_HS:
- case UHS_SDR12:
- case UHS_SDR25:
- case UHS_SDR50:
- case UHS_SDR104:
- writel(mixctrl, ®s->mixctrl);
- break;
- case UHS_DDR50:
- case MMC_DDR_52:
- mixctrl |= MIX_CTRL_DDREN;
- writel(mixctrl, ®s->mixctrl);
- break;
- default:
- printf("Not supported %d\n", mmc->selected_mode);
- return -EINVAL;
- }
-
- priv->mode = mmc->selected_mode;
-
- return esdhc_change_pinstate(mmc->dev);
-}
-
-static int esdhc_set_voltage(struct mmc *mmc)
-{
- struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
- struct fsl_esdhc *regs = priv->esdhc_regs;
- int ret;
-
- priv->signal_voltage = mmc->signal_voltage;
- switch (mmc->signal_voltage) {
- case MMC_SIGNAL_VOLTAGE_330:
- if (priv->vs18_enable)
- return -EIO;
-#if CONFIG_IS_ENABLED(DM_REGULATOR)
- if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
- ret = regulator_set_value(priv->vqmmc_dev, 3300000);
- if (ret) {
- printf("Setting to 3.3V error");
- return -EIO;
- }
- /* Wait for 5ms */
- mdelay(5);
- }
-#endif
-
- esdhc_clrbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
- if (!(esdhc_read32(®s->vendorspec) &
- ESDHC_VENDORSPEC_VSELECT))
- return 0;
-
- return -EAGAIN;
- case MMC_SIGNAL_VOLTAGE_180:
-#if CONFIG_IS_ENABLED(DM_REGULATOR)
- if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
- ret = regulator_set_value(priv->vqmmc_dev, 1800000);
- if (ret) {
- printf("Setting to 1.8V error");
- return -EIO;
- }
- }
-#endif
- esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
- if (esdhc_read32(®s->vendorspec) & ESDHC_VENDORSPEC_VSELECT)
- return 0;
-
- return -EAGAIN;
- case MMC_SIGNAL_VOLTAGE_120:
- return -ENOTSUPP;
- default:
- return 0;
- }
-}
-
-static void esdhc_stop_tuning(struct mmc *mmc)
-{
- struct mmc_cmd cmd;
-
- cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
- cmd.cmdarg = 0;
- cmd.resp_type = MMC_RSP_R1b;
-
- dm_mmc_send_cmd(mmc->dev, &cmd, NULL);
-}
-
-static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
-{
- struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
- struct fsl_esdhc_priv *priv = dev_get_priv(dev);
- struct fsl_esdhc *regs = priv->esdhc_regs;
- struct mmc *mmc = &plat->mmc;
- u32 irqstaten = readl(®s->irqstaten);
- u32 irqsigen = readl(®s->irqsigen);
- int i, ret = -ETIMEDOUT;
- u32 val, mixctrl;
-
- /* clock tuning is not needed for upto 52MHz */
- if (mmc->clock <= 52000000)
- return 0;
-
- /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
- if (priv->flags & ESDHC_FLAG_STD_TUNING) {
- val = readl(®s->autoc12err);
- mixctrl = readl(®s->mixctrl);
- val &= ~MIX_CTRL_SMPCLK_SEL;
- mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN);
-
- val |= MIX_CTRL_EXE_TUNE;
- mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN;
-
- writel(val, ®s->autoc12err);
- writel(mixctrl, ®s->mixctrl);
- }
-
- /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */
- mixctrl = readl(®s->mixctrl);
- mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK);
- writel(mixctrl, ®s->mixctrl);
-
- writel(IRQSTATEN_BRR, ®s->irqstaten);
- writel(IRQSTATEN_BRR, ®s->irqsigen);
-
- /*
- * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
- * of loops reaches 40 times.
- */
- for (i = 0; i < MAX_TUNING_LOOP; i++) {
- u32 ctrl;
-
- if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
- if (mmc->bus_width == 8)
- writel(0x7080, ®s->blkattr);
- else if (mmc->bus_width == 4)
- writel(0x7040, ®s->blkattr);
- } else {
- writel(0x7040, ®s->blkattr);
- }
-
- /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */
- val = readl(®s->mixctrl);
- val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK);
- writel(val, ®s->mixctrl);
-
- /* We are using STD tuning, no need to check return value */
- mmc_send_tuning(mmc, opcode, NULL);
-
- ctrl = readl(®s->autoc12err);
- if ((!(ctrl & MIX_CTRL_EXE_TUNE)) &&
- (ctrl & MIX_CTRL_SMPCLK_SEL)) {
- /*
- * need to wait some time, make sure sd/mmc fininsh
- * send out tuning data, otherwise, the sd/mmc can't
- * response to any command when the card still out
- * put the tuning data.
- */
- mdelay(1);
- ret = 0;
- break;
- }
-
- /* Add 1ms delay for SD and eMMC */
- mdelay(1);
- }
-
- writel(irqstaten, ®s->irqstaten);
- writel(irqsigen, ®s->irqsigen);
-
- esdhc_stop_tuning(mmc);
-
- return ret;
-}
-#endif
-
static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
{
struct fsl_esdhc *regs = priv->esdhc_regs;
- int ret __maybe_unused;
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
/* Select to use peripheral clock */
esdhc_clock_control(priv, false);
- esdhc_setbits32(®s->scr, ESDHCCTL_PCS);
+ esdhc_setbits32(®s->esdhcctl, ESDHCCTL_PCS);
esdhc_clock_control(priv, true);
#endif
/* Set the clock speed */
if (priv->clock != mmc->clock)
set_sysctl(priv, mmc, mmc->clock);
-#ifdef MMC_SUPPORTS_TUNING
- if (mmc->clk_disable) {
-#ifdef CONFIG_FSL_USDHC
- esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
-#else
- esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
-#endif
- } else {
-#ifdef CONFIG_FSL_USDHC
- esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
- VENDORSPEC_CKEN);
-#else
- esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
-#endif
- }
-
- if (priv->mode != mmc->selected_mode) {
- ret = esdhc_set_timing(mmc);
- if (ret) {
- printf("esdhc_set_timing error %d\n", ret);
- return ret;
- }
- }
-
- if (priv->signal_voltage != mmc->signal_voltage) {
- ret = esdhc_set_voltage(mmc);
- if (ret) {
- printf("esdhc_set_voltage error %d\n", ret);
- return ret;
- }
- }
-#endif
-
/* Set the bus width */
esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
@@ -1030,34 +613,10 @@
return -ETIMEDOUT;
}
-#if defined(CONFIG_FSL_USDHC)
- /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
- esdhc_write32(®s->mmcboot, 0x0);
- /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
- esdhc_write32(®s->mixctrl, 0x0);
- esdhc_write32(®s->clktunectrlstatus, 0x0);
-
- /* Put VEND_SPEC to default value */
- if (priv->vs18_enable)
- esdhc_write32(®s->vendorspec, (VENDORSPEC_INIT |
- ESDHC_VENDORSPEC_VSELECT));
- else
- esdhc_write32(®s->vendorspec, VENDORSPEC_INIT);
-
- /* Disable DLL_CTRL delay line */
- esdhc_write32(®s->dllctrl, 0x0);
-#endif
-
-#ifndef ARCH_MXC
/* Enable cache snooping */
- esdhc_write32(®s->scr, 0x00000040);
-#endif
+ esdhc_write32(®s->esdhcctl, 0x00000040);
-#ifndef CONFIG_FSL_USDHC
esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
-#else
- esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
-#endif
/* Set the initial clock speed */
mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
@@ -1065,12 +624,8 @@
/* Disable the BRR and BWR bits in IRQSTAT */
esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
-#ifdef CONFIG_MCF5441x
- esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD);
-#else
/* Put the PROCTL reg back to the default */
esdhc_write32(®s->proctl, PROCTL_INIT);
-#endif
/* Set timout to the maximum value */
esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
@@ -1091,10 +646,6 @@
#if CONFIG_IS_ENABLED(DM_MMC)
if (priv->non_removable)
return 1;
-#ifdef CONFIG_DM_GPIO
- if (dm_gpio_is_valid(&priv->cd_gpio))
- return dm_gpio_get_value(&priv->cd_gpio);
-#endif
#endif
while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
@@ -1178,25 +729,8 @@
if (ret)
return ret;
-#ifdef CONFIG_MCF5441x
- /* ColdFire, using SDHC_DATA[3] for card detection */
- esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD);
-#endif
-
-#ifndef CONFIG_FSL_USDHC
- esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
- | SYSCTL_IPGEN | SYSCTL_CKEN);
- /* Clearing tuning bits in case ROM has set it already */
- esdhc_write32(®s->mixctrl, 0);
- esdhc_write32(®s->autoc12err, 0);
- esdhc_write32(®s->clktunectrlstatus, 0);
-#else
- esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
- VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
-#endif
-
- if (priv->vs18_enable)
- esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
+ esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN |
+ SYSCTL_IPGEN | SYSCTL_CKEN);
writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
cfg = &plat->cfg;
@@ -1207,15 +741,6 @@
voltage_caps = 0;
caps = esdhc_read32(®s->hostcapblt);
-#ifdef CONFIG_MCF5441x
- /*
- * MCF5441x RM declares in more points that sdhc clock speed must
- * never exceed 25 Mhz. From this, the HS bit needs to be disabled
- * from host capabilities.
- */
- caps &= ~ESDHC_HOSTCAPBLT_HSS;
-#endif
-
#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
@@ -1272,27 +797,11 @@
cfg->host_caps &= ~MMC_MODE_8BIT;
#endif
- cfg->host_caps |= priv->caps;
-
cfg->f_min = 400000;
cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
- writel(0, ®s->dllctrl);
- if (priv->flags & ESDHC_FLAG_USDHC) {
- if (priv->flags & ESDHC_FLAG_STD_TUNING) {
- u32 val = readl(®s->tuning_ctrl);
-
- val |= ESDHC_STD_TUNING_EN;
- val &= ~ESDHC_TUNING_START_TAP_MASK;
- val |= priv->tuning_start_tap;
- val &= ~ESDHC_TUNING_STEP_MASK;
- val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;
- writel(val, ®s->tuning_ctrl);
- }
- }
-
return 0;
}
@@ -1307,7 +816,6 @@
priv->bus_width = cfg->max_bus_width;
priv->sdhc_clk = cfg->sdhc_clk;
priv->wp_enable = cfg->wp_enable;
- priv->vs18_enable = cfg->vs18_enable;
return 0;
};
@@ -1444,22 +952,11 @@
#ifndef CONFIG_PPC
#include <asm/arch/clock.h>
#endif
-__weak void init_clk_usdhc(u32 index)
-{
-}
-
static int fsl_esdhc_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
- const void *fdt = gd->fdt_blob;
- int node = dev_of_offset(dev);
- struct esdhc_soc_data *data =
- (struct esdhc_soc_data *)dev_get_driver_data(dev);
-#if CONFIG_IS_ENABLED(DM_REGULATOR)
- struct udevice *vqmmc_dev;
-#endif
fdt_addr_t addr;
unsigned int val;
struct mmc *mmc;
@@ -1477,11 +974,6 @@
priv->esdhc_regs = (struct fsl_esdhc *)addr;
#endif
priv->dev = dev;
- priv->mode = -1;
- if (data) {
- priv->flags = data->flags;
- priv->caps = data->caps;
- }
val = dev_read_u32_default(dev, "bus-width", -1);
if (val == 8)
@@ -1491,81 +983,13 @@
else
priv->bus_width = 1;
- val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1);
- priv->tuning_step = val;
- val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap",
- ESDHC_TUNING_START_TAP_DEFAULT);
- priv->tuning_start_tap = val;
- val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target",
- ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
- priv->strobe_dll_delay_target = val;
-
if (dev_read_bool(dev, "non-removable")) {
priv->non_removable = 1;
} else {
priv->non_removable = 0;
-#ifdef CONFIG_DM_GPIO
- gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
- GPIOD_IS_IN);
-#endif
}
- if (dev_read_prop(dev, "fsl,wp-controller", NULL)) {
- priv->wp_enable = 1;
- } else {
- priv->wp_enable = 0;
-#ifdef CONFIG_DM_GPIO
- gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
- GPIOD_IS_IN);
-#endif
- }
-
- priv->vs18_enable = 0;
-
-#if CONFIG_IS_ENABLED(DM_REGULATOR)
- /*
- * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
- * otherwise, emmc will work abnormally.
- */
- ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
- if (ret) {
- dev_dbg(dev, "no vqmmc-supply\n");
- } else {
- ret = regulator_set_enable(vqmmc_dev, true);
- if (ret) {
- dev_err(dev, "fail to enable vqmmc-supply\n");
- return ret;
- }
-
- if (regulator_get_value(vqmmc_dev) == 1800000)
- priv->vs18_enable = 1;
- }
-#endif
-
- if (fdt_get_property(fdt, node, "no-1-8-v", NULL))
- priv->caps &= ~(UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_HS400);
-
- /*
- * TODO:
- * Because lack of clk driver, if SDHC clk is not enabled,
- * need to enable it first before this driver is invoked.
- *
- * we use MXC_ESDHC_CLK to get clk freq.
- * If one would like to make this function work,
- * the aliases should be provided in dts as this:
- *
- * aliases {
- * mmc0 = &usdhc1;
- * mmc1 = &usdhc2;
- * mmc2 = &usdhc3;
- * mmc3 = &usdhc4;
- * };
- * Then if your board only supports mmc2 and mmc3, but we can
- * correctly get the seq as 2 and 3, then let mxc_get_clock
- * work as expected.
- */
-
- init_clk_usdhc(dev->seq);
+ priv->wp_enable = 1;
if (IS_ENABLED(CONFIG_CLK)) {
/* Assigned clock already set clock */
@@ -1599,6 +1023,8 @@
return ret;
}
+ mmc_of_parse(dev, &plat->cfg);
+
mmc = &plat->mmc;
mmc->cfg = &plat->cfg;
mmc->dev = dev;
@@ -1657,27 +1083,12 @@
.send_cmd = fsl_esdhc_send_cmd,
.set_ios = fsl_esdhc_set_ios,
#ifdef MMC_SUPPORTS_TUNING
- .execute_tuning = fsl_esdhc_execute_tuning,
+ .execute_tuning = fsl_esdhc_execute_tuning,
#endif
};
#endif
-static struct esdhc_soc_data usdhc_imx7d_data = {
- .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
- | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
- | ESDHC_FLAG_HS400,
- .caps = UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_DDR_52MHz |
- MMC_MODE_HS_52MHz | MMC_MODE_HS,
-};
-
static const struct udevice_id fsl_esdhc_ids[] = {
- { .compatible = "fsl,imx53-esdhc", },
- { .compatible = "fsl,imx6ul-usdhc", },
- { .compatible = "fsl,imx6sx-usdhc", },
- { .compatible = "fsl,imx6sl-usdhc", },
- { .compatible = "fsl,imx6q-usdhc", },
- { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,},
- { .compatible = "fsl,imx7ulp-usdhc", },
{ .compatible = "fsl,esdhc", },
{ /* sentinel */ }
};
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
new file mode 100644
index 0000000..43106de
--- /dev/null
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -0,0 +1,1673 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
+ * Copyright 2019 NXP Semiconductors
+ * Andy Fleming
+ * Yangbo Lu <yangbo.lu@nxp.com>
+ *
+ * Based vaguely on the pxa mmc code:
+ * (C) Copyright 2003
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <clk.h>
+#include <errno.h>
+#include <hwconfig.h>
+#include <mmc.h>
+#include <part.h>
+#include <power/regulator.h>
+#include <malloc.h>
+#include <fsl_esdhc_imx.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <asm-generic/gpio.h>
+#include <dm/pinctrl.h>
+
+#if !CONFIG_IS_ENABLED(BLK)
+#include "mmc_private.h"
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
+ IRQSTATEN_CINT | \
+ IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
+ IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
+ IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
+ IRQSTATEN_DINT)
+#define MAX_TUNING_LOOP 40
+#define ESDHC_DRIVER_STAGE_VALUE 0xffffffff
+
+struct fsl_esdhc {
+ uint dsaddr; /* SDMA system address register */
+ uint blkattr; /* Block attributes register */
+ uint cmdarg; /* Command argument register */
+ uint xfertyp; /* Transfer type register */
+ uint cmdrsp0; /* Command response 0 register */
+ uint cmdrsp1; /* Command response 1 register */
+ uint cmdrsp2; /* Command response 2 register */
+ uint cmdrsp3; /* Command response 3 register */
+ uint datport; /* Buffer data port register */
+ uint prsstat; /* Present state register */
+ uint proctl; /* Protocol control register */
+ uint sysctl; /* System Control Register */
+ uint irqstat; /* Interrupt status register */
+ uint irqstaten; /* Interrupt status enable register */
+ uint irqsigen; /* Interrupt signal enable register */
+ uint autoc12err; /* Auto CMD error status register */
+ uint hostcapblt; /* Host controller capabilities register */
+ uint wml; /* Watermark level register */
+ uint mixctrl; /* For USDHC */
+ char reserved1[4]; /* reserved */
+ uint fevt; /* Force event register */
+ uint admaes; /* ADMA error status register */
+ uint adsaddr; /* ADMA system address register */
+ char reserved2[4];
+ uint dllctrl;
+ uint dllstat;
+ uint clktunectrlstatus;
+ char reserved3[4];
+ uint strobe_dllctrl;
+ uint strobe_dllstat;
+ char reserved4[72];
+ uint vendorspec;
+ uint mmcboot;
+ uint vendorspec2;
+ uint tuning_ctrl; /* on i.MX6/7/8 */
+ char reserved5[44];
+ uint hostver; /* Host controller version register */
+ char reserved6[4]; /* reserved */
+ uint dmaerraddr; /* DMA error address register */
+ char reserved7[4]; /* reserved */
+ uint dmaerrattr; /* DMA error attribute register */
+ char reserved8[4]; /* reserved */
+ uint hostcapblt2; /* Host controller capabilities register 2 */
+ char reserved9[8]; /* reserved */
+ uint tcr; /* Tuning control register */
+ char reserved10[28]; /* reserved */
+ uint sddirctl; /* SD direction control register */
+ char reserved11[712];/* reserved */
+ uint scr; /* eSDHC control register */
+};
+
+struct fsl_esdhc_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
+struct esdhc_soc_data {
+ u32 flags;
+};
+
+/**
+ * struct fsl_esdhc_priv
+ *
+ * @esdhc_regs: registers of the sdhc controller
+ * @sdhc_clk: Current clk of the sdhc controller
+ * @bus_width: bus width, 1bit, 4bit or 8bit
+ * @cfg: mmc config
+ * @mmc: mmc
+ * Following is used when Driver Model is enabled for MMC
+ * @dev: pointer for the device
+ * @non_removable: 0: removable; 1: non-removable
+ * @wp_enable: 1: enable checking wp; 0: no check
+ * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
+ * @flags: ESDHC_FLAG_xx in include/fsl_esdhc_imx.h
+ * @caps: controller capabilities
+ * @tuning_step: tuning step setting in tuning_ctrl register
+ * @start_tuning_tap: the start point for tuning in tuning_ctrl register
+ * @strobe_dll_delay_target: settings in strobe_dllctrl
+ * @signal_voltage: indicating the current voltage
+ * @cd_gpio: gpio for card detection
+ * @wp_gpio: gpio for write protection
+ */
+struct fsl_esdhc_priv {
+ struct fsl_esdhc *esdhc_regs;
+ unsigned int sdhc_clk;
+ struct clk per_clk;
+ unsigned int clock;
+ unsigned int mode;
+ unsigned int bus_width;
+#if !CONFIG_IS_ENABLED(BLK)
+ struct mmc *mmc;
+#endif
+ struct udevice *dev;
+ int non_removable;
+ int wp_enable;
+ int vs18_enable;
+ u32 flags;
+ u32 caps;
+ u32 tuning_step;
+ u32 tuning_start_tap;
+ u32 strobe_dll_delay_target;
+ u32 signal_voltage;
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ struct udevice *vqmmc_dev;
+ struct udevice *vmmc_dev;
+#endif
+#ifdef CONFIG_DM_GPIO
+ struct gpio_desc cd_gpio;
+ struct gpio_desc wp_gpio;
+#endif
+};
+
+/* Return the XFERTYP flags for a given command and data packet */
+static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
+{
+ uint xfertyp = 0;
+
+ if (data) {
+ xfertyp |= XFERTYP_DPSEL;
+#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
+ xfertyp |= XFERTYP_DMAEN;
+#endif
+ if (data->blocks > 1) {
+ xfertyp |= XFERTYP_MSBSEL;
+ xfertyp |= XFERTYP_BCEN;
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
+ xfertyp |= XFERTYP_AC12EN;
+#endif
+ }
+
+ if (data->flags & MMC_DATA_READ)
+ xfertyp |= XFERTYP_DTDSEL;
+ }
+
+ if (cmd->resp_type & MMC_RSP_CRC)
+ xfertyp |= XFERTYP_CCCEN;
+ if (cmd->resp_type & MMC_RSP_OPCODE)
+ xfertyp |= XFERTYP_CICEN;
+ if (cmd->resp_type & MMC_RSP_136)
+ xfertyp |= XFERTYP_RSPTYP_136;
+ else if (cmd->resp_type & MMC_RSP_BUSY)
+ xfertyp |= XFERTYP_RSPTYP_48_BUSY;
+ else if (cmd->resp_type & MMC_RSP_PRESENT)
+ xfertyp |= XFERTYP_RSPTYP_48;
+
+ if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
+ xfertyp |= XFERTYP_CMDTYP_ABORT;
+
+ return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
+}
+
+#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
+/*
+ * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
+ */
+static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
+ struct mmc_data *data)
+{
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+ uint blocks;
+ char *buffer;
+ uint databuf;
+ uint size;
+ uint irqstat;
+ ulong start;
+
+ if (data->flags & MMC_DATA_READ) {
+ blocks = data->blocks;
+ buffer = data->dest;
+ while (blocks) {
+ start = get_timer(0);
+ size = data->blocksize;
+ irqstat = esdhc_read32(®s->irqstat);
+ while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)) {
+ if (get_timer(start) > PIO_TIMEOUT) {
+ printf("\nData Read Failed in PIO Mode.");
+ return;
+ }
+ }
+ while (size && (!(irqstat & IRQSTAT_TC))) {
+ udelay(100); /* Wait before last byte transfer complete */
+ irqstat = esdhc_read32(®s->irqstat);
+ databuf = in_le32(®s->datport);
+ *((uint *)buffer) = databuf;
+ buffer += 4;
+ size -= 4;
+ }
+ blocks--;
+ }
+ } else {
+ blocks = data->blocks;
+ buffer = (char *)data->src;
+ while (blocks) {
+ start = get_timer(0);
+ size = data->blocksize;
+ irqstat = esdhc_read32(®s->irqstat);
+ while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)) {
+ if (get_timer(start) > PIO_TIMEOUT) {
+ printf("\nData Write Failed in PIO Mode.");
+ return;
+ }
+ }
+ while (size && (!(irqstat & IRQSTAT_TC))) {
+ udelay(100); /* Wait before last byte transfer complete */
+ databuf = *((uint *)buffer);
+ buffer += 4;
+ size -= 4;
+ irqstat = esdhc_read32(®s->irqstat);
+ out_le32(®s->datport, databuf);
+ }
+ blocks--;
+ }
+ }
+}
+#endif
+
+static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
+ struct mmc_data *data)
+{
+ int timeout;
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+ dma_addr_t addr;
+#endif
+ uint wml_value;
+
+ wml_value = data->blocksize/4;
+
+ if (data->flags & MMC_DATA_READ) {
+ if (wml_value > WML_RD_WML_MAX)
+ wml_value = WML_RD_WML_MAX_VAL;
+
+ esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
+#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
+#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+ addr = virt_to_phys((void *)(data->dest));
+ if (upper_32_bits(addr))
+ printf("Error found for upper 32 bits\n");
+ else
+ esdhc_write32(®s->dsaddr, lower_32_bits(addr));
+#else
+ esdhc_write32(®s->dsaddr, (u32)data->dest);
+#endif
+#endif
+ } else {
+#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
+ flush_dcache_range((ulong)data->src,
+ (ulong)data->src+data->blocks
+ *data->blocksize);
+#endif
+ if (wml_value > WML_WR_WML_MAX)
+ wml_value = WML_WR_WML_MAX_VAL;
+ if (priv->wp_enable) {
+ if ((esdhc_read32(®s->prsstat) &
+ PRSSTAT_WPSPL) == 0) {
+ printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
+ return -ETIMEDOUT;
+ }
+ } else {
+#ifdef CONFIG_DM_GPIO
+ if (dm_gpio_is_valid(&priv->wp_gpio) && dm_gpio_get_value(&priv->wp_gpio)) {
+ printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
+ return -ETIMEDOUT;
+ }
+#endif
+ }
+
+ esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
+ wml_value << 16);
+#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
+#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+ addr = virt_to_phys((void *)(data->src));
+ if (upper_32_bits(addr))
+ printf("Error found for upper 32 bits\n");
+ else
+ esdhc_write32(®s->dsaddr, lower_32_bits(addr));
+#else
+ esdhc_write32(®s->dsaddr, (u32)data->src);
+#endif
+#endif
+ }
+
+ esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
+
+ /* Calculate the timeout period for data transactions */
+ /*
+ * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
+ * 2)Timeout period should be minimum 0.250sec as per SD Card spec
+ * So, Number of SD Clock cycles for 0.25sec should be minimum
+ * (SD Clock/sec * 0.25 sec) SD Clock cycles
+ * = (mmc->clock * 1/4) SD Clock cycles
+ * As 1) >= 2)
+ * => (2^(timeout+13)) >= mmc->clock * 1/4
+ * Taking log2 both the sides
+ * => timeout + 13 >= log2(mmc->clock/4)
+ * Rounding up to next power of 2
+ * => timeout + 13 = log2(mmc->clock/4) + 1
+ * => timeout + 13 = fls(mmc->clock/4)
+ *
+ * However, the MMC spec "It is strongly recommended for hosts to
+ * implement more than 500ms timeout value even if the card
+ * indicates the 250ms maximum busy length." Even the previous
+ * value of 300ms is known to be insufficient for some cards.
+ * So, we use
+ * => timeout + 13 = fls(mmc->clock/2)
+ */
+ timeout = fls(mmc->clock/2);
+ timeout -= 13;
+
+ if (timeout > 14)
+ timeout = 14;
+
+ if (timeout < 0)
+ timeout = 0;
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
+ if ((timeout == 4) || (timeout == 8) || (timeout == 12))
+ timeout++;
+#endif
+
+#ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
+ timeout = 0xE;
+#endif
+ esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
+
+ return 0;
+}
+
+static void check_and_invalidate_dcache_range
+ (struct mmc_cmd *cmd,
+ struct mmc_data *data) {
+ unsigned start = 0;
+ unsigned end = 0;
+ unsigned size = roundup(ARCH_DMA_MINALIGN,
+ data->blocks*data->blocksize);
+#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+ dma_addr_t addr;
+
+ addr = virt_to_phys((void *)(data->dest));
+ if (upper_32_bits(addr))
+ printf("Error found for upper 32 bits\n");
+ else
+ start = lower_32_bits(addr);
+#else
+ start = (unsigned)data->dest;
+#endif
+ end = start + size;
+ invalidate_dcache_range(start, end);
+}
+
+#ifdef CONFIG_MCF5441x
+/*
+ * Swaps 32-bit words to little-endian byte order.
+ */
+static inline void sd_swap_dma_buff(struct mmc_data *data)
+{
+ int i, size = data->blocksize >> 2;
+ u32 *buffer = (u32 *)data->dest;
+ u32 sw;
+
+ while (data->blocks--) {
+ for (i = 0; i < size; i++) {
+ sw = __sw32(*buffer);
+ *buffer++ = sw;
+ }
+ }
+}
+#endif
+
+/*
+ * Sends a command out on the bus. Takes the mmc pointer,
+ * a command pointer, and an optional data pointer.
+ */
+static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
+ struct mmc_cmd *cmd, struct mmc_data *data)
+{
+ int err = 0;
+ uint xfertyp;
+ uint irqstat;
+ u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+ unsigned long start;
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
+ if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
+ return 0;
+#endif
+
+ esdhc_write32(®s->irqstat, -1);
+
+ sync();
+
+ /* Wait for the bus to be idle */
+ while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
+ (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
+ ;
+
+ while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
+ ;
+
+ /* Wait at least 8 SD clock cycles before the next command */
+ /*
+ * Note: This is way more than 8 cycles, but 1ms seems to
+ * resolve timing issues with some cards
+ */
+ udelay(1000);
+
+ /* Set up for a data transfer if we have one */
+ if (data) {
+ err = esdhc_setup_data(priv, mmc, data);
+ if(err)
+ return err;
+
+ if (data->flags & MMC_DATA_READ)
+ check_and_invalidate_dcache_range(cmd, data);
+ }
+
+ /* Figure out the transfer arguments */
+ xfertyp = esdhc_xfertyp(cmd, data);
+
+ /* Mask all irqs */
+ esdhc_write32(®s->irqsigen, 0);
+
+ /* Send the command */
+ esdhc_write32(®s->cmdarg, cmd->cmdarg);
+#if defined(CONFIG_FSL_USDHC)
+ esdhc_write32(®s->mixctrl,
+ (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
+ | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
+ esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
+#else
+ esdhc_write32(®s->xfertyp, xfertyp);
+#endif
+
+ if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
+ (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))
+ flags = IRQSTAT_BRR;
+
+ /* Wait for the command to complete */
+ start = get_timer(0);
+ while (!(esdhc_read32(®s->irqstat) & flags)) {
+ if (get_timer(start) > 1000) {
+ err = -ETIMEDOUT;
+ goto out;
+ }
+ }
+
+ irqstat = esdhc_read32(®s->irqstat);
+
+ if (irqstat & CMD_ERR) {
+ err = -ECOMM;
+ goto out;
+ }
+
+ if (irqstat & IRQSTAT_CTOE) {
+ err = -ETIMEDOUT;
+ goto out;
+ }
+
+ /* Switch voltage to 1.8V if CMD11 succeeded */
+ if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
+ esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
+
+ printf("Run CMD11 1.8V switch\n");
+ /* Sleep for 5 ms - max time for card to switch to 1.8V */
+ udelay(5000);
+ }
+
+ /* Workaround for ESDHC errata ENGcm03648 */
+ if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
+ int timeout = 50000;
+
+ /* Poll on DATA0 line for cmd with busy signal for 5000 ms */
+ while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
+ PRSSTAT_DAT0)) {
+ udelay(100);
+ timeout--;
+ }
+
+ if (timeout <= 0) {
+ printf("Timeout waiting for DAT0 to go high!\n");
+ err = -ETIMEDOUT;
+ goto out;
+ }
+ }
+
+ /* Copy the response to the response buffer */
+ if (cmd->resp_type & MMC_RSP_136) {
+ u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
+
+ cmdrsp3 = esdhc_read32(®s->cmdrsp3);
+ cmdrsp2 = esdhc_read32(®s->cmdrsp2);
+ cmdrsp1 = esdhc_read32(®s->cmdrsp1);
+ cmdrsp0 = esdhc_read32(®s->cmdrsp0);
+ cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
+ cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
+ cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
+ cmd->response[3] = (cmdrsp0 << 8);
+ } else
+ cmd->response[0] = esdhc_read32(®s->cmdrsp0);
+
+ /* Wait until all of the blocks are transferred */
+ if (data) {
+#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
+ esdhc_pio_read_write(priv, data);
+#else
+ flags = DATA_COMPLETE;
+ if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
+ (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) {
+ flags = IRQSTAT_BRR;
+ }
+
+ do {
+ irqstat = esdhc_read32(®s->irqstat);
+
+ if (irqstat & IRQSTAT_DTOE) {
+ err = -ETIMEDOUT;
+ goto out;
+ }
+
+ if (irqstat & DATA_ERR) {
+ err = -ECOMM;
+ goto out;
+ }
+ } while ((irqstat & flags) != flags);
+
+ /*
+ * Need invalidate the dcache here again to avoid any
+ * cache-fill during the DMA operations such as the
+ * speculative pre-fetching etc.
+ */
+ if (data->flags & MMC_DATA_READ) {
+ check_and_invalidate_dcache_range(cmd, data);
+#ifdef CONFIG_MCF5441x
+ sd_swap_dma_buff(data);
+#endif
+ }
+#endif
+ }
+
+out:
+ /* Reset CMD and DATA portions on error */
+ if (err) {
+ esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
+ SYSCTL_RSTC);
+ while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
+ ;
+
+ if (data) {
+ esdhc_write32(®s->sysctl,
+ esdhc_read32(®s->sysctl) |
+ SYSCTL_RSTD);
+ while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
+ ;
+ }
+
+ /* If this was CMD11, then notify that power cycle is needed */
+ if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
+ printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
+ }
+
+ esdhc_write32(®s->irqstat, -1);
+
+ return err;
+}
+
+static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
+{
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+ int div = 1;
+#ifdef ARCH_MXC
+#ifdef CONFIG_MX53
+ /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
+ int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
+#else
+ int pre_div = 1;
+#endif
+#else
+ int pre_div = 2;
+#endif
+ int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
+ int sdhc_clk = priv->sdhc_clk;
+ uint clk;
+
+ if (clock < mmc->cfg->f_min)
+ clock = mmc->cfg->f_min;
+
+ while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
+ pre_div *= 2;
+
+ while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
+ div++;
+
+ pre_div >>= 1;
+ div -= 1;
+
+ clk = (pre_div << 8) | (div << 4);
+
+#ifdef CONFIG_FSL_USDHC
+ esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
+#else
+ esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
+#endif
+
+ esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
+
+ udelay(10000);
+
+#ifdef CONFIG_FSL_USDHC
+ esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
+#else
+ esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
+#endif
+
+ priv->clock = clock;
+}
+
+#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
+static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
+{
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+ u32 value;
+ u32 time_out;
+
+ value = esdhc_read32(®s->sysctl);
+
+ if (enable)
+ value |= SYSCTL_CKEN;
+ else
+ value &= ~SYSCTL_CKEN;
+
+ esdhc_write32(®s->sysctl, value);
+
+ time_out = 20;
+ value = PRSSTAT_SDSTB;
+ while (!(esdhc_read32(®s->prsstat) & value)) {
+ if (time_out == 0) {
+ printf("fsl_esdhc: Internal clock never stabilised.\n");
+ break;
+ }
+ time_out--;
+ mdelay(1);
+ }
+}
+#endif
+
+#ifdef MMC_SUPPORTS_TUNING
+static int esdhc_change_pinstate(struct udevice *dev)
+{
+ struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ switch (priv->mode) {
+ case UHS_SDR50:
+ case UHS_DDR50:
+ ret = pinctrl_select_state(dev, "state_100mhz");
+ break;
+ case UHS_SDR104:
+ case MMC_HS_200:
+ case MMC_HS_400:
+ case MMC_HS_400_ES:
+ ret = pinctrl_select_state(dev, "state_200mhz");
+ break;
+ default:
+ ret = pinctrl_select_state(dev, "default");
+ break;
+ }
+
+ if (ret)
+ printf("%s %d error\n", __func__, priv->mode);
+
+ return ret;
+}
+
+static void esdhc_reset_tuning(struct mmc *mmc)
+{
+ struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+
+ if (priv->flags & ESDHC_FLAG_USDHC) {
+ if (priv->flags & ESDHC_FLAG_STD_TUNING) {
+ esdhc_clrbits32(®s->autoc12err,
+ MIX_CTRL_SMPCLK_SEL |
+ MIX_CTRL_EXE_TUNE);
+ }
+ }
+}
+
+static void esdhc_set_strobe_dll(struct mmc *mmc)
+{
+ struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+ u32 val;
+
+ if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
+ writel(ESDHC_STROBE_DLL_CTRL_RESET, ®s->strobe_dllctrl);
+
+ /*
+ * enable strobe dll ctrl and adjust the delay target
+ * for the uSDHC loopback read clock
+ */
+ val = ESDHC_STROBE_DLL_CTRL_ENABLE |
+ (priv->strobe_dll_delay_target <<
+ ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
+ writel(val, ®s->strobe_dllctrl);
+ /* wait 1us to make sure strobe dll status register stable */
+ mdelay(1);
+ val = readl(®s->strobe_dllstat);
+ if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK))
+ pr_warn("HS400 strobe DLL status REF not lock!\n");
+ if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
+ pr_warn("HS400 strobe DLL status SLV not lock!\n");
+ }
+}
+
+static int esdhc_set_timing(struct mmc *mmc)
+{
+ struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+ u32 mixctrl;
+
+ mixctrl = readl(®s->mixctrl);
+ mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN);
+
+ switch (mmc->selected_mode) {
+ case MMC_LEGACY:
+ case SD_LEGACY:
+ esdhc_reset_tuning(mmc);
+ writel(mixctrl, ®s->mixctrl);
+ break;
+ case MMC_HS_400:
+ case MMC_HS_400_ES:
+ mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN;
+ writel(mixctrl, ®s->mixctrl);
+ esdhc_set_strobe_dll(mmc);
+ break;
+ case MMC_HS:
+ case MMC_HS_52:
+ case MMC_HS_200:
+ case SD_HS:
+ case UHS_SDR12:
+ case UHS_SDR25:
+ case UHS_SDR50:
+ case UHS_SDR104:
+ writel(mixctrl, ®s->mixctrl);
+ break;
+ case UHS_DDR50:
+ case MMC_DDR_52:
+ mixctrl |= MIX_CTRL_DDREN;
+ writel(mixctrl, ®s->mixctrl);
+ break;
+ default:
+ printf("Not supported %d\n", mmc->selected_mode);
+ return -EINVAL;
+ }
+
+ priv->mode = mmc->selected_mode;
+
+ return esdhc_change_pinstate(mmc->dev);
+}
+
+static int esdhc_set_voltage(struct mmc *mmc)
+{
+ struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+ int ret;
+
+ priv->signal_voltage = mmc->signal_voltage;
+ switch (mmc->signal_voltage) {
+ case MMC_SIGNAL_VOLTAGE_330:
+ if (priv->vs18_enable)
+ return -EIO;
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
+ ret = regulator_set_value(priv->vqmmc_dev, 3300000);
+ if (ret) {
+ printf("Setting to 3.3V error");
+ return -EIO;
+ }
+ /* Wait for 5ms */
+ mdelay(5);
+ }
+#endif
+
+ esdhc_clrbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
+ if (!(esdhc_read32(®s->vendorspec) &
+ ESDHC_VENDORSPEC_VSELECT))
+ return 0;
+
+ return -EAGAIN;
+ case MMC_SIGNAL_VOLTAGE_180:
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
+ ret = regulator_set_value(priv->vqmmc_dev, 1800000);
+ if (ret) {
+ printf("Setting to 1.8V error");
+ return -EIO;
+ }
+ }
+#endif
+ esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
+ if (esdhc_read32(®s->vendorspec) & ESDHC_VENDORSPEC_VSELECT)
+ return 0;
+
+ return -EAGAIN;
+ case MMC_SIGNAL_VOLTAGE_120:
+ return -ENOTSUPP;
+ default:
+ return 0;
+ }
+}
+
+static void esdhc_stop_tuning(struct mmc *mmc)
+{
+ struct mmc_cmd cmd;
+
+ cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
+ cmd.cmdarg = 0;
+ cmd.resp_type = MMC_RSP_R1b;
+
+ dm_mmc_send_cmd(mmc->dev, &cmd, NULL);
+}
+
+static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
+{
+ struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
+ struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+ struct mmc *mmc = &plat->mmc;
+ u32 irqstaten = readl(®s->irqstaten);
+ u32 irqsigen = readl(®s->irqsigen);
+ int i, ret = -ETIMEDOUT;
+ u32 val, mixctrl;
+
+ /* clock tuning is not needed for upto 52MHz */
+ if (mmc->clock <= 52000000)
+ return 0;
+
+ /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
+ if (priv->flags & ESDHC_FLAG_STD_TUNING) {
+ val = readl(®s->autoc12err);
+ mixctrl = readl(®s->mixctrl);
+ val &= ~MIX_CTRL_SMPCLK_SEL;
+ mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN);
+
+ val |= MIX_CTRL_EXE_TUNE;
+ mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN;
+
+ writel(val, ®s->autoc12err);
+ writel(mixctrl, ®s->mixctrl);
+ }
+
+ /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */
+ mixctrl = readl(®s->mixctrl);
+ mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK);
+ writel(mixctrl, ®s->mixctrl);
+
+ writel(IRQSTATEN_BRR, ®s->irqstaten);
+ writel(IRQSTATEN_BRR, ®s->irqsigen);
+
+ /*
+ * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
+ * of loops reaches 40 times.
+ */
+ for (i = 0; i < MAX_TUNING_LOOP; i++) {
+ u32 ctrl;
+
+ if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
+ if (mmc->bus_width == 8)
+ writel(0x7080, ®s->blkattr);
+ else if (mmc->bus_width == 4)
+ writel(0x7040, ®s->blkattr);
+ } else {
+ writel(0x7040, ®s->blkattr);
+ }
+
+ /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */
+ val = readl(®s->mixctrl);
+ val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK);
+ writel(val, ®s->mixctrl);
+
+ /* We are using STD tuning, no need to check return value */
+ mmc_send_tuning(mmc, opcode, NULL);
+
+ ctrl = readl(®s->autoc12err);
+ if ((!(ctrl & MIX_CTRL_EXE_TUNE)) &&
+ (ctrl & MIX_CTRL_SMPCLK_SEL)) {
+ /*
+ * need to wait some time, make sure sd/mmc fininsh
+ * send out tuning data, otherwise, the sd/mmc can't
+ * response to any command when the card still out
+ * put the tuning data.
+ */
+ mdelay(1);
+ ret = 0;
+ break;
+ }
+
+ /* Add 1ms delay for SD and eMMC */
+ mdelay(1);
+ }
+
+ writel(irqstaten, ®s->irqstaten);
+ writel(irqsigen, ®s->irqsigen);
+
+ esdhc_stop_tuning(mmc);
+
+ return ret;
+}
+#endif
+
+static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
+{
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+ int ret __maybe_unused;
+
+#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
+ /* Select to use peripheral clock */
+ esdhc_clock_control(priv, false);
+ esdhc_setbits32(®s->scr, ESDHCCTL_PCS);
+ esdhc_clock_control(priv, true);
+#endif
+ /* Set the clock speed */
+ if (priv->clock != mmc->clock)
+ set_sysctl(priv, mmc, mmc->clock);
+
+#ifdef MMC_SUPPORTS_TUNING
+ if (mmc->clk_disable) {
+#ifdef CONFIG_FSL_USDHC
+ esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
+#else
+ esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
+#endif
+ } else {
+#ifdef CONFIG_FSL_USDHC
+ esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
+ VENDORSPEC_CKEN);
+#else
+ esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
+#endif
+ }
+
+ if (priv->mode != mmc->selected_mode) {
+ ret = esdhc_set_timing(mmc);
+ if (ret) {
+ printf("esdhc_set_timing error %d\n", ret);
+ return ret;
+ }
+ }
+
+ if (priv->signal_voltage != mmc->signal_voltage) {
+ ret = esdhc_set_voltage(mmc);
+ if (ret) {
+ printf("esdhc_set_voltage error %d\n", ret);
+ return ret;
+ }
+ }
+#endif
+
+ /* Set the bus width */
+ esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
+
+ if (mmc->bus_width == 4)
+ esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
+ else if (mmc->bus_width == 8)
+ esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
+
+ return 0;
+}
+
+static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
+{
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+ ulong start;
+
+ /* Reset the entire host controller */
+ esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
+
+ /* Wait until the controller is available */
+ start = get_timer(0);
+ while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
+ if (get_timer(start) > 1000)
+ return -ETIMEDOUT;
+ }
+
+#if defined(CONFIG_FSL_USDHC)
+ /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
+ esdhc_write32(®s->mmcboot, 0x0);
+ /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
+ esdhc_write32(®s->mixctrl, 0x0);
+ esdhc_write32(®s->clktunectrlstatus, 0x0);
+
+ /* Put VEND_SPEC to default value */
+ if (priv->vs18_enable)
+ esdhc_write32(®s->vendorspec, (VENDORSPEC_INIT |
+ ESDHC_VENDORSPEC_VSELECT));
+ else
+ esdhc_write32(®s->vendorspec, VENDORSPEC_INIT);
+
+ /* Disable DLL_CTRL delay line */
+ esdhc_write32(®s->dllctrl, 0x0);
+#endif
+
+#ifndef ARCH_MXC
+ /* Enable cache snooping */
+ esdhc_write32(®s->scr, 0x00000040);
+#endif
+
+#ifndef CONFIG_FSL_USDHC
+ esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
+#else
+ esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
+#endif
+
+ /* Set the initial clock speed */
+ mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
+
+ /* Disable the BRR and BWR bits in IRQSTAT */
+ esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
+
+#ifdef CONFIG_MCF5441x
+ esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD);
+#else
+ /* Put the PROCTL reg back to the default */
+ esdhc_write32(®s->proctl, PROCTL_INIT);
+#endif
+
+ /* Set timout to the maximum value */
+ esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
+
+ return 0;
+}
+
+static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
+{
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+ int timeout = 1000;
+
+#ifdef CONFIG_ESDHC_DETECT_QUIRK
+ if (CONFIG_ESDHC_DETECT_QUIRK)
+ return 1;
+#endif
+
+#if CONFIG_IS_ENABLED(DM_MMC)
+ if (priv->non_removable)
+ return 1;
+#ifdef CONFIG_DM_GPIO
+ if (dm_gpio_is_valid(&priv->cd_gpio))
+ return dm_gpio_get_value(&priv->cd_gpio);
+#endif
+#endif
+
+ while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
+ udelay(1000);
+
+ return timeout > 0;
+}
+
+static int esdhc_reset(struct fsl_esdhc *regs)
+{
+ ulong start;
+
+ /* reset the controller */
+ esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
+
+ /* hardware clears the bit when it is done */
+ start = get_timer(0);
+ while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
+ if (get_timer(start) > 100) {
+ printf("MMC/SD: Reset never completed.\n");
+ return -ETIMEDOUT;
+ }
+ }
+
+ return 0;
+}
+
+#if !CONFIG_IS_ENABLED(DM_MMC)
+static int esdhc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_priv *priv = mmc->priv;
+
+ return esdhc_getcd_common(priv);
+}
+
+static int esdhc_init(struct mmc *mmc)
+{
+ struct fsl_esdhc_priv *priv = mmc->priv;
+
+ return esdhc_init_common(priv, mmc);
+}
+
+static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ struct fsl_esdhc_priv *priv = mmc->priv;
+
+ return esdhc_send_cmd_common(priv, mmc, cmd, data);
+}
+
+static int esdhc_set_ios(struct mmc *mmc)
+{
+ struct fsl_esdhc_priv *priv = mmc->priv;
+
+ return esdhc_set_ios_common(priv, mmc);
+}
+
+static const struct mmc_ops esdhc_ops = {
+ .getcd = esdhc_getcd,
+ .init = esdhc_init,
+ .send_cmd = esdhc_send_cmd,
+ .set_ios = esdhc_set_ios,
+};
+#endif
+
+static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
+ struct fsl_esdhc_plat *plat)
+{
+ struct mmc_config *cfg;
+ struct fsl_esdhc *regs;
+ u32 caps, voltage_caps;
+ int ret;
+
+ if (!priv)
+ return -EINVAL;
+
+ regs = priv->esdhc_regs;
+
+ /* First reset the eSDHC controller */
+ ret = esdhc_reset(regs);
+ if (ret)
+ return ret;
+
+#ifdef CONFIG_MCF5441x
+ /* ColdFire, using SDHC_DATA[3] for card detection */
+ esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD);
+#endif
+
+#ifndef CONFIG_FSL_USDHC
+ esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
+ | SYSCTL_IPGEN | SYSCTL_CKEN);
+ /* Clearing tuning bits in case ROM has set it already */
+ esdhc_write32(®s->mixctrl, 0);
+ esdhc_write32(®s->autoc12err, 0);
+ esdhc_write32(®s->clktunectrlstatus, 0);
+#else
+ esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
+ VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
+#endif
+
+ if (priv->vs18_enable)
+ esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
+
+ writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
+ cfg = &plat->cfg;
+#ifndef CONFIG_DM_MMC
+ memset(cfg, '\0', sizeof(*cfg));
+#endif
+
+ voltage_caps = 0;
+ caps = esdhc_read32(®s->hostcapblt);
+
+#ifdef CONFIG_MCF5441x
+ /*
+ * MCF5441x RM declares in more points that sdhc clock speed must
+ * never exceed 25 Mhz. From this, the HS bit needs to be disabled
+ * from host capabilities.
+ */
+ caps &= ~ESDHC_HOSTCAPBLT_HSS;
+#endif
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
+ caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
+ ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
+#endif
+
+/* T4240 host controller capabilities register should have VS33 bit */
+#ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+ caps = caps | ESDHC_HOSTCAPBLT_VS33;
+#endif
+
+ if (caps & ESDHC_HOSTCAPBLT_VS18)
+ voltage_caps |= MMC_VDD_165_195;
+ if (caps & ESDHC_HOSTCAPBLT_VS30)
+ voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
+ if (caps & ESDHC_HOSTCAPBLT_VS33)
+ voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
+
+ cfg->name = "FSL_SDHC";
+#if !CONFIG_IS_ENABLED(DM_MMC)
+ cfg->ops = &esdhc_ops;
+#endif
+#ifdef CONFIG_SYS_SD_VOLTAGE
+ cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
+#else
+ cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
+#endif
+ if ((cfg->voltages & voltage_caps) == 0) {
+ printf("voltage not supported by controller\n");
+ return -1;
+ }
+
+ if (priv->bus_width == 8)
+ cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
+ else if (priv->bus_width == 4)
+ cfg->host_caps = MMC_MODE_4BIT;
+
+ cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
+#ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
+ cfg->host_caps |= MMC_MODE_DDR_52MHz;
+#endif
+
+ if (priv->bus_width > 0) {
+ if (priv->bus_width < 8)
+ cfg->host_caps &= ~MMC_MODE_8BIT;
+ if (priv->bus_width < 4)
+ cfg->host_caps &= ~MMC_MODE_4BIT;
+ }
+
+ if (caps & ESDHC_HOSTCAPBLT_HSS)
+ cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
+
+#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
+ if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
+ cfg->host_caps &= ~MMC_MODE_8BIT;
+#endif
+
+ cfg->host_caps |= priv->caps;
+
+ cfg->f_min = 400000;
+ cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
+
+ cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+
+ writel(0, ®s->dllctrl);
+ if (priv->flags & ESDHC_FLAG_USDHC) {
+ if (priv->flags & ESDHC_FLAG_STD_TUNING) {
+ u32 val = readl(®s->tuning_ctrl);
+
+ val |= ESDHC_STD_TUNING_EN;
+ val &= ~ESDHC_TUNING_START_TAP_MASK;
+ val |= priv->tuning_start_tap;
+ val &= ~ESDHC_TUNING_STEP_MASK;
+ val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;
+ writel(val, ®s->tuning_ctrl);
+ }
+ }
+
+ return 0;
+}
+
+#if !CONFIG_IS_ENABLED(DM_MMC)
+static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
+ struct fsl_esdhc_priv *priv)
+{
+ if (!cfg || !priv)
+ return -EINVAL;
+
+ priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
+ priv->bus_width = cfg->max_bus_width;
+ priv->sdhc_clk = cfg->sdhc_clk;
+ priv->wp_enable = cfg->wp_enable;
+ priv->vs18_enable = cfg->vs18_enable;
+
+ return 0;
+};
+
+int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
+{
+ struct fsl_esdhc_plat *plat;
+ struct fsl_esdhc_priv *priv;
+ struct mmc *mmc;
+ int ret;
+
+ if (!cfg)
+ return -EINVAL;
+
+ priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
+ if (!priv)
+ return -ENOMEM;
+ plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
+ if (!plat) {
+ free(priv);
+ return -ENOMEM;
+ }
+
+ ret = fsl_esdhc_cfg_to_priv(cfg, priv);
+ if (ret) {
+ debug("%s xlate failure\n", __func__);
+ free(plat);
+ free(priv);
+ return ret;
+ }
+
+ ret = fsl_esdhc_init(priv, plat);
+ if (ret) {
+ debug("%s init failure\n", __func__);
+ free(plat);
+ free(priv);
+ return ret;
+ }
+
+ mmc = mmc_create(&plat->cfg, priv);
+ if (!mmc)
+ return -EIO;
+
+ priv->mmc = mmc;
+
+ return 0;
+}
+
+int fsl_esdhc_mmc_init(bd_t *bis)
+{
+ struct fsl_esdhc_cfg *cfg;
+
+ cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
+ cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
+ cfg->sdhc_clk = gd->arch.sdhc_clk;
+ return fsl_esdhc_initialize(bis, cfg);
+}
+#endif
+
+#ifdef CONFIG_OF_LIBFDT
+__weak int esdhc_status_fixup(void *blob, const char *compat)
+{
+#ifdef CONFIG_FSL_ESDHC_PIN_MUX
+ if (!hwconfig("esdhc")) {
+ do_fixup_by_compat(blob, compat, "status", "disabled",
+ sizeof("disabled"), 1);
+ return 1;
+ }
+#endif
+ return 0;
+}
+
+void fdt_fixup_esdhc(void *blob, bd_t *bd)
+{
+ const char *compat = "fsl,esdhc";
+
+ if (esdhc_status_fixup(blob, compat))
+ return;
+
+#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
+ do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
+ gd->arch.sdhc_clk, 1);
+#else
+ do_fixup_by_compat_u32(blob, compat, "clock-frequency",
+ gd->arch.sdhc_clk, 1);
+#endif
+}
+#endif
+
+#if CONFIG_IS_ENABLED(DM_MMC)
+#include <asm/arch/clock.h>
+__weak void init_clk_usdhc(u32 index)
+{
+}
+
+static int fsl_esdhc_probe(struct udevice *dev)
+{
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
+ struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+ const void *fdt = gd->fdt_blob;
+ int node = dev_of_offset(dev);
+ struct esdhc_soc_data *data =
+ (struct esdhc_soc_data *)dev_get_driver_data(dev);
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ struct udevice *vqmmc_dev;
+#endif
+ fdt_addr_t addr;
+ unsigned int val;
+ struct mmc *mmc;
+#if !CONFIG_IS_ENABLED(BLK)
+ struct blk_desc *bdesc;
+#endif
+ int ret;
+
+ addr = dev_read_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+ priv->esdhc_regs = (struct fsl_esdhc *)addr;
+ priv->dev = dev;
+ priv->mode = -1;
+ if (data)
+ priv->flags = data->flags;
+
+ val = dev_read_u32_default(dev, "bus-width", -1);
+ if (val == 8)
+ priv->bus_width = 8;
+ else if (val == 4)
+ priv->bus_width = 4;
+ else
+ priv->bus_width = 1;
+
+ val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1);
+ priv->tuning_step = val;
+ val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap",
+ ESDHC_TUNING_START_TAP_DEFAULT);
+ priv->tuning_start_tap = val;
+ val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target",
+ ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
+ priv->strobe_dll_delay_target = val;
+
+ if (dev_read_bool(dev, "non-removable")) {
+ priv->non_removable = 1;
+ } else {
+ priv->non_removable = 0;
+#ifdef CONFIG_DM_GPIO
+ gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
+ GPIOD_IS_IN);
+#endif
+ }
+
+ if (dev_read_prop(dev, "fsl,wp-controller", NULL)) {
+ priv->wp_enable = 1;
+ } else {
+ priv->wp_enable = 0;
+#ifdef CONFIG_DM_GPIO
+ gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
+ GPIOD_IS_IN);
+#endif
+ }
+
+ priv->vs18_enable = 0;
+
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ /*
+ * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
+ * otherwise, emmc will work abnormally.
+ */
+ ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
+ if (ret) {
+ dev_dbg(dev, "no vqmmc-supply\n");
+ } else {
+ ret = regulator_set_enable(vqmmc_dev, true);
+ if (ret) {
+ dev_err(dev, "fail to enable vqmmc-supply\n");
+ return ret;
+ }
+
+ if (regulator_get_value(vqmmc_dev) == 1800000)
+ priv->vs18_enable = 1;
+ }
+#endif
+
+ /*
+ * TODO:
+ * Because lack of clk driver, if SDHC clk is not enabled,
+ * need to enable it first before this driver is invoked.
+ *
+ * we use MXC_ESDHC_CLK to get clk freq.
+ * If one would like to make this function work,
+ * the aliases should be provided in dts as this:
+ *
+ * aliases {
+ * mmc0 = &usdhc1;
+ * mmc1 = &usdhc2;
+ * mmc2 = &usdhc3;
+ * mmc3 = &usdhc4;
+ * };
+ * Then if your board only supports mmc2 and mmc3, but we can
+ * correctly get the seq as 2 and 3, then let mxc_get_clock
+ * work as expected.
+ */
+
+ init_clk_usdhc(dev->seq);
+
+ if (CONFIG_IS_ENABLED(CLK)) {
+ /* Assigned clock already set clock */
+ ret = clk_get_by_name(dev, "per", &priv->per_clk);
+ if (ret) {
+ printf("Failed to get per_clk\n");
+ return ret;
+ }
+ ret = clk_enable(&priv->per_clk);
+ if (ret) {
+ printf("Failed to enable per_clk\n");
+ return ret;
+ }
+
+ priv->sdhc_clk = clk_get_rate(&priv->per_clk);
+ } else {
+ priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
+ if (priv->sdhc_clk <= 0) {
+ dev_err(dev, "Unable to get clk for %s\n", dev->name);
+ return -EINVAL;
+ }
+ }
+
+ ret = fsl_esdhc_init(priv, plat);
+ if (ret) {
+ dev_err(dev, "fsl_esdhc_init failure\n");
+ return ret;
+ }
+
+ ret = mmc_of_parse(dev, &plat->cfg);
+ if (ret)
+ return ret;
+
+ mmc = &plat->mmc;
+ mmc->cfg = &plat->cfg;
+ mmc->dev = dev;
+#if !CONFIG_IS_ENABLED(BLK)
+ mmc->priv = priv;
+
+ /* Setup dsr related values */
+ mmc->dsr_imp = 0;
+ mmc->dsr = ESDHC_DRIVER_STAGE_VALUE;
+ /* Setup the universal parts of the block interface just once */
+ bdesc = mmc_get_blk_desc(mmc);
+ bdesc->if_type = IF_TYPE_MMC;
+ bdesc->removable = 1;
+ bdesc->devnum = mmc_get_next_devnum();
+ bdesc->block_read = mmc_bread;
+ bdesc->block_write = mmc_bwrite;
+ bdesc->block_erase = mmc_berase;
+
+ /* setup initial part type */
+ bdesc->part_type = mmc->cfg->part_type;
+ mmc_list_add(mmc);
+#endif
+
+ upriv->mmc = mmc;
+
+ return esdhc_init_common(priv, mmc);
+}
+
+#if CONFIG_IS_ENABLED(DM_MMC)
+static int fsl_esdhc_get_cd(struct udevice *dev)
+{
+ struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+
+ return esdhc_getcd_common(priv);
+}
+
+static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
+ struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+
+ return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
+}
+
+static int fsl_esdhc_set_ios(struct udevice *dev)
+{
+ struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
+ struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+
+ return esdhc_set_ios_common(priv, &plat->mmc);
+}
+
+#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
+static int fsl_esdhc_set_enhanced_strobe(struct udevice *dev)
+{
+ struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+ u32 m;
+
+ m = readl(®s->mixctrl);
+ m |= MIX_CTRL_HS400_ES;
+ writel(m, ®s->mixctrl);
+
+ return 0;
+}
+#endif
+
+static const struct dm_mmc_ops fsl_esdhc_ops = {
+ .get_cd = fsl_esdhc_get_cd,
+ .send_cmd = fsl_esdhc_send_cmd,
+ .set_ios = fsl_esdhc_set_ios,
+#ifdef MMC_SUPPORTS_TUNING
+ .execute_tuning = fsl_esdhc_execute_tuning,
+#endif
+#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
+ .set_enhanced_strobe = fsl_esdhc_set_enhanced_strobe,
+#endif
+};
+#endif
+
+static struct esdhc_soc_data usdhc_imx7d_data = {
+ .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
+ | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
+ | ESDHC_FLAG_HS400,
+};
+
+static struct esdhc_soc_data usdhc_imx8qm_data = {
+ .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING |
+ ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 |
+ ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES,
+};
+
+static const struct udevice_id fsl_esdhc_ids[] = {
+ { .compatible = "fsl,imx53-esdhc", },
+ { .compatible = "fsl,imx6ul-usdhc", },
+ { .compatible = "fsl,imx6sx-usdhc", },
+ { .compatible = "fsl,imx6sl-usdhc", },
+ { .compatible = "fsl,imx6q-usdhc", },
+ { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,},
+ { .compatible = "fsl,imx7ulp-usdhc", },
+ { .compatible = "fsl,imx8qm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
+ { .compatible = "fsl,esdhc", },
+ { /* sentinel */ }
+};
+
+#if CONFIG_IS_ENABLED(BLK)
+static int fsl_esdhc_bind(struct udevice *dev)
+{
+ struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
+
+ return mmc_bind(dev, &plat->mmc, &plat->cfg);
+}
+#endif
+
+U_BOOT_DRIVER(fsl_esdhc) = {
+ .name = "fsl-esdhc-mmc",
+ .id = UCLASS_MMC,
+ .of_match = fsl_esdhc_ids,
+ .ops = &fsl_esdhc_ops,
+#if CONFIG_IS_ENABLED(BLK)
+ .bind = fsl_esdhc_bind,
+#endif
+ .probe = fsl_esdhc_probe,
+ .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
+ .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
+};
+#endif
diff --git a/drivers/mmc/hi6220_dw_mmc.c b/drivers/mmc/hi6220_dw_mmc.c
index effd1e4..6de7924 100644
--- a/drivers/mmc/hi6220_dw_mmc.c
+++ b/drivers/mmc/hi6220_dw_mmc.c
@@ -22,6 +22,11 @@
struct dwmci_host host;
};
+struct hisi_mmc_data {
+ unsigned int clock;
+ bool use_fifo;
+};
+
static int hi6220_dwmmc_ofdata_to_platdata(struct udevice *dev)
{
struct hi6220_dwmmc_priv_data *priv = dev_get_priv(dev);
@@ -49,13 +54,17 @@
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct hi6220_dwmmc_priv_data *priv = dev_get_priv(dev);
struct dwmci_host *host = &priv->host;
+ struct hisi_mmc_data *mmc_data;
+
+ mmc_data = (struct hisi_mmc_data *)dev_get_driver_data(dev);
/* Use default bus speed due to absence of clk driver */
- host->bus_hz = 50000000;
+ host->bus_hz = mmc_data->clock;
dwmci_setup_cfg(&plat->cfg, host, host->bus_hz, 400000);
host->mmc = &plat->mmc;
+ host->fifo_mode = mmc_data->use_fifo;
host->mmc->priv = &priv->host;
upriv->mmc = host->mmc;
host->mmc->dev = dev;
@@ -75,9 +84,23 @@
return 0;
}
+static const struct hisi_mmc_data hi3660_mmc_data = {
+ .clock = 3200000,
+ .use_fifo = true,
+};
+
+static const struct hisi_mmc_data hi6220_mmc_data = {
+ .clock = 50000000,
+ .use_fifo = false,
+};
+
static const struct udevice_id hi6220_dwmmc_ids[] = {
- { .compatible = "hisilicon,hi6220-dw-mshc" },
- { .compatible = "hisilicon,hi3798cv200-dw-mshc" },
+ { .compatible = "hisilicon,hi6220-dw-mshc",
+ .data = (ulong)&hi6220_mmc_data },
+ { .compatible = "hisilicon,hi3798cv200-dw-mshc",
+ .data = (ulong)&hi6220_mmc_data },
+ { .compatible = "hisilicon,hi3660-dw-mshc",
+ .data = (ulong)&hi3660_mmc_data },
{ }
};
diff --git a/drivers/mmc/k3_arsan_sdhci.c b/drivers/mmc/k3_arsan_sdhci.c
deleted file mode 100644
index d5f2857..0000000
--- a/drivers/mmc/k3_arsan_sdhci.c
+++ /dev/null
@@ -1,109 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
- *
- * Texas Instruments' K3 SD Host Controller Interface
- */
-
-#include <clk.h>
-#include <common.h>
-#include <dm.h>
-#include <malloc.h>
-#include <power-domain.h>
-#include <sdhci.h>
-
-#define K3_ARASAN_SDHCI_MIN_FREQ 0
-
-struct k3_arasan_sdhci_plat {
- struct mmc_config cfg;
- struct mmc mmc;
- unsigned int f_max;
-};
-
-static int k3_arasan_sdhci_probe(struct udevice *dev)
-{
- struct k3_arasan_sdhci_plat *plat = dev_get_platdata(dev);
- struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
- struct sdhci_host *host = dev_get_priv(dev);
- struct power_domain sdhci_pwrdmn;
- struct clk clk;
- unsigned long clock;
- int ret;
-
- ret = power_domain_get_by_index(dev, &sdhci_pwrdmn, 0);
- if (ret) {
- dev_err(dev, "failed to get power domain\n");
- return ret;
- }
-
- ret = power_domain_on(&sdhci_pwrdmn);
- if (ret) {
- dev_err(dev, "Power domain on failed\n");
- return ret;
- }
-
- ret = clk_get_by_index(dev, 0, &clk);
- if (ret) {
- dev_err(dev, "failed to get clock\n");
- return ret;
- }
-
- clock = clk_get_rate(&clk);
- if (IS_ERR_VALUE(clock)) {
- dev_err(dev, "failed to get rate\n");
- return clock;
- }
-
- host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
- SDHCI_QUIRK_BROKEN_R1B;
-
- host->max_clk = clock;
-
- ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max,
- K3_ARASAN_SDHCI_MIN_FREQ);
- host->mmc = &plat->mmc;
- if (ret)
- return ret;
- host->mmc->priv = host;
- host->mmc->dev = dev;
- upriv->mmc = host->mmc;
-
- return sdhci_probe(dev);
-}
-
-static int k3_arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
-{
- struct k3_arasan_sdhci_plat *plat = dev_get_platdata(dev);
- struct sdhci_host *host = dev_get_priv(dev);
-
- host->name = dev->name;
- host->ioaddr = (void *)dev_read_addr(dev);
- host->bus_width = dev_read_u32_default(dev, "bus-width", 4);
- plat->f_max = dev_read_u32_default(dev, "max-frequency", 0);
-
- return 0;
-}
-
-static int k3_arasan_sdhci_bind(struct udevice *dev)
-{
- struct k3_arasan_sdhci_plat *plat = dev_get_platdata(dev);
-
- return sdhci_bind(dev, &plat->mmc, &plat->cfg);
-}
-
-static const struct udevice_id k3_arasan_sdhci_ids[] = {
- { .compatible = "arasan,sdhci-5.1" },
- { }
-};
-
-U_BOOT_DRIVER(k3_arasan_sdhci_drv) = {
- .name = "k3_arasan_sdhci",
- .id = UCLASS_MMC,
- .of_match = k3_arasan_sdhci_ids,
- .ofdata_to_platdata = k3_arasan_sdhci_ofdata_to_platdata,
- .ops = &sdhci_ops,
- .bind = k3_arasan_sdhci_bind,
- .probe = k3_arasan_sdhci_probe,
- .priv_auto_alloc_size = sizeof(struct sdhci_host),
- .platdata_auto_alloc_size = sizeof(struct k3_arasan_sdhci_plat),
-};
diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c
index a9c8f33..37c3843 100644
--- a/drivers/mmc/mmc-uclass.c
+++ b/drivers/mmc/mmc-uclass.c
@@ -47,34 +47,19 @@
return dm_mmc_set_ios(mmc->dev);
}
-void dm_mmc_send_init_stream(struct udevice *dev)
-{
- struct dm_mmc_ops *ops = mmc_get_ops(dev);
-
- if (ops->send_init_stream)
- ops->send_init_stream(dev);
-}
-
-void mmc_send_init_stream(struct mmc *mmc)
-{
- dm_mmc_send_init_stream(mmc->dev);
-}
-
-#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
-int dm_mmc_wait_dat0(struct udevice *dev, int state, int timeout)
+int dm_mmc_wait_dat0(struct udevice *dev, int state, int timeout_us)
{
struct dm_mmc_ops *ops = mmc_get_ops(dev);
if (!ops->wait_dat0)
return -ENOSYS;
- return ops->wait_dat0(dev, state, timeout);
+ return ops->wait_dat0(dev, state, timeout_us);
}
-int mmc_wait_dat0(struct mmc *mmc, int state, int timeout)
+int mmc_wait_dat0(struct mmc *mmc, int state, int timeout_us)
{
- return dm_mmc_wait_dat0(mmc->dev, state, timeout);
+ return dm_mmc_wait_dat0(mmc->dev, state, timeout_us);
}
-#endif
int dm_mmc_get_wp(struct udevice *dev)
{
@@ -120,6 +105,23 @@
}
#endif
+#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
+int dm_mmc_set_enhanced_strobe(struct udevice *dev)
+{
+ struct dm_mmc_ops *ops = mmc_get_ops(dev);
+
+ if (ops->set_enhanced_strobe)
+ return ops->set_enhanced_strobe(dev);
+
+ return -ENOTSUPP;
+}
+
+int mmc_set_enhanced_strobe(struct mmc *mmc)
+{
+ return dm_mmc_set_enhanced_strobe(mmc->dev);
+}
+#endif
+
int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg)
{
int val;
@@ -170,6 +172,22 @@
cfg->host_caps |= MMC_CAP(MMC_HS_400);
if (dev_read_bool(dev, "mmc-hs400-1_2v"))
cfg->host_caps |= MMC_CAP(MMC_HS_400);
+ if (dev_read_bool(dev, "mmc-hs400-enhanced-strobe"))
+ cfg->host_caps |= MMC_CAP(MMC_HS_400_ES);
+
+ if (dev_read_bool(dev, "non-removable")) {
+ cfg->host_caps |= MMC_CAP_NONREMOVABLE;
+ } else {
+ if (dev_read_bool(dev, "cd-inverted"))
+ cfg->host_caps |= MMC_CAP_CD_ACTIVE_HIGH;
+ if (dev_read_bool(dev, "broken-cd"))
+ cfg->host_caps |= MMC_CAP_NEEDS_POLL;
+ }
+
+ if (dev_read_bool(dev, "no-1-8-v")) {
+ cfg->host_caps &= ~(UHS_CAPS | MMC_MODE_HS200 |
+ MMC_MODE_HS400 | MMC_MODE_HS400_ES);
+ }
return 0;
}
@@ -342,6 +360,7 @@
struct udevice *mmc_dev = dev_get_parent(bdev);
struct mmc *mmc = mmc_get_mmc_dev(mmc_dev);
struct blk_desc *desc = dev_get_uclass_platdata(bdev);
+ int ret;
if (desc->hwpart == hwpart)
return 0;
@@ -349,7 +368,11 @@
if (mmc->part_config == MMCPART_NOAVAILABLE)
return -EMEDIUMTYPE;
- return mmc_switch_part(mmc, hwpart);
+ ret = mmc_switch_part(mmc, hwpart);
+ if (!ret)
+ blkcache_invalidate(desc->if_type, desc->devnum);
+
+ return ret;
}
static int mmc_blk_probe(struct udevice *dev)
@@ -404,10 +427,6 @@
};
#endif /* CONFIG_BLK */
-U_BOOT_DRIVER(mmc) = {
- .name = "mmc",
- .id = UCLASS_MMC,
-};
UCLASS_DRIVER(mmc) = {
.id = UCLASS_MMC,
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 71b52c6..c8f71cd 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -21,6 +21,8 @@
#include <div64.h>
#include "mmc_private.h"
+#define DEFAULT_CMD6_TIMEOUT_MS 500
+
static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
static int mmc_power_cycle(struct mmc *mmc);
#if !CONFIG_IS_ENABLED(MMC_TINY)
@@ -29,12 +31,10 @@
#if !CONFIG_IS_ENABLED(DM_MMC)
-#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
-static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout)
+static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout_us)
{
return -ENOSYS;
}
-#endif
__weak int board_mmc_getwp(struct mmc *mmc)
{
@@ -148,6 +148,7 @@
[MMC_DDR_52] = "MMC DDR52 (52MHz)",
[MMC_HS_200] = "HS200 (200MHz)",
[MMC_HS_400] = "HS400 (200MHz)",
+ [MMC_HS_400_ES] = "HS400ES (200MHz)",
};
if (mode >= MMC_MODES_END)
@@ -173,6 +174,7 @@
[UHS_SDR104] = 208000000,
[MMC_HS_200] = 200000000,
[MMC_HS_400] = 200000000,
+ [MMC_HS_400_ES] = 200000000,
};
if (mode == MMC_LEGACY)
@@ -206,7 +208,7 @@
}
#endif
-int mmc_send_status(struct mmc *mmc, int timeout)
+int mmc_send_status(struct mmc *mmc, unsigned int *status)
{
struct mmc_cmd cmd;
int err, retries = 5;
@@ -216,32 +218,51 @@
if (!mmc_host_is_spi(mmc))
cmd.cmdarg = mmc->rca << 16;
- while (1) {
+ while (retries--) {
err = mmc_send_cmd(mmc, &cmd, NULL);
if (!err) {
- if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
- (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
- MMC_STATE_PRG)
- break;
+ mmc_trace_state(mmc, &cmd);
+ *status = cmd.response[0];
+ return 0;
+ }
+ }
+ mmc_trace_state(mmc, &cmd);
+ return -ECOMM;
+}
- if (cmd.response[0] & MMC_STATUS_MASK) {
-#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
- pr_err("Status Error: 0x%08x\n",
- cmd.response[0]);
-#endif
- return -ECOMM;
- }
- } else if (--retries < 0)
+int mmc_poll_for_busy(struct mmc *mmc, int timeout_ms)
+{
+ unsigned int status;
+ int err;
+
+ err = mmc_wait_dat0(mmc, 1, timeout_ms * 1000);
+ if (err != -ENOSYS)
+ return err;
+
+ while (1) {
+ err = mmc_send_status(mmc, &status);
+ if (err)
return err;
- if (timeout-- <= 0)
+ if ((status & MMC_STATUS_RDY_FOR_DATA) &&
+ (status & MMC_STATUS_CURR_STATE) !=
+ MMC_STATE_PRG)
+ break;
+
+ if (status & MMC_STATUS_MASK) {
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
+ pr_err("Status Error: 0x%08x\n", status);
+#endif
+ return -ECOMM;
+ }
+
+ if (timeout_ms-- <= 0)
break;
udelay(1000);
}
- mmc_trace_state(mmc, &cmd);
- if (timeout <= 0) {
+ if (timeout_ms <= 0) {
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
pr_err("Timeout waiting card ready\n");
#endif
@@ -727,36 +748,67 @@
static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value,
bool send_status)
{
+ unsigned int status, start;
struct mmc_cmd cmd;
- int timeout = 1000;
+ int timeout_ms = DEFAULT_CMD6_TIMEOUT_MS;
+ bool is_part_switch = (set == EXT_CSD_CMD_SET_NORMAL) &&
+ (index == EXT_CSD_PART_CONF);
int retries = 3;
int ret;
+ if (mmc->gen_cmd6_time)
+ timeout_ms = mmc->gen_cmd6_time * 10;
+
+ if (is_part_switch && mmc->part_switch_time)
+ timeout_ms = mmc->part_switch_time * 10;
+
cmd.cmdidx = MMC_CMD_SWITCH;
cmd.resp_type = MMC_RSP_R1b;
cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
(index << 16) |
(value << 8);
- while (retries > 0) {
+ do {
ret = mmc_send_cmd(mmc, &cmd, NULL);
+ } while (ret && retries-- > 0);
- if (ret) {
- retries--;
- continue;
+ if (ret)
+ return ret;
+
+ start = get_timer(0);
+
+ /* poll dat0 for rdy/buys status */
+ ret = mmc_wait_dat0(mmc, 1, timeout_ms * 1000);
+ if (ret && ret != -ENOSYS)
+ return ret;
+
+ /*
+ * In cases when not allowed to poll by using CMD13 or because we aren't
+ * capable of polling by using mmc_wait_dat0, then rely on waiting the
+ * stated timeout to be sufficient.
+ */
+ if (ret == -ENOSYS && !send_status)
+ mdelay(timeout_ms);
+
+ /* Finally wait until the card is ready or indicates a failure
+ * to switch. It doesn't hurt to use CMD13 here even if send_status
+ * is false, because by now (after 'timeout_ms' ms) the bus should be
+ * reliable.
+ */
+ do {
+ ret = mmc_send_status(mmc, &status);
+
+ if (!ret && (status & MMC_STATUS_SWITCH_ERROR)) {
+ pr_debug("switch failed %d/%d/0x%x !\n", set, index,
+ value);
+ return -EIO;
}
-
- if (!send_status) {
- mdelay(50);
+ if (!ret && (status & MMC_STATUS_RDY_FOR_DATA))
return 0;
- }
+ udelay(100);
+ } while (get_timer(start) < timeout_ms);
- /* Waiting for the ready status */
- return mmc_send_status(mmc, timeout);
- }
-
- return ret;
-
+ return -ETIMEDOUT;
}
int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
@@ -789,6 +841,11 @@
speed_bits = EXT_CSD_TIMING_HS400;
break;
#endif
+#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
+ case MMC_HS_400_ES:
+ speed_bits = EXT_CSD_TIMING_HS400;
+ break;
+#endif
case MMC_LEGACY:
speed_bits = EXT_CSD_TIMING_LEGACY;
break;
@@ -859,7 +916,8 @@
mmc->card_caps |= MMC_MODE_HS200;
}
#endif
-#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
+#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) || \
+ CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
if (cardtype & (EXT_CSD_CARD_TYPE_HS400_1_2V |
EXT_CSD_CARD_TYPE_HS400_1_8V)) {
mmc->card_caps |= MMC_MODE_HS400;
@@ -873,6 +931,13 @@
if (cardtype & EXT_CSD_CARD_TYPE_26)
mmc->card_caps |= MMC_MODE_HS;
+#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
+ if (ext_csd[EXT_CSD_STROBE_SUPPORT] &&
+ (mmc->card_caps & MMC_MODE_HS400)) {
+ mmc->card_caps |= MMC_MODE_HS400_ES;
+ }
+#endif
+
return 0;
}
#endif
@@ -905,49 +970,17 @@
return 0;
}
-#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
-static int mmc_boot_part_access_chk(struct mmc *mmc, unsigned int part_num)
-{
- int forbidden = 0;
- bool change = false;
-
- if (part_num & PART_ACCESS_MASK)
- forbidden = MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_HS_400);
-
- if (MMC_CAP(mmc->selected_mode) & forbidden) {
- pr_debug("selected mode (%s) is forbidden for part %d\n",
- mmc_mode_name(mmc->selected_mode), part_num);
- change = true;
- } else if (mmc->selected_mode != mmc->best_mode) {
- pr_debug("selected mode is not optimal\n");
- change = true;
- }
-
- if (change)
- return mmc_select_mode_and_width(mmc,
- mmc->card_caps & ~forbidden);
-
- return 0;
-}
-#else
-static inline int mmc_boot_part_access_chk(struct mmc *mmc,
- unsigned int part_num)
-{
- return 0;
-}
-#endif
-
int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
{
int ret;
+ int retry = 3;
- ret = mmc_boot_part_access_chk(mmc, part_num);
- if (ret)
- return ret;
-
- ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
- (mmc->part_config & ~PART_ACCESS_MASK)
- | (part_num & PART_ACCESS_MASK));
+ do {
+ ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+ EXT_CSD_PART_CONF,
+ (mmc->part_config & ~PART_ACCESS_MASK)
+ | (part_num & PART_ACCESS_MASK));
+ } while (ret && retry--);
/*
* Set the capacity if the switch succeeded or was intended
@@ -1504,10 +1537,6 @@
}
#endif
-static void mmc_send_init_stream(struct mmc *mmc)
-{
-}
-
static int mmc_set_ios(struct mmc *mmc)
{
int ret = 0;
@@ -1672,6 +1701,13 @@
mmc_dump_capabilities("host", mmc->host_caps);
#endif
+ if (mmc_host_is_spi(mmc)) {
+ mmc_set_bus_width(mmc, 1);
+ mmc_select_mode(mmc, SD_LEGACY);
+ mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE);
+ return 0;
+ }
+
/* Restrict card's capabilities by what the host can do */
caps = card_caps & mmc->host_caps;
@@ -1778,6 +1814,7 @@
u32 card_mask = 0;
switch (mode) {
+ case MMC_HS_400_ES:
case MMC_HS_400:
case MMC_HS_200:
if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_8V |
@@ -1820,6 +1857,12 @@
#endif
static const struct mode_width_tuning mmc_modes_by_pref[] = {
+#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
+ {
+ .mode = MMC_HS_400_ES,
+ .widths = MMC_MODE_8BIT,
+ },
+#endif
#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
{
.mode = MMC_HS_400,
@@ -1917,6 +1960,47 @@
}
#endif
+#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
+#if !CONFIG_IS_ENABLED(DM_MMC)
+static int mmc_set_enhanced_strobe(struct mmc *mmc)
+{
+ return -ENOTSUPP;
+}
+#endif
+static int mmc_select_hs400es(struct mmc *mmc)
+{
+ int err;
+
+ err = mmc_set_card_speed(mmc, MMC_HS, true);
+ if (err)
+ return err;
+
+ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
+ EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG |
+ EXT_CSD_BUS_WIDTH_STROBE);
+ if (err) {
+ printf("switch to bus width for hs400 failed\n");
+ return err;
+ }
+ /* TODO: driver strength */
+ err = mmc_set_card_speed(mmc, MMC_HS_400_ES, false);
+ if (err)
+ return err;
+
+ mmc_select_mode(mmc, MMC_HS_400_ES);
+ err = mmc_set_clock(mmc, mmc->tran_speed, false);
+ if (err)
+ return err;
+
+ return mmc_set_enhanced_strobe(mmc);
+}
+#else
+static int mmc_select_hs400es(struct mmc *mmc)
+{
+ return -ENOTSUPP;
+}
+#endif
+
#define for_each_supported_width(caps, ddr, ecbv) \
for (ecbv = ext_csd_bus_width;\
ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\
@@ -1934,6 +2018,13 @@
mmc_dump_capabilities("host", mmc->host_caps);
#endif
+ if (mmc_host_is_spi(mmc)) {
+ mmc_set_bus_width(mmc, 1);
+ mmc_select_mode(mmc, MMC_LEGACY);
+ mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE);
+ return 0;
+ }
+
/* Restrict card's capabilities by what the host can do */
card_caps &= mmc->host_caps;
@@ -1988,6 +2079,13 @@
printf("Select HS400 failed %d\n", err);
goto error;
}
+ } else if (mwt->mode == MMC_HS_400_ES) {
+ err = mmc_select_hs400es(mmc);
+ if (err) {
+ printf("Select HS400ES failed %d\n",
+ err);
+ goto error;
+ }
} else {
/* configure the bus speed (card) */
err = mmc_set_card_speed(mmc, mwt->mode, false);
@@ -2122,6 +2220,9 @@
mmc->capacity_user = capacity;
}
+ if (mmc->version >= MMC_VERSION_4_5)
+ mmc->gen_cmd6_time = ext_csd[EXT_CSD_GENERIC_CMD6_TIME];
+
/* The partition data may be non-zero but it is only
* effective if PARTITION_SETTING_COMPLETED is set in
* EXT_CSD, so ignore any data if this bit is not set,
@@ -2131,6 +2232,11 @@
part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
EXT_CSD_PARTITION_SETTING_COMPLETED);
+ mmc->part_switch_time = ext_csd[EXT_CSD_PART_SWITCH_TIME];
+ /* Some eMMC set the value too low so set a minimum */
+ if (mmc->part_switch_time < MMC_MIN_PART_SWITCH_TIME && mmc->part_switch_time)
+ mmc->part_switch_time = MMC_MIN_PART_SWITCH_TIME;
+
/* store the partition info of emmc */
mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
@@ -2664,7 +2770,6 @@
retry:
mmc_set_initial_state(mmc);
- mmc_send_init_stream(mmc);
/* Reset the Card */
err = mmc_go_idle(mmc);
@@ -2714,12 +2819,12 @@
MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT;
#if !defined(CONFIG_MMC_BROKEN_CD)
- /* we pretend there's no card when init is NULL */
no_card = mmc_getcd(mmc) == 0;
#else
no_card = 0;
#endif
#if !CONFIG_IS_ENABLED(DM_MMC)
+ /* we pretend there's no card when init is NULL */
no_card = no_card || (mmc->cfg->ops->init == NULL);
#endif
if (no_card) {
diff --git a/drivers/mmc/mmc_legacy.c b/drivers/mmc/mmc_legacy.c
index 66a7cda..b0f5cf5 100644
--- a/drivers/mmc/mmc_legacy.c
+++ b/drivers/mmc/mmc_legacy.c
@@ -150,6 +150,15 @@
{
struct mmc *mmc = &mmc_static;
+ /* First MMC device registered, fail to register a new one.
+ * Given users are not expecting this to fail, instead
+ * of failing let's just return the only MMC device
+ */
+ if (mmc->cfg) {
+ debug("Warning: MMC_TINY doesn't support multiple MMC devices\n");
+ return mmc;
+ }
+
mmc->cfg = cfg;
mmc->priv = priv;
diff --git a/drivers/mmc/mmc_private.h b/drivers/mmc/mmc_private.h
index f49b6eb..35170d0 100644
--- a/drivers/mmc/mmc_private.h
+++ b/drivers/mmc/mmc_private.h
@@ -11,10 +11,11 @@
#include <mmc.h>
-extern int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
- struct mmc_data *data);
-extern int mmc_send_status(struct mmc *mmc, int timeout);
-extern int mmc_set_blocklen(struct mmc *mmc, int len);
+int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data);
+int mmc_send_status(struct mmc *mmc, unsigned int *status);
+int mmc_poll_for_busy(struct mmc *mmc, int timeout);
+
+int mmc_set_blocklen(struct mmc *mmc, int len);
#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
void mmc_adapter_card_type_ident(void);
#endif
diff --git a/drivers/mmc/mmc_spi.c b/drivers/mmc/mmc_spi.c
index 4f57990..c693fb2 100644
--- a/drivers/mmc/mmc_spi.c
+++ b/drivers/mmc/mmc_spi.c
@@ -2,6 +2,8 @@
* generic mmc spi driver
*
* Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
+ * Copyright 2019 Bhargav Shah <bhargavshah1988@gmail.com>
+ *
* Licensed under the GPL-2 or later.
*/
#include <common.h>
@@ -9,21 +11,23 @@
#include <malloc.h>
#include <part.h>
#include <mmc.h>
-#include <spi.h>
+#include <stdlib.h>
#include <u-boot/crc.h>
#include <linux/crc7.h>
#include <asm/byteorder.h>
+#include <dm.h>
+#include <spi.h>
/* MMC/SD in SPI mode reports R1 status always */
-#define R1_SPI_IDLE (1 << 0)
-#define R1_SPI_ERASE_RESET (1 << 1)
-#define R1_SPI_ILLEGAL_COMMAND (1 << 2)
-#define R1_SPI_COM_CRC (1 << 3)
-#define R1_SPI_ERASE_SEQ (1 << 4)
-#define R1_SPI_ADDRESS (1 << 5)
-#define R1_SPI_PARAMETER (1 << 6)
+#define R1_SPI_IDLE BIT(0)
+#define R1_SPI_ERASE_RESET BIT(1)
+#define R1_SPI_ILLEGAL_COMMAND BIT(2)
+#define R1_SPI_COM_CRC BIT(3)
+#define R1_SPI_ERASE_SEQ BIT(4)
+#define R1_SPI_ADDRESS BIT(5)
+#define R1_SPI_PARAMETER BIT(6)
/* R1 bit 7 is always zero, reuse this bit for error */
-#define R1_SPI_ERROR (1 << 7)
+#define R1_SPI_ERROR BIT(7)
/* Response tokens used to ack each block written: */
#define SPI_MMC_RESPONSE_CODE(x) ((x) & 0x1f)
@@ -34,28 +38,48 @@
/* Read and write blocks start with these tokens and end with crc;
* on error, read tokens act like a subset of R2_SPI_* values.
*/
-#define SPI_TOKEN_SINGLE 0xfe /* single block r/w, multiblock read */
-#define SPI_TOKEN_MULTI_WRITE 0xfc /* multiblock write */
-#define SPI_TOKEN_STOP_TRAN 0xfd /* terminate multiblock write */
+/* single block write multiblock read */
+#define SPI_TOKEN_SINGLE 0xfe
+/* multiblock write */
+#define SPI_TOKEN_MULTI_WRITE 0xfc
+/* terminate multiblock write */
+#define SPI_TOKEN_STOP_TRAN 0xfd
/* MMC SPI commands start with a start bit "0" and a transmit bit "1" */
-#define MMC_SPI_CMD(x) (0x40 | (x & 0x3f))
+#define MMC_SPI_CMD(x) (0x40 | (x))
/* bus capability */
-#define MMC_SPI_VOLTAGE (MMC_VDD_32_33 | MMC_VDD_33_34)
-#define MMC_SPI_MIN_CLOCK 400000 /* 400KHz to meet MMC spec */
+#define MMC_SPI_VOLTAGE (MMC_VDD_32_33 | MMC_VDD_33_34)
+#define MMC_SPI_MIN_CLOCK 400000 /* 400KHz to meet MMC spec */
+#define MMC_SPI_MAX_CLOCK 25000000 /* SD/MMC legacy speed */
/* timeout value */
-#define CTOUT 8
-#define RTOUT 3000000 /* 1 sec */
-#define WTOUT 3000000 /* 1 sec */
+#define CMD_TIMEOUT 8
+#define READ_TIMEOUT 3000000 /* 1 sec */
+#define WRITE_TIMEOUT 3000000 /* 1 sec */
-static uint mmc_spi_sendcmd(struct mmc *mmc, ushort cmdidx, u32 cmdarg)
+struct mmc_spi_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
+struct mmc_spi_priv {
+ struct spi_slave *spi;
+};
+
+static int mmc_spi_sendcmd(struct udevice *dev,
+ ushort cmdidx, u32 cmdarg, u32 resp_type,
+ u8 *resp, u32 resp_size,
+ bool resp_match, u8 resp_match_value)
{
- struct spi_slave *spi = mmc->priv;
- u8 cmdo[7];
- u8 r1;
- int i;
+ int i, rpos = 0, ret = 0;
+ u8 cmdo[7], r;
+
+ debug("%s: cmd%d cmdarg=0x%x resp_type=0x%x "
+ "resp_size=%d resp_match=%d resp_match_value=0x%x\n",
+ __func__, cmdidx, cmdarg, resp_type,
+ resp_size, resp_match, resp_match_value);
+
cmdo[0] = 0xff;
cmdo[1] = MMC_SPI_CMD(cmdidx);
cmdo[2] = cmdarg >> 24;
@@ -63,37 +87,79 @@
cmdo[4] = cmdarg >> 8;
cmdo[5] = cmdarg;
cmdo[6] = (crc7(0, &cmdo[1], 5) << 1) | 0x01;
- spi_xfer(spi, sizeof(cmdo) * 8, cmdo, NULL, 0);
- for (i = 0; i < CTOUT; i++) {
- spi_xfer(spi, 1 * 8, NULL, &r1, 0);
- if (i && (r1 & 0x80) == 0) /* r1 response */
- break;
- }
- debug("%s:cmd%d resp%d %x\n", __func__, cmdidx, i, r1);
- return r1;
-}
+ ret = dm_spi_xfer(dev, sizeof(cmdo) * 8, cmdo, NULL, SPI_XFER_BEGIN);
+ if (ret)
+ return ret;
-static uint mmc_spi_readdata(struct mmc *mmc, void *xbuf,
- u32 bcnt, u32 bsize)
-{
- struct spi_slave *spi = mmc->priv;
- u8 *buf = xbuf;
- u8 r1;
- u16 crc;
- int i;
- while (bcnt--) {
- for (i = 0; i < RTOUT; i++) {
- spi_xfer(spi, 1 * 8, NULL, &r1, 0);
- if (r1 != 0xff) /* data token */
+ ret = dm_spi_xfer(dev, 1 * 8, NULL, &r, 0);
+ if (ret)
+ return ret;
+
+ if (!resp || !resp_size)
+ return 0;
+
+ debug("%s: cmd%d", __func__, cmdidx);
+
+ if (resp_match) {
+ r = ~resp_match_value;
+ i = CMD_TIMEOUT;
+ while (i--) {
+ ret = dm_spi_xfer(dev, 1 * 8, NULL, &r, 0);
+ if (ret)
+ return ret;
+ debug(" resp%d=0x%x", rpos, r);
+ rpos++;
+ if (r == resp_match_value)
break;
}
- debug("%s:tok%d %x\n", __func__, i, r1);
+ if (!i && (r != resp_match_value))
+ return -ETIMEDOUT;
+ }
+
+ for (i = 0; i < resp_size; i++) {
+ if (i == 0 && resp_match) {
+ resp[i] = resp_match_value;
+ continue;
+ }
+ ret = dm_spi_xfer(dev, 1 * 8, NULL, &r, 0);
+ if (ret)
+ return ret;
+ debug(" resp%d=0x%x", rpos, r);
+ rpos++;
+ resp[i] = r;
+ }
+
+ debug("\n");
+
+ return 0;
+}
+
+static int mmc_spi_readdata(struct udevice *dev,
+ void *xbuf, u32 bcnt, u32 bsize)
+{
+ u16 crc;
+ u8 *buf = xbuf, r1;
+ int i, ret = 0;
+
+ while (bcnt--) {
+ for (i = 0; i < READ_TIMEOUT; i++) {
+ ret = dm_spi_xfer(dev, 1 * 8, NULL, &r1, 0);
+ if (ret)
+ return ret;
+ if (r1 == SPI_TOKEN_SINGLE)
+ break;
+ }
+ debug("%s: data tok%d 0x%x\n", __func__, i, r1);
if (r1 == SPI_TOKEN_SINGLE) {
- spi_xfer(spi, bsize * 8, NULL, buf, 0);
- spi_xfer(spi, 2 * 8, NULL, &crc, 0);
+ ret = dm_spi_xfer(dev, bsize * 8, NULL, buf, 0);
+ if (ret)
+ return ret;
+ ret = dm_spi_xfer(dev, 2 * 8, NULL, &crc, 0);
+ if (ret)
+ return ret;
#ifdef CONFIG_MMC_SPI_CRC_ON
- if (be_to_cpu16(crc16_ccitt(0, buf, bsize)) != crc) {
- debug("%s: CRC error\n", mmc->cfg->name);
+ if (be16_to_cpu(crc16_ccitt(0, buf, bsize)) != crc) {
+ debug("%s: data crc error\n", __func__);
r1 = R1_SPI_COM_CRC;
break;
}
@@ -105,48 +171,56 @@
}
buf += bsize;
}
- return r1;
+
+ if (r1 & R1_SPI_COM_CRC)
+ ret = -ECOMM;
+ else if (r1) /* other errors */
+ ret = -ETIMEDOUT;
+
+ return ret;
}
-static uint mmc_spi_writedata(struct mmc *mmc, const void *xbuf,
- u32 bcnt, u32 bsize, int multi)
+static int mmc_spi_writedata(struct udevice *dev, const void *xbuf,
+ u32 bcnt, u32 bsize, int multi)
{
- struct spi_slave *spi = mmc->priv;
const u8 *buf = xbuf;
- u8 r1;
+ u8 r1, tok[2];
u16 crc;
- u8 tok[2];
- int i;
+ int i, ret = 0;
+
tok[0] = 0xff;
tok[1] = multi ? SPI_TOKEN_MULTI_WRITE : SPI_TOKEN_SINGLE;
+
while (bcnt--) {
#ifdef CONFIG_MMC_SPI_CRC_ON
crc = cpu_to_be16(crc16_ccitt(0, (u8 *)buf, bsize));
#endif
- spi_xfer(spi, 2 * 8, tok, NULL, 0);
- spi_xfer(spi, bsize * 8, buf, NULL, 0);
- spi_xfer(spi, 2 * 8, &crc, NULL, 0);
- for (i = 0; i < CTOUT; i++) {
- spi_xfer(spi, 1 * 8, NULL, &r1, 0);
+ dm_spi_xfer(dev, 2 * 8, tok, NULL, 0);
+ dm_spi_xfer(dev, bsize * 8, buf, NULL, 0);
+ dm_spi_xfer(dev, 2 * 8, &crc, NULL, 0);
+ for (i = 0; i < CMD_TIMEOUT; i++) {
+ dm_spi_xfer(dev, 1 * 8, NULL, &r1, 0);
if ((r1 & 0x10) == 0) /* response token */
break;
}
- debug("%s:tok%d %x\n", __func__, i, r1);
+ debug("%s: data tok%d 0x%x\n", __func__, i, r1);
if (SPI_MMC_RESPONSE_CODE(r1) == SPI_RESPONSE_ACCEPTED) {
- for (i = 0; i < WTOUT; i++) { /* wait busy */
- spi_xfer(spi, 1 * 8, NULL, &r1, 0);
+ debug("%s: data accepted\n", __func__);
+ for (i = 0; i < WRITE_TIMEOUT; i++) { /* wait busy */
+ dm_spi_xfer(dev, 1 * 8, NULL, &r1, 0);
if (i && r1 == 0xff) {
r1 = 0;
break;
}
}
- if (i == WTOUT) {
- debug("%s:wtout %x\n", __func__, r1);
+ if (i == WRITE_TIMEOUT) {
+ debug("%s: data write timeout 0x%x\n",
+ __func__, r1);
r1 = R1_SPI_ERROR;
break;
}
} else {
- debug("%s: err %x\n", __func__, r1);
+ debug("%s: data error 0x%x\n", __func__, r1);
r1 = R1_SPI_COM_CRC;
break;
}
@@ -154,140 +228,208 @@
}
if (multi && bcnt == -1) { /* stop multi write */
tok[1] = SPI_TOKEN_STOP_TRAN;
- spi_xfer(spi, 2 * 8, tok, NULL, 0);
- for (i = 0; i < WTOUT; i++) { /* wait busy */
- spi_xfer(spi, 1 * 8, NULL, &r1, 0);
+ dm_spi_xfer(dev, 2 * 8, tok, NULL, 0);
+ for (i = 0; i < WRITE_TIMEOUT; i++) { /* wait busy */
+ dm_spi_xfer(dev, 1 * 8, NULL, &r1, 0);
if (i && r1 == 0xff) {
r1 = 0;
break;
}
}
- if (i == WTOUT) {
- debug("%s:wstop %x\n", __func__, r1);
+ if (i == WRITE_TIMEOUT) {
+ debug("%s: data write timeout 0x%x\n", __func__, r1);
r1 = R1_SPI_ERROR;
}
}
- return r1;
-}
-static int mmc_spi_request(struct mmc *mmc, struct mmc_cmd *cmd,
- struct mmc_data *data)
-{
- struct spi_slave *spi = mmc->priv;
- u8 r1;
- int i;
- int ret = 0;
- debug("%s:cmd%d %x %x\n", __func__,
- cmd->cmdidx, cmd->resp_type, cmd->cmdarg);
- spi_claim_bus(spi);
- spi_cs_activate(spi);
- r1 = mmc_spi_sendcmd(mmc, cmd->cmdidx, cmd->cmdarg);
- if (r1 == 0xff) { /* no response */
- ret = -ENOMEDIUM;
- goto done;
- } else if (r1 & R1_SPI_COM_CRC) {
+ if (r1 & R1_SPI_COM_CRC)
ret = -ECOMM;
- goto done;
- } else if (r1 & ~R1_SPI_IDLE) { /* other errors */
+ else if (r1) /* other errors */
ret = -ETIMEDOUT;
- goto done;
- } else if (cmd->resp_type == MMC_RSP_R2) {
- r1 = mmc_spi_readdata(mmc, cmd->response, 1, 16);
- for (i = 0; i < 4; i++)
- cmd->response[i] = be32_to_cpu(cmd->response[i]);
- debug("r128 %x %x %x %x\n", cmd->response[0], cmd->response[1],
- cmd->response[2], cmd->response[3]);
- } else if (!data) {
- switch (cmd->cmdidx) {
- case SD_CMD_APP_SEND_OP_COND:
- case MMC_CMD_SEND_OP_COND:
- cmd->response[0] = (r1 & R1_SPI_IDLE) ? 0 : OCR_BUSY;
- break;
- case SD_CMD_SEND_IF_COND:
- case MMC_CMD_SPI_READ_OCR:
- spi_xfer(spi, 4 * 8, NULL, cmd->response, 0);
- cmd->response[0] = be32_to_cpu(cmd->response[0]);
- debug("r32 %x\n", cmd->response[0]);
- break;
- case MMC_CMD_SEND_STATUS:
- spi_xfer(spi, 1 * 8, NULL, cmd->response, 0);
- cmd->response[0] = (cmd->response[0] & 0xff) ?
- MMC_STATUS_ERROR : MMC_STATUS_RDY_FOR_DATA;
- break;
- }
- } else {
- debug("%s:data %x %x %x\n", __func__,
- data->flags, data->blocks, data->blocksize);
- if (data->flags == MMC_DATA_READ)
- r1 = mmc_spi_readdata(mmc, data->dest,
- data->blocks, data->blocksize);
- else if (data->flags == MMC_DATA_WRITE)
- r1 = mmc_spi_writedata(mmc, data->src,
- data->blocks, data->blocksize,
- (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK));
- if (r1 & R1_SPI_COM_CRC)
- ret = -ECOMM;
- else if (r1) /* other errors */
- ret = -ETIMEDOUT;
- }
-done:
- spi_cs_deactivate(spi);
- spi_release_bus(spi);
+
return ret;
}
-static int mmc_spi_set_ios(struct mmc *mmc)
+static int dm_mmc_spi_set_ios(struct udevice *dev)
{
- struct spi_slave *spi = mmc->priv;
-
- debug("%s: clock %u\n", __func__, mmc->clock);
- if (mmc->clock)
- spi_set_speed(spi, mmc->clock);
return 0;
}
-static int mmc_spi_init_p(struct mmc *mmc)
+static int dm_mmc_spi_request(struct udevice *dev, struct mmc_cmd *cmd,
+ struct mmc_data *data)
{
- struct spi_slave *spi = mmc->priv;
- spi_set_speed(spi, MMC_SPI_MIN_CLOCK);
- spi_claim_bus(spi);
- /* cs deactivated for 100+ clock */
- spi_xfer(spi, 18 * 8, NULL, NULL, 0);
- spi_release_bus(spi);
- return 0;
-}
+ int i, multi, ret = 0;
+ u8 *resp = NULL;
+ u32 resp_size = 0;
+ bool resp_match = false;
+ u8 resp8 = 0, resp40[5] = { 0 }, resp_match_value = 0;
-static const struct mmc_ops mmc_spi_ops = {
- .send_cmd = mmc_spi_request,
- .set_ios = mmc_spi_set_ios,
- .init = mmc_spi_init_p,
-};
+ dm_spi_claim_bus(dev);
-static struct mmc_config mmc_spi_cfg = {
- .name = "MMC_SPI",
- .ops = &mmc_spi_ops,
- .host_caps = MMC_MODE_SPI,
- .voltages = MMC_SPI_VOLTAGE,
- .f_min = MMC_SPI_MIN_CLOCK,
- .part_type = PART_TYPE_DOS,
- .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
-};
+ for (i = 0; i < 4; i++)
+ cmd->response[i] = 0;
-struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode)
-{
- struct mmc *mmc;
- struct spi_slave *spi;
+ switch (cmd->cmdidx) {
+ case SD_CMD_APP_SEND_OP_COND:
+ case MMC_CMD_SEND_OP_COND:
+ resp = &resp8;
+ resp_size = sizeof(resp8);
+ cmd->cmdarg = 0x40000000;
+ break;
+ case SD_CMD_SEND_IF_COND:
+ resp = (u8 *)&resp40[0];
+ resp_size = sizeof(resp40);
+ resp_match = true;
+ resp_match_value = R1_SPI_IDLE;
+ break;
+ case MMC_CMD_SPI_READ_OCR:
+ resp = (u8 *)&resp40[0];
+ resp_size = sizeof(resp40);
+ break;
+ case MMC_CMD_SEND_STATUS:
+ case MMC_CMD_SET_BLOCKLEN:
+ case MMC_CMD_SPI_CRC_ON_OFF:
+ case MMC_CMD_STOP_TRANSMISSION:
+ resp = &resp8;
+ resp_size = sizeof(resp8);
+ resp_match = true;
+ resp_match_value = 0x0;
+ break;
+ case MMC_CMD_SEND_CSD:
+ case MMC_CMD_SEND_CID:
+ case MMC_CMD_READ_SINGLE_BLOCK:
+ case MMC_CMD_READ_MULTIPLE_BLOCK:
+ case MMC_CMD_WRITE_SINGLE_BLOCK:
+ case MMC_CMD_WRITE_MULTIPLE_BLOCK:
+ break;
+ default:
+ resp = &resp8;
+ resp_size = sizeof(resp8);
+ resp_match = true;
+ resp_match_value = R1_SPI_IDLE;
+ break;
+ };
- spi = spi_setup_slave(bus, cs, speed, mode);
- if (spi == NULL)
- return NULL;
+ ret = mmc_spi_sendcmd(dev, cmd->cmdidx, cmd->cmdarg, cmd->resp_type,
+ resp, resp_size, resp_match, resp_match_value);
+ if (ret)
+ goto done;
- mmc_spi_cfg.f_max = speed;
-
- mmc = mmc_create(&mmc_spi_cfg, spi);
- if (mmc == NULL) {
- spi_free_slave(spi);
- return NULL;
+ switch (cmd->cmdidx) {
+ case SD_CMD_APP_SEND_OP_COND:
+ case MMC_CMD_SEND_OP_COND:
+ cmd->response[0] = (resp8 & R1_SPI_IDLE) ? 0 : OCR_BUSY;
+ break;
+ case SD_CMD_SEND_IF_COND:
+ case MMC_CMD_SPI_READ_OCR:
+ cmd->response[0] = resp40[4];
+ cmd->response[0] |= (uint)resp40[3] << 8;
+ cmd->response[0] |= (uint)resp40[2] << 16;
+ cmd->response[0] |= (uint)resp40[1] << 24;
+ break;
+ case MMC_CMD_SEND_STATUS:
+ cmd->response[0] = (resp8 & 0xff) ?
+ MMC_STATUS_ERROR : MMC_STATUS_RDY_FOR_DATA;
+ break;
+ case MMC_CMD_SEND_CID:
+ case MMC_CMD_SEND_CSD:
+ ret = mmc_spi_readdata(dev, cmd->response, 1, 16);
+ if (ret)
+ return ret;
+ for (i = 0; i < 4; i++)
+ cmd->response[i] =
+ cpu_to_be32(cmd->response[i]);
+ break;
+ default:
+ cmd->response[0] = resp8;
+ break;
}
- return mmc;
+
+ debug("%s: cmd%d resp0=0x%x resp1=0x%x resp2=0x%x resp3=0x%x\n",
+ __func__, cmd->cmdidx, cmd->response[0], cmd->response[1],
+ cmd->response[2], cmd->response[3]);
+
+ if (data) {
+ debug("%s: data flags=0x%x blocks=%d block_size=%d\n",
+ __func__, data->flags, data->blocks, data->blocksize);
+ multi = (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK);
+ if (data->flags == MMC_DATA_READ)
+ ret = mmc_spi_readdata(dev, data->dest,
+ data->blocks, data->blocksize);
+ else if (data->flags == MMC_DATA_WRITE)
+ ret = mmc_spi_writedata(dev, data->src,
+ data->blocks, data->blocksize,
+ multi);
+ }
+
+done:
+ dm_spi_xfer(dev, 0, NULL, NULL, SPI_XFER_END);
+
+ dm_spi_release_bus(dev);
+
+ return ret;
}
+
+static int mmc_spi_probe(struct udevice *dev)
+{
+ struct mmc_spi_priv *priv = dev_get_priv(dev);
+ struct mmc_spi_plat *plat = dev_get_platdata(dev);
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ char *name;
+
+ priv->spi = dev_get_parent_priv(dev);
+ if (!priv->spi->max_hz)
+ priv->spi->max_hz = MMC_SPI_MAX_CLOCK;
+ priv->spi->speed = 0;
+ priv->spi->mode = SPI_MODE_0;
+ priv->spi->wordlen = 8;
+
+ name = malloc(strlen(dev->parent->name) + strlen(dev->name) + 4);
+ if (!name)
+ return -ENOMEM;
+ sprintf(name, "%s:%s", dev->parent->name, dev->name);
+
+ plat->cfg.name = name;
+ plat->cfg.host_caps = MMC_MODE_SPI;
+ plat->cfg.voltages = MMC_SPI_VOLTAGE;
+ plat->cfg.f_min = MMC_SPI_MIN_CLOCK;
+ plat->cfg.f_max = priv->spi->max_hz;
+ plat->cfg.part_type = PART_TYPE_DOS;
+ plat->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+
+ plat->mmc.cfg = &plat->cfg;
+ plat->mmc.priv = priv;
+ plat->mmc.dev = dev;
+
+ upriv->mmc = &plat->mmc;
+
+ return 0;
+}
+
+static int mmc_spi_bind(struct udevice *dev)
+{
+ struct mmc_spi_plat *plat = dev_get_platdata(dev);
+
+ return mmc_bind(dev, &plat->mmc, &plat->cfg);
+}
+
+static const struct dm_mmc_ops mmc_spi_ops = {
+ .send_cmd = dm_mmc_spi_request,
+ .set_ios = dm_mmc_spi_set_ios,
+};
+
+static const struct udevice_id dm_mmc_spi_match[] = {
+ { .compatible = "mmc-spi-slot" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(mmc_spi) = {
+ .name = "mmc_spi",
+ .id = UCLASS_MMC,
+ .of_match = dm_mmc_spi_match,
+ .ops = &mmc_spi_ops,
+ .probe = mmc_spi_probe,
+ .bind = mmc_spi_bind,
+ .platdata_auto_alloc_size = sizeof(struct mmc_spi_plat),
+ .priv_auto_alloc_size = sizeof(struct mmc_spi_priv),
+};
diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c
index c8c83c9..b52ff9f 100644
--- a/drivers/mmc/mmc_write.c
+++ b/drivers/mmc/mmc_write.c
@@ -79,7 +79,7 @@
u32 start_rem, blkcnt_rem;
struct mmc *mmc = find_mmc_device(dev_num);
lbaint_t blk = 0, blk_r = 0;
- int timeout = 1000;
+ int timeout_ms = 1000;
if (!mmc)
return -1;
@@ -119,7 +119,7 @@
blk += blk_r;
/* Waiting for the ready status */
- if (mmc_send_status(mmc, timeout))
+ if (mmc_poll_for_busy(mmc, timeout_ms))
return 0;
}
@@ -131,7 +131,7 @@
{
struct mmc_cmd cmd;
struct mmc_data data;
- int timeout = 1000;
+ int timeout_ms = 1000;
if ((start + blkcnt) > mmc_get_blk_desc(mmc)->lba) {
printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
@@ -177,7 +177,7 @@
}
/* Waiting for the ready status */
- if (mmc_send_status(mmc, timeout))
+ if (mmc_poll_for_busy(mmc, timeout_ms))
return 0;
return blkcnt;
diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c
index 51f9e0e..cae42ec 100644
--- a/drivers/mmc/msm_sdhci.c
+++ b/drivers/mmc/msm_sdhci.c
@@ -141,12 +141,12 @@
writel(caps, host->ioaddr + SDHCI_VENDOR_SPEC_CAPABILITIES0);
}
- ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
host->mmc = &plat->mmc;
+ host->mmc->dev = dev;
+ ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
if (ret)
return ret;
host->mmc->priv = &prv->host;
- host->mmc->dev = dev;
upriv->mmc = host->mmc;
return sdhci_probe(dev);
diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c
index e0ac3e9..f555357 100644
--- a/drivers/mmc/mtk-sd.c
+++ b/drivers/mmc/mtk-sd.c
@@ -13,6 +13,7 @@
#include <errno.h>
#include <malloc.h>
#include <stdbool.h>
+#include <watchdog.h>
#include <asm/gpio.h>
#include <dm/pinctrl.h>
#include <linux/bitops.h>
@@ -623,6 +624,8 @@
u32 size;
int ret;
+ WATCHDOG_RESET();
+
if (data->flags == MMC_DATA_WRITE)
host->last_data_write = 1;
@@ -1390,9 +1393,19 @@
.stop_clk_fix = true,
};
+static const struct msdc_compatible mt8183_compat = {
+ .clk_div_bits = 12,
+ .pad_tune0 = true,
+ .async_fifo = true,
+ .data_tune = true,
+ .busy_check = true,
+ .stop_clk_fix = true,
+};
+
static const struct udevice_id msdc_ids[] = {
{ .compatible = "mediatek,mt7623-mmc", .data = (ulong)&mt7623_compat },
{ .compatible = "mediatek,mt8516-mmc", .data = (ulong)&mt8516_compat },
+ { .compatible = "mediatek,mt8183-mmc", .data = (ulong)&mt8183_compat },
{}
};
diff --git a/drivers/mmc/mv_sdhci.c b/drivers/mmc/mv_sdhci.c
index bf26d2e..f5f3e43 100644
--- a/drivers/mmc/mv_sdhci.c
+++ b/drivers/mmc/mv_sdhci.c
@@ -114,6 +114,9 @@
host->name = MVSDH_NAME;
host->ioaddr = (void *)devfdt_get_addr(dev);
host->quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD;
+ host->mmc = &plat->mmc;
+ host->mmc->dev = dev;
+ host->mmc->priv = host;
ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
if (ret)
@@ -124,9 +127,6 @@
sdhci_mvebu_mbus_config(host->ioaddr);
}
- host->mmc = &plat->mmc;
- host->mmc->dev = dev;
- host->mmc->priv = host;
upriv->mmc = host->mmc;
return sdhci_probe(dev);
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index 133cdc1..bade129 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -430,8 +430,7 @@
writel(ac12, &mmc_base->ac12);
}
-#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
-static int omap_hsmmc_wait_dat0(struct udevice *dev, int state, int timeout)
+static int omap_hsmmc_wait_dat0(struct udevice *dev, int state, int timeout_us)
{
int ret = -ETIMEDOUT;
u32 con;
@@ -443,8 +442,8 @@
con = readl(&mmc_base->con);
writel(con | CON_CLKEXTFREE | CON_PADEN, &mmc_base->con);
- timeout = DIV_ROUND_UP(timeout, 10); /* check every 10 us. */
- while (timeout--) {
+ timeout_us = DIV_ROUND_UP(timeout_us, 10); /* check every 10 us. */
+ while (timeout_us--) {
dat0_high = !!(readl(&mmc_base->pstate) & PSTATE_DLEV_DAT0);
if (dat0_high == target_dat0_high) {
ret = 0;
@@ -456,7 +455,6 @@
return ret;
}
-#endif
#if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
#if CONFIG_IS_ENABLED(DM_REGULATOR)
@@ -775,14 +773,6 @@
return ret;
}
#endif
-
-static void omap_hsmmc_send_init_stream(struct udevice *dev)
-{
- struct omap_hsmmc_data *priv = dev_get_priv(dev);
- struct hsmmc *mmc_base = priv->base_addr;
-
- mmc_init_stream(mmc_base);
-}
#endif
static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd)
@@ -1065,18 +1055,17 @@
if (get_timer(0) - start > MAX_RETRY_MS) {
printf("%s: timedout waiting on cmd inhibit to clear\n",
__func__);
+ mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
+ mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
return -ETIMEDOUT;
}
}
writel(0xFFFFFFFF, &mmc_base->stat);
- start = get_timer(0);
- while (readl(&mmc_base->stat)) {
- if (get_timer(0) - start > MAX_RETRY_MS) {
- printf("%s: timedout waiting for STAT (%x) to clear\n",
- __func__, readl(&mmc_base->stat));
- return -ETIMEDOUT;
- }
+ if (readl(&mmc_base->stat)) {
+ mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
+ mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
}
+
/*
* CMDREG
* CMDIDX[13:8] : Command index
@@ -1522,10 +1511,7 @@
#ifdef MMC_SUPPORTS_TUNING
.execute_tuning = omap_hsmmc_execute_tuning,
#endif
- .send_init_stream = omap_hsmmc_send_init_stream,
-#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
.wait_dat0 = omap_hsmmc_wait_dat0,
-#endif
};
#else
static const struct mmc_ops omap_hsmmc_ops = {
diff --git a/drivers/mmc/pci_mmc.c b/drivers/mmc/pci_mmc.c
index 182d416..404264a 100644
--- a/drivers/mmc/pci_mmc.c
+++ b/drivers/mmc/pci_mmc.c
@@ -33,12 +33,12 @@
host->ioaddr = (void *)dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0,
PCI_REGION_MEM);
host->name = dev->name;
+ host->mmc = &plat->mmc;
+ host->mmc->dev = dev;
ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
if (ret)
return ret;
- host->mmc = &plat->mmc;
host->mmc->priv = &priv->host;
- host->mmc->dev = dev;
upriv->mmc = host->mmc;
return sdhci_probe(dev);
diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index 7c53aa2..0cb65b4 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -499,15 +499,16 @@
}
#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
-static int renesas_sdhi_wait_dat0(struct udevice *dev, int state, int timeout)
+static int renesas_sdhi_wait_dat0(struct udevice *dev, int state,
+ int timeout_us)
{
int ret = -ETIMEDOUT;
bool dat0_high;
bool target_dat0_high = !!state;
struct tmio_sd_priv *priv = dev_get_priv(dev);
- timeout = DIV_ROUND_UP(timeout, 10); /* check every 10 us. */
- while (timeout--) {
+ timeout_us = DIV_ROUND_UP(timeout_us, 10); /* check every 10 us. */
+ while (timeout_us--) {
dat0_high = !!(tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_DAT0);
if (dat0_high == target_dat0_high) {
ret = 0;
diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index b6df2a6..d771080 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -69,15 +69,15 @@
if (host->bus_width == 8)
host->host_caps |= MMC_MODE_8BIT;
- ret = sdhci_setup_cfg(&plat->cfg, host, 0, EMMC_MIN_FREQ);
-
host->mmc = &plat->mmc;
- if (ret)
- return ret;
host->mmc->priv = &prv->host;
host->mmc->dev = dev;
upriv->mmc = host->mmc;
+ ret = sdhci_setup_cfg(&plat->cfg, host, 0, EMMC_MIN_FREQ);
+ if (ret)
+ return ret;
+
return sdhci_probe(dev);
}
diff --git a/drivers/mmc/rpmb.c b/drivers/mmc/rpmb.c
index 908f192..33371fe 100644
--- a/drivers/mmc/rpmb.c
+++ b/drivers/mmc/rpmb.c
@@ -103,7 +103,7 @@
cmd.cmdidx = MMC_CMD_WRITE_MULTIPLE_BLOCK;
cmd.cmdarg = 0;
- cmd.resp_type = MMC_RSP_R1b;
+ cmd.resp_type = MMC_RSP_R1;
data.src = (const char *)s;
data.blocks = 1;
@@ -327,7 +327,7 @@
{
struct mmc_cmd cmd = {
.cmdidx = MMC_CMD_WRITE_MULTIPLE_BLOCK,
- .resp_type = MMC_RSP_R1b,
+ .resp_type = MMC_RSP_R1,
};
struct mmc_data data = {
.src = (const void *)frm,
diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c
index 9dd0b86..53efa96 100644
--- a/drivers/mmc/s5p_sdhci.c
+++ b/drivers/mmc/s5p_sdhci.c
@@ -204,13 +204,13 @@
if (ret)
return ret;
+ host->mmc = &plat->mmc;
+ host->mmc->dev = dev;
ret = sdhci_setup_cfg(&plat->cfg, host, 0, 400000);
if (ret)
return ret;
- host->mmc = &plat->mmc;
host->mmc->priv = host;
- host->mmc->dev = dev;
upriv->mmc = host->mmc;
return sdhci_probe(dev);
diff --git a/drivers/mmc/sdhci-cadence.c b/drivers/mmc/sdhci-cadence.c
index 4f9338f..4736263 100644
--- a/drivers/mmc/sdhci-cadence.c
+++ b/drivers/mmc/sdhci-cadence.c
@@ -269,12 +269,13 @@
if (ret)
return ret;
+ host->mmc = &plat->mmc;
+ host->mmc->dev = dev;
ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
if (ret)
return ret;
upriv->mmc = &plat->mmc;
- host->mmc = &plat->mmc;
host->mmc->priv = host;
return sdhci_probe(dev);
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index e2bb90a..fbc576f 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -8,10 +8,12 @@
*/
#include <common.h>
+#include <dm.h>
#include <errno.h>
#include <malloc.h>
#include <mmc.h>
#include <sdhci.h>
+#include <dm.h>
#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
@@ -408,7 +410,7 @@
return 0;
}
#endif
-static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
+int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
{
struct sdhci_host *host = mmc->priv;
unsigned int div, clk = 0, timeout;
@@ -532,6 +534,34 @@
sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
}
+void sdhci_set_uhs_timing(struct sdhci_host *host)
+{
+ struct mmc *mmc = (struct mmc *)host->mmc;
+ u32 reg;
+
+ reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ reg &= ~SDHCI_CTRL_UHS_MASK;
+
+ switch (mmc->selected_mode) {
+ case UHS_SDR50:
+ case MMC_HS_52:
+ reg |= SDHCI_CTRL_UHS_SDR50;
+ break;
+ case UHS_DDR50:
+ case MMC_DDR_52:
+ reg |= SDHCI_CTRL_UHS_DDR50;
+ break;
+ case UHS_SDR104:
+ case MMC_HS_200:
+ reg |= SDHCI_CTRL_UHS_SDR104;
+ break;
+ default:
+ reg |= SDHCI_CTRL_UHS_SDR12;
+ }
+
+ sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
+}
+
#ifdef CONFIG_DM_MMC
static int sdhci_set_ios(struct udevice *dev)
{
@@ -582,7 +612,7 @@
/* If available, call the driver specific "post" set_ios() function */
if (host->ops && host->ops->set_ios_post)
- host->ops->set_ios_post(host);
+ return host->ops->set_ios_post(host);
return 0;
}
@@ -590,6 +620,12 @@
static int sdhci_init(struct mmc *mmc)
{
struct sdhci_host *host = mmc->priv;
+#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_GPIO)
+ struct udevice *dev = mmc->dev;
+
+ gpio_request_by_name(dev, "cd-gpios", 0,
+ &host->cd_gpio, GPIOD_IS_IN);
+#endif
sdhci_reset(host, SDHCI_RESET_ALL);
@@ -624,9 +660,40 @@
return sdhci_init(mmc);
}
+int sdhci_get_cd(struct udevice *dev)
+{
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+ struct sdhci_host *host = mmc->priv;
+ int value;
+
+ /* If nonremovable, assume that the card is always present. */
+ if (mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE)
+ return 1;
+ /* If polling, assume that the card is always present. */
+ if (mmc->cfg->host_caps & MMC_CAP_NEEDS_POLL)
+ return 1;
+
+#if CONFIG_IS_ENABLED(DM_GPIO)
+ value = dm_gpio_get_value(&host->cd_gpio);
+ if (value >= 0) {
+ if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
+ return !value;
+ else
+ return value;
+ }
+#endif
+ value = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
+ SDHCI_CARD_PRESENT);
+ if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
+ return !value;
+ else
+ return value;
+}
+
const struct dm_mmc_ops sdhci_ops = {
.send_cmd = sdhci_send_command,
.set_ios = sdhci_set_ios,
+ .get_cd = sdhci_get_cd,
#ifdef MMC_SUPPORTS_TUNING
.execute_tuning = sdhci_execute_tuning,
#endif
@@ -643,8 +710,20 @@
u32 f_max, u32 f_min)
{
u32 caps, caps_1 = 0;
+#if CONFIG_IS_ENABLED(DM_MMC)
+ u64 dt_caps, dt_caps_mask;
+ dt_caps_mask = dev_read_u64_default(host->mmc->dev,
+ "sdhci-caps-mask", 0);
+ dt_caps = dev_read_u64_default(host->mmc->dev,
+ "sdhci-caps", 0);
+ caps = ~(u32)dt_caps_mask &
+ sdhci_readl(host, SDHCI_CAPABILITIES);
+ caps |= (u32)dt_caps;
+#else
caps = sdhci_readl(host, SDHCI_CAPABILITIES);
+#endif
+ debug("%s, caps: 0x%x\n", __func__, caps);
#ifdef CONFIG_MMC_SDHCI_SDMA
if (!(caps & SDHCI_CAN_DO_SDMA)) {
@@ -684,7 +763,14 @@
/* Check whether the clock multiplier is supported or not */
if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
+#if CONFIG_IS_ENABLED(DM_MMC)
+ caps_1 = ~(u32)(dt_caps_mask >> 32) &
+ sdhci_readl(host, SDHCI_CAPABILITIES_1);
+ caps_1 |= (u32)(dt_caps >> 32);
+#else
caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
+#endif
+ debug("%s, caps_1: 0x%x\n", __func__, caps_1);
host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
SDHCI_CLOCK_MUL_SHIFT;
}
@@ -741,9 +827,6 @@
cfg->host_caps &= ~MMC_MODE_HS_52MHz;
}
- if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
- caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
-
if (!(cfg->voltages & MMC_VDD_165_195) ||
(host->quirks & SDHCI_QUIRK_NO_1_8_V))
caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
diff --git a/drivers/mmc/sti_sdhci.c b/drivers/mmc/sti_sdhci.c
index 8ed47e1..d6c75ea 100644
--- a/drivers/mmc/sti_sdhci.c
+++ b/drivers/mmc/sti_sdhci.c
@@ -97,14 +97,14 @@
SDHCI_QUIRK_NO_HISPD_BIT;
host->host_caps = MMC_MODE_DDR_52MHz;
+ host->mmc = &plat->mmc;
+ host->mmc->dev = dev;
+ host->mmc->priv = host;
ret = sdhci_setup_cfg(&plat->cfg, host, 50000000, 400000);
if (ret)
return ret;
- host->mmc = &plat->mmc;
- host->mmc->priv = host;
- host->mmc->dev = dev;
upriv->mmc = host->mmc;
return sdhci_probe(dev);
diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c
index ed31ca1..32434a4 100644
--- a/drivers/mmc/stm32_sdmmc2.c
+++ b/drivers/mmc/stm32_sdmmc2.c
@@ -14,6 +14,7 @@
#include <asm/io.h>
#include <asm/gpio.h>
#include <linux/iopoll.h>
+#include <watchdog.h>
struct stm32_sdmmc2_plat {
struct mmc_config cfg;
@@ -190,7 +191,7 @@
#define SDMMC_IDMACTRL_IDMAEN BIT(0)
#define SDMMC_CMD_TIMEOUT 0xFFFFFFFF
-#define SDMMC_BUSYD0END_TIMEOUT_US 1000000
+#define SDMMC_BUSYD0END_TIMEOUT_US 2000000
static void stm32_sdmmc2_start_data(struct stm32_sdmmc2_priv *priv,
struct mmc_data *data,
@@ -432,6 +433,8 @@
u32 cmdat = data ? SDMMC_CMD_CMDTRANS : 0;
int ret, retry = 3;
+ WATCHDOG_RESET();
+
retry_cmd:
ctx.data_length = 0;
ctx.dpsm_abort = false;
@@ -669,6 +672,7 @@
switch (dev_read_u32_default(dev, "bus-width", 1)) {
case 8:
cfg->host_caps |= MMC_MODE_8BIT;
+ /* fall through */
case 4:
cfg->host_caps |= MMC_MODE_4BIT;
break;
@@ -692,7 +696,7 @@
return ret;
}
-int stm32_sdmmc_bind(struct udevice *dev)
+static int stm32_sdmmc_bind(struct udevice *dev)
{
struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
diff --git a/drivers/mmc/tangier_sdhci.c b/drivers/mmc/tangier_sdhci.c
index 4c33356..0d6e5d6 100644
--- a/drivers/mmc/tangier_sdhci.c
+++ b/drivers/mmc/tangier_sdhci.c
@@ -51,13 +51,14 @@
/* MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195 */
host->voltages = MMC_VDD_165_195;
+ host->mmc = &plat->mmc;
+ host->mmc->dev = dev;
ret = sdhci_setup_cfg(&plat->cfg, host, SDHCI_TANGIER_FMAX,
SDHCI_TANGIER_FMIN);
if (ret)
return ret;
upriv->mmc = &plat->mmc;
- host->mmc = &plat->mmc;
host->mmc->priv = host;
return sdhci_probe(dev);
diff --git a/drivers/mmc/xenon_sdhci.c b/drivers/mmc/xenon_sdhci.c
index b576511..829b756 100644
--- a/drivers/mmc/xenon_sdhci.c
+++ b/drivers/mmc/xenon_sdhci.c
@@ -326,7 +326,7 @@
}
/* Platform specific function for post set_ios configuration */
-static void xenon_sdhci_set_ios_post(struct sdhci_host *host)
+static int xenon_sdhci_set_ios_post(struct sdhci_host *host)
{
struct xenon_sdhci_priv *priv = host->mmc->priv;
uint speed = host->mmc->tran_speed;
@@ -364,6 +364,8 @@
/* Re-init the PHY */
xenon_mmc_phy_set(host);
+
+ return 0;
}
/* Install a driver specific handler for post set_ios configuration */
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 0802378..3225a7a 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -48,11 +48,6 @@
[MMC_HS_200] = MMC_HS200_BUS_SPEED,
};
-#define SDHCI_HOST_CTRL2 0x3E
-#define SDHCI_CTRL2_MODE_MASK 0x7
-#define SDHCI_18V_SIGNAL 0x8
-#define SDHCI_CTRL_EXEC_TUNING 0x0040
-#define SDHCI_CTRL_TUNED_CLK 0x80
#define SDHCI_TUNING_LOOP_COUNT 40
static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 deviceid)
@@ -99,9 +94,9 @@
host = priv->host;
deviceid = priv->deviceid;
- ctrl = sdhci_readw(host, SDHCI_HOST_CTRL2);
+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
ctrl |= SDHCI_CTRL_EXEC_TUNING;
- sdhci_writew(host, ctrl, SDHCI_HOST_CTRL2);
+ sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
mdelay(1);
@@ -133,7 +128,7 @@
sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
mmc_send_cmd(mmc, &cmd, NULL);
- ctrl = sdhci_readw(host, SDHCI_HOST_CTRL2);
+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
udelay(1);
@@ -142,7 +137,7 @@
if (tuning_loop_counter < 0) {
ctrl &= ~SDHCI_CTRL_TUNED_CLK;
- sdhci_writel(host, ctrl, SDHCI_HOST_CTRL2);
+ sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2);
}
if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
@@ -184,36 +179,14 @@
return;
if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
- reg = sdhci_readw(host, SDHCI_HOST_CTRL2);
- reg |= SDHCI_18V_SIGNAL;
- sdhci_writew(host, reg, SDHCI_HOST_CTRL2);
+ reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ reg |= SDHCI_CTRL_VDD_180;
+ sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
}
if (mmc->selected_mode > SD_HS &&
- mmc->selected_mode <= UHS_DDR50) {
- reg = sdhci_readw(host, SDHCI_HOST_CTRL2);
- reg &= ~SDHCI_CTRL2_MODE_MASK;
- switch (mmc->selected_mode) {
- case UHS_SDR12:
- reg |= UHS_SDR12_BUS_SPEED;
- break;
- case UHS_SDR25:
- reg |= UHS_SDR25_BUS_SPEED;
- break;
- case UHS_SDR50:
- reg |= UHS_SDR50_BUS_SPEED;
- break;
- case UHS_SDR104:
- reg |= UHS_SDR104_BUS_SPEED;
- break;
- case UHS_DDR50:
- reg |= UHS_DDR50_BUS_SPEED;
- break;
- default:
- break;
- }
- sdhci_writew(host, reg, SDHCI_HOST_CTRL2);
- }
+ mmc->selected_mode <= UHS_DDR50)
+ sdhci_set_uhs_timing(host);
}
#endif
@@ -269,13 +242,14 @@
host->max_clk = clock;
+ host->mmc = &plat->mmc;
+ host->mmc->dev = dev;
+ host->mmc->priv = host;
+
ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max,
CONFIG_ZYNQ_SDHCI_MIN_FREQ);
- host->mmc = &plat->mmc;
if (ret)
return ret;
- host->mmc->priv = host;
- host->mmc->dev = dev;
upriv->mmc = host->mmc;
return sdhci_probe(dev);
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index 6b97e14..c59254c 100644
--- a/drivers/mtd/cfi_flash.c
+++ b/drivers/mtd/cfi_flash.c
@@ -19,13 +19,14 @@
#include <common.h>
#include <console.h>
#include <dm.h>
+#include <env.h>
#include <errno.h>
#include <fdt_support.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/byteorder.h>
#include <asm/unaligned.h>
-#include <environment.h>
+#include <env_internal.h>
#include <mtd/cfi_flash.h>
#include <watchdog.h>
diff --git a/drivers/mtd/jedec_flash.c b/drivers/mtd/jedec_flash.c
index a3540c1..f59b2bc 100644
--- a/drivers/mtd/jedec_flash.c
+++ b/drivers/mtd/jedec_flash.c
@@ -15,7 +15,6 @@
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/byteorder.h>
-#include <environment.h>
#define P_ID_AMD_STD CFI_CMDSET_AMD_LEGACY
diff --git a/drivers/mtd/mtd_uboot.c b/drivers/mtd/mtd_uboot.c
index 0a41ed4..55742275 100644
--- a/drivers/mtd/mtd_uboot.c
+++ b/drivers/mtd/mtd_uboot.c
@@ -4,6 +4,7 @@
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*/
#include <common.h>
+#include <env.h>
#include <dm/device.h>
#include <dm/uclass-internal.h>
#include <jffs2/jffs2.h> /* LEGACY */
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index f86035b..a129f44 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -15,6 +15,11 @@
Omit standard ECC layouts to safe space. Select this if your driver
is known to provide its own ECC layout.
+config SYS_NAND_USE_FLASH_BBT
+ bool "Enable BBT (Bad Block Table) support"
+ help
+ Enable the BBT (Bad Block Table) usage.
+
config NAND_ATMEL
bool "Support Atmel NAND controller"
imply SYS_NAND_USE_FLASH_BBT
diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/davinci_nand.c
index cfa9b53..724bbee 100644
--- a/drivers/mtd/nand/raw/davinci_nand.c
+++ b/drivers/mtd/nand/raw/davinci_nand.c
@@ -31,6 +31,7 @@
#include <common.h>
#include <asm/io.h>
#include <nand.h>
+#include <dm/uclass.h>
#include <asm/ti-common/davinci_nand.h>
/* Definitions for 4-bit hardware ECC */
@@ -730,7 +731,7 @@
return __raw_readl(&davinci_emif_regs->nandfsr) & 0x1;
}
-void davinci_nand_init(struct nand_chip *nand)
+static void davinci_nand_init(struct nand_chip *nand)
{
#if defined CONFIG_KEYSTONE_RBL_NAND
int i;
@@ -738,8 +739,8 @@
layout = &nand_keystone_rbl_4bit_layout_oobfirst;
layout->oobavail = 0;
- for (i = 0; layout->oobfree[i].length &&
- i < ARRAY_SIZE(layout->oobfree); i++)
+ for (i = 0; i < ARRAY_SIZE(layout->oobfree) &&
+ layout->oobfree[i].length; i++)
layout->oobavail += layout->oobfree[i].length;
nand->write_page = nand_davinci_write_page;
@@ -785,10 +786,53 @@
nand->dev_ready = nand_davinci_dev_ready;
}
-int board_nand_init(struct nand_chip *chip) __attribute__((weak));
+#ifdef CONFIG_SYS_NAND_SELF_INIT
+static int davinci_nand_probe(struct udevice *dev)
+{
+ struct nand_chip *nand = dev_get_priv(dev);
+ struct mtd_info *mtd = nand_to_mtd(nand);
+ int ret;
+ nand->IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
+ nand->IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
+
+ davinci_nand_init(nand);
+
+ ret = nand_scan(mtd, CONFIG_SYS_NAND_MAX_CHIPS);
+ if (ret)
+ return ret;
+
+ return nand_register(0, mtd);
+}
+
+static const struct udevice_id davinci_nand_ids[] = {
+ { .compatible = "ti,davinci-nand" },
+ { }
+};
+
+U_BOOT_DRIVER(davinci_nand) = {
+ .name = "davinci-nand",
+ .id = UCLASS_MTD,
+ .of_match = davinci_nand_ids,
+ .probe = davinci_nand_probe,
+ .priv_auto_alloc_size = sizeof(struct nand_chip),
+};
+
+void board_nand_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MTD,
+ DM_GET_DRIVER(davinci_nand), &dev);
+ if (ret && ret != -ENODEV)
+ pr_err("Failed to initialize %s: %d\n", dev->name, ret);
+}
+#else
+int board_nand_init(struct nand_chip *chip) __attribute__((weak));
int board_nand_init(struct nand_chip *chip)
{
davinci_nand_init(chip);
return 0;
}
+#endif /* CONFIG_SYS_NAND_SELF_INIT */
diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c
index b93d77a..a41b962 100644
--- a/drivers/mtd/nand/raw/mxs_nand.c
+++ b/drivers/mtd/nand/raw/mxs_nand.c
@@ -25,7 +25,7 @@
#include <asm/mach-imx/regs-bch.h>
#include <asm/mach-imx/regs-gpmi.h>
#include <asm/arch/sys_proto.h>
-#include "mxs_nand.h"
+#include <mxs_nand.h>
#define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
diff --git a/drivers/mtd/nand/raw/mxs_nand_dt.c b/drivers/mtd/nand/raw/mxs_nand_dt.c
index 44dec5d..8ad7d61 100644
--- a/drivers/mtd/nand/raw/mxs_nand_dt.c
+++ b/drivers/mtd/nand/raw/mxs_nand_dt.c
@@ -15,7 +15,7 @@
#include <linux/ioport.h>
#include <linux/printk.h>
-#include "mxs_nand.h"
+#include <mxs_nand.h>
struct mxs_nand_dt_data {
unsigned int max_ecc_strength_supported;
diff --git a/drivers/mtd/nand/raw/mxs_nand_spl.c b/drivers/mtd/nand/raw/mxs_nand_spl.c
index ee7d9cb..975a91a 100644
--- a/drivers/mtd/nand/raw/mxs_nand_spl.c
+++ b/drivers/mtd/nand/raw/mxs_nand_spl.c
@@ -6,7 +6,7 @@
#include <common.h>
#include <nand.h>
#include <malloc.h>
-#include "mxs_nand.h"
+#include <mxs_nand.h>
static struct mtd_info *mtd;
static struct nand_chip nand_chip;
diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c
index 2bb749d..f3179cc 100644
--- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c
+++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c
@@ -627,21 +627,16 @@
struct stm32_fmc2_timings *tims = &nand->timings;
unsigned long hclk = clk_get_rate(&fmc2->clk);
unsigned long hclkp = FMC2_NSEC_PER_SEC / (hclk / 1000);
- int tar, tclr, thiz, twait, tset_mem, tset_att, thold_mem, thold_att;
+ unsigned long timing, tar, tclr, thiz, twait;
+ unsigned long tset_mem, tset_att, thold_mem, thold_att;
- tar = hclkp;
- if (tar < sdrt->tAR_min)
- tar = sdrt->tAR_min;
- tims->tar = DIV_ROUND_UP(tar, hclkp) - 1;
- if (tims->tar > FMC2_PCR_TIMING_MASK)
- tims->tar = FMC2_PCR_TIMING_MASK;
+ tar = max_t(unsigned long, hclkp, sdrt->tAR_min);
+ timing = DIV_ROUND_UP(tar, hclkp) - 1;
+ tims->tar = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK);
- tclr = hclkp;
- if (tclr < sdrt->tCLR_min)
- tclr = sdrt->tCLR_min;
- tims->tclr = DIV_ROUND_UP(tclr, hclkp) - 1;
- if (tims->tclr > FMC2_PCR_TIMING_MASK)
- tims->tclr = FMC2_PCR_TIMING_MASK;
+ tclr = max_t(unsigned long, hclkp, sdrt->tCLR_min);
+ timing = DIV_ROUND_UP(tclr, hclkp) - 1;
+ tims->tclr = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK);
tims->thiz = FMC2_THIZ;
thiz = (tims->thiz + 1) * hclkp;
@@ -651,18 +646,11 @@
* tWAIT > tWP
* tWAIT > tREA + tIO
*/
- twait = hclkp;
- if (twait < sdrt->tRP_min)
- twait = sdrt->tRP_min;
- if (twait < sdrt->tWP_min)
- twait = sdrt->tWP_min;
- if (twait < sdrt->tREA_max + FMC2_TIO)
- twait = sdrt->tREA_max + FMC2_TIO;
- tims->twait = DIV_ROUND_UP(twait, hclkp);
- if (tims->twait == 0)
- tims->twait = 1;
- else if (tims->twait > FMC2_PMEM_PATT_TIMING_MASK)
- tims->twait = FMC2_PMEM_PATT_TIMING_MASK;
+ twait = max_t(unsigned long, hclkp, sdrt->tRP_min);
+ twait = max_t(unsigned long, twait, sdrt->tWP_min);
+ twait = max_t(unsigned long, twait, sdrt->tREA_max + FMC2_TIO);
+ timing = DIV_ROUND_UP(twait, hclkp);
+ tims->twait = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
/*
* tSETUP_MEM > tCS - tWAIT
@@ -677,20 +665,15 @@
if (twait > thiz && (sdrt->tDS_min > twait - thiz) &&
(tset_mem < sdrt->tDS_min - (twait - thiz)))
tset_mem = sdrt->tDS_min - (twait - thiz);
- tims->tset_mem = DIV_ROUND_UP(tset_mem, hclkp);
- if (tims->tset_mem == 0)
- tims->tset_mem = 1;
- else if (tims->tset_mem > FMC2_PMEM_PATT_TIMING_MASK)
- tims->tset_mem = FMC2_PMEM_PATT_TIMING_MASK;
+ timing = DIV_ROUND_UP(tset_mem, hclkp);
+ tims->tset_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
/*
* tHOLD_MEM > tCH
* tHOLD_MEM > tREH - tSETUP_MEM
* tHOLD_MEM > max(tRC, tWC) - (tSETUP_MEM + tWAIT)
*/
- thold_mem = hclkp;
- if (thold_mem < sdrt->tCH_min)
- thold_mem = sdrt->tCH_min;
+ thold_mem = max_t(unsigned long, hclkp, sdrt->tCH_min);
if (sdrt->tREH_min > tset_mem &&
(thold_mem < sdrt->tREH_min - tset_mem))
thold_mem = sdrt->tREH_min - tset_mem;
@@ -700,11 +683,8 @@
if ((sdrt->tWC_min > tset_mem + twait) &&
(thold_mem < sdrt->tWC_min - (tset_mem + twait)))
thold_mem = sdrt->tWC_min - (tset_mem + twait);
- tims->thold_mem = DIV_ROUND_UP(thold_mem, hclkp);
- if (tims->thold_mem == 0)
- tims->thold_mem = 1;
- else if (tims->thold_mem > FMC2_PMEM_PATT_TIMING_MASK)
- tims->thold_mem = FMC2_PMEM_PATT_TIMING_MASK;
+ timing = DIV_ROUND_UP(thold_mem, hclkp);
+ tims->thold_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
/*
* tSETUP_ATT > tCS - tWAIT
@@ -726,11 +706,8 @@
if (twait > thiz && (sdrt->tDS_min > twait - thiz) &&
(tset_att < sdrt->tDS_min - (twait - thiz)))
tset_att = sdrt->tDS_min - (twait - thiz);
- tims->tset_att = DIV_ROUND_UP(tset_att, hclkp);
- if (tims->tset_att == 0)
- tims->tset_att = 1;
- else if (tims->tset_att > FMC2_PMEM_PATT_TIMING_MASK)
- tims->tset_att = FMC2_PMEM_PATT_TIMING_MASK;
+ timing = DIV_ROUND_UP(tset_att, hclkp);
+ tims->tset_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
/*
* tHOLD_ATT > tALH
@@ -745,17 +722,11 @@
* tHOLD_ATT > tRC - (tSETUP_ATT + tWAIT)
* tHOLD_ATT > tWC - (tSETUP_ATT + tWAIT)
*/
- thold_att = hclkp;
- if (thold_att < sdrt->tALH_min)
- thold_att = sdrt->tALH_min;
- if (thold_att < sdrt->tCH_min)
- thold_att = sdrt->tCH_min;
- if (thold_att < sdrt->tCLH_min)
- thold_att = sdrt->tCLH_min;
- if (thold_att < sdrt->tCOH_min)
- thold_att = sdrt->tCOH_min;
- if (thold_att < sdrt->tDH_min)
- thold_att = sdrt->tDH_min;
+ thold_att = max_t(unsigned long, hclkp, sdrt->tALH_min);
+ thold_att = max_t(unsigned long, thold_att, sdrt->tCH_min);
+ thold_att = max_t(unsigned long, thold_att, sdrt->tCLH_min);
+ thold_att = max_t(unsigned long, thold_att, sdrt->tCOH_min);
+ thold_att = max_t(unsigned long, thold_att, sdrt->tDH_min);
if ((sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC > tset_mem) &&
(thold_att < sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem))
thold_att = sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem;
@@ -774,11 +745,8 @@
if ((sdrt->tWC_min > tset_att + twait) &&
(thold_att < sdrt->tWC_min - (tset_att + twait)))
thold_att = sdrt->tWC_min - (tset_att + twait);
- tims->thold_att = DIV_ROUND_UP(thold_att, hclkp);
- if (tims->thold_att == 0)
- tims->thold_att = 1;
- else if (tims->thold_att > FMC2_PMEM_PATT_TIMING_MASK)
- tims->thold_att = FMC2_PMEM_PATT_TIMING_MASK;
+ timing = DIV_ROUND_UP(thold_att, hclkp);
+ tims->thold_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
}
static int stm32_fmc2_setup_interface(struct mtd_info *mtd, int chipnr,
@@ -932,7 +900,8 @@
struct nand_ecclayout *ecclayout;
struct resource resource;
struct reset_ctl reset;
- int oob_index, chip_cs, mem_region, ret, i;
+ int oob_index, chip_cs, mem_region, ret;
+ unsigned int i;
spin_lock_init(&fmc2->controller.lock);
init_waitqueue_head(&fmc2->controller.wq);
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index f99f6cb..20db101 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -18,6 +18,6 @@
endif
obj-$(CONFIG_SPI_FLASH) += spi-nor.o
-obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o sf.o
+obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o
obj-$(CONFIG_SPI_FLASH_MTD) += sf_mtd.o
obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
diff --git a/drivers/mtd/spi/sf.c b/drivers/mtd/spi/sf.c
deleted file mode 100644
index ee3cf8b..0000000
--- a/drivers/mtd/spi/sf.c
+++ /dev/null
@@ -1,53 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * SPI flash interface
- *
- * Copyright (C) 2008 Atmel Corporation
- * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
- */
-
-#include <common.h>
-#include <spi.h>
-
-static int spi_flash_read_write(struct spi_slave *spi,
- const u8 *cmd, size_t cmd_len,
- const u8 *data_out, u8 *data_in,
- size_t data_len)
-{
- unsigned long flags = SPI_XFER_BEGIN;
- int ret;
-
- if (data_len == 0)
- flags |= SPI_XFER_END;
-
- ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags);
- if (ret) {
- debug("SF: Failed to send command (%zu bytes): %d\n",
- cmd_len, ret);
- } else if (data_len != 0) {
- ret = spi_xfer(spi, data_len * 8, data_out, data_in,
- SPI_XFER_END);
- if (ret)
- debug("SF: Failed to transfer %zu bytes of data: %d\n",
- data_len, ret);
- }
-
- return ret;
-}
-
-int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd,
- size_t cmd_len, void *data, size_t data_len)
-{
- return spi_flash_read_write(spi, cmd, cmd_len, NULL, data, data_len);
-}
-
-int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len)
-{
- return spi_flash_cmd_read(spi, &cmd, 1, response, len);
-}
-
-int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len,
- const void *data, size_t data_len)
-{
- return spi_flash_read_write(spi, cmd, cmd_len, data, NULL, data_len);
-}
diff --git a/drivers/mtd/spi/sf_dataflash.c b/drivers/mtd/spi/sf_dataflash.c
index b6a2631..55fb4bd 100644
--- a/drivers/mtd/spi/sf_dataflash.c
+++ b/drivers/mtd/spi/sf_dataflash.c
@@ -76,12 +76,14 @@
static inline int dataflash_status(struct spi_slave *spi)
{
int ret;
+ u8 opcode = OP_READ_STATUS;
u8 status;
+
/*
* NOTE: at45db321c over 25 MHz wants to write
* a dummy byte after the opcode...
*/
- ret = spi_flash_cmd(spi, OP_READ_STATUS, &status, 1);
+ ret = spi_write_then_read(spi, &opcode, 1, NULL, &status, 1);
return ret ? -EIO : status;
}
@@ -173,7 +175,7 @@
command[0], command[1], command[2], command[3],
pageaddr);
- status = spi_flash_cmd_write(spi, command, 4, NULL, 0);
+ status = spi_write_then_read(spi, command, 4, NULL, NULL, 0);
if (status < 0) {
debug("%s: erase send command error!\n", dev->name);
return -EIO;
@@ -248,7 +250,7 @@
command[3] = (uint8_t)(addr >> 0);
/* plus 4 "don't care" bytes, command len: 4 + 4 "don't care" bytes */
- status = spi_flash_cmd_read(spi, command, 8, buf, len);
+ status = spi_write_then_read(spi, command, 8, NULL, buf, len);
spi_release_bus(spi);
@@ -327,7 +329,8 @@
debug("TRANSFER: (%x) %x %x %x\n",
command[0], command[1], command[2], command[3]);
- status = spi_flash_cmd_write(spi, command, 4, NULL, 0);
+ status = spi_write_then_read(spi, command, 4,
+ NULL, NULL, 0);
if (status < 0) {
debug("%s: write(<pagesize) command error!\n",
dev->name);
@@ -352,8 +355,8 @@
debug("PROGRAM: (%x) %x %x %x\n",
command[0], command[1], command[2], command[3]);
- status = spi_flash_cmd_write(spi, command,
- 4, writebuf, writelen);
+ status = spi_write_then_read(spi, command, 4,
+ writebuf, NULL, writelen);
if (status < 0) {
debug("%s: write send command error!\n", dev->name);
return -EIO;
@@ -376,8 +379,8 @@
debug("COMPARE: (%x) %x %x %x\n",
command[0], command[1], command[2], command[3]);
- status = spi_flash_cmd_write(spi, command,
- 4, writebuf, writelen);
+ status = spi_write_then_read(spi, command, 4,
+ writebuf, NULL, writelen);
if (status < 0) {
debug("%s: write(compare) send command error!\n",
dev->name);
@@ -508,6 +511,7 @@
uint8_t id[5];
uint32_t jedec;
struct data_flash_info *info;
+ u8 opcode = CMD_READ_ID;
int status;
/*
@@ -519,7 +523,7 @@
* That's not an error; only rev C and newer chips handle it, and
* only Atmel sells these chips.
*/
- tmp = spi_flash_cmd(spi, CMD_READ_ID, id, sizeof(id));
+ tmp = spi_write_then_read(spi, &opcode, 1, NULL, id, sizeof(id));
if (tmp < 0) {
printf("dataflash: error %d reading JEDEC ID\n", tmp);
return ERR_PTR(tmp);
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index a6bf734..bb8c19a 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -65,6 +65,7 @@
#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
#define USE_CLSR BIT(14) /* use CLSR command */
+#define SPI_NOR_HAS_SST26LOCK BIT(15) /* Flash supports lock/unlock via BPR */
};
extern const struct flash_info spi_nor_ids[];
@@ -72,24 +73,6 @@
#define JEDEC_MFR(info) ((info)->id[0])
#define JEDEC_ID(info) (((info)->id[1]) << 8 | ((info)->id[2]))
-/* Send a single-byte command to the device and read the response */
-int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len);
-
-/*
- * Send a multi-byte command to the device and read the response. Used
- * for flash array reads, etc.
- */
-int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd,
- size_t cmd_len, void *data, size_t data_len);
-
-/*
- * Send a multi-byte command to the device followed by (optional)
- * data. Used for programming the flash array, etc.
- */
-int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len,
- const void *data, size_t data_len);
-
-
/* Get software write-protect value (BP bits) */
int spi_flash_cmd_get_sw_write_prot(struct spi_flash *flash);
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 1acff74..990e39d 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -945,6 +945,177 @@
}
#ifdef CONFIG_SPI_FLASH_SST
+/*
+ * sst26 flash series has its own block protection implementation:
+ * 4x - 8 KByte blocks - read & write protection bits - upper addresses
+ * 1x - 32 KByte blocks - write protection bits
+ * rest - 64 KByte blocks - write protection bits
+ * 1x - 32 KByte blocks - write protection bits
+ * 4x - 8 KByte blocks - read & write protection bits - lower addresses
+ *
+ * We'll support only per 64k lock/unlock so lower and upper 64 KByte region
+ * will be treated as single block.
+ */
+#define SST26_BPR_8K_NUM 4
+#define SST26_MAX_BPR_REG_LEN (18 + 1)
+#define SST26_BOUND_REG_SIZE ((32 + SST26_BPR_8K_NUM * 8) * SZ_1K)
+
+enum lock_ctl {
+ SST26_CTL_LOCK,
+ SST26_CTL_UNLOCK,
+ SST26_CTL_CHECK
+};
+
+static bool sst26_process_bpr(u32 bpr_size, u8 *cmd, u32 bit, enum lock_ctl ctl)
+{
+ switch (ctl) {
+ case SST26_CTL_LOCK:
+ cmd[bpr_size - (bit / 8) - 1] |= BIT(bit % 8);
+ break;
+ case SST26_CTL_UNLOCK:
+ cmd[bpr_size - (bit / 8) - 1] &= ~BIT(bit % 8);
+ break;
+ case SST26_CTL_CHECK:
+ return !!(cmd[bpr_size - (bit / 8) - 1] & BIT(bit % 8));
+ }
+
+ return false;
+}
+
+/*
+ * Lock, unlock or check lock status of the flash region of the flash (depending
+ * on the lock_ctl value)
+ */
+static int sst26_lock_ctl(struct spi_nor *nor, loff_t ofs, uint64_t len, enum lock_ctl ctl)
+{
+ struct mtd_info *mtd = &nor->mtd;
+ u32 i, bpr_ptr, rptr_64k, lptr_64k, bpr_size;
+ bool lower_64k = false, upper_64k = false;
+ u8 bpr_buff[SST26_MAX_BPR_REG_LEN] = {};
+ int ret;
+
+ /* Check length and offset for 64k alignment */
+ if ((ofs & (SZ_64K - 1)) || (len & (SZ_64K - 1))) {
+ dev_err(nor->dev, "length or offset is not 64KiB allighned\n");
+ return -EINVAL;
+ }
+
+ if (ofs + len > mtd->size) {
+ dev_err(nor->dev, "range is more than device size: %#llx + %#llx > %#llx\n",
+ ofs, len, mtd->size);
+ return -EINVAL;
+ }
+
+ /* SST26 family has only 16 Mbit, 32 Mbit and 64 Mbit IC */
+ if (mtd->size != SZ_2M &&
+ mtd->size != SZ_4M &&
+ mtd->size != SZ_8M)
+ return -EINVAL;
+
+ bpr_size = 2 + (mtd->size / SZ_64K / 8);
+
+ ret = nor->read_reg(nor, SPINOR_OP_READ_BPR, bpr_buff, bpr_size);
+ if (ret < 0) {
+ dev_err(nor->dev, "fail to read block-protection register\n");
+ return ret;
+ }
+
+ rptr_64k = min_t(u32, ofs + len, mtd->size - SST26_BOUND_REG_SIZE);
+ lptr_64k = max_t(u32, ofs, SST26_BOUND_REG_SIZE);
+
+ upper_64k = ((ofs + len) > (mtd->size - SST26_BOUND_REG_SIZE));
+ lower_64k = (ofs < SST26_BOUND_REG_SIZE);
+
+ /* Lower bits in block-protection register are about 64k region */
+ bpr_ptr = lptr_64k / SZ_64K - 1;
+
+ /* Process 64K blocks region */
+ while (lptr_64k < rptr_64k) {
+ if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
+ return EACCES;
+
+ bpr_ptr++;
+ lptr_64k += SZ_64K;
+ }
+
+ /* 32K and 8K region bits in BPR are after 64k region bits */
+ bpr_ptr = (mtd->size - 2 * SST26_BOUND_REG_SIZE) / SZ_64K;
+
+ /* Process lower 32K block region */
+ if (lower_64k)
+ if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
+ return EACCES;
+
+ bpr_ptr++;
+
+ /* Process upper 32K block region */
+ if (upper_64k)
+ if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
+ return EACCES;
+
+ bpr_ptr++;
+
+ /* Process lower 8K block regions */
+ for (i = 0; i < SST26_BPR_8K_NUM; i++) {
+ if (lower_64k)
+ if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
+ return EACCES;
+
+ /* In 8K area BPR has both read and write protection bits */
+ bpr_ptr += 2;
+ }
+
+ /* Process upper 8K block regions */
+ for (i = 0; i < SST26_BPR_8K_NUM; i++) {
+ if (upper_64k)
+ if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
+ return EACCES;
+
+ /* In 8K area BPR has both read and write protection bits */
+ bpr_ptr += 2;
+ }
+
+ /* If we check region status we don't need to write BPR back */
+ if (ctl == SST26_CTL_CHECK)
+ return 0;
+
+ ret = nor->write_reg(nor, SPINOR_OP_WRITE_BPR, bpr_buff, bpr_size);
+ if (ret < 0) {
+ dev_err(nor->dev, "fail to write block-protection register\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int sst26_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
+{
+ return sst26_lock_ctl(nor, ofs, len, SST26_CTL_UNLOCK);
+}
+
+static int sst26_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
+{
+ return sst26_lock_ctl(nor, ofs, len, SST26_CTL_LOCK);
+}
+
+/*
+ * Returns EACCES (positive value) if region is locked, 0 if region is unlocked,
+ * and negative on errors.
+ */
+static int sst26_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
+{
+ /*
+ * is_locked function is used for check before reading or erasing flash
+ * region, so offset and length might be not 64k allighned, so adjust
+ * them to be 64k allighned as sst26_lock_ctl works only with 64k
+ * allighned regions.
+ */
+ ofs -= ofs & (SZ_64K - 1);
+ len = len & (SZ_64K - 1) ? (len & ~(SZ_64K - 1)) + SZ_64K : len;
+
+ return sst26_lock_ctl(nor, ofs, len, SST26_CTL_CHECK);
+}
+
static int sst_write_byteprogram(struct spi_nor *nor, loff_t to, size_t len,
size_t *retlen, const u_char *buf)
{
@@ -2302,6 +2473,16 @@
#endif
#ifdef CONFIG_SPI_FLASH_SST
+ /*
+ * sst26 series block protection implementation differs from other
+ * series.
+ */
+ if (info->flags & SPI_NOR_HAS_SST26LOCK) {
+ nor->flash_lock = sst26_lock;
+ nor->flash_unlock = sst26_unlock;
+ nor->flash_is_locked = sst26_is_locked;
+ }
+
/* sst nor chips use AAI word program */
if (info->flags & SST_WRITE)
mtd->_write = sst_write;
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index ec92976..6996c0a 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -163,11 +163,15 @@
{ INFO("n25q128a13", 0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
{ INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+ { INFO6("mt25qu512a", 0x20bb20, 0x104400, 64 * 1024, 1024,
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
{ INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
{ INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
+ { INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_4B_OPCODES) },
+ { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, USE_FSR | SPI_NOR_4B_OPCODES) },
#endif
#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
/* Spansion/Cypress -- single (large) sector size only, at least
@@ -210,10 +214,10 @@
{ INFO("sst25wf040b", 0x621613, 0, 64 * 1024, 8, SECT_4K) },
{ INFO("sst25wf040", 0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
{ INFO("sst25wf080", 0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
- { INFO("sst26vf064b", 0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
- { INFO("sst26wf016", 0xbf2651, 0, 64 * 1024, 32, SECT_4K) },
- { INFO("sst26wf032", 0xbf2622, 0, 64 * 1024, 64, SECT_4K) },
- { INFO("sst26wf064", 0xbf2643, 0, 64 * 1024, 128, SECT_4K) },
+ { INFO("sst26vf064b", 0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_SST26LOCK | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("sst26wf016", 0xbf2651, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_HAS_SST26LOCK) },
+ { INFO("sst26wf032", 0xbf2622, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_SST26LOCK) },
+ { INFO("sst26wf064", 0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_SST26LOCK) },
#endif
#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
/* ST Microelectronics -- newer production may have feature updates */
diff --git a/drivers/mtd/ubi/Kconfig b/drivers/mtd/ubi/Kconfig
index 2b17eae..a78fd51 100644
--- a/drivers/mtd/ubi/Kconfig
+++ b/drivers/mtd/ubi/Kconfig
@@ -1,6 +1,6 @@
menu "UBI support"
-config CONFIG_UBI_SILENCE_MSG
+config UBI_SILENCE_MSG
bool "UBI silence verbose messages"
default ENV_IS_IN_UBI
help
diff --git a/drivers/mtd/ubi/io.c b/drivers/mtd/ubi/io.c
index 8ef7823..688fb50 100644
--- a/drivers/mtd/ubi/io.c
+++ b/drivers/mtd/ubi/io.c
@@ -1351,6 +1351,7 @@
ubi_err(ubi, "self-check failed for PEB %d:%d, len %d",
pnum, offset, len);
+#if !defined(CONFIG_UBI_SILENCE_MSG)
ubi_msg(ubi, "data differ at position %d", i);
ubi_msg(ubi, "hex dump of the original buffer from %d to %d",
i, i + dump_len);
@@ -1360,6 +1361,7 @@
i, i + dump_len);
print_hex_dump("", DUMP_PREFIX_OFFSET, 32, 1,
buf1 + i, dump_len, 1);
+#endif
dump_stack();
err = -EINVAL;
goto out_free;
diff --git a/drivers/mtd/ubispl/ubispl.c b/drivers/mtd/ubispl/ubispl.c
index eeb1cbe..3f3b9b4 100644
--- a/drivers/mtd/ubispl/ubispl.c
+++ b/drivers/mtd/ubispl/ubispl.c
@@ -45,6 +45,187 @@
return peb >= ubi->peb_count || peb < 0;
}
+#ifdef CONFIG_SPL_UBI_LOAD_BY_VOLNAME
+
+/**
+ * ubi_dump_vtbl_record - dump a &struct ubi_vtbl_record object.
+ * @r: the object to dump
+ * @idx: volume table index
+ */
+void ubi_dump_vtbl_record(const struct ubi_vtbl_record *r, int idx)
+{
+ int name_len = be16_to_cpu(r->name_len);
+
+ ubi_dbg("Volume table record %d dump: size: %d",
+ idx, sizeof(struct ubi_vtbl_record));
+ ubi_dbg("\treserved_pebs %d", be32_to_cpu(r->reserved_pebs));
+ ubi_dbg("\talignment %d", be32_to_cpu(r->alignment));
+ ubi_dbg("\tdata_pad %d", be32_to_cpu(r->data_pad));
+ ubi_dbg("\tvol_type %d", (int)r->vol_type);
+ ubi_dbg("\tupd_marker %d", (int)r->upd_marker);
+ ubi_dbg("\tname_len %d", name_len);
+
+ if (r->name[0] == '\0') {
+ ubi_dbg("\tname NULL");
+ return;
+ }
+
+ if (name_len <= UBI_VOL_NAME_MAX &&
+ strnlen(&r->name[0], name_len + 1) == name_len) {
+ ubi_dbg("\tname %s", &r->name[0]);
+ } else {
+ ubi_dbg("\t1st 5 characters of name: %c%c%c%c%c",
+ r->name[0], r->name[1], r->name[2], r->name[3],
+ r->name[4]);
+ }
+ ubi_dbg("\tcrc %#08x", be32_to_cpu(r->crc));
+}
+
+/* Empty volume table record */
+static struct ubi_vtbl_record empty_vtbl_record;
+
+/**
+ * vtbl_check - check if volume table is not corrupted and sensible.
+ * @ubi: UBI device description object
+ * @vtbl: volume table
+ *
+ * This function returns zero if @vtbl is all right, %1 if CRC is incorrect,
+ * and %-EINVAL if it contains inconsistent data.
+ */
+static int vtbl_check(struct ubi_scan_info *ubi,
+ struct ubi_vtbl_record *vtbl)
+{
+ int i, n, reserved_pebs, alignment, data_pad, vol_type, name_len;
+ int upd_marker, err;
+ uint32_t crc;
+ const char *name;
+
+ for (i = 0; i < UBI_SPL_VOL_IDS; i++) {
+ reserved_pebs = be32_to_cpu(vtbl[i].reserved_pebs);
+ alignment = be32_to_cpu(vtbl[i].alignment);
+ data_pad = be32_to_cpu(vtbl[i].data_pad);
+ upd_marker = vtbl[i].upd_marker;
+ vol_type = vtbl[i].vol_type;
+ name_len = be16_to_cpu(vtbl[i].name_len);
+ name = &vtbl[i].name[0];
+
+ crc = crc32(UBI_CRC32_INIT, &vtbl[i], UBI_VTBL_RECORD_SIZE_CRC);
+ if (be32_to_cpu(vtbl[i].crc) != crc) {
+ ubi_err("bad CRC at record %u: %#08x, not %#08x",
+ i, crc, be32_to_cpu(vtbl[i].crc));
+ ubi_dump_vtbl_record(&vtbl[i], i);
+ return 1;
+ }
+
+ if (reserved_pebs == 0) {
+ if (memcmp(&vtbl[i], &empty_vtbl_record,
+ UBI_VTBL_RECORD_SIZE)) {
+ err = 2;
+ goto bad;
+ }
+ continue;
+ }
+
+ if (reserved_pebs < 0 || alignment < 0 || data_pad < 0 ||
+ name_len < 0) {
+ err = 3;
+ goto bad;
+ }
+
+ if (alignment > ubi->leb_size || alignment == 0) {
+ err = 4;
+ goto bad;
+ }
+
+ n = alignment & (CONFIG_SPL_UBI_VID_OFFSET - 1);
+ if (alignment != 1 && n) {
+ err = 5;
+ goto bad;
+ }
+
+ n = ubi->leb_size % alignment;
+ if (data_pad != n) {
+ ubi_err("bad data_pad, has to be %d", n);
+ err = 6;
+ goto bad;
+ }
+
+ if (vol_type != UBI_VID_DYNAMIC && vol_type != UBI_VID_STATIC) {
+ err = 7;
+ goto bad;
+ }
+
+ if (upd_marker != 0 && upd_marker != 1) {
+ err = 8;
+ goto bad;
+ }
+
+ if (name_len > UBI_VOL_NAME_MAX) {
+ err = 10;
+ goto bad;
+ }
+
+ if (name[0] == '\0') {
+ err = 11;
+ goto bad;
+ }
+
+ if (name_len != strnlen(name, name_len + 1)) {
+ err = 12;
+ goto bad;
+ }
+
+ ubi_dump_vtbl_record(&vtbl[i], i);
+ }
+
+ /* Checks that all names are unique */
+ for (i = 0; i < UBI_SPL_VOL_IDS - 1; i++) {
+ for (n = i + 1; n < UBI_SPL_VOL_IDS; n++) {
+ int len1 = be16_to_cpu(vtbl[i].name_len);
+ int len2 = be16_to_cpu(vtbl[n].name_len);
+
+ if (len1 > 0 && len1 == len2 &&
+ !strncmp(vtbl[i].name, vtbl[n].name, len1)) {
+ ubi_err("volumes %d and %d have the same name \"%s\"",
+ i, n, vtbl[i].name);
+ ubi_dump_vtbl_record(&vtbl[i], i);
+ ubi_dump_vtbl_record(&vtbl[n], n);
+ return -EINVAL;
+ }
+ }
+ }
+
+ return 0;
+
+bad:
+ ubi_err("volume table check failed: record %d, error %d", i, err);
+ ubi_dump_vtbl_record(&vtbl[i], i);
+ return -EINVAL;
+}
+
+static int ubi_read_volume_table(struct ubi_scan_info *ubi, u32 pnum)
+{
+ int err = -EINVAL;
+
+ empty_vtbl_record.crc = cpu_to_be32(0xf116c36b);
+
+ err = ubi_io_read(ubi, &ubi->vtbl, pnum, ubi->leb_start,
+ sizeof(struct ubi_vtbl_record) * UBI_SPL_VOL_IDS);
+ if (err && err != UBI_IO_BITFLIPS) {
+ ubi_err("unable to read volume table");
+ goto out;
+ }
+
+ if (!vtbl_check(ubi, ubi->vtbl)) {
+ ubi->vtbl_valid = 1;
+ err = 0;
+ }
+out:
+ return err;
+}
+
+#endif /* CONFIG_SPL_UBI_LOAD_BY_VOLNAME */
+
static int ubi_io_read_vid_hdr(struct ubi_scan_info *ubi, int pnum,
struct ubi_vid_hdr *vh, int unused)
{
@@ -210,14 +391,23 @@
if (vol_id == UBI_FM_SB_VOLUME_ID)
return ubi->fm_enabled ? UBI_FASTMAP_ANCHOR : 0;
+#ifdef CONFIG_SPL_UBI_LOAD_BY_VOLNAME
+ /* If this is a UBI volume table, read it and return */
+ if (vol_id == UBI_LAYOUT_VOLUME_ID && !ubi->vtbl_valid) {
+ res = ubi_read_volume_table(ubi, pnum);
+ return res;
+ }
+#endif
+
/* We only care about static volumes with an id < UBI_SPL_VOL_IDS */
if (vol_id >= UBI_SPL_VOL_IDS || vh->vol_type != UBI_VID_STATIC)
return 0;
+#ifndef CONFIG_SPL_UBI_LOAD_BY_VOLNAME
/* We are only interested in the volumes to load */
if (!test_bit(vol_id, ubi->toload))
return 0;
-
+#endif
lnum = be32_to_cpu(vh->lnum);
return ubi_add_peb_to_vol(ubi, vh, vol_id, pnum, lnum);
}
@@ -232,13 +422,14 @@
ubi->fastmap_pebs++;
+#ifndef CONFIG_SPL_UBI_LOAD_BY_VOLNAME
if (vol_id >= UBI_SPL_VOL_IDS || vol_type != UBI_STATIC_VOLUME)
return 0;
/* We are only interested in the volumes to load */
if (!test_bit(vol_id, ubi->toload))
return 0;
-
+#endif
vh = ubi->blockinfo + pnum;
return ubi_scan_vid_hdr(ubi, vh, pnum);
@@ -892,6 +1083,10 @@
ubi->peb_count = info->peb_count;
ubi->peb_offset = info->peb_offset;
+#ifdef CONFIG_SPL_UBI_LOAD_BY_VOLNAME
+ ubi->vtbl_valid = 0;
+#endif
+
fsize = info->peb_size * info->peb_count;
ubi->fsize_mb = fsize >> 20;
@@ -910,7 +1105,23 @@
for (i = 0; i < nrvols; i++) {
struct ubispl_load *lv = lvols + i;
+#ifdef CONFIG_SPL_UBI_LOAD_BY_VOLNAME
+ if (lv->vol_id == -1) {
+ for (int j = 0; j < UBI_SPL_VOL_IDS; j++) {
+ int len = be16_to_cpu(ubi->vtbl[j].name_len);
+
+ if (strncmp(lv->name,
+ ubi->vtbl[j].name,
+ len) == 0) {
+ lv->vol_id = j;
+ break;
+ }
+ }
+ }
+ ubi_msg("Loading VolName %s (VolId #%d)", lv->name, lv->vol_id);
+#else
ubi_msg("Loading VolId #%d", lv->vol_id);
+#endif
res = ipl_load(ubi, lv->vol_id, lv->load_addr);
if (res < 0) {
if (fastmap) {
diff --git a/drivers/mtd/ubispl/ubispl.h b/drivers/mtd/ubispl/ubispl.h
index 9e40b46..b7cb7fc 100644
--- a/drivers/mtd/ubispl/ubispl.h
+++ b/drivers/mtd/ubispl/ubispl.h
@@ -77,6 +77,8 @@
* @blockinfo: The vid headers of the scanned blocks
* @volinfo: The volume information of the interesting (toload)
* volumes
+ * @vtbl_corrupted: Flag to indicate status of volume table
+ * @vtbl: Volume table
*
* @fm_buf: The large fastmap attach buffer
*/
@@ -112,6 +114,11 @@
struct ubi_vol_info volinfo[UBI_SPL_VOL_IDS];
struct ubi_vid_hdr blockinfo[CONFIG_SPL_UBI_MAX_PEBS];
+#ifdef CONFIG_SPL_UBI_LOAD_BY_VOLNAME
+ /* Volume table */
+ int vtbl_valid;
+ struct ubi_vtbl_record vtbl[UBI_SPL_VOL_IDS];
+#endif
/* The large buffer for the fastmap */
uint8_t fm_buf[UBI_FM_BUF_SIZE];
};
@@ -122,7 +129,7 @@
#define ubi_dbg(fmt, ...)
#endif
-#ifdef CONFIG_UBI_SILENCE_MSG
+#ifdef CONFIG_UBI_SPL_SILENCE_MSG
#define ubi_msg(fmt, ...)
#else
#define ubi_msg(fmt, ...) printf("UBI: " fmt "\n", ##__VA_ARGS__)
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index e6a4fdf..2ce3092 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -1,5 +1,6 @@
source "drivers/net/phy/Kconfig"
source "drivers/net/pfe_eth/Kconfig"
+source "drivers/net/fsl-mc/Kconfig"
config DM_ETH
bool "Enable Driver Model for Ethernet drivers"
@@ -11,6 +12,51 @@
This is currently implemented in net/eth-uclass.c
Look in include/net.h for details.
+config DM_MDIO
+ bool "Enable Driver Model for MDIO devices"
+ depends on DM_ETH && PHYLIB
+ help
+ Enable driver model for MDIO devices
+
+ Adds UCLASS_MDIO DM class supporting MDIO buses that are probed as
+ stand-alone devices. Useful in particular for systems that support
+ DM_ETH and have a stand-alone MDIO hardware block shared by multiple
+ Ethernet interfaces.
+ This is currently implemented in net/mdio-uclass.c
+ Look in include/miiphy.h for details.
+
+config DM_MDIO_MUX
+ bool "Enable Driver Model for MDIO MUX devices"
+ depends on DM_MDIO
+ help
+ Enable driver model for MDIO MUX devices
+
+ Adds UCLASS_MDIO_MUX DM class supporting MDIO MUXes. Useful for
+ systems that support DM_MDIO and integrate one or multiple muxes on
+ the MDIO bus.
+ This is currently implemented in net/mdio-mux-uclass.c
+ Look in include/miiphy.h for details.
+
+config MDIO_SANDBOX
+ depends on DM_MDIO && SANDBOX
+ default y
+ bool "Sandbox: Mocked MDIO driver"
+ help
+ This driver implements dummy read/write/reset MDIO functions mimicking
+ a bus with a single PHY.
+
+ This driver is used in for testing in test/dm/mdio.c
+
+config MDIO_MUX_SANDBOX
+ depends on DM_MDIO_MUX && MDIO_SANDBOX
+ default y
+ bool "Sandbox: Mocked MDIO-MUX driver"
+ help
+ This driver implements dummy select/deselect ops mimicking a MUX on
+ the MDIO bux. It uses mdio_sandbox driver as parent MDIO.
+
+ This driver is used for testing in test/dm/mdio.c
+
menuconfig NETDEVICES
bool "Network device support"
depends on NET
@@ -151,7 +197,7 @@
This driver is a bridge from the bottom of the network stack
in U-Boot to the RAW AF_PACKET API in Linux. This allows real
network traffic to be tested from within sandbox. See
- board/sandbox/README.sandbox for more details.
+ doc/arch/index.rst for more details.
config ETH_DESIGNWARE
bool "Synopsys Designware Ethernet MAC"
@@ -190,7 +236,7 @@
config FEC_MXC
bool "FEC Ethernet controller"
- depends on MX5 || MX6 || MX7 || IMX8 || VF610
+ depends on MX28 || MX5 || MX6 || MX7 || IMX8 || VF610
help
This driver supports the 10/100 Fast Ethernet controller for
NXP i.MX processors.
@@ -543,4 +589,29 @@
This driver supports HIGMACV300 Ethernet controller found on
HiSilicon SoCs.
+config FSL_ENETC
+ bool "NXP ENETC Ethernet controller"
+ depends on DM_PCI && DM_ETH && DM_MDIO
+ help
+ This driver supports the NXP ENETC Ethernet controller found on some
+ of the NXP SoCs.
+
+config MDIO_MUX_I2CREG
+ bool "MDIO MUX accessed as a register over I2C"
+ depends on DM_MDIO_MUX && DM_I2C
+ help
+ This driver is used for MDIO muxes driven by writing to a register of
+ an I2C chip. The board it was developed for uses a mux controlled by
+ on-board FPGA which in turn is accessed as a chip over I2C.
+
+config MVMDIO
+ bool "Marvell MDIO interface support"
+ depends on DM_MDIO
+ help
+ This driver supports the MDIO interface found in the network
+ interface units of the Marvell EBU SoCs (Kirkwood, Orion5x,
+ Dove, Armada 370, Armada XP, Armada 37xx and Armada7K/8K/8KP).
+
+ This driver is used by the MVPP2 and MVNETA drivers.
+
endif # NETDEVICES
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 8d02a37..3099183 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -37,9 +37,12 @@
obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o
obj-$(CONFIG_MACB) += macb.o
obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
+obj-$(CONFIG_MDIO_MUX_I2CREG) += mdio_mux_i2creg.o
+obj-$(CONFIG_MDIO_MUX_SANDBOX) += mdio_mux_sandbox.o
obj-$(CONFIG_MPC8XX_FEC) += mpc8xx_fec.o
obj-$(CONFIG_MT7628_ETH) += mt7628-eth.o
obj-$(CONFIG_MVGBE) += mvgbe.o
+obj-$(CONFIG_MVMDIO) += mvmdio.o
obj-$(CONFIG_MVNETA) += mvneta.o
obj-$(CONFIG_MVPP2) += mvpp2.o
obj-$(CONFIG_NATSEMI) += natsemi.o
@@ -77,3 +80,5 @@
obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o
obj-y += mscc_eswitch/
obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o
+obj-$(CONFIG_MDIO_SANDBOX) += mdio_sandbox.o
+obj-$(CONFIG_FSL_ENETC) += fsl_enetc.o fsl_enetc_mdio.o
diff --git a/drivers/net/dc2114x.c b/drivers/net/dc2114x.c
index e3c403c..43c2253 100644
--- a/drivers/net/dc2114x.c
+++ b/drivers/net/dc2114x.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
#include <common.h>
+#include <env.h>
#include <malloc.h>
#include <net.h>
#include <netdev.h>
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index 2c5d956..0031370 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -480,18 +480,16 @@
static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
{
struct phy_device *phydev;
- int mask = 0xffffffff, ret;
+ int phy_addr = -1, ret;
#ifdef CONFIG_PHY_ADDR
- mask = 1 << CONFIG_PHY_ADDR;
+ phy_addr = CONFIG_PHY_ADDR;
#endif
- phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
+ phydev = phy_connect(priv->bus, phy_addr, dev, priv->interface);
if (!phydev)
return -ENODEV;
- phy_connect_dev(phydev, dev);
-
phydev->supported &= PHY_GBIT_FEATURES;
if (priv->max_speed) {
ret = phy_set_supported(phydev, priv->max_speed);
@@ -677,10 +675,10 @@
struct dw_eth_dev *priv = dev_get_priv(dev);
u32 iobase = pdata->iobase;
ulong ioaddr;
- int ret;
+ int ret, err;
struct reset_ctl_bulk reset_bulk;
#ifdef CONFIG_CLK
- int i, err, clock_nb;
+ int i, clock_nb;
priv->clock_count = 0;
clock_nb = dev_count_phandle_with_args(dev, "clocks", "#clock-cells");
@@ -753,13 +751,23 @@
priv->interface = pdata->phy_interface;
priv->max_speed = pdata->max_speed;
- dw_mdio_init(dev->name, dev);
+ ret = dw_mdio_init(dev->name, dev);
+ if (ret) {
+ err = ret;
+ goto mdio_err;
+ }
priv->bus = miiphy_get_dev_by_name(dev->name);
ret = dw_phy_init(priv, dev);
debug("%s, ret=%d\n", __func__, ret);
+ if (!ret)
+ return 0;
- return ret;
+ /* continue here for cleanup if no PHY found */
+ err = ret;
+ mdio_unregister(priv->bus);
+ mdio_free(priv->bus);
+mdio_err:
#ifdef CONFIG_CLK
clk_err:
@@ -767,8 +775,8 @@
if (ret)
pr_err("failed to disable all clocks\n");
- return err;
#endif
+ return err;
}
static int designware_eth_remove(struct udevice *dev)
@@ -839,12 +847,12 @@
static const struct udevice_id designware_eth_ids[] = {
{ .compatible = "allwinner,sun7i-a20-gmac" },
- { .compatible = "altr,socfpga-stmmac" },
{ .compatible = "amlogic,meson6-dwmac" },
{ .compatible = "amlogic,meson-gx-dwmac" },
{ .compatible = "amlogic,meson-gxbb-dwmac" },
{ .compatible = "amlogic,meson-axg-dwmac" },
{ .compatible = "st,stm32-dwmac" },
+ { .compatible = "snps,arc-dwmac-3.70a" },
{ }
};
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 07b3667..4557093 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -621,7 +621,7 @@
return ret;
}
-void eqos_stop_clks_tegra186(struct udevice *dev)
+static void eqos_stop_clks_tegra186(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
@@ -636,7 +636,7 @@
debug("%s: OK\n", __func__);
}
-void eqos_stop_clks_stm32(struct udevice *dev)
+static void eqos_stop_clks_stm32(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
@@ -1290,7 +1290,7 @@
return ret;
}
-void eqos_stop(struct udevice *dev)
+static void eqos_stop(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
int i;
@@ -1344,7 +1344,7 @@
debug("%s: OK\n", __func__);
}
-int eqos_send(struct udevice *dev, void *packet, int length)
+static int eqos_send(struct udevice *dev, void *packet, int length)
{
struct eqos_priv *eqos = dev_get_priv(dev);
struct eqos_desc *tx_desc;
@@ -1385,7 +1385,7 @@
return -ETIMEDOUT;
}
-int eqos_recv(struct udevice *dev, int flags, uchar **packetp)
+static int eqos_recv(struct udevice *dev, int flags, uchar **packetp)
{
struct eqos_priv *eqos = dev_get_priv(dev);
struct eqos_desc *rx_desc;
@@ -1409,7 +1409,7 @@
return length;
}
-int eqos_free_pkt(struct udevice *dev, uchar *packet, int length)
+static int eqos_free_pkt(struct udevice *dev, uchar *packet, int length)
{
struct eqos_priv *eqos = dev_get_priv(dev);
uchar *packet_expected;
@@ -1591,8 +1591,8 @@
}
/* board-specific Ethernet Interface initializations. */
-__weak int board_interface_eth_init(int interface_type, bool eth_clk_sel_reg,
- bool eth_ref_clk_sel_reg)
+__weak int board_interface_eth_init(struct udevice *dev,
+ phy_interface_t interface_type)
{
return 0;
}
@@ -1602,8 +1602,6 @@
struct eqos_priv *eqos = dev_get_priv(dev);
int ret;
phy_interface_t interface;
- bool eth_clk_sel_reg = false;
- bool eth_ref_clk_sel_reg = false;
debug("%s(dev=%p):\n", __func__, dev);
@@ -1614,15 +1612,7 @@
return -EINVAL;
}
- /* Gigabit Ethernet 125MHz clock selection. */
- eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel");
-
- /* Ethernet 50Mhz RMII clock selection */
- eth_ref_clk_sel_reg =
- dev_read_bool(dev, "st,eth_ref_clk_sel");
-
- ret = board_interface_eth_init(interface, eth_clk_sel_reg,
- eth_ref_clk_sel_reg);
+ ret = board_interface_eth_init(dev, interface);
if (ret)
return -EINVAL;
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index d7c0809..080dbcf 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -9,7 +9,7 @@
#include <common.h>
#include <dm.h>
-#include <environment.h>
+#include <env.h>
#include <malloc.h>
#include <memalign.h>
#include <miiphy.h>
@@ -1485,6 +1485,7 @@
}
static const struct udevice_id fecmxc_ids[] = {
+ { .compatible = "fsl,imx28-fec" },
{ .compatible = "fsl,imx6q-fec" },
{ .compatible = "fsl,imx6sl-fec" },
{ .compatible = "fsl,imx6sx-fec" },
diff --git a/drivers/net/fm/b4860.c b/drivers/net/fm/b4860.c
index 1e20685..5be0ad2 100644
--- a/drivers/net/fm/b4860.c
+++ b/drivers/net/fm/b4860.c
@@ -4,6 +4,7 @@
* Roy Zang <tie-fei.zang@freescale.com>
*/
#include <common.h>
+#include <env.h>
#include <phy.h>
#include <fm_eth.h>
#include <asm/io.h>
diff --git a/drivers/net/fm/fdt.c b/drivers/net/fm/fdt.c
index 6125797..72d1294 100644
--- a/drivers/net/fm/fdt.c
+++ b/drivers/net/fm/fdt.c
@@ -3,6 +3,7 @@
* Copyright 2016 Freescale Semiconductor, Inc.
*/
#include <asm/io.h>
+#include <env.h>
#include <fsl_qe.h> /* For struct qe_firmware */
#ifdef CONFIG_SYS_DPAA_FMAN
diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index 0a43dfe..4c9dce8 100644
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c
@@ -4,6 +4,7 @@
* Dave Liu <daveliu@freescale.com>
*/
#include <common.h>
+#include <env.h>
#include <malloc.h>
#include <asm/io.h>
#include <linux/errno.h>
@@ -14,7 +15,6 @@
#include <nand.h>
#include <spi_flash.h>
#include <mmc.h>
-#include <environment.h>
#ifdef CONFIG_ARM64
#include <asm/armv8/mmu.h>
diff --git a/drivers/net/fsl-mc/Kconfig b/drivers/net/fsl-mc/Kconfig
new file mode 100644
index 0000000..25a2cb8
--- /dev/null
+++ b/drivers/net/fsl-mc/Kconfig
@@ -0,0 +1,25 @@
+#
+# NXP Management Complex
+#
+
+menuconfig FSL_MC_ENET
+ bool "NXP Management Complex"
+ depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A
+ default y
+ select RESV_RAM
+ help
+ Enable Management Complex (MC) network
+ This is NXP Management Complex menuconfig
+ that contains all MC related config options
+
+if FSL_MC_ENET
+
+config SYS_MC_RSV_MEM_ALIGN
+ hex "Management Complex reserved memory alignment"
+ depends on RESV_RAM
+ default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A
+ help
+ Reserved memory needs to be aligned for MC to use. Default value
+ is 512MB.
+
+endif # FSL_MC_ENET
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index cc59b21..c980ba4 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -5,6 +5,7 @@
* Copyright 2017-2018 NXP
*/
#include <common.h>
+#include <env.h>
#include <errno.h>
#include <linux/bug.h>
#include <asm/io.h>
@@ -281,6 +282,16 @@
MC_FIXUP_DPL);
}
+void fdt_fixup_mc_ddr(u64 *base, u64 *size)
+{
+ u64 mc_size = mc_get_dram_block_size();
+
+ if (mc_size < MC_DRAM_BLOCK_DEFAULT_SIZE) {
+ *base = mc_get_dram_addr() + mc_size;
+ *size = MC_DRAM_BLOCK_DEFAULT_SIZE - mc_size;
+ }
+}
+
void fdt_fsl_mc_fixup_iommu_map_entry(void *blob)
{
u32 *prop;
diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c
new file mode 100644
index 0000000..e7c5062
--- /dev/null
+++ b/drivers/net/fsl_enetc.c
@@ -0,0 +1,597 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * ENETC ethernet controller driver
+ * Copyright 2017-2019 NXP
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <memalign.h>
+#include <asm/io.h>
+#include <pci.h>
+#include <miiphy.h>
+
+#include "fsl_enetc.h"
+
+/*
+ * Bind the device:
+ * - set a more explicit name on the interface
+ */
+static int enetc_bind(struct udevice *dev)
+{
+ char name[16];
+ static int eth_num_devices;
+
+ /*
+ * prefer using PCI function numbers to number interfaces, but these
+ * are only available if dts nodes are present. For PCI they are
+ * optional, handle that case too. Just in case some nodes are present
+ * and some are not, use different naming scheme - enetc-N based on
+ * PCI function # and enetc#N based on interface count
+ */
+ if (ofnode_valid(dev->node))
+ sprintf(name, "enetc-%u", PCI_FUNC(pci_get_devfn(dev)));
+ else
+ sprintf(name, "enetc#%u", eth_num_devices++);
+ device_set_name(dev, name);
+
+ return 0;
+}
+
+/* MDIO wrappers, we're using these to drive internal MDIO to get to serdes */
+static int enetc_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
+{
+ struct enetc_mdio_priv priv;
+
+ priv.regs_base = bus->priv;
+ return enetc_mdio_read_priv(&priv, addr, devad, reg);
+}
+
+static int enetc_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
+ u16 val)
+{
+ struct enetc_mdio_priv priv;
+
+ priv.regs_base = bus->priv;
+ return enetc_mdio_write_priv(&priv, addr, devad, reg, val);
+}
+
+/* only interfaces that can pin out through serdes have internal MDIO */
+static bool enetc_has_imdio(struct udevice *dev)
+{
+ struct enetc_priv *priv = dev_get_priv(dev);
+
+ return !!(priv->imdio.priv);
+}
+
+/* set up serdes for SGMII */
+static int enetc_init_sgmii(struct udevice *dev)
+{
+ struct enetc_priv *priv = dev_get_priv(dev);
+ bool is2500 = false;
+ u16 reg;
+
+ if (!enetc_has_imdio(dev))
+ return 0;
+
+ if (priv->if_type == PHY_INTERFACE_MODE_SGMII_2500)
+ is2500 = true;
+
+ /*
+ * Set to SGMII mode, for 1Gbps enable AN, for 2.5Gbps set fixed speed.
+ * Although fixed speed is 1Gbps, we could be running at 2.5Gbps based
+ * on PLL configuration. Setting 1G for 2.5G here is counter intuitive
+ * but intentional.
+ */
+ reg = ENETC_PCS_IF_MODE_SGMII;
+ reg |= is2500 ? ENETC_PCS_IF_MODE_SPEED_1G : ENETC_PCS_IF_MODE_SGMII_AN;
+ enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
+ ENETC_PCS_IF_MODE, reg);
+
+ /* Dev ability - SGMII */
+ enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
+ ENETC_PCS_DEV_ABILITY, ENETC_PCS_DEV_ABILITY_SGMII);
+
+ /* Adjust link timer for SGMII */
+ enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
+ ENETC_PCS_LINK_TIMER1, ENETC_PCS_LINK_TIMER1_VAL);
+ enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
+ ENETC_PCS_LINK_TIMER2, ENETC_PCS_LINK_TIMER2_VAL);
+
+ reg = ENETC_PCS_CR_DEF_VAL;
+ reg |= is2500 ? ENETC_PCS_CR_RST : ENETC_PCS_CR_RESET_AN;
+ /* restart PCS AN */
+ enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
+ ENETC_PCS_CR, reg);
+
+ return 0;
+}
+
+/* set up MAC for RGMII */
+static int enetc_init_rgmii(struct udevice *dev)
+{
+ struct enetc_priv *priv = dev_get_priv(dev);
+ u32 if_mode;
+
+ /* enable RGMII AN */
+ if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE);
+ if_mode |= ENETC_PM_IF_MODE_AN_ENA;
+ enetc_write_port(priv, ENETC_PM_IF_MODE, if_mode);
+
+ return 0;
+}
+
+/* set up MAC and serdes for SXGMII */
+static int enetc_init_sxgmii(struct udevice *dev)
+{
+ struct enetc_priv *priv = dev_get_priv(dev);
+ u32 if_mode;
+
+ /* set ifmode to (US)XGMII */
+ if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE);
+ if_mode &= ~ENETC_PM_IF_IFMODE_MASK;
+ enetc_write_port(priv, ENETC_PM_IF_MODE, if_mode);
+
+ if (!enetc_has_imdio(dev))
+ return 0;
+
+ /* Dev ability - SXGMII */
+ enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, ENETC_PCS_DEVAD_REPL,
+ ENETC_PCS_DEV_ABILITY, ENETC_PCS_DEV_ABILITY_SXGMII);
+
+ /* Restart PCS AN */
+ enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, ENETC_PCS_DEVAD_REPL,
+ ENETC_PCS_CR,
+ ENETC_PCS_CR_RST | ENETC_PCS_CR_RESET_AN);
+
+ return 0;
+}
+
+/* Apply protocol specific configuration to MAC, serdes as needed */
+static void enetc_start_pcs(struct udevice *dev)
+{
+ struct enetc_priv *priv = dev_get_priv(dev);
+ const char *if_str;
+
+ priv->if_type = PHY_INTERFACE_MODE_NONE;
+
+ /* check internal mdio capability, not all ports need it */
+ if (enetc_read_port(priv, ENETC_PCAPR0) & ENETC_PCAPRO_MDIO) {
+ /*
+ * set up internal MDIO, this is part of ETH PCI function and is
+ * used to access serdes / internal SoC PHYs.
+ * We don't currently register it as a MDIO bus as it goes away
+ * when the interface is removed, so it can't practically be
+ * used in the console.
+ */
+ priv->imdio.read = enetc_mdio_read;
+ priv->imdio.write = enetc_mdio_write;
+ priv->imdio.priv = priv->port_regs + ENETC_PM_IMDIO_BASE;
+ strncpy(priv->imdio.name, dev->name, MDIO_NAME_LEN);
+ }
+
+ if (!ofnode_valid(dev->node)) {
+ enetc_dbg(dev, "no enetc ofnode found, skipping PCS set-up\n");
+ return;
+ }
+
+ if_str = ofnode_read_string(dev->node, "phy-mode");
+ if (if_str)
+ priv->if_type = phy_get_interface_by_name(if_str);
+ else
+ enetc_dbg(dev,
+ "phy-mode property not found, defaulting to SGMII\n");
+ if (priv->if_type < 0)
+ priv->if_type = PHY_INTERFACE_MODE_NONE;
+
+ switch (priv->if_type) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_SGMII_2500:
+ enetc_init_sgmii(dev);
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ enetc_init_rgmii(dev);
+ break;
+ case PHY_INTERFACE_MODE_XGMII:
+ enetc_init_sxgmii(dev);
+ break;
+ };
+}
+
+/* Configure the actual/external ethernet PHY, if one is found */
+static void enetc_start_phy(struct udevice *dev)
+{
+ struct enetc_priv *priv = dev_get_priv(dev);
+ struct udevice *miidev;
+ struct phy_device *phy;
+ u32 phandle, phy_id;
+ ofnode phy_node;
+ int supported;
+
+ if (!ofnode_valid(dev->node)) {
+ enetc_dbg(dev, "no enetc ofnode found, skipping PHY set-up\n");
+ return;
+ }
+
+ if (ofnode_read_u32(dev->node, "phy-handle", &phandle)) {
+ enetc_dbg(dev, "phy-handle not found, skipping PHY set-up\n");
+ return;
+ }
+
+ phy_node = ofnode_get_by_phandle(phandle);
+ if (!ofnode_valid(phy_node)) {
+ enetc_dbg(dev, "invalid phy node, skipping PHY set-up\n");
+ return;
+ }
+ enetc_dbg(dev, "phy node: %s\n", ofnode_get_name(phy_node));
+
+ if (ofnode_read_u32(phy_node, "reg", &phy_id)) {
+ enetc_dbg(dev,
+ "missing reg in PHY node, skipping PHY set-up\n");
+ return;
+ }
+
+ if (uclass_get_device_by_ofnode(UCLASS_MDIO,
+ ofnode_get_parent(phy_node),
+ &miidev)) {
+ enetc_dbg(dev, "can't find MDIO bus for node %s\n",
+ ofnode_get_name(ofnode_get_parent(phy_node)));
+ return;
+ }
+
+ phy = dm_mdio_phy_connect(miidev, phy_id, dev, priv->if_type);
+ if (!phy) {
+ enetc_dbg(dev, "dm_mdio_phy_connect returned null\n");
+ return;
+ }
+
+ supported = GENMASK(6, 0); /* speeds up to 1G & AN */
+ phy->advertising = phy->supported & supported;
+ phy_config(phy);
+ phy_startup(phy);
+}
+
+/*
+ * Probe ENETC driver:
+ * - initialize port and station interface BARs
+ */
+static int enetc_probe(struct udevice *dev)
+{
+ struct enetc_priv *priv = dev_get_priv(dev);
+
+ if (ofnode_valid(dev->node) && !ofnode_is_available(dev->node)) {
+ enetc_dbg(dev, "interface disabled\n");
+ return -ENODEV;
+ }
+
+ priv->enetc_txbd = memalign(ENETC_BD_ALIGN,
+ sizeof(struct enetc_tx_bd) * ENETC_BD_CNT);
+ priv->enetc_rxbd = memalign(ENETC_BD_ALIGN,
+ sizeof(union enetc_rx_bd) * ENETC_BD_CNT);
+
+ if (!priv->enetc_txbd || !priv->enetc_rxbd) {
+ /* free should be able to handle NULL, just free all pointers */
+ free(priv->enetc_txbd);
+ free(priv->enetc_rxbd);
+
+ return -ENOMEM;
+ }
+
+ /* initialize register */
+ priv->regs_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0);
+ if (!priv->regs_base) {
+ enetc_dbg(dev, "failed to map BAR0\n");
+ return -EINVAL;
+ }
+ priv->port_regs = priv->regs_base + ENETC_PORT_REGS_OFF;
+
+ dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY);
+
+ return 0;
+}
+
+/*
+ * Remove the driver from an interface:
+ * - free up allocated memory
+ */
+static int enetc_remove(struct udevice *dev)
+{
+ struct enetc_priv *priv = dev_get_priv(dev);
+
+ free(priv->enetc_txbd);
+ free(priv->enetc_rxbd);
+
+ return 0;
+}
+
+/* ENETC Port MAC address registers, accepts big-endian format */
+static void enetc_set_primary_mac_addr(struct enetc_priv *priv, const u8 *addr)
+{
+ u16 lower = *(const u16 *)(addr + 4);
+ u32 upper = *(const u32 *)addr;
+
+ enetc_write_port(priv, ENETC_PSIPMAR0, upper);
+ enetc_write_port(priv, ENETC_PSIPMAR1, lower);
+}
+
+/* Configure port parameters (# of rings, frame size, enable port) */
+static void enetc_enable_si_port(struct enetc_priv *priv)
+{
+ u32 val;
+
+ /* set Rx/Tx BDR count */
+ val = ENETC_PSICFGR_SET_TXBDR(ENETC_TX_BDR_CNT);
+ val |= ENETC_PSICFGR_SET_RXBDR(ENETC_RX_BDR_CNT);
+ enetc_write_port(priv, ENETC_PSICFGR(0), val);
+ /* set Rx max frame size */
+ enetc_write_port(priv, ENETC_PM_MAXFRM, ENETC_RX_MAXFRM_SIZE);
+ /* enable MAC port */
+ enetc_write_port(priv, ENETC_PM_CC, ENETC_PM_CC_RX_TX_EN);
+ /* enable port */
+ enetc_write_port(priv, ENETC_PMR, ENETC_PMR_SI0_EN);
+ /* set SI cache policy */
+ enetc_write(priv, ENETC_SICAR0,
+ ENETC_SICAR_RD_CFG | ENETC_SICAR_WR_CFG);
+ /* enable SI */
+ enetc_write(priv, ENETC_SIMR, ENETC_SIMR_EN);
+}
+
+/* returns DMA address for a given buffer index */
+static inline u64 enetc_rxb_address(struct udevice *dev, int i)
+{
+ return cpu_to_le64(dm_pci_virt_to_mem(dev, net_rx_packets[i]));
+}
+
+/*
+ * Setup a single Tx BD Ring (ID = 0):
+ * - set Tx buffer descriptor address
+ * - set the BD count
+ * - initialize the producer and consumer index
+ */
+static void enetc_setup_tx_bdr(struct udevice *dev)
+{
+ struct enetc_priv *priv = dev_get_priv(dev);
+ struct bd_ring *tx_bdr = &priv->tx_bdr;
+ u64 tx_bd_add = (u64)priv->enetc_txbd;
+
+ /* used later to advance to the next Tx BD */
+ tx_bdr->bd_count = ENETC_BD_CNT;
+ tx_bdr->next_prod_idx = 0;
+ tx_bdr->next_cons_idx = 0;
+ tx_bdr->cons_idx = priv->regs_base +
+ ENETC_BDR(TX, ENETC_TX_BDR_ID, ENETC_TBCIR);
+ tx_bdr->prod_idx = priv->regs_base +
+ ENETC_BDR(TX, ENETC_TX_BDR_ID, ENETC_TBPIR);
+
+ /* set Tx BD address */
+ enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBBAR0,
+ lower_32_bits(tx_bd_add));
+ enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBBAR1,
+ upper_32_bits(tx_bd_add));
+ /* set Tx 8 BD count */
+ enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBLENR,
+ tx_bdr->bd_count);
+
+ /* reset both producer/consumer indexes */
+ enetc_write_reg(tx_bdr->cons_idx, tx_bdr->next_cons_idx);
+ enetc_write_reg(tx_bdr->prod_idx, tx_bdr->next_prod_idx);
+
+ /* enable TX ring */
+ enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBMR, ENETC_TBMR_EN);
+}
+
+/*
+ * Setup a single Rx BD Ring (ID = 0):
+ * - set Rx buffer descriptors address (one descriptor per buffer)
+ * - set buffer size as max frame size
+ * - enable Rx ring
+ * - reset consumer and producer indexes
+ * - set buffer for each descriptor
+ */
+static void enetc_setup_rx_bdr(struct udevice *dev)
+{
+ struct enetc_priv *priv = dev_get_priv(dev);
+ struct bd_ring *rx_bdr = &priv->rx_bdr;
+ u64 rx_bd_add = (u64)priv->enetc_rxbd;
+ int i;
+
+ /* used later to advance to the next BD produced by ENETC HW */
+ rx_bdr->bd_count = ENETC_BD_CNT;
+ rx_bdr->next_prod_idx = 0;
+ rx_bdr->next_cons_idx = 0;
+ rx_bdr->cons_idx = priv->regs_base +
+ ENETC_BDR(RX, ENETC_RX_BDR_ID, ENETC_RBCIR);
+ rx_bdr->prod_idx = priv->regs_base +
+ ENETC_BDR(RX, ENETC_RX_BDR_ID, ENETC_RBPIR);
+
+ /* set Rx BD address */
+ enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBAR0,
+ lower_32_bits(rx_bd_add));
+ enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBAR1,
+ upper_32_bits(rx_bd_add));
+ /* set Rx BD count (multiple of 8) */
+ enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBLENR,
+ rx_bdr->bd_count);
+ /* set Rx buffer size */
+ enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBSR, PKTSIZE_ALIGN);
+
+ /* fill Rx BD */
+ memset(priv->enetc_rxbd, 0,
+ rx_bdr->bd_count * sizeof(union enetc_rx_bd));
+ for (i = 0; i < rx_bdr->bd_count; i++) {
+ priv->enetc_rxbd[i].w.addr = enetc_rxb_address(dev, i);
+ /* each RX buffer must be aligned to 64B */
+ WARN_ON(priv->enetc_rxbd[i].w.addr & (ARCH_DMA_MINALIGN - 1));
+ }
+
+ /* reset producer (ENETC owned) and consumer (SW owned) index */
+ enetc_write_reg(rx_bdr->cons_idx, rx_bdr->next_cons_idx);
+ enetc_write_reg(rx_bdr->prod_idx, rx_bdr->next_prod_idx);
+
+ /* enable Rx ring */
+ enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBMR, ENETC_RBMR_EN);
+}
+
+/*
+ * Start ENETC interface:
+ * - perform FLR
+ * - enable access to port and SI registers
+ * - set mac address
+ * - setup TX/RX buffer descriptors
+ * - enable Tx/Rx rings
+ */
+static int enetc_start(struct udevice *dev)
+{
+ struct eth_pdata *plat = dev_get_platdata(dev);
+ struct enetc_priv *priv = dev_get_priv(dev);
+
+ /* reset and enable the PCI device */
+ dm_pci_flr(dev);
+ dm_pci_clrset_config16(dev, PCI_COMMAND, 0,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+
+ if (!is_valid_ethaddr(plat->enetaddr)) {
+ enetc_dbg(dev, "invalid MAC address, generate random ...\n");
+ net_random_ethaddr(plat->enetaddr);
+ }
+ enetc_set_primary_mac_addr(priv, plat->enetaddr);
+
+ enetc_enable_si_port(priv);
+
+ /* setup Tx/Rx buffer descriptors */
+ enetc_setup_tx_bdr(dev);
+ enetc_setup_rx_bdr(dev);
+
+ enetc_start_pcs(dev);
+ enetc_start_phy(dev);
+
+ return 0;
+}
+
+/*
+ * Stop the network interface:
+ * - just quiesce it, we can wipe all configuration as _start starts from
+ * scratch each time
+ */
+static void enetc_stop(struct udevice *dev)
+{
+ /* FLR is sufficient to quiesce the device */
+ dm_pci_flr(dev);
+}
+
+/*
+ * ENETC transmit packet:
+ * - check if Tx BD ring is full
+ * - set buffer/packet address (dma address)
+ * - set final fragment flag
+ * - try while producer index equals consumer index or timeout
+ */
+static int enetc_send(struct udevice *dev, void *packet, int length)
+{
+ struct enetc_priv *priv = dev_get_priv(dev);
+ struct bd_ring *txr = &priv->tx_bdr;
+ void *nv_packet = (void *)packet;
+ int tries = ENETC_POLL_TRIES;
+ u32 pi, ci;
+
+ pi = txr->next_prod_idx;
+ ci = enetc_read_reg(txr->cons_idx) & ENETC_BDR_IDX_MASK;
+ /* Tx ring is full when */
+ if (((pi + 1) % txr->bd_count) == ci) {
+ enetc_dbg(dev, "Tx BDR full\n");
+ return -ETIMEDOUT;
+ }
+ enetc_dbg(dev, "TxBD[%d]send: pkt_len=%d, buff @0x%x%08x\n", pi, length,
+ upper_32_bits((u64)nv_packet), lower_32_bits((u64)nv_packet));
+
+ /* prepare Tx BD */
+ memset(&priv->enetc_txbd[pi], 0x0, sizeof(struct enetc_tx_bd));
+ priv->enetc_txbd[pi].addr =
+ cpu_to_le64(dm_pci_virt_to_mem(dev, nv_packet));
+ priv->enetc_txbd[pi].buf_len = cpu_to_le16(length);
+ priv->enetc_txbd[pi].frm_len = cpu_to_le16(length);
+ priv->enetc_txbd[pi].flags = cpu_to_le16(ENETC_TXBD_FLAGS_F);
+ dmb();
+ /* send frame: increment producer index */
+ pi = (pi + 1) % txr->bd_count;
+ txr->next_prod_idx = pi;
+ enetc_write_reg(txr->prod_idx, pi);
+ while ((--tries >= 0) &&
+ (pi != (enetc_read_reg(txr->cons_idx) & ENETC_BDR_IDX_MASK)))
+ udelay(10);
+
+ return tries > 0 ? 0 : -ETIMEDOUT;
+}
+
+/*
+ * Receive frame:
+ * - wait for the next BD to get ready bit set
+ * - clean up the descriptor
+ * - move on and indicate to HW that the cleaned BD is available for Rx
+ */
+static int enetc_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct enetc_priv *priv = dev_get_priv(dev);
+ struct bd_ring *rxr = &priv->rx_bdr;
+ int tries = ENETC_POLL_TRIES;
+ int pi = rxr->next_prod_idx;
+ int ci = rxr->next_cons_idx;
+ u32 status;
+ int len;
+ u8 rdy;
+
+ do {
+ dmb();
+ status = le32_to_cpu(priv->enetc_rxbd[pi].r.lstatus);
+ /* check if current BD is ready to be consumed */
+ rdy = ENETC_RXBD_STATUS_R(status);
+ } while (--tries >= 0 && !rdy);
+
+ if (!rdy)
+ return -EAGAIN;
+
+ dmb();
+ len = le16_to_cpu(priv->enetc_rxbd[pi].r.buf_len);
+ *packetp = (uchar *)enetc_rxb_address(dev, pi);
+ enetc_dbg(dev, "RxBD[%d]: len=%d err=%d pkt=0x%x%08x\n", pi, len,
+ ENETC_RXBD_STATUS_ERRORS(status),
+ upper_32_bits((u64)*packetp), lower_32_bits((u64)*packetp));
+
+ /* BD clean up and advance to next in ring */
+ memset(&priv->enetc_rxbd[pi], 0, sizeof(union enetc_rx_bd));
+ priv->enetc_rxbd[pi].w.addr = enetc_rxb_address(dev, pi);
+ rxr->next_prod_idx = (pi + 1) % rxr->bd_count;
+ ci = (ci + 1) % rxr->bd_count;
+ rxr->next_cons_idx = ci;
+ dmb();
+ /* free up the slot in the ring for HW */
+ enetc_write_reg(rxr->cons_idx, ci);
+
+ return len;
+}
+
+static const struct eth_ops enetc_ops = {
+ .start = enetc_start,
+ .send = enetc_send,
+ .recv = enetc_recv,
+ .stop = enetc_stop,
+};
+
+U_BOOT_DRIVER(eth_enetc) = {
+ .name = "enetc_eth",
+ .id = UCLASS_ETH,
+ .bind = enetc_bind,
+ .probe = enetc_probe,
+ .remove = enetc_remove,
+ .ops = &enetc_ops,
+ .priv_auto_alloc_size = sizeof(struct enetc_priv),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
+
+static struct pci_device_id enetc_ids[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_ENETC_ETH) },
+ {}
+};
+
+U_BOOT_PCI_DEVICE(eth_enetc, enetc_ids);
diff --git a/drivers/net/fsl_enetc.h b/drivers/net/fsl_enetc.h
new file mode 100644
index 0000000..0bb4cdf
--- /dev/null
+++ b/drivers/net/fsl_enetc.h
@@ -0,0 +1,229 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * ENETC ethernet controller driver
+ * Copyright 2017-2019 NXP
+ */
+
+#ifndef _ENETC_H
+#define _ENETC_H
+
+#define enetc_dbg(dev, fmt, args...) debug("%s:" fmt, dev->name, ##args)
+
+/* PCI function IDs */
+#define PCI_DEVICE_ID_ENETC_ETH 0xE100
+#define PCI_DEVICE_ID_ENETC_MDIO 0xEE01
+
+/* ENETC Ethernet controller registers */
+/* Station interface register offsets */
+#define ENETC_SIMR 0x000
+#define ENETC_SIMR_EN BIT(31)
+#define ENETC_SICAR0 0x040
+/* write cache cfg: snoop, no allocate, data & BD coherent */
+#define ENETC_SICAR_WR_CFG 0x6767
+/* read cache cfg: coherent copy, look up, don't alloc in cache */
+#define ENETC_SICAR_RD_CFG 0x27270000
+#define ENETC_SIROCT 0x300
+#define ENETC_SIRFRM 0x308
+#define ENETC_SITOCT 0x320
+#define ENETC_SITFRM 0x328
+
+/* Rx/Tx Buffer Descriptor Ring registers */
+enum enetc_bdr_type {TX, RX};
+#define ENETC_BDR(type, n, off) (0x8000 + (type) * 0x100 + (n) * 0x200 + (off))
+#define ENETC_BDR_IDX_MASK 0xffff
+
+/* Rx BDR reg offsets */
+#define ENETC_RBMR 0x00
+#define ENETC_RBMR_EN BIT(31)
+#define ENETC_RBBSR 0x08
+/* initial consumer index for Rx BDR */
+#define ENETC_RBCIR 0x0c
+#define ENETC_RBBAR0 0x10
+#define ENETC_RBBAR1 0x14
+#define ENETC_RBPIR 0x18
+#define ENETC_RBLENR 0x20
+
+/* Tx BDR reg offsets */
+#define ENETC_TBMR 0x00
+#define ENETC_TBMR_EN BIT(31)
+#define ENETC_TBBAR0 0x10
+#define ENETC_TBBAR1 0x14
+#define ENETC_TBPIR 0x18
+#define ENETC_TBCIR 0x1c
+#define ENETC_TBLENR 0x20
+
+/* Port registers offset */
+#define ENETC_PORT_REGS_OFF 0x10000
+
+/* Port registers */
+#define ENETC_PMR 0x0000
+#define ENETC_PMR_SI0_EN BIT(16)
+#define ENETC_PSIPMMR 0x0018
+#define ENETC_PSIPMAR0 0x0100
+#define ENETC_PSIPMAR1 0x0104
+#define ENETC_PCAPR0 0x0900
+#define ENETC_PCAPRO_MDIO BIT(11)
+#define ENETC_PSICFGR(n) (0x0940 + (n) * 0x10)
+#define ENETC_PSICFGR_SET_TXBDR(val) ((val) & 0xff)
+#define ENETC_PSICFGR_SET_RXBDR(val) (((val) & 0xff) << 16)
+/* MAC configuration */
+#define ENETC_PM_CC 0x8008
+#define ENETC_PM_CC_DEFAULT 0x0810
+#define ENETC_PM_CC_RX_TX_EN 0x8813
+#define ENETC_PM_MAXFRM 0x8014
+#define ENETC_RX_MAXFRM_SIZE PKTSIZE_ALIGN
+#define ENETC_PM_IMDIO_BASE 0x8030
+#define ENETC_PM_IF_MODE 0x8300
+#define ENETC_PM_IF_MODE_RG BIT(2)
+#define ENETC_PM_IF_MODE_AN_ENA BIT(15)
+#define ENETC_PM_IF_IFMODE_MASK GENMASK(1, 0)
+
+/* buffer descriptors count must be multiple of 8 and aligned to 128 bytes */
+#define ENETC_BD_CNT CONFIG_SYS_RX_ETH_BUFFER
+#define ENETC_BD_ALIGN 128
+
+/* single pair of Rx/Tx rings */
+#define ENETC_RX_BDR_CNT 1
+#define ENETC_TX_BDR_CNT 1
+#define ENETC_RX_BDR_ID 0
+#define ENETC_TX_BDR_ID 0
+
+/* Tx buffer descriptor */
+struct enetc_tx_bd {
+ __le64 addr;
+ __le16 buf_len;
+ __le16 frm_len;
+ __le16 err_csum;
+ __le16 flags;
+};
+
+#define ENETC_TXBD_FLAGS_F BIT(15)
+#define ENETC_POLL_TRIES 32000
+
+/* Rx buffer descriptor */
+union enetc_rx_bd {
+ /* SW provided BD format */
+ struct {
+ __le64 addr;
+ u8 reserved[8];
+ } w;
+
+ /* ENETC returned BD format */
+ struct {
+ __le16 inet_csum;
+ __le16 parse_summary;
+ __le32 rss_hash;
+ __le16 buf_len;
+ __le16 vlan_opt;
+ union {
+ struct {
+ __le16 flags;
+ __le16 error;
+ };
+ __le32 lstatus;
+ };
+ } r;
+};
+
+#define ENETC_RXBD_STATUS_R(status) (((status) >> 30) & 0x1)
+#define ENETC_RXBD_STATUS_F(status) (((status) >> 31) & 0x1)
+#define ENETC_RXBD_STATUS_ERRORS(status) (((status) >> 16) & 0xff)
+#define ENETC_RXBD_STATUS(flags) ((flags) << 16)
+
+/* Tx/Rx ring info */
+struct bd_ring {
+ void *cons_idx;
+ void *prod_idx;
+ /* next BD index to use */
+ int next_prod_idx;
+ int next_cons_idx;
+ int bd_count;
+};
+
+/* ENETC private structure */
+struct enetc_priv {
+ struct enetc_tx_bd *enetc_txbd;
+ union enetc_rx_bd *enetc_rxbd;
+
+ void *regs_base; /* base ENETC registers */
+ void *port_regs; /* base ENETC port registers */
+
+ /* Rx/Tx buffer descriptor rings info */
+ struct bd_ring tx_bdr;
+ struct bd_ring rx_bdr;
+
+ int if_type;
+ struct mii_dev imdio;
+};
+
+/* register accessors */
+#define enetc_read_reg(x) readl((x))
+#define enetc_write_reg(x, val) writel((val), (x))
+#define enetc_read(priv, off) enetc_read_reg((priv)->regs_base + (off))
+#define enetc_write(priv, off, v) \
+ enetc_write_reg((priv)->regs_base + (off), v)
+
+/* port register accessors */
+#define enetc_port_regs(priv, off) ((priv)->port_regs + (off))
+#define enetc_read_port(priv, off) \
+ enetc_read_reg(enetc_port_regs((priv), (off)))
+#define enetc_write_port(priv, off, v) \
+ enetc_write_reg(enetc_port_regs((priv), (off)), v)
+
+/* BDR register accessors, see ENETC_BDR() */
+#define enetc_bdr_read(priv, t, n, off) \
+ enetc_read(priv, ENETC_BDR(t, n, off))
+#define enetc_bdr_write(priv, t, n, off, val) \
+ enetc_write(priv, ENETC_BDR(t, n, off), val)
+
+/* PCS / internal SoC PHY ID, it defaults to 0 on all interfaces */
+#define ENETC_PCS_PHY_ADDR 0
+
+/* PCS registers */
+#define ENETC_PCS_CR 0x00
+#define ENETC_PCS_CR_RESET_AN 0x1200
+#define ENETC_PCS_CR_DEF_VAL 0x0140
+#define ENETC_PCS_CR_RST BIT(15)
+#define ENETC_PCS_DEV_ABILITY 0x04
+#define ENETC_PCS_DEV_ABILITY_SGMII 0x4001
+#define ENETC_PCS_DEV_ABILITY_SXGMII 0x5001
+#define ENETC_PCS_LINK_TIMER1 0x12
+#define ENETC_PCS_LINK_TIMER1_VAL 0x06a0
+#define ENETC_PCS_LINK_TIMER2 0x13
+#define ENETC_PCS_LINK_TIMER2_VAL 0x0003
+#define ENETC_PCS_IF_MODE 0x14
+#define ENETC_PCS_IF_MODE_SGMII BIT(0)
+#define ENETC_PCS_IF_MODE_SGMII_AN BIT(1)
+#define ENETC_PCS_IF_MODE_SPEED_1G BIT(3)
+
+/* PCS replicator block for USXGMII */
+#define ENETC_PCS_DEVAD_REPL 0x1f
+
+/* ENETC external MDIO registers */
+#define ENETC_MDIO_BASE 0x1c00
+#define ENETC_MDIO_CFG 0x00
+#define ENETC_EMDIO_CFG_C22 0x00809508
+#define ENETC_EMDIO_CFG_C45 0x00809548
+#define ENETC_EMDIO_CFG_RD_ER BIT(1)
+#define ENETC_EMDIO_CFG_BSY BIT(0)
+#define ENETC_MDIO_CTL 0x04
+#define ENETC_MDIO_CTL_READ BIT(15)
+#define ENETC_MDIO_DATA 0x08
+#define ENETC_MDIO_STAT 0x0c
+
+#define ENETC_MDIO_READ_ERR 0xffff
+
+struct enetc_mdio_priv {
+ void *regs_base;
+};
+
+/*
+ * these functions are implemented by ENETC_MDIO and are re-used by ENETC driver
+ * to drive serdes / internal SoC PHYs
+ */
+int enetc_mdio_read_priv(struct enetc_mdio_priv *priv, int addr, int devad,
+ int reg);
+int enetc_mdio_write_priv(struct enetc_mdio_priv *priv, int addr, int devad,
+ int reg, u16 val);
+
+#endif /* _ENETC_H */
diff --git a/drivers/net/fsl_enetc_mdio.c b/drivers/net/fsl_enetc_mdio.c
new file mode 100644
index 0000000..b4463a5
--- /dev/null
+++ b/drivers/net/fsl_enetc_mdio.c
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * ENETC ethernet controller driver
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <pci.h>
+#include <miiphy.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <miiphy.h>
+
+#include "fsl_enetc.h"
+
+static void enetc_mdio_wait_bsy(struct enetc_mdio_priv *priv)
+{
+ while (enetc_read(priv, ENETC_MDIO_CFG) & ENETC_EMDIO_CFG_BSY)
+ cpu_relax();
+}
+
+int enetc_mdio_read_priv(struct enetc_mdio_priv *priv, int addr, int devad,
+ int reg)
+{
+ if (devad == MDIO_DEVAD_NONE)
+ enetc_write(priv, ENETC_MDIO_CFG, ENETC_EMDIO_CFG_C22);
+ else
+ enetc_write(priv, ENETC_MDIO_CFG, ENETC_EMDIO_CFG_C45);
+ enetc_mdio_wait_bsy(priv);
+
+ if (devad == MDIO_DEVAD_NONE) {
+ enetc_write(priv, ENETC_MDIO_CTL, ENETC_MDIO_CTL_READ |
+ (addr << 5) | reg);
+ } else {
+ enetc_write(priv, ENETC_MDIO_CTL, (addr << 5) + devad);
+ enetc_mdio_wait_bsy(priv);
+
+ enetc_write(priv, ENETC_MDIO_STAT, reg);
+ enetc_mdio_wait_bsy(priv);
+
+ enetc_write(priv, ENETC_MDIO_CTL, ENETC_MDIO_CTL_READ |
+ (addr << 5) | devad);
+ }
+
+ enetc_mdio_wait_bsy(priv);
+ if (enetc_read(priv, ENETC_MDIO_CFG) & ENETC_EMDIO_CFG_RD_ER)
+ return ENETC_MDIO_READ_ERR;
+
+ return enetc_read(priv, ENETC_MDIO_DATA);
+}
+
+int enetc_mdio_write_priv(struct enetc_mdio_priv *priv, int addr, int devad,
+ int reg, u16 val)
+{
+ if (devad == MDIO_DEVAD_NONE)
+ enetc_write(priv, ENETC_MDIO_CFG, ENETC_EMDIO_CFG_C22);
+ else
+ enetc_write(priv, ENETC_MDIO_CFG, ENETC_EMDIO_CFG_C45);
+ enetc_mdio_wait_bsy(priv);
+
+ if (devad != MDIO_DEVAD_NONE) {
+ enetc_write(priv, ENETC_MDIO_CTL, (addr << 5) + devad);
+ enetc_write(priv, ENETC_MDIO_STAT, reg);
+ } else {
+ enetc_write(priv, ENETC_MDIO_CTL, (addr << 5) + reg);
+ }
+ enetc_mdio_wait_bsy(priv);
+
+ enetc_write(priv, ENETC_MDIO_DATA, val);
+ enetc_mdio_wait_bsy(priv);
+
+ return 0;
+}
+
+/* DM wrappers */
+static int dm_enetc_mdio_read(struct udevice *dev, int addr, int devad, int reg)
+{
+ struct enetc_mdio_priv *priv = dev_get_priv(dev);
+
+ return enetc_mdio_read_priv(priv, addr, devad, reg);
+}
+
+static int dm_enetc_mdio_write(struct udevice *dev, int addr, int devad,
+ int reg, u16 val)
+{
+ struct enetc_mdio_priv *priv = dev_get_priv(dev);
+
+ return enetc_mdio_write_priv(priv, addr, devad, reg, val);
+}
+
+static const struct mdio_ops enetc_mdio_ops = {
+ .read = dm_enetc_mdio_read,
+ .write = dm_enetc_mdio_write,
+};
+
+static int enetc_mdio_bind(struct udevice *dev)
+{
+ char name[16];
+ static int eth_num_devices;
+
+ /*
+ * prefer using PCI function numbers to number interfaces, but these
+ * are only available if dts nodes are present. For PCI they are
+ * optional, handle that case too. Just in case some nodes are present
+ * and some are not, use different naming scheme - enetc-N based on
+ * PCI function # and enetc#N based on interface count
+ */
+ if (ofnode_valid(dev->node))
+ sprintf(name, "emdio-%u", PCI_FUNC(pci_get_devfn(dev)));
+ else
+ sprintf(name, "emdio#%u", eth_num_devices++);
+ device_set_name(dev, name);
+
+ return 0;
+}
+
+static int enetc_mdio_probe(struct udevice *dev)
+{
+ struct enetc_mdio_priv *priv = dev_get_priv(dev);
+
+ priv->regs_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0);
+ if (!priv->regs_base) {
+ enetc_dbg(dev, "failed to map BAR0\n");
+ return -EINVAL;
+ }
+
+ priv->regs_base += ENETC_MDIO_BASE;
+
+ dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(enetc_mdio) = {
+ .name = "enetc_mdio",
+ .id = UCLASS_MDIO,
+ .bind = enetc_mdio_bind,
+ .probe = enetc_mdio_probe,
+ .ops = &enetc_mdio_ops,
+ .priv_auto_alloc_size = sizeof(struct enetc_mdio_priv),
+};
+
+static struct pci_device_id enetc_mdio_ids[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_ENETC_MDIO) },
+ { }
+};
+
+U_BOOT_PCI_DEVICE(enetc_mdio, enetc_mdio_ids);
diff --git a/drivers/net/fsl_mcdmafec.c b/drivers/net/fsl_mcdmafec.c
index 88309b1..e66fb16 100644
--- a/drivers/net/fsl_mcdmafec.c
+++ b/drivers/net/fsl_mcdmafec.c
@@ -8,7 +8,7 @@
*/
#include <common.h>
-#include <environment.h>
+#include <env.h>
#include <malloc.h>
#include <command.h>
#include <config.h>
diff --git a/drivers/net/ftmac100.c b/drivers/net/ftmac100.c
index c08889c..d8f1dde 100644
--- a/drivers/net/ftmac100.c
+++ b/drivers/net/ftmac100.c
@@ -8,6 +8,7 @@
#include <config.h>
#include <common.h>
+#include <env.h>
#include <malloc.h>
#include <net.h>
#include <linux/io.h>
diff --git a/drivers/net/lan91c96.c b/drivers/net/lan91c96.c
index f2489aa..c08bd21 100644
--- a/drivers/net/lan91c96.c
+++ b/drivers/net/lan91c96.c
@@ -46,6 +46,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <malloc.h>
#include "lan91c96.h"
#include <net.h>
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index c5560a7..377188e 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -45,9 +45,17 @@
DECLARE_GLOBAL_DATA_PTR;
-#define MACB_RX_BUFFER_SIZE 4096
-#define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128)
+/*
+ * These buffer sizes must be power of 2 and divisible
+ * by RX_BUFFER_MULTIPLE
+ */
+#define MACB_RX_BUFFER_SIZE 128
+#define GEM_RX_BUFFER_SIZE 2048
+#define RX_BUFFER_MULTIPLE 64
+
+#define MACB_RX_RING_SIZE 32
#define MACB_TX_RING_SIZE 16
+
#define MACB_TX_TIMEOUT 1000
#define MACB_AUTONEG_TIMEOUT 5000000
@@ -77,31 +85,16 @@
#define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
#define MACB_TX_DUMMY_DMA_DESC_SIZE (DMA_DESC_BYTES(1))
-#define RXADDR_USED 0x00000001
-#define RXADDR_WRAP 0x00000002
-
#define RXBUF_FRMLEN_MASK 0x00000fff
-#define RXBUF_FRAME_START 0x00004000
-#define RXBUF_FRAME_END 0x00008000
-#define RXBUF_TYPEID_MATCH 0x00400000
-#define RXBUF_ADDR4_MATCH 0x00800000
-#define RXBUF_ADDR3_MATCH 0x01000000
-#define RXBUF_ADDR2_MATCH 0x02000000
-#define RXBUF_ADDR1_MATCH 0x04000000
-#define RXBUF_BROADCAST 0x80000000
-
#define TXBUF_FRMLEN_MASK 0x000007ff
-#define TXBUF_FRAME_END 0x00008000
-#define TXBUF_NOCRC 0x00010000
-#define TXBUF_EXHAUSTED 0x08000000
-#define TXBUF_UNDERRUN 0x10000000
-#define TXBUF_MAXRETRY 0x20000000
-#define TXBUF_WRAP 0x40000000
-#define TXBUF_USED 0x80000000
struct macb_device {
void *regs;
+ bool is_big_endian;
+
+ const struct macb_config *config;
+
unsigned int rx_tail;
unsigned int tx_head;
unsigned int tx_tail;
@@ -112,6 +105,7 @@
void *tx_buffer;
struct macb_dma_desc *rx_ring;
struct macb_dma_desc *tx_ring;
+ size_t rx_buffer_size;
unsigned long rx_buffer_dma;
unsigned long rx_ring_dma;
@@ -137,6 +131,13 @@
phy_interface_t phy_interface;
#endif
};
+
+struct macb_config {
+ unsigned int dma_burst_length;
+
+ int (*clk_init)(struct udevice *dev, ulong rate);
+};
+
#ifndef CONFIG_DM_ETH
#define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
#endif
@@ -295,13 +296,15 @@
static inline void macb_flush_rx_buffer(struct macb_device *macb)
{
flush_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
- ALIGN(MACB_RX_BUFFER_SIZE, PKTALIGN));
+ ALIGN(macb->rx_buffer_size * MACB_RX_RING_SIZE,
+ PKTALIGN));
}
static inline void macb_invalidate_rx_buffer(struct macb_device *macb)
{
invalidate_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
- ALIGN(MACB_RX_BUFFER_SIZE, PKTALIGN));
+ ALIGN(macb->rx_buffer_size * MACB_RX_RING_SIZE,
+ PKTALIGN));
}
#if defined(CONFIG_CMD_NET)
@@ -316,9 +319,9 @@
paddr = dma_map_single(packet, length, DMA_TO_DEVICE);
ctrl = length & TXBUF_FRMLEN_MASK;
- ctrl |= TXBUF_FRAME_END;
+ ctrl |= MACB_BIT(TX_LAST);
if (tx_head == (MACB_TX_RING_SIZE - 1)) {
- ctrl |= TXBUF_WRAP;
+ ctrl |= MACB_BIT(TX_WRAP);
macb->tx_head = 0;
} else {
macb->tx_head++;
@@ -340,7 +343,7 @@
barrier();
macb_invalidate_ring_desc(macb, TX);
ctrl = macb->tx_ring[tx_head].ctrl;
- if (ctrl & TXBUF_USED)
+ if (ctrl & MACB_BIT(TX_USED))
break;
udelay(1);
}
@@ -348,9 +351,9 @@
dma_unmap_single(packet, length, paddr);
if (i <= MACB_TX_TIMEOUT) {
- if (ctrl & TXBUF_UNDERRUN)
+ if (ctrl & MACB_BIT(TX_UNDERRUN))
printf("%s: TX underrun\n", name);
- if (ctrl & TXBUF_EXHAUSTED)
+ if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
printf("%s: TX buffers exhausted in mid frame\n", name);
} else {
printf("%s: TX timeout\n", name);
@@ -369,14 +372,14 @@
macb_invalidate_ring_desc(macb, RX);
while (i > new_tail) {
- macb->rx_ring[i].addr &= ~RXADDR_USED;
+ macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
i++;
if (i > MACB_RX_RING_SIZE)
i = 0;
}
while (i < new_tail) {
- macb->rx_ring[i].addr &= ~RXADDR_USED;
+ macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
i++;
}
@@ -396,26 +399,27 @@
for (;;) {
macb_invalidate_ring_desc(macb, RX);
- if (!(macb->rx_ring[next_rx_tail].addr & RXADDR_USED))
+ if (!(macb->rx_ring[next_rx_tail].addr & MACB_BIT(RX_USED)))
return -EAGAIN;
status = macb->rx_ring[next_rx_tail].ctrl;
- if (status & RXBUF_FRAME_START) {
+ if (status & MACB_BIT(RX_SOF)) {
if (next_rx_tail != macb->rx_tail)
reclaim_rx_buffers(macb, next_rx_tail);
macb->wrapped = false;
}
- if (status & RXBUF_FRAME_END) {
- buffer = macb->rx_buffer + 128 * macb->rx_tail;
+ if (status & MACB_BIT(RX_EOF)) {
+ buffer = macb->rx_buffer +
+ macb->rx_buffer_size * macb->rx_tail;
length = status & RXBUF_FRMLEN_MASK;
macb_invalidate_rx_buffer(macb);
if (macb->wrapped) {
unsigned int headlen, taillen;
- headlen = 128 * (MACB_RX_RING_SIZE
- - macb->rx_tail);
+ headlen = macb->rx_buffer_size *
+ (MACB_RX_RING_SIZE - macb->rx_tail);
taillen = length - headlen;
memcpy((void *)net_rx_packets[0],
buffer, headlen);
@@ -495,21 +499,38 @@
* when operation failed.
*/
#ifdef CONFIG_DM_ETH
+static int macb_sifive_clk_init(struct udevice *dev, ulong rate)
+{
+ fdt_addr_t addr;
+ void *gemgxl_regs;
+
+ addr = dev_read_addr_index(dev, 1);
+ if (addr == FDT_ADDR_T_NONE)
+ return -ENODEV;
+
+ gemgxl_regs = (void __iomem *)addr;
+ if (!gemgxl_regs)
+ return -ENODEV;
+
+ /*
+ * SiFive GEMGXL TX clock operation mode:
+ *
+ * 0 = GMII mode. Use 125 MHz gemgxlclk from PRCI in TX logic
+ * and output clock on GMII output signal GTX_CLK
+ * 1 = MII mode. Use MII input signal TX_CLK in TX logic
+ */
+ writel(rate != 125000000, gemgxl_regs);
+ return 0;
+}
+
int __weak macb_linkspd_cb(struct udevice *dev, unsigned int speed)
{
#ifdef CONFIG_CLK
+ struct macb_device *macb = dev_get_priv(dev);
struct clk tx_clk;
ulong rate;
int ret;
- /*
- * "tx_clk" is an optional clock source for MACB.
- * Ignore if it does not exist in DT.
- */
- ret = clk_get_by_name(dev, "tx_clk", &tx_clk);
- if (ret)
- return 0;
-
switch (speed) {
case _10BASET:
rate = 2500000; /* 2.5 MHz */
@@ -525,6 +546,17 @@
return 0;
}
+ if (macb->config->clk_init)
+ return macb->config->clk_init(dev, rate);
+
+ /*
+ * "tx_clk" is an optional clock source for MACB.
+ * Ignore if it does not exist in DT.
+ */
+ ret = clk_get_by_name(dev, "tx_clk", &tx_clk);
+ if (ret)
+ return 0;
+
if (tx_clk.dev) {
ret = clk_set_rate(&tx_clk, rate);
if (ret)
@@ -615,8 +647,10 @@
if (gem_is_gigabit_capable(macb)) {
lpa = macb_mdio_read(macb, MII_STAT1000);
- if (lpa & (LPA_1000FULL | LPA_1000HALF)) {
- duplex = ((lpa & LPA_1000FULL) ? 1 : 0);
+ if (lpa & (LPA_1000FULL | LPA_1000HALF | LPA_1000XFULL |
+ LPA_1000XHALF)) {
+ duplex = ((lpa & (LPA_1000FULL | LPA_1000XFULL)) ?
+ 1 : 0);
printf("%s: link up, 1000Mbps %s-duplex (lpa: 0x%04x)\n",
name,
@@ -697,7 +731,7 @@
if (queue_mask & (1 << i))
num_queues++;
- macb->dummy_desc->ctrl = TXBUF_USED;
+ macb->dummy_desc->ctrl = MACB_BIT(TX_USED);
macb->dummy_desc->addr = 0;
flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma +
ALIGN(MACB_TX_DUMMY_DMA_DESC_SIZE, PKTALIGN));
@@ -708,6 +742,31 @@
return 0;
}
+static void gmac_configure_dma(struct macb_device *macb)
+{
+ u32 buffer_size;
+ u32 dmacfg;
+
+ buffer_size = macb->rx_buffer_size / RX_BUFFER_MULTIPLE;
+ dmacfg = gem_readl(macb, DMACFG) & ~GEM_BF(RXBS, -1L);
+ dmacfg |= GEM_BF(RXBS, buffer_size);
+
+ if (macb->config->dma_burst_length)
+ dmacfg = GEM_BFINS(FBLDO,
+ macb->config->dma_burst_length, dmacfg);
+
+ dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
+ dmacfg &= ~GEM_BIT(ENDIA_PKT);
+
+ if (macb->is_big_endian)
+ dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
+ else
+ dmacfg &= ~GEM_BIT(ENDIA_DESC);
+
+ dmacfg &= ~GEM_BIT(ADDR64);
+ gem_writel(macb, DMACFG, dmacfg);
+}
+
#ifdef CONFIG_DM_ETH
static int _macb_init(struct udevice *dev, const char *name)
#else
@@ -730,10 +789,10 @@
paddr = macb->rx_buffer_dma;
for (i = 0; i < MACB_RX_RING_SIZE; i++) {
if (i == (MACB_RX_RING_SIZE - 1))
- paddr |= RXADDR_WRAP;
+ paddr |= MACB_BIT(RX_WRAP);
macb->rx_ring[i].addr = paddr;
macb->rx_ring[i].ctrl = 0;
- paddr += 128;
+ paddr += macb->rx_buffer_size;
}
macb_flush_ring_desc(macb, RX);
macb_flush_rx_buffer(macb);
@@ -741,9 +800,10 @@
for (i = 0; i < MACB_TX_RING_SIZE; i++) {
macb->tx_ring[i].addr = 0;
if (i == (MACB_TX_RING_SIZE - 1))
- macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP;
+ macb->tx_ring[i].ctrl = MACB_BIT(TX_USED) |
+ MACB_BIT(TX_WRAP);
else
- macb->tx_ring[i].ctrl = TXBUF_USED;
+ macb->tx_ring[i].ctrl = MACB_BIT(TX_USED);
}
macb_flush_ring_desc(macb, TX);
@@ -760,6 +820,8 @@
macb_writel(macb, TBQP, macb->tx_ring_dma);
if (macb_is_gem(macb)) {
+ /* Initialize DMA properties */
+ gmac_configure_dma(macb);
/* Check the multi queue and initialize the queue for tx */
gmac_init_multi_queues(macb);
@@ -772,14 +834,21 @@
#ifdef CONFIG_DM_ETH
if ((macb->phy_interface == PHY_INTERFACE_MODE_RMII) ||
(macb->phy_interface == PHY_INTERFACE_MODE_RGMII))
- gem_writel(macb, UR, GEM_BIT(RGMII));
+ gem_writel(macb, USRIO, GEM_BIT(RGMII));
else
- gem_writel(macb, UR, 0);
+ gem_writel(macb, USRIO, 0);
+
+ if (macb->phy_interface == PHY_INTERFACE_MODE_SGMII) {
+ unsigned int ncfgr = macb_readl(macb, NCFGR);
+
+ ncfgr |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
+ macb_writel(macb, NCFGR, ncfgr);
+ }
#else
#if defined(CONFIG_RGMII) || defined(CONFIG_RMII)
- gem_writel(macb, UR, GEM_BIT(RGMII));
+ gem_writel(macb, USRIO, GEM_BIT(RGMII));
#else
- gem_writel(macb, UR, 0);
+ gem_writel(macb, USRIO, 0);
#endif
#endif
} else {
@@ -901,8 +970,12 @@
config = GEM_BF(CLK, GEM_CLK_DIV48);
else if (macb_hz < 160000000)
config = GEM_BF(CLK, GEM_CLK_DIV64);
- else
+ else if (macb_hz < 240000000)
config = GEM_BF(CLK, GEM_CLK_DIV96);
+ else if (macb_hz < 320000000)
+ config = GEM_BF(CLK, GEM_CLK_DIV128);
+ else
+ config = GEM_BF(CLK, GEM_CLK_DIV224);
return config;
}
@@ -930,8 +1003,14 @@
int id = 0; /* This is not used by functions we call */
u32 ncfgr;
+ if (macb_is_gem(macb))
+ macb->rx_buffer_size = GEM_RX_BUFFER_SIZE;
+ else
+ macb->rx_buffer_size = MACB_RX_BUFFER_SIZE;
+
/* TODO: we need check the rx/tx_ring_dma is dcache line aligned */
- macb->rx_buffer = dma_alloc_coherent(MACB_RX_BUFFER_SIZE,
+ macb->rx_buffer = dma_alloc_coherent(macb->rx_buffer_size *
+ MACB_RX_RING_SIZE,
&macb->rx_buffer_dma);
macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE,
&macb->rx_ring_dma);
@@ -1140,12 +1219,17 @@
}
#endif
+static const struct macb_config default_gem_config = {
+ .dma_burst_length = 16,
+ .clk_init = NULL,
+};
+
static int macb_eth_probe(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct macb_device *macb = dev_get_priv(dev);
const char *phy_mode;
- __maybe_unused int ret;
+ int ret;
phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
NULL);
@@ -1158,6 +1242,12 @@
macb->regs = (void *)pdata->iobase;
+ macb->is_big_endian = (cpu_to_be32(0x12345678) == 0x12345678);
+
+ macb->config = (struct macb_config *)dev_get_driver_data(dev);
+ if (!macb->config)
+ macb->config = &default_gem_config;
+
#ifdef CONFIG_CLK
ret = macb_enable_clk(dev);
if (ret)
@@ -1218,13 +1308,25 @@
return macb_late_eth_ofdata_to_platdata(dev);
}
+static const struct macb_config sama5d4_config = {
+ .dma_burst_length = 4,
+ .clk_init = NULL,
+};
+
+static const struct macb_config sifive_config = {
+ .dma_burst_length = 16,
+ .clk_init = macb_sifive_clk_init,
+};
+
static const struct udevice_id macb_eth_ids[] = {
{ .compatible = "cdns,macb" },
{ .compatible = "cdns,at91sam9260-macb" },
{ .compatible = "atmel,sama5d2-gem" },
{ .compatible = "atmel,sama5d3-gem" },
- { .compatible = "atmel,sama5d4-gem" },
+ { .compatible = "atmel,sama5d4-gem", .data = (ulong)&sama5d4_config },
{ .compatible = "cdns,zynq-gem" },
+ { .compatible = "sifive,fu540-c000-gem",
+ .data = (ulong)&sifive_config },
{ }
};
diff --git a/drivers/net/macb.h b/drivers/net/macb.h
index 3cc27f8..9b16383 100644
--- a/drivers/net/macb.h
+++ b/drivers/net/macb.h
@@ -5,221 +5,410 @@
#ifndef __DRIVERS_MACB_H__
#define __DRIVERS_MACB_H__
+#define MACB_GREGS_NBR 16
+#define MACB_GREGS_VERSION 2
+#define MACB_MAX_QUEUES 8
+
/* MACB register offsets */
-#define MACB_NCR 0x0000
-#define MACB_NCFGR 0x0004
-#define MACB_NSR 0x0008
-#define GEM_UR 0x000c
-#define MACB_DMACFG 0x0010
-#define MACB_TSR 0x0014
-#define MACB_RBQP 0x0018
-#define MACB_TBQP 0x001c
-#define MACB_RSR 0x0020
-#define MACB_ISR 0x0024
-#define MACB_IER 0x0028
-#define MACB_IDR 0x002c
-#define MACB_IMR 0x0030
-#define MACB_MAN 0x0034
-#define MACB_PTR 0x0038
-#define MACB_PFR 0x003c
-#define MACB_FTO 0x0040
-#define MACB_SCF 0x0044
-#define MACB_MCF 0x0048
-#define MACB_FRO 0x004c
-#define MACB_FCSE 0x0050
-#define MACB_ALE 0x0054
-#define MACB_DTF 0x0058
-#define MACB_LCOL 0x005c
-#define MACB_EXCOL 0x0060
-#define MACB_TUND 0x0064
-#define MACB_CSE 0x0068
-#define MACB_RRE 0x006c
-#define MACB_ROVR 0x0070
-#define MACB_RSE 0x0074
-#define MACB_ELE 0x0078
-#define MACB_RJA 0x007c
-#define MACB_USF 0x0080
-#define MACB_STE 0x0084
-#define MACB_RLE 0x0088
-#define MACB_TPF 0x008c
-#define MACB_HRB 0x0090
-#define MACB_HRT 0x0094
-#define MACB_SA1B 0x0098
-#define MACB_SA1T 0x009c
-#define MACB_SA2B 0x00a0
-#define MACB_SA2T 0x00a4
-#define MACB_SA3B 0x00a8
-#define MACB_SA3T 0x00ac
-#define MACB_SA4B 0x00b0
-#define MACB_SA4T 0x00b4
-#define MACB_TID 0x00b8
-#define MACB_TPQ 0x00bc
-#define MACB_USRIO 0x00c0
-#define MACB_WOL 0x00c4
-#define MACB_MID 0x00fc
+#define MACB_NCR 0x0000 /* Network Control */
+#define MACB_NCFGR 0x0004 /* Network Config */
+#define MACB_NSR 0x0008 /* Network Status */
+#define MACB_TAR 0x000c /* AT91RM9200 only */
+#define MACB_TCR 0x0010 /* AT91RM9200 only */
+#define MACB_TSR 0x0014 /* Transmit Status */
+#define MACB_RBQP 0x0018 /* RX Q Base Address */
+#define MACB_TBQP 0x001c /* TX Q Base Address */
+#define MACB_RSR 0x0020 /* Receive Status */
+#define MACB_ISR 0x0024 /* Interrupt Status */
+#define MACB_IER 0x0028 /* Interrupt Enable */
+#define MACB_IDR 0x002c /* Interrupt Disable */
+#define MACB_IMR 0x0030 /* Interrupt Mask */
+#define MACB_MAN 0x0034 /* PHY Maintenance */
+#define MACB_PTR 0x0038
+#define MACB_PFR 0x003c
+#define MACB_FTO 0x0040
+#define MACB_SCF 0x0044
+#define MACB_MCF 0x0048
+#define MACB_FRO 0x004c
+#define MACB_FCSE 0x0050
+#define MACB_ALE 0x0054
+#define MACB_DTF 0x0058
+#define MACB_LCOL 0x005c
+#define MACB_EXCOL 0x0060
+#define MACB_TUND 0x0064
+#define MACB_CSE 0x0068
+#define MACB_RRE 0x006c
+#define MACB_ROVR 0x0070
+#define MACB_RSE 0x0074
+#define MACB_ELE 0x0078
+#define MACB_RJA 0x007c
+#define MACB_USF 0x0080
+#define MACB_STE 0x0084
+#define MACB_RLE 0x0088
+#define MACB_TPF 0x008c
+#define MACB_HRB 0x0090
+#define MACB_HRT 0x0094
+#define MACB_SA1B 0x0098
+#define MACB_SA1T 0x009c
+#define MACB_SA2B 0x00a0
+#define MACB_SA2T 0x00a4
+#define MACB_SA3B 0x00a8
+#define MACB_SA3T 0x00ac
+#define MACB_SA4B 0x00b0
+#define MACB_SA4T 0x00b4
+#define MACB_TID 0x00b8
+#define MACB_TPQ 0x00bc
+#define MACB_USRIO 0x00c0
+#define MACB_WOL 0x00c4
+#define MACB_MID 0x00fc
+#define MACB_TBQPH 0x04C8
+#define MACB_RBQPH 0x04D4
-/* GEM specific register offsets */
-#define GEM_DCFG1 0x0280
-#define GEM_DCFG6 0x0294
+/* GEM register offsets. */
+#define GEM_NCFGR 0x0004 /* Network Config */
+#define GEM_USRIO 0x000c /* User IO */
+#define GEM_DMACFG 0x0010 /* DMA Configuration */
+#define GEM_JML 0x0048 /* Jumbo Max Length */
+#define GEM_HRB 0x0080 /* Hash Bottom */
+#define GEM_HRT 0x0084 /* Hash Top */
+#define GEM_SA1B 0x0088 /* Specific1 Bottom */
+#define GEM_SA1T 0x008C /* Specific1 Top */
+#define GEM_SA2B 0x0090 /* Specific2 Bottom */
+#define GEM_SA2T 0x0094 /* Specific2 Top */
+#define GEM_SA3B 0x0098 /* Specific3 Bottom */
+#define GEM_SA3T 0x009C /* Specific3 Top */
+#define GEM_SA4B 0x00A0 /* Specific4 Bottom */
+#define GEM_SA4T 0x00A4 /* Specific4 Top */
+#define GEM_EFTSH 0x00e8 /* PTP Event Frame Transmitted Seconds Register 47:32 */
+#define GEM_EFRSH 0x00ec /* PTP Event Frame Received Seconds Register 47:32 */
+#define GEM_PEFTSH 0x00f0 /* PTP Peer Event Frame Transmitted Seconds Register 47:32 */
+#define GEM_PEFRSH 0x00f4 /* PTP Peer Event Frame Received Seconds Register 47:32 */
+#define GEM_OTX 0x0100 /* Octets transmitted */
+#define GEM_OCTTXL 0x0100 /* Octets transmitted [31:0] */
+#define GEM_OCTTXH 0x0104 /* Octets transmitted [47:32] */
+#define GEM_TXCNT 0x0108 /* Frames Transmitted counter */
+#define GEM_TXBCCNT 0x010c /* Broadcast Frames counter */
+#define GEM_TXMCCNT 0x0110 /* Multicast Frames counter */
+#define GEM_TXPAUSECNT 0x0114 /* Pause Frames Transmitted Counter */
+#define GEM_TX64CNT 0x0118 /* 64 byte Frames TX counter */
+#define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */
+#define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */
+#define GEM_TX256CNT 0x0124 /* 256-511 byte Frames TX counter */
+#define GEM_TX512CNT 0x0128 /* 512-1023 byte Frames TX counter */
+#define GEM_TX1024CNT 0x012c /* 1024-1518 byte Frames TX counter */
+#define GEM_TX1519CNT 0x0130 /* 1519+ byte Frames TX counter */
+#define GEM_TXURUNCNT 0x0134 /* TX under run error counter */
+#define GEM_SNGLCOLLCNT 0x0138 /* Single Collision Frame Counter */
+#define GEM_MULTICOLLCNT 0x013c /* Multiple Collision Frame Counter */
+#define GEM_EXCESSCOLLCNT 0x0140 /* Excessive Collision Frame Counter */
+#define GEM_LATECOLLCNT 0x0144 /* Late Collision Frame Counter */
+#define GEM_TXDEFERCNT 0x0148 /* Deferred Transmission Frame Counter */
+#define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error Counter */
+#define GEM_ORX 0x0150 /* Octets received */
+#define GEM_OCTRXL 0x0150 /* Octets received [31:0] */
+#define GEM_OCTRXH 0x0154 /* Octets received [47:32] */
+#define GEM_RXCNT 0x0158 /* Frames Received Counter */
+#define GEM_RXBROADCNT 0x015c /* Broadcast Frames Received Counter */
+#define GEM_RXMULTICNT 0x0160 /* Multicast Frames Received Counter */
+#define GEM_RXPAUSECNT 0x0164 /* Pause Frames Received Counter */
+#define GEM_RX64CNT 0x0168 /* 64 byte Frames RX Counter */
+#define GEM_RX65CNT 0x016c /* 65-127 byte Frames RX Counter */
+#define GEM_RX128CNT 0x0170 /* 128-255 byte Frames RX Counter */
+#define GEM_RX256CNT 0x0174 /* 256-511 byte Frames RX Counter */
+#define GEM_RX512CNT 0x0178 /* 512-1023 byte Frames RX Counter */
+#define GEM_RX1024CNT 0x017c /* 1024-1518 byte Frames RX Counter */
+#define GEM_RX1519CNT 0x0180 /* 1519+ byte Frames RX Counter */
+#define GEM_RXUNDRCNT 0x0184 /* Undersize Frames Received Counter */
+#define GEM_RXOVRCNT 0x0188 /* Oversize Frames Received Counter */
+#define GEM_RXJABCNT 0x018c /* Jabbers Received Counter */
+#define GEM_RXFCSCNT 0x0190 /* Frame Check Sequence Error Counter */
+#define GEM_RXLENGTHCNT 0x0194 /* Length Field Error Counter */
+#define GEM_RXSYMBCNT 0x0198 /* Symbol Error Counter */
+#define GEM_RXALIGNCNT 0x019c /* Alignment Error Counter */
+#define GEM_RXRESERRCNT 0x01a0 /* Receive Resource Error Counter */
+#define GEM_RXORCNT 0x01a4 /* Receive Overrun Counter */
+#define GEM_RXIPCCNT 0x01a8 /* IP header Checksum Error Counter */
+#define GEM_RXTCPCCNT 0x01ac /* TCP Checksum Error Counter */
+#define GEM_RXUDPCCNT 0x01b0 /* UDP Checksum Error Counter */
+#define GEM_TISUBN 0x01bc /* 1588 Timer Increment Sub-ns */
+#define GEM_TSH 0x01c0 /* 1588 Timer Seconds High */
+#define GEM_TSL 0x01d0 /* 1588 Timer Seconds Low */
+#define GEM_TN 0x01d4 /* 1588 Timer Nanoseconds */
+#define GEM_TA 0x01d8 /* 1588 Timer Adjust */
+#define GEM_TI 0x01dc /* 1588 Timer Increment */
+#define GEM_EFTSL 0x01e0 /* PTP Event Frame Tx Seconds Low */
+#define GEM_EFTN 0x01e4 /* PTP Event Frame Tx Nanoseconds */
+#define GEM_EFRSL 0x01e8 /* PTP Event Frame Rx Seconds Low */
+#define GEM_EFRN 0x01ec /* PTP Event Frame Rx Nanoseconds */
+#define GEM_PEFTSL 0x01f0 /* PTP Peer Event Frame Tx Secs Low */
+#define GEM_PEFTN 0x01f4 /* PTP Peer Event Frame Tx Ns */
+#define GEM_PEFRSL 0x01f8 /* PTP Peer Event Frame Rx Sec Low */
+#define GEM_PEFRN 0x01fc /* PTP Peer Event Frame Rx Ns */
+#define GEM_DCFG1 0x0280 /* Design Config 1 */
+#define GEM_DCFG2 0x0284 /* Design Config 2 */
+#define GEM_DCFG3 0x0288 /* Design Config 3 */
+#define GEM_DCFG4 0x028c /* Design Config 4 */
+#define GEM_DCFG5 0x0290 /* Design Config 5 */
+#define GEM_DCFG6 0x0294 /* Design Config 6 */
+#define GEM_DCFG7 0x0298 /* Design Config 7 */
+#define GEM_DCFG8 0x029C /* Design Config 8 */
+#define GEM_DCFG10 0x02A4 /* Design Config 10 */
-#define MACB_MAX_QUEUES 8
+#define GEM_TXBDCTRL 0x04cc /* TX Buffer Descriptor control register */
+#define GEM_RXBDCTRL 0x04d0 /* RX Buffer Descriptor control register */
-/* GEM specific multi queues register offset */
-/* hw_q can be 0~7 */
-#define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2))
+/* Screener Type 2 match registers */
+#define GEM_SCRT2 0x540
+
+/* EtherType registers */
+#define GEM_ETHT 0x06E0
+
+/* Type 2 compare registers */
+#define GEM_T2CMPW0 0x0700
+#define GEM_T2CMPW1 0x0704
+#define T2CMP_OFST(t2idx) (t2idx * 2)
+
+/* type 2 compare registers
+ * each location requires 3 compare regs
+ */
+#define GEM_IP4SRC_CMP(idx) (idx * 3)
+#define GEM_IP4DST_CMP(idx) (idx * 3 + 1)
+#define GEM_PORT_CMP(idx) (idx * 3 + 2)
+
+/* Which screening type 2 EtherType register will be used (0 - 7) */
+#define SCRT2_ETHT 0
+
+#define GEM_ISR(hw_q) (0x0400 + ((hw_q) << 2))
+#define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2))
+#define GEM_TBQPH(hw_q) (0x04C8)
+#define GEM_RBQP(hw_q) (0x0480 + ((hw_q) << 2))
+#define GEM_RBQS(hw_q) (0x04A0 + ((hw_q) << 2))
+#define GEM_RBQPH(hw_q) (0x04D4)
+#define GEM_IER(hw_q) (0x0600 + ((hw_q) << 2))
+#define GEM_IDR(hw_q) (0x0620 + ((hw_q) << 2))
+#define GEM_IMR(hw_q) (0x0640 + ((hw_q) << 2))
/* Bitfields in NCR */
-#define MACB_LB_OFFSET 0
-#define MACB_LB_SIZE 1
-#define MACB_LLB_OFFSET 1
-#define MACB_LLB_SIZE 1
-#define MACB_RE_OFFSET 2
-#define MACB_RE_SIZE 1
-#define MACB_TE_OFFSET 3
-#define MACB_TE_SIZE 1
-#define MACB_MPE_OFFSET 4
-#define MACB_MPE_SIZE 1
-#define MACB_CLRSTAT_OFFSET 5
-#define MACB_CLRSTAT_SIZE 1
-#define MACB_INCSTAT_OFFSET 6
-#define MACB_INCSTAT_SIZE 1
-#define MACB_WESTAT_OFFSET 7
-#define MACB_WESTAT_SIZE 1
-#define MACB_BP_OFFSET 8
-#define MACB_BP_SIZE 1
-#define MACB_TSTART_OFFSET 9
-#define MACB_TSTART_SIZE 1
-#define MACB_THALT_OFFSET 10
-#define MACB_THALT_SIZE 1
-#define MACB_NCR_TPF_OFFSET 11
-#define MACB_NCR_TPF_SIZE 1
-#define MACB_TZQ_OFFSET 12
-#define MACB_TZQ_SIZE 1
+#define MACB_LB_OFFSET 0 /* reserved */
+#define MACB_LB_SIZE 1
+#define MACB_LLB_OFFSET 1 /* Loop back local */
+#define MACB_LLB_SIZE 1
+#define MACB_RE_OFFSET 2 /* Receive enable */
+#define MACB_RE_SIZE 1
+#define MACB_TE_OFFSET 3 /* Transmit enable */
+#define MACB_TE_SIZE 1
+#define MACB_MPE_OFFSET 4 /* Management port enable */
+#define MACB_MPE_SIZE 1
+#define MACB_CLRSTAT_OFFSET 5 /* Clear stats regs */
+#define MACB_CLRSTAT_SIZE 1
+#define MACB_INCSTAT_OFFSET 6 /* Incremental stats regs */
+#define MACB_INCSTAT_SIZE 1
+#define MACB_WESTAT_OFFSET 7 /* Write enable stats regs */
+#define MACB_WESTAT_SIZE 1
+#define MACB_BP_OFFSET 8 /* Back pressure */
+#define MACB_BP_SIZE 1
+#define MACB_TSTART_OFFSET 9 /* Start transmission */
+#define MACB_TSTART_SIZE 1
+#define MACB_THALT_OFFSET 10 /* Transmit halt */
+#define MACB_THALT_SIZE 1
+#define MACB_NCR_TPF_OFFSET 11 /* Transmit pause frame */
+#define MACB_NCR_TPF_SIZE 1
+#define MACB_TZQ_OFFSET 12 /* Transmit zero quantum pause frame */
+#define MACB_TZQ_SIZE 1
+#define MACB_SRTSM_OFFSET 15
+#define MACB_OSSMODE_OFFSET 24 /* Enable One Step Synchro Mode */
+#define MACB_OSSMODE_SIZE 1
/* Bitfields in NCFGR */
-#define MACB_SPD_OFFSET 0
-#define MACB_SPD_SIZE 1
-#define MACB_FD_OFFSET 1
-#define MACB_FD_SIZE 1
-#define MACB_BIT_RATE_OFFSET 2
-#define MACB_BIT_RATE_SIZE 1
-#define MACB_JFRAME_OFFSET 3
-#define MACB_JFRAME_SIZE 1
-#define MACB_CAF_OFFSET 4
-#define MACB_CAF_SIZE 1
-#define MACB_NBC_OFFSET 5
-#define MACB_NBC_SIZE 1
-#define MACB_NCFGR_MTI_OFFSET 6
-#define MACB_NCFGR_MTI_SIZE 1
-#define MACB_UNI_OFFSET 7
-#define MACB_UNI_SIZE 1
-#define MACB_BIG_OFFSET 8
-#define MACB_BIG_SIZE 1
-#define MACB_EAE_OFFSET 9
-#define MACB_EAE_SIZE 1
-#define MACB_CLK_OFFSET 10
-#define MACB_CLK_SIZE 2
-#define MACB_RTY_OFFSET 12
-#define MACB_RTY_SIZE 1
-#define MACB_PAE_OFFSET 13
-#define MACB_PAE_SIZE 1
-#define MACB_RBOF_OFFSET 14
-#define MACB_RBOF_SIZE 2
-#define MACB_RLCE_OFFSET 16
-#define MACB_RLCE_SIZE 1
-#define MACB_DRFCS_OFFSET 17
-#define MACB_DRFCS_SIZE 1
-#define MACB_EFRHD_OFFSET 18
-#define MACB_EFRHD_SIZE 1
-#define MACB_IRXFCS_OFFSET 19
-#define MACB_IRXFCS_SIZE 1
+#define MACB_SPD_OFFSET 0 /* Speed */
+#define MACB_SPD_SIZE 1
+#define MACB_FD_OFFSET 1 /* Full duplex */
+#define MACB_FD_SIZE 1
+#define MACB_BIT_RATE_OFFSET 2 /* Discard non-VLAN frames */
+#define MACB_BIT_RATE_SIZE 1
+#define MACB_JFRAME_OFFSET 3 /* reserved */
+#define MACB_JFRAME_SIZE 1
+#define MACB_CAF_OFFSET 4 /* Copy all frames */
+#define MACB_CAF_SIZE 1
+#define MACB_NBC_OFFSET 5 /* No broadcast */
+#define MACB_NBC_SIZE 1
+#define MACB_NCFGR_MTI_OFFSET 6 /* Multicast hash enable */
+#define MACB_NCFGR_MTI_SIZE 1
+#define MACB_UNI_OFFSET 7 /* Unicast hash enable */
+#define MACB_UNI_SIZE 1
+#define MACB_BIG_OFFSET 8 /* Receive 1536 byte frames */
+#define MACB_BIG_SIZE 1
+#define MACB_EAE_OFFSET 9 /* External address match enable */
+#define MACB_EAE_SIZE 1
+#define MACB_CLK_OFFSET 10
+#define MACB_CLK_SIZE 2
+#define MACB_RTY_OFFSET 12 /* Retry test */
+#define MACB_RTY_SIZE 1
+#define MACB_PAE_OFFSET 13 /* Pause enable */
+#define MACB_PAE_SIZE 1
+#define MACB_RM9200_RMII_OFFSET 13 /* AT91RM9200 only */
+#define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */
+#define MACB_RBOF_OFFSET 14 /* Receive buffer offset */
+#define MACB_RBOF_SIZE 2
+#define MACB_RLCE_OFFSET 16 /* Length field error frame discard */
+#define MACB_RLCE_SIZE 1
+#define MACB_DRFCS_OFFSET 17 /* FCS remove */
+#define MACB_DRFCS_SIZE 1
+#define MACB_EFRHD_OFFSET 18
+#define MACB_EFRHD_SIZE 1
+#define MACB_IRXFCS_OFFSET 19
+#define MACB_IRXFCS_SIZE 1
-#define GEM_GBE_OFFSET 10
-#define GEM_GBE_SIZE 1
-#define GEM_CLK_OFFSET 18
-#define GEM_CLK_SIZE 3
-#define GEM_DBW_OFFSET 21
-#define GEM_DBW_SIZE 2
+/* GEM specific NCFGR bitfields. */
+#define GEM_GBE_OFFSET 10 /* Gigabit mode enable */
+#define GEM_GBE_SIZE 1
+#define GEM_PCSSEL_OFFSET 11
+#define GEM_PCSSEL_SIZE 1
+#define GEM_CLK_OFFSET 18 /* MDC clock division */
+#define GEM_CLK_SIZE 3
+#define GEM_DBW_OFFSET 21 /* Data bus width */
+#define GEM_DBW_SIZE 2
+#define GEM_RXCOEN_OFFSET 24
+#define GEM_RXCOEN_SIZE 1
+#define GEM_SGMIIEN_OFFSET 27
+#define GEM_SGMIIEN_SIZE 1
+
+
+/* Constants for data bus width. */
+#define GEM_DBW32 0 /* 32 bit AMBA AHB data bus width */
+#define GEM_DBW64 1 /* 64 bit AMBA AHB data bus width */
+#define GEM_DBW128 2 /* 128 bit AMBA AHB data bus width */
+
+/* Bitfields in DMACFG. */
+#define GEM_FBLDO_OFFSET 0 /* fixed burst length for DMA */
+#define GEM_FBLDO_SIZE 5
+#define GEM_ENDIA_DESC_OFFSET 6 /* endian swap mode for management descriptor access */
+#define GEM_ENDIA_DESC_SIZE 1
+#define GEM_ENDIA_PKT_OFFSET 7 /* endian swap mode for packet data access */
+#define GEM_ENDIA_PKT_SIZE 1
+#define GEM_RXBMS_OFFSET 8 /* RX packet buffer memory size select */
+#define GEM_RXBMS_SIZE 2
+#define GEM_TXPBMS_OFFSET 10 /* TX packet buffer memory size select */
+#define GEM_TXPBMS_SIZE 1
+#define GEM_TXCOEN_OFFSET 11 /* TX IP/TCP/UDP checksum gen offload */
+#define GEM_TXCOEN_SIZE 1
+#define GEM_RXBS_OFFSET 16 /* DMA receive buffer size */
+#define GEM_RXBS_SIZE 8
+#define GEM_DDRP_OFFSET 24 /* disc_when_no_ahb */
+#define GEM_DDRP_SIZE 1
+#define GEM_RXEXT_OFFSET 28 /* RX extended Buffer Descriptor mode */
+#define GEM_RXEXT_SIZE 1
+#define GEM_TXEXT_OFFSET 29 /* TX extended Buffer Descriptor mode */
+#define GEM_TXEXT_SIZE 1
+#define GEM_ADDR64_OFFSET 30 /* Address bus width - 64b or 32b */
+#define GEM_ADDR64_SIZE 1
+
/* Bitfields in NSR */
-#define MACB_NSR_LINK_OFFSET 0
-#define MACB_NSR_LINK_SIZE 1
-#define MACB_MDIO_OFFSET 1
-#define MACB_MDIO_SIZE 1
-#define MACB_IDLE_OFFSET 2
-#define MACB_IDLE_SIZE 1
-
-/* Bitfields in UR */
-#define GEM_RGMII_OFFSET 0
-#define GEM_RGMII_SIZE 1
+#define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */
+#define MACB_NSR_LINK_SIZE 1
+#define MACB_MDIO_OFFSET 1 /* status of the mdio_in pin */
+#define MACB_MDIO_SIZE 1
+#define MACB_IDLE_OFFSET 2 /* The PHY management logic is idle */
+#define MACB_IDLE_SIZE 1
/* Bitfields in TSR */
-#define MACB_UBR_OFFSET 0
-#define MACB_UBR_SIZE 1
-#define MACB_COL_OFFSET 1
-#define MACB_COL_SIZE 1
-#define MACB_TSR_RLE_OFFSET 2
-#define MACB_TSR_RLE_SIZE 1
-#define MACB_TGO_OFFSET 3
-#define MACB_TGO_SIZE 1
-#define MACB_BEX_OFFSET 4
-#define MACB_BEX_SIZE 1
-#define MACB_COMP_OFFSET 5
-#define MACB_COMP_SIZE 1
-#define MACB_UND_OFFSET 6
-#define MACB_UND_SIZE 1
+#define MACB_UBR_OFFSET 0 /* Used bit read */
+#define MACB_UBR_SIZE 1
+#define MACB_COL_OFFSET 1 /* Collision occurred */
+#define MACB_COL_SIZE 1
+#define MACB_TSR_RLE_OFFSET 2 /* Retry limit exceeded */
+#define MACB_TSR_RLE_SIZE 1
+#define MACB_TGO_OFFSET 3 /* Transmit go */
+#define MACB_TGO_SIZE 1
+#define MACB_BEX_OFFSET 4 /* TX frame corruption due to AHB error */
+#define MACB_BEX_SIZE 1
+#define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */
+#define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */
+#define MACB_COMP_OFFSET 5 /* Trnasmit complete */
+#define MACB_COMP_SIZE 1
+#define MACB_UND_OFFSET 6 /* Trnasmit under run */
+#define MACB_UND_SIZE 1
/* Bitfields in RSR */
-#define MACB_BNA_OFFSET 0
-#define MACB_BNA_SIZE 1
-#define MACB_REC_OFFSET 1
-#define MACB_REC_SIZE 1
-#define MACB_OVR_OFFSET 2
-#define MACB_OVR_SIZE 1
+#define MACB_BNA_OFFSET 0 /* Buffer not available */
+#define MACB_BNA_SIZE 1
+#define MACB_REC_OFFSET 1 /* Frame received */
+#define MACB_REC_SIZE 1
+#define MACB_OVR_OFFSET 2 /* Receive overrun */
+#define MACB_OVR_SIZE 1
/* Bitfields in ISR/IER/IDR/IMR */
-#define MACB_MFD_OFFSET 0
-#define MACB_MFD_SIZE 1
-#define MACB_RCOMP_OFFSET 1
-#define MACB_RCOMP_SIZE 1
-#define MACB_RXUBR_OFFSET 2
-#define MACB_RXUBR_SIZE 1
-#define MACB_TXUBR_OFFSET 3
-#define MACB_TXUBR_SIZE 1
-#define MACB_ISR_TUND_OFFSET 4
-#define MACB_ISR_TUND_SIZE 1
-#define MACB_ISR_RLE_OFFSET 5
-#define MACB_ISR_RLE_SIZE 1
-#define MACB_TXERR_OFFSET 6
-#define MACB_TXERR_SIZE 1
-#define MACB_TCOMP_OFFSET 7
-#define MACB_TCOMP_SIZE 1
-#define MACB_ISR_LINK_OFFSET 9
-#define MACB_ISR_LINK_SIZE 1
-#define MACB_ISR_ROVR_OFFSET 10
-#define MACB_ISR_ROVR_SIZE 1
-#define MACB_HRESP_OFFSET 11
-#define MACB_HRESP_SIZE 1
-#define MACB_PFR_OFFSET 12
-#define MACB_PFR_SIZE 1
-#define MACB_PTZ_OFFSET 13
-#define MACB_PTZ_SIZE 1
+#define MACB_MFD_OFFSET 0 /* Management frame sent */
+#define MACB_MFD_SIZE 1
+#define MACB_RCOMP_OFFSET 1 /* Receive complete */
+#define MACB_RCOMP_SIZE 1
+#define MACB_RXUBR_OFFSET 2 /* RX used bit read */
+#define MACB_RXUBR_SIZE 1
+#define MACB_TXUBR_OFFSET 3 /* TX used bit read */
+#define MACB_TXUBR_SIZE 1
+#define MACB_ISR_TUND_OFFSET 4 /* Enable TX buffer under run interrupt */
+#define MACB_ISR_TUND_SIZE 1
+#define MACB_ISR_RLE_OFFSET 5 /* EN retry exceeded/late coll interrupt */
+#define MACB_ISR_RLE_SIZE 1
+#define MACB_TXERR_OFFSET 6 /* EN TX frame corrupt from error interrupt */
+#define MACB_TXERR_SIZE 1
+#define MACB_TCOMP_OFFSET 7 /* Enable transmit complete interrupt */
+#define MACB_TCOMP_SIZE 1
+#define MACB_ISR_LINK_OFFSET 9 /* Enable link change interrupt */
+#define MACB_ISR_LINK_SIZE 1
+#define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun interrupt */
+#define MACB_ISR_ROVR_SIZE 1
+#define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK interrupt */
+#define MACB_HRESP_SIZE 1
+#define MACB_PFR_OFFSET 12 /* Enable pause frame w/ quantum interrupt */
+#define MACB_PFR_SIZE 1
+#define MACB_PTZ_OFFSET 13 /* Enable pause time zero interrupt */
+#define MACB_PTZ_SIZE 1
+#define MACB_WOL_OFFSET 14 /* Enable wake-on-lan interrupt */
+#define MACB_WOL_SIZE 1
+#define MACB_DRQFR_OFFSET 18 /* PTP Delay Request Frame Received */
+#define MACB_DRQFR_SIZE 1
+#define MACB_SFR_OFFSET 19 /* PTP Sync Frame Received */
+#define MACB_SFR_SIZE 1
+#define MACB_DRQFT_OFFSET 20 /* PTP Delay Request Frame Transmitted */
+#define MACB_DRQFT_SIZE 1
+#define MACB_SFT_OFFSET 21 /* PTP Sync Frame Transmitted */
+#define MACB_SFT_SIZE 1
+#define MACB_PDRQFR_OFFSET 22 /* PDelay Request Frame Received */
+#define MACB_PDRQFR_SIZE 1
+#define MACB_PDRSFR_OFFSET 23 /* PDelay Response Frame Received */
+#define MACB_PDRSFR_SIZE 1
+#define MACB_PDRQFT_OFFSET 24 /* PDelay Request Frame Transmitted */
+#define MACB_PDRQFT_SIZE 1
+#define MACB_PDRSFT_OFFSET 25 /* PDelay Response Frame Transmitted */
+#define MACB_PDRSFT_SIZE 1
+#define MACB_SRI_OFFSET 26 /* TSU Seconds Register Increment */
+#define MACB_SRI_SIZE 1
+
+/* Timer increment fields */
+#define MACB_TI_CNS_OFFSET 0
+#define MACB_TI_CNS_SIZE 8
+#define MACB_TI_ACNS_OFFSET 8
+#define MACB_TI_ACNS_SIZE 8
+#define MACB_TI_NIT_OFFSET 16
+#define MACB_TI_NIT_SIZE 8
/* Bitfields in MAN */
-#define MACB_DATA_OFFSET 0
-#define MACB_DATA_SIZE 16
-#define MACB_CODE_OFFSET 16
-#define MACB_CODE_SIZE 2
-#define MACB_REGA_OFFSET 18
-#define MACB_REGA_SIZE 5
-#define MACB_PHYA_OFFSET 23
-#define MACB_PHYA_SIZE 5
-#define MACB_RW_OFFSET 28
-#define MACB_RW_SIZE 2
-#define MACB_SOF_OFFSET 30
-#define MACB_SOF_SIZE 2
+#define MACB_DATA_OFFSET 0 /* data */
+#define MACB_DATA_SIZE 16
+#define MACB_CODE_OFFSET 16 /* Must be written to 10 */
+#define MACB_CODE_SIZE 2
+#define MACB_REGA_OFFSET 18 /* Register address */
+#define MACB_REGA_SIZE 5
+#define MACB_PHYA_OFFSET 23 /* PHY address */
+#define MACB_PHYA_SIZE 5
+#define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01 is write. */
+#define MACB_RW_SIZE 2
+#define MACB_SOF_OFFSET 30 /* Must be written to 1 for Clause 22 */
+#define MACB_SOF_SIZE 2
-/* Bitfields in USRIO */
+/* Bitfields in USRIO (AVR32) */
#define MACB_MII_OFFSET 0
#define MACB_MII_SIZE 1
#define MACB_EAM_OFFSET 1
@@ -232,6 +421,8 @@
/* Bitfields in USRIO (AT91) */
#define MACB_RMII_OFFSET 0
#define MACB_RMII_SIZE 1
+#define GEM_RGMII_OFFSET 0 /* GEM gigabit mode */
+#define GEM_RGMII_SIZE 1
#define MACB_CLKEN_OFFSET 1
#define MACB_CLKEN_SIZE 1
@@ -249,17 +440,166 @@
/* Bitfields in MID */
#define MACB_IDNUM_OFFSET 16
-#define MACB_IDNUM_SIZE 16
+#define MACB_IDNUM_SIZE 12
+#define MACB_REV_OFFSET 0
+#define MACB_REV_SIZE 16
-/* Bitfields in DCFG1 */
+/* Bitfields in DCFG1. */
+#define GEM_IRQCOR_OFFSET 23
+#define GEM_IRQCOR_SIZE 1
#define GEM_DBWDEF_OFFSET 25
#define GEM_DBWDEF_SIZE 3
-/* constants for data bus width */
-#define GEM_DBW32 0
-#define GEM_DBW64 1
-#define GEM_DBW128 2
+/* Bitfields in DCFG2. */
+#define GEM_RX_PKT_BUFF_OFFSET 20
+#define GEM_RX_PKT_BUFF_SIZE 1
+#define GEM_TX_PKT_BUFF_OFFSET 21
+#define GEM_TX_PKT_BUFF_SIZE 1
+
+/* Bitfields in DCFG5. */
+#define GEM_TSU_OFFSET 8
+#define GEM_TSU_SIZE 1
+
+/* Bitfields in DCFG6. */
+#define GEM_PBUF_LSO_OFFSET 27
+#define GEM_PBUF_LSO_SIZE 1
+#define GEM_DAW64_OFFSET 23
+#define GEM_DAW64_SIZE 1
+
+/* Bitfields in DCFG8. */
+#define GEM_T1SCR_OFFSET 24
+#define GEM_T1SCR_SIZE 8
+#define GEM_T2SCR_OFFSET 16
+#define GEM_T2SCR_SIZE 8
+#define GEM_SCR2ETH_OFFSET 8
+#define GEM_SCR2ETH_SIZE 8
+#define GEM_SCR2CMP_OFFSET 0
+#define GEM_SCR2CMP_SIZE 8
+
+/* Bitfields in DCFG10 */
+#define GEM_TXBD_RDBUFF_OFFSET 12
+#define GEM_TXBD_RDBUFF_SIZE 4
+#define GEM_RXBD_RDBUFF_OFFSET 8
+#define GEM_RXBD_RDBUFF_SIZE 4
+
+/* Bitfields in TISUBN */
+#define GEM_SUBNSINCR_OFFSET 0
+#define GEM_SUBNSINCR_SIZE 16
+
+/* Bitfields in TI */
+#define GEM_NSINCR_OFFSET 0
+#define GEM_NSINCR_SIZE 8
+
+/* Bitfields in TSH */
+#define GEM_TSH_OFFSET 0 /* TSU timer value (s). MSB [47:32] of seconds timer count */
+#define GEM_TSH_SIZE 16
+
+/* Bitfields in TSL */
+#define GEM_TSL_OFFSET 0 /* TSU timer value (s). LSB [31:0] of seconds timer count */
+#define GEM_TSL_SIZE 32
+
+/* Bitfields in TN */
+#define GEM_TN_OFFSET 0 /* TSU timer value (ns) */
+#define GEM_TN_SIZE 30
+
+/* Bitfields in TXBDCTRL */
+#define GEM_TXTSMODE_OFFSET 4 /* TX Descriptor Timestamp Insertion mode */
+#define GEM_TXTSMODE_SIZE 2
+
+/* Bitfields in RXBDCTRL */
+#define GEM_RXTSMODE_OFFSET 4 /* RX Descriptor Timestamp Insertion mode */
+#define GEM_RXTSMODE_SIZE 2
+
+/* Bitfields in SCRT2 */
+#define GEM_QUEUE_OFFSET 0 /* Queue Number */
+#define GEM_QUEUE_SIZE 4
+#define GEM_VLANPR_OFFSET 4 /* VLAN Priority */
+#define GEM_VLANPR_SIZE 3
+#define GEM_VLANEN_OFFSET 8 /* VLAN Enable */
+#define GEM_VLANEN_SIZE 1
+#define GEM_ETHT2IDX_OFFSET 9 /* Index to screener type 2 EtherType register */
+#define GEM_ETHT2IDX_SIZE 3
+#define GEM_ETHTEN_OFFSET 12 /* EtherType Enable */
+#define GEM_ETHTEN_SIZE 1
+#define GEM_CMPA_OFFSET 13 /* Compare A - Index to screener type 2 Compare register */
+#define GEM_CMPA_SIZE 5
+#define GEM_CMPAEN_OFFSET 18 /* Compare A Enable */
+#define GEM_CMPAEN_SIZE 1
+#define GEM_CMPB_OFFSET 19 /* Compare B - Index to screener type 2 Compare register */
+#define GEM_CMPB_SIZE 5
+#define GEM_CMPBEN_OFFSET 24 /* Compare B Enable */
+#define GEM_CMPBEN_SIZE 1
+#define GEM_CMPC_OFFSET 25 /* Compare C - Index to screener type 2 Compare register */
+#define GEM_CMPC_SIZE 5
+#define GEM_CMPCEN_OFFSET 30 /* Compare C Enable */
+#define GEM_CMPCEN_SIZE 1
+
+/* Bitfields in ETHT */
+#define GEM_ETHTCMP_OFFSET 0 /* EtherType compare value */
+#define GEM_ETHTCMP_SIZE 16
+
+/* Bitfields in T2CMPW0 */
+#define GEM_T2CMP_OFFSET 16 /* 0xFFFF0000 compare value */
+#define GEM_T2CMP_SIZE 16
+#define GEM_T2MASK_OFFSET 0 /* 0x0000FFFF compare value or mask */
+#define GEM_T2MASK_SIZE 16
+
+/* Bitfields in T2CMPW1 */
+#define GEM_T2DISMSK_OFFSET 9 /* disable mask */
+#define GEM_T2DISMSK_SIZE 1
+#define GEM_T2CMPOFST_OFFSET 7 /* compare offset */
+#define GEM_T2CMPOFST_SIZE 2
+#define GEM_T2OFST_OFFSET 0 /* offset value */
+#define GEM_T2OFST_SIZE 7
+
+/* Offset for screener type 2 compare values (T2CMPOFST).
+ * Note the offset is applied after the specified point,
+ * e.g. GEM_T2COMPOFST_ETYPE denotes the EtherType field, so an offset
+ * of 12 bytes from this would be the source IP address in an IP header
+ */
+#define GEM_T2COMPOFST_SOF 0
+#define GEM_T2COMPOFST_ETYPE 1
+#define GEM_T2COMPOFST_IPHDR 2
+#define GEM_T2COMPOFST_TCPUDP 3
+
+/* offset from EtherType to IP address */
+#define ETYPE_SRCIP_OFFSET 12
+#define ETYPE_DSTIP_OFFSET 16
+
+/* offset from IP header to port */
+#define IPHDR_SRCPORT_OFFSET 0
+#define IPHDR_DSTPORT_OFFSET 2
+
+/* Transmit DMA buffer descriptor Word 1 */
+#define GEM_DMA_TXVALID_OFFSET 23 /* timestamp has been captured in the Buffer Descriptor */
+#define GEM_DMA_TXVALID_SIZE 1
+
+/* Receive DMA buffer descriptor Word 0 */
+#define GEM_DMA_RXVALID_OFFSET 2 /* indicates a valid timestamp in the Buffer Descriptor */
+#define GEM_DMA_RXVALID_SIZE 1
+
+/* DMA buffer descriptor Word 2 (32 bit addressing) or Word 4 (64 bit addressing) */
+#define GEM_DMA_SECL_OFFSET 30 /* Timestamp seconds[1:0] */
+#define GEM_DMA_SECL_SIZE 2
+#define GEM_DMA_NSEC_OFFSET 0 /* Timestamp nanosecs [29:0] */
+#define GEM_DMA_NSEC_SIZE 30
+
+/* DMA buffer descriptor Word 3 (32 bit addressing) or Word 5 (64 bit addressing) */
+
+/* New hardware supports 12 bit precision of timestamp in DMA buffer descriptor.
+ * Old hardware supports only 6 bit precision but it is enough for PTP.
+ * Less accuracy is used always instead of checking hardware version.
+ */
+#define GEM_DMA_SECH_OFFSET 0 /* Timestamp seconds[5:2] */
+#define GEM_DMA_SECH_SIZE 4
+#define GEM_DMA_SEC_WIDTH (GEM_DMA_SECH_SIZE + GEM_DMA_SECL_SIZE)
+#define GEM_DMA_SEC_TOP (1 << GEM_DMA_SEC_WIDTH)
+#define GEM_DMA_SEC_MASK (GEM_DMA_SEC_TOP - 1)
+
+/* Bitfields in ADJ */
+#define GEM_ADDSUB_OFFSET 31
+#define GEM_ADDSUB_SIZE 1
/* Constants for CLK */
#define MACB_CLK_DIV8 0
#define MACB_CLK_DIV16 1
@@ -273,6 +613,8 @@
#define GEM_CLK_DIV48 3
#define GEM_CLK_DIV64 4
#define GEM_CLK_DIV96 5
+#define GEM_CLK_DIV128 6
+#define GEM_CLK_DIV224 7
/* Constants for MAN register */
#define MACB_MAN_SOF 1
@@ -280,19 +622,38 @@
#define MACB_MAN_READ 2
#define MACB_MAN_CODE 2
+/* Capability mask bits */
+#define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x00000001
+#define MACB_CAPS_USRIO_HAS_CLKEN 0x00000002
+#define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII 0x00000004
+#define MACB_CAPS_NO_GIGABIT_HALF 0x00000008
+#define MACB_CAPS_USRIO_DISABLED 0x00000010
+#define MACB_CAPS_JUMBO 0x00000020
+#define MACB_CAPS_GEM_HAS_PTP 0x00000040
+#define MACB_CAPS_BD_RD_PREFETCH 0x00000080
+#define MACB_CAPS_NEEDS_RSTONUBR 0x00000100
+#define MACB_CAPS_FIFO_MODE 0x10000000
+#define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000
+#define MACB_CAPS_SG_DISABLED 0x40000000
+#define MACB_CAPS_MACB_IS_GEM 0x80000000
+
+/* LSO settings */
+#define MACB_LSO_UFO_ENABLE 0x01
+#define MACB_LSO_TSO_ENABLE 0x02
+
/* Bit manipulation macros */
#define MACB_BIT(name) \
(1 << MACB_##name##_OFFSET)
-#define MACB_BF(name, value) \
+#define MACB_BF(name,value) \
(((value) & ((1 << MACB_##name##_SIZE) - 1)) \
<< MACB_##name##_OFFSET)
-#define MACB_BFEXT(name, value)\
+#define MACB_BFEXT(name,value)\
(((value) >> MACB_##name##_OFFSET) \
& ((1 << MACB_##name##_SIZE) - 1))
-#define MACB_BFINS(name, value, old) \
+#define MACB_BFINS(name,value,old) \
(((old) & ~(((1 << MACB_##name##_SIZE) - 1) \
<< MACB_##name##_OFFSET)) \
- | MACB_BF(name, value))
+ | MACB_BF(name,value))
#define GEM_BIT(name) \
(1 << GEM_##name##_OFFSET)
@@ -316,6 +677,95 @@
readl((port)->regs + GEM_##reg)
#define gem_writel(port, reg, value) \
writel((value), (port)->regs + GEM_##reg)
+
+/* DMA descriptor bitfields */
+#define MACB_RX_USED_OFFSET 0
+#define MACB_RX_USED_SIZE 1
+#define MACB_RX_WRAP_OFFSET 1
+#define MACB_RX_WRAP_SIZE 1
+#define MACB_RX_WADDR_OFFSET 2
+#define MACB_RX_WADDR_SIZE 30
+
+#define MACB_RX_FRMLEN_OFFSET 0
+#define MACB_RX_FRMLEN_SIZE 12
+#define MACB_RX_OFFSET_OFFSET 12
+#define MACB_RX_OFFSET_SIZE 2
+#define MACB_RX_SOF_OFFSET 14
+#define MACB_RX_SOF_SIZE 1
+#define MACB_RX_EOF_OFFSET 15
+#define MACB_RX_EOF_SIZE 1
+#define MACB_RX_CFI_OFFSET 16
+#define MACB_RX_CFI_SIZE 1
+#define MACB_RX_VLAN_PRI_OFFSET 17
+#define MACB_RX_VLAN_PRI_SIZE 3
+#define MACB_RX_PRI_TAG_OFFSET 20
+#define MACB_RX_PRI_TAG_SIZE 1
+#define MACB_RX_VLAN_TAG_OFFSET 21
+#define MACB_RX_VLAN_TAG_SIZE 1
+#define MACB_RX_TYPEID_MATCH_OFFSET 22
+#define MACB_RX_TYPEID_MATCH_SIZE 1
+#define MACB_RX_SA4_MATCH_OFFSET 23
+#define MACB_RX_SA4_MATCH_SIZE 1
+#define MACB_RX_SA3_MATCH_OFFSET 24
+#define MACB_RX_SA3_MATCH_SIZE 1
+#define MACB_RX_SA2_MATCH_OFFSET 25
+#define MACB_RX_SA2_MATCH_SIZE 1
+#define MACB_RX_SA1_MATCH_OFFSET 26
+#define MACB_RX_SA1_MATCH_SIZE 1
+#define MACB_RX_EXT_MATCH_OFFSET 28
+#define MACB_RX_EXT_MATCH_SIZE 1
+#define MACB_RX_UHASH_MATCH_OFFSET 29
+#define MACB_RX_UHASH_MATCH_SIZE 1
+#define MACB_RX_MHASH_MATCH_OFFSET 30
+#define MACB_RX_MHASH_MATCH_SIZE 1
+#define MACB_RX_BROADCAST_OFFSET 31
+#define MACB_RX_BROADCAST_SIZE 1
+
+#define MACB_RX_FRMLEN_MASK 0xFFF
+#define MACB_RX_JFRMLEN_MASK 0x3FFF
+
+/* RX checksum offload disabled: bit 24 clear in NCFGR */
+#define GEM_RX_TYPEID_MATCH_OFFSET 22
+#define GEM_RX_TYPEID_MATCH_SIZE 2
+
+/* RX checksum offload enabled: bit 24 set in NCFGR */
+#define GEM_RX_CSUM_OFFSET 22
+#define GEM_RX_CSUM_SIZE 2
+
+#define MACB_TX_FRMLEN_OFFSET 0
+#define MACB_TX_FRMLEN_SIZE 11
+#define MACB_TX_LAST_OFFSET 15
+#define MACB_TX_LAST_SIZE 1
+#define MACB_TX_NOCRC_OFFSET 16
+#define MACB_TX_NOCRC_SIZE 1
+#define MACB_MSS_MFS_OFFSET 16
+#define MACB_MSS_MFS_SIZE 14
+#define MACB_TX_LSO_OFFSET 17
+#define MACB_TX_LSO_SIZE 2
+#define MACB_TX_TCP_SEQ_SRC_OFFSET 19
+#define MACB_TX_TCP_SEQ_SRC_SIZE 1
+#define MACB_TX_BUF_EXHAUSTED_OFFSET 27
+#define MACB_TX_BUF_EXHAUSTED_SIZE 1
+#define MACB_TX_UNDERRUN_OFFSET 28
+#define MACB_TX_UNDERRUN_SIZE 1
+#define MACB_TX_ERROR_OFFSET 29
+#define MACB_TX_ERROR_SIZE 1
+#define MACB_TX_WRAP_OFFSET 30
+#define MACB_TX_WRAP_SIZE 1
+#define MACB_TX_USED_OFFSET 31
+#define MACB_TX_USED_SIZE 1
+
+#define GEM_TX_FRMLEN_OFFSET 0
+#define GEM_TX_FRMLEN_SIZE 14
+
+/* Buffer descriptor constants */
+#define GEM_RX_CSUM_NONE 0
+#define GEM_RX_CSUM_IP_ONLY 1
+#define GEM_RX_CSUM_IP_TCP 2
+#define GEM_RX_CSUM_IP_UDP 3
+
+/* limit RX checksum offload to TCP and UDP packets */
+#define GEM_RX_CSUM_CHECKED_MASK 2
#define gem_writel_queue_TBQP(port, value, queue_num) \
writel((value), (port)->regs + GEM_TBQP(queue_num))
diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c
index 2b54e3a..fb93041 100644
--- a/drivers/net/mcffec.c
+++ b/drivers/net/mcffec.c
@@ -8,7 +8,7 @@
*/
#include <common.h>
-#include <environment.h>
+#include <env.h>
#include <malloc.h>
#include <command.h>
diff --git a/drivers/net/mdio_mux_i2creg.c b/drivers/net/mdio_mux_i2creg.c
new file mode 100644
index 0000000..3e82898
--- /dev/null
+++ b/drivers/net/mdio_mux_i2creg.c
@@ -0,0 +1,108 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019
+ * Alex Marginean, NXP
+ */
+
+#include <dm.h>
+#include <errno.h>
+#include <miiphy.h>
+#include <i2c.h>
+
+/*
+ * This driver is used for MDIO muxes driven by writing to a register of an I2C
+ * chip. The board it was developed for uses a mux controlled by on-board FPGA
+ * which in turn is accessed as a chip over I2C.
+ */
+
+struct mdio_mux_i2creg_priv {
+ struct udevice *chip;
+ int reg;
+ int mask;
+};
+
+static int mdio_mux_i2creg_select(struct udevice *mux, int cur, int sel)
+{
+ struct mdio_mux_i2creg_priv *priv = dev_get_priv(mux);
+ u8 val, val_old;
+
+ /* if last selection didn't change we're good to go */
+ if (cur == sel)
+ return 0;
+
+ val_old = dm_i2c_reg_read(priv->chip, priv->reg);
+ val = (val_old & ~priv->mask) | (sel & priv->mask);
+ debug("%s: chip %s, reg %x, val %x => %x\n", __func__, priv->chip->name,
+ priv->reg, val_old, val);
+ dm_i2c_reg_write(priv->chip, priv->reg, val);
+
+ return 0;
+}
+
+static const struct mdio_mux_ops mdio_mux_i2creg_ops = {
+ .select = mdio_mux_i2creg_select,
+};
+
+static int mdio_mux_i2creg_probe(struct udevice *dev)
+{
+ struct mdio_mux_i2creg_priv *priv = dev_get_priv(dev);
+ ofnode chip_node, bus_node;
+ struct udevice *i2c_bus;
+ u32 reg_mask[2];
+ u32 chip_addr;
+ int err;
+
+ /* read the register addr/mask pair */
+ err = dev_read_u32_array(dev, "mux-reg-masks", reg_mask, 2);
+ if (err) {
+ debug("%s: error reading mux-reg-masks property\n", __func__);
+ return err;
+ }
+
+ /* parent should be an I2C chip, grandparent should be an I2C bus */
+ chip_node = ofnode_get_parent(dev->node);
+ bus_node = ofnode_get_parent(chip_node);
+
+ err = uclass_get_device_by_ofnode(UCLASS_I2C, bus_node, &i2c_bus);
+ if (err) {
+ debug("%s: can't find I2C bus for node %s\n", __func__,
+ ofnode_get_name(bus_node));
+ return err;
+ }
+
+ err = ofnode_read_u32(chip_node, "reg", &chip_addr);
+ if (err) {
+ debug("%s: can't read chip address in %s\n", __func__,
+ ofnode_get_name(chip_node));
+ return err;
+ }
+
+ err = i2c_get_chip(i2c_bus, (uint)chip_addr, 1, &priv->chip);
+ if (err) {
+ debug("%s: can't find i2c chip device for addr %x\n", __func__,
+ chip_addr);
+ return err;
+ }
+
+ priv->reg = (int)reg_mask[0];
+ priv->mask = (int)reg_mask[1];
+
+ debug("%s: chip %s, reg %x, mask %x\n", __func__, priv->chip->name,
+ priv->reg, priv->mask);
+
+ return 0;
+}
+
+static const struct udevice_id mdio_mux_i2creg_ids[] = {
+ { .compatible = "mdio-mux-i2creg" },
+ { }
+};
+
+U_BOOT_DRIVER(mdio_mux_i2creg) = {
+ .name = "mdio_mux_i2creg",
+ .id = UCLASS_MDIO_MUX,
+ .of_match = mdio_mux_i2creg_ids,
+ .probe = mdio_mux_i2creg_probe,
+ .ops = &mdio_mux_i2creg_ops,
+ .priv_auto_alloc_size = sizeof(struct mdio_mux_i2creg_priv),
+};
diff --git a/drivers/net/mdio_mux_sandbox.c b/drivers/net/mdio_mux_sandbox.c
new file mode 100644
index 0000000..3dba4d1
--- /dev/null
+++ b/drivers/net/mdio_mux_sandbox.c
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019
+ * Alex Marginean, NXP
+ */
+
+#include <dm.h>
+#include <errno.h>
+#include <miiphy.h>
+
+/* macros copied over from mdio_sandbox.c */
+#define SANDBOX_PHY_ADDR 5
+#define SANDBOX_PHY_REG_CNT 2
+
+struct mdio_mux_sandbox_priv {
+ int enabled;
+ int sel;
+};
+
+static int mdio_mux_sandbox_mark_selection(struct udevice *dev, int sel)
+{
+ struct udevice *mdio;
+ struct mdio_ops *ops;
+ int err;
+
+ /*
+ * find the sandbox parent mdio and write a register on the PHY there
+ * so the mux test can verify selection.
+ */
+ err = uclass_get_device_by_name(UCLASS_MDIO, "mdio-test", &mdio);
+ if (err)
+ return err;
+ ops = mdio_get_ops(mdio);
+ return ops->write(mdio, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE,
+ SANDBOX_PHY_REG_CNT - 1, (u16)sel);
+}
+
+static int mdio_mux_sandbox_select(struct udevice *dev, int cur, int sel)
+{
+ struct mdio_mux_sandbox_priv *priv = dev_get_priv(dev);
+
+ if (!priv->enabled)
+ return -ENODEV;
+
+ if (cur != priv->sel)
+ return -EINVAL;
+
+ priv->sel = sel;
+ mdio_mux_sandbox_mark_selection(dev, priv->sel);
+
+ return 0;
+}
+
+static int mdio_mux_sandbox_deselect(struct udevice *dev, int sel)
+{
+ struct mdio_mux_sandbox_priv *priv = dev_get_priv(dev);
+
+ if (!priv->enabled)
+ return -ENODEV;
+
+ if (sel != priv->sel)
+ return -EINVAL;
+
+ priv->sel = -1;
+ mdio_mux_sandbox_mark_selection(dev, priv->sel);
+
+ return 0;
+}
+
+static const struct mdio_mux_ops mdio_mux_sandbox_ops = {
+ .select = mdio_mux_sandbox_select,
+ .deselect = mdio_mux_sandbox_deselect,
+};
+
+static int mdio_mux_sandbox_probe(struct udevice *dev)
+{
+ struct mdio_mux_sandbox_priv *priv = dev_get_priv(dev);
+
+ priv->enabled = 1;
+ priv->sel = -1;
+
+ return 0;
+}
+
+static const struct udevice_id mdio_mux_sandbox_ids[] = {
+ { .compatible = "sandbox,mdio-mux" },
+ { }
+};
+
+U_BOOT_DRIVER(mdio_mux_sandbox) = {
+ .name = "mdio_mux_sandbox",
+ .id = UCLASS_MDIO_MUX,
+ .of_match = mdio_mux_sandbox_ids,
+ .probe = mdio_mux_sandbox_probe,
+ .ops = &mdio_mux_sandbox_ops,
+ .priv_auto_alloc_size = sizeof(struct mdio_mux_sandbox_priv),
+};
diff --git a/drivers/net/mdio_sandbox.c b/drivers/net/mdio_sandbox.c
new file mode 100644
index 0000000..b731f60
--- /dev/null
+++ b/drivers/net/mdio_sandbox.c
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019
+ * Alex Marginean, NXP
+ */
+
+#include <dm.h>
+#include <errno.h>
+#include <miiphy.h>
+
+#define SANDBOX_PHY_ADDR 5
+#define SANDBOX_PHY_REG_CNT 2
+
+struct mdio_sandbox_priv {
+ int enabled;
+ u16 reg[SANDBOX_PHY_REG_CNT];
+};
+
+static int mdio_sandbox_read(struct udevice *dev, int addr, int devad, int reg)
+{
+ struct mdio_sandbox_priv *priv = dev_get_priv(dev);
+
+ if (!priv->enabled)
+ return -ENODEV;
+
+ if (addr != SANDBOX_PHY_ADDR)
+ return -ENODEV;
+ if (devad != MDIO_DEVAD_NONE)
+ return -ENODEV;
+ if (reg < 0 || reg >= SANDBOX_PHY_REG_CNT)
+ return -ENODEV;
+
+ return priv->reg[reg];
+}
+
+static int mdio_sandbox_write(struct udevice *dev, int addr, int devad, int reg,
+ u16 val)
+{
+ struct mdio_sandbox_priv *priv = dev_get_priv(dev);
+
+ if (!priv->enabled)
+ return -ENODEV;
+
+ if (addr != SANDBOX_PHY_ADDR)
+ return -ENODEV;
+ if (devad != MDIO_DEVAD_NONE)
+ return -ENODEV;
+ if (reg < 0 || reg >= SANDBOX_PHY_REG_CNT)
+ return -ENODEV;
+
+ priv->reg[reg] = val;
+
+ return 0;
+}
+
+static int mdio_sandbox_reset(struct udevice *dev)
+{
+ struct mdio_sandbox_priv *priv = dev_get_priv(dev);
+ int i;
+
+ for (i = 0; i < SANDBOX_PHY_REG_CNT; i++)
+ priv->reg[i] = 0;
+
+ return 0;
+}
+
+static const struct mdio_ops mdio_sandbox_ops = {
+ .read = mdio_sandbox_read,
+ .write = mdio_sandbox_write,
+ .reset = mdio_sandbox_reset,
+};
+
+static int mdio_sandbox_probe(struct udevice *dev)
+{
+ struct mdio_sandbox_priv *priv = dev_get_priv(dev);
+
+ priv->enabled = 1;
+
+ return 0;
+}
+
+static const struct udevice_id mdio_sandbox_ids[] = {
+ { .compatible = "sandbox,mdio" },
+ { }
+};
+
+U_BOOT_DRIVER(mdio_sandbox) = {
+ .name = "mdio_sandbox",
+ .id = UCLASS_MDIO,
+ .of_match = mdio_sandbox_ids,
+ .probe = mdio_sandbox_probe,
+ .ops = &mdio_sandbox_ops,
+ .priv_auto_alloc_size = sizeof(struct mdio_sandbox_priv),
+};
diff --git a/drivers/net/mscc_eswitch/Makefile b/drivers/net/mscc_eswitch/Makefile
index 02f39a7..d583fe9 100644
--- a/drivers/net/mscc_eswitch/Makefile
+++ b/drivers/net/mscc_eswitch/Makefile
@@ -1,6 +1,6 @@
-obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o mscc_xfer.o mscc_mac_table.o
-obj-$(CONFIG_MSCC_LUTON_SWITCH) += luton_switch.o mscc_xfer.o mscc_mac_table.o
-obj-$(CONFIG_MSCC_JR2_SWITCH) += jr2_switch.o mscc_xfer.o
-obj-$(CONFIG_MSCC_SERVALT_SWITCH) += servalt_switch.o mscc_xfer.o
-obj-$(CONFIG_MSCC_SERVAL_SWITCH) += serval_switch.o mscc_xfer.o mscc_mac_table.o
+obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o mscc_xfer.o mscc_mac_table.o mscc_miim.o
+obj-$(CONFIG_MSCC_LUTON_SWITCH) += luton_switch.o mscc_xfer.o mscc_mac_table.o mscc_miim.o
+obj-$(CONFIG_MSCC_JR2_SWITCH) += jr2_switch.o mscc_xfer.o mscc_miim.o
+obj-$(CONFIG_MSCC_SERVALT_SWITCH) += servalt_switch.o mscc_xfer.o mscc_miim.o
+obj-$(CONFIG_MSCC_SERVAL_SWITCH) += serval_switch.o mscc_xfer.o mscc_mac_table.o mscc_miim.o
diff --git a/drivers/net/mscc_eswitch/jr2_switch.c b/drivers/net/mscc_eswitch/jr2_switch.c
index 60d408f..6655177 100644
--- a/drivers/net/mscc_eswitch/jr2_switch.c
+++ b/drivers/net/mscc_eswitch/jr2_switch.c
@@ -17,20 +17,7 @@
#include <dt-bindings/mscc/jr2_data.h>
#include "mscc_xfer.h"
-
-#define GCB_MIIM_MII_STATUS 0x0
-#define GCB_MIIM_STAT_BUSY BIT(3)
-#define GCB_MIIM_MII_CMD 0x8
-#define GCB_MIIM_MII_CMD_SCAN BIT(0)
-#define GCB_MIIM_MII_CMD_OPR_WRITE BIT(1)
-#define GCB_MIIM_MII_CMD_OPR_READ BIT(2)
-#define GCB_MIIM_MII_CMD_SINGLE_SCAN BIT(3)
-#define GCB_MIIM_MII_CMD_WRDATA(x) ((x) << 4)
-#define GCB_MIIM_MII_CMD_REGAD(x) ((x) << 20)
-#define GCB_MIIM_MII_CMD_PHYAD(x) ((x) << 25)
-#define GCB_MIIM_MII_CMD_VLD BIT(31)
-#define GCB_MIIM_DATA 0xC
-#define GCB_MIIM_DATA_ERROR (0x3 << 16)
+#include "mscc_miim.h"
#define ANA_AC_RAM_CTRL_RAM_INIT 0x94358
#define ANA_AC_STAT_GLOBAL_CFG_PORT_RESET 0x94370
@@ -279,13 +266,6 @@
struct jr2_phy_port_t ports[MAX_PORT];
};
-struct jr2_miim_dev {
- void __iomem *regs;
- phys_addr_t miim_base;
- unsigned long miim_size;
- struct mii_dev *bus;
-};
-
static const unsigned long jr2_regs_qs[] = {
[MSCC_QS_XTR_RD] = 0x8,
[MSCC_QS_XTR_FLUSH] = 0x18,
@@ -294,99 +274,9 @@
[MSCC_QS_INJ_CTRL] = 0x34,
};
-static struct jr2_miim_dev miim[JR2_MIIM_BUS_COUNT];
+static struct mscc_miim_dev miim[JR2_MIIM_BUS_COUNT];
static int miim_count = -1;
-static int mscc_miim_wait_ready(struct jr2_miim_dev *miim)
-{
- unsigned long deadline;
- u32 val;
-
- deadline = timer_get_us() + 250000;
-
- do {
- val = readl(miim->regs + GCB_MIIM_MII_STATUS);
- } while (timer_get_us() <= deadline && (val & GCB_MIIM_STAT_BUSY));
-
- if (val & GCB_MIIM_STAT_BUSY)
- return -ETIMEDOUT;
-
- return 0;
-}
-
-static int mscc_miim_read(struct mii_dev *bus, int addr, int devad, int reg)
-{
- struct jr2_miim_dev *miim = (struct jr2_miim_dev *)bus->priv;
- u32 val;
- int ret;
-
- ret = mscc_miim_wait_ready(miim);
- if (ret)
- goto out;
-
- writel(GCB_MIIM_MII_CMD_VLD | GCB_MIIM_MII_CMD_PHYAD(addr) |
- GCB_MIIM_MII_CMD_REGAD(reg) | GCB_MIIM_MII_CMD_OPR_READ,
- miim->regs + GCB_MIIM_MII_CMD);
-
- ret = mscc_miim_wait_ready(miim);
- if (ret)
- goto out;
-
- val = readl(miim->regs + GCB_MIIM_DATA);
- if (val & GCB_MIIM_DATA_ERROR) {
- ret = -EIO;
- goto out;
- }
-
- ret = val & 0xFFFF;
- out:
- return ret;
-}
-
-static int mscc_miim_write(struct mii_dev *bus, int addr, int devad, int reg,
- u16 val)
-{
- struct jr2_miim_dev *miim = (struct jr2_miim_dev *)bus->priv;
- int ret;
-
- ret = mscc_miim_wait_ready(miim);
- if (ret < 0)
- goto out;
-
- writel(GCB_MIIM_MII_CMD_VLD | GCB_MIIM_MII_CMD_PHYAD(addr) |
- GCB_MIIM_MII_CMD_REGAD(reg) | GCB_MIIM_MII_CMD_WRDATA(val) |
- GCB_MIIM_MII_CMD_OPR_WRITE, miim->regs + GCB_MIIM_MII_CMD);
-
- out:
- return ret;
-}
-
-static struct mii_dev *jr2_mdiobus_init(phys_addr_t miim_base,
- unsigned long miim_size)
-{
- struct mii_dev *bus;
-
- bus = mdio_alloc();
- if (!bus)
- return NULL;
-
- ++miim_count;
- sprintf(bus->name, "miim-bus%d", miim_count);
-
- miim[miim_count].regs = ioremap(miim_base, miim_size);
- miim[miim_count].miim_base = miim_base;
- miim[miim_count].miim_size = miim_size;
- bus->priv = &miim[miim_count];
- bus->read = mscc_miim_read;
- bus->write = mscc_miim_write;
-
- if (mdio_register(bus))
- return NULL;
-
- miim[miim_count].bus = bus;
- return bus;
-}
-
static void jr2_cpu_capture_setup(struct jr2_private *priv)
{
/* ASM: No preamble and IFH prefix on CPU injected frames */
@@ -973,7 +863,7 @@
}
/* Initialize miim buses */
- memset(&miim, 0x0, sizeof(struct jr2_miim_dev) * JR2_MIIM_BUS_COUNT);
+ memset(&miim, 0x0, sizeof(struct mscc_miim_dev) * JR2_MIIM_BUS_COUNT);
/* iterate all the ports and find out on which bus they are */
i = 0;
@@ -1008,7 +898,8 @@
/* If the bus is new then create a new bus */
if (!get_mdiobus(addr_base, addr_size))
priv->bus[miim_count] =
- jr2_mdiobus_init(addr_base, addr_size);
+ mscc_mdiobus_init(miim, &miim_count, addr_base,
+ addr_size);
/* Connect mdio bus with the port */
bus = get_mdiobus(addr_base, addr_size);
diff --git a/drivers/net/mscc_eswitch/luton_switch.c b/drivers/net/mscc_eswitch/luton_switch.c
index 94852b0..dffe81d 100644
--- a/drivers/net/mscc_eswitch/luton_switch.c
+++ b/drivers/net/mscc_eswitch/luton_switch.c
@@ -17,18 +17,7 @@
#include "mscc_xfer.h"
#include "mscc_mac_table.h"
-
-#define GCB_MIIM_MII_STATUS 0x0
-#define GCB_MIIM_STAT_BUSY BIT(3)
-#define GCB_MIIM_MII_CMD 0x8
-#define GCB_MIIM_MII_CMD_OPR_WRITE BIT(1)
-#define GCB_MIIM_MII_CMD_OPR_READ BIT(2)
-#define GCB_MIIM_MII_CMD_WRDATA(x) ((x) << 4)
-#define GCB_MIIM_MII_CMD_REGAD(x) ((x) << 20)
-#define GCB_MIIM_MII_CMD_PHYAD(x) ((x) << 25)
-#define GCB_MIIM_MII_CMD_VLD BIT(31)
-#define GCB_MIIM_DATA 0xC
-#define GCB_MIIM_DATA_ERROR (0x2 << 16)
+#include "mscc_miim.h"
#define ANA_PORT_VLAN_CFG(x) (0x00 + 0x80 * (x))
#define ANA_PORT_VLAN_CFG_AWARE_ENA BIT(20)
@@ -189,13 +178,6 @@
struct luton_phy_port_t ports[MAX_PORT];
};
-struct mscc_miim_dev {
- void __iomem *regs;
- phys_addr_t miim_base;
- unsigned long miim_size;
- struct mii_dev *bus;
-};
-
static const unsigned long luton_regs_qs[] = {
[MSCC_QS_XTR_RD] = 0x18,
[MSCC_QS_XTR_FLUSH] = 0x28,
@@ -213,84 +195,6 @@
static struct mscc_miim_dev miim[LUTON_MIIM_BUS_COUNT];
static int miim_count = -1;
-static int mscc_miim_wait_ready(struct mscc_miim_dev *miim)
-{
- return wait_for_bit_le32(miim->regs + GCB_MIIM_MII_STATUS,
- GCB_MIIM_STAT_BUSY, false, 250, false);
-}
-
-static int mscc_miim_read(struct mii_dev *bus, int addr, int devad, int reg)
-{
- struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
- u32 val;
- int ret;
-
- ret = mscc_miim_wait_ready(miim);
- if (ret)
- goto out;
-
- writel(GCB_MIIM_MII_CMD_VLD | GCB_MIIM_MII_CMD_PHYAD(addr) |
- GCB_MIIM_MII_CMD_REGAD(reg) | GCB_MIIM_MII_CMD_OPR_READ,
- miim->regs + GCB_MIIM_MII_CMD);
-
- ret = mscc_miim_wait_ready(miim);
- if (ret)
- goto out;
-
- val = readl(miim->regs + GCB_MIIM_DATA);
- if (val & GCB_MIIM_DATA_ERROR) {
- ret = -EIO;
- goto out;
- }
-
- ret = val & 0xFFFF;
- out:
- return ret;
-}
-
-static int mscc_miim_write(struct mii_dev *bus, int addr, int devad, int reg,
- u16 val)
-{
- struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
- int ret;
-
- ret = mscc_miim_wait_ready(miim);
- if (ret < 0)
- goto out;
-
- writel(GCB_MIIM_MII_CMD_VLD | GCB_MIIM_MII_CMD_PHYAD(addr) |
- GCB_MIIM_MII_CMD_REGAD(reg) | GCB_MIIM_MII_CMD_WRDATA(val) |
- GCB_MIIM_MII_CMD_OPR_WRITE, miim->regs + GCB_MIIM_MII_CMD);
- out:
- return ret;
-}
-
-static struct mii_dev *serval_mdiobus_init(phys_addr_t miim_base,
- unsigned long miim_size)
-{
- struct mii_dev *bus;
-
- bus = mdio_alloc();
- if (!bus)
- return NULL;
-
- ++miim_count;
- sprintf(bus->name, "miim-bus%d", miim_count);
-
- miim[miim_count].regs = ioremap(miim_base, miim_size);
- miim[miim_count].miim_base = miim_base;
- miim[miim_count].miim_size = miim_size;
- bus->priv = &miim[miim_count];
- bus->read = mscc_miim_read;
- bus->write = mscc_miim_write;
-
- if (mdio_register(bus))
- return NULL;
-
- miim[miim_count].bus = bus;
- return bus;
-}
-
static void luton_stop(struct udevice *dev)
{
struct luton_private *priv = dev_get_priv(dev);
@@ -760,7 +664,8 @@
/* If the bus is new then create a new bus */
if (!get_mdiobus(addr_base, addr_size))
priv->bus[miim_count] =
- serval_mdiobus_init(addr_base, addr_size);
+ mscc_mdiobus_init(miim, &miim_count, addr_base,
+ addr_size);
/* Connect mdio bus with the port */
bus = get_mdiobus(addr_base, addr_size);
diff --git a/drivers/net/mscc_eswitch/mscc_miim.c b/drivers/net/mscc_eswitch/mscc_miim.c
index 419dcc1..d8ee8df 100644
--- a/drivers/net/mscc_eswitch/mscc_miim.c
+++ b/drivers/net/mscc_eswitch/mscc_miim.c
@@ -72,3 +72,31 @@
out:
return ret;
}
+
+struct mii_dev *mscc_mdiobus_init(struct mscc_miim_dev *miim, int *miim_count,
+ phys_addr_t miim_base,
+ unsigned long miim_size)
+{
+ struct mii_dev *bus;
+
+ bus = mdio_alloc();
+
+ if (!bus)
+ return NULL;
+
+ *miim_count += 1;
+ sprintf(bus->name, "miim-bus%d", *miim_count);
+
+ miim[*miim_count].regs = ioremap(miim_base, miim_size);
+ miim[*miim_count].miim_base = miim_base;
+ miim[*miim_count].miim_size = miim_size;
+ bus->priv = &miim[*miim_count];
+ bus->read = mscc_miim_read;
+ bus->write = mscc_miim_write;
+
+ if (mdio_register(bus))
+ return NULL;
+
+ miim[*miim_count].bus = bus;
+ return bus;
+}
diff --git a/drivers/net/mscc_eswitch/mscc_miim.h b/drivers/net/mscc_eswitch/mscc_miim.h
index 0e5d5e3..feb1f40 100644
--- a/drivers/net/mscc_eswitch/mscc_miim.h
+++ b/drivers/net/mscc_eswitch/mscc_miim.h
@@ -3,10 +3,22 @@
* Copyright (c) 2018 Microsemi Corporation
*/
+#ifndef _MSCC_MIIM_H_
+#define _MSCC_MIIM_H_
+
struct mscc_miim_dev {
void __iomem *regs;
- void __iomem *phy_regs;
+ phys_addr_t miim_base;
+ unsigned long miim_size;
+ struct mii_dev *bus;
};
int mscc_miim_read(struct mii_dev *bus, int addr, int devad, int reg);
int mscc_miim_write(struct mii_dev *bus, int addr, int devad, int reg, u16 val);
+
+struct mii_dev *mscc_mdiobus_init(struct mscc_miim_dev *miim, int *miim_count,
+ phys_addr_t miim_base,
+ unsigned long miim_size);
+
+
+#endif /* _MSCC_MIIM_H_ */
diff --git a/drivers/net/mscc_eswitch/ocelot_switch.c b/drivers/net/mscc_eswitch/ocelot_switch.c
index 5c7e696..0ba84ab 100644
--- a/drivers/net/mscc_eswitch/ocelot_switch.c
+++ b/drivers/net/mscc_eswitch/ocelot_switch.c
@@ -17,6 +17,7 @@
#include "mscc_xfer.h"
#include "mscc_mac_table.h"
+#include "mscc_miim.h"
#define PHY_CFG 0x0
#define PHY_CFG_ENA 0xF
@@ -25,20 +26,6 @@
#define PHY_STAT 0x4
#define PHY_STAT_SUPERVISOR_COMPLETE BIT(0)
-#define GCB_MIIM_MII_STATUS 0x0
-#define GCB_MIIM_STAT_BUSY BIT(3)
-#define GCB_MIIM_MII_CMD 0x8
-#define GCB_MIIM_MII_CMD_SCAN BIT(0)
-#define GCB_MIIM_MII_CMD_OPR_WRITE BIT(1)
-#define GCB_MIIM_MII_CMD_OPR_READ BIT(2)
-#define GCB_MIIM_MII_CMD_SINGLE_SCAN BIT(3)
-#define GCB_MIIM_MII_CMD_WRDATA(x) ((x) << 4)
-#define GCB_MIIM_MII_CMD_REGAD(x) ((x) << 20)
-#define GCB_MIIM_MII_CMD_PHYAD(x) ((x) << 25)
-#define GCB_MIIM_MII_CMD_VLD BIT(31)
-#define GCB_MIIM_DATA 0xC
-#define GCB_MIIM_DATA_ERROR (0x3 << 16)
-
#define ANA_PORT_VLAN_CFG(x) (0x7000 + 0x100 * (x))
#define ANA_PORT_VLAN_CFG_AWARE_ENA BIT(20)
#define ANA_PORT_VLAN_CFG_POP_CNT(x) ((x) << 18)
@@ -173,13 +160,6 @@
struct ocelot_phy_port_t ports[MAX_PORT];
};
-struct mscc_miim_dev {
- void __iomem *regs;
- phys_addr_t miim_base;
- unsigned long miim_size;
- struct mii_dev *bus;
-};
-
static struct mscc_miim_dev miim[OCELOT_MIIM_BUS_COUNT];
static int miim_count = -1;
@@ -209,85 +189,6 @@
}
}
-static int mscc_miim_wait_ready(struct mscc_miim_dev *miim)
-{
- return wait_for_bit_le32(miim->regs + GCB_MIIM_MII_STATUS,
- GCB_MIIM_STAT_BUSY, false, 250, false);
-}
-
-static int mscc_miim_read(struct mii_dev *bus, int addr, int devad, int reg)
-{
- struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
- u32 val;
- int ret;
-
- ret = mscc_miim_wait_ready(miim);
- if (ret)
- goto out;
-
- writel(GCB_MIIM_MII_CMD_VLD | GCB_MIIM_MII_CMD_PHYAD(addr) |
- GCB_MIIM_MII_CMD_REGAD(reg) | GCB_MIIM_MII_CMD_OPR_READ,
- miim->regs + GCB_MIIM_MII_CMD);
-
- ret = mscc_miim_wait_ready(miim);
- if (ret)
- goto out;
-
- val = readl(miim->regs + GCB_MIIM_DATA);
- if (val & GCB_MIIM_DATA_ERROR) {
- ret = -EIO;
- goto out;
- }
-
- ret = val & 0xFFFF;
- out:
- return ret;
-}
-
-static int mscc_miim_write(struct mii_dev *bus, int addr, int devad, int reg,
- u16 val)
-{
- struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
- int ret;
-
- ret = mscc_miim_wait_ready(miim);
- if (ret < 0)
- goto out;
-
- writel(GCB_MIIM_MII_CMD_VLD | GCB_MIIM_MII_CMD_PHYAD(addr) |
- GCB_MIIM_MII_CMD_REGAD(reg) | GCB_MIIM_MII_CMD_WRDATA(val) |
- GCB_MIIM_MII_CMD_OPR_WRITE, miim->regs + GCB_MIIM_MII_CMD);
- out:
- return ret;
-}
-
-static struct mii_dev *ocelot_mdiobus_init(phys_addr_t miim_base,
- unsigned long miim_size)
-{
- struct mii_dev *bus;
-
- bus = mdio_alloc();
-
- if (!bus)
- return NULL;
-
- ++miim_count;
- sprintf(bus->name, "miim-bus%d", miim_count);
-
- miim[miim_count].regs = ioremap(miim_base, miim_size);
- miim[miim_count].miim_base = miim_base;
- miim[miim_count].miim_size = miim_size;
- bus->priv = &miim[miim_count];
- bus->read = mscc_miim_read;
- bus->write = mscc_miim_write;
-
- if (mdio_register(bus))
- return NULL;
-
- miim[miim_count].bus = bus;
- return bus;
-}
-
__weak void mscc_switch_reset(void)
{
}
@@ -682,7 +583,8 @@
/* If the bus is new then create a new bus */
if (!get_mdiobus(addr_base, addr_size))
priv->bus[miim_count] =
- ocelot_mdiobus_init(addr_base, addr_size);
+ mscc_mdiobus_init(miim, &miim_count, addr_base,
+ addr_size);
/* Connect mdio bus with the port */
bus = get_mdiobus(addr_base, addr_size);
diff --git a/drivers/net/mscc_eswitch/serval_switch.c b/drivers/net/mscc_eswitch/serval_switch.c
index 2559f5d..1a21360 100644
--- a/drivers/net/mscc_eswitch/serval_switch.c
+++ b/drivers/net/mscc_eswitch/serval_switch.c
@@ -17,18 +17,7 @@
#include "mscc_xfer.h"
#include "mscc_mac_table.h"
-
-#define GCB_MIIM_MII_STATUS 0x0
-#define GCB_MIIM_STAT_BUSY BIT(3)
-#define GCB_MIIM_MII_CMD 0x8
-#define GCB_MIIM_MII_CMD_OPR_WRITE BIT(1)
-#define GCB_MIIM_MII_CMD_OPR_READ BIT(2)
-#define GCB_MIIM_MII_CMD_WRDATA(x) ((x) << 4)
-#define GCB_MIIM_MII_CMD_REGAD(x) ((x) << 20)
-#define GCB_MIIM_MII_CMD_PHYAD(x) ((x) << 25)
-#define GCB_MIIM_MII_CMD_VLD BIT(31)
-#define GCB_MIIM_DATA 0xC
-#define GCB_MIIM_DATA_ERROR (0x2 << 16)
+#include "mscc_miim.h"
#define ANA_PORT_VLAN_CFG(x) (0xc000 + 0x100 * (x))
#define ANA_PORT_VLAN_CFG_AWARE_ENA BIT(20)
@@ -156,13 +145,6 @@
struct serval_phy_port_t ports[MAX_PORT];
};
-struct mscc_miim_dev {
- void __iomem *regs;
- phys_addr_t miim_base;
- unsigned long miim_size;
- struct mii_dev *bus;
-};
-
static const unsigned long serval_regs_qs[] = {
[MSCC_QS_XTR_RD] = 0x8,
[MSCC_QS_XTR_FLUSH] = 0x18,
@@ -180,84 +162,6 @@
static struct mscc_miim_dev miim[SERVAL_MIIM_BUS_COUNT];
static int miim_count = -1;
-static int mscc_miim_wait_ready(struct mscc_miim_dev *miim)
-{
- return wait_for_bit_le32(miim->regs + GCB_MIIM_MII_STATUS,
- GCB_MIIM_STAT_BUSY, false, 250, false);
-}
-
-static int mscc_miim_read(struct mii_dev *bus, int addr, int devad, int reg)
-{
- struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
- u32 val;
- int ret;
-
- ret = mscc_miim_wait_ready(miim);
- if (ret)
- goto out;
-
- writel(GCB_MIIM_MII_CMD_VLD | GCB_MIIM_MII_CMD_PHYAD(addr) |
- GCB_MIIM_MII_CMD_REGAD(reg) | GCB_MIIM_MII_CMD_OPR_READ,
- miim->regs + GCB_MIIM_MII_CMD);
-
- ret = mscc_miim_wait_ready(miim);
- if (ret)
- goto out;
-
- val = readl(miim->regs + GCB_MIIM_DATA);
- if (val & GCB_MIIM_DATA_ERROR) {
- ret = -EIO;
- goto out;
- }
-
- ret = val & 0xFFFF;
- out:
- return ret;
-}
-
-static int mscc_miim_write(struct mii_dev *bus, int addr, int devad, int reg,
- u16 val)
-{
- struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
- int ret;
-
- ret = mscc_miim_wait_ready(miim);
- if (ret < 0)
- goto out;
-
- writel(GCB_MIIM_MII_CMD_VLD | GCB_MIIM_MII_CMD_PHYAD(addr) |
- GCB_MIIM_MII_CMD_REGAD(reg) | GCB_MIIM_MII_CMD_WRDATA(val) |
- GCB_MIIM_MII_CMD_OPR_WRITE, miim->regs + GCB_MIIM_MII_CMD);
- out:
- return ret;
-}
-
-static struct mii_dev *serval_mdiobus_init(phys_addr_t miim_base,
- unsigned long miim_size)
-{
- struct mii_dev *bus;
-
- bus = mdio_alloc();
- if (!bus)
- return NULL;
-
- ++miim_count;
- sprintf(bus->name, "miim-bus%d", miim_count);
-
- miim[miim_count].regs = ioremap(miim_base, miim_size);
- miim[miim_count].miim_base = miim_base;
- miim[miim_count].miim_size = miim_size;
- bus->priv = &miim[miim_count];
- bus->read = mscc_miim_read;
- bus->write = mscc_miim_write;
-
- if (mdio_register(bus))
- return NULL;
-
- miim[miim_count].bus = bus;
- return bus;
-}
-
static void serval_cpu_capture_setup(struct serval_private *priv)
{
int i;
@@ -356,8 +260,6 @@
do {
data = readl(base + HSIO_MCB_SERDES1G_CFG);
} while (data & HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT);
-
- mdelay(100);
}
static void serdes1g_setup(void __iomem *base, uint32_t addr,
@@ -636,7 +538,8 @@
/* If the bus is new then create a new bus */
if (!get_mdiobus(addr_base, addr_size))
priv->bus[miim_count] =
- serval_mdiobus_init(addr_base, addr_size);
+ mscc_mdiobus_init(miim, &miim_count, addr_base,
+ addr_size);
/* Connect mdio bus with the port */
bus = get_mdiobus(addr_base, addr_size);
diff --git a/drivers/net/mscc_eswitch/servalt_switch.c b/drivers/net/mscc_eswitch/servalt_switch.c
index 995c623..d20ec49 100644
--- a/drivers/net/mscc_eswitch/servalt_switch.c
+++ b/drivers/net/mscc_eswitch/servalt_switch.c
@@ -16,18 +16,7 @@
#include <wait_bit.h>
#include "mscc_xfer.h"
-
-#define GCB_MIIM_MII_STATUS 0x0
-#define GCB_MIIM_STAT_BUSY BIT(3)
-#define GCB_MIIM_MII_CMD 0x8
-#define GCB_MIIM_MII_CMD_OPR_WRITE BIT(1)
-#define GCB_MIIM_MII_CMD_OPR_READ BIT(2)
-#define GCB_MIIM_MII_CMD_WRDATA(x) ((x) << 4)
-#define GCB_MIIM_MII_CMD_REGAD(x) ((x) << 20)
-#define GCB_MIIM_MII_CMD_PHYAD(x) ((x) << 25)
-#define GCB_MIIM_MII_CMD_VLD BIT(31)
-#define GCB_MIIM_DATA 0xC
-#define GCB_MIIM_DATA_ERROR (0x3 << 16)
+#include "mscc_miim.h"
#define PHY_CFG 0x0
#define PHY_CFG_ENA 0x3
@@ -134,13 +123,6 @@
struct servalt_phy_port_t ports[MAX_PORT];
};
-struct mscc_miim_dev {
- void __iomem *regs;
- phys_addr_t miim_base;
- unsigned long miim_size;
- struct mii_dev *bus;
-};
-
static const unsigned long servalt_regs_qs[] = {
[MSCC_QS_XTR_RD] = 0x8,
[MSCC_QS_XTR_FLUSH] = 0x18,
@@ -152,85 +134,6 @@
static struct mscc_miim_dev miim[SERVALT_MIIM_BUS_COUNT];
static int miim_count = -1;
-static int mscc_miim_wait_ready(struct mscc_miim_dev *miim)
-{
- return wait_for_bit_le32(miim->regs + GCB_MIIM_MII_STATUS,
- GCB_MIIM_STAT_BUSY, false, 250, false);
-}
-
-static int mscc_miim_read(struct mii_dev *bus, int addr, int devad, int reg)
-{
- struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
- u32 val;
- int ret;
-
- ret = mscc_miim_wait_ready(miim);
- if (ret)
- goto out;
-
- writel(GCB_MIIM_MII_CMD_VLD | GCB_MIIM_MII_CMD_PHYAD(addr) |
- GCB_MIIM_MII_CMD_REGAD(reg) | GCB_MIIM_MII_CMD_OPR_READ,
- miim->regs + GCB_MIIM_MII_CMD);
-
- ret = mscc_miim_wait_ready(miim);
- if (ret)
- goto out;
-
- val = readl(miim->regs + GCB_MIIM_DATA);
- if (val & GCB_MIIM_DATA_ERROR) {
- ret = -EIO;
- goto out;
- }
-
- ret = val & 0xFFFF;
-out:
- return ret;
-}
-
-static int mscc_miim_write(struct mii_dev *bus, int addr, int devad, int reg,
- u16 val)
-{
- struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
- int ret;
-
- ret = mscc_miim_wait_ready(miim);
- if (ret < 0)
- goto out;
-
- writel(GCB_MIIM_MII_CMD_VLD | GCB_MIIM_MII_CMD_PHYAD(addr) |
- GCB_MIIM_MII_CMD_REGAD(reg) | GCB_MIIM_MII_CMD_WRDATA(val) |
- GCB_MIIM_MII_CMD_OPR_WRITE, miim->regs + GCB_MIIM_MII_CMD);
-
-out:
- return ret;
-}
-
-static struct mii_dev *servalt_mdiobus_init(phys_addr_t miim_base,
- unsigned long miim_size)
-{
- struct mii_dev *bus;
-
- bus = mdio_alloc();
- if (!bus)
- return NULL;
-
- ++miim_count;
- sprintf(bus->name, "miim-bus%d", miim_count);
-
- miim[miim_count].regs = ioremap(miim_base, miim_size);
- miim[miim_count].miim_base = miim_base;
- miim[miim_count].miim_size = miim_size;
- bus->priv = &miim[miim_count];
- bus->read = mscc_miim_read;
- bus->write = mscc_miim_write;
-
- if (mdio_register(bus))
- return NULL;
-
- miim[miim_count].bus = bus;
- return bus;
-}
-
static void mscc_phy_reset(void)
{
writel(0, BASE_DEVCPU_GCB + GCB_PHY_CFG + PHY_CFG);
@@ -564,7 +467,8 @@
/* If the bus is new then create a new bus */
if (!get_mdiobus(addr_base, addr_size))
priv->bus[miim_count] =
- servalt_mdiobus_init(addr_base, addr_size);
+ mscc_mdiobus_init(miim, &miim_count, addr_base,
+ addr_size);
/* Connect mdio bus with the port */
bus = get_mdiobus(addr_base, addr_size);
diff --git a/drivers/net/mvmdio.c b/drivers/net/mvmdio.c
new file mode 100644
index 0000000..ec6805e
--- /dev/null
+++ b/drivers/net/mvmdio.c
@@ -0,0 +1,236 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ * Author: Ken Ma<make@marvell.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <asm/io.h>
+#include <wait_bit.h>
+
+#define MVMDIO_SMI_DATA_SHIFT 0
+#define MVMDIO_SMI_PHY_ADDR_SHIFT 16
+#define MVMDIO_SMI_PHY_REG_SHIFT 21
+#define MVMDIO_SMI_READ_OPERATION BIT(26)
+#define MVMDIO_SMI_WRITE_OPERATION 0
+#define MVMDIO_SMI_READ_VALID BIT(27)
+#define MVMDIO_SMI_BUSY BIT(28)
+
+#define MVMDIO_XSMI_MGNT_REG 0x0
+#define MVMDIO_XSMI_PHYADDR_SHIFT 16
+#define MVMDIO_XSMI_DEVADDR_SHIFT 21
+#define MVMDIO_XSMI_WRITE_OPERATION (0x5 << 26)
+#define MVMDIO_XSMI_READ_OPERATION (0x7 << 26)
+#define MVMDIO_XSMI_READ_VALID BIT(29)
+#define MVMDIO_XSMI_BUSY BIT(30)
+#define MVMDIO_XSMI_ADDR_REG 0x8
+
+enum mvmdio_bus_type {
+ BUS_TYPE_SMI,
+ BUS_TYPE_XSMI
+};
+
+struct mvmdio_priv {
+ void *mdio_base;
+ enum mvmdio_bus_type type;
+};
+
+static int mvmdio_smi_read(struct udevice *dev, int addr,
+ int devad, int reg)
+{
+ struct mvmdio_priv *priv = dev_get_priv(dev);
+ u32 val;
+ int ret;
+
+ if (devad != MDIO_DEVAD_NONE)
+ return -EOPNOTSUPP;
+
+ ret = wait_for_bit_le32(priv->mdio_base, MVMDIO_SMI_BUSY,
+ false, CONFIG_SYS_HZ, false);
+ if (ret < 0)
+ return ret;
+
+ writel(((addr << MVMDIO_SMI_PHY_ADDR_SHIFT) |
+ (reg << MVMDIO_SMI_PHY_REG_SHIFT) |
+ MVMDIO_SMI_READ_OPERATION),
+ priv->mdio_base);
+
+ ret = wait_for_bit_le32(priv->mdio_base, MVMDIO_SMI_BUSY,
+ false, CONFIG_SYS_HZ, false);
+ if (ret < 0)
+ return ret;
+
+ val = readl(priv->mdio_base);
+ if (!(val & MVMDIO_SMI_READ_VALID)) {
+ pr_err("SMI bus read not valid\n");
+ return -ENODEV;
+ }
+
+ return val & GENMASK(15, 0);
+}
+
+static int mvmdio_smi_write(struct udevice *dev, int addr, int devad,
+ int reg, u16 value)
+{
+ struct mvmdio_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ if (devad != MDIO_DEVAD_NONE)
+ return -EOPNOTSUPP;
+
+ ret = wait_for_bit_le32(priv->mdio_base, MVMDIO_SMI_BUSY,
+ false, CONFIG_SYS_HZ, false);
+ if (ret < 0)
+ return ret;
+
+ writel(((addr << MVMDIO_SMI_PHY_ADDR_SHIFT) |
+ (reg << MVMDIO_SMI_PHY_REG_SHIFT) |
+ MVMDIO_SMI_WRITE_OPERATION |
+ (value << MVMDIO_SMI_DATA_SHIFT)),
+ priv->mdio_base);
+
+ return 0;
+}
+
+static int mvmdio_xsmi_read(struct udevice *dev, int addr,
+ int devad, int reg)
+{
+ struct mvmdio_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ if (devad == MDIO_DEVAD_NONE)
+ return -EOPNOTSUPP;
+
+ ret = wait_for_bit_le32(priv->mdio_base, MVMDIO_XSMI_BUSY,
+ false, CONFIG_SYS_HZ, false);
+ if (ret < 0)
+ return ret;
+
+ writel(reg & GENMASK(15, 0), priv->mdio_base + MVMDIO_XSMI_ADDR_REG);
+ writel(((addr << MVMDIO_XSMI_PHYADDR_SHIFT) |
+ (devad << MVMDIO_XSMI_DEVADDR_SHIFT) |
+ MVMDIO_XSMI_READ_OPERATION),
+ priv->mdio_base + MVMDIO_XSMI_MGNT_REG);
+
+ ret = wait_for_bit_le32(priv->mdio_base, MVMDIO_XSMI_BUSY,
+ false, CONFIG_SYS_HZ, false);
+ if (ret < 0)
+ return ret;
+
+ if (!(readl(priv->mdio_base + MVMDIO_XSMI_MGNT_REG) &
+ MVMDIO_XSMI_READ_VALID)) {
+ pr_err("XSMI bus read not valid\n");
+ return -ENODEV;
+ }
+
+ return readl(priv->mdio_base + MVMDIO_XSMI_MGNT_REG) & GENMASK(15, 0);
+}
+
+static int mvmdio_xsmi_write(struct udevice *dev, int addr, int devad,
+ int reg, u16 value)
+{
+ struct mvmdio_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ if (devad == MDIO_DEVAD_NONE)
+ return -EOPNOTSUPP;
+
+ ret = wait_for_bit_le32(priv->mdio_base, MVMDIO_XSMI_BUSY,
+ false, CONFIG_SYS_HZ, false);
+ if (ret < 0)
+ return ret;
+
+ writel(reg & GENMASK(15, 0), priv->mdio_base + MVMDIO_XSMI_ADDR_REG);
+ writel(((addr << MVMDIO_XSMI_PHYADDR_SHIFT) |
+ (devad << MVMDIO_XSMI_DEVADDR_SHIFT) |
+ MVMDIO_XSMI_WRITE_OPERATION | value),
+ priv->mdio_base + MVMDIO_XSMI_MGNT_REG);
+
+ return 0;
+}
+
+static int mvmdio_read(struct udevice *dev, int addr, int devad, int reg)
+{
+ struct mvmdio_priv *priv = dev_get_priv(dev);
+ int err = -ENOTSUPP;
+
+ switch (priv->type) {
+ case BUS_TYPE_SMI:
+ err = mvmdio_smi_read(dev, addr, devad, reg);
+ break;
+ case BUS_TYPE_XSMI:
+ err = mvmdio_xsmi_read(dev, addr, devad, reg);
+ break;
+ }
+
+ return err;
+}
+
+static int mvmdio_write(struct udevice *dev, int addr, int devad, int reg,
+ u16 value)
+{
+ struct mvmdio_priv *priv = dev_get_priv(dev);
+ int err = -ENOTSUPP;
+
+ switch (priv->type) {
+ case BUS_TYPE_SMI:
+ err = mvmdio_smi_write(dev, addr, devad, reg, value);
+ break;
+ case BUS_TYPE_XSMI:
+ err = mvmdio_xsmi_write(dev, addr, devad, reg, value);
+ break;
+ }
+
+ return err;
+}
+
+/*
+ * Name the device, we use the device tree node name.
+ * This can be overwritten by MDIO class code if device-name property is
+ * present.
+ */
+static int mvmdio_bind(struct udevice *dev)
+{
+ if (ofnode_valid(dev->node))
+ device_set_name(dev, ofnode_get_name(dev->node));
+
+ return 0;
+}
+
+/* Get device base address and type, either C22 SMII or C45 XSMI */
+static int mvmdio_probe(struct udevice *dev)
+{
+ struct mvmdio_priv *priv = dev_get_priv(dev);
+
+ priv->mdio_base = (void *)dev_read_addr(dev);
+ priv->type = (enum mvmdio_bus_type)dev_get_driver_data(dev);
+
+ return 0;
+}
+
+static const struct mdio_ops mvmdio_ops = {
+ .read = mvmdio_read,
+ .write = mvmdio_write,
+};
+
+static const struct udevice_id mvmdio_ids[] = {
+ { .compatible = "marvell,orion-mdio", .data = BUS_TYPE_SMI },
+ { .compatible = "marvell,xmdio", .data = BUS_TYPE_XSMI },
+ { }
+};
+
+U_BOOT_DRIVER(mvmdio) = {
+ .name = "mvmdio",
+ .id = UCLASS_MDIO,
+ .of_match = mvmdio_ids,
+ .bind = mvmdio_bind,
+ .probe = mvmdio_probe,
+ .ops = &mvmdio_ops,
+ .priv_auto_alloc_size = sizeof(struct mvmdio_priv),
+};
+
diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index bcc6fe9..bd89725 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -5321,6 +5321,13 @@
mvpp2_cleanup_txqs(port);
}
+static int mvpp2_write_hwaddr(struct udevice *dev)
+{
+ struct mvpp2_port *port = dev_get_priv(dev);
+
+ return mvpp2_prs_update_mac_da(port, port->dev_addr);
+}
+
static int mvpp22_smi_phy_addr_cfg(struct mvpp2_port *port)
{
writel(port->phyaddr, port->priv->iface_base +
@@ -5525,6 +5532,7 @@
.send = mvpp2_send,
.recv = mvpp2_recv,
.stop = mvpp2_stop,
+ .write_hwaddr = mvpp2_write_hwaddr
};
static struct driver mvpp2_driver = {
diff --git a/drivers/net/ne2000_base.c b/drivers/net/ne2000_base.c
index 421aa20..a240d06 100644
--- a/drivers/net/ne2000_base.c
+++ b/drivers/net/ne2000_base.c
@@ -74,7 +74,7 @@
#include <common.h>
#include <command.h>
-#include <environment.h>
+#include <env.h>
#include <net.h>
#include <malloc.h>
#include <linux/compiler.h>
@@ -693,16 +693,6 @@
}
}
-#ifdef CONFIG_DRIVER_NE2000_CCR
- {
- vu_char *p = (vu_char *) CONFIG_DRIVER_NE2000_CCR;
-
- PRINTK("CCR before is %x\n", *p);
- *p = CONFIG_DRIVER_NE2000_VAL;
- PRINTK("CCR after is %x\n", *p);
- }
-#endif
-
nic.base = (u8 *) CONFIG_DRIVER_NE2000_BASE;
nic.data = nic.base + DP_DATA;
diff --git a/drivers/net/netconsole.c b/drivers/net/netconsole.c
index ce5a15e..73005ff 100644
--- a/drivers/net/netconsole.c
+++ b/drivers/net/netconsole.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <stdio_dev.h>
#include <net.h>
@@ -55,7 +56,7 @@
static struct in_addr netmask;
static struct in_addr our_ip;
static int env_changed_id;
- int env_id = get_env_id();
+ int env_id = env_get_id();
/* update only when the environment has changed */
if (env_changed_id != env_id) {
@@ -75,7 +76,7 @@
{
const char *p;
static int env_changed_id;
- int env_id = get_env_id();
+ int env_id = env_get_id();
/* update only when the environment has changed */
if (env_changed_id != env_id) {
diff --git a/drivers/net/pfe_eth/pfe_mdio.c b/drivers/net/pfe_eth/pfe_mdio.c
index 2dde9e7..6230967 100644
--- a/drivers/net/pfe_eth/pfe_mdio.c
+++ b/drivers/net/pfe_eth/pfe_mdio.c
@@ -110,7 +110,6 @@
u32 phy;
u32 reg_data;
int timeout = MDIO_TIMEOUT;
- int val;
if (dev_addr == MDIO_DEVAD_NONE) {
reg = ((reg_addr & EMAC_MII_DATA_RA_MASK) <<
@@ -150,7 +149,7 @@
debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phy_addr,
reg_addr, data);
- return val;
+ return 0;
}
static void pfe_configure_serdes(struct pfe_eth_dev *priv)
diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c
index 5c3298d..465ec2d 100644
--- a/drivers/net/phy/aquantia.c
+++ b/drivers/net/phy/aquantia.c
@@ -461,6 +461,19 @@
.shutdown = &gen10g_shutdown,
};
+struct phy_driver aqr112_driver = {
+ .name = "Aquantia AQR112",
+ .uid = 0x3a1b660,
+ .mask = 0xfffffff0,
+ .features = PHY_10G_FEATURES,
+ .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS |
+ MDIO_MMD_PHYXS | MDIO_MMD_AN |
+ MDIO_MMD_VEND1),
+ .config = &aquantia_config,
+ .startup = &aquantia_startup,
+ .shutdown = &gen10g_shutdown,
+};
+
struct phy_driver aqr405_driver = {
.name = "Aquantia AQR405",
.uid = 0x3a1b4b2,
@@ -474,6 +487,19 @@
.shutdown = &gen10g_shutdown,
};
+struct phy_driver aqr412_driver = {
+ .name = "Aquantia AQR412",
+ .uid = 0x3a1b710,
+ .mask = 0xfffffff0,
+ .features = PHY_10G_FEATURES,
+ .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS |
+ MDIO_MMD_PHYXS | MDIO_MMD_AN |
+ MDIO_MMD_VEND1),
+ .config = &aquantia_config,
+ .startup = &aquantia_startup,
+ .shutdown = &gen10g_shutdown,
+};
+
int phy_aquantia_init(void)
{
phy_register(&aq1202_driver);
@@ -481,7 +507,9 @@
phy_register(&aqr105_driver);
phy_register(&aqr106_driver);
phy_register(&aqr107_driver);
+ phy_register(&aqr112_driver);
phy_register(&aqr405_driver);
+ phy_register(&aqr412_driver);
return 0;
}
diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c
index a04a118..ec81dab 100644
--- a/drivers/net/phy/cortina.c
+++ b/drivers/net/phy/cortina.c
@@ -176,8 +176,13 @@
printf("MMC read: dev # %u, block # %u, count %u ...\n",
dev, blk, cnt);
mmc_init(mmc);
+#ifdef CONFIG_BLK
+ (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
+ addr);
+#else
(void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt,
addr);
+#endif
}
#endif
diff --git a/drivers/net/phy/micrel_ksz90x1.c b/drivers/net/phy/micrel_ksz90x1.c
index f18e40a..0105fc5 100644
--- a/drivers/net/phy/micrel_ksz90x1.c
+++ b/drivers/net/phy/micrel_ksz90x1.c
@@ -10,6 +10,7 @@
*/
#include <common.h>
#include <dm.h>
+#include <env.h>
#include <errno.h>
#include <micrel.h>
#include <phy.h>
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index c1c1af9..ae37dd6 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -727,12 +727,23 @@
while (phy_mask) {
int addr = ffs(phy_mask) - 1;
int r = get_phy_id(bus, addr, devad, &phy_id);
+
+ /*
+ * If the PHY ID is flat 0 we ignore it. There are C45 PHYs
+ * that return all 0s for C22 reads (like Aquantia AQR112) and
+ * there are C22 PHYs that return all 0s for C45 reads (like
+ * Atheros AR8035).
+ */
+ if (r == 0 && phy_id == 0)
+ goto next;
+
/* If the PHY ID is mostly f's, we didn't find anything */
if (r == 0 && (phy_id & 0x1fffffff) != 0x1fffffff) {
is_c45 = (devad == MDIO_DEVAD_NONE) ? false : true;
return phy_device_create(bus, addr, phy_id, is_c45,
interface);
}
+next:
phy_mask &= ~(1 << addr);
}
return NULL;
diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c
index 25f1332..7509936 100644
--- a/drivers/net/phy/ti.c
+++ b/drivers/net/phy/ti.c
@@ -103,7 +103,7 @@
int io_impedance;
bool rxctrl_strap_quirk;
int port_mirroring;
- int clk_output_sel;
+ unsigned int clk_output_sel;
};
static int dp83867_config_port_mirroring(struct phy_device *phydev)
@@ -136,17 +136,11 @@
ofnode node;
u16 val;
- /* Optional configuration */
-
node = phy_get_ofnode(phydev);
if (!ofnode_valid(node))
return -EINVAL;
- /*
- * Keep the default value if ti,clk-output-sel is not set
- * or to high
- */
-
+ /* Keep the default value if ti,clk-output-sel is not set */
dp83867->clk_output_sel =
ofnode_read_u32_default(node, "ti,clk-output-sel",
DP83867_CLK_O_SEL_REF_CLK);
@@ -162,14 +156,14 @@
dp83867->rxctrl_strap_quirk = true;
dp83867->rx_id_delay = ofnode_read_u32_default(node,
"ti,rx-internal-delay",
- -1);
+ DEFAULT_RX_ID_DELAY);
dp83867->tx_id_delay = ofnode_read_u32_default(node,
"ti,tx-internal-delay",
- -1);
+ DEFAULT_TX_ID_DELAY);
dp83867->fifo_depth = ofnode_read_u32_default(node, "ti,fifo-depth",
- -1);
+ DEFAULT_FIFO_DEPTH);
if (ofnode_read_bool(node, "enet-phy-lane-swap"))
dp83867->port_mirroring = DP83867_PORT_MIRRORING_EN;
diff --git a/drivers/net/sandbox-raw.c b/drivers/net/sandbox-raw.c
index 7e6625d..3707ee3 100644
--- a/drivers/net/sandbox-raw.c
+++ b/drivers/net/sandbox-raw.c
@@ -9,6 +9,7 @@
#include <asm/eth-raw-os.h>
#include <common.h>
#include <dm.h>
+#include <env.h>
#include <malloc.h>
#include <net.h>
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index da79b76..749f651 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -10,7 +10,7 @@
#include <config.h>
#include <common.h>
-#include <environment.h>
+#include <env.h>
#include <malloc.h>
#include <net.h>
#include <netdev.h>
@@ -37,8 +37,8 @@
#if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && \
!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#define flush_cache_wback(addr, len) \
- flush_dcache_range((u32)addr, \
- (u32)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))
+ flush_dcache_range((unsigned long)addr, \
+ (unsigned long)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))
#else
#define flush_cache_wback(...)
#endif
@@ -46,11 +46,11 @@
#if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
#define invalidate_cache(addr, len) \
{ \
- u32 line_size = CONFIG_SH_ETHER_ALIGNE_SIZE; \
- u32 start, end; \
+ unsigned long line_size = CONFIG_SH_ETHER_ALIGNE_SIZE; \
+ unsigned long start, end; \
\
- start = (u32)addr; \
- end = start + len; \
+ start = (unsigned long)addr; \
+ end = start + len; \
start &= ~(line_size - 1); \
end = ((end + line_size - 1) & ~(line_size - 1)); \
\
@@ -74,7 +74,7 @@
}
/* packet must be a 4 byte boundary */
- if ((int)packet & 3) {
+ if ((uintptr_t)packet & 3) {
printf(SHETHER_NAME ": %s: packet not 4 byte aligned\n"
, __func__);
ret = -EFAULT;
@@ -211,7 +211,7 @@
/* Make sure we use a P2 address (non-cacheable) */
port_info->tx_desc_base =
- (struct tx_desc_s *)ADDR_TO_P2((u32)port_info->tx_desc_alloc);
+ (struct tx_desc_s *)ADDR_TO_P2((uintptr_t)port_info->tx_desc_alloc);
port_info->tx_desc_cur = port_info->tx_desc_base;
/* Initialize all descriptors */
@@ -265,7 +265,7 @@
/* Make sure we use a P2 address (non-cacheable) */
port_info->rx_desc_base =
- (struct rx_desc_s *)ADDR_TO_P2((u32)port_info->rx_desc_alloc);
+ (struct rx_desc_s *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_alloc);
port_info->rx_desc_cur = port_info->rx_desc_base;
@@ -281,7 +281,7 @@
goto err_buf_alloc;
}
- port_info->rx_buf_base = (u8 *)ADDR_TO_P2((u32)port_info->rx_buf_alloc);
+ port_info->rx_buf_base = (u8 *)ADDR_TO_P2((uintptr_t)port_info->rx_buf_alloc);
/* Initialize all descriptors */
for (cur_rx_desc = port_info->rx_desc_base,
@@ -374,10 +374,16 @@
static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac)
{
struct sh_eth_info *port_info = ð->port_info[eth->port];
+ unsigned long edmr;
/* Configure e-dmac registers */
- sh_eth_write(port_info, (sh_eth_read(port_info, EDMR) & ~EMDR_DESC_R) |
- (EMDR_DESC | EDMR_EL), EDMR);
+ edmr = sh_eth_read(port_info, EDMR);
+ edmr &= ~EMDR_DESC_R;
+ edmr |= EMDR_DESC | EDMR_EL;
+#if defined(CONFIG_R8A77980)
+ edmr |= EDMR_NBST;
+#endif
+ sh_eth_write(port_info, edmr, EDMR);
sh_eth_write(port_info, 0, EESIPR);
sh_eth_write(port_info, 0, TRSCER);
@@ -407,7 +413,7 @@
#if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
-#elif defined(CONFIG_RCAR_GEN2)
+#elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_R8A77980)
sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR);
#endif
}
@@ -426,7 +432,7 @@
sh_eth_write(port_info, GECMR_100B, GECMR);
#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
sh_eth_write(port_info, 1, RTRATE);
-#elif defined(CONFIG_RCAR_GEN2)
+#elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_R8A77980)
val = ECMR_RTM;
#endif
} else if (phy->speed == 10) {
@@ -694,7 +700,7 @@
struct sh_ether_priv *priv = dev_get_priv(dev);
struct sh_eth_dev *eth = &priv->shdev;
struct sh_eth_info *port_info = ð->port_info[eth->port];
- uchar *packet = (uchar *)ADDR_TO_P2(port_info->rx_desc_cur->rd2);
+ uchar *packet = (uchar *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_cur->rd2);
int len;
len = sh_eth_recv_start(eth);
@@ -844,7 +850,7 @@
eth->port = CONFIG_SH_ETHER_USE_PORT;
eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
eth->port_info[eth->port].iobase =
- (void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
+ (void __iomem *)(uintptr_t)(BASE_IO_ADDR + 0x800 * eth->port);
#if CONFIG_IS_ENABLED(CLK)
ret = clk_enable(&priv->clk);
@@ -931,6 +937,7 @@
{ .compatible = "renesas,ether-r8a7791" },
{ .compatible = "renesas,ether-r8a7793" },
{ .compatible = "renesas,ether-r8a7794" },
+ { .compatible = "renesas,gether-r8a77980" },
{ }
};
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index e1bbd49..d197dfd 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -15,20 +15,20 @@
#if defined(CONFIG_SH)
/* Malloc returns addresses in the P1 area (cacheable). However we need to
use area P2 (non-cacheable) */
-#define ADDR_TO_P2(addr) ((((int)(addr) & ~0xe0000000) | 0xa0000000))
+#define ADDR_TO_P2(addr) ((((uintptr_t)(addr) & ~0xe0000000) | 0xa0000000))
/* The ethernet controller needs to use physical addresses */
#if defined(CONFIG_SH_32BIT)
-#define ADDR_TO_PHY(addr) ((((int)(addr) & ~0xe0000000) | 0x40000000))
+#define ADDR_TO_PHY(addr) ((((uintptr_t)(addr) & ~0xe0000000) | 0x40000000))
#else
-#define ADDR_TO_PHY(addr) ((int)(addr) & ~0xe0000000)
+#define ADDR_TO_PHY(addr) ((uintptr_t)(addr) & ~0xe0000000)
#endif
#elif defined(CONFIG_ARM)
#ifndef inl
#define inl readl
#define outl writel
#endif
-#define ADDR_TO_PHY(addr) ((int)(addr))
+#define ADDR_TO_PHY(addr) ((uintptr_t)(addr))
#define ADDR_TO_P2(addr) (addr)
#endif /* defined(CONFIG_SH) */
@@ -358,6 +358,9 @@
#elif defined(CONFIG_R7S72100)
#define SH_ETH_TYPE_RZ
#define BASE_IO_ADDR 0xE8203000
+#elif defined(CONFIG_R8A77980)
+#define SH_ETH_TYPE_GETHER
+#define BASE_IO_ADDR 0xE7400000
#endif
/*
@@ -374,6 +377,7 @@
/* EDMR */
enum DMAC_M_BIT {
+ EDMR_NBST = 0x80, /* DMA transfer burst mode */
EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
EDMR_SRST = 0x03, /* Receive/Send reset */
@@ -563,7 +567,7 @@
ECMR_PRM = 0x00000001,
#ifdef CONFIG_CPU_SH7724
ECMR_RTM = 0x00000010,
-#elif defined(CONFIG_RCAR_GEN2)
+#elif defined(CONFIG_RCAR_GEN2) || defined (CONFIG_R8A77980)
ECMR_RTM = 0x00000004,
#endif
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index c0a4408..0629b16 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -846,31 +846,44 @@
static int sun8i_get_ephy_nodes(struct emac_eth_dev *priv)
{
- int node, ret;
+ int emac_node, ephy_node, ret, ephy_handle;
+
+ emac_node = fdt_path_offset(gd->fdt_blob,
+ "/soc/ethernet@1c30000");
+ if (emac_node < 0) {
+ debug("failed to get emac node\n");
+ return emac_node;
+ }
+ ephy_handle = fdtdec_lookup_phandle(gd->fdt_blob,
+ emac_node, "phy-handle");
/* look for mdio-mux node for internal PHY node */
- node = fdt_path_offset(gd->fdt_blob,
- "/soc/ethernet@1c30000/mdio-mux/mdio@1/ethernet-phy@1");
- if (node < 0) {
+ ephy_node = fdt_path_offset(gd->fdt_blob,
+ "/soc/ethernet@1c30000/mdio-mux/mdio@1/ethernet-phy@1");
+ if (ephy_node < 0) {
debug("failed to get mdio-mux with internal PHY\n");
- return node;
+ return ephy_node;
}
- ret = fdt_node_check_compatible(gd->fdt_blob, node,
+ /* This is not the phy we are looking for */
+ if (ephy_node != ephy_handle)
+ return 0;
+
+ ret = fdt_node_check_compatible(gd->fdt_blob, ephy_node,
"allwinner,sun8i-h3-mdio-internal");
if (ret < 0) {
debug("failed to find mdio-internal node\n");
return ret;
}
- ret = clk_get_by_index_nodev(offset_to_ofnode(node), 0,
+ ret = clk_get_by_index_nodev(offset_to_ofnode(ephy_node), 0,
&priv->ephy_clk);
if (ret) {
dev_err(dev, "failed to get EPHY TX clock\n");
return ret;
}
- ret = reset_get_by_index_nodev(offset_to_ofnode(node), 0,
+ ret = reset_get_by_index_nodev(offset_to_ofnode(ephy_node), 0,
&priv->ephy_rst);
if (ret) {
dev_err(dev, "failed to get EPHY TX reset\n");
diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig
index 82bc9f5..ecf642d 100644
--- a/drivers/net/ti/Kconfig
+++ b/drivers/net/ti/Kconfig
@@ -18,3 +18,11 @@
bool "TI Keystone 2 Ethernet"
help
This driver supports the TI Keystone 2 Ethernet subsystem
+
+config TI_AM65_CPSW_NUSS
+ bool "TI K3 AM65x MCU CPSW Nuss Ethernet controller driver"
+ depends on ARCH_K3
+ select PHYLIB
+ help
+ This driver supports TI K3 MCU CPSW Nuss Ethernet controller
+ in Texas Instruments K3 AM65x SoCs.
diff --git a/drivers/net/ti/Makefile b/drivers/net/ti/Makefile
index ee3e4eb..8d3808b 100644
--- a/drivers/net/ti/Makefile
+++ b/drivers/net/ti/Makefile
@@ -5,3 +5,4 @@
obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o cpsw-common.o cpsw_mdio.o
obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o cpsw_mdio.o
+obj-$(CONFIG_TI_AM65_CPSW_NUSS) += am65-cpsw-nuss.o cpsw_mdio.o
diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c
new file mode 100644
index 0000000..e11fbde
--- /dev/null
+++ b/drivers/net/ti/am65-cpsw-nuss.c
@@ -0,0 +1,792 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments K3 AM65 Ethernet Switch SubSystem Driver
+ *
+ * Copyright (C) 2019, Texas Instruments, Incorporated
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/lists.h>
+#include <dma-uclass.h>
+#include <dm/of_access.h>
+#include <miiphy.h>
+#include <net.h>
+#include <phy.h>
+#include <power-domain.h>
+#include <linux/soc/ti/ti-udma.h>
+
+#include "cpsw_mdio.h"
+
+#define AM65_CPSW_CPSWNU_MAX_PORTS 2
+
+#define AM65_CPSW_SS_BASE 0x0
+#define AM65_CPSW_SGMII_BASE 0x100
+#define AM65_CPSW_MDIO_BASE 0xf00
+#define AM65_CPSW_XGMII_BASE 0x2100
+#define AM65_CPSW_CPSW_NU_BASE 0x20000
+#define AM65_CPSW_CPSW_NU_ALE_BASE 0x1e000
+
+#define AM65_CPSW_CPSW_NU_PORTS_OFFSET 0x1000
+#define AM65_CPSW_CPSW_NU_PORT_MACSL_OFFSET 0x330
+
+#define AM65_CPSW_MDIO_BUS_FREQ_DEF 1000000
+
+#define AM65_CPSW_CTL_REG 0x4
+#define AM65_CPSW_STAT_PORT_EN_REG 0x14
+#define AM65_CPSW_PTYPE_REG 0x18
+
+#define AM65_CPSW_CTL_REG_P0_ENABLE BIT(2)
+#define AM65_CPSW_CTL_REG_P0_TX_CRC_REMOVE BIT(13)
+#define AM65_CPSW_CTL_REG_P0_RX_PAD BIT(14)
+
+#define AM65_CPSW_P0_FLOW_ID_REG 0x8
+#define AM65_CPSW_PN_RX_MAXLEN_REG 0x24
+#define AM65_CPSW_PN_REG_SA_L 0x308
+#define AM65_CPSW_PN_REG_SA_H 0x30c
+
+#define AM65_CPSW_ALE_CTL_REG 0x8
+#define AM65_CPSW_ALE_CTL_REG_ENABLE BIT(31)
+#define AM65_CPSW_ALE_CTL_REG_RESET_TBL BIT(30)
+#define AM65_CPSW_ALE_CTL_REG_BYPASS BIT(4)
+#define AM65_CPSW_ALE_PN_CTL_REG(x) (0x40 + (x) * 4)
+#define AM65_CPSW_ALE_PN_CTL_REG_MODE_FORWARD 0x3
+#define AM65_CPSW_ALE_PN_CTL_REG_MAC_ONLY BIT(11)
+
+#define AM65_CPSW_MACSL_CTL_REG 0x0
+#define AM65_CPSW_MACSL_CTL_REG_IFCTL_A BIT(15)
+#define AM65_CPSW_MACSL_CTL_REG_GIG BIT(7)
+#define AM65_CPSW_MACSL_CTL_REG_GMII_EN BIT(5)
+#define AM65_CPSW_MACSL_CTL_REG_LOOPBACK BIT(1)
+#define AM65_CPSW_MACSL_CTL_REG_FULL_DUPLEX BIT(0)
+#define AM65_CPSW_MACSL_RESET_REG 0x8
+#define AM65_CPSW_MACSL_RESET_REG_RESET BIT(0)
+#define AM65_CPSW_MACSL_STATUS_REG 0x4
+#define AM65_CPSW_MACSL_RESET_REG_PN_IDLE BIT(31)
+#define AM65_CPSW_MACSL_RESET_REG_PN_E_IDLE BIT(30)
+#define AM65_CPSW_MACSL_RESET_REG_PN_P_IDLE BIT(29)
+#define AM65_CPSW_MACSL_RESET_REG_PN_TX_IDLE BIT(28)
+#define AM65_CPSW_MACSL_RESET_REG_IDLE_MASK \
+ (AM65_CPSW_MACSL_RESET_REG_PN_IDLE | \
+ AM65_CPSW_MACSL_RESET_REG_PN_E_IDLE | \
+ AM65_CPSW_MACSL_RESET_REG_PN_P_IDLE | \
+ AM65_CPSW_MACSL_RESET_REG_PN_TX_IDLE)
+
+#define AM65_CPSW_CPPI_PKT_TYPE 0x7
+
+struct am65_cpsw_port {
+ fdt_addr_t port_base;
+ fdt_addr_t macsl_base;
+ bool disabled;
+ u32 mac_control;
+};
+
+struct am65_cpsw_common {
+ struct udevice *dev;
+ fdt_addr_t ss_base;
+ fdt_addr_t cpsw_base;
+ fdt_addr_t mdio_base;
+ fdt_addr_t ale_base;
+ fdt_addr_t gmii_sel;
+ fdt_addr_t mac_efuse;
+
+ struct clk fclk;
+ struct power_domain pwrdmn;
+
+ u32 port_num;
+ struct am65_cpsw_port ports[AM65_CPSW_CPSWNU_MAX_PORTS];
+ u32 rflow_id_base;
+
+ struct mii_dev *bus;
+ u32 bus_freq;
+
+ struct dma dma_tx;
+ struct dma dma_rx;
+ u32 rx_next;
+ u32 rx_pend;
+ bool started;
+};
+
+struct am65_cpsw_priv {
+ struct udevice *dev;
+ struct am65_cpsw_common *cpsw_common;
+ u32 port_id;
+
+ struct phy_device *phydev;
+ bool has_phy;
+ ofnode phy_node;
+ u32 phy_addr;
+};
+
+#ifdef PKTSIZE_ALIGN
+#define UDMA_RX_BUF_SIZE PKTSIZE_ALIGN
+#else
+#define UDMA_RX_BUF_SIZE ALIGN(1522, ARCH_DMA_MINALIGN)
+#endif
+
+#ifdef PKTBUFSRX
+#define UDMA_RX_DESC_NUM PKTBUFSRX
+#else
+#define UDMA_RX_DESC_NUM 4
+#endif
+
+#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
+ ((mac)[2] << 16) | ((mac)[3] << 24))
+#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
+
+static void am65_cpsw_set_sl_mac(struct am65_cpsw_port *slave,
+ unsigned char *addr)
+{
+ writel(mac_hi(addr),
+ slave->port_base + AM65_CPSW_PN_REG_SA_H);
+ writel(mac_lo(addr),
+ slave->port_base + AM65_CPSW_PN_REG_SA_L);
+}
+
+int am65_cpsw_macsl_reset(struct am65_cpsw_port *slave)
+{
+ u32 i = 100;
+
+ /* Set the soft reset bit */
+ writel(AM65_CPSW_MACSL_RESET_REG_RESET,
+ slave->macsl_base + AM65_CPSW_MACSL_RESET_REG);
+
+ while ((readl(slave->macsl_base + AM65_CPSW_MACSL_RESET_REG) &
+ AM65_CPSW_MACSL_RESET_REG_RESET) && i--)
+ cpu_relax();
+
+ /* Timeout on the reset */
+ return i;
+}
+
+static int am65_cpsw_macsl_wait_for_idle(struct am65_cpsw_port *slave)
+{
+ u32 i = 100;
+
+ while ((readl(slave->macsl_base + AM65_CPSW_MACSL_STATUS_REG) &
+ AM65_CPSW_MACSL_RESET_REG_IDLE_MASK) && i--)
+ cpu_relax();
+
+ return i;
+}
+
+static int am65_cpsw_update_link(struct am65_cpsw_priv *priv)
+{
+ struct am65_cpsw_common *common = priv->cpsw_common;
+ struct am65_cpsw_port *port = &common->ports[priv->port_id];
+ struct phy_device *phy = priv->phydev;
+ u32 mac_control = 0;
+
+ if (phy->link) { /* link up */
+ mac_control = /*AM65_CPSW_MACSL_CTL_REG_LOOPBACK |*/
+ AM65_CPSW_MACSL_CTL_REG_GMII_EN;
+ if (phy->speed == 1000)
+ mac_control |= AM65_CPSW_MACSL_CTL_REG_GIG;
+ if (phy->duplex == DUPLEX_FULL)
+ mac_control |= AM65_CPSW_MACSL_CTL_REG_FULL_DUPLEX;
+ if (phy->speed == 100)
+ mac_control |= AM65_CPSW_MACSL_CTL_REG_IFCTL_A;
+ }
+
+ if (mac_control == port->mac_control)
+ goto out;
+
+ if (mac_control) {
+ printf("link up on port %d, speed %d, %s duplex\n",
+ priv->port_id, phy->speed,
+ (phy->duplex == DUPLEX_FULL) ? "full" : "half");
+ } else {
+ printf("link down on port %d\n", priv->port_id);
+ }
+
+ writel(mac_control, port->macsl_base + AM65_CPSW_MACSL_CTL_REG);
+ port->mac_control = mac_control;
+
+out:
+ return phy->link;
+}
+
+#define AM65_GMII_SEL_MODE_MII 0
+#define AM65_GMII_SEL_MODE_RMII 1
+#define AM65_GMII_SEL_MODE_RGMII 2
+
+#define AM65_GMII_SEL_RGMII_IDMODE BIT(4)
+
+static void am65_cpsw_gmii_sel_k3(struct am65_cpsw_priv *priv,
+ phy_interface_t phy_mode, int slave)
+{
+ struct am65_cpsw_common *common = priv->cpsw_common;
+ u32 reg;
+ u32 mode = 0;
+ bool rgmii_id = false;
+
+ reg = readl(common->gmii_sel);
+
+ dev_dbg(common->dev, "old gmii_sel: %08x\n", reg);
+
+ switch (phy_mode) {
+ case PHY_INTERFACE_MODE_RMII:
+ mode = AM65_GMII_SEL_MODE_RMII;
+ break;
+
+ case PHY_INTERFACE_MODE_RGMII:
+ mode = AM65_GMII_SEL_MODE_RGMII;
+ break;
+
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ mode = AM65_GMII_SEL_MODE_RGMII;
+ rgmii_id = true;
+ break;
+
+ default:
+ dev_warn(common->dev,
+ "Unsupported PHY mode: %u. Defaulting to MII.\n",
+ phy_mode);
+ /* fallthrough */
+ case PHY_INTERFACE_MODE_MII:
+ mode = AM65_GMII_SEL_MODE_MII;
+ break;
+ };
+
+ if (rgmii_id)
+ mode |= AM65_GMII_SEL_RGMII_IDMODE;
+
+ reg = mode;
+ dev_dbg(common->dev, "gmii_sel PHY mode: %u, new gmii_sel: %08x\n",
+ phy_mode, reg);
+ writel(reg, common->gmii_sel);
+
+ reg = readl(common->gmii_sel);
+ if (reg != mode)
+ dev_err(common->dev,
+ "gmii_sel PHY mode NOT SET!: requested: %08x, gmii_sel: %08x\n",
+ mode, reg);
+}
+
+static int am65_cpsw_start(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct am65_cpsw_priv *priv = dev_get_priv(dev);
+ struct am65_cpsw_common *common = priv->cpsw_common;
+ struct am65_cpsw_port *port = &common->ports[priv->port_id];
+ struct am65_cpsw_port *port0 = &common->ports[0];
+ int ret, i;
+
+ ret = power_domain_on(&common->pwrdmn);
+ if (ret) {
+ dev_err(dev, "power_domain_on() failed %d\n", ret);
+ goto out;
+ }
+
+ ret = clk_enable(&common->fclk);
+ if (ret) {
+ dev_err(dev, "clk enabled failed %d\n", ret);
+ goto err_off_pwrdm;
+ }
+
+ common->rx_next = 0;
+ common->rx_pend = 0;
+ ret = dma_get_by_name(common->dev, "tx0", &common->dma_tx);
+ if (ret) {
+ dev_err(dev, "TX dma get failed %d\n", ret);
+ goto err_off_clk;
+ }
+ ret = dma_get_by_name(common->dev, "rx", &common->dma_rx);
+ if (ret) {
+ dev_err(dev, "RX dma get failed %d\n", ret);
+ goto err_free_tx;
+ }
+
+ for (i = 0; i < UDMA_RX_DESC_NUM; i++) {
+ ret = dma_prepare_rcv_buf(&common->dma_rx,
+ net_rx_packets[i],
+ UDMA_RX_BUF_SIZE);
+ if (ret) {
+ dev_err(dev, "RX dma add buf failed %d\n", ret);
+ goto err_free_tx;
+ }
+ }
+
+ ret = dma_enable(&common->dma_tx);
+ if (ret) {
+ dev_err(dev, "TX dma_enable failed %d\n", ret);
+ goto err_free_rx;
+ }
+ ret = dma_enable(&common->dma_rx);
+ if (ret) {
+ dev_err(dev, "RX dma_enable failed %d\n", ret);
+ goto err_dis_tx;
+ }
+
+ /* Control register */
+ writel(AM65_CPSW_CTL_REG_P0_ENABLE |
+ AM65_CPSW_CTL_REG_P0_TX_CRC_REMOVE |
+ AM65_CPSW_CTL_REG_P0_RX_PAD,
+ common->cpsw_base + AM65_CPSW_CTL_REG);
+
+ /* disable priority elevation */
+ writel(0, common->cpsw_base + AM65_CPSW_PTYPE_REG);
+
+ /* enable statistics */
+ writel(BIT(0) | BIT(priv->port_id),
+ common->cpsw_base + AM65_CPSW_STAT_PORT_EN_REG);
+
+ /* Port 0 length register */
+ writel(PKTSIZE_ALIGN, port0->port_base + AM65_CPSW_PN_RX_MAXLEN_REG);
+
+ /* set base flow_id */
+ writel(common->rflow_id_base,
+ port0->port_base + AM65_CPSW_P0_FLOW_ID_REG);
+
+ /* Reset and enable the ALE */
+ writel(AM65_CPSW_ALE_CTL_REG_ENABLE | AM65_CPSW_ALE_CTL_REG_RESET_TBL |
+ AM65_CPSW_ALE_CTL_REG_BYPASS,
+ common->ale_base + AM65_CPSW_ALE_CTL_REG);
+
+ /* port 0 put into forward mode */
+ writel(AM65_CPSW_ALE_PN_CTL_REG_MODE_FORWARD,
+ common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(0));
+
+ /* PORT x configuration */
+
+ /* Port x Max length register */
+ writel(PKTSIZE_ALIGN, port->port_base + AM65_CPSW_PN_RX_MAXLEN_REG);
+
+ /* Port x set mac */
+ am65_cpsw_set_sl_mac(port, pdata->enetaddr);
+
+ /* Port x ALE: mac_only, Forwarding */
+ writel(AM65_CPSW_ALE_PN_CTL_REG_MAC_ONLY |
+ AM65_CPSW_ALE_PN_CTL_REG_MODE_FORWARD,
+ common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(priv->port_id));
+
+ port->mac_control = 0;
+ if (!am65_cpsw_macsl_reset(port)) {
+ dev_err(dev, "mac_sl reset failed\n");
+ ret = -EFAULT;
+ goto err_dis_rx;
+ }
+
+ ret = phy_startup(priv->phydev);
+ if (ret) {
+ dev_err(dev, "phy_startup failed\n");
+ goto err_dis_rx;
+ }
+
+ ret = am65_cpsw_update_link(priv);
+ if (!ret) {
+ ret = -ENODEV;
+ goto err_phy_shutdown;
+ }
+
+ common->started = true;
+
+ return 0;
+
+err_phy_shutdown:
+ phy_shutdown(priv->phydev);
+err_dis_rx:
+ /* disable ports */
+ writel(0, common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(priv->port_id));
+ writel(0, common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(0));
+ if (!am65_cpsw_macsl_wait_for_idle(port))
+ dev_err(dev, "mac_sl idle timeout\n");
+ writel(0, port->macsl_base + AM65_CPSW_MACSL_CTL_REG);
+ writel(0, common->ale_base + AM65_CPSW_ALE_CTL_REG);
+ writel(0, common->cpsw_base + AM65_CPSW_CTL_REG);
+
+ dma_disable(&common->dma_rx);
+err_dis_tx:
+ dma_disable(&common->dma_tx);
+err_free_rx:
+ dma_free(&common->dma_rx);
+err_free_tx:
+ dma_free(&common->dma_tx);
+err_off_clk:
+ clk_disable(&common->fclk);
+err_off_pwrdm:
+ power_domain_off(&common->pwrdmn);
+out:
+ dev_err(dev, "%s end error\n", __func__);
+
+ return ret;
+}
+
+static int am65_cpsw_send(struct udevice *dev, void *packet, int length)
+{
+ struct am65_cpsw_priv *priv = dev_get_priv(dev);
+ struct am65_cpsw_common *common = priv->cpsw_common;
+ struct ti_udma_drv_packet_data packet_data;
+ int ret;
+
+ packet_data.pkt_type = AM65_CPSW_CPPI_PKT_TYPE;
+ packet_data.dest_tag = priv->port_id;
+ ret = dma_send(&common->dma_tx, packet, length, &packet_data);
+ if (ret) {
+ dev_err(dev, "TX dma_send failed %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int am65_cpsw_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct am65_cpsw_priv *priv = dev_get_priv(dev);
+ struct am65_cpsw_common *common = priv->cpsw_common;
+
+ /* try to receive a new packet */
+ return dma_receive(&common->dma_rx, (void **)packetp, NULL);
+}
+
+static int am65_cpsw_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+ struct am65_cpsw_priv *priv = dev_get_priv(dev);
+ struct am65_cpsw_common *common = priv->cpsw_common;
+ int ret;
+
+ if (length > 0) {
+ u32 pkt = common->rx_next % UDMA_RX_DESC_NUM;
+
+ ret = dma_prepare_rcv_buf(&common->dma_rx,
+ net_rx_packets[pkt],
+ UDMA_RX_BUF_SIZE);
+ if (ret)
+ dev_err(dev, "RX dma free_pkt failed %d\n", ret);
+ common->rx_next++;
+ }
+
+ return 0;
+}
+
+static void am65_cpsw_stop(struct udevice *dev)
+{
+ struct am65_cpsw_priv *priv = dev_get_priv(dev);
+ struct am65_cpsw_common *common = priv->cpsw_common;
+ struct am65_cpsw_port *port = &common->ports[priv->port_id];
+
+ if (!common->started)
+ return;
+
+ phy_shutdown(priv->phydev);
+
+ writel(0, common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(priv->port_id));
+ writel(0, common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(0));
+ if (!am65_cpsw_macsl_wait_for_idle(port))
+ dev_err(dev, "mac_sl idle timeout\n");
+ writel(0, port->macsl_base + AM65_CPSW_MACSL_CTL_REG);
+ writel(0, common->ale_base + AM65_CPSW_ALE_CTL_REG);
+ writel(0, common->cpsw_base + AM65_CPSW_CTL_REG);
+
+ dma_disable(&common->dma_tx);
+ dma_free(&common->dma_tx);
+
+ dma_disable(&common->dma_rx);
+ dma_free(&common->dma_rx);
+
+ common->started = false;
+}
+
+static int am65_cpsw_read_rom_hwaddr(struct udevice *dev)
+{
+ struct am65_cpsw_priv *priv = dev_get_priv(dev);
+ struct am65_cpsw_common *common = priv->cpsw_common;
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ u32 mac_hi, mac_lo;
+
+ if (common->mac_efuse == FDT_ADDR_T_NONE)
+ return -1;
+
+ mac_lo = readl(common->mac_efuse);
+ mac_hi = readl(common->mac_efuse + 4);
+ pdata->enetaddr[0] = (mac_hi >> 8) & 0xff;
+ pdata->enetaddr[1] = mac_hi & 0xff;
+ pdata->enetaddr[2] = (mac_lo >> 24) & 0xff;
+ pdata->enetaddr[3] = (mac_lo >> 16) & 0xff;
+ pdata->enetaddr[4] = (mac_lo >> 8) & 0xff;
+ pdata->enetaddr[5] = mac_lo & 0xff;
+
+ return 0;
+}
+
+static const struct eth_ops am65_cpsw_ops = {
+ .start = am65_cpsw_start,
+ .send = am65_cpsw_send,
+ .recv = am65_cpsw_recv,
+ .free_pkt = am65_cpsw_free_pkt,
+ .stop = am65_cpsw_stop,
+ .read_rom_hwaddr = am65_cpsw_read_rom_hwaddr,
+};
+
+static int am65_cpsw_mdio_init(struct udevice *dev)
+{
+ struct am65_cpsw_priv *priv = dev_get_priv(dev);
+ struct am65_cpsw_common *cpsw_common = priv->cpsw_common;
+
+ if (!priv->has_phy || cpsw_common->bus)
+ return 0;
+
+ cpsw_common->bus = cpsw_mdio_init(dev->name,
+ cpsw_common->mdio_base,
+ cpsw_common->bus_freq,
+ clk_get_rate(&cpsw_common->fclk));
+ if (!cpsw_common->bus)
+ return -EFAULT;
+
+ return 0;
+}
+
+static int am65_cpsw_phy_init(struct udevice *dev)
+{
+ struct am65_cpsw_priv *priv = dev_get_priv(dev);
+ struct am65_cpsw_common *cpsw_common = priv->cpsw_common;
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct phy_device *phydev;
+ u32 supported = PHY_GBIT_FEATURES;
+ int ret;
+
+ phydev = phy_connect(cpsw_common->bus,
+ priv->phy_addr,
+ priv->dev,
+ pdata->phy_interface);
+
+ if (!phydev) {
+ dev_err(dev, "phy_connect() failed\n");
+ return -ENODEV;
+ }
+
+ phydev->supported &= supported;
+ if (pdata->max_speed) {
+ ret = phy_set_supported(phydev, pdata->max_speed);
+ if (ret)
+ return ret;
+ }
+ phydev->advertising = phydev->supported;
+
+ if (ofnode_valid(priv->phy_node))
+ phydev->node = priv->phy_node;
+
+ priv->phydev = phydev;
+ ret = phy_config(phydev);
+ if (ret < 0)
+ pr_err("phy_config() failed: %d", ret);
+
+ return ret;
+}
+
+static int am65_cpsw_ofdata_parse_phy(struct udevice *dev, ofnode port_np)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct am65_cpsw_priv *priv = dev_get_priv(dev);
+ struct ofnode_phandle_args out_args;
+ const char *phy_mode;
+ int ret = 0;
+
+ phy_mode = ofnode_read_string(port_np, "phy-mode");
+ if (phy_mode) {
+ pdata->phy_interface =
+ phy_get_interface_by_name(phy_mode);
+ if (pdata->phy_interface == -1) {
+ dev_err(dev, "Invalid PHY mode '%s', port %u\n",
+ phy_mode, priv->port_id);
+ ret = -EINVAL;
+ goto out;
+ }
+ }
+
+ ofnode_read_u32(port_np, "max-speed", (u32 *)&pdata->max_speed);
+ if (pdata->max_speed)
+ dev_err(dev, "Port %u speed froced to %uMbit\n",
+ priv->port_id, pdata->max_speed);
+
+ priv->has_phy = true;
+ ret = ofnode_parse_phandle_with_args(port_np, "phy-handle",
+ NULL, 0, 0, &out_args);
+ if (ret) {
+ dev_err(dev, "can't parse phy-handle port %u (%d)\n",
+ priv->port_id, ret);
+ priv->has_phy = false;
+ ret = 0;
+ }
+
+ priv->phy_node = out_args.node;
+ if (priv->has_phy) {
+ ret = ofnode_read_u32(priv->phy_node, "reg", &priv->phy_addr);
+ if (ret) {
+ dev_err(dev, "failed to get phy_addr port %u (%d)\n",
+ priv->port_id, ret);
+ goto out;
+ }
+ }
+
+out:
+ return ret;
+}
+
+static int am65_cpsw_probe_cpsw(struct udevice *dev)
+{
+ struct am65_cpsw_priv *priv = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct am65_cpsw_common *cpsw_common;
+ ofnode ports_np, node;
+ int ret, i;
+
+ priv->dev = dev;
+
+ cpsw_common = calloc(1, sizeof(*priv->cpsw_common));
+ if (!cpsw_common)
+ return -ENOMEM;
+ priv->cpsw_common = cpsw_common;
+
+ cpsw_common->dev = dev;
+ cpsw_common->ss_base = dev_read_addr(dev);
+ if (cpsw_common->ss_base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+ cpsw_common->mac_efuse = devfdt_get_addr_name(dev, "mac_efuse");
+ /* no err check - optional */
+
+ ret = power_domain_get_by_index(dev, &cpsw_common->pwrdmn, 0);
+ if (ret) {
+ dev_err(dev, "failed to get pwrdmn: %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_get_by_name(dev, "fck", &cpsw_common->fclk);
+ if (ret) {
+ power_domain_free(&cpsw_common->pwrdmn);
+ dev_err(dev, "failed to get clock %d\n", ret);
+ return ret;
+ }
+
+ cpsw_common->cpsw_base = cpsw_common->ss_base + AM65_CPSW_CPSW_NU_BASE;
+ cpsw_common->ale_base = cpsw_common->cpsw_base +
+ AM65_CPSW_CPSW_NU_ALE_BASE;
+ cpsw_common->mdio_base = cpsw_common->ss_base + AM65_CPSW_MDIO_BASE;
+
+ cpsw_common->rflow_id_base = 0;
+ cpsw_common->rflow_id_base =
+ dev_read_u32_default(dev, "ti,rx-flow-id-base",
+ cpsw_common->rflow_id_base);
+
+ ports_np = dev_read_subnode(dev, "ports");
+ if (!ofnode_valid(ports_np)) {
+ ret = -ENOENT;
+ goto out;
+ }
+
+ ofnode_for_each_subnode(node, ports_np) {
+ const char *node_name;
+ u32 port_id;
+ bool disabled;
+
+ node_name = ofnode_get_name(node);
+
+ disabled = !ofnode_is_available(node);
+
+ ret = ofnode_read_u32(node, "reg", &port_id);
+ if (ret) {
+ dev_err(dev, "%s: failed to get port_id (%d)\n",
+ node_name, ret);
+ goto out;
+ }
+
+ if (port_id >= AM65_CPSW_CPSWNU_MAX_PORTS) {
+ dev_err(dev, "%s: invalid port_id (%d)\n",
+ node_name, port_id);
+ ret = -EINVAL;
+ goto out;
+ }
+ cpsw_common->port_num++;
+
+ if (!port_id)
+ continue;
+
+ priv->port_id = port_id;
+ cpsw_common->ports[port_id].disabled = disabled;
+ if (disabled)
+ continue;
+
+ ret = am65_cpsw_ofdata_parse_phy(dev, node);
+ if (ret)
+ goto out;
+ }
+
+ for (i = 0; i < AM65_CPSW_CPSWNU_MAX_PORTS; i++) {
+ struct am65_cpsw_port *port = &cpsw_common->ports[i];
+
+ port->port_base = cpsw_common->cpsw_base +
+ AM65_CPSW_CPSW_NU_PORTS_OFFSET +
+ (i * AM65_CPSW_CPSW_NU_PORTS_OFFSET);
+ port->macsl_base = port->port_base +
+ AM65_CPSW_CPSW_NU_PORT_MACSL_OFFSET;
+ }
+
+ node = dev_read_subnode(dev, "cpsw-phy-sel");
+ if (!ofnode_valid(node)) {
+ dev_err(dev, "can't find cpsw-phy-sel\n");
+ ret = -ENOENT;
+ goto out;
+ }
+
+ cpsw_common->gmii_sel = ofnode_get_addr(node);
+ if (cpsw_common->gmii_sel == FDT_ADDR_T_NONE) {
+ dev_err(dev, "failed to get gmii_sel base\n");
+ goto out;
+ }
+
+ node = dev_read_subnode(dev, "mdio");
+ if (!ofnode_valid(node)) {
+ dev_err(dev, "can't find mdio\n");
+ ret = -ENOENT;
+ goto out;
+ }
+
+ cpsw_common->bus_freq =
+ dev_read_u32_default(dev, "bus_freq",
+ AM65_CPSW_MDIO_BUS_FREQ_DEF);
+
+ am65_cpsw_gmii_sel_k3(priv, pdata->phy_interface, priv->port_id);
+
+ ret = am65_cpsw_mdio_init(dev);
+ if (ret)
+ goto out;
+
+ ret = am65_cpsw_phy_init(dev);
+ if (ret)
+ goto out;
+
+ dev_info(dev, "K3 CPSW: nuss_ver: 0x%08X cpsw_ver: 0x%08X ale_ver: 0x%08X Ports:%u rflow_id_base:%u mdio_freq:%u\n",
+ readl(cpsw_common->ss_base),
+ readl(cpsw_common->cpsw_base),
+ readl(cpsw_common->ale_base),
+ cpsw_common->port_num,
+ cpsw_common->rflow_id_base,
+ cpsw_common->bus_freq);
+
+out:
+ clk_free(&cpsw_common->fclk);
+ power_domain_free(&cpsw_common->pwrdmn);
+ return ret;
+}
+
+static const struct udevice_id am65_cpsw_nuss_ids[] = {
+ { .compatible = "ti,am654-cpsw-nuss" },
+ { }
+};
+
+U_BOOT_DRIVER(am65_cpsw_nuss_slave) = {
+ .name = "am65_cpsw_nuss_slave",
+ .id = UCLASS_ETH,
+ .of_match = am65_cpsw_nuss_ids,
+ .probe = am65_cpsw_probe_cpsw,
+ .ops = &am65_cpsw_ops,
+ .priv_auto_alloc_size = sizeof(struct am65_cpsw_priv),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
diff --git a/drivers/net/ti/cpsw-common.c b/drivers/net/ti/cpsw-common.c
index ac12cfe..21b8bbd 100644
--- a/drivers/net/ti/cpsw-common.c
+++ b/drivers/net/ti/cpsw-common.c
@@ -7,7 +7,6 @@
#include <common.h>
#include <dm.h>
-#include <environment.h>
#include <fdt_support.h>
#include <asm/io.h>
#include <cpsw.h>
diff --git a/drivers/net/ti/cpsw_mdio.c b/drivers/net/ti/cpsw_mdio.c
index 70f547e..6e8f652 100644
--- a/drivers/net/ti/cpsw_mdio.c
+++ b/drivers/net/ti/cpsw_mdio.c
@@ -125,7 +125,7 @@
return val & GENMASK(15, 0);
}
-struct mii_dev *cpsw_mdio_init(const char *name, u32 mdio_base,
+struct mii_dev *cpsw_mdio_init(const char *name, phys_addr_t mdio_base,
u32 bus_freq, int fck_freq)
{
struct cpsw_mdio *cpsw_mdio;
@@ -144,7 +144,7 @@
return NULL;
}
- cpsw_mdio->regs = (struct cpsw_mdio_regs *)mdio_base;
+ cpsw_mdio->regs = (struct cpsw_mdio_regs *)(uintptr_t)mdio_base;
if (!bus_freq || !fck_freq)
cpsw_mdio->div = CPSW_MDIO_DIV_DEF;
diff --git a/drivers/net/ti/cpsw_mdio.h b/drivers/net/ti/cpsw_mdio.h
index 4a76d4e..dbf4a2d 100644
--- a/drivers/net/ti/cpsw_mdio.h
+++ b/drivers/net/ti/cpsw_mdio.h
@@ -10,7 +10,7 @@
struct cpsw_mdio;
-struct mii_dev *cpsw_mdio_init(const char *name, u32 mdio_base,
+struct mii_dev *cpsw_mdio_init(const char *name, phys_addr_t mdio_base,
u32 bus_freq, int fck_freq);
void cpsw_mdio_free(struct mii_dev *bus);
u32 cpsw_mdio_get_alive(struct mii_dev *bus);
diff --git a/drivers/net/ti/davinci_emac.c b/drivers/net/ti/davinci_emac.c
index 9d53984..2bd9c51 100644
--- a/drivers/net/ti/davinci_emac.c
+++ b/drivers/net/ti/davinci_emac.c
@@ -26,7 +26,6 @@
#include <net.h>
#include <miiphy.h>
#include <malloc.h>
-#include <netdev.h>
#include <linux/compiler.h>
#include <asm/arch/emac_defs.h>
#include <asm/io.h>
@@ -107,8 +106,9 @@
phy_t phy[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT];
-static int davinci_eth_set_mac_addr(struct eth_device *dev)
+static int davinci_emac_write_hwaddr(struct udevice *dev)
{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
unsigned long mac_hi;
unsigned long mac_lo;
@@ -118,12 +118,12 @@
* Using channel 0 only - other channels are disabled
* */
writel(0, &adap_emac->MACINDEX);
- mac_hi = (dev->enetaddr[3] << 24) |
- (dev->enetaddr[2] << 16) |
- (dev->enetaddr[1] << 8) |
- (dev->enetaddr[0]);
- mac_lo = (dev->enetaddr[5] << 8) |
- (dev->enetaddr[4]);
+ mac_hi = (pdata->enetaddr[3] << 24) |
+ (pdata->enetaddr[2] << 16) |
+ (pdata->enetaddr[1] << 8) |
+ (pdata->enetaddr[0]);
+ mac_lo = (pdata->enetaddr[5] << 8) |
+ (pdata->enetaddr[4]);
writel(mac_hi, &adap_emac->MACADDRHI);
#if defined(DAVINCI_EMAC_VERSION2)
@@ -411,7 +411,7 @@
}
/* Eth device open */
-static int davinci_eth_open(struct eth_device *dev, bd_t *bis)
+static int davinci_emac_start(struct udevice *dev)
{
dv_reg_p addr;
u_int32_t clkdiv, cnt, mac_control;
@@ -447,7 +447,7 @@
writel(1, &adap_emac->TXCONTROL);
writel(1, &adap_emac->RXCONTROL);
- davinci_eth_set_mac_addr(dev);
+ davinci_emac_write_hwaddr(dev);
/* Set DMA 8 TX / 8 RX Head pointers to 0 */
addr = &adap_emac->TX0HDP;
@@ -588,7 +588,7 @@
}
/* Eth device close */
-static void davinci_eth_close(struct eth_device *dev)
+static void davinci_emac_stop(struct udevice *dev)
{
debug_emac("+ emac_close\n");
@@ -619,8 +619,8 @@
* This function sends a single packet on the network and returns
* positive number (number of bytes transmitted) or negative for error
*/
-static int davinci_eth_send_packet (struct eth_device *dev,
- void *packet, int length)
+static int davinci_emac_send(struct udevice *dev,
+ void *packet, int length)
{
int ret_status = -1;
int index;
@@ -672,7 +672,7 @@
/*
* This function handles receipt of a packet from the network
*/
-static int davinci_eth_rcv_packet (struct eth_device *dev)
+static int davinci_emac_recv(struct udevice *dev, int flags, uchar **packetp)
{
volatile emac_desc *rx_curr_desc;
volatile emac_desc *curr_desc;
@@ -682,6 +682,7 @@
rx_curr_desc = emac_rx_active_head;
if (!rx_curr_desc)
return 0;
+ *packetp = rx_curr_desc->buffer;
status = rx_curr_desc->pkt_flag_len;
if ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0) {
if (status & EMAC_CPPI_RX_ERROR_FRAME) {
@@ -693,7 +694,6 @@
rx_curr_desc->buff_off_len & 0xffff;
invalidate_dcache_range(tmp, tmp + ALIGN(len, PKTALIGN));
- net_process_received_packet(rx_curr_desc->buffer, len);
ret = len;
}
@@ -742,6 +742,7 @@
}
return (ret);
}
+
return (0);
}
@@ -750,30 +751,12 @@
* EMAC modules power or pin multiplexors, that is done by board_init()
* much earlier in bootup process. Returns 1 on success, 0 otherwise.
*/
-int davinci_emac_initialize(void)
+static int davinci_emac_probe(struct udevice *dev)
{
u_int32_t phy_id;
u_int16_t tmp;
int i;
int ret;
- struct eth_device *dev;
-
- dev = malloc(sizeof *dev);
-
- if (dev == NULL)
- return -1;
-
- memset(dev, 0, sizeof *dev);
- strcpy(dev->name, "DaVinci-EMAC");
-
- dev->iobase = 0;
- dev->init = davinci_eth_open;
- dev->halt = davinci_eth_close;
- dev->send = davinci_eth_send_packet;
- dev->recv = davinci_eth_rcv_packet;
- dev->write_hwaddr = davinci_eth_set_mac_addr;
-
- eth_register(dev);
davinci_eth_mdio_enable();
@@ -854,5 +837,29 @@
phy[i].auto_negotiate(i);
}
#endif
- return(1);
+ return 0;
}
+
+static const struct eth_ops davinci_emac_ops = {
+ .start = davinci_emac_start,
+ .send = davinci_emac_send,
+ .recv = davinci_emac_recv,
+ .stop = davinci_emac_stop,
+ .write_hwaddr = davinci_emac_write_hwaddr,
+};
+
+static const struct udevice_id davinci_emac_ids[] = {
+ { .compatible = "ti,davinci-dm6467-emac" },
+ { .compatible = "ti,am3517-emac", },
+ { .compatible = "ti,dm816-emac", },
+ { }
+};
+
+U_BOOT_DRIVER(davinci_emac) = {
+ .name = "davinci_emac",
+ .id = UCLASS_ETH,
+ .of_match = davinci_emac_ids,
+ .probe = davinci_emac_probe,
+ .ops = &davinci_emac_ops,
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 06a9b4f..f85cdcb 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -259,8 +259,8 @@
{
struct tsec_private *priv = (struct tsec_private *)dev->priv;
struct tsec __iomem *regs = priv->regs;
- u16 status;
int result = 0;
+ u16 status;
int i;
/* Find an empty buffer descriptor */
@@ -268,7 +268,7 @@
in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
i++) {
if (i >= TOUT_LOOP) {
- debug("%s: tsec: tx buffers full\n", dev->name);
+ printf("%s: tsec: tx buffers full\n", dev->name);
return result;
}
}
@@ -287,7 +287,7 @@
in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
i++) {
if (i >= TOUT_LOOP) {
- debug("%s: tsec: tx error\n", dev->name);
+ printf("%s: tsec: tx error\n", dev->name);
return result;
}
}
@@ -560,6 +560,8 @@
struct tsec_private *priv = (struct tsec_private *)dev->priv;
#ifdef CONFIG_DM_ETH
struct eth_pdata *pdata = dev_get_platdata(dev);
+#else
+ struct eth_device *pdata = dev;
#endif
struct tsec __iomem *regs = priv->regs;
u32 tempval;
@@ -580,21 +582,12 @@
* order (BE), MACnADDR1 is set to 0xCDAB7856 and
* MACnADDR2 is set to 0x34120000.
*/
-#ifndef CONFIG_DM_ETH
- tempval = (dev->enetaddr[5] << 24) | (dev->enetaddr[4] << 16) |
- (dev->enetaddr[3] << 8) | dev->enetaddr[2];
-#else
tempval = (pdata->enetaddr[5] << 24) | (pdata->enetaddr[4] << 16) |
(pdata->enetaddr[3] << 8) | pdata->enetaddr[2];
-#endif
out_be32(®s->macstnaddr1, tempval);
-#ifndef CONFIG_DM_ETH
- tempval = (dev->enetaddr[1] << 24) | (dev->enetaddr[0] << 16);
-#else
tempval = (pdata->enetaddr[1] << 24) | (pdata->enetaddr[0] << 16);
-#endif
out_be32(®s->macstnaddr2, tempval);
@@ -708,9 +701,9 @@
*/
static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info)
{
+ struct tsec_private *priv;
struct eth_device *dev;
int i;
- struct tsec_private *priv;
dev = (struct eth_device *)malloc(sizeof(*dev));
@@ -794,12 +787,14 @@
#else /* CONFIG_DM_ETH */
int tsec_probe(struct udevice *dev)
{
- struct tsec_private *priv = dev_get_priv(dev);
struct eth_pdata *pdata = dev_get_platdata(dev);
- struct fsl_pq_mdio_info mdio_info;
+ struct tsec_private *priv = dev_get_priv(dev);
struct ofnode_phandle_args phandle_args;
- ofnode parent;
+ u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;
+ struct fsl_pq_mdio_info mdio_info;
const char *phy_mode;
+ fdt_addr_t reg;
+ ofnode parent;
int ret;
pdata->iobase = (phys_addr_t)dev_read_addr(dev);
@@ -807,7 +802,7 @@
if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
&phandle_args)) {
- debug("phy-handle does not exist under tsec %s\n", dev->name);
+ printf("phy-handle does not exist under tsec %s\n", dev->name);
return -ENOENT;
} else {
int reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
@@ -816,29 +811,27 @@
}
parent = ofnode_get_parent(phandle_args.node);
- if (ofnode_valid(parent)) {
- int reg = ofnode_get_addr_index(parent, 0);
-
- priv->phyregs_sgmii = (struct tsec_mii_mng *)reg;
- } else {
- debug("No parent node for PHY?\n");
+ if (!ofnode_valid(parent)) {
+ printf("No parent node for PHY?\n");
return -ENOENT;
}
- if (dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0,
- &phandle_args)) {
- priv->tbiaddr = CONFIG_SYS_TBIPA_VALUE;
- } else {
- int reg = ofnode_read_u32_default(phandle_args.node, "reg",
- CONFIG_SYS_TBIPA_VALUE);
- priv->tbiaddr = reg;
- }
+ reg = ofnode_get_addr_index(parent, 0);
+ priv->phyregs_sgmii = (struct tsec_mii_mng *)
+ (reg + TSEC_MDIO_REGS_OFFSET);
+
+ ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0,
+ &phandle_args);
+ if (ret == 0)
+ ofnode_read_u32(phandle_args.node, "reg", &tbiaddr);
+
+ priv->tbiaddr = tbiaddr;
phy_mode = dev_read_prop(dev, "phy-connection-type", NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
- debug("Invalid PHY interface '%s'\n", phy_mode);
+ printf("Invalid PHY interface '%s'\n", phy_mode);
return -EINVAL;
}
priv->interface = pdata->phy_interface;
@@ -887,7 +880,7 @@
};
static const struct udevice_id tsec_ids[] = {
- { .compatible = "fsl,tsec" },
+ { .compatible = "fsl,etsec2" },
{ }
};
diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
index d4965e2..47f101e 100644
--- a/drivers/nvme/nvme.c
+++ b/drivers/nvme/nvme.c
@@ -73,6 +73,9 @@
u64 *prp_pool;
int length = total_len;
int i, nprps;
+ u32 prps_per_page = (page_size >> 3) - 1;
+ u32 num_pages;
+
length -= (page_size - offset);
if (length <= 0) {
@@ -89,15 +92,20 @@
}
nprps = DIV_ROUND_UP(length, page_size);
+ num_pages = DIV_ROUND_UP(nprps, prps_per_page);
if (nprps > dev->prp_entry_num) {
free(dev->prp_pool);
- dev->prp_pool = malloc(nprps << 3);
+ /*
+ * Always increase in increments of pages. It doesn't waste
+ * much memory and reduces the number of allocations.
+ */
+ dev->prp_pool = memalign(page_size, num_pages * page_size);
if (!dev->prp_pool) {
printf("Error: malloc prp_pool fail\n");
return -ENOMEM;
}
- dev->prp_entry_num = nprps;
+ dev->prp_entry_num = prps_per_page * num_pages;
}
prp_pool = dev->prp_pool;
@@ -788,14 +796,6 @@
}
memset(ndev->queues, 0, NVME_Q_NUM * sizeof(struct nvme_queue *));
- ndev->prp_pool = malloc(MAX_PRP_POOL);
- if (!ndev->prp_pool) {
- ret = -ENOMEM;
- printf("Error: %s: Out of memory!\n", udev->name);
- goto free_nvme;
- }
- ndev->prp_entry_num = MAX_PRP_POOL >> 3;
-
ndev->cap = nvme_readq(&ndev->bar->cap);
ndev->q_depth = min_t(int, NVME_CAP_MQES(ndev->cap) + 1, NVME_Q_DEPTH);
ndev->db_stride = 1 << NVME_CAP_STRIDE(ndev->cap);
@@ -805,6 +805,15 @@
if (ret)
goto free_queue;
+ /* Allocate after the page size is known */
+ ndev->prp_pool = memalign(ndev->page_size, MAX_PRP_POOL);
+ if (!ndev->prp_pool) {
+ ret = -ENOMEM;
+ printf("Error: %s: Out of memory!\n", udev->name);
+ goto free_nvme;
+ }
+ ndev->prp_entry_num = MAX_PRP_POOL >> 3;
+
ret = nvme_setup_io_queues(ndev);
if (ret)
goto free_queue;
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 3fe38f7..bdfc0c1 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -145,4 +145,10 @@
Say Y here if you want to enable PCIe controller support on
Armada XP/38x SoCs.
+config PCI_KEYSTONE
+ bool "TI Keystone PCIe controller"
+ depends on DM_PCI
+ help
+ Say Y here if you want to enable PCI controller support on AM654 SoC.
+
endif
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index b5ebd50..e54a98b 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -38,3 +38,4 @@
pcie_layerscape_gen4_fixup.o
obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o
obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
+obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index b4c8556..ab5e499 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -4,6 +4,7 @@
*/
#include <common.h>
+#include <env.h>
#include <malloc.h>
#include <asm/fsl_serdes.h>
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index cf1e761..ab3e131 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -1341,10 +1341,56 @@
return bus_addr;
}
+static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags,
+ int ea_off)
+{
+ int ea_cnt, i, entry_size;
+ int bar_id = (bar - PCI_BASE_ADDRESS_0) >> 2;
+ u32 ea_entry;
+ phys_addr_t addr;
+
+ /* EA capability structure header */
+ dm_pci_read_config32(dev, ea_off, &ea_entry);
+ ea_cnt = (ea_entry >> 16) & PCI_EA_NUM_ENT_MASK;
+ ea_off += PCI_EA_FIRST_ENT;
+
+ for (i = 0; i < ea_cnt; i++, ea_off += entry_size) {
+ /* Entry header */
+ dm_pci_read_config32(dev, ea_off, &ea_entry);
+ entry_size = ((ea_entry & PCI_EA_ES) + 1) << 2;
+
+ if (((ea_entry & PCI_EA_BEI) >> 4) != bar_id)
+ continue;
+
+ /* Base address, 1st DW */
+ dm_pci_read_config32(dev, ea_off + 4, &ea_entry);
+ addr = ea_entry & PCI_EA_FIELD_MASK;
+ if (ea_entry & PCI_EA_IS_64) {
+ /* Base address, 2nd DW, skip over 4B MaxOffset */
+ dm_pci_read_config32(dev, ea_off + 12, &ea_entry);
+ addr |= ((u64)ea_entry) << 32;
+ }
+
+ /* size ignored for now */
+ return map_physmem(addr, flags, 0);
+ }
+
+ return 0;
+}
+
void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
{
pci_addr_t pci_bus_addr;
u32 bar_response;
+ int ea_off;
+
+ /*
+ * if the function supports Enhanced Allocation use that instead of
+ * BARs
+ */
+ ea_off = dm_pci_find_capability(dev, PCI_CAP_ID_EA);
+ if (ea_off)
+ return dm_pci_map_ea_bar(dev, bar, flags, ea_off);
/* read BAR address */
dm_pci_read_config32(dev, bar, &bar_response);
@@ -1448,6 +1494,30 @@
return dm_pci_find_next_ext_capability(dev, 0, cap);
}
+int dm_pci_flr(struct udevice *dev)
+{
+ int pcie_off;
+ u32 cap;
+
+ /* look for PCI Express Capability */
+ pcie_off = dm_pci_find_capability(dev, PCI_CAP_ID_EXP);
+ if (!pcie_off)
+ return -ENOENT;
+
+ /* check FLR capability */
+ dm_pci_read_config32(dev, pcie_off + PCI_EXP_DEVCAP, &cap);
+ if (!(cap & PCI_EXP_DEVCAP_FLR))
+ return -ENOENT;
+
+ dm_pci_clrset_config16(dev, pcie_off + PCI_EXP_DEVCTL, 0,
+ PCI_EXP_DEVCTL_BCR_FLR);
+
+ /* wait 100ms, per PCI spec */
+ mdelay(100);
+
+ return 0;
+}
+
UCLASS_DRIVER(pci) = {
.id = UCLASS_PCI,
.name = "pci",
@@ -1502,9 +1572,9 @@
* Enumerate all known controller devices. Enumeration has the side-
* effect of probing them, so PCIe devices will be enumerated too.
*/
- for (uclass_first_device(UCLASS_PCI, &bus);
+ for (uclass_first_device_check(UCLASS_PCI, &bus);
bus;
- uclass_next_device(&bus)) {
+ uclass_next_device_check(&bus)) {
;
}
}
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index e219572..5db24f1 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -17,6 +17,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <errno.h>
#include <asm/processor.h>
#include <asm/io.h>
diff --git a/drivers/pci/pci_common.c b/drivers/pci/pci_common.c
index 9f2d267..5231b69 100644
--- a/drivers/pci/pci_common.c
+++ b/drivers/pci/pci_common.c
@@ -11,6 +11,7 @@
#include <common.h>
#include <dm.h>
+#include <env.h>
#include <errno.h>
#include <pci.h>
#include <asm/io.h>
diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c
index e21dc10..f9b08f3 100644
--- a/drivers/pci/pci_mvebu.c
+++ b/drivers/pci/pci_mvebu.c
@@ -313,10 +313,6 @@
reg |= BIT(10); /* disable interrupts */
writel(reg, pcie->base + PCIE_CMD_OFF);
- /* Set BAR0 to internal registers */
- writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0));
- writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
-
/* PCI memory space */
pci_set_region(hose->regions + 0, pcie->mem.start,
pcie->mem.start, PCIE_MEM_SIZE, PCI_REGION_MEM);
@@ -326,6 +322,10 @@
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
hose->region_count = 2;
+ /* Set BAR0 to internal registers */
+ writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0));
+ writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
+
bus++;
return 0;
diff --git a/drivers/pci/pci_sh7751.c b/drivers/pci/pci_sh7751.c
index 2f918f1..53e1668 100644
--- a/drivers/pci/pci_sh7751.c
+++ b/drivers/pci/pci_sh7751.c
@@ -6,6 +6,7 @@
*/
#include <common.h>
+#include <dm.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/io.h>
@@ -19,82 +20,113 @@
#define SH7751_WCR3 (vu_long *)0xFF800010
#define SH7751_MCR (vu_long *)0xFF800014
#define SH7751_BCR3 (vu_short *)0xFF800050
-#define SH7751_PCICONF0 (vu_long *)0xFE200000
-#define SH7751_PCICONF1 (vu_long *)0xFE200004
-#define SH7751_PCICONF2 (vu_long *)0xFE200008
-#define SH7751_PCICONF3 (vu_long *)0xFE20000C
-#define SH7751_PCICONF4 (vu_long *)0xFE200010
-#define SH7751_PCICONF5 (vu_long *)0xFE200014
-#define SH7751_PCICONF6 (vu_long *)0xFE200018
-#define SH7751_PCICR (vu_long *)0xFE200100
-#define SH7751_PCILSR0 (vu_long *)0xFE200104
-#define SH7751_PCILSR1 (vu_long *)0xFE200108
-#define SH7751_PCILAR0 (vu_long *)0xFE20010C
-#define SH7751_PCILAR1 (vu_long *)0xFE200110
-#define SH7751_PCIMBR (vu_long *)0xFE2001C4
-#define SH7751_PCIIOBR (vu_long *)0xFE2001C8
-#define SH7751_PCIPINT (vu_long *)0xFE2001CC
-#define SH7751_PCIPINTM (vu_long *)0xFE2001D0
-#define SH7751_PCICLKR (vu_long *)0xFE2001D4
-#define SH7751_PCIBCR1 (vu_long *)0xFE2001E0
-#define SH7751_PCIBCR2 (vu_long *)0xFE2001E4
-#define SH7751_PCIWCR1 (vu_long *)0xFE2001E8
-#define SH7751_PCIWCR2 (vu_long *)0xFE2001EC
-#define SH7751_PCIWCR3 (vu_long *)0xFE2001F0
-#define SH7751_PCIMCR (vu_long *)0xFE2001F4
-#define SH7751_PCIBCR3 (vu_long *)0xFE2001F8
+#define SH7751_PCICONF0 (vu_long *)0xFE200000
+#define SH7751_PCICONF1 (vu_long *)0xFE200004
+#define SH7751_PCICONF2 (vu_long *)0xFE200008
+#define SH7751_PCICONF3 (vu_long *)0xFE20000C
+#define SH7751_PCICONF4 (vu_long *)0xFE200010
+#define SH7751_PCICONF5 (vu_long *)0xFE200014
+#define SH7751_PCICONF6 (vu_long *)0xFE200018
+#define SH7751_PCICR (vu_long *)0xFE200100
+#define SH7751_PCILSR0 (vu_long *)0xFE200104
+#define SH7751_PCILSR1 (vu_long *)0xFE200108
+#define SH7751_PCILAR0 (vu_long *)0xFE20010C
+#define SH7751_PCILAR1 (vu_long *)0xFE200110
+#define SH7751_PCIMBR (vu_long *)0xFE2001C4
+#define SH7751_PCIIOBR (vu_long *)0xFE2001C8
+#define SH7751_PCIPINT (vu_long *)0xFE2001CC
+#define SH7751_PCIPINTM (vu_long *)0xFE2001D0
+#define SH7751_PCICLKR (vu_long *)0xFE2001D4
+#define SH7751_PCIBCR1 (vu_long *)0xFE2001E0
+#define SH7751_PCIBCR2 (vu_long *)0xFE2001E4
+#define SH7751_PCIWCR1 (vu_long *)0xFE2001E8
+#define SH7751_PCIWCR2 (vu_long *)0xFE2001EC
+#define SH7751_PCIWCR3 (vu_long *)0xFE2001F0
+#define SH7751_PCIMCR (vu_long *)0xFE2001F4
+#define SH7751_PCIBCR3 (vu_long *)0xFE2001F8
-#define BCR1_BREQEN 0x00080000
-#define PCI_SH7751_ID 0x35051054
-#define PCI_SH7751R_ID 0x350E1054
-#define SH7751_PCICONF1_WCC 0x00000080
-#define SH7751_PCICONF1_PER 0x00000040
-#define SH7751_PCICONF1_BUM 0x00000004
-#define SH7751_PCICONF1_MES 0x00000002
+#define BCR1_BREQEN 0x00080000
+#define PCI_SH7751_ID 0x35051054
+#define PCI_SH7751R_ID 0x350E1054
+#define SH7751_PCICONF1_WCC 0x00000080
+#define SH7751_PCICONF1_PER 0x00000040
+#define SH7751_PCICONF1_BUM 0x00000004
+#define SH7751_PCICONF1_MES 0x00000002
#define SH7751_PCICONF1_CMDS 0x000000C6
#define SH7751_PCI_HOST_BRIDGE 0x6
-#define SH7751_PCICR_PREFIX 0xa5000000
-#define SH7751_PCICR_PRST 0x00000002
-#define SH7751_PCICR_CFIN 0x00000001
-#define SH7751_PCIPINT_D3 0x00000002
-#define SH7751_PCIPINT_D0 0x00000001
-#define SH7751_PCICLKR_PREFIX 0xa5000000
+#define SH7751_PCICR_PREFIX 0xa5000000
+#define SH7751_PCICR_PRST 0x00000002
+#define SH7751_PCICR_CFIN 0x00000001
+#define SH7751_PCIPINT_D3 0x00000002
+#define SH7751_PCIPINT_D0 0x00000001
+#define SH7751_PCICLKR_PREFIX 0xa5000000
-#define SH7751_PCI_MEM_BASE 0xFD000000
-#define SH7751_PCI_MEM_SIZE 0x01000000
-#define SH7751_PCI_IO_BASE 0xFE240000
-#define SH7751_PCI_IO_SIZE 0x00040000
+#define SH7751_PCI_MEM_BASE 0xFD000000
+#define SH7751_PCI_MEM_SIZE 0x01000000
+#define SH7751_PCI_IO_BASE 0xFE240000
+#define SH7751_PCI_IO_SIZE 0x00040000
-#define SH7751_PCIPAR (vu_long *)0xFE2001C0
-#define SH7751_PCIPDR (vu_long *)0xFE200220
+#define SH7751_PCIPAR (vu_long *)0xFE2001C0
+#define SH7751_PCIPDR (vu_long *)0xFE200220
#define p4_in(addr) (*addr)
#define p4_out(data, addr) (*addr) = (data)
-/* Double word */
-int pci_sh4_read_config_dword(struct pci_controller *hose,
- pci_dev_t dev, int offset, u32 *value)
+static int sh7751_pci_addr_valid(pci_dev_t d, uint offset)
{
- u32 par_data = 0x80000000 | dev;
-
- p4_out(par_data | (offset & 0xfc), SH7751_PCIPAR);
- *value = p4_in(SH7751_PCIPDR);
+ if (PCI_FUNC(d))
+ return -EINVAL;
return 0;
}
-int pci_sh4_write_config_dword(struct pci_controller *hose,
- pci_dev_t dev, int offset, u32 value)
+static u32 get_bus_address(struct udevice *dev, pci_dev_t bdf, u32 offset)
{
- u32 par_data = 0x80000000 | dev;
+ return BIT(31) | (PCI_DEV(bdf) << 8) | (offset & ~3);
+}
- p4_out(par_data | (offset & 0xfc), SH7751_PCIPAR);
- p4_out(value, SH7751_PCIPDR);
+static int sh7751_pci_read_config(struct udevice *dev, pci_dev_t bdf,
+ uint offset, ulong *value,
+ enum pci_size_t size)
+{
+ u32 addr, reg;
+ int ret;
+
+ ret = sh7751_pci_addr_valid(bdf, offset);
+ if (ret) {
+ *value = pci_get_ff(size);
+ return 0;
+ }
+
+ addr = get_bus_address(dev, bdf, offset);
+ p4_out(addr, SH7751_PCIPAR);
+ reg = p4_in(SH7751_PCIPDR);
+ *value = pci_conv_32_to_size(reg, offset, size);
return 0;
}
-int pci_sh7751_init(struct pci_controller *hose)
+static int sh7751_pci_write_config(struct udevice *dev, pci_dev_t bdf,
+ uint offset, ulong value,
+ enum pci_size_t size)
+{
+ u32 addr, reg, old;
+ int ret;
+
+ ret = sh7751_pci_addr_valid(bdf, offset);
+ if (ret)
+ return ret;
+
+ addr = get_bus_address(dev, bdf, offset);
+ p4_out(addr, SH7751_PCIPAR);
+ old = p4_in(SH7751_PCIPDR);
+ reg = pci_conv_size_to_32(old, value, offset, size);
+ p4_out(reg, SH7751_PCIPDR);
+
+ return 0;
+}
+
+static int sh7751_pci_probe(struct udevice *dev)
{
/* Double-check that we're a 7751 or 7751R chip */
if (p4_in(SH7751_PCICONF0) != PCI_SH7751_ID
@@ -178,7 +210,23 @@
/* Finally, set central function init complete */
p4_out((SH7751_PCICR_PREFIX | SH7751_PCICR_CFIN), SH7751_PCICR);
- pci_sh4_init(hose);
-
return 0;
}
+
+static const struct dm_pci_ops sh7751_pci_ops = {
+ .read_config = sh7751_pci_read_config,
+ .write_config = sh7751_pci_write_config,
+};
+
+static const struct udevice_id sh7751_pci_ids[] = {
+ { .compatible = "renesas,pci-sh7751" },
+ { }
+};
+
+U_BOOT_DRIVER(sh7751_pci) = {
+ .name = "sh7751_pci",
+ .id = UCLASS_PCI,
+ .of_match = sh7751_pci_ids,
+ .ops = &sh7751_pci_ops,
+ .probe = sh7751_pci_probe,
+};
diff --git a/drivers/pci/pcie_dw_ti.c b/drivers/pci/pcie_dw_ti.c
new file mode 100644
index 0000000..b37fc2d
--- /dev/null
+++ b/drivers/pci/pcie_dw_ti.c
@@ -0,0 +1,725 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Texas Instruments, Inc
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <pci.h>
+#include <generic-phy.h>
+#include <power-domain.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm-generic/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PCIE_VENDORID_MASK GENMASK(15, 0)
+#define PCIE_DEVICEID_SHIFT 16
+
+/* PCI DBICS registers */
+#define PCIE_CONFIG_BAR0 0x10
+#define PCIE_LINK_STATUS_REG 0x80
+#define PCIE_LINK_STATUS_SPEED_OFF 16
+#define PCIE_LINK_STATUS_SPEED_MASK (0xf << PCIE_LINK_STATUS_SPEED_OFF)
+#define PCIE_LINK_STATUS_WIDTH_OFF 20
+#define PCIE_LINK_STATUS_WIDTH_MASK (0xf << PCIE_LINK_STATUS_WIDTH_OFF)
+
+#define PCIE_LINK_CAPABILITY 0x7c
+#define PCIE_LINK_CTL_2 0xa0
+#define TARGET_LINK_SPEED_MASK 0xf
+#define LINK_SPEED_GEN_1 0x1
+#define LINK_SPEED_GEN_2 0x2
+#define LINK_SPEED_GEN_3 0x3
+
+#define PCIE_MISC_CONTROL_1_OFF 0x8bc
+#define PCIE_DBI_RO_WR_EN BIT(0)
+
+#define PLR_OFFSET 0x700
+#define PCIE_PORT_DEBUG0 (PLR_OFFSET + 0x28)
+#define PORT_LOGIC_LTSSM_STATE_MASK 0x1f
+#define PORT_LOGIC_LTSSM_STATE_L0 0x11
+
+#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80c
+#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
+
+#define PCIE_LINK_UP_TIMEOUT_MS 100
+
+/*
+ * iATU Unroll-specific register definitions
+ * From 4.80 core version the address translation will be made by unroll.
+ * The registers are offset from atu_base
+ */
+#define PCIE_ATU_UNR_REGION_CTRL1 0x00
+#define PCIE_ATU_UNR_REGION_CTRL2 0x04
+#define PCIE_ATU_UNR_LOWER_BASE 0x08
+#define PCIE_ATU_UNR_UPPER_BASE 0x0c
+#define PCIE_ATU_UNR_LIMIT 0x10
+#define PCIE_ATU_UNR_LOWER_TARGET 0x14
+#define PCIE_ATU_UNR_UPPER_TARGET 0x18
+
+#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
+#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
+#define PCIE_ATU_TYPE_MEM (0x0 << 0)
+#define PCIE_ATU_TYPE_IO (0x2 << 0)
+#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
+#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
+#define PCIE_ATU_ENABLE (0x1 << 31)
+#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
+#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
+#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
+#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
+
+/* Register address builder */
+#define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) ((region) << 9)
+
+/* Offsets from App base */
+#define PCIE_CMD_STATUS 0x04
+#define LTSSM_EN_VAL BIT(0)
+
+/* Parameters for the waiting for iATU enabled routine */
+#define LINK_WAIT_MAX_IATU_RETRIES 5
+#define LINK_WAIT_IATU 10000
+
+#define AM654_PCIE_DEV_TYPE_MASK 0x3
+#define EP 0x0
+#define LEG_EP 0x1
+#define RC 0x2
+
+/**
+ * struct pcie_dw_ti - TI DW PCIe controller state
+ *
+ * @app_base: The base address of application register space
+ * @dbics_base: The base address of dbics register space
+ * @cfg_base: The base address of configuration space
+ * @atu_base: The base address of ATU space
+ * @cfg_size: The size of the configuration space which is needed
+ * as it gets written into the PCIE_ATU_LIMIT register
+ * @first_busno: This driver supports multiple PCIe controllers.
+ * first_busno stores the bus number of the PCIe root-port
+ * number which may vary depending on the PCIe setup
+ * (PEX switches etc).
+ */
+struct pcie_dw_ti {
+ void *app_base;
+ void *dbi_base;
+ void *cfg_base;
+ void *atu_base;
+ fdt_size_t cfg_size;
+ int first_busno;
+ struct udevice *dev;
+
+ /* IO and MEM PCI regions */
+ struct pci_region io;
+ struct pci_region mem;
+};
+
+enum dw_pcie_device_mode {
+ DW_PCIE_UNKNOWN_TYPE,
+ DW_PCIE_EP_TYPE,
+ DW_PCIE_LEG_EP_TYPE,
+ DW_PCIE_RC_TYPE,
+};
+
+static int pcie_dw_get_link_speed(struct pcie_dw_ti *pci)
+{
+ return (readl(pci->dbi_base + PCIE_LINK_STATUS_REG) &
+ PCIE_LINK_STATUS_SPEED_MASK) >> PCIE_LINK_STATUS_SPEED_OFF;
+}
+
+static int pcie_dw_get_link_width(struct pcie_dw_ti *pci)
+{
+ return (readl(pci->dbi_base + PCIE_LINK_STATUS_REG) &
+ PCIE_LINK_STATUS_WIDTH_MASK) >> PCIE_LINK_STATUS_WIDTH_OFF;
+}
+
+static void dw_pcie_writel_ob_unroll(struct pcie_dw_ti *pci, u32 index, u32 reg,
+ u32 val)
+{
+ u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
+ void __iomem *base = pci->atu_base;
+
+ writel(val, base + offset + reg);
+}
+
+static u32 dw_pcie_readl_ob_unroll(struct pcie_dw_ti *pci, u32 index, u32 reg)
+{
+ u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
+ void __iomem *base = pci->atu_base;
+
+ return readl(base + offset + reg);
+}
+
+/**
+ * pcie_dw_prog_outbound_atu_unroll() - Configure ATU for outbound accesses
+ *
+ * @pcie: Pointer to the PCI controller state
+ * @index: ATU region index
+ * @type: ATU accsess type
+ * @cpu_addr: the physical address for the translation entry
+ * @pci_addr: the pcie bus address for the translation entry
+ * @size: the size of the translation entry
+ */
+static void pcie_dw_prog_outbound_atu_unroll(struct pcie_dw_ti *pci, int index,
+ int type, u64 cpu_addr,
+ u64 pci_addr, u32 size)
+{
+ u32 retries, val;
+
+ debug("ATU programmed with: index: %d, type: %d, cpu addr: %8llx, pci addr: %8llx, size: %8x\n",
+ index, type, cpu_addr, pci_addr, size);
+
+ dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE,
+ lower_32_bits(cpu_addr));
+ dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE,
+ upper_32_bits(cpu_addr));
+ dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LIMIT,
+ lower_32_bits(cpu_addr + size - 1));
+ dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
+ lower_32_bits(pci_addr));
+ dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
+ upper_32_bits(pci_addr));
+ dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1,
+ type);
+ dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
+ PCIE_ATU_ENABLE);
+
+ /*
+ * Make sure ATU enable takes effect before any subsequent config
+ * and I/O accesses.
+ */
+ for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
+ val = dw_pcie_readl_ob_unroll(pci, index,
+ PCIE_ATU_UNR_REGION_CTRL2);
+ if (val & PCIE_ATU_ENABLE)
+ return;
+
+ udelay(LINK_WAIT_IATU);
+ }
+ dev_err(pci->dev, "outbound iATU is not being enabled\n");
+}
+
+/**
+ * set_cfg_address() - Configure the PCIe controller config space access
+ *
+ * @pcie: Pointer to the PCI controller state
+ * @d: PCI device to access
+ * @where: Offset in the configuration space
+ *
+ * Configures the PCIe controller to access the configuration space of
+ * a specific PCIe device and returns the address to use for this
+ * access.
+ *
+ * Return: Address that can be used to access the configation space
+ * of the requested device / offset
+ */
+static uintptr_t set_cfg_address(struct pcie_dw_ti *pcie,
+ pci_dev_t d, uint where)
+{
+ int bus = PCI_BUS(d) - pcie->first_busno;
+ uintptr_t va_address;
+ u32 atu_type;
+
+ /* Use dbi_base for own configuration read and write */
+ if (!bus) {
+ va_address = (uintptr_t)pcie->dbi_base;
+ goto out;
+ }
+
+ if (bus == 1)
+ /* For local bus, change TLP Type field to 4. */
+ atu_type = PCIE_ATU_TYPE_CFG0;
+ else
+ /* Otherwise, change TLP Type field to 5. */
+ atu_type = PCIE_ATU_TYPE_CFG1;
+
+ /*
+ * Not accessing root port configuration space?
+ * Region #0 is used for Outbound CFG space access.
+ * Direction = Outbound
+ * Region Index = 0
+ */
+ d = PCI_MASK_BUS(d);
+ d = PCI_ADD_BUS(bus, d);
+ pcie_dw_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1,
+ atu_type, (u64)pcie->cfg_base,
+ d << 8, pcie->cfg_size);
+
+ va_address = (uintptr_t)pcie->cfg_base;
+
+out:
+ va_address += where & ~0x3;
+
+ return va_address;
+}
+
+/**
+ * pcie_dw_addr_valid() - Check for valid bus address
+ *
+ * @d: The PCI device to access
+ * @first_busno: Bus number of the PCIe controller root complex
+ *
+ * Return 1 (true) if the PCI device can be accessed by this controller.
+ *
+ * Return: 1 on valid, 0 on invalid
+ */
+static int pcie_dw_addr_valid(pci_dev_t d, int first_busno)
+{
+ if ((PCI_BUS(d) == first_busno) && (PCI_DEV(d) > 0))
+ return 0;
+ if ((PCI_BUS(d) == first_busno + 1) && (PCI_DEV(d) > 0))
+ return 0;
+
+ return 1;
+}
+
+/**
+ * pcie_dw_ti_read_config() - Read from configuration space
+ *
+ * @bus: Pointer to the PCI bus
+ * @bdf: Identifies the PCIe device to access
+ * @offset: The offset into the device's configuration space
+ * @valuep: A pointer at which to store the read value
+ * @size: Indicates the size of access to perform
+ *
+ * Read a value of size @size from offset @offset within the configuration
+ * space of the device identified by the bus, device & function numbers in @bdf
+ * on the PCI bus @bus.
+ *
+ * Return: 0 on success
+ */
+static int pcie_dw_ti_read_config(struct udevice *bus, pci_dev_t bdf,
+ uint offset, ulong *valuep,
+ enum pci_size_t size)
+{
+ struct pcie_dw_ti *pcie = dev_get_priv(bus);
+ uintptr_t va_address;
+ ulong value;
+
+ debug("PCIE CFG read: bdf=%2x:%2x:%2x ",
+ PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
+
+ if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) {
+ debug("- out of range\n");
+ *valuep = pci_get_ff(size);
+ return 0;
+ }
+
+ va_address = set_cfg_address(pcie, bdf, offset);
+
+ value = readl(va_address);
+
+ debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
+ *valuep = pci_conv_32_to_size(value, offset, size);
+
+ pcie_dw_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1,
+ PCIE_ATU_TYPE_IO, pcie->io.phys_start,
+ pcie->io.bus_start, pcie->io.size);
+
+ return 0;
+}
+
+/**
+ * pcie_dw_ti_write_config() - Write to configuration space
+ *
+ * @bus: Pointer to the PCI bus
+ * @bdf: Identifies the PCIe device to access
+ * @offset: The offset into the device's configuration space
+ * @value: The value to write
+ * @size: Indicates the size of access to perform
+ *
+ * Write the value @value of size @size from offset @offset within the
+ * configuration space of the device identified by the bus, device & function
+ * numbers in @bdf on the PCI bus @bus.
+ *
+ * Return: 0 on success
+ */
+static int pcie_dw_ti_write_config(struct udevice *bus, pci_dev_t bdf,
+ uint offset, ulong value,
+ enum pci_size_t size)
+{
+ struct pcie_dw_ti *pcie = dev_get_priv(bus);
+ uintptr_t va_address;
+ ulong old;
+
+ debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
+ PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
+ debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
+
+ if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) {
+ debug("- out of range\n");
+ return 0;
+ }
+
+ va_address = set_cfg_address(pcie, bdf, offset);
+
+ old = readl(va_address);
+ value = pci_conv_size_to_32(old, value, offset, size);
+ writel(value, va_address);
+
+ pcie_dw_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1,
+ PCIE_ATU_TYPE_IO, pcie->io.phys_start,
+ pcie->io.bus_start, pcie->io.size);
+
+ return 0;
+}
+
+static inline void dw_pcie_dbi_write_enable(struct pcie_dw_ti *pci, bool en)
+{
+ u32 val;
+
+ val = readl(pci->dbi_base + PCIE_MISC_CONTROL_1_OFF);
+ if (en)
+ val |= PCIE_DBI_RO_WR_EN;
+ else
+ val &= ~PCIE_DBI_RO_WR_EN;
+ writel(val, pci->dbi_base + PCIE_MISC_CONTROL_1_OFF);
+}
+
+/**
+ * pcie_dw_configure() - Configure link capabilities and speed
+ *
+ * @regs_base: A pointer to the PCIe controller registers
+ * @cap_speed: The capabilities and speed to configure
+ *
+ * Configure the link capabilities and speed in the PCIe root complex.
+ */
+static void pcie_dw_configure(struct pcie_dw_ti *pci, u32 cap_speed)
+{
+ u32 val;
+
+ dw_pcie_dbi_write_enable(pci, true);
+
+ val = readl(pci->dbi_base + PCIE_LINK_CAPABILITY);
+ val &= ~TARGET_LINK_SPEED_MASK;
+ val |= cap_speed;
+ writel(val, pci->dbi_base + PCIE_LINK_CAPABILITY);
+
+ val = readl(pci->dbi_base + PCIE_LINK_CTL_2);
+ val &= ~TARGET_LINK_SPEED_MASK;
+ val |= cap_speed;
+ writel(val, pci->dbi_base + PCIE_LINK_CTL_2);
+
+ dw_pcie_dbi_write_enable(pci, false);
+}
+
+/**
+ * is_link_up() - Return the link state
+ *
+ * @regs_base: A pointer to the PCIe DBICS registers
+ *
+ * Return: 1 (true) for active line and 0 (false) for no link
+ */
+static int is_link_up(struct pcie_dw_ti *pci)
+{
+ u32 val;
+
+ val = readl(pci->dbi_base + PCIE_PORT_DEBUG0);
+ val &= PORT_LOGIC_LTSSM_STATE_MASK;
+
+ return (val == PORT_LOGIC_LTSSM_STATE_L0);
+}
+
+/**
+ * wait_link_up() - Wait for the link to come up
+ *
+ * @regs_base: A pointer to the PCIe controller registers
+ *
+ * Return: 1 (true) for active line and 0 (false) for no link (timeout)
+ */
+static int wait_link_up(struct pcie_dw_ti *pci)
+{
+ unsigned long timeout;
+
+ timeout = get_timer(0) + PCIE_LINK_UP_TIMEOUT_MS;
+ while (!is_link_up(pci)) {
+ if (get_timer(0) > timeout)
+ return 0;
+ };
+
+ return 1;
+}
+
+static int pcie_dw_ti_pcie_link_up(struct pcie_dw_ti *pci, u32 cap_speed)
+{
+ u32 val;
+
+ if (is_link_up(pci)) {
+ printf("PCI Link already up before configuration!\n");
+ return 1;
+ }
+
+ /* DW pre link configurations */
+ pcie_dw_configure(pci, cap_speed);
+
+ /* Initiate link training */
+ val = readl(pci->app_base + PCIE_CMD_STATUS);
+ val |= LTSSM_EN_VAL;
+ writel(val, pci->app_base + PCIE_CMD_STATUS);
+
+ /* Check that link was established */
+ if (!wait_link_up(pci))
+ return 0;
+
+ /*
+ * Link can be established in Gen 1. still need to wait
+ * till MAC nagaotiation is completed
+ */
+ udelay(100);
+
+ return 1;
+}
+
+/**
+ * pcie_dw_setup_host() - Setup the PCIe controller for RC opertaion
+ *
+ * @pcie: Pointer to the PCI controller state
+ *
+ * Configure the host BARs of the PCIe controller root port so that
+ * PCI(e) devices may access the system memory.
+ */
+static void pcie_dw_setup_host(struct pcie_dw_ti *pci)
+{
+ u32 val;
+
+ /* setup RC BARs */
+ writel(PCI_BASE_ADDRESS_MEM_TYPE_64,
+ pci->dbi_base + PCI_BASE_ADDRESS_0);
+ writel(0x0, pci->dbi_base + PCI_BASE_ADDRESS_1);
+
+ /* setup interrupt pins */
+ dw_pcie_dbi_write_enable(pci, true);
+ val = readl(pci->dbi_base + PCI_INTERRUPT_LINE);
+ val &= 0xffff00ff;
+ val |= 0x00000100;
+ writel(val, pci->dbi_base + PCI_INTERRUPT_LINE);
+ dw_pcie_dbi_write_enable(pci, false);
+
+ /* setup bus numbers */
+ val = readl(pci->dbi_base + PCI_PRIMARY_BUS);
+ val &= 0xff000000;
+ val |= 0x00ff0100;
+ writel(val, pci->dbi_base + PCI_PRIMARY_BUS);
+
+ /* setup command register */
+ val = readl(pci->dbi_base + PCI_COMMAND);
+ val &= 0xffff0000;
+ val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
+ PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
+ writel(val, pci->dbi_base + PCI_COMMAND);
+
+ /* Enable write permission for the DBI read-only register */
+ dw_pcie_dbi_write_enable(pci, true);
+ /* program correct class for RC */
+ writew(PCI_CLASS_BRIDGE_PCI, pci->dbi_base + PCI_CLASS_DEVICE);
+ /* Better disable write permission right after the update */
+ dw_pcie_dbi_write_enable(pci, false);
+
+ val = readl(pci->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
+ val |= PORT_LOGIC_SPEED_CHANGE;
+ writel(val, pci->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
+}
+
+static int pcie_am654_set_mode(struct pcie_dw_ti *pci,
+ enum dw_pcie_device_mode mode)
+{
+ struct regmap *syscon;
+ u32 val;
+ u32 mask;
+ int ret;
+
+ syscon = syscon_regmap_lookup_by_phandle(pci->dev,
+ "ti,syscon-pcie-mode");
+ if (IS_ERR(syscon))
+ return 0;
+
+ mask = AM654_PCIE_DEV_TYPE_MASK;
+
+ switch (mode) {
+ case DW_PCIE_RC_TYPE:
+ val = RC;
+ break;
+ case DW_PCIE_EP_TYPE:
+ val = EP;
+ break;
+ default:
+ dev_err(pci->dev, "INVALID device type %d\n", mode);
+ return -EINVAL;
+ }
+
+ ret = regmap_update_bits(syscon, 0, mask, val);
+ if (ret) {
+ dev_err(pci->dev, "failed to set pcie mode\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int pcie_dw_init_id(struct pcie_dw_ti *pci)
+{
+ struct regmap *devctrl_regs;
+ unsigned int id;
+ int ret;
+
+ devctrl_regs = syscon_regmap_lookup_by_phandle(pci->dev,
+ "ti,syscon-pcie-id");
+ if (IS_ERR(devctrl_regs))
+ return PTR_ERR(devctrl_regs);
+
+ ret = regmap_read(devctrl_regs, 0, &id);
+ if (ret)
+ return ret;
+
+ dw_pcie_dbi_write_enable(pci, true);
+ writew(id & PCIE_VENDORID_MASK, pci->dbi_base + PCI_VENDOR_ID);
+ writew(id >> PCIE_DEVICEID_SHIFT, pci->dbi_base + PCI_DEVICE_ID);
+ dw_pcie_dbi_write_enable(pci, false);
+
+ return 0;
+}
+
+/**
+ * pcie_dw_ti_probe() - Probe the PCIe bus for active link
+ *
+ * @dev: A pointer to the device being operated on
+ *
+ * Probe for an active link on the PCIe bus and configure the controller
+ * to enable this port.
+ *
+ * Return: 0 on success, else -ENODEV
+ */
+static int pcie_dw_ti_probe(struct udevice *dev)
+{
+ struct pcie_dw_ti *pci = dev_get_priv(dev);
+ struct udevice *ctlr = pci_get_controller(dev);
+ struct pci_controller *hose = dev_get_uclass_priv(ctlr);
+ struct power_domain pci_pwrdmn;
+ struct phy phy0, phy1;
+ int ret;
+
+ ret = power_domain_get_by_index(dev, &pci_pwrdmn, 0);
+ if (ret) {
+ dev_err(dev, "failed to get power domain\n");
+ return ret;
+ }
+
+ ret = power_domain_on(&pci_pwrdmn);
+ if (ret) {
+ dev_err(dev, "Power domain on failed\n");
+ return ret;
+ }
+
+ ret = generic_phy_get_by_name(dev, "pcie-phy0", &phy0);
+ if (ret) {
+ dev_err(dev, "Unable to get phy0");
+ return ret;
+ }
+ generic_phy_reset(&phy0);
+ generic_phy_init(&phy0);
+ generic_phy_power_on(&phy0);
+
+ ret = generic_phy_get_by_name(dev, "pcie-phy1", &phy1);
+ if (ret) {
+ dev_err(dev, "Unable to get phy1");
+ return ret;
+ }
+ generic_phy_reset(&phy1);
+ generic_phy_init(&phy1);
+ generic_phy_power_on(&phy1);
+
+ pci->first_busno = dev->seq;
+ pci->dev = dev;
+
+ pcie_dw_setup_host(pci);
+ pcie_dw_init_id(pci);
+
+ if (device_is_compatible(dev, "ti,am654-pcie-rc"))
+ pcie_am654_set_mode(pci, DW_PCIE_RC_TYPE);
+
+ if (!pcie_dw_ti_pcie_link_up(pci, LINK_SPEED_GEN_2)) {
+ printf("PCIE-%d: Link down\n", dev->seq);
+ return -ENODEV;
+ }
+
+ printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", dev->seq,
+ pcie_dw_get_link_speed(pci),
+ pcie_dw_get_link_width(pci),
+ hose->first_busno);
+
+ /* Store the IO and MEM windows settings for future use by the ATU */
+ pci->io.phys_start = hose->regions[0].phys_start; /* IO base */
+ pci->io.bus_start = hose->regions[0].bus_start; /* IO_bus_addr */
+ pci->io.size = hose->regions[0].size; /* IO size */
+
+ pci->mem.phys_start = hose->regions[1].phys_start; /* MEM base */
+ pci->mem.bus_start = hose->regions[1].bus_start; /* MEM_bus_addr */
+ pci->mem.size = hose->regions[1].size; /* MEM size */
+
+ pcie_dw_prog_outbound_atu_unroll(pci, PCIE_ATU_REGION_INDEX0,
+ PCIE_ATU_TYPE_MEM,
+ pci->mem.phys_start,
+ pci->mem.bus_start, pci->mem.size);
+
+ return 0;
+}
+
+/**
+ * pcie_dw_ti_ofdata_to_platdata() - Translate from DT to device state
+ *
+ * @dev: A pointer to the device being operated on
+ *
+ * Translate relevant data from the device tree pertaining to device @dev into
+ * state that the driver will later make use of. This state is stored in the
+ * device's private data structure.
+ *
+ * Return: 0 on success, else -EINVAL
+ */
+static int pcie_dw_ti_ofdata_to_platdata(struct udevice *dev)
+{
+ struct pcie_dw_ti *pcie = dev_get_priv(dev);
+
+ /* Get the controller base address */
+ pcie->dbi_base = (void *)dev_read_addr_name(dev, "dbics");
+ if ((fdt_addr_t)pcie->dbi_base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ /* Get the config space base address and size */
+ pcie->cfg_base = (void *)dev_read_addr_size_name(dev, "config",
+ &pcie->cfg_size);
+ if ((fdt_addr_t)pcie->cfg_base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ /* Get the iATU base address and size */
+ pcie->atu_base = (void *)dev_read_addr_name(dev, "atu");
+ if ((fdt_addr_t)pcie->atu_base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ /* Get the app base address and size */
+ pcie->app_base = (void *)dev_read_addr_name(dev, "app");
+ if ((fdt_addr_t)pcie->app_base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct dm_pci_ops pcie_dw_ti_ops = {
+ .read_config = pcie_dw_ti_read_config,
+ .write_config = pcie_dw_ti_write_config,
+};
+
+static const struct udevice_id pcie_dw_ti_ids[] = {
+ { .compatible = "ti,am654-pcie-rc" },
+ { }
+};
+
+U_BOOT_DRIVER(pcie_dw_ti) = {
+ .name = "pcie_dw_ti",
+ .id = UCLASS_PCI,
+ .of_match = pcie_dw_ti_ids,
+ .ops = &pcie_dw_ti_ops,
+ .ofdata_to_platdata = pcie_dw_ti_ofdata_to_platdata,
+ .probe = pcie_dw_ti_probe,
+ .priv_auto_alloc_size = sizeof(struct pcie_dw_ti),
+};
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index 4d61a46..ab25aee 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -299,8 +299,9 @@
out_be32(&pi->piwbear, 0);
#endif
- if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A005434))
- flag = 0;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005434
+ flag = 0;
+#endif
flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
if (pf)
@@ -401,47 +402,47 @@
fsl_pcie_init_atmu(pcie);
- if (IS_ENABLED(CONFIG_FSL_PCIE_DISABLE_ASPM)) {
- val_32 = 0;
- fsl_pcie_hose_read_config_dword(pcie, PCI_LCR, &val_32);
- val_32 &= ~0x03;
- fsl_pcie_hose_write_config_dword(pcie, PCI_LCR, val_32);
- udelay(1);
- }
+#ifdef CONFIG_FSL_PCIE_DISABLE_ASPM
+ val_32 = 0;
+ fsl_pcie_hose_read_config_dword(pcie, PCI_LCR, &val_32);
+ val_32 &= ~0x03;
+ fsl_pcie_hose_write_config_dword(pcie, PCI_LCR, val_32);
+ udelay(1);
+#endif
- if (IS_ENABLED(CONFIG_FSL_PCIE_RESET)) {
- u16 ltssm;
- int i;
+#ifdef CONFIG_FSL_PCIE_RESET
+ u16 ltssm;
+ int i;
- if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
+ if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
+ /* assert PCIe reset */
+ setbits_be32(®s->pdb_stat, 0x08000000);
+ (void)in_be32(®s->pdb_stat);
+ udelay(1000);
+ /* clear PCIe reset */
+ clrbits_be32(®s->pdb_stat, 0x08000000);
+ asm("sync;isync");
+ for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)
+ udelay(1000);
+ } else {
+ fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, <ssm);
+ if (ltssm == 1) {
/* assert PCIe reset */
setbits_be32(®s->pdb_stat, 0x08000000);
(void)in_be32(®s->pdb_stat);
- udelay(1000);
+ udelay(100);
/* clear PCIe reset */
clrbits_be32(®s->pdb_stat, 0x08000000);
asm("sync;isync");
- for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)
+ for (i = 0; i < 100 &&
+ !fsl_pcie_link_up(pcie); i++)
udelay(1000);
- } else {
- fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, <ssm);
- if (ltssm == 1) {
- /* assert PCIe reset */
- setbits_be32(®s->pdb_stat, 0x08000000);
- (void)in_be32(®s->pdb_stat);
- udelay(100);
- /* clear PCIe reset */
- clrbits_be32(®s->pdb_stat, 0x08000000);
- asm("sync;isync");
- for (i = 0; i < 100 &&
- !fsl_pcie_link_up(pcie); i++)
- udelay(1000);
- }
}
}
+#endif
- if (IS_ENABLED(CONFIG_SYS_P4080_ERRATUM_PCIE_A003) &&
- !fsl_pcie_link_up(pcie)) {
+#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
+ if (!fsl_pcie_link_up(pcie)) {
serdes_corenet_t *srds_regs;
srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
@@ -460,13 +461,15 @@
udelay(1000);
}
}
+#endif
/*
* The Read-Only Write Enable bit defaults to 1 instead of 0.
* Set to 0 to protect the read-only registers.
*/
- if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A007815))
- clrbits_be32(®s->dbi_ro_wr_en, 0x01);
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007815
+ clrbits_be32(®s->dbi_ro_wr_en, 0x01);
+#endif
/*
* Enable All Error Interrupts except
@@ -500,14 +503,23 @@
static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie)
{
ccsr_fsl_pci_t *regs = pcie->regs;
+ u32 classcode_reg;
u32 val;
- setbits_be32(®s->dbi_ro_wr_en, 0x01);
- fsl_pcie_hose_read_config_dword(pcie, PCI_CLASS_REVISION, &val);
+ if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
+ classcode_reg = PCI_CLASS_REVISION;
+ setbits_be32(®s->dbi_ro_wr_en, 0x01);
+ } else {
+ classcode_reg = CSR_CLASSCODE;
+ }
+
+ fsl_pcie_hose_read_config_dword(pcie, classcode_reg, &val);
val &= 0xff;
val |= PCI_CLASS_BRIDGE_PCI << 16;
- fsl_pcie_hose_write_config_dword(pcie, PCI_CLASS_REVISION, val);
- clrbits_be32(®s->dbi_ro_wr_en, 0x01);
+ fsl_pcie_hose_write_config_dword(pcie, classcode_reg, val);
+
+ if (pcie->block_rev >= PEX_IP_BLK_REV_3_0)
+ clrbits_be32(®s->dbi_ro_wr_en, 0x01);
return 0;
}
@@ -570,6 +582,7 @@
static int fsl_pcie_ofdata_to_platdata(struct udevice *dev)
{
struct fsl_pcie *pcie = dev_get_priv(dev);
+ struct fsl_pcie_data *info;
int ret;
pcie->regs = dev_remap_addr(dev);
@@ -584,7 +597,10 @@
return ret;
}
- pcie->idx = (dev_read_addr(dev) - 0xffe240000) / 0x10000;
+ info = (struct fsl_pcie_data *)dev_get_driver_data(dev);
+ pcie->info = info;
+ pcie->idx = abs((u32)(dev_read_addr(dev) & info->block_offset_mask) -
+ info->block_offset) / info->stride;
return 0;
}
@@ -594,8 +610,35 @@
.write_config = fsl_pcie_write_config,
};
+static struct fsl_pcie_data p1_p2_data = {
+ .block_offset = 0xa000,
+ .block_offset_mask = 0xffff,
+ .stride = 0x1000,
+};
+
+static struct fsl_pcie_data p2041_data = {
+ .block_offset = 0x200000,
+ .block_offset_mask = 0x3fffff,
+ .stride = 0x1000,
+};
+
+static struct fsl_pcie_data t2080_data = {
+ .block_offset = 0x240000,
+ .block_offset_mask = 0x3fffff,
+ .stride = 0x10000,
+};
+
static const struct udevice_id fsl_pcie_ids[] = {
- { .compatible = "fsl,pcie-t2080" },
+ { .compatible = "fsl,pcie-mpc8548", .data = (ulong)&p1_p2_data },
+ { .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data },
+ { .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data },
+ { .compatible = "fsl,pcie-p3041", .data = (ulong)&p2041_data },
+ { .compatible = "fsl,pcie-p4080", .data = (ulong)&p2041_data },
+ { .compatible = "fsl,pcie-p5040", .data = (ulong)&p2041_data },
+ { .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data },
+ { .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data },
+ { .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data },
+ { .compatible = "fsl,pcie-t4240", .data = (ulong)&t2080_data },
{ }
};
diff --git a/drivers/pci/pcie_fsl.h b/drivers/pci/pcie_fsl.h
index 5eefc31..dc8368d 100644
--- a/drivers/pci/pcie_fsl.h
+++ b/drivers/pci/pcie_fsl.h
@@ -9,6 +9,9 @@
#ifndef _PCIE_FSL_H_
#define _PCIE_FSL_H_
+/* GPEX CSR */
+#define CSR_CLASSCODE 0x474
+
#ifdef CONFIG_SYS_FSL_PCI_VER_3_X
#define FSL_PCIE_CAP_ID 0x70
#else
@@ -40,6 +43,12 @@
#define LTSSM_L0_REV3 0x11
#define LTSSM_L0 0x16
+struct fsl_pcie_data {
+ u32 block_offset; /* Offset from CCSR of 1st controller */
+ u32 block_offset_mask; /* Mask out the CCSR base */
+ u32 stride; /* Offset stride between controllers */
+};
+
struct fsl_pcie {
int idx;
struct udevice *bus;
@@ -49,6 +58,7 @@
bool mode; /* RC&EP mode flag */
bool enabled; /* Enable status */
struct list_head list;
+ struct fsl_pcie_data *info;
};
extern struct list_head fsl_pcie_list;
diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c
index 3cdf05b..a5ea488 100644
--- a/drivers/pci/pcie_intel_fpga.c
+++ b/drivers/pci/pcie_intel_fpga.c
@@ -36,16 +36,18 @@
#define RP_CFG_ADDR(pcie, reg) \
((pcie->hip_base) + (reg) + (1 << 20))
+#define RP_SECONDARY(pcie) \
+ readb(RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
#define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
#define TLP_CFGRD_DW0(pcie, bus) \
- ((((bus != pcie->first_busno) ? TLP_FMTTYPE_CFGRD0 \
- : TLP_FMTTYPE_CFGRD1) << 24) | \
+ ((((bus > RP_SECONDARY(pcie)) ? TLP_FMTTYPE_CFGRD1 \
+ : TLP_FMTTYPE_CFGRD0) << 24) | \
TLP_PAYLOAD_SIZE)
#define TLP_CFGWR_DW0(pcie, bus) \
- ((((bus != pcie->first_busno) ? TLP_FMTTYPE_CFGWR0 \
- : TLP_FMTTYPE_CFGWR1) << 24) | \
+ ((((bus > RP_SECONDARY(pcie)) ? TLP_FMTTYPE_CFGWR1 \
+ : TLP_FMTTYPE_CFGWR0) << 24) | \
TLP_PAYLOAD_SIZE)
#define TLP_CFG_DW1(pcie, tag, be) \
@@ -56,7 +58,7 @@
#define TLP_COMP_STATUS(s) (((s) >> 13) & 7)
#define TLP_BYTE_COUNT(s) (((s) >> 0) & 0xfff)
#define TLP_HDR_SIZE 3
-#define TLP_LOOP 500
+#define TLP_LOOP 20000
#define DWORD_MASK 3
#define IS_ROOT_PORT(pcie, bdf) \
@@ -161,8 +163,10 @@
dw[count++] = cra_readl(pcie, RP_RXCPL_REG);
if (ctrl & RP_RXCPL_EOP) {
comp_status = TLP_COMP_STATUS(dw[1]);
- if (comp_status)
- return -EFAULT;
+ if (comp_status) {
+ *value = pci_get_ff(PCI_SIZE_32);
+ return 0;
+ }
if (value &&
TLP_BYTE_COUNT(dw[1]) == sizeof(u32) &&
diff --git a/drivers/pci_endpoint/Kconfig b/drivers/pci_endpoint/Kconfig
new file mode 100644
index 0000000..19cfa0a
--- /dev/null
+++ b/drivers/pci_endpoint/Kconfig
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# PCI Endpoint Support
+#
+
+menu "PCI Endpoint"
+
+config PCI_ENDPOINT
+ bool "PCI Endpoint Support"
+ depends on DM
+ help
+ Enable this configuration option to support configurable PCI
+ endpoints. This should be enabled if the platform has a PCI
+ controllers that can operate in endpoint mode (as a device
+ connected to PCI host or bridge).
+
+config PCIE_CADENCE_EP
+ bool "Cadence PCIe endpoint controller"
+ depends on PCI_ENDPOINT
+ help
+ Say Y here if you want to support the Cadence PCIe controller in
+ endpoint mode. This PCIe controller may be embedded into many
+ different vendors SoCs.
+
+config PCI_SANDBOX_EP
+ bool "Sandbox PCIe endpoint controller"
+ depends on PCI_ENDPOINT
+ help
+ Say Y here if you want to support the Sandbox PCIe controller in
+ endpoint mode.
+ The sandbox driver act as a dummy driver which stores and
+ retrieves PCIe endpoint configuration as is.
+
+endmenu
diff --git a/drivers/pci_endpoint/Makefile b/drivers/pci_endpoint/Makefile
new file mode 100644
index 0000000..3cd9872
--- /dev/null
+++ b/drivers/pci_endpoint/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019
+# Ramon Fried <ramon.fried@gmail.com>
+
+obj-y += pci_ep-uclass.o
+obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep.o
+obj-$(CONFIG_PCI_SANDBOX_EP) += sandbox-pci_ep.o
diff --git a/drivers/pci_endpoint/pci_ep-uclass.c b/drivers/pci_endpoint/pci_ep-uclass.c
new file mode 100644
index 0000000..9f53a9a
--- /dev/null
+++ b/drivers/pci_endpoint/pci_ep-uclass.c
@@ -0,0 +1,211 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * PCI Endpoint uclass
+ *
+ * Based on Linux PCI-EP driver written by
+ * Kishon Vijay Abraham I <kishon@ti.com>
+ *
+ * Copyright (c) 2019
+ * Written by Ramon Fried <ramon.fried@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <linux/log2.h>
+#include <pci_ep.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int pci_ep_write_header(struct udevice *dev, uint fn, struct pci_ep_header *hdr)
+{
+ struct pci_ep_ops *ops = pci_ep_get_ops(dev);
+
+ if (!ops->write_header)
+ return -ENOSYS;
+
+ return ops->write_header(dev, fn, hdr);
+}
+
+int pci_ep_read_header(struct udevice *dev, uint fn, struct pci_ep_header *hdr)
+{
+ struct pci_ep_ops *ops = pci_ep_get_ops(dev);
+
+ if (!ops->read_header)
+ return -ENOSYS;
+
+ return ops->read_header(dev, fn, hdr);
+}
+
+int pci_ep_set_bar(struct udevice *dev, uint func_no, struct pci_bar *ep_bar)
+{
+ struct pci_ep_ops *ops = pci_ep_get_ops(dev);
+ int flags = ep_bar->flags;
+
+ /* Some basic bar validity checks */
+ if (ep_bar->barno > BAR_5 || ep_bar->barno < BAR_0)
+ return -EINVAL;
+
+ if ((ep_bar->barno == BAR_5 &&
+ (flags & PCI_BASE_ADDRESS_MEM_TYPE_64)) ||
+ ((flags & PCI_BASE_ADDRESS_SPACE_IO) &&
+ (flags & PCI_BASE_ADDRESS_IO_MASK)) ||
+ (upper_32_bits(ep_bar->size) &&
+ !(flags & PCI_BASE_ADDRESS_MEM_TYPE_64)))
+ return -EINVAL;
+
+ if (!ops->set_bar)
+ return -ENOSYS;
+
+ return ops->set_bar(dev, func_no, ep_bar);
+}
+
+int pci_ep_read_bar(struct udevice *dev, uint func_no, struct pci_bar *ep_bar,
+ enum pci_barno barno)
+{
+ struct pci_ep_ops *ops = pci_ep_get_ops(dev);
+
+ /* Some basic bar validity checks */
+ if (barno > BAR_5 || barno < BAR_0)
+ return -EINVAL;
+
+ if (!ops->read_bar)
+ return -ENOSYS;
+
+ return ops->read_bar(dev, func_no, ep_bar, barno);
+}
+
+int pci_ep_clear_bar(struct udevice *dev, uint func_num, enum pci_barno bar)
+{
+ struct pci_ep_ops *ops = pci_ep_get_ops(dev);
+
+ if (!ops->clear_bar)
+ return -ENOSYS;
+
+ return ops->clear_bar(dev, func_num, bar);
+}
+
+int pci_ep_map_addr(struct udevice *dev, uint func_no, phys_addr_t addr,
+ u64 pci_addr, size_t size)
+{
+ struct pci_ep_ops *ops = pci_ep_get_ops(dev);
+
+ if (!ops->map_addr)
+ return -ENOSYS;
+
+ return ops->map_addr(dev, func_no, addr, pci_addr, size);
+}
+
+int pci_ep_unmap_addr(struct udevice *dev, uint func_no, phys_addr_t addr)
+{
+ struct pci_ep_ops *ops = pci_ep_get_ops(dev);
+
+ if (!ops->unmap_addr)
+ return -ENOSYS;
+
+ return ops->unmap_addr(dev, func_no, addr);
+}
+
+int pci_ep_set_msi(struct udevice *dev, uint func_no, uint interrupts)
+{
+ struct pci_ep_ops *ops = pci_ep_get_ops(dev);
+ uint encode_int;
+
+ if (interrupts > 32)
+ return -EINVAL;
+
+ if (!ops->set_msi)
+ return -ENOSYS;
+
+ /* MSI spec permits allocation of
+ * only 1, 2, 4, 8, 16, 32 interrupts
+ */
+ encode_int = order_base_2(interrupts);
+
+ return ops->set_msi(dev, func_no, encode_int);
+}
+
+int pci_ep_get_msi(struct udevice *dev, uint func_no)
+{
+ struct pci_ep_ops *ops = pci_ep_get_ops(dev);
+ int interrupt;
+
+ if (!ops->get_msi)
+ return -ENOSYS;
+
+ interrupt = ops->get_msi(dev, func_no);
+
+ if (interrupt < 0)
+ return 0;
+
+ /* Translate back from order base 2*/
+ interrupt = 1 << interrupt;
+
+ return interrupt;
+}
+
+int pci_ep_set_msix(struct udevice *dev, uint func_no, uint interrupts)
+{
+ struct pci_ep_ops *ops = pci_ep_get_ops(dev);
+
+ if (interrupts < 1 || interrupts > 2048)
+ return -EINVAL;
+
+ if (!ops->set_msix)
+ return -ENOSYS;
+
+ return ops->set_msix(dev, func_no, interrupts - 1);
+}
+
+int pci_ep_get_msix(struct udevice *dev, uint func_no)
+{
+ struct pci_ep_ops *ops = pci_ep_get_ops(dev);
+ int interrupt;
+
+ if (!ops->get_msix)
+ return -ENOSYS;
+
+ interrupt = ops->get_msix(dev, func_no);
+
+ if (interrupt < 0)
+ return 0;
+
+ return interrupt + 1;
+}
+
+int pci_ep_raise_irq(struct udevice *dev, uint func_no,
+ enum pci_ep_irq_type type, uint interrupt_num)
+{
+ struct pci_ep_ops *ops = pci_ep_get_ops(dev);
+
+ if (!ops->raise_irq)
+ return -ENOSYS;
+
+ return ops->raise_irq(dev, func_no, type, interrupt_num);
+}
+
+int pci_ep_start(struct udevice *dev)
+{
+ struct pci_ep_ops *ops = pci_ep_get_ops(dev);
+
+ if (!ops->start)
+ return -ENOSYS;
+
+ return ops->start(dev);
+}
+
+int pci_ep_stop(struct udevice *dev)
+{
+ struct pci_ep_ops *ops = pci_ep_get_ops(dev);
+
+ if (!ops->stop)
+ return -ENOSYS;
+
+ return ops->stop(dev);
+}
+
+UCLASS_DRIVER(pci_ep) = {
+ .id = UCLASS_PCI_EP,
+ .name = "pci_ep",
+ .flags = DM_UC_FLAG_SEQ_ALIAS,
+};
diff --git a/drivers/pci_endpoint/pcie-cadence-ep.c b/drivers/pci_endpoint/pcie-cadence-ep.c
new file mode 100644
index 0000000..59231d3
--- /dev/null
+++ b/drivers/pci_endpoint/pcie-cadence-ep.c
@@ -0,0 +1,177 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019
+ * Written by Ramon Fried <ramon.fried@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <pci_ep.h>
+#include <linux/sizes.h>
+#include <linux/log2.h>
+#include "pcie-cadence.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int cdns_write_header(struct udevice *dev, uint fn,
+ struct pci_ep_header *hdr)
+{
+ struct cdns_pcie *pcie = dev_get_priv(dev);
+
+ cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid);
+ cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid);
+ cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG,
+ hdr->progif_code);
+ cdns_pcie_ep_fn_writew(pcie, fn, PCI_CLASS_DEVICE,
+ hdr->subclass_code |
+ hdr->baseclass_code << 8);
+ cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CACHE_LINE_SIZE,
+ hdr->cache_line_size);
+ cdns_pcie_ep_fn_writew(pcie, fn, PCI_SUBSYSTEM_ID,
+ hdr->subsys_id);
+ cdns_pcie_ep_fn_writeb(pcie, fn, PCI_INTERRUPT_PIN,
+ hdr->interrupt_pin);
+
+ /*
+ * Vendor ID can only be modified from function 0, all other functions
+ * use the same vendor ID as function 0.
+ */
+ if (fn == 0) {
+ /* Update the vendor IDs. */
+ u32 id = CDNS_PCIE_LM_ID_VENDOR(hdr->vendorid) |
+ CDNS_PCIE_LM_ID_SUBSYS(hdr->subsys_vendor_id);
+
+ cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id);
+ }
+
+ return 0;
+}
+
+static int cdns_set_bar(struct udevice *dev, uint fn, struct pci_bar *ep_bar)
+{
+ struct cdns_pcie *pcie = dev_get_priv(dev);
+ dma_addr_t bar_phys = ep_bar->phys_addr;
+ enum pci_barno bar = ep_bar->barno;
+ int flags = ep_bar->flags;
+ u32 addr0, addr1, reg, cfg, b, aperture, ctrl;
+ u64 sz;
+
+ /* BAR size is 2^(aperture + 7) */
+ sz = max_t(size_t, ep_bar->size, CDNS_PCIE_EP_MIN_APERTURE);
+ /*
+ * roundup_pow_of_two() returns an unsigned long, which is not suited
+ * for 64bit values.
+ */
+ sz = 1ULL << fls64(sz - 1);
+ aperture = ilog2(sz) - 7; /* 128B -> 0, 256B -> 1, 512B -> 2, ... */
+
+ if ((flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
+ ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS;
+ } else {
+ bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH);
+ bool is_64bits = (sz > SZ_2G) |
+ !!(ep_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64);
+
+ if (is_64bits && (bar & 1))
+ return -EINVAL;
+
+ if (is_64bits && !(flags & PCI_BASE_ADDRESS_MEM_TYPE_64))
+ ep_bar->flags |= PCI_BASE_ADDRESS_MEM_TYPE_64;
+
+ if (is_64bits && is_prefetch)
+ ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS;
+ else if (is_prefetch)
+ ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS;
+ else if (is_64bits)
+ ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS;
+ else
+ ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS;
+ }
+
+ addr0 = lower_32_bits(bar_phys);
+ addr1 = upper_32_bits(bar_phys);
+ cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar),
+ addr0);
+ cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar),
+ addr1);
+
+ if (bar < BAR_4) {
+ reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn);
+ b = bar;
+ } else {
+ reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn);
+ b = bar - BAR_4;
+ }
+
+ cfg = cdns_pcie_readl(pcie, reg);
+ cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
+ CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
+ cfg |= (CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) |
+ CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl));
+ cdns_pcie_writel(pcie, reg, cfg);
+
+ return 0;
+}
+
+static int cdns_set_msi(struct udevice *dev, uint fn, uint mmc)
+{
+ struct cdns_pcie *pcie = dev_get_priv(dev);
+ u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
+
+ /*
+ * Set the Multiple Message Capable bitfield into the Message Control
+ * register.
+ */
+ u16 flags;
+
+ flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
+ flags = (flags & ~PCI_MSI_FLAGS_QMASK) | (mmc << 1);
+ flags |= PCI_MSI_FLAGS_64BIT;
+ flags &= ~PCI_MSI_FLAGS_MASKBIT;
+ cdns_pcie_ep_fn_writew(pcie, fn, cap + PCI_MSI_FLAGS, flags);
+
+ return 0;
+}
+
+static struct pci_ep_ops cdns_pci_ep_ops = {
+ .write_header = cdns_write_header,
+ .set_bar = cdns_set_bar,
+ .set_msi = cdns_set_msi,
+};
+
+static int cdns_pci_ep_probe(struct udevice *dev)
+{
+ struct cdns_pcie *pdata = dev_get_priv(dev);
+
+ pdata->reg_base = (void __iomem *)devfdt_get_addr(dev);
+ if (!pdata->reg_base)
+ return -ENOMEM;
+
+ pdata->max_functions = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "max-functions", 1);
+ pdata->max_regions = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "cdns,max-outbound-regions", 8);
+
+ return 0;
+}
+
+static int cdns_pci_ep_remove(struct udevice *dev)
+{
+ return 0;
+}
+
+const struct udevice_id cadence_pci_ep_of_match[] = {
+ { .compatible = "cdns,cdns-pcie-ep" },
+ { }
+};
+
+U_BOOT_DRIVER(cdns_pcie) = {
+ .name = "cdns,pcie-ep",
+ .id = UCLASS_PCI_EP,
+ .of_match = cadence_pci_ep_of_match,
+ .ops = &cdns_pci_ep_ops,
+ .probe = cdns_pci_ep_probe,
+ .remove = cdns_pci_ep_remove,
+ .priv_auto_alloc_size = sizeof(struct cdns_pcie),
+};
diff --git a/drivers/pci_endpoint/pcie-cadence.h b/drivers/pci_endpoint/pcie-cadence.h
new file mode 100644
index 0000000..91630d3
--- /dev/null
+++ b/drivers/pci_endpoint/pcie-cadence.h
@@ -0,0 +1,309 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Cadence PCIe controlloer definitions
+ * Adapted from linux kernel driver.
+ * Copyright (c) 2017 Cadence
+ *
+ * Copyright (c) 2019
+ * Written by Ramon Fried <ramon.fried@gmail.com>
+ */
+
+#ifndef PCIE_CADENCE_H
+#define PCIE_CADENCE_H
+
+#include <common.h>
+#include <pci_ep.h>
+#include <asm/io.h>
+
+/*
+ * Local Management Registers
+ */
+#define CDNS_PCIE_LM_BASE 0x00100000
+
+/* Vendor ID Register */
+#define CDNS_PCIE_LM_ID (CDNS_PCIE_LM_BASE + 0x0044)
+#define CDNS_PCIE_LM_ID_VENDOR_MASK GENMASK(15, 0)
+#define CDNS_PCIE_LM_ID_VENDOR_SHIFT 0
+#define CDNS_PCIE_LM_ID_VENDOR(vid) \
+ (((vid) << CDNS_PCIE_LM_ID_VENDOR_SHIFT) & CDNS_PCIE_LM_ID_VENDOR_MASK)
+#define CDNS_PCIE_LM_ID_SUBSYS_MASK GENMASK(31, 16)
+#define CDNS_PCIE_LM_ID_SUBSYS_SHIFT 16
+#define CDNS_PCIE_LM_ID_SUBSYS(sub) \
+ (((sub) << CDNS_PCIE_LM_ID_SUBSYS_SHIFT) & CDNS_PCIE_LM_ID_SUBSYS_MASK)
+
+/* Root Port Requestor ID Register */
+#define CDNS_PCIE_LM_RP_RID (CDNS_PCIE_LM_BASE + 0x0228)
+#define CDNS_PCIE_LM_RP_RID_MASK GENMASK(15, 0)
+#define CDNS_PCIE_LM_RP_RID_SHIFT 0
+#define CDNS_PCIE_LM_RP_RID_(rid) \
+ (((rid) << CDNS_PCIE_LM_RP_RID_SHIFT) & CDNS_PCIE_LM_RP_RID_MASK)
+
+/* Endpoint Bus and Device Number Register */
+#define CDNS_PCIE_LM_EP_ID (CDNS_PCIE_LM_BASE + 0x022c)
+#define CDNS_PCIE_LM_EP_ID_DEV_MASK GENMASK(4, 0)
+#define CDNS_PCIE_LM_EP_ID_DEV_SHIFT 0
+#define CDNS_PCIE_LM_EP_ID_BUS_MASK GENMASK(15, 8)
+#define CDNS_PCIE_LM_EP_ID_BUS_SHIFT 8
+
+/* Endpoint Function f BAR b Configuration Registers */
+#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) \
+ (CDNS_PCIE_LM_BASE + 0x0240 + (fn) * 0x0008)
+#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn) \
+ (CDNS_PCIE_LM_BASE + 0x0244 + (fn) * 0x0008)
+#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) \
+ (GENMASK(4, 0) << ((b) * 8))
+#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \
+ (((a) << ((b) * 8)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b))
+#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b) \
+ (GENMASK(7, 5) << ((b) * 8))
+#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \
+ (((c) << ((b) * 8 + 5)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b))
+
+/* Endpoint Function Configuration Register */
+#define CDNS_PCIE_LM_EP_FUNC_CFG (CDNS_PCIE_LM_BASE + 0x02c0)
+
+/* Root Complex BAR Configuration Register */
+#define CDNS_PCIE_LM_RC_BAR_CFG (CDNS_PCIE_LM_BASE + 0x0300)
+#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(5, 0)
+#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE(a) \
+ (((a) << 0) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK)
+#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(8, 6)
+#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(c) \
+ (((c) << 6) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK)
+#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(13, 9)
+#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE(a) \
+ (((a) << 9) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK)
+#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(16, 14)
+#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(c) \
+ (((c) << 14) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK)
+#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(17)
+#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_32BITS 0
+#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(18)
+#define CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE BIT(19)
+#define CDNS_PCIE_LM_RC_BAR_CFG_IO_16BITS 0
+#define CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS BIT(20)
+#define CDNS_PCIE_LM_RC_BAR_CFG_CHECK_ENABLE BIT(31)
+
+/* BAR control values applicable to both Endpoint Function and Root Complex */
+#define CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED 0x0
+#define CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS 0x1
+#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS 0x4
+#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x5
+#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS 0x6
+#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0x7
+
+/*
+ * Endpoint Function Registers (PCI configuration space for endpoint functions)
+ */
+#define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12))
+
+#define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET 0x90
+
+/*
+ * Root Port Registers (PCI configuration space for the root port function)
+ */
+#define CDNS_PCIE_RP_BASE 0x00200000
+
+/*
+ * Address Translation Registers
+ */
+#define CDNS_PCIE_AT_BASE 0x00400000
+
+/* Region r Outbound AXI to PCIe Address Translation Register 0 */
+#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r) \
+ (CDNS_PCIE_AT_BASE + 0x0000 + ((r) & 0x1f) * 0x0020)
+#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0)
+#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \
+ (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK)
+#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(19, 12)
+#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \
+ (((devfn) << 12) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK)
+#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(27, 20)
+#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \
+ (((bus) << 20) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK)
+
+/* Region r Outbound AXI to PCIe Address Translation Register 1 */
+#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r) \
+ (CDNS_PCIE_AT_BASE + 0x0004 + ((r) & 0x1f) * 0x0020)
+
+/* Region r Outbound PCIe Descriptor Register 0 */
+#define CDNS_PCIE_AT_OB_REGION_DESC0(r) \
+ (CDNS_PCIE_AT_BASE + 0x0008 + ((r) & 0x1f) * 0x0020)
+#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(3, 0)
+#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM 0x2
+#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO 0x6
+#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 0xa
+#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 0xb
+#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG 0xc
+#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_VENDOR_MSG 0xd
+/* Bit 23 MUST be set in RC mode. */
+#define CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID BIT(23)
+#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK GENMASK(31, 24)
+#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) \
+ (((devfn) << 24) & CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK)
+
+/* Region r Outbound PCIe Descriptor Register 1 */
+#define CDNS_PCIE_AT_OB_REGION_DESC1(r) \
+ (CDNS_PCIE_AT_BASE + 0x000c + ((r) & 0x1f) * 0x0020)
+#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK GENMASK(7, 0)
+#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus) \
+ ((bus) & CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK)
+
+/* Region r AXI Region Base Address Register 0 */
+#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r) \
+ (CDNS_PCIE_AT_BASE + 0x0018 + ((r) & 0x1f) * 0x0020)
+#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0)
+#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \
+ (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK)
+
+/* Region r AXI Region Base Address Register 1 */
+#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r) \
+ (CDNS_PCIE_AT_BASE + 0x001c + ((r) & 0x1f) * 0x0020)
+
+/* Root Port BAR Inbound PCIe to AXI Address Translation Register */
+#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar) \
+ (CDNS_PCIE_AT_BASE + 0x0800 + (bar) * 0x0008)
+#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0)
+#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \
+ (((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK)
+#define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \
+ (CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008)
+
+/* AXI link down register */
+#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824)
+
+enum cdns_pcie_rp_bar {
+ RP_BAR0,
+ RP_BAR1,
+ RP_NO_BAR
+};
+
+/* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register */
+#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \
+ (CDNS_PCIE_AT_BASE + 0x0840 + (fn) * 0x0040 + (bar) * 0x0008)
+#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \
+ (CDNS_PCIE_AT_BASE + 0x0844 + (fn) * 0x0040 + (bar) * 0x0008)
+
+/* Normal/Vendor specific message access: offset inside some outbound region */
+#define CDNS_PCIE_NORMAL_MSG_ROUTING_MASK GENMASK(7, 5)
+#define CDNS_PCIE_NORMAL_MSG_ROUTING(route) \
+ (((route) << 5) & CDNS_PCIE_NORMAL_MSG_ROUTING_MASK)
+#define CDNS_PCIE_NORMAL_MSG_CODE_MASK GENMASK(15, 8)
+#define CDNS_PCIE_NORMAL_MSG_CODE(code) \
+ (((code) << 8) & CDNS_PCIE_NORMAL_MSG_CODE_MASK)
+#define CDNS_PCIE_MSG_NO_DATA BIT(16)
+
+#define CDNS_PCIE_EP_MIN_APERTURE 128 /* 128 bytes */
+
+enum cdns_pcie_msg_code {
+ MSG_CODE_ASSERT_INTA = 0x20,
+ MSG_CODE_ASSERT_INTB = 0x21,
+ MSG_CODE_ASSERT_INTC = 0x22,
+ MSG_CODE_ASSERT_INTD = 0x23,
+ MSG_CODE_DEASSERT_INTA = 0x24,
+ MSG_CODE_DEASSERT_INTB = 0x25,
+ MSG_CODE_DEASSERT_INTC = 0x26,
+ MSG_CODE_DEASSERT_INTD = 0x27,
+};
+
+enum cdns_pcie_msg_routing {
+ /* Route to Root Complex */
+ MSG_ROUTING_TO_RC,
+
+ /* Use Address Routing */
+ MSG_ROUTING_BY_ADDR,
+
+ /* Use ID Routing */
+ MSG_ROUTING_BY_ID,
+
+ /* Route as Broadcast Message from Root Complex */
+ MSG_ROUTING_BCAST,
+
+ /* Local message; terminate at receiver (INTx messages) */
+ MSG_ROUTING_LOCAL,
+
+ /* Gather & route to Root Complex (PME_TO_Ack message) */
+ MSG_ROUTING_GATHER,
+};
+
+struct cdns_pcie {
+ void __iomem *reg_base;
+ u32 max_functions;
+ u32 max_regions;
+};
+
+/* Register access */
+static inline void cdns_pcie_writeb(struct cdns_pcie *pcie, u32 reg, u8 value)
+{
+ writeb(value, pcie->reg_base + reg);
+}
+
+static inline void cdns_pcie_writew(struct cdns_pcie *pcie, u32 reg, u16 value)
+{
+ writew(value, pcie->reg_base + reg);
+}
+
+static inline void cdns_pcie_writel(struct cdns_pcie *pcie, u32 reg, u32 value)
+{
+ writel(value, pcie->reg_base + reg);
+}
+
+static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg)
+{
+ return readl(pcie->reg_base + reg);
+}
+
+/* Root Port register access */
+static inline void cdns_pcie_rp_writeb(struct cdns_pcie *pcie,
+ u32 reg, u8 value)
+{
+ writeb(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg);
+}
+
+static inline void cdns_pcie_rp_writew(struct cdns_pcie *pcie,
+ u32 reg, u16 value)
+{
+ writew(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg);
+}
+
+static inline void cdns_pcie_rp_writel(struct cdns_pcie *pcie,
+ u32 reg, u32 value)
+{
+ writel(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg);
+}
+
+/* Endpoint Function register access */
+static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn,
+ u32 reg, u8 value)
+{
+ writeb(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
+}
+
+static inline void cdns_pcie_ep_fn_writew(struct cdns_pcie *pcie, u8 fn,
+ u32 reg, u16 value)
+{
+ writew(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
+}
+
+static inline void cdns_pcie_ep_fn_writel(struct cdns_pcie *pcie, u8 fn,
+ u32 reg, u32 value)
+{
+ writel(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
+}
+
+static inline u8 cdns_pcie_ep_fn_readb(struct cdns_pcie *pcie, u8 fn, u32 reg)
+{
+ return readb(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
+}
+
+static inline u16 cdns_pcie_ep_fn_readw(struct cdns_pcie *pcie, u8 fn, u32 reg)
+{
+ return readw(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
+}
+
+static inline u32 cdns_pcie_ep_fn_readl(struct cdns_pcie *pcie, u8 fn, u32 reg)
+{
+ return readl(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
+}
+
+#endif /* end of include guard: PCIE_CADENCE_H */
diff --git a/drivers/pci_endpoint/sandbox-pci_ep.c b/drivers/pci_endpoint/sandbox-pci_ep.c
new file mode 100644
index 0000000..8e05d5b
--- /dev/null
+++ b/drivers/pci_endpoint/sandbox-pci_ep.c
@@ -0,0 +1,179 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Ramon Fried <ramon.fried@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <pci.h>
+#include <pci_ep.h>
+#include <asm/test.h>
+
+/**
+ * struct sandbox_pci_ep_priv - private data for driver
+ * @hdr: Stores the EP device header
+ * @msix: required MSIx count;
+ * @msi: required MSI count;
+ */
+struct sandbox_pci_ep_priv {
+ struct pci_ep_header hdr;
+ struct pci_bar bars[6];
+ int msix;
+ int msi;
+ int irq_count;
+};
+
+/* Method exported for testing purposes */
+int sandbox_get_pci_ep_irq_count(struct udevice *dev)
+{
+ struct sandbox_pci_ep_priv *priv = dev_get_priv(dev);
+
+ return priv->irq_count;
+}
+
+static const struct udevice_id sandbox_pci_ep_ids[] = {
+ { .compatible = "sandbox,pci_ep" },
+ { }
+};
+
+static int sandbox_write_header(struct udevice *dev, uint fn,
+ struct pci_ep_header *hdr)
+{
+ struct sandbox_pci_ep_priv *priv = dev_get_priv(dev);
+
+ if (fn > 0)
+ return -ENODEV;
+
+ memcpy(&priv->hdr, hdr, sizeof(*hdr));
+
+ return 0;
+}
+
+static int sandbox_read_header(struct udevice *dev, uint fn,
+ struct pci_ep_header *hdr)
+{
+ struct sandbox_pci_ep_priv *priv = dev_get_priv(dev);
+
+ if (fn > 0)
+ return -ENODEV;
+
+ memcpy(hdr, &priv->hdr, sizeof(*hdr));
+
+ return 0;
+}
+
+static int sandbox_set_bar(struct udevice *dev, uint fn,
+ struct pci_bar *ep_bar)
+{
+ struct sandbox_pci_ep_priv *priv = dev_get_priv(dev);
+ int bar_idx;
+
+ if (fn > 0)
+ return -ENODEV;
+
+ bar_idx = ep_bar->barno;
+
+ memcpy(&priv->bars[bar_idx], ep_bar, sizeof(*ep_bar));
+
+ return 0;
+}
+
+static int sandbox_read_bar(struct udevice *dev, uint fn,
+ struct pci_bar *ep_bar, enum pci_barno barno)
+{
+ struct sandbox_pci_ep_priv *priv = dev_get_priv(dev);
+
+ if (fn > 0)
+ return -ENODEV;
+
+ memcpy(ep_bar, &priv->bars[barno], sizeof(*ep_bar));
+
+ return 0;
+}
+
+static int sandbox_set_msi(struct udevice *dev, uint fn, uint interrupts)
+{
+ struct sandbox_pci_ep_priv *priv = dev_get_priv(dev);
+
+ if (fn > 0)
+ return -ENODEV;
+
+ priv->msi = interrupts;
+
+ return 0;
+}
+
+static int sandbox_get_msi(struct udevice *dev, uint fn)
+{
+ struct sandbox_pci_ep_priv *priv = dev_get_priv(dev);
+
+ if (fn > 0)
+ return -ENODEV;
+
+ return priv->msi;
+}
+
+static int sandbox_set_msix(struct udevice *dev, uint fn, uint interrupts)
+{
+ struct sandbox_pci_ep_priv *priv = dev_get_priv(dev);
+
+ if (fn > 0)
+ return -ENODEV;
+
+ priv->msix = interrupts;
+
+ return 0;
+}
+
+static int sandbox_get_msix(struct udevice *dev, uint fn)
+{
+ struct sandbox_pci_ep_priv *priv = dev_get_priv(dev);
+
+ if (fn > 0)
+ return -ENODEV;
+
+ return priv->msix;
+}
+
+static int sandbox_raise_irq(struct udevice *dev, uint fn,
+ enum pci_ep_irq_type type, uint interrupt_num)
+{
+ struct sandbox_pci_ep_priv *priv = dev_get_priv(dev);
+
+ if (fn > 0)
+ return -ENODEV;
+
+ priv->irq_count++;
+
+ return 0;
+}
+
+static int sandbox_pci_ep_probe(struct udevice *dev)
+{
+ struct sandbox_pci_ep_priv *priv = dev_get_priv(dev);
+
+ memset(priv, 0, sizeof(*priv));
+ return 0;
+}
+
+static struct pci_ep_ops sandbox_pci_ep_ops = {
+ .write_header = sandbox_write_header,
+ .read_header = sandbox_read_header,
+ .set_bar = sandbox_set_bar,
+ .read_bar = sandbox_read_bar,
+ .set_msi = sandbox_set_msi,
+ .get_msi = sandbox_get_msi,
+ .set_msix = sandbox_set_msix,
+ .get_msix = sandbox_get_msix,
+ .raise_irq = sandbox_raise_irq,
+};
+
+U_BOOT_DRIVER(pci_ep_sandbox) = {
+ .name = "pci_ep_sandbox",
+ .id = UCLASS_PCI_EP,
+ .of_match = sandbox_pci_ep_ids,
+ .probe = sandbox_pci_ep_probe,
+ .ops = &sandbox_pci_ep_ops,
+ .priv_auto_alloc_size = sizeof(struct sandbox_pci_ep_priv),
+};
diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile
deleted file mode 100644
index 8374a56..0000000
--- a/drivers/pcmcia/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-$(CONFIG_MARUBUN_PCCARD) += marubun_pcmcia.o
diff --git a/drivers/pcmcia/marubun_pcmcia.c b/drivers/pcmcia/marubun_pcmcia.c
deleted file mode 100644
index b2eea6c..0000000
--- a/drivers/pcmcia/marubun_pcmcia.c
+++ /dev/null
@@ -1,99 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Marubun MR-SHPC-01 PCMCIA controller device driver
- *
- * (c) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- */
-
-#include <common.h>
-#include <config.h>
-#include <pcmcia.h>
-#include <asm/io.h>
-
-#undef CONFIG_PCMCIA
-
-#if defined(CONFIG_CMD_PCMCIA)
-#define CONFIG_PCMCIA
-#endif
-
-#if defined(CONFIG_IDE)
-#define CONFIG_PCMCIA
-#endif
-
-#if defined(CONFIG_PCMCIA)
-
-/* MR-SHPC-01 register */
-#define MRSHPC_MODE (CONFIG_SYS_MARUBUN_MRSHPC + 4)
-#define MRSHPC_OPTION (CONFIG_SYS_MARUBUN_MRSHPC + 6)
-#define MRSHPC_CSR (CONFIG_SYS_MARUBUN_MRSHPC + 8)
-#define MRSHPC_ISR (CONFIG_SYS_MARUBUN_MRSHPC + 10)
-#define MRSHPC_ICR (CONFIG_SYS_MARUBUN_MRSHPC + 12)
-#define MRSHPC_CPWCR (CONFIG_SYS_MARUBUN_MRSHPC + 14)
-#define MRSHPC_MW0CR1 (CONFIG_SYS_MARUBUN_MRSHPC + 16)
-#define MRSHPC_MW1CR1 (CONFIG_SYS_MARUBUN_MRSHPC + 18)
-#define MRSHPC_IOWCR1 (CONFIG_SYS_MARUBUN_MRSHPC + 20)
-#define MRSHPC_MW0CR2 (CONFIG_SYS_MARUBUN_MRSHPC + 22)
-#define MRSHPC_MW1CR2 (CONFIG_SYS_MARUBUN_MRSHPC + 24)
-#define MRSHPC_IOWCR2 (CONFIG_SYS_MARUBUN_MRSHPC + 26)
-#define MRSHPC_CDCR (CONFIG_SYS_MARUBUN_MRSHPC + 28)
-#define MRSHPC_PCIC_INFO (CONFIG_SYS_MARUBUN_MRSHPC + 30)
-
-int pcmcia_on (void)
-{
- printf("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
-
- /* Init */
- outw( 0x0000 , MRSHPC_MODE );
-
- if ((inw(MRSHPC_CSR) & 0x000c) == 0){ /* if card detect is true */
- if ((inw(MRSHPC_CSR) & 0x0080) == 0){
- outw(0x0674 ,MRSHPC_CPWCR); /* Card Vcc is 3.3v? */
- }else{
- outw(0x0678 ,MRSHPC_CPWCR); /* Card Vcc is 5V */
- }
- udelay( 100000 ); /* wait for power on */
- }else{
- return 1;
- }
- /*
- * PC-Card window open
- * flag == COMMON/ATTRIBUTE/IO
- */
- /* common window open */
- outw(0x8a84,MRSHPC_MW0CR1); /* window 0xb8400000 */
- if ((inw(MRSHPC_CSR) & 0x4000) != 0)
- outw(0x0b00,MRSHPC_MW0CR2); /* common mode & bus width 16bit SWAP = 1 */
- else
- outw(0x0300,MRSHPC_MW0CR2); /* common mode & bus width 16bit SWAP = 0 */
-
- /* attribute window open */
- outw(0x8a85,MRSHPC_MW1CR1); /* window 0xb8500000 */
- if ((inw(MRSHPC_CSR) & 0x4000) != 0)
- outw(0x0a00,MRSHPC_MW1CR2); /* attribute mode & bus width 16bit SWAP = 1 */
- else
- outw(0x0200,MRSHPC_MW1CR2); /* attribute mode & bus width 16bit SWAP = 0 */
-
- /* I/O window open */
- outw(0x8a86,MRSHPC_IOWCR1); /* I/O window 0xb8600000 */
- outw(0x0008,MRSHPC_CDCR); /* I/O card mode */
- if ((inw(MRSHPC_CSR) & 0x4000) != 0)
- outw(0x0a00,MRSHPC_IOWCR2); /* bus width 16bit SWAP = 1 */
- else
- outw(0x0200,MRSHPC_IOWCR2); /* bus width 16bit SWAP = 0 */
-
- outw(0x0000,MRSHPC_ISR);
- outw(0x2000,MRSHPC_ICR);
- outb(0x00,(CONFIG_SYS_MARUBUN_MW2 + 0x206));
- outb(0x42,(CONFIG_SYS_MARUBUN_MW2 + 0x200));
-
- return 0;
-}
-
-int pcmcia_off (void)
-{
- printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n");
-
- return 0;
-}
-
-#endif /* CONFIG_PCMCIA */
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 957efb3..0231227 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -19,7 +19,7 @@
config SPL_PHY
bool "PHY Core in SPL"
- depends on DM
+ depends on DM && SPL
help
PHY support in SPL.
@@ -84,6 +84,12 @@
help
Support for the Broadcom MIPS BCM6368 USBH PHY.
+config PHY_DA8XX_USB
+ tristate "TI DA8xx USB PHY Driver"
+ depends on PHY && ARCH_DAVINCI
+ help
+ Enable this to support the USB PHY on DA8xx SoCs.
+
config PIPE3_PHY
bool "Support omap's PIPE3 PHY"
depends on PHY && ARCH_OMAP2PLUS
@@ -102,6 +108,15 @@
This PHY is found on omap devices supporting SATA such as dra7, am57x
and omap5
+config AM654_PHY
+ tristate "TI AM654 SERDES support"
+ depends on PHY && ARCH_K3
+ select REGMAP
+ select SYSCON
+ help
+ This option enables support for TI AM654 SerDes PHY used for
+ PCIe.
+
config STI_USB_PHY
bool "STMicroelectronics USB2 picoPHY driver for STiH407 family"
depends on PHY && ARCH_STI
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 90646ca..3157f1b 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -11,6 +11,7 @@
obj-$(CONFIG_BCM6368_USBH_PHY) += bcm6368-usbh-phy.o
obj-$(CONFIG_PHY_SANDBOX) += sandbox-phy.o
obj-$(CONFIG_$(SPL_)PIPE3_PHY) += ti-pipe3-phy.o
+obj-$(CONFIG_AM654_PHY) += phy-ti-am654.o
obj-$(CONFIG_STI_USB_PHY) += sti_usb_phy.o
obj-$(CONFIG_PHY_RCAR_GEN2) += phy-rcar-gen2.o
obj-$(CONFIG_PHY_RCAR_GEN3) += phy-rcar-gen3.o
@@ -21,3 +22,4 @@
obj-$(CONFIG_OMAP_USB2_PHY) += omap-usb2-phy.o
obj-$(CONFIG_KEYSTONE_USB_PHY) += keystone-usb-phy.o
obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o
+obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
index f206fa3..5e8f877 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -75,6 +75,7 @@
sun8i_h3_phy,
sun8i_v3s_phy,
sun50i_a64_phy,
+ sun50i_h6_phy,
};
struct sun4i_usb_phy_cfg {
@@ -85,6 +86,7 @@
bool dedicated_clocks;
bool enable_pmu_unk1;
bool phy0_dual_route;
+ int missing_phys;
};
struct sun4i_usb_phy_info {
@@ -349,6 +351,9 @@
if (args->args_count >= data->cfg->num_phys)
return -EINVAL;
+ if (data->cfg->missing_phys & BIT(args->args[0]))
+ return -ENODEV;
+
if (args->args_count)
phy->id = args->args[0];
else
@@ -429,6 +434,9 @@
struct sun4i_usb_phy_info *info = &phy_info[i];
char name[16];
+ if (data->cfg->missing_phys & BIT(i))
+ continue;
+
phy->gpio_vbus = sunxi_name_to_gpio(info->gpio_vbus);
if (phy->gpio_vbus >= 0) {
ret = gpio_request(phy->gpio_vbus, "usb_vbus");
@@ -583,6 +591,17 @@
.phy0_dual_route = true,
};
+static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
+ .num_phys = 4,
+ .type = sun50i_h6_phy,
+ .disc_thresh = 3,
+ .phyctl_offset = REG_PHYCTL_A33,
+ .dedicated_clocks = true,
+ .enable_pmu_unk1 = true,
+ .phy0_dual_route = true,
+ .missing_phys = BIT(1) | BIT(2),
+};
+
static const struct udevice_id sun4i_usb_phy_ids[] = {
{ .compatible = "allwinner,sun4i-a10-usb-phy", .data = (ulong)&sun4i_a10_cfg },
{ .compatible = "allwinner,sun5i-a13-usb-phy", .data = (ulong)&sun5i_a13_cfg },
@@ -594,6 +613,7 @@
{ .compatible = "allwinner,sun8i-h3-usb-phy", .data = (ulong)&sun8i_h3_cfg },
{ .compatible = "allwinner,sun8i-v3s-usb-phy", .data = (ulong)&sun8i_v3s_cfg },
{ .compatible = "allwinner,sun50i-a64-usb-phy", .data = (ulong)&sun50i_a64_cfg},
+ { .compatible = "allwinner,sun50i-h6-usb-phy", .data = (ulong)&sun50i_h6_cfg},
{ }
};
diff --git a/drivers/phy/phy-da8xx-usb.c b/drivers/phy/phy-da8xx-usb.c
new file mode 100644
index 0000000..034b479
--- /dev/null
+++ b/drivers/phy/phy-da8xx-usb.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Based on the DA8xx "glue layer" code.
+ * Copyright (c) 2008-2019, MontaVista Software, Inc. <source@mvista.com>
+ *
+ * DT support added by: Adam Ford <aford173@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/da8xx-usb.h>
+#include <asm/io.h>
+#include <generic-phy.h>
+
+static int da8xx_usb_phy_power_on(struct phy *phy)
+{
+ unsigned long timeout;
+
+ clrsetbits_le32(&davinci_syscfg_regs->cfgchip2,
+ CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN |
+ CFGCHIP2_OTGMODE | CFGCHIP2_REFFREQ,
+ CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN |
+ CFGCHIP2_PHY_PLLON | CFGCHIP2_REFFREQ_24MHZ);
+
+ /* wait until the usb phy pll locks */
+ timeout = get_timer(0);
+ while (get_timer(timeout) < 10) {
+ if (readl(&davinci_syscfg_regs->cfgchip2) & CFGCHIP2_PHYCLKGD)
+ return 0;
+ }
+
+ debug("Phy was not turned on\n");
+
+ return -ENODEV;
+}
+
+static int da8xx_usb_phy_power_off(struct phy *phy)
+{
+ clrsetbits_le32(&davinci_syscfg_regs->cfgchip2,
+ CFGCHIP2_PHY_PLLON,
+ CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN);
+
+ return 0;
+}
+
+static const struct udevice_id da8xx_phy_ids[] = {
+ { .compatible = "ti,da830-usb-phy" },
+ { }
+};
+
+static struct phy_ops da8xx_phy_ops = {
+ .power_on = da8xx_usb_phy_power_on,
+ .power_off = da8xx_usb_phy_power_off,
+};
+
+U_BOOT_DRIVER(da8xx_phy) = {
+ .name = "da8xx-usb-phy",
+ .id = UCLASS_PHY,
+ .of_match = da8xx_phy_ids,
+ .ops = &da8xx_phy_ops,
+};
diff --git a/drivers/phy/phy-ti-am654.c b/drivers/phy/phy-ti-am654.c
new file mode 100644
index 0000000..3949012
--- /dev/null
+++ b/drivers/phy/phy-ti-am654.c
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: GPL-2.0+
+/**
+ * PCIe SERDES driver for AM654x SoC
+ *
+ * Copyright (C) 2018 Texas Instruments
+ * Author: Kishon Vijay Abraham I <kishon@ti.com>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <dm/device.h>
+#include <dm/lists.h>
+#include <dt-bindings/phy/phy.h>
+#include <generic-phy.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <power-domain.h>
+#include <regmap.h>
+#include <syscon.h>
+
+#define CMU_R07C 0x7c
+#define CMU_MASTER_CDN_O BIT(24)
+
+#define COMLANE_R138 0xb38
+#define CONFIG_VERSION_REG_MASK GENMASK(23, 16)
+#define CONFIG_VERSION_REG_SHIFT 16
+#define VERSION 0x70
+
+#define COMLANE_R190 0xb90
+#define L1_MASTER_CDN_O BIT(9)
+
+#define COMLANE_R194 0xb94
+#define CMU_OK_I_0 BIT(19)
+
+#define SERDES_CTRL 0x1fd0
+#define POR_EN BIT(29)
+
+#define WIZ_LANEXCTL_STS 0x1fe0
+#define TX0_ENABLE_OVL BIT(31)
+#define TX0_ENABLE_MASK GENMASK(30, 29)
+#define TX0_ENABLE_SHIFT 29
+#define TX0_DISABLE_STATE 0x0
+#define TX0_SLEEP_STATE 0x1
+#define TX0_SNOOZE_STATE 0x2
+#define TX0_ENABLE_STATE 0x3
+#define RX0_ENABLE_OVL BIT(15)
+#define RX0_ENABLE_MASK GENMASK(14, 13)
+#define RX0_ENABLE_SHIFT 13
+#define RX0_DISABLE_STATE 0x0
+#define RX0_SLEEP_STATE 0x1
+#define RX0_SNOOZE_STATE 0x2
+#define RX0_ENABLE_STATE 0x3
+
+#define WIZ_PLL_CTRL 0x1ff4
+#define PLL_ENABLE_OVL BIT(31)
+#define PLL_ENABLE_MASK GENMASK(30, 29)
+#define PLL_ENABLE_SHIFT 29
+#define PLL_DISABLE_STATE 0x0
+#define PLL_SLEEP_STATE 0x1
+#define PLL_SNOOZE_STATE 0x2
+#define PLL_ENABLE_STATE 0x3
+#define PLL_OK BIT(28)
+
+#define PLL_LOCK_TIME 1000 /* in milliseconds */
+#define SLEEP_TIME 100 /* in microseconds */
+
+#define LANE_USB3 0x0
+#define LANE_PCIE0_LANE0 0x1
+
+#define LANE_PCIE1_LANE0 0x0
+#define LANE_PCIE0_LANE1 0x1
+
+#define SERDES_NUM_CLOCKS 3
+
+/* SERDES control MMR bit offsets */
+#define SERDES_CTL_LANE_FUNC_SEL_SHIFT 0
+#define SERDES_CTL_LANE_FUNC_SEL_MASK GENMASK(1, 0)
+#define SERDES_CTL_CLK_SEL_SHIFT 4
+#define SERDES_CTL_CLK_SEL_MASK GENMASK(7, 4)
+
+/**
+ * struct serdes_am654_mux_clk_data - clock controller information structure
+ */
+struct serdes_am654_mux_clk_data {
+ struct regmap *regmap;
+ struct clk_bulk parents;
+};
+
+static int serdes_am654_mux_clk_probe(struct udevice *dev)
+{
+ struct serdes_am654_mux_clk_data *data = dev_get_priv(dev);
+ struct udevice *syscon;
+ struct regmap *regmap;
+ int ret;
+
+ debug("%s(dev=%s)\n", __func__, dev->name);
+
+ if (!data)
+ return -ENOMEM;
+
+ ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
+ "ti,serdes-clk", &syscon);
+ if (ret) {
+ dev_err(dev, "unable to find syscon device\n");
+ return ret;
+ }
+
+ regmap = syscon_get_regmap(syscon);
+ if (IS_ERR(regmap)) {
+ dev_err(dev, "Fail to get Syscon regmap\n");
+ return PTR_ERR(regmap);
+ }
+
+ data->regmap = regmap;
+
+ ret = clk_get_bulk(dev, &data->parents);
+ if (ret) {
+ dev_err(dev, "Failed to obtain parent clocks\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int mux_table[SERDES_NUM_CLOCKS][3] = {
+ /*
+ * The entries represent values for selecting between
+ * {left input, external reference clock, right input}
+ * Only one of Left Output or Right Output should be used since
+ * both left and right output clock uses the same bits and modifying
+ * one clock will impact the other.
+ */
+ { BIT(2), 0, BIT(0) }, /* Mux of CMU refclk */
+ { -1, BIT(3), BIT(1) }, /* Mux of Left Output */
+ { BIT(1), BIT(3) | BIT(1), -1 }, /* Mux of Right Output */
+};
+
+static int serdes_am654_mux_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct serdes_am654_mux_clk_data *data = dev_get_priv(clk->dev);
+ u32 val;
+ int i;
+
+ debug("%s(clk=%s, parent=%s)\n", __func__, clk->dev->name,
+ parent->dev->name);
+
+ /*
+ * Since we have the same device-tree node represent both the
+ * clock and serdes device, we have two devices associated with
+ * the serdes node. assigned-clocks for this node is processed twice,
+ * once for the clock device and another time for the serdes
+ * device. When it is processed for the clock device, it is before
+ * the probe for clock device has been called. We ignore this case
+ * and rely on assigned-clocks to be processed correctly for the
+ * serdes case.
+ */
+ if (!data->regmap)
+ return 0;
+
+ for (i = 0; i < data->parents.count; i++) {
+ if (clk_is_match(&data->parents.clks[i], parent))
+ break;
+ }
+
+ if (i >= data->parents.count)
+ return -EINVAL;
+
+ val = mux_table[clk->id][i];
+ val <<= SERDES_CTL_CLK_SEL_SHIFT;
+
+ regmap_update_bits(data->regmap, 0, SERDES_CTL_CLK_SEL_MASK, val);
+
+ return 0;
+}
+
+static struct clk_ops serdes_am654_mux_clk_ops = {
+ .set_parent = serdes_am654_mux_clk_set_parent,
+};
+
+U_BOOT_DRIVER(serdes_am654_mux_clk) = {
+ .name = "ti-serdes-am654-mux-clk",
+ .id = UCLASS_CLK,
+ .probe = serdes_am654_mux_clk_probe,
+ .priv_auto_alloc_size = sizeof(struct serdes_am654_mux_clk_data),
+ .ops = &serdes_am654_mux_clk_ops,
+};
+
+struct serdes_am654 {
+ struct regmap *regmap;
+ struct regmap *serdes_ctl;
+};
+
+static int serdes_am654_enable_pll(struct serdes_am654 *phy)
+{
+ u32 mask = PLL_ENABLE_OVL | PLL_ENABLE_MASK;
+ u32 val = PLL_ENABLE_OVL | (PLL_ENABLE_STATE << PLL_ENABLE_SHIFT);
+
+ regmap_update_bits(phy->regmap, WIZ_PLL_CTRL, mask, val);
+
+ return regmap_read_poll_timeout(phy->regmap, WIZ_PLL_CTRL, val,
+ val & PLL_OK, 1000, PLL_LOCK_TIME);
+}
+
+static void serdes_am654_disable_pll(struct serdes_am654 *phy)
+{
+ u32 mask = PLL_ENABLE_OVL | PLL_ENABLE_MASK;
+
+ regmap_update_bits(phy->regmap, WIZ_PLL_CTRL, mask, 0);
+}
+
+static int serdes_am654_enable_txrx(struct serdes_am654 *phy)
+{
+ u32 mask;
+ u32 val;
+
+ /* Enable TX */
+ mask = TX0_ENABLE_OVL | TX0_ENABLE_MASK;
+ val = TX0_ENABLE_OVL | (TX0_ENABLE_STATE << TX0_ENABLE_SHIFT);
+ regmap_update_bits(phy->regmap, WIZ_LANEXCTL_STS, mask, val);
+
+ /* Enable RX */
+ mask = RX0_ENABLE_OVL | RX0_ENABLE_MASK;
+ val = RX0_ENABLE_OVL | (RX0_ENABLE_STATE << RX0_ENABLE_SHIFT);
+ regmap_update_bits(phy->regmap, WIZ_LANEXCTL_STS, mask, val);
+
+ return 0;
+}
+
+static int serdes_am654_disable_txrx(struct serdes_am654 *phy)
+{
+ u32 mask;
+
+ /* Disable TX */
+ mask = TX0_ENABLE_OVL | TX0_ENABLE_MASK;
+ regmap_update_bits(phy->regmap, WIZ_LANEXCTL_STS, mask, 0);
+
+ /* Disable RX */
+ mask = RX0_ENABLE_OVL | RX0_ENABLE_MASK;
+ regmap_update_bits(phy->regmap, WIZ_LANEXCTL_STS, mask, 0);
+
+ return 0;
+}
+
+static int serdes_am654_power_on(struct phy *x)
+{
+ struct serdes_am654 *phy = dev_get_priv(x->dev);
+ int ret;
+ u32 val;
+
+ ret = serdes_am654_enable_pll(phy);
+ if (ret) {
+ dev_err(x->dev, "Failed to enable PLL\n");
+ return ret;
+ }
+
+ ret = serdes_am654_enable_txrx(phy);
+ if (ret) {
+ dev_err(x->dev, "Failed to enable TX RX\n");
+ return ret;
+ }
+
+ return regmap_read_poll_timeout(phy->regmap, COMLANE_R194, val,
+ val & CMU_OK_I_0, SLEEP_TIME,
+ PLL_LOCK_TIME);
+}
+
+static int serdes_am654_power_off(struct phy *x)
+{
+ struct serdes_am654 *phy = dev_get_priv(x->dev);
+
+ serdes_am654_disable_txrx(phy);
+ serdes_am654_disable_pll(phy);
+
+ return 0;
+}
+
+static int serdes_am654_init(struct phy *x)
+{
+ struct serdes_am654 *phy = dev_get_priv(x->dev);
+ u32 mask;
+ u32 val;
+
+ mask = CONFIG_VERSION_REG_MASK;
+ val = VERSION << CONFIG_VERSION_REG_SHIFT;
+ regmap_update_bits(phy->regmap, COMLANE_R138, mask, val);
+
+ val = CMU_MASTER_CDN_O;
+ regmap_update_bits(phy->regmap, CMU_R07C, val, val);
+
+ val = L1_MASTER_CDN_O;
+ regmap_update_bits(phy->regmap, COMLANE_R190, val, val);
+
+ return 0;
+}
+
+static int serdes_am654_reset(struct phy *x)
+{
+ struct serdes_am654 *phy = dev_get_priv(x->dev);
+ u32 val;
+
+ val = POR_EN;
+ regmap_update_bits(phy->regmap, SERDES_CTRL, val, val);
+ mdelay(1);
+ regmap_update_bits(phy->regmap, SERDES_CTRL, val, 0);
+
+ return 0;
+}
+
+static int serdes_am654_of_xlate(struct phy *x,
+ struct ofnode_phandle_args *args)
+{
+ struct serdes_am654 *phy = dev_get_priv(x->dev);
+
+ if (args->args_count != 2) {
+ dev_err(phy->dev, "Invalid DT PHY argument count: %d\n",
+ args->args_count);
+ return -EINVAL;
+ }
+
+ if (args->args[0] != PHY_TYPE_PCIE) {
+ dev_err(phy->dev, "Unrecognized PHY type: %d\n",
+ args->args[0]);
+ return -EINVAL;
+ }
+
+ x->id = args->args[0] | (args->args[1] << 16);
+
+ /* Setup mux mode using second argument */
+ regmap_update_bits(phy->serdes_ctl, 0, SERDES_CTL_LANE_FUNC_SEL_MASK,
+ args->args[1]);
+
+ return 0;
+}
+
+static int serdes_am654_bind(struct udevice *dev)
+{
+ int ret;
+
+ ret = device_bind_driver_to_node(dev->parent,
+ "ti-serdes-am654-mux-clk",
+ dev_read_name(dev), dev->node,
+ NULL);
+ if (ret) {
+ dev_err(dev, "%s: not able to bind clock driver\n", __func__);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int serdes_am654_probe(struct udevice *dev)
+{
+ struct serdes_am654 *phy = dev_get_priv(dev);
+ struct power_domain serdes_pwrdmn;
+ struct regmap *serdes_ctl;
+ struct regmap *map;
+ int ret;
+
+ ret = regmap_init_mem(dev_ofnode(dev), &map);
+ if (ret)
+ return ret;
+
+ phy->regmap = map;
+
+ serdes_ctl = syscon_regmap_lookup_by_phandle(dev, "ti,serdes-clk");
+ if (IS_ERR(serdes_ctl)) {
+ dev_err(dev, "unable to find syscon device\n");
+ return PTR_ERR(serdes_ctl);
+ }
+
+ phy->serdes_ctl = serdes_ctl;
+
+ ret = power_domain_get_by_index(dev, &serdes_pwrdmn, 0);
+ if (ret) {
+ dev_err(dev, "failed to get power domain\n");
+ return ret;
+ }
+
+ ret = power_domain_on(&serdes_pwrdmn);
+ if (ret) {
+ dev_err(dev, "Power domain on failed\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id serdes_am654_phy_ids[] = {
+ {
+ .compatible = "ti,phy-am654-serdes",
+ },
+};
+
+static const struct phy_ops serdes_am654_phy_ops = {
+ .reset = serdes_am654_reset,
+ .init = serdes_am654_init,
+ .power_on = serdes_am654_power_on,
+ .power_off = serdes_am654_power_off,
+ .of_xlate = serdes_am654_of_xlate,
+};
+
+U_BOOT_DRIVER(am654_serdes_phy) = {
+ .name = "am654_serdes_phy",
+ .id = UCLASS_PHY,
+ .of_match = serdes_am654_phy_ids,
+ .bind = serdes_am654_bind,
+ .ops = &serdes_am654_phy_ops,
+ .probe = serdes_am654_probe,
+ .priv_auto_alloc_size = sizeof(struct serdes_am654),
+};
diff --git a/drivers/pinctrl/aspeed/pinctrl_ast2500.c b/drivers/pinctrl/aspeed/pinctrl_ast2500.c
index ed333b9..a6e9c0d 100644
--- a/drivers/pinctrl/aspeed/pinctrl_ast2500.c
+++ b/drivers/pinctrl/aspeed/pinctrl_ast2500.c
@@ -58,6 +58,8 @@
{ "MDIO1", 3, (1 << 31) | (1 << 30) },
{ "MAC2LINK", 1, (1 << 1) },
{ "MDIO2", 5, (1 << 2) },
+ { "SD1", 5, (1 << 0) },
+ { "SD2", 5, (1 << 1) },
};
static int ast2500_pinctrl_get_groups_count(struct udevice *dev)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
index 938cc75..3004335 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
@@ -14,6 +14,7 @@
#include "pinctrl-mtk-common.h"
+#if CONFIG_IS_ENABLED(PINCONF)
/**
* struct mtk_drive_desc - the structure that holds the information
* of the driving current
@@ -39,6 +40,7 @@
[DRV_GRP3] = { 2, 8, 2, 2 },
[DRV_GRP4] = { 2, 16, 2, 1 },
};
+#endif
static const char *mtk_pinctrl_dummy_name = "_dummy";
diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig
index 61f93be..f2e67ca 100644
--- a/drivers/pinctrl/nxp/Kconfig
+++ b/drivers/pinctrl/nxp/Kconfig
@@ -89,6 +89,16 @@
only parses the 'fsl,pins' property and configure related
registers.
+config PINCTRL_MXS
+ bool "NXP MXS pinctrl driver"
+ depends on ARCH_MX28 && PINCTRL_FULL
+ help
+ Say Y here to enable the i.MX mxs pinctrl driver
+
+ This option provides a simple pinctrl driver for i.MX mxs SoC
+ familiy, e.g. i.MX28. This feature depends on device tree
+ configuration.
+
config PINCTRL_VYBRID
bool "Vybrid (vf610) pinctrl driver"
depends on ARCH_VF610 && PINCTRL_FULL
diff --git a/drivers/pinctrl/nxp/Makefile b/drivers/pinctrl/nxp/Makefile
index b340d94..b86448a 100644
--- a/drivers/pinctrl/nxp/Makefile
+++ b/drivers/pinctrl/nxp/Makefile
@@ -6,4 +6,5 @@
obj-$(CONFIG_PINCTRL_IMX_SCU) += pinctrl-scu.o
obj-$(CONFIG_PINCTRL_IMX8) += pinctrl-imx8.o
obj-$(CONFIG_PINCTRL_IMX8M) += pinctrl-imx8m.o
+obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
obj-$(CONFIG_PINCTRL_VYBRID) += pinctrl-vf610.o
diff --git a/drivers/pinctrl/nxp/pinctrl-mxs.c b/drivers/pinctrl/nxp/pinctrl-mxs.c
new file mode 100644
index 0000000..6f6ca84
--- /dev/null
+++ b/drivers/pinctrl/nxp/pinctrl-mxs.c
@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ */
+
+#include <common.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <dm/read.h>
+#include "pinctrl-mxs.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct mxs_pinctrl_priv {
+ void __iomem *base;
+ const struct mxs_regs *regs;
+};
+
+static unsigned long mxs_dt_node_to_map(struct udevice *conf)
+{
+ unsigned long config = 0;
+ int ret;
+ u32 val;
+
+ ret = dev_read_u32(conf, "fsl,drive-strength", &val);
+ if (!ret)
+ config = val | MA_PRESENT;
+
+ ret = dev_read_u32(conf, "fsl,voltage", &val);
+ if (!ret)
+ config |= val << VOL_SHIFT | VOL_PRESENT;
+
+ ret = dev_read_u32(conf, "fsl,pull-up", &val);
+ if (!ret)
+ config |= val << PULL_SHIFT | PULL_PRESENT;
+
+ return config;
+}
+
+static int mxs_pinctrl_set_mux(struct udevice *dev, u32 val, int bank, int pin)
+{
+ struct mxs_pinctrl_priv *iomux = dev_get_priv(dev);
+ int muxsel = MUXID_TO_MUXSEL(val), shift;
+ void __iomem *reg;
+
+ reg = iomux->base + iomux->regs->muxsel;
+ reg += bank * 0x20 + pin / 16 * 0x10;
+ shift = pin % 16 * 2;
+
+ mxs_pinctrl_rmwl(muxsel, 0x3, shift, reg);
+ debug(" mux %d,", muxsel);
+
+ return 0;
+}
+
+static int mxs_pinctrl_set_state(struct udevice *dev, struct udevice *conf)
+{
+ struct mxs_pinctrl_priv *iomux = dev_get_priv(dev);
+ u32 *pin_data, val, ma, vol, pull;
+ int npins, size, i, ret;
+ unsigned long config;
+
+ debug("\n%s: set state: %s\n", __func__, conf->name);
+
+ size = dev_read_size(conf, "fsl,pinmux-ids");
+ if (size < 0)
+ return size;
+
+ if (!size || size % sizeof(int)) {
+ dev_err(dev, "Invalid fsl,pinmux-ids property in %s\n",
+ conf->name);
+ return -EINVAL;
+ }
+
+ npins = size / sizeof(int);
+
+ pin_data = devm_kzalloc(dev, size, 0);
+ if (!pin_data)
+ return -ENOMEM;
+
+ ret = dev_read_u32_array(conf, "fsl,pinmux-ids", pin_data, npins);
+ if (ret) {
+ dev_err(dev, "Error reading pin data.\n");
+ devm_kfree(dev, pin_data);
+ return -EINVAL;
+ }
+
+ config = mxs_dt_node_to_map(conf);
+
+ ma = CONFIG_TO_MA(config);
+ vol = CONFIG_TO_VOL(config);
+ pull = CONFIG_TO_PULL(config);
+
+ for (i = 0; i < npins; i++) {
+ int pinid, bank, pin, shift;
+ void __iomem *reg;
+
+ val = pin_data[i];
+
+ pinid = MUXID_TO_PINID(val);
+ bank = PINID_TO_BANK(pinid);
+ pin = PINID_TO_PIN(pinid);
+
+ debug("(val: 0x%x) pin %d,", val, pinid);
+ /* Setup pinmux */
+ mxs_pinctrl_set_mux(dev, val, bank, pin);
+
+ debug(" ma: %d, vol: %d, pull: %d\n", ma, vol, pull);
+
+ /* drive */
+ reg = iomux->base + iomux->regs->drive;
+ reg += bank * 0x40 + pin / 8 * 0x10;
+
+ /* mA */
+ if (config & MA_PRESENT) {
+ shift = pin % 8 * 4;
+ mxs_pinctrl_rmwl(ma, 0x3, shift, reg);
+ }
+
+ /* vol */
+ if (config & VOL_PRESENT) {
+ shift = pin % 8 * 4 + 2;
+ if (vol)
+ writel(1 << shift, reg + SET);
+ else
+ writel(1 << shift, reg + CLR);
+ }
+
+ /* pull */
+ if (config & PULL_PRESENT) {
+ reg = iomux->base + iomux->regs->pull;
+ reg += bank * 0x10;
+ shift = pin;
+ if (pull)
+ writel(1 << shift, reg + SET);
+ else
+ writel(1 << shift, reg + CLR);
+ }
+ }
+
+ devm_kfree(dev, pin_data);
+ return 0;
+}
+
+static struct pinctrl_ops mxs_pinctrl_ops = {
+ .set_state = mxs_pinctrl_set_state,
+};
+
+static int mxs_pinctrl_probe(struct udevice *dev)
+{
+ struct mxs_pinctrl_priv *iomux = dev_get_priv(dev);
+
+ iomux->base = dev_read_addr_ptr(dev);
+ iomux->regs = (struct mxs_regs *)dev_get_driver_data(dev);
+
+ return 0;
+}
+
+static const struct mxs_regs imx23_regs = {
+ .muxsel = 0x100,
+ .drive = 0x200,
+ .pull = 0x400,
+};
+
+static const struct mxs_regs imx28_regs = {
+ .muxsel = 0x100,
+ .drive = 0x300,
+ .pull = 0x600,
+};
+
+static const struct udevice_id mxs_pinctrl_match[] = {
+ { .compatible = "fsl,imx23-pinctrl", .data = (ulong)&imx23_regs },
+ { .compatible = "fsl,imx28-pinctrl", .data = (ulong)&imx28_regs },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(mxs_pinctrl) = {
+ .name = "mxs-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(mxs_pinctrl_match),
+ .probe = mxs_pinctrl_probe,
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ .bind = dm_scan_fdt_dev,
+#endif
+ .priv_auto_alloc_size = sizeof(struct mxs_pinctrl_priv),
+ .ops = &mxs_pinctrl_ops,
+};
diff --git a/drivers/pinctrl/nxp/pinctrl-mxs.h b/drivers/pinctrl/nxp/pinctrl-mxs.h
new file mode 100644
index 0000000..a398e43
--- /dev/null
+++ b/drivers/pinctrl/nxp/pinctrl-mxs.h
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __PINCTRL_MXS_H
+#define __PINCTRL_MXS_H
+
+#include <dm/pinctrl.h>
+
+#define SET 0x4
+#define CLR 0x8
+#define TOG 0xc
+
+#define MXS_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
+#define PINID(bank, pin) ((bank) * 32 + (pin))
+
+/*
+ * pinmux-id bit field definitions
+ *
+ * bank: 15..12 (4)
+ * pin: 11..4 (8)
+ * muxsel: 3..0 (4)
+ */
+#define MUXID_TO_PINID(m) PINID((m) >> 12 & 0xf, (m) >> 4 & 0xff)
+#define MUXID_TO_MUXSEL(m) ((m) & 0xf)
+
+#define PINID_TO_BANK(p) ((p) >> 5)
+#define PINID_TO_PIN(p) ((p) % 32)
+
+/*
+ * pin config bit field definitions
+ *
+ * pull-up: 6..5 (2)
+ * voltage: 4..3 (2)
+ * mA: 2..0 (3)
+ *
+ * MSB of each field is presence bit for the config.
+ */
+#define PULL_PRESENT (1 << 6)
+#define PULL_SHIFT 5
+#define VOL_PRESENT (1 << 4)
+#define VOL_SHIFT 3
+#define MA_PRESENT (1 << 2)
+#define MA_SHIFT 0
+#define CONFIG_TO_PULL(c) ((c) >> PULL_SHIFT & 0x1)
+#define CONFIG_TO_VOL(c) ((c) >> VOL_SHIFT & 0x1)
+#define CONFIG_TO_MA(c) ((c) >> MA_SHIFT & 0x3)
+
+struct mxs_regs {
+ u16 muxsel;
+ u16 drive;
+ u16 pull;
+};
+
+static inline void mxs_pinctrl_rmwl(u32 value, u32 mask, u8 shift,
+ void __iomem *reg)
+{
+ clrsetbits_le32(reg, mask << shift, value << shift);
+}
+#endif /* __PINCTRL_MXS_H */
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index 9dec88c..1dfc97d 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -16,6 +16,7 @@
int offset; /* index of last configuration register */
u32 mask; /* configuration-value mask bits */
int width; /* configuration register bit width */
+ bool bits_per_mux;
};
struct single_fdt_pin_cfg {
@@ -23,6 +24,12 @@
fdt32_t val; /* configuration register value */
};
+struct single_fdt_bits_cfg {
+ fdt32_t reg; /* configuration register offset */
+ fdt32_t val; /* configuration register value */
+ fdt32_t mask; /* configuration register mask */
+};
+
/**
* single_configure_pins() - Configure pins based on FDT data
*
@@ -71,15 +78,53 @@
return 0;
}
+static int single_configure_bits(struct udevice *dev,
+ const struct single_fdt_bits_cfg *pins,
+ int size)
+{
+ struct single_pdata *pdata = dev->platdata;
+ int count = size / sizeof(struct single_fdt_bits_cfg);
+ phys_addr_t n, reg;
+ u32 val, mask;
+
+ for (n = 0; n < count; n++, pins++) {
+ reg = fdt32_to_cpu(pins->reg);
+ if ((reg < 0) || (reg > pdata->offset)) {
+ dev_dbg(dev, " invalid register offset 0x%pa\n", ®);
+ continue;
+ }
+ reg += pdata->base;
+
+ mask = fdt32_to_cpu(pins->mask);
+ val = fdt32_to_cpu(pins->val) & mask;
+
+ switch (pdata->width) {
+ case 16:
+ writew((readw(reg) & ~mask) | val, reg);
+ break;
+ case 32:
+ writel((readl(reg) & ~mask) | val, reg);
+ break;
+ default:
+ dev_warn(dev, "unsupported register width %i\n",
+ pdata->width);
+ continue;
+ }
+ dev_dbg(dev, " reg/val 0x%pa/0x%08x\n", ®, val);
+ }
+ return 0;
+}
static int single_set_state(struct udevice *dev,
struct udevice *config)
{
const void *fdt = gd->fdt_blob;
const struct single_fdt_pin_cfg *prop;
+ const struct single_fdt_bits_cfg *prop_bits;
int len;
prop = fdt_getprop(fdt, dev_of_offset(config), "pinctrl-single,pins",
&len);
+
if (prop) {
dev_dbg(dev, "configuring pins for %s\n", config->name);
if (len % sizeof(struct single_fdt_pin_cfg)) {
@@ -87,9 +132,24 @@
return -FDT_ERR_BADSTRUCTURE;
}
single_configure_pins(dev, prop, len);
- len = 0;
+ return 0;
}
+ /* pinctrl-single,pins not found so check for pinctrl-single,bits */
+ prop_bits = fdt_getprop(fdt, dev_of_offset(config),
+ "pinctrl-single,bits",
+ &len);
+ if (prop_bits) {
+ dev_dbg(dev, "configuring pins for %s\n", config->name);
+ if (len % sizeof(struct single_fdt_bits_cfg)) {
+ dev_dbg(dev, " invalid bits configuration in fdt\n");
+ return -FDT_ERR_BADSTRUCTURE;
+ }
+ single_configure_bits(dev, prop_bits, len);
+ return 0;
+ }
+
+ /* Neither 'pinctrl-single,pins' nor 'pinctrl-single,bits' were found */
return len;
}
@@ -119,6 +179,9 @@
pdata->mask = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"pinctrl-single,function-mask",
0xffffffff);
+ pdata->bits_per_mux = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
+ "pinctrl-single,bit-per-mux");
+
return 0;
}
diff --git a/drivers/pinctrl/pinctrl-stmfx.c b/drivers/pinctrl/pinctrl-stmfx.c
index 5431df9..0b5a043 100644
--- a/drivers/pinctrl/pinctrl-stmfx.c
+++ b/drivers/pinctrl/pinctrl-stmfx.c
@@ -231,23 +231,23 @@
switch (param) {
case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
case PIN_CONFIG_BIAS_DISABLE:
+ case PIN_CONFIG_DRIVE_PUSH_PULL:
+ ret = stmfx_pinctrl_set_type(dev, pin, 0);
+ break;
case PIN_CONFIG_BIAS_PULL_DOWN:
+ ret = stmfx_pinctrl_set_type(dev, pin, 1);
+ if (ret)
+ return ret;
ret = stmfx_pinctrl_set_pupd(dev, pin, 0);
break;
case PIN_CONFIG_BIAS_PULL_UP:
+ ret = stmfx_pinctrl_set_type(dev, pin, 1);
+ if (ret)
+ return ret;
ret = stmfx_pinctrl_set_pupd(dev, pin, 1);
break;
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
- if (dir == GPIOF_OUTPUT)
- ret = stmfx_pinctrl_set_type(dev, pin, 1);
- else
- ret = stmfx_pinctrl_set_type(dev, pin, 0);
- break;
- case PIN_CONFIG_DRIVE_PUSH_PULL:
- if (dir == GPIOF_OUTPUT)
- ret = stmfx_pinctrl_set_type(dev, pin, 0);
- else
- ret = stmfx_pinctrl_set_type(dev, pin, 1);
+ ret = stmfx_pinctrl_set_type(dev, pin, 1);
break;
case PIN_CONFIG_OUTPUT:
ret = stmfx_gpio_direction_output(plat->gpio, pin, arg);
diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c
index 43dbdd9..3a235ae 100644
--- a/drivers/pinctrl/pinctrl_stm32.c
+++ b/drivers/pinctrl/pinctrl_stm32.c
@@ -1,10 +1,11 @@
#include <common.h>
#include <dm.h>
-#include <dm/pinctrl.h>
#include <hwspinlock.h>
#include <asm/arch/gpio.h>
#include <asm/gpio.h>
#include <asm/io.h>
+#include <dm/lists.h>
+#include <dm/pinctrl.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -136,7 +137,7 @@
*/
*idx = stm32_offset_to_index(gpio_bank->gpio_dev,
selector - pin_count);
- if (*idx < 0)
+ if (IS_ERR_VALUE(*idx))
return NULL;
return gpio_bank->gpio_dev;
@@ -215,7 +216,7 @@
#endif
-int stm32_pinctrl_probe(struct udevice *dev)
+static int stm32_pinctrl_probe(struct udevice *dev)
{
struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
int ret;
@@ -364,6 +365,35 @@
return 0;
}
+static int stm32_pinctrl_bind(struct udevice *dev)
+{
+ ofnode node;
+ const char *name;
+ int ret;
+
+ dev_for_each_subnode(node, dev) {
+ debug("%s: bind %s\n", __func__, ofnode_get_name(node));
+
+ ofnode_get_property(node, "gpio-controller", &ret);
+ if (ret < 0)
+ continue;
+ /* Get the name of each gpio node */
+ name = ofnode_get_name(node);
+ if (!name)
+ return -EINVAL;
+
+ /* Bind each gpio node */
+ ret = device_bind_driver_to_node(dev, "gpio_stm32",
+ name, node, NULL);
+ if (ret)
+ return ret;
+
+ debug("%s: bind %s\n", __func__, name);
+ }
+
+ return 0;
+}
+
#if CONFIG_IS_ENABLED(PINCTRL_FULL)
static int stm32_pinctrl_set_state(struct udevice *dev, struct udevice *config)
{
@@ -433,7 +463,7 @@
.id = UCLASS_PINCTRL,
.of_match = stm32_pinctrl_ids,
.ops = &stm32_pinctrl_ops,
- .bind = dm_scan_fdt_dev,
+ .bind = stm32_pinctrl_bind,
.probe = stm32_pinctrl_probe,
.priv_auto_alloc_size = sizeof(struct stm32_pinctrl_priv),
};
diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig
index 0ffd7fc..4d3d68d 100644
--- a/drivers/pinctrl/renesas/Kconfig
+++ b/drivers/pinctrl/renesas/Kconfig
@@ -97,6 +97,16 @@
the GPIO definitions and pin control functions for each available
multiplex function.
+config PINCTRL_PFC_R8A77980
+ bool "Renesas RCar Gen3 R8A77980 pin control driver"
+ depends on PINCTRL_PFC
+ help
+ Support pin multiplexing control on Renesas RCar Gen3 R8A77980 SoCs.
+
+ The driver is controlled by a device tree node which contains both
+ the GPIO definitions and pin control functions for each available
+ multiplex function.
+
config PINCTRL_PFC_R8A77990
bool "Renesas RCar Gen3 R8A77990 pin control driver"
depends on PINCTRL_PFC
diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile
index e8703f6..a92f787 100644
--- a/drivers/pinctrl/renesas/Makefile
+++ b/drivers/pinctrl/renesas/Makefile
@@ -8,6 +8,7 @@
obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o
obj-$(CONFIG_PINCTRL_PFC_R8A77965) += pfc-r8a77965.o
obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o
+obj-$(CONFIG_PINCTRL_PFC_R8A77980) += pfc-r8a77980.o
obj-$(CONFIG_PINCTRL_PFC_R8A77990) += pfc-r8a77990.o
obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o
obj-$(CONFIG_PINCTRL_PFC_R7S72100) += pfc-r7s72100.o
diff --git a/drivers/pinctrl/renesas/pfc-r8a7790.c b/drivers/pinctrl/renesas/pfc-r8a7790.c
index ef23ca2..5e1502e 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7790.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7790.c
@@ -4745,7 +4745,7 @@
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
- { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
+ { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
GP_0_31_FN, FN_IP3_17_15,
GP_0_30_FN, FN_IP3_14_12,
GP_0_29_FN, FN_IP3_11_8,
@@ -4777,9 +4777,9 @@
GP_0_3_FN, FN_IP0_11_9,
GP_0_2_FN, FN_IP0_8_6,
GP_0_1_FN, FN_IP0_5_3,
- GP_0_0_FN, FN_IP0_2_0 }
+ GP_0_0_FN, FN_IP0_2_0 ))
},
- { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
+ { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
0, 0,
0, 0,
GP_1_29_FN, FN_IP6_13_11,
@@ -4811,9 +4811,9 @@
GP_1_3_FN, FN_IP3_28_26,
GP_1_2_FN, FN_IP3_25_23,
GP_1_1_FN, FN_IP3_22_20,
- GP_1_0_FN, FN_IP3_19_18, }
+ GP_1_0_FN, FN_IP3_19_18, ))
},
- { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
+ { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
0, 0,
0, 0,
GP_2_29_FN, FN_IP7_15_13,
@@ -4845,9 +4845,9 @@
GP_2_3_FN, FN_IP8_3_2,
GP_2_2_FN, FN_IP8_1_0,
GP_2_1_FN, FN_IP7_30_29,
- GP_2_0_FN, FN_IP7_28_27 }
+ GP_2_0_FN, FN_IP7_28_27 ))
},
- { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
+ { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
GP_3_31_FN, FN_IP11_21_18,
GP_3_30_FN, FN_IP11_17_15,
GP_3_29_FN, FN_IP11_14_13,
@@ -4879,9 +4879,9 @@
GP_3_3_FN, FN_IP9_3_2,
GP_3_2_FN, FN_IP9_1_0,
GP_3_1_FN, FN_IP8_30_29,
- GP_3_0_FN, FN_IP8_28 }
+ GP_3_0_FN, FN_IP8_28 ))
},
- { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
+ { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
GP_4_31_FN, FN_IP14_18_16,
GP_4_30_FN, FN_IP14_15_12,
GP_4_29_FN, FN_IP14_11_9,
@@ -4913,9 +4913,9 @@
GP_4_3_FN, FN_IP11_31_30,
GP_4_2_FN, FN_IP11_29_27,
GP_4_1_FN, FN_IP11_26_24,
- GP_4_0_FN, FN_IP11_23_22 }
+ GP_4_0_FN, FN_IP11_23_22 ))
},
- { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
+ { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
GP_5_31_FN, FN_IP7_24_22,
GP_5_30_FN, FN_IP7_21_19,
GP_5_29_FN, FN_IP7_18_16,
@@ -4947,10 +4947,11 @@
GP_5_3_FN, FN_IP14_30_28,
GP_5_2_FN, FN_IP14_27_25,
GP_5_1_FN, FN_IP14_24_22,
- GP_5_0_FN, FN_IP14_21_19 }
+ GP_5_0_FN, FN_IP14_21_19 ))
},
{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
- 1, 4, 4, 3, 4, 4, 3, 3, 3, 3) {
+ GROUP(1, 4, 4, 3, 4, 4, 3, 3, 3, 3),
+ GROUP(
/* IP0_31 [1] */
0, 0,
/* IP0_30_27 [4] */
@@ -4983,10 +4984,11 @@
0, 0, 0,
/* IP0_2_0 [3] */
FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
- 0, 0, 0, }
+ 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
- 2, 2, 2, 4, 4, 3, 3, 4, 4, 4) {
+ GROUP(2, 2, 2, 4, 4, 3, 3, 4, 4, 4),
+ GROUP(
/* IP1_31_30 [2] */
0, 0, 0, 0,
/* IP1_29_28 [2] */
@@ -5020,10 +5022,11 @@
/* IP1_3_0 [4] */
FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0,
FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, }
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
- 3, 3, 4, 4, 3, 3, 3, 3, 3, 3) {
+ GROUP(3, 3, 4, 4, 3, 3, 3, 3, 3, 3),
+ GROUP(
/* IP2_31_29 [3] */
0, 0, 0, 0, 0, 0, 0, 0,
/* IP2_28_26 [3] */
@@ -5049,10 +5052,11 @@
/* IP2_5_3 [3] */
FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0,
/* IP2_2_0 [3] */
- FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, }
+ FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
- 3, 3, 3, 3, 2, 3, 3, 4, 4, 4) {
+ GROUP(3, 3, 3, 3, 2, 3, 3, 4, 4, 4),
+ GROUP(
/* IP3_31_29 [3] */
FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
0, 0, 0,
@@ -5082,10 +5086,11 @@
/* IP3_3_0 [4] */
FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, }
+ 0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
- 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
+ GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
+ GROUP(
/* IP4_31_30 [2] */
0, 0, 0, 0,
/* IP4_29_27 [3] */
@@ -5115,10 +5120,11 @@
FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0,
/* IP4_2_0 [3] */
FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0,
- }
+ ))
},
{ PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
- 2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3) {
+ GROUP(2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3),
+ GROUP(
/* IP5_31_30 [2] */
0, 0, 0, 0,
/* IP5_29_27 [3] */
@@ -5152,10 +5158,11 @@
FN_INTC_EN0_N, FN_I2C1_SCL,
/* IP5_2_0 [3] */
FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
- FN_VI2_R3, 0, 0, }
+ FN_VI2_R3, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
- 3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) {
+ GROUP(3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3),
+ GROUP(
/* IP6_31_29 [3] */
FN_ETH_REF_CLK, 0, FN_HCTS0_N_E,
FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,
@@ -5188,10 +5195,11 @@
FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
/* IP6_2_0 [3] */
FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
- FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, }
+ FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
- 1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) {
+ GROUP(1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3),
+ GROUP(
/* IP7_31 [1] */
0, 0,
/* IP7_30_29 [2] */
@@ -5223,11 +5231,12 @@
FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0,
/* IP7_2_0 [3] */
FN_ETH_MDIO, 0, FN_HRTS0_N_E,
- FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, }
+ FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
- 1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2,
- 2, 2, 2, 2, 2, 2, 2) {
+ GROUP(1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2),
+ GROUP(
/* IP8_31 [1] */
0, 0,
/* IP8_30_29 [2] */
@@ -5264,10 +5273,11 @@
/* IP8_3_2 [2] */
FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0,
/* IP8_1_0 [2] */
- FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, }
+ FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
- 4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) {
+ GROUP(4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2),
+ GROUP(
/* IP9_31_28 [4] */
FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP,
FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D,
@@ -5299,10 +5309,11 @@
/* IP9_3_2 [2] */
FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0,
/* IP9_1_0 [2] */
- FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, }
+ FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
- 2, 4, 3, 4, 4, 4, 4, 3, 4) {
+ GROUP(2, 4, 3, 4, 4, 4, 4, 3, 4),
+ GROUP(
/* IP10_31_30 [2] */
0, 0, 0, 0,
/* IP10_29_26 [4] */
@@ -5338,10 +5349,11 @@
/* IP10_3_0 [4] */
FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
- FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, }
+ FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
- 2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) {
+ GROUP(2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4),
+ GROUP(
/* IP11_31_30 [2] */
FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0,
/* IP11_29_27 [3] */
@@ -5373,10 +5385,11 @@
/* IP11_3_0 [4] */
FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
- FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, }
+ FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
- 1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
+ GROUP(1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2),
+ GROUP(
/* IP12_31 [1] */
0, 0,
/* IP12_30_28 [3] */
@@ -5412,10 +5425,11 @@
/* IP12_3_2 [2] */
FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0,
/* IP12_1_0 [2] */
- FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, }
+ FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
- 1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3) {
+ GROUP(1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3),
+ GROUP(
/* IP13_31 [1] */
0, 0,
/* IP13_30_29 [2] */
@@ -5448,10 +5462,11 @@
FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP13_2_0 [3] */
FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
- FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, }
+ FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
- 1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3) {
+ GROUP(1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3),
+ GROUP(
/* IP14_30 [1] */
0, 0,
/* IP14_30_28 [3] */
@@ -5486,10 +5501,11 @@
/* IP14_2_0 [3] */
FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
- FN_REMOCON, 0, }
+ FN_REMOCON, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
- 2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3) {
+ GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3),
+ GROUP(
/* IP15_31_30 [2] */
0, 0, 0, 0,
/* IP15_29_28 [2] */
@@ -5521,10 +5537,11 @@
FN_IIC2_SCL, FN_I2C2_SCL, 0,
/* IP15_2_0 [3] */
FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
- FN_LCDOUT15, FN_SCIF_CLK_B, 0, }
+ FN_LCDOUT15, FN_SCIF_CLK_B, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
- 4, 4, 4, 4, 4, 4, 1, 1, 3, 3) {
+ GROUP(4, 4, 4, 4, 4, 4, 1, 1, 3, 3),
+ GROUP(
/* IP16_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@@ -5552,11 +5569,12 @@
FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 0,
/* IP16_2_0 [3] */
FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
- FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, }
+ FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
- 3, 2, 2, 3, 2, 1, 1, 1, 2, 1,
- 2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) {
+ GROUP(3, 2, 2, 3, 2, 1, 1, 1, 2, 1, 2, 1,
+ 1, 1, 1, 2, 1, 1, 2, 1, 1),
+ GROUP(
/* SEL_SCIF1 [3] */
FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
FN_SEL_SCIF1_4, 0, 0, 0,
@@ -5602,11 +5620,12 @@
/* SEL_SOF3 [1] */
FN_SEL_SOF3_0, FN_SEL_SOF3_1,
/* SEL_SOF0 [1] */
- FN_SEL_SOF0_0, FN_SEL_SOF0_1, }
+ FN_SEL_SOF0_0, FN_SEL_SOF0_1, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
- 3, 1, 1, 1, 2, 1, 2, 1, 2,
- 1, 1, 1, 3, 3, 2, 3, 2, 2) {
+ GROUP(3, 1, 1, 1, 2, 1, 2, 1, 2, 1, 1, 1,
+ 3, 3, 2, 3, 2, 2),
+ GROUP(
/* RESERVED [3] */
0, 0, 0, 0, 0, 0, 0, 0,
/* SEL_TMU1 [1] */
@@ -5644,11 +5663,11 @@
/* SEL_SIM [2] */
FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
/* SEL_SSI8 [2] */
- FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, }
+ FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
- 1, 1, 2, 4, 4, 2, 2,
- 4, 2, 3, 2, 3, 2) {
+ GROUP(1, 1, 2, 4, 4, 2, 2, 4, 2, 3, 2, 3, 2),
+ GROUP(
/* SEL_IICDVFS [1] */
FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
/* SEL_IIC0 [1] */
@@ -5679,7 +5698,7 @@
FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
FN_SEL_I2C2_4, 0, 0, 0,
/* SEL_I2C1 [2] */
- FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, }
+ FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, ))
},
{ },
};
diff --git a/drivers/pinctrl/renesas/pfc-r8a7791.c b/drivers/pinctrl/renesas/pfc-r8a7791.c
index 8166955..d6095d6 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7791.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7791.c
@@ -5431,7 +5431,7 @@
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
- { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
+ { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
GP_0_31_FN, FN_IP1_22_20,
GP_0_30_FN, FN_IP1_19_17,
GP_0_29_FN, FN_IP1_16_14,
@@ -5463,9 +5463,9 @@
GP_0_3_FN, FN_IP0_3,
GP_0_2_FN, FN_IP0_2,
GP_0_1_FN, FN_IP0_1,
- GP_0_0_FN, FN_IP0_0, }
+ GP_0_0_FN, FN_IP0_0, ))
},
- { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
+ { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -5497,9 +5497,9 @@
GP_1_3_FN, FN_IP2_2_0,
GP_1_2_FN, FN_IP1_31_29,
GP_1_1_FN, FN_IP1_28_26,
- GP_1_0_FN, FN_IP1_25_23, }
+ GP_1_0_FN, FN_IP1_25_23, ))
},
- { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
+ { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
GP_2_31_FN, FN_IP6_7_6,
GP_2_30_FN, FN_IP6_5_3,
GP_2_29_FN, FN_IP6_2_0,
@@ -5531,9 +5531,9 @@
GP_2_3_FN, FN_IP4_4_2,
GP_2_2_FN, FN_IP4_1_0,
GP_2_1_FN, FN_IP3_30_28,
- GP_2_0_FN, FN_IP3_27_25 }
+ GP_2_0_FN, FN_IP3_27_25 ))
},
- { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
+ { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
GP_3_31_FN, FN_IP9_18_17,
GP_3_30_FN, FN_IP9_16,
GP_3_29_FN, FN_IP9_15_13,
@@ -5565,9 +5565,9 @@
GP_3_3_FN, FN_IP7_12_11,
GP_3_2_FN, FN_IP7_10_9,
GP_3_1_FN, FN_IP7_8_6,
- GP_3_0_FN, FN_IP7_5_3 }
+ GP_3_0_FN, FN_IP7_5_3 ))
},
- { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
+ { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
GP_4_31_FN, FN_IP15_5_4,
GP_4_30_FN, FN_IP15_3_2,
GP_4_29_FN, FN_IP15_1_0,
@@ -5599,9 +5599,9 @@
GP_4_3_FN, FN_IP9_24_23,
GP_4_2_FN, FN_IP9_22_21,
GP_4_1_FN, FN_IP9_20_19,
- GP_4_0_FN, FN_VI0_CLK }
+ GP_4_0_FN, FN_VI0_CLK ))
},
- { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
+ { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
GP_5_31_FN, FN_IP3_24_22,
GP_5_30_FN, FN_IP13_9_7,
GP_5_29_FN, FN_IP13_6_5,
@@ -5633,9 +5633,9 @@
GP_5_3_FN, FN_IP11_18_17,
GP_5_2_FN, FN_IP11_16_15,
GP_5_1_FN, FN_IP11_14_12,
- GP_5_0_FN, FN_IP11_11_9 }
+ GP_5_0_FN, FN_IP11_11_9 ))
},
- { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
+ { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP(
GP_6_31_FN, FN_DU0_DOTCLKIN,
GP_6_30_FN, FN_USB1_OVC,
GP_6_29_FN, FN_IP14_31_29,
@@ -5667,9 +5667,9 @@
GP_6_3_FN, FN_IP13_13,
GP_6_2_FN, FN_IP13_12,
GP_6_1_FN, FN_IP13_11,
- GP_6_0_FN, FN_IP13_10 }
+ GP_6_0_FN, FN_IP13_10 ))
},
- { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) {
+ { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -5701,11 +5701,12 @@
GP_7_3_FN, FN_IP15_26_24,
GP_7_2_FN, FN_IP15_23_21,
GP_7_1_FN, FN_IP15_20_18,
- GP_7_0_FN, FN_IP15_17_15 }
+ GP_7_0_FN, FN_IP15_17_15 ))
},
{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
- 1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1) {
+ GROUP(1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
/* IP0_31 [1] */
0, 0,
/* IP0_30_29 [2] */
@@ -5760,10 +5761,11 @@
/* IP0_1 [1] */
FN_D1, 0,
/* IP0_0 [1] */
- FN_D0, 0, }
+ FN_D0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
- 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
+ GROUP(3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2),
+ GROUP(
/* IP1_31_29 [3] */
FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C,
0, 0, 0,
@@ -5796,10 +5798,11 @@
FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL, 0,
/* IP1_1_0 [2] */
FN_A7, FN_MSIOF1_SYNC,
- 0, 0, }
+ 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
- 2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3) {
+ GROUP(2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3),
+ GROUP(
/* IP2_31_30 [2] */
0, 0, 0, 0,
/* IP2_29_27 [3] */
@@ -5832,10 +5835,11 @@
FN_A20, FN_SPCLK, 0, 0,
/* IP2_2_0 [3] */
FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, 0,
- FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, }
+ FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
- 1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3) {
+ GROUP(1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3),
+ GROUP(
/* IP3_31 [1] */
0, 0,
/* IP3_30_28 [3] */
@@ -5870,10 +5874,12 @@
FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 0,
/* IP3_2_0 [3] */
FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, 0, FN_EX_WAIT2,
- 0, 0, 0, }
+ 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
- 1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2, 3, 3, 2) {
+ GROUP(1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2,
+ 3, 3, 2),
+ GROUP(
/* IP4_31 [1] */
0, 0,
/* IP4_30_28 [3] */
@@ -5912,10 +5918,12 @@
FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
0, 0, 0,
/* IP4_1_0 [2] */
- FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C, }
+ FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C,
+ ))
},
{ PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
- 3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3) {
+ GROUP(3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3),
+ GROUP(
/* IP5_31_29 [3] */
FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
0, 0, 0, 0, 0,
@@ -5950,10 +5958,11 @@
/* IP5_2_0 [3] */
FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
FN_MSIOF2_TXD_D, FN_VI1_R3_B,
- 0, 0, }
+ 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
- 2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3) {
+ GROUP(2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3),
+ GROUP(
/* IP6_31_30 [2] */
0, 0, 0, 0,
/* IP6_29_27 [3] */
@@ -5990,10 +5999,11 @@
/* IP6_2_0 [3] */
FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,
- 0, 0, }
+ 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
- 2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3) {
+ GROUP(2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3),
+ GROUP(
/* IP7_31_30 [2] */
0, 0, 0, 0,
/* IP7_29_27 [3] */
@@ -6031,10 +6041,11 @@
/* IP7_2_0 [3] */
FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
FN_SCIF_CLK_B, FN_GPS_MAG_D,
- 0, 0, }
+ 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
- 1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3) {
+ GROUP(1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3),
+ GROUP(
/* IP8_31 [1] */
0, 0,
/* IP8_30_28 [3] */
@@ -6074,10 +6085,12 @@
0, 0,
/* IP8_2_0 [3] */
FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, 0, FN_SSI_WS78_B,
- 0, 0, 0, }
+ 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
- 3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3, 1, 1, 3, 3) {
+ GROUP(3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3,
+ 1, 1, 3, 3),
+ GROUP(
/* IP9_31_29 [3] */
FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL,
FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0,
@@ -6117,10 +6130,11 @@
0, 0, 0,
/* IP9_2_0 [3] */
FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD,
- 0, 0, 0, }
+ 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
- 3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3) {
+ GROUP(3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3),
+ GROUP(
/* IP10_31_29 [3] */
FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D,
0, 0, 0,
@@ -6154,11 +6168,12 @@
FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0,
/* IP10_2_0 [3] */
FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA,
- FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, }
+ FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
- 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
- 3, 3, 3, 3, 3) {
+ GROUP(2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2,
+ 2, 3, 3, 3, 3, 3),
+ GROUP(
/* IP11_31_30 [2] */
FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C, 0,
/* IP11_29_28 [2] */
@@ -6201,10 +6216,11 @@
0, 0, 0,
/* IP11_2_0 [3] */
FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C,
- FN_I2C1_SDA_D, 0, 0, 0, }
+ FN_I2C1_SDA_D, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
- 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) {
+ GROUP(2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2),
+ GROUP(
/* IP12_31_30 [2] */
0, 0, 0, 0,
/* IP12_29_27 [3] */
@@ -6242,11 +6258,12 @@
/* IP12_3_2 [2] */
FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA,
/* IP12_1_0 [2] */
- FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, }
+ FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, ))
},
{ PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
- 1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, 1, 1, 1,
- 3, 2, 2, 3) {
+ GROUP(1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1,
+ 1, 1, 1, 3, 2, 2, 3),
+ GROUP(
/* IP13_31 [1] */
0, 0,
/* IP13_30_28 [3] */
@@ -6293,10 +6310,12 @@
/* IP13_2_0 [3] */
FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
FN_ADICLK_B, FN_MSIOF0_SS1_C,
- 0, 0, 0, }
+ 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
- 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 2) {
+ GROUP(3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1,
+ 1, 1, 2),
+ GROUP(
/* IP14_31_29 [3] */
FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B, 0,
@@ -6336,10 +6355,11 @@
/* IP14_2 [1] */
FN_SD2_CLK, FN_MMC_CLK,
/* IP14_1_0 [2] */
- FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 0, }
+ FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
- 2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2) {
+ GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2),
+ GROUP(
/* IP15_31_30 [2] */
0, 0, 0, 0,
/* IP15_29_27 [3] */
@@ -6377,10 +6397,11 @@
/* IP15_3_2 [2] */
FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0,
/* IP15_1_0 [2] */
- FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, }
+ FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
- 4, 4, 4, 4, 4, 2, 2, 2, 3, 3) {
+ GROUP(4, 4, 4, 4, 4, 2, 2, 2, 3, 3),
+ GROUP(
/* IP16_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@@ -6409,11 +6430,12 @@
/* IP16_2_0 [3] */
FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B,
FN_GLO_SDATA_C, FN_VI1_DATA6_C,
- 0, 0, 0, }
+ 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
- 1, 2, 2, 2, 3, 2, 1, 1, 1, 1,
- 3, 2, 2, 2, 1, 2, 2, 2) {
+ GROUP(1, 2, 2, 2, 3, 2, 1, 1, 1, 1, 3, 2,
+ 2, 2, 1, 2, 2, 2),
+ GROUP(
/* RESERVED [1] */
0, 0,
/* SEL_SCIF1 [2] */
@@ -6454,11 +6476,12 @@
/* SEL_TSIF0 [2] */
FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
/* SEL_SOF0 [2] */
- FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, }
+ FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
- 3, 1, 1, 3, 2, 1, 1, 2, 2,
- 1, 3, 2, 1, 2, 2, 2, 1, 1, 1) {
+ GROUP(3, 1, 1, 3, 2, 1, 1, 2, 2, 1, 3, 2,
+ 1, 2, 2, 2, 1, 1, 1),
+ GROUP(
/* SEL_SCIF0 [3] */
FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
@@ -6502,11 +6525,12 @@
/* RESERVED [1] */
0, 0,
/* SEL_SSI8 [1] */
- FN_SEL_SSI8_0, FN_SEL_SSI8_1, }
+ FN_SEL_SSI8_0, FN_SEL_SSI8_1, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
- 2, 2, 2, 2, 2, 2, 2, 2,
- 1, 1, 2, 2, 3, 2, 2, 2, 1) {
+ GROUP(2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 2, 2,
+ 3, 2, 2, 2, 1),
+ GROUP(
/* SEL_HSCIF2 [2] */
FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
@@ -6544,11 +6568,12 @@
/* RESERVED [2] */
0, 0, 0, 0,
/* RESERVED [1] */
- 0, 0, }
+ 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
- 3, 2, 2, 1, 1, 1, 1, 3, 2,
- 2, 3, 1, 1, 1, 2, 2, 2, 2) {
+ GROUP(3, 2, 2, 1, 1, 1, 1, 3, 2, 2, 3, 1,
+ 1, 1, 2, 2, 2, 2),
+ GROUP(
/* SEL_SOF1 [3] */
FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
FN_SEL_SOF1_4,
@@ -6590,7 +6615,7 @@
/* RESERVED [2] */
0, 0, 0, 0,
/* RESERVED [2] */
- 0, 0, 0, 0, }
+ 0, 0, 0, 0, ))
},
{ },
};
diff --git a/drivers/pinctrl/renesas/pfc-r8a7792.c b/drivers/pinctrl/renesas/pfc-r8a7792.c
index 95bb523..1c90412 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7792.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7792.c
@@ -1991,7 +1991,7 @@
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
- { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
+ { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -2023,9 +2023,9 @@
GP_0_3_FN, FN_IP0_3,
GP_0_2_FN, FN_IP0_2,
GP_0_1_FN, FN_IP0_1,
- GP_0_0_FN, FN_IP0_0 }
+ GP_0_0_FN, FN_IP0_0 ))
},
- { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
+ { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -2057,9 +2057,9 @@
GP_1_3_FN, FN_IP1_8,
GP_1_2_FN, FN_IP1_7,
GP_1_1_FN, FN_IP1_6,
- GP_1_0_FN, FN_IP1_5, }
+ GP_1_0_FN, FN_IP1_5, ))
},
- { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
+ { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
GP_2_31_FN, FN_A15,
GP_2_30_FN, FN_A14,
GP_2_29_FN, FN_A13,
@@ -2091,9 +2091,9 @@
GP_2_3_FN, FN_D3,
GP_2_2_FN, FN_D2,
GP_2_1_FN, FN_D1,
- GP_2_0_FN, FN_D0 }
+ GP_2_0_FN, FN_D0 ))
},
- { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
+ { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -2125,9 +2125,9 @@
GP_3_3_FN, FN_A19,
GP_3_2_FN, FN_A18,
GP_3_1_FN, FN_A17,
- GP_3_0_FN, FN_A16 }
+ GP_3_0_FN, FN_A16 ))
},
- { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
+ { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -2159,9 +2159,9 @@
GP_4_3_FN, FN_VI0_VSYNC_N,
GP_4_2_FN, FN_VI0_HSYNC_N,
GP_4_1_FN, FN_VI0_CLKENB,
- GP_4_0_FN, FN_VI0_CLK }
+ GP_4_0_FN, FN_VI0_CLK ))
},
- { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
+ { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -2193,9 +2193,9 @@
GP_5_3_FN, FN_VI1_VSYNC_N,
GP_5_2_FN, FN_VI1_HSYNC_N,
GP_5_1_FN, FN_VI1_CLKENB,
- GP_5_0_FN, FN_VI1_CLK }
+ GP_5_0_FN, FN_VI1_CLK ))
},
- { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
+ { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -2227,9 +2227,9 @@
GP_6_3_FN, FN_IP2_3,
GP_6_2_FN, FN_IP2_2,
GP_6_1_FN, FN_IP2_1,
- GP_6_0_FN, FN_IP2_0 }
+ GP_6_0_FN, FN_IP2_0 ))
},
- { PINMUX_CFG_REG("GPSR7", 0xE6060020, 32, 1) {
+ { PINMUX_CFG_REG("GPSR7", 0xE6060020, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -2261,9 +2261,9 @@
GP_7_3_FN, FN_IP3_3,
GP_7_2_FN, FN_IP3_2,
GP_7_1_FN, FN_IP3_1,
- GP_7_0_FN, FN_IP3_0 }
+ GP_7_0_FN, FN_IP3_0 ))
},
- { PINMUX_CFG_REG("GPSR8", 0xE6060024, 32, 1) {
+ { PINMUX_CFG_REG("GPSR8", 0xE6060024, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -2295,9 +2295,9 @@
GP_8_3_FN, FN_IP4_3_2,
GP_8_2_FN, FN_IP4_1,
GP_8_1_FN, FN_IP4_0,
- GP_8_0_FN, FN_VI4_CLK }
+ GP_8_0_FN, FN_VI4_CLK ))
},
- { PINMUX_CFG_REG("GPSR9", 0xE6060028, 32, 1) {
+ { PINMUX_CFG_REG("GPSR9", 0xE6060028, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -2329,9 +2329,9 @@
GP_9_3_FN, FN_IP5_2,
GP_9_2_FN, FN_IP5_1,
GP_9_1_FN, FN_IP5_0,
- GP_9_0_FN, FN_VI5_CLK }
+ GP_9_0_FN, FN_VI5_CLK ))
},
- { PINMUX_CFG_REG("GPSR10", 0xE606002C, 32, 1) {
+ { PINMUX_CFG_REG("GPSR10", 0xE606002C, 32, 1, GROUP(
GP_10_31_FN, FN_CAN1_RX,
GP_10_30_FN, FN_CAN1_TX,
GP_10_29_FN, FN_CAN_CLK,
@@ -2363,9 +2363,9 @@
GP_10_3_FN, FN_IP6_2,
GP_10_2_FN, FN_HRTS0_N,
GP_10_1_FN, FN_IP6_1,
- GP_10_0_FN, FN_IP6_0 }
+ GP_10_0_FN, FN_IP6_0 ))
},
- { PINMUX_CFG_REG("GPSR11", 0xE6060030, 32, 1) {
+ { PINMUX_CFG_REG("GPSR11", 0xE6060030, 32, 1, GROUP(
0, 0,
0, 0,
GP_11_29_FN, FN_AVS2,
@@ -2397,13 +2397,14 @@
GP_11_3_FN, FN_IP7_6,
GP_11_2_FN, FN_IP7_5_4,
GP_11_1_FN, FN_IP7_3_2,
- GP_11_0_FN, FN_IP7_1_0 }
+ GP_11_0_FN, FN_IP7_1_0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
- 4, 4,
- 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1) {
+ GROUP(4, 4,
+ 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
/* IP0_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP0_27_24 [4] */
@@ -2455,13 +2456,14 @@
/* IP0_1 [1] */
FN_DU0_DR1_DATA1, 0,
/* IP0_0 [1] */
- FN_DU0_DR0_DATA0, 0 }
+ FN_DU0_DR0_DATA0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
- 4, 4,
- 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1) {
+ GROUP(4, 4,
+ 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
/* IP1_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP1_27_24 [4] */
@@ -2513,13 +2515,14 @@
/* IP1_1 [1] */
FN_DU0_EXVSYNC_DU0_VSYNC, 0,
/* IP1_0 [1] */
- FN_DU0_EXHSYNC_DU0_HSYNC, 0 }
+ FN_DU0_EXHSYNC_DU0_HSYNC, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
- 4, 4,
- 4, 3, 1,
- 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1) {
+ GROUP(4, 4,
+ 4, 3, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
/* IP2_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP2_27_24 [4] */
@@ -2561,13 +2564,14 @@
/* IP2_1 [1] */
FN_VI2_CLKENB, FN_AVB_RX_DV,
/* IP2_0 [1] */
- FN_VI2_CLK, FN_AVB_RX_CLK }
+ FN_VI2_CLK, FN_AVB_RX_CLK ))
},
{ PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
- 4, 4,
- 4, 4,
- 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1) {
+ GROUP(4, 4,
+ 4, 4,
+ 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
/* IP3_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP3_27_24 [4] */
@@ -2607,12 +2611,13 @@
/* IP3_1 [1] */
FN_VI3_CLKENB, FN_AVB_TXD4,
/* IP3_0 [1] */
- FN_VI3_CLK, FN_AVB_TX_CLK }
+ FN_VI3_CLK, FN_AVB_TX_CLK ))
},
{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
- 4, 3, 1,
- 1, 1, 1, 2, 2, 2,
- 2, 2, 2, 2, 2, 1, 2, 1, 1) {
+ GROUP(4, 3, 1,
+ 1, 1, 1, 2, 2, 2,
+ 2, 2, 2, 2, 2, 1, 2, 1, 1),
+ GROUP(
/* IP4_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP4_27_25 [3] */
@@ -2648,13 +2653,14 @@
/* IP4_1 [1] */
FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5,
/* IP4_0 [1] */
- FN_VI4_CLKENB, FN_VI0_D12_G4_Y4 }
+ FN_VI4_CLKENB, FN_VI0_D12_G4_Y4 ))
},
{ PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
- 4, 4,
- 4, 4,
- 4, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1) {
+ GROUP(4, 4,
+ 4, 4,
+ 4, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
/* IP5_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP5_27_24 [4] */
@@ -2688,13 +2694,14 @@
/* IP5_1 [1] */
FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B,
/* IP5_0 [1] */
- FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B }
+ FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B ))
},
{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
- 4, 4,
- 4, 1, 2, 1,
- 2, 2, 2, 2,
- 1, 1, 1, 1, 1, 1, 1, 1) {
+ GROUP(4, 4,
+ 4, 1, 2, 1,
+ 2, 2, 2, 2,
+ 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
/* IP6_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP6_27_24 [4] */
@@ -2730,13 +2737,14 @@
/* IP6_1 [1] */
FN_MSIOF0_SYNC, FN_HCTS0_N,
/* IP6_0 [1] */
- FN_MSIOF0_SCK, FN_HSCK0 }
+ FN_MSIOF0_SCK, FN_HSCK0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
- 4, 4,
- 3, 1, 1, 1, 1, 1,
- 2, 2, 2, 2,
- 1, 1, 2, 2, 2) {
+ GROUP(4, 4,
+ 3, 1, 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ 1, 1, 2, 2, 2),
+ GROUP(
/* IP7_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP7_27_24 [4] */
@@ -2770,7 +2778,7 @@
/* IP7_3_2 [2] */
FN_PWM1, FN_TCLK2, FN_FSO_CFE_1, 0,
/* IP7_1_0 [2] */
- FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0 }
+ FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0 ))
},
{ },
};
diff --git a/drivers/pinctrl/renesas/pfc-r8a7794.c b/drivers/pinctrl/renesas/pfc-r8a7794.c
index 657ebca..91ac815 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7794.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7794.c
@@ -4619,7 +4619,7 @@
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
- { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
+ { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
GP_0_31_FN, FN_IP2_17_16,
GP_0_30_FN, FN_IP2_15_14,
GP_0_29_FN, FN_IP2_13_12,
@@ -4651,9 +4651,9 @@
GP_0_3_FN, FN_IP0_27_26,
GP_0_2_FN, FN_IP0_25,
GP_0_1_FN, FN_IP0_24,
- GP_0_0_FN, FN_IP0_23_22, }
+ GP_0_0_FN, FN_IP0_23_22, ))
},
- { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
+ { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -4685,9 +4685,9 @@
GP_1_3_FN, FN_IP2_29_27,
GP_1_2_FN, FN_IP2_26_24,
GP_1_1_FN, FN_IP2_23_21,
- GP_1_0_FN, FN_IP2_20_18, }
+ GP_1_0_FN, FN_IP2_20_18, ))
},
- { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
+ { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
GP_2_31_FN, FN_IP6_7_6,
GP_2_30_FN, FN_IP6_5_4,
GP_2_29_FN, FN_IP6_3_2,
@@ -4719,9 +4719,9 @@
GP_2_3_FN, FN_IP4_11_10,
GP_2_2_FN, FN_IP4_9_8,
GP_2_1_FN, FN_IP4_7_5,
- GP_2_0_FN, FN_IP4_4_2 }
+ GP_2_0_FN, FN_IP4_4_2 ))
},
- { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
+ { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
GP_3_31_FN, FN_IP8_22_20,
GP_3_30_FN, FN_IP8_19_17,
GP_3_29_FN, FN_IP8_16_15,
@@ -4753,9 +4753,9 @@
GP_3_3_FN, FN_IP6_11,
GP_3_2_FN, FN_IP6_10,
GP_3_1_FN, FN_IP6_9,
- GP_3_0_FN, FN_IP6_8 }
+ GP_3_0_FN, FN_IP6_8 ))
},
- { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
+ { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
GP_4_31_FN, FN_IP11_17_16,
GP_4_30_FN, FN_IP11_15_14,
GP_4_29_FN, FN_IP11_13_11,
@@ -4787,9 +4787,9 @@
GP_4_3_FN, FN_IP9_2_0,
GP_4_2_FN, FN_IP8_31_29,
GP_4_1_FN, FN_IP8_28_26,
- GP_4_0_FN, FN_IP8_25_23 }
+ GP_4_0_FN, FN_IP8_25_23 ))
},
- { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
+ { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -4821,9 +4821,9 @@
GP_5_3_FN, FN_IP11_29_27,
GP_5_2_FN, FN_IP11_26_24,
GP_5_1_FN, FN_IP11_23_21,
- GP_5_0_FN, FN_IP11_20_18 }
+ GP_5_0_FN, FN_IP11_20_18 ))
},
- { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
+ { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -4855,11 +4855,12 @@
GP_6_3_FN, FN_SD0_DATA1,
GP_6_2_FN, FN_SD0_DATA0,
GP_6_1_FN, FN_SD0_CMD,
- GP_6_0_FN, FN_SD0_CLK }
+ GP_6_0_FN, FN_SD0_CLK ))
},
{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
- 2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1,
- 2, 1, 1, 1, 1, 1, 1, 1, 1) {
+ GROUP(2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1,
+ 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
/* IP0_31_30 [2] */
FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0,
/* IP0_29_28 [2] */
@@ -4909,11 +4910,12 @@
/* IP0_1 [1] */
0, 0,
/* IP0_0 [1] */
- FN_SD1_CD, FN_CAN0_RX, }
+ FN_SD1_CD, FN_CAN0_RX, ))
},
{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
- 2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 2, 2, 3, 2, 2,
- 2, 2) {
+ GROUP(2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 2, 2,
+ 3, 2, 2, 2, 2),
+ GROUP(
/* IP1_31_30 [2] */
FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
/* IP1_29_28 [2] */
@@ -4949,10 +4951,11 @@
/* IP1_3_2 [2] */
FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B,
/* IP1_1_0 [2] */
- FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, 0, }
+ FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
- 2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2) {
+ GROUP(2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2),
+ GROUP(
/* IP2_31_30 [2] */
FN_A20, FN_SPCLK, 0, 0,
/* IP2_29_27 [3] */
@@ -4984,10 +4987,12 @@
/* IP2_3_2 [2] */
FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B, 0,
/* IP2_1_0 [2] */
- FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, 0, }
+ FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
- 1, 1, 3, 3, 3, 3, 3, 2, 1, 1, 1, 2, 2, 2, 2, 2) {
+ GROUP(1, 1, 3, 3, 3, 3, 3, 2, 1, 1, 1, 2,
+ 2, 2, 2, 2),
+ GROUP(
/* IP3_31 [1] */
FN_RD_WR_N, FN_ATAG1_N,
/* IP3_30 [1] */
@@ -5024,10 +5029,11 @@
/* IP3_3_2 [2] */
FN_A22, FN_MISO_IO1, 0, FN_ATADIR1_N,
/* IP3_1_0 [2] */
- FN_A21, FN_MOSI_IO0, 0, 0, }
+ FN_A21, FN_MOSI_IO0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
- 2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2) {
+ GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2),
+ GROUP(
/* IP4_31_30 [2] */
FN_DU0_DG4, FN_LCDOUT12, 0, 0,
/* IP4_29_28 [2] */
@@ -5059,10 +5065,12 @@
FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D,
0, 0, 0, 0,
/* IP4_1_0 [2] */
- FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, 0, }
+ FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
- 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 2, 2, 2) {
+ GROUP(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3,
+ 2, 2, 2),
+ GROUP(
/* IP5_31_30 [2] */
FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, 0, 0,
/* IP5_29_28 [2] */
@@ -5094,11 +5102,12 @@
/* IP5_3_2 [2] */
FN_DU0_DG6, FN_LCDOUT14, 0, 0,
/* IP5_1_0 [2] */
- FN_DU0_DG5, FN_LCDOUT13, 0, 0, }
+ FN_DU0_DG5, FN_LCDOUT13, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
- 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
- 2, 2) {
+ GROUP(3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 2, 2, 2, 2),
+ GROUP(
/* IP6_31_29 [3] */
FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D,
FN_AVB_TX_CLK, FN_ADIDATA, 0, 0,
@@ -5140,10 +5149,11 @@
FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, 0,
0,
/* IP6_1_0 [2] */
- FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 0, 0, }
+ FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
- 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
+ GROUP(1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
+ GROUP(
/* IP7_31 [1] */
FN_DREQ0_N, FN_SCIFB1_RXD,
/* IP7_30 [1] */
@@ -5177,10 +5187,11 @@
FN_AVB_TXD1, FN_ADICLK, 0, 0,
/* IP7_2_0 [3] */
FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D,
- FN_AVB_TXD0, FN_ADICS_SAMP, 0, 0, }
+ FN_AVB_TXD0, FN_ADICS_SAMP, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
- 3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3) {
+ GROUP(3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3),
+ GROUP(
/* IP8_31_29 [3] */
FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2,
0, FN_TS_SDEN_D, FN_FMCLK_C, 0,
@@ -5212,10 +5223,11 @@
FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0,
/* IP8_2_0 [3] */
FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E,
- FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, }
+ FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
- 1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3) {
+ GROUP(1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3),
+ GROUP(
/* IP9_31 [1] */
0, 0,
/* IP9_30_28 [3] */
@@ -5248,10 +5260,11 @@
0, FN_TPUTO1_C, 0, 0,
/* IP9_2_0 [3] */
FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3,
- 0, FN_TS_SPSYNC_D, FN_FMIN_C, 0, }
+ 0, FN_TS_SPSYNC_D, FN_FMIN_C, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
- 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
+ GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
+ GROUP(
/* IP10_31_30 [2] */
FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, 0,
/* IP10_29_27 [3] */
@@ -5283,10 +5296,11 @@
0, 0, 0, 0,
/* IP10_2_0 [3] */
FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B,
- 0, 0, 0, 0, }
+ 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
- 2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3) {
+ GROUP(2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3),
+ GROUP(
/* IP11_31_30 [2] */
0, 0, 0, 0,
/* IP11_29_27 [3] */
@@ -5318,10 +5332,11 @@
0, 0, 0, 0,
/* IP11_2_0 [3] */
FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
- 0, 0, 0, 0, }
+ 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
- 2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3) {
+ GROUP(2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3),
+ GROUP(
/* IP12_31_30 [2] */
0, 0, 0, 0,
/* IP12_29_27 [3] */
@@ -5353,10 +5368,11 @@
FN_CAN1_RX_C, FN_DACK1_B, 0, 0,
/* IP12_2_0 [3] */
FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
- 0, FN_DREQ1_N_B, 0, 0, }
+ 0, FN_DREQ1_N_B, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
- 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
+ GROUP(1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3),
+ GROUP(
/* IP13_31 [1] */
0, 0,
/* IP13_30 [1] */
@@ -5393,11 +5409,11 @@
FN_VI1_DATA4, 0, FN_ATACS10_N, FN_ETH_REFCLK_B, 0,
/* IP13_2_0 [3] */
FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3,
- 0, FN_ATACS00_N, FN_ETH_LINK_B, 0, }
+ 0, FN_ATACS00_N, FN_ETH_LINK_B, 0, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
- 2, 1, 2, 3, 4, 1, 1, 3, 3, 3, 3, 3,
- 2, 1) {
+ GROUP(2, 1, 2, 3, 4, 1, 1, 3, 3, 3, 3, 3, 2, 1),
+ GROUP(
/* SEL_ADG [2] */
FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
/* RESERVED [1] */
@@ -5431,11 +5447,12 @@
/* SEL_I2C05 [2] */
FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3,
/* RESERVED [1] */
- 0, 0, }
+ 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
- 2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1,
- 2, 2, 2, 1, 1, 2) {
+ GROUP(2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1,
+ 2, 2, 1, 1, 2, 2, 2, 1, 1, 2),
+ GROUP(
/* SEL_IEB [2] */
FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
/* SEL_IIC0 [2] */
@@ -5482,11 +5499,12 @@
/* SEL_HSCIF1 [1] */
FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
/* RESERVED [2] */
- 0, 0, 0, 0, }
+ 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
- 2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
+ GROUP(2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
/* SEL_SCIF0 [2] */
FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
/* SEL_SCIF1 [2] */
@@ -5539,7 +5557,7 @@
/* RESERVED [1] */
0, 0,
/* RESERVED [1] */
- 0, 0, }
+ 0, 0, ))
},
{ },
};
diff --git a/drivers/pinctrl/renesas/pfc-r8a7795.c b/drivers/pinctrl/renesas/pfc-r8a7795.c
index 89ae6f6..ba17a55 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7795.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7795.c
@@ -2,7 +2,7 @@
/*
* R8A7795 ES2.0+ processor support - PFC hardware block.
*
- * Copyright (C) 2015-2017 Renesas Electronics Corporation
+ * Copyright (C) 2015-2019 Renesas Electronics Corporation
*/
#include <common.h>
@@ -202,8 +202,8 @@
#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
/* GPSR7 */
-#define GPSR7_3 FM(HDMI1_CEC)
-#define GPSR7_2 FM(HDMI0_CEC)
+#define GPSR7_3 FM(GP7_03)
+#define GPSR7_2 FM(GP7_02)
#define GPSR7_1 FM(AVS2)
#define GPSR7_0 FM(AVS1)
@@ -352,7 +352,7 @@
#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
@@ -463,7 +463,7 @@
#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
-#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
+#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
@@ -499,8 +499,8 @@
#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
-#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
-#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
+#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
+#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
#define PINMUX_MOD_SELS \
@@ -592,8 +592,8 @@
PINMUX_SINGLE(AVS1),
PINMUX_SINGLE(AVS2),
PINMUX_SINGLE(CLKOUT),
- PINMUX_SINGLE(HDMI0_CEC),
- PINMUX_SINGLE(HDMI1_CEC),
+ PINMUX_SINGLE(GP7_02),
+ PINMUX_SINGLE(GP7_03),
PINMUX_SINGLE(MSIOF0_RXD),
PINMUX_SINGLE(MSIOF0_SCK),
PINMUX_SINGLE(MSIOF0_TXD),
@@ -1131,7 +1131,7 @@
PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
- PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
+ PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
@@ -1164,7 +1164,7 @@
PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
- PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
+ PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
@@ -1223,7 +1223,7 @@
PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
- PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
+ PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
@@ -1270,7 +1270,7 @@
PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A),
- PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
+ PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
@@ -1279,7 +1279,7 @@
PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
- PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
+ PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
@@ -1410,10 +1410,9 @@
PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
/* IPSR17 */
- PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
- PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
+ PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),
- PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
+ PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
@@ -2133,22 +2132,6 @@
DU_DISP_MARK,
};
-/* - HDMI ------------------------------------------------------------------- */
-static const unsigned int hdmi0_cec_pins[] = {
- /* HDMI0_CEC */
- RCAR_GP_PIN(7, 2),
-};
-static const unsigned int hdmi0_cec_mux[] = {
- HDMI0_CEC_MARK,
-};
-static const unsigned int hdmi1_cec_pins[] = {
- /* HDMI1_CEC */
- RCAR_GP_PIN(7, 3),
-};
-static const unsigned int hdmi1_cec_mux[] = {
- HDMI1_CEC_MARK,
-};
-
/* - HSCIF0 ----------------------------------------------------------------- */
static const unsigned int hscif0_data_pins[] = {
/* RX, TX */
@@ -4227,8 +4210,6 @@
SH_PFC_PIN_GROUP(du_oddf),
SH_PFC_PIN_GROUP(du_cde),
SH_PFC_PIN_GROUP(du_disp),
- SH_PFC_PIN_GROUP(hdmi0_cec),
- SH_PFC_PIN_GROUP(hdmi1_cec),
SH_PFC_PIN_GROUP(hscif0_data),
SH_PFC_PIN_GROUP(hscif0_clk),
SH_PFC_PIN_GROUP(hscif0_ctrl),
@@ -4613,14 +4594,6 @@
"du_disp",
};
-static const char * const hdmi0_groups[] = {
- "hdmi0_cec",
-};
-
-static const char * const hdmi1_groups[] = {
- "hdmi1_cec",
-};
-
static const char * const hscif0_groups[] = {
"hscif0_data",
"hscif0_clk",
@@ -5039,8 +5012,6 @@
SH_PFC_FUNCTION(drif2),
SH_PFC_FUNCTION(drif3),
SH_PFC_FUNCTION(du),
- SH_PFC_FUNCTION(hdmi0),
- SH_PFC_FUNCTION(hdmi1),
SH_PFC_FUNCTION(hscif0),
SH_PFC_FUNCTION(hscif1),
SH_PFC_FUNCTION(hscif2),
@@ -5090,7 +5061,7 @@
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) FN_##y
#define FM(x) FN_##x
- { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
+ { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -5122,9 +5093,9 @@
GP_0_3_FN, GPSR0_3,
GP_0_2_FN, GPSR0_2,
GP_0_1_FN, GPSR0_1,
- GP_0_0_FN, GPSR0_0, }
+ GP_0_0_FN, GPSR0_0, ))
},
- { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
+ { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -5156,9 +5127,9 @@
GP_1_3_FN, GPSR1_3,
GP_1_2_FN, GPSR1_2,
GP_1_1_FN, GPSR1_1,
- GP_1_0_FN, GPSR1_0, }
+ GP_1_0_FN, GPSR1_0, ))
},
- { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
+ { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -5190,9 +5161,9 @@
GP_2_3_FN, GPSR2_3,
GP_2_2_FN, GPSR2_2,
GP_2_1_FN, GPSR2_1,
- GP_2_0_FN, GPSR2_0, }
+ GP_2_0_FN, GPSR2_0, ))
},
- { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
+ { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -5224,9 +5195,9 @@
GP_3_3_FN, GPSR3_3,
GP_3_2_FN, GPSR3_2,
GP_3_1_FN, GPSR3_1,
- GP_3_0_FN, GPSR3_0, }
+ GP_3_0_FN, GPSR3_0, ))
},
- { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
+ { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -5258,9 +5229,9 @@
GP_4_3_FN, GPSR4_3,
GP_4_2_FN, GPSR4_2,
GP_4_1_FN, GPSR4_1,
- GP_4_0_FN, GPSR4_0, }
+ GP_4_0_FN, GPSR4_0, ))
},
- { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
+ { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -5292,9 +5263,9 @@
GP_5_3_FN, GPSR5_3,
GP_5_2_FN, GPSR5_2,
GP_5_1_FN, GPSR5_1,
- GP_5_0_FN, GPSR5_0, }
+ GP_5_0_FN, GPSR5_0, ))
},
- { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
+ { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
GP_6_31_FN, GPSR6_31,
GP_6_30_FN, GPSR6_30,
GP_6_29_FN, GPSR6_29,
@@ -5326,9 +5297,9 @@
GP_6_3_FN, GPSR6_3,
GP_6_2_FN, GPSR6_2,
GP_6_1_FN, GPSR6_1,
- GP_6_0_FN, GPSR6_0, }
+ GP_6_0_FN, GPSR6_0, ))
},
- { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
+ { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -5360,14 +5331,14 @@
GP_7_3_FN, GPSR7_3,
GP_7_2_FN, GPSR7_2,
GP_7_1_FN, GPSR7_1,
- GP_7_0_FN, GPSR7_0, }
+ GP_7_0_FN, GPSR7_0, ))
},
#undef F_
#undef FM
#define F_(x, y) x,
#define FM(x) FN_##x,
- { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
+ { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
IP0_31_28
IP0_27_24
IP0_23_20
@@ -5375,9 +5346,9 @@
IP0_15_12
IP0_11_8
IP0_7_4
- IP0_3_0 }
+ IP0_3_0 ))
},
- { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
+ { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
IP1_31_28
IP1_27_24
IP1_23_20
@@ -5385,9 +5356,9 @@
IP1_15_12
IP1_11_8
IP1_7_4
- IP1_3_0 }
+ IP1_3_0 ))
},
- { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
+ { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
IP2_31_28
IP2_27_24
IP2_23_20
@@ -5395,9 +5366,9 @@
IP2_15_12
IP2_11_8
IP2_7_4
- IP2_3_0 }
+ IP2_3_0 ))
},
- { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
IP3_31_28
IP3_27_24
IP3_23_20
@@ -5405,9 +5376,9 @@
IP3_15_12
IP3_11_8
IP3_7_4
- IP3_3_0 }
+ IP3_3_0 ))
},
- { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
+ { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
IP4_31_28
IP4_27_24
IP4_23_20
@@ -5415,9 +5386,9 @@
IP4_15_12
IP4_11_8
IP4_7_4
- IP4_3_0 }
+ IP4_3_0 ))
},
- { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
+ { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
IP5_31_28
IP5_27_24
IP5_23_20
@@ -5425,9 +5396,9 @@
IP5_15_12
IP5_11_8
IP5_7_4
- IP5_3_0 }
+ IP5_3_0 ))
},
- { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
+ { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
IP6_31_28
IP6_27_24
IP6_23_20
@@ -5435,9 +5406,9 @@
IP6_15_12
IP6_11_8
IP6_7_4
- IP6_3_0 }
+ IP6_3_0 ))
},
- { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
IP7_31_28
IP7_27_24
IP7_23_20
@@ -5445,9 +5416,9 @@
/* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
IP7_11_8
IP7_7_4
- IP7_3_0 }
+ IP7_3_0 ))
},
- { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
+ { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
IP8_31_28
IP8_27_24
IP8_23_20
@@ -5455,9 +5426,9 @@
IP8_15_12
IP8_11_8
IP8_7_4
- IP8_3_0 }
+ IP8_3_0 ))
},
- { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
+ { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
IP9_31_28
IP9_27_24
IP9_23_20
@@ -5465,9 +5436,9 @@
IP9_15_12
IP9_11_8
IP9_7_4
- IP9_3_0 }
+ IP9_3_0 ))
},
- { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
+ { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
IP10_31_28
IP10_27_24
IP10_23_20
@@ -5475,9 +5446,9 @@
IP10_15_12
IP10_11_8
IP10_7_4
- IP10_3_0 }
+ IP10_3_0 ))
},
- { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
IP11_31_28
IP11_27_24
IP11_23_20
@@ -5485,9 +5456,9 @@
IP11_15_12
IP11_11_8
IP11_7_4
- IP11_3_0 }
+ IP11_3_0 ))
},
- { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
+ { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
IP12_31_28
IP12_27_24
IP12_23_20
@@ -5495,9 +5466,9 @@
IP12_15_12
IP12_11_8
IP12_7_4
- IP12_3_0 }
+ IP12_3_0 ))
},
- { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
+ { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
IP13_31_28
IP13_27_24
IP13_23_20
@@ -5505,9 +5476,9 @@
IP13_15_12
IP13_11_8
IP13_7_4
- IP13_3_0 }
+ IP13_3_0 ))
},
- { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
+ { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
IP14_31_28
IP14_27_24
IP14_23_20
@@ -5515,9 +5486,9 @@
IP14_15_12
IP14_11_8
IP14_7_4
- IP14_3_0 }
+ IP14_3_0 ))
},
- { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
IP15_31_28
IP15_27_24
IP15_23_20
@@ -5525,9 +5496,9 @@
IP15_15_12
IP15_11_8
IP15_7_4
- IP15_3_0 }
+ IP15_3_0 ))
},
- { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
+ { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
IP16_31_28
IP16_27_24
IP16_23_20
@@ -5535,9 +5506,9 @@
IP16_15_12
IP16_11_8
IP16_7_4
- IP16_3_0 }
+ IP16_3_0 ))
},
- { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
+ { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
IP17_31_28
IP17_27_24
IP17_23_20
@@ -5545,9 +5516,9 @@
IP17_15_12
IP17_11_8
IP17_7_4
- IP17_3_0 }
+ IP17_3_0 ))
},
- { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
+ { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
/* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -5555,7 +5526,7 @@
/* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
IP18_7_4
- IP18_3_0 }
+ IP18_3_0 ))
},
#undef F_
#undef FM
@@ -5563,8 +5534,9 @@
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
- 3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
- 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
+ GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
+ 1, 1, 1, 2, 2, 1, 2, 3),
+ GROUP(
MOD_SEL0_31_30_29
MOD_SEL0_28_27
MOD_SEL0_26_25_24
@@ -5585,11 +5557,12 @@
MOD_SEL0_5
MOD_SEL0_4_3
/* RESERVED 2, 1, 0 */
- 0, 0, 0, 0, 0, 0, 0, 0 }
+ 0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
- 2, 3, 1, 2, 3, 1, 1, 2, 1,
- 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
+ GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
+ 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
MOD_SEL1_31_30
MOD_SEL1_29_28_27
MOD_SEL1_26
@@ -5612,11 +5585,12 @@
MOD_SEL1_3
MOD_SEL1_2
MOD_SEL1_1
- MOD_SEL1_0 }
+ MOD_SEL1_0 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
- 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
- 4, 4, 4, 3, 1) {
+ GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
+ 1, 4, 4, 4, 3, 1),
+ GROUP(
MOD_SEL2_31
MOD_SEL2_30
MOD_SEL2_29
@@ -5643,7 +5617,7 @@
0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED 3, 2, 1 */
0, 0, 0, 0, 0, 0, 0, 0,
- MOD_SEL2_0 }
+ MOD_SEL2_0 ))
},
{ },
};
@@ -5764,8 +5738,8 @@
{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
- { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
- { RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */
+ { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
+ { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
{ PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
{ PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
} },
@@ -5899,10 +5873,12 @@
enum ioctrl_regs {
POCCTRL,
+ TDSELCTRL,
};
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[POCCTRL] = { 0xe6060380, },
+ [TDSELCTRL] = { 0xe60603c0, },
{ /* sentinel */ },
};
@@ -6019,8 +5995,8 @@
[25] = RCAR_GP_PIN(0, 15), /* D15 */
[26] = RCAR_GP_PIN(7, 0), /* AVS1 */
[27] = RCAR_GP_PIN(7, 1), /* AVS2 */
- [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */
- [29] = RCAR_GP_PIN(7, 3), /* HDMI1_CEC */
+ [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
+ [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
[30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
[31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
} },
diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c b/drivers/pinctrl/renesas/pfc-r8a7796.c
index 24fbbf1..a92c8ad 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7796.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7796.c
@@ -2,7 +2,7 @@
/*
* R8A7796 processor support - PFC hardware block.
*
- * Copyright (C) 2016-2017 Renesas Electronics Corp.
+ * Copyright (C) 2016-2019 Renesas Electronics Corp.
*
* This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
*
@@ -209,7 +209,7 @@
/* GPSR7 */
#define GPSR7_3 FM(GP7_03)
-#define GPSR7_2 FM(HDMI0_CEC)
+#define GPSR7_2 FM(GP7_02)
#define GPSR7_1 FM(AVS2)
#define GPSR7_0 FM(AVS1)
@@ -358,7 +358,7 @@
#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
@@ -469,7 +469,7 @@
#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
-#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
+#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
@@ -502,12 +502,12 @@
#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define MOD_SEL2_22 FM(SEL_NDFC_0) FM(SEL_NDFC_1)
+#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
-#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
-#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
+#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
+#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
#define PINMUX_MOD_SELS \
@@ -600,7 +600,7 @@
PINMUX_SINGLE(AVS2),
PINMUX_SINGLE(CLKOUT),
PINMUX_SINGLE(GP7_03),
- PINMUX_SINGLE(HDMI0_CEC),
+ PINMUX_SINGLE(GP7_02),
PINMUX_SINGLE(MSIOF0_RXD),
PINMUX_SINGLE(MSIOF0_SCK),
PINMUX_SINGLE(MSIOF0_TXD),
@@ -1024,35 +1024,35 @@
PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
- PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
- PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
- PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
- PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
- PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
@@ -1118,28 +1118,28 @@
PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
- PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDFC_0),
+ PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0),
PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
- PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDFC_0),
+ PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0),
PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
- PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDFC_0),
+ PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0),
PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
- PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDFC_0),
+ PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0),
PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
- PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
+ PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
@@ -1172,7 +1172,7 @@
PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
- PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
+ PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
@@ -1231,7 +1231,7 @@
PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
- PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
+ PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
@@ -1277,8 +1277,8 @@
/* IPSR14 */
PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
- PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDFC_0),
- PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
+ PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
+ PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
@@ -1287,7 +1287,7 @@
PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
- PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
+ PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
@@ -1415,10 +1415,9 @@
PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
/* IPSR17 */
- PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
- PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
+ PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),
- PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
+ PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
@@ -1502,11 +1501,6 @@
PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
- /* I2C */
- PINMUX_IPSR_NOGP(0, I2C_SEL_0_1),
- PINMUX_IPSR_NOGP(0, I2C_SEL_3_1),
- PINMUX_IPSR_NOGP(0, I2C_SEL_5_1),
-
/*
* Static pins can not be muxed between different functions but
* still need mark entries in the pinmux list. Add each static
@@ -2143,15 +2137,6 @@
DU_DISP_MARK,
};
-/* - HDMI ------------------------------------------------------------------- */
-static const unsigned int hdmi0_cec_pins[] = {
- /* HDMI0_CEC */
- RCAR_GP_PIN(7, 2),
-};
-static const unsigned int hdmi0_cec_mux[] = {
- HDMI0_CEC_MARK,
-};
-
/* - HSCIF0 ----------------------------------------------------------------- */
static const unsigned int hscif0_data_pins[] = {
/* RX, TX */
@@ -4127,8 +4112,8 @@
};
static const struct {
- struct sh_pfc_pin_group common[310];
- struct sh_pfc_pin_group automotive[33];
+ struct sh_pfc_pin_group common[312];
+ struct sh_pfc_pin_group automotive[30];
} pinmux_groups = {
.common = {
SH_PFC_PIN_GROUP(audio_clk_a_a),
@@ -4163,6 +4148,9 @@
SH_PFC_PIN_GROUP(can0_data_b),
SH_PFC_PIN_GROUP(can1_data),
SH_PFC_PIN_GROUP(can_clk),
+ SH_PFC_PIN_GROUP(canfd0_data_a),
+ SH_PFC_PIN_GROUP(canfd0_data_b),
+ SH_PFC_PIN_GROUP(canfd1_data),
SH_PFC_PIN_GROUP(du_rgb666),
SH_PFC_PIN_GROUP(du_rgb888),
SH_PFC_PIN_GROUP(du_clk_out_0),
@@ -4171,7 +4159,6 @@
SH_PFC_PIN_GROUP(du_oddf),
SH_PFC_PIN_GROUP(du_cde),
SH_PFC_PIN_GROUP(du_disp),
- SH_PFC_PIN_GROUP(hdmi0_cec),
SH_PFC_PIN_GROUP(hscif0_data),
SH_PFC_PIN_GROUP(hscif0_clk),
SH_PFC_PIN_GROUP(hscif0_ctrl),
@@ -4443,9 +4430,6 @@
SH_PFC_PIN_GROUP(vin5_clk),
},
.automotive = {
- SH_PFC_PIN_GROUP(canfd0_data_a),
- SH_PFC_PIN_GROUP(canfd0_data_b),
- SH_PFC_PIN_GROUP(canfd1_data),
SH_PFC_PIN_GROUP(drif0_ctrl_a),
SH_PFC_PIN_GROUP(drif0_data0_a),
SH_PFC_PIN_GROUP(drif0_data1_a),
@@ -4588,10 +4572,6 @@
"du_disp",
};
-static const char * const hdmi0_groups[] = {
- "hdmi0_cec",
-};
-
static const char * const hscif0_groups[] = {
"hscif0_data",
"hscif0_clk",
@@ -4985,8 +4965,8 @@
};
static const struct {
- struct sh_pfc_function common[48];
- struct sh_pfc_function automotive[6];
+ struct sh_pfc_function common[49];
+ struct sh_pfc_function automotive[4];
} pinmux_functions = {
.common = {
SH_PFC_FUNCTION(audio_clk),
@@ -4994,8 +4974,9 @@
SH_PFC_FUNCTION(can0),
SH_PFC_FUNCTION(can1),
SH_PFC_FUNCTION(can_clk),
+ SH_PFC_FUNCTION(canfd0),
+ SH_PFC_FUNCTION(canfd1),
SH_PFC_FUNCTION(du),
- SH_PFC_FUNCTION(hdmi0),
SH_PFC_FUNCTION(hscif0),
SH_PFC_FUNCTION(hscif1),
SH_PFC_FUNCTION(hscif2),
@@ -5039,8 +5020,6 @@
SH_PFC_FUNCTION(vin5),
},
.automotive = {
- SH_PFC_FUNCTION(canfd0),
- SH_PFC_FUNCTION(canfd1),
SH_PFC_FUNCTION(drif0),
SH_PFC_FUNCTION(drif1),
SH_PFC_FUNCTION(drif2),
@@ -5051,7 +5030,7 @@
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) FN_##y
#define FM(x) FN_##x
- { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
+ { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -5083,9 +5062,9 @@
GP_0_3_FN, GPSR0_3,
GP_0_2_FN, GPSR0_2,
GP_0_1_FN, GPSR0_1,
- GP_0_0_FN, GPSR0_0, }
+ GP_0_0_FN, GPSR0_0, ))
},
- { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
+ { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -5117,9 +5096,9 @@
GP_1_3_FN, GPSR1_3,
GP_1_2_FN, GPSR1_2,
GP_1_1_FN, GPSR1_1,
- GP_1_0_FN, GPSR1_0, }
+ GP_1_0_FN, GPSR1_0, ))
},
- { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
+ { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -5151,9 +5130,9 @@
GP_2_3_FN, GPSR2_3,
GP_2_2_FN, GPSR2_2,
GP_2_1_FN, GPSR2_1,
- GP_2_0_FN, GPSR2_0, }
+ GP_2_0_FN, GPSR2_0, ))
},
- { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
+ { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -5185,9 +5164,9 @@
GP_3_3_FN, GPSR3_3,
GP_3_2_FN, GPSR3_2,
GP_3_1_FN, GPSR3_1,
- GP_3_0_FN, GPSR3_0, }
+ GP_3_0_FN, GPSR3_0, ))
},
- { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
+ { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -5219,9 +5198,9 @@
GP_4_3_FN, GPSR4_3,
GP_4_2_FN, GPSR4_2,
GP_4_1_FN, GPSR4_1,
- GP_4_0_FN, GPSR4_0, }
+ GP_4_0_FN, GPSR4_0, ))
},
- { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
+ { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -5253,9 +5232,9 @@
GP_5_3_FN, GPSR5_3,
GP_5_2_FN, GPSR5_2,
GP_5_1_FN, GPSR5_1,
- GP_5_0_FN, GPSR5_0, }
+ GP_5_0_FN, GPSR5_0, ))
},
- { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
+ { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
GP_6_31_FN, GPSR6_31,
GP_6_30_FN, GPSR6_30,
GP_6_29_FN, GPSR6_29,
@@ -5287,9 +5266,9 @@
GP_6_3_FN, GPSR6_3,
GP_6_2_FN, GPSR6_2,
GP_6_1_FN, GPSR6_1,
- GP_6_0_FN, GPSR6_0, }
+ GP_6_0_FN, GPSR6_0, ))
},
- { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
+ { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -5321,14 +5300,14 @@
GP_7_3_FN, GPSR7_3,
GP_7_2_FN, GPSR7_2,
GP_7_1_FN, GPSR7_1,
- GP_7_0_FN, GPSR7_0, }
+ GP_7_0_FN, GPSR7_0, ))
},
#undef F_
#undef FM
#define F_(x, y) x,
#define FM(x) FN_##x,
- { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
+ { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
IP0_31_28
IP0_27_24
IP0_23_20
@@ -5336,9 +5315,9 @@
IP0_15_12
IP0_11_8
IP0_7_4
- IP0_3_0 }
+ IP0_3_0 ))
},
- { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
+ { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
IP1_31_28
IP1_27_24
IP1_23_20
@@ -5346,9 +5325,9 @@
IP1_15_12
IP1_11_8
IP1_7_4
- IP1_3_0 }
+ IP1_3_0 ))
},
- { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
+ { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
IP2_31_28
IP2_27_24
IP2_23_20
@@ -5356,9 +5335,9 @@
IP2_15_12
IP2_11_8
IP2_7_4
- IP2_3_0 }
+ IP2_3_0 ))
},
- { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
IP3_31_28
IP3_27_24
IP3_23_20
@@ -5366,9 +5345,9 @@
IP3_15_12
IP3_11_8
IP3_7_4
- IP3_3_0 }
+ IP3_3_0 ))
},
- { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
+ { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
IP4_31_28
IP4_27_24
IP4_23_20
@@ -5376,9 +5355,9 @@
IP4_15_12
IP4_11_8
IP4_7_4
- IP4_3_0 }
+ IP4_3_0 ))
},
- { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
+ { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
IP5_31_28
IP5_27_24
IP5_23_20
@@ -5386,9 +5365,9 @@
IP5_15_12
IP5_11_8
IP5_7_4
- IP5_3_0 }
+ IP5_3_0 ))
},
- { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
+ { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
IP6_31_28
IP6_27_24
IP6_23_20
@@ -5396,9 +5375,9 @@
IP6_15_12
IP6_11_8
IP6_7_4
- IP6_3_0 }
+ IP6_3_0 ))
},
- { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
IP7_31_28
IP7_27_24
IP7_23_20
@@ -5406,9 +5385,9 @@
/* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
IP7_11_8
IP7_7_4
- IP7_3_0 }
+ IP7_3_0 ))
},
- { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
+ { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
IP8_31_28
IP8_27_24
IP8_23_20
@@ -5416,9 +5395,9 @@
IP8_15_12
IP8_11_8
IP8_7_4
- IP8_3_0 }
+ IP8_3_0 ))
},
- { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
+ { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
IP9_31_28
IP9_27_24
IP9_23_20
@@ -5426,9 +5405,9 @@
IP9_15_12
IP9_11_8
IP9_7_4
- IP9_3_0 }
+ IP9_3_0 ))
},
- { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
+ { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
IP10_31_28
IP10_27_24
IP10_23_20
@@ -5436,9 +5415,9 @@
IP10_15_12
IP10_11_8
IP10_7_4
- IP10_3_0 }
+ IP10_3_0 ))
},
- { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
IP11_31_28
IP11_27_24
IP11_23_20
@@ -5446,9 +5425,9 @@
IP11_15_12
IP11_11_8
IP11_7_4
- IP11_3_0 }
+ IP11_3_0 ))
},
- { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
+ { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
IP12_31_28
IP12_27_24
IP12_23_20
@@ -5456,9 +5435,9 @@
IP12_15_12
IP12_11_8
IP12_7_4
- IP12_3_0 }
+ IP12_3_0 ))
},
- { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
+ { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
IP13_31_28
IP13_27_24
IP13_23_20
@@ -5466,9 +5445,9 @@
IP13_15_12
IP13_11_8
IP13_7_4
- IP13_3_0 }
+ IP13_3_0 ))
},
- { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
+ { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
IP14_31_28
IP14_27_24
IP14_23_20
@@ -5476,9 +5455,9 @@
IP14_15_12
IP14_11_8
IP14_7_4
- IP14_3_0 }
+ IP14_3_0 ))
},
- { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
IP15_31_28
IP15_27_24
IP15_23_20
@@ -5486,9 +5465,9 @@
IP15_15_12
IP15_11_8
IP15_7_4
- IP15_3_0 }
+ IP15_3_0 ))
},
- { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
+ { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
IP16_31_28
IP16_27_24
IP16_23_20
@@ -5496,9 +5475,9 @@
IP16_15_12
IP16_11_8
IP16_7_4
- IP16_3_0 }
+ IP16_3_0 ))
},
- { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
+ { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
IP17_31_28
IP17_27_24
IP17_23_20
@@ -5506,9 +5485,9 @@
IP17_15_12
IP17_11_8
IP17_7_4
- IP17_3_0 }
+ IP17_3_0 ))
},
- { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
+ { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
/* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -5516,7 +5495,7 @@
/* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
IP18_7_4
- IP18_3_0 }
+ IP18_3_0 ))
},
#undef F_
#undef FM
@@ -5524,8 +5503,9 @@
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
- 3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
- 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
+ GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
+ 1, 1, 1, 2, 2, 1, 2, 3),
+ GROUP(
MOD_SEL0_31_30_29
MOD_SEL0_28_27
MOD_SEL0_26_25_24
@@ -5546,11 +5526,12 @@
MOD_SEL0_5
MOD_SEL0_4_3
/* RESERVED 2, 1, 0 */
- 0, 0, 0, 0, 0, 0, 0, 0 }
+ 0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
- 2, 3, 1, 2, 3, 1, 1, 2, 1,
- 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
+ GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
+ 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
MOD_SEL1_31_30
MOD_SEL1_29_28_27
MOD_SEL1_26
@@ -5573,11 +5554,12 @@
MOD_SEL1_3
MOD_SEL1_2
MOD_SEL1_1
- MOD_SEL1_0 }
+ MOD_SEL1_0 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
- 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
- 4, 4, 4, 3, 1) {
+ GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
+ 1, 4, 4, 4, 3, 1),
+ GROUP(
MOD_SEL2_31
MOD_SEL2_30
MOD_SEL2_29
@@ -5603,7 +5585,7 @@
0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED 3, 2, 1 */
0, 0, 0, 0, 0, 0, 0, 0,
- MOD_SEL2_0 }
+ MOD_SEL2_0 ))
},
{ },
};
@@ -5724,7 +5706,7 @@
{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
- { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
+ { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
{ RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
{ PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
{ PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
@@ -5858,10 +5840,12 @@
enum ioctrl_regs {
POCCTRL,
+ TDSELCTRL,
};
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[POCCTRL] = { 0xe6060380, },
+ [TDSELCTRL] = { 0xe60603c0, },
{ /* sentinel */ },
};
@@ -5978,7 +5962,7 @@
[25] = RCAR_GP_PIN(0, 15), /* D15 */
[26] = RCAR_GP_PIN(7, 0), /* AVS1 */
[27] = RCAR_GP_PIN(7, 1), /* AVS2 */
- [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */
+ [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
[29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
[30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
[31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c b/drivers/pinctrl/renesas/pfc-r8a77965.c
index 7c24836..2523904 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77965.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77965.c
@@ -3,7 +3,7 @@
* R8A77965 processor support - PFC hardware block.
*
* Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
- * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2016-2019 Renesas Electronics Corp.
*
* This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
*
@@ -210,7 +210,7 @@
/* GPSR7 */
#define GPSR7_3 FM(GP7_03)
-#define GPSR7_2 FM(HDMI0_CEC)
+#define GPSR7_2 FM(GP7_02)
#define GPSR7_1 FM(AVS2)
#define GPSR7_0 FM(AVS1)
@@ -359,7 +359,7 @@
#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
@@ -470,7 +470,7 @@
#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
-#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
+#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
@@ -503,12 +503,12 @@
#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define MOD_SEL2_22 FM(SEL_NDFC_0) FM(SEL_NDFC_1)
+#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
-#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
-#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
+#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
+#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
#define PINMUX_MOD_SELS \
@@ -560,6 +560,9 @@
FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN3) \
FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
+#define PINMUX_PHYS \
+ FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
+
enum {
PINMUX_RESERVED = 0,
@@ -585,6 +588,7 @@
PINMUX_IPSR
PINMUX_MOD_SELS
PINMUX_STATIC
+ PINMUX_PHYS
PINMUX_MARK_END,
#undef F_
#undef FM
@@ -597,7 +601,7 @@
PINMUX_SINGLE(AVS2),
PINMUX_SINGLE(CLKOUT),
PINMUX_SINGLE(GP7_03),
- PINMUX_SINGLE(HDMI0_CEC),
+ PINMUX_SINGLE(GP7_02),
PINMUX_SINGLE(MSIOF0_RXD),
PINMUX_SINGLE(MSIOF0_SCK),
PINMUX_SINGLE(MSIOF0_TXD),
@@ -622,13 +626,15 @@
PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
- PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
- PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
- PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
+ PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
+ PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
+ PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
+ PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
- PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
- PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
- PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0),
+ PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
+ PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
+ PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
+ PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
@@ -681,14 +687,16 @@
PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
- PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
- PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
- PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
- PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
+ PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
+ PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
+ PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
+ PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
+ PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1),
- PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
- PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
- PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
+ PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
+ PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
+ PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
+ PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
PINMUX_IPSR_GPSR(IP1_31_28, A0),
PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
@@ -1019,35 +1027,35 @@
PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
- PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
- PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
- PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
- PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
- PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
@@ -1114,26 +1122,28 @@
PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
- PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDFC_0),
+ PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0),
PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
- PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDFC_0),
+ PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0),
PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
- PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
- PINMUX_IPSR_MSEL(IP11_19_16, NFRB_N_A, SEL_NDFC_0),
- PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
+ PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
+ PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0),
+ PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
+ PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
- PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
- PINMUX_IPSR_MSEL(IP11_23_20, NFCE_N_A, SEL_NDFC_0),
- PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
+ PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
+ PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0),
+ PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
+ PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
- PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
+ PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
@@ -1166,7 +1176,7 @@
PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
- PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
+ PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
@@ -1225,7 +1235,7 @@
PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
- PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
+ PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
@@ -1271,8 +1281,8 @@
/* IPSR14 */
PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
- PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDFC_0),
- PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
+ PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
+ PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
@@ -1281,7 +1291,7 @@
PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
- PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
+ PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
@@ -1410,10 +1420,9 @@
PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
/* IPSR17 */
- PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
- PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
+ PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),
- PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
+ PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
@@ -1497,11 +1506,6 @@
PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
- /* I2C */
- PINMUX_IPSR_NOGP(0, I2C_SEL_0_1),
- PINMUX_IPSR_NOGP(0, I2C_SEL_3_1),
- PINMUX_IPSR_NOGP(0, I2C_SEL_5_1),
-
/*
* Static pins can not be muxed between different functions but
* still need mark entries in the pinmux list. Add each static
@@ -2481,52 +2485,92 @@
};
/* - I2C -------------------------------------------------------------------- */
+static const unsigned int i2c0_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
+};
+
+static const unsigned int i2c0_mux[] = {
+ SCL0_MARK, SDA0_MARK,
+};
+
static const unsigned int i2c1_a_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
};
+
static const unsigned int i2c1_a_mux[] = {
SDA1_A_MARK, SCL1_A_MARK,
};
+
static const unsigned int i2c1_b_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
};
+
static const unsigned int i2c1_b_mux[] = {
SDA1_B_MARK, SCL1_B_MARK,
};
+
static const unsigned int i2c2_a_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
};
+
static const unsigned int i2c2_a_mux[] = {
SDA2_A_MARK, SCL2_A_MARK,
};
+
static const unsigned int i2c2_b_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
};
+
static const unsigned int i2c2_b_mux[] = {
SDA2_B_MARK, SCL2_B_MARK,
};
+
+static const unsigned int i2c3_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
+};
+
+static const unsigned int i2c3_mux[] = {
+ SCL3_MARK, SDA3_MARK,
+};
+
+static const unsigned int i2c5_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
+};
+
+static const unsigned int i2c5_mux[] = {
+ SCL5_MARK, SDA5_MARK,
+};
+
static const unsigned int i2c6_a_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
};
+
static const unsigned int i2c6_a_mux[] = {
SDA6_A_MARK, SCL6_A_MARK,
};
+
static const unsigned int i2c6_b_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
};
+
static const unsigned int i2c6_b_mux[] = {
SDA6_B_MARK, SCL6_B_MARK,
};
+
static const unsigned int i2c6_c_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
};
+
static const unsigned int i2c6_c_mux[] = {
SDA6_C_MARK, SCL6_C_MARK,
};
@@ -4416,10 +4460,13 @@
SH_PFC_PIN_GROUP(hscif4_clk),
SH_PFC_PIN_GROUP(hscif4_ctrl),
SH_PFC_PIN_GROUP(hscif4_data_b),
+ SH_PFC_PIN_GROUP(i2c0),
SH_PFC_PIN_GROUP(i2c1_a),
SH_PFC_PIN_GROUP(i2c1_b),
SH_PFC_PIN_GROUP(i2c2_a),
SH_PFC_PIN_GROUP(i2c2_b),
+ SH_PFC_PIN_GROUP(i2c3),
+ SH_PFC_PIN_GROUP(i2c5),
SH_PFC_PIN_GROUP(i2c6_a),
SH_PFC_PIN_GROUP(i2c6_b),
SH_PFC_PIN_GROUP(i2c6_c),
@@ -4810,6 +4857,10 @@
"hscif4_data_b",
};
+static const char * const i2c0_groups[] = {
+ "i2c0",
+};
+
static const char * const i2c1_groups[] = {
"i2c1_a",
"i2c1_b",
@@ -4820,6 +4871,14 @@
"i2c2_b",
};
+static const char * const i2c3_groups[] = {
+ "i2c3",
+};
+
+static const char * const i2c5_groups[] = {
+ "i2c5",
+};
+
static const char * const i2c6_groups[] = {
"i2c6_a",
"i2c6_b",
@@ -5169,8 +5228,11 @@
SH_PFC_FUNCTION(hscif2),
SH_PFC_FUNCTION(hscif3),
SH_PFC_FUNCTION(hscif4),
+ SH_PFC_FUNCTION(i2c0),
SH_PFC_FUNCTION(i2c1),
SH_PFC_FUNCTION(i2c2),
+ SH_PFC_FUNCTION(i2c3),
+ SH_PFC_FUNCTION(i2c5),
SH_PFC_FUNCTION(i2c6),
SH_PFC_FUNCTION(intc_ex),
SH_PFC_FUNCTION(msiof0),
@@ -5208,7 +5270,7 @@
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) FN_##y
#define FM(x) FN_##x
- { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
+ { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -5240,9 +5302,9 @@
GP_0_3_FN, GPSR0_3,
GP_0_2_FN, GPSR0_2,
GP_0_1_FN, GPSR0_1,
- GP_0_0_FN, GPSR0_0, }
+ GP_0_0_FN, GPSR0_0, ))
},
- { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
+ { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -5274,9 +5336,9 @@
GP_1_3_FN, GPSR1_3,
GP_1_2_FN, GPSR1_2,
GP_1_1_FN, GPSR1_1,
- GP_1_0_FN, GPSR1_0, }
+ GP_1_0_FN, GPSR1_0, ))
},
- { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
+ { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -5308,9 +5370,9 @@
GP_2_3_FN, GPSR2_3,
GP_2_2_FN, GPSR2_2,
GP_2_1_FN, GPSR2_1,
- GP_2_0_FN, GPSR2_0, }
+ GP_2_0_FN, GPSR2_0, ))
},
- { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
+ { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -5342,9 +5404,9 @@
GP_3_3_FN, GPSR3_3,
GP_3_2_FN, GPSR3_2,
GP_3_1_FN, GPSR3_1,
- GP_3_0_FN, GPSR3_0, }
+ GP_3_0_FN, GPSR3_0, ))
},
- { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
+ { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -5376,9 +5438,9 @@
GP_4_3_FN, GPSR4_3,
GP_4_2_FN, GPSR4_2,
GP_4_1_FN, GPSR4_1,
- GP_4_0_FN, GPSR4_0, }
+ GP_4_0_FN, GPSR4_0, ))
},
- { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
+ { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -5410,9 +5472,9 @@
GP_5_3_FN, GPSR5_3,
GP_5_2_FN, GPSR5_2,
GP_5_1_FN, GPSR5_1,
- GP_5_0_FN, GPSR5_0, }
+ GP_5_0_FN, GPSR5_0, ))
},
- { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
+ { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
GP_6_31_FN, GPSR6_31,
GP_6_30_FN, GPSR6_30,
GP_6_29_FN, GPSR6_29,
@@ -5444,9 +5506,9 @@
GP_6_3_FN, GPSR6_3,
GP_6_2_FN, GPSR6_2,
GP_6_1_FN, GPSR6_1,
- GP_6_0_FN, GPSR6_0, }
+ GP_6_0_FN, GPSR6_0, ))
},
- { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
+ { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -5478,14 +5540,14 @@
GP_7_3_FN, GPSR7_3,
GP_7_2_FN, GPSR7_2,
GP_7_1_FN, GPSR7_1,
- GP_7_0_FN, GPSR7_0, }
+ GP_7_0_FN, GPSR7_0, ))
},
#undef F_
#undef FM
#define F_(x, y) x,
#define FM(x) FN_##x,
- { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
+ { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
IP0_31_28
IP0_27_24
IP0_23_20
@@ -5493,9 +5555,9 @@
IP0_15_12
IP0_11_8
IP0_7_4
- IP0_3_0 }
+ IP0_3_0 ))
},
- { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
+ { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
IP1_31_28
IP1_27_24
IP1_23_20
@@ -5503,9 +5565,9 @@
IP1_15_12
IP1_11_8
IP1_7_4
- IP1_3_0 }
+ IP1_3_0 ))
},
- { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
+ { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
IP2_31_28
IP2_27_24
IP2_23_20
@@ -5513,9 +5575,9 @@
IP2_15_12
IP2_11_8
IP2_7_4
- IP2_3_0 }
+ IP2_3_0 ))
},
- { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
IP3_31_28
IP3_27_24
IP3_23_20
@@ -5523,9 +5585,9 @@
IP3_15_12
IP3_11_8
IP3_7_4
- IP3_3_0 }
+ IP3_3_0 ))
},
- { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
+ { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
IP4_31_28
IP4_27_24
IP4_23_20
@@ -5533,9 +5595,9 @@
IP4_15_12
IP4_11_8
IP4_7_4
- IP4_3_0 }
+ IP4_3_0 ))
},
- { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
+ { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
IP5_31_28
IP5_27_24
IP5_23_20
@@ -5543,9 +5605,9 @@
IP5_15_12
IP5_11_8
IP5_7_4
- IP5_3_0 }
+ IP5_3_0 ))
},
- { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
+ { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
IP6_31_28
IP6_27_24
IP6_23_20
@@ -5553,9 +5615,9 @@
IP6_15_12
IP6_11_8
IP6_7_4
- IP6_3_0 }
+ IP6_3_0 ))
},
- { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
IP7_31_28
IP7_27_24
IP7_23_20
@@ -5563,9 +5625,9 @@
/* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
IP7_11_8
IP7_7_4
- IP7_3_0 }
+ IP7_3_0 ))
},
- { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
+ { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
IP8_31_28
IP8_27_24
IP8_23_20
@@ -5573,9 +5635,9 @@
IP8_15_12
IP8_11_8
IP8_7_4
- IP8_3_0 }
+ IP8_3_0 ))
},
- { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
+ { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
IP9_31_28
IP9_27_24
IP9_23_20
@@ -5583,9 +5645,9 @@
IP9_15_12
IP9_11_8
IP9_7_4
- IP9_3_0 }
+ IP9_3_0 ))
},
- { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
+ { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
IP10_31_28
IP10_27_24
IP10_23_20
@@ -5593,9 +5655,9 @@
IP10_15_12
IP10_11_8
IP10_7_4
- IP10_3_0 }
+ IP10_3_0 ))
},
- { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
IP11_31_28
IP11_27_24
IP11_23_20
@@ -5603,9 +5665,9 @@
IP11_15_12
IP11_11_8
IP11_7_4
- IP11_3_0 }
+ IP11_3_0 ))
},
- { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
+ { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
IP12_31_28
IP12_27_24
IP12_23_20
@@ -5613,9 +5675,9 @@
IP12_15_12
IP12_11_8
IP12_7_4
- IP12_3_0 }
+ IP12_3_0 ))
},
- { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
+ { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
IP13_31_28
IP13_27_24
IP13_23_20
@@ -5623,9 +5685,9 @@
IP13_15_12
IP13_11_8
IP13_7_4
- IP13_3_0 }
+ IP13_3_0 ))
},
- { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
+ { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
IP14_31_28
IP14_27_24
IP14_23_20
@@ -5633,9 +5695,9 @@
IP14_15_12
IP14_11_8
IP14_7_4
- IP14_3_0 }
+ IP14_3_0 ))
},
- { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
IP15_31_28
IP15_27_24
IP15_23_20
@@ -5643,9 +5705,9 @@
IP15_15_12
IP15_11_8
IP15_7_4
- IP15_3_0 }
+ IP15_3_0 ))
},
- { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
+ { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
IP16_31_28
IP16_27_24
IP16_23_20
@@ -5653,9 +5715,9 @@
IP16_15_12
IP16_11_8
IP16_7_4
- IP16_3_0 }
+ IP16_3_0 ))
},
- { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
+ { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
IP17_31_28
IP17_27_24
IP17_23_20
@@ -5663,9 +5725,9 @@
IP17_15_12
IP17_11_8
IP17_7_4
- IP17_3_0 }
+ IP17_3_0 ))
},
- { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
+ { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
/* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -5673,7 +5735,7 @@
/* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
IP18_7_4
- IP18_3_0 }
+ IP18_3_0 ))
},
#undef F_
#undef FM
@@ -5681,8 +5743,9 @@
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
- 3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
- 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
+ GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
+ 1, 1, 1, 2, 2, 1, 2, 3),
+ GROUP(
MOD_SEL0_31_30_29
MOD_SEL0_28_27
MOD_SEL0_26_25_24
@@ -5703,11 +5766,12 @@
MOD_SEL0_5
MOD_SEL0_4_3
/* RESERVED 2, 1, 0 */
- 0, 0, 0, 0, 0, 0, 0, 0 }
+ 0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
- 2, 3, 1, 2, 3, 1, 1, 2, 1,
- 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
+ GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
+ 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
MOD_SEL1_31_30
MOD_SEL1_29_28_27
MOD_SEL1_26
@@ -5730,11 +5794,12 @@
MOD_SEL1_3
MOD_SEL1_2
MOD_SEL1_1
- MOD_SEL1_0 }
+ MOD_SEL1_0 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
- 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
- 4, 4, 4, 3, 1) {
+ GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
+ 1, 4, 4, 4, 3, 1),
+ GROUP(
MOD_SEL2_31
MOD_SEL2_30
MOD_SEL2_29
@@ -5760,7 +5825,7 @@
0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED 3, 2, 1 */
0, 0, 0, 0, 0, 0, 0, 0,
- MOD_SEL2_0 }
+ MOD_SEL2_0 ))
},
{ },
};
@@ -5881,7 +5946,7 @@
{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
- { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
+ { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
{ RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
{ PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
{ PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
@@ -6015,10 +6080,12 @@
enum ioctrl_regs {
POCCTRL,
+ TDSELCTRL,
};
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[POCCTRL] = { 0xe6060380, },
+ [TDSELCTRL] = { 0xe60603c0, },
{ /* sentinel */ },
};
@@ -6135,7 +6202,7 @@
[25] = RCAR_GP_PIN(0, 15), /* D15 */
[26] = RCAR_GP_PIN(7, 0), /* AVS1 */
[27] = RCAR_GP_PIN(7, 1), /* AVS2 */
- [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */
+ [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
[29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
[30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
[31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
diff --git a/drivers/pinctrl/renesas/pfc-r8a77970.c b/drivers/pinctrl/renesas/pfc-r8a77970.c
index 823edb5..33ecd93 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77970.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77970.c
@@ -173,19 +173,19 @@
#define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(HRX0) F_(0, 0) FM(A19) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_27_24 FM(IRQ0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_27_24 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N_TANS) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_23_20 FM(VI0_DATA2) FM(AVB0_AVTP_PPS) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N_TANS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) FM(PWM0_A) FM(A22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) FM(A23) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) FM(A24) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -200,18 +200,18 @@
#define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_31_28 FM(VI1_DATA3) FM(CANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_3_0 FM(VI1_DATA4) FM(CANFD_CLK_B) F_(0, 0) FM(D7) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_7_4 FM(VI1_DATA5) F_(0,0) FM(SCK4) FM(D8) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_11_8 FM(VI1_DATA6) F_(0,0) FM(RX4) FM(D9) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_15_12 FM(VI1_DATA7) F_(0,0) FM(TX4) FM(D10) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_19_16 FM(VI1_DATA8) F_(0,0) FM(CTS4_N) FM(D11) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_23_20 FM(VI1_DATA9) F_(0,0) FM(RTS4_N_TANS) FM(D12) FM(MMC_D6) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_27_24 FM(VI1_DATA10) F_(0,0) F_(0, 0) FM(D13) FM(MMC_D7) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_7_4 FM(VI1_DATA5) F_(0, 0) FM(SCK4) FM(D8) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_11_8 FM(VI1_DATA6) F_(0, 0) FM(RX4) FM(D9) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_15_12 FM(VI1_DATA7) F_(0, 0) FM(TX4) FM(D10) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_19_16 FM(VI1_DATA8) F_(0, 0) FM(CTS4_N) FM(D11) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_23_20 FM(VI1_DATA9) F_(0, 0) FM(RTS4_N) FM(D12) FM(MMC_D6) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_27_24 FM(VI1_DATA10) F_(0, 0) F_(0, 0) FM(D13) FM(MMC_D7) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_31_28 FM(VI1_DATA11) FM(SCL4) FM(IRQ4) FM(D14) FM(MMC_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_3_0 FM(VI1_FIELD) FM(SDA4) FM(IRQ5) FM(D15) FM(MMC_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_7_4 FM(SCL0) FM(DU_DR0) FM(TPU0TO0) FM(CLKOUT) F_(0, 0) FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_11_8 FM(SDA0) FM(DU_DR1) FM(TPU0TO1) FM(BS_N) FM(SCK0) FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_15_12 FM(SCL1) FM(DU_DG0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_19_16 FM(SDA1) FM(DU_DG1) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N_TANS) FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_19_16 FM(SDA1) FM(DU_DG1) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N) FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_23_20 FM(SCL2) FM(DU_DB0) FM(TCLK1_A) FM(WE1_N) FM(RX0) FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_27_24 FM(SDA2) FM(DU_DB1) FM(TCLK2_A) FM(EX_WAIT0) FM(TX0) FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_31_28 FM(AVB0_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSCLKST2_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -472,7 +472,6 @@
PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC),
PINMUX_IPSR_GPSR(IP2_27_24, IRQ0),
- PINMUX_IPSR_GPSR(IP2_27_24, CC5_OSCOUT),
PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK),
PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK),
@@ -498,7 +497,7 @@
PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0),
PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1),
- PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N_TANS),
+ PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N),
PINMUX_IPSR_GPSR(IP3_15_12, HRX3),
PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1),
@@ -529,7 +528,7 @@
PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7),
PINMUX_IPSR_GPSR(IP4_11_8, HRX1),
- PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N_TANS),
+ PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N),
PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8),
PINMUX_IPSR_GPSR(IP4_15_12, HSCK2),
@@ -619,7 +618,7 @@
PINMUX_IPSR_GPSR(IP6_19_16, MMC_D5),
PINMUX_IPSR_GPSR(IP6_23_20, VI1_DATA9),
- PINMUX_IPSR_GPSR(IP6_23_20, RTS4_N_TANS),
+ PINMUX_IPSR_GPSR(IP6_23_20, RTS4_N),
PINMUX_IPSR_GPSR(IP6_23_20, D12),
PINMUX_IPSR_GPSR(IP6_23_20, MMC_D6),
PINMUX_IPSR_MSEL(IP6_23_20, SCL3_B, SEL_I2C3_1),
@@ -666,7 +665,7 @@
PINMUX_IPSR_GPSR(IP7_19_16, DU_DG1),
PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3),
PINMUX_IPSR_GPSR(IP7_19_16, WE0_N),
- PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N_TANS),
+ PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N),
PINMUX_IPSR_GPSR(IP7_19_16, MSIOF0_SYNC),
PINMUX_IPSR_GPSR(IP7_23_20, SCL2),
@@ -1470,7 +1469,7 @@
RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
};
static const unsigned int scif0_ctrl_mux[] = {
- RTS0_N_TANS_MARK, CTS0_N_MARK,
+ RTS0_N_MARK, CTS0_N_MARK,
};
/* - SCIF1 ------------------------------------------------------------------ */
@@ -1493,7 +1492,7 @@
RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
};
static const unsigned int scif1_ctrl_mux[] = {
- RTS1_N_TANS_MARK, CTS1_N_MARK,
+ RTS1_N_MARK, CTS1_N_MARK,
};
static const unsigned int scif1_data_b_pins[] = {
/* RX, TX */
@@ -1523,7 +1522,7 @@
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
};
static const unsigned int scif3_ctrl_mux[] = {
- RTS3_N_TANS_MARK, CTS3_N_MARK,
+ RTS3_N_MARK, CTS3_N_MARK,
};
/* - SCIF4 ------------------------------------------------------------------ */
@@ -1546,7 +1545,7 @@
RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
};
static const unsigned int scif4_ctrl_mux[] = {
- RTS4_N_TANS_MARK, CTS4_N_MARK,
+ RTS4_N_MARK, CTS4_N_MARK,
};
/* - TMU -------------------------------------------------------------------- */
@@ -2074,7 +2073,7 @@
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) FN_##y
#define FM(x) FN_##x
- { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
+ { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -2106,9 +2105,9 @@
GP_0_3_FN, GPSR0_3,
GP_0_2_FN, GPSR0_2,
GP_0_1_FN, GPSR0_1,
- GP_0_0_FN, GPSR0_0, }
+ GP_0_0_FN, GPSR0_0, ))
},
- { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
+ { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -2140,9 +2139,9 @@
GP_1_3_FN, GPSR1_3,
GP_1_2_FN, GPSR1_2,
GP_1_1_FN, GPSR1_1,
- GP_1_0_FN, GPSR1_0, }
+ GP_1_0_FN, GPSR1_0, ))
},
- { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
+ { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -2174,9 +2173,9 @@
GP_2_3_FN, GPSR2_3,
GP_2_2_FN, GPSR2_2,
GP_2_1_FN, GPSR2_1,
- GP_2_0_FN, GPSR2_0, }
+ GP_2_0_FN, GPSR2_0, ))
},
- { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
+ { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -2208,9 +2207,9 @@
GP_3_3_FN, GPSR3_3,
GP_3_2_FN, GPSR3_2,
GP_3_1_FN, GPSR3_1,
- GP_3_0_FN, GPSR3_0, }
+ GP_3_0_FN, GPSR3_0, ))
},
- { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
+ { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -2242,9 +2241,9 @@
GP_4_3_FN, GPSR4_3,
GP_4_2_FN, GPSR4_2,
GP_4_1_FN, GPSR4_1,
- GP_4_0_FN, GPSR4_0, }
+ GP_4_0_FN, GPSR4_0, ))
},
- { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
+ { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -2276,14 +2275,14 @@
GP_5_3_FN, GPSR5_3,
GP_5_2_FN, GPSR5_2,
GP_5_1_FN, GPSR5_1,
- GP_5_0_FN, GPSR5_0, }
+ GP_5_0_FN, GPSR5_0, ))
},
#undef F_
#undef FM
#define F_(x, y) x,
#define FM(x) FN_##x,
- { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
+ { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
IP0_31_28
IP0_27_24
IP0_23_20
@@ -2291,9 +2290,9 @@
IP0_15_12
IP0_11_8
IP0_7_4
- IP0_3_0 }
+ IP0_3_0 ))
},
- { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
+ { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
IP1_31_28
IP1_27_24
IP1_23_20
@@ -2301,9 +2300,9 @@
IP1_15_12
IP1_11_8
IP1_7_4
- IP1_3_0 }
+ IP1_3_0 ))
},
- { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
+ { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
IP2_31_28
IP2_27_24
IP2_23_20
@@ -2311,9 +2310,9 @@
IP2_15_12
IP2_11_8
IP2_7_4
- IP2_3_0 }
+ IP2_3_0 ))
},
- { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
IP3_31_28
IP3_27_24
IP3_23_20
@@ -2321,9 +2320,9 @@
IP3_15_12
IP3_11_8
IP3_7_4
- IP3_3_0 }
+ IP3_3_0 ))
},
- { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
+ { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
IP4_31_28
IP4_27_24
IP4_23_20
@@ -2331,9 +2330,9 @@
IP4_15_12
IP4_11_8
IP4_7_4
- IP4_3_0 }
+ IP4_3_0 ))
},
- { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
+ { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
IP5_31_28
IP5_27_24
IP5_23_20
@@ -2341,9 +2340,9 @@
IP5_15_12
IP5_11_8
IP5_7_4
- IP5_3_0 }
+ IP5_3_0 ))
},
- { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
+ { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
IP6_31_28
IP6_27_24
IP6_23_20
@@ -2351,9 +2350,9 @@
IP6_15_12
IP6_11_8
IP6_7_4
- IP6_3_0 }
+ IP6_3_0 ))
},
- { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
IP7_31_28
IP7_27_24
IP7_23_20
@@ -2361,9 +2360,9 @@
IP7_15_12
IP7_11_8
IP7_7_4
- IP7_3_0 }
+ IP7_3_0 ))
},
- { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
+ { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
IP8_31_28
IP8_27_24
IP8_23_20
@@ -2371,7 +2370,7 @@
IP8_15_12
IP8_11_8
IP8_7_4
- IP8_3_0 }
+ IP8_3_0 ))
},
#undef F_
#undef FM
@@ -2379,8 +2378,9 @@
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
- 4, 4, 4, 4, 4,
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
+ GROUP(4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1),
+ GROUP(
/* RESERVED 31, 30, 29, 28 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED 27, 26, 25, 24 */
@@ -2402,21 +2402,23 @@
MOD_SEL0_3
MOD_SEL0_2
MOD_SEL0_1
- MOD_SEL0_0 }
+ MOD_SEL0_0 ))
},
{ },
};
enum ioctrl_regs {
- IOCTRL30,
- IOCTRL31,
- IOCTRL32,
+ POCCTRL0,
+ POCCTRL1,
+ POCCTRL2,
+ TDSELCTRL,
};
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
- [IOCTRL30] = { 0xe6060380 },
- [IOCTRL31] = { 0xe6060384 },
- [IOCTRL32] = { 0xe6060388 },
+ [POCCTRL0] = { 0xe6060380 },
+ [POCCTRL1] = { 0xe6060384 },
+ [POCCTRL2] = { 0xe6060388 },
+ [TDSELCTRL] = { 0xe60603c0, },
{ /* sentinel */ },
};
@@ -2425,13 +2427,13 @@
{
int bit = pin & 0x1f;
- *pocctrl = pinmux_ioctrl_regs[IOCTRL30].reg;
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
return bit;
if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
return bit + 22;
- *pocctrl = pinmux_ioctrl_regs[IOCTRL31].reg;
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
return bit - 10;
if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))
diff --git a/drivers/pinctrl/renesas/pfc-r8a77980.c b/drivers/pinctrl/renesas/pfc-r8a77980.c
new file mode 100644
index 0000000..32efb44
--- /dev/null
+++ b/drivers/pinctrl/renesas/pfc-r8a77980.c
@@ -0,0 +1,2897 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * R8A77980 processor support - PFC hardware block.
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
+ *
+ * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+ *
+ * R-Car Gen3 processor support - PFC hardware block.
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <dm/pinctrl.h>
+#include <linux/kernel.h>
+
+#include "sh_pfc.h"
+
+#define CPU_ALL_PORT(fn, sfx) \
+ PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_28(1, fn, sfx), \
+ PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_25(4, fn, sfx), \
+ PORT_GP_15(5, fn, sfx)
+
+/*
+ * F_() : just information
+ * FM() : macro for FN_xxx / xxx_MARK
+ */
+
+/* GPSR0 */
+#define GPSR0_21 F_(DU_EXODDF_DU_ODDF_DISP_CDE, IP2_23_20)
+#define GPSR0_20 F_(DU_EXVSYNC_DU_VSYNC, IP2_19_16)
+#define GPSR0_19 F_(DU_EXHSYNC_DU_HSYNC, IP2_15_12)
+#define GPSR0_18 F_(DU_DOTCLKOUT, IP2_11_8)
+#define GPSR0_17 F_(DU_DB7, IP2_7_4)
+#define GPSR0_16 F_(DU_DB6, IP2_3_0)
+#define GPSR0_15 F_(DU_DB5, IP1_31_28)
+#define GPSR0_14 F_(DU_DB4, IP1_27_24)
+#define GPSR0_13 F_(DU_DB3, IP1_23_20)
+#define GPSR0_12 F_(DU_DB2, IP1_19_16)
+#define GPSR0_11 F_(DU_DG7, IP1_15_12)
+#define GPSR0_10 F_(DU_DG6, IP1_11_8)
+#define GPSR0_9 F_(DU_DG5, IP1_7_4)
+#define GPSR0_8 F_(DU_DG4, IP1_3_0)
+#define GPSR0_7 F_(DU_DG3, IP0_31_28)
+#define GPSR0_6 F_(DU_DG2, IP0_27_24)
+#define GPSR0_5 F_(DU_DR7, IP0_23_20)
+#define GPSR0_4 F_(DU_DR6, IP0_19_16)
+#define GPSR0_3 F_(DU_DR5, IP0_15_12)
+#define GPSR0_2 F_(DU_DR4, IP0_11_8)
+#define GPSR0_1 F_(DU_DR3, IP0_7_4)
+#define GPSR0_0 F_(DU_DR2, IP0_3_0)
+
+/* GPSR1 */
+#define GPSR1_27 F_(DIGRF_CLKOUT, IP8_31_28)
+#define GPSR1_26 F_(DIGRF_CLKIN, IP8_27_24)
+#define GPSR1_25 F_(CANFD_CLK_A, IP8_23_20)
+#define GPSR1_24 F_(CANFD1_RX, IP8_19_16)
+#define GPSR1_23 F_(CANFD1_TX, IP8_15_12)
+#define GPSR1_22 F_(CANFD0_RX_A, IP8_11_8)
+#define GPSR1_21 F_(CANFD0_TX_A, IP8_7_4)
+#define GPSR1_20 F_(AVB_AVTP_CAPTURE, IP8_3_0)
+#define GPSR1_19 F_(AVB_AVTP_MATCH, IP7_31_28)
+#define GPSR1_18 FM(AVB_LINK)
+#define GPSR1_17 FM(AVB_PHY_INT)
+#define GPSR1_16 FM(AVB_MAGIC)
+#define GPSR1_15 FM(AVB_MDC)
+#define GPSR1_14 FM(AVB_MDIO)
+#define GPSR1_13 FM(AVB_TXCREFCLK)
+#define GPSR1_12 FM(AVB_TD3)
+#define GPSR1_11 FM(AVB_TD2)
+#define GPSR1_10 FM(AVB_TD1)
+#define GPSR1_9 FM(AVB_TD0)
+#define GPSR1_8 FM(AVB_TXC)
+#define GPSR1_7 FM(AVB_TX_CTL)
+#define GPSR1_6 FM(AVB_RD3)
+#define GPSR1_5 FM(AVB_RD2)
+#define GPSR1_4 FM(AVB_RD1)
+#define GPSR1_3 FM(AVB_RD0)
+#define GPSR1_2 FM(AVB_RXC)
+#define GPSR1_1 FM(AVB_RX_CTL)
+#define GPSR1_0 F_(IRQ0, IP2_27_24)
+
+/* GPSR2 */
+#define GPSR2_29 F_(FSO_TOE_N, IP10_19_16)
+#define GPSR2_28 F_(FSO_CFE_1_N, IP10_15_12)
+#define GPSR2_27 F_(FSO_CFE_0_N, IP10_11_8)
+#define GPSR2_26 F_(SDA3, IP10_7_4)
+#define GPSR2_25 F_(SCL3, IP10_3_0)
+#define GPSR2_24 F_(MSIOF0_SS2, IP9_31_28)
+#define GPSR2_23 F_(MSIOF0_SS1, IP9_27_24)
+#define GPSR2_22 F_(MSIOF0_SYNC, IP9_23_20)
+#define GPSR2_21 F_(MSIOF0_SCK, IP9_19_16)
+#define GPSR2_20 F_(MSIOF0_TXD, IP9_15_12)
+#define GPSR2_19 F_(MSIOF0_RXD, IP9_11_8)
+#define GPSR2_18 F_(IRQ5, IP9_7_4)
+#define GPSR2_17 F_(IRQ4, IP9_3_0)
+#define GPSR2_16 F_(VI0_FIELD, IP4_31_28)
+#define GPSR2_15 F_(VI0_DATA11, IP4_27_24)
+#define GPSR2_14 F_(VI0_DATA10, IP4_23_20)
+#define GPSR2_13 F_(VI0_DATA9, IP4_19_16)
+#define GPSR2_12 F_(VI0_DATA8, IP4_15_12)
+#define GPSR2_11 F_(VI0_DATA7, IP4_11_8)
+#define GPSR2_10 F_(VI0_DATA6, IP4_7_4)
+#define GPSR2_9 F_(VI0_DATA5, IP4_3_0)
+#define GPSR2_8 F_(VI0_DATA4, IP3_31_28)
+#define GPSR2_7 F_(VI0_DATA3, IP3_27_24)
+#define GPSR2_6 F_(VI0_DATA2, IP3_23_20)
+#define GPSR2_5 F_(VI0_DATA1, IP3_19_16)
+#define GPSR2_4 F_(VI0_DATA0, IP3_15_12)
+#define GPSR2_3 F_(VI0_VSYNC_N, IP3_11_8)
+#define GPSR2_2 F_(VI0_HSYNC_N, IP3_7_4)
+#define GPSR2_1 F_(VI0_CLKENB, IP3_3_0)
+#define GPSR2_0 F_(VI0_CLK, IP2_31_28)
+
+/* GPSR3 */
+#define GPSR3_16 F_(VI1_FIELD, IP7_3_0)
+#define GPSR3_15 F_(VI1_DATA11, IP6_31_28)
+#define GPSR3_14 F_(VI1_DATA10, IP6_27_24)
+#define GPSR3_13 F_(VI1_DATA9, IP6_23_20)
+#define GPSR3_12 F_(VI1_DATA8, IP6_19_16)
+#define GPSR3_11 F_(VI1_DATA7, IP6_15_12)
+#define GPSR3_10 F_(VI1_DATA6, IP6_11_8)
+#define GPSR3_9 F_(VI1_DATA5, IP6_7_4)
+#define GPSR3_8 F_(VI1_DATA4, IP6_3_0)
+#define GPSR3_7 F_(VI1_DATA3, IP5_31_28)
+#define GPSR3_6 F_(VI1_DATA2, IP5_27_24)
+#define GPSR3_5 F_(VI1_DATA1, IP5_23_20)
+#define GPSR3_4 F_(VI1_DATA0, IP5_19_16)
+#define GPSR3_3 F_(VI1_VSYNC_N, IP5_15_12)
+#define GPSR3_2 F_(VI1_HSYNC_N, IP5_11_8)
+#define GPSR3_1 F_(VI1_CLKENB, IP5_7_4)
+#define GPSR3_0 F_(VI1_CLK, IP5_3_0)
+
+/* GPSR4 */
+#define GPSR4_24 FM(GETHER_LINK_A)
+#define GPSR4_23 FM(GETHER_PHY_INT_A)
+#define GPSR4_22 FM(GETHER_MAGIC)
+#define GPSR4_21 FM(GETHER_MDC_A)
+#define GPSR4_20 FM(GETHER_MDIO_A)
+#define GPSR4_19 FM(GETHER_TXCREFCLK_MEGA)
+#define GPSR4_18 FM(GETHER_TXCREFCLK)
+#define GPSR4_17 FM(GETHER_TD3)
+#define GPSR4_16 FM(GETHER_TD2)
+#define GPSR4_15 FM(GETHER_TD1)
+#define GPSR4_14 FM(GETHER_TD0)
+#define GPSR4_13 FM(GETHER_TXC)
+#define GPSR4_12 FM(GETHER_TX_CTL)
+#define GPSR4_11 FM(GETHER_RD3)
+#define GPSR4_10 FM(GETHER_RD2)
+#define GPSR4_9 FM(GETHER_RD1)
+#define GPSR4_8 FM(GETHER_RD0)
+#define GPSR4_7 FM(GETHER_RXC)
+#define GPSR4_6 FM(GETHER_RX_CTL)
+#define GPSR4_5 F_(SDA2, IP7_27_24)
+#define GPSR4_4 F_(SCL2, IP7_23_20)
+#define GPSR4_3 F_(SDA1, IP7_19_16)
+#define GPSR4_2 F_(SCL1, IP7_15_12)
+#define GPSR4_1 F_(SDA0, IP7_11_8)
+#define GPSR4_0 F_(SCL0, IP7_7_4)
+
+/* GPSR5 */
+#define GPSR5_14 FM(RPC_INT_N)
+#define GPSR5_13 FM(RPC_WP_N)
+#define GPSR5_12 FM(RPC_RESET_N)
+#define GPSR5_11 FM(QSPI1_SSL)
+#define GPSR5_10 FM(QSPI1_IO3)
+#define GPSR5_9 FM(QSPI1_IO2)
+#define GPSR5_8 FM(QSPI1_MISO_IO1)
+#define GPSR5_7 FM(QSPI1_MOSI_IO0)
+#define GPSR5_6 FM(QSPI1_SPCLK)
+#define GPSR5_5 FM(QSPI0_SSL)
+#define GPSR5_4 FM(QSPI0_IO3)
+#define GPSR5_3 FM(QSPI0_IO2)
+#define GPSR5_2 FM(QSPI0_MISO_IO1)
+#define GPSR5_1 FM(QSPI0_MOSI_IO0)
+#define GPSR5_0 FM(QSPI0_SPCLK)
+
+
+/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
+#define IP0_3_0 FM(DU_DR2) FM(SCK4) FM(GETHER_RMII_CRS_DV) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_7_4 FM(DU_DR3) FM(RX4) FM(GETHER_RMII_RX_ER) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_11_8 FM(DU_DR4) FM(TX4) FM(GETHER_RMII_RXD0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_15_12 FM(DU_DR5) FM(CTS4_N) FM(GETHER_RMII_RXD1) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_19_16 FM(DU_DR6) FM(RTS4_N) FM(GETHER_RMII_TXD_EN) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_23_20 FM(DU_DR7) F_(0, 0) FM(GETHER_RMII_TXD0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_27_24 FM(DU_DG2) F_(0, 0) FM(GETHER_RMII_TXD1) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_31_28 FM(DU_DG3) FM(CPG_CPCKOUT) FM(GETHER_RMII_REFCLK) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_3_0 FM(DU_DG4) FM(SCL5) F_(0, 0) FM(A8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_7_4 FM(DU_DG5) FM(SDA5) FM(GETHER_MDC_B) FM(A9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_11_8 FM(DU_DG6) FM(SCIF_CLK_A) FM(GETHER_MDIO_B) FM(A10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_15_12 FM(DU_DG7) FM(HRX0_A) F_(0, 0) FM(A11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_19_16 FM(DU_DB2) FM(HSCK0_A) F_(0, 0) FM(A12) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_23_20 FM(DU_DB3) FM(HRTS0_N_A) F_(0, 0) FM(A13) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_27_24 FM(DU_DB4) FM(HCTS0_N_A) F_(0, 0) FM(A14) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_31_28 FM(DU_DB5) FM(HTX0_A) FM(PWM0_A) FM(A15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_3_0 FM(DU_DB6) FM(MSIOF3_RXD) F_(0, 0) FM(A16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_7_4 FM(DU_DB7) FM(MSIOF3_TXD) F_(0, 0) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_11_8 FM(DU_DOTCLKOUT) FM(MSIOF3_SS1) FM(GETHER_LINK_B) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(MSIOF3_SS2) FM(GETHER_PHY_INT_B) FM(A19) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_27_24 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_23_20 FM(VI0_DATA2) FM(AVB_AVTP_PPS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_27_24 FM(VI0_DATA11) FM(HTX2) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_31_28 FM(VI0_FIELD) FM(HRX2) FM(PWM4_A) FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_3_0 FM(VI1_CLK) FM(MSIOF1_RXD) F_(0, 0) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_7_4 FM(VI1_CLKENB) FM(MSIOF1_TXD) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_11_8 FM(VI1_HSYNC_N) FM(MSIOF1_SCK) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_15_12 FM(VI1_VSYNC_N) FM(MSIOF1_SYNC) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_19_16 FM(VI1_DATA0) FM(MSIOF1_SS1) F_(0, 0) FM(D3) FM(MMC_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_23_20 FM(VI1_DATA1) FM(MSIOF1_SS2) F_(0, 0) FM(D4) FM(MMC_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_31_28 FM(VI1_DATA3) FM(CANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_3_0 FM(VI1_DATA4) FM(CANFD_CLK_B) F_(0, 0) FM(D7) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_7_4 FM(VI1_DATA5) F_(0, 0) F_(0, 0) FM(D8) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_11_8 FM(VI1_DATA6) F_(0, 0) F_(0, 0) FM(D9) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_15_12 FM(VI1_DATA7) F_(0, 0) F_(0, 0) FM(D10) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_19_16 FM(VI1_DATA8) F_(0, 0) F_(0, 0) FM(D11) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_23_20 FM(VI1_DATA9) FM(TCLK1_A) F_(0, 0) FM(D12) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_27_24 FM(VI1_DATA10) FM(TCLK2_A) F_(0, 0) FM(D13) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_31_28 FM(VI1_DATA11) FM(SCL4) F_(0, 0) FM(D14) FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_3_0 FM(VI1_FIELD) FM(SDA4) F_(0, 0) FM(D15) FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_7_4 FM(SCL0) F_(0, 0) F_(0, 0) FM(CLKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_11_8 FM(SDA0) F_(0, 0) F_(0, 0) FM(BS_N) FM(SCK0) FM(HSCK0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_15_12 FM(SCL1) F_(0, 0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(HCTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_19_16 FM(SDA1) F_(0, 0) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N) FM(HRTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_23_20 FM(SCL2) F_(0, 0) F_(0, 0) FM(WE1_N) FM(RX0) FM(HRX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_27_24 FM(SDA2) F_(0, 0) F_(0, 0) FM(EX_WAIT0) FM(TX0) FM(HTX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_31_28 FM(AVB_AVTP_MATCH) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_3_0 FM(AVB_AVTP_CAPTURE) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_7_4 FM(CANFD0_TX_A) FM(FXR_TXDA) FM(PWM0_B) FM(DU_DISP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_11_8 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_15_12 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_19_16 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_23_20 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_27_24 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_31_28 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_3_0 FM(IRQ4) F_(0, 0) F_(0, 0) FM(VI0_DATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_7_4 FM(IRQ5) F_(0, 0) F_(0, 0) FM(VI0_DATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_11_8 FM(MSIOF0_RXD) FM(DU_DR0) F_(0, 0) FM(VI0_DATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_15_12 FM(MSIOF0_TXD) FM(DU_DR1) F_(0, 0) FM(VI0_DATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_19_16 FM(MSIOF0_SCK) FM(DU_DG0) F_(0, 0) FM(VI0_DATA16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_23_20 FM(MSIOF0_SYNC) FM(DU_DG1) F_(0, 0) FM(VI0_DATA17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_27_24 FM(MSIOF0_SS1) FM(DU_DB0) FM(TCLK3) FM(VI0_DATA18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_31_28 FM(MSIOF0_SS2) FM(DU_DB1) FM(TCLK4) FM(VI0_DATA19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_3_0 FM(SCL3) F_(0, 0) F_(0, 0) FM(VI0_DATA20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_7_4 FM(SDA3) F_(0, 0) F_(0, 0) FM(VI0_DATA21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_11_8 FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) FM(VI0_DATA22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_15_12 FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) FM(VI0_DATA23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_19_16 FM(FSO_TOE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+#define PINMUX_GPSR \
+\
+ GPSR2_29 \
+ GPSR2_28 \
+ GPSR1_27 GPSR2_27 \
+ GPSR1_26 GPSR2_26 \
+ GPSR1_25 GPSR2_25 \
+ GPSR1_24 GPSR2_24 GPSR4_24 \
+ GPSR1_23 GPSR2_23 GPSR4_23 \
+ GPSR1_22 GPSR2_22 GPSR4_22 \
+GPSR0_21 GPSR1_21 GPSR2_21 GPSR4_21 \
+GPSR0_20 GPSR1_20 GPSR2_20 GPSR4_20 \
+GPSR0_19 GPSR1_19 GPSR2_19 GPSR4_19 \
+GPSR0_18 GPSR1_18 GPSR2_18 GPSR4_18 \
+GPSR0_17 GPSR1_17 GPSR2_17 GPSR4_17 \
+GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 GPSR4_16 \
+GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR4_15 \
+GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 \
+GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 \
+GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 \
+GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 \
+GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 \
+GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 \
+GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 \
+GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 \
+GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 \
+GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 \
+GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 \
+GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 \
+GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 \
+GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 \
+GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0
+
+#define PINMUX_IPSR \
+\
+FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
+FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
+FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
+FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
+FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
+FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
+FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
+FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
+\
+FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
+FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
+FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
+FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
+FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
+FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
+FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
+FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
+\
+FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 \
+FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 \
+FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 \
+FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 \
+FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 \
+FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 \
+FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 \
+FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28
+
+/* MOD_SEL0 */ /* 0 */ /* 1 */
+#define MOD_SEL0_11 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
+#define MOD_SEL0_10 FM(SEL_GETHER_0) FM(SEL_GETHER_1)
+#define MOD_SEL0_9 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1)
+#define MOD_SEL0_8 FM(SEL_PWM0_0) FM(SEL_PWM0_1)
+#define MOD_SEL0_7 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
+#define MOD_SEL0_6 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
+#define MOD_SEL0_5 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
+#define MOD_SEL0_4 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
+#define MOD_SEL0_2 FM(SEL_RSP_0) FM(SEL_RSP_1)
+#define MOD_SEL0_1 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
+#define MOD_SEL0_0 FM(SEL_TMU_0) FM(SEL_TMU_1)
+
+#define PINMUX_MOD_SELS \
+\
+MOD_SEL0_11 \
+MOD_SEL0_10 \
+MOD_SEL0_9 \
+MOD_SEL0_8 \
+MOD_SEL0_7 \
+MOD_SEL0_6 \
+MOD_SEL0_5 \
+MOD_SEL0_4 \
+MOD_SEL0_2 \
+MOD_SEL0_1 \
+MOD_SEL0_0
+
+enum {
+ PINMUX_RESERVED = 0,
+
+ PINMUX_DATA_BEGIN,
+ GP_ALL(DATA),
+ PINMUX_DATA_END,
+
+#define F_(x, y)
+#define FM(x) FN_##x,
+ PINMUX_FUNCTION_BEGIN,
+ GP_ALL(FN),
+ PINMUX_GPSR
+ PINMUX_IPSR
+ PINMUX_MOD_SELS
+ PINMUX_FUNCTION_END,
+#undef F_
+#undef FM
+
+#define F_(x, y)
+#define FM(x) x##_MARK,
+ PINMUX_MARK_BEGIN,
+ PINMUX_GPSR
+ PINMUX_IPSR
+ PINMUX_MOD_SELS
+ PINMUX_MARK_END,
+#undef F_
+#undef FM
+};
+
+static const u16 pinmux_data[] = {
+ PINMUX_DATA_GP_ALL(),
+
+ PINMUX_SINGLE(AVB_RX_CTL),
+ PINMUX_SINGLE(AVB_RXC),
+ PINMUX_SINGLE(AVB_RD0),
+ PINMUX_SINGLE(AVB_RD1),
+ PINMUX_SINGLE(AVB_RD2),
+ PINMUX_SINGLE(AVB_RD3),
+ PINMUX_SINGLE(AVB_TX_CTL),
+ PINMUX_SINGLE(AVB_TXC),
+ PINMUX_SINGLE(AVB_TD0),
+ PINMUX_SINGLE(AVB_TD1),
+ PINMUX_SINGLE(AVB_TD2),
+ PINMUX_SINGLE(AVB_TD3),
+ PINMUX_SINGLE(AVB_TXCREFCLK),
+ PINMUX_SINGLE(AVB_MDIO),
+ PINMUX_SINGLE(AVB_MDC),
+ PINMUX_SINGLE(AVB_MAGIC),
+ PINMUX_SINGLE(AVB_PHY_INT),
+ PINMUX_SINGLE(AVB_LINK),
+
+ PINMUX_SINGLE(GETHER_RX_CTL),
+ PINMUX_SINGLE(GETHER_RXC),
+ PINMUX_SINGLE(GETHER_RD0),
+ PINMUX_SINGLE(GETHER_RD1),
+ PINMUX_SINGLE(GETHER_RD2),
+ PINMUX_SINGLE(GETHER_RD3),
+ PINMUX_SINGLE(GETHER_TX_CTL),
+ PINMUX_SINGLE(GETHER_TXC),
+ PINMUX_SINGLE(GETHER_TD0),
+ PINMUX_SINGLE(GETHER_TD1),
+ PINMUX_SINGLE(GETHER_TD2),
+ PINMUX_SINGLE(GETHER_TD3),
+ PINMUX_SINGLE(GETHER_TXCREFCLK),
+ PINMUX_SINGLE(GETHER_TXCREFCLK_MEGA),
+ PINMUX_SINGLE(GETHER_MDIO_A),
+ PINMUX_SINGLE(GETHER_MDC_A),
+ PINMUX_SINGLE(GETHER_MAGIC),
+ PINMUX_SINGLE(GETHER_PHY_INT_A),
+ PINMUX_SINGLE(GETHER_LINK_A),
+
+ PINMUX_SINGLE(QSPI0_SPCLK),
+ PINMUX_SINGLE(QSPI0_MOSI_IO0),
+ PINMUX_SINGLE(QSPI0_MISO_IO1),
+ PINMUX_SINGLE(QSPI0_IO2),
+ PINMUX_SINGLE(QSPI0_IO3),
+ PINMUX_SINGLE(QSPI0_SSL),
+ PINMUX_SINGLE(QSPI1_SPCLK),
+ PINMUX_SINGLE(QSPI1_MOSI_IO0),
+ PINMUX_SINGLE(QSPI1_MISO_IO1),
+ PINMUX_SINGLE(QSPI1_IO2),
+ PINMUX_SINGLE(QSPI1_IO3),
+ PINMUX_SINGLE(QSPI1_SSL),
+ PINMUX_SINGLE(RPC_RESET_N),
+ PINMUX_SINGLE(RPC_WP_N),
+ PINMUX_SINGLE(RPC_INT_N),
+
+ /* IPSR0 */
+ PINMUX_IPSR_GPSR(IP0_3_0, DU_DR2),
+ PINMUX_IPSR_GPSR(IP0_3_0, SCK4),
+ PINMUX_IPSR_GPSR(IP0_3_0, GETHER_RMII_CRS_DV),
+ PINMUX_IPSR_GPSR(IP0_3_0, A0),
+
+ PINMUX_IPSR_GPSR(IP0_7_4, DU_DR3),
+ PINMUX_IPSR_GPSR(IP0_7_4, RX4),
+ PINMUX_IPSR_GPSR(IP0_7_4, GETHER_RMII_RX_ER),
+ PINMUX_IPSR_GPSR(IP0_7_4, A1),
+
+ PINMUX_IPSR_GPSR(IP0_11_8, DU_DR4),
+ PINMUX_IPSR_GPSR(IP0_11_8, TX4),
+ PINMUX_IPSR_GPSR(IP0_11_8, GETHER_RMII_RXD0),
+ PINMUX_IPSR_GPSR(IP0_11_8, A2),
+
+ PINMUX_IPSR_GPSR(IP0_15_12, DU_DR5),
+ PINMUX_IPSR_GPSR(IP0_15_12, CTS4_N),
+ PINMUX_IPSR_GPSR(IP0_15_12, GETHER_RMII_RXD1),
+ PINMUX_IPSR_GPSR(IP0_15_12, A3),
+
+ PINMUX_IPSR_GPSR(IP0_19_16, DU_DR6),
+ PINMUX_IPSR_GPSR(IP0_19_16, RTS4_N),
+ PINMUX_IPSR_GPSR(IP0_19_16, GETHER_RMII_TXD_EN),
+ PINMUX_IPSR_GPSR(IP0_19_16, A4),
+
+ PINMUX_IPSR_GPSR(IP0_23_20, DU_DR7),
+ PINMUX_IPSR_GPSR(IP0_23_20, GETHER_RMII_TXD0),
+ PINMUX_IPSR_GPSR(IP0_23_20, A5),
+
+ PINMUX_IPSR_GPSR(IP0_27_24, DU_DG2),
+ PINMUX_IPSR_GPSR(IP0_27_24, GETHER_RMII_TXD1),
+ PINMUX_IPSR_GPSR(IP0_27_24, A6),
+
+ PINMUX_IPSR_GPSR(IP0_31_28, DU_DG3),
+ PINMUX_IPSR_GPSR(IP0_31_28, CPG_CPCKOUT),
+ PINMUX_IPSR_GPSR(IP0_31_28, GETHER_RMII_REFCLK),
+ PINMUX_IPSR_GPSR(IP0_31_28, A7),
+ PINMUX_IPSR_GPSR(IP0_31_28, PWMFSW0),
+
+ /* IPSR1 */
+ PINMUX_IPSR_GPSR(IP1_3_0, DU_DG4),
+ PINMUX_IPSR_GPSR(IP1_3_0, SCL5),
+ PINMUX_IPSR_GPSR(IP1_3_0, A8),
+
+ PINMUX_IPSR_GPSR(IP1_7_4, DU_DG5),
+ PINMUX_IPSR_GPSR(IP1_7_4, SDA5),
+ PINMUX_IPSR_MSEL(IP1_7_4, GETHER_MDC_B, SEL_GETHER_1),
+ PINMUX_IPSR_GPSR(IP1_7_4, A9),
+
+ PINMUX_IPSR_GPSR(IP1_11_8, DU_DG6),
+ PINMUX_IPSR_MSEL(IP1_11_8, SCIF_CLK_A, SEL_HSCIF0_0),
+ PINMUX_IPSR_MSEL(IP1_11_8, GETHER_MDIO_B, SEL_GETHER_1),
+ PINMUX_IPSR_GPSR(IP1_11_8, A10),
+
+ PINMUX_IPSR_GPSR(IP1_15_12, DU_DG7),
+ PINMUX_IPSR_MSEL(IP1_15_12, HRX0_A, SEL_HSCIF0_0),
+ PINMUX_IPSR_GPSR(IP1_15_12, A11),
+
+ PINMUX_IPSR_GPSR(IP1_19_16, DU_DB2),
+ PINMUX_IPSR_MSEL(IP1_19_16, HSCK0_A, SEL_HSCIF0_0),
+ PINMUX_IPSR_GPSR(IP1_19_16, A12),
+ PINMUX_IPSR_GPSR(IP1_19_16, IRQ1),
+
+ PINMUX_IPSR_GPSR(IP1_23_20, DU_DB3),
+ PINMUX_IPSR_MSEL(IP1_23_20, HRTS0_N_A, SEL_HSCIF0_0),
+ PINMUX_IPSR_GPSR(IP1_23_20, A13),
+ PINMUX_IPSR_GPSR(IP1_23_20, IRQ2),
+
+ PINMUX_IPSR_GPSR(IP1_27_24, DU_DB4),
+ PINMUX_IPSR_MSEL(IP1_27_24, HCTS0_N_A, SEL_HSCIF0_0),
+ PINMUX_IPSR_GPSR(IP1_27_24, A14),
+ PINMUX_IPSR_GPSR(IP1_27_24, IRQ3),
+
+ PINMUX_IPSR_GPSR(IP1_31_28, DU_DB5),
+ PINMUX_IPSR_MSEL(IP1_31_28, HTX0_A, SEL_HSCIF0_0),
+ PINMUX_IPSR_MSEL(IP1_31_28, PWM0_A, SEL_PWM0_0),
+ PINMUX_IPSR_GPSR(IP1_31_28, A15),
+
+ /* IPSR2 */
+ PINMUX_IPSR_GPSR(IP2_3_0, DU_DB6),
+ PINMUX_IPSR_GPSR(IP2_3_0, MSIOF3_RXD),
+ PINMUX_IPSR_GPSR(IP2_3_0, A16),
+
+ PINMUX_IPSR_GPSR(IP2_7_4, DU_DB7),
+ PINMUX_IPSR_GPSR(IP2_7_4, MSIOF3_TXD),
+ PINMUX_IPSR_GPSR(IP2_7_4, A17),
+
+ PINMUX_IPSR_GPSR(IP2_11_8, DU_DOTCLKOUT),
+ PINMUX_IPSR_GPSR(IP2_11_8, MSIOF3_SS1),
+ PINMUX_IPSR_MSEL(IP2_11_8, GETHER_LINK_B, SEL_GETHER_1),
+ PINMUX_IPSR_GPSR(IP2_11_8, A18),
+
+ PINMUX_IPSR_GPSR(IP2_15_12, DU_EXHSYNC_DU_HSYNC),
+ PINMUX_IPSR_GPSR(IP2_15_12, MSIOF3_SS2),
+ PINMUX_IPSR_MSEL(IP2_15_12, GETHER_PHY_INT_B, SEL_GETHER_1),
+ PINMUX_IPSR_GPSR(IP2_15_12, A19),
+ PINMUX_IPSR_GPSR(IP2_15_12, FXR_TXENA_N),
+
+ PINMUX_IPSR_GPSR(IP2_19_16, DU_EXVSYNC_DU_VSYNC),
+ PINMUX_IPSR_GPSR(IP2_19_16, MSIOF3_SCK),
+ PINMUX_IPSR_GPSR(IP2_19_16, FXR_TXENB_N),
+
+ PINMUX_IPSR_GPSR(IP2_23_20, DU_EXODDF_DU_ODDF_DISP_CDE),
+ PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC),
+
+ PINMUX_IPSR_GPSR(IP2_27_24, IRQ0),
+
+ PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK),
+ PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK),
+ PINMUX_IPSR_GPSR(IP2_31_28, SCK3),
+ PINMUX_IPSR_GPSR(IP2_31_28, HSCK3),
+
+ /* IPSR3 */
+ PINMUX_IPSR_GPSR(IP3_3_0, VI0_CLKENB),
+ PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_RXD),
+ PINMUX_IPSR_GPSR(IP3_3_0, RX3),
+ PINMUX_IPSR_GPSR(IP3_3_0, RD_WR_N),
+ PINMUX_IPSR_GPSR(IP3_3_0, HCTS3_N),
+
+ PINMUX_IPSR_GPSR(IP3_7_4, VI0_HSYNC_N),
+ PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
+ PINMUX_IPSR_GPSR(IP3_7_4, TX3),
+ PINMUX_IPSR_GPSR(IP3_7_4, HRTS3_N),
+
+ PINMUX_IPSR_GPSR(IP3_11_8, VI0_VSYNC_N),
+ PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_SYNC),
+ PINMUX_IPSR_GPSR(IP3_11_8, CTS3_N),
+ PINMUX_IPSR_GPSR(IP3_11_8, HTX3),
+
+ PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0),
+ PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1),
+ PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N),
+ PINMUX_IPSR_GPSR(IP3_15_12, HRX3),
+
+ PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1),
+ PINMUX_IPSR_GPSR(IP3_19_16, MSIOF2_SS2),
+ PINMUX_IPSR_GPSR(IP3_19_16, SCK1),
+ PINMUX_IPSR_MSEL(IP3_19_16, SPEEDIN_A, SEL_RSP_0),
+
+ PINMUX_IPSR_GPSR(IP3_23_20, VI0_DATA2),
+ PINMUX_IPSR_GPSR(IP3_23_20, AVB_AVTP_PPS),
+
+ PINMUX_IPSR_GPSR(IP3_27_24, VI0_DATA3),
+ PINMUX_IPSR_GPSR(IP3_27_24, HSCK1),
+
+ PINMUX_IPSR_GPSR(IP3_31_28, VI0_DATA4),
+ PINMUX_IPSR_GPSR(IP3_31_28, HRTS1_N),
+ PINMUX_IPSR_MSEL(IP3_31_28, RX1_A, SEL_SCIF1_0),
+
+ /* IPSR4 */
+ PINMUX_IPSR_GPSR(IP4_3_0, VI0_DATA5),
+ PINMUX_IPSR_GPSR(IP4_3_0, HCTS1_N),
+ PINMUX_IPSR_MSEL(IP4_3_0, TX1_A, SEL_SCIF1_0),
+
+ PINMUX_IPSR_GPSR(IP4_7_4, VI0_DATA6),
+ PINMUX_IPSR_GPSR(IP4_7_4, HTX1),
+ PINMUX_IPSR_GPSR(IP4_7_4, CTS1_N),
+
+ PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7),
+ PINMUX_IPSR_GPSR(IP4_11_8, HRX1),
+ PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N),
+
+ PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8),
+ PINMUX_IPSR_GPSR(IP4_15_12, HSCK2),
+
+ PINMUX_IPSR_GPSR(IP4_19_16, VI0_DATA9),
+ PINMUX_IPSR_GPSR(IP4_19_16, HCTS2_N),
+ PINMUX_IPSR_MSEL(IP4_19_16, PWM1_A, SEL_PWM1_0),
+
+ PINMUX_IPSR_GPSR(IP4_23_20, VI0_DATA10),
+ PINMUX_IPSR_GPSR(IP4_23_20, HRTS2_N),
+ PINMUX_IPSR_MSEL(IP4_23_20, PWM2_A, SEL_PWM2_0),
+
+ PINMUX_IPSR_GPSR(IP4_27_24, VI0_DATA11),
+ PINMUX_IPSR_GPSR(IP4_27_24, HTX2),
+ PINMUX_IPSR_MSEL(IP4_27_24, PWM3_A, SEL_PWM3_0),
+
+ PINMUX_IPSR_GPSR(IP4_31_28, VI0_FIELD),
+ PINMUX_IPSR_GPSR(IP4_31_28, HRX2),
+ PINMUX_IPSR_MSEL(IP4_31_28, PWM4_A, SEL_PWM4_0),
+ PINMUX_IPSR_GPSR(IP4_31_28, CS1_N),
+
+ /* IPSR5 */
+ PINMUX_IPSR_GPSR(IP5_3_0, VI1_CLK),
+ PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD),
+ PINMUX_IPSR_GPSR(IP5_3_0, CS0_N),
+
+ PINMUX_IPSR_GPSR(IP5_7_4, VI1_CLKENB),
+ PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD),
+ PINMUX_IPSR_GPSR(IP5_7_4, D0),
+
+ PINMUX_IPSR_GPSR(IP5_11_8, VI1_HSYNC_N),
+ PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK),
+ PINMUX_IPSR_GPSR(IP5_11_8, D1),
+
+ PINMUX_IPSR_GPSR(IP5_15_12, VI1_VSYNC_N),
+ PINMUX_IPSR_GPSR(IP5_15_12, MSIOF1_SYNC),
+ PINMUX_IPSR_GPSR(IP5_15_12, D2),
+
+ PINMUX_IPSR_GPSR(IP5_19_16, VI1_DATA0),
+ PINMUX_IPSR_GPSR(IP5_19_16, MSIOF1_SS1),
+ PINMUX_IPSR_GPSR(IP5_19_16, D3),
+ PINMUX_IPSR_GPSR(IP5_19_16, MMC_WP),
+
+ PINMUX_IPSR_GPSR(IP5_23_20, VI1_DATA1),
+ PINMUX_IPSR_GPSR(IP5_23_20, MSIOF1_SS2),
+ PINMUX_IPSR_GPSR(IP5_23_20, D4),
+ PINMUX_IPSR_GPSR(IP5_23_20, MMC_CD),
+
+ PINMUX_IPSR_GPSR(IP5_27_24, VI1_DATA2),
+ PINMUX_IPSR_MSEL(IP5_27_24, CANFD0_TX_B, SEL_CANFD0_1),
+ PINMUX_IPSR_GPSR(IP5_27_24, D5),
+ PINMUX_IPSR_GPSR(IP5_27_24, MMC_DS),
+
+ PINMUX_IPSR_GPSR(IP5_31_28, VI1_DATA3),
+ PINMUX_IPSR_MSEL(IP5_31_28, CANFD0_RX_B, SEL_CANFD0_1),
+ PINMUX_IPSR_GPSR(IP5_31_28, D6),
+ PINMUX_IPSR_GPSR(IP5_31_28, MMC_CMD),
+
+ /* IPSR6 */
+ PINMUX_IPSR_GPSR(IP6_3_0, VI1_DATA4),
+ PINMUX_IPSR_MSEL(IP6_3_0, CANFD_CLK_B, SEL_CANFD0_1),
+ PINMUX_IPSR_GPSR(IP6_3_0, D7),
+ PINMUX_IPSR_GPSR(IP6_3_0, MMC_D0),
+
+ PINMUX_IPSR_GPSR(IP6_7_4, VI1_DATA5),
+ PINMUX_IPSR_GPSR(IP6_7_4, D8),
+ PINMUX_IPSR_GPSR(IP6_7_4, MMC_D1),
+
+ PINMUX_IPSR_GPSR(IP6_11_8, VI1_DATA6),
+ PINMUX_IPSR_GPSR(IP6_11_8, D9),
+ PINMUX_IPSR_GPSR(IP6_11_8, MMC_D2),
+
+ PINMUX_IPSR_GPSR(IP6_15_12, VI1_DATA7),
+ PINMUX_IPSR_GPSR(IP6_15_12, D10),
+ PINMUX_IPSR_GPSR(IP6_15_12, MMC_D3),
+
+ PINMUX_IPSR_GPSR(IP6_19_16, VI1_DATA8),
+ PINMUX_IPSR_GPSR(IP6_19_16, D11),
+ PINMUX_IPSR_GPSR(IP6_19_16, MMC_CLK),
+
+ PINMUX_IPSR_GPSR(IP6_23_20, VI1_DATA9),
+ PINMUX_IPSR_MSEL(IP6_23_20, TCLK1_A, SEL_TMU_0),
+ PINMUX_IPSR_GPSR(IP6_23_20, D12),
+ PINMUX_IPSR_GPSR(IP6_23_20, MMC_D4),
+
+ PINMUX_IPSR_GPSR(IP6_27_24, VI1_DATA10),
+ PINMUX_IPSR_MSEL(IP6_27_24, TCLK2_A, SEL_TMU_0),
+ PINMUX_IPSR_GPSR(IP6_27_24, D13),
+ PINMUX_IPSR_GPSR(IP6_27_24, MMC_D5),
+
+ PINMUX_IPSR_GPSR(IP6_31_28, VI1_DATA11),
+ PINMUX_IPSR_GPSR(IP6_31_28, SCL4),
+ PINMUX_IPSR_GPSR(IP6_31_28, D14),
+ PINMUX_IPSR_GPSR(IP6_31_28, MMC_D6),
+
+ /* IPSR7 */
+ PINMUX_IPSR_GPSR(IP7_3_0, VI1_FIELD),
+ PINMUX_IPSR_GPSR(IP7_3_0, SDA4),
+ PINMUX_IPSR_GPSR(IP7_3_0, D15),
+ PINMUX_IPSR_GPSR(IP7_3_0, MMC_D7),
+
+ PINMUX_IPSR_GPSR(IP7_7_4, SCL0),
+ PINMUX_IPSR_GPSR(IP7_7_4, CLKOUT),
+
+ PINMUX_IPSR_GPSR(IP7_11_8, SDA0),
+ PINMUX_IPSR_GPSR(IP7_11_8, BS_N),
+ PINMUX_IPSR_GPSR(IP7_11_8, SCK0),
+ PINMUX_IPSR_MSEL(IP7_11_8, HSCK0_B, SEL_HSCIF0_1),
+
+ PINMUX_IPSR_GPSR(IP7_15_12, SCL1),
+ PINMUX_IPSR_GPSR(IP7_15_12, TPU0TO2),
+ PINMUX_IPSR_GPSR(IP7_15_12, RD_N),
+ PINMUX_IPSR_GPSR(IP7_15_12, CTS0_N),
+ PINMUX_IPSR_GPSR(IP7_15_12, HCTS0_N_B),
+
+ PINMUX_IPSR_GPSR(IP7_19_16, SDA1),
+ PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3),
+ PINMUX_IPSR_GPSR(IP7_19_16, WE0_N),
+ PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N),
+ PINMUX_IPSR_MSEL(IP1_23_20, HRTS0_N_B, SEL_HSCIF0_1),
+
+ PINMUX_IPSR_GPSR(IP7_23_20, SCL2),
+ PINMUX_IPSR_GPSR(IP7_23_20, WE1_N),
+ PINMUX_IPSR_GPSR(IP7_23_20, RX0),
+ PINMUX_IPSR_MSEL(IP7_23_20, HRX0_B, SEL_HSCIF0_1),
+
+ PINMUX_IPSR_GPSR(IP7_27_24, SDA2),
+ PINMUX_IPSR_GPSR(IP7_27_24, EX_WAIT0),
+ PINMUX_IPSR_GPSR(IP7_27_24, TX0),
+ PINMUX_IPSR_MSEL(IP7_27_24, HTX0_B, SEL_HSCIF0_1),
+
+ PINMUX_IPSR_GPSR(IP7_31_28, AVB_AVTP_MATCH),
+ PINMUX_IPSR_GPSR(IP7_31_28, TPU0TO0),
+
+ /* IPSR8 */
+ PINMUX_IPSR_GPSR(IP8_3_0, AVB_AVTP_CAPTURE),
+ PINMUX_IPSR_GPSR(IP8_3_0, TPU0TO1),
+
+ PINMUX_IPSR_MSEL(IP8_7_4, CANFD0_TX_A, SEL_CANFD0_0),
+ PINMUX_IPSR_GPSR(IP8_7_4, FXR_TXDA),
+ PINMUX_IPSR_MSEL(IP8_7_4, PWM0_B, SEL_PWM0_1),
+ PINMUX_IPSR_GPSR(IP8_7_4, DU_DISP),
+
+ PINMUX_IPSR_MSEL(IP8_11_8, CANFD0_RX_A, SEL_CANFD0_0),
+ PINMUX_IPSR_GPSR(IP8_11_8, RXDA_EXTFXR),
+ PINMUX_IPSR_MSEL(IP8_11_8, PWM1_B, SEL_PWM1_1),
+ PINMUX_IPSR_GPSR(IP8_11_8, DU_CDE),
+
+ PINMUX_IPSR_GPSR(IP8_15_12, CANFD1_TX),
+ PINMUX_IPSR_GPSR(IP8_15_12, FXR_TXDB),
+ PINMUX_IPSR_MSEL(IP8_15_12, PWM2_B, SEL_PWM2_1),
+ PINMUX_IPSR_MSEL(IP8_15_12, TCLK1_B, SEL_TMU_1),
+ PINMUX_IPSR_MSEL(IP8_15_12, TX1_B, SEL_SCIF1_1),
+
+ PINMUX_IPSR_GPSR(IP8_19_16, CANFD1_RX),
+ PINMUX_IPSR_GPSR(IP8_19_16, RXDB_EXTFXR),
+ PINMUX_IPSR_MSEL(IP8_19_16, PWM3_B, SEL_PWM3_1),
+ PINMUX_IPSR_MSEL(IP8_19_16, TCLK2_B, SEL_TMU_1),
+ PINMUX_IPSR_MSEL(IP8_19_16, RX1_B, SEL_SCIF1_1),
+
+ PINMUX_IPSR_MSEL(IP8_23_20, CANFD_CLK_A, SEL_CANFD0_0),
+ PINMUX_IPSR_GPSR(IP8_23_20, CLK_EXTFXR),
+ PINMUX_IPSR_MSEL(IP8_23_20, PWM4_B, SEL_PWM4_1),
+ PINMUX_IPSR_MSEL(IP8_23_20, SPEEDIN_B, SEL_RSP_1),
+ PINMUX_IPSR_MSEL(IP8_23_20, SCIF_CLK_B, SEL_HSCIF0_1),
+
+ PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKIN),
+ PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKEN_IN),
+
+ PINMUX_IPSR_GPSR(IP8_31_28, DIGRF_CLKOUT),
+ PINMUX_IPSR_GPSR(IP8_31_28, DIGRF_CLKEN_OUT),
+
+ /* IPSR9 */
+ PINMUX_IPSR_GPSR(IP9_3_0, IRQ4),
+ PINMUX_IPSR_GPSR(IP9_3_0, VI0_DATA12),
+
+ PINMUX_IPSR_GPSR(IP9_7_4, IRQ5),
+ PINMUX_IPSR_GPSR(IP9_7_4, VI0_DATA13),
+
+ PINMUX_IPSR_GPSR(IP9_11_8, MSIOF0_RXD),
+ PINMUX_IPSR_GPSR(IP9_11_8, DU_DR0),
+ PINMUX_IPSR_GPSR(IP9_11_8, VI0_DATA14),
+
+ PINMUX_IPSR_GPSR(IP9_15_12, MSIOF0_TXD),
+ PINMUX_IPSR_GPSR(IP9_15_12, DU_DR1),
+ PINMUX_IPSR_GPSR(IP9_15_12, VI0_DATA15),
+
+ PINMUX_IPSR_GPSR(IP9_19_16, MSIOF0_SCK),
+ PINMUX_IPSR_GPSR(IP9_19_16, DU_DG0),
+ PINMUX_IPSR_GPSR(IP9_19_16, VI0_DATA16),
+
+ PINMUX_IPSR_GPSR(IP9_23_20, MSIOF0_SYNC),
+ PINMUX_IPSR_GPSR(IP9_23_20, DU_DG1),
+ PINMUX_IPSR_GPSR(IP9_23_20, VI0_DATA17),
+
+ PINMUX_IPSR_GPSR(IP9_27_24, MSIOF0_SS1),
+ PINMUX_IPSR_GPSR(IP9_27_24, DU_DB0),
+ PINMUX_IPSR_GPSR(IP9_27_24, TCLK3),
+ PINMUX_IPSR_GPSR(IP9_27_24, VI0_DATA18),
+
+ PINMUX_IPSR_GPSR(IP9_31_28, MSIOF0_SS2),
+ PINMUX_IPSR_GPSR(IP9_31_28, DU_DB1),
+ PINMUX_IPSR_GPSR(IP9_31_28, TCLK4),
+ PINMUX_IPSR_GPSR(IP9_31_28, VI0_DATA19),
+
+ /* IPSR10 */
+ PINMUX_IPSR_GPSR(IP10_3_0, SCL3),
+ PINMUX_IPSR_GPSR(IP10_3_0, VI0_DATA20),
+
+ PINMUX_IPSR_GPSR(IP10_7_4, SDA3),
+ PINMUX_IPSR_GPSR(IP10_7_4, VI0_DATA21),
+
+ PINMUX_IPSR_GPSR(IP10_11_8, FSO_CFE_0_N),
+ PINMUX_IPSR_GPSR(IP10_11_8, VI0_DATA22),
+
+ PINMUX_IPSR_GPSR(IP10_15_12, FSO_CFE_1_N),
+ PINMUX_IPSR_GPSR(IP10_15_12, VI0_DATA23),
+
+ PINMUX_IPSR_GPSR(IP10_19_16, FSO_TOE_N),
+};
+
+static const struct sh_pfc_pin pinmux_pins[] = {
+ PINMUX_GPIO_GP_ALL(),
+};
+
+/* - AVB -------------------------------------------------------------------- */
+static const unsigned int avb_link_pins[] = {
+ /* AVB_LINK */
+ RCAR_GP_PIN(1, 18),
+};
+static const unsigned int avb_link_mux[] = {
+ AVB_LINK_MARK,
+};
+static const unsigned int avb_magic_pins[] = {
+ /* AVB_MAGIC */
+ RCAR_GP_PIN(1, 16),
+};
+static const unsigned int avb_magic_mux[] = {
+ AVB_MAGIC_MARK,
+};
+static const unsigned int avb_phy_int_pins[] = {
+ /* AVB_PHY_INT */
+ RCAR_GP_PIN(1, 17),
+};
+static const unsigned int avb_phy_int_mux[] = {
+ AVB_PHY_INT_MARK,
+};
+static const unsigned int avb_mdio_pins[] = {
+ /* AVB_MDC, AVB_MDIO */
+ RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
+};
+static const unsigned int avb_mdio_mux[] = {
+ AVB_MDC_MARK, AVB_MDIO_MARK,
+};
+static const unsigned int avb_rgmii_pins[] = {
+ /*
+ * AVB_TX_CTL, AVB_TXC, AVB_TD0, AVB_TD1, AVB_TD2, AVB_TD3,
+ * AVB_RX_CTL, AVB_RXC, AVB_RD0, AVB_RD1, AVB_RD2, AVB_RD3,
+ */
+ RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
+ RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
+ RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12),
+ RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
+ RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
+ RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
+};
+static const unsigned int avb_rgmii_mux[] = {
+ AVB_TX_CTL_MARK, AVB_TXC_MARK,
+ AVB_TD0_MARK, AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
+ AVB_RX_CTL_MARK, AVB_RXC_MARK,
+ AVB_RD0_MARK, AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
+};
+static const unsigned int avb_txcrefclk_pins[] = {
+ /* AVB_TXCREFCLK */
+ RCAR_GP_PIN(1, 13),
+};
+static const unsigned int avb_txcrefclk_mux[] = {
+ AVB_TXCREFCLK_MARK,
+};
+static const unsigned int avb_avtp_pps_pins[] = {
+ /* AVB_AVTP_PPS */
+ RCAR_GP_PIN(2, 6),
+};
+static const unsigned int avb_avtp_pps_mux[] = {
+ AVB_AVTP_PPS_MARK,
+};
+static const unsigned int avb_avtp_capture_pins[] = {
+ /* AVB_AVTP_CAPTURE */
+ RCAR_GP_PIN(1, 20),
+};
+static const unsigned int avb_avtp_capture_mux[] = {
+ AVB_AVTP_CAPTURE_MARK,
+};
+static const unsigned int avb_avtp_match_pins[] = {
+ /* AVB_AVTP_MATCH */
+ RCAR_GP_PIN(1, 19),
+};
+static const unsigned int avb_avtp_match_mux[] = {
+ AVB_AVTP_MATCH_MARK,
+};
+
+/* - CANFD0 ----------------------------------------------------------------- */
+static const unsigned int canfd0_data_a_pins[] = {
+ /* CANFD0_TX, CANFD0_RX */
+ RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
+};
+static const unsigned int canfd0_data_a_mux[] = {
+ CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
+};
+static const unsigned int canfd0_data_b_pins[] = {
+ /* CANFD0_TX, CANFD0_RX */
+ RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+};
+static const unsigned int canfd0_data_b_mux[] = {
+ CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
+};
+
+/* - CANFD1 ----------------------------------------------------------------- */
+static const unsigned int canfd1_data_pins[] = {
+ /* CANFD1_TX, CANFD1_RX */
+ RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
+};
+static const unsigned int canfd1_data_mux[] = {
+ CANFD1_TX_MARK, CANFD1_RX_MARK,
+};
+
+/* - CANFD Clock ------------------------------------------------------------ */
+static const unsigned int canfd_clk_a_pins[] = {
+ /* CANFD_CLK */
+ RCAR_GP_PIN(1, 25),
+};
+static const unsigned int canfd_clk_a_mux[] = {
+ CANFD_CLK_A_MARK,
+};
+static const unsigned int canfd_clk_b_pins[] = {
+ /* CANFD_CLK */
+ RCAR_GP_PIN(3, 8),
+};
+static const unsigned int canfd_clk_b_mux[] = {
+ CANFD_CLK_B_MARK,
+};
+
+/* - DU --------------------------------------------------------------------- */
+static const unsigned int du_rgb666_pins[] = {
+ /* DU_DR[7:2], DU_DG[7:2], DU_DB[7:2] */
+ RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
+ RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
+ RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
+ RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
+ RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
+};
+static const unsigned int du_rgb666_mux[] = {
+ DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
+ DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
+ DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
+ DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
+ DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
+ DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
+};
+static const unsigned int du_rgb888_pins[] = {
+ /* DU_DR[7:0], DU_DG[7:0], DU_DB[7:0] */
+ RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
+ RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19),
+ RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
+ RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
+ RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
+ RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
+ RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
+ RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23),
+};
+static const unsigned int du_rgb888_mux[] = {
+ DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
+ DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
+ DU_DR1_MARK, DU_DR0_MARK,
+ DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
+ DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
+ DU_DG1_MARK, DU_DG0_MARK,
+ DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
+ DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
+ DU_DB1_MARK, DU_DB0_MARK,
+};
+static const unsigned int du_clk_out_pins[] = {
+ /* DU_DOTCLKOUT */
+ RCAR_GP_PIN(0, 18),
+};
+static const unsigned int du_clk_out_mux[] = {
+ DU_DOTCLKOUT_MARK,
+};
+static const unsigned int du_sync_pins[] = {
+ /* DU_EXVSYNC/DU_VSYNC, DU_EXHSYNC/DU_HSYNC */
+ RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
+};
+static const unsigned int du_sync_mux[] = {
+ DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK,
+};
+static const unsigned int du_oddf_pins[] = {
+ /* DU_EXODDF/DU_ODDF/DISP/CDE */
+ RCAR_GP_PIN(0, 21),
+};
+static const unsigned int du_oddf_mux[] = {
+ DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
+};
+static const unsigned int du_cde_pins[] = {
+ /* DU_CDE */
+ RCAR_GP_PIN(1, 22),
+};
+static const unsigned int du_cde_mux[] = {
+ DU_CDE_MARK,
+};
+static const unsigned int du_disp_pins[] = {
+ /* DU_DISP */
+ RCAR_GP_PIN(1, 21),
+};
+static const unsigned int du_disp_mux[] = {
+ DU_DISP_MARK,
+};
+
+/* - GETHER ----------------------------------------------------------------- */
+static const unsigned int gether_link_a_pins[] = {
+ /* GETHER_LINK */
+ RCAR_GP_PIN(4, 24),
+};
+static const unsigned int gether_link_a_mux[] = {
+ GETHER_LINK_A_MARK,
+};
+static const unsigned int gether_phy_int_a_pins[] = {
+ /* GETHER_PHY_INT */
+ RCAR_GP_PIN(4, 23),
+};
+static const unsigned int gether_phy_int_a_mux[] = {
+ GETHER_PHY_INT_A_MARK,
+};
+static const unsigned int gether_mdio_a_pins[] = {
+ /* GETHER_MDC, GETHER_MDIO */
+ RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
+};
+static const unsigned int gether_mdio_a_mux[] = {
+ GETHER_MDC_A_MARK, GETHER_MDIO_A_MARK,
+};
+static const unsigned int gether_link_b_pins[] = {
+ /* GETHER_LINK */
+ RCAR_GP_PIN(0, 18),
+};
+static const unsigned int gether_link_b_mux[] = {
+ GETHER_LINK_B_MARK,
+};
+static const unsigned int gether_phy_int_b_pins[] = {
+ /* GETHER_PHY_INT */
+ RCAR_GP_PIN(0, 19),
+};
+static const unsigned int gether_phy_int_b_mux[] = {
+ GETHER_PHY_INT_B_MARK,
+};
+static const unsigned int gether_mdio_b_mux[] = {
+ GETHER_MDC_B_MARK, GETHER_MDIO_B_MARK,
+};
+static const unsigned int gether_mdio_b_pins[] = {
+ /* GETHER_MDC, GETHER_MDIO */
+ RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
+};
+static const unsigned int gether_magic_pins[] = {
+ /* GETHER_MAGIC */
+ RCAR_GP_PIN(4, 22),
+};
+static const unsigned int gether_magic_mux[] = {
+ GETHER_MAGIC_MARK,
+};
+static const unsigned int gether_rgmii_pins[] = {
+ /*
+ * GETHER_TX_CTL, GETHER_TXC,
+ * GETHER_TD0, GETHER_TD1, GETHER_TD2, GETHER_TD3,
+ * GETHER_RX_CTL, GETHER_RXC,
+ * GETHER_RD0, GETHER_RD1, GETHER_RD2, GETHER_RD3,
+ */
+ RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13),
+ RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
+ RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
+ RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
+ RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
+ RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
+};
+static const unsigned int gether_rgmii_mux[] = {
+ GETHER_TX_CTL_MARK, GETHER_TXC_MARK,
+ GETHER_TD0_MARK, GETHER_TD1_MARK,
+ GETHER_TD2_MARK, GETHER_TD3_MARK,
+ GETHER_RX_CTL_MARK, GETHER_RXC_MARK,
+ GETHER_RD0_MARK, AVB_RD1_MARK,
+ GETHER_RD2_MARK, AVB_RD3_MARK,
+};
+static const unsigned int gether_txcrefclk_pins[] = {
+ /* GETHER_TXCREFCLK */
+ RCAR_GP_PIN(4, 18),
+};
+static const unsigned int gether_txcrefclk_mux[] = {
+ GETHER_TXCREFCLK_MARK,
+};
+static const unsigned int gether_txcrefclk_mega_pins[] = {
+ /* GETHER_TXCREFCLK_MEGA */
+ RCAR_GP_PIN(4, 19),
+};
+static const unsigned int gether_txcrefclk_mega_mux[] = {
+ GETHER_TXCREFCLK_MEGA_MARK,
+};
+static const unsigned int gether_rmii_pins[] = {
+ /*
+ * GETHER_RMII_CRS_DV, GETHER_RMII_RX_ER,
+ * GETHER_RMII_RXD0, GETHER_RMII_RXD1,
+ * GETHER_RMII_TXD_EN, GETHER_RMII_TXD0,
+ * GETHER_RMII_TXD1, GETHER_RMII_REFCLK
+ */
+ RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+};
+static const unsigned int gether_rmii_mux[] = {
+ GETHER_RMII_CRS_DV_MARK, GETHER_RMII_RX_ER_MARK,
+ GETHER_RMII_RXD0_MARK, GETHER_RMII_RXD1_MARK,
+ GETHER_RMII_TXD_EN_MARK, GETHER_RMII_TXD0_MARK,
+ GETHER_RMII_TXD1_MARK, GETHER_RMII_REFCLK_MARK,
+};
+
+/* - HSCIF0 ----------------------------------------------------------------- */
+static const unsigned int hscif0_data_a_pins[] = {
+ /* HRX0, HTX0 */
+ RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 15),
+};
+static const unsigned int hscif0_data_a_mux[] = {
+ HRX0_A_MARK, HTX0_A_MARK,
+};
+static const unsigned int hscif0_clk_a_pins[] = {
+ /* HSCK0 */
+ RCAR_GP_PIN(0, 12),
+};
+static const unsigned int hscif0_clk_a_mux[] = {
+ HSCK0_A_MARK,
+};
+static const unsigned int hscif0_ctrl_a_pins[] = {
+ /* HRTS0#, HCTS0# */
+ RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
+};
+static const unsigned int hscif0_ctrl_a_mux[] = {
+ HRTS0_N_A_MARK, HCTS0_N_A_MARK,
+};
+static const unsigned int hscif0_data_b_pins[] = {
+ /* HRX0, HTX0 */
+ RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
+};
+static const unsigned int hscif0_data_b_mux[] = {
+ HRX0_B_MARK, HTX0_B_MARK,
+};
+static const unsigned int hscif0_clk_b_pins[] = {
+ /* HSCK0 */
+ RCAR_GP_PIN(4, 1),
+};
+static const unsigned int hscif0_clk_b_mux[] = {
+ HSCK0_B_MARK,
+};
+static const unsigned int hscif0_ctrl_b_pins[] = {
+ /* HRTS0#, HCTS0# */
+ RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
+};
+static const unsigned int hscif0_ctrl_b_mux[] = {
+ HRTS0_N_B_MARK, HCTS0_N_B_MARK,
+};
+
+/* - HSCIF1 ----------------------------------------------------------------- */
+static const unsigned int hscif1_data_pins[] = {
+ /* HRX1, HTX1 */
+ RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
+};
+static const unsigned int hscif1_data_mux[] = {
+ HRX1_MARK, HTX1_MARK,
+};
+static const unsigned int hscif1_clk_pins[] = {
+ /* HSCK1 */
+ RCAR_GP_PIN(2, 7),
+};
+static const unsigned int hscif1_clk_mux[] = {
+ HSCK1_MARK,
+};
+static const unsigned int hscif1_ctrl_pins[] = {
+ /* HRTS1#, HCTS1# */
+ RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
+};
+static const unsigned int hscif1_ctrl_mux[] = {
+ HRTS1_N_MARK, HCTS1_N_MARK,
+};
+
+/* - HSCIF2 ----------------------------------------------------------------- */
+static const unsigned int hscif2_data_pins[] = {
+ /* HRX2, HTX2 */
+ RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15),
+};
+static const unsigned int hscif2_data_mux[] = {
+ HRX2_MARK, HTX2_MARK,
+};
+static const unsigned int hscif2_clk_pins[] = {
+ /* HSCK2 */
+ RCAR_GP_PIN(2, 12),
+};
+static const unsigned int hscif2_clk_mux[] = {
+ HSCK2_MARK,
+};
+static const unsigned int hscif2_ctrl_pins[] = {
+ /* HRTS2#, HCTS2# */
+ RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
+};
+static const unsigned int hscif2_ctrl_mux[] = {
+ HRTS2_N_MARK, HCTS2_N_MARK,
+};
+
+/* - HSCIF3 ----------------------------------------------------------------- */
+static const unsigned int hscif3_data_pins[] = {
+ /* HRX3, HTX3 */
+ RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
+};
+static const unsigned int hscif3_data_mux[] = {
+ HRX3_MARK, HTX3_MARK,
+};
+static const unsigned int hscif3_clk_pins[] = {
+ /* HSCK3 */
+ RCAR_GP_PIN(2, 0),
+};
+static const unsigned int hscif3_clk_mux[] = {
+ HSCK3_MARK,
+};
+static const unsigned int hscif3_ctrl_pins[] = {
+ /* HRTS3#, HCTS3# */
+ RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
+};
+static const unsigned int hscif3_ctrl_mux[] = {
+ HRTS3_N_MARK, HCTS3_N_MARK,
+};
+
+/* - I2C0 ------------------------------------------------------------------- */
+static const unsigned int i2c0_pins[] = {
+ /* SDA0, SCL0 */
+ RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
+};
+static const unsigned int i2c0_mux[] = {
+ SDA0_MARK, SCL0_MARK,
+};
+
+/* - I2C1 ------------------------------------------------------------------- */
+static const unsigned int i2c1_pins[] = {
+ /* SDA1, SCL1 */
+ RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
+};
+static const unsigned int i2c1_mux[] = {
+ SDA1_MARK, SCL1_MARK,
+};
+
+/* - I2C2 ------------------------------------------------------------------- */
+static const unsigned int i2c2_pins[] = {
+ /* SDA2, SCL2 */
+ RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
+};
+static const unsigned int i2c2_mux[] = {
+ SDA2_MARK, SCL2_MARK,
+};
+
+/* - I2C3 ------------------------------------------------------------------- */
+static const unsigned int i2c3_pins[] = {
+ /* SDA3, SCL3 */
+ RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 25),
+};
+static const unsigned int i2c3_mux[] = {
+ SDA3_MARK, SCL3_MARK,
+};
+
+/* - I2C4 ------------------------------------------------------------------- */
+static const unsigned int i2c4_pins[] = {
+ /* SDA4, SCL4 */
+ RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
+};
+static const unsigned int i2c4_mux[] = {
+ SDA4_MARK, SCL4_MARK,
+};
+
+/* - I2C5 ------------------------------------------------------------------- */
+static const unsigned int i2c5_pins[] = {
+ /* SDA5, SCL5 */
+ RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
+};
+static const unsigned int i2c5_mux[] = {
+ SDA5_MARK, SCL5_MARK,
+};
+
+/* - INTC-EX ---------------------------------------------------------------- */
+static const unsigned int intc_ex_irq0_pins[] = {
+ /* IRQ0 */
+ RCAR_GP_PIN(1, 0),
+};
+static const unsigned int intc_ex_irq0_mux[] = {
+ IRQ0_MARK,
+};
+static const unsigned int intc_ex_irq1_pins[] = {
+ /* IRQ1 */
+ RCAR_GP_PIN(0, 12),
+};
+static const unsigned int intc_ex_irq1_mux[] = {
+ IRQ1_MARK,
+};
+static const unsigned int intc_ex_irq2_pins[] = {
+ /* IRQ2 */
+ RCAR_GP_PIN(0, 13),
+};
+static const unsigned int intc_ex_irq2_mux[] = {
+ IRQ2_MARK,
+};
+static const unsigned int intc_ex_irq3_pins[] = {
+ /* IRQ3 */
+ RCAR_GP_PIN(0, 14),
+};
+static const unsigned int intc_ex_irq3_mux[] = {
+ IRQ3_MARK,
+};
+static const unsigned int intc_ex_irq4_pins[] = {
+ /* IRQ4 */
+ RCAR_GP_PIN(2, 17),
+};
+static const unsigned int intc_ex_irq4_mux[] = {
+ IRQ4_MARK,
+};
+static const unsigned int intc_ex_irq5_pins[] = {
+ /* IRQ5 */
+ RCAR_GP_PIN(2, 18),
+};
+static const unsigned int intc_ex_irq5_mux[] = {
+ IRQ5_MARK,
+};
+
+/* - MMC -------------------------------------------------------------------- */
+static const unsigned int mmc_data1_pins[] = {
+ /* MMC_D0 */
+ RCAR_GP_PIN(3, 8),
+};
+static const unsigned int mmc_data1_mux[] = {
+ MMC_D0_MARK,
+};
+static const unsigned int mmc_data4_pins[] = {
+ /* MMC_D[0:3] */
+ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
+ RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+};
+static const unsigned int mmc_data4_mux[] = {
+ MMC_D0_MARK, MMC_D1_MARK,
+ MMC_D2_MARK, MMC_D3_MARK,
+};
+static const unsigned int mmc_data8_pins[] = {
+ /* MMC_D[0:7] */
+ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
+ RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+ RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
+ RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
+};
+static const unsigned int mmc_data8_mux[] = {
+ MMC_D0_MARK, MMC_D1_MARK,
+ MMC_D2_MARK, MMC_D3_MARK,
+ MMC_D4_MARK, MMC_D5_MARK,
+ MMC_D6_MARK, MMC_D7_MARK,
+};
+static const unsigned int mmc_ctrl_pins[] = {
+ /* MMC_CLK, MMC_CMD */
+ RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 7),
+};
+static const unsigned int mmc_ctrl_mux[] = {
+ MMC_CLK_MARK, MMC_CMD_MARK,
+};
+static const unsigned int mmc_cd_pins[] = {
+ /* MMC_CD */
+ RCAR_GP_PIN(3, 5),
+};
+static const unsigned int mmc_cd_mux[] = {
+ MMC_CD_MARK,
+};
+static const unsigned int mmc_wp_pins[] = {
+ /* MMC_WP */
+ RCAR_GP_PIN(3, 4),
+};
+static const unsigned int mmc_wp_mux[] = {
+ MMC_WP_MARK,
+};
+static const unsigned int mmc_ds_pins[] = {
+ /* MMC_DS */
+ RCAR_GP_PIN(3, 6),
+};
+static const unsigned int mmc_ds_mux[] = {
+ MMC_DS_MARK,
+};
+
+/* - MSIOF0 ----------------------------------------------------------------- */
+static const unsigned int msiof0_clk_pins[] = {
+ /* MSIOF0_SCK */
+ RCAR_GP_PIN(2, 21),
+};
+static const unsigned int msiof0_clk_mux[] = {
+ MSIOF0_SCK_MARK,
+};
+static const unsigned int msiof0_sync_pins[] = {
+ /* MSIOF0_SYNC */
+ RCAR_GP_PIN(2, 22),
+};
+static const unsigned int msiof0_sync_mux[] = {
+ MSIOF0_SYNC_MARK,
+};
+static const unsigned int msiof0_ss1_pins[] = {
+ /* MSIOF0_SS1 */
+ RCAR_GP_PIN(2, 23),
+};
+static const unsigned int msiof0_ss1_mux[] = {
+ MSIOF0_SS1_MARK,
+};
+static const unsigned int msiof0_ss2_pins[] = {
+ /* MSIOF0_SS2 */
+ RCAR_GP_PIN(2, 24),
+};
+static const unsigned int msiof0_ss2_mux[] = {
+ MSIOF0_SS2_MARK,
+};
+static const unsigned int msiof0_txd_pins[] = {
+ /* MSIOF0_TXD */
+ RCAR_GP_PIN(2, 20),
+};
+static const unsigned int msiof0_txd_mux[] = {
+ MSIOF0_TXD_MARK,
+};
+static const unsigned int msiof0_rxd_pins[] = {
+ /* MSIOF0_RXD */
+ RCAR_GP_PIN(2, 19),
+};
+static const unsigned int msiof0_rxd_mux[] = {
+ MSIOF0_RXD_MARK,
+};
+
+/* - MSIOF1 ----------------------------------------------------------------- */
+static const unsigned int msiof1_clk_pins[] = {
+ /* MSIOF1_SCK */
+ RCAR_GP_PIN(3, 2),
+};
+static const unsigned int msiof1_clk_mux[] = {
+ MSIOF1_SCK_MARK,
+};
+static const unsigned int msiof1_sync_pins[] = {
+ /* MSIOF1_SYNC */
+ RCAR_GP_PIN(3, 3),
+};
+static const unsigned int msiof1_sync_mux[] = {
+ MSIOF1_SYNC_MARK,
+};
+static const unsigned int msiof1_ss1_pins[] = {
+ /* MSIOF1_SS1 */
+ RCAR_GP_PIN(3, 4),
+};
+static const unsigned int msiof1_ss1_mux[] = {
+ MSIOF1_SS1_MARK,
+};
+static const unsigned int msiof1_ss2_pins[] = {
+ /* MSIOF1_SS2 */
+ RCAR_GP_PIN(3, 5),
+};
+static const unsigned int msiof1_ss2_mux[] = {
+ MSIOF1_SS2_MARK,
+};
+static const unsigned int msiof1_txd_pins[] = {
+ /* MSIOF1_TXD */
+ RCAR_GP_PIN(3, 1),
+};
+static const unsigned int msiof1_txd_mux[] = {
+ MSIOF1_TXD_MARK,
+};
+static const unsigned int msiof1_rxd_pins[] = {
+ /* MSIOF1_RXD */
+ RCAR_GP_PIN(3, 0),
+};
+static const unsigned int msiof1_rxd_mux[] = {
+ MSIOF1_RXD_MARK,
+};
+
+/* - MSIOF2 ----------------------------------------------------------------- */
+static const unsigned int msiof2_clk_pins[] = {
+ /* MSIOF2_SCK */
+ RCAR_GP_PIN(2, 0),
+};
+static const unsigned int msiof2_clk_mux[] = {
+ MSIOF2_SCK_MARK,
+};
+static const unsigned int msiof2_sync_pins[] = {
+ /* MSIOF2_SYNC */
+ RCAR_GP_PIN(2, 3),
+};
+static const unsigned int msiof2_sync_mux[] = {
+ MSIOF2_SYNC_MARK,
+};
+static const unsigned int msiof2_ss1_pins[] = {
+ /* MSIOF2_SS1 */
+ RCAR_GP_PIN(2, 4),
+};
+static const unsigned int msiof2_ss1_mux[] = {
+ MSIOF2_SS1_MARK,
+};
+static const unsigned int msiof2_ss2_pins[] = {
+ /* MSIOF2_SS2 */
+ RCAR_GP_PIN(2, 5),
+};
+static const unsigned int msiof2_ss2_mux[] = {
+ MSIOF2_SS2_MARK,
+};
+static const unsigned int msiof2_txd_pins[] = {
+ /* MSIOF2_TXD */
+ RCAR_GP_PIN(2, 2),
+};
+static const unsigned int msiof2_txd_mux[] = {
+ MSIOF2_TXD_MARK,
+};
+static const unsigned int msiof2_rxd_pins[] = {
+ /* MSIOF2_RXD */
+ RCAR_GP_PIN(2, 1),
+};
+static const unsigned int msiof2_rxd_mux[] = {
+ MSIOF2_RXD_MARK,
+};
+
+/* - MSIOF3 ----------------------------------------------------------------- */
+static const unsigned int msiof3_clk_pins[] = {
+ /* MSIOF3_SCK */
+ RCAR_GP_PIN(0, 20),
+};
+static const unsigned int msiof3_clk_mux[] = {
+ MSIOF3_SCK_MARK,
+};
+static const unsigned int msiof3_sync_pins[] = {
+ /* MSIOF3_SYNC */
+ RCAR_GP_PIN(0, 21),
+};
+static const unsigned int msiof3_sync_mux[] = {
+ MSIOF3_SYNC_MARK,
+};
+static const unsigned int msiof3_ss1_pins[] = {
+ /* MSIOF3_SS1 */
+ RCAR_GP_PIN(0, 18),
+};
+static const unsigned int msiof3_ss1_mux[] = {
+ MSIOF3_SS1_MARK,
+};
+static const unsigned int msiof3_ss2_pins[] = {
+ /* MSIOF3_SS2 */
+ RCAR_GP_PIN(0, 19),
+};
+static const unsigned int msiof3_ss2_mux[] = {
+ MSIOF3_SS2_MARK,
+};
+static const unsigned int msiof3_txd_pins[] = {
+ /* MSIOF3_TXD */
+ RCAR_GP_PIN(0, 17),
+};
+static const unsigned int msiof3_txd_mux[] = {
+ MSIOF3_TXD_MARK,
+};
+static const unsigned int msiof3_rxd_pins[] = {
+ /* MSIOF3_RXD */
+ RCAR_GP_PIN(0, 16),
+};
+static const unsigned int msiof3_rxd_mux[] = {
+ MSIOF3_RXD_MARK,
+};
+
+/* - PWM0 ------------------------------------------------------------------- */
+static const unsigned int pwm0_a_pins[] = {
+ /* PWM0 */
+ RCAR_GP_PIN(0, 15),
+};
+static const unsigned int pwm0_a_mux[] = {
+ PWM0_A_MARK,
+};
+static const unsigned int pwm0_b_pins[] = {
+ /* PWM0 */
+ RCAR_GP_PIN(1, 21),
+};
+static const unsigned int pwm0_b_mux[] = {
+ PWM0_B_MARK,
+};
+
+/* - PWM1 ------------------------------------------------------------------- */
+static const unsigned int pwm1_a_pins[] = {
+ /* PWM1 */
+ RCAR_GP_PIN(2, 13),
+};
+static const unsigned int pwm1_a_mux[] = {
+ PWM1_A_MARK,
+};
+static const unsigned int pwm1_b_pins[] = {
+ /* PWM1 */
+ RCAR_GP_PIN(1, 22),
+};
+static const unsigned int pwm1_b_mux[] = {
+ PWM1_B_MARK,
+};
+
+/* - PWM2 ------------------------------------------------------------------- */
+static const unsigned int pwm2_a_pins[] = {
+ /* PWM2 */
+ RCAR_GP_PIN(2, 14),
+};
+static const unsigned int pwm2_a_mux[] = {
+ PWM2_A_MARK,
+};
+static const unsigned int pwm2_b_pins[] = {
+ /* PWM2 */
+ RCAR_GP_PIN(1, 23),
+};
+static const unsigned int pwm2_b_mux[] = {
+ PWM2_B_MARK,
+};
+
+/* - PWM3 ------------------------------------------------------------------- */
+static const unsigned int pwm3_a_pins[] = {
+ /* PWM3 */
+ RCAR_GP_PIN(2, 15),
+};
+static const unsigned int pwm3_a_mux[] = {
+ PWM3_A_MARK,
+};
+static const unsigned int pwm3_b_pins[] = {
+ /* PWM3 */
+ RCAR_GP_PIN(1, 24),
+};
+static const unsigned int pwm3_b_mux[] = {
+ PWM3_B_MARK,
+};
+
+/* - PWM4 ------------------------------------------------------------------- */
+static const unsigned int pwm4_a_pins[] = {
+ /* PWM4 */
+ RCAR_GP_PIN(2, 16),
+};
+static const unsigned int pwm4_a_mux[] = {
+ PWM4_A_MARK,
+};
+static const unsigned int pwm4_b_pins[] = {
+ /* PWM4 */
+ RCAR_GP_PIN(1, 25),
+};
+static const unsigned int pwm4_b_mux[] = {
+ PWM4_B_MARK,
+};
+
+/* - QSPI0 ------------------------------------------------------------------ */
+static const unsigned int qspi0_ctrl_pins[] = {
+ /* SPCLK, SSL */
+ RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 5),
+};
+static const unsigned int qspi0_ctrl_mux[] = {
+ QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
+};
+static const unsigned int qspi0_data2_pins[] = {
+ /* MOSI_IO0, MISO_IO1 */
+ RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
+};
+static const unsigned int qspi0_data2_mux[] = {
+ QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
+};
+static const unsigned int qspi0_data4_pins[] = {
+ /* MOSI_IO0, MISO_IO1, IO2, IO3 */
+ RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
+ RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
+};
+static const unsigned int qspi0_data4_mux[] = {
+ QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
+ QSPI0_IO2_MARK, QSPI0_IO3_MARK
+};
+
+/* - QSPI1 ------------------------------------------------------------------ */
+static const unsigned int qspi1_ctrl_pins[] = {
+ /* SPCLK, SSL */
+ RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 11),
+};
+static const unsigned int qspi1_ctrl_mux[] = {
+ QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
+};
+static const unsigned int qspi1_data2_pins[] = {
+ /* MOSI_IO0, MISO_IO1 */
+ RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
+};
+static const unsigned int qspi1_data2_mux[] = {
+ QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
+};
+static const unsigned int qspi1_data4_pins[] = {
+ /* MOSI_IO0, MISO_IO1, IO2, IO3 */
+ RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
+ RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
+};
+static const unsigned int qspi1_data4_mux[] = {
+ QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
+ QSPI1_IO2_MARK, QSPI1_IO3_MARK
+};
+
+/* - SCIF0 ------------------------------------------------------------------ */
+static const unsigned int scif0_data_pins[] = {
+ /* RX0, TX0 */
+ RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
+};
+static const unsigned int scif0_data_mux[] = {
+ RX0_MARK, TX0_MARK,
+};
+static const unsigned int scif0_clk_pins[] = {
+ /* SCK0 */
+ RCAR_GP_PIN(4, 1),
+};
+static const unsigned int scif0_clk_mux[] = {
+ SCK0_MARK,
+};
+static const unsigned int scif0_ctrl_pins[] = {
+ /* RTS0#, CTS0# */
+ RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
+};
+static const unsigned int scif0_ctrl_mux[] = {
+ RTS0_N_MARK, CTS0_N_MARK,
+};
+
+/* - SCIF1 ------------------------------------------------------------------ */
+static const unsigned int scif1_data_a_pins[] = {
+ /* RX1, TX1 */
+ RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
+};
+static const unsigned int scif1_data_a_mux[] = {
+ RX1_A_MARK, TX1_A_MARK,
+};
+static const unsigned int scif1_clk_pins[] = {
+ /* SCK1 */
+ RCAR_GP_PIN(2, 5),
+};
+static const unsigned int scif1_clk_mux[] = {
+ SCK1_MARK,
+};
+static const unsigned int scif1_ctrl_pins[] = {
+ /* RTS1#, CTS1# */
+ RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
+};
+static const unsigned int scif1_ctrl_mux[] = {
+ RTS1_N_MARK, CTS1_N_MARK,
+};
+static const unsigned int scif1_data_b_pins[] = {
+ /* RX1, TX1 */
+ RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
+};
+static const unsigned int scif1_data_b_mux[] = {
+ RX1_B_MARK, TX1_B_MARK,
+};
+
+/* - SCIF3 ------------------------------------------------------------------ */
+static const unsigned int scif3_data_pins[] = {
+ /* RX3, TX3 */
+ RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
+};
+static const unsigned int scif3_data_mux[] = {
+ RX3_MARK, TX3_MARK,
+};
+static const unsigned int scif3_clk_pins[] = {
+ /* SCK3 */
+ RCAR_GP_PIN(2, 0),
+};
+static const unsigned int scif3_clk_mux[] = {
+ SCK3_MARK,
+};
+static const unsigned int scif3_ctrl_pins[] = {
+ /* RTS3#, CTS3# */
+ RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
+};
+static const unsigned int scif3_ctrl_mux[] = {
+ RTS3_N_MARK, CTS3_N_MARK,
+};
+
+/* - SCIF4 ------------------------------------------------------------------ */
+static const unsigned int scif4_data_pins[] = {
+ /* RX4, TX4 */
+ RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
+};
+static const unsigned int scif4_data_mux[] = {
+ RX4_MARK, TX4_MARK,
+};
+static const unsigned int scif4_clk_pins[] = {
+ /* SCK4 */
+ RCAR_GP_PIN(0, 0),
+};
+static const unsigned int scif4_clk_mux[] = {
+ SCK4_MARK,
+};
+static const unsigned int scif4_ctrl_pins[] = {
+ /* RTS4#, CTS4# */
+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
+};
+static const unsigned int scif4_ctrl_mux[] = {
+ RTS4_N_MARK, CTS4_N_MARK,
+};
+
+/* - SCIF Clock ------------------------------------------------------------- */
+static const unsigned int scif_clk_a_pins[] = {
+ /* SCIF_CLK */
+ RCAR_GP_PIN(0, 10),
+};
+static const unsigned int scif_clk_a_mux[] = {
+ SCIF_CLK_A_MARK,
+};
+static const unsigned int scif_clk_b_pins[] = {
+ /* SCIF_CLK */
+ RCAR_GP_PIN(1, 25),
+};
+static const unsigned int scif_clk_b_mux[] = {
+ SCIF_CLK_B_MARK,
+};
+
+/* - TMU -------------------------------------------------------------------- */
+static const unsigned int tmu_tclk1_a_pins[] = {
+ /* TCLK1 */
+ RCAR_GP_PIN(3, 13),
+};
+static const unsigned int tmu_tclk1_a_mux[] = {
+ TCLK1_A_MARK,
+};
+static const unsigned int tmu_tclk1_b_pins[] = {
+ /* TCLK1 */
+ RCAR_GP_PIN(1, 23),
+};
+static const unsigned int tmu_tclk1_b_mux[] = {
+ TCLK1_B_MARK,
+};
+static const unsigned int tmu_tclk2_a_pins[] = {
+ /* TCLK2 */
+ RCAR_GP_PIN(3, 14),
+};
+static const unsigned int tmu_tclk2_a_mux[] = {
+ TCLK2_A_MARK,
+};
+static const unsigned int tmu_tclk2_b_pins[] = {
+ /* TCLK2 */
+ RCAR_GP_PIN(1, 24),
+};
+static const unsigned int tmu_tclk2_b_mux[] = {
+ TCLK2_B_MARK,
+};
+
+/* - TPU ------------------------------------------------------------------- */
+static const unsigned int tpu_to0_pins[] = {
+ /* TPU0TO0 */
+ RCAR_GP_PIN(1, 19),
+};
+static const unsigned int tpu_to0_mux[] = {
+ TPU0TO0_MARK,
+};
+static const unsigned int tpu_to1_pins[] = {
+ /* TPU0TO1 */
+ RCAR_GP_PIN(1, 20),
+};
+static const unsigned int tpu_to1_mux[] = {
+ TPU0TO1_MARK,
+};
+static const unsigned int tpu_to2_pins[] = {
+ /* TPU0TO2 */
+ RCAR_GP_PIN(4, 2),
+};
+static const unsigned int tpu_to2_mux[] = {
+ TPU0TO2_MARK,
+};
+static const unsigned int tpu_to3_pins[] = {
+ /* TPU0TO3 */
+ RCAR_GP_PIN(4, 3),
+};
+static const unsigned int tpu_to3_mux[] = {
+ TPU0TO3_MARK,
+};
+
+/* - VIN0 ------------------------------------------------------------------- */
+static const union vin_data vin0_data_pins = {
+ .data24 = {
+ RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+ RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+ RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
+ RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
+ RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
+ RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
+ RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
+ RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
+ RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
+ RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
+ RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
+ RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
+ },
+};
+static const union vin_data vin0_data_mux = {
+ .data24 = {
+ VI0_DATA0_MARK, VI0_DATA1_MARK,
+ VI0_DATA2_MARK, VI0_DATA3_MARK,
+ VI0_DATA4_MARK, VI0_DATA5_MARK,
+ VI0_DATA6_MARK, VI0_DATA7_MARK,
+ VI0_DATA8_MARK, VI0_DATA9_MARK,
+ VI0_DATA10_MARK, VI0_DATA11_MARK,
+ VI0_DATA12_MARK, VI0_DATA13_MARK,
+ VI0_DATA14_MARK, VI0_DATA15_MARK,
+ VI0_DATA16_MARK, VI0_DATA17_MARK,
+ VI0_DATA18_MARK, VI0_DATA19_MARK,
+ VI0_DATA20_MARK, VI0_DATA21_MARK,
+ VI0_DATA22_MARK, VI0_DATA23_MARK,
+ },
+};
+static const unsigned int vin0_data18_pins[] = {
+ RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+ RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
+ RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
+ RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
+ RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
+ RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
+ RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
+ RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
+ RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
+};
+static const unsigned int vin0_data18_mux[] = {
+ VI0_DATA2_MARK, VI0_DATA3_MARK,
+ VI0_DATA4_MARK, VI0_DATA5_MARK,
+ VI0_DATA6_MARK, VI0_DATA7_MARK,
+ VI0_DATA10_MARK, VI0_DATA11_MARK,
+ VI0_DATA12_MARK, VI0_DATA13_MARK,
+ VI0_DATA14_MARK, VI0_DATA15_MARK,
+ VI0_DATA18_MARK, VI0_DATA19_MARK,
+ VI0_DATA20_MARK, VI0_DATA21_MARK,
+ VI0_DATA22_MARK, VI0_DATA23_MARK,
+};
+static const unsigned int vin0_sync_pins[] = {
+ /* VI0_VSYNC#, VI0_HSYNC# */
+ RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
+};
+static const unsigned int vin0_sync_mux[] = {
+ VI0_VSYNC_N_MARK, VI0_HSYNC_N_MARK,
+};
+static const unsigned int vin0_field_pins[] = {
+ /* VI0_FIELD */
+ RCAR_GP_PIN(2, 16),
+};
+static const unsigned int vin0_field_mux[] = {
+ VI0_FIELD_MARK,
+};
+static const unsigned int vin0_clkenb_pins[] = {
+ /* VI0_CLKENB */
+ RCAR_GP_PIN(2, 1),
+};
+static const unsigned int vin0_clkenb_mux[] = {
+ VI0_CLKENB_MARK,
+};
+static const unsigned int vin0_clk_pins[] = {
+ /* VI0_CLK */
+ RCAR_GP_PIN(2, 0),
+};
+static const unsigned int vin0_clk_mux[] = {
+ VI0_CLK_MARK,
+};
+
+/* - VIN1 ------------------------------------------------------------------- */
+static const union vin_data12 vin1_data_pins = {
+ .data12 = {
+ RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
+ RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
+ RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+ RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
+ RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
+ },
+};
+static const union vin_data12 vin1_data_mux = {
+ .data12 = {
+ VI1_DATA0_MARK, VI1_DATA1_MARK,
+ VI1_DATA2_MARK, VI1_DATA3_MARK,
+ VI1_DATA4_MARK, VI1_DATA5_MARK,
+ VI1_DATA6_MARK, VI1_DATA7_MARK,
+ VI1_DATA8_MARK, VI1_DATA9_MARK,
+ VI1_DATA10_MARK, VI1_DATA11_MARK,
+ },
+};
+static const unsigned int vin1_sync_pins[] = {
+ /* VI1_VSYNC#, VI1_HSYNC# */
+ RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
+};
+static const unsigned int vin1_sync_mux[] = {
+ VI1_VSYNC_N_MARK, VI1_HSYNC_N_MARK,
+};
+static const unsigned int vin1_field_pins[] = {
+ /* VI1_FIELD */
+ RCAR_GP_PIN(3, 16),
+};
+static const unsigned int vin1_field_mux[] = {
+ VI1_FIELD_MARK,
+};
+static const unsigned int vin1_clkenb_pins[] = {
+ /* VI1_CLKENB */
+ RCAR_GP_PIN(3, 1),
+};
+static const unsigned int vin1_clkenb_mux[] = {
+ VI1_CLKENB_MARK,
+};
+static const unsigned int vin1_clk_pins[] = {
+ /* VI1_CLK */
+ RCAR_GP_PIN(3, 0),
+};
+static const unsigned int vin1_clk_mux[] = {
+ VI1_CLK_MARK,
+};
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+ SH_PFC_PIN_GROUP(avb_link),
+ SH_PFC_PIN_GROUP(avb_magic),
+ SH_PFC_PIN_GROUP(avb_phy_int),
+ SH_PFC_PIN_GROUP(avb_mdio),
+ SH_PFC_PIN_GROUP(avb_rgmii),
+ SH_PFC_PIN_GROUP(avb_txcrefclk),
+ SH_PFC_PIN_GROUP(avb_avtp_pps),
+ SH_PFC_PIN_GROUP(avb_avtp_capture),
+ SH_PFC_PIN_GROUP(avb_avtp_match),
+ SH_PFC_PIN_GROUP(canfd0_data_a),
+ SH_PFC_PIN_GROUP(canfd0_data_b),
+ SH_PFC_PIN_GROUP(canfd1_data),
+ SH_PFC_PIN_GROUP(canfd_clk_a),
+ SH_PFC_PIN_GROUP(canfd_clk_b),
+ SH_PFC_PIN_GROUP(du_rgb666),
+ SH_PFC_PIN_GROUP(du_rgb888),
+ SH_PFC_PIN_GROUP(du_clk_out),
+ SH_PFC_PIN_GROUP(du_sync),
+ SH_PFC_PIN_GROUP(du_oddf),
+ SH_PFC_PIN_GROUP(du_cde),
+ SH_PFC_PIN_GROUP(du_disp),
+ SH_PFC_PIN_GROUP(gether_link_a),
+ SH_PFC_PIN_GROUP(gether_phy_int_a),
+ SH_PFC_PIN_GROUP(gether_mdio_a),
+ SH_PFC_PIN_GROUP(gether_link_b),
+ SH_PFC_PIN_GROUP(gether_phy_int_b),
+ SH_PFC_PIN_GROUP(gether_mdio_b),
+ SH_PFC_PIN_GROUP(gether_magic),
+ SH_PFC_PIN_GROUP(gether_rgmii),
+ SH_PFC_PIN_GROUP(gether_txcrefclk),
+ SH_PFC_PIN_GROUP(gether_txcrefclk_mega),
+ SH_PFC_PIN_GROUP(gether_rmii),
+ SH_PFC_PIN_GROUP(hscif0_data_a),
+ SH_PFC_PIN_GROUP(hscif0_clk_a),
+ SH_PFC_PIN_GROUP(hscif0_ctrl_a),
+ SH_PFC_PIN_GROUP(hscif0_data_b),
+ SH_PFC_PIN_GROUP(hscif0_clk_b),
+ SH_PFC_PIN_GROUP(hscif0_ctrl_b),
+ SH_PFC_PIN_GROUP(hscif1_data),
+ SH_PFC_PIN_GROUP(hscif1_clk),
+ SH_PFC_PIN_GROUP(hscif1_ctrl),
+ SH_PFC_PIN_GROUP(hscif2_data),
+ SH_PFC_PIN_GROUP(hscif2_clk),
+ SH_PFC_PIN_GROUP(hscif2_ctrl),
+ SH_PFC_PIN_GROUP(hscif3_data),
+ SH_PFC_PIN_GROUP(hscif3_clk),
+ SH_PFC_PIN_GROUP(hscif3_ctrl),
+ SH_PFC_PIN_GROUP(i2c0),
+ SH_PFC_PIN_GROUP(i2c1),
+ SH_PFC_PIN_GROUP(i2c2),
+ SH_PFC_PIN_GROUP(i2c3),
+ SH_PFC_PIN_GROUP(i2c4),
+ SH_PFC_PIN_GROUP(i2c5),
+ SH_PFC_PIN_GROUP(intc_ex_irq0),
+ SH_PFC_PIN_GROUP(intc_ex_irq1),
+ SH_PFC_PIN_GROUP(intc_ex_irq2),
+ SH_PFC_PIN_GROUP(intc_ex_irq3),
+ SH_PFC_PIN_GROUP(intc_ex_irq4),
+ SH_PFC_PIN_GROUP(intc_ex_irq5),
+ SH_PFC_PIN_GROUP(mmc_data1),
+ SH_PFC_PIN_GROUP(mmc_data4),
+ SH_PFC_PIN_GROUP(mmc_data8),
+ SH_PFC_PIN_GROUP(mmc_ctrl),
+ SH_PFC_PIN_GROUP(mmc_cd),
+ SH_PFC_PIN_GROUP(mmc_wp),
+ SH_PFC_PIN_GROUP(mmc_ds),
+ SH_PFC_PIN_GROUP(msiof0_clk),
+ SH_PFC_PIN_GROUP(msiof0_sync),
+ SH_PFC_PIN_GROUP(msiof0_ss1),
+ SH_PFC_PIN_GROUP(msiof0_ss2),
+ SH_PFC_PIN_GROUP(msiof0_txd),
+ SH_PFC_PIN_GROUP(msiof0_rxd),
+ SH_PFC_PIN_GROUP(msiof1_clk),
+ SH_PFC_PIN_GROUP(msiof1_sync),
+ SH_PFC_PIN_GROUP(msiof1_ss1),
+ SH_PFC_PIN_GROUP(msiof1_ss2),
+ SH_PFC_PIN_GROUP(msiof1_txd),
+ SH_PFC_PIN_GROUP(msiof1_rxd),
+ SH_PFC_PIN_GROUP(msiof2_clk),
+ SH_PFC_PIN_GROUP(msiof2_sync),
+ SH_PFC_PIN_GROUP(msiof2_ss1),
+ SH_PFC_PIN_GROUP(msiof2_ss2),
+ SH_PFC_PIN_GROUP(msiof2_txd),
+ SH_PFC_PIN_GROUP(msiof2_rxd),
+ SH_PFC_PIN_GROUP(msiof3_clk),
+ SH_PFC_PIN_GROUP(msiof3_sync),
+ SH_PFC_PIN_GROUP(msiof3_ss1),
+ SH_PFC_PIN_GROUP(msiof3_ss2),
+ SH_PFC_PIN_GROUP(msiof3_txd),
+ SH_PFC_PIN_GROUP(msiof3_rxd),
+ SH_PFC_PIN_GROUP(pwm0_a),
+ SH_PFC_PIN_GROUP(pwm0_b),
+ SH_PFC_PIN_GROUP(pwm1_a),
+ SH_PFC_PIN_GROUP(pwm1_b),
+ SH_PFC_PIN_GROUP(pwm2_a),
+ SH_PFC_PIN_GROUP(pwm2_b),
+ SH_PFC_PIN_GROUP(pwm3_a),
+ SH_PFC_PIN_GROUP(pwm3_b),
+ SH_PFC_PIN_GROUP(pwm4_a),
+ SH_PFC_PIN_GROUP(pwm4_b),
+ SH_PFC_PIN_GROUP(qspi0_ctrl),
+ SH_PFC_PIN_GROUP(qspi0_data2),
+ SH_PFC_PIN_GROUP(qspi0_data4),
+ SH_PFC_PIN_GROUP(qspi1_ctrl),
+ SH_PFC_PIN_GROUP(qspi1_data2),
+ SH_PFC_PIN_GROUP(qspi1_data4),
+ SH_PFC_PIN_GROUP(scif0_data),
+ SH_PFC_PIN_GROUP(scif0_clk),
+ SH_PFC_PIN_GROUP(scif0_ctrl),
+ SH_PFC_PIN_GROUP(scif1_data_a),
+ SH_PFC_PIN_GROUP(scif1_clk),
+ SH_PFC_PIN_GROUP(scif1_ctrl),
+ SH_PFC_PIN_GROUP(scif1_data_b),
+ SH_PFC_PIN_GROUP(scif3_data),
+ SH_PFC_PIN_GROUP(scif3_clk),
+ SH_PFC_PIN_GROUP(scif3_ctrl),
+ SH_PFC_PIN_GROUP(scif4_data),
+ SH_PFC_PIN_GROUP(scif4_clk),
+ SH_PFC_PIN_GROUP(scif4_ctrl),
+ SH_PFC_PIN_GROUP(scif_clk_a),
+ SH_PFC_PIN_GROUP(scif_clk_b),
+ SH_PFC_PIN_GROUP(tmu_tclk1_a),
+ SH_PFC_PIN_GROUP(tmu_tclk1_b),
+ SH_PFC_PIN_GROUP(tmu_tclk2_a),
+ SH_PFC_PIN_GROUP(tmu_tclk2_b),
+ SH_PFC_PIN_GROUP(tpu_to0),
+ SH_PFC_PIN_GROUP(tpu_to1),
+ SH_PFC_PIN_GROUP(tpu_to2),
+ SH_PFC_PIN_GROUP(tpu_to3),
+ VIN_DATA_PIN_GROUP(vin0_data, 8),
+ VIN_DATA_PIN_GROUP(vin0_data, 10),
+ VIN_DATA_PIN_GROUP(vin0_data, 12),
+ VIN_DATA_PIN_GROUP(vin0_data, 16),
+ SH_PFC_PIN_GROUP(vin0_data18),
+ VIN_DATA_PIN_GROUP(vin0_data, 20),
+ VIN_DATA_PIN_GROUP(vin0_data, 24),
+ SH_PFC_PIN_GROUP(vin0_sync),
+ SH_PFC_PIN_GROUP(vin0_field),
+ SH_PFC_PIN_GROUP(vin0_clkenb),
+ SH_PFC_PIN_GROUP(vin0_clk),
+ VIN_DATA_PIN_GROUP(vin1_data, 8),
+ VIN_DATA_PIN_GROUP(vin1_data, 10),
+ VIN_DATA_PIN_GROUP(vin1_data, 12),
+ SH_PFC_PIN_GROUP(vin1_sync),
+ SH_PFC_PIN_GROUP(vin1_field),
+ SH_PFC_PIN_GROUP(vin1_clkenb),
+ SH_PFC_PIN_GROUP(vin1_clk),
+};
+
+static const char * const avb_groups[] = {
+ "avb_link",
+ "avb_magic",
+ "avb_phy_int",
+ "avb_mdio",
+ "avb_rgmii",
+ "avb_txcrefclk",
+ "avb_avtp_pps",
+ "avb_avtp_capture",
+ "avb_avtp_match",
+};
+
+static const char * const canfd0_groups[] = {
+ "canfd0_data_a",
+ "canfd0_data_b",
+};
+
+static const char * const canfd1_groups[] = {
+ "canfd1_data",
+};
+
+static const char * const canfd_clk_groups[] = {
+ "canfd_clk_a",
+ "canfd_clk_b",
+};
+
+static const char * const du_groups[] = {
+ "du_rgb666",
+ "du_rgb888",
+ "du_clk_out",
+ "du_sync",
+ "du_oddf",
+ "du_cde",
+ "du_disp",
+};
+
+static const char * const gether_groups[] = {
+ "gether_link_a",
+ "gether_phy_int_a",
+ "gether_mdio_a",
+ "gether_link_b",
+ "gether_phy_int_b",
+ "gether_mdio_b",
+ "gether_magic",
+ "gether_rgmii",
+ "gether_txcrefclk",
+ "gether_txcrefclk_mega",
+ "gether_rmii",
+};
+
+static const char * const hscif0_groups[] = {
+ "hscif0_data_a",
+ "hscif0_clk_a",
+ "hscif0_ctrl_a",
+ "hscif0_data_b",
+ "hscif0_clk_b",
+ "hscif0_ctrl_b",
+};
+
+static const char * const hscif1_groups[] = {
+ "hscif1_data",
+ "hscif1_clk",
+ "hscif1_ctrl",
+};
+
+static const char * const hscif2_groups[] = {
+ "hscif2_data",
+ "hscif2_clk",
+ "hscif2_ctrl",
+};
+
+static const char * const hscif3_groups[] = {
+ "hscif3_data",
+ "hscif3_clk",
+ "hscif3_ctrl",
+};
+
+static const char * const i2c0_groups[] = {
+ "i2c0",
+};
+
+static const char * const i2c1_groups[] = {
+ "i2c1",
+};
+
+static const char * const i2c2_groups[] = {
+ "i2c2",
+};
+
+static const char * const i2c3_groups[] = {
+ "i2c3",
+};
+
+static const char * const i2c4_groups[] = {
+ "i2c4",
+};
+
+static const char * const i2c5_groups[] = {
+ "i2c5",
+};
+
+static const char * const intc_ex_groups[] = {
+ "intc_ex_irq0",
+ "intc_ex_irq1",
+ "intc_ex_irq2",
+ "intc_ex_irq3",
+ "intc_ex_irq4",
+ "intc_ex_irq5",
+};
+
+static const char * const mmc_groups[] = {
+ "mmc_data1",
+ "mmc_data4",
+ "mmc_data8",
+ "mmc_ctrl",
+ "mmc_cd",
+ "mmc_wp",
+ "mmc_ds",
+};
+
+static const char * const msiof0_groups[] = {
+ "msiof0_clk",
+ "msiof0_sync",
+ "msiof0_ss1",
+ "msiof0_ss2",
+ "msiof0_txd",
+ "msiof0_rxd",
+};
+
+static const char * const msiof1_groups[] = {
+ "msiof1_clk",
+ "msiof1_sync",
+ "msiof1_ss1",
+ "msiof1_ss2",
+ "msiof1_txd",
+ "msiof1_rxd",
+};
+
+static const char * const msiof2_groups[] = {
+ "msiof2_clk",
+ "msiof2_sync",
+ "msiof2_ss1",
+ "msiof2_ss2",
+ "msiof2_txd",
+ "msiof2_rxd",
+};
+
+static const char * const msiof3_groups[] = {
+ "msiof3_clk",
+ "msiof3_sync",
+ "msiof3_ss1",
+ "msiof3_ss2",
+ "msiof3_txd",
+ "msiof3_rxd",
+};
+
+static const char * const pwm0_groups[] = {
+ "pwm0_a",
+ "pwm0_b",
+};
+
+static const char * const pwm1_groups[] = {
+ "pwm1_a",
+ "pwm1_b",
+};
+
+static const char * const pwm2_groups[] = {
+ "pwm2_a",
+ "pwm2_b",
+};
+
+static const char * const pwm3_groups[] = {
+ "pwm3_a",
+ "pwm3_b",
+};
+
+static const char * const pwm4_groups[] = {
+ "pwm4_a",
+ "pwm4_b",
+};
+
+static const char * const qspi0_groups[] = {
+ "qspi0_ctrl",
+ "qspi0_data2",
+ "qspi0_data4",
+};
+
+static const char * const qspi1_groups[] = {
+ "qspi1_ctrl",
+ "qspi1_data2",
+ "qspi1_data4",
+};
+
+static const char * const scif0_groups[] = {
+ "scif0_data",
+ "scif0_clk",
+ "scif0_ctrl",
+};
+
+static const char * const scif1_groups[] = {
+ "scif1_data_a",
+ "scif1_clk",
+ "scif1_ctrl",
+ "scif1_data_b",
+};
+
+static const char * const scif3_groups[] = {
+ "scif3_data",
+ "scif3_clk",
+ "scif3_ctrl",
+};
+
+static const char * const scif4_groups[] = {
+ "scif4_data",
+ "scif4_clk",
+ "scif4_ctrl",
+};
+
+static const char * const scif_clk_groups[] = {
+ "scif_clk_a",
+ "scif_clk_b",
+};
+
+static const char * const tmu_groups[] = {
+ "tmu_tclk1_a",
+ "tmu_tclk1_b",
+ "tmu_tclk2_a",
+ "tmu_tclk2_b",
+};
+
+static const char * const tpu_groups[] = {
+ "tpu_to0",
+ "tpu_to1",
+ "tpu_to2",
+ "tpu_to3",
+};
+
+static const char * const vin0_groups[] = {
+ "vin0_data8",
+ "vin0_data10",
+ "vin0_data12",
+ "vin0_data16",
+ "vin0_data18",
+ "vin0_data20",
+ "vin0_data24",
+ "vin0_sync",
+ "vin0_field",
+ "vin0_clkenb",
+ "vin0_clk",
+};
+
+static const char * const vin1_groups[] = {
+ "vin1_data8",
+ "vin1_data10",
+ "vin1_data12",
+ "vin1_sync",
+ "vin1_field",
+ "vin1_clkenb",
+ "vin1_clk",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+ SH_PFC_FUNCTION(avb),
+ SH_PFC_FUNCTION(canfd0),
+ SH_PFC_FUNCTION(canfd1),
+ SH_PFC_FUNCTION(canfd_clk),
+ SH_PFC_FUNCTION(du),
+ SH_PFC_FUNCTION(gether),
+ SH_PFC_FUNCTION(hscif0),
+ SH_PFC_FUNCTION(hscif1),
+ SH_PFC_FUNCTION(hscif2),
+ SH_PFC_FUNCTION(hscif3),
+ SH_PFC_FUNCTION(i2c0),
+ SH_PFC_FUNCTION(i2c1),
+ SH_PFC_FUNCTION(i2c2),
+ SH_PFC_FUNCTION(i2c3),
+ SH_PFC_FUNCTION(i2c4),
+ SH_PFC_FUNCTION(i2c5),
+ SH_PFC_FUNCTION(intc_ex),
+ SH_PFC_FUNCTION(mmc),
+ SH_PFC_FUNCTION(msiof0),
+ SH_PFC_FUNCTION(msiof1),
+ SH_PFC_FUNCTION(msiof2),
+ SH_PFC_FUNCTION(msiof3),
+ SH_PFC_FUNCTION(pwm0),
+ SH_PFC_FUNCTION(pwm1),
+ SH_PFC_FUNCTION(pwm2),
+ SH_PFC_FUNCTION(pwm3),
+ SH_PFC_FUNCTION(pwm4),
+ SH_PFC_FUNCTION(qspi0),
+ SH_PFC_FUNCTION(qspi1),
+ SH_PFC_FUNCTION(scif0),
+ SH_PFC_FUNCTION(scif1),
+ SH_PFC_FUNCTION(scif3),
+ SH_PFC_FUNCTION(scif4),
+ SH_PFC_FUNCTION(scif_clk),
+ SH_PFC_FUNCTION(tmu),
+ SH_PFC_FUNCTION(tpu),
+ SH_PFC_FUNCTION(vin0),
+ SH_PFC_FUNCTION(vin1),
+};
+
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
+#define F_(x, y) FN_##y
+#define FM(x) FN_##x
+ { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_0_21_FN, GPSR0_21,
+ GP_0_20_FN, GPSR0_20,
+ GP_0_19_FN, GPSR0_19,
+ GP_0_18_FN, GPSR0_18,
+ GP_0_17_FN, GPSR0_17,
+ GP_0_16_FN, GPSR0_16,
+ GP_0_15_FN, GPSR0_15,
+ GP_0_14_FN, GPSR0_14,
+ GP_0_13_FN, GPSR0_13,
+ GP_0_12_FN, GPSR0_12,
+ GP_0_11_FN, GPSR0_11,
+ GP_0_10_FN, GPSR0_10,
+ GP_0_9_FN, GPSR0_9,
+ GP_0_8_FN, GPSR0_8,
+ GP_0_7_FN, GPSR0_7,
+ GP_0_6_FN, GPSR0_6,
+ GP_0_5_FN, GPSR0_5,
+ GP_0_4_FN, GPSR0_4,
+ GP_0_3_FN, GPSR0_3,
+ GP_0_2_FN, GPSR0_2,
+ GP_0_1_FN, GPSR0_1,
+ GP_0_0_FN, GPSR0_0, ))
+ },
+ { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_1_27_FN, GPSR1_27,
+ GP_1_26_FN, GPSR1_26,
+ GP_1_25_FN, GPSR1_25,
+ GP_1_24_FN, GPSR1_24,
+ GP_1_23_FN, GPSR1_23,
+ GP_1_22_FN, GPSR1_22,
+ GP_1_21_FN, GPSR1_21,
+ GP_1_20_FN, GPSR1_20,
+ GP_1_19_FN, GPSR1_19,
+ GP_1_18_FN, GPSR1_18,
+ GP_1_17_FN, GPSR1_17,
+ GP_1_16_FN, GPSR1_16,
+ GP_1_15_FN, GPSR1_15,
+ GP_1_14_FN, GPSR1_14,
+ GP_1_13_FN, GPSR1_13,
+ GP_1_12_FN, GPSR1_12,
+ GP_1_11_FN, GPSR1_11,
+ GP_1_10_FN, GPSR1_10,
+ GP_1_9_FN, GPSR1_9,
+ GP_1_8_FN, GPSR1_8,
+ GP_1_7_FN, GPSR1_7,
+ GP_1_6_FN, GPSR1_6,
+ GP_1_5_FN, GPSR1_5,
+ GP_1_4_FN, GPSR1_4,
+ GP_1_3_FN, GPSR1_3,
+ GP_1_2_FN, GPSR1_2,
+ GP_1_1_FN, GPSR1_1,
+ GP_1_0_FN, GPSR1_0, ))
+ },
+ { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
+ 0, 0,
+ 0, 0,
+ GP_2_29_FN, GPSR2_29,
+ GP_2_28_FN, GPSR2_28,
+ GP_2_27_FN, GPSR2_27,
+ GP_2_26_FN, GPSR2_26,
+ GP_2_25_FN, GPSR2_25,
+ GP_2_24_FN, GPSR2_24,
+ GP_2_23_FN, GPSR2_23,
+ GP_2_22_FN, GPSR2_22,
+ GP_2_21_FN, GPSR2_21,
+ GP_2_20_FN, GPSR2_20,
+ GP_2_19_FN, GPSR2_19,
+ GP_2_18_FN, GPSR2_18,
+ GP_2_17_FN, GPSR2_17,
+ GP_2_16_FN, GPSR2_16,
+ GP_2_15_FN, GPSR2_15,
+ GP_2_14_FN, GPSR2_14,
+ GP_2_13_FN, GPSR2_13,
+ GP_2_12_FN, GPSR2_12,
+ GP_2_11_FN, GPSR2_11,
+ GP_2_10_FN, GPSR2_10,
+ GP_2_9_FN, GPSR2_9,
+ GP_2_8_FN, GPSR2_8,
+ GP_2_7_FN, GPSR2_7,
+ GP_2_6_FN, GPSR2_6,
+ GP_2_5_FN, GPSR2_5,
+ GP_2_4_FN, GPSR2_4,
+ GP_2_3_FN, GPSR2_3,
+ GP_2_2_FN, GPSR2_2,
+ GP_2_1_FN, GPSR2_1,
+ GP_2_0_FN, GPSR2_0, ))
+ },
+ { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_3_16_FN, GPSR3_16,
+ GP_3_15_FN, GPSR3_15,
+ GP_3_14_FN, GPSR3_14,
+ GP_3_13_FN, GPSR3_13,
+ GP_3_12_FN, GPSR3_12,
+ GP_3_11_FN, GPSR3_11,
+ GP_3_10_FN, GPSR3_10,
+ GP_3_9_FN, GPSR3_9,
+ GP_3_8_FN, GPSR3_8,
+ GP_3_7_FN, GPSR3_7,
+ GP_3_6_FN, GPSR3_6,
+ GP_3_5_FN, GPSR3_5,
+ GP_3_4_FN, GPSR3_4,
+ GP_3_3_FN, GPSR3_3,
+ GP_3_2_FN, GPSR3_2,
+ GP_3_1_FN, GPSR3_1,
+ GP_3_0_FN, GPSR3_0, ))
+ },
+ { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_4_24_FN, GPSR4_24,
+ GP_4_23_FN, GPSR4_23,
+ GP_4_22_FN, GPSR4_22,
+ GP_4_21_FN, GPSR4_21,
+ GP_4_20_FN, GPSR4_20,
+ GP_4_19_FN, GPSR4_19,
+ GP_4_18_FN, GPSR4_18,
+ GP_4_17_FN, GPSR4_17,
+ GP_4_16_FN, GPSR4_16,
+ GP_4_15_FN, GPSR4_15,
+ GP_4_14_FN, GPSR4_14,
+ GP_4_13_FN, GPSR4_13,
+ GP_4_12_FN, GPSR4_12,
+ GP_4_11_FN, GPSR4_11,
+ GP_4_10_FN, GPSR4_10,
+ GP_4_9_FN, GPSR4_9,
+ GP_4_8_FN, GPSR4_8,
+ GP_4_7_FN, GPSR4_7,
+ GP_4_6_FN, GPSR4_6,
+ GP_4_5_FN, GPSR4_5,
+ GP_4_4_FN, GPSR4_4,
+ GP_4_3_FN, GPSR4_3,
+ GP_4_2_FN, GPSR4_2,
+ GP_4_1_FN, GPSR4_1,
+ GP_4_0_FN, GPSR4_0, ))
+ },
+ { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_5_14_FN, GPSR5_14,
+ GP_5_13_FN, GPSR5_13,
+ GP_5_12_FN, GPSR5_12,
+ GP_5_11_FN, GPSR5_11,
+ GP_5_10_FN, GPSR5_10,
+ GP_5_9_FN, GPSR5_9,
+ GP_5_8_FN, GPSR5_8,
+ GP_5_7_FN, GPSR5_7,
+ GP_5_6_FN, GPSR5_6,
+ GP_5_5_FN, GPSR5_5,
+ GP_5_4_FN, GPSR5_4,
+ GP_5_3_FN, GPSR5_3,
+ GP_5_2_FN, GPSR5_2,
+ GP_5_1_FN, GPSR5_1,
+ GP_5_0_FN, GPSR5_0, ))
+ },
+#undef F_
+#undef FM
+
+#define F_(x, y) x,
+#define FM(x) FN_##x,
+ { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
+ IP0_31_28
+ IP0_27_24
+ IP0_23_20
+ IP0_19_16
+ IP0_15_12
+ IP0_11_8
+ IP0_7_4
+ IP0_3_0 ))
+ },
+ { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
+ IP1_31_28
+ IP1_27_24
+ IP1_23_20
+ IP1_19_16
+ IP1_15_12
+ IP1_11_8
+ IP1_7_4
+ IP1_3_0 ))
+ },
+ { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
+ IP2_31_28
+ IP2_27_24
+ IP2_23_20
+ IP2_19_16
+ IP2_15_12
+ IP2_11_8
+ IP2_7_4
+ IP2_3_0 ))
+ },
+ { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
+ IP3_31_28
+ IP3_27_24
+ IP3_23_20
+ IP3_19_16
+ IP3_15_12
+ IP3_11_8
+ IP3_7_4
+ IP3_3_0 ))
+ },
+ { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
+ IP4_31_28
+ IP4_27_24
+ IP4_23_20
+ IP4_19_16
+ IP4_15_12
+ IP4_11_8
+ IP4_7_4
+ IP4_3_0 ))
+ },
+ { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
+ IP5_31_28
+ IP5_27_24
+ IP5_23_20
+ IP5_19_16
+ IP5_15_12
+ IP5_11_8
+ IP5_7_4
+ IP5_3_0 ))
+ },
+ { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
+ IP6_31_28
+ IP6_27_24
+ IP6_23_20
+ IP6_19_16
+ IP6_15_12
+ IP6_11_8
+ IP6_7_4
+ IP6_3_0 ))
+ },
+ { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
+ IP7_31_28
+ IP7_27_24
+ IP7_23_20
+ IP7_19_16
+ IP7_15_12
+ IP7_11_8
+ IP7_7_4
+ IP7_3_0 ))
+ },
+ { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
+ IP8_31_28
+ IP8_27_24
+ IP8_23_20
+ IP8_19_16
+ IP8_15_12
+ IP8_11_8
+ IP8_7_4
+ IP8_3_0 ))
+ },
+ { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
+ IP9_31_28
+ IP9_27_24
+ IP9_23_20
+ IP9_19_16
+ IP9_15_12
+ IP9_11_8
+ IP9_7_4
+ IP9_3_0 ))
+ },
+ { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
+ IP10_31_28
+ IP10_27_24
+ IP10_23_20
+ IP10_19_16
+ IP10_15_12
+ IP10_11_8
+ IP10_7_4
+ IP10_3_0 ))
+ },
+#undef F_
+#undef FM
+
+#define F_(x, y) x,
+#define FM(x) FN_##x,
+ { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
+ GROUP(4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1),
+ GROUP(
+ /* RESERVED 31, 30, 29, 28 */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESERVED 27, 26, 25, 24 */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESERVED 23, 22, 21, 20 */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESERVED 19, 18, 17, 16 */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESERVED 15, 14, 13, 12 */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ MOD_SEL0_11
+ MOD_SEL0_10
+ MOD_SEL0_9
+ MOD_SEL0_8
+ MOD_SEL0_7
+ MOD_SEL0_6
+ MOD_SEL0_5
+ MOD_SEL0_4
+ 0, 0,
+ MOD_SEL0_2
+ MOD_SEL0_1
+ MOD_SEL0_0 ))
+ },
+ { },
+};
+
+enum ioctrl_regs {
+ POCCTRL0,
+ POCCTRL1,
+ POCCTRL2,
+ POCCTRL3,
+ TDSELCTRL,
+};
+
+static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
+ [POCCTRL0] = { 0xe6060380, },
+ [POCCTRL1] = { 0xe6060384, },
+ [POCCTRL2] = { 0xe6060388, },
+ [POCCTRL3] = { 0xe606038c, },
+ [TDSELCTRL] = { 0xe60603c0, },
+ { /* sentinel */ },
+};
+
+static int r8a77980_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
+ u32 *pocctrl)
+{
+ int bit = pin & 0x1f;
+
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
+ if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
+ return bit;
+ else if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
+ return bit + 22;
+
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
+ if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
+ return bit - 10;
+ if ((pin >= RCAR_GP_PIN(2, 17) && pin <= RCAR_GP_PIN(2, 24)) ||
+ (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16)))
+ return bit + 7;
+
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
+ if (pin >= RCAR_GP_PIN(2, 25) && pin <= RCAR_GP_PIN(2, 29))
+ return pin - 25;
+
+ return -EINVAL;
+}
+
+static const struct sh_pfc_soc_operations pinmux_ops = {
+ .pin_to_pocctrl = r8a77980_pin_to_pocctrl,
+};
+
+const struct sh_pfc_soc_info r8a77980_pinmux_info = {
+ .name = "r8a77980_pfc",
+ .ops = &pinmux_ops,
+ .unlock_reg = 0xe6060000, /* PMMR */
+
+ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .groups = pinmux_groups,
+ .nr_groups = ARRAY_SIZE(pinmux_groups),
+ .functions = pinmux_functions,
+ .nr_functions = ARRAY_SIZE(pinmux_functions),
+
+ .cfg_regs = pinmux_config_regs,
+ .ioctrl_regs = pinmux_ioctrl_regs,
+
+ .pinmux_data = pinmux_data,
+ .pinmux_data_size = ARRAY_SIZE(pinmux_data),
+};
diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c
index 1cf08ae..5313f2f 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77990.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77990.c
@@ -2,7 +2,7 @@
/*
* R8A77990 processor support - PFC hardware block.
*
- * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018-2019 Renesas Electronics Corp.
*
* This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
*
@@ -168,7 +168,7 @@
#define GPSR5_7 F_(SCK2_A, IP12_7_4)
#define GPSR5_6 F_(TX1, IP12_3_0)
#define GPSR5_5 F_(RX1, IP11_31_28)
-#define GPSR5_4 F_(RTS0_N_TANS_A, IP11_23_20)
+#define GPSR5_4 F_(RTS0_N_A, IP11_23_20)
#define GPSR5_3 F_(CTS0_N_A, IP11_19_16)
#define GPSR5_2 F_(TX0_A, IP11_15_12)
#define GPSR5_1 F_(RX0_A, IP11_11_8)
@@ -222,7 +222,7 @@
#define IP3_3_0 FM(A1) FM(IRQ1) FM(PWM3_A) FM(DU_DOTCLKIN1) FM(VI5_DATA0_A) FM(DU_DISP_CDE) FM(SDA6_B) FM(IETX) FM(QCPV_QDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_7_4 FM(A2) FM(IRQ2) FM(AVB_AVTP_PPS) FM(VI4_CLKENB) FM(VI5_DATA1_A) FM(DU_DISP) FM(SCL6_B) F_(0, 0) FM(QSTVB_QVE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_11_8 FM(A3) FM(CTS4_N_A) FM(PWM4_A) FM(VI4_DATA12) F_(0, 0) FM(DU_DOTCLKOUT0) FM(HTX3_D) FM(IECLK) FM(LCDOUT12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3_15_12 FM(A4) FM(RTS4_N_TANS_A) FM(MSIOF3_SYNC_B) FM(VI4_DATA8) FM(PWM2_B) FM(DU_DG4) FM(RIF2_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_15_12 FM(A4) FM(RTS4_N_A) FM(MSIOF3_SYNC_B) FM(VI4_DATA8) FM(PWM2_B) FM(DU_DG4) FM(RIF2_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_19_16 FM(A5) FM(SCK4_A) FM(MSIOF3_SCK_B) FM(VI4_DATA9) FM(PWM3_B) F_(0, 0) FM(RIF2_SYNC_B) F_(0, 0) FM(QPOLA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_23_20 FM(A6) FM(RX4_A) FM(MSIOF3_RXD_B) FM(VI4_DATA10) F_(0, 0) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_27_24 FM(A7) FM(TX4_A) FM(MSIOF3_TXD_B) FM(VI4_DATA11) F_(0, 0) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -243,10 +243,10 @@
#define IP5_15_12 FM(CS0_N) FM(SCL5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR0) FM(VI4_DATA2_B) F_(0, 0) FM(LCDOUT16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_19_16 FM(WE0_N) FM(SDA5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR1) FM(VI4_DATA3_B) F_(0, 0) FM(LCDOUT17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_23_20 FM(D0) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR2) FM(CTS4_N_C) F_(0, 0) FM(LCDOUT18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP5_27_24 FM(D1) FM(MSIOF3_SYNC_A) FM(SCK3_A) FM(VI4_DATA23) FM(VI5_CLKENB_A) FM(DU_DB7) FM(RTS4_N_TANS_C) F_(0, 0) FM(LCDOUT7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_27_24 FM(D1) FM(MSIOF3_SYNC_A) FM(SCK3_A) FM(VI4_DATA23) FM(VI5_CLKENB_A) FM(DU_DB7) FM(RTS4_N_C) F_(0, 0) FM(LCDOUT7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_31_28 FM(D2) FM(MSIOF3_RXD_A) FM(RX5_C) F_(0, 0) FM(VI5_DATA14_A) FM(DU_DR3) FM(RX4_C) F_(0, 0) FM(LCDOUT19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_3_0 FM(D3) FM(MSIOF3_TXD_A) FM(TX5_C) F_(0, 0) FM(VI5_DATA15_A) FM(DU_DR4) FM(TX4_C) F_(0, 0) FM(LCDOUT20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP6_7_4 FM(D4) FM(CANFD1_TX) FM(HSCK3_B) FM(CAN1_TX) FM(RTS3_N_TANS_A) FM(MSIOF3_SS2_A) F_(0, 0) FM(VI5_DATA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_7_4 FM(D4) FM(CANFD1_TX) FM(HSCK3_B) FM(CAN1_TX) FM(RTS3_N_A) FM(MSIOF3_SS2_A) F_(0, 0) FM(VI5_DATA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_11_8 FM(D5) FM(RX3_A) FM(HRX3_B) F_(0, 0) F_(0, 0) FM(DU_DR5) FM(VI4_DATA4_B) F_(0, 0) FM(LCDOUT21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_15_12 FM(D6) FM(TX3_A) FM(HTX3_B) F_(0, 0) F_(0, 0) FM(DU_DR6) FM(VI4_DATA5_B) F_(0, 0) FM(LCDOUT22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_19_16 FM(D7) FM(CANFD1_RX) FM(IRQ5) FM(CAN1_RX) FM(CTS3_N_A) F_(0, 0) F_(0, 0) FM(VI5_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -292,8 +292,8 @@
#define IP11_11_8 FM(RX0_A) FM(HRX1_A) FM(SSI_SCK2_A) FM(RIF1_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_15_12 FM(TX0_A) FM(HTX1_A) FM(SSI_WS2_A) FM(RIF1_D0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_19_16 FM(CTS0_N_A) FM(NFDATA14_A) FM(AUDIO_CLKOUT_A) FM(RIF1_D1) FM(SCIF_CLK_A) FM(FMCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_23_20 FM(RTS0_N_TANS_A) FM(NFDATA15_A) FM(AUDIO_CLKOUT1_A) FM(RIF1_CLK) FM(SCL2_A) FM(FMIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_27_24 FM(SCK0_A) FM(HSCK1_A) FM(USB3HS0_ID) FM(RTS1_N_TANS) FM(SDA2_A) FM(FMCLK_C) F_(0, 0) F_(0, 0) FM(USB0_ID) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_23_20 FM(RTS0_N_A) FM(NFDATA15_A) FM(AUDIO_CLKOUT1_A) FM(RIF1_CLK) FM(SCL2_A) FM(FMIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_27_24 FM(SCK0_A) FM(HSCK1_A) FM(USB3HS0_ID) FM(RTS1_N) FM(SDA2_A) FM(FMCLK_C) F_(0, 0) F_(0, 0) FM(USB0_ID) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_31_28 FM(RX1) FM(HRX2_B) FM(SSI_SCK9_B) FM(AUDIO_CLKOUT1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */
@@ -417,7 +417,7 @@
#define MOD_SEL0_22 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1)
#define MOD_SEL0_21_20 REV4(FM(SEL_I2C1_0), FM(SEL_I2C1_1), FM(SEL_I2C1_2), FM(SEL_I2C1_3))
#define MOD_SEL0_19_18_17 REV8(FM(SEL_I2C2_0), FM(SEL_I2C2_1), FM(SEL_I2C2_2), FM(SEL_I2C2_3), FM(SEL_I2C2_4), F_(0, 0), F_(0, 0), F_(0, 0))
-#define MOD_SEL0_16 FM(SEL_NDFC_0) FM(SEL_NDFC_1)
+#define MOD_SEL0_16 FM(SEL_NDF_0) FM(SEL_NDF_1)
#define MOD_SEL0_15 FM(SEL_PWM0_0) FM(SEL_PWM0_1)
#define MOD_SEL0_14 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
#define MOD_SEL0_13_12 REV4(FM(SEL_PWM2_0), FM(SEL_PWM2_1), FM(SEL_PWM2_2), F_(0, 0))
@@ -432,8 +432,6 @@
#define MOD_SEL0_1_0 REV4(FM(SEL_SPEED_PULSE_IF_0), FM(SEL_SPEED_PULSE_IF_1), FM(SEL_SPEED_PULSE_IF_2), F_(0, 0))
/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
-#define MOD_SEL1_31 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1)
-#define MOD_SEL1_30 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
#define MOD_SEL1_29 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
#define MOD_SEL1_28 FM(SEL_USB_20_CH0_0) FM(SEL_USB_20_CH0_1)
#define MOD_SEL1_26 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
@@ -454,8 +452,7 @@
#define PINMUX_MOD_SELS \
\
- MOD_SEL1_31 \
-MOD_SEL0_30_29 MOD_SEL1_30 \
+MOD_SEL0_30_29 \
MOD_SEL1_29 \
MOD_SEL0_28 MOD_SEL1_28 \
MOD_SEL0_27_26 \
@@ -674,7 +671,7 @@
PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT12),
PINMUX_IPSR_GPSR(IP3_15_12, A4),
- PINMUX_IPSR_MSEL(IP3_15_12, RTS4_N_TANS_A, SEL_SCIF4_0),
+ PINMUX_IPSR_MSEL(IP3_15_12, RTS4_N_A, SEL_SCIF4_0),
PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SYNC_B, SEL_MSIOF3_1),
PINMUX_IPSR_GPSR(IP3_15_12, VI4_DATA8),
PINMUX_IPSR_MSEL(IP3_15_12, PWM2_B, SEL_PWM2_1),
@@ -824,7 +821,7 @@
PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA23),
PINMUX_IPSR_MSEL(IP5_27_24, VI5_CLKENB_A, SEL_VIN5_0),
PINMUX_IPSR_GPSR(IP5_27_24, DU_DB7),
- PINMUX_IPSR_MSEL(IP5_27_24, RTS4_N_TANS_C, SEL_SCIF4_2),
+ PINMUX_IPSR_MSEL(IP5_27_24, RTS4_N_C, SEL_SCIF4_2),
PINMUX_IPSR_GPSR(IP5_27_24, LCDOUT7),
PINMUX_IPSR_GPSR(IP5_31_28, D2),
@@ -848,7 +845,7 @@
PINMUX_IPSR_GPSR(IP6_7_4, CANFD1_TX),
PINMUX_IPSR_MSEL(IP6_7_4, HSCK3_B, SEL_HSCIF3_1),
PINMUX_IPSR_GPSR(IP6_7_4, CAN1_TX),
- PINMUX_IPSR_MSEL(IP6_7_4, RTS3_N_TANS_A, SEL_SCIF3_0),
+ PINMUX_IPSR_MSEL(IP6_7_4, RTS3_N_A, SEL_SCIF3_0),
PINMUX_IPSR_GPSR(IP6_7_4, MSIOF3_SS2_A),
PINMUX_IPSR_MSEL(IP6_7_4, VI5_DATA1_B, SEL_VIN5_1),
@@ -987,23 +984,23 @@
PINMUX_IPSR_MSEL(IP8_19_16, REMOCON_C, SEL_REMOCON_2),
PINMUX_IPSR_GPSR(IP8_23_20, SD1_CLK),
- PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
PINMUX_IPSR_GPSR(IP8_27_24, SD1_CMD),
- PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT0),
- PINMUX_IPSR_MSEL(IP8_31_28, NFWP_N_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP8_31_28, NFWP_N_B, SEL_NDF_1),
/* IPSR9 */
PINMUX_IPSR_GPSR(IP9_3_0, SD1_DAT1),
- PINMUX_IPSR_MSEL(IP9_3_0, NFCE_N_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP9_3_0, NFCE_N_B, SEL_NDF_1),
PINMUX_IPSR_GPSR(IP9_7_4, SD1_DAT2),
- PINMUX_IPSR_MSEL(IP9_7_4, NFALE_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP9_7_4, NFALE_B, SEL_NDF_1),
PINMUX_IPSR_GPSR(IP9_11_8, SD1_DAT3),
- PINMUX_IPSR_MSEL(IP9_11_8, NFRB_N_B, SEL_NDFC_1),
+ PINMUX_IPSR_MSEL(IP9_11_8, NFRB_N_B, SEL_NDF_1),
PINMUX_IPSR_GPSR(IP9_15_12, SD3_CLK),
PINMUX_IPSR_GPSR(IP9_15_12, NFWE_N),
@@ -1040,57 +1037,57 @@
PINMUX_IPSR_GPSR(IP10_23_20, NFCLE),
PINMUX_IPSR_GPSR(IP10_27_24, SD0_CD),
- PINMUX_IPSR_GPSR(IP10_27_24, NFALE_A),
+ PINMUX_IPSR_MSEL(IP10_27_24, NFALE_A, SEL_NDF_0),
PINMUX_IPSR_GPSR(IP10_27_24, SD3_CD),
PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1),
PINMUX_IPSR_MSEL(IP10_27_24, SCL2_B, SEL_I2C2_1),
PINMUX_IPSR_MSEL(IP10_27_24, TCLK1_A, SEL_TIMER_TMU_0),
- PINMUX_IPSR_MSEL(IP10_27_24, SSI_SCK2_B, SEL_SSI2_1),
+ PINMUX_IPSR_GPSR(IP10_27_24, SSI_SCK2_B),
PINMUX_IPSR_GPSR(IP10_27_24, TS_SCK0),
PINMUX_IPSR_GPSR(IP10_31_28, SD0_WP),
- PINMUX_IPSR_GPSR(IP10_31_28, NFRB_N_A),
+ PINMUX_IPSR_MSEL(IP10_31_28, NFRB_N_A, SEL_NDF_0),
PINMUX_IPSR_GPSR(IP10_31_28, SD3_WP),
PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1),
PINMUX_IPSR_MSEL(IP10_31_28, SDA2_B, SEL_I2C2_1),
PINMUX_IPSR_MSEL(IP10_31_28, TCLK2_A, SEL_TIMER_TMU_0),
- PINMUX_IPSR_MSEL(IP10_31_28, SSI_WS2_B, SEL_SSI2_1),
+ PINMUX_IPSR_GPSR(IP10_31_28, SSI_WS2_B),
PINMUX_IPSR_GPSR(IP10_31_28, TS_SDAT0),
/* IPSR11 */
PINMUX_IPSR_GPSR(IP11_3_0, SD1_CD),
- PINMUX_IPSR_MSEL(IP11_3_0, NFCE_N_A, SEL_NDFC_0),
+ PINMUX_IPSR_MSEL(IP11_3_0, NFCE_N_A, SEL_NDF_0),
PINMUX_IPSR_GPSR(IP11_3_0, SSI_SCK1),
PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1),
PINMUX_IPSR_GPSR(IP11_3_0, TS_SDEN0),
PINMUX_IPSR_GPSR(IP11_7_4, SD1_WP),
- PINMUX_IPSR_MSEL(IP11_7_4, NFWP_N_A, SEL_NDFC_0),
+ PINMUX_IPSR_MSEL(IP11_7_4, NFWP_N_A, SEL_NDF_0),
PINMUX_IPSR_GPSR(IP11_7_4, SSI_WS1),
PINMUX_IPSR_MSEL(IP11_7_4, RIF0_SYNC_B, SEL_DRIF0_1),
PINMUX_IPSR_GPSR(IP11_7_4, TS_SPSYNC0),
PINMUX_IPSR_MSEL(IP11_11_8, RX0_A, SEL_SCIF0_0),
PINMUX_IPSR_MSEL(IP11_11_8, HRX1_A, SEL_HSCIF1_0),
- PINMUX_IPSR_MSEL(IP11_11_8, SSI_SCK2_A, SEL_SSI2_0),
+ PINMUX_IPSR_GPSR(IP11_11_8, SSI_SCK2_A),
PINMUX_IPSR_GPSR(IP11_11_8, RIF1_SYNC),
PINMUX_IPSR_GPSR(IP11_11_8, TS_SCK1),
PINMUX_IPSR_MSEL(IP11_15_12, TX0_A, SEL_SCIF0_0),
PINMUX_IPSR_GPSR(IP11_15_12, HTX1_A),
- PINMUX_IPSR_MSEL(IP11_15_12, SSI_WS2_A, SEL_SSI2_0),
+ PINMUX_IPSR_GPSR(IP11_15_12, SSI_WS2_A),
PINMUX_IPSR_GPSR(IP11_15_12, RIF1_D0),
PINMUX_IPSR_GPSR(IP11_15_12, TS_SDAT1),
PINMUX_IPSR_MSEL(IP11_19_16, CTS0_N_A, SEL_SCIF0_0),
- PINMUX_IPSR_MSEL(IP11_19_16, NFDATA14_A, SEL_NDFC_0),
+ PINMUX_IPSR_MSEL(IP11_19_16, NFDATA14_A, SEL_NDF_0),
PINMUX_IPSR_GPSR(IP11_19_16, AUDIO_CLKOUT_A),
PINMUX_IPSR_GPSR(IP11_19_16, RIF1_D1),
PINMUX_IPSR_MSEL(IP11_19_16, SCIF_CLK_A, SEL_SCIF_0),
PINMUX_IPSR_MSEL(IP11_19_16, FMCLK_A, SEL_FM_0),
- PINMUX_IPSR_MSEL(IP11_23_20, RTS0_N_TANS_A, SEL_SCIF0_0),
- PINMUX_IPSR_MSEL(IP11_23_20, NFDATA15_A, SEL_NDFC_0),
+ PINMUX_IPSR_MSEL(IP11_23_20, RTS0_N_A, SEL_SCIF0_0),
+ PINMUX_IPSR_MSEL(IP11_23_20, NFDATA15_A, SEL_NDF_0),
PINMUX_IPSR_GPSR(IP11_23_20, AUDIO_CLKOUT1_A),
PINMUX_IPSR_GPSR(IP11_23_20, RIF1_CLK),
PINMUX_IPSR_MSEL(IP11_23_20, SCL2_A, SEL_I2C2_0),
@@ -1099,7 +1096,7 @@
PINMUX_IPSR_MSEL(IP11_27_24, SCK0_A, SEL_SCIF0_0),
PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_A, SEL_HSCIF1_0),
PINMUX_IPSR_GPSR(IP11_27_24, USB3HS0_ID),
- PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N_TANS),
+ PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N),
PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP11_27_24, FMCLK_C, SEL_FM_2),
PINMUX_IPSR_GPSR(IP11_27_24, USB0_ID),
@@ -1183,7 +1180,7 @@
PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_A, SEL_DRIF0_0),
PINMUX_IPSR_MSEL(IP13_19_16, SDA1_B, SEL_I2C1_1),
PINMUX_IPSR_MSEL(IP13_19_16, TCLK2_B, SEL_TIMER_TMU_1),
- PINMUX_IPSR_MSEL(IP13_19_16, SIM0_D_A, SEL_SIMCARD_0),
+ PINMUX_IPSR_GPSR(IP13_19_16, SIM0_D_A),
PINMUX_IPSR_GPSR(IP13_23_20, MLB_DAT),
PINMUX_IPSR_MSEL(IP13_23_20, TX0_B, SEL_SCIF0_1),
@@ -1251,7 +1248,7 @@
PINMUX_IPSR_GPSR(IP15_15_12, TPU0TO2),
PINMUX_IPSR_MSEL(IP15_15_12, SDA1_D, SEL_I2C1_3),
PINMUX_IPSR_MSEL(IP15_15_12, FSO_CFE_1_N_B, SEL_FSO_1),
- PINMUX_IPSR_MSEL(IP15_15_12, SIM0_D_B, SEL_SIMCARD_1),
+ PINMUX_IPSR_GPSR(IP15_15_12, SIM0_D_B),
PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA6),
PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
@@ -2842,7 +2839,7 @@
};
static const unsigned int scif0_ctrl_a_mux[] = {
- RTS0_N_TANS_A_MARK, CTS0_N_A_MARK,
+ RTS0_N_A_MARK, CTS0_N_A_MARK,
};
static const unsigned int scif0_data_b_pins[] = {
@@ -2888,7 +2885,7 @@
};
static const unsigned int scif1_ctrl_mux[] = {
- RTS1_N_TANS_MARK, CTS1_N_MARK,
+ RTS1_N_MARK, CTS1_N_MARK,
};
/* - SCIF2 ------------------------------------------------------------------ */
@@ -2944,7 +2941,7 @@
};
static const unsigned int scif3_ctrl_a_mux[] = {
- RTS3_N_TANS_A_MARK, CTS3_N_A_MARK,
+ RTS3_N_A_MARK, CTS3_N_A_MARK,
};
static const unsigned int scif3_data_b_pins[] = {
@@ -2999,7 +2996,7 @@
};
static const unsigned int scif4_ctrl_a_mux[] = {
- RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
+ RTS4_N_A_MARK, CTS4_N_A_MARK,
};
static const unsigned int scif4_data_b_pins[] = {
@@ -3035,7 +3032,7 @@
};
static const unsigned int scif4_ctrl_c_mux[] = {
- RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
+ RTS4_N_C_MARK, CTS4_N_C_MARK,
};
/* - SCIF5 ------------------------------------------------------------------ */
@@ -3769,8 +3766,8 @@
};
static const struct {
- struct sh_pfc_pin_group common[245];
- struct sh_pfc_pin_group automotive[23];
+ struct sh_pfc_pin_group common[247];
+ struct sh_pfc_pin_group automotive[21];
} pinmux_groups = {
.common = {
SH_PFC_PIN_GROUP(audio_clk_a),
@@ -3801,6 +3798,8 @@
SH_PFC_PIN_GROUP(can0_data),
SH_PFC_PIN_GROUP(can1_data),
SH_PFC_PIN_GROUP(can_clk),
+ SH_PFC_PIN_GROUP(canfd0_data),
+ SH_PFC_PIN_GROUP(canfd1_data),
SH_PFC_PIN_GROUP(du_rgb666),
SH_PFC_PIN_GROUP(du_rgb888),
SH_PFC_PIN_GROUP(du_clk_in_0),
@@ -4020,8 +4019,6 @@
SH_PFC_PIN_GROUP(vin5_clk_b),
},
.automotive = {
- SH_PFC_PIN_GROUP(canfd0_data),
- SH_PFC_PIN_GROUP(canfd1_data),
SH_PFC_PIN_GROUP(drif0_ctrl_a),
SH_PFC_PIN_GROUP(drif0_data0_a),
SH_PFC_PIN_GROUP(drif0_data1_a),
@@ -4468,8 +4465,8 @@
};
static const struct {
- struct sh_pfc_function common[45];
- struct sh_pfc_function automotive[6];
+ struct sh_pfc_function common[47];
+ struct sh_pfc_function automotive[4];
} pinmux_functions = {
.common = {
SH_PFC_FUNCTION(audio_clk),
@@ -4477,6 +4474,8 @@
SH_PFC_FUNCTION(can0),
SH_PFC_FUNCTION(can1),
SH_PFC_FUNCTION(can_clk),
+ SH_PFC_FUNCTION(canfd0),
+ SH_PFC_FUNCTION(canfd1),
SH_PFC_FUNCTION(du),
SH_PFC_FUNCTION(hscif0),
SH_PFC_FUNCTION(hscif1),
@@ -4519,8 +4518,6 @@
SH_PFC_FUNCTION(vin5),
},
.automotive = {
- SH_PFC_FUNCTION(canfd0),
- SH_PFC_FUNCTION(canfd1),
SH_PFC_FUNCTION(drif0),
SH_PFC_FUNCTION(drif1),
SH_PFC_FUNCTION(drif2),
@@ -4531,7 +4528,7 @@
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) FN_##y
#define FM(x) FN_##x
- { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
+ { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -4563,9 +4560,9 @@
GP_0_3_FN, GPSR0_3,
GP_0_2_FN, GPSR0_2,
GP_0_1_FN, GPSR0_1,
- GP_0_0_FN, GPSR0_0, }
+ GP_0_0_FN, GPSR0_0, ))
},
- { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
+ { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -4597,9 +4594,9 @@
GP_1_3_FN, GPSR1_3,
GP_1_2_FN, GPSR1_2,
GP_1_1_FN, GPSR1_1,
- GP_1_0_FN, GPSR1_0, }
+ GP_1_0_FN, GPSR1_0, ))
},
- { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
+ { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -4631,9 +4628,9 @@
GP_2_3_FN, GPSR2_3,
GP_2_2_FN, GPSR2_2,
GP_2_1_FN, GPSR2_1,
- GP_2_0_FN, GPSR2_0, }
+ GP_2_0_FN, GPSR2_0, ))
},
- { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
+ { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -4665,9 +4662,9 @@
GP_3_3_FN, GPSR3_3,
GP_3_2_FN, GPSR3_2,
GP_3_1_FN, GPSR3_1,
- GP_3_0_FN, GPSR3_0, }
+ GP_3_0_FN, GPSR3_0, ))
},
- { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
+ { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -4699,9 +4696,9 @@
GP_4_3_FN, GPSR4_3,
GP_4_2_FN, GPSR4_2,
GP_4_1_FN, GPSR4_1,
- GP_4_0_FN, GPSR4_0, }
+ GP_4_0_FN, GPSR4_0, ))
},
- { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
+ { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -4733,9 +4730,9 @@
GP_5_3_FN, GPSR5_3,
GP_5_2_FN, GPSR5_2,
GP_5_1_FN, GPSR5_1,
- GP_5_0_FN, GPSR5_0, }
+ GP_5_0_FN, GPSR5_0, ))
},
- { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
+ { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -4767,14 +4764,14 @@
GP_6_3_FN, GPSR6_3,
GP_6_2_FN, GPSR6_2,
GP_6_1_FN, GPSR6_1,
- GP_6_0_FN, GPSR6_0, }
+ GP_6_0_FN, GPSR6_0, ))
},
#undef F_
#undef FM
#define F_(x, y) x,
#define FM(x) FN_##x,
- { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
+ { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
IP0_31_28
IP0_27_24
IP0_23_20
@@ -4782,9 +4779,9 @@
IP0_15_12
IP0_11_8
IP0_7_4
- IP0_3_0 }
+ IP0_3_0 ))
},
- { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
+ { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
IP1_31_28
IP1_27_24
IP1_23_20
@@ -4792,9 +4789,9 @@
IP1_15_12
IP1_11_8
IP1_7_4
- IP1_3_0 }
+ IP1_3_0 ))
},
- { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
+ { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
IP2_31_28
IP2_27_24
IP2_23_20
@@ -4802,9 +4799,9 @@
IP2_15_12
IP2_11_8
IP2_7_4
- IP2_3_0 }
+ IP2_3_0 ))
},
- { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
IP3_31_28
IP3_27_24
IP3_23_20
@@ -4812,9 +4809,9 @@
IP3_15_12
IP3_11_8
IP3_7_4
- IP3_3_0 }
+ IP3_3_0 ))
},
- { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
+ { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
IP4_31_28
IP4_27_24
IP4_23_20
@@ -4822,9 +4819,9 @@
IP4_15_12
IP4_11_8
IP4_7_4
- IP4_3_0 }
+ IP4_3_0 ))
},
- { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
+ { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
IP5_31_28
IP5_27_24
IP5_23_20
@@ -4832,9 +4829,9 @@
IP5_15_12
IP5_11_8
IP5_7_4
- IP5_3_0 }
+ IP5_3_0 ))
},
- { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
+ { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
IP6_31_28
IP6_27_24
IP6_23_20
@@ -4842,9 +4839,9 @@
IP6_15_12
IP6_11_8
IP6_7_4
- IP6_3_0 }
+ IP6_3_0 ))
},
- { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
IP7_31_28
IP7_27_24
IP7_23_20
@@ -4852,9 +4849,9 @@
IP7_15_12
IP7_11_8
IP7_7_4
- IP7_3_0 }
+ IP7_3_0 ))
},
- { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
+ { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
IP8_31_28
IP8_27_24
IP8_23_20
@@ -4862,9 +4859,9 @@
IP8_15_12
IP8_11_8
IP8_7_4
- IP8_3_0 }
+ IP8_3_0 ))
},
- { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
+ { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
IP9_31_28
IP9_27_24
IP9_23_20
@@ -4872,9 +4869,9 @@
IP9_15_12
IP9_11_8
IP9_7_4
- IP9_3_0 }
+ IP9_3_0 ))
},
- { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
+ { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
IP10_31_28
IP10_27_24
IP10_23_20
@@ -4882,9 +4879,9 @@
IP10_15_12
IP10_11_8
IP10_7_4
- IP10_3_0 }
+ IP10_3_0 ))
},
- { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
IP11_31_28
IP11_27_24
IP11_23_20
@@ -4892,9 +4889,9 @@
IP11_15_12
IP11_11_8
IP11_7_4
- IP11_3_0 }
+ IP11_3_0 ))
},
- { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
+ { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
IP12_31_28
IP12_27_24
IP12_23_20
@@ -4902,9 +4899,9 @@
IP12_15_12
IP12_11_8
IP12_7_4
- IP12_3_0 }
+ IP12_3_0 ))
},
- { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
+ { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
IP13_31_28
IP13_27_24
IP13_23_20
@@ -4912,9 +4909,9 @@
IP13_15_12
IP13_11_8
IP13_7_4
- IP13_3_0 }
+ IP13_3_0 ))
},
- { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
+ { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
IP14_31_28
IP14_27_24
IP14_23_20
@@ -4922,9 +4919,9 @@
IP14_15_12
IP14_11_8
IP14_7_4
- IP14_3_0 }
+ IP14_3_0 ))
},
- { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
IP15_31_28
IP15_27_24
IP15_23_20
@@ -4932,7 +4929,7 @@
IP15_15_12
IP15_11_8
IP15_7_4
- IP15_3_0 }
+ IP15_3_0 ))
},
#undef F_
#undef FM
@@ -4940,8 +4937,9 @@
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
- 1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1,
- 1, 1, 2, 2, 1, 1, 1, 2, 1, 1, 1, 2) {
+ GROUP(1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1, 1,
+ 1, 2, 2, 1, 1, 1, 2, 1, 1, 1, 2),
+ GROUP(
/* RESERVED 31 */
0, 0,
MOD_SEL0_30_29
@@ -4965,13 +4963,14 @@
MOD_SEL0_4
MOD_SEL0_3
MOD_SEL0_2
- MOD_SEL0_1_0 }
+ MOD_SEL0_1_0 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
- 1, 1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1,
- 1, 2, 2, 2, 1, 1, 2, 1, 4) {
- MOD_SEL1_31
- MOD_SEL1_30
+ GROUP(2, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1, 1,
+ 2, 2, 2, 1, 1, 2, 1, 4),
+ GROUP(
+ /* RESERVED 31, 30 */
+ 0, 0, 0, 0,
MOD_SEL1_29
MOD_SEL1_28
/* RESERVED 27 */
@@ -4992,17 +4991,19 @@
MOD_SEL1_6_5
MOD_SEL1_4
/* RESERVED 3, 2, 1, 0 */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ },
};
enum ioctrl_regs {
- IOCTRL30,
+ POCCTRL0,
+ TDSELCTRL,
};
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
- [IOCTRL30] = { 0xe6060380, },
+ [POCCTRL0] = { 0xe6060380, },
+ [TDSELCTRL] = { 0xe60603c0, },
{ /* sentinel */ },
};
@@ -5011,7 +5012,7 @@
{
int bit = -EINVAL;
- *pocctrl = pinmux_ioctrl_regs[IOCTRL30].reg;
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
bit = pin & 0x1f;
@@ -5127,7 +5128,7 @@
} },
{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
[0] = RCAR_GP_PIN(5, 0), /* SCK0_A */
- [1] = RCAR_GP_PIN(5, 4), /* RTS0#/TANS_A */
+ [1] = RCAR_GP_PIN(5, 4), /* RTS0#_A */
[2] = RCAR_GP_PIN(5, 3), /* CTS0#_A */
[3] = RCAR_GP_PIN(5, 2), /* TX0_A */
[4] = RCAR_GP_PIN(5, 1), /* RX0_A */
diff --git a/drivers/pinctrl/renesas/pfc-r8a77995.c b/drivers/pinctrl/renesas/pfc-r8a77995.c
index ed67858..724cf4a 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77995.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77995.c
@@ -290,7 +290,7 @@
#define IP10_23_20 FM(SSI_SDATA4_A) FM(HTX0) FM(SCL2_A) FM(CAN1_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_27_24 FM(SSI_WS4_A) FM(HRX0) FM(SDA2_A) FM(CAN1_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_31_28 FM(SCL1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP11_3_0 FM(SDA1) FM(RTS1_N_TANS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_3_0 FM(SDA1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_7_4 FM(MSIOF1_SCK) FM(AVB0_AVTP_PPS_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_11_8 FM(MSIOF1_TXD) FM(AVB0_AVTP_CAPTURE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_15_12 FM(MSIOF1_RXD) FM(AVB0_AVTP_MATCH_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -301,7 +301,7 @@
/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
#define IP12_3_0 FM(RX1_A) FM(CTS0_N) FM(TPU0TO0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP12_7_4 FM(TX1_A) FM(RTS0_N_TANS) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP12_7_4 FM(TX1_A) FM(RTS0_N) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_11_8 FM(SCK2) FM(MSIOF1_SS1) FM(TPU0TO3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_15_12 FM(TPU0TO0_A) FM(AVB0_AVTP_CAPTURE_A) FM(HCTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_19_16 FM(TPU0TO1_A) FM(AVB0_AVTP_MATCH_A) FM(HRTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -860,7 +860,7 @@
/* IPSR11 */
PINMUX_IPSR_GPSR(IP11_3_0, SDA1),
- PINMUX_IPSR_GPSR(IP11_3_0, RTS1_N_TANS),
+ PINMUX_IPSR_GPSR(IP11_3_0, RTS1_N),
PINMUX_IPSR_GPSR(IP11_7_4, MSIOF1_SCK),
PINMUX_IPSR_MSEL(IP11_7_4, AVB0_AVTP_PPS_B, SEL_ETHERAVB_1),
@@ -895,7 +895,7 @@
PINMUX_IPSR_GPSR(IP12_3_0, TPU0TO0_B),
PINMUX_IPSR_MSEL(IP12_7_4, TX1_A, SEL_SCIF1_0),
- PINMUX_IPSR_GPSR(IP12_7_4, RTS0_N_TANS),
+ PINMUX_IPSR_GPSR(IP12_7_4, RTS0_N),
PINMUX_IPSR_GPSR(IP12_7_4, TPU0TO1_B),
PINMUX_IPSR_GPSR(IP12_11_8, SCK2),
@@ -1707,7 +1707,7 @@
RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23),
};
static const unsigned int scif0_ctrl_mux[] = {
- RTS0_N_TANS_MARK, CTS0_N_MARK,
+ RTS0_N_MARK, CTS0_N_MARK,
};
/* - SCIF1 ------------------------------------------------------------------ */
static const unsigned int scif1_data_a_pins[] = {
@@ -1743,7 +1743,7 @@
RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
};
static const unsigned int scif1_ctrl_mux[] = {
- RTS1_N_TANS_MARK, CTS1_N_MARK,
+ RTS1_N_MARK, CTS1_N_MARK,
};
/* - SCIF2 ------------------------------------------------------------------ */
@@ -2377,7 +2377,7 @@
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) FN_##y
#define FM(x) FN_##x
- { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
+ { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -2409,9 +2409,9 @@
GP_0_3_FN, GPSR0_3,
GP_0_2_FN, GPSR0_2,
GP_0_1_FN, GPSR0_1,
- GP_0_0_FN, GPSR0_0, }
+ GP_0_0_FN, GPSR0_0, ))
},
- { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
+ { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
GP_1_31_FN, GPSR1_31,
GP_1_30_FN, GPSR1_30,
GP_1_29_FN, GPSR1_29,
@@ -2443,9 +2443,9 @@
GP_1_3_FN, GPSR1_3,
GP_1_2_FN, GPSR1_2,
GP_1_1_FN, GPSR1_1,
- GP_1_0_FN, GPSR1_0, }
+ GP_1_0_FN, GPSR1_0, ))
},
- { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
+ { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
GP_2_31_FN, GPSR2_31,
GP_2_30_FN, GPSR2_30,
GP_2_29_FN, GPSR2_29,
@@ -2477,9 +2477,9 @@
GP_2_3_FN, GPSR2_3,
GP_2_2_FN, GPSR2_2,
GP_2_1_FN, GPSR2_1,
- GP_2_0_FN, GPSR2_0, }
+ GP_2_0_FN, GPSR2_0, ))
},
- { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
+ { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -2511,9 +2511,9 @@
GP_3_3_FN, GPSR3_3,
GP_3_2_FN, GPSR3_2,
GP_3_1_FN, GPSR3_1,
- GP_3_0_FN, GPSR3_0, }
+ GP_3_0_FN, GPSR3_0, ))
},
- { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
+ { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
GP_4_31_FN, GPSR4_31,
GP_4_30_FN, GPSR4_30,
GP_4_29_FN, GPSR4_29,
@@ -2545,9 +2545,9 @@
GP_4_3_FN, GPSR4_3,
GP_4_2_FN, GPSR4_2,
GP_4_1_FN, GPSR4_1,
- GP_4_0_FN, GPSR4_0, }
+ GP_4_0_FN, GPSR4_0, ))
},
- { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
+ { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -2579,9 +2579,9 @@
GP_5_3_FN, GPSR5_3,
GP_5_2_FN, GPSR5_2,
GP_5_1_FN, GPSR5_1,
- GP_5_0_FN, GPSR5_0, }
+ GP_5_0_FN, GPSR5_0, ))
},
- { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
+ { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@@ -2613,14 +2613,14 @@
GP_6_3_FN, GPSR6_3,
GP_6_2_FN, GPSR6_2,
GP_6_1_FN, GPSR6_1,
- GP_6_0_FN, GPSR6_0, }
+ GP_6_0_FN, GPSR6_0, ))
},
#undef F_
#undef FM
#define F_(x, y) x,
#define FM(x) FN_##x,
- { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
+ { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
IP0_31_28
IP0_27_24
IP0_23_20
@@ -2628,9 +2628,9 @@
IP0_15_12
IP0_11_8
IP0_7_4
- IP0_3_0 }
+ IP0_3_0 ))
},
- { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
+ { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
IP1_31_28
IP1_27_24
IP1_23_20
@@ -2638,9 +2638,9 @@
IP1_15_12
IP1_11_8
IP1_7_4
- IP1_3_0 }
+ IP1_3_0 ))
},
- { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
+ { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
IP2_31_28
IP2_27_24
IP2_23_20
@@ -2648,9 +2648,9 @@
IP2_15_12
IP2_11_8
IP2_7_4
- IP2_3_0 }
+ IP2_3_0 ))
},
- { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
IP3_31_28
IP3_27_24
IP3_23_20
@@ -2658,9 +2658,9 @@
IP3_15_12
IP3_11_8
IP3_7_4
- IP3_3_0 }
+ IP3_3_0 ))
},
- { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
+ { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
IP4_31_28
IP4_27_24
IP4_23_20
@@ -2668,9 +2668,9 @@
IP4_15_12
IP4_11_8
IP4_7_4
- IP4_3_0 }
+ IP4_3_0 ))
},
- { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
+ { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
IP5_31_28
IP5_27_24
IP5_23_20
@@ -2678,9 +2678,9 @@
IP5_15_12
IP5_11_8
IP5_7_4
- IP5_3_0 }
+ IP5_3_0 ))
},
- { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
+ { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
IP6_31_28
IP6_27_24
IP6_23_20
@@ -2688,9 +2688,9 @@
IP6_15_12
IP6_11_8
IP6_7_4
- IP6_3_0 }
+ IP6_3_0 ))
},
- { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
IP7_31_28
IP7_27_24
IP7_23_20
@@ -2698,9 +2698,9 @@
IP7_15_12
IP7_11_8
IP7_7_4
- IP7_3_0 }
+ IP7_3_0 ))
},
- { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
+ { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
IP8_31_28
IP8_27_24
IP8_23_20
@@ -2708,9 +2708,9 @@
IP8_15_12
IP8_11_8
IP8_7_4
- IP8_3_0 }
+ IP8_3_0 ))
},
- { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
+ { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
IP9_31_28
IP9_27_24
IP9_23_20
@@ -2718,9 +2718,9 @@
IP9_15_12
IP9_11_8
IP9_7_4
- IP9_3_0 }
+ IP9_3_0 ))
},
- { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
+ { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
IP10_31_28
IP10_27_24
IP10_23_20
@@ -2728,9 +2728,9 @@
IP10_15_12
IP10_11_8
IP10_7_4
- IP10_3_0 }
+ IP10_3_0 ))
},
- { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
+ { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
IP11_31_28
IP11_27_24
IP11_23_20
@@ -2738,9 +2738,9 @@
IP11_15_12
IP11_11_8
IP11_7_4
- IP11_3_0 }
+ IP11_3_0 ))
},
- { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
+ { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
IP12_31_28
IP12_27_24
IP12_23_20
@@ -2748,9 +2748,9 @@
IP12_15_12
IP12_11_8
IP12_7_4
- IP12_3_0 }
+ IP12_3_0 ))
},
- { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
+ { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
/* IP13_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP13_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP13_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -2758,7 +2758,7 @@
/* IP13_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP13_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
IP13_7_4
- IP13_3_0 }
+ IP13_3_0 ))
},
#undef F_
#undef FM
@@ -2766,8 +2766,9 @@
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
- 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 1,
- 1, 1, 1, 1, 1, 1, 4, 1, 1, 1, 1, 1, 1) {
+ GROUP(1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 1,
+ 1, 1, 1, 1, 1, 1, 4, 1, 1, 1, 1, 1, 1),
+ GROUP(
/* RESERVED 31 */
0, 0,
MOD_SEL0_30
@@ -2795,11 +2796,11 @@
MOD_SEL0_3
MOD_SEL0_2
MOD_SEL0_1
- MOD_SEL0_0 }
+ MOD_SEL0_0 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
- 1, 1, 1, 1, 1, 1, 2, 4, 4,
- 4, 4, 4, 4) {
+ GROUP(1, 1, 1, 1, 1, 1, 2, 4, 4, 4, 4, 4, 4),
+ GROUP(
MOD_SEL1_31
MOD_SEL1_30
MOD_SEL1_29
@@ -2819,7 +2820,7 @@
/* RESERVED 7, 6, 5, 4 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED 3, 2, 1, 0 */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ },
};
@@ -2836,6 +2837,15 @@
return bit;
}
+enum ioctrl_regs {
+ TDSELCTRL,
+};
+
+static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
+ [TDSELCTRL] = { 0xe60603c0, },
+ { /* sentinel */ },
+};
+
static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = {
.pin_to_pocctrl = r8a77995_pin_to_pocctrl,
};
@@ -2855,6 +2865,7 @@
.nr_functions = ARRAY_SIZE(pinmux_functions),
.cfg_regs = pinmux_config_regs,
+ .ioctrl_regs = pinmux_ioctrl_regs,
.pinmux_data = pinmux_data,
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c
index d1271da..5ec560e 100644
--- a/drivers/pinctrl/renesas/pfc.c
+++ b/drivers/pinctrl/renesas/pfc.c
@@ -30,6 +30,7 @@
SH_PFC_R8A7796,
SH_PFC_R8A77965,
SH_PFC_R8A77970,
+ SH_PFC_R8A77980,
SH_PFC_R8A77990,
SH_PFC_R8A77995,
};
@@ -469,7 +470,7 @@
const struct sh_pfc_pin *pin = NULL;
int i, ret, idx;
- for (i = 1; i < pfc->info->nr_pins; i++) {
+ for (i = 0; i < pfc->info->nr_pins; i++) {
if (priv->pfc.info->pins[i].pin != pin_selector)
continue;
@@ -505,7 +506,7 @@
const struct sh_pfc_pin *pin = NULL;
int i, idx;
- for (i = 1; i < pfc->info->nr_pins; i++) {
+ for (i = 0; i < pfc->info->nr_pins; i++) {
if (priv->pfc.info->pins[i].pin != pin_selector)
continue;
@@ -856,6 +857,10 @@
if (model == SH_PFC_R8A77970)
priv->pfc.info = &r8a77970_pinmux_info;
#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A77980
+ if (model == SH_PFC_R8A77980)
+ priv->pfc.info = &r8a77980_pinmux_info;
+#endif
#ifdef CONFIG_PINCTRL_PFC_R8A77990
if (model == SH_PFC_R8A77990)
priv->pfc.info = &r8a77990_pinmux_info;
@@ -927,6 +932,12 @@
.data = SH_PFC_R8A77970,
},
#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A77980
+ {
+ .compatible = "renesas,pfc-r8a77980",
+ .data = SH_PFC_R8A77980,
+ },
+#endif
#ifdef CONFIG_PINCTRL_PFC_R8A77990
{
.compatible = "renesas,pfc-r8a77990",
diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h
index 6629e1f..1cfb881 100644
--- a/drivers/pinctrl/renesas/sh_pfc.h
+++ b/drivers/pinctrl/renesas/sh_pfc.h
@@ -41,7 +41,8 @@
.name = #alias, \
.pins = n##_pins, \
.mux = n##_mux, \
- .nr_pins = ARRAY_SIZE(n##_pins), \
+ .nr_pins = ARRAY_SIZE(n##_pins) + \
+ BUILD_BUG_ON_ZERO(sizeof(n##_pins) != sizeof(n##_mux)), \
}
#define SH_PFC_PIN_GROUP(n) SH_PFC_PIN_GROUP_ALIAS(n, n)
@@ -110,40 +111,54 @@
struct pinmux_cfg_reg {
u32 reg;
u8 reg_width, field_width;
+#ifdef DEBUG
+ u16 nr_enum_ids; /* for variable width regs only */
+#define SET_NR_ENUM_IDS(n) .nr_enum_ids = n,
+#else
+#define SET_NR_ENUM_IDS(n)
+#endif
const u16 *enum_ids;
const u8 *var_field_width;
};
+#define GROUP(...) __VA_ARGS__
+
/*
* Describe a config register consisting of several fields of the same width
* - name: Register name (unused, for documentation purposes only)
* - r: Physical register address
* - r_width: Width of the register (in bits)
* - f_width: Width of the fixed-width register fields (in bits)
- * This macro must be followed by initialization data: For each register field
- * (from left to right, i.e. MSB to LSB), 2^f_width enum IDs must be specified,
- * one for each possible combination of the register field bit values.
+ * - ids: For each register field (from left to right, i.e. MSB to LSB),
+ * 2^f_width enum IDs must be specified, one for each possible
+ * combination of the register field bit values, all wrapped using
+ * the GROUP() macro.
*/
-#define PINMUX_CFG_REG(name, r, r_width, f_width) \
- .reg = r, .reg_width = r_width, .field_width = f_width, \
- .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)])
+#define PINMUX_CFG_REG(name, r, r_width, f_width, ids) \
+ .reg = r, .reg_width = r_width, \
+ .field_width = f_width + BUILD_BUG_ON_ZERO(r_width % f_width) + \
+ BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \
+ (r_width / f_width) * (1 << f_width)), \
+ .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)]) \
+ { ids }
/*
* Describe a config register consisting of several fields of different widths
* - name: Register name (unused, for documentation purposes only)
* - r: Physical register address
* - r_width: Width of the register (in bits)
- * - var_fw0, var_fwn...: List of widths of the register fields (in bits),
- * From left to right (i.e. MSB to LSB)
- * This macro must be followed by initialization data: For each register field
- * (from left to right, i.e. MSB to LSB), 2^var_fwi enum IDs must be specified,
- * one for each possible combination of the register field bit values.
+ * - f_widths: List of widths of the register fields (in bits), from left
+ * to right (i.e. MSB to LSB), wrapped using the GROUP() macro.
+ * - ids: For each register field (from left to right, i.e. MSB to LSB),
+ * 2^f_widths[i] enum IDs must be specified, one for each possible
+ * combination of the register field bit values, all wrapped using
+ * the GROUP() macro.
*/
-#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
- .reg = r, .reg_width = r_width, \
- .var_field_width = (const u8 [r_width]) \
- { var_fw0, var_fwn, 0 }, \
- .enum_ids = (const u16 [])
+#define PINMUX_CFG_REG_VAR(name, r, r_width, f_widths, ids) \
+ .reg = r, .reg_width = r_width, \
+ .var_field_width = (const u8 []) { f_widths, 0 }, \
+ SET_NR_ENUM_IDS(sizeof((const u16 []) { ids }) / sizeof(u16)) \
+ .enum_ids = (const u16 []) { ids }
struct pinmux_drive_reg_field {
u16 pin;
@@ -186,12 +201,14 @@
* - name: Register name (unused, for documentation purposes only)
* - r: Physical register address
* - r_width: Width of the register (in bits)
- * This macro must be followed by initialization data: For each register bit
- * (from left to right, i.e. MSB to LSB), one enum ID must be specified.
+ * - ids: For each register bit (from left to right, i.e. MSB to LSB), one
+ * enum ID must be specified, all wrapped using the GROUP() macro.
*/
-#define PINMUX_DATA_REG(name, r, r_width) \
- .reg = r, .reg_width = r_width, \
- .enum_ids = (const u16 [r_width]) \
+#define PINMUX_DATA_REG(name, r, r_width, ids) \
+ .reg = r, .reg_width = r_width + \
+ BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \
+ r_width), \
+ .enum_ids = (const u16 [r_width]) { ids }
struct pinmux_irq {
const short *gpios;
@@ -285,6 +302,7 @@
extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
extern const struct sh_pfc_soc_info r8a77965_pinmux_info;
extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
+extern const struct sh_pfc_soc_info r8a77980_pinmux_info;
extern const struct sh_pfc_soc_info r8a77990_pinmux_info;
extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
@@ -371,8 +389,8 @@
/*
* Describe a pinmux configuration in which a pin is physically multiplexed
* with other pins.
- * - ipsr: IPSR field
- * - fn: Function name, also referring to the IPSR field
+ * - ipsr: IPSR field (unused, for documentation purposes only)
+ * - fn: Function name
* - psel: Physical multiplexing selector
*/
#define PINMUX_IPSR_PHYS(ipsr, fn, psel) \
@@ -632,7 +650,9 @@
*/
#define PORTCR(nr, reg) \
{ \
- PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, 2, 2, 1, 3) {\
+ PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, \
+ GROUP(2, 2, 1, 3), \
+ GROUP( \
/* PULMD[1:0], handled by .set_bias() */ \
0, 0, 0, 0, \
/* IE and OE */ \
@@ -644,7 +664,7 @@
PORT##nr##_FN2, PORT##nr##_FN3, \
PORT##nr##_FN4, PORT##nr##_FN5, \
PORT##nr##_FN6, PORT##nr##_FN7 \
- } \
+ )) \
}
/*
diff --git a/drivers/power/domain/ti-sci-power-domain.c b/drivers/power/domain/ti-sci-power-domain.c
index aafde62..4c4351d 100644
--- a/drivers/power/domain/ti-sci-power-domain.c
+++ b/drivers/power/domain/ti-sci-power-domain.c
@@ -13,6 +13,7 @@
#include <errno.h>
#include <power-domain-uclass.h>
#include <linux/soc/ti/ti_sci_protocol.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
/**
* struct ti_sci_power_domain_data - pm domain controller information structure
@@ -56,14 +57,19 @@
struct ti_sci_power_domain_data *data = dev_get_priv(pd->dev);
const struct ti_sci_handle *sci = data->sci;
const struct ti_sci_dev_ops *dops = &sci->ops.dev_ops;
+ u8 flags = (uintptr_t)pd->priv;
int ret;
debug("%s(pd=%p)\n", __func__, pd);
- ret = dops->get_device(sci, pd->id);
+ if (flags & TI_SCI_PD_EXCLUSIVE)
+ ret = dops->get_device_exclusive(sci, pd->id);
+ else
+ ret = dops->get_device(sci, pd->id);
+
if (ret)
- dev_err(power_domain->dev, "%s: get_device failed (%d)\n",
- __func__, ret);
+ dev_err(pd->dev, "%s: get_device(%lu) failed (%d)\n",
+ __func__, pd->id, ret);
return ret;
}
@@ -79,12 +85,34 @@
ret = dops->put_device(sci, pd->id);
if (ret)
- dev_err(power_domain->dev, "%s: put_device failed (%d)\n",
- __func__, ret);
+ dev_err(pd->dev, "%s: put_device(%lu) failed (%d)\n",
+ __func__, pd->id, ret);
return ret;
}
+static int ti_sci_power_domain_of_xlate(struct power_domain *pd,
+ struct ofnode_phandle_args *args)
+{
+ u8 flags;
+
+ debug("%s(power_domain=%p)\n", __func__, pd);
+
+ if (args->args_count < 1) {
+ debug("Invalid args_count: %d\n", args->args_count);
+ return -EINVAL;
+ }
+
+ pd->id = args->args[0];
+ /* By default request for device exclusive */
+ flags = TI_SCI_PD_EXCLUSIVE;
+ if (args->args_count == 2)
+ flags = args->args[1] & TI_SCI_PD_EXCLUSIVE;
+ pd->priv = (void *)(uintptr_t)flags;
+
+ return 0;
+}
+
static const struct udevice_id ti_sci_power_domain_of_match[] = {
{ .compatible = "ti,sci-pm-domain" },
{ /* sentinel */ }
@@ -95,6 +123,7 @@
.free = ti_sci_power_domain_free,
.on = ti_sci_power_domain_on,
.off = ti_sci_power_domain_off,
+ .of_xlate = ti_sci_power_domain_of_xlate,
};
U_BOOT_DRIVER(ti_sci_pm_domains) = {
diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index 450935f..586772f 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -241,7 +241,29 @@
config PMIC_STPMIC1
bool "Enable support for STMicroelectronics STPMIC1 PMIC"
depends on DM_PMIC && DM_I2C
+ select SYSRESET_CMD_POWEROFF if CMD_POWEROFF && !ARM_PSCI_FW
---help---
The STPMIC1 PMIC provides 4 BUCKs, 6 LDOs, 1 VREF and 2 power switches.
It is accessed via an I2C interface. The device is used with STM32MP1
SoCs. This driver implements register read/write operations.
+
+config SPL_PMIC_PALMAS
+ bool "Enable driver for Texas Instruments PALMAS PMIC"
+ depends on DM_PMIC
+ help
+ The PALMAS is a PMIC containing several LDOs, SMPS.
+ This driver binds the pmic children in SPL.
+
+config SPL_PMIC_LP873X
+ bool "Enable driver for Texas Instruments LP873X PMIC"
+ depends on DM_PMIC
+ help
+ The LP873X is a PMIC containing couple of LDOs and couple of SMPS.
+ This driver binds the pmic children in SPL.
+
+config SPL_PMIC_LP87565
+ bool "Enable driver for Texas Instruments LP87565 PMIC"
+ depends on DM_PMIC
+ help
+ The LP87565 is a PMIC containing a bunch of SMPS.
+ This driver binds the pmic children in SPL.
diff --git a/drivers/power/pmic/bd71837.c b/drivers/power/pmic/bd71837.c
index 24d9f7f..e292d42 100644
--- a/drivers/power/pmic/bd71837.c
+++ b/drivers/power/pmic/bd71837.c
@@ -3,6 +3,8 @@
* Copyright 2018 NXP
*/
+#define DEBUG
+
#include <common.h>
#include <errno.h>
#include <dm.h>
@@ -15,15 +17,15 @@
static const struct pmic_child_info pmic_children_info[] = {
/* buck */
- { .prefix = "b", .driver = BD71837_REGULATOR_DRIVER},
+ { .prefix = "b", .driver = BD718XX_REGULATOR_DRIVER},
/* ldo */
- { .prefix = "l", .driver = BD71837_REGULATOR_DRIVER},
+ { .prefix = "l", .driver = BD718XX_REGULATOR_DRIVER},
{ },
};
static int bd71837_reg_count(struct udevice *dev)
{
- return BD71837_REG_NUM;
+ return BD718XX_MAX_REGISTER - 1;
}
static int bd71837_write(struct udevice *dev, uint reg, const uint8_t *buff,
@@ -54,7 +56,7 @@
regulators_node = dev_read_subnode(dev, "regulators");
if (!ofnode_valid(regulators_node)) {
- debug("%s: %s regulators subnode not found!", __func__,
+ debug("%s: %s regulators subnode not found!\n", __func__,
dev->name);
return -ENXIO;
}
@@ -69,6 +71,24 @@
return 0;
}
+static int bd718x7_probe(struct udevice *dev)
+{
+ int ret;
+ uint8_t mask = BD718XX_REGLOCK_PWRSEQ | BD718XX_REGLOCK_VREG;
+
+ /* Unlock the PMIC regulator control before probing the children */
+ ret = pmic_clrsetbits(dev, BD718XX_REGLOCK, mask, 0);
+ if (ret) {
+ debug("%s: %s Failed to unlock regulator control\n", __func__,
+ dev->name);
+ return ret;
+ }
+ debug("%s: '%s' - BD718x7 PMIC registers unlocked\n", __func__,
+ dev->name);
+
+ return 0;
+}
+
static struct dm_pmic_ops bd71837_ops = {
.reg_count = bd71837_reg_count,
.read = bd71837_read,
@@ -76,7 +96,8 @@
};
static const struct udevice_id bd71837_ids[] = {
- { .compatible = "rohm,bd71837", .data = 0x4b, },
+ { .compatible = "rohm,bd71837", .data = ROHM_CHIP_TYPE_BD71837, },
+ { .compatible = "rohm,bd71847", .data = ROHM_CHIP_TYPE_BD71847, },
{ }
};
@@ -85,5 +106,6 @@
.id = UCLASS_PMIC,
.of_match = bd71837_ids,
.bind = bd71837_bind,
+ .probe = bd718x7_probe,
.ops = &bd71837_ops,
};
diff --git a/drivers/power/pmic/stpmic1.c b/drivers/power/pmic/stpmic1.c
index 65296c5..de31934 100644
--- a/drivers/power/pmic/stpmic1.c
+++ b/drivers/power/pmic/stpmic1.c
@@ -7,6 +7,7 @@
#include <dm.h>
#include <errno.h>
#include <i2c.h>
+#include <misc.h>
#include <sysreset.h>
#include <dm/device.h>
#include <dm/lists.h>
@@ -69,6 +70,7 @@
static int stpmic1_bind(struct udevice *dev)
{
+ int ret;
#if CONFIG_IS_ENABLED(DM_REGULATOR)
ofnode regulators_node;
int children;
@@ -86,6 +88,13 @@
dev_dbg(dev, "no child found\n");
#endif /* DM_REGULATOR */
+ if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
+ ret = device_bind_driver(dev, "stpmic1-nvm",
+ "stpmic1-nvm", NULL);
+ if (ret)
+ return ret;
+ }
+
if (CONFIG_IS_ENABLED(SYSRESET))
return device_bind_driver(dev, "stpmic1-sysreset",
"stpmic1-sysreset", NULL);
@@ -113,32 +122,38 @@
};
#ifndef CONFIG_SPL_BUILD
-static int stpmic1_nvm_rw(u8 addr, u8 *buf, int buf_len, enum pmic_nvm_op op)
+static int stpmic1_nvm_rw(struct udevice *dev, u8 addr, u8 *buf, int buf_len,
+ enum pmic_nvm_op op)
{
- struct udevice *dev;
unsigned long timeout;
u8 cmd = STPMIC1_NVM_CMD_READ;
- int ret;
-
- ret = uclass_get_device_by_driver(UCLASS_PMIC,
- DM_GET_DRIVER(pmic_stpmic1), &dev);
- if (ret)
- /* No PMIC on power discrete board */
- return -EOPNOTSUPP;
+ int ret, len = buf_len;
if (addr < STPMIC1_NVM_START_ADDRESS)
return -EACCES;
+ if (addr + buf_len > STPMIC1_NVM_START_ADDRESS + STPMIC1_NVM_SIZE)
+ len = STPMIC1_NVM_START_ADDRESS + STPMIC1_NVM_SIZE - addr;
- if (op == SHADOW_READ)
- return pmic_read(dev, addr, buf, buf_len);
+ if (op == SHADOW_READ) {
+ ret = pmic_read(dev, addr, buf, len);
+ if (ret < 0)
+ return ret;
+ else
+ return len;
+ }
- if (op == SHADOW_WRITE)
- return pmic_write(dev, addr, buf, buf_len);
+ if (op == SHADOW_WRITE) {
+ ret = pmic_write(dev, addr, buf, len);
+ if (ret < 0)
+ return ret;
+ else
+ return len;
+ }
if (op == NVM_WRITE) {
cmd = STPMIC1_NVM_CMD_PROGRAM;
- ret = pmic_write(dev, addr, buf, buf_len);
+ ret = pmic_write(dev, addr, buf, len);
if (ret < 0)
return ret;
}
@@ -168,75 +183,72 @@
return -ETIMEDOUT;
if (op == NVM_READ) {
- ret = pmic_read(dev, addr, buf, buf_len);
+ ret = pmic_read(dev, addr, buf, len);
if (ret < 0)
return ret;
}
- return 0;
+ return len;
}
-int stpmic1_shadow_read_byte(u8 addr, u8 *buf)
+static int stpmic1_nvm_read(struct udevice *dev, int offset,
+ void *buf, int size)
{
- return stpmic1_nvm_rw(addr, buf, 1, SHADOW_READ);
+ enum pmic_nvm_op op = NVM_READ;
+
+ if (offset < 0) {
+ op = SHADOW_READ;
+ offset = -offset;
+ }
+
+ return stpmic1_nvm_rw(dev->parent, offset, buf, size, op);
}
-int stpmic1_shadow_write_byte(u8 addr, u8 *buf)
+static int stpmic1_nvm_write(struct udevice *dev, int offset,
+ const void *buf, int size)
{
- return stpmic1_nvm_rw(addr, buf, 1, SHADOW_WRITE);
+ enum pmic_nvm_op op = NVM_WRITE;
+
+ if (offset < 0) {
+ op = SHADOW_WRITE;
+ offset = -offset;
+ }
+
+ return stpmic1_nvm_rw(dev->parent, offset, (void *)buf, size, op);
}
-int stpmic1_nvm_read_byte(u8 addr, u8 *buf)
-{
- return stpmic1_nvm_rw(addr, buf, 1, NVM_READ);
-}
+static const struct misc_ops stpmic1_nvm_ops = {
+ .read = stpmic1_nvm_read,
+ .write = stpmic1_nvm_write,
+};
-int stpmic1_nvm_write_byte(u8 addr, u8 *buf)
-{
- return stpmic1_nvm_rw(addr, buf, 1, NVM_WRITE);
-}
-
-int stpmic1_nvm_read_all(u8 *buf, int buf_len)
-{
- if (buf_len != STPMIC1_NVM_SIZE)
- return -EINVAL;
-
- return stpmic1_nvm_rw(STPMIC1_NVM_START_ADDRESS,
- buf, buf_len, NVM_READ);
-}
-
-int stpmic1_nvm_write_all(u8 *buf, int buf_len)
-{
- if (buf_len != STPMIC1_NVM_SIZE)
- return -EINVAL;
-
- return stpmic1_nvm_rw(STPMIC1_NVM_START_ADDRESS,
- buf, buf_len, NVM_WRITE);
-}
+U_BOOT_DRIVER(stpmic1_nvm) = {
+ .name = "stpmic1-nvm",
+ .id = UCLASS_MISC,
+ .ops = &stpmic1_nvm_ops,
+};
#endif /* CONFIG_SPL_BUILD */
#ifdef CONFIG_SYSRESET
static int stpmic1_sysreset_request(struct udevice *dev, enum sysreset_t type)
{
- struct udevice *pmic_dev;
+ struct udevice *pmic_dev = dev->parent;
int ret;
- if (type != SYSRESET_POWER)
+ if (type != SYSRESET_POWER && type != SYSRESET_POWER_OFF)
return -EPROTONOSUPPORT;
- ret = uclass_get_device_by_driver(UCLASS_PMIC,
- DM_GET_DRIVER(pmic_stpmic1),
- &pmic_dev);
-
- if (ret)
- return -EOPNOTSUPP;
-
ret = pmic_reg_read(pmic_dev, STPMIC1_MAIN_CR);
if (ret < 0)
return ret;
- ret = pmic_reg_write(pmic_dev, STPMIC1_MAIN_CR,
- ret | STPMIC1_SWOFF | STPMIC1_RREQ_EN);
+ ret |= STPMIC1_SWOFF;
+ ret &= ~STPMIC1_RREQ_EN;
+ /* request Power Cycle */
+ if (type == SYSRESET_POWER)
+ ret |= STPMIC1_RREQ_EN;
+
+ ret = pmic_reg_write(pmic_dev, STPMIC1_MAIN_CR, ret);
if (ret < 0)
return ret;
diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig
index 72dfc48..9aa00fa 100644
--- a/drivers/power/regulator/Kconfig
+++ b/drivers/power/regulator/Kconfig
@@ -43,6 +43,23 @@
but does not yet support change voltages. Currently this must be
done using direct register writes to the PMIC.
+config DM_REGULATOR_BD71837
+ bool "Enable Driver Model for ROHM BD71837/BD71847 regulators"
+ depends on DM_REGULATOR && DM_PMIC_BD71837
+ help
+ This config enables implementation of driver-model regulator uclass
+ features for regulators on ROHM BD71837 and BD71847 PMICs.
+ BD71837 contains 8 bucks and 7 LDOS. BD71847 is reduced version
+ containing 6 bucks and 6 LDOs. The driver implements get/set api for
+ value and enable.
+
+config SPL_DM_REGULATOR_BD71837
+ bool "Enable Driver Model for ROHM BD71837/BD71847 regulators in SPL"
+ depends on DM_REGULATOR_BD71837
+ help
+ This config enables implementation of driver-model regulator uclass
+ features for regulators on ROHM BD71837 and BD71847 in SPL.
+
config DM_REGULATOR_PFUZE100
bool "Enable Driver Model for REGULATOR PFUZE100"
depends on DM_REGULATOR && DM_PMIC_PFUZE100
@@ -92,9 +109,18 @@
or switching the mode is not supported by this driver (at
this time).
+config DM_REGULATOR_COMMON
+ bool
+ depends on DM_REGULATOR
+
+config SPL_DM_REGULATOR_COMMON
+ bool
+ depends on DM_REGULATOR
+
config DM_REGULATOR_FIXED
bool "Enable Driver Model for REGULATOR Fixed value"
depends on DM_REGULATOR
+ select DM_REGULATOR_COMMON
---help---
This config enables implementation of driver-model regulator uclass
features for fixed value regulators. The driver implements get/set api
@@ -103,6 +129,7 @@
config SPL_DM_REGULATOR_FIXED
bool "Enable Driver Model for REGULATOR Fixed value in SPL"
depends on DM_REGULATOR_FIXED
+ select SPL_DM_REGULATOR_COMMON
---help---
This config enables implementation of driver-model regulator uclass
features for fixed value regulators in SPL.
@@ -110,6 +137,7 @@
config DM_REGULATOR_GPIO
bool "Enable Driver Model for GPIO REGULATOR"
depends on DM_REGULATOR && DM_GPIO
+ select DM_REGULATOR_COMMON
---help---
This config enables implementation of driver-model regulator uclass
features for gpio regulators. The driver implements get/set for
@@ -118,6 +146,7 @@
config SPL_DM_REGULATOR_GPIO
bool "Enable Driver Model for GPIO REGULATOR in SPL"
depends on DM_REGULATOR_GPIO && SPL_GPIO_SUPPORT
+ select SPL_DM_REGULATOR_COMMON
---help---
This config enables implementation of driver-model regulator uclass
features for gpio regulators in SPL.
@@ -258,3 +287,29 @@
depends on SPL_DM_REGULATOR && PMIC_STPMIC1
help
Enable support for the regulator functions of the STPMIC1 PMIC in SPL.
+
+config SPL_DM_REGULATOR_PALMAS
+ bool "Enable driver for PALMAS PMIC regulators"
+ depends on SPL_PMIC_PALMAS
+ help
+ This enables implementation of driver-model regulator uclass
+ features for REGULATOR PALMAS and the family of PALMAS PMICs.
+ The driver implements get/set api for: value and enable in SPL.
+
+config SPL_DM_REGULATOR_LP87565
+ bool "Enable driver for LP87565 PMIC regulators"
+ depends on SPL_PMIC_LP87565
+ help
+ This enables implementation of driver-model regulator uclass
+ features for REGULATOR LP87565 and the family of LP87565 PMICs.
+ LP87565 series of PMICs have 4 single phase BUCKs that can also
+ be configured in multi phase modes. The driver implements
+ get/set api for value and enable in SPL.
+
+config SPL_DM_REGULATOR_LP873X
+ bool "Enable driver for LP873X PMIC regulators"
+ depends on SPL_PMIC_LP873X
+ help
+ This enables implementation of driver-model regulator uclass
+ features for REGULATOR LP873X and the family of LP873X PMICs.
+ The driver implements get/set api for: value and enable in SPL.
diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile
index 8c1506c..6a3d4bb 100644
--- a/drivers/power/regulator/Makefile
+++ b/drivers/power/regulator/Makefile
@@ -9,8 +9,10 @@
obj-$(CONFIG_REGULATOR_AS3722) += as3722_regulator.o
obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o
obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o
+obj-$(CONFIG_$(SPL_)DM_REGULATOR_BD71837) += bd71837.o
obj-$(CONFIG_$(SPL_)REGULATOR_PWM) += pwm_regulator.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_FAN53555) += fan53555.o
+obj-$(CONFIG_$(SPL_)DM_REGULATOR_COMMON) += regulator_common.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_FIXED) += fixed.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_GPIO) += gpio-regulator.o
obj-$(CONFIG_REGULATOR_RK8XX) += rk8xx.o
diff --git a/drivers/power/regulator/bd71837.c b/drivers/power/regulator/bd71837.c
new file mode 100644
index 0000000..575429a
--- /dev/null
+++ b/drivers/power/regulator/bd71837.c
@@ -0,0 +1,468 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2019 ROHM Semiconductors
+ *
+ * ROHM BD71837 regulator driver
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <power/bd71837.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+
+#define HW_STATE_CONTROL 0
+#define DEBUG
+
+/**
+ * struct bd71837_vrange - describe linear range of voltages
+ *
+ * @min_volt: smallest voltage in range
+ * @step: how much voltage changes at each selector step
+ * @min_sel: smallest selector in the range
+ * @max_sel: maximum selector in the range
+ * @rangeval: register value used to select this range if selectible
+ * ranges are supported
+ */
+struct bd71837_vrange {
+ unsigned int min_volt;
+ unsigned int step;
+ u8 min_sel;
+ u8 max_sel;
+ u8 rangeval;
+};
+
+/**
+ * struct bd71837_platdata - describe regulator control registers
+ *
+ * @name: name of the regulator. Used for matching the dt-entry
+ * @enable_reg: register address used to enable/disable regulator
+ * @enablemask: register mask used to enable/disable regulator
+ * @volt_reg: register address used to configure regulator voltage
+ * @volt_mask: register mask used to configure regulator voltage
+ * @ranges: pointer to ranges of regulator voltages and matching register
+ * values
+ * @numranges: number of voltage ranges pointed by ranges
+ * @rangemask: mask for selecting used ranges if multiple ranges are supported
+ * @sel_mask: bit to toggle in order to transfer the register control to SW
+ * @dvs: whether the voltage can be changed when regulator is enabled
+ */
+struct bd71837_platdata {
+ const char *name;
+ u8 enable_reg;
+ u8 enablemask;
+ u8 volt_reg;
+ u8 volt_mask;
+ struct bd71837_vrange *ranges;
+ unsigned int numranges;
+ u8 rangemask;
+ u8 sel_mask;
+ bool dvs;
+};
+
+#define BD_RANGE(_min, _vstep, _sel_low, _sel_hi, _range_sel) \
+{ \
+ .min_volt = (_min), .step = (_vstep), .min_sel = (_sel_low), \
+ .max_sel = (_sel_hi), .rangeval = (_range_sel) \
+}
+
+#define BD_DATA(_name, enreg, enmask, vreg, vmask, _range, rmask, _dvs, sel) \
+{ \
+ .name = (_name), .enable_reg = (enreg), .enablemask = (enmask), \
+ .volt_reg = (vreg), .volt_mask = (vmask), .ranges = (_range), \
+ .numranges = ARRAY_SIZE(_range), .rangemask = (rmask), .dvs = (_dvs), \
+ .sel_mask = (sel) \
+}
+
+static struct bd71837_vrange dvs_buck_vranges[] = {
+ BD_RANGE(700000, 10000, 0, 0x3c, 0),
+ BD_RANGE(1300000, 0, 0x3d, 0x3f, 0),
+};
+
+static struct bd71837_vrange bd71847_buck3_vranges[] = {
+ BD_RANGE(700000, 100000, 0x00, 0x03, 0),
+ BD_RANGE(1050000, 50000, 0x04, 0x05, 0),
+ BD_RANGE(1200000, 150000, 0x06, 0x07, 0),
+ BD_RANGE(550000, 50000, 0x0, 0x7, 0x40),
+ BD_RANGE(675000, 100000, 0x0, 0x3, 0x80),
+ BD_RANGE(1025000, 50000, 0x4, 0x5, 0x80),
+ BD_RANGE(1175000, 150000, 0x6, 0x7, 0x80),
+};
+
+static struct bd71837_vrange bd71847_buck4_vranges[] = {
+ BD_RANGE(3000000, 100000, 0x00, 0x03, 0),
+ BD_RANGE(2600000, 100000, 0x00, 0x03, 40),
+};
+
+static struct bd71837_vrange bd71837_buck5_vranges[] = {
+ BD_RANGE(700000, 100000, 0, 0x3, 0),
+ BD_RANGE(1050000, 50000, 0x04, 0x05, 0),
+ BD_RANGE(1200000, 150000, 0x06, 0x07, 0),
+ BD_RANGE(675000, 100000, 0x0, 0x3, 0x80),
+ BD_RANGE(1025000, 50000, 0x04, 0x05, 0x80),
+ BD_RANGE(1175000, 150000, 0x06, 0x07, 0x80),
+};
+
+static struct bd71837_vrange bd71837_buck6_vranges[] = {
+ BD_RANGE(3000000, 100000, 0x00, 0x03, 0),
+};
+
+static struct bd71837_vrange nodvs_buck3_vranges[] = {
+ BD_RANGE(1605000, 90000, 0, 1, 0),
+ BD_RANGE(1755000, 45000, 2, 4, 0),
+ BD_RANGE(1905000, 45000, 5, 7, 0),
+};
+
+static struct bd71837_vrange nodvs_buck4_vranges[] = {
+ BD_RANGE(800000, 10000, 0x00, 0x3C, 0),
+};
+
+static struct bd71837_vrange ldo1_vranges[] = {
+ BD_RANGE(3000000, 100000, 0x00, 0x03, 0),
+ BD_RANGE(1600000, 100000, 0x00, 0x03, 0x20),
+};
+
+static struct bd71837_vrange ldo2_vranges[] = {
+ BD_RANGE(900000, 0, 0, 0, 0),
+ BD_RANGE(800000, 0, 1, 1, 0),
+};
+
+static struct bd71837_vrange ldo3_vranges[] = {
+ BD_RANGE(1800000, 100000, 0x00, 0x0f, 0),
+};
+
+static struct bd71837_vrange ldo4_vranges[] = {
+ BD_RANGE(900000, 100000, 0x00, 0x09, 0),
+};
+
+static struct bd71837_vrange bd71837_ldo5_vranges[] = {
+ BD_RANGE(1800000, 100000, 0x00, 0x0f, 0),
+};
+
+static struct bd71837_vrange bd71847_ldo5_vranges[] = {
+ BD_RANGE(1800000, 100000, 0x00, 0x0f, 0),
+ BD_RANGE(800000, 100000, 0x00, 0x0f, 0x20),
+};
+
+static struct bd71837_vrange ldo6_vranges[] = {
+ BD_RANGE(900000, 100000, 0x00, 0x09, 0),
+};
+
+static struct bd71837_vrange ldo7_vranges[] = {
+ BD_RANGE(1800000, 100000, 0x00, 0x0f, 0),
+};
+
+/*
+ * We use enable mask 'HW_STATE_CONTROL' to indicate that this regulator
+ * must not be enabled or disabled by SW. The typical use-case for BD71837
+ * is powering NXP i.MX8. In this use-case we (for now) only allow control
+ * for BUCK3 and BUCK4 which are not boot critical.
+ */
+static struct bd71837_platdata bd71837_reg_data[] = {
+/* Bucks 1-4 which support dynamic voltage scaling */
+ BD_DATA("BUCK1", BD718XX_BUCK1_CTRL, HW_STATE_CONTROL,
+ BD718XX_BUCK1_VOLT_RUN, DVS_BUCK_RUN_MASK, dvs_buck_vranges, 0,
+ true, BD718XX_BUCK_SEL),
+ BD_DATA("BUCK2", BD718XX_BUCK2_CTRL, HW_STATE_CONTROL,
+ BD718XX_BUCK2_VOLT_RUN, DVS_BUCK_RUN_MASK, dvs_buck_vranges, 0,
+ true, BD718XX_BUCK_SEL),
+ BD_DATA("BUCK3", BD71837_BUCK3_CTRL, BD718XX_BUCK_EN,
+ BD71837_BUCK3_VOLT_RUN, DVS_BUCK_RUN_MASK, dvs_buck_vranges, 0,
+ true, BD718XX_BUCK_SEL),
+ BD_DATA("BUCK4", BD71837_BUCK4_CTRL, BD718XX_BUCK_EN,
+ BD71837_BUCK4_VOLT_RUN, DVS_BUCK_RUN_MASK, dvs_buck_vranges, 0,
+ true, BD718XX_BUCK_SEL),
+/* Bucks 5-8 which do not support dynamic voltage scaling */
+ BD_DATA("BUCK5", BD718XX_1ST_NODVS_BUCK_CTRL, HW_STATE_CONTROL,
+ BD718XX_1ST_NODVS_BUCK_VOLT, BD718XX_1ST_NODVS_BUCK_MASK,
+ bd71837_buck5_vranges, 0x80, false, BD718XX_BUCK_SEL),
+ BD_DATA("BUCK6", BD718XX_2ND_NODVS_BUCK_CTRL, HW_STATE_CONTROL,
+ BD718XX_2ND_NODVS_BUCK_VOLT, BD71837_BUCK6_MASK,
+ bd71837_buck6_vranges, 0, false, BD718XX_BUCK_SEL),
+ BD_DATA("BUCK7", BD718XX_3RD_NODVS_BUCK_CTRL, HW_STATE_CONTROL,
+ BD718XX_3RD_NODVS_BUCK_VOLT, BD718XX_3RD_NODVS_BUCK_MASK,
+ nodvs_buck3_vranges, 0, false, BD718XX_BUCK_SEL),
+ BD_DATA("BUCK8", BD718XX_4TH_NODVS_BUCK_CTRL, HW_STATE_CONTROL,
+ BD718XX_4TH_NODVS_BUCK_VOLT, BD718XX_4TH_NODVS_BUCK_MASK,
+ nodvs_buck4_vranges, 0, false, BD718XX_BUCK_SEL),
+/* LDOs */
+ BD_DATA("LDO1", BD718XX_LDO1_VOLT, HW_STATE_CONTROL, BD718XX_LDO1_VOLT,
+ BD718XX_LDO1_MASK, ldo1_vranges, 0x20, false, BD718XX_LDO_SEL),
+ BD_DATA("LDO2", BD718XX_LDO2_VOLT, HW_STATE_CONTROL, BD718XX_LDO2_VOLT,
+ BD718XX_LDO2_MASK, ldo2_vranges, 0, false, BD718XX_LDO_SEL),
+ BD_DATA("LDO3", BD718XX_LDO3_VOLT, HW_STATE_CONTROL, BD718XX_LDO3_VOLT,
+ BD718XX_LDO3_MASK, ldo3_vranges, 0, false, BD718XX_LDO_SEL),
+ BD_DATA("LDO4", BD718XX_LDO4_VOLT, HW_STATE_CONTROL, BD718XX_LDO4_VOLT,
+ BD718XX_LDO4_MASK, ldo4_vranges, 0, false, BD718XX_LDO_SEL),
+ BD_DATA("LDO5", BD718XX_LDO5_VOLT, HW_STATE_CONTROL, BD718XX_LDO5_VOLT,
+ BD71837_LDO5_MASK, bd71837_ldo5_vranges, 0, false,
+ BD718XX_LDO_SEL),
+ BD_DATA("LDO6", BD718XX_LDO6_VOLT, HW_STATE_CONTROL, BD718XX_LDO6_VOLT,
+ BD718XX_LDO6_MASK, ldo6_vranges, 0, false, BD718XX_LDO_SEL),
+ BD_DATA("LDO7", BD71837_LDO7_VOLT, HW_STATE_CONTROL, BD71837_LDO7_VOLT,
+ BD71837_LDO7_MASK, ldo7_vranges, 0, false, BD718XX_LDO_SEL),
+};
+
+static struct bd71837_platdata bd71847_reg_data[] = {
+/* Bucks 1 and 2 which support dynamic voltage scaling */
+ BD_DATA("BUCK1", BD718XX_BUCK1_CTRL, HW_STATE_CONTROL,
+ BD718XX_BUCK1_VOLT_RUN, DVS_BUCK_RUN_MASK, dvs_buck_vranges, 0,
+ true, BD718XX_BUCK_SEL),
+ BD_DATA("BUCK2", BD718XX_BUCK2_CTRL, HW_STATE_CONTROL,
+ BD718XX_BUCK2_VOLT_RUN, DVS_BUCK_RUN_MASK, dvs_buck_vranges, 0,
+ true, BD718XX_BUCK_SEL),
+/* Bucks 3-6 which do not support dynamic voltage scaling */
+ BD_DATA("BUCK3", BD718XX_1ST_NODVS_BUCK_CTRL, HW_STATE_CONTROL,
+ BD718XX_1ST_NODVS_BUCK_VOLT, BD718XX_1ST_NODVS_BUCK_MASK,
+ bd71847_buck3_vranges, 0xc0, false, BD718XX_BUCK_SEL),
+ BD_DATA("BUCK4", BD718XX_2ND_NODVS_BUCK_CTRL, HW_STATE_CONTROL,
+ BD718XX_2ND_NODVS_BUCK_VOLT, BD71837_BUCK6_MASK,
+ bd71847_buck4_vranges, 0x40, false, BD718XX_BUCK_SEL),
+ BD_DATA("BUCK5", BD718XX_3RD_NODVS_BUCK_CTRL, HW_STATE_CONTROL,
+ BD718XX_3RD_NODVS_BUCK_VOLT, BD718XX_3RD_NODVS_BUCK_MASK,
+ nodvs_buck3_vranges, 0, false, BD718XX_BUCK_SEL),
+ BD_DATA("BUCK6", BD718XX_4TH_NODVS_BUCK_CTRL, HW_STATE_CONTROL,
+ BD718XX_4TH_NODVS_BUCK_VOLT, BD718XX_4TH_NODVS_BUCK_MASK,
+ nodvs_buck4_vranges, 0, false, BD718XX_BUCK_SEL),
+/* LDOs */
+ BD_DATA("LDO1", BD718XX_LDO1_VOLT, HW_STATE_CONTROL, BD718XX_LDO1_VOLT,
+ BD718XX_LDO1_MASK, ldo1_vranges, 0x20, false, BD718XX_LDO_SEL),
+ BD_DATA("LDO2", BD718XX_LDO2_VOLT, HW_STATE_CONTROL, BD718XX_LDO2_VOLT,
+ BD718XX_LDO2_MASK, ldo2_vranges, 0, false, BD718XX_LDO_SEL),
+ BD_DATA("LDO3", BD718XX_LDO3_VOLT, HW_STATE_CONTROL, BD718XX_LDO3_VOLT,
+ BD718XX_LDO3_MASK, ldo3_vranges, 0, false, BD718XX_LDO_SEL),
+ BD_DATA("LDO4", BD718XX_LDO4_VOLT, HW_STATE_CONTROL, BD718XX_LDO4_VOLT,
+ BD718XX_LDO4_MASK, ldo4_vranges, 0, false, BD718XX_LDO_SEL),
+ BD_DATA("LDO5", BD718XX_LDO5_VOLT, HW_STATE_CONTROL, BD718XX_LDO5_VOLT,
+ BD71847_LDO5_MASK, bd71847_ldo5_vranges, 0x20, false,
+ BD718XX_LDO_SEL),
+ BD_DATA("LDO6", BD718XX_LDO6_VOLT, HW_STATE_CONTROL, BD718XX_LDO6_VOLT,
+ BD718XX_LDO6_MASK, ldo6_vranges, 0, false, BD718XX_LDO_SEL),
+};
+
+static int vrange_find_value(struct bd71837_vrange *r, unsigned int sel,
+ unsigned int *val)
+{
+ if (!val || sel < r->min_sel || sel > r->max_sel)
+ return -EINVAL;
+
+ *val = r->min_volt + r->step * (sel - r->min_sel);
+ return 0;
+}
+
+static int vrange_find_selector(struct bd71837_vrange *r, int val,
+ unsigned int *sel)
+{
+ int ret = -EINVAL;
+ int num_vals = r->max_sel - r->min_sel + 1;
+
+ if (val >= r->min_volt &&
+ val <= r->min_volt + r->step * (num_vals - 1)) {
+ if (r->step) {
+ *sel = r->min_sel + ((val - r->min_volt) / r->step);
+ ret = 0;
+ } else {
+ *sel = r->min_sel;
+ ret = 0;
+ }
+ }
+ return ret;
+}
+
+static int bd71837_get_enable(struct udevice *dev)
+{
+ int val;
+ struct bd71837_platdata *plat = dev_get_platdata(dev);
+
+ /*
+ * boot critical regulators on bd71837 must not be controlled by sw
+ * due to the 'feature' which leaves power rails down if bd71837 is
+ * reseted to snvs state. hence we can't get the state here.
+ *
+ * if we are alive it means we probably are on run state and
+ * if the regulator can't be controlled we can assume it is
+ * enabled.
+ */
+ if (plat->enablemask == HW_STATE_CONTROL)
+ return 1;
+
+ val = pmic_reg_read(dev->parent, plat->enable_reg);
+ if (val < 0)
+ return val;
+
+ return (val & plat->enablemask);
+}
+
+static int bd71837_set_enable(struct udevice *dev, bool enable)
+{
+ int val = 0;
+ struct bd71837_platdata *plat = dev_get_platdata(dev);
+
+ /*
+ * boot critical regulators on bd71837 must not be controlled by sw
+ * due to the 'feature' which leaves power rails down if bd71837 is
+ * reseted to snvs state. Hence we can't set the state here.
+ */
+ if (plat->enablemask == HW_STATE_CONTROL)
+ return -EINVAL;
+
+ if (enable)
+ val = plat->enablemask;
+
+ return pmic_clrsetbits(dev->parent, plat->enable_reg, plat->enablemask,
+ val);
+}
+
+static int bd71837_set_value(struct udevice *dev, int uvolt)
+{
+ unsigned int sel;
+ unsigned int range;
+ int i;
+ int found = 0;
+ struct bd71837_platdata *plat = dev_get_platdata(dev);
+
+ /*
+ * An under/overshooting may occur if voltage is changed for other
+ * regulators but buck 1,2,3 or 4 when regulator is enabled. Prevent
+ * change to protect the HW
+ */
+ if (!plat->dvs)
+ if (bd71837_get_enable(dev)) {
+ pr_err("Only DVS bucks can be changed when enabled\n");
+ return -EINVAL;
+ }
+
+ for (i = 0; i < plat->numranges; i++) {
+ struct bd71837_vrange *r = &plat->ranges[i];
+
+ found = !vrange_find_selector(r, uvolt, &sel);
+ if (found) {
+ unsigned int tmp;
+
+ /*
+ * We require exactly the requested value to be
+ * supported - this can be changed later if needed
+ */
+ range = r->rangeval;
+ found = !vrange_find_value(r, sel, &tmp);
+ if (found && tmp == uvolt)
+ break;
+ found = 0;
+ }
+ }
+
+ if (!found)
+ return -EINVAL;
+
+ sel <<= ffs(plat->volt_mask) - 1;
+
+ if (plat->rangemask)
+ sel |= range;
+
+ return pmic_clrsetbits(dev->parent, plat->volt_reg, plat->volt_mask |
+ plat->rangemask, sel);
+}
+
+static int bd71837_get_value(struct udevice *dev)
+{
+ unsigned int reg, range;
+ unsigned int tmp;
+ struct bd71837_platdata *plat = dev_get_platdata(dev);
+ int i;
+
+ reg = pmic_reg_read(dev->parent, plat->volt_reg);
+ if (((int)reg) < 0)
+ return reg;
+
+ range = reg & plat->rangemask;
+
+ reg &= plat->volt_mask;
+ reg >>= ffs(plat->volt_mask) - 1;
+
+ for (i = 0; i < plat->numranges; i++) {
+ struct bd71837_vrange *r = &plat->ranges[i];
+
+ if (plat->rangemask && ((plat->rangemask & range) !=
+ r->rangeval))
+ continue;
+
+ if (!vrange_find_value(r, reg, &tmp))
+ return tmp;
+ }
+
+ pr_err("Unknown voltage value read from pmic\n");
+
+ return -EINVAL;
+}
+
+static int bd71837_regulator_probe(struct udevice *dev)
+{
+ struct bd71837_platdata *plat = dev_get_platdata(dev);
+ int i, ret;
+ struct dm_regulator_uclass_platdata *uc_pdata;
+ int type;
+ struct bd71837_platdata *init_data;
+ int data_amnt;
+
+ type = dev_get_driver_data(dev_get_parent(dev));
+
+ switch (type) {
+ case ROHM_CHIP_TYPE_BD71837:
+ init_data = bd71837_reg_data;
+ data_amnt = ARRAY_SIZE(bd71837_reg_data);
+ break;
+ case ROHM_CHIP_TYPE_BD71847:
+ init_data = bd71847_reg_data;
+ data_amnt = ARRAY_SIZE(bd71847_reg_data);
+ break;
+ default:
+ debug("Unknown PMIC type\n");
+ init_data = NULL;
+ data_amnt = 0;
+ break;
+ }
+
+ for (i = 0; i < data_amnt; i++) {
+ if (!strcmp(dev->name, init_data[i].name)) {
+ *plat = init_data[i];
+ if (plat->enablemask != HW_STATE_CONTROL) {
+ /*
+ * Take the regulator under SW control. Ensure
+ * the initial state matches dt flags and then
+ * write the SEL bit
+ */
+ uc_pdata = dev_get_uclass_platdata(dev);
+ ret = bd71837_set_enable(dev,
+ !!(uc_pdata->boot_on ||
+ uc_pdata->always_on));
+ if (ret)
+ return ret;
+
+ return pmic_clrsetbits(dev->parent,
+ plat->enable_reg,
+ plat->sel_mask,
+ plat->sel_mask);
+ }
+ return 0;
+ }
+ }
+
+ pr_err("Unknown regulator '%s'\n", dev->name);
+
+ return -ENOENT;
+}
+
+static const struct dm_regulator_ops bd71837_regulator_ops = {
+ .get_value = bd71837_get_value,
+ .set_value = bd71837_set_value,
+ .get_enable = bd71837_get_enable,
+ .set_enable = bd71837_set_enable,
+};
+
+U_BOOT_DRIVER(bd71837_regulator) = {
+ .name = BD718XX_REGULATOR_DRIVER,
+ .id = UCLASS_REGULATOR,
+ .ops = &bd71837_regulator_ops,
+ .probe = bd71837_regulator_probe,
+ .platdata_auto_alloc_size = sizeof(struct bd71837_platdata),
+};
diff --git a/drivers/power/regulator/fixed.c b/drivers/power/regulator/fixed.c
index a99aa78..763e671 100644
--- a/drivers/power/regulator/fixed.c
+++ b/drivers/power/regulator/fixed.c
@@ -5,56 +5,26 @@
* Przemyslaw Marczak <p.marczak@samsung.com>
*/
+#include "regulator_common.h"
#include <common.h>
#include <errno.h>
#include <dm.h>
-#include <i2c.h>
-#include <asm/gpio.h>
#include <power/pmic.h>
#include <power/regulator.h>
-struct fixed_regulator_platdata {
- struct gpio_desc gpio; /* GPIO for regulator enable control */
- unsigned int startup_delay_us;
- unsigned int off_on_delay_us;
-};
-
static int fixed_regulator_ofdata_to_platdata(struct udevice *dev)
{
struct dm_regulator_uclass_platdata *uc_pdata;
- struct fixed_regulator_platdata *dev_pdata;
- struct gpio_desc *gpio;
- int flags = GPIOD_IS_OUT;
- int ret;
+ struct regulator_common_platdata *dev_pdata;
dev_pdata = dev_get_platdata(dev);
uc_pdata = dev_get_uclass_platdata(dev);
if (!uc_pdata)
return -ENXIO;
- /* Set type to fixed */
uc_pdata->type = REGULATOR_TYPE_FIXED;
- if (dev_read_bool(dev, "enable-active-high"))
- flags |= GPIOD_IS_OUT_ACTIVE;
-
- /* Get fixed regulator optional enable GPIO desc */
- gpio = &dev_pdata->gpio;
- ret = gpio_request_by_name(dev, "gpio", 0, gpio, flags);
- if (ret) {
- debug("Fixed regulator optional enable GPIO - not found! Error: %d\n",
- ret);
- if (ret != -ENOENT)
- return ret;
- }
-
- /* Get optional ramp up delay */
- dev_pdata->startup_delay_us = dev_read_u32_default(dev,
- "startup-delay-us", 0);
- dev_pdata->off_on_delay_us =
- dev_read_u32_default(dev, "u-boot,off-on-delay-us", 0);
-
- return 0;
+ return regulator_common_ofdata_to_platdata(dev, dev_pdata, "gpio");
}
static int fixed_regulator_get_value(struct udevice *dev)
@@ -91,45 +61,12 @@
static int fixed_regulator_get_enable(struct udevice *dev)
{
- struct fixed_regulator_platdata *dev_pdata = dev_get_platdata(dev);
-
- /* Enable GPIO is optional */
- if (!dev_pdata->gpio.dev)
- return true;
-
- return dm_gpio_get_value(&dev_pdata->gpio);
+ return regulator_common_get_enable(dev, dev_get_platdata(dev));
}
static int fixed_regulator_set_enable(struct udevice *dev, bool enable)
{
- struct fixed_regulator_platdata *dev_pdata = dev_get_platdata(dev);
- int ret;
-
- debug("%s: dev='%s', enable=%d, delay=%d, has_gpio=%d\n", __func__,
- dev->name, enable, dev_pdata->startup_delay_us,
- dm_gpio_is_valid(&dev_pdata->gpio));
- /* Enable GPIO is optional */
- if (!dm_gpio_is_valid(&dev_pdata->gpio)) {
- if (!enable)
- return -ENOSYS;
- return 0;
- }
-
- ret = dm_gpio_set_value(&dev_pdata->gpio, enable);
- if (ret) {
- pr_err("Can't set regulator : %s gpio to: %d\n", dev->name,
- enable);
- return ret;
- }
-
- if (enable && dev_pdata->startup_delay_us)
- udelay(dev_pdata->startup_delay_us);
- debug("%s: done\n", __func__);
-
- if (!enable && dev_pdata->off_on_delay_us)
- udelay(dev_pdata->off_on_delay_us);
-
- return 0;
+ return regulator_common_set_enable(dev, dev_get_platdata(dev), enable);
}
static const struct dm_regulator_ops fixed_regulator_ops = {
@@ -150,5 +87,5 @@
.ops = &fixed_regulator_ops,
.of_match = fixed_regulator_ids,
.ofdata_to_platdata = fixed_regulator_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct fixed_regulator_platdata),
+ .platdata_auto_alloc_size = sizeof(struct regulator_common_platdata),
};
diff --git a/drivers/power/regulator/gpio-regulator.c b/drivers/power/regulator/gpio-regulator.c
index d18e5d8..ec1dcb6 100644
--- a/drivers/power/regulator/gpio-regulator.c
+++ b/drivers/power/regulator/gpio-regulator.c
@@ -4,6 +4,7 @@
* Keerthy <j-keerthy@ti.com>
*/
+#include "regulator_common.h"
#include <common.h>
#include <fdtdec.h>
#include <errno.h>
@@ -18,6 +19,7 @@
DECLARE_GLOBAL_DATA_PTR;
struct gpio_regulator_platdata {
+ struct regulator_common_platdata common;
struct gpio_desc gpio; /* GPIO for regulator voltage control */
int states[GPIO_REGULATOR_MAX_STATES];
int voltages[GPIO_REGULATOR_MAX_STATES];
@@ -65,7 +67,7 @@
j++;
}
- return 0;
+ return regulator_common_ofdata_to_platdata(dev, &dev_pdata->common, "enable-gpios");
}
static int gpio_regulator_get_value(struct udevice *dev)
@@ -116,9 +118,23 @@
return 0;
}
+static int gpio_regulator_get_enable(struct udevice *dev)
+{
+ struct gpio_regulator_platdata *dev_pdata = dev_get_platdata(dev);
+ return regulator_common_get_enable(dev, &dev_pdata->common);
+}
+
+static int gpio_regulator_set_enable(struct udevice *dev, bool enable)
+{
+ struct gpio_regulator_platdata *dev_pdata = dev_get_platdata(dev);
+ return regulator_common_set_enable(dev, &dev_pdata->common, enable);
+}
+
static const struct dm_regulator_ops gpio_regulator_ops = {
.get_value = gpio_regulator_get_value,
.set_value = gpio_regulator_set_value,
+ .get_enable = gpio_regulator_get_enable,
+ .set_enable = gpio_regulator_set_enable,
};
static const struct udevice_id gpio_regulator_ids[] = {
diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c
index 9118b8e..76be95b 100644
--- a/drivers/power/regulator/regulator-uclass.c
+++ b/drivers/power/regulator/regulator-uclass.c
@@ -238,6 +238,9 @@
if (!uc_pdata->always_on && !uc_pdata->boot_on)
return -EMEDIUMTYPE;
+ if (uc_pdata->type == REGULATOR_TYPE_FIXED)
+ return regulator_set_enable(dev, true);
+
if (uc_pdata->flags & REGULATOR_FLAG_AUTOSET_UV)
ret = regulator_set_value(dev, uc_pdata->min_uV);
if (!ret && (uc_pdata->flags & REGULATOR_FLAG_AUTOSET_UA))
diff --git a/drivers/power/regulator/regulator_common.c b/drivers/power/regulator/regulator_common.c
new file mode 100644
index 0000000..3dabbe2
--- /dev/null
+++ b/drivers/power/regulator/regulator_common.c
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Disruptive Technologies Research AS
+ * Sven Schwermer <sven.svenschwermer@disruptive-technologies.com>
+ */
+
+#include "regulator_common.h"
+#include <common.h>
+#include <power/regulator.h>
+
+int regulator_common_ofdata_to_platdata(struct udevice *dev,
+ struct regulator_common_platdata *dev_pdata, const char *enable_gpio_name)
+{
+ struct gpio_desc *gpio;
+ int flags = GPIOD_IS_OUT;
+ int ret;
+
+ if (dev_read_bool(dev, "enable-active-high"))
+ flags |= GPIOD_IS_OUT_ACTIVE;
+
+ /* Get optional enable GPIO desc */
+ gpio = &dev_pdata->gpio;
+ ret = gpio_request_by_name(dev, enable_gpio_name, 0, gpio, flags);
+ if (ret) {
+ debug("Regulator '%s' optional enable GPIO - not found! Error: %d\n",
+ dev->name, ret);
+ if (ret != -ENOENT)
+ return ret;
+ }
+
+ /* Get optional ramp up delay */
+ dev_pdata->startup_delay_us = dev_read_u32_default(dev,
+ "startup-delay-us", 0);
+ dev_pdata->off_on_delay_us =
+ dev_read_u32_default(dev, "u-boot,off-on-delay-us", 0);
+
+ return 0;
+}
+
+int regulator_common_get_enable(const struct udevice *dev,
+ struct regulator_common_platdata *dev_pdata)
+{
+ /* Enable GPIO is optional */
+ if (!dev_pdata->gpio.dev)
+ return true;
+
+ return dm_gpio_get_value(&dev_pdata->gpio);
+}
+
+int regulator_common_set_enable(const struct udevice *dev,
+ struct regulator_common_platdata *dev_pdata, bool enable)
+{
+ int ret;
+
+ debug("%s: dev='%s', enable=%d, delay=%d, has_gpio=%d\n", __func__,
+ dev->name, enable, dev_pdata->startup_delay_us,
+ dm_gpio_is_valid(&dev_pdata->gpio));
+ /* Enable GPIO is optional */
+ if (!dm_gpio_is_valid(&dev_pdata->gpio)) {
+ if (!enable)
+ return -ENOSYS;
+ return 0;
+ }
+
+ ret = dm_gpio_set_value(&dev_pdata->gpio, enable);
+ if (ret) {
+ pr_err("Can't set regulator : %s gpio to: %d\n", dev->name,
+ enable);
+ return ret;
+ }
+
+ if (enable && dev_pdata->startup_delay_us)
+ udelay(dev_pdata->startup_delay_us);
+ debug("%s: done\n", __func__);
+
+ if (!enable && dev_pdata->off_on_delay_us)
+ udelay(dev_pdata->off_on_delay_us);
+
+ return 0;
+}
diff --git a/drivers/power/regulator/regulator_common.h b/drivers/power/regulator/regulator_common.h
new file mode 100644
index 0000000..18a5258
--- /dev/null
+++ b/drivers/power/regulator/regulator_common.h
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Disruptive Technologies Research AS
+ * Sven Schwermer <sven.svenschwermer@disruptive-technologies.com>
+ */
+
+#ifndef _REGULATOR_COMMON_H
+#define _REGULATOR_COMMON_H
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <dm.h>
+
+struct regulator_common_platdata {
+ struct gpio_desc gpio; /* GPIO for regulator enable control */
+ unsigned int startup_delay_us;
+ unsigned int off_on_delay_us;
+};
+
+int regulator_common_ofdata_to_platdata(struct udevice *dev,
+ struct regulator_common_platdata *dev_pdata, const char *enable_gpio_name);
+int regulator_common_get_enable(const struct udevice *dev,
+ struct regulator_common_platdata *dev_pdata);
+int regulator_common_set_enable(const struct udevice *dev,
+ struct regulator_common_platdata *dev_pdata, bool enable);
+
+#endif /* _REGULATOR_COMMON_H */
diff --git a/drivers/power/regulator/stm32-vrefbuf.c b/drivers/power/regulator/stm32-vrefbuf.c
index 0ad6833..645528e 100644
--- a/drivers/power/regulator/stm32-vrefbuf.c
+++ b/drivers/power/regulator/stm32-vrefbuf.c
@@ -30,7 +30,7 @@
struct udevice *vdda_supply;
};
-static const unsigned int stm32_vrefbuf_voltages[] = {
+static const int stm32_vrefbuf_voltages[] = {
/* Matches resp. VRS = 000b, 001b, 010b, 011b */
2500000, 2048000, 1800000, 1500000,
};
diff --git a/drivers/power/regulator/stpmic1.c b/drivers/power/regulator/stpmic1.c
index 50ef2a2..1e3f96f 100644
--- a/drivers/power/regulator/stpmic1.c
+++ b/drivers/power/regulator/stpmic1.c
@@ -422,6 +422,7 @@
case STPMIC1_LDO_MODE_SINK_SOURCE:
ret &= ~STPMIC1_LDO12356_VOUT_MASK;
ret |= STPMIC1_LDO3_DDR_SEL << STPMIC1_LDO12356_VOUT_SHIFT;
+ /* fallthrough */
case STPMIC1_LDO_MODE_NORMAL:
ret &= ~STPMIC1_LDO3_MODE;
break;
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 2984b79..1f36fc7 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -18,6 +18,11 @@
used. It provides 5 channels which can be independently
programmed. Channel 4 (the last) is normally used as a timer.
+config PWM_IMX
+ bool "Enable support for i.MX27 and later PWM"
+ help
+ This PWM is found i.MX27 and later i.MX SoCs.
+
config PWM_ROCKCHIP
bool "Enable support for the Rockchip PWM"
depends on DM_PWM
diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
index 83c1bfa..8d8f3e6 100644
--- a/drivers/pwm/pwm-imx.c
+++ b/drivers/pwm/pwm-imx.c
@@ -8,6 +8,7 @@
#include <common.h>
#include <div64.h>
+#include <dm.h>
#include <pwm.h>
#include <asm/arch/imx-regs.h>
#include <asm/io.h>
@@ -24,18 +25,12 @@
return 0;
}
-int pwm_config(int pwm_id, int duty_ns, int period_ns)
+int pwm_config_internal(struct pwm_regs *pwm, unsigned long period_cycles,
+ unsigned long duty_cycles, unsigned long prescale)
{
- struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id);
- unsigned long period_cycles, duty_cycles, prescale;
u32 cr;
- if (!pwm)
- return -1;
-
- pwm_imx_get_parms(period_ns, duty_ns, &period_cycles, &duty_cycles,
- &prescale);
-
+ writel(0, &pwm->ir);
cr = PWMCR_PRESCALER(prescale) |
PWMCR_DOZEEN | PWMCR_WAITEN |
PWMCR_DBGEN | PWMCR_CLKSRC_IPG_HIGH;
@@ -48,6 +43,20 @@
return 0;
}
+int pwm_config(int pwm_id, int duty_ns, int period_ns)
+{
+ struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id);
+ unsigned long period_cycles, duty_cycles, prescale;
+
+ if (!pwm)
+ return -1;
+
+ pwm_imx_get_parms(period_ns, duty_ns, &period_cycles, &duty_cycles,
+ &prescale);
+
+ return pwm_config_internal(pwm, period_cycles, duty_cycles, prescale);
+}
+
int pwm_enable(int pwm_id)
{
struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id);
@@ -68,3 +77,86 @@
clrbits_le32(&pwm->cr, PWMCR_EN);
}
+
+#if defined(CONFIG_DM_PWM)
+struct imx_pwm_priv {
+ struct pwm_regs *regs;
+ bool invert;
+};
+
+static int imx_pwm_set_invert(struct udevice *dev, uint channel,
+ bool polarity)
+{
+ struct imx_pwm_priv *priv = dev_get_priv(dev);
+
+ debug("%s: polarity=%u\n", __func__, polarity);
+ priv->invert = polarity;
+
+ return 0;
+}
+
+static int imx_pwm_set_config(struct udevice *dev, uint channel,
+ uint period_ns, uint duty_ns)
+{
+ struct imx_pwm_priv *priv = dev_get_priv(dev);
+ struct pwm_regs *regs = priv->regs;
+ unsigned long period_cycles, duty_cycles, prescale;
+
+ debug("%s: Config '%s' channel: %d\n", __func__, dev->name, channel);
+
+ pwm_imx_get_parms(period_ns, duty_ns, &period_cycles, &duty_cycles,
+ &prescale);
+
+ return pwm_config_internal(regs, period_cycles, duty_cycles, prescale);
+};
+
+static int imx_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
+{
+ struct imx_pwm_priv *priv = dev_get_priv(dev);
+ struct pwm_regs *regs = priv->regs;
+
+ debug("%s: Enable '%s' state: %d\n", __func__, dev->name, enable);
+
+ if (enable)
+ setbits_le32(®s->cr, PWMCR_EN);
+ else
+ clrbits_le32(®s->cr, PWMCR_EN);
+
+ return 0;
+};
+
+static int imx_pwm_ofdata_to_platdata(struct udevice *dev)
+{
+ struct imx_pwm_priv *priv = dev_get_priv(dev);
+
+ priv->regs = (struct pwm_regs *)devfdt_get_addr(dev);
+
+ return 0;
+}
+
+static int imx_pwm_probe(struct udevice *dev)
+{
+ return 0;
+}
+
+static const struct pwm_ops imx_pwm_ops = {
+ .set_invert = imx_pwm_set_invert,
+ .set_config = imx_pwm_set_config,
+ .set_enable = imx_pwm_set_enable,
+};
+
+static const struct udevice_id imx_pwm_ids[] = {
+ { .compatible = "fsl,imx27-pwm" },
+ { }
+};
+
+U_BOOT_DRIVER(imx_pwm) = {
+ .name = "imx_pwm",
+ .id = UCLASS_PWM,
+ .of_match = imx_pwm_ids,
+ .ops = &imx_pwm_ops,
+ .ofdata_to_platdata = imx_pwm_ofdata_to_platdata,
+ .probe = imx_pwm_probe,
+ .priv_auto_alloc_size = sizeof(struct imx_pwm_priv),
+};
+#endif
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 505ae9b..6e4d732 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -14,7 +14,6 @@
#include <linux/immap_qe.h>
#include <fsl_qe.h>
#include <mmc.h>
-#include <environment.h>
#ifdef CONFIG_ARCH_LS1021A
#include <asm/arch/immap_ls102xa.h>
diff --git a/drivers/ram/rockchip/sdram_rk322x.c b/drivers/ram/rockchip/sdram_rk322x.c
index e96ac54..94893e1 100644
--- a/drivers/ram/rockchip/sdram_rk322x.c
+++ b/drivers/ram/rockchip/sdram_rk322x.c
@@ -16,7 +16,6 @@
#include <asm/arch-rockchip/grf_rk322x.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/sdram_rk322x.h>
-#include <asm/arch-rockchip/timer.h>
#include <asm/arch-rockchip/uart.h>
#include <asm/arch-rockchip/sdram_common.h>
#include <asm/types.h>
@@ -96,26 +95,26 @@
1 << DDRCTRL_PSRST_SHIFT | 1 << DDRCTRL_SRST_SHIFT |
1 << DDRPHY_PSRST_SHIFT | 1 << DDRPHY_SRST_SHIFT);
- rockchip_udelay(10);
+ udelay(10);
rk_clrreg(&cru->cru_softrst_con[5], 1 << DDRPHY_PSRST_SHIFT |
1 << DDRPHY_SRST_SHIFT);
- rockchip_udelay(10);
+ udelay(10);
rk_clrreg(&cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT |
1 << DDRCTRL_SRST_SHIFT);
- rockchip_udelay(10);
+ udelay(10);
clrbits_le32(&ddr_phy->ddrphy_reg[0],
SOFT_RESET_MASK << SOFT_RESET_SHIFT);
- rockchip_udelay(10);
+ udelay(10);
setbits_le32(&ddr_phy->ddrphy_reg[0],
SOFT_DERESET_ANALOG);
- rockchip_udelay(5);
+ udelay(5);
setbits_le32(&ddr_phy->ddrphy_reg[0],
SOFT_DERESET_DIGITAL);
- rockchip_udelay(1);
+ udelay(1);
}
void phy_dll_bypass_set(struct rk322x_ddr_phy *ddr_phy, u32 freq)
@@ -154,7 +153,7 @@
u32 rank, u32 cmd, u32 arg)
{
writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd);
- rockchip_udelay(1);
+ udelay(1);
while (readl(&pctl->mcmd) & START_CMD)
;
}
@@ -167,7 +166,7 @@
if (dramtype == DDR3) {
send_command(pctl, 3, DESELECT_CMD, 0);
- rockchip_udelay(1);
+ udelay(1);
send_command(pctl, 3, PREA_CMD, 0);
send_command(pctl, 3, MRS_CMD,
(0x02 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |
@@ -196,17 +195,17 @@
(0x63 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT |
(0 & LPDDR23_OP_MASK) <<
LPDDR23_OP_SHIFT);
- rockchip_udelay(10);
+ udelay(10);
send_command(pctl, 3, MRS_CMD,
(0x10 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT |
(0xff & LPDDR23_OP_MASK) <<
LPDDR23_OP_SHIFT);
- rockchip_udelay(1);
+ udelay(1);
send_command(pctl, 3, MRS_CMD,
(0x10 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT |
(0xff & LPDDR23_OP_MASK) <<
LPDDR23_OP_SHIFT);
- rockchip_udelay(1);
+ udelay(1);
send_command(pctl, 3, MRS_CMD,
(1 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT |
(sdram_params->phy_timing.mr[1] &
@@ -243,7 +242,7 @@
DQS_SQU_CAL_SEL_CS0);
setbits_le32(&ddr_phy->ddrphy_reg[2], DQS_SQU_CAL_START);
- rockchip_udelay(30);
+ udelay(30);
ret = readl(&ddr_phy->ddrphy_reg[0xff]);
clrbits_le32(&ddr_phy->ddrphy_reg[2],
@@ -367,9 +366,9 @@
writel(GRF_DDRPHY_BUFFEREN_CORE_EN, &grf->soc_con[0]);
clrbits_le32(&ddr_phy->ddrphy_reg[0], 0x3 << 2);
- rockchip_udelay(1);
+ udelay(1);
setbits_le32(&ddr_phy->ddrphy_reg[0], 1 << 2);
- rockchip_udelay(5);
+ udelay(5);
setbits_le32(&ddr_phy->ddrphy_reg[0], 1 << 3);
writel(GRF_DDRPHY_BUFFEREN_CORE_DIS, &grf->soc_con[0]);
}
diff --git a/drivers/ram/rockchip/sdram_rk3288.c b/drivers/ram/rockchip/sdram_rk3288.c
index 6bb025a..5775254 100644
--- a/drivers/ram/rockchip/sdram_rk3288.c
+++ b/drivers/ram/rockchip/sdram_rk3288.c
@@ -79,7 +79,8 @@
#define DQS_GATE_TRAINING_ERROR_RANK0 (1 << 4)
#define DQS_GATE_TRAINING_ERROR_RANK1 (2 << 4)
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_TPL_BUILD) || \
+ (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
{
int i;
@@ -1035,7 +1036,8 @@
static int rk3288_dmc_probe(struct udevice *dev)
{
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_TPL_BUILD) || \
+ (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
struct rk3288_sdram_params *plat = dev_get_platdata(dev);
struct udevice *dev_clk;
struct regmap *map;
@@ -1044,7 +1046,8 @@
struct dram_info *priv = dev_get_priv(dev);
priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_TPL_BUILD) || \
+ (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
#if CONFIG_IS_ENABLED(OF_PLATDATA)
ret = conv_of_platdata(dev);
if (ret)
@@ -1111,12 +1114,14 @@
.id = UCLASS_RAM,
.of_match = rk3288_dmc_ids,
.ops = &rk3288_dmc_ops,
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_TPL_BUILD) || \
+ (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
.ofdata_to_platdata = rk3288_dmc_ofdata_to_platdata,
#endif
.probe = rk3288_dmc_probe,
.priv_auto_alloc_size = sizeof(struct dram_info),
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_TPL_BUILD) || \
+ (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
.platdata_auto_alloc_size = sizeof(struct rk3288_sdram_params),
#endif
};
diff --git a/drivers/ram/rockchip/sdram_rk3328.c b/drivers/ram/rockchip/sdram_rk3328.c
index f4e0b18..656696a 100644
--- a/drivers/ram/rockchip/sdram_rk3328.c
+++ b/drivers/ram/rockchip/sdram_rk3328.c
@@ -2,22 +2,1029 @@
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd.
*/
-
#include <common.h>
+#include <clk.h>
+#include <debug_uart.h>
#include <dm.h>
+#include <dt-structs.h>
#include <ram.h>
+#include <regmap.h>
#include <syscon.h>
+#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3328.h>
#include <asm/arch-rockchip/grf_rk3328.h>
#include <asm/arch-rockchip/sdram_common.h>
+#include <asm/arch-rockchip/sdram_rk3328.h>
+#include <asm/arch-rockchip/uart.h>
struct dram_info {
+#ifdef CONFIG_TPL_BUILD
+ struct rk3328_ddr_pctl_regs *pctl;
+ struct rk3328_ddr_phy_regs *phy;
+ struct clk ddr_clk;
+ struct rk3328_cru *cru;
+ struct rk3328_msch_regs *msch;
+ struct rk3328_ddr_grf_regs *ddr_grf;
+#endif
struct ram_info info;
struct rk3328_grf_regs *grf;
};
+#ifdef CONFIG_TPL_BUILD
+
+struct rk3328_sdram_channel sdram_ch;
+
+struct rockchip_dmc_plat {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct dtd_rockchip_rk3328_dmc dtplat;
+#else
+ struct rk3328_sdram_params sdram_params;
+#endif
+ struct regmap *map;
+};
+
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+static int conv_of_platdata(struct udevice *dev)
+{
+ struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
+ struct dtd_rockchip_rk3328_dmc *dtplat = &plat->dtplat;
+ int ret;
+
+ ret = regmap_init_mem_platdata(dev, dtplat->reg,
+ ARRAY_SIZE(dtplat->reg) / 2,
+ &plat->map);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+#endif
+
+static void rkclk_ddr_reset(struct dram_info *dram,
+ u32 ctl_srstn, u32 ctl_psrstn,
+ u32 phy_srstn, u32 phy_psrstn)
+{
+ writel(ddrctrl_srstn_req(ctl_srstn) | ddrctrl_psrstn_req(ctl_psrstn) |
+ ddrphy_srstn_req(phy_srstn) | ddrphy_psrstn_req(phy_psrstn),
+ &dram->cru->softrst_con[5]);
+ writel(ddrctrl_asrstn_req(ctl_srstn), &dram->cru->softrst_con[9]);
+}
+
+static void rkclk_set_dpll(struct dram_info *dram, unsigned int mhz)
+{
+ unsigned int refdiv, postdiv1, postdiv2, fbdiv;
+ int delay = 1000;
+
+ refdiv = 1;
+ if (mhz <= 300) {
+ postdiv1 = 4;
+ postdiv2 = 2;
+ } else if (mhz <= 400) {
+ postdiv1 = 6;
+ postdiv2 = 1;
+ } else if (mhz <= 600) {
+ postdiv1 = 4;
+ postdiv2 = 1;
+ } else if (mhz <= 800) {
+ postdiv1 = 3;
+ postdiv2 = 1;
+ } else if (mhz <= 1600) {
+ postdiv1 = 2;
+ postdiv2 = 1;
+ } else {
+ postdiv1 = 1;
+ postdiv2 = 1;
+ }
+ fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24;
+
+ writel(((0x1 << 4) << 16) | (0 << 4), &dram->cru->mode_con);
+ writel(POSTDIV1(postdiv1) | FBDIV(fbdiv), &dram->cru->dpll_con[0]);
+ writel(DSMPD(1) | POSTDIV2(postdiv2) | REFDIV(refdiv),
+ &dram->cru->dpll_con[1]);
+
+ while (delay > 0) {
+ udelay(1);
+ if (LOCK(readl(&dram->cru->dpll_con[1])))
+ break;
+ delay--;
+ }
+
+ writel(((0x1 << 4) << 16) | (1 << 4), &dram->cru->mode_con);
+}
+
+static void rkclk_configure_ddr(struct dram_info *dram,
+ struct rk3328_sdram_params *sdram_params)
+{
+ void __iomem *phy_base = dram->phy;
+
+ /* choose DPLL for ddr clk source */
+ clrbits_le32(PHY_REG(phy_base, 0xef), 1 << 7);
+
+ /* for inno ddr phy need 2*freq */
+ rkclk_set_dpll(dram, sdram_params->ddr_freq * 2);
+}
+
+static void phy_soft_reset(struct dram_info *dram)
+{
+ void __iomem *phy_base = dram->phy;
+
+ clrbits_le32(PHY_REG(phy_base, 0), 0x3 << 2);
+ udelay(1);
+ setbits_le32(PHY_REG(phy_base, 0), ANALOG_DERESET);
+ udelay(5);
+ setbits_le32(PHY_REG(phy_base, 0), DIGITAL_DERESET);
+ udelay(1);
+}
+
+static int pctl_cfg(struct dram_info *dram,
+ struct rk3328_sdram_params *sdram_params)
+{
+ u32 i;
+ void __iomem *pctl_base = dram->pctl;
+
+ for (i = 0; sdram_params->pctl_regs.pctl[i][0] != 0xFFFFFFFF; i++) {
+ writel(sdram_params->pctl_regs.pctl[i][1],
+ pctl_base + sdram_params->pctl_regs.pctl[i][0]);
+ }
+ clrsetbits_le32(pctl_base + DDR_PCTL2_PWRTMG,
+ (0xff << 16) | 0x1f,
+ ((SR_IDLE & 0xff) << 16) | (PD_IDLE & 0x1f));
+ /*
+ * dfi_lp_en_pd=1,dfi_lp_wakeup_pd=2
+ * hw_lp_idle_x32=1
+ */
+ if (sdram_params->dramtype == LPDDR3) {
+ setbits_le32(pctl_base + DDR_PCTL2_DFILPCFG0, 1);
+ clrsetbits_le32(pctl_base + DDR_PCTL2_DFILPCFG0,
+ 0xf << 4,
+ 2 << 4);
+ }
+ clrsetbits_le32(pctl_base + DDR_PCTL2_HWLPCTL,
+ 0xfff << 16,
+ 1 << 16);
+ /* disable zqcs */
+ setbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1u << 31);
+ setbits_le32(pctl_base + 0x2000 + DDR_PCTL2_ZQCTL0, 1u << 31);
+
+ return 0;
+}
+
+/* return ddrconfig value
+ * (-1), find ddrconfig fail
+ * other, the ddrconfig value
+ * only support cs0_row >= cs1_row
+ */
+static unsigned int calculate_ddrconfig(struct rk3328_sdram_params *sdram_params)
+{
+ static const u16 ddr_cfg_2_rbc[] = {
+ /***************************
+ * [5:4] row(13+n)
+ * [3] cs(0:0 cs, 1:2 cs)
+ * [2] bank(0:0bank,1:8bank)
+ * [1:0] col(11+n)
+ ****************************/
+ /* row, cs, bank, col */
+ ((3 << 4) | (0 << 3) | (1 << 2) | 0),
+ ((3 << 4) | (0 << 3) | (1 << 2) | 1),
+ ((2 << 4) | (0 << 3) | (1 << 2) | 2),
+ ((3 << 4) | (0 << 3) | (1 << 2) | 2),
+ ((2 << 4) | (0 << 3) | (1 << 2) | 3),
+ ((3 << 4) | (1 << 3) | (1 << 2) | 0),
+ ((3 << 4) | (1 << 3) | (1 << 2) | 1),
+ ((2 << 4) | (1 << 3) | (1 << 2) | 2),
+ ((3 << 4) | (0 << 3) | (0 << 2) | 1),
+ ((2 << 4) | (0 << 3) | (1 << 2) | 1),
+ };
+
+ static const u16 ddr4_cfg_2_rbc[] = {
+ /***************************
+ * [6] cs 0:0cs 1:2 cs
+ * [5:3] row(13+n)
+ * [2] cs(0:0 cs, 1:2 cs)
+ * [1] bw 0: 16bit 1:32bit
+ * [0] diebw 0:8bit 1:16bit
+ ***************************/
+ /* cs, row, cs, bw, diebw */
+ ((0 << 6) | (3 << 3) | (0 << 2) | (1 << 1) | 0),
+ ((1 << 6) | (2 << 3) | (0 << 2) | (1 << 1) | 0),
+ ((0 << 6) | (4 << 3) | (0 << 2) | (0 << 1) | 0),
+ ((1 << 6) | (3 << 3) | (0 << 2) | (0 << 1) | 0),
+ ((0 << 6) | (4 << 3) | (0 << 2) | (1 << 1) | 1),
+ ((1 << 6) | (3 << 3) | (0 << 2) | (1 << 1) | 1),
+ ((1 << 6) | (4 << 3) | (0 << 2) | (0 << 1) | 1),
+ ((0 << 6) | (2 << 3) | (1 << 2) | (1 << 1) | 0),
+ ((0 << 6) | (3 << 3) | (1 << 2) | (0 << 1) | 0),
+ ((0 << 6) | (3 << 3) | (1 << 2) | (1 << 1) | 1),
+ ((0 << 6) | (4 << 3) | (1 << 2) | (0 << 1) | 1),
+ };
+
+ u32 cs, bw, die_bw, col, row, bank;
+ u32 i, tmp;
+ u32 ddrconf = -1;
+
+ cs = sdram_ch.rank;
+ bw = sdram_ch.bw;
+ die_bw = sdram_ch.dbw;
+ col = sdram_ch.col;
+ row = sdram_ch.cs0_row;
+ bank = sdram_ch.bk;
+
+ if (sdram_params->dramtype == DDR4) {
+ tmp = ((cs - 1) << 6) | ((row - 13) << 3) | (bw & 0x2) | die_bw;
+ for (i = 10; i < 17; i++) {
+ if (((tmp & 0x7) == (ddr4_cfg_2_rbc[i - 10] & 0x7)) &&
+ ((tmp & 0x3c) <= (ddr4_cfg_2_rbc[i - 10] & 0x3c)) &&
+ ((tmp & 0x40) <= (ddr4_cfg_2_rbc[i - 10] & 0x40))) {
+ ddrconf = i;
+ goto out;
+ }
+ }
+ } else {
+ if (bank == 2) {
+ ddrconf = 8;
+ goto out;
+ }
+
+ tmp = ((row - 13) << 4) | (1 << 2) | ((bw + col - 11) << 0);
+ for (i = 0; i < 5; i++)
+ if (((tmp & 0xf) == (ddr_cfg_2_rbc[i] & 0xf)) &&
+ ((tmp & 0x30) <= (ddr_cfg_2_rbc[i] & 0x30))) {
+ ddrconf = i;
+ goto out;
+ }
+ }
+
+out:
+ if (ddrconf > 20)
+ printf("calculate_ddrconfig error\n");
+
+ return ddrconf;
+}
+
+/* n: Unit bytes */
+static void copy_to_reg(u32 *dest, u32 *src, u32 n)
+{
+ int i;
+
+ for (i = 0; i < n / sizeof(u32); i++) {
+ writel(*src, dest);
+ src++;
+ dest++;
+ }
+}
+
+/*******
+ * calculate controller dram address map, and setting to register.
+ * argument sdram_ch.ddrconf must be right value before
+ * call this function.
+ *******/
+static void set_ctl_address_map(struct dram_info *dram,
+ struct rk3328_sdram_params *sdram_params)
+{
+ void __iomem *pctl_base = dram->pctl;
+
+ copy_to_reg((u32 *)(pctl_base + DDR_PCTL2_ADDRMAP0),
+ &addrmap[sdram_ch.ddrconfig][0], 9 * 4);
+ if (sdram_params->dramtype == LPDDR3 && sdram_ch.row_3_4)
+ setbits_le32(pctl_base + DDR_PCTL2_ADDRMAP6, 1 << 31);
+ if (sdram_params->dramtype == DDR4 && sdram_ch.bw == 0x1)
+ setbits_le32(pctl_base + DDR_PCTL2_PCCFG, 1 << 8);
+
+ if (sdram_ch.rank == 1)
+ clrsetbits_le32(pctl_base + DDR_PCTL2_ADDRMAP0, 0x1f, 0x1f);
+}
+
+static void phy_dll_bypass_set(struct dram_info *dram, u32 freq)
+{
+ u32 tmp;
+ void __iomem *phy_base = dram->phy;
+
+ setbits_le32(PHY_REG(phy_base, 0x13), 1 << 4);
+ clrbits_le32(PHY_REG(phy_base, 0x14), 1 << 3);
+ setbits_le32(PHY_REG(phy_base, 0x26), 1 << 4);
+ clrbits_le32(PHY_REG(phy_base, 0x27), 1 << 3);
+ setbits_le32(PHY_REG(phy_base, 0x36), 1 << 4);
+ clrbits_le32(PHY_REG(phy_base, 0x37), 1 << 3);
+ setbits_le32(PHY_REG(phy_base, 0x46), 1 << 4);
+ clrbits_le32(PHY_REG(phy_base, 0x47), 1 << 3);
+ setbits_le32(PHY_REG(phy_base, 0x56), 1 << 4);
+ clrbits_le32(PHY_REG(phy_base, 0x57), 1 << 3);
+
+ if (freq <= (400 * MHz))
+ /* DLL bypass */
+ setbits_le32(PHY_REG(phy_base, 0xa4), 0x1f);
+ else
+ clrbits_le32(PHY_REG(phy_base, 0xa4), 0x1f);
+ if (freq <= (680 * MHz))
+ tmp = 2;
+ else
+ tmp = 1;
+ writel(tmp, PHY_REG(phy_base, 0x28));
+ writel(tmp, PHY_REG(phy_base, 0x38));
+ writel(tmp, PHY_REG(phy_base, 0x48));
+ writel(tmp, PHY_REG(phy_base, 0x58));
+}
+
+static void set_ds_odt(struct dram_info *dram,
+ struct rk3328_sdram_params *sdram_params)
+{
+ u32 cmd_drv, clk_drv, dqs_drv, dqs_odt;
+ void __iomem *phy_base = dram->phy;
+
+ if (sdram_params->dramtype == DDR3) {
+ cmd_drv = PHY_DDR3_RON_RTT_34ohm;
+ clk_drv = PHY_DDR3_RON_RTT_45ohm;
+ dqs_drv = PHY_DDR3_RON_RTT_34ohm;
+ dqs_odt = PHY_DDR3_RON_RTT_225ohm;
+ } else {
+ cmd_drv = PHY_DDR4_LPDDR3_RON_RTT_34ohm;
+ clk_drv = PHY_DDR4_LPDDR3_RON_RTT_43ohm;
+ dqs_drv = PHY_DDR4_LPDDR3_RON_RTT_34ohm;
+ dqs_odt = PHY_DDR4_LPDDR3_RON_RTT_240ohm;
+ }
+ /* DS */
+ writel(cmd_drv, PHY_REG(phy_base, 0x11));
+ clrsetbits_le32(PHY_REG(phy_base, 0x12), 0x1f << 3, cmd_drv << 3);
+ writel(clk_drv, PHY_REG(phy_base, 0x16));
+ writel(clk_drv, PHY_REG(phy_base, 0x18));
+ writel(dqs_drv, PHY_REG(phy_base, 0x20));
+ writel(dqs_drv, PHY_REG(phy_base, 0x2f));
+ writel(dqs_drv, PHY_REG(phy_base, 0x30));
+ writel(dqs_drv, PHY_REG(phy_base, 0x3f));
+ writel(dqs_drv, PHY_REG(phy_base, 0x40));
+ writel(dqs_drv, PHY_REG(phy_base, 0x4f));
+ writel(dqs_drv, PHY_REG(phy_base, 0x50));
+ writel(dqs_drv, PHY_REG(phy_base, 0x5f));
+ /* ODT */
+ writel(dqs_odt, PHY_REG(phy_base, 0x21));
+ writel(dqs_odt, PHY_REG(phy_base, 0x2e));
+ writel(dqs_odt, PHY_REG(phy_base, 0x31));
+ writel(dqs_odt, PHY_REG(phy_base, 0x3e));
+ writel(dqs_odt, PHY_REG(phy_base, 0x41));
+ writel(dqs_odt, PHY_REG(phy_base, 0x4e));
+ writel(dqs_odt, PHY_REG(phy_base, 0x51));
+ writel(dqs_odt, PHY_REG(phy_base, 0x5e));
+}
+
+static void phy_cfg(struct dram_info *dram,
+ struct rk3328_sdram_params *sdram_params)
+{
+ u32 i;
+ void __iomem *phy_base = dram->phy;
+
+ phy_dll_bypass_set(dram, sdram_params->ddr_freq);
+ for (i = 0; sdram_params->phy_regs.phy[i][0] != 0xFFFFFFFF; i++) {
+ writel(sdram_params->phy_regs.phy[i][1],
+ phy_base + sdram_params->phy_regs.phy[i][0]);
+ }
+ if (sdram_ch.bw == 2) {
+ clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 0xf << 4);
+ } else {
+ clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 3 << 4);
+ /* disable DQS2,DQS3 tx dll for saving power */
+ clrbits_le32(PHY_REG(phy_base, 0x46), 1 << 3);
+ clrbits_le32(PHY_REG(phy_base, 0x56), 1 << 3);
+ }
+ set_ds_odt(dram, sdram_params);
+ /* deskew */
+ setbits_le32(PHY_REG(phy_base, 2), 8);
+ copy_to_reg(PHY_REG(phy_base, 0xb0),
+ &sdram_params->skew.a0_a1_skew[0], 15 * 4);
+ copy_to_reg(PHY_REG(phy_base, 0x70),
+ &sdram_params->skew.cs0_dm0_skew[0], 44 * 4);
+ copy_to_reg(PHY_REG(phy_base, 0xc0),
+ &sdram_params->skew.cs0_dm1_skew[0], 44 * 4);
+}
+
+static int update_refresh_reg(struct dram_info *dram)
+{
+ void __iomem *pctl_base = dram->pctl;
+ u32 ret;
+
+ ret = readl(pctl_base + DDR_PCTL2_RFSHCTL3) ^ (1 << 1);
+ writel(ret, pctl_base + DDR_PCTL2_RFSHCTL3);
+
+ return 0;
+}
+
+static int data_training(struct dram_info *dram, u32 cs, u32 dramtype)
+{
+ u32 ret;
+ u32 dis_auto_zq = 0;
+ void __iomem *pctl_base = dram->pctl;
+ void __iomem *phy_base = dram->phy;
+
+ /* disable zqcs */
+ if (!(readl(pctl_base + DDR_PCTL2_ZQCTL0) &
+ (1ul << 31))) {
+ dis_auto_zq = 1;
+ setbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1 << 31);
+ }
+ /* disable auto refresh */
+ setbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, 1);
+ update_refresh_reg(dram);
+
+ if (dramtype == DDR4) {
+ clrsetbits_le32(PHY_REG(phy_base, 0x29), 0x3, 0);
+ clrsetbits_le32(PHY_REG(phy_base, 0x39), 0x3, 0);
+ clrsetbits_le32(PHY_REG(phy_base, 0x49), 0x3, 0);
+ clrsetbits_le32(PHY_REG(phy_base, 0x59), 0x3, 0);
+ }
+ /* choose training cs */
+ clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs));
+ /* enable gate training */
+ clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs) | 1);
+ udelay(50);
+ ret = readl(PHY_REG(phy_base, 0xff));
+ /* disable gate training */
+ clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs) | 0);
+ /* restore zqcs */
+ if (dis_auto_zq)
+ clrbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1 << 31);
+ /* restore auto refresh */
+ clrbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, 1);
+ update_refresh_reg(dram);
+
+ if (dramtype == DDR4) {
+ clrsetbits_le32(PHY_REG(phy_base, 0x29), 0x3, 0x2);
+ clrsetbits_le32(PHY_REG(phy_base, 0x39), 0x3, 0x2);
+ clrsetbits_le32(PHY_REG(phy_base, 0x49), 0x3, 0x2);
+ clrsetbits_le32(PHY_REG(phy_base, 0x59), 0x3, 0x2);
+ }
+
+ if (ret & 0x10) {
+ ret = -1;
+ } else {
+ ret = (ret & 0xf) ^ (readl(PHY_REG(phy_base, 0)) >> 4);
+ ret = (ret == 0) ? 0 : -1;
+ }
+ return ret;
+}
+
+/* rank = 1: cs0
+ * rank = 2: cs1
+ * rank = 3: cs0 & cs1
+ * note: be careful of keep mr original val
+ */
+static int write_mr(struct dram_info *dram, u32 rank, u32 mr_num, u32 arg,
+ u32 dramtype)
+{
+ void __iomem *pctl_base = dram->pctl;
+
+ while (readl(pctl_base + DDR_PCTL2_MRSTAT) & MR_WR_BUSY)
+ continue;
+ if (dramtype == DDR3 || dramtype == DDR4) {
+ writel((mr_num << 12) | (rank << 4) | (0 << 0),
+ pctl_base + DDR_PCTL2_MRCTRL0);
+ writel(arg, pctl_base + DDR_PCTL2_MRCTRL1);
+ } else {
+ writel((rank << 4) | (0 << 0),
+ pctl_base + DDR_PCTL2_MRCTRL0);
+ writel((mr_num << 8) | (arg & 0xff),
+ pctl_base + DDR_PCTL2_MRCTRL1);
+ }
+
+ setbits_le32(pctl_base + DDR_PCTL2_MRCTRL0, 1u << 31);
+ while (readl(pctl_base + DDR_PCTL2_MRCTRL0) & (1u << 31))
+ continue;
+ while (readl(pctl_base + DDR_PCTL2_MRSTAT) & MR_WR_BUSY)
+ continue;
+
+ return 0;
+}
+
+/*
+ * rank : 1:cs0, 2:cs1, 3:cs0&cs1
+ * vrefrate: 4500: 45%,
+ */
+static int write_vrefdq(struct dram_info *dram, u32 rank, u32 vrefrate,
+ u32 dramtype)
+{
+ u32 tccd_l, value;
+ u32 dis_auto_zq = 0;
+ void __iomem *pctl_base = dram->pctl;
+
+ if (dramtype != DDR4 || vrefrate < 4500 || vrefrate > 9200)
+ return -1;
+
+ tccd_l = (readl(pctl_base + DDR_PCTL2_DRAMTMG4) >> 16) & 0xf;
+ tccd_l = (tccd_l - 4) << 10;
+
+ if (vrefrate > 7500) {
+ /* range 1 */
+ value = ((vrefrate - 6000) / 65) | tccd_l;
+ } else {
+ /* range 2 */
+ value = ((vrefrate - 4500) / 65) | tccd_l | (1 << 6);
+ }
+
+ /* disable zqcs */
+ if (!(readl(pctl_base + DDR_PCTL2_ZQCTL0) &
+ (1ul << 31))) {
+ dis_auto_zq = 1;
+ setbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1 << 31);
+ }
+ /* disable auto refresh */
+ setbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, 1);
+ update_refresh_reg(dram);
+
+ /* enable vrefdq calibratin */
+ write_mr(dram, rank, 6, value | (1 << 7), dramtype);
+ udelay(1);/* tvrefdqe */
+ /* write vrefdq value */
+ write_mr(dram, rank, 6, value | (1 << 7), dramtype);
+ udelay(1);/* tvref_time */
+ write_mr(dram, rank, 6, value | (0 << 7), dramtype);
+ udelay(1);/* tvrefdqx */
+
+ /* restore zqcs */
+ if (dis_auto_zq)
+ clrbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1 << 31);
+ /* restore auto refresh */
+ clrbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, 1);
+ update_refresh_reg(dram);
+
+ return 0;
+}
+
+#define _MAX_(x, y) ((x) > (y) ? (x) : (y))
+
+static void rx_deskew_switch_adjust(struct dram_info *dram)
+{
+ u32 i, deskew_val;
+ u32 gate_val = 0;
+ void __iomem *phy_base = dram->phy;
+
+ for (i = 0; i < 4; i++)
+ gate_val = _MAX_(readl(PHY_REG(phy_base, 0xfb + i)), gate_val);
+
+ deskew_val = (gate_val >> 3) + 1;
+ deskew_val = (deskew_val > 0x1f) ? 0x1f : deskew_val;
+ clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0xc, (deskew_val & 0x3) << 2);
+ clrsetbits_le32(PHY_REG(phy_base, 0x6f), 0x7 << 4,
+ (deskew_val & 0x1c) << 2);
+}
+
+#undef _MAX_
+
+static void tx_deskew_switch_adjust(struct dram_info *dram)
+{
+ void __iomem *phy_base = dram->phy;
+
+ clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0x3, 1);
+}
+
+static void set_ddrconfig(struct dram_info *dram, u32 ddrconfig)
+{
+ writel(ddrconfig, &dram->msch->ddrconf);
+}
+
+static void dram_all_config(struct dram_info *dram,
+ struct rk3328_sdram_params *sdram_params)
+{
+ u32 sys_reg = 0, tmp = 0;
+
+ set_ddrconfig(dram, sdram_ch.ddrconfig);
+
+ sys_reg |= SYS_REG_ENC_DDRTYPE(sdram_params->dramtype);
+ sys_reg |= SYS_REG_ENC_ROW_3_4(sdram_ch.row_3_4, 0);
+ sys_reg |= SYS_REG_ENC_RANK(sdram_ch.rank, 0);
+ sys_reg |= SYS_REG_ENC_COL(sdram_ch.col, 0);
+ sys_reg |= SYS_REG_ENC_BK(sdram_ch.bk, 0);
+ SYS_REG_ENC_CS0_ROW(sdram_ch.cs0_row, sys_reg, tmp, 0);
+ if (sdram_ch.cs1_row)
+ SYS_REG_ENC_CS1_ROW(sdram_ch.cs1_row, sys_reg, tmp, 0);
+ sys_reg |= SYS_REG_ENC_BW(sdram_ch.bw, 0);
+ sys_reg |= SYS_REG_ENC_DBW(sdram_ch.dbw, 0);
+
+ writel(sys_reg, &dram->grf->os_reg[2]);
+
+ writel(sdram_ch.noc_timings.ddrtiming.d32, &dram->msch->ddrtiming);
+
+ writel(sdram_ch.noc_timings.ddrmode.d32, &dram->msch->ddrmode);
+ writel(sdram_ch.noc_timings.readlatency, &dram->msch->readlatency);
+
+ writel(sdram_ch.noc_timings.activate.d32, &dram->msch->activate);
+ writel(sdram_ch.noc_timings.devtodev.d32, &dram->msch->devtodev);
+ writel(sdram_ch.noc_timings.ddr4timing.d32, &dram->msch->ddr4_timing);
+ writel(sdram_ch.noc_timings.agingx0, &dram->msch->aging0);
+ writel(sdram_ch.noc_timings.agingx0, &dram->msch->aging1);
+ writel(sdram_ch.noc_timings.agingx0, &dram->msch->aging2);
+ writel(sdram_ch.noc_timings.agingx0, &dram->msch->aging3);
+ writel(sdram_ch.noc_timings.agingx0, &dram->msch->aging4);
+ writel(sdram_ch.noc_timings.agingx0, &dram->msch->aging5);
+}
+
+static void enable_low_power(struct dram_info *dram,
+ struct rk3328_sdram_params *sdram_params)
+{
+ void __iomem *pctl_base = dram->pctl;
+
+ /* enable upctl2 axi clock auto gating */
+ writel(0x00800000, &dram->ddr_grf->ddr_grf_con[0]);
+ writel(0x20012001, &dram->ddr_grf->ddr_grf_con[2]);
+ /* enable upctl2 core clock auto gating */
+ writel(0x001e001a, &dram->ddr_grf->ddr_grf_con[2]);
+ /* enable sr, pd */
+ if (PD_IDLE == 0)
+ clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 1));
+ else
+ setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 1));
+ if (SR_IDLE == 0)
+ clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 1);
+ else
+ setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 1);
+ setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 3));
+}
+
+static int sdram_init(struct dram_info *dram,
+ struct rk3328_sdram_params *sdram_params, u32 pre_init)
+{
+ void __iomem *pctl_base = dram->pctl;
+
+ rkclk_ddr_reset(dram, 1, 1, 1, 1);
+ udelay(10);
+ /*
+ * dereset ddr phy psrstn to config pll,
+ * if using phy pll psrstn must be dereset
+ * before config pll
+ */
+ rkclk_ddr_reset(dram, 1, 1, 1, 0);
+ rkclk_configure_ddr(dram, sdram_params);
+ if (pre_init == 0) {
+ switch (sdram_params->dramtype) {
+ case DDR3:
+ printf("DDR3\n");
+ break;
+ case DDR4:
+ printf("DDR4\n");
+ break;
+ case LPDDR3:
+ default:
+ printf("LPDDR3\n");
+ break;
+ }
+ }
+ /* release phy srst to provide clk to ctrl */
+ rkclk_ddr_reset(dram, 1, 1, 0, 0);
+ udelay(10);
+ phy_soft_reset(dram);
+ /* release ctrl presetn, and config ctl registers */
+ rkclk_ddr_reset(dram, 1, 0, 0, 0);
+ pctl_cfg(dram, sdram_params);
+ sdram_ch.ddrconfig = calculate_ddrconfig(sdram_params);
+ set_ctl_address_map(dram, sdram_params);
+ phy_cfg(dram, sdram_params);
+
+ /* enable dfi_init_start to init phy after ctl srstn deassert */
+ setbits_le32(pctl_base + DDR_PCTL2_DFIMISC, (1 << 5) | (1 << 4));
+ rkclk_ddr_reset(dram, 0, 0, 0, 0);
+ /* wait for dfi_init_done and dram init complete */
+ while ((readl(pctl_base + DDR_PCTL2_STAT) & 0x7) == 0)
+ continue;
+
+ /* do ddr gate training */
+ if (data_training(dram, 0, sdram_params->dramtype) != 0) {
+ printf("data training error\n");
+ return -1;
+ }
+
+ if (sdram_params->dramtype == DDR4)
+ write_vrefdq(dram, 0x3, 5670, sdram_params->dramtype);
+
+ if (pre_init == 0) {
+ rx_deskew_switch_adjust(dram);
+ tx_deskew_switch_adjust(dram);
+ }
+
+ dram_all_config(dram, sdram_params);
+ enable_low_power(dram, sdram_params);
+
+ return 0;
+}
+
+static u64 dram_detect_cap(struct dram_info *dram,
+ struct rk3328_sdram_params *sdram_params,
+ unsigned char channel)
+{
+ void __iomem *pctl_base = dram->pctl;
+
+ /*
+ * for ddr3: ddrconf = 3
+ * for ddr4: ddrconf = 12
+ * for lpddr3: ddrconf = 3
+ * default bw = 1
+ */
+ u32 bk, bktmp;
+ u32 col, coltmp;
+ u32 row, rowtmp, row_3_4;
+ void __iomem *test_addr, *test_addr1;
+ u32 dbw;
+ u32 cs;
+ u32 bw = 1;
+ u64 cap = 0;
+ u32 dram_type = sdram_params->dramtype;
+ u32 pwrctl;
+
+ if (dram_type != DDR4) {
+ /* detect col and bk for ddr3/lpddr3 */
+ coltmp = 12;
+ bktmp = 3;
+ rowtmp = 16;
+
+ for (col = coltmp; col >= 9; col -= 1) {
+ writel(0, SDRAM_ADDR);
+ test_addr = (void __iomem *)(SDRAM_ADDR +
+ (1ul << (col + bw - 1ul)));
+ writel(PATTERN, test_addr);
+ if ((readl(test_addr) == PATTERN) &&
+ (readl(SDRAM_ADDR) == 0))
+ break;
+ }
+ if (col == 8) {
+ printf("col error\n");
+ goto cap_err;
+ }
+
+ test_addr = (void __iomem *)(SDRAM_ADDR +
+ (1ul << (coltmp + bktmp + bw - 1ul)));
+ writel(0, SDRAM_ADDR);
+ writel(PATTERN, test_addr);
+ if ((readl(test_addr) == PATTERN) &&
+ (readl(SDRAM_ADDR) == 0))
+ bk = 3;
+ else
+ bk = 2;
+ if (dram_type == LPDDR3)
+ dbw = 2;
+ else
+ dbw = 1;
+ } else {
+ /* detect bg for ddr4 */
+ coltmp = 10;
+ bktmp = 4;
+ rowtmp = 17;
+
+ col = 10;
+ bk = 2;
+ test_addr = (void __iomem *)(SDRAM_ADDR +
+ (1ul << (coltmp + bw + 1ul)));
+ writel(0, SDRAM_ADDR);
+ writel(PATTERN, test_addr);
+ if ((readl(test_addr) == PATTERN) &&
+ (readl(SDRAM_ADDR) == 0))
+ dbw = 0;
+ else
+ dbw = 1;
+ }
+ /* detect row */
+ for (row = rowtmp; row > 12; row--) {
+ writel(0, SDRAM_ADDR);
+ test_addr = (void __iomem *)(SDRAM_ADDR +
+ (1ul << (row + bktmp + coltmp + bw - 1ul)));
+ writel(PATTERN, test_addr);
+ if ((readl(test_addr) == PATTERN) &&
+ (readl(SDRAM_ADDR) == 0))
+ break;
+ }
+ if (row == 12) {
+ printf("row error");
+ goto cap_err;
+ }
+ /* detect row_3_4 */
+ test_addr = SDRAM_ADDR;
+ test_addr1 = (void __iomem *)(SDRAM_ADDR +
+ (0x3ul << (row + bktmp + coltmp + bw - 1ul - 1ul)));
+
+ writel(0, test_addr);
+ writel(PATTERN, test_addr1);
+ if ((readl(test_addr) == 0) &&
+ (readl(test_addr1) == PATTERN))
+ row_3_4 = 0;
+ else
+ row_3_4 = 1;
+
+ /* disable auto low-power */
+ pwrctl = readl(pctl_base + DDR_PCTL2_PWRCTL);
+ writel(0, pctl_base + DDR_PCTL2_PWRCTL);
+
+ /* bw and cs detect using phy read gate training */
+ if (data_training(dram, 1, dram_type) == 0)
+ cs = 1;
+ else
+ cs = 0;
+
+ bw = 2;
+
+ /* restore auto low-power */
+ writel(pwrctl, pctl_base + DDR_PCTL2_PWRCTL);
+
+ sdram_ch.rank = cs + 1;
+ sdram_ch.col = col;
+ sdram_ch.bk = bk;
+ sdram_ch.dbw = dbw;
+ sdram_ch.bw = bw;
+ sdram_ch.cs0_row = row;
+ if (cs)
+ sdram_ch.cs1_row = row;
+ else
+ sdram_ch.cs1_row = 0;
+ sdram_ch.row_3_4 = row_3_4;
+
+ if (dram_type == DDR4)
+ cap = 1llu << (cs + row + bk + col + ((dbw == 0) ? 2 : 1) + bw);
+ else
+ cap = 1llu << (cs + row + bk + col + bw);
+
+ return cap;
+
+cap_err:
+ return 0;
+}
+
+static u32 remodify_sdram_params(struct rk3328_sdram_params *sdram_params)
+{
+ u32 tmp = 0, tmp_adr = 0, i;
+
+ for (i = 0; sdram_params->pctl_regs.pctl[i][0] != 0xFFFFFFFF; i++) {
+ if (sdram_params->pctl_regs.pctl[i][0] == 0) {
+ tmp = sdram_params->pctl_regs.pctl[i][1];/* MSTR */
+ tmp_adr = i;
+ }
+ }
+
+ tmp &= ~((3ul << 30) | (3ul << 24) | (3ul << 12));
+
+ switch (sdram_ch.dbw) {
+ case 2:
+ tmp |= (3ul << 30);
+ break;
+ case 1:
+ tmp |= (2ul << 30);
+ break;
+ case 0:
+ default:
+ tmp |= (1ul << 30);
+ break;
+ }
+
+ if (sdram_ch.rank == 2)
+ tmp |= 3 << 24;
+ else
+ tmp |= 1 << 24;
+
+ tmp |= (2 - sdram_ch.bw) << 12;
+
+ sdram_params->pctl_regs.pctl[tmp_adr][1] = tmp;
+
+ if (sdram_ch.bw == 2)
+ sdram_ch.noc_timings.ddrtiming.b.bwratio = 0;
+ else
+ sdram_ch.noc_timings.ddrtiming.b.bwratio = 1;
+
+ return 0;
+}
+
+static int dram_detect_cs1_row(struct rk3328_sdram_params *sdram_params,
+ unsigned char channel)
+{
+ u32 ret = 0;
+ u32 cs1_bit;
+ void __iomem *test_addr, *cs1_addr;
+ u32 row, bktmp, coltmp, bw;
+ u32 ddrconf = sdram_ch.ddrconfig;
+
+ if (sdram_ch.rank == 2) {
+ cs1_bit = addrmap[ddrconf][0] + 8;
+
+ if (cs1_bit > 31)
+ goto out;
+
+ cs1_addr = (void __iomem *)(1ul << cs1_bit);
+ if (cs1_bit < 20)
+ cs1_bit = 1;
+ else
+ cs1_bit = 0;
+
+ if (sdram_params->dramtype == DDR4) {
+ if (sdram_ch.dbw == 0)
+ bktmp = sdram_ch.bk + 2;
+ else
+ bktmp = sdram_ch.bk + 1;
+ } else {
+ bktmp = sdram_ch.bk;
+ }
+ bw = sdram_ch.bw;
+ coltmp = sdram_ch.col;
+
+ /* detect cs1 row */
+ for (row = sdram_ch.cs0_row; row > 12; row--) {
+ test_addr = (void __iomem *)(SDRAM_ADDR + cs1_addr +
+ (1ul << (row + cs1_bit + bktmp +
+ coltmp + bw - 1ul)));
+ writel(0, SDRAM_ADDR + cs1_addr);
+ writel(PATTERN, test_addr);
+ if ((readl(test_addr) == PATTERN) &&
+ (readl(SDRAM_ADDR + cs1_addr) == 0)) {
+ ret = row;
+ break;
+ }
+ }
+ }
+
+out:
+ return ret;
+}
+
+static int sdram_init_detect(struct dram_info *dram,
+ struct rk3328_sdram_params *sdram_params)
+{
+ debug("Starting SDRAM initialization...\n");
+
+ memcpy(&sdram_ch, &sdram_params->ch,
+ sizeof(struct rk3328_sdram_channel));
+
+ sdram_init(dram, sdram_params, 1);
+ dram_detect_cap(dram, sdram_params, 0);
+
+ /* modify bw, cs related timing */
+ remodify_sdram_params(sdram_params);
+ /* reinit sdram by real dram cap */
+ sdram_init(dram, sdram_params, 0);
+
+ /* redetect cs1 row */
+ sdram_ch.cs1_row =
+ dram_detect_cs1_row(sdram_params, 0);
+
+ return 0;
+}
+
+static int rk3328_dmc_init(struct udevice *dev)
+{
+ struct dram_info *priv = dev_get_priv(dev);
+ struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
+ int ret;
+
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct rk3328_sdram_params *params = &plat->sdram_params;
+#else
+ struct dtd_rockchip_rk3328_dmc *dtplat = &plat->dtplat;
+ struct rk3328_sdram_params *params =
+ (void *)dtplat->rockchip_sdram_params;
+
+ ret = conv_of_platdata(dev);
+ if (ret)
+ return ret;
+#endif
+ priv->phy = regmap_get_range(plat->map, 0);
+ priv->pctl = regmap_get_range(plat->map, 1);
+ priv->grf = regmap_get_range(plat->map, 2);
+ priv->cru = regmap_get_range(plat->map, 3);
+ priv->msch = regmap_get_range(plat->map, 4);
+ priv->ddr_grf = regmap_get_range(plat->map, 5);
+
+ debug("%s phy %p pctrl %p grf %p cru %p msch %p ddr_grf %p\n",
+ __func__, priv->phy, priv->pctl, priv->grf, priv->cru,
+ priv->msch, priv->ddr_grf);
+ ret = sdram_init_detect(priv, params);
+ if (ret < 0) {
+ printf("%s DRAM init failed%d\n", __func__, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int rk3328_dmc_ofdata_to_platdata(struct udevice *dev)
+{
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
+ int ret;
+
+ ret = dev_read_u32_array(dev, "rockchip,sdram-params",
+ (u32 *)&plat->sdram_params,
+ sizeof(plat->sdram_params) / sizeof(u32));
+ if (ret) {
+ printf("%s: Cannot read rockchip,sdram-params %d\n",
+ __func__, ret);
+ return ret;
+ }
+ ret = regmap_init_mem(dev, &plat->map);
+ if (ret)
+ printf("%s: regmap failed %d\n", __func__, ret);
+#endif
+ return 0;
+}
+
+#endif
+
static int rk3328_dmc_probe(struct udevice *dev)
{
+#ifdef CONFIG_TPL_BUILD
+ if (rk3328_dmc_init(dev))
+ return 0;
+#else
struct dram_info *priv = dev_get_priv(dev);
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
@@ -25,7 +1032,7 @@
priv->info.base = CONFIG_SYS_SDRAM_BASE;
priv->info.size = rockchip_sdram_size(
(phys_addr_t)&priv->grf->os_reg[2]);
-
+#endif
return 0;
}
@@ -42,7 +1049,6 @@
.get_info = rk3328_dmc_get_info,
};
-
static const struct udevice_id rk3328_dmc_ids[] = {
{ .compatible = "rockchip,rk3328-dmc" },
{ }
@@ -53,6 +1059,12 @@
.id = UCLASS_RAM,
.of_match = rk3328_dmc_ids,
.ops = &rk3328_dmc_ops,
+#ifdef CONFIG_TPL_BUILD
+ .ofdata_to_platdata = rk3328_dmc_ofdata_to_platdata,
+#endif
.probe = rk3328_dmc_probe,
.priv_auto_alloc_size = sizeof(struct dram_info),
+#ifdef CONFIG_TPL_BUILD
+ .platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat),
+#endif
};
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index e009113..ed70137 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1444,7 +1444,6 @@
if (info->cap_info.cs1_row)
SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, sys_reg2,
sys_reg3, channel);
-
sys_reg3 |= SYS_REG_ENC_CS1_COL(info->cap_info.col, channel);
sys_reg3 |= SYS_REG_ENC_VERSION(DDR_SYS_REG_VERSION);
@@ -1489,6 +1488,84 @@
clrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3);
}
+static void set_cap_relate_config(const struct chan_info *chan,
+ struct rk3399_sdram_params *params,
+ unsigned int channel)
+{
+ u32 *denali_ctl = chan->pctl->denali_ctl;
+ u32 tmp;
+ struct rk3399_msch_timings *noc_timing;
+
+ if (params->base.dramtype == LPDDR3) {
+ tmp = (8 << params->ch[channel].cap_info.bw) /
+ (8 << params->ch[channel].cap_info.dbw);
+
+ /**
+ * memdata_ratio
+ * 1 -> 0, 2 -> 1, 4 -> 2
+ */
+ clrsetbits_le32(&denali_ctl[197], 0x7,
+ (tmp >> 1));
+ clrsetbits_le32(&denali_ctl[198], 0x7 << 8,
+ (tmp >> 1) << 8);
+ }
+
+ noc_timing = ¶ms->ch[channel].noc_timings;
+
+ /*
+ * noc timing bw relate timing is 32 bit, and real bw is 16bit
+ * actually noc reg is setting at function dram_all_config
+ */
+ if (params->ch[channel].cap_info.bw == 16 &&
+ noc_timing->ddrmode.b.mwrsize == 2) {
+ if (noc_timing->ddrmode.b.burstsize)
+ noc_timing->ddrmode.b.burstsize -= 1;
+ noc_timing->ddrmode.b.mwrsize -= 1;
+ noc_timing->ddrtimingc0.b.burstpenalty *= 2;
+ noc_timing->ddrtimingc0.b.wrtomwr *= 2;
+ }
+}
+
+static u32 calculate_ddrconfig(struct rk3399_sdram_params *params, u32 channel)
+{
+ unsigned int cs0_row = params->ch[channel].cap_info.cs0_row;
+ unsigned int col = params->ch[channel].cap_info.col;
+ unsigned int bw = params->ch[channel].cap_info.bw;
+ u16 ddr_cfg_2_rbc[] = {
+ /*
+ * [6] highest bit col
+ * [5:3] max row(14+n)
+ * [2] insertion row
+ * [1:0] col(9+n),col, data bus 32bit
+ *
+ * highbitcol, max_row, insertion_row, col
+ */
+ ((0 << 6) | (2 << 3) | (0 << 2) | 0), /* 0 */
+ ((0 << 6) | (2 << 3) | (0 << 2) | 1), /* 1 */
+ ((0 << 6) | (1 << 3) | (0 << 2) | 2), /* 2 */
+ ((0 << 6) | (0 << 3) | (0 << 2) | 3), /* 3 */
+ ((0 << 6) | (2 << 3) | (1 << 2) | 1), /* 4 */
+ ((0 << 6) | (1 << 3) | (1 << 2) | 2), /* 5 */
+ ((1 << 6) | (0 << 3) | (0 << 2) | 2), /* 6 */
+ ((1 << 6) | (1 << 3) | (0 << 2) | 2), /* 7 */
+ };
+ u32 i;
+
+ col -= (bw == 2) ? 0 : 1;
+ col -= 9;
+
+ for (i = 0; i < 4; i++) {
+ if ((col == (ddr_cfg_2_rbc[i] & 0x3)) &&
+ (cs0_row <= (((ddr_cfg_2_rbc[i] >> 3) & 0x7) + 14)))
+ break;
+ }
+
+ if (i >= 4)
+ i = -EINVAL;
+
+ return i;
+}
+
#if !defined(CONFIG_RAM_RK3399_LPDDR4)
static int default_data_training(struct dram_info *dram, u32 channel, u8 rank,
struct rk3399_sdram_params *params)
@@ -1589,84 +1666,6 @@
rk_clrsetreg(&pmusgrf->soc_con4, 0x1f << 10, stride << 10);
}
-static void set_cap_relate_config(const struct chan_info *chan,
- struct rk3399_sdram_params *params,
- unsigned int channel)
-{
- u32 *denali_ctl = chan->pctl->denali_ctl;
- u32 tmp;
- struct rk3399_msch_timings *noc_timing;
-
- if (params->base.dramtype == LPDDR3) {
- tmp = (8 << params->ch[channel].cap_info.bw) /
- (8 << params->ch[channel].cap_info.dbw);
-
- /**
- * memdata_ratio
- * 1 -> 0, 2 -> 1, 4 -> 2
- */
- clrsetbits_le32(&denali_ctl[197], 0x7,
- (tmp >> 1));
- clrsetbits_le32(&denali_ctl[198], 0x7 << 8,
- (tmp >> 1) << 8);
- }
-
- noc_timing = ¶ms->ch[channel].noc_timings;
-
- /*
- * noc timing bw relate timing is 32 bit, and real bw is 16bit
- * actually noc reg is setting at function dram_all_config
- */
- if (params->ch[channel].cap_info.bw == 16 &&
- noc_timing->ddrmode.b.mwrsize == 2) {
- if (noc_timing->ddrmode.b.burstsize)
- noc_timing->ddrmode.b.burstsize -= 1;
- noc_timing->ddrmode.b.mwrsize -= 1;
- noc_timing->ddrtimingc0.b.burstpenalty *= 2;
- noc_timing->ddrtimingc0.b.wrtomwr *= 2;
- }
-}
-
-static u32 calculate_ddrconfig(struct rk3399_sdram_params *params, u32 channel)
-{
- unsigned int cs0_row = params->ch[channel].cap_info.cs0_row;
- unsigned int col = params->ch[channel].cap_info.col;
- unsigned int bw = params->ch[channel].cap_info.bw;
- u16 ddr_cfg_2_rbc[] = {
- /*
- * [6] highest bit col
- * [5:3] max row(14+n)
- * [2] insertion row
- * [1:0] col(9+n),col, data bus 32bit
- *
- * highbitcol, max_row, insertion_row, col
- */
- ((0 << 6) | (2 << 3) | (0 << 2) | 0), /* 0 */
- ((0 << 6) | (2 << 3) | (0 << 2) | 1), /* 1 */
- ((0 << 6) | (1 << 3) | (0 << 2) | 2), /* 2 */
- ((0 << 6) | (0 << 3) | (0 << 2) | 3), /* 3 */
- ((0 << 6) | (2 << 3) | (1 << 2) | 1), /* 4 */
- ((0 << 6) | (1 << 3) | (1 << 2) | 2), /* 5 */
- ((1 << 6) | (0 << 3) | (0 << 2) | 2), /* 6 */
- ((1 << 6) | (1 << 3) | (0 << 2) | 2), /* 7 */
- };
- u32 i;
-
- col -= (bw == 2) ? 0 : 1;
- col -= 9;
-
- for (i = 0; i < 4; i++) {
- if ((col == (ddr_cfg_2_rbc[i] & 0x3)) &&
- (cs0_row <= (((ddr_cfg_2_rbc[i] >> 3) & 0x7) + 14)))
- break;
- }
-
- if (i >= 4)
- i = -EINVAL;
-
- return i;
-}
-
/**
* read mr_num mode register
* rank = 1: cs0
@@ -2328,7 +2327,7 @@
struct rk3399_sdram_params *params, u32 ctl, u32 hz)
{
u32 channel;
- int ret_clk, ret[2];
+ int ret_clk, ret;
/* cci idle req stall */
writel(0x70007, &dram->grf->soc_con0);
@@ -2371,13 +2370,9 @@
for (channel = 0; channel < 2; channel++) {
if (!(params->ch[channel].cap_info.col))
continue;
- ret[channel] = data_training(dram, channel, params,
+ ret = data_training(dram, channel, params,
PI_FULL_TRAINING);
- }
- for (channel = 0; channel < 2; channel++) {
- if (!(params->ch[channel].cap_info.col))
- continue;
- if (ret[channel])
+ if (ret)
printf("%s: channel %d training failed!\n",
__func__, channel);
else
@@ -2569,6 +2564,7 @@
for (channel = 0; channel < 2; channel++) {
const struct chan_info *chan = &dram->chan[channel];
struct sdram_cap_info *cap_info = ¶ms->ch[channel].cap_info;
+ u8 training_flag = PI_FULL_TRAINING;
if (cap_info->rank == 0) {
clear_channel_params(params, channel);
@@ -2580,9 +2576,27 @@
debug("Channel ");
debug(channel ? "1: " : "0: ");
+ /* LPDDR3 should have write and read gate training */
+ if (params->base.dramtype == LPDDR3)
+ training_flag = PI_WRITE_LEVELING |
+ PI_READ_GATE_TRAINING;
+
+ if (params->base.dramtype != LPDDR4) {
+ ret = data_training(dram, channel, params,
+ training_flag);
+ if (!ret) {
+ debug("%s: data train failed for channel %d\n",
+ __func__, ret);
+ continue;
+ }
+ }
+
sdram_print_ddr_info(cap_info, ¶ms->base);
+ set_memory_map(chan, channel, params);
+ cap_info->ddrconfig = calculate_ddrconfig(params, channel);
set_ddrconfig(chan, params, channel, cap_info->ddrconfig);
+ set_cap_relate_config(chan, params, channel);
}
if (params->base.num_channels == 0) {
diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.h b/drivers/ram/stm32mp1/stm32mp1_ddr.h
index a8eed89..52b748f 100644
--- a/drivers/ram/stm32mp1/stm32mp1_ddr.h
+++ b/drivers/ram/stm32mp1/stm32mp1_ddr.h
@@ -197,10 +197,6 @@
char *name,
char *string);
-void stm32mp1_dump_info(
- const struct ddr_info *priv,
- const struct stm32mp1_ddr_config *config);
-
bool stm32mp1_ddr_interactive(
void *priv,
enum stm32mp1_ddr_interact_step step,
diff --git a/drivers/ram/stm32mp1/stm32mp1_ram.c b/drivers/ram/stm32mp1/stm32mp1_ram.c
index 84e39d0..a362cf9 100644
--- a/drivers/ram/stm32mp1/stm32mp1_ram.c
+++ b/drivers/ram/stm32mp1/stm32mp1_ram.c
@@ -26,7 +26,7 @@
unsigned long ddr_clk;
struct clk clk;
int ret;
- int idx;
+ unsigned int idx;
for (idx = 0; idx < ARRAY_SIZE(clkname); idx++) {
ret = clk_get_by_name(priv->dev, clkname[idx], &clk);
@@ -59,7 +59,8 @@
static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
{
struct ddr_info *priv = dev_get_priv(dev);
- int ret, idx;
+ int ret;
+ unsigned int idx;
struct clk axidcg;
struct stm32mp1_ddr_config config;
diff --git a/drivers/ram/stm32mp1/stm32mp1_tests.c b/drivers/ram/stm32mp1/stm32mp1_tests.c
index b6fb2a9..581ee48 100644
--- a/drivers/ram/stm32mp1/stm32mp1_tests.c
+++ b/drivers/ram/stm32mp1/stm32mp1_tests.c
@@ -4,6 +4,7 @@
*/
#include <common.h>
#include <console.h>
+#include <watchdog.h>
#include <asm/io.h>
#include <linux/log2.h>
#include "stm32mp1_tests.h"
@@ -154,6 +155,8 @@
return 1;
}
printf("loop #%d\n", *loop);
+ WATCHDOG_RESET();
+
return 0;
}
@@ -578,27 +581,29 @@
u32 error = 0;
unsigned int seed;
- if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024))
+ if (get_bufsize(string, argc, argv, 0, &bufsize, 8 * 1024))
return TEST_ERROR;
if (get_nb_loop(string, argc, argv, 1, &nb_loop, 1))
return TEST_ERROR;
if (get_addr(string, argc, argv, 2, &addr))
return TEST_ERROR;
- printf("running %d loops at 0x%x\n", nb_loop, addr);
+ bufsize /= 2;
+ printf("running %d loops copy from 0x%x to 0x%x (buffer size=0x%x)\n",
+ nb_loop, addr, addr + bufsize, bufsize);
while (!error) {
seed = rand();
- for (offset = addr; offset < addr + bufsize; offset += 4)
- writel(rand(), offset);
+ for (offset = 0; offset < bufsize; offset += 4)
+ writel(rand(), addr + offset);
memcpy((void *)addr + bufsize, (void *)addr, bufsize);
srand(seed);
- for (offset = addr; offset < addr + 2 * bufsize; offset += 4) {
- if (offset == (addr + bufsize))
+ for (offset = 0; offset < 2 * bufsize; offset += 4) {
+ if (offset == bufsize)
srand(seed);
value = rand();
- error = check_addr(offset, value);
+ error = check_addr(addr + offset, value);
if (error)
break;
if (progress(offset))
@@ -607,6 +612,7 @@
if (test_loop_end(&loop, nb_loop, 100))
break;
}
+ putc('\n');
if (error) {
sprintf(string,
@@ -791,9 +797,9 @@
int i;
int j;
enum test_result res = TEST_PASSED;
- u32 *offset, testsize, remaining;
+ u32 offset, testsize, remaining;
- offset = address;
+ offset = (u32)address;
remaining = bufsize;
while (remaining) {
testsize = bufsize > 0x1000000 ? 0x1000000 : bufsize;
@@ -809,7 +815,7 @@
__asm__("stmia r1!, {R3-R10}");
__asm__("stmia r1!, {R3-R10}");
__asm__("stmia r1!, {R3-R10}");
- __asm__("subs r2, r2, #8");
+ __asm__("subs r2, r2, #128");
__asm__("bge loop2");
__asm__("pop {R0-R10}");
@@ -1238,27 +1244,38 @@
u32 *addr;
u32 data;
u32 loop = 0;
+ int i, size = 1024 * 1024;
bool random = false;
if (get_addr(string, argc, argv, 0, (u32 *)&addr))
return TEST_ERROR;
- if ((u32)addr == ADDR_INVALID) {
- printf("random ");
- random = true;
- }
+ if (get_pattern(string, argc, argv, 1, &data, 0xA5A5AA55))
+ return TEST_ERROR;
- printf("running at 0x%08x\n", (u32)addr);
+ if ((u32)addr == ADDR_INVALID) {
+ printf("running random\n");
+ random = true;
+ } else {
+ printf("running at 0x%08x with pattern=0x%08x\n",
+ (u32)addr, data);
+ writel(data, addr);
+ }
while (1) {
- if (random)
- addr = (u32 *)(STM32_DDR_BASE +
- (rand() & (STM32_DDR_SIZE - 1) & ~0x3));
- data = readl(addr);
- if (test_loop_end(&loop, 0, 1000))
+ for (i = 0; i < size; i++) {
+ if (random)
+ addr = (u32 *)(STM32_DDR_BASE +
+ (rand() & (STM32_DDR_SIZE - 1) & ~0x3));
+ data = readl(addr);
+ }
+ if (test_loop_end(&loop, 0, 1))
break;
}
- sprintf(string, "0x%x: %x", (u32)addr, data);
+ if (random)
+ sprintf(string, "%d loops random", loop);
+ else
+ sprintf(string, "%d loops at 0x%x: %x", loop, (u32)addr, data);
return TEST_PASSED;
}
@@ -1275,31 +1292,41 @@
char *string, int argc, char *argv[])
{
u32 *addr;
- u32 data = 0xA5A5AA55;
+ u32 data;
u32 loop = 0;
+ int i, size = 1024 * 1024;
bool random = false;
if (get_addr(string, argc, argv, 0, (u32 *)&addr))
return TEST_ERROR;
- if ((u32)addr == ADDR_INVALID) {
- printf("random ");
- random = true;
- }
+ if (get_pattern(string, argc, argv, 1, &data, 0xA5A5AA55))
+ return TEST_ERROR;
- printf("running at 0x%08x\n", (u32)addr);
+ if ((u32)addr == ADDR_INVALID) {
+ printf("running random\n");
+ random = true;
+ } else {
+ printf("running at 0x%08x with pattern 0x%08x\n",
+ (u32)addr, data);
+ }
while (1) {
- if (random) {
- addr = (u32 *)(STM32_DDR_BASE +
- (rand() & (STM32_DDR_SIZE - 1) & ~0x3));
- data = rand();
+ for (i = 0; i < size; i++) {
+ if (random) {
+ addr = (u32 *)(STM32_DDR_BASE +
+ (rand() & (STM32_DDR_SIZE - 1) & ~0x3));
+ data = rand();
+ }
+ writel(data, addr);
}
- writel(data, addr);
- if (test_loop_end(&loop, 0, 1000))
+ if (test_loop_end(&loop, 0, 1))
break;
}
- sprintf(string, "0x%x: %x", (u32)addr, data);
+ if (random)
+ sprintf(string, "%d loops random", loop);
+ else
+ sprintf(string, "%d loops at 0x%x: %x", loop, (u32)addr, data);
return TEST_PASSED;
}
@@ -1388,7 +1415,7 @@
"Verifies r/w and memcopy(burst for pseudo random value.",
3
},
- {test_freq_pattern, "FrequencySelectivePattern ", "[size]",
+ {test_freq_pattern, "FrequencySelectivePattern", "[size]",
"write & test patterns: Mostly Zero, Mostly One and F/n",
1
},
@@ -1417,10 +1444,10 @@
3
},
/* need to the the 2 last one (infinite) : skipped for test all */
- {test_read, "infinite read", "[addr]",
- "basic test : infinite read access", 1},
- {test_write, "infinite write", "[addr]",
- "basic test : infinite write access", 1},
+ {test_read, "infinite read", "[addr] [pattern]",
+ "basic test : infinite read access (random: addr=0xFFFFFFFF)", 2},
+ {test_write, "infinite write", "[addr] [pattern]",
+ "basic test : infinite write access (random: addr=0xFFFFFFFF)", 2},
};
const int test_nb = ARRAY_SIZE(test);
diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig
index 9eb532b..f54a245 100644
--- a/drivers/remoteproc/Kconfig
+++ b/drivers/remoteproc/Kconfig
@@ -22,15 +22,6 @@
help
Say 'y' here to add support for TI' K3 System Controller.
-config REMOTEPROC_K3
- bool "Support for TI's K3 based remoteproc driver"
- select REMOTEPROC
- depends on DM
- depends on ARCH_K3
- depends on OF_CONTROL
- help
- Say 'y' here to add support for TI' K3 remoteproc driver.
-
config REMOTEPROC_SANDBOX
bool "Support for Test processor for Sandbox"
select REMOTEPROC
@@ -40,6 +31,27 @@
Say 'y' here to add support for test processor which does dummy
operations for sandbox platform.
+config REMOTEPROC_STM32_COPRO
+ bool "Support for STM32 coprocessor"
+ select REMOTEPROC
+ depends on DM
+ depends on ARCH_STM32MP
+ depends on OF_CONTROL
+ help
+ Say 'y' here to add support for STM32 Cortex-M4 coprocessors via the
+ remoteproc framework.
+
+config REMOTEPROC_TI_K3_ARM64
+ bool "Support for TI's K3 based ARM64 remoteproc driver"
+ select REMOTEPROC
+ depends on DM
+ depends on ARCH_K3
+ depends on OF_CONTROL
+ help
+ Say y here to support TI's ARM64 processor subsystems
+ on various TI K3 family of SoCs through the remote processor
+ framework.
+
config REMOTEPROC_TI_POWER
bool "Support for TI Power processor"
select REMOTEPROC
diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile
index 77eb708..271ba55 100644
--- a/drivers/remoteproc/Makefile
+++ b/drivers/remoteproc/Makefile
@@ -4,10 +4,11 @@
# Texas Instruments Incorporated - http://www.ti.com/
#
-obj-$(CONFIG_$(SPL_)REMOTEPROC) += rproc-uclass.o
+obj-$(CONFIG_$(SPL_)REMOTEPROC) += rproc-uclass.o rproc-elf-loader.o
# Remote proc drivers - Please keep this list alphabetically sorted.
obj-$(CONFIG_K3_SYSTEM_CONTROLLER) += k3_system_controller.o
-obj-$(CONFIG_REMOTEPROC_K3) += k3_rproc.o
obj-$(CONFIG_REMOTEPROC_SANDBOX) += sandbox_testproc.o
+obj-$(CONFIG_REMOTEPROC_STM32_COPRO) += stm32_copro.o
+obj-$(CONFIG_REMOTEPROC_TI_K3_ARM64) += ti_k3_arm64_rproc.o
obj-$(CONFIG_REMOTEPROC_TI_POWER) += ti_power_proc.o
diff --git a/drivers/remoteproc/k3_rproc.c b/drivers/remoteproc/k3_rproc.c
deleted file mode 100644
index 3c29d92..0000000
--- a/drivers/remoteproc/k3_rproc.c
+++ /dev/null
@@ -1,244 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Texas Instruments' K3 Remoteproc driver
- *
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
- * Lokesh Vutla <lokeshvutla@ti.com>
- *
- */
-
-#include <common.h>
-#include <dm.h>
-#include <remoteproc.h>
-#include <errno.h>
-#include <clk.h>
-#include <reset.h>
-#include <asm/io.h>
-#include <power-domain.h>
-#include <linux/soc/ti/ti_sci_protocol.h>
-
-#define INVALID_ID 0xffff
-
-#define GTC_CNTCR_REG 0x0
-#define GTC_CNTR_EN 0x3
-
-/**
- * struct k3_rproc_privdata - Structure representing Remote processor data.
- * @rproc_pwrdmn: rproc power domain data
- * @rproc_rst: rproc reset control data
- * @sci: Pointer to TISCI handle
- * @gtc_base: Timer base address.
- * @proc_id: TISCI processor ID
- * @host_id: TISCI host id to which the processor gets assigned to.
- */
-struct k3_rproc_privdata {
- struct power_domain rproc_pwrdmn;
- struct power_domain gtc_pwrdmn;
- struct reset_ctl rproc_rst;
- const struct ti_sci_handle *sci;
- void *gtc_base;
- u16 proc_id;
- u16 host_id;
-};
-
-/**
- * k3_rproc_load() - Load up the Remote processor image
- * @dev: rproc device pointer
- * @addr: Address at which image is available
- * @size: size of the image
- *
- * Return: 0 if all goes good, else appropriate error message.
- */
-static int k3_rproc_load(struct udevice *dev, ulong addr, ulong size)
-{
- struct k3_rproc_privdata *rproc = dev_get_priv(dev);
- const struct ti_sci_proc_ops *pops = &rproc->sci->ops.proc_ops;
- int ret;
-
- dev_dbg(dev, "%s addr = 0x%lx, size = 0x%lx\n", __func__, addr, size);
-
- /* request for the processor */
- ret = pops->proc_request(rproc->sci, rproc->proc_id);
- if (ret) {
- dev_err(dev, "Requesting processor failed %d\n", ret);
- return ret;
- }
-
- ret = pops->set_proc_boot_cfg(rproc->sci, rproc->proc_id, addr, 0, 0);
- if (ret) {
- dev_err(dev, "set_proc_boot_cfg failed %d\n", ret);
- return ret;
- }
-
- dev_dbg(dev, "%s: rproc successfully loaded\n", __func__);
-
- return 0;
-}
-
-/**
- * k3_rproc_start() - Start the remote processor
- * @dev: rproc device pointer
- *
- * Return: 0 if all went ok, else return appropriate error
- */
-static int k3_rproc_start(struct udevice *dev)
-{
- struct k3_rproc_privdata *rproc = dev_get_priv(dev);
- const struct ti_sci_proc_ops *pops = &rproc->sci->ops.proc_ops;
- int ret;
-
- dev_dbg(dev, "%s\n", __func__);
-
- ret = power_domain_on(&rproc->gtc_pwrdmn);
- if (ret) {
- dev_err(dev, "power_domain_on() failed: %d\n", ret);
- return ret;
- }
-
- /* Enable the timer before starting remote core */
- writel(GTC_CNTR_EN, rproc->gtc_base + GTC_CNTCR_REG);
-
- /*
- * Setting the right clock frequency would have taken care by
- * assigned-clock-rates during the device probe. So no need to
- * set the frequency again here.
- */
- ret = power_domain_on(&rproc->rproc_pwrdmn);
- if (ret) {
- dev_err(dev, "power_domain_on() failed: %d\n", ret);
- return ret;
- }
-
- if (rproc->host_id != INVALID_ID) {
- ret = pops->proc_handover(rproc->sci, rproc->proc_id,
- rproc->host_id);
- if (ret) {
- dev_err(dev, "Handover processor failed %d\n", ret);
- return ret;
- }
- } else {
- ret = pops->proc_release(rproc->sci, rproc->proc_id);
- if (ret) {
- dev_err(dev, "Processor release failed %d\n", ret);
- return ret;
- }
- }
-
- dev_dbg(dev, "%s: rproc successfully started\n", __func__);
-
- return 0;
-}
-
-/**
- * k3_rproc_init() - Initialize the remote processor
- * @dev: rproc device pointer
- *
- * Return: 0 if all went ok, else return appropriate error
- */
-static int k3_rproc_init(struct udevice *dev)
-{
- dev_dbg(dev, "%s\n", __func__);
-
- /* Enable the module */
- dev_dbg(dev, "%s: rproc successfully initialized\n", __func__);
-
- return 0;
-}
-
-static const struct dm_rproc_ops k3_rproc_ops = {
- .init = k3_rproc_init,
- .load = k3_rproc_load,
- .start = k3_rproc_start,
-};
-
-/**
- * k3_of_to_priv() - generate private data from device tree
- * @dev: corresponding k3 remote processor device
- * @priv: pointer to driver specific private data
- *
- * Return: 0 if all goes good, else appropriate error message.
- */
-static int k3_rproc_of_to_priv(struct udevice *dev,
- struct k3_rproc_privdata *rproc)
-{
- int ret;
-
- dev_dbg(dev, "%s\n", __func__);
-
- ret = power_domain_get_by_index(dev, &rproc->rproc_pwrdmn, 1);
- if (ret) {
- dev_err(dev, "power_domain_get() failed: %d\n", ret);
- return ret;
- }
-
- ret = power_domain_get_by_index(dev, &rproc->gtc_pwrdmn, 0);
- if (ret) {
- dev_err(dev, "power_domain_get() failed: %d\n", ret);
- return ret;
- }
-
- ret = reset_get_by_index(dev, 0, &rproc->rproc_rst);
- if (ret) {
- dev_err(dev, "reset_get() failed: %d\n", ret);
- return ret;
- }
-
- rproc->sci = ti_sci_get_by_phandle(dev, "ti,sci");
- if (IS_ERR(rproc->sci)) {
- dev_err(dev, "ti_sci get failed: %d\n", ret);
- return PTR_ERR(rproc->sci);
- }
-
- rproc->gtc_base = dev_read_addr_ptr(dev);
- if (!rproc->gtc_base) {
- dev_err(dev, "Get address failed\n");
- return -ENODEV;
- }
-
- rproc->proc_id = dev_read_u32_default(dev, "ti,sci-proc-id",
- INVALID_ID);
- rproc->host_id = dev_read_u32_default(dev, "ti,sci-host-id",
- INVALID_ID);
-
- return 0;
-}
-
-/**
- * k3_rproc_probe() - Basic probe
- * @dev: corresponding k3 remote processor device
- *
- * Return: 0 if all goes good, else appropriate error message.
- */
-static int k3_rproc_probe(struct udevice *dev)
-{
- struct k3_rproc_privdata *priv;
- int ret;
-
- dev_dbg(dev, "%s\n", __func__);
-
- priv = dev_get_priv(dev);
-
- ret = k3_rproc_of_to_priv(dev, priv);
- if (ret) {
- dev_dbg(dev, "%s: Probe failed with error %d\n", __func__, ret);
- return ret;
- }
-
- dev_dbg(dev, "Remoteproc successfully probed\n");
-
- return 0;
-}
-
-static const struct udevice_id k3_rproc_ids[] = {
- { .compatible = "ti,am654-rproc"},
- {}
-};
-
-U_BOOT_DRIVER(k3_rproc) = {
- .name = "k3_rproc",
- .of_match = k3_rproc_ids,
- .id = UCLASS_REMOTEPROC,
- .ops = &k3_rproc_ops,
- .probe = k3_rproc_probe,
- .priv_auto_alloc_size = sizeof(struct k3_rproc_privdata),
-};
diff --git a/drivers/remoteproc/rproc-elf-loader.c b/drivers/remoteproc/rproc-elf-loader.c
new file mode 100644
index 0000000..67937a7
--- /dev/null
+++ b/drivers/remoteproc/rproc-elf-loader.c
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
+ */
+#include <common.h>
+#include <dm.h>
+#include <elf.h>
+#include <remoteproc.h>
+
+/* Basic function to verify ELF32 image format */
+int rproc_elf32_sanity_check(ulong addr, ulong size)
+{
+ Elf32_Ehdr *ehdr;
+ char class;
+
+ if (!addr) {
+ pr_debug("Invalid fw address?\n");
+ return -EFAULT;
+ }
+
+ if (size < sizeof(Elf32_Ehdr)) {
+ pr_debug("Image is too small\n");
+ return -ENOSPC;
+ }
+
+ ehdr = (Elf32_Ehdr *)addr;
+ class = ehdr->e_ident[EI_CLASS];
+
+ if (!IS_ELF(*ehdr) || ehdr->e_type != ET_EXEC || class != ELFCLASS32) {
+ pr_debug("Not an executable ELF32 image\n");
+ return -EPROTONOSUPPORT;
+ }
+
+ /* We assume the firmware has the same endianness as the host */
+# ifdef __LITTLE_ENDIAN
+ if (ehdr->e_ident[EI_DATA] != ELFDATA2LSB) {
+# else /* BIG ENDIAN */
+ if (ehdr->e_ident[EI_DATA] != ELFDATA2MSB) {
+# endif
+ pr_debug("Unsupported firmware endianness\n");
+ return -EILSEQ;
+ }
+
+ if (size < ehdr->e_shoff + sizeof(Elf32_Shdr)) {
+ pr_debug("Image is too small\n");
+ return -ENOSPC;
+ }
+
+ if (memcmp(ehdr->e_ident, ELFMAG, SELFMAG)) {
+ pr_debug("Image is corrupted (bad magic)\n");
+ return -EBADF;
+ }
+
+ if (ehdr->e_phnum == 0) {
+ pr_debug("No loadable segments\n");
+ return -ENOEXEC;
+ }
+
+ if (ehdr->e_phoff > size) {
+ pr_debug("Firmware size is too small\n");
+ return -ENOSPC;
+ }
+
+ return 0;
+}
+
+/* A very simple elf loader, assumes the image is valid */
+int rproc_elf32_load_image(struct udevice *dev, unsigned long addr)
+{
+ Elf32_Ehdr *ehdr; /* Elf header structure pointer */
+ Elf32_Phdr *phdr; /* Program header structure pointer */
+ const struct dm_rproc_ops *ops;
+ unsigned int i;
+
+ ehdr = (Elf32_Ehdr *)addr;
+ phdr = (Elf32_Phdr *)(addr + ehdr->e_phoff);
+
+ ops = rproc_get_ops(dev);
+
+ /* Load each program header */
+ for (i = 0; i < ehdr->e_phnum; ++i) {
+ void *dst = (void *)(uintptr_t)phdr->p_paddr;
+ void *src = (void *)addr + phdr->p_offset;
+
+ if (phdr->p_type != PT_LOAD)
+ continue;
+
+ if (ops->device_to_virt)
+ dst = ops->device_to_virt(dev, (ulong)dst);
+
+ dev_dbg(dev, "Loading phdr %i to 0x%p (%i bytes)\n",
+ i, dst, phdr->p_filesz);
+ if (phdr->p_filesz)
+ memcpy(dst, src, phdr->p_filesz);
+ if (phdr->p_filesz != phdr->p_memsz)
+ memset(dst + phdr->p_filesz, 0x00,
+ phdr->p_memsz - phdr->p_filesz);
+ flush_cache(rounddown((unsigned long)dst, ARCH_DMA_MINALIGN),
+ roundup((unsigned long)dst + phdr->p_filesz,
+ ARCH_DMA_MINALIGN) -
+ rounddown((unsigned long)dst, ARCH_DMA_MINALIGN));
+ ++phdr;
+ }
+
+ return 0;
+}
diff --git a/drivers/remoteproc/sandbox_testproc.c b/drivers/remoteproc/sandbox_testproc.c
index 51a67e6..5f35119 100644
--- a/drivers/remoteproc/sandbox_testproc.c
+++ b/drivers/remoteproc/sandbox_testproc.c
@@ -8,6 +8,7 @@
#include <dm.h>
#include <errno.h>
#include <remoteproc.h>
+#include <asm/io.h>
/**
* enum sandbox_state - different device states
@@ -300,6 +301,23 @@
return ret;
}
+#define SANDBOX_RPROC_DEV_TO_PHY_OFFSET 0x1000
+/**
+ * sandbox_testproc_device_to_virt() - Convert device address to virtual address
+ * @dev: device to operate upon
+ * @da: device address
+ * @return converted virtual address
+ */
+static void *sandbox_testproc_device_to_virt(struct udevice *dev, ulong da)
+{
+ u64 paddr;
+
+ /* Use a simple offset conversion */
+ paddr = da + SANDBOX_RPROC_DEV_TO_PHY_OFFSET;
+
+ return phys_to_virt(paddr);
+}
+
static const struct dm_rproc_ops sandbox_testproc_ops = {
.init = sandbox_testproc_init,
.reset = sandbox_testproc_reset,
@@ -308,6 +326,7 @@
.stop = sandbox_testproc_stop,
.is_running = sandbox_testproc_is_running,
.ping = sandbox_testproc_ping,
+ .device_to_virt = sandbox_testproc_device_to_virt,
};
static const struct udevice_id sandbox_ids[] = {
diff --git a/drivers/remoteproc/stm32_copro.c b/drivers/remoteproc/stm32_copro.c
new file mode 100644
index 0000000..ad941f6
--- /dev/null
+++ b/drivers/remoteproc/stm32_copro.c
@@ -0,0 +1,257 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
+ */
+#define pr_fmt(fmt) "%s: " fmt, __func__
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <regmap.h>
+#include <remoteproc.h>
+#include <reset.h>
+#include <syscon.h>
+#include <asm/io.h>
+
+#define RCC_GCR_HOLD_BOOT 0
+#define RCC_GCR_RELEASE_BOOT 1
+
+/**
+ * struct stm32_copro_privdata - power processor private data
+ * @reset_ctl: reset controller handle
+ * @hold_boot_regmap: regmap for remote processor reset hold boot
+ * @hold_boot_offset: offset of the register controlling the hold boot setting
+ * @hold_boot_mask: bitmask of the register for the hold boot field
+ * @is_running: is the remote processor running
+ */
+struct stm32_copro_privdata {
+ struct reset_ctl reset_ctl;
+ struct regmap *hold_boot_regmap;
+ uint hold_boot_offset;
+ uint hold_boot_mask;
+ bool is_running;
+};
+
+/**
+ * stm32_copro_probe() - Basic probe
+ * @dev: corresponding STM32 remote processor device
+ * @return 0 if all went ok, else corresponding -ve error
+ */
+static int stm32_copro_probe(struct udevice *dev)
+{
+ struct stm32_copro_privdata *priv;
+ struct regmap *regmap;
+ const fdt32_t *cell;
+ int len, ret;
+
+ priv = dev_get_priv(dev);
+
+ regmap = syscon_regmap_lookup_by_phandle(dev, "st,syscfg-holdboot");
+ if (IS_ERR(regmap)) {
+ dev_err(dev, "unable to find holdboot regmap (%ld)\n",
+ PTR_ERR(regmap));
+ return PTR_ERR(regmap);
+ }
+
+ cell = dev_read_prop(dev, "st,syscfg-holdboot", &len);
+ if (len < 3 * sizeof(fdt32_t)) {
+ dev_err(dev, "holdboot offset and mask not available\n");
+ return -EINVAL;
+ }
+
+ priv->hold_boot_regmap = regmap;
+ priv->hold_boot_offset = fdtdec_get_number(cell + 1, 1);
+ priv->hold_boot_mask = fdtdec_get_number(cell + 2, 1);
+
+ ret = reset_get_by_index(dev, 0, &priv->reset_ctl);
+ if (ret) {
+ dev_err(dev, "failed to get reset (%d)\n", ret);
+ return ret;
+ }
+
+ dev_dbg(dev, "probed\n");
+
+ return 0;
+}
+
+/**
+ * stm32_copro_set_hold_boot() - Hold boot bit management
+ * @dev: corresponding STM32 remote processor device
+ * @hold: hold boot value
+ * @return 0 if all went ok, else corresponding -ve error
+ */
+static int stm32_copro_set_hold_boot(struct udevice *dev, bool hold)
+{
+ struct stm32_copro_privdata *priv;
+ uint val;
+ int ret;
+
+ priv = dev_get_priv(dev);
+
+ val = hold ? RCC_GCR_HOLD_BOOT : RCC_GCR_RELEASE_BOOT;
+
+ /*
+ * Note: shall run an SMC call (STM32_SMC_RCC) if platform is secured.
+ * To be updated when the code for this SMC service is available which
+ * is not the case for the time being.
+ */
+ ret = regmap_update_bits(priv->hold_boot_regmap, priv->hold_boot_offset,
+ priv->hold_boot_mask, val);
+ if (ret)
+ dev_err(dev, "failed to set hold boot\n");
+
+ return ret;
+}
+
+/**
+ * stm32_copro_device_to_virt() - Convert device address to virtual address
+ * @dev: corresponding STM32 remote processor device
+ * @da: device address
+ * @return converted virtual address
+ */
+static void *stm32_copro_device_to_virt(struct udevice *dev, ulong da)
+{
+ fdt32_t in_addr = cpu_to_be32(da);
+ u64 paddr;
+
+ paddr = dev_translate_dma_address(dev, &in_addr);
+ if (paddr == OF_BAD_ADDR) {
+ dev_err(dev, "Unable to convert address %ld\n", da);
+ return NULL;
+ }
+
+ return phys_to_virt(paddr);
+}
+
+/**
+ * stm32_copro_load() - Loadup the STM32 remote processor
+ * @dev: corresponding STM32 remote processor device
+ * @addr: Address in memory where image is stored
+ * @size: Size in bytes of the image
+ * @return 0 if all went ok, else corresponding -ve error
+ */
+static int stm32_copro_load(struct udevice *dev, ulong addr, ulong size)
+{
+ struct stm32_copro_privdata *priv;
+ int ret;
+
+ priv = dev_get_priv(dev);
+
+ ret = stm32_copro_set_hold_boot(dev, true);
+ if (ret)
+ return ret;
+
+ ret = reset_assert(&priv->reset_ctl);
+ if (ret) {
+ dev_err(dev, "Unable to assert reset line (ret=%d)\n", ret);
+ return ret;
+ }
+
+ /* Support only ELF32 image */
+ ret = rproc_elf32_sanity_check(addr, size);
+ if (ret) {
+ dev_err(dev, "Invalid ELF32 image (%d)\n", ret);
+ return ret;
+ }
+
+ return rproc_elf32_load_image(dev, addr);
+}
+
+/**
+ * stm32_copro_start() - Start the STM32 remote processor
+ * @dev: corresponding STM32 remote processor device
+ * @return 0 if all went ok, else corresponding -ve error
+ */
+static int stm32_copro_start(struct udevice *dev)
+{
+ struct stm32_copro_privdata *priv;
+ int ret;
+
+ priv = dev_get_priv(dev);
+
+ /* move hold boot from true to false start the copro */
+ ret = stm32_copro_set_hold_boot(dev, false);
+ if (ret)
+ return ret;
+
+ /*
+ * Once copro running, reset hold boot flag to avoid copro
+ * rebooting autonomously
+ */
+ ret = stm32_copro_set_hold_boot(dev, true);
+ priv->is_running = !ret;
+ return ret;
+}
+
+/**
+ * stm32_copro_reset() - Reset the STM32 remote processor
+ * @dev: corresponding STM32 remote processor device
+ * @return 0 if all went ok, else corresponding -ve error
+ */
+static int stm32_copro_reset(struct udevice *dev)
+{
+ struct stm32_copro_privdata *priv;
+ int ret;
+
+ priv = dev_get_priv(dev);
+
+ ret = stm32_copro_set_hold_boot(dev, true);
+ if (ret)
+ return ret;
+
+ ret = reset_assert(&priv->reset_ctl);
+ if (ret) {
+ dev_err(dev, "Unable to assert reset line (ret=%d)\n", ret);
+ return ret;
+ }
+
+ priv->is_running = false;
+
+ return 0;
+}
+
+/**
+ * stm32_copro_stop() - Stop the STM32 remote processor
+ * @dev: corresponding STM32 remote processor device
+ * @return 0 if all went ok, else corresponding -ve error
+ */
+static int stm32_copro_stop(struct udevice *dev)
+{
+ return stm32_copro_reset(dev);
+}
+
+/**
+ * stm32_copro_is_running() - Is the STM32 remote processor running
+ * @dev: corresponding STM32 remote processor device
+ * @return 1 if the remote processor is running, 0 otherwise
+ */
+static int stm32_copro_is_running(struct udevice *dev)
+{
+ struct stm32_copro_privdata *priv;
+
+ priv = dev_get_priv(dev);
+ return priv->is_running;
+}
+
+static const struct dm_rproc_ops stm32_copro_ops = {
+ .load = stm32_copro_load,
+ .start = stm32_copro_start,
+ .stop = stm32_copro_stop,
+ .reset = stm32_copro_reset,
+ .is_running = stm32_copro_is_running,
+ .device_to_virt = stm32_copro_device_to_virt,
+};
+
+static const struct udevice_id stm32_copro_ids[] = {
+ {.compatible = "st,stm32mp1-m4"},
+ {}
+};
+
+U_BOOT_DRIVER(stm32_copro) = {
+ .name = "stm32_m4_proc",
+ .of_match = stm32_copro_ids,
+ .id = UCLASS_REMOTEPROC,
+ .ops = &stm32_copro_ops,
+ .probe = stm32_copro_probe,
+ .priv_auto_alloc_size = sizeof(struct stm32_copro_privdata),
+};
diff --git a/drivers/remoteproc/ti_k3_arm64_rproc.c b/drivers/remoteproc/ti_k3_arm64_rproc.c
new file mode 100644
index 0000000..9676a96
--- /dev/null
+++ b/drivers/remoteproc/ti_k3_arm64_rproc.c
@@ -0,0 +1,228 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments' K3 ARM64 Remoteproc driver
+ *
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Lokesh Vutla <lokeshvutla@ti.com>
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <remoteproc.h>
+#include <errno.h>
+#include <clk.h>
+#include <reset.h>
+#include <asm/io.h>
+#include <power-domain.h>
+#include <linux/soc/ti/ti_sci_protocol.h>
+#include "ti_sci_proc.h"
+
+#define INVALID_ID 0xffff
+
+#define GTC_CNTCR_REG 0x0
+#define GTC_CNTR_EN 0x3
+
+/**
+ * struct k3_arm64_privdata - Structure representing Remote processor data.
+ * @rproc_pwrdmn: rproc power domain data
+ * @rproc_rst: rproc reset control data
+ * @sci: Pointer to TISCI handle
+ * @tsp: TISCI processor control helper structure
+ * @gtc_base: Timer base address.
+ */
+struct k3_arm64_privdata {
+ struct power_domain rproc_pwrdmn;
+ struct power_domain gtc_pwrdmn;
+ struct reset_ctl rproc_rst;
+ struct ti_sci_proc tsp;
+ void *gtc_base;
+};
+
+/**
+ * k3_arm64_load() - Load up the Remote processor image
+ * @dev: rproc device pointer
+ * @addr: Address at which image is available
+ * @size: size of the image
+ *
+ * Return: 0 if all goes good, else appropriate error message.
+ */
+static int k3_arm64_load(struct udevice *dev, ulong addr, ulong size)
+{
+ struct k3_arm64_privdata *rproc = dev_get_priv(dev);
+ int ret;
+
+ dev_dbg(dev, "%s addr = 0x%lx, size = 0x%lx\n", __func__, addr, size);
+
+ /* request for the processor */
+ ret = ti_sci_proc_request(&rproc->tsp);
+ if (ret)
+ return ret;
+
+ return ti_sci_proc_set_config(&rproc->tsp, addr, 0, 0);
+}
+
+/**
+ * k3_arm64_start() - Start the remote processor
+ * @dev: rproc device pointer
+ *
+ * Return: 0 if all went ok, else return appropriate error
+ */
+static int k3_arm64_start(struct udevice *dev)
+{
+ struct k3_arm64_privdata *rproc = dev_get_priv(dev);
+ int ret;
+
+ dev_dbg(dev, "%s\n", __func__);
+
+ ret = power_domain_on(&rproc->gtc_pwrdmn);
+ if (ret) {
+ dev_err(dev, "power_domain_on() failed: %d\n", ret);
+ return ret;
+ }
+
+ /* Enable the timer before starting remote core */
+ writel(GTC_CNTR_EN, rproc->gtc_base + GTC_CNTCR_REG);
+
+ /*
+ * Setting the right clock frequency would have taken care by
+ * assigned-clock-rates during the device probe. So no need to
+ * set the frequency again here.
+ */
+ ret = power_domain_on(&rproc->rproc_pwrdmn);
+ if (ret) {
+ dev_err(dev, "power_domain_on() failed: %d\n", ret);
+ return ret;
+ }
+
+ return ti_sci_proc_release(&rproc->tsp);
+}
+
+/**
+ * k3_arm64_init() - Initialize the remote processor
+ * @dev: rproc device pointer
+ *
+ * Return: 0 if all went ok, else return appropriate error
+ */
+static int k3_arm64_init(struct udevice *dev)
+{
+ dev_dbg(dev, "%s\n", __func__);
+
+ /* Enable the module */
+ dev_dbg(dev, "%s: rproc successfully initialized\n", __func__);
+
+ return 0;
+}
+
+static const struct dm_rproc_ops k3_arm64_ops = {
+ .init = k3_arm64_init,
+ .load = k3_arm64_load,
+ .start = k3_arm64_start,
+};
+
+static int ti_sci_proc_of_to_priv(struct udevice *dev, struct ti_sci_proc *tsp)
+{
+ dev_dbg(dev, "%s\n", __func__);
+
+ tsp->sci = ti_sci_get_by_phandle(dev, "ti,sci");
+ if (IS_ERR(tsp->sci)) {
+ dev_err(dev, "ti_sci get failed: %ld\n", PTR_ERR(tsp->sci));
+ return PTR_ERR(tsp->sci);
+ }
+
+ tsp->proc_id = dev_read_u32_default(dev, "ti,sci-proc-id", INVALID_ID);
+ if (tsp->proc_id == INVALID_ID) {
+ dev_err(dev, "proc id not populated\n");
+ return -ENOENT;
+ }
+ tsp->host_id = dev_read_u32_default(dev, "ti,sci-host-id", INVALID_ID);
+ tsp->ops = &tsp->sci->ops.proc_ops;
+
+ return 0;
+}
+
+/**
+ * k3_of_to_priv() - generate private data from device tree
+ * @dev: corresponding k3 remote processor device
+ * @priv: pointer to driver specific private data
+ *
+ * Return: 0 if all goes good, else appropriate error message.
+ */
+static int k3_arm64_of_to_priv(struct udevice *dev,
+ struct k3_arm64_privdata *rproc)
+{
+ int ret;
+
+ dev_dbg(dev, "%s\n", __func__);
+
+ ret = power_domain_get_by_index(dev, &rproc->rproc_pwrdmn, 1);
+ if (ret) {
+ dev_err(dev, "power_domain_get() failed: %d\n", ret);
+ return ret;
+ }
+
+ ret = power_domain_get_by_index(dev, &rproc->gtc_pwrdmn, 0);
+ if (ret) {
+ dev_err(dev, "power_domain_get() failed: %d\n", ret);
+ return ret;
+ }
+
+ ret = reset_get_by_index(dev, 0, &rproc->rproc_rst);
+ if (ret) {
+ dev_err(dev, "reset_get() failed: %d\n", ret);
+ return ret;
+ }
+
+ ret = ti_sci_proc_of_to_priv(dev, &rproc->tsp);
+ if (ret)
+ return ret;
+
+ rproc->gtc_base = dev_read_addr_ptr(dev);
+ if (!rproc->gtc_base) {
+ dev_err(dev, "Get address failed\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+/**
+ * k3_arm64_probe() - Basic probe
+ * @dev: corresponding k3 remote processor device
+ *
+ * Return: 0 if all goes good, else appropriate error message.
+ */
+static int k3_arm64_probe(struct udevice *dev)
+{
+ struct k3_arm64_privdata *priv;
+ int ret;
+
+ dev_dbg(dev, "%s\n", __func__);
+
+ priv = dev_get_priv(dev);
+
+ ret = k3_arm64_of_to_priv(dev, priv);
+ if (ret) {
+ dev_dbg(dev, "%s: Probe failed with error %d\n", __func__, ret);
+ return ret;
+ }
+
+ dev_dbg(dev, "Remoteproc successfully probed\n");
+
+ return 0;
+}
+
+static const struct udevice_id k3_arm64_ids[] = {
+ { .compatible = "ti,am654-arm64"},
+ { .compatible = "ti,am654-rproc"},
+ {}
+};
+
+U_BOOT_DRIVER(k3_arm64) = {
+ .name = "k3_arm64",
+ .of_match = k3_arm64_ids,
+ .id = UCLASS_REMOTEPROC,
+ .ops = &k3_arm64_ops,
+ .probe = k3_arm64_probe,
+ .priv_auto_alloc_size = sizeof(struct k3_arm64_privdata),
+};
diff --git a/drivers/remoteproc/ti_sci_proc.h b/drivers/remoteproc/ti_sci_proc.h
new file mode 100644
index 0000000..ccfc39e
--- /dev/null
+++ b/drivers/remoteproc/ti_sci_proc.h
@@ -0,0 +1,121 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Texas Instruments TI-SCI Processor Controller Helper Functions
+ *
+ * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Lokesh Vutla <lokeshvutla@ti.com>
+ * Suman Anna <s-anna@ti.com>
+ */
+
+#ifndef REMOTEPROC_TI_SCI_PROC_H
+#define REMOTEPROC_TI_SCI_PROC_H
+
+#define TISCI_INVALID_HOST 0xff
+
+/**
+ * struct ti_sci_proc - structure representing a processor control client
+ * @sci: cached TI-SCI protocol handle
+ * @ops: cached TI-SCI proc ops
+ * @proc_id: processor id for the consumer remoteproc device
+ * @host_id: host id to pass the control over for this consumer remoteproc
+ * device
+ */
+struct ti_sci_proc {
+ const struct ti_sci_handle *sci;
+ const struct ti_sci_proc_ops *ops;
+ u8 proc_id;
+ u8 host_id;
+};
+
+static inline int ti_sci_proc_request(struct ti_sci_proc *tsp)
+{
+ int ret;
+
+ debug("%s: proc_id = %d\n", __func__, tsp->proc_id);
+
+ ret = tsp->ops->proc_request(tsp->sci, tsp->proc_id);
+ if (ret)
+ pr_err("ti-sci processor request failed: %d\n", ret);
+ return ret;
+}
+
+static inline int ti_sci_proc_release(struct ti_sci_proc *tsp)
+{
+ int ret;
+
+ debug("%s: proc_id = %d\n", __func__, tsp->proc_id);
+
+ if (tsp->host_id != TISCI_INVALID_HOST)
+ ret = tsp->ops->proc_handover(tsp->sci, tsp->proc_id,
+ tsp->host_id);
+ else
+ ret = tsp->ops->proc_release(tsp->sci, tsp->proc_id);
+
+ if (ret)
+ pr_err("ti-sci processor release failed: %d\n", ret);
+ return ret;
+}
+
+static inline int ti_sci_proc_handover(struct ti_sci_proc *tsp)
+{
+ int ret;
+
+ debug("%s: proc_id = %d\n", __func__, tsp->proc_id);
+
+ ret = tsp->ops->proc_handover(tsp->sci, tsp->proc_id, tsp->host_id);
+ if (ret)
+ pr_err("ti-sci processor handover of %d to %d failed: %d\n",
+ tsp->proc_id, tsp->host_id, ret);
+ return ret;
+}
+
+static inline int ti_sci_proc_get_status(struct ti_sci_proc *tsp,
+ u64 *boot_vector, u32 *cfg_flags,
+ u32 *ctrl_flags, u32 *status_flags)
+{
+ int ret;
+
+ ret = tsp->ops->get_proc_boot_status(tsp->sci, tsp->proc_id,
+ boot_vector, cfg_flags, ctrl_flags,
+ status_flags);
+ if (ret)
+ pr_err("ti-sci processor get_status failed: %d\n", ret);
+
+ debug("%s: proc_id = %d, boot_vector = 0x%llx, cfg_flags = 0x%x, ctrl_flags = 0x%x, sts = 0x%x\n",
+ __func__, tsp->proc_id, *boot_vector, *cfg_flags, *ctrl_flags,
+ *status_flags);
+ return ret;
+}
+
+static inline int ti_sci_proc_set_config(struct ti_sci_proc *tsp,
+ u64 boot_vector,
+ u32 cfg_set, u32 cfg_clr)
+{
+ int ret;
+
+ debug("%s: proc_id = %d, boot_vector = 0x%llx, cfg_set = 0x%x, cfg_clr = 0x%x\n",
+ __func__, tsp->proc_id, boot_vector, cfg_set, cfg_clr);
+
+ ret = tsp->ops->set_proc_boot_cfg(tsp->sci, tsp->proc_id, boot_vector,
+ cfg_set, cfg_clr);
+ if (ret)
+ pr_err("ti-sci processor set_config failed: %d\n", ret);
+ return ret;
+}
+
+static inline int ti_sci_proc_set_control(struct ti_sci_proc *tsp,
+ u32 ctrl_set, u32 ctrl_clr)
+{
+ int ret;
+
+ debug("%s: proc_id = %d, ctrl_set = 0x%x, ctrl_clr = 0x%x\n", __func__,
+ tsp->proc_id, ctrl_set, ctrl_clr);
+
+ ret = tsp->ops->set_proc_boot_ctrl(tsp->sci, tsp->proc_id, ctrl_set,
+ ctrl_clr);
+ if (ret)
+ pr_err("ti-sci processor set_control failed: %d\n", ret);
+ return ret;
+}
+
+#endif /* REMOTEPROC_TI_SCI_PROC_H */
diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
index ee4cbcb..93ec9cf 100644
--- a/drivers/reset/reset-socfpga.c
+++ b/drivers/reset/reset-socfpga.c
@@ -14,7 +14,9 @@
#include <common.h>
#include <dm.h>
+#include <dm/lists.h>
#include <dm/of_access.h>
+#include <env.h>
#include <reset-uclass.h>
#include <linux/bitops.h>
#include <linux/io.h>
@@ -130,6 +132,23 @@
return 0;
}
+static int socfpga_reset_bind(struct udevice *dev)
+{
+ int ret;
+ struct udevice *sys_child;
+
+ /*
+ * The sysreset driver does not have a device node, so bind it here.
+ * Bind it to the node, too, so that it can get its base address.
+ */
+ ret = device_bind_driver_to_node(dev, "socfpga_sysreset", "sysreset",
+ dev->node, &sys_child);
+ if (ret)
+ debug("Warning: No sysreset driver: ret=%d\n", ret);
+
+ return 0;
+}
+
static const struct udevice_id socfpga_reset_match[] = {
{ .compatible = "altr,rst-mgr" },
{ /* sentinel */ },
@@ -139,6 +158,7 @@
.name = "socfpga-reset",
.id = UCLASS_RESET,
.of_match = socfpga_reset_match,
+ .bind = socfpga_reset_bind,
.probe = socfpga_reset_probe,
.priv_auto_alloc_size = sizeof(struct socfpga_reset_data),
.ops = &socfpga_reset_ops,
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index fd0009b..8778cc7 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -31,6 +31,12 @@
drivers to perform the actual functions. See rtc.h for a
description of the API.
+config RTC_ENABLE_32KHZ_OUTPUT
+ bool "Enable RTC 32Khz output"
+ help
+ Some real-time clocks support the output of 32kHz square waves (such as ds3231),
+ the config symbol choose Real Time Clock device 32Khz output feature.
+
config RTC_PCF2127
bool "Enable PCF2127 driver"
depends on DM_RTC
@@ -70,12 +76,27 @@
This driver supports reading and writing the RTC/calendar and the
battery-baced SRAM section.
+config RTC_RV8803
+ bool "Enable RV8803 driver"
+ depends on DM_RTC
+ help
+ The Micro Crystal RV8803 is a high accuracy, ultra-low power I2C
+ Real Time Clock (RTC) with temperature compensation.
+
+ This driver supports reading and writing the RTC/calendar and
+ detects total power failures.
+
config RTC_RX8010SJ
bool "Enable RX8010SJ driver"
depends on DM_RTC
help
Support for Epson RX8010SJ Real Time Clock devices.
+config RTC_RX8025
+ bool "Enable RX8025 driver"
+ help
+ Support for Epson RX8025 Real Time Clock devices.
+
config RTC_PL031
bool "Enable ARM AMBA PL031 RTC driver"
help
@@ -110,4 +131,10 @@
Enable driver for ST's M41T62 compatible RTC devices (like RV-4162).
It is a serial (I2C) real-time clock (RTC) with alarm.
+config RTC_STM32
+ bool "Enable STM32 RTC driver"
+ depends on DM_RTC
+ help
+ Enable STM32 RTC driver. This driver supports the rtc that is present
+ on some STM32 SoCs.
endmenu
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 1724602..f97a669 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -46,9 +46,11 @@
obj-$(CONFIG_RTC_PT7C4338) += pt7c4338.o
obj-$(CONFIG_RTC_RS5C372A) += rs5c372.o
obj-$(CONFIG_RTC_RV3029) += rv3029.o
+obj-$(CONFIG_RTC_RV8803) += rv8803.o
obj-$(CONFIG_RTC_RX8025) += rx8025.o
obj-$(CONFIG_RTC_RX8010SJ) += rx8010sj.o
obj-$(CONFIG_RTC_S3C24X0) += s3c24x0_rtc.o
obj-$(CONFIG_RTC_S35392A) += s35392a.o
+obj-$(CONFIG_RTC_STM32) += stm32_rtc.o
obj-$(CONFIG_SANDBOX) += sandbox_rtc.o
obj-$(CONFIG_RTC_X1205) += x1205.o
diff --git a/drivers/rtc/ds1307.c b/drivers/rtc/ds1307.c
index 48220b4..a33f475 100644
--- a/drivers/rtc/ds1307.c
+++ b/drivers/rtc/ds1307.c
@@ -23,6 +23,7 @@
ds_1307,
ds_1337,
ds_1340,
+ m41t11,
mcp794xx,
};
@@ -260,6 +261,18 @@
}
}
+ if (type == m41t11) {
+ /* clock halted? turn it on, so clock can tick. */
+ if (buf[RTC_SEC_REG_ADDR] & RTC_SEC_BIT_CH) {
+ buf[RTC_SEC_REG_ADDR] &= ~RTC_SEC_BIT_CH;
+ dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR,
+ MCP7941X_BIT_ST);
+ dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR,
+ buf[RTC_SEC_REG_ADDR]);
+ goto read_rtc;
+ }
+ }
+
if (type == mcp794xx) {
/* make sure that the backup battery is enabled */
if (!(buf[RTC_DAY_REG_ADDR] & MCP7941X_BIT_VBATEN)) {
@@ -332,6 +345,7 @@
{ .compatible = "dallas,ds1337", .data = ds_1337 },
{ .compatible = "dallas,ds1340", .data = ds_1340 },
{ .compatible = "microchip,mcp7941x", .data = mcp794xx },
+ { .compatible = "st,m41t11", .data = m41t11 },
{ }
};
diff --git a/drivers/rtc/ds3231.c b/drivers/rtc/ds3231.c
index 9352ff8..eb5ce73 100644
--- a/drivers/rtc/ds3231.c
+++ b/drivers/rtc/ds3231.c
@@ -2,6 +2,9 @@
/*
* (C) Copyright 2006
* Markus Klotzbuecher, mk@denx.de
+ *
+ * (C) Copyright 2019 NXP
+ * Chuanhua Han <chuanhua.han@nxp.com>
*/
/*
@@ -13,6 +16,7 @@
#include <common.h>
#include <command.h>
+#include <dm.h>
#include <rtc.h>
#include <i2c.h>
@@ -50,6 +54,7 @@
#define RTC_STAT_BIT_EN32KHZ 0x8 /* Enable 32KHz Output */
+#if !CONFIG_IS_ENABLED(DM_RTC)
static uchar rtc_read (uchar reg);
static void rtc_write (uchar reg, uchar val);
@@ -143,11 +148,13 @@
/*
* Enable 32KHz output
*/
+#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT
void rtc_enable_32khz_output(void)
{
rtc_write(RTC_STAT_REG_ADDR,
RTC_STAT_BIT_BB32KHZ | RTC_STAT_BIT_EN32KHZ);
}
+#endif
/*
* Helper functions
@@ -164,3 +171,121 @@
{
i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
}
+#else
+static int ds3231_rtc_get(struct udevice *dev, struct rtc_time *tmp)
+{
+ uchar sec, min, hour, mday, wday, mon_cent, year, status;
+
+ status = dm_i2c_reg_read(dev, RTC_STAT_REG_ADDR);
+ sec = dm_i2c_reg_read(dev, RTC_SEC_REG_ADDR);
+ min = dm_i2c_reg_read(dev, RTC_MIN_REG_ADDR);
+ hour = dm_i2c_reg_read(dev, RTC_HR_REG_ADDR);
+ wday = dm_i2c_reg_read(dev, RTC_DAY_REG_ADDR);
+ mday = dm_i2c_reg_read(dev, RTC_DATE_REG_ADDR);
+ mon_cent = dm_i2c_reg_read(dev, RTC_MON_REG_ADDR);
+ year = dm_i2c_reg_read(dev, RTC_YR_REG_ADDR);
+
+ if (status & RTC_STAT_BIT_OSF) {
+ printf("### Warning: RTC oscillator has stopped\n");
+ /* clear the OSF flag */
+ dm_i2c_reg_write(dev, RTC_STAT_REG_ADDR,
+ dm_i2c_reg_read(dev, RTC_STAT_REG_ADDR)
+ & ~RTC_STAT_BIT_OSF);
+ return -EINVAL;
+ }
+
+ tmp->tm_sec = bcd2bin(sec & 0x7F);
+ tmp->tm_min = bcd2bin(min & 0x7F);
+ tmp->tm_hour = bcd2bin(hour & 0x3F);
+ tmp->tm_mday = bcd2bin(mday & 0x3F);
+ tmp->tm_mon = bcd2bin(mon_cent & 0x1F);
+ tmp->tm_year = bcd2bin(year) + ((mon_cent & 0x80) ? 2000 : 1900);
+ tmp->tm_wday = bcd2bin((wday - 1) & 0x07);
+ tmp->tm_yday = 0;
+ tmp->tm_isdst = 0;
+
+ debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+ tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+
+ return 0;
+}
+
+static int ds3231_rtc_set(struct udevice *dev, const struct rtc_time *tmp)
+{
+ uchar century;
+
+ debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+ tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+
+ dm_i2c_reg_write(dev, RTC_YR_REG_ADDR, bin2bcd(tmp->tm_year % 100));
+
+ century = (tmp->tm_year >= 2000) ? 0x80 : 0;
+ dm_i2c_reg_write(dev, RTC_MON_REG_ADDR, bin2bcd(tmp->tm_mon) | century);
+
+ dm_i2c_reg_write(dev, RTC_DAY_REG_ADDR, bin2bcd(tmp->tm_wday + 1));
+ dm_i2c_reg_write(dev, RTC_DATE_REG_ADDR, bin2bcd(tmp->tm_mday));
+ dm_i2c_reg_write(dev, RTC_HR_REG_ADDR, bin2bcd(tmp->tm_hour));
+ dm_i2c_reg_write(dev, RTC_MIN_REG_ADDR, bin2bcd(tmp->tm_min));
+ dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR, bin2bcd(tmp->tm_sec));
+
+ return 0;
+}
+
+static int ds3231_rtc_reset(struct udevice *dev)
+{
+ int ret;
+
+ ret = dm_i2c_reg_write(dev, RTC_CTL_REG_ADDR,
+ RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int ds3231_probe(struct udevice *dev)
+{
+ i2c_set_chip_flags(dev, DM_I2C_CHIP_RD_ADDRESS |
+ DM_I2C_CHIP_WR_ADDRESS);
+
+ return 0;
+}
+
+#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT
+int rtc_enable_32khz_output(int busnum, int chip_addr)
+{
+ int ret;
+ struct udevice *dev;
+
+ ret = i2c_get_chip_for_busnum(busnum, chip_addr, 1, &dev);
+ if (!ret) {
+ ret = dm_i2c_reg_write(dev, RTC_STAT_REG_ADDR,
+ RTC_STAT_BIT_BB32KHZ |
+ RTC_STAT_BIT_EN32KHZ);
+ }
+ return ret;
+}
+#endif
+
+static const struct rtc_ops ds3231_rtc_ops = {
+ .get = ds3231_rtc_get,
+ .set = ds3231_rtc_set,
+ .reset = ds3231_rtc_reset,
+};
+
+static const struct udevice_id ds3231_rtc_ids[] = {
+ { .compatible = "dallas,ds3231" },
+ { .compatible = "dallas,ds3232" },
+ { }
+};
+
+U_BOOT_DRIVER(rtc_ds3231) = {
+ .name = "rtc-ds3231",
+ .id = UCLASS_RTC,
+ .probe = ds3231_probe,
+ .of_match = ds3231_rtc_ids,
+ .ops = &ds3231_rtc_ops,
+};
+#endif
diff --git a/drivers/rtc/m41t60.c b/drivers/rtc/m41t60.c
index c84c8e1..532d210 100644
--- a/drivers/rtc/m41t60.c
+++ b/drivers/rtc/m41t60.c
@@ -17,6 +17,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <rtc.h>
#include <i2c.h>
diff --git a/drivers/rtc/pcf2127.c b/drivers/rtc/pcf2127.c
index dcf0340..f695350 100644
--- a/drivers/rtc/pcf2127.c
+++ b/drivers/rtc/pcf2127.c
@@ -22,14 +22,32 @@
#define PCF2127_REG_MO 0x08
#define PCF2127_REG_YR 0x09
+static int pcf2127_read_reg(struct udevice *dev, uint offset,
+ u8 *buffer, int len)
+{
+ struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
+ struct i2c_msg msg;
+ int ret;
+
+ /* Set the address of the start register to be read */
+ ret = dm_i2c_write(dev, offset, NULL, 0);
+ if (ret < 0)
+ return ret;
+
+ /* Read register's data */
+ msg.addr = chip->chip_addr;
+ msg.flags |= I2C_M_RD;
+ msg.len = len;
+ msg.buf = buffer;
+
+ return dm_i2c_xfer(dev, &msg, 1);
+}
+
static int pcf2127_rtc_set(struct udevice *dev, const struct rtc_time *tm)
{
- uchar buf[8];
+ uchar buf[7] = {0};
int i = 0, ret;
- /* start register address */
- buf[i++] = PCF2127_REG_SC;
-
/* hours, minutes and seconds */
buf[i++] = bin2bcd(tm->tm_sec);
buf[i++] = bin2bcd(tm->tm_min);
@@ -44,7 +62,7 @@
buf[i++] = bin2bcd(tm->tm_year % 100);
/* write register's data */
- ret = dm_i2c_write(dev, PCF2127_REG_CTRL1, buf, sizeof(buf));
+ ret = dm_i2c_write(dev, PCF2127_REG_SC, buf, i);
return ret;
}
@@ -54,10 +72,7 @@
int ret = 0;
uchar buf[10] = { PCF2127_REG_CTRL1 };
- ret = dm_i2c_write(dev, PCF2127_REG_CTRL1, buf, 1);
- if (ret < 0)
- return ret;
- ret = dm_i2c_read(dev, PCF2127_REG_CTRL1, buf, sizeof(buf));
+ ret = pcf2127_read_reg(dev, PCF2127_REG_CTRL1, buf, sizeof(buf));
if (ret < 0)
return ret;
diff --git a/drivers/rtc/rv8803.c b/drivers/rtc/rv8803.c
new file mode 100644
index 0000000..2ab40f0
--- /dev/null
+++ b/drivers/rtc/rv8803.c
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Date & Time support for Micro Crystal RV-8803-C7.
+ *
+ * based on ds1307.c which is
+ * (C) Copyright 2001, 2002, 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Keith Outwater, keith_outwater@mvis.com`
+ * Steven Scholz, steven.scholz@imc-berlin.de
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <dm.h>
+#include <rtc.h>
+#include <i2c.h>
+
+/*
+ * RTC register addresses
+ */
+#define RTC_SEC_REG_ADDR 0x00
+#define RTC_MIN_REG_ADDR 0x01
+#define RTC_HR_REG_ADDR 0x02
+#define RTC_DAY_REG_ADDR 0x03
+#define RTC_DATE_REG_ADDR 0x04
+#define RTC_MON_REG_ADDR 0x05
+#define RTC_YR_REG_ADDR 0x06
+
+#define RTC_FLAG_REG_ADDR 0x0E
+#define RTC_FLAG_BIT_V1F BIT(0)
+#define RTC_FLAG_BIT_V2F BIT(1)
+
+#define RTC_CTL_REG_ADDR 0x0F
+#define RTC_CTL_BIT_RST BIT(0)
+
+static int rv8803_rtc_set(struct udevice *dev, const struct rtc_time *tm)
+{
+ int ret;
+ u8 buf[7];
+
+ debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
+ tm->tm_hour, tm->tm_min, tm->tm_sec);
+
+ if (tm->tm_year < 2000 || tm->tm_year > 2099)
+ printf("WARNING: year should be between 2000 and 2099!\n");
+
+ buf[RTC_YR_REG_ADDR] = bin2bcd(tm->tm_year % 100);
+ buf[RTC_MON_REG_ADDR] = bin2bcd(tm->tm_mon);
+ buf[RTC_DAY_REG_ADDR] = 1 << (tm->tm_wday & 0x7);
+ buf[RTC_DATE_REG_ADDR] = bin2bcd(tm->tm_mday);
+ buf[RTC_HR_REG_ADDR] = bin2bcd(tm->tm_hour);
+ buf[RTC_MIN_REG_ADDR] = bin2bcd(tm->tm_min);
+ buf[RTC_SEC_REG_ADDR] = bin2bcd(tm->tm_sec);
+
+ ret = dm_i2c_write(dev, 0, buf, sizeof(buf));
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int rv8803_rtc_get(struct udevice *dev, struct rtc_time *tm)
+{
+ int ret;
+ u8 buf[7];
+ int flags;
+
+ flags = dm_i2c_reg_read(dev, RTC_FLAG_REG_ADDR);
+ if (flags < 0)
+ return flags;
+ debug("%s: flags=%Xh\n", __func__, flags);
+
+ if (flags & RTC_FLAG_BIT_V1F)
+ printf("### Warning: temperature compensation has stopped\n");
+
+ if (flags & RTC_FLAG_BIT_V2F) {
+ printf("### Warning: Voltage low, data is invalid\n");
+ return -1;
+ }
+
+ ret = dm_i2c_read(dev, 0, buf, sizeof(buf));
+ if (ret < 0)
+ return ret;
+
+ tm->tm_sec = bcd2bin(buf[RTC_SEC_REG_ADDR] & 0x7F);
+ tm->tm_min = bcd2bin(buf[RTC_MIN_REG_ADDR] & 0x7F);
+ tm->tm_hour = bcd2bin(buf[RTC_HR_REG_ADDR] & 0x3F);
+ tm->tm_mday = bcd2bin(buf[RTC_DATE_REG_ADDR] & 0x3F);
+ tm->tm_mon = bcd2bin(buf[RTC_MON_REG_ADDR] & 0x1F);
+ tm->tm_year = bcd2bin(buf[RTC_YR_REG_ADDR]) + 2000;
+ tm->tm_wday = fls(buf[RTC_DAY_REG_ADDR] & 0x7F) - 1;
+ tm->tm_yday = 0;
+ tm->tm_isdst = 0;
+
+ debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
+ tm->tm_hour, tm->tm_min, tm->tm_sec);
+
+ return 0;
+}
+
+static int rv8803_rtc_reset(struct udevice *dev)
+{
+ int ret;
+ struct rtc_time tmp = {
+ .tm_year = 2000,
+ .tm_mon = 1,
+ .tm_mday = 1,
+ .tm_hour = 0,
+ .tm_min = 0,
+ .tm_sec = 0,
+ };
+
+ /* assert reset */
+ ret = dm_i2c_reg_write(dev, RTC_CTL_REG_ADDR, RTC_CTL_BIT_RST);
+ if (ret < 0)
+ return ret;
+
+ /* clear all flags */
+ ret = dm_i2c_reg_write(dev, RTC_FLAG_REG_ADDR, 0);
+ if (ret < 0)
+ return ret;
+
+ ret = rv8803_rtc_set(dev, &tmp);
+ if (ret < 0)
+ return ret;
+
+ /* clear reset */
+ ret = dm_i2c_reg_write(dev, RTC_CTL_REG_ADDR, 0);
+ if (ret < 0)
+ return ret;
+
+ debug("RTC: %4d-%02d-%02d %2d:%02d:%02d UTC\n",
+ tmp.tm_year, tmp.tm_mon, tmp.tm_mday,
+ tmp.tm_hour, tmp.tm_min, tmp.tm_sec);
+
+ return 0;
+}
+
+static int rv8803_probe(struct udevice *dev)
+{
+ i2c_set_chip_flags(dev, DM_I2C_CHIP_RD_ADDRESS |
+ DM_I2C_CHIP_WR_ADDRESS);
+
+ return 0;
+}
+
+static const struct rtc_ops rv8803_rtc_ops = {
+ .get = rv8803_rtc_get,
+ .set = rv8803_rtc_set,
+ .reset = rv8803_rtc_reset,
+};
+
+static const struct udevice_id rv8803_rtc_ids[] = {
+ { .compatible = "microcrystal,rv8803", },
+ { }
+};
+
+U_BOOT_DRIVER(rtc_rv8803) = {
+ .name = "rtc-rv8803",
+ .id = UCLASS_RTC,
+ .probe = rv8803_probe,
+ .of_match = rv8803_rtc_ids,
+ .ops = &rv8803_rtc_ops,
+};
diff --git a/drivers/rtc/rx8025.c b/drivers/rtc/rx8025.c
index 7bd9f8b..e717dcb 100644
--- a/drivers/rtc/rx8025.c
+++ b/drivers/rtc/rx8025.c
@@ -10,8 +10,9 @@
#include <common.h>
#include <command.h>
-#include <rtc.h>
+#include <dm.h>
#include <i2c.h>
+#include <rtc.h>
/*---------------------------------------------------------------------*/
#undef DEBUG_RTC
@@ -27,6 +28,18 @@
# define CONFIG_SYS_I2C_RTC_ADDR 0x32
#endif
+#ifdef CONFIG_DM_RTC
+#define DEV_TYPE struct udevice
+#else
+/* Local udevice */
+struct ludevice {
+ u8 chip;
+};
+
+#define DEV_TYPE struct ludevice
+
+#endif
+
/*
* RTC register addresses
*/
@@ -68,21 +81,35 @@
*/
/* static uchar rtc_read (uchar reg); */
+#ifdef CONFIG_DM_RTC
+/*
+ * on mpc85xx based board with DM and offset len 1
+ * accessing rtc works fine. May we can drop this ?
+ */
+#define rtc_read(reg) buf[(reg) & 0xf]
+#else
#define rtc_read(reg) buf[((reg) + 1) & 0xf]
+#endif
-static void rtc_write (uchar reg, uchar val);
+static int rtc_write(DEV_TYPE *dev, uchar reg, uchar val);
/*
* Get the current time from the RTC
*/
-int rtc_get (struct rtc_time *tmp)
+static int rx8025_rtc_get(DEV_TYPE *dev, struct rtc_time *tmp)
{
int rel = 0;
uchar sec, min, hour, mday, wday, mon, year, ctl2;
uchar buf[16];
- if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 16))
+#ifdef CONFIG_DM_RTC
+ if (dm_i2c_read(dev, 0, buf, sizeof(buf))) {
+#else
+ if (i2c_read(dev->chip, 0, 0, buf, 16)) {
+#endif
printf("Error reading from RTC\n");
+ return -EIO;
+ }
sec = rtc_read(RTC_SEC_REG_ADDR);
min = rtc_read(RTC_MIN_REG_ADDR);
@@ -92,9 +119,9 @@
mon = rtc_read(RTC_MON_REG_ADDR);
year = rtc_read(RTC_YR_REG_ADDR);
- DEBUGR ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
- "hr: %02x min: %02x sec: %02x\n",
- year, mon, mday, wday, hour, min, sec);
+ DEBUGR("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
+ "hr: %02x min: %02x sec: %02x\n",
+ year, mon, mday, wday, hour, min, sec);
/* dump status */
ctl2 = rtc_read(RTC_CTL2_REG_ADDR);
@@ -113,13 +140,14 @@
rel = -1;
}
- tmp->tm_sec = bcd2bin (sec & 0x7F);
- tmp->tm_min = bcd2bin (min & 0x7F);
+ tmp->tm_sec = bcd2bin(sec & 0x7F);
+ tmp->tm_min = bcd2bin(min & 0x7F);
if (rtc_read(RTC_CTL1_REG_ADDR) & RTC_CTL1_BIT_2412)
- tmp->tm_hour = bcd2bin (hour & 0x3F);
+ tmp->tm_hour = bcd2bin(hour & 0x3F);
else
- tmp->tm_hour = bcd2bin (hour & 0x1F) % 12 +
+ tmp->tm_hour = bcd2bin(hour & 0x1F) % 12 +
((hour & 0x20) ? 12 : 0);
+
tmp->tm_mday = bcd2bin (mday & 0x3F);
tmp->tm_mon = bcd2bin (mon & 0x1F);
tmp->tm_year = bcd2bin (year) + ( bcd2bin (year) >= 70 ? 1900 : 2000);
@@ -127,9 +155,9 @@
tmp->tm_yday = 0;
tmp->tm_isdst= 0;
- DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
- tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
- tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+ DEBUGR("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+ tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
return rel;
}
@@ -137,54 +165,142 @@
/*
* Set the RTC
*/
-int rtc_set (struct rtc_time *tmp)
+static int rx8025_rtc_set(DEV_TYPE *dev, const struct rtc_time *tmp)
{
- DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
- tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
- tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+ DEBUGR("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+ tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
if (tmp->tm_year < 1970 || tmp->tm_year > 2069)
printf("WARNING: year should be between 1970 and 2069!\n");
- rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
- rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon));
- rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday));
- rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
- rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
- rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
- rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
+ if (rtc_write(dev, RTC_YR_REG_ADDR, bin2bcd(tmp->tm_year % 100)))
+ return -EIO;
- rtc_write (RTC_CTL1_REG_ADDR, RTC_CTL1_BIT_2412);
+ if (rtc_write(dev, RTC_MON_REG_ADDR, bin2bcd(tmp->tm_mon)))
+ return -EIO;
- return 0;
+ if (rtc_write(dev, RTC_DAY_REG_ADDR, bin2bcd(tmp->tm_wday)))
+ return -EIO;
+
+ if (rtc_write(dev, RTC_DATE_REG_ADDR, bin2bcd(tmp->tm_mday)))
+ return -EIO;
+
+ if (rtc_write(dev, RTC_HR_REG_ADDR, bin2bcd(tmp->tm_hour)))
+ return -EIO;
+
+ if (rtc_write(dev, RTC_MIN_REG_ADDR, bin2bcd(tmp->tm_min)))
+ return -EIO;
+
+ if (rtc_write(dev, RTC_SEC_REG_ADDR, bin2bcd(tmp->tm_sec)))
+ return -EIO;
+
+ return rtc_write(dev, RTC_CTL1_REG_ADDR, RTC_CTL1_BIT_2412);
}
/*
* Reset the RTC
*/
-void rtc_reset (void)
+static int rx8025_rtc_reset(DEV_TYPE *dev)
{
uchar buf[16];
uchar ctl2;
- if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 16))
+#ifdef CONFIG_DM_RTC
+ if (dm_i2c_read(dev, 0, buf, sizeof(buf))) {
+#else
+ if (i2c_read(dev->chip, 0, 0, buf, 16)) {
+#endif
printf("Error reading from RTC\n");
+ return -EIO;
+ }
ctl2 = rtc_read(RTC_CTL2_REG_ADDR);
ctl2 &= ~(RTC_CTL2_BIT_PON | RTC_CTL2_BIT_VDET);
ctl2 |= RTC_CTL2_BIT_XST | RTC_CTL2_BIT_VDSL;
- rtc_write (RTC_CTL2_REG_ADDR, ctl2);
+
+ return rtc_write(dev, RTC_CTL2_REG_ADDR, ctl2);
}
/*
* Helper functions
*/
-static void rtc_write (uchar reg, uchar val)
+static int rtc_write(DEV_TYPE *dev, uchar reg, uchar val)
{
uchar buf[2];
buf[0] = reg << 4;
buf[1] = val;
- if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 2) != 0)
- printf("Error writing to RTC\n");
+#ifdef CONFIG_DM_RTC
+ if (dm_i2c_write(dev, 0, buf, 2)) {
+#else
+ if (i2c_write(dev->chip, 0, 0, buf, 2) != 0) {
+#endif
+ printf("Error writing to RTC\n");
+ return -EIO;
+ }
+
+ return 0;
}
+
+#ifdef CONFIG_DM_RTC
+static int rx8025_probe(struct udevice *dev)
+{
+ uchar buf[16];
+ int ret = 0;
+
+ if (i2c_get_chip_offset_len(dev) != 1)
+ ret = i2c_set_chip_offset_len(dev, 1);
+
+ if (ret)
+ return ret;
+
+ return dm_i2c_read(dev, 0, buf, sizeof(buf));
+}
+
+static const struct rtc_ops rx8025_rtc_ops = {
+ .get = rx8025_rtc_get,
+ .set = rx8025_rtc_set,
+ .reset = rx8025_rtc_reset,
+};
+
+static const struct udevice_id rx8025_rtc_ids[] = {
+ { .compatible = "epson,rx8025" },
+ { }
+};
+
+U_BOOT_DRIVER(rx8010sj_rtc) = {
+ .name = "rx8025_rtc",
+ .id = UCLASS_RTC,
+ .probe = rx8025_probe,
+ .of_match = rx8025_rtc_ids,
+ .ops = &rx8025_rtc_ops,
+};
+#else
+int rtc_get(struct rtc_time *tm)
+{
+ struct ludevice dev = {
+ .chip = CONFIG_SYS_I2C_RTC_ADDR,
+ };
+
+ return rx8025_rtc_get(&dev, tm);
+}
+
+int rtc_set(struct rtc_time *tm)
+{
+ struct ludevice dev = {
+ .chip = CONFIG_SYS_I2C_RTC_ADDR,
+ };
+
+ return rx8025_rtc_set(&dev, tm);
+}
+
+void rtc_reset(void)
+{
+ struct ludevice dev = {
+ .chip = CONFIG_SYS_I2C_RTC_ADDR,
+ };
+
+ rx8025_rtc_reset(&dev);
+}
+#endif
diff --git a/drivers/rtc/stm32_rtc.c b/drivers/rtc/stm32_rtc.c
new file mode 100644
index 0000000..2674714
--- /dev/null
+++ b/drivers/rtc/stm32_rtc.c
@@ -0,0 +1,328 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
+ */
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <rtc.h>
+#include <asm/io.h>
+#include <linux/iopoll.h>
+
+#define STM32_RTC_TR 0x00
+#define STM32_RTC_DR 0x04
+#define STM32_RTC_ISR 0x0C
+#define STM32_RTC_PRER 0x10
+#define STM32_RTC_CR 0x18
+#define STM32_RTC_WPR 0x24
+
+/* STM32_RTC_TR bit fields */
+#define STM32_RTC_SEC_SHIFT 0
+#define STM32_RTC_SEC GENMASK(6, 0)
+#define STM32_RTC_MIN_SHIFT 8
+#define STM32_RTC_MIN GENMASK(14, 8)
+#define STM32_RTC_HOUR_SHIFT 16
+#define STM32_RTC_HOUR GENMASK(21, 16)
+
+/* STM32_RTC_DR bit fields */
+#define STM32_RTC_DATE_SHIFT 0
+#define STM32_RTC_DATE GENMASK(5, 0)
+#define STM32_RTC_MONTH_SHIFT 8
+#define STM32_RTC_MONTH GENMASK(12, 8)
+#define STM32_RTC_WDAY_SHIFT 13
+#define STM32_RTC_WDAY GENMASK(15, 13)
+#define STM32_RTC_YEAR_SHIFT 16
+#define STM32_RTC_YEAR GENMASK(23, 16)
+
+/* STM32_RTC_CR bit fields */
+#define STM32_RTC_CR_FMT BIT(6)
+
+/* STM32_RTC_ISR/STM32_RTC_ICSR bit fields */
+#define STM32_RTC_ISR_INITS BIT(4)
+#define STM32_RTC_ISR_RSF BIT(5)
+#define STM32_RTC_ISR_INITF BIT(6)
+#define STM32_RTC_ISR_INIT BIT(7)
+
+/* STM32_RTC_PRER bit fields */
+#define STM32_RTC_PRER_PRED_S_SHIFT 0
+#define STM32_RTC_PRER_PRED_S GENMASK(14, 0)
+#define STM32_RTC_PRER_PRED_A_SHIFT 16
+#define STM32_RTC_PRER_PRED_A GENMASK(22, 16)
+
+/* STM32_RTC_WPR key constants */
+#define RTC_WPR_1ST_KEY 0xCA
+#define RTC_WPR_2ND_KEY 0x53
+#define RTC_WPR_WRONG_KEY 0xFF
+
+struct stm32_rtc_priv {
+ fdt_addr_t base;
+};
+
+static int stm32_rtc_get(struct udevice *dev, struct rtc_time *tm)
+{
+ struct stm32_rtc_priv *priv = dev_get_priv(dev);
+ u32 tr, dr;
+
+ tr = readl(priv->base + STM32_RTC_TR);
+ dr = readl(priv->base + STM32_RTC_DR);
+
+ tm->tm_sec = bcd2bin((tr & STM32_RTC_SEC) >> STM32_RTC_SEC_SHIFT);
+ tm->tm_min = bcd2bin((tr & STM32_RTC_MIN) >> STM32_RTC_MIN_SHIFT);
+ tm->tm_hour = bcd2bin((tr & STM32_RTC_HOUR) >> STM32_RTC_HOUR_SHIFT);
+
+ tm->tm_mday = bcd2bin((dr & STM32_RTC_DATE) >> STM32_RTC_DATE_SHIFT);
+ tm->tm_mon = bcd2bin((dr & STM32_RTC_MONTH) >> STM32_RTC_MONTH_SHIFT);
+ tm->tm_year = 2000 +
+ bcd2bin((dr & STM32_RTC_YEAR) >> STM32_RTC_YEAR_SHIFT);
+ tm->tm_wday = bcd2bin((dr & STM32_RTC_WDAY) >> STM32_RTC_WDAY_SHIFT);
+ tm->tm_yday = 0;
+ tm->tm_isdst = 0;
+
+ dev_dbg(dev, "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
+ tm->tm_hour, tm->tm_min, tm->tm_sec);
+
+ return 0;
+}
+
+static void stm32_rtc_unlock(struct udevice *dev)
+{
+ struct stm32_rtc_priv *priv = dev_get_priv(dev);
+
+ writel(RTC_WPR_1ST_KEY, priv->base + STM32_RTC_WPR);
+ writel(RTC_WPR_2ND_KEY, priv->base + STM32_RTC_WPR);
+}
+
+static void stm32_rtc_lock(struct udevice *dev)
+{
+ struct stm32_rtc_priv *priv = dev_get_priv(dev);
+
+ writel(RTC_WPR_WRONG_KEY, priv->base + STM32_RTC_WPR);
+}
+
+static int stm32_rtc_enter_init_mode(struct udevice *dev)
+{
+ struct stm32_rtc_priv *priv = dev_get_priv(dev);
+ u32 isr = readl(priv->base + STM32_RTC_ISR);
+
+ if (!(isr & STM32_RTC_ISR_INITF)) {
+ isr |= STM32_RTC_ISR_INIT;
+ writel(isr, priv->base + STM32_RTC_ISR);
+
+ return readl_poll_timeout(priv->base + STM32_RTC_ISR,
+ isr,
+ (isr & STM32_RTC_ISR_INITF),
+ 100000);
+ }
+
+ return 0;
+}
+
+static int stm32_rtc_wait_sync(struct udevice *dev)
+{
+ struct stm32_rtc_priv *priv = dev_get_priv(dev);
+ u32 isr = readl(priv->base + STM32_RTC_ISR);
+
+ isr &= ~STM32_RTC_ISR_RSF;
+ writel(isr, priv->base + STM32_RTC_ISR);
+
+ /*
+ * Wait for RSF to be set to ensure the calendar registers are
+ * synchronised, it takes around 2 rtc_ck clock cycles
+ */
+ return readl_poll_timeout(priv->base + STM32_RTC_ISR,
+ isr, (isr & STM32_RTC_ISR_RSF),
+ 100000);
+}
+
+static void stm32_rtc_exit_init_mode(struct udevice *dev)
+{
+ struct stm32_rtc_priv *priv = dev_get_priv(dev);
+ u32 isr = readl(priv->base + STM32_RTC_ISR);
+
+ isr &= ~STM32_RTC_ISR_INIT;
+ writel(isr, priv->base + STM32_RTC_ISR);
+}
+
+static int stm32_rtc_set_time(struct udevice *dev, u32 time, u32 date)
+{
+ struct stm32_rtc_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ stm32_rtc_unlock(dev);
+
+ ret = stm32_rtc_enter_init_mode(dev);
+ if (ret)
+ goto lock;
+
+ writel(time, priv->base + STM32_RTC_TR);
+ writel(date, priv->base + STM32_RTC_DR);
+
+ stm32_rtc_exit_init_mode(dev);
+
+ ret = stm32_rtc_wait_sync(dev);
+
+lock:
+ stm32_rtc_lock(dev);
+ return ret;
+}
+
+static int stm32_rtc_set(struct udevice *dev, const struct rtc_time *tm)
+{
+ u32 t, d;
+
+ dev_dbg(dev, "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
+ tm->tm_hour, tm->tm_min, tm->tm_sec);
+
+ if (tm->tm_year < 2000 || tm->tm_year > 2099)
+ return -EINVAL;
+
+ /* Time in BCD format */
+ t = (bin2bcd(tm->tm_sec) << STM32_RTC_SEC_SHIFT) & STM32_RTC_SEC;
+ t |= (bin2bcd(tm->tm_min) << STM32_RTC_MIN_SHIFT) & STM32_RTC_MIN;
+ t |= (bin2bcd(tm->tm_hour) << STM32_RTC_HOUR_SHIFT) & STM32_RTC_HOUR;
+
+ /* Date in BCD format */
+ d = (bin2bcd(tm->tm_mday) << STM32_RTC_DATE_SHIFT) & STM32_RTC_DATE;
+ d |= (bin2bcd(tm->tm_mon) << STM32_RTC_MONTH_SHIFT) & STM32_RTC_MONTH;
+ d |= (bin2bcd(tm->tm_year - 2000) << STM32_RTC_YEAR_SHIFT) &
+ STM32_RTC_YEAR;
+ d |= (bin2bcd(tm->tm_wday) << STM32_RTC_WDAY_SHIFT) & STM32_RTC_WDAY;
+
+ return stm32_rtc_set_time(dev, t, d);
+}
+
+static int stm32_rtc_reset(struct udevice *dev)
+{
+ dev_dbg(dev, "Reset DATE\n");
+
+ return stm32_rtc_set_time(dev, 0, 0);
+}
+
+static int stm32_rtc_init(struct udevice *dev)
+{
+ struct stm32_rtc_priv *priv = dev_get_priv(dev);
+ unsigned int prer, pred_a, pred_s, pred_a_max, pred_s_max, cr;
+ unsigned int rate;
+ struct clk clk;
+ int ret;
+ u32 isr = readl(priv->base + STM32_RTC_ISR);
+
+ if (isr & STM32_RTC_ISR_INITS)
+ return 0;
+
+ ret = clk_get_by_index(dev, 1, &clk);
+ if (ret)
+ return ret;
+
+ ret = clk_enable(&clk);
+ if (ret) {
+ clk_free(&clk);
+ return ret;
+ }
+
+ rate = clk_get_rate(&clk);
+
+ /* Find prediv_a and prediv_s to obtain the 1Hz calendar clock */
+ pred_a_max = STM32_RTC_PRER_PRED_A >> STM32_RTC_PRER_PRED_A_SHIFT;
+ pred_s_max = STM32_RTC_PRER_PRED_S >> STM32_RTC_PRER_PRED_S_SHIFT;
+
+ for (pred_a = pred_a_max; pred_a + 1 > 0; pred_a--) {
+ pred_s = (rate / (pred_a + 1)) - 1;
+
+ if (((pred_s + 1) * (pred_a + 1)) == rate)
+ break;
+ }
+
+ /*
+ * Can't find a 1Hz, so give priority to RTC power consumption
+ * by choosing the higher possible value for prediv_a
+ */
+ if (pred_s > pred_s_max || pred_a > pred_a_max) {
+ pred_a = pred_a_max;
+ pred_s = (rate / (pred_a + 1)) - 1;
+ }
+
+ stm32_rtc_unlock(dev);
+
+ ret = stm32_rtc_enter_init_mode(dev);
+ if (ret) {
+ dev_err(dev,
+ "Can't enter in init mode. Prescaler config failed.\n");
+ goto unlock;
+ }
+
+ prer = (pred_s << STM32_RTC_PRER_PRED_S_SHIFT) & STM32_RTC_PRER_PRED_S;
+ prer |= (pred_a << STM32_RTC_PRER_PRED_A_SHIFT) & STM32_RTC_PRER_PRED_A;
+ writel(prer, priv->base + STM32_RTC_PRER);
+
+ /* Force 24h time format */
+ cr = readl(priv->base + STM32_RTC_CR);
+ cr &= ~STM32_RTC_CR_FMT;
+ writel(cr, priv->base + STM32_RTC_CR);
+
+ stm32_rtc_exit_init_mode(dev);
+
+ ret = stm32_rtc_wait_sync(dev);
+
+unlock:
+ stm32_rtc_lock(dev);
+
+ if (ret) {
+ clk_disable(&clk);
+ clk_free(&clk);
+ }
+
+ return ret;
+}
+
+static int stm32_rtc_probe(struct udevice *dev)
+{
+ struct stm32_rtc_priv *priv = dev_get_priv(dev);
+ struct clk clk;
+ int ret;
+
+ priv->base = dev_read_addr(dev);
+ if (priv->base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret)
+ return ret;
+
+ ret = clk_enable(&clk);
+ if (ret) {
+ clk_free(&clk);
+ return ret;
+ }
+
+ ret = stm32_rtc_init(dev);
+
+ if (ret) {
+ clk_disable(&clk);
+ clk_free(&clk);
+ }
+
+ return ret;
+}
+
+static const struct rtc_ops stm32_rtc_ops = {
+ .get = stm32_rtc_get,
+ .set = stm32_rtc_set,
+ .reset = stm32_rtc_reset,
+};
+
+static const struct udevice_id stm32_rtc_ids[] = {
+ { .compatible = "st,stm32mp1-rtc" },
+ { }
+};
+
+U_BOOT_DRIVER(rtc_stm32) = {
+ .name = "rtc-stm32",
+ .id = UCLASS_RTC,
+ .probe = stm32_rtc_probe,
+ .of_match = stm32_rtc_ids,
+ .ops = &stm32_rtc_ops,
+ .priv_auto_alloc_size = sizeof(struct stm32_rtc_priv),
+};
diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c
index 75900d8..48cb2a2 100644
--- a/drivers/scsi/scsi.c
+++ b/drivers/scsi/scsi.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <dm.h>
+#include <env.h>
#include <pci.h>
#include <scsi.h>
#include <dm/device-internal.h>
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 8a447fd..ae2d819 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -45,7 +45,7 @@
config SPL_SERIAL_PRESENT
bool "Provide a serial driver in SPL"
- depends on DM_SERIAL
+ depends on DM_SERIAL && SPL
default y
help
In very space-constrained devices even the full UART driver is too
@@ -55,7 +55,7 @@
config TPL_SERIAL_PRESENT
bool "Provide a serial driver in TPL"
- depends on DM_SERIAL
+ depends on DM_SERIAL && TPL
default y
help
In very space-constrained devices even the full UART driver is too
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index d4488a2..dcdaede 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -5,7 +5,7 @@
#include <common.h>
#include <dm.h>
-#include <environment.h>
+#include <env_internal.h>
#include <errno.h>
#include <os.h>
#include <serial.h>
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index 09365ba..b907508 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -5,7 +5,7 @@
*/
#include <common.h>
-#include <environment.h>
+#include <env_internal.h>
#include <serial.h>
#include <stdio_dev.h>
#include <post.h>
diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index a357b00..4b0a964 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
+ * Copyright 2019 NXP
* Copyright 2013 Freescale Semiconductor, Inc.
*/
@@ -105,7 +106,7 @@
return CONFIG_SYS_CLK_FREQ;
}
-#if IS_ENABLED(CONFIG_CLK)
+#if CONFIG_IS_ENABLED(CLK)
static int get_lpuart_clk_rate(struct udevice *dev, u32 *clk)
{
struct clk per_clk;
@@ -147,7 +148,7 @@
u16 sbr;
int ret;
- if (IS_ENABLED(CONFIG_CLK)) {
+ if (CONFIG_IS_ENABLED(CLK)) {
ret = get_lpuart_clk_rate(dev, &clk);
if (ret)
return;
@@ -236,7 +237,7 @@
u32 clk;
int ret;
- if (IS_ENABLED(CONFIG_CLK)) {
+ if (CONFIG_IS_ENABLED(CLK)) {
ret = get_lpuart_clk_rate(dev, &clk);
if (ret)
return;
@@ -305,7 +306,7 @@
u32 sbr;
int ret;
- if (IS_ENABLED(CONFIG_CLK)) {
+ if (CONFIG_IS_ENABLED(CLK)) {
ret = get_lpuart_clk_rate(dev, &clk);
if (ret)
return;
@@ -502,6 +503,9 @@
plat->reg = (void *)addr;
plat->flags = dev_get_driver_data(dev);
+ if (fdtdec_get_bool(blob, node, "little-endian"))
+ plat->flags &= ~LPUART_FLAG_REGMAP_ENDIAN_BIG;
+
if (!fdt_node_check_compatible(blob, node, "fsl,ls1021a-lpuart"))
plat->devtype = DEV_LS1021A;
else if (!fdt_node_check_compatible(blob, node, "fsl,imx7ulp-lpuart"))
diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index a435e68..42abb96 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -342,6 +342,8 @@
}
static const struct udevice_id mxc_serial_ids[] = {
+ { .compatible = "fsl,imx21-uart" },
+ { .compatible = "fsl,imx53-uart" },
{ .compatible = "fsl,imx6sx-uart" },
{ .compatible = "fsl,imx6ul-uart" },
{ .compatible = "fsl,imx7d-uart" },
@@ -360,9 +362,7 @@
#endif
.probe = mxc_serial_probe,
.ops = &mxc_serial_ops,
-#if !CONFIG_IS_ENABLED(OF_CONTROL)
.flags = DM_FLAG_PRE_RELOC,
-#endif
};
#endif
diff --git a/drivers/serial/serial_sifive.c b/drivers/serial/serial_sifive.c
index fdfef69..c142ccd 100644
--- a/drivers/serial/serial_sifive.c
+++ b/drivers/serial/serial_sifive.c
@@ -22,6 +22,9 @@
#define UART_TXCTRL_TXEN 0x1
#define UART_RXCTRL_RXEN 0x1
+/* IP register */
+#define UART_IP_RXWM 0x2
+
struct uart_sifive {
u32 txfifo;
u32 rxfifo;
@@ -34,7 +37,6 @@
struct sifive_uart_platdata {
unsigned long clock;
- int saved_input_char;
struct uart_sifive *regs;
};
@@ -94,7 +96,7 @@
return -EAGAIN;
ch &= UART_RXFIFO_DATA;
- return (!ch) ? -EAGAIN : ch;
+ return ch;
}
static int sifive_serial_setbrg(struct udevice *dev, int baudrate)
@@ -133,7 +135,6 @@
if (gd->flags & GD_FLG_RELOC)
return 0;
- platdata->saved_input_char = 0;
_sifive_serial_init(platdata->regs);
return 0;
@@ -145,12 +146,6 @@
struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
struct uart_sifive *regs = platdata->regs;
- if (platdata->saved_input_char > 0) {
- c = platdata->saved_input_char;
- platdata->saved_input_char = 0;
- return c;
- }
-
while ((c = _sifive_serial_getc(regs)) == -EAGAIN) ;
return c;
@@ -171,14 +166,10 @@
struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
struct uart_sifive *regs = platdata->regs;
- if (input) {
- if (platdata->saved_input_char > 0)
- return 1;
- platdata->saved_input_char = _sifive_serial_getc(regs);
- return (platdata->saved_input_char > 0) ? 1 : 0;
- } else {
+ if (input)
+ return (readl(®s->ip) & UART_IP_RXWM);
+ else
return !!(readl(®s->txfifo) & UART_TXFIFO_FULL);
- }
}
static int sifive_serial_ofdata_to_platdata(struct udevice *dev)
diff --git a/drivers/serial/serial_stm32.c b/drivers/serial/serial_stm32.c
index cca8b70..00a8e72 100644
--- a/drivers/serial/serial_stm32.c
+++ b/drivers/serial/serial_stm32.c
@@ -106,10 +106,11 @@
if ((isr & USART_ISR_RXNE) == 0)
return -EAGAIN;
- if (isr & (USART_ISR_PE | USART_ISR_ORE)) {
+ if (isr & (USART_ISR_PE | USART_ISR_ORE | USART_ISR_FE)) {
if (!stm32f4)
setbits_le32(base + ICR_OFFSET,
- USART_ICR_PCECF | USART_ICR_ORECF);
+ USART_ICR_PCECF | USART_ICR_ORECF |
+ USART_ICR_FECF);
else
readl(base + RDR_OFFSET(stm32f4));
return -EIO;
@@ -195,9 +196,9 @@
}
plat->clock_rate = clk_get_rate(&clk);
- if (plat->clock_rate < 0) {
+ if (!plat->clock_rate) {
clk_disable(&clk);
- return plat->clock_rate;
+ return -EINVAL;
};
_stm32_serial_init(plat->base, plat->uart_info);
diff --git a/drivers/serial/serial_stm32.h b/drivers/serial/serial_stm32.h
index 5549f8c..7b0c531 100644
--- a/drivers/serial/serial_stm32.h
+++ b/drivers/serial/serial_stm32.h
@@ -67,6 +67,7 @@
#define USART_ISR_TXE BIT(7)
#define USART_ISR_RXNE BIT(5)
#define USART_ISR_ORE BIT(3)
+#define USART_ISR_FE BIT(1)
#define USART_ISR_PE BIT(0)
#define USART_BRR_F_MASK GENMASK(7, 0)
@@ -74,6 +75,7 @@
#define USART_BRR_M_MASK GENMASK(15, 4)
#define USART_ICR_ORECF BIT(3)
+#define USART_ICR_FECF BIT(1)
#define USART_ICR_PCECF BIT(0)
#endif
diff --git a/drivers/serial/usbtty.c b/drivers/serial/usbtty.c
index d0465b8..76d9c8a 100644
--- a/drivers/serial/usbtty.c
+++ b/drivers/serial/usbtty.c
@@ -10,6 +10,7 @@
#include <common.h>
#include <config.h>
#include <circbuf.h>
+#include <env.h>
#include <stdio_dev.h>
#include <asm/unaligned.h>
#include "usbtty.h"
diff --git a/drivers/soc/ti/k3-navss-ringacc.c b/drivers/soc/ti/k3-navss-ringacc.c
index fcb84f7..64ebc0b 100644
--- a/drivers/soc/ti/k3-navss-ringacc.c
+++ b/drivers/soc/ti/k3-navss-ringacc.c
@@ -366,8 +366,10 @@
if (!ring || !(ring->flags & KNAV_RING_FLAG_BUSY))
return;
- if (!ring->parent->dma_ring_reset_quirk)
+ if (!ring->parent->dma_ring_reset_quirk) {
+ k3_nav_ringacc_ring_reset(ring);
return;
+ }
if (!occ)
occ = ringacc_readl(&ring->rt->occ);
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 9469147..8dd3213 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -49,6 +49,14 @@
uses driver model and requires a device tree binding to operate.
please refer to doc/device-tree-bindings/spi/spi-ath79.txt.
+config ATMEL_QSPI
+ bool "Atmel Quad SPI Controller"
+ depends on ARCH_AT91
+ help
+ Enable the Atmel Quad SPI controller in master mode. This driver
+ does not support generic SPI. The implementation supports only the
+ spi-mem interface.
+
config ATMEL_SPI
bool "Atmel SPI driver"
default y if ARCH_AT91
@@ -150,13 +158,14 @@
the SPI NOR flash on platforms embedding this Ralink / MediaTek
SPI core, like MT7621/7628/7688.
-config MTK_QSPI
- bool "Mediatek QSPI driver"
- imply SPI_FLASH_BAR
+config MTK_SNFI_SPI
+ bool "Mediatek SPI memory controller driver"
+ depends on SPI_MEM
help
- Enable the Mediatek QSPI driver. This driver can be
- used to access the SPI NOR flash on platforms embedding this
- Mediatek QSPI IP core.
+ Enable the Mediatek SPI memory controller driver. This driver is
+ originally based on the MediaTek SNFI IP core. It can only be
+ used to access SPI memory devices like SPI-NOR or SPI-NAND on
+ platforms embedding this IP core, like MT7622/M7629.
config MVEBU_A3700_SPI
bool "Marvell Armada 3700 SPI driver"
@@ -218,12 +227,20 @@
cs-gpios = <0>, <&gpio_a 0>;
flash@0 {
reg = <0>;
- compatible = "spansion,m25p16", "sandbox,spi-flash";
+ compatible = "spansion,m25p16", "jedec,spi-nor";
spi-max-frequency = <40000000>;
sandbox,filename = "spi.bin";
};
};
+config SPI_SIFIVE
+ bool "SiFive SPI driver"
+ help
+ This driver supports the SiFive SPI IP. If unsure say N.
+ Enable the SiFive SPI controller driver.
+
+ The SiFive SPI controller driver is found on various SiFive SoCs.
+
config SPI_SUNXI
bool "Allwinner SoC SPI controllers"
help
@@ -285,6 +302,14 @@
Enable the TI Quad-SPI (QSPI) driver for DRA7xx and AM43xx evms.
This driver support spi flash single, quad and memory reads.
+config UNIPHIER_SPI
+ bool "Socionext UniPhier SPI driver"
+ depends on ARCH_UNIPHIER
+ help
+ Enable the Socionext UniPhier SPI driver. This driver can
+ be used to access SPI chips on platforms embedding this
+ UniPhier IP core.
+
config XILINX_SPI
bool "Xilinx SPI driver"
help
@@ -394,7 +419,6 @@
config MXS_SPI
bool "MXS SPI Driver"
- depends on DEPRECATED
help
Enable the MXS SPI controller driver. This driver can be used
on the i.MX23 and i.MX28 SoCs.
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 3f9f2fa..ae4f295 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -18,6 +18,7 @@
obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
+obj-$(CONFIG_ATMEL_QSPI) += atmel-quadspi.o
obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
obj-$(CONFIG_BCM63XX_HSSPI) += bcm63xx_hsspi.o
obj-$(CONFIG_BCM63XX_SPI) += bcm63xx_spi.o
@@ -36,7 +37,7 @@
obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o
obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o
obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
-obj-$(CONFIG_MTK_QSPI) += mtk_qspi.o
+obj-$(CONFIG_MTK_SNFI_SPI) += mtk_snfi_spi.o
obj-$(CONFIG_MT7621_SPI) += mt7621_spi.o
obj-$(CONFIG_MSCC_BB_SPI) += mscc_bb_spi.o
obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o
@@ -49,6 +50,7 @@
obj-$(CONFIG_RENESAS_RPC_SPI) += renesas_rpc_spi.o
obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o
obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
+obj-$(CONFIG_SPI_SIFIVE) += spi-sifive.o
obj-$(CONFIG_SPI_SUNXI) += spi-sunxi.o
obj-$(CONFIG_SH_SPI) += sh_spi.o
obj-$(CONFIG_SH_QSPI) += sh_qspi.o
@@ -58,6 +60,7 @@
obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
obj-$(CONFIG_TEGRA210_QSPI) += tegra210_qspi.o
+obj-$(CONFIG_UNIPHIER_SPI) += uniphier_spi.o
obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
obj-$(CONFIG_ZYNQ_QSPI) += zynq_qspi.o
diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c
new file mode 100644
index 0000000..7d9a540
--- /dev/null
+++ b/drivers/spi/atmel-quadspi.c
@@ -0,0 +1,536 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Driver for Atmel QSPI Controller
+ *
+ * Copyright (C) 2015 Atmel Corporation
+ * Copyright (C) 2018 Cryptera A/S
+ *
+ * Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
+ * Author: Piotr Bugalski <bugalski.piotr@gmail.com>
+ */
+
+#include <asm/io.h>
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/ioport.h>
+#include <mach/clk.h>
+#include <spi.h>
+#include <spi-mem.h>
+
+/* QSPI register offsets */
+#define QSPI_CR 0x0000 /* Control Register */
+#define QSPI_MR 0x0004 /* Mode Register */
+#define QSPI_RD 0x0008 /* Receive Data Register */
+#define QSPI_TD 0x000c /* Transmit Data Register */
+#define QSPI_SR 0x0010 /* Status Register */
+#define QSPI_IER 0x0014 /* Interrupt Enable Register */
+#define QSPI_IDR 0x0018 /* Interrupt Disable Register */
+#define QSPI_IMR 0x001c /* Interrupt Mask Register */
+#define QSPI_SCR 0x0020 /* Serial Clock Register */
+
+#define QSPI_IAR 0x0030 /* Instruction Address Register */
+#define QSPI_ICR 0x0034 /* Instruction Code Register */
+#define QSPI_WICR 0x0034 /* Write Instruction Code Register */
+#define QSPI_IFR 0x0038 /* Instruction Frame Register */
+#define QSPI_RICR 0x003C /* Read Instruction Code Register */
+
+#define QSPI_SMR 0x0040 /* Scrambling Mode Register */
+#define QSPI_SKR 0x0044 /* Scrambling Key Register */
+
+#define QSPI_WPMR 0x00E4 /* Write Protection Mode Register */
+#define QSPI_WPSR 0x00E8 /* Write Protection Status Register */
+
+#define QSPI_VERSION 0x00FC /* Version Register */
+
+/* Bitfields in QSPI_CR (Control Register) */
+#define QSPI_CR_QSPIEN BIT(0)
+#define QSPI_CR_QSPIDIS BIT(1)
+#define QSPI_CR_SWRST BIT(7)
+#define QSPI_CR_LASTXFER BIT(24)
+
+/* Bitfields in QSPI_MR (Mode Register) */
+#define QSPI_MR_SMM BIT(0)
+#define QSPI_MR_LLB BIT(1)
+#define QSPI_MR_WDRBT BIT(2)
+#define QSPI_MR_SMRM BIT(3)
+#define QSPI_MR_CSMODE_MASK GENMASK(5, 4)
+#define QSPI_MR_CSMODE_NOT_RELOADED (0 << 4)
+#define QSPI_MR_CSMODE_LASTXFER (1 << 4)
+#define QSPI_MR_CSMODE_SYSTEMATICALLY (2 << 4)
+#define QSPI_MR_NBBITS_MASK GENMASK(11, 8)
+#define QSPI_MR_NBBITS(n) ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)
+#define QSPI_MR_DLYBCT_MASK GENMASK(23, 16)
+#define QSPI_MR_DLYBCT(n) (((n) << 16) & QSPI_MR_DLYBCT_MASK)
+#define QSPI_MR_DLYCS_MASK GENMASK(31, 24)
+#define QSPI_MR_DLYCS(n) (((n) << 24) & QSPI_MR_DLYCS_MASK)
+
+/* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR */
+#define QSPI_SR_RDRF BIT(0)
+#define QSPI_SR_TDRE BIT(1)
+#define QSPI_SR_TXEMPTY BIT(2)
+#define QSPI_SR_OVRES BIT(3)
+#define QSPI_SR_CSR BIT(8)
+#define QSPI_SR_CSS BIT(9)
+#define QSPI_SR_INSTRE BIT(10)
+#define QSPI_SR_QSPIENS BIT(24)
+
+#define QSPI_SR_CMD_COMPLETED (QSPI_SR_INSTRE | QSPI_SR_CSR)
+
+/* Bitfields in QSPI_SCR (Serial Clock Register) */
+#define QSPI_SCR_CPOL BIT(0)
+#define QSPI_SCR_CPHA BIT(1)
+#define QSPI_SCR_SCBR_MASK GENMASK(15, 8)
+#define QSPI_SCR_SCBR(n) (((n) << 8) & QSPI_SCR_SCBR_MASK)
+#define QSPI_SCR_DLYBS_MASK GENMASK(23, 16)
+#define QSPI_SCR_DLYBS(n) (((n) << 16) & QSPI_SCR_DLYBS_MASK)
+
+/* Bitfields in QSPI_ICR (Read/Write Instruction Code Register) */
+#define QSPI_ICR_INST_MASK GENMASK(7, 0)
+#define QSPI_ICR_INST(inst) (((inst) << 0) & QSPI_ICR_INST_MASK)
+#define QSPI_ICR_OPT_MASK GENMASK(23, 16)
+#define QSPI_ICR_OPT(opt) (((opt) << 16) & QSPI_ICR_OPT_MASK)
+
+/* Bitfields in QSPI_IFR (Instruction Frame Register) */
+#define QSPI_IFR_WIDTH_MASK GENMASK(2, 0)
+#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0 << 0)
+#define QSPI_IFR_WIDTH_DUAL_OUTPUT (1 << 0)
+#define QSPI_IFR_WIDTH_QUAD_OUTPUT (2 << 0)
+#define QSPI_IFR_WIDTH_DUAL_IO (3 << 0)
+#define QSPI_IFR_WIDTH_QUAD_IO (4 << 0)
+#define QSPI_IFR_WIDTH_DUAL_CMD (5 << 0)
+#define QSPI_IFR_WIDTH_QUAD_CMD (6 << 0)
+#define QSPI_IFR_INSTEN BIT(4)
+#define QSPI_IFR_ADDREN BIT(5)
+#define QSPI_IFR_OPTEN BIT(6)
+#define QSPI_IFR_DATAEN BIT(7)
+#define QSPI_IFR_OPTL_MASK GENMASK(9, 8)
+#define QSPI_IFR_OPTL_1BIT (0 << 8)
+#define QSPI_IFR_OPTL_2BIT (1 << 8)
+#define QSPI_IFR_OPTL_4BIT (2 << 8)
+#define QSPI_IFR_OPTL_8BIT (3 << 8)
+#define QSPI_IFR_ADDRL BIT(10)
+#define QSPI_IFR_TFRTYP_MEM BIT(12)
+#define QSPI_IFR_SAMA5D2_WRITE_TRSFR BIT(13)
+#define QSPI_IFR_CRM BIT(14)
+#define QSPI_IFR_NBDUM_MASK GENMASK(20, 16)
+#define QSPI_IFR_NBDUM(n) (((n) << 16) & QSPI_IFR_NBDUM_MASK)
+#define QSPI_IFR_APBTFRTYP_READ BIT(24) /* Defined in SAM9X60 */
+
+/* Bitfields in QSPI_SMR (Scrambling Mode Register) */
+#define QSPI_SMR_SCREN BIT(0)
+#define QSPI_SMR_RVDIS BIT(1)
+
+/* Bitfields in QSPI_WPMR (Write Protection Mode Register) */
+#define QSPI_WPMR_WPEN BIT(0)
+#define QSPI_WPMR_WPKEY_MASK GENMASK(31, 8)
+#define QSPI_WPMR_WPKEY(wpkey) (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK)
+
+/* Bitfields in QSPI_WPSR (Write Protection Status Register) */
+#define QSPI_WPSR_WPVS BIT(0)
+#define QSPI_WPSR_WPVSRC_MASK GENMASK(15, 8)
+#define QSPI_WPSR_WPVSRC(src) (((src) << 8) & QSPI_WPSR_WPVSRC)
+
+struct atmel_qspi_caps {
+ bool has_qspick;
+ bool has_ricr;
+};
+
+struct atmel_qspi {
+ void __iomem *regs;
+ void __iomem *mem;
+ const struct atmel_qspi_caps *caps;
+ ulong bus_clk_rate;
+ u32 mr;
+};
+
+struct atmel_qspi_mode {
+ u8 cmd_buswidth;
+ u8 addr_buswidth;
+ u8 data_buswidth;
+ u32 config;
+};
+
+static const struct atmel_qspi_mode atmel_qspi_modes[] = {
+ { 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI },
+ { 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT },
+ { 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT },
+ { 1, 2, 2, QSPI_IFR_WIDTH_DUAL_IO },
+ { 1, 4, 4, QSPI_IFR_WIDTH_QUAD_IO },
+ { 2, 2, 2, QSPI_IFR_WIDTH_DUAL_CMD },
+ { 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD },
+};
+
+static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op,
+ const struct atmel_qspi_mode *mode)
+{
+ if (op->cmd.buswidth != mode->cmd_buswidth)
+ return false;
+
+ if (op->addr.nbytes && op->addr.buswidth != mode->addr_buswidth)
+ return false;
+
+ if (op->data.nbytes && op->data.buswidth != mode->data_buswidth)
+ return false;
+
+ return true;
+}
+
+static int atmel_qspi_find_mode(const struct spi_mem_op *op)
+{
+ u32 i;
+
+ for (i = 0; i < ARRAY_SIZE(atmel_qspi_modes); i++)
+ if (atmel_qspi_is_compatible(op, &atmel_qspi_modes[i]))
+ return i;
+
+ return -ENOTSUPP;
+}
+
+static bool atmel_qspi_supports_op(struct spi_slave *slave,
+ const struct spi_mem_op *op)
+{
+ if (atmel_qspi_find_mode(op) < 0)
+ return false;
+
+ /* special case not supported by hardware */
+ if (op->addr.nbytes == 2 && op->cmd.buswidth != op->addr.buswidth &&
+ op->dummy.nbytes == 0)
+ return false;
+
+ return true;
+}
+
+static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
+ const struct spi_mem_op *op, u32 *offset)
+{
+ u32 iar, icr, ifr;
+ u32 dummy_cycles = 0;
+ int mode;
+
+ iar = 0;
+ icr = QSPI_ICR_INST(op->cmd.opcode);
+ ifr = QSPI_IFR_INSTEN;
+
+ mode = atmel_qspi_find_mode(op);
+ if (mode < 0)
+ return mode;
+ ifr |= atmel_qspi_modes[mode].config;
+
+ if (op->dummy.buswidth && op->dummy.nbytes)
+ dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
+
+ /*
+ * The controller allows 24 and 32-bit addressing while NAND-flash
+ * requires 16-bit long. Handling 8-bit long addresses is done using
+ * the option field. For the 16-bit addresses, the workaround depends
+ * of the number of requested dummy bits. If there are 8 or more dummy
+ * cycles, the address is shifted and sent with the first dummy byte.
+ * Otherwise opcode is disabled and the first byte of the address
+ * contains the command opcode (works only if the opcode and address
+ * use the same buswidth). The limitation is when the 16-bit address is
+ * used without enough dummy cycles and the opcode is using a different
+ * buswidth than the address.
+ */
+ if (op->addr.buswidth) {
+ switch (op->addr.nbytes) {
+ case 0:
+ break;
+ case 1:
+ ifr |= QSPI_IFR_OPTEN | QSPI_IFR_OPTL_8BIT;
+ icr |= QSPI_ICR_OPT(op->addr.val & 0xff);
+ break;
+ case 2:
+ if (dummy_cycles < 8 / op->addr.buswidth) {
+ ifr &= ~QSPI_IFR_INSTEN;
+ ifr |= QSPI_IFR_ADDREN;
+ iar = (op->cmd.opcode << 16) |
+ (op->addr.val & 0xffff);
+ } else {
+ ifr |= QSPI_IFR_ADDREN;
+ iar = (op->addr.val << 8) & 0xffffff;
+ dummy_cycles -= 8 / op->addr.buswidth;
+ }
+ break;
+ case 3:
+ ifr |= QSPI_IFR_ADDREN;
+ iar = op->addr.val & 0xffffff;
+ break;
+ case 4:
+ ifr |= QSPI_IFR_ADDREN | QSPI_IFR_ADDRL;
+ iar = op->addr.val & 0x7ffffff;
+ break;
+ default:
+ return -ENOTSUPP;
+ }
+ }
+
+ /* offset of the data access in the QSPI memory space */
+ *offset = iar;
+
+ /* Set number of dummy cycles */
+ if (dummy_cycles)
+ ifr |= QSPI_IFR_NBDUM(dummy_cycles);
+
+ /* Set data enable */
+ if (op->data.nbytes)
+ ifr |= QSPI_IFR_DATAEN;
+
+ /*
+ * If the QSPI controller is set in regular SPI mode, set it in
+ * Serial Memory Mode (SMM).
+ */
+ if (aq->mr != QSPI_MR_SMM) {
+ writel(QSPI_MR_SMM, aq->regs + QSPI_MR);
+ aq->mr = QSPI_MR_SMM;
+ }
+
+ /* Clear pending interrupts */
+ (void)readl(aq->regs + QSPI_SR);
+
+ if (aq->caps->has_ricr) {
+ if (!op->addr.nbytes && op->data.dir == SPI_MEM_DATA_IN)
+ ifr |= QSPI_IFR_APBTFRTYP_READ;
+
+ /* Set QSPI Instruction Frame registers */
+ writel(iar, aq->regs + QSPI_IAR);
+ if (op->data.dir == SPI_MEM_DATA_IN)
+ writel(icr, aq->regs + QSPI_RICR);
+ else
+ writel(icr, aq->regs + QSPI_WICR);
+ writel(ifr, aq->regs + QSPI_IFR);
+ } else {
+ if (op->data.dir == SPI_MEM_DATA_OUT)
+ ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR;
+
+ /* Set QSPI Instruction Frame registers */
+ writel(iar, aq->regs + QSPI_IAR);
+ writel(icr, aq->regs + QSPI_ICR);
+ writel(ifr, aq->regs + QSPI_IFR);
+ }
+
+ return 0;
+}
+
+static int atmel_qspi_exec_op(struct spi_slave *slave,
+ const struct spi_mem_op *op)
+{
+ struct atmel_qspi *aq = dev_get_priv(slave->dev->parent);
+ u32 sr, imr, offset;
+ int err;
+
+ err = atmel_qspi_set_cfg(aq, op, &offset);
+ if (err)
+ return err;
+
+ /* Skip to the final steps if there is no data */
+ if (op->data.nbytes) {
+ /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
+ (void)readl(aq->regs + QSPI_IFR);
+
+ /* Send/Receive data */
+ if (op->data.dir == SPI_MEM_DATA_IN)
+ memcpy_fromio(op->data.buf.in, aq->mem + offset,
+ op->data.nbytes);
+ else
+ memcpy_toio(aq->mem + offset, op->data.buf.out,
+ op->data.nbytes);
+
+ /* Release the chip-select */
+ writel(QSPI_CR_LASTXFER, aq->regs + QSPI_CR);
+ }
+
+ /* Poll INSTruction End and Chip Select Rise flags. */
+ imr = QSPI_SR_INSTRE | QSPI_SR_CSR;
+ return readl_poll_timeout(aq->regs + QSPI_SR, sr, (sr & imr) == imr,
+ 1000000);
+}
+
+static int atmel_qspi_set_speed(struct udevice *bus, uint hz)
+{
+ struct atmel_qspi *aq = dev_get_priv(bus);
+ u32 scr, scbr, mask, new_value;
+
+ /* Compute the QSPI baudrate */
+ scbr = DIV_ROUND_UP(aq->bus_clk_rate, hz);
+ if (scbr > 0)
+ scbr--;
+
+ new_value = QSPI_SCR_SCBR(scbr);
+ mask = QSPI_SCR_SCBR_MASK;
+
+ scr = readl(aq->regs + QSPI_SCR);
+ if ((scr & mask) == new_value)
+ return 0;
+
+ scr = (scr & ~mask) | new_value;
+ writel(scr, aq->regs + QSPI_SCR);
+
+ return 0;
+}
+
+static int atmel_qspi_set_mode(struct udevice *bus, uint mode)
+{
+ struct atmel_qspi *aq = dev_get_priv(bus);
+ u32 scr, mask, new_value = 0;
+
+ if (mode & SPI_CPOL)
+ new_value = QSPI_SCR_CPOL;
+ if (mode & SPI_CPHA)
+ new_value = QSPI_SCR_CPHA;
+
+ mask = QSPI_SCR_CPOL | QSPI_SCR_CPHA;
+
+ scr = readl(aq->regs + QSPI_SCR);
+ if ((scr & mask) == new_value)
+ return 0;
+
+ scr = (scr & ~mask) | new_value;
+ writel(scr, aq->regs + QSPI_SCR);
+
+ return 0;
+}
+
+static int atmel_qspi_enable_clk(struct udevice *dev)
+{
+ struct atmel_qspi *aq = dev_get_priv(dev);
+ struct clk pclk, qspick;
+ int ret;
+
+ ret = clk_get_by_name(dev, "pclk", &pclk);
+ if (ret)
+ ret = clk_get_by_index(dev, 0, &pclk);
+
+ if (ret) {
+ dev_err(dev, "Missing QSPI peripheral clock\n");
+ return ret;
+ }
+
+ ret = clk_enable(&pclk);
+ if (ret) {
+ dev_err(dev, "Failed to enable QSPI peripheral clock\n");
+ goto free_pclk;
+ }
+
+ if (aq->caps->has_qspick) {
+ /* Get the QSPI system clock */
+ ret = clk_get_by_name(dev, "qspick", &qspick);
+ if (ret) {
+ dev_err(dev, "Missing QSPI peripheral clock\n");
+ goto free_pclk;
+ }
+
+ ret = clk_enable(&qspick);
+ if (ret)
+ dev_err(dev, "Failed to enable QSPI system clock\n");
+ clk_free(&qspick);
+ }
+
+ aq->bus_clk_rate = clk_get_rate(&pclk);
+ if (!aq->bus_clk_rate)
+ ret = -EINVAL;
+
+free_pclk:
+ clk_free(&pclk);
+
+ return ret;
+}
+
+static void atmel_qspi_init(struct atmel_qspi *aq)
+{
+ /* Reset the QSPI controller */
+ writel(QSPI_CR_SWRST, aq->regs + QSPI_CR);
+
+ /* Set the QSPI controller by default in Serial Memory Mode */
+ writel(QSPI_MR_SMM, aq->regs + QSPI_MR);
+ aq->mr = QSPI_MR_SMM;
+
+ /* Enable the QSPI controller */
+ writel(QSPI_CR_QSPIEN, aq->regs + QSPI_CR);
+}
+
+static int atmel_qspi_probe(struct udevice *dev)
+{
+ struct atmel_qspi *aq = dev_get_priv(dev);
+ struct resource res;
+ int ret;
+
+ aq->caps = (struct atmel_qspi_caps *)dev_get_driver_data(dev);
+ if (!aq->caps) {
+ dev_err(dev, "Could not retrieve QSPI caps\n");
+ return -EINVAL;
+ };
+
+ /* Map the registers */
+ ret = dev_read_resource_byname(dev, "qspi_base", &res);
+ if (ret) {
+ dev_err(dev, "missing registers\n");
+ return ret;
+ }
+
+ aq->regs = devm_ioremap(dev, res.start, resource_size(&res));
+ if (IS_ERR(aq->regs))
+ return PTR_ERR(aq->regs);
+
+ /* Map the AHB memory */
+ ret = dev_read_resource_byname(dev, "qspi_mmap", &res);
+ if (ret) {
+ dev_err(dev, "missing AHB memory\n");
+ return ret;
+ }
+
+ aq->mem = devm_ioremap(dev, res.start, resource_size(&res));
+ if (IS_ERR(aq->mem))
+ return PTR_ERR(aq->mem);
+
+ ret = atmel_qspi_enable_clk(dev);
+ if (ret)
+ return ret;
+
+ atmel_qspi_init(aq);
+
+ return 0;
+}
+
+static const struct spi_controller_mem_ops atmel_qspi_mem_ops = {
+ .supports_op = atmel_qspi_supports_op,
+ .exec_op = atmel_qspi_exec_op,
+};
+
+static const struct dm_spi_ops atmel_qspi_ops = {
+ .set_speed = atmel_qspi_set_speed,
+ .set_mode = atmel_qspi_set_mode,
+ .mem_ops = &atmel_qspi_mem_ops,
+};
+
+static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = {};
+
+static const struct atmel_qspi_caps atmel_sam9x60_qspi_caps = {
+ .has_qspick = true,
+ .has_ricr = true,
+};
+
+static const struct udevice_id atmel_qspi_ids[] = {
+ {
+ .compatible = "atmel,sama5d2-qspi",
+ .data = (ulong)&atmel_sama5d2_qspi_caps,
+ },
+ {
+ .compatible = "microchip,sam9x60-qspi",
+ .data = (ulong)&atmel_sam9x60_qspi_caps,
+ },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(atmel_qspi) = {
+ .name = "atmel_qspi",
+ .id = UCLASS_SPI,
+ .of_match = atmel_qspi_ids,
+ .ops = &atmel_qspi_ops,
+ .priv_auto_alloc_size = sizeof(struct atmel_qspi),
+ .probe = atmel_qspi_probe,
+};
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 1598c4f..41abe19 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -10,6 +10,7 @@
#include <spi.h>
#include <asm/io.h>
#include <linux/sizes.h>
+#include <linux/iopoll.h>
#include <dm.h>
#include <errno.h>
#include <watchdog.h>
@@ -150,20 +151,13 @@
static inline int is_controller_busy(const struct fsl_qspi_priv *priv)
{
u32 val;
- const u32 mask = QSPI_SR_BUSY_MASK | QSPI_SR_AHB_ACC_MASK |
- QSPI_SR_IP_ACC_MASK;
- unsigned int retry = 5;
+ u32 mask = QSPI_SR_BUSY_MASK | QSPI_SR_AHB_ACC_MASK |
+ QSPI_SR_IP_ACC_MASK;
- do {
- val = qspi_read32(priv->flags, &priv->regs->sr);
+ if (priv->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG)
+ mask = (u32)cpu_to_be32(mask);
- if ((~val & mask) == mask)
- return 0;
-
- udelay(1);
- } while (--retry);
-
- return -ETIMEDOUT;
+ return readl_poll_timeout(&priv->regs->sr, val, !(val & mask), 1000);
}
/* QSPI support swapping the flash read/write data
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index 03531a8..fbb58c7 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -14,6 +14,8 @@
#include <pci_ids.h>
#include <spi.h>
#include <asm/io.h>
+#include <spi-mem.h>
+#include <div64.h>
#include "ich.h"
@@ -171,18 +173,6 @@
return 0;
}
-static inline void spi_use_out(struct spi_trans *trans, unsigned bytes)
-{
- trans->out += bytes;
- trans->bytesout -= bytes;
-}
-
-static inline void spi_use_in(struct spi_trans *trans, unsigned bytes)
-{
- trans->in += bytes;
- trans->bytesin -= bytes;
-}
-
static void spi_lock_down(struct ich_spi_platdata *plat, void *sbase)
{
if (plat->ich_version == ICHV_7) {
@@ -213,47 +203,12 @@
return lock != 0;
}
-static void spi_setup_type(struct spi_trans *trans, int data_bytes)
-{
- trans->type = 0xFF;
-
- /* Try to guess spi type from read/write sizes */
- if (trans->bytesin == 0) {
- if (trans->bytesout + data_bytes > 4)
- /*
- * If bytesin = 0 and bytesout > 4, we presume this is
- * a write data operation, which is accompanied by an
- * address.
- */
- trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
- else
- trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
- return;
- }
-
- if (trans->bytesout == 1) { /* and bytesin is > 0 */
- trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
- return;
- }
-
- if (trans->bytesout == 4) /* and bytesin is > 0 */
- trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
-
- /* Fast read command is called with 5 bytes instead of 4 */
- if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) {
- trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
- --trans->bytesout;
- }
-}
-
static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans,
bool lock)
{
uint16_t optypes;
uint8_t opmenu[ctlr->menubytes];
- trans->opcode = trans->out[0];
- spi_use_out(trans, 1);
if (!lock) {
/* The lock is off, so just use index 0. */
ich_writeb(ctlr, trans->opcode, ctlr->opmenu);
@@ -285,12 +240,7 @@
optypes = ich_readw(ctlr, ctlr->optype);
optype = (optypes >> (opcode_index * 2)) & 0x3;
- if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS &&
- optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS &&
- trans->bytesout >= 3) {
- /* We guessed wrong earlier. Fix it up. */
- trans->type = optype;
- }
+
if (optype != trans->type) {
printf("ICH SPI: Transaction doesn't fit type %d\n",
optype);
@@ -300,26 +250,6 @@
}
}
-static int spi_setup_offset(struct spi_trans *trans)
-{
- /* Separate the SPI address and data */
- switch (trans->type) {
- case SPI_OPCODE_TYPE_READ_NO_ADDRESS:
- case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS:
- return 0;
- case SPI_OPCODE_TYPE_READ_WITH_ADDRESS:
- case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS:
- trans->offset = ((uint32_t)trans->out[0] << 16) |
- ((uint32_t)trans->out[1] << 8) |
- ((uint32_t)trans->out[2] << 0);
- spi_use_out(trans, 3);
- return 1;
- default:
- printf("Unrecognized SPI transaction type %#x\n", trans->type);
- return -EPROTO;
- }
-}
-
/*
* Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set
* below is true) or 0. In case the wait was for the bit(s) to set - write
@@ -350,7 +280,7 @@
return -ETIMEDOUT;
}
-void ich_spi_config_opcode(struct udevice *dev)
+static void ich_spi_config_opcode(struct udevice *dev)
{
struct ich_spi_priv *ctlr = dev_get_priv(dev);
@@ -365,90 +295,38 @@
ich_writel(ctlr, SPI_OPMENU_UPPER, ctlr->opmenu + sizeof(u32));
}
-static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
- const void *dout, void *din, unsigned long flags)
+static int ich_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
{
- struct udevice *bus = dev_get_parent(dev);
+ struct udevice *bus = dev_get_parent(slave->dev);
struct ich_spi_platdata *plat = dev_get_platdata(bus);
struct ich_spi_priv *ctlr = dev_get_priv(bus);
uint16_t control;
int16_t opcode_index;
int with_address;
int status;
- int bytes = bitlen / 8;
struct spi_trans *trans = &ctlr->trans;
- unsigned type = flags & (SPI_XFER_BEGIN | SPI_XFER_END);
- int using_cmd = 0;
bool lock = spi_lock_status(plat, ctlr->base);
- int ret;
+ int ret = 0;
- /* We don't support writing partial bytes */
- if (bitlen % 8) {
- debug("ICH SPI: Accessing partial bytes not supported\n");
- return -EPROTONOSUPPORT;
- }
+ trans->in = NULL;
+ trans->out = NULL;
+ trans->type = 0xFF;
- /* An empty end transaction can be ignored */
- if (type == SPI_XFER_END && !dout && !din)
- return 0;
-
- if (type & SPI_XFER_BEGIN)
- memset(trans, '\0', sizeof(*trans));
-
- /* Dp we need to come back later to finish it? */
- if (dout && type == SPI_XFER_BEGIN) {
- if (bytes > ICH_MAX_CMD_LEN) {
- debug("ICH SPI: Command length limit exceeded\n");
- return -ENOSPC;
+ if (op->data.nbytes) {
+ if (op->data.dir == SPI_MEM_DATA_IN) {
+ trans->in = op->data.buf.in;
+ trans->bytesin = op->data.nbytes;
+ } else {
+ trans->out = op->data.buf.out;
+ trans->bytesout = op->data.nbytes;
}
- memcpy(trans->cmd, dout, bytes);
- trans->cmd_len = bytes;
- debug_trace("ICH SPI: Saved %d bytes\n", bytes);
+ }
+
+ if (trans->opcode != op->cmd.opcode)
+ trans->opcode = op->cmd.opcode;
+
+ if (lock && trans->opcode == SPI_OPCODE_WRDIS)
return 0;
- }
-
- /*
- * We process a 'middle' spi_xfer() call, which has no
- * SPI_XFER_BEGIN/END, as an independent transaction as if it had
- * an end. We therefore repeat the command. This is because ICH
- * seems to have no support for this, or because interest (in digging
- * out the details and creating a special case in the code) is low.
- */
- if (trans->cmd_len) {
- trans->out = trans->cmd;
- trans->bytesout = trans->cmd_len;
- using_cmd = 1;
- debug_trace("ICH SPI: Using %d bytes\n", trans->cmd_len);
- } else {
- trans->out = dout;
- trans->bytesout = dout ? bytes : 0;
- }
-
- trans->in = din;
- trans->bytesin = din ? bytes : 0;
-
- /* There has to always at least be an opcode */
- if (!trans->bytesout) {
- debug("ICH SPI: No opcode for transfer\n");
- return -EPROTO;
- }
-
- ret = ich_status_poll(ctlr, SPIS_SCIP, 0);
- if (ret < 0)
- return ret;
-
- if (plat->ich_version == ICHV_7)
- ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
- else
- ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
-
- spi_setup_type(trans, using_cmd ? bytes : 0);
- opcode_index = spi_setup_opcode(ctlr, trans, lock);
- if (opcode_index < 0)
- return -EINVAL;
- with_address = spi_setup_offset(trans);
- if (with_address < 0)
- return -EINVAL;
if (trans->opcode == SPI_OPCODE_WREN) {
/*
@@ -461,6 +339,40 @@
return 0;
}
+ ret = ich_status_poll(ctlr, SPIS_SCIP, 0);
+ if (ret < 0)
+ return ret;
+
+ if (plat->ich_version == ICHV_7)
+ ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
+ else
+ ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
+
+ /* Try to guess spi transaction type */
+ if (op->data.dir == SPI_MEM_DATA_OUT) {
+ if (op->addr.nbytes)
+ trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
+ else
+ trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
+ } else {
+ if (op->addr.nbytes)
+ trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
+ else
+ trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
+ }
+ /* Special erase case handling */
+ if (op->addr.nbytes && !op->data.buswidth)
+ trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
+
+ opcode_index = spi_setup_opcode(ctlr, trans, lock);
+ if (opcode_index < 0)
+ return -EINVAL;
+
+ if (op->addr.nbytes) {
+ trans->offset = op->addr.val;
+ with_address = 1;
+ }
+
if (ctlr->speed && ctlr->max_speed >= 33000000) {
int byte;
@@ -472,13 +384,6 @@
ich_writeb(ctlr, byte, ctlr->speed);
}
- /* See if we have used up the command data */
- if (using_cmd && dout && bytes) {
- trans->out = dout;
- trans->bytesout = bytes;
- debug_trace("ICH SPI: Moving to data, %d bytes\n", bytes);
- }
-
/* Preset control fields */
control = SPIC_SCGO | ((opcode_index & 0x07) << 4);
@@ -513,22 +418,6 @@
return 0;
}
- /*
- * Check if this is a write command atempting to transfer more bytes
- * than the controller can handle. Iterations for writes are not
- * supported here because each SPI write command needs to be preceded
- * and followed by other SPI commands, and this sequence is controlled
- * by the SPI chip driver.
- */
- if (trans->bytesout > ctlr->databytes) {
- debug("ICH SPI: Too much to write. This should be prevented by the driver's max_write_size?\n");
- return -EPROTO;
- }
-
- /*
- * Read or write up to databytes bytes at a time until everything has
- * been sent.
- */
while (trans->bytesout || trans->bytesin) {
uint32_t data_length;
@@ -543,9 +432,7 @@
/* Program data into FDATA0 to N */
if (trans->bytesout) {
write_reg(ctlr, trans->out, ctlr->data, data_length);
- spi_use_out(trans, data_length);
- if (with_address)
- trans->offset += data_length;
+ trans->bytesout -= data_length;
}
/* Add proper control fields' values */
@@ -568,9 +455,7 @@
if (trans->bytesin) {
read_reg(ctlr, ctlr->data, trans->in, data_length);
- spi_use_in(trans, data_length);
- if (with_address)
- trans->offset += data_length;
+ trans->bytesin -= data_length;
}
}
@@ -581,6 +466,40 @@
return 0;
}
+static int ich_spi_adjust_size(struct spi_slave *slave, struct spi_mem_op *op)
+{
+ unsigned int page_offset;
+ int addr = op->addr.val;
+ unsigned int byte_count = op->data.nbytes;
+
+ if (hweight32(ICH_BOUNDARY) == 1) {
+ page_offset = addr & (ICH_BOUNDARY - 1);
+ } else {
+ u64 aux = addr;
+
+ page_offset = do_div(aux, ICH_BOUNDARY);
+ }
+
+ if (op->data.dir == SPI_MEM_DATA_IN && slave->max_read_size) {
+ op->data.nbytes = min(ICH_BOUNDARY - page_offset,
+ slave->max_read_size);
+ } else if (slave->max_write_size) {
+ op->data.nbytes = min(ICH_BOUNDARY - page_offset,
+ slave->max_write_size);
+ }
+
+ op->data.nbytes = min(op->data.nbytes, byte_count);
+
+ return 0;
+}
+
+static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ printf("ICH SPI: Only supports memory operations\n");
+ return -1;
+}
+
static int ich_spi_probe(struct udevice *dev)
{
struct ich_spi_platdata *plat = dev_get_platdata(dev);
@@ -686,10 +605,17 @@
return ret;
}
+static const struct spi_controller_mem_ops ich_controller_mem_ops = {
+ .adjust_op_size = ich_spi_adjust_size,
+ .supports_op = NULL,
+ .exec_op = ich_spi_exec_op,
+};
+
static const struct dm_spi_ops ich_spi_ops = {
.xfer = ich_spi_xfer,
.set_speed = ich_spi_set_speed,
.set_mode = ich_spi_set_mode,
+ .mem_ops = &ich_controller_mem_ops,
/*
* cs_info is not needed, since we require all chip selects to be
* in the device tree explicitly
diff --git a/drivers/spi/ich.h b/drivers/spi/ich.h
index a974241..3dfb2aa 100644
--- a/drivers/spi/ich.h
+++ b/drivers/spi/ich.h
@@ -100,13 +100,8 @@
HSFC_FSMIE = 0x8000
};
-enum {
- ICH_MAX_CMD_LEN = 5,
-};
-
struct spi_trans {
- uint8_t cmd[ICH_MAX_CMD_LEN];
- int cmd_len;
+ uint8_t cmd;
const uint8_t *out;
uint32_t bytesout;
uint8_t *in;
@@ -166,6 +161,8 @@
#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
(SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0))
+#define ICH_BOUNDARY 0x1000
+
enum ich_version {
ICHV_7,
ICHV_9,
diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c
index 5dd1ad6..c725625 100644
--- a/drivers/spi/kirkwood_spi.c
+++ b/drivers/spi/kirkwood_spi.c
@@ -151,10 +151,6 @@
free(slave);
}
-#if defined(CONFIG_SYS_KW_SPI_MPP)
-u32 spi_mpp_backup[4];
-#endif
-
__attribute__((weak)) int board_spi_claim_bus(struct spi_slave *slave)
{
return 0;
@@ -162,34 +158,6 @@
int spi_claim_bus(struct spi_slave *slave)
{
-#if defined(CONFIG_SYS_KW_SPI_MPP)
- u32 config;
- u32 spi_mpp_config[4];
-
- config = CONFIG_SYS_KW_SPI_MPP;
-
- if (config & MOSI_MPP6)
- spi_mpp_config[0] = MPP6_SPI_MOSI;
- else
- spi_mpp_config[0] = MPP1_SPI_MOSI;
-
- if (config & SCK_MPP10)
- spi_mpp_config[1] = MPP10_SPI_SCK;
- else
- spi_mpp_config[1] = MPP2_SPI_SCK;
-
- if (config & MISO_MPP11)
- spi_mpp_config[2] = MPP11_SPI_MISO;
- else
- spi_mpp_config[2] = MPP3_SPI_MISO;
-
- spi_mpp_config[3] = 0;
- spi_mpp_backup[3] = 0;
-
- /* set new spi mpp and save current mpp config */
- kirkwood_mpp_conf(spi_mpp_config, spi_mpp_backup);
-#endif
-
return board_spi_claim_bus(slave);
}
@@ -199,10 +167,6 @@
void spi_release_bus(struct spi_slave *slave)
{
-#if defined(CONFIG_SYS_KW_SPI_MPP)
- kirkwood_mpp_conf(spi_mpp_backup, NULL);
-#endif
-
board_spi_release_bus(slave);
}
@@ -338,6 +302,11 @@
return _spi_xfer(plat->spireg, bitlen, dout, din, flags);
}
+__attribute__((weak)) int mvebu_board_spi_claim_bus(struct udevice *dev)
+{
+ return 0;
+}
+
static int mvebu_spi_claim_bus(struct udevice *dev)
{
struct udevice *bus = dev->parent;
@@ -348,9 +317,19 @@
KWSPI_CS_MASK << KWSPI_CS_SHIFT,
spi_chip_select(dev) << KWSPI_CS_SHIFT);
+ return mvebu_board_spi_claim_bus(dev);
+}
+
+__attribute__((weak)) int mvebu_board_spi_release_bus(struct udevice *dev)
+{
return 0;
}
+static int mvebu_spi_release_bus(struct udevice *dev)
+{
+ return mvebu_board_spi_release_bus(dev);
+}
+
static int mvebu_spi_probe(struct udevice *bus)
{
struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
@@ -377,6 +356,7 @@
static const struct dm_spi_ops mvebu_spi_ops = {
.claim_bus = mvebu_spi_claim_bus,
+ .release_bus = mvebu_spi_release_bus,
.xfer = mvebu_spi_xfer,
.set_speed = mvebu_spi_set_speed,
.set_mode = mvebu_spi_set_mode,
diff --git a/drivers/spi/mtk_qspi.c b/drivers/spi/mtk_qspi.c
deleted file mode 100644
index b510733..0000000
--- a/drivers/spi/mtk_qspi.c
+++ /dev/null
@@ -1,359 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2018 MediaTek, Inc.
- * Author : Guochun.Mao@mediatek.com
- */
-
-#include <common.h>
-#include <dm.h>
-#include <malloc.h>
-#include <spi.h>
-#include <asm/io.h>
-#include <linux/iopoll.h>
-#include <linux/ioport.h>
-
-/* Register Offset */
-struct mtk_qspi_regs {
- u32 cmd;
- u32 cnt;
- u32 rdsr;
- u32 rdata;
- u32 radr[3];
- u32 wdata;
- u32 prgdata[6];
- u32 shreg[10];
- u32 cfg[2];
- u32 shreg10;
- u32 mode_mon;
- u32 status[4];
- u32 flash_time;
- u32 flash_cfg;
- u32 reserved_0[3];
- u32 sf_time;
- u32 pp_dw_data;
- u32 reserved_1;
- u32 delsel_0[2];
- u32 intrstus;
- u32 intren;
- u32 reserved_2;
- u32 cfg3;
- u32 reserved_3;
- u32 chksum;
- u32 aaicmd;
- u32 wrprot;
- u32 radr3;
- u32 dual;
- u32 delsel_1[3];
-};
-
-struct mtk_qspi_platdata {
- fdt_addr_t reg_base;
- fdt_addr_t mem_base;
-};
-
-struct mtk_qspi_priv {
- struct mtk_qspi_regs *regs;
- unsigned long *mem_base;
- u8 op;
- u8 tx[3]; /* only record max 3 bytes paras, when it's address. */
- u32 txlen; /* dout buffer length - op code length */
- u8 *rx;
- u32 rxlen;
-};
-
-#define MTK_QSPI_CMD_POLLINGREG_US 500000
-#define MTK_QSPI_WRBUF_SIZE 256
-#define MTK_QSPI_COMMAND_ENABLE 0x30
-
-/* NOR flash controller commands */
-#define MTK_QSPI_RD_TRIGGER BIT(0)
-#define MTK_QSPI_READSTATUS BIT(1)
-#define MTK_QSPI_PRG_CMD BIT(2)
-#define MTK_QSPI_WR_TRIGGER BIT(4)
-#define MTK_QSPI_WRITESTATUS BIT(5)
-#define MTK_QSPI_AUTOINC BIT(7)
-
-#define MTK_QSPI_MAX_RX_TX_SHIFT 0x6
-#define MTK_QSPI_MAX_SHIFT 0x8
-
-#define MTK_QSPI_WR_BUF_ENABLE 0x1
-#define MTK_QSPI_WR_BUF_DISABLE 0x0
-
-static int mtk_qspi_execute_cmd(struct mtk_qspi_priv *priv, u8 cmd)
-{
- u8 tmp;
- u8 val = cmd & ~MTK_QSPI_AUTOINC;
-
- writeb(cmd, &priv->regs->cmd);
-
- return readb_poll_timeout(&priv->regs->cmd, tmp, !(val & tmp),
- MTK_QSPI_CMD_POLLINGREG_US);
-}
-
-static int mtk_qspi_tx_rx(struct mtk_qspi_priv *priv)
-{
- int len = 1 + priv->txlen + priv->rxlen;
- int i, ret, idx;
-
- if (len > MTK_QSPI_MAX_SHIFT)
- return -ERR_INVAL;
-
- writeb(len * 8, &priv->regs->cnt);
-
- /* start at PRGDATA5, go down to PRGDATA0 */
- idx = MTK_QSPI_MAX_RX_TX_SHIFT - 1;
-
- /* opcode */
- writeb(priv->op, &priv->regs->prgdata[idx]);
- idx--;
-
- /* program TX data */
- for (i = 0; i < priv->txlen; i++, idx--)
- writeb(priv->tx[i], &priv->regs->prgdata[idx]);
-
- /* clear out rest of TX registers */
- while (idx >= 0) {
- writeb(0, &priv->regs->prgdata[idx]);
- idx--;
- }
-
- ret = mtk_qspi_execute_cmd(priv, MTK_QSPI_PRG_CMD);
- if (ret)
- return ret;
-
- /* restart at first RX byte */
- idx = priv->rxlen - 1;
-
- /* read out RX data */
- for (i = 0; i < priv->rxlen; i++, idx--)
- priv->rx[i] = readb(&priv->regs->shreg[idx]);
-
- return 0;
-}
-
-static int mtk_qspi_read(struct mtk_qspi_priv *priv,
- u32 addr, u8 *buf, u32 len)
-{
- memcpy(buf, (u8 *)priv->mem_base + addr, len);
- return 0;
-}
-
-static void mtk_qspi_set_addr(struct mtk_qspi_priv *priv, u32 addr)
-{
- int i;
-
- for (i = 0; i < 3; i++) {
- writeb(addr & 0xff, &priv->regs->radr[i]);
- addr >>= 8;
- }
-}
-
-static int mtk_qspi_write_single_byte(struct mtk_qspi_priv *priv,
- u32 addr, u32 length, const u8 *data)
-{
- int i, ret;
-
- mtk_qspi_set_addr(priv, addr);
-
- for (i = 0; i < length; i++) {
- writeb(*data++, &priv->regs->wdata);
- ret = mtk_qspi_execute_cmd(priv, MTK_QSPI_WR_TRIGGER);
- if (ret < 0)
- return ret;
- }
- return 0;
-}
-
-static int mtk_qspi_write_buffer(struct mtk_qspi_priv *priv, u32 addr,
- const u8 *buf)
-{
- int i, data;
-
- mtk_qspi_set_addr(priv, addr);
-
- for (i = 0; i < MTK_QSPI_WRBUF_SIZE; i += 4) {
- data = buf[i + 3] << 24 | buf[i + 2] << 16 |
- buf[i + 1] << 8 | buf[i];
- writel(data, &priv->regs->pp_dw_data);
- }
-
- return mtk_qspi_execute_cmd(priv, MTK_QSPI_WR_TRIGGER);
-}
-
-static int mtk_qspi_write(struct mtk_qspi_priv *priv,
- u32 addr, const u8 *buf, u32 len)
-{
- int ret;
-
- /* setting pre-fetch buffer for page program */
- writel(MTK_QSPI_WR_BUF_ENABLE, &priv->regs->cfg[1]);
- while (len >= MTK_QSPI_WRBUF_SIZE) {
- ret = mtk_qspi_write_buffer(priv, addr, buf);
- if (ret < 0)
- return ret;
-
- len -= MTK_QSPI_WRBUF_SIZE;
- addr += MTK_QSPI_WRBUF_SIZE;
- buf += MTK_QSPI_WRBUF_SIZE;
- }
- /* disable pre-fetch buffer for page program */
- writel(MTK_QSPI_WR_BUF_DISABLE, &priv->regs->cfg[1]);
-
- if (len)
- return mtk_qspi_write_single_byte(priv, addr, len, buf);
-
- return 0;
-}
-
-static int mtk_qspi_claim_bus(struct udevice *dev)
-{
- /* nothing to do */
- return 0;
-}
-
-static int mtk_qspi_release_bus(struct udevice *dev)
-{
- /* nothing to do */
- return 0;
-}
-
-static int mtk_qspi_transfer(struct mtk_qspi_priv *priv, unsigned int bitlen,
- const void *dout, void *din, unsigned long flags)
-{
- u32 bytes = DIV_ROUND_UP(bitlen, 8);
- u32 addr;
-
- if (!bytes)
- return -ERR_INVAL;
-
- if (dout) {
- if (flags & SPI_XFER_BEGIN) {
- /* parse op code and potential paras first */
- priv->op = *(u8 *)dout;
- if (bytes > 1)
- memcpy(priv->tx, (u8 *)dout + 1,
- bytes <= 4 ? bytes - 1 : 3);
- priv->txlen = bytes - 1;
- }
-
- if (flags == SPI_XFER_ONCE) {
- /* operations without receiving or sending data.
- * for example: erase, write flash register or write
- * enable...
- */
- priv->rx = NULL;
- priv->rxlen = 0;
- return mtk_qspi_tx_rx(priv);
- }
-
- if (flags & SPI_XFER_END) {
- /* here, dout should be data to be written.
- * and priv->tx should be filled 3Bytes address.
- */
- addr = priv->tx[0] << 16 | priv->tx[1] << 8 |
- priv->tx[2];
- return mtk_qspi_write(priv, addr, (u8 *)dout, bytes);
- }
- }
-
- if (din) {
- if (priv->txlen >= 3) {
- /* if run to here, priv->tx[] should be the address
- * where read data from,
- * and, din is the buf to receive data.
- */
- addr = priv->tx[0] << 16 | priv->tx[1] << 8 |
- priv->tx[2];
- return mtk_qspi_read(priv, addr, (u8 *)din, bytes);
- }
-
- /* should be reading flash's register */
- priv->rx = (u8 *)din;
- priv->rxlen = bytes;
- return mtk_qspi_tx_rx(priv);
- }
-
- return 0;
-}
-
-static int mtk_qspi_xfer(struct udevice *dev, unsigned int bitlen,
- const void *dout, void *din, unsigned long flags)
-{
- struct udevice *bus = dev->parent;
- struct mtk_qspi_priv *priv = dev_get_priv(bus);
-
- return mtk_qspi_transfer(priv, bitlen, dout, din, flags);
-}
-
-static int mtk_qspi_set_speed(struct udevice *bus, uint speed)
-{
- /* nothing to do */
- return 0;
-}
-
-static int mtk_qspi_set_mode(struct udevice *bus, uint mode)
-{
- /* nothing to do */
- return 0;
-}
-
-static int mtk_qspi_ofdata_to_platdata(struct udevice *bus)
-{
- struct resource res_reg, res_mem;
- struct mtk_qspi_platdata *plat = bus->platdata;
- int ret;
-
- ret = dev_read_resource_byname(bus, "reg_base", &res_reg);
- if (ret) {
- debug("can't get reg_base resource(ret = %d)\n", ret);
- return -ENOMEM;
- }
-
- ret = dev_read_resource_byname(bus, "mem_base", &res_mem);
- if (ret) {
- debug("can't get map_base resource(ret = %d)\n", ret);
- return -ENOMEM;
- }
-
- plat->mem_base = res_mem.start;
- plat->reg_base = res_reg.start;
-
- return 0;
-}
-
-static int mtk_qspi_probe(struct udevice *bus)
-{
- struct mtk_qspi_platdata *plat = dev_get_platdata(bus);
- struct mtk_qspi_priv *priv = dev_get_priv(bus);
-
- priv->regs = (struct mtk_qspi_regs *)plat->reg_base;
- priv->mem_base = (unsigned long *)plat->mem_base;
-
- writel(MTK_QSPI_COMMAND_ENABLE, &priv->regs->wrprot);
-
- return 0;
-}
-
-static const struct dm_spi_ops mtk_qspi_ops = {
- .claim_bus = mtk_qspi_claim_bus,
- .release_bus = mtk_qspi_release_bus,
- .xfer = mtk_qspi_xfer,
- .set_speed = mtk_qspi_set_speed,
- .set_mode = mtk_qspi_set_mode,
-};
-
-static const struct udevice_id mtk_qspi_ids[] = {
- { .compatible = "mediatek,mt7629-qspi" },
- { }
-};
-
-U_BOOT_DRIVER(mtk_qspi) = {
- .name = "mtk_qspi",
- .id = UCLASS_SPI,
- .of_match = mtk_qspi_ids,
- .ops = &mtk_qspi_ops,
- .ofdata_to_platdata = mtk_qspi_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct mtk_qspi_platdata),
- .priv_auto_alloc_size = sizeof(struct mtk_qspi_priv),
- .probe = mtk_qspi_probe,
-};
diff --git a/drivers/spi/mtk_snfi_spi.c b/drivers/spi/mtk_snfi_spi.c
new file mode 100644
index 0000000..2a89476
--- /dev/null
+++ b/drivers/spi/mtk_snfi_spi.c
@@ -0,0 +1,318 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <errno.h>
+#include <spi.h>
+#include <spi-mem.h>
+#include <stdbool.h>
+#include <watchdog.h>
+#include <dm/pinctrl.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+
+#define SNFI_MAC_CTL 0x500
+#define MAC_XIO_SEL BIT(4)
+#define SF_MAC_EN BIT(3)
+#define SF_TRIG BIT(2)
+#define WIP_READY BIT(1)
+#define WIP BIT(0)
+
+#define SNFI_MAC_OUTL 0x504
+#define SNFI_MAC_INL 0x508
+
+#define SNFI_MISC_CTL 0x538
+#define SW_RST BIT(28)
+#define FIFO_RD_LTC_SHIFT 25
+#define FIFO_RD_LTC GENMASK(26, 25)
+#define LATCH_LAT_SHIFT 8
+#define LATCH_LAT GENMASK(9, 8)
+#define CS_DESELECT_CYC_SHIFT 0
+#define CS_DESELECT_CYC GENMASK(4, 0)
+
+#define SNF_STA_CTL1 0x550
+#define SPI_STATE GENMASK(3, 0)
+
+#define SNFI_GPRAM_OFFSET 0x800
+#define SNFI_GPRAM_SIZE 0x80
+
+#define SNFI_POLL_INTERVAL 500000
+#define SNFI_RST_POLL_INTERVAL 1000000
+
+struct mtk_snfi_priv {
+ void __iomem *base;
+
+ struct clk nfi_clk;
+ struct clk pad_clk;
+};
+
+static int mtk_snfi_adjust_op_size(struct spi_slave *slave,
+ struct spi_mem_op *op)
+{
+ u32 nbytes;
+
+ /*
+ * When there is input data, it will be appended after the output
+ * data in the GPRAM. So the total size of either pure output data
+ * or the output+input data must not exceed the GPRAM size.
+ */
+
+ nbytes = sizeof(op->cmd.opcode) + op->addr.nbytes +
+ op->dummy.nbytes;
+
+ if (nbytes + op->data.nbytes <= SNFI_GPRAM_SIZE)
+ return 0;
+
+ if (nbytes >= SNFI_GPRAM_SIZE)
+ return -ENOTSUPP;
+
+ op->data.nbytes = SNFI_GPRAM_SIZE - nbytes;
+
+ return 0;
+}
+
+static bool mtk_snfi_supports_op(struct spi_slave *slave,
+ const struct spi_mem_op *op)
+{
+ if (op->cmd.buswidth > 1 || op->addr.buswidth > 1 ||
+ op->dummy.buswidth > 1 || op->data.buswidth > 1)
+ return false;
+
+ return true;
+}
+
+static int mtk_snfi_mac_trigger(struct mtk_snfi_priv *priv,
+ struct udevice *bus, u32 outlen, u32 inlen)
+{
+ int ret;
+ u32 val;
+
+#ifdef CONFIG_PINCTRL
+ pinctrl_select_state(bus, "snfi");
+#endif
+
+ writel(SF_MAC_EN, priv->base + SNFI_MAC_CTL);
+ writel(outlen, priv->base + SNFI_MAC_OUTL);
+ writel(inlen, priv->base + SNFI_MAC_INL);
+
+ writel(SF_MAC_EN | SF_TRIG, priv->base + SNFI_MAC_CTL);
+
+ ret = readl_poll_timeout(priv->base + SNFI_MAC_CTL, val,
+ val & WIP_READY, SNFI_POLL_INTERVAL);
+ if (ret) {
+ printf("%s: timed out waiting for WIP_READY\n", __func__);
+ goto cleanup;
+ }
+
+ ret = readl_poll_timeout(priv->base + SNFI_MAC_CTL, val,
+ !(val & WIP), SNFI_POLL_INTERVAL);
+ if (ret)
+ printf("%s: timed out waiting for WIP cleared\n", __func__);
+
+ writel(0, priv->base + SNFI_MAC_CTL);
+
+cleanup:
+#ifdef CONFIG_PINCTRL
+ pinctrl_select_state(bus, "default");
+#endif
+
+ return ret;
+}
+
+static int mtk_snfi_mac_reset(struct mtk_snfi_priv *priv)
+{
+ int ret;
+ u32 val;
+
+ setbits_32(priv->base + SNFI_MISC_CTL, SW_RST);
+
+ ret = readl_poll_timeout(priv->base + SNF_STA_CTL1, val,
+ !(val & SPI_STATE), SNFI_POLL_INTERVAL);
+ if (ret)
+ printf("%s: failed to reset snfi mac\n", __func__);
+
+ writel((2 << FIFO_RD_LTC_SHIFT) |
+ (10 << CS_DESELECT_CYC_SHIFT),
+ priv->base + SNFI_MISC_CTL);
+
+ return ret;
+}
+
+static void mtk_snfi_copy_to_gpram(struct mtk_snfi_priv *priv,
+ const void *data, size_t len)
+{
+ void __iomem *gpram = priv->base + SNFI_GPRAM_OFFSET;
+ size_t i, n = (len + sizeof(u32) - 1) / sizeof(u32);
+ const u32 *buff = data;
+
+ /*
+ * The output data will always be copied to the beginning of
+ * the GPRAM. Uses word write for better performace.
+ *
+ * Trailing bytes in the last word are not cared.
+ */
+
+ for (i = 0; i < n; i++)
+ writel(buff[i], gpram + i * sizeof(u32));
+}
+
+static void mtk_snfi_copy_from_gpram(struct mtk_snfi_priv *priv, u8 *cache,
+ void *data, size_t pos, size_t len)
+{
+ void __iomem *gpram = priv->base + SNFI_GPRAM_OFFSET;
+ u32 *buff = (u32 *)cache;
+ size_t i, off, end;
+
+ /* Start position in the buffer */
+ off = pos & (sizeof(u32) - 1);
+
+ /* End position for copy */
+ end = (len + pos + sizeof(u32) - 1) & (~(sizeof(u32) - 1));
+
+ /* Start position for copy */
+ pos &= ~(sizeof(u32) - 1);
+
+ /*
+ * Read aligned data from GPRAM to buffer first.
+ * Uses word read for better performace.
+ */
+ i = 0;
+ while (pos < end) {
+ buff[i++] = readl(gpram + pos);
+ pos += sizeof(u32);
+ }
+
+ /* Copy rx data */
+ memcpy(data, cache + off, len);
+}
+
+static int mtk_snfi_exec_op(struct spi_slave *slave,
+ const struct spi_mem_op *op)
+{
+ struct udevice *bus = dev_get_parent(slave->dev);
+ struct mtk_snfi_priv *priv = dev_get_priv(bus);
+ u8 gpram_cache[SNFI_GPRAM_SIZE];
+ u32 i, len = 0, inlen = 0;
+ int addr_sh;
+ int ret;
+
+ WATCHDOG_RESET();
+
+ ret = mtk_snfi_mac_reset(priv);
+ if (ret)
+ return ret;
+
+ /* Put opcode */
+ gpram_cache[len++] = op->cmd.opcode;
+
+ /* Put address */
+ addr_sh = (op->addr.nbytes - 1) * 8;
+ while (addr_sh >= 0) {
+ gpram_cache[len++] = (op->addr.val >> addr_sh) & 0xff;
+ addr_sh -= 8;
+ }
+
+ /* Put dummy bytes */
+ for (i = 0; i < op->dummy.nbytes; i++)
+ gpram_cache[len++] = 0;
+
+ /* Put output data */
+ if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT) {
+ memcpy(gpram_cache + len, op->data.buf.out, op->data.nbytes);
+ len += op->data.nbytes;
+ }
+
+ /* Copy final output data to GPRAM */
+ mtk_snfi_copy_to_gpram(priv, gpram_cache, len);
+
+ /* Start one SPI transaction */
+ if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
+ inlen = op->data.nbytes;
+
+ ret = mtk_snfi_mac_trigger(priv, bus, len, inlen);
+ if (ret)
+ return ret;
+
+ /* Copy input data from GPRAM */
+ if (inlen)
+ mtk_snfi_copy_from_gpram(priv, gpram_cache, op->data.buf.in,
+ len, inlen);
+
+ return 0;
+}
+
+static int mtk_snfi_spi_probe(struct udevice *bus)
+{
+ struct mtk_snfi_priv *priv = dev_get_priv(bus);
+ int ret;
+
+ priv->base = (void __iomem *)devfdt_get_addr(bus);
+ if (!priv->base)
+ return -EINVAL;
+
+ ret = clk_get_by_name(bus, "nfi_clk", &priv->nfi_clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_get_by_name(bus, "pad_clk", &priv->pad_clk);
+ if (ret < 0)
+ return ret;
+
+ clk_enable(&priv->nfi_clk);
+ clk_enable(&priv->pad_clk);
+
+ return 0;
+}
+
+static int mtk_snfi_set_speed(struct udevice *bus, uint speed)
+{
+ /*
+ * The SNFI does not have a bus clock divider.
+ * The bus clock is set in dts (pad_clk, UNIVPLL2_D8 = 50MHz).
+ */
+
+ return 0;
+}
+
+static int mtk_snfi_set_mode(struct udevice *bus, uint mode)
+{
+ /* The SNFI supports only mode 0 */
+
+ if (mode)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct spi_controller_mem_ops mtk_snfi_mem_ops = {
+ .adjust_op_size = mtk_snfi_adjust_op_size,
+ .supports_op = mtk_snfi_supports_op,
+ .exec_op = mtk_snfi_exec_op,
+};
+
+static const struct dm_spi_ops mtk_snfi_spi_ops = {
+ .mem_ops = &mtk_snfi_mem_ops,
+ .set_speed = mtk_snfi_set_speed,
+ .set_mode = mtk_snfi_set_mode,
+};
+
+static const struct udevice_id mtk_snfi_spi_ids[] = {
+ { .compatible = "mediatek,mtk-snfi-spi" },
+ { }
+};
+
+U_BOOT_DRIVER(mtk_snfi_spi) = {
+ .name = "mtk_snfi_spi",
+ .id = UCLASS_SPI,
+ .of_match = mtk_snfi_spi_ids,
+ .ops = &mtk_snfi_spi_ops,
+ .priv_auto_alloc_size = sizeof(struct mtk_snfi_priv),
+ .probe = mtk_snfi_spi_probe,
+};
diff --git a/drivers/spi/mvebu_a3700_spi.c b/drivers/spi/mvebu_a3700_spi.c
index feeafdc..99ad505 100644
--- a/drivers/spi/mvebu_a3700_spi.c
+++ b/drivers/spi/mvebu_a3700_spi.c
@@ -181,10 +181,9 @@
data = readl(®->cfg);
prescale = DIV_ROUND_UP(clk_get_rate(&plat->clk), hz);
- if (prescale > 0x1f)
- prescale = 0x1f;
- else if (prescale > 0xf)
+ if (prescale > 0xf)
prescale = 0x10 + (prescale + 1) / 2;
+ prescale = min(prescale, 0x1fu);
data &= ~MVEBU_SPI_A3700_CLK_PRESCALE_MASK;
data |= prescale & MVEBU_SPI_A3700_CLK_PRESCALE_MASK;
diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
index 5065e40..3a9756f 100644
--- a/drivers/spi/mxs_spi.c
+++ b/drivers/spi/mxs_spi.c
@@ -2,6 +2,9 @@
/*
* Freescale i.MX28 SPI driver
*
+ * Copyright (C) 2019 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
@@ -27,89 +30,6 @@
#define MXSSSP_SMALL_TRANSFER 512
-struct mxs_spi_slave {
- struct spi_slave slave;
- uint32_t max_khz;
- uint32_t mode;
- struct mxs_ssp_regs *regs;
-};
-
-static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave)
-{
- return container_of(slave, struct mxs_spi_slave, slave);
-}
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- /* MXS SPI: 4 ports and 3 chip selects maximum */
- if (!mxs_ssp_bus_id_valid(bus) || cs > 2)
- return 0;
- else
- return 1;
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- struct mxs_spi_slave *mxs_slave;
-
- if (!spi_cs_is_valid(bus, cs)) {
- printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs);
- return NULL;
- }
-
- mxs_slave = spi_alloc_slave(struct mxs_spi_slave, bus, cs);
- if (!mxs_slave)
- return NULL;
-
- if (mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + bus))
- goto err_init;
-
- mxs_slave->max_khz = max_hz / 1000;
- mxs_slave->mode = mode;
- mxs_slave->regs = mxs_ssp_regs_by_bus(bus);
-
- return &mxs_slave->slave;
-
-err_init:
- free(mxs_slave);
- return NULL;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
- struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
- free(mxs_slave);
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
- struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
- struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
- uint32_t reg = 0;
-
- mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
-
- writel((slave->cs << MXS_SSP_CHIPSELECT_SHIFT) |
- SSP_CTRL0_BUS_WIDTH_ONE_BIT,
- &ssp_regs->hw_ssp_ctrl0);
-
- reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
- reg |= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
- reg |= (mxs_slave->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0;
- writel(reg, &ssp_regs->hw_ssp_ctrl1);
-
- writel(0, &ssp_regs->hw_ssp_cmd0);
-
- mxs_set_ssp_busclock(slave->bus, mxs_slave->max_khz);
-
- return 0;
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
-}
-
static void mxs_spi_start_xfer(struct mxs_ssp_regs *ssp_regs)
{
writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_set);
@@ -122,10 +42,50 @@
writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_set);
}
+#if !CONFIG_IS_ENABLED(DM_SPI)
+struct mxs_spi_slave {
+ struct spi_slave slave;
+ uint32_t max_khz;
+ uint32_t mode;
+ struct mxs_ssp_regs *regs;
+};
+
+static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave)
+{
+ return container_of(slave, struct mxs_spi_slave, slave);
+}
+#else
+#include <dm.h>
+#include <errno.h>
+struct mxs_spi_platdata {
+ s32 frequency; /* Default clock frequency, -1 for none */
+ fdt_addr_t base; /* SPI IP block base address */
+ int num_cs; /* Number of CSes supported */
+ int dma_id; /* ID of the DMA channel */
+ int clk_id; /* ID of the SSP clock */
+};
+
+struct mxs_spi_priv {
+ struct mxs_ssp_regs *regs;
+ unsigned int dma_channel;
+ unsigned int max_freq;
+ unsigned int clk_id;
+ unsigned int mode;
+};
+#endif
+
+#if !CONFIG_IS_ENABLED(DM_SPI)
static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave,
char *data, int length, int write, unsigned long flags)
{
struct mxs_ssp_regs *ssp_regs = slave->regs;
+#else
+static int mxs_spi_xfer_pio(struct mxs_spi_priv *priv,
+ char *data, int length, int write,
+ unsigned long flags)
+{
+ struct mxs_ssp_regs *ssp_regs = priv->regs;
+#endif
if (flags & SPI_XFER_BEGIN)
mxs_spi_start_xfer(ssp_regs);
@@ -181,12 +141,19 @@
return 0;
}
+#if !CONFIG_IS_ENABLED(DM_SPI)
static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
char *data, int length, int write, unsigned long flags)
{
+ struct mxs_ssp_regs *ssp_regs = slave->regs;
+#else
+static int mxs_spi_xfer_dma(struct mxs_spi_priv *priv,
+ char *data, int length, int write,
+ unsigned long flags)
+{ struct mxs_ssp_regs *ssp_regs = priv->regs;
+#endif
const int xfer_max_sz = 0xff00;
const int desc_count = DIV_ROUND_UP(length, xfer_max_sz) + 1;
- struct mxs_ssp_regs *ssp_regs = slave->regs;
struct mxs_dma_desc *dp;
uint32_t ctrl0;
uint32_t cache_data_count;
@@ -225,7 +192,11 @@
/* Invalidate the area, so no writeback into the RAM races with DMA */
invalidate_dcache_range(dstart, dstart + cache_data_count);
+#if !CONFIG_IS_ENABLED(DM_SPI)
dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + slave->slave.bus;
+#else
+ dmach = priv->dma_channel;
+#endif
dp = desc;
while (length) {
@@ -302,11 +273,20 @@
return ret;
}
+#if !CONFIG_IS_ENABLED(DM_SPI)
int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
{
struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
+#else
+int mxs_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct udevice *bus = dev_get_parent(dev);
+ struct mxs_spi_priv *priv = dev_get_priv(bus);
+ struct mxs_ssp_regs *ssp_regs = priv->regs;
+#endif
int len = bitlen / 8;
char dummy;
int write = 0;
@@ -350,9 +330,263 @@
if (!dma || (len < MXSSSP_SMALL_TRANSFER)) {
writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
+#if !CONFIG_IS_ENABLED(DM_SPI)
return mxs_spi_xfer_pio(mxs_slave, data, len, write, flags);
+#else
+ return mxs_spi_xfer_pio(priv, data, len, write, flags);
+#endif
} else {
writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
+#if !CONFIG_IS_ENABLED(DM_SPI)
return mxs_spi_xfer_dma(mxs_slave, data, len, write, flags);
+#else
+ return mxs_spi_xfer_dma(priv, data, len, write, flags);
+#endif
}
}
+
+#if !CONFIG_IS_ENABLED(DM_SPI)
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ /* MXS SPI: 4 ports and 3 chip selects maximum */
+ if (!mxs_ssp_bus_id_valid(bus) || cs > 2)
+ return 0;
+ else
+ return 1;
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct mxs_spi_slave *mxs_slave;
+
+ if (!spi_cs_is_valid(bus, cs)) {
+ printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs);
+ return NULL;
+ }
+
+ mxs_slave = spi_alloc_slave(struct mxs_spi_slave, bus, cs);
+ if (!mxs_slave)
+ return NULL;
+
+ if (mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + bus))
+ goto err_init;
+
+ mxs_slave->max_khz = max_hz / 1000;
+ mxs_slave->mode = mode;
+ mxs_slave->regs = mxs_ssp_regs_by_bus(bus);
+
+ return &mxs_slave->slave;
+
+err_init:
+ free(mxs_slave);
+ return NULL;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
+
+ free(mxs_slave);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
+ struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
+ u32 reg = 0;
+
+ mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
+
+ writel((slave->cs << MXS_SSP_CHIPSELECT_SHIFT) |
+ SSP_CTRL0_BUS_WIDTH_ONE_BIT,
+ &ssp_regs->hw_ssp_ctrl0);
+
+ reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
+ reg |= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
+ reg |= (mxs_slave->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0;
+ writel(reg, &ssp_regs->hw_ssp_ctrl1);
+
+ writel(0, &ssp_regs->hw_ssp_cmd0);
+
+ mxs_set_ssp_busclock(slave->bus, mxs_slave->max_khz);
+
+ return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+}
+
+#else /* CONFIG_DM_SPI */
+/* Base numbers of i.MX2[38] clk for ssp0 IP block */
+#define MXS_SSP_IMX23_CLKID_SSP0 33
+#define MXS_SSP_IMX28_CLKID_SSP0 46
+
+static int mxs_spi_probe(struct udevice *bus)
+{
+ struct mxs_spi_platdata *plat = dev_get_platdata(bus);
+ struct mxs_spi_priv *priv = dev_get_priv(bus);
+ int ret;
+
+ debug("%s: probe\n", __func__);
+ priv->regs = (struct mxs_ssp_regs *)plat->base;
+ priv->max_freq = plat->frequency;
+
+ priv->dma_channel = plat->dma_id;
+ priv->clk_id = plat->clk_id;
+
+ ret = mxs_dma_init_channel(priv->dma_channel);
+ if (ret) {
+ printf("%s: DMA init channel error %d\n", __func__, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int mxs_spi_claim_bus(struct udevice *dev)
+{
+ struct udevice *bus = dev_get_parent(dev);
+ struct mxs_spi_priv *priv = dev_get_priv(bus);
+ struct mxs_ssp_regs *ssp_regs = priv->regs;
+ int cs = spi_chip_select(dev);
+
+ /*
+ * i.MX28 supports up to 3 CS (SSn0, SSn1, SSn2)
+ * To set them it uses following tuple (WAIT_FOR_IRQ,WAIT_FOR_CMD),
+ * where:
+ *
+ * WAIT_FOR_IRQ is bit 21 of HW_SSP_CTRL0
+ * WAIT_FOR_CMD is bit 20 (#defined as MXS_SSP_CHIPSELECT_SHIFT here) of
+ * HW_SSP_CTRL0
+ * SSn0 b00
+ * SSn1 b01
+ * SSn2 b10 (which require setting WAIT_FOR_IRQ)
+ *
+ * However, for now i.MX28 SPI driver will support up till 2 CSes
+ * (SSn0, and SSn1).
+ */
+
+ /* Ungate SSP clock and set active CS */
+ clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
+ BIT(MXS_SSP_CHIPSELECT_SHIFT) |
+ SSP_CTRL0_CLKGATE, (cs << MXS_SSP_CHIPSELECT_SHIFT));
+
+ return 0;
+}
+
+static int mxs_spi_release_bus(struct udevice *dev)
+{
+ struct udevice *bus = dev_get_parent(dev);
+ struct mxs_spi_priv *priv = dev_get_priv(bus);
+ struct mxs_ssp_regs *ssp_regs = priv->regs;
+
+ /* Gate SSP clock */
+ setbits_le32(&ssp_regs->hw_ssp_ctrl0, SSP_CTRL0_CLKGATE);
+
+ return 0;
+}
+
+static int mxs_spi_set_speed(struct udevice *bus, uint speed)
+{
+ struct mxs_spi_priv *priv = dev_get_priv(bus);
+#ifdef CONFIG_MX28
+ int clkid = priv->clk_id - MXS_SSP_IMX28_CLKID_SSP0;
+#else /* CONFIG_MX23 */
+ int clkid = priv->clk_id - MXS_SSP_IMX23_CLKID_SSP0;
+#endif
+ if (speed > priv->max_freq)
+ speed = priv->max_freq;
+
+ debug("%s speed: %u [Hz] clkid: %d\n", __func__, speed, clkid);
+ mxs_set_ssp_busclock(clkid, speed / 1000);
+
+ return 0;
+}
+
+static int mxs_spi_set_mode(struct udevice *bus, uint mode)
+{
+ struct mxs_spi_priv *priv = dev_get_priv(bus);
+ struct mxs_ssp_regs *ssp_regs = priv->regs;
+ u32 reg;
+
+ priv->mode = mode;
+ debug("%s: mode 0x%x\n", __func__, mode);
+
+ reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
+ reg |= (priv->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
+ reg |= (priv->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0;
+ writel(reg, &ssp_regs->hw_ssp_ctrl1);
+
+ /* Single bit SPI support */
+ writel(SSP_CTRL0_BUS_WIDTH_ONE_BIT, &ssp_regs->hw_ssp_ctrl0);
+
+ return 0;
+}
+
+static const struct dm_spi_ops mxs_spi_ops = {
+ .claim_bus = mxs_spi_claim_bus,
+ .release_bus = mxs_spi_release_bus,
+ .xfer = mxs_spi_xfer,
+ .set_speed = mxs_spi_set_speed,
+ .set_mode = mxs_spi_set_mode,
+ /*
+ * cs_info is not needed, since we require all chip selects to be
+ * in the device tree explicitly
+ */
+};
+
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+static int mxs_ofdata_to_platdata(struct udevice *bus)
+{
+ struct mxs_spi_platdata *plat = bus->platdata;
+ u32 prop[2];
+ int ret;
+
+ plat->base = dev_read_addr(bus);
+ plat->frequency =
+ dev_read_u32_default(bus, "spi-max-frequency", 40000000);
+ plat->num_cs = dev_read_u32_default(bus, "num-cs", 2);
+
+ ret = dev_read_u32_array(bus, "dmas", prop, ARRAY_SIZE(prop));
+ if (ret) {
+ printf("%s: Reading 'dmas' property failed!\n", __func__);
+ return ret;
+ }
+ plat->dma_id = prop[1];
+
+ ret = dev_read_u32_array(bus, "clocks", prop, ARRAY_SIZE(prop));
+ if (ret) {
+ printf("%s: Reading 'clocks' property failed!\n", __func__);
+ return ret;
+ }
+ plat->clk_id = prop[1];
+
+ debug("%s: base=0x%x, max-frequency=%d num-cs=%d dma_id=%d clk_id=%d\n",
+ __func__, (uint)plat->base, plat->frequency, plat->num_cs,
+ plat->dma_id, plat->clk_id);
+
+ return 0;
+}
+#endif
+
+static const struct udevice_id mxs_spi_ids[] = {
+ { .compatible = "fsl,imx23-spi" },
+ { .compatible = "fsl,imx28-spi" },
+ { }
+};
+
+U_BOOT_DRIVER(mxs_spi) = {
+ .name = "mxs_spi",
+ .id = UCLASS_SPI,
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+ .of_match = mxs_spi_ids,
+ .ofdata_to_platdata = mxs_ofdata_to_platdata,
+#endif
+ .priv_auto_alloc_size = sizeof(struct mxs_spi_platdata),
+ .ops = &mxs_spi_ops,
+ .priv_auto_alloc_size = sizeof(struct mxs_spi_priv),
+ .probe = mxs_spi_probe,
+};
+#endif
diff --git a/drivers/spi/soft_spi.c b/drivers/spi/soft_spi.c
index b06883f..b80f810 100644
--- a/drivers/spi/soft_spi.c
+++ b/drivers/spi/soft_spi.c
@@ -215,8 +215,8 @@
int cs_flags, clk_flags;
int ret;
- cs_flags = (slave->mode & SPI_CS_HIGH) ? 0 : GPIOD_ACTIVE_LOW;
- clk_flags = (slave->mode & SPI_CPOL) ? GPIOD_ACTIVE_LOW : 0;
+ cs_flags = (slave && slave->mode & SPI_CS_HIGH) ? 0 : GPIOD_ACTIVE_LOW;
+ clk_flags = (slave && slave->mode & SPI_CPOL) ? GPIOD_ACTIVE_LOW : 0;
if (gpio_request_by_name(dev, "cs-gpios", 0, &plat->cs,
GPIOD_IS_OUT | cs_flags) ||
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index b86eee7..7788ab9 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -201,7 +201,6 @@
unsigned int pos = 0;
const u8 *tx_buf = NULL;
u8 *rx_buf = NULL;
- u8 *op_buf;
int op_len;
u32 flag;
int ret;
@@ -338,7 +337,17 @@
}
op_len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes;
- op_buf = calloc(1, op_len);
+
+ /*
+ * Avoid using malloc() here so that we can use this code in SPL where
+ * simple malloc may be used. That implementation does not allow free()
+ * so repeated calls to this code can exhaust the space.
+ *
+ * The value of op_len is small, since it does not include the actual
+ * data being sent, only the op-code and address. In fact, it should be
+ * possible to just use a small fixed value here instead of op_len.
+ */
+ u8 op_buf[op_len];
op_buf[pos++] = op->cmd.opcode;
@@ -382,8 +391,6 @@
debug("%02x ", tx_buf ? tx_buf[i] : rx_buf[i]);
debug("[ret %d]\n", ret);
- free(op_buf);
-
if (ret < 0)
return ret;
#endif /* __UBOOT__ */
@@ -423,12 +430,14 @@
if (slave->max_write_size && len > slave->max_write_size)
return -EINVAL;
- if (op->data.dir == SPI_MEM_DATA_IN && slave->max_read_size)
- op->data.nbytes = min(op->data.nbytes,
+ if (op->data.dir == SPI_MEM_DATA_IN) {
+ if (slave->max_read_size)
+ op->data.nbytes = min(op->data.nbytes,
slave->max_read_size);
- else if (slave->max_write_size)
+ } else if (slave->max_write_size) {
op->data.nbytes = min(op->data.nbytes,
slave->max_write_size - len);
+ }
if (!op->data.nbytes)
return -EINVAL;
diff --git a/drivers/spi/spi-sifive.c b/drivers/spi/spi-sifive.c
new file mode 100644
index 0000000..969bd4b
--- /dev/null
+++ b/drivers/spi/spi-sifive.c
@@ -0,0 +1,370 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 SiFive, Inc.
+ * Copyright 2019 Bhargav Shah <bhargavshah1988@gmail.com>
+ *
+ * SiFive SPI controller driver (master mode only)
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <malloc.h>
+#include <spi.h>
+#include <asm/io.h>
+#include <linux/log2.h>
+#include <clk.h>
+
+#define SIFIVE_SPI_MAX_CS 32
+
+#define SIFIVE_SPI_DEFAULT_DEPTH 8
+#define SIFIVE_SPI_DEFAULT_BITS 8
+
+/* register offsets */
+#define SIFIVE_SPI_REG_SCKDIV 0x00 /* Serial clock divisor */
+#define SIFIVE_SPI_REG_SCKMODE 0x04 /* Serial clock mode */
+#define SIFIVE_SPI_REG_CSID 0x10 /* Chip select ID */
+#define SIFIVE_SPI_REG_CSDEF 0x14 /* Chip select default */
+#define SIFIVE_SPI_REG_CSMODE 0x18 /* Chip select mode */
+#define SIFIVE_SPI_REG_DELAY0 0x28 /* Delay control 0 */
+#define SIFIVE_SPI_REG_DELAY1 0x2c /* Delay control 1 */
+#define SIFIVE_SPI_REG_FMT 0x40 /* Frame format */
+#define SIFIVE_SPI_REG_TXDATA 0x48 /* Tx FIFO data */
+#define SIFIVE_SPI_REG_RXDATA 0x4c /* Rx FIFO data */
+#define SIFIVE_SPI_REG_TXMARK 0x50 /* Tx FIFO watermark */
+#define SIFIVE_SPI_REG_RXMARK 0x54 /* Rx FIFO watermark */
+#define SIFIVE_SPI_REG_FCTRL 0x60 /* SPI flash interface control */
+#define SIFIVE_SPI_REG_FFMT 0x64 /* SPI flash instruction format */
+#define SIFIVE_SPI_REG_IE 0x70 /* Interrupt Enable Register */
+#define SIFIVE_SPI_REG_IP 0x74 /* Interrupt Pendings Register */
+
+/* sckdiv bits */
+#define SIFIVE_SPI_SCKDIV_DIV_MASK 0xfffU
+
+/* sckmode bits */
+#define SIFIVE_SPI_SCKMODE_PHA BIT(0)
+#define SIFIVE_SPI_SCKMODE_POL BIT(1)
+#define SIFIVE_SPI_SCKMODE_MODE_MASK (SIFIVE_SPI_SCKMODE_PHA | \
+ SIFIVE_SPI_SCKMODE_POL)
+
+/* csmode bits */
+#define SIFIVE_SPI_CSMODE_MODE_AUTO 0U
+#define SIFIVE_SPI_CSMODE_MODE_HOLD 2U
+#define SIFIVE_SPI_CSMODE_MODE_OFF 3U
+
+/* delay0 bits */
+#define SIFIVE_SPI_DELAY0_CSSCK(x) ((u32)(x))
+#define SIFIVE_SPI_DELAY0_CSSCK_MASK 0xffU
+#define SIFIVE_SPI_DELAY0_SCKCS(x) ((u32)(x) << 16)
+#define SIFIVE_SPI_DELAY0_SCKCS_MASK (0xffU << 16)
+
+/* delay1 bits */
+#define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x))
+#define SIFIVE_SPI_DELAY1_INTERCS_MASK 0xffU
+#define SIFIVE_SPI_DELAY1_INTERXFR(x) ((u32)(x) << 16)
+#define SIFIVE_SPI_DELAY1_INTERXFR_MASK (0xffU << 16)
+
+/* fmt bits */
+#define SIFIVE_SPI_FMT_PROTO_SINGLE 0U
+#define SIFIVE_SPI_FMT_PROTO_DUAL 1U
+#define SIFIVE_SPI_FMT_PROTO_QUAD 2U
+#define SIFIVE_SPI_FMT_PROTO_MASK 3U
+#define SIFIVE_SPI_FMT_ENDIAN BIT(2)
+#define SIFIVE_SPI_FMT_DIR BIT(3)
+#define SIFIVE_SPI_FMT_LEN(x) ((u32)(x) << 16)
+#define SIFIVE_SPI_FMT_LEN_MASK (0xfU << 16)
+
+/* txdata bits */
+#define SIFIVE_SPI_TXDATA_DATA_MASK 0xffU
+#define SIFIVE_SPI_TXDATA_FULL BIT(31)
+
+/* rxdata bits */
+#define SIFIVE_SPI_RXDATA_DATA_MASK 0xffU
+#define SIFIVE_SPI_RXDATA_EMPTY BIT(31)
+
+/* ie and ip bits */
+#define SIFIVE_SPI_IP_TXWM BIT(0)
+#define SIFIVE_SPI_IP_RXWM BIT(1)
+
+struct sifive_spi {
+ void *regs; /* base address of the registers */
+ u32 fifo_depth;
+ u32 bits_per_word;
+ u32 cs_inactive; /* Level of the CS pins when inactive*/
+ u32 freq;
+ u32 num_cs;
+};
+
+static void sifive_spi_prep_device(struct sifive_spi *spi,
+ struct dm_spi_slave_platdata *slave)
+{
+ /* Update the chip select polarity */
+ if (slave->mode & SPI_CS_HIGH)
+ spi->cs_inactive &= ~BIT(slave->cs);
+ else
+ spi->cs_inactive |= BIT(slave->cs);
+ writel(spi->cs_inactive, spi->regs + SIFIVE_SPI_REG_CSDEF);
+
+ /* Select the correct device */
+ writel(slave->cs, spi->regs + SIFIVE_SPI_REG_CSID);
+}
+
+static int sifive_spi_set_cs(struct sifive_spi *spi,
+ struct dm_spi_slave_platdata *slave)
+{
+ u32 cs_mode = SIFIVE_SPI_CSMODE_MODE_HOLD;
+
+ if (slave->mode & SPI_CS_HIGH)
+ cs_mode = SIFIVE_SPI_CSMODE_MODE_AUTO;
+
+ writel(cs_mode, spi->regs + SIFIVE_SPI_REG_CSMODE);
+
+ return 0;
+}
+
+static void sifive_spi_clear_cs(struct sifive_spi *spi)
+{
+ writel(SIFIVE_SPI_CSMODE_MODE_AUTO, spi->regs + SIFIVE_SPI_REG_CSMODE);
+}
+
+static void sifive_spi_prep_transfer(struct sifive_spi *spi,
+ bool is_rx_xfer,
+ struct dm_spi_slave_platdata *slave)
+{
+ u32 cr;
+
+ /* Modify the SPI protocol mode */
+ cr = readl(spi->regs + SIFIVE_SPI_REG_FMT);
+
+ /* Bits per word ? */
+ cr &= ~SIFIVE_SPI_FMT_LEN_MASK;
+ cr |= SIFIVE_SPI_FMT_LEN(spi->bits_per_word);
+
+ /* LSB first? */
+ cr &= ~SIFIVE_SPI_FMT_ENDIAN;
+ if (slave->mode & SPI_LSB_FIRST)
+ cr |= SIFIVE_SPI_FMT_ENDIAN;
+
+ /* Number of wires ? */
+ cr &= ~SIFIVE_SPI_FMT_PROTO_MASK;
+ if ((slave->mode & SPI_TX_QUAD) || (slave->mode & SPI_RX_QUAD))
+ cr |= SIFIVE_SPI_FMT_PROTO_QUAD;
+ else if ((slave->mode & SPI_TX_DUAL) || (slave->mode & SPI_RX_DUAL))
+ cr |= SIFIVE_SPI_FMT_PROTO_DUAL;
+ else
+ cr |= SIFIVE_SPI_FMT_PROTO_SINGLE;
+
+ /* SPI direction in/out ? */
+ cr &= ~SIFIVE_SPI_FMT_DIR;
+ if (!is_rx_xfer)
+ cr |= SIFIVE_SPI_FMT_DIR;
+
+ writel(cr, spi->regs + SIFIVE_SPI_REG_FMT);
+}
+
+static void sifive_spi_rx(struct sifive_spi *spi, u8 *rx_ptr)
+{
+ u32 data;
+
+ do {
+ data = readl(spi->regs + SIFIVE_SPI_REG_RXDATA);
+ } while (data & SIFIVE_SPI_RXDATA_EMPTY);
+
+ if (rx_ptr)
+ *rx_ptr = data & SIFIVE_SPI_RXDATA_DATA_MASK;
+}
+
+static void sifive_spi_tx(struct sifive_spi *spi, const u8 *tx_ptr)
+{
+ u32 data;
+ u8 tx_data = (tx_ptr) ? *tx_ptr & SIFIVE_SPI_TXDATA_DATA_MASK :
+ SIFIVE_SPI_TXDATA_DATA_MASK;
+
+ do {
+ data = readl(spi->regs + SIFIVE_SPI_REG_TXDATA);
+ } while (data & SIFIVE_SPI_TXDATA_FULL);
+
+ writel(tx_data, spi->regs + SIFIVE_SPI_REG_TXDATA);
+}
+
+static int sifive_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct udevice *bus = dev->parent;
+ struct sifive_spi *spi = dev_get_priv(bus);
+ struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
+ const unsigned char *tx_ptr = dout;
+ u8 *rx_ptr = din;
+ u32 remaining_len;
+ int ret;
+
+ if (flags & SPI_XFER_BEGIN) {
+ sifive_spi_prep_device(spi, slave);
+
+ ret = sifive_spi_set_cs(spi, slave);
+ if (ret)
+ return ret;
+ }
+
+ sifive_spi_prep_transfer(spi, true, slave);
+
+ remaining_len = bitlen / 8;
+
+ while (remaining_len) {
+ int n_words, tx_words, rx_words;
+
+ n_words = min(remaining_len, spi->fifo_depth);
+
+ /* Enqueue n_words for transmission */
+ if (tx_ptr) {
+ for (tx_words = 0; tx_words < n_words; ++tx_words) {
+ sifive_spi_tx(spi, tx_ptr);
+ sifive_spi_rx(spi, NULL);
+ tx_ptr++;
+ }
+ }
+
+ /* Read out all the data from the RX FIFO */
+ if (rx_ptr) {
+ for (rx_words = 0; rx_words < n_words; ++rx_words) {
+ sifive_spi_tx(spi, NULL);
+ sifive_spi_rx(spi, rx_ptr);
+ rx_ptr++;
+ }
+ }
+
+ remaining_len -= n_words;
+ }
+
+ if (flags & SPI_XFER_END)
+ sifive_spi_clear_cs(spi);
+
+ return 0;
+}
+
+static int sifive_spi_set_speed(struct udevice *bus, uint speed)
+{
+ struct sifive_spi *spi = dev_get_priv(bus);
+ u32 scale;
+
+ if (speed > spi->freq)
+ speed = spi->freq;
+
+ /* Cofigure max speed */
+ scale = (DIV_ROUND_UP(spi->freq >> 1, speed) - 1)
+ & SIFIVE_SPI_SCKDIV_DIV_MASK;
+ writel(scale, spi->regs + SIFIVE_SPI_REG_SCKDIV);
+
+ return 0;
+}
+
+static int sifive_spi_set_mode(struct udevice *bus, uint mode)
+{
+ struct sifive_spi *spi = dev_get_priv(bus);
+ u32 cr;
+
+ /* Switch clock mode bits */
+ cr = readl(spi->regs + SIFIVE_SPI_REG_SCKMODE) &
+ ~SIFIVE_SPI_SCKMODE_MODE_MASK;
+ if (mode & SPI_CPHA)
+ cr |= SIFIVE_SPI_SCKMODE_PHA;
+ if (mode & SPI_CPOL)
+ cr |= SIFIVE_SPI_SCKMODE_POL;
+
+ writel(cr, spi->regs + SIFIVE_SPI_REG_SCKMODE);
+
+ return 0;
+}
+
+static int sifive_spi_cs_info(struct udevice *bus, uint cs,
+ struct spi_cs_info *info)
+{
+ struct sifive_spi *spi = dev_get_priv(bus);
+
+ if (cs >= spi->num_cs)
+ return -EINVAL;
+
+ return 0;
+}
+
+static void sifive_spi_init_hw(struct sifive_spi *spi)
+{
+ u32 cs_bits;
+
+ /* probe the number of CS lines */
+ spi->cs_inactive = readl(spi->regs + SIFIVE_SPI_REG_CSDEF);
+ writel(0xffffffffU, spi->regs + SIFIVE_SPI_REG_CSDEF);
+ cs_bits = readl(spi->regs + SIFIVE_SPI_REG_CSDEF);
+ writel(spi->cs_inactive, spi->regs + SIFIVE_SPI_REG_CSDEF);
+ if (!cs_bits) {
+ printf("Could not auto probe CS lines\n");
+ return;
+ }
+
+ spi->num_cs = ilog2(cs_bits) + 1;
+ if (spi->num_cs > SIFIVE_SPI_MAX_CS) {
+ printf("Invalid number of spi slaves\n");
+ return;
+ }
+
+ /* Watermark interrupts are disabled by default */
+ writel(0, spi->regs + SIFIVE_SPI_REG_IE);
+
+ /* Set CS/SCK Delays and Inactive Time to defaults */
+ writel(SIFIVE_SPI_DELAY0_CSSCK(1) | SIFIVE_SPI_DELAY0_SCKCS(1),
+ spi->regs + SIFIVE_SPI_REG_DELAY0);
+ writel(SIFIVE_SPI_DELAY1_INTERCS(1) | SIFIVE_SPI_DELAY1_INTERXFR(0),
+ spi->regs + SIFIVE_SPI_REG_DELAY1);
+
+ /* Exit specialized memory-mapped SPI flash mode */
+ writel(0, spi->regs + SIFIVE_SPI_REG_FCTRL);
+}
+
+static int sifive_spi_probe(struct udevice *bus)
+{
+ struct sifive_spi *spi = dev_get_priv(bus);
+ struct clk clkdev;
+ int ret;
+
+ spi->regs = (void *)(ulong)dev_remap_addr(bus);
+ if (!spi->regs)
+ return -ENODEV;
+
+ spi->fifo_depth = dev_read_u32_default(bus,
+ "sifive,fifo-depth",
+ SIFIVE_SPI_DEFAULT_DEPTH);
+
+ spi->bits_per_word = dev_read_u32_default(bus,
+ "sifive,max-bits-per-word",
+ SIFIVE_SPI_DEFAULT_BITS);
+
+ ret = clk_get_by_index(bus, 0, &clkdev);
+ if (ret)
+ return ret;
+ spi->freq = clk_get_rate(&clkdev);
+
+ /* init the sifive spi hw */
+ sifive_spi_init_hw(spi);
+
+ return 0;
+}
+
+static const struct dm_spi_ops sifive_spi_ops = {
+ .xfer = sifive_spi_xfer,
+ .set_speed = sifive_spi_set_speed,
+ .set_mode = sifive_spi_set_mode,
+ .cs_info = sifive_spi_cs_info,
+};
+
+static const struct udevice_id sifive_spi_ids[] = {
+ { .compatible = "sifive,spi0" },
+ { }
+};
+
+U_BOOT_DRIVER(sifive_spi) = {
+ .name = "sifive_spi",
+ .id = UCLASS_SPI,
+ .of_match = sifive_spi_ids,
+ .ops = &sifive_spi_ops,
+ .priv_auto_alloc_size = sizeof(struct sifive_spi),
+ .probe = sifive_spi_probe,
+};
diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index 88cb2a1..76c4b53 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -108,6 +108,30 @@
return dm_spi_xfer(slave->dev, bitlen, dout, din, flags);
}
+int spi_write_then_read(struct spi_slave *slave, const u8 *opcode,
+ size_t n_opcode, const u8 *txbuf, u8 *rxbuf,
+ size_t n_buf)
+{
+ unsigned long flags = SPI_XFER_BEGIN;
+ int ret;
+
+ if (n_buf == 0)
+ flags |= SPI_XFER_END;
+
+ ret = spi_xfer(slave, n_opcode * 8, opcode, NULL, flags);
+ if (ret) {
+ debug("spi: failed to send command (%zu bytes): %d\n",
+ n_opcode, ret);
+ } else if (n_buf != 0) {
+ ret = spi_xfer(slave, n_buf * 8, txbuf, rxbuf, SPI_XFER_END);
+ if (ret)
+ debug("spi: failed to transfer %zu bytes of data: %d\n",
+ n_buf, ret);
+ }
+
+ return ret;
+}
+
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
static int spi_child_post_bind(struct udevice *dev)
{
diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c
index bb1067f..958c394 100644
--- a/drivers/spi/stm32_qspi.c
+++ b/drivers/spi/stm32_qspi.c
@@ -361,9 +361,9 @@
}
priv->clock_rate = clk_get_rate(&clk);
- if (priv->clock_rate < 0) {
+ if (!priv->clock_rate) {
clk_disable(&clk);
- return priv->clock_rate;
+ return -EINVAL;
}
ret = reset_get_by_index(bus, 0, &reset_ctl);
@@ -395,14 +395,15 @@
{
struct stm32_qspi_priv *priv = dev_get_priv(dev->parent);
struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ int slave_cs = slave_plat->cs;
- if (slave_plat->cs >= STM32_QSPI_MAX_CHIP)
+ if (slave_cs >= STM32_QSPI_MAX_CHIP)
return -ENODEV;
- if (priv->cs_used != slave_plat->cs) {
- struct stm32_qspi_flash *flash = &priv->flash[slave_plat->cs];
+ if (priv->cs_used != slave_cs) {
+ struct stm32_qspi_flash *flash = &priv->flash[slave_cs];
- priv->cs_used = slave_plat->cs;
+ priv->cs_used = slave_cs;
if (flash->initialized) {
/* Set the configuration: speed + cs */
@@ -444,11 +445,12 @@
int ret;
if (speed > 0) {
- prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;
- if (prescaler > 255)
- prescaler = 255;
- else if (prescaler < 0)
- prescaler = 0;
+ prescaler = 0;
+ if (qspi_clk) {
+ prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;
+ if (prescaler > 255)
+ prescaler = 255;
+ }
}
csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000);
@@ -524,7 +526,6 @@
};
static const struct udevice_id stm32_qspi_ids[] = {
- { .compatible = "st,stm32-qspi" },
{ .compatible = "st,stm32f469-qspi" },
{ }
};
diff --git a/drivers/spi/stm32_spi.c b/drivers/spi/stm32_spi.c
index 34b2175..75b6006 100644
--- a/drivers/spi/stm32_spi.c
+++ b/drivers/spi/stm32_spi.c
@@ -99,8 +99,8 @@
unsigned int cur_bpw;
unsigned int cur_hz;
unsigned int cur_xferlen; /* current transfer length in bytes */
- int tx_len; /* number of data to be written in bytes */
- int rx_len; /* number of data to be read in bytes */
+ unsigned int tx_len; /* number of data to be written in bytes */
+ unsigned int rx_len; /* number of data to be read in bytes */
const void *tx_buf; /* data to be written, or NULL */
void *rx_buf; /* data to be read, or NULL */
u32 cur_mode;
@@ -322,7 +322,8 @@
static int stm32_spi_set_speed(struct udevice *bus, uint hz)
{
struct stm32_spi_priv *priv = dev_get_priv(bus);
- u32 div, mbrdiv;
+ u32 mbrdiv;
+ long div;
debug("%s: hz=%d\n", __func__, hz);
@@ -341,7 +342,7 @@
else
mbrdiv = fls(div) - 1;
- if ((mbrdiv - 1) < 0)
+ if (!mbrdiv)
return -EINVAL;
clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_MBR,
@@ -481,7 +482,7 @@
struct stm32_spi_priv *priv = dev_get_priv(dev);
unsigned long clk_rate;
int ret;
- int i;
+ unsigned int i;
priv->base = dev_remap_addr(dev);
if (!priv->base)
diff --git a/drivers/spi/uniphier_spi.c b/drivers/spi/uniphier_spi.c
new file mode 100644
index 0000000..ef02d07
--- /dev/null
+++ b/drivers/spi/uniphier_spi.c
@@ -0,0 +1,413 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * uniphier_spi.c - Socionext UniPhier SPI driver
+ * Copyright 2019 Socionext, Inc.
+ */
+
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <linux/bitfield.h>
+#include <linux/io.h>
+#include <spi.h>
+#include <wait_bit.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SSI_CTL 0x00
+#define SSI_CTL_EN BIT(0)
+
+#define SSI_CKS 0x04
+#define SSI_CKS_CKRAT_MASK GENMASK(7, 0)
+#define SSI_CKS_CKPHS BIT(14)
+#define SSI_CKS_CKINIT BIT(13)
+#define SSI_CKS_CKDLY BIT(12)
+
+#define SSI_TXWDS 0x08
+#define SSI_TXWDS_WDLEN_MASK GENMASK(13, 8)
+#define SSI_TXWDS_TDTF_MASK GENMASK(7, 6)
+#define SSI_TXWDS_DTLEN_MASK GENMASK(5, 0)
+
+#define SSI_RXWDS 0x0c
+#define SSI_RXWDS_RDTF_MASK GENMASK(7, 6)
+#define SSI_RXWDS_DTLEN_MASK GENMASK(5, 0)
+
+#define SSI_FPS 0x10
+#define SSI_FPS_FSPOL BIT(15)
+#define SSI_FPS_FSTRT BIT(14)
+
+#define SSI_SR 0x14
+#define SSI_SR_BUSY BIT(7)
+#define SSI_SR_TNF BIT(5)
+#define SSI_SR_RNE BIT(0)
+
+#define SSI_IE 0x18
+
+#define SSI_IC 0x1c
+#define SSI_IC_TCIC BIT(4)
+#define SSI_IC_RCIC BIT(3)
+#define SSI_IC_RORIC BIT(0)
+
+#define SSI_FC 0x20
+#define SSI_FC_TXFFL BIT(12)
+#define SSI_FC_TXFTH_MASK GENMASK(11, 8)
+#define SSI_FC_RXFFL BIT(4)
+#define SSI_FC_RXFTH_MASK GENMASK(3, 0)
+
+#define SSI_XDR 0x24 /* TXDR for write, RXDR for read */
+
+#define SSI_FIFO_DEPTH 8U
+
+#define SSI_REG_TIMEOUT (CONFIG_SYS_HZ / 100) /* 10 ms */
+#define SSI_XFER_TIMEOUT (CONFIG_SYS_HZ) /* 1 sec */
+
+#define SSI_CLK 50000000 /* internal I/O clock: 50MHz */
+
+struct uniphier_spi_platdata {
+ void __iomem *base;
+ u32 frequency; /* input frequency */
+ u32 speed_hz;
+ uint deactivate_delay_us; /* Delay to wait after deactivate */
+ uint activate_delay_us; /* Delay to wait after activate */
+};
+
+struct uniphier_spi_priv {
+ void __iomem *base;
+ u8 mode;
+ u8 fifo_depth;
+ u8 bits_per_word;
+ ulong last_transaction_us; /* Time of last transaction end */
+};
+
+static void uniphier_spi_enable(struct uniphier_spi_priv *priv, int enable)
+{
+ u32 val;
+
+ val = readl(priv->base + SSI_CTL);
+ if (enable)
+ val |= SSI_CTL_EN;
+ else
+ val &= ~SSI_CTL_EN;
+ writel(val, priv->base + SSI_CTL);
+}
+
+static void uniphier_spi_regdump(struct uniphier_spi_priv *priv)
+{
+ pr_debug("CTL %08x\n", readl(priv->base + SSI_CTL));
+ pr_debug("CKS %08x\n", readl(priv->base + SSI_CKS));
+ pr_debug("TXWDS %08x\n", readl(priv->base + SSI_TXWDS));
+ pr_debug("RXWDS %08x\n", readl(priv->base + SSI_RXWDS));
+ pr_debug("FPS %08x\n", readl(priv->base + SSI_FPS));
+ pr_debug("SR %08x\n", readl(priv->base + SSI_SR));
+ pr_debug("IE %08x\n", readl(priv->base + SSI_IE));
+ pr_debug("IC %08x\n", readl(priv->base + SSI_IC));
+ pr_debug("FC %08x\n", readl(priv->base + SSI_FC));
+ pr_debug("XDR %08x\n", readl(priv->base + SSI_XDR));
+}
+
+static void spi_cs_activate(struct udevice *dev)
+{
+ struct udevice *bus = dev->parent;
+ struct uniphier_spi_platdata *plat = bus->platdata;
+ struct uniphier_spi_priv *priv = dev_get_priv(bus);
+ ulong delay_us; /* The delay completed so far */
+ u32 val;
+
+ /* If it's too soon to do another transaction, wait */
+ if (plat->deactivate_delay_us && priv->last_transaction_us) {
+ delay_us = timer_get_us() - priv->last_transaction_us;
+ if (delay_us < plat->deactivate_delay_us)
+ udelay(plat->deactivate_delay_us - delay_us);
+ }
+
+ val = readl(priv->base + SSI_FPS);
+ if (priv->mode & SPI_CS_HIGH)
+ val |= SSI_FPS_FSPOL;
+ else
+ val &= ~SSI_FPS_FSPOL;
+ writel(val, priv->base + SSI_FPS);
+
+ if (plat->activate_delay_us)
+ udelay(plat->activate_delay_us);
+}
+
+static void spi_cs_deactivate(struct udevice *dev)
+{
+ struct udevice *bus = dev->parent;
+ struct uniphier_spi_platdata *plat = bus->platdata;
+ struct uniphier_spi_priv *priv = dev_get_priv(bus);
+ u32 val;
+
+ val = readl(priv->base + SSI_FPS);
+ if (priv->mode & SPI_CS_HIGH)
+ val &= ~SSI_FPS_FSPOL;
+ else
+ val |= SSI_FPS_FSPOL;
+ writel(val, priv->base + SSI_FPS);
+
+ /* Remember time of this transaction so we can honour the bus delay */
+ if (plat->deactivate_delay_us)
+ priv->last_transaction_us = timer_get_us();
+}
+
+static int uniphier_spi_claim_bus(struct udevice *dev)
+{
+ struct udevice *bus = dev->parent;
+ struct uniphier_spi_priv *priv = dev_get_priv(bus);
+ u32 val, size;
+
+ uniphier_spi_enable(priv, false);
+
+ /* disable interrupts */
+ writel(0, priv->base + SSI_IE);
+
+ /* bits_per_word */
+ size = priv->bits_per_word;
+ val = readl(priv->base + SSI_TXWDS);
+ val &= ~(SSI_TXWDS_WDLEN_MASK | SSI_TXWDS_DTLEN_MASK);
+ val |= FIELD_PREP(SSI_TXWDS_WDLEN_MASK, size);
+ val |= FIELD_PREP(SSI_TXWDS_DTLEN_MASK, size);
+ writel(val, priv->base + SSI_TXWDS);
+
+ val = readl(priv->base + SSI_RXWDS);
+ val &= ~SSI_RXWDS_DTLEN_MASK;
+ val |= FIELD_PREP(SSI_RXWDS_DTLEN_MASK, size);
+ writel(val, priv->base + SSI_RXWDS);
+
+ /* reset FIFOs */
+ val = SSI_FC_TXFFL | SSI_FC_RXFFL;
+ writel(val, priv->base + SSI_FC);
+
+ /* FIFO threthold */
+ val = readl(priv->base + SSI_FC);
+ val &= ~(SSI_FC_TXFTH_MASK | SSI_FC_RXFTH_MASK);
+ val |= FIELD_PREP(SSI_FC_TXFTH_MASK, priv->fifo_depth);
+ val |= FIELD_PREP(SSI_FC_RXFTH_MASK, priv->fifo_depth);
+ writel(val, priv->base + SSI_FC);
+
+ /* clear interrupts */
+ writel(SSI_IC_TCIC | SSI_IC_RCIC | SSI_IC_RORIC,
+ priv->base + SSI_IC);
+
+ uniphier_spi_enable(priv, true);
+
+ return 0;
+}
+
+static int uniphier_spi_release_bus(struct udevice *dev)
+{
+ struct udevice *bus = dev->parent;
+ struct uniphier_spi_priv *priv = dev_get_priv(bus);
+
+ uniphier_spi_enable(priv, false);
+
+ return 0;
+}
+
+static int uniphier_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct udevice *bus = dev->parent;
+ struct uniphier_spi_priv *priv = dev_get_priv(bus);
+ const u8 *tx_buf = dout;
+ u8 *rx_buf = din, buf;
+ u32 len = bitlen / 8;
+ u32 tx_len, rx_len;
+ u32 ts, status;
+ int ret = 0;
+
+ if (bitlen % 8) {
+ dev_err(dev, "Non byte aligned SPI transfer\n");
+ return -EINVAL;
+ }
+
+ if (flags & SPI_XFER_BEGIN)
+ spi_cs_activate(dev);
+
+ uniphier_spi_enable(priv, true);
+
+ ts = get_timer(0);
+ tx_len = len;
+ rx_len = len;
+
+ uniphier_spi_regdump(priv);
+
+ while (tx_len || rx_len) {
+ ret = wait_for_bit_le32(priv->base + SSI_SR, SSI_SR_BUSY, false,
+ SSI_REG_TIMEOUT * 1000, false);
+ if (ret) {
+ if (ret == -ETIMEDOUT)
+ dev_err(dev, "access timeout\n");
+ break;
+ }
+
+ status = readl(priv->base + SSI_SR);
+ /* write the data into TX */
+ if (tx_len && (status & SSI_SR_TNF)) {
+ buf = tx_buf ? *tx_buf++ : 0;
+ writel(buf, priv->base + SSI_XDR);
+ tx_len--;
+ }
+
+ /* read the data from RX */
+ if (rx_len && (status & SSI_SR_RNE)) {
+ buf = readl(priv->base + SSI_XDR);
+ if (rx_buf)
+ *rx_buf++ = buf;
+ rx_len--;
+ }
+
+ if (get_timer(ts) >= SSI_XFER_TIMEOUT) {
+ dev_err(dev, "transfer timeout\n");
+ ret = -ETIMEDOUT;
+ break;
+ }
+ }
+
+ if (flags & SPI_XFER_END)
+ spi_cs_deactivate(dev);
+
+ uniphier_spi_enable(priv, false);
+
+ return ret;
+}
+
+static int uniphier_spi_set_speed(struct udevice *bus, uint speed)
+{
+ struct uniphier_spi_platdata *plat = bus->platdata;
+ struct uniphier_spi_priv *priv = dev_get_priv(bus);
+ u32 val, ckdiv;
+
+ if (speed > plat->frequency)
+ speed = plat->frequency;
+
+ /* baudrate */
+ ckdiv = DIV_ROUND_UP(SSI_CLK, speed);
+ ckdiv = round_up(ckdiv, 2);
+
+ val = readl(priv->base + SSI_CKS);
+ val &= ~SSI_CKS_CKRAT_MASK;
+ val |= ckdiv & SSI_CKS_CKRAT_MASK;
+ writel(val, priv->base + SSI_CKS);
+
+ return 0;
+}
+
+static int uniphier_spi_set_mode(struct udevice *bus, uint mode)
+{
+ struct uniphier_spi_priv *priv = dev_get_priv(bus);
+ u32 val1, val2;
+
+ /*
+ * clock setting
+ * CKPHS capture timing. 0:rising edge, 1:falling edge
+ * CKINIT clock initial level. 0:low, 1:high
+ * CKDLY clock delay. 0:no delay, 1:delay depending on FSTRT
+ * (FSTRT=0: 1 clock, FSTRT=1: 0.5 clock)
+ *
+ * frame setting
+ * FSPOL frame signal porarity. 0: low, 1: high
+ * FSTRT start frame timing
+ * 0: rising edge of clock, 1: falling edge of clock
+ */
+ val1 = readl(priv->base + SSI_CKS);
+ val2 = readl(priv->base + SSI_FPS);
+
+ switch (mode & (SPI_CPOL | SPI_CPHA)) {
+ case SPI_MODE_0:
+ /* CKPHS=1, CKINIT=0, CKDLY=1, FSTRT=0 */
+ val1 |= SSI_CKS_CKPHS | SSI_CKS_CKDLY;
+ val1 &= ~SSI_CKS_CKINIT;
+ val2 &= ~SSI_FPS_FSTRT;
+ break;
+ case SPI_MODE_1:
+ /* CKPHS=0, CKINIT=0, CKDLY=0, FSTRT=1 */
+ val1 &= ~(SSI_CKS_CKPHS | SSI_CKS_CKINIT | SSI_CKS_CKDLY);
+ val2 |= SSI_FPS_FSTRT;
+ break;
+ case SPI_MODE_2:
+ /* CKPHS=0, CKINIT=1, CKDLY=1, FSTRT=1 */
+ val1 |= SSI_CKS_CKINIT | SSI_CKS_CKDLY;
+ val1 &= ~SSI_CKS_CKPHS;
+ val2 |= SSI_FPS_FSTRT;
+ break;
+ case SPI_MODE_3:
+ /* CKPHS=1, CKINIT=1, CKDLY=0, FSTRT=0 */
+ val1 |= SSI_CKS_CKPHS | SSI_CKS_CKINIT;
+ val1 &= ~SSI_CKS_CKDLY;
+ val2 &= ~SSI_FPS_FSTRT;
+ break;
+ }
+
+ writel(val1, priv->base + SSI_CKS);
+ writel(val2, priv->base + SSI_FPS);
+
+ /* format */
+ val1 = readl(priv->base + SSI_TXWDS);
+ val2 = readl(priv->base + SSI_RXWDS);
+ if (mode & SPI_LSB_FIRST) {
+ val1 |= FIELD_PREP(SSI_TXWDS_TDTF_MASK, 1);
+ val2 |= FIELD_PREP(SSI_RXWDS_RDTF_MASK, 1);
+ }
+ writel(val1, priv->base + SSI_TXWDS);
+ writel(val2, priv->base + SSI_RXWDS);
+
+ priv->mode = mode;
+
+ return 0;
+}
+
+static int uniphier_spi_ofdata_to_platdata(struct udevice *bus)
+{
+ struct uniphier_spi_platdata *plat = bus->platdata;
+ const void *blob = gd->fdt_blob;
+ int node = dev_of_offset(bus);
+
+ plat->base = devfdt_get_addr_ptr(bus);
+
+ plat->frequency =
+ fdtdec_get_int(blob, node, "spi-max-frequency", 12500000);
+ plat->deactivate_delay_us =
+ fdtdec_get_int(blob, node, "spi-deactivate-delay", 0);
+ plat->activate_delay_us =
+ fdtdec_get_int(blob, node, "spi-activate-delay", 0);
+ plat->speed_hz = plat->frequency / 2;
+
+ return 0;
+}
+
+static int uniphier_spi_probe(struct udevice *bus)
+{
+ struct uniphier_spi_platdata *plat = dev_get_platdata(bus);
+ struct uniphier_spi_priv *priv = dev_get_priv(bus);
+
+ priv->base = plat->base;
+ priv->fifo_depth = SSI_FIFO_DEPTH;
+ priv->bits_per_word = 8;
+
+ return 0;
+}
+
+static const struct dm_spi_ops uniphier_spi_ops = {
+ .claim_bus = uniphier_spi_claim_bus,
+ .release_bus = uniphier_spi_release_bus,
+ .xfer = uniphier_spi_xfer,
+ .set_speed = uniphier_spi_set_speed,
+ .set_mode = uniphier_spi_set_mode,
+};
+
+static const struct udevice_id uniphier_spi_ids[] = {
+ { .compatible = "socionext,uniphier-scssi" },
+ { /* Sentinel */ }
+};
+
+U_BOOT_DRIVER(uniphier_spi) = {
+ .name = "uniphier_spi",
+ .id = UCLASS_SPI,
+ .of_match = uniphier_spi_ids,
+ .ops = &uniphier_spi_ops,
+ .ofdata_to_platdata = uniphier_spi_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct uniphier_spi_platdata),
+ .priv_auto_alloc_size = sizeof(struct uniphier_spi_priv),
+ .probe = uniphier_spi_probe,
+};
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index 30aed2c..f565ae0 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -33,6 +33,16 @@
if SYSRESET
+if CMD_POWEROFF
+
+config SYSRESET_CMD_POWEROFF
+ bool "sysreset implementation of the poweroff command"
+ help
+ This should be selected by the appropriate PMIC driver if
+ the poweroff command is enabled.
+
+endif
+
config SYSRESET_GPIO
bool "Enable support for GPIO reset driver"
select DM_GPIO
@@ -50,10 +60,25 @@
config SYSRESET_PSCI
bool "Enable support for PSCI System Reset"
depends on ARM_PSCI_FW
+ select SPL_ARM_PSCI_FW if SPL
help
Enable PSCI SYSTEM_RESET function call. To use this, PSCI firmware
must be running on your system.
+config SYSRESET_SOCFPGA
+ bool "Enable support for Intel SOCFPGA family"
+ depends on ARCH_SOCFPGA && (TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10)
+ help
+ This enables the system reset driver support for Intel SOCFPGA SoCs
+ (Cyclone 5, Arria 5 and Arria 10).
+
+config SYSRESET_SOCFPGA_S10
+ bool "Enable support for Intel SOCFPGA Stratix 10"
+ depends on ARCH_SOCFPGA && TARGET_SOCFPGA_STRATIX10
+ help
+ This enables the system reset driver support for Intel SOCFPGA
+ Stratix SoCs.
+
config SYSRESET_TI_SCI
bool "TI System Control Interface (TI SCI) system reset driver"
depends on TI_SCI_PROTOCOL
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index 8e1c845..cf01492 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -11,6 +11,8 @@
obj-$(CONFIG_SYSRESET_MCP83XX) += sysreset_mpc83xx.o
obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o
obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
+obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o
+obj-$(CONFIG_SYSRESET_SOCFPGA_S10) += sysreset_socfpga_s10.o
obj-$(CONFIG_SYSRESET_TI_SCI) += sysreset-ti-sci.o
obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o
obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o
diff --git a/drivers/sysreset/sysreset-uclass.c b/drivers/sysreset/sysreset-uclass.c
index ad831c7..3920258 100644
--- a/drivers/sysreset/sysreset-uclass.c
+++ b/drivers/sysreset/sysreset-uclass.c
@@ -118,6 +118,24 @@
return 0;
}
+#if IS_ENABLED(CONFIG_SYSRESET_CMD_POWEROFF)
+int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int ret;
+
+ puts("poweroff ...\n");
+ mdelay(100);
+
+ ret = sysreset_walk(SYSRESET_POWER_OFF);
+
+ if (ret == -EINPROGRESS)
+ mdelay(1000);
+
+ /*NOTREACHED when power off*/
+ return CMD_RET_FAILURE;
+}
+#endif
+
static int sysreset_post_bind(struct udevice *dev)
{
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
diff --git a/drivers/sysreset/sysreset_psci.c b/drivers/sysreset/sysreset_psci.c
index de2ec8a..c7907b3 100644
--- a/drivers/sysreset/sysreset_psci.c
+++ b/drivers/sysreset/sysreset_psci.c
@@ -18,7 +18,7 @@
case SYSRESET_COLD:
function_id = PSCI_0_2_FN_SYSTEM_RESET;
break;
- case SYSRESET_POWER:
+ case SYSRESET_POWER_OFF:
function_id = PSCI_0_2_FN_SYSTEM_OFF;
break;
default:
diff --git a/drivers/sysreset/sysreset_sandbox.c b/drivers/sysreset/sysreset_sandbox.c
index 38e2a7e..69c22a7 100644
--- a/drivers/sysreset/sysreset_sandbox.c
+++ b/drivers/sysreset/sysreset_sandbox.c
@@ -57,15 +57,16 @@
case SYSRESET_COLD:
state->last_sysreset = type;
break;
- case SYSRESET_POWER:
+ case SYSRESET_POWER_OFF:
state->last_sysreset = type;
if (!state->sysreset_allowed[type])
return -EACCES;
sandbox_exit();
break;
- case SYSRESET_POWER_OFF:
+ case SYSRESET_POWER:
if (!state->sysreset_allowed[type])
return -EACCES;
+ sandbox_exit();
default:
return -ENOSYS;
}
diff --git a/drivers/sysreset/sysreset_socfpga.c b/drivers/sysreset/sysreset_socfpga.c
new file mode 100644
index 0000000..d6c26a5
--- /dev/null
+++ b/drivers/sysreset/sysreset_socfpga.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Pepperl+Fuchs
+ * Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <sysreset.h>
+#include <asm/io.h>
+#include <asm/arch/reset_manager.h>
+
+struct socfpga_sysreset_data {
+ struct socfpga_reset_manager *rstmgr_base;
+};
+
+static int socfpga_sysreset_request(struct udevice *dev,
+ enum sysreset_t type)
+{
+ struct socfpga_sysreset_data *data = dev_get_priv(dev);
+
+ switch (type) {
+ case SYSRESET_WARM:
+ writel(BIT(RSTMGR_CTRL_SWWARMRSTREQ_LSB),
+ &data->rstmgr_base->ctrl);
+ break;
+ case SYSRESET_COLD:
+ writel(BIT(RSTMGR_CTRL_SWCOLDRSTREQ_LSB),
+ &data->rstmgr_base->ctrl);
+ break;
+ default:
+ return -EPROTONOSUPPORT;
+ }
+ return -EINPROGRESS;
+}
+
+static int socfpga_sysreset_probe(struct udevice *dev)
+{
+ struct socfpga_sysreset_data *data = dev_get_priv(dev);
+
+ data->rstmgr_base = devfdt_get_addr_ptr(dev);
+ return 0;
+}
+
+static struct sysreset_ops socfpga_sysreset = {
+ .request = socfpga_sysreset_request,
+};
+
+U_BOOT_DRIVER(sysreset_socfpga) = {
+ .id = UCLASS_SYSRESET,
+ .name = "socfpga_sysreset",
+ .priv_auto_alloc_size = sizeof(struct socfpga_sysreset_data),
+ .ops = &socfpga_sysreset,
+ .probe = socfpga_sysreset_probe,
+};
diff --git a/drivers/sysreset/sysreset_socfpga_s10.c b/drivers/sysreset/sysreset_socfpga_s10.c
new file mode 100644
index 0000000..9837aad
--- /dev/null
+++ b/drivers/sysreset/sysreset_socfpga_s10.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Pepperl+Fuchs
+ * Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <sysreset.h>
+#include <asm/arch/mailbox_s10.h>
+
+static int socfpga_sysreset_request(struct udevice *dev,
+ enum sysreset_t type)
+{
+ puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n");
+ mbox_reset_cold();
+ return -EINPROGRESS;
+}
+
+static struct sysreset_ops socfpga_sysreset = {
+ .request = socfpga_sysreset_request,
+};
+
+U_BOOT_DRIVER(sysreset_socfpga) = {
+ .id = UCLASS_SYSRESET,
+ .name = "socfpga_sysreset",
+ .ops = &socfpga_sysreset,
+};
diff --git a/drivers/sysreset/sysreset_syscon.c b/drivers/sysreset/sysreset_syscon.c
index 1028160..d0e586f 100644
--- a/drivers/sysreset/sysreset_syscon.c
+++ b/drivers/sysreset/sysreset_syscon.c
@@ -23,8 +23,9 @@
static int syscon_reboot_request(struct udevice *dev, enum sysreset_t type)
{
struct syscon_reboot_priv *priv = dev_get_priv(dev);
+ ulong driver_data = dev_get_driver_data(dev);
- if (type == SYSRESET_POWER)
+ if (type != driver_data)
return -EPROTONOSUPPORT;
regmap_write(priv->regmap, priv->offset, priv->mask);
@@ -53,7 +54,8 @@
}
static const struct udevice_id syscon_reboot_ids[] = {
- { .compatible = "syscon-reboot" },
+ { .compatible = "syscon-reboot", .data = SYSRESET_COLD },
+ { .compatible = "syscon-poweroff", .data = SYSRESET_POWER_OFF },
{ /* sentinel */ }
};
diff --git a/drivers/tee/sandbox.c b/drivers/tee/sandbox.c
index 2f3355c..4b91e7d 100644
--- a/drivers/tee/sandbox.c
+++ b/drivers/tee/sandbox.c
@@ -79,7 +79,7 @@
struct tee_param *params)
{
struct sandbox_tee_state *state = dev_get_priv(dev);
- ENTRY e, *ep;
+ struct env_entry e, *ep;
char *name;
u32 res;
uint slot;
@@ -174,7 +174,7 @@
e.key = name;
e.data = NULL;
- hsearch_r(e, FIND, &ep, &state->pstorage_htab, 0);
+ hsearch_r(e, ENV_FIND, &ep, &state->pstorage_htab, 0);
if (!ep)
return TEE_ERROR_ITEM_NOT_FOUND;
@@ -198,13 +198,13 @@
e.key = name;
e.data = NULL;
- hsearch_r(e, FIND, &ep, &state->pstorage_htab, 0);
+ hsearch_r(e, ENV_FIND, &ep, &state->pstorage_htab, 0);
if (ep)
hdelete_r(e.key, &state->pstorage_htab, 0);
e.key = name;
e.data = value;
- hsearch_r(e, ENTER, &ep, &state->pstorage_htab, 0);
+ hsearch_r(e, ENV_ENTER, &ep, &state->pstorage_htab, 0);
if (!ep)
return TEE_ERROR_OUT_OF_MEMORY;
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index a71b9be..bdf8dc6 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -17,6 +17,15 @@
cpufreq is used as the cooling device to throttle CPUs when the
passive trip is crossed.
+config IMX_SCU_THERMAL
+ bool "Temperature sensor driver for NXP i.MX8"
+ depends on ARCH_IMX8
+ help
+ Support for Temperature sensors on NXP i.MX8.
+ It supports one critical trip point and one passive trip point. The
+ boot is hold to the cool device to throttle CPUs when the passive
+ trip is crossed
+
config TI_DRA7_THERMAL
bool "Temperature sensor driver for TI dra7xx SOCs"
help
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
index cc75e38..ef2929d 100644
--- a/drivers/thermal/Makefile
+++ b/drivers/thermal/Makefile
@@ -5,4 +5,5 @@
obj-$(CONFIG_DM_THERMAL) += thermal-uclass.o
obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o
+obj-$(CONFIG_IMX_SCU_THERMAL) += imx_scu_thermal.o
obj-$(CONFIG_TI_DRA7_THERMAL) += ti-bandgap.o
diff --git a/drivers/thermal/imx_scu_thermal.c b/drivers/thermal/imx_scu_thermal.c
new file mode 100644
index 0000000..7e17377
--- /dev/null
+++ b/drivers/thermal/imx_scu_thermal.c
@@ -0,0 +1,203 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <config.h>
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <thermal.h>
+#include <dm/device-internal.h>
+#include <dm/device.h>
+#include <asm/arch/sci/sci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct imx_sc_thermal_plat {
+ int critical;
+ int alert;
+ int polling_delay;
+ int id;
+ bool zone_node;
+};
+
+static int read_temperature(struct udevice *dev, int *temp)
+{
+ s16 celsius;
+ s8 tenths;
+ int ret;
+
+ sc_rsrc_t *sensor_rsrc = (sc_rsrc_t *)dev_get_driver_data(dev);
+
+ struct imx_sc_thermal_plat *pdata = dev_get_platdata(dev);
+
+ if (!temp)
+ return -EINVAL;
+
+ ret = sc_misc_get_temp(-1, sensor_rsrc[pdata->id], SC_C_TEMP,
+ &celsius, &tenths);
+ if (ret) {
+ printf("Error: get temperature failed! (error = %d)\n", ret);
+ return ret;
+ }
+
+ *temp = celsius * 1000 + tenths * 100;
+
+ return 0;
+}
+
+int imx_sc_thermal_get_temp(struct udevice *dev, int *temp)
+{
+ struct imx_sc_thermal_plat *pdata = dev_get_platdata(dev);
+ int cpu_temp = 0;
+ int ret;
+
+ ret = read_temperature(dev, &cpu_temp);
+ if (ret)
+ return ret;
+
+ while (cpu_temp >= pdata->alert) {
+ printf("CPU Temperature (%dC) has beyond alert (%dC), close to critical (%dC)",
+ cpu_temp, pdata->alert, pdata->critical);
+ puts(" waiting...\n");
+ mdelay(pdata->polling_delay);
+ ret = read_temperature(dev, &cpu_temp);
+ if (ret)
+ return ret;
+ }
+
+ *temp = cpu_temp / 1000;
+
+ return 0;
+}
+
+static const struct dm_thermal_ops imx_sc_thermal_ops = {
+ .get_temp = imx_sc_thermal_get_temp,
+};
+
+static int imx_sc_thermal_probe(struct udevice *dev)
+{
+ debug("%s dev name %s\n", __func__, dev->name);
+ return 0;
+}
+
+static int imx_sc_thermal_bind(struct udevice *dev)
+{
+ struct imx_sc_thermal_plat *pdata = dev_get_platdata(dev);
+ int reg, ret;
+ int offset;
+ const char *name;
+ const void *prop;
+
+ debug("%s dev name %s\n", __func__, dev->name);
+
+ prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "compatible",
+ NULL);
+ if (!prop)
+ return 0;
+
+ pdata->zone_node = 1;
+
+ reg = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "tsens-num", 0);
+ if (reg == 0) {
+ printf("%s: no temp sensor number provided!\n", __func__);
+ return -EINVAL;
+ }
+
+ offset = fdt_subnode_offset(gd->fdt_blob, 0, "thermal-zones");
+ fdt_for_each_subnode(offset, gd->fdt_blob, offset) {
+ /* Bind the subnode to this driver */
+ name = fdt_get_name(gd->fdt_blob, offset, NULL);
+
+ ret = device_bind_with_driver_data(dev, dev->driver, name,
+ dev->driver_data,
+ offset_to_ofnode(offset),
+ NULL);
+ if (ret)
+ printf("Error binding driver '%s': %d\n",
+ dev->driver->name, ret);
+ }
+ return 0;
+}
+
+static int imx_sc_thermal_ofdata_to_platdata(struct udevice *dev)
+{
+ struct imx_sc_thermal_plat *pdata = dev_get_platdata(dev);
+ struct fdtdec_phandle_args args;
+ const char *type;
+ int ret;
+ int trips_np;
+
+ debug("%s dev name %s\n", __func__, dev->name);
+
+ if (pdata->zone_node)
+ return 0;
+
+ ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev_of_offset(dev),
+ "thermal-sensors",
+ "#thermal-sensor-cells",
+ 0, 0, &args);
+ if (ret)
+ return ret;
+
+ if (args.node != dev_of_offset(dev->parent))
+ return -EFAULT;
+
+ if (args.args_count >= 1)
+ pdata->id = args.args[0];
+ else
+ pdata->id = 0;
+
+ debug("args.args_count %d, id %d\n", args.args_count, pdata->id);
+
+ pdata->polling_delay = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "polling-delay", 1000);
+
+ trips_np = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(dev),
+ "trips");
+ fdt_for_each_subnode(trips_np, gd->fdt_blob, trips_np) {
+ type = fdt_getprop(gd->fdt_blob, trips_np, "type", NULL);
+ if (type) {
+ if (strcmp(type, "critical") == 0) {
+ pdata->critical = fdtdec_get_int(gd->fdt_blob,
+ trips_np,
+ "temperature",
+ 85);
+ } else if (strcmp(type, "passive") == 0) {
+ pdata->alert = fdtdec_get_int(gd->fdt_blob,
+ trips_np,
+ "temperature",
+ 80);
+ }
+ }
+ }
+
+ debug("id %d polling_delay %d, critical %d, alert %d\n", pdata->id,
+ pdata->polling_delay, pdata->critical, pdata->alert);
+
+ return 0;
+}
+
+static const sc_rsrc_t imx8qxp_sensor_rsrc[] = {
+ SC_R_SYSTEM, SC_R_DRC_0, SC_R_PMIC_0,
+ SC_R_PMIC_1, SC_R_PMIC_2,
+};
+
+static const struct udevice_id imx_sc_thermal_ids[] = {
+ { .compatible = "nxp,imx8qxp-sc-tsens", .data =
+ (ulong)&imx8qxp_sensor_rsrc, },
+ { }
+};
+
+U_BOOT_DRIVER(imx_sc_thermal) = {
+ .name = "imx_sc_thermal",
+ .id = UCLASS_THERMAL,
+ .ops = &imx_sc_thermal_ops,
+ .of_match = imx_sc_thermal_ids,
+ .bind = imx_sc_thermal_bind,
+ .probe = imx_sc_thermal_probe,
+ .ofdata_to_platdata = imx_sc_thermal_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct imx_sc_thermal_plat),
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c
index 12ee6eb..97a4c74 100644
--- a/drivers/timer/timer-uclass.c
+++ b/drivers/timer/timer-uclass.c
@@ -48,6 +48,10 @@
int err;
ulong ret;
+ /* It is possible that a timer device has a null ofnode */
+ if (!dev_of_valid(dev))
+ return 0;
+
err = clk_get_by_index(dev, 0, &timer_clk);
if (!err) {
ret = clk_get_rate(&timer_clk);
diff --git a/drivers/tpm/tpm2_tis_spi.c b/drivers/tpm/tpm2_tis_spi.c
index 8878130..7186c17 100644
--- a/drivers/tpm/tpm2_tis_spi.c
+++ b/drivers/tpm/tpm2_tis_spi.c
@@ -295,6 +295,14 @@
return -ETIMEDOUT;
}
+static u8 tpm_tis_spi_valid_status(struct udevice *dev, u8 *status)
+{
+ struct tpm_chip *chip = dev_get_priv(dev);
+
+ return tpm_tis_spi_wait_for_stat(dev, TPM_STS_VALID,
+ chip->timeout_c, status);
+}
+
static int tpm_tis_spi_get_burstcount(struct udevice *dev)
{
struct tpm_chip *chip = dev_get_priv(dev);
@@ -455,7 +463,7 @@
i += size;
}
- ret = tpm_tis_spi_status(dev, &status);
+ ret = tpm_tis_spi_valid_status(dev, &status);
if (ret)
goto out_err;
@@ -469,7 +477,7 @@
if (ret)
goto out_err;
- ret = tpm_tis_spi_status(dev, &status);
+ ret = tpm_tis_spi_valid_status(dev, &status);
if (ret)
goto out_err;
diff --git a/drivers/usb/emul/sandbox_keyb.c b/drivers/usb/emul/sandbox_keyb.c
index 6359451..dc43880 100644
--- a/drivers/usb/emul/sandbox_keyb.c
+++ b/drivers/usb/emul/sandbox_keyb.c
@@ -178,7 +178,8 @@
}
static int sandbox_keyb_interrupt(struct udevice *dev, struct usb_device *udev,
- unsigned long pipe, void *buffer, int length, int interval)
+ unsigned long pipe, void *buffer, int length, int interval,
+ bool nonblock)
{
struct sandbox_keyb_priv *priv = dev_get_priv(dev);
uint8_t *data = buffer;
diff --git a/drivers/usb/emul/usb-emul-uclass.c b/drivers/usb/emul/usb-emul-uclass.c
index 9739815..50da6bd 100644
--- a/drivers/usb/emul/usb-emul-uclass.c
+++ b/drivers/usb/emul/usb-emul-uclass.c
@@ -245,7 +245,8 @@
}
int usb_emul_int(struct udevice *emul, struct usb_device *udev,
- unsigned long pipe, void *buffer, int length, int interval)
+ unsigned long pipe, void *buffer, int length, int interval,
+ bool nonblock)
{
struct dm_usb_ops *ops = usb_get_emul_ops(emul);
@@ -253,7 +254,8 @@
return -ENOSYS;
debug("%s: dev=%s\n", __func__, emul->name);
- return ops->interrupt(emul, udev, pipe, buffer, length, interval);
+ return ops->interrupt(emul, udev, pipe, buffer, length, interval,
+ nonblock);
}
int usb_emul_setup_device(struct udevice *dev, struct usb_string *strings,
diff --git a/drivers/usb/gadget/designware_udc.c b/drivers/usb/gadget/designware_udc.c
index fa947da..432f312 100644
--- a/drivers/usb/gadget/designware_udc.c
+++ b/drivers/usb/gadget/designware_udc.c
@@ -10,6 +10,7 @@
#include <common.h>
#include <asm/io.h>
+#include <env.h>
#include <usbdevice.h>
#include "ep0.h"
#include <usb/designware_udc.h>
diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c
index 0b5a1a4..a118283 100644
--- a/drivers/usb/gadget/ether.c
+++ b/drivers/usb/gadget/ether.c
@@ -9,7 +9,7 @@
#include <common.h>
#include <console.h>
-#include <environment.h>
+#include <env.h>
#include <linux/errno.h>
#include <linux/netdevice.h>
#include <linux/usb/ch9.h>
diff --git a/drivers/usb/gadget/f_dfu.c b/drivers/usb/gadget/f_dfu.c
index 30ece52..6756155 100644
--- a/drivers/usb/gadget/f_dfu.c
+++ b/drivers/usb/gadget/f_dfu.c
@@ -14,6 +14,7 @@
* (C) Copyright 2006 by Harald Welte <hwelte at hmw-consulting.de>
*/
+#include <env.h>
#include <errno.h>
#include <common.h>
#include <malloc.h>
@@ -748,6 +749,7 @@
if (f_dfu->function) {
i = alt_num;
+ i++; /* free DFU Functional Descriptor */
while (i) {
free(f_dfu->function[--i]);
f_dfu->function[i] = NULL;
diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c
index 3ad4346..fc27dbe 100644
--- a/drivers/usb/gadget/f_fastboot.c
+++ b/drivers/usb/gadget/f_fastboot.c
@@ -11,6 +11,7 @@
*/
#include <config.h>
#include <common.h>
+#include <env.h>
#include <errno.h>
#include <fastboot.h>
#include <malloc.h>
diff --git a/drivers/usb/gadget/f_rockusb.c b/drivers/usb/gadget/f_rockusb.c
index f3d2477..1cfeabc 100644
--- a/drivers/usb/gadget/f_rockusb.c
+++ b/drivers/usb/gadget/f_rockusb.c
@@ -6,6 +6,7 @@
*/
#include <config.h>
#include <common.h>
+#include <env.h>
#include <errno.h>
#include <malloc.h>
#include <memalign.h>
diff --git a/drivers/usb/gadget/f_sdp.c b/drivers/usb/gadget/f_sdp.c
index fab7ce6..bcd1c5d 100644
--- a/drivers/usb/gadget/f_sdp.c
+++ b/drivers/usb/gadget/f_sdp.c
@@ -19,6 +19,7 @@
#include <errno.h>
#include <common.h>
#include <console.h>
+#include <env.h>
#include <malloc.h>
#include <linux/usb/ch9.h>
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index b1188bc..30c6b69 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -24,6 +24,7 @@
config USB_XHCI_DWC3_OF_SIMPLE
bool "DesignWare USB3 DRD Generic OF Simple Glue Layer"
depends on DM_USB
+ default y if ARCH_ROCKCHIP
default y if DRA7XX
help
Support USB2/3 functionality in simple SoC integrations with
@@ -235,6 +236,13 @@
based system where you're not sure, the "lspci -v" entry will list the
right "prog-if" for your USB controller(s): EHCI, OHCI, or UHCI.
+config USB_OHCI_PCI
+ bool "Support for PCI-based OHCI USB controller"
+ depends on DM_USB
+ default n
+ help
+ Enables support for the PCI-based OHCI controller.
+
if USB_OHCI_HCD
config USB_OHCI_GENERIC
@@ -292,3 +300,12 @@
because larger transactions could be split in smaller ones.
endif # USB_DWC2
+
+config USB_R8A66597_HCD
+ bool "Renesas R8A66597 USB Core support"
+ depends on OF_CONTROL
+ depends on DM_USB
+ select USB_HOST
+ ---help---
+ This enables support for the on-chip Renesas R8A66597 USB 2.0
+ controller, present in various RZ and SH SoCs.
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 6aa574f..dd13528 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -16,6 +16,7 @@
obj-$(CONFIG_USB_SL811HS) += sl811-hcd.o
obj-$(CONFIG_USB_OHCI_EP93XX) += ohci-ep93xx.o
obj-$(CONFIG_USB_OHCI_LPC32XX) += ohci-lpc32xx.o
+obj-$(CONFIG_USB_OHCI_PCI) += ohci-pci.o
obj-$(CONFIG_USB_OHCI_GENERIC) += ohci-generic.o
# echi
diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index a62a2f8..350d820 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -1108,7 +1108,8 @@
}
int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev,
- unsigned long pipe, void *buffer, int len, int interval)
+ unsigned long pipe, void *buffer, int len, int interval,
+ bool nonblock)
{
unsigned long timeout;
int ret;
@@ -1122,7 +1123,7 @@
return -ETIMEDOUT;
}
ret = _submit_bulk_msg(priv, dev, pipe, buffer, len);
- if (ret != -EAGAIN)
+ if ((ret != -EAGAIN) || nonblock)
return ret;
}
}
@@ -1236,9 +1237,10 @@
}
int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int len, int interval)
+ int len, int interval, bool nonblock)
{
- return _submit_int_msg(&local, dev, pipe, buffer, len, interval);
+ return _submit_int_msg(&local, dev, pipe, buffer, len, interval,
+ nonblock);
}
/* U-Boot USB control interface */
@@ -1292,13 +1294,14 @@
static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev,
unsigned long pipe, void *buffer, int length,
- int interval)
+ int interval, bool nonblock)
{
struct dwc2_priv *priv = dev_get_priv(dev);
debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
- return _submit_int_msg(priv, udev, pipe, buffer, length, interval);
+ return _submit_int_msg(priv, udev, pipe, buffer, length, interval,
+ nonblock);
}
static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
diff --git a/drivers/usb/host/dwc3-of-simple.c b/drivers/usb/host/dwc3-of-simple.c
index b118997..45df614 100644
--- a/drivers/usb/host/dwc3-of-simple.c
+++ b/drivers/usb/host/dwc3-of-simple.c
@@ -92,6 +92,7 @@
static const struct udevice_id dwc3_of_simple_ids[] = {
{ .compatible = "amlogic,meson-gxl-dwc3" },
+ { .compatible = "rockchip,rk3399-dwc3" },
{ .compatible = "ti,dwc3" },
{ }
};
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index b8f8e7a..ced295e 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -8,6 +8,7 @@
*/
#include <common.h>
+#include <env.h>
#include <pci.h>
#include <usb.h>
#include <asm/io.h>
diff --git a/drivers/usb/host/ehci-generic.c b/drivers/usb/host/ehci-generic.c
index 0270f3b..682a070 100644
--- a/drivers/usb/host/ehci-generic.c
+++ b/drivers/usb/host/ehci-generic.c
@@ -96,7 +96,7 @@
if (err < 0)
break;
err = clk_enable(&priv->clocks[i]);
- if (err) {
+ if (err && err != -ENOSYS) {
dev_err(dev, "failed to enable clock %d\n", i);
clk_free(&priv->clocks[i]);
goto clk_err;
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 4b28db7..61a61ab 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -1482,7 +1482,8 @@
}
static int _ehci_submit_int_msg(struct usb_device *dev, unsigned long pipe,
- void *buffer, int length, int interval)
+ void *buffer, int length, int interval,
+ bool nonblock)
{
void *backbuffer;
struct int_queue *queue;
@@ -1532,9 +1533,10 @@
}
int submit_int_msg(struct usb_device *dev, unsigned long pipe,
- void *buffer, int length, int interval)
+ void *buffer, int length, int interval, bool nonblock)
{
- return _ehci_submit_int_msg(dev, pipe, buffer, length, interval);
+ return _ehci_submit_int_msg(dev, pipe, buffer, length, interval,
+ nonblock);
}
struct int_queue *create_int_queue(struct usb_device *dev,
@@ -1576,10 +1578,11 @@
static int ehci_submit_int_msg(struct udevice *dev, struct usb_device *udev,
unsigned long pipe, void *buffer, int length,
- int interval)
+ int interval, bool nonblock)
{
debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
- return _ehci_submit_int_msg(udev, pipe, buffer, length, interval);
+ return _ehci_submit_int_msg(udev, pipe, buffer, length, interval,
+ nonblock);
}
static struct int_queue *ehci_create_int_queue(struct udevice *dev,
diff --git a/drivers/usb/host/ohci-generic.c b/drivers/usb/host/ohci-generic.c
index 24b5c31..916ea0b 100644
--- a/drivers/usb/host/ohci-generic.c
+++ b/drivers/usb/host/ohci-generic.c
@@ -95,7 +95,7 @@
break;
err = clk_enable(&priv->clocks[i]);
- if (err) {
+ if (err && err != -ENOSYS) {
dev_err(dev, "failed to enable clock %d\n", i);
clk_free(&priv->clocks[i]);
goto clk_err;
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index 2b0df88..57e92a9 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -50,8 +50,9 @@
#endif
#if defined(CONFIG_CPU_ARM920T) || \
- defined(CONFIG_PCI_OHCI) || \
- defined(CONFIG_SYS_OHCI_USE_NPS)
+ defined(CONFIG_PCI_OHCI) || \
+ defined(CONFIG_DM_PCI) || \
+ defined(CONFIG_SYS_OHCI_USE_NPS)
# define OHCI_USE_NPS /* force NoPowerSwitching mode */
#endif
@@ -64,6 +65,7 @@
#define OHCI_CONTROL_INIT \
(OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
+#if !CONFIG_IS_ENABLED(DM_USB)
#ifdef CONFIG_PCI_OHCI
static struct pci_device_id ohci_pci_ids[] = {
{0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */
@@ -73,6 +75,7 @@
{0, 0}
};
#endif
+#endif
#ifdef CONFIG_PCI_EHCI_DEVNO
static struct pci_device_id ehci_pci_ids[] = {
@@ -1700,7 +1703,7 @@
}
int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len, int interval)
+ int transfer_len, int interval, bool nonblock)
{
info("submit_int_msg");
return submit_common_msg(&gohci, dev, pipe, buffer, transfer_len, NULL,
@@ -2044,8 +2047,11 @@
pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base);
printf("OHCI regs address 0x%08x\n", base);
gohci.regs = (struct ohci_regs *)base;
- } else
+ } else {
+ printf("%s: OHCI devnr: %d not found\n", __func__,
+ CONFIG_PCI_OHCI_DEVNO);
return -1;
+ }
#else
gohci.regs = (struct ohci_regs *)CONFIG_SYS_USB_OHCI_REGS_BASE;
#endif
@@ -2149,7 +2155,7 @@
static int ohci_submit_int_msg(struct udevice *dev, struct usb_device *udev,
unsigned long pipe, void *buffer, int length,
- int interval)
+ int interval, bool nonblock)
{
ohci_t *ohci = dev_get_priv(usb_get_bus(dev));
diff --git a/drivers/usb/host/ohci-pci.c b/drivers/usb/host/ohci-pci.c
new file mode 100644
index 0000000..4c1c778
--- /dev/null
+++ b/drivers/usb/host/ohci-pci.c
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <pci.h>
+#include <usb.h>
+#include <asm/io.h>
+
+#include "ohci.h"
+
+static int ohci_pci_probe(struct udevice *dev)
+{
+ struct ohci_regs *regs;
+
+ regs = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
+ return ohci_register(dev, regs);
+}
+
+static int ohci_pci_remove(struct udevice *dev)
+{
+ return ohci_deregister(dev);
+}
+
+static const struct udevice_id ohci_pci_ids[] = {
+ { .compatible = "ohci-pci" },
+ { }
+};
+
+U_BOOT_DRIVER(ohci_pci) = {
+ .name = "ohci_pci",
+ .id = UCLASS_USB,
+ .probe = ohci_pci_probe,
+ .remove = ohci_pci_remove,
+ .of_match = ohci_pci_ids,
+ .ops = &ohci_usb_ops,
+ .platdata_auto_alloc_size = sizeof(struct usb_platdata),
+ .priv_auto_alloc_size = sizeof(ohci_t),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
+
+static struct pci_device_id ohci_pci_supported[] = {
+ { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_OHCI, ~0) },
+ {},
+};
+
+U_BOOT_PCI_DEVICE(ohci_pci, ohci_pci_supported);
diff --git a/drivers/usb/host/ohci.h b/drivers/usb/host/ohci.h
index f9f02cb..9b264bd 100644
--- a/drivers/usb/host/ohci.h
+++ b/drivers/usb/host/ohci.h
@@ -14,8 +14,8 @@
#include <asm/io.h>
#ifdef CONFIG_SYS_OHCI_SWAP_REG_ACCESS
-# define ohci_readl(a) __swap_32(readl(a))
-# define ohci_writel(v, a) writel(__swap_32(v), a)
+# define ohci_readl(a) __swap_32(in_be32((u32 *)a))
+# define ohci_writel(a, b) out_be32((u32 *)b, __swap_32(a))
#else
# define ohci_readl(a) readl(a)
# define ohci_writel(v, a) writel(v, a)
diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c
index 3c263e5..a37696d 100644
--- a/drivers/usb/host/r8a66597-hcd.c
+++ b/drivers/usb/host/r8a66597-hcd.c
@@ -7,9 +7,11 @@
#include <common.h>
#include <console.h>
+#include <dm.h>
#include <usb.h>
#include <asm/io.h>
#include <linux/iopoll.h>
+#include <power/regulator.h>
#include "r8a66597.h"
@@ -19,33 +21,53 @@
#define R8A66597_DPRINT(...)
#endif
-static struct r8a66597 gr8a66597;
+static inline struct usb_device *usb_dev_get_parent(struct usb_device *udev)
+{
+ struct udevice *parent = udev->dev->parent;
+
+ /*
+ * When called from usb-uclass.c: usb_scan_device() udev->dev points
+ * to the parent udevice, not the actual udevice belonging to the
+ * udev as the device is not instantiated yet.
+ *
+ * If dev is an usb-bus, then we are called from usb_scan_device() for
+ * an usb-device plugged directly into the root port, return NULL.
+ */
+ if (device_get_uclass_id(udev->dev) == UCLASS_USB)
+ return NULL;
+
+ /*
+ * If these 2 are not the same we are being called from
+ * usb_scan_device() and udev itself is the parent.
+ */
+ if (dev_get_parent_priv(udev->dev) != udev)
+ return udev;
+
+ /* We are being called normally, use the parent pointer */
+ if (device_get_uclass_id(parent) == UCLASS_USB_HUB)
+ return dev_get_parent_priv(parent);
+
+ return NULL;
+}
static void get_hub_data(struct usb_device *dev, u16 *hub_devnum, u16 *hubport)
{
- int i;
+ struct usb_device *parent = usb_dev_get_parent(dev);
*hub_devnum = 0;
*hubport = 0;
/* check a device connected to root_hub */
- if ((dev->parent && dev->parent->devnum == 1) ||
- (dev->devnum == 1))
+ if ((parent && parent->devnum == 1) ||
+ dev->devnum == 1)
return;
- for (i = 0; i < USB_MAXCHILDREN; i++) {
- if (dev->parent->children[i] == dev) {
- *hub_devnum = (u8)dev->parent->devnum;
- *hubport = i;
- return;
- }
- }
-
- printf("get_hub_data error.\n");
+ *hub_devnum = (u8)parent->devnum;
+ *hubport = parent->portnr - 1;
}
static void set_devadd(struct r8a66597 *r8a66597, u8 r8a66597_address,
- struct usb_device *dev, int port)
+ struct usb_device *dev, int port)
{
u16 val, usbspd, upphub, hubport;
unsigned long devadd_reg = get_devadd_addr(r8a66597_address);
@@ -61,17 +83,6 @@
u16 tmp;
int i = 0;
-#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
- do {
- r8a66597_write(r8a66597, SCKE, SYSCFG0);
- tmp = r8a66597_read(r8a66597, SYSCFG0);
- if (i++ > 1000) {
- printf("register access fail.\n");
- return -1;
- }
- } while ((tmp & SCKE) != SCKE);
- r8a66597_write(r8a66597, 0x04, 0x02);
-#else
do {
r8a66597_write(r8a66597, USBE, SYSCFG0);
tmp = r8a66597_read(r8a66597, SYSCFG0);
@@ -81,57 +92,30 @@
}
} while ((tmp & USBE) != USBE);
r8a66597_bclr(r8a66597, USBE, SYSCFG0);
-#if !defined(CONFIG_RZA_USB)
- r8a66597_mdfy(r8a66597, CONFIG_R8A66597_XTAL, XTAL, SYSCFG0);
-
- i = 0;
- r8a66597_bset(r8a66597, XCKE, SYSCFG0);
- do {
- udelay(1000);
- tmp = r8a66597_read(r8a66597, SYSCFG0);
- if (i++ > 500) {
- printf("register access fail.\n");
- return -1;
- }
- } while ((tmp & SCKE) != SCKE);
-#else
/*
* RZ/A Only:
* Bits XTAL(UCKSEL) and UPLLE in SYSCFG0 for USB0 controls both USB0
* and USB1, so we must always set the USB0 register
*/
#if (CONFIG_R8A66597_XTAL == 1)
- setbits(le16, R8A66597_BASE0, XTAL);
+ r8a66597_bset(r8a66597, XTAL, SYSCFG0);
#endif
mdelay(1);
- setbits(le16, R8A66597_BASE0, UPLLE);
+ r8a66597_bset(r8a66597, UPLLE, SYSCFG0);
mdelay(1);
r8a66597_bset(r8a66597, SUSPM, SUSPMODE0);
-#endif /* CONFIG_RZA_USB */
-#endif /* #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) */
return 0;
}
static void r8a66597_clock_disable(struct r8a66597 *r8a66597)
{
-#if !defined(CONFIG_RZA_USB)
- r8a66597_bclr(r8a66597, SCKE, SYSCFG0);
- udelay(1);
-#if !defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
- r8a66597_bclr(r8a66597, PLLC, SYSCFG0);
- r8a66597_bclr(r8a66597, XCKE, SYSCFG0);
- r8a66597_bclr(r8a66597, USBE, SYSCFG0);
-#endif
-#else
r8a66597_bclr(r8a66597, SUSPM, SUSPMODE0);
- clrbits(le16, R8A66597_BASE0, UPLLE);
+ r8a66597_bclr(r8a66597, UPLLE, SYSCFG0);
mdelay(1);
r8a66597_bclr(r8a66597, USBE, SYSCFG0);
mdelay(1);
-
-#endif
}
static void r8a66597_enable_port(struct r8a66597 *r8a66597, int port)
@@ -141,10 +125,6 @@
val = port ? DRPD : DCFM | DRPD;
r8a66597_bset(r8a66597, val, get_syscfg_reg(port));
r8a66597_bset(r8a66597, HSE, get_syscfg_reg(port));
-
-#if !defined(CONFIG_RZA_USB)
- r8a66597_write(r8a66597, BURST | CPU_ADR_RD_WR, get_dmacfg_reg(port));
-#endif
}
static void r8a66597_disable_port(struct r8a66597 *r8a66597, int port)
@@ -174,9 +154,6 @@
if (ret < 0)
return ret;
-#if !defined(CONFIG_RZA_USB)
- r8a66597_bset(r8a66597, CONFIG_R8A66597_LDRV & LDRV, PINCFG);
-#endif
r8a66597_bset(r8a66597, USBE, SYSCFG0);
r8a66597_bset(r8a66597, INTL, SOFCFG);
@@ -184,9 +161,9 @@
for (port = 0; port < R8A66597_MAX_ROOT_HUB; port++)
r8a66597_write(r8a66597, 0, get_intenb_reg(port));
- r8a66597_bset(r8a66597, CONFIG_R8A66597_ENDIAN & BIGEND, CFIFOSEL);
- r8a66597_bset(r8a66597, CONFIG_R8A66597_ENDIAN & BIGEND, D0FIFOSEL);
- r8a66597_bset(r8a66597, CONFIG_R8A66597_ENDIAN & BIGEND, D1FIFOSEL);
+ r8a66597_bclr(r8a66597, BIGEND, CFIFOSEL);
+ r8a66597_bclr(r8a66597, BIGEND, D0FIFOSEL);
+ r8a66597_bclr(r8a66597, BIGEND, D1FIFOSEL);
r8a66597_bset(r8a66597, TRNENSEL, SOFCFG);
for (port = 0; port < R8A66597_MAX_ROOT_HUB; port++)
@@ -294,16 +271,13 @@
unsigned long setup_addr = USBREQ;
u16 intsts1;
int timeout = 3000;
-#if defined(CONFIG_RZA_USB)
u16 dcpctr;
-#endif
u16 devsel = setup->request == USB_REQ_SET_ADDRESS ? 0 : dev->devnum;
r8a66597_write(r8a66597, make_devsel(devsel) |
(8 << dev->maxpacketsize), DCPMAXP);
r8a66597_write(r8a66597, ~(SIGN | SACK), INTSTS1);
-#if defined(CONFIG_RZA_USB)
dcpctr = r8a66597_read(r8a66597, DCPCTR);
if ((dcpctr & PID) == PID_BUF) {
if (readw_poll_timeout(r8a66597->reg + DCPCTR, dcpctr,
@@ -312,7 +286,6 @@
return -ETIMEDOUT;
}
}
-#endif
for (i = 0; i < 4; i++) {
r8a66597_write(r8a66597, le16_to_cpu(p[i]), setup_addr);
@@ -349,7 +322,7 @@
R8A66597_DPRINT("%s\n", __func__);
r8a66597_mdfy(r8a66597, MBW | BULK_OUT_PIPENUM,
- MBW | CURPIPE, CFIFOSEL);
+ MBW | CURPIPE, CFIFOSEL);
r8a66597_reg_wait(r8a66597, CFIFOSEL, CURPIPE, BULK_OUT_PIPENUM);
tmp = r8a66597_read(r8a66597, CFIFOCTR);
if ((tmp & FRDY) == 0) {
@@ -373,7 +346,7 @@
dev->act_len += size;
r8a66597_mdfy(r8a66597, PID_BUF, PID,
- get_pipectr_addr(BULK_OUT_PIPENUM));
+ get_pipectr_addr(BULK_OUT_PIPENUM));
while (!(r8a66597_read(r8a66597, BEMPSTS) & (1 << BULK_OUT_PIPENUM)))
if (ctrlc())
@@ -382,7 +355,7 @@
if (dev->act_len >= transfer_len)
r8a66597_mdfy(r8a66597, PID_NAK, PID,
- get_pipectr_addr(BULK_OUT_PIPENUM));
+ get_pipectr_addr(BULK_OUT_PIPENUM));
return 0;
}
@@ -403,17 +376,17 @@
/* prepare */
if (dev->act_len == 0) {
r8a66597_mdfy(r8a66597, PID_NAK, PID,
- get_pipectr_addr(pipenum));
+ get_pipectr_addr(pipenum));
r8a66597_write(r8a66597, ~(1 << pipenum), BRDYSTS);
r8a66597_write(r8a66597, TRCLR, get_pipetre_addr(pipenum));
r8a66597_write(r8a66597,
- (transfer_len + maxpacket - 1) / maxpacket,
+ (transfer_len + maxpacket - 1) / maxpacket,
get_pipetrn_addr(pipenum));
r8a66597_bset(r8a66597, TRENB, get_pipetre_addr(pipenum));
r8a66597_mdfy(r8a66597, PID_BUF, PID,
- get_pipectr_addr(pipenum));
+ get_pipectr_addr(pipenum));
}
r8a66597_mdfy(r8a66597, MBW | pipenum, MBW | CURPIPE, CFIFOSEL);
@@ -490,7 +463,7 @@
}
static int send_status_packet(struct r8a66597 *r8a66597,
- unsigned long pipe)
+ unsigned long pipe)
{
r8a66597_bset(r8a66597, SQSET, DCPCTR);
r8a66597_mdfy(r8a66597, PID_NAK, PID, DCPCTR);
@@ -581,16 +554,15 @@
return -1; /* fail */
}
-/*-------------------------------------------------------------------------*
- * Virtual Root Hub
- *-------------------------------------------------------------------------*/
+/* Virtual Root Hub */
#include <usbroothubdes.h>
-static int r8a66597_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
- void *buffer, int transfer_len, struct devrequest *cmd)
+static int r8a66597_submit_rh_msg(struct udevice *udev, struct usb_device *dev,
+ unsigned long pipe, void *buffer,
+ int transfer_len, struct devrequest *cmd)
{
- struct r8a66597 *r8a66597 = &gr8a66597;
+ struct r8a66597 *r8a66597 = dev_get_priv(udev);
int leni = transfer_len;
int len = 0;
int stat = 0;
@@ -658,40 +630,40 @@
}
break;
case RH_SET_ADDRESS:
- gr8a66597.rh_devnum = wValue;
+ r8a66597->rh_devnum = wValue;
break;
case RH_GET_DESCRIPTOR:
switch ((wValue & 0xff00) >> 8) {
case (0x01): /* device descriptor */
len = min_t(unsigned int,
- leni,
+ leni,
min_t(unsigned int,
- sizeof(root_hub_dev_des),
+ sizeof(root_hub_dev_des),
wLength));
memcpy(buffer, root_hub_dev_des, len);
break;
case (0x02): /* configuration descriptor */
len = min_t(unsigned int,
- leni,
+ leni,
min_t(unsigned int,
- sizeof(root_hub_config_des),
+ sizeof(root_hub_config_des),
wLength));
memcpy(buffer, root_hub_config_des, len);
break;
case (0x03): /* string descriptors */
if (wValue == 0x0300) {
len = min_t(unsigned int,
- leni,
+ leni,
min_t(unsigned int,
- sizeof(root_hub_str_index0),
+ sizeof(root_hub_str_index0),
wLength));
memcpy(buffer, root_hub_str_index0, len);
}
if (wValue == 0x0301) {
len = min_t(unsigned int,
- leni,
+ leni,
min_t(unsigned int,
- sizeof(root_hub_str_index1),
+ sizeof(root_hub_str_index1),
wLength));
memcpy(buffer, root_hub_str_index1, len);
}
@@ -724,7 +696,8 @@
} else {
data[0] += 2;
data[8] = (temp & RH_B_DR) >> 8;
- data[10] = data[9] = 0xff;
+ data[9] = 0xff;
+ data[10] = 0xff;
}
len = min_t(unsigned int, leni,
@@ -734,7 +707,7 @@
}
case RH_GET_CONFIGURATION:
- *(__u8 *) buffer = 0x01;
+ *(__u8 *)buffer = 0x01;
len = 1;
break;
case RH_SET_CONFIGURATION:
@@ -754,50 +727,22 @@
return stat;
}
-int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len)
+static int r8a66597_submit_control_msg(struct udevice *udev,
+ struct usb_device *dev,
+ unsigned long pipe, void *buffer,
+ int length, struct devrequest *setup)
{
- struct r8a66597 *r8a66597 = &gr8a66597;
- int ret = 0;
-
- R8A66597_DPRINT("%s\n", __func__);
- R8A66597_DPRINT("pipe = %08x, buffer = %p, len = %d, devnum = %d\n",
- pipe, buffer, transfer_len, dev->devnum);
-
- set_devadd(r8a66597, dev->devnum, dev, 0);
-
- pipe_buffer_setting(r8a66597, dev, pipe);
-
- dev->act_len = 0;
- while (dev->act_len < transfer_len && ret == 0) {
- if (ctrlc())
- return -1;
-
- if (usb_pipein(pipe))
- ret = receive_bulk_packet(r8a66597, dev, pipe, buffer,
- transfer_len);
- else
- ret = send_bulk_packet(r8a66597, dev, pipe, buffer,
- transfer_len);
- }
-
- if (ret == 0)
- dev->status = 0;
-
- return ret;
-}
-
-int submit_control_msg(struct usb_device *dev, unsigned long pipe,
- void *buffer, int transfer_len, struct devrequest *setup)
-{
- struct r8a66597 *r8a66597 = &gr8a66597;
+ struct r8a66597 *r8a66597 = dev_get_priv(udev);
u16 r8a66597_address = setup->request == USB_REQ_SET_ADDRESS ?
0 : dev->devnum;
+ debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
+ udev->name, dev, dev->dev->name, dev->portnr);
+
R8A66597_DPRINT("%s\n", __func__);
if (usb_pipedevice(pipe) == r8a66597->rh_devnum)
- return r8a66597_submit_rh_msg(dev, pipe, buffer, transfer_len,
- setup);
+ return r8a66597_submit_rh_msg(udev, dev, pipe, buffer,
+ length, setup);
R8A66597_DPRINT("%s: setup\n", __func__);
set_devadd(r8a66597, r8a66597_address, dev, 0);
@@ -810,7 +755,7 @@
dev->act_len = 0;
if (usb_pipein(pipe))
if (receive_control_packet(r8a66597, dev, buffer,
- transfer_len) < 0)
+ length) < 0)
return -1;
if (send_status_packet(r8a66597, pipe) < 0)
@@ -821,40 +766,131 @@
return 0;
}
-int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len, int interval)
+static int r8a66597_submit_bulk_msg(struct udevice *udev,
+ struct usb_device *dev, unsigned long pipe,
+ void *buffer, int length)
{
- /* no implement */
+ struct r8a66597 *r8a66597 = dev_get_priv(udev);
+ int ret = 0;
+
+ debug("%s: dev='%s', udev=%p\n", __func__, udev->name, dev);
+
R8A66597_DPRINT("%s\n", __func__);
+ R8A66597_DPRINT("pipe = %08x, buffer = %p, len = %d, devnum = %d\n",
+ pipe, buffer, length, dev->devnum);
+
+ set_devadd(r8a66597, dev->devnum, dev, 0);
+
+ pipe_buffer_setting(r8a66597, dev, pipe);
+
+ dev->act_len = 0;
+ while (dev->act_len < length && ret == 0) {
+ if (ctrlc())
+ return -1;
+
+ if (usb_pipein(pipe))
+ ret = receive_bulk_packet(r8a66597, dev, pipe, buffer,
+ length);
+ else
+ ret = send_bulk_packet(r8a66597, dev, pipe, buffer,
+ length);
+ }
+
+ if (ret == 0)
+ dev->status = 0;
+
+ return ret;
+}
+
+static int r8a66597_usb_ofdata_to_platdata(struct udevice *dev)
+{
+ struct r8a66597 *priv = dev_get_priv(dev);
+ fdt_addr_t addr;
+
+ addr = dev_read_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+ priv->reg = addr;
+
return 0;
}
-int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
+static int r8a66597_usb_probe(struct udevice *dev)
{
- struct r8a66597 *r8a66597 = &gr8a66597;
+ struct r8a66597 *priv = dev_get_priv(dev);
+ struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev);
+ int ret;
- R8A66597_DPRINT("%s\n", __func__);
+ bus_priv->desc_before_addr = true;
- memset(r8a66597, 0, sizeof(*r8a66597));
- r8a66597->reg = CONFIG_R8A66597_BASE_ADDR;
+ if (CONFIG_IS_ENABLED(DM_REGULATOR)) {
+ ret = device_get_supply_regulator(dev, "vbus-supply",
+ &priv->vbus_supply);
+ if (ret) {
+ dev_err(dev,
+ "can't get VBUS supply\n");
+ return ret;
+ }
- disable_controller(r8a66597);
+ ret = regulator_set_enable(priv->vbus_supply, true);
+ if (ret) {
+ dev_err(dev,
+ "can't enable VBUS supply\n");
+ return ret;
+ }
+ }
+
+ disable_controller(priv);
mdelay(100);
- enable_controller(r8a66597);
- r8a66597_port_power(r8a66597, 0 , 1);
+ enable_controller(priv);
+ r8a66597_port_power(priv, 0, 1);
/* check usb device */
- check_usb_device_connecting(r8a66597);
+ check_usb_device_connecting(priv);
mdelay(50);
return 0;
}
-int usb_lowlevel_stop(int index)
+static int r8a66597_usb_remove(struct udevice *dev)
{
- disable_controller(&gr8a66597);
+ struct r8a66597 *priv = dev_get_priv(dev);
+ int ret;
+
+ disable_controller(priv);
+
+ if (CONFIG_IS_ENABLED(DM_REGULATOR)) {
+ ret = regulator_set_enable(priv->vbus_supply, false);
+ if (ret) {
+ dev_err(dev,
+ "can't disable VBUS supply\n");
+ return ret;
+ }
+ }
return 0;
}
+
+struct dm_usb_ops r8a66597_usb_ops = {
+ .control = r8a66597_submit_control_msg,
+ .bulk = r8a66597_submit_bulk_msg,
+};
+
+static const struct udevice_id r8a66597_usb_ids[] = {
+ { .compatible = "renesas,rza1-usbhs" },
+ { }
+};
+
+U_BOOT_DRIVER(usb_r8a66597) = {
+ .name = "r8a66597_usb",
+ .id = UCLASS_USB,
+ .of_match = r8a66597_usb_ids,
+ .ofdata_to_platdata = r8a66597_usb_ofdata_to_platdata,
+ .probe = r8a66597_usb_probe,
+ .remove = r8a66597_usb_remove,
+ .ops = &r8a66597_usb_ops,
+ .priv_auto_alloc_size = sizeof(struct r8a66597),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
diff --git a/drivers/usb/host/r8a66597.h b/drivers/usb/host/r8a66597.h
index ffdb39e..b6110d6 100644
--- a/drivers/usb/host/r8a66597.h
+++ b/drivers/usb/host/r8a66597.h
@@ -72,9 +72,9 @@
#define PIPE3TRE 0x98
#define PIPE3TRN 0x9A
#define PIPE4TRE 0x9C
-#define PIPE4TRN 0x9E
-#define PIPE5TRE 0xA0
-#define PIPE5TRN 0xA2
+#define PIPE4TRN 0x9E
+#define PIPE5TRE 0xA0
+#define PIPE5TRN 0xA2
#define DEVADD0 0xD0
#define DEVADD1 0xD2
#define DEVADD2 0xD4
@@ -89,320 +89,295 @@
#define SUSPMODE0 0x102 /* RZ/A only */
/* System Configuration Control Register */
-#if !defined(CONFIG_RZA_USB)
-#define XTAL 0xC000 /* b15-14: Crystal selection */
-#define XTAL48 0x8000 /* 48MHz */
-#define XTAL24 0x4000 /* 24MHz */
-#define XTAL12 0x0000 /* 12MHz */
-#define XCKE 0x2000 /* b13: External clock enable */
-#define PLLC 0x0800 /* b11: PLL control */
-#define SCKE 0x0400 /* b10: USB clock enable */
-#define PCSDIS 0x0200 /* b9: not CS wakeup */
-#define LPSME 0x0100 /* b8: Low power sleep mode */
-#endif
-#define HSE 0x0080 /* b7: Hi-speed enable */
-#define DCFM 0x0040 /* b6: Controller function select */
-#define DRPD 0x0020 /* b5: D+/- pull down control */
-#define DPRPU 0x0010 /* b4: D+ pull up control */
-#if defined(CONFIG_RZA_USB)
-#define XTAL 0x0004 /* b2: Crystal selection */
-#define XTAL12 0x0004 /* 12MHz */
-#define XTAL48 0x0000 /* 48MHz */
-#define UPLLE 0x0002 /* b1: internal PLL control */
-#endif
-#define USBE 0x0001 /* b0: USB module operation enable */
+#define HSE 0x0080 /* b7: Hi-speed enable */
+#define DCFM 0x0040 /* b6: Controller function select */
+#define DRPD 0x0020 /* b5: D+/- pull down control */
+#define DPRPU 0x0010 /* b4: D+ pull up control */
+#define XTAL 0x0004 /* b2: Crystal selection */
+#define XTAL12 0x0004 /* 12MHz */
+#define XTAL48 0x0000 /* 48MHz */
+#define UPLLE 0x0002 /* b1: internal PLL control */
+#define USBE 0x0001 /* b0: USB module operation enable */
/* System Configuration Status Register */
-#define OVCBIT 0x8000 /* b15-14: Over-current bit */
-#define OVCMON 0xC000 /* b15-14: Over-current monitor */
-#define SOFEA 0x0020 /* b5: SOF monitor */
-#define IDMON 0x0004 /* b3: ID-pin monitor */
-#define LNST 0x0003 /* b1-0: D+, D- line status */
-#define SE1 0x0003 /* SE1 */
-#define FS_KSTS 0x0002 /* Full-Speed K State */
-#define FS_JSTS 0x0001 /* Full-Speed J State */
-#define LS_JSTS 0x0002 /* Low-Speed J State */
-#define LS_KSTS 0x0001 /* Low-Speed K State */
-#define SE0 0x0000 /* SE0 */
+#define OVCBIT 0x8000 /* b15-14: Over-current bit */
+#define OVCMON 0xC000 /* b15-14: Over-current monitor */
+#define SOFEA 0x0020 /* b5: SOF monitor */
+#define IDMON 0x0004 /* b3: ID-pin monitor */
+#define LNST 0x0003 /* b1-0: D+, D- line status */
+#define SE1 0x0003 /* SE1 */
+#define FS_KSTS 0x0002 /* Full-Speed K State */
+#define FS_JSTS 0x0001 /* Full-Speed J State */
+#define LS_JSTS 0x0002 /* Low-Speed J State */
+#define LS_KSTS 0x0001 /* Low-Speed K State */
+#define SE0 0x0000 /* SE0 */
/* Device State Control Register */
-#define EXTLP0 0x0400 /* b10: External port */
-#define VBOUT 0x0200 /* b9: VBUS output */
-#define WKUP 0x0100 /* b8: Remote wakeup */
-#define RWUPE 0x0080 /* b7: Remote wakeup sense */
-#define USBRST 0x0040 /* b6: USB reset enable */
-#define RESUME 0x0020 /* b5: Resume enable */
-#define UACT 0x0010 /* b4: USB bus enable */
-#define RHST 0x0007 /* b1-0: Reset handshake status */
-#define HSPROC 0x0004 /* HS handshake is processing */
-#define HSMODE 0x0003 /* Hi-Speed mode */
-#define FSMODE 0x0002 /* Full-Speed mode */
-#define LSMODE 0x0001 /* Low-Speed mode */
-#define UNDECID 0x0000 /* Undecided */
+#define EXTLP0 0x0400 /* b10: External port */
+#define VBOUT 0x0200 /* b9: VBUS output */
+#define WKUP 0x0100 /* b8: Remote wakeup */
+#define RWUPE 0x0080 /* b7: Remote wakeup sense */
+#define USBRST 0x0040 /* b6: USB reset enable */
+#define RESUME 0x0020 /* b5: Resume enable */
+#define UACT 0x0010 /* b4: USB bus enable */
+#define RHST 0x0007 /* b1-0: Reset handshake status */
+#define HSPROC 0x0004 /* HS handshake is processing */
+#define HSMODE 0x0003 /* Hi-Speed mode */
+#define FSMODE 0x0002 /* Full-Speed mode */
+#define LSMODE 0x0001 /* Low-Speed mode */
+#define UNDECID 0x0000 /* Undecided */
/* Test Mode Register */
-#define UTST 0x000F /* b3-0: Test select */
-#define H_TST_PACKET 0x000C /* HOST TEST Packet */
-#define H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */
-#define H_TST_K 0x000A /* HOST TEST K */
-#define H_TST_J 0x0009 /* HOST TEST J */
-#define H_TST_NORMAL 0x0000 /* HOST Normal Mode */
-#define P_TST_PACKET 0x0004 /* PERI TEST Packet */
-#define P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */
-#define P_TST_K 0x0002 /* PERI TEST K */
-#define P_TST_J 0x0001 /* PERI TEST J */
-#define P_TST_NORMAL 0x0000 /* PERI Normal Mode */
+#define UTST 0x000F /* b3-0: Test select */
+#define H_TST_PACKET 0x000C /* HOST TEST Packet */
+#define H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */
+#define H_TST_K 0x000A /* HOST TEST K */
+#define H_TST_J 0x0009 /* HOST TEST J */
+#define H_TST_NORMAL 0x0000 /* HOST Normal Mode */
+#define P_TST_PACKET 0x0004 /* PERI TEST Packet */
+#define P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */
+#define P_TST_K 0x0002 /* PERI TEST K */
+#define P_TST_J 0x0001 /* PERI TEST J */
+#define P_TST_NORMAL 0x0000 /* PERI Normal Mode */
/* Data Pin Configuration Register */
-#define LDRV 0x8000 /* b15: Drive Current Adjust */
-#define VIF1 0x0000 /* VIF = 1.8V */
-#define VIF3 0x8000 /* VIF = 3.3V */
-#define INTA 0x0001 /* b1: USB INT-pin active */
+#define LDRV 0x8000 /* b15: Drive Current Adjust */
+#define VIF1 0x0000 /* VIF = 1.8V */
+#define VIF3 0x8000 /* VIF = 3.3V */
+#define INTA 0x0001 /* b1: USB INT-pin active */
/* DMAx Pin Configuration Register */
-#define DREQA 0x4000 /* b14: Dreq active select */
-#define BURST 0x2000 /* b13: Burst mode */
-#define DACKA 0x0400 /* b10: Dack active select */
-#define DFORM 0x0380 /* b9-7: DMA mode select */
-#define CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */
-#define CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */
-#define CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */
-#define SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */
-#define DENDA 0x0040 /* b6: Dend active select */
-#define PKTM 0x0020 /* b5: Packet mode */
-#define DENDE 0x0010 /* b4: Dend enable */
-#define OBUS 0x0004 /* b2: OUTbus mode */
+#define DREQA 0x4000 /* b14: Dreq active select */
+#define BURST 0x2000 /* b13: Burst mode */
+#define DACKA 0x0400 /* b10: Dack active select */
+#define DFORM 0x0380 /* b9-7: DMA mode select */
+#define CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */
+#define CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */
+#define CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */
+#define SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */
+#define DENDA 0x0040 /* b6: Dend active select */
+#define PKTM 0x0020 /* b5: Packet mode */
+#define DENDE 0x0010 /* b4: Dend enable */
+#define OBUS 0x0004 /* b2: OUTbus mode */
/* CFIFO/DxFIFO Port Select Register */
-#define RCNT 0x8000 /* b15: Read count mode */
-#define REW 0x4000 /* b14: Buffer rewind */
-#define DCLRM 0x2000 /* b13: DMA buffer clear mode */
-#define DREQE 0x1000 /* b12: DREQ output enable */
-#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
-#define MBW 0x0800
-#else
-#if !defined(CONFIG_RZA_USB)
-#define MBW 0x0400 /* b10: Maximum bit width for FIFO access */
-#else
-#define MBW 0x0800 /* b10: Maximum bit width for FIFO access */
-#endif
-#endif
-#define MBW_8 0x0000 /* 8bit */
-#define MBW_16 0x0400 /* 16bit */
-#define MBW_32 0x0800 /* 32bit */
-#define BIGEND 0x0100 /* b8: Big endian mode */
-#define BYTE_LITTLE 0x0000 /* little dendian */
-#define BYTE_BIG 0x0100 /* big endifan */
-#define ISEL 0x0020 /* b5: DCP FIFO port direction select */
-#define CURPIPE 0x000F /* b2-0: PIPE select */
+#define RCNT 0x8000 /* b15: Read count mode */
+#define REW 0x4000 /* b14: Buffer rewind */
+#define DCLRM 0x2000 /* b13: DMA buffer clear mode */
+#define DREQE 0x1000 /* b12: DREQ output enable */
+#define MBW 0x0800 /* b10: Maximum bit width for FIFO access */
+#define MBW_8 0x0000 /* 8bit */
+#define MBW_16 0x0400 /* 16bit */
+#define MBW_32 0x0800 /* 32bit */
+#define BIGEND 0x0100 /* b8: Big endian mode */
+#define BYTE_LITTLE 0x0000 /* little dendian */
+#define BYTE_BIG 0x0100 /* big endifan */
+#define ISEL 0x0020 /* b5: DCP FIFO port direction select */
+#define CURPIPE 0x000F /* b2-0: PIPE select */
/* CFIFO/DxFIFO Port Control Register */
-#define BVAL 0x8000 /* b15: Buffer valid flag */
-#define BCLR 0x4000 /* b14: Buffer clear */
-#define FRDY 0x2000 /* b13: FIFO ready */
-#define DTLN 0x0FFF /* b11-0: FIFO received data length */
+#define BVAL 0x8000 /* b15: Buffer valid flag */
+#define BCLR 0x4000 /* b14: Buffer clear */
+#define FRDY 0x2000 /* b13: FIFO ready */
+#define DTLN 0x0FFF /* b11-0: FIFO received data length */
/* Interrupt Enable Register 0 */
-#define VBSE 0x8000 /* b15: VBUS interrupt */
-#define RSME 0x4000 /* b14: Resume interrupt */
-#define SOFE 0x2000 /* b13: Frame update interrupt */
-#define DVSE 0x1000 /* b12: Device state transition interrupt */
-#define CTRE 0x0800 /* b11: Control transfer stage transition interrupt */
-#define BEMPE 0x0400 /* b10: Buffer empty interrupt */
-#define NRDYE 0x0200 /* b9: Buffer not ready interrupt */
-#define BRDYE 0x0100 /* b8: Buffer ready interrupt */
+#define VBSE 0x8000 /* b15: VBUS interrupt */
+#define RSME 0x4000 /* b14: Resume interrupt */
+#define SOFE 0x2000 /* b13: Frame update interrupt */
+#define DVSE 0x1000 /* b12: Device state transition interrupt */
+#define CTRE 0x0800 /* b11: Control transfer stage transition interrupt */
+#define BEMPE 0x0400 /* b10: Buffer empty interrupt */
+#define NRDYE 0x0200 /* b9: Buffer not ready interrupt */
+#define BRDYE 0x0100 /* b8: Buffer ready interrupt */
/* Interrupt Enable Register 1 */
-#define OVRCRE 0x8000 /* b15: Over-current interrupt */
-#define BCHGE 0x4000 /* b14: USB us chenge interrupt */
-#define DTCHE 0x1000 /* b12: Detach sense interrupt */
-#define ATTCHE 0x0800 /* b11: Attach sense interrupt */
-#define EOFERRE 0x0040 /* b6: EOF error interrupt */
-#define SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */
-#define SACKE 0x0010 /* b4: SETUP ACK interrupt */
+#define OVRCRE 0x8000 /* b15: Over-current interrupt */
+#define BCHGE 0x4000 /* b14: USB us chenge interrupt */
+#define DTCHE 0x1000 /* b12: Detach sense interrupt */
+#define ATTCHE 0x0800 /* b11: Attach sense interrupt */
+#define EOFERRE 0x0040 /* b6: EOF error interrupt */
+#define SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */
+#define SACKE 0x0010 /* b4: SETUP ACK interrupt */
/* BRDY Interrupt Enable/Status Register */
-#define BRDY9 0x0200 /* b9: PIPE9 */
-#define BRDY8 0x0100 /* b8: PIPE8 */
-#define BRDY7 0x0080 /* b7: PIPE7 */
-#define BRDY6 0x0040 /* b6: PIPE6 */
-#define BRDY5 0x0020 /* b5: PIPE5 */
-#define BRDY4 0x0010 /* b4: PIPE4 */
-#define BRDY3 0x0008 /* b3: PIPE3 */
-#define BRDY2 0x0004 /* b2: PIPE2 */
-#define BRDY1 0x0002 /* b1: PIPE1 */
-#define BRDY0 0x0001 /* b1: PIPE0 */
+#define BRDY9 0x0200 /* b9: PIPE9 */
+#define BRDY8 0x0100 /* b8: PIPE8 */
+#define BRDY7 0x0080 /* b7: PIPE7 */
+#define BRDY6 0x0040 /* b6: PIPE6 */
+#define BRDY5 0x0020 /* b5: PIPE5 */
+#define BRDY4 0x0010 /* b4: PIPE4 */
+#define BRDY3 0x0008 /* b3: PIPE3 */
+#define BRDY2 0x0004 /* b2: PIPE2 */
+#define BRDY1 0x0002 /* b1: PIPE1 */
+#define BRDY0 0x0001 /* b1: PIPE0 */
/* NRDY Interrupt Enable/Status Register */
-#define NRDY9 0x0200 /* b9: PIPE9 */
-#define NRDY8 0x0100 /* b8: PIPE8 */
-#define NRDY7 0x0080 /* b7: PIPE7 */
-#define NRDY6 0x0040 /* b6: PIPE6 */
-#define NRDY5 0x0020 /* b5: PIPE5 */
-#define NRDY4 0x0010 /* b4: PIPE4 */
-#define NRDY3 0x0008 /* b3: PIPE3 */
-#define NRDY2 0x0004 /* b2: PIPE2 */
-#define NRDY1 0x0002 /* b1: PIPE1 */
-#define NRDY0 0x0001 /* b1: PIPE0 */
+#define NRDY9 0x0200 /* b9: PIPE9 */
+#define NRDY8 0x0100 /* b8: PIPE8 */
+#define NRDY7 0x0080 /* b7: PIPE7 */
+#define NRDY6 0x0040 /* b6: PIPE6 */
+#define NRDY5 0x0020 /* b5: PIPE5 */
+#define NRDY4 0x0010 /* b4: PIPE4 */
+#define NRDY3 0x0008 /* b3: PIPE3 */
+#define NRDY2 0x0004 /* b2: PIPE2 */
+#define NRDY1 0x0002 /* b1: PIPE1 */
+#define NRDY0 0x0001 /* b1: PIPE0 */
/* BEMP Interrupt Enable/Status Register */
-#define BEMP9 0x0200 /* b9: PIPE9 */
-#define BEMP8 0x0100 /* b8: PIPE8 */
-#define BEMP7 0x0080 /* b7: PIPE7 */
-#define BEMP6 0x0040 /* b6: PIPE6 */
-#define BEMP5 0x0020 /* b5: PIPE5 */
-#define BEMP4 0x0010 /* b4: PIPE4 */
-#define BEMP3 0x0008 /* b3: PIPE3 */
-#define BEMP2 0x0004 /* b2: PIPE2 */
-#define BEMP1 0x0002 /* b1: PIPE1 */
-#define BEMP0 0x0001 /* b0: PIPE0 */
+#define BEMP9 0x0200 /* b9: PIPE9 */
+#define BEMP8 0x0100 /* b8: PIPE8 */
+#define BEMP7 0x0080 /* b7: PIPE7 */
+#define BEMP6 0x0040 /* b6: PIPE6 */
+#define BEMP5 0x0020 /* b5: PIPE5 */
+#define BEMP4 0x0010 /* b4: PIPE4 */
+#define BEMP3 0x0008 /* b3: PIPE3 */
+#define BEMP2 0x0004 /* b2: PIPE2 */
+#define BEMP1 0x0002 /* b1: PIPE1 */
+#define BEMP0 0x0001 /* b0: PIPE0 */
/* SOF Pin Configuration Register */
-#define TRNENSEL 0x0100 /* b8: Select transaction enable period */
-#define BRDYM 0x0040 /* b6: BRDY clear timing */
-#define INTL 0x0020 /* b5: Interrupt sense select */
-#define EDGESTS 0x0010 /* b4: */
-#define SOFMODE 0x000C /* b3-2: SOF pin select */
-#define SOF_125US 0x0008 /* SOF OUT 125us Frame Signal */
-#define SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */
-#define SOF_DISABLE 0x0000 /* SOF OUT Disable */
+#define TRNENSEL 0x0100 /* b8: Select transaction enable period */
+#define BRDYM 0x0040 /* b6: BRDY clear timing */
+#define INTL 0x0020 /* b5: Interrupt sense select */
+#define EDGESTS 0x0010 /* b4: */
+#define SOFMODE 0x000C /* b3-2: SOF pin select */
+#define SOF_125US 0x0008 /* SOF OUT 125us Frame Signal */
+#define SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */
+#define SOF_DISABLE 0x0000 /* SOF OUT Disable */
/* Interrupt Status Register 0 */
-#define VBINT 0x8000 /* b15: VBUS interrupt */
-#define RESM 0x4000 /* b14: Resume interrupt */
-#define SOFR 0x2000 /* b13: SOF frame update interrupt */
-#define DVST 0x1000 /* b12: Device state transition interrupt */
-#define CTRT 0x0800 /* b11: Control transfer stage transition interrupt */
-#define BEMP 0x0400 /* b10: Buffer empty interrupt */
-#define NRDY 0x0200 /* b9: Buffer not ready interrupt */
-#define BRDY 0x0100 /* b8: Buffer ready interrupt */
-#define VBSTS 0x0080 /* b7: VBUS input port */
-#define DVSQ 0x0070 /* b6-4: Device state */
-#define DS_SPD_CNFG 0x0070 /* Suspend Configured */
-#define DS_SPD_ADDR 0x0060 /* Suspend Address */
-#define DS_SPD_DFLT 0x0050 /* Suspend Default */
-#define DS_SPD_POWR 0x0040 /* Suspend Powered */
-#define DS_SUSP 0x0040 /* Suspend */
-#define DS_CNFG 0x0030 /* Configured */
-#define DS_ADDS 0x0020 /* Address */
-#define DS_DFLT 0x0010 /* Default */
-#define DS_POWR 0x0000 /* Powered */
-#define DVSQS 0x0030 /* b5-4: Device state */
-#define VALID 0x0008 /* b3: Setup packet detected flag */
-#define CTSQ 0x0007 /* b2-0: Control transfer stage */
-#define CS_SQER 0x0006 /* Sequence error */
-#define CS_WRND 0x0005 /* Control write nodata status stage */
-#define CS_WRSS 0x0004 /* Control write status stage */
-#define CS_WRDS 0x0003 /* Control write data stage */
-#define CS_RDSS 0x0002 /* Control read status stage */
-#define CS_RDDS 0x0001 /* Control read data stage */
-#define CS_IDST 0x0000 /* Idle or setup stage */
+#define VBINT 0x8000 /* b15: VBUS interrupt */
+#define RESM 0x4000 /* b14: Resume interrupt */
+#define SOFR 0x2000 /* b13: SOF frame update interrupt */
+#define DVST 0x1000 /* b12: Device state transition interrupt */
+#define CTRT 0x0800 /* b11: Control transfer stage transition interrupt */
+#define BEMP 0x0400 /* b10: Buffer empty interrupt */
+#define NRDY 0x0200 /* b9: Buffer not ready interrupt */
+#define BRDY 0x0100 /* b8: Buffer ready interrupt */
+#define VBSTS 0x0080 /* b7: VBUS input port */
+#define DVSQ 0x0070 /* b6-4: Device state */
+#define DS_SPD_CNFG 0x0070 /* Suspend Configured */
+#define DS_SPD_ADDR 0x0060 /* Suspend Address */
+#define DS_SPD_DFLT 0x0050 /* Suspend Default */
+#define DS_SPD_POWR 0x0040 /* Suspend Powered */
+#define DS_SUSP 0x0040 /* Suspend */
+#define DS_CNFG 0x0030 /* Configured */
+#define DS_ADDS 0x0020 /* Address */
+#define DS_DFLT 0x0010 /* Default */
+#define DS_POWR 0x0000 /* Powered */
+#define DVSQS 0x0030 /* b5-4: Device state */
+#define VALID 0x0008 /* b3: Setup packet detected flag */
+#define CTSQ 0x0007 /* b2-0: Control transfer stage */
+#define CS_SQER 0x0006 /* Sequence error */
+#define CS_WRND 0x0005 /* Control write nodata status stage */
+#define CS_WRSS 0x0004 /* Control write status stage */
+#define CS_WRDS 0x0003 /* Control write data stage */
+#define CS_RDSS 0x0002 /* Control read status stage */
+#define CS_RDDS 0x0001 /* Control read data stage */
+#define CS_IDST 0x0000 /* Idle or setup stage */
/* Interrupt Status Register 1 */
-#define OVRCR 0x8000 /* b15: Over-current interrupt */
-#define BCHG 0x4000 /* b14: USB bus chenge interrupt */
-#define DTCH 0x1000 /* b12: Detach sense interrupt */
-#define ATTCH 0x0800 /* b11: Attach sense interrupt */
-#define EOFERR 0x0040 /* b6: EOF-error interrupt */
-#define SIGN 0x0020 /* b5: Setup ignore interrupt */
-#define SACK 0x0010 /* b4: Setup acknowledge interrupt */
+#define OVRCR 0x8000 /* b15: Over-current interrupt */
+#define BCHG 0x4000 /* b14: USB bus chenge interrupt */
+#define DTCH 0x1000 /* b12: Detach sense interrupt */
+#define ATTCH 0x0800 /* b11: Attach sense interrupt */
+#define EOFERR 0x0040 /* b6: EOF-error interrupt */
+#define SIGN 0x0020 /* b5: Setup ignore interrupt */
+#define SACK 0x0010 /* b4: Setup acknowledge interrupt */
/* Frame Number Register */
-#define OVRN 0x8000 /* b15: Overrun error */
-#define CRCE 0x4000 /* b14: Received data error */
-#define FRNM 0x07FF /* b10-0: Frame number */
+#define OVRN 0x8000 /* b15: Overrun error */
+#define CRCE 0x4000 /* b14: Received data error */
+#define FRNM 0x07FF /* b10-0: Frame number */
/* Micro Frame Number Register */
-#define UFRNM 0x0007 /* b2-0: Micro frame number */
+#define UFRNM 0x0007 /* b2-0: Micro frame number */
/* Default Control Pipe Maxpacket Size Register */
/* Pipe Maxpacket Size Register */
-#define DEVSEL 0xF000 /* b15-14: Device address select */
-#define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */
+#define DEVSEL 0xF000 /* b15-14: Device address select */
+#define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */
/* Default Control Pipe Control Register */
-#define BSTS 0x8000 /* b15: Buffer status */
-#define SUREQ 0x4000 /* b14: Send USB request */
-#define CSCLR 0x2000 /* b13: complete-split status clear */
-#define CSSTS 0x1000 /* b12: complete-split status */
-#define SUREQCLR 0x0800 /* b11: stop setup request */
-#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
-#define SQSET 0x0080 /* b7: Sequence toggle bit set */
-#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
-#define PBUSY 0x0020 /* b5: pipe busy */
-#define PINGE 0x0010 /* b4: ping enable */
-#define CCPL 0x0004 /* b2: Enable control transfer complete */
-#define PID 0x0003 /* b1-0: Response PID */
-#define PID_STALL11 0x0003 /* STALL */
-#define PID_STALL 0x0002 /* STALL */
-#define PID_BUF 0x0001 /* BUF */
-#define PID_NAK 0x0000 /* NAK */
+#define BSTS 0x8000 /* b15: Buffer status */
+#define SUREQ 0x4000 /* b14: Send USB request */
+#define CSCLR 0x2000 /* b13: complete-split status clear */
+#define CSSTS 0x1000 /* b12: complete-split status */
+#define SUREQCLR 0x0800 /* b11: stop setup request */
+#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
+#define SQSET 0x0080 /* b7: Sequence toggle bit set */
+#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
+#define PBUSY 0x0020 /* b5: pipe busy */
+#define PINGE 0x0010 /* b4: ping enable */
+#define CCPL 0x0004 /* b2: Enable control transfer complete */
+#define PID 0x0003 /* b1-0: Response PID */
+#define PID_STALL11 0x0003 /* STALL */
+#define PID_STALL 0x0002 /* STALL */
+#define PID_BUF 0x0001 /* BUF */
+#define PID_NAK 0x0000 /* NAK */
/* Pipe Window Select Register */
-#define PIPENM 0x0007 /* b2-0: Pipe select */
+#define PIPENM 0x0007 /* b2-0: Pipe select */
/* Pipe Configuration Register */
-#define R8A66597_TYP 0xC000 /* b15-14: Transfer type */
-#define R8A66597_ISO 0xC000 /* Isochronous */
-#define R8A66597_INT 0x8000 /* Interrupt */
-#define R8A66597_BULK 0x4000 /* Bulk */
-#define R8A66597_BFRE 0x0400 /* b10: Buffer ready interrupt mode select */
-#define R8A66597_DBLB 0x0200 /* b9: Double buffer mode select */
-#define R8A66597_CNTMD 0x0100 /* b8: Continuous transfer mode select */
-#define R8A66597_SHTNAK 0x0080 /* b7: Transfer end NAK */
-#define R8A66597_DIR 0x0010 /* b4: Transfer direction select */
-#define R8A66597_EPNUM 0x000F /* b3-0: Eendpoint number select */
+#define R8A66597_TYP 0xC000 /* b15-14: Transfer type */
+#define R8A66597_ISO 0xC000 /* Isochronous */
+#define R8A66597_INT 0x8000 /* Interrupt */
+#define R8A66597_BULK 0x4000 /* Bulk */
+#define R8A66597_BFRE 0x0400 /* b10: Buffer ready interrupt mode select */
+#define R8A66597_DBLB 0x0200 /* b9: Double buffer mode select */
+#define R8A66597_CNTMD 0x0100 /* b8: Continuous transfer mode select */
+#define R8A66597_SHTNAK 0x0080 /* b7: Transfer end NAK */
+#define R8A66597_DIR 0x0010 /* b4: Transfer direction select */
+#define R8A66597_EPNUM 0x000F /* b3-0: Eendpoint number select */
/* Pipe Buffer Configuration Register */
-#define BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */
-#define BUFNMB 0x007F /* b6-0: Pipe buffer number */
-#define PIPE0BUF 256
-#define PIPExBUF 64
+#define BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */
+#define BUFNMB 0x007F /* b6-0: Pipe buffer number */
+#define PIPE0BUF 256
+#define PIPExBUF 64
/* Pipe Maxpacket Size Register */
-#define MXPS 0x07FF /* b10-0: Maxpacket size */
+#define MXPS 0x07FF /* b10-0: Maxpacket size */
/* Pipe Cycle Configuration Register */
-#define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */
-#define IITV 0x0007 /* b2-0: Isochronous interval */
+#define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */
+#define IITV 0x0007 /* b2-0: Isochronous interval */
/* Pipex Control Register */
-#define BSTS 0x8000 /* b15: Buffer status */
-#define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */
-#define CSCLR 0x2000 /* b13: complete-split status clear */
-#define CSSTS 0x1000 /* b12: complete-split status */
-#define ATREPM 0x0400 /* b10: Auto repeat mode */
-#define ACLRM 0x0200 /* b9: Out buffer auto clear mode */
-#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
-#define SQSET 0x0080 /* b7: Sequence toggle bit set */
-#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
-#define PBUSY 0x0020 /* b5: pipe busy */
-#define PID 0x0003 /* b1-0: Response PID */
+#define BSTS 0x8000 /* b15: Buffer status */
+#define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */
+#define CSCLR 0x2000 /* b13: complete-split status clear */
+#define CSSTS 0x1000 /* b12: complete-split status */
+#define ATREPM 0x0400 /* b10: Auto repeat mode */
+#define ACLRM 0x0200 /* b9: Out buffer auto clear mode */
+#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
+#define SQSET 0x0080 /* b7: Sequence toggle bit set */
+#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
+#define PBUSY 0x0020 /* b5: pipe busy */
+#define PID 0x0003 /* b1-0: Response PID */
/* PIPExTRE */
-#define TRENB 0x0200 /* b9: Transaction counter enable */
-#define TRCLR 0x0100 /* b8: Transaction counter clear */
+#define TRENB 0x0200 /* b9: Transaction counter enable */
+#define TRCLR 0x0100 /* b8: Transaction counter clear */
/* PIPExTRN */
-#define TRNCNT 0xFFFF /* b15-0: Transaction counter */
+#define TRNCNT 0xFFFF /* b15-0: Transaction counter */
/* DEVADDx */
-#define UPPHUB 0x7800
-#define HUBPORT 0x0700
-#define USBSPD 0x00C0
-#define RTPORT 0x0001
+#define UPPHUB 0x7800
+#define HUBPORT 0x0700
+#define USBSPD 0x00C0
+#define RTPORT 0x0001
/* Suspend Mode Register */
-#define SUSPM 0x4000 /* b14: Suspend */
+#define SUSPM 0x4000 /* b14: Suspend */
#define R8A66597_MAX_NUM_PIPE 10
#define R8A66597_BUF_BSIZE 8
#define R8A66597_MAX_DEVICE 10
-#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
-#define R8A66597_MAX_ROOT_HUB 1
-#else
#define R8A66597_MAX_ROOT_HUB 2
-#endif
#define R8A66597_MAX_SAMPLING 5
#define R8A66597_RH_POLL_TIME 10
@@ -412,9 +387,7 @@
#define BULK_OUT_PIPENUM 4
#define BULK_OUT_BUFNUM 40
-#define check_bulk_or_isoc(pipenum) ((pipenum >= 1 && pipenum <= 5))
-#define check_interrupt(pipenum) ((pipenum >= 6 && pipenum <= 9))
-#define make_devsel(addr) (addr << 12)
+#define make_devsel(addr) ((addr) << 12)
struct r8a66597 {
unsigned long reg;
@@ -423,11 +396,12 @@
unsigned short port_change;
u16 speed; /* HSMODE or FSMODE or LSMODE */
unsigned char rh_devnum;
+ struct udevice *vbus_supply;
};
static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
{
- return inw(r8a66597->reg + offset);
+ return readw(r8a66597->reg + offset);
}
static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
@@ -435,32 +409,25 @@
int len)
{
int i;
-#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) || defined(CONFIG_RZA_USB)
unsigned long fifoaddr = r8a66597->reg + offset;
unsigned long count;
unsigned long *p = buf;
count = len / 4;
for (i = 0; i < count; i++)
- p[i] = inl(r8a66597->reg + offset);
+ p[i] = readl(r8a66597->reg + offset);
if (len & 0x00000003) {
- unsigned long tmp = inl(fifoaddr);
+ unsigned long tmp = readl(fifoaddr);
+
memcpy((unsigned char *)buf + count * 4, &tmp, len & 0x03);
}
-#else
- unsigned short *p = buf;
-
- len = (len + 1) / 2;
- for (i = 0; i < len; i++)
- p[i] = inw(r8a66597->reg + offset);
-#endif
}
static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
unsigned long offset)
{
- outw(val, r8a66597->reg + offset);
+ writew(val, r8a66597->reg + offset);
}
static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
@@ -469,43 +436,30 @@
{
int i;
unsigned long fifoaddr = r8a66597->reg + offset;
-#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) || defined(CONFIG_RZA_USB)
unsigned long count;
unsigned char *pb;
unsigned long *p = buf;
count = len / 4;
for (i = 0; i < count; i++)
- outl(p[i], fifoaddr);
+ writel(p[i], fifoaddr);
if (len & 0x00000003) {
pb = (unsigned char *)buf + count * 4;
for (i = 0; i < (len & 0x00000003); i++) {
if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)
- outb(pb[i], fifoaddr + i);
+ writeb(pb[i], fifoaddr + i);
else
- outb(pb[i], fifoaddr + 3 - i);
+ writeb(pb[i], fifoaddr + 3 - i);
}
}
-#else
- int odd = len & 0x0001;
- unsigned short *p = buf;
-
- len = len / 2;
- for (i = 0; i < len; i++)
- outw(p[i], fifoaddr);
-
- if (odd) {
- unsigned char *pb = (unsigned char *)(buf + len);
- outb(*pb, fifoaddr);
- }
-#endif
}
static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
u16 val, u16 pat, unsigned long offset)
{
u16 tmp;
+
tmp = r8a66597_read(r8a66597, offset);
tmp = tmp & (~pat);
tmp = tmp | val;
@@ -570,7 +524,6 @@
#define get_pipetrn_addr(pipenum) (PIPE1TRN + (pipenum - 1) * 4)
#define get_devadd_addr(address) (DEVADD0 + address * 2)
-
/* USB HUB CONSTANTS (not OHCI-specific; see hub.h, based on usb_ohci.h) */
/* destination of request */
@@ -653,11 +606,11 @@
/* roothub.a masks */
#define RH_A_NDP (0xff << 0) /* number of downstream ports */
-#define RH_A_PSM (1 << 8) /* power switching mode */
-#define RH_A_NPS (1 << 9) /* no power switching */
-#define RH_A_DT (1 << 10) /* device type (mbz) */
-#define RH_A_OCPM (1 << 11) /* over current protection mode */
-#define RH_A_NOCP (1 << 12) /* no over current protection */
+#define RH_A_PSM BIT(8) /* power switching mode */
+#define RH_A_NPS BIT(9) /* no power switching */
+#define RH_A_DT BIT(10) /* device type (mbz) */
+#define RH_A_OCPM BIT(11) /* over current protection mode */
+#define RH_A_NOCP BIT(12) /* no over current protection */
#define RH_A_POTPGT (0xff << 24) /* power on to power good time */
#endif /* __R8A66597_H__ */
diff --git a/drivers/usb/host/sl811-hcd.c b/drivers/usb/host/sl811-hcd.c
index daba0dc..e08da61 100644
--- a/drivers/usb/host/sl811-hcd.c
+++ b/drivers/usb/host/sl811-hcd.c
@@ -384,7 +384,7 @@
}
int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int len, int interval)
+ int len, int interval, bool nonblock)
{
PDEBUG(0, "dev = %p pipe = %#lx buf = %p size = %d int = %d\n", dev, pipe,
buffer, len, interval);
diff --git a/drivers/usb/host/usb-sandbox.c b/drivers/usb/host/usb-sandbox.c
index ff9d5b7..28ee4b0 100644
--- a/drivers/usb/host/usb-sandbox.c
+++ b/drivers/usb/host/usb-sandbox.c
@@ -99,7 +99,7 @@
static int sandbox_submit_int(struct udevice *bus, struct usb_device *udev,
unsigned long pipe, void *buffer, int length,
- int interval)
+ int interval, bool nonblock)
{
struct udevice *emul;
int ret;
@@ -110,7 +110,8 @@
usbmon_trace(bus, pipe, NULL, emul);
if (ret)
return ret;
- ret = usb_emul_int(emul, udev, pipe, buffer, length, interval);
+ ret = usb_emul_int(emul, udev, pipe, buffer, length, interval,
+ nonblock);
return ret;
}
diff --git a/drivers/usb/host/usb-uclass.c b/drivers/usb/host/usb-uclass.c
index 6e118b5..8521651 100644
--- a/drivers/usb/host/usb-uclass.c
+++ b/drivers/usb/host/usb-uclass.c
@@ -31,7 +31,7 @@
}
int submit_int_msg(struct usb_device *udev, unsigned long pipe, void *buffer,
- int length, int interval)
+ int length, int interval, bool nonblock)
{
struct udevice *bus = udev->controller_dev;
struct dm_usb_ops *ops = usb_get_ops(bus);
@@ -39,7 +39,8 @@
if (!ops->interrupt)
return -ENOSYS;
- return ops->interrupt(bus, udev, pipe, buffer, length, interval);
+ return ops->interrupt(bus, udev, pipe, buffer, length, interval,
+ nonblock);
}
int submit_control_msg(struct usb_device *udev, unsigned long pipe,
diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c
index 83b9f11..55a1b22 100644
--- a/drivers/usb/host/xhci-dwc3.c
+++ b/drivers/usb/host/xhci-dwc3.c
@@ -118,6 +118,8 @@
struct dwc3 *dwc3_reg;
enum usb_dr_mode dr_mode;
struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
+ const char *phy;
+ u32 reg;
int ret;
hccr = (struct xhci_hccr *)((uintptr_t)dev_read_addr(dev));
@@ -132,6 +134,27 @@
dwc3_core_init(dwc3_reg);
+ /* Set dwc3 usb2 phy config */
+ reg = readl(&dwc3_reg->g_usb2phycfg[0]);
+
+ phy = dev_read_string(dev, "phy_type");
+ if (phy && strcmp(phy, "utmi_wide") == 0) {
+ reg |= DWC3_GUSB2PHYCFG_PHYIF;
+ reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
+ reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;
+ }
+
+ if (dev_read_bool(dev, "snps,dis_enblslpm-quirk"))
+ reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
+
+ if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk"))
+ reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
+
+ if (dev_read_bool(dev, "snps,dis_u2_susphy_quirk"))
+ reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
+
+ writel(reg, &dwc3_reg->g_usb2phycfg[0]);
+
dr_mode = usb_get_dr_mode(dev_of_offset(dev));
if (dr_mode == USB_DR_MODE_UNKNOWN)
/* by default set dual role mode to HOST */
diff --git a/drivers/usb/host/xhci-rockchip.c b/drivers/usb/host/xhci-rockchip.c
index f19bea3..e7b0dbc 100644
--- a/drivers/usb/host/xhci-rockchip.c
+++ b/drivers/usb/host/xhci-rockchip.c
@@ -167,7 +167,6 @@
}
static const struct udevice_id xhci_usb_ids[] = {
- { .compatible = "rockchip,rk3399-xhci" },
{ .compatible = "rockchip,rk3328-xhci" },
{ }
};
@@ -187,7 +186,6 @@
};
static const struct udevice_id usb_phy_ids[] = {
- { .compatible = "rockchip,rk3399-usb3-phy" },
{ .compatible = "rockchip,rk3328-usb3-phy" },
{ }
};
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index 44c5f2d..b3e4dcd 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -1109,7 +1109,8 @@
* @return 0
*/
static int _xhci_submit_int_msg(struct usb_device *udev, unsigned long pipe,
- void *buffer, int length, int interval)
+ void *buffer, int length, int interval,
+ bool nonblock)
{
if (usb_pipetype(pipe) != PIPE_INTERRUPT) {
printf("non-interrupt pipe (type=%lu)", usb_pipetype(pipe));
@@ -1277,9 +1278,10 @@
}
int submit_int_msg(struct usb_device *udev, unsigned long pipe, void *buffer,
- int length, int interval)
+ int length, int interval, bool nonblock)
{
- return _xhci_submit_int_msg(udev, pipe, buffer, length, interval);
+ return _xhci_submit_int_msg(udev, pipe, buffer, length, interval,
+ nonblock);
}
/**
@@ -1386,10 +1388,11 @@
static int xhci_submit_int_msg(struct udevice *dev, struct usb_device *udev,
unsigned long pipe, void *buffer, int length,
- int interval)
+ int interval, bool nonblock)
{
debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
- return _xhci_submit_int_msg(udev, pipe, buffer, length, interval);
+ return _xhci_submit_int_msg(udev, pipe, buffer, length, interval,
+ nonblock);
}
static int xhci_alloc_device(struct udevice *dev, struct usb_device *udev)
diff --git a/drivers/usb/musb-new/Kconfig b/drivers/usb/musb-new/Kconfig
index 75005cc..79ad14e 100644
--- a/drivers/usb/musb-new/Kconfig
+++ b/drivers/usb/musb-new/Kconfig
@@ -18,6 +18,14 @@
help
Enables the MUSB USB dual-role controller in gadget mode.
+config USB_MUSB_DA8XX
+ bool "Enable DA8xx MUSB Controller"
+ depends on DM_USB
+ help
+ Say y here to enable support for the dual role high
+ speed USB controller based on the Mentor Graphics
+ silicon IP.
+
config USB_MUSB_TI
bool "Enable TI OTG USB controller"
depends on DM_USB
diff --git a/drivers/usb/musb-new/Makefile b/drivers/usb/musb-new/Makefile
index 4eca0e5..ec7852c 100644
--- a/drivers/usb/musb-new/Makefile
+++ b/drivers/usb/musb-new/Makefile
@@ -6,6 +6,7 @@
obj-$(CONFIG_USB_MUSB_GADGET) += musb_uboot.o
obj-$(CONFIG_USB_MUSB_HOST) += musb_host.o musb_core.o musb_uboot.o
obj-$(CONFIG_USB_MUSB_DSPS) += musb_dsps.o
+obj-$(CONFIG_USB_MUSB_DA8XX) += da8xx.o
obj-$(CONFIG_USB_MUSB_AM35X) += am35x.o
obj-$(CONFIG_USB_MUSB_OMAP2PLUS) += omap2430.o
obj-$(CONFIG_USB_MUSB_PIC32) += pic32.o
diff --git a/drivers/usb/musb-new/da8xx.c b/drivers/usb/musb-new/da8xx.c
new file mode 100644
index 0000000..899b30d
--- /dev/null
+++ b/drivers/usb/musb-new/da8xx.c
@@ -0,0 +1,350 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Texas Instruments da8xx "glue layer"
+ *
+ * Copyright (c) 2019, by Texas Instruments
+ *
+ * Based on the DA8xx "glue layer" code.
+ * Copyright (c) 2008-2019, MontaVista Software, Inc. <source@mvista.com>
+ *
+ * DT support
+ * Copyright (c) 2016 Petr Kulhavy <petr@barix.com>
+ * This file is part of the Inventra Controller Driver for Linux.
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/da8xx-usb.h>
+#include <linux/usb/otg.h>
+#include <asm/omap_musb.h>
+#include <generic-phy.h>
+#include "linux-compat.h"
+#include "musb_core.h"
+#include "musb_uboot.h"
+
+/* USB 2.0 OTG module registers */
+#define DA8XX_USB_REVISION_REG 0x00
+#define DA8XX_USB_CTRL_REG 0x04
+#define DA8XX_USB_STAT_REG 0x08
+#define DA8XX_USB_EMULATION_REG 0x0c
+#define DA8XX_USB_SRP_FIX_TIME_REG 0x18
+#define DA8XX_USB_INTR_SRC_REG 0x20
+#define DA8XX_USB_INTR_SRC_SET_REG 0x24
+#define DA8XX_USB_INTR_SRC_CLEAR_REG 0x28
+#define DA8XX_USB_INTR_MASK_REG 0x2c
+#define DA8XX_USB_INTR_MASK_SET_REG 0x30
+#define DA8XX_USB_INTR_MASK_CLEAR_REG 0x34
+#define DA8XX_USB_INTR_SRC_MASKED_REG 0x38
+#define DA8XX_USB_END_OF_INTR_REG 0x3c
+#define DA8XX_USB_GENERIC_RNDIS_EP_SIZE_REG(n) (0x50 + (((n) - 1) << 2))
+
+/* Control register bits */
+#define DA8XX_SOFT_RESET_MASK 1
+
+#define DA8XX_USB_TX_EP_MASK 0x1f /* EP0 + 4 Tx EPs */
+#define DA8XX_USB_RX_EP_MASK 0x1e /* 4 Rx EPs */
+
+/* USB interrupt register bits */
+#define DA8XX_INTR_USB_SHIFT 16
+#define DA8XX_INTR_USB_MASK (0x1ff << DA8XX_INTR_USB_SHIFT) /* 8 Mentor */
+ /* interrupts and DRVVBUS interrupt */
+#define DA8XX_INTR_DRVVBUS 0x100
+#define DA8XX_INTR_RX_SHIFT 8
+#define DA8XX_INTR_RX_MASK (DA8XX_USB_RX_EP_MASK << DA8XX_INTR_RX_SHIFT)
+#define DA8XX_INTR_TX_SHIFT 0
+#define DA8XX_INTR_TX_MASK (DA8XX_USB_TX_EP_MASK << DA8XX_INTR_TX_SHIFT)
+
+#define DA8XX_MENTOR_CORE_OFFSET 0x400
+
+static irqreturn_t da8xx_musb_interrupt(int irq, void *hci)
+{
+ struct musb *musb = hci;
+ void __iomem *reg_base = musb->ctrl_base;
+ unsigned long flags;
+ irqreturn_t ret = IRQ_NONE;
+ u32 status;
+
+ spin_lock_irqsave(&musb->lock, flags);
+
+ /*
+ * NOTE: DA8XX shadows the Mentor IRQs. Don't manage them through
+ * the Mentor registers (except for setup), use the TI ones and EOI.
+ */
+
+ /* Acknowledge and handle non-CPPI interrupts */
+ status = musb_readl(reg_base, DA8XX_USB_INTR_SRC_MASKED_REG);
+ if (!status)
+ goto eoi;
+
+ musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status);
+ dev_dbg(musb->controller, "USB IRQ %08x\n", status);
+
+ musb->int_rx = (status & DA8XX_INTR_RX_MASK) >> DA8XX_INTR_RX_SHIFT;
+ musb->int_tx = (status & DA8XX_INTR_TX_MASK) >> DA8XX_INTR_TX_SHIFT;
+ musb->int_usb = (status & DA8XX_INTR_USB_MASK) >> DA8XX_INTR_USB_SHIFT;
+
+ /*
+ * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
+ * DA8xx's missing ID change IRQ. We need an ID change IRQ to
+ * switch appropriately between halves of the OTG state machine.
+ * Managing DEVCTL.Session per Mentor docs requires that we know its
+ * value but DEVCTL.BDevice is invalid without DEVCTL.Session set.
+ * Also, DRVVBUS pulses for SRP (but not at 5 V)...
+ */
+ if (status & (DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT)) {
+ int drvvbus = musb_readl(reg_base, DA8XX_USB_STAT_REG);
+ void __iomem *mregs = musb->mregs;
+ u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
+ int err;
+
+ err = musb->int_usb & MUSB_INTR_VBUSERROR;
+ if (err) {
+ /*
+ * The Mentor core doesn't debounce VBUS as needed
+ * to cope with device connect current spikes. This
+ * means it's not uncommon for bus-powered devices
+ * to get VBUS errors during enumeration.
+ *
+ * This is a workaround, but newer RTL from Mentor
+ * seems to allow a better one: "re"-starting sessions
+ * without waiting for VBUS to stop registering in
+ * devctl.
+ */
+ musb->int_usb &= ~MUSB_INTR_VBUSERROR;
+ WARNING("VBUS error workaround (delay coming)\n");
+ } else if (drvvbus) {
+ MUSB_HST_MODE(musb);
+ musb->port1_status |= USB_PORT_STAT_POWER;
+ } else if (!(musb->int_usb & MUSB_INTR_BABBLE)) {
+ /*
+ * When babble condition happens, drvvbus interrupt
+ * is also generated. Ignore this drvvbus interrupt
+ * and let babble interrupt handler recovers the
+ * controller; otherwise, the host-mode flag is lost
+ * due to the MUSB_DEV_MODE() call below and babble
+ * recovery logic will not be called.
+ */
+ musb->is_active = 0;
+ MUSB_DEV_MODE(musb);
+ musb->port1_status &= ~USB_PORT_STAT_POWER;
+ }
+ ret = IRQ_HANDLED;
+ }
+
+ if (musb->int_tx || musb->int_rx || musb->int_usb)
+ ret |= musb_interrupt(musb);
+eoi:
+ /* EOI needs to be written for the IRQ to be re-asserted. */
+ if (ret == IRQ_HANDLED || status)
+ musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
+
+ spin_unlock_irqrestore(&musb->lock, flags);
+
+ return ret;
+}
+
+static int da8xx_musb_init(struct musb *musb)
+{
+ u32 revision;
+ void __iomem *reg_base = musb->ctrl_base;
+
+ int ret;
+
+ /* reset the controller */
+ writel(0x1, &da8xx_usb_regs->control);
+ udelay(50);
+
+ /* Returns zero if e.g. not clocked */
+ revision = readl(&da8xx_usb_regs->revision);
+ if (revision == 0)
+ return -ENODEV;
+
+ /* Disable all interrupts */
+ writel((DA8XX_USB_USBINT_MASK | DA8XX_USB_TXINT_MASK |
+ DA8XX_USB_RXINT_MASK), &da8xx_usb_regs->intmsk_set);
+
+ musb->mregs += DA8XX_MENTOR_CORE_OFFSET;
+
+ /* NOTE: IRQs are in mixed mode, not bypass to pure MUSB */
+ debug("DA8xx OTG revision %08x, control %02x\n", revision,
+ musb_readb(reg_base, DA8XX_USB_CTRL_REG));
+
+ musb->isr = da8xx_musb_interrupt;
+ return 0;
+}
+
+static int da8xx_musb_exit(struct musb *musb)
+{
+ /* flush any interrupts */
+ writel((DA8XX_USB_USBINT_MASK | DA8XX_USB_TXINT_MASK |
+ DA8XX_USB_RXINT_MASK), &da8xx_usb_regs->intmsk_clr);
+ writel(0, &da8xx_usb_regs->eoi);
+
+ return 0;
+}
+
+/**
+ * da8xx_musb_enable - enable interrupts
+ */
+static int da8xx_musb_enable(struct musb *musb)
+{
+ void __iomem *reg_base = musb->ctrl_base;
+ u32 mask;
+
+ /* Workaround: setup IRQs through both register sets. */
+ mask = ((musb->epmask & DA8XX_USB_TX_EP_MASK) << DA8XX_INTR_TX_SHIFT) |
+ ((musb->epmask & DA8XX_USB_RX_EP_MASK) << DA8XX_INTR_RX_SHIFT) |
+ DA8XX_INTR_USB_MASK;
+ musb_writel(reg_base, DA8XX_USB_INTR_MASK_SET_REG, mask);
+
+ /* Force the DRVVBUS IRQ so we can start polling for ID change. */
+ musb_writel(reg_base, DA8XX_USB_INTR_SRC_SET_REG,
+ DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT);
+
+ return 0;
+}
+
+/**
+ * da8xx_musb_disable - disable HDRC and flush interrupts
+ */
+static void da8xx_musb_disable(struct musb *musb)
+{
+ void __iomem *reg_base = musb->ctrl_base;
+
+ musb_writel(reg_base, DA8XX_USB_INTR_MASK_CLEAR_REG,
+ DA8XX_INTR_USB_MASK |
+ DA8XX_INTR_TX_MASK | DA8XX_INTR_RX_MASK);
+ musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
+}
+
+void da8xx_musb_reset(struct udevice *dev)
+{
+ void *reg_base = dev_read_addr_ptr(dev);
+
+ /* Reset the controller */
+ musb_writel(reg_base, DA8XX_USB_CTRL_REG, DA8XX_SOFT_RESET_MASK);
+}
+
+void da8xx_musb_clear_irq(struct udevice *dev)
+{
+ /* flush any interrupts */
+ writel((DA8XX_USB_USBINT_MASK | DA8XX_USB_TXINT_MASK |
+ DA8XX_USB_RXINT_MASK), &da8xx_usb_regs->intmsk_clr);
+ writel(0, &da8xx_usb_regs->eoi);
+}
+
+const struct musb_platform_ops da8xx_ops = {
+ .init = da8xx_musb_init,
+ .exit = da8xx_musb_exit,
+ .enable = da8xx_musb_enable,
+ .disable = da8xx_musb_disable,
+};
+
+struct da8xx_musb_platdata {
+ void *base;
+ void *ctrl_mod_base;
+ struct musb_hdrc_platform_data plat;
+ struct musb_hdrc_config musb_config;
+ struct omap_musb_board_data otg_board_data;
+ struct phy phy;
+};
+
+static int da8xx_musb_ofdata_to_platdata(struct udevice *dev)
+{
+ struct da8xx_musb_platdata *platdata = dev_get_platdata(dev);
+ const void *fdt = gd->fdt_blob;
+ int node = dev_of_offset(dev);
+
+ platdata->base = (void *)dev_read_addr_ptr(dev);
+ platdata->musb_config.multipoint = 1;
+ platdata->musb_config.dyn_fifo = 1;
+ platdata->musb_config.num_eps = 5;
+ platdata->musb_config.ram_bits = 10;
+ platdata->plat.power = fdtdec_get_int(fdt, node, "power", 50);
+ platdata->otg_board_data.interface_type = MUSB_INTERFACE_UTMI;
+ platdata->plat.mode = MUSB_HOST;
+ platdata->otg_board_data.dev = dev;
+ platdata->plat.config = &platdata->musb_config;
+ platdata->plat.platform_ops = &da8xx_ops;
+ platdata->plat.board_data = &platdata->otg_board_data;
+ platdata->otg_board_data.clear_irq = da8xx_musb_clear_irq;
+ platdata->otg_board_data.reset = da8xx_musb_reset;
+ return 0;
+}
+
+static int da8xx_musb_probe(struct udevice *dev)
+{
+ struct musb_host_data *host = dev_get_priv(dev);
+ struct da8xx_musb_platdata *platdata = dev_get_platdata(dev);
+ struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
+ struct omap_musb_board_data *otg_board_data;
+ int ret;
+ void *base = dev_read_addr_ptr(dev);
+
+ /* Get the phy info from the device tree */
+ ret = generic_phy_get_by_name(dev, "usb-phy", &platdata->phy);
+ if (ret)
+ return ret;
+
+ /* Initialize the phy */
+ ret = generic_phy_init(&platdata->phy);
+ if (ret)
+ return ret;
+
+ /* enable psc for usb2.0 */
+ lpsc_on(33);
+
+ /* Enable phy */
+ generic_phy_power_on(&platdata->phy);
+
+ priv->desc_before_addr = true;
+ otg_board_data = &platdata->otg_board_data;
+
+ host->host = musb_init_controller(&platdata->plat,
+ (struct device *)otg_board_data,
+ platdata->base);
+ if (!host->host) {
+ ret = -ENODEV;
+ goto shutdown; /* Shutdown what we started */
+ }
+
+ ret = musb_lowlevel_init(host);
+
+ if (ret == 0)
+ return 0;
+shutdown:
+ /* Turn off the phy if we fail */
+ generic_phy_power_off(&platdata->phy);
+ lpsc_disable(33);
+ return ret;
+}
+
+static int da8xx_musb_remove(struct udevice *dev)
+{
+ struct musb_host_data *host = dev_get_priv(dev);
+
+ musb_stop(host->host);
+
+ return 0;
+}
+
+static const struct udevice_id da8xx_musb_ids[] = {
+ { .compatible = "ti,da830-musb" },
+ { }
+};
+
+U_BOOT_DRIVER(da8xx_musb) = {
+ .name = "da8xx-musb",
+ .id = UCLASS_USB,
+ .of_match = da8xx_musb_ids,
+ .ofdata_to_platdata = da8xx_musb_ofdata_to_platdata,
+ .probe = da8xx_musb_probe,
+ .remove = da8xx_musb_remove,
+ .ops = &musb_usb_ops,
+ .platdata_auto_alloc_size = sizeof(struct da8xx_musb_platdata),
+ .priv_auto_alloc_size = sizeof(struct musb_host_data),
+};
diff --git a/drivers/usb/musb-new/musb_uboot.c b/drivers/usb/musb-new/musb_uboot.c
index 9c8cc6e..9eb5934 100644
--- a/drivers/usb/musb-new/musb_uboot.c
+++ b/drivers/usb/musb-new/musb_uboot.c
@@ -110,7 +110,7 @@
static int _musb_submit_int_msg(struct musb_host_data *host,
struct usb_device *dev, unsigned long pipe,
- void *buffer, int len, int interval)
+ void *buffer, int len, int interval, bool nonblock)
{
construct_urb(&host->urb, &host->hep, dev, USB_ENDPOINT_XFER_INT, pipe,
buffer, len, NULL, interval);
@@ -268,9 +268,10 @@
}
int submit_int_msg(struct usb_device *dev, unsigned long pipe,
- void *buffer, int length, int interval)
+ void *buffer, int length, int interval, bool nonblock)
{
- return _musb_submit_int_msg(&musb_host, dev, pipe, buffer, length, interval);
+ return _musb_submit_int_msg(&musb_host, dev, pipe, buffer, length,
+ interval, nonblock);
}
struct int_queue *create_int_queue(struct usb_device *dev,
@@ -320,10 +321,11 @@
static int musb_submit_int_msg(struct udevice *dev, struct usb_device *udev,
unsigned long pipe, void *buffer, int length,
- int interval)
+ int interval, bool nonblock)
{
struct musb_host_data *host = dev_get_priv(dev);
- return _musb_submit_int_msg(host, udev, pipe, buffer, length, interval);
+ return _musb_submit_int_msg(host, udev, pipe, buffer, length, interval,
+ nonblock);
}
static struct int_queue *musb_create_int_queue(struct udevice *dev,
diff --git a/drivers/usb/musb-new/omap2430.c b/drivers/usb/musb-new/omap2430.c
index 32743aa..cca1653 100644
--- a/drivers/usb/musb-new/omap2430.c
+++ b/drivers/usb/musb-new/omap2430.c
@@ -215,11 +215,13 @@
{
#ifdef CONFIG_USB_MUSB_HOST
struct musb_host_data *host = dev_get_priv(dev);
+#else
+ struct musb *musbp;
#endif
struct omap2430_musb_platdata *platdata = dev_get_platdata(dev);
struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
struct omap_musb_board_data *otg_board_data;
- int ret;
+ int ret = 0;
void *base = dev_read_addr_ptr(dev);
priv->desc_before_addr = true;
@@ -236,9 +238,11 @@
ret = musb_lowlevel_init(host);
#else
- ret = musb_register(&platdata->plat,
+ musbp = musb_register(&platdata->plat,
(struct device *)otg_board_data,
platdata->base);
+ if (IS_ERR_OR_NULL(musbp))
+ return -EINVAL;
#endif
return ret;
}
diff --git a/drivers/usb/musb/musb_hcd.c b/drivers/usb/musb/musb_hcd.c
index 1f28052..adcd319 100644
--- a/drivers/usb/musb/musb_hcd.c
+++ b/drivers/usb/musb/musb_hcd.c
@@ -1049,8 +1049,8 @@
* This function supports usb interrupt transfers. Currently, usb interrupt
* transfers are not supported.
*/
-int submit_int_msg(struct usb_device *dev, unsigned long pipe,
- void *buffer, int len, int interval)
+int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int len, int interval, bool nonblock)
{
int dir_out = usb_pipeout(pipe);
int ep = usb_pipeendpoint(pipe);
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index c3781b1..261fa98 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -484,7 +484,7 @@
config VIDEO_FSL_DCU_FB
bool "Enable Freescale Display Control Unit"
- depends on VIDEO
+ depends on VIDEO || DM_VIDEO
help
This enables support for Freescale Display Control Unit (DCU4)
module found on Freescale Vybrid and QorIQ family of SoCs.
diff --git a/drivers/video/ati_radeon_fb.c b/drivers/video/ati_radeon_fb.c
index 87557e5..6fce033 100644
--- a/drivers/video/ati_radeon_fb.c
+++ b/drivers/video/ati_radeon_fb.c
@@ -19,6 +19,7 @@
#include <command.h>
#include <bios_emul.h>
+#include <env.h>
#include <pci.h>
#include <asm/processor.h>
#include <linux/errno.h>
diff --git a/drivers/video/bcm2835.c b/drivers/video/bcm2835.c
index bc41090..1d2eda0 100644
--- a/drivers/video/bcm2835.c
+++ b/drivers/video/bcm2835.c
@@ -19,13 +19,15 @@
debug("bcm2835: Query resolution...\n");
ret = bcm2835_get_video_size(&w, &h);
- if (ret)
+ if (ret || w == 0 || h == 0)
return -EIO;
debug("bcm2835: Setting up display for %d x %d\n", w, h);
ret = bcm2835_set_video_params(&w, &h, 32, BCM2835_MBOX_PIXEL_ORDER_RGB,
BCM2835_MBOX_ALPHA_MODE_IGNORED,
&fb_base, &fb_size, &pitch);
+ if (ret)
+ return -EIO;
debug("bcm2835: Final resolution is %d x %d\n", w, h);
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index 636c3e8..e5c077e 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -65,7 +65,9 @@
*/
#include <common.h>
+#include <env.h>
#include <fdtdec.h>
+#include <gzip.h>
#include <version.h>
#include <malloc.h>
#include <video.h>
diff --git a/drivers/video/display-uclass.c b/drivers/video/display-uclass.c
index 99ef5e7..1a29ce5 100644
--- a/drivers/video/display-uclass.c
+++ b/drivers/video/display-uclass.c
@@ -37,6 +37,17 @@
return 0;
}
+static bool display_mode_valid(void *priv, const struct display_timing *timing)
+{
+ struct udevice *dev = priv;
+ struct dm_display_ops *ops = display_get_ops(dev);
+
+ if (ops && ops->mode_valid)
+ return ops->mode_valid(dev, timing);
+
+ return true;
+}
+
int display_read_timing(struct udevice *dev, struct display_timing *timing)
{
struct dm_display_ops *ops = display_get_ops(dev);
@@ -53,7 +64,9 @@
if (ret < 0)
return ret;
- return edid_get_timing(buf, ret, timing, &panel_bits_per_colour);
+ return edid_get_timing_validate(buf, ret, timing,
+ &panel_bits_per_colour,
+ display_mode_valid, dev);
}
bool display_in_use(struct udevice *dev)
diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c
index 463436e..bf74d6a 100644
--- a/drivers/video/dw_hdmi.c
+++ b/drivers/video/dw_hdmi.c
@@ -8,6 +8,7 @@
#include <common.h>
#include <fdtdec.h>
#include <asm/io.h>
+#include <i2c.h>
#include <media_bus_format.h>
#include "dw_hdmi.h"
@@ -812,6 +813,18 @@
u32 trytime = 5;
u32 n;
+ if (CONFIG_IS_ENABLED(DM_I2C) && hdmi->ddc_bus) {
+ struct udevice *chip;
+
+ edid_read_err = i2c_get_chip(hdmi->ddc_bus,
+ HDMI_I2CM_SLAVE_DDC_ADDR,
+ 1, &chip);
+ if (edid_read_err)
+ return edid_read_err;
+
+ return dm_i2c_read(chip, shift, buff, HDMI_EDID_BLOCK_SIZE);
+ }
+
/* set ddc i2c clk which devided from ddc_clk to 100khz */
hdmi_write(hdmi, hdmi->i2c_clk_high, HDMI_I2CM_SS_SCL_HCNT_0_ADDR);
hdmi_write(hdmi, hdmi->i2c_clk_low, HDMI_I2CM_SS_SCL_LCNT_0_ADDR);
diff --git a/drivers/video/fsl_dcu_fb.c b/drivers/video/fsl_dcu_fb.c
index 9f6e7f8..add64b8 100644
--- a/drivers/video/fsl_dcu_fb.c
+++ b/drivers/video/fsl_dcu_fb.c
@@ -1,16 +1,19 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2019 Toradex AG
*
* FSL DCU Framebuffer driver
*/
#include <asm/io.h>
#include <common.h>
+#include <dm.h>
#include <fdt_support.h>
#include <fsl_dcu_fb.h>
#include <linux/fb.h>
#include <malloc.h>
+#include <video.h>
#include <video_fb.h>
#include "videomodes.h"
@@ -218,8 +221,6 @@
u32 ctrldescl[DCU_LAYER_MAX_NUM][16];
};
-static struct fb_info info;
-
static void reset_total_layers(void)
{
struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
@@ -240,20 +241,22 @@
}
}
-static int layer_ctrldesc_init(int index, u32 pixel_format)
+static int layer_ctrldesc_init(struct fb_info fbinfo,
+ int index, u32 pixel_format)
{
struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
unsigned int bpp = BPP_24_RGB888;
dcu_write32(®s->ctrldescl[index][0],
- DCU_CTRLDESCLN_1_HEIGHT(info.var.yres) |
- DCU_CTRLDESCLN_1_WIDTH(info.var.xres));
+ DCU_CTRLDESCLN_1_HEIGHT(fbinfo.var.yres) |
+ DCU_CTRLDESCLN_1_WIDTH(fbinfo.var.xres));
dcu_write32(®s->ctrldescl[index][1],
DCU_CTRLDESCLN_2_POSY(0) |
DCU_CTRLDESCLN_2_POSX(0));
- dcu_write32(®s->ctrldescl[index][2], (unsigned int)info.screen_base);
+ dcu_write32(®s->ctrldescl[index][2],
+ (unsigned int)fbinfo.screen_base);
switch (pixel_format) {
case 16:
@@ -294,42 +297,46 @@
return 0;
}
-int fsl_dcu_init(unsigned int xres, unsigned int yres,
- unsigned int pixel_format)
+int fsl_dcu_init(struct fb_info *fbinfo, unsigned int xres,
+ unsigned int yres, unsigned int pixel_format)
{
struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
unsigned int div, mode;
+/*
+ * When DM_VIDEO is enabled reservation of framebuffer is done
+ * in advance during bind() call.
+ */
+#if !CONFIG_IS_ENABLED(DM_VIDEO)
+ fbinfo->screen_size = fbinfo->var.xres * fbinfo->var.yres *
+ (fbinfo->var.bits_per_pixel / 8);
- info.screen_size =
- info.var.xres * info.var.yres * (info.var.bits_per_pixel / 8);
-
- if (info.screen_size > CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB) {
- info.screen_size = 0;
+ if (fbinfo->screen_size > CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB) {
+ fbinfo->screen_size = 0;
return -ENOMEM;
}
-
/* Reserve framebuffer at the end of memory */
gd->fb_base = gd->bd->bi_dram[0].start +
- gd->bd->bi_dram[0].size - info.screen_size;
- info.screen_base = (char *)gd->fb_base;
+ gd->bd->bi_dram[0].size - fbinfo->screen_size;
+ fbinfo->screen_base = (char *)gd->fb_base;
- memset(info.screen_base, 0, info.screen_size);
+ memset(fbinfo->screen_base, 0, fbinfo->screen_size);
+#endif
reset_total_layers();
dcu_write32(®s->disp_size,
- DCU_DISP_SIZE_DELTA_Y(info.var.yres) |
- DCU_DISP_SIZE_DELTA_X(info.var.xres / 16));
+ DCU_DISP_SIZE_DELTA_Y(fbinfo->var.yres) |
+ DCU_DISP_SIZE_DELTA_X(fbinfo->var.xres / 16));
dcu_write32(®s->hsyn_para,
- DCU_HSYN_PARA_BP(info.var.left_margin) |
- DCU_HSYN_PARA_PW(info.var.hsync_len) |
- DCU_HSYN_PARA_FP(info.var.right_margin));
+ DCU_HSYN_PARA_BP(fbinfo->var.left_margin) |
+ DCU_HSYN_PARA_PW(fbinfo->var.hsync_len) |
+ DCU_HSYN_PARA_FP(fbinfo->var.right_margin));
dcu_write32(®s->vsyn_para,
- DCU_VSYN_PARA_BP(info.var.upper_margin) |
- DCU_VSYN_PARA_PW(info.var.vsync_len) |
- DCU_VSYN_PARA_FP(info.var.lower_margin));
+ DCU_VSYN_PARA_BP(fbinfo->var.upper_margin) |
+ DCU_VSYN_PARA_PW(fbinfo->var.vsync_len) |
+ DCU_VSYN_PARA_FP(fbinfo->var.lower_margin));
dcu_write32(®s->synpol,
DCU_SYN_POL_INV_PXCK_FALL |
@@ -352,9 +359,9 @@
mode = dcu_read32(®s->mode);
dcu_write32(®s->mode, mode | DCU_MODE_NORMAL);
- layer_ctrldesc_init(0, pixel_format);
+ layer_ctrldesc_init(*fbinfo, 0, pixel_format);
- div = dcu_set_pixel_clock(info.var.pixclock);
+ div = dcu_set_pixel_clock(fbinfo->var.pixclock);
dcu_write32(®s->div_ratio, (div - 1));
dcu_write32(®s->update_mode, DCU_UPDATE_MODE_READREG);
@@ -367,24 +374,26 @@
return gd->ram_top - CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB;
}
-void *video_hw_init(void)
+int fsl_probe_common(struct fb_info *fbinfo, unsigned int *win_x,
+ unsigned int *win_y)
{
- static GraphicDevice ctfb;
const char *options;
unsigned int depth = 0, freq = 0;
+
struct fb_videomode *fsl_dcu_mode_db = &fsl_dcu_mode_480_272;
- if (!video_get_video_mode(&ctfb.winSizeX, &ctfb.winSizeY, &depth, &freq,
+ if (!video_get_video_mode(win_x, win_y, &depth, &freq,
&options))
- return NULL;
+ return -EINVAL;
/* Find the monitor port, which is a required option */
if (!options)
- return NULL;
- if (strncmp(options, "monitor=", 8) != 0)
- return NULL;
+ return -EINVAL;
- switch (RESOLUTION(ctfb.winSizeX, ctfb.winSizeY)) {
+ if (strncmp(options, "monitor=", 8) != 0)
+ return -EINVAL;
+
+ switch (RESOLUTION(*win_x, *win_y)) {
case RESOLUTION(480, 272):
fsl_dcu_mode_db = &fsl_dcu_mode_480_272;
break;
@@ -402,39 +411,31 @@
break;
default:
printf("unsupported resolution %ux%u\n",
- ctfb.winSizeX, ctfb.winSizeY);
+ *win_x, *win_y);
}
- info.var.xres = fsl_dcu_mode_db->xres;
- info.var.yres = fsl_dcu_mode_db->yres;
- info.var.bits_per_pixel = 32;
- info.var.pixclock = fsl_dcu_mode_db->pixclock;
- info.var.left_margin = fsl_dcu_mode_db->left_margin;
- info.var.right_margin = fsl_dcu_mode_db->right_margin;
- info.var.upper_margin = fsl_dcu_mode_db->upper_margin;
- info.var.lower_margin = fsl_dcu_mode_db->lower_margin;
- info.var.hsync_len = fsl_dcu_mode_db->hsync_len;
- info.var.vsync_len = fsl_dcu_mode_db->vsync_len;
- info.var.sync = fsl_dcu_mode_db->sync;
- info.var.vmode = fsl_dcu_mode_db->vmode;
- info.fix.line_length = info.var.xres * info.var.bits_per_pixel / 8;
+ fbinfo->var.xres = fsl_dcu_mode_db->xres;
+ fbinfo->var.yres = fsl_dcu_mode_db->yres;
+ fbinfo->var.bits_per_pixel = 32;
+ fbinfo->var.pixclock = fsl_dcu_mode_db->pixclock;
+ fbinfo->var.left_margin = fsl_dcu_mode_db->left_margin;
+ fbinfo->var.right_margin = fsl_dcu_mode_db->right_margin;
+ fbinfo->var.upper_margin = fsl_dcu_mode_db->upper_margin;
+ fbinfo->var.lower_margin = fsl_dcu_mode_db->lower_margin;
+ fbinfo->var.hsync_len = fsl_dcu_mode_db->hsync_len;
+ fbinfo->var.vsync_len = fsl_dcu_mode_db->vsync_len;
+ fbinfo->var.sync = fsl_dcu_mode_db->sync;
+ fbinfo->var.vmode = fsl_dcu_mode_db->vmode;
+ fbinfo->fix.line_length = fbinfo->var.xres *
+ fbinfo->var.bits_per_pixel / 8;
- if (platform_dcu_init(ctfb.winSizeX, ctfb.winSizeY,
- options + 8, fsl_dcu_mode_db) < 0)
- return NULL;
-
- ctfb.frameAdrs = (unsigned int)info.screen_base;
- ctfb.plnSizeX = ctfb.winSizeX;
- ctfb.plnSizeY = ctfb.winSizeY;
-
- ctfb.gdfBytesPP = 4;
- ctfb.gdfIndex = GDF_32BIT_X888RGB;
-
- ctfb.memSize = info.screen_size;
-
- return &ctfb;
+ return platform_dcu_init(fbinfo, *win_x, *win_y,
+ options + 8, fsl_dcu_mode_db);
}
+#ifndef CONFIG_DM_VIDEO
+static struct fb_info info;
+
#if defined(CONFIG_OF_BOARD_SETUP)
int fsl_dcu_fixedfb_setup(void *blob)
{
@@ -457,3 +458,89 @@
return 0;
}
#endif
+
+void *video_hw_init(void)
+{
+ static GraphicDevice ctfb;
+
+ if (fsl_probe_common(&info, &ctfb.winSizeX, &ctfb.winSizeY) < 0)
+ return NULL;
+
+ ctfb.frameAdrs = (unsigned int)info.screen_base;
+ ctfb.plnSizeX = ctfb.winSizeX;
+ ctfb.plnSizeY = ctfb.winSizeY;
+
+ ctfb.gdfBytesPP = 4;
+ ctfb.gdfIndex = GDF_32BIT_X888RGB;
+
+ ctfb.memSize = info.screen_size;
+
+ return &ctfb;
+}
+
+#else /* ifndef CONFIG_DM_VIDEO */
+
+static int fsl_dcu_video_probe(struct udevice *dev)
+{
+ struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct fb_info fbinfo = { 0 };
+ unsigned int win_x;
+ unsigned int win_y;
+ u32 fb_start, fb_end;
+ int ret = 0;
+
+ fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
+ fb_end = plat->base + plat->size;
+ fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
+
+ fbinfo.screen_base = (char *)fb_start;
+ fbinfo.screen_size = plat->size;
+
+ ret = fsl_probe_common(&fbinfo, &win_x, &win_y);
+ if (ret < 0)
+ return ret;
+
+ uc_priv->bpix = VIDEO_BPP32;
+ uc_priv->xsize = win_x;
+ uc_priv->ysize = win_y;
+
+ /* Enable dcache for the frame buffer */
+ mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
+ DCACHE_WRITEBACK);
+ video_set_flush_dcache(dev, true);
+ return ret;
+}
+
+static int fsl_dcu_video_bind(struct udevice *dev)
+{
+ struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ unsigned int win_x;
+ unsigned int win_y;
+ unsigned int depth = 0, freq = 0;
+ const char *options;
+ int ret = 0;
+
+ ret = video_get_video_mode(&win_x, &win_y, &depth, &freq, &options);
+ if (ret < 0)
+ return ret;
+
+ plat->size = win_x * win_y * 32;
+
+ return 0;
+}
+
+static const struct udevice_id fsl_dcu_video_ids[] = {
+ { .compatible = "fsl,vf610-dcu" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(fsl_dcu_video) = {
+ .name = "fsl_dcu_video",
+ .id = UCLASS_VIDEO,
+ .of_match = fsl_dcu_video_ids,
+ .bind = fsl_dcu_video_bind,
+ .probe = fsl_dcu_video_probe,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+#endif /* ifndef CONFIG_DM_VIDEO */
diff --git a/drivers/video/imx/mxc_ipuv3_fb.c b/drivers/video/imx/mxc_ipuv3_fb.c
index 29ecac4..c64be38 100644
--- a/drivers/video/imx/mxc_ipuv3_fb.c
+++ b/drivers/video/imx/mxc_ipuv3_fb.c
@@ -24,6 +24,8 @@
#include "ipu.h"
#include "mxcfb.h"
#include "ipu_regs.h"
+#include "display.h"
+#include <panel.h>
#include <dm.h>
#include <video.h>
@@ -609,6 +611,7 @@
ret = mxcfb_probe(gpixfmt, gdisp, gmode);
debug("Framebuffer at 0x%x\n", (unsigned int)panel.frameAdrs);
+ gd->fb_base = panel.frameAdrs;
return (void *)&panel;
}
@@ -636,6 +639,10 @@
{
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+#if defined(CONFIG_DISPLAY)
+ struct udevice *disp_dev;
+#endif
+ struct udevice *panel_dev;
u32 fb_start, fb_end;
int ret;
@@ -654,6 +661,18 @@
if (ret < 0)
return ret;
+#if defined(CONFIG_DISPLAY)
+ ret = uclass_first_device(UCLASS_DISPLAY, &disp_dev);
+ if (disp_dev) {
+ ret = display_enable(disp_dev, 16, NULL);
+ if (ret < 0)
+ return ret;
+ }
+#endif
+ ret = uclass_get_device(UCLASS_PANEL, 0, &panel_dev);
+ if (panel_dev)
+ panel_enable_backlight(panel_dev);
+
uc_priv->xsize = gmode->xres;
uc_priv->ysize = gmode->yres;
uc_priv->bpix = LCD_MAX_LOG2_BPP;
@@ -665,6 +684,7 @@
mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
DCACHE_WRITEBACK);
video_set_flush_dcache(dev, true);
+ gd->fb_base = fb_start;
return 0;
}
diff --git a/drivers/video/mb862xx.c b/drivers/video/mb862xx.c
index 1a3c970..301c1f0 100644
--- a/drivers/video/mb862xx.c
+++ b/drivers/video/mb862xx.c
@@ -12,6 +12,7 @@
#include <common.h>
#include <asm/io.h>
+#include <env.h>
#include <pci.h>
#include <video_fb.h>
#include "videomodes.h"
diff --git a/drivers/video/meson/meson_dw_hdmi.c b/drivers/video/meson/meson_dw_hdmi.c
index 483c93f..9831d97 100644
--- a/drivers/video/meson/meson_dw_hdmi.c
+++ b/drivers/video/meson/meson_dw_hdmi.c
@@ -375,6 +375,9 @@
}
#endif
+ uclass_get_device_by_phandle(UCLASS_I2C, dev, "ddc-i2c-bus",
+ &priv->hdmi.ddc_bus);
+
ret = reset_get_bulk(dev, &resets);
if (ret)
return ret;
@@ -426,9 +429,16 @@
return ret;
}
+static bool meson_dw_hdmi_mode_valid(struct udevice *dev,
+ const struct display_timing *timing)
+{
+ return meson_venc_hdmi_supported_mode(timing);
+}
+
static const struct dm_display_ops meson_dw_hdmi_ops = {
.read_edid = meson_dw_hdmi_read_edid,
.enable = meson_dw_hdmi_enable,
+ .mode_valid = meson_dw_hdmi_mode_valid,
};
static const struct udevice_id meson_dw_hdmi_ids[] = {
diff --git a/drivers/video/mx3fb.c b/drivers/video/mx3fb.c
index 176ae70..a984443 100644
--- a/drivers/video/mx3fb.c
+++ b/drivers/video/mx3fb.c
@@ -6,6 +6,7 @@
* HALE electronic GmbH, <helmut.raiger@hale.at>
*/
#include <common.h>
+#include <env.h>
#include <malloc.h>
#include <video_fb.h>
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index f02ba20..6922a13 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -6,6 +6,7 @@
*/
#include <common.h>
#include <dm.h>
+#include <env.h>
#include <linux/errno.h>
#include <malloc.h>
#include <video.h>
@@ -271,6 +272,42 @@
}
#else /* ifndef CONFIG_DM_VIDEO */
+static int mxs_of_get_timings(struct udevice *dev,
+ struct display_timing *timings,
+ u32 *bpp)
+{
+ int ret = 0;
+ u32 display_phandle;
+ ofnode display_node;
+
+ ret = ofnode_read_u32(dev_ofnode(dev), "display", &display_phandle);
+ if (ret) {
+ dev_err(dev, "required display property isn't provided\n");
+ return -EINVAL;
+ }
+
+ display_node = ofnode_get_by_phandle(display_phandle);
+ if (!ofnode_valid(display_node)) {
+ dev_err(dev, "failed to find display subnode\n");
+ return -EINVAL;
+ }
+
+ ret = ofnode_read_u32(display_node, "bits-per-pixel", bpp);
+ if (ret) {
+ dev_err(dev,
+ "required bits-per-pixel property isn't provided\n");
+ return -EINVAL;
+ }
+
+ ret = ofnode_decode_display_timing(display_node, 0, timings);
+ if (ret) {
+ dev_err(dev, "failed to get any display timings\n");
+ return -EINVAL;
+ }
+
+ return ret;
+}
+
static int mxs_video_probe(struct udevice *dev)
{
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
@@ -278,18 +315,16 @@
struct ctfb_res_modes mode;
struct display_timing timings;
- int bpp = -1;
+ u32 bpp = 0;
u32 fb_start, fb_end;
int ret;
debug("%s() plat: base 0x%lx, size 0x%x\n",
__func__, plat->base, plat->size);
- ret = ofnode_decode_display_timing(dev_ofnode(dev), 0, &timings);
- if (ret) {
- dev_err(dev, "failed to get any display timings\n");
- return -EINVAL;
- }
+ ret = mxs_of_get_timings(dev, &timings, &bpp);
+ if (ret)
+ return ret;
mode.xres = timings.hactive.typ;
mode.yres = timings.vactive.typ;
@@ -301,13 +336,12 @@
mode.vsync_len = timings.vsync_len.typ;
mode.pixclock = HZ2PS(timings.pixelclock.typ);
- bpp = BITS_PP;
-
ret = mxs_probe_common(&mode, bpp, plat->base);
if (ret)
return ret;
switch (bpp) {
+ case 32:
case 24:
case 18:
uc_priv->bpix = VIDEO_BPP32;
@@ -341,15 +375,32 @@
{
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
struct display_timing timings;
+ u32 bpp = 0;
+ u32 bytes_pp = 0;
int ret;
- ret = ofnode_decode_display_timing(dev_ofnode(dev), 0, &timings);
- if (ret) {
- dev_err(dev, "failed to get any display timings\n");
+ ret = mxs_of_get_timings(dev, &timings, &bpp);
+ if (ret)
+ return ret;
+
+ switch (bpp) {
+ case 32:
+ case 24:
+ case 18:
+ bytes_pp = 4;
+ break;
+ case 16:
+ bytes_pp = 2;
+ break;
+ case 8:
+ bytes_pp = 1;
+ break;
+ default:
+ dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp);
return -EINVAL;
}
- plat->size = timings.hactive.typ * timings.vactive.typ * BYTES_PP;
+ plat->size = timings.hactive.typ * timings.vactive.typ * bytes_pp;
return 0;
}
diff --git a/drivers/video/rockchip/rk3288_hdmi.c b/drivers/video/rockchip/rk3288_hdmi.c
index 315d3ad..3d25ce9 100644
--- a/drivers/video/rockchip/rk3288_hdmi.c
+++ b/drivers/video/rockchip/rk3288_hdmi.c
@@ -33,7 +33,7 @@
/* hdmi data from vop id */
rk_clrsetreg(&grf->soc_con6, 1 << 4, (vop_id == 1) ? (1 << 4) : 0);
- return 0;
+ return dw_hdmi_enable(&priv->hdmi, edid);
}
static int rk3288_hdmi_ofdata_to_platdata(struct udevice *dev)
diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c
index 51931ce..5b44a7e 100644
--- a/drivers/video/rockchip/rk_hdmi.c
+++ b/drivers/video/rockchip/rk_hdmi.c
@@ -93,6 +93,9 @@
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ uclass_get_device_by_phandle(UCLASS_I2C, dev, "ddc-i2c-bus",
+ &hdmi->ddc_bus);
+
return 0;
}
diff --git a/drivers/video/simple_panel.c b/drivers/video/simple_panel.c
index 7a968e7..c3c0e84 100644
--- a/drivers/video/simple_panel.c
+++ b/drivers/video/simple_panel.c
@@ -105,6 +105,7 @@
{ .compatible = "auo,b133xtn01" },
{ .compatible = "auo,b116xw03" },
{ .compatible = "auo,b133htn01" },
+ { .compatible = "lg,lb070wv8" },
{ }
};
diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c
index 6fe1aa7..66a3191 100644
--- a/drivers/video/sunxi/sunxi_dw_hdmi.c
+++ b/drivers/video/sunxi/sunxi_dw_hdmi.c
@@ -254,7 +254,7 @@
{
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- int div = clock_get_pll3() / edid->pixelclock.typ;
+ int div = DIV_ROUND_UP(clock_get_pll3(), edid->pixelclock.typ);
struct sunxi_lcdc_reg *lcdc;
if (mux == 0) {
@@ -373,6 +373,9 @@
priv->hdmi.phy_set = sunxi_dw_hdmi_phy_cfg;
priv->mux = uc_plat->source_id;
+ uclass_get_device_by_phandle(UCLASS_I2C, dev, "ddc-i2c-bus",
+ &priv->hdmi.ddc_bus);
+
dw_hdmi_init(&priv->hdmi);
return 0;
diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c
index b19bfb4..d4071c0 100644
--- a/drivers/video/video-uclass.c
+++ b/drivers/video/video-uclass.c
@@ -291,7 +291,9 @@
return 0;
size = alloc_fb(dev, &addr);
if (addr < gd->video_bottom) {
- /* Device tree node may need the 'u-boot,dm-pre-reloc' tag */
+ /* Device tree node may need the 'u-boot,dm-pre-reloc' or
+ * 'u-boot,dm-pre-proper' tag
+ */
printf("Video device '%s' cannot allocate frame buffer memory -ensure the device is set up before relocation\n",
dev->name);
return -ENOSPC;
diff --git a/drivers/video/videomodes.c b/drivers/video/videomodes.c
index d761432..ac25b45 100644
--- a/drivers/video/videomodes.c
+++ b/drivers/video/videomodes.c
@@ -58,6 +58,7 @@
#include <common.h>
#include <edid.h>
+#include <env.h>
#include <errno.h>
#include <linux/ctype.h>
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index ee0ddff..a66a9bc 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -17,18 +17,9 @@
Disable reset watchdog, which can let WATCHDOG_RESET invalid, so
that the watchdog will not be fed in u-boot.
-config BCM2835_WDT
- bool "Enable BCM2835/2836 watchdog driver"
- select HW_WATCHDOG
- help
- Say Y here to enable the BCM2835/2836 watchdog
-
- This provides basic infrastructure to support BCM2835/2836 watchdog
- hardware, with a max timeout of ~15secs.
-
config IMX_WATCHDOG
bool "Enable Watchdog Timer support for IMX and LSCH2 of NXP"
- select HW_WATCHDOG
+ select HW_WATCHDOG if !WDT
help
Select this to enable the IMX and LSCH2 of Layerscape watchdog
driver.
@@ -37,7 +28,6 @@
bool "TI OMAP watchdog driver"
depends on ARCH_OMAP2PLUS
select HW_WATCHDOG
- default y if AM33XX
help
Say Y here to enable the OMAP3+ watchdog driver.
@@ -122,6 +112,14 @@
The watchdog timer is stopped when initialized.
It performs full SoC reset.
+config WDT_OMAP3
+ bool "TI OMAP watchdog timer support"
+ depends on WDT && ARCH_OMAP2PLUS
+ default y if AM33XX
+ help
+ This enables OMAP3+ watchdog timer driver, which can be
+ found on some TI chipsets and inline with driver model.
+
config WDT_ORION
bool "Orion watchdog timer support"
depends on WDT
@@ -169,4 +167,11 @@
Intel Tangier SoC. If you're using a board with Intel Tangier
SoC, say Y here.
+config SPL_WDT
+ bool "Enable driver model for watchdog timer drivers in SPL"
+ depends on SPL_DM
+ help
+ Enable driver model for watchdog timer in SPL.
+ This is similar to CONFIG_WDT in U-Boot.
+
endmenu
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 68c989a..955caef 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -15,17 +15,17 @@
obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o
obj-$(CONFIG_ULP_WATCHDOG) += ulp_wdog.o
-obj-$(CONFIG_WDT) += wdt-uclass.o
+obj-$(CONFIG_$(SPL_TPL_)WDT) += wdt-uclass.o
obj-$(CONFIG_WDT_SANDBOX) += sandbox_wdt.o
obj-$(CONFIG_WDT_ARMADA_37XX) += armada-37xx-wdt.o
obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o
obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o
-obj-$(CONFIG_BCM2835_WDT) += bcm2835_wdt.o
obj-$(CONFIG_WDT_ORION) += orion_wdt.o
obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o
obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o
obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o
obj-$(CONFIG_WDT_MTK) += mtk_wdt.o
+obj-$(CONFIG_WDT_OMAP3) += omap_wdt.o
obj-$(CONFIG_WDT_SP805) += sp805_wdt.o
obj-$(CONFIG_WDT_STM32MP) += stm32mp_wdt.o
obj-$(CONFIG_WDT_TANGIER) += tangier_wdt.o
diff --git a/drivers/watchdog/bcm2835_wdt.c b/drivers/watchdog/bcm2835_wdt.c
deleted file mode 100644
index 6cffcb1..0000000
--- a/drivers/watchdog/bcm2835_wdt.c
+++ /dev/null
@@ -1,34 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Watchdog driver for Broadcom BCM2835
- *
- * Copyright (C) 2017 Paolo Pisati <p.pisati@gmail.com>
- */
-
-#include <common.h>
-#include <efi_loader.h>
-#include <asm/io.h>
-#include <asm/arch/wdog.h>
-
-#define SECS_TO_WDOG_TICKS(x) ((x) << 16)
-#define MAX_TIMEOUT 0xf /* ~15s */
-
-static __efi_runtime_data bool enabled = true;
-
-extern void reset_cpu(ulong ticks);
-
-void hw_watchdog_reset(void)
-{
- if (enabled)
- reset_cpu(SECS_TO_WDOG_TICKS(MAX_TIMEOUT));
-}
-
-void hw_watchdog_init(void)
-{
- hw_watchdog_reset();
-}
-
-void __efi_runtime hw_watchdog_disable(void)
-{
- enabled = false;
-}
diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c
index 14cc618..53a3e9f 100644
--- a/drivers/watchdog/imx_watchdog.c
+++ b/drivers/watchdog/imx_watchdog.c
@@ -5,7 +5,9 @@
*/
#include <common.h>
+#include <dm.h>
#include <asm/io.h>
+#include <wdt.h>
#include <watchdog.h>
#include <asm/arch/imx-regs.h>
#ifdef CONFIG_FSL_LSCH2
@@ -13,20 +15,40 @@
#endif
#include <fsl_wdog.h>
-#ifdef CONFIG_IMX_WATCHDOG
-void hw_watchdog_reset(void)
+static void imx_watchdog_expire_now(struct watchdog_regs *wdog)
{
-#ifndef CONFIG_WATCHDOG_RESET_DISABLE
+ clrsetbits_le16(&wdog->wcr, WCR_WT_MSK, WCR_WDE);
+
+ writew(0x5555, &wdog->wsr);
+ writew(0xaaaa, &wdog->wsr); /* load minimum 1/2 second timeout */
+ while (1) {
+ /*
+ * spin for .5 seconds before reset
+ */
+ }
+}
+
+#if !defined(CONFIG_IMX_WATCHDOG) || \
+ (defined(CONFIG_IMX_WATCHDOG) && !CONFIG_IS_ENABLED(WDT))
+void __attribute__((weak)) reset_cpu(ulong addr)
+{
struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
+ imx_watchdog_expire_now(wdog);
+}
+#endif
+
+#if defined(CONFIG_IMX_WATCHDOG)
+static void imx_watchdog_reset(struct watchdog_regs *wdog)
+{
+#ifndef CONFIG_WATCHDOG_RESET_DISABLE
writew(0x5555, &wdog->wsr);
writew(0xaaaa, &wdog->wsr);
#endif /* CONFIG_WATCHDOG_RESET_DISABLE*/
}
-void hw_watchdog_init(void)
+static void imx_watchdog_init(struct watchdog_regs *wdog)
{
- struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
u16 timeout;
/*
@@ -44,21 +66,86 @@
writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS |
WCR_WDA | SET_WCR_WT(timeout), &wdog->wcr);
#endif /* CONFIG_FSL_LSCH2*/
- hw_watchdog_reset();
+ imx_watchdog_reset(wdog);
}
-#endif
-void __attribute__((weak)) reset_cpu(ulong addr)
+#if !CONFIG_IS_ENABLED(WDT)
+void hw_watchdog_reset(void)
{
struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
- clrsetbits_le16(&wdog->wcr, WCR_WT_MSK, WCR_WDE);
-
- writew(0x5555, &wdog->wsr);
- writew(0xaaaa, &wdog->wsr); /* load minimum 1/2 second timeout */
- while (1) {
- /*
- * spin for .5 seconds before reset
- */
- }
+ imx_watchdog_reset(wdog);
}
+
+void hw_watchdog_init(void)
+{
+ struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
+
+ imx_watchdog_init(wdog);
+}
+#else
+struct imx_wdt_priv {
+ void __iomem *base;
+};
+
+static int imx_wdt_reset(struct udevice *dev)
+{
+ struct imx_wdt_priv *priv = dev_get_priv(dev);
+
+ imx_watchdog_reset(priv->base);
+
+ return 0;
+}
+
+static int imx_wdt_expire_now(struct udevice *dev, ulong flags)
+{
+ struct imx_wdt_priv *priv = dev_get_priv(dev);
+
+ imx_watchdog_expire_now(priv->base);
+ hang();
+
+ return 0;
+}
+
+static int imx_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
+{
+ struct imx_wdt_priv *priv = dev_get_priv(dev);
+
+ imx_watchdog_init(priv->base);
+
+ return 0;
+}
+
+static int imx_wdt_probe(struct udevice *dev)
+{
+ struct imx_wdt_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_read_addr_ptr(dev);
+ if (!priv->base)
+ return -ENOENT;
+
+ return 0;
+}
+
+static const struct wdt_ops imx_wdt_ops = {
+ .start = imx_wdt_start,
+ .reset = imx_wdt_reset,
+ .expire_now = imx_wdt_expire_now,
+};
+
+static const struct udevice_id imx_wdt_ids[] = {
+ { .compatible = "fsl,imx21-wdt" },
+ {}
+};
+
+U_BOOT_DRIVER(imx_wdt) = {
+ .name = "imx_wdt",
+ .id = UCLASS_WDT,
+ .of_match = imx_wdt_ids,
+ .probe = imx_wdt_probe,
+ .ops = &imx_wdt_ops,
+ .priv_auto_alloc_size = sizeof(struct imx_wdt_priv),
+ .flags = DM_FLAG_PRE_RELOC,
+};
+#endif
+#endif
diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c
index a7d4c7a..dafd2b5 100644
--- a/drivers/watchdog/mtk_wdt.c
+++ b/drivers/watchdog/mtk_wdt.c
@@ -70,9 +70,12 @@
return 0;
}
-static void mtk_wdt_set_timeout(struct udevice *dev, unsigned int timeout_ms)
+static void mtk_wdt_set_timeout(struct udevice *dev, u64 timeout_ms)
{
struct mtk_wdt_priv *priv = dev_get_priv(dev);
+ u64 timeout_us;
+ u32 timeout_cc;
+ u32 length;
/*
* One WDT_LENGTH count is 512 ticks of the wdt clock
@@ -88,21 +91,25 @@
* The MediaTek docs lack details to know if this is the case here.
* So we enforce a minimum of 1 to guarantee operation.
*/
- if(timeout_ms > 15984) timeout_ms = 15984;
- u64 timeout_us = timeout_ms * 1000;
- u32 timeout_cc = (u32) ( (15624 + timeout_us) / 15625 );
- if(timeout_cc == 0) timeout_cc = 1;
- u32 length = WDT_LENGTH_TIMEOUT(timeout_cc) | WDT_LENGTH_KEY;
+ if (timeout_ms > 15984)
+ timeout_ms = 15984;
+
+ timeout_us = timeout_ms * 1000;
+ timeout_cc = (15624 + timeout_us) / 15625;
+ if (timeout_cc == 0)
+ timeout_cc = 1;
+
+ length = WDT_LENGTH_TIMEOUT(timeout_cc) | WDT_LENGTH_KEY;
writel(length, priv->base + MTK_WDT_LENGTH);
}
-static int mtk_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
+static int mtk_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
{
struct mtk_wdt_priv *priv = dev_get_priv(dev);
- mtk_wdt_set_timeout(dev, timeout);
+ mtk_wdt_set_timeout(dev, timeout_ms);
- mtk_wdt_reset(dev);
+ mtk_wdt_reset(dev);
/* Enable watchdog reset signal */
setbits_le32(priv->base + MTK_WDT_MODE,
diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c
index 343adb0..284cfbb 100644
--- a/drivers/watchdog/omap_wdt.c
+++ b/drivers/watchdog/omap_wdt.c
@@ -42,10 +42,14 @@
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/arch/cpu.h>
+#include <wdt.h>
+#include <dm.h>
+#include <errno.h>
/* Hardware timeout in seconds */
#define WDT_HW_TIMEOUT 60
+#if !CONFIG_IS_ENABLED(WDT)
static unsigned int wdt_trgr_pattern = 0x1234;
void hw_watchdog_reset(void)
@@ -134,3 +138,120 @@
while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WSPR)
;
}
+
+void watchdog_reset(void)
+{
+ hw_watchdog_reset();
+}
+
+#else
+
+static int omap3_wdt_reset(struct udevice *dev)
+{
+ struct omap3_wdt_priv *priv = dev_get_priv(dev);
+
+/*
+ * Somebody just triggered watchdog reset and write to WTGR register
+ * is in progress. It is resetting right now, no need to trigger it
+ * again
+ */
+ if ((readl(&priv->regs->wdtwwps)) & WDT_WWPS_PEND_WTGR)
+ return 0;
+
+ priv->wdt_trgr_pattern = ~(priv->wdt_trgr_pattern);
+ writel(priv->wdt_trgr_pattern, &priv->regs->wdtwtgr);
+/*
+ * Don't wait for posted write to complete, i.e. don't check
+ * WDT_WWPS_PEND_WTGR bit in WWPS register. There is no writes to
+ * WTGR register outside of this func, and if entering it
+ * we see WDT_WWPS_PEND_WTGR bit set, it means watchdog reset
+ * was just triggered. This prevents us from wasting time in busy
+ * polling of WDT_WWPS_PEND_WTGR bit.
+ */
+ return 0;
+}
+
+static int omap3_wdt_stop(struct udevice *dev)
+{
+ struct omap3_wdt_priv *priv = dev_get_priv(dev);
+
+/* disable watchdog */
+ writel(0xAAAA, &priv->regs->wdtwspr);
+ while (readl(&priv->regs->wdtwwps) != 0x0)
+ ;
+ writel(0x5555, &priv->regs->wdtwspr);
+ while (readl(&priv->regs->wdtwwps) != 0x0)
+ ;
+ return 0;
+}
+
+static int omap3_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
+{
+ struct omap3_wdt_priv *priv = dev_get_priv(dev);
+ u32 pre_margin = GET_WLDR_VAL(timeout_ms);
+/*
+ * Make sure the watchdog is disabled. This is unfortunately required
+ * because writing to various registers with the watchdog running has no
+ * effect.
+ */
+ omap3_wdt_stop(dev);
+
+/* initialize prescaler */
+ while (readl(&priv->regs->wdtwwps) & WDT_WWPS_PEND_WCLR)
+ ;
+
+ writel(WDT_WCLR_PRE | (PTV << WDT_WCLR_PTV_OFF), &priv->regs->wdtwclr);
+ while (readl(&priv->regs->wdtwwps) & WDT_WWPS_PEND_WCLR)
+ ;
+/* just count up at 32 KHz */
+ while (readl(&priv->regs->wdtwwps) & WDT_WWPS_PEND_WLDR)
+ ;
+
+ writel(pre_margin, &priv->regs->wdtwldr);
+ while (readl(&priv->regs->wdtwwps) & WDT_WWPS_PEND_WLDR)
+ ;
+/* Sequence to enable the watchdog */
+ writel(0xBBBB, &priv->regs->wdtwspr);
+ while ((readl(&priv->regs->wdtwwps)) & WDT_WWPS_PEND_WSPR)
+ ;
+
+ writel(0x4444, &priv->regs->wdtwspr);
+ while ((readl(&priv->regs->wdtwwps)) & WDT_WWPS_PEND_WSPR)
+ ;
+
+ return 0;
+}
+
+static int omap3_wdt_probe(struct udevice *dev)
+{
+ struct omap3_wdt_priv *priv = dev_get_priv(dev);
+
+ priv->regs = (struct wd_timer *)devfdt_get_addr(dev);
+ if (!priv->regs)
+ return -EINVAL;
+
+ priv->wdt_trgr_pattern = 0x1234;
+ debug("%s: Probing wdt%u\n", __func__, dev->seq);
+ return 0;
+}
+
+static const struct wdt_ops omap3_wdt_ops = {
+ .start = omap3_wdt_start,
+ .stop = omap3_wdt_stop,
+ .reset = omap3_wdt_reset,
+};
+
+static const struct udevice_id omap3_wdt_ids[] = {
+ { .compatible = "ti,omap3-wdt" },
+ { }
+};
+
+U_BOOT_DRIVER(omap3_wdt) = {
+ .name = "omap3_wdt",
+ .id = UCLASS_WDT,
+ .of_match = omap3_wdt_ids,
+ .ops = &omap3_wdt_ops,
+ .probe = omap3_wdt_probe,
+ .priv_auto_alloc_size = sizeof(struct omap3_wdt_priv),
+};
+#endif /* !CONFIG_IS_ENABLED(WDT) */
diff --git a/drivers/watchdog/sp805_wdt.c b/drivers/watchdog/sp805_wdt.c
index 9661282..f1e781e 100644
--- a/drivers/watchdog/sp805_wdt.c
+++ b/drivers/watchdog/sp805_wdt.c
@@ -87,9 +87,16 @@
return 0;
}
+static int sp805_wdt_expire_now(struct udevice *dev, ulong flags)
+{
+ sp805_wdt_start(dev, 0, flags);
+
+ return 0;
+}
+
static int sp805_wdt_probe(struct udevice *dev)
{
- debug("%s: Probing wdt%u\n", __func__, dev->seq);
+ debug("%s: Probing wdt%u (sp805-wdt)\n", __func__, dev->seq);
return 0;
}
@@ -109,6 +116,7 @@
.start = sp805_wdt_start,
.reset = sp805_wdt_reset,
.stop = sp805_wdt_stop,
+ .expire_now = sp805_wdt_expire_now,
};
static const struct udevice_id sp805_wdt_ids[] = {
diff --git a/env/Kconfig b/env/Kconfig
index e326f5f..e6ae1fe 100644
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -495,34 +495,36 @@
It's a string of the EXT4 file name. This file use to store the
environment (explicit path to the file)
-if ARCH_ROCKCHIP || ARCH_SUNXI || ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARC || ARCH_STM32MP
+if ARCH_ROCKCHIP || ARCH_SUNXI || ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARC || ARCH_STM32MP || ARCH_OMAP2PLUS || ARCH_AT91
config ENV_OFFSET
hex "Environment Offset"
- depends on !ENV_IS_IN_UBI
- depends on !ENV_IS_NOWHERE
+ depends on (!ENV_IS_IN_UBI && !ENV_IS_NOWHERE) || ARCH_STM32MP
default 0x3f8000 if ARCH_ROCKCHIP
default 0x88000 if ARCH_SUNXI
default 0xE0000 if ARCH_ZYNQ
default 0x1E00000 if ARCH_ZYNQMP
default 0 if ARC
+ default 0x140000 if ARCH_AT91
+ default 0x260000 if ARCH_OMAP2PLUS
help
Offset from the start of the device (or partition)
config ENV_SIZE
hex "Environment Size"
default 0x40000 if ENV_IS_IN_SPI_FLASH && ARCH_ZYNQMP
- default 0x20000 if ARCH_SUNXI || ARCH_ZYNQ
+ default 0x20000 if ARCH_SUNXI || ARCH_ZYNQ || ARCH_OMAP2PLUS || ARCH_AT91
default 0x8000 if ARCH_ROCKCHIP || ARCH_ZYNQMP || ARCH_VERSAL
default 0x4000 if ARC
+ default 0x1f000
help
Size of the environment storage area
config ENV_SECT_SIZE
hex "Environment Sector-Size"
- depends on !ENV_IS_NOWHERE && (ARCH_ZYNQ || ARCH_ZYNQMP)
+ depends on (!ENV_IS_NOWHERE && (ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_OMAP2PLUS || ARCH_AT91) )|| ARCH_STM32MP
default 0x40000 if ARCH_ZYNQMP
- default 0x20000 if ARCH_ZYNQ
+ default 0x20000 if ARCH_ZYNQ || ARCH_OMAP2PLUS || ARCH_AT91
help
Size of the sector containing the environment.
@@ -538,6 +540,19 @@
help
Name of the volume that you want to store the environment in.
+config ENV_UBI_VOLUME_REDUND
+ string "UBI redundant volume name"
+ depends on ENV_IS_IN_UBI
+ help
+ Name of the redundant volume that you want to store the environment in.
+
+config ENV_UBI_VID_OFFSET
+ int "ubi environment VID offset"
+ depends on ENV_IS_IN_UBI
+ default 0
+ help
+ UBI VID offset for environment. If 0, no custom VID offset is used.
+
endif
config USE_DEFAULT_ENV_FILE
diff --git a/env/callback.c b/env/callback.c
index 54d2de4..f0904cf 100644
--- a/env/callback.c
+++ b/env/callback.c
@@ -5,7 +5,8 @@
*/
#include <common.h>
-#include <environment.h>
+#include <env.h>
+#include <env_internal.h>
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
DECLARE_GLOBAL_DATA_PTR;
@@ -42,7 +43,7 @@
* This is called specifically when the variable did not exist in the hash
* previously, so the blanket update did not find this variable.
*/
-void env_callback_init(ENTRY *var_entry)
+void env_callback_init(struct env_entry *var_entry)
{
const char *var_name = var_entry->key;
char callback_name[256] = "";
@@ -79,7 +80,7 @@
* Called on each existing env var prior to the blanket update since removing
* a callback association should remove its callback.
*/
-static int clear_callback(ENTRY *entry)
+static int clear_callback(struct env_entry *entry)
{
entry->callback = NULL;
@@ -91,13 +92,13 @@
*/
static int set_callback(const char *name, const char *value, void *priv)
{
- ENTRY e, *ep;
+ struct env_entry e, *ep;
struct env_clbk_tbl *clbkp;
e.key = name;
e.data = NULL;
e.callback = NULL;
- hsearch_r(e, FIND, &ep, &env_htab, 0);
+ hsearch_r(e, ENV_FIND, &ep, &env_htab, 0);
/* does the env variable actually exist? */
if (ep != NULL) {
diff --git a/env/common.c b/env/common.c
index bd340fe..4daaa6f 100644
--- a/env/common.c
+++ b/env/common.c
@@ -9,7 +9,8 @@
#include <common.h>
#include <command.h>
-#include <environment.h>
+#include <env.h>
+#include <env_internal.h>
#include <linux/stddef.h>
#include <search.h>
#include <errno.h>
@@ -23,10 +24,7 @@
#include <env_default.h>
struct hsearch_data env_htab = {
-#if CONFIG_IS_ENABLED(ENV_SUPPORT)
- /* defined in flags.c, only compile with ENV_SUPPORT */
.change_ok = env_flags_validate,
-#endif
};
/*
@@ -61,7 +59,7 @@
return ret_val;
}
-void set_default_env(const char *s, int flags)
+void env_set_default(const char *s, int flags)
{
if (sizeof(default_environment) > ENV_SIZE) {
puts("*** Error - default environment is too large\n\n");
@@ -91,7 +89,7 @@
/* [re]set individual variables to their value in the default environment */
-int set_default_vars(int nvars, char * const vars[], int flags)
+int env_set_default_vars(int nvars, char * const vars[], int flags)
{
/*
* Special use-case: import from default environment
@@ -117,7 +115,7 @@
memcpy(&crc, &ep->crc, sizeof(crc));
if (crc32(0, ep->data, ENV_SIZE) != crc) {
- set_default_env("bad CRC", 0);
+ env_set_default("bad CRC", 0);
return -ENOMSG; /* needed for env_load() */
}
}
@@ -130,7 +128,7 @@
pr_err("Cannot import environment: errno = %d\n", errno);
- set_default_env("import failed", 0);
+ env_set_default("import failed", 0);
return -EIO;
}
@@ -155,7 +153,7 @@
}
if (buf1_read_fail && buf2_read_fail) {
- set_default_env("bad env area", 0);
+ env_set_default("bad env area", 0);
return -EIO;
} else if (!buf1_read_fail && buf2_read_fail) {
gd->env_valid = ENV_VALID;
@@ -171,7 +169,7 @@
tmp_env2->crc;
if (!crc1_ok && !crc2_ok) {
- set_default_env("bad CRC", 0);
+ env_set_default("bad CRC", 0);
return -ENOMSG; /* needed for env_load() */
} else if (crc1_ok && !crc2_ok) {
gd->env_valid = ENV_VALID;
@@ -228,17 +226,15 @@
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
env_reloc();
env_fix_drivers();
-
- if (env_htab.change_ok)
- env_htab.change_ok += gd->reloc_off;
+ env_htab.change_ok += gd->reloc_off;
#endif
if (gd->env_valid == ENV_INVALID) {
#if defined(CONFIG_ENV_IS_NOWHERE) || defined(CONFIG_SPL_BUILD)
/* Environment not changable */
- set_default_env(NULL, 0);
+ env_set_default(NULL, 0);
#else
bootstage_error(BOOTSTAGE_ID_NET_CHECKSUM);
- set_default_env("bad CRC", 0);
+ env_set_default("bad CRC", 0);
#endif
} else {
env_load();
@@ -249,7 +245,7 @@
int env_complete(char *var, int maxv, char *cmdv[], int bufsz, char *buf,
bool dollar_comp)
{
- ENTRY *match;
+ struct env_entry *match;
int found, idx;
if (dollar_comp) {
diff --git a/env/eeprom.c b/env/eeprom.c
index ac2689c..cb04d2a 100644
--- a/env/eeprom.c
+++ b/env/eeprom.c
@@ -9,7 +9,8 @@
#include <common.h>
#include <command.h>
-#include <environment.h>
+#include <env.h>
+#include <env_internal.h>
#include <linux/stddef.h>
#if defined(CONFIG_I2C_ENV_EEPROM_BUS)
#include <i2c.h>
@@ -131,9 +132,11 @@
gd->env_valid = ENV_REDUND;
} else {
/* both ok - check serial */
- if (flags[0] == ACTIVE_FLAG && flags[1] == OBSOLETE_FLAG)
+ if (flags[0] == ENV_REDUND_ACTIVE &&
+ flags[1] == ENV_REDUND_OBSOLETE)
gd->env_valid = ENV_VALID;
- else if (flags[0] == OBSOLETE_FLAG && flags[1] == ACTIVE_FLAG)
+ else if (flags[0] == ENV_REDUND_OBSOLETE &&
+ flags[1] == ENV_REDUND_ACTIVE)
gd->env_valid = ENV_REDUND;
else if (flags[0] == 0xFF && flags[1] == 0)
gd->env_valid = ENV_REDUND;
@@ -193,7 +196,7 @@
unsigned int off = CONFIG_ENV_OFFSET;
#ifdef CONFIG_ENV_OFFSET_REDUND
unsigned int off_red = CONFIG_ENV_OFFSET_REDUND;
- char flag_obsolete = OBSOLETE_FLAG;
+ char flag_obsolete = ENV_REDUND_OBSOLETE;
#endif
rc = env_export(&env_new);
@@ -206,7 +209,7 @@
off_red = CONFIG_ENV_OFFSET;
}
- env_new.flags = ACTIVE_FLAG;
+ env_new.flags = ENV_REDUND_ACTIVE;
#endif
rc = eeprom_bus_write(CONFIG_SYS_DEF_EEPROM_ADDR,
diff --git a/env/embedded.c b/env/embedded.c
index b1090e9..a38e169 100644
--- a/env/embedded.c
+++ b/env/embedded.c
@@ -12,7 +12,7 @@
#define __ASM_STUB_PROCESSOR_H__ /* don't include asm/processor. */
#include <config.h>
#undef __ASSEMBLY__
-#include <environment.h>
+#include <env_internal.h>
#include <linux/stringify.h>
/* Handle HOSTS that have prepended crap on symbol names, not TARGETS. */
diff --git a/env/env.c b/env/env.c
index b844828..7c1a9ac 100644
--- a/env/env.c
+++ b/env/env.c
@@ -5,7 +5,8 @@
*/
#include <common.h>
-#include <environment.h>
+#include <env.h>
+#include <env_internal.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -24,6 +25,8 @@
entry->load += gd->reloc_off;
if (entry->save)
entry->save += gd->reloc_off;
+ if (entry->erase)
+ entry->erase += gd->reloc_off;
if (entry->init)
entry->init += gd->reloc_off;
}
@@ -69,7 +72,7 @@
ENVL_NVRAM,
#endif
#ifdef CONFIG_ENV_IS_IN_RAW_DISK
- ENVL_RAW_DISK,
+ ENVL_RAW_DISK,
#endif
#ifdef CONFIG_ENV_IS_IN_REMOTE
ENVL_REMOTE,
@@ -257,6 +260,34 @@
return -ENODEV;
}
+int env_erase(void)
+{
+ struct env_driver *drv;
+
+ drv = env_driver_lookup(ENVOP_ERASE, gd->env_load_prio);
+ if (drv) {
+ int ret;
+
+ if (!drv->erase)
+ return -ENODEV;
+
+ if (!env_has_inited(drv->location))
+ return -ENODEV;
+
+ printf("Erasing Environment on %s... ", drv->name);
+ ret = drv->erase();
+ if (ret)
+ printf("Failed (%d)\n", ret);
+ else
+ printf("OK\n");
+
+ if (!ret)
+ return 0;
+ }
+
+ return -ENODEV;
+}
+
int env_init(void)
{
struct env_driver *drv;
diff --git a/env/ext4.c b/env/ext4.c
index 9947381..1f6b1b5 100644
--- a/env/ext4.c
+++ b/env/ext4.c
@@ -21,7 +21,8 @@
#include <common.h>
#include <command.h>
-#include <environment.h>
+#include <env.h>
+#include <env_internal.h>
#include <linux/stddef.h>
#include <malloc.h>
#include <memalign.h>
@@ -127,7 +128,7 @@
return env_import(buf, 1);
err_env_relocate:
- set_default_env(NULL, 0);
+ env_set_default(NULL, 0);
return -EIO;
}
diff --git a/env/fat.c b/env/fat.c
index 7f74c64..1836556 100644
--- a/env/fat.c
+++ b/env/fat.c
@@ -9,7 +9,8 @@
#include <common.h>
#include <command.h>
-#include <environment.h>
+#include <env.h>
+#include <env_internal.h>
#include <linux/stddef.h>
#include <malloc.h>
#include <memalign.h>
@@ -122,7 +123,7 @@
return env_import(buf, 1);
err_env_relocate:
- set_default_env(NULL, 0);
+ env_set_default(NULL, 0);
return -EIO;
}
diff --git a/env/flags.c b/env/flags.c
index 79dccc0..418d6cc 100644
--- a/env/flags.c
+++ b/env/flags.c
@@ -4,6 +4,7 @@
* Joe Hershberger, National Instruments, joe.hershberger@ni.com
*/
+#include <env.h>
#include <linux/string.h>
#include <linux/ctype.h>
@@ -18,7 +19,7 @@
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
#else
#include <common.h>
-#include <environment.h>
+#include <env_internal.h>
#endif
#ifdef CONFIG_CMD_NET
@@ -418,7 +419,7 @@
* This is called specifically when the variable did not exist in the hash
* previously, so the blanket update did not find this variable.
*/
-void env_flags_init(ENTRY *var_entry)
+void env_flags_init(struct env_entry *var_entry)
{
const char *var_name = var_entry->key;
char flags[ENV_FLAGS_ATTR_MAX_LEN + 1] = "";
@@ -440,7 +441,7 @@
* Called on each existing env var prior to the blanket update since removing
* a flag in the flag list should remove its flags.
*/
-static int clear_flags(ENTRY *entry)
+static int clear_flags(struct env_entry *entry)
{
entry->flags = 0;
@@ -452,12 +453,12 @@
*/
static int set_flags(const char *name, const char *value, void *priv)
{
- ENTRY e, *ep;
+ struct env_entry e, *ep;
e.key = name;
e.data = NULL;
e.callback = NULL;
- hsearch_r(e, FIND, &ep, &env_htab, 0);
+ hsearch_r(e, ENV_FIND, &ep, &env_htab, 0);
/* does the env variable actually exist? */
if (ep != NULL) {
@@ -495,8 +496,8 @@
* overwriting of write-once variables.
*/
-int env_flags_validate(const ENTRY *item, const char *newval, enum env_op op,
- int flag)
+int env_flags_validate(const struct env_entry *item, const char *newval,
+ enum env_op op, int flag)
{
const char *name;
const char *oldval = NULL;
diff --git a/env/flash.c b/env/flash.c
index dca6567..231a5fd 100644
--- a/env/flash.c
+++ b/env/flash.c
@@ -11,7 +11,8 @@
#include <common.h>
#include <command.h>
-#include <environment.h>
+#include <env.h>
+#include <env_internal.h>
#include <linux/stddef.h>
#include <malloc.h>
#include <search.h>
@@ -47,7 +48,7 @@
#if defined(CONFIG_ENV_ADDR_REDUND) && defined(CMD_SAVEENV) || \
!defined(CONFIG_ENV_ADDR_REDUND) && defined(INITENV)
#ifdef ENV_IS_EMBEDDED
-static env_t *env_ptr = &environment;
+static env_t *env_ptr = &embedded_environment;
#else /* ! ENV_IS_EMBEDDED */
static env_t *env_ptr = (env_t *)CONFIG_ENV_ADDR;
@@ -94,10 +95,12 @@
} else if (!crc1_ok && !crc2_ok) {
gd->env_addr = addr_default;
gd->env_valid = ENV_INVALID;
- } else if (flag1 == ACTIVE_FLAG && flag2 == OBSOLETE_FLAG) {
+ } else if (flag1 == ENV_REDUND_ACTIVE &&
+ flag2 == ENV_REDUND_OBSOLETE) {
gd->env_addr = addr1;
gd->env_valid = ENV_VALID;
- } else if (flag1 == OBSOLETE_FLAG && flag2 == ACTIVE_FLAG) {
+ } else if (flag1 == ENV_REDUND_OBSOLETE &&
+ flag2 == ENV_REDUND_ACTIVE) {
gd->env_addr = addr2;
gd->env_valid = ENV_VALID;
} else if (flag1 == flag2) {
@@ -120,7 +123,7 @@
{
env_t env_new;
char *saved_data = NULL;
- char flag = OBSOLETE_FLAG, new_flag = ACTIVE_FLAG;
+ char flag = ENV_REDUND_OBSOLETE, new_flag = ENV_REDUND_ACTIVE;
int rc = 1;
#if CONFIG_ENV_SECT_SIZE > CONFIG_ENV_SIZE
ulong up_data = 0;
@@ -321,9 +324,9 @@
end_addr_new = ltmp;
}
- if (flash_addr_new->flags != OBSOLETE_FLAG &&
+ if (flash_addr_new->flags != ENV_REDUND_OBSOLETE &&
crc32(0, flash_addr_new->data, ENV_SIZE) == flash_addr_new->crc) {
- char flag = OBSOLETE_FLAG;
+ char flag = ENV_REDUND_OBSOLETE;
gd->env_valid = ENV_REDUND;
flash_sect_protect(0, (ulong)flash_addr_new, end_addr_new);
@@ -333,9 +336,9 @@
flash_sect_protect(1, (ulong)flash_addr_new, end_addr_new);
}
- if (flash_addr->flags != ACTIVE_FLAG &&
- (flash_addr->flags & ACTIVE_FLAG) == ACTIVE_FLAG) {
- char flag = ACTIVE_FLAG;
+ if (flash_addr->flags != ENV_REDUND_ACTIVE &&
+ (flash_addr->flags & ENV_REDUND_ACTIVE) == ENV_REDUND_ACTIVE) {
+ char flag = ENV_REDUND_ACTIVE;
gd->env_valid = ENV_REDUND;
flash_sect_protect(0, (ulong)flash_addr, end_addr);
diff --git a/env/mmc.c b/env/mmc.c
index c3cf35d..9f1878d 100644
--- a/env/mmc.c
+++ b/env/mmc.c
@@ -8,7 +8,8 @@
#include <common.h>
#include <command.h>
-#include <environment.h>
+#include <env.h>
+#include <env_internal.h>
#include <fdtdec.h>
#include <linux/stddef.h>
#include <malloc.h>
@@ -242,6 +243,54 @@
fini_mmc_for_env(mmc);
return ret;
}
+
+#if defined(CONFIG_CMD_ERASEENV)
+static inline int erase_env(struct mmc *mmc, unsigned long size,
+ unsigned long offset)
+{
+ uint blk_start, blk_cnt, n;
+ struct blk_desc *desc = mmc_get_blk_desc(mmc);
+
+ blk_start = ALIGN(offset, mmc->write_bl_len) / mmc->write_bl_len;
+ blk_cnt = ALIGN(size, mmc->write_bl_len) / mmc->write_bl_len;
+
+ n = blk_derase(desc, blk_start, blk_cnt);
+ printf("%d blocks erased: %s\n", n, (n == blk_cnt) ? "OK" : "ERROR");
+
+ return (n == blk_cnt) ? 0 : 1;
+}
+
+static int env_mmc_erase(void)
+{
+ int dev = mmc_get_env_dev();
+ struct mmc *mmc = find_mmc_device(dev);
+ int ret, copy = 0;
+ u32 offset;
+ const char *errmsg;
+
+ errmsg = init_mmc_for_env(mmc);
+ if (errmsg) {
+ printf("%s\n", errmsg);
+ return 1;
+ }
+
+ if (mmc_get_env_addr(mmc, copy, &offset))
+ return CMD_RET_FAILURE;
+
+ ret = erase_env(mmc, CONFIG_ENV_SIZE, offset);
+
+#ifdef CONFIG_ENV_OFFSET_REDUND
+ copy = 1;
+
+ if (mmc_get_env_addr(mmc, copy, &offset))
+ return CMD_RET_FAILURE;
+
+ ret |= erase_env(mmc, CONFIG_ENV_SIZE, offset);
+#endif
+
+ return ret;
+}
+#endif /* CONFIG_CMD_ERASEENV */
#endif /* CONFIG_CMD_SAVEENV && !CONFIG_SPL_BUILD */
static inline int read_env(struct mmc *mmc, unsigned long size,
@@ -298,7 +347,7 @@
fini_mmc_for_env(mmc);
err:
if (ret)
- set_default_env(errmsg, 0);
+ env_set_default(errmsg, 0);
#endif
return ret;
@@ -339,7 +388,7 @@
fini_mmc_for_env(mmc);
err:
if (ret)
- set_default_env(errmsg, 0);
+ env_set_default(errmsg, 0);
#endif
return ret;
}
@@ -351,5 +400,8 @@
.load = env_mmc_load,
#ifndef CONFIG_SPL_BUILD
.save = env_save_ptr(env_mmc_save),
+#if defined(CONFIG_CMD_ERASEENV)
+ .erase = env_mmc_erase,
+#endif
#endif
};
diff --git a/env/nand.c b/env/nand.c
index d0b95f4..9f3dc63 100644
--- a/env/nand.c
+++ b/env/nand.c
@@ -15,7 +15,8 @@
#include <common.h>
#include <command.h>
-#include <environment.h>
+#include <env.h>
+#include <env_internal.h>
#include <linux/stddef.h>
#include <malloc.h>
#include <memalign.h>
@@ -325,7 +326,7 @@
tmp_env2 = (env_t *)malloc(CONFIG_ENV_SIZE);
if (tmp_env1 == NULL || tmp_env2 == NULL) {
puts("Can't allocate buffers for environment\n");
- set_default_env("malloc() failed", 0);
+ env_set_default("malloc() failed", 0);
ret = -EIO;
goto done;
}
@@ -364,14 +365,14 @@
if (mtd && !get_nand_env_oob(mtd, &nand_env_oob_offset)) {
printf("Found Environment offset in OOB..\n");
} else {
- set_default_env("no env offset in OOB", 0);
+ env_set_default("no env offset in OOB", 0);
return;
}
#endif
ret = readenv(CONFIG_ENV_OFFSET, (u_char *)buf);
if (ret) {
- set_default_env("readenv() failed", 0);
+ env_set_default("readenv() failed", 0);
return -EIO;
}
diff --git a/env/nowhere.c b/env/nowhere.c
index ea6c32e..f5b0a17 100644
--- a/env/nowhere.c
+++ b/env/nowhere.c
@@ -9,7 +9,8 @@
#include <common.h>
#include <command.h>
-#include <environment.h>
+#include <env.h>
+#include <env_internal.h>
#include <linux/stddef.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/env/nvram.c b/env/nvram.c
index df1b379..79201bd 100644
--- a/env/nvram.c
+++ b/env/nvram.c
@@ -25,7 +25,8 @@
#include <common.h>
#include <command.h>
-#include <environment.h>
+#include <env.h>
+#include <env_internal.h>
#include <linux/stddef.h>
#include <search.h>
#include <errno.h>
diff --git a/env/onenand.c b/env/onenand.c
index d371bd7..dfd4e93 100644
--- a/env/onenand.c
+++ b/env/onenand.c
@@ -9,7 +9,7 @@
#include <common.h>
#include <command.h>
-#include <environment.h>
+#include <env_internal.h>
#include <linux/stddef.h>
#include <malloc.h>
#include <search.h>
diff --git a/env/remote.c b/env/remote.c
index b1a7d1a..02531f4 100644
--- a/env/remote.c
+++ b/env/remote.c
@@ -7,7 +7,7 @@
#include <common.h>
#include <command.h>
-#include <environment.h>
+#include <env_internal.h>
#include <linux/stddef.h>
#ifdef ENV_IS_EMBEDDED
diff --git a/env/sata.c b/env/sata.c
index a2ff5c6..9369710 100644
--- a/env/sata.c
+++ b/env/sata.c
@@ -8,7 +8,8 @@
#include <common.h>
#include <command.h>
-#include <environment.h>
+#include <env.h>
+#include <env_internal.h>
#include <linux/stddef.h>
#include <errno.h>
#include <memalign.h>
@@ -106,7 +107,7 @@
}
if (read_env(sata, CONFIG_ENV_SIZE, CONFIG_ENV_OFFSET, buf)) {
- set_default_env(NULL, 0);
+ env_set_default(NULL, 0);
return -EIO;
}
diff --git a/env/sf.c b/env/sf.c
index 4f92ae0..590d0ce 100644
--- a/env/sf.c
+++ b/env/sf.c
@@ -10,7 +10,8 @@
*/
#include <common.h>
#include <dm.h>
-#include <environment.h>
+#include <env.h>
+#include <env_internal.h>
#include <malloc.h>
#include <spi.h>
#include <spi_flash.h>
@@ -29,8 +30,6 @@
static ulong env_new_offset = CONFIG_ENV_OFFSET_REDUND;
#endif
-#define ACTIVE_FLAG 1
-#define OBSOLETE_FLAG 0
#endif /* CONFIG_ENV_OFFSET_REDUND */
DECLARE_GLOBAL_DATA_PTR;
@@ -48,7 +47,7 @@
CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE,
&new);
if (ret) {
- set_default_env("spi_flash_probe_bus_cs() failed", 0);
+ env_set_default("spi_flash_probe_bus_cs() failed", 0);
return ret;
}
@@ -60,7 +59,7 @@
CONFIG_ENV_SPI_CS,
CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
if (!env_flash) {
- set_default_env("spi_flash_probe() failed", 0);
+ env_set_default("spi_flash_probe() failed", 0);
return -EIO;
}
}
@@ -73,7 +72,7 @@
static int env_sf_save(void)
{
env_t env_new;
- char *saved_buffer = NULL, flag = OBSOLETE_FLAG;
+ char *saved_buffer = NULL, flag = ENV_REDUND_OBSOLETE;
u32 saved_size, saved_offset, sector;
int ret;
@@ -84,7 +83,7 @@
ret = env_export(&env_new);
if (ret)
return -EIO;
- env_new.flags = ACTIVE_FLAG;
+ env_new.flags = ENV_REDUND_ACTIVE;
if (gd->env_valid == ENV_VALID) {
env_new_offset = CONFIG_ENV_OFFSET_REDUND;
@@ -161,7 +160,7 @@
tmp_env2 = (env_t *)memalign(ARCH_DMA_MINALIGN,
CONFIG_ENV_SIZE);
if (!tmp_env1 || !tmp_env2) {
- set_default_env("malloc() failed", 0);
+ env_set_default("malloc() failed", 0);
ret = -EIO;
goto out;
}
@@ -256,7 +255,7 @@
buf = (char *)memalign(ARCH_DMA_MINALIGN, CONFIG_ENV_SIZE);
if (!buf) {
- set_default_env("malloc() failed", 0);
+ env_set_default("malloc() failed", 0);
return -EIO;
}
@@ -267,7 +266,7 @@
ret = spi_flash_read(env_flash,
CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, buf);
if (ret) {
- set_default_env("spi_flash_read() failed", 0);
+ env_set_default("spi_flash_read() failed", 0);
goto err_read;
}
diff --git a/env/ubi.c b/env/ubi.c
index 1dfdf0a..08aac47 100644
--- a/env/ubi.c
+++ b/env/ubi.c
@@ -7,7 +7,8 @@
#include <common.h>
#include <command.h>
-#include <environment.h>
+#include <env.h>
+#include <env_internal.h>
#include <errno.h>
#include <malloc.h>
#include <memalign.h>
@@ -15,6 +16,15 @@
#include <ubi_uboot.h>
#undef crc32
+#define _QUOTE(x) #x
+#define QUOTE(x) _QUOTE(x)
+
+#if (CONFIG_ENV_UBI_VID_OFFSET == 0)
+ #define UBI_VID_OFFSET NULL
+#else
+ #define UBI_VID_OFFSET QUOTE(CONFIG_ENV_UBI_VID_OFFSET)
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_CMD_SAVEENV
@@ -28,7 +38,7 @@
if (ret)
return ret;
- if (ubi_part(CONFIG_ENV_UBI_PART, NULL)) {
+ if (ubi_part(CONFIG_ENV_UBI_PART, UBI_VID_OFFSET)) {
printf("\n** Cannot find mtd partition \"%s\"\n",
CONFIG_ENV_UBI_PART);
return 1;
@@ -70,7 +80,7 @@
if (ret)
return ret;
- if (ubi_part(CONFIG_ENV_UBI_PART, NULL)) {
+ if (ubi_part(CONFIG_ENV_UBI_PART, UBI_VID_OFFSET)) {
printf("\n** Cannot find mtd partition \"%s\"\n",
CONFIG_ENV_UBI_PART);
return 1;
@@ -111,10 +121,10 @@
tmp_env1 = (env_t *)env1_buf;
tmp_env2 = (env_t *)env2_buf;
- if (ubi_part(CONFIG_ENV_UBI_PART, NULL)) {
+ if (ubi_part(CONFIG_ENV_UBI_PART, UBI_VID_OFFSET)) {
printf("\n** Cannot find mtd partition \"%s\"\n",
CONFIG_ENV_UBI_PART);
- set_default_env(NULL, 0);
+ env_set_default(NULL, 0);
return -EIO;
}
@@ -148,17 +158,17 @@
*/
memset(buf, 0x0, CONFIG_ENV_SIZE);
- if (ubi_part(CONFIG_ENV_UBI_PART, NULL)) {
+ if (ubi_part(CONFIG_ENV_UBI_PART, UBI_VID_OFFSET)) {
printf("\n** Cannot find mtd partition \"%s\"\n",
CONFIG_ENV_UBI_PART);
- set_default_env(NULL, 0);
+ env_set_default(NULL, 0);
return -EIO;
}
if (ubi_volume_read(CONFIG_ENV_UBI_VOLUME, buf, CONFIG_ENV_SIZE)) {
printf("\n** Unable to read env from %s:%s **\n",
CONFIG_ENV_UBI_PART, CONFIG_ENV_UBI_VOLUME);
- set_default_env(NULL, 0);
+ env_set_default(NULL, 0);
return -EIO;
}
diff --git a/examples/api/demo.c b/examples/api/demo.c
index e177bf1..e752378 100644
--- a/examples/api/demo.c
+++ b/examples/api/demo.c
@@ -6,6 +6,7 @@
*/
#include <common.h>
+#include <env.h>
#include <linux/types.h>
#include <api_public.h>
diff --git a/examples/api/glue.c b/examples/api/glue.c
index 9c8ed8d..4086616 100644
--- a/examples/api/glue.c
+++ b/examples/api/glue.c
@@ -4,6 +4,7 @@
*/
#include <common.h>
+#include <env.h>
#include <linux/types.h>
#include <api_public.h>
@@ -365,7 +366,7 @@
/*
* It's OK to pass only the name piece as last (and not the whole
- * 'name=val' string), since the API_ENUM_ENV call uses envmatch()
+ * 'name=val' string), since the API_ENUM_ENV call uses env_match()
* internally, which handles such case
*/
if (!syscall(API_ENV_ENUM, NULL, last, &env))
diff --git a/fs/Makefile b/fs/Makefile
index 2ed4aea..42e669c 100644
--- a/fs/Makefile
+++ b/fs/Makefile
@@ -8,6 +8,7 @@
obj-$(CONFIG_FS_LOADER) += fs.o
obj-$(CONFIG_SPL_FS_FAT) += fat/
obj-$(CONFIG_SPL_FS_EXT4) += ext4/
+obj-$(CONFIG_SPL_FS_CBFS) += cbfs/
else
obj-y += fs.o
diff --git a/fs/cbfs/Kconfig b/fs/cbfs/Kconfig
index 1608954..03980d8 100644
--- a/fs/cbfs/Kconfig
+++ b/fs/cbfs/Kconfig
@@ -6,3 +6,15 @@
on systems that use coreboot as the first boot-loader and then load
U-Boot to actually boot the Operating System. You can also enable
CMD_CBFS to get command-line access.
+
+config SPL_FS_CBFS
+ bool "Enable CBFS (Coreboot Filesystem) in SPL"
+ help
+ Define this to enable support for reading from a Coreboot
+ filesystem. This is a ROM-based filesystem used for accessing files
+ on systems that use coreboot as the first boot-loader and then load
+ U-Boot to actually boot the Operating System.
+
+ Note that most functions in the CBFS API do not work with SPL. Only
+ those which accept a cbfs_priv * can be used, since BSS is not
+ available.
diff --git a/fs/cbfs/cbfs.c b/fs/cbfs/cbfs.c
index 7b2513c..1aa6f8e 100644
--- a/fs/cbfs/cbfs.c
+++ b/fs/cbfs/cbfs.c
@@ -8,11 +8,21 @@
#include <malloc.h>
#include <asm/byteorder.h>
-enum cbfs_result file_cbfs_result;
+static const u32 good_magic = 0x4f524243;
+static const u8 good_file_magic[] = "LARCHIVE";
+
+struct cbfs_priv {
+ int initialized;
+ struct cbfs_header header;
+ struct cbfs_cachenode *file_cache;
+ enum cbfs_result result;
+};
+
+static struct cbfs_priv cbfs_s;
const char *file_cbfs_error(void)
{
- switch (file_cbfs_result) {
+ switch (cbfs_s.result) {
case CBFS_SUCCESS:
return "Success";
case CBFS_NOT_INITIALIZED:
@@ -28,14 +38,10 @@
}
}
-
-static const u32 good_magic = 0x4f524243;
-static const u8 good_file_magic[] = "LARCHIVE";
-
-
-static int initialized;
-static struct cbfs_header cbfs_header;
-static struct cbfs_cachenode *file_cache;
+enum cbfs_result cbfs_get_result(void)
+{
+ return cbfs_s.result;
+}
/* Do endian conversion on the CBFS header structure. */
static void swap_header(struct cbfs_header *dest, struct cbfs_header *src)
@@ -55,7 +61,7 @@
memcpy(&dest->magic, &src->magic, sizeof(dest->magic));
dest->len = be32_to_cpu(src->len);
dest->type = be32_to_cpu(src->type);
- dest->checksum = be32_to_cpu(src->checksum);
+ dest->attributes_offset = be32_to_cpu(src->attributes_offset);
dest->offset = be32_to_cpu(src->offset);
}
@@ -67,48 +73,49 @@
* @param start The location in memory to start from.
* @param size The size of the memory region to search.
* @param align The alignment boundaries to check on.
- * @param newNode A pointer to the file structure to load.
+ * @param new_node A pointer to the file structure to load.
* @param used A pointer to the count of of bytes scanned through,
* including the file if one is found.
*
* @return 1 if a file is found, 0 if one isn't.
*/
-static int file_cbfs_next_file(u8 *start, u32 size, u32 align,
- struct cbfs_cachenode *newNode, u32 *used)
+static int file_cbfs_next_file(struct cbfs_priv *priv, u8 *start, u32 size,
+ u32 align, struct cbfs_cachenode *new_node,
+ u32 *used)
{
struct cbfs_fileheader header;
*used = 0;
while (size >= align) {
- const struct cbfs_fileheader *fileHeader =
+ const struct cbfs_fileheader *file_header =
(const struct cbfs_fileheader *)start;
u32 name_len;
u32 step;
/* Check if there's a file here. */
- if (memcmp(good_file_magic, &(fileHeader->magic),
- sizeof(fileHeader->magic))) {
+ if (memcmp(good_file_magic, &file_header->magic,
+ sizeof(file_header->magic))) {
*used += align;
size -= align;
start += align;
continue;
}
- swap_file_header(&header, fileHeader);
+ swap_file_header(&header, file_header);
if (header.offset < sizeof(struct cbfs_fileheader)) {
- file_cbfs_result = CBFS_BAD_FILE;
+ priv->result = CBFS_BAD_FILE;
return -1;
}
- newNode->next = NULL;
- newNode->type = header.type;
- newNode->data = start + header.offset;
- newNode->data_length = header.len;
+ new_node->next = NULL;
+ new_node->type = header.type;
+ new_node->data = start + header.offset;
+ new_node->data_length = header.len;
name_len = header.offset - sizeof(struct cbfs_fileheader);
- newNode->name = (char *)fileHeader +
+ new_node->name = (char *)file_header +
sizeof(struct cbfs_fileheader);
- newNode->name_length = name_len;
- newNode->checksum = header.checksum;
+ new_node->name_length = name_len;
+ new_node->attributes_offset = header.attributes_offset;
step = header.len;
if (step % align)
@@ -121,44 +128,45 @@
}
/* Look through a CBFS instance and copy file metadata into regular memory. */
-static void file_cbfs_fill_cache(u8 *start, u32 size, u32 align)
+static void file_cbfs_fill_cache(struct cbfs_priv *priv, u8 *start, u32 size,
+ u32 align)
{
struct cbfs_cachenode *cache_node;
- struct cbfs_cachenode *newNode;
- struct cbfs_cachenode **cache_tail = &file_cache;
+ struct cbfs_cachenode *new_node;
+ struct cbfs_cachenode **cache_tail = &priv->file_cache;
/* Clear out old information. */
- cache_node = file_cache;
+ cache_node = priv->file_cache;
while (cache_node) {
- struct cbfs_cachenode *oldNode = cache_node;
+ struct cbfs_cachenode *old_node = cache_node;
cache_node = cache_node->next;
- free(oldNode);
+ free(old_node);
}
- file_cache = NULL;
+ priv->file_cache = NULL;
while (size >= align) {
int result;
u32 used;
- newNode = (struct cbfs_cachenode *)
+ new_node = (struct cbfs_cachenode *)
malloc(sizeof(struct cbfs_cachenode));
- result = file_cbfs_next_file(start, size, align,
- newNode, &used);
+ result = file_cbfs_next_file(priv, start, size, align, new_node,
+ &used);
if (result < 0) {
- free(newNode);
+ free(new_node);
return;
} else if (result == 0) {
- free(newNode);
+ free(new_node);
break;
}
- *cache_tail = newNode;
- cache_tail = &newNode->next;
+ *cache_tail = new_node;
+ cache_tail = &new_node->next;
size -= used;
start += used;
}
- file_cbfs_result = CBFS_SUCCESS;
+ priv->result = CBFS_SUCCESS;
}
/* Get the CBFS header out of the ROM and do endian conversion. */
@@ -173,69 +181,128 @@
if (header->magic != good_magic || header->offset >
header->rom_size - header->boot_block_size) {
- file_cbfs_result = CBFS_BAD_HEADER;
+ cbfs_s.result = CBFS_BAD_HEADER;
return 1;
}
return 0;
}
-void file_cbfs_init(uintptr_t end_of_rom)
+static int cbfs_load_header_ptr(struct cbfs_priv *priv, ulong base,
+ struct cbfs_header *header)
+{
+ struct cbfs_header *header_in_rom;
+
+ header_in_rom = (struct cbfs_header *)base;
+ swap_header(header, header_in_rom);
+
+ if (header->magic != good_magic || header->offset >
+ header->rom_size - header->boot_block_size) {
+ priv->result = CBFS_BAD_HEADER;
+ return -EFAULT;
+ }
+
+ return 0;
+}
+
+static void cbfs_init(struct cbfs_priv *priv, uintptr_t end_of_rom)
{
u8 *start_of_rom;
- initialized = 0;
- if (file_cbfs_load_header(end_of_rom, &cbfs_header))
+ priv->initialized = 0;
+
+ if (file_cbfs_load_header(end_of_rom, &priv->header))
return;
- start_of_rom = (u8 *)(end_of_rom + 1 - cbfs_header.rom_size);
+ start_of_rom = (u8 *)(end_of_rom + 1 - priv->header.rom_size);
- file_cbfs_fill_cache(start_of_rom, cbfs_header.rom_size,
- cbfs_header.align);
- if (file_cbfs_result == CBFS_SUCCESS)
- initialized = 1;
+ file_cbfs_fill_cache(priv, start_of_rom, priv->header.rom_size,
+ priv->header.align);
+ if (priv->result == CBFS_SUCCESS)
+ priv->initialized = 1;
+}
+
+void file_cbfs_init(uintptr_t end_of_rom)
+{
+ cbfs_init(&cbfs_s, end_of_rom);
+}
+
+int cbfs_init_mem(ulong base, ulong size, struct cbfs_priv **privp)
+{
+ struct cbfs_priv priv_s, *priv = &priv_s;
+ int ret;
+
+ /*
+ * Use a local variable to start with until we know that the CBFS is
+ * valid. Assume that a master header appears at the start, at offset
+ * 0x38.
+ */
+ ret = cbfs_load_header_ptr(priv, base + 0x38, &priv->header);
+ if (ret)
+ return ret;
+
+ file_cbfs_fill_cache(priv, (u8 *)base, priv->header.rom_size,
+ priv->header.align);
+ if (priv->result != CBFS_SUCCESS)
+ return -EINVAL;
+
+ priv->initialized = 1;
+ priv = malloc(sizeof(priv_s));
+ if (!priv)
+ return -ENOMEM;
+ memcpy(priv, &priv_s, sizeof(priv_s));
+ *privp = priv;
+
+ return 0;
}
const struct cbfs_header *file_cbfs_get_header(void)
{
- if (initialized) {
- file_cbfs_result = CBFS_SUCCESS;
- return &cbfs_header;
+ struct cbfs_priv *priv = &cbfs_s;
+
+ if (priv->initialized) {
+ priv->result = CBFS_SUCCESS;
+ return &priv->header;
} else {
- file_cbfs_result = CBFS_NOT_INITIALIZED;
+ priv->result = CBFS_NOT_INITIALIZED;
return NULL;
}
}
const struct cbfs_cachenode *file_cbfs_get_first(void)
{
- if (!initialized) {
- file_cbfs_result = CBFS_NOT_INITIALIZED;
+ struct cbfs_priv *priv = &cbfs_s;
+
+ if (!priv->initialized) {
+ priv->result = CBFS_NOT_INITIALIZED;
return NULL;
} else {
- file_cbfs_result = CBFS_SUCCESS;
- return file_cache;
+ priv->result = CBFS_SUCCESS;
+ return priv->file_cache;
}
}
void file_cbfs_get_next(const struct cbfs_cachenode **file)
{
- if (!initialized) {
- file_cbfs_result = CBFS_NOT_INITIALIZED;
- file = NULL;
+ struct cbfs_priv *priv = &cbfs_s;
+
+ if (!priv->initialized) {
+ priv->result = CBFS_NOT_INITIALIZED;
+ *file = NULL;
return;
}
if (*file)
*file = (*file)->next;
- file_cbfs_result = CBFS_SUCCESS;
+ priv->result = CBFS_SUCCESS;
}
-const struct cbfs_cachenode *file_cbfs_find(const char *name)
+const struct cbfs_cachenode *cbfs_find_file(struct cbfs_priv *priv,
+ const char *name)
{
- struct cbfs_cachenode *cache_node = file_cache;
+ struct cbfs_cachenode *cache_node = priv->file_cache;
- if (!initialized) {
- file_cbfs_result = CBFS_NOT_INITIALIZED;
+ if (!priv->initialized) {
+ priv->result = CBFS_NOT_INITIALIZED;
return NULL;
}
@@ -245,33 +312,40 @@
cache_node = cache_node->next;
}
if (!cache_node)
- file_cbfs_result = CBFS_FILE_NOT_FOUND;
+ priv->result = CBFS_FILE_NOT_FOUND;
else
- file_cbfs_result = CBFS_SUCCESS;
+ priv->result = CBFS_SUCCESS;
return cache_node;
}
+const struct cbfs_cachenode *file_cbfs_find(const char *name)
+{
+ return cbfs_find_file(&cbfs_s, name);
+}
+
const struct cbfs_cachenode *file_cbfs_find_uncached(uintptr_t end_of_rom,
const char *name)
{
+ struct cbfs_priv *priv = &cbfs_s;
u8 *start;
u32 size;
u32 align;
static struct cbfs_cachenode node;
- if (file_cbfs_load_header(end_of_rom, &cbfs_header))
+ if (file_cbfs_load_header(end_of_rom, &priv->header))
return NULL;
- start = (u8 *)(end_of_rom + 1 - cbfs_header.rom_size);
- size = cbfs_header.rom_size;
- align = cbfs_header.align;
+ start = (u8 *)(end_of_rom + 1 - priv->header.rom_size);
+ size = priv->header.rom_size;
+ align = priv->header.align;
while (size >= align) {
int result;
u32 used;
- result = file_cbfs_next_file(start, size, align, &node, &used);
+ result = file_cbfs_next_file(priv, start, size, align, &node,
+ &used);
if (result < 0)
return NULL;
@@ -284,25 +358,28 @@
size -= used;
start += used;
}
- file_cbfs_result = CBFS_FILE_NOT_FOUND;
+ cbfs_s.result = CBFS_FILE_NOT_FOUND;
return NULL;
}
const char *file_cbfs_name(const struct cbfs_cachenode *file)
{
- file_cbfs_result = CBFS_SUCCESS;
+ cbfs_s.result = CBFS_SUCCESS;
+
return file->name;
}
u32 file_cbfs_size(const struct cbfs_cachenode *file)
{
- file_cbfs_result = CBFS_SUCCESS;
+ cbfs_s.result = CBFS_SUCCESS;
+
return file->data_length;
}
u32 file_cbfs_type(const struct cbfs_cachenode *file)
{
- file_cbfs_result = CBFS_SUCCESS;
+ cbfs_s.result = CBFS_SUCCESS;
+
return file->type;
}
@@ -316,7 +393,7 @@
size = maxsize;
memcpy(buffer, file->data, size);
+ cbfs_s.result = CBFS_SUCCESS;
- file_cbfs_result = CBFS_SUCCESS;
return size;
}
diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c
index 464c33d..5bf78b5 100644
--- a/fs/ext4/ext4_common.c
+++ b/fs/ext4/ext4_common.c
@@ -570,7 +570,7 @@
g_parent_inode->size = cpu_to_le32(new_size);
new_blockcnt = le32_to_cpu(g_parent_inode->blockcnt);
- new_blockcnt += fs->sect_perblk;
+ new_blockcnt += fs->blksz >> LOG2_SECTOR_SIZE;
g_parent_inode->blockcnt = cpu_to_le32(new_blockcnt);
if (ext4fs_put_metadata
@@ -1571,8 +1571,12 @@
int log2blksz = get_fs()->dev_desc->log2blksz;
int desc_size = get_fs()->gdsize;
+ if (desc_size == 0)
+ return 0;
desc_per_blk = EXT2_BLOCK_SIZE(data) / desc_size;
+ if (desc_per_blk == 0)
+ return 0;
blkno = le32_to_cpu(data->sblock.first_data_block) + 1 +
group / desc_per_blk;
blkoff = (group % desc_per_blk) * desc_size;
@@ -1602,6 +1606,10 @@
/* It is easier to calculate if the first inode is 0. */
ino--;
+ if ( le32_to_cpu(sblock->inodes_per_group) == 0 || fs->inodesz == 0) {
+ free(blkgrp);
+ return 0;
+ }
status = ext4fs_blockgroup(data, ino / le32_to_cpu
(sblock->inodes_per_group), blkgrp);
if (status == 0) {
@@ -1610,6 +1618,10 @@
}
inodes_per_block = EXT2_BLOCK_SIZE(data) / fs->inodesz;
+ if ( inodes_per_block == 0 ) {
+ free(blkgrp);
+ return 0;
+ }
blkno = ext4fs_bg_get_inode_table_id(blkgrp, fs) +
(ino % le32_to_cpu(sblock->inodes_per_group)) / inodes_per_block;
blkoff = (ino % inodes_per_block) * fs->inodesz;
diff --git a/fs/ext4/ext4_journal.c b/fs/ext4/ext4_journal.c
index 6adbab9..3559daf 100644
--- a/fs/ext4/ext4_journal.c
+++ b/fs/ext4/ext4_journal.c
@@ -645,6 +645,10 @@
struct ext_filesystem *fs = get_fs();
long int blknr;
int i;
+
+ if (!(fs->sb->feature_compatibility & EXT4_FEATURE_COMPAT_HAS_JOURNAL))
+ return;
+
ext4fs_read_inode(ext4fs_root, EXT2_JOURNAL_INO, &inode_journal);
blknr = read_allocated_block(&inode_journal, jrnl_blk_idx++, NULL);
update_descriptor_block(blknr);
diff --git a/fs/ext4/ext4_journal.h b/fs/ext4/ext4_journal.h
index c9cf195..43fb8e7 100644
--- a/fs/ext4/ext4_journal.h
+++ b/fs/ext4/ext4_journal.h
@@ -17,6 +17,8 @@
#ifndef __EXT4_JRNL__
#define __EXT4_JRNL__
+#define EXT4_FEATURE_COMPAT_HAS_JOURNAL 0x0004
+
#define EXT2_JOURNAL_INO 8 /* Journal inode */
#define EXT2_JOURNAL_SUPERBLOCK 0 /* Journal Superblock number */
diff --git a/fs/ext4/ext4_write.c b/fs/ext4/ext4_write.c
index 504d23a..3368bd8 100644
--- a/fs/ext4/ext4_write.c
+++ b/fs/ext4/ext4_write.c
@@ -957,7 +957,7 @@
ext4fs_allocate_blocks(file_inode, blocks_remaining,
&blks_reqd_for_file);
file_inode->blockcnt = cpu_to_le32((blks_reqd_for_file * fs->blksz) >>
- fs->dev_desc->log2blksz);
+ LOG2_SECTOR_SIZE);
temp_ptr = zalloc(fs->blksz);
if (!temp_ptr)
diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c
index 26db677..37b31d9 100644
--- a/fs/ext4/ext4fs.c
+++ b/fs/ext4/ext4fs.c
@@ -61,18 +61,21 @@
lbaint_t delayed_skipfirst = 0;
lbaint_t delayed_next = 0;
char *delayed_buf = NULL;
+ char *start_buf = buf;
short status;
struct ext_block_cache cache;
ext_cache_init(&cache);
- if (blocksize <= 0)
- return -1;
-
/* Adjust len so it we can't read past the end of the file. */
if (len + pos > filesize)
len = (filesize - pos);
+ if (blocksize <= 0 || len <= 0) {
+ ext_cache_fini(&cache);
+ return -1;
+ }
+
blockcnt = lldiv(((len + pos) + blocksize - 1), blocksize);
for (i = lldiv(pos, blocksize); i < blockcnt; i++) {
@@ -137,6 +140,7 @@
}
} else {
int n;
+ int n_left;
if (previous_block_number != -1) {
/* spill */
status = ext4fs_devread(delayed_start,
@@ -151,8 +155,9 @@
}
/* Zero no more than `len' bytes. */
n = blocksize - skipfirst;
- if (n > len)
- n = len;
+ n_left = len - ( buf - start_buf );
+ if (n > n_left)
+ n = n_left;
memset(buf, 0, n);
}
buf += blocksize - skipfirst;
@@ -286,7 +291,7 @@
if (!cache->buf)
return 0;
if (!ext4fs_devread(block, 0, size, cache->buf)) {
- free(cache->buf);
+ ext_cache_fini(cache);
return 0;
}
cache->block = block;
diff --git a/fs/fat/fat.c b/fs/fat/fat.c
index 06c8ed1..29cae8d 100644
--- a/fs/fat/fat.c
+++ b/fs/fat/fat.c
@@ -1174,10 +1174,6 @@
/* For saving default max clustersize memory allocated to malloc pool */
dir_entry *dentptr = itr->dent;
- free(itr);
-
- itr = NULL;
-
ret = get_contents(&fsdata, dentptr, pos, buffer, maxsize, actread);
out_free_both:
diff --git a/fs/fs.c b/fs/fs.c
index 48d8f1f..d8a4ced 100644
--- a/fs/fs.c
+++ b/fs/fs.c
@@ -6,6 +6,7 @@
#include <config.h>
#include <errno.h>
#include <common.h>
+#include <env.h>
#include <mapmem.h>
#include <part.h>
#include <ext4fs.h>
diff --git a/fs/jffs2/jffs2_nand_1pass.c b/fs/jffs2/jffs2_nand_1pass.c
deleted file mode 100644
index b16005e..0000000
--- a/fs/jffs2/jffs2_nand_1pass.c
+++ /dev/null
@@ -1,1036 +0,0 @@
-#include <common.h>
-
-#include <malloc.h>
-#include <linux/stat.h>
-#include <linux/time.h>
-
-#include <jffs2/jffs2.h>
-#include <jffs2/jffs2_1pass.h>
-#include <nand.h>
-
-#include "jffs2_nand_private.h"
-
-#define NODE_CHUNK 1024 /* size of memory allocation chunk in b_nodes */
-
-/* Debugging switches */
-#undef DEBUG_DIRENTS /* print directory entry list after scan */
-#undef DEBUG_FRAGMENTS /* print fragment list after scan */
-#undef DEBUG /* enable debugging messages */
-
-#ifdef DEBUG
-# define DEBUGF(fmt,args...) printf(fmt ,##args)
-#else
-# define DEBUGF(fmt,args...)
-#endif
-
-static struct mtd_info *mtd;
-
-/* Compression names */
-static char *compr_names[] = {
- "NONE",
- "ZERO",
- "RTIME",
- "RUBINMIPS",
- "COPY",
- "DYNRUBIN",
- "ZLIB",
-#if defined(CONFIG_JFFS2_LZO)
- "LZO",
-#endif
-};
-
-/* Spinning wheel */
-static char spinner[] = { '|', '/', '-', '\\' };
-
-/* Memory management */
-struct mem_block {
- unsigned index;
- struct mem_block *next;
- char nodes[0];
-};
-
-static void
-free_nodes(struct b_list *list)
-{
- while (list->listMemBase != NULL) {
- struct mem_block *next = list->listMemBase->next;
- free(list->listMemBase);
- list->listMemBase = next;
- }
-}
-
-static struct b_node *
-add_node(struct b_list *list, int size)
-{
- u32 index = 0;
- struct mem_block *memBase;
- struct b_node *b;
-
- memBase = list->listMemBase;
- if (memBase != NULL)
- index = memBase->index;
-
- if (memBase == NULL || index >= NODE_CHUNK) {
- /* we need more space before we continue */
- memBase = mmalloc(sizeof(struct mem_block) + NODE_CHUNK * size);
- if (memBase == NULL) {
- putstr("add_node: malloc failed\n");
- return NULL;
- }
- memBase->next = list->listMemBase;
- index = 0;
- }
- /* now we have room to add it. */
- b = (struct b_node *)&memBase->nodes[size * index];
- index ++;
-
- memBase->index = index;
- list->listMemBase = memBase;
- list->listCount++;
- return b;
-}
-
-static struct b_node *
-insert_node(struct b_list *list, struct b_node *new)
-{
-#ifdef CONFIG_SYS_JFFS2_SORT_FRAGMENTS
- struct b_node *b, *prev;
-
- if (list->listTail != NULL && list->listCompare(new, list->listTail))
- prev = list->listTail;
- else if (list->listLast != NULL && list->listCompare(new, list->listLast))
- prev = list->listLast;
- else
- prev = NULL;
-
- for (b = (prev ? prev->next : list->listHead);
- b != NULL && list->listCompare(new, b);
- prev = b, b = b->next) {
- list->listLoops++;
- }
- if (b != NULL)
- list->listLast = prev;
-
- if (b != NULL) {
- new->next = b;
- if (prev != NULL)
- prev->next = new;
- else
- list->listHead = new;
- } else
-#endif
- {
- new->next = (struct b_node *) NULL;
- if (list->listTail != NULL) {
- list->listTail->next = new;
- list->listTail = new;
- } else {
- list->listTail = list->listHead = new;
- }
- }
-
- return new;
-}
-
-static struct b_node *
-insert_inode(struct b_list *list, struct jffs2_raw_inode *node, u32 offset)
-{
- struct b_inode *new;
-
- if (!(new = (struct b_inode *)add_node(list, sizeof(struct b_inode)))) {
- putstr("add_node failed!\r\n");
- return NULL;
- }
- new->offset = offset;
- new->version = node->version;
- new->ino = node->ino;
- new->isize = node->isize;
- new->csize = node->csize;
-
- return insert_node(list, (struct b_node *)new);
-}
-
-static struct b_node *
-insert_dirent(struct b_list *list, struct jffs2_raw_dirent *node, u32 offset)
-{
- struct b_dirent *new;
-
- if (!(new = (struct b_dirent *)add_node(list, sizeof(struct b_dirent)))) {
- putstr("add_node failed!\r\n");
- return NULL;
- }
- new->offset = offset;
- new->version = node->version;
- new->pino = node->pino;
- new->ino = node->ino;
- new->nhash = full_name_hash(node->name, node->nsize);
- new->nsize = node->nsize;
- new->type = node->type;
-
- return insert_node(list, (struct b_node *)new);
-}
-
-#ifdef CONFIG_SYS_JFFS2_SORT_FRAGMENTS
-/* Sort data entries with the latest version last, so that if there
- * is overlapping data the latest version will be used.
- */
-static int compare_inodes(struct b_node *new, struct b_node *old)
-{
- struct jffs2_raw_inode ojNew;
- struct jffs2_raw_inode ojOld;
- struct jffs2_raw_inode *jNew =
- (struct jffs2_raw_inode *)get_fl_mem(new->offset, sizeof(ojNew), &ojNew);
- struct jffs2_raw_inode *jOld =
- (struct jffs2_raw_inode *)get_fl_mem(old->offset, sizeof(ojOld), &ojOld);
-
- return jNew->version > jOld->version;
-}
-
-/* Sort directory entries so all entries in the same directory
- * with the same name are grouped together, with the latest version
- * last. This makes it easy to eliminate all but the latest version
- * by marking the previous version dead by setting the inode to 0.
- */
-static int compare_dirents(struct b_node *new, struct b_node *old)
-{
- struct jffs2_raw_dirent ojNew;
- struct jffs2_raw_dirent ojOld;
- struct jffs2_raw_dirent *jNew =
- (struct jffs2_raw_dirent *)get_fl_mem(new->offset, sizeof(ojNew), &ojNew);
- struct jffs2_raw_dirent *jOld =
- (struct jffs2_raw_dirent *)get_fl_mem(old->offset, sizeof(ojOld), &ojOld);
- int cmp;
-
- /* ascending sort by pino */
- if (jNew->pino != jOld->pino)
- return jNew->pino > jOld->pino;
-
- /* pino is the same, so use ascending sort by nsize, so
- * we don't do strncmp unless we really must.
- */
- if (jNew->nsize != jOld->nsize)
- return jNew->nsize > jOld->nsize;
-
- /* length is also the same, so use ascending sort by name
- */
- cmp = strncmp(jNew->name, jOld->name, jNew->nsize);
- if (cmp != 0)
- return cmp > 0;
-
- /* we have duplicate names in this directory, so use ascending
- * sort by version
- */
- if (jNew->version > jOld->version) {
- /* since jNew is newer, we know jOld is not valid, so
- * mark it with inode 0 and it will not be used
- */
- jOld->ino = 0;
- return 1;
- }
-
- return 0;
-}
-#endif
-
-static u32
-jffs_init_1pass_list(struct part_info *part)
-{
- struct b_lists *pL;
-
- if (part->jffs2_priv != NULL) {
- pL = (struct b_lists *)part->jffs2_priv;
- free_nodes(&pL->frag);
- free_nodes(&pL->dir);
- free(pL);
- }
- if (NULL != (part->jffs2_priv = malloc(sizeof(struct b_lists)))) {
- pL = (struct b_lists *)part->jffs2_priv;
-
- memset(pL, 0, sizeof(*pL));
-#ifdef CONFIG_SYS_JFFS2_SORT_FRAGMENTS
- pL->dir.listCompare = compare_dirents;
- pL->frag.listCompare = compare_inodes;
-#endif
- }
- return 0;
-}
-
-/* find the inode from the slashless name given a parent */
-static long
-jffs2_1pass_read_inode(struct b_lists *pL, u32 ino, char *dest,
- struct stat *stat)
-{
- struct b_inode *jNode;
- u32 totalSize = 0;
- u32 latestVersion = 0;
- long ret;
-
-#ifdef CONFIG_SYS_JFFS2_SORT_FRAGMENTS
- /* Find file size before loading any data, so fragments that
- * start past the end of file can be ignored. A fragment
- * that is partially in the file is loaded, so extra data may
- * be loaded up to the next 4K boundary above the file size.
- * This shouldn't cause trouble when loading kernel images, so
- * we will live with it.
- */
- for (jNode = (struct b_inode *)pL->frag.listHead; jNode; jNode = jNode->next) {
- if ((ino == jNode->ino)) {
- /* get actual file length from the newest node */
- if (jNode->version >= latestVersion) {
- totalSize = jNode->isize;
- latestVersion = jNode->version;
- }
- }
- }
-#endif
-
- for (jNode = (struct b_inode *)pL->frag.listHead; jNode; jNode = jNode->next) {
- if ((ino != jNode->ino))
- continue;
-#ifndef CONFIG_SYS_JFFS2_SORT_FRAGMENTS
- /* get actual file length from the newest node */
- if (jNode->version >= latestVersion) {
- totalSize = jNode->isize;
- latestVersion = jNode->version;
- }
-#endif
- if (dest || stat) {
- char *src, *dst;
- char data[4096 + sizeof(struct jffs2_raw_inode)];
- struct jffs2_raw_inode *inode;
- size_t len;
-
- inode = (struct jffs2_raw_inode *)&data;
- len = sizeof(struct jffs2_raw_inode);
- if (dest)
- len += jNode->csize;
- nand_read(mtd, jNode->offset, &len, inode);
- /* ignore data behind latest known EOF */
- if (inode->offset > totalSize)
- continue;
-
- if (stat) {
- stat->st_mtime = inode->mtime;
- stat->st_mode = inode->mode;
- stat->st_ino = inode->ino;
- stat->st_size = totalSize;
- }
-
- if (!dest)
- continue;
-
- src = ((char *) inode) + sizeof(struct jffs2_raw_inode);
- dst = (char *) (dest + inode->offset);
-
- switch (inode->compr) {
- case JFFS2_COMPR_NONE:
- ret = 0;
- memcpy(dst, src, inode->dsize);
- break;
- case JFFS2_COMPR_ZERO:
- ret = 0;
- memset(dst, 0, inode->dsize);
- break;
- case JFFS2_COMPR_RTIME:
- ret = 0;
- rtime_decompress(src, dst, inode->csize, inode->dsize);
- break;
- case JFFS2_COMPR_DYNRUBIN:
- /* this is slow but it works */
- ret = 0;
- dynrubin_decompress(src, dst, inode->csize, inode->dsize);
- break;
- case JFFS2_COMPR_ZLIB:
- ret = zlib_decompress(src, dst, inode->csize, inode->dsize);
- break;
-#if defined(CONFIG_JFFS2_LZO)
- case JFFS2_COMPR_LZO:
- ret = lzo_decompress(src, dst, inode->csize, inode->dsize);
- break;
-#endif
- default:
- /* unknown */
- putLabeledWord("UNKNOWN COMPRESSION METHOD = ", inode->compr);
- return -1;
- }
- }
- }
-
- return totalSize;
-}
-
-/* find the inode from the slashless name given a parent */
-static u32
-jffs2_1pass_find_inode(struct b_lists * pL, const char *name, u32 pino)
-{
- struct b_dirent *jDir;
- int len = strlen(name); /* name is assumed slash free */
- unsigned int nhash = full_name_hash(name, len);
- u32 version = 0;
- u32 inode = 0;
-
- /* we need to search all and return the inode with the highest version */
- for (jDir = (struct b_dirent *)pL->dir.listHead; jDir; jDir = jDir->next) {
- if ((pino == jDir->pino) && (jDir->ino) && /* 0 for unlink */
- (len == jDir->nsize) && (nhash == jDir->nhash)) {
- /* TODO: compare name */
- if (jDir->version < version)
- continue;
-
- if (jDir->version == version && inode != 0) {
- /* I'm pretty sure this isn't legal */
- putstr(" ** ERROR ** ");
-/* putnstr(jDir->name, jDir->nsize); */
-/* putLabeledWord(" has dup version =", version); */
- }
- inode = jDir->ino;
- version = jDir->version;
- }
- }
- return inode;
-}
-
-char *mkmodestr(unsigned long mode, char *str)
-{
- static const char *l = "xwr";
- int mask = 1, i;
- char c;
-
- switch (mode & S_IFMT) {
- case S_IFDIR: str[0] = 'd'; break;
- case S_IFBLK: str[0] = 'b'; break;
- case S_IFCHR: str[0] = 'c'; break;
- case S_IFIFO: str[0] = 'f'; break;
- case S_IFLNK: str[0] = 'l'; break;
- case S_IFSOCK: str[0] = 's'; break;
- case S_IFREG: str[0] = '-'; break;
- default: str[0] = '?';
- }
-
- for(i = 0; i < 9; i++) {
- c = l[i%3];
- str[9-i] = (mode & mask)?c:'-';
- mask = mask<<1;
- }
-
- if(mode & S_ISUID) str[3] = (mode & S_IXUSR)?'s':'S';
- if(mode & S_ISGID) str[6] = (mode & S_IXGRP)?'s':'S';
- if(mode & S_ISVTX) str[9] = (mode & S_IXOTH)?'t':'T';
- str[10] = '\0';
- return str;
-}
-
-static inline void dump_stat(struct stat *st, const char *name)
-{
- char str[20];
- char s[64], *p;
-
- if (st->st_mtime == (time_t)(-1)) /* some ctimes really hate -1 */
- st->st_mtime = 1;
-
- ctime_r(&st->st_mtime, s/*,64*/); /* newlib ctime doesn't have buflen */
-
- if ((p = strchr(s,'\n')) != NULL) *p = '\0';
- if ((p = strchr(s,'\r')) != NULL) *p = '\0';
-
-/*
- printf("%6lo %s %8ld %s %s\n", st->st_mode, mkmodestr(st->st_mode, str),
- st->st_size, s, name);
-*/
-
- printf(" %s %8ld %s %s", mkmodestr(st->st_mode,str), st->st_size, s, name);
-}
-
-static inline int
-dump_inode(struct b_lists *pL, struct b_dirent *d, struct b_inode *i)
-{
- char fname[JFFS2_MAX_NAME_LEN + 1];
- struct stat st;
- size_t len;
-
- if(!d || !i) return -1;
- len = d->nsize;
- nand_read(mtd, d->offset + sizeof(struct jffs2_raw_dirent),
- &len, &fname);
- fname[d->nsize] = '\0';
-
- memset(&st, 0, sizeof(st));
-
- jffs2_1pass_read_inode(pL, i->ino, NULL, &st);
-
- dump_stat(&st, fname);
-/* FIXME
- if (d->type == DT_LNK) {
- unsigned char *src = (unsigned char *) (&i[1]);
- putstr(" -> ");
- putnstr(src, (int)i->dsize);
- }
-*/
- putstr("\r\n");
-
- return 0;
-}
-
-/* list inodes with the given pino */
-static u32
-jffs2_1pass_list_inodes(struct b_lists * pL, u32 pino)
-{
- struct b_dirent *jDir;
- u32 i_version = 0;
-
- for (jDir = (struct b_dirent *)pL->dir.listHead; jDir; jDir = jDir->next) {
- if ((pino == jDir->pino) && (jDir->ino)) { /* ino=0 -> unlink */
- struct b_inode *jNode = (struct b_inode *)pL->frag.listHead;
- struct b_inode *i = NULL;
-
- while (jNode) {
- if (jNode->ino == jDir->ino && jNode->version >= i_version) {
- i_version = jNode->version;
- i = jNode;
- }
- jNode = jNode->next;
- }
- dump_inode(pL, jDir, i);
- }
- }
- return pino;
-}
-
-static u32
-jffs2_1pass_search_inode(struct b_lists * pL, const char *fname, u32 pino)
-{
- int i;
- char tmp[256];
- char working_tmp[256];
- char *c;
-
- /* discard any leading slash */
- i = 0;
- while (fname[i] == '/')
- i++;
- strcpy(tmp, &fname[i]);
-
- while ((c = (char *) strchr(tmp, '/'))) /* we are still dired searching */
- {
- strncpy(working_tmp, tmp, c - tmp);
- working_tmp[c - tmp] = '\0';
-#if 0
- putstr("search_inode: tmp = ");
- putstr(tmp);
- putstr("\r\n");
- putstr("search_inode: wtmp = ");
- putstr(working_tmp);
- putstr("\r\n");
- putstr("search_inode: c = ");
- putstr(c);
- putstr("\r\n");
-#endif
- for (i = 0; i < strlen(c) - 1; i++)
- tmp[i] = c[i + 1];
- tmp[i] = '\0';
-#if 0
- putstr("search_inode: post tmp = ");
- putstr(tmp);
- putstr("\r\n");
-#endif
-
- if (!(pino = jffs2_1pass_find_inode(pL, working_tmp, pino))) {
- putstr("find_inode failed for name=");
- putstr(working_tmp);
- putstr("\r\n");
- return 0;
- }
- }
- /* this is for the bare filename, directories have already been mapped */
- if (!(pino = jffs2_1pass_find_inode(pL, tmp, pino))) {
- putstr("find_inode failed for name=");
- putstr(tmp);
- putstr("\r\n");
- return 0;
- }
- return pino;
-
-}
-
-static u32
-jffs2_1pass_resolve_inode(struct b_lists * pL, u32 ino)
-{
- struct b_dirent *jDir;
- struct b_inode *jNode;
- u8 jDirFoundType = 0;
- u32 jDirFoundIno = 0;
- u32 jDirFoundPino = 0;
- char tmp[JFFS2_MAX_NAME_LEN + 1];
- u32 version = 0;
- u32 pino;
-
- /* we need to search all and return the inode with the highest version */
- for (jDir = (struct b_dirent *)pL->dir.listHead; jDir; jDir = jDir->next) {
- if (ino == jDir->ino) {
- if (jDir->version < version)
- continue;
-
- if (jDir->version == version && jDirFoundType) {
- /* I'm pretty sure this isn't legal */
- putstr(" ** ERROR ** ");
-/* putnstr(jDir->name, jDir->nsize); */
-/* putLabeledWord(" has dup version (resolve) = ", */
-/* version); */
- }
-
- jDirFoundType = jDir->type;
- jDirFoundIno = jDir->ino;
- jDirFoundPino = jDir->pino;
- version = jDir->version;
- }
- }
- /* now we found the right entry again. (shoulda returned inode*) */
- if (jDirFoundType != DT_LNK)
- return jDirFoundIno;
-
- /* it's a soft link so we follow it again. */
- for (jNode = (struct b_inode *)pL->frag.listHead; jNode; jNode = jNode->next) {
- if (jNode->ino == jDirFoundIno) {
- size_t len = jNode->csize;
- nand_read(mtd,
- jNode->offset + sizeof(struct jffs2_raw_inode),
- &len, &tmp);
- tmp[jNode->csize] = '\0';
- break;
- }
- }
- /* ok so the name of the new file to find is in tmp */
- /* if it starts with a slash it is root based else shared dirs */
- if (tmp[0] == '/')
- pino = 1;
- else
- pino = jDirFoundPino;
-
- return jffs2_1pass_search_inode(pL, tmp, pino);
-}
-
-static u32
-jffs2_1pass_search_list_inodes(struct b_lists * pL, const char *fname, u32 pino)
-{
- int i;
- char tmp[256];
- char working_tmp[256];
- char *c;
-
- /* discard any leading slash */
- i = 0;
- while (fname[i] == '/')
- i++;
- strcpy(tmp, &fname[i]);
- working_tmp[0] = '\0';
- while ((c = (char *) strchr(tmp, '/'))) /* we are still dired searching */
- {
- strncpy(working_tmp, tmp, c - tmp);
- working_tmp[c - tmp] = '\0';
- for (i = 0; i < strlen(c) - 1; i++)
- tmp[i] = c[i + 1];
- tmp[i] = '\0';
- /* only a failure if we arent looking at top level */
- if (!(pino = jffs2_1pass_find_inode(pL, working_tmp, pino)) &&
- (working_tmp[0])) {
- putstr("find_inode failed for name=");
- putstr(working_tmp);
- putstr("\r\n");
- return 0;
- }
- }
-
- if (tmp[0] && !(pino = jffs2_1pass_find_inode(pL, tmp, pino))) {
- putstr("find_inode failed for name=");
- putstr(tmp);
- putstr("\r\n");
- return 0;
- }
- /* this is for the bare filename, directories have already been mapped */
- if (!(pino = jffs2_1pass_list_inodes(pL, pino))) {
- putstr("find_inode failed for name=");
- putstr(tmp);
- putstr("\r\n");
- return 0;
- }
- return pino;
-
-}
-
-unsigned char
-jffs2_1pass_rescan_needed(struct part_info *part)
-{
- struct b_node *b;
- struct jffs2_unknown_node onode;
- struct jffs2_unknown_node *node;
- struct b_lists *pL = (struct b_lists *)part->jffs2_priv;
-
- if (part->jffs2_priv == 0){
- DEBUGF ("rescan: First time in use\n");
- return 1;
- }
- /* if we have no list, we need to rescan */
- if (pL->frag.listCount == 0) {
- DEBUGF ("rescan: fraglist zero\n");
- return 1;
- }
-
- /* or if we are scanning a new partition */
- if (pL->partOffset != part->offset) {
- DEBUGF ("rescan: different partition\n");
- return 1;
- }
-
- /* FIXME */
-#if 0
- /* but suppose someone reflashed a partition at the same offset... */
- b = pL->dir.listHead;
- while (b) {
- node = (struct jffs2_unknown_node *) get_fl_mem(b->offset,
- sizeof(onode), &onode);
- if (node->nodetype != JFFS2_NODETYPE_DIRENT) {
- DEBUGF ("rescan: fs changed beneath me? (%lx)\n",
- (unsigned long) b->offset);
- return 1;
- }
- b = b->next;
- }
-#endif
- return 0;
-}
-
-#ifdef DEBUG_FRAGMENTS
-static void
-dump_fragments(struct b_lists *pL)
-{
- struct b_node *b;
- struct jffs2_raw_inode ojNode;
- struct jffs2_raw_inode *jNode;
-
- putstr("\r\n\r\n******The fragment Entries******\r\n");
- b = pL->frag.listHead;
- while (b) {
- jNode = (struct jffs2_raw_inode *) get_fl_mem(b->offset,
- sizeof(ojNode), &ojNode);
- putLabeledWord("\r\n\tbuild_list: FLASH_OFFSET = ", b->offset);
- putLabeledWord("\tbuild_list: totlen = ", jNode->totlen);
- putLabeledWord("\tbuild_list: inode = ", jNode->ino);
- putLabeledWord("\tbuild_list: version = ", jNode->version);
- putLabeledWord("\tbuild_list: isize = ", jNode->isize);
- putLabeledWord("\tbuild_list: atime = ", jNode->atime);
- putLabeledWord("\tbuild_list: offset = ", jNode->offset);
- putLabeledWord("\tbuild_list: csize = ", jNode->csize);
- putLabeledWord("\tbuild_list: dsize = ", jNode->dsize);
- putLabeledWord("\tbuild_list: compr = ", jNode->compr);
- putLabeledWord("\tbuild_list: usercompr = ", jNode->usercompr);
- putLabeledWord("\tbuild_list: flags = ", jNode->flags);
- putLabeledWord("\tbuild_list: offset = ", b->offset); /* FIXME: ? [RS] */
- b = b->next;
- }
-}
-#endif
-
-#ifdef DEBUG_DIRENTS
-static void
-dump_dirents(struct b_lists *pL)
-{
- struct b_node *b;
- struct jffs2_raw_dirent *jDir;
-
- putstr("\r\n\r\n******The directory Entries******\r\n");
- b = pL->dir.listHead;
- while (b) {
- jDir = (struct jffs2_raw_dirent *) get_node_mem(b->offset);
- putstr("\r\n");
- putnstr(jDir->name, jDir->nsize);
- putLabeledWord("\r\n\tbuild_list: magic = ", jDir->magic);
- putLabeledWord("\tbuild_list: nodetype = ", jDir->nodetype);
- putLabeledWord("\tbuild_list: hdr_crc = ", jDir->hdr_crc);
- putLabeledWord("\tbuild_list: pino = ", jDir->pino);
- putLabeledWord("\tbuild_list: version = ", jDir->version);
- putLabeledWord("\tbuild_list: ino = ", jDir->ino);
- putLabeledWord("\tbuild_list: mctime = ", jDir->mctime);
- putLabeledWord("\tbuild_list: nsize = ", jDir->nsize);
- putLabeledWord("\tbuild_list: type = ", jDir->type);
- putLabeledWord("\tbuild_list: node_crc = ", jDir->node_crc);
- putLabeledWord("\tbuild_list: name_crc = ", jDir->name_crc);
- putLabeledWord("\tbuild_list: offset = ", b->offset); /* FIXME: ? [RS] */
- b = b->next;
- put_fl_mem(jDir);
- }
-}
-#endif
-
-static int
-jffs2_fill_scan_buf(struct mtd_info *mtd, unsigned char *buf,
- unsigned ofs, unsigned len)
-{
- int ret;
- unsigned olen;
-
- olen = len;
- ret = nand_read(mtd, ofs, &olen, buf);
- if (ret) {
- printf("nand_read(0x%x bytes from 0x%x) returned %d\n", len, ofs, ret);
- return ret;
- }
- if (olen < len) {
- printf("Read at 0x%x gave only 0x%x bytes\n", ofs, olen);
- return -1;
- }
- return 0;
-}
-
-#define EMPTY_SCAN_SIZE 1024
-static u32
-jffs2_1pass_build_lists(struct part_info * part)
-{
- struct b_lists *pL;
- struct jffs2_unknown_node *node;
- unsigned nr_blocks, sectorsize, ofs, offset;
- char *buf;
- int i;
- u32 counter = 0;
- u32 counter4 = 0;
- u32 counterF = 0;
- u32 counterN = 0;
-
- struct mtdids *id = part->dev->id;
- mtd = get_nand_dev_by_index(id->num);
- if (!mtd) {
- pr_err("\nno NAND devices available\n");
- return 0;
- }
-
- /* if we are building a list we need to refresh the cache. */
- jffs_init_1pass_list(part);
- pL = (struct b_lists *)part->jffs2_priv;
- pL->partOffset = part->offset;
- puts ("Scanning JFFS2 FS: ");
-
- sectorsize = mtd->erasesize;
- nr_blocks = part->size / sectorsize;
- buf = malloc(sectorsize);
- if (!buf)
- return 0;
-
- for (i = 0; i < nr_blocks; i++) {
- printf("\b\b%c ", spinner[counter++ % sizeof(spinner)]);
-
- offset = part->offset + i * sectorsize;
-
- if (nand_block_isbad(mtd, offset))
- continue;
-
- if (jffs2_fill_scan_buf(mtd, buf, offset, EMPTY_SCAN_SIZE))
- return 0;
-
- ofs = 0;
- /* Scan only 4KiB of 0xFF before declaring it's empty */
- while (ofs < EMPTY_SCAN_SIZE && *(uint32_t *)(&buf[ofs]) == 0xFFFFFFFF)
- ofs += 4;
- if (ofs == EMPTY_SCAN_SIZE)
- continue;
-
- if (jffs2_fill_scan_buf(mtd, buf + EMPTY_SCAN_SIZE, offset + EMPTY_SCAN_SIZE, sectorsize - EMPTY_SCAN_SIZE))
- return 0;
- offset += ofs;
-
- while (ofs < sectorsize - sizeof(struct jffs2_unknown_node)) {
- node = (struct jffs2_unknown_node *)&buf[ofs];
- if (node->magic != JFFS2_MAGIC_BITMASK || !hdr_crc(node)) {
- offset += 4;
- ofs += 4;
- counter4++;
- continue;
- }
- /* if its a fragment add it */
- if (node->nodetype == JFFS2_NODETYPE_INODE &&
- inode_crc((struct jffs2_raw_inode *) node)) {
- if (insert_inode(&pL->frag, (struct jffs2_raw_inode *) node,
- offset) == NULL) {
- return 0;
- }
- } else if (node->nodetype == JFFS2_NODETYPE_DIRENT &&
- dirent_crc((struct jffs2_raw_dirent *) node) &&
- dirent_name_crc((struct jffs2_raw_dirent *) node)) {
- if (! (counterN%100))
- puts ("\b\b. ");
- if (insert_dirent(&pL->dir, (struct jffs2_raw_dirent *) node,
- offset) == NULL) {
- return 0;
- }
- counterN++;
- } else if (node->nodetype == JFFS2_NODETYPE_CLEANMARKER) {
- if (node->totlen != sizeof(struct jffs2_unknown_node))
- printf("OOPS Cleanmarker has bad size "
- "%d != %zu\n",
- node->totlen,
- sizeof(struct jffs2_unknown_node));
- } else if (node->nodetype == JFFS2_NODETYPE_PADDING) {
- if (node->totlen < sizeof(struct jffs2_unknown_node))
- printf("OOPS Padding has bad size "
- "%d < %zu\n",
- node->totlen,
- sizeof(struct jffs2_unknown_node));
- } else {
- printf("Unknown node type: %x len %d offset 0x%x\n",
- node->nodetype,
- node->totlen, offset);
- }
- offset += ((node->totlen + 3) & ~3);
- ofs += ((node->totlen + 3) & ~3);
- counterF++;
- }
- }
-
- putstr("\b\b done.\r\n"); /* close off the dots */
-
-#if 0
- putLabeledWord("dir entries = ", pL->dir.listCount);
- putLabeledWord("frag entries = ", pL->frag.listCount);
- putLabeledWord("+4 increments = ", counter4);
- putLabeledWord("+file_offset increments = ", counterF);
-#endif
-
-#ifdef DEBUG_DIRENTS
- dump_dirents(pL);
-#endif
-
-#ifdef DEBUG_FRAGMENTS
- dump_fragments(pL);
-#endif
-
- /* give visual feedback that we are done scanning the flash */
- led_blink(0x0, 0x0, 0x1, 0x1); /* off, forever, on 100ms, off 100ms */
- free(buf);
-
- return 1;
-}
-
-
-static u32
-jffs2_1pass_fill_info(struct b_lists * pL, struct b_jffs2_info * piL)
-{
- struct b_node *b;
- struct jffs2_raw_inode ojNode;
- struct jffs2_raw_inode *jNode;
- int i;
-
- for (i = 0; i < JFFS2_NUM_COMPR; i++) {
- piL->compr_info[i].num_frags = 0;
- piL->compr_info[i].compr_sum = 0;
- piL->compr_info[i].decompr_sum = 0;
- }
-/* FIXME
- b = pL->frag.listHead;
- while (b) {
- jNode = (struct jffs2_raw_inode *) get_fl_mem(b->offset,
- sizeof(ojNode), &ojNode);
- if (jNode->compr < JFFS2_NUM_COMPR) {
- piL->compr_info[jNode->compr].num_frags++;
- piL->compr_info[jNode->compr].compr_sum += jNode->csize;
- piL->compr_info[jNode->compr].decompr_sum += jNode->dsize;
- }
- b = b->next;
- }
-*/
- return 0;
-}
-
-
-static struct b_lists *
-jffs2_get_list(struct part_info * part, const char *who)
-{
- if (jffs2_1pass_rescan_needed(part)) {
- if (!jffs2_1pass_build_lists(part)) {
- printf("%s: Failed to scan JFFSv2 file structure\n", who);
- return NULL;
- }
- }
- return (struct b_lists *)part->jffs2_priv;
-}
-
-
-/* Print directory / file contents */
-u32
-jffs2_1pass_ls(struct part_info * part, const char *fname)
-{
- struct b_lists *pl;
- long ret = 0;
- u32 inode;
-
- if (! (pl = jffs2_get_list(part, "ls")))
- return 0;
-
- if (! (inode = jffs2_1pass_search_list_inodes(pl, fname, 1))) {
- putstr("ls: Failed to scan jffs2 file structure\r\n");
- return 0;
- }
-
-#if 0
- putLabeledWord("found file at inode = ", inode);
- putLabeledWord("read_inode returns = ", ret);
-#endif
-
- return ret;
-}
-
-
-/* Load a file from flash into memory. fname can be a full path */
-u32
-jffs2_1pass_load(char *dest, struct part_info * part, const char *fname)
-{
-
- struct b_lists *pl;
- long ret = 0;
- u32 inode;
-
- if (! (pl = jffs2_get_list(part, "load")))
- return 0;
-
- if (! (inode = jffs2_1pass_search_inode(pl, fname, 1))) {
- putstr("load: Failed to find inode\r\n");
- return 0;
- }
-
- /* Resolve symlinks */
- if (! (inode = jffs2_1pass_resolve_inode(pl, inode))) {
- putstr("load: Failed to resolve inode structure\r\n");
- return 0;
- }
-
- if ((ret = jffs2_1pass_read_inode(pl, inode, dest, NULL)) < 0) {
- putstr("load: Failed to read inode\r\n");
- return 0;
- }
-
- DEBUGF ("load: loaded '%s' to 0x%lx (%ld bytes)\n", fname,
- (unsigned long) dest, ret);
- return ret;
-}
-
-/* Return information about the fs on this partition */
-u32
-jffs2_1pass_info(struct part_info * part)
-{
- struct b_jffs2_info info;
- struct b_lists *pl;
- int i;
-
- if (! (pl = jffs2_get_list(part, "info")))
- return 0;
-
- jffs2_1pass_fill_info(pl, &info);
- for (i = 0; i < JFFS2_NUM_COMPR; i++) {
- printf ("Compression: %s\n"
- "\tfrag count: %d\n"
- "\tcompressed sum: %d\n"
- "\tuncompressed sum: %d\n",
- compr_names[i],
- info.compr_info[i].num_frags,
- info.compr_info[i].compr_sum,
- info.compr_info[i].decompr_sum);
- }
- return 1;
-}
diff --git a/fs/jffs2/jffs2_nand_private.h b/fs/jffs2/jffs2_nand_private.h
deleted file mode 100644
index 18cca8d..0000000
--- a/fs/jffs2/jffs2_nand_private.h
+++ /dev/null
@@ -1,133 +0,0 @@
-#ifndef jffs2_private_h
-#define jffs2_private_h
-
-#include <jffs2/jffs2.h>
-
-struct b_node {
- struct b_node *next;
-};
-
-struct b_inode {
- struct b_inode *next;
- u32 offset; /* physical offset to beginning of real inode */
- u32 version;
- u32 ino;
- u32 isize;
- u32 csize;
-};
-
-struct b_dirent {
- struct b_dirent *next;
- u32 offset; /* physical offset to beginning of real dirent */
- u32 version;
- u32 pino;
- u32 ino;
- unsigned int nhash;
- unsigned char nsize;
- unsigned char type;
-};
-
-struct b_list {
- struct b_node *listTail;
- struct b_node *listHead;
- unsigned int listCount;
- struct mem_block *listMemBase;
-};
-
-struct b_lists {
- char *partOffset;
- struct b_list dir;
- struct b_list frag;
-};
-
-struct b_compr_info {
- u32 num_frags;
- u32 compr_sum;
- u32 decompr_sum;
-};
-
-struct b_jffs2_info {
- struct b_compr_info compr_info[JFFS2_NUM_COMPR];
-};
-
-static inline int
-hdr_crc(struct jffs2_unknown_node *node)
-{
-#if 1
- u32 crc = crc32_no_comp(0, (unsigned char *)node, sizeof(struct jffs2_unknown_node) - 4);
-#else
- /* what's the semantics of this? why is this here? */
- u32 crc = crc32_no_comp(~0, (unsigned char *)node, sizeof(struct jffs2_unknown_node) - 4);
-
- crc ^= ~0;
-#endif
- if (node->hdr_crc != crc) {
- return 0;
- } else {
- return 1;
- }
-}
-
-static inline int
-dirent_crc(struct jffs2_raw_dirent *node)
-{
- if (node->node_crc != crc32_no_comp(0, (unsigned char *)node, sizeof(struct jffs2_raw_dirent) - 8)) {
- return 0;
- } else {
- return 1;
- }
-}
-
-static inline int
-dirent_name_crc(struct jffs2_raw_dirent *node)
-{
- if (node->name_crc != crc32_no_comp(0, (unsigned char *)&(node->name), node->nsize)) {
- return 0;
- } else {
- return 1;
- }
-}
-
-static inline int
-inode_crc(struct jffs2_raw_inode *node)
-{
- if (node->node_crc != crc32_no_comp(0, (unsigned char *)node, sizeof(struct jffs2_raw_inode) - 8)) {
- return 0;
- } else {
- return 1;
- }
-}
-
-/* Borrowed from include/linux/dcache.h */
-
-/* Name hashing routines. Initial hash value */
-/* Hash courtesy of the R5 hash in reiserfs modulo sign bits */
-#define init_name_hash() 0
-
-/* partial hash update function. Assume roughly 4 bits per character */
-static inline unsigned long
-partial_name_hash(unsigned long c, unsigned long prevhash)
-{
- return (prevhash + (c << 4) + (c >> 4)) * 11;
-}
-
-/*
- * Finally: cut down the number of bits to a int value (and try to avoid
- * losing bits)
- */
-static inline unsigned long end_name_hash(unsigned long hash)
-{
- return (unsigned int) hash;
-}
-
-/* Compute the hash for a name string. */
-static inline unsigned int
-full_name_hash(const unsigned char *name, unsigned int len)
-{
- unsigned long hash = init_name_hash();
- while (len--)
- hash = partial_name_hash(*name++, hash);
- return end_name_hash(hash);
-}
-
-#endif /* jffs2_private.h */
diff --git a/fs/ubifs/ubifs.c b/fs/ubifs/ubifs.c
index d5101d3..67a0e8c 100644
--- a/fs/ubifs/ubifs.c
+++ b/fs/ubifs/ubifs.c
@@ -12,6 +12,8 @@
*/
#include <common.h>
+#include <env.h>
+#include <gzip.h>
#include <memalign.h>
#include "ubifs.h"
#include <u-boot/zlib.h>
diff --git a/include/ACEX1K.h b/include/ACEX1K.h
index 9814bba..7c5253c 100644
--- a/include/ACEX1K.h
+++ b/include/ACEX1K.h
@@ -60,6 +60,16 @@
#define Altera_EP2C35_SIZE 883905
#define Altera_EP3C5_SIZE 368011 /* .rbf size in bytes */
+#define ALTERA_EP4CE6_SIZE 368011 /* 2944088 Bits */
+#define ALTERA_EP4CE10_SIZE 368011 /* 2944088 Bits */
+#define ALTERA_EP4CE15_SIZE 510856 /* 4086848 Bits */
+#define ALTERA_EP4CE22_SIZE 718569 /* 5748552 Bits */
+#define ALTERA_EP4CE30_SIZE 1191788 /* 9534304 Bits */
+#define ALTERA_EP4CE40_SIZE 1191788 /* 9534304 Bits */
+#define ALTERA_EP4CE55_SIZE 1861195 /* 14889560 Bits */
+#define ALTERA_EP4CE75_SIZE 2495719 /* 19965752 Bits */
+#define ALTERA_EP4CE115_SIZE 3571462 /* 28571696 Bits */
+
/* Descriptor Macros
*********************************************************************/
/* ACEX1K devices */
diff --git a/include/_exports.h b/include/_exports.h
index c15050e..0dee05f 100644
--- a/include/_exports.h
+++ b/include/_exports.h
@@ -40,8 +40,7 @@
EXPORT_FUNC(simple_strtol, long, simple_strtol,
const char *, char **, unsigned int)
EXPORT_FUNC(strcmp, int, strcmp, const char *cs, const char *ct)
-#if defined(CONFIG_CMD_I2C) && \
- (!defined(CONFIG_DM_I2C) || defined(CONFIG_DM_I2C_COMPAT))
+#if defined(CONFIG_CMD_I2C) && !defined(CONFIG_DM_I2C)
EXPORT_FUNC(i2c_write, int, i2c_write, uchar, uint, int , uchar * , int)
EXPORT_FUNC(i2c_read, int, i2c_read, uchar, uint, int , uchar * , int)
#else
diff --git a/include/android_image.h b/include/android_image.h
index d78db9e..0519ece 100644
--- a/include/android_image.h
+++ b/include/android_image.h
@@ -1,59 +1,78 @@
-/* SPDX-License-Identifier: BSD-2-Clause */
+/* SPDX-License-Identifier: BSD-3-Clause */
/*
* This is from the Android Project,
- * Repository: https://android.googlesource.com/platform/system/core/
- * File: mkbootimg/bootimg.h
- * Commit: d162828814b08ada310846a33205befb69ef5799
+ * Repository: https://android.googlesource.com/platform/system/tools/mkbootimg
+ * File: include/bootimg/bootimg.h
+ * Commit: e55998a0f2b61b685d5eb4a486ca3a0c680b1a2f
*
- * Copyright (C) 2008 The Android Open Source Project
+ * Copyright (C) 2007 The Android Open Source Project
*/
#ifndef _ANDROID_IMAGE_H_
#define _ANDROID_IMAGE_H_
-typedef struct andr_img_hdr andr_img_hdr;
-
#define ANDR_BOOT_MAGIC "ANDROID!"
#define ANDR_BOOT_MAGIC_SIZE 8
#define ANDR_BOOT_NAME_SIZE 16
#define ANDR_BOOT_ARGS_SIZE 512
#define ANDR_BOOT_EXTRA_ARGS_SIZE 1024
+/*
+ * It is expected that callers would explicitly specify which version of the
+ * boot image header they need to use.
+ */
+typedef struct andr_img_hdr andr_img_hdr;
+
+/* The bootloader expects the structure of andr_img_hdr with header
+ * version 0 to be as follows: */
struct andr_img_hdr {
- char magic[ANDR_BOOT_MAGIC_SIZE];
+ /* Must be ANDR_BOOT_MAGIC. */
+ char magic[ANDR_BOOT_MAGIC_SIZE];
- u32 kernel_size; /* size in bytes */
- u32 kernel_addr; /* physical load addr */
+ u32 kernel_size; /* size in bytes */
+ u32 kernel_addr; /* physical load addr */
- u32 ramdisk_size; /* size in bytes */
- u32 ramdisk_addr; /* physical load addr */
+ u32 ramdisk_size; /* size in bytes */
+ u32 ramdisk_addr; /* physical load addr */
- u32 second_size; /* size in bytes */
- u32 second_addr; /* physical load addr */
+ u32 second_size; /* size in bytes */
+ u32 second_addr; /* physical load addr */
- u32 tags_addr; /* physical addr for kernel tags */
- u32 page_size; /* flash page size we assume */
- u32 unused; /* reserved for future expansion: MUST be 0 */
+ u32 tags_addr; /* physical addr for kernel tags */
+ u32 page_size; /* flash page size we assume */
- /* operating system version and security patch level; for
- * version "A.B.C" and patch level "Y-M-D":
- * ver = A << 14 | B << 7 | C (7 bits for each of A, B, C)
- * lvl = ((Y - 2000) & 127) << 4 | M (7 bits for Y, 4 bits for M)
- * os_version = ver << 11 | lvl */
- u32 os_version;
+ /* Version of the boot image header. */
+ u32 header_version;
- char name[ANDR_BOOT_NAME_SIZE]; /* asciiz product name */
+ /* Operating system version and security patch level.
+ * For version "A.B.C" and patch level "Y-M-D":
+ * (7 bits for each of A, B, C; 7 bits for (Y-2000), 4 bits for M)
+ * os_version = A[31:25] B[24:18] C[17:11] (Y-2000)[10:4] M[3:0] */
+ u32 os_version;
- char cmdline[ANDR_BOOT_ARGS_SIZE];
+ char name[ANDR_BOOT_NAME_SIZE]; /* asciiz product name */
- u32 id[8]; /* timestamp / checksum / sha1 / etc */
+ char cmdline[ANDR_BOOT_ARGS_SIZE];
- /* Supplemental command line data; kept here to maintain
- * binary compatibility with older versions of mkbootimg */
- char extra_cmdline[ANDR_BOOT_EXTRA_ARGS_SIZE];
+ u32 id[8]; /* timestamp / checksum / sha1 / etc */
+
+ /* Supplemental command line data; kept here to maintain
+ * binary compatibility with older versions of mkbootimg. */
+ char extra_cmdline[ANDR_BOOT_EXTRA_ARGS_SIZE];
+
+ /* Fields in boot_img_hdr_v1 and newer. */
+ u32 recovery_dtbo_size; /* size in bytes for recovery DTBO/ACPIO image */
+ u64 recovery_dtbo_offset; /* offset to recovery dtbo/acpio in boot image */
+ u32 header_size;
+
+ /* Fields in boot_img_hdr_v2 and newer. */
+ u32 dtb_size; /* size in bytes for DTB image */
+ u64 dtb_addr; /* physical load address for DTB image */
} __attribute__((packed));
-/*
+/* When a boot header is of version 0, the structure of boot image is as
+ * follows:
+ *
* +-----------------+
* | boot header | 1 page
* +-----------------+
@@ -79,4 +98,45 @@
* 6. if second_size != 0: jump to second_addr
* else: jump to kernel_addr
*/
+
+/* When the boot image header has a version of 2, the structure of the boot
+ * image is as follows:
+ *
+ * +---------------------+
+ * | boot header | 1 page
+ * +---------------------+
+ * | kernel | n pages
+ * +---------------------+
+ * | ramdisk | m pages
+ * +---------------------+
+ * | second stage | o pages
+ * +---------------------+
+ * | recovery dtbo/acpio | p pages
+ * +---------------------+
+ * | dtb | q pages
+ * +---------------------+
+
+ * n = (kernel_size + page_size - 1) / page_size
+ * m = (ramdisk_size + page_size - 1) / page_size
+ * o = (second_size + page_size - 1) / page_size
+ * p = (recovery_dtbo_size + page_size - 1) / page_size
+ * q = (dtb_size + page_size - 1) / page_size
+ *
+ * 0. all entities are page_size aligned in flash
+ * 1. kernel, ramdisk and DTB are required (size != 0)
+ * 2. recovery_dtbo/recovery_acpio is required for recovery.img in non-A/B
+ * devices(recovery_dtbo_size != 0)
+ * 3. second is optional (second_size == 0 -> no second)
+ * 4. load each element (kernel, ramdisk, second, dtb) at
+ * the specified physical address (kernel_addr, etc)
+ * 5. If booting to recovery mode in a non-A/B device, extract recovery
+ * dtbo/acpio and apply the correct set of overlays on the base device tree
+ * depending on the hardware/product revision.
+ * 6. prepare tags at tag_addr. kernel_args[] is
+ * appended to the kernel commandline in the tags.
+ * 7. r0 = 0, r1 = MACHINE_TYPE, r2 = tags_addr
+ * 8. if second_size != 0: jump to second_addr
+ * else: jump to kernel_addr
+ */
+
#endif
diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
index 02a3ed6..7587ba2 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -33,7 +33,7 @@
/* We cannot bracket this with CONFIG_PCI due to mpc5xxx */
unsigned long pci_clk;
unsigned long mem_clk;
-#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
+#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO) || defined(CONFIG_DM_VIDEO)
unsigned long fb_base; /* Base address of framebuffer mem */
#endif
#if defined(CONFIG_POST)
@@ -137,7 +137,7 @@
#if defined(CONFIG_TRANSLATION_OFFSET)
fdt_addr_t translation_offset; /* optional translation offset */
#endif
-#if defined(CONFIG_WDT)
+#if CONFIG_IS_ENABLED(WDT)
struct udevice *watchdog_dev;
#endif
} gd_t;
@@ -150,7 +150,7 @@
#endif
/*
- * Global Data Flags - the top 16 bits are reserved for arch-specific flags
+ * Global Data Flags
*/
#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */
#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
index d036026..d6cf187 100644
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -349,6 +349,23 @@
int dm_gpio_lookup_name(const char *name, struct gpio_desc *desc);
/**
+ * gpio_hog_lookup_name() - Look up a named GPIO and return the gpio descr.
+ *
+ * @name: Name to look up
+ * @desc: Returns GPIO description, on success, else NULL
+ * @return: Returns 0 if OK, else -ENODEV
+ */
+int gpio_hog_lookup_name(const char *name, struct gpio_desc **desc);
+
+/**
+ * gpio_hog_probe_all() - probe all gpio devices with
+ * gpio-hog subnodes.
+ *
+ * @return: Returns return value from device_probe()
+ */
+int gpio_hog_probe_all(void);
+
+/**
* gpio_lookup_name - Look up a GPIO name and return its details
*
* This is used to convert a named GPIO into a device, offset and GPIO
@@ -504,6 +521,23 @@
int flags);
/**
+ * gpio_dev_request_index() - request single GPIO from gpio device
+ *
+ * @dev: GPIO device
+ * @nodename: Name of node for which gpio gets requested, used
+ * for the gpio label name
+ * @list_name: Name of GPIO list (e.g. "board-id-gpios")
+ * @index: Index number of the GPIO in that list use request (0=first)
+ * @flags: GPIOD_* flags
+ * @dtflags: GPIO flags read from DT defined see GPIOD_*
+ * @desc: returns GPIO descriptor filled from this function
+ * @return: return value from gpio_request_tail()
+ */
+int gpio_dev_request_index(struct udevice *dev, const char *nodename,
+ char *list_name, int index, int flags,
+ int dtflags, struct gpio_desc *desc);
+
+/**
* dm_gpio_free() - Free a single GPIO
*
* This frees a single GPIOs previously returned from gpio_request_by_name().
diff --git a/include/asm-generic/pe.h b/include/asm-generic/pe.h
index faae534..b247519 100644
--- a/include/asm-generic/pe.h
+++ b/include/asm-generic/pe.h
@@ -29,6 +29,22 @@
#define IMAGE_FILE_UP_SYSTEM_ONLY 0x4000
#define IMAGE_FILE_BYTES_REVERSED_HI 0x8000
+/* Machine types */
+#define IMAGE_FILE_MACHINE_I386 0x014c
+#define IMAGE_FILE_MACHINE_ARM 0x01c0
+#define IMAGE_FILE_MACHINE_THUMB 0x01c2
+#define IMAGE_FILE_MACHINE_ARMNT 0x01c4
+#define IMAGE_FILE_MACHINE_AMD64 0x8664
+#define IMAGE_FILE_MACHINE_ARM64 0xaa64
+#define IMAGE_FILE_MACHINE_RISCV32 0x5032
+#define IMAGE_FILE_MACHINE_RISCV64 0x5064
+
+/* Header magic constants */
+#define IMAGE_NT_OPTIONAL_HDR32_MAGIC 0x010b
+#define IMAGE_NT_OPTIONAL_HDR64_MAGIC 0x020b
+#define IMAGE_DOS_SIGNATURE 0x5a4d /* MZ */
+#define IMAGE_NT_SIGNATURE 0x00004550 /* PE00 */
+
/* Subsystem type */
#define IMAGE_SUBSYSTEM_EFI_APPLICATION 10
#define IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER 11
diff --git a/include/autoboot.h b/include/autoboot.h
index 3ebd6f9..ac8157e 100644
--- a/include/autoboot.h
+++ b/include/autoboot.h
@@ -27,7 +27,7 @@
* autoboot_command() - run the autoboot command
*
* If enabled, run the autoboot command returned from bootdelay_process().
- * Also do the CONFIG_MENUKEY processing if enabled.
+ * Also do the CONFIG_AUTOBOOT_MENUKEY processing if enabled.
*
* @cmd: Command to run
*/
diff --git a/include/bootcount.h b/include/bootcount.h
index daee843..8fa8cf8 100644
--- a/include/bootcount.h
+++ b/include/bootcount.h
@@ -9,6 +9,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/byteorder.h>
+#include <env.h>
#ifdef CONFIG_DM_BOOTCOUNT
diff --git a/include/bootm.h b/include/bootm.h
index f771b73..edeeacb 100644
--- a/include/bootm.h
+++ b/include/bootm.h
@@ -59,23 +59,6 @@
void arch_preboot_os(void);
-/**
- * bootm_decomp_image() - decompress the operating system
- *
- * @comp: Compression algorithm that is used (IH_COMP_...)
- * @load: Destination load address in U-Boot memory
- * @image_start Image start address (where we are decompressing from)
- * @type: OS type (IH_OS_...)
- * @load_bug: Place to decompress to
- * @image_buf: Address to decompress from
- * @image_len: Number of bytes in @image_buf to decompress
- * @unc_len: Available space for decompression
- * @return 0 if OK, -ve on error (BOOTM_ERR_...)
- */
-int bootm_decomp_image(int comp, ulong load, ulong image_start, int type,
- void *load_buf, void *image_buf, ulong image_len,
- uint unc_len, ulong *load_end);
-
/*
* boards should define this to disable devices when EFI exits from boot
* services.
diff --git a/include/cache.h b/include/cache.h
index c6334ca..32f59fd 100644
--- a/include/cache.h
+++ b/include/cache.h
@@ -22,6 +22,22 @@
* @return 0 if OK, -ve on error
*/
int (*get_info)(struct udevice *dev, struct cache_info *info);
+
+ /**
+ * enable() - Enable cache
+ *
+ * @dev: Device to check (UCLASS_CACHE)
+ * @return 0 if OK, -ve on error
+ */
+ int (*enable)(struct udevice *dev);
+
+ /**
+ * disable() - Flush and disable cache
+ *
+ * @dev: Device to check (UCLASS_CACHE)
+ * @return 0 if OK, -ve on error
+ */
+ int (*disable)(struct udevice *dev);
};
#define cache_get_ops(dev) ((struct cache_ops *)(dev)->driver->ops)
@@ -35,4 +51,19 @@
*/
int cache_get_info(struct udevice *dev, struct cache_info *info);
+/**
+ * cache_enable() - Enable cache
+ *
+ * @dev: Device to check (UCLASS_CACHE)
+ * @return 0 if OK, -ve on error
+ */
+int cache_enable(struct udevice *dev);
+
+/**
+ * cache_disable() - Flush and disable cache
+ *
+ * @dev: Device to check (UCLASS_CACHE)
+ * @return 0 if OK, -ve on error
+ */
+int cache_disable(struct udevice *dev);
#endif
diff --git a/include/cbfs.h b/include/cbfs.h
index bd1bf75..6d4c4d4 100644
--- a/include/cbfs.h
+++ b/include/cbfs.h
@@ -40,6 +40,17 @@
CBFS_TYPE_CMOS_LAYOUT = 0x01aa
};
+enum {
+ CBFS_HEADER_MAGIC = 0x4f524243,
+};
+
+/**
+ * struct cbfs_header - header at the start of a CBFS region
+ *
+ * All fields use big-endian format.
+ *
+ * @magic: Magic number (CBFS_HEADER_MAGIC)
+ */
struct cbfs_header {
u32 magic;
u32 version;
@@ -54,7 +65,8 @@
u8 magic[8];
u32 len;
u32 type;
- u32 checksum;
+ /* offset to struct cbfs_file_attribute or 0 */
+ u32 attributes_offset;
u32 offset;
} __packed;
@@ -65,7 +77,7 @@
u32 data_length;
char *name;
u32 name_length;
- u32 checksum;
+ u32 attributes_offset;
} __packed;
extern enum cbfs_result file_cbfs_result;
@@ -79,6 +91,13 @@
const char *file_cbfs_error(void);
/**
+ * cbfs_get_result() - Get the result of the last CBFS operation
+ *
+ *@return last result
+ */
+enum cbfs_result cbfs_get_result(void);
+
+/**
* file_cbfs_init() - Initialize the CBFS driver and load metadata into RAM.
*
* @end_of_rom: Points to the end of the ROM the CBFS should be read
@@ -116,6 +135,28 @@
*/
const struct cbfs_cachenode *file_cbfs_find(const char *name);
+struct cbfs_priv *priv;
+
+/**
+ * cbfs_find_file() - Find a file in a given CBFS
+ *
+ * @cbfs: CBFS to look in (use cbfs_init_mem() to set it up)
+ * @name: Filename to look for
+ * @return pointer to CBFS node if found, else NULL
+ */
+const struct cbfs_cachenode *cbfs_find_file(struct cbfs_priv *cbfs,
+ const char *name);
+
+/**
+ * cbfs_init_mem() - Set up a new CBFS
+ *
+ * @base: Base address of CBFS
+ * @size: Size of CBFS in bytes
+ * @cbfsp: Returns a pointer to CBFS on success
+ * @return 0 if OK, -ve on error
+ */
+int cbfs_init_mem(ulong base, ulong size, struct cbfs_priv **privp);
+
/***************************************************************************/
/* All of the functions below can be used without first initializing CBFS. */
diff --git a/include/charset.h b/include/charset.h
index 4f7ae8f..fde6bdd 100644
--- a/include/charset.h
+++ b/include/charset.h
@@ -168,6 +168,21 @@
*/
s32 utf_to_upper(const s32 code);
+/*
+ * u16_strncmp() - compare two u16 string
+ *
+ * @s1: first string to compare
+ * @s2: second string to compare
+ * @n: maximum number of u16 to compare
+ * Return: 0 if the first n u16 are the same in s1 and s2
+ * < 0 if the first different u16 in s1 is less than the
+ * corresponding u16 in s2
+ * > 0 if the first different u16 in s1 is greater than the
+ * corresponding u16 in s2
+ */
+int u16_strncmp(const u16 *s1, const u16 *s2, size_t n);
+#define u16_strcmp(s1, s2) u16_strncmp((s1), (s2), SIZE_MAX)
+
/**
* u16_strlen - count non-zero words
*
@@ -178,7 +193,7 @@
* ReturnValue: number of non-zero words.
* This is not the number of utf-16 letters!
*/
-size_t u16_strlen(const u16 *in);
+size_t u16_strlen(const void *in);
/**
* u16_strlen - count non-zero words
@@ -214,7 +229,7 @@
* @src: source buffer (null terminated)
* Return: allocated new buffer on success, NULL on failure
*/
-u16 *u16_strdup(const u16 *src);
+u16 *u16_strdup(const void *src);
/**
* utf16_to_utf8() - Convert an utf16 string to utf8
diff --git a/include/clk.h b/include/clk.h
index d24e997..18b2e3c 100644
--- a/include/clk.h
+++ b/include/clk.h
@@ -20,7 +20,7 @@
* clock provider. This API provides a standard means for drivers to enable and
* disable clocks, and to set the rate at which they oscillate.
*
- * A driver that implements UCLASS_CLOCK is a clock provider. A provider will
+ * A driver that implements UCLASS_CLK is a clock provider. A provider will
* often implement multiple separate clocks, since the hardware it manages
* often has this capability. clk-uclass.h describes the interface which
* clock providers must implement.
@@ -40,6 +40,10 @@
* other clock APIs to identify which clock signal to operate upon.
*
* @dev: The device which implements the clock signal.
+ * @rate: The clock rate (in HZ).
+ * @flags: Flags used across common clock structure (e.g. CLK_)
+ * Clock IP blocks specific flags (i.e. mux, div, gate, etc) are defined
+ * in struct's for those devices (e.g. struct clk_mux).
* @id: The clock signal ID within the provider.
* @data: An optional data field for scenarios where a single integer ID is not
* sufficient. If used, it can be populated through an .of_xlate op and
@@ -55,6 +59,9 @@
*/
struct clk {
struct udevice *dev;
+ long long rate; /* in HZ */
+ u32 flags;
+ int enable_count;
/*
* Written by of_xlate. In the future, we might add more fields here.
*/
@@ -253,6 +260,24 @@
ulong clk_get_rate(struct clk *clk);
/**
+ * clk_get_parent() - Get current clock's parent.
+ *
+ * @clk: A clock struct that was previously successfully requested by
+ * clk_request/get_by_*().
+ * @return pointer to parent's struct clk, or error code passed as pointer
+ */
+struct clk *clk_get_parent(struct clk *clk);
+
+/**
+ * clk_get_parent_rate() - Get parent of current clock rate.
+ *
+ * @clk: A clock struct that was previously successfully requested by
+ * clk_request/get_by_*().
+ * @return clock rate in Hz, or -ve error code.
+ */
+long long clk_get_parent_rate(struct clk *clk);
+
+/**
* clk_set_rate() - Set current clock rate.
*
* @clk: A clock struct that was previously successfully requested by
@@ -309,6 +334,18 @@
*/
int clk_disable_bulk(struct clk_bulk *bulk);
+/**
+ * clk_is_match - check if two clk's point to the same hardware clock
+ * @p: clk compared against q
+ * @q: clk compared against p
+ *
+ * Returns true if the two struct clk pointers both point to the same hardware
+ * clock node.
+ *
+ * Returns false otherwise. Note that two NULL clks are treated as matching.
+ */
+bool clk_is_match(const struct clk *p, const struct clk *q);
+
int soc_clk_dump(void);
/**
@@ -321,4 +358,24 @@
{
return !!clk->dev;
}
+
+/**
+ * clk_get_by_id() - Get the clock by its ID
+ *
+ * @id: The clock ID to search for
+ *
+ * @clkp: A pointer to clock struct that has been found among added clocks
+ * to UCLASS_CLK
+ * @return zero on success, or -ENOENT on error
+ */
+int clk_get_by_id(ulong id, struct clk **clkp);
+
+/**
+ * clk_dev_binded() - Check whether the clk has a device binded
+ *
+ * @clk A pointer to the clk
+ *
+ * @return true on binded, or false on no
+ */
+bool clk_dev_binded(struct clk *clk);
#endif
diff --git a/include/command.h b/include/command.h
index 2bfee89..f6170e7 100644
--- a/include/command.h
+++ b/include/command.h
@@ -10,6 +10,7 @@
#ifndef __COMMAND_H
#define __COMMAND_H
+#include <env.h>
#include <linker_lists.h>
#ifndef NULL
diff --git a/include/common.h b/include/common.h
index 2c21dee..d8f302e 100644
--- a/include/common.h
+++ b/include/common.h
@@ -1,5 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
+ * Common header file for U-Boot
+ *
+ * This file still includes quite a bit of stuff that should be in separate
+ * headers like command.h, cpu.h and timer.h. Please think before adding more
+ * things. Patches to remove things are welcome.
+ *
* (C) Copyright 2000-2009
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
@@ -45,16 +51,6 @@
#include <asm/u-boot.h> /* boot information for Linux kernel */
#include <asm/global_data.h> /* global data used for startup functions */
-#if defined(CONFIG_ENV_IS_EMBEDDED)
-#define TOTAL_MALLOC_LEN CONFIG_SYS_MALLOC_LEN
-#elif ( ((CONFIG_ENV_ADDR+CONFIG_ENV_SIZE) < CONFIG_SYS_MONITOR_BASE) || \
- (CONFIG_ENV_ADDR >= (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)) ) || \
- defined(CONFIG_ENV_IS_IN_NVRAM)
-#define TOTAL_MALLOC_LEN (CONFIG_SYS_MALLOC_LEN + CONFIG_ENV_SIZE)
-#else
-#define TOTAL_MALLOC_LEN CONFIG_SYS_MALLOC_LEN
-#endif
-
/* startup functions, used in:
* common/board_f.c
* common/init/board_init.c
@@ -145,114 +141,6 @@
/* common/cmd_ext2.c */
int do_ext2load(cmd_tbl_t *, int, int, char * const []);
-/* common/cmd_nvedit.c */
-int env_init (void);
-void env_relocate (void);
-int envmatch (uchar *, int);
-
-/**
- * env_get() - Look up the value of an environment variable
- *
- * In U-Boot proper this can be called before relocation (which is when the
- * environment is loaded from storage, i.e. GD_FLG_ENV_READY is 0). In that
- * case this function calls env_get_f().
- *
- * @varname: Variable to look up
- * @return value of variable, or NULL if not found
- */
-char *env_get(const char *varname);
-
-/**
- * env_get_f() - Look up the value of an environment variable (early)
- *
- * This function is called from env_get() if the environment has not been
- * loaded yet (GD_FLG_ENV_READY flag is 0). Some environment locations will
- * support reading the value (slowly) and some will not.
- *
- * @varname: Variable to look up
- * @return value of variable, or NULL if not found
- */
-int env_get_f(const char *name, char *buf, unsigned len);
-
-/**
- * env_get_ulong() - Return an environment variable as an integer value
- *
- * Most U-Boot environment variables store hex values. For those which store
- * (e.g.) base-10 integers, this function can be used to read the value.
- *
- * @name: Variable to look up
- * @base: Base to use (e.g. 10 for base 10, 2 for binary)
- * @default_val: Default value to return if no value is found
- * @return the value found, or @default_val if none
- */
-ulong env_get_ulong(const char *name, int base, ulong default_val);
-
-/**
- * env_get_hex() - Return an environment variable as a hex value
- *
- * Decode an environment as a hex number (it may or may not have a 0x
- * prefix). If the environment variable cannot be found, or does not start
- * with hex digits, the default value is returned.
- *
- * @varname: Variable to decode
- * @default_val: Value to return on error
- */
-ulong env_get_hex(const char *varname, ulong default_val);
-
-/*
- * Read an environment variable as a boolean
- * Return -1 if variable does not exist (default to true)
- */
-int env_get_yesno(const char *var);
-
-/**
- * env_set() - set an environment variable
- *
- * This sets or deletes the value of an environment variable. For setting the
- * value the variable is created if it does not already exist.
- *
- * @varname: Variable to adjust
- * @value: Value to set for the variable, or NULL or "" to delete the variable
- * @return 0 if OK, 1 on error
- */
-int env_set(const char *varname, const char *value);
-
-/**
- * env_set_ulong() - set an environment variable to an integer
- *
- * @varname: Variable to adjust
- * @value: Value to set for the variable (will be converted to a string)
- * @return 0 if OK, 1 on error
- */
-int env_set_ulong(const char *varname, ulong value);
-
-/**
- * env_set_hex() - set an environment variable to a hex value
- *
- * @varname: Variable to adjust
- * @value: Value to set for the variable (will be converted to a hex string)
- * @return 0 if OK, 1 on error
- */
-int env_set_hex(const char *varname, ulong value);
-
-/**
- * env_set_addr - Set an environment variable to an address in hex
- *
- * @varname: Environment variable to set
- * @addr: Value to set it to
- * @return 0 if ok, 1 on error
- */
-static inline int env_set_addr(const char *varname, const void *addr)
-{
- return env_set_hex(varname, (ulong)addr);
-}
-
-#ifdef CONFIG_AUTO_COMPLETE
-int env_complete(char *var, int maxv, char *cmdv[], int maxsz, char *buf,
- bool dollar_comp);
-#endif
-int get_env_id (void);
-
void pci_init_board(void);
/* common/exports.c */
@@ -379,23 +267,12 @@
int disable_interrupts (void);
/* $(CPU)/.../commproc.c */
-int dpram_init (void);
-uint dpram_base(void);
-uint dpram_base_align(uint align);
-uint dpram_alloc(uint size);
-uint dpram_alloc_align(uint size,uint align);
void bootcount_store (ulong);
ulong bootcount_load (void);
/* $(CPU)/.../<eth> */
void mii_init (void);
-/* $(CPU)/.../lcd.c */
-ulong lcd_setmem (ulong);
-
-/* $(CPU)/.../video.c */
-ulong video_setmem (ulong);
-
/* arch/$(ARCH)/lib/cache.c */
void enable_caches(void);
void flush_cache (unsigned long, unsigned long);
@@ -428,51 +305,6 @@
ulong usec2ticks (unsigned long usec);
ulong ticks2usec (unsigned long ticks);
-/* lib/gunzip.c */
-int gzip_parse_header(const unsigned char *src, unsigned long len);
-int gunzip(void *, int, unsigned char *, unsigned long *);
-int zunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp,
- int stoponerr, int offset);
-
-/**
- * gzwrite progress indicators: defined weak to allow board-specific
- * overrides:
- *
- * gzwrite_progress_init called on startup
- * gzwrite_progress called during decompress/write loop
- * gzwrite_progress_finish called at end of loop to
- * indicate success (retcode=0) or failure
- */
-void gzwrite_progress_init(u64 expected_size);
-
-void gzwrite_progress(int iteration,
- u64 bytes_written,
- u64 total_bytes);
-
-void gzwrite_progress_finish(int retcode,
- u64 totalwritten,
- u64 totalsize,
- u32 expected_crc,
- u32 calculated_crc);
-
-/**
- * decompress and write gzipped image from memory to block device
- *
- * @param src compressed image address
- * @param len compressed image length in bytes
- * @param dev block device descriptor
- * @param szwritebuf bytes per write (pad to erase size)
- * @param startoffs offset in bytes of first write
- * @param szexpected expected uncompressed length
- * may be zero to use gzip trailer
- * for files under 4GiB
- */
-int gzwrite(unsigned char *src, int len,
- struct blk_desc *dev,
- unsigned long szwritebuf,
- u64 startoffs,
- u64 szexpected);
-
/* lib/lz4_wrapper.c */
int ulz4fn(const void *src, size_t srcn, void *dst, size_t *dstn);
@@ -506,13 +338,6 @@
int serial_printf (const char *fmt, ...)
__attribute__ ((format (__printf__, 1, 2)));
-/* lib/gzip.c */
-int gzip(void *dst, unsigned long *lenp,
- unsigned char *src, unsigned long srclen);
-int zzip(void *dst, unsigned long *lenp, unsigned char *src,
- unsigned long srclen, int stoponerr,
- int (*func)(unsigned long, unsigned long));
-
/* lib/net_utils.c */
#include <net.h>
static inline struct in_addr env_get_ip(char *var)
@@ -520,8 +345,6 @@
return string_to_ip(env_get(var));
}
-int pcmcia_init (void);
-
#ifdef CONFIG_LED_STATUS
# include <status_led.h>
#endif
@@ -575,7 +398,7 @@
/* Pull in stuff for the build system */
#ifdef DO_DEPS_ONLY
-# include <environment.h>
+# include <env_internal.h>
#endif
#endif /* __COMMON_H_ */
diff --git a/include/config_defaults.h b/include/config_defaults.h
index 4ed0968..d211a41 100644
--- a/include/config_defaults.h
+++ b/include/config_defaults.h
@@ -9,11 +9,4 @@
#ifndef _CONFIG_DEFAULTS_H_
#define _CONFIG_DEFAULTS_H_
-/* Support bootm-ing different OSes */
-#define CONFIG_BOOTM_LINUX 1
-#define CONFIG_BOOTM_NETBSD 1
-#define CONFIG_BOOTM_PLAN9 1
-#define CONFIG_BOOTM_RTEMS 1
-#define CONFIG_BOOTM_VXWORKS 1
-
#endif
diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h
index 26e61ef..3570a32 100644
--- a/include/config_distro_bootcmd.h
+++ b/include/config_distro_bootcmd.h
@@ -254,11 +254,11 @@
#endif
#if defined(CONFIG_DM_PCI)
-#define BOOTENV_RUN_NET_PCI_ENUM "run boot_net_pci_enum; "
+#define BOOTENV_RUN_PCI_ENUM "run boot_pci_enum; "
#define BOOTENV_SHARED_PCI \
- "boot_net_pci_enum=pci enum\0"
+ "boot_pci_enum=pci enum\0"
#else
-#define BOOTENV_RUN_NET_PCI_ENUM
+#define BOOTENV_RUN_PCI_ENUM
#define BOOTENV_SHARED_PCI
#endif
@@ -281,10 +281,24 @@
#endif
#ifdef CONFIG_CMD_VIRTIO
-#define BOOTENV_SHARED_VIRTIO BOOTENV_SHARED_BLKDEV(virtio)
+#define BOOTENV_RUN_VIRTIO_INIT "run virtio_init; "
+#define BOOTENV_SET_VIRTIO_NEED_INIT "virtio_need_init=; "
+#define BOOTENV_SHARED_VIRTIO \
+ "virtio_init=" \
+ "if ${virtio_need_init}; then " \
+ "virtio_need_init=false; " \
+ "virtio scan; " \
+ "fi\0" \
+ \
+ "virtio_boot=" \
+ BOOTENV_RUN_PCI_ENUM \
+ BOOTENV_RUN_VIRTIO_INIT \
+ BOOTENV_SHARED_BLKDEV_BODY(virtio)
#define BOOTENV_DEV_VIRTIO BOOTENV_DEV_BLKDEV
#define BOOTENV_DEV_NAME_VIRTIO BOOTENV_DEV_NAME_BLKDEV
#else
+#define BOOTENV_RUN_VIRTIO_INIT
+#define BOOTENV_SET_VIRTIO_NEED_INIT
#define BOOTENV_SHARED_VIRTIO
#define BOOTENV_DEV_VIRTIO \
BOOT_TARGET_DEVICES_references_VIRTIO_without_CONFIG_CMD_VIRTIO
@@ -350,7 +364,7 @@
#define BOOTENV_DEV_DHCP(devtypeu, devtypel, instance) \
"bootcmd_dhcp=" \
BOOTENV_RUN_NET_USB_START \
- BOOTENV_RUN_NET_PCI_ENUM \
+ BOOTENV_RUN_PCI_ENUM \
"if dhcp ${scriptaddr} ${boot_script_dhcp}; then " \
"source ${scriptaddr}; " \
"fi;" \
@@ -369,7 +383,7 @@
#define BOOTENV_DEV_PXE(devtypeu, devtypel, instance) \
"bootcmd_pxe=" \
BOOTENV_RUN_NET_USB_START \
- BOOTENV_RUN_NET_PCI_ENUM \
+ BOOTENV_RUN_PCI_ENUM \
"dhcp; " \
"if pxe get; then " \
"pxe boot; " \
@@ -465,6 +479,7 @@
"distro_bootcmd=" BOOTENV_SET_SCSI_NEED_INIT \
BOOTENV_SET_NVME_NEED_INIT \
BOOTENV_SET_IDE_NEED_INIT \
+ BOOTENV_SET_VIRTIO_NEED_INIT \
"for target in ${boot_targets}; do " \
"run bootcmd_${target}; " \
"done\0"
diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h
index 49ed668..f214dc9 100644
--- a/include/configs/M5249EVB.h
+++ b/include/configs/M5249EVB.h
@@ -36,7 +36,6 @@
*/
#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
-#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 7640d76..7352e34 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -347,10 +347,6 @@
#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"hostname=mpc8349emds\0" \
diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h
index 493f6df..2ae1069 100644
--- a/include/configs/MPC8349EMDS_SDRAM.h
+++ b/include/configs/MPC8349EMDS_SDRAM.h
@@ -404,10 +404,6 @@
#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"hostname=mpc8349emds\0" \
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index b37601c..3a8c074 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -18,8 +18,6 @@
#define CONFIG_PCI1 /* PCI controller 1 */
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#undef CONFIG_PCI2
-#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_ENV_OVERWRITE
@@ -289,7 +287,7 @@
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
/* Serial Port */
@@ -343,24 +341,18 @@
#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
#ifdef CONFIG_PCIE1
-#define CONFIG_SYS_PCIE1_NAME "Slot"
#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull
#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull
#else
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
#endif
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
#endif
/*
@@ -386,6 +378,20 @@
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
+#if !defined(CONFIG_DM_PCI)
+#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1
+#define CONFIG_SYS_PCIE1_NAME "Slot"
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
+#endif
+
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif /* CONFIG_PCI */
diff --git a/include/configs/MigoR.h b/include/configs/MigoR.h
index e4ebd33..64172f3 100644
--- a/include/configs/MigoR.h
+++ b/include/configs/MigoR.h
@@ -11,7 +11,6 @@
#define CONFIG_CPU_SH7722 1
#define CONFIG_DISPLAY_BOARDINFO
-#undef CONFIG_SHOW_BOOT_PROGRESS
/* SMC9111 */
#define CONFIG_SMC91111
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index e196f3c..f8cfef7 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -37,7 +37,6 @@
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_SYS_SRIO
@@ -354,60 +353,21 @@
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
-#else
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
-#endif
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
-#endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
-#else
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
-#endif
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
-#else
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
-#endif
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
-#else
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
-#endif
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
/* Qman/Bman */
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
@@ -483,7 +443,22 @@
#endif
#ifdef CONFIG_PCI
+#if !defined(CONFIG_DM_PCI)
+#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
+#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
+#endif
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif /* CONFIG_PCI */
diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h
index 1539e8f..f24cd23 100644
--- a/include/configs/SBx81LIFKW.h
+++ b/include/configs/SBx81LIFKW.h
@@ -83,7 +83,6 @@
/*
* Other required minimal configurations
*/
-#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */
#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */
#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h
index af19193..b602323 100644
--- a/include/configs/SBx81LIFXCAT.h
+++ b/include/configs/SBx81LIFXCAT.h
@@ -83,7 +83,6 @@
/*
* Other required minimal configurations
*/
-#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */
#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */
#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 5ab51e3..8c1434f 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -494,96 +494,48 @@
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
-#ifdef CONFIG_ARCH_T1040
-#define CONFIG_PCIE4 /* PCIE controller 4 */
-#endif
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-#define CONFIG_PCI_INDIRECT_BRIDGE
#ifdef CONFIG_PCI
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#ifdef CONFIG_PCIE1
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
-#else
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
-#endif
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
#endif
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#ifdef CONFIG_PCIE2
#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000
-#endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
-#else
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
-#endif
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
#endif
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#ifdef CONFIG_PCIE3
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
-#else
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
-#endif
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
-#else
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
-#endif
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
#endif
-/* controller 4, Base address 203000, to be removed */
-#ifdef CONFIG_PCIE4
-#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
-#else
-#define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000
-#define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000
-#endif
-#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
-#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
-#else
-#define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000
-#endif
-#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
+#if !defined(CONFIG_DM_PCI)
+#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
+#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
+#define CONFIG_PCI_INDIRECT_BRIDGE
#endif
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 56ddef0..53ee148 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -145,13 +145,11 @@
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
#define CONFIG_PCIE4 /* PCIE controller 4 */
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_ENV_OVERWRITE
@@ -524,51 +522,55 @@
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#ifdef CONFIG_PCIE1
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
#endif
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#ifdef CONFIG_PCIE2
#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
#endif
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#ifdef CONFIG_PCIE3
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
#endif
/* controller 4, Base address 203000 */
#ifdef CONFIG_PCIE4
#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
-#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
-#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
-#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
-#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
#endif
+#if !defined(CONFIG_DM_PCI)
+#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
+#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
+#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#endif
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif /* CONFIG_PCI */
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index ab92ca3..3d95c4a 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -433,49 +433,51 @@
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
#define CONFIG_PCIE4 /* PCIE controller 4 */
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
/* controller 4, Base address 203000 */
#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
-#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
-#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
-#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
#ifdef CONFIG_PCI
+#if !defined(CONFIG_DM_PCI)
+#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
+#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
+#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
#define CONFIG_PCI_INDIRECT_BRIDGE
+#endif
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index 0accdc6..57d8d17 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -61,7 +61,6 @@
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_ENV_OVERWRITE
@@ -176,44 +175,48 @@
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
/* controller 4, Base address 203000 */
#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
-#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
-#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
#ifdef CONFIG_PCI
+#if !defined(CONFIG_DM_PCI)
+#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
+#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
+#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
#define CONFIG_PCI_INDIRECT_BRIDGE
+#endif
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif /* CONFIG_PCI */
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 0da34d0..9bf5d9d 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -236,10 +236,6 @@
/* default location for tftp and bootm */
#define CONFIG_LOADADDR 400000
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"hostname=tqm834x\0" \
diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h
index 268a41c..6a01a90 100644
--- a/include/configs/UCP1020.h
+++ b/include/configs/UCP1020.h
@@ -438,7 +438,6 @@
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_MMC_SPI
#endif
/* Misc Extra Settings */
diff --git a/include/configs/advantech_dms-ba16.h b/include/configs/advantech_dms-ba16.h
index 22d1e41..1298859 100644
--- a/include/configs/advantech_dms-ba16.h
+++ b/include/configs/advantech_dms-ba16.h
@@ -39,7 +39,6 @@
#define CONFIG_LBA48
/* MMC Configs */
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
/* USB Configs */
@@ -223,7 +222,6 @@
#define CONFIG_IMX_VIDEO_SKIP
#endif
-#define CONFIG_PWM_IMX
#define CONFIG_IMX6_PWM_PER_CLK 66000000
#ifdef CONFIG_CMD_PCI
diff --git a/include/configs/alt.h b/include/configs/alt.h
index eb7eb55..bb52675 100644
--- a/include/configs/alt.h
+++ b/include/configs/alt.h
@@ -45,7 +45,6 @@
/* SPL support */
#define CONFIG_SPL_STACK 0xe6340000
#define CONFIG_SPL_MAX_SIZE 0x4000
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
#ifdef CONFIG_SPL_BUILD
#define CONFIG_CONS_SCIF2
#define CONFIG_SH_SCIF_CLK_FREQ 65000000
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index b5fba0a..be57106 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -31,9 +31,6 @@
#define V_OSCK 24000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
-/* Always 128 KiB env size */
-#define CONFIG_ENV_SIZE SZ_128K
-
#ifdef CONFIG_NAND
#define NANDARGS \
"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
@@ -277,7 +274,6 @@
*/
#if defined(CONFIG_SPI_BOOT)
/* SPL related */
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */
diff --git a/include/configs/am335x_igep003x.h b/include/configs/am335x_igep003x.h
index 5fe7565..5b5e160 100644
--- a/include/configs/am335x_igep003x.h
+++ b/include/configs/am335x_igep003x.h
@@ -20,8 +20,6 @@
#define V_OSCK 24000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
-#define CONFIG_ENV_SIZE (96 << 10) /* 96 KiB */
-
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
@@ -108,27 +106,6 @@
/* NAND support */
#define CONFIG_SYS_NAND_ONFI_DETECTION 1
-/* SPL */
-
-/* UBI configuration */
-#define CONFIG_SPL_UBI 1
-#define CONFIG_SPL_UBI_MAX_VOL_LEBS 256
-#define CONFIG_SPL_UBI_MAX_PEB_SIZE (256*1024)
-#define CONFIG_SPL_UBI_MAX_PEBS 4096
-#define CONFIG_SPL_UBI_VOL_IDS 8
-#define CONFIG_SPL_UBI_LOAD_MONITOR_ID 0
-#define CONFIG_SPL_UBI_LOAD_KERNEL_ID 3
-#define CONFIG_SPL_UBI_LOAD_ARGS_ID 4
-#define CONFIG_SPL_UBI_PEB_OFFSET 4
-#define CONFIG_SPL_UBI_VID_OFFSET 512
-#define CONFIG_SPL_UBI_LEB_START 2048
-#define CONFIG_SPL_UBI_INFO_ADDR 0x88080000
-
-/* environment organization */
-#define CONFIG_ENV_UBI_PART "UBI"
-#define CONFIG_ENV_UBI_VOLUME "config"
-#define CONFIG_ENV_UBI_VOLUME_REDUND "config_r"
-
/* NAND config */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
diff --git a/include/configs/am335x_shc.h b/include/configs/am335x_shc.h
index 6368872..f4a000f 100644
--- a/include/configs/am335x_shc.h
+++ b/include/configs/am335x_shc.h
@@ -258,6 +258,4 @@
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_I2C_SPEED 400000
#define CONFIG_SYS_I2C_SLAVE 1
-
-#define CONFIG_SHOW_BOOT_PROGRESS
#endif /* ! __CONFIG_AM335X_SHC_H */
diff --git a/include/configs/am335x_sl50.h b/include/configs/am335x_sl50.h
index 381c75e..a08e6bf 100644
--- a/include/configs/am335x_sl50.h
+++ b/include/configs/am335x_sl50.h
@@ -22,9 +22,6 @@
#define V_OSCK 24000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
-/* Always 128 KiB env size */
-#define CONFIG_ENV_SIZE (128 << 10)
-
#ifndef CONFIG_SPL_BUILD
#define MEM_LAYOUT_ENV_SETTINGS \
diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h
index 2c51026..5fa393d 100644
--- a/include/configs/am3517_crane.h
+++ b/include/configs/am3517_crane.h
@@ -31,7 +31,6 @@
/*
* Size of malloc() pool
*/
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
/* initial data */
/*
@@ -69,15 +68,6 @@
*/
#ifdef CONFIG_USB_AM35X
-
-#ifdef CONFIG_USB_MUSB_HCD
-
-#ifdef CONFIG_USB_KEYBOARD
-#define CONFIG_PREBOOT "usb start"
-#endif /* CONFIG_USB_KEYBOARD */
-
-#endif /* CONFIG_USB_MUSB_HCD */
-
#ifdef CONFIG_USB_MUSB_UDC
/* USB device configuration */
#define CONFIG_USB_DEVICE 1
@@ -192,7 +182,6 @@
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB sector */
-#define CONFIG_ENV_OFFSET 0x260000
#define CONFIG_ENV_ADDR 0x260000
/*-----------------------------------------------------------------------
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 9475e99..3e5f0b1 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -14,7 +14,6 @@
#include <configs/ti_omap3_common.h>
-#undef CONFIG_DM_I2C_COMPAT
#define CONFIG_REVISION_TAG
/* Hardware drivers */
@@ -27,18 +26,11 @@
* Enable CONFIG_USB_MUSB_HOST for Host functionalities MSC, keyboard
* Enable CONFIG_USB_MUSB_GADGET for Device functionalities.
*/
-
-#ifdef CONFIG_USB_MUSB_AM35X
-
-#ifdef CONFIG_USB_MUSB_HOST
-
-#ifdef CONFIG_USB_KEYBOARD
-#define CONFIG_PREBOOT "usb start"
-#endif /* CONFIG_USB_KEYBOARD */
-
-#endif /* CONFIG_USB_MUSB_HOST */
-
-#endif /* CONFIG_USB_MUSB_AM35X */
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_USB_EHCI_OMAP
+#else
+#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57
+#endif
/* I2C */
@@ -184,8 +176,6 @@
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_ENV_SIZE CONFIG_SYS_ENV_SECT_SIZE
-#define CONFIG_ENV_OFFSET 0x260000
#define CONFIG_ENV_ADDR 0x260000
/* Defines for SPL */
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index ef85cd2..d355b80 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -8,7 +8,6 @@
#ifndef __CONFIG_AM43XX_EVM_H
#define __CONFIG_AM43XX_EVM_H
-#define CONFIG_ARCH_CPU_INIT
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 21) /* 2GB */
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
@@ -59,9 +58,6 @@
/* Now bring in the rest of the common code. */
#include <configs/ti_armv7_omap.h>
-/* Always 64 KiB env size */
-#define CONFIG_ENV_SIZE (64 << 10)
-
/* Clock Defines */
#define V_OSCK 24000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
@@ -114,8 +110,6 @@
#ifdef CONFIG_QSPI_BOOT
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64 KB sectors */
-#define CONFIG_ENV_OFFSET 0x110000
#define CONFIG_ENV_OFFSET_REDUND 0x120000
#endif
diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h
index 9a39cd6..531f79e 100644
--- a/include/configs/am57xx_evm.h
+++ b/include/configs/am57xx_evm.h
@@ -19,14 +19,12 @@
/* MMC ENV related defines */
#define CONFIG_SYS_MMC_ENV_DEV 1 /* eMMC */
#define CONFIG_SYS_MMC_ENV_PART 0
-#define CONFIG_ENV_SIZE SZ_128K
-#define CONFIG_ENV_OFFSET 0x260000
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_SYS_BOOTM_LEN SZ_64M
-#define CONSOLEDEV "ttyO2"
+#define CONSOLEDEV "ttyS2"
#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */
#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */
#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */
@@ -92,6 +90,5 @@
#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000
/* SPI SPL */
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
#endif /* __CONFIG_AM57XX_EVM_H */
diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h
index b043bf8..0249a20 100644
--- a/include/configs/am65x_evm.h
+++ b/include/configs/am65x_evm.h
@@ -19,6 +19,32 @@
#define CONFIG_SYS_SDRAM_BASE1 0x880000000
/* SPL Loader Configuration */
+#ifdef CONFIG_TARGET_AM654_A53_EVM
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \
+ CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE)
+#else
+/*
+ * Maximum size in memory allocated to the SPL BSS. Keep it as tight as
+ * possible (to allow the build to go through), as this directly affects
+ * our memory footprint. The less we use for BSS the more we have available
+ * for everything else.
+ */
+#define CONFIG_SPL_BSS_MAX_SIZE 0x5000
+/*
+ * Link BSS to be within SPL in a dedicated region located near the top of
+ * the MCU SRAM, this way making it available also before relocation. Note
+ * that we are not using the actual top of the MCU SRAM as there is a memory
+ * location filled in by the boot ROM that we want to read out without any
+ * interference from the C context.
+ */
+#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX -\
+ CONFIG_SPL_BSS_MAX_SIZE)
+/* Set the stack right below the SPL BSS section */
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_BSS_START_ADDR
+/* Configure R5 SPL post-relocation malloc pool in DDR */
+#define CONFIG_SYS_SPL_MALLOC_START 0x84000000
+#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M
+#endif
#ifdef CONFIG_SYS_K3_SPL_ATF
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin"
@@ -29,26 +55,25 @@
#endif
#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \
- CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE - 4)
#define CONFIG_SYS_BOOTM_LEN SZ_64M
+#define PARTS_DEFAULT \
+ /* Linux partitions */ \
+ "name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0"
+
/* U-Boot general configuration */
#define EXTRA_ENV_AM65X_BOARD_SETTINGS \
"findfdt=" \
- "if test $board_name = am65x; then " \
- "setenv name_fdt k3-am654-base-board.dtb; " \
- "else if test $name_fdt = undefined; then " \
- "echo WARNING: Could not determine device tree to use;"\
- "fi; fi; " \
+ "setenv name_fdt k3-am654-base-board.dtb;" \
"setenv fdtfile ${name_fdt}\0" \
"loadaddr=0x80080000\0" \
"fdtaddr=0x82000000\0" \
+ "overlayaddr=0x83000000\0" \
"name_kern=Image\0" \
"console=ttyS2,115200n8\0" \
"args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000\0" \
- "run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0"
+ "run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0" \
/* U-Boot MMC-specific configuration */
#define EXTRA_ENV_AM65X_BOARD_SETTINGS_MMC \
@@ -59,15 +84,39 @@
"rd_spec=-\0" \
"init_mmc=run args_all args_mmc\0" \
"get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}\0" \
+ "get_overlay_mmc=" \
+ "fdt address ${fdtaddr};" \
+ "fdt resize 0x100000;" \
+ "for overlay in $name_overlays;" \
+ "do;" \
+ "load mmc ${bootpart} ${overlayaddr} ${bootdir}/${overlay};" \
+ "fdt apply ${overlayaddr};" \
+ "done;\0" \
"get_kern_mmc=load mmc ${bootpart} ${loadaddr} " \
- "${bootdir}/${name_kern}\0"
+ "${bootdir}/${name_kern}\0" \
+ "get_fit_mmc=load mmc ${bootpart} ${addr_fit} " \
+ "${bootdir}/${name_fit}\0" \
+ "partitions=" PARTS_DEFAULT
/* Incorporate settings into the U-Boot environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_MMC_TI_ARGS \
+ DEFAULT_FIT_TI_ARGS \
EXTRA_ENV_AM65X_BOARD_SETTINGS \
EXTRA_ENV_AM65X_BOARD_SETTINGS_MMC
+/* MMC ENV related defines */
+#ifdef CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART 1
+#define CONFIG_ENV_SIZE (128 << 10)
+#define CONFIG_ENV_OFFSET 0x680000
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#endif
+
+#define CONFIG_SUPPORT_EMMC_BOOT
+
/* Now for the remaining common defines */
#include <configs/ti_armv7_common.h>
diff --git a/include/configs/amcore.h b/include/configs/amcore.h
index 4daa0ba..26d6fef 100644
--- a/include/configs/amcore.h
+++ b/include/configs/amcore.h
@@ -30,8 +30,6 @@
/* undef to save memory */
-#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
-
#define CONFIG_SYS_LOAD_ADDR 0x20000 /* default load address */
#define CONFIG_SYS_MEMTEST_START 0x0
diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h
index 780ae61..3a8d2d4 100644
--- a/include/configs/apalis-imx8.h
+++ b/include/configs/apalis-imx8.h
@@ -13,10 +13,6 @@
#define CONFIG_DISPLAY_BOARDINFO_LATE
-#undef CONFIG_BOOTM_NETBSD
-
-#define CONFIG_FSL_ESDHC
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5b010000
#define USDHC2_BASE_ADDR 0x5b020000
diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h
index b4ddd1b..dacf36b 100644
--- a/include/configs/apalis-tk1.h
+++ b/include/configs/apalis-tk1.h
@@ -18,6 +18,9 @@
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
+#define FDT_MODULE "apalis-v1.2"
+#define FDT_MODULE_V1_0 "apalis"
+
/* Environment in eMMC, before config block at the end of 1st "boot sector" */
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \
CONFIG_TDX_CFG_BLOCK_OFFSET)
@@ -42,7 +45,7 @@
#define DFU_ALT_EMMC_INFO "apalis-tk1.img raw 0x0 0x500 mmcpart 1; " \
"boot part 0 1 mmcpart 0; " \
"rootfs part 0 2 mmcpart 0; " \
- "uImage fat 0 1 mmcpart 0; " \
+ "zImage fat 0 1 mmcpart 0; " \
"tegra124-apalis-eval.dtb fat 0 1 mmcpart 0"
#define EMMC_BOOTCMD \
@@ -54,11 +57,11 @@
"run emmcdtbload; " \
"load mmc ${emmcdev}:${emmcbootpart} ${kernel_addr_r} " \
"${boot_file} && run fdt_fixup && " \
- "bootm ${kernel_addr_r} - ${dtbparam}\0" \
+ "bootz ${kernel_addr_r} - ${dtbparam}\0" \
"emmcbootpart=1\0" \
"emmcdev=0\0" \
"emmcdtbload=setenv dtbparam; load mmc ${emmcdev}:${emmcbootpart} " \
- "${fdt_addr_r} ${soc}-apalis-${fdt_board}.dtb && " \
+ "${fdt_addr_r} ${soc}-${fdt_module}-${fdt_board}.dtb && " \
"setenv dtbparam ${fdt_addr_r}\0" \
"emmcfinduuid=part uuid mmc ${mmcdev}:${emmcrootpart} uuid\0" \
"emmcrootpart=2\0"
@@ -68,9 +71,9 @@
"nfsboot=pci enum; run setup; setenv bootargs ${defargs} ${nfsargs} " \
"${setupargs} ${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \
"run nfsdtbload; dhcp ${kernel_addr_r} " \
- "&& run fdt_fixup && bootm ${kernel_addr_r} - ${dtbparam}\0" \
+ "&& run fdt_fixup && bootz ${kernel_addr_r} - ${dtbparam}\0" \
"nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} " \
- "${soc}-apalis-${fdt_board}.dtb " \
+ "${soc}-${fdt_module}-${fdt_board}.dtb " \
"&& setenv dtbparam ${fdt_addr_r}\0"
#define SD_BOOTCMD \
@@ -81,44 +84,28 @@
"${vidargs}; echo Booting from SD card in 8bit slot...; " \
"run sddtbload; load mmc ${sddev}:${sdbootpart} " \
"${kernel_addr_r} ${boot_file} && run fdt_fixup && " \
- "bootm ${kernel_addr_r} - ${dtbparam}\0" \
+ "bootz ${kernel_addr_r} - ${dtbparam}\0" \
"sdbootpart=1\0" \
"sddev=1\0" \
"sddtbload=setenv dtbparam; load mmc ${sddev}:${sdbootpart} " \
- "${fdt_addr_r} ${soc}-apalis-${fdt_board}.dtb " \
+ "${fdt_addr_r} ${soc}-${fdt_module}-${fdt_board}.dtb " \
"&& setenv dtbparam ${fdt_addr_r}\0" \
"sdfinduuid=part uuid mmc ${sddev}:${sdrootpart} uuid\0" \
"sdrootpart=2\0"
-#define USB_BOOTCMD \
- "set_usbargs=setenv usbargs ip=off root=PARTUUID=${uuid} ro " \
- "rootfstype=ext4 rootwait\0" \
- "usbboot=run setup; usb start; run usbfinduuid; run set_usbargs; " \
- "setenv bootargs ${defargs} ${setupargs} " \
- "${usbargs} ${vidargs}; echo Booting from USB stick...; " \
- "run usbdtbload; load usb ${usbdev}:${usbbootpart} " \
- "${kernel_addr_r} ${boot_file} && run fdt_fixup && " \
- "bootm ${kernel_addr_r} - ${dtbparam}\0" \
- "usbbootpart=1\0" \
- "usbdev=0\0" \
- "usbdtbload=setenv dtbparam; load usb ${usbdev}:${usbbootpart} " \
- "${fdt_addr_r} ${soc}-apalis-${fdt_board}.dtb " \
- "&& setenv dtbparam ${fdt_addr_r}\0" \
- "usbfinduuid=part uuid usb ${usbdev}:${usbrootpart} uuid\0" \
- "usbrootpart=2\0"
-
#define BOARD_EXTRA_ENV_SETTINGS \
- "boot_file=uImage\0" \
+ "boot_file=zImage\0" \
"console=ttyS0\0" \
"defargs=lp0_vec=2064@0xf46ff000 core_edp_mv=1150 core_edp_ma=4000 " \
- "usb_port_owner_info=2 lane_owner_info=6 emc_max_dvfs=0\0" \
+ "usb_port_owner_info=2 lane_owner_info=6 emc_max_dvfs=0 " \
+ "user_debug=30 pcie_aspm=off\0" \
"dfu_alt_info=" DFU_ALT_EMMC_INFO "\0" \
EMMC_BOOTCMD \
"fdt_board=eval\0" \
"fdt_fixup=;\0" \
+ "fdt_module=" FDT_MODULE "\0" \
NFS_BOOTCMD \
SD_BOOTCMD \
- USB_BOOTCMD \
"setethupdate=if env exists ethaddr; then; else setenv ethaddr " \
"00:14:2d:00:00:00; fi; pci enum && tftpboot ${loadaddr} " \
"flash_eth.img && source ${loadaddr}\0" \
@@ -135,8 +122,7 @@
"setusbupdate=usb start && setenv interface usb; setenv drive 0; " \
"load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \
"source ${loadaddr}\0" \
- USB_BOOTCMD \
- "vidargs=video=tegrafb0:640x480-16@60 fbcon=map:1\0"
+ "vidargs=fbcon=map:1\0"
/* Increase console I/O buffer size */
#undef CONFIG_SYS_CBSIZE
diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h
index db37fa7..c3bc394 100644
--- a/include/configs/apalis_imx6.h
+++ b/include/configs/apalis_imx6.h
@@ -42,7 +42,6 @@
#define CONFIG_SYS_MXC_I2C3_SPEED 400000
/* MMC Configs */
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 3
@@ -176,27 +175,6 @@
"sdfinduuid=part uuid mmc ${sddev}:${sdrootpart} uuid\0" \
"sdrootpart=2\0"
-
-#define USB_BOOTCMD \
- "set_usbargs=setenv usbargs ip=off root=PARTUUID=${uuid} ro,noatime " \
- "rootfstype=ext4 rootwait\0" \
- "usbboot=run setup; usb start; run usbfinduuid; run set_usbargs; " \
- "setenv bootargs ${defargs} ${setupargs} " \
- "${usbargs} ${vidargs}; echo Booting from USB stick...; " \
- "run usbdtbload; load usb " \
- "${usbdev}:${usbbootpart} ${kernel_addr_r} " \
- "${boot_file} && run fdt_fixup && " \
- "bootz ${kernel_addr_r} ${dtbparam}\0" \
- "usbbootpart=1\0" \
- "usbdev=0\0" \
- "usbdtbload=setenv dtbparam; load usb ${usbdev}:${usbbootpart} "\
- "${fdt_addr_r} " \
- "${fdt_file} && setenv dtbparam \" - " \
- "${fdt_addr_r}\" && true\0" \
- "usbfinduuid=part uuid usb ${usbdev}:${usbrootpart} uuid\0" \
- "usbrootpart=2\0"
-
-
#ifndef CONFIG_TDX_APALIS_IMX6_V1_0
#define FDT_FILE "imx6q-apalis-eval.dtb"
#define FDT_FILE_V1_0 "imx6q-apalis_v1_0-eval.dtb"
@@ -219,7 +197,6 @@
MEM_LAYOUT_ENV_SETTINGS \
NFS_BOOTCMD \
SD_BOOTCMD \
- USB_BOOTCMD \
"setethupdate=if env exists ethaddr; then; else setenv ethaddr " \
"00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \
"flash_eth.img && source ${loadaddr}\0" \
@@ -236,6 +213,7 @@
"load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \
"source ${loadaddr}\0" \
"splashpos=m,m\0" \
+ "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \
"vidargs=mxc_hdmi.only_cea=1 " \
"video=mxcfb0:dev=hdmi,1920x1080M@60,if=RGB24 " \
"video=mxcfb1:off video=mxcfb2:off video=mxcfb3:off " \
diff --git a/include/configs/apf27.h b/include/configs/apf27.h
index b7a7ec5..044ce44 100644
--- a/include/configs/apf27.h
+++ b/include/configs/apf27.h
@@ -83,7 +83,6 @@
#define CONFIG_SYS_CBSIZE 2048 /* console I/O buffer */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* Boot argument buffer size */
-#define CONFIG_PREBOOT "run check_flash check_env;"
/*
* Boot Linux
diff --git a/include/configs/aristainetos-common.h b/include/configs/aristainetos-common.h
index a248146..e998d9b 100644
--- a/include/configs/aristainetos-common.h
+++ b/include/configs/aristainetos-common.h
@@ -196,7 +196,6 @@
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_IMX_VIDEO_SKIP
-#define CONFIG_PWM_IMX
#define CONFIG_IMX6_PWM_PER_CLK 66000000
#endif /* __ARISTAINETOS_COMMON_CONFIG_H */
diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h
index 00e5667..361e6ac 100644
--- a/include/configs/aristainetos2.h
+++ b/include/configs/aristainetos2.h
@@ -45,9 +45,6 @@
#define CONFIG_LG4573_BUS 0
#define CONFIG_LG4573_CS 0
-#define CONFIG_PWM_IMX
-#define CONFIG_IMX6_PWM_PER_CLK 66000000
-
#include "aristainetos-common.h"
#endif /* __ARISTAINETOS2_CONFIG_H */
diff --git a/include/configs/aristainetos2b.h b/include/configs/aristainetos2b.h
index cfe0e05..cdeb7a3 100644
--- a/include/configs/aristainetos2b.h
+++ b/include/configs/aristainetos2b.h
@@ -45,9 +45,6 @@
#define CONFIG_LG4573_BUS 0
#define CONFIG_LG4573_CS 1
-#define CONFIG_PWM_IMX
-#define CONFIG_IMX6_PWM_PER_CLK 66000000
-
#include "aristainetos-common.h"
#endif /* __ARISTAINETOS2B_CONFIG_H */
diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h
index 0cb40e7..c3cccee 100644
--- a/include/configs/armadillo-800eva.h
+++ b/include/configs/armadillo-800eva.h
@@ -14,9 +14,6 @@
#define BOARD_LATE_INIT
-#undef CONFIG_SHOW_BOOT_PROGRESS
-
-#define CONFIG_ARCH_CPU_INIT
#define CONFIG_TMU_TIMER
#define CONFIG_SYS_TIMER_COUNTS_DOWN
#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */
diff --git a/include/configs/arndale.h b/include/configs/arndale.h
index 841f361..8aa6e1d 100644
--- a/include/configs/arndale.h
+++ b/include/configs/arndale.h
@@ -29,8 +29,6 @@
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK
-#define CONFIG_PREBOOT
-
#define CONFIG_S5P_PA_SYSRAM 0x02020000
#define CONFIG_SMP_PEN_ADDR CONFIG_S5P_PA_SYSRAM
diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h
index 30c6cd4..6131277 100644
--- a/include/configs/at91-sama5_common.h
+++ b/include/configs/at91-sama5_common.h
@@ -13,8 +13,6 @@
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
-#define CONFIG_ARCH_CPU_INIT
-
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
@@ -37,13 +35,7 @@
#ifdef CONFIG_SD_BOOT
#ifdef CONFIG_ENV_IS_IN_MMC
-/* Use raw reserved sectors to save environment */
-#define CONFIG_ENV_OFFSET 0x2000
-#define CONFIG_ENV_SIZE 0x1000
#define CONFIG_SYS_MMC_ENV_DEV 0
-#else
-/* u-boot env in sd/mmc card */
-#define CONFIG_ENV_SIZE 0x4000
#endif
#define CONFIG_BOOTCOMMAND "if test ! -n ${dtb_name}; then " \
@@ -57,21 +49,21 @@
#ifdef CONFIG_NAND_BOOT
/* u-boot env in nand flash */
-#define CONFIG_ENV_OFFSET 0x140000
#define CONFIG_ENV_OFFSET_REDUND 0x100000
-#define CONFIG_ENV_SIZE 0x20000
#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0x180000 0x80000;" \
"nand read 0x22000000 0x200000 0x600000;" \
"bootz 0x22000000 - 0x21000000"
#elif CONFIG_SPI_BOOT
/* u-boot env in serial flash, by default is bus 0 and cs 0 */
-#define CONFIG_ENV_OFFSET 0x6000
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x1000
#define CONFIG_BOOTCOMMAND "sf probe 0; " \
"sf read 0x21000000 0x60000 0xc000; " \
"sf read 0x22000000 0x6c000 0x394000; " \
"bootz 0x22000000 - 0x21000000"
+#elif CONFIG_QSPI_BOOT
+#define CONFIG_BOOTCOMMAND "sf probe 0; " \
+ "sf read 0x21000000 0x180000 0x80000; " \
+ "sf read 0x22000000 0x200000 0x600000; " \
+ "bootz 0x22000000 - 0x21000000"
#endif
#endif
diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h
index e2a2f3b..8bfba35 100644
--- a/include/configs/at91rm9200ek.h
+++ b/include/configs/at91rm9200ek.h
@@ -145,7 +145,7 @@
*/
#define CONFIG_ENV_ADDR \
(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_SIZE SZ_64K /* sectors are 64K here */
+
/* The following #defines are needed to get flash environment right */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN SZ_256K
diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h
index 95710fb..b283c9d 100644
--- a/include/configs/at91sam9260ek.h
+++ b/include/configs/at91sam9260ek.h
@@ -35,7 +35,6 @@
#endif
/* Misc CPU related */
-#define CONFIG_ARCH_CPU_INIT
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index 6b1db9f..3e7adf6 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -20,8 +20,6 @@
#define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
-#define CONFIG_ARCH_CPU_INIT
-
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h
index e9b97b6..bc79e17 100644
--- a/include/configs/at91sam9n12ek.h
+++ b/include/configs/at91sam9n12ek.h
@@ -151,11 +151,6 @@
#ifdef CONFIG_SD_BOOT
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-
-#elif CONFIG_SYS_USE_NANDFLASH
-#elif CONFIG_SPI_BOOT
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400
-
#elif CONFIG_NAND_BOOT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h
index 3e18716..1c67be5 100644
--- a/include/configs/at91sam9rlek.h
+++ b/include/configs/at91sam9rlek.h
@@ -16,7 +16,6 @@
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */
-#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h
index 9353de7..f9a100b 100644
--- a/include/configs/at91sam9x5ek.h
+++ b/include/configs/at91sam9x5ek.h
@@ -72,32 +72,21 @@
#ifdef CONFIG_NAND_BOOT
/* bootstrap + u-boot + env + linux in nandflash */
-#define CONFIG_ENV_OFFSET 0x140000
#define CONFIG_ENV_OFFSET_REDUND 0x100000
-#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
#define CONFIG_BOOTCOMMAND "nand read " \
"0x22000000 0x200000 0x600000; " \
"nand read 0x21000000 0x180000 0x20000; " \
"bootz 0x22000000 - 0x21000000"
#elif defined(CONFIG_SPI_BOOT)
/* bootstrap + u-boot + env + linux in spi flash */
-#define CONFIG_ENV_OFFSET 0x5000
-#define CONFIG_ENV_SIZE 0x3000
-#define CONFIG_ENV_SECT_SIZE 0x1000
#define CONFIG_BOOTCOMMAND "sf probe 0; " \
"sf read 0x22000000 0x100000 0x300000; " \
"bootm 0x22000000"
#elif defined(CONFIG_SYS_USE_DATAFLASH)
/* bootstrap + u-boot + env + linux in data flash */
-#define CONFIG_ENV_OFFSET 0x4200
-#define CONFIG_ENV_SIZE 0x4200
-#define CONFIG_ENV_SECT_SIZE 0x210
#define CONFIG_BOOTCOMMAND "sf probe 0; " \
"sf read 0x22000000 0x84000 0x294000; " \
"bootm 0x22000000"
-#else /* CONFIG_SD_BOOT */
-/* bootstrap + u-boot + env + linux in mmc */
-#define CONFIG_ENV_SIZE 0x4000
#endif
/*
@@ -124,10 +113,6 @@
#ifdef CONFIG_SD_BOOT
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-
-#elif CONFIG_SPI_BOOT
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400
-
#elif CONFIG_NAND_BOOT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
diff --git a/include/configs/baltos.h b/include/configs/baltos.h
index fbf657f..a9b14c5 100644
--- a/include/configs/baltos.h
+++ b/include/configs/baltos.h
@@ -25,9 +25,6 @@
#define V_OSCK 24000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
-/* Always 128 KiB env size */
-#define CONFIG_ENV_SIZE (128 << 10)
-
/* FIT support */
#define CONFIG_SYS_BOOTM_LEN SZ_64M
diff --git a/include/configs/bav335x.h b/include/configs/bav335x.h
index 0525efa..db21a47 100644
--- a/include/configs/bav335x.h
+++ b/include/configs/bav335x.h
@@ -31,9 +31,6 @@
#define V_OSCK 24000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
-/* Always 128 KiB env size */
-#define CONFIG_ENV_SIZE (128 << 10)
-
#ifdef CONFIG_NAND
#define NANDARGS \
"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
@@ -446,7 +443,6 @@
*/
#if defined(CONFIG_SPI_BOOT)
/* SPL related */
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */
diff --git a/include/configs/bcm23550_w1d.h b/include/configs/bcm23550_w1d.h
index deafb7b..f59cd75 100644
--- a/include/configs/bcm23550_w1d.h
+++ b/include/configs/bcm23550_w1d.h
@@ -93,8 +93,6 @@
/* version string, parser, etc */
-#define CONFIG_MX_CYCLIC
-
/* Initial upstream - boot to cmd prompt only */
#define CONFIG_BOOTCOMMAND ""
diff --git a/include/configs/bcm28155_ap.h b/include/configs/bcm28155_ap.h
index 781689a..111858f 100644
--- a/include/configs/bcm28155_ap.h
+++ b/include/configs/bcm28155_ap.h
@@ -92,8 +92,6 @@
/* version string, parser, etc */
-#define CONFIG_MX_CYCLIC
-
/* Initial upstream - boot to cmd prompt only */
#define CONFIG_BOOTCOMMAND ""
diff --git a/include/configs/bcm_ep_board.h b/include/configs/bcm_ep_board.h
index 09a5804..b67100a 100644
--- a/include/configs/bcm_ep_board.h
+++ b/include/configs/bcm_ep_board.h
@@ -51,8 +51,6 @@
/* version string, parser, etc */
-#define CONFIG_MX_CYCLIC
-
/* Enable Time Command */
#endif /* __BCM_EP_BOARD_H */
diff --git a/include/configs/bcmstb.h b/include/configs/bcmstb.h
index cc28924..b843705 100644
--- a/include/configs/bcmstb.h
+++ b/include/configs/bcmstb.h
@@ -157,10 +157,6 @@
/*
* Save the prior stage provided DTB.
*/
-#define CONFIG_PREBOOT \
- "fdt addr ${fdtcontroladdr};" \
- "fdt move ${fdtcontroladdr} ${fdtsaveaddr};" \
- "fdt addr ${fdtsaveaddr};"
/*
* Enable in-place RFS with this initrd_high setting.
*/
diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h
index 05ebb7d..285e28b 100644
--- a/include/configs/bk4r1.h
+++ b/include/configs/bk4r1.h
@@ -37,7 +37,6 @@
"run manage_userdata; "
/* Enable PREBOOT variable */
-#define CONFIG_PREBOOT
/* Set ARP_TIMEOUT to 500ms */
#define CONFIG_ARP_TIMEOUT 500UL
diff --git a/include/configs/brppt1.h b/include/configs/brppt1.h
index 82f3f1a..bc0dabb 100644
--- a/include/configs/brppt1.h
+++ b/include/configs/brppt1.h
@@ -59,9 +59,6 @@
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
#endif /* CONFIG_NAND */
-/* Always 64 KiB env size */
-#define CONFIG_ENV_SIZE (64 << 10)
-
#ifdef CONFIG_NAND
#define NANDTGTS \
"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
@@ -184,11 +181,8 @@
#if defined(CONFIG_SPI)
/* SPI Flash */
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
/* Environment */
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-#define CONFIG_ENV_OFFSET 0x20000
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
CONFIG_ENV_SECT_SIZE)
#elif defined(CONFIG_ENV_IS_IN_MMC)
diff --git a/include/configs/brsmarc1.h b/include/configs/brsmarc1.h
new file mode 100644
index 0000000..19e796e
--- /dev/null
+++ b/include/configs/brsmarc1.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * brsmarc1.h
+ *
+ * specific parts for B&R BRSMARC1 Motherboard
+ *
+ * Copyright (C) 2017 Hannes Schmelzer <oe5hpm@oevsv.at> -
+ * B&R Industrial Automation GmbH - http://www.br-automation.com
+ *
+ */
+
+#ifndef __CONFIG_BRSMARC1_H__
+#define __CONFIG_BRSMARC1_H__
+
+#include <configs/bur_cfg_common.h>
+#include <configs/bur_am335x_common.h>
+/* ------------------------------------------------------------------------- */
+#define CONFIG_BOARD_TYPES
+
+/* memory */
+#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024)
+#define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024)
+
+/* Clock Defines */
+#define V_OSCK 26000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK)
+
+#define CONFIG_MACH_TYPE 3589
+
+#ifndef CONFIG_SPL_BUILD
+
+/* Default environment */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+BUR_COMMON_ENV \
+"autoload=0\0" \
+"scradr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+"cfgscr=mw ${dtbaddr} 0;" \
+" sf probe && sf read ${scradr} 0xC0000 0x10000 && source ${scradr};" \
+" fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0" \
+"dtbaddr=0x84000000\0" \
+"loadaddr=0x82000000\0" \
+"b_break=0\0" \
+"b_tgts_std=mmc0 mmc1 def net usb0\0" \
+"b_tgts_rcy=def net usb0\0" \
+"b_tgts_pme=net usb0 mmc0 mmc1\0" \
+"b_deftgts=if test ${b_mode} = 12; then setenv b_tgts ${b_tgts_pme};" \
+" elif test ${b_mode} = 0; then setenv b_tgts ${b_tgts_rcy};" \
+" else setenv b_tgts ${b_tgts_std}; fi\0" \
+"b_mmc0=load mmc 1 ${scradr} bootscr.img && source ${scradr}\0" \
+"b_mmc1=load mmc 1 ${loadaddr} arimg.ugz && run startsys\0" \
+"b_def=sf read ${loadaddr} 100000 700000; run startsys\0" \
+"b_net=tftp ${scradr} netscript.img && source ${scradr}\0" \
+"b_usb0=usb start && load usb 0 ${scradr} bootscr.img && source ${scradr}\0" \
+"b_default=run b_deftgts; for target in ${b_tgts};"\
+" do run b_${target}; if test ${b_break} = 1; then; exit; fi; done\0" \
+"vxargs=setenv bootargs cpsw(0,0)host:vxWorks h=${serverip}" \
+" e=${ipaddr}:${netmask} g=${gatewayip} u=vxWorksFTP pw=vxWorks\0" \
+"vxfdt=fdt addr ${dtbaddr}; fdt resize 0x8000;" \
+" fdt boardsetup\0" \
+"startsys=run vxargs && mw 0x80001100 0 && run vxfdt &&" \
+" bootm ${loadaddr} - ${dtbaddr}\0"
+#endif /* !CONFIG_SPL_BUILD*/
+
+/* Support both device trees and ATAGs. */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/* SPI Flash */
+
+/* Environment */
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
+ CONFIG_ENV_SECT_SIZE)
+
+#define CONFIG_CONS_INDEX 1
+#endif /* __CONFIG_BRSMARC1_H__ */
diff --git a/include/configs/brxre1.h b/include/configs/brxre1.h
index 7309e7d..c6e308b 100644
--- a/include/configs/brxre1.h
+++ b/include/configs/brxre1.h
@@ -58,11 +58,6 @@
#define CONFIG_BOOTCOMMAND "mmc dev 1; run b_default"
-/* undefine command which we not need here */
-#undef CONFIG_BOOTM_NETBSD
-#undef CONFIG_BOOTM_PLAN9
-#undef CONFIG_BOOTM_RTEMS
-
/* Support both device trees and ATAGs. */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
diff --git a/include/configs/bur_cfg_common.h b/include/configs/bur_cfg_common.h
index 0f29384..dff4123 100644
--- a/include/configs/bur_cfg_common.h
+++ b/include/configs/bur_cfg_common.h
@@ -23,8 +23,6 @@
"setcurs 1 10;lcdputs serverip; setcurs 10 10; lcdputs ${serverip};" \
"setenv stdout nc;setenv stdin nc;setenv stderr nc\0"
-#define CONFIG_PREBOOT "run cfgscr; run brdefaultip"
-
/* Network defines */
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h
index 15ac179..89deeac 100644
--- a/include/configs/caddy2.h
+++ b/include/configs/caddy2.h
@@ -225,7 +225,6 @@
*/
#define CONFIG_SYS_RTC_BUS_NUM 0x01
#define CONFIG_SYS_I2C_RTC_ADDR 0x32
-#define CONFIG_RTC_RX8025
/* Pass Ethernet MAC to VxWorks */
#define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0
diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h
index 07c6409..f109b22 100644
--- a/include/configs/cgtqmx6eval.h
+++ b/include/configs/cgtqmx6eval.h
@@ -17,7 +17,6 @@
#define CONFIG_MACH_TYPE 4122
#ifdef CONFIG_SPL
-#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
#include "imx6_spl.h"
#endif
diff --git a/include/configs/chiliboard.h b/include/configs/chiliboard.h
index db990fc..13c15bd 100644
--- a/include/configs/chiliboard.h
+++ b/include/configs/chiliboard.h
@@ -161,15 +161,11 @@
#endif
#if defined(CONFIG_ENV_IS_IN_NAND)
-#define CONFIG_ENV_OFFSET 0x001c0000
#define CONFIG_ENV_OFFSET_REDUND 0x001e0000
-#define CONFIG_ENV_SIZE SZ_128K
#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#else
#define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_ENV_OFFSET SZ_128K
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE SZ_8K
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#endif
diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h
index 4c93fc6..67c52d7 100644
--- a/include/configs/cl-som-imx7.h
+++ b/include/configs/cl-som-imx7.h
@@ -38,10 +38,6 @@
#define CONFIG_POWER_PFUZE3000
#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
-#undef CONFIG_BOOTM_NETBSD
-#undef CONFIG_BOOTM_PLAN9
-#undef CONFIG_BOOTM_RTEMS
-
/* I2C configs */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
@@ -147,7 +143,6 @@
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
/* MMC Config*/
-#define CONFIG_FSL_USDHC
#ifdef CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
@@ -166,8 +161,5 @@
/* SPL */
#include "imx7_spl.h"
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
-#endif /* CONFIG_SPL_BUILD */
#endif /* __CONFIG_H */
diff --git a/include/configs/clearfog.h b/include/configs/clearfog.h
index 4198ff0..9d20a5e 100644
--- a/include/configs/clearfog.h
+++ b/include/configs/clearfog.h
@@ -83,9 +83,8 @@
#if defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI)
/* SPL related SPI defines */
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
-#elif defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC)
+#elif defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC) || defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SATA)
/* SPL related MMC defines */
#define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10)
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index 2e8dda8..b957e9c 100644
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h
@@ -144,8 +144,6 @@
"echo WARNING: Could not determine dtb to use; fi; \0" \
BOOTENV
-#define CONFIG_PREBOOT "usb start;sf probe"
-
#define BOOT_TARGET_DEVICES(func) \
func(USB, usb, 0) \
func(MMC, mmc, 2) \
@@ -209,7 +207,6 @@
/* SPL */
#include "imx6_spl.h"
-#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
/* Display */
#define CONFIG_IMX_HDMI
diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h
index 740bbd4..54f2cea 100644
--- a/include/configs/cm_t335.h
+++ b/include/configs/cm_t335.h
@@ -23,8 +23,6 @@
#define V_OSCK 25000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
-#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
-
#ifndef CONFIG_SPL_BUILD
#define MMCARGS \
"mmcdev=0\0" \
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index fd693cf..f9a6444 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -39,7 +39,6 @@
/*
* Size of malloc() pool
*/
-#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
/* Sector */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
@@ -179,7 +178,6 @@
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-#define CONFIG_ENV_OFFSET 0x260000
#define CONFIG_ENV_ADDR 0x260000
/* additions for new relocation code, must be added to all boards */
diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h
index bd40989..1314cf9 100644
--- a/include/configs/cm_t43.h
+++ b/include/configs/cm_t43.h
@@ -9,7 +9,6 @@
#define __CONFIG_CM_T43_H
#define CONFIG_CM_T43
-#define CONFIG_ARCH_CPU_INIT
#define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2GB */
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
@@ -75,14 +74,9 @@
#include <configs/ti_armv7_omap.h>
#undef CONFIG_SYS_MONITOR_LEN
-#define CONFIG_ENV_SIZE (16 * 1024)
-
#define V_OSCK 24000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
-#define CONFIG_ENV_SECT_SIZE (64 * 1024)
-#define CONFIG_ENV_OFFSET (768 * 1024)
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x80200000\0" \
"fdtaddr=0x81200000\0" \
@@ -120,7 +114,6 @@
/* SPL defines. */
#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + (128 << 20))
-#define CONFIG_SYS_SPI_U_BOOT_OFFS (256 * 1024)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
/* EEPROM */
diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h
index 21d9a3d..0a4f30f 100644
--- a/include/configs/colibri-imx6ull.h
+++ b/include/configs/colibri-imx6ull.h
@@ -28,9 +28,6 @@
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 1
-#undef CONFIG_BOOTM_PLAN9
-#undef CONFIG_BOOTM_RTEMS
-
/* I2C configs */
#define CONFIG_SYS_I2C_SPEED 100000
@@ -123,7 +120,7 @@
"${board}/flash_blk.img && source ${loadaddr}\0" \
"splashpos=m,m\0" \
"videomode=video=ctfb:x:640,y:480,depth:18,pclk:39722,le:48,ri:16,up:33,lo:10,hs:96,vs:2,sync:0,vmode:0\0" \
- "vidargs=video=mxsfb:640x480-16@60"
+ "vidargs=video=mxsfb:640x480M-16@60"
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x08000000)
@@ -153,7 +150,6 @@
/* used to initialize CONFIG_SYS_NAND_BASE_LIST which is unused */
#define CONFIG_SYS_NAND_BASE -1
#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
/* USB Configs */
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
@@ -170,7 +166,7 @@
#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M
#define DFU_DEFAULT_POLL_TIMEOUT 300
-#ifdef CONFIG_VIDEO
+#if defined(CONFIG_VIDEO) || defined(CONFIG_DM_VIDEO)
#define CONFIG_VIDEO_MXS
#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR
#define CONFIG_VIDEO_LOGO
diff --git a/include/configs/colibri-imx8x.h b/include/configs/colibri-imx8x.h
index e15bab2..69a876f 100644
--- a/include/configs/colibri-imx8x.h
+++ b/include/configs/colibri-imx8x.h
@@ -13,10 +13,6 @@
#define CONFIG_DISPLAY_BOARDINFO_LATE
-#undef CONFIG_BOOTM_NETBSD
-
-#define CONFIG_FSL_ESDHC
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5b010000
#define USDHC2_BASE_ADDR 0x5b020000
diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h
index 86f3f0d..fa4dc49 100644
--- a/include/configs/colibri_imx6.h
+++ b/include/configs/colibri_imx6.h
@@ -40,7 +40,6 @@
#define CONFIG_SYS_MXC_I2C3_SPEED 400000
/* MMC Configs */
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 2
@@ -165,25 +164,6 @@
"sdfinduuid=part uuid mmc ${sddev}:${sdrootpart} uuid\0" \
"sdrootpart=2\0"
-#define USB_BOOTCMD \
- "set_usbargs=setenv usbargs ip=off root=PARTUUID=${uuid} rw,noatime " \
- "rootfstype=ext4 rootwait\0" \
- "usbboot=run setup; usb start; run usbfinduuid; run set_usbargs; " \
- "setenv bootargs ${defargs} ${setupargs} " \
- "${usbargs} ${vidargs}; echo Booting from USB stick...; " \
- "run usbdtbload; " \
- "load usb ${usbdev}:${usbbootpart} ${kernel_addr_r} " \
- "${boot_file} && run fdt_fixup && " \
- "bootz ${kernel_addr_r} ${dtbparam}\0" \
- "usbbootpart=1\0" \
- "usbdev=0\0" \
- "usbdtbload=setenv dtbparam; load usb ${usbdev}:${usbbootpart} " \
- "${fdt_addr_r} " \
- "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && " \
- "true\0" \
- "usbfinduuid=part uuid usb ${usbdev}:${usbrootpart} uuid\0" \
- "usbrootpart=2\0"
-
#define FDT_FILE "imx6dl-colibri-eval-v3.dtb"
#define CONFIG_EXTRA_ENV_SETTINGS \
BOOTENV \
@@ -201,7 +181,6 @@
MEM_LAYOUT_ENV_SETTINGS \
NFS_BOOTCMD \
SD_BOOTCMD \
- USB_BOOTCMD \
"setethupdate=if env exists ethaddr; then; else setenv ethaddr " \
"00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \
"flash_eth.img && source ${loadaddr}\0" \
@@ -216,6 +195,7 @@
"load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \
"source ${loadaddr}\0" \
"splashpos=m,m\0" \
+ "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \
"vidargs=video=mxcfb0:dev=lcd,640x480M@60,if=RGB666 " \
"video=mxcfb1:off fbmem=8M\0 "
diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h
index 40173b1..4677e09 100644
--- a/include/configs/colibri_imx7.h
+++ b/include/configs/colibri_imx7.h
@@ -35,9 +35,6 @@
#define CONFIG_SYS_FSL_USDHC_NUM 2
#endif
-#undef CONFIG_BOOTM_PLAN9
-#undef CONFIG_BOOTM_RTEMS
-
/* I2C configs */
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_SPEED 100000
@@ -46,6 +43,46 @@
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_SERVERIP 192.168.10.1
+#ifndef PARTS_DEFAULT
+/* Define the default GPT table for eMMC */
+#define PARTS_DEFAULT \
+ /* Android partitions */ \
+ "partitions_android=" \
+ "uuid_disk=${uuid_gpt_disk};" \
+ "name=boot,start=1M,size=32M,uuid=${uuid_gpt_boot};" \
+ "name=environment,size=4M,uuid=${uuid_gpt_environment};" \
+ "name=recovery,size=16M,uuid=${uuid_gpt_recovery};" \
+ "name=system,size=1536M,uuid=${uuid_gpt_system};" \
+ "name=cache,size=512M,uuid=${uuid_gpt_cache};" \
+ "name=device,size=8M,uuid=${uuid_gpt_device};" \
+ "name=misc,size=4M,uuid=${uuid_gpt_misc};" \
+ "name=datafooter,size=2M,uuid=${uuid_gpt_datafooter};" \
+ "name=metadata,size=2M,uuid=${uuid_gpt_metadata};" \
+ "name=persistdata,size=2M,uuid=${uuid_gpt_persistdata};" \
+ "name=userdata,size=128M,uuid=${uuid_gpt_userdata};" \
+ "name=fbmisc,size=-,uuid=${uuid_gpt_fbmisc}\0"
+#endif /* PARTS_DEFAULT */
+
+#define EMMC_ANDROID_BOOTCMD \
+ "android_args=androidboot.storage_type=emmc\0" \
+ PARTS_DEFAULT \
+ "android_fdt_addr=0x83700000\0" \
+ "android_mmc_dev=0\0" \
+ "m4binary=rpmsg_imu_freertos.elf\0" \
+ "androidboot=ext4load mmc 0:a ${loadaddr} media/0/${m4binary}; "\
+ "bootaux ${loadaddr}; " \
+ "setenv loadaddr 0x88000000; " \
+ "setenv bootm_boot_mode sec;" \
+ "setenv bootargs androidboot.serialno=${serial#} " \
+ "$android_args; " \
+ "part start mmc ${android_mmc_dev} boot boot_start; " \
+ "part size mmc ${android_mmc_dev} boot boot_size; " \
+ "mmc read ${loadaddr} ${boot_start} ${boot_size}; " \
+ "part start mmc ${android_mmc_dev} environment env_start; " \
+ "part size mmc ${android_mmc_dev} environment env_size; " \
+ "mmc read ${android_fdt_addr} ${env_start} ${env_size}; " \
+ "bootm ${loadaddr} ${loadaddr} ${android_fdt_addr}\0 "
+
#define EMMC_BOOTCMD \
"set_emmcargs=setenv emmcargs ip=off root=PARTUUID=${uuid} ro " \
"rootfstype=ext4 rootwait\0" \
@@ -63,7 +100,6 @@
"emmcfinduuid=part uuid mmc ${emmcdev}:${emmcrootpart} uuid\0" \
"emmcrootpart=2\0"
-
#define MEM_LAYOUT_ENV_SETTINGS \
"bootm_size=0x10000000\0" \
"fdt_addr_r=0x82000000\0" \
@@ -125,7 +161,8 @@
"setenv fdtfile ${soc}-colibri-emmc-${fdt_board}.dtb && run distro_bootcmd;"
#define MODULE_EXTRA_ENV_SETTINGS \
"variant=-emmc\0" \
- EMMC_BOOTCMD
+ EMMC_BOOTCMD \
+ EMMC_ANDROID_BOOTCMD
#endif
#if defined(CONFIG_TARGET_COLIBRI_IMX7_NAND)
diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h
index d4802f9..bc3d40e 100644
--- a/include/configs/colibri_pxa270.h
+++ b/include/configs/colibri_pxa270.h
@@ -21,7 +21,6 @@
*/
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
-#define CONFIG_ARCH_CPU_INIT
#define CONFIG_BOOTCOMMAND \
"if fatload mmc 0 0xa0000000 uImage; then " \
"bootm 0xa0000000; " \
diff --git a/include/configs/condor.h b/include/configs/condor.h
new file mode 100644
index 0000000..e3c146e
--- /dev/null
+++ b/include/configs/condor.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * include/configs/condor.h
+ * This file is Condor board configuration.
+ *
+ * Copyright (C) 2019 Renesas Electronics Corporation
+ */
+
+#ifndef __CONDOR_H
+#define __CONDOR_H
+
+#include "rcar-gen3-common.h"
+
+/* Ethernet RAVB */
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* Environment compatibility */
+#undef CONFIG_ENV_SIZE_REDUND
+#undef CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_SECT_SIZE (256 * 1024)
+#define CONFIG_ENV_OFFSET 0x700000
+
+/* SH Ether */
+#define CONFIG_SH_ETHER_USE_PORT 0
+#define CONFIG_SH_ETHER_PHY_ADDR 0x1
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SH_ETHER_CACHE_WRITEBACK
+#define CONFIG_SH_ETHER_CACHE_INVALIDATE
+#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* Board Clock */
+/* XTAL_CLK : 33.33MHz */
+#define CONFIG_SYS_CLK_FREQ 33333333u
+
+/* Generic Timer Definitions (use in assembler source) */
+#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
+
+#endif /* __CONDOR_H */
diff --git a/include/configs/conga-qeval20-qa3-e3845.h b/include/configs/conga-qeval20-qa3-e3845.h
index 94aa273..93dcad4 100644
--- a/include/configs/conga-qeval20-qa3-e3845.h
+++ b/include/configs/conga-qeval20-qa3-e3845.h
@@ -37,6 +37,4 @@
"upd_uboot=tftp 100000 conga/u-boot.rom;" \
"sf probe;sf update 100000 0 800000;saveenv\0"
-#define CONFIG_PREBOOT
-
#endif /* __CONFIG_H */
diff --git a/include/configs/controlcenterdc.h b/include/configs/controlcenterdc.h
index 3affdb0..f6d5328 100644
--- a/include/configs/controlcenterdc.h
+++ b/include/configs/controlcenterdc.h
@@ -97,7 +97,6 @@
#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
/* SPL related SPI defines */
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x30000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
#endif
@@ -124,8 +123,6 @@
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_BOOTFILE "ccdc.img"
-#define CONFIG_PREBOOT /* enable preboot variable */
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth1\0" \
"consoledev=ttyS1\0" \
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index e5c3a0c..60e09c1 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -54,7 +54,6 @@
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_ENV_OVERWRITE
@@ -362,68 +361,25 @@
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
-#else
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
-#endif
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
-#endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
-#else
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
-#endif
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
-#else
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
-#endif
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
-#else
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
-#endif
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
/* controller 4, Base address 203000 */
-#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
-#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
-#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
/* Qman/Bman */
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
@@ -499,7 +455,26 @@
#endif
#ifdef CONFIG_PCI
+#if !defined(CONFIG_DM_PCI)
+#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
+#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
+#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
+#endif
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif /* CONFIG_PCI */
diff --git a/include/configs/corvus.h b/include/configs/corvus.h
index f1b0374..f2df66e 100644
--- a/include/configs/corvus.h
+++ b/include/configs/corvus.h
@@ -88,9 +88,7 @@
#define CONFIG_SYS_LOAD_ADDR ATMEL_BASE_CS6
/* bootstrap + u-boot + env in nandflash */
-#define CONFIG_ENV_OFFSET 0x100000
#define CONFIG_ENV_OFFSET_REDUND 0x180000
-#define CONFIG_ENV_SIZE SZ_128K
#define CONFIG_BOOTCOMMAND \
"nand read 0x70000000 0x200000 0x300000;" \
diff --git a/include/configs/crs305-1g-4s.h b/include/configs/crs305-1g-4s.h
index c73cb99..a2df69a 100644
--- a/include/configs/crs305-1g-4s.h
+++ b/include/configs/crs305-1g-4s.h
@@ -10,6 +10,7 @@
* High Level Configuration Options (easy to change)
*/
+#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024) /* 64 MB */
#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index ccdac0a..41f0813 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -19,14 +19,6 @@
#endif
/*
-* Disable DM_* for SPL build and can be re-enabled after adding
-* DM support in SPL
-*/
-#ifdef CONFIG_SPL_BUILD
-#undef CONFIG_DM_I2C
-#undef CONFIG_DM_I2C_COMPAT
-#endif
-/*
* SoC Configuration
*/
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
@@ -34,10 +26,9 @@
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
-#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
#ifdef CONFIG_DIRECT_NOR_BOOT
-#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
#endif
@@ -114,20 +105,11 @@
/*
* Serial Driver info
*/
-
-#if !CONFIG_IS_ENABLED(DM_SERIAL)
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
-#endif
#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
-#endif
#ifdef CONFIG_USE_SPIFLASH
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
#endif
@@ -147,7 +129,6 @@
#define CONFIG_ENV_SIZE (128 << 10)
#define CONFIG_ENV_SECT_SIZE (128 << 10)
#endif
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
#define CONFIG_SYS_NAND_PAGE_2K
#define CONFIG_SYS_NAND_CS 3
@@ -182,6 +163,10 @@
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_NAND_LOAD
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_NAND_SELF_INIT
+#endif
#endif
/*
@@ -196,7 +181,7 @@
#ifdef CONFIG_USE_NOR
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
#define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */
-#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3)
+#define CONFIG_ENV_OFFSET (SZ_1M)
#define CONFIG_ENV_SIZE (10 << 10) /* 10KB */
#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
#define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */
@@ -223,7 +208,6 @@
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
-#define CONFIG_MX_CYCLIC
/*
* Linux Information
@@ -268,12 +252,8 @@
#endif
/* USB Configs */
-#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_USB_OHCI_NEW
-#define CONFIG_USB_STORAGE
-#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x01E25000
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "da850evm"
#ifndef CONFIG_DIRECT_NOR_BOOT
/* defines for SPL */
diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h
index fb1b899..4f99805 100644
--- a/include/configs/dart_6ul.h
+++ b/include/configs/dart_6ul.h
@@ -55,7 +55,6 @@
#define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configs */
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
#define CONFIG_SUPPORT_EMMC_BOOT
diff --git a/include/configs/db-88f6281-bp.h b/include/configs/db-88f6281-bp.h
index 97af9a6..1b5541e 100644
--- a/include/configs/db-88f6281-bp.h
+++ b/include/configs/db-88f6281-bp.h
@@ -72,7 +72,6 @@
/*
* Other required minimal configurations
*/
-#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */
#define CONFIG_SYS_MEMTEST_END 0x007fffff /* (_8M - 1) */
#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
diff --git a/include/configs/db-88f6720.h b/include/configs/db-88f6720.h
index a1780fa..79b9ccf 100644
--- a/include/configs/db-88f6720.h
+++ b/include/configs/db-88f6720.h
@@ -73,7 +73,6 @@
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
/* SPL related SPI defines */
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
#endif /* _CONFIG_DB_88F6720_H */
diff --git a/include/configs/db-88f6820-amc.h b/include/configs/db-88f6820-amc.h
index 5b59a92..61b91dd 100644
--- a/include/configs/db-88f6820-amc.h
+++ b/include/configs/db-88f6820-amc.h
@@ -32,7 +32,6 @@
#endif
/* NAND */
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_ONFI_DETECTION
/* Keep device tree and initrd in lower memory so the kernel can access them */
@@ -69,7 +68,6 @@
#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
/* SPL related SPI defines */
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
#endif
diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h
index c98679e..900c962 100644
--- a/include/configs/db-88f6820-gp.h
+++ b/include/configs/db-88f6820-gp.h
@@ -85,7 +85,6 @@
#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
/* SPL related SPI defines */
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
#endif
diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h
index 6ed58ce..907bd0d 100644
--- a/include/configs/db-mv784mp-gp.h
+++ b/include/configs/db-mv784mp-gp.h
@@ -46,7 +46,6 @@
#endif
/* NAND */
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_ONFI_DETECTION
/*
@@ -83,7 +82,6 @@
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
/* SPL related SPI defines */
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
diff --git a/include/configs/db-xc3-24g4xg.h b/include/configs/db-xc3-24g4xg.h
index 0f75ad7..86d11e4 100644
--- a/include/configs/db-xc3-24g4xg.h
+++ b/include/configs/db-xc3-24g4xg.h
@@ -22,7 +22,6 @@
#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
/* NAND */
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_ONFI_DETECTION
/* Keep device tree and initrd in lower memory so the kernel can access them */
diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h
index c93a5de..16031c1 100644
--- a/include/configs/devkit3250.h
+++ b/include/configs/devkit3250.h
@@ -98,7 +98,6 @@
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
#define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
/*
* USB
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
index 2eb658d..baf1a73b 100644
--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h
@@ -37,8 +37,6 @@
#define CONFIG_REVISION_TAG 1
/* Size of malloc() pool */
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
- /* Sector */
#undef CONFIG_SYS_MALLOC_LEN
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
@@ -144,10 +142,6 @@
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
0x01000000) /* 16MB */
-/* NAND and environment organization */
-
-#define CONFIG_ENV_OFFSET 0x260000
-
/* SRAM config */
#define CONFIG_SYS_SRAM_START 0x40200000
#define CONFIG_SYS_SRAM_SIZE 0x10000
diff --git a/include/configs/dfi-bt700.h b/include/configs/dfi-bt700.h
index f7bad8e..a8e1850 100644
--- a/include/configs/dfi-bt700.h
+++ b/include/configs/dfi-bt700.h
@@ -42,6 +42,4 @@
"upd_uboot=usb reset;tftp 100000 dfi/u-boot.rom;" \
"sf probe;sf update 100000 0 800000;saveenv\0"
-#define CONFIG_PREBOOT
-
#endif /* __CONFIG_H */
diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h
index 3b1d0a9..c516e6e 100644
--- a/include/configs/dh_imx6.h
+++ b/include/configs/dh_imx6.h
@@ -23,7 +23,6 @@
/* SPL */
#include "imx6_spl.h" /* common IMX6 SPL configuration */
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x11400
#define CONFIG_SPL_TARGET "u-boot-with-spl.imx"
/* Miscellaneous configurable options */
@@ -48,16 +47,7 @@
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_ARP_TIMEOUT 200UL
-/* I2C Configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_SPEED 100000
-
/* MMC Configs */
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 3
#define CONFIG_SYS_MMC_ENV_DEV 2 /* 1 = SDHC3, 2 = SDHC4 (eMMC) */
diff --git a/include/configs/display5.h b/include/configs/display5.h
index 8829cba..e503e4a 100644
--- a/include/configs/display5.h
+++ b/include/configs/display5.h
@@ -45,7 +45,6 @@
#define CONFIG_SYS_SPI_ARGS_SIZE 0x10000
#include "imx6_spl.h"
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
@@ -55,11 +54,8 @@
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024)
-/*#define CONFIG_MXC_UART*/
#define CONFIG_MXC_UART_BASE UART5_BASE
-/* SPI NOR Flash */
-
/* I2C Configs */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
@@ -80,7 +76,6 @@
#endif
/* MMC Configs */
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 2
@@ -358,8 +353,6 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-/* Commands */
-
/* Watchdog */
#define CONFIG_WATCHDOG_TIMEOUT_MSECS 15000
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index aec70ee..3487b8a 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -21,16 +21,14 @@
#ifndef CONFIG_QSPI_BOOT
/* MMC ENV related defines */
#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
-#define CONFIG_ENV_SIZE (128 << 10)
-#define CONFIG_ENV_OFFSET 0x260000
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#endif
#if (CONFIG_CONS_INDEX == 1)
-#define CONSOLEDEV "ttyO0"
+#define CONSOLEDEV "ttyS0"
#elif (CONFIG_CONS_INDEX == 3)
-#define CONSOLEDEV "ttyO2"
+#define CONSOLEDEV "ttyS2"
#endif
#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */
#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */
@@ -94,7 +92,6 @@
#endif
/* SPI SPL */
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
/* USB xHCI HOST */
#define CONFIG_USB_XHCI_OMAP
diff --git a/include/configs/ds414.h b/include/configs/ds414.h
index 7269c42..552c744 100644
--- a/include/configs/ds414.h
+++ b/include/configs/ds414.h
@@ -91,7 +91,6 @@
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
/* SPL related SPI defines */
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
/* DS414 bus width is 32bits */
#define CONFIG_DDR_32BIT
@@ -99,7 +98,5 @@
/* Default Environment */
#define CONFIG_BOOTCOMMAND "sf read ${loadaddr} 0xd0000 0x700000; bootm"
#define CONFIG_LOADADDR 0x80000
-#undef CONFIG_PREBOOT /* override preboot for USB and SPI flash init */
-#define CONFIG_PREBOOT "usb start; sf probe"
#endif /* _CONFIG_SYNOLOGY_DS414_H */
diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
index a608c0f..f071718 100644
--- a/include/configs/edminiv2.h
+++ b/include/configs/edminiv2.h
@@ -183,7 +183,6 @@
/*
* Other required minimal configurations
*/
-#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
#define CONFIG_SYS_LOAD_ADDR 0x00800000
#define CONFIG_SYS_MEMTEST_START 0x00400000
diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h
index bf70ea0..fe28154 100644
--- a/include/configs/el6x_common.h
+++ b/include/configs/el6x_common.h
@@ -20,7 +20,6 @@
#define CONFIG_MXC_UART
#ifdef CONFIG_SPL
-#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
#include "imx6_spl.h"
#endif
diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h
index b86b542..c9e7c8c 100644
--- a/include/configs/ethernut5.h
+++ b/include/configs/ethernut5.h
@@ -20,7 +20,6 @@
#define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5
/* CPU information */
-#define CONFIG_ARCH_CPU_INIT
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
@@ -52,8 +51,6 @@
/* bootstrap + u-boot + env + linux in dataflash on CS0 */
#define CONFIG_ENV_OFFSET 0x3DE000
-#define CONFIG_ENV_SIZE (132 << 10)
-#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
/* NAND flash */
#ifdef CONFIG_CMD_NAND
diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h
index 752acc5..5ae2b42 100644
--- a/include/configs/exynos-common.h
+++ b/include/configs/exynos-common.h
@@ -15,7 +15,6 @@
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <linux/sizes.h>
-#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SKIP_LOWLEVEL_INIT
/* Keep L2 Cache Disabled */
diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h
index 397bbf6..e0a4d76 100644
--- a/include/configs/exynos5-common.h
+++ b/include/configs/exynos5-common.h
@@ -128,9 +128,9 @@
#define EXYNOS_IRAM_SECONDARY_BASE 0x02020018
#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 2) \
func(MMC, mmc, 1) \
func(MMC, mmc, 0) \
- func(MMC, mmc, 2) \
func(PXE, pxe, na) \
func(DHCP, dhcp, na)
diff --git a/include/configs/exynos7420-common.h b/include/configs/exynos7420-common.h
index 2885cd7..157260c 100644
--- a/include/configs/exynos7420-common.h
+++ b/include/configs/exynos7420-common.h
@@ -16,8 +16,6 @@
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <linux/sizes.h>
-#define CONFIG_ARCH_CPU_INIT
-
/* Size of malloc() pool before and after relocation */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20))
diff --git a/include/configs/fennec_rk3288.h b/include/configs/fennec_rk3288.h
deleted file mode 100644
index ddd7012..0000000
--- a/include/configs/fennec_rk3288.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define ROCKCHIP_DEVICE_SETTINGS
-#include <configs/rk3288_common.h>
-
-#define CONFIG_SYS_MMC_ENV_DEV 0
-
-#endif
diff --git a/include/configs/gardena-smart-gateway-at91sam.h b/include/configs/gardena-smart-gateway-at91sam.h
index 02bf4d1..482e471 100644
--- a/include/configs/gardena-smart-gateway-at91sam.h
+++ b/include/configs/gardena-smart-gateway-at91sam.h
@@ -43,12 +43,6 @@
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
-/* environment organization */
-#define CONFIG_ENV_UBI_PART "ubi"
-#define CONFIG_ENV_UBI_VOLUME "env"
-#define CONFIG_ENV_UBI_VOLUME_REDUND "env_r"
-#define CONFIG_ENV_SIZE (64 << 10)
-
/* SPL */
#define CONFIG_SPL_MAX_SIZE 0x7000
#define CONFIG_SPL_STACK 0x308000
diff --git a/include/configs/gazerbeam.h b/include/configs/gazerbeam.h
index 11d367a..0ff4828 100644
--- a/include/configs/gazerbeam.h
+++ b/include/configs/gazerbeam.h
@@ -100,8 +100,6 @@
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_PREBOOT /* enable preboot variable */
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS1\0" \
diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
index 0481ed0..31214a6 100644
--- a/include/configs/ge_bx50v3.h
+++ b/include/configs/ge_bx50v3.h
@@ -198,7 +198,6 @@
#define CONFIG_IMX_VIDEO_SKIP
#define CONFIG_CMD_BMP
-#define CONFIG_PWM_IMX
#define CONFIG_IMX6_PWM_PER_CLK 66000000
#define CONFIG_PCI
diff --git a/include/configs/gose.h b/include/configs/gose.h
index 0de0a36..fcb9f17 100644
--- a/include/configs/gose.h
+++ b/include/configs/gose.h
@@ -40,7 +40,6 @@
/* SPL support */
#define CONFIG_SPL_STACK 0xe6340000
#define CONFIG_SPL_MAX_SIZE 0x4000
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
#ifdef CONFIG_SPL_BUILD
#define CONFIG_CONS_SCIF0
#define CONFIG_SH_SCIF_CLK_FREQ 65000000
diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h
index b7271ab..26ca694 100644
--- a/include/configs/grpeach.h
+++ b/include/configs/grpeach.h
@@ -18,7 +18,6 @@
#define CONFIG_SYS_PBSIZE 256
#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
#define CONFIG_CMDLINE_TAG
-#define CONFIG_ARCH_CPU_INIT
/* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */
#define CONFIG_SYS_SDRAM_BASE 0x20000000
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index 02ceb4c..a27627e 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -138,7 +138,6 @@
/* Miscellaneous configurable options */
#define CONFIG_HWCONFIG
-#define CONFIG_PREBOOT
/* Memory configuration */
#define CONFIG_SYS_MEMTEST_START 0x10000000
diff --git a/include/configs/helios4.h b/include/configs/helios4.h
index e03d840..4df3200 100644
--- a/include/configs/helios4.h
+++ b/include/configs/helios4.h
@@ -104,7 +104,6 @@
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x30000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
#endif
diff --git a/include/configs/hikey960.h b/include/configs/hikey960.h
new file mode 100644
index 0000000..f6f9c8d
--- /dev/null
+++ b/include/configs/hikey960.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Linaro
+ * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ */
+
+#ifndef __HIKEY_H
+#define __HIKEY_H
+
+#include <linux/sizes.h>
+
+#define CONFIG_SYS_BOOTM_LEN SZ_64M
+
+/* Physical Memory Map */
+
+/* CONFIG_SYS_TEXT_BASE needs to align with where ATF loads bl33.bin */
+
+#define PHYS_SDRAM_1 0x00000000
+#define PHYS_SDRAM_1_SIZE 0xC0000000
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
+
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000)
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY 19000000
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE 0xe82b1000
+#define GICC_BASE 0xe82b2000
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M)
+
+#define CONFIG_ENV_SIZE 0x1000
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0)
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "image=Image\0" \
+ "fdtfile=hi3660-hikey960.dtb\0" \
+ "fdt_addr_r=0x10000000\0" \
+ "kernel_addr_r=0x11000000\0" \
+ "scriptaddr=0x00020000\0" \
+ "fdt_high=0xffffffffffffffff\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ BOOTENV
+
+#define CONFIG_ENV_SIZE 0x1000
+
+/* TODO: Remove this once the SD clock is fixed */
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT 1024
+
+#endif /* __HIKEY_H */
diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h
index 6e6c171..8fb3211 100644
--- a/include/configs/hrcon.h
+++ b/include/configs/hrcon.h
@@ -403,8 +403,6 @@
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_PREBOOT /* enable preboot variable */
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS1\0" \
diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h
index b1d01c5..43cb14c 100644
--- a/include/configs/ids8313.h
+++ b/include/configs/ids8313.h
@@ -253,9 +253,6 @@
#define CONFIG_SYS_LOAD_ADDR 0x100000
#define CONFIG_LOADS_ECHO
#define CONFIG_TIMESTAMP
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run nfsboot\\\" " \
- "to mount root filesystem over NFS;echo"
#define CONFIG_BOOTCOMMAND "run boot_cramfs"
#undef CONFIG_SYS_LOADS_BAUD_CHANGE
diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h
index 56b3c75..0826195 100644
--- a/include/configs/imx6-engicam.h
+++ b/include/configs/imx6-engicam.h
@@ -37,6 +37,7 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"splashpos=m,m\0" \
+ "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \
"image=uImage\0" \
"fit_image=fit.itb\0" \
"fdt_high=0xffffffff\0" \
diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h
index dbf5665..d6b7477 100644
--- a/include/configs/imx6_logic.h
+++ b/include/configs/imx6_logic.h
@@ -144,7 +144,6 @@
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00500000
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
/* MTD device */
diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h
index e4fa2df..1ceec5a 100644
--- a/include/configs/imx8mq_evk.h
+++ b/include/configs/imx8mq_evk.h
@@ -69,7 +69,6 @@
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_CRC32
-#undef CONFIG_BOOTM_NETBSD
/* ENET Config */
/* ENET1 */
@@ -216,8 +215,6 @@
#define CONFIG_IMX_BOOTAUX
#define CONFIG_CMD_MMC
-#define CONFIG_FSL_ESDHC
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h
index d06ed61..7a790ef 100644
--- a/include/configs/imx8qm_mek.h
+++ b/include/configs/imx8qm_mek.h
@@ -45,10 +45,7 @@
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_CRC32
-#undef CONFIG_BOOTM_NETBSD
-#define CONFIG_FSL_ESDHC
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5B010000
#define USDHC2_BASE_ADDR 0x5B020000
diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h
index a8591c9..c357c7b 100644
--- a/include/configs/imx8qxp_mek.h
+++ b/include/configs/imx8qxp_mek.h
@@ -44,10 +44,7 @@
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_CRC32
-#undef CONFIG_BOOTM_NETBSD
-#define CONFIG_FSL_ESDHC
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5B010000
#define USDHC2_BASE_ADDR 0x5B020000
diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h
new file mode 100644
index 0000000..5fe77ef
--- /dev/null
+++ b/include/configs/j721e_evm.h
@@ -0,0 +1,99 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration header file for K3 J721E EVM
+ *
+ * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Lokesh Vutla <lokeshvutla@ti.com>
+ */
+
+#ifndef __CONFIG_J721E_EVM_H
+#define __CONFIG_J721E_EVM_H
+
+#include <linux/sizes.h>
+#include <config_distro_bootcmd.h>
+#include <environment/ti/mmc.h>
+
+#define CONFIG_ENV_SIZE (128 << 10)
+
+/* DDR Configuration */
+#define CONFIG_SYS_SDRAM_BASE1 0x880000000
+
+/* SPL Loader Configuration */
+#ifdef CONFIG_TARGET_J721E_A72_EVM
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \
+ CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE)
+#else
+/*
+ * Maximum size in memory allocated to the SPL BSS. Keep it as tight as
+ * possible (to allow the build to go through), as this directly affects
+ * our memory footprint. The less we use for BSS the more we have available
+ * for everything else.
+ */
+#define CONFIG_SPL_BSS_MAX_SIZE 0xA000
+/*
+ * Link BSS to be within SPL in a dedicated region located near the top of
+ * the MCU SRAM, this way making it available also before relocation. Note
+ * that we are not using the actual top of the MCU SRAM as there is a memory
+ * location filled in by the boot ROM that we want to read out without any
+ * interference from the C context.
+ */
+#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX -\
+ CONFIG_SPL_BSS_MAX_SIZE)
+/* Set the stack right below the SPL BSS section */
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_BSS_START_ADDR
+/* Configure R5 SPL post-relocation malloc pool in DDR */
+#define CONFIG_SYS_SPL_MALLOC_START 0x84000000
+#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M
+#endif
+
+#ifdef CONFIG_SYS_K3_SPL_ATF
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin"
+#endif
+
+#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
+
+#define CONFIG_SYS_BOOTM_LEN SZ_64M
+#define CONFIG_CQSPI_REF_CLK 133333333
+
+/* U-Boot general configuration */
+#define EXTRA_ENV_J721E_BOARD_SETTINGS \
+ "default_device_tree=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
+ "findfdt=setenv fdtfile ${default_device_tree}\0" \
+ "loadaddr=0x80080000\0" \
+ "fdtaddr=0x82000000\0" \
+ "overlayaddr=0x83000000\0" \
+ "name_kern=Image\0" \
+ "console=ttyS2,115200n8\0" \
+ "args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000\0" \
+ "run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0"
+
+/* U-Boot MMC-specific configuration */
+#define EXTRA_ENV_J721E_BOARD_SETTINGS_MMC \
+ "boot=mmc\0" \
+ "mmcdev=1\0" \
+ "bootpart=1:2\0" \
+ "bootdir=/boot\0" \
+ "rd_spec=-\0" \
+ "init_mmc=run args_all args_mmc\0" \
+ "get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+ "get_overlay_mmc=" \
+ "fdt address ${fdtaddr};" \
+ "fdt resize 0x100000;" \
+ "for overlay in $name_overlays;" \
+ "do;" \
+ "load mmc ${bootpart} ${overlayaddr} ${bootdir}/${overlay} && " \
+ "fdt apply ${overlayaddr};" \
+ "done;\0" \
+ "get_kern_mmc=load mmc ${bootpart} ${loadaddr} " \
+ "${bootdir}/${name_kern}\0"
+
+/* Incorporate settings into the U-Boot environment */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ DEFAULT_MMC_TI_ARGS \
+ EXTRA_ENV_J721E_BOARD_SETTINGS \
+ EXTRA_ENV_J721E_BOARD_SETTINGS_MMC
+
+/* Now for the remaining common defines */
+#include <configs/ti_armv7_common.h>
+
+#endif /* __CONFIG_J721E_EVM_H */
diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h
index 3ec5a5a..b39e956 100644
--- a/include/configs/k2g_evm.h
+++ b/include/configs/k2g_evm.h
@@ -69,7 +69,7 @@
"run run_mon_hs; " \
"run init_${boot}; " \
"run get_fit_${boot}; " \
- "bootm ${fit_loadaddr}#${name_fdt}"
+ "bootm ${addr_fit}#${name_fdt}"
#endif
/* NAND Configuration */
diff --git a/include/configs/kc1.h b/include/configs/kc1.h
index 59814b5..e3a219c 100644
--- a/include/configs/kc1.h
+++ b/include/configs/kc1.h
@@ -103,8 +103,6 @@
* Environment
*/
-#define CONFIG_ENV_SIZE (128 * 1024)
-
#define CONFIG_ENV_OVERWRITE
#define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h
index a83782e..8433d8e 100644
--- a/include/configs/km/keymile-common.h
+++ b/include/configs/km/keymile-common.h
@@ -7,8 +7,6 @@
#ifndef __CONFIG_KEYMILE_H
#define __CONFIG_KEYMILE_H
-#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
-
/*
* Miscellaneous configurable options
*/
@@ -27,12 +25,6 @@
#define CONFIG_LOADS_ECHO
#define CONFIG_SYS_LOADS_BAUD_CHANGE
-
-/* Support the IVM EEprom */
-#define CONFIG_SYS_IVM_EEPROM_ADR 0x50
-#define CONFIG_SYS_IVM_EEPROM_MAX_LEN 0x400
-#define CONFIG_SYS_IVM_EEPROM_PAGE_LEN 0x100
-
/*
* BOOTP options
*/
diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h
index 455e523..c06143c 100644
--- a/include/configs/km/km-mpc83xx.h
+++ b/include/configs/km/km-mpc83xx.h
@@ -3,8 +3,6 @@
*/
#define BOOTFLASH_START 0xF0000000
-#define CONFIG_KM_CONSOLE_TTY "ttyS0"
-
/*
* DDR Setup
*/
@@ -89,8 +87,6 @@
{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
{1, {I2C_NULL_HOP} } }
-#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/
-
#if defined(CONFIG_CMD_NAND)
#define CONFIG_NAND_KMETER1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
diff --git a/include/configs/km/km-powerpc.h b/include/configs/km/km-powerpc.h
index 16b11d8..20b596f 100644
--- a/include/configs/km/km-powerpc.h
+++ b/include/configs/km/km-powerpc.h
@@ -11,9 +11,6 @@
#define CONFIG_JFFS2_CMDLINE
-/* standard km ethernet_present for piggy */
-#define CONFIG_KM_COMMON_ETH_INIT
-
/* EEprom support 24C08, 24C16, 24C64 */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* 8 Byte write page */
@@ -45,20 +42,10 @@
/* size of rootfs in RAM */
#define CONFIG_KM_ROOTFSSIZE 0x0
-/* pseudo-non volatile RAM [hex] */
-#define CONFIG_KM_PNVRAM 0x80000
-/* physical RAM MTD size [hex] */
-#define CONFIG_KM_PHRAM 0x100000
-/* resereved pram area at the end of memroy [hex] */
-#define CONFIG_KM_RESERVED_PRAM 0x0
/* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
* is not valid yet, which is the case for when u-boot copies itself to RAM */
#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10)
-#define CONFIG_KM_CRAMFS_ADDR 0xC00000
-#define CONFIG_KM_KERNEL_ADDR 0x400000 /* 7680Kbytes */
-#define CONFIG_KM_FDT_ADDR 0xB80000 /* 512Kbytes */
-
/* architecture specific default bootargs */
#define CONFIG_KM_DEF_BOOT_ARGS_CPU ""
diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h
index 8a00ac0..829a5c7 100644
--- a/include/configs/km/km_arm.h
+++ b/include/configs/km/km_arm.h
@@ -32,8 +32,6 @@
/* include common defines/options for all Keymile boards */
#include "keymile-common.h"
-/* SPI NOR Flash default params, used by sf commands */
-
/* Reserve 4 MB for malloc */
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
@@ -43,15 +41,6 @@
#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */
#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
-/* pseudo-non volatile RAM [hex] */
-#define CONFIG_KM_PNVRAM 0x80000
-/* physical RAM MTD size [hex] */
-#define CONFIG_KM_PHRAM 0x17F000
-
-#define CONFIG_KM_CRAMFS_ADDR 0x2400000
-#define CONFIG_KM_KERNEL_ADDR 0x2000000 /* 3098KBytes */
-#define CONFIG_KM_FDT_ADDR 0x23E0000 /* 128KBytes */
-
/* architecture specific default bootargs */
#define CONFIG_KM_DEF_BOOT_ARGS_CPU \
"bootcountaddr=${bootcountaddr} ${mtdparts}" \
@@ -72,26 +61,10 @@
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
/*
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
-#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE
-#define CONFIG_SYS_NS16550_COM2 KW_UART1_BASE
-
-/*
- * Serial Port configuration
- * The following definitions let you select what serial you want to use
- * for your console driver.
- */
-
-/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_BOOTMAPSZ (8 << 20) /* Initial Memmap for Linux */
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_INITRD_TAG /* enable INITRD tag */
#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */
@@ -101,30 +74,16 @@
*/
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define BOOTFLASH_START 0x0
-
-/* Kirkwood has two serial IF */
-#if (CONFIG_CONS_INDEX == 2)
-#define CONFIG_KM_CONSOLE_TTY "ttyS1"
-#else
-#define CONFIG_KM_CONSOLE_TTY "ttyS0"
-#endif
-
/*
* Other required minimal configurations
*/
-#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
-#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
/*
* Ethernet Driver configuration
*/
-#define CONFIG_NETCONSOLE /* include NetConsole support */
-#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
+#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer autoneg timeout */
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
#define CONFIG_PHY_BASE_ADR 0
-#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
-#define CONFIG_KM_COMMON_ETH_INIT /* standard km ethernet_present for piggy */
/*
* I2C related stuff
@@ -201,11 +160,6 @@
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-
-/* SPI bus claim MPP configuration */
-#define CONFIG_SYS_KW_SPI_MPP 0x0
-
-#define FLASH_GPIO_PIN 0x00010000
#define KM_FLASH_GPIO_PIN 16
#define CONFIG_KM_UPDATE_UBOOT \
@@ -243,19 +197,9 @@
"arch=arm\0" \
""
-#if !defined(CONFIG_MTD_NOR_FLASH)
-#undef CONFIG_JFFS2_CMDLINE
-#endif
-
/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_SDRAM_BASE 0x00000000
-/* Do early setups now in board_init_f() */
-/*
- * resereved pram area at the end of memroy [hex]
- * 8Mbytes for switch + 4Kbytes for bootcount
- */
-#define CONFIG_KM_RESERVED_PRAM 0x801000
/* address for the bootcount (taken from end of RAM) */
#define BOOTCOUNT_ADDR (CONFIG_KM_RESERVED_PRAM)
@@ -264,6 +208,4 @@
#define CONFIG_POST_SKIP_ENV_FLAGS
#define CONFIG_POST_EXTERNAL_WORD_FUNCS
-/* we do the whole PCIe FPGA config stuff here */
-
#endif /* _CONFIG_KM_ARM_H */
diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h
deleted file mode 100644
index 3eff380..0000000
--- a/include/configs/km/kmp204x-common.h
+++ /dev/null
@@ -1,409 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2013 Keymile AG
- * Valentin Longchamp <valentin.longchamp@keymile.com>
- */
-
-#ifndef _CONFIG_KMP204X_H
-#define _CONFIG_KMP204X_H
-
-#define CONFIG_KM_DEF_NETDEV "netdev=eth0\0"
-
-/* an additionnal option is required for UBI as subpage access is
- * supported in u-boot */
-#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048"
-
-#define CONFIG_NAND_ECC_BCH
-
-/* common KM defines */
-#include "keymile-common.h"
-
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_RAMBOOT_PBL
-#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg
-#define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg
-
-/* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
-#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
-
-#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE3 /* PCIE controller 3 */
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-
-#define CONFIG_SYS_DPAA_RMAN /* RMan */
-
-/* Environment in SPI Flash */
-#define CONFIG_ENV_OFFSET 0x100000 /* 1MB for u-boot */
-#define CONFIG_ENV_SIZE 0x004000 /* 16K env */
-#define CONFIG_ENV_SECT_SIZE 0x010000
-#define CONFIG_ENV_OFFSET_REDUND 0x110000
-#define CONFIG_ENV_TOTAL_SIZE 0x020000
-
-#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(unsigned long dummy);
-#endif
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BACKSIDE_L2_CACHE
-#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
-#define CONFIG_BTB /* toggle branch predition */
-
-#define CONFIG_ENABLE_36BIT_PHYS
-
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-
-#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS /* POST memory regions test */
-
-/*
- * Config the L3 Cache as L3 SRAM
- */
-#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
-#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
- CONFIG_RAMBOOT_TEXT_BASE)
-#define CONFIG_SYS_L3_SIZE (1024 << 10)
-#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
-
-#define CONFIG_SYS_DCSRBAR 0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
-
-/*
- * DDR Setup
- */
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-#define CONFIG_DDR_SPD
-
-#define CONFIG_SYS_SPD_BUS_NUM 0
-#define SPD_EEPROM_ADDRESS 0x54
-#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-
-/******************************************************************************
- * (PRAM usage)
- * ... -------------------------------------------------------
- * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
- * ... |<------------------- pram -------------------------->|
- * ... -------------------------------------------------------
- * @END_OF_RAM:
- * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
- * @CONFIG_KM_PHRAM: address for /var
- * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
- * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
- */
-
-/* size of rootfs in RAM */
-#define CONFIG_KM_ROOTFSSIZE 0x0
-/* pseudo-non volatile RAM [hex] */
-#define CONFIG_KM_PNVRAM 0x80000
-/* physical RAM MTD size [hex] */
-#define CONFIG_KM_PHRAM 0x100000
-/* reserved pram area at the end of memory [hex]
- * u-boot reserves some memory for the MP boot page */
-#define CONFIG_KM_RESERVED_PRAM 0x1000
-/* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
- * is not valid yet, which is the case for when u-boot copies itself to RAM */
-#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10)
-
-#define CONFIG_KM_CRAMFS_ADDR 0x2000000
-#define CONFIG_KM_KERNEL_ADDR 0x1000000 /* max kernel size 15.5Mbytes */
-#define CONFIG_KM_FDT_ADDR 0x1F80000 /* max dtb size 0.5Mbytes */
-
-/*
- * Local Bus Definitions
- */
-
-/* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */
-#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_2)
-
-/* Nand Flash */
-#define CONFIG_NAND_FSL_ELBC
-#define CONFIG_SYS_NAND_BASE 0xffa00000
-#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
-
-#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-
-/* NAND flash config */
-#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | BR_PS_8 /* Port Size = 8 bit */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-
-#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \
- | OR_FCM_BCTLD /* LBCTL not ass */ \
- | OR_FCM_SCY_1 /* 1 clk wait cycle */ \
- | OR_FCM_RST /* 1 clk read setup */ \
- | OR_FCM_PGS /* Large page size */ \
- | OR_FCM_CST) /* 0.25 command setup */
-
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-
-/* QRIO FPGA */
-#define CONFIG_SYS_QRIO_BASE 0xfb000000
-#define CONFIG_SYS_QRIO_BASE_PHYS 0xffb000000ull
-
-#define CONFIG_SYS_QRIO_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \
- | BR_PS_8 /* Port Size 8 bits */ \
- | BR_DECC_OFF /* no error corr */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-
-#define CONFIG_SYS_QRIO_OR_PRELIM (OR_AM_64KB /* length 64K */ \
- | OR_GPCM_BCTLD /* no LCTL assert */ \
- | OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \
- | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
- | OR_GPCM_TRLX /* relaxed tmgs */ \
- | OR_GPCM_EAD) /* extra bus clk cycles */
-
-#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */
-
-#define CONFIG_MISC_INIT_F
-
-#define CONFIG_HWCONFIG
-
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
-/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
-
-#define CONFIG_KM_CONSOLE_TTY "ttyS0"
-
-/* I2C */
-
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_SYS_I2C_SPEED 100000 /* deblocking */
-#define CONFIG_SYS_NUM_I2C_BUSES 3
-#define CONFIG_SYS_I2C_MAX_HOPS 1
-#define CONFIG_SYS_I2C_FSL /* Use FSL I2C driver */
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
-#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
- {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
- {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \
- }
-#ifndef __ASSEMBLY__
-void set_sda(int state);
-void set_scl(int state);
-int get_sda(void);
-int get_scl(void);
-#endif
-
-#define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/
-
-/*
- * eSPI - Enhanced SPI
- */
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-/* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 3, Slot 1, tgtid 1, Base address 202000 */
-#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8010000
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8010000ull
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
-
-/* Qman/Bman */
-#define CONFIG_SYS_BMAN_NUM_PORTALS 10
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS 10
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
-#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
-
-#define CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_DPAA_PME
-/* Default address of microcode for the Linux Fman driver
- * env is stored at 0x100000, sector size is 0x10000, x2 (redundant)
- * ucode is stored after env, so we got 0x120000.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0x120000
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
-
-#define CONFIG_PHYLIB_10G
-
-#define CONFIG_PCI_INDIRECT_BRIDGE
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-
-/* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */
-#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x11
-#define CONFIG_SYS_TBIPA_VALUE 8
-#define CONFIG_ETHPRIME "FM1@DTSEC5"
-
-/*
- * Environment
- */
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
- * Hardware Watchdog
- */
-#define CONFIG_WATCHDOG /* enable CPU watchdog */
-#define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) (~10min) */
-#define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */
-
-
-/*
- * additionnal command line configuration.
- */
-
-/* we don't need flash support */
-#undef CONFIG_JFFS2_CMDLINE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-#define __USB_PHY_TYPE utmi
-#define CONFIG_USB_EHCI_FSL
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ENV_OVERWRITE
-#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
-#define CONFIG_KM_DEF_ENV "km-common=empty\0"
-#endif
-
-/* architecture specific default bootargs */
-#define CONFIG_KM_DEF_BOOT_ARGS_CPU ""
-
-/* FIXME: FDT_ADDR is unspecified */
-#define CONFIG_KM_DEF_ENV_CPU \
- "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \
- "cramfsloadfdt=" \
- "cramfsload ${fdt_addr_r} " \
- "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
- "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \
- "u-boot="CONFIG_HOSTNAME "/u-boot.pbl\0" \
- "update=" \
- "sf probe 0;sf erase 0 +${filesize};" \
- "sf write ${load_addr_r} 0 ${filesize};\0" \
- "set_fdthigh=true\0" \
- "checkfdt=true\0" \
- ""
-
-#define CONFIG_HW_ENV_SETTINGS \
- "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \
- "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
- "usb_dr_mode=host\0"
-
-#define CONFIG_KM_NEW_ENV \
- "newenv=sf probe 0;" \
- "sf erase " __stringify(CONFIG_ENV_OFFSET) " " \
- __stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
-
-/* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */
-#ifndef CONFIG_KM_DEF_ARCH
-#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
-#endif
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_KM_DEF_ENV \
- CONFIG_KM_DEF_ARCH \
- CONFIG_KM_NEW_ENV \
- CONFIG_HW_ENV_SETTINGS \
- "EEprom_ivm=pca9547:70:9\0" \
- ""
-
-#endif /* _CONFIG_KMP204X_H */
diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h
index e7b12d0..6fce83c 100644
--- a/include/configs/km_kirkwood.h
+++ b/include/configs/km_kirkwood.h
@@ -24,13 +24,10 @@
#if defined(CONFIG_KM_KIRKWOOD)
#define CONFIG_HOSTNAME "km_kirkwood"
#define CONFIG_KM_DISABLE_PCIE
-#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
/* KM_KIRKWOOD_PCI */
#elif defined(CONFIG_KM_KIRKWOOD_PCI)
#define CONFIG_HOSTNAME "km_kirkwood_pci"
-#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
-#define CONFIG_KM_FPGA_CONFIG
#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048"
#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
@@ -40,11 +37,9 @@
#undef CONFIG_SYS_KWD_CONFIG
#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
#define CONFIG_KM_DISABLE_PCIE
-#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
/* KM_NUSA / KM_SUGP1 */
#elif defined(CONFIG_KM_NUSA) || defined(CONFIG_KM_SUGP1)
-#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
# if defined(CONFIG_KM_NUSA)
#define CONFIG_HOSTNAME "kmnusa"
@@ -55,48 +50,27 @@
#undef CONFIG_SYS_KWD_CONFIG
#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
-#define CONFIG_KM_ENV_IS_IN_SPI_NOR
-#define CONFIG_KM_FPGA_CONFIG
-#define CONFIG_KM_PIGGY4_88E6352
-#define CONFIG_MV88E6352_SWITCH
-#define CONFIG_KM_MVEXTSW_ADDR 0x10
/* KM_MGCOGE3UN */
#elif defined(CONFIG_KM_MGCOGE3UN)
#define CONFIG_HOSTNAME "mgcoge3un"
-#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
#undef CONFIG_SYS_KWD_CONFIG
#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-memphis.cfg
#define CONFIG_KM_BOARD_EXTRA_ENV "waitforne=true\0"
-#define CONFIG_PIGGY_MAC_ADRESS_OFFSET 3
#define CONFIG_KM_DISABLE_PCIE
-#define CONFIG_KM_PIGGY4_88E6061
/* KMCOGE5UN */
#elif defined(CONFIG_KM_COGE5UN)
-#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
#undef CONFIG_SYS_KWD_CONFIG
#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_256M8_1.cfg
-#define CONFIG_KM_ENV_IS_IN_SPI_NOR
-#define CONFIG_PIGGY_MAC_ADRESS_OFFSET 3
#define CONFIG_HOSTNAME "kmcoge5un"
#define CONFIG_KM_DISABLE_PCIE
-#define CONFIG_KM_PIGGY4_88E6352
-
-/* KM_PORTL2 */
-#elif defined(CONFIG_KM_PORTL2)
-#define CONFIG_HOSTNAME "portl2"
-#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
-#define CONFIG_KM_PIGGY4_88E6061
/* KM_SUV31 */
#elif defined(CONFIG_KM_SUV31)
-#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
#define CONFIG_HOSTNAME "kmsuv31"
#undef CONFIG_SYS_KWD_CONFIG
#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
-#define CONFIG_KM_ENV_IS_IN_SPI_NOR
-#define CONFIG_KM_FPGA_CONFIG
#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048"
#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
#else
@@ -166,7 +140,7 @@
MVGBE_SET_MII_SPEED_TO_100)
#endif
-#ifdef CONFIG_KM_DISABLE_PCI
+#ifdef CONFIG_KM_DISABLE_PCIE
#undef CONFIG_KIRKWOOD_PCIE_INIT
#endif
diff --git a/include/configs/kmp204x.h b/include/configs/kmp204x.h
index c50026d..75480a8 100644
--- a/include/configs/kmp204x.h
+++ b/include/configs/kmp204x.h
@@ -7,13 +7,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-/* KMLION1 */
-#if defined(CONFIG_KMLION1)
-#define CONFIG_HOSTNAME "kmlion1"
-#define CONFIG_KM_BOARD_NAME "kmlion1"
-
-/* KMCOGE4 */
-#elif defined(CONFIG_KMCOGE4)
+#if defined(CONFIG_KMCOGE4)
#define CONFIG_HOSTNAME "kmcoge4"
#define CONFIG_KM_BOARD_NAME "kmcoge4"
@@ -23,31 +17,407 @@
#define CONFIG_KMP204X
-#include "km/kmp204x-common.h"
+#define CONFIG_KM_DEF_NETDEV "netdev=eth0\0"
-#if defined(CONFIG_KMLION1)
-/* App1 Local bus */
-#define CONFIG_SYS_LBAPP1_BASE 0xD0000000
-#define CONFIG_SYS_LBAPP1_BASE_PHYS 0xFD0000000ull
+/* an additionnal option is required for UBI as subpage access is
+ * supported in u-boot
+ */
+#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048"
-#define CONFIG_SYS_LBAPP1_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBAPP1_BASE_PHYS) \
+#define CONFIG_NAND_ECC_BCH
+
+/* common KM defines */
+#include "km/keymile-common.h"
+
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_RAMBOOT_PBL
+#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg
+
+/* High Level Configuration Options */
+#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
+#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
+
+#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
+#define CONFIG_PCIE1 /* PCIE controller 1 */
+#define CONFIG_PCIE3 /* PCIE controller 3 */
+#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
+
+#define CONFIG_SYS_DPAA_RMAN /* RMan */
+
+/* Environment in SPI Flash */
+#define CONFIG_ENV_OFFSET 0x100000 /* 1MB for u-boot */
+#define CONFIG_ENV_SIZE 0x004000 /* 16K env */
+#define CONFIG_ENV_SECT_SIZE 0x010000
+#define CONFIG_ENV_OFFSET_REDUND 0x110000
+#define CONFIG_ENV_TOTAL_SIZE 0x020000
+
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(unsigned long dummy);
+#endif
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BACKSIDE_L2_CACHE
+#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
+#define CONFIG_BTB /* toggle branch predition */
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
+
+#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS /* POST memory regions test */
+
+/*
+ * Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
+#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
+ CONFIG_RAMBOOT_TEXT_BASE)
+#define CONFIG_SYS_L3_SIZE (1024 << 10)
+#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
+
+#define CONFIG_SYS_DCSRBAR 0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#define CONFIG_DDR_SPD
+
+#define CONFIG_SYS_SPD_BUS_NUM 0
+#define SPD_EEPROM_ADDRESS 0x54
+#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
+
+#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+
+/******************************************************************************
+ * (PRAM usage)
+ * ... -------------------------------------------------------
+ * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
+ * ... |<------------------- pram -------------------------->|
+ * ... -------------------------------------------------------
+ * @END_OF_RAM:
+ * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
+ * @CONFIG_KM_PHRAM: address for /var
+ * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
+ * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
+ */
+
+/* size of rootfs in RAM */
+#define CONFIG_KM_ROOTFSSIZE 0x0
+/* pseudo-non volatile RAM [hex] */
+#define CONFIG_KM_PNVRAM 0x80000
+/* physical RAM MTD size [hex] */
+#define CONFIG_KM_PHRAM 0x100000
+/* reserved pram area at the end of memory [hex]
+ * u-boot reserves some memory for the MP boot page
+ */
+#define CONFIG_KM_RESERVED_PRAM 0x1000
+/* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
+ * is not valid yet, which is the case for when u-boot copies itself to RAM
+ */
+#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM) >> 10)
+
+#define CONFIG_KM_CRAMFS_ADDR 0x2000000
+#define CONFIG_KM_KERNEL_ADDR 0x1000000 /* max kernel size 15.5Mbytes */
+#define CONFIG_KM_FDT_ADDR 0x1F80000 /* max dtb size 0.5Mbytes */
+
+/*
+ * Local Bus Definitions
+ */
+
+/* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */
+#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_2)
+
+/* Nand Flash */
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_NAND_BASE 0xffa00000
+#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
+
+#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+
+/* NAND flash config */
+#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+ | BR_PS_8 /* Port Size = 8 bit */ \
+ | BR_MS_FCM /* MSEL = FCM */ \
+ | BR_V) /* valid */
+
+#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \
+ | OR_FCM_BCTLD /* LBCTL not ass */ \
+ | OR_FCM_SCY_1 /* 1 clk wait cycle */ \
+ | OR_FCM_RST /* 1 clk read setup */ \
+ | OR_FCM_PGS /* Large page size */ \
+ | OR_FCM_CST) /* 0.25 command setup */
+
+#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+
+/* QRIO FPGA */
+#define CONFIG_SYS_QRIO_BASE 0xfb000000
+#define CONFIG_SYS_QRIO_BASE_PHYS 0xffb000000ull
+
+#define CONFIG_SYS_QRIO_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \
| BR_PS_8 /* Port Size 8 bits */ \
| BR_DECC_OFF /* no error corr */ \
| BR_MS_GPCM /* MSEL = GPCM */ \
| BR_V) /* valid */
-#define CONFIG_SYS_LBAPP1_OR_PRELIM (OR_AM_256MB /* length 256MB */ \
- | OR_GPCM_ACS_DIV2 /* LCS 1/2 clk after */ \
- | OR_GPCM_CSNT /* LCS 1/4 clk before */ \
+#define CONFIG_SYS_QRIO_OR_PRELIM (OR_AM_64KB /* length 64K */ \
+ | OR_GPCM_BCTLD /* no LCTL assert */ \
+ | OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \
| OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
| OR_GPCM_TRLX /* relaxed tmgs */ \
| OR_GPCM_EAD) /* extra bus clk cycles */
-/* Local bus app1 Base Address */
-#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_LBAPP1_BR_PRELIM
-/* Local bus app1 Options */
-#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_LBAPP1_OR_PRELIM
+
+#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */
+#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */
+
+#define CONFIG_MISC_INIT_F
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x11C600)
+#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x11D500)
+#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x11D600)
+
+#define CONFIG_KM_CONSOLE_TTY "ttyS0"
+
+/* I2C */
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_SYS_I2C_SPEED 100000 /* deblocking */
+#define CONFIG_SYS_NUM_I2C_BUSES 3
+#define CONFIG_SYS_I2C_MAX_HOPS 1
+#define CONFIG_SYS_I2C_FSL /* Use FSL I2C driver */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
+#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
+ {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
+ {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \
+ }
+#ifndef __ASSEMBLY__
+void set_sda(int state);
+void set_scl(int state);
+int get_sda(void);
+int get_scl(void);
#endif
+#define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/
+
+/*
+ * eSPI - Enhanced SPI
+ */
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
+#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8010000
+#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8010000ull
+#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
+
+/* Qman/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS 10
+#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
+#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
+#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
+#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
+#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
+ CONFIG_SYS_BMAN_CENA_SIZE)
+#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
+#define CONFIG_SYS_QMAN_NUM_PORTALS 10
+#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
+#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
+#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
+#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
+#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
+#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
+ CONFIG_SYS_QMAN_CENA_SIZE)
+#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+/* Default address of microcode for the Linux Fman driver
+ * env is stored at 0x100000, sector size is 0x10000, x2 (redundant)
+ * ucode is stored after env, so we got 0x120000.
+ */
+#define CONFIG_SYS_FMAN_FW_ADDR 0x120000
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
+#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+
+#define CONFIG_PHYLIB_10G
+
+#define CONFIG_PCI_INDIRECT_BRIDGE
+
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+
+/* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */
+#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x11
+#define CONFIG_SYS_TBIPA_VALUE 8
+#define CONFIG_ETHPRIME "FM1@DTSEC5"
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
+
+/*
+ * Hardware Watchdog
+ */
+#define CONFIG_WATCHDOG /* enable CPU watchdog */
+#define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) (~10min) */
+#define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */
+
+/*
+ * additionnal command line configuration.
+ */
+
+/* we don't need flash support */
+#undef CONFIG_JFFS2_CMDLINE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#endif
+
+#define __USB_PHY_TYPE utmi
+#define CONFIG_USB_EHCI_FSL
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
+#define CONFIG_KM_DEF_ENV "km-common=empty\0"
+#endif
+
+/* architecture specific default bootargs */
+#define CONFIG_KM_DEF_BOOT_ARGS_CPU ""
+
+/* FIXME: FDT_ADDR is unspecified */
+#define CONFIG_KM_DEF_ENV_CPU \
+ "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \
+ "cramfsloadfdt=" \
+ "cramfsload ${fdt_addr_r} " \
+ "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
+ "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \
+ "u-boot=" CONFIG_HOSTNAME "/u-boot.pbl\0" \
+ "update=" \
+ "sf probe 0;sf erase 0 +${filesize};" \
+ "sf write ${load_addr_r} 0 ${filesize};\0" \
+ "set_fdthigh=true\0" \
+ "checkfdt=true\0" \
+ ""
+
+#define CONFIG_HW_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \
+ "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
+ "usb_dr_mode=host\0"
+
+#define CONFIG_KM_NEW_ENV \
+ "newenv=sf probe 0;" \
+ "sf erase " __stringify(CONFIG_ENV_OFFSET) " " \
+ __stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
+
+/* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */
+#ifndef CONFIG_KM_DEF_ARCH
+#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_KM_DEF_ENV \
+ CONFIG_KM_DEF_ARCH \
+ CONFIG_KM_NEW_ENV \
+ CONFIG_HW_ENV_SETTINGS \
+ "EEprom_ivm=pca9547:70:9\0" \
+ ""
+
/* App2 Local bus */
#define CONFIG_SYS_LBAPP2_BASE 0xE0000000
#define CONFIG_SYS_LBAPP2_BASE_PHYS 0xFE0000000ull
diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h
deleted file mode 100644
index 6e5d507..0000000
--- a/include/configs/kmvect1.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
- * Dave Liu <daveliu@freescale.com>
- *
- * Copyright (C) 2007 Logic Product Development, Inc.
- * Peter Barada <peterb@logicpd.com>
- *
- * Copyright (C) 2007 MontaVista Software, Inc.
- * Anton Vorontsov <avorontsov@ru.mvista.com>
- *
- * (C) Copyright 2010
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-
-#define CONFIG_HOSTNAME "kmvect1"
-#define CONFIG_KM_BOARD_NAME "kmvect1"
-/* at end of uboot partition, before env */
-#define CONFIG_SYS_QE_FW_ADDR 0xF00B0000
-
-/* include common defines/options for all Keymile boards */
-#include "km/keymile-common.h"
-#include "km/km-powerpc.h"
-#include "km/km-mpc83xx.h"
-#include "km/km-mpc8309.h"
-
-#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
- 0x0000c000 | \
- MxMR_WLFx_2X)
-/*
- * QE UEC ethernet configuration
- */
-#define CONFIG_MV88E6352_SWITCH
-#define CONFIG_KM_MVEXTSW_ADDR 0x10
-
-/* ethernet port connected to simple switch 88e6122 (UEC0) */
-#define CONFIG_UEC_ETH1
-#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
-#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
-#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
-
-#define CONFIG_FIXED_PHY 0xFFFFFFFF
-#define CONFIG_SYS_FIXED_PHY_ADDR 0x1E /* unused address */
-#define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
- {devnum, speed, duplex}
-#define CONFIG_SYS_FIXED_PHY_PORTS \
- CONFIG_SYS_FIXED_PHY_PORT("UEC0", SPEED_100, DUPLEX_FULL)
-
-#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
-#define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
-#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
-#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h
index c42139d..140076a 100644
--- a/include/configs/koelsch.h
+++ b/include/configs/koelsch.h
@@ -40,7 +40,6 @@
/* SPL support */
#define CONFIG_SPL_STACK 0xe6340000
#define CONFIG_SPL_MAX_SIZE 0x4000
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
#ifdef CONFIG_SPL_BUILD
#define CONFIG_CONS_SCIF0
#define CONFIG_SH_SCIF_CLK_FREQ 65000000
diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h
index d2ebf92..2435ebb 100644
--- a/include/configs/kp_imx6q_tpc.h
+++ b/include/configs/kp_imx6q_tpc.h
@@ -39,8 +39,6 @@
#define CONFIG_SYS_I2C_SPEED 100000
/* MMC Configs */
-#define CONFIG_FSL_ESDHC
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_MMC_ENV_DEV 1 /* 0 = SDHC2, 1 = SDHC4 (eMMC) */
diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h
index 071d928..5a2b040 100644
--- a/include/configs/kzm9g.h
+++ b/include/configs/kzm9g.h
@@ -12,14 +12,10 @@
#include <asm/arch/rmobile.h>
-#define CONFIG_ARCH_CPU_INIT
-
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
-#undef CONFIG_SHOW_BOOT_PROGRESS
-
/* MEMORY */
#define KZM_SDRAM_BASE (0x40000000)
#define PHYS_SDRAM KZM_SDRAM_BASE
diff --git a/include/configs/lager.h b/include/configs/lager.h
index 5acd5a2..db1dbc0 100644
--- a/include/configs/lager.h
+++ b/include/configs/lager.h
@@ -41,7 +41,6 @@
/* SPL support */
#define CONFIG_SPL_STACK 0xe6340000
#define CONFIG_SPL_MAX_SIZE 0x4000
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
#ifdef CONFIG_SPL_BUILD
#define CONFIG_CONS_SCIF0
#define CONFIG_SH_SCIF_CLK_FREQ 65000000
diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h
index 36ca3b2..c1eeca0 100644
--- a/include/configs/legoev3.h
+++ b/include/configs/legoev3.h
@@ -42,11 +42,8 @@
* Serial Driver info
*/
#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
-#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART1_BASE /* Base address of UART1 */
#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
-#define CONFIG_SYS_SPI_BASE DAVINCI_SPI0_BASE
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID)
/*
@@ -63,7 +60,6 @@
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
-#define CONFIG_MX_CYCLIC
/*
* Linux Information
diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h
index 12e6437..77aa22b 100644
--- a/include/configs/ls1012afrwy.h
+++ b/include/configs/ls1012afrwy.h
@@ -41,7 +41,6 @@
/* MMC */
#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h
new file mode 100644
index 0000000..b011cb2
--- /dev/null
+++ b/include/configs/ls1021atsn.h
@@ -0,0 +1,250 @@
+/* SPDX-License-Identifier: GPL-2.0
+ * Copyright 2016-2018 NXP Semiconductors
+ * Copyright 2019 Vladimir Oltean <olteanv@gmail.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
+
+#define CONFIG_SYS_FSL_CLK
+
+#define CONFIG_DEEP_SLEEP
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
+
+#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
+
+/* XHCI Support - enabled by default */
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+
+#define CONFIG_SYS_CLK_FREQ 100000000
+#define CONFIG_DDR_CLK_FREQ 100000000
+
+#define DDR_SDRAM_CFG 0x470c0008
+#define DDR_CS0_BNDS 0x008000bf
+#define DDR_CS0_CONFIG 0x80014302
+#define DDR_TIMING_CFG_0 0x50550004
+#define DDR_TIMING_CFG_1 0xbcb38c56
+#define DDR_TIMING_CFG_2 0x0040d120
+#define DDR_TIMING_CFG_3 0x010e1000
+#define DDR_TIMING_CFG_4 0x00000001
+#define DDR_TIMING_CFG_5 0x03401400
+#define DDR_SDRAM_CFG_2 0x00401010
+#define DDR_SDRAM_MODE 0x00061c60
+#define DDR_SDRAM_MODE_2 0x00180000
+#define DDR_SDRAM_INTERVAL 0x18600618
+#define DDR_DDR_WRLVL_CNTL 0x8655f605
+#define DDR_DDR_WRLVL_CNTL_2 0x05060607
+#define DDR_DDR_WRLVL_CNTL_3 0x05050505
+#define DDR_DDR_CDR1 0x80040000
+#define DDR_DDR_CDR2 0x00000001
+#define DDR_SDRAM_CLK_CNTL 0x02000000
+#define DDR_DDR_ZQ_CNTL 0x89080600
+#define DDR_CS0_CONFIG_2 0
+#define DDR_SDRAM_CFG_MEM_EN 0x80000000
+#define SDRAM_CFG2_D_INIT 0x00000010
+#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
+#define SDRAM_CFG2_FRC_SR 0x80000000
+#define SDRAM_CFG_BI 0x00000001
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI \
+ "board/freescale/ls1021atsn/ls102xa_pbi.cfg"
+#endif
+
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_SYS_FSL_PBL_RCW \
+ "board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg"
+
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
+#endif /* ifdef CONFIG_SECURE_BOOT */
+
+#define CONFIG_SPL_MAX_SIZE 0x1a000
+#define CONFIG_SPL_STACK 0x1001d000
+#define CONFIG_SPL_PAD_TO 0x1c000
+
+#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
+#define CONFIG_SPL_BSS_START_ADDR 0x80100000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
+
+#ifdef CONFIG_U_BOOT_HDR_SIZE
+/*
+ * HDR would be appended at end of image and copied to DDR along
+ * with U-Boot image. Here u-boot max. size is 512K. So if binary
+ * size increases then increase this size in case of secure boot as
+ * it uses raw U-Boot image instead of FIT image.
+ */
+#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
+#else
+#define CONFIG_SYS_MONITOR_LEN 0x100000
+#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
+#endif
+
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM 0x80000000
+#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
+
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_CHIP_SELECTS_PER_CTRL 4
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550_SERIAL
+#ifndef CONFIG_DM_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#endif
+#define CONFIG_SYS_NS16550_CLK get_serial_clock()
+
+#define CONFIG_BAUDRATE 115200
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+
+/* QSPI */
+#define FSL_QSPI_FLASH_SIZE (1 << 24)
+#define FSL_QSPI_FLASH_NUM 2
+
+/* PCIe */
+#define CONFIG_PCIE1 /* PCIE controller 1 */
+#define CONFIG_PCIE2 /* PCIE controller 2 */
+#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+
+#define CONFIG_LAYERSCAPE_NS_ACCESS
+#define COUNTER_FREQUENCY 12500000
+
+#define CONFIG_HWCONFIG
+#define HWCONFIG_BUFFER_SIZE 256
+
+#define CONFIG_FSL_DEVICE_DISABLE
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(USB, usb, 0) \
+ func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
+ "initrd_high=0xffffffff\0" \
+ "fdt_high=0xffffffff\0" \
+ "fdt_addr=0x64f00000\0" \
+ "kernel_addr=0x61000000\0" \
+ "kernelheader_addr=0x60800000\0" \
+ "scriptaddr=0x80000000\0" \
+ "scripthdraddr=0x80080000\0" \
+ "fdtheader_addr_r=0x80100000\0" \
+ "kernelheader_addr_r=0x80200000\0" \
+ "kernel_addr_r=0x80008000\0" \
+ "kernelheader_size=0x40000\0" \
+ "fdt_addr_r=0x8f000000\0" \
+ "ramdisk_addr_r=0xa0000000\0" \
+ "load_addr=0x80008000\0" \
+ "kernel_size=0x2800000\0" \
+ "kernel_addr_sd=0x8000\0" \
+ "kernel_size_sd=0x14000\0" \
+ "kernelhdr_addr_sd=0x4000\0" \
+ "kernelhdr_size_sd=0x10\0" \
+ BOOTENV \
+ "boot_scripts=ls1021atsn_boot.scr\0" \
+ "boot_script_hdr=hdr_ls1021atsn_bs.out\0" \
+ "scan_dev_for_boot_part=" \
+ "part list ${devtype} ${devnum} devplist; " \
+ "env exists devplist || setenv devplist 1; " \
+ "for distro_bootpart in ${devplist}; do " \
+ "if fstype ${devtype} " \
+ "${devnum}:${distro_bootpart} " \
+ "bootfstype; then " \
+ "run scan_dev_for_boot; " \
+ "fi; " \
+ "done\0" \
+ "scan_dev_for_boot=" \
+ "echo Scanning ${devtype} " \
+ "${devnum}:${distro_bootpart}...; " \
+ "for prefix in ${boot_prefixes}; do " \
+ "run scan_dev_for_scripts; " \
+ "run scan_dev_for_extlinux; " \
+ "done;" \
+ "\0" \
+ "boot_a_script=" \
+ "load ${devtype} ${devnum}:${distro_bootpart} " \
+ "${scriptaddr} ${prefix}${script}; " \
+ "env exists secureboot && load ${devtype} " \
+ "${devnum}:${distro_bootpart} " \
+ "${scripthdraddr} ${prefix}${boot_script_hdr} " \
+ "&& esbc_validate ${scripthdraddr};" \
+ "source ${scriptaddr}\0" \
+ "qspi_bootcmd=echo Trying load from qspi..;" \
+ "sf probe && sf read $load_addr " \
+ "$kernel_addr $kernel_size; env exists secureboot " \
+ "&& sf read $kernelheader_addr_r $kernelheader_addr " \
+ "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
+ "bootm $load_addr#$board\0" \
+ "sd_bootcmd=echo Trying load from SD ..;" \
+ "mmcinfo && mmc read $load_addr " \
+ "$kernel_addr_sd $kernel_size_sd && " \
+ "env exists secureboot && mmc read $kernelheader_addr_r " \
+ "$kernelhdr_addr_sd $kernelhdr_size_sd " \
+ " && esbc_validate ${kernelheader_addr_r};" \
+ "bootm $load_addr#$board\0"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_LOAD_ADDR 0x82000000
+
+#define CONFIG_LS102XA_STREAM_ID
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+
+/* Environment */
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_SD_BOOT)
+#define CONFIG_ENV_OFFSET 0x300000
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_SIZE 0x20000
+#elif defined(CONFIG_QSPI_BOOT)
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_OFFSET 0x300000
+#define CONFIG_ENV_SECT_SIZE 0x40000
+#endif
+
+#define CONFIG_SYS_BOOTM_LEN 0x8000000 /* 128 MB */
+
+#endif
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index de0c9c7..31abee8 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -260,33 +260,7 @@
*/
#ifdef CONFIG_TSEC_ENET
-#define CONFIG_MII_DEFAULT_TSEC 1
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "eTSEC1"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "eTSEC2"
-#define CONFIG_TSEC3 1
-#define CONFIG_TSEC3_NAME "eTSEC3"
-
-#define TSEC1_PHY_ADDR 2
-#define TSEC2_PHY_ADDR 0
-#define TSEC3_PHY_ADDR 1
-
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC3_PHYIDX 0
-
-#define CONFIG_ETHPRIME "eTSEC1"
-
-#define CONFIG_PHY_ATHEROS
-
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
+#define CONFIG_ETHPRIME "ethernet@2d10000"
#endif
/* PCIe */
@@ -444,7 +418,7 @@
#undef CONFIG_BOOTCOMMAND
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd" \
+#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
"env exists secureboot && esbc_halt"
#elif defined(CONFIG_SD_BOOT)
#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h
index d3d787f..40fcd22 100644
--- a/include/configs/ls1028a_common.h
+++ b/include/configs/ls1028a_common.h
@@ -42,7 +42,9 @@
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
/* I2C */
+#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
+#endif
/* Serial Port */
#define CONFIG_CONS_INDEX 1
@@ -164,7 +166,6 @@
/* MMC */
#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
@@ -178,12 +179,6 @@
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-/* MMC */
-#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#endif
-
/* I2C bus multiplexer */
#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
#define I2C_MUX_CH_DEFAULT 0x8
@@ -201,4 +196,8 @@
#include <asm/fsl_secure_boot.h>
#endif
+/* Ethernet */
+/* smallest ENETC BD ring has 8 entries */
+#define CONFIG_SYS_RX_ETH_BUFFER 8
+
#endif /* __L1028A_COMMON_H */
diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h
index be018ef..b0e9441 100644
--- a/include/configs/ls1028aqds.h
+++ b/include/configs/ls1028aqds.h
@@ -16,7 +16,6 @@
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#define CONFIG_QIXIS_I2C_ACCESS
-#define CONFIG_SYS_I2C_EARLY_INIT
/*
* QIXIS Definitions
diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h
index 10791be..b77c36d 100644
--- a/include/configs/ls1028ardb.h
+++ b/include/configs/ls1028ardb.h
@@ -22,7 +22,6 @@
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_QIXIS_I2C_ACCESS
-#define CONFIG_SYS_I2C_EARLY_INIT
/*
* QIXIS Definitions
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index 0e4e370..0ea3ca0 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -382,7 +382,6 @@
/* QSPI device */
#if defined(CONFIG_TFABOOT) || \
(defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI))
-#define CONFIG_FSL_QSPI
#ifdef CONFIG_FSL_QSPI
#define CONFIG_SPI_FLASH_SPANSION
#define FSL_QSPI_FLASH_SIZE (1 << 24)
diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h
index 791bb8d..8609ebf 100644
--- a/include/configs/ls1046afrwy.h
+++ b/include/configs/ls1046afrwy.h
@@ -103,6 +103,9 @@
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */
#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */
+#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FSL_QSPI_BASE + \
+ CONFIG_ENV_OFFSET)
/* FMan */
#ifdef CONFIG_SYS_DPAA_FMAN
diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h
index e8e1dc2..6f04dba 100644
--- a/include/configs/ls1088a_common.h
+++ b/include/configs/ls1088a_common.h
@@ -67,7 +67,10 @@
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
/* I2C */
+#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
+#endif
+
/* Serial Port */
#define CONFIG_SYS_NS16550_SERIAL
diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h
index 4387862..85e20617 100644
--- a/include/configs/ls1088aqds.h
+++ b/include/configs/ls1088aqds.h
@@ -17,6 +17,8 @@
#ifdef CONFIG_TFABOOT
#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_MISC_INIT_R
+
#define CONFIG_ENV_SIZE 0x20000
#define CONFIG_ENV_OFFSET 0x500000
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
@@ -46,7 +48,9 @@
#define CONFIG_DDR_CLK_FREQ 100000000
#else
#define CONFIG_QIXIS_I2C_ACCESS
+#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C_EARLY_INIT
+#endif
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
#endif
@@ -357,9 +361,7 @@
* RTC configuration
*/
#define RTC
-#define CONFIG_RTC_PCF8563 1
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
-#define CONFIG_CMD_DATE
/* EEPROM */
#define CONFIG_ID_EEPROM
diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h
index 322adb5..b71f704 100644
--- a/include/configs/ls1088ardb.h
+++ b/include/configs/ls1088ardb.h
@@ -269,9 +269,7 @@
* RTC configuration
*/
#define RTC
-#define CONFIG_RTC_PCF8563 1
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
-#define CONFIG_CMD_DATE
#endif
/* EEPROM */
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index c7d8a3b..6be581a 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -75,7 +75,9 @@
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
/* I2C */
+#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
+#endif
/* Serial Port */
#define CONFIG_SYS_NS16550_SERIAL
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 18f30b5..e2a8975 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -16,7 +16,9 @@
#ifdef CONFIG_FSL_QSPI
#define CONFIG_QIXIS_I2C_ACCESS
+#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C_EARLY_INIT
+#endif
#define CONFIG_SYS_I2C_IFDR_DIV 0x7e
#endif
@@ -324,7 +326,9 @@
*/
#define RTC
#define CONFIG_RTC_DS3231 1
+#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT
/* EEPROM */
#define CONFIG_ID_EEPROM
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index bfb54be..2bf8217 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -13,8 +13,10 @@
#ifdef CONFIG_TARGET_LS2081ARDB
#define CONFIG_QIXIS_I2C_ACCESS
#endif
+#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C_EARLY_INIT
#endif
+#endif
#define I2C_MUX_CH_VOL_MONITOR 0xa
#define I2C_VOL_MONITOR_ADDR 0x38
diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h
index 55c4e63..3ba5548 100644
--- a/include/configs/lsxl.h
+++ b/include/configs/lsxl.h
@@ -29,7 +29,6 @@
#define CONFIG_KW88F6281 /* SOC Name */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-#define CONFIG_SHOW_BOOT_PROGRESS
#define CONFIG_KIRKWOOD_GPIO
diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
index 711b434..110d497 100644
--- a/include/configs/lx2160a_common.h
+++ b/include/configs/lx2160a_common.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2018 NXP
+ * Copyright 2018-2019 NXP
*/
#ifndef __LX2_COMMON_H
@@ -199,14 +199,14 @@
"fsl_mc start mc 0x20a00000 0x20e00000\0"
#define SD_MC_INIT_CMD \
- "mmc read 0x80000000 0x5000 0x800;" \
- "mmc read 0x80100000 0x7000 0x800;" \
+ "mmc read 0x80a00000 0x5000 0x1200;" \
+ "mmc read 0x80e00000 0x7000 0x800;" \
"env exists secureboot && " \
"mmc read 0x80700000 0x3800 0x10 && " \
"mmc read 0x80740000 0x3A00 0x10 && " \
"esbc_validate 0x80700000 && " \
"esbc_validate 0x80740000 ;" \
- "fsl_mc start mc 0x80000000 0x80100000\0"
+ "fsl_mc start mc 0x80a00000 0x80e00000\0"
#define EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
@@ -265,11 +265,11 @@
#define SD_BOOTCOMMAND \
"env exists mcinitcmd && mmcinfo; " \
- "mmc read 0x80001000 0x6800 0x800; " \
+ "mmc read 0x80d00000 0x6800 0x800; " \
"env exists mcinitcmd && env exists secureboot " \
" && mmc read 0x80780000 0x3C00 0x10 " \
"&& esbc_validate 0x80780000;env exists mcinitcmd " \
- "&& fsl_mc lazyapply dpl 0x80001000;" \
+ "&& fsl_mc lazyapply dpl 0x80d00000;" \
"run distro_bootcmd;run sd_bootcmd;" \
"env exists secureboot && esbc_halt;"
diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h
index 7b68c1c..49f11ea 100644
--- a/include/configs/m53menlo.h
+++ b/include/configs/m53menlo.h
@@ -70,7 +70,6 @@
#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_MXC_NAND_HWECC
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
/* Environment is in NAND */
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
@@ -185,7 +184,6 @@
/*
* Extra Environments
*/
-#define CONFIG_PREBOOT "run try_bootscript"
#define CONFIG_HOSTNAME "m53menlo"
#define CONFIG_EXTRA_ENV_SETTINGS \
@@ -242,4 +240,9 @@
"fi ; " \
"fi\0"
+#if defined(CONFIG_SPL_BUILD)
+#undef CONFIG_WATCHDOG
+#define CONFIG_HW_WATCHDOG
+#endif
+
#endif /* __M53MENLO_CONFIG_H__ */
diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h
index a017d92..9d5fbcd 100644
--- a/include/configs/maxbcm.h
+++ b/include/configs/maxbcm.h
@@ -71,7 +71,6 @@
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
/* SPL related SPI defines */
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
#define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */
diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h
index a1774c0..667dac7 100644
--- a/include/configs/mccmon6.h
+++ b/include/configs/mccmon6.h
@@ -65,13 +65,6 @@
#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) }
#define CONFIG_SYS_FLASH_BANKS_SIZES { (32 * SZ_1M) }
-/* MTD support */
-
-/* USB Configs */
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CONFIG_MXC_USB_FLAGS 0
-
/* Ethernet Configuration */
#define CONFIG_FEC_MXC
#define IMX_FEC_BASE ENET_BASE_ADDR
@@ -85,6 +78,7 @@
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"boot_os=yes\0" \
+ "disable_giga=yes\0" \
"download_kernel=" \
"tftpboot ${kernel_addr} ${kernel_file};" \
"tftpboot ${fdt_addr} ${fdtfile};\0" \
diff --git a/include/configs/meesc.h b/include/configs/meesc.h
index a1fd5f6..3a173a2 100644
--- a/include/configs/meesc.h
+++ b/include/configs/meesc.h
@@ -33,15 +33,12 @@
/* Misc CPU related */
#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_SERIAL_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_PREBOOT /* enable preboot variable */
-
/*
* Hardware drivers
*/
diff --git a/include/configs/meson64.h b/include/configs/meson64.h
index d82a674..f8d3eee 100644
--- a/include/configs/meson64.h
+++ b/include/configs/meson64.h
@@ -31,14 +31,15 @@
#ifdef CONFIG_USB_KEYBOARD
#define STDIN_CFG "usbkbd,serial"
-#define CONFIG_PREBOOT "usb start"
#else
#define STDIN_CFG "serial"
#endif
#define CONFIG_CPU_ARMV8
#define CONFIG_REMAKE_ELF
+#ifndef CONFIG_ENV_SIZE
#define CONFIG_ENV_SIZE 0x2000
+#endif
#define CONFIG_SYS_MAXARGS 32
#define CONFIG_SYS_MALLOC_LEN (32 << 20)
#define CONFIG_SYS_CBSIZE 1024
diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index d1ab40e..814fec5 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -140,8 +140,6 @@
/* architecture dependent code */
#define CONFIG_SYS_USR_EXCEP /* user exception */
-#define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo"
-
#ifndef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \
"nor0=flash-0\0"\
diff --git a/include/configs/mt7629.h b/include/configs/mt7629.h
index 6e9b868..741b6fb 100644
--- a/include/configs/mt7629.h
+++ b/include/configs/mt7629.h
@@ -38,7 +38,6 @@
#define CONFIG_SPL_PAD_TO 0x10000
#define CONFIG_SPI_ADDR 0x30000000
-#define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO
#define CONFIG_SYS_UBOOT_BASE (CONFIG_SPI_ADDR + CONFIG_SPL_PAD_TO)
/* SPL -> Uboot */
diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h
index a803093..a041ddb 100644
--- a/include/configs/mv-common.h
+++ b/include/configs/mv-common.h
@@ -38,7 +38,6 @@
#endif
/* auto boot */
-#define CONFIG_PREBOOT
/*
* For booting Linux, the board info and command line data
@@ -59,7 +58,6 @@
/*
* Other required minimal configurations
*/
-#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
#define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */
#define CONFIG_SYS_MEMTEST_END 0x00ffffff /*(_16M -1) */
diff --git a/include/configs/mvebu_armada-37xx.h b/include/configs/mvebu_armada-37xx.h
index 10b94f4..bc24903 100644
--- a/include/configs/mvebu_armada-37xx.h
+++ b/include/configs/mvebu_armada-37xx.h
@@ -14,7 +14,6 @@
#define CONFIG_SYS_SDRAM_BASE 0x00000000
/* auto boot */
-#define CONFIG_PREBOOT
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
115200, 230400, 460800, 921600 }
@@ -38,7 +37,6 @@
/*
* Other required minimal configurations
*/
-#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
#define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */
#define CONFIG_SYS_MEMTEST_END 0x00ffffff /*(_16M -1) */
diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h
index b28f3b9..3be3683 100644
--- a/include/configs/mvebu_armada-8k.h
+++ b/include/configs/mvebu_armada-8k.h
@@ -15,7 +15,6 @@
#define CONFIG_SYS_SDRAM_BASE 0x00000000
/* auto boot */
-#define CONFIG_PREBOOT
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
115200, 230400, 460800, 921600 }
@@ -39,7 +38,6 @@
/*
* Other required minimal configurations
*/
-#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
#define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */
#define CONFIG_SYS_MEMTEST_END 0x00ffffff /*(_16M -1) */
@@ -59,7 +57,6 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
/*
* Ethernet Driver configuration
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
index f5fd01d..fc498b2 100644
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -66,7 +66,6 @@
#define CONFIG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED
/* Framebuffer and LCD */
-#define CONFIG_PREBOOT
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_SPLASH_SCREEN
#define CONFIG_BMP_16BPP
diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h
index 46ff99b..d25629f 100644
--- a/include/configs/mx53ard.h
+++ b/include/configs/mx53ard.h
@@ -28,7 +28,6 @@
#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_MXC_NAND_HWECC
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h
index ab61a07..bbe0574 100644
--- a/include/configs/mx53cx9020.h
+++ b/include/configs/mx53cx9020.h
@@ -160,6 +160,5 @@
/* Framebuffer and LCD */
#define CONFIG_IMX_VIDEO_SKIP
-#define CONFIG_PREBOOT
#endif /* __CONFIG_H */
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
index 4f17908..b734b82 100644
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
@@ -176,7 +176,6 @@
#endif
/* Framebuffer and LCD */
-#define CONFIG_PREBOOT
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_SPLASH_SCREEN
#define CONFIG_BMP_16BPP
diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h
index 2d6715c..d5b54df 100644
--- a/include/configs/mx53ppd.h
+++ b/include/configs/mx53ppd.h
@@ -211,7 +211,6 @@
#define CONFIG_BCH
/* Backlight Control */
-#define CONFIG_PWM_IMX
#define CONFIG_IMX6_PWM_PER_CLK 66666000
#endif /* __CONFIG_H */
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index 2b8ce9d..f6c0e21 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -55,7 +55,6 @@
#define CONFIG_SYS_MAXARGS 32
/* MMC */
-#define CONFIG_FSL_USDHC
/* Secure boot (HAB) support */
#ifdef CONFIG_SECURE_BOOT
diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h
index 7b4ae21..3cf2f1c 100644
--- a/include/configs/mx6cuboxi.h
+++ b/include/configs/mx6cuboxi.h
@@ -49,17 +49,6 @@
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_PREBOOT \
- "if hdmidet; then " \
- "usb start; " \
- "setenv stdin serial,usbkbd; "\
- "setenv stdout serial,vga; " \
- "setenv stderr serial,vga; " \
- "else " \
- "setenv stdin serial; " \
- "setenv stdout serial; " \
- "setenv stderr serial; " \
- "fi;"
/* Command definition */
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
index c137612..d704cda 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -62,6 +62,7 @@
"dfu_alt_info=spl raw 0x400\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
+ "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"mmcpart=1\0" \
"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
index 4f822ef..70dda35 100644
--- a/include/configs/mx7_common.h
+++ b/include/configs/mx7_common.h
@@ -40,7 +40,6 @@
#define CONFIG_MXC_UART
/* MMC */
-#define CONFIG_FSL_USDHC
#define CONFIG_ARMV7_SECURE_BASE 0x00900000
diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h
index 77856a8..e1f92da 100644
--- a/include/configs/mx7dsabresd.h
+++ b/include/configs/mx7dsabresd.h
@@ -30,10 +30,6 @@
/* MMC Config*/
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#undef CONFIG_BOOTM_NETBSD
-#undef CONFIG_BOOTM_PLAN9
-#undef CONFIG_BOOTM_RTEMS
-
/* I2C configs */
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_SPEED 100000
diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h
index 2af5a4f..763a46b 100644
--- a/include/configs/mx7ulp_evk.h
+++ b/include/configs/mx7ulp_evk.h
@@ -27,8 +27,6 @@
#define IRAM_BASE_ADDR OCRAM_0_BASE
#define IOMUXC_BASE_ADDR IOMUXC1_RBASE
-#define CONFIG_FSL_USDHC
-
#define CONFIG_SYS_FSL_USDHC_NUM 1
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
diff --git a/include/configs/mxs.h b/include/configs/mxs.h
index cc5d4c8..6cadd72 100644
--- a/include/configs/mxs.h
+++ b/include/configs/mxs.h
@@ -94,12 +94,6 @@
/*
* Drivers
*/
-
-/* APBH DMA */
-
-/* GPIO */
-#define CONFIG_MXS_GPIO
-
/*
* DUART Serial Driver.
* Conflicts with AUART driver which can be set by board.
diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
index afaa908..23c370b 100644
--- a/include/configs/nitrogen6x.h
+++ b/include/configs/nitrogen6x.h
@@ -67,8 +67,6 @@
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
-#define CONFIG_PREBOOT ""
-
#ifdef CONFIG_CMD_MMC
#define DISTRO_BOOT_DEV_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1)
#else
diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h
index 453dd32..fd755bb 100644
--- a/include/configs/nokia_rx51.h
+++ b/include/configs/nokia_rx51.h
@@ -50,7 +50,6 @@
/*
* Size of malloc() pool
*/
-#define CONFIG_ENV_SIZE (128 << 10)
#define CONFIG_UBI_SIZE (512 << 10)
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + CONFIG_UBI_SIZE + \
(128 << 10))
@@ -254,30 +253,6 @@
"bootmenu_delay=30\0" \
""
-#define CONFIG_PREBOOT \
- "setenv mmcnum 1; setenv mmcpart 1;" \
- "setenv mmcscriptfile bootmenu.scr;" \
- "if run switchmmc; then " \
- "setenv mmcdone true;" \
- "setenv mmctype fat;" \
- "if run scriptload; then true; else " \
- "setenv mmctype ext2;" \
- "if run scriptload; then true; else " \
- "setenv mmctype ext4;" \
- "if run scriptload; then true; else " \
- "setenv mmcdone false;" \
- "fi;" \
- "fi;" \
- "fi;" \
- "if ${mmcdone}; then " \
- "run scriptboot;" \
- "fi;" \
- "fi;" \
- "if run slide; then true; else " \
- "setenv bootmenu_delay 0;" \
- "setenv bootdelay 0;" \
- "fi"
-
#define CONFIG_POSTBOOTMENU \
"echo;" \
"echo Extra commands:;" \
@@ -295,8 +270,6 @@
"run attachboot;" \
"echo"
-#define CONFIG_MENU_SHOW
-
/*
* Miscellaneous configurable options
*/
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index f0c8c99..e8c6083 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -40,7 +40,6 @@
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
#define CONFIG_SYS_ENV_SECT_SIZE SZ_128K
-#define CONFIG_ENV_OFFSET 0x260000
#define CONFIG_ENV_ADDR 0x260000
#define CONFIG_ENV_OVERWRITE
/* NAND: SPL falcon mode configs */
@@ -59,11 +58,6 @@
/* TWL4030 LED Support */
-/* Environment */
-#define CONFIG_ENV_SIZE SZ_128K
-
-#define CONFIG_PREBOOT "usb start"
-
#define MEM_LAYOUT_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV
diff --git a/include/configs/omap3_cairo.h b/include/configs/omap3_cairo.h
index ef69b24..9e2b752 100644
--- a/include/configs/omap3_cairo.h
+++ b/include/configs/omap3_cairo.h
@@ -160,11 +160,7 @@
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
-#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
-
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_ENV_OFFSET 0x260000
#define CONFIG_ENV_ADDR 0x260000
/* Defines for SPL */
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index 5b9d8a5..8e98977 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -44,7 +44,6 @@
#define CONFIG_SYS_NAND_ECCBYTES 3
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
#define CONFIG_SYS_ENV_SECT_SIZE SZ_128K
-#define CONFIG_ENV_OFFSET 0x260000
#define CONFIG_ENV_ADDR 0x260000
#define CONFIG_ENV_OVERWRITE
/* NAND: SPL falcon mode configs */
@@ -53,11 +52,6 @@
#endif /* CONFIG_SPL_OS_BOOT */
#endif /* CONFIG_NAND */
-/* Environment */
-#define CONFIG_ENV_SIZE SZ_128K
-
-#define CONFIG_PREBOOT "usb start"
-
#define MEM_LAYOUT_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV
diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h
index 23d12c6..4ad7dc1 100644
--- a/include/configs/omap3_igep00x0.h
+++ b/include/configs/omap3_igep00x0.h
@@ -96,24 +96,4 @@
#define CONFIG_SYS_NAND_ECCBYTES 14
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
-/* UBI configuration */
-#define CONFIG_SPL_UBI 1
-#define CONFIG_SPL_UBI_MAX_VOL_LEBS 256
-#define CONFIG_SPL_UBI_MAX_PEB_SIZE (256*1024)
-#define CONFIG_SPL_UBI_MAX_PEBS 4096
-#define CONFIG_SPL_UBI_VOL_IDS 8
-#define CONFIG_SPL_UBI_LOAD_MONITOR_ID 0
-#define CONFIG_SPL_UBI_LOAD_KERNEL_ID 3
-#define CONFIG_SPL_UBI_LOAD_ARGS_ID 4
-#define CONFIG_SPL_UBI_PEB_OFFSET 4
-#define CONFIG_SPL_UBI_VID_OFFSET 512
-#define CONFIG_SPL_UBI_LEB_START 2048
-#define CONFIG_SPL_UBI_INFO_ADDR 0x88080000
-
-/* environment organization */
-#define CONFIG_ENV_UBI_PART "UBI"
-#define CONFIG_ENV_UBI_VOLUME "config"
-#define CONFIG_ENV_UBI_VOLUME_REDUND "config_r"
-#define CONFIG_ENV_SIZE (32*1024)
-
#endif /* __IGEP00X0_H */
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
index e318a9f..90292ae 100644
--- a/include/configs/omap3_logic.h
+++ b/include/configs/omap3_logic.h
@@ -30,6 +30,13 @@
/* I2C */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_USB_EHCI_OMAP
+#endif
+#ifdef CONFIG_USB_EHCI_OMAP
+#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 4
+#endif
+
/* Board NAND Info. */
#ifdef CONFIG_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
@@ -56,10 +63,6 @@
/* Environment information */
-#define CONFIG_PREBOOT \
- "setenv preboot;" \
- "saveenv;"
-
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
@@ -194,10 +197,7 @@
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
-
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_ENV_OFFSET 0x260000
#define CONFIG_ENV_ADDR 0x260000
/* Defines for SPL */
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index ea941db..38a10e2 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -19,7 +19,6 @@
/* override size of malloc() pool */
#undef CONFIG_SYS_MALLOC_LEN
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
/* Shift 128 << 15 provides 4 MiB heap to support UBI commands.
* Shift 128 << 10 provides 128 KiB heap for limited-memory devices. */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 15))
diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h
index 82c66c4..98f243f 100644
--- a/include/configs/omap3_pandora.h
+++ b/include/configs/omap3_pandora.h
@@ -15,8 +15,6 @@
#define CONFIG_REVISION_TAG 1
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
-
#define CONFIG_SYS_DEVICE_NULLDEV 1
/*
@@ -63,7 +61,6 @@
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_ENV_OFFSET 0x260000
#define CONFIG_ENV_ADDR 0x260000
#endif /* __CONFIG_H */
diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h
index 0a02ecd..4dc22a7 100644
--- a/include/configs/omap3_zoom1.h
+++ b/include/configs/omap3_zoom1.h
@@ -23,8 +23,6 @@
#define CONFIG_REVISION_TAG 1
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
-
/*
* Hardware drivers
*/
@@ -132,7 +130,6 @@
#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_ENV_OFFSET 0x260000
#define CONFIG_ENV_ADDR 0x260000
#endif /* __CONFIG_H */
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index 0d8f945..3710a71 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
@@ -32,8 +32,6 @@
/* MMC ENV related defines */
#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
-#define CONFIG_ENV_SIZE (128 << 10)
-#define CONFIG_ENV_OFFSET 0x260000
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
@@ -55,7 +53,7 @@
/* USB Networking options */
-#define CONSOLEDEV "ttyO2"
+#define CONSOLEDEV "ttyS2"
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index da615e5..1c41e7e 100644
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h
@@ -13,18 +13,8 @@
/*
* Board
*/
-#undef CONFIG_USE_SPIFLASH
-#undef CONFIG_SYS_USE_NOR
/*
-* Disable DM_* for SPL build and can be re-enabled after adding
-* DM support in SPL
-*/
-#ifdef CONFIG_SPL_BUILD
-#undef CONFIG_DM_I2C
-#undef CONFIG_DM_I2C_COMPAT
-#endif
-/*
* SoC Configuration
*/
#define CONFIG_MACH_OMAPL138_LCDK
@@ -112,22 +102,10 @@
* Serial Driver info
*/
#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
-#if !defined(CONFIG_DM_SERIAL)
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
-#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
-#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-#endif
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
-#ifdef CONFIG_USE_SPIFLASH
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
-#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000
-#endif
-
/*
* I2C Configuration
*/
@@ -141,7 +119,6 @@
#ifdef CONFIG_NAND
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
#define CONFIG_ENV_SIZE (128 << 9)
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
#define CONFIG_SYS_NAND_PAGE_2K
#define CONFIG_SYS_NAND_CS 3
@@ -178,24 +155,6 @@
#define CONFIG_SPL_NAND_LOAD
#endif
-#ifdef CONFIG_SYS_USE_NOR
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
-#define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */
-#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3)
-#define CONFIG_ENV_SIZE (128 << 10)
-#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
-#define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */
-#define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
- + 3)
-#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
-#endif
-
-#ifdef CONFIG_USE_SPIFLASH
-#define CONFIG_ENV_SIZE (64 << 10)
-#define CONFIG_ENV_OFFSET (256 << 10)
-#define CONFIG_ENV_SECT_SIZE (64 << 10)
-#endif
-
/*
* Network & Ethernet Configuration
*/
@@ -214,7 +173,12 @@
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
-#define CONFIG_MX_CYCLIC
+
+/*
+ * USB Configs
+ */
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
/*
* Linux Information
@@ -249,12 +213,6 @@
#define CONFIG_CLOCKS
#endif
-#if !defined(CONFIG_NAND) && \
- !defined(CONFIG_SYS_USE_NOR) && \
- !defined(CONFIG_USE_SPIFLASH)
-#define CONFIG_ENV_SIZE (16 << 10)
-#endif
-
/* SD/MMC */
#ifdef CONFIG_ENV_IS_IN_MMC
@@ -264,7 +222,6 @@
#define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */
#endif
-#ifndef CONFIG_DIRECT_NOR_BOOT
/* defines for SPL */
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
CONFIG_SYS_MALLOC_LEN)
@@ -272,7 +229,6 @@
#define CONFIG_SPL_STACK 0x8001ff00
#define CONFIG_SPL_MAX_FOOTPRINT 32768
#define CONFIG_SPL_PAD_TO 32768
-#endif
/* additions for new relocation code, must added to all boards */
#define CONFIG_SYS_SDRAM_BASE 0xc0000000
diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h
index e0c76ff..309b471 100644
--- a/include/configs/opos6uldev.h
+++ b/include/configs/opos6uldev.h
@@ -76,7 +76,6 @@
#define ACFG_CONSOLE_DEV ttymxc0
#define CONFIG_SYS_AUTOLOAD "no"
#define CONFIG_ROOTPATH "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root"
-#define CONFIG_PREBOOT "run check_env"
#define CONFIG_BOOTCOMMAND "run emmcboot"
#define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h
index 925e7ae..4efef89 100644
--- a/include/configs/ot1200.h
+++ b/include/configs/ot1200.h
@@ -59,7 +59,6 @@
/* SPL */
#ifdef CONFIG_SPL
#include "imx6_spl.h"
-#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
#endif
#define CONFIG_FEC_MXC
@@ -77,8 +76,6 @@
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#endif
-#define CONFIG_PREBOOT ""
-
/* Thermal support */
#define CONFIG_IMX_THERMAL
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index e07d2a1..1481d68 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -207,8 +207,6 @@
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_ENV_OVERWRITE
@@ -572,44 +570,56 @@
*/
/* controller 2, direct to uli, tgtid 2, Base address 9000 */
-#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT"
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
#else
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
#endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
#else
#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
#endif
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
/* controller 1, Slot 2, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
#else
#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
#endif
+
+#if !defined(CONFIG_DM_PCI)
+#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT"
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
+#else
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
+#endif
+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
+
+#define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
+#endif
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif /* CONFIG_PCI */
diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h
index 8fef250..943fca9 100644
--- a/include/configs/pcl063.h
+++ b/include/configs/pcl063.h
@@ -31,7 +31,6 @@
#define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configs */
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h
index 0f1a010..650caaa 100644
--- a/include/configs/pcl063_ull.h
+++ b/include/configs/pcl063_ull.h
@@ -37,7 +37,6 @@
#define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configs */
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
#define CONFIG_SUPPORT_EMMC_BOOT
diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h
index 8cde12e..fdbc075 100644
--- a/include/configs/pcm051.h
+++ b/include/configs/pcm051.h
@@ -21,7 +21,6 @@
#include <configs/ti_am335x_common.h>
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
#define CONFIG_MACH_TYPE MACH_TYPE_PCM051
/* set to negative value for no autoboot */
@@ -118,7 +117,6 @@
/* CPU */
#ifdef CONFIG_SPI_BOOT
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
#endif
diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h
index b0415b2..855bc44 100644
--- a/include/configs/pcm058.h
+++ b/include/configs/pcm058.h
@@ -8,7 +8,6 @@
#define __PCM058_CONFIG_H
#ifdef CONFIG_SPL
-#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
#include "imx6_spl.h"
#endif
@@ -51,7 +50,6 @@
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
#endif
/* DMA stuff, needed for GPMI/MXS NAND support */
diff --git a/include/configs/pepper.h b/include/configs/pepper.h
index ef662d7..662fce3 100644
--- a/include/configs/pepper.h
+++ b/include/configs/pepper.h
@@ -17,8 +17,6 @@
/* Mach type */
#define CONFIG_MACH_TYPE MACH_TYPE_PEPPER
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
-
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
"bootdir=/boot\0" \
diff --git a/include/configs/pfla02.h b/include/configs/pfla02.h
index 3a9b85a..8731d89 100644
--- a/include/configs/pfla02.h
+++ b/include/configs/pfla02.h
@@ -8,7 +8,6 @@
#define __PCM058_CONFIG_H
#ifdef CONFIG_SPL
-#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
#include "imx6_spl.h"
#endif
diff --git a/include/configs/phycore_am335x_r2.h b/include/configs/phycore_am335x_r2.h
new file mode 100644
index 0000000..ca28b6f
--- /dev/null
+++ b/include/configs/phycore_am335x_r2.h
@@ -0,0 +1,127 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * phycore_am335x_r2.h
+ *
+ * Phytec phyCORE-AM335x R2 (PCL060 / PCM060) boards information header
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH
+ * Copyright (C) 2019 DENX Software Engineering GmbH
+ */
+
+#ifndef __CONFIG_PHYCORE_AM335x_R2_H
+#define __CONFIG_PHYCORE_AM335x_R2_H
+
+#include <configs/ti_am335x_common.h>
+
+#define CONFIG_MACH_TYPE MACH_TYPE_SBC_PHYCORE_AM335X
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
+
+#ifdef CONFIG_NAND
+#define NANDARGS \
+ "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
+ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+ "nandargs=setenv bootargs console=${console} " \
+ "${optargs} " \
+ "root=${nandroot} " \
+ "rootfstype=${nandrootfstype}\0" \
+ "nandroot=ubi0:root ubi.mtd=NAND.UBI\0" \
+ "nandrootfstype=ubifs rootwait rw fsck.repair=yes\0" \
+ "nandboot=echo Booting from nand ...; " \
+ "run nandargs; " \
+ "ubi part NAND.UBI; " \
+ "ubi readvol ${fdtaddr} oftree; " \
+ "ubi readvol ${loadaddr} kernel; " \
+ "bootz ${loadaddr} - ${fdtaddr}\0"
+
+#else
+#define NANDARGS ""
+#endif
+
+/* set to negative value for no autoboot */
+#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \
+ "bootcmd_" #devtypel #instance "=" \
+ "setenv mmcdev " #instance "; "\
+ "setenv bootpart " #instance ":1 ; "\
+ "setenv rootpart " #instance ":2 ; "\
+ "run mmcboot\0"
+
+#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \
+ #devtypel #instance " "
+
+#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
+ "bootcmd_" #devtypel #instance "=" \
+ "run nandboot\0"
+
+#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
+ #devtypel #instance " "
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(LEGACY_MMC, legacy_mmc, 0) \
+ func(MMC, mmc, 1) \
+ func(LEGACY_MMC, legacy_mmc, 1) \
+ func(NAND, nand, 0)
+
+#include <config_distro_bootcmd.h>
+#include <environment/ti/dfu.h>
+#include <environment/ti/mmc.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ DEFAULT_MMC_TI_ARGS \
+ DEFAULT_LINUX_BOOT_ENV \
+ "bootfile=zImage\0" \
+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "console=ttyS0,115200\0" \
+ "optargs=\0" \
+ "mmcrootfstype=ext2 rootwait\0" \
+ "finduuid=part uuid mmc ${rootpart} uuid\0" \
+ "boot_fit=0\0" \
+ NANDARGS \
+ BOOTENV
+
+/* Clock Macros */
+#define V_OSCK 25000000 /* Clock output from T2 */
+#define V_SCLK V_OSCK
+
+#define CONFIG_POWER_TPS65910
+
+#ifdef CONFIG_NAND
+/* NAND: device related configs */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
+ CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+/* NAND: driver related configs */
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+ 10, 11, 12, 13, 14, 15, 16, 17, \
+ 18, 19, 20, 21, 22, 23, 24, 25, \
+ 26, 27, 28, 29, 30, 31, 32, 33, \
+ 34, 35, 36, 37, 38, 39, 40, 41, \
+ 42, 43, 44, 45, 46, 47, 48, 49, \
+ 50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE 512
+#define CONFIG_SYS_NAND_ECCBYTES 14
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
+
+/* NAND: SPL related configs */
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */
+#endif
+#endif /* !CONFIG_NAND */
+
+/* CPU */
+
+#ifdef CONFIG_SPI_BOOT
+#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#endif
+
+#endif /* ! __CONFIG_PHYCORE_AM335x_R2_H */
diff --git a/include/configs/platinum.h b/include/configs/platinum.h
index d1ebaf5..1b57e99 100644
--- a/include/configs/platinum.h
+++ b/include/configs/platinum.h
@@ -102,7 +102,6 @@
#define CONFIG_BOOTCOMMAND "run bootubi_scr"
/* Miscellaneous configurable options */
-#define CONFIG_PREBOOT
/* MTD/UBI/UBIFS config */
diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h
index c1ce122..99ca1f7 100644
--- a/include/configs/pm9261.h
+++ b/include/configs/pm9261.h
@@ -26,7 +26,6 @@
#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261"
-#define CONFIG_ARCH_CPU_INIT
#define CONFIG_MACH_TYPE MACH_TYPE_PM9261
diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h
index b09d851..595acf1 100644
--- a/include/configs/pm9263.h
+++ b/include/configs/pm9263.h
@@ -26,7 +26,6 @@
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9263"
-#define CONFIG_ARCH_CPU_INIT
#define CONFIG_MACH_TYPE MACH_TYPE_PM9263
diff --git a/include/configs/porter.h b/include/configs/porter.h
index 1db2886..db42176 100644
--- a/include/configs/porter.h
+++ b/include/configs/porter.h
@@ -45,7 +45,6 @@
/* SPL support */
#define CONFIG_SPL_STACK 0xe6340000
#define CONFIG_SPL_MAX_SIZE 0x4000
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
#ifdef CONFIG_SPL_BUILD
#define CONFIG_CONS_SCIF0
#define CONFIG_SH_SCIF_CLK_FREQ 65000000
diff --git a/include/configs/pumpkin.h b/include/configs/pumpkin.h
new file mode 100644
index 0000000..b2dda64
--- /dev/null
+++ b/include/configs/pumpkin.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration for Pumpkin board
+ *
+ * Copyright (C) 2019 BayLibre, SAS
+ * Author: Fabien Parent <fparent@baylibre.com
+ */
+
+#ifndef __PUMPKIN_H
+#define __PUMPKIN_H
+
+#include <linux/sizes.h>
+
+#define CONFIG_ENV_SIZE SZ_4K
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MALLOC_LEN SZ_4M
+
+#define CONFIG_CPU_ARMV8
+#define COUNTER_FREQUENCY 13000000
+
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_NS16550_COM1 0x11005000
+#define CONFIG_SYS_NS16550_CLK 26000000
+
+#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - \
+ GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_BOOTM_LEN SZ_64M
+
+/* Environment settings */
+#include <config_distro_bootcmd.h>
+
+#define MMCBOOT \
+ "mmcdev=0\0" \
+ "kernel_partition=2\0" \
+ "rootfs_partition=3\0" \
+ "mmc_discover_partition=" \
+ "part start mmc ${mmcdev} ${kernel_partition} kernel_part_addr;" \
+ "part size mmc ${mmcdev} ${kernel_partition} kernel_part_size;\0" \
+ "mmcboot=" \
+ "mmc dev ${mmcdev};" \
+ "run mmc_discover_partition;" \
+ "mmc read ${kerneladdr} ${kernel_part_addr} ${kernel_part_size};" \
+ "setenv bootargs ${bootargs} root=/dev/mmcblk${mmcdev}p${rootfs_partition} rootwait; " \
+ "bootm ${kerneladdr}; \0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "kerneladdr=0x4A000000\0" \
+ MMCBOOT \
+ "bootcmd=run mmcboot;\0"
+
+#endif
diff --git a/include/configs/qemu-arm.h b/include/configs/qemu-arm.h
index 65fdb1e..c7aaafa 100644
--- a/include/configs/qemu-arm.h
+++ b/include/configs/qemu-arm.h
@@ -32,7 +32,6 @@
#include <config_distro_bootcmd.h>
-#define CONFIG_PREBOOT "pci enum"
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
@@ -46,8 +45,13 @@
#define CONFIG_SYS_CBSIZE 512
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_FLASH_BASE 0x4000000
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#else
#define CONFIG_SYS_FLASH_BASE 0x0
#define CONFIG_SYS_MAX_FLASH_BANKS 2
+#endif
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* Sector: 256K, Bank: 64M */
#endif /* __CONFIG_H */
diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h
index df22f78..fa9b9af 100644
--- a/include/configs/qemu-riscv.h
+++ b/include/configs/qemu-riscv.h
@@ -8,6 +8,18 @@
#include <linux/sizes.h>
+#ifdef CONFIG_SPL
+
+#define CONFIG_SPL_MAX_SIZE 0x00100000
+#define CONFIG_SPL_BSS_START_ADDR 0x84000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
+#define CONFIG_SYS_SPL_MALLOC_START 0x84100000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
+
+#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x80200000
+
+#endif
+
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M)
@@ -22,6 +34,7 @@
/* Environment options */
#define CONFIG_ENV_SIZE SZ_128K
+#ifndef CONFIG_SPL_BUILD
#define BOOT_TARGET_DEVICES(func) \
func(QEMU, qemu, na) \
func(VIRTIO, virtio, 0) \
@@ -47,9 +60,6 @@
"pxefile_addr_r=0x88200000\0" \
"ramdisk_addr_r=0x88300000\0" \
BOOTENV
-
-#define CONFIG_PREBOOT \
- "setenv fdt_addr ${fdtcontroladdr};" \
- "fdt addr ${fdtcontroladdr};"
+#endif
#endif /* __CONFIG_H */
diff --git a/include/configs/qemu-x86.h b/include/configs/qemu-x86.h
index 64e7a60..c557420 100644
--- a/include/configs/qemu-x86.h
+++ b/include/configs/qemu-x86.h
@@ -10,8 +10,23 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+#include <linux/sizes.h>
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(USB, usb, 0) \
+ func(SCSI, scsi, 0) \
+ func(VIRTIO, virtio, 0) \
+ func(IDE, ide, 0) \
+ func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
#include <configs/x86-common.h>
+#undef CONFIG_ENV_SIZE
+#define CONFIG_ENV_SIZE SZ_256K
+
+#define CONFIG_PREBOOT "pci enum"
+
#define CONFIG_SYS_MONITOR_LEN (1 << 20)
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd\0" \
diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h
index e10de1b..0b16fb0 100644
--- a/include/configs/r2dplus.h
+++ b/include/configs/r2dplus.h
@@ -64,19 +64,6 @@
/*
* SuperH PCI Bridge Configration
*/
-#define CONFIG_SH4_PCI
#define CONFIG_SH7751_PCI
-#define CONFIG_PCI_SCAN_SHOW 1
-#define __mem_pci
-
-#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
-#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
-#define CONFIG_PCI_IO_BUS 0xFE240000 /* IO space base address */
-#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE 0x00040000 /* Size of IO window */
-#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
#endif /* __CONFIG_H */
diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h
index 7f72ff2..71a5909 100644
--- a/include/configs/rcar-gen2-common.h
+++ b/include/configs/rcar-gen2-common.h
@@ -18,10 +18,6 @@
#define CONFIG_SPL_TARGET "spl/u-boot-spl.srec"
#endif
-#undef CONFIG_SHOW_BOOT_PROGRESS
-
-#define CONFIG_ARCH_CPU_INIT
-
#ifndef CONFIG_PINCTRL_PFC
#define CONFIG_SH_GPIO_PFC
#endif
diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h
index 203b0a7..95bd97c 100644
--- a/include/configs/rcar-gen3-common.h
+++ b/include/configs/rcar-gen3-common.h
@@ -23,10 +23,6 @@
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
-#undef CONFIG_SHOW_BOOT_PROGRESS
-
-#define CONFIG_ARCH_CPU_INIT
-
/* Generic Interrupt Controller Definitions */
#define CONFIG_GICV2
#define GICD_BASE 0xF1010000
diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h
index f5d09d1..7f148ef 100644
--- a/include/configs/rk3036_common.h
+++ b/include/configs/rk3036_common.h
@@ -8,13 +8,13 @@
#include <asm/arch-rockchip/hardware.h>
#include "rockchip-common.h"
-#define CONFIG_SYS_MALLOC_LEN (32 << 20)
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000)
-#define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */
-#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
+#define CONFIG_ROCKCHIP_STIMER_BASE 0x200440a0
+#define COUNTER_FREQUENCY 24000000
+#define CONFIG_SYS_ARCH_TIMER
+#define CONFIG_SYS_HZ_CLOCK 24000000
#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
#define CONFIG_SYS_LOAD_ADDR 0x60800800
@@ -27,15 +27,8 @@
#define SDRAM_BANK_SIZE (512UL << 20UL)
#define SDRAM_MAX_SIZE (CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE)
-#define CONFIG_SPI_FLASH_GIGADEVICE
-
#ifndef CONFIG_SPL_BUILD
-/* usb otg */
-/* usb mass storage */
-#define CONFIG_CMD_USB_MASS_STORAGE
-
-/* usb host */
#define ENV_MEM_LAYOUT_SETTINGS \
"scriptaddr=0x60000000\0" \
"pxefile_addr_r=0x60100000\0" \
@@ -55,6 +48,4 @@
BOOTENV
#endif
-#define CONFIG_PREBOOT
-
#endif
diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h
index 0c08d7a..d0c9e5c 100644
--- a/include/configs/rk3128_common.h
+++ b/include/configs/rk3128_common.h
@@ -10,13 +10,15 @@
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_MALLOC_LEN (32 << 20)
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000)
-#define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */
-#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
+#define CONFIG_ROCKCHIP_STIMER_BASE 0x200440a0
+#define COUNTER_FREQUENCY 24000000
+#define CONFIG_SYS_ARCH_TIMER
+#define CONFIG_SYS_HZ_CLOCK 24000000
+
+#define CONFIG_IRAM_BASE 0x10080000
#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
#define CONFIG_SYS_LOAD_ADDR 0x60800800
@@ -24,7 +26,6 @@
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
/* RAW SD card / eMMC locations. */
-#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10)
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SYS_SDRAM_BASE 0x60000000
diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h
index 1d41702..3bcc048 100644
--- a/include/configs/rk3188_common.h
+++ b/include/configs/rk3188_common.h
@@ -12,11 +12,8 @@
#include "rockchip-common.h"
#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
-#define CONFIG_SYS_MALLOC_LEN (32 << 20)
#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_SYS_NS16550_MEM32
-
#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
/* Bootrom will load u-boot binary to 0x60000000 once return from SPL */
#endif
@@ -25,6 +22,7 @@
#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (0x8000 - 0x800)
#define CONFIG_ROCKCHIP_CHIP_TAG "RK31"
+#define CONFIG_IRAM_BASE 0x10080000
/* spl size 32kb sram - 2kb bootrom */
#define CONFIG_SPL_MAX_SIZE (0x8000 - 0x800)
@@ -62,6 +60,4 @@
#endif /* CONFIG_SPL_BUILD */
-#define CONFIG_PREBOOT
-
#endif
diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h
index 15bb8d6..7e0c831 100644
--- a/include/configs/rk322x_common.h
+++ b/include/configs/rk322x_common.h
@@ -9,13 +9,13 @@
#include "rockchip-common.h"
#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SYS_MALLOC_LEN (32 << 20)
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
-#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000)
-#define CONFIG_SYS_TIMER_BASE 0x110c00a0 /* TIMER5 */
-#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
+#define CONFIG_ROCKCHIP_STIMER_BASE 0x110d0020
+#define COUNTER_FREQUENCY 24000000
+#define CONFIG_SYS_ARCH_TIMER
+#define CONFIG_SYS_HZ_CLOCK 24000000
#define CONFIG_SYS_INIT_SP_ADDR 0x61100000
#define CONFIG_SYS_LOAD_ADDR 0x61800800
@@ -23,18 +23,14 @@
#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (28 << 10)
#define CONFIG_ROCKCHIP_CHIP_TAG "RK32"
+#define CONFIG_IRAM_BASE 0x10080000
#define CONFIG_SYS_SDRAM_BASE 0x60000000
#define SDRAM_BANK_SIZE (512UL << 20UL)
#define SDRAM_MAX_SIZE 0x80000000
#ifndef CONFIG_SPL_BUILD
-/* usb otg */
-/* usb mass storage */
-#define CONFIG_CMD_USB_MASS_STORAGE
-
-/* usb host */
#define ENV_MEM_LAYOUT_SETTINGS \
"scriptaddr=0x60000000\0" \
"pxefile_addr_r=0x60100000\0" \
@@ -54,6 +50,4 @@
BOOTENV
#endif
-#define CONFIG_PREBOOT
-
#endif
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 7c79ed6..910fe58 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -9,13 +9,15 @@
#include <asm/arch-rockchip/hardware.h>
#include "rockchip-common.h"
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64MB */
+
#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
-#define CONFIG_SYS_MALLOC_LEN (32 << 20)
#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000)
-#define CONFIG_SYS_TIMER_BASE 0xff810020 /* TIMER7 */
-#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
+#define CONFIG_ROCKCHIP_STIMER_BASE 0xff810020
+#define COUNTER_FREQUENCY 24000000
+#define CONFIG_SYS_ARCH_TIMER
+#define CONFIG_SYS_HZ_CLOCK 24000000
#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
/* Bootrom will load u-boot binary to 0x0 once return from SPL */
@@ -24,8 +26,9 @@
#define CONFIG_SYS_LOAD_ADDR 0x00800800
#define CONFIG_SPL_STACK 0xff718000
+#define CONFIG_IRAM_BASE 0xff700000
+
/* RAW SD card / eMMC locations. */
-#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10)
/* FAT sd card locations. */
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
@@ -35,13 +38,10 @@
#define SDRAM_BANK_SIZE (2UL << 30)
#define SDRAM_MAX_SIZE 0xfe000000
+#define CONFIG_SYS_MONITOR_LEN (600 * 1024)
+
#ifndef CONFIG_SPL_BUILD
-/* usb otg */
-/* usb mass storage */
-#define CONFIG_CMD_USB_MASS_STORAGE
-
-/* usb host support */
#define ENV_MEM_LAYOUT_SETTINGS \
"scriptaddr=0x00000000\0" \
"pxefile_addr_r=0x00100000\0" \
@@ -63,6 +63,4 @@
BOOTENV
#endif
-#define CONFIG_PREBOOT
-
#endif
diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h
index 2a81c80..3ff3331 100644
--- a/include/configs/rk3328_common.h
+++ b/include/configs/rk3328_common.h
@@ -8,12 +8,13 @@
#include "rockchip-common.h"
-#define CONFIG_SYS_MALLOC_LEN (32 << 20)
+#define CONFIG_IRAM_BASE 0xff090000
+
+#define CONFIG_ROCKCHIP_STIMER_BASE 0xff1d0020
+
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SYS_NS16550_MEM32
-
#define CONFIG_SYS_INIT_SP_ADDR 0x00300000
#define CONFIG_SYS_LOAD_ADDR 0x00800800
#define CONFIG_SPL_STACK 0x00400000
@@ -23,8 +24,6 @@
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
-#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10)
-
/* FAT sd card locations. */
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SYS_SDRAM_BASE 0
diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h
index 13630ba..e4b2114 100644
--- a/include/configs/rk3368_common.h
+++ b/include/configs/rk3368_common.h
@@ -16,13 +16,13 @@
#define CONFIG_SYS_SDRAM_BASE 0
#define SDRAM_MAX_SIZE 0xff000000
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_MALLOC_LEN (32 << 20)
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SKIP_LOWLEVEL_INIT
-#define COUNTER_FREQUENCY 24000000
+#define CONFIG_ROCKCHIP_STIMER_BASE 0xff830020
+#define COUNTER_FREQUENCY 24000000
-#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_IRAM_BASE 0xff8c0000
#define CONFIG_SYS_INIT_SP_ADDR 0x00300000
#define CONFIG_SYS_LOAD_ADDR 0x00280000
diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index c9cc092..9615ea7 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -8,13 +8,13 @@
#include "rockchip-common.h"
-#define CONFIG_SYS_MALLOC_LEN (32 << 20)
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SKIP_LOWLEVEL_INIT
#define COUNTER_FREQUENCY 24000000
+#define CONFIG_ROCKCHIP_STIMER_BASE 0xff8680a0
-#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_IRAM_BASE 0xff8c0000
#define CONFIG_SYS_INIT_SP_ADDR 0x00300000
#define CONFIG_SYS_LOAD_ADDR 0x00800800
@@ -38,7 +38,6 @@
#define CONFIG_ROCKCHIP_SDHCI_MAX_FREQ 200000000
/* RAW SD card / eMMC locations. */
-#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10)
/* FAT sd card locations. */
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
diff --git a/include/configs/rpi.h b/include/configs/rpi.h
index f76c7d1..77d2d54 100644
--- a/include/configs/rpi.h
+++ b/include/configs/rpi.h
@@ -14,7 +14,6 @@
#endif
/* Architecture, CPU, etc.*/
-#define CONFIG_ARCH_CPU_INIT
/* Use SoC timer for AArch32, but architected timer for AArch64 */
#ifndef CONFIG_ARM64
@@ -56,6 +55,10 @@
#define CONFIG_SYS_MEMTEST_END 0x00200000
#define CONFIG_LOADADDR 0x00200000
+#ifdef CONFIG_ARM64
+#define CONFIG_SYS_BOOTM_LEN SZ_64M
+#endif
+
/* Devices */
/* GPIO */
#define CONFIG_BCM2835_GPIO
@@ -73,7 +76,6 @@
/* Environment */
#define CONFIG_ENV_SIZE SZ_16K
#define CONFIG_SYS_LOAD_ADDR 0x1000000
-#define CONFIG_PREBOOT "usb start"
/* Shell */
diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h
index 6f61f01..758e85e 100644
--- a/include/configs/rv1108_common.h
+++ b/include/configs/rv1108_common.h
@@ -8,7 +8,8 @@
#include <asm/arch-rockchip/hardware.h>
#include "rockchip-common.h"
-#define CONFIG_SYS_MALLOC_LEN (32 << 20)
+#define CONFIG_IRAM_BASE 0x10080000
+
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SKIP_LOWLEVEL_INIT
diff --git a/include/configs/s32v234evb.h b/include/configs/s32v234evb.h
index 2169320..cc6d920 100644
--- a/include/configs/s32v234evb.h
+++ b/include/configs/s32v234evb.h
@@ -65,7 +65,6 @@
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_UART_PORT (1)
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC_BASE_ADDR
#define CONFIG_SYS_FSL_ESDHC_NUM 1
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
index ff634d9..be6f011 100644
--- a/include/configs/s5p_goni.h
+++ b/include/configs/s5p_goni.h
@@ -18,8 +18,6 @@
#include <linux/sizes.h>
#include <asm/arch/cpu.h> /* get chip and board defs */
-#define CONFIG_ARCH_CPU_INIT
-
/* input clock of PLL: has 24MHz input clock at S5PC110 */
#define CONFIG_SYS_CLK_FREQ_C110 24000000
diff --git a/include/configs/sama5d27_som1_ek.h b/include/configs/sama5d27_som1_ek.h
index 5f6979c..7343201 100644
--- a/include/configs/sama5d27_som1_ek.h
+++ b/include/configs/sama5d27_som1_ek.h
@@ -34,8 +34,6 @@
#undef CONFIG_BOOTCOMMAND
#ifdef CONFIG_SD_BOOT
-/* u-boot env in sd/mmc card */
-#define CONFIG_ENV_SIZE 0x4000
/* bootstrap + u-boot + env in sd card */
#define CONFIG_BOOTCOMMAND "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x21000000 at91-sama5d27_som1_ek.dtb; " \
"fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x22000000 zImage; " \
@@ -43,13 +41,6 @@
#endif
#ifdef CONFIG_QSPI_BOOT
-#define CONFIG_ENV_OFFSET 0xb0000
-#define CONFIG_ENV_SIZE 0x10000
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#define CONFIG_BOOTCOMMAND "sf probe 0; " \
- "sf read 0x21000000 0xc0000 0x20000; " \
- "sf read 0x22000000 0xe0000 0x400000; " \
- "bootz 0x22000000 - 0x21000000"
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTARGS \
"console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
@@ -69,8 +60,4 @@
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#endif
-#ifdef CONFIG_QSPI_BOOT
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
-#endif
-
#endif
diff --git a/include/configs/sama5d2_icp.h b/include/configs/sama5d2_icp.h
index 5c54a9c..17028ca 100644
--- a/include/configs/sama5d2_icp.h
+++ b/include/configs/sama5d2_icp.h
@@ -41,7 +41,6 @@
#define FAT_ENV_INTERFACE "mmc"
#define FAT_ENV_DEVICE_AND_PART "0"
#define FAT_ENV_FILE "uboot.env"
-#define CONFIG_ENV_SIZE 0x4000
/* bootstrap + u-boot + env in sd card */
#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 at91-sama5d2_icp.dtb; " \
"fatload mmc 0:1 0x22000000 zImage; " \
diff --git a/include/configs/sama5d2_xplained.h b/include/configs/sama5d2_xplained.h
index e522740..4873395 100644
--- a/include/configs/sama5d2_xplained.h
+++ b/include/configs/sama5d2_xplained.h
@@ -46,6 +46,17 @@
#endif
+#ifdef CONFIG_QSPI_BOOT
+#undef CONFIG_ENV_SPI_BUS
+#undef CONFIG_BOOTCOMMAND
+#define CONFIG_ENV_SPI_BUS 1
+#define CONFIG_BOOTCOMMAND "sf probe 1:0; " \
+ "sf read 0x21000000 0x180000 0x80000; " \
+ "sf read 0x22000000 0x200000 0x600000; "\
+ "bootz 0x22000000 - 0x21000000"
+
+#endif
+
/* SPL */
#define CONFIG_SPL_MAX_SIZE 0x10000
#define CONFIG_SPL_BSS_START_ADDR 0x20000000
@@ -58,10 +69,6 @@
#ifdef CONFIG_SD_BOOT
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-
-#elif CONFIG_SPI_BOOT
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
-
#endif
#endif
diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h
index db840e9..3a712b5 100644
--- a/include/configs/sama5d3xek.h
+++ b/include/configs/sama5d3xek.h
@@ -83,10 +83,6 @@
#ifdef CONFIG_SD_BOOT
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-
-#elif CONFIG_SPI_BOOT
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
-
#elif CONFIG_NAND_BOOT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h
index 5e6f59f..1773412 100644
--- a/include/configs/sama5d4_xplained.h
+++ b/include/configs/sama5d4_xplained.h
@@ -47,11 +47,6 @@
#ifdef CONFIG_SD_BOOT
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-
-#elif CONFIG_SYS_USE_NANDFLASH
-#elif CONFIG_SPI_BOOT
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
-
#elif CONFIG_NAND_BOOT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h
index c1f22f7..6cf07a1 100644
--- a/include/configs/sama5d4ek.h
+++ b/include/configs/sama5d4ek.h
@@ -47,10 +47,6 @@
#ifdef CONFIG_SD_BOOT
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-
-#elif CONFIG_SPI_BOOT
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
-
#elif CONFIG_NAND_BOOT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index 50affaf..5d75021 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -63,7 +63,11 @@
func(HOST, host, 1) \
func(HOST, host, 0)
+#ifdef __ASSEMBLY__
+#define BOOTENV
+#else
#include <config_distro_bootcmd.h>
+#endif
#define CONFIG_KEEP_SERVERADDR
#define CONFIG_UDP_CHECKSUM
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index ba61367..6aa40ca 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -48,8 +48,6 @@
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#endif
-#ifdef CONFIG_PCIE1
-#endif
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/sei510.h b/include/configs/sei510.h
new file mode 100644
index 0000000..9957902
--- /dev/null
+++ b/include/configs/sei510.h
@@ -0,0 +1,137 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration for the SEI510
+ *
+ * Copyright (C) 2019 Baylibre, SAS
+ * Author: Jerome Brunet <jbrunet@baylibre.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_MMC_ENV_DEV 2
+#define CONFIG_SYS_MMC_ENV_PART 1
+#define CONFIG_ENV_SIZE 0x10000
+#define CONFIG_ENV_OFFSET (-0x10000)
+
+#define CACHE_UUID "99207ae6-5207-11e9-999e-6f77a3612069;"
+#define SYSTEM_UUID "99f9b7ac-5207-11e9-8507-c3c037e393f3;"
+#define VENDOR_UUID "9d082802-5207-11e9-954c-cbbce08ba108;"
+#define USERDATA_UUID "9b976e42-5207-11e9-8f16-ff47ac594b22;"
+#define ROOT_UUID "ddb8c3f6-d94d-4394-b633-3134139cc2e0;"
+
+#define PARTS_DEFAULT \
+ "uuid_disk=${uuid_gpt_disk};" \
+ "name=boot,size=64M,bootable,uuid=${uuid_gpt_boot};" \
+ "name=cache,size=256M,uuid=" CACHE_UUID \
+ "name=system,size=1536M,uuid=" SYSTEM_UUID \
+ "name=vendor,size=256M,uuid=" VENDOR_UUID \
+ "name=userdata,size=4746M,uuid=" USERDATA_UUID \
+ "name=rootfs,size=-,uuid=" ROOT_UUID
+
+#define BOOTENV_DEV_FASTBOOT(devtypeu, devtypel, instance) \
+ "bootcmd_fastboot=" \
+ "sm reboot_reason reason;" \
+ "setenv run_fastboot 0;" \
+ "if gpt verify mmc ${mmcdev} ${partitions}; then; " \
+ "else " \
+ "echo Broken MMC partition scheme;" \
+ "setenv run_fastboot 1;" \
+ "fi;" \
+ "if test \"${reason}\" = \"bootloader\" -o " \
+ "\"${reason}\" = \"fastboot\"; then " \
+ "echo Fastboot asked by reboot reason;" \
+ "setenv run_fastboot 1;" \
+ "fi;" \
+ "if test \"${skip_fastboot}\" -eq 1; then " \
+ "echo Fastboot skipped by environment;" \
+ "setenv run_fastboot 0;" \
+ "fi;" \
+ "if test \"${force_fastboot}\" -eq 1; then " \
+ "echo Fastboot forced by environment;" \
+ "setenv run_fastboot 1;" \
+ "fi;" \
+ "if test \"${run_fastboot}\" -eq 1; then " \
+ "echo Running Fastboot...;" \
+ "fastboot 0;" \
+ "fi\0"
+
+#define BOOTENV_DEV_NAME_FASTBOOT(devtypeu, devtypel, instance) \
+ "fastboot "
+
+/* TOFIX: Run actual recovery instead of fastboot */
+#define BOOTENV_DEV_RECOVERY(devtypeu, devtypel, instance) \
+ "bootcmd_recovery=" \
+ "pinmux dev pinctrl@14;" \
+ "pinmux dev pinctrl@40;" \
+ "sm reboot_reason reason;" \
+ "setenv run_recovery 0;" \
+ "if run check_button; then " \
+ "echo Recovery button is pressed;" \
+ "setenv run_recovery 1;" \
+ "elif test \"${reason}\" = \"recovery\" -o " \
+ "\"${reason}\" = \"update\"; then " \
+ "echo Recovery asked by reboot reason;" \
+ "setenv run_recovery 1;" \
+ "fi;" \
+ "if test \"${skip_recovery}\" -eq 1; then " \
+ "echo Recovery skipped by environment;" \
+ "setenv run_recovery 0;" \
+ "fi;" \
+ "if test \"${force_recovery}\" -eq 1; then " \
+ "echo Recovery forced by environment;" \
+ "setenv run_recovery 1;" \
+ "fi;" \
+ "if test \"${run_recovery}\" -eq 1; then " \
+ "echo Running Recovery...;" \
+ "fastboot 0;" \
+ "fi\0"
+
+#define BOOTENV_DEV_NAME_RECOVERY(devtypeu, devtypel, instance) \
+ "recovery "
+
+#define BOOTENV_DEV_SYSTEM(devtypeu, devtypel, instance) \
+ "bootcmd_system=" \
+ "echo Loading Android boot partition...;" \
+ "mmc dev ${mmcdev};" \
+ "setenv bootargs ${bootargs} console=${console} androidboot.serialno=${serial#};" \
+ "part start mmc ${mmcdev} ${bootpart} boot_start;" \
+ "part size mmc ${mmcdev} ${bootpart} boot_size;" \
+ "if mmc read ${loadaddr} ${boot_start} ${boot_size}; then " \
+ "echo Running Android...;" \
+ "bootm ${loadaddr};" \
+ "fi;" \
+ "echo Failed to boot Android...;" \
+ "reset\0"
+
+#define BOOTENV_DEV_NAME_SYSTEM(devtypeu, devtypel, instance) \
+ "system "
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(ROMUSB, romusb, na) \
+ func(FASTBOOT, fastboot, na) \
+ func(RECOVERY, recovery, na) \
+ func(SYSTEM, system, na) \
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "partitions=" PARTS_DEFAULT "\0" \
+ "mmcdev=2\0" \
+ "bootpart=1\0" \
+ "gpio_recovery=88\0" \
+ "check_button=gpio input ${gpio_recovery};test $? -eq 0;\0" \
+ "console=/dev/ttyAML0\0" \
+ "bootargs=no_console_suspend\0" \
+ "stdin=" STDIN_CFG "\0" \
+ "stdout=" STDOUT_CFG "\0" \
+ "stderr=" STDOUT_CFG "\0" \
+ "loadaddr=0x01000000\0" \
+ "fdt_addr_r=0x01000000\0" \
+ "scriptaddr=0x08000000\0" \
+ "kernel_addr_r=0x01080000\0" \
+ "pxefile_addr_r=0x01080000\0" \
+ "ramdisk_addr_r=0x13000000\0" \
+ "fdtfile=amlogic/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" BOOTENV
+
+#include <configs/meson64.h>
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/sh7752evb.h b/include/configs/sh7752evb.h
index c90d8e0..cd7f51c 100644
--- a/include/configs/sh7752evb.h
+++ b/include/configs/sh7752evb.h
@@ -11,7 +11,6 @@
#define CONFIG_CPU_SH7752 1
#define CONFIG_DISPLAY_BOARDINFO
-#undef CONFIG_SHOW_BOOT_PROGRESS
/* MEMORY */
#define SH7752EVB_SDRAM_BASE (0x40000000)
diff --git a/include/configs/sh7753evb.h b/include/configs/sh7753evb.h
index 83d123f..6b00bd7 100644
--- a/include/configs/sh7753evb.h
+++ b/include/configs/sh7753evb.h
@@ -11,7 +11,6 @@
#define CONFIG_CPU_SH7753 1
#define CONFIG_DISPLAY_BOARDINFO
-#undef CONFIG_SHOW_BOOT_PROGRESS
/* MEMORY */
#define SH7753EVB_SDRAM_BASE (0x40000000)
diff --git a/include/configs/sh7757lcr.h b/include/configs/sh7757lcr.h
index f92f066..f1955a1 100644
--- a/include/configs/sh7757lcr.h
+++ b/include/configs/sh7757lcr.h
@@ -12,7 +12,6 @@
#define CONFIG_SH7757LCR_DDR_ECC 1
#define CONFIG_DISPLAY_BOARDINFO
-#undef CONFIG_SHOW_BOOT_PROGRESS
/* MEMORY */
#define SH7757LCR_SDRAM_BASE (0x80000000)
diff --git a/include/configs/sh7763rdp.h b/include/configs/sh7763rdp.h
index d857fcb..10961b1 100644
--- a/include/configs/sh7763rdp.h
+++ b/include/configs/sh7763rdp.h
@@ -15,7 +15,6 @@
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_DISPLAY_BOARDINFO
-#undef CONFIG_SHOW_BOOT_PROGRESS
/* SCIF */
#define CONFIG_CONS_SCIF2 1
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index 1281955..ea6cc38 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -18,7 +18,6 @@
#define CONFIG_DMA_COHERENT
#define CONFIG_DMA_COHERENT_SIZE (1 << 20)
-#define CONFIG_ENV_SIZE (0x2000)
#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024)
#ifdef CONFIG_SIEMENS_MACH_TYPE
#define CONFIG_MACH_TYPE CONFIG_SIEMENS_MACH_TYPE
@@ -95,8 +94,6 @@
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
-
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
@@ -190,7 +187,6 @@
/* UBI Support */
/* Commen environment */
-#define CONFIG_PREBOOT
#define COMMON_ENV_DFU_ARGS "dfu_args=run bootargs_defaults;" \
"setenv bootargs ${bootargs};" \
"mtdparts default;" \
@@ -461,7 +457,6 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND
devices */
#if !defined(CONFIG_SPI_BOOT)
-#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
#endif
#endif
diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h
index 7007b5f..736ceb1 100644
--- a/include/configs/sifive-fu540.h
+++ b/include/configs/sifive-fu540.h
@@ -18,14 +18,15 @@
#define CONFIG_SYS_MALLOC_LEN SZ_8M
-#define CONFIG_SYS_BOOTM_LEN SZ_16M
+#define CONFIG_SYS_BOOTM_LEN SZ_64M
#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
/* Environment options */
-#define CONFIG_ENV_SIZE SZ_4K
+#define CONFIG_ENV_SIZE SZ_128K
#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
@@ -33,11 +34,15 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0xffffffffffffffff\0" \
"initrd_high=0xffffffffffffffff\0" \
- "kernel_addr_r=0x80600000\0" \
- "fdt_addr_r=0x82200000\0" \
- "scriptaddr=0x82300000\0" \
- "pxefile_addr_r=0x82400000\0" \
- "ramdisk_addr_r=0x82500000\0" \
+ "kernel_addr_r=0x84000000\0" \
+ "fdt_addr_r=0x88000000\0" \
+ "scriptaddr=0x88100000\0" \
+ "pxefile_addr_r=0x88200000\0" \
+ "ramdisk_addr_r=0x88300000\0" \
BOOTENV
+#define CONFIG_PREBOOT \
+ "setenv fdt_addr ${fdtcontroladdr};" \
+ "fdt addr ${fdtcontroladdr};"
+
#endif /* __CONFIG_H */
diff --git a/include/configs/silk.h b/include/configs/silk.h
index c42b57a..a78da46 100644
--- a/include/configs/silk.h
+++ b/include/configs/silk.h
@@ -45,7 +45,6 @@
/* SPL support */
#define CONFIG_SPL_STACK 0xe6340000
#define CONFIG_SPL_MAX_SIZE 0x4000
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
#ifdef CONFIG_SPL_BUILD
#define CONFIG_CONS_SCIF2
#define CONFIG_SH_SCIF_CLK_FREQ 65000000
diff --git a/include/configs/slimbootloader.h b/include/configs/slimbootloader.h
new file mode 100644
index 0000000..e0011ed
--- /dev/null
+++ b/include/configs/slimbootloader.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#ifndef __SLIMBOOTLOADER_CONFIG_H__
+#define __SLIMBOOTLOADER_CONFIG_H__
+
+#include <configs/x86-common.h>
+
+/*
+ * By default, CONFIG_SYS_NS16550_PORT_MAPPED is enabled for port io serial.
+ * To use mmio base serial, enable CONFIG_SYS_NS16550_MEM32 and disable
+ * CONFIG_SYS_NS16550_PORT_MAPPED until ns16550 driver supports serial port
+ * configuration in run-time.
+ *
+ * #define CONFIG_SYS_NS16550_MEM32
+ * #undef CONFIG_SYS_NS16550_PORT_MAPPED
+ */
+#ifdef CONFIG_SYS_NS16550_MEM32
+#undef CONFIG_SYS_NS16550_PORT_MAPPED
+#endif
+
+#define CONFIG_STD_DEVICES_SETTINGS \
+ "stdin=serial,i8042-kbd,usbkbd\0" \
+ "stdout=serial\0" \
+ "stderr=serial\0"
+
+/*
+ * Override CONFIG_EXTRA_ENV_SETTINGS in x86-common.h
+ */
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_STD_DEVICES_SETTINGS \
+ "netdev=eth0\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=0x4000000\0" \
+ "ramdiskfile=initrd\0" \
+ "bootdev=usb\0" \
+ "bootdevnum=0\0" \
+ "bootdevpart=0\0" \
+ "bootfsload=fatload\0" \
+ "bootusb=setenv bootdev usb; boot\0" \
+ "bootscsi=setenv bootdev scsi; boot\0" \
+ "bootmmc=setenv bootdev mmc; boot\0" \
+ "bootargs=console=ttyS0,115200 console=tty0\0"
+
+/*
+ * Override CONFIG_BOOTCOMMAND in x86-common.h
+ */
+#undef CONFIG_BOOTCOMMAND
+#define CONFIG_BOOTCOMMAND \
+ "if test ${bootdev} = \"usb\"; then ${bootdev} start; fi; " \
+ "if test ${bootdev} = \"scsi\"; then ${bootdev} scan; fi; " \
+ "${bootdev} info; " \
+ "${bootfsload} ${bootdev} ${bootdevnum}:${bootdevpart} " \
+ "${loadaddr} ${bootfile}; " \
+ "${bootfsload} ${bootdev} ${bootdevnum}:${bootdevpart} " \
+ "${ramdiskaddr} ${ramdiskfile}; " \
+ "zboot ${loadaddr} 0 ${ramdiskaddr} ${filesize}"
+
+#endif /* __SLIMBOOTLOADER_CONFIG_H__ */
diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h
index 776d7d7..c1a43a5 100644
--- a/include/configs/smartweb.h
+++ b/include/configs/smartweb.h
@@ -144,10 +144,8 @@
/*
* The NAND Flash partitions:
*/
-#define CONFIG_ENV_OFFSET (0x100000)
#define CONFIG_ENV_OFFSET_REDUND (0x180000)
#define CONFIG_ENV_RANGE (SZ_512K)
-#define CONFIG_ENV_SIZE (SZ_128K)
/*
* Predefined environment variables.
diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h
index b934ee7..1d09792 100644
--- a/include/configs/smdkc100.h
+++ b/include/configs/smdkc100.h
@@ -21,8 +21,6 @@
#include <asm/arch/cpu.h> /* get chip and board defs */
-#define CONFIG_ARCH_CPU_INIT
-
/* input clock of PLL: SMDKC100 has 12MHz input clock */
#define CONFIG_SYS_CLK_FREQ 12000000
diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h
index f212d15..b0408a5 100644
--- a/include/configs/snapper9260.h
+++ b/include/configs/snapper9260.h
@@ -19,7 +19,6 @@
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
/* CPU */
-#define CONFIG_ARCH_CPU_INIT
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
@@ -111,8 +110,6 @@
#define CONFIG_BOOTP_BOOTFILESIZE
/* Environment settings */
-#define CONFIG_ENV_OFFSET (512 << 10)
-#define CONFIG_ENV_SIZE (256 << 10)
#define CONFIG_ENV_OVERWRITE
/* Console settings */
diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h
index dac2e65..ffcfdca 100644
--- a/include/configs/snapper9g45.h
+++ b/include/configs/snapper9g45.h
@@ -74,8 +74,6 @@
#define CONFIG_BOOTP_BOOTFILESIZE
/* Environment settings */
-#define CONFIG_ENV_OFFSET (512 << 10)
-#define CONFIG_ENV_SIZE (256 << 10)
#define CONFIG_ENV_OVERWRITE
#define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/sniper.h b/include/configs/sniper.h
index 540ea77..0e2fcc3 100644
--- a/include/configs/sniper.h
+++ b/include/configs/sniper.h
@@ -96,8 +96,6 @@
* Environment
*/
-#define CONFIG_ENV_SIZE (128 * 1024)
-
#define CONFIG_ENV_OVERWRITE
#define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index d1034ac..b11fe02 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -203,7 +203,7 @@
/* SPL SDMMC boot support */
#ifdef CONFIG_SPL_MMC_SUPPORT
#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
-#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#endif
#else
@@ -213,13 +213,6 @@
#endif
/* SPL QSPI boot support */
-#ifdef CONFIG_SPL_SPI_SUPPORT
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
-#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x100000
-#endif
-#endif
/* SPL NAND boot support */
#ifdef CONFIG_SPL_NAND_SUPPORT
diff --git a/include/configs/socfpga_dbm_soc1.h b/include/configs/socfpga_dbm_soc1.h
index b36d7e5..befaeaa 100644
--- a/include/configs/socfpga_dbm_soc1.h
+++ b/include/configs/socfpga_dbm_soc1.h
@@ -12,7 +12,6 @@
/* Booting Linux */
#define CONFIG_BOOTFILE "fitImage"
-#define CONFIG_PREBOOT "run try_bootscript"
#define CONFIG_BOOTCOMMAND "run mmc_mmc"
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
@@ -87,7 +86,8 @@
"echo Running bootscript... ; " \
"source ${kernel_addr_r} ; " \
"fi ; " \
- "fi\0"
+ "fi\0" \
+ "socfpga_legacy_reset_compat=1\0"
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
diff --git a/include/configs/socfpga_mcvevk.h b/include/configs/socfpga_mcvevk.h
index a2fc103..590a9af 100644
--- a/include/configs/socfpga_mcvevk.h
+++ b/include/configs/socfpga_mcvevk.h
@@ -12,7 +12,6 @@
/* Booting Linux */
#define CONFIG_BOOTFILE "fitImage"
-#define CONFIG_PREBOOT "run try_bootscript"
#define CONFIG_BOOTCOMMAND "run mmc_mmc"
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h
index 8d2971c..7b55dd1 100644
--- a/include/configs/socfpga_stratix10_socdk.h
+++ b/include/configs/socfpga_stratix10_socdk.h
@@ -113,7 +113,8 @@
"scriptaddr=0x02100000\0" \
"scriptfile=u-boot.scr\0" \
"fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
- "then source ${scriptaddr}; fi\0"
+ "then source ${scriptaddr}; fi\0" \
+ "socfpga_legacy_reset_compat=1\0"
/*
* Generic Interrupt Controller Definitions
@@ -200,7 +201,6 @@
#define CONFIG_SYS_SPL_MALLOC_SIZE (CONFIG_SYS_MALLOC_LEN)
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR \
- CONFIG_SYS_SPL_MALLOC_SIZE)
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x3C00000
/* SPL SDMMC boot support */
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h
index 29a92b9..232536a 100644
--- a/include/configs/socfpga_vining_fpga.h
+++ b/include/configs/socfpga_vining_fpga.h
@@ -33,16 +33,6 @@
* if button B is not pressed, boot normal Linux system immediatelly
* if button B is pressed, wait $bootdelay and boot recovery system
*/
-#define CONFIG_PREBOOT \
- "setenv hostname vining-${unit_serial} ; " \
- "setenv PS1 \"${unit_ident} (${unit_serial}) => \" ; " \
- "if gpio input 78 ; then " \
- "setenv bootdelay 10 ; " \
- "setenv boottype rcvr ; " \
- "else " \
- "setenv bootdelay 5 ; " \
- "setenv boottype norm ; " \
- "fi"
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=n\0" \
@@ -145,6 +135,7 @@
"run ubi_ubi ; " \
"else echo \"Unsupported boot mode: \"${bootmode} ; " \
"fi\0" \
+ "socfpga_legacy_reset_compat=1\0"
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 3f84fab..c7c30d3 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -187,7 +187,6 @@
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
/* I2C RTC */
-#define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */
#define CONFIG_SYS_I2C_RTC_ADDR 0x32 /* at address 0x32 */
/* I2C W83782G HW-Monitoring IC */
@@ -273,11 +272,6 @@
#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Welcome on the ABB Socrates Board;" \
- "echo"
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consdev=ttyS0\0" \
diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
index ea5996f..d21ff97 100644
--- a/include/configs/spear-common.h
+++ b/include/configs/spear-common.h
@@ -150,7 +150,6 @@
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
/* Miscellaneous configurable options */
-#define CONFIG_ARCH_CPU_INIT
#define CONFIG_BOOT_PARAMS_ADDR 0x00000100
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h
index 1d385e0..92660fe 100644
--- a/include/configs/stm32mp1.h
+++ b/include/configs/stm32mp1.h
@@ -10,11 +10,6 @@
#include <linux/sizes.h>
#include <asm/arch/stm32.h>
-/*
- * Number of clock ticks in 1 sec
- */
-#define CONFIG_SYS_HZ 1000
-
#ifndef CONFIG_STM32MP1_TRUSTED
/* PSCI support */
#define CONFIG_ARMV7_PSCI_1_0
@@ -28,6 +23,10 @@
#define CONFIG_SYS_SDRAM_BASE STM32_DDR_BASE
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
+#ifdef CONFIG_STM32MP1_OPTEE
+#define CONFIG_SYS_MEM_TOP_HIDE SZ_32M
+#endif /* CONFIG_STM32MP1_OPTEE */
+
/*
* Console I/O buffer size
*/
@@ -38,15 +37,6 @@
*/
#define CONFIG_SYS_LOAD_ADDR STM32_DDR_BASE
-#if defined(CONFIG_ENV_IS_IN_UBI)
-#define CONFIG_ENV_UBI_VOLUME_REDUND "uboot_config_r"
-#endif
-
-#if defined(CONFIG_ENV_IS_IN_SPI_FLASH)
-#define CONFIG_ENV_SECT_SIZE SZ_256K
-#define CONFIG_ENV_OFFSET 0x00280000
-#endif
-
/* ATAGs */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
@@ -57,7 +47,6 @@
/* SPL support */
#ifdef CONFIG_SPL
-/* BOOTROM load address */
/* SPL use DDR */
#define CONFIG_SPL_BSS_START_ADDR 0xC0200000
#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
@@ -77,6 +66,10 @@
/*MMC SD*/
#define CONFIG_SYS_MMC_MAX_DEVICE 3
+/* NAND support */
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+
/* Ethernet need */
#ifdef CONFIG_DWC_ETH_QOS
#define CONFIG_SYS_NONCACHED_MEMORY (1 * SZ_1M) /* 1M */
@@ -85,17 +78,20 @@
#define CONFIG_SYS_AUTOLOAD "no"
#endif
+/* Dynamic MTD partition support */
+#if defined(CONFIG_STM32_QSPI) || defined(CONFIG_NAND_STM32_FMC2)
+#define CONFIG_SYS_MTDPARTS_RUNTIME
+#endif
+
/*****************************************************************************/
#ifdef CONFIG_DISTRO_DEFAULTS
/*****************************************************************************/
#if !defined(CONFIG_SPL_BUILD)
-/* NAND support */
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 1) \
+ func(UBIFS, ubifs, 0) \
func(MMC, mmc, 0) \
func(MMC, mmc, 2) \
func(PXE, pxe, na)
@@ -112,6 +108,7 @@
"if test ${boot_device} = serial || test ${boot_device} = usb;" \
"then stm32prog ${boot_device} ${boot_instance}; " \
"else " \
+ "run env_check;" \
"if test ${boot_device} = mmc;" \
"then env set boot_targets \"mmc${boot_instance}\"; fi;" \
"if test ${boot_device} = nand;" \
@@ -121,20 +118,31 @@
#include <config_distro_bootcmd.h>
-#if defined(CONFIG_STM32_QSPI) || defined(CONFIG_NAND_STM32_FMC)
-#define CONFIG_SYS_MTDPARTS_RUNTIME
-#endif
+#ifdef CONFIG_STM32MP1_OPTEE
+/* with OPTEE: define specific MTD partitions = teeh, teed, teex */
+#define STM32MP_MTDPARTS \
+ "mtdparts_nor0=256k(fsbl1),256k(fsbl2),2m(ssbl),256k(u-boot-env),256k(teeh),256k(teed),256k(teex),-(nor_user)\0" \
+ "mtdparts_nand0=2m(fsbl),2m(ssbl1),2m(ssbl2),512k(teeh),512k(teed),512k(teex),-(UBI)\0"
+#else /* CONFIG_STM32MP1_OPTEE */
#define STM32MP_MTDPARTS \
"mtdparts_nor0=256k(fsbl1),256k(fsbl2),2m(ssbl),256k(u-boot-env),-(nor_user)\0" \
"mtdparts_nand0=2m(fsbl),2m(ssbl1),2m(ssbl2),-(UBI)\0"
+#endif /* CONFIG_STM32MP1_OPTEE */
+
+#ifndef CONFIG_SYS_MTDPARTS_RUNTIME
+#undef STM32MP_MTDPARTS
+#define STM32MP_MTDPARTS
+#endif
+
/*
* memory layout for 32M uncompressed/compressed kernel,
* 1M fdt, 1M script, 1M pxe and 1M for splashimage
* and the ramdisk at the end.
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootdelay=1\0" \
"kernel_addr_r=0xc2000000\0" \
"fdt_addr_r=0xc4000000\0" \
"scriptaddr=0xc4100000\0" \
@@ -143,9 +151,14 @@
"ramdisk_addr_r=0xc4400000\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
+ "altbootcmd=run bootcmd\0" \
+ "env_default=1\0" \
+ "env_check=if test $env_default -eq 1;"\
+ " then env set env_default 0;env save;fi\0" \
STM32MP_BOOTCMD \
STM32MP_MTDPARTS \
- BOOTENV
+ BOOTENV \
+ "boot_net_usb_start=true\0"
#endif /* ifndef CONFIG_SPL_BUILD */
#endif /* ifdef CONFIG_DISTRO_DEFAULTS*/
diff --git a/include/configs/stout.h b/include/configs/stout.h
index 4a465e0..6734595 100644
--- a/include/configs/stout.h
+++ b/include/configs/stout.h
@@ -49,7 +49,6 @@
/* SPL support */
#define CONFIG_SPL_STACK 0xe6340000
#define CONFIG_SPL_MAX_SIZE 0x4000
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
#ifdef CONFIG_SPL_BUILD
#define CONFIG_CONS_SCIFA0
#define CONFIG_SH_SCIF_CLK_FREQ 52000000
diff --git a/include/configs/strider.h b/include/configs/strider.h
index 8b942e3..e3d64e5 100644
--- a/include/configs/strider.h
+++ b/include/configs/strider.h
@@ -436,8 +436,6 @@
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_PREBOOT /* enable preboot variable */
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS1\0" \
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index fceb812..0ef289f 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -118,10 +118,6 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 8
#endif
-#ifdef CONFIG_SPL_SPI_SUNXI
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
-#endif
-
/* mmc config */
#ifdef CONFIG_MMC
#define CONFIG_MMC_SUNXI_SLOT 0
@@ -257,9 +253,6 @@
#endif
#endif /* ifdef CONFIG_REQUIRE_SERIAL_CONSOLE */
-/* GPIO */
-#define CONFIG_SUNXI_GPIO
-
#ifdef CONFIG_VIDEO_SUNXI
/*
* The amount of RAM to keep free at the top of RAM when relocating u-boot,
@@ -288,10 +281,6 @@
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
#endif
-#ifdef CONFIG_USB_KEYBOARD
-#define CONFIG_PREBOOT
-#endif
-
#ifndef CONFIG_SPL_BUILD
#ifdef CONFIG_ARM64
diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h
index e7bab72..121de2b 100644
--- a/include/configs/tam3517-common.h
+++ b/include/configs/tam3517-common.h
@@ -28,7 +28,6 @@
/*
* Size of malloc() pool
*/
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \
2 * 1024 * 1024)
/*
diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h
index a95cbed..c34e785 100644
--- a/include/configs/tao3530.h
+++ b/include/configs/tao3530.h
@@ -32,7 +32,6 @@
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (4 << 20)
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
/*
* Hardware drivers
@@ -170,7 +169,6 @@
#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10)
-#define CONFIG_ENV_OFFSET 0x260000
#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
index dbb01af..fdd1c52 100644
--- a/include/configs/taurus.h
+++ b/include/configs/taurus.h
@@ -33,7 +33,6 @@
#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */
/* Misc CPU related */
-#define CONFIG_ARCH_CPU_INIT
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
@@ -103,16 +102,13 @@
#if defined(CONFIG_SPL_BUILD)
/* SPL related */
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#endif
/* load address */
#define CONFIG_SYS_LOAD_ADDR 0x22000000
/* bootstrap in spi flash , u-boot + env + linux in nandflash */
-#define CONFIG_ENV_OFFSET 0x100000
#define CONFIG_ENV_OFFSET_REDUND 0x180000
-#define CONFIG_ENV_SIZE (SZ_128K) /* 1 sector = 128 kB */
#ifndef CONFIG_SPL_BUILD
#if defined(CONFIG_BOARD_AXM)
diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h
index a753d41..11f76e7 100644
--- a/include/configs/tbs2910.h
+++ b/include/configs/tbs2910.h
@@ -79,15 +79,6 @@
#ifdef CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_USBD_HS
#endif /* CONFIG_CMD_USB_MASS_STORAGE */
-#ifdef CONFIG_USB_KEYBOARD
-#define CONFIG_PREBOOT \
- "usb start; " \
- "if hdmidet; then " \
- "run set_con_hdmi; " \
- "else " \
- "run set_con_serial; " \
- "fi"
-#endif /* CONFIG_USB_KEYBOARD */
#endif /* CONFIG_CMD_USB */
/* Environment organization */
diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h
index 9685ee5..fae0e76 100644
--- a/include/configs/tegra-common-post.h
+++ b/include/configs/tegra-common-post.h
@@ -42,7 +42,6 @@
#ifdef CONFIG_USB_KEYBOARD
#define STDIN_KBD_USB ",usbkbd"
-#define CONFIG_PREBOOT "usb start"
#else
#define STDIN_KBD_USB ""
#endif
diff --git a/include/configs/theadorable-x86-common.h b/include/configs/theadorable-x86-common.h
index e0a033b..0c563e7 100644
--- a/include/configs/theadorable-x86-common.h
+++ b/include/configs/theadorable-x86-common.h
@@ -13,8 +13,6 @@
#define CONFIG_SYS_MONITOR_LEN (1 << 20)
-#define CONFIG_PREBOOT
-
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \
"stdout=serial\0" \
"stderr=serial\0"
diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h
index 6d41d18..45cd7e2 100644
--- a/include/configs/theadorable.h
+++ b/include/configs/theadorable.h
@@ -47,8 +47,6 @@
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-#define CONFIG_PREBOOT
-
/* Keep device tree and initrd in lower memory so the kernel can access them */
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0x10000000\0" \
@@ -108,7 +106,6 @@
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
/* SPL related SPI defines */
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x1a000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h
index 512386e..46b1b41 100644
--- a/include/configs/ti814x_evm.h
+++ b/include/configs/ti814x_evm.h
@@ -18,7 +18,6 @@
#include <asm/arch/omap.h>
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
#define CONFIG_MACH_TYPE MACH_TYPE_TI8148EVM
@@ -117,7 +116,6 @@
#define CONFIG_SYS_NS16550_COM1 0x48020000 /* Base EVM has UART0 */
/* CPU */
-#define CONFIG_ARCH_CPU_INIT
#define CONFIG_ENV_OVERWRITE
@@ -131,7 +129,6 @@
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
/*
diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h
index 0b9930e..19e1e22 100644
--- a/include/configs/ti_am335x_common.h
+++ b/include/configs/ti_am335x_common.h
@@ -11,7 +11,6 @@
#ifndef __CONFIG_TI_AM335X_COMMON_H__
#define __CONFIG_TI_AM335X_COMMON_H__
-#define CONFIG_ARCH_CPU_INIT
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index 828fb1b..2de6bc2 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -52,10 +52,16 @@
#define DEFAULT_FIT_TI_ARGS \
"boot_fit=0\0" \
- "fit_loadaddr=0x90000000\0" \
- "fit_bootfile=fitImage\0" \
- "update_to_fit=setenv loadaddr ${fit_loadaddr}; setenv bootfile ${fit_bootfile}\0" \
- "loadfit=run args_mmc; bootm ${loadaddr}#${fdtfile};\0" \
+ "addr_fit=0x90000000\0" \
+ "name_fit=fitImage\0" \
+ "update_to_fit=setenv loadaddr ${addr_fit}; setenv bootfile ${name_fit}\0" \
+ "get_overlaystring=" \
+ "for overlay in $overlay_files;" \
+ "do;" \
+ "setenv overlaystring ${overlaystring}'#'${overlay};" \
+ "done;\0" \
+ "run_fit=bootm ${loadaddr}#${fdtfile}${overlaystring}\0" \
+ "loadfit=run args_mmc; run run_fit;\0" \
/*
* DDR information. If the CONFIG_NR_DRAM_BANKS is not defined,
diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h
index b44b51b..ba12428 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -15,7 +15,6 @@
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage loader */
/* SoC Configuration */
-#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SPL_TARGET "u-boot-spi.gph"
/* Memory Configuration */
@@ -44,7 +43,6 @@
CONFIG_SYS_SPL_MALLOC_SIZE + \
SPL_MALLOC_F_SIZE + \
KEYSTONE_SPL_STACK_SIZE - 4)
-#define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO
/* SRAM scratch space entries */
#define SRAM_SCRATCH_SPACE_ADDR CONFIG_SPL_STACK + 0x8
@@ -154,7 +152,6 @@
#define CONFIG_SYS_NAND_MASK_CLE 0x4000
#define CONFIG_SYS_NAND_MASK_ALE 0x2000
#define CONFIG_SYS_NAND_CS 2
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
#define CONFIG_SYS_NAND_LARGEPAGE
@@ -175,7 +172,6 @@
DFU_ALT_INFO_MMC \
/* U-Boot general configuration */
-#define CONFIG_MX_CYCLIC
#define CONFIG_TIMESTAMP
/* EDMA3 */
@@ -221,8 +217,8 @@
"addr_secdb_key=0xc000000\0" \
"name_kern=zImage\0" \
"addr_mon=0x87000000\0" \
- "addr_non_sec_mon=0x0c087fc0\0" \
- "addr_load_sec_bm=0x0c08c000\0" \
+ "addr_non_sec_mon=0x0c097fc0\0" \
+ "addr_load_sec_bm=0x0c09c000\0" \
"run_mon=mon_install ${addr_mon}\0" \
"run_mon_hs=mon_install ${addr_non_sec_mon} " \
"${addr_load_sec_bm}\0" \
@@ -240,12 +236,10 @@
"get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \
"get_mon_nfs=nfs ${addr_mon} ${nfs_root}/boot/${name_mon}\0" \
"get_mon_ubi=ubifsload ${addr_mon} ${bootdir}/${name_mon}\0" \
- "get_fit_net=dhcp ${fit_loadaddr} ${tftp_root}" \
- "/${fit_bootfile}\0" \
- "get_fit_nfs=nfs ${fit_loadaddr} ${nfs_root}/boot/${fit_bootfile}\0"\
- "get_fit_ubi=ubifsload ${fit_loadaddr} ${bootdir}/${fit_bootfile}\0"\
- "get_fit_mmc=load mmc ${bootpart} ${fit_loadaddr} " \
- "${bootdir}/${fit_bootfile}\0" \
+ "get_fit_net=dhcp ${addr_fit} ${tftp_root}/${name_fit}\0" \
+ "get_fit_nfs=nfs ${addr_fit} ${nfs_root}/boot/${name_fit}\0" \
+ "get_fit_ubi=ubifsload ${addr_fit} ${bootdir}/${name_fit}\0" \
+ "get_fit_mmc=load mmc ${bootpart} ${addr_fit} ${bootdir}/${name_fit}\0" \
"get_uboot_net=dhcp ${loadaddr} ${tftp_root}/${name_uboot}\0" \
"get_uboot_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_uboot}\0" \
"burn_uboot_spi=sf probe; sf erase 0 0x100000; " \
@@ -261,8 +255,7 @@
"get_fdt_ramfs=dhcp ${fdtaddr} ${tftp_root}/${name_fdt}\0" \
"get_kern_ramfs=dhcp ${loadaddr} ${tftp_root}/${name_kern}\0" \
"get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \
- "get_fit_ramfs=dhcp ${fit_loadaddr} ${tftp_root}" \
- "/${fit_bootfile}\0" \
+ "get_fit_ramfs=dhcp ${addr_fit} ${tftp_root}/${name_fit}\0" \
"get_fs_ramfs=dhcp ${rdaddr} ${tftp_root}/${name_fs}\0" \
"get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi}\0" \
"get_ubi_nfs=nfs ${addr_ubi} ${nfs_root}/boot/${name_ubi}\0" \
@@ -290,7 +283,7 @@
"run run_mon_hs; " \
"run init_${boot}; " \
"run get_fit_${boot}; " \
- "bootm ${fit_loadaddr}#${name_fdt}"
+ "bootm ${addr_fit}#${name_fdt}"
#endif
#endif
diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h
index fc59aba..1e31622 100644
--- a/include/configs/ti_omap4_common.h
+++ b/include/configs/ti_omap4_common.h
@@ -24,11 +24,6 @@
#define CONFIG_SYS_TIMERBASE GPT2_BASE
/*
- * Total Size Environment - 128k
- */
-#define CONFIG_ENV_SIZE (128 << 10)
-
-/*
* For the DDR timing information we can either dynamically determine
* the timings to use or use pre-determined timings (based on using the
* dynamic method. Default to the static timing infomation.
diff --git a/include/configs/tinker_rk3288.h b/include/configs/tinker_rk3288.h
index 32057b3..5adae68 100644
--- a/include/configs/tinker_rk3288.h
+++ b/include/configs/tinker_rk3288.h
@@ -18,6 +18,5 @@
func(DHCP, dchp, na)
#define CONFIG_SYS_MMC_ENV_DEV 1
-#define CONFIG_SYS_MONITOR_LEN (600 * 1024)
#endif
diff --git a/include/configs/topic_miami.h b/include/configs/topic_miami.h
index 69aa79b..b98656d 100644
--- a/include/configs/topic_miami.h
+++ b/include/configs/topic_miami.h
@@ -22,8 +22,6 @@
/* SPL settings */
#undef CONFIG_SPL_ETH_SUPPORT
-#undef CONFIG_SYS_SPI_U_BOOT_OFFS
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#undef CONFIG_SPL_MAX_FOOTPRINT
#define CONFIG_SPL_MAX_FOOTPRINT CONFIG_SYS_SPI_U_BOOT_OFFS
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
@@ -79,8 +77,6 @@
# define EXTRA_ENV_USB
#endif
-#undef CONFIG_PREBOOT
-
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"kernel_image=uImage\0" \
diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h
index 683375a..2106f4e 100644
--- a/include/configs/tricorder.h
+++ b/include/configs/tricorder.h
@@ -78,9 +78,7 @@
/* environment placement (for NAND), is different for FLASHCARD but does not
* harm there */
-#define CONFIG_ENV_OFFSET 0x120000 /* env start */
#define CONFIG_ENV_OFFSET_REDUND 0x2A0000 /* redundant env start */
-#define CONFIG_ENV_SIZE (16 << 10) /* use 16KiB for env */
#define CONFIG_ENV_RANGE (384 << 10) /* allow badblocks in env */
/* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend
diff --git a/include/configs/turris_mox.h b/include/configs/turris_mox.h
index 0de40ed..16a49c7 100644
--- a/include/configs/turris_mox.h
+++ b/include/configs/turris_mox.h
@@ -21,7 +21,6 @@
#define CONFIG_SYS_SDRAM_BASE 0x00000000
/* auto boot */
-#define CONFIG_PREBOOT
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
115200, 230400, 460800, 921600 }
@@ -45,7 +44,6 @@
/*
* Other required minimal configurations
*/
-#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
#define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */
#define CONFIG_SYS_MEMTEST_END 0x00ffffff /*(_16M -1) */
diff --git a/include/configs/turris_omnia.h b/include/configs/turris_omnia.h
index 018f544..abe1e99 100644
--- a/include/configs/turris_omnia.h
+++ b/include/configs/turris_omnia.h
@@ -22,17 +22,12 @@
#define CONFIG_EHCI_IS_TDI
/* Environment in SPI NOR flash */
-#define CONFIG_ENV_OFFSET (3*(1 << 18)) /* 768KiB in */
#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
-#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
+#define CONFIG_ENV_OFFSET ((1 << 20) - CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB */
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-/* PCIe support */
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_PCI_SCAN_SHOW
-#endif
-
/* Keep device tree and initrd in lower memory so the kernel can access them */
#define RELOCATION_LIMITS_ENV_SETTINGS \
"fdt_high=0x10000000\0" \
@@ -55,7 +50,6 @@
#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI
/* SPL related SPI defines */
-# define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
# define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
#endif
@@ -97,8 +91,8 @@
#define BOOT_TARGET_DEVICES(func) \
BOOT_TARGET_DEVICES_MMC(func) \
- BOOT_TARGET_DEVICES_USB(func) \
BOOT_TARGET_DEVICES_SCSI(func) \
+ BOOT_TARGET_DEVICES_USB(func) \
func(PXE, pxe, na) \
func(DHCP, dhcp, na)
@@ -122,6 +116,7 @@
LOAD_ADDRESS_ENV_SETTINGS \
"fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
"console=ttyS0,115200\0" \
+ "ethact=ethernet@34000\0" \
BOOTENV
#endif /* CONFIG_SPL_BUILD */
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index 5b42e0c..68568f4 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -90,10 +90,6 @@
#define CONFIG_SYS_NAND_DATA_BASE 0x68000000
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
-/* memtest works on */
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000)
-
/*
* Network Configuration
*/
@@ -102,8 +98,7 @@
#define CONFIG_GATEWAYIP 192.168.11.1
#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_LOADADDR 0x85000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SYS_LOAD_ADDR 0x85000000
#define CONFIG_SYS_BOOTM_LEN (32 << 20)
#if defined(CONFIG_ARM64)
@@ -126,8 +121,8 @@
#ifdef CONFIG_FIT
#define CONFIG_BOOTFILE "fitImage"
+#define KERNEL_ADDR_R_OFFSET "0x05100000"
#define LINUXBOOT_ENV_SETTINGS \
- "kernel_addr_r=0x85100000\0" \
"tftpboot=tftpboot $kernel_addr_r $bootfile &&" \
"bootm $kernel_addr_r\0" \
"__nfsboot=run tftpboot\0"
@@ -135,17 +130,13 @@
#ifdef CONFIG_ARM64
#define CONFIG_BOOTFILE "Image"
#define LINUXBOOT_CMD "booti"
-#define KERNEL_ADDR_R "kernel_addr_r=0x82080000\0"
+#define KERNEL_ADDR_R_OFFSET "0x02080000"
#else
#define CONFIG_BOOTFILE "zImage"
#define LINUXBOOT_CMD "bootz"
-#define KERNEL_ADDR_R "kernel_addr_r=0x80208000\0"
+#define KERNEL_ADDR_R_OFFSET "0x00208000"
#endif
#define LINUXBOOT_ENV_SETTINGS \
- "fdt_addr_r=0x85100000\0" \
- KERNEL_ADDR_R \
- "ramdisk_addr_r=0x86000000\0" \
- "ramdisk_file=rootfs.cpio.gz\0" \
"boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 && " \
LINUXBOOT_CMD " $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
"tftpboot=tftpboot $kernel_addr_r $bootfile && " \
@@ -160,8 +151,13 @@
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_addr_r_offset=0x05100000\0" \
+ "kernel_addr_r_offset=" KERNEL_ADDR_R_OFFSET "\0" \
+ "ramdisk_addr_r_offset=0x06000000\0" \
+ "ramdisk_file=rootfs.cpio.gz\0" \
"netdev=eth0\0" \
"initrd_high=0xffffffffffffffff\0" \
+ "loadaddr_offset=0x05000000\0" \
"script=boot.scr\0" \
"scriptaddr=0x85000000\0" \
"nor_base=0x42000000\0" \
@@ -215,15 +211,9 @@
#define CONFIG_SYS_BOOTMAPSZ 0x20000000
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
-
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE)
/* only for SPL */
-#if defined(CONFIG_ARCH_UNIPHIER_LD4) || \
- defined(CONFIG_ARCH_UNIPHIER_SLD8)
-#endif
-
#define CONFIG_SPL_STACK (0x00200000)
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h
index fa38274..c0ba647 100644
--- a/include/configs/usb_a9263.h
+++ b/include/configs/usb_a9263.h
@@ -22,8 +22,6 @@
#define CONFIG_MACH_TYPE MACH_TYPE_USB_A9263
-#define CONFIG_ARCH_CPU_INIT
-
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
@@ -79,9 +77,6 @@
#define CONFIG_SYS_MEMTEST_END 0x23e00000
/* bootstrap + u-boot + env + linux in dataflash on CS0 */
-#define CONFIG_ENV_OFFSET 0x2000
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
#define CONFIG_BOOTCOMMAND "nboot 21000000 0"
#define CONFIG_EXTRA_ENV_SETTINGS \
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h
index 2354f4e..b2c14f9 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -11,14 +11,12 @@
#ifndef CONFIG_SEMIHOSTING
#error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING
#endif
-#define CONFIG_ARMV8_SWITCH_TO_EL1
#endif
#define CONFIG_REMAKE_ELF
/* Link Definitions */
-#if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \
- defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM)
+#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
/* ATF loads u-boot here for BASE_FVP model */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
#elif CONFIG_TARGET_VEXPRESS64_JUNO
@@ -84,8 +82,7 @@
#define GICR_BASE (0x2f100000)
#else
-#if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \
- defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM)
+#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
#define GICD_BASE (0x2f000000)
#define GICC_BASE (0x2c000000)
#elif CONFIG_TARGET_VEXPRESS64_JUNO
@@ -110,8 +107,6 @@
#define CONFIG_PL011_CLOCK 24000000
#endif
-/*#define CONFIG_MENU_SHOW*/
-
/* BOOTP options */
#define CONFIG_BOOTP_BOOTFILESIZE
@@ -194,17 +189,6 @@
"booti $kernel_addr - $fdt_addr"
-#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "kernel_addr=0x80080000\0" \
- "initrd_addr=0x84000000\0" \
- "fdt_addr=0x83000000\0" \
- "fdt_high=0xffffffffffffffff\0" \
- "initrd_high=0xffffffffffffffff\0"
-
-#define CONFIG_BOOTCOMMAND "booti $kernel_addr $initrd_addr $fdt_addr"
-
-
#endif
/* Monitor Command Prompt */
diff --git a/include/configs/veyron.h b/include/configs/veyron.h
index 0761de3..2ab6d6c 100644
--- a/include/configs/veyron.h
+++ b/include/configs/veyron.h
@@ -13,8 +13,6 @@
#include <configs/rk3288_common.h>
-#define CONFIG_SPI_FLASH_GIGADEVICE
-
#define CONFIG_KEYBOARD
#endif
diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h
index d4db9b4..33f06c0 100644
--- a/include/configs/vining_2000.h
+++ b/include/configs/vining_2000.h
@@ -83,7 +83,6 @@
#define CONFIG_IMX_THERMAL
-#define CONFIG_PWM_IMX
#define CONFIG_IMX6_PWM_PER_CLK 66000000
#define CONFIG_ENV_OFFSET (8 * SZ_64K)
diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h
index 1c3430d..a4f2af4 100644
--- a/include/configs/vme8349.h
+++ b/include/configs/vme8349.h
@@ -225,7 +225,6 @@
*/
#define CONFIG_SYS_RTC_BUS_NUM 0x01
#define CONFIG_SYS_I2C_RTC_ADDR 0x32
-#define CONFIG_RTC_RX8025
/* Pass Ethernet MAC to VxWorks */
#define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0
diff --git a/include/configs/vyasa-rk3288.h b/include/configs/vyasa-rk3288.h
index 382fdac..3574a3b 100644
--- a/include/configs/vyasa-rk3288.h
+++ b/include/configs/vyasa-rk3288.h
@@ -17,7 +17,6 @@
func(MMC, mmc, 1) \
#define CONFIG_SYS_MMC_ENV_DEV 1
-#undef CONFIG_CMD_USB_MASS_STORAGE
#ifndef CONFIG_TPL_BUILD
diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
index bdcd5e9..8faf5f0 100644
--- a/include/configs/wandboard.h
+++ b/include/configs/wandboard.h
@@ -61,6 +61,7 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=ttymxc0\0" \
"splashpos=m,m\0" \
+ "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \
"fdtfile=undefined\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
diff --git a/include/configs/warp7.h b/include/configs/warp7.h
index 8ceaa0c..73541fe 100644
--- a/include/configs/warp7.h
+++ b/include/configs/warp7.h
@@ -27,10 +27,23 @@
#define CONFIG_DFU_ENV_SETTINGS \
"dfu_alt_info=boot raw 0x2 0x1000 mmcpart 1\0" \
+/* When booting with FIT specify the node entry containing boot.scr */
+#if defined(CONFIG_FIT)
+#define BOOT_SCR_STRING "source ${bootscriptaddr}:${bootscr_fitimage_name}\0"
+#else
+#define BOOT_SCR_STRING "source ${bootscriptaddr}\0"
+#endif
+
+#ifndef CONFIG_OPTEE_LOAD_ADDR
+#define CONFIG_OPTEE_LOAD_ADDR 0
+#endif
+
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_DFU_ENV_SETTINGS \
"script=boot.scr\0" \
+ "bootscr_fitimage_name=bootscr\0" \
"script_signed=boot.scr.imx-signed\0" \
+ "bootscriptaddr=0x83200000\0" \
"image=zImage\0" \
"console=ttymxc0\0" \
"ethact=usb_ether\0" \
@@ -38,6 +51,7 @@
"initrd_high=0xffffffff\0" \
"fdt_file=imx7s-warp.dtb\0" \
"fdt_addr=" __stringify(CONFIG_SYS_FDT_ADDR)"\0" \
+ "fdtovaddr=0x83100000\0" \
"optee_addr=" __stringify(CONFIG_OPTEE_LOAD_ADDR)"\0" \
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
@@ -51,16 +65,16 @@
"warp7_auth_or_fail=hab_auth_img_or_fail ${hab_ivt_addr} ${filesize} 0;\0" \
"do_bootscript_hab=" \
"if test ${hab_enabled} -eq 1; then " \
- "setexpr hab_ivt_addr ${loadaddr} - ${ivt_offset}; " \
+ "setexpr hab_ivt_addr ${bootscriptaddr} - ${ivt_offset}; " \
"setenv script ${script_signed}; " \
"load mmc ${mmcdev}:${mmcpart} ${hab_ivt_addr} ${script}; " \
"run warp7_auth_or_fail; " \
"run bootscript; "\
"fi;\0" \
"loadbootscript=" \
- "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "load mmc ${mmcdev}:${mmcpart} ${bootscriptaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
- "source\0" \
+ BOOT_SCR_STRING \
"loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
"mmcboot=echo Booting from mmc ...; " \
diff --git a/include/configs/wb50n.h b/include/configs/wb50n.h
index e3973d0..6e471f6 100644
--- a/include/configs/wb50n.h
+++ b/include/configs/wb50n.h
@@ -12,8 +12,6 @@
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
-#define CONFIG_ARCH_CPU_INIT
-
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
@@ -74,9 +72,7 @@
"autostart=no\0"
/* bootstrap + u-boot + env in nandflash */
-#define CONFIG_ENV_OFFSET 0xA0000
#define CONFIG_ENV_OFFSET_REDUND 0xC0000
-#define CONFIG_ENV_SIZE 0x20000
#define CONFIG_BOOTCOMMAND \
"nand read 0x22000000 0x000e0000 0x500000; " \
"bootm"
diff --git a/include/configs/x530.h b/include/configs/x530.h
index 80ae15b..2269d1e 100644
--- a/include/configs/x530.h
+++ b/include/configs/x530.h
@@ -39,7 +39,6 @@
/* NAND */
#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define BBT_CUSTOM_SCAN
@@ -74,7 +73,6 @@
#endif
/* NAND */
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
@@ -89,7 +87,6 @@
/*
* Other required minimal configurations
*/
-#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
#define CONFIG_SYS_ALT_MEMTEST
@@ -120,8 +117,6 @@
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
/* SPL related SPI defines */
-#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
#endif /* _CONFIG_X530_H */
diff --git a/include/configs/x600.h b/include/configs/x600.h
index c893752..d4bbdcd 100644
--- a/include/configs/x600.h
+++ b/include/configs/x600.h
@@ -96,11 +96,9 @@
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
/* Miscellaneous configurable options */
-#define CONFIG_ARCH_CPU_INIT
#define CONFIG_BOOT_PARAMS_ADDR 0x00000100
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */
#define CONFIG_SYS_MEMTEST_START 0x00800000
#define CONFIG_SYS_MEMTEST_END 0x04000000
diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
index 7fcf76a..54214f9 100644
--- a/include/configs/x86-common.h
+++ b/include/configs/x86-common.h
@@ -14,7 +14,6 @@
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_SHOW_BOOT_PROGRESS
#define CONFIG_PHYSMEM
#define CONFIG_LMB
@@ -106,30 +105,40 @@
#define CONFIG_OTHBOOTARGS "othbootargs=acpi=off\0"
#endif
+#if defined(CONFIG_DISTRO_DEFAULTS)
+#define DISTRO_BOOTENV BOOTENV
+#else
+#define DISTRO_BOOTENV
+#endif
+
#define CONFIG_EXTRA_ENV_SETTINGS \
+ DISTRO_BOOTENV \
CONFIG_STD_DEVICES_SETTINGS \
"pciconfighost=1\0" \
"netdev=eth0\0" \
"consoledev=ttyS0\0" \
CONFIG_OTHBOOTARGS \
- "ramdiskaddr=0x4000000\0" \
+ "scriptaddr=0x7000000\0" \
+ "kernel_addr_r=0x1000000\0" \
+ "ramdisk_addr_r=0x4000000\0" \
"ramdiskfile=initramfs.gz\0"
+
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
- "tftpboot $loadaddr $bootfile;" \
- "tftpboot $ramdiskaddr $ramdiskfile;" \
- "zboot $loadaddr 0 $ramdiskaddr $filesize"
+ "tftpboot $kernel_addr_r $bootfile;" \
+ "tftpboot $ramdisk_addr_r $ramdiskfile;" \
+ "zboot $kernel_addr_r 0 $ramdisk_addr_r $filesize"
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
- "tftpboot $loadaddr $bootfile;" \
- "zboot $loadaddr"
+ "tftpboot $kernel_addr_r $bootfile;" \
+ "zboot $kernel_addr_r"
#endif /* __CONFIG_H */
diff --git a/include/configs/xilinx_versal_mini.h b/include/configs/xilinx_versal_mini.h
index 4b3691b..d30a697 100644
--- a/include/configs/xilinx_versal_mini.h
+++ b/include/configs/xilinx_versal_mini.h
@@ -21,9 +21,6 @@
#undef CONFIG_ZLIB
#undef CONFIG_GZIP
#undef CONFIG_CMD_ENV
-#undef CONFIG_BOOTM_NETBSD
-#undef CONFIG_BOOTM_VXWORKS
-#undef CONFIG_BOOTM_LINUX
/* BOOTP options */
#undef CONFIG_BOOTP_BOOTFILESIZE
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 684faae..a1c55a8 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -62,7 +62,6 @@
#if defined(CONFIG_ZYNQMP_USB)
#define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x1800000
#define DFU_DEFAULT_POLL_TIMEOUT 300
-#define CONFIG_USB_CABLE_CHECK
#define CONFIG_THOR_RESET_OFF
#define DFU_ALT_INFO_RAM \
"dfu_ram_info=" \
@@ -218,8 +217,6 @@
# define CONFIG_SYS_SPI_KERNEL_OFFS 0x80000
# define CONFIG_SYS_SPI_ARGS_OFFS 0xa0000
# define CONFIG_SYS_SPI_ARGS_SIZE 0xa0000
-
-# define CONFIG_SYS_SPI_U_BOOT_OFFS 0x170000
#endif
/* u-boot is like dtb */
diff --git a/include/configs/xilinx_zynqmp_mini.h b/include/configs/xilinx_zynqmp_mini.h
index 7138851..a692289 100644
--- a/include/configs/xilinx_zynqmp_mini.h
+++ b/include/configs/xilinx_zynqmp_mini.h
@@ -24,9 +24,6 @@
#undef CONFIG_GZIP
#undef CONFIG_CMD_ENV
#undef CONFIG_SYS_INIT_SP_ADDR
-#undef CONFIG_BOOTM_NETBSD
-#undef CONFIG_BOOTM_VXWORKS
-#undef CONFIG_BOOTM_LINUX
/* BOOTP options */
#undef CONFIG_BOOTP_BOOTFILESIZE
diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h
index 1ef803b..23f0389 100644
--- a/include/configs/xpedite517x.h
+++ b/include/configs/xpedite517x.h
@@ -472,7 +472,6 @@
*/
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
-#define CONFIG_PREBOOT /* enable preboot variable */
#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
/*
diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h
index 5737cfe..21e91ee 100644
--- a/include/configs/xpedite520x.h
+++ b/include/configs/xpedite520x.h
@@ -271,7 +271,6 @@
*/
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
-#define CONFIG_PREBOOT /* enable preboot variable */
#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h
index 0a87f22..73e1fa3 100644
--- a/include/configs/xpedite537x.h
+++ b/include/configs/xpedite537x.h
@@ -322,7 +322,6 @@
*/
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
-#define CONFIG_PREBOOT /* enable preboot variable */
#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
/*
diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h
index 0389874..e5a41ab 100644
--- a/include/configs/xpedite550x.h
+++ b/include/configs/xpedite550x.h
@@ -320,7 +320,6 @@
*/
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
-#define CONFIG_PREBOOT /* enable preboot variable */
#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
/*
diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h
index 33255a3..2f20273 100644
--- a/include/configs/xtfpga.h
+++ b/include/configs/xtfpga.h
@@ -119,9 +119,6 @@
/* U-Boot autoboot configuration */
/*==============================*/
-#define CONFIG_MX_CYCLIC
-#define CONFIG_SHOW_BOOT_PROGRESS
-
/*=========================================*/
/* FPGA Registers (board info and control) */
diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h
index c8b6161..9d68376 100644
--- a/include/configs/zmx25.h
+++ b/include/configs/zmx25.h
@@ -98,8 +98,6 @@
#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM + (512*1024))
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM + PHYS_SDRAM_SIZE)
-#define CONFIG_PREBOOT ""
-
/*
* Size of malloc() pool
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index b51914d..ae08ebf 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -65,7 +65,6 @@
# define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x600000
# define DFU_DEFAULT_POLL_TIMEOUT 300
-# define CONFIG_USB_CABLE_CHECK
# define CONFIG_THOR_RESET_OFF
# define DFU_ALT_INFO_RAM \
"dfu_ram_info=" \
@@ -103,7 +102,6 @@
#define CONFIG_ENV_OVERWRITE
/* enable preboot to be loaded before CONFIG_BOOTDELAY */
-#define CONFIG_PREBOOT
/* Boot configuration */
#define CONFIG_SYS_LOAD_ADDR 0 /* default? */
@@ -295,7 +293,6 @@
/* qspi mode is working fine */
#ifdef CONFIG_ZYNQ_QSPI
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x100000
#define CONFIG_SYS_SPI_ARGS_OFFS 0x200000
#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000
#define CONFIG_SYS_SPI_KERNEL_OFFS (CONFIG_SYS_SPI_ARGS_OFFS + \
diff --git a/include/configs/zynq_cse.h b/include/configs/zynq_cse.h
index daf7d75..917f35b 100644
--- a/include/configs/zynq_cse.h
+++ b/include/configs/zynq_cse.h
@@ -19,8 +19,6 @@
#undef CONFIG_GZIP
#undef CONFIG_SYS_CBSIZE
-#undef CONFIG_BOOTM_VXWORKS
-#undef CONFIG_BOOTM_LINUX
#define CONFIG_SYS_CBSIZE 1024
diff --git a/include/display.h b/include/display.h
index 16f317c..6629461 100644
--- a/include/display.h
+++ b/include/display.h
@@ -80,6 +80,16 @@
*/
int (*enable)(struct udevice *dev, int panel_bpp,
const struct display_timing *timing);
+
+ /**
+ * mode_valid() - Check if mode is supported
+ *
+ * @dev: Device to enable
+ * @timing: Display timings
+ * @return true if supported, false if not
+ */
+ bool (*mode_valid)(struct udevice *dev,
+ const struct display_timing *timing);
};
#define display_get_ops(dev) ((struct dm_display_ops *)(dev)->driver->ops)
diff --git a/include/dm/fdtaddr.h b/include/dm/fdtaddr.h
index 3bc2599..57b326c 100644
--- a/include/dm/fdtaddr.h
+++ b/include/dm/fdtaddr.h
@@ -120,4 +120,22 @@
*/
fdt_addr_t devfdt_get_addr_name(struct udevice *dev, const char *name);
+/**
+ * devfdt_get_addr_size_name() - Get the reg property and its size for a device,
+ * indexed by name
+ *
+ * Returns the address and size specified in the 'reg' property of a device.
+ *
+ * @dev: Pointer to a device
+ * @name: the 'reg' property can hold a list of <addr, size> pairs, with the
+ * 'reg-names' property providing named-based identification. @index
+ * indicates the value to search for in 'reg-names'.
+ * @size: Pointer to size variable - this function returns the size
+ * specified in the 'reg' property here
+ *
+ * @return addr
+ */
+fdt_addr_t devfdt_get_addr_size_name(struct udevice *dev, const char *name,
+ fdt_size_t *size);
+
#endif
diff --git a/include/dm/of_addr.h b/include/dm/of_addr.h
index 12b1a99..3fa1ffc 100644
--- a/include/dm/of_addr.h
+++ b/include/dm/of_addr.h
@@ -27,6 +27,24 @@
u64 of_translate_address(const struct device_node *no, const __be32 *in_addr);
/**
+ * of_translate_dma_address() - translate a device-tree DMA address to a CPU
+ * address
+ *
+ * Translate a DMA address from the device-tree into a CPU physical address,
+ * this walks up the tree and applies the various bus mappings on the way.
+ *
+ * Note: We consider that crossing any level with #size-cells == 0 to mean
+ * that translation is impossible (that is we are not dealing with a value
+ * that can be mapped to a cpu physical address). This is not really specified
+ * that way, but this is traditionally the way IBM at least do things
+ *
+ * @np: node to check
+ * @in_addr: pointer to input DMA address
+ * @return translated DMA address or OF_BAD_ADDR on error
+ */
+u64 of_translate_dma_address(const struct device_node *no, const __be32 *in_addr);
+
+/**
* of_get_address() - obtain an address from a node
*
* Extract an address from a node, returns the region size and the address
diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h
index 4ab2ae1..5c4cbf0 100644
--- a/include/dm/ofnode.h
+++ b/include/dm/ofnode.h
@@ -254,7 +254,7 @@
* @def: default value to return if the property has no value
* @return property value, or @def if not found
*/
-int ofnode_read_u64_default(ofnode node, const char *propname, u64 def);
+u64 ofnode_read_u64_default(ofnode node, const char *propname, u64 def);
/**
* ofnode_read_string() - Read a string from a property
@@ -676,12 +676,14 @@
* After relocation and jumping into the real U-Boot binary it is possible to
* determine if a node was bound in one of SPL/TPL stages.
*
- * There are 3 settings currently in use
- * -
+ * There are 4 settings currently in use
+ * - u-boot,dm-pre-proper: U-Boot proper pre-relocation only
* - u-boot,dm-pre-reloc: legacy and indicates any of TPL or SPL
* Existing platforms only use it to indicate nodes needed in
* SPL. Should probably be replaced by u-boot,dm-spl for
* new platforms.
+ * - u-boot,dm-spl: SPL and U-Boot pre-relocation
+ * - u-boot,dm-tpl: TPL and U-Boot pre-relocation
*
* @node: node to check
* @return true if node is needed in SPL/TL, false otherwise
@@ -765,7 +767,7 @@
node = ofnode_next_subnode(node))
/**
- * ofnode_translate_address() - Tranlate a device-tree address
+ * ofnode_translate_address() - Translate a device-tree address
*
* Translate an address from the device-tree into a CPU physical address. This
* function walks up the tree and applies the various bus mappings along the
@@ -779,6 +781,20 @@
u64 ofnode_translate_address(ofnode node, const fdt32_t *in_addr);
/**
+ * ofnode_translate_dma_address() - Translate a device-tree DMA address
+ *
+ * Translate a DMA address from the device-tree into a CPU physical address.
+ * This function walks up the tree and applies the various bus mappings along
+ * the way.
+ *
+ * @ofnode: Device tree node giving the context in which to translate the
+ * DMA address
+ * @in_addr: pointer to the DMA address to translate
+ * @return the translated DMA address; OF_BAD_ADDR on error
+ */
+u64 ofnode_translate_dma_address(ofnode node, const fdt32_t *in_addr);
+
+/**
* ofnode_device_is_compatible() - check if the node is compatible with compat
*
* This allows to check whether the node is comaptible with the compat.
diff --git a/include/dm/platform_data/serial_stm32.h b/include/dm/platform_data/serial_stm32.h
deleted file mode 100644
index 85153df..0000000
--- a/include/dm/platform_data/serial_stm32.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2015
- * Kamil Lulko, <kamil.lulko@gmail.com>
- */
-
-#ifndef __SERIAL_STM32_H
-#define __SERIAL_STM32_H
-
-/* Information about a serial port */
-struct stm32_serial_platdata {
- struct stm32_usart *base; /* address of registers in physical memory */
-};
-
-#endif /* __SERIAL_STM32_H */
diff --git a/include/dm/read.h b/include/dm/read.h
index 60b727c..803daf7 100644
--- a/include/dm/read.h
+++ b/include/dm/read.h
@@ -44,6 +44,7 @@
}
#ifndef CONFIG_DM_DEV_READ_INLINE
+
/**
* dev_read_u32() - read a 32-bit integer from a device's DT property
*
@@ -97,6 +98,26 @@
int dev_read_u32u(struct udevice *dev, const char *propname, uint *outp);
/**
+ * dev_read_u64() - read a 64-bit integer from a device's DT property
+ *
+ * @dev: device to read DT property from
+ * @propname: name of the property to read from
+ * @outp: place to put value (if found)
+ * @return 0 if OK, -ve on error
+ */
+int dev_read_u64(struct udevice *dev, const char *propname, u64 *outp);
+
+/**
+ * dev_read_u64_default() - read a 64-bit integer from a device's DT property
+ *
+ * @dev: device to read DT property from
+ * @propname: name of the property to read from
+ * @def: default value to return if the property has no value
+ * @return property value, or @def if not found
+ */
+u64 dev_read_u64_default(struct udevice *dev, const char *propname, u64 def);
+
+/**
* dev_read_string() - Read a string from a device's DT property
*
* @dev: device to read DT property from
@@ -145,6 +166,19 @@
fdt_addr_t dev_read_addr_index(struct udevice *dev, int index);
/**
+ * dev_read_addr_size_index() - Get the indexed reg property of a device
+ *
+ * @dev: Device to read from
+ * @index: the 'reg' property can hold a list of <addr, size> pairs
+ * and @index is used to select which one is required
+ * @size: place to put size value (on success)
+ *
+ * @return address or FDT_ADDR_T_NONE if not found
+ */
+fdt_addr_t dev_read_addr_size_index(struct udevice *dev, int index,
+ fdt_size_t *size);
+
+/**
* dev_remap_addr_index() - Get the indexed reg property of a device
* as a memory-mapped I/O pointer
*
@@ -169,6 +203,20 @@
fdt_addr_t dev_read_addr_name(struct udevice *dev, const char* name);
/**
+ * dev_read_addr_size_name() - Get the reg property of a device, indexed by name
+ *
+ * @dev: Device to read from
+ * @name: the 'reg' property can hold a list of <addr, size> pairs, with the
+ * 'reg-names' property providing named-based identification. @index
+ * indicates the value to search for in 'reg-names'.
+ * @size: place to put size value (on success)
+ *
+ * @return address or FDT_ADDR_T_NONE if not found
+ */
+fdt_addr_t dev_read_addr_size_name(struct udevice *dev, const char *name,
+ fdt_size_t *size);
+
+/**
* dev_remap_addr_name() - Get the reg property of a device, indexed by name,
* as a memory-mapped I/O pointer
*
@@ -227,7 +275,7 @@
/**
* dev_read_name() - get the name of a device's node
*
- * @node: valid node to look up
+ * @dev: Device to read from
* @return name of node
*/
const char *dev_read_name(struct udevice *dev);
@@ -499,7 +547,7 @@
struct resource *res);
/**
- * dev_translate_address() - Tranlate a device-tree address
+ * dev_translate_address() - Translate a device-tree address
*
* Translate an address from the device-tree into a CPU physical address. This
* function walks up the tree and applies the various bus mappings along the
@@ -512,6 +560,19 @@
u64 dev_translate_address(struct udevice *dev, const fdt32_t *in_addr);
/**
+ * dev_translate_dma_address() - Translate a device-tree DMA address
+ *
+ * Translate a DMA address from the device-tree into a CPU physical address.
+ * This function walks up the tree and applies the various bus mappings along
+ * the way.
+ *
+ * @dev: device giving the context in which to translate the DMA address
+ * @in_addr: pointer to the DMA address to translate
+ * @return the translated DMA address; OF_BAD_ADDR on error
+ */
+u64 dev_translate_dma_address(struct udevice *dev, const fdt32_t *in_addr);
+
+/**
* dev_read_alias_highest_id - Get highest alias id for the given stem
* @stem: Alias stem to be examined
*
@@ -561,6 +622,18 @@
return 0;
}
+static inline int dev_read_u64(struct udevice *dev,
+ const char *propname, u64 *outp)
+{
+ return ofnode_read_u64(dev_ofnode(dev), propname, outp);
+}
+
+static inline u64 dev_read_u64_default(struct udevice *dev,
+ const char *propname, u64 def)
+{
+ return ofnode_read_u64_default(dev_ofnode(dev), propname, def);
+}
+
static inline const char *dev_read_string(struct udevice *dev,
const char *propname)
{
@@ -588,12 +661,26 @@
return devfdt_get_addr_index(dev, index);
}
+static inline fdt_addr_t dev_read_addr_size_index(struct udevice *dev,
+ int index,
+ fdt_size_t *size)
+{
+ return devfdt_get_addr_size_index(dev, index, size);
+}
+
static inline fdt_addr_t dev_read_addr_name(struct udevice *dev,
const char *name)
{
return devfdt_get_addr_name(dev, name);
}
+static inline fdt_addr_t dev_read_addr_size_name(struct udevice *dev,
+ const char *name,
+ fdt_size_t *size)
+{
+ return devfdt_get_addr_size_name(dev, name, size);
+}
+
static inline fdt_addr_t dev_read_addr(struct udevice *dev)
{
return devfdt_get_addr(dev);
@@ -751,6 +838,11 @@
return ofnode_translate_address(dev_ofnode(dev), in_addr);
}
+static inline u64 dev_translate_dma_address(struct udevice *dev, const fdt32_t *in_addr)
+{
+ return ofnode_translate_dma_address(dev_ofnode(dev), in_addr);
+}
+
static inline int dev_read_alias_highest_id(const char *stem)
{
return fdtdec_get_alias_highest_id(gd->fdt_blob, stem);
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 4183928..d4d9610 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -58,6 +58,8 @@
UCLASS_LPC, /* x86 'low pin count' interface */
UCLASS_MAILBOX, /* Mailbox controller */
UCLASS_MASS_STORAGE, /* Mass storage device */
+ UCLASS_MDIO, /* MDIO bus */
+ UCLASS_MDIO_MUX, /* MDIO MUX/switch */
UCLASS_MISC, /* Miscellaneous device */
UCLASS_MMC, /* SD / MMC card or chip */
UCLASS_MOD_EXP, /* RSA Mod Exp device */
@@ -69,6 +71,7 @@
UCLASS_PANEL_BACKLIGHT, /* Backlight controller for panel */
UCLASS_PCH, /* x86 platform controller hub */
UCLASS_PCI, /* PCI bus */
+ UCLASS_PCI_EP, /* PCI endpoint device */
UCLASS_PCI_GENERIC, /* Generic PCI bus device */
UCLASS_PHY, /* Physical Layer (PHY) device */
UCLASS_PINCONFIG, /* Pin configuration node device */
diff --git a/include/dm/uclass.h b/include/dm/uclass.h
index 1bc62d5..484d166 100644
--- a/include/dm/uclass.h
+++ b/include/dm/uclass.h
@@ -297,7 +297,7 @@
*
* The device returned is probed if necessary, and ready for use
*
- * This function is useful to start iterating through a list of devices which
+ * This function is useful to iterate through a list of devices which
* are functioning correctly and can be probed.
*
* @devp: On entry, pointer to device to lookup. On exit, returns pointer
diff --git a/include/dm/util.h b/include/dm/util.h
index 60d3b93..348c2ac 100644
--- a/include/dm/util.h
+++ b/include/dm/util.h
@@ -52,12 +52,14 @@
* it is possible to determine if a node was bound in one of
* SPL/TPL stages.
*
- * There are 3 settings currently in use
- * -
+ * There are 4 settings currently in use
+ * - u-boot,dm-pre-proper: U-Boot proper pre-relocation only
* - u-boot,dm-pre-reloc: legacy and indicates any of TPL or SPL
* Existing platforms only use it to indicate nodes needed in
* SPL. Should probably be replaced by u-boot,dm-spl for
* existing platforms.
+ * - u-boot,dm-spl: SPL and U-Boot pre-relocation
+ * - u-boot,dm-tpl: TPL and U-Boot pre-relocation
* @node: of node
*
* Returns true if node is needed in SPL/TL, false otherwise.
diff --git a/include/dt-bindings/clk/sifive-fu540-prci.h b/include/dt-bindings/clk/sifive-fu540-prci.h
deleted file mode 100644
index 531523e..0000000
--- a/include/dt-bindings/clk/sifive-fu540-prci.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2019 Western Digital Corporation or its affiliates.
- *
- * Copyright (C) 2018 SiFive, Inc.
- * Wesley Terpstra
- * Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __LINUX_CLK_SIFIVE_FU540_PRCI_H
-#define __LINUX_CLK_SIFIVE_FU540_PRCI_H
-
-/* Clock indexes for use by Device Tree data */
-
-#define PRCI_CLK_COREPLL 0
-#define PRCI_CLK_DDRPLL 1
-#define PRCI_CLK_GEMGXLPLL 2
-#define PRCI_CLK_TLCLK 3
-
-#endif
diff --git a/include/dt-bindings/clock/axg-aoclkc.h b/include/dt-bindings/clock/axg-aoclkc.h
index 6195501..8ec4a26 100644
--- a/include/dt-bindings/clock/axg-aoclkc.h
+++ b/include/dt-bindings/clock/axg-aoclkc.h
@@ -21,6 +21,11 @@
#define CLKID_AO_SAR_ADC_SEL 8
#define CLKID_AO_SAR_ADC_DIV 9
#define CLKID_AO_SAR_ADC_CLK 10
-#define CLKID_AO_ALT_XTAL 11
+#define CLKID_AO_CTS_OSCIN 11
+#define CLKID_AO_32K_PRE 12
+#define CLKID_AO_32K_DIV 13
+#define CLKID_AO_32K_SEL 14
+#define CLKID_AO_32K 15
+#define CLKID_AO_CTS_RTC_OSCIN 16
#endif
diff --git a/include/dt-bindings/clock/axg-audio-clkc.h b/include/dt-bindings/clock/axg-audio-clkc.h
index fd9c362..75901c6 100644
--- a/include/dt-bindings/clock/axg-audio-clkc.h
+++ b/include/dt-bindings/clock/axg-audio-clkc.h
@@ -7,26 +7,6 @@
#ifndef __AXG_AUDIO_CLKC_BINDINGS_H
#define __AXG_AUDIO_CLKC_BINDINGS_H
-#define AUD_CLKID_SLV_SCLK0 9
-#define AUD_CLKID_SLV_SCLK1 10
-#define AUD_CLKID_SLV_SCLK2 11
-#define AUD_CLKID_SLV_SCLK3 12
-#define AUD_CLKID_SLV_SCLK4 13
-#define AUD_CLKID_SLV_SCLK5 14
-#define AUD_CLKID_SLV_SCLK6 15
-#define AUD_CLKID_SLV_SCLK7 16
-#define AUD_CLKID_SLV_SCLK8 17
-#define AUD_CLKID_SLV_SCLK9 18
-#define AUD_CLKID_SLV_LRCLK0 19
-#define AUD_CLKID_SLV_LRCLK1 20
-#define AUD_CLKID_SLV_LRCLK2 21
-#define AUD_CLKID_SLV_LRCLK3 22
-#define AUD_CLKID_SLV_LRCLK4 23
-#define AUD_CLKID_SLV_LRCLK5 24
-#define AUD_CLKID_SLV_LRCLK6 25
-#define AUD_CLKID_SLV_LRCLK7 26
-#define AUD_CLKID_SLV_LRCLK8 27
-#define AUD_CLKID_SLV_LRCLK9 28
#define AUD_CLKID_DDR_ARB 29
#define AUD_CLKID_PDM 30
#define AUD_CLKID_TDMIN_A 31
@@ -90,5 +70,15 @@
#define AUD_CLKID_TDMOUT_A_LRCLK 134
#define AUD_CLKID_TDMOUT_B_LRCLK 135
#define AUD_CLKID_TDMOUT_C_LRCLK 136
+#define AUD_CLKID_SPDIFOUT_B 151
+#define AUD_CLKID_SPDIFOUT_B_CLK 152
+#define AUD_CLKID_TDM_MCLK_PAD0 155
+#define AUD_CLKID_TDM_MCLK_PAD1 156
+#define AUD_CLKID_TDM_LRCLK_PAD0 157
+#define AUD_CLKID_TDM_LRCLK_PAD1 158
+#define AUD_CLKID_TDM_LRCLK_PAD2 159
+#define AUD_CLKID_TDM_SCLK_PAD0 160
+#define AUD_CLKID_TDM_SCLK_PAD1 161
+#define AUD_CLKID_TDM_SCLK_PAD2 162
#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */
diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h
index 82c9e0c..b6b127e 100644
--- a/include/dt-bindings/clock/g12a-clkc.h
+++ b/include/dt-bindings/clock/g12a-clkc.h
@@ -130,11 +130,12 @@
#define CLKID_MALI_1_SEL 172
#define CLKID_MALI_1 174
#define CLKID_MALI 175
-#define CLKID_MPLL_5OM 177
+#define CLKID_MPLL_50M 177
#define CLKID_CPU_CLK 187
#define CLKID_PCIE_PLL 201
#define CLKID_VDEC_1 204
#define CLKID_VDEC_HEVC 207
#define CLKID_VDEC_HEVCF 210
+#define CLKID_TS 212
#endif /* __G12A_CLKC_H */
diff --git a/include/dt-bindings/clock/hi3660-clock.h b/include/dt-bindings/clock/hi3660-clock.h
new file mode 100644
index 0000000..e1374e1
--- /dev/null
+++ b/include/dt-bindings/clock/hi3660-clock.h
@@ -0,0 +1,214 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2016-2017 Linaro Ltd.
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ */
+
+#ifndef __DTS_HI3660_CLOCK_H
+#define __DTS_HI3660_CLOCK_H
+
+/* fixed rate clocks */
+#define HI3660_CLKIN_SYS 0
+#define HI3660_CLKIN_REF 1
+#define HI3660_CLK_FLL_SRC 2
+#define HI3660_CLK_PPLL0 3
+#define HI3660_CLK_PPLL1 4
+#define HI3660_CLK_PPLL2 5
+#define HI3660_CLK_PPLL3 6
+#define HI3660_CLK_SCPLL 7
+#define HI3660_PCLK 8
+#define HI3660_CLK_UART0_DBG 9
+#define HI3660_CLK_UART6 10
+#define HI3660_OSC32K 11
+#define HI3660_OSC19M 12
+#define HI3660_CLK_480M 13
+#define HI3660_CLK_INV 14
+
+/* clk in crgctrl */
+#define HI3660_FACTOR_UART3 15
+#define HI3660_CLK_FACTOR_MMC 16
+#define HI3660_CLK_GATE_I2C0 17
+#define HI3660_CLK_GATE_I2C1 18
+#define HI3660_CLK_GATE_I2C2 19
+#define HI3660_CLK_GATE_I2C6 20
+#define HI3660_CLK_DIV_SYSBUS 21
+#define HI3660_CLK_DIV_320M 22
+#define HI3660_CLK_DIV_A53 23
+#define HI3660_CLK_GATE_SPI0 24
+#define HI3660_CLK_GATE_SPI2 25
+#define HI3660_PCIEPHY_REF 26
+#define HI3660_CLK_ABB_USB 27
+#define HI3660_HCLK_GATE_SDIO0 28
+#define HI3660_HCLK_GATE_SD 29
+#define HI3660_CLK_GATE_AOMM 30
+#define HI3660_PCLK_GPIO0 31
+#define HI3660_PCLK_GPIO1 32
+#define HI3660_PCLK_GPIO2 33
+#define HI3660_PCLK_GPIO3 34
+#define HI3660_PCLK_GPIO4 35
+#define HI3660_PCLK_GPIO5 36
+#define HI3660_PCLK_GPIO6 37
+#define HI3660_PCLK_GPIO7 38
+#define HI3660_PCLK_GPIO8 39
+#define HI3660_PCLK_GPIO9 40
+#define HI3660_PCLK_GPIO10 41
+#define HI3660_PCLK_GPIO11 42
+#define HI3660_PCLK_GPIO12 43
+#define HI3660_PCLK_GPIO13 44
+#define HI3660_PCLK_GPIO14 45
+#define HI3660_PCLK_GPIO15 46
+#define HI3660_PCLK_GPIO16 47
+#define HI3660_PCLK_GPIO17 48
+#define HI3660_PCLK_GPIO18 49
+#define HI3660_PCLK_GPIO19 50
+#define HI3660_PCLK_GPIO20 51
+#define HI3660_PCLK_GPIO21 52
+#define HI3660_CLK_GATE_SPI3 53
+#define HI3660_CLK_GATE_I2C7 54
+#define HI3660_CLK_GATE_I2C3 55
+#define HI3660_CLK_GATE_SPI1 56
+#define HI3660_CLK_GATE_UART1 57
+#define HI3660_CLK_GATE_UART2 58
+#define HI3660_CLK_GATE_UART4 59
+#define HI3660_CLK_GATE_UART5 60
+#define HI3660_CLK_GATE_I2C4 61
+#define HI3660_CLK_GATE_DMAC 62
+#define HI3660_PCLK_GATE_DSS 63
+#define HI3660_ACLK_GATE_DSS 64
+#define HI3660_CLK_GATE_LDI1 65
+#define HI3660_CLK_GATE_LDI0 66
+#define HI3660_CLK_GATE_VIVOBUS 67
+#define HI3660_CLK_GATE_EDC0 68
+#define HI3660_CLK_GATE_TXDPHY0_CFG 69
+#define HI3660_CLK_GATE_TXDPHY0_REF 70
+#define HI3660_CLK_GATE_TXDPHY1_CFG 71
+#define HI3660_CLK_GATE_TXDPHY1_REF 72
+#define HI3660_ACLK_GATE_USB3OTG 73
+#define HI3660_CLK_GATE_SPI4 74
+#define HI3660_CLK_GATE_SD 75
+#define HI3660_CLK_GATE_SDIO0 76
+#define HI3660_CLK_GATE_UFS_SUBSYS 77
+#define HI3660_PCLK_GATE_DSI0 78
+#define HI3660_PCLK_GATE_DSI1 79
+#define HI3660_ACLK_GATE_PCIE 80
+#define HI3660_PCLK_GATE_PCIE_SYS 81
+#define HI3660_CLK_GATE_PCIEAUX 82
+#define HI3660_PCLK_GATE_PCIE_PHY 83
+#define HI3660_CLK_ANDGT_LDI0 84
+#define HI3660_CLK_ANDGT_LDI1 85
+#define HI3660_CLK_ANDGT_EDC0 86
+#define HI3660_CLK_GATE_UFSPHY_GT 87
+#define HI3660_CLK_ANDGT_MMC 88
+#define HI3660_CLK_ANDGT_SD 89
+#define HI3660_CLK_A53HPM_ANDGT 90
+#define HI3660_CLK_ANDGT_SDIO 91
+#define HI3660_CLK_ANDGT_UART0 92
+#define HI3660_CLK_ANDGT_UART1 93
+#define HI3660_CLK_ANDGT_UARTH 94
+#define HI3660_CLK_ANDGT_SPI 95
+#define HI3660_CLK_VIVOBUS_ANDGT 96
+#define HI3660_CLK_AOMM_ANDGT 97
+#define HI3660_CLK_320M_PLL_GT 98
+#define HI3660_AUTODIV_EMMC0BUS 99
+#define HI3660_AUTODIV_SYSBUS 100
+#define HI3660_CLK_GATE_UFSPHY_CFG 101
+#define HI3660_CLK_GATE_UFSIO_REF 102
+#define HI3660_CLK_MUX_SYSBUS 103
+#define HI3660_CLK_MUX_UART0 104
+#define HI3660_CLK_MUX_UART1 105
+#define HI3660_CLK_MUX_UARTH 106
+#define HI3660_CLK_MUX_SPI 107
+#define HI3660_CLK_MUX_I2C 108
+#define HI3660_CLK_MUX_MMC_PLL 109
+#define HI3660_CLK_MUX_LDI1 110
+#define HI3660_CLK_MUX_LDI0 111
+#define HI3660_CLK_MUX_SD_PLL 112
+#define HI3660_CLK_MUX_SD_SYS 113
+#define HI3660_CLK_MUX_EDC0 114
+#define HI3660_CLK_MUX_SDIO_SYS 115
+#define HI3660_CLK_MUX_SDIO_PLL 116
+#define HI3660_CLK_MUX_VIVOBUS 117
+#define HI3660_CLK_MUX_A53HPM 118
+#define HI3660_CLK_MUX_320M 119
+#define HI3660_CLK_MUX_IOPERI 120
+#define HI3660_CLK_DIV_UART0 121
+#define HI3660_CLK_DIV_UART1 122
+#define HI3660_CLK_DIV_UARTH 123
+#define HI3660_CLK_DIV_MMC 124
+#define HI3660_CLK_DIV_SD 125
+#define HI3660_CLK_DIV_EDC0 126
+#define HI3660_CLK_DIV_LDI0 127
+#define HI3660_CLK_DIV_SDIO 128
+#define HI3660_CLK_DIV_LDI1 129
+#define HI3660_CLK_DIV_SPI 130
+#define HI3660_CLK_DIV_VIVOBUS 131
+#define HI3660_CLK_DIV_I2C 132
+#define HI3660_CLK_DIV_UFSPHY 133
+#define HI3660_CLK_DIV_CFGBUS 134
+#define HI3660_CLK_DIV_MMC0BUS 135
+#define HI3660_CLK_DIV_MMC1BUS 136
+#define HI3660_CLK_DIV_UFSPERI 137
+#define HI3660_CLK_DIV_AOMM 138
+#define HI3660_CLK_DIV_IOPERI 139
+#define HI3660_VENC_VOLT_HOLD 140
+#define HI3660_PERI_VOLT_HOLD 141
+#define HI3660_CLK_GATE_VENC 142
+#define HI3660_CLK_GATE_VDEC 143
+#define HI3660_CLK_ANDGT_VENC 144
+#define HI3660_CLK_ANDGT_VDEC 145
+#define HI3660_CLK_MUX_VENC 146
+#define HI3660_CLK_MUX_VDEC 147
+#define HI3660_CLK_DIV_VENC 148
+#define HI3660_CLK_DIV_VDEC 149
+#define HI3660_CLK_FAC_ISP_SNCLK 150
+#define HI3660_CLK_GATE_ISP_SNCLK0 151
+#define HI3660_CLK_GATE_ISP_SNCLK1 152
+#define HI3660_CLK_GATE_ISP_SNCLK2 153
+#define HI3660_CLK_ANGT_ISP_SNCLK 154
+#define HI3660_CLK_MUX_ISP_SNCLK 155
+#define HI3660_CLK_DIV_ISP_SNCLK 156
+
+/* clk in pmuctrl */
+#define HI3660_GATE_ABB_192 0
+
+/* clk in pctrl */
+#define HI3660_GATE_UFS_TCXO_EN 0
+#define HI3660_GATE_USB_TCXO_EN 1
+
+/* clk in sctrl */
+#define HI3660_PCLK_AO_GPIO0 0
+#define HI3660_PCLK_AO_GPIO1 1
+#define HI3660_PCLK_AO_GPIO2 2
+#define HI3660_PCLK_AO_GPIO3 3
+#define HI3660_PCLK_AO_GPIO4 4
+#define HI3660_PCLK_AO_GPIO5 5
+#define HI3660_PCLK_AO_GPIO6 6
+#define HI3660_PCLK_GATE_MMBUF 7
+#define HI3660_CLK_GATE_DSS_AXI_MM 8
+#define HI3660_PCLK_MMBUF_ANDGT 9
+#define HI3660_CLK_MMBUF_PLL_ANDGT 10
+#define HI3660_CLK_FLL_MMBUF_ANDGT 11
+#define HI3660_CLK_SYS_MMBUF_ANDGT 12
+#define HI3660_CLK_GATE_PCIEPHY_GT 13
+#define HI3660_ACLK_MUX_MMBUF 14
+#define HI3660_CLK_SW_MMBUF 15
+#define HI3660_CLK_DIV_AOBUS 16
+#define HI3660_PCLK_DIV_MMBUF 17
+#define HI3660_ACLK_DIV_MMBUF 18
+#define HI3660_CLK_DIV_PCIEPHY 19
+
+/* clk in iomcu */
+#define HI3660_CLK_I2C0_IOMCU 0
+#define HI3660_CLK_I2C1_IOMCU 1
+#define HI3660_CLK_I2C2_IOMCU 2
+#define HI3660_CLK_I2C6_IOMCU 3
+#define HI3660_CLK_IOMCU_PERI0 4
+
+/* clk in stub clock */
+#define HI3660_CLK_STUB_CLUSTER0 0
+#define HI3660_CLK_STUB_CLUSTER1 1
+#define HI3660_CLK_STUB_GPU 2
+#define HI3660_CLK_STUB_DDR 3
+#define HI3660_CLK_STUB_NUM 4
+
+#endif /* __DTS_HI3660_CLOCK_H */
diff --git a/include/dt-bindings/clock/r8a77980-cpg-mssr.h b/include/dt-bindings/clock/r8a77980-cpg-mssr.h
new file mode 100644
index 0000000..a4c0d76
--- /dev/null
+++ b/include/dt-bindings/clock/r8a77980-cpg-mssr.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a77980 CPG Core Clocks */
+#define R8A77980_CLK_Z2 0
+#define R8A77980_CLK_ZR 1
+#define R8A77980_CLK_ZTR 2
+#define R8A77980_CLK_ZTRD2 3
+#define R8A77980_CLK_ZT 4
+#define R8A77980_CLK_ZX 5
+#define R8A77980_CLK_S0D1 6
+#define R8A77980_CLK_S0D2 7
+#define R8A77980_CLK_S0D3 8
+#define R8A77980_CLK_S0D4 9
+#define R8A77980_CLK_S0D6 10
+#define R8A77980_CLK_S0D12 11
+#define R8A77980_CLK_S0D24 12
+#define R8A77980_CLK_S1D1 13
+#define R8A77980_CLK_S1D2 14
+#define R8A77980_CLK_S1D4 15
+#define R8A77980_CLK_S2D1 16
+#define R8A77980_CLK_S2D2 17
+#define R8A77980_CLK_S2D4 18
+#define R8A77980_CLK_S3D1 19
+#define R8A77980_CLK_S3D2 20
+#define R8A77980_CLK_S3D4 21
+#define R8A77980_CLK_LB 22
+#define R8A77980_CLK_CL 23
+#define R8A77980_CLK_ZB3 24
+#define R8A77980_CLK_ZB3D2 25
+#define R8A77980_CLK_ZB3D4 26
+#define R8A77980_CLK_SD0H 27
+#define R8A77980_CLK_SD0 28
+#define R8A77980_CLK_RPC 29
+#define R8A77980_CLK_RPCD2 30
+#define R8A77980_CLK_MSO 31
+#define R8A77980_CLK_CANFD 32
+#define R8A77980_CLK_CSI0 33
+#define R8A77980_CLK_CP 34
+#define R8A77980_CLK_CPEX 35
+#define R8A77980_CLK_R 36
+#define R8A77980_CLK_OSC 37
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/sifive-fu540-prci.h b/include/dt-bindings/clock/sifive-fu540-prci.h
new file mode 100644
index 0000000..6a0b70a
--- /dev/null
+++ b/include/dt-bindings/clock/sifive-fu540-prci.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018-2019 SiFive, Inc.
+ * Wesley Terpstra
+ * Paul Walmsley
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H
+#define __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H
+
+/* Clock indexes for use by Device Tree data and the PRCI driver */
+
+#define PRCI_CLK_COREPLL 0
+#define PRCI_CLK_DDRPLL 1
+#define PRCI_CLK_GEMGXLPLL 2
+#define PRCI_CLK_TLCLK 3
+
+#endif
diff --git a/include/dt-bindings/phy/phy-am654-serdes.h b/include/dt-bindings/phy/phy-am654-serdes.h
new file mode 100644
index 0000000..e8d9017
--- /dev/null
+++ b/include/dt-bindings/phy/phy-am654-serdes.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for AM654 SERDES.
+ */
+
+#ifndef _DT_BINDINGS_AM654_SERDES
+#define _DT_BINDINGS_AM654_SERDES
+
+#define AM654_SERDES_CMU_REFCLK 0
+#define AM654_SERDES_LO_REFCLK 1
+#define AM654_SERDES_RO_REFCLK 2
+
+#endif /* _DT_BINDINGS_AM654_SERDES */
diff --git a/include/dt-bindings/pinctrl/k3.h b/include/dt-bindings/pinctrl/k3.h
index a67521c..ce0cd38 100644
--- a/include/dt-bindings/pinctrl/k3.h
+++ b/include/dt-bindings/pinctrl/k3.h
@@ -35,4 +35,7 @@
#define AM65X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
#define AM65X_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
+#define J721E_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
+#define J721E_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
+
#endif
diff --git a/include/dt-bindings/pinctrl/stm32-pinfunc.h b/include/dt-bindings/pinctrl/stm32-pinfunc.h
index b5a2174..e6fb8ad 100644
--- a/include/dt-bindings/pinctrl/stm32-pinfunc.h
+++ b/include/dt-bindings/pinctrl/stm32-pinfunc.h
@@ -32,5 +32,11 @@
#define STM32_PINMUX(port, line, mode) (((PIN_NO(port, line)) << 8) | (mode))
+/* package information */
+#define STM32MP_PKG_AA 0x1
+#define STM32MP_PKG_AB 0x2
+#define STM32MP_PKG_AC 0x4
+#define STM32MP_PKG_AD 0x8
+
#endif /* _DT_BINDINGS_STM32_PINFUNC_H */
diff --git a/include/dt-bindings/power/r8a77965-sysc.h b/include/dt-bindings/power/r8a77965-sysc.h
index 05a4b59..de82d8a 100644
--- a/include/dt-bindings/power/r8a77965-sysc.h
+++ b/include/dt-bindings/power/r8a77965-sysc.h
@@ -21,7 +21,6 @@
#define R8A77965_PD_A3VC 14
#define R8A77965_PD_3DG_A 17
#define R8A77965_PD_3DG_B 18
-#define R8A77965_PD_A3IR 24
#define R8A77965_PD_A2VC1 26
/* Always-on power area */
diff --git a/include/dt-bindings/power/r8a77970-sysc.h b/include/dt-bindings/power/r8a77970-sysc.h
index bf54779..85cc5f2 100644
--- a/include/dt-bindings/power/r8a77970-sysc.h
+++ b/include/dt-bindings/power/r8a77970-sysc.h
@@ -16,13 +16,12 @@
#define R8A77970_PD_CA53_CPU0 5
#define R8A77970_PD_CA53_CPU1 6
-#define R8A77970_PD_CR7 13
#define R8A77970_PD_CA53_SCU 21
#define R8A77970_PD_A2IR0 23
-#define R8A77970_PD_A3IR 24
+#define R8A77970_PD_A3IR 24
#define R8A77970_PD_A2IR1 27
-#define R8A77970_PD_A2IR2 28
-#define R8A77970_PD_A2IR3 29
+#define R8A77970_PD_A2DP 28
+#define R8A77970_PD_A2CN 29
#define R8A77970_PD_A2SC0 30
#define R8A77970_PD_A2SC1 31
diff --git a/include/dt-bindings/power/r8a77980-sysc.h b/include/dt-bindings/power/r8a77980-sysc.h
new file mode 100644
index 0000000..e12c858
--- /dev/null
+++ b/include/dt-bindings/power/r8a77980-sysc.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A77980_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A77980_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A77980_PD_A2SC2 0
+#define R8A77980_PD_A2SC3 1
+#define R8A77980_PD_A2SC4 2
+#define R8A77980_PD_A2DP0 3
+#define R8A77980_PD_A2DP1 4
+#define R8A77980_PD_CA53_CPU0 5
+#define R8A77980_PD_CA53_CPU1 6
+#define R8A77980_PD_CA53_CPU2 7
+#define R8A77980_PD_CA53_CPU3 8
+#define R8A77980_PD_A2CN 10
+#define R8A77980_PD_A3VIP0 11
+#define R8A77980_PD_A2IR5 12
+#define R8A77980_PD_CR7 13
+#define R8A77980_PD_A2IR4 15
+#define R8A77980_PD_CA53_SCU 21
+#define R8A77980_PD_A2IR0 23
+#define R8A77980_PD_A3IR 24
+#define R8A77980_PD_A3VIP1 25
+#define R8A77980_PD_A3VIP2 26
+#define R8A77980_PD_A2IR1 27
+#define R8A77980_PD_A2IR2 28
+#define R8A77980_PD_A2IR3 29
+#define R8A77980_PD_A2SC0 30
+#define R8A77980_PD_A2SC1 31
+
+/* Always-on power area */
+#define R8A77980_PD_ALWAYS_ON 32
+
+#endif /* __DT_BINDINGS_POWER_R8A77980_SYSC_H__ */
diff --git a/include/dt-bindings/reset/mtk-reset.h b/include/dt-bindings/reset/mtk-reset.h
index 5f0a74f..78fcdab 100644
--- a/include/dt-bindings/reset/mtk-reset.h
+++ b/include/dt-bindings/reset/mtk-reset.h
@@ -15,4 +15,13 @@
#define ETHSYS_MCM_RST 2
#define ETHSYS_SYS_RST 0
+/* HIFSYS resets */
+#define HIFSYS_PCIE2_RST 26
+#define HIFSYS_PCIE1_RST 25
+#define HIFSYS_PCIE0_RST 24
+#define HIFSYS_UPHY1_RST 22
+#define HIFSYS_UPHY0_RST 21
+#define HIFSYS_UHOST1_RST 4
+#define HIFSYS_UHOST0_RST 3
+
#endif /* _DT_BINDINGS_MTK_RESET_H_ */
diff --git a/include/dt-bindings/soc/ti,sci_pm_domain.h b/include/dt-bindings/soc/ti,sci_pm_domain.h
new file mode 100644
index 0000000..8f2a736
--- /dev/null
+++ b/include/dt-bindings/soc/ti,sci_pm_domain.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __DT_BINDINGS_TI_SCI_PM_DOMAIN_H
+#define __DT_BINDINGS_TI_SCI_PM_DOMAIN_H
+
+#define TI_SCI_PD_EXCLUSIVE 1
+#define TI_SCI_PD_SHARED 0
+
+#endif /* __DT_BINDINGS_TI_SCI_PM_DOMAIN_H */
diff --git a/include/dt-bindings/sound/meson-g12a-tohdmitx.h b/include/dt-bindings/sound/meson-g12a-tohdmitx.h
new file mode 100644
index 0000000..c5e1f48
--- /dev/null
+++ b/include/dt-bindings/sound/meson-g12a-tohdmitx.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DT_MESON_G12A_TOHDMITX_H
+#define __DT_MESON_G12A_TOHDMITX_H
+
+#define TOHDMITX_I2S_IN_A 0
+#define TOHDMITX_I2S_IN_B 1
+#define TOHDMITX_I2S_IN_C 2
+#define TOHDMITX_I2S_OUT 3
+#define TOHDMITX_SPDIF_IN_A 4
+#define TOHDMITX_SPDIF_IN_B 5
+#define TOHDMITX_SPDIF_OUT 6
+
+#endif /* __DT_MESON_G12A_TOHDMITX_H */
diff --git a/include/dw_hdmi.h b/include/dw_hdmi.h
index 90fb64b..8acae38 100644
--- a/include/dw_hdmi.h
+++ b/include/dw_hdmi.h
@@ -542,6 +542,7 @@
u8 i2c_clk_low;
u8 reg_io_width;
struct hdmi_data_info hdmi_data;
+ struct udevice *ddc_bus;
int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock);
void (*write_reg)(struct dw_hdmi *hdmi, u8 val, int offset);
diff --git a/include/edid.h b/include/edid.h
index f05d2b8..2562733 100644
--- a/include/edid.h
+++ b/include/edid.h
@@ -307,6 +307,28 @@
struct display_timing;
/**
+ * edid_get_timing_validate() - Get basic digital display parameters with
+ * mode selection callback
+ *
+ * @param buf Buffer containing EDID data
+ * @param buf_size Size of buffer in bytes
+ * @param timing Place to put preferring timing information
+ * @param panel_bits_per_colourp Place to put the number of bits per
+ * colour supported by the panel. This will be set to
+ * -1 if not available
+ * @param mode_valid Callback validating mode, returning true is mode is
+ * supported, false otherwise.
+ * @parem valid_priv Pointer to private data for mode_valid callback
+ * @return 0 if timings are OK, -ve on error
+ */
+int edid_get_timing_validate(u8 *buf, int buf_size,
+ struct display_timing *timing,
+ int *panel_bits_per_colourp,
+ bool (*mode_valid)(void *priv,
+ const struct display_timing *timing),
+ void *mode_valid_priv);
+
+/**
* edid_get_timing() - Get basic digital display parameters
*
* @param buf Buffer containing EDID data
diff --git a/include/efi_api.h b/include/efi_api.h
index a36ecec..37e56da 100644
--- a/include/efi_api.h
+++ b/include/efi_api.h
@@ -23,8 +23,8 @@
#include <asm/setjmp.h>
#endif
-/* UEFI spec version 2.7 */
-#define EFI_SPECIFICATION_VERSION (2 << 16 | 70)
+/* UEFI spec version 2.8 */
+#define EFI_SPECIFICATION_VERSION (2 << 16 | 80)
/* Types and defines for EFI CreateEvent */
enum efi_timer_delay {
@@ -238,8 +238,8 @@
efi_status_t (EFIAPI *set_wakeup_time)(char enabled,
struct efi_time *time);
efi_status_t (EFIAPI *set_virtual_address_map)(
- unsigned long memory_map_size,
- unsigned long descriptor_size,
+ efi_uintn_t memory_map_size,
+ efi_uintn_t descriptor_size,
uint32_t descriptor_version,
struct efi_mem_desc *virtmap);
efi_status_t (EFIAPI *convert_pointer)(
@@ -483,7 +483,7 @@
struct efi_device_path dp;
u32 boot_entry;
u64 partition_start;
- u64 partition_end;
+ u64 partition_size;
} __packed;
struct efi_device_path_file_path {
@@ -1281,12 +1281,17 @@
struct efi_mac_address *dest_addr, u16 *protocol);
struct efi_event *wait_for_packet;
struct efi_simple_network_mode *mode;
+ /* private fields */
+ u32 int_status;
};
#define EFI_PXE_BASE_CODE_PROTOCOL_GUID \
EFI_GUID(0x03c4e603, 0xac28, 0x11d3, \
0x9a, 0x2d, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d)
+#define EFI_PXE_BASE_CODE_PROTOCOL_REVISION 0x00010000
+#define EFI_PXE_BASE_CODE_MAX_IPCNT 8
+
struct efi_pxe_packet {
u8 packet[1472];
};
@@ -1321,20 +1326,131 @@
struct efi_pxe_packet pxe_reply;
};
-struct efi_pxe {
- u64 rev;
- void (EFIAPI *start)(void);
- void (EFIAPI *stop)(void);
- void (EFIAPI *dhcp)(void);
- void (EFIAPI *discover)(void);
- void (EFIAPI *mftp)(void);
- void (EFIAPI *udpwrite)(void);
- void (EFIAPI *udpread)(void);
- void (EFIAPI *setipfilter)(void);
- void (EFIAPI *arp)(void);
- void (EFIAPI *setparams)(void);
- void (EFIAPI *setstationip)(void);
- void (EFIAPI *setpackets)(void);
+struct efi_pxe_base_code_srvlist {
+ u16 type;
+ u8 accept_any_response;
+ u8 reserved;
+ struct efi_ip_address ip_addr;
+};
+
+struct efi_pxe_base_code_discover_info {
+ u8 use_m_cast;
+ u8 use_b_cast;
+ u8 use_u_cast;
+ u8 must_use_list;
+ struct efi_ip_address server_m_cast_ip;
+ u16 ip_cnt;
+ struct efi_pxe_base_code_srvlist srv_list[];
+};
+
+struct efi_pxe_base_code_mtftp_info {
+ struct efi_ip_address m_cast_ip;
+ u16 cport;
+ u16 sport;
+ u16 listen_timeout;
+ u16 transit_timeout;
+};
+
+struct efi_pxe_base_code_filter {
+ u8 filters;
+ u8 ip_cnt;
+ u16 reserved;
+ struct efi_ip_address ip_list[EFI_PXE_BASE_CODE_MAX_IPCNT];
+};
+
+struct efi_pxe_base_code_dhcpv4_packet {
+ u8 bootp_op_code;
+ u8 bootp_hw_type;
+ u8 bootp_addr_len;
+ u8 bootp_gate_hops;
+ u32 bootp_ident;
+ u16 bootp_seconds;
+ u16 bootp_flags;
+ u8 bootp_ci_addr[4];
+ u8 bootp_yi_addr[4];
+ u8 bootp_si_addr[4];
+ u8 bootp_gi_addr[4];
+ u8 bootp_hw_addr[16];
+ u8 bootp_srv_name[64];
+ u8 bootp_boot_file[128];
+ u32 dhcp_magick;
+ u8 dhcp_options[56];
+};
+
+struct efi_pxe_base_code_dhcpv6_packet {
+ u8 message_type;
+ u8 transaction_id[3];
+ u8 dhcp_options[1024];
+};
+
+typedef union {
+ u8 raw[1472];
+ struct efi_pxe_base_code_dhcpv4_packet dhcpv4;
+ struct efi_pxe_base_code_dhcpv6_packet dhcpv6;
+} EFI_PXE_BASE_CODE_PACKET;
+
+struct efi_pxe_base_code_protocol {
+ u64 revision;
+ efi_status_t (EFIAPI *start)(struct efi_pxe_base_code_protocol *this,
+ u8 use_ipv6);
+ efi_status_t (EFIAPI *stop)(struct efi_pxe_base_code_protocol *this);
+ efi_status_t (EFIAPI *dhcp)(struct efi_pxe_base_code_protocol *this,
+ u8 sort_offers);
+ efi_status_t (EFIAPI *discover)(
+ struct efi_pxe_base_code_protocol *this,
+ u16 type, u16 *layer, u8 bis,
+ struct efi_pxe_base_code_discover_info *info);
+ efi_status_t (EFIAPI *mtftp)(
+ struct efi_pxe_base_code_protocol *this,
+ u32 operation, void *buffer_ptr,
+ u8 overwrite, efi_uintn_t *buffer_size,
+ struct efi_ip_address server_ip, char *filename,
+ struct efi_pxe_base_code_mtftp_info *info,
+ u8 dont_use_buffer);
+ efi_status_t (EFIAPI *udp_write)(
+ struct efi_pxe_base_code_protocol *this,
+ u16 op_flags, struct efi_ip_address *dest_ip,
+ u16 *dest_port,
+ struct efi_ip_address *gateway_ip,
+ struct efi_ip_address *src_ip, u16 *src_port,
+ efi_uintn_t *header_size, void *header_ptr,
+ efi_uintn_t *buffer_size, void *buffer_ptr);
+ efi_status_t (EFIAPI *udp_read)(
+ struct efi_pxe_base_code_protocol *this,
+ u16 op_flags, struct efi_ip_address *dest_ip,
+ u16 *dest_port, struct efi_ip_address *src_ip,
+ u16 *src_port, efi_uintn_t *header_size,
+ void *header_ptr, efi_uintn_t *buffer_size,
+ void *buffer_ptr);
+ efi_status_t (EFIAPI *set_ip_filter)(
+ struct efi_pxe_base_code_protocol *this,
+ struct efi_pxe_base_code_filter *new_filter);
+ efi_status_t (EFIAPI *arp)(struct efi_pxe_base_code_protocol *this,
+ struct efi_ip_address *ip_addr,
+ struct efi_mac_address *mac_addr);
+ efi_status_t (EFIAPI *set_parameters)(
+ struct efi_pxe_base_code_protocol *this,
+ u8 *new_auto_arp, u8 *new_send_guid,
+ u8 *new_ttl, u8 *new_tos,
+ u8 *new_make_callback);
+ efi_status_t (EFIAPI *set_station_ip)(
+ struct efi_pxe_base_code_protocol *this,
+ struct efi_ip_address *new_station_ip,
+ struct efi_ip_address *new_subnet_mask);
+ efi_status_t (EFIAPI *set_packets)(
+ struct efi_pxe_base_code_protocol *this,
+ u8 *new_dhcp_discover_valid,
+ u8 *new_dhcp_ack_received,
+ u8 *new_proxy_offer_received,
+ u8 *new_pxe_discover_valid,
+ u8 *new_pxe_reply_received,
+ u8 *new_pxe_bis_reply_received,
+ EFI_PXE_BASE_CODE_PACKET *new_dchp_discover,
+ EFI_PXE_BASE_CODE_PACKET *new_dhcp_acc,
+ EFI_PXE_BASE_CODE_PACKET *new_proxy_offer,
+ EFI_PXE_BASE_CODE_PACKET *new_pxe_discover,
+ EFI_PXE_BASE_CODE_PACKET *new_pxe_reply,
+ EFI_PXE_BASE_CODE_PACKET *new_pxe_bis_reply);
struct efi_pxe_mode *mode;
};
@@ -1345,6 +1461,12 @@
#define EFI_FILE_PROTOCOL_REVISION2 0x00020000
#define EFI_FILE_PROTOCOL_LATEST_REVISION EFI_FILE_PROTOCOL_REVISION2
+struct efi_file_io_token {
+ struct efi_event *event;
+ efi_status_t status;
+ efi_uintn_t buffer_size;
+ void *buffer;};
+
struct efi_file_handle {
u64 rev;
efi_status_t (EFIAPI *open)(struct efi_file_handle *file,
@@ -1367,10 +1489,16 @@
const efi_guid_t *info_type, efi_uintn_t buffer_size,
void *buffer);
efi_status_t (EFIAPI *flush)(struct efi_file_handle *file);
- /*
- * TODO: We currently only support EFI file protocol revision 0x00010000
- * while UEFI specs 2.4 - 2.7 prescribe revision 0x00020000.
- */
+ efi_status_t (EFIAPI *open_ex)(struct efi_file_handle *file,
+ struct efi_file_handle **new_handle,
+ u16 *file_name, u64 open_mode, u64 attributes,
+ struct efi_file_io_token *token);
+ efi_status_t (EFIAPI *read_ex)(struct efi_file_handle *file,
+ struct efi_file_io_token *token);
+ efi_status_t (EFIAPI *write_ex)(struct efi_file_handle *file,
+ struct efi_file_io_token *token);
+ efi_status_t (EFIAPI *flush_ex)(struct efi_file_handle *file,
+ struct efi_file_io_token *token);
};
#define EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_REVISION 0x00010000
@@ -1389,6 +1517,10 @@
EFI_GUID(0x09576e93, 0x6d3f, 0x11d2, \
0x8e, 0x39, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b)
+#define EFI_FILE_SYSTEM_VOLUME_LABEL_ID \
+ EFI_GUID(0xdb47d7d3, 0xfe81, 0x11d3, \
+ 0x9a, 0x35, 0x00, 0x90, 0x27, 0x3f, 0xC1, 0x4d)
+
#define EFI_FILE_MODE_READ 0x0000000000000001
#define EFI_FILE_MODE_WRITE 0x0000000000000002
#define EFI_FILE_MODE_CREATE 0x8000000000000000
diff --git a/include/efi_loader.h b/include/efi_loader.h
index b07155c..53b3699 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -24,6 +24,10 @@
#define U_BOOT_GUID \
EFI_GUID(0xe61d73b9, 0xa384, 0x4acc, \
0xae, 0xab, 0x82, 0xe8, 0x28, 0xf3, 0x62, 0x8b)
+/* GUID used as host device on sandbox */
+#define U_BOOT_HOST_DEV_GUID \
+ EFI_GUID(0xbbe4e671, 0x5773, 0x4ea1, \
+ 0x9a, 0xab, 0x3a, 0x7d, 0xbf, 0x40, 0xc4, 0x82)
/* Root node */
extern efi_handle_t efi_root;
@@ -121,6 +125,10 @@
/* GUID of the U-Boot root node */
extern const efi_guid_t efi_u_boot_guid;
+#ifdef CONFIG_SANDBOX
+/* GUID of U-Boot host device on sandbox */
+extern const efi_guid_t efi_guid_host_dev;
+#endif
/* GUID of the EFI_BLOCK_IO_PROTOCOL */
extern const efi_guid_t efi_block_io_guid;
extern const efi_guid_t efi_global_variable_guid;
@@ -325,10 +333,16 @@
/* Initialize efi execution environment */
efi_status_t efi_init_obj_list(void);
+/* Initialize variable services */
+efi_status_t efi_init_variables(void);
+/* Notify ExitBootServices() is called */
+void efi_variables_boot_exit_notify(void);
/* Called by bootefi to initialize root node */
efi_status_t efi_root_node_register(void);
/* Called by bootefi to initialize runtime */
efi_status_t efi_initialize_system_table(void);
+/* efi_runtime_detach() - detach unimplemented runtime functions */
+void efi_runtime_detach(void);
/* Called by bootefi to make console interface available */
efi_status_t efi_console_register(void);
/* Called by bootefi to make all disk storage accessible as EFI objects */
@@ -470,8 +484,12 @@
efi_uintn_t *descriptor_size,
uint32_t *descriptor_version);
/* Adds a range into the EFI memory map */
-uint64_t efi_add_memory_map(uint64_t start, uint64_t pages, int memory_type,
- bool overlap_only_ram);
+efi_status_t efi_add_memory_map(uint64_t start, uint64_t pages, int memory_type,
+ bool overlap_only_ram);
+/* Adds a conventional range into the EFI memory map */
+efi_status_t efi_add_conventional_memory_map(u64 ram_start, u64 ram_end,
+ u64 ram_top);
+
/* Called by board init to initialize the EFI drivers */
efi_status_t efi_driver_init(void);
/* Called by board init to initialize the EFI memory map */
@@ -545,23 +563,7 @@
(((_dp)->type == DEVICE_PATH_TYPE_##_type) && \
((_dp)->sub_type == DEVICE_PATH_SUB_TYPE_##_subtype))
-/**
- * ascii2unicode() - convert ASCII string to UTF-16 string
- *
- * A zero terminated ASCII string is converted to a zero terminated UTF-16
- * string. The output buffer must be preassigned.
- *
- * @unicode: preassigned output buffer for UTF-16 string
- * @ascii: ASCII string to be converted
- */
-static inline void ascii2unicode(u16 *unicode, const char *ascii)
-{
- while (*ascii)
- *(unicode++) = *(ascii++);
- *unicode = 0;
-}
-
-static inline int guidcmp(const efi_guid_t *g1, const efi_guid_t *g2)
+static inline int guidcmp(const void *g1, const void *g2)
{
return memcmp(g1, g2, sizeof(efi_guid_t));
}
@@ -618,6 +620,11 @@
const efi_guid_t *vendor, u32 attributes,
efi_uintn_t data_size, const void *data);
+efi_status_t EFIAPI efi_query_variable_info(
+ u32 attributes, u64 *maximum_variable_storage_size,
+ u64 *remaining_variable_storage_size,
+ u64 *maximum_variable_size);
+
/*
* See section 3.1.3 in the v2.7 UEFI spec for more details on
* the layout of EFI_LOAD_OPTION. In short it is:
diff --git a/include/env.h b/include/env.h
new file mode 100644
index 0000000..b72239f
--- /dev/null
+++ b/include/env.h
@@ -0,0 +1,336 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Common environment functions and definitions
+ *
+ * (C) Copyright 2000-2009
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#ifndef __ENV_H
+#define __ENV_H
+
+#include <compiler.h>
+#include <stdbool.h>
+#include <linux/types.h>
+
+struct environment_s;
+
+/* Value for environment validity */
+enum env_valid {
+ ENV_INVALID, /* No valid environment */
+ ENV_VALID, /* First or only environment is valid */
+ ENV_REDUND, /* Redundant environment is valid */
+};
+
+/** enum env_op - environment callback operation */
+enum env_op {
+ env_op_create,
+ env_op_delete,
+ env_op_overwrite,
+};
+
+/** struct env_clbk_tbl - declares a new callback */
+struct env_clbk_tbl {
+ const char *name; /* Callback name */
+ int (*callback)(const char *name, const char *value, enum env_op op,
+ int flags);
+};
+
+/*
+ * Define a callback that can be associated with variables.
+ * when associated through the ".callbacks" environment variable, the callback
+ * will be executed any time the variable is inserted, overwritten, or deleted.
+ *
+ * For SPL these are silently dropped to reduce code size, since environment
+ * callbacks are not supported with SPL.
+ */
+#ifdef CONFIG_SPL_BUILD
+#define U_BOOT_ENV_CALLBACK(name, callback) \
+ static inline __maybe_unused void _u_boot_env_noop_##name(void) \
+ { \
+ (void)callback; \
+ }
+#else
+#define U_BOOT_ENV_CALLBACK(name, callback) \
+ ll_entry_declare(struct env_clbk_tbl, name, env_clbk) = \
+ {#name, callback}
+#endif
+
+/** enum env_redund_flags - Flags for the redundand_environment */
+enum env_redund_flags {
+ ENV_REDUND_OBSOLETE = 0,
+ ENV_REDUND_ACTIVE = 1,
+};
+
+/**
+ * env_get_id() - Gets a sequence number for the environment
+ *
+ * This value increments every time the environment changes, so can be used an
+ * an indication of this
+ *
+ * @return environment ID
+ */
+int env_get_id(void);
+
+/**
+ * env_init() - Set up the pre-relocation environment
+ *
+ * This locates the environment or uses the default if nothing is available.
+ * This must be called before env_get() will work.
+ *
+ * @return 0 if OK, -ENODEV if no environment drivers are enabled
+ */
+int env_init(void);
+
+/**
+ * env_relocate() - Set up the post-relocation environment
+ *
+ * This loads the environment into RAM so that it can be modified. This is
+ * called after relocation, before the environment is used
+ */
+void env_relocate(void);
+
+/**
+ * env_match() - Match a name / name=value pair
+ *
+ * This is used prior to relocation for finding envrionment variables
+ *
+ * @name: A simple 'name', or a 'name=value' pair.
+ * @index: The environment index for a 'name2=value2' pair.
+ * @return index for the value if the names match, else -1.
+ */
+int env_match(unsigned char *name, int index);
+
+/**
+ * env_get() - Look up the value of an environment variable
+ *
+ * In U-Boot proper this can be called before relocation (which is when the
+ * environment is loaded from storage, i.e. GD_FLG_ENV_READY is 0). In that
+ * case this function calls env_get_f().
+ *
+ * @varname: Variable to look up
+ * @return value of variable, or NULL if not found
+ */
+char *env_get(const char *varname);
+
+/**
+ * env_get_f() - Look up the value of an environment variable (early)
+ *
+ * This function is called from env_get() if the environment has not been
+ * loaded yet (GD_FLG_ENV_READY flag is 0). Some environment locations will
+ * support reading the value (slowly) and some will not.
+ *
+ * @varname: Variable to look up
+ * @return value of variable, or NULL if not found
+ */
+int env_get_f(const char *name, char *buf, unsigned int len);
+
+/**
+ * env_get_yesno() - Read an environment variable as a boolean
+ *
+ * @return 1 if yes/true (Y/y/T/t), -1 if variable does not exist (i.e. default
+ * to true), 0 if otherwise
+ */
+int env_get_yesno(const char *var);
+
+/**
+ * env_set() - set an environment variable
+ *
+ * This sets or deletes the value of an environment variable. For setting the
+ * value the variable is created if it does not already exist.
+ *
+ * @varname: Variable to adjust
+ * @value: Value to set for the variable, or NULL or "" to delete the variable
+ * @return 0 if OK, 1 on error
+ */
+int env_set(const char *varname, const char *value);
+
+/**
+ * env_get_ulong() - Return an environment variable as an integer value
+ *
+ * Most U-Boot environment variables store hex values. For those which store
+ * (e.g.) base-10 integers, this function can be used to read the value.
+ *
+ * @name: Variable to look up
+ * @base: Base to use (e.g. 10 for base 10, 2 for binary)
+ * @default_val: Default value to return if no value is found
+ * @return the value found, or @default_val if none
+ */
+ulong env_get_ulong(const char *name, int base, ulong default_val);
+
+/**
+ * env_set_ulong() - set an environment variable to an integer
+ *
+ * @varname: Variable to adjust
+ * @value: Value to set for the variable (will be converted to a string)
+ * @return 0 if OK, 1 on error
+ */
+int env_set_ulong(const char *varname, ulong value);
+
+/**
+ * env_get_hex() - Return an environment variable as a hex value
+ *
+ * Decode an environment as a hex number (it may or may not have a 0x
+ * prefix). If the environment variable cannot be found, or does not start
+ * with hex digits, the default value is returned.
+ *
+ * @varname: Variable to decode
+ * @default_val: Value to return on error
+ */
+ulong env_get_hex(const char *varname, ulong default_val);
+
+/**
+ * env_set_hex() - set an environment variable to a hex value
+ *
+ * @varname: Variable to adjust
+ * @value: Value to set for the variable (will be converted to a hex string)
+ * @return 0 if OK, 1 on error
+ */
+int env_set_hex(const char *varname, ulong value);
+
+/**
+ * env_set_addr - Set an environment variable to an address in hex
+ *
+ * @varname: Environment variable to set
+ * @addr: Value to set it to
+ * @return 0 if ok, 1 on error
+ */
+static inline int env_set_addr(const char *varname, const void *addr)
+{
+ return env_set_hex(varname, (ulong)addr);
+}
+
+/**
+ * env_complete() - return an auto-complete for environment variables
+ *
+ * @var: partial name to auto-complete
+ * @maxv: Maximum number of matches to return
+ * @cmdv: Returns a list of possible matches
+ * @maxsz: Size of buffer to use for matches
+ * @buf: Buffer to use for matches
+ * @dollar_comp: non-zero to wrap each match in ${...}
+ * @return number of matches found (in @cmdv)
+ */
+int env_complete(char *var, int maxv, char *cmdv[], int maxsz, char *buf,
+ bool dollar_comp);
+
+/**
+ * eth_env_get_enetaddr() - Get an ethernet address from the environmnet
+ *
+ * @name: Environment variable to get (e.g. "ethaddr")
+ * @enetaddr: Place to put MAC address (6 bytes)
+ * @return 0 if OK, 1 on error
+ */
+int eth_env_get_enetaddr(const char *name, uint8_t *enetaddr);
+
+/**
+ * eth_env_set_enetaddr() - Set an ethernet address in the environmnet
+ *
+ * @name: Environment variable to set (e.g. "ethaddr")
+ * @enetaddr: Pointer to MAC address to put into the variable (6 bytes)
+ * @return 0 if OK, 1 on error
+ */
+int eth_env_set_enetaddr(const char *name, const uint8_t *enetaddr);
+
+/**
+ * env_fix_drivers() - Updates envdriver as per relocation
+ */
+void env_fix_drivers(void);
+
+/**
+ * env_set_default_vars() - reset variables to their default value
+ *
+ * This resets individual variables to their value in the default environment
+ *
+ * @nvars: Number of variables to set/reset
+ * @vars: List of variables to set/reset
+ * @flags: Flags controlling matching (H_... - see search.h)
+ */
+int env_set_default_vars(int nvars, char *const vars[], int flags);
+
+/**
+ * env_load() - Load the environment from storage
+ *
+ * @return 0 if OK, -ve on error
+ */
+int env_load(void);
+
+/**
+ * env_save() - Save the environment to storage
+ *
+ * @return 0 if OK, -ve on error
+ */
+int env_save(void);
+
+/**
+ * env_erase() - Erase the environment on storage
+ *
+ * @return 0 if OK, -ve on error
+ */
+int env_erase(void);
+
+/**
+ * env_import() - Import from a binary representation into hash table
+ *
+ * This imports the environment from a buffer. The format for each variable is
+ * var=value\0 with a double \0 at the end of the buffer.
+ *
+ * @buf: Buffer containing the environment (struct environemnt_s *)
+ * @check: non-zero to check the CRC at the start of the environment, 0 to
+ * ignore it
+ * @return 0 if imported successfully, -ENOMSG if the CRC was bad, -EIO if
+ * something else went wrong
+ */
+int env_import(const char *buf, int check);
+
+/**
+ * env_export() - Export the environment to a buffer
+ *
+ * Export from hash table into binary representation
+ *
+ * @env_out: Buffer to contain the environment (must be large enough!)
+ * @return 0 if OK, 1 on error
+ */
+int env_export(struct environment_s *env_out);
+
+/**
+ * env_import_redund() - Select and import one of two redundant environments
+ *
+ * @buf1: First environment (struct environemnt_s *)
+ * @buf1_read_fail: 0 if buf1 is valid, non-zero if invalid
+ * @buf2: Second environment (struct environemnt_s *)
+ * @buf2_read_fail: 0 if buf2 is valid, non-zero if invalid
+ * @return 0 if OK, -EIO if no environment is valid, -ENOMSG if the CRC was bad
+ */
+int env_import_redund(const char *buf1, int buf1_read_fail,
+ const char *buf2, int buf2_read_fail);
+
+/**
+ * env_get_default() - Look up a variable from the default environment
+ *
+ * @name: Variable to look up
+ * @return value if found, NULL if not found in default environment
+ */
+char *env_get_default(const char *name);
+
+/* [re]set to the default environment */
+void env_set_default(const char *s, int flags);
+
+/**
+ * env_get_char() - Get a character from the early environment
+ *
+ * This reads from the pre-relocation environment
+ *
+ * @index: Index of character to read (0 = first)
+ * @return character read, or -ve on error
+ */
+int env_get_char(int index);
+
+/**
+ * env_reloc() - Relocate the 'env' sub-commands
+ *
+ * This is used for those unfortunate archs with crappy toolchains
+ */
+void env_reloc(void);
+
+#endif
diff --git a/include/env_callback.h b/include/env_callback.h
index 507a52e..74da20e 100644
--- a/include/env_callback.h
+++ b/include/env_callback.h
@@ -42,7 +42,7 @@
#define DNS_CALLBACK
#endif
-#ifdef CONFIG_CMD_NET
+#ifdef CONFIG_NET
#define NET_CALLBACKS \
"bootfile:bootfile," \
"ipaddr:ipaddr," \
@@ -72,29 +72,6 @@
"serial#:serialno," \
CONFIG_ENV_CALLBACK_LIST_STATIC
-struct env_clbk_tbl {
- const char *name; /* Callback name */
- int (*callback)(const char *name, const char *value, enum env_op op,
- int flags);
-};
-
-void env_callback_init(ENTRY *var_entry);
-
-/*
- * Define a callback that can be associated with variables.
- * when associated through the ".callbacks" environment variable, the callback
- * will be executed any time the variable is inserted, overwritten, or deleted.
- */
-#ifdef CONFIG_SPL_BUILD
-#define U_BOOT_ENV_CALLBACK(name, callback) \
- static inline __maybe_unused void _u_boot_env_noop_##name(void) \
- { \
- (void)callback; \
- }
-#else
-#define U_BOOT_ENV_CALLBACK(name, callback) \
- ll_entry_declare(struct env_clbk_tbl, name, env_clbk) = \
- {#name, callback}
-#endif
+void env_callback_init(struct env_entry *var_entry);
#endif /* __ENV_CALLBACK_H__ */
diff --git a/include/env_default.h b/include/env_default.h
index 86b639d..56a8bae 100644
--- a/include/env_default.h
+++ b/include/env_default.h
@@ -10,7 +10,7 @@
#include <env_callback.h>
#ifdef DEFAULT_ENV_INSTANCE_EMBEDDED
-env_t environment __UBOOT_ENV_SECTION__(environment) = {
+env_t embedded_environment __UBOOT_ENV_SECTION__(environment) = {
ENV_CRC, /* CRC Sum */
#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT
1, /* Flags: valid */
diff --git a/include/env_flags.h b/include/env_flags.h
index 23744e3..725841a 100644
--- a/include/env_flags.h
+++ b/include/env_flags.h
@@ -36,7 +36,7 @@
#define CONFIG_ENV_FLAGS_LIST_STATIC ""
#endif
-#ifdef CONFIG_CMD_NET
+#ifdef CONFIG_NET
#ifdef CONFIG_REGEX
#define ETHADDR_WILDCARD "\\d*"
#else
@@ -146,19 +146,20 @@
#else /* !USE_HOSTCC */
+#include <env.h>
#include <search.h>
/*
* When adding a variable to the environment, initialize the flags for that
* variable.
*/
-void env_flags_init(ENTRY *var_entry);
+void env_flags_init(struct env_entry *var_entry);
/*
* Validate the newval for to conform with the requirements defined by its flags
*/
-int env_flags_validate(const ENTRY *item, const char *newval, enum env_op op,
- int flag);
+int env_flags_validate(const struct env_entry *item, const char *newval,
+ enum env_op op, int flag);
#endif /* USE_HOSTCC */
diff --git a/include/env_internal.h b/include/env_internal.h
new file mode 100644
index 0000000..eb47f0a
--- /dev/null
+++ b/include/env_internal.h
@@ -0,0 +1,279 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Internal environment header file. This includes direct access to environment
+ * information such as its size and offset, direct access to the default
+ * environment and embedded environment (if used). It also provides environment
+ * drivers with various declarations.
+ *
+ * It should not be included by board files, drivers and code other than that
+ * related to the environment implementation.
+ *
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#ifndef _ENV_INTERNAL_H_
+#define _ENV_INTERNAL_H_
+
+#include <linux/kconfig.h>
+
+/**************************************************************************
+ *
+ * The "environment" is stored as a list of '\0' terminated
+ * "name=value" strings. The end of the list is marked by a double
+ * '\0'. New entries are always added at the end. Deleting an entry
+ * shifts the remaining entries to the front. Replacing an entry is a
+ * combination of deleting the old value and adding the new one.
+ *
+ * The environment is preceded by a 32 bit CRC over the data part.
+ *
+ *************************************************************************/
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+# ifndef CONFIG_ENV_ADDR
+# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+# endif
+# ifndef CONFIG_ENV_OFFSET
+# define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
+# endif
+# if !defined(CONFIG_ENV_ADDR_REDUND) && defined(CONFIG_ENV_OFFSET_REDUND)
+# define CONFIG_ENV_ADDR_REDUND \
+ (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET_REDUND)
+# endif
+# if defined(CONFIG_ENV_SECT_SIZE) || defined(CONFIG_ENV_SIZE)
+# ifndef CONFIG_ENV_SECT_SIZE
+# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
+# endif
+# ifndef CONFIG_ENV_SIZE
+# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+# endif
+# else
+# error "Both CONFIG_ENV_SECT_SIZE and CONFIG_ENV_SIZE undefined"
+# endif
+# if defined(CONFIG_ENV_ADDR_REDUND) && !defined(CONFIG_ENV_SIZE_REDUND)
+# define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+# endif
+# if (CONFIG_ENV_ADDR >= CONFIG_SYS_MONITOR_BASE) && \
+ (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) <= \
+ (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+# define ENV_IS_EMBEDDED
+# endif
+# if defined(CONFIG_ENV_ADDR_REDUND) || defined(CONFIG_ENV_OFFSET_REDUND)
+# define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+# endif
+# ifdef CONFIG_ENV_IS_EMBEDDED
+# error "do not define CONFIG_ENV_IS_EMBEDDED in your board config"
+# error "it is calculated automatically for you"
+# endif
+#endif /* CONFIG_ENV_IS_IN_FLASH */
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+# ifdef CONFIG_ENV_OFFSET_REDUND
+# define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+# endif
+#endif
+
+#if defined(CONFIG_ENV_IS_IN_NAND)
+# if defined(CONFIG_ENV_OFFSET_OOB)
+# ifdef CONFIG_ENV_OFFSET_REDUND
+# error "CONFIG_ENV_OFFSET_REDUND is not supported when CONFIG_ENV_OFFSET_OOB"
+# error "is set"
+# endif
+extern unsigned long nand_env_oob_offset;
+# define CONFIG_ENV_OFFSET nand_env_oob_offset
+# else
+# ifndef CONFIG_ENV_OFFSET
+# error "Need to define CONFIG_ENV_OFFSET when using CONFIG_ENV_IS_IN_NAND"
+# endif
+# ifdef CONFIG_ENV_OFFSET_REDUND
+# define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+# endif
+# endif /* CONFIG_ENV_OFFSET_OOB */
+# ifndef CONFIG_ENV_SIZE
+# error "Need to define CONFIG_ENV_SIZE when using CONFIG_ENV_IS_IN_NAND"
+# endif
+#endif /* CONFIG_ENV_IS_IN_NAND */
+
+#if defined(CONFIG_ENV_IS_IN_UBI)
+# ifndef CONFIG_ENV_UBI_PART
+# error "Need to define CONFIG_ENV_UBI_PART when using CONFIG_ENV_IS_IN_UBI"
+# endif
+# ifndef CONFIG_ENV_UBI_VOLUME
+# error "Need to define CONFIG_ENV_UBI_VOLUME when using CONFIG_ENV_IS_IN_UBI"
+# endif
+# if defined(CONFIG_ENV_UBI_VOLUME_REDUND)
+# define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+# endif
+# ifndef CONFIG_ENV_SIZE
+# error "Need to define CONFIG_ENV_SIZE when using CONFIG_ENV_IS_IN_UBI"
+# endif
+# ifndef CONFIG_CMD_UBI
+# error "Need to define CONFIG_CMD_UBI when using CONFIG_ENV_IS_IN_UBI"
+# endif
+#endif /* CONFIG_ENV_IS_IN_UBI */
+
+/* Embedded env is only supported for some flash types */
+#ifdef CONFIG_ENV_IS_EMBEDDED
+# if !defined(CONFIG_ENV_IS_IN_FLASH) && \
+ !defined(CONFIG_ENV_IS_IN_NAND) && \
+ !defined(CONFIG_ENV_IS_IN_ONENAND) && \
+ !defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+# error "CONFIG_ENV_IS_EMBEDDED not supported for your flash type"
+# endif
+#endif
+
+/*
+ * For the flash types where embedded env is supported, but it cannot be
+ * calculated automatically (i.e. NAND), take the board opt-in.
+ */
+#if defined(CONFIG_ENV_IS_EMBEDDED) && !defined(ENV_IS_EMBEDDED)
+# define ENV_IS_EMBEDDED
+#endif
+
+/* The build system likes to know if the env is embedded */
+#ifdef DO_DEPS_ONLY
+# ifdef ENV_IS_EMBEDDED
+# ifndef CONFIG_ENV_IS_EMBEDDED
+# define CONFIG_ENV_IS_EMBEDDED
+# endif
+# endif
+#endif
+
+#include "compiler.h"
+
+#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT
+# define ENV_HEADER_SIZE (sizeof(uint32_t) + 1)
+#else
+# define ENV_HEADER_SIZE (sizeof(uint32_t))
+#endif
+
+#define ENV_SIZE (CONFIG_ENV_SIZE - ENV_HEADER_SIZE)
+
+/*
+ * If the environment is in RAM, allocate extra space for it in the malloc
+ * region.
+ */
+#if defined(CONFIG_ENV_IS_EMBEDDED)
+#define TOTAL_MALLOC_LEN CONFIG_SYS_MALLOC_LEN
+#elif (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE < CONFIG_SYS_MONITOR_BASE) || \
+ (CONFIG_ENV_ADDR >= CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) || \
+ defined(CONFIG_ENV_IS_IN_NVRAM)
+#define TOTAL_MALLOC_LEN (CONFIG_SYS_MALLOC_LEN + CONFIG_ENV_SIZE)
+#else
+#define TOTAL_MALLOC_LEN CONFIG_SYS_MALLOC_LEN
+#endif
+
+typedef struct environment_s {
+ uint32_t crc; /* CRC32 over data bytes */
+#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT
+ unsigned char flags; /* active/obsolete flags ENVF_REDUND_ */
+#endif
+ unsigned char data[ENV_SIZE]; /* Environment data */
+} env_t;
+
+#ifdef ENV_IS_EMBEDDED
+extern env_t embedded_environment;
+#endif /* ENV_IS_EMBEDDED */
+
+extern const unsigned char default_environment[];
+
+#ifndef DO_DEPS_ONLY
+
+#include <env_attr.h>
+#include <env_callback.h>
+#include <env_flags.h>
+#include <search.h>
+
+enum env_location {
+ ENVL_UNKNOWN,
+ ENVL_EEPROM,
+ ENVL_EXT4,
+ ENVL_FAT,
+ ENVL_FLASH,
+ ENVL_MMC,
+ ENVL_NAND,
+ ENVL_NVRAM,
+ ENVL_ONENAND,
+ ENVL_RAW_DISK,
+ ENVL_REMOTE,
+ ENVL_SPI_FLASH,
+ ENVL_UBI,
+ ENVL_NOWHERE,
+
+ ENVL_COUNT,
+};
+
+/* value for the various operations we want to perform on the env */
+enum env_operation {
+ ENVOP_GET_CHAR, /* we want to call the get_char function */
+ ENVOP_INIT, /* we want to call the init function */
+ ENVOP_LOAD, /* we want to call the load function */
+ ENVOP_SAVE, /* we want to call the save function */
+ ENVOP_ERASE, /* we want to call the erase function */
+};
+
+struct env_driver {
+ const char *name;
+ enum env_location location;
+
+ /**
+ * load() - Load the environment from storage
+ *
+ * This method is optional. If not provided, no environment will be
+ * loaded.
+ *
+ * @return 0 if OK, -ve on error
+ */
+ int (*load)(void);
+
+ /**
+ * save() - Save the environment to storage
+ *
+ * This method is required for 'saveenv' to work.
+ *
+ * @return 0 if OK, -ve on error
+ */
+ int (*save)(void);
+
+ /**
+ * erase() - Erase the environment on storage
+ *
+ * This method is optional and required for 'eraseenv' to work.
+ *
+ * @return 0 if OK, -ve on error
+ */
+ int (*erase)(void);
+
+ /**
+ * init() - Set up the initial pre-relocation environment
+ *
+ * This method is optional.
+ *
+ * @return 0 if OK, -ENOENT if no initial environment could be found,
+ * other -ve on error
+ */
+ int (*init)(void);
+};
+
+/* Declare a new environment location driver */
+#define U_BOOT_ENV_LOCATION(__name) \
+ ll_entry_declare(struct env_driver, __name, env_driver)
+
+/* Declare the name of a location */
+#ifdef CONFIG_CMD_SAVEENV
+#define ENV_NAME(_name) .name = _name,
+#else
+#define ENV_NAME(_name)
+#endif
+
+#ifdef CONFIG_CMD_SAVEENV
+#define env_save_ptr(x) x
+#else
+#define env_save_ptr(x) NULL
+#endif
+
+extern struct hsearch_data env_htab;
+
+#endif /* DO_DEPS_ONLY */
+
+#endif /* _ENV_INTERNAL_H_ */
diff --git a/include/environment.h b/include/environment.h
deleted file mode 100644
index 266fa41..0000000
--- a/include/environment.h
+++ /dev/null
@@ -1,318 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#ifndef _ENVIRONMENT_H_
-#define _ENVIRONMENT_H_
-
-#include <linux/kconfig.h>
-
-/**************************************************************************
- *
- * The "environment" is stored as a list of '\0' terminated
- * "name=value" strings. The end of the list is marked by a double
- * '\0'. New entries are always added at the end. Deleting an entry
- * shifts the remaining entries to the front. Replacing an entry is a
- * combination of deleting the old value and adding the new one.
- *
- * The environment is preceded by a 32 bit CRC over the data part.
- *
- *************************************************************************/
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef CONFIG_ENV_ADDR
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef CONFIG_ENV_OFFSET
-# define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
-# endif
-# if !defined(CONFIG_ENV_ADDR_REDUND) && defined(CONFIG_ENV_OFFSET_REDUND)
-# define CONFIG_ENV_ADDR_REDUND \
- (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET_REDUND)
-# endif
-# if defined(CONFIG_ENV_SECT_SIZE) || defined(CONFIG_ENV_SIZE)
-# ifndef CONFIG_ENV_SECT_SIZE
-# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-# endif
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
-# else
-# error "Both CONFIG_ENV_SECT_SIZE and CONFIG_ENV_SIZE undefined"
-# endif
-# if defined(CONFIG_ENV_ADDR_REDUND) && !defined(CONFIG_ENV_SIZE_REDUND)
-# define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-# endif
-# if (CONFIG_ENV_ADDR >= CONFIG_SYS_MONITOR_BASE) && \
- (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) <= \
- (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-# define ENV_IS_EMBEDDED
-# endif
-# if defined(CONFIG_ENV_ADDR_REDUND) || defined(CONFIG_ENV_OFFSET_REDUND)
-# define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-# endif
-# ifdef CONFIG_ENV_IS_EMBEDDED
-# error "do not define CONFIG_ENV_IS_EMBEDDED in your board config"
-# error "it is calculated automatically for you"
-# endif
-#endif /* CONFIG_ENV_IS_IN_FLASH */
-
-#if defined(CONFIG_ENV_IS_IN_MMC)
-# ifdef CONFIG_ENV_OFFSET_REDUND
-# define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-# endif
-#endif
-
-#if defined(CONFIG_ENV_IS_IN_NAND)
-# if defined(CONFIG_ENV_OFFSET_OOB)
-# ifdef CONFIG_ENV_OFFSET_REDUND
-# error "CONFIG_ENV_OFFSET_REDUND is not supported when CONFIG_ENV_OFFSET_OOB"
-# error "is set"
-# endif
-extern unsigned long nand_env_oob_offset;
-# define CONFIG_ENV_OFFSET nand_env_oob_offset
-# else
-# ifndef CONFIG_ENV_OFFSET
-# error "Need to define CONFIG_ENV_OFFSET when using CONFIG_ENV_IS_IN_NAND"
-# endif
-# ifdef CONFIG_ENV_OFFSET_REDUND
-# define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-# endif
-# endif /* CONFIG_ENV_OFFSET_OOB */
-# ifndef CONFIG_ENV_SIZE
-# error "Need to define CONFIG_ENV_SIZE when using CONFIG_ENV_IS_IN_NAND"
-# endif
-#endif /* CONFIG_ENV_IS_IN_NAND */
-
-#if defined(CONFIG_ENV_IS_IN_UBI)
-# ifndef CONFIG_ENV_UBI_PART
-# error "Need to define CONFIG_ENV_UBI_PART when using CONFIG_ENV_IS_IN_UBI"
-# endif
-# ifndef CONFIG_ENV_UBI_VOLUME
-# error "Need to define CONFIG_ENV_UBI_VOLUME when using CONFIG_ENV_IS_IN_UBI"
-# endif
-# if defined(CONFIG_ENV_UBI_VOLUME_REDUND)
-# define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-# endif
-# ifndef CONFIG_ENV_SIZE
-# error "Need to define CONFIG_ENV_SIZE when using CONFIG_ENV_IS_IN_UBI"
-# endif
-# ifndef CONFIG_CMD_UBI
-# error "Need to define CONFIG_CMD_UBI when using CONFIG_ENV_IS_IN_UBI"
-# endif
-#endif /* CONFIG_ENV_IS_IN_UBI */
-
-/* Embedded env is only supported for some flash types */
-#ifdef CONFIG_ENV_IS_EMBEDDED
-# if !defined(CONFIG_ENV_IS_IN_FLASH) && \
- !defined(CONFIG_ENV_IS_IN_NAND) && \
- !defined(CONFIG_ENV_IS_IN_ONENAND) && \
- !defined(CONFIG_ENV_IS_IN_SPI_FLASH)
-# error "CONFIG_ENV_IS_EMBEDDED not supported for your flash type"
-# endif
-#endif
-
-/*
- * For the flash types where embedded env is supported, but it cannot be
- * calculated automatically (i.e. NAND), take the board opt-in.
- */
-#if defined(CONFIG_ENV_IS_EMBEDDED) && !defined(ENV_IS_EMBEDDED)
-# define ENV_IS_EMBEDDED
-#endif
-
-/* The build system likes to know if the env is embedded */
-#ifdef DO_DEPS_ONLY
-# ifdef ENV_IS_EMBEDDED
-# ifndef CONFIG_ENV_IS_EMBEDDED
-# define CONFIG_ENV_IS_EMBEDDED
-# endif
-# endif
-#endif
-
-#include "compiler.h"
-
-#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT
-# define ENV_HEADER_SIZE (sizeof(uint32_t) + 1)
-
-# define ACTIVE_FLAG 1
-# define OBSOLETE_FLAG 0
-#else
-# define ENV_HEADER_SIZE (sizeof(uint32_t))
-#endif
-
-#define ENV_SIZE (CONFIG_ENV_SIZE - ENV_HEADER_SIZE)
-
-typedef struct environment_s {
- uint32_t crc; /* CRC32 over data bytes */
-#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT
- unsigned char flags; /* active/obsolete flags */
-#endif
- unsigned char data[ENV_SIZE]; /* Environment data */
-} env_t;
-
-#ifdef ENV_IS_EMBEDDED
-extern env_t environment;
-#endif /* ENV_IS_EMBEDDED */
-
-extern const unsigned char default_environment[];
-
-#if defined(CONFIG_NEEDS_MANUAL_RELOC)
-extern void env_reloc(void);
-#endif
-
-#ifndef DO_DEPS_ONLY
-
-#include <env_attr.h>
-#include <env_callback.h>
-#include <env_flags.h>
-#include <search.h>
-
-/* Value for environment validity */
-enum env_valid {
- ENV_INVALID, /* No valid environment */
- ENV_VALID, /* First or only environment is valid */
- ENV_REDUND, /* Redundant environment is valid */
-};
-
-enum env_location {
- ENVL_UNKNOWN,
- ENVL_EEPROM,
- ENVL_EXT4,
- ENVL_FAT,
- ENVL_FLASH,
- ENVL_MMC,
- ENVL_NAND,
- ENVL_NVRAM,
- ENVL_ONENAND,
- ENVL_RAW_DISK,
- ENVL_REMOTE,
- ENVL_SPI_FLASH,
- ENVL_UBI,
- ENVL_NOWHERE,
-
- ENVL_COUNT,
-};
-
-/* value for the various operations we want to perform on the env */
-enum env_operation {
- ENVOP_GET_CHAR, /* we want to call the get_char function */
- ENVOP_INIT, /* we want to call the init function */
- ENVOP_LOAD, /* we want to call the load function */
- ENVOP_SAVE, /* we want to call the save function */
-};
-
-struct env_driver {
- const char *name;
- enum env_location location;
-
- /**
- * load() - Load the environment from storage
- *
- * This method is optional. If not provided, no environment will be
- * loaded.
- *
- * @return 0 if OK, -ve on error
- */
- int (*load)(void);
-
- /**
- * save() - Save the environment to storage
- *
- * This method is required for 'saveenv' to work.
- *
- * @return 0 if OK, -ve on error
- */
- int (*save)(void);
-
- /**
- * init() - Set up the initial pre-relocation environment
- *
- * This method is optional.
- *
- * @return 0 if OK, -ENOENT if no initial environment could be found,
- * other -ve on error
- */
- int (*init)(void);
-};
-
-/* Declare a new environment location driver */
-#define U_BOOT_ENV_LOCATION(__name) \
- ll_entry_declare(struct env_driver, __name, env_driver)
-
-/* Declare the name of a location */
-#ifdef CONFIG_CMD_SAVEENV
-#define ENV_NAME(_name) .name = _name,
-#else
-#define ENV_NAME(_name)
-#endif
-
-#ifdef CONFIG_CMD_SAVEENV
-#define env_save_ptr(x) x
-#else
-#define env_save_ptr(x) NULL
-#endif
-
-extern struct hsearch_data env_htab;
-
-/* Function that updates CRC of the enironment */
-void env_crc_update(void);
-
-/* Look up the variable from the default environment */
-char *env_get_default(const char *name);
-
-/* [re]set to the default environment */
-void set_default_env(const char *s, int flags);
-
-/* [re]set individual variables to their value in the default environment */
-int set_default_vars(int nvars, char * const vars[], int flags);
-
-/* Import from binary representation into hash table */
-int env_import(const char *buf, int check);
-
-/* Export from hash table into binary representation */
-int env_export(env_t *env_out);
-
-#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT
-/* Select and import one of two redundant environments */
-int env_import_redund(const char *buf1, int buf1_status,
- const char *buf2, int buf2_status);
-#endif
-
-/**
- * env_get_char() - Get a character from the early environment
- *
- * This reads from the pre-relocation environment
- *
- * @index: Index of character to read (0 = first)
- * @return character read, or -ve on error
- */
-int env_get_char(int index);
-
-/**
- * env_load() - Load the environment from storage
- *
- * @return 0 if OK, -ve on error
- */
-int env_load(void);
-
-/**
- * env_save() - Save the environment to storage
- *
- * @return 0 if OK, -ve on error
- */
-int env_save(void);
-
-/**
- * env_fix_drivers() - Updates envdriver as per relocation
- */
-void env_fix_drivers(void);
-
-void eth_parse_enetaddr(const char *addr, uint8_t *enetaddr);
-int eth_env_get_enetaddr(const char *name, uint8_t *enetaddr);
-int eth_env_set_enetaddr(const char *name, const uint8_t *enetaddr);
-
-#endif /* DO_DEPS_ONLY */
-
-#endif /* _ENVIRONMENT_H_ */
diff --git a/include/environment/ti/boot.h b/include/environment/ti/boot.h
index 54e9b2d..684a744 100644
--- a/include/environment/ti/boot.h
+++ b/include/environment/ti/boot.h
@@ -10,7 +10,7 @@
#define __TI_BOOT_H
#ifndef CONSOLEDEV
-#define CONSOLEDEV "ttyO2"
+#define CONSOLEDEV "ttyS2"
#endif
#define VBMETA_PART_SIZE (64 * 1024)
@@ -98,6 +98,10 @@
#define AB_SELECT ""
#endif
+#define FASTBOOT_CMD \
+ "echo Booting into fastboot ...; " \
+ "fastboot " __stringify(CONFIG_FASTBOOT_USB_DEV) "; "
+
#define DEFAULT_COMMON_BOOT_TI_ARGS \
"console=" CONSOLEDEV ",115200n8\0" \
"fdtfile=undefined\0" \
@@ -117,6 +121,28 @@
"setenv mmcroot /dev/mmcblk0p2 rw; " \
"run mmcboot;\0" \
"emmc_android_boot=" \
+ "if bcb load " __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) " " \
+ CONTROL_PARTITION "; then " \
+ "if bcb test command = bootonce-bootloader; then " \
+ "echo BCB: Bootloader boot...; " \
+ "bcb clear command; bcb store; " \
+ FASTBOOT_CMD \
+ "elif bcb test command = boot-recovery; then " \
+ "echo BCB: Recovery boot...; " \
+ "echo Warning: recovery is not implemented; " \
+ "echo Performing normal boot for now...; " \
+ "bcb clear command; bcb store; " \
+ "run emmc_android_normal_boot; " \
+ "else " \
+ "echo BCB: Normal boot requested...; " \
+ "run emmc_android_normal_boot; " \
+ "fi; " \
+ "else " \
+ "echo Warning: BCB is corrupted or does not exist; " \
+ "echo Performing normal boot...; " \
+ "run emmc_android_normal_boot; " \
+ "fi;\0" \
+ "emmc_android_normal_boot=" \
"echo Trying to boot Android from eMMC ...; " \
"run update_to_fit; " \
"setenv eval_bootargs setenv bootargs $bootargs; " \
@@ -176,8 +202,7 @@
"if test ${dofastboot} -eq 1; then " \
"echo Boot fastboot requested, resetting dofastboot ...;" \
"setenv dofastboot 0; saveenv;" \
- "echo Booting into fastboot ...; " \
- "fastboot " __stringify(CONFIG_FASTBOOT_USB_DEV) "; " \
+ FASTBOOT_CMD \
"fi;" \
"if test ${boot_fit} -eq 1; then " \
"run update_to_fit;" \
diff --git a/include/environment/ti/mmc.h b/include/environment/ti/mmc.h
index 785fc15..bb4af0a 100644
--- a/include/environment/ti/mmc.h
+++ b/include/environment/ti/mmc.h
@@ -56,7 +56,7 @@
"bootz; " \
"fi;\0" \
"mmcboot=mmc dev ${mmcdev}; " \
- "setenv devnum ${mmcdev}; " \
+ "devnum=${mmcdev}; " \
"setenv devtype mmc; " \
"if mmc rescan; then " \
"echo SD/MMC found on device ${mmcdev};" \
diff --git a/include/exports.h b/include/exports.h
index a4b862f..147a00f 100644
--- a/include/exports.h
+++ b/include/exports.h
@@ -3,6 +3,7 @@
#ifndef __ASSEMBLY__
#ifdef CONFIG_PHY_AQUANTIA
+#include <env.h>
#include <phy_interface.h>
#endif
@@ -32,8 +33,7 @@
int strcmp(const char *cs, const char *ct);
unsigned long ustrtoul(const char *cp, char **endp, unsigned int base);
unsigned long long ustrtoull(const char *cp, char **endp, unsigned int base);
-#if defined(CONFIG_CMD_I2C) && \
- (!defined(CONFIG_DM_I2C) || defined(CONFIG_DM_I2C_COMPAT))
+#if defined(CONFIG_CMD_I2C) && !defined(CONFIG_DM_I2C)
int i2c_write (uchar, uint, int , uchar* , int);
int i2c_read (uchar, uint, int , uchar* , int);
#endif
diff --git a/include/ext_common.h b/include/ext_common.h
index 17c92f1..1c10c50 100644
--- a/include/ext_common.h
+++ b/include/ext_common.h
@@ -21,6 +21,7 @@
#define __EXT_COMMON__
#include <command.h>
#define SECTOR_SIZE 0x200
+#define LOG2_SECTOR_SIZE 9
/* Magic value used to identify an ext2 filesystem. */
#define EXT2_MAGIC 0xEF53
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 27fe564..cefb2b2 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -218,8 +218,32 @@
#endif
void fdt_del_node_and_alias(void *blob, const char *alias);
+
+/**
+ * Translate an address from the DT into a CPU physical address
+ *
+ * The translation relies on the "ranges" property.
+ *
+ * @param blob Pointer to device tree blob
+ * @param node_offset Node DT offset
+ * @param in_addr Pointer to the address to translate
+ * @return translated address or OF_BAD_ADDR on error
+ */
u64 fdt_translate_address(const void *blob, int node_offset,
const __be32 *in_addr);
+/**
+ * Translate a DMA address from the DT into a CPU physical address
+ *
+ * The translation relies on the "dma-ranges" property.
+ *
+ * @param blob Pointer to device tree blob
+ * @param node_offset Node DT offset
+ * @param in_addr Pointer to the DMA address to translate
+ * @return translated DMA address or OF_BAD_ADDR on error
+ */
+u64 fdt_translate_dma_address(const void *blob, int node_offset,
+ const __be32 *in_addr);
+
int fdt_node_offset_by_compat_reg(void *blob, const char *compat,
phys_addr_t compat_off);
int fdt_alloc_phandle(void *blob);
diff --git a/include/fdtdec.h b/include/fdtdec.h
index e6c22dd..635f530 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -54,7 +54,7 @@
#define SPL_BUILD 0
#endif
-#if CONFIG_IS_ENABLED(OF_PRIOR_STAGE)
+#ifdef CONFIG_OF_PRIOR_STAGE
extern phys_addr_t prior_stage_fdt_address;
#endif
diff --git a/include/fpga.h b/include/fpga.h
index 51de5c5..ec51443 100644
--- a/include/fpga.h
+++ b/include/fpga.h
@@ -15,7 +15,7 @@
/* fpga_xxxx function return value definitions */
#define FPGA_SUCCESS 0
-#define FPGA_FAIL -1
+#define FPGA_FAIL 1
/* device numbers must be non-negative */
#define FPGA_INVALID_DEVICE -1
diff --git a/include/fsl-mc/fsl_mc.h b/include/fsl-mc/fsl_mc.h
index 0abd797..a4d7d85 100644
--- a/include/fsl-mc/fsl_mc.h
+++ b/include/fsl-mc/fsl_mc.h
@@ -55,6 +55,7 @@
int get_mc_boot_status(void);
int get_dpl_apply_status(void);
int is_lazy_dpl_addr_valid(void);
+void fdt_fixup_mc_ddr(u64 *base, u64 *size);
#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
int get_aiop_apply_status(void);
#endif
diff --git a/include/fsl_dcu_fb.h b/include/fsl_dcu_fb.h
index 2dd5f54..7a5347a 100644
--- a/include/fsl_dcu_fb.h
+++ b/include/fsl_dcu_fb.h
@@ -6,11 +6,17 @@
*/
#include <linux/fb.h>
-int fsl_dcu_init(unsigned int xres, unsigned int yres,
+int fsl_dcu_init(struct fb_info *fbinfo,
+ unsigned int xres,
+ unsigned int yres,
unsigned int pixel_format);
+
int fsl_dcu_fixedfb_setup(void *blob);
/* Prototypes for external board-specific functions */
-int platform_dcu_init(unsigned int xres, unsigned int yres,
- const char *port, struct fb_videomode *dcu_fb_videomode);
+int platform_dcu_init(struct fb_info *fbinfo,
+ unsigned int xres,
+ unsigned int yres,
+ const char *port,
+ struct fb_videomode *dcu_fb_videomode);
unsigned int dcu_set_pixel_clock(unsigned int pixclock);
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index 8dbd524..33dcbee 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -9,7 +9,6 @@
#ifndef __FSL_ESDHC_H__
#define __FSL_ESDHC_H__
-#include <linux/bitops.h>
#include <linux/errno.h>
#include <asm/byteorder.h>
@@ -25,22 +24,14 @@
#define SYSCTL_INITA 0x08000000
#define SYSCTL_TIMEOUT_MASK 0x000f0000
#define SYSCTL_CLOCK_MASK 0x0000fff0
-#if !defined(CONFIG_FSL_USDHC)
#define SYSCTL_CKEN 0x00000008
#define SYSCTL_PEREN 0x00000004
#define SYSCTL_HCKEN 0x00000002
#define SYSCTL_IPGEN 0x00000001
-#endif
#define SYSCTL_RSTA 0x01000000
#define SYSCTL_RSTC 0x02000000
#define SYSCTL_RSTD 0x04000000
-#define VENDORSPEC_CKEN 0x00004000
-#define VENDORSPEC_PEREN 0x00002000
-#define VENDORSPEC_HCKEN 0x00001000
-#define VENDORSPEC_IPGEN 0x00000800
-#define VENDORSPEC_INIT 0x20007809
-
#define IRQSTAT 0x0002e030
#define IRQSTAT_DMAE (0x10000000)
#define IRQSTAT_AC12E (0x01000000)
@@ -172,54 +163,6 @@
#define ESDHC_HOSTCAPBLT_DMAS 0x00400000
#define ESDHC_HOSTCAPBLT_HSS 0x00200000
-#define ESDHC_VENDORSPEC_VSELECT 0x00000002 /* Use 1.8V */
-
-/* Imported from Linux Kernel drivers/mmc/host/sdhci-esdhc-imx.c */
-#define MIX_CTRL_DDREN BIT(3)
-#define MIX_CTRL_DTDSEL_READ BIT(4)
-#define MIX_CTRL_AC23EN BIT(7)
-#define MIX_CTRL_EXE_TUNE BIT(22)
-#define MIX_CTRL_SMPCLK_SEL BIT(23)
-#define MIX_CTRL_AUTO_TUNE_EN BIT(24)
-#define MIX_CTRL_FBCLK_SEL BIT(25)
-#define MIX_CTRL_HS400_EN BIT(26)
-#define MIX_CTRL_HS400_ES BIT(27)
-/* Bits 3 and 6 are not SDHCI standard definitions */
-#define MIX_CTRL_SDHCI_MASK 0xb7
-/* Tuning bits */
-#define MIX_CTRL_TUNING_MASK 0x03c00000
-
-/* strobe dll register */
-#define ESDHC_STROBE_DLL_CTRL 0x70
-#define ESDHC_STROBE_DLL_CTRL_ENABLE BIT(0)
-#define ESDHC_STROBE_DLL_CTRL_RESET BIT(1)
-#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT 0x7
-#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
-
-#define ESDHC_STROBE_DLL_STATUS 0x74
-#define ESDHC_STROBE_DLL_STS_REF_LOCK BIT(1)
-#define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1
-#define ESDHC_STROBE_DLL_CLK_FREQ 100000000
-
-#define ESDHC_STD_TUNING_EN BIT(24)
-/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
-#define ESDHC_TUNING_START_TAP_DEFAULT 0x1
-#define ESDHC_TUNING_START_TAP_MASK 0xff
-#define ESDHC_TUNING_STEP_MASK 0x00070000
-#define ESDHC_TUNING_STEP_SHIFT 16
-
-#define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1)
-#define ESDHC_FLAG_ENGCM07207 BIT(2)
-#define ESDHC_FLAG_USDHC BIT(3)
-#define ESDHC_FLAG_MAN_TUNING BIT(4)
-#define ESDHC_FLAG_STD_TUNING BIT(5)
-#define ESDHC_FLAG_HAVE_CAP1 BIT(6)
-#define ESDHC_FLAG_ERR004536 BIT(7)
-#define ESDHC_FLAG_HS200 BIT(8)
-#define ESDHC_FLAG_HS400 BIT(9)
-#define ESDHC_FLAG_ERR010450 BIT(10)
-#define ESDHC_FLAG_HS400_ES BIT(11)
-
struct fsl_esdhc_cfg {
phys_addr_t esdhc_base;
u32 sdhc_clk;
@@ -262,6 +205,10 @@
int fsl_esdhc_mmc_init(bd_t *bis);
int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg);
void fdt_fixup_esdhc(void *blob, bd_t *bd);
+#ifdef MMC_SUPPORTS_TUNING
+static inline int fsl_esdhc_execute_tuning(struct udevice *dev,
+ uint32_t opcode) {return 0; }
+#endif
#else
static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; }
static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {}
diff --git a/include/fsl_esdhc_imx.h b/include/fsl_esdhc_imx.h
new file mode 100644
index 0000000..33c6d52
--- /dev/null
+++ b/include/fsl_esdhc_imx.h
@@ -0,0 +1,271 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * FSL SD/MMC Defines
+ *-------------------------------------------------------------------
+ *
+ * Copyright 2019 NXP
+ * Yangbo Lu <yangbo.lu@nxp.com>
+ *
+ * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc
+ */
+
+#ifndef __FSL_ESDHC_IMX_H__
+#define __FSL_ESDHC_IMX_H__
+
+#include <linux/bitops.h>
+#include <linux/errno.h>
+#include <asm/byteorder.h>
+
+/* needed for the mmc_cfg definition */
+#include <mmc.h>
+
+/* FSL eSDHC-specific constants */
+#define SYSCTL 0x0002e02c
+#define SYSCTL_INITA 0x08000000
+#define SYSCTL_TIMEOUT_MASK 0x000f0000
+#define SYSCTL_CLOCK_MASK 0x0000fff0
+#if !defined(CONFIG_FSL_USDHC)
+#define SYSCTL_CKEN 0x00000008
+#define SYSCTL_PEREN 0x00000004
+#define SYSCTL_HCKEN 0x00000002
+#define SYSCTL_IPGEN 0x00000001
+#endif
+#define SYSCTL_RSTA 0x01000000
+#define SYSCTL_RSTC 0x02000000
+#define SYSCTL_RSTD 0x04000000
+
+#define VENDORSPEC_CKEN 0x00004000
+#define VENDORSPEC_PEREN 0x00002000
+#define VENDORSPEC_HCKEN 0x00001000
+#define VENDORSPEC_IPGEN 0x00000800
+#define VENDORSPEC_INIT 0x20007809
+
+#define IRQSTAT 0x0002e030
+#define IRQSTAT_DMAE (0x10000000)
+#define IRQSTAT_AC12E (0x01000000)
+#define IRQSTAT_DEBE (0x00400000)
+#define IRQSTAT_DCE (0x00200000)
+#define IRQSTAT_DTOE (0x00100000)
+#define IRQSTAT_CIE (0x00080000)
+#define IRQSTAT_CEBE (0x00040000)
+#define IRQSTAT_CCE (0x00020000)
+#define IRQSTAT_CTOE (0x00010000)
+#define IRQSTAT_CINT (0x00000100)
+#define IRQSTAT_CRM (0x00000080)
+#define IRQSTAT_CINS (0x00000040)
+#define IRQSTAT_BRR (0x00000020)
+#define IRQSTAT_BWR (0x00000010)
+#define IRQSTAT_DINT (0x00000008)
+#define IRQSTAT_BGE (0x00000004)
+#define IRQSTAT_TC (0x00000002)
+#define IRQSTAT_CC (0x00000001)
+
+#define CMD_ERR (IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE)
+#define DATA_ERR (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE | \
+ IRQSTAT_DMAE)
+#define DATA_COMPLETE (IRQSTAT_TC | IRQSTAT_DINT)
+
+#define IRQSTATEN 0x0002e034
+#define IRQSTATEN_DMAE (0x10000000)
+#define IRQSTATEN_AC12E (0x01000000)
+#define IRQSTATEN_DEBE (0x00400000)
+#define IRQSTATEN_DCE (0x00200000)
+#define IRQSTATEN_DTOE (0x00100000)
+#define IRQSTATEN_CIE (0x00080000)
+#define IRQSTATEN_CEBE (0x00040000)
+#define IRQSTATEN_CCE (0x00020000)
+#define IRQSTATEN_CTOE (0x00010000)
+#define IRQSTATEN_CINT (0x00000100)
+#define IRQSTATEN_CRM (0x00000080)
+#define IRQSTATEN_CINS (0x00000040)
+#define IRQSTATEN_BRR (0x00000020)
+#define IRQSTATEN_BWR (0x00000010)
+#define IRQSTATEN_DINT (0x00000008)
+#define IRQSTATEN_BGE (0x00000004)
+#define IRQSTATEN_TC (0x00000002)
+#define IRQSTATEN_CC (0x00000001)
+
+#define ESDHCCTL 0x0002e40c
+#define ESDHCCTL_PCS (0x00080000)
+
+#define PRSSTAT 0x0002e024
+#define PRSSTAT_DAT0 (0x01000000)
+#define PRSSTAT_CLSL (0x00800000)
+#define PRSSTAT_WPSPL (0x00080000)
+#define PRSSTAT_CDPL (0x00040000)
+#define PRSSTAT_CINS (0x00010000)
+#define PRSSTAT_BREN (0x00000800)
+#define PRSSTAT_BWEN (0x00000400)
+#define PRSSTAT_SDSTB (0X00000008)
+#define PRSSTAT_DLA (0x00000004)
+#define PRSSTAT_CICHB (0x00000002)
+#define PRSSTAT_CIDHB (0x00000001)
+
+#define PROCTL 0x0002e028
+#define PROCTL_INIT 0x00000020
+#define PROCTL_DTW_4 0x00000002
+#define PROCTL_DTW_8 0x00000004
+#define PROCTL_D3CD 0x00000008
+
+#define CMDARG 0x0002e008
+
+#define XFERTYP 0x0002e00c
+#define XFERTYP_CMD(x) ((x & 0x3f) << 24)
+#define XFERTYP_CMDTYP_NORMAL 0x0
+#define XFERTYP_CMDTYP_SUSPEND 0x00400000
+#define XFERTYP_CMDTYP_RESUME 0x00800000
+#define XFERTYP_CMDTYP_ABORT 0x00c00000
+#define XFERTYP_DPSEL 0x00200000
+#define XFERTYP_CICEN 0x00100000
+#define XFERTYP_CCCEN 0x00080000
+#define XFERTYP_RSPTYP_NONE 0
+#define XFERTYP_RSPTYP_136 0x00010000
+#define XFERTYP_RSPTYP_48 0x00020000
+#define XFERTYP_RSPTYP_48_BUSY 0x00030000
+#define XFERTYP_MSBSEL 0x00000020
+#define XFERTYP_DTDSEL 0x00000010
+#define XFERTYP_DDREN 0x00000008
+#define XFERTYP_AC12EN 0x00000004
+#define XFERTYP_BCEN 0x00000002
+#define XFERTYP_DMAEN 0x00000001
+
+#define CINS_TIMEOUT 1000
+#define PIO_TIMEOUT 500
+
+#define DSADDR 0x2e004
+
+#define CMDRSP0 0x2e010
+#define CMDRSP1 0x2e014
+#define CMDRSP2 0x2e018
+#define CMDRSP3 0x2e01c
+
+#define DATPORT 0x2e020
+
+#define WML 0x2e044
+#define WML_WRITE 0x00010000
+#ifdef CONFIG_FSL_SDHC_V2_3
+#define WML_RD_WML_MAX 0x80
+#define WML_WR_WML_MAX 0x80
+#define WML_RD_WML_MAX_VAL 0x0
+#define WML_WR_WML_MAX_VAL 0x0
+#define WML_RD_WML_MASK 0x7f
+#define WML_WR_WML_MASK 0x7f0000
+#else
+#define WML_RD_WML_MAX 0x10
+#define WML_WR_WML_MAX 0x80
+#define WML_RD_WML_MAX_VAL 0x10
+#define WML_WR_WML_MAX_VAL 0x80
+#define WML_RD_WML_MASK 0xff
+#define WML_WR_WML_MASK 0xff0000
+#endif
+
+#define BLKATTR 0x2e004
+#define BLKATTR_CNT(x) ((x & 0xffff) << 16)
+#define BLKATTR_SIZE(x) (x & 0x1fff)
+#define MAX_BLK_CNT 0x7fff /* so malloc will have enough room with 32M */
+
+#define ESDHC_HOSTCAPBLT_VS18 0x04000000
+#define ESDHC_HOSTCAPBLT_VS30 0x02000000
+#define ESDHC_HOSTCAPBLT_VS33 0x01000000
+#define ESDHC_HOSTCAPBLT_SRS 0x00800000
+#define ESDHC_HOSTCAPBLT_DMAS 0x00400000
+#define ESDHC_HOSTCAPBLT_HSS 0x00200000
+
+#define ESDHC_VENDORSPEC_VSELECT 0x00000002 /* Use 1.8V */
+
+/* Imported from Linux Kernel drivers/mmc/host/sdhci-esdhc-imx.c */
+#define MIX_CTRL_DDREN BIT(3)
+#define MIX_CTRL_DTDSEL_READ BIT(4)
+#define MIX_CTRL_AC23EN BIT(7)
+#define MIX_CTRL_EXE_TUNE BIT(22)
+#define MIX_CTRL_SMPCLK_SEL BIT(23)
+#define MIX_CTRL_AUTO_TUNE_EN BIT(24)
+#define MIX_CTRL_FBCLK_SEL BIT(25)
+#define MIX_CTRL_HS400_EN BIT(26)
+#define MIX_CTRL_HS400_ES BIT(27)
+/* Bits 3 and 6 are not SDHCI standard definitions */
+#define MIX_CTRL_SDHCI_MASK 0xb7
+/* Tuning bits */
+#define MIX_CTRL_TUNING_MASK 0x03c00000
+
+/* strobe dll register */
+#define ESDHC_STROBE_DLL_CTRL 0x70
+#define ESDHC_STROBE_DLL_CTRL_ENABLE BIT(0)
+#define ESDHC_STROBE_DLL_CTRL_RESET BIT(1)
+#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT 0x7
+#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
+
+#define ESDHC_STROBE_DLL_STATUS 0x74
+#define ESDHC_STROBE_DLL_STS_REF_LOCK BIT(1)
+#define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1
+#define ESDHC_STROBE_DLL_CLK_FREQ 100000000
+
+#define ESDHC_STD_TUNING_EN BIT(24)
+/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
+#define ESDHC_TUNING_START_TAP_DEFAULT 0x1
+#define ESDHC_TUNING_START_TAP_MASK 0xff
+#define ESDHC_TUNING_STEP_MASK 0x00070000
+#define ESDHC_TUNING_STEP_SHIFT 16
+
+#define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1)
+#define ESDHC_FLAG_ENGCM07207 BIT(2)
+#define ESDHC_FLAG_USDHC BIT(3)
+#define ESDHC_FLAG_MAN_TUNING BIT(4)
+#define ESDHC_FLAG_STD_TUNING BIT(5)
+#define ESDHC_FLAG_HAVE_CAP1 BIT(6)
+#define ESDHC_FLAG_ERR004536 BIT(7)
+#define ESDHC_FLAG_HS200 BIT(8)
+#define ESDHC_FLAG_HS400 BIT(9)
+#define ESDHC_FLAG_ERR010450 BIT(10)
+#define ESDHC_FLAG_HS400_ES BIT(11)
+
+struct fsl_esdhc_cfg {
+ phys_addr_t esdhc_base;
+ u32 sdhc_clk;
+ u8 max_bus_width;
+ int wp_enable;
+ int vs18_enable; /* Use 1.8V if set to 1 */
+ struct mmc_config cfg;
+};
+
+/* Select the correct accessors depending on endianess */
+#if defined CONFIG_SYS_FSL_ESDHC_LE
+#define esdhc_read32 in_le32
+#define esdhc_write32 out_le32
+#define esdhc_clrsetbits32 clrsetbits_le32
+#define esdhc_clrbits32 clrbits_le32
+#define esdhc_setbits32 setbits_le32
+#elif defined(CONFIG_SYS_FSL_ESDHC_BE)
+#define esdhc_read32 in_be32
+#define esdhc_write32 out_be32
+#define esdhc_clrsetbits32 clrsetbits_be32
+#define esdhc_clrbits32 clrbits_be32
+#define esdhc_setbits32 setbits_be32
+#elif __BYTE_ORDER == __LITTLE_ENDIAN
+#define esdhc_read32 in_le32
+#define esdhc_write32 out_le32
+#define esdhc_clrsetbits32 clrsetbits_le32
+#define esdhc_clrbits32 clrbits_le32
+#define esdhc_setbits32 setbits_le32
+#elif __BYTE_ORDER == __BIG_ENDIAN
+#define esdhc_read32 in_be32
+#define esdhc_write32 out_be32
+#define esdhc_clrsetbits32 clrsetbits_be32
+#define esdhc_clrbits32 clrbits_be32
+#define esdhc_setbits32 setbits_be32
+#else
+#error "Endianess is not defined: please fix to continue"
+#endif
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+int fsl_esdhc_mmc_init(bd_t *bis);
+int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg);
+void fdt_fixup_esdhc(void *blob, bd_t *bd);
+#else
+static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; }
+static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {}
+#endif /* CONFIG_FSL_ESDHC_IMX */
+void __noreturn mmc_boot(void);
+void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst);
+
+#endif /* __FSL_ESDHC_IMX_H__ */
diff --git a/include/gzip.h b/include/gzip.h
new file mode 100644
index 0000000..2e34067
--- /dev/null
+++ b/include/gzip.h
@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2000-2009
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#ifndef __GZIP_H
+#define __GZIP_H
+
+/**
+ * gzip_parse_header() - Parse a header from a gzip file
+ *
+ * This returns the length of the header.
+ *
+ * @src: Pointer to gzip file
+ * @len: Length of data
+ * @return length of header in bytes, or -1 if not enough data
+ */
+int gzip_parse_header(const unsigned char *src, unsigned long len);
+
+/**
+ * gunzip() - Decompress gzipped data
+ *
+ * @dst: Destination for uncompressed data
+ * @dstlen: Size of destination buffer
+ * @src: Source data to decompress
+ * @lenp: Returns length of uncompressed data
+ * @return 0 if OK, -1 on error
+ */
+int gunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp);
+
+/**
+ * zunzip() - Uncompress blocks compressed with zlib without headers
+ *
+ * @dst: Destination for uncompressed data
+ * @dstlen: Size of destination buffer
+ * @src: Source data to decompress
+ * @lenp: On entry, length data at @src. On exit, number of bytes used from @src
+ * @stoponerr: 0 to continue when a decode error is found, 1 to stop
+ * @offset: start offset within the src buffer
+ * @return 0 if OK, -1 on error
+ */
+int zunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp,
+ int stoponerr, int offset);
+
+/**
+ * gzwrite progress indicators: defined weak to allow board-specific
+ * overrides:
+ *
+ * gzwrite_progress_init called on startup
+ * gzwrite_progress called during decompress/write loop
+ * gzwrite_progress_finish called at end of loop to
+ * indicate success (retcode=0) or failure
+ */
+void gzwrite_progress_init(u64 expected_size);
+
+void gzwrite_progress(int iteration, u64 bytes_written, u64 total_bytes);
+
+void gzwrite_progress_finish(int retcode, u64 totalwritten, u64 totalsize,
+ u32 expected_crc, u32 calculated_crc);
+
+/**
+ * gzwrite() - decompress and write gzipped image from memory to block device
+ *
+ * @src: compressed image address
+ * @len: compressed image length in bytes
+ * @dev: block device descriptor
+ * @szwritebuf: bytes per write (pad to erase size)
+ * @startoffs: offset in bytes of first write
+ * @szexpected: expected uncompressed length, may be zero to use gzip trailer
+ * for files under 4GiB
+ * @return 0 if OK, -1 on error
+ */
+int gzwrite(unsigned char *src, int len, struct blk_desc *dev, ulong szwritebuf,
+ u64 startoffs, u64 szexpected);
+
+/**
+ * gzip()- Compress data into a buffer using the gzip algorithm
+ *
+ * @dst: Destination buffer for compressed data
+ * @lenp: On entry, space available in destination buffer (in bytes). On exit,
+ * number of bytes used in the buffer
+ * @src: Source data to compress
+ * @srclen: Size of source data
+ * @return 0 if OK, -1 on error
+ */
+int gzip(void *dst, unsigned long *lenp, unsigned char *src, ulong srclen);
+
+/**
+ * zzip() - Compress blocks with zlib
+ *
+ * @dst: Destination for compressed data
+ * @lenp: On entry, length data at @dst. On exit, number of bytes written to
+ * @dst
+ * @src: Source data to compress
+ * @srclen: Size of source data
+ * @stoponerr: 0 to continue when a decode error is found, 1 to stop
+ * @func: Some sort of function that is called to do something. !ADD DOCS HERE!
+ */
+int zzip(void *dst, ulong *lenp, unsigned char *src, ulong srclen,
+ int stoponerr, int (*func)(ulong, ulong));
+
+#endif
diff --git a/include/i2c.h b/include/i2c.h
index a5c760c..33570f5 100644
--- a/include/i2c.h
+++ b/include/i2c.h
@@ -271,86 +271,6 @@
*/
int i2c_deblock(struct udevice *bus);
-#ifdef CONFIG_DM_I2C_COMPAT
-/**
- * i2c_probe() - Compatibility function for driver model
- *
- * Calls dm_i2c_probe() on the current bus
- */
-int i2c_probe(uint8_t chip_addr);
-
-/**
- * i2c_read() - Compatibility function for driver model
- *
- * Calls dm_i2c_read() with the device corresponding to @chip_addr, and offset
- * set to @addr. @alen must match the current setting for the device.
- */
-int i2c_read(uint8_t chip_addr, unsigned int addr, int alen, uint8_t *buffer,
- int len);
-
-/**
- * i2c_write() - Compatibility function for driver model
- *
- * Calls dm_i2c_write() with the device corresponding to @chip_addr, and offset
- * set to @addr. @alen must match the current setting for the device.
- */
-int i2c_write(uint8_t chip_addr, unsigned int addr, int alen, uint8_t *buffer,
- int len);
-
-/**
- * i2c_get_bus_num_fdt() - Compatibility function for driver model
- *
- * @return the bus number associated with the given device tree node
- */
-int i2c_get_bus_num_fdt(int node);
-
-/**
- * i2c_get_bus_num() - Compatibility function for driver model
- *
- * @return the 'current' bus number
- */
-unsigned int i2c_get_bus_num(void);
-
-/**
- * i2c_set_bus_num() - Compatibility function for driver model
- *
- * Sets the 'current' bus
- */
-int i2c_set_bus_num(unsigned int bus);
-
-static inline void I2C_SET_BUS(unsigned int bus)
-{
- i2c_set_bus_num(bus);
-}
-
-static inline unsigned int I2C_GET_BUS(void)
-{
- return i2c_get_bus_num();
-}
-
-/**
- * i2c_init() - Compatibility function for driver model
- *
- * This function does nothing.
- */
-void i2c_init(int speed, int slaveaddr);
-
-/**
- * board_i2c_init() - Compatibility function for driver model
- *
- * @param blob Device tree blbo
- * @return the number of I2C bus
- */
-void board_i2c_init(const void *blob);
-
-/*
- * Compatibility functions for driver model.
- */
-uint8_t i2c_reg_read(uint8_t addr, uint8_t reg);
-void i2c_reg_write(uint8_t addr, uint8_t reg, uint8_t val);
-
-#endif
-
/**
* struct dm_i2c_ops - driver operations for I2C uclass
*
diff --git a/include/image.h b/include/image.h
index bb7089e..c1065c0 100644
--- a/include/image.h
+++ b/include/image.h
@@ -156,6 +156,7 @@
IH_OS_OPENRTOS, /* OpenRTOS */
IH_OS_ARM_TRUSTED_FIRMWARE, /* ARM Trusted Firmware */
IH_OS_TEE, /* Trusted Execution Environment */
+ IH_OS_OPENSBI, /* RISC-V OpenSBI */
IH_OS_COUNT,
};
@@ -283,6 +284,7 @@
IH_TYPE_MTKIMAGE, /* MediaTek BootROM loadable Image */
IH_TYPE_IMX8MIMAGE, /* Freescale IMX8MBoot Image */
IH_TYPE_IMX8IMAGE, /* Freescale IMX8Boot Image */
+ IH_TYPE_COPRO, /* Coprocessor Image for remoteproc*/
IH_TYPE_COUNT, /* Number of image types */
};
@@ -561,7 +563,7 @@
#ifndef USE_HOSTCC
/* Image format types, returned by _get_format() routine */
#define IMAGE_FORMAT_INVALID 0x00
-#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
+#if defined(CONFIG_LEGACY_IMAGE_FORMAT)
#define IMAGE_FORMAT_LEGACY 0x01 /* legacy image_header based format */
#endif
#define IMAGE_FORMAT_FIT 0x02 /* new, libfdt based format */
@@ -850,6 +852,23 @@
#endif /* USE_HOSTCC */
/**
+ * image_decomp() - decompress an image
+ *
+ * @comp: Compression algorithm that is used (IH_COMP_...)
+ * @load: Destination load address in U-Boot memory
+ * @image_start Image start address (where we are decompressing from)
+ * @type: OS type (IH_OS_...)
+ * @load_bug: Place to decompress to
+ * @image_buf: Address to decompress from
+ * @image_len: Number of bytes in @image_buf to decompress
+ * @unc_len: Available space for decompression
+ * @return 0 if OK, -ve on error (BOOTM_ERR_...)
+ */
+int image_decomp(int comp, ulong load, ulong image_start, int type,
+ void *load_buf, void *image_buf, ulong image_len,
+ uint unc_len, ulong *load_end);
+
+/**
* Set up properties in the FDT
*
* This sets up properties in the FDT that is to be passed to linux.
diff --git a/include/initcall.h b/include/initcall.h
index 78d15af..b5acdd0 100644
--- a/include/initcall.h
+++ b/include/initcall.h
@@ -30,11 +30,13 @@
#ifdef CONFIG_EFI_APP
reloc_ofs = (unsigned long)image_base;
#endif
- debug("initcall: %p", (char *)*init_fnc_ptr - reloc_ofs);
if (reloc_ofs)
- debug(" (relocated to %p)\n", (char *)*init_fnc_ptr);
+ debug("initcall: %p (relocated to %p)\n",
+ (char *)*init_fnc_ptr - reloc_ofs,
+ (char *)*init_fnc_ptr);
else
- debug("\n");
+ debug("initcall: %p\n", (char *)*init_fnc_ptr - reloc_ofs);
+
ret = (*init_fnc_ptr)();
if (ret) {
printf("initcall sequence %p failed at call %p (err=%d)\n",
diff --git a/include/lcd.h b/include/lcd.h
index cb6b6a4..9a4c0da 100644
--- a/include/lcd.h
+++ b/include/lcd.h
@@ -30,6 +30,7 @@
void lcd_ctrl_init(void *lcdbase);
void lcd_enable(void);
void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue);
+ulong lcd_setmem(ulong addr);
/**
* Set whether we need to flush the dcache when changing the LCD image. This
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
new file mode 100644
index 0000000..02ff1a3
--- /dev/null
+++ b/include/linux/clk-provider.h
@@ -0,0 +1,190 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
+ * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
+ */
+#ifndef __LINUX_CLK_PROVIDER_H
+#define __LINUX_CLK_PROVIDER_H
+#include <clk-uclass.h>
+
+static inline void clk_dm(ulong id, struct clk *clk)
+{
+ if (!IS_ERR(clk))
+ clk->id = id;
+}
+
+/*
+ * flags used across common struct clk. these flags should only affect the
+ * top-level framework. custom flags for dealing with hardware specifics
+ * belong in struct clk_foo
+ *
+ * Please update clk_flags[] in drivers/clk/clk.c when making changes here!
+ */
+#define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
+#define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
+#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
+#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
+ /* unused */
+#define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */
+#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
+#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
+#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
+#define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
+#define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
+#define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
+/* parents need enable during gate/ungate, set rate and re-parent */
+#define CLK_OPS_PARENT_ENABLE BIT(12)
+/* duty cycle call may be forwarded to the parent clock */
+#define CLK_DUTY_CYCLE_PARENT BIT(13)
+
+#define CLK_MUX_INDEX_ONE BIT(0)
+#define CLK_MUX_INDEX_BIT BIT(1)
+#define CLK_MUX_HIWORD_MASK BIT(2)
+#define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
+#define CLK_MUX_ROUND_CLOSEST BIT(4)
+
+struct clk_mux {
+ struct clk clk;
+ void __iomem *reg;
+ u32 *table;
+ u32 mask;
+ u8 shift;
+ u8 flags;
+
+ /*
+ * Fields from struct clk_init_data - this struct has been
+ * omitted to avoid too deep level of CCF for bootloader
+ */
+ const char * const *parent_names;
+ u8 num_parents;
+#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+ u32 io_mux_val;
+#endif
+
+};
+
+#define to_clk_mux(_clk) container_of(_clk, struct clk_mux, clk)
+extern const struct clk_ops clk_mux_ops;
+u8 clk_mux_get_parent(struct clk *clk);
+
+struct clk_gate {
+ struct clk clk;
+ void __iomem *reg;
+ u8 bit_idx;
+ u8 flags;
+#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+ u32 io_gate_val;
+#endif
+};
+
+#define to_clk_gate(_clk) container_of(_clk, struct clk_gate, clk)
+
+#define CLK_GATE_SET_TO_DISABLE BIT(0)
+#define CLK_GATE_HIWORD_MASK BIT(1)
+
+extern const struct clk_ops clk_gate_ops;
+struct clk *clk_register_gate(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ void __iomem *reg, u8 bit_idx,
+ u8 clk_gate_flags, spinlock_t *lock);
+
+struct clk_div_table {
+ unsigned int val;
+ unsigned int div;
+};
+
+struct clk_divider {
+ struct clk clk;
+ void __iomem *reg;
+ u8 shift;
+ u8 width;
+ u8 flags;
+ const struct clk_div_table *table;
+#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+ u32 io_divider_val;
+#endif
+};
+
+#define clk_div_mask(width) ((1 << (width)) - 1)
+#define to_clk_divider(_clk) container_of(_clk, struct clk_divider, clk)
+
+#define CLK_DIVIDER_ONE_BASED BIT(0)
+#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
+#define CLK_DIVIDER_ALLOW_ZERO BIT(2)
+#define CLK_DIVIDER_HIWORD_MASK BIT(3)
+#define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
+#define CLK_DIVIDER_READ_ONLY BIT(5)
+#define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
+extern const struct clk_ops clk_divider_ops;
+unsigned long divider_recalc_rate(struct clk *hw, unsigned long parent_rate,
+ unsigned int val,
+ const struct clk_div_table *table,
+ unsigned long flags, unsigned long width);
+
+struct clk_fixed_factor {
+ struct clk clk;
+ unsigned int mult;
+ unsigned int div;
+};
+
+#define to_clk_fixed_factor(_clk) container_of(_clk, struct clk_fixed_factor,\
+ clk)
+
+struct clk_fixed_rate {
+ struct clk clk;
+ unsigned long fixed_rate;
+};
+
+#define to_clk_fixed_rate(dev) ((struct clk_fixed_rate *)dev_get_platdata(dev))
+
+struct clk_composite {
+ struct clk clk;
+ struct clk_ops ops;
+
+ struct clk *mux;
+ struct clk *rate;
+ struct clk *gate;
+
+ const struct clk_ops *mux_ops;
+ const struct clk_ops *rate_ops;
+ const struct clk_ops *gate_ops;
+};
+
+#define to_clk_composite(_clk) container_of(_clk, struct clk_composite, clk)
+
+struct clk *clk_register_composite(struct device *dev, const char *name,
+ const char * const *parent_names, int num_parents,
+ struct clk *mux_clk, const struct clk_ops *mux_ops,
+ struct clk *rate_clk, const struct clk_ops *rate_ops,
+ struct clk *gate_clk, const struct clk_ops *gate_ops,
+ unsigned long flags);
+
+int clk_register(struct clk *clk, const char *drv_name, const char *name,
+ const char *parent_name);
+
+struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ unsigned int mult, unsigned int div);
+
+struct clk *clk_register_divider(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ void __iomem *reg, u8 shift, u8 width,
+ u8 clk_divider_flags);
+
+struct clk *clk_register_mux(struct device *dev, const char *name,
+ const char * const *parent_names, u8 num_parents,
+ unsigned long flags,
+ void __iomem *reg, u8 shift, u8 width,
+ u8 clk_mux_flags);
+
+const char *clk_hw_get_name(const struct clk *hw);
+ulong clk_generic_get_rate(struct clk *clk);
+
+static inline struct clk *dev_get_clk_ptr(struct udevice *dev)
+{
+ return (struct clk *)dev_get_uclass_priv(dev);
+}
+#endif /* __LINUX_CLK_PROVIDER_H */
diff --git a/include/linux/clk/analogbits-wrpll-cln28hpc.h b/include/linux/clk/analogbits-wrpll-cln28hpc.h
new file mode 100644
index 0000000..0327909
--- /dev/null
+++ b/include/linux/clk/analogbits-wrpll-cln28hpc.h
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018-2019 SiFive, Inc.
+ * Wesley Terpstra
+ * Paul Walmsley
+ */
+
+#ifndef __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H
+#define __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H
+
+#include <linux/types.h>
+
+/* DIVQ_VALUES: number of valid DIVQ values */
+#define DIVQ_VALUES 6
+
+/*
+ * Bit definitions for struct wrpll_cfg.flags
+ *
+ * WRPLL_FLAGS_BYPASS_FLAG: if set, the PLL is either in bypass, or should be
+ * programmed to enter bypass
+ * WRPLL_FLAGS_RESET_FLAG: if set, the PLL is in reset
+ * WRPLL_FLAGS_INT_FEEDBACK_FLAG: if set, the PLL is configured for internal
+ * feedback mode
+ * WRPLL_FLAGS_EXT_FEEDBACK_FLAG: if set, the PLL is configured for external
+ * feedback mode (not yet supported by this driver)
+ */
+#define WRPLL_FLAGS_BYPASS_SHIFT 0
+#define WRPLL_FLAGS_BYPASS_MASK BIT(WRPLL_FLAGS_BYPASS_SHIFT)
+#define WRPLL_FLAGS_RESET_SHIFT 1
+#define WRPLL_FLAGS_RESET_MASK BIT(WRPLL_FLAGS_RESET_SHIFT)
+#define WRPLL_FLAGS_INT_FEEDBACK_SHIFT 2
+#define WRPLL_FLAGS_INT_FEEDBACK_MASK BIT(WRPLL_FLAGS_INT_FEEDBACK_SHIFT)
+#define WRPLL_FLAGS_EXT_FEEDBACK_SHIFT 3
+#define WRPLL_FLAGS_EXT_FEEDBACK_MASK BIT(WRPLL_FLAGS_EXT_FEEDBACK_SHIFT)
+
+/**
+ * struct wrpll_cfg - WRPLL configuration values
+ * @divr: reference divider value (6 bits), as presented to the PLL signals
+ * @divf: feedback divider value (9 bits), as presented to the PLL signals
+ * @divq: output divider value (3 bits), as presented to the PLL signals
+ * @flags: PLL configuration flags. See above for more information
+ * @range: PLL loop filter range. See below for more information
+ * @output_rate_cache: cached output rates, swept across DIVQ
+ * @parent_rate: PLL refclk rate for which values are valid
+ * @max_r: maximum possible R divider value, given @parent_rate
+ * @init_r: initial R divider value to start the search from
+ *
+ * @divr, @divq, @divq, @range represent what the PLL expects to see
+ * on its input signals. Thus @divr and @divf are the actual divisors
+ * minus one. @divq is a power-of-two divider; for example, 1 =
+ * divide-by-2 and 6 = divide-by-64. 0 is an invalid @divq value.
+ *
+ * When initially passing a struct wrpll_cfg record, the
+ * record should be zero-initialized with the exception of the @flags
+ * field. The only flag bits that need to be set are either
+ * WRPLL_FLAGS_INT_FEEDBACK or WRPLL_FLAGS_EXT_FEEDBACK.
+ */
+struct wrpll_cfg {
+ u8 divr;
+ u8 divq;
+ u8 range;
+ u8 flags;
+ u16 divf;
+/* private: */
+ u32 output_rate_cache[DIVQ_VALUES];
+ unsigned long parent_rate;
+ u8 max_r;
+ u8 init_r;
+};
+
+int wrpll_configure_for_rate(struct wrpll_cfg *c, u32 target_rate,
+ unsigned long parent_rate);
+
+unsigned int wrpll_calc_max_lock_us(const struct wrpll_cfg *c);
+
+unsigned long wrpll_calc_output_rate(const struct wrpll_cfg *c,
+ unsigned long parent_rate);
+
+#endif /* __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H */
diff --git a/include/linux/kconfig.h b/include/linux/kconfig.h
index fbfc718..3a2da73 100644
--- a/include/linux/kconfig.h
+++ b/include/linux/kconfig.h
@@ -75,6 +75,7 @@
* CONFIG_VAL(FOO) evaluates to the value of
* CONFIG_FOO if CONFIG_SPL_BUILD is undefined,
* CONFIG_SPL_FOO if CONFIG_SPL_BUILD is defined.
+ * CONFIG_TPL_FOO if CONFIG_TPL_BUILD is defined.
*/
#define CONFIG_VAL(option) config_val(option)
@@ -82,6 +83,7 @@
* CONFIG_IS_ENABLED(FOO) evaluates to
* 1 if CONFIG_SPL_BUILD is undefined and CONFIG_FOO is set to 'y' or 'm',
* 1 if CONFIG_SPL_BUILD is defined and CONFIG_SPL_FOO is set to 'y' or 'm',
+ * 1 if CONFIG_TPL_BUILD is defined and CONFIG_TPL_FOO is set to 'y' or 'm',
* 0 otherwise.
*/
#define CONFIG_IS_ENABLED(option) \
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 88e80af..709b49d 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -91,6 +91,10 @@
#define SPINOR_OP_WRDI 0x04 /* Write disable */
#define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
+/* Used for SST26* flashes only. */
+#define SPINOR_OP_READ_BPR 0x72 /* Read block protection register */
+#define SPINOR_OP_WRITE_BPR 0x42 /* Write block protection register */
+
/* Used for S3AN flashes only */
#define SPINOR_OP_XSE 0x50 /* Sector erase */
#define SPINOR_OP_XPP 0x82 /* Page program */
diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h
index c57802f..1cba8d9 100644
--- a/include/linux/soc/ti/ti_sci_protocol.h
+++ b/include/linux/soc/ti/ti_sci_protocol.h
@@ -105,6 +105,9 @@
* -reset_state: pointer to u32 which will retrieve resets
* Returns 0 for successful request, else returns
* corresponding error message.
+ * @release_exclusive_devices: Command to release all the exclusive devices
+ * attached to this host. This should be used very carefully
+ * and only at the end of execution of your software.
*
* NOTE: for all these functions, the following parameters are generic in
* nature:
@@ -117,7 +120,10 @@
*/
struct ti_sci_dev_ops {
int (*get_device)(const struct ti_sci_handle *handle, u32 id);
+ int (*get_device_exclusive)(const struct ti_sci_handle *handle, u32 id);
int (*idle_device)(const struct ti_sci_handle *handle, u32 id);
+ int (*idle_device_exclusive)(const struct ti_sci_handle *handle,
+ u32 id);
int (*put_device)(const struct ti_sci_handle *handle, u32 id);
int (*is_valid)(const struct ti_sci_handle *handle, u32 id);
int (*get_context_loss_count)(const struct ti_sci_handle *handle,
@@ -134,6 +140,7 @@
u32 reset_state);
int (*get_device_resets)(const struct ti_sci_handle *handle, u32 id,
u32 *reset_state);
+ int (*release_exclusive_devices)(const struct ti_sci_handle *handle);
};
/**
@@ -263,6 +270,8 @@
* @set_proc_boot_ctrl: Setup limited control flags in specific cases.
* @proc_auth_boot_image:
* @get_proc_boot_status: Get the state of physical processor
+ * @proc_shutdown_no_wait: Shutdown a core without requesting or waiting for a
+ * response.
*
* NOTE: for all these functions, the following parameters are generic in
* nature:
@@ -284,6 +293,8 @@
int (*get_proc_boot_status)(const struct ti_sci_handle *handle, u8 pid,
u64 *bv, u32 *cfg_flags, u32 *ctrl_flags,
u32 *sts_flags);
+ int (*proc_shutdown_no_wait)(const struct ti_sci_handle *handle,
+ u8 pid);
};
#define TI_SCI_RING_MODE_RING (0)
diff --git a/include/log.h b/include/log.h
index 7566ba7..6d15e95 100644
--- a/include/log.h
+++ b/include/log.h
@@ -183,6 +183,18 @@
*/
void __assert_fail(const char *assertion, const char *file, unsigned int line,
const char *function);
+
+/**
+ * assert() - assert expression is true
+ *
+ * If the expression x evaluates to false and _DEBUG evaluates to true, a panic
+ * message is written and the system stalls. The value of _DEBUG is set to true
+ * if DEBUG is defined before including common.h.
+ *
+ * The expression x is always executed irrespective of the value of _DEBUG.
+ *
+ * @x: expression to test
+ */
#define assert(x) \
({ if (!(x) && _DEBUG) \
__assert_fail(#x, __FILE__, __LINE__, __func__); })
diff --git a/include/menu.h b/include/menu.h
index fbff429..2d227c2 100644
--- a/include/menu.h
+++ b/include/menu.h
@@ -19,7 +19,20 @@
void menu_display_statusline(struct menu *m);
int menu_default_choice(struct menu *m, void **choice);
-#if defined(CONFIG_MENU_SHOW)
+/**
+ * menu_show() Show a boot menu
+ *
+ * This shows a menu and lets the user select an option. The menu is defined by
+ * environment variables (see README.bootmenu).
+ *
+ * This function doesn't normally return, but if the users requests the command
+ * problem, it will.
+ *
+ * @bootdelay: Delay to wait before running the default menu option (0 to run
+ * the entry immediately)
+ * @return If it returns, it always returns -1 to indicate that the boot should
+ * be aborted and the command prompt should be provided
+ */
int menu_show(int bootdelay);
-#endif
+
#endif /* __MENU_H__ */
diff --git a/include/miiphy.h b/include/miiphy.h
index f11763a..9b97d09 100644
--- a/include/miiphy.h
+++ b/include/miiphy.h
@@ -118,4 +118,73 @@
#define ESTATUS_1000XF 0x8000
#define ESTATUS_1000XH 0x4000
+#ifdef CONFIG_DM_MDIO
+
+/**
+ * struct mdio_perdev_priv - Per-device class data for MDIO DM
+ *
+ * @mii_bus: Supporting MII legacy bus
+ */
+struct mdio_perdev_priv {
+ struct mii_dev *mii_bus;
+};
+
+/**
+ * struct mdio_ops - MDIO bus operations
+ *
+ * @read: Read from a PHY register
+ * @write: Write to a PHY register
+ * @reset: Reset the MDIO bus, NULL if not supported
+ */
+struct mdio_ops {
+ int (*read)(struct udevice *mdio_dev, int addr, int devad, int reg);
+ int (*write)(struct udevice *mdio_dev, int addr, int devad, int reg,
+ u16 val);
+ int (*reset)(struct udevice *mdio_dev);
+};
+
+#define mdio_get_ops(dev) ((struct mdio_ops *)(dev)->driver->ops)
+
+/**
+ * dm_mdio_probe_devices - Call probe on all MII devices, currently used for
+ * MDIO console commands.
+ */
+void dm_mdio_probe_devices(void);
+
+/**
+ * dm_mdio_phy_connect - Wrapper over phy_connect for DM MDIO
+ *
+ * @dev: mdio dev
+ * @addr: PHY address on MDIO bus
+ * @ethdev: ethernet device to connect to the PHY
+ * @interface: MAC-PHY protocol
+ *
+ * @return pointer to phy_device, or 0 on error
+ */
+struct phy_device *dm_mdio_phy_connect(struct udevice *dev, int addr,
+ struct udevice *ethdev,
+ phy_interface_t interface);
+
+#endif
+
+#ifdef CONFIG_DM_MDIO_MUX
+
+/* indicates none of the child buses is selected */
+#define MDIO_MUX_SELECT_NONE -1
+
+/**
+ * struct mdio_mux_ops - MDIO MUX operations
+ *
+ * @select: Selects a child bus
+ * @deselect: Clean up selection. Optional, can be NULL
+ */
+struct mdio_mux_ops {
+ int (*select)(struct udevice *mux, int cur, int sel);
+ int (*deselect)(struct udevice *mux, int sel);
+};
+
+#define mdio_mux_get_ops(dev) ((struct mdio_mux_ops *)(dev)->driver->ops)
+
+#endif
+
#endif
diff --git a/include/mmc.h b/include/mmc.h
index 1f30f71..686ba00 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -65,6 +65,11 @@
#define MMC_MODE_DDR_52MHz MMC_CAP(MMC_DDR_52)
#define MMC_MODE_HS200 MMC_CAP(MMC_HS_200)
#define MMC_MODE_HS400 MMC_CAP(MMC_HS_400)
+#define MMC_MODE_HS400_ES MMC_CAP(MMC_HS_400_ES)
+
+#define MMC_CAP_NONREMOVABLE BIT(14)
+#define MMC_CAP_NEEDS_POLL BIT(15)
+#define MMC_CAP_CD_ACTIVE_HIGH BIT(16)
#define MMC_MODE_8BIT BIT(30)
#define MMC_MODE_4BIT BIT(29)
@@ -219,13 +224,16 @@
#define EXT_CSD_BOOT_BUS_WIDTH 177
#define EXT_CSD_PART_CONF 179 /* R/W */
#define EXT_CSD_BUS_WIDTH 183 /* R/W */
+#define EXT_CSD_STROBE_SUPPORT 184 /* R/W */
#define EXT_CSD_HS_TIMING 185 /* R/W */
#define EXT_CSD_REV 192 /* RO */
#define EXT_CSD_CARD_TYPE 196 /* RO */
+#define EXT_CSD_PART_SWITCH_TIME 199 /* RO */
#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
#define EXT_CSD_BOOT_MULT 226 /* RO */
+#define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */
#define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
/*
@@ -260,11 +268,13 @@
#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
#define EXT_CSD_DDR_FLAG BIT(2) /* Flag for DDR mode */
+#define EXT_CSD_BUS_WIDTH_STROBE BIT(7) /* Enhanced strobe mode */
#define EXT_CSD_TIMING_LEGACY 0 /* no high speed */
#define EXT_CSD_TIMING_HS 1 /* HS */
#define EXT_CSD_TIMING_HS200 2 /* HS200 */
#define EXT_CSD_TIMING_HS400 3 /* HS400 */
+#define EXT_CSD_DRV_STR_SHIFT 4 /* Driver Strength shift */
#define EXT_CSD_BOOT_ACK_ENABLE (1 << 6)
#define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3)
@@ -415,14 +425,6 @@
int (*set_ios)(struct udevice *dev);
/**
- * send_init_stream() - send the initialization stream: 74 clock cycles
- * This is used after power up before sending the first command
- *
- * @dev: Device to update
- */
- void (*send_init_stream)(struct udevice *dev);
-
- /**
* get_cd() - See whether a card is present
*
* @dev: Device to check
@@ -449,17 +451,20 @@
int (*execute_tuning)(struct udevice *dev, uint opcode);
#endif
-#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
/**
* wait_dat0() - wait until dat0 is in the target state
* (CLK must be running during the wait)
*
* @dev: Device to check
* @state: target state
- * @timeout: timeout in us
+ * @timeout_us: timeout in us
* @return 0 if dat0 is in the target state, -ve on error
*/
- int (*wait_dat0)(struct udevice *dev, int state, int timeout);
+ int (*wait_dat0)(struct udevice *dev, int state, int timeout_us);
+
+#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
+ /* set_enhanced_strobe() - set HS400 enhanced strobe */
+ int (*set_enhanced_strobe)(struct udevice *dev);
#endif
};
@@ -468,19 +473,18 @@
int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
struct mmc_data *data);
int dm_mmc_set_ios(struct udevice *dev);
-void dm_mmc_send_init_stream(struct udevice *dev);
int dm_mmc_get_cd(struct udevice *dev);
int dm_mmc_get_wp(struct udevice *dev);
int dm_mmc_execute_tuning(struct udevice *dev, uint opcode);
-int dm_mmc_wait_dat0(struct udevice *dev, int state, int timeout);
+int dm_mmc_wait_dat0(struct udevice *dev, int state, int timeout_us);
/* Transition functions for compatibility */
int mmc_set_ios(struct mmc *mmc);
-void mmc_send_init_stream(struct mmc *mmc);
int mmc_getcd(struct mmc *mmc);
int mmc_getwp(struct mmc *mmc);
int mmc_execute_tuning(struct mmc *mmc, uint opcode);
-int mmc_wait_dat0(struct mmc *mmc, int state, int timeout);
+int mmc_wait_dat0(struct mmc *mmc, int state, int timeout_us);
+int mmc_set_enhanced_strobe(struct mmc *mmc);
#else
struct mmc_ops {
@@ -526,6 +530,7 @@
UHS_SDR104,
MMC_HS_200,
MMC_HS_400,
+ MMC_HS_400_ES,
MMC_MODES_END
};
@@ -544,6 +549,10 @@
else if (mode == MMC_HS_400)
return true;
#endif
+#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
+ else if (mode == MMC_HS_400_ES)
+ return true;
+#endif
else
return false;
}
@@ -593,6 +602,8 @@
u8 part_attr;
u8 wr_rel_set;
u8 part_config;
+ u8 gen_cmd6_time; /* units: 10 ms */
+ u8 part_switch_time; /* units: 10 ms */
uint tran_speed;
uint legacy_speed; /* speed for the legacy mode provided by the card */
uint read_bl_len;
@@ -828,7 +839,6 @@
#else
#define mmc_host_is_spi(mmc) 0
#endif
-struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
void board_mmc_power_init(void);
int board_mmc_init(bd_t *bis);
@@ -839,6 +849,9 @@
# endif
int mmc_get_env_dev(void);
+/* Minimum partition switch timeout in units of 10-milliseconds */
+#define MMC_MIN_PART_SWITCH_TIME 30 /* 300 ms */
+
/* Set block count limit because of 16 bit register limit on some hardware*/
#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
diff --git a/include/mvebu_mmc.h b/include/mvebu_mmc.h
index d51b1fe..7397165 100644
--- a/include/mvebu_mmc.h
+++ b/include/mvebu_mmc.h
@@ -222,13 +222,9 @@
#define MMC_CAP_SDIO_IRQ (1 << 3)
/* Talks only SPI protocols */
#define MMC_CAP_SPI (1 << 4)
-/* Needs polling for card-detection */
-#define MMC_CAP_NEEDS_POLL (1 << 5)
/* Can the host do 8 bit transfers */
#define MMC_CAP_8_BIT_DATA (1 << 6)
-/* Nonremovable e.g. eMMC */
-#define MMC_CAP_NONREMOVABLE (1 << 8)
/* Waits while card is busy */
#define MMC_CAP_WAIT_WHILE_BUSY (1 << 9)
/* Allow erase/trim commands */
diff --git a/drivers/mtd/nand/raw/mxs_nand.h b/include/mxs_nand.h
similarity index 100%
rename from drivers/mtd/nand/raw/mxs_nand.h
rename to include/mxs_nand.h
diff --git a/include/net.h b/include/net.h
index 44b3238..75a16e4 100644
--- a/include/net.h
+++ b/include/net.h
@@ -14,6 +14,7 @@
#include <asm/cache.h>
#include <asm/byteorder.h> /* for nton* / ntoh* stuff */
+#include <env.h>
#include <linux/if_ether.h>
#define DEBUG_LL_STATE 0 /* Link local state machine changes */
@@ -728,7 +729,7 @@
}
/* return ulong *in network byteorder* */
-static inline u32 net_read_u32(u32 *from)
+static inline u32 net_read_u32(void *from)
{
u32 l;
@@ -749,7 +750,7 @@
}
/* copy ulong */
-static inline void net_copy_u32(u32 *to, u32 *from)
+static inline void net_copy_u32(void *to, void *from)
{
memcpy((void *)to, (void *)from, sizeof(u32));
}
@@ -815,7 +816,7 @@
static inline void net_random_ethaddr(uchar *addr)
{
int i;
- unsigned int seed = get_timer(0);
+ unsigned int seed = get_ticks();
for (i = 0; i < 6; i++)
addr[i] = rand_r(&seed);
@@ -874,4 +875,15 @@
/**********************************************************************/
+/**
+ * eth_parse_enetaddr() - Parse a MAC address
+ *
+ * Convert a string MAC address
+ *
+ * @addr: MAC address in aa:bb:cc:dd:ee:ff format, where each part is a 2-digit
+ * hex value
+ * @enetaddr: Place to put MAC address (6 bytes)
+ */
+void eth_parse_enetaddr(const char *addr, uint8_t *enetaddr);
+
#endif /* __NET_H__ */
diff --git a/include/net/pcap.h b/include/net/pcap.h
new file mode 100644
index 0000000..512ba98
--- /dev/null
+++ b/include/net/pcap.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2019
+ * Ramon Fried <rfried.dev@gmail.com>
+ */
+
+/**
+ * pcap_init() - Initialize PCAP memory buffer
+ *
+ * @paddr physicaly memory address to store buffer
+ * @size maximum size of capture file in memory
+ *
+ * @return 0 on success, -ERROR on error
+ */
+int pcap_init(phys_addr_t paddr, unsigned long size);
+
+/**
+ * pcap_start_stop() - start / stop pcap capture
+ *
+ * @start if true, start capture if false stop capture
+ *
+ * @return 0 on success, -ERROR on error
+ */
+int pcap_start_stop(bool start);
+
+/**
+ * pcap_clear() - clear pcap capture buffer and statistics
+ *
+ * @return 0 on success, -ERROR on error
+ */
+int pcap_clear(void);
+
+/**
+ * pcap_print_status() - print status of pcap capture
+ *
+ * @return 0 on success, -ERROR on error
+ */
+int pcap_print_status(void);
+
+/**
+ * pcap_active() - check if pcap is enabled
+ *
+ * @return TRUE if active, FALSE if not.
+ */
+bool pcap_active(void);
+
+/**
+ * pcap_post() - Post a packet to PCAP file
+ *
+ * @packet: packet to post
+ * @len: packet length in bytes
+ * @outgoing packet direction (outgoing/incoming)
+ * @return 0 on success, -ERROR on error
+ */
+int pcap_post(const void *packet, size_t len, bool outgoing);
diff --git a/include/netdev.h b/include/netdev.h
index 0a1a3a2..68a3fce 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -10,6 +10,7 @@
#ifndef _NETDEV_H_
#define _NETDEV_H_
+#include <phy_interface.h>
/*
* Board and CPU-specific initialization functions
@@ -21,6 +22,8 @@
*/
int board_eth_init(bd_t *bis);
+int board_interface_eth_init(struct udevice *dev,
+ phy_interface_t interface_type);
int cpu_eth_init(bd_t *bis);
/* Driver initialization prototypes */
@@ -30,7 +33,6 @@
int bfin_EMAC_initialize(bd_t *bis);
int calxedaxgmac_initialize(u32 id, ulong base_addr);
int cs8900_initialize(u8 dev_num, int base_addr);
-int davinci_emac_initialize(void);
int dc21x4x_initialize(bd_t *bis);
int designware_initialize(ulong base_addr, u32 interface);
int dm9000_initialize(bd_t *bis);
diff --git a/include/opensbi.h b/include/opensbi.h
new file mode 100644
index 0000000..9f1d62e
--- /dev/null
+++ b/include/opensbi.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Based on include/sbi/{fw_dynamic.h,sbi_scratch.h} from the OpenSBI project.
+ */
+#ifndef OPENSBI_H
+#define OPENSBI_H
+
+/** Expected value of info magic ('OSBI' ascii string in hex) */
+#define FW_DYNAMIC_INFO_MAGIC_VALUE 0x4942534f
+
+/** Maximum supported info version */
+#define FW_DYNAMIC_INFO_VERSION 0x1
+
+/** Possible next mode values */
+#define FW_DYNAMIC_INFO_NEXT_MODE_U 0x0
+#define FW_DYNAMIC_INFO_NEXT_MODE_S 0x1
+#define FW_DYNAMIC_INFO_NEXT_MODE_M 0x3
+
+enum sbi_scratch_options {
+ /** Disable prints during boot */
+ SBI_SCRATCH_NO_BOOT_PRINTS = (1 << 0),
+};
+
+/** Representation dynamic info passed by previous booting stage */
+struct fw_dynamic_info {
+ /** Info magic */
+ unsigned long magic;
+ /** Info version */
+ unsigned long version;
+ /** Next booting stage address */
+ unsigned long next_addr;
+ /** Next booting stage mode */
+ unsigned long next_mode;
+ /** Options for OpenSBI library */
+ unsigned long options;
+} __packed;
+
+#endif
diff --git a/include/part_efi.h b/include/part_efi.h
index 7170b61..eb5797a 100644
--- a/include/part_efi.h
+++ b/include/part_efi.h
@@ -25,6 +25,8 @@
#define EFI_PMBR_OSTYPE_EFI_GPT 0xEE
#define GPT_HEADER_SIGNATURE_UBOOT 0x5452415020494645ULL
+#define GPT_HEADER_CHROMEOS_IGNORE 0x454d45524f4e4749ULL // 'IGNOREME'
+
#define GPT_HEADER_REVISION_V1 0x00010000
#define GPT_PRIMARY_PARTITION_TABLE_LBA 1ULL
#define GPT_ENTRY_NUMBERS CONFIG_EFI_PARTITION_ENTRIES_NUMBERS
diff --git a/include/pci.h b/include/pci.h
index 508f7bc..298d0d4 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -455,6 +455,23 @@
#define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */
#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM
+/* Enhanced Allocation Registers */
+#define PCI_EA_NUM_ENT 2 /* Number of Capability Entries */
+#define PCI_EA_NUM_ENT_MASK 0x3f /* Num Entries Mask */
+#define PCI_EA_FIRST_ENT 4 /* First EA Entry in List */
+#define PCI_EA_ES 0x00000007 /* Entry Size */
+#define PCI_EA_BEI 0x000000f0 /* BAR Equivalent Indicator */
+/* Base, MaxOffset registers */
+/* bit 0 is reserved */
+#define PCI_EA_IS_64 0x00000002 /* 64-bit field flag */
+#define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */
+
+/* PCI Express capabilities */
+#define PCI_EXP_DEVCAP 4 /* Device capabilities */
+#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */
+#define PCI_EXP_DEVCTL 8 /* Device Control */
+#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */
+
/* Include the ID list */
#include <pci_ids.h>
@@ -1309,12 +1326,16 @@
* dm_pci_map_bar() - get a virtual address associated with a BAR region
*
* Looks up a base address register and finds the physical memory address
- * that corresponds to it
+ * that corresponds to it.
+ * Can be used for 32b BARs 0-5 on type 0 functions and for 32b BARs 0-1 on
+ * type 1 functions.
+ * Can also be used on type 0 functions that support Enhanced Allocation for
+ * 32b/64b BARs. Note that duplicate BEI entries are not supported.
*
* @dev: Device to check
- * @bar: Bar number to read (numbered from 0)
+ * @bar: Bar register offset (PCI_BASE_ADDRESS_...)
* @flags: Flags for the region type (PCI_REGION_...)
- * @return: pointer to the virtual address to use
+ * @return: pointer to the virtual address to use or 0 on error
*/
void *dm_pci_map_bar(struct udevice *dev, int bar, int flags);
@@ -1411,6 +1432,14 @@
*/
int dm_pci_find_ext_capability(struct udevice *dev, int cap);
+/**
+ * dm_pci_flr() - Perform FLR if the device suppoorts it
+ *
+ * @dev: PCI device to reset
+ * @return: 0 if OK, -ENOENT if FLR is not supported by dev
+ */
+int dm_pci_flr(struct udevice *dev);
+
#define dm_pci_virt_to_bus(dev, addr, flags) \
dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), (flags))
#define dm_pci_bus_to_virt(dev, addr, flags, len, map_flags) \
diff --git a/include/pci_ep.h b/include/pci_ep.h
new file mode 100644
index 0000000..00e8c6d
--- /dev/null
+++ b/include/pci_ep.h
@@ -0,0 +1,414 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Adapted from Linux kernel driver
+ * Copyright (C) 2017 Texas Instruments
+ * Author: Kishon Vijay Abraham I <kishon@ti.com>
+ *
+ * (C) Copyright 2019
+ * Ramon Fried <ramon.fried@gmail.com>
+ */
+
+#ifndef _PCI_EP_H
+#define _PCI_EP_H
+
+#include <pci.h>
+
+/**
+ * enum pci_interrupt_pin - PCI INTx interrupt values
+ * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
+ * @PCI_INTERRUPT_INTA: PCI INTA pin
+ * @PCI_INTERRUPT_INTB: PCI INTB pin
+ * @PCI_INTERRUPT_INTC: PCI INTC pin
+ * @PCI_INTERRUPT_INTD: PCI INTD pin
+ *
+ * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
+ * PCI_INTERRUPT_PIN register.
+ */
+enum pci_interrupt_pin {
+ PCI_INTERRUPT_UNKNOWN,
+ PCI_INTERRUPT_INTA,
+ PCI_INTERRUPT_INTB,
+ PCI_INTERRUPT_INTC,
+ PCI_INTERRUPT_INTD,
+};
+
+enum pci_barno {
+ BAR_0,
+ BAR_1,
+ BAR_2,
+ BAR_3,
+ BAR_4,
+ BAR_5,
+};
+
+enum pci_ep_irq_type {
+ PCI_EP_IRQ_UNKNOWN,
+ PCI_EP_IRQ_LEGACY,
+ PCI_EP_IRQ_MSI,
+ PCI_EP_IRQ_MSIX,
+};
+
+/**
+ * struct pci_bar - represents the BAR (Base Address Register) of EP device
+ * @phys_addr: physical address that should be mapped to the BAR
+ * @size: the size of the address space present in BAR
+ * pci_barno: number of pci BAR to set (0..5)
+ * @flags: BAR access flags
+ */
+struct pci_bar {
+ dma_addr_t phys_addr;
+ size_t size;
+ enum pci_barno barno;
+ int flags;
+};
+
+/**
+ * struct pci_ep_header - represents standard configuration header
+ * @vendorid: identifies device manufacturer
+ * @deviceid: identifies a particular device
+ * @revid: specifies a device-specific revision identifier
+ * @progif_code: identifies a specific register-level programming interface
+ * @subclass_code: identifies more specifically the function of the device
+ * @baseclass_code: broadly classifies the type of function the device performs
+ * @cache_line_size: specifies the system cacheline size in units of DWORDs
+ * @subsys_vendor_id: vendor of the add-in card or subsystem
+ * @subsys_id: id specific to vendor
+ * @interrupt_pin: interrupt pin the device (or device function) uses
+ */
+struct pci_ep_header {
+ u16 vendorid;
+ u16 deviceid;
+ u8 revid;
+ u8 progif_code;
+ u8 subclass_code;
+ u8 baseclass_code;
+ u8 cache_line_size;
+ u16 subsys_vendor_id;
+ u16 subsys_id;
+ enum pci_interrupt_pin interrupt_pin;
+};
+
+/* PCI endpoint operations */
+struct pci_ep_ops {
+ /**
+ * write_header() - Write a PCI configuration space header
+ *
+ * @dev: device to write to
+ * @func_num: EP function to fill
+ * @hdr: header to write
+ * @return 0 if OK, -ve on error
+ */
+ int (*write_header)(struct udevice *dev, uint func_num,
+ struct pci_ep_header *hdr);
+ /**
+ * read_header() - Read a PCI configuration space header
+ *
+ * @dev: device to write to
+ * @func_num: EP function to fill
+ * @hdr: header to read to
+ * @return 0 if OK, -ve on error
+ */
+ int (*read_header)(struct udevice *dev, uint func_num,
+ struct pci_ep_header *hdr);
+ /**
+ * set_bar() - Set BAR (Base Address Register) properties
+ *
+ * @dev: device to set
+ * @func_num: EP function to set
+ * @bar: bar data
+ * @return 0 if OK, -ve on error
+ */
+ int (*set_bar)(struct udevice *dev, uint func_num,
+ struct pci_bar *bar);
+ /**
+ * read_bar() - Read BAR (Base Address Register) properties
+ *
+ * @dev: device to read
+ * @func_num: EP function to read
+ * @bar: struct to copy data to
+ * @barno: bar number to read
+ * @return 0 if OK, -ve on error
+ */
+ int (*read_bar)(struct udevice *dev, uint func_num,
+ struct pci_bar *bar, enum pci_barno barno);
+ /**
+ * clear_bar() - clear BAR (Base Address Register)
+ *
+ * @dev: device to clear
+ * @func_num: EP function to clear
+ * @bar: bar number
+ * @return 0 if OK, -ve on error
+ */
+ int (*clear_bar)(struct udevice *dev, uint func_num,
+ enum pci_barno bar);
+ /**
+ * map_addr() - map CPU address to PCI address
+ *
+ * outband region is used in order to generate PCI read/write
+ * transaction from local memory/write.
+ *
+ * @dev: device to set
+ * @func_num: EP function to set
+ * @addr: local physical address base
+ * @pci_addr: pci address to translate to
+ * @size: region size
+ * @return 0 if OK, -ve on error
+ */
+ int (*map_addr)(struct udevice *dev, uint func_num,
+ phys_addr_t addr, u64 pci_addr, size_t size);
+ /**
+ * unmap_addr() - unmap CPU address to PCI address
+ *
+ * unmap previously mapped region.
+ *
+ * @dev: device to set
+ * @func_num: EP function to set
+ * @addr: local physical address base
+ * @return 0 if OK, -ve on error
+ */
+ int (*unmap_addr)(struct udevice *dev, uint func_num,
+ phys_addr_t addr);
+ /**
+ * set_msi() - set msi capability property
+ *
+ * set the number of required MSI vectors the device
+ * needs for operation.
+ *
+ * @dev: device to set
+ * @func_num: EP function to set
+ * @interrupts: required interrupts count
+ * @return 0 if OK, -ve on error
+ */
+ int (*set_msi)(struct udevice *dev, uint func_num, uint interrupts);
+
+ /**
+ * get_msi() - get the number of MSI interrupts allocated by the host.
+ *
+ * Read the Multiple Message Enable bitfield from
+ * Message control register.
+ *
+ * @dev: device to use
+ * @func_num: EP function to use
+ * @return msi count if OK, -EINVAL if msi were not enabled at host.
+ */
+ int (*get_msi)(struct udevice *dev, uint func_num);
+
+ /**
+ * set_msix() - set msix capability property
+ *
+ * set the number of required MSIx vectors the device
+ * needs for operation.
+ *
+ * @dev: device to set
+ * @func_num: EP function to set
+ * @interrupts: required interrupts count
+ * @return 0 if OK, -ve on error
+ */
+ int (*set_msix)(struct udevice *dev, uint func_num,
+ uint interrupts);
+
+ /**
+ * get_msix() - get the number of MSIx interrupts allocated by the host.
+ *
+ * Read the Multiple Message Enable bitfield from
+ * Message control register.
+ *
+ * @dev: device to use
+ * @func_num: EP function to use
+ * @return msi count if OK, -EINVAL if msi were not enabled at host.
+ */
+ int (*get_msix)(struct udevice *dev, uint func_num);
+
+ /**
+ * raise_irq() - raise a legacy, MSI or MSI-X interrupt
+ *
+ * @dev: device to set
+ * @func_num: EP function to set
+ * @type: type of irq to send
+ * @interrupt_num: interrupt vector to use
+ * @return 0 if OK, -ve on error
+ */
+ int (*raise_irq)(struct udevice *dev, uint func_num,
+ enum pci_ep_irq_type type, uint interrupt_num);
+ /**
+ * start() - start the PCI link
+ *
+ * @dev: device to set
+ * @return 0 if OK, -ve on error
+ */
+ int (*start)(struct udevice *dev);
+
+ /**
+ * stop() - stop the PCI link
+ *
+ * @dev: device to set
+ * @return 0 if OK, -ve on error
+ */
+ int (*stop)(struct udevice *dev);
+};
+
+#define pci_ep_get_ops(dev) ((struct pci_ep_ops *)(dev)->driver->ops)
+
+/**
+ * pci_ep_write_header() - Write a PCI configuration space header
+ *
+ * @dev: device to write to
+ * @func_num: EP function to fill
+ * @hdr: header to write
+ * @return 0 if OK, -ve on error
+ */
+int pci_ep_write_header(struct udevice *dev, uint func_num,
+ struct pci_ep_header *hdr);
+
+/**
+ * dm_pci_ep_read_header() - Read a PCI configuration space header
+ *
+ * @dev: device to write to
+ * @func_num: EP function to fill
+ * @hdr: header to read to
+ * @return 0 if OK, -ve on error
+ */
+int pci_ep_read_header(struct udevice *dev, uint func_num,
+ struct pci_ep_header *hdr);
+/**
+ * pci_ep_set_bar() - Set BAR (Base Address Register) properties
+ *
+ * @dev: device to set
+ * @func_num: EP function to set
+ * @bar: bar data
+ * @return 0 if OK, -ve on error
+ */
+int pci_ep_set_bar(struct udevice *dev, uint func_num, struct pci_bar *bar);
+
+/**
+ * pci_ep_read_bar() - Read BAR (Base Address Register) properties
+ *
+ * @dev: device to read
+ * @func_num: EP function to read
+ * @bar: struct to copy data to
+ * @barno: bar number to read
+ * @return 0 if OK, -ve on error
+ */
+int pci_ep_read_bar(struct udevice *dev, uint func_no, struct pci_bar *ep_bar,
+ enum pci_barno barno);
+
+/**
+ * pci_ep_clear_bar() - Clear BAR (Base Address Register)
+ * mark the BAR as empty so host won't map it.
+ * @dev: device to clear
+ * @func_num: EP function to clear
+ * @bar: bar number
+ * @return 0 if OK, -ve on error
+ */
+int pci_ep_clear_bar(struct udevice *dev, uint func_num, enum pci_barno bar);
+/**
+ * pci_ep_map_addr() - map CPU address to PCI address
+ *
+ * outband region is used in order to generate PCI read/write
+ * transaction from local memory/write.
+ *
+ * @dev: device to set
+ * @func_num: EP function to set
+ * @addr: local physical address base
+ * @pci_addr: pci address to translate to
+ * @size: region size
+ * @return 0 if OK, -ve on error
+ */
+int pci_ep_map_addr(struct udevice *dev, uint func_num, phys_addr_t addr,
+ u64 pci_addr, size_t size);
+/**
+ * pci_ep_unmap_addr() - unmap CPU address to PCI address
+ *
+ * unmap previously mapped region.
+ *
+ * @dev: device to set
+ * @func_num: EP function to set
+ * @addr: local physical address base
+ * @return 0 if OK, -ve on error
+ */
+int pci_ep_unmap_addr(struct udevice *dev, uint func_num, phys_addr_t addr);
+
+/**
+ * pci_ep_set_msi() - set msi capability property
+ *
+ * set the number of required MSI vectors the device
+ * needs for operation.
+ *
+ * @dev: device to set
+ * @func_num: EP function to set
+ * @interrupts: required interrupts count
+ * @return 0 if OK, -ve on error
+ */
+int pci_ep_set_msi(struct udevice *dev, uint func_num, uint interrupts);
+
+/**
+ * pci_ep_get_msi() - get the number of MSI interrupts allocated by the host.
+ *
+ * Read the Multiple Message Enable bitfield from
+ * Message control register.
+ *
+ * @dev: device to use
+ * @func_num: EP function to use
+ * @return msi count if OK, -EINVAL if msi were not enabled at host.
+ */
+int pci_ep_get_msi(struct udevice *dev, uint func_num);
+
+/**
+ * pci_ep_set_msix() - set msi capability property
+ *
+ * set the number of required MSIx vectors the device
+ * needs for operation.
+ *
+ * @dev: device to set
+ * @func_num: EP function to set
+ * @interrupts: required interrupts count
+ * @return 0 if OK, -ve on error
+ */
+int pci_ep_set_msix(struct udevice *dev, uint func_num, uint interrupts);
+
+/**
+ * pci_ep_get_msix() - get the number of MSIx interrupts allocated by the host.
+ *
+ * Read the Multiple Message Enable bitfield from
+ * Message control register.
+ *
+ * @dev: device to use
+ * @func_num: EP function to use
+ * @return msi count if OK, -EINVAL if msi were not enabled at host.
+ */
+int pci_ep_get_msix(struct udevice *dev, uint func_num);
+
+/**
+ * pci_ep_raise_irq() - raise a legacy, MSI or MSI-X interrupt
+ *
+ * @dev: device to set
+ * @func_num: EP function to set
+ * @type: type of irq to send
+ * @interrupt_num: interrupt vector to use
+ * @return 0 if OK, -ve on error
+ */
+int pci_ep_raise_irq(struct udevice *dev, uint func_num,
+ enum pci_ep_irq_type type, uint interrupt_num);
+/**
+ * pci_ep_start() - start the PCI link
+ *
+ * Enable PCI endpoint device and start link
+ * process.
+ *
+ * @dev: device to set
+ * @return 0 if OK, -ve on error
+ */
+int pci_ep_start(struct udevice *dev);
+
+/**
+ * pci_ep_stop() - stop the PCI link
+ *
+ * Disable PCI endpoint device and stop
+ * link.
+ *
+ * @dev: device to set
+ * @return 0 if OK, -ve on error
+ */
+int pci_ep_stop(struct udevice *dev);
+
+#endif
diff --git a/include/pcmcia.h b/include/pcmcia.h
deleted file mode 100644
index 89e528e..0000000
--- a/include/pcmcia.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#ifndef _PCMCIA_H
-#define _PCMCIA_H
-
-#include <common.h>
-#include <config.h>
-
-/*
- * Allow configuration to select PCMCIA slot,
- * or try to generate a useful default
- */
-#if defined(CONFIG_CMD_PCMCIA)
-
-#if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
-# error "PCMCIA Slot not configured"
-#endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */
-
-/* Make sure exactly one slot is defined - we support only one for now */
-#if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
-#error Neither CONFIG_PCMCIA_SLOT_A nor CONFIG_PCMCIA_SLOT_B configured
-#endif
-#if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B)
-#error Both CONFIG_PCMCIA_SLOT_A and CONFIG_PCMCIA_SLOT_B configured
-#endif
-
-#ifndef PCMCIA_SOCKETS_NO
-#define PCMCIA_SOCKETS_NO 1
-#endif
-#ifndef PCMCIA_MEM_WIN_NO
-#define PCMCIA_MEM_WIN_NO 4
-#endif
-#define PCMCIA_IO_WIN_NO 2
-
-/* define _slot_ to be able to optimize macros */
-#ifdef CONFIG_PCMCIA_SLOT_A
-# define _slot_ 0
-# define PCMCIA_SLOT_MSG "slot A"
-# define PCMCIA_SLOT_x PCMCIA_PSLOT_A
-#else
-# define _slot_ 1
-# define PCMCIA_SLOT_MSG "slot B"
-# define PCMCIA_SLOT_x PCMCIA_PSLOT_B
-#endif
-
-/*
- * This structure is used to address each window in the PCMCIA controller.
- *
- * Keep in mind that we assume that pcmcia_win_t[n+1] is mapped directly
- * after pcmcia_win_t[n]...
- */
-
-typedef struct {
- ulong br;
- ulong or;
-} pcmcia_win_t;
-
-/**********************************************************************/
-
-/*
- * CIS Tupel codes
- */
-#define CISTPL_NULL 0x00
-#define CISTPL_DEVICE 0x01
-#define CISTPL_LONGLINK_CB 0x02
-#define CISTPL_INDIRECT 0x03
-#define CISTPL_CONFIG_CB 0x04
-#define CISTPL_CFTABLE_ENTRY_CB 0x05
-#define CISTPL_LONGLINK_MFC 0x06
-#define CISTPL_BAR 0x07
-#define CISTPL_PWR_MGMNT 0x08
-#define CISTPL_EXTDEVICE 0x09
-#define CISTPL_CHECKSUM 0x10
-#define CISTPL_LONGLINK_A 0x11
-#define CISTPL_LONGLINK_C 0x12
-#define CISTPL_LINKTARGET 0x13
-#define CISTPL_NO_LINK 0x14
-#define CISTPL_VERS_1 0x15
-#define CISTPL_ALTSTR 0x16
-#define CISTPL_DEVICE_A 0x17
-#define CISTPL_JEDEC_C 0x18
-#define CISTPL_JEDEC_A 0x19
-#define CISTPL_CONFIG 0x1a
-#define CISTPL_CFTABLE_ENTRY 0x1b
-#define CISTPL_DEVICE_OC 0x1c
-#define CISTPL_DEVICE_OA 0x1d
-#define CISTPL_DEVICE_GEO 0x1e
-#define CISTPL_DEVICE_GEO_A 0x1f
-#define CISTPL_MANFID 0x20
-#define CISTPL_FUNCID 0x21
-#define CISTPL_FUNCE 0x22
-#define CISTPL_SWIL 0x23
-#define CISTPL_END 0xff
-
-/*
- * CIS Function ID codes
- */
-#define CISTPL_FUNCID_MULTI 0x00
-#define CISTPL_FUNCID_MEMORY 0x01
-#define CISTPL_FUNCID_SERIAL 0x02
-#define CISTPL_FUNCID_PARALLEL 0x03
-#define CISTPL_FUNCID_FIXED 0x04
-#define CISTPL_FUNCID_VIDEO 0x05
-#define CISTPL_FUNCID_NETWORK 0x06
-#define CISTPL_FUNCID_AIMS 0x07
-#define CISTPL_FUNCID_SCSI 0x08
-
-/*
- * Fixed Disk FUNCE codes
- */
-#define CISTPL_IDE_INTERFACE 0x01
-
-#define CISTPL_FUNCE_IDE_IFACE 0x01
-#define CISTPL_FUNCE_IDE_MASTER 0x02
-#define CISTPL_FUNCE_IDE_SLAVE 0x03
-
-/* First feature byte */
-#define CISTPL_IDE_SILICON 0x04
-#define CISTPL_IDE_UNIQUE 0x08
-#define CISTPL_IDE_DUAL 0x10
-
-/* Second feature byte */
-#define CISTPL_IDE_HAS_SLEEP 0x01
-#define CISTPL_IDE_HAS_STANDBY 0x02
-#define CISTPL_IDE_HAS_IDLE 0x04
-#define CISTPL_IDE_LOW_POWER 0x08
-#define CISTPL_IDE_REG_INHIBIT 0x10
-#define CISTPL_IDE_HAS_INDEX 0x20
-#define CISTPL_IDE_IOIS16 0x40
-
-#endif
-
-#endif /* _PCMCIA_H */
diff --git a/include/pcmcia/yenta.h b/include/pcmcia/yenta.h
deleted file mode 100644
index 5cd58a7..0000000
--- a/include/pcmcia/yenta.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * yenta.h 1.20 2001/08/24 12:15:34
- *
- * The contents of this file are subject to the Mozilla Public License
- * Version 1.1 (the "License"); you may not use this file except in
- * compliance with the License. You may obtain a copy of the License
- * at http://www.mozilla.org/MPL/
- *
- * Software distributed under the License is distributed on an "AS IS"
- * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
- * the License for the specific language governing rights and
- * limitations under the License.
- *
- * The initial developer of the original code is David A. Hinds
- * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
- * are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
- *
- * Alternatively, the contents of this file may be used under the
- * terms of the GNU General Public License version 2 (the "GPL"), in
- * which case the provisions of the GPL are applicable instead of the
- * above. If you wish to allow the use of your version of this file
- * only under the terms of the GPL and not to allow others to use
- * your version of this file under the MPL, indicate your decision by
- * deleting the provisions above and replace them with the notice and
- * other provisions required by the GPL. If you do not delete the
- * provisions above, a recipient may use your version of this file
- * under either the MPL or the GPL.
- */
-
-#ifndef _LINUX_YENTA_H
-#define _LINUX_YENTA_H
-
-/* PCI Configuration Registers */
-
-#define PCI_STATUS_CAPLIST 0x10
-#define PCI_CB_CAPABILITY_POINTER 0x14 /* 8 bit */
-#define PCI_CAPABILITY_ID 0x00 /* 8 bit */
-#define PCI_CAPABILITY_PM 0x01
-#define PCI_NEXT_CAPABILITY 0x01 /* 8 bit */
-#define PCI_PM_CAPABILITIES 0x02 /* 16 bit */
-#define PCI_PMCAP_PME_D3COLD 0x8000
-#define PCI_PMCAP_PME_D3HOT 0x4000
-#define PCI_PMCAP_PME_D2 0x2000
-#define PCI_PMCAP_PME_D1 0x1000
-#define PCI_PMCAP_PME_D0 0x0800
-#define PCI_PMCAP_D2_CAP 0x0400
-#define PCI_PMCAP_D1_CAP 0x0200
-#define PCI_PMCAP_DYN_DATA 0x0100
-#define PCI_PMCAP_DSI 0x0020
-#define PCI_PMCAP_AUX_PWR 0x0010
-#define PCI_PMCAP_PMECLK 0x0008
-#define PCI_PMCAP_VERSION_MASK 0x0007
-#define PCI_PM_CONTROL_STATUS 0x04 /* 16 bit */
-#define PCI_PMCS_PME_STATUS 0x8000
-#define PCI_PMCS_DATASCALE_MASK 0x6000
-#define PCI_PMCS_DATASCALE_SHIFT 13
-#define PCI_PMCS_DATASEL_MASK 0x1e00
-#define PCI_PMCS_DATASEL_SHIFT 9
-#define PCI_PMCS_PME_ENABLE 0x0100
-#define PCI_PMCS_PWR_STATE_MASK 0x0003
-#define PCI_PMCS_PWR_STATE_D0 0x0000
-#define PCI_PMCS_PWR_STATE_D1 0x0001
-#define PCI_PMCS_PWR_STATE_D2 0x0002
-#define PCI_PMCS_PWR_STATE_D3 0x0003
-#define PCI_PM_BRIDGE_EXT 0x06 /* 8 bit */
-#define PCI_PM_DATA 0x07 /* 8 bit */
-
-#define CB_PRIMARY_BUS 0x18 /* 8 bit */
-#define CB_CARDBUS_BUS 0x19 /* 8 bit */
-#define CB_SUBORD_BUS 0x1a /* 8 bit */
-#define CB_LATENCY_TIMER 0x1b /* 8 bit */
-
-#define CB_MEM_BASE(m) (0x1c + 8*(m))
-#define CB_MEM_LIMIT(m) (0x20 + 8*(m))
-#define CB_IO_BASE(m) (0x2c + 8*(m))
-#define CB_IO_LIMIT(m) (0x30 + 8*(m))
-
-#define CB_BRIDGE_CONTROL 0x3e /* 16 bit */
-#define CB_BCR_PARITY_ENA 0x0001
-#define CB_BCR_SERR_ENA 0x0002
-#define CB_BCR_ISA_ENA 0x0004
-#define CB_BCR_VGA_ENA 0x0008
-#define CB_BCR_MABORT 0x0020
-#define CB_BCR_CB_RESET 0x0040
-#define CB_BCR_ISA_IRQ 0x0080
-#define CB_BCR_PREFETCH(m) (0x0100 << (m))
-#define CB_BCR_WRITE_POST 0x0400
-
-#define CB_LEGACY_MODE_BASE 0x44
-
-/* Memory mapped registers */
-
-#define CB_SOCKET_EVENT 0x0000
-#define CB_SE_CSTSCHG 0x00000001
-#define CB_SE_CCD 0x00000006
-#define CB_SE_CCD1 0x00000002
-#define CB_SE_CCD2 0x00000004
-#define CB_SE_PWRCYCLE 0x00000008
-
-#define CB_SOCKET_MASK 0x0004
-#define CB_SM_CSTSCHG 0x00000001
-#define CB_SM_CCD 0x00000006
-#define CB_SM_PWRCYCLE 0x00000008
-
-#define CB_SOCKET_STATE 0x0008
-#define CB_SS_CSTSCHG 0x00000001
-#define CB_SS_CCD 0x00000006
-#define CB_SS_CCD1 0x00000002
-#define CB_SS_CCD2 0x00000004
-#define CB_SS_PWRCYCLE 0x00000008
-#define CB_SS_16BIT 0x00000010
-#define CB_SS_32BIT 0x00000020
-#define CB_SS_CINT 0x00000040
-#define CB_SS_BADCARD 0x00000080
-#define CB_SS_DATALOST 0x00000100
-#define CB_SS_BADVCC 0x00000200
-#define CB_SS_5VCARD 0x00000400
-#define CB_SS_3VCARD 0x00000800
-#define CB_SS_XVCARD 0x00001000
-#define CB_SS_YVCARD 0x00002000
-#define CB_SS_VSENSE 0x00003c86
-#define CB_SS_5VSOCKET 0x10000000
-#define CB_SS_3VSOCKET 0x20000000
-#define CB_SS_XVSOCKET 0x40000000
-#define CB_SS_YVSOCKET 0x80000000
-
-#define CB_SOCKET_FORCE 0x000c
-#define CB_SF_CVSTEST 0x00004000
-
-#define CB_SOCKET_CONTROL 0x0010
-#define CB_SC_VPP_MASK 0x00000007
-#define CB_SC_VPP_OFF 0x00000000
-#define CB_SC_VPP_12V 0x00000001
-#define CB_SC_VPP_5V 0x00000002
-#define CB_SC_VPP_3V 0x00000003
-#define CB_SC_VPP_XV 0x00000004
-#define CB_SC_VPP_YV 0x00000005
-#define CB_SC_VCC_MASK 0x00000070
-#define CB_SC_VCC_OFF 0x00000000
-#define CB_SC_VCC_5V 0x00000020
-#define CB_SC_VCC_3V 0x00000030
-#define CB_SC_VCC_XV 0x00000040
-#define CB_SC_VCC_YV 0x00000050
-#define CB_SC_CCLK_STOP 0x00000080
-
-#define CB_SOCKET_POWER 0x0020
-#define CB_SP_CLK_CTRL 0x00000001
-#define CB_SP_CLK_CTRL_ENA 0x00010000
-#define CB_SP_CLK_MODE 0x01000000
-#define CB_SP_ACCESS 0x02000000
-
-/* Address bits 31..24 for memory windows for 16-bit cards,
- accessable only by memory mapping the 16-bit register set */
-#define CB_MEM_PAGE(map) (0x40 + (map))
-
-#endif /* _LINUX_YENTA_H */
diff --git a/include/pe.h b/include/pe.h
index 36e1908..bff3b0a 100644
--- a/include/pe.h
+++ b/include/pe.h
@@ -34,22 +34,6 @@
uint32_t e_lfanew; /* 3c: Offset to extended header */
} IMAGE_DOS_HEADER, *PIMAGE_DOS_HEADER;
-#define IMAGE_DOS_SIGNATURE 0x5A4D /* MZ */
-#define IMAGE_NT_SIGNATURE 0x00004550 /* PE00 */
-
-#define IMAGE_FILE_MACHINE_I386 0x014c
-#define IMAGE_FILE_MACHINE_ARM 0x01c0
-#define IMAGE_FILE_MACHINE_THUMB 0x01c2
-#define IMAGE_FILE_MACHINE_ARMNT 0x01c4
-#define IMAGE_FILE_MACHINE_AMD64 0x8664
-#define IMAGE_FILE_MACHINE_ARM64 0xaa64
-#define IMAGE_FILE_MACHINE_RISCV32 0x5032
-#define IMAGE_FILE_MACHINE_RISCV64 0x5064
-
-#define IMAGE_NT_OPTIONAL_HDR32_MAGIC 0x10b
-#define IMAGE_NT_OPTIONAL_HDR64_MAGIC 0x20b
-#define IMAGE_SUBSYSTEM_EFI_APPLICATION 10
-
typedef struct _IMAGE_FILE_HEADER {
uint16_t Machine;
uint16_t NumberOfSections;
diff --git a/include/phy.h b/include/phy.h
index d01435d..f4530fa 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -246,15 +246,71 @@
#endif
+/**
+ * phy_init() - Initializes the PHY drivers
+ *
+ * This function registers all available PHY drivers
+ *
+ * @return 0 if OK, -ve on error
+ */
int phy_init(void);
+
+/**
+ * phy_reset() - Resets the specified PHY
+ *
+ * Issues a reset of the PHY and waits for it to complete
+ *
+ * @phydev: PHY to reset
+ * @return 0 if OK, -ve on error
+ */
int phy_reset(struct phy_device *phydev);
+
+/**
+ * phy_find_by_mask() - Searches for a PHY on the specified MDIO bus
+ *
+ * The function checks the PHY addresses flagged in phy_mask and returns a
+ * phy_device pointer if it detects a PHY.
+ * This function should only be called if just one PHY is expected to be present
+ * in the set of addresses flagged in phy_mask. If multiple PHYs are present,
+ * it is undefined which of these PHYs is returned.
+ *
+ * @bus: MII/MDIO bus to scan
+ * @phy_mask: bitmap of PYH addresses to scan
+ * @interface: type of MAC-PHY interface
+ * @return pointer to phy_device if a PHY is found, or NULL otherwise
+ */
struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask,
phy_interface_t interface);
+
#ifdef CONFIG_DM_ETH
+
+/**
+ * phy_connect_dev() - Associates the given pair of PHY and Ethernet devices
+ * @phydev: PHY device
+ * @dev: Ethernet device
+ */
void phy_connect_dev(struct phy_device *phydev, struct udevice *dev);
+
+/**
+ * phy_connect() - Creates a PHY device for the Ethernet interface
+ *
+ * Creates a PHY device for the PHY at the given address, if one doesn't exist
+ * already, and associates it with the Ethernet device.
+ * The function may be called with addr <= 0, in this case addr value is ignored
+ * and the bus is scanned to detect a PHY. Scanning should only be used if only
+ * one PHY is expected to be present on the MDIO bus, otherwise it is undefined
+ * which PHY is returned.
+ *
+ * @bus: MII/MDIO bus that hosts the PHY
+ * @addr: PHY address on MDIO bus
+ * @dev: Ethernet device to associate to the PHY
+ * @interface: type of MAC-PHY interface
+ * @return pointer to phy_device if a PHY is found, or NULL otherwise
+ */
struct phy_device *phy_connect(struct mii_dev *bus, int addr,
struct udevice *dev,
phy_interface_t interface);
+
static inline ofnode phy_get_ofnode(struct phy_device *phydev)
{
if (ofnode_valid(phydev->node))
@@ -263,10 +319,34 @@
return dev_ofnode(phydev->dev);
}
#else
+
+/**
+ * phy_connect_dev() - Associates the given pair of PHY and Ethernet devices
+ * @phydev: PHY device
+ * @dev: Ethernet device
+ */
void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev);
+
+/**
+ * phy_connect() - Creates a PHY device for the Ethernet interface
+ *
+ * Creates a PHY device for the PHY at the given address, if one doesn't exist
+ * already, and associates it with the Ethernet device.
+ * The function may be called with addr <= 0, in this case addr value is ignored
+ * and the bus is scanned to detect a PHY. Scanning should only be used if only
+ * one PHY is expected to be present on the MDIO bus, otherwise it is undefined
+ * which PHY is returned.
+ *
+ * @bus: MII/MDIO bus that hosts the PHY
+ * @addr: PHY address on MDIO bus
+ * @dev: Ethernet device to associate to the PHY
+ * @interface: type of MAC-PHY interface
+ * @return pointer to phy_device if a PHY is found, or NULL otherwise
+ */
struct phy_device *phy_connect(struct mii_dev *bus, int addr,
struct eth_device *dev,
phy_interface_t interface);
+
static inline ofnode phy_get_ofnode(struct phy_device *phydev)
{
return ofnode_null();
diff --git a/include/power-domain.h b/include/power-domain.h
index 0099605..ef15dc9 100644
--- a/include/power-domain.h
+++ b/include/power-domain.h
@@ -55,23 +55,12 @@
*
* @dev: The device which implements the power domain.
* @id: The power domain ID within the provider.
- *
- * Currently, the power domain API assumes that a single integer ID is enough
- * to identify and configure any power domain for any power domain provider. If
- * this assumption becomes invalid in the future, the struct could be expanded
- * to either (a) add more fields to allow power domain providers to store
- * additional information, or (b) replace the id field with an opaque pointer,
- * which the provider would dynamically allocate during its .of_xlate op, and
- * process during is .request op. This may require the addition of an extra op
- * to clean up the allocation.
+ * @priv: Private data corresponding to each power domain.
*/
struct power_domain {
struct udevice *dev;
- /*
- * Written by of_xlate. We assume a single id is enough for now. In the
- * future, we might add more fields here.
- */
unsigned long id;
+ void *priv;
};
/**
@@ -151,7 +140,7 @@
#endif
/**
- * power_domain_off - Disable power ot a power domain.
+ * power_domain_off - Disable power to a power domain.
*
* @power_domain: A power domain struct that was previously successfully
* requested by power_domain_get().
diff --git a/include/power/bd71837.h b/include/power/bd71837.h
index 38c69b2..75e07e1 100644
--- a/include/power/bd71837.h
+++ b/include/power/bd71837.h
@@ -1,62 +1,103 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/* Copyright (C) 2018 ROHM Semiconductors */
-#ifndef BD71837_H_
-#define BD71837_H_
+#ifndef BD718XX_H_
+#define BD718XX_H_
-#define BD71837_REGULATOR_DRIVER "bd71837_regulator"
+#define BD718XX_REGULATOR_DRIVER "bd718x7_regulator"
enum {
- BD71837_REV = 0x00,
- BD71837_SWRESET = 0x01,
- BD71837_I2C_DEV = 0x02,
- BD71837_PWRCTRL0 = 0x03,
- BD71837_PWRCTRL1 = 0x04,
- BD71837_BUCK1_CTRL = 0x05,
- BD71837_BUCK2_CTRL = 0x06,
- BD71837_BUCK3_CTRL = 0x07,
- BD71837_BUCK4_CTRL = 0x08,
- BD71837_BUCK5_CTRL = 0x09,
- BD71837_BUCK6_CTRL = 0x0a,
- BD71837_BUCK7_CTRL = 0x0b,
- BD71837_BUCK8_CTRL = 0x0c,
- BD71837_BUCK1_VOLT_RUN = 0x0d,
- BD71837_BUCK1_VOLT_IDLE = 0x0e,
- BD71837_BUCK1_VOLT_SUSP = 0x0f,
- BD71837_BUCK2_VOLT_RUN = 0x10,
- BD71837_BUCK2_VOLT_IDLE = 0x11,
- BD71837_BUCK3_VOLT_RUN = 0x12,
- BD71837_BUCK4_VOLT_RUN = 0x13,
- BD71837_BUCK5_VOLT = 0x14,
- BD71837_BUCK6_VOLT = 0x15,
- BD71837_BUCK7_VOLT = 0x16,
- BD71837_BUCK8_VOLT = 0x17,
- BD71837_LDO1_VOLT = 0x18,
- BD71837_LDO2_VOLT = 0x19,
- BD71837_LDO3_VOLT = 0x1a,
- BD71837_LDO4_VOLT = 0x1b,
- BD71837_LDO5_VOLT = 0x1c,
- BD71837_LDO6_VOLT = 0x1d,
- BD71837_LDO7_VOLT = 0x1e,
- BD71837_TRANS_COND0 = 0x1f,
- BD71837_TRANS_COND1 = 0x20,
- BD71837_VRFAULTEN = 0x21,
- BD71837_MVRFLTMASK0 = 0x22,
- BD71837_MVRFLTMASK1 = 0x23,
- BD71837_MVRFLTMASK2 = 0x24,
- BD71837_RCVCFG = 0x25,
- BD71837_RCVNUM = 0x26,
- BD71837_PWRONCONFIG0 = 0x27,
- BD71837_PWRONCONFIG1 = 0x28,
- BD71837_RESETSRC = 0x29,
- BD71837_MIRQ = 0x2a,
- BD71837_IRQ = 0x2b,
- BD71837_IN_MON = 0x2c,
- BD71837_POW_STATE = 0x2d,
- BD71837_OUT32K = 0x2e,
- BD71837_REGLOCK = 0x2f,
- BD71837_MUXSW_EN = 0x30,
- BD71837_REG_NUM,
+ ROHM_CHIP_TYPE_BD71837 = 0,
+ ROHM_CHIP_TYPE_BD71847,
+ ROHM_CHIP_TYPE_BD70528,
+ ROHM_CHIP_TYPE_AMOUNT
};
+enum {
+ BD718XX_REV = 0x00,
+ BD718XX_SWRESET = 0x01,
+ BD718XX_I2C_DEV = 0x02,
+ BD718XX_PWRCTRL0 = 0x03,
+ BD718XX_PWRCTRL1 = 0x04,
+ BD718XX_BUCK1_CTRL = 0x05,
+ BD718XX_BUCK2_CTRL = 0x06,
+ BD71837_BUCK3_CTRL = 0x07,
+ BD71837_BUCK4_CTRL = 0x08,
+ BD718XX_1ST_NODVS_BUCK_CTRL = 0x09,
+ BD718XX_2ND_NODVS_BUCK_CTRL = 0x0a,
+ BD718XX_3RD_NODVS_BUCK_CTRL = 0x0b,
+ BD718XX_4TH_NODVS_BUCK_CTRL = 0x0c,
+ BD718XX_BUCK1_VOLT_RUN = 0x0d,
+ BD718XX_BUCK1_VOLT_IDLE = 0x0e,
+ BD718XX_BUCK1_VOLT_SUSP = 0x0f,
+ BD718XX_BUCK2_VOLT_RUN = 0x10,
+ BD718XX_BUCK2_VOLT_IDLE = 0x11,
+ BD71837_BUCK3_VOLT_RUN = 0x12,
+ BD71837_BUCK4_VOLT_RUN = 0x13,
+ BD718XX_1ST_NODVS_BUCK_VOLT = 0x14,
+ BD718XX_2ND_NODVS_BUCK_VOLT = 0x15,
+ BD718XX_3RD_NODVS_BUCK_VOLT = 0x16,
+ BD718XX_4TH_NODVS_BUCK_VOLT = 0x17,
+ BD718XX_LDO1_VOLT = 0x18,
+ BD718XX_LDO2_VOLT = 0x19,
+ BD718XX_LDO3_VOLT = 0x1a,
+ BD718XX_LDO4_VOLT = 0x1b,
+ BD718XX_LDO5_VOLT = 0x1c,
+ BD718XX_LDO6_VOLT = 0x1d,
+ BD71837_LDO7_VOLT = 0x1e,
+ BD718XX_TRANS_COND0 = 0x1f,
+ BD718XX_TRANS_COND1 = 0x20,
+ BD718XX_VRFAULTEN = 0x21,
+ BD718XX_MVRFLTMASK0 = 0x22,
+ BD718XX_MVRFLTMASK1 = 0x23,
+ BD718XX_MVRFLTMASK2 = 0x24,
+ BD718XX_RCVCFG = 0x25,
+ BD718XX_RCVNUM = 0x26,
+ BD718XX_PWRONCONFIG0 = 0x27,
+ BD718XX_PWRONCONFIG1 = 0x28,
+ BD718XX_RESETSRC = 0x29,
+ BD718XX_MIRQ = 0x2a,
+ BD718XX_IRQ = 0x2b,
+ BD718XX_IN_MON = 0x2c,
+ BD718XX_POW_STATE = 0x2d,
+ BD718XX_OUT32K = 0x2e,
+ BD718XX_REGLOCK = 0x2f,
+ BD718XX_MUXSW_EN = 0x30,
+ BD718XX_REG_OTPVER = 0xff,
+ BD718XX_MAX_REGISTER = 0x100,
+};
+
+#define BD718XX_REGLOCK_PWRSEQ 0x1
+#define BD718XX_REGLOCK_VREG 0x10
+
+#define BD718XX_BUCK_EN 0x01
+#define BD718XX_LDO_EN 0x40
+#define BD718XX_BUCK_SEL 0x02
+#define BD718XX_LDO_SEL 0x80
+
+#define DVS_BUCK_RUN_MASK 0x3f
+#define BD718XX_1ST_NODVS_BUCK_MASK 0x07
+#define BD718XX_3RD_NODVS_BUCK_MASK 0x07
+#define BD718XX_4TH_NODVS_BUCK_MASK 0x3f
+
+#define BD71847_BUCK3_MASK 0x07
+#define BD71847_BUCK3_RANGE_MASK 0xc0
+#define BD71847_BUCK4_MASK 0x03
+#define BD71847_BUCK4_RANGE_MASK 0x40
+
+#define BD71837_BUCK5_RANGE_MASK 0x80
+#define BD71837_BUCK6_MASK 0x03
+
+#define BD718XX_LDO1_MASK 0x03
+#define BD718XX_LDO1_RANGE_MASK 0x20
+#define BD718XX_LDO2_MASK 0x20
+#define BD718XX_LDO3_MASK 0x0f
+#define BD718XX_LDO4_MASK 0x0f
+#define BD718XX_LDO6_MASK 0x0f
+
+#define BD71837_LDO5_MASK 0x0f
+#define BD71847_LDO5_MASK 0x0f
+#define BD71847_LDO5_RANGE_MASK 0x20
+#define BD71837_LDO7_MASK 0x0f
+
#endif
diff --git a/include/power/stpmic1.h b/include/power/stpmic1.h
index 0e6721d..dc8b5a7 100644
--- a/include/power/stpmic1.h
+++ b/include/power/stpmic1.h
@@ -22,11 +22,12 @@
/* BUCKS_MRST_CR */
#define STPMIC1_MRST_BUCK(buck) BIT(buck)
-#define STPMIC1_MRST_BUCK_ALL GENMASK(3, 0)
+#define STPMIC1_MRST_BUCK_DEBUG (STPMIC1_MRST_BUCK(STPMIC1_BUCK1) | \
+ STPMIC1_MRST_BUCK(STPMIC1_BUCK3))
/* LDOS_MRST_CR */
#define STPMIC1_MRST_LDO(ldo) BIT(ldo)
-#define STPMIC1_MRST_LDO_ALL GENMASK(6, 0)
+#define STPMIC1_MRST_LDO_DEBUG 0
/* BUCKx_MAIN_CR (x=1...4) */
#define STPMIC1_BUCK_ENA BIT(0)
@@ -107,11 +108,4 @@
STPMIC1_PWR_SW2,
STPMIC1_MAX_PWR_SW,
};
-
-int stpmic1_shadow_read_byte(u8 addr, u8 *buf);
-int stpmic1_shadow_write_byte(u8 addr, u8 *buf);
-int stpmic1_nvm_read_byte(u8 addr, u8 *buf);
-int stpmic1_nvm_write_byte(u8 addr, u8 *buf);
-int stpmic1_nvm_read_all(u8 *buf, int buf_len);
-int stpmic1_nvm_write_all(u8 *buf, int buf_len);
#endif
diff --git a/include/regmap.h b/include/regmap.h
index 3cd7a66..0854200 100644
--- a/include/regmap.h
+++ b/include/regmap.h
@@ -330,6 +330,8 @@
int regmap_init_mem_platdata(struct udevice *dev, fdt_val_t *reg, int count,
struct regmap **mapp);
+int regmap_init_mem_index(ofnode node, struct regmap **mapp, int index);
+
/**
* regmap_get_range() - Obtain the base memory address of a regmap range
*
diff --git a/include/remoteproc.h b/include/remoteproc.h
index a59dba8..4987194 100644
--- a/include/remoteproc.h
+++ b/include/remoteproc.h
@@ -45,117 +45,181 @@
};
/**
- * struct dm_rproc_ops - Operations that are provided by remote proc driver
- * @init: Initialize the remoteproc device invoked after probe (optional)
- * Return 0 on success, -ve error on fail
- * @load: Load the remoteproc device using data provided(mandatory)
- * This takes the following additional arguments.
- * addr- Address of the binary image to be loaded
- * size- Size of the binary image to be loaded
- * Return 0 on success, -ve error on fail
- * @start: Start the remoteproc device (mandatory)
- * Return 0 on success, -ve error on fail
- * @stop: Stop the remoteproc device (optional)
- * Return 0 on success, -ve error on fail
- * @reset: Reset the remote proc device (optional)
- * Return 0 on success, -ve error on fail
- * @is_running: Check if the remote processor is running(optional)
- * Return 0 on success, 1 if not running, -ve on others errors
- * @ping: Ping the remote device for basic communication check(optional)
- * Return 0 on success, 1 if not responding, -ve on other errors
+ * struct dm_rproc_ops - Driver model remote proc operations.
+ *
+ * This defines the operations provided by remote proc driver.
*/
struct dm_rproc_ops {
+ /**
+ * init() - Initialize the remoteproc device (optional)
+ *
+ * This is called after the probe is completed allowing the remote
+ * processor drivers to split up the initializations between probe and
+ * init if needed.
+ *
+ * @dev: Remote proc device
+ * @return 0 if all ok, else appropriate error value.
+ */
int (*init)(struct udevice *dev);
+
+ /**
+ * load() - Load the remoteproc device using data provided (mandatory)
+ *
+ * Load the remoteproc device with an image, do not start the device.
+ *
+ * @dev: Remote proc device
+ * @addr: Address of the image to be loaded
+ * @size: Size of the image to be loaded
+ * @return 0 if all ok, else appropriate error value.
+ */
int (*load)(struct udevice *dev, ulong addr, ulong size);
+
+ /**
+ * start() - Start the remoteproc device (mandatory)
+ *
+ * @dev: Remote proc device
+ * @return 0 if all ok, else appropriate error value.
+ */
int (*start)(struct udevice *dev);
+
+ /**
+ * stop() - Stop the remoteproc device (optional)
+ *
+ * @dev: Remote proc device
+ * @return 0 if all ok, else appropriate error value.
+ */
int (*stop)(struct udevice *dev);
+
+ /**
+ * reset() - Reset the remoteproc device (optional)
+ *
+ * @dev: Remote proc device
+ * @return 0 if all ok, else appropriate error value.
+ */
int (*reset)(struct udevice *dev);
+
+ /**
+ * is_running() - Check if the remote processor is running (optional)
+ *
+ * @dev: Remote proc device
+ * @return 0 if running, 1 if not running, -ve on error.
+ */
int (*is_running)(struct udevice *dev);
+
+ /**
+ * ping() - Ping the remote device for basic communication (optional)
+ *
+ * @dev: Remote proc device
+ * @return 0 on success, 1 if not responding, -ve on other errors.
+ */
int (*ping)(struct udevice *dev);
+
+ /**
+ * device_to_virt() - Return translated virtual address (optional)
+ *
+ * Translate a device address (remote processor view) to virtual
+ * address (main processor view).
+ *
+ * @dev: Remote proc device
+ * @da: Device address
+ * @return virtual address.
+ */
+ void * (*device_to_virt)(struct udevice *dev, ulong da);
};
/* Accessor */
#define rproc_get_ops(dev) ((struct dm_rproc_ops *)(dev)->driver->ops)
-#ifdef CONFIG_REMOTEPROC
+#if CONFIG_IS_ENABLED(REMOTEPROC)
/**
* rproc_init() - Initialize all bound remote proc devices
- *
- * Return: 0 if all ok, else appropriate error value.
+ * @return 0 if all ok, else appropriate error value.
*/
int rproc_init(void);
/**
* rproc_dev_init() - Initialize a remote proc device based on id
* @id: id of the remote processor
- *
- * Return: 0 if all ok, else appropriate error value.
+ * @return 0 if all ok, else appropriate error value.
*/
int rproc_dev_init(int id);
/**
* rproc_is_initialized() - check to see if remoteproc devices are initialized
- *
- * Return: 0 if all devices are initialized, else appropriate error value.
+ * @return true if all devices are initialized, false otherwise.
*/
bool rproc_is_initialized(void);
/**
- * rproc_load() - load binary to a remote processor
+ * rproc_load() - load binary or elf to a remote processor
* @id: id of the remote processor
- * @addr: address in memory where the binary image is located
- * @size: size of the binary image
- *
- * Return: 0 if all ok, else appropriate error value.
+ * @addr: address in memory where the image is located
+ * @size: size of the image
+ * @return 0 if all ok, else appropriate error value.
*/
int rproc_load(int id, ulong addr, ulong size);
/**
* rproc_start() - Start a remote processor
* @id: id of the remote processor
- *
- * Return: 0 if all ok, else appropriate error value.
+ * @return 0 if all ok, else appropriate error value.
*/
int rproc_start(int id);
/**
* rproc_stop() - Stop a remote processor
* @id: id of the remote processor
- *
- * Return: 0 if all ok, else appropriate error value.
+ * @return 0 if all ok, else appropriate error value.
*/
int rproc_stop(int id);
/**
* rproc_reset() - reset a remote processor
* @id: id of the remote processor
- *
- * Return: 0 if all ok, else appropriate error value.
+ * @return 0 if all ok, else appropriate error value.
*/
int rproc_reset(int id);
/**
* rproc_ping() - ping a remote processor to check if it can communicate
* @id: id of the remote processor
+ * @return 0 if all ok, else appropriate error value.
*
* NOTE: this might need communication path available, which is not implemented
* as part of remoteproc framework - hook on to appropriate bus architecture to
* do the same
- *
- * Return: 0 if all ok, else appropriate error value.
*/
int rproc_ping(int id);
/**
* rproc_is_running() - check to see if remote processor is running
* @id: id of the remote processor
+ * @return 0 if running, 1 if not running, -ve on error.
*
* NOTE: this may not involve actual communication capability of the remote
* processor, but just ensures that it is out of reset and executing code.
- *
- * Return: 0 if all ok, else appropriate error value.
*/
int rproc_is_running(int id);
+
+/**
+ * rproc_elf32_sanity_check() - Verify if an image is a valid ELF32 one
+ *
+ * Check if a valid ELF32 image exists at the given memory location. Verify
+ * basic ELF32 format requirements like magic number and sections size.
+ *
+ * @addr: address of the image to verify
+ * @size: size of the image
+ * @return 0 if the image looks good, else appropriate error value.
+ */
+int rproc_elf32_sanity_check(ulong addr, ulong size);
+
+/**
+ * rproc_elf32_load_image() - load an ELF32 image
+ * @dev: device loading the ELF32 image
+ * @addr: valid ELF32 image address
+ * @return 0 if the image is successfully loaded, else appropriate error value.
+ */
+int rproc_elf32_load_image(struct udevice *dev, unsigned long addr);
#else
static inline int rproc_init(void) { return -ENOSYS; }
static inline int rproc_dev_init(int id) { return -ENOSYS; }
@@ -166,6 +230,10 @@
static inline int rproc_reset(int id) { return -ENOSYS; }
static inline int rproc_ping(int id) { return -ENOSYS; }
static inline int rproc_is_running(int id) { return -ENOSYS; }
+static inline int rproc_elf32_sanity_check(ulong addr,
+ ulong size) { return -ENOSYS; }
+static inline int rproc_elf32_load_image(struct udevice *dev,
+ unsigned long addr) { return -ENOSYS; }
#endif
#endif /* _RPROC_H_ */
diff --git a/include/rtc.h b/include/rtc.h
index b255bdc..7386d52 100644
--- a/include/rtc.h
+++ b/include/rtc.h
@@ -166,11 +166,17 @@
*/
int rtc_write32(struct udevice *dev, unsigned int reg, u32 value);
+#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT
+int rtc_enable_32khz_output(int busnum, int chip_addr);
+#endif
+
#else
int rtc_get (struct rtc_time *);
int rtc_set (struct rtc_time *);
void rtc_reset (void);
+#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT
void rtc_enable_32khz_output(void);
+#endif
/**
* rtc_read8() - Read an 8-bit register
diff --git a/include/sandbox-clk.h b/include/sandbox-clk.h
new file mode 100644
index 0000000..296cddf
--- /dev/null
+++ b/include/sandbox-clk.h
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ */
+
+#ifndef __SANDBOX_CLK_H__
+#define __SANDBOX_CLK_H__
+
+#include <linux/clk-provider.h>
+
+enum {
+ SANDBOX_CLK_PLL2 = 1,
+ SANDBOX_CLK_PLL3,
+ SANDBOX_CLK_PLL3_60M,
+ SANDBOX_CLK_PLL3_80M,
+ SANDBOX_CLK_ECSPI_ROOT,
+ SANDBOX_CLK_ECSPI0,
+ SANDBOX_CLK_ECSPI1,
+ SANDBOX_CLK_USDHC1_SEL,
+ SANDBOX_CLK_USDHC2_SEL,
+ SANDBOX_CLK_I2C,
+ SANDBOX_CLK_I2C_ROOT,
+};
+
+enum sandbox_pllv3_type {
+ SANDBOX_PLLV3_GENERIC,
+ SANDBOX_PLLV3_USB,
+};
+
+struct clk *sandbox_clk_pllv3(enum sandbox_pllv3_type type, const char *name,
+ const char *parent_name, void __iomem *base,
+ u32 div_mask);
+
+static inline struct clk *sandbox_clk_fixed_factor(const char *name,
+ const char *parent,
+ unsigned int mult,
+ unsigned int div)
+{
+ return clk_register_fixed_factor(NULL, name, parent,
+ CLK_SET_RATE_PARENT, mult, div);
+}
+
+static inline struct clk *sandbox_clk_divider(const char *name,
+ const char *parent,
+ void __iomem *reg, u8 shift,
+ u8 width)
+{
+ return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
+ reg, shift, width, 0);
+}
+
+struct clk *sandbox_clk_register_gate2(struct device *dev, const char *name,
+ const char *parent_name,
+ unsigned long flags,
+ void __iomem *reg, u8 bit_idx,
+ u8 cgr_val, u8 clk_gate_flags);
+
+static inline struct clk *sandbox_clk_gate2(const char *name,
+ const char *parent,
+ void __iomem *reg, u8 shift)
+{
+ return sandbox_clk_register_gate2(NULL, name, parent,
+ CLK_SET_RATE_PARENT, reg, shift,
+ 0x3, 0);
+}
+
+static inline struct clk *sandbox_clk_mux(const char *name, void __iomem *reg,
+ u8 shift, u8 width,
+ const char * const *parents,
+ int num_parents)
+{
+ return clk_register_mux(NULL, name, parents, num_parents,
+ CLK_SET_RATE_NO_REPARENT, reg, shift,
+ width, 0);
+}
+
+int sandbox_clk_enable_count(struct clk *clk);
+
+#endif /* __SANDBOX_CLK_H__ */
diff --git a/include/sdhci.h b/include/sdhci.h
index eee493a..01addb7 100644
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -144,7 +144,23 @@
#define SDHCI_ACMD12_ERR 0x3C
-/* 3E-3F reserved */
+#define SDHCI_HOST_CONTROL2 0x3E
+#define SDHCI_CTRL_UHS_MASK 0x0007
+#define SDHCI_CTRL_UHS_SDR12 0x0000
+#define SDHCI_CTRL_UHS_SDR25 0x0001
+#define SDHCI_CTRL_UHS_SDR50 0x0002
+#define SDHCI_CTRL_UHS_SDR104 0x0003
+#define SDHCI_CTRL_UHS_DDR50 0x0004
+#define SDHCI_CTRL_HS400 0x0005 /* Non-standard */
+#define SDHCI_CTRL_VDD_180 0x0008
+#define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
+#define SDHCI_CTRL_DRV_TYPE_B 0x0000
+#define SDHCI_CTRL_DRV_TYPE_A 0x0010
+#define SDHCI_CTRL_DRV_TYPE_C 0x0020
+#define SDHCI_CTRL_DRV_TYPE_D 0x0030
+#define SDHCI_CTRL_EXEC_TUNING 0x0040
+#define SDHCI_CTRL_TUNED_CLK 0x0080
+#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
#define SDHCI_CAPABILITIES 0x40
#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
@@ -247,7 +263,7 @@
#endif
int (*get_cd)(struct sdhci_host *host);
void (*set_control_reg)(struct sdhci_host *host);
- void (*set_ios_post)(struct sdhci_host *host);
+ int (*set_ios_post)(struct sdhci_host *host);
void (*set_clock)(struct sdhci_host *host, u32 div);
int (*platform_execute_tuning)(struct mmc *host, u8 opcode);
void (*set_delay)(struct sdhci_host *host);
@@ -467,9 +483,11 @@
int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min);
#endif /* !CONFIG_BLK */
+void sdhci_set_uhs_timing(struct sdhci_host *host);
#ifdef CONFIG_DM_MMC
/* Export the operations to drivers */
int sdhci_probe(struct udevice *dev);
+int sdhci_set_clock(struct mmc *mmc, unsigned int clock);
extern const struct dm_mmc_ops sdhci_ops;
#else
#endif
diff --git a/include/search.h b/include/search.h
index 5d07b49..0469a85 100644
--- a/include/search.h
+++ b/include/search.h
@@ -14,32 +14,25 @@
#ifndef _SEARCH_H_
#define _SEARCH_H_
+#include <env.h>
#include <stddef.h>
-#define __set_errno(val) do { errno = val; } while (0)
+#define set_errno(val) do { errno = val; } while (0)
-enum env_op {
- env_op_create,
- env_op_delete,
- env_op_overwrite,
+/* enum env_action: action which shall be performed in the call to hsearch */
+enum env_action {
+ ENV_FIND,
+ ENV_ENTER,
};
-/* Action which shall be performed in the call to hsearch. */
-typedef enum {
- FIND,
- ENTER
-} ACTION;
-
-typedef struct entry {
+/** struct env_entry - An entry in the environment hashtable */
+struct env_entry {
const char *key;
char *data;
int (*callback)(const char *name, const char *value, enum env_op op,
int flags);
int flags;
-} ENTRY;
-
-/* Opaque type for internal use. */
-struct _ENTRY;
+};
/*
* Family of hash table handling functions. The functions also
@@ -49,61 +42,59 @@
/* Data type for reentrant functions. */
struct hsearch_data {
- struct _ENTRY *table;
+ struct env_entry_node *table;
unsigned int size;
unsigned int filled;
/*
* Callback function which will check whether the given change for variable
- * "__item" to "newval" may be applied or not, and possibly apply such change.
+ * "item" to "newval" may be applied or not, and possibly apply such change.
* When (flag & H_FORCE) is set, it shall not print out any error message and
* shall force overwriting of write-once variables.
* Must return 0 for approval, 1 for denial.
*/
- int (*change_ok)(const ENTRY *__item, const char *newval, enum env_op,
- int flag);
+ int (*change_ok)(const struct env_entry *item, const char *newval,
+ enum env_op, int flag);
};
-/* Create a new hash table which will contain at most "__nel" elements. */
-extern int hcreate_r(size_t __nel, struct hsearch_data *__htab);
+/* Create a new hash table which will contain at most "nel" elements. */
+int hcreate_r(size_t nel, struct hsearch_data *htab);
/* Destroy current internal hash table. */
-extern void hdestroy_r(struct hsearch_data *__htab);
+void hdestroy_r(struct hsearch_data *htab);
/*
- * Search for entry matching __item.key in internal hash table. If
- * ACTION is `FIND' return found entry or signal error by returning
- * NULL. If ACTION is `ENTER' replace existing data (if any) with
- * __item.data.
+ * Search for entry matching item.key in internal hash table. If
+ * action is `ENV_FIND' return found entry or signal error by returning
+ * NULL. If action is `ENV_ENTER' replace existing data (if any) with
+ * item.data.
* */
-extern int hsearch_r(ENTRY __item, ACTION __action, ENTRY ** __retval,
- struct hsearch_data *__htab, int __flag);
+int hsearch_r(struct env_entry item, enum env_action action,
+ struct env_entry **retval, struct hsearch_data *htab, int flag);
/*
- * Search for an entry matching "__match". Otherwise, Same semantics
+ * Search for an entry matching "match". Otherwise, Same semantics
* as hsearch_r().
*/
-extern int hmatch_r(const char *__match, int __last_idx, ENTRY ** __retval,
- struct hsearch_data *__htab);
+int hmatch_r(const char *match, int last_idx, struct env_entry **retval,
+ struct hsearch_data *htab);
-/* Search and delete entry matching "__key" in internal hash table. */
-extern int hdelete_r(const char *__key, struct hsearch_data *__htab,
- int __flag);
+/* Search and delete entry matching "key" in internal hash table. */
+int hdelete_r(const char *key, struct hsearch_data *htab, int flag);
-extern ssize_t hexport_r(struct hsearch_data *__htab,
- const char __sep, int __flag, char **__resp, size_t __size,
- int argc, char * const argv[]);
+ssize_t hexport_r(struct hsearch_data *htab, const char sep, int flag,
+ char **resp, size_t size, int argc, char * const argv[]);
/*
* nvars: length of vars array
* vars: array of strings (variable names) to import (nvars == 0 means all)
*/
-extern int himport_r(struct hsearch_data *__htab,
- const char *__env, size_t __size, const char __sep,
- int __flag, int __crlf_is_lf, int nvars,
- char * const vars[]);
+int himport_r(struct hsearch_data *htab, const char *env, size_t size,
+ const char sep, int flag, int crlf_is_lf, int nvars,
+ char * const vars[]);
/* Walk the whole table calling the callback on each element */
-extern int hwalk_r(struct hsearch_data *__htab, int (*callback)(ENTRY *));
+int hwalk_r(struct hsearch_data *htab,
+ int (*callback)(struct env_entry *entry));
/* Flags for himport_r(), hexport_r(), hdelete_r(), and hsearch_r() */
#define H_NOCLEAR (1 << 0) /* do not clear hash table before importing */
diff --git a/include/spi.h b/include/spi.h
index 3785941..5eec0c4 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -248,6 +248,26 @@
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
void *din, unsigned long flags);
+/**
+ * spi_write_then_read - SPI synchronous write followed by read
+ *
+ * This performs a half duplex transaction in which the first transaction
+ * is to send the opcode and if the length of buf is non-zero then it start
+ * the second transaction as tx or rx based on the need from respective slave.
+ *
+ * @slave: The SPI slave device with which opcode/data will be exchanged
+ * @opcode: opcode used for specific transfer
+ * @n_opcode: size of opcode, in bytes
+ * @txbuf: buffer into which data to be written
+ * @rxbuf: buffer into which data will be read
+ * @n_buf: size of buf (whether it's [tx|rx]buf), in bytes
+ *
+ * Returns: 0 on success, not 0 on failure
+ */
+int spi_write_then_read(struct spi_slave *slave, const u8 *opcode,
+ size_t n_opcode, const u8 *txbuf, u8 *rxbuf,
+ size_t n_buf);
+
/* Copy memory mapped data */
void spi_flash_copy_mmap(void *data, void *offset, size_t len);
diff --git a/include/spl.h b/include/spl.h
index a9aaef3..e4640f3 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -109,6 +109,15 @@
binman_sym_extern(ulong, u_boot_any, image_pos);
/**
+ * spl_load_simple_fit_skip_processing() - Hook to allow skipping the FIT
+ * image processing during spl_load_simple_fit().
+ *
+ * Return true to skip FIT processing, false to preserve the full code flow
+ * of spl_load_simple_fit().
+ */
+bool spl_load_simple_fit_skip_processing(void);
+
+/**
* spl_load_simple_fit() - Loads a fit image from a device.
* @spl_image: Image description to set up
* @info: Structure containing the information required to load data.
@@ -331,6 +340,23 @@
struct spl_boot_device *bootdev);
/**
+ * spl_mmc_load() - Load an image file from MMC/SD media
+ *
+ * @param spl_image Image data filled in by loading process
+ * @param bootdev Describes which device to load from
+ * @param filename Name of file to load (in FS mode)
+ * @param raw_part Partition to load from (in RAW mode)
+ * @param raw_sect Sector to load from (in RAW mode)
+ *
+ * @return 0 on success, otherwise error code
+ */
+int spl_mmc_load(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev,
+ const char *filename,
+ int raw_part,
+ unsigned long raw_sect);
+
+/**
* spl_invoke_atf - boot using an ARM trusted firmware image
*/
void spl_invoke_atf(struct spl_image_info *spl_image);
@@ -349,6 +375,11 @@
void spl_optee_entry(void *arg0, void *arg1, void *arg2, void *arg3);
/**
+ * spl_invoke_opensbi - boot using a RISC-V OpenSBI image
+ */
+void spl_invoke_opensbi(struct spl_image_info *spl_image);
+
+/**
* board_return_to_bootrom - allow for boards to continue with the boot ROM
*
* If a board (e.g. the Rockchip RK3368 boards) provide some
diff --git a/include/trace.h b/include/trace.h
index 99f34f7..606dba9 100644
--- a/include/trace.h
+++ b/include/trace.h
@@ -39,7 +39,7 @@
/* A header at the start of the trace output buffer */
struct trace_output_hdr {
enum trace_chunk_type type; /* Record type */
- uint32_t rec_count; /* Number of records */
+ size_t rec_count; /* Number of records */
};
/* Print statistics about traced function calls */
@@ -57,7 +57,7 @@
* @param needed Returns number of bytes used / needed
* @return 0 if ok, -1 on error (buffer exhausted)
*/
-int trace_list_functions(void *buff, int buff_size, unsigned *needed);
+int trace_list_functions(void *buff, size_t buff_size, size_t *needed);
/* Flags for ftrace_record */
enum ftrace_flags {
@@ -77,7 +77,7 @@
uint32_t flags; /* Flags and timestamp */
};
-int trace_list_calls(void *buff, int buff_size, unsigned int *needed);
+int trace_list_calls(void *buff, size_t buff_size, size_t *needed);
/**
* Turn function tracing on and off
diff --git a/include/tsec.h b/include/tsec.h
index e900951..b17fa95 100644
--- a/include/tsec.h
+++ b/include/tsec.h
@@ -17,6 +17,8 @@
#include <config.h>
#include <phy.h>
+#define TSEC_MDIO_REGS_OFFSET 0x520
+
#ifndef CONFIG_DM_ETH
#ifdef CONFIG_ARCH_LS1021A
@@ -27,7 +29,7 @@
#define TSEC_MDIO_OFFSET 0x01000
#endif
-#define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520)
+#define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + TSEC_MDIO_REGS_OFFSET)
#define TSEC_GET_REGS(num, offset) \
(struct tsec __iomem *)\
diff --git a/include/ubispl.h b/include/ubispl.h
index 1e5da94..ecfe0c9 100644
--- a/include/ubispl.h
+++ b/include/ubispl.h
@@ -5,6 +5,8 @@
#ifndef __UBOOT_UBISPL_H
#define __UBOOT_UBISPL_H
+#define UBI_VOL_NAME_MAX 127
+
/*
* The following CONFIG options are relevant for UBISPL
*
@@ -74,6 +76,10 @@
*/
struct ubispl_load {
int vol_id;
+#ifdef CONFIG_SPL_UBI_LOAD_BY_VOLNAME
+ u32 name_len;
+ char name[UBI_VOL_NAME_MAX + 1];
+#endif
void *load_addr;
};
diff --git a/include/usb.h b/include/usb.h
index 420a30e..bcad552 100644
--- a/include/usb.h
+++ b/include/usb.h
@@ -184,7 +184,7 @@
int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
int transfer_len, struct devrequest *setup);
int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len, int interval);
+ int transfer_len, int interval, bool nonblock);
#if defined CONFIG_USB_EHCI_HCD || defined CONFIG_USB_MUSB_HOST \
|| CONFIG_IS_ENABLED(DM_USB)
@@ -261,8 +261,8 @@
void *data, unsigned short size, int timeout);
int usb_bulk_msg(struct usb_device *dev, unsigned int pipe,
void *data, int len, int *actual_length, int timeout);
-int usb_submit_int_msg(struct usb_device *dev, unsigned long pipe,
- void *buffer, int transfer_len, int interval);
+int usb_int_msg(struct usb_device *dev, unsigned long pipe,
+ void *buffer, int transfer_len, int interval, bool nonblock);
int usb_disable_asynch(int disable);
int usb_maxpacket(struct usb_device *dev, unsigned long pipe);
int usb_get_configuration_no(struct usb_device *dev, int cfgno,
@@ -708,7 +708,7 @@
*/
int (*interrupt)(struct udevice *bus, struct usb_device *udev,
unsigned long pipe, void *buffer, int length,
- int interval);
+ int interval, bool nonblock);
/**
* create_int_queue() - Create and queue interrupt packets
@@ -1029,7 +1029,8 @@
* @return 0 if OK, -ve on error
*/
int usb_emul_int(struct udevice *emul, struct usb_device *udev,
- unsigned long pipe, void *buffer, int length, int interval);
+ unsigned long pipe, void *buffer, int length, int interval,
+ bool nonblock);
/**
* usb_emul_find() - Find an emulator for a particular device
diff --git a/include/video_logo.h b/include/video_logo.h
deleted file mode 100644
index a0d2da4..0000000
--- a/include/video_logo.h
+++ /dev/null
@@ -1,1951 +0,0 @@
-/* */
-/* Generated by EasyLogo, (C) 2000 by Paolo Scaffardi */
-/* */
-/* To use this, include it and call: easylogo_plot(screen,&u_boot_logo, width,x,y) */
-/* */
-/* Where: 'screen' is the pointer to the frame buffer */
-/* 'width' is the screen width */
-/* 'x' is the horizontal position */
-/* 'y' is the vertical position */
-/* */
-
-#include <video_easylogo.h>
-
-#define DEF_U_BOOT_LOGO_WIDTH 160
-#define DEF_U_BOOT_LOGO_HEIGHT 96
-#define DEF_U_BOOT_LOGO_PIXELS 15360
-#define DEF_U_BOOT_LOGO_BPP 16
-#define DEF_U_BOOT_LOGO_PIXEL_SIZE 2
-#define DEF_U_BOOT_LOGO_SIZE 30720
-
-unsigned char DEF_U_BOOT_LOGO_DATA[DEF_U_BOOT_LOGO_SIZE] = {
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xb6,
- 0x80, 0xb6, 0x80, 0xb6, 0x80, 0xb6, 0x80, 0xb6, 0x80, 0xb6, 0x80, 0xb6, 0x80, 0xb6, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
- 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
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- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
- 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
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- 0x80, 0xe1, 0x7c, 0x69, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
- 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7e, 0xaa, 0x7a, 0x3f,
- 0x7c, 0x69, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xb6, 0x7a, 0x3f, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
- 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xc0, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x7c, 0x69, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
- 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7e, 0xaa, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xc0, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7b, 0x60, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x7b, 0x60, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7d, 0x80, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7b, 0x60, 0x7a, 0x3f,
- 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7c, 0x4b, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xd5, 0x7a, 0x3f, 0x7d, 0x80, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7e, 0xaa, 0x7a, 0x3f, 0x7e, 0xa0, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7c, 0x4b, 0x7a, 0x3f, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7c, 0x4b, 0x7c, 0x69,
- 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7d, 0x80, 0x7a, 0x3f, 0x7a, 0x3f,
- 0x7a, 0x3f, 0x7c, 0x69, 0x7b, 0x60, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1
-};
-
-fastimage_t u_boot_logo = {
- DEF_U_BOOT_LOGO_DATA,
- DEF_U_BOOT_LOGO_WIDTH,
- DEF_U_BOOT_LOGO_HEIGHT,
- DEF_U_BOOT_LOGO_BPP,
- DEF_U_BOOT_LOGO_PIXEL_SIZE,
- DEF_U_BOOT_LOGO_SIZE
-};
diff --git a/include/virtex2.h b/include/virtex2.h
index a481130..7e8d93f 100644
--- a/include/virtex2.h
+++ b/include/virtex2.h
@@ -11,7 +11,7 @@
#include <xilinx.h>
/*
- * Slave SelectMap Implementation function table.
+ * Slave SelectMap or Serial Implementation function table.
*/
typedef struct {
xilinx_pre_fn pre;
@@ -24,18 +24,11 @@
xilinx_wr_fn wr;
xilinx_rdata_fn rdata;
xilinx_wdata_fn wdata;
+ xilinx_bwr_fn wbulkdata;
xilinx_busy_fn busy;
xilinx_abort_fn abort;
xilinx_post_fn post;
-} xilinx_virtex2_slave_selectmap_fns;
-
-/* Slave Serial Implementation function table */
-typedef struct {
- xilinx_pgm_fn pgm;
- xilinx_clk_fn clk;
- xilinx_rdata_fn rdata;
- xilinx_wdata_fn wdata;
-} xilinx_virtex2_slave_serial_fns;
+} xilinx_virtex2_slave_fns;
#if defined(CONFIG_FPGA_VIRTEX2)
extern struct xilinx_fpga_op virtex2_op;
diff --git a/include/watchdog.h b/include/watchdog.h
index 3a357de..a4a4e8e 100644
--- a/include/watchdog.h
+++ b/include/watchdog.h
@@ -77,7 +77,7 @@
* Prototypes from $(CPU)/cpu.c.
*/
-#if defined(CONFIG_HW_WATCHDOG) && !defined(__ASSEMBLY__)
+#if (defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)) && !defined(__ASSEMBLY__)
void hw_watchdog_init(void);
#endif
diff --git a/include/wdt.h b/include/wdt.h
index aa77d3e..5bcff24 100644
--- a/include/wdt.h
+++ b/include/wdt.h
@@ -106,7 +106,7 @@
int (*expire_now)(struct udevice *dev, ulong flags);
};
-#if defined(CONFIG_WDT)
+#if CONFIG_IS_ENABLED(WDT)
#ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
#define CONFIG_WATCHDOG_TIMEOUT_MSECS (60 * 1000)
#endif
diff --git a/lib/Kconfig b/lib/Kconfig
index 416e63c..3da45a5 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -97,6 +97,8 @@
config USE_TINY_PRINTF
bool "Enable tiny printf() version"
+ depends on SPL || TPL
+ default y
help
This option enables a tiny, stripped down printf version.
This should only be used in space limited environments,
@@ -192,6 +194,13 @@
the size is too small then 'trace stats' will show a message saying
how many records were dropped due to buffer overflow.
+config TRACE_CALL_DEPTH_LIMIT
+ int "Trace call depth limit"
+ depends on TRACE
+ default 15
+ help
+ Sets the maximum call depth up to which function calls are recorded.
+
config TRACE_EARLY
bool "Enable tracing before relocation"
depends on TRACE
@@ -209,6 +218,14 @@
Sets the size of the early trace buffer in bytes. This is used to hold
tracing information before relocation.
+config TRACE_EARLY_CALL_DEPTH_LIMIT
+ int "Early trace call depth limit"
+ depends on TRACE_EARLY
+ default 200
+ help
+ Sets the maximum call depth up to which function calls are recorded
+ during early tracing.
+
config TRACE_EARLY_ADDR
hex "Address of early trace buffer in U-Boot"
depends on TRACE_EARLY
diff --git a/lib/charset.c b/lib/charset.c
index 5e349ed..1c6a7f6 100644
--- a/lib/charset.c
+++ b/lib/charset.c
@@ -335,11 +335,41 @@
return ret;
}
-size_t u16_strlen(const u16 *in)
+/*
+ * u16_strncmp() - compare two u16 string
+ *
+ * @s1: first string to compare
+ * @s2: second string to compare
+ * @n: maximum number of u16 to compare
+ * Return: 0 if the first n u16 are the same in s1 and s2
+ * < 0 if the first different u16 in s1 is less than the
+ * corresponding u16 in s2
+ * > 0 if the first different u16 in s1 is greater than the
+ * corresponding u16 in s2
+ */
+int u16_strncmp(const u16 *s1, const u16 *s2, size_t n)
{
- size_t i;
- for (i = 0; in[i]; i++);
- return i;
+ int ret = 0;
+
+ for (; n; --n, ++s1, ++s2) {
+ ret = *s1 - *s2;
+ if (ret || !*s1)
+ break;
+ }
+
+ return ret;
+}
+
+size_t u16_strlen(const void *in)
+{
+ const char *pos = in;
+ size_t ret;
+
+ for (; pos[0] || pos[1]; pos += 2)
+ ;
+ ret = pos - (char *)in;
+ ret >>= 1;
+ return ret;
}
size_t u16_strnlen(const u16 *in, size_t count)
@@ -362,18 +392,18 @@
return tmp;
}
-u16 *u16_strdup(const u16 *src)
+u16 *u16_strdup(const void *src)
{
u16 *new;
+ size_t len;
if (!src)
return NULL;
-
- new = malloc((u16_strlen(src) + 1) * sizeof(u16));
+ len = (u16_strlen(src) + 1) * sizeof(u16);
+ new = malloc(len);
if (!new)
return NULL;
-
- u16_strcpy(new, src);
+ memcpy(new, src, len);
return new;
}
diff --git a/lib/efi_driver/efi_block_device.c b/lib/efi_driver/efi_block_device.c
index 3f147cf..cf02341 100644
--- a/lib/efi_driver/efi_block_device.c
+++ b/lib/efi_driver/efi_block_device.c
@@ -43,14 +43,14 @@
struct efi_block_io *io;
};
-/*
+/**
* Read from block device
*
- * @dev device
- * @blknr first block to be read
- * @blkcnt number of blocks to read
- * @buffer output buffer
- * @return number of blocks transferred
+ * @dev: device
+ * @blknr: first block to be read
+ * @blkcnt: number of blocks to read
+ * @buffer: output buffer
+ * Return: number of blocks transferred
*/
static ulong efi_bl_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
void *buffer)
@@ -72,14 +72,14 @@
return blkcnt;
}
-/*
+/**
* Write to block device
*
- * @dev device
- * @blknr first block to be write
- * @blkcnt number of blocks to write
- * @buffer input buffer
- * @return number of blocks transferred
+ * @dev: device
+ * @blknr: first block to be write
+ * @blkcnt: number of blocks to write
+ * @buffer: input buffer
+ * Return: number of blocks transferred
*/
static ulong efi_bl_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
const void *buffer)
@@ -102,11 +102,12 @@
return blkcnt;
}
-/*
+/**
* Create partions for the block device.
*
- * @handle EFI handle of the block device
- * @dev udevice of the block device
+ * @handle: EFI handle of the block device
+ * @dev: udevice of the block device
+ * Return: number of partitions created
*/
static int efi_bl_bind_partitions(efi_handle_t handle, struct udevice *dev)
{
@@ -120,12 +121,12 @@
desc->devnum, dev->name);
}
-/*
+/**
* Create a block device for a handle
*
- * @handle handle
- * @interface block io protocol
- * @return 0 = success
+ * @handle: handle
+ * @interface: block io protocol
+ * Return: 0 = success
*/
static int efi_bl_bind(efi_handle_t handle, void *interface)
{
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index cd5436c..c7027a9 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -101,4 +101,18 @@
RFC 4646 format, e.g. "en-US;de-DE". The first language code is used
to initialize the PlatformLang variable.
+config EFI_HAVE_RUNTIME_RESET
+ # bool "Reset runtime service is available"
+ bool
+ default y
+ depends on ARCH_BCM283X || FSL_LAYERSCAPE || PSCI_RESET || SYSRESET_X86
+
+config EFI_GRUB_ARM32_WORKAROUND
+ bool "Workaround for GRUB on 32bit ARM"
+ default y
+ depends on ARM && !ARM64
+ help
+ GRUB prior to version 2.04 requires U-Boot to disable caches. This
+ workaround currently is also needed on systems with caches that
+ cannot be managed via CP15.
endif
diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c
index b2102c5..2ea2144 100644
--- a/lib/efi_loader/efi_bootmgr.c
+++ b/lib/efi_loader/efi_bootmgr.c
@@ -27,7 +27,15 @@
*/
-/* Parse serialized data and transform it into efi_load_option structure */
+/**
+ * efi_deserialize_load_option() - parse serialized data
+ *
+ * Parse serialized data describing a load option and transform it to the
+ * efi_load_option structure.
+ *
+ * @lo: pointer to target
+ * @data: serialized data
+ */
void efi_deserialize_load_option(struct efi_load_option *lo, u8 *data)
{
lo->attributes = get_unaligned_le32(data);
@@ -47,9 +55,14 @@
lo->optional_data = data;
}
-/*
+/**
+ * efi_serialize_load_option() - serialize load option
+ *
* Serialize efi_load_option structure into byte stream for BootXXXX.
- * Return a size of allocated data.
+ *
+ * @data: buffer for serialized data
+ * @lo: load option
+ * Return: size of allocated buffer
*/
unsigned long efi_serialize_load_option(struct efi_load_option *lo, u8 **data)
{
@@ -92,7 +105,16 @@
return size;
}
-/* free() the result */
+/**
+ * get_var() - get UEFI variable
+ *
+ * It is the caller's duty to free the returned buffer.
+ *
+ * @name: name of variable
+ * @vendor: vendor GUID of variable
+ * @size: size of allocated buffer
+ * Return: buffer with variable data or NULL
+ */
static void *get_var(u16 *name, const efi_guid_t *vendor,
efi_uintn_t *size)
{
@@ -116,10 +138,16 @@
return buf;
}
-/*
+/**
+ * try_load_entry() - try to load image for boot option
+ *
* Attempt to load load-option number 'n', returning device_path and file_path
- * if successful. This checks that the EFI_LOAD_OPTION is active (enabled)
+ * if successful. This checks that the EFI_LOAD_OPTION is active (enabled)
* and that the specified file to boot exists.
+ *
+ * @n: number of the boot option, e.g. 0x0a13 for Boot0A13
+ * @handle: on return handle for the newly installed image
+ * Return: status code
*/
static efi_status_t try_load_entry(u16 n, efi_handle_t *handle)
{
@@ -180,10 +208,15 @@
return ret;
}
-/*
+/**
+ * efi_bootmgr_load() - try to load from BootNext or BootOrder
+ *
* Attempt to load from BootNext or in the order specified by BootOrder
* EFI variable, the available load-options, finding and returning
* the first one that can be loaded successfully.
+ *
+ * @handle: on return handle for the newly installed image
+ * Return: status code
*/
efi_status_t efi_bootmgr_load(efi_handle_t *handle)
{
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index d104cc6..493d906 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -1,14 +1,13 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * EFI application boot time services
+ * EFI application boot time services
*
- * Copyright (c) 2016 Alexander Graf
+ * Copyright (c) 2016 Alexander Graf
*/
#include <common.h>
#include <div64.h>
#include <efi_loader.h>
-#include <environment.h>
#include <malloc.h>
#include <linux/libfdt_env.h>
#include <u-boot/crc.h>
@@ -25,7 +24,7 @@
LIST_HEAD(efi_obj_list);
/* List of all events */
-LIST_HEAD(efi_events);
+__efi_runtime_data LIST_HEAD(efi_events);
/* List of queued events */
LIST_HEAD(efi_event_queue);
@@ -39,14 +38,6 @@
/* Handle of the currently executing image */
static efi_handle_t current_image;
-/*
- * If we're running on nasty systems (32bit ARM booting into non-EFI Linux)
- * we need to do trickery with caches. Since we don't want to break the EFI
- * aware boot path, only apply hacks when loading exiting directly (breaking
- * direct Linux EFI booting along the way - oh well).
- */
-static bool efi_is_direct_boot = true;
-
#ifdef CONFIG_ARM
/*
* The "gd" pointer lives in a register on ARM and AArch64 that we declare
@@ -596,7 +587,7 @@
/**
* efi_delete_handle() - delete handle
*
- * @obj: handle to delete
+ * @handle: handle to delete
*/
void efi_delete_handle(efi_handle_t handle)
{
@@ -628,6 +619,7 @@
/**
* efi_create_event() - create an event
+ *
* @type: type of the event to create
* @notify_tpl: task priority level of the event
* @notify_function: notification function of the event
@@ -650,6 +642,8 @@
struct efi_event **event)
{
struct efi_event *evt;
+ efi_status_t ret;
+ int pool_type;
if (event == NULL)
return EFI_INVALID_PARAMETER;
@@ -662,7 +656,10 @@
case EVT_NOTIFY_WAIT:
case EVT_TIMER | EVT_NOTIFY_WAIT:
case EVT_SIGNAL_EXIT_BOOT_SERVICES:
+ pool_type = EFI_BOOT_SERVICES_DATA;
+ break;
case EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE:
+ pool_type = EFI_RUNTIME_SERVICES_DATA;
break;
default:
return EFI_INVALID_PARAMETER;
@@ -672,9 +669,11 @@
(!notify_function || is_valid_tpl(notify_tpl) != EFI_SUCCESS))
return EFI_INVALID_PARAMETER;
- evt = calloc(1, sizeof(struct efi_event));
- if (!evt)
- return EFI_OUT_OF_RESOURCES;
+ ret = efi_allocate_pool(pool_type, sizeof(struct efi_event),
+ (void **)&evt);
+ if (ret != EFI_SUCCESS)
+ return ret;
+ memset(evt, 0, sizeof(struct efi_event));
evt->type = type;
evt->notify_tpl = notify_tpl;
evt->notify_function = notify_function;
@@ -982,7 +981,7 @@
list_del(&event->queue_link);
list_del(&event->link);
- free(event);
+ efi_free_pool(event);
return EFI_EXIT(EFI_SUCCESS);
}
@@ -1411,9 +1410,9 @@
/**
* efi_search() - determine if an EFI handle implements a protocol
+ *
* @search_type: selection criterion
* @protocol: GUID of the protocol
- * @search_key: registration key
* @handle: handle
*
* See the documentation of the LocateHandle service in the UEFI specification.
@@ -1675,7 +1674,7 @@
* Initialize a loaded_image_info and loaded_image_info object with correct
* protocols, boot-device, etc.
*
- * In case of an error *handle_ptr and *info_ptr are set to NULL and an error
+ * In case of an error \*handle_ptr and \*info_ptr are set to NULL and an error
* code is returned.
*
* @device_path: device path of the loaded image
@@ -1903,13 +1902,21 @@
*/
static void efi_exit_caches(void)
{
-#if defined(CONFIG_ARM) && !defined(CONFIG_ARM64)
+#if defined(CONFIG_EFI_GRUB_ARM32_WORKAROUND)
/*
- * Grub on 32bit ARM needs to have caches disabled before jumping into
- * a zImage, but does not know of all cache layers. Give it a hand.
+ * Boooting Linux via GRUB prior to version 2.04 fails on 32bit ARM if
+ * caches are enabled.
+ *
+ * TODO:
+ * According to the UEFI spec caches that can be managed via CP15
+ * operations should be enabled. Caches requiring platform information
+ * to manage should be disabled. This should not happen in
+ * ExitBootServices() but before invoking any UEFI binary is invoked.
+ *
+ * We want to keep the current workaround while GRUB prior to version
+ * 2.04 is still in use.
*/
- if (efi_is_direct_boot)
- cleanup_before_linux();
+ cleanup_before_linux();
#endif
}
@@ -1932,7 +1939,7 @@
static efi_status_t EFIAPI efi_exit_boot_services(efi_handle_t image_handle,
efi_uintn_t map_key)
{
- struct efi_event *evt;
+ struct efi_event *evt, *next_event;
efi_status_t ret = EFI_SUCCESS;
EFI_ENTRY("%p, %zx", image_handle, map_key);
@@ -1968,10 +1975,20 @@
/* Make sure that notification functions are not called anymore */
efi_tpl = TPL_HIGH_LEVEL;
- /* TODO: Should persist EFI variables here */
+ /* Notify variable services */
+ efi_variables_boot_exit_notify();
+
+ /* Remove all events except EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE */
+ list_for_each_entry_safe(evt, next_event, &efi_events, link) {
+ if (evt->type != EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE)
+ list_del(&evt->link);
+ }
board_quiesce_devices();
+ /* Patch out unsupported runtime function */
+ efi_runtime_detach();
+
/* Fix up caches for EFI payloads if necessary */
efi_exit_caches();
@@ -2875,8 +2892,6 @@
if (ret != EFI_SUCCESS)
return EFI_EXIT(EFI_INVALID_PARAMETER);
- efi_is_direct_boot = false;
-
image_obj->exit_data_size = exit_data_size;
image_obj->exit_data = exit_data;
@@ -3030,9 +3045,9 @@
/**
* efi_update_exit_data() - fill exit data parameters of StartImage()
*
- * @image_obj image handle
- * @exit_data_size size of the exit data buffer
- * @exit_data buffer with data returned by UEFI payload
+ * @image_obj: image handle
+ * @exit_data_size: size of the exit data buffer
+ * @exit_data: buffer with data returned by UEFI payload
* Return: status code
*/
static efi_status_t efi_update_exit_data(struct efi_loaded_image_obj *image_obj,
@@ -3234,7 +3249,7 @@
if (r != EFI_SUCCESS)
return r;
- /* Context Override */
+ /* Context Override */
if (driver_image_handle) {
for (; *driver_image_handle; ++driver_image_handle) {
for (i = 0; i < count; ++i) {
@@ -3341,7 +3356,7 @@
}
}
}
- /* Check for child controller specified by end node */
+ /* Check for child controller specified by end node */
if (ret != EFI_SUCCESS && remain_device_path &&
remain_device_path->type == DEVICE_PATH_TYPE_END)
ret = EFI_SUCCESS;
@@ -3484,7 +3499,6 @@
efi_handle_t *child_handle_buffer = NULL;
size_t number_of_children = 0;
efi_status_t r;
- size_t stop_count = 0;
struct efi_object *efiobj;
EFI_ENTRY("%p, %p, %p", controller_handle, driver_image_handle,
@@ -3524,32 +3538,35 @@
(void **)&binding_protocol,
driver_image_handle, NULL,
EFI_OPEN_PROTOCOL_GET_PROTOCOL));
- if (r != EFI_SUCCESS)
+ if (r != EFI_SUCCESS) {
+ r = EFI_INVALID_PARAMETER;
goto out;
+ }
/* Remove the children */
if (number_of_children) {
r = EFI_CALL(binding_protocol->stop(binding_protocol,
controller_handle,
number_of_children,
child_handle_buffer));
- if (r == EFI_SUCCESS)
- ++stop_count;
+ if (r != EFI_SUCCESS) {
+ r = EFI_DEVICE_ERROR;
+ goto out;
+ }
}
/* Remove the driver */
- if (!child_handle)
+ if (!child_handle) {
r = EFI_CALL(binding_protocol->stop(binding_protocol,
controller_handle,
0, NULL));
- if (r == EFI_SUCCESS)
- ++stop_count;
+ if (r != EFI_SUCCESS) {
+ r = EFI_DEVICE_ERROR;
+ goto out;
+ }
+ }
EFI_CALL(efi_close_protocol(driver_image_handle,
&efi_guid_driver_binding_protocol,
driver_image_handle, NULL));
-
- if (stop_count)
- r = EFI_SUCCESS;
- else
- r = EFI_NOT_FOUND;
+ r = EFI_SUCCESS;
out:
if (!child_handle)
free(child_handle_buffer);
@@ -3620,11 +3637,7 @@
},
.fw_vendor = firmware_vendor,
.fw_revision = FW_VERSION << 16 | FW_PATCHLEVEL << 8,
- .con_in = &efi_con_in,
- .con_out = &efi_con_out,
- .std_err = &efi_con_out,
.runtime = &efi_runtime_services,
- .boottime = &efi_boot_services,
.nr_tables = 0,
.tables = NULL,
};
@@ -3644,6 +3657,15 @@
sizeof(struct efi_configuration_table),
(void **)&systab.tables);
+ /*
+ * These entries will be set to NULL in ExitBootServices(). To avoid
+ * relocation in SetVirtualAddressMap(), set them dynamically.
+ */
+ systab.con_in = &efi_con_in;
+ systab.con_out = &efi_con_out;
+ systab.std_err = &efi_con_out;
+ systab.boottime = &efi_boot_services;
+
/* Set CRC32 field in table headers */
efi_update_table_header_crc32(&systab.hdr);
efi_update_table_header_crc32(&efi_runtime_services.hdr);
diff --git a/lib/efi_loader/efi_console.c b/lib/efi_loader/efi_console.c
index 6c8229d..a55e4b3 100644
--- a/lib/efi_loader/efi_console.c
+++ b/lib/efi_loader/efi_console.c
@@ -9,6 +9,7 @@
#include <charset.h>
#include <dm/device.h>
#include <efi_loader.h>
+#include <env.h>
#include <stdio_dev.h>
#include <video_console.h>
@@ -155,13 +156,14 @@
* Update the cursor position.
*
* The UEFI spec provides advance rules for U+0000, U+0008, U+000A,
- * and U000D. All other characters, including control characters
- * U+0007 (BEL) and U+0009 (TAB), have to increase the column by one.
+ * and U000D. All other control characters are ignored. Any non-control
+ * character increase the column by one.
*/
for (p = string; *p; ++p) {
switch (*p) {
case '\b': /* U+0008, backspace */
- con->cursor_column = max(0, con->cursor_column - 1);
+ if (con->cursor_column)
+ con->cursor_column--;
break;
case '\n': /* U+000A, newline */
con->cursor_column = 0;
@@ -177,14 +179,21 @@
*/
break;
default:
- con->cursor_column++;
+ /* Exclude control codes */
+ if (*p > 0x1f)
+ con->cursor_column++;
break;
}
if (con->cursor_column >= mode->columns) {
con->cursor_column = 0;
con->cursor_row++;
}
- con->cursor_row = min(con->cursor_row, (s32)mode->rows - 1);
+ /*
+ * When we exceed the row count the terminal will scroll up one
+ * line. We have to adjust the cursor position.
+ */
+ if (con->cursor_row >= mode->rows && con->cursor_row)
+ con->cursor_row--;
}
out:
@@ -210,9 +219,9 @@
/**
* query_console_serial() - query console size
*
- * @rows pointer to return number of rows
- * @columns pointer to return number of columns
- * Returns 0 on success
+ * @rows: pointer to return number of rows
+ * @cols: pointer to return number of columns
+ * Returns: 0 on success
*/
static int query_console_serial(int *rows, int *cols)
{
@@ -370,6 +379,10 @@
if (mode_number >= efi_con_mode.max_mode)
return EFI_EXIT(EFI_UNSUPPORTED);
+
+ if (!efi_cout_modes[mode_number].present)
+ return EFI_EXIT(EFI_UNSUPPORTED);
+
efi_con_mode.mode = mode_number;
EFI_CALL(efi_cout_clear_screen(this));
@@ -451,7 +464,7 @@
* struct efi_cin_notify_function - registered console input notify function
*
* @link: link to list
- * @data: key to notify
+ * @key: key to notify
* @function: function to call
*/
struct efi_cin_notify_function {
@@ -469,6 +482,7 @@
* set_shift_mask() - set shift mask
*
* @mod: Xterm shift mask
+ * @key_state: receives the state of the shift, alt, control, and logo keys
*/
void set_shift_mask(int mod, struct efi_key_state *key_state)
{
@@ -491,7 +505,7 @@
*
* This gets called when we have already parsed CSI.
*
- * @modifiers: bit mask (shift, alt, ctrl)
+ * @key_state: receives the state of the shift, alt, control, and logo keys
* @return: the unmodified code
*/
static int analyze_modifiers(struct efi_key_state *key_state)
diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c
index 10f890f..86297bb 100644
--- a/lib/efi_loader/efi_device_path.c
+++ b/lib/efi_loader/efi_device_path.c
@@ -12,6 +12,12 @@
#include <mmc.h>
#include <efi_loader.h>
#include <part.h>
+#include <sandboxblockdev.h>
+#include <asm-generic/unaligned.h>
+
+#ifdef CONFIG_SANDBOX
+const efi_guid_t efi_guid_host_dev = U_BOOT_HOST_DEV_GUID;
+#endif
/* template END node: */
static const struct efi_device_path END = {
@@ -445,6 +451,16 @@
return dp_size(dev->parent) +
sizeof(struct efi_device_path_sd_mmc_path);
#endif
+#ifdef CONFIG_SANDBOX
+ case UCLASS_ROOT:
+ /*
+ * Sandbox's host device will be represented
+ * as vendor device with extra one byte for
+ * device number
+ */
+ return dp_size(dev->parent)
+ + sizeof(struct efi_device_path_vendor) + 1;
+#endif
default:
return dp_size(dev->parent);
}
@@ -504,6 +520,24 @@
#ifdef CONFIG_BLK
case UCLASS_BLK:
switch (dev->parent->uclass->uc_drv->id) {
+#ifdef CONFIG_SANDBOX
+ case UCLASS_ROOT: {
+ /* stop traversing parents at this point: */
+ struct efi_device_path_vendor *dp = buf;
+ struct blk_desc *desc = dev_get_uclass_platdata(dev);
+
+ dp_fill(buf, dev->parent);
+ dp = buf;
+ ++dp;
+ dp->dp.type = DEVICE_PATH_TYPE_HARDWARE_DEVICE;
+ dp->dp.sub_type = DEVICE_PATH_SUB_TYPE_VENDOR;
+ dp->dp.length = sizeof(*dp) + 1;
+ memcpy(&dp->guid, &efi_guid_host_dev,
+ sizeof(efi_guid_t));
+ dp->vendor_data[0] = desc->devnum;
+ return &dp->vendor_data[1];
+ }
+#endif
#ifdef CONFIG_IDE
case UCLASS_IDE: {
struct efi_device_path_atapi *dp =
@@ -664,7 +698,7 @@
cddp->dp.sub_type = DEVICE_PATH_SUB_TYPE_CDROM_PATH;
cddp->dp.length = sizeof(*cddp);
cddp->partition_start = info.start;
- cddp->partition_end = info.size;
+ cddp->partition_size = info.size;
buf = &cddp[1];
} else {
@@ -793,16 +827,36 @@
return buf;
}
-/* convert path to an UEFI style path (i.e. DOS style backslashes and UTF-16) */
-static void path_to_uefi(u16 *uefi, const char *path)
+/**
+ * path_to_uefi() - convert UTF-8 path to an UEFI style path
+ *
+ * Convert UTF-8 path to a UEFI style path (i.e. with backslashes as path
+ * separators and UTF-16).
+ *
+ * @src: source buffer
+ * @uefi: target buffer, possibly unaligned
+ */
+static void path_to_uefi(void *uefi, const char *src)
{
- while (*path) {
- char c = *(path++);
- if (c == '/')
- c = '\\';
- *(uefi++) = c;
+ u16 *pos = uefi;
+
+ /*
+ * efi_set_bootdev() calls this routine indirectly before the UEFI
+ * subsystem is initialized. So we cannot assume unaligned access to be
+ * enabled.
+ */
+ allow_unaligned();
+
+ while (*src) {
+ s32 code = utf8_get(&src);
+
+ if (code < 0)
+ code = '?';
+ else if (code == '/')
+ code = '\\';
+ utf16_put(code, &pos);
}
- *uefi = '\0';
+ *pos = 0;
}
/*
@@ -819,7 +873,8 @@
if (desc)
dpsize = dp_part_size(desc, part);
- fpsize = sizeof(struct efi_device_path) + 2 * (strlen(path) + 1);
+ fpsize = sizeof(struct efi_device_path) +
+ 2 * (utf8_utf16_strlen(path) + 1);
dpsize += fpsize;
start = buf = dp_alloc(dpsize + sizeof(END));
diff --git a/lib/efi_loader/efi_device_path_to_text.c b/lib/efi_loader/efi_device_path_to_text.c
index 96fd089..0f3796b 100644
--- a/lib/efi_loader/efi_device_path_to_text.c
+++ b/lib/efi_loader/efi_device_path_to_text.c
@@ -29,15 +29,15 @@
static u16 *efi_str_to_u16(char *str)
{
efi_uintn_t len;
- u16 *out;
+ u16 *out, *dst;
efi_status_t ret;
- len = strlen(str) + 1;
- ret = efi_allocate_pool(EFI_ALLOCATE_ANY_PAGES, len * sizeof(u16),
- (void **)&out);
+ len = sizeof(u16) * (utf8_utf16_strlen(str) + 1);
+ ret = efi_allocate_pool(EFI_ALLOCATE_ANY_PAGES, len, (void **)&out);
if (ret != EFI_SUCCESS)
return NULL;
- ascii2unicode(out, str);
+ dst = out;
+ utf8_utf16_strcpy(&dst, str);
return out;
}
@@ -60,9 +60,18 @@
break;
}
case DEVICE_PATH_SUB_TYPE_VENDOR: {
+ int i, n;
struct efi_device_path_vendor *vdp =
(struct efi_device_path_vendor *)dp;
- s += sprintf(s, "VenHw(%pUl)", &vdp->guid);
+
+ s += sprintf(s, "VenHw(%pUl", &vdp->guid);
+ n = (int)vdp->dp.length - sizeof(struct efi_device_path_vendor);
+ if (n > 0) {
+ s += sprintf(s, ",");
+ for (i = 0; i < n; ++i)
+ s += sprintf(s, "%02x", vdp->vendor_data[i]);
+ }
+ s += sprintf(s, ")");
break;
}
default:
@@ -115,17 +124,16 @@
break;
}
case DEVICE_PATH_SUB_TYPE_MSG_MAC_ADDR: {
+ int i, n = sizeof(struct efi_mac_addr);
struct efi_device_path_mac_addr *mdp =
(struct efi_device_path_mac_addr *)dp;
- if (mdp->if_type != 0 && mdp->if_type != 1)
- break;
-
- s += sprintf(s, "MAC(%02x%02x%02x%02x%02x%02x,0x%1x)",
- mdp->mac.addr[0], mdp->mac.addr[1],
- mdp->mac.addr[2], mdp->mac.addr[3],
- mdp->mac.addr[4], mdp->mac.addr[5],
- mdp->if_type);
+ if (mdp->if_type <= 1)
+ n = 6;
+ s += sprintf(s, "MAC(");
+ for (i = 0; i < n; ++i)
+ s += sprintf(s, "%02x", mdp->mac.addr[i]);
+ s += sprintf(s, ",%u)", mdp->if_type);
break;
}
@@ -133,7 +141,7 @@
struct efi_device_path_usb_class *ucdp =
(struct efi_device_path_usb_class *)dp;
- s += sprintf(s, "USBClass(%x,%x,%x,%x,%x)",
+ s += sprintf(s, "UsbClass(0x%x,0x%x,0x%x,0x%x,0x%x)",
ucdp->vendor_id, ucdp->product_id,
ucdp->device_class, ucdp->device_subclass,
ucdp->device_protocol);
@@ -206,7 +214,8 @@
case DEVICE_PATH_SUB_TYPE_CDROM_PATH: {
struct efi_device_path_cdrom_path *cddp =
(struct efi_device_path_cdrom_path *)dp;
- s += sprintf(s, "CDROM(0x%x)", cddp->boot_entry);
+ s += sprintf(s, "CDROM(%u,0x%llx,0x%llx)", cddp->boot_entry,
+ cddp->partition_start, cddp->partition_size);
break;
}
case DEVICE_PATH_SUB_TYPE_FILE_PATH: {
diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
index 7a6b068..9007a5f 100644
--- a/lib/efi_loader/efi_disk.c
+++ b/lib/efi_loader/efi_disk.c
@@ -41,11 +41,26 @@
struct blk_desc *desc;
};
+/**
+ * efi_disk_reset() - reset block device
+ *
+ * This function implements the Reset service of the EFI_BLOCK_IO_PROTOCOL.
+ *
+ * As U-Boot's block devices do not have a reset function simply return
+ * EFI_SUCCESS.
+ *
+ * See the Unified Extensible Firmware Interface (UEFI) specification for
+ * details.
+ *
+ * @this: pointer to the BLOCK_IO_PROTOCOL
+ * @extended_verification: extended verification
+ * Return: status code
+ */
static efi_status_t EFIAPI efi_disk_reset(struct efi_block_io *this,
char extended_verification)
{
EFI_ENTRY("%p, %x", this, extended_verification);
- return EFI_EXIT(EFI_DEVICE_ERROR);
+ return EFI_EXIT(EFI_SUCCESS);
}
enum efi_disk_direction {
@@ -69,12 +84,12 @@
blocks = buffer_size / blksz;
lba += diskobj->offset;
- debug("EFI: %s:%d blocks=%x lba=%llx blksz=%x dir=%d\n", __func__,
- __LINE__, blocks, lba, blksz, direction);
+ EFI_PRINT("blocks=%x lba=%llx blksz=%x dir=%d\n",
+ blocks, lba, blksz, direction);
/* We only support full block access */
if (buffer_size & (blksz - 1))
- return EFI_DEVICE_ERROR;
+ return EFI_BAD_BUFFER_SIZE;
if (direction == EFI_DISK_READ)
n = blk_dread(desc, lba, blocks, buffer);
@@ -84,7 +99,7 @@
/* We don't do interrupts, so check for timers cooperatively */
efi_timer_check();
- debug("EFI: %s:%d n=%lx blocks=%x\n", __func__, __LINE__, n, blocks);
+ EFI_PRINT("n=%lx blocks=%x\n", n, blocks);
if (n != blocks)
return EFI_DEVICE_ERROR;
@@ -99,6 +114,20 @@
void *real_buffer = buffer;
efi_status_t r;
+ if (!this)
+ return EFI_INVALID_PARAMETER;
+ /* TODO: check for media changes */
+ if (media_id != this->media->media_id)
+ return EFI_MEDIA_CHANGED;
+ if (!this->media->media_present)
+ return EFI_NO_MEDIA;
+ /* media->io_align is a power of 2 */
+ if ((uintptr_t)buffer & (this->media->io_align - 1))
+ return EFI_INVALID_PARAMETER;
+ if (lba * this->media->block_size + buffer_size >
+ this->media->last_block * this->media->block_size)
+ return EFI_INVALID_PARAMETER;
+
#ifdef CONFIG_EFI_LOADER_BOUNCE_BUFFER
if (buffer_size > EFI_LOADER_BOUNCE_BUFFER_SIZE) {
r = efi_disk_read_blocks(this, media_id, lba,
@@ -134,6 +163,22 @@
void *real_buffer = buffer;
efi_status_t r;
+ if (!this)
+ return EFI_INVALID_PARAMETER;
+ if (this->media->read_only)
+ return EFI_WRITE_PROTECTED;
+ /* TODO: check for media changes */
+ if (media_id != this->media->media_id)
+ return EFI_MEDIA_CHANGED;
+ if (!this->media->media_present)
+ return EFI_NO_MEDIA;
+ /* media->io_align is a power of 2 */
+ if ((uintptr_t)buffer & (this->media->io_align - 1))
+ return EFI_INVALID_PARAMETER;
+ if (lba * this->media->block_size + buffer_size >
+ this->media->last_block * this->media->block_size)
+ return EFI_INVALID_PARAMETER;
+
#ifdef CONFIG_EFI_LOADER_BOUNCE_BUFFER
if (buffer_size > EFI_LOADER_BOUNCE_BUFFER_SIZE) {
r = efi_disk_write_blocks(this, media_id, lba,
@@ -288,6 +333,11 @@
/* Fill in EFI IO Media info (for read/write callbacks) */
diskobj->media.removable_media = desc->removable;
diskobj->media.media_present = 1;
+ /*
+ * MediaID is just an arbitrary counter.
+ * We have to change it if the medium is removed or changed.
+ */
+ diskobj->media.media_id = 1;
diskobj->media.block_size = desc->blksz;
diskobj->media.io_align = desc->blksz;
diskobj->media.last_block = desc->lba - offset;
diff --git a/lib/efi_loader/efi_file.c b/lib/efi_loader/efi_file.c
index 36ca719..6d3f680 100644
--- a/lib/efi_loader/efi_file.c
+++ b/lib/efi_loader/efi_file.c
@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * EFI utils
+ * EFI_FILE_PROTOCOL
*
- * Copyright (c) 2017 Rob Clark
+ * Copyright (c) 2017 Rob Clark
*/
#include <common.h>
@@ -15,6 +15,9 @@
/* GUID for file system information */
const efi_guid_t efi_file_system_info_guid = EFI_FILE_SYSTEM_INFO_GUID;
+/* GUID to obtain the volume label */
+const efi_guid_t efi_system_volume_label_id = EFI_FILE_SYSTEM_VOLUME_LABEL_ID;
+
struct file_system {
struct efi_simple_file_system_protocol base;
struct efi_device_path *dp;
@@ -28,6 +31,7 @@
struct file_system *fs;
loff_t offset; /* current file position/cursor */
int isdir;
+ u64 open_mode;
/* for reading a directory: */
struct fs_dir_stream *dirs;
@@ -161,13 +165,13 @@
* @file_name: path of the file to be opened. '\', '.', or '..' may
* be used as modifiers. A leading backslash indicates an
* absolute path.
- * @mode: bit mask indicating the access mode (read, write,
+ * @open_mode: bit mask indicating the access mode (read, write,
* create)
* @attributes: attributes for newly created file
* Returns: handle to the opened file or NULL
*/
static struct efi_file_handle *file_open(struct file_system *fs,
- struct file_handle *parent, u16 *file_name, u64 mode,
+ struct file_handle *parent, u16 *file_name, u64 open_mode,
u64 attributes)
{
struct file_handle *fh;
@@ -190,6 +194,7 @@
/* +2 is for null and '/' */
fh = calloc(1, sizeof(*fh) + plen + (flen * MAX_UTF8_PER_UTF16) + 2);
+ fh->open_mode = open_mode;
fh->base = efi_file_handle_protocol;
fh->fs = fs;
@@ -218,9 +223,11 @@
goto error;
if (!exists) {
- if (!(mode & EFI_FILE_MODE_CREATE) ||
+ if (!(open_mode & EFI_FILE_MODE_CREATE) ||
efi_create_file(fh, attributes))
goto error;
+ if (set_blk_dev(fh))
+ goto error;
}
/* figure out if file is a directory: */
@@ -314,11 +321,42 @@
return EFI_EXIT(ret);
}
+/**
+ * efi_get_file_size() - determine the size of a file
+ *
+ * @fh: file handle
+ * @file_size: pointer to receive file size
+ * Return: status code
+ */
+static efi_status_t efi_get_file_size(struct file_handle *fh,
+ loff_t *file_size)
+{
+ if (set_blk_dev(fh))
+ return EFI_DEVICE_ERROR;
+
+ if (fs_size(fh->path, file_size))
+ return EFI_DEVICE_ERROR;
+
+ return EFI_SUCCESS;
+}
+
static efi_status_t file_read(struct file_handle *fh, u64 *buffer_size,
void *buffer)
{
loff_t actread;
+ efi_status_t ret;
+ loff_t file_size;
+ ret = efi_get_file_size(fh, &file_size);
+ if (ret != EFI_SUCCESS)
+ return ret;
+ if (file_size < fh->offset) {
+ ret = EFI_DEVICE_ERROR;
+ return ret;
+ }
+
+ if (set_blk_dev(fh))
+ return EFI_DEVICE_ERROR;
if (fs_read(fh->path, map_to_sysmem(buffer), fh->offset,
*buffer_size, &actread))
return EFI_DEVICE_ERROR;
@@ -334,13 +372,18 @@
{
struct efi_file_info *info = buffer;
struct fs_dirent *dent;
- unsigned int required_size;
+ u64 required_size;
+ u16 *dst;
+
+ if (set_blk_dev(fh))
+ return EFI_DEVICE_ERROR;
if (!fh->dirs) {
assert(fh->offset == 0);
fh->dirs = fs_opendir(fh->path);
if (!fh->dirs)
return EFI_DEVICE_ERROR;
+ fh->dent = NULL;
}
/*
@@ -351,38 +394,25 @@
*/
if (fh->dent) {
dent = fh->dent;
- fh->dent = NULL;
} else {
dent = fs_readdir(fh->dirs);
}
-
if (!dent) {
- /* no more files in directory: */
- /* workaround shim.efi bug/quirk.. as find_boot_csv()
- * loops through directory contents, it initially calls
- * read w/ zero length buffer to find out how much mem
- * to allocate for the EFI_FILE_INFO, then allocates,
- * and then calls a 2nd time. If we return size of
- * zero the first time, it happily passes that to
- * AllocateZeroPool(), and when that returns NULL it
- * thinks it is EFI_OUT_OF_RESOURCES. So on first
- * call return a non-zero size:
- */
- if (*buffer_size == 0)
- *buffer_size = sizeof(*info);
- else
- *buffer_size = 0;
+ /* no more files in directory */
+ *buffer_size = 0;
return EFI_SUCCESS;
}
/* check buffer size: */
- required_size = sizeof(*info) + 2 * (strlen(dent->name) + 1);
+ required_size = sizeof(*info) +
+ 2 * (utf8_utf16_strlen(dent->name) + 1);
if (*buffer_size < required_size) {
*buffer_size = required_size;
fh->dent = dent;
return EFI_BUFFER_TOO_SMALL;
}
+ fh->dent = NULL;
*buffer_size = required_size;
memset(info, 0, required_size);
@@ -394,7 +424,8 @@
if (dent->type == FS_DT_DIR)
info->attribute |= EFI_FILE_DIRECTORY;
- ascii2unicode(info->file_name, dent->name);
+ dst = info->file_name;
+ utf8_utf16_strcpy(&dst, dent->name);
fh->offset++;
@@ -415,11 +446,6 @@
goto error;
}
- if (set_blk_dev(fh)) {
- ret = EFI_DEVICE_ERROR;
- goto error;
- }
-
bs = *buffer_size;
if (fh->isdir)
ret = dir_read(fh, &bs, buffer);
@@ -434,6 +460,19 @@
return EFI_EXIT(ret);
}
+/**
+ * efi_file_write() - write to file
+ *
+ * This function implements the Write() service of the EFI_FILE_PROTOCOL.
+ *
+ * See the Unified Extensible Firmware Interface (UEFI) specification for
+ * details.
+ *
+ * @file: file handle
+ * @buffer_size: number of bytes to write
+ * @buffer: buffer with the bytes to write
+ * Return: status code
+ */
static efi_status_t EFIAPI efi_file_write(struct efi_file_handle *file,
efi_uintn_t *buffer_size,
void *buffer)
@@ -444,21 +483,35 @@
EFI_ENTRY("%p, %p, %p", file, buffer_size, buffer);
- if (set_blk_dev(fh)) {
- ret = EFI_DEVICE_ERROR;
- goto error;
+ if (!file || !buffer_size || !buffer) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+ if (fh->isdir) {
+ ret = EFI_UNSUPPORTED;
+ goto out;
+ }
+ if (!(fh->open_mode & EFI_FILE_MODE_WRITE)) {
+ ret = EFI_ACCESS_DENIED;
+ goto out;
}
+ if (!*buffer_size)
+ goto out;
+
+ if (set_blk_dev(fh)) {
+ ret = EFI_DEVICE_ERROR;
+ goto out;
+ }
if (fs_write(fh->path, map_to_sysmem(buffer), fh->offset, *buffer_size,
&actwrite)) {
ret = EFI_DEVICE_ERROR;
- goto error;
+ goto out;
}
-
*buffer_size = actwrite;
fh->offset += actwrite;
-error:
+out:
return EFI_EXIT(ret);
}
@@ -520,16 +573,9 @@
if (pos == ~0ULL) {
loff_t file_size;
- if (set_blk_dev(fh)) {
- ret = EFI_DEVICE_ERROR;
+ ret = efi_get_file_size(fh, &file_size);
+ if (ret != EFI_SUCCESS)
goto error;
- }
-
- if (fs_size(fh->path, &file_size)) {
- ret = EFI_DEVICE_ERROR;
- goto error;
- }
-
pos = file_size;
}
@@ -546,9 +592,16 @@
{
struct file_handle *fh = to_fh(file);
efi_status_t ret = EFI_SUCCESS;
+ u16 *dst;
EFI_ENTRY("%p, %pUl, %p, %p", file, info_type, buffer_size, buffer);
+ if (!file || !info_type || !buffer_size ||
+ (*buffer_size && !buffer)) {
+ ret = EFI_INVALID_PARAMETER;
+ goto error;
+ }
+
if (!guidcmp(info_type, &efi_file_info_guid)) {
struct efi_file_info *info = buffer;
char *filename = basename(fh);
@@ -556,22 +609,17 @@
loff_t file_size;
/* check buffer size: */
- required_size = sizeof(*info) + 2 * (strlen(filename) + 1);
+ required_size = sizeof(*info) +
+ 2 * (utf8_utf16_strlen(filename) + 1);
if (*buffer_size < required_size) {
*buffer_size = required_size;
ret = EFI_BUFFER_TOO_SMALL;
goto error;
}
- if (set_blk_dev(fh)) {
- ret = EFI_DEVICE_ERROR;
+ ret = efi_get_file_size(fh, &file_size);
+ if (ret != EFI_SUCCESS)
goto error;
- }
-
- if (fs_size(fh->path, &file_size)) {
- ret = EFI_DEVICE_ERROR;
- goto error;
- }
memset(info, 0, required_size);
@@ -582,7 +630,8 @@
if (fh->isdir)
info->attribute |= EFI_FILE_DIRECTORY;
- ascii2unicode(info->file_name, filename);
+ dst = info->file_name;
+ utf8_utf16_strcpy(&dst, filename);
} else if (!guidcmp(info_type, &efi_file_system_info_guid)) {
struct efi_file_system_info *info = buffer;
disk_partition_t part;
@@ -597,8 +646,7 @@
ret = EFI_DEVICE_ERROR;
goto error;
}
- required_size = sizeof(info) + 2 *
- (strlen((const char *)part.name) + 1);
+ required_size = sizeof(*info) + 2;
if (*buffer_size < required_size) {
*buffer_size = required_size;
ret = EFI_BUFFER_TOO_SMALL;
@@ -614,10 +662,15 @@
info->block_size = part.blksz;
/*
* TODO: The volume label is not available in U-Boot.
- * Use the partition name as substitute.
*/
- ascii2unicode((u16 *)info->volume_label,
- (const char *)part.name);
+ info->volume_label[0] = 0;
+ } else if (!guidcmp(info_type, &efi_system_volume_label_id)) {
+ if (*buffer_size < 2) {
+ *buffer_size = 2;
+ ret = EFI_BUFFER_TOO_SMALL;
+ goto error;
+ }
+ *(u16 *)buffer = 0;
} else {
ret = EFI_UNSUPPORTED;
}
@@ -642,7 +695,9 @@
char *new_file_name, *pos;
loff_t file_size;
- if (buffer_size < sizeof(struct efi_file_info)) {
+ /* The buffer will always contain a file name. */
+ if (buffer_size < sizeof(struct efi_file_info) + 2 ||
+ buffer_size < info->size) {
ret = EFI_BAD_BUFFER_SIZE;
goto out;
}
@@ -668,14 +723,9 @@
}
free(new_file_name);
/* Check for truncation */
- if (set_blk_dev(fh)) {
- ret = EFI_DEVICE_ERROR;
+ ret = efi_get_file_size(fh, &file_size);
+ if (ret != EFI_SUCCESS)
goto out;
- }
- if (fs_size(fh->path, &file_size)) {
- ret = EFI_DEVICE_ERROR;
- goto out;
- }
if (file_size != info->file_size) {
/* TODO: we do not support truncation */
EFI_PRINT("Truncation not supported\n");
@@ -687,12 +737,8 @@
* TODO: Support read only
*/
ret = EFI_SUCCESS;
- } else if (!guidcmp(info_type, &efi_file_system_info_guid)) {
- if (buffer_size < sizeof(struct efi_file_system_info)) {
- ret = EFI_BAD_BUFFER_SIZE;
- goto out;
- }
} else {
+ /* TODO: We do not support changing the volume label */
ret = EFI_UNSUPPORTED;
}
out:
@@ -705,12 +751,34 @@
return EFI_EXIT(EFI_SUCCESS);
}
+static efi_status_t EFIAPI efi_file_open_ex(struct efi_file_handle *file,
+ struct efi_file_handle **new_handle,
+ u16 *file_name, u64 open_mode, u64 attributes,
+ struct efi_file_io_token *token)
+{
+ return EFI_UNSUPPORTED;
+}
+
+static efi_status_t EFIAPI efi_file_read_ex(struct efi_file_handle *file,
+ struct efi_file_io_token *token)
+{
+ return EFI_UNSUPPORTED;
+}
+
+static efi_status_t EFIAPI efi_file_write_ex(struct efi_file_handle *file,
+ struct efi_file_io_token *token)
+{
+ return EFI_UNSUPPORTED;
+}
+
+static efi_status_t EFIAPI efi_file_flush_ex(struct efi_file_handle *file,
+ struct efi_file_io_token *token)
+{
+ return EFI_UNSUPPORTED;
+}
+
static const struct efi_file_handle efi_file_handle_protocol = {
- /*
- * TODO: We currently only support EFI file protocol revision 0x00010000
- * while UEFI specs 2.4 - 2.7 prescribe revision 0x00020000.
- */
- .rev = EFI_FILE_PROTOCOL_REVISION,
+ .rev = EFI_FILE_PROTOCOL_REVISION2,
.open = efi_file_open,
.close = efi_file_close,
.delete = efi_file_delete,
@@ -721,6 +789,10 @@
.getinfo = efi_file_getinfo,
.setinfo = efi_file_setinfo,
.flush = efi_file_flush,
+ .open_ex = efi_file_open_ex,
+ .read_ex = efi_file_read_ex,
+ .write_ex = efi_file_write_ex,
+ .flush_ex = efi_file_flush_ex,
};
/**
@@ -755,6 +827,7 @@
struct efi_device_path_file_path *fdp =
container_of(fp, struct efi_device_path_file_path, dp);
struct efi_file_handle *f2;
+ u16 *filename;
if (!EFI_DP_TYPE(fp, MEDIA_DEVICE, FILE_PATH)) {
printf("bad file path!\n");
@@ -762,8 +835,12 @@
return NULL;
}
- EFI_CALL(ret = f->open(f, &f2, fdp->str,
+ filename = u16_strdup(fdp->str);
+ if (!filename)
+ return NULL;
+ EFI_CALL(ret = f->open(f, &f2, filename,
EFI_FILE_MODE_READ, 0));
+ free(filename);
if (ret != EFI_SUCCESS)
return NULL;
diff --git a/lib/efi_loader/efi_gop.c b/lib/efi_loader/efi_gop.c
index cad509b..1511e3b 100644
--- a/lib/efi_loader/efi_gop.c
+++ b/lib/efi_loader/efi_gop.c
@@ -319,7 +319,7 @@
* details.
*
* @this: the graphical output protocol
- * @model_number: the mode to be set
+ * @mode_number: the mode to be set
* Return: status code
*/
static efi_status_t EFIAPI gop_set_mode(struct efi_gop *this, u32 mode_number)
diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
index 2737938..83cbc91 100644
--- a/lib/efi_loader/efi_memory.c
+++ b/lib/efi_loader/efi_memory.c
@@ -37,17 +37,21 @@
#endif
/**
- * efi_pool_allocation - memory block allocated from pool
+ * struct efi_pool_allocation - memory block allocated from pool
*
* @num_pages: number of pages allocated
* @checksum: checksum
+ * @data: allocated pool memory
*
- * U-Boot services each EFI AllocatePool request as a separate
- * (multiple) page allocation. We have to track the number of pages
+ * U-Boot services each UEFI AllocatePool() request as a separate
+ * (multiple) page allocation. We have to track the number of pages
* to be able to free the correct amount later.
+ *
+ * The checksum calculated in function checksum() is used in FreePool() to avoid
+ * freeing memory not allocated by AllocatePool() and duplicate freeing.
+ *
* EFI requires 8 byte alignment for pool allocations, so we can
- * prepend each allocation with an 64 bit header tracking the
- * allocation size, and hand out the remainder to the caller.
+ * prepend each allocation with these header fields.
*/
struct efi_pool_allocation {
u64 num_pages;
@@ -223,8 +227,17 @@
return EFI_CARVE_LOOP_AGAIN;
}
-uint64_t efi_add_memory_map(uint64_t start, uint64_t pages, int memory_type,
- bool overlap_only_ram)
+/**
+ * efi_add_memory_map() - add memory area to the memory map
+ *
+ * @start: start address, must be a multiple of EFI_PAGE_SIZE
+ * @pages: number of pages to add
+ * @memory_type: type of memory added
+ * @overlap_only_ram: the memory area must overlap existing
+ * Return: status code
+ */
+efi_status_t efi_add_memory_map(uint64_t start, uint64_t pages, int memory_type,
+ bool overlap_only_ram)
{
struct list_head *lhandle;
struct efi_mem_list *newlist;
@@ -239,7 +252,7 @@
return EFI_INVALID_PARAMETER;
if (!pages)
- return start;
+ return EFI_SUCCESS;
++efi_memory_map_key;
newlist = calloc(1, sizeof(*newlist));
@@ -277,7 +290,7 @@
* The user requested to only have RAM overlaps,
* but we hit a non-RAM region. Error out.
*/
- return 0;
+ return EFI_NO_MAPPING;
case EFI_CARVE_NO_OVERLAP:
/* Just ignore this list entry */
break;
@@ -307,7 +320,7 @@
* The payload wanted to have RAM overlaps, but we overlapped
* with an unallocated region. Error out.
*/
- return 0;
+ return EFI_NO_MAPPING;
}
/* Add our new map */
@@ -326,7 +339,7 @@
}
}
- return start;
+ return EFI_SUCCESS;
}
/**
@@ -455,7 +468,7 @@
}
/* Reserve that map in our memory maps */
- if (efi_add_memory_map(addr, pages, memory_type, true) != addr)
+ if (efi_add_memory_map(addr, pages, memory_type, true) != EFI_SUCCESS)
/* Map would overlap, bail out */
return EFI_OUT_OF_RESOURCES;
@@ -487,7 +500,6 @@
*/
efi_status_t efi_free_pages(uint64_t memory, efi_uintn_t pages)
{
- uint64_t r = 0;
efi_status_t ret;
ret = efi_check_allocated(memory, true);
@@ -501,13 +513,13 @@
return EFI_INVALID_PARAMETER;
}
- r = efi_add_memory_map(memory, pages, EFI_CONVENTIONAL_MEMORY, false);
+ ret = efi_add_memory_map(memory, pages, EFI_CONVENTIONAL_MEMORY, false);
/* Merging of adjacent free regions is missing */
- if (r == memory)
- return EFI_SUCCESS;
+ if (ret != EFI_SUCCESS)
+ return EFI_NOT_FOUND;
- return EFI_NOT_FOUND;
+ return ret;
}
/**
@@ -643,6 +655,54 @@
return EFI_SUCCESS;
}
+/**
+ * efi_add_conventional_memory_map() - add a RAM memory area to the map
+ *
+ * @ram_start: start address of a RAM memory area
+ * @ram_end: end address of a RAM memory area
+ * @ram_top: max address to be used as conventional memory
+ * Return: status code
+ */
+efi_status_t efi_add_conventional_memory_map(u64 ram_start, u64 ram_end,
+ u64 ram_top)
+{
+ u64 pages;
+
+ /* Remove partial pages */
+ ram_end &= ~EFI_PAGE_MASK;
+ ram_start = (ram_start + EFI_PAGE_MASK) & ~EFI_PAGE_MASK;
+
+ if (ram_end <= ram_start) {
+ /* Invalid mapping */
+ return EFI_INVALID_PARAMETER;
+ }
+
+ pages = (ram_end - ram_start) >> EFI_PAGE_SHIFT;
+
+ efi_add_memory_map(ram_start, pages,
+ EFI_CONVENTIONAL_MEMORY, false);
+
+ /*
+ * Boards may indicate to the U-Boot memory core that they
+ * can not support memory above ram_top. Let's honor this
+ * in the efi_loader subsystem too by declaring any memory
+ * above ram_top as "already occupied by firmware".
+ */
+ if (ram_top < ram_start) {
+ /* ram_top is before this region, reserve all */
+ efi_add_memory_map(ram_start, pages,
+ EFI_BOOT_SERVICES_DATA, true);
+ } else if ((ram_top >= ram_start) && (ram_top < ram_end)) {
+ /* ram_top is inside this region, reserve parts */
+ pages = (ram_end - ram_top) >> EFI_PAGE_SHIFT;
+
+ efi_add_memory_map(ram_top, pages,
+ EFI_BOOT_SERVICES_DATA, true);
+ }
+
+ return EFI_SUCCESS;
+}
+
__weak void efi_add_known_memory(void)
{
u64 ram_top = board_get_usable_ram_top(0) & ~EFI_PAGE_MASK;
@@ -660,42 +720,12 @@
/* Add RAM */
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- u64 ram_end, ram_start, pages;
+ u64 ram_end, ram_start;
ram_start = (uintptr_t)map_sysmem(gd->bd->bi_dram[i].start, 0);
ram_end = ram_start + gd->bd->bi_dram[i].size;
- /* Remove partial pages */
- ram_end &= ~EFI_PAGE_MASK;
- ram_start = (ram_start + EFI_PAGE_MASK) & ~EFI_PAGE_MASK;
-
- if (ram_end <= ram_start) {
- /* Invalid mapping, keep going. */
- continue;
- }
-
- pages = (ram_end - ram_start) >> EFI_PAGE_SHIFT;
-
- efi_add_memory_map(ram_start, pages,
- EFI_CONVENTIONAL_MEMORY, false);
-
- /*
- * Boards may indicate to the U-Boot memory core that they
- * can not support memory above ram_top. Let's honor this
- * in the efi_loader subsystem too by declaring any memory
- * above ram_top as "already occupied by firmware".
- */
- if (ram_top < ram_start) {
- /* ram_top is before this region, reserve all */
- efi_add_memory_map(ram_start, pages,
- EFI_BOOT_SERVICES_DATA, true);
- } else if ((ram_top >= ram_start) && (ram_top < ram_end)) {
- /* ram_top is inside this region, reserve parts */
- pages = (ram_end - ram_top) >> EFI_PAGE_SHIFT;
-
- efi_add_memory_map(ram_top, pages,
- EFI_BOOT_SERVICES_DATA, true);
- }
+ efi_add_conventional_memory_map(ram_start, ram_end, ram_top);
}
}
diff --git a/lib/efi_loader/efi_net.c b/lib/efi_loader/efi_net.c
index d71c663..82d2595 100644
--- a/lib/efi_loader/efi_net.c
+++ b/lib/efi_loader/efi_net.c
@@ -1,8 +1,18 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * EFI application network access support
+ * Simple network protocol
+ * PXE base code protocol
*
- * Copyright (c) 2016 Alexander Graf
+ * Copyright (c) 2016 Alexander Graf
+ *
+ * The simple network protocol has the following statuses and services
+ * to move between them:
+ *
+ * Start(): EfiSimpleNetworkStopped -> EfiSimpleNetworkStarted
+ * Initialize(): EfiSimpleNetworkStarted -> EfiSimpleNetworkInitialized
+ * Shutdown(): EfiSimpleNetworkInitialized -> EfiSimpleNetworkStarted
+ * Stop(): EfiSimpleNetworkStarted -> EfiSimpleNetworkStopped
+ * Reset(): EfiSimpleNetworkInitialized -> EfiSimpleNetworkInitialized
*/
#include <common.h>
@@ -10,7 +20,8 @@
#include <malloc.h>
static const efi_guid_t efi_net_guid = EFI_SIMPLE_NETWORK_PROTOCOL_GUID;
-static const efi_guid_t efi_pxe_guid = EFI_PXE_BASE_CODE_PROTOCOL_GUID;
+static const efi_guid_t efi_pxe_base_code_protocol_guid =
+ EFI_PXE_BASE_CODE_PROTOCOL_GUID;
static struct efi_pxe_packet *dhcp_ack;
static bool new_rx_packet;
static void *new_tx_packet;
@@ -39,7 +50,7 @@
struct efi_object header;
struct efi_simple_network net;
struct efi_simple_network_mode net_mode;
- struct efi_pxe pxe;
+ struct efi_pxe_base_code_protocol pxe;
struct efi_pxe_mode pxe_mode;
};
@@ -65,10 +76,13 @@
goto out;
}
- if (this->mode->state != EFI_NETWORK_STOPPED)
+ if (this->mode->state != EFI_NETWORK_STOPPED) {
ret = EFI_ALREADY_STARTED;
- else
+ } else {
+ this->int_status = 0;
+ wait_for_packet->is_signaled = false;
this->mode->state = EFI_NETWORK_STARTED;
+ }
out:
return EFI_EXIT(ret);
}
@@ -95,10 +109,13 @@
goto out;
}
- if (this->mode->state == EFI_NETWORK_STOPPED)
+ if (this->mode->state == EFI_NETWORK_STOPPED) {
ret = EFI_NOT_STARTED;
- else
+ } else {
+ /* Disable hardware and put it into the reset state */
+ eth_halt();
this->mode->state = EFI_NETWORK_STOPPED;
+ }
out:
return EFI_EXIT(ret);
}
@@ -129,6 +146,15 @@
goto out;
}
+ switch (this->mode->state) {
+ case EFI_NETWORK_INITIALIZED:
+ case EFI_NETWORK_STARTED:
+ break;
+ default:
+ r = EFI_NOT_STARTED;
+ goto out;
+ }
+
/* Setup packet buffers */
net_init();
/* Disable hardware and put it into the reset state */
@@ -143,6 +169,8 @@
r = EFI_DEVICE_ERROR;
goto out;
} else {
+ this->int_status = 0;
+ wait_for_packet->is_signaled = false;
this->mode->state = EFI_NETWORK_INITIALIZED;
}
out:
@@ -163,9 +191,31 @@
static efi_status_t EFIAPI efi_net_reset(struct efi_simple_network *this,
int extended_verification)
{
+ efi_status_t ret;
+
EFI_ENTRY("%p, %x", this, extended_verification);
- return EFI_EXIT(EFI_CALL(efi_net_initialize(this, 0, 0)));
+ /* Check parameters */
+ if (!this) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+
+ switch (this->mode->state) {
+ case EFI_NETWORK_INITIALIZED:
+ break;
+ case EFI_NETWORK_STOPPED:
+ ret = EFI_NOT_STARTED;
+ goto out;
+ default:
+ ret = EFI_DEVICE_ERROR;
+ goto out;
+ }
+
+ this->mode->state = EFI_NETWORK_STARTED;
+ ret = EFI_CALL(efi_net_initialize(this, 0, 0));
+out:
+ return EFI_EXIT(ret);
}
/*
@@ -190,8 +240,21 @@
goto out;
}
+ switch (this->mode->state) {
+ case EFI_NETWORK_INITIALIZED:
+ break;
+ case EFI_NETWORK_STOPPED:
+ ret = EFI_NOT_STARTED;
+ goto out;
+ default:
+ ret = EFI_DEVICE_ERROR;
+ goto out;
+ }
+
eth_halt();
- this->mode->state = EFI_NETWORK_STOPPED;
+ this->int_status = 0;
+ wait_for_packet->is_signaled = false;
+ this->mode->state = EFI_NETWORK_STARTED;
out:
return EFI_EXIT(ret);
@@ -269,7 +332,7 @@
/*
* efi_net_mcastiptomac() - translate multicast IP address to MAC address
*
- * This function implements the Statistics service of the
+ * This function implements the MCastIPtoMAC service of the
* EFI_SIMPLE_NETWORK_PROTOCOL. See the Unified Extensible Firmware Interface
* (UEFI) specification for details.
*
@@ -284,9 +347,49 @@
struct efi_ip_address *ip,
struct efi_mac_address *mac)
{
+ efi_status_t ret = EFI_SUCCESS;
+
EFI_ENTRY("%p, %x, %p, %p", this, ipv6, ip, mac);
- return EFI_EXIT(EFI_INVALID_PARAMETER);
+ if (!this || !ip || !mac) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+
+ if (ipv6) {
+ ret = EFI_UNSUPPORTED;
+ goto out;
+ }
+
+ /* Multi-cast addresses are in the range 224.0.0.0 - 239.255.255.255 */
+ if ((ip->ip_addr[0] & 0xf0) != 0xe0) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ };
+
+ switch (this->mode->state) {
+ case EFI_NETWORK_INITIALIZED:
+ case EFI_NETWORK_STARTED:
+ break;
+ default:
+ ret = EFI_NOT_STARTED;
+ goto out;
+ }
+
+ memset(mac, 0, sizeof(struct efi_mac_address));
+
+ /*
+ * Copy lower 23 bits of IPv4 multi-cast address
+ * RFC 1112, RFC 7042 2.1.1.
+ */
+ mac->mac_addr[0] = 0x01;
+ mac->mac_addr[1] = 0x00;
+ mac->mac_addr[2] = 0x5E;
+ mac->mac_addr[3] = ip->ip_addr[1] & 0x7F;
+ mac->mac_addr[4] = ip->ip_addr[2];
+ mac->mac_addr[5] = ip->ip_addr[3];
+out:
+ return EFI_EXIT(ret);
}
/**
@@ -296,7 +399,7 @@
* Protocol. See the UEFI spec for details.
*
* @this: the instance of the Simple Network Protocol
- * @readwrite: true for read, false for write
+ * @read_write: true for read, false for write
* @offset: offset in NVRAM
* @buffer_size: size of buffer
* @buffer: buffer
@@ -349,10 +452,8 @@
}
if (int_status) {
- /* We send packets synchronously, so nothing is outstanding */
- *int_status = EFI_SIMPLE_NETWORK_TRANSMIT_INTERRUPT;
- if (new_rx_packet)
- *int_status |= EFI_SIMPLE_NETWORK_RECEIVE_INTERRUPT;
+ *int_status = this->int_status;
+ this->int_status = 0;
}
if (txbuf)
*txbuf = new_tx_packet;
@@ -403,15 +504,33 @@
goto out;
}
- if (header_size) {
- /*
- * TODO: We would need to create the header
- * if header_size != 0
- */
- ret = EFI_UNSUPPORTED;
+ /* At least the IP header has to fit into the buffer */
+ if (buffer_size < this->mode->media_header_size) {
+ ret = EFI_BUFFER_TOO_SMALL;
goto out;
}
+ /*
+ * TODO:
+ * Support VLANs. Use net_set_ether() for copying the header. Use a
+ * U_BOOT_ENV_CALLBACK to update the media header size.
+ */
+ if (header_size) {
+ struct ethernet_hdr *header = buffer;
+
+ if (!dest_addr || !protocol ||
+ header_size != this->mode->media_header_size) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+ if (!src_addr)
+ src_addr = &this->mode->current_address;
+
+ memcpy(header->et_dest, dest_addr, ARP_HLEN);
+ memcpy(header->et_src, src_addr, ARP_HLEN);
+ header->et_protlen = htons(*protocol);
+ }
+
switch (this->mode->state) {
case EFI_NETWORK_STOPPED:
ret = EFI_NOT_STARTED;
@@ -428,7 +547,7 @@
net_send_packet(transmit_buffer, buffer_size);
new_tx_packet = buffer;
-
+ this->int_status |= EFI_SIMPLE_NETWORK_TRANSMIT_INTERRUPT;
out:
return EFI_EXIT(ret);
}
@@ -486,12 +605,6 @@
ret = EFI_NOT_READY;
goto out;
}
- /* Check that we at least received an Ethernet header */
- if (net_rx_packet_len < sizeof(struct ethernet_hdr)) {
- new_rx_packet = false;
- ret = EFI_NOT_READY;
- goto out;
- }
/* Fill export parameters */
eth_hdr = (struct ethernet_hdr *)net_rx_packet;
protlen = ntohs(eth_hdr->et_protlen);
@@ -516,7 +629,8 @@
/* Copy packet */
memcpy(buffer, net_rx_packet, net_rx_packet_len);
*buffer_size = net_rx_packet_len;
- new_rx_packet = false;
+ new_rx_packet = 0;
+ this->int_status &= ~EFI_SIMPLE_NETWORK_RECEIVE_INTERRUPT;
out:
return EFI_EXIT(ret);
}
@@ -525,6 +639,9 @@
* efi_net_set_dhcp_ack() - take note of a selected DHCP IP address
*
* This function is called by dhcp_handler().
+ *
+ * @pkt: packet received by dhcp_handler()
+ * @len: length of the packet received
*/
void efi_net_set_dhcp_ack(void *pkt, int len)
{
@@ -547,7 +664,6 @@
static void efi_net_push(void *pkt, int len)
{
new_rx_packet = true;
- wait_for_packet->is_signaled = true;
}
/**
@@ -555,8 +671,8 @@
*
* This notification function is called in every timer cycle.
*
- * @event the event for which this notification function is registered
- * @context event context - not used in this function
+ * @event: the event for which this notification function is registered
+ * @context: event context - not used in this function
*/
static void EFIAPI efi_network_timer_notify(struct efi_event *event,
void *context)
@@ -576,11 +692,134 @@
push_packet = efi_net_push;
eth_rx();
push_packet = NULL;
+ if (new_rx_packet) {
+ /* Check that we at least received an Ethernet header */
+ if (net_rx_packet_len >=
+ sizeof(struct ethernet_hdr)) {
+ this->int_status |=
+ EFI_SIMPLE_NETWORK_RECEIVE_INTERRUPT;
+ wait_for_packet->is_signaled = true;
+ } else {
+ new_rx_packet = 0;
+ }
+ }
}
out:
EFI_EXIT(EFI_SUCCESS);
}
+static efi_status_t EFIAPI efi_pxe_base_code_start(
+ struct efi_pxe_base_code_protocol *this,
+ u8 use_ipv6)
+{
+ return EFI_UNSUPPORTED;
+}
+
+static efi_status_t EFIAPI efi_pxe_base_code_stop(
+ struct efi_pxe_base_code_protocol *this)
+{
+ return EFI_UNSUPPORTED;
+}
+
+static efi_status_t EFIAPI efi_pxe_base_code_dhcp(
+ struct efi_pxe_base_code_protocol *this,
+ u8 sort_offers)
+{
+ return EFI_UNSUPPORTED;
+}
+
+static efi_status_t EFIAPI efi_pxe_base_code_discover(
+ struct efi_pxe_base_code_protocol *this,
+ u16 type, u16 *layer, u8 bis,
+ struct efi_pxe_base_code_discover_info *info)
+{
+ return EFI_UNSUPPORTED;
+}
+
+static efi_status_t EFIAPI efi_pxe_base_code_mtftp(
+ struct efi_pxe_base_code_protocol *this,
+ u32 operation, void *buffer_ptr,
+ u8 overwrite, efi_uintn_t *buffer_size,
+ struct efi_ip_address server_ip, char *filename,
+ struct efi_pxe_base_code_mtftp_info *info,
+ u8 dont_use_buffer)
+{
+ return EFI_UNSUPPORTED;
+}
+
+static efi_status_t EFIAPI efi_pxe_base_code_udp_write(
+ struct efi_pxe_base_code_protocol *this,
+ u16 op_flags, struct efi_ip_address *dest_ip,
+ u16 *dest_port,
+ struct efi_ip_address *gateway_ip,
+ struct efi_ip_address *src_ip, u16 *src_port,
+ efi_uintn_t *header_size, void *header_ptr,
+ efi_uintn_t *buffer_size, void *buffer_ptr)
+{
+ return EFI_UNSUPPORTED;
+}
+
+static efi_status_t EFIAPI efi_pxe_base_code_udp_read(
+ struct efi_pxe_base_code_protocol *this,
+ u16 op_flags, struct efi_ip_address *dest_ip,
+ u16 *dest_port, struct efi_ip_address *src_ip,
+ u16 *src_port, efi_uintn_t *header_size,
+ void *header_ptr, efi_uintn_t *buffer_size,
+ void *buffer_ptr)
+{
+ return EFI_UNSUPPORTED;
+}
+
+static efi_status_t EFIAPI efi_pxe_base_code_set_ip_filter(
+ struct efi_pxe_base_code_protocol *this,
+ struct efi_pxe_base_code_filter *new_filter)
+{
+ return EFI_UNSUPPORTED;
+}
+
+static efi_status_t EFIAPI efi_pxe_base_code_arp(
+ struct efi_pxe_base_code_protocol *this,
+ struct efi_ip_address *ip_addr,
+ struct efi_mac_address *mac_addr)
+{
+ return EFI_UNSUPPORTED;
+}
+
+static efi_status_t EFIAPI efi_pxe_base_code_set_parameters(
+ struct efi_pxe_base_code_protocol *this,
+ u8 *new_auto_arp, u8 *new_send_guid,
+ u8 *new_ttl, u8 *new_tos,
+ u8 *new_make_callback)
+{
+ return EFI_UNSUPPORTED;
+}
+
+static efi_status_t EFIAPI efi_pxe_base_code_set_station_ip(
+ struct efi_pxe_base_code_protocol *this,
+ struct efi_ip_address *new_station_ip,
+ struct efi_ip_address *new_subnet_mask)
+{
+ return EFI_UNSUPPORTED;
+}
+
+static efi_status_t EFIAPI efi_pxe_base_code_set_packets(
+ struct efi_pxe_base_code_protocol *this,
+ u8 *new_dhcp_discover_valid,
+ u8 *new_dhcp_ack_received,
+ u8 *new_proxy_offer_received,
+ u8 *new_pxe_discover_valid,
+ u8 *new_pxe_reply_received,
+ u8 *new_pxe_bis_reply_received,
+ EFI_PXE_BASE_CODE_PACKET *new_dchp_discover,
+ EFI_PXE_BASE_CODE_PACKET *new_dhcp_acc,
+ EFI_PXE_BASE_CODE_PACKET *new_proxy_offer,
+ EFI_PXE_BASE_CODE_PACKET *new_pxe_discover,
+ EFI_PXE_BASE_CODE_PACKET *new_pxe_reply,
+ EFI_PXE_BASE_CODE_PACKET *new_pxe_bis_reply)
+{
+ return EFI_UNSUPPORTED;
+}
+
/**
* efi_net_register() - register the simple network protocol
*
@@ -619,7 +858,7 @@
efi_dp_from_eth());
if (r != EFI_SUCCESS)
goto failure_to_add_protocol;
- r = efi_add_protocol(&netobj->header, &efi_pxe_guid,
+ r = efi_add_protocol(&netobj->header, &efi_pxe_base_code_protocol_guid,
&netobj->pxe);
if (r != EFI_SUCCESS)
goto failure_to_add_protocol;
@@ -638,12 +877,26 @@
netobj->net.transmit = efi_net_transmit;
netobj->net.receive = efi_net_receive;
netobj->net.mode = &netobj->net_mode;
- netobj->net_mode.state = EFI_NETWORK_STARTED;
+ netobj->net_mode.state = EFI_NETWORK_STOPPED;
memcpy(netobj->net_mode.current_address.mac_addr, eth_get_ethaddr(), 6);
netobj->net_mode.hwaddr_size = ARP_HLEN;
+ netobj->net_mode.media_header_size = ETHER_HDR_SIZE;
netobj->net_mode.max_packet_size = PKTSIZE;
netobj->net_mode.if_type = ARP_ETHER;
+ netobj->pxe.revision = EFI_PXE_BASE_CODE_PROTOCOL_REVISION;
+ netobj->pxe.start = efi_pxe_base_code_start;
+ netobj->pxe.stop = efi_pxe_base_code_stop;
+ netobj->pxe.dhcp = efi_pxe_base_code_dhcp;
+ netobj->pxe.discover = efi_pxe_base_code_discover;
+ netobj->pxe.mtftp = efi_pxe_base_code_mtftp;
+ netobj->pxe.udp_write = efi_pxe_base_code_udp_write;
+ netobj->pxe.udp_read = efi_pxe_base_code_udp_read;
+ netobj->pxe.set_ip_filter = efi_pxe_base_code_set_ip_filter;
+ netobj->pxe.arp = efi_pxe_base_code_arp;
+ netobj->pxe.set_parameters = efi_pxe_base_code_set_parameters;
+ netobj->pxe.set_station_ip = efi_pxe_base_code_set_station_ip;
+ netobj->pxe.set_packets = efi_pxe_base_code_set_packets;
netobj->pxe.mode = &netobj->pxe_mode;
if (dhcp_ack)
netobj->pxe_mode.dhcp_ack = *dhcp_ack;
diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c
index 40fdc0e..ced0051 100644
--- a/lib/efi_loader/efi_runtime.c
+++ b/lib/efi_loader/efi_runtime.c
@@ -26,8 +26,6 @@
LIST_HEAD(efi_runtime_mmio);
static efi_status_t __efi_runtime EFIAPI efi_unimplemented(void);
-static efi_status_t __efi_runtime EFIAPI efi_device_error(void);
-static efi_status_t __efi_runtime EFIAPI efi_invalid_parameter(void);
/*
* TODO(sjg@chromium.org): These defines and structures should come from the ELF
@@ -83,6 +81,10 @@
long addend;
};
+static __efi_runtime_data struct efi_mem_desc *efi_virtmap;
+static __efi_runtime_data efi_uintn_t efi_descriptor_count;
+static __efi_runtime_data efi_uintn_t efi_descriptor_size;
+
/*
* EFI runtime code lives in two stages. In the first stage, U-Boot and an EFI
* payload are running concurrently at the same time. In this mode, we can
@@ -91,20 +93,18 @@
efi_status_t efi_init_runtime_supported(void)
{
- u16 efi_runtime_services_supported = 0;
+ u16 efi_runtime_services_supported =
+ EFI_RT_SUPPORTED_SET_VIRTUAL_ADDRESS_MAP |
+ EFI_RT_SUPPORTED_CONVERT_POINTER;
/*
* This value must be synced with efi_runtime_detach_list
* as well as efi_runtime_services.
*/
-#if CONFIG_IS_ENABLED(ARCH_BCM283X) || \
- CONFIG_IS_ENABLED(FSL_LAYERSCAPE) || \
- CONFIG_IS_ENABLED(SYSRESET_X86) || \
- CONFIG_IS_ENABLED(PSCI_RESET)
+#ifdef CONFIG_EFI_HAVE_RUNTIME_RESET
efi_runtime_services_supported |= EFI_RT_SUPPORTED_RESET_SYSTEM;
#endif
- efi_runtime_services_supported |=
- EFI_RT_SUPPORTED_SET_VIRTUAL_ADDRESS_MAP;
+
return EFI_CALL(efi_set_variable(L"RuntimeServicesSupported",
&efi_global_variable_guid,
EFI_VARIABLE_BOOTSERVICE_ACCESS |
@@ -387,80 +387,162 @@
return EFI_UNSUPPORTED;
}
-struct efi_runtime_detach_list_struct {
- void *ptr;
- void *patchto;
-};
-
-static const struct efi_runtime_detach_list_struct efi_runtime_detach_list[] = {
- {
- /* do_reset is gone */
- .ptr = &efi_runtime_services.reset_system,
- .patchto = efi_reset_system,
- }, {
- /* invalidate_*cache_all are gone */
- .ptr = &efi_runtime_services.set_virtual_address_map,
- .patchto = &efi_unimplemented,
- }, {
- /* RTC accessors are gone */
- .ptr = &efi_runtime_services.get_time,
- .patchto = &efi_get_time,
- }, {
- .ptr = &efi_runtime_services.set_time,
- .patchto = &efi_set_time,
- }, {
- /* Clean up system table */
- .ptr = &systab.con_in,
- .patchto = NULL,
- }, {
- /* Clean up system table */
- .ptr = &systab.con_out,
- .patchto = NULL,
- }, {
- /* Clean up system table */
- .ptr = &systab.std_err,
- .patchto = NULL,
- }, {
- /* Clean up system table */
- .ptr = &systab.boottime,
- .patchto = NULL,
- }, {
- .ptr = &efi_runtime_services.get_variable,
- .patchto = &efi_device_error,
- }, {
- .ptr = &efi_runtime_services.get_next_variable_name,
- .patchto = &efi_device_error,
- }, {
- .ptr = &efi_runtime_services.set_variable,
- .patchto = &efi_device_error,
- }
-};
-
-static bool efi_runtime_tobedetached(void *p)
+/**
+ * efi_is_runtime_service_pointer() - check if pointer points to runtime table
+ *
+ * @p: pointer to check
+ * Return: true if the pointer points to a service function pointer in the
+ * runtime table
+ */
+static bool efi_is_runtime_service_pointer(void *p)
{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(efi_runtime_detach_list); i++)
- if (efi_runtime_detach_list[i].ptr == p)
- return true;
-
- return false;
+ return (p >= (void *)&efi_runtime_services.get_time &&
+ p <= (void *)&efi_runtime_services.query_variable_info) ||
+ p == (void *)&efi_events.prev ||
+ p == (void *)&efi_events.next;
}
-static void efi_runtime_detach(ulong offset)
+/**
+ * efi_runtime_detach() - detach unimplemented runtime functions
+ */
+void efi_runtime_detach(void)
{
- int i;
- ulong patchoff = offset - (ulong)gd->relocaddr;
+ efi_runtime_services.reset_system = efi_reset_system;
+ efi_runtime_services.get_time = efi_get_time;
+ efi_runtime_services.set_time = efi_set_time;
- for (i = 0; i < ARRAY_SIZE(efi_runtime_detach_list); i++) {
- ulong patchto = (ulong)efi_runtime_detach_list[i].patchto;
- ulong *p = efi_runtime_detach_list[i].ptr;
- ulong newaddr = patchto ? (patchto + patchoff) : 0;
+ /* Update CRC32 */
+ efi_update_table_header_crc32(&efi_runtime_services.hdr);
+}
- debug("%s: Setting %p to %lx\n", __func__, p, newaddr);
- *p = newaddr;
+/**
+ * efi_set_virtual_address_map_runtime() - change from physical to virtual
+ * mapping
+ *
+ * This function implements the SetVirtualAddressMap() runtime service after
+ * it is first called.
+ *
+ * See the Unified Extensible Firmware Interface (UEFI) specification for
+ * details.
+ *
+ * @memory_map_size: size of the virtual map
+ * @descriptor_size: size of an entry in the map
+ * @descriptor_version: version of the map entries
+ * @virtmap: virtual address mapping information
+ * Return: status code EFI_UNSUPPORTED
+ */
+static __efi_runtime efi_status_t EFIAPI efi_set_virtual_address_map_runtime(
+ efi_uintn_t memory_map_size,
+ efi_uintn_t descriptor_size,
+ uint32_t descriptor_version,
+ struct efi_mem_desc *virtmap)
+{
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ * efi_convert_pointer_runtime() - convert from physical to virtual pointer
+ *
+ * This function implements the ConvertPointer() runtime service after
+ * the first call to SetVirtualAddressMap().
+ *
+ * See the Unified Extensible Firmware Interface (UEFI) specification for
+ * details.
+ *
+ * @debug_disposition: indicates if pointer may be converted to NULL
+ * @address: pointer to be converted
+ * Return: status code EFI_UNSUPPORTED
+ */
+static __efi_runtime efi_status_t EFIAPI efi_convert_pointer_runtime(
+ efi_uintn_t debug_disposition, void **address)
+{
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ * efi_convert_pointer_runtime() - convert from physical to virtual pointer
+ *
+ * This function implements the ConvertPointer() runtime service until
+ * the first call to SetVirtualAddressMap().
+ *
+ * See the Unified Extensible Firmware Interface (UEFI) specification for
+ * details.
+ *
+ * @debug_disposition: indicates if pointer may be converted to NULL
+ * @address: pointer to be converted
+ * Return: status code EFI_UNSUPPORTED
+ */
+static __efi_runtime efi_status_t EFIAPI efi_convert_pointer(
+ efi_uintn_t debug_disposition, void **address)
+{
+ efi_physical_addr_t addr = (uintptr_t)*address;
+ efi_uintn_t i;
+ efi_status_t ret = EFI_NOT_FOUND;
+
+ EFI_ENTRY("%zu %p", debug_disposition, address);
+
+ if (!efi_virtmap) {
+ ret = EFI_UNSUPPORTED;
+ goto out;
}
+ if (!address) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+
+ for (i = 0; i < efi_descriptor_count; i++) {
+ struct efi_mem_desc *map = (void *)efi_virtmap +
+ (efi_descriptor_size * i);
+
+ if (addr >= map->physical_start &&
+ (addr < map->physical_start
+ + (map->num_pages << EFI_PAGE_SHIFT))) {
+ *address = (void *)(uintptr_t)
+ (addr + map->virtual_start -
+ map->physical_start);
+
+ ret = EFI_SUCCESS;
+ break;
+ }
+ }
+
+out:
+ return EFI_EXIT(ret);
+}
+
+static __efi_runtime void efi_relocate_runtime_table(ulong offset)
+{
+ ulong patchoff;
+ void **pos;
+
+ /* Relocate the runtime services pointers */
+ patchoff = offset - gd->relocaddr;
+ for (pos = (void **)&efi_runtime_services.get_time;
+ pos <= (void **)&efi_runtime_services.query_variable_info; ++pos) {
+ if (*pos)
+ *pos += patchoff;
+ }
+
+ /*
+ * The entry for SetVirtualAddress() must point to a physical address.
+ * After the first execution the service must return EFI_UNSUPPORTED.
+ */
+ efi_runtime_services.set_virtual_address_map =
+ &efi_set_virtual_address_map_runtime;
+
+ /*
+ * The entry for ConvertPointer() must point to a physical address.
+ * The service is not usable after SetVirtualAddress().
+ */
+ efi_runtime_services.convert_pointer = &efi_convert_pointer_runtime;
+
+ /*
+ * TODO: Update UEFI variable RuntimeServicesSupported removing flags
+ * EFI_RT_SUPPORTED_SET_VIRTUAL_ADDRESS_MAP and
+ * EFI_RT_SUPPORTED_CONVERT_POINTER as required by the UEFI spec 2.8.
+ */
+
/* Update CRC32 */
efi_update_table_header_crc32(&efi_runtime_services.hdr);
}
@@ -483,6 +565,13 @@
p = (void*)((ulong)rel->offset - base) + gd->relocaddr;
+ /*
+ * The runtime services table is updated in
+ * efi_relocate_runtime_table()
+ */
+ if (map && efi_is_runtime_service_pointer(p))
+ continue;
+
debug("%s: rel->info=%#lx *p=%#lx rel->offset=%p\n", __func__,
rel->info, *p, rel->offset);
@@ -506,9 +595,8 @@
}
#endif
default:
- if (!efi_runtime_tobedetached(p))
- printf("%s: Unknown relocation type %llx\n",
- __func__, rel->info & R_MASK);
+ printf("%s: Unknown relocation type %llx\n",
+ __func__, rel->info & R_MASK);
continue;
}
@@ -516,9 +604,8 @@
if (map && ((newaddr < map->virtual_start) ||
newaddr > (map->virtual_start +
(map->num_pages << EFI_PAGE_SHIFT)))) {
- if (!efi_runtime_tobedetached(p))
- printf("%s: Relocation at %p is out of "
- "range (%lx)\n", __func__, p, newaddr);
+ printf("%s: Relocation at %p is out of range (%lx)\n",
+ __func__, p, newaddr);
continue;
}
@@ -550,18 +637,28 @@
* Return: status code
*/
static efi_status_t EFIAPI efi_set_virtual_address_map(
- unsigned long memory_map_size,
- unsigned long descriptor_size,
+ efi_uintn_t memory_map_size,
+ efi_uintn_t descriptor_size,
uint32_t descriptor_version,
struct efi_mem_desc *virtmap)
{
- int n = memory_map_size / descriptor_size;
- int i;
+ efi_uintn_t n = memory_map_size / descriptor_size;
+ efi_uintn_t i;
+ efi_status_t ret = EFI_INVALID_PARAMETER;
int rt_code_sections = 0;
+ struct efi_event *event;
- EFI_ENTRY("%lx %lx %x %p", memory_map_size, descriptor_size,
+ EFI_ENTRY("%zx %zx %x %p", memory_map_size, descriptor_size,
descriptor_version, virtmap);
+ if (descriptor_version != EFI_MEMORY_DESCRIPTOR_VERSION ||
+ descriptor_size < sizeof(struct efi_mem_desc))
+ goto out;
+
+ efi_virtmap = virtmap;
+ efi_descriptor_size = descriptor_size;
+ efi_descriptor_count = n;
+
/*
* TODO:
* Further down we are cheating. While really we should implement
@@ -588,7 +685,14 @@
* We expose exactly one single runtime code section, so
* something is definitely going wrong.
*/
- return EFI_EXIT(EFI_INVALID_PARAMETER);
+ goto out;
+ }
+
+ /* Notify EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE */
+ list_for_each_entry(event, &efi_events, link) {
+ if (event->notify_function)
+ EFI_CALL_VOID(event->notify_function(
+ event, event->notify_context));
}
/* Rebind mmio pointers */
@@ -623,7 +727,7 @@
}
}
- /* Move the actual runtime code over */
+ /* Relocate the runtime. See TODO above */
for (i = 0; i < n; i++) {
struct efi_mem_desc *map;
@@ -632,15 +736,15 @@
ulong new_offset = map->virtual_start -
map->physical_start + gd->relocaddr;
+ efi_relocate_runtime_table(new_offset);
efi_runtime_relocate(new_offset, map);
- /* Once we're virtual, we can no longer handle
- complex callbacks */
- efi_runtime_detach(new_offset);
- return EFI_EXIT(EFI_SUCCESS);
+ ret = EFI_SUCCESS;
+ goto out;
}
}
- return EFI_EXIT(EFI_INVALID_PARAMETER);
+out:
+ return EFI_EXIT(ret);
}
/**
@@ -659,10 +763,10 @@
struct efi_runtime_mmio_list *newmmio;
u64 pages = (len + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
uint64_t addr = *(uintptr_t *)mmio_ptr;
- uint64_t retaddr;
+ efi_status_t ret;
- retaddr = efi_add_memory_map(addr, pages, EFI_MMAP_IO, false);
- if (retaddr != addr)
+ ret = efi_add_memory_map(addr, pages, EFI_MMAP_IO, false);
+ if (ret != EFI_SUCCESS)
return EFI_OUT_OF_RESOURCES;
newmmio = calloc(1, sizeof(*newmmio));
@@ -711,34 +815,6 @@
}
/**
- * efi_device_error() - replacement function, returns EFI_DEVICE_ERROR
- *
- * This function is used after SetVirtualAddressMap() is called as replacement
- * for services that are not available anymore due to constraints of the U-Boot
- * implementation.
- *
- * Return: EFI_DEVICE_ERROR
- */
-static efi_status_t __efi_runtime EFIAPI efi_device_error(void)
-{
- return EFI_DEVICE_ERROR;
-}
-
-/**
- * efi_invalid_parameter() - replacement function, returns EFI_INVALID_PARAMETER
- *
- * This function is used after SetVirtualAddressMap() is called as replacement
- * for services that are not available anymore due to constraints of the U-Boot
- * implementation.
- *
- * Return: EFI_INVALID_PARAMETER
- */
-static efi_status_t __efi_runtime EFIAPI efi_invalid_parameter(void)
-{
- return EFI_INVALID_PARAMETER;
-}
-
-/**
* efi_update_capsule() - process information from operating system
*
* This function implements the UpdateCapsule() runtime service.
@@ -782,33 +858,6 @@
return EFI_UNSUPPORTED;
}
-/**
- * efi_query_variable_info() - get information about EFI variables
- *
- * This function implements the QueryVariableInfo() runtime service.
- *
- * See the Unified Extensible Firmware Interface (UEFI) specification for
- * details.
- *
- * @attributes: bitmask to select variables to be
- * queried
- * @maximum_variable_storage_size: maximum size of storage area for the
- * selected variable types
- * @remaining_variable_storage_size: remaining size of storage are for the
- * selected variable types
- * @maximum_variable_size: maximum size of a variable of the
- * selected type
- * Returns: status code
- */
-efi_status_t __efi_runtime EFIAPI efi_query_variable_info(
- u32 attributes,
- u64 *maximum_variable_storage_size,
- u64 *remaining_variable_storage_size,
- u64 *maximum_variable_size)
-{
- return EFI_UNSUPPORTED;
-}
-
struct efi_runtime_services __efi_runtime_data efi_runtime_services = {
.hdr = {
.signature = EFI_RUNTIME_SERVICES_SIGNATURE,
@@ -820,11 +869,11 @@
.get_wakeup_time = (void *)&efi_unimplemented,
.set_wakeup_time = (void *)&efi_unimplemented,
.set_virtual_address_map = &efi_set_virtual_address_map,
- .convert_pointer = (void *)&efi_invalid_parameter,
+ .convert_pointer = efi_convert_pointer,
.get_variable = efi_get_variable,
.get_next_variable_name = efi_get_next_variable_name,
.set_variable = efi_set_variable,
- .get_next_high_mono_count = (void *)&efi_device_error,
+ .get_next_high_mono_count = (void *)&efi_unimplemented,
.reset_system = &efi_reset_system_boottime,
.update_capsule = efi_update_capsule,
.query_capsule_caps = efi_query_capsule_caps,
diff --git a/lib/efi_loader/efi_setup.c b/lib/efi_loader/efi_setup.c
index bfb5783..de7b616 100644
--- a/lib/efi_loader/efi_setup.c
+++ b/lib/efi_loader/efi_setup.c
@@ -102,6 +102,11 @@
/* On ARM switch from EL3 or secure mode to EL2 or non-secure mode */
switch_to_non_secure_mode();
+ /* Initialize variable services */
+ ret = efi_init_variables();
+ if (ret != EFI_SUCCESS)
+ goto out;
+
/* Define supported languages */
ret = efi_init_platform_lang();
if (ret != EFI_SUCCESS)
diff --git a/lib/efi_loader/efi_unicode_collation.c b/lib/efi_loader/efi_unicode_collation.c
index 243c51a..c700be8 100644
--- a/lib/efi_loader/efi_unicode_collation.c
+++ b/lib/efi_loader/efi_unicode_collation.c
@@ -43,11 +43,6 @@
* See the Unified Extensible Firmware Interface (UEFI) specification for
* details.
*
- * TODO:
- * The implementation does not follow the Unicode collation algorithm.
- * For ASCII characters it results in the same sort order as EDK2.
- * We could use table UNICODE_CAPITALIZATION_TABLE for better results.
- *
* Return: 0: s1 == s2, > 0: s1 > s2, < 0: s1 < s2
*/
static efi_intn_t EFIAPI efi_stri_coll(
diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c
index d6b75ca..4c554c5 100644
--- a/lib/efi_loader/efi_variable.c
+++ b/lib/efi_loader/efi_variable.c
@@ -5,11 +5,12 @@
* Copyright (c) 2017 Rob Clark
*/
+#include <env.h>
#include <malloc.h>
#include <charset.h>
#include <efi_loader.h>
#include <hexdump.h>
-#include <environment.h>
+#include <env_internal.h>
#include <search.h>
#include <uuid.h>
@@ -263,8 +264,8 @@
* is the size of variable name including NULL.
*
* Return: EFI_SUCCESS if parsing is OK, EFI_NOT_FOUND when
- the entire variable list has been returned,
- otherwise non-zero status code
+ * the entire variable list has been returned,
+ * otherwise non-zero status code
*/
static efi_status_t parse_uboot_variable(char *variable,
efi_uintn_t *variable_name_size,
@@ -315,6 +316,7 @@
/**
* efi_get_next_variable_name() - enumerate the current variable names
+ *
* @variable_name_size: size of variable_name buffer in byte
* @variable_name: name of uefi variable's name in u16
* @vendor: vendor's guid
@@ -322,8 +324,7 @@
* This function implements the GetNextVariableName service.
*
* See the Unified Extensible Firmware Interface (UEFI) specification for
- * details: http://wiki.phoenix.com/wiki/index.php/
- * EFI_RUNTIME_SERVICES#GetNextVariableName.28.29
+ * details.
*
* Return: status code
*/
@@ -423,17 +424,17 @@
efi_uintn_t data_size, const void *data)
{
char *native_name = NULL, *val = NULL, *s;
+ const char *old_val;
+ size_t old_size;
efi_status_t ret = EFI_SUCCESS;
u32 attr;
EFI_ENTRY("\"%ls\" %pUl %x %zu %p", variable_name, vendor, attributes,
data_size, data);
- /* TODO: implement APPEND_WRITE */
if (!variable_name || !*variable_name || !vendor ||
((attributes & EFI_VARIABLE_RUNTIME_ACCESS) &&
- !(attributes & EFI_VARIABLE_BOOTSERVICE_ACCESS)) ||
- (attributes & EFI_VARIABLE_APPEND_WRITE)) {
+ !(attributes & EFI_VARIABLE_BOOTSERVICE_ACCESS))) {
ret = EFI_INVALID_PARAMETER;
goto out;
}
@@ -442,37 +443,54 @@
if (ret)
goto out;
-#define ACCESS_ATTR (EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_BOOTSERVICE_ACCESS)
+ old_val = env_get(native_name);
+ if (old_val) {
+ old_val = parse_attr(old_val, &attr);
- if ((data_size == 0) || !(attributes & ACCESS_ATTR)) {
- /* delete the variable: */
- env_set(native_name, NULL);
- ret = EFI_SUCCESS;
- goto out;
- }
-
- val = env_get(native_name);
- if (val) {
- parse_attr(val, &attr);
-
- /* We should not free val */
- val = NULL;
+ /* check read-only first */
if (attr & READ_ONLY) {
ret = EFI_WRITE_PROTECTED;
goto out;
}
- /*
- * attributes won't be changed
- * TODO: take care of APPEND_WRITE once supported
- */
- if (attr != attributes) {
+ if ((data_size == 0 &&
+ !(attributes & EFI_VARIABLE_APPEND_WRITE)) ||
+ !attributes) {
+ /* delete the variable: */
+ env_set(native_name, NULL);
+ ret = EFI_SUCCESS;
+ goto out;
+ }
+
+ /* attributes won't be changed */
+ if (attr != (attributes & ~EFI_VARIABLE_APPEND_WRITE)) {
ret = EFI_INVALID_PARAMETER;
goto out;
}
+
+ if (attributes & EFI_VARIABLE_APPEND_WRITE) {
+ if (!prefix(old_val, "(blob)")) {
+ ret = EFI_DEVICE_ERROR;
+ goto out;
+ }
+ old_size = strlen(old_val);
+ } else {
+ old_size = 0;
+ }
+ } else {
+ if ((data_size == 0 &&
+ !(attributes & EFI_VARIABLE_APPEND_WRITE)) ||
+ !attributes) {
+ /* delete, but nothing to do */
+ ret = EFI_NOT_FOUND;
+ goto out;
+ }
+
+ old_size = 0;
}
- val = malloc(2 * data_size + strlen("{ro,run,boot,nv}(blob)") + 1);
+ val = malloc(old_size + 2 * data_size
+ + strlen("{ro,run,boot,nv}(blob)") + 1);
if (!val) {
ret = EFI_OUT_OF_RESOURCES;
goto out;
@@ -480,10 +498,7 @@
s = val;
- /*
- * store attributes
- * TODO: several attributes are not supported
- */
+ /* store attributes */
attributes &= (EFI_VARIABLE_NON_VOLATILE |
EFI_VARIABLE_BOOTSERVICE_ACCESS |
EFI_VARIABLE_RUNTIME_ACCESS);
@@ -504,8 +519,13 @@
}
s += sprintf(s, "}");
+ if (old_size)
+ /* APPEND_WRITE */
+ s += sprintf(s, old_val);
+ else
+ s += sprintf(s, "(blob)");
+
/* store payload: */
- s += sprintf(s, "(blob)");
s = bin2hex(s, data, data_size);
*s = '\0';
@@ -520,3 +540,103 @@
return EFI_EXIT(ret);
}
+
+/**
+ * efi_query_variable_info() - get information about EFI variables
+ *
+ * This function implements the QueryVariableInfo() runtime service.
+ *
+ * See the Unified Extensible Firmware Interface (UEFI) specification for
+ * details.
+ *
+ * @attributes: bitmask to select variables to be
+ * queried
+ * @maximum_variable_storage_size: maximum size of storage area for the
+ * selected variable types
+ * @remaining_variable_storage_size: remaining size of storage are for the
+ * selected variable types
+ * @maximum_variable_size: maximum size of a variable of the
+ * selected type
+ * Returns: status code
+ */
+efi_status_t __efi_runtime EFIAPI efi_query_variable_info(
+ u32 attributes,
+ u64 *maximum_variable_storage_size,
+ u64 *remaining_variable_storage_size,
+ u64 *maximum_variable_size)
+{
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ * efi_get_variable_runtime() - runtime implementation of GetVariable()
+ *
+ * @variable_name: name of the variable
+ * @vendor: vendor GUID
+ * @attributes: attributes of the variable
+ * @data_size: size of the buffer to which the variable value is copied
+ * @data: buffer to which the variable value is copied
+ * Return: status code
+ */
+static efi_status_t __efi_runtime EFIAPI
+efi_get_variable_runtime(u16 *variable_name, const efi_guid_t *vendor,
+ u32 *attributes, efi_uintn_t *data_size, void *data)
+{
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ * efi_get_next_variable_name_runtime() - runtime implementation of
+ * GetNextVariable()
+ *
+ * @variable_name_size: size of variable_name buffer in byte
+ * @variable_name: name of uefi variable's name in u16
+ * @vendor: vendor's guid
+ * Return: status code
+ */
+static efi_status_t __efi_runtime EFIAPI
+efi_get_next_variable_name_runtime(efi_uintn_t *variable_name_size,
+ u16 *variable_name, const efi_guid_t *vendor)
+{
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ * efi_set_variable_runtime() - runtime implementation of SetVariable()
+ *
+ * @variable_name: name of the variable
+ * @vendor: vendor GUID
+ * @attributes: attributes of the variable
+ * @data_size: size of the buffer with the variable value
+ * @data: buffer with the variable value
+ * Return: status code
+ */
+static efi_status_t __efi_runtime EFIAPI
+efi_set_variable_runtime(u16 *variable_name, const efi_guid_t *vendor,
+ u32 attributes, efi_uintn_t data_size,
+ const void *data)
+{
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ * efi_variables_boot_exit_notify() - notify ExitBootServices() is called
+ */
+void efi_variables_boot_exit_notify(void)
+{
+ efi_runtime_services.get_variable = efi_get_variable_runtime;
+ efi_runtime_services.get_next_variable_name =
+ efi_get_next_variable_name_runtime;
+ efi_runtime_services.set_variable = efi_set_variable_runtime;
+ efi_update_table_header_crc32(&efi_runtime_services.hdr);
+}
+
+/**
+ * efi_init_variables() - initialize variable services
+ *
+ * Return: status code
+ */
+efi_status_t efi_init_variables(void)
+{
+ return EFI_SUCCESS;
+}
diff --git a/lib/efi_selftest/Kconfig b/lib/efi_selftest/Kconfig
index 59f9f36..d20f589 100644
--- a/lib/efi_selftest/Kconfig
+++ b/lib/efi_selftest/Kconfig
@@ -1,9 +1,9 @@
config CMD_BOOTEFI_SELFTEST
- bool "Allow booting an EFI efi_selftest"
+ bool "UEFI unit tests"
depends on CMD_BOOTEFI
imply FAT
imply FAT_WRITE
help
- This adds an EFI test application to U-Boot that can be executed
- with the 'bootefi selftest' command. It provides extended tests of
- the EFI API implementation.
+ This adds a UEFI test application to U-Boot that can be executed
+ via the 'bootefi selftest' command. It provides extended tests of
+ the UEFI API implementation.
diff --git a/lib/efi_selftest/Makefile b/lib/efi_selftest/Makefile
index 3bebd0f..8348014 100644
--- a/lib/efi_selftest/Makefile
+++ b/lib/efi_selftest/Makefile
@@ -20,7 +20,6 @@
efi_selftest_devicepath_util.o \
efi_selftest_events.o \
efi_selftest_event_groups.o \
-efi_selftest_exception.o \
efi_selftest_exitbootservices.o \
efi_selftest_gop.o \
efi_selftest_loaded_image.o \
@@ -28,6 +27,7 @@
efi_selftest_memory.o \
efi_selftest_open_protocol.o \
efi_selftest_register_notify.o \
+efi_selftest_set_virtual_address_map.o \
efi_selftest_snp.o \
efi_selftest_textinput.o \
efi_selftest_textinputex.o \
@@ -35,6 +35,7 @@
efi_selftest_tpl.o \
efi_selftest_util.o \
efi_selftest_variables.o \
+efi_selftest_variables_runtime.o \
efi_selftest_watchdog.o
obj-$(CONFIG_EFI_DEVICE_PATH_TO_TEXT) += efi_selftest_devicepath.o
@@ -53,21 +54,28 @@
obj-y += efi_selftest_block_device.o
endif
-# TODO: As of v2019.01 the relocation code for the EFI application cannot
-# be built on ARMv7-M, Sandbox, and x86_64.
-ifeq ($(CONFIG_SANDBOX)$(CONFIG_CPU_V7M)$(CONFIG_X86_64),)
+# TODO: As of v2019.10 the relocation code for the EFI application cannot
+# be built on ARMv7-M and Sandbox.
+ifeq ($(CONFIG_SANDBOX)$(CONFIG_CPU_V7M),)
obj-y += \
+efi_selftest_exception.o \
efi_selftest_loadimage.o \
efi_selftest_startimage_exit.o \
efi_selftest_startimage_return.o
targets += \
+efi_miniapp_file_image_exception.h \
efi_miniapp_file_image_exit.h \
efi_miniapp_file_image_return.h \
+efi_selftest_miniapp_exception.efi \
efi_selftest_miniapp_exit.efi \
efi_selftest_miniapp_return.efi
+$(obj)/efi_miniapp_file_image_exception.h: $(obj)/efi_selftest_miniapp_exception.efi
+ $(obj)/../../tools/file2include $(obj)/efi_selftest_miniapp_exception.efi > \
+ $(obj)/efi_miniapp_file_image_exception.h
+
$(obj)/efi_miniapp_file_image_exit.h: $(obj)/efi_selftest_miniapp_exit.efi
$(obj)/../../tools/file2include $(obj)/efi_selftest_miniapp_exit.efi > \
$(obj)/efi_miniapp_file_image_exit.h
@@ -78,6 +86,8 @@
$(obj)/efi_selftest_loadimage.o: $(obj)/efi_miniapp_file_image_exit.h
+$(obj)/efi_selftest_exception.o: $(obj)/efi_miniapp_file_image_exception.h
+
$(obj)/efi_selftest_startimage_exit.o: $(obj)/efi_miniapp_file_image_exit.h
$(obj)/efi_selftest_startimage_return.o: $(obj)/efi_miniapp_file_image_return.h
diff --git a/lib/efi_selftest/efi_selftest_exception.c b/lib/efi_selftest/efi_selftest_exception.c
index 76cfb88..6e900a3 100644
--- a/lib/efi_selftest/efi_selftest_exception.c
+++ b/lib/efi_selftest/efi_selftest_exception.c
@@ -2,42 +2,138 @@
/*
* efi_selftest_exception
*
- * Copyright (c) 2018 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ * Copyright (c) 2019 Heinrich Schuchardt <xypron.glpk@gmx.de>
*
- * Test the handling of exceptions by trying to execute an undefined
- * instruction.
+ * This test checks the handling of exceptions.
+ *
+ * The efi_selftest_miniapp_exception.efi application is loaded into memory
+ * and started.
*/
#include <efi_selftest.h>
+/* Include containing the UEFI application */
+#include "efi_miniapp_file_image_exception.h"
-/**
- * undefined_instruction() - try to executed an undefined instruction
+/* Block size of compressed disk image */
+#define COMPRESSED_DISK_IMAGE_BLOCK_SIZE 8
+
+/* Binary logarithm of the block size */
+#define LB_BLOCK_SIZE 9
+
+/* File device path for LoadImage() */
+static struct {
+ struct efi_device_path dp;
+ u16 filename[8];
+ struct efi_device_path end;
+} dp = {
+ {
+ DEVICE_PATH_TYPE_MEDIA_DEVICE,
+ DEVICE_PATH_SUB_TYPE_FILE_PATH,
+ sizeof(dp.dp) + sizeof(dp.filename),
+ },
+ L"bug.efi",
+ {
+ DEVICE_PATH_TYPE_END,
+ DEVICE_PATH_SUB_TYPE_END,
+ sizeof(dp.end),
+ }
+};
+
+static efi_handle_t image_handle;
+static struct efi_boot_services *boottime;
+
+/* One 8 byte block of the compressed disk image */
+struct line {
+ size_t addr;
+ char *line;
+};
+
+/* Compressed file image */
+struct compressed_file_image {
+ size_t length;
+ struct line lines[];
+};
+
+static struct compressed_file_image img = EFI_ST_DISK_IMG;
+
+/* Decompressed file image */
+static u8 *image;
+
+/*
+ * Decompress the disk image.
+ *
+ * @image decompressed disk image
+ * @return status code
*/
-static void undefined_instruction(void)
+static efi_status_t decompress(u8 **image)
{
-#if defined(CONFIG_ARM)
- /*
- * 0xe7f...f. is undefined in ARM mode
- * 0xde.. is undefined in Thumb mode
- */
- asm volatile (".word 0xe7f7defb\n");
-#elif defined(CONFIG_RISCV)
- asm volatile (".word 0xffffffff\n");
-#elif defined(CONFIG_X86)
- asm volatile (".word 0xffff\n");
-#endif
+ u8 *buf;
+ size_t i;
+ size_t addr;
+ size_t len;
+ efi_status_t ret;
+
+ ret = boottime->allocate_pool(EFI_LOADER_DATA, img.length,
+ (void **)&buf);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Out of memory\n");
+ return ret;
+ }
+ boottime->set_mem(buf, img.length, 0);
+
+ for (i = 0; ; ++i) {
+ if (!img.lines[i].line)
+ break;
+ addr = img.lines[i].addr;
+ len = COMPRESSED_DISK_IMAGE_BLOCK_SIZE;
+ if (addr + len > img.length)
+ len = img.length - addr;
+ boottime->copy_mem(buf + addr, img.lines[i].line, len);
+ }
+ *image = buf;
+ return ret;
}
-/**
- * execute() - execute unit test
+/*
+ * Setup unit test.
*
- * Return: EFI_ST_SUCCESS for success
+ * @handle: handle of the loaded image
+ * @systable: system table
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int setup(const efi_handle_t handle,
+ const struct efi_system_table *systable)
+{
+ image_handle = handle;
+ boottime = systable->boottime;
+
+ /* Load the application image into memory */
+ decompress(&image);
+
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Execute unit test.
+ *
+ * Load and start the application image.
+ *
+ * @return: EFI_ST_SUCCESS for success
*/
static int execute(void)
{
- undefined_instruction();
+ efi_status_t ret;
+ efi_handle_t handle;
- efi_st_error("An undefined instruction exception was not raised\n");
+ ret = boottime->load_image(false, image_handle, &dp.dp, image,
+ img.length, &handle);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to load image\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->start_image(handle, NULL, NULL);
+
+ efi_st_error("Exception not triggered\n");
return EFI_ST_FAILURE;
}
@@ -45,6 +141,7 @@
EFI_UNIT_TEST(exception) = {
.name = "exception",
.phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
+ .setup = setup,
.execute = execute,
.on_request = true,
};
diff --git a/lib/efi_selftest/efi_selftest_exitbootservices.c b/lib/efi_selftest/efi_selftest_exitbootservices.c
index f1a1360..4fecd1b 100644
--- a/lib/efi_selftest/efi_selftest_exitbootservices.c
+++ b/lib/efi_selftest/efi_selftest_exitbootservices.c
@@ -56,28 +56,6 @@
}
/*
- * Tear down unit test.
- *
- * Close the event created in setup.
- *
- * @return: EFI_ST_SUCCESS for success
- */
-static int teardown(void)
-{
- efi_status_t ret;
-
- if (event_notify) {
- ret = boottime->close_event(event_notify);
- event_notify = NULL;
- if (ret != EFI_SUCCESS) {
- efi_st_error("could not close event\n");
- return EFI_ST_FAILURE;
- }
- }
- return EFI_ST_SUCCESS;
-}
-
-/*
* Execute unit test.
*
* Check that the notification function of the EVT_SIGNAL_EXIT_BOOT_SERVICES
@@ -107,5 +85,4 @@
.phase = EFI_SETUP_BEFORE_BOOTTIME_EXIT,
.setup = setup,
.execute = execute,
- .teardown = teardown,
};
diff --git a/lib/efi_selftest/efi_selftest_miniapp_exception.c b/lib/efi_selftest/efi_selftest_miniapp_exception.c
new file mode 100644
index 0000000..63c63d7
--- /dev/null
+++ b/lib/efi_selftest/efi_selftest_miniapp_exception.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * efi_selftest_miniapp_return
+ *
+ * Copyright (c) 2019 Heinrich Schuchardt
+ *
+ * This EFI application triggers an exception.
+ */
+
+#include <common.h>
+#include <efi_api.h>
+
+/*
+ * Entry point of the EFI application.
+ *
+ * @handle handle of the loaded image
+ * @systable system table
+ * @return status code
+ */
+efi_status_t EFIAPI efi_main(efi_handle_t handle,
+ struct efi_system_table *systable)
+{
+ struct efi_simple_text_output_protocol *con_out = systable->con_out;
+
+ con_out->output_string(con_out,
+ L"EFI application triggers exception.\n");
+
+#if defined(CONFIG_ARM)
+ /*
+ * 0xe7f...f. is undefined in ARM mode
+ * 0xde.. is undefined in Thumb mode
+ */
+ asm volatile (".word 0xe7f7defb\n");
+#elif defined(CONFIG_RISCV)
+ asm volatile (".word 0xffffffff\n");
+#elif defined(CONFIG_X86)
+ asm volatile (".word 0xffff\n");
+#endif
+ con_out->output_string(con_out, L"Exception not triggered.\n");
+ return EFI_ABORTED;
+}
diff --git a/lib/efi_selftest/efi_selftest_set_virtual_address_map.c b/lib/efi_selftest/efi_selftest_set_virtual_address_map.c
new file mode 100644
index 0000000..a4e5a50
--- /dev/null
+++ b/lib/efi_selftest/efi_selftest_set_virtual_address_map.c
@@ -0,0 +1,207 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * efi_selftest_set_virtual_address_map.c
+ *
+ * Copyright (c) 2019 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ *
+ * This test checks the notification of EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE
+ * and the following services: SetVirtualAddressMap, ConvertPointer.
+ */
+
+#include <efi_selftest.h>
+
+static const struct efi_boot_services *boottime;
+static const struct efi_runtime_services *runtime;
+static struct efi_event *event;
+static struct efi_mem_desc *memory_map;
+static efi_uintn_t map_size;
+static efi_uintn_t desc_size;
+static u32 desc_version;
+static u64 page1;
+static u64 page2;
+static u32 notify_call_count;
+static bool convert_pointer_failed;
+
+/**
+ * notify () - notification function
+ *
+ * This function is called when the EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE event
+ * occurs. The correct output of ConvertPointer() is checked.
+ *
+ * @event notified event
+ * @context pointer to the notification count
+ */
+static void EFIAPI notify(struct efi_event *event, void *context)
+{
+ void *addr;
+ efi_status_t ret;
+
+ ++notify_call_count;
+
+ addr = (void *)(uintptr_t)page1;
+ ret = runtime->convert_pointer(0, &addr);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("ConvertPointer failed\n");
+ convert_pointer_failed = true;
+ return;
+ }
+ if ((uintptr_t)addr != page1 + EFI_PAGE_SIZE) {
+ efi_st_error("ConvertPointer wrong address\n");
+ convert_pointer_failed = true;
+ return;
+ }
+
+ addr = (void *)(uintptr_t)page2;
+ ret = runtime->convert_pointer(0, &addr);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("ConvertPointer failed\n");
+ convert_pointer_failed = true;
+ return;
+ }
+ if ((uintptr_t)addr != page2 + 2 * EFI_PAGE_SIZE) {
+ efi_st_error("ConvertPointer wrong address\n");
+ convert_pointer_failed = true;
+ }
+}
+
+/**
+ * setup() - setup unit test
+ *
+ * The memory map is read. Boottime only entries are deleted. Two entries for
+ * newly allocated pages are added. For these virtual addresses deviating from
+ * the physical addresses are set.
+ *
+ * @handle: handle of the loaded image
+ * @systable: system table
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int setup(const efi_handle_t handle,
+ const struct efi_system_table *systable)
+{
+ efi_uintn_t map_key;
+ efi_status_t ret;
+ struct efi_mem_desc *end, *pos1, *pos2;
+
+ boottime = systable->boottime;
+ runtime = systable->runtime;
+
+ ret = boottime->create_event(EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE,
+ TPL_CALLBACK, notify, NULL,
+ &event);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("could not create event\n");
+ return EFI_ST_FAILURE;
+ }
+
+ ret = boottime->get_memory_map(&map_size, NULL, &map_key, &desc_size,
+ &desc_version);
+ if (ret != EFI_BUFFER_TOO_SMALL) {
+ efi_st_error(
+ "GetMemoryMap did not return EFI_BUFFER_TOO_SMALL\n");
+ return EFI_ST_FAILURE;
+ }
+ /* Allocate extra space for newly allocated memory */
+ map_size += 3 * sizeof(struct efi_mem_desc);
+ ret = boottime->allocate_pool(EFI_BOOT_SERVICES_DATA, map_size,
+ (void **)&memory_map);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("AllocatePool failed\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->get_memory_map(&map_size, memory_map, &map_key,
+ &desc_size, &desc_version);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("GetMemoryMap failed\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->allocate_pages(EFI_ALLOCATE_ANY_PAGES,
+ EFI_BOOT_SERVICES_DATA, 2, &page1);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("AllocatePages failed\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->allocate_pages(EFI_ALLOCATE_ANY_PAGES,
+ EFI_BOOT_SERVICES_DATA, 3, &page2);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("AllocatePages failed\n");
+ return EFI_ST_FAILURE;
+ }
+ /* Remove entries not relevant for runtime from map */
+ end = (struct efi_mem_desc *)((u8 *)memory_map + map_size);
+ for (pos1 = memory_map, pos2 = memory_map;
+ pos2 < end; ++pos2) {
+ switch (pos2->type) {
+ case EFI_LOADER_CODE:
+ case EFI_LOADER_DATA:
+ case EFI_BOOT_SERVICES_CODE:
+ case EFI_BOOT_SERVICES_DATA:
+ case EFI_CONVENTIONAL_MEMORY:
+ continue;
+ }
+ memcpy(pos1, pos2, desc_size);
+ ++pos1;
+ }
+
+ /*
+ * Add entries with virtual addresses deviating from the physical
+ * addresses. By choosing virtual address ranges within the allocated
+ * physical pages address space collisions are avoided.
+ */
+ pos1->type = EFI_RUNTIME_SERVICES_DATA;
+ pos1->reserved = 0;
+ pos1->physical_start = page1;
+ pos1->virtual_start = page1 + EFI_PAGE_SIZE;
+ pos1->num_pages = 1;
+ pos1->attribute = EFI_MEMORY_RUNTIME;
+ ++pos1;
+
+ pos1->type = EFI_RUNTIME_SERVICES_DATA;
+ pos1->reserved = 0;
+ pos1->physical_start = page2;
+ pos1->virtual_start = page2 + 2 * EFI_PAGE_SIZE;
+ pos1->num_pages = 1;
+ pos1->attribute = EFI_MEMORY_RUNTIME;
+ ++pos1;
+
+ map_size = (u8 *)pos1 - (u8 *)memory_map;
+
+ return EFI_ST_SUCCESS;
+}
+
+/**
+ * execute() - execute unit test
+ *
+ * SetVirtualAddressMap() is called with the memory map prepared in setup().
+ *
+ * The triggering of the EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE event is checked via
+ * the call count of the notification function.
+ *
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int execute(void)
+{
+ efi_status_t ret;
+
+ ret = runtime->set_virtual_address_map(map_size, desc_size,
+ desc_version, memory_map);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("SetVirtualAddressMap failed\n");
+ return EFI_ST_FAILURE;
+ }
+ if (notify_call_count != 1) {
+ efi_st_error("EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE triggered %d times\n",
+ notify_call_count);
+ return EFI_ST_FAILURE;
+ }
+ if (convert_pointer_failed)
+ return EFI_ST_FAILURE;
+
+ return EFI_ST_SUCCESS;
+}
+
+EFI_UNIT_TEST(virtaddrmap) = {
+ .name = "virtual address map",
+ .phase = EFI_SETUP_BEFORE_BOOTTIME_EXIT,
+ .setup = setup,
+ .execute = execute,
+};
diff --git a/lib/efi_selftest/efi_selftest_snp.c b/lib/efi_selftest/efi_selftest_snp.c
index 4c26619..9797eca 100644
--- a/lib/efi_selftest/efi_selftest_snp.c
+++ b/lib/efi_selftest/efi_selftest_snp.c
@@ -228,6 +228,26 @@
efi_st_error("WaitForPacket event missing\n");
return EFI_ST_FAILURE;
}
+ if (net->mode->state == EFI_NETWORK_INITIALIZED) {
+ /*
+ * Shut down network adapter.
+ */
+ ret = net->shutdown(net);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to shut down network adapter\n");
+ return EFI_ST_FAILURE;
+ }
+ }
+ if (net->mode->state == EFI_NETWORK_STARTED) {
+ /*
+ * Stop network adapter.
+ */
+ ret = net->stop(net);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to stop network adapter\n");
+ return EFI_ST_FAILURE;
+ }
+ }
/*
* Start network adapter.
*/
@@ -236,6 +256,10 @@
efi_st_error("Failed to start network adapter\n");
return EFI_ST_FAILURE;
}
+ if (net->mode->state != EFI_NETWORK_STARTED) {
+ efi_st_error("Failed to start network adapter\n");
+ return EFI_ST_FAILURE;
+ }
/*
* Initialize network adapter.
*/
@@ -244,6 +268,10 @@
efi_st_error("Failed to initialize network adapter\n");
return EFI_ST_FAILURE;
}
+ if (net->mode->state != EFI_NETWORK_INITIALIZED) {
+ efi_st_error("Failed to initialize network adapter\n");
+ return EFI_ST_FAILURE;
+ }
return EFI_ST_SUCCESS;
}
@@ -268,6 +296,7 @@
struct efi_mac_address destaddr;
size_t buffer_size;
u8 *addr;
+
/*
* The timeout is to occur after 10 s.
*/
@@ -298,6 +327,8 @@
events[0] = timer;
events[1] = net->wait_for_packet;
for (;;) {
+ u32 int_status;
+
/*
* Wait for packet to be received or timer event.
*/
@@ -323,8 +354,17 @@
* Receive packet
*/
buffer_size = sizeof(buffer);
- net->receive(net, NULL, &buffer_size, &buffer,
- &srcaddr, &destaddr, NULL);
+ ret = net->get_status(net, &int_status, NULL);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to get status");
+ return EFI_ST_FAILURE;
+ }
+ if (!(int_status & EFI_SIMPLE_NETWORK_RECEIVE_INTERRUPT)) {
+ efi_st_error("RX interrupt not set");
+ return EFI_ST_FAILURE;
+ }
+ ret = net->receive(net, NULL, &buffer_size, &buffer,
+ &srcaddr, &destaddr, NULL);
if (ret != EFI_SUCCESS) {
efi_st_error("Failed to receive packet");
return EFI_ST_FAILURE;
@@ -400,6 +440,18 @@
}
if (net) {
/*
+ * Shut down network adapter.
+ */
+ ret = net->shutdown(net);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to shut down network adapter\n");
+ exit_status = EFI_ST_FAILURE;
+ }
+ if (net->mode->state != EFI_NETWORK_STARTED) {
+ efi_st_error("Failed to shutdown network adapter\n");
+ return EFI_ST_FAILURE;
+ }
+ /*
* Stop network adapter.
*/
ret = net->stop(net);
@@ -407,13 +459,9 @@
efi_st_error("Failed to stop network adapter\n");
exit_status = EFI_ST_FAILURE;
}
- /*
- * Shut down network adapter.
- */
- ret = net->shutdown(net);
- if (ret != EFI_SUCCESS) {
- efi_st_error("Failed to shut down network adapter\n");
- exit_status = EFI_ST_FAILURE;
+ if (net->mode->state != EFI_NETWORK_STOPPED) {
+ efi_st_error("Failed to stop network adapter\n");
+ return EFI_ST_FAILURE;
}
}
diff --git a/lib/efi_selftest/efi_selftest_variables.c b/lib/efi_selftest/efi_selftest_variables.c
index 06c1a03..a6b41d1 100644
--- a/lib/efi_selftest/efi_selftest_variables.c
+++ b/lib/efi_selftest/efi_selftest_variables.c
@@ -21,6 +21,9 @@
static const efi_guid_t guid_vendor1 =
EFI_GUID(0xff629290, 0x1fc1, 0xd73f,
0x8f, 0xb1, 0x32, 0xf9, 0x0c, 0xa0, 0x42, 0xea);
+static const efi_guid_t guid_global =
+ EFI_GUID(0x8be4df61, 0x93ca, 0x11d2,
+ 0xaa, 0x0d, 0x00, 0xe0, 0x98, 0x03, 0x2b, 0x8c);
/*
* Setup unit test.
@@ -116,7 +119,7 @@
EFI_VARIABLE_APPEND_WRITE,
7, v + 8);
if (ret != EFI_SUCCESS) {
- efi_st_todo("SetVariable(APPEND_WRITE) failed\n");
+ efi_st_error("SetVariable(APPEND_WRITE) failed\n");
} else {
len = EFI_ST_MAX_DATA_SIZE;
ret = runtime->get_variable(L"efi_st_var1", &guid_vendor1,
@@ -131,6 +134,21 @@
if (memcmp(data, v, len))
efi_st_todo("GetVariable returned wrong value\n");
}
+ /* Append variable 2 */
+ ret = runtime->set_variable(L"efi_none", &guid_vendor1,
+ EFI_VARIABLE_BOOTSERVICE_ACCESS |
+ EFI_VARIABLE_APPEND_WRITE,
+ 15, v);
+ if (ret != EFI_NOT_FOUND)
+ efi_st_error("SetVariable(APPEND_WRITE) with size 0 to non-existent variable returns wrong code\n");
+ /* Append variable 3 */
+ ret = runtime->set_variable(L"PlatformLangCodes", &guid_global,
+ EFI_VARIABLE_BOOTSERVICE_ACCESS |
+ EFI_VARIABLE_RUNTIME_ACCESS |
+ EFI_VARIABLE_APPEND_WRITE,
+ 15, v);
+ if (ret != EFI_WRITE_PROTECTED)
+ efi_st_todo("SetVariable(APPEND_WRITE) to read-only variable returns wrong code\n");
/* Enumerate variables */
boottime->set_mem(&guid, 16, 0);
*varname = 0;
diff --git a/lib/efi_selftest/efi_selftest_variables_runtime.c b/lib/efi_selftest/efi_selftest_variables_runtime.c
new file mode 100644
index 0000000..b3b40ad
--- /dev/null
+++ b/lib/efi_selftest/efi_selftest_variables_runtime.c
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * efi_selftest_variables_runtime
+ *
+ * Copyright (c) 2019 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ *
+ * This unit test checks the runtime services for variables after
+ * ExitBootServices():
+ * GetVariable, GetNextVariableName, SetVariable, QueryVariableInfo.
+ */
+
+#include <efi_selftest.h>
+
+#define EFI_ST_MAX_DATA_SIZE 16
+#define EFI_ST_MAX_VARNAME_SIZE 40
+
+static struct efi_boot_services *boottime;
+static struct efi_runtime_services *runtime;
+static const efi_guid_t guid_vendor0 =
+ EFI_GUID(0x67029eb5, 0x0af2, 0xf6b1,
+ 0xda, 0x53, 0xfc, 0xb5, 0x66, 0xdd, 0x1c, 0xe6);
+
+/*
+ * Setup unit test.
+ *
+ * @handle handle of the loaded image
+ * @systable system table
+ */
+static int setup(const efi_handle_t img_handle,
+ const struct efi_system_table *systable)
+{
+ boottime = systable->boottime;
+ runtime = systable->runtime;
+
+ return EFI_ST_SUCCESS;
+}
+
+/**
+ * execute() - execute unit test
+ *
+ * As runtime support is not implmented expect EFI_UNSUPPORTED to be returned.
+ */
+static int execute(void)
+{
+ efi_status_t ret;
+ efi_uintn_t len;
+ u32 attr;
+ u8 v[16] = {0x5d, 0xd1, 0x5e, 0x51, 0x5a, 0x05, 0xc7, 0x0c,
+ 0x35, 0x4a, 0xae, 0x87, 0xa5, 0xdf, 0x0f, 0x65,};
+ u8 data[EFI_ST_MAX_DATA_SIZE];
+ u16 varname[EFI_ST_MAX_VARNAME_SIZE];
+ efi_guid_t guid;
+ u64 max_storage, rem_storage, max_size;
+
+ ret = runtime->query_variable_info(EFI_VARIABLE_BOOTSERVICE_ACCESS,
+ &max_storage, &rem_storage,
+ &max_size);
+ if (ret != EFI_UNSUPPORTED) {
+ efi_st_error("QueryVariableInfo failed\n");
+ return EFI_ST_FAILURE;
+ }
+
+ ret = runtime->set_variable(L"efi_st_var0", &guid_vendor0,
+ EFI_VARIABLE_BOOTSERVICE_ACCESS |
+ EFI_VARIABLE_RUNTIME_ACCESS,
+ 3, v + 4);
+ if (ret != EFI_UNSUPPORTED) {
+ efi_st_error("SetVariable failed\n");
+ return EFI_ST_FAILURE;
+ }
+ len = 3;
+ ret = runtime->get_variable(L"efi_st_var0", &guid_vendor0,
+ &attr, &len, data);
+ if (ret != EFI_UNSUPPORTED) {
+ efi_st_error("GetVariable failed\n");
+ return EFI_ST_FAILURE;
+ }
+ memset(&guid, 0, 16);
+ *varname = 0;
+ ret = runtime->get_next_variable_name(&len, varname, &guid);
+ if (ret != EFI_UNSUPPORTED) {
+ efi_st_error("GetNextVariableName failed\n");
+ return EFI_ST_FAILURE;
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+EFI_UNIT_TEST(variables_run) = {
+ .name = "variables at runtime",
+ .phase = EFI_SETUP_BEFORE_BOOTTIME_EXIT,
+ .setup = setup,
+ .execute = execute,
+};
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 3ee786b..74430c8 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -8,9 +8,11 @@
#include <boot_fit.h>
#include <dm.h>
#include <dm/of_extra.h>
+#include <env.h>
#include <errno.h>
#include <fdtdec.h>
#include <fdt_support.h>
+#include <gzip.h>
#include <mapmem.h>
#include <linux/libfdt.h>
#include <serial.h>
@@ -215,7 +217,7 @@
if ((fdt32_to_cpu(*cell) & type) == type) {
addr->phys_hi = fdt32_to_cpu(cell[0]);
addr->phys_mid = fdt32_to_cpu(cell[1]);
- addr->phys_lo = fdt32_to_cpu(cell[1]);
+ addr->phys_lo = fdt32_to_cpu(cell[2]);
break;
}
@@ -1533,16 +1535,14 @@
puts("Failed to read control FDT\n");
return -1;
}
+# elif defined(CONFIG_OF_PRIOR_STAGE)
+ gd->fdt_blob = (void *)prior_stage_fdt_address;
# endif
# ifndef CONFIG_SPL_BUILD
/* Allow the early environment to override the fdt address */
-# if CONFIG_IS_ENABLED(OF_PRIOR_STAGE)
- gd->fdt_blob = (void *)prior_stage_fdt_address;
-# else
gd->fdt_blob = map_sysmem
(env_get_ulong("fdtcontroladdr", 16,
(unsigned long)map_to_sysmem(gd->fdt_blob)), 0);
-# endif
# endif
# if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
diff --git a/lib/fdtdec_test.c b/lib/fdtdec_test.c
index 1f4f270..e8bfd1f 100644
--- a/lib/fdtdec_test.c
+++ b/lib/fdtdec_test.c
@@ -138,6 +138,7 @@
}
printf("pass\n");
+ free(blob);
return 0;
}
@@ -292,6 +293,7 @@
CHECKVAL(make_fdt_carveout(fdt, FDT_SIZE, 2, 2), 0);
CHECKOK(check_fdt_carveout(fdt, 2, 2));
+ free(fdt);
return 0;
}
diff --git a/lib/gunzip.c b/lib/gunzip.c
index 15c7b2c..1d65616 100644
--- a/lib/gunzip.c
+++ b/lib/gunzip.c
@@ -5,14 +5,15 @@
*/
#include <common.h>
-#include <watchdog.h>
#include <command.h>
#include <console.h>
+#include <div64.h>
+#include <gzip.h>
#include <image.h>
#include <malloc.h>
#include <memalign.h>
+#include <watchdog.h>
#include <u-boot/zlib.h>
-#include <div64.h>
#define HEADER0 '\x1f'
#define HEADER1 '\x8b'
diff --git a/lib/gzip.c b/lib/gzip.c
index 674d732..c6c0ec8 100644
--- a/lib/gzip.c
+++ b/lib/gzip.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <watchdog.h>
#include <command.h>
+#include <gzip.h>
#include <image.h>
#include <malloc.h>
#include <memalign.h>
diff --git a/lib/hang.c b/lib/hang.c
index c5a7869..4d026a3 100644
--- a/lib/hang.c
+++ b/lib/hang.c
@@ -9,6 +9,7 @@
#include <common.h>
#include <bootstage.h>
+#include <os.h>
/**
* hang - stop processing by staying in an endless loop
@@ -26,6 +27,8 @@
puts("### ERROR ### Please RESET the board ###\n");
#endif
bootstage_error(BOOTSTAGE_ID_NEED_RESET);
+ if (IS_ENABLED(CONFIG_SANDBOX))
+ os_exit(1);
for (;;)
;
}
diff --git a/lib/hashtable.c b/lib/hashtable.c
index 0d288d1..2caab0a 100644
--- a/lib/hashtable.c
+++ b/lib/hashtable.c
@@ -59,14 +59,14 @@
* which describes the current status.
*/
-typedef struct _ENTRY {
+struct env_entry_node {
int used;
- ENTRY entry;
-} _ENTRY;
+ struct env_entry entry;
+};
-static void _hdelete(const char *key, struct hsearch_data *htab, ENTRY *ep,
- int idx);
+static void _hdelete(const char *key, struct hsearch_data *htab,
+ struct env_entry *ep, int idx);
/*
* hcreate()
@@ -120,7 +120,8 @@
htab->filled = 0;
/* allocate memory and zero out */
- htab->table = (_ENTRY *) calloc(htab->size + 1, sizeof(_ENTRY));
+ htab->table = (struct env_entry_node *)calloc(htab->size + 1,
+ sizeof(struct env_entry_node));
if (htab->table == NULL)
return 0;
@@ -151,7 +152,7 @@
/* free used memory */
for (i = 1; i <= htab->size; ++i) {
if (htab->table[i].used > 0) {
- ENTRY *ep = &htab->table[i].entry;
+ struct env_entry *ep = &htab->table[i].entry;
free((void *)ep->key);
free(ep->data);
@@ -193,14 +194,14 @@
* data any more.
* - The standard implementation does not provide a way to update an
* existing entry. This version will create a new entry or update an
- * existing one when both "action == ENTER" and "item.data != NULL".
+ * existing one when both "action == ENV_ENTER" and "item.data != NULL".
* - Instead of returning 1 on success, we return the index into the
* internal hash table, which is also guaranteed to be positive.
* This allows us direct access to the found hash table slot for
* example for functions like hdelete().
*/
-int hmatch_r(const char *match, int last_idx, ENTRY ** retval,
+int hmatch_r(const char *match, int last_idx, struct env_entry **retval,
struct hsearch_data *htab)
{
unsigned int idx;
@@ -222,16 +223,17 @@
/*
* Compare an existing entry with the desired key, and overwrite if the action
- * is ENTER. This is simply a helper function for hsearch_r().
+ * is ENV_ENTER. This is simply a helper function for hsearch_r().
*/
-static inline int _compare_and_overwrite_entry(ENTRY item, ACTION action,
- ENTRY **retval, struct hsearch_data *htab, int flag,
- unsigned int hval, unsigned int idx)
+static inline int _compare_and_overwrite_entry(struct env_entry item,
+ enum env_action action, struct env_entry **retval,
+ struct hsearch_data *htab, int flag, unsigned int hval,
+ unsigned int idx)
{
if (htab->table[idx].used == hval
&& strcmp(item.key, htab->table[idx].entry.key) == 0) {
/* Overwrite existing value? */
- if ((action == ENTER) && (item.data != NULL)) {
+ if (action == ENV_ENTER && item.data) {
/* check for permission */
if (htab->change_ok != NULL && htab->change_ok(
&htab->table[idx].entry, item.data,
@@ -270,8 +272,8 @@
return -1;
}
-int hsearch_r(ENTRY item, ACTION action, ENTRY ** retval,
- struct hsearch_data *htab, int flag)
+int hsearch_r(struct env_entry item, enum env_action action,
+ struct env_entry **retval, struct hsearch_data *htab, int flag)
{
unsigned int hval;
unsigned int count;
@@ -352,7 +354,7 @@
}
/* An empty bucket has been found. */
- if (action == ENTER) {
+ if (action == ENV_ENTER) {
/*
* If table is full and another entry should be
* entered return with error.
@@ -431,10 +433,10 @@
* do that.
*/
-static void _hdelete(const char *key, struct hsearch_data *htab, ENTRY *ep,
- int idx)
+static void _hdelete(const char *key, struct hsearch_data *htab,
+ struct env_entry *ep, int idx)
{
- /* free used ENTRY */
+ /* free used entry */
debug("hdelete: DELETING key \"%s\"\n", key);
free((void *)ep->key);
free(ep->data);
@@ -447,14 +449,14 @@
int hdelete_r(const char *key, struct hsearch_data *htab, int flag)
{
- ENTRY e, *ep;
+ struct env_entry e, *ep;
int idx;
debug("hdelete: DELETE key \"%s\"\n", key);
e.key = (char *)key;
- idx = hsearch_r(e, FIND, &ep, htab, 0);
+ idx = hsearch_r(e, ENV_FIND, &ep, htab, 0);
if (idx == 0) {
__set_errno(ESRCH);
return 0; /* not found */
@@ -528,8 +530,8 @@
static int cmpkey(const void *p1, const void *p2)
{
- ENTRY *e1 = *(ENTRY **) p1;
- ENTRY *e2 = *(ENTRY **) p2;
+ struct env_entry *e1 = *(struct env_entry **)p1;
+ struct env_entry *e2 = *(struct env_entry **)p2;
return (strcmp(e1->key, e2->key));
}
@@ -563,8 +565,8 @@
return 0;
}
-static int match_entry(ENTRY *ep, int flag,
- int argc, char * const argv[])
+static int match_entry(struct env_entry *ep, int flag, int argc,
+ char *const argv[])
{
int arg;
void *priv = NULL;
@@ -596,7 +598,7 @@
char **resp, size_t size,
int argc, char * const argv[])
{
- ENTRY *list[htab->size];
+ struct env_entry *list[htab->size];
char *res, *p;
size_t totlen;
int i, n;
@@ -617,7 +619,7 @@
for (i = 1, n = 0, totlen = 0; i <= htab->size; ++i) {
if (htab->table[i].used > 0) {
- ENTRY *ep = &htab->table[i].entry;
+ struct env_entry *ep = &htab->table[i].entry;
int found = match_entry(ep, flag, argc, argv);
if ((argc > 0) && (found == 0))
@@ -657,7 +659,7 @@
#endif
/* Sort list by keys */
- qsort(list, n, sizeof(ENTRY *), cmpkey);
+ qsort(list, n, sizeof(struct env_entry *), cmpkey);
/* Check if the user supplied buffer size is sufficient */
if (size) {
@@ -869,7 +871,7 @@
}
/* Parse environment; allow for '\0' and 'sep' as separators */
do {
- ENTRY e, *rv;
+ struct env_entry e, *rv;
/* skip leading white space */
while (isblank(*dp))
@@ -929,7 +931,7 @@
e.key = name;
e.data = value;
- hsearch_r(e, ENTER, &rv, htab, flag);
+ hsearch_r(e, ENV_ENTER, &rv, htab, flag);
if (rv == NULL)
printf("himport_r: can't insert \"%s=%s\" into hash table\n",
name, value);
@@ -976,7 +978,7 @@
* Walk all of the entries in the hash, calling the callback for each one.
* this allows some generic operation to be performed on each element.
*/
-int hwalk_r(struct hsearch_data *htab, int (*callback)(ENTRY *))
+int hwalk_r(struct hsearch_data *htab, int (*callback)(struct env_entry *entry))
{
int i;
int retval;
diff --git a/lib/optee/Kconfig b/lib/optee/Kconfig
index 3773d89..c398f9b 100644
--- a/lib/optee/Kconfig
+++ b/lib/optee/Kconfig
@@ -17,6 +17,7 @@
config OPTEE_TZDRAM_SIZE
hex "Amount of Trust-Zone RAM for the OPTEE image"
default 0x0000000
+ depends on OPTEE
help
The size of pre-allocated Trust Zone DRAM to allocate for the OPTEE
runtime.
@@ -24,6 +25,7 @@
config OPTEE_TZDRAM_BASE
hex "Base address of Trust-Zone RAM for the OPTEE image"
default 0x00000000
+ depends on OPTEE
help
The base address of pre-allocated Trust Zone DRAM for
the OPTEE runtime.
diff --git a/lib/rsa/rsa-sign.c b/lib/rsa/rsa-sign.c
index fb5e07b..5b5905a 100644
--- a/lib/rsa/rsa-sign.c
+++ b/lib/rsa/rsa-sign.c
@@ -141,6 +141,15 @@
snprintf(key_id, sizeof(key_id),
"pkcs11:object=%s;type=public",
name);
+ } else if (engine_id) {
+ if (keydir)
+ snprintf(key_id, sizeof(key_id),
+ "%s%s",
+ keydir, name);
+ else
+ snprintf(key_id, sizeof(key_id),
+ "%s",
+ name);
} else {
fprintf(stderr, "Engine not supported\n");
return -ENOTSUP;
@@ -252,6 +261,15 @@
snprintf(key_id, sizeof(key_id),
"pkcs11:object=%s;type=private",
name);
+ } else if (engine_id) {
+ if (keydir)
+ snprintf(key_id, sizeof(key_id),
+ "%s%s",
+ keydir, name);
+ else
+ snprintf(key_id, sizeof(key_id),
+ "%s",
+ name);
} else {
fprintf(stderr, "Engine not supported\n");
return -ENOTSUP;
diff --git a/lib/smbios.c b/lib/smbios.c
index e8ee55c..7b74971 100644
--- a/lib/smbios.c
+++ b/lib/smbios.c
@@ -6,6 +6,7 @@
*/
#include <common.h>
+#include <env.h>
#include <mapmem.h>
#include <smbios.h>
#include <tables_csum.h>
diff --git a/lib/trace.c b/lib/trace.c
index 9956442..f2402b9 100644
--- a/lib/trace.c
+++ b/lib/trace.c
@@ -56,6 +56,49 @@
return offset / FUNC_SITE_SIZE;
}
+#ifdef CONFIG_EFI_LOADER
+
+/**
+ * trace_gd - the value of the gd register
+ */
+static volatile void *trace_gd;
+
+/**
+ * trace_save_gd() - save the value of the gd register
+ */
+static void __attribute__((no_instrument_function)) trace_save_gd(void)
+{
+ trace_gd = gd;
+}
+
+/**
+ * trace_swap_gd() - swap between U-Boot and application gd register value
+ *
+ * An UEFI application may change the value of the register that gd lives in.
+ * But some of our functions like get_ticks() access this register. So we
+ * have to set the gd register to the U-Boot value when entering a trace
+ * point and set it back to the application value when exiting the trace point.
+ */
+static void __attribute__((no_instrument_function)) trace_swap_gd(void)
+{
+ volatile void *temp_gd = trace_gd;
+
+ trace_gd = gd;
+ gd = temp_gd;
+}
+
+#else
+
+static void __attribute__((no_instrument_function)) trace_save_gd(void)
+{
+}
+
+static void __attribute__((no_instrument_function)) trace_swap_gd(void)
+{
+}
+
+#endif
+
static void __attribute__((no_instrument_function)) add_ftrace(void *func_ptr,
void *caller, ulong flags)
{
@@ -100,6 +143,7 @@
if (trace_enabled) {
int func;
+ trace_swap_gd();
add_ftrace(func_ptr, caller, FUNCF_ENTRY);
func = func_ptr_to_num(func_ptr);
if (func < hdr->func_count) {
@@ -111,6 +155,7 @@
hdr->depth++;
if (hdr->depth > hdr->depth_limit)
hdr->max_depth = hdr->depth;
+ trace_swap_gd();
}
}
@@ -126,8 +171,10 @@
void *func_ptr, void *caller)
{
if (trace_enabled) {
+ trace_swap_gd();
add_ftrace(func_ptr, caller, FUNCF_EXIT);
hdr->depth--;
+ trace_swap_gd();
}
}
@@ -143,12 +190,12 @@
* greater than buff_size if we ran out of space.
* @return 0 if ok, -1 if space was exhausted
*/
-int trace_list_functions(void *buff, int buff_size, unsigned int *needed)
+int trace_list_functions(void *buff, size_t buff_size, size_t *needed)
{
struct trace_output_hdr *output_hdr = NULL;
void *end, *ptr = buff;
- int func;
- int upto;
+ size_t func;
+ size_t upto;
end = buff ? buff + buff_size : NULL;
@@ -159,7 +206,7 @@
/* Add information about each function */
for (func = upto = 0; func < hdr->func_count; func++) {
- int calls = hdr->call_accum[func];
+ size_t calls = hdr->call_accum[func];
if (!calls)
continue;
@@ -188,12 +235,12 @@
return 0;
}
-int trace_list_calls(void *buff, int buff_size, unsigned *needed)
+int trace_list_calls(void *buff, size_t buff_size, size_t *needed)
{
struct trace_output_hdr *output_hdr = NULL;
void *end, *ptr = buff;
- int rec, upto;
- int count;
+ size_t rec, upto;
+ size_t count;
end = buff ? buff + buff_size : NULL;
@@ -284,6 +331,8 @@
size_t needed;
int was_disabled = !trace_enabled;
+ trace_save_gd();
+
if (!was_disabled) {
#ifdef CONFIG_TRACE_EARLY
char *end;
@@ -327,7 +376,7 @@
add_textbase();
puts("trace: enabled\n");
- hdr->depth_limit = 15;
+ hdr->depth_limit = CONFIG_TRACE_CALL_DEPTH_LIMIT;
trace_enabled = 1;
trace_inited = 1;
@@ -361,7 +410,7 @@
hdr->ftrace = (struct trace_call *)((char *)hdr + needed);
hdr->ftrace_size = (buff_size - needed) / sizeof(*hdr->ftrace);
add_textbase();
- hdr->depth_limit = 200;
+ hdr->depth_limit = CONFIG_TRACE_EARLY_CALL_DEPTH_LIMIT;
printf("trace: early enable at %08x\n", CONFIG_TRACE_EARLY_ADDR);
trace_enabled = 1;
diff --git a/lib/uuid.c b/lib/uuid.c
index 7d7a274..a48e19c 100644
--- a/lib/uuid.c
+++ b/lib/uuid.c
@@ -4,6 +4,7 @@
*/
#include <common.h>
+#include <env.h>
#include <linux/ctype.h>
#include <errno.h>
#include <common.h>
@@ -240,25 +241,25 @@
#if defined(CONFIG_RANDOM_UUID) || defined(CONFIG_CMD_UUID)
void gen_rand_uuid(unsigned char *uuid_bin)
{
- struct uuid uuid;
- unsigned int *ptr = (unsigned int *)&uuid;
+ u32 ptr[4];
+ struct uuid *uuid = (struct uuid *)ptr;
int i;
srand(get_ticks() + rand());
/* Set all fields randomly */
- for (i = 0; i < sizeof(struct uuid) / sizeof(*ptr); i++)
- *(ptr + i) = cpu_to_be32(rand());
+ for (i = 0; i < 4; i++)
+ ptr[i] = rand();
- clrsetbits_be16(&uuid.time_hi_and_version,
+ clrsetbits_be16(&uuid->time_hi_and_version,
UUID_VERSION_MASK,
UUID_VERSION << UUID_VERSION_SHIFT);
- clrsetbits_8(&uuid.clock_seq_hi_and_reserved,
+ clrsetbits_8(&uuid->clock_seq_hi_and_reserved,
UUID_VARIANT_MASK,
UUID_VARIANT << UUID_VARIANT_SHIFT);
- memcpy(uuid_bin, &uuid, sizeof(struct uuid));
+ memcpy(uuid_bin, uuid, 16);
}
/*
diff --git a/net/Makefile b/net/Makefile
index ce36362..2a700c8 100644
--- a/net/Makefile
+++ b/net/Makefile
@@ -15,11 +15,14 @@
else
obj-$(CONFIG_NET) += eth_legacy.o
endif
+obj-$(CONFIG_DM_MDIO) += mdio-uclass.o
+obj-$(CONFIG_DM_MDIO_MUX) += mdio-mux-uclass.o
obj-$(CONFIG_NET) += eth_common.o
obj-$(CONFIG_CMD_LINK_LOCAL) += link_local.o
obj-$(CONFIG_NET) += net.o
obj-$(CONFIG_CMD_NFS) += nfs.o
obj-$(CONFIG_CMD_PING) += ping.o
+obj-$(CONFIG_CMD_PCAP) += pcap.o
obj-$(CONFIG_CMD_RARP) += rarp.o
obj-$(CONFIG_CMD_SNTP) += sntp.o
obj-$(CONFIG_CMD_TFTPBOOT) += tftp.o
diff --git a/net/bootp.c b/net/bootp.c
index 9a2b512..5054891 100644
--- a/net/bootp.c
+++ b/net/bootp.c
@@ -10,6 +10,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <efi_loader.h>
#include <net.h>
#include <net/tftp.h>
diff --git a/net/dns.c b/net/dns.c
index eee8a02..67d761d 100644
--- a/net/dns.c
+++ b/net/dns.c
@@ -24,6 +24,7 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <net.h>
#include <asm/unaligned.h>
diff --git a/net/eth-uclass.c b/net/eth-uclass.c
index 031d558..3bd98b0 100644
--- a/net/eth-uclass.c
+++ b/net/eth-uclass.c
@@ -7,10 +7,11 @@
#include <common.h>
#include <dm.h>
-#include <environment.h>
+#include <env.h>
#include <net.h>
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
+#include <net/pcap.h>
#include "eth_internal.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -344,6 +345,10 @@
/* We cannot completely return the error at present */
debug("%s: send() returned error %d\n", __func__, ret);
}
+#if defined(CONFIG_CMD_PCAP)
+ if (ret >= 0)
+ pcap_post(packet, length, true);
+#endif
return ret;
}
diff --git a/net/eth_common.c b/net/eth_common.c
index 63f9379..ed26b1b 100644
--- a/net/eth_common.c
+++ b/net/eth_common.c
@@ -7,7 +7,7 @@
#include <common.h>
#include <dm.h>
-#include <environment.h>
+#include <env.h>
#include <miiphy.h>
#include <net.h>
#include "eth_internal.h"
@@ -110,7 +110,7 @@
static int env_changed_id;
int env_id;
- env_id = get_env_id();
+ env_id = env_get_id();
if ((act == NULL) || (env_changed_id != env_id)) {
act = env_get("ethact");
env_changed_id = env_id;
diff --git a/net/eth_legacy.c b/net/eth_legacy.c
index e250a43..41f5263 100644
--- a/net/eth_legacy.c
+++ b/net/eth_legacy.c
@@ -7,10 +7,11 @@
#include <common.h>
#include <command.h>
-#include <environment.h>
+#include <env.h>
#include <net.h>
#include <phy.h>
#include <linux/errno.h>
+#include <net/pcap.h>
#include "eth_internal.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -352,10 +353,17 @@
int eth_send(void *packet, int length)
{
+ int ret;
+
if (!eth_current)
return -ENODEV;
- return eth_current->send(eth_current, packet, length);
+ ret = eth_current->send(eth_current, packet, length);
+#if defined(CONFIG_CMD_PCAP)
+ if (ret >= 0)
+ pcap_post(packet, lengeth, true);
+#endif
+ return ret;
}
int eth_rx(void)
diff --git a/net/link_local.c b/net/link_local.c
index 31cdef4..dd9fcad 100644
--- a/net/link_local.c
+++ b/net/link_local.c
@@ -12,6 +12,7 @@
*/
#include <common.h>
+#include <env.h>
#include <net.h>
#include "arp.h"
#include "net_rand.h"
diff --git a/net/mdio-mux-uclass.c b/net/mdio-mux-uclass.c
new file mode 100644
index 0000000..e425207
--- /dev/null
+++ b/net/mdio-mux-uclass.c
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019
+ * Alex Marginean, NXP
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <miiphy.h>
+#include <dm/device-internal.h>
+#include <dm/uclass-internal.h>
+#include <dm/lists.h>
+
+#define MDIO_MUX_CHILD_DRV_NAME "mdio-mux-bus-drv"
+
+/**
+ * struct mdio_mux_perdev_priv - Per-device class data for MDIO MUX DM
+ *
+ * @parent_mdio: Parent DM MDIO device, this is called for actual MDIO I/O after
+ * setting up the mux. Typically this is a real MDIO device,
+ * unless there are cascaded muxes.
+ * @selected: Current child bus selection. Defaults to -1
+ */
+struct mdio_mux_perdev_priv {
+ struct udevice *mdio_parent;
+ int selected;
+};
+
+/*
+ * This source file uses three types of devices, as follows:
+ * - mux is the hardware MDIO MUX which selects between the existing child MDIO
+ * buses, this is the device relevant for MDIO MUX class of drivers.
+ * - ch is a child MDIO bus, this is just a representation of a mux selection,
+ * not a real piece of hardware.
+ * - mdio_parent is the actual MDIO bus called to perform reads/writes after
+ * the MUX is configured. Typically this is a real MDIO device, unless there
+ * are cascaded muxes.
+ */
+
+/**
+ * struct mdio_mux_ch_data - Per-device data for child MDIOs
+ *
+ * @sel: Selection value used by the MDIO MUX to access this child MDIO bus
+ */
+struct mdio_mux_ch_data {
+ int sel;
+};
+
+static struct udevice *mmux_get_parent_mdio(struct udevice *mux)
+{
+ struct mdio_mux_perdev_priv *pdata = dev_get_uclass_priv(mux);
+
+ return pdata->mdio_parent;
+}
+
+static struct mdio_ops *mmux_get_mdio_parent_ops(struct udevice *mux)
+{
+ return mdio_get_ops(mmux_get_parent_mdio(mux));
+}
+
+/* call driver select function before performing MDIO r/w */
+static int mmux_change_sel(struct udevice *ch, bool sel)
+{
+ struct udevice *mux = ch->parent;
+ struct mdio_mux_perdev_priv *priv = dev_get_uclass_priv(mux);
+ struct mdio_mux_ops *ops = mdio_mux_get_ops(mux);
+ struct mdio_mux_ch_data *ch_data = dev_get_parent_platdata(ch);
+ int err = 0;
+
+ if (sel) {
+ err = ops->select(mux, priv->selected, ch_data->sel);
+ if (err)
+ return err;
+
+ priv->selected = ch_data->sel;
+ } else {
+ if (ops->deselect) {
+ ops->deselect(mux, ch_data->sel);
+ priv->selected = MDIO_MUX_SELECT_NONE;
+ }
+ }
+
+ return 0;
+}
+
+/* Read wrapper, sets up the mux before issuing a read on parent MDIO bus */
+static int mmux_read(struct udevice *ch, int addr, int devad,
+ int reg)
+{
+ struct udevice *mux = ch->parent;
+ struct udevice *parent_mdio = mmux_get_parent_mdio(mux);
+ struct mdio_ops *parent_ops = mmux_get_mdio_parent_ops(mux);
+ int err;
+
+ err = mmux_change_sel(ch, true);
+ if (err)
+ return err;
+
+ err = parent_ops->read(parent_mdio, addr, devad, reg);
+ mmux_change_sel(ch, false);
+
+ return err;
+}
+
+/* Write wrapper, sets up the mux before issuing a write on parent MDIO bus */
+static int mmux_write(struct udevice *ch, int addr, int devad,
+ int reg, u16 val)
+{
+ struct udevice *mux = ch->parent;
+ struct udevice *parent_mdio = mmux_get_parent_mdio(mux);
+ struct mdio_ops *parent_ops = mmux_get_mdio_parent_ops(mux);
+ int err;
+
+ err = mmux_change_sel(ch, true);
+ if (err)
+ return err;
+
+ err = parent_ops->write(parent_mdio, addr, devad, reg, val);
+ mmux_change_sel(ch, false);
+
+ return err;
+}
+
+/* Reset wrapper, sets up the mux before issuing a reset on parent MDIO bus */
+static int mmux_reset(struct udevice *ch)
+{
+ struct udevice *mux = ch->parent;
+ struct udevice *parent_mdio = mmux_get_parent_mdio(mux);
+ struct mdio_ops *parent_ops = mmux_get_mdio_parent_ops(mux);
+ int err;
+
+ /* reset is optional, if it's not implemented just exit */
+ if (!parent_ops->reset)
+ return 0;
+
+ err = mmux_change_sel(ch, true);
+ if (err)
+ return err;
+
+ err = parent_ops->reset(parent_mdio);
+ mmux_change_sel(ch, false);
+
+ return err;
+}
+
+/* Picks up the mux selection value for each child */
+static int dm_mdio_mux_child_post_bind(struct udevice *ch)
+{
+ struct mdio_mux_ch_data *ch_data = dev_get_parent_platdata(ch);
+
+ ch_data->sel = dev_read_u32_default(ch, "reg", MDIO_MUX_SELECT_NONE);
+
+ if (ch_data->sel == MDIO_MUX_SELECT_NONE)
+ return -EINVAL;
+
+ return 0;
+}
+
+/* Explicitly bind child MDIOs after binding the mux */
+static int dm_mdio_mux_post_bind(struct udevice *mux)
+{
+ ofnode ch_node;
+ int err, first_err = 0;
+
+ if (!ofnode_valid(mux->node)) {
+ debug("%s: no mux node found, no child MDIO busses set up\n",
+ __func__);
+ return 0;
+ }
+
+ /*
+ * we're going by Linux bindings so the child nodes do not have
+ * compatible strings. We're going through them here and binding to
+ * them.
+ */
+ dev_for_each_subnode(ch_node, mux) {
+ struct udevice *ch_dev;
+ const char *ch_name;
+
+ ch_name = ofnode_get_name(ch_node);
+
+ err = device_bind_driver_to_node(mux, MDIO_MUX_CHILD_DRV_NAME,
+ ch_name, ch_node, &ch_dev);
+ /* try to bind all, but keep 1st error */
+ if (err && !first_err)
+ first_err = err;
+ }
+
+ return first_err;
+}
+
+/* Get a reference to the parent MDIO bus, it should be bound by now */
+static int dm_mdio_mux_post_probe(struct udevice *mux)
+{
+ struct mdio_mux_perdev_priv *priv = dev_get_uclass_priv(mux);
+ int err;
+
+ priv->selected = MDIO_MUX_SELECT_NONE;
+
+ /* pick up mdio parent from device tree */
+ err = uclass_get_device_by_phandle(UCLASS_MDIO, mux, "mdio-parent-bus",
+ &priv->mdio_parent);
+ if (err) {
+ debug("%s: didn't find mdio-parent-bus\n", __func__);
+ return err;
+ }
+
+ return 0;
+}
+
+const struct mdio_ops mmux_child_mdio_ops = {
+ .read = mmux_read,
+ .write = mmux_write,
+ .reset = mmux_reset,
+};
+
+/* MDIO class driver used for MUX child MDIO buses */
+U_BOOT_DRIVER(mdio_mux_child) = {
+ .name = MDIO_MUX_CHILD_DRV_NAME,
+ .id = UCLASS_MDIO,
+ .ops = &mmux_child_mdio_ops,
+};
+
+UCLASS_DRIVER(mdio_mux) = {
+ .id = UCLASS_MDIO_MUX,
+ .name = "mdio-mux",
+ .child_post_bind = dm_mdio_mux_child_post_bind,
+ .post_bind = dm_mdio_mux_post_bind,
+ .post_probe = dm_mdio_mux_post_probe,
+ .per_device_auto_alloc_size = sizeof(struct mdio_mux_perdev_priv),
+ .per_child_platdata_auto_alloc_size = sizeof(struct mdio_mux_ch_data),
+};
diff --git a/net/mdio-uclass.c b/net/mdio-uclass.c
new file mode 100644
index 0000000..6f922e8
--- /dev/null
+++ b/net/mdio-uclass.c
@@ -0,0 +1,126 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019
+ * Alex Marginean, NXP
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <miiphy.h>
+#include <dm/device-internal.h>
+#include <dm/uclass-internal.h>
+
+void dm_mdio_probe_devices(void)
+{
+ struct udevice *it;
+ struct uclass *uc;
+
+ uclass_get(UCLASS_MDIO, &uc);
+ uclass_foreach_dev(it, uc) {
+ device_probe(it);
+ }
+}
+
+static int dm_mdio_post_bind(struct udevice *dev)
+{
+ const char *dt_name;
+
+ /* set a custom name for the MDIO device, if present in DT */
+ if (ofnode_valid(dev->node)) {
+ dt_name = ofnode_read_string(dev->node, "device-name");
+ if (dt_name) {
+ debug("renaming dev %s to %s\n", dev->name, dt_name);
+ device_set_name(dev, dt_name);
+ }
+ }
+
+ /*
+ * MDIO command doesn't like spaces in names, don't allow them to keep
+ * it happy
+ */
+ if (strchr(dev->name, ' ')) {
+ debug("\nError: MDIO device name \"%s\" has a space!\n",
+ dev->name);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/*
+ * Following read/write/reset functions are registered with legacy MII code.
+ * These are called for PHY operations by upper layers and we further call the
+ * DM MDIO driver functions.
+ */
+static int mdio_read(struct mii_dev *mii_bus, int addr, int devad, int reg)
+{
+ struct udevice *dev = mii_bus->priv;
+
+ return mdio_get_ops(dev)->read(dev, addr, devad, reg);
+}
+
+static int mdio_write(struct mii_dev *mii_bus, int addr, int devad, int reg,
+ u16 val)
+{
+ struct udevice *dev = mii_bus->priv;
+
+ return mdio_get_ops(dev)->write(dev, addr, devad, reg, val);
+}
+
+static int mdio_reset(struct mii_dev *mii_bus)
+{
+ struct udevice *dev = mii_bus->priv;
+
+ if (mdio_get_ops(dev)->reset)
+ return mdio_get_ops(dev)->reset(dev);
+ else
+ return 0;
+}
+
+static int dm_mdio_post_probe(struct udevice *dev)
+{
+ struct mdio_perdev_priv *pdata = dev_get_uclass_priv(dev);
+
+ pdata->mii_bus = mdio_alloc();
+ pdata->mii_bus->read = mdio_read;
+ pdata->mii_bus->write = mdio_write;
+ pdata->mii_bus->reset = mdio_reset;
+ pdata->mii_bus->priv = dev;
+ strncpy(pdata->mii_bus->name, dev->name, MDIO_NAME_LEN - 1);
+
+ return mdio_register(pdata->mii_bus);
+}
+
+static int dm_mdio_pre_remove(struct udevice *dev)
+{
+ struct mdio_perdev_priv *pdata = dev_get_uclass_priv(dev);
+ struct mdio_ops *ops = mdio_get_ops(dev);
+
+ if (ops->reset)
+ ops->reset(dev);
+ mdio_unregister(pdata->mii_bus);
+ mdio_free(pdata->mii_bus);
+
+ return 0;
+}
+
+struct phy_device *dm_mdio_phy_connect(struct udevice *dev, int addr,
+ struct udevice *ethdev,
+ phy_interface_t interface)
+{
+ struct mdio_perdev_priv *pdata = dev_get_uclass_priv(dev);
+
+ if (device_probe(dev))
+ return 0;
+
+ return phy_connect(pdata->mii_bus, addr, ethdev, interface);
+}
+
+UCLASS_DRIVER(mdio) = {
+ .id = UCLASS_MDIO,
+ .name = "mdio",
+ .post_bind = dm_mdio_post_bind,
+ .post_probe = dm_mdio_post_probe,
+ .pre_remove = dm_mdio_pre_remove,
+ .per_device_auto_alloc_size = sizeof(struct mdio_perdev_priv),
+};
diff --git a/net/net.c b/net/net.c
index 58b0417..ded86e7 100644
--- a/net/net.c
+++ b/net/net.c
@@ -90,11 +90,15 @@
#include <common.h>
#include <command.h>
#include <console.h>
-#include <environment.h>
+#include <env.h>
+#include <env_internal.h>
#include <errno.h>
#include <net.h>
#include <net/fastboot.h>
#include <net/tftp.h>
+#if defined(CONFIG_CMD_PCAP)
+#include <net/pcap.h>
+#endif
#if defined(CONFIG_LED_STATUS)
#include <miiphy.h>
#include <status_led.h>
@@ -671,6 +675,11 @@
net_set_icmp_handler(NULL);
#endif
net_set_state(prev_net_state);
+
+#if defined(CONFIG_CMD_PCAP)
+ if (pcap_active())
+ pcap_print_status();
+#endif
return ret;
}
@@ -1083,6 +1092,9 @@
debug_cond(DEBUG_NET_PKT, "packet received\n");
+#if defined(CONFIG_CMD_PCAP)
+ pcap_post(in_packet, len, false);
+#endif
net_rx_packet = in_packet;
net_rx_packet_len = len;
et = (struct ethernet_hdr *)in_packet;
@@ -1252,6 +1264,9 @@
return;
}
+ if (ntohs(ip->udp_len) < UDP_HDR_SIZE || ntohs(ip->udp_len) > ntohs(ip->ip_len))
+ return;
+
debug_cond(DEBUG_DEV_PKT,
"received UDP (to=%pI4, from=%pI4, len=%d)\n",
&dst_ip, &src_ip, len);
@@ -1613,3 +1628,15 @@
{
return string_to_vlan(env_get(var));
}
+
+void eth_parse_enetaddr(const char *addr, uint8_t *enetaddr)
+{
+ char *end;
+ int i;
+
+ for (i = 0; i < 6; ++i) {
+ enetaddr[i] = addr ? simple_strtoul(addr, &end, 16) : 0;
+ if (addr)
+ addr = (*end) ? end + 1 : end;
+ }
+}
diff --git a/net/nfs.c b/net/nfs.c
index d6a7f8e..aca0ca5 100644
--- a/net/nfs.c
+++ b/net/nfs.c
@@ -196,10 +196,10 @@
rpc_pkt.u.call.vers = htonl(2); /* portmapper is version 2 */
}
rpc_pkt.u.call.proc = htonl(rpc_proc);
- p = (uint32_t *)&(rpc_pkt.u.call.data);
+ p = rpc_pkt.u.call.data;
if (datalen)
- memcpy((char *)p, (char *)data, datalen*sizeof(uint32_t));
+ memcpy(p, data, datalen * sizeof(uint32_t));
pktlen = (char *)p + datalen * sizeof(uint32_t) - (char *)&rpc_pkt;
@@ -566,11 +566,15 @@
}
if (supported_nfs_versions & NFSV2_FLAG) {
+ if (((uchar *)&(rpc_pkt.u.reply.data[0]) - (uchar *)(&rpc_pkt) + NFS_FHSIZE) > len)
+ return -NFS_RPC_DROP;
memcpy(filefh, rpc_pkt.u.reply.data + 1, NFS_FHSIZE);
} else { /* NFSV3_FLAG */
filefh3_length = ntohl(rpc_pkt.u.reply.data[1]);
if (filefh3_length > NFS3_FHSIZE)
filefh3_length = NFS3_FHSIZE;
+ if (((uchar *)&(rpc_pkt.u.reply.data[0]) - (uchar *)(&rpc_pkt) + filefh3_length) > len)
+ return -NFS_RPC_DROP;
memcpy(filefh, rpc_pkt.u.reply.data + 2, filefh3_length);
}
@@ -579,7 +583,7 @@
static int nfs3_get_attributes_offset(uint32_t *data)
{
- if (ntohl(data[1]) != 0) {
+ if (data[1]) {
/* 'attributes_follow' flag is TRUE,
* so we have attributes on 21 dwords */
/* Skip unused values :
@@ -634,6 +638,9 @@
/* new path length */
rlen = ntohl(rpc_pkt.u.reply.data[1 + nfsv3_data_offset]);
+ if (((uchar *)&(rpc_pkt.u.reply.data[0]) - (uchar *)(&rpc_pkt) + rlen) > len)
+ return -NFS_RPC_DROP;
+
if (*((char *)&(rpc_pkt.u.reply.data[2 + nfsv3_data_offset])) != '/') {
int pathlen;
@@ -701,6 +708,9 @@
&(rpc_pkt.u.reply.data[4 + nfsv3_data_offset]);
}
+ if (((uchar *)&(rpc_pkt.u.reply.data[0]) - (uchar *)(&rpc_pkt) + rlen) > len)
+ return -9999;
+
if (store_block(data_ptr, nfs_offset, rlen))
return -9999;
@@ -732,6 +742,9 @@
debug("%s\n", __func__);
+ if (len > sizeof(struct rpc_t))
+ return;
+
if (dest != nfs_our_port)
return;
diff --git a/net/nfs.h b/net/nfs.h
index a377c90..68ada0e 100644
--- a/net/nfs.h
+++ b/net/nfs.h
@@ -78,7 +78,7 @@
NFS_MAX_ATTRS];
} reply;
} u;
-} __attribute__((packed));
+};
void nfs_start(void); /* Begin NFS */
diff --git a/net/pcap.c b/net/pcap.c
new file mode 100644
index 0000000..4036d8a
--- /dev/null
+++ b/net/pcap.c
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Ramon Fried <rfried.dev@gmail.com>
+ */
+
+#include <common.h>
+#include <net.h>
+#include <net/pcap.h>
+#include <time.h>
+#include <asm/io.h>
+
+#define LINKTYPE_ETHERNET 1
+
+static bool initialized;
+static bool running;
+static bool buffer_full;
+static void *buf;
+static unsigned int max_size;
+static unsigned int pos;
+
+static unsigned long incoming_count;
+static unsigned long outgoing_count;
+
+struct pcap_header {
+ u32 magic;
+ u16 version_major;
+ u16 version_minor;
+ s32 thiszone;
+ u32 sigfigs;
+ u32 snaplen;
+ u32 network;
+};
+
+struct pcap_packet_header {
+ u32 ts_sec;
+ u32 ts_usec;
+ u32 incl_len;
+ u32 orig_len;
+};
+
+static struct pcap_header file_header = {
+ .magic = 0xa1b2c3d4,
+ .version_major = 2,
+ .version_minor = 4,
+ .snaplen = 65535,
+ .network = LINKTYPE_ETHERNET,
+};
+
+int pcap_init(phys_addr_t paddr, unsigned long size)
+{
+ buf = map_physmem(paddr, size, 0);
+ if (!buf) {
+ printf("Failed mapping PCAP memory\n");
+ return -ENOMEM;
+ }
+
+ printf("PCAP capture initialized: addr: 0x%lx max length: %lu\n",
+ (unsigned long)buf, size);
+
+ memcpy(buf, &file_header, sizeof(file_header));
+ pos = sizeof(file_header);
+ max_size = size;
+ initialized = true;
+ running = false;
+ buffer_full = false;
+ incoming_count = 0;
+ outgoing_count = 0;
+ return 0;
+}
+
+int pcap_start_stop(bool start)
+{
+ if (!initialized) {
+ printf("error: pcap was not initialized\n");
+ return -ENODEV;
+ }
+
+ running = start;
+
+ return 0;
+}
+
+int pcap_clear(void)
+{
+ if (!initialized) {
+ printf("error: pcap was not initialized\n");
+ return -ENODEV;
+ }
+
+ pos = sizeof(file_header);
+ incoming_count = 0;
+ outgoing_count = 0;
+ buffer_full = false;
+
+ printf("pcap capture cleared\n");
+ return 0;
+}
+
+int pcap_post(const void *packet, size_t len, bool outgoing)
+{
+ struct pcap_packet_header header;
+ u64 cur_time = timer_get_us();
+
+ if (!initialized || !running || !buf)
+ return -ENODEV;
+
+ if (buffer_full)
+ return -ENOMEM;
+
+ if ((pos + len + sizeof(header)) >= max_size) {
+ buffer_full = true;
+ printf("\n!!! Buffer is full, consider increasing buffer size !!!\n");
+ return -ENOMEM;
+ }
+
+ header.ts_sec = cur_time / 1000000;
+ header.ts_usec = cur_time % 1000000;
+ header.incl_len = len;
+ header.orig_len = len;
+
+ memcpy(buf + pos, &header, sizeof(header));
+ pos += sizeof(header);
+ memcpy(buf + pos, packet, len);
+ pos += len;
+
+ if (outgoing)
+ outgoing_count++;
+ else
+ incoming_count++;
+
+ env_set_hex("pcapsize", pos);
+
+ return 0;
+}
+
+int pcap_print_status(void)
+{
+ if (!initialized) {
+ printf("pcap was not initialized\n");
+ return -ENODEV;
+ }
+ printf("PCAP status:\n");
+ printf("\tInitialized addr: 0x%lx\tmax length: %u\n",
+ (unsigned long)buf, max_size);
+ printf("\tStatus: %s.\t file size: %u\n", running ? "Active" : "Idle",
+ pos);
+ printf("\tIncoming packets: %lu Outgoing packets: %lu\n",
+ incoming_count, outgoing_count);
+
+ return 0;
+}
+
+bool pcap_active(void)
+{
+ return running;
+}
diff --git a/net/tftp.c b/net/tftp.c
index 34488b7..5a69bca 100644
--- a/net/tftp.c
+++ b/net/tftp.c
@@ -9,6 +9,7 @@
#include <common.h>
#include <command.h>
#include <efi_loader.h>
+#include <env.h>
#include <mapmem.h>
#include <net.h>
#include <net/tftp.h>
diff --git a/net/wol.c b/net/wol.c
index 946bd91..0a62566 100644
--- a/net/wol.c
+++ b/net/wol.c
@@ -5,8 +5,8 @@
#include <common.h>
#include <command.h>
+#include <env.h>
#include <net.h>
-#include <environment.h>
#include "wol.h"
static ulong wol_timeout = WOL_DEFAULT_TIMEOUT;
diff --git a/post/post.c b/post/post.c
index ebb6205..fb751d9 100644
--- a/post/post.c
+++ b/post/post.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
+#include <env.h>
#include <stdio_dev.h>
#include <watchdog.h>
#include <div64.h>
diff --git a/prebuilt-intermediates/env.h b/prebuilt-intermediates/env.h
new file mode 120000
index 0000000..6be9b5a
--- /dev/null
+++ b/prebuilt-intermediates/env.h
@@ -0,0 +1 @@
+../include/env.h
\ No newline at end of file
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index de67677..ef116e0 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -383,7 +383,7 @@
EFI_LDS_PATH = $(srctree)/arch/$(ARCH)/lib/$(EFI_LDS)
-$(obj)/efi_crt0.o: $(srctree)/arch/$(ARCH)/lib/$(EFI_CRT0:.o=.S)
+$(obj)/efi_crt0.o: $(srctree)/arch/$(ARCH)/lib/$(EFI_CRT0:.o=.S) FORCE
$(call if_changed_dep,as_o_S)
$(obj)/efi_reloc.o: $(srctree)/arch/$(ARCH)/lib/$(EFI_RELOC:.o=.c) $(recordmcount_source) FORCE
@@ -395,11 +395,22 @@
# ACPI
# ---------------------------------------------------------------------------
+#
+# This first sends the file (typically dsdt.asl) through the preprocessor
+# resolve includes and any CONFIG options used. This produces dsdt.asl.tmp
+# which is pure ASL code. The Intel ASL (ACPI (Advanced Configuration and Power
+# Interface) Source Language compiler (iasl) then converts this ASL code into a
+# C file containing the hex data to build into U-Boot. This file is called
+# dsdt.hex (despite us setting the prefix to .../dsdt.asl.tmp) so must be
+# renamed to dsdt.c for consumption by the build system.
+ASL_TMP = $(patsubst %.c,%.asl.tmp,$@)
+
quiet_cmd_acpi_c_asl= ASL $<
cmd_acpi_c_asl= \
- $(CPP) -x assembler-with-cpp -D__ASSEMBLY__ -P $(UBOOTINCLUDE) -o $<.tmp $<; \
- iasl -p $< -tc $<.tmp $(if $(KBUILD_VERBOSE:1=), >/dev/null) && \
- mv $(patsubst %.asl,%.hex,$<) $@
+ $(CPP) -x assembler-with-cpp -D__ASSEMBLY__ -P $(UBOOTINCLUDE) \
+ -o $(ASL_TMP) $< && \
+ iasl -p $@ -tc $(ASL_TMP) $(if $(KBUILD_VERBOSE:1=), >/dev/null) && \
+ mv $(patsubst %.c,%.hex,$@) $@
$(obj)/dsdt.c: $(src)/dsdt.asl
$(call cmd,acpi_c_asl)
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index d252045..5a007d3 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -35,7 +35,6 @@
CONFIG_APER_SIZE
CONFIG_APUS_FAST_EXCEPT
CONFIG_ARCH_ADPAG101P
-CONFIG_ARCH_CPU_INIT
CONFIG_ARCH_HAS_ILOG2_U32
CONFIG_ARCH_HAS_ILOG2_U64
CONFIG_ARCH_KIRKWOOD
@@ -61,7 +60,6 @@
CONFIG_ARM_GIC_BASE_ADDRESS
CONFIG_ARM_PL180_MMCI_BASE
CONFIG_ARM_PL180_MMCI_CLOCK_FREQ
-CONFIG_ARM_THUMB
CONFIG_ARP_TIMEOUT
CONFIG_ASTRO_COFDMDUOS2
CONFIG_ASTRO_TWIN7S2
@@ -129,15 +127,7 @@
CONFIG_BOOGER
CONFIG_BOOTBLOCK
CONFIG_BOOTFILE
-CONFIG_BOOTMAPSZ
CONFIG_BOOTMODE
-CONFIG_BOOTM_LINUX
-CONFIG_BOOTM_NETBSD
-CONFIG_BOOTM_OPENRTOS
-CONFIG_BOOTM_OSE
-CONFIG_BOOTM_PLAN9
-CONFIG_BOOTM_RTEMS
-CONFIG_BOOTM_VXWORKS
CONFIG_BOOTP_
CONFIG_BOOTP_BOOTFILE
CONFIG_BOOTP_BOOTFILESIZE
@@ -281,7 +271,6 @@
CONFIG_CTL_TBE
CONFIG_CUSTOMER_BOARD_SUPPORT
CONFIG_D2NET_V2
-CONFIG_DA850_AM18X_EVM
CONFIG_DA850_EVM_MAX_CPU_CLK
CONFIG_DBGU
CONFIG_DB_784MP_GP
@@ -363,8 +352,6 @@
CONFIG_DRIVER_EP93XX_MAC
CONFIG_DRIVER_NE2000
CONFIG_DRIVER_NE2000_BASE
-CONFIG_DRIVER_NE2000_CCR
-CONFIG_DRIVER_NE2000_VAL
CONFIG_DRIVER_SMC911X_BASE
CONFIG_DRIVER_TI_EMAC_USE_RMII
CONFIG_DSP_CLUSTER_START
@@ -473,7 +460,6 @@
CONFIG_ENV_TOTAL_SIZE
CONFIG_ENV_UBIFS_OPTION
CONFIG_ENV_UBI_MTD
-CONFIG_ENV_UBI_VOLUME_REDUND
CONFIG_ENV_VERSION
CONFIG_EP9302
CONFIG_EP9307
@@ -596,7 +582,6 @@
CONFIG_FSL_DSPI1
CONFIG_FSL_ESDHC_ADAPTER_IDENT
CONFIG_FSL_ESDHC_PIN_MUX
-CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
CONFIG_FSL_FIXED_MMC_LOCATION
CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
CONFIG_FSL_I2C_CUSTOM_DFSR
@@ -627,7 +612,6 @@
CONFIG_FSL_SPI_INTERFACE
CONFIG_FSL_TBCLK_EXTRA_DIV
CONFIG_FSL_TRUST_ARCH_v1
-CONFIG_FSL_USDHC
CONFIG_FSL_VIA
CONFIG_FSMC_NAND_BASE
CONFIG_FSMTDBLK
@@ -949,16 +933,11 @@
CONFIG_KIRQ_EN
CONFIG_KM8321
CONFIG_KMCOGE4
-CONFIG_KMLION1
CONFIG_KMP204X
CONFIG_KMTEGR1
-CONFIG_KMVECT1
CONFIG_KM_BOARD_EXTRA_ENV
CONFIG_KM_BOARD_NAME
CONFIG_KM_COGE5UN
-CONFIG_KM_COMMON_ETH_INIT
-CONFIG_KM_CONSOLE_TTY
-CONFIG_KM_CRAMFS_ADDR
CONFIG_KM_DEF_ARCH
CONFIG_KM_DEF_BOOT_ARGS_CPU
CONFIG_KM_DEF_ENV
@@ -970,27 +949,14 @@
CONFIG_KM_DEF_ENV_FLASH_BOOT
CONFIG_KM_DEF_NETDEV
CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI
-CONFIG_KM_DISABLE_PCI
CONFIG_KM_DISABLE_PCIE
CONFIG_KM_ECC_MODE
-CONFIG_KM_ENV_IS_IN_SPI_NOR
-CONFIG_KM_FDT_ADDR
-CONFIG_KM_FPGA_CONFIG
-CONFIG_KM_IVM_BUS
-CONFIG_KM_KERNEL_ADDR
CONFIG_KM_KIRKWOOD
CONFIG_KM_KIRKWOOD_128M16
CONFIG_KM_KIRKWOOD_PCI
CONFIG_KM_MGCOGE3UN
-CONFIG_KM_MVEXTSW_ADDR
CONFIG_KM_NEW_ENV
CONFIG_KM_NUSA
-CONFIG_KM_PHRAM
-CONFIG_KM_PIGGY4_88E6061
-CONFIG_KM_PIGGY4_88E6352
-CONFIG_KM_PNVRAM
-CONFIG_KM_PORTL2
-CONFIG_KM_RESERVED_PRAM
CONFIG_KM_ROOTFSSIZE
CONFIG_KM_SUGP1
CONFIG_KM_SUV31
@@ -1143,9 +1109,6 @@
CONFIG_MEM_HOLE_16M
CONFIG_MEM_INIT_VALUE
CONFIG_MEM_REMAP
-CONFIG_MENUKEY
-CONFIG_MENUPROMPT
-CONFIG_MENU_SHOW
CONFIG_MFG_ENV_SETTINGS
CONFIG_MIIM_ADDRESS
CONFIG_MII_DEFAULT_TSEC
@@ -1166,12 +1129,6 @@
CONFIG_MMCROOT
CONFIG_MMC_DEFAULT_DEV
CONFIG_MMC_RPMB_TRACE
-CONFIG_MMC_SPI
-CONFIG_MMC_SPI_BUS
-CONFIG_MMC_SPI_CRC_ON
-CONFIG_MMC_SPI_CS
-CONFIG_MMC_SPI_MODE
-CONFIG_MMC_SPI_SPEED
CONFIG_MMC_SUNXI_SLOT
CONFIG_MMU
CONFIG_MONITOR_IS_IN_RAM
@@ -1243,9 +1200,7 @@
CONFIG_MXS
CONFIG_MXS_AUART
CONFIG_MXS_AUART_BASE
-CONFIG_MXS_GPIO
CONFIG_MXS_OCOTP
-CONFIG_MX_CYCLIC
CONFIG_MY_OPTION
CONFIG_NANDFLASH_SIZE
CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
@@ -1368,9 +1323,6 @@
CONFIG_PCI_SYS_BUS
CONFIG_PCI_SYS_PHYS
CONFIG_PCI_SYS_SIZE
-CONFIG_PCMCIA
-CONFIG_PCMCIA_SLOT_A
-CONFIG_PCMCIA_SLOT_B
CONFIG_PCNET
CONFIG_PCNET_79C973
CONFIG_PCNET_79C975
@@ -1390,7 +1342,6 @@
CONFIG_PHY_MODE_NEED_CHANGE
CONFIG_PHY_RESET
CONFIG_PHY_RESET_DELAY
-CONFIG_PIGGY_MAC_ADRESS_OFFSET
CONFIG_PIXIS_BRDCFG0_SPI
CONFIG_PIXIS_BRDCFG0_USB2
CONFIG_PIXIS_BRDCFG1_AUDCLK_11
@@ -1467,7 +1418,6 @@
CONFIG_PRPMC_PCI_ALIAS
CONFIG_PSRAM_SCFG
CONFIG_PWM
-CONFIG_PWM_IMX
CONFIG_PXA_LCD
CONFIG_PXA_MMC_GENERIC
CONFIG_PXA_PWR_I2C
@@ -1480,10 +1430,6 @@
CONFIG_QSPI
CONFIG_QUOTA
CONFIG_R7780MP
-CONFIG_R8A66597_BASE_ADDR
-CONFIG_R8A66597_ENDIAN
-CONFIG_R8A66597_LDRV
-CONFIG_R8A66597_XTAL
CONFIG_RAMBOOT
CONFIG_RAMBOOTCOMMAND
CONFIG_RAMBOOTCOMMAND_TFTP
@@ -1540,6 +1486,7 @@
CONFIG_ROCKCHIP_CHIP_TAG
CONFIG_ROCKCHIP_MAX_INIT_SIZE
CONFIG_ROCKCHIP_SDHCI_MAX_FREQ
+CONFIG_ROCKCHIP_STIMER_BASE
CONFIG_ROM_STUBS
CONFIG_ROOTFS_OFFSET
CONFIG_ROOTPATH
@@ -1560,7 +1507,6 @@
CONFIG_RTC_MXS
CONFIG_RTC_PCF8563
CONFIG_RTC_PT7C4338
-CONFIG_RTC_RX8025
CONFIG_RUN_FROM_DDR0
CONFIG_RUN_FROM_DDR1
CONFIG_RUN_FROM_IRAM_ONLY
@@ -1630,7 +1576,6 @@
CONFIG_SHEEVA_88SV131
CONFIG_SHEEVA_88SV331xV5
CONFIG_SHOW_ACTIVITY
-CONFIG_SHOW_BOOT_PROGRESS
CONFIG_SH_CMT_CLK_FREQ
CONFIG_SH_DSP
CONFIG_SH_ETHER_ALIGNE_SIZE
@@ -1795,18 +1740,6 @@
CONFIG_SPL_STACK_SIZE
CONFIG_SPL_START_S_PATH
CONFIG_SPL_TARGET
-CONFIG_SPL_UBI
-CONFIG_SPL_UBI_INFO_ADDR
-CONFIG_SPL_UBI_LEB_START
-CONFIG_SPL_UBI_LOAD_ARGS_ID
-CONFIG_SPL_UBI_LOAD_KERNEL_ID
-CONFIG_SPL_UBI_LOAD_MONITOR_ID
-CONFIG_SPL_UBI_MAX_PEBS
-CONFIG_SPL_UBI_MAX_PEB_SIZE
-CONFIG_SPL_UBI_MAX_VOL_LEBS
-CONFIG_SPL_UBI_PEB_OFFSET
-CONFIG_SPL_UBI_VID_OFFSET
-CONFIG_SPL_UBI_VOL_IDS
CONFIG_SPL_UBOOT_KEY_HASH
CONFIG_SRAM_BASE
CONFIG_SRAM_SIZE
@@ -1845,7 +1778,6 @@
CONFIG_STV0991_HZ
CONFIG_STV0991_HZ_CLOCK
CONFIG_ST_SMI
-CONFIG_SUNXI_GPIO
CONFIG_SUNXI_MAX_FB_SIZE
CONFIG_SUVD3
CONFIG_SXNI855T
@@ -3068,9 +3000,6 @@
CONFIG_SYS_ISA_IO_OFFSET
CONFIG_SYS_ISA_IO_STRIDE
CONFIG_SYS_ISA_MEM
-CONFIG_SYS_IVM_EEPROM_ADR
-CONFIG_SYS_IVM_EEPROM_MAX_LEN
-CONFIG_SYS_IVM_EEPROM_PAGE_LEN
CONFIG_SYS_JFFS2_FIRST_BANK
CONFIG_SYS_JFFS2_FIRST_SECTOR
CONFIG_SYS_JFFS2_MEM_NAND
@@ -3079,7 +3008,6 @@
CONFIG_SYS_KMBEC_FPGA_BASE
CONFIG_SYS_KMBEC_FPGA_SIZE
CONFIG_SYS_KWD_CONFIG
-CONFIG_SYS_KW_SPI_MPP
CONFIG_SYS_L2
CONFIG_SYS_L2_PL310
CONFIG_SYS_L2_SIZE
@@ -3087,8 +3015,6 @@
CONFIG_SYS_LATCH_ADDR
CONFIG_SYS_LBAPP1_BASE
CONFIG_SYS_LBAPP1_BASE_PHYS
-CONFIG_SYS_LBAPP1_BR_PRELIM
-CONFIG_SYS_LBAPP1_OR_PRELIM
CONFIG_SYS_LBAPP2_BASE
CONFIG_SYS_LBAPP2_BASE_PHYS
CONFIG_SYS_LBAPP2_BR_PRELIM
@@ -3395,7 +3321,6 @@
CONFIG_SYS_NAND_SIZE
CONFIG_SYS_NAND_SPL_KERNEL_OFFS
CONFIG_SYS_NAND_SPL_SIZE
-CONFIG_SYS_NAND_USE_FLASH_BBT
CONFIG_SYS_NAND_U_BOOT_DST
CONFIG_SYS_NAND_U_BOOT_RELOC
CONFIG_SYS_NAND_U_BOOT_RELOC_SP
@@ -3731,7 +3656,6 @@
CONFIG_SYS_PCI_TBATR4
CONFIG_SYS_PCI_TBATR5
CONFIG_SYS_PCI_VIRT
-CONFIG_SYS_PCMCIA_MEM_SIZE
CONFIG_SYS_PDCNT
CONFIG_SYS_PEHLPAR
CONFIG_SYS_PEPAR
@@ -4001,7 +3925,6 @@
CONFIG_SYS_SPI_MXC_WAIT
CONFIG_SYS_SPI_RTC_DEVID
CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
-CONFIG_SYS_SPI_U_BOOT_OFFS
CONFIG_SYS_SPI_U_BOOT_SIZE
CONFIG_SYS_SPI_WRITE_TOUT
CONFIG_SYS_SPL_ARGS_ADDR
@@ -4153,7 +4076,6 @@
CONFIG_SYS_USE_MPC834XSYS_USB_PHY
CONFIG_SYS_USE_NAND
CONFIG_SYS_USE_NANDFLASH
-CONFIG_SYS_USE_NOR
CONFIG_SYS_USE_NORFLASH
CONFIG_SYS_USR_EXCEP
CONFIG_SYS_U_BOOT_OFFS
@@ -4316,7 +4238,6 @@
CONFIG_USB_ATMEL_CLK_SEL_UPLL
CONFIG_USB_BIN_FIXUP
CONFIG_USB_BOOTING
-CONFIG_USB_CABLE_CHECK
CONFIG_USB_DEVICE
CONFIG_USB_DEV_BASE
CONFIG_USB_DEV_PULLUP_GPIO
diff --git a/scripts/dtc/libfdt/fdt_sw.c b/scripts/dtc/libfdt/fdt_sw.c
index 6d33cc2..d8ef748 100644
--- a/scripts/dtc/libfdt/fdt_sw.c
+++ b/scripts/dtc/libfdt/fdt_sw.c
@@ -114,7 +114,7 @@
FDT_SW_CHECK_HEADER(fdt);
- headsize = fdt_off_dt_struct(fdt);
+ headsize = fdt_off_dt_struct(fdt) + fdt_size_dt_struct(fdt);
tailsize = fdt_size_dt_strings(fdt);
if ((headsize + tailsize) > bufsize)
diff --git a/scripts/fill_scrapyard.py b/scripts/fill_scrapyard.py
deleted file mode 100755
index 55a7f38..0000000
--- a/scripts/fill_scrapyard.py
+++ /dev/null
@@ -1,165 +0,0 @@
-#!/usr/bin/env python2
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
-#
-
-"""
-Fill the "Commit" and "Removed" fields of doc/README.scrapyard
-
-The file doc/README.scrapyard is used to keep track of removed boards.
-
-When we remove support for boards, we are supposed to add entries to
-doc/README.scrapyard leaving "Commit" and "Removed" fields blank.
-
-The "Commit" field is the commit hash in which the board was removed
-and the "Removed" is the date at which the board was removed. Those
-two are known only after the board removal patch was applied, thus they
-need to be filled in later.
-
-This effectively means that the person who removes other boards is
-supposed to fill in the blank fields before adding new entries to
-doc/README.scrapyard.
-
-That is a really tedious task that should be automated.
-This script fills the blank fields of doc/README.scrapyard for you!
-
-Usage:
-
-The "Commit" and "Removed" fields must be "-". The other fields should
-have already been filled in by a former commit.
-
-Run
- scripts/fill_scrapyard.py
-"""
-
-import os
-import subprocess
-import sys
-import tempfile
-
-DOC='doc/README.scrapyard'
-
-def get_last_modify_commit(file, line_num):
- """Get the commit that last modified the given line.
-
- This function runs "git blame" against the given line of the given
- file and returns the commit hash that last modified it.
-
- Arguments:
- file: the file to be git-blame'd.
- line_num: the line number to be git-blame'd. This line number
- starts from 1, not 0.
-
- Returns:
- Commit hash that last modified the line. The number of digits is
- long enough to form a unique commit.
- """
- result = subprocess.check_output(['git', 'blame', '-L',
- '%d,%d' % (line_num, line_num), file])
- commit = result.split()[0]
-
- if commit[0] == '^':
- sys.exit('%s: line %d: ' % (file, line_num) +
- 'this line was modified before the beginning of git history')
-
- if commit == '0' * len(commit):
- sys.exit('%s: line %d: locally modified\n' % (file, line_num) +
- 'Please run this script in a clean repository.')
-
- return commit
-
-def get_committer_date(commit):
- """Get the committer date of the given commit.
-
- This function returns the date when the given commit was applied.
-
- Arguments:
- commit: commit-ish object.
-
- Returns:
- The committer date of the given commit in the form YY-MM-DD.
- """
- committer_date = subprocess.check_output(['git', 'show', '-s',
- '--format=%ci', commit])
- return committer_date.split()[0]
-
-def move_to_topdir():
- """Change directory to the top of the git repository.
-
- Or, exit with an error message if called out of a git repository.
- """
- try:
- toplevel = subprocess.check_output(['git', 'rev-parse',
- '--show-toplevel'])
- except subprocess.CalledProcessError:
- sys.exit('Please run in a git repository.')
-
- # strip '\n'
- toplevel = toplevel.rstrip()
-
- # Change the current working directory to the toplevel of the respository
- # for our easier life.
- os.chdir(toplevel)
-
-class TmpFile:
-
- """Useful class to handle a temporary file.
-
- tempfile.mkstemp() is often used to create a unique temporary file,
- but what is inconvenient is that the caller is responsible for
- deleting the file when done with it.
-
- Even when the caller errors out on the way, the temporary file must
- be deleted somehow. The idea here is that we delete the file in
- the destructor of this class because the destructor is always
- invoked when the instance of the class is freed.
- """
-
- def __init__(self):
- """Constructor - create a temporary file"""
- fd, self.filename = tempfile.mkstemp()
- self.file = os.fdopen(fd, 'w')
-
- def __del__(self):
- """Destructor - delete the temporary file"""
- try:
- os.remove(self.filename)
- except:
- pass
-
-def main():
- move_to_topdir()
-
- line_num = 1
-
- tmpfile = TmpFile()
- for line in open(DOC):
- tmp = line.split(None, 5)
- modified = False
-
- if len(tmp) >= 5:
- # fill "Commit" field
- if tmp[3] == '-':
- tmp[3] = get_last_modify_commit(DOC, line_num)
- modified = True
- # fill "Removed" field
- if tmp[4] == '-':
- tmp[4] = get_committer_date(tmp[3])
- if modified:
- line = tmp[0].ljust(17)
- line += tmp[1].ljust(12)
- line += tmp[2].ljust(15)
- line += tmp[3].ljust(12)
- line += tmp[4].ljust(12)
- if len(tmp) >= 6:
- line += tmp[5]
- line = line.rstrip() + '\n'
-
- tmpfile.file.write(line)
- line_num += 1
-
- os.rename(tmpfile.filename, DOC)
-
-if __name__ == '__main__':
- main()
diff --git a/scripts/kernel-doc b/scripts/kernel-doc
index 3cb6259..516cf1d 100755
--- a/scripts/kernel-doc
+++ b/scripts/kernel-doc
@@ -212,7 +212,7 @@
my $type_constant = '\b``([^\`]+)``\b';
my $type_constant2 = '\%([-_\w]+)';
my $type_func = '(\w+)\(\)';
-my $type_param = '\@(\w*(\.\w+)*(\.\.\.)?)';
+my $type_param = '\@(\w*((\.\w+)|(->\w+))*(\.\.\.)?)';
my $type_fp_param = '\@(\w+)\(\)'; # Special RST handling for func ptr params
my $type_env = '(\$\w+)';
my $type_enum = '\&(enum\s*([_\w]+))';
@@ -1062,7 +1062,7 @@
my $x = shift;
my $file = shift;
- if ($x =~ /(struct|union)\s+(\w+)\s*{(.*)}/) {
+ if ($x =~ /(struct|union)\s+(\w+)\s*\{(.*)\}(\s*(__packed|__aligned|__attribute__\s*\(\([a-z0-9,_\s\(\)]*\)\)))*/) {
my $decl_type = $1;
$declaration_name = $2;
my $members = $3;
@@ -1073,8 +1073,9 @@
# strip comments:
$members =~ s/\/\*.*?\*\///gos;
# strip attributes
- $members =~ s/__attribute__\s*\(\([a-z,_\*\s\(\)]*\)\)//i;
- $members =~ s/__aligned\s*\([^;]*\)//gos;
+ $members =~ s/\s*__attribute__\s*\(\([a-z0-9,_\*\s\(\)]*\)\)//gi;
+ $members =~ s/\s*__aligned\s*\([^;]*\)//gos;
+ $members =~ s/\s*__packed\s*//gos;
$members =~ s/\s*CRYPTO_MINALIGN_ATTR//gos;
# replace DECLARE_BITMAP
$members =~ s/DECLARE_BITMAP\s*\(([^,)]+),\s*([^,)]+)\)/unsigned long $1\[BITS_TO_LONGS($2)\]/gos;
@@ -1148,20 +1149,20 @@
}
}
}
- $members =~ s/(struct|union)([^\{\};]+)\{([^\{\}]*)}([^\{\}\;]*)\;/$newmember/;
+ $members =~ s/(struct|union)([^\{\};]+)\{([^\{\}]*)\}([^\{\}\;]*)\;/$newmember/;
}
# Ignore other nested elements, like enums
- $members =~ s/({[^\{\}]*})//g;
+ $members =~ s/(\{[^\{\}]*\})//g;
create_parameterlist($members, ';', $file, $declaration_name);
check_sections($file, $declaration_name, $decl_type, $sectcheck, $struct_actual);
# Adjust declaration for better display
- $declaration =~ s/([{;])/$1\n/g;
- $declaration =~ s/}\s+;/};/g;
+ $declaration =~ s/([\{;])/$1\n/g;
+ $declaration =~ s/\}\s+;/};/g;
# Better handle inlined enums
- do {} while ($declaration =~ s/(enum\s+{[^}]+),([^\n])/$1,\n$2/);
+ do {} while ($declaration =~ s/(enum\s+\{[^\}]+),([^\n])/$1,\n$2/);
my @def_args = split /\n/, $declaration;
my $level = 1;
@@ -1171,12 +1172,12 @@
$clause =~ s/\s+$//;
$clause =~ s/\s+/ /;
next if (!$clause);
- $level-- if ($clause =~ m/(})/ && $level > 1);
+ $level-- if ($clause =~ m/(\})/ && $level > 1);
if (!($clause =~ m/^\s*#/)) {
$declaration .= "\t" x $level;
}
$declaration .= "\t" . $clause . "\n";
- $level++ if ($clause =~ m/({)/ && !($clause =~m/}/));
+ $level++ if ($clause =~ m/(\{)/ && !($clause =~m/\}/));
}
output_declaration($declaration_name,
'struct',
@@ -1244,7 +1245,7 @@
# strip #define macros inside enums
$x =~ s@#\s*((define|ifdef)\s+|endif)[^;]*;@@gos;
- if ($x =~ /enum\s+(\w+)\s*{(.*)}/) {
+ if ($x =~ /enum\s+(\w+)\s*\{(.*)\}/) {
$declaration_name = $1;
my $members = $2;
my %_members;
@@ -1381,7 +1382,7 @@
} elsif ($arg =~ m/\(.+\)\s*\(/) {
# pointer-to-function
$arg =~ tr/#/,/;
- $arg =~ m/[^\(]+\(\*?\s*([\w\.]*)\s*\)/;
+ $arg =~ m/[^\(]+\([\w\s]*\*?\s*([\w\.]*)\s*\)/;
$param = $1;
$type = $arg;
$type =~ s/([^\(]+\(\*?)\s*$param/$1/;
@@ -1473,7 +1474,7 @@
if (!defined $parameterdescs{$param} && $param !~ /^#/) {
$parameterdescs{$param} = $undescribed;
- if (show_warnings($type, $declaration_name)) {
+ if (show_warnings($type, $declaration_name) && $param !~ /\./) {
print STDERR
"${file}:$.: warning: Function parameter or member '$param' not described in '$declaration_name'\n";
++$warnings;
@@ -1785,7 +1786,7 @@
}
while (1) {
- if ( $x =~ /([^{};]*)([{};])(.*)/ ) {
+ if ( $x =~ /([^\{\};]*)([\{\};])(.*)/ ) {
if( length $prototype ) {
$prototype .= " "
}
@@ -1904,13 +1905,13 @@
++$warnings;
}
- if ($identifier =~ m/^struct/) {
+ if ($identifier =~ m/^struct\b/) {
$decl_type = 'struct';
- } elsif ($identifier =~ m/^union/) {
+ } elsif ($identifier =~ m/^union\b/) {
$decl_type = 'union';
- } elsif ($identifier =~ m/^enum/) {
+ } elsif ($identifier =~ m/^enum\b/) {
$decl_type = 'enum';
- } elsif ($identifier =~ m/^typedef/) {
+ } elsif ($identifier =~ m/^typedef\b/) {
$decl_type = 'typedef';
} else {
$decl_type = 'function';
diff --git a/test/compression.c b/test/compression.c
index 7bc0f73..08fef59 100644
--- a/test/compression.c
+++ b/test/compression.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <bootm.h>
#include <command.h>
+#include <gzip.h>
#include <malloc.h>
#include <mapmem.h>
#include <asm/io.h>
@@ -471,15 +472,15 @@
unc_len = strlen(plain);
compress(uts, (void *)plain, unc_len, compress_buff, compress_size,
&compress_size);
- err = bootm_decomp_image(comp_type, load_addr, image_start,
- IH_TYPE_KERNEL, map_sysmem(load_addr, 0),
- compress_buff, compress_size, unc_len,
- &load_end);
+ err = image_decomp(comp_type, load_addr, image_start,
+ IH_TYPE_KERNEL, map_sysmem(load_addr, 0),
+ compress_buff, compress_size, unc_len,
+ &load_end);
ut_assertok(err);
- err = bootm_decomp_image(comp_type, load_addr, image_start,
- IH_TYPE_KERNEL, map_sysmem(load_addr, 0),
- compress_buff, compress_size, unc_len - 1,
- &load_end);
+ err = image_decomp(comp_type, load_addr, image_start,
+ IH_TYPE_KERNEL, map_sysmem(load_addr, 0),
+ compress_buff, compress_size, unc_len - 1,
+ &load_end);
ut_assert(err);
/* We can't detect corruption when not decompressing */
@@ -487,10 +488,10 @@
return 0;
memset(compress_buff + compress_size / 2, '\x49',
compress_size / 2);
- err = bootm_decomp_image(comp_type, load_addr, image_start,
- IH_TYPE_KERNEL, map_sysmem(load_addr, 0),
- compress_buff, compress_size, 0x10000,
- &load_end);
+ err = image_decomp(comp_type, load_addr, image_start,
+ IH_TYPE_KERNEL, map_sysmem(load_addr, 0),
+ compress_buff, compress_size, 0x10000,
+ &load_end);
ut_assert(err);
return 0;
diff --git a/test/dm/Makefile b/test/dm/Makefile
index aeb3aa0..55a7940 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -17,7 +17,7 @@
obj-$(CONFIG_BLK) += blk.o
obj-$(CONFIG_BOARD) += board.o
obj-$(CONFIG_DM_BOOTCOUNT) += bootcount.o
-obj-$(CONFIG_CLK) += clk.o
+obj-$(CONFIG_CLK) += clk.o clk_ccf.o
obj-$(CONFIG_DM_ETH) += eth.o
obj-$(CONFIG_FIRMWARE) += firmware.o
obj-$(CONFIG_DM_GPIO) += gpio.o
@@ -31,6 +31,7 @@
obj-$(CONFIG_OSD) += osd.o
obj-$(CONFIG_DM_VIDEO) += panel.o
obj-$(CONFIG_DM_PCI) += pci.o
+obj-$(CONFIG_PCI_ENDPOINT) += pci_ep.o
obj-$(CONFIG_PCH) += pch.o
obj-$(CONFIG_PHY) += phy.o
obj-$(CONFIG_POWER_DOMAIN) += power-domain.o
@@ -61,4 +62,6 @@
obj-$(CONFIG_TEE) += tee.o
obj-$(CONFIG_VIRTIO_SANDBOX) += virtio.o
obj-$(CONFIG_DMA) += dma.o
+obj-$(CONFIG_DM_MDIO) += mdio.o
+obj-$(CONFIG_DM_MDIO_MUX) += mdio_mux.o
endif
diff --git a/test/dm/adc.c b/test/dm/adc.c
index 1f82304..da7bd4b 100644
--- a/test/dm/adc.c
+++ b/test/dm/adc.c
@@ -24,7 +24,7 @@
struct udevice *dev;
unsigned int channel_mask;
- ut_assertok(uclass_get_device_by_name(UCLASS_ADC, "adc", &dev));
+ ut_assertok(uclass_get_device_by_name(UCLASS_ADC, "adc@0", &dev));
ut_asserteq_str(SANDBOX_ADC_DEVNAME, dev->name);
ut_assertok(adc_channel_mask(dev, &channel_mask));
@@ -38,7 +38,7 @@
{
struct udevice *dev;
- ut_assertok(uclass_get_device_by_name(UCLASS_ADC, "adc", &dev));
+ ut_assertok(uclass_get_device_by_name(UCLASS_ADC, "adc@0", &dev));
ut_asserteq(-EINVAL, adc_start_channel(dev, SANDBOX_ADC_CHANNELS));
return 0;
@@ -51,7 +51,7 @@
struct udevice *dev;
int uV;
- ut_assertok(uclass_get_device_by_name(UCLASS_ADC, "adc", &dev));
+ ut_assertok(uclass_get_device_by_name(UCLASS_ADC, "adc@0", &dev));
/* Test Vss value - predefined 0 uV */
ut_assertok(adc_vss_value(dev, &uV));
@@ -94,7 +94,7 @@
unsigned int i, data;
struct udevice *dev;
- ut_assertok(uclass_get_device_by_name(UCLASS_ADC, "adc", &dev));
+ ut_assertok(uclass_get_device_by_name(UCLASS_ADC, "adc@0", &dev));
/* Test each ADC channel's value */
for (i = 0; i < SANDBOX_ADC_CHANNELS; i++, tdata++) {
ut_assertok(adc_start_channel(dev, tdata->id));
@@ -117,7 +117,7 @@
ADC_CHANNEL(2) | ADC_CHANNEL(3);
/* Start multi channel conversion */
- ut_assertok(uclass_get_device_by_name(UCLASS_ADC, "adc", &dev));
+ ut_assertok(uclass_get_device_by_name(UCLASS_ADC, "adc@0", &dev));
ut_assertok(adc_start_channels(dev, channel_mask));
ut_assertok(adc_channels_data(dev, channel_mask, channels));
@@ -136,7 +136,7 @@
for (i = 0; i < SANDBOX_ADC_CHANNELS; i++, tdata++) {
/* Start single channel conversion */
- ut_assertok(adc_channel_single_shot("adc", tdata->id, &data));
+ ut_assertok(adc_channel_single_shot("adc@0", tdata->id, &data));
/* Compare the expected and returned conversion data. */
ut_asserteq(tdata->data, data);
}
@@ -155,7 +155,7 @@
ADC_CHANNEL(2) | ADC_CHANNEL(3);
/* Start single call and multi channel conversion */
- ut_assertok(adc_channels_single_shot("adc", channel_mask, channels));
+ ut_assertok(adc_channels_single_shot("adc@0", channel_mask, channels));
/* Compare the expected and returned conversion data. */
for (i = 0; i < SANDBOX_ADC_CHANNELS; i++, tdata++)
@@ -183,7 +183,7 @@
struct udevice *dev;
int uV;
- ut_assertok(uclass_get_device_by_name(UCLASS_ADC, "adc", &dev));
+ ut_assertok(uclass_get_device_by_name(UCLASS_ADC, "adc@0", &dev));
/* Test each ADC channel's value in microvolts */
for (i = 0; i < SANDBOX_ADC_CHANNELS; i++, tdata++) {
ut_assertok(adc_start_channel(dev, tdata->id));
diff --git a/test/dm/cache.c b/test/dm/cache.c
index d4144aa..2e244b1 100644
--- a/test/dm/cache.c
+++ b/test/dm/cache.c
@@ -14,6 +14,8 @@
ut_assertok(uclass_get_device(UCLASS_CACHE, 0, &dev_cache));
ut_assertok(cache_get_info(dev, &info));
+ ut_assertok(cache_enable(dev));
+ ut_assertok(cache_disable(dev));
return 0;
}
diff --git a/test/dm/clk.c b/test/dm/clk.c
index f301ecb..676ef21 100644
--- a/test/dm/clk.c
+++ b/test/dm/clk.c
@@ -24,6 +24,7 @@
/* Get the same clk port in 2 different ways and compare */
ut_assertok(clk_get_by_index(dev, 1, &clk_method1));
ut_assertok(clk_get_by_index_nodev(dev_ofnode(dev), 1, &clk_method2));
+ ut_asserteq(clk_is_match(&clk_method1, &clk_method2), true);
ut_asserteq(clk_method1.id, clk_method2.id);
return 0;
diff --git a/test/dm/clk_ccf.c b/test/dm/clk_ccf.c
new file mode 100644
index 0000000..ae3a4d8
--- /dev/null
+++ b/test/dm/clk_ccf.c
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <asm/clk.h>
+#include <dm/test.h>
+#include <dm/uclass.h>
+#include <linux/err.h>
+#include <test/ut.h>
+#include <sandbox-clk.h>
+
+/* Tests for Common Clock Framework driver */
+static int dm_test_clk_ccf(struct unit_test_state *uts)
+{
+ struct clk *clk, *pclk;
+ struct udevice *dev;
+ long long rate;
+ int ret;
+
+ /* Get the device using the clk device */
+ ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-ccf", &dev));
+
+ /* Test for clk_get_by_id() */
+ ret = clk_get_by_id(SANDBOX_CLK_ECSPI_ROOT, &clk);
+ ut_assertok(ret);
+ ut_asserteq_str("ecspi_root", clk->dev->name);
+
+ /* Test for clk_get_parent_rate() */
+ ret = clk_get_by_id(SANDBOX_CLK_ECSPI1, &clk);
+ ut_assertok(ret);
+ ut_asserteq_str("ecspi1", clk->dev->name);
+
+ rate = clk_get_parent_rate(clk);
+ ut_asserteq(rate, 20000000);
+
+ /* Test the mux of CCF */
+ ret = clk_get_by_id(SANDBOX_CLK_USDHC1_SEL, &clk);
+ ut_assertok(ret);
+ ut_asserteq_str("usdhc1_sel", clk->dev->name);
+
+ rate = clk_get_parent_rate(clk);
+ ut_asserteq(rate, 60000000);
+
+ ret = clk_get_by_id(SANDBOX_CLK_USDHC2_SEL, &clk);
+ ut_assertok(ret);
+ ut_asserteq_str("usdhc2_sel", clk->dev->name);
+
+ rate = clk_get_parent_rate(clk);
+ ut_asserteq(rate, 80000000);
+
+ pclk = clk_get_parent(clk);
+ ut_asserteq_str("pll3_80m", pclk->dev->name);
+
+ /* Test the composite of CCF */
+ ret = clk_get_by_id(SANDBOX_CLK_I2C, &clk);
+ ut_assertok(ret);
+ ut_asserteq_str("i2c", clk->dev->name);
+
+ rate = clk_get_rate(clk);
+ ut_asserteq(rate, 60000000);
+
+#if CONFIG_IS_ENABLED(CLK_CCF)
+ /* Test clk tree enable/disable */
+ ret = clk_get_by_id(SANDBOX_CLK_I2C_ROOT, &clk);
+ ut_assertok(ret);
+ ut_asserteq_str("i2c_root", clk->dev->name);
+
+ ret = clk_enable(clk);
+ ut_assertok(ret);
+
+ ret = sandbox_clk_enable_count(clk);
+ ut_asserteq(ret, 1);
+
+ ret = clk_get_by_id(SANDBOX_CLK_I2C, &pclk);
+ ut_assertok(ret);
+
+ ret = sandbox_clk_enable_count(pclk);
+ ut_asserteq(ret, 1);
+
+ ret = clk_disable(clk);
+ ut_assertok(ret);
+
+ ret = sandbox_clk_enable_count(clk);
+ ut_asserteq(ret, 0);
+
+ ret = sandbox_clk_enable_count(pclk);
+ ut_asserteq(ret, 0);
+#endif
+
+ return 1;
+}
+
+DM_TEST(dm_test_clk_ccf, DM_TESTF_SCAN_FDT);
diff --git a/test/dm/eth.c b/test/dm/eth.c
index 6e002b8..ad5354b 100644
--- a/test/dm/eth.c
+++ b/test/dm/eth.c
@@ -8,6 +8,7 @@
#include <common.h>
#include <dm.h>
+#include <env.h>
#include <fdtdec.h>
#include <malloc.h>
#include <net.h>
diff --git a/test/dm/mdio.c b/test/dm/mdio.c
new file mode 100644
index 0000000..dc229ae
--- /dev/null
+++ b/test/dm/mdio.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019
+ * Alex Marginean, NXP
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/test.h>
+#include <misc.h>
+#include <test/ut.h>
+#include <miiphy.h>
+
+/* macros copied over from mdio_sandbox.c */
+#define SANDBOX_PHY_ADDR 5
+#define SANDBOX_PHY_REG_CNT 2
+
+/* test using 1st register, 0 */
+#define SANDBOX_PHY_REG 0
+
+#define TEST_REG_VALUE 0xabcd
+
+static int dm_test_mdio(struct unit_test_state *uts)
+{
+ struct uclass *uc;
+ struct udevice *dev;
+ struct mdio_ops *ops;
+ u16 reg;
+
+ ut_assertok(uclass_get(UCLASS_MDIO, &uc));
+
+ ut_assertok(uclass_get_device_by_name(UCLASS_MDIO, "mdio-test", &dev));
+
+ ops = mdio_get_ops(dev);
+ ut_assertnonnull(ops);
+ ut_assertnonnull(ops->read);
+ ut_assertnonnull(ops->write);
+
+ ut_assertok(ops->write(dev, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE,
+ SANDBOX_PHY_REG, TEST_REG_VALUE));
+ reg = ops->read(dev, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE,
+ SANDBOX_PHY_REG);
+ ut_asserteq(reg, TEST_REG_VALUE);
+
+ ut_assert(ops->read(dev, SANDBOX_PHY_ADDR + 1, MDIO_DEVAD_NONE,
+ SANDBOX_PHY_REG) != 0);
+
+ ut_assertok(ops->reset(dev));
+ reg = ops->read(dev, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE,
+ SANDBOX_PHY_REG);
+ ut_asserteq(reg, 0);
+
+ return 0;
+}
+
+DM_TEST(dm_test_mdio, DM_TESTF_SCAN_FDT);
diff --git a/test/dm/mdio_mux.c b/test/dm/mdio_mux.c
new file mode 100644
index 0000000..f962e09
--- /dev/null
+++ b/test/dm/mdio_mux.c
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019
+ * Alex Marginean, NXP
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/test.h>
+#include <misc.h>
+#include <test/ut.h>
+#include <miiphy.h>
+
+/* macros copied over from mdio_sandbox.c */
+#define SANDBOX_PHY_ADDR 5
+#define SANDBOX_PHY_REG_CNT 2
+
+#define TEST_REG_VALUE 0xabcd
+
+static int dm_test_mdio_mux(struct unit_test_state *uts)
+{
+ struct uclass *uc;
+ struct udevice *mux;
+ struct udevice *mdio_ch0, *mdio_ch1, *mdio;
+ struct mdio_ops *ops, *ops_parent;
+ struct mdio_mux_ops *mmops;
+ u16 reg;
+
+ ut_assertok(uclass_get(UCLASS_MDIO_MUX, &uc));
+
+ ut_assertok(uclass_get_device_by_name(UCLASS_MDIO_MUX, "mdio-mux-test",
+ &mux));
+
+ ut_assertok(uclass_get_device_by_name(UCLASS_MDIO, "mdio-ch-test@0",
+ &mdio_ch0));
+ ut_assertok(uclass_get_device_by_name(UCLASS_MDIO, "mdio-ch-test@1",
+ &mdio_ch1));
+
+ ut_assertok(uclass_get_device_by_name(UCLASS_MDIO, "mdio-test", &mdio));
+
+ ops = mdio_get_ops(mdio_ch0);
+ ut_assertnonnull(ops);
+ ut_assertnonnull(ops->read);
+ ut_assertnonnull(ops->write);
+
+ mmops = mdio_mux_get_ops(mux);
+ ut_assertnonnull(mmops);
+ ut_assertnonnull(mmops->select);
+
+ ops_parent = mdio_get_ops(mdio);
+ ut_assertnonnull(ops);
+ ut_assertnonnull(ops->read);
+
+ /*
+ * mux driver sets last register on the emulated PHY whenever a group
+ * is selected to the selection #. Just reading that register from
+ * either of the child buses should return the id of the child bus
+ */
+ reg = ops->read(mdio_ch0, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE,
+ SANDBOX_PHY_REG_CNT - 1);
+ ut_asserteq(reg, 0);
+
+ reg = ops->read(mdio_ch1, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE,
+ SANDBOX_PHY_REG_CNT - 1);
+ ut_asserteq(reg, 1);
+
+ mmops->select(mux, MDIO_MUX_SELECT_NONE, 5);
+ reg = ops_parent->read(mdio, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE,
+ SANDBOX_PHY_REG_CNT - 1);
+ ut_asserteq(reg, 5);
+
+ mmops->deselect(mux, 5);
+ reg = ops_parent->read(mdio, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE,
+ SANDBOX_PHY_REG_CNT - 1);
+ ut_asserteq(reg, (u16)MDIO_MUX_SELECT_NONE);
+
+ return 0;
+}
+
+DM_TEST(dm_test_mdio_mux, DM_TESTF_SCAN_FDT);
diff --git a/test/dm/pci.c b/test/dm/pci.c
index a1febd5..c325f66 100644
--- a/test/dm/pci.c
+++ b/test/dm/pci.c
@@ -245,3 +245,52 @@
return 0;
}
DM_TEST(dm_test_pci_cap, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test looking up BARs in EA capability structure */
+static int dm_test_pci_ea(struct unit_test_state *uts)
+{
+ struct udevice *bus, *swap;
+ void *bar;
+ int cap;
+
+ /*
+ * use emulated device mapping function, we're not using real physical
+ * addresses in this test
+ */
+ sandbox_set_enable_pci_map(true);
+
+ ut_assertok(uclass_get_device_by_seq(UCLASS_PCI, 0, &bus));
+ ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x01, 0), &swap));
+
+ /* look up PCI_CAP_ID_EA */
+ cap = dm_pci_find_capability(swap, PCI_CAP_ID_EA);
+ ut_asserteq(PCI_CAP_ID_EA_OFFSET, cap);
+
+ /* test swap case in BAR 1 */
+ bar = dm_pci_map_bar(swap, PCI_BASE_ADDRESS_0, 0);
+ ut_assertnonnull(bar);
+ *(int *)bar = 2; /* swap upper/lower */
+
+ bar = dm_pci_map_bar(swap, PCI_BASE_ADDRESS_1, 0);
+ ut_assertnonnull(bar);
+ strcpy(bar, "ea TEST");
+ unmap_sysmem(bar);
+ bar = dm_pci_map_bar(swap, PCI_BASE_ADDRESS_1, 0);
+ ut_assertnonnull(bar);
+ ut_asserteq_str("EA test", bar);
+
+ /* test magic values in BARs2, 4; BAR 3 is n/a */
+ bar = dm_pci_map_bar(swap, PCI_BASE_ADDRESS_2, 0);
+ ut_assertnonnull(bar);
+ ut_asserteq(PCI_EA_BAR2_MAGIC, *(u32 *)bar);
+
+ bar = dm_pci_map_bar(swap, PCI_BASE_ADDRESS_3, 0);
+ ut_assertnull(bar);
+
+ bar = dm_pci_map_bar(swap, PCI_BASE_ADDRESS_4, 0);
+ ut_assertnonnull(bar);
+ ut_asserteq(PCI_EA_BAR4_MAGIC, *(u32 *)bar);
+
+ return 0;
+}
+DM_TEST(dm_test_pci_ea, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
diff --git a/test/dm/pci_ep.c b/test/dm/pci_ep.c
new file mode 100644
index 0000000..101f861
--- /dev/null
+++ b/test/dm/pci_ep.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Ramon Fried
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <asm/test.h>
+#include <dm/test.h>
+#include <test/ut.h>
+#include <hexdump.h>
+#include <pci_ep.h>
+
+/* Test that sandbox PCI EP works correctly */
+static int dm_test_pci_ep_base(struct unit_test_state *uts)
+{
+ struct udevice *bus;
+ struct pci_bar tmp_bar;
+ struct pci_ep_header tmp_header;
+ int i;
+
+ struct pci_ep_header ep_header = {
+ .vendorid = 0x1234,
+ .deviceid = 0x2020,
+ .revid = 1,
+ .interrupt_pin = PCI_INTERRUPT_INTA,
+ };
+
+ struct pci_bar bar = {
+ .phys_addr = 0x80000000,
+ .size = 0x100000,
+ .barno = BAR_0,
+ .flags = PCI_BASE_ADDRESS_MEM_TYPE_64 |
+ PCI_BASE_ADDRESS_MEM_PREFETCH,
+ };
+
+ ut_assertok(uclass_get_device(UCLASS_PCI_EP, 0, &bus));
+ ut_assertnonnull(bus);
+
+ ut_assertok(pci_ep_write_header(bus, 0, &ep_header));
+ ut_assertok(pci_ep_read_header(bus, 0, &tmp_header));
+ ut_asserteq_mem(&tmp_header, &ep_header, sizeof(ep_header));
+
+ ut_assertok(pci_ep_set_msi(bus, 0, 4));
+ ut_asserteq(pci_ep_get_msi(bus, 0), 4);
+
+ ut_assertok(pci_ep_set_msix(bus, 0, 360));
+ ut_asserteq(pci_ep_get_msix(bus, 0), 360);
+
+ ut_assertok(pci_ep_set_bar(bus, 0, &bar));
+
+ ut_assertok(pci_ep_read_bar(bus, 0, &tmp_bar, BAR_0));
+ ut_asserteq_mem(&tmp_bar, &bar, sizeof(bar));
+
+ for (i = 0; i < 10; i++)
+ ut_assertok(pci_ep_raise_irq(bus, 0, 1, PCI_EP_IRQ_LEGACY));
+
+ ut_asserteq(sandbox_get_pci_ep_irq_count(bus), 10);
+ return 0;
+}
+
+DM_TEST(dm_test_pci_ep_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
diff --git a/test/dm/remoteproc.c b/test/dm/remoteproc.c
index 3975c67..a2c4be7 100644
--- a/test/dm/remoteproc.c
+++ b/test/dm/remoteproc.c
@@ -5,8 +5,10 @@
*/
#include <common.h>
#include <dm.h>
+#include <elf.h>
#include <errno.h>
#include <remoteproc.h>
+#include <asm/io.h>
#include <dm/test.h>
#include <test/ut.h>
/**
@@ -65,3 +67,123 @@
return 0;
}
DM_TEST(dm_test_remoteproc_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+#define DEVICE_TO_PHYSICAL_OFFSET 0x1000
+/**
+ * dm_test_remoteproc_elf() - test the ELF operations
+ * @uts: unit test state
+ *
+ * Return: 0 if test passed, else error
+ */
+static int dm_test_remoteproc_elf(struct unit_test_state *uts)
+{
+ u8 valid_elf32[] = {
+ /* @0x00 - ELF HEADER - */
+ /* ELF magic */
+ 0x7f, 0x45, 0x4c, 0x46,
+ /* 32 Bits */
+ 0x01,
+ /* Endianness */
+#ifdef __LITTLE_ENDIAN
+ 0x01,
+#else
+ 0x02,
+#endif
+ /* Version */
+ 0x01,
+ /* Padding */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* Type : executable */
+ 0x02, 0x00,
+ /* Machine: ARM */
+ 0x28, 0x00,
+ /* Version */
+ 0x01, 0x00, 0x00, 0x00,
+ /* Entry */
+ 0x00, 0x00, 0x00, 0x08,
+ /* phoff (program header offset @ 0x40)*/
+ 0x40, 0x00, 0x00, 0x00,
+ /* shoff (section header offset : none) */
+ 0x00, 0x00, 0x00, 0x00,
+ /* flags */
+ 0x00, 0x00, 0x00, 0x00,
+ /* ehsize (elf header size = 0x34) */
+ 0x34, 0x00,
+ /* phentsize (program header size = 0x20) */
+ 0x20, 0x00,
+ /* phnum (program header number : 1) */
+ 0x01, 0x00,
+ /* shentsize (section heade size : none) */
+ 0x00, 0x00,
+ /* shnum (section header number: none) */
+ 0x00, 0x00,
+ /* shstrndx (section header name section index: none) */
+ 0x00, 0x00,
+ /* padding */
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ /* @0x40 - PROGRAM HEADER TABLE - */
+ /* type : PT_LOAD */
+ 0x01, 0x00, 0x00, 0x00,
+ /* offset */
+ 0x00, 0x00, 0x00, 0x00,
+ /* vaddr */
+ 0x00, 0x00, 0x00, 0x00,
+ /* paddr : physical address */
+ 0x00, 0x00, 0x00, 0x00,
+ /* filesz : 0x20 bytes (program header size) */
+ 0x20, 0x00, 0x00, 0x00,
+ /* memsz = filesz */
+ 0x20, 0x00, 0x00, 0x00,
+ /* flags : readable and exectuable */
+ 0x05, 0x00, 0x00, 0x00,
+ /* padding */
+ 0x00, 0x00, 0x00, 0x00,
+ };
+ unsigned int size = ARRAY_SIZE(valid_elf32);
+ struct udevice *dev;
+ phys_addr_t loaded_firmware_paddr;
+ void *loaded_firmware;
+ u32 loaded_firmware_size;
+ Elf32_Ehdr *ehdr = (Elf32_Ehdr *)valid_elf32;
+ Elf32_Phdr *phdr = (Elf32_Phdr *)(valid_elf32 + ehdr->e_phoff);
+
+ ut_assertok(uclass_get_device(UCLASS_REMOTEPROC, 0, &dev));
+
+ /*
+ * In its Program Header Table, let the firmware specifies to be loaded
+ * at SDRAM_BASE *device* address (p_paddr field).
+ * Its size is defined by the p_filesz field.
+ */
+ phdr->p_paddr = CONFIG_SYS_SDRAM_BASE;
+ loaded_firmware_size = phdr->p_filesz;
+
+ /*
+ * This *device* address is converted to a *physical* address by the
+ * device_to_virt() operation of sandbox_test_rproc which returns
+ * DeviceAddress + DEVICE_TO_PHYSICAL_OFFSET.
+ * This is where we expect to get the firmware loaded.
+ */
+ loaded_firmware_paddr = phdr->p_paddr + DEVICE_TO_PHYSICAL_OFFSET;
+ loaded_firmware = map_physmem(loaded_firmware_paddr,
+ loaded_firmware_size, MAP_NOCACHE);
+ ut_assertnonnull(loaded_firmware);
+ memset(loaded_firmware, 0, loaded_firmware_size);
+
+ /* Verify valid ELF format */
+ ut_assertok(rproc_elf32_sanity_check((ulong)valid_elf32, size));
+
+ /* Load firmware in loaded_firmware, and verify it */
+ ut_assertok(rproc_elf32_load_image(dev, (unsigned long)valid_elf32));
+ ut_assertok(memcmp(loaded_firmware, valid_elf32, loaded_firmware_size));
+ unmap_physmem(loaded_firmware, MAP_NOCACHE);
+
+ /* Invalid ELF Magic */
+ valid_elf32[0] = 0;
+ ut_asserteq(-EPROTONOSUPPORT,
+ rproc_elf32_sanity_check((ulong)valid_elf32, size));
+
+ return 0;
+}
+DM_TEST(dm_test_remoteproc_elf, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
diff --git a/test/dm/test-fdt.c b/test/dm/test-fdt.c
index be16c99..1fb8b5c 100644
--- a/test/dm/test-fdt.c
+++ b/test/dm/test-fdt.c
@@ -490,6 +490,7 @@
static int dm_test_fdt_translation(struct unit_test_state *uts)
{
struct udevice *dev;
+ fdt32_t dma_addr[2];
/* Some simple translations */
ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_DUMMY, 0, true, &dev));
@@ -509,6 +510,17 @@
ut_asserteq_str("dev@42", dev->name);
ut_asserteq(0x42, dev_read_addr(dev));
+ /* dma address translation */
+ ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_DUMMY, 0, true, &dev));
+ dma_addr[0] = cpu_to_be32(0);
+ dma_addr[1] = cpu_to_be32(0);
+ ut_asserteq(0x10000000, dev_translate_dma_address(dev, dma_addr));
+
+ ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_DUMMY, 1, true, &dev));
+ dma_addr[0] = cpu_to_be32(1);
+ dma_addr[1] = cpu_to_be32(0x100);
+ ut_asserteq(0x20000000, dev_translate_dma_address(dev, dma_addr));
+
return 0;
}
DM_TEST(dm_test_fdt_translation, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
@@ -537,12 +549,14 @@
{
struct udevice *dev;
fdt_addr_t addr;
+ fdt_size_t size;
void *paddr;
ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_DUMMY, 0, true, &dev));
- addr = devfdt_get_addr_index(dev, 0);
+ addr = devfdt_get_addr_size_index(dev, 0, &size);
ut_asserteq(0x8000, addr);
+ ut_asserteq(0x1000, size);
paddr = map_physmem(addr, 0, MAP_NOCACHE);
ut_assertnonnull(paddr);
@@ -557,12 +571,14 @@
{
struct udevice *dev;
fdt_addr_t addr;
+ fdt_size_t size;
void *paddr;
ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_DUMMY, 0, true, &dev));
- addr = devfdt_get_addr_name(dev, "sandbox-dummy-0");
+ addr = devfdt_get_addr_size_name(dev, "sandbox-dummy-0", &size);
ut_asserteq(0x8000, addr);
+ ut_asserteq(0x1000, size);
paddr = map_physmem(addr, 0, MAP_NOCACHE);
ut_assertnonnull(paddr);
@@ -597,12 +613,14 @@
{
struct udevice *dev;
fdt_addr_t addr;
+ fdt_size_t size;
void *paddr;
ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_DUMMY, 0, true, &dev));
- addr = dev_read_addr_index(dev, 0);
+ addr = dev_read_addr_size_index(dev, 0, &size);
ut_asserteq(0x8000, addr);
+ ut_asserteq(0x1000, size);
paddr = map_physmem(addr, 0, MAP_NOCACHE);
ut_assertnonnull(paddr);
@@ -617,12 +635,14 @@
{
struct udevice *dev;
fdt_addr_t addr;
+ fdt_size_t size;
void *paddr;
ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_DUMMY, 0, true, &dev));
- addr = dev_read_addr_name(dev, "sandbox-dummy-0");
+ addr = dev_read_addr_size_name(dev, "sandbox-dummy-0", &size);
ut_asserteq(0x8000, addr);
+ ut_asserteq(0x1000, size);
paddr = map_physmem(addr, 0, MAP_NOCACHE);
ut_assertnonnull(paddr);
diff --git a/test/dm/usb.c b/test/dm/usb.c
index 3493617..ef454b0 100644
--- a/test/dm/usb.c
+++ b/test/dm/usb.c
@@ -125,7 +125,7 @@
/* Initially there should be no characters */
ut_asserteq(0, tstc());
- ut_assertok(uclass_get_device_by_name(UCLASS_USB_EMUL, "keyb",
+ ut_assertok(uclass_get_device_by_name(UCLASS_USB_EMUL, "keyb@3",
&dev));
/*
diff --git a/test/env/hashtable.c b/test/env/hashtable.c
index 8c87e65..5242c4c 100644
--- a/test/env/hashtable.c
+++ b/test/env/hashtable.c
@@ -18,8 +18,8 @@
struct hsearch_data *htab, size_t size)
{
size_t i;
- ENTRY item;
- ENTRY *ritem;
+ struct env_entry item;
+ struct env_entry *ritem;
char key[20];
for (i = 0; i < size; i++) {
@@ -28,7 +28,7 @@
item.data = key;
item.flags = 0;
item.key = key;
- ut_asserteq(1, hsearch_r(item, ENTER, &ritem, htab, 0));
+ ut_asserteq(1, hsearch_r(item, ENV_ENTER, &ritem, htab, 0));
}
return 0;
@@ -38,8 +38,8 @@
struct hsearch_data *htab, size_t size)
{
size_t i;
- ENTRY item;
- ENTRY *ritem;
+ struct env_entry item;
+ struct env_entry *ritem;
char key[20];
for (i = 0; i < size; i++) {
@@ -48,7 +48,7 @@
item.flags = 0;
item.data = key;
item.key = key;
- hsearch_r(item, FIND, &ritem, htab, 0);
+ hsearch_r(item, ENV_FIND, &ritem, htab, 0);
ut_assert(ritem);
ut_asserteq_str(key, ritem->key);
ut_asserteq_str(key, ritem->data);
@@ -61,8 +61,8 @@
struct hsearch_data *htab, size_t iterations)
{
size_t i;
- ENTRY item;
- ENTRY *ritem;
+ struct env_entry item;
+ struct env_entry *ritem;
char key[20];
for (i = 0; i < iterations; i++) {
@@ -71,10 +71,10 @@
item.flags = 0;
item.data = key;
item.key = key;
- hsearch_r(item, ENTER, &ritem, htab, 0);
+ hsearch_r(item, ENV_ENTER, &ritem, htab, 0);
ritem = NULL;
- hsearch_r(item, FIND, &ritem, htab, 0);
+ hsearch_r(item, ENV_FIND, &ritem, htab, 0);
ut_assert(ritem);
ut_asserteq_str(key, ritem->key);
ut_asserteq_str(key, ritem->data);
diff --git a/test/py/tests/test_avb.py b/test/py/tests/test_android/test_avb.py
similarity index 100%
rename from test/py/tests/test_avb.py
rename to test/py/tests/test_android/test_avb.py
diff --git a/test/py/tests/test_efi_selftest.py b/test/py/tests/test_efi_selftest.py
index 07e4db0..d5430f9 100644
--- a/test/py/tests/test_efi_selftest.py
+++ b/test/py/tests/test_efi_selftest.py
@@ -19,10 +19,6 @@
m = u_boot_console.p.expect(['Summary: 0 failures', 'Press any key'])
if m != 0:
raise Exception('Failures occurred during the EFI selftest')
- u_boot_console.run_command(cmd='', wait_for_echo=False, wait_for_prompt=False);
- m = u_boot_console.p.expect(['resetting', 'U-Boot'])
- if m != 0:
- raise Exception('Reset failed during the EFI selftest')
u_boot_console.restart_uboot();
@pytest.mark.buildconfigspec('cmd_bootefi_selftest')
@@ -37,7 +33,7 @@
u_boot_console.run_command(cmd='bootefi selftest ${fdtcontroladdr}', wait_for_prompt=False)
m = u_boot_console.p.expect(['serial-number: Testing DT', 'U-Boot'])
if m != 0:
- raise Exception('Reset failed in \'device tree\' test')
+ raise Exception('serial-number missing in device tree')
u_boot_console.restart_uboot();
@pytest.mark.buildconfigspec('cmd_bootefi_selftest')
diff --git a/test/py/tests/test_fit.py b/test/py/tests/test_fit.py
index 49d6fea..e3210ed 100755
--- a/test/py/tests/test_fit.py
+++ b/test/py/tests/test_fit.py
@@ -24,7 +24,7 @@
type = "kernel";
arch = "sandbox";
os = "linux";
- compression = "none";
+ compression = "%(compression)s";
load = <0x40000>;
entry = <0x8>;
};
@@ -39,11 +39,11 @@
};
fdt@1 {
description = "snow";
- data = /incbin/("u-boot.dtb");
+ data = /incbin/("%(fdt)s");
type = "flat_dt";
arch = "sandbox";
%(fdt_load)s
- compression = "none";
+ compression = "%(compression)s";
signature@1 {
algo = "sha1,rsa2048";
key-name-hint = "dev";
@@ -56,7 +56,7 @@
arch = "sandbox";
os = "linux";
%(ramdisk_load)s
- compression = "none";
+ compression = "%(compression)s";
};
ramdisk@2 {
description = "snow";
@@ -221,6 +221,10 @@
print(data, file=fd)
return fname
+ def make_compressed(filename):
+ util.run_and_log(cons, ['gzip', '-f', '-k', filename])
+ return filename + '.gz'
+
def find_matching(text, match):
"""Find a match in a line of text, and return the unmatched line portion
@@ -265,6 +269,11 @@
def check_equal(expected_fname, actual_fname, failure_msg):
"""Check that a file matches its expected contents
+ This is always used on out-buffers whose size is decided by the test
+ script anyway, which in some cases may be larger than what we're
+ actually looking for. So it's safe to truncate it to the size of the
+ expected data.
+
Args:
expected_fname: Filename containing expected contents
actual_fname: Filename containing actual contents
@@ -272,6 +281,8 @@
"""
expected_data = read_file(expected_fname)
actual_data = read_file(actual_fname)
+ if len(expected_data) < len(actual_data):
+ actual_data = actual_data[:len(expected_data)]
assert expected_data == actual_data, failure_msg
def check_not_equal(expected_fname, actual_fname, failure_msg):
@@ -312,6 +323,7 @@
loadables1 = make_kernel('test-loadables1.bin', 'lenrek')
loadables2 = make_ramdisk('test-loadables2.bin', 'ksidmar')
kernel_out = make_fname('kernel-out.bin')
+ fdt = make_fname('u-boot.dtb')
fdt_out = make_fname('fdt-out.dtb')
ramdisk_out = make_fname('ramdisk-out.bin')
loadables1_out = make_fname('loadables1-out.bin')
@@ -326,6 +338,7 @@
'kernel_addr' : 0x40000,
'kernel_size' : filesize(kernel),
+ 'fdt' : fdt,
'fdt_out' : fdt_out,
'fdt_addr' : 0x80000,
'fdt_size' : filesize(control_dtb),
@@ -351,6 +364,7 @@
'loadables2_load' : '',
'loadables_config' : '',
+ 'compression' : 'none',
}
# Make a basic FIT and a script to load it
@@ -417,6 +431,21 @@
check_equal(loadables2, loadables2_out,
'Loadables2 (ramdisk) not loaded')
+ # Kernel, FDT and Ramdisk all compressed
+ with cons.log.section('(Kernel + FDT + Ramdisk) compressed'):
+ params['compression'] = 'gzip'
+ params['kernel'] = make_compressed(kernel)
+ params['fdt'] = make_compressed(fdt)
+ params['ramdisk'] = make_compressed(ramdisk)
+ fit = make_fit(mkimage, params)
+ cons.restart_uboot()
+ output = cons.run_command_list(cmd.splitlines())
+ check_equal(kernel, kernel_out, 'Kernel not loaded')
+ check_equal(control_dtb, fdt_out, 'FDT not loaded')
+ check_not_equal(ramdisk, ramdisk_out, 'Ramdisk got decompressed?')
+ check_equal(ramdisk + '.gz', ramdisk_out, 'Ramdist not loaded')
+
+
cons = u_boot_console
try:
# We need to use our own device tree file. Remember to restore it
diff --git a/test/py/tests/test_gpt.py b/test/py/tests/test_gpt.py
index c8edb33..229d7eb 100644
--- a/test/py/tests/test_gpt.py
+++ b/test/py/tests/test_gpt.py
@@ -40,16 +40,19 @@
fd = os.open(persistent, os.O_RDWR | os.O_CREAT)
os.ftruncate(fd, 4194304)
os.close(fd)
- cmd = ('sgdisk', '-U', '375a56f7-d6c9-4e81-b5f0-09d41ca89efe',
+ cmd = ('sgdisk',
+ '--disk-guid=375a56f7-d6c9-4e81-b5f0-09d41ca89efe',
persistent)
u_boot_utils.run_and_log(u_boot_console, cmd)
# part1 offset 1MB size 1MB
- cmd = ('sgdisk', '--new=1:2048:4095', '-c 1:part1', persistent)
+ cmd = ('sgdisk', '--new=1:2048:4095', '--change-name=1:part1',
+ persistent)
# part2 offset 2MB size 1.5MB
u_boot_utils.run_and_log(u_boot_console, cmd)
- cmd = ('sgdisk', '--new=2:4096:7167', '-c 2:part2', persistent)
+ cmd = ('sgdisk', '--new=2:4096:7167', '--change-name=2:part2',
+ persistent)
u_boot_utils.run_and_log(u_boot_console, cmd)
- cmd = ('sgdisk', '-l', persistent)
+ cmd = ('sgdisk', '--load-backup=' + persistent)
u_boot_utils.run_and_log(u_boot_console, cmd)
cmd = ('cp', persistent, self.path)
diff --git a/test/py/tests/test_mmc_wr.py b/test/py/tests/test_mmc_wr.py
new file mode 100644
index 0000000..8b18781
--- /dev/null
+++ b/test/py/tests/test_mmc_wr.py
@@ -0,0 +1,105 @@
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (c) 2019, Texas Instrument
+# Author: Jean-Jacques Hiblot <jjhiblot@ti.com>
+
+# Test U-Boot's "mmc write" command. The test generates random data, writes it
+# to the eMMC or SD card, then reads it back and performs a comparison.
+
+import pytest
+import u_boot_utils
+
+"""
+This test relies on boardenv_* to containing configuration values to define
+which MMC devices should be tested. For example:
+
+env__mmc_wr_configs = (
+ {
+ "fixture_id": "emmc-boot0",
+ "is_emmc": True,
+ "devid": 1,
+ "partid": 1,
+ "sector": 0x10,
+ "count": 100,
+ "test_iterations": 50,
+ },
+ {
+ "fixture_id": "emmc-boot1",
+ "is_emmc": True,
+ "devid": 1,
+ "partid": 2,
+ "sector": 0x10,
+ "count": 100,
+ "test_iterations": 50,
+ },
+)
+
+"""
+
+@pytest.mark.buildconfigspec('cmd_mmc','cmd_memory', 'cmd_random')
+def test_mmc_wr(u_boot_console, env__mmc_wr_config):
+ """Test the "mmc write" command.
+
+ Args:
+ u_boot_console: A U-Boot console connection.
+ env__mmc_wr_config: The single MMC configuration on which
+ to run the test. See the file-level comment above for details
+ of the format.
+
+ Returns:
+ Nothing.
+ """
+
+ is_emmc = env__mmc_wr_config['is_emmc']
+ devid = env__mmc_wr_config['devid']
+ partid = env__mmc_wr_config.get('partid', 0)
+ sector = env__mmc_wr_config.get('sector', 0)
+ count_sectors = env__mmc_wr_config.get('count', 1)
+ test_iterations = env__mmc_wr_config.get('test_iterations', 1)
+
+
+ count_bytes = count_sectors * 512
+ bcfg = u_boot_console.config.buildconfig
+ ram_base = u_boot_utils.find_ram_base(u_boot_console)
+ src_addr = '0x%08x' % ram_base
+ dst_addr = '0x%08x' % (ram_base + count_bytes)
+
+
+ for i in range(test_iterations):
+ # Generate random data
+ cmd = 'random %s %x' % (src_addr, count_bytes)
+ response = u_boot_console.run_command(cmd)
+ good_response = '%d bytes filled with random data' % (count_bytes)
+ assert good_response in response
+
+ # Select MMC device
+ cmd = 'mmc dev %d' % devid
+ if is_emmc:
+ cmd += ' %d' % partid
+ response = u_boot_console.run_command(cmd)
+ assert 'no card present' not in response
+ if is_emmc:
+ partid_response = "(part %d)" % partid
+ else:
+ partid_response = ""
+ good_response = 'mmc%d%s is current device' % (devid, partid_response)
+ assert good_response in response
+
+ # Write data
+ cmd = 'mmc write %s %x %x' % (src_addr, sector, count_sectors)
+ response = u_boot_console.run_command(cmd)
+ good_response = 'MMC write: dev # %d, block # %d, count %d ... %d blocks written: OK' % (
+ devid, sector, count_sectors, count_sectors)
+ assert good_response in response
+
+ # Read data
+ cmd = 'mmc read %s %x %x' % (dst_addr, sector, count_sectors)
+ response = u_boot_console.run_command(cmd)
+ good_response = 'MMC read: dev # %d, block # %d, count %d ... %d blocks read: OK' % (
+ devid, sector, count_sectors, count_sectors)
+ assert good_response in response
+
+ # Compare src and dst data
+ cmd = 'cmp.b %s %s %x' % (src_addr, dst_addr, count_bytes)
+ response = u_boot_console.run_command(cmd)
+ good_response = 'Total of %d byte(s) were the same' % (count_bytes)
+ assert good_response in response
diff --git a/test/py/tests/test_ofplatdata.py b/test/py/tests/test_ofplatdata.py
index 98103ee..263334b 100644
--- a/test/py/tests/test_ofplatdata.py
+++ b/test/py/tests/test_ofplatdata.py
@@ -2,6 +2,7 @@
# Copyright (c) 2016 Google, Inc
import pytest
+import u_boot_utils as util
OF_PLATDATA_OUTPUT = '''
of-platdata probe:
@@ -31,6 +32,15 @@
longbytearray 00 00 00 00 00 00 00 00 00
string <NULL>
stringarray "one" "" ""
+of-platdata probe:
+bool 0
+byte 00
+bytearray 00 00 00
+int 0
+intarray 0 0 0 0
+longbytearray 00 00 00 00 00 00 00 00 00
+string <NULL>
+stringarray "spl" "" ""
'''
@pytest.mark.buildconfigspec('spl_of_platdata')
@@ -40,3 +50,21 @@
cons.restart_uboot_with_flags(['--show_of_platdata'])
output = cons.get_spawn_output().replace('\r', '')
assert OF_PLATDATA_OUTPUT in output
+
+@pytest.mark.buildconfigspec('spl_of_platdata')
+def test_spl_devicetree(u_boot_console):
+ """Test content of spl device-tree"""
+ cons = u_boot_console
+ dtb = cons.config.build_dir + '/spl/u-boot-spl.dtb'
+ fdtgrep = cons.config.build_dir + '/tools/fdtgrep'
+ output = util.run_and_log(cons, [fdtgrep, '-l', dtb])
+
+ assert "u-boot,dm-pre-reloc" not in output
+ assert "u-boot,dm-pre-proper" not in output
+ assert "u-boot,dm-spl" not in output
+ assert "u-boot,dm-tpl" not in output
+
+ assert "spl-test4" in output
+ assert "spl-test5" not in output
+ assert "spl-test6" not in output
+ assert "spl-test7" in output
diff --git a/test/run b/test/run
index 55a6649..d635622 100755
--- a/test/run
+++ b/test/run
@@ -33,12 +33,14 @@
-k test_ut
# Set up a path to dtc (device-tree compiler) and libfdt.py, a library it
-# provides and which is built by the sandbox_spl config.
+# provides and which is built by the sandbox_spl config. Also set up the path
+# to tools build by the build.
DTC_DIR=build-sandbox_spl/scripts/dtc
export PYTHONPATH=${DTC_DIR}/pylibfdt
export DTC=${DTC_DIR}/dtc
+TOOLS_DIR=build-sandbox_spl/tools
-run_test "binman" ./tools/binman/binman -t
+run_test "binman" ./tools/binman/binman --toolpath ${TOOLS_DIR} test
run_test "patman" ./tools/patman/patman --test
[ "$1" == "quick" ] && skip=--skip-net-tests
@@ -49,7 +51,8 @@
# This needs you to set up Python test coverage tools.
# To enable Python test coverage on Debian-type distributions (e.g. Ubuntu):
# $ sudo apt-get install python-pytest python-coverage
-run_test "binman code coverage" ./tools/binman/binman -T
+export PATH=$PATH:${TOOLS_DIR}
+run_test "binman code coverage" ./tools/binman/binman test -T
run_test "dtoc code coverage" ./tools/dtoc/dtoc -T
run_test "fdt code coverage" ./tools/dtoc/test_fdt -T
diff --git a/test/unicode_ut.c b/test/unicode_ut.c
index 8e1efe6..8875cdc 100644
--- a/test/unicode_ut.c
+++ b/test/unicode_ut.c
@@ -50,6 +50,16 @@
static const char j2[] = {0x6a, 0x32, 0xc3, 0xc3, 0x6c, 0x00};
static const char j3[] = {0x6a, 0x33, 0xf0, 0x90, 0xf0, 0x00};
+static int unicode_test_u16_strlen(struct unit_test_state *uts)
+{
+ ut_asserteq(6, u16_strlen(c1));
+ ut_asserteq(8, u16_strlen(c2));
+ ut_asserteq(3, u16_strlen(c3));
+ ut_asserteq(6, u16_strlen(c4));
+ return 0;
+}
+UNICODE_TEST(unicode_test_u16_strlen);
+
static int unicode_test_u16_strdup(struct unit_test_state *uts)
{
u16 *copy = u16_strdup(c4);
@@ -557,6 +567,19 @@
}
UNICODE_TEST(unicode_test_utf_to_upper);
+static int unicode_test_u16_strncmp(struct unit_test_state *uts)
+{
+ ut_assert(u16_strncmp(L"abc", L"abc", 3) == 0);
+ ut_assert(u16_strncmp(L"abcdef", L"abcghi", 3) == 0);
+ ut_assert(u16_strncmp(L"abcdef", L"abcghi", 6) < 0);
+ ut_assert(u16_strncmp(L"abcghi", L"abcdef", 6) > 0);
+ ut_assert(u16_strcmp(L"abc", L"abc") == 0);
+ ut_assert(u16_strcmp(L"abcdef", L"deghi") < 0);
+ ut_assert(u16_strcmp(L"deghi", L"abcdef") > 0);
+ return 0;
+}
+UNICODE_TEST(unicode_test_u16_strncmp);
+
int do_ut_unicode(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
struct unit_test *tests = ll_entry_start(struct unit_test, unicode_test);
diff --git a/tools/.gitignore b/tools/.gitignore
index 767b056..bd03d32 100644
--- a/tools/.gitignore
+++ b/tools/.gitignore
@@ -14,6 +14,7 @@
/gen_eth_addr
/gen_ethaddr_crc
/ifdtool
+/ifwitool
/img2srec
/kwboot
/lib/
diff --git a/tools/Makefile b/tools/Makefile
index 33e90a8..24581ad 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -15,7 +15,6 @@
CONFIG_ARCH_SUNXI = y
endif
-subdir-$(HOST_TOOLS_ALL) += easylogo
subdir-$(HOST_TOOLS_ALL) += gdb
# Merge all the different vars for envcrc into one
@@ -175,6 +174,9 @@
ifdtool-objs := $(LIBFDT_OBJS) ifdtool.o
hostprogs-$(CONFIG_X86) += ifdtool
+ifwitool-objs := ifwitool.o
+hostprogs-$(CONFIG_X86)$(CONFIG_SANDBOX) += ifwitool
+
hostprogs-$(CONFIG_MX23) += mxsboot
hostprogs-$(CONFIG_MX28) += mxsboot
HOSTCFLAGS_mxsboot.o := -pedantic
@@ -266,8 +268,14 @@
$(LOGO_H): $(obj)/bmp_logo $(LOGO_BMP)
$(obj)/bmp_logo --gen-info $(LOGO_BMP) > $@
+ifeq ($(CONFIG_DM_VIDEO),y)
+$(LOGO_DATA_H): $(obj)/bmp_logo $(LOGO_BMP)
+ $(obj)/bmp_logo --gen-bmp $(LOGO_BMP) > $@
+else
$(LOGO_DATA_H): $(obj)/bmp_logo $(LOGO_BMP)
$(obj)/bmp_logo --gen-data $(LOGO_BMP) > $@
+#endif
+endif
# Let clean descend into subdirs
subdir- += env
diff --git a/tools/binman/README b/tools/binman/README
index 927fa85..b4f6392 100644
--- a/tools/binman/README
+++ b/tools/binman/README
@@ -36,10 +36,9 @@
they are included, by adding a Python plug-in. The device tree is available
to U-Boot at run-time so that the images can be interpreted.
-Binman does not yet update the device tree with the final location of
-everything when it is done. A simple C structure could be generated for
-constrained environments like SPL (using dtoc) but this is also not
-implemented.
+Binman can update the device tree with the final location of everything when it
+is done. Entry positions can be provided to U-Boot SPL as run-time symbols,
+avoiding device-tree code overhead.
Binman can also support incorporating filesystems in the image if required.
For example x86 platforms may use CBFS in some cases.
@@ -181,9 +180,14 @@
Running binman
--------------
+First install prerequisites, e.g.
+
+ sudo apt-get install python-pyelftools python3-pyelftools lzma-alone \
+ liblz4-tool
+
Type:
- binman -b <board_name>
+ binman build -b <board_name>
to build an image for a board. The board name is the same name used when
configuring U-Boot (e.g. for sandbox_defconfig the board name is 'sandbox').
@@ -191,7 +195,7 @@
Or you can specify this explicitly:
- binman -I <build_path>
+ binman build -I <build_path>
where <build_path> is the build directory containing the output of the U-Boot
build.
@@ -335,6 +339,10 @@
limited by the size of the image/section and the position of the next
entry.
+compress:
+ Sets the compression algortihm to use (for blobs only). See the entry
+ documentation for details.
+
The attributes supported for images and sections are described below. Several
are similar to those for entries.
@@ -473,13 +481,150 @@
distinguish binaries with otherwise identical names.
+Image Properties
+----------------
+
+Image nodes act like sections but also have a few extra properties:
+
+filename:
+ Output filename for the image. This defaults to image.bin (or in the
+ case of multiple images <nodename>.bin where <nodename> is the name of
+ the image node.
+
+allow-repack:
+ Create an image that can be repacked. With this option it is possible
+ to change anything in the image after it is created, including updating
+ the position and size of image components. By default this is not
+ permitted since it is not possibly to know whether this might violate a
+ constraint in the image description. For example, if a section has to
+ increase in size to hold a larger binary, that might cause the section
+ to fall out of its allow region (e.g. read-only portion of flash).
+
+ Adding this property causes the original offset and size values in the
+ image description to be stored in the FDT and fdtmap.
+
+
Entry Documentation
-------------------
For details on the various entry types supported by binman and how to use them,
see README.entries. This is generated from the source code using:
- binman -E >tools/binman/README.entries
+ binman entry-docs >tools/binman/README.entries
+
+
+Listing images
+--------------
+
+It is possible to list the entries in an existing firmware image created by
+binman, provided that there is an 'fdtmap' entry in the image. For example:
+
+ $ binman ls -i image.bin
+ Name Image-pos Size Entry-type Offset Uncomp-size
+ ----------------------------------------------------------------------
+ main-section c00 section 0
+ u-boot 0 4 u-boot 0
+ section 5fc section 4
+ cbfs 100 400 cbfs 0
+ u-boot 138 4 u-boot 38
+ u-boot-dtb 180 108 u-boot-dtb 80 3b5
+ u-boot-dtb 500 1ff u-boot-dtb 400 3b5
+ fdtmap 6fc 381 fdtmap 6fc
+ image-header bf8 8 image-header bf8
+
+This shows the hierarchy of the image, the position, size and type of each
+entry, the offset of each entry within its parent and the uncompressed size if
+the entry is compressed.
+
+It is also possible to list just some files in an image, e.g.
+
+ $ binman ls -i image.bin section/cbfs
+ Name Image-pos Size Entry-type Offset Uncomp-size
+ --------------------------------------------------------------------
+ cbfs 100 400 cbfs 0
+ u-boot 138 4 u-boot 38
+ u-boot-dtb 180 108 u-boot-dtb 80 3b5
+
+or with wildcards:
+
+ $ binman ls -i image.bin "*cb*" "*head*"
+ Name Image-pos Size Entry-type Offset Uncomp-size
+ ----------------------------------------------------------------------
+ cbfs 100 400 cbfs 0
+ u-boot 138 4 u-boot 38
+ u-boot-dtb 180 108 u-boot-dtb 80 3b5
+ image-header bf8 8 image-header bf8
+
+
+Extracting files from images
+----------------------------
+
+You can extract files from an existing firmware image created by binman,
+provided that there is an 'fdtmap' entry in the image. For example:
+
+ $ binman extract -i image.bin section/cbfs/u-boot
+
+which will write the uncompressed contents of that entry to the file 'u-boot' in
+the current directory. You can also extract to a particular file, in this case
+u-boot.bin:
+
+ $ binman extract -i image.bin section/cbfs/u-boot -f u-boot.bin
+
+It is possible to extract all files into a destination directory, which will
+put files in subdirectories matching the entry hierarchy:
+
+ $ binman extract -i image.bin -O outdir
+
+or just a selection:
+
+ $ binman extract -i image.bin "*u-boot*" -O outdir
+
+
+Replacing files in an image
+---------------------------
+
+You can replace files in an existing firmware image created by binman, provided
+that there is an 'fdtmap' entry in the image. For example:
+
+ $ binman replace -i image.bin section/cbfs/u-boot
+
+which will write the contents of the file 'u-boot' from the current directory
+to the that entry, compressing if necessary. If the entry size changes, you must
+add the 'allow-repack' property to the original image before generating it (see
+above), otherwise you will get an error.
+
+You can also use a particular file, in this case u-boot.bin:
+
+ $ binman replace -i image.bin section/cbfs/u-boot -f u-boot.bin
+
+It is possible to replace all files from a source directory which uses the same
+hierarchy as the entries:
+
+ $ binman replace -i image.bin -I indir
+
+Files that are missing will generate a warning.
+
+You can also replace just a selection of entries:
+
+ $ binman replace -i image.bin "*u-boot*" -I indir
+
+
+Logging
+-------
+
+Binman normally operates silently unless there is an error, in which case it
+just displays the error. The -D/--debug option can be used to create a full
+backtrace when errors occur.
+
+Internally binman logs some output while it is running. This can be displayed
+by increasing the -v/--verbosity from the default of 1:
+
+ 0: silent
+ 1: warnings only
+ 2: notices (important messages)
+ 3: info about major operations
+ 4: detailed information about each operation
+ 5: debug (all output)
Hashing Entries
@@ -551,21 +696,35 @@
7. CheckEntries() - checks that the entries do not overlap, nor extend
outside the image.
-8. SetCalculatedProperties() - update any calculated properties in the device
+8. SetImagePos() - sets the image position of every entry. This is the absolute
+position 'image-pos', as opposed to 'offset' which is relative to the containing
+section. This must be done after all offsets are known, which is why it is quite
+late in the ordering.
+
+9. SetCalculatedProperties() - update any calculated properties in the device
tree. This sets the correct 'offset' and 'size' vaues, for example.
-9. ProcessEntryContents() - this calls Entry.ProcessContents() on each entry.
+10. ProcessEntryContents() - this calls Entry.ProcessContents() on each entry.
The default implementatoin does nothing. This can be overriden to adjust the
contents of an entry in some way. For example, it would be possible to create
an entry containing a hash of the contents of some other entries. At this
-stage the offset and size of entries should not be adjusted.
+stage the offset and size of entries should not be adjusted unless absolutely
+necessary, since it requires a repack (going back to PackEntries()).
-10. WriteSymbols() - write the value of symbols into the U-Boot SPL binary.
+11. ResetForPack() - if the ProcessEntryContents() step failed, in that an entry
+has changed its size, then there is no alternative but to go back to step 5 and
+try again, repacking the entries with the updated size. ResetForPack() removes
+the fixed offset/size values added by binman, so that the packing can start from
+scratch.
+
+12. WriteSymbols() - write the value of symbols into the U-Boot SPL binary.
See 'Access to binman entry offsets at run time' below for a description of
what happens in this stage.
-11. BuildImage() - builds the image and writes it to a file. This is the final
-step.
+13. BuildImage() - builds the image and writes it to a file
+
+14. WriteMap() - writes a text file containing a map of the image. This is the
+final step.
Automatic .dtsi inclusion
@@ -634,20 +793,27 @@
the device tree. These can be used by U-Boot at run-time to find the location
of each entry.
+Alternatively, an FDT map entry can be used to add a special FDT containing
+just the information about the image. This is preceded by a magic string so can
+be located anywhere in the image. An image header (typically at the start or end
+of the image) can be used to point to the FDT map. See fdtmap and image-header
+entries for more information.
+
Compression
-----------
Binman support compression for 'blob' entries (those of type 'blob' and
-derivatives). To enable this for an entry, add a 'compression' property:
+derivatives). To enable this for an entry, add a 'compress' property:
blob {
filename = "datafile";
- compression = "lz4";
+ compress = "lz4";
};
The entry will then contain the compressed data, using the 'lz4' compression
-algorithm. Currently this is the only one that is supported.
+algorithm. Currently this is the only one that is supported. The uncompressed
+size is written to the node in an 'uncomp-size' property, if -u is used.
@@ -691,15 +857,47 @@
typically for filenames.
+External tools
+--------------
+
+Binman can make use of external command-line tools to handle processing of
+entry contents or to generate entry contents. These tools are executed using
+the 'tools' module's Run() method. The tools generally must exist on the PATH,
+but the --toolpath option can be used to specify additional search paths to
+use. This option can be specified multiple times to add more than one path.
+
+
Code coverage
-------------
Binman is a critical tool and is designed to be very testable. Entry
-implementations target 100% test coverage. Run 'binman -T' to check this.
+implementations target 100% test coverage. Run 'binman test -T' to check this.
To enable Python test coverage on Debian-type distributions (e.g. Ubuntu):
- $ sudo apt-get install python-coverage python-pytest
+ $ sudo apt-get install python-coverage python3-coverage python-pytest
+
+
+Concurrent tests
+----------------
+
+Binman tries to run tests concurrently. This means that the tests make use of
+all available CPUs to run.
+
+ To enable this:
+
+ $ sudo apt-get install python-subunit python3-subunit
+
+Use '-P 1' to disable this. It is automatically disabled when code coverage is
+being used (-T) since they are incompatible.
+
+
+Debugging tests
+---------------
+
+Sometimes when debugging tests it is useful to keep the input and output
+directories so they can be examined later. Use -X or --test-preserve-dirs for
+this.
Advanced Features / Technical docs
@@ -774,13 +972,12 @@
- Use of-platdata to make the information available to code that is unable
to use device tree (such as a very small SPL image)
- Allow easy building of images by specifying just the board name
-- Produce a full Python binding for libfdt (for upstream). This is nearing
- completion but some work remains
-- Add an option to decode an image into the constituent binaries
- Support building an image for a board (-b) more completely, with a
configurable build directory
-- Consider making binman work with buildman, although if it is used in the
- Makefile, this will be automatic
+- Support adding FITs to an image
+- Support for ARM Trusted Firmware (ATF)
+- Detect invalid properties in nodes
+- Sort the fdtmap by offset
--
Simon Glass <sjg@chromium.org>
diff --git a/tools/binman/README.entries b/tools/binman/README.entries
index 9fc2f83..0f0e367 100644
--- a/tools/binman/README.entries
+++ b/tools/binman/README.entries
@@ -60,6 +60,158 @@
+Entry: cbfs: Entry containing a Coreboot Filesystem (CBFS)
+----------------------------------------------------------
+
+A CBFS provides a way to group files into a group. It has a simple directory
+structure and allows the position of individual files to be set, since it is
+designed to support execute-in-place in an x86 SPI-flash device. Where XIP
+is not used, it supports compression and storing ELF files.
+
+CBFS is used by coreboot as its way of orgnanising SPI-flash contents.
+
+The contents of the CBFS are defined by subnodes of the cbfs entry, e.g.:
+
+ cbfs {
+ size = <0x100000>;
+ u-boot {
+ cbfs-type = "raw";
+ };
+ u-boot-dtb {
+ cbfs-type = "raw";
+ };
+ };
+
+This creates a CBFS 1MB in size two files in it: u-boot.bin and u-boot.dtb.
+Note that the size is required since binman does not support calculating it.
+The contents of each entry is just what binman would normally provide if it
+were not a CBFS node. A blob type can be used to import arbitrary files as
+with the second subnode below:
+
+ cbfs {
+ size = <0x100000>;
+ u-boot {
+ cbfs-name = "BOOT";
+ cbfs-type = "raw";
+ };
+
+ dtb {
+ type = "blob";
+ filename = "u-boot.dtb";
+ cbfs-type = "raw";
+ cbfs-compress = "lz4";
+ cbfs-offset = <0x100000>;
+ };
+ };
+
+This creates a CBFS 1MB in size with u-boot.bin (named "BOOT") and
+u-boot.dtb (named "dtb") and compressed with the lz4 algorithm.
+
+
+Properties supported in the top-level CBFS node:
+
+cbfs-arch:
+ Defaults to "x86", but you can specify the architecture if needed.
+
+
+Properties supported in the CBFS entry subnodes:
+
+cbfs-name:
+ This is the name of the file created in CBFS. It defaults to the entry
+ name (which is the node name), but you can override it with this
+ property.
+
+cbfs-type:
+ This is the CBFS file type. The following are supported:
+
+ raw:
+ This is a 'raw' file, although compression is supported. It can be
+ used to store any file in CBFS.
+
+ stage:
+ This is an ELF file that has been loaded (i.e. mapped to memory), so
+ appears in the CBFS as a flat binary. The input file must be an ELF
+ image, for example this puts "u-boot" (the ELF image) into a 'stage'
+ entry:
+
+ cbfs {
+ size = <0x100000>;
+ u-boot-elf {
+ cbfs-name = "BOOT";
+ cbfs-type = "stage";
+ };
+ };
+
+ You can use your own ELF file with something like:
+
+ cbfs {
+ size = <0x100000>;
+ something {
+ type = "blob";
+ filename = "cbfs-stage.elf";
+ cbfs-type = "stage";
+ };
+ };
+
+ As mentioned, the file is converted to a flat binary, so it is
+ equivalent to adding "u-boot.bin", for example, but with the load and
+ start addresses specified by the ELF. At present there is no option
+ to add a flat binary with a load/start address, similar to the
+ 'add-flat-binary' option in cbfstool.
+
+cbfs-offset:
+ This is the offset of the file's data within the CBFS. It is used to
+ specify where the file should be placed in cases where a fixed position
+ is needed. Typical uses are for code which is not relocatable and must
+ execute in-place from a particular address. This works because SPI flash
+ is generally mapped into memory on x86 devices. The file header is
+ placed before this offset so that the data start lines up exactly with
+ the chosen offset. If this property is not provided, then the file is
+ placed in the next available spot.
+
+The current implementation supports only a subset of CBFS features. It does
+not support other file types (e.g. payload), adding multiple files (like the
+'files' entry with a pattern supported by binman), putting files at a
+particular offset in the CBFS and a few other things.
+
+Of course binman can create images containing multiple CBFSs, simply by
+defining these in the binman config:
+
+
+ binman {
+ size = <0x800000>;
+ cbfs {
+ offset = <0x100000>;
+ size = <0x100000>;
+ u-boot {
+ cbfs-type = "raw";
+ };
+ u-boot-dtb {
+ cbfs-type = "raw";
+ };
+ };
+
+ cbfs2 {
+ offset = <0x700000>;
+ size = <0x100000>;
+ u-boot {
+ cbfs-type = "raw";
+ };
+ u-boot-dtb {
+ cbfs-type = "raw";
+ };
+ image {
+ type = "blob";
+ filename = "image.jpg";
+ };
+ };
+ };
+
+This creates an 8MB image with two CBFSs, one at offset 1MB, one at 7MB,
+both of size 1MB.
+
+
+
Entry: cros-ec-rw: A blob entry which contains a Chromium OS read-write EC image
--------------------------------------------------------------------------------
@@ -71,6 +223,50 @@
+Entry: fdtmap: An entry which contains an FDT map
+-------------------------------------------------
+
+Properties / Entry arguments:
+ None
+
+An FDT map is just a header followed by an FDT containing a list of all the
+entries in the image. The root node corresponds to the image node in the
+original FDT, and an image-name property indicates the image name in that
+original tree.
+
+The header is the string _FDTMAP_ followed by 8 unused bytes.
+
+When used, this entry will be populated with an FDT map which reflects the
+entries in the current image. Hierarchy is preserved, and all offsets and
+sizes are included.
+
+Note that the -u option must be provided to ensure that binman updates the
+FDT with the position of each entry.
+
+Example output for a simple image with U-Boot and an FDT map:
+
+/ {
+ image-name = "binman";
+ size = <0x00000112>;
+ image-pos = <0x00000000>;
+ offset = <0x00000000>;
+ u-boot {
+ size = <0x00000004>;
+ image-pos = <0x00000000>;
+ offset = <0x00000000>;
+ };
+ fdtmap {
+ size = <0x0000010e>;
+ image-pos = <0x00000004>;
+ offset = <0x00000004>;
+ };
+};
+
+If allow-repack is used then 'orig-offset' and 'orig-size' properties are
+added as necessary. See the binman README.
+
+
+
Entry: files: Entry containing a set of files
---------------------------------------------
@@ -118,7 +314,8 @@
When used, this entry will be populated with an FMAP which reflects the
entries in the current image. Note that any hierarchy is squashed, since
-FMAP does not support this.
+FMAP does not support this. Also, CBFS entries appear as a single entry -
+the sub-entries are ignored.
@@ -141,6 +338,25 @@
+Entry: image-header: An entry which contains a pointer to the FDT map
+---------------------------------------------------------------------
+
+Properties / Entry arguments:
+ location: Location of header ("start" or "end" of image). This is
+ optional. If omitted then the entry must have an offset property.
+
+This adds an 8-byte entry to the start or end of the image, pointing to the
+location of the FDT map. The format is a magic number followed by an offset
+from the start or end of the image, in twos-compliment format.
+
+This entry must be in the top-level part of the image.
+
+NOTE: If the location is at the start/end, you will probably need to specify
+sort-by-offset for the image, unless you actually put the image header
+first/last in the entry list.
+
+
+
Entry: intel-cmc: Entry containing an Intel Chipset Micro Code (CMC) file
-------------------------------------------------------------------------
@@ -192,6 +408,34 @@
+Entry: intel-ifwi: Entry containing an Intel Integrated Firmware Image (IFWI) file
+----------------------------------------------------------------------------------
+
+Properties / Entry arguments:
+ - filename: Filename of file to read into entry. This is either the
+ IFWI file itself, or a file that can be converted into one using a
+ tool
+ - convert-fit: If present this indicates that the ifwitool should be
+ used to convert the provided file into a IFWI.
+
+This file contains code and data used by the SoC that is required to make
+it work. It includes U-Boot TPL, microcode, things related to the CSE
+(Converged Security Engine, the microcontroller that loads all the firmware)
+and other items beyond the wit of man.
+
+A typical filename is 'ifwi.bin' for an IFWI file, or 'fitimage.bin' for a
+file that will be converted to an IFWI.
+
+The position of this entry is generally set by the intel-descriptor entry.
+
+The contents of the IFWI are specified by the subnodes of the IFWI node.
+Each subnode describes an entry which is placed into the IFWFI with a given
+sub-partition (and optional entry name).
+
+See README.x86 for information about x86 binary blobs.
+
+
+
Entry: intel-me: Entry containing an Intel Management Engine (ME) file
----------------------------------------------------------------------
@@ -206,6 +450,8 @@
A typical filename is 'me.bin'.
+The position of this entry is generally set by the intel-descriptor entry.
+
See README.x86 for information about x86 binary blobs.
@@ -224,6 +470,20 @@
+Entry: intel-refcode: Entry containing an Intel Reference Code file
+-------------------------------------------------------------------
+
+Properties / Entry arguments:
+ - filename: Filename of file to read into entry
+
+This file contains code for setting up the platform on some Intel systems.
+This is executed by U-Boot when needed early during startup. A typical
+filename is 'refcode.bin'.
+
+See README.x86 for information about x86 binary blobs.
+
+
+
Entry: intel-vbt: Entry containing an Intel Video BIOS Table (VBT) file
-----------------------------------------------------------------------
@@ -268,16 +528,21 @@
-------------------------------------------------
Properties / Entry arguments: (see binman README for more information)
- - size: Size of section in bytes
- - align-size: Align size to a particular power of two
- - pad-before: Add padding before the entry
- - pad-after: Add padding after the entry
- - pad-byte: Pad byte to use when padding
- - sort-by-offset: Reorder the entries by offset
- - end-at-4gb: Used to build an x86 ROM which ends at 4GB (2^32)
- - name-prefix: Adds a prefix to the name of every entry in the section
+ pad-byte: Pad byte to use when padding
+ sort-by-offset: True if entries should be sorted by offset, False if
+ they must be in-order in the device tree description
+ end-at-4gb: Used to build an x86 ROM which ends at 4GB (2^32)
+ skip-at-start: Number of bytes before the first entry starts. These
+ effectively adjust the starting offset of entries. For example,
+ if this is 16, then the first entry would start at 16. An entry
+ with offset = 20 would in fact be written at offset 4 in the image
+ file, since the first 16 bytes are skipped when writing.
+ name-prefix: Adds a prefix to the name of every entry in the section
when writing out the map
+Since a section is also an entry, it inherits all the properies of entries
+too.
+
A section is an entry which can contain other entries, thus allowing
hierarchical images to be created. See 'Sections and hierarchical images'
in the binman README for more information.
@@ -296,6 +561,8 @@
that contains the string to place in the entry
<xxx> (actual name is the value of text-label): contains the string to
place in the entry.
+ <text>: The text to place in the entry (overrides the above mechanism).
+ This is useful when the text is constant.
Example node:
@@ -318,6 +585,13 @@
message = "a message directly in the node"
};
+or just:
+
+ text {
+ size = <8>;
+ text = "some text directly in the node"
+ };
+
The text is not itself nul-terminated. This can be achieved, if required,
by setting the size of the entry to something larger than the text.
@@ -471,7 +745,7 @@
-------------------------------------------
Properties / Entry arguments:
- - filename: Filename of SPL u-boot (default 'spl/u-boot')
+ - filename: Filename of SPL u-boot (default 'spl/u-boot-spl')
This is the U-Boot SPL ELF image. It does not include a device tree but can
be relocated to any address for execution.
@@ -549,6 +823,17 @@
+Entry: u-boot-tpl-elf: U-Boot TPL ELF image
+-------------------------------------------
+
+Properties / Entry arguments:
+ - filename: Filename of TPL u-boot (default 'tpl/u-boot-tpl')
+
+This is the U-Boot TPL ELF image. It does not include a device tree but can
+be relocated to any address for execution.
+
+
+
Entry: u-boot-tpl-with-ucode-ptr: U-Boot TPL with embedded microcode pointer
----------------------------------------------------------------------------
@@ -627,6 +912,7 @@
------------------------------------------------------------------------
Properties / Entry arguments:
+ - content: List of phandles to entries to sign
- keydir: Directory containing the public keys to use
- keyblock: Name of the key file to use (inside keydir)
- signprivate: Name of provide key file to use (inside keydir)
diff --git a/tools/binman/binman.py b/tools/binman/binman.py
index 439908e..8bd5868 100755
--- a/tools/binman/binman.py
+++ b/tools/binman/binman.py
@@ -9,23 +9,34 @@
"""See README for more information"""
+from __future__ import print_function
+
+from distutils.sysconfig import get_python_lib
import glob
import multiprocessing
import os
+import site
import sys
import traceback
import unittest
-# Bring in the patman and dtoc libraries
+# Bring in the patman and dtoc libraries (but don't override the first path
+# in PYTHONPATH)
our_path = os.path.dirname(os.path.realpath(__file__))
for dirname in ['../patman', '../dtoc', '..', '../concurrencytest']:
- sys.path.insert(0, os.path.join(our_path, dirname))
+ sys.path.insert(2, os.path.join(our_path, dirname))
# Bring in the libfdt module
-sys.path.insert(0, 'scripts/dtc/pylibfdt')
-sys.path.insert(0, os.path.join(our_path,
+sys.path.insert(2, 'scripts/dtc/pylibfdt')
+sys.path.insert(2, os.path.join(our_path,
'../../build-sandbox_spl/scripts/dtc/pylibfdt'))
+# When running under python-coverage on Ubuntu 16.04, the dist-packages
+# directories are dropped from the python path. Add them in so that we can find
+# the elffile module. We could use site.getsitepackages() here but unfortunately
+# that is not available in a virtualenv.
+sys.path.append(get_python_lib())
+
import cmdline
import command
use_concurrent = True
@@ -36,15 +47,23 @@
import control
import test_util
-def RunTests(debug, processes, args):
+def RunTests(debug, verbosity, processes, test_preserve_dirs, args, toolpath):
"""Run the functional tests and any embedded doctests
Args:
debug: True to enable debugging, which shows a full stack trace on error
- args: List of positional args provided to binman. This can hold a test
- name to execute (as in 'binman -t testSections', for example)
+ verbosity: Verbosity level to use
+ test_preserve_dirs: True to preserve the input directory used by tests
+ so that it can be examined afterwards (only useful for debugging
+ tests). If a single test is selected (in args[0]) it also preserves
+ the output directory for this test. Both directories are displayed
+ on the command line.
processes: Number of processes to use to run tests (None=same as #CPUs)
+ args: List of positional args provided to binman. This can hold a test
+ name to execute (as in 'binman test testSections', for example)
+ toolpath: List of paths to use for tools
"""
+ import cbfs_util_test
import elf_test
import entry_test
import fdt_test
@@ -61,8 +80,11 @@
sys.argv = [sys.argv[0]]
if debug:
sys.argv.append('-D')
- if debug:
- sys.argv.append('-D')
+ if verbosity:
+ sys.argv.append('-v%d' % verbosity)
+ if toolpath:
+ for path in toolpath:
+ sys.argv += ['--toolpath', path]
# Run the entry tests first ,since these need to be the first to import the
# 'entry' module.
@@ -70,7 +92,14 @@
suite = unittest.TestSuite()
loader = unittest.TestLoader()
for module in (entry_test.TestEntry, ftest.TestFunctional, fdt_test.TestFdt,
- elf_test.TestElf, image_test.TestImage):
+ elf_test.TestElf, image_test.TestImage,
+ cbfs_util_test.TestCbfs):
+ # Test the test module about our arguments, if it is interested
+ if hasattr(module, 'setup_test_args'):
+ setup_test_args = getattr(module, 'setup_test_args')
+ setup_test_args(preserve_indir=test_preserve_dirs,
+ preserve_outdirs=test_preserve_dirs and test_name is not None,
+ toolpath=toolpath, verbosity=verbosity)
if test_name:
try:
suite.addTests(loader.loadTestsFromName(test_name, module))
@@ -85,14 +114,31 @@
else:
suite.run(result)
- print result
+ # Remove errors which just indicate a missing test. Since Python v3.5 If an
+ # ImportError or AttributeError occurs while traversing name then a
+ # synthetic test that raises that error when run will be returned. These
+ # errors are included in the errors accumulated by result.errors.
+ if test_name:
+ errors = []
+ for test, err in result.errors:
+ if ("has no attribute '%s'" % test_name) not in err:
+ errors.append((test, err))
+ result.testsRun -= 1
+ result.errors = errors
+
+ print(result)
for test, err in result.errors:
- print test.id(), err
+ print(test.id(), err)
for test, err in result.failures:
- print err, result.failures
+ print(err, result.failures)
+ if result.skipped:
+ print('%d binman test%s SKIPPED:' %
+ (len(result.skipped), 's' if len(result.skipped) > 1 else ''))
+ for skip_info in result.skipped:
+ print('%s: %s' % (skip_info[0], skip_info[1]))
if result.errors or result.failures:
- print 'binman tests FAILED'
- return 1
+ print('binman tests FAILED')
+ return 1
return 0
def GetEntryModules(include_testing=True):
@@ -113,45 +159,44 @@
for item in glob_list if '_testing' not in item])
test_util.RunTestCoverage('tools/binman/binman.py', None,
['*test*', '*binman.py', 'tools/patman/*', 'tools/dtoc/*'],
- options.build_dir, all_set)
+ args.build_dir, all_set)
-def RunBinman(options, args):
+def RunBinman(args):
"""Main entry point to binman once arguments are parsed
Args:
- options: Command-line options
- args: Non-option arguments
+ args: Command line arguments Namespace object
"""
ret_code = 0
- # For testing: This enables full exception traces.
- #options.debug = True
-
- if not options.debug:
+ if not args.debug:
sys.tracebacklimit = 0
- if options.test:
- ret_code = RunTests(options.debug, options.processes, args[1:])
+ if args.cmd == 'test':
+ if args.test_coverage:
+ RunTestCoverage()
+ else:
+ ret_code = RunTests(args.debug, args.verbosity, args.processes,
+ args.test_preserve_dirs, args.tests,
+ args.toolpath)
- elif options.test_coverage:
- RunTestCoverage()
-
- elif options.entry_docs:
+ elif args.cmd == 'entry-docs':
control.WriteEntryDocs(GetEntryModules())
else:
try:
- ret_code = control.Binman(options, args)
+ ret_code = control.Binman(args)
except Exception as e:
- print 'binman: %s' % e
- if options.debug:
- print
+ print('binman: %s' % e)
+ if args.debug:
+ print()
traceback.print_exc()
ret_code = 1
return ret_code
if __name__ == "__main__":
- (options, args) = cmdline.ParseArgs(sys.argv)
- ret_code = RunBinman(options, args)
+ args = cmdline.ParseArgs(sys.argv[1:])
+
+ ret_code = RunBinman(args)
sys.exit(ret_code)
diff --git a/tools/binman/bsection.py b/tools/binman/bsection.py
deleted file mode 100644
index 0ba542e..0000000
--- a/tools/binman/bsection.py
+++ /dev/null
@@ -1,465 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-# Copyright (c) 2018 Google, Inc
-# Written by Simon Glass <sjg@chromium.org>
-#
-# Base class for sections (collections of entries)
-#
-
-from __future__ import print_function
-
-from collections import OrderedDict
-from sets import Set
-import sys
-
-import fdt_util
-import re
-import state
-import tools
-
-class Section(object):
- """A section which contains multiple entries
-
- A section represents a collection of entries. There must be one or more
- sections in an image. Sections are used to group entries together.
-
- Attributes:
- _node: Node object that contains the section definition in device tree
- _parent_section: Parent Section object which created this Section
- _size: Section size in bytes, or None if not known yet
- _align_size: Section size alignment, or None
- _pad_before: Number of bytes before the first entry starts. This
- effectively changes the place where entry offset 0 starts
- _pad_after: Number of bytes after the last entry ends. The last
- entry will finish on or before this boundary
- _pad_byte: Byte to use to pad the section where there is no entry
- _sort: True if entries should be sorted by offset, False if they
- must be in-order in the device tree description
- _skip_at_start: Number of bytes before the first entry starts. These
- effectively adjust the starting offset of entries. For example,
- if _pad_before is 16, then the first entry would start at 16.
- An entry with offset = 20 would in fact be written at offset 4
- in the image file.
- _end_4gb: Indicates that the section ends at the 4GB boundary. This is
- used for x86 images, which want to use offsets such that a memory
- address (like 0xff800000) is the first entry offset. This causes
- _skip_at_start to be set to the starting memory address.
- _name_prefix: Prefix to add to the name of all entries within this
- section
- _entries: OrderedDict() of entries
- """
- def __init__(self, name, parent_section, node, image, test=False):
- global entry
- global Entry
- import entry
- from entry import Entry
-
- self._parent_section = parent_section
- self._name = name
- self._node = node
- self._image = image
- self._offset = None
- self._size = None
- self._align_size = None
- self._pad_before = 0
- self._pad_after = 0
- self._pad_byte = 0
- self._sort = False
- self._skip_at_start = None
- self._end_4gb = False
- self._name_prefix = ''
- self._entries = OrderedDict()
- self._image_pos = None
- if not test:
- self._ReadNode()
- self._ReadEntries()
-
- def _ReadNode(self):
- """Read properties from the section node"""
- self._offset = fdt_util.GetInt(self._node, 'offset')
- self._size = fdt_util.GetInt(self._node, 'size')
- self._align_size = fdt_util.GetInt(self._node, 'align-size')
- if tools.NotPowerOfTwo(self._align_size):
- self._Raise("Alignment size %s must be a power of two" %
- self._align_size)
- self._pad_before = fdt_util.GetInt(self._node, 'pad-before', 0)
- self._pad_after = fdt_util.GetInt(self._node, 'pad-after', 0)
- self._pad_byte = fdt_util.GetInt(self._node, 'pad-byte', 0)
- self._sort = fdt_util.GetBool(self._node, 'sort-by-offset')
- self._end_4gb = fdt_util.GetBool(self._node, 'end-at-4gb')
- self._skip_at_start = fdt_util.GetInt(self._node, 'skip-at-start')
- if self._end_4gb:
- if not self._size:
- self._Raise("Section size must be provided when using end-at-4gb")
- if self._skip_at_start is not None:
- self._Raise("Provide either 'end-at-4gb' or 'skip-at-start'")
- else:
- self._skip_at_start = 0x100000000 - self._size
- else:
- if self._skip_at_start is None:
- self._skip_at_start = 0
- self._name_prefix = fdt_util.GetString(self._node, 'name-prefix')
-
- def _ReadEntries(self):
- for node in self._node.subnodes:
- if node.name == 'hash':
- continue
- entry = Entry.Create(self, node)
- entry.SetPrefix(self._name_prefix)
- self._entries[node.name] = entry
-
- def GetFdtSet(self):
- """Get the set of device tree files used by this image"""
- fdt_set = Set()
- for entry in self._entries.values():
- fdt_set.update(entry.GetFdtSet())
- return fdt_set
-
- def SetOffset(self, offset):
- self._offset = offset
-
- def ExpandEntries(self):
- for entry in self._entries.values():
- entry.ExpandEntries()
-
- def AddMissingProperties(self):
- """Add new properties to the device tree as needed for this entry"""
- for prop in ['offset', 'size', 'image-pos']:
- if not prop in self._node.props:
- state.AddZeroProp(self._node, prop)
- state.CheckAddHashProp(self._node)
- for entry in self._entries.values():
- entry.AddMissingProperties()
-
- def SetCalculatedProperties(self):
- state.SetInt(self._node, 'offset', self._offset or 0)
- state.SetInt(self._node, 'size', self._size)
- image_pos = self._image_pos
- if self._parent_section:
- image_pos -= self._parent_section.GetRootSkipAtStart()
- state.SetInt(self._node, 'image-pos', image_pos)
- for entry in self._entries.values():
- entry.SetCalculatedProperties()
-
- def ProcessFdt(self, fdt):
- todo = self._entries.values()
- for passnum in range(3):
- next_todo = []
- for entry in todo:
- if not entry.ProcessFdt(fdt):
- next_todo.append(entry)
- todo = next_todo
- if not todo:
- break
- if todo:
- self._Raise('Internal error: Could not complete processing of Fdt: '
- 'remaining %s' % todo)
- return True
-
- def CheckSize(self):
- """Check that the section contents does not exceed its size, etc."""
- contents_size = 0
- for entry in self._entries.values():
- contents_size = max(contents_size, entry.offset + entry.size)
-
- contents_size -= self._skip_at_start
-
- size = self._size
- if not size:
- size = self._pad_before + contents_size + self._pad_after
- size = tools.Align(size, self._align_size)
-
- if self._size and contents_size > self._size:
- self._Raise("contents size %#x (%d) exceeds section size %#x (%d)" %
- (contents_size, contents_size, self._size, self._size))
- if not self._size:
- self._size = size
- if self._size != tools.Align(self._size, self._align_size):
- self._Raise("Size %#x (%d) does not match align-size %#x (%d)" %
- (self._size, self._size, self._align_size, self._align_size))
- return size
-
- def _Raise(self, msg):
- """Raises an error for this section
-
- Args:
- msg: Error message to use in the raise string
- Raises:
- ValueError()
- """
- raise ValueError("Section '%s': %s" % (self._node.path, msg))
-
- def GetPath(self):
- """Get the path of an image (in the FDT)
-
- Returns:
- Full path of the node for this image
- """
- return self._node.path
-
- def FindEntryType(self, etype):
- """Find an entry type in the section
-
- Args:
- etype: Entry type to find
- Returns:
- entry matching that type, or None if not found
- """
- for entry in self._entries.values():
- if entry.etype == etype:
- return entry
- return None
-
- def GetEntryContents(self):
- """Call ObtainContents() for each entry
-
- This calls each entry's ObtainContents() a few times until they all
- return True. We stop calling an entry's function once it returns
- True. This allows the contents of one entry to depend on another.
-
- After 3 rounds we give up since it's likely an error.
- """
- todo = self._entries.values()
- for passnum in range(3):
- next_todo = []
- for entry in todo:
- if not entry.ObtainContents():
- next_todo.append(entry)
- todo = next_todo
- if not todo:
- break
- if todo:
- self._Raise('Internal error: Could not complete processing of '
- 'contents: remaining %s' % todo)
- return True
-
- def _SetEntryOffsetSize(self, name, offset, size):
- """Set the offset and size of an entry
-
- Args:
- name: Entry name to update
- offset: New offset
- size: New size
- """
- entry = self._entries.get(name)
- if not entry:
- self._Raise("Unable to set offset/size for unknown entry '%s'" %
- name)
- entry.SetOffsetSize(self._skip_at_start + offset, size)
-
- def GetEntryOffsets(self):
- """Handle entries that want to set the offset/size of other entries
-
- This calls each entry's GetOffsets() method. If it returns a list
- of entries to update, it updates them.
- """
- for entry in self._entries.values():
- offset_dict = entry.GetOffsets()
- for name, info in offset_dict.iteritems():
- self._SetEntryOffsetSize(name, *info)
-
- def PackEntries(self):
- """Pack all entries into the section"""
- offset = self._skip_at_start
- for entry in self._entries.values():
- offset = entry.Pack(offset)
- self._size = self.CheckSize()
-
- def _SortEntries(self):
- """Sort entries by offset"""
- entries = sorted(self._entries.values(), key=lambda entry: entry.offset)
- self._entries.clear()
- for entry in entries:
- self._entries[entry._node.name] = entry
-
- def _ExpandEntries(self):
- """Expand any entries that are permitted to"""
- exp_entry = None
- for entry in self._entries.values():
- if exp_entry:
- exp_entry.ExpandToLimit(entry.offset)
- exp_entry = None
- if entry.expand_size:
- exp_entry = entry
- if exp_entry:
- exp_entry.ExpandToLimit(self._size)
-
- def CheckEntries(self):
- """Check that entries do not overlap or extend outside the section
-
- This also sorts entries, if needed and expands
- """
- if self._sort:
- self._SortEntries()
- self._ExpandEntries()
- offset = 0
- prev_name = 'None'
- for entry in self._entries.values():
- entry.CheckOffset()
- if (entry.offset < self._skip_at_start or
- entry.offset + entry.size > self._skip_at_start + self._size):
- entry.Raise("Offset %#x (%d) is outside the section starting "
- "at %#x (%d)" %
- (entry.offset, entry.offset, self._skip_at_start,
- self._skip_at_start))
- if entry.offset < offset:
- entry.Raise("Offset %#x (%d) overlaps with previous entry '%s' "
- "ending at %#x (%d)" %
- (entry.offset, entry.offset, prev_name, offset, offset))
- offset = entry.offset + entry.size
- prev_name = entry.GetPath()
-
- def SetImagePos(self, image_pos):
- self._image_pos = image_pos
- for entry in self._entries.values():
- entry.SetImagePos(image_pos)
-
- def ProcessEntryContents(self):
- """Call the ProcessContents() method for each entry
-
- This is intended to adjust the contents as needed by the entry type.
- """
- for entry in self._entries.values():
- entry.ProcessContents()
-
- def WriteSymbols(self):
- """Write symbol values into binary files for access at run time"""
- for entry in self._entries.values():
- entry.WriteSymbols(self)
-
- def BuildSection(self, fd, base_offset):
- """Write the section to a file"""
- fd.seek(base_offset)
- fd.write(self.GetData())
-
- def GetData(self):
- """Get the contents of the section"""
- section_data = chr(self._pad_byte) * self._size
-
- for entry in self._entries.values():
- data = entry.GetData()
- base = self._pad_before + entry.offset - self._skip_at_start
- section_data = (section_data[:base] + data +
- section_data[base + len(data):])
- return section_data
-
- def LookupSymbol(self, sym_name, optional, msg):
- """Look up a symbol in an ELF file
-
- Looks up a symbol in an ELF file. Only entry types which come from an
- ELF image can be used by this function.
-
- At present the only entry property supported is offset.
-
- Args:
- sym_name: Symbol name in the ELF file to look up in the format
- _binman_<entry>_prop_<property> where <entry> is the name of
- the entry and <property> is the property to find (e.g.
- _binman_u_boot_prop_offset). As a special case, you can append
- _any to <entry> to have it search for any matching entry. E.g.
- _binman_u_boot_any_prop_offset will match entries called u-boot,
- u-boot-img and u-boot-nodtb)
- optional: True if the symbol is optional. If False this function
- will raise if the symbol is not found
- msg: Message to display if an error occurs
-
- Returns:
- Value that should be assigned to that symbol, or None if it was
- optional and not found
-
- Raises:
- ValueError if the symbol is invalid or not found, or references a
- property which is not supported
- """
- m = re.match(r'^_binman_(\w+)_prop_(\w+)$', sym_name)
- if not m:
- raise ValueError("%s: Symbol '%s' has invalid format" %
- (msg, sym_name))
- entry_name, prop_name = m.groups()
- entry_name = entry_name.replace('_', '-')
- entry = self._entries.get(entry_name)
- if not entry:
- if entry_name.endswith('-any'):
- root = entry_name[:-4]
- for name in self._entries:
- if name.startswith(root):
- rest = name[len(root):]
- if rest in ['', '-img', '-nodtb']:
- entry = self._entries[name]
- if not entry:
- err = ("%s: Entry '%s' not found in list (%s)" %
- (msg, entry_name, ','.join(self._entries.keys())))
- if optional:
- print('Warning: %s' % err, file=sys.stderr)
- return None
- raise ValueError(err)
- if prop_name == 'offset':
- return entry.offset
- elif prop_name == 'image_pos':
- return entry.image_pos
- else:
- raise ValueError("%s: No such property '%s'" % (msg, prop_name))
-
- def GetEntries(self):
- """Get the number of entries in a section
-
- Returns:
- Number of entries in a section
- """
- return self._entries
-
- def GetSize(self):
- """Get the size of a section in bytes
-
- This is only meaningful if the section has a pre-defined size, or the
- entries within it have been packed, so that the size has been
- calculated.
-
- Returns:
- Entry size in bytes
- """
- return self._size
-
- def WriteMap(self, fd, indent):
- """Write a map of the section to a .map file
-
- Args:
- fd: File to write the map to
- """
- Entry.WriteMapLine(fd, indent, self._name, self._offset or 0,
- self._size, self._image_pos)
- for entry in self._entries.values():
- entry.WriteMap(fd, indent + 1)
-
- def GetContentsByPhandle(self, phandle, source_entry):
- """Get the data contents of an entry specified by a phandle
-
- This uses a phandle to look up a node and and find the entry
- associated with it. Then it returnst he contents of that entry.
-
- Args:
- phandle: Phandle to look up (integer)
- source_entry: Entry containing that phandle (used for error
- reporting)
-
- Returns:
- data from associated entry (as a string), or None if not found
- """
- node = self._node.GetFdt().LookupPhandle(phandle)
- if not node:
- source_entry.Raise("Cannot find node for phandle %d" % phandle)
- for entry in self._entries.values():
- if entry._node == node:
- return entry.GetData()
- source_entry.Raise("Cannot find entry for node '%s'" % node.name)
-
- def ExpandSize(self, size):
- if size != self._size:
- self._size = size
-
- def GetRootSkipAtStart(self):
- if self._parent_section:
- return self._parent_section.GetRootSkipAtStart()
- return self._skip_at_start
-
- def GetImageSize(self):
- return self._image._size
diff --git a/tools/binman/cbfs_util.py b/tools/binman/cbfs_util.py
new file mode 100644
index 0000000..99d7787
--- /dev/null
+++ b/tools/binman/cbfs_util.py
@@ -0,0 +1,889 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright 2019 Google LLC
+# Written by Simon Glass <sjg@chromium.org>
+
+"""Support for coreboot's CBFS format
+
+CBFS supports a header followed by a number of files, generally targeted at SPI
+flash.
+
+The format is somewhat defined by documentation in the coreboot tree although
+it is necessary to rely on the C structures and source code (mostly cbfstool)
+to fully understand it.
+
+Currently supported: raw and stage types with compression, padding empty areas
+ with empty files, fixed-offset files
+"""
+
+from __future__ import print_function
+
+from collections import OrderedDict
+import io
+import struct
+import sys
+
+import command
+import elf
+import tools
+
+# Set to True to enable printing output while working
+DEBUG = False
+
+# Set to True to enable output from running cbfstool for debugging
+VERBOSE = False
+
+# The master header, at the start of the CBFS
+HEADER_FORMAT = '>IIIIIIII'
+HEADER_LEN = 0x20
+HEADER_MAGIC = 0x4f524243
+HEADER_VERSION1 = 0x31313131
+HEADER_VERSION2 = 0x31313132
+
+# The file header, at the start of each file in the CBFS
+FILE_HEADER_FORMAT = b'>8sIIII'
+FILE_HEADER_LEN = 0x18
+FILE_MAGIC = b'LARCHIVE'
+FILENAME_ALIGN = 16 # Filename lengths are aligned to this
+
+# A stage header containing information about 'stage' files
+# Yes this is correct: this header is in litte-endian format
+STAGE_FORMAT = '<IQQII'
+STAGE_LEN = 0x1c
+
+# An attribute describring the compression used in a file
+ATTR_COMPRESSION_FORMAT = '>IIII'
+ATTR_COMPRESSION_LEN = 0x10
+
+# Attribute tags
+# Depending on how the header was initialised, it may be backed with 0x00 or
+# 0xff. Support both.
+FILE_ATTR_TAG_UNUSED = 0
+FILE_ATTR_TAG_UNUSED2 = 0xffffffff
+FILE_ATTR_TAG_COMPRESSION = 0x42435a4c
+FILE_ATTR_TAG_HASH = 0x68736148
+FILE_ATTR_TAG_POSITION = 0x42435350 # PSCB
+FILE_ATTR_TAG_ALIGNMENT = 0x42434c41 # ALCB
+FILE_ATTR_TAG_PADDING = 0x47444150 # PDNG
+
+# This is 'the size of bootblock reserved in firmware image (cbfs.txt)'
+# Not much more info is available, but we set it to 4, due to this comment in
+# cbfstool.c:
+# This causes 4 bytes to be left out at the end of the image, for two reasons:
+# 1. The cbfs master header pointer resides there
+# 2. Ssme cbfs implementations assume that an image that resides below 4GB has
+# a bootblock and get confused when the end of the image is at 4GB == 0.
+MIN_BOOTBLOCK_SIZE = 4
+
+# Files start aligned to this boundary in the CBFS
+ENTRY_ALIGN = 0x40
+
+# CBFSs must declare an architecture since much of the logic is designed with
+# x86 in mind. The effect of setting this value is not well documented, but in
+# general x86 is used and this makes use of a boot block and an image that ends
+# at the end of 32-bit address space.
+ARCHITECTURE_UNKNOWN = 0xffffffff
+ARCHITECTURE_X86 = 0x00000001
+ARCHITECTURE_ARM = 0x00000010
+ARCHITECTURE_AARCH64 = 0x0000aa64
+ARCHITECTURE_MIPS = 0x00000100
+ARCHITECTURE_RISCV = 0xc001d0de
+ARCHITECTURE_PPC64 = 0x407570ff
+
+ARCH_NAMES = {
+ ARCHITECTURE_UNKNOWN : 'unknown',
+ ARCHITECTURE_X86 : 'x86',
+ ARCHITECTURE_ARM : 'arm',
+ ARCHITECTURE_AARCH64 : 'arm64',
+ ARCHITECTURE_MIPS : 'mips',
+ ARCHITECTURE_RISCV : 'riscv',
+ ARCHITECTURE_PPC64 : 'ppc64',
+ }
+
+# File types. Only supported ones are included here
+TYPE_CBFSHEADER = 0x02 # Master header, HEADER_FORMAT
+TYPE_STAGE = 0x10 # Stage, holding an executable, see STAGE_FORMAT
+TYPE_RAW = 0x50 # Raw file, possibly compressed
+TYPE_EMPTY = 0xffffffff # Empty data
+
+# Compression types
+COMPRESS_NONE, COMPRESS_LZMA, COMPRESS_LZ4 = range(3)
+
+COMPRESS_NAMES = {
+ COMPRESS_NONE : 'none',
+ COMPRESS_LZMA : 'lzma',
+ COMPRESS_LZ4 : 'lz4',
+ }
+
+def find_arch(find_name):
+ """Look up an architecture name
+
+ Args:
+ find_name: Architecture name to find
+
+ Returns:
+ ARCHITECTURE_... value or None if not found
+ """
+ for arch, name in ARCH_NAMES.items():
+ if name == find_name:
+ return arch
+ return None
+
+def find_compress(find_name):
+ """Look up a compression algorithm name
+
+ Args:
+ find_name: Compression algorithm name to find
+
+ Returns:
+ COMPRESS_... value or None if not found
+ """
+ for compress, name in COMPRESS_NAMES.items():
+ if name == find_name:
+ return compress
+ return None
+
+def compress_name(compress):
+ """Look up the name of a compression algorithm
+
+ Args:
+ compress: Compression algorithm number to find (COMPRESS_...)
+
+ Returns:
+ Compression algorithm name (string)
+
+ Raises:
+ KeyError if the algorithm number is invalid
+ """
+ return COMPRESS_NAMES[compress]
+
+def align_int(val, align):
+ """Align a value up to the given alignment
+
+ Args:
+ val: Integer value to align
+ align: Integer alignment value (e.g. 4 to align to 4-byte boundary)
+
+ Returns:
+ integer value aligned to the required boundary, rounding up if necessary
+ """
+ return int((val + align - 1) / align) * align
+
+def align_int_down(val, align):
+ """Align a value down to the given alignment
+
+ Args:
+ val: Integer value to align
+ align: Integer alignment value (e.g. 4 to align to 4-byte boundary)
+
+ Returns:
+ integer value aligned to the required boundary, rounding down if
+ necessary
+ """
+ return int(val / align) * align
+
+def _pack_string(instr):
+ """Pack a string to the required aligned size by adding padding
+
+ Args:
+ instr: String to process
+
+ Returns:
+ String with required padding (at least one 0x00 byte) at the end
+ """
+ val = tools.ToBytes(instr)
+ pad_len = align_int(len(val) + 1, FILENAME_ALIGN)
+ return val + tools.GetBytes(0, pad_len - len(val))
+
+
+class CbfsFile(object):
+ """Class to represent a single CBFS file
+
+ This is used to hold the information about a file, including its contents.
+ Use the get_data_and_offset() method to obtain the raw output for writing to
+ CBFS.
+
+ Properties:
+ name: Name of file
+ offset: Offset of file data from start of file header
+ cbfs_offset: Offset of file data in bytes from start of CBFS, or None to
+ place this file anyway
+ data: Contents of file, uncompressed
+ orig_data: Original data added to the file, possibly compressed
+ data_len: Length of (possibly compressed) data in bytes
+ ftype: File type (TYPE_...)
+ compression: Compression type (COMPRESS_...)
+ memlen: Length of data in memory, i.e. the uncompressed length, None if
+ no compression algortihm is selected
+ load: Load address in memory if known, else None
+ entry: Entry address in memory if known, else None. This is where
+ execution starts after the file is loaded
+ base_address: Base address to use for 'stage' files
+ erase_byte: Erase byte to use for padding between the file header and
+ contents (used for empty files)
+ size: Size of the file in bytes (used for empty files)
+ """
+ def __init__(self, name, ftype, data, cbfs_offset, compress=COMPRESS_NONE):
+ self.name = name
+ self.offset = None
+ self.cbfs_offset = cbfs_offset
+ self.data = data
+ self.orig_data = data
+ self.ftype = ftype
+ self.compress = compress
+ self.memlen = None
+ self.load = None
+ self.entry = None
+ self.base_address = None
+ self.data_len = len(data)
+ self.erase_byte = None
+ self.size = None
+
+ def decompress(self):
+ """Handle decompressing data if necessary"""
+ indata = self.data
+ if self.compress == COMPRESS_LZ4:
+ data = tools.Decompress(indata, 'lz4', with_header=False)
+ elif self.compress == COMPRESS_LZMA:
+ data = tools.Decompress(indata, 'lzma', with_header=False)
+ else:
+ data = indata
+ self.memlen = len(data)
+ self.data = data
+ self.data_len = len(indata)
+
+ @classmethod
+ def stage(cls, base_address, name, data, cbfs_offset):
+ """Create a new stage file
+
+ Args:
+ base_address: Int base address for memory-mapping of ELF file
+ name: String file name to put in CBFS (does not need to correspond
+ to the name that the file originally came from)
+ data: Contents of file
+ cbfs_offset: Offset of file data in bytes from start of CBFS, or
+ None to place this file anyway
+
+ Returns:
+ CbfsFile object containing the file information
+ """
+ cfile = CbfsFile(name, TYPE_STAGE, data, cbfs_offset)
+ cfile.base_address = base_address
+ return cfile
+
+ @classmethod
+ def raw(cls, name, data, cbfs_offset, compress):
+ """Create a new raw file
+
+ Args:
+ name: String file name to put in CBFS (does not need to correspond
+ to the name that the file originally came from)
+ data: Contents of file
+ cbfs_offset: Offset of file data in bytes from start of CBFS, or
+ None to place this file anyway
+ compress: Compression algorithm to use (COMPRESS_...)
+
+ Returns:
+ CbfsFile object containing the file information
+ """
+ return CbfsFile(name, TYPE_RAW, data, cbfs_offset, compress)
+
+ @classmethod
+ def empty(cls, space_to_use, erase_byte):
+ """Create a new empty file of a given size
+
+ Args:
+ space_to_use:: Size of available space, which must be at least as
+ large as the alignment size for this CBFS
+ erase_byte: Byte to use for contents of file (repeated through the
+ whole file)
+
+ Returns:
+ CbfsFile object containing the file information
+ """
+ cfile = CbfsFile('', TYPE_EMPTY, b'', None)
+ cfile.size = space_to_use - FILE_HEADER_LEN - FILENAME_ALIGN
+ cfile.erase_byte = erase_byte
+ return cfile
+
+ def calc_start_offset(self):
+ """Check if this file needs to start at a particular offset in CBFS
+
+ Returns:
+ None if the file can be placed anywhere, or
+ the largest offset where the file could start (integer)
+ """
+ if self.cbfs_offset is None:
+ return None
+ return self.cbfs_offset - self.get_header_len()
+
+ def get_header_len(self):
+ """Get the length of headers required for a file
+
+ This is the minimum length required before the actual data for this file
+ could start. It might start later if there is padding.
+
+ Returns:
+ Total length of all non-data fields, in bytes
+ """
+ name = _pack_string(self.name)
+ hdr_len = len(name) + FILE_HEADER_LEN
+ if self.ftype == TYPE_STAGE:
+ pass
+ elif self.ftype == TYPE_RAW:
+ hdr_len += ATTR_COMPRESSION_LEN
+ elif self.ftype == TYPE_EMPTY:
+ pass
+ else:
+ raise ValueError('Unknown file type %#x\n' % self.ftype)
+ return hdr_len
+
+ def get_data_and_offset(self, offset=None, pad_byte=None):
+ """Obtain the contents of the file, in CBFS format and the offset of
+ the data within the file
+
+ Returns:
+ tuple:
+ bytes representing the contents of this file, packed and aligned
+ for directly inserting into the final CBFS output
+ offset to the file data from the start of the returned data.
+ """
+ name = _pack_string(self.name)
+ hdr_len = len(name) + FILE_HEADER_LEN
+ attr_pos = 0
+ content = b''
+ attr = b''
+ pad = b''
+ data = self.data
+ if self.ftype == TYPE_STAGE:
+ elf_data = elf.DecodeElf(data, self.base_address)
+ content = struct.pack(STAGE_FORMAT, self.compress,
+ elf_data.entry, elf_data.load,
+ len(elf_data.data), elf_data.memsize)
+ data = elf_data.data
+ elif self.ftype == TYPE_RAW:
+ orig_data = data
+ if self.compress == COMPRESS_LZ4:
+ data = tools.Compress(orig_data, 'lz4', with_header=False)
+ elif self.compress == COMPRESS_LZMA:
+ data = tools.Compress(orig_data, 'lzma', with_header=False)
+ self.memlen = len(orig_data)
+ self.data_len = len(data)
+ attr = struct.pack(ATTR_COMPRESSION_FORMAT,
+ FILE_ATTR_TAG_COMPRESSION, ATTR_COMPRESSION_LEN,
+ self.compress, self.memlen)
+ elif self.ftype == TYPE_EMPTY:
+ data = tools.GetBytes(self.erase_byte, self.size)
+ else:
+ raise ValueError('Unknown type %#x when writing\n' % self.ftype)
+ if attr:
+ attr_pos = hdr_len
+ hdr_len += len(attr)
+ if self.cbfs_offset is not None:
+ pad_len = self.cbfs_offset - offset - hdr_len
+ if pad_len < 0: # pragma: no cover
+ # Test coverage of this is not available since this should never
+ # happen. It indicates that get_header_len() provided an
+ # incorrect value (too small) so that we decided that we could
+ # put this file at the requested place, but in fact a previous
+ # file extends far enough into the CBFS that this is not
+ # possible.
+ raise ValueError("Internal error: CBFS file '%s': Requested offset %#x but current output position is %#x" %
+ (self.name, self.cbfs_offset, offset))
+ pad = tools.GetBytes(pad_byte, pad_len)
+ hdr_len += pad_len
+
+ # This is the offset of the start of the file's data,
+ size = len(content) + len(data)
+ hdr = struct.pack(FILE_HEADER_FORMAT, FILE_MAGIC, size,
+ self.ftype, attr_pos, hdr_len)
+
+ # Do a sanity check of the get_header_len() function, to ensure that it
+ # stays in lockstep with this function
+ expected_len = self.get_header_len()
+ actual_len = len(hdr + name + attr)
+ if expected_len != actual_len: # pragma: no cover
+ # Test coverage of this is not available since this should never
+ # happen. It probably indicates that get_header_len() is broken.
+ raise ValueError("Internal error: CBFS file '%s': Expected headers of %#x bytes, got %#d" %
+ (self.name, expected_len, actual_len))
+ return hdr + name + attr + pad + content + data, hdr_len
+
+
+class CbfsWriter(object):
+ """Class to handle writing a Coreboot File System (CBFS)
+
+ Usage is something like:
+
+ cbw = CbfsWriter(size)
+ cbw.add_file_raw('u-boot', tools.ReadFile('u-boot.bin'))
+ ...
+ data, cbfs_offset = cbw.get_data_and_offset()
+
+ Attributes:
+ _master_name: Name of the file containing the master header
+ _size: Size of the filesystem, in bytes
+ _files: Ordered list of files in the CBFS, each a CbfsFile
+ _arch: Architecture of the CBFS (ARCHITECTURE_...)
+ _bootblock_size: Size of the bootblock, typically at the end of the CBFS
+ _erase_byte: Byte to use for empty space in the CBFS
+ _align: Alignment to use for files, typically ENTRY_ALIGN
+ _base_address: Boot block offset in bytes from the start of CBFS.
+ Typically this is located at top of the CBFS. It is 0 when there is
+ no boot block
+ _header_offset: Offset of master header in bytes from start of CBFS
+ _contents_offset: Offset of first file header
+ _hdr_at_start: True if the master header is at the start of the CBFS,
+ instead of the end as normal for x86
+ _add_fileheader: True to add a fileheader around the master header
+ """
+ def __init__(self, size, arch=ARCHITECTURE_X86):
+ """Set up a new CBFS
+
+ This sets up all properties to default values. Files can be added using
+ add_file_raw(), etc.
+
+ Args:
+ size: Size of CBFS in bytes
+ arch: Architecture to declare for CBFS
+ """
+ self._master_name = 'cbfs master header'
+ self._size = size
+ self._files = OrderedDict()
+ self._arch = arch
+ self._bootblock_size = 0
+ self._erase_byte = 0xff
+ self._align = ENTRY_ALIGN
+ self._add_fileheader = False
+ if self._arch == ARCHITECTURE_X86:
+ # Allow 4 bytes for the header pointer. That holds the
+ # twos-compliment negative offset of the master header in bytes
+ # measured from one byte past the end of the CBFS
+ self._base_address = self._size - max(self._bootblock_size,
+ MIN_BOOTBLOCK_SIZE)
+ self._header_offset = self._base_address - HEADER_LEN
+ self._contents_offset = 0
+ self._hdr_at_start = False
+ else:
+ # For non-x86, different rules apply
+ self._base_address = 0
+ self._header_offset = align_int(self._base_address +
+ self._bootblock_size, 4)
+ self._contents_offset = align_int(self._header_offset +
+ FILE_HEADER_LEN +
+ self._bootblock_size, self._align)
+ self._hdr_at_start = True
+
+ def _skip_to(self, fd, offset):
+ """Write out pad bytes until a given offset
+
+ Args:
+ fd: File objext to write to
+ offset: Offset to write to
+ """
+ if fd.tell() > offset:
+ raise ValueError('No space for data before offset %#x (current offset %#x)' %
+ (offset, fd.tell()))
+ fd.write(tools.GetBytes(self._erase_byte, offset - fd.tell()))
+
+ def _pad_to(self, fd, offset):
+ """Write out pad bytes and/or an empty file until a given offset
+
+ Args:
+ fd: File objext to write to
+ offset: Offset to write to
+ """
+ self._align_to(fd, self._align)
+ upto = fd.tell()
+ if upto > offset:
+ raise ValueError('No space for data before pad offset %#x (current offset %#x)' %
+ (offset, upto))
+ todo = align_int_down(offset - upto, self._align)
+ if todo:
+ cbf = CbfsFile.empty(todo, self._erase_byte)
+ fd.write(cbf.get_data_and_offset()[0])
+ self._skip_to(fd, offset)
+
+ def _align_to(self, fd, align):
+ """Write out pad bytes until a given alignment is reached
+
+ This only aligns if the resulting output would not reach the end of the
+ CBFS, since we want to leave the last 4 bytes for the master-header
+ pointer.
+
+ Args:
+ fd: File objext to write to
+ align: Alignment to require (e.g. 4 means pad to next 4-byte
+ boundary)
+ """
+ offset = align_int(fd.tell(), align)
+ if offset < self._size:
+ self._skip_to(fd, offset)
+
+ def add_file_stage(self, name, data, cbfs_offset=None):
+ """Add a new stage file to the CBFS
+
+ Args:
+ name: String file name to put in CBFS (does not need to correspond
+ to the name that the file originally came from)
+ data: Contents of file
+ cbfs_offset: Offset of this file's data within the CBFS, in bytes,
+ or None to place this file anywhere
+
+ Returns:
+ CbfsFile object created
+ """
+ cfile = CbfsFile.stage(self._base_address, name, data, cbfs_offset)
+ self._files[name] = cfile
+ return cfile
+
+ def add_file_raw(self, name, data, cbfs_offset=None,
+ compress=COMPRESS_NONE):
+ """Create a new raw file
+
+ Args:
+ name: String file name to put in CBFS (does not need to correspond
+ to the name that the file originally came from)
+ data: Contents of file
+ cbfs_offset: Offset of this file's data within the CBFS, in bytes,
+ or None to place this file anywhere
+ compress: Compression algorithm to use (COMPRESS_...)
+
+ Returns:
+ CbfsFile object created
+ """
+ cfile = CbfsFile.raw(name, data, cbfs_offset, compress)
+ self._files[name] = cfile
+ return cfile
+
+ def _write_header(self, fd, add_fileheader):
+ """Write out the master header to a CBFS
+
+ Args:
+ fd: File object
+ add_fileheader: True to place the master header in a file header
+ record
+ """
+ if fd.tell() > self._header_offset:
+ raise ValueError('No space for header at offset %#x (current offset %#x)' %
+ (self._header_offset, fd.tell()))
+ if not add_fileheader:
+ self._pad_to(fd, self._header_offset)
+ hdr = struct.pack(HEADER_FORMAT, HEADER_MAGIC, HEADER_VERSION2,
+ self._size, self._bootblock_size, self._align,
+ self._contents_offset, self._arch, 0xffffffff)
+ if add_fileheader:
+ name = _pack_string(self._master_name)
+ fd.write(struct.pack(FILE_HEADER_FORMAT, FILE_MAGIC, len(hdr),
+ TYPE_CBFSHEADER, 0,
+ FILE_HEADER_LEN + len(name)))
+ fd.write(name)
+ self._header_offset = fd.tell()
+ fd.write(hdr)
+ self._align_to(fd, self._align)
+ else:
+ fd.write(hdr)
+
+ def get_data(self):
+ """Obtain the full contents of the CBFS
+
+ Thhis builds the CBFS with headers and all required files.
+
+ Returns:
+ 'bytes' type containing the data
+ """
+ fd = io.BytesIO()
+
+ # THe header can go at the start in some cases
+ if self._hdr_at_start:
+ self._write_header(fd, add_fileheader=self._add_fileheader)
+ self._skip_to(fd, self._contents_offset)
+
+ # Write out each file
+ for cbf in self._files.values():
+ # Place the file at its requested place, if any
+ offset = cbf.calc_start_offset()
+ if offset is not None:
+ self._pad_to(fd, align_int_down(offset, self._align))
+ pos = fd.tell()
+ data, data_offset = cbf.get_data_and_offset(pos, self._erase_byte)
+ fd.write(data)
+ self._align_to(fd, self._align)
+ cbf.calced_cbfs_offset = pos + data_offset
+ if not self._hdr_at_start:
+ self._write_header(fd, add_fileheader=self._add_fileheader)
+
+ # Pad to the end and write a pointer to the CBFS master header
+ self._pad_to(fd, self._base_address or self._size - 4)
+ rel_offset = self._header_offset - self._size
+ fd.write(struct.pack('<I', rel_offset & 0xffffffff))
+
+ return fd.getvalue()
+
+
+class CbfsReader(object):
+ """Class to handle reading a Coreboot File System (CBFS)
+
+ Usage is something like:
+ cbfs = cbfs_util.CbfsReader(data)
+ cfile = cbfs.files['u-boot']
+ self.WriteFile('u-boot.bin', cfile.data)
+
+ Attributes:
+ files: Ordered list of CbfsFile objects
+ align: Alignment to use for files, typically ENTRT_ALIGN
+ stage_base_address: Base address to use when mapping ELF files into the
+ CBFS for TYPE_STAGE files. If this is larger than the code address
+ of the ELF file, then data at the start of the ELF file will not
+ appear in the CBFS. Currently there are no tests for behaviour as
+ documentation is sparse
+ magic: Integer magic number from master header (HEADER_MAGIC)
+ version: Version number of CBFS (HEADER_VERSION2)
+ rom_size: Size of CBFS
+ boot_block_size: Size of boot block
+ cbfs_offset: Offset of the first file in bytes from start of CBFS
+ arch: Architecture of CBFS file (ARCHITECTURE_...)
+ """
+ def __init__(self, data, read=True):
+ self.align = ENTRY_ALIGN
+ self.arch = None
+ self.boot_block_size = None
+ self.cbfs_offset = None
+ self.files = OrderedDict()
+ self.magic = None
+ self.rom_size = None
+ self.stage_base_address = 0
+ self.version = None
+ self.data = data
+ if read:
+ self.read()
+
+ def read(self):
+ """Read all the files in the CBFS and add them to self.files"""
+ with io.BytesIO(self.data) as fd:
+ # First, get the master header
+ if not self._find_and_read_header(fd, len(self.data)):
+ raise ValueError('Cannot find master header')
+ fd.seek(self.cbfs_offset)
+
+ # Now read in the files one at a time
+ while True:
+ cfile = self._read_next_file(fd)
+ if cfile:
+ self.files[cfile.name] = cfile
+ elif cfile is False:
+ break
+
+ def _find_and_read_header(self, fd, size):
+ """Find and read the master header in the CBFS
+
+ This looks at the pointer word at the very end of the CBFS. This is an
+ offset to the header relative to the size of the CBFS, which is assumed
+ to be known. Note that the offset is in *little endian* format.
+
+ Args:
+ fd: File to read from
+ size: Size of file
+
+ Returns:
+ True if header was found, False if not
+ """
+ orig_pos = fd.tell()
+ fd.seek(size - 4)
+ rel_offset, = struct.unpack('<I', fd.read(4))
+ pos = (size + rel_offset) & 0xffffffff
+ fd.seek(pos)
+ found = self._read_header(fd)
+ if not found:
+ print('Relative offset seems wrong, scanning whole image')
+ for pos in range(0, size - HEADER_LEN, 4):
+ fd.seek(pos)
+ found = self._read_header(fd)
+ if found:
+ break
+ fd.seek(orig_pos)
+ return found
+
+ def _read_next_file(self, fd):
+ """Read the next file from a CBFS
+
+ Args:
+ fd: File to read from
+
+ Returns:
+ CbfsFile object, if found
+ None if no object found, but data was parsed (e.g. TYPE_CBFSHEADER)
+ False if at end of CBFS and reading should stop
+ """
+ file_pos = fd.tell()
+ data = fd.read(FILE_HEADER_LEN)
+ if len(data) < FILE_HEADER_LEN:
+ print('File header at %#x ran out of data' % file_pos)
+ return False
+ magic, size, ftype, attr, offset = struct.unpack(FILE_HEADER_FORMAT,
+ data)
+ if magic != FILE_MAGIC:
+ return False
+ pos = fd.tell()
+ name = self._read_string(fd)
+ if name is None:
+ print('String at %#x ran out of data' % pos)
+ return False
+
+ if DEBUG:
+ print('name', name)
+
+ # If there are attribute headers present, read those
+ compress = self._read_attr(fd, file_pos, attr, offset)
+ if compress is None:
+ return False
+
+ # Create the correct CbfsFile object depending on the type
+ cfile = None
+ cbfs_offset = file_pos + offset
+ fd.seek(cbfs_offset, io.SEEK_SET)
+ if ftype == TYPE_CBFSHEADER:
+ self._read_header(fd)
+ elif ftype == TYPE_STAGE:
+ data = fd.read(STAGE_LEN)
+ cfile = CbfsFile.stage(self.stage_base_address, name, b'',
+ cbfs_offset)
+ (cfile.compress, cfile.entry, cfile.load, cfile.data_len,
+ cfile.memlen) = struct.unpack(STAGE_FORMAT, data)
+ cfile.data = fd.read(cfile.data_len)
+ elif ftype == TYPE_RAW:
+ data = fd.read(size)
+ cfile = CbfsFile.raw(name, data, cbfs_offset, compress)
+ cfile.decompress()
+ if DEBUG:
+ print('data', data)
+ elif ftype == TYPE_EMPTY:
+ # Just read the data and discard it, since it is only padding
+ fd.read(size)
+ cfile = CbfsFile('', TYPE_EMPTY, b'', cbfs_offset)
+ else:
+ raise ValueError('Unknown type %#x when reading\n' % ftype)
+ if cfile:
+ cfile.offset = offset
+
+ # Move past the padding to the start of a possible next file. If we are
+ # already at an alignment boundary, then there is no padding.
+ pad = (self.align - fd.tell() % self.align) % self.align
+ fd.seek(pad, io.SEEK_CUR)
+ return cfile
+
+ @classmethod
+ def _read_attr(cls, fd, file_pos, attr, offset):
+ """Read attributes from the file
+
+ CBFS files can have attributes which are things that cannot fit into the
+ header. The only attributes currently supported are compression and the
+ unused tag.
+
+ Args:
+ fd: File to read from
+ file_pos: Position of file in fd
+ attr: Offset of attributes, 0 if none
+ offset: Offset of file data (used to indicate the end of the
+ attributes)
+
+ Returns:
+ Compression to use for the file (COMPRESS_...)
+ """
+ compress = COMPRESS_NONE
+ if not attr:
+ return compress
+ attr_size = offset - attr
+ fd.seek(file_pos + attr, io.SEEK_SET)
+ while attr_size:
+ pos = fd.tell()
+ hdr = fd.read(8)
+ if len(hdr) < 8:
+ print('Attribute tag at %x ran out of data' % pos)
+ return None
+ atag, alen = struct.unpack(">II", hdr)
+ data = hdr + fd.read(alen - 8)
+ if atag == FILE_ATTR_TAG_COMPRESSION:
+ # We don't currently use this information
+ atag, alen, compress, _decomp_size = struct.unpack(
+ ATTR_COMPRESSION_FORMAT, data)
+ elif atag == FILE_ATTR_TAG_UNUSED2:
+ break
+ else:
+ print('Unknown attribute tag %x' % atag)
+ attr_size -= len(data)
+ return compress
+
+ def _read_header(self, fd):
+ """Read the master header
+
+ Reads the header and stores the information obtained into the member
+ variables.
+
+ Args:
+ fd: File to read from
+
+ Returns:
+ True if header was read OK, False if it is truncated or has the
+ wrong magic or version
+ """
+ pos = fd.tell()
+ data = fd.read(HEADER_LEN)
+ if len(data) < HEADER_LEN:
+ print('Header at %x ran out of data' % pos)
+ return False
+ (self.magic, self.version, self.rom_size, self.boot_block_size,
+ self.align, self.cbfs_offset, self.arch, _) = struct.unpack(
+ HEADER_FORMAT, data)
+ return self.magic == HEADER_MAGIC and (
+ self.version == HEADER_VERSION1 or
+ self.version == HEADER_VERSION2)
+
+ @classmethod
+ def _read_string(cls, fd):
+ """Read a string from a file
+
+ This reads a string and aligns the data to the next alignment boundary
+
+ Args:
+ fd: File to read from
+
+ Returns:
+ string read ('str' type) encoded to UTF-8, or None if we ran out of
+ data
+ """
+ val = b''
+ while True:
+ data = fd.read(FILENAME_ALIGN)
+ if len(data) < FILENAME_ALIGN:
+ return None
+ pos = data.find(b'\0')
+ if pos == -1:
+ val += data
+ else:
+ val += data[:pos]
+ break
+ return val.decode('utf-8')
+
+
+def cbfstool(fname, *cbfs_args, **kwargs):
+ """Run cbfstool with provided arguments
+
+ If the tool fails then this function raises an exception and prints out the
+ output and stderr.
+
+ Args:
+ fname: Filename of CBFS
+ *cbfs_args: List of arguments to pass to cbfstool
+
+ Returns:
+ CommandResult object containing the results
+ """
+ args = ['cbfstool', fname] + list(cbfs_args)
+ if kwargs.get('base') is not None:
+ args += ['-b', '%#x' % kwargs['base']]
+ result = command.RunPipe([args], capture=not VERBOSE,
+ capture_stderr=not VERBOSE, raise_on_error=False)
+ if result.return_code:
+ print(result.stderr, file=sys.stderr)
+ raise Exception("Failed to run (error %d): '%s'" %
+ (result.return_code, ' '.join(args)))
diff --git a/tools/binman/cbfs_util_test.py b/tools/binman/cbfs_util_test.py
new file mode 100755
index 0000000..772c794
--- /dev/null
+++ b/tools/binman/cbfs_util_test.py
@@ -0,0 +1,625 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright 2019 Google LLC
+# Written by Simon Glass <sjg@chromium.org>
+
+"""Tests for cbfs_util
+
+These create and read various CBFSs and compare the results with expected
+values and with cbfstool
+"""
+
+from __future__ import print_function
+
+import io
+import os
+import shutil
+import struct
+import tempfile
+import unittest
+
+import cbfs_util
+from cbfs_util import CbfsWriter
+import elf
+import test_util
+import tools
+
+U_BOOT_DATA = b'1234'
+U_BOOT_DTB_DATA = b'udtb'
+COMPRESS_DATA = b'compress xxxxxxxxxxxxxxxxxxxxxx data'
+
+
+class TestCbfs(unittest.TestCase):
+ """Test of cbfs_util classes"""
+ #pylint: disable=W0212
+ @classmethod
+ def setUpClass(cls):
+ # Create a temporary directory for test files
+ cls._indir = tempfile.mkdtemp(prefix='cbfs_util.')
+ tools.SetInputDirs([cls._indir])
+
+ # Set up some useful data files
+ TestCbfs._make_input_file('u-boot.bin', U_BOOT_DATA)
+ TestCbfs._make_input_file('u-boot.dtb', U_BOOT_DTB_DATA)
+ TestCbfs._make_input_file('compress', COMPRESS_DATA)
+
+ # Set up a temporary output directory, used by the tools library when
+ # compressing files
+ tools.PrepareOutputDir(None)
+
+ cls.have_cbfstool = True
+ try:
+ tools.Run('which', 'cbfstool')
+ except:
+ cls.have_cbfstool = False
+
+ cls.have_lz4 = True
+ try:
+ tools.Run('lz4', '--no-frame-crc', '-c',
+ tools.GetInputFilename('u-boot.bin'))
+ except:
+ cls.have_lz4 = False
+
+ @classmethod
+ def tearDownClass(cls):
+ """Remove the temporary input directory and its contents"""
+ if cls._indir:
+ shutil.rmtree(cls._indir)
+ cls._indir = None
+ tools.FinaliseOutputDir()
+
+ @classmethod
+ def _make_input_file(cls, fname, contents):
+ """Create a new test input file, creating directories as needed
+
+ Args:
+ fname: Filename to create
+ contents: File contents to write in to the file
+ Returns:
+ Full pathname of file created
+ """
+ pathname = os.path.join(cls._indir, fname)
+ tools.WriteFile(pathname, contents)
+ return pathname
+
+ def _check_hdr(self, data, size, offset=0, arch=cbfs_util.ARCHITECTURE_X86):
+ """Check that the CBFS has the expected header
+
+ Args:
+ data: Data to check
+ size: Expected ROM size
+ offset: Expected offset to first CBFS file
+ arch: Expected architecture
+
+ Returns:
+ CbfsReader object containing the CBFS
+ """
+ cbfs = cbfs_util.CbfsReader(data)
+ self.assertEqual(cbfs_util.HEADER_MAGIC, cbfs.magic)
+ self.assertEqual(cbfs_util.HEADER_VERSION2, cbfs.version)
+ self.assertEqual(size, cbfs.rom_size)
+ self.assertEqual(0, cbfs.boot_block_size)
+ self.assertEqual(cbfs_util.ENTRY_ALIGN, cbfs.align)
+ self.assertEqual(offset, cbfs.cbfs_offset)
+ self.assertEqual(arch, cbfs.arch)
+ return cbfs
+
+ def _check_uboot(self, cbfs, ftype=cbfs_util.TYPE_RAW, offset=0x38,
+ data=U_BOOT_DATA, cbfs_offset=None):
+ """Check that the U-Boot file is as expected
+
+ Args:
+ cbfs: CbfsReader object to check
+ ftype: Expected file type
+ offset: Expected offset of file
+ data: Expected data in file
+ cbfs_offset: Expected CBFS offset for file's data
+
+ Returns:
+ CbfsFile object containing the file
+ """
+ self.assertIn('u-boot', cbfs.files)
+ cfile = cbfs.files['u-boot']
+ self.assertEqual('u-boot', cfile.name)
+ self.assertEqual(offset, cfile.offset)
+ if cbfs_offset is not None:
+ self.assertEqual(cbfs_offset, cfile.cbfs_offset)
+ self.assertEqual(data, cfile.data)
+ self.assertEqual(ftype, cfile.ftype)
+ self.assertEqual(cbfs_util.COMPRESS_NONE, cfile.compress)
+ self.assertEqual(len(data), cfile.memlen)
+ return cfile
+
+ def _check_dtb(self, cbfs, offset=0x38, data=U_BOOT_DTB_DATA,
+ cbfs_offset=None):
+ """Check that the U-Boot dtb file is as expected
+
+ Args:
+ cbfs: CbfsReader object to check
+ offset: Expected offset of file
+ data: Expected data in file
+ cbfs_offset: Expected CBFS offset for file's data
+ """
+ self.assertIn('u-boot-dtb', cbfs.files)
+ cfile = cbfs.files['u-boot-dtb']
+ self.assertEqual('u-boot-dtb', cfile.name)
+ self.assertEqual(offset, cfile.offset)
+ if cbfs_offset is not None:
+ self.assertEqual(cbfs_offset, cfile.cbfs_offset)
+ self.assertEqual(U_BOOT_DTB_DATA, cfile.data)
+ self.assertEqual(cbfs_util.TYPE_RAW, cfile.ftype)
+ self.assertEqual(cbfs_util.COMPRESS_NONE, cfile.compress)
+ self.assertEqual(len(U_BOOT_DTB_DATA), cfile.memlen)
+
+ def _check_raw(self, data, size, offset=0, arch=cbfs_util.ARCHITECTURE_X86):
+ """Check that two raw files are added as expected
+
+ Args:
+ data: Data to check
+ size: Expected ROM size
+ offset: Expected offset to first CBFS file
+ arch: Expected architecture
+ """
+ cbfs = self._check_hdr(data, size, offset=offset, arch=arch)
+ self._check_uboot(cbfs)
+ self._check_dtb(cbfs)
+
+ def _get_expected_cbfs(self, size, arch='x86', compress=None, base=None):
+ """Get the file created by cbfstool for a particular scenario
+
+ Args:
+ size: Size of the CBFS in bytes
+ arch: Architecture of the CBFS, as a string
+ compress: Compression to use, e.g. cbfs_util.COMPRESS_LZMA
+ base: Base address of file, or None to put it anywhere
+
+ Returns:
+ Resulting CBFS file, or None if cbfstool is not available
+ """
+ if not self.have_cbfstool or not self.have_lz4:
+ return None
+ cbfs_fname = os.path.join(self._indir, 'test.cbfs')
+ cbfs_util.cbfstool(cbfs_fname, 'create', '-m', arch, '-s', '%#x' % size)
+ if base:
+ base = [(1 << 32) - size + b for b in base]
+ cbfs_util.cbfstool(cbfs_fname, 'add', '-n', 'u-boot', '-t', 'raw',
+ '-c', compress and compress[0] or 'none',
+ '-f', tools.GetInputFilename(
+ compress and 'compress' or 'u-boot.bin'),
+ base=base[0] if base else None)
+ cbfs_util.cbfstool(cbfs_fname, 'add', '-n', 'u-boot-dtb', '-t', 'raw',
+ '-c', compress and compress[1] or 'none',
+ '-f', tools.GetInputFilename(
+ compress and 'compress' or 'u-boot.dtb'),
+ base=base[1] if base else None)
+ return cbfs_fname
+
+ def _compare_expected_cbfs(self, data, cbfstool_fname):
+ """Compare against what cbfstool creates
+
+ This compares what binman creates with what cbfstool creates for what
+ is proportedly the same thing.
+
+ Args:
+ data: CBFS created by binman
+ cbfstool_fname: CBFS created by cbfstool
+ """
+ if not self.have_cbfstool or not self.have_lz4:
+ return
+ expect = tools.ReadFile(cbfstool_fname)
+ if expect != data:
+ tools.WriteFile('/tmp/expect', expect)
+ tools.WriteFile('/tmp/actual', data)
+ print('diff -y <(xxd -g1 /tmp/expect) <(xxd -g1 /tmp/actual) | colordiff')
+ self.fail('cbfstool produced a different result')
+
+ def test_cbfs_functions(self):
+ """Test global functions of cbfs_util"""
+ self.assertEqual(cbfs_util.ARCHITECTURE_X86, cbfs_util.find_arch('x86'))
+ self.assertIsNone(cbfs_util.find_arch('bad-arch'))
+
+ self.assertEqual(cbfs_util.COMPRESS_LZMA, cbfs_util.find_compress('lzma'))
+ self.assertIsNone(cbfs_util.find_compress('bad-comp'))
+
+ def test_cbfstool_failure(self):
+ """Test failure to run cbfstool"""
+ if not self.have_cbfstool:
+ self.skipTest('No cbfstool available')
+ try:
+ # In verbose mode this test fails since stderr is not captured. Fix
+ # this by turning off verbosity.
+ old_verbose = cbfs_util.VERBOSE
+ cbfs_util.VERBOSE = False
+ with test_util.capture_sys_output() as (_stdout, stderr):
+ with self.assertRaises(Exception) as e:
+ cbfs_util.cbfstool('missing-file', 'bad-command')
+ finally:
+ cbfs_util.VERBOSE = old_verbose
+ self.assertIn('Unknown command', stderr.getvalue())
+ self.assertIn('Failed to run', str(e.exception))
+
+ def test_cbfs_raw(self):
+ """Test base handling of a Coreboot Filesystem (CBFS)"""
+ size = 0xb0
+ cbw = CbfsWriter(size)
+ cbw.add_file_raw('u-boot', U_BOOT_DATA)
+ cbw.add_file_raw('u-boot-dtb', U_BOOT_DTB_DATA)
+ data = cbw.get_data()
+ self._check_raw(data, size)
+ cbfs_fname = self._get_expected_cbfs(size=size)
+ self._compare_expected_cbfs(data, cbfs_fname)
+
+ def test_cbfs_invalid_file_type(self):
+ """Check handling of an invalid file type when outputiing a CBFS"""
+ size = 0xb0
+ cbw = CbfsWriter(size)
+ cfile = cbw.add_file_raw('u-boot', U_BOOT_DATA)
+
+ # Change the type manually before generating the CBFS, and make sure
+ # that the generator complains
+ cfile.ftype = 0xff
+ with self.assertRaises(ValueError) as e:
+ cbw.get_data()
+ self.assertIn('Unknown type 0xff when writing', str(e.exception))
+
+ def test_cbfs_invalid_file_type_on_read(self):
+ """Check handling of an invalid file type when reading the CBFS"""
+ size = 0xb0
+ cbw = CbfsWriter(size)
+ cbw.add_file_raw('u-boot', U_BOOT_DATA)
+
+ data = cbw.get_data()
+
+ # Read in the first file header
+ cbr = cbfs_util.CbfsReader(data, read=False)
+ with io.BytesIO(data) as fd:
+ self.assertTrue(cbr._find_and_read_header(fd, len(data)))
+ pos = fd.tell()
+ hdr_data = fd.read(cbfs_util.FILE_HEADER_LEN)
+ magic, size, ftype, attr, offset = struct.unpack(
+ cbfs_util.FILE_HEADER_FORMAT, hdr_data)
+
+ # Create a new CBFS with a change to the file type
+ ftype = 0xff
+ newdata = data[:pos]
+ newdata += struct.pack(cbfs_util.FILE_HEADER_FORMAT, magic, size, ftype,
+ attr, offset)
+ newdata += data[pos + cbfs_util.FILE_HEADER_LEN:]
+
+ # Read in this CBFS and make sure that the reader complains
+ with self.assertRaises(ValueError) as e:
+ cbfs_util.CbfsReader(newdata)
+ self.assertIn('Unknown type 0xff when reading', str(e.exception))
+
+ def test_cbfs_no_space(self):
+ """Check handling of running out of space in the CBFS"""
+ size = 0x60
+ cbw = CbfsWriter(size)
+ cbw.add_file_raw('u-boot', U_BOOT_DATA)
+ with self.assertRaises(ValueError) as e:
+ cbw.get_data()
+ self.assertIn('No space for header', str(e.exception))
+
+ def test_cbfs_no_space_skip(self):
+ """Check handling of running out of space in CBFS with file header"""
+ size = 0x5c
+ cbw = CbfsWriter(size, arch=cbfs_util.ARCHITECTURE_PPC64)
+ cbw._add_fileheader = True
+ cbw.add_file_raw('u-boot', U_BOOT_DATA)
+ with self.assertRaises(ValueError) as e:
+ cbw.get_data()
+ self.assertIn('No space for data before offset', str(e.exception))
+
+ def test_cbfs_no_space_pad(self):
+ """Check handling of running out of space in CBFS with file header"""
+ size = 0x70
+ cbw = CbfsWriter(size)
+ cbw._add_fileheader = True
+ cbw.add_file_raw('u-boot', U_BOOT_DATA)
+ with self.assertRaises(ValueError) as e:
+ cbw.get_data()
+ self.assertIn('No space for data before pad offset', str(e.exception))
+
+ def test_cbfs_bad_header_ptr(self):
+ """Check handling of a bad master-header pointer"""
+ size = 0x70
+ cbw = CbfsWriter(size)
+ cbw.add_file_raw('u-boot', U_BOOT_DATA)
+ data = cbw.get_data()
+
+ # Add one to the pointer to make it invalid
+ newdata = data[:-4] + struct.pack('<I', cbw._header_offset + 1)
+
+ # We should still be able to find the master header by searching
+ with test_util.capture_sys_output() as (stdout, _stderr):
+ cbfs = cbfs_util.CbfsReader(newdata)
+ self.assertIn('Relative offset seems wrong', stdout.getvalue())
+ self.assertIn('u-boot', cbfs.files)
+ self.assertEqual(size, cbfs.rom_size)
+
+ def test_cbfs_bad_header(self):
+ """Check handling of a bad master header"""
+ size = 0x70
+ cbw = CbfsWriter(size)
+ cbw.add_file_raw('u-boot', U_BOOT_DATA)
+ data = cbw.get_data()
+
+ # Drop most of the header and try reading the modified CBFS
+ newdata = data[:cbw._header_offset + 4]
+
+ with test_util.capture_sys_output() as (stdout, _stderr):
+ with self.assertRaises(ValueError) as e:
+ cbfs_util.CbfsReader(newdata)
+ self.assertIn('Relative offset seems wrong', stdout.getvalue())
+ self.assertIn('Cannot find master header', str(e.exception))
+
+ def test_cbfs_bad_file_header(self):
+ """Check handling of a bad file header"""
+ size = 0x70
+ cbw = CbfsWriter(size)
+ cbw.add_file_raw('u-boot', U_BOOT_DATA)
+ data = cbw.get_data()
+
+ # Read in the CBFS master header (only), then stop
+ cbr = cbfs_util.CbfsReader(data, read=False)
+ with io.BytesIO(data) as fd:
+ self.assertTrue(cbr._find_and_read_header(fd, len(data)))
+ pos = fd.tell()
+
+ # Remove all but 4 bytes of the file headerm and try to read the file
+ newdata = data[:pos + 4]
+ with test_util.capture_sys_output() as (stdout, _stderr):
+ with io.BytesIO(newdata) as fd:
+ fd.seek(pos)
+ self.assertEqual(False, cbr._read_next_file(fd))
+ self.assertIn('File header at 0x0 ran out of data', stdout.getvalue())
+
+ def test_cbfs_bad_file_string(self):
+ """Check handling of an incomplete filename string"""
+ size = 0x70
+ cbw = CbfsWriter(size)
+ cbw.add_file_raw('16-characters xx', U_BOOT_DATA)
+ data = cbw.get_data()
+
+ # Read in the CBFS master header (only), then stop
+ cbr = cbfs_util.CbfsReader(data, read=False)
+ with io.BytesIO(data) as fd:
+ self.assertTrue(cbr._find_and_read_header(fd, len(data)))
+ pos = fd.tell()
+
+ # Create a new CBFS with only the first 16 bytes of the file name, then
+ # try to read the file
+ newdata = data[:pos + cbfs_util.FILE_HEADER_LEN + 16]
+ with test_util.capture_sys_output() as (stdout, _stderr):
+ with io.BytesIO(newdata) as fd:
+ fd.seek(pos)
+ self.assertEqual(False, cbr._read_next_file(fd))
+ self.assertIn('String at %#x ran out of data' %
+ cbfs_util.FILE_HEADER_LEN, stdout.getvalue())
+
+ def test_cbfs_debug(self):
+ """Check debug output"""
+ size = 0x70
+ cbw = CbfsWriter(size)
+ cbw.add_file_raw('u-boot', U_BOOT_DATA)
+ data = cbw.get_data()
+
+ try:
+ cbfs_util.DEBUG = True
+ with test_util.capture_sys_output() as (stdout, _stderr):
+ cbfs_util.CbfsReader(data)
+ self.assertEqual('name u-boot\ndata %s\n' % U_BOOT_DATA,
+ stdout.getvalue())
+ finally:
+ cbfs_util.DEBUG = False
+
+ def test_cbfs_bad_attribute(self):
+ """Check handling of bad attribute tag"""
+ if not self.have_lz4:
+ self.skipTest('lz4 --no-frame-crc not available')
+ size = 0x140
+ cbw = CbfsWriter(size)
+ cbw.add_file_raw('u-boot', COMPRESS_DATA, None,
+ compress=cbfs_util.COMPRESS_LZ4)
+ data = cbw.get_data()
+
+ # Search the CBFS for the expected compression tag
+ with io.BytesIO(data) as fd:
+ while True:
+ pos = fd.tell()
+ tag, = struct.unpack('>I', fd.read(4))
+ if tag == cbfs_util.FILE_ATTR_TAG_COMPRESSION:
+ break
+
+ # Create a new CBFS with the tag changed to something invalid
+ newdata = data[:pos] + struct.pack('>I', 0x123) + data[pos + 4:]
+ with test_util.capture_sys_output() as (stdout, _stderr):
+ cbfs_util.CbfsReader(newdata)
+ self.assertEqual('Unknown attribute tag 123\n', stdout.getvalue())
+
+ def test_cbfs_missing_attribute(self):
+ """Check handling of an incomplete attribute tag"""
+ if not self.have_lz4:
+ self.skipTest('lz4 --no-frame-crc not available')
+ size = 0x140
+ cbw = CbfsWriter(size)
+ cbw.add_file_raw('u-boot', COMPRESS_DATA, None,
+ compress=cbfs_util.COMPRESS_LZ4)
+ data = cbw.get_data()
+
+ # Read in the CBFS master header (only), then stop
+ cbr = cbfs_util.CbfsReader(data, read=False)
+ with io.BytesIO(data) as fd:
+ self.assertTrue(cbr._find_and_read_header(fd, len(data)))
+ pos = fd.tell()
+
+ # Create a new CBFS with only the first 4 bytes of the compression tag,
+ # then try to read the file
+ tag_pos = pos + cbfs_util.FILE_HEADER_LEN + cbfs_util.FILENAME_ALIGN
+ newdata = data[:tag_pos + 4]
+ with test_util.capture_sys_output() as (stdout, _stderr):
+ with io.BytesIO(newdata) as fd:
+ fd.seek(pos)
+ self.assertEqual(False, cbr._read_next_file(fd))
+ self.assertIn('Attribute tag at %x ran out of data' % tag_pos,
+ stdout.getvalue())
+
+ def test_cbfs_file_master_header(self):
+ """Check handling of a file containing a master header"""
+ size = 0x100
+ cbw = CbfsWriter(size)
+ cbw._add_fileheader = True
+ cbw.add_file_raw('u-boot', U_BOOT_DATA)
+ data = cbw.get_data()
+
+ cbr = cbfs_util.CbfsReader(data)
+ self.assertIn('u-boot', cbr.files)
+ self.assertEqual(size, cbr.rom_size)
+
+ def test_cbfs_arch(self):
+ """Test on non-x86 architecture"""
+ size = 0x100
+ cbw = CbfsWriter(size, arch=cbfs_util.ARCHITECTURE_PPC64)
+ cbw.add_file_raw('u-boot', U_BOOT_DATA)
+ cbw.add_file_raw('u-boot-dtb', U_BOOT_DTB_DATA)
+ data = cbw.get_data()
+ self._check_raw(data, size, offset=0x40,
+ arch=cbfs_util.ARCHITECTURE_PPC64)
+
+ # Compare against what cbfstool creates
+ cbfs_fname = self._get_expected_cbfs(size=size, arch='ppc64')
+ self._compare_expected_cbfs(data, cbfs_fname)
+
+ def test_cbfs_stage(self):
+ """Tests handling of a Coreboot Filesystem (CBFS)"""
+ if not elf.ELF_TOOLS:
+ self.skipTest('Python elftools not available')
+ elf_fname = os.path.join(self._indir, 'cbfs-stage.elf')
+ elf.MakeElf(elf_fname, U_BOOT_DATA, U_BOOT_DTB_DATA)
+
+ size = 0xb0
+ cbw = CbfsWriter(size)
+ cbw.add_file_stage('u-boot', tools.ReadFile(elf_fname))
+
+ data = cbw.get_data()
+ cbfs = self._check_hdr(data, size)
+ load = 0xfef20000
+ entry = load + 2
+
+ cfile = self._check_uboot(cbfs, cbfs_util.TYPE_STAGE, offset=0x28,
+ data=U_BOOT_DATA + U_BOOT_DTB_DATA)
+
+ self.assertEqual(entry, cfile.entry)
+ self.assertEqual(load, cfile.load)
+ self.assertEqual(len(U_BOOT_DATA) + len(U_BOOT_DTB_DATA),
+ cfile.data_len)
+
+ # Compare against what cbfstool creates
+ if self.have_cbfstool:
+ cbfs_fname = os.path.join(self._indir, 'test.cbfs')
+ cbfs_util.cbfstool(cbfs_fname, 'create', '-m', 'x86', '-s',
+ '%#x' % size)
+ cbfs_util.cbfstool(cbfs_fname, 'add-stage', '-n', 'u-boot',
+ '-f', elf_fname)
+ self._compare_expected_cbfs(data, cbfs_fname)
+
+ def test_cbfs_raw_compress(self):
+ """Test base handling of compressing raw files"""
+ if not self.have_lz4:
+ self.skipTest('lz4 --no-frame-crc not available')
+ size = 0x140
+ cbw = CbfsWriter(size)
+ cbw.add_file_raw('u-boot', COMPRESS_DATA, None,
+ compress=cbfs_util.COMPRESS_LZ4)
+ cbw.add_file_raw('u-boot-dtb', COMPRESS_DATA, None,
+ compress=cbfs_util.COMPRESS_LZMA)
+ data = cbw.get_data()
+
+ cbfs = self._check_hdr(data, size)
+ self.assertIn('u-boot', cbfs.files)
+ cfile = cbfs.files['u-boot']
+ self.assertEqual(cfile.name, 'u-boot')
+ self.assertEqual(cfile.offset, 56)
+ self.assertEqual(cfile.data, COMPRESS_DATA)
+ self.assertEqual(cfile.ftype, cbfs_util.TYPE_RAW)
+ self.assertEqual(cfile.compress, cbfs_util.COMPRESS_LZ4)
+ self.assertEqual(cfile.memlen, len(COMPRESS_DATA))
+
+ self.assertIn('u-boot-dtb', cbfs.files)
+ cfile = cbfs.files['u-boot-dtb']
+ self.assertEqual(cfile.name, 'u-boot-dtb')
+ self.assertEqual(cfile.offset, 56)
+ self.assertEqual(cfile.data, COMPRESS_DATA)
+ self.assertEqual(cfile.ftype, cbfs_util.TYPE_RAW)
+ self.assertEqual(cfile.compress, cbfs_util.COMPRESS_LZMA)
+ self.assertEqual(cfile.memlen, len(COMPRESS_DATA))
+
+ cbfs_fname = self._get_expected_cbfs(size=size, compress=['lz4', 'lzma'])
+ self._compare_expected_cbfs(data, cbfs_fname)
+
+ def test_cbfs_raw_space(self):
+ """Test files with unused space in the CBFS"""
+ size = 0xf0
+ cbw = CbfsWriter(size)
+ cbw.add_file_raw('u-boot', U_BOOT_DATA)
+ cbw.add_file_raw('u-boot-dtb', U_BOOT_DTB_DATA)
+ data = cbw.get_data()
+ self._check_raw(data, size)
+ cbfs_fname = self._get_expected_cbfs(size=size)
+ self._compare_expected_cbfs(data, cbfs_fname)
+
+ def test_cbfs_offset(self):
+ """Test a CBFS with files at particular offsets"""
+ size = 0x200
+ cbw = CbfsWriter(size)
+ cbw.add_file_raw('u-boot', U_BOOT_DATA, 0x40)
+ cbw.add_file_raw('u-boot-dtb', U_BOOT_DTB_DATA, 0x140)
+
+ data = cbw.get_data()
+ cbfs = self._check_hdr(data, size)
+ self._check_uboot(cbfs, ftype=cbfs_util.TYPE_RAW, offset=0x40,
+ cbfs_offset=0x40)
+ self._check_dtb(cbfs, offset=0x40, cbfs_offset=0x140)
+
+ cbfs_fname = self._get_expected_cbfs(size=size, base=(0x40, 0x140))
+ self._compare_expected_cbfs(data, cbfs_fname)
+
+ def test_cbfs_invalid_file_type_header(self):
+ """Check handling of an invalid file type when outputting a header"""
+ size = 0xb0
+ cbw = CbfsWriter(size)
+ cfile = cbw.add_file_raw('u-boot', U_BOOT_DATA, 0)
+
+ # Change the type manually before generating the CBFS, and make sure
+ # that the generator complains
+ cfile.ftype = 0xff
+ with self.assertRaises(ValueError) as e:
+ cbw.get_data()
+ self.assertIn('Unknown file type 0xff', str(e.exception))
+
+ def test_cbfs_offset_conflict(self):
+ """Test a CBFS with files that want to overlap"""
+ size = 0x200
+ cbw = CbfsWriter(size)
+ cbw.add_file_raw('u-boot', U_BOOT_DATA, 0x40)
+ cbw.add_file_raw('u-boot-dtb', U_BOOT_DTB_DATA, 0x80)
+
+ with self.assertRaises(ValueError) as e:
+ cbw.get_data()
+ self.assertIn('No space for data before pad offset', str(e.exception))
+
+ def test_cbfs_check_offset(self):
+ """Test that we can discover the offset of a file after writing it"""
+ size = 0xb0
+ cbw = CbfsWriter(size)
+ cbw.add_file_raw('u-boot', U_BOOT_DATA)
+ cbw.add_file_raw('u-boot-dtb', U_BOOT_DTB_DATA)
+ data = cbw.get_data()
+
+ cbfs = cbfs_util.CbfsReader(data)
+ self.assertEqual(0x38, cbfs.files['u-boot'].cbfs_offset)
+ self.assertEqual(0x78, cbfs.files['u-boot-dtb'].cbfs_offset)
+
+
+if __name__ == '__main__':
+ unittest.main()
diff --git a/tools/binman/cmdline.py b/tools/binman/cmdline.py
index 3886d52..1e38593 100644
--- a/tools/binman/cmdline.py
+++ b/tools/binman/cmdline.py
@@ -5,7 +5,7 @@
# Command-line parser for binman
#
-from optparse import OptionParser
+from argparse import ArgumentParser
def ParseArgs(argv):
"""Parse the binman command-line arguments
@@ -17,50 +17,100 @@
options provides access to the options (e.g. option.debug)
args is a list of string arguments
"""
- parser = OptionParser()
- parser.add_option('-a', '--entry-arg', type='string', action='append',
- help='Set argument value arg=value')
- parser.add_option('-b', '--board', type='string',
- help='Board name to build')
- parser.add_option('-B', '--build-dir', type='string', default='b',
- help='Directory containing the build output')
- parser.add_option('-d', '--dt', type='string',
- help='Configuration file (.dtb) to use')
- parser.add_option('-D', '--debug', action='store_true',
- help='Enabling debugging (provides a full traceback on error)')
- parser.add_option('-E', '--entry-docs', action='store_true',
- help='Write out entry documentation (see README.entries)')
- parser.add_option('--fake-dtb', action='store_true',
- help='Use fake device tree contents (for testing only)')
- parser.add_option('-i', '--image', type='string', action='append',
- help='Image filename to build (if not specified, build all)')
- parser.add_option('-I', '--indir', action='append',
- help='Add a path to a directory to use for input files')
- parser.add_option('-H', '--full-help', action='store_true',
+ if '-H' in argv:
+ argv.append('build')
+
+ epilog = '''Binman creates and manipulate images for a board from a set of binaries. Binman is
+controlled by a description in the board device tree.'''
+
+ parser = ArgumentParser(epilog=epilog)
+ parser.add_argument('-B', '--build-dir', type=str, default='b',
+ help='Directory containing the build output')
+ parser.add_argument('-D', '--debug', action='store_true',
+ help='Enabling debugging (provides a full traceback on error)')
+ parser.add_argument('-H', '--full-help', action='store_true',
default=False, help='Display the README file')
- parser.add_option('-m', '--map', action='store_true',
+ parser.add_argument('--toolpath', type=str, action='append',
+ help='Add a path to the directories containing tools')
+ parser.add_argument('-v', '--verbosity', default=1,
+ type=int, help='Control verbosity: 0=silent, 1=warnings, 2=notices, '
+ '3=info, 4=detail, 5=debug')
+
+ subparsers = parser.add_subparsers(dest='cmd')
+
+ build_parser = subparsers.add_parser('build', help='Build firmware image')
+ build_parser.add_argument('-a', '--entry-arg', type=str, action='append',
+ help='Set argument value arg=value')
+ build_parser.add_argument('-b', '--board', type=str,
+ help='Board name to build')
+ build_parser.add_argument('-d', '--dt', type=str,
+ help='Configuration file (.dtb) to use')
+ build_parser.add_argument('--fake-dtb', action='store_true',
+ help='Use fake device tree contents (for testing only)')
+ build_parser.add_argument('-i', '--image', type=str, action='append',
+ help='Image filename to build (if not specified, build all)')
+ build_parser.add_argument('-I', '--indir', action='append',
+ help='Add a path to the list of directories to use for input files')
+ build_parser.add_argument('-m', '--map', action='store_true',
default=False, help='Output a map file for each image')
- parser.add_option('-O', '--outdir', type='string',
+ build_parser.add_argument('-O', '--outdir', type=str,
action='store', help='Path to directory to use for intermediate and '
'output files')
- parser.add_option('-p', '--preserve', action='store_true',\
+ build_parser.add_argument('-p', '--preserve', action='store_true',\
help='Preserve temporary output directory even if option -O is not '
'given')
- parser.add_option('-P', '--processes', type=int,
- help='set number of processes to use for running tests')
- parser.add_option('-t', '--test', action='store_true',
- default=False, help='run tests')
- parser.add_option('-T', '--test-coverage', action='store_true',
- default=False, help='run tests and check for 100% coverage')
- parser.add_option('-u', '--update-fdt', action='store_true',
+ build_parser.add_argument('-u', '--update-fdt', action='store_true',
default=False, help='Update the binman node with offset/size info')
- parser.add_option('-v', '--verbosity', default=1,
- type='int', help='Control verbosity: 0=silent, 1=progress, 3=full, '
- '4=debug')
- parser.usage += """
+ entry_parser = subparsers.add_parser('entry-docs',
+ help='Write out entry documentation (see README.entries)')
-Create images for a board from a set of binaries. It is controlled by a
-description in the board device tree."""
+ list_parser = subparsers.add_parser('ls', help='List files in an image')
+ list_parser.add_argument('-i', '--image', type=str, required=True,
+ help='Image filename to list')
+ list_parser.add_argument('paths', type=str, nargs='*',
+ help='Paths within file to list (wildcard)')
+
+ extract_parser = subparsers.add_parser('extract',
+ help='Extract files from an image')
+ extract_parser.add_argument('-i', '--image', type=str, required=True,
+ help='Image filename to extract')
+ extract_parser.add_argument('-f', '--filename', type=str,
+ help='Output filename to write to')
+ extract_parser.add_argument('-O', '--outdir', type=str, default='',
+ help='Path to directory to use for output files')
+ extract_parser.add_argument('paths', type=str, nargs='*',
+ help='Paths within file to extract (wildcard)')
+ extract_parser.add_argument('-U', '--uncompressed', action='store_true',
+ help='Output raw uncompressed data for compressed entries')
+
+ replace_parser = subparsers.add_parser('replace',
+ help='Replace entries in an image')
+ replace_parser.add_argument('-C', '--compressed', action='store_true',
+ help='Input data is already compressed if needed for the entry')
+ replace_parser.add_argument('-i', '--image', type=str, required=True,
+ help='Image filename to extract')
+ replace_parser.add_argument('-f', '--filename', type=str,
+ help='Input filename to read from')
+ replace_parser.add_argument('-F', '--fix-size', action='store_true',
+ help="Don't allow entries to be resized")
+ replace_parser.add_argument('-I', '--indir', type=str, default='',
+ help='Path to directory to use for input files')
+ replace_parser.add_argument('-m', '--map', action='store_true',
+ default=False, help='Output a map file for the updated image')
+ replace_parser.add_argument('paths', type=str, nargs='*',
+ help='Paths within file to extract (wildcard)')
+
+ test_parser = subparsers.add_parser('test', help='Run tests')
+ test_parser.add_argument('-P', '--processes', type=int,
+ help='set number of processes to use for running tests')
+ test_parser.add_argument('-T', '--test-coverage', action='store_true',
+ default=False, help='run tests and check for 100%% coverage')
+ test_parser.add_argument('-X', '--test-preserve-dirs', action='store_true',
+ help='Preserve and display test-created input directories; also '
+ 'preserve the output directory if a single test is run (pass test '
+ 'name at the end of the command line')
+ test_parser.add_argument('tests', nargs='*',
+ help='Test names to run (omit for all)')
return parser.parse_args(argv)
diff --git a/tools/binman/control.py b/tools/binman/control.py
index b32e4e1..9e75878 100644
--- a/tools/binman/control.py
+++ b/tools/binman/control.py
@@ -5,11 +5,14 @@
# Creates binary images from input files controlled by a description
#
+from __future__ import print_function
+
from collections import OrderedDict
import os
import sys
import tools
+import cbfs_util
import command
import elf
from image import Image
@@ -64,19 +67,399 @@
from entry import Entry
Entry.WriteDocs(modules, test_missing)
-def Binman(options, args):
+
+def ListEntries(image_fname, entry_paths):
+ """List the entries in an image
+
+ This decodes the supplied image and displays a table of entries from that
+ image, preceded by a header.
+
+ Args:
+ image_fname: Image filename to process
+ entry_paths: List of wildcarded paths (e.g. ['*dtb*', 'u-boot*',
+ 'section/u-boot'])
+ """
+ image = Image.FromFile(image_fname)
+
+ entries, lines, widths = image.GetListEntries(entry_paths)
+
+ num_columns = len(widths)
+ for linenum, line in enumerate(lines):
+ if linenum == 1:
+ # Print header line
+ print('-' * (sum(widths) + num_columns * 2))
+ out = ''
+ for i, item in enumerate(line):
+ width = -widths[i]
+ if item.startswith('>'):
+ width = -width
+ item = item[1:]
+ txt = '%*s ' % (width, item)
+ out += txt
+ print(out.rstrip())
+
+
+def ReadEntry(image_fname, entry_path, decomp=True):
+ """Extract an entry from an image
+
+ This extracts the data from a particular entry in an image
+
+ Args:
+ image_fname: Image filename to process
+ entry_path: Path to entry to extract
+ decomp: True to return uncompressed data, if the data is compress
+ False to return the raw data
+
+ Returns:
+ data extracted from the entry
+ """
+ image = Image.FromFile(image_fname)
+ entry = image.FindEntryPath(entry_path)
+ return entry.ReadData(decomp)
+
+
+def ExtractEntries(image_fname, output_fname, outdir, entry_paths,
+ decomp=True):
+ """Extract the data from one or more entries and write it to files
+
+ Args:
+ image_fname: Image filename to process
+ output_fname: Single output filename to use if extracting one file, None
+ otherwise
+ outdir: Output directory to use (for any number of files), else None
+ entry_paths: List of entry paths to extract
+ decomp: True to decompress the entry data
+
+ Returns:
+ List of EntryInfo records that were written
+ """
+ image = Image.FromFile(image_fname)
+
+ # Output an entry to a single file, as a special case
+ if output_fname:
+ if not entry_paths:
+ raise ValueError('Must specify an entry path to write with -f')
+ if len(entry_paths) != 1:
+ raise ValueError('Must specify exactly one entry path to write with -f')
+ entry = image.FindEntryPath(entry_paths[0])
+ data = entry.ReadData(decomp)
+ tools.WriteFile(output_fname, data)
+ tout.Notice("Wrote %#x bytes to file '%s'" % (len(data), output_fname))
+ return
+
+ # Otherwise we will output to a path given by the entry path of each entry.
+ # This means that entries will appear in subdirectories if they are part of
+ # a sub-section.
+ einfos = image.GetListEntries(entry_paths)[0]
+ tout.Notice('%d entries match and will be written' % len(einfos))
+ for einfo in einfos:
+ entry = einfo.entry
+ data = entry.ReadData(decomp)
+ path = entry.GetPath()[1:]
+ fname = os.path.join(outdir, path)
+
+ # If this entry has children, create a directory for it and put its
+ # data in a file called 'root' in that directory
+ if entry.GetEntries():
+ if not os.path.exists(fname):
+ os.makedirs(fname)
+ fname = os.path.join(fname, 'root')
+ tout.Notice("Write entry '%s' to '%s'" % (entry.GetPath(), fname))
+ tools.WriteFile(fname, data)
+ return einfos
+
+
+def BeforeReplace(image, allow_resize):
+ """Handle getting an image ready for replacing entries in it
+
+ Args:
+ image: Image to prepare
+ """
+ state.PrepareFromLoadedData(image)
+ image.LoadData()
+
+ # If repacking, drop the old offset/size values except for the original
+ # ones, so we are only left with the constraints.
+ if allow_resize:
+ image.ResetForPack()
+
+
+def ReplaceOneEntry(image, entry, data, do_compress, allow_resize):
+ """Handle replacing a single entry an an image
+
+ Args:
+ image: Image to update
+ entry: Entry to write
+ data: Data to replace with
+ do_compress: True to compress the data if needed, False if data is
+ already compressed so should be used as is
+ allow_resize: True to allow entries to change size (this does a re-pack
+ of the entries), False to raise an exception
+ """
+ if not entry.WriteData(data, do_compress):
+ if not image.allow_repack:
+ entry.Raise('Entry data size does not match, but allow-repack is not present for this image')
+ if not allow_resize:
+ entry.Raise('Entry data size does not match, but resize is disabled')
+
+
+def AfterReplace(image, allow_resize, write_map):
+ """Handle write out an image after replacing entries in it
+
+ Args:
+ image: Image to write
+ allow_resize: True to allow entries to change size (this does a re-pack
+ of the entries), False to raise an exception
+ write_map: True to write a map file
+ """
+ tout.Info('Processing image')
+ ProcessImage(image, update_fdt=True, write_map=write_map,
+ get_contents=False, allow_resize=allow_resize)
+
+
+def WriteEntryToImage(image, entry, data, do_compress=True, allow_resize=True,
+ write_map=False):
+ BeforeReplace(image, allow_resize)
+ tout.Info('Writing data to %s' % entry.GetPath())
+ ReplaceOneEntry(image, entry, data, do_compress, allow_resize)
+ AfterReplace(image, allow_resize=allow_resize, write_map=write_map)
+
+
+def WriteEntry(image_fname, entry_path, data, do_compress=True,
+ allow_resize=True, write_map=False):
+ """Replace an entry in an image
+
+ This replaces the data in a particular entry in an image. This size of the
+ new data must match the size of the old data unless allow_resize is True.
+
+ Args:
+ image_fname: Image filename to process
+ entry_path: Path to entry to extract
+ data: Data to replace with
+ do_compress: True to compress the data if needed, False if data is
+ already compressed so should be used as is
+ allow_resize: True to allow entries to change size (this does a re-pack
+ of the entries), False to raise an exception
+ write_map: True to write a map file
+
+ Returns:
+ Image object that was updated
+ """
+ tout.Info("Write entry '%s', file '%s'" % (entry_path, image_fname))
+ image = Image.FromFile(image_fname)
+ entry = image.FindEntryPath(entry_path)
+ WriteEntryToImage(image, entry, data, do_compress=do_compress,
+ allow_resize=allow_resize, write_map=write_map)
+
+ return image
+
+
+def ReplaceEntries(image_fname, input_fname, indir, entry_paths,
+ do_compress=True, allow_resize=True, write_map=False):
+ """Replace the data from one or more entries from input files
+
+ Args:
+ image_fname: Image filename to process
+ input_fname: Single input ilename to use if replacing one file, None
+ otherwise
+ indir: Input directory to use (for any number of files), else None
+ entry_paths: List of entry paths to extract
+ do_compress: True if the input data is uncompressed and may need to be
+ compressed if the entry requires it, False if the data is already
+ compressed.
+ write_map: True to write a map file
+
+ Returns:
+ List of EntryInfo records that were written
+ """
+ image = Image.FromFile(image_fname)
+
+ # Replace an entry from a single file, as a special case
+ if input_fname:
+ if not entry_paths:
+ raise ValueError('Must specify an entry path to read with -f')
+ if len(entry_paths) != 1:
+ raise ValueError('Must specify exactly one entry path to write with -f')
+ entry = image.FindEntryPath(entry_paths[0])
+ data = tools.ReadFile(input_fname)
+ tout.Notice("Read %#x bytes from file '%s'" % (len(data), input_fname))
+ WriteEntryToImage(image, entry, data, do_compress=do_compress,
+ allow_resize=allow_resize, write_map=write_map)
+ return
+
+ # Otherwise we will input from a path given by the entry path of each entry.
+ # This means that files must appear in subdirectories if they are part of
+ # a sub-section.
+ einfos = image.GetListEntries(entry_paths)[0]
+ tout.Notice("Replacing %d matching entries in image '%s'" %
+ (len(einfos), image_fname))
+
+ BeforeReplace(image, allow_resize)
+
+ for einfo in einfos:
+ entry = einfo.entry
+ if entry.GetEntries():
+ tout.Info("Skipping section entry '%s'" % entry.GetPath())
+ continue
+
+ path = entry.GetPath()[1:]
+ fname = os.path.join(indir, path)
+
+ if os.path.exists(fname):
+ tout.Notice("Write entry '%s' from file '%s'" %
+ (entry.GetPath(), fname))
+ data = tools.ReadFile(fname)
+ ReplaceOneEntry(image, entry, data, do_compress, allow_resize)
+ else:
+ tout.Warning("Skipping entry '%s' from missing file '%s'" %
+ (entry.GetPath(), fname))
+
+ AfterReplace(image, allow_resize=allow_resize, write_map=write_map)
+ return image
+
+
+def PrepareImagesAndDtbs(dtb_fname, select_images, update_fdt):
+ """Prepare the images to be processed and select the device tree
+
+ This function:
+ - reads in the device tree
+ - finds and scans the binman node to create all entries
+ - selects which images to build
+ - Updates the device tress with placeholder properties for offset,
+ image-pos, etc.
+
+ Args:
+ dtb_fname: Filename of the device tree file to use (.dts or .dtb)
+ selected_images: List of images to output, or None for all
+ update_fdt: True to update the FDT wth entry offsets, etc.
+ """
+ # Import these here in case libfdt.py is not available, in which case
+ # the above help option still works.
+ import fdt
+ import fdt_util
+ global images
+
+ # Get the device tree ready by compiling it and copying the compiled
+ # output into a file in our output directly. Then scan it for use
+ # in binman.
+ dtb_fname = fdt_util.EnsureCompiled(dtb_fname)
+ fname = tools.GetOutputFilename('u-boot.dtb.out')
+ tools.WriteFile(fname, tools.ReadFile(dtb_fname))
+ dtb = fdt.FdtScan(fname)
+
+ node = _FindBinmanNode(dtb)
+ if not node:
+ raise ValueError("Device tree '%s' does not have a 'binman' "
+ "node" % dtb_fname)
+
+ images = _ReadImageDesc(node)
+
+ if select_images:
+ skip = []
+ new_images = OrderedDict()
+ for name, image in images.items():
+ if name in select_images:
+ new_images[name] = image
+ else:
+ skip.append(name)
+ images = new_images
+ tout.Notice('Skipping images: %s' % ', '.join(skip))
+
+ state.Prepare(images, dtb)
+
+ # Prepare the device tree by making sure that any missing
+ # properties are added (e.g. 'pos' and 'size'). The values of these
+ # may not be correct yet, but we add placeholders so that the
+ # size of the device tree is correct. Later, in
+ # SetCalculatedProperties() we will insert the correct values
+ # without changing the device-tree size, thus ensuring that our
+ # entry offsets remain the same.
+ for image in images.values():
+ image.ExpandEntries()
+ if update_fdt:
+ image.AddMissingProperties()
+ image.ProcessFdt(dtb)
+
+ for dtb_item in state.GetAllFdts():
+ dtb_item.Sync(auto_resize=True)
+ dtb_item.Pack()
+ dtb_item.Flush()
+ return images
+
+
+def ProcessImage(image, update_fdt, write_map, get_contents=True,
+ allow_resize=True):
+ """Perform all steps for this image, including checking and # writing it.
+
+ This means that errors found with a later image will be reported after
+ earlier images are already completed and written, but that does not seem
+ important.
+
+ Args:
+ image: Image to process
+ update_fdt: True to update the FDT wth entry offsets, etc.
+ write_map: True to write a map file
+ get_contents: True to get the image contents from files, etc., False if
+ the contents is already present
+ allow_resize: True to allow entries to change size (this does a re-pack
+ of the entries), False to raise an exception
+ """
+ if get_contents:
+ image.GetEntryContents()
+ image.GetEntryOffsets()
+
+ # We need to pack the entries to figure out where everything
+ # should be placed. This sets the offset/size of each entry.
+ # However, after packing we call ProcessEntryContents() which
+ # may result in an entry changing size. In that case we need to
+ # do another pass. Since the device tree often contains the
+ # final offset/size information we try to make space for this in
+ # AddMissingProperties() above. However, if the device is
+ # compressed we cannot know this compressed size in advance,
+ # since changing an offset from 0x100 to 0x104 (for example) can
+ # alter the compressed size of the device tree. So we need a
+ # third pass for this.
+ passes = 5
+ for pack_pass in range(passes):
+ try:
+ image.PackEntries()
+ image.CheckSize()
+ image.CheckEntries()
+ except Exception as e:
+ if write_map:
+ fname = image.WriteMap()
+ print("Wrote map file '%s' to show errors" % fname)
+ raise
+ image.SetImagePos()
+ if update_fdt:
+ image.SetCalculatedProperties()
+ for dtb_item in state.GetAllFdts():
+ dtb_item.Sync()
+ dtb_item.Flush()
+ sizes_ok = image.ProcessEntryContents()
+ if sizes_ok:
+ break
+ image.ResetForPack()
+ if not sizes_ok:
+ image.Raise('Entries changed size after packing (tried %s passes)' %
+ passes)
+
+ image.WriteSymbols()
+ image.BuildImage()
+ if write_map:
+ image.WriteMap()
+
+
+def Binman(args):
"""The main control code for binman
This assumes that help and test options have already been dealt with. It
deals with the core task of building images.
Args:
- options: Command line options object
- args: Command line arguments (list of strings)
+ args: Command line arguments Namespace object
"""
- global images
-
- if options.full_help:
+ if args.full_help:
pager = os.getenv('PAGER')
if not pager:
pager = 'more'
@@ -85,106 +468,64 @@
command.Run(pager, fname)
return 0
+ if args.cmd == 'ls':
+ try:
+ tools.PrepareOutputDir(None)
+ ListEntries(args.image, args.paths)
+ finally:
+ tools.FinaliseOutputDir()
+ return 0
+
+ if args.cmd == 'extract':
+ try:
+ tools.PrepareOutputDir(None)
+ ExtractEntries(args.image, args.filename, args.outdir, args.paths,
+ not args.uncompressed)
+ finally:
+ tools.FinaliseOutputDir()
+ return 0
+
+ if args.cmd == 'replace':
+ try:
+ tools.PrepareOutputDir(None)
+ ReplaceEntries(args.image, args.filename, args.indir, args.paths,
+ do_compress=not args.compressed,
+ allow_resize=not args.fix_size, write_map=args.map)
+ finally:
+ tools.FinaliseOutputDir()
+ return 0
+
# Try to figure out which device tree contains our image description
- if options.dt:
- dtb_fname = options.dt
+ if args.dt:
+ dtb_fname = args.dt
else:
- board = options.board
+ board = args.board
if not board:
raise ValueError('Must provide a board to process (use -b <board>)')
- board_pathname = os.path.join(options.build_dir, board)
+ board_pathname = os.path.join(args.build_dir, board)
dtb_fname = os.path.join(board_pathname, 'u-boot.dtb')
- if not options.indir:
- options.indir = ['.']
- options.indir.append(board_pathname)
+ if not args.indir:
+ args.indir = ['.']
+ args.indir.append(board_pathname)
try:
- # Import these here in case libfdt.py is not available, in which case
- # the above help option still works.
- import fdt
- import fdt_util
-
- tout.Init(options.verbosity)
- elf.debug = options.debug
- state.use_fake_dtb = options.fake_dtb
+ tout.Init(args.verbosity)
+ elf.debug = args.debug
+ cbfs_util.VERBOSE = args.verbosity > 2
+ state.use_fake_dtb = args.fake_dtb
try:
- tools.SetInputDirs(options.indir)
- tools.PrepareOutputDir(options.outdir, options.preserve)
- state.SetEntryArgs(options.entry_arg)
+ tools.SetInputDirs(args.indir)
+ tools.PrepareOutputDir(args.outdir, args.preserve)
+ tools.SetToolPaths(args.toolpath)
+ state.SetEntryArgs(args.entry_arg)
- # Get the device tree ready by compiling it and copying the compiled
- # output into a file in our output directly. Then scan it for use
- # in binman.
- dtb_fname = fdt_util.EnsureCompiled(dtb_fname)
- fname = tools.GetOutputFilename('u-boot.dtb.out')
- tools.WriteFile(fname, tools.ReadFile(dtb_fname))
- dtb = fdt.FdtScan(fname)
-
- node = _FindBinmanNode(dtb)
- if not node:
- raise ValueError("Device tree '%s' does not have a 'binman' "
- "node" % dtb_fname)
-
- images = _ReadImageDesc(node)
-
- if options.image:
- skip = []
- for name, image in images.iteritems():
- if name not in options.image:
- del images[name]
- skip.append(name)
- if skip and options.verbosity >= 2:
- print 'Skipping images: %s' % ', '.join(skip)
-
- state.Prepare(images, dtb)
-
- # Prepare the device tree by making sure that any missing
- # properties are added (e.g. 'pos' and 'size'). The values of these
- # may not be correct yet, but we add placeholders so that the
- # size of the device tree is correct. Later, in
- # SetCalculatedProperties() we will insert the correct values
- # without changing the device-tree size, thus ensuring that our
- # entry offsets remain the same.
+ images = PrepareImagesAndDtbs(dtb_fname, args.image,
+ args.update_fdt)
for image in images.values():
- image.ExpandEntries()
- if options.update_fdt:
- image.AddMissingProperties()
- image.ProcessFdt(dtb)
-
- for dtb_item in state.GetFdts():
- dtb_item.Sync(auto_resize=True)
- dtb_item.Pack()
- dtb_item.Flush()
-
- for image in images.values():
- # Perform all steps for this image, including checking and
- # writing it. This means that errors found with a later
- # image will be reported after earlier images are already
- # completed and written, but that does not seem important.
- image.GetEntryContents()
- image.GetEntryOffsets()
- try:
- image.PackEntries()
- image.CheckSize()
- image.CheckEntries()
- except Exception as e:
- if options.map:
- fname = image.WriteMap()
- print "Wrote map file '%s' to show errors" % fname
- raise
- image.SetImagePos()
- if options.update_fdt:
- image.SetCalculatedProperties()
- for dtb_item in state.GetFdts():
- dtb_item.Sync()
- image.ProcessEntryContents()
- image.WriteSymbols()
- image.BuildImage()
- if options.map:
- image.WriteMap()
+ ProcessImage(image, args.update_fdt, args.map)
# Write the updated FDTs to our output files
- for dtb_item in state.GetFdts():
+ for dtb_item in state.GetAllFdts():
tools.WriteFile(dtb_item._fname, dtb_item.GetContents())
finally:
diff --git a/tools/binman/elf.py b/tools/binman/elf.py
index 97df8e3..af40024 100644
--- a/tools/binman/elf.py
+++ b/tools/binman/elf.py
@@ -5,19 +5,37 @@
# Handle various things related to ELF images
#
+from __future__ import print_function
+
from collections import namedtuple, OrderedDict
import command
+import io
import os
import re
+import shutil
import struct
+import tempfile
import tools
+import tout
-# This is enabled from control.py
-debug = False
+ELF_TOOLS = True
+try:
+ from elftools.elf.elffile import ELFFile
+ from elftools.elf.sections import SymbolTableSection
+except: # pragma: no cover
+ ELF_TOOLS = False
Symbol = namedtuple('Symbol', ['section', 'address', 'size', 'weak'])
+# Information about an ELF file:
+# data: Extracted program contents of ELF file (this would be loaded by an
+# ELF loader when reading this file
+# load: Load address of code
+# entry: Entry address of code
+# memsize: Number of bytes in memory occupied by loading this ELF file
+ElfInfo = namedtuple('ElfInfo', ['data', 'load', 'entry', 'memsize'])
+
def GetSymbols(fname, patterns):
"""Get the symbols from an ELF file
@@ -59,7 +77,7 @@
flags[1] == 'w')
# Sort dict by address
- return OrderedDict(sorted(syms.iteritems(), key=lambda x: x[1].address))
+ return OrderedDict(sorted(syms.items(), key=lambda x: x[1].address))
def GetSymbolAddress(fname, sym_name):
"""Get a value of a symbol from an ELF file
@@ -98,7 +116,7 @@
base = syms.get('__image_copy_start')
if not base:
return
- for name, sym in syms.iteritems():
+ for name, sym in syms.items():
if name.startswith('_binman'):
msg = ("Section '%s': Symbol '%s'\n in entry '%s'" %
(section.GetPath(), name, entry.GetPath()))
@@ -123,8 +141,161 @@
value = -1
pack_string = pack_string.lower()
value_bytes = struct.pack(pack_string, value)
- if debug:
- print('%s:\n insert %s, offset %x, value %x, length %d' %
- (msg, name, offset, value, len(value_bytes)))
+ tout.Debug('%s:\n insert %s, offset %x, value %x, length %d' %
+ (msg, name, offset, value, len(value_bytes)))
entry.data = (entry.data[:offset] + value_bytes +
entry.data[offset + sym.size:])
+
+def MakeElf(elf_fname, text, data):
+ """Make an elf file with the given data in a single section
+
+ The output file has a several section including '.text' and '.data',
+ containing the info provided in arguments.
+
+ Args:
+ elf_fname: Output filename
+ text: Text (code) to put in the file's .text section
+ data: Data to put in the file's .data section
+ """
+ outdir = tempfile.mkdtemp(prefix='binman.elf.')
+ s_file = os.path.join(outdir, 'elf.S')
+
+ # Spilt the text into two parts so that we can make the entry point two
+ # bytes after the start of the text section
+ text_bytes1 = ['\t.byte\t%#x' % tools.ToByte(byte) for byte in text[:2]]
+ text_bytes2 = ['\t.byte\t%#x' % tools.ToByte(byte) for byte in text[2:]]
+ data_bytes = ['\t.byte\t%#x' % tools.ToByte(byte) for byte in data]
+ with open(s_file, 'w') as fd:
+ print('''/* Auto-generated C program to produce an ELF file for testing */
+
+.section .text
+.code32
+.globl _start
+.type _start, @function
+%s
+_start:
+%s
+.ident "comment"
+
+.comm fred,8,4
+
+.section .empty
+.globl _empty
+_empty:
+.byte 1
+
+.globl ernie
+.data
+.type ernie, @object
+.size ernie, 4
+ernie:
+%s
+''' % ('\n'.join(text_bytes1), '\n'.join(text_bytes2), '\n'.join(data_bytes)),
+ file=fd)
+ lds_file = os.path.join(outdir, 'elf.lds')
+
+ # Use a linker script to set the alignment and text address.
+ with open(lds_file, 'w') as fd:
+ print('''/* Auto-generated linker script to produce an ELF file for testing */
+
+PHDRS
+{
+ text PT_LOAD ;
+ data PT_LOAD ;
+ empty PT_LOAD FLAGS ( 6 ) ;
+ note PT_NOTE ;
+}
+
+SECTIONS
+{
+ . = 0xfef20000;
+ ENTRY(_start)
+ .text . : SUBALIGN(0)
+ {
+ *(.text)
+ } :text
+ .data : {
+ *(.data)
+ } :data
+ _bss_start = .;
+ .empty : {
+ *(.empty)
+ } :empty
+ .note : {
+ *(.comment)
+ } :note
+ .bss _bss_start (OVERLAY) : {
+ *(.bss)
+ }
+}
+''', file=fd)
+ # -static: Avoid requiring any shared libraries
+ # -nostdlib: Don't link with C library
+ # -Wl,--build-id=none: Don't generate a build ID, so that we just get the
+ # text section at the start
+ # -m32: Build for 32-bit x86
+ # -T...: Specifies the link script, which sets the start address
+ stdout = command.Output('cc', '-static', '-nostdlib', '-Wl,--build-id=none',
+ '-m32','-T', lds_file, '-o', elf_fname, s_file)
+ shutil.rmtree(outdir)
+
+def DecodeElf(data, location):
+ """Decode an ELF file and return information about it
+
+ Args:
+ data: Data from ELF file
+ location: Start address of data to return
+
+ Returns:
+ ElfInfo object containing information about the decoded ELF file
+ """
+ file_size = len(data)
+ with io.BytesIO(data) as fd:
+ elf = ELFFile(fd)
+ data_start = 0xffffffff;
+ data_end = 0;
+ mem_end = 0;
+ virt_to_phys = 0;
+
+ for i in range(elf.num_segments()):
+ segment = elf.get_segment(i)
+ if segment['p_type'] != 'PT_LOAD' or not segment['p_memsz']:
+ skipped = 1 # To make code-coverage see this line
+ continue
+ start = segment['p_paddr']
+ mend = start + segment['p_memsz']
+ rend = start + segment['p_filesz']
+ data_start = min(data_start, start)
+ data_end = max(data_end, rend)
+ mem_end = max(mem_end, mend)
+ if not virt_to_phys:
+ virt_to_phys = segment['p_paddr'] - segment['p_vaddr']
+
+ output = bytearray(data_end - data_start)
+ for i in range(elf.num_segments()):
+ segment = elf.get_segment(i)
+ if segment['p_type'] != 'PT_LOAD' or not segment['p_memsz']:
+ skipped = 1 # To make code-coverage see this line
+ continue
+ start = segment['p_paddr']
+ offset = 0
+ if start < location:
+ offset = location - start
+ start = location
+ # A legal ELF file can have a program header with non-zero length
+ # but zero-length file size and a non-zero offset which, added
+ # together, are greater than input->size (i.e. the total file size).
+ # So we need to not even test in the case that p_filesz is zero.
+ # Note: All of this code is commented out since we don't have a test
+ # case for it.
+ size = segment['p_filesz']
+ #if not size:
+ #continue
+ #end = segment['p_offset'] + segment['p_filesz']
+ #if end > file_size:
+ #raise ValueError('Underflow copying out the segment. File has %#x bytes left, segment end is %#x\n',
+ #file_size, end)
+ output[start - data_start:start - data_start + size] = (
+ segment.data()[offset:])
+ return ElfInfo(output, data_start, elf.header['e_entry'] + virt_to_phys,
+ mem_end - data_start)
diff --git a/tools/binman/elf_test.py b/tools/binman/elf_test.py
index b68530c..416e43b 100644
--- a/tools/binman/elf_test.py
+++ b/tools/binman/elf_test.py
@@ -5,12 +5,16 @@
# Test for the elf module
import os
+import shutil
import sys
+import tempfile
import unittest
+import command
import elf
import test_util
import tools
+import tout
binman_dir = os.path.dirname(os.path.realpath(sys.argv[0]))
@@ -22,7 +26,7 @@
"""
def __init__(self, contents_size):
self.contents_size = contents_size
- self.data = 'a' * contents_size
+ self.data = tools.GetBytes(ord('a'), contents_size)
def GetPath(self):
return 'entry_path'
@@ -122,18 +126,59 @@
section = FakeSection(sym_value=None)
elf_fname = os.path.join(binman_dir, 'test', 'u_boot_binman_syms')
syms = elf.LookupAndWriteSymbols(elf_fname, entry, section)
- self.assertEqual(chr(255) * 16 + 'a' * 4, entry.data)
+ self.assertEqual(tools.GetBytes(255, 16) + tools.GetBytes(ord('a'), 4),
+ entry.data)
def testDebug(self):
"""Check that enabling debug in the elf module produced debug output"""
- elf.debug = True
- entry = FakeEntry(20)
- section = FakeSection()
- elf_fname = os.path.join(binman_dir, 'test', 'u_boot_binman_syms')
- with test_util.capture_sys_output() as (stdout, stderr):
- syms = elf.LookupAndWriteSymbols(elf_fname, entry, section)
- elf.debug = False
- self.assertTrue(len(stdout.getvalue()) > 0)
+ try:
+ tout.Init(tout.DEBUG)
+ entry = FakeEntry(20)
+ section = FakeSection()
+ elf_fname = os.path.join(binman_dir, 'test', 'u_boot_binman_syms')
+ with test_util.capture_sys_output() as (stdout, stderr):
+ syms = elf.LookupAndWriteSymbols(elf_fname, entry, section)
+ self.assertTrue(len(stdout.getvalue()) > 0)
+ finally:
+ tout.Init(tout.WARNING)
+
+ def testMakeElf(self):
+ """Test for the MakeElf function"""
+ outdir = tempfile.mkdtemp(prefix='elf.')
+ expected_text = b'1234'
+ expected_data = b'wxyz'
+ elf_fname = os.path.join(outdir, 'elf')
+ bin_fname = os.path.join(outdir, 'elf')
+
+ # Make an Elf file and then convert it to a fkat binary file. This
+ # should produce the original data.
+ elf.MakeElf(elf_fname, expected_text, expected_data)
+ stdout = command.Output('objcopy', '-O', 'binary', elf_fname, bin_fname)
+ with open(bin_fname, 'rb') as fd:
+ data = fd.read()
+ self.assertEqual(expected_text + expected_data, data)
+ shutil.rmtree(outdir)
+
+ def testDecodeElf(self):
+ """Test for the MakeElf function"""
+ if not elf.ELF_TOOLS:
+ self.skipTest('Python elftools not available')
+ outdir = tempfile.mkdtemp(prefix='elf.')
+ expected_text = b'1234'
+ expected_data = b'wxyz'
+ elf_fname = os.path.join(outdir, 'elf')
+ elf.MakeElf(elf_fname, expected_text, expected_data)
+ data = tools.ReadFile(elf_fname)
+
+ load = 0xfef20000
+ entry = load + 2
+ expected = expected_text + expected_data
+ self.assertEqual(elf.ElfInfo(expected, load, entry, len(expected)),
+ elf.DecodeElf(data, 0))
+ self.assertEqual(elf.ElfInfo(b'\0\0' + expected[2:],
+ load, entry, len(expected)),
+ elf.DecodeElf(data, load + 2))
+ #shutil.rmtree(outdir)
if __name__ == '__main__':
diff --git a/tools/binman/entry.py b/tools/binman/entry.py
index 648cfd2..6a2c6e0 100644
--- a/tools/binman/entry.py
+++ b/tools/binman/entry.py
@@ -18,12 +18,13 @@
have_importlib = False
import os
-from sets import Set
import sys
import fdt_util
import state
import tools
+from tools import ToHex, ToHexSize
+import tout
modules = {}
@@ -34,6 +35,10 @@
# device-tree properties.
EntryArg = namedtuple('EntryArg', ['name', 'datatype'])
+# Information about an entry for use when displaying summaries
+EntryInfo = namedtuple('EntryInfo', ['indent', 'name', 'etype', 'size',
+ 'image_pos', 'uncomp_size', 'offset',
+ 'entry'])
class Entry(object):
"""An Entry in the section
@@ -52,6 +57,8 @@
offset: Offset of entry within the section, None if not known yet (in
which case it will be calculated by Pack())
size: Entry size in bytes, None if not known
+ uncomp_size: Size of uncompressed data in bytes, if the entry is
+ compressed, else None
contents_size: Size of contents in bytes, 0 by default
align: Entry start offset alignment, or None
align_size: Entry size alignment, or None
@@ -59,14 +66,18 @@
pad_before: Number of pad bytes before the contents, 0 if none
pad_after: Number of pad bytes after the contents, 0 if none
data: Contents of entry (string of bytes)
+ compress: Compression algoithm used (e.g. 'lz4'), 'none' if none
+ orig_offset: Original offset value read from node
+ orig_size: Original size value read from node
"""
- def __init__(self, section, etype, node, read_node=True, name_prefix=''):
+ def __init__(self, section, etype, node, name_prefix=''):
self.section = section
self.etype = etype
self._node = node
self.name = node and (name_prefix + node.name) or 'none'
self.offset = None
self.size = None
+ self.uncomp_size = None
self.data = None
self.contents_size = 0
self.align = None
@@ -77,15 +88,13 @@
self.offset_unset = False
self.image_pos = None
self._expand_size = False
- if read_node:
- self.ReadNode()
+ self.compress = 'none'
@staticmethod
- def Lookup(section, node_path, etype):
+ def Lookup(node_path, etype):
"""Look up the entry class for a node.
Args:
- section: Section object containing this node
node_node: Path name of Node object containing information about
the entry to create (used for errors)
etype: Entry type to use
@@ -136,7 +145,7 @@
"""
if not etype:
etype = fdt_util.GetString(node, 'type', node.name)
- obj = Entry.Lookup(section, node.path, etype)
+ obj = Entry.Lookup(node.path, etype)
# Call its constructor to get the object we want.
return obj(section, etype, node)
@@ -144,12 +153,25 @@
def ReadNode(self):
"""Read entry information from the node
+ This must be called as the first thing after the Entry is created.
+
This reads all the fields we recognise from the node, ready for use.
"""
if 'pos' in self._node.props:
self.Raise("Please use 'offset' instead of 'pos'")
self.offset = fdt_util.GetInt(self._node, 'offset')
self.size = fdt_util.GetInt(self._node, 'size')
+ self.orig_offset = fdt_util.GetInt(self._node, 'orig-offset')
+ self.orig_size = fdt_util.GetInt(self._node, 'orig-size')
+ if self.GetImage().copy_to_orig:
+ self.orig_offset = self.offset
+ self.orig_size = self.size
+
+ # These should not be set in input files, but are set in an FDT map,
+ # which is also read by this code.
+ self.image_pos = fdt_util.GetInt(self._node, 'image-pos')
+ self.uncomp_size = fdt_util.GetInt(self._node, 'uncomp-size')
+
self.align = fdt_util.GetInt(self._node, 'align')
if tools.NotPowerOfTwo(self.align):
raise ValueError("Node '%s': Alignment %s must be a power of two" %
@@ -158,8 +180,8 @@
self.pad_after = fdt_util.GetInt(self._node, 'pad-after', 0)
self.align_size = fdt_util.GetInt(self._node, 'align-size')
if tools.NotPowerOfTwo(self.align_size):
- raise ValueError("Node '%s': Alignment size %s must be a power "
- "of two" % (self._node.path, self.align_size))
+ self.Raise("Alignment size %s must be a power of two" %
+ self.align_size)
self.align_end = fdt_util.GetInt(self._node, 'align-end')
self.offset_unset = fdt_util.GetBool(self._node, 'offset-unset')
self.expand_size = fdt_util.GetBool(self._node, 'expand-size')
@@ -167,19 +189,18 @@
def GetDefaultFilename(self):
return None
- def GetFdtSet(self):
- """Get the set of device trees used by this entry
+ def GetFdts(self):
+ """Get the device trees used by this entry
Returns:
- Set containing the filename from this entry, if it is a .dtb, else
- an empty set
+ Empty dict, if this entry is not a .dtb, otherwise:
+ Dict:
+ key: Filename from this entry (without the path)
+ value: Tuple:
+ Fdt object for this dtb, or None if not available
+ Filename of file containing this dtb
"""
- fname = self.GetDefaultFilename()
- # It would be better to use isinstance(self, Entry_blob_dtb) here but
- # we cannot access Entry_blob_dtb
- if fname and fname.endswith('.dtb'):
- return Set([fname])
- return Set()
+ return {}
def ExpandEntries(self):
pass
@@ -189,6 +210,14 @@
for prop in ['offset', 'size', 'image-pos']:
if not prop in self._node.props:
state.AddZeroProp(self._node, prop)
+ if self.GetImage().allow_repack:
+ if self.orig_offset is not None:
+ state.AddZeroProp(self._node, 'orig-offset', True)
+ if self.orig_size is not None:
+ state.AddZeroProp(self._node, 'orig-size', True)
+
+ if self.compress != 'none':
+ state.AddZeroProp(self._node, 'uncomp-size')
err = state.CheckAddHashProp(self._node)
if err:
self.Raise(err)
@@ -197,8 +226,15 @@
"""Set the value of device-tree properties calculated by binman"""
state.SetInt(self._node, 'offset', self.offset)
state.SetInt(self._node, 'size', self.size)
- state.SetInt(self._node, 'image-pos',
- self.image_pos - self.section.GetRootSkipAtStart())
+ base = self.section.GetRootSkipAtStart() if self.section else 0
+ state.SetInt(self._node, 'image-pos', self.image_pos - base)
+ if self.GetImage().allow_repack:
+ if self.orig_offset is not None:
+ state.SetInt(self._node, 'orig-offset', self.orig_offset, True)
+ if self.orig_size is not None:
+ state.SetInt(self._node, 'orig-size', self.orig_size, True)
+ if self.uncomp_size is not None:
+ state.SetInt(self._node, 'uncomp-size', self.uncomp_size)
state.CheckSetHashValue(self._node, self.GetData)
def ProcessFdt(self, fdt):
@@ -230,26 +266,47 @@
This sets both the data and content_size properties
Args:
- data: Data to set to the contents (string)
+ data: Data to set to the contents (bytes)
"""
self.data = data
self.contents_size = len(self.data)
def ProcessContentsUpdate(self, data):
- """Update the contens of an entry, after the size is fixed
+ """Update the contents of an entry, after the size is fixed
- This checks that the new data is the same size as the old.
+ This checks that the new data is the same size as the old. If the size
+ has changed, this triggers a re-run of the packing algorithm.
Args:
- data: Data to set to the contents (string)
+ data: Data to set to the contents (bytes)
Raises:
ValueError if the new data size is not the same as the old
"""
- if len(data) != self.contents_size:
- self.Raise('Cannot update entry size from %d to %d' %
- (len(data), self.contents_size))
+ size_ok = True
+ new_size = len(data)
+ if state.AllowEntryExpansion() and new_size > self.contents_size:
+ # self.data will indicate the new size needed
+ size_ok = False
+ elif state.AllowEntryContraction() and new_size < self.contents_size:
+ size_ok = False
+
+ # If not allowed to change, try to deal with it or give up
+ if size_ok:
+ if new_size > self.contents_size:
+ self.Raise('Cannot update entry size from %d to %d' %
+ (self.contents_size, new_size))
+
+ # Don't let the data shrink. Pad it if necessary
+ if size_ok and new_size < self.contents_size:
+ data += tools.GetBytes(0, self.contents_size - new_size)
+
+ if not size_ok:
+ tout.Debug("Entry '%s' size change from %s to %s" % (
+ self._node.path, ToHex(self.contents_size),
+ ToHex(new_size)))
self.SetContents(data)
+ return size_ok
def ObtainContents(self):
"""Figure out the contents of an entry.
@@ -261,6 +318,14 @@
# No contents by default: subclasses can implement this
return True
+ def ResetForPack(self):
+ """Reset offset/size fields so that packing can be done again"""
+ self.Detail('ResetForPack: offset %s->%s, size %s->%s' %
+ (ToHex(self.offset), ToHex(self.orig_offset),
+ ToHex(self.size), ToHex(self.orig_size)))
+ self.offset = self.orig_offset
+ self.size = self.orig_size
+
def Pack(self, offset):
"""Figure out how to pack the entry into the section
@@ -279,6 +344,9 @@
Returns:
New section offset pointer (after this entry)
"""
+ self.Detail('Packing: offset=%s, size=%s, content_size=%x' %
+ (ToHex(self.offset), ToHex(self.size),
+ self.contents_size))
if self.offset is None:
if self.offset_unset:
self.Raise('No offset set with offset-unset: should another '
@@ -310,6 +378,8 @@
if self.offset != tools.Align(self.offset, self.align):
self.Raise("Offset %#x (%d) does not match align %#x (%d)" %
(self.offset, self.offset, self.align, self.align))
+ self.Detail(' - packed: offset=%#x, size=%#x, content_size=%#x, next_offset=%x' %
+ (self.offset, self.size, self.contents_size, new_offset))
return new_offset
@@ -317,6 +387,11 @@
"""Convenience function to raise an error referencing a node"""
raise ValueError("Node '%s': %s" % (self._node.path, msg))
+ def Detail(self, msg):
+ """Convenience function to log detail referencing a node"""
+ tag = "Node '%s'" % self._node.path
+ tout.Detail('%30s: %s' % (tag, msg))
+
def GetEntryArgsOrProps(self, props, required=False):
"""Return the values of a set of properties
@@ -353,14 +428,38 @@
return self._node.path
def GetData(self):
+ self.Detail('GetData: size %s' % ToHexSize(self.data))
return self.data
def GetOffsets(self):
+ """Get the offsets for siblings
+
+ Some entry types can contain information about the position or size of
+ other entries. An example of this is the Intel Flash Descriptor, which
+ knows where the Intel Management Engine section should go.
+
+ If this entry knows about the position of other entries, it can specify
+ this by returning values here
+
+ Returns:
+ Dict:
+ key: Entry type
+ value: List containing position and size of the given entry
+ type. Either can be None if not known
+ """
return {}
- def SetOffsetSize(self, pos, size):
- self.offset = pos
- self.size = size
+ def SetOffsetSize(self, offset, size):
+ """Set the offset and/or size of an entry
+
+ Args:
+ offset: New offset, or None to leave alone
+ size: New size, or None to leave alone
+ """
+ if offset is not None:
+ self.offset = offset
+ if size is not None:
+ self.size = size
def SetImagePos(self, image_pos):
"""Set the position in the image
@@ -371,7 +470,22 @@
self.image_pos = image_pos + self.offset
def ProcessContents(self):
- pass
+ """Do any post-packing updates of entry contents
+
+ This function should call ProcessContentsUpdate() to update the entry
+ contents, if necessary, returning its return value here.
+
+ Args:
+ data: Data to set to the contents (bytes)
+
+ Returns:
+ True if the new data size is OK, False if expansion is needed
+
+ Raises:
+ ValueError if the new data size is not the same as the old and
+ state.AllowEntryExpansion() is False
+ """
+ return True
def WriteSymbols(self, section):
"""Write symbol values into binary files for access at run time
@@ -483,7 +597,9 @@
modules.remove('_testing')
missing = []
for name in modules:
- module = Entry.Lookup(name, name, name)
+ if name.startswith('__'):
+ continue
+ module = Entry.Lookup(name, name)
docs = getattr(module, '__doc__')
if test_missing == name:
docs = None
@@ -530,3 +646,143 @@
# the data grows. This should not fail, but check it to be sure.
if not self.ObtainContents():
self.Raise('Cannot obtain contents when expanding entry')
+
+ def HasSibling(self, name):
+ """Check if there is a sibling of a given name
+
+ Returns:
+ True if there is an entry with this name in the the same section,
+ else False
+ """
+ return name in self.section.GetEntries()
+
+ def GetSiblingImagePos(self, name):
+ """Return the image position of the given sibling
+
+ Returns:
+ Image position of sibling, or None if the sibling has no position,
+ or False if there is no such sibling
+ """
+ if not self.HasSibling(name):
+ return False
+ return self.section.GetEntries()[name].image_pos
+
+ @staticmethod
+ def AddEntryInfo(entries, indent, name, etype, size, image_pos,
+ uncomp_size, offset, entry):
+ """Add a new entry to the entries list
+
+ Args:
+ entries: List (of EntryInfo objects) to add to
+ indent: Current indent level to add to list
+ name: Entry name (string)
+ etype: Entry type (string)
+ size: Entry size in bytes (int)
+ image_pos: Position within image in bytes (int)
+ uncomp_size: Uncompressed size if the entry uses compression, else
+ None
+ offset: Entry offset within parent in bytes (int)
+ entry: Entry object
+ """
+ entries.append(EntryInfo(indent, name, etype, size, image_pos,
+ uncomp_size, offset, entry))
+
+ def ListEntries(self, entries, indent):
+ """Add files in this entry to the list of entries
+
+ This can be overridden by subclasses which need different behaviour.
+
+ Args:
+ entries: List (of EntryInfo objects) to add to
+ indent: Current indent level to add to list
+ """
+ self.AddEntryInfo(entries, indent, self.name, self.etype, self.size,
+ self.image_pos, self.uncomp_size, self.offset, self)
+
+ def ReadData(self, decomp=True):
+ """Read the data for an entry from the image
+
+ This is used when the image has been read in and we want to extract the
+ data for a particular entry from that image.
+
+ Args:
+ decomp: True to decompress any compressed data before returning it;
+ False to return the raw, uncompressed data
+
+ Returns:
+ Entry data (bytes)
+ """
+ # Use True here so that we get an uncompressed section to work from,
+ # although compressed sections are currently not supported
+ data = self.section.ReadChildData(self, decomp)
+ return data
+
+ def LoadData(self, decomp=True):
+ data = self.ReadData(decomp)
+ self.contents_size = len(data)
+ self.ProcessContentsUpdate(data)
+ self.Detail('Loaded data size %x' % len(data))
+
+ def GetImage(self):
+ """Get the image containing this entry
+
+ Returns:
+ Image object containing this entry
+ """
+ return self.section.GetImage()
+
+ def WriteData(self, data, decomp=True):
+ """Write the data to an entry in the image
+
+ This is used when the image has been read in and we want to replace the
+ data for a particular entry in that image.
+
+ The image must be re-packed and written out afterwards.
+
+ Args:
+ data: Data to replace it with
+ decomp: True to compress the data if needed, False if data is
+ already compressed so should be used as is
+
+ Returns:
+ True if the data did not result in a resize of this entry, False if
+ the entry must be resized
+ """
+ self.contents_size = self.size
+ ok = self.ProcessContentsUpdate(data)
+ self.Detail('WriteData: size=%x, ok=%s' % (len(data), ok))
+ section_ok = self.section.WriteChildData(self)
+ return ok and section_ok
+
+ def WriteChildData(self, child):
+ """Handle writing the data in a child entry
+
+ This should be called on the child's parent section after the child's
+ data has been updated. It
+
+ This base-class implementation does nothing, since the base Entry object
+ does not have any children.
+
+ Args:
+ child: Child Entry that was written
+
+ Returns:
+ True if the section could be updated successfully, False if the
+ data is such that the section could not updat
+ """
+ return True
+
+ def GetSiblingOrder(self):
+ """Get the relative order of an entry amoung its siblings
+
+ Returns:
+ 'start' if this entry is first among siblings, 'end' if last,
+ otherwise None
+ """
+ entries = list(self.section.GetEntries().values())
+ if entries:
+ if self == entries[0]:
+ return 'start'
+ elif self == entries[-1]:
+ return 'end'
+ return 'middle'
diff --git a/tools/binman/entry_test.py b/tools/binman/entry_test.py
index 1f7ff5b..cc1fb79 100644
--- a/tools/binman/entry_test.py
+++ b/tools/binman/entry_test.py
@@ -9,12 +9,11 @@
import sys
import unittest
+import entry
import fdt
import fdt_util
import tools
-entry = None
-
class TestEntry(unittest.TestCase):
def setUp(self):
tools.PrepareOutputDir(None)
@@ -29,33 +28,40 @@
dtb = fdt.FdtScan(fname)
return dtb.GetNode('/binman/u-boot')
+ def _ReloadEntry(self):
+ global entry
+ if entry:
+ if sys.version_info[0] >= 3:
+ import importlib
+ importlib.reload(entry)
+ else:
+ reload(entry)
+ else:
+ import entry
+
def test1EntryNoImportLib(self):
"""Test that we can import Entry subclassess successfully"""
-
sys.modules['importlib'] = None
global entry
- import entry
+ self._ReloadEntry()
entry.Entry.Create(None, self.GetNode(), 'u-boot')
+ self.assertFalse(entry.have_importlib)
def test2EntryImportLib(self):
del sys.modules['importlib']
global entry
- if entry:
- reload(entry)
- else:
- import entry
+ self._ReloadEntry()
entry.Entry.Create(None, self.GetNode(), 'u-boot-spl')
- del entry
+ self.assertTrue(entry.have_importlib)
def testEntryContents(self):
"""Test the Entry bass class"""
import entry
- base_entry = entry.Entry(None, None, None, read_node=False)
+ base_entry = entry.Entry(None, None, None)
self.assertEqual(True, base_entry.ObtainContents())
def testUnknownEntry(self):
"""Test that unknown entry types are detected"""
- import entry
Node = collections.namedtuple('Node', ['name', 'path'])
node = Node('invalid-name', 'invalid-path')
with self.assertRaises(ValueError) as e:
@@ -65,20 +71,32 @@
def testUniqueName(self):
"""Test Entry.GetUniqueName"""
- import entry
Node = collections.namedtuple('Node', ['name', 'parent'])
base_node = Node('root', None)
- base_entry = entry.Entry(None, None, base_node, read_node=False)
+ base_entry = entry.Entry(None, None, base_node)
self.assertEqual('root', base_entry.GetUniqueName())
sub_node = Node('subnode', base_node)
- sub_entry = entry.Entry(None, None, sub_node, read_node=False)
+ sub_entry = entry.Entry(None, None, sub_node)
self.assertEqual('root.subnode', sub_entry.GetUniqueName())
def testGetDefaultFilename(self):
"""Trivial test for this base class function"""
- import entry
- base_entry = entry.Entry(None, None, None, read_node=False)
+ base_entry = entry.Entry(None, None, None)
self.assertIsNone(base_entry.GetDefaultFilename())
+ def testBlobFdt(self):
+ """Test the GetFdtEtype() method of the blob-dtb entries"""
+ base = entry.Entry.Create(None, self.GetNode(), 'blob-dtb')
+ self.assertIsNone(base.GetFdtEtype())
+
+ dtb = entry.Entry.Create(None, self.GetNode(), 'u-boot-dtb')
+ self.assertEqual('u-boot-dtb', dtb.GetFdtEtype())
+
+ def testWriteChildData(self):
+ """Test the WriteChildData() method of the base class"""
+ base = entry.Entry.Create(None, self.GetNode(), 'blob-dtb')
+ self.assertTrue(base.WriteChildData(base))
+
+
if __name__ == "__main__":
unittest.main()
diff --git a/drivers/pcmcia/Kconfig b/tools/binman/etype/__init__.py
similarity index 100%
rename from drivers/pcmcia/Kconfig
rename to tools/binman/etype/__init__.py
diff --git a/tools/binman/etype/_testing.py b/tools/binman/etype/_testing.py
index 3e345bd..25a6206 100644
--- a/tools/binman/etype/_testing.py
+++ b/tools/binman/etype/_testing.py
@@ -31,8 +31,8 @@
return-invalid-entry: Return an invalid entry from GetOffsets()
return-unknown-contents: Refuse to provide any contents (to cause a
failure)
- bad-update-contents: Implement ProcessContents() incorrectly so as to
- cause a failure
+ bad-update-contents: Return a larger size in ProcessContents
+ bad-shrink-contents: Return a larger size in ProcessContents
never-complete-process-fdt: Refund to process the FDT (to cause a
failure)
require-args: Require that all used args are present (generating an
@@ -42,14 +42,21 @@
"""
def __init__(self, section, etype, node):
Entry.__init__(self, section, etype, node)
+
+ def ReadNode(self):
+ Entry.ReadNode(self)
self.return_invalid_entry = fdt_util.GetBool(self._node,
'return-invalid-entry')
self.return_unknown_contents = fdt_util.GetBool(self._node,
'return-unknown-contents')
self.bad_update_contents = fdt_util.GetBool(self._node,
'bad-update-contents')
+ self.bad_shrink_contents = fdt_util.GetBool(self._node,
+ 'bad-shrink-contents')
self.return_contents_once = fdt_util.GetBool(self._node,
'return-contents-once')
+ self.bad_update_contents_twice = fdt_util.GetBool(self._node,
+ 'bad-update-contents-twice')
# Set to True when the entry is ready to process the FDT.
self.process_fdt_ready = False
@@ -71,11 +78,12 @@
if self.force_bad_datatype:
self.GetEntryArgsOrProps([EntryArg('test-bad-datatype-arg', bool)])
self.return_contents = True
+ self.contents = b'aa'
def ObtainContents(self):
if self.return_unknown_contents or not self.return_contents:
return False
- self.data = 'a'
+ self.data = self.contents
self.contents_size = len(self.data)
if self.return_contents_once:
self.return_contents = False
@@ -87,10 +95,26 @@
return {}
def ProcessContents(self):
+ data = self.contents
if self.bad_update_contents:
- # Request to update the conents with something larger, to cause a
+ # Request to update the contents with something larger, to cause a
# failure.
- self.ProcessContentsUpdate('aa')
+ if self.bad_update_contents_twice:
+ data = self.data + b'a'
+ else:
+ data = b'aaa'
+ return self.ProcessContentsUpdate(data)
+ if self.bad_shrink_contents:
+ # Request to update the contents with something smaller, to cause a
+ # failure.
+ data = b'a'
+ return self.ProcessContentsUpdate(data)
+ if self.bad_shrink_contents:
+ # Request to update the contents with something smaller, to cause a
+ # failure.
+ data = b'a'
+ return self.ProcessContentsUpdate(data)
+ return True
def ProcessFdt(self, fdt):
"""Force reprocessing the first time"""
diff --git a/tools/binman/etype/blob.py b/tools/binman/etype/blob.py
index ae80bbe..d15d078 100644
--- a/tools/binman/etype/blob.py
+++ b/tools/binman/etype/blob.py
@@ -9,6 +9,7 @@
import fdt_util
import state
import tools
+import tout
class Entry_blob(Entry):
"""Entry containing an arbitrary binary blob
@@ -33,8 +34,7 @@
def __init__(self, section, etype, node):
Entry.__init__(self, section, etype, node)
self._filename = fdt_util.GetString(self._node, 'filename', self.etype)
- self._compress = fdt_util.GetString(self._node, 'compress', 'none')
- self._uncompressed_size = None
+ self.compress = fdt_util.GetString(self._node, 'compress', 'none')
def ObtainContents(self):
self._filename = self.GetDefaultFilename()
@@ -42,37 +42,28 @@
self.ReadBlobContents()
return True
- def ReadBlobContents(self):
- # We assume the data is small enough to fit into memory. If this
- # is used for large filesystem image that might not be true.
- # In that case, Image.BuildImage() could be adjusted to use a
- # new Entry method which can read in chunks. Then we could copy
- # the data in chunks and avoid reading it all at once. For now
- # this seems like an unnecessary complication.
- data = tools.ReadFile(self._pathname)
- if self._compress == 'lz4':
- self._uncompressed_size = len(data)
- '''
- import lz4 # Import this only if needed (python-lz4 dependency)
+ def CompressData(self, indata):
+ if self.compress != 'none':
+ self.uncomp_size = len(indata)
+ data = tools.Compress(indata, self.compress)
+ return data
- try:
- data = lz4.frame.compress(data)
- except AttributeError:
- data = lz4.compress(data)
- '''
- data = tools.Run('lz4', '-c', self._pathname)
+ def ReadBlobContents(self):
+ """Read blob contents into memory
+
+ This function compresses the data before storing if needed.
+
+ We assume the data is small enough to fit into memory. If this
+ is used for large filesystem image that might not be true.
+ In that case, Image.BuildImage() could be adjusted to use a
+ new Entry method which can read in chunks. Then we could copy
+ the data in chunks and avoid reading it all at once. For now
+ this seems like an unnecessary complication.
+ """
+ indata = tools.ReadFile(self._pathname)
+ data = self.CompressData(indata)
self.SetContents(data)
return True
def GetDefaultFilename(self):
return self._filename
-
- def AddMissingProperties(self):
- Entry.AddMissingProperties(self)
- if self._compress != 'none':
- state.AddZeroProp(self._node, 'uncomp-size')
-
- def SetCalculatedProperties(self):
- Entry.SetCalculatedProperties(self)
- if self._uncompressed_size is not None:
- state.SetInt(self._node, 'uncomp-size', self._uncompressed_size)
diff --git a/tools/binman/etype/blob_dtb.py b/tools/binman/etype/blob_dtb.py
index cc5b4a3..5b55996 100644
--- a/tools/binman/etype/blob_dtb.py
+++ b/tools/binman/etype/blob_dtb.py
@@ -23,11 +23,42 @@
def ObtainContents(self):
"""Get the device-tree from the list held by the 'state' module"""
self._filename = self.GetDefaultFilename()
- self._pathname, data = state.GetFdtContents(self._filename)
- self.SetContents(data)
- return True
+ self._pathname, _ = state.GetFdtContents(self.GetFdtEtype())
+ return Entry_blob.ReadBlobContents(self)
def ProcessContents(self):
"""Re-read the DTB contents so that we get any calculated properties"""
- _, data = state.GetFdtContents(self._filename)
- self.SetContents(data)
+ _, indata = state.GetFdtContents(self.GetFdtEtype())
+ data = self.CompressData(indata)
+ return self.ProcessContentsUpdate(data)
+
+ def GetFdtEtype(self):
+ """Get the entry type of this device tree
+
+ This can be 'u-boot-dtb', 'u-boot-spl-dtb' or 'u-boot-tpl-dtb'
+ Returns:
+ Entry type if any, e.g. 'u-boot-dtb'
+ """
+ return None
+
+ def GetFdts(self):
+ """Get the device trees used by this entry
+
+ Returns:
+ Dict:
+ key: Filename from this entry (without the path)
+ value: Tuple:
+ Fdt object for this dtb, or None if not available
+ Filename of file containing this dtb
+ """
+ fname = self.GetDefaultFilename()
+ return {self.GetFdtEtype(): [self, fname]}
+
+ def WriteData(self, data, decomp=True):
+ ok = Entry_blob.WriteData(self, data, decomp)
+
+ # Update the state module, since it has the authoritative record of the
+ # device trees used. If we don't do this, then state.GetFdtContents()
+ # will still return the old contents
+ state.UpdateFdtContents(self.GetFdtEtype(), data)
+ return ok
diff --git a/tools/binman/etype/cbfs.py b/tools/binman/etype/cbfs.py
new file mode 100644
index 0000000..28a9c81
--- /dev/null
+++ b/tools/binman/etype/cbfs.py
@@ -0,0 +1,281 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright 2019 Google LLC
+# Written by Simon Glass <sjg@chromium.org>
+#
+# Entry-type module for a Coreboot Filesystem (CBFS)
+#
+
+from collections import OrderedDict
+
+import cbfs_util
+from cbfs_util import CbfsWriter
+from entry import Entry
+import fdt_util
+import state
+
+class Entry_cbfs(Entry):
+ """Entry containing a Coreboot Filesystem (CBFS)
+
+ A CBFS provides a way to group files into a group. It has a simple directory
+ structure and allows the position of individual files to be set, since it is
+ designed to support execute-in-place in an x86 SPI-flash device. Where XIP
+ is not used, it supports compression and storing ELF files.
+
+ CBFS is used by coreboot as its way of orgnanising SPI-flash contents.
+
+ The contents of the CBFS are defined by subnodes of the cbfs entry, e.g.:
+
+ cbfs {
+ size = <0x100000>;
+ u-boot {
+ cbfs-type = "raw";
+ };
+ u-boot-dtb {
+ cbfs-type = "raw";
+ };
+ };
+
+ This creates a CBFS 1MB in size two files in it: u-boot.bin and u-boot.dtb.
+ Note that the size is required since binman does not support calculating it.
+ The contents of each entry is just what binman would normally provide if it
+ were not a CBFS node. A blob type can be used to import arbitrary files as
+ with the second subnode below:
+
+ cbfs {
+ size = <0x100000>;
+ u-boot {
+ cbfs-name = "BOOT";
+ cbfs-type = "raw";
+ };
+
+ dtb {
+ type = "blob";
+ filename = "u-boot.dtb";
+ cbfs-type = "raw";
+ cbfs-compress = "lz4";
+ cbfs-offset = <0x100000>;
+ };
+ };
+
+ This creates a CBFS 1MB in size with u-boot.bin (named "BOOT") and
+ u-boot.dtb (named "dtb") and compressed with the lz4 algorithm.
+
+
+ Properties supported in the top-level CBFS node:
+
+ cbfs-arch:
+ Defaults to "x86", but you can specify the architecture if needed.
+
+
+ Properties supported in the CBFS entry subnodes:
+
+ cbfs-name:
+ This is the name of the file created in CBFS. It defaults to the entry
+ name (which is the node name), but you can override it with this
+ property.
+
+ cbfs-type:
+ This is the CBFS file type. The following are supported:
+
+ raw:
+ This is a 'raw' file, although compression is supported. It can be
+ used to store any file in CBFS.
+
+ stage:
+ This is an ELF file that has been loaded (i.e. mapped to memory), so
+ appears in the CBFS as a flat binary. The input file must be an ELF
+ image, for example this puts "u-boot" (the ELF image) into a 'stage'
+ entry:
+
+ cbfs {
+ size = <0x100000>;
+ u-boot-elf {
+ cbfs-name = "BOOT";
+ cbfs-type = "stage";
+ };
+ };
+
+ You can use your own ELF file with something like:
+
+ cbfs {
+ size = <0x100000>;
+ something {
+ type = "blob";
+ filename = "cbfs-stage.elf";
+ cbfs-type = "stage";
+ };
+ };
+
+ As mentioned, the file is converted to a flat binary, so it is
+ equivalent to adding "u-boot.bin", for example, but with the load and
+ start addresses specified by the ELF. At present there is no option
+ to add a flat binary with a load/start address, similar to the
+ 'add-flat-binary' option in cbfstool.
+
+ cbfs-offset:
+ This is the offset of the file's data within the CBFS. It is used to
+ specify where the file should be placed in cases where a fixed position
+ is needed. Typical uses are for code which is not relocatable and must
+ execute in-place from a particular address. This works because SPI flash
+ is generally mapped into memory on x86 devices. The file header is
+ placed before this offset so that the data start lines up exactly with
+ the chosen offset. If this property is not provided, then the file is
+ placed in the next available spot.
+
+ The current implementation supports only a subset of CBFS features. It does
+ not support other file types (e.g. payload), adding multiple files (like the
+ 'files' entry with a pattern supported by binman), putting files at a
+ particular offset in the CBFS and a few other things.
+
+ Of course binman can create images containing multiple CBFSs, simply by
+ defining these in the binman config:
+
+
+ binman {
+ size = <0x800000>;
+ cbfs {
+ offset = <0x100000>;
+ size = <0x100000>;
+ u-boot {
+ cbfs-type = "raw";
+ };
+ u-boot-dtb {
+ cbfs-type = "raw";
+ };
+ };
+
+ cbfs2 {
+ offset = <0x700000>;
+ size = <0x100000>;
+ u-boot {
+ cbfs-type = "raw";
+ };
+ u-boot-dtb {
+ cbfs-type = "raw";
+ };
+ image {
+ type = "blob";
+ filename = "image.jpg";
+ };
+ };
+ };
+
+ This creates an 8MB image with two CBFSs, one at offset 1MB, one at 7MB,
+ both of size 1MB.
+ """
+ def __init__(self, section, etype, node):
+ Entry.__init__(self, section, etype, node)
+ self._cbfs_arg = fdt_util.GetString(node, 'cbfs-arch', 'x86')
+ self._cbfs_entries = OrderedDict()
+ self._ReadSubnodes()
+ self.reader = None
+
+ def ObtainContents(self, skip=None):
+ arch = cbfs_util.find_arch(self._cbfs_arg)
+ if arch is None:
+ self.Raise("Invalid architecture '%s'" % self._cbfs_arg)
+ if self.size is None:
+ self.Raise("'cbfs' entry must have a size property")
+ cbfs = CbfsWriter(self.size, arch)
+ for entry in self._cbfs_entries.values():
+ # First get the input data and put it in a file. If not available,
+ # try later.
+ if entry != skip and not entry.ObtainContents():
+ return False
+ data = entry.GetData()
+ cfile = None
+ if entry._type == 'raw':
+ cfile = cbfs.add_file_raw(entry._cbfs_name, data,
+ entry._cbfs_offset,
+ entry._cbfs_compress)
+ elif entry._type == 'stage':
+ cfile = cbfs.add_file_stage(entry._cbfs_name, data,
+ entry._cbfs_offset)
+ else:
+ entry.Raise("Unknown cbfs-type '%s' (use 'raw', 'stage')" %
+ entry._type)
+ if cfile:
+ entry._cbfs_file = cfile
+ data = cbfs.get_data()
+ self.SetContents(data)
+ return True
+
+ def _ReadSubnodes(self):
+ """Read the subnodes to find out what should go in this IFWI"""
+ for node in self._node.subnodes:
+ entry = Entry.Create(self, node)
+ entry.ReadNode()
+ entry._cbfs_name = fdt_util.GetString(node, 'cbfs-name', entry.name)
+ entry._type = fdt_util.GetString(node, 'cbfs-type')
+ compress = fdt_util.GetString(node, 'cbfs-compress', 'none')
+ entry._cbfs_offset = fdt_util.GetInt(node, 'cbfs-offset')
+ entry._cbfs_compress = cbfs_util.find_compress(compress)
+ if entry._cbfs_compress is None:
+ self.Raise("Invalid compression in '%s': '%s'" %
+ (node.name, compress))
+ self._cbfs_entries[entry._cbfs_name] = entry
+
+ def SetImagePos(self, image_pos):
+ """Override this function to set all the entry properties from CBFS
+
+ We can only do this once image_pos is known
+
+ Args:
+ image_pos: Position of this entry in the image
+ """
+ Entry.SetImagePos(self, image_pos)
+
+ # Now update the entries with info from the CBFS entries
+ for entry in self._cbfs_entries.values():
+ cfile = entry._cbfs_file
+ entry.size = cfile.data_len
+ entry.offset = cfile.calced_cbfs_offset
+ entry.image_pos = self.image_pos + entry.offset
+ if entry._cbfs_compress:
+ entry.uncomp_size = cfile.memlen
+
+ def AddMissingProperties(self):
+ Entry.AddMissingProperties(self)
+ for entry in self._cbfs_entries.values():
+ entry.AddMissingProperties()
+ if entry._cbfs_compress:
+ state.AddZeroProp(entry._node, 'uncomp-size')
+ # Store the 'compress' property, since we don't look at
+ # 'cbfs-compress' in Entry.ReadData()
+ state.AddString(entry._node, 'compress',
+ cbfs_util.compress_name(entry._cbfs_compress))
+
+ def SetCalculatedProperties(self):
+ """Set the value of device-tree properties calculated by binman"""
+ Entry.SetCalculatedProperties(self)
+ for entry in self._cbfs_entries.values():
+ state.SetInt(entry._node, 'offset', entry.offset)
+ state.SetInt(entry._node, 'size', entry.size)
+ state.SetInt(entry._node, 'image-pos', entry.image_pos)
+ if entry.uncomp_size is not None:
+ state.SetInt(entry._node, 'uncomp-size', entry.uncomp_size)
+
+ def ListEntries(self, entries, indent):
+ """Override this method to list all files in the section"""
+ Entry.ListEntries(self, entries, indent)
+ for entry in self._cbfs_entries.values():
+ entry.ListEntries(entries, indent + 1)
+
+ def GetEntries(self):
+ return self._cbfs_entries
+
+ def ReadData(self, decomp=True):
+ data = Entry.ReadData(self, True)
+ return data
+
+ def ReadChildData(self, child, decomp=True):
+ if not self.reader:
+ data = Entry.ReadData(self, True)
+ self.reader = cbfs_util.CbfsReader(data)
+ reader = self.reader
+ cfile = reader.files.get(child.name)
+ return cfile.data if decomp else cfile.orig_data
+
+ def WriteChildData(self, child):
+ self.ObtainContents(skip=child)
+ return True
diff --git a/tools/binman/etype/fdtmap.py b/tools/binman/etype/fdtmap.py
new file mode 100644
index 0000000..b1810b9
--- /dev/null
+++ b/tools/binman/etype/fdtmap.py
@@ -0,0 +1,144 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2018 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+
+"""# Entry-type module for a full map of the firmware image
+
+This handles putting an FDT into the image with just the information about the
+image.
+"""
+
+import libfdt
+
+from entry import Entry
+from fdt import Fdt
+import state
+import tools
+import tout
+
+FDTMAP_MAGIC = b'_FDTMAP_'
+FDTMAP_HDR_LEN = 16
+
+def LocateFdtmap(data):
+ """Search an image for an fdt map
+
+ Args:
+ data: Data to search
+
+ Returns:
+ Position of fdt map in data, or None if not found. Note that the
+ position returned is of the FDT header, i.e. before the FDT data
+ """
+ hdr_pos = data.find(FDTMAP_MAGIC)
+ size = len(data)
+ if hdr_pos != -1:
+ hdr = data[hdr_pos:hdr_pos + FDTMAP_HDR_LEN]
+ if len(hdr) == FDTMAP_HDR_LEN:
+ return hdr_pos
+ return None
+
+class Entry_fdtmap(Entry):
+ """An entry which contains an FDT map
+
+ Properties / Entry arguments:
+ None
+
+ An FDT map is just a header followed by an FDT containing a list of all the
+ entries in the image. The root node corresponds to the image node in the
+ original FDT, and an image-name property indicates the image name in that
+ original tree.
+
+ The header is the string _FDTMAP_ followed by 8 unused bytes.
+
+ When used, this entry will be populated with an FDT map which reflects the
+ entries in the current image. Hierarchy is preserved, and all offsets and
+ sizes are included.
+
+ Note that the -u option must be provided to ensure that binman updates the
+ FDT with the position of each entry.
+
+ Example output for a simple image with U-Boot and an FDT map:
+
+ / {
+ image-name = "binman";
+ size = <0x00000112>;
+ image-pos = <0x00000000>;
+ offset = <0x00000000>;
+ u-boot {
+ size = <0x00000004>;
+ image-pos = <0x00000000>;
+ offset = <0x00000000>;
+ };
+ fdtmap {
+ size = <0x0000010e>;
+ image-pos = <0x00000004>;
+ offset = <0x00000004>;
+ };
+ };
+
+ If allow-repack is used then 'orig-offset' and 'orig-size' properties are
+ added as necessary. See the binman README.
+ """
+ def __init__(self, section, etype, node):
+ Entry.__init__(self, section, etype, node)
+
+ def _GetFdtmap(self):
+ """Build an FDT map from the entries in the current image
+
+ Returns:
+ FDT map binary data
+ """
+ def _AddNode(node):
+ """Add a node to the FDT map"""
+ for pname, prop in node.props.items():
+ fsw.property(pname, prop.bytes)
+ for subnode in node.subnodes:
+ with fsw.add_node(subnode.name):
+ _AddNode(subnode)
+
+ data = state.GetFdtContents('fdtmap')[1]
+ # If we have an fdtmap it means that we are using this as the
+ # fdtmap for this image.
+ if data is None:
+ # Get the FDT data into an Fdt object
+ data = state.GetFdtContents()[1]
+ infdt = Fdt.FromData(data)
+ infdt.Scan()
+
+ # Find the node for the image containing the Fdt-map entry
+ path = self.section.GetPath()
+ self.Detail("Fdtmap: Using section '%s' (path '%s')" %
+ (self.section.name, path))
+ node = infdt.GetNode(path)
+ if not node:
+ self.Raise("Internal error: Cannot locate node for path '%s'" %
+ path)
+
+ # Build a new tree with all nodes and properties starting from that
+ # node
+ fsw = libfdt.FdtSw()
+ fsw.finish_reservemap()
+ with fsw.add_node(''):
+ fsw.property_string('image-node', node.name)
+ _AddNode(node)
+ fdt = fsw.as_fdt()
+
+ # Pack this new FDT and return its contents
+ fdt.pack()
+ outfdt = Fdt.FromData(fdt.as_bytearray())
+ data = outfdt.GetContents()
+ data = FDTMAP_MAGIC + tools.GetBytes(0, 8) + data
+ return data
+
+ def ObtainContents(self):
+ """Obtain a placeholder for the fdt-map contents"""
+ self.SetContents(self._GetFdtmap())
+ return True
+
+ def ProcessContents(self):
+ """Write an updated version of the FDT map to this entry
+
+ This is necessary since new data may have been written back to it during
+ processing, e.g. the image-pos properties.
+ """
+ return self.ProcessContentsUpdate(self._GetFdtmap())
diff --git a/tools/binman/etype/files.py b/tools/binman/etype/files.py
index 99f2f2f..0068b30 100644
--- a/tools/binman/etype/files.py
+++ b/tools/binman/etype/files.py
@@ -14,7 +14,6 @@
import state
import tools
-import bsection
class Entry_files(Entry_section):
"""Entry containing a set of files
@@ -54,4 +53,4 @@
state.AddString(subnode, 'compress', self._compress)
# Read entries again, now that we have some
- self._section._ReadEntries()
+ self._ReadEntries()
diff --git a/tools/binman/etype/fill.py b/tools/binman/etype/fill.py
index dcfe978..623b7f4 100644
--- a/tools/binman/etype/fill.py
+++ b/tools/binman/etype/fill.py
@@ -5,7 +5,7 @@
from entry import Entry
import fdt_util
-
+import tools
class Entry_fill(Entry):
"""An entry which is filled to a particular byte value
@@ -23,10 +23,13 @@
"""
def __init__(self, section, etype, node):
Entry.__init__(self, section, etype, node)
+
+ def ReadNode(self):
+ Entry.ReadNode(self)
if self.size is None:
self.Raise("'fill' entry must have a size property")
self.fill_value = fdt_util.GetByte(self._node, 'fill-byte', 0)
def ObtainContents(self):
- self.SetContents(chr(self.fill_value) * self.size)
+ self.SetContents(tools.GetBytes(self.fill_value, self.size))
return True
diff --git a/tools/binman/etype/fmap.py b/tools/binman/etype/fmap.py
index bf35a5b..835ba50 100644
--- a/tools/binman/etype/fmap.py
+++ b/tools/binman/etype/fmap.py
@@ -7,6 +7,9 @@
from entry import Entry
import fmap_util
+import tools
+from tools import ToHexSize
+import tout
class Entry_fmap(Entry):
@@ -25,7 +28,8 @@
When used, this entry will be populated with an FMAP which reflects the
entries in the current image. Note that any hierarchy is squashed, since
- FMAP does not support this.
+ FMAP does not support this. Also, CBFS entries appear as a single entry -
+ the sub-entries are ignored.
"""
def __init__(self, section, etype, node):
Entry.__init__(self, section, etype, node)
@@ -38,7 +42,9 @@
"""
def _AddEntries(areas, entry):
entries = entry.GetEntries()
- if entries:
+ tout.Debug("fmap: Add entry '%s' type '%s' (%s subentries)" %
+ (entry.GetPath(), entry.etype, ToHexSize(entries)))
+ if entries and entry.etype != 'cbfs':
for subentry in entries.values():
_AddEntries(areas, subentry)
else:
@@ -46,9 +52,9 @@
if pos is not None:
pos -= entry.section.GetRootSkipAtStart()
areas.append(fmap_util.FmapArea(pos or 0, entry.size or 0,
- entry.name, 0))
+ tools.FromUnicode(entry.name), 0))
- entries = self.section._image.GetEntries()
+ entries = self.GetImage().GetEntries()
areas = []
for entry in entries.values():
_AddEntries(areas, entry)
@@ -61,4 +67,4 @@
return True
def ProcessContents(self):
- self.SetContents(self._GetFmap())
+ return self.ProcessContentsUpdate(self._GetFmap())
diff --git a/tools/binman/etype/gbb.py b/tools/binman/etype/gbb.py
index 8fe10f4..a94c0fc 100644
--- a/tools/binman/etype/gbb.py
+++ b/tools/binman/etype/gbb.py
@@ -64,7 +64,7 @@
self.gbb_flags = 0
flags_node = node.FindNode('flags')
if flags_node:
- for flag, value in gbb_flag_properties.iteritems():
+ for flag, value in gbb_flag_properties.items():
if fdt_util.GetBool(flags_node, flag):
self.gbb_flags |= value
diff --git a/tools/binman/etype/image_header.py b/tools/binman/etype/image_header.py
new file mode 100644
index 0000000..4b69eda
--- /dev/null
+++ b/tools/binman/etype/image_header.py
@@ -0,0 +1,111 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2018 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+
+"""Entry-type module for an image header which points to the FDT map
+
+This creates an 8-byte entry with a magic number and the offset of the FDT map
+(which is another entry in the image), relative to the start or end of the
+image.
+"""
+
+import struct
+
+from entry import Entry
+import fdt_util
+
+IMAGE_HEADER_MAGIC = b'BinM'
+IMAGE_HEADER_LEN = 8
+
+def LocateHeaderOffset(data):
+ """Search an image for an image header
+
+ Args:
+ data: Data to search
+
+ Returns:
+ Offset of image header in the image, or None if not found
+ """
+ hdr_pos = data.find(IMAGE_HEADER_MAGIC)
+ if hdr_pos != -1:
+ size = len(data)
+ hdr = data[hdr_pos:hdr_pos + IMAGE_HEADER_LEN]
+ if len(hdr) == IMAGE_HEADER_LEN:
+ offset = struct.unpack('<I', hdr[4:])[0]
+ if hdr_pos == len(data) - IMAGE_HEADER_LEN:
+ pos = size + offset - (1 << 32)
+ else:
+ pos = offset
+ return pos
+ return None
+
+class Entry_image_header(Entry):
+ """An entry which contains a pointer to the FDT map
+
+ Properties / Entry arguments:
+ location: Location of header ("start" or "end" of image). This is
+ optional. If omitted then the entry must have an offset property.
+
+ This adds an 8-byte entry to the start or end of the image, pointing to the
+ location of the FDT map. The format is a magic number followed by an offset
+ from the start or end of the image, in twos-compliment format.
+
+ This entry must be in the top-level part of the image.
+
+ NOTE: If the location is at the start/end, you will probably need to specify
+ sort-by-offset for the image, unless you actually put the image header
+ first/last in the entry list.
+ """
+ def __init__(self, section, etype, node):
+ Entry.__init__(self, section, etype, node)
+ self.location = fdt_util.GetString(self._node, 'location')
+
+ def _GetHeader(self):
+ image_pos = self.GetSiblingImagePos('fdtmap')
+ if image_pos == False:
+ self.Raise("'image_header' section must have an 'fdtmap' sibling")
+ elif image_pos is None:
+ # This will be available when called from ProcessContents(), but not
+ # when called from ObtainContents()
+ offset = 0xffffffff
+ else:
+ image_size = self.section.GetImageSize() or 0
+ base = (0 if self.location != 'end' else image_size)
+ offset = (image_pos - base) & 0xffffffff
+ data = IMAGE_HEADER_MAGIC + struct.pack('<I', offset)
+ return data
+
+ def ObtainContents(self):
+ """Obtain a placeholder for the header contents"""
+ self.SetContents(self._GetHeader())
+ return True
+
+ def Pack(self, offset):
+ """Special pack method to set the offset to start/end of image"""
+ if not self.offset:
+ if self.location not in ['start', 'end']:
+ self.Raise("Invalid location '%s', expected 'start' or 'end'" %
+ self.location)
+ order = self.GetSiblingOrder()
+ if self.location != order and not self.section.GetSort():
+ self.Raise("Invalid sibling order '%s' for image-header: Must be at '%s' to match location" %
+ (order, self.location))
+ if self.location != 'end':
+ offset = 0
+ else:
+ image_size = self.section.GetImageSize()
+ if image_size is None:
+ # We don't know the image, but this must be the last entry,
+ # so we can assume it goes
+ offset = offset
+ else:
+ offset = image_size - IMAGE_HEADER_LEN
+ return Entry.Pack(self, offset)
+
+ def ProcessContents(self):
+ """Write an updated version of the FDT map to this entry
+
+ This is necessary since image_pos is not available when ObtainContents()
+ is called, since by then the entries have not been packed in the image.
+ """
+ return self.ProcessContentsUpdate(self._GetHeader())
diff --git a/tools/binman/etype/intel_descriptor.py b/tools/binman/etype/intel_descriptor.py
index 6acbbd8..fb5e889 100644
--- a/tools/binman/etype/intel_descriptor.py
+++ b/tools/binman/etype/intel_descriptor.py
@@ -48,16 +48,28 @@
Entry_blob.__init__(self, section, etype, node)
self._regions = []
+ def Pack(self, offset):
+ """Put this entry at the start of the image"""
+ if self.offset is None:
+ offset = self.section.GetStartOffset()
+ return Entry_blob.Pack(self, offset)
+
def GetOffsets(self):
offset = self.data.find(FD_SIGNATURE)
if offset == -1:
- self.Raise('Cannot find FD signature')
+ self.Raise('Cannot find Intel Flash Descriptor (FD) signature')
flvalsig, flmap0, flmap1, flmap2 = struct.unpack('<LLLL',
self.data[offset:offset + 16])
frba = ((flmap0 >> 16) & 0xff) << 4
for i in range(MAX_REGIONS):
self._regions.append(Region(self.data, frba, i))
- # Set the offset for ME only, for now, since the others are not used
- return {'intel-me': [self._regions[REGION_ME].base,
- self._regions[REGION_ME].size]}
+ # Set the offset for ME (Management Engine) and IFWI (Integrated
+ # Firmware Image), for now, since the others are not used.
+ info = {}
+ if self.HasSibling('intel-me'):
+ info['intel-me'] = [self._regions[REGION_ME].base,
+ self._regions[REGION_ME].size]
+ if self.HasSibling('intel-ifwi'):
+ info['intel-ifwi'] = [self._regions[REGION_BIOS].base, None]
+ return info
diff --git a/tools/binman/etype/intel_ifwi.py b/tools/binman/etype/intel_ifwi.py
new file mode 100644
index 0000000..9cbdf36
--- /dev/null
+++ b/tools/binman/etype/intel_ifwi.py
@@ -0,0 +1,101 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# Entry-type module for Intel Management Engine binary blob
+#
+
+from collections import OrderedDict
+
+from entry import Entry
+from blob import Entry_blob
+import fdt_util
+import tools
+
+class Entry_intel_ifwi(Entry_blob):
+ """Entry containing an Intel Integrated Firmware Image (IFWI) file
+
+ Properties / Entry arguments:
+ - filename: Filename of file to read into entry. This is either the
+ IFWI file itself, or a file that can be converted into one using a
+ tool
+ - convert-fit: If present this indicates that the ifwitool should be
+ used to convert the provided file into a IFWI.
+
+ This file contains code and data used by the SoC that is required to make
+ it work. It includes U-Boot TPL, microcode, things related to the CSE
+ (Converged Security Engine, the microcontroller that loads all the firmware)
+ and other items beyond the wit of man.
+
+ A typical filename is 'ifwi.bin' for an IFWI file, or 'fitimage.bin' for a
+ file that will be converted to an IFWI.
+
+ The position of this entry is generally set by the intel-descriptor entry.
+
+ The contents of the IFWI are specified by the subnodes of the IFWI node.
+ Each subnode describes an entry which is placed into the IFWFI with a given
+ sub-partition (and optional entry name).
+
+ See README.x86 for information about x86 binary blobs.
+ """
+ def __init__(self, section, etype, node):
+ Entry_blob.__init__(self, section, etype, node)
+ self._convert_fit = fdt_util.GetBool(self._node, 'convert-fit')
+ self._ifwi_entries = OrderedDict()
+ self._ReadSubnodes()
+
+ def ObtainContents(self):
+ """Get the contects for the IFWI
+
+ Unfortunately we cannot create anything from scratch here, as Intel has
+ tools which create precursor binaries with lots of data and settings,
+ and these are not incorporated into binman.
+
+ The first step is to get a file in the IFWI format. This is either
+ supplied directly or is extracted from a fitimage using the 'create'
+ subcommand.
+
+ After that we delete the OBBP sub-partition and add each of the files
+ that we want in the IFWI file, one for each sub-entry of the IWFI node.
+ """
+ self._pathname = tools.GetInputFilename(self._filename)
+
+ # Create the IFWI file if needed
+ if self._convert_fit:
+ inname = self._pathname
+ outname = tools.GetOutputFilename('ifwi.bin')
+ tools.RunIfwiTool(inname, tools.CMD_CREATE, outname)
+ self._filename = 'ifwi.bin'
+ self._pathname = outname
+ else:
+ # Provide a different code path here to ensure we have test coverage
+ inname = self._pathname
+
+ # Delete OBBP if it is there, then add the required new items.
+ tools.RunIfwiTool(inname, tools.CMD_DELETE, subpart='OBBP')
+
+ for entry in self._ifwi_entries.values():
+ # First get the input data and put it in a file
+ if not entry.ObtainContents():
+ return False
+ data = entry.GetData()
+ uniq = self.GetUniqueName()
+ input_fname = tools.GetOutputFilename('input.%s' % uniq)
+ tools.WriteFile(input_fname, data)
+
+ tools.RunIfwiTool(inname,
+ tools.CMD_REPLACE if entry._ifwi_replace else tools.CMD_ADD,
+ input_fname, entry._ifwi_subpart, entry._ifwi_entry_name)
+
+ self.ReadBlobContents()
+ return True
+
+ def _ReadSubnodes(self):
+ """Read the subnodes to find out what should go in this IFWI"""
+ for node in self._node.subnodes:
+ entry = Entry.Create(self.section, node)
+ entry.ReadNode()
+ entry._ifwi_replace = fdt_util.GetBool(node, 'replace')
+ entry._ifwi_subpart = fdt_util.GetString(node, 'ifwi-subpart')
+ entry._ifwi_entry_name = fdt_util.GetString(node, 'ifwi-entry')
+ self._ifwi_entries[entry._ifwi_subpart] = entry
diff --git a/tools/binman/etype/intel_me.py b/tools/binman/etype/intel_me.py
index 247c5b3..c932ec5 100644
--- a/tools/binman/etype/intel_me.py
+++ b/tools/binman/etype/intel_me.py
@@ -22,6 +22,8 @@
A typical filename is 'me.bin'.
+ The position of this entry is generally set by the intel-descriptor entry.
+
See README.x86 for information about x86 binary blobs.
"""
def __init__(self, section, etype, node):
diff --git a/tools/binman/etype/section.py b/tools/binman/etype/section.py
index 3681a48..5d34fc5 100644
--- a/tools/binman/etype/section.py
+++ b/tools/binman/etype/section.py
@@ -1,59 +1,157 @@
# SPDX-License-Identifier: GPL-2.0+
# Copyright (c) 2018 Google, Inc
# Written by Simon Glass <sjg@chromium.org>
-#
-# Entry-type module for sections, which are entries which can contain other
-# entries.
-#
+
+"""Entry-type module for sections (groups of entries)
+
+Sections are entries which can contain other entries. This allows hierarchical
+images to be created.
+"""
+
+from __future__ import print_function
+
+from collections import OrderedDict
+import re
+import sys
from entry import Entry
import fdt_util
import tools
+import tout
-import bsection
class Entry_section(Entry):
"""Entry that contains other entries
Properties / Entry arguments: (see binman README for more information)
- - size: Size of section in bytes
- - align-size: Align size to a particular power of two
- - pad-before: Add padding before the entry
- - pad-after: Add padding after the entry
- - pad-byte: Pad byte to use when padding
- - sort-by-offset: Reorder the entries by offset
- - end-at-4gb: Used to build an x86 ROM which ends at 4GB (2^32)
- - name-prefix: Adds a prefix to the name of every entry in the section
+ pad-byte: Pad byte to use when padding
+ sort-by-offset: True if entries should be sorted by offset, False if
+ they must be in-order in the device tree description
+ end-at-4gb: Used to build an x86 ROM which ends at 4GB (2^32)
+ skip-at-start: Number of bytes before the first entry starts. These
+ effectively adjust the starting offset of entries. For example,
+ if this is 16, then the first entry would start at 16. An entry
+ with offset = 20 would in fact be written at offset 4 in the image
+ file, since the first 16 bytes are skipped when writing.
+ name-prefix: Adds a prefix to the name of every entry in the section
when writing out the map
+ Since a section is also an entry, it inherits all the properies of entries
+ too.
+
A section is an entry which can contain other entries, thus allowing
hierarchical images to be created. See 'Sections and hierarchical images'
in the binman README for more information.
"""
- def __init__(self, section, etype, node):
- Entry.__init__(self, section, etype, node)
- self._section = bsection.Section(node.name, section, node,
- section._image)
+ def __init__(self, section, etype, node, test=False):
+ if not test:
+ Entry.__init__(self, section, etype, node)
+ self._entries = OrderedDict()
+ self._pad_byte = 0
+ self._sort = False
+ self._skip_at_start = None
+ self._end_4gb = False
- def GetFdtSet(self):
- return self._section.GetFdtSet()
+ def ReadNode(self):
+ """Read properties from the image node"""
+ Entry.ReadNode(self)
+ self._pad_byte = fdt_util.GetInt(self._node, 'pad-byte', 0)
+ self._sort = fdt_util.GetBool(self._node, 'sort-by-offset')
+ self._end_4gb = fdt_util.GetBool(self._node, 'end-at-4gb')
+ self._skip_at_start = fdt_util.GetInt(self._node, 'skip-at-start')
+ if self._end_4gb:
+ if not self.size:
+ self.Raise("Section size must be provided when using end-at-4gb")
+ if self._skip_at_start is not None:
+ self.Raise("Provide either 'end-at-4gb' or 'skip-at-start'")
+ else:
+ self._skip_at_start = 0x100000000 - self.size
+ else:
+ if self._skip_at_start is None:
+ self._skip_at_start = 0
+ self._name_prefix = fdt_util.GetString(self._node, 'name-prefix')
+ filename = fdt_util.GetString(self._node, 'filename')
+ if filename:
+ self._filename = filename
+
+ self._ReadEntries()
+
+ def _ReadEntries(self):
+ for node in self._node.subnodes:
+ if node.name == 'hash':
+ continue
+ entry = Entry.Create(self, node)
+ entry.ReadNode()
+ entry.SetPrefix(self._name_prefix)
+ self._entries[node.name] = entry
+
+ def _Raise(self, msg):
+ """Raises an error for this section
+
+ Args:
+ msg: Error message to use in the raise string
+ Raises:
+ ValueError()
+ """
+ raise ValueError("Section '%s': %s" % (self._node.path, msg))
+
+ def GetFdts(self):
+ fdts = {}
+ for entry in self._entries.values():
+ fdts.update(entry.GetFdts())
+ return fdts
def ProcessFdt(self, fdt):
- return self._section.ProcessFdt(fdt)
+ """Allow entries to adjust the device tree
+
+ Some entries need to adjust the device tree for their purposes. This
+ may involve adding or deleting properties.
+ """
+ todo = self._entries.values()
+ for passnum in range(3):
+ next_todo = []
+ for entry in todo:
+ if not entry.ProcessFdt(fdt):
+ next_todo.append(entry)
+ todo = next_todo
+ if not todo:
+ break
+ if todo:
+ self.Raise('Internal error: Could not complete processing of Fdt: remaining %s' %
+ todo)
+ return True
def ExpandEntries(self):
+ """Expand out any entries which have calculated sub-entries
+
+ Some entries are expanded out at runtime, e.g. 'files', which produces
+ a section containing a list of files. Process these entries so that
+ this information is added to the device tree.
+ """
Entry.ExpandEntries(self)
- self._section.ExpandEntries()
+ for entry in self._entries.values():
+ entry.ExpandEntries()
def AddMissingProperties(self):
+ """Add new properties to the device tree as needed for this entry"""
Entry.AddMissingProperties(self)
- self._section.AddMissingProperties()
+ for entry in self._entries.values():
+ entry.AddMissingProperties()
def ObtainContents(self):
- return self._section.GetEntryContents()
+ return self.GetEntryContents()
def GetData(self):
- return self._section.GetData()
+ section_data = tools.GetBytes(self._pad_byte, self.size)
+
+ for entry in self._entries.values():
+ data = entry.GetData()
+ base = self.pad_before + entry.offset - self._skip_at_start
+ section_data = (section_data[:base] + data +
+ section_data[base + len(data):])
+ self.Detail('GetData: %d entries, total size %#x' %
+ (len(self._entries), len(section_data)))
+ return section_data
def GetOffsets(self):
"""Handle entries that want to set the offset/size of other entries
@@ -61,35 +159,94 @@
This calls each entry's GetOffsets() method. If it returns a list
of entries to update, it updates them.
"""
- self._section.GetEntryOffsets()
+ self.GetEntryOffsets()
return {}
+ def ResetForPack(self):
+ """Reset offset/size fields so that packing can be done again"""
+ Entry.ResetForPack(self)
+ for entry in self._entries.values():
+ entry.ResetForPack()
+
def Pack(self, offset):
"""Pack all entries into the section"""
- self._section.PackEntries()
- if self._section._offset is None:
- self._section.SetOffset(offset)
- self.size = self._section.GetSize()
- return super(Entry_section, self).Pack(offset)
+ self._PackEntries()
+ return Entry.Pack(self, offset)
- def SetImagePos(self, image_pos):
- Entry.SetImagePos(self, image_pos)
- self._section.SetImagePos(image_pos + self.offset)
+ def _PackEntries(self):
+ """Pack all entries into the image"""
+ offset = self._skip_at_start
+ for entry in self._entries.values():
+ offset = entry.Pack(offset)
+ self.size = self.CheckSize()
+
+ def _ExpandEntries(self):
+ """Expand any entries that are permitted to"""
+ exp_entry = None
+ for entry in self._entries.values():
+ if exp_entry:
+ exp_entry.ExpandToLimit(entry.offset)
+ exp_entry = None
+ if entry.expand_size:
+ exp_entry = entry
+ if exp_entry:
+ exp_entry.ExpandToLimit(self.size)
+
+ def _SortEntries(self):
+ """Sort entries by offset"""
+ entries = sorted(self._entries.values(), key=lambda entry: entry.offset)
+ self._entries.clear()
+ for entry in entries:
+ self._entries[entry._node.name] = entry
+
+ def CheckEntries(self):
+ """Check that entries do not overlap or extend outside the image"""
+ if self._sort:
+ self._SortEntries()
+ self._ExpandEntries()
+ offset = 0
+ prev_name = 'None'
+ for entry in self._entries.values():
+ entry.CheckOffset()
+ if (entry.offset < self._skip_at_start or
+ entry.offset + entry.size > self._skip_at_start +
+ self.size):
+ entry.Raise("Offset %#x (%d) is outside the section starting "
+ "at %#x (%d)" %
+ (entry.offset, entry.offset, self._skip_at_start,
+ self._skip_at_start))
+ if entry.offset < offset:
+ entry.Raise("Offset %#x (%d) overlaps with previous entry '%s' "
+ "ending at %#x (%d)" %
+ (entry.offset, entry.offset, prev_name, offset, offset))
+ offset = entry.offset + entry.size
+ prev_name = entry.GetPath()
def WriteSymbols(self, section):
"""Write symbol values into binary files for access at run time"""
- self._section.WriteSymbols()
+ for entry in self._entries.values():
+ entry.WriteSymbols(self)
def SetCalculatedProperties(self):
Entry.SetCalculatedProperties(self)
- self._section.SetCalculatedProperties()
+ for entry in self._entries.values():
+ entry.SetCalculatedProperties()
+
+ def SetImagePos(self, image_pos):
+ Entry.SetImagePos(self, image_pos)
+ for entry in self._entries.values():
+ entry.SetImagePos(image_pos + self.offset)
def ProcessContents(self):
- self._section.ProcessEntryContents()
- super(Entry_section, self).ProcessContents()
+ sizes_ok_base = super(Entry_section, self).ProcessContents()
+ sizes_ok = True
+ for entry in self._entries.values():
+ if not entry.ProcessContents():
+ sizes_ok = False
+ return sizes_ok and sizes_ok_base
def CheckOffset(self):
- self._section.CheckEntries()
+ self.CheckEntries()
def WriteMap(self, fd, indent):
"""Write a map of the section to a .map file
@@ -97,11 +254,272 @@
Args:
fd: File to write the map to
"""
- self._section.WriteMap(fd, indent)
+ Entry.WriteMapLine(fd, indent, self.name, self.offset or 0,
+ self.size, self.image_pos)
+ for entry in self._entries.values():
+ entry.WriteMap(fd, indent + 1)
def GetEntries(self):
- return self._section.GetEntries()
+ return self._entries
- def ExpandToLimit(self, limit):
- super(Entry_section, self).ExpandToLimit(limit)
- self._section.ExpandSize(self.size)
+ def GetContentsByPhandle(self, phandle, source_entry):
+ """Get the data contents of an entry specified by a phandle
+
+ This uses a phandle to look up a node and and find the entry
+ associated with it. Then it returnst he contents of that entry.
+
+ Args:
+ phandle: Phandle to look up (integer)
+ source_entry: Entry containing that phandle (used for error
+ reporting)
+
+ Returns:
+ data from associated entry (as a string), or None if not found
+ """
+ node = self._node.GetFdt().LookupPhandle(phandle)
+ if not node:
+ source_entry.Raise("Cannot find node for phandle %d" % phandle)
+ for entry in self._entries.values():
+ if entry._node == node:
+ return entry.GetData()
+ source_entry.Raise("Cannot find entry for node '%s'" % node.name)
+
+ def LookupSymbol(self, sym_name, optional, msg):
+ """Look up a symbol in an ELF file
+
+ Looks up a symbol in an ELF file. Only entry types which come from an
+ ELF image can be used by this function.
+
+ At present the only entry property supported is offset.
+
+ Args:
+ sym_name: Symbol name in the ELF file to look up in the format
+ _binman_<entry>_prop_<property> where <entry> is the name of
+ the entry and <property> is the property to find (e.g.
+ _binman_u_boot_prop_offset). As a special case, you can append
+ _any to <entry> to have it search for any matching entry. E.g.
+ _binman_u_boot_any_prop_offset will match entries called u-boot,
+ u-boot-img and u-boot-nodtb)
+ optional: True if the symbol is optional. If False this function
+ will raise if the symbol is not found
+ msg: Message to display if an error occurs
+
+ Returns:
+ Value that should be assigned to that symbol, or None if it was
+ optional and not found
+
+ Raises:
+ ValueError if the symbol is invalid or not found, or references a
+ property which is not supported
+ """
+ m = re.match(r'^_binman_(\w+)_prop_(\w+)$', sym_name)
+ if not m:
+ raise ValueError("%s: Symbol '%s' has invalid format" %
+ (msg, sym_name))
+ entry_name, prop_name = m.groups()
+ entry_name = entry_name.replace('_', '-')
+ entry = self._entries.get(entry_name)
+ if not entry:
+ if entry_name.endswith('-any'):
+ root = entry_name[:-4]
+ for name in self._entries:
+ if name.startswith(root):
+ rest = name[len(root):]
+ if rest in ['', '-img', '-nodtb']:
+ entry = self._entries[name]
+ if not entry:
+ err = ("%s: Entry '%s' not found in list (%s)" %
+ (msg, entry_name, ','.join(self._entries.keys())))
+ if optional:
+ print('Warning: %s' % err, file=sys.stderr)
+ return None
+ raise ValueError(err)
+ if prop_name == 'offset':
+ return entry.offset
+ elif prop_name == 'image_pos':
+ return entry.image_pos
+ else:
+ raise ValueError("%s: No such property '%s'" % (msg, prop_name))
+
+ def GetRootSkipAtStart(self):
+ """Get the skip-at-start value for the top-level section
+
+ This is used to find out the starting offset for root section that
+ contains this section. If this is a top-level section then it returns
+ the skip-at-start offset for this section.
+
+ This is used to get the absolute position of section within the image.
+
+ Returns:
+ Integer skip-at-start value for the root section containing this
+ section
+ """
+ if self.section:
+ return self.section.GetRootSkipAtStart()
+ return self._skip_at_start
+
+ def GetStartOffset(self):
+ """Get the start offset for this section
+
+ Returns:
+ The first available offset in this section (typically 0)
+ """
+ return self._skip_at_start
+
+ def GetImageSize(self):
+ """Get the size of the image containing this section
+
+ Returns:
+ Image size as an integer number of bytes, which may be None if the
+ image size is dynamic and its sections have not yet been packed
+ """
+ return self.GetImage().size
+
+ def FindEntryType(self, etype):
+ """Find an entry type in the section
+
+ Args:
+ etype: Entry type to find
+ Returns:
+ entry matching that type, or None if not found
+ """
+ for entry in self._entries.values():
+ if entry.etype == etype:
+ return entry
+ return None
+
+ def GetEntryContents(self):
+ """Call ObtainContents() for the section
+ """
+ todo = self._entries.values()
+ for passnum in range(3):
+ next_todo = []
+ for entry in todo:
+ if not entry.ObtainContents():
+ next_todo.append(entry)
+ todo = next_todo
+ if not todo:
+ break
+ if todo:
+ self.Raise('Internal error: Could not complete processing of contents: remaining %s' %
+ todo)
+ return True
+
+ def _SetEntryOffsetSize(self, name, offset, size):
+ """Set the offset and size of an entry
+
+ Args:
+ name: Entry name to update
+ offset: New offset, or None to leave alone
+ size: New size, or None to leave alone
+ """
+ entry = self._entries.get(name)
+ if not entry:
+ self._Raise("Unable to set offset/size for unknown entry '%s'" %
+ name)
+ entry.SetOffsetSize(self._skip_at_start + offset if offset else None,
+ size)
+
+ def GetEntryOffsets(self):
+ """Handle entries that want to set the offset/size of other entries
+
+ This calls each entry's GetOffsets() method. If it returns a list
+ of entries to update, it updates them.
+ """
+ for entry in self._entries.values():
+ offset_dict = entry.GetOffsets()
+ for name, info in offset_dict.items():
+ self._SetEntryOffsetSize(name, *info)
+
+
+ def CheckSize(self):
+ """Check that the image contents does not exceed its size, etc."""
+ contents_size = 0
+ for entry in self._entries.values():
+ contents_size = max(contents_size, entry.offset + entry.size)
+
+ contents_size -= self._skip_at_start
+
+ size = self.size
+ if not size:
+ size = self.pad_before + contents_size + self.pad_after
+ size = tools.Align(size, self.align_size)
+
+ if self.size and contents_size > self.size:
+ self._Raise("contents size %#x (%d) exceeds section size %#x (%d)" %
+ (contents_size, contents_size, self.size, self.size))
+ if not self.size:
+ self.size = size
+ if self.size != tools.Align(self.size, self.align_size):
+ self._Raise("Size %#x (%d) does not match align-size %#x (%d)" %
+ (self.size, self.size, self.align_size,
+ self.align_size))
+ return size
+
+ def ListEntries(self, entries, indent):
+ """List the files in the section"""
+ Entry.AddEntryInfo(entries, indent, self.name, 'section', self.size,
+ self.image_pos, None, self.offset, self)
+ for entry in self._entries.values():
+ entry.ListEntries(entries, indent + 1)
+
+ def LoadData(self, decomp=True):
+ for entry in self._entries.values():
+ entry.LoadData(decomp)
+ self.Detail('Loaded data')
+
+ def GetImage(self):
+ """Get the image containing this section
+
+ Note that a top-level section is actually an Image, so this function may
+ return self.
+
+ Returns:
+ Image object containing this section
+ """
+ if not self.section:
+ return self
+ return self.section.GetImage()
+
+ def GetSort(self):
+ """Check if the entries in this section will be sorted
+
+ Returns:
+ True if to be sorted, False if entries will be left in the order
+ they appear in the device tree
+ """
+ return self._sort
+
+ def ReadData(self, decomp=True):
+ tout.Info("ReadData path='%s'" % self.GetPath())
+ parent_data = self.section.ReadData(True)
+ tout.Info('%s: Reading data from offset %#x-%#x, size %#x' %
+ (self.GetPath(), self.offset, self.offset + self.size,
+ self.size))
+ data = parent_data[self.offset:self.offset + self.size]
+ return data
+
+ def ReadChildData(self, child, decomp=True):
+ """Read the data for a particular child entry
+
+ Args:
+ child: Child entry to read data for
+ decomp: True to return uncompressed data, False to leave the data
+ compressed if it is compressed
+
+ Returns:
+ Data contents of entry
+ """
+ parent_data = self.ReadData(True)
+ data = parent_data[child.offset:child.offset + child.size]
+ if decomp:
+ indata = data
+ data = tools.Decompress(indata, child.compress)
+ if child.uncomp_size:
+ tout.Info("%s: Decompressing data size %#x with algo '%s' to data size %#x" %
+ (child.GetPath(), len(indata), child.compress,
+ len(data)))
+ return data
+
+ def WriteChildData(self, child):
+ return True
diff --git a/tools/binman/etype/text.py b/tools/binman/etype/text.py
index c4aa510..da1813a 100644
--- a/tools/binman/etype/text.py
+++ b/tools/binman/etype/text.py
@@ -7,6 +7,7 @@
from entry import Entry, EntryArg
import fdt_util
+import tools
class Entry_text(Entry):
@@ -21,6 +22,8 @@
that contains the string to place in the entry
<xxx> (actual name is the value of text-label): contains the string to
place in the entry.
+ <text>: The text to place in the entry (overrides the above mechanism).
+ This is useful when the text is constant.
Example node:
@@ -43,14 +46,29 @@
message = "a message directly in the node"
};
+ or just:
+
+ text {
+ size = <8>;
+ text = "some text directly in the node"
+ };
+
The text is not itself nul-terminated. This can be achieved, if required,
by setting the size of the entry to something larger than the text.
"""
def __init__(self, section, etype, node):
Entry.__init__(self, section, etype, node)
- self.text_label, = self.GetEntryArgsOrProps(
- [EntryArg('text-label', str)])
- self.value, = self.GetEntryArgsOrProps([EntryArg(self.text_label, str)])
+ value = fdt_util.GetString(self._node, 'text')
+ if value:
+ value = tools.ToBytes(value)
+ else:
+ label, = self.GetEntryArgsOrProps([EntryArg('text-label', str)])
+ self.text_label = label
+ if self.text_label:
+ value, = self.GetEntryArgsOrProps([EntryArg(self.text_label,
+ str)])
+ value = tools.ToBytes(value) if value is not None else value
+ self.value = value
def ObtainContents(self):
if not self.value:
diff --git a/tools/binman/etype/u_boot_dtb.py b/tools/binman/etype/u_boot_dtb.py
index 6263c4e..6c805a6 100644
--- a/tools/binman/etype/u_boot_dtb.py
+++ b/tools/binman/etype/u_boot_dtb.py
@@ -26,3 +26,6 @@
def GetDefaultFilename(self):
return 'u-boot.dtb'
+
+ def GetFdtEtype(self):
+ return 'u-boot-dtb'
diff --git a/tools/binman/etype/u_boot_dtb_with_ucode.py b/tools/binman/etype/u_boot_dtb_with_ucode.py
index 444c51b..cb6c373 100644
--- a/tools/binman/etype/u_boot_dtb_with_ucode.py
+++ b/tools/binman/etype/u_boot_dtb_with_ucode.py
@@ -26,7 +26,7 @@
"""
def __init__(self, section, etype, node):
Entry_blob_dtb.__init__(self, section, etype, node)
- self.ucode_data = ''
+ self.ucode_data = b''
self.collate = False
self.ucode_offset = None
self.ucode_size = None
@@ -36,6 +36,9 @@
def GetDefaultFilename(self):
return 'u-boot.dtb'
+ def GetFdtEtype(self):
+ return 'u-boot-dtb'
+
def ProcessFdt(self, fdt):
# So the module can be loaded without it
import fdt
@@ -53,11 +56,11 @@
return True
# Remove the microcode
- fname = self.GetDefaultFilename()
- fdt = state.GetFdt(fname)
+ etype = self.GetFdtEtype()
+ fdt = state.GetFdtForEtype(etype)
self.ucode = fdt.GetNode('/microcode')
if not self.ucode:
- raise self.Raise("No /microcode node found in '%s'" % fname)
+ raise self.Raise("No /microcode node found in '%s'" % etype)
# There's no need to collate it (move all microcode into one place)
# if we only have one chunk of microcode.
@@ -65,7 +68,7 @@
for node in self.ucode.subnodes:
data_prop = node.props.get('data')
if data_prop:
- self.ucode_data += ''.join(data_prop.bytes)
+ self.ucode_data += data_prop.bytes
if self.collate:
node.DeleteProp('data')
return True
diff --git a/tools/binman/etype/u_boot_spl_bss_pad.py b/tools/binman/etype/u_boot_spl_bss_pad.py
index 00b7ac5..66a296a 100644
--- a/tools/binman/etype/u_boot_spl_bss_pad.py
+++ b/tools/binman/etype/u_boot_spl_bss_pad.py
@@ -38,5 +38,5 @@
bss_size = elf.GetSymbolAddress(fname, '__bss_size')
if not bss_size:
self.Raise('Expected __bss_size symbol in spl/u-boot-spl')
- self.SetContents(chr(0) * bss_size)
+ self.SetContents(tools.GetBytes(0, bss_size))
return True
diff --git a/tools/binman/etype/u_boot_spl_dtb.py b/tools/binman/etype/u_boot_spl_dtb.py
index e735464..1bcd449 100644
--- a/tools/binman/etype/u_boot_spl_dtb.py
+++ b/tools/binman/etype/u_boot_spl_dtb.py
@@ -23,3 +23,6 @@
def GetDefaultFilename(self):
return 'spl/u-boot-spl.dtb'
+
+ def GetFdtEtype(self):
+ return 'u-boot-spl-dtb'
diff --git a/tools/binman/etype/u_boot_spl_elf.py b/tools/binman/etype/u_boot_spl_elf.py
index da328ae..24ee772 100644
--- a/tools/binman/etype/u_boot_spl_elf.py
+++ b/tools/binman/etype/u_boot_spl_elf.py
@@ -12,7 +12,7 @@
"""U-Boot SPL ELF image
Properties / Entry arguments:
- - filename: Filename of SPL u-boot (default 'spl/u-boot')
+ - filename: Filename of SPL u-boot (default 'spl/u-boot-spl')
This is the U-Boot SPL ELF image. It does not include a device tree but can
be relocated to any address for execution.
diff --git a/tools/binman/etype/u_boot_tpl_dtb.py b/tools/binman/etype/u_boot_tpl_dtb.py
index bdeb0f7..81a3970 100644
--- a/tools/binman/etype/u_boot_tpl_dtb.py
+++ b/tools/binman/etype/u_boot_tpl_dtb.py
@@ -23,3 +23,6 @@
def GetDefaultFilename(self):
return 'tpl/u-boot-tpl.dtb'
+
+ def GetFdtEtype(self):
+ return 'u-boot-tpl-dtb'
diff --git a/tools/binman/etype/u_boot_tpl_dtb_with_ucode.py b/tools/binman/etype/u_boot_tpl_dtb_with_ucode.py
index 71e04fc..ce19a49 100644
--- a/tools/binman/etype/u_boot_tpl_dtb_with_ucode.py
+++ b/tools/binman/etype/u_boot_tpl_dtb_with_ucode.py
@@ -23,3 +23,6 @@
def GetDefaultFilename(self):
return 'tpl/u-boot-tpl.dtb'
+
+ def GetFdtEtype(self):
+ return 'u-boot-tpl-dtb'
diff --git a/tools/binman/etype/u_boot_tpl_elf.py b/tools/binman/etype/u_boot_tpl_elf.py
new file mode 100644
index 0000000..9cc1cc2
--- /dev/null
+++ b/tools/binman/etype/u_boot_tpl_elf.py
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2018 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# Entry-type module for U-Boot TPL ELF image
+#
+
+from entry import Entry
+from blob import Entry_blob
+
+class Entry_u_boot_tpl_elf(Entry_blob):
+ """U-Boot TPL ELF image
+
+ Properties / Entry arguments:
+ - filename: Filename of TPL u-boot (default 'tpl/u-boot-tpl')
+
+ This is the U-Boot TPL ELF image. It does not include a device tree but can
+ be relocated to any address for execution.
+ """
+ def __init__(self, section, etype, node):
+ Entry_blob.__init__(self, section, etype, node)
+
+ def GetDefaultFilename(self):
+ return 'tpl/u-boot-tpl'
diff --git a/tools/binman/etype/u_boot_ucode.py b/tools/binman/etype/u_boot_ucode.py
index a00e530..dee8848 100644
--- a/tools/binman/etype/u_boot_ucode.py
+++ b/tools/binman/etype/u_boot_ucode.py
@@ -69,7 +69,7 @@
if entry and entry.target_offset:
found = True
if not found:
- self.data = ''
+ self.data = b''
return True
# Get the microcode from the device tree entry. If it is not available
# yet, return False so we will be called later. If the section simply
@@ -87,7 +87,7 @@
if not fdt_entry.collate:
# This binary can be empty
- self.data = ''
+ self.data = b''
return True
# Write it out to a file
diff --git a/tools/binman/etype/u_boot_with_ucode_ptr.py b/tools/binman/etype/u_boot_with_ucode_ptr.py
index da0e124..cb7dbc6 100644
--- a/tools/binman/etype/u_boot_with_ucode_ptr.py
+++ b/tools/binman/etype/u_boot_with_ucode_ptr.py
@@ -49,7 +49,7 @@
def ProcessContents(self):
# If the image does not need microcode, there is nothing to do
if not self.target_offset:
- return
+ return True
# Get the offset of the microcode
ucode_entry = self.section.FindEntryType('u-boot-ucode')
@@ -91,6 +91,6 @@
# Write the microcode offset and size into the entry
offset_and_size = struct.pack('<2L', offset, size)
self.target_offset -= self.image_pos
- self.ProcessContentsUpdate(self.data[:self.target_offset] +
- offset_and_size +
- self.data[self.target_offset + 8:])
+ return self.ProcessContentsUpdate(self.data[:self.target_offset] +
+ offset_and_size +
+ self.data[self.target_offset + 8:])
diff --git a/tools/binman/etype/vblock.py b/tools/binman/etype/vblock.py
index 334ff9f..91fa2f7 100644
--- a/tools/binman/etype/vblock.py
+++ b/tools/binman/etype/vblock.py
@@ -51,7 +51,7 @@
def ObtainContents(self):
# Join up the data files to be signed
- input_data = ''
+ input_data = b''
for entry_phandle in self.content:
data = self.section.GetContentsByPhandle(entry_phandle, self)
if data is None:
diff --git a/tools/binman/fmap_util.py b/tools/binman/fmap_util.py
index be3cbee..d0f956b 100644
--- a/tools/binman/fmap_util.py
+++ b/tools/binman/fmap_util.py
@@ -8,9 +8,12 @@
import collections
import struct
+import sys
+
+import tools
# constants imported from lib/fmap.h
-FMAP_SIGNATURE = '__FMAP__'
+FMAP_SIGNATURE = b'__FMAP__'
FMAP_VER_MAJOR = 1
FMAP_VER_MINOR = 0
FMAP_STRLEN = 32
@@ -50,6 +53,8 @@
def NameToFmap(name):
+ if type(name) == bytes and sys.version_info[0] >= 3:
+ name = name.decode('utf-8') # pragma: no cover (for Python 2)
return name.replace('\0', '').replace('-', '_').upper()
def ConvertName(field_names, fields):
@@ -65,7 +70,7 @@
value: value of that field (string for the ones we support)
"""
name_index = field_names.index('name')
- fields[name_index] = NameToFmap(fields[name_index])
+ fields[name_index] = tools.ToBytes(NameToFmap(fields[name_index]))
def DecodeFmap(data):
"""Decode a flashmap into a header and list of areas
@@ -106,7 +111,8 @@
ConvertName(names, params)
return struct.pack(fmt, *params)
- values = FmapHeader(FMAP_SIGNATURE, 1, 0, 0, image_size, name, len(areas))
+ values = FmapHeader(FMAP_SIGNATURE, 1, 0, 0, image_size,
+ tools.FromUnicode(name), len(areas))
blob = _FormatBlob(FMAP_HEADER_FORMAT, FMAP_HEADER_NAMES, values)
for area in areas:
blob += _FormatBlob(FMAP_AREA_FORMAT, FMAP_AREA_NAMES, area)
diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py
index daea1ea..0f3b70b 100644
--- a/tools/binman/ftest.py
+++ b/tools/binman/ftest.py
@@ -6,6 +6,8 @@
#
# python -m unittest func_test.TestFunctional.testHelp
+from __future__ import print_function
+
import hashlib
from optparse import OptionParser
import os
@@ -16,51 +18,65 @@
import unittest
import binman
+import cbfs_util
import cmdline
import command
import control
import elf
import fdt
+from etype import fdtmap
+from etype import image_header
import fdt_util
import fmap_util
import test_util
+import gzip
+from image import Image
import state
import tools
import tout
# Contents of test files, corresponding to different entry types
-U_BOOT_DATA = '1234'
-U_BOOT_IMG_DATA = 'img'
-U_BOOT_SPL_DATA = '56780123456789abcde'
-U_BOOT_TPL_DATA = 'tpl'
-BLOB_DATA = '89'
-ME_DATA = '0abcd'
-VGA_DATA = 'vga'
-U_BOOT_DTB_DATA = 'udtb'
-U_BOOT_SPL_DTB_DATA = 'spldtb'
-U_BOOT_TPL_DTB_DATA = 'tpldtb'
-X86_START16_DATA = 'start16'
-X86_START16_SPL_DATA = 'start16spl'
-X86_START16_TPL_DATA = 'start16tpl'
-PPC_MPC85XX_BR_DATA = 'ppcmpc85xxbr'
-U_BOOT_NODTB_DATA = 'nodtb with microcode pointer somewhere in here'
-U_BOOT_SPL_NODTB_DATA = 'splnodtb with microcode pointer somewhere in here'
-U_BOOT_TPL_NODTB_DATA = 'tplnodtb with microcode pointer somewhere in here'
-FSP_DATA = 'fsp'
-CMC_DATA = 'cmc'
-VBT_DATA = 'vbt'
-MRC_DATA = 'mrc'
+U_BOOT_DATA = b'1234'
+U_BOOT_IMG_DATA = b'img'
+U_BOOT_SPL_DATA = b'56780123456789abcde'
+U_BOOT_TPL_DATA = b'tpl'
+BLOB_DATA = b'89'
+ME_DATA = b'0abcd'
+VGA_DATA = b'vga'
+U_BOOT_DTB_DATA = b'udtb'
+U_BOOT_SPL_DTB_DATA = b'spldtb'
+U_BOOT_TPL_DTB_DATA = b'tpldtb'
+X86_START16_DATA = b'start16'
+X86_START16_SPL_DATA = b'start16spl'
+X86_START16_TPL_DATA = b'start16tpl'
+PPC_MPC85XX_BR_DATA = b'ppcmpc85xxbr'
+U_BOOT_NODTB_DATA = b'nodtb with microcode pointer somewhere in here'
+U_BOOT_SPL_NODTB_DATA = b'splnodtb with microcode pointer somewhere in here'
+U_BOOT_TPL_NODTB_DATA = b'tplnodtb with microcode pointer somewhere in here'
+FSP_DATA = b'fsp'
+CMC_DATA = b'cmc'
+VBT_DATA = b'vbt'
+MRC_DATA = b'mrc'
TEXT_DATA = 'text'
TEXT_DATA2 = 'text2'
TEXT_DATA3 = 'text3'
-CROS_EC_RW_DATA = 'ecrw'
-GBB_DATA = 'gbbd'
-BMPBLK_DATA = 'bmp'
-VBLOCK_DATA = 'vblk'
-FILES_DATA = ("sorry I'm late\nOh, don't bother apologising, I'm " +
- "sorry you're alive\n")
-COMPRESS_DATA = 'data to compress'
-REFCODE_DATA = 'refcode'
+CROS_EC_RW_DATA = b'ecrw'
+GBB_DATA = b'gbbd'
+BMPBLK_DATA = b'bmp'
+VBLOCK_DATA = b'vblk'
+FILES_DATA = (b"sorry I'm late\nOh, don't bother apologising, I'm " +
+ b"sorry you're alive\n")
+COMPRESS_DATA = b'compress xxxxxxxxxxxxxxxxxxxxxx data'
+REFCODE_DATA = b'refcode'
+
+# The expected size for the device tree in some tests
+EXTRACT_DTB_SIZE = 0x3c9
+
+# Properties expected to be in the device tree when update_dtb is used
+BASE_DTB_PROPS = ['offset', 'size', 'image-pos']
+
+# Extra properties expected to be in the device tree when allow-repack is used
+REPACK_DTB_PROPS = ['orig-offset', 'orig-size']
class TestFunctional(unittest.TestCase):
@@ -119,11 +135,11 @@
TestFunctional._MakeInputFile('refcode.bin', REFCODE_DATA)
# ELF file with a '_dt_ucode_base_size' symbol
- with open(self.TestFile('u_boot_ucode_ptr')) as fd:
+ with open(self.TestFile('u_boot_ucode_ptr'), 'rb') as fd:
TestFunctional._MakeInputFile('u-boot', fd.read())
# Intel flash descriptor file
- with open(self.TestFile('descriptor.bin')) as fd:
+ with open(self.TestFile('descriptor.bin'), 'rb') as fd:
TestFunctional._MakeInputFile('descriptor.bin', fd.read())
shutil.copytree(self.TestFile('files'),
@@ -131,13 +147,53 @@
TestFunctional._MakeInputFile('compress', COMPRESS_DATA)
+ # Travis-CI may have an old lz4
+ self.have_lz4 = True
+ try:
+ tools.Run('lz4', '--no-frame-crc', '-c',
+ os.path.join(self._indir, 'u-boot.bin'))
+ except:
+ self.have_lz4 = False
+
@classmethod
def tearDownClass(self):
"""Remove the temporary input directory and its contents"""
- if self._indir:
- shutil.rmtree(self._indir)
+ if self.preserve_indir:
+ print('Preserving input dir: %s' % self._indir)
+ else:
+ if self._indir:
+ shutil.rmtree(self._indir)
self._indir = None
+ @classmethod
+ def setup_test_args(cls, preserve_indir=False, preserve_outdirs=False,
+ toolpath=None, verbosity=None):
+ """Accept arguments controlling test execution
+
+ Args:
+ preserve_indir: Preserve the shared input directory used by all
+ tests in this class.
+ preserve_outdir: Preserve the output directories used by tests. Each
+ test has its own, so this is normally only useful when running a
+ single test.
+ toolpath: ist of paths to use for tools
+ """
+ cls.preserve_indir = preserve_indir
+ cls.preserve_outdirs = preserve_outdirs
+ cls.toolpath = toolpath
+ cls.verbosity = verbosity
+
+ def _CheckLz4(self):
+ if not self.have_lz4:
+ self.skipTest('lz4 --no-frame-crc not available')
+
+ def _CleanupOutputDir(self):
+ """Remove the temporary output directory"""
+ if self.preserve_outdirs:
+ print('Preserving output dir: %s' % tools.outdir)
+ else:
+ tools._FinaliseForTest()
+
def setUp(self):
# Enable this to turn on debugging output
# tout.Init(tout.DEBUG)
@@ -145,7 +201,29 @@
def tearDown(self):
"""Remove the temporary output directory"""
- tools._FinaliseForTest()
+ self._CleanupOutputDir()
+
+ def _SetupImageInTmpdir(self):
+ """Set up the output image in a new temporary directory
+
+ This is used when an image has been generated in the output directory,
+ but we want to run binman again. This will create a new output
+ directory and fail to delete the original one.
+
+ This creates a new temporary directory, copies the image to it (with a
+ new name) and removes the old output directory.
+
+ Returns:
+ Tuple:
+ Temporary directory to use
+ New image filename
+ """
+ image_fname = tools.GetOutputFilename('image.bin')
+ tmpdir = tempfile.mkdtemp(prefix='binman.')
+ updated_fname = os.path.join(tmpdir, 'image-updated.bin')
+ tools.WriteFile(updated_fname, tools.ReadFile(image_fname))
+ self._CleanupOutputDir()
+ return tmpdir, updated_fname
@classmethod
def _ResetDtbs(self):
@@ -167,7 +245,7 @@
result.stdout + result.stderr))
return result
- def _DoBinman(self, *args):
+ def _DoBinman(self, *argv):
"""Run binman using directly (in the same process)
Args:
@@ -175,16 +253,14 @@
Returns:
Return value (0 for success)
"""
- args = list(args)
- if '-D' in sys.argv:
- args = args + ['-D']
- (options, args) = cmdline.ParseArgs(args)
- options.pager = 'binman-invalid-pager'
- options.build_dir = self._indir
+ argv = list(argv)
+ args = cmdline.ParseArgs(argv)
+ args.pager = 'binman-invalid-pager'
+ args.build_dir = self._indir
# For testing, you can force an increase in verbosity here
- # options.verbosity = tout.DEBUG
- return control.Binman(options, args)
+ # args.verbosity = tout.DEBUG
+ return control.Binman(args)
def _DoTestFile(self, fname, debug=False, map=False, update_dtb=False,
entry_args=None, images=None, use_real_dtb=False,
@@ -202,19 +278,25 @@
value: value of that arg
images: List of image names to build
"""
- args = ['-p', '-I', self._indir, '-d', self.TestFile(fname)]
+ args = []
if debug:
args.append('-D')
+ if verbosity is not None:
+ args.append('-v%d' % verbosity)
+ elif self.verbosity:
+ args.append('-v%d' % self.verbosity)
+ if self.toolpath:
+ for path in self.toolpath:
+ args += ['--toolpath', path]
+ args += ['build', '-p', '-I', self._indir, '-d', self.TestFile(fname)]
if map:
args.append('-m')
if update_dtb:
- args.append('-up')
+ args.append('-u')
if not use_real_dtb:
args.append('--fake-dtb')
- if verbosity is not None:
- args.append('-v%d' % verbosity)
if entry_args:
- for arg, value in entry_args.iteritems():
+ for arg, value in entry_args.items():
args.append('-a%s=%s' % (arg, value))
if images:
for image in images:
@@ -234,12 +316,12 @@
Returns:
Contents of device-tree binary
"""
- tools.PrepareOutputDir(None)
- dtb = fdt_util.EnsureCompiled(self.TestFile(fname))
- with open(dtb) as fd:
+ tmpdir = tempfile.mkdtemp(prefix='binmant.')
+ dtb = fdt_util.EnsureCompiled(self.TestFile(fname), tmpdir)
+ with open(dtb, 'rb') as fd:
data = fd.read()
TestFunctional._MakeInputFile(outfile, data)
- tools.FinaliseOutputDir()
+ shutil.rmtree(tmpdir)
return data
def _GetDtbContentsForSplTpl(self, dtb_data, name):
@@ -291,7 +373,6 @@
# Use the compiled test file as the u-boot-dtb input
if use_real_dtb:
dtb_data = self._SetupDtb(fname)
- infile = os.path.join(self._indir, 'u-boot.dtb')
# For testing purposes, make a copy of the DT for SPL and TPL. Add
# a node indicating which it is, so aid verification.
@@ -317,13 +398,24 @@
map_data = fd.read()
else:
map_data = None
- with open(image_fname) as fd:
+ with open(image_fname, 'rb') as fd:
return fd.read(), dtb_data, map_data, out_dtb_fname
finally:
# Put the test file back
if reset_dtbs and use_real_dtb:
self._ResetDtbs()
+ def _DoReadFileRealDtb(self, fname):
+ """Run binman with a real .dtb file and return the resulting data
+
+ Args:
+ fname: DT source filename to use (e.g. 082_fdt_update_all.dts)
+
+ Returns:
+ Resulting image contents
+ """
+ return self._DoReadFileDtb(fname, use_real_dtb=True, update_dtb=True)[0]
+
def _DoReadFile(self, fname, use_real_dtb=False):
"""Helper function which discards the device-tree binary
@@ -379,7 +471,7 @@
Args:
Filename of ELF file to use as SPL
"""
- with open(self.TestFile(src_fname)) as fd:
+ with open(self.TestFile(src_fname), 'rb') as fd:
TestFunctional._MakeInputFile('spl/u-boot-spl', fd.read())
@classmethod
@@ -396,7 +488,7 @@
for grep in grep_list:
if grep in target:
return
- self.fail("Error: '%' not found in '%s'" % (grep_list, target))
+ self.fail("Error: '%s' not found in '%s'" % (grep_list, target))
def CheckNoGaps(self, entries):
"""Check that all entries fit together without gaps
@@ -420,16 +512,16 @@
"""
return struct.unpack('>L', dtb[4:8])[0]
- def _GetPropTree(self, dtb, prop_names):
+ def _GetPropTree(self, dtb, prop_names, prefix='/binman/'):
def AddNode(node, path):
if node.name != '/':
path += '/' + node.name
+ for prop in node.props.values():
+ if prop.name in prop_names:
+ prop_path = path + ':' + prop.name
+ tree[prop_path[len(prefix):]] = fdt_util.fdt32_to_cpu(
+ prop.value)
for subnode in node.subnodes:
- for prop in subnode.props.values():
- if prop.name in prop_names:
- prop_path = path + '/' + subnode.name + ':' + prop.name
- tree[prop_path[len('/binman/'):]] = fdt_util.fdt32_to_cpu(
- prop.value)
AddNode(subnode, path)
tree = {}
@@ -471,20 +563,20 @@
"""Test that we can run it with a specific board"""
self._SetupDtb('005_simple.dts', 'sandbox/u-boot.dtb')
TestFunctional._MakeInputFile('sandbox/u-boot.bin', U_BOOT_DATA)
- result = self._DoBinman('-b', 'sandbox')
+ result = self._DoBinman('build', '-b', 'sandbox')
self.assertEqual(0, result)
def testNeedBoard(self):
"""Test that we get an error when no board ius supplied"""
with self.assertRaises(ValueError) as e:
- result = self._DoBinman()
+ result = self._DoBinman('build')
self.assertIn("Must provide a board to process (use -b <board>)",
str(e.exception))
def testMissingDt(self):
"""Test that an invalid device-tree file generates an error"""
with self.assertRaises(Exception) as e:
- self._RunBinman('-d', 'missing_file')
+ self._RunBinman('build', '-d', 'missing_file')
# We get one error from libfdt, and a different one from fdtget.
self.AssertInList(["Couldn't open blob from 'missing_file'",
'No such file or directory'], str(e.exception))
@@ -496,26 +588,26 @@
will come from the device-tree compiler (dtc).
"""
with self.assertRaises(Exception) as e:
- self._RunBinman('-d', self.TestFile('001_invalid.dts'))
+ self._RunBinman('build', '-d', self.TestFile('001_invalid.dts'))
self.assertIn("FATAL ERROR: Unable to parse input tree",
str(e.exception))
def testMissingNode(self):
"""Test that a device tree without a 'binman' node generates an error"""
with self.assertRaises(Exception) as e:
- self._DoBinman('-d', self.TestFile('002_missing_node.dts'))
+ self._DoBinman('build', '-d', self.TestFile('002_missing_node.dts'))
self.assertIn("does not have a 'binman' node", str(e.exception))
def testEmpty(self):
"""Test that an empty binman node works OK (i.e. does nothing)"""
- result = self._RunBinman('-d', self.TestFile('003_empty.dts'))
+ result = self._RunBinman('build', '-d', self.TestFile('003_empty.dts'))
self.assertEqual(0, len(result.stderr))
self.assertEqual(0, result.return_code)
def testInvalidEntry(self):
"""Test that an invalid entry is flagged"""
with self.assertRaises(Exception) as e:
- result = self._RunBinman('-d',
+ result = self._RunBinman('build', '-d',
self.TestFile('004_invalid_entry.dts'))
self.assertIn("Unknown entry type 'not-a-valid-type' in node "
"'/binman/not-a-valid-type'", str(e.exception))
@@ -527,7 +619,7 @@
def testSimpleDebug(self):
"""Test a simple binman run with debugging enabled"""
- data = self._DoTestFile('005_simple.dts', debug=True)
+ self._DoTestFile('005_simple.dts', debug=True)
def testDual(self):
"""Test that we can handle creating two images
@@ -538,22 +630,22 @@
self.assertEqual(0, retcode)
image = control.images['image1']
- self.assertEqual(len(U_BOOT_DATA), image._size)
+ self.assertEqual(len(U_BOOT_DATA), image.size)
fname = tools.GetOutputFilename('image1.bin')
self.assertTrue(os.path.exists(fname))
- with open(fname) as fd:
+ with open(fname, 'rb') as fd:
data = fd.read()
self.assertEqual(U_BOOT_DATA, data)
image = control.images['image2']
- self.assertEqual(3 + len(U_BOOT_DATA) + 5, image._size)
+ self.assertEqual(3 + len(U_BOOT_DATA) + 5, image.size)
fname = tools.GetOutputFilename('image2.bin')
self.assertTrue(os.path.exists(fname))
- with open(fname) as fd:
+ with open(fname, 'rb') as fd:
data = fd.read()
self.assertEqual(U_BOOT_DATA, data[3:7])
- self.assertEqual(chr(0) * 3, data[:3])
- self.assertEqual(chr(0) * 5, data[7:])
+ self.assertEqual(tools.GetBytes(0, 3), data[:3])
+ self.assertEqual(tools.GetBytes(0, 5), data[7:])
def testBadAlign(self):
"""Test that an invalid alignment value is detected"""
@@ -602,7 +694,7 @@
self.assertEqual(61, entry.offset)
self.assertEqual(len(U_BOOT_DATA), entry.size)
- self.assertEqual(65, image._size)
+ self.assertEqual(65, image.size)
def testPackExtra(self):
"""Test that extra packing feature works as expected"""
@@ -646,7 +738,7 @@
self.assertEqual(64, entry.size)
self.CheckNoGaps(entries)
- self.assertEqual(128, image._size)
+ self.assertEqual(128, image.size)
def testPackAlignPowerOf2(self):
"""Test that invalid entry alignment is detected"""
@@ -704,7 +796,7 @@
self.assertEqual(0, retcode)
self.assertIn('image', control.images)
image = control.images['image']
- self.assertEqual(7, image._size)
+ self.assertEqual(7, image.size)
def testPackImageSizeAlign(self):
"""Test that image size alignemnt works as expected"""
@@ -712,7 +804,7 @@
self.assertEqual(0, retcode)
self.assertIn('image', control.images)
image = control.images['image']
- self.assertEqual(16, image._size)
+ self.assertEqual(16, image.size)
def testPackInvalidImageAlign(self):
"""Test that invalid image alignment is detected"""
@@ -725,14 +817,15 @@
"""Test that invalid image alignment is detected"""
with self.assertRaises(ValueError) as e:
self._DoTestFile('020_pack_inv_image_align_power2.dts')
- self.assertIn("Section '/binman': Alignment size 131 must be a power of "
+ self.assertIn("Image '/binman': Alignment size 131 must be a power of "
"two", str(e.exception))
def testImagePadByte(self):
"""Test that the image pad byte can be specified"""
self._SetupSplElf()
data = self._DoReadFile('021_image_pad.dts')
- self.assertEqual(U_BOOT_SPL_DATA + (chr(0xff) * 1) + U_BOOT_DATA, data)
+ self.assertEqual(U_BOOT_SPL_DATA + tools.GetBytes(0xff, 1) +
+ U_BOOT_DATA, data)
def testImageName(self):
"""Test that image files can be named"""
@@ -755,8 +848,8 @@
"""Test that entries can be sorted"""
self._SetupSplElf()
data = self._DoReadFile('024_sorted.dts')
- self.assertEqual(chr(0) * 1 + U_BOOT_SPL_DATA + chr(0) * 2 +
- U_BOOT_DATA, data)
+ self.assertEqual(tools.GetBytes(0, 1) + U_BOOT_SPL_DATA +
+ tools.GetBytes(0, 2) + U_BOOT_DATA, data)
def testPackZeroOffset(self):
"""Test that an entry at offset 0 is not given a new offset"""
@@ -775,7 +868,7 @@
"""Test that the end-at-4gb property requires a size property"""
with self.assertRaises(ValueError) as e:
self._DoTestFile('027_pack_4gb_no_size.dts')
- self.assertIn("Section '/binman': Section size must be provided when "
+ self.assertIn("Image '/binman': Section size must be provided when "
"using end-at-4gb", str(e.exception))
def test4gbAndSkipAtStartTogether(self):
@@ -783,7 +876,7 @@
together"""
with self.assertRaises(ValueError) as e:
self._DoTestFile('80_4gb_and_skip_at_start_together.dts')
- self.assertIn("Section '/binman': Provide either 'end-at-4gb' or "
+ self.assertIn("Image '/binman': Provide either 'end-at-4gb' or "
"'skip-at-start'", str(e.exception))
def testPackX86RomOutside(self):
@@ -798,16 +891,16 @@
"""Test that a basic x86 ROM can be created"""
self._SetupSplElf()
data = self._DoReadFile('029_x86-rom.dts')
- self.assertEqual(U_BOOT_DATA + chr(0) * 7 + U_BOOT_SPL_DATA +
- chr(0) * 2, data)
+ self.assertEqual(U_BOOT_DATA + tools.GetBytes(0, 7) + U_BOOT_SPL_DATA +
+ tools.GetBytes(0, 2), data)
def testPackX86RomMeNoDesc(self):
"""Test that an invalid Intel descriptor entry is detected"""
- TestFunctional._MakeInputFile('descriptor.bin', '')
+ TestFunctional._MakeInputFile('descriptor.bin', b'')
with self.assertRaises(ValueError) as e:
self._DoTestFile('031_x86-rom-me.dts')
- self.assertIn("Node '/binman/intel-descriptor': Cannot find FD "
- "signature", str(e.exception))
+ self.assertIn("Node '/binman/intel-descriptor': Cannot find Intel Flash Descriptor (FD) signature",
+ str(e.exception))
def testPackX86RomBadDesc(self):
"""Test that the Intel requires a descriptor entry"""
@@ -820,6 +913,9 @@
def testPackX86RomMe(self):
"""Test that an x86 ROM with an ME region can be created"""
data = self._DoReadFile('031_x86-rom-me.dts')
+ expected_desc = tools.ReadFile(self.TestFile('descriptor.bin'))
+ if data[:0x1000] != expected_desc:
+ self.fail('Expected descriptor binary at start of image')
self.assertEqual(ME_DATA, data[0x1000:0x1000 + len(ME_DATA)])
def testPackVga(self):
@@ -900,8 +996,8 @@
"""
first, pos_and_size = self._RunMicrocodeTest('034_x86_ucode.dts',
U_BOOT_NODTB_DATA)
- self.assertEqual('nodtb with microcode' + pos_and_size +
- ' somewhere in here', first)
+ self.assertEqual(b'nodtb with microcode' + pos_and_size +
+ b' somewhere in here', first)
def _RunPackUbootSingleMicrocode(self):
"""Test that x86 microcode can be handled correctly
@@ -932,8 +1028,8 @@
pos_and_size = struct.pack('<2L', 0xfffffe00 + ucode_pos,
len(ucode_data))
first = data[:len(U_BOOT_NODTB_DATA)]
- self.assertEqual('nodtb with microcode' + pos_and_size +
- ' somewhere in here', first)
+ self.assertEqual(b'nodtb with microcode' + pos_and_size +
+ b' somewhere in here', first)
def testPackUbootSingleMicrocode(self):
"""Test that x86 microcode can be handled correctly with fdt_normal.
@@ -970,7 +1066,7 @@
"""Test that a U-Boot binary without the microcode symbol is detected"""
# ELF file without a '_dt_ucode_base_size' symbol
try:
- with open(self.TestFile('u_boot_no_ucode_ptr')) as fd:
+ with open(self.TestFile('u_boot_no_ucode_ptr'), 'rb') as fd:
TestFunctional._MakeInputFile('u-boot', fd.read())
with self.assertRaises(ValueError) as e:
@@ -980,7 +1076,7 @@
finally:
# Put the original file back
- with open(self.TestFile('u_boot_ucode_ptr')) as fd:
+ with open(self.TestFile('u_boot_ucode_ptr'), 'rb') as fd:
TestFunctional._MakeInputFile('u-boot', fd.read())
def testMicrocodeNotInImage(self):
@@ -993,7 +1089,7 @@
def testWithoutMicrocode(self):
"""Test that we can cope with an image without microcode (e.g. qemu)"""
- with open(self.TestFile('u_boot_no_ucode_ptr')) as fd:
+ with open(self.TestFile('u_boot_no_ucode_ptr'), 'rb') as fd:
TestFunctional._MakeInputFile('u-boot', fd.read())
data, dtb, _, _ = self._DoReadFileDtb('044_x86_optional_ucode.dts', True)
@@ -1006,7 +1102,7 @@
used_len = len(U_BOOT_NODTB_DATA) + fdt_len
third = data[used_len:]
- self.assertEqual(chr(0) * (0x200 - used_len), third)
+ self.assertEqual(tools.GetBytes(0, 0x200 - used_len), third)
def testUnknownPosSize(self):
"""Test that microcode must be placed within the image"""
@@ -1035,7 +1131,8 @@
# ELF file with a '__bss_size' symbol
self._SetupSplElf()
data = self._DoReadFile('047_spl_bss_pad.dts')
- self.assertEqual(U_BOOT_SPL_DATA + (chr(0) * 10) + U_BOOT_DATA, data)
+ self.assertEqual(U_BOOT_SPL_DATA + tools.GetBytes(0, 10) + U_BOOT_DATA,
+ data)
def testSplBssPadMissing(self):
"""Test that a missing symbol is detected"""
@@ -1067,8 +1164,8 @@
self._SetupSplElf('u_boot_ucode_ptr')
first, pos_and_size = self._RunMicrocodeTest(dts, U_BOOT_SPL_NODTB_DATA,
ucode_second=ucode_second)
- self.assertEqual('splnodtb with microc' + pos_and_size +
- 'ter somewhere in here', first)
+ self.assertEqual(b'splnodtb with microc' + pos_and_size +
+ b'ter somewhere in here', first)
def testPackUbootSplMicrocode(self):
"""Test that x86 microcode can be handled correctly in SPL"""
@@ -1109,9 +1206,9 @@
self._SetupSplElf('u_boot_binman_syms')
data = self._DoReadFile('053_symbols.dts')
sym_values = struct.pack('<LQL', 0x24 + 0, 0x24 + 24, 0x24 + 20)
- expected = (sym_values + U_BOOT_SPL_DATA[16:] + chr(0xff) +
- U_BOOT_DATA +
- sym_values + U_BOOT_SPL_DATA[16:])
+ expected = (sym_values + U_BOOT_SPL_DATA[16:] +
+ tools.GetBytes(0xff, 1) + U_BOOT_DATA + sym_values +
+ U_BOOT_SPL_DATA[16:])
self.assertEqual(expected, data)
def testPackUnitAddress(self):
@@ -1122,8 +1219,9 @@
def testSections(self):
"""Basic test of sections"""
data = self._DoReadFile('055_sections.dts')
- expected = (U_BOOT_DATA + '!' * 12 + U_BOOT_DATA + 'a' * 12 +
- U_BOOT_DATA + '&' * 4)
+ expected = (U_BOOT_DATA + tools.GetBytes(ord('!'), 12) +
+ U_BOOT_DATA + tools.GetBytes(ord('a'), 12) +
+ U_BOOT_DATA + tools.GetBytes(ord('&'), 4))
self.assertEqual(expected, data)
def testMap(self):
@@ -1154,16 +1252,20 @@
"""Test that obtaining the contents works as expected"""
with self.assertRaises(ValueError) as e:
self._DoReadFile('057_unknown_contents.dts', True)
- self.assertIn("Section '/binman': Internal error: Could not complete "
+ self.assertIn("Image '/binman': Internal error: Could not complete "
"processing of contents: remaining [<_testing.Entry__testing ",
str(e.exception))
def testBadChangeSize(self):
"""Test that trying to change the size of an entry fails"""
- with self.assertRaises(ValueError) as e:
- self._DoReadFile('059_change_size.dts', True)
- self.assertIn("Node '/binman/_testing': Cannot update entry size from "
- '2 to 1', str(e.exception))
+ try:
+ state.SetAllowEntryExpansion(False)
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFile('059_change_size.dts', True)
+ self.assertIn("Node '/binman/_testing': Cannot update entry size from 2 to 3",
+ str(e.exception))
+ finally:
+ state.SetAllowEntryExpansion(True)
def testUpdateFdt(self):
"""Test that we can update the device tree with offset/size info"""
@@ -1171,12 +1273,12 @@
update_dtb=True)
dtb = fdt.Fdt(out_dtb_fname)
dtb.Scan()
- props = self._GetPropTree(dtb, ['offset', 'size', 'image-pos'])
+ props = self._GetPropTree(dtb, BASE_DTB_PROPS + REPACK_DTB_PROPS)
self.assertEqual({
'image-pos': 0,
'offset': 0,
'_testing:offset': 32,
- '_testing:size': 1,
+ '_testing:size': 2,
'_testing:image-pos': 32,
'section@0/u-boot:offset': 0,
'section@0/u-boot:size': len(U_BOOT_DATA),
@@ -1240,7 +1342,8 @@
def testEntryArgsInvalidFormat(self):
"""Test that an invalid entry-argument format is detected"""
- args = ['-d', self.TestFile('064_entry_args_required.dts'), '-ano-value']
+ args = ['build', '-d', self.TestFile('064_entry_args_required.dts'),
+ '-ano-value']
with self.assertRaises(ValueError) as e:
self._DoBinman(*args)
self.assertIn("Invalid entry arguemnt 'no-value'", str(e.exception))
@@ -1281,8 +1384,10 @@
}
data, _, _, _ = self._DoReadFileDtb('066_text.dts',
entry_args=entry_args)
- expected = (TEXT_DATA + chr(0) * (8 - len(TEXT_DATA)) + TEXT_DATA2 +
- TEXT_DATA3 + 'some text')
+ expected = (tools.ToBytes(TEXT_DATA) +
+ tools.GetBytes(0, 8 - len(TEXT_DATA)) +
+ tools.ToBytes(TEXT_DATA2) + tools.ToBytes(TEXT_DATA3) +
+ b'some text' + b'more text')
self.assertEqual(expected, data)
def testEntryDocs(self):
@@ -1303,32 +1408,33 @@
"""Basic test of generation of a flashrom fmap"""
data = self._DoReadFile('067_fmap.dts')
fhdr, fentries = fmap_util.DecodeFmap(data[32:])
- expected = U_BOOT_DATA + '!' * 12 + U_BOOT_DATA + 'a' * 12
+ expected = (U_BOOT_DATA + tools.GetBytes(ord('!'), 12) +
+ U_BOOT_DATA + tools.GetBytes(ord('a'), 12))
self.assertEqual(expected, data[:32])
- self.assertEqual('__FMAP__', fhdr.signature)
+ self.assertEqual(b'__FMAP__', fhdr.signature)
self.assertEqual(1, fhdr.ver_major)
self.assertEqual(0, fhdr.ver_minor)
self.assertEqual(0, fhdr.base)
self.assertEqual(16 + 16 +
fmap_util.FMAP_HEADER_LEN +
fmap_util.FMAP_AREA_LEN * 3, fhdr.image_size)
- self.assertEqual('FMAP', fhdr.name)
+ self.assertEqual(b'FMAP', fhdr.name)
self.assertEqual(3, fhdr.nareas)
for fentry in fentries:
self.assertEqual(0, fentry.flags)
self.assertEqual(0, fentries[0].offset)
self.assertEqual(4, fentries[0].size)
- self.assertEqual('RO_U_BOOT', fentries[0].name)
+ self.assertEqual(b'RO_U_BOOT', fentries[0].name)
self.assertEqual(16, fentries[1].offset)
self.assertEqual(4, fentries[1].size)
- self.assertEqual('RW_U_BOOT', fentries[1].name)
+ self.assertEqual(b'RW_U_BOOT', fentries[1].name)
self.assertEqual(32, fentries[2].offset)
self.assertEqual(fmap_util.FMAP_HEADER_LEN +
fmap_util.FMAP_AREA_LEN * 3, fentries[2].size)
- self.assertEqual('FMAP', fentries[2].name)
+ self.assertEqual(b'FMAP', fentries[2].name)
def testBlobNamedByArg(self):
"""Test we can add a blob with the filename coming from an entry arg"""
@@ -1341,7 +1447,7 @@
def testFill(self):
"""Test for an fill entry type"""
data = self._DoReadFile('069_fill.dts')
- expected = 8 * chr(0xff) + 8 * chr(0)
+ expected = tools.GetBytes(0xff, 8) + tools.GetBytes(0, 8)
self.assertEqual(expected, data)
def testFillNoSize(self):
@@ -1357,7 +1463,7 @@
fname = pipe_list[0][-1]
# Append our GBB data to the file, which will happen every time the
# futility command is called.
- with open(fname, 'a') as fd:
+ with open(fname, 'ab') as fd:
fd.write(GBB_DATA)
return command.CommandResult()
@@ -1371,7 +1477,8 @@
data, _, _, _ = self._DoReadFileDtb('071_gbb.dts', entry_args=entry_args)
# Since futility
- expected = GBB_DATA + GBB_DATA + 8 * chr(0) + (0x2180 - 16) * chr(0)
+ expected = (GBB_DATA + GBB_DATA + tools.GetBytes(0, 8) +
+ tools.GetBytes(0, 0x2180 - 16))
self.assertEqual(expected, data)
def testGbbTooSmall(self):
@@ -1431,7 +1538,7 @@
def testTpl(self):
"""Test that an image with TPL and ots device tree can be created"""
# ELF file with a '__bss_size' symbol
- with open(self.TestFile('bss_data')) as fd:
+ with open(self.TestFile('bss_data'), 'rb') as fd:
TestFunctional._MakeInputFile('tpl/u-boot-tpl', fd.read())
data = self._DoReadFile('078_u_boot_tpl.dts')
self.assertEqual(U_BOOT_TPL_DATA + U_BOOT_TPL_DTB_DATA, data)
@@ -1446,7 +1553,7 @@
def testFillZero(self):
"""Test for an fill entry type with a size of 0"""
data = self._DoReadFile('080_fill_empty.dts')
- self.assertEqual(chr(0) * 16, data)
+ self.assertEqual(tools.GetBytes(0, 16), data)
def testTextMissing(self):
"""Test for a text entry type where there is no text"""
@@ -1465,7 +1572,7 @@
expected = 'Skipping images: image1'
# We should only get the expected message in verbose mode
- for verbosity in (None, 2):
+ for verbosity in (0, 2):
with test_util.capture_sys_output() as (stdout, stderr):
retcode = self._DoTestFile('006_dual_image.dts',
verbosity=verbosity,
@@ -1478,11 +1585,11 @@
self.assertFalse(os.path.exists(tools.GetOutputFilename('image1.bin')))
self.assertTrue(os.path.exists(tools.GetOutputFilename('image2.bin')))
+ self._CleanupOutputDir()
def testUpdateFdtAll(self):
"""Test that all device trees are updated with offset/size info"""
- data, _, _, _ = self._DoReadFileDtb('082_fdt_update_all.dts',
- use_real_dtb=True, update_dtb=True)
+ data = self._DoReadFileRealDtb('082_fdt_update_all.dts')
base_expected = {
'section:image-pos': 0,
@@ -1510,8 +1617,8 @@
for item in ['', 'spl', 'tpl']:
dtb = fdt.Fdt.FromData(data[start:])
dtb.Scan()
- props = self._GetPropTree(dtb, ['offset', 'size', 'image-pos',
- 'spl', 'tpl'])
+ props = self._GetPropTree(dtb, BASE_DTB_PROPS + REPACK_DTB_PROPS +
+ ['spl', 'tpl'])
expected = dict(base_expected)
if item:
expected[item] = 0
@@ -1554,19 +1661,11 @@
self._ResetDtbs()
def _decompress(self, data):
- out = os.path.join(self._indir, 'lz4.tmp')
- with open(out, 'wb') as fd:
- fd.write(data)
- return tools.Run('lz4', '-dc', out)
- '''
- try:
- orig = lz4.frame.decompress(data)
- except AttributeError:
- orig = lz4.decompress(data)
- '''
+ return tools.Decompress(data, 'lz4')
def testCompress(self):
"""Test compression of blobs"""
+ self._CheckLz4()
data, _, _, out_dtb_fname = self._DoReadFileDtb('083_compress.dts',
use_real_dtb=True, update_dtb=True)
dtb = fdt.Fdt(out_dtb_fname)
@@ -1588,14 +1687,15 @@
def testFilesCompress(self):
"""Test bringing in multiple files and compressing them"""
+ self._CheckLz4()
data = self._DoReadFile('085_files_compress.dts')
image = control.images['image']
entries = image.GetEntries()
files = entries['files']
- entries = files._section._entries
+ entries = files._entries
- orig = ''
+ orig = b''
for i in range(1, 3):
key = '%d.dat' % i
start = entries[key].image_pos
@@ -1623,10 +1723,10 @@
"""Test an expanding entry"""
data, _, map_data, _ = self._DoReadFileDtb('088_expand_size.dts',
map=True)
- expect = ('a' * 8 + U_BOOT_DATA +
- MRC_DATA + 'b' * 1 + U_BOOT_DATA +
- 'c' * 8 + U_BOOT_DATA +
- 'd' * 8)
+ expect = (tools.GetBytes(ord('a'), 8) + U_BOOT_DATA +
+ MRC_DATA + tools.GetBytes(ord('b'), 1) + U_BOOT_DATA +
+ tools.GetBytes(ord('c'), 8) + U_BOOT_DATA +
+ tools.GetBytes(ord('d'), 8))
self.assertEqual(expect, data)
self.assertEqual('''ImagePos Offset Size Name
00000000 00000000 00000028 main-section
@@ -1658,7 +1758,7 @@
hash_node = dtb.GetNode('/binman/u-boot/hash').props['value']
m = hashlib.sha256()
m.update(U_BOOT_DATA)
- self.assertEqual(m.digest(), ''.join(hash_node.value))
+ self.assertEqual(m.digest(), b''.join(hash_node.value))
def testHashNoAlgo(self):
with self.assertRaises(ValueError) as e:
@@ -1681,8 +1781,8 @@
hash_node = dtb.GetNode('/binman/section/hash').props['value']
m = hashlib.sha256()
m.update(U_BOOT_DATA)
- m.update(16 * 'a')
- self.assertEqual(m.digest(), ''.join(hash_node.value))
+ m.update(tools.GetBytes(ord('a'), 16))
+ self.assertEqual(m.digest(), b''.join(hash_node.value))
def testPackUBootTplMicrocode(self):
"""Test that x86 microcode can be handled correctly in TPL
@@ -1693,18 +1793,18 @@
u-boot-tpl.dtb with the microcode removed
the microcode
"""
- with open(self.TestFile('u_boot_ucode_ptr')) as fd:
+ with open(self.TestFile('u_boot_ucode_ptr'), 'rb') as fd:
TestFunctional._MakeInputFile('tpl/u-boot-tpl', fd.read())
first, pos_and_size = self._RunMicrocodeTest('093_x86_tpl_ucode.dts',
U_BOOT_TPL_NODTB_DATA)
- self.assertEqual('tplnodtb with microc' + pos_and_size +
- 'ter somewhere in here', first)
+ self.assertEqual(b'tplnodtb with microc' + pos_and_size +
+ b'ter somewhere in here', first)
def testFmapX86(self):
"""Basic test of generation of a flashrom fmap"""
data = self._DoReadFile('094_fmap_x86.dts')
fhdr, fentries = fmap_util.DecodeFmap(data[32:])
- expected = U_BOOT_DATA + MRC_DATA + 'a' * (32 - 7)
+ expected = U_BOOT_DATA + MRC_DATA + tools.GetBytes(ord('a'), 32 - 7)
self.assertEqual(expected, data[:32])
fhdr, fentries = fmap_util.DecodeFmap(data[32:])
@@ -1712,21 +1812,21 @@
self.assertEqual(0, fentries[0].offset)
self.assertEqual(4, fentries[0].size)
- self.assertEqual('U_BOOT', fentries[0].name)
+ self.assertEqual(b'U_BOOT', fentries[0].name)
self.assertEqual(4, fentries[1].offset)
self.assertEqual(3, fentries[1].size)
- self.assertEqual('INTEL_MRC', fentries[1].name)
+ self.assertEqual(b'INTEL_MRC', fentries[1].name)
self.assertEqual(32, fentries[2].offset)
self.assertEqual(fmap_util.FMAP_HEADER_LEN +
fmap_util.FMAP_AREA_LEN * 3, fentries[2].size)
- self.assertEqual('FMAP', fentries[2].name)
+ self.assertEqual(b'FMAP', fentries[2].name)
def testFmapX86Section(self):
"""Basic test of generation of a flashrom fmap"""
data = self._DoReadFile('095_fmap_x86_section.dts')
- expected = U_BOOT_DATA + MRC_DATA + 'b' * (32 - 7)
+ expected = U_BOOT_DATA + MRC_DATA + tools.GetBytes(ord('b'), 32 - 7)
self.assertEqual(expected, data[:32])
fhdr, fentries = fmap_util.DecodeFmap(data[36:])
@@ -1734,28 +1834,30 @@
self.assertEqual(0, fentries[0].offset)
self.assertEqual(4, fentries[0].size)
- self.assertEqual('U_BOOT', fentries[0].name)
+ self.assertEqual(b'U_BOOT', fentries[0].name)
self.assertEqual(4, fentries[1].offset)
self.assertEqual(3, fentries[1].size)
- self.assertEqual('INTEL_MRC', fentries[1].name)
+ self.assertEqual(b'INTEL_MRC', fentries[1].name)
self.assertEqual(36, fentries[2].offset)
self.assertEqual(fmap_util.FMAP_HEADER_LEN +
fmap_util.FMAP_AREA_LEN * 3, fentries[2].size)
- self.assertEqual('FMAP', fentries[2].name)
+ self.assertEqual(b'FMAP', fentries[2].name)
def testElf(self):
"""Basic test of ELF entries"""
self._SetupSplElf()
- with open(self.TestFile('bss_data')) as fd:
+ with open(self.TestFile('bss_data'), 'rb') as fd:
+ TestFunctional._MakeInputFile('tpl/u-boot-tpl', fd.read())
+ with open(self.TestFile('bss_data'), 'rb') as fd:
TestFunctional._MakeInputFile('-boot', fd.read())
data = self._DoReadFile('096_elf.dts')
- def testElfStripg(self):
+ def testElfStrip(self):
"""Basic test of ELF entries"""
self._SetupSplElf()
- with open(self.TestFile('bss_data')) as fd:
+ with open(self.TestFile('bss_data'), 'rb') as fd:
TestFunctional._MakeInputFile('-boot', fd.read())
data = self._DoReadFile('097_elf_strip.dts')
@@ -1771,14 +1873,14 @@
# We should not get an inmage, but there should be a map file
self.assertFalse(os.path.exists(tools.GetOutputFilename('image.bin')))
self.assertTrue(os.path.exists(map_fname))
- map_data = tools.ReadFile(map_fname)
+ map_data = tools.ReadFile(map_fname, binary=False)
self.assertEqual('''ImagePos Offset Size Name
<none> 00000000 00000007 main-section
<none> 00000000 00000004 u-boot
<none> 00000003 00000004 u-boot-align
''', map_data)
- def testPacRefCode(self):
+ def testPackRefCode(self):
"""Test that an image with an Intel Reference code binary works"""
data = self._DoReadFile('100_intel_refcode.dts')
self.assertEqual(REFCODE_DATA, data[:len(REFCODE_DATA)])
@@ -1797,9 +1899,1342 @@
0000002c 00000000 00000004 u-boot
''', map_data)
self.assertEqual(data,
- 4 * chr(0x26) + U_BOOT_DATA + 12 * chr(0x21) +
- 4 * chr(0x26) + U_BOOT_DATA + 12 * chr(0x61) +
- 4 * chr(0x26) + U_BOOT_DATA + 8 * chr(0x26))
+ tools.GetBytes(0x26, 4) + U_BOOT_DATA +
+ tools.GetBytes(0x21, 12) +
+ tools.GetBytes(0x26, 4) + U_BOOT_DATA +
+ tools.GetBytes(0x61, 12) +
+ tools.GetBytes(0x26, 4) + U_BOOT_DATA +
+ tools.GetBytes(0x26, 8))
+
+ def testCbfsRaw(self):
+ """Test base handling of a Coreboot Filesystem (CBFS)
+
+ The exact contents of the CBFS is verified by similar tests in
+ cbfs_util_test.py. The tests here merely check that the files added to
+ the CBFS can be found in the final image.
+ """
+ data = self._DoReadFile('102_cbfs_raw.dts')
+ size = 0xb0
+
+ cbfs = cbfs_util.CbfsReader(data)
+ self.assertEqual(size, cbfs.rom_size)
+
+ self.assertIn('u-boot-dtb', cbfs.files)
+ cfile = cbfs.files['u-boot-dtb']
+ self.assertEqual(U_BOOT_DTB_DATA, cfile.data)
+
+ def testCbfsArch(self):
+ """Test on non-x86 architecture"""
+ data = self._DoReadFile('103_cbfs_raw_ppc.dts')
+ size = 0x100
+
+ cbfs = cbfs_util.CbfsReader(data)
+ self.assertEqual(size, cbfs.rom_size)
+
+ self.assertIn('u-boot-dtb', cbfs.files)
+ cfile = cbfs.files['u-boot-dtb']
+ self.assertEqual(U_BOOT_DTB_DATA, cfile.data)
+
+ def testCbfsStage(self):
+ """Tests handling of a Coreboot Filesystem (CBFS)"""
+ if not elf.ELF_TOOLS:
+ self.skipTest('Python elftools not available')
+ elf_fname = os.path.join(self._indir, 'cbfs-stage.elf')
+ elf.MakeElf(elf_fname, U_BOOT_DATA, U_BOOT_DTB_DATA)
+ size = 0xb0
+
+ data = self._DoReadFile('104_cbfs_stage.dts')
+ cbfs = cbfs_util.CbfsReader(data)
+ self.assertEqual(size, cbfs.rom_size)
+
+ self.assertIn('u-boot', cbfs.files)
+ cfile = cbfs.files['u-boot']
+ self.assertEqual(U_BOOT_DATA + U_BOOT_DTB_DATA, cfile.data)
+
+ def testCbfsRawCompress(self):
+ """Test handling of compressing raw files"""
+ self._CheckLz4()
+ data = self._DoReadFile('105_cbfs_raw_compress.dts')
+ size = 0x140
+
+ cbfs = cbfs_util.CbfsReader(data)
+ self.assertIn('u-boot', cbfs.files)
+ cfile = cbfs.files['u-boot']
+ self.assertEqual(COMPRESS_DATA, cfile.data)
+
+ def testCbfsBadArch(self):
+ """Test handling of a bad architecture"""
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFile('106_cbfs_bad_arch.dts')
+ self.assertIn("Invalid architecture 'bad-arch'", str(e.exception))
+
+ def testCbfsNoSize(self):
+ """Test handling of a missing size property"""
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFile('107_cbfs_no_size.dts')
+ self.assertIn('entry must have a size property', str(e.exception))
+
+ def testCbfsNoCOntents(self):
+ """Test handling of a CBFS entry which does not provide contentsy"""
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFile('108_cbfs_no_contents.dts')
+ self.assertIn('Could not complete processing of contents',
+ str(e.exception))
+
+ def testCbfsBadCompress(self):
+ """Test handling of a bad architecture"""
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFile('109_cbfs_bad_compress.dts')
+ self.assertIn("Invalid compression in 'u-boot': 'invalid-algo'",
+ str(e.exception))
+
+ def testCbfsNamedEntries(self):
+ """Test handling of named entries"""
+ data = self._DoReadFile('110_cbfs_name.dts')
+
+ cbfs = cbfs_util.CbfsReader(data)
+ self.assertIn('FRED', cbfs.files)
+ cfile1 = cbfs.files['FRED']
+ self.assertEqual(U_BOOT_DATA, cfile1.data)
+
+ self.assertIn('hello', cbfs.files)
+ cfile2 = cbfs.files['hello']
+ self.assertEqual(U_BOOT_DTB_DATA, cfile2.data)
+
+ def _SetupIfwi(self, fname):
+ """Set up to run an IFWI test
+
+ Args:
+ fname: Filename of input file to provide (fitimage.bin or ifwi.bin)
+ """
+ self._SetupSplElf()
+
+ # Intel Integrated Firmware Image (IFWI) file
+ with gzip.open(self.TestFile('%s.gz' % fname), 'rb') as fd:
+ data = fd.read()
+ TestFunctional._MakeInputFile(fname,data)
+
+ def _CheckIfwi(self, data):
+ """Check that an image with an IFWI contains the correct output
+
+ Args:
+ data: Conents of output file
+ """
+ expected_desc = tools.ReadFile(self.TestFile('descriptor.bin'))
+ if data[:0x1000] != expected_desc:
+ self.fail('Expected descriptor binary at start of image')
+
+ # We expect to find the TPL wil in subpart IBBP entry IBBL
+ image_fname = tools.GetOutputFilename('image.bin')
+ tpl_fname = tools.GetOutputFilename('tpl.out')
+ tools.RunIfwiTool(image_fname, tools.CMD_EXTRACT, fname=tpl_fname,
+ subpart='IBBP', entry_name='IBBL')
+
+ tpl_data = tools.ReadFile(tpl_fname)
+ self.assertEqual(tpl_data[:len(U_BOOT_TPL_DATA)], U_BOOT_TPL_DATA)
+
+ def testPackX86RomIfwi(self):
+ """Test that an x86 ROM with Integrated Firmware Image can be created"""
+ self._SetupIfwi('fitimage.bin')
+ data = self._DoReadFile('111_x86-rom-ifwi.dts')
+ self._CheckIfwi(data)
+
+ def testPackX86RomIfwiNoDesc(self):
+ """Test that an x86 ROM with IFWI can be created from an ifwi.bin file"""
+ self._SetupIfwi('ifwi.bin')
+ data = self._DoReadFile('112_x86-rom-ifwi-nodesc.dts')
+ self._CheckIfwi(data)
+
+ def testPackX86RomIfwiNoData(self):
+ """Test that an x86 ROM with IFWI handles missing data"""
+ self._SetupIfwi('ifwi.bin')
+ with self.assertRaises(ValueError) as e:
+ data = self._DoReadFile('113_x86-rom-ifwi-nodata.dts')
+ self.assertIn('Could not complete processing of contents',
+ str(e.exception))
+
+ def testCbfsOffset(self):
+ """Test a CBFS with files at particular offsets
+
+ Like all CFBS tests, this is just checking the logic that calls
+ cbfs_util. See cbfs_util_test for fully tests (e.g. test_cbfs_offset()).
+ """
+ data = self._DoReadFile('114_cbfs_offset.dts')
+ size = 0x200
+
+ cbfs = cbfs_util.CbfsReader(data)
+ self.assertEqual(size, cbfs.rom_size)
+
+ self.assertIn('u-boot', cbfs.files)
+ cfile = cbfs.files['u-boot']
+ self.assertEqual(U_BOOT_DATA, cfile.data)
+ self.assertEqual(0x40, cfile.cbfs_offset)
+
+ self.assertIn('u-boot-dtb', cbfs.files)
+ cfile2 = cbfs.files['u-boot-dtb']
+ self.assertEqual(U_BOOT_DTB_DATA, cfile2.data)
+ self.assertEqual(0x140, cfile2.cbfs_offset)
+
+ def testFdtmap(self):
+ """Test an FDT map can be inserted in the image"""
+ data = self.data = self._DoReadFileRealDtb('115_fdtmap.dts')
+ fdtmap_data = data[len(U_BOOT_DATA):]
+ magic = fdtmap_data[:8]
+ self.assertEqual('_FDTMAP_', magic)
+ self.assertEqual(tools.GetBytes(0, 8), fdtmap_data[8:16])
+
+ fdt_data = fdtmap_data[16:]
+ dtb = fdt.Fdt.FromData(fdt_data)
+ dtb.Scan()
+ props = self._GetPropTree(dtb, BASE_DTB_PROPS, prefix='/')
+ self.assertEqual({
+ 'image-pos': 0,
+ 'offset': 0,
+ 'u-boot:offset': 0,
+ 'u-boot:size': len(U_BOOT_DATA),
+ 'u-boot:image-pos': 0,
+ 'fdtmap:image-pos': 4,
+ 'fdtmap:offset': 4,
+ 'fdtmap:size': len(fdtmap_data),
+ 'size': len(data),
+ }, props)
+
+ def testFdtmapNoMatch(self):
+ """Check handling of an FDT map when the section cannot be found"""
+ self.data = self._DoReadFileRealDtb('115_fdtmap.dts')
+
+ # Mangle the section name, which should cause a mismatch between the
+ # correct FDT path and the one expected by the section
+ image = control.images['image']
+ image._node.path += '-suffix'
+ entries = image.GetEntries()
+ fdtmap = entries['fdtmap']
+ with self.assertRaises(ValueError) as e:
+ fdtmap._GetFdtmap()
+ self.assertIn("Cannot locate node for path '/binman-suffix'",
+ str(e.exception))
+
+ def testFdtmapHeader(self):
+ """Test an FDT map and image header can be inserted in the image"""
+ data = self.data = self._DoReadFileRealDtb('116_fdtmap_hdr.dts')
+ fdtmap_pos = len(U_BOOT_DATA)
+ fdtmap_data = data[fdtmap_pos:]
+ fdt_data = fdtmap_data[16:]
+ dtb = fdt.Fdt.FromData(fdt_data)
+ fdt_size = dtb.GetFdtObj().totalsize()
+ hdr_data = data[-8:]
+ self.assertEqual('BinM', hdr_data[:4])
+ offset = struct.unpack('<I', hdr_data[4:])[0] & 0xffffffff
+ self.assertEqual(fdtmap_pos - 0x400, offset - (1 << 32))
+
+ def testFdtmapHeaderStart(self):
+ """Test an image header can be inserted at the image start"""
+ data = self.data = self._DoReadFileRealDtb('117_fdtmap_hdr_start.dts')
+ fdtmap_pos = 0x100 + len(U_BOOT_DATA)
+ hdr_data = data[:8]
+ self.assertEqual('BinM', hdr_data[:4])
+ offset = struct.unpack('<I', hdr_data[4:])[0]
+ self.assertEqual(fdtmap_pos, offset)
+
+ def testFdtmapHeaderPos(self):
+ """Test an image header can be inserted at a chosen position"""
+ data = self.data = self._DoReadFileRealDtb('118_fdtmap_hdr_pos.dts')
+ fdtmap_pos = 0x100 + len(U_BOOT_DATA)
+ hdr_data = data[0x80:0x88]
+ self.assertEqual('BinM', hdr_data[:4])
+ offset = struct.unpack('<I', hdr_data[4:])[0]
+ self.assertEqual(fdtmap_pos, offset)
+
+ def testHeaderMissingFdtmap(self):
+ """Test an image header requires an fdtmap"""
+ with self.assertRaises(ValueError) as e:
+ self.data = self._DoReadFileRealDtb('119_fdtmap_hdr_missing.dts')
+ self.assertIn("'image_header' section must have an 'fdtmap' sibling",
+ str(e.exception))
+
+ def testHeaderNoLocation(self):
+ """Test an image header with a no specified location is detected"""
+ with self.assertRaises(ValueError) as e:
+ self.data = self._DoReadFileRealDtb('120_hdr_no_location.dts')
+ self.assertIn("Invalid location 'None', expected 'start' or 'end'",
+ str(e.exception))
+
+ def testEntryExpand(self):
+ """Test expanding an entry after it is packed"""
+ data = self._DoReadFile('121_entry_expand.dts')
+ self.assertEqual(b'aaa', data[:3])
+ self.assertEqual(U_BOOT_DATA, data[3:3 + len(U_BOOT_DATA)])
+ self.assertEqual(b'aaa', data[-3:])
+
+ def testEntryExpandBad(self):
+ """Test expanding an entry after it is packed, twice"""
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFile('122_entry_expand_twice.dts')
+ self.assertIn("Image '/binman': Entries changed size after packing",
+ str(e.exception))
+
+ def testEntryExpandSection(self):
+ """Test expanding an entry within a section after it is packed"""
+ data = self._DoReadFile('123_entry_expand_section.dts')
+ self.assertEqual(b'aaa', data[:3])
+ self.assertEqual(U_BOOT_DATA, data[3:3 + len(U_BOOT_DATA)])
+ self.assertEqual(b'aaa', data[-3:])
+
+ def testCompressDtb(self):
+ """Test that compress of device-tree files is supported"""
+ self._CheckLz4()
+ data = self.data = self._DoReadFileRealDtb('124_compress_dtb.dts')
+ self.assertEqual(U_BOOT_DATA, data[:len(U_BOOT_DATA)])
+ comp_data = data[len(U_BOOT_DATA):]
+ orig = self._decompress(comp_data)
+ dtb = fdt.Fdt.FromData(orig)
+ dtb.Scan()
+ props = self._GetPropTree(dtb, ['size', 'uncomp-size'])
+ expected = {
+ 'u-boot:size': len(U_BOOT_DATA),
+ 'u-boot-dtb:uncomp-size': len(orig),
+ 'u-boot-dtb:size': len(comp_data),
+ 'size': len(data),
+ }
+ self.assertEqual(expected, props)
+
+ def testCbfsUpdateFdt(self):
+ """Test that we can update the device tree with CBFS offset/size info"""
+ self._CheckLz4()
+ data, _, _, out_dtb_fname = self._DoReadFileDtb('125_cbfs_update.dts',
+ update_dtb=True)
+ dtb = fdt.Fdt(out_dtb_fname)
+ dtb.Scan()
+ props = self._GetPropTree(dtb, BASE_DTB_PROPS + ['uncomp-size'])
+ del props['cbfs/u-boot:size']
+ self.assertEqual({
+ 'offset': 0,
+ 'size': len(data),
+ 'image-pos': 0,
+ 'cbfs:offset': 0,
+ 'cbfs:size': len(data),
+ 'cbfs:image-pos': 0,
+ 'cbfs/u-boot:offset': 0x38,
+ 'cbfs/u-boot:uncomp-size': len(U_BOOT_DATA),
+ 'cbfs/u-boot:image-pos': 0x38,
+ 'cbfs/u-boot-dtb:offset': 0xb8,
+ 'cbfs/u-boot-dtb:size': len(U_BOOT_DATA),
+ 'cbfs/u-boot-dtb:image-pos': 0xb8,
+ }, props)
+
+ def testCbfsBadType(self):
+ """Test an image header with a no specified location is detected"""
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFile('126_cbfs_bad_type.dts')
+ self.assertIn("Unknown cbfs-type 'badtype'", str(e.exception))
+
+ def testList(self):
+ """Test listing the files in an image"""
+ self._CheckLz4()
+ data = self._DoReadFile('127_list.dts')
+ image = control.images['image']
+ entries = image.BuildEntryList()
+ self.assertEqual(7, len(entries))
+
+ ent = entries[0]
+ self.assertEqual(0, ent.indent)
+ self.assertEqual('main-section', ent.name)
+ self.assertEqual('section', ent.etype)
+ self.assertEqual(len(data), ent.size)
+ self.assertEqual(0, ent.image_pos)
+ self.assertEqual(None, ent.uncomp_size)
+ self.assertEqual(0, ent.offset)
+
+ ent = entries[1]
+ self.assertEqual(1, ent.indent)
+ self.assertEqual('u-boot', ent.name)
+ self.assertEqual('u-boot', ent.etype)
+ self.assertEqual(len(U_BOOT_DATA), ent.size)
+ self.assertEqual(0, ent.image_pos)
+ self.assertEqual(None, ent.uncomp_size)
+ self.assertEqual(0, ent.offset)
+
+ ent = entries[2]
+ self.assertEqual(1, ent.indent)
+ self.assertEqual('section', ent.name)
+ self.assertEqual('section', ent.etype)
+ section_size = ent.size
+ self.assertEqual(0x100, ent.image_pos)
+ self.assertEqual(None, ent.uncomp_size)
+ self.assertEqual(0x100, ent.offset)
+
+ ent = entries[3]
+ self.assertEqual(2, ent.indent)
+ self.assertEqual('cbfs', ent.name)
+ self.assertEqual('cbfs', ent.etype)
+ self.assertEqual(0x400, ent.size)
+ self.assertEqual(0x100, ent.image_pos)
+ self.assertEqual(None, ent.uncomp_size)
+ self.assertEqual(0, ent.offset)
+
+ ent = entries[4]
+ self.assertEqual(3, ent.indent)
+ self.assertEqual('u-boot', ent.name)
+ self.assertEqual('u-boot', ent.etype)
+ self.assertEqual(len(U_BOOT_DATA), ent.size)
+ self.assertEqual(0x138, ent.image_pos)
+ self.assertEqual(None, ent.uncomp_size)
+ self.assertEqual(0x38, ent.offset)
+
+ ent = entries[5]
+ self.assertEqual(3, ent.indent)
+ self.assertEqual('u-boot-dtb', ent.name)
+ self.assertEqual('text', ent.etype)
+ self.assertGreater(len(COMPRESS_DATA), ent.size)
+ self.assertEqual(0x178, ent.image_pos)
+ self.assertEqual(len(COMPRESS_DATA), ent.uncomp_size)
+ self.assertEqual(0x78, ent.offset)
+
+ ent = entries[6]
+ self.assertEqual(2, ent.indent)
+ self.assertEqual('u-boot-dtb', ent.name)
+ self.assertEqual('u-boot-dtb', ent.etype)
+ self.assertEqual(0x500, ent.image_pos)
+ self.assertEqual(len(U_BOOT_DTB_DATA), ent.uncomp_size)
+ dtb_size = ent.size
+ # Compressing this data expands it since headers are added
+ self.assertGreater(dtb_size, len(U_BOOT_DTB_DATA))
+ self.assertEqual(0x400, ent.offset)
+
+ self.assertEqual(len(data), 0x100 + section_size)
+ self.assertEqual(section_size, 0x400 + dtb_size)
+
+ def testFindFdtmap(self):
+ """Test locating an FDT map in an image"""
+ self._CheckLz4()
+ data = self.data = self._DoReadFileRealDtb('128_decode_image.dts')
+ image = control.images['image']
+ entries = image.GetEntries()
+ entry = entries['fdtmap']
+ self.assertEqual(entry.image_pos, fdtmap.LocateFdtmap(data))
+
+ def testFindFdtmapMissing(self):
+ """Test failing to locate an FDP map"""
+ data = self._DoReadFile('005_simple.dts')
+ self.assertEqual(None, fdtmap.LocateFdtmap(data))
+
+ def testFindImageHeader(self):
+ """Test locating a image header"""
+ self._CheckLz4()
+ data = self.data = self._DoReadFileRealDtb('128_decode_image.dts')
+ image = control.images['image']
+ entries = image.GetEntries()
+ entry = entries['fdtmap']
+ # The header should point to the FDT map
+ self.assertEqual(entry.image_pos, image_header.LocateHeaderOffset(data))
+
+ def testFindImageHeaderStart(self):
+ """Test locating a image header located at the start of an image"""
+ data = self.data = self._DoReadFileRealDtb('117_fdtmap_hdr_start.dts')
+ image = control.images['image']
+ entries = image.GetEntries()
+ entry = entries['fdtmap']
+ # The header should point to the FDT map
+ self.assertEqual(entry.image_pos, image_header.LocateHeaderOffset(data))
+
+ def testFindImageHeaderMissing(self):
+ """Test failing to locate an image header"""
+ data = self._DoReadFile('005_simple.dts')
+ self.assertEqual(None, image_header.LocateHeaderOffset(data))
+
+ def testReadImage(self):
+ """Test reading an image and accessing its FDT map"""
+ self._CheckLz4()
+ data = self.data = self._DoReadFileRealDtb('128_decode_image.dts')
+ image_fname = tools.GetOutputFilename('image.bin')
+ orig_image = control.images['image']
+ image = Image.FromFile(image_fname)
+ self.assertEqual(orig_image.GetEntries().keys(),
+ image.GetEntries().keys())
+
+ orig_entry = orig_image.GetEntries()['fdtmap']
+ entry = image.GetEntries()['fdtmap']
+ self.assertEquals(orig_entry.offset, entry.offset)
+ self.assertEquals(orig_entry.size, entry.size)
+ self.assertEquals(orig_entry.image_pos, entry.image_pos)
+
+ def testReadImageNoHeader(self):
+ """Test accessing an image's FDT map without an image header"""
+ self._CheckLz4()
+ data = self._DoReadFileRealDtb('129_decode_image_nohdr.dts')
+ image_fname = tools.GetOutputFilename('image.bin')
+ image = Image.FromFile(image_fname)
+ self.assertTrue(isinstance(image, Image))
+ self.assertEqual('image', image.image_name[-5:])
+
+ def testReadImageFail(self):
+ """Test failing to read an image image's FDT map"""
+ self._DoReadFile('005_simple.dts')
+ image_fname = tools.GetOutputFilename('image.bin')
+ with self.assertRaises(ValueError) as e:
+ image = Image.FromFile(image_fname)
+ self.assertIn("Cannot find FDT map in image", str(e.exception))
+
+ def testListCmd(self):
+ """Test listing the files in an image using an Fdtmap"""
+ self._CheckLz4()
+ data = self._DoReadFileRealDtb('130_list_fdtmap.dts')
+
+ # lz4 compression size differs depending on the version
+ image = control.images['image']
+ entries = image.GetEntries()
+ section_size = entries['section'].size
+ fdt_size = entries['section'].GetEntries()['u-boot-dtb'].size
+ fdtmap_offset = entries['fdtmap'].offset
+
+ try:
+ tmpdir, updated_fname = self._SetupImageInTmpdir()
+ with test_util.capture_sys_output() as (stdout, stderr):
+ self._DoBinman('ls', '-i', updated_fname)
+ finally:
+ shutil.rmtree(tmpdir)
+ lines = stdout.getvalue().splitlines()
+ expected = [
+'Name Image-pos Size Entry-type Offset Uncomp-size',
+'----------------------------------------------------------------------',
+'main-section 0 c00 section 0',
+' u-boot 0 4 u-boot 0',
+' section 100 %x section 100' % section_size,
+' cbfs 100 400 cbfs 0',
+' u-boot 138 4 u-boot 38',
+' u-boot-dtb 180 10f u-boot-dtb 80 3c9',
+' u-boot-dtb 500 %x u-boot-dtb 400 3c9' % fdt_size,
+' fdtmap %x 3b4 fdtmap %x' %
+ (fdtmap_offset, fdtmap_offset),
+' image-header bf8 8 image-header bf8',
+ ]
+ self.assertEqual(expected, lines)
+
+ def testListCmdFail(self):
+ """Test failing to list an image"""
+ self._DoReadFile('005_simple.dts')
+ try:
+ tmpdir, updated_fname = self._SetupImageInTmpdir()
+ with self.assertRaises(ValueError) as e:
+ self._DoBinman('ls', '-i', updated_fname)
+ finally:
+ shutil.rmtree(tmpdir)
+ self.assertIn("Cannot find FDT map in image", str(e.exception))
+
+ def _RunListCmd(self, paths, expected):
+ """List out entries and check the result
+
+ Args:
+ paths: List of paths to pass to the list command
+ expected: Expected list of filenames to be returned, in order
+ """
+ self._CheckLz4()
+ self._DoReadFileRealDtb('130_list_fdtmap.dts')
+ image_fname = tools.GetOutputFilename('image.bin')
+ image = Image.FromFile(image_fname)
+ lines = image.GetListEntries(paths)[1]
+ files = [line[0].strip() for line in lines[1:]]
+ self.assertEqual(expected, files)
+
+ def testListCmdSection(self):
+ """Test listing the files in a section"""
+ self._RunListCmd(['section'],
+ ['section', 'cbfs', 'u-boot', 'u-boot-dtb', 'u-boot-dtb'])
+
+ def testListCmdFile(self):
+ """Test listing a particular file"""
+ self._RunListCmd(['*u-boot-dtb'], ['u-boot-dtb', 'u-boot-dtb'])
+
+ def testListCmdWildcard(self):
+ """Test listing a wildcarded file"""
+ self._RunListCmd(['*boot*'],
+ ['u-boot', 'u-boot', 'u-boot-dtb', 'u-boot-dtb'])
+
+ def testListCmdWildcardMulti(self):
+ """Test listing a wildcarded file"""
+ self._RunListCmd(['*cb*', '*head*'],
+ ['cbfs', 'u-boot', 'u-boot-dtb', 'image-header'])
+
+ def testListCmdEmpty(self):
+ """Test listing a wildcarded file"""
+ self._RunListCmd(['nothing'], [])
+
+ def testListCmdPath(self):
+ """Test listing the files in a sub-entry of a section"""
+ self._RunListCmd(['section/cbfs'], ['cbfs', 'u-boot', 'u-boot-dtb'])
+
+ def _RunExtractCmd(self, entry_name, decomp=True):
+ """Extract an entry from an image
+
+ Args:
+ entry_name: Entry name to extract
+ decomp: True to decompress the data if compressed, False to leave
+ it in its raw uncompressed format
+
+ Returns:
+ data from entry
+ """
+ self._CheckLz4()
+ self._DoReadFileRealDtb('130_list_fdtmap.dts')
+ image_fname = tools.GetOutputFilename('image.bin')
+ return control.ReadEntry(image_fname, entry_name, decomp)
+
+ def testExtractSimple(self):
+ """Test extracting a single file"""
+ data = self._RunExtractCmd('u-boot')
+ self.assertEqual(U_BOOT_DATA, data)
+
+ def testExtractSection(self):
+ """Test extracting the files in a section"""
+ data = self._RunExtractCmd('section')
+ cbfs_data = data[:0x400]
+ cbfs = cbfs_util.CbfsReader(cbfs_data)
+ self.assertEqual(['u-boot', 'u-boot-dtb', ''], cbfs.files.keys())
+ dtb_data = data[0x400:]
+ dtb = self._decompress(dtb_data)
+ self.assertEqual(EXTRACT_DTB_SIZE, len(dtb))
+
+ def testExtractCompressed(self):
+ """Test extracting compressed data"""
+ data = self._RunExtractCmd('section/u-boot-dtb')
+ self.assertEqual(EXTRACT_DTB_SIZE, len(data))
+
+ def testExtractRaw(self):
+ """Test extracting compressed data without decompressing it"""
+ data = self._RunExtractCmd('section/u-boot-dtb', decomp=False)
+ dtb = self._decompress(data)
+ self.assertEqual(EXTRACT_DTB_SIZE, len(dtb))
+
+ def testExtractCbfs(self):
+ """Test extracting CBFS data"""
+ data = self._RunExtractCmd('section/cbfs/u-boot')
+ self.assertEqual(U_BOOT_DATA, data)
+
+ def testExtractCbfsCompressed(self):
+ """Test extracting CBFS compressed data"""
+ data = self._RunExtractCmd('section/cbfs/u-boot-dtb')
+ self.assertEqual(EXTRACT_DTB_SIZE, len(data))
+
+ def testExtractCbfsRaw(self):
+ """Test extracting CBFS compressed data without decompressing it"""
+ data = self._RunExtractCmd('section/cbfs/u-boot-dtb', decomp=False)
+ dtb = tools.Decompress(data, 'lzma', with_header=False)
+ self.assertEqual(EXTRACT_DTB_SIZE, len(dtb))
+
+ def testExtractBadEntry(self):
+ """Test extracting a bad section path"""
+ with self.assertRaises(ValueError) as e:
+ self._RunExtractCmd('section/does-not-exist')
+ self.assertIn("Entry 'does-not-exist' not found in '/section'",
+ str(e.exception))
+
+ def testExtractMissingFile(self):
+ """Test extracting file that does not exist"""
+ with self.assertRaises(IOError) as e:
+ control.ReadEntry('missing-file', 'name')
+
+ def testExtractBadFile(self):
+ """Test extracting an invalid file"""
+ fname = os.path.join(self._indir, 'badfile')
+ tools.WriteFile(fname, b'')
+ with self.assertRaises(ValueError) as e:
+ control.ReadEntry(fname, 'name')
+
+ def testExtractCmd(self):
+ """Test extracting a file fron an image on the command line"""
+ self._CheckLz4()
+ self._DoReadFileRealDtb('130_list_fdtmap.dts')
+ fname = os.path.join(self._indir, 'output.extact')
+ try:
+ tmpdir, updated_fname = self._SetupImageInTmpdir()
+ with test_util.capture_sys_output() as (stdout, stderr):
+ self._DoBinman('extract', '-i', updated_fname, 'u-boot',
+ '-f', fname)
+ finally:
+ shutil.rmtree(tmpdir)
+ data = tools.ReadFile(fname)
+ self.assertEqual(U_BOOT_DATA, data)
+
+ def testExtractOneEntry(self):
+ """Test extracting a single entry fron an image """
+ self._CheckLz4()
+ self._DoReadFileRealDtb('130_list_fdtmap.dts')
+ image_fname = tools.GetOutputFilename('image.bin')
+ fname = os.path.join(self._indir, 'output.extact')
+ control.ExtractEntries(image_fname, fname, None, ['u-boot'])
+ data = tools.ReadFile(fname)
+ self.assertEqual(U_BOOT_DATA, data)
+
+ def _CheckExtractOutput(self, decomp):
+ """Helper to test file output with and without decompression
+
+ Args:
+ decomp: True to decompress entry data, False to output it raw
+ """
+ def _CheckPresent(entry_path, expect_data, expect_size=None):
+ """Check and remove expected file
+
+ This checks the data/size of a file and removes the file both from
+ the outfiles set and from the output directory. Once all files are
+ processed, both the set and directory should be empty.
+
+ Args:
+ entry_path: Entry path
+ expect_data: Data to expect in file, or None to skip check
+ expect_size: Size of data to expect in file, or None to skip
+ """
+ path = os.path.join(outdir, entry_path)
+ data = tools.ReadFile(path)
+ os.remove(path)
+ if expect_data:
+ self.assertEqual(expect_data, data)
+ elif expect_size:
+ self.assertEqual(expect_size, len(data))
+ outfiles.remove(path)
+
+ def _CheckDirPresent(name):
+ """Remove expected directory
+
+ This gives an error if the directory does not exist as expected
+
+ Args:
+ name: Name of directory to remove
+ """
+ path = os.path.join(outdir, name)
+ os.rmdir(path)
+
+ self._DoReadFileRealDtb('130_list_fdtmap.dts')
+ image_fname = tools.GetOutputFilename('image.bin')
+ outdir = os.path.join(self._indir, 'extract')
+ einfos = control.ExtractEntries(image_fname, None, outdir, [], decomp)
+
+ # Create a set of all file that were output (should be 9)
+ outfiles = set()
+ for root, dirs, files in os.walk(outdir):
+ outfiles |= set([os.path.join(root, fname) for fname in files])
+ self.assertEqual(9, len(outfiles))
+ self.assertEqual(9, len(einfos))
+
+ image = control.images['image']
+ entries = image.GetEntries()
+
+ # Check the 9 files in various ways
+ section = entries['section']
+ section_entries = section.GetEntries()
+ cbfs_entries = section_entries['cbfs'].GetEntries()
+ _CheckPresent('u-boot', U_BOOT_DATA)
+ _CheckPresent('section/cbfs/u-boot', U_BOOT_DATA)
+ dtb_len = EXTRACT_DTB_SIZE
+ if not decomp:
+ dtb_len = cbfs_entries['u-boot-dtb'].size
+ _CheckPresent('section/cbfs/u-boot-dtb', None, dtb_len)
+ if not decomp:
+ dtb_len = section_entries['u-boot-dtb'].size
+ _CheckPresent('section/u-boot-dtb', None, dtb_len)
+
+ fdtmap = entries['fdtmap']
+ _CheckPresent('fdtmap', fdtmap.data)
+ hdr = entries['image-header']
+ _CheckPresent('image-header', hdr.data)
+
+ _CheckPresent('section/root', section.data)
+ cbfs = section_entries['cbfs']
+ _CheckPresent('section/cbfs/root', cbfs.data)
+ data = tools.ReadFile(image_fname)
+ _CheckPresent('root', data)
+
+ # There should be no files left. Remove all the directories to check.
+ # If there are any files/dirs remaining, one of these checks will fail.
+ self.assertEqual(0, len(outfiles))
+ _CheckDirPresent('section/cbfs')
+ _CheckDirPresent('section')
+ _CheckDirPresent('')
+ self.assertFalse(os.path.exists(outdir))
+
+ def testExtractAllEntries(self):
+ """Test extracting all entries"""
+ self._CheckLz4()
+ self._CheckExtractOutput(decomp=True)
+
+ def testExtractAllEntriesRaw(self):
+ """Test extracting all entries without decompressing them"""
+ self._CheckLz4()
+ self._CheckExtractOutput(decomp=False)
+
+ def testExtractSelectedEntries(self):
+ """Test extracting some entries"""
+ self._CheckLz4()
+ self._DoReadFileRealDtb('130_list_fdtmap.dts')
+ image_fname = tools.GetOutputFilename('image.bin')
+ outdir = os.path.join(self._indir, 'extract')
+ einfos = control.ExtractEntries(image_fname, None, outdir,
+ ['*cb*', '*head*'])
+
+ # File output is tested by testExtractAllEntries(), so just check that
+ # the expected entries are selected
+ names = [einfo.name for einfo in einfos]
+ self.assertEqual(names,
+ ['cbfs', 'u-boot', 'u-boot-dtb', 'image-header'])
+
+ def testExtractNoEntryPaths(self):
+ """Test extracting some entries"""
+ self._CheckLz4()
+ self._DoReadFileRealDtb('130_list_fdtmap.dts')
+ image_fname = tools.GetOutputFilename('image.bin')
+ with self.assertRaises(ValueError) as e:
+ control.ExtractEntries(image_fname, 'fname', None, [])
+ self.assertIn('Must specify an entry path to write with -f',
+ str(e.exception))
+
+ def testExtractTooManyEntryPaths(self):
+ """Test extracting some entries"""
+ self._CheckLz4()
+ self._DoReadFileRealDtb('130_list_fdtmap.dts')
+ image_fname = tools.GetOutputFilename('image.bin')
+ with self.assertRaises(ValueError) as e:
+ control.ExtractEntries(image_fname, 'fname', None, ['a', 'b'])
+ self.assertIn('Must specify exactly one entry path to write with -f',
+ str(e.exception))
+
+ def testPackAlignSection(self):
+ """Test that sections can have alignment"""
+ self._DoReadFile('131_pack_align_section.dts')
+
+ self.assertIn('image', control.images)
+ image = control.images['image']
+ entries = image.GetEntries()
+ self.assertEqual(3, len(entries))
+
+ # First u-boot
+ self.assertIn('u-boot', entries)
+ entry = entries['u-boot']
+ self.assertEqual(0, entry.offset)
+ self.assertEqual(0, entry.image_pos)
+ self.assertEqual(len(U_BOOT_DATA), entry.contents_size)
+ self.assertEqual(len(U_BOOT_DATA), entry.size)
+
+ # Section0
+ self.assertIn('section0', entries)
+ section0 = entries['section0']
+ self.assertEqual(0x10, section0.offset)
+ self.assertEqual(0x10, section0.image_pos)
+ self.assertEqual(len(U_BOOT_DATA), section0.size)
+
+ # Second u-boot
+ section_entries = section0.GetEntries()
+ self.assertIn('u-boot', section_entries)
+ entry = section_entries['u-boot']
+ self.assertEqual(0, entry.offset)
+ self.assertEqual(0x10, entry.image_pos)
+ self.assertEqual(len(U_BOOT_DATA), entry.contents_size)
+ self.assertEqual(len(U_BOOT_DATA), entry.size)
+
+ # Section1
+ self.assertIn('section1', entries)
+ section1 = entries['section1']
+ self.assertEqual(0x14, section1.offset)
+ self.assertEqual(0x14, section1.image_pos)
+ self.assertEqual(0x20, section1.size)
+
+ # Second u-boot
+ section_entries = section1.GetEntries()
+ self.assertIn('u-boot', section_entries)
+ entry = section_entries['u-boot']
+ self.assertEqual(0, entry.offset)
+ self.assertEqual(0x14, entry.image_pos)
+ self.assertEqual(len(U_BOOT_DATA), entry.contents_size)
+ self.assertEqual(len(U_BOOT_DATA), entry.size)
+
+ # Section2
+ self.assertIn('section2', section_entries)
+ section2 = section_entries['section2']
+ self.assertEqual(0x4, section2.offset)
+ self.assertEqual(0x18, section2.image_pos)
+ self.assertEqual(4, section2.size)
+
+ # Third u-boot
+ section_entries = section2.GetEntries()
+ self.assertIn('u-boot', section_entries)
+ entry = section_entries['u-boot']
+ self.assertEqual(0, entry.offset)
+ self.assertEqual(0x18, entry.image_pos)
+ self.assertEqual(len(U_BOOT_DATA), entry.contents_size)
+ self.assertEqual(len(U_BOOT_DATA), entry.size)
+
+ def _RunReplaceCmd(self, entry_name, data, decomp=True, allow_resize=True,
+ dts='132_replace.dts'):
+ """Replace an entry in an image
+
+ This writes the entry data to update it, then opens the updated file and
+ returns the value that it now finds there.
+
+ Args:
+ entry_name: Entry name to replace
+ data: Data to replace it with
+ decomp: True to compress the data if needed, False if data is
+ already compressed so should be used as is
+ allow_resize: True to allow entries to change size, False to raise
+ an exception
+
+ Returns:
+ Tuple:
+ data from entry
+ data from fdtmap (excluding header)
+ Image object that was modified
+ """
+ dtb_data = self._DoReadFileDtb(dts, use_real_dtb=True,
+ update_dtb=True)[1]
+
+ self.assertIn('image', control.images)
+ image = control.images['image']
+ entries = image.GetEntries()
+ orig_dtb_data = entries['u-boot-dtb'].data
+ orig_fdtmap_data = entries['fdtmap'].data
+
+ image_fname = tools.GetOutputFilename('image.bin')
+ updated_fname = tools.GetOutputFilename('image-updated.bin')
+ tools.WriteFile(updated_fname, tools.ReadFile(image_fname))
+ image = control.WriteEntry(updated_fname, entry_name, data, decomp,
+ allow_resize)
+ data = control.ReadEntry(updated_fname, entry_name, decomp)
+
+ # The DT data should not change unless resized:
+ if not allow_resize:
+ new_dtb_data = entries['u-boot-dtb'].data
+ self.assertEqual(new_dtb_data, orig_dtb_data)
+ new_fdtmap_data = entries['fdtmap'].data
+ self.assertEqual(new_fdtmap_data, orig_fdtmap_data)
+
+ return data, orig_fdtmap_data[fdtmap.FDTMAP_HDR_LEN:], image
+
+ def testReplaceSimple(self):
+ """Test replacing a single file"""
+ expected = b'x' * len(U_BOOT_DATA)
+ data, expected_fdtmap, _ = self._RunReplaceCmd('u-boot', expected,
+ allow_resize=False)
+ self.assertEqual(expected, data)
+
+ # Test that the state looks right. There should be an FDT for the fdtmap
+ # that we jsut read back in, and it should match what we find in the
+ # 'control' tables. Checking for an FDT that does not exist should
+ # return None.
+ path, fdtmap = state.GetFdtContents('fdtmap')
+ self.assertIsNotNone(path)
+ self.assertEqual(expected_fdtmap, fdtmap)
+
+ dtb = state.GetFdtForEtype('fdtmap')
+ self.assertEqual(dtb.GetContents(), fdtmap)
+
+ missing_path, missing_fdtmap = state.GetFdtContents('missing')
+ self.assertIsNone(missing_path)
+ self.assertIsNone(missing_fdtmap)
+
+ missing_dtb = state.GetFdtForEtype('missing')
+ self.assertIsNone(missing_dtb)
+
+ self.assertEqual('/binman', state.fdt_path_prefix)
+
+ def testReplaceResizeFail(self):
+ """Test replacing a file by something larger"""
+ expected = U_BOOT_DATA + b'x'
+ with self.assertRaises(ValueError) as e:
+ self._RunReplaceCmd('u-boot', expected, allow_resize=False,
+ dts='139_replace_repack.dts')
+ self.assertIn("Node '/u-boot': Entry data size does not match, but resize is disabled",
+ str(e.exception))
+
+ def testReplaceMulti(self):
+ """Test replacing entry data where multiple images are generated"""
+ data = self._DoReadFileDtb('133_replace_multi.dts', use_real_dtb=True,
+ update_dtb=True)[0]
+ expected = b'x' * len(U_BOOT_DATA)
+ updated_fname = tools.GetOutputFilename('image-updated.bin')
+ tools.WriteFile(updated_fname, data)
+ entry_name = 'u-boot'
+ control.WriteEntry(updated_fname, entry_name, expected,
+ allow_resize=False)
+ data = control.ReadEntry(updated_fname, entry_name)
+ self.assertEqual(expected, data)
+
+ # Check the state looks right.
+ self.assertEqual('/binman/image', state.fdt_path_prefix)
+
+ # Now check we can write the first image
+ image_fname = tools.GetOutputFilename('first-image.bin')
+ updated_fname = tools.GetOutputFilename('first-updated.bin')
+ tools.WriteFile(updated_fname, tools.ReadFile(image_fname))
+ entry_name = 'u-boot'
+ control.WriteEntry(updated_fname, entry_name, expected,
+ allow_resize=False)
+ data = control.ReadEntry(updated_fname, entry_name)
+ self.assertEqual(expected, data)
+
+ # Check the state looks right.
+ self.assertEqual('/binman/first-image', state.fdt_path_prefix)
+
+ def testUpdateFdtAllRepack(self):
+ """Test that all device trees are updated with offset/size info"""
+ data = self._DoReadFileRealDtb('134_fdt_update_all_repack.dts')
+ SECTION_SIZE = 0x300
+ DTB_SIZE = 602
+ FDTMAP_SIZE = 608
+ base_expected = {
+ 'offset': 0,
+ 'size': SECTION_SIZE + DTB_SIZE * 2 + FDTMAP_SIZE,
+ 'image-pos': 0,
+ 'section:offset': 0,
+ 'section:size': SECTION_SIZE,
+ 'section:image-pos': 0,
+ 'section/u-boot-dtb:offset': 4,
+ 'section/u-boot-dtb:size': 636,
+ 'section/u-boot-dtb:image-pos': 4,
+ 'u-boot-spl-dtb:offset': SECTION_SIZE,
+ 'u-boot-spl-dtb:size': DTB_SIZE,
+ 'u-boot-spl-dtb:image-pos': SECTION_SIZE,
+ 'u-boot-tpl-dtb:offset': SECTION_SIZE + DTB_SIZE,
+ 'u-boot-tpl-dtb:image-pos': SECTION_SIZE + DTB_SIZE,
+ 'u-boot-tpl-dtb:size': DTB_SIZE,
+ 'fdtmap:offset': SECTION_SIZE + DTB_SIZE * 2,
+ 'fdtmap:size': FDTMAP_SIZE,
+ 'fdtmap:image-pos': SECTION_SIZE + DTB_SIZE * 2,
+ }
+ main_expected = {
+ 'section:orig-size': SECTION_SIZE,
+ 'section/u-boot-dtb:orig-offset': 4,
+ }
+
+ # We expect three device-tree files in the output, with the first one
+ # within a fixed-size section.
+ # Read them in sequence. We look for an 'spl' property in the SPL tree,
+ # and 'tpl' in the TPL tree, to make sure they are distinct from the
+ # main U-Boot tree. All three should have the same positions and offset
+ # except that the main tree should include the main_expected properties
+ start = 4
+ for item in ['', 'spl', 'tpl', None]:
+ if item is None:
+ start += 16 # Move past fdtmap header
+ dtb = fdt.Fdt.FromData(data[start:])
+ dtb.Scan()
+ props = self._GetPropTree(dtb,
+ BASE_DTB_PROPS + REPACK_DTB_PROPS + ['spl', 'tpl'],
+ prefix='/' if item is None else '/binman/')
+ expected = dict(base_expected)
+ if item:
+ expected[item] = 0
+ else:
+ # Main DTB and fdtdec should include the 'orig-' properties
+ expected.update(main_expected)
+ # Helpful for debugging:
+ #for prop in sorted(props):
+ #print('prop %s %s %s' % (prop, props[prop], expected[prop]))
+ self.assertEqual(expected, props)
+ if item == '':
+ start = SECTION_SIZE
+ else:
+ start += dtb._fdt_obj.totalsize()
+
+ def testFdtmapHeaderMiddle(self):
+ """Test an FDT map in the middle of an image when it should be at end"""
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFileRealDtb('135_fdtmap_hdr_middle.dts')
+ self.assertIn("Invalid sibling order 'middle' for image-header: Must be at 'end' to match location",
+ str(e.exception))
+
+ def testFdtmapHeaderStartBad(self):
+ """Test an FDT map in middle of an image when it should be at start"""
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFileRealDtb('136_fdtmap_hdr_startbad.dts')
+ self.assertIn("Invalid sibling order 'end' for image-header: Must be at 'start' to match location",
+ str(e.exception))
+
+ def testFdtmapHeaderEndBad(self):
+ """Test an FDT map at the start of an image when it should be at end"""
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFileRealDtb('137_fdtmap_hdr_endbad.dts')
+ self.assertIn("Invalid sibling order 'start' for image-header: Must be at 'end' to match location",
+ str(e.exception))
+
+ def testFdtmapHeaderNoSize(self):
+ """Test an image header at the end of an image with undefined size"""
+ self._DoReadFileRealDtb('138_fdtmap_hdr_nosize.dts')
+
+ def testReplaceResize(self):
+ """Test replacing a single file in an entry with a larger file"""
+ expected = U_BOOT_DATA + b'x'
+ data, _, image = self._RunReplaceCmd('u-boot', expected,
+ dts='139_replace_repack.dts')
+ self.assertEqual(expected, data)
+
+ entries = image.GetEntries()
+ dtb_data = entries['u-boot-dtb'].data
+ dtb = fdt.Fdt.FromData(dtb_data)
+ dtb.Scan()
+
+ # The u-boot section should now be larger in the dtb
+ node = dtb.GetNode('/binman/u-boot')
+ self.assertEqual(len(expected), fdt_util.GetInt(node, 'size'))
+
+ # Same for the fdtmap
+ fdata = entries['fdtmap'].data
+ fdtb = fdt.Fdt.FromData(fdata[fdtmap.FDTMAP_HDR_LEN:])
+ fdtb.Scan()
+ fnode = fdtb.GetNode('/u-boot')
+ self.assertEqual(len(expected), fdt_util.GetInt(fnode, 'size'))
+
+ def testReplaceResizeNoRepack(self):
+ """Test replacing an entry with a larger file when not allowed"""
+ expected = U_BOOT_DATA + b'x'
+ with self.assertRaises(ValueError) as e:
+ self._RunReplaceCmd('u-boot', expected)
+ self.assertIn('Entry data size does not match, but allow-repack is not present for this image',
+ str(e.exception))
+
+ def testEntryShrink(self):
+ """Test contracting an entry after it is packed"""
+ try:
+ state.SetAllowEntryContraction(True)
+ data = self._DoReadFileDtb('140_entry_shrink.dts',
+ update_dtb=True)[0]
+ finally:
+ state.SetAllowEntryContraction(False)
+ self.assertEqual(b'a', data[:1])
+ self.assertEqual(U_BOOT_DATA, data[1:1 + len(U_BOOT_DATA)])
+ self.assertEqual(b'a', data[-1:])
+
+ def testEntryShrinkFail(self):
+ """Test not being allowed to contract an entry after it is packed"""
+ data = self._DoReadFileDtb('140_entry_shrink.dts', update_dtb=True)[0]
+
+ # In this case there is a spare byte at the end of the data. The size of
+ # the contents is only 1 byte but we still have the size before it
+ # shrunk.
+ self.assertEqual(b'a\0', data[:2])
+ self.assertEqual(U_BOOT_DATA, data[2:2 + len(U_BOOT_DATA)])
+ self.assertEqual(b'a\0', data[-2:])
+
+ def testDescriptorOffset(self):
+ """Test that the Intel descriptor is always placed at at the start"""
+ data = self._DoReadFileDtb('141_descriptor_offset.dts')
+ image = control.images['image']
+ entries = image.GetEntries()
+ desc = entries['intel-descriptor']
+ self.assertEqual(0xff800000, desc.offset);
+ self.assertEqual(0xff800000, desc.image_pos);
+
+ def testReplaceCbfs(self):
+ """Test replacing a single file in CBFS without changing the size"""
+ self._CheckLz4()
+ expected = b'x' * len(U_BOOT_DATA)
+ data = self._DoReadFileRealDtb('142_replace_cbfs.dts')
+ updated_fname = tools.GetOutputFilename('image-updated.bin')
+ tools.WriteFile(updated_fname, data)
+ entry_name = 'section/cbfs/u-boot'
+ control.WriteEntry(updated_fname, entry_name, expected,
+ allow_resize=True)
+ data = control.ReadEntry(updated_fname, entry_name)
+ self.assertEqual(expected, data)
+
+ def testReplaceResizeCbfs(self):
+ """Test replacing a single file in CBFS with one of a different size"""
+ self._CheckLz4()
+ expected = U_BOOT_DATA + b'x'
+ data = self._DoReadFileRealDtb('142_replace_cbfs.dts')
+ updated_fname = tools.GetOutputFilename('image-updated.bin')
+ tools.WriteFile(updated_fname, data)
+ entry_name = 'section/cbfs/u-boot'
+ control.WriteEntry(updated_fname, entry_name, expected,
+ allow_resize=True)
+ data = control.ReadEntry(updated_fname, entry_name)
+ self.assertEqual(expected, data)
+
+ def _SetupForReplace(self):
+ """Set up some files to use to replace entries
+
+ This generates an image, copies it to a new file, extracts all the files
+ in it and updates some of them
+
+ Returns:
+ List
+ Image filename
+ Output directory
+ Expected values for updated entries, each a string
+ """
+ data = self._DoReadFileRealDtb('143_replace_all.dts')
+
+ updated_fname = tools.GetOutputFilename('image-updated.bin')
+ tools.WriteFile(updated_fname, data)
+
+ outdir = os.path.join(self._indir, 'extract')
+ einfos = control.ExtractEntries(updated_fname, None, outdir, [])
+
+ expected1 = b'x' + U_BOOT_DATA + b'y'
+ u_boot_fname1 = os.path.join(outdir, 'u-boot')
+ tools.WriteFile(u_boot_fname1, expected1)
+
+ expected2 = b'a' + U_BOOT_DATA + b'b'
+ u_boot_fname2 = os.path.join(outdir, 'u-boot2')
+ tools.WriteFile(u_boot_fname2, expected2)
+
+ expected_text = b'not the same text'
+ text_fname = os.path.join(outdir, 'text')
+ tools.WriteFile(text_fname, expected_text)
+
+ dtb_fname = os.path.join(outdir, 'u-boot-dtb')
+ dtb = fdt.FdtScan(dtb_fname)
+ node = dtb.GetNode('/binman/text')
+ node.AddString('my-property', 'the value')
+ dtb.Sync(auto_resize=True)
+ dtb.Flush()
+
+ return updated_fname, outdir, expected1, expected2, expected_text
+
+ def _CheckReplaceMultiple(self, entry_paths):
+ """Handle replacing the contents of multiple entries
+
+ Args:
+ entry_paths: List of entry paths to replace
+
+ Returns:
+ List
+ Dict of entries in the image:
+ key: Entry name
+ Value: Entry object
+ Expected values for updated entries, each a string
+ """
+ updated_fname, outdir, expected1, expected2, expected_text = (
+ self._SetupForReplace())
+ control.ReplaceEntries(updated_fname, None, outdir, entry_paths)
+
+ image = Image.FromFile(updated_fname)
+ image.LoadData()
+ return image.GetEntries(), expected1, expected2, expected_text
+
+ def testReplaceAll(self):
+ """Test replacing the contents of all entries"""
+ entries, expected1, expected2, expected_text = (
+ self._CheckReplaceMultiple([]))
+ data = entries['u-boot'].data
+ self.assertEqual(expected1, data)
+
+ data = entries['u-boot2'].data
+ self.assertEqual(expected2, data)
+
+ data = entries['text'].data
+ self.assertEqual(expected_text, data)
+
+ # Check that the device tree is updated
+ data = entries['u-boot-dtb'].data
+ dtb = fdt.Fdt.FromData(data)
+ dtb.Scan()
+ node = dtb.GetNode('/binman/text')
+ self.assertEqual('the value', node.props['my-property'].value)
+
+ def testReplaceSome(self):
+ """Test replacing the contents of a few entries"""
+ entries, expected1, expected2, expected_text = (
+ self._CheckReplaceMultiple(['u-boot2', 'text']))
+
+ # This one should not change
+ data = entries['u-boot'].data
+ self.assertEqual(U_BOOT_DATA, data)
+
+ data = entries['u-boot2'].data
+ self.assertEqual(expected2, data)
+
+ data = entries['text'].data
+ self.assertEqual(expected_text, data)
+
+ def testReplaceCmd(self):
+ """Test replacing a file fron an image on the command line"""
+ self._DoReadFileRealDtb('143_replace_all.dts')
+
+ try:
+ tmpdir, updated_fname = self._SetupImageInTmpdir()
+
+ fname = os.path.join(tmpdir, 'update-u-boot.bin')
+ expected = b'x' * len(U_BOOT_DATA)
+ tools.WriteFile(fname, expected)
+
+ self._DoBinman('replace', '-i', updated_fname, 'u-boot', '-f', fname)
+ data = tools.ReadFile(updated_fname)
+ self.assertEqual(expected, data[:len(expected)])
+ map_fname = os.path.join(tmpdir, 'image-updated.map')
+ self.assertFalse(os.path.exists(map_fname))
+ finally:
+ shutil.rmtree(tmpdir)
+
+ def testReplaceCmdSome(self):
+ """Test replacing some files fron an image on the command line"""
+ updated_fname, outdir, expected1, expected2, expected_text = (
+ self._SetupForReplace())
+
+ self._DoBinman('replace', '-i', updated_fname, '-I', outdir,
+ 'u-boot2', 'text')
+
+ tools.PrepareOutputDir(None)
+ image = Image.FromFile(updated_fname)
+ image.LoadData()
+ entries = image.GetEntries()
+
+ # This one should not change
+ data = entries['u-boot'].data
+ self.assertEqual(U_BOOT_DATA, data)
+
+ data = entries['u-boot2'].data
+ self.assertEqual(expected2, data)
+
+ data = entries['text'].data
+ self.assertEqual(expected_text, data)
+
+ def testReplaceMissing(self):
+ """Test replacing entries where the file is missing"""
+ updated_fname, outdir, expected1, expected2, expected_text = (
+ self._SetupForReplace())
+
+ # Remove one of the files, to generate a warning
+ u_boot_fname1 = os.path.join(outdir, 'u-boot')
+ os.remove(u_boot_fname1)
+
+ with test_util.capture_sys_output() as (stdout, stderr):
+ control.ReplaceEntries(updated_fname, None, outdir, [])
+ self.assertIn("Skipping entry '/u-boot' from missing file",
+ stdout.getvalue())
+
+ def testReplaceCmdMap(self):
+ """Test replacing a file fron an image on the command line"""
+ self._DoReadFileRealDtb('143_replace_all.dts')
+
+ try:
+ tmpdir, updated_fname = self._SetupImageInTmpdir()
+
+ fname = os.path.join(self._indir, 'update-u-boot.bin')
+ expected = b'x' * len(U_BOOT_DATA)
+ tools.WriteFile(fname, expected)
+
+ self._DoBinman('replace', '-i', updated_fname, 'u-boot',
+ '-f', fname, '-m')
+ map_fname = os.path.join(tmpdir, 'image-updated.map')
+ self.assertTrue(os.path.exists(map_fname))
+ finally:
+ shutil.rmtree(tmpdir)
+
+ def testReplaceNoEntryPaths(self):
+ """Test replacing an entry without an entry path"""
+ self._DoReadFileRealDtb('143_replace_all.dts')
+ image_fname = tools.GetOutputFilename('image.bin')
+ with self.assertRaises(ValueError) as e:
+ control.ReplaceEntries(image_fname, 'fname', None, [])
+ self.assertIn('Must specify an entry path to read with -f',
+ str(e.exception))
+
+ def testReplaceTooManyEntryPaths(self):
+ """Test extracting some entries"""
+ self._DoReadFileRealDtb('143_replace_all.dts')
+ image_fname = tools.GetOutputFilename('image.bin')
+ with self.assertRaises(ValueError) as e:
+ control.ReplaceEntries(image_fname, 'fname', None, ['a', 'b'])
+ self.assertIn('Must specify exactly one entry path to write with -f',
+ str(e.exception))
if __name__ == "__main__":
diff --git a/tools/binman/image.py b/tools/binman/image.py
index f237ae3..7b39a1d 100644
--- a/tools/binman/image.py
+++ b/tools/binman/image.py
@@ -8,15 +8,22 @@
from __future__ import print_function
from collections import OrderedDict
+import fnmatch
from operator import attrgetter
+import os
import re
import sys
+from entry import Entry
+from etype import fdtmap
+from etype import image_header
+from etype import section
+import fdt
import fdt_util
-import bsection
import tools
+import tout
-class Image:
+class Image(section.Entry_section):
"""A Image, representing an output from binman
An image is comprised of a collection of entries each containing binary
@@ -24,119 +31,126 @@
This class implements the various operations needed for images.
- Atrtributes:
- _node: Node object that contains the image definition in device tree
- _name: Image name
- _size: Image size in bytes, or None if not known yet
- _filename: Output filename for image
- _sections: Sections present in this image (may be one or more)
+ Attributes:
+ filename: Output filename for image
+ image_node: Name of node containing the description for this image
+ fdtmap_dtb: Fdt object for the fdtmap when loading from a file
+ fdtmap_data: Contents of the fdtmap when loading from a file
+ allow_repack: True to add properties to allow the image to be safely
+ repacked later
Args:
+ copy_to_orig: Copy offset/size to orig_offset/orig_size after reading
+ from the device tree
test: True if this is being called from a test of Images. This this case
there is no device tree defining the structure of the section, so
we create a section manually.
"""
- def __init__(self, name, node, test=False):
- self._node = node
- self._name = name
- self._size = None
- self._filename = '%s.bin' % self._name
- if test:
- self._section = bsection.Section('main-section', None, self._node,
- self, True)
- else:
- self._ReadNode()
+ def __init__(self, name, node, copy_to_orig=True, test=False):
+ section.Entry_section.__init__(self, None, 'section', node, test=test)
+ self.copy_to_orig = copy_to_orig
+ self.name = 'main-section'
+ self.image_name = name
+ self._filename = '%s.bin' % self.image_name
+ self.fdtmap_dtb = None
+ self.fdtmap_data = None
+ self.allow_repack = False
+ if not test:
+ self.ReadNode()
- def _ReadNode(self):
- """Read properties from the image node"""
- self._size = fdt_util.GetInt(self._node, 'size')
+ def ReadNode(self):
+ section.Entry_section.ReadNode(self)
filename = fdt_util.GetString(self._node, 'filename')
if filename:
self._filename = filename
- self._section = bsection.Section('main-section', None, self._node, self)
+ self.allow_repack = fdt_util.GetBool(self._node, 'allow-repack')
- def GetFdtSet(self):
- """Get the set of device tree files used by this image"""
- return self._section.GetFdtSet()
+ @classmethod
+ def FromFile(cls, fname):
+ """Convert an image file into an Image for use in binman
- def ExpandEntries(self):
- """Expand out any entries which have calculated sub-entries
+ Args:
+ fname: Filename of image file to read
- Some entries are expanded out at runtime, e.g. 'files', which produces
- a section containing a list of files. Process these entries so that
- this information is added to the device tree.
+ Returns:
+ Image object on success
+
+ Raises:
+ ValueError if something goes wrong
"""
- self._section.ExpandEntries()
+ data = tools.ReadFile(fname)
+ size = len(data)
- def AddMissingProperties(self):
- """Add properties that are not present in the device tree
+ # First look for an image header
+ pos = image_header.LocateHeaderOffset(data)
+ if pos is None:
+ # Look for the FDT map
+ pos = fdtmap.LocateFdtmap(data)
+ if pos is None:
+ raise ValueError('Cannot find FDT map in image')
- When binman has completed packing the entries the offset and size of
- each entry are known. But before this the device tree may not specify
- these. Add any missing properties, with a dummy value, so that the
- size of the entry is correct. That way we can insert the correct values
- later.
- """
- self._section.AddMissingProperties()
+ # We don't know the FDT size, so check its header first
+ probe_dtb = fdt.Fdt.FromData(
+ data[pos + fdtmap.FDTMAP_HDR_LEN:pos + 256])
+ dtb_size = probe_dtb.GetFdtObj().totalsize()
+ fdtmap_data = data[pos:pos + dtb_size + fdtmap.FDTMAP_HDR_LEN]
+ fdt_data = fdtmap_data[fdtmap.FDTMAP_HDR_LEN:]
+ out_fname = tools.GetOutputFilename('fdtmap.in.dtb')
+ tools.WriteFile(out_fname, fdt_data)
+ dtb = fdt.Fdt(out_fname)
+ dtb.Scan()
- def ProcessFdt(self, fdt):
- """Allow entries to adjust the device tree
+ # Return an Image with the associated nodes
+ root = dtb.GetRoot()
+ image = Image('image', root, copy_to_orig=False)
- Some entries need to adjust the device tree for their purposes. This
- may involve adding or deleting properties.
- """
- return self._section.ProcessFdt(fdt)
+ image.image_node = fdt_util.GetString(root, 'image-node', 'image')
+ image.fdtmap_dtb = dtb
+ image.fdtmap_data = fdtmap_data
+ image._data = data
+ image._filename = fname
+ image.image_name, _ = os.path.splitext(fname)
+ return image
- def GetEntryContents(self):
- """Call ObtainContents() for the section
- """
- self._section.GetEntryContents()
-
- def GetEntryOffsets(self):
- """Handle entries that want to set the offset/size of other entries
-
- This calls each entry's GetOffsets() method. If it returns a list
- of entries to update, it updates them.
- """
- self._section.GetEntryOffsets()
+ def Raise(self, msg):
+ """Convenience function to raise an error referencing an image"""
+ raise ValueError("Image '%s': %s" % (self._node.path, msg))
def PackEntries(self):
"""Pack all entries into the image"""
- self._section.PackEntries()
-
- def CheckSize(self):
- """Check that the image contents does not exceed its size, etc."""
- self._size = self._section.CheckSize()
-
- def CheckEntries(self):
- """Check that entries do not overlap or extend outside the image"""
- self._section.CheckEntries()
-
- def SetCalculatedProperties(self):
- self._section.SetCalculatedProperties()
+ section.Entry_section.Pack(self, 0)
def SetImagePos(self):
- self._section.SetImagePos(0)
+ # This first section in the image so it starts at 0
+ section.Entry_section.SetImagePos(self, 0)
def ProcessEntryContents(self):
"""Call the ProcessContents() method for each entry
This is intended to adjust the contents as needed by the entry type.
+
+ Returns:
+ True if the new data size is OK, False if expansion is needed
"""
- self._section.ProcessEntryContents()
+ sizes_ok = True
+ for entry in self._entries.values():
+ if not entry.ProcessContents():
+ sizes_ok = False
+ tout.Debug("Entry '%s' size change" % self._node.path)
+ return sizes_ok
def WriteSymbols(self):
"""Write symbol values into binary files for access at run time"""
- self._section.WriteSymbols()
+ section.Entry_section.WriteSymbols(self, self)
def BuildImage(self):
"""Write the image to a file"""
fname = tools.GetOutputFilename(self._filename)
+ tout.Info("Writing image to '%s'" % fname)
with open(fname, 'wb') as fd:
- self._section.BuildSection(fd, 0)
-
- def GetEntries(self):
- return self._section.GetEntries()
+ data = self.GetData()
+ fd.write(data)
+ tout.Info("Wrote %#x bytes" % len(data))
def WriteMap(self):
"""Write a map of the image to a .map file
@@ -144,10 +158,169 @@
Returns:
Filename of map file written
"""
- filename = '%s.map' % self._name
+ filename = '%s.map' % self.image_name
fname = tools.GetOutputFilename(filename)
with open(fname, 'w') as fd:
print('%8s %8s %8s %s' % ('ImagePos', 'Offset', 'Size', 'Name'),
file=fd)
- self._section.WriteMap(fd, 0)
+ section.Entry_section.WriteMap(self, fd, 0)
return fname
+
+ def BuildEntryList(self):
+ """List the files in an image
+
+ Returns:
+ List of entry.EntryInfo objects describing all entries in the image
+ """
+ entries = []
+ self.ListEntries(entries, 0)
+ return entries
+
+ def FindEntryPath(self, entry_path):
+ """Find an entry at a given path in the image
+
+ Args:
+ entry_path: Path to entry (e.g. /ro-section/u-boot')
+
+ Returns:
+ Entry object corresponding to that past
+
+ Raises:
+ ValueError if no entry found
+ """
+ parts = entry_path.split('/')
+ entries = self.GetEntries()
+ parent = '/'
+ for part in parts:
+ entry = entries.get(part)
+ if not entry:
+ raise ValueError("Entry '%s' not found in '%s'" %
+ (part, parent))
+ parent = entry.GetPath()
+ entries = entry.GetEntries()
+ return entry
+
+ def ReadData(self, decomp=True):
+ return self._data
+
+ def GetListEntries(self, entry_paths):
+ """List the entries in an image
+
+ This decodes the supplied image and returns a list of entries from that
+ image, preceded by a header.
+
+ Args:
+ entry_paths: List of paths to match (each can have wildcards). Only
+ entries whose names match one of these paths will be printed
+
+ Returns:
+ String error message if something went wrong, otherwise
+ 3-Tuple:
+ List of EntryInfo objects
+ List of lines, each
+ List of text columns, each a string
+ List of widths of each column
+ """
+ def _EntryToStrings(entry):
+ """Convert an entry to a list of strings, one for each column
+
+ Args:
+ entry: EntryInfo object containing information to output
+
+ Returns:
+ List of strings, one for each field in entry
+ """
+ def _AppendHex(val):
+ """Append a hex value, or an empty string if val is None
+
+ Args:
+ val: Integer value, or None if none
+ """
+ args.append('' if val is None else '>%x' % val)
+
+ args = [' ' * entry.indent + entry.name]
+ _AppendHex(entry.image_pos)
+ _AppendHex(entry.size)
+ args.append(entry.etype)
+ _AppendHex(entry.offset)
+ _AppendHex(entry.uncomp_size)
+ return args
+
+ def _DoLine(lines, line):
+ """Add a line to the output list
+
+ This adds a line (a list of columns) to the output list. It also updates
+ the widths[] array with the maximum width of each column
+
+ Args:
+ lines: List of lines to add to
+ line: List of strings, one for each column
+ """
+ for i, item in enumerate(line):
+ widths[i] = max(widths[i], len(item))
+ lines.append(line)
+
+ def _NameInPaths(fname, entry_paths):
+ """Check if a filename is in a list of wildcarded paths
+
+ Args:
+ fname: Filename to check
+ entry_paths: List of wildcarded paths (e.g. ['*dtb*', 'u-boot*',
+ 'section/u-boot'])
+
+ Returns:
+ True if any wildcard matches the filename (using Unix filename
+ pattern matching, not regular expressions)
+ False if not
+ """
+ for path in entry_paths:
+ if fnmatch.fnmatch(fname, path):
+ return True
+ return False
+
+ entries = self.BuildEntryList()
+
+ # This is our list of lines. Each item in the list is a list of strings, one
+ # for each column
+ lines = []
+ HEADER = ['Name', 'Image-pos', 'Size', 'Entry-type', 'Offset',
+ 'Uncomp-size']
+ num_columns = len(HEADER)
+
+ # This records the width of each column, calculated as the maximum width of
+ # all the strings in that column
+ widths = [0] * num_columns
+ _DoLine(lines, HEADER)
+
+ # We won't print anything unless it has at least this indent. So at the
+ # start we will print nothing, unless a path matches (or there are no
+ # entry paths)
+ MAX_INDENT = 100
+ min_indent = MAX_INDENT
+ path_stack = []
+ path = ''
+ indent = 0
+ selected_entries = []
+ for entry in entries:
+ if entry.indent > indent:
+ path_stack.append(path)
+ elif entry.indent < indent:
+ path_stack.pop()
+ if path_stack:
+ path = path_stack[-1] + '/' + entry.name
+ indent = entry.indent
+
+ # If there are entry paths to match and we are not looking at a
+ # sub-entry of a previously matched entry, we need to check the path
+ if entry_paths and indent <= min_indent:
+ if _NameInPaths(path[1:], entry_paths):
+ # Print this entry and all sub-entries (=higher indent)
+ min_indent = indent
+ else:
+ # Don't print this entry, nor any following entries until we get
+ # a path match
+ min_indent = MAX_INDENT
+ continue
+ _DoLine(lines, _EntryToStrings(entry))
+ selected_entries.append(entry)
+ return selected_entries, lines, widths
diff --git a/tools/binman/image_test.py b/tools/binman/image_test.py
index 3775e1a..4004f78 100644
--- a/tools/binman/image_test.py
+++ b/tools/binman/image_test.py
@@ -12,28 +12,25 @@
class TestImage(unittest.TestCase):
def testInvalidFormat(self):
image = Image('name', 'node', test=True)
- section = image._section
with self.assertRaises(ValueError) as e:
- section.LookupSymbol('_binman_something_prop_', False, 'msg')
+ image.LookupSymbol('_binman_something_prop_', False, 'msg')
self.assertIn(
"msg: Symbol '_binman_something_prop_' has invalid format",
str(e.exception))
def testMissingSymbol(self):
image = Image('name', 'node', test=True)
- section = image._section
- section._entries = {}
+ image._entries = {}
with self.assertRaises(ValueError) as e:
- section.LookupSymbol('_binman_type_prop_pname', False, 'msg')
+ image.LookupSymbol('_binman_type_prop_pname', False, 'msg')
self.assertIn("msg: Entry 'type' not found in list ()",
str(e.exception))
def testMissingSymbolOptional(self):
image = Image('name', 'node', test=True)
- section = image._section
- section._entries = {}
+ image._entries = {}
with capture_sys_output() as (stdout, stderr):
- val = section.LookupSymbol('_binman_type_prop_pname', True, 'msg')
+ val = image.LookupSymbol('_binman_type_prop_pname', True, 'msg')
self.assertEqual(val, None)
self.assertEqual("Warning: msg: Entry 'type' not found in list ()\n",
stderr.getvalue())
@@ -41,8 +38,7 @@
def testBadProperty(self):
image = Image('name', 'node', test=True)
- section = image._section
- section._entries = {'u-boot': 1}
+ image._entries = {'u-boot': 1}
with self.assertRaises(ValueError) as e:
- section.LookupSymbol('_binman_u_boot_prop_bad', False, 'msg')
+ image.LookupSymbol('_binman_u_boot_prop_bad', False, 'msg')
self.assertIn("msg: No such property 'bad", str(e.exception))
diff --git a/tools/binman/state.py b/tools/binman/state.py
index d945e4b..d704ed2 100644
--- a/tools/binman/state.py
+++ b/tools/binman/state.py
@@ -7,14 +7,25 @@
import hashlib
import re
-from sets import Set
+import fdt
import os
import tools
+import tout
-# Records the device-tree files known to binman, keyed by filename (e.g.
-# 'u-boot-spl.dtb')
-fdt_files = {}
+# Records the device-tree files known to binman, keyed by entry type (e.g.
+# 'u-boot-spl-dtb'). These are the output FDT files, which can be updated by
+# binman. They have been copied to <xxx>.out files.
+#
+# key: entry type
+# value: tuple:
+# Fdt object
+# Filename
+# Entry object, or None if not known
+output_fdt_info = {}
+
+# Prefix to add to an fdtmap path to turn it into a path to the /binman node
+fdt_path_prefix = ''
# Arguments passed to binman to provide arguments to entries
entry_args = {}
@@ -23,44 +34,55 @@
# ftest.py)
use_fake_dtb = False
-# Set of all device tree files references by images
-fdt_set = Set()
-
-# Same as above, but excluding the main one
-fdt_subset = Set()
-
# The DTB which contains the full image information
main_dtb = None
-def GetFdt(fname):
- """Get the Fdt object for a particular device-tree filename
+# Allow entries to expand after they have been packed. This is detected and
+# forces a re-pack. If not allowed, any attempted expansion causes an error in
+# Entry.ProcessContentsUpdate()
+allow_entry_expansion = True
+
+# Don't allow entries to contract after they have been packed. Instead just
+# leave some wasted space. If allowed, this is detected and forces a re-pack,
+# but may result in entries that oscillate in size, thus causing a pack error.
+# An example is a compressed device tree where the original offset values
+# result in a larger compressed size than the new ones, but then after updating
+# to the new ones, the compressed size increases, etc.
+allow_entry_contraction = False
+
+def GetFdtForEtype(etype):
+ """Get the Fdt object for a particular device-tree entry
Binman keeps track of at least one device-tree file called u-boot.dtb but
can also have others (e.g. for SPL). This function looks up the given
- filename and returns the associated Fdt object.
+ entry and returns the associated Fdt object.
Args:
- fname: Filename to look up (e.g. 'u-boot.dtb').
+ etype: Entry type of device tree (e.g. 'u-boot-dtb')
Returns:
- Fdt object associated with the filename
+ Fdt object associated with the entry type
"""
- return fdt_files[fname]
+ value = output_fdt_info.get(etype);
+ if not value:
+ return None
+ return value[0]
-def GetFdtPath(fname):
+def GetFdtPath(etype):
"""Get the full pathname of a particular Fdt object
- Similar to GetFdt() but returns the pathname associated with the Fdt.
+ Similar to GetFdtForEtype() but returns the pathname associated with the
+ Fdt.
Args:
- fname: Filename to look up (e.g. 'u-boot.dtb').
+ etype: Entry type of device tree (e.g. 'u-boot-dtb')
Returns:
Full path name to the associated Fdt
"""
- return fdt_files[fname]._fname
+ return output_fdt_info[etype][0]._fname
-def GetFdtContents(fname):
+def GetFdtContents(etype='u-boot-dtb'):
"""Looks up the FDT pathname and contents
This is used to obtain the Fdt pathname and contents when needed by an
@@ -68,21 +90,40 @@
the real dtb.
Args:
- fname: Filename to look up (e.g. 'u-boot.dtb').
+ etype: Entry type to look up (e.g. 'u-boot.dtb').
Returns:
tuple:
pathname to Fdt
Fdt data (as bytes)
"""
- if fname in fdt_files and not use_fake_dtb:
- pathname = GetFdtPath(fname)
- data = GetFdt(fname).GetContents()
+ if etype not in output_fdt_info:
+ return None, None
+ if not use_fake_dtb:
+ pathname = GetFdtPath(etype)
+ data = GetFdtForEtype(etype).GetContents()
else:
+ fname = output_fdt_info[etype][1]
pathname = tools.GetInputFilename(fname)
data = tools.ReadFile(pathname)
return pathname, data
+def UpdateFdtContents(etype, data):
+ """Update the contents of a particular device tree
+
+ The device tree is updated and written back to its file. This affects what
+ is returned from future called to GetFdtContents(), etc.
+
+ Args:
+ etype: Entry type (e.g. 'u-boot-dtb')
+ data: Data to replace the DTB with
+ """
+ dtb, fname, entry = output_fdt_info[etype]
+ dtb_fname = dtb.GetFilename()
+ tools.WriteFile(dtb_fname, data)
+ dtb = fdt.FdtScan(dtb_fname)
+ output_fdt_info[etype] = [dtb, fname, entry]
+
def SetEntryArgs(args):
"""Set the value of the entry args
@@ -116,14 +157,14 @@
def Prepare(images, dtb):
"""Get device tree files ready for use
- This sets up a set of device tree files that can be retrieved by GetFdts().
- At present there is only one, that for U-Boot proper.
+ This sets up a set of device tree files that can be retrieved by
+ GetAllFdts(). This includes U-Boot proper and any SPL device trees.
Args:
images: List of images being used
dtb: Main dtb
"""
- global fdt_set, fdt_subset, fdt_files, main_dtb
+ global output_fdt_info, main_dtb, fdt_path_prefix
# Import these here in case libfdt.py is not available, in which case
# the above help option still works.
import fdt
@@ -134,33 +175,82 @@
# since it is assumed to be the one passed in with options.dt, and
# was handled just above.
main_dtb = dtb
- fdt_files.clear()
- fdt_files['u-boot.dtb'] = dtb
- fdt_subset = Set()
+ output_fdt_info.clear()
+ fdt_path_prefix = ''
+ output_fdt_info['u-boot-dtb'] = [dtb, 'u-boot.dtb', None]
+ output_fdt_info['u-boot-spl-dtb'] = [dtb, 'spl/u-boot-spl.dtb', None]
+ output_fdt_info['u-boot-tpl-dtb'] = [dtb, 'tpl/u-boot-tpl.dtb', None]
if not use_fake_dtb:
+ fdt_set = {}
for image in images.values():
- fdt_subset.update(image.GetFdtSet())
- fdt_subset.discard('u-boot.dtb')
- for other_fname in fdt_subset:
+ fdt_set.update(image.GetFdts())
+ for etype, other in fdt_set.items():
+ entry, other_fname = other
infile = tools.GetInputFilename(other_fname)
other_fname_dtb = fdt_util.EnsureCompiled(infile)
out_fname = tools.GetOutputFilename('%s.out' %
os.path.split(other_fname)[1])
tools.WriteFile(out_fname, tools.ReadFile(other_fname_dtb))
other_dtb = fdt.FdtScan(out_fname)
- fdt_files[other_fname] = other_dtb
+ output_fdt_info[etype] = [other_dtb, out_fname, entry]
-def GetFdts():
+def PrepareFromLoadedData(image):
+ """Get device tree files ready for use with a loaded image
+
+ Loaded images are different from images that are being created by binman,
+ since there is generally already an fdtmap and we read the description from
+ that. This provides the position and size of every entry in the image with
+ no calculation required.
+
+ This function uses the same output_fdt_info[] as Prepare(). It finds the
+ device tree files, adds a reference to the fdtmap and sets the FDT path
+ prefix to translate from the fdtmap (where the root node is the image node)
+ to the normal device tree (where the image node is under a /binman node).
+
+ Args:
+ images: List of images being used
+ """
+ global output_fdt_info, main_dtb, fdt_path_prefix
+
+ tout.Info('Preparing device trees')
+ output_fdt_info.clear()
+ fdt_path_prefix = ''
+ output_fdt_info['fdtmap'] = [image.fdtmap_dtb, 'u-boot.dtb', None]
+ main_dtb = None
+ tout.Info(" Found device tree type 'fdtmap' '%s'" % image.fdtmap_dtb.name)
+ for etype, value in image.GetFdts().items():
+ entry, fname = value
+ out_fname = tools.GetOutputFilename('%s.dtb' % entry.etype)
+ tout.Info(" Found device tree type '%s' at '%s' path '%s'" %
+ (etype, out_fname, entry.GetPath()))
+ entry._filename = entry.GetDefaultFilename()
+ data = entry.ReadData()
+
+ tools.WriteFile(out_fname, data)
+ dtb = fdt.Fdt(out_fname)
+ dtb.Scan()
+ image_node = dtb.GetNode('/binman')
+ if 'multiple-images' in image_node.props:
+ image_node = dtb.GetNode('/binman/%s' % image.image_node)
+ fdt_path_prefix = image_node.path
+ output_fdt_info[etype] = [dtb, None, entry]
+ tout.Info(" FDT path prefix '%s'" % fdt_path_prefix)
+
+
+def GetAllFdts():
"""Yield all device tree files being used by binman
Yields:
Device trees being used (U-Boot proper, SPL, TPL)
"""
- yield main_dtb
- for other_fname in fdt_subset:
- yield fdt_files[other_fname]
+ if main_dtb:
+ yield main_dtb
+ for etype in output_fdt_info:
+ dtb = output_fdt_info[etype][0]
+ if dtb != main_dtb:
+ yield dtb
-def GetUpdateNodes(node):
+def GetUpdateNodes(node, for_repack=False):
"""Yield all the nodes that need to be updated in all device trees
The property referenced by this node is added to any device trees which
@@ -169,25 +259,32 @@
Args:
node: Node object in the main device tree to look up
+ for_repack: True if we want only nodes which need 'repack' properties
+ added to them (e.g. 'orig-offset'), False to return all nodes. We
+ don't add repack properties to SPL/TPL device trees.
Yields:
Node objects in each device tree that is in use (U-Boot proper, which
is node, SPL and TPL)
"""
yield node
- for dtb in fdt_files.values():
+ for dtb, fname, entry in output_fdt_info.values():
if dtb != node.GetFdt():
- other_node = dtb.GetNode(node.path)
+ if for_repack and entry.etype != 'u-boot-dtb':
+ continue
+ other_node = dtb.GetNode(fdt_path_prefix + node.path)
+ #print(' try', fdt_path_prefix + node.path, other_node)
if other_node:
yield other_node
-def AddZeroProp(node, prop):
+def AddZeroProp(node, prop, for_repack=False):
"""Add a new property to affected device trees with an integer value of 0.
Args:
prop_name: Name of property
+ for_repack: True is this property is only needed for repacking
"""
- for n in GetUpdateNodes(node):
+ for n in GetUpdateNodes(node, for_repack):
n.AddZeroProp(prop)
def AddSubnode(node, name):
@@ -217,15 +314,18 @@
for n in GetUpdateNodes(node):
n.AddString(prop, value)
-def SetInt(node, prop, value):
+def SetInt(node, prop, value, for_repack=False):
"""Update an integer property in affected device trees with an integer value
This is not allowed to change the size of the FDT.
Args:
prop_name: Name of property
+ for_repack: True is this property is only needed for repacking
"""
- for n in GetUpdateNodes(node):
+ for n in GetUpdateNodes(node, for_repack):
+ tout.Detail("File %s: Update node '%s' prop '%s' to %#x" %
+ (n.GetFdt().name, n.path, prop, value))
n.SetInt(prop, value)
def CheckAddHashProp(node):
@@ -251,3 +351,41 @@
data = m.digest()
for n in GetUpdateNodes(hash_node):
n.SetData('value', data)
+
+def SetAllowEntryExpansion(allow):
+ """Set whether post-pack expansion of entries is allowed
+
+ Args:
+ allow: True to allow expansion, False to raise an exception
+ """
+ global allow_entry_expansion
+
+ allow_entry_expansion = allow
+
+def AllowEntryExpansion():
+ """Check whether post-pack expansion of entries is allowed
+
+ Returns:
+ True if expansion should be allowed, False if an exception should be
+ raised
+ """
+ return allow_entry_expansion
+
+def SetAllowEntryContraction(allow):
+ """Set whether post-pack contraction of entries is allowed
+
+ Args:
+ allow: True to allow contraction, False to raise an exception
+ """
+ global allow_entry_contraction
+
+ allow_entry_contraction = allow
+
+def AllowEntryContraction():
+ """Check whether post-pack contraction of entries is allowed
+
+ Returns:
+ True if contraction should be allowed, False if an exception should be
+ raised
+ """
+ return allow_entry_contraction
diff --git a/tools/binman/test/066_text.dts b/tools/binman/test/066_text.dts
index 59b1fed..f23a75a 100644
--- a/tools/binman/test/066_text.dts
+++ b/tools/binman/test/066_text.dts
@@ -24,5 +24,10 @@
text-label = "test-id4";
test-id4 = "some text";
};
+ /* Put text directly in the node */
+ text5 {
+ type = "text";
+ text = "more text";
+ };
};
};
diff --git a/tools/binman/test/096_elf.dts b/tools/binman/test/096_elf.dts
index df3440c..8e3f3f1 100644
--- a/tools/binman/test/096_elf.dts
+++ b/tools/binman/test/096_elf.dts
@@ -10,5 +10,7 @@
};
u-boot-spl-elf {
};
+ u-boot-tpl-elf {
+ };
};
};
diff --git a/tools/binman/test/102_cbfs_raw.dts b/tools/binman/test/102_cbfs_raw.dts
new file mode 100644
index 0000000..779cbc1
--- /dev/null
+++ b/tools/binman/test/102_cbfs_raw.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ cbfs {
+ size = <0xb0>;
+ u-boot {
+ cbfs-type = "raw";
+ };
+ u-boot-dtb {
+ cbfs-type = "raw";
+ };
+ };
+ };
+};
diff --git a/tools/binman/test/103_cbfs_raw_ppc.dts b/tools/binman/test/103_cbfs_raw_ppc.dts
new file mode 100644
index 0000000..df1caf0
--- /dev/null
+++ b/tools/binman/test/103_cbfs_raw_ppc.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ cbfs {
+ size = <0x100>;
+ cbfs-arch = "ppc64";
+ u-boot {
+ cbfs-type = "raw";
+ };
+ u-boot-dtb {
+ cbfs-type = "raw";
+ };
+ };
+ };
+};
diff --git a/tools/binman/test/104_cbfs_stage.dts b/tools/binman/test/104_cbfs_stage.dts
new file mode 100644
index 0000000..215e2f2
--- /dev/null
+++ b/tools/binman/test/104_cbfs_stage.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ cbfs {
+ size = <0xb0>;
+ u-boot {
+ type = "blob";
+ filename = "cbfs-stage.elf";
+ cbfs-type = "stage";
+ };
+ };
+ };
+};
diff --git a/tools/binman/test/105_cbfs_raw_compress.dts b/tools/binman/test/105_cbfs_raw_compress.dts
new file mode 100644
index 0000000..646168d
--- /dev/null
+++ b/tools/binman/test/105_cbfs_raw_compress.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ cbfs {
+ size = <0x140>;
+ u-boot {
+ type = "text";
+ text = "compress xxxxxxxxxxxxxxxxxxxxxx data";
+ cbfs-type = "raw";
+ cbfs-compress = "lz4";
+ };
+ u-boot-dtb {
+ type = "text";
+ text = "compress xxxxxxxxxxxxxxxxxxxxxx data";
+ cbfs-type = "raw";
+ cbfs-compress = "lzma";
+ };
+ };
+ };
+};
diff --git a/tools/binman/test/106_cbfs_bad_arch.dts b/tools/binman/test/106_cbfs_bad_arch.dts
new file mode 100644
index 0000000..4318d45
--- /dev/null
+++ b/tools/binman/test/106_cbfs_bad_arch.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ cbfs {
+ size = <0x100>;
+ cbfs-arch = "bad-arch";
+ };
+ };
+};
diff --git a/tools/binman/test/107_cbfs_no_size.dts b/tools/binman/test/107_cbfs_no_size.dts
new file mode 100644
index 0000000..3592f62
--- /dev/null
+++ b/tools/binman/test/107_cbfs_no_size.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ cbfs {
+ };
+ };
+};
diff --git a/tools/binman/test/108_cbfs_no_contents.dts b/tools/binman/test/108_cbfs_no_contents.dts
new file mode 100644
index 0000000..6233467
--- /dev/null
+++ b/tools/binman/test/108_cbfs_no_contents.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ cbfs {
+ size = <0x100>;
+ _testing {
+ return-unknown-contents;
+ };
+ };
+ };
+};
diff --git a/tools/binman/test/109_cbfs_bad_compress.dts b/tools/binman/test/109_cbfs_bad_compress.dts
new file mode 100644
index 0000000..9695024
--- /dev/null
+++ b/tools/binman/test/109_cbfs_bad_compress.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ cbfs {
+ size = <0xb0>;
+ u-boot {
+ cbfs-type = "raw";
+ cbfs-compress = "invalid-algo";
+ };
+ };
+ };
+};
diff --git a/tools/binman/test/110_cbfs_name.dts b/tools/binman/test/110_cbfs_name.dts
new file mode 100644
index 0000000..98c16f3
--- /dev/null
+++ b/tools/binman/test/110_cbfs_name.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ cbfs {
+ size = <0x100>;
+ u-boot {
+ cbfs-name = "FRED";
+ cbfs-type = "raw";
+ };
+
+ hello {
+ type = "blob";
+ filename = "u-boot.dtb";
+ cbfs-type = "raw";
+ };
+ };
+ };
+};
diff --git a/tools/binman/test/111_x86-rom-ifwi.dts b/tools/binman/test/111_x86-rom-ifwi.dts
new file mode 100644
index 0000000..63b5972
--- /dev/null
+++ b/tools/binman/test/111_x86-rom-ifwi.dts
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ sort-by-offset;
+ end-at-4gb;
+ size = <0x800000>;
+ intel-descriptor {
+ filename = "descriptor.bin";
+ };
+
+ intel-ifwi {
+ offset-unset;
+ filename = "fitimage.bin";
+ convert-fit;
+
+ u-boot-tpl {
+ replace;
+ ifwi-subpart = "IBBP";
+ ifwi-entry = "IBBL";
+ };
+ };
+ };
+};
diff --git a/tools/binman/test/112_x86-rom-ifwi-nodesc.dts b/tools/binman/test/112_x86-rom-ifwi-nodesc.dts
new file mode 100644
index 0000000..21ec465
--- /dev/null
+++ b/tools/binman/test/112_x86-rom-ifwi-nodesc.dts
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ sort-by-offset;
+ end-at-4gb;
+ size = <0x800000>;
+ intel-descriptor {
+ filename = "descriptor.bin";
+ };
+
+ intel-ifwi {
+ offset-unset;
+ filename = "ifwi.bin";
+
+ u-boot-tpl {
+ replace;
+ ifwi-subpart = "IBBP";
+ ifwi-entry = "IBBL";
+ };
+ };
+ };
+};
diff --git a/tools/binman/test/113_x86-rom-ifwi-nodata.dts b/tools/binman/test/113_x86-rom-ifwi-nodata.dts
new file mode 100644
index 0000000..62486fd
--- /dev/null
+++ b/tools/binman/test/113_x86-rom-ifwi-nodata.dts
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ sort-by-offset;
+ end-at-4gb;
+ size = <0x800000>;
+ intel-descriptor {
+ filename = "descriptor.bin";
+ };
+
+ intel-ifwi {
+ offset-unset;
+ filename = "ifwi.bin";
+
+ _testing {
+ return-unknown-contents;
+ replace;
+ ifwi-subpart = "IBBP";
+ ifwi-entry = "IBBL";
+ };
+ };
+ };
+};
diff --git a/tools/binman/test/114_cbfs_offset.dts b/tools/binman/test/114_cbfs_offset.dts
new file mode 100644
index 0000000..7aa9d9d
--- /dev/null
+++ b/tools/binman/test/114_cbfs_offset.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ sort-by-offset;
+ end-at-4gb;
+ size = <0x200>;
+ cbfs {
+ size = <0x200>;
+ offset = <0xfffffe00>;
+ u-boot {
+ cbfs-offset = <0x40>;
+ cbfs-type = "raw";
+ };
+ u-boot-dtb {
+ cbfs-offset = <0x140>;
+ cbfs-type = "raw";
+ };
+ };
+ };
+};
diff --git a/tools/binman/test/115_fdtmap.dts b/tools/binman/test/115_fdtmap.dts
new file mode 100644
index 0000000..2450c41
--- /dev/null
+++ b/tools/binman/test/115_fdtmap.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ u-boot {
+ };
+ fdtmap {
+ };
+ };
+};
diff --git a/tools/binman/test/116_fdtmap_hdr.dts b/tools/binman/test/116_fdtmap_hdr.dts
new file mode 100644
index 0000000..77a2194
--- /dev/null
+++ b/tools/binman/test/116_fdtmap_hdr.dts
@@ -0,0 +1,17 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ size = <0x400>;
+ u-boot {
+ };
+ fdtmap {
+ };
+ image-header {
+ location = "end";
+ };
+ };
+};
diff --git a/tools/binman/test/117_fdtmap_hdr_start.dts b/tools/binman/test/117_fdtmap_hdr_start.dts
new file mode 100644
index 0000000..17b6be0
--- /dev/null
+++ b/tools/binman/test/117_fdtmap_hdr_start.dts
@@ -0,0 +1,19 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ size = <0x400>;
+ sort-by-offset;
+ u-boot {
+ offset = <0x100>;
+ };
+ fdtmap {
+ };
+ image-header {
+ location = "start";
+ };
+ };
+};
diff --git a/tools/binman/test/118_fdtmap_hdr_pos.dts b/tools/binman/test/118_fdtmap_hdr_pos.dts
new file mode 100644
index 0000000..fd803f5
--- /dev/null
+++ b/tools/binman/test/118_fdtmap_hdr_pos.dts
@@ -0,0 +1,19 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ size = <0x400>;
+ sort-by-offset;
+ u-boot {
+ offset = <0x100>;
+ };
+ fdtmap {
+ };
+ image-header {
+ offset = <0x80>;
+ };
+ };
+};
diff --git a/tools/binman/test/119_fdtmap_hdr_missing.dts b/tools/binman/test/119_fdtmap_hdr_missing.dts
new file mode 100644
index 0000000..41bb680
--- /dev/null
+++ b/tools/binman/test/119_fdtmap_hdr_missing.dts
@@ -0,0 +1,16 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ sort-by-offset;
+ u-boot {
+ };
+ image-header {
+ offset = <0x80>;
+ location = "start";
+ };
+ };
+};
diff --git a/tools/binman/test/120_hdr_no_location.dts b/tools/binman/test/120_hdr_no_location.dts
new file mode 100644
index 0000000..585e21f
--- /dev/null
+++ b/tools/binman/test/120_hdr_no_location.dts
@@ -0,0 +1,16 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ sort-by-offset;
+ u-boot {
+ };
+ fdtmap {
+ };
+ image-header {
+ };
+ };
+};
diff --git a/tools/binman/test/121_entry_expand.dts b/tools/binman/test/121_entry_expand.dts
new file mode 100644
index 0000000..ebb7816
--- /dev/null
+++ b/tools/binman/test/121_entry_expand.dts
@@ -0,0 +1,20 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ _testing {
+ bad-update-contents;
+ };
+
+ u-boot {
+ };
+
+ _testing2 {
+ type = "_testing";
+ bad-update-contents;
+ };
+ };
+};
diff --git a/tools/binman/test/122_entry_expand_twice.dts b/tools/binman/test/122_entry_expand_twice.dts
new file mode 100644
index 0000000..258cf85
--- /dev/null
+++ b/tools/binman/test/122_entry_expand_twice.dts
@@ -0,0 +1,21 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ _testing {
+ bad-update-contents;
+ bad-update-contents-twice;
+ };
+
+ u-boot {
+ };
+
+ _testing2 {
+ type = "_testing";
+ bad-update-contents;
+ };
+ };
+};
diff --git a/tools/binman/test/123_entry_expand_section.dts b/tools/binman/test/123_entry_expand_section.dts
new file mode 100644
index 0000000..046f723
--- /dev/null
+++ b/tools/binman/test/123_entry_expand_section.dts
@@ -0,0 +1,22 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ _testing {
+ bad-update-contents;
+ };
+
+ u-boot {
+ };
+
+ section {
+ _testing2 {
+ type = "_testing";
+ bad-update-contents;
+ };
+ };
+ };
+};
diff --git a/tools/binman/test/124_compress_dtb.dts b/tools/binman/test/124_compress_dtb.dts
new file mode 100644
index 0000000..46bfd8b
--- /dev/null
+++ b/tools/binman/test/124_compress_dtb.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ u-boot {
+ };
+ u-boot-dtb {
+ compress = "lz4";
+ };
+ };
+};
diff --git a/tools/binman/test/125_cbfs_update.dts b/tools/binman/test/125_cbfs_update.dts
new file mode 100644
index 0000000..6d2e8a0
--- /dev/null
+++ b/tools/binman/test/125_cbfs_update.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ cbfs {
+ size = <0x100>;
+ u-boot {
+ cbfs-type = "raw";
+ cbfs-compress = "lz4";
+ };
+ u-boot-dtb {
+ cbfs-type = "raw";
+ };
+ };
+ };
+};
diff --git a/tools/binman/test/126_cbfs_bad_type.dts b/tools/binman/test/126_cbfs_bad_type.dts
new file mode 100644
index 0000000..2cd6fc6
--- /dev/null
+++ b/tools/binman/test/126_cbfs_bad_type.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ cbfs {
+ size = <0x100>;
+ u-boot {
+ cbfs-type = "badtype";
+ };
+ };
+ };
+};
diff --git a/tools/binman/test/127_list.dts b/tools/binman/test/127_list.dts
new file mode 100644
index 0000000..c1d6fce
--- /dev/null
+++ b/tools/binman/test/127_list.dts
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ u-boot {
+ };
+ section {
+ align = <0x100>;
+ cbfs {
+ size = <0x400>;
+ u-boot {
+ cbfs-type = "raw";
+ cbfs-offset = <0x38>;
+ };
+ u-boot-dtb {
+ type = "text";
+ text = "compress xxxxxxxxxxxxxxxxxxxxxx data";
+ cbfs-type = "raw";
+ cbfs-compress = "lzma";
+ cbfs-offset = <0x78>;
+ };
+ };
+ u-boot-dtb {
+ compress = "lz4";
+ };
+ };
+ };
+};
diff --git a/tools/binman/test/128_decode_image.dts b/tools/binman/test/128_decode_image.dts
new file mode 100644
index 0000000..449fccc
--- /dev/null
+++ b/tools/binman/test/128_decode_image.dts
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ size = <0xc00>;
+ u-boot {
+ };
+ section {
+ align = <0x100>;
+ cbfs {
+ size = <0x400>;
+ u-boot {
+ cbfs-type = "raw";
+ };
+ u-boot-dtb {
+ cbfs-type = "raw";
+ cbfs-compress = "lzma";
+ cbfs-offset = <0x80>;
+ };
+ };
+ u-boot-dtb {
+ compress = "lz4";
+ };
+ };
+ fdtmap {
+ };
+ image-header {
+ location = "end";
+ };
+ };
+};
diff --git a/tools/binman/test/129_decode_image_nohdr.dts b/tools/binman/test/129_decode_image_nohdr.dts
new file mode 100644
index 0000000..90fdd88
--- /dev/null
+++ b/tools/binman/test/129_decode_image_nohdr.dts
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ size = <0xc00>;
+ u-boot {
+ };
+ section {
+ align = <0x100>;
+ cbfs {
+ size = <0x400>;
+ u-boot {
+ cbfs-type = "raw";
+ };
+ u-boot-dtb {
+ cbfs-type = "raw";
+ cbfs-compress = "lzma";
+ cbfs-offset = <0x80>;
+ };
+ };
+ u-boot-dtb {
+ compress = "lz4";
+ };
+ };
+ fdtmap {
+ };
+ };
+};
diff --git a/tools/binman/test/130_list_fdtmap.dts b/tools/binman/test/130_list_fdtmap.dts
new file mode 100644
index 0000000..449fccc
--- /dev/null
+++ b/tools/binman/test/130_list_fdtmap.dts
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ size = <0xc00>;
+ u-boot {
+ };
+ section {
+ align = <0x100>;
+ cbfs {
+ size = <0x400>;
+ u-boot {
+ cbfs-type = "raw";
+ };
+ u-boot-dtb {
+ cbfs-type = "raw";
+ cbfs-compress = "lzma";
+ cbfs-offset = <0x80>;
+ };
+ };
+ u-boot-dtb {
+ compress = "lz4";
+ };
+ };
+ fdtmap {
+ };
+ image-header {
+ location = "end";
+ };
+ };
+};
diff --git a/tools/binman/test/131_pack_align_section.dts b/tools/binman/test/131_pack_align_section.dts
new file mode 100644
index 0000000..4447885
--- /dev/null
+++ b/tools/binman/test/131_pack_align_section.dts
@@ -0,0 +1,28 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ u-boot {
+ };
+ section0 {
+ type = "section";
+ align = <0x10>;
+ u-boot {
+ };
+ };
+ section1 {
+ type = "section";
+ align-size = <0x20>;
+ u-boot {
+ };
+ section2 {
+ type = "section";
+ u-boot {
+ };
+ };
+ };
+ };
+};
diff --git a/tools/binman/test/132_replace.dts b/tools/binman/test/132_replace.dts
new file mode 100644
index 0000000..6ebdcda
--- /dev/null
+++ b/tools/binman/test/132_replace.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ size = <0xc00>;
+ u-boot {
+ };
+ fdtmap {
+ };
+ u-boot-dtb {
+ };
+ image-header {
+ location = "end";
+ };
+ };
+};
diff --git a/tools/binman/test/133_replace_multi.dts b/tools/binman/test/133_replace_multi.dts
new file mode 100644
index 0000000..38b2f39
--- /dev/null
+++ b/tools/binman/test/133_replace_multi.dts
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ multiple-images;
+ first-image {
+ size = <0xc00>;
+ u-boot {
+ };
+ fdtmap {
+ };
+ u-boot-dtb {
+ };
+ image-header {
+ location = "end";
+ };
+ };
+
+ image {
+ fdtmap {
+ };
+ u-boot {
+ };
+ u-boot-dtb {
+ };
+ };
+ };
+};
diff --git a/tools/binman/test/134_fdt_update_all_repack.dts b/tools/binman/test/134_fdt_update_all_repack.dts
new file mode 100644
index 0000000..625d376
--- /dev/null
+++ b/tools/binman/test/134_fdt_update_all_repack.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ allow-repack;
+ section {
+ size = <0x300>;
+ u-boot-dtb {
+ offset = <4>;
+ };
+ };
+ u-boot-spl-dtb {
+ };
+ u-boot-tpl-dtb {
+ };
+ fdtmap {
+ };
+ };
+};
diff --git a/tools/binman/test/135_fdtmap_hdr_middle.dts b/tools/binman/test/135_fdtmap_hdr_middle.dts
new file mode 100644
index 0000000..d6211da
--- /dev/null
+++ b/tools/binman/test/135_fdtmap_hdr_middle.dts
@@ -0,0 +1,16 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ u-boot {
+ };
+ image-header {
+ location = "end";
+ };
+ fdtmap {
+ };
+ };
+};
diff --git a/tools/binman/test/136_fdtmap_hdr_startbad.dts b/tools/binman/test/136_fdtmap_hdr_startbad.dts
new file mode 100644
index 0000000..ec5f4bc
--- /dev/null
+++ b/tools/binman/test/136_fdtmap_hdr_startbad.dts
@@ -0,0 +1,16 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ u-boot {
+ };
+ fdtmap {
+ };
+ image-header {
+ location = "start";
+ };
+ };
+};
diff --git a/tools/binman/test/137_fdtmap_hdr_endbad.dts b/tools/binman/test/137_fdtmap_hdr_endbad.dts
new file mode 100644
index 0000000..ebacd71
--- /dev/null
+++ b/tools/binman/test/137_fdtmap_hdr_endbad.dts
@@ -0,0 +1,16 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ image-header {
+ location = "end";
+ };
+ u-boot {
+ };
+ fdtmap {
+ };
+ };
+};
diff --git a/tools/binman/test/138_fdtmap_hdr_nosize.dts b/tools/binman/test/138_fdtmap_hdr_nosize.dts
new file mode 100644
index 0000000..c362f8f
--- /dev/null
+++ b/tools/binman/test/138_fdtmap_hdr_nosize.dts
@@ -0,0 +1,16 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ u-boot {
+ };
+ fdtmap {
+ };
+ image-header {
+ location = "end";
+ };
+ };
+};
diff --git a/tools/binman/test/139_replace_repack.dts b/tools/binman/test/139_replace_repack.dts
new file mode 100644
index 0000000..a3daf6f
--- /dev/null
+++ b/tools/binman/test/139_replace_repack.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ size = <0xc00>;
+ allow-repack;
+ u-boot {
+ };
+ fdtmap {
+ };
+ u-boot-dtb {
+ };
+ image-header {
+ location = "end";
+ };
+ };
+};
diff --git a/tools/binman/test/140_entry_shrink.dts b/tools/binman/test/140_entry_shrink.dts
new file mode 100644
index 0000000..b750d63
--- /dev/null
+++ b/tools/binman/test/140_entry_shrink.dts
@@ -0,0 +1,20 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ _testing {
+ bad-shrink-contents;
+ };
+
+ u-boot {
+ };
+
+ _testing2 {
+ type = "_testing";
+ bad-shrink-contents;
+ };
+ };
+};
diff --git a/tools/binman/test/141_descriptor_offset.dts b/tools/binman/test/141_descriptor_offset.dts
new file mode 100644
index 0000000..f9bff01
--- /dev/null
+++ b/tools/binman/test/141_descriptor_offset.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ sort-by-offset;
+ end-at-4gb;
+ size = <0x800000>;
+ u-boot {
+ offset = <0xffff0000>;
+ };
+ intel-descriptor {
+ filename = "descriptor.bin";
+ };
+ };
+};
diff --git a/tools/binman/test/142_replace_cbfs.dts b/tools/binman/test/142_replace_cbfs.dts
new file mode 100644
index 0000000..d64142f
--- /dev/null
+++ b/tools/binman/test/142_replace_cbfs.dts
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ size = <0xe00>;
+ allow-repack;
+ u-boot {
+ };
+ section {
+ align = <0x100>;
+ cbfs {
+ size = <0x400>;
+ u-boot {
+ cbfs-type = "raw";
+ };
+ u-boot-dtb {
+ cbfs-type = "raw";
+ cbfs-compress = "lzma";
+ cbfs-offset = <0x80>;
+ };
+ };
+ u-boot-dtb {
+ compress = "lz4";
+ };
+ };
+ fdtmap {
+ };
+ image-header {
+ location = "end";
+ };
+ };
+};
diff --git a/tools/binman/test/143_replace_all.dts b/tools/binman/test/143_replace_all.dts
new file mode 100644
index 0000000..c5744a3
--- /dev/null
+++ b/tools/binman/test/143_replace_all.dts
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ size = <0xc00>;
+ allow-repack;
+ u-boot {
+ };
+ fdtmap {
+ };
+ u-boot2 {
+ type = "u-boot";
+ };
+ text {
+ text = "some text";
+ };
+ u-boot-dtb {
+ };
+ image-header {
+ location = "end";
+ };
+ };
+};
diff --git a/tools/binman/test/fitimage.bin.gz b/tools/binman/test/fitimage.bin.gz
new file mode 100644
index 0000000..0a9dcfc
--- /dev/null
+++ b/tools/binman/test/fitimage.bin.gz
Binary files differ
diff --git a/tools/binman/test/ifwi.bin.gz b/tools/binman/test/ifwi.bin.gz
new file mode 100644
index 0000000..25d7289
--- /dev/null
+++ b/tools/binman/test/ifwi.bin.gz
Binary files differ
diff --git a/tools/bmp_logo.c b/tools/bmp_logo.c
index 55f833f..74fcadc 100644
--- a/tools/bmp_logo.c
+++ b/tools/bmp_logo.c
@@ -2,7 +2,8 @@
enum {
MODE_GEN_INFO,
- MODE_GEN_DATA
+ MODE_GEN_DATA,
+ MODE_GEN_BMP
};
typedef struct bitmap_s { /* bitmap description */
@@ -16,7 +17,8 @@
void usage(const char *prog)
{
- fprintf(stderr, "Usage: %s [--gen-info|--gen-data] file\n", prog);
+ fprintf(stderr, "Usage: %s [--gen-info|--gen-data|--gen-bmp] file\n",
+ prog);
}
/*
@@ -73,6 +75,7 @@
int main (int argc, char *argv[])
{
int mode, i, x;
+ int size;
FILE *fp;
bitmap_t bmp;
bitmap_t *b = &bmp;
@@ -87,6 +90,8 @@
mode = MODE_GEN_INFO;
else if (!strcmp(argv[1], "--gen-data"))
mode = MODE_GEN_DATA;
+ else if (!strcmp(argv[1], "--gen-bmp"))
+ mode = MODE_GEN_BMP;
else {
usage(argv[0]);
exit(EXIT_FAILURE);
@@ -131,6 +136,7 @@
b->width = le_short(b->width);
b->height = le_short(b->height);
n_colors = le_short(n_colors);
+ size = b->width * b->height;
/* assume we are working with an 8-bit file */
if ((n_colors == 0) || (n_colors > 256 - DEFAULT_CMAP_SIZE)) {
@@ -152,10 +158,6 @@
"#ifndef __BMP_LOGO_DATA_H__\n"
"#define __BMP_LOGO_DATA_H__\n\n");
- /* allocate memory */
- if ((b->data = (uint8_t *)malloc(b->width * b->height)) == NULL)
- error ("Error allocating memory for file", fp);
-
/* read and print the palette information */
printf("unsigned short bmp_logo_palette[] = {\n");
@@ -175,21 +177,39 @@
}
/* seek to offset indicated by file header */
- fseek(fp, (long)data_offset, SEEK_SET);
+ if (mode == MODE_GEN_BMP) {
+ /* copy full bmp file */
+ fseek(fp, 0L, SEEK_END);
+ size = ftell(fp);
+ fseek(fp, 0L, SEEK_SET);
+ } else {
+ fseek(fp, (long)data_offset, SEEK_SET);
+ }
+
+ /* allocate memory */
+ b->data = (uint8_t *)malloc(size);
+ if (!b->data)
+ error("Error allocating memory for file", fp);
/* read the bitmap; leave room for default color map */
printf ("\n");
printf ("};\n");
printf ("\n");
printf("unsigned char bmp_logo_bitmap[] = {\n");
- for (i=(b->height-1)*b->width; i>=0; i-=b->width) {
- for (x = 0; x < b->width; x++) {
- b->data[i + x] = (uint8_t) fgetc(fp)
+ if (mode == MODE_GEN_BMP) {
+ /* write full bmp */
+ for (i = 0; i < size; i++)
+ b->data[i] = (uint8_t)fgetc(fp);
+ } else {
+ for (i = (b->height - 1) * b->width; i >= 0; i -= b->width) {
+ for (x = 0; x < b->width; x++) {
+ b->data[i + x] = (uint8_t)fgetc(fp)
+ DEFAULT_CMAP_SIZE;
+ }
}
}
- for (i=0; i<(b->height*b->width); ++i) {
+ for (i = 0; i < size; ++i) {
if ((i%8) == 0)
putchar ('\t');
printf ("0x%02X,%c",
diff --git a/tools/buildman/README b/tools/buildman/README
index 56a99c7..e366192 100644
--- a/tools/buildman/README
+++ b/tools/buildman/README
@@ -137,7 +137,7 @@
You can also use -x to specifically exclude some boards. For example:
- buildmand arm -x nvidia,freescale,.*ball$
+ buildman arm -x nvidia,freescale,.*ball$
means to build all arm boards except nvidia, freescale and anything ending
with 'ball'.
@@ -146,7 +146,7 @@
comma-separated list of board target names and be used multiple times on
the command line:
- buidman --boards sandbox,snow --boards
+ buildman --boards sandbox,snow --boards
It is convenient to use the -n option to see what will be built based on
the subset given. Use -v as well to get an actual list of boards.
diff --git a/tools/dtoc/dtb_platdata.py b/tools/dtoc/dtb_platdata.py
index 17a3dcc..037e82c 100644
--- a/tools/dtoc/dtb_platdata.py
+++ b/tools/dtoc/dtb_platdata.py
@@ -17,6 +17,7 @@
import fdt
import fdt_util
+import tools
# When we see these properties we ignore them - i.e. do not create a structure member
PROP_IGNORE_LIST = [
@@ -99,7 +100,7 @@
if ftype == fdt.TYPE_INT:
return '%#x' % fdt_util.fdt32_to_cpu(value)
elif ftype == fdt.TYPE_BYTE:
- return '%#x' % ord(value[0])
+ return '%#x' % tools.ToByte(value[0])
elif ftype == fdt.TYPE_STRING:
return '"%s"' % value
elif ftype == fdt.TYPE_BOOL:
@@ -449,7 +450,7 @@
self.out(';\n')
self.out('};\n')
- for alias, struct_name in self._aliases.iteritems():
+ for alias, struct_name in self._aliases.items():
if alias not in sorted(structs):
self.out('#define %s%s %s%s\n'% (STRUCT_PREFIX, alias,
STRUCT_PREFIX, struct_name))
@@ -464,7 +465,8 @@
var_name = conv_name_to_c(node.name)
self.buf('static const struct %s%s %s%s = {\n' %
(STRUCT_PREFIX, struct_name, VAL_PREFIX, var_name))
- for pname, prop in node.props.items():
+ for pname in sorted(node.props):
+ prop = node.props[pname]
if pname in PROP_IGNORE_LIST or pname[0] == '#':
continue
member_name = conv_name_to_c(prop.name)
@@ -498,7 +500,7 @@
vals.append(get_value(prop.type, val))
# Put 8 values per line to avoid very long lines.
- for i in xrange(0, len(vals), 8):
+ for i in range(0, len(vals), 8):
if i:
self.buf(',\n\t\t')
self.buf(', '.join(vals[i:i + 8]))
diff --git a/tools/dtoc/dtoc.py b/tools/dtoc/dtoc.py
index 2277af9..514e0dd 100755
--- a/tools/dtoc/dtoc.py
+++ b/tools/dtoc/dtoc.py
@@ -25,6 +25,8 @@
see doc/driver-model/of-plat.txt
"""
+from __future__ import print_function
+
from optparse import OptionParser
import os
import sys
@@ -64,11 +66,15 @@
suite = unittest.TestLoader().loadTestsFromTestCase(module)
suite.run(result)
- print result
+ print(result)
for _, err in result.errors:
- print err
+ print(err)
for _, err in result.failures:
- print err
+ print(err)
+ if result.errors or result.failures:
+ print('dtoc tests FAILED')
+ return 1
+ return 0
def RunTestCoverage():
"""Run the tests and check that we get 100% coverage"""
@@ -99,7 +105,8 @@
# Run our meagre tests
if options.test:
- run_tests(args)
+ ret_code = run_tests(args)
+ sys.exit(ret_code)
elif options.test_coverage:
RunTestCoverage()
diff --git a/tools/dtoc/fdt.py b/tools/dtoc/fdt.py
index 9ad72f8..6770be7 100644
--- a/tools/dtoc/fdt.py
+++ b/tools/dtoc/fdt.py
@@ -11,6 +11,7 @@
import fdt_util
import libfdt
from libfdt import QUIET_NOTFOUND
+import tools
# This deals with a device tree, presenting it as an assortment of Node and
# Prop objects, representing nodes and properties, respectively. This file
@@ -28,6 +29,66 @@
raise ValueError('Error %d: %s: %s' %
(errnum, libfdt.fdt_strerror(errnum), msg))
+
+def BytesToValue(data):
+ """Converts a string of bytes into a type and value
+
+ Args:
+ A bytes value (which on Python 2 is an alias for str)
+
+ Return:
+ A tuple:
+ Type of data
+ Data, either a single element or a list of elements. Each element
+ is one of:
+ TYPE_STRING: str/bytes value from the property
+ TYPE_INT: a byte-swapped integer stored as a 4-byte str/bytes
+ TYPE_BYTE: a byte stored as a single-byte str/bytes
+ """
+ data = bytes(data)
+ size = len(data)
+ strings = data.split(b'\0')
+ is_string = True
+ count = len(strings) - 1
+ if count > 0 and not len(strings[-1]):
+ for string in strings[:-1]:
+ if not string:
+ is_string = False
+ break
+ for ch in string:
+ # Handle Python 2 treating bytes as str
+ if type(ch) == str:
+ ch = ord(ch)
+ if ch < 32 or ch > 127:
+ is_string = False
+ break
+ else:
+ is_string = False
+ if is_string:
+ if count == 1:
+ if sys.version_info[0] >= 3: # pragma: no cover
+ return TYPE_STRING, strings[0].decode()
+ else:
+ return TYPE_STRING, strings[0]
+ else:
+ if sys.version_info[0] >= 3: # pragma: no cover
+ return TYPE_STRING, [s.decode() for s in strings[:-1]]
+ else:
+ return TYPE_STRING, strings[:-1]
+ if size % 4:
+ if size == 1:
+ return TYPE_BYTE, tools.ToChar(data[0])
+ else:
+ return TYPE_BYTE, [tools.ToChar(ch) for ch in list(data)]
+ val = []
+ for i in range(0, size, 4):
+ val.append(data[i:i + 4])
+ if size == 4:
+ return TYPE_INT, val[0]
+ else:
+ return TYPE_INT, val
+
+
class Prop:
"""A device tree property
@@ -37,18 +98,18 @@
bytes
type: Value type
"""
- def __init__(self, node, offset, name, bytes):
+ def __init__(self, node, offset, name, data):
self._node = node
self._offset = offset
self.name = name
self.value = None
- self.bytes = str(bytes)
+ self.bytes = bytes(data)
self.dirty = False
- if not bytes:
+ if not data:
self.type = TYPE_BOOL
self.value = True
return
- self.type, self.value = self.BytesToValue(bytes)
+ self.type, self.value = BytesToValue(bytes(data))
def RefreshOffset(self, poffset):
self._offset = poffset
@@ -87,55 +148,6 @@
while len(self.value) < len(newprop.value):
self.value.append(val)
- def BytesToValue(self, bytes):
- """Converts a string of bytes into a type and value
-
- Args:
- A string containing bytes
-
- Return:
- A tuple:
- Type of data
- Data, either a single element or a list of elements. Each element
- is one of:
- TYPE_STRING: string value from the property
- TYPE_INT: a byte-swapped integer stored as a 4-byte string
- TYPE_BYTE: a byte stored as a single-byte string
- """
- bytes = str(bytes)
- size = len(bytes)
- strings = bytes.split('\0')
- is_string = True
- count = len(strings) - 1
- if count > 0 and not strings[-1]:
- for string in strings[:-1]:
- if not string:
- is_string = False
- break
- for ch in string:
- if ch < ' ' or ch > '~':
- is_string = False
- break
- else:
- is_string = False
- if is_string:
- if count == 1:
- return TYPE_STRING, strings[0]
- else:
- return TYPE_STRING, strings[:-1]
- if size % 4:
- if size == 1:
- return TYPE_BYTE, bytes[0]
- else:
- return TYPE_BYTE, list(bytes)
- val = []
- for i in range(0, size, 4):
- val.append(bytes[i:i + 4])
- if size == 4:
- return TYPE_INT, val[0]
- else:
- return TYPE_INT, val
-
@classmethod
def GetEmpty(self, type):
"""Get an empty / zero value of the given type
@@ -181,8 +193,8 @@
Args:
bytes: New property value to set
"""
- self.bytes = str(bytes)
- self.type, self.value = self.BytesToValue(bytes)
+ self.bytes = bytes
+ self.type, self.value = BytesToValue(bytes)
self.dirty = True
def Sync(self, auto_resize=False):
@@ -334,7 +346,8 @@
Args:
prop_name: Name of property
"""
- self.props[prop_name] = Prop(self, None, prop_name, '\0' * 4)
+ self.props[prop_name] = Prop(self, None, prop_name,
+ tools.GetBytes(0, 4))
def AddEmptyProp(self, prop_name, len):
"""Add a property with a fixed data size, for filling in later
@@ -346,9 +359,26 @@
prop_name: Name of property
len: Length of data in property
"""
- value = chr(0) * len
+ value = tools.GetBytes(0, len)
self.props[prop_name] = Prop(self, None, prop_name, value)
+ def _CheckProp(self, prop_name):
+ """Check if a property is present
+
+ Args:
+ prop_name: Name of property
+
+ Returns:
+ self
+
+ Raises:
+ ValueError if the property is missing
+ """
+ if prop_name not in self.props:
+ raise ValueError("Fdt '%s', node '%s': Missing property '%s'" %
+ (self._fdt._fname, self.path, prop_name))
+ return self
+
def SetInt(self, prop_name, val):
"""Update an integer property int the device tree.
@@ -361,7 +391,7 @@
prop_name: Name of property
val: Value to set
"""
- self.props[prop_name].SetInt(val)
+ self._CheckProp(prop_name).props[prop_name].SetInt(val)
def SetData(self, prop_name, val):
"""Set the data value of a property
@@ -373,7 +403,7 @@
prop_name: Name of property to set
val: Data value to set
"""
- self.props[prop_name].SetData(val)
+ self._CheckProp(prop_name).props[prop_name].SetData(val)
def SetString(self, prop_name, val):
"""Set the string value of a property
@@ -385,7 +415,9 @@
prop_name: Name of property to set
val: String value to set (will be \0-terminated in DT)
"""
- self.props[prop_name].SetData(val + chr(0))
+ if sys.version_info[0] >= 3: # pragma: no cover
+ val = bytes(val, 'utf-8')
+ self._CheckProp(prop_name).props[prop_name].SetData(val + b'\0')
def AddString(self, prop_name, val):
"""Add a new string property to a node
@@ -397,7 +429,9 @@
prop_name: Name of property to add
val: String value of property
"""
- self.props[prop_name] = Prop(self, None, prop_name, val + chr(0))
+ if sys.version_info[0] >= 3: # pragma: no cover
+ val = bytes(val, 'utf-8')
+ self.props[prop_name] = Prop(self, None, prop_name, val + b'\0')
def AddSubnode(self, name):
"""Add a new subnode to the node
@@ -448,8 +482,11 @@
# Sync properties now, whose offsets should not have been disturbed.
# We do this after subnodes, since this disturbs the offsets of these
- # properties.
- prop_list = sorted(self.props.values(), key=lambda prop: prop._offset,
+ # properties. Note that new properties will have an offset of None here,
+ # which Python 3 cannot sort against int. So use a large value instead
+ # to ensure that the new properties are added first.
+ prop_list = sorted(self.props.values(),
+ key=lambda prop: prop._offset or 1 << 31,
reverse=True)
for prop in prop_list:
prop.Sync(auto_resize)
@@ -461,29 +498,35 @@
Properties:
fname: Filename of fdt
_root: Root of device tree (a Node object)
+ name: Helpful name for this Fdt for the user (useful when creating the
+ DT from data rather than a file)
"""
def __init__(self, fname):
self._fname = fname
self._cached_offsets = False
self.phandle_to_node = {}
+ self.name = ''
if self._fname:
+ self.name = self._fname
self._fname = fdt_util.EnsureCompiled(self._fname)
- with open(self._fname) as fd:
+ with open(self._fname, 'rb') as fd:
self._fdt_obj = libfdt.Fdt(fd.read())
@staticmethod
- def FromData(data):
+ def FromData(data, name=''):
"""Create a new Fdt object from the given data
Args:
data: Device-tree data blob
+ name: Helpful name for this Fdt for the user
Returns:
Fdt object containing the data
"""
fdt = Fdt(None)
- fdt._fdt_obj = libfdt.Fdt(bytearray(data))
+ fdt._fdt_obj = libfdt.Fdt(bytes(data))
+ fdt.name = name
return fdt
def LookupPhandle(self, phandle):
@@ -531,6 +574,8 @@
parts = path.split('/')
if len(parts) < 2:
return None
+ if len(parts) == 2 and parts[1] == '':
+ return node
for part in parts[1:]:
node = node.FindNode(part)
if not node:
@@ -573,7 +618,7 @@
Returns:
The FDT contents as a string of bytes
"""
- return self._fdt_obj.as_bytearray()
+ return bytes(self._fdt_obj.as_bytearray())
def GetFdtObj(self):
"""Get the contents of the FDT
@@ -650,6 +695,14 @@
node = Node(fdt, parent, offset, name, path)
return node
+ def GetFilename(self):
+ """Get the filename of the device tree
+
+ Returns:
+ String filename
+ """
+ return self._fname
+
def FdtScan(fname):
"""Returns a new Fdt object"""
dtb = Fdt(fname)
diff --git a/tools/dtoc/fdt_util.py b/tools/dtoc/fdt_util.py
index 5fbfc88..b105fae 100644
--- a/tools/dtoc/fdt_util.py
+++ b/tools/dtoc/fdt_util.py
@@ -16,14 +16,6 @@
import command
import tools
-VERSION3 = sys.version_info > (3, 0)
-
-def get_plain_bytes(val):
- """Handle Python 3 strings"""
- if isinstance(val, bytes):
- val = val.decode('utf-8')
- return val.encode('raw_unicode_escape')
-
def fdt32_to_cpu(val):
"""Convert a device tree cell to an integer
@@ -33,9 +25,6 @@
Return:
A native-endian integer value
"""
- if VERSION3:
- # This code is not reached in Python 2
- val = get_plain_bytes(val) # pragma: no cover
return struct.unpack('>I', val)[0]
def fdt_cells_to_cpu(val, cells):
@@ -45,21 +34,23 @@
Value to convert (array of one or more 4-character strings)
Return:
- A native-endian long value
+ A native-endian integer value
"""
if not cells:
return 0
- out = long(fdt32_to_cpu(val[0]))
+ out = int(fdt32_to_cpu(val[0]))
if cells == 2:
out = out << 32 | fdt32_to_cpu(val[1])
return out
-def EnsureCompiled(fname, capture_stderr=False):
+def EnsureCompiled(fname, tmpdir=None, capture_stderr=False):
"""Compile an fdt .dts source file into a .dtb binary blob if needed.
Args:
fname: Filename (if .dts it will be compiled). It not it will be
left alone
+ tmpdir: Temporary directory for output files, or None to use the
+ tools-module output directory
Returns:
Filename of resulting .dtb file
@@ -68,8 +59,12 @@
if ext != '.dts':
return fname
- dts_input = tools.GetOutputFilename('source.dts')
- dtb_output = tools.GetOutputFilename('source.dtb')
+ if tmpdir:
+ dts_input = os.path.join(tmpdir, 'source.dts')
+ dtb_output = os.path.join(tmpdir, 'source.dtb')
+ else:
+ dts_input = tools.GetOutputFilename('source.dts')
+ dtb_output = tools.GetOutputFilename('source.dtb')
search_paths = [os.path.join(os.getcwd(), 'include')]
root, _ = os.path.splitext(fname)
diff --git a/tools/dtoc/test_dtoc.py b/tools/dtoc/test_dtoc.py
index cb6d6e7..b915b27 100644
--- a/tools/dtoc/test_dtoc.py
+++ b/tools/dtoc/test_dtoc.py
@@ -8,6 +8,8 @@
tool.
"""
+from __future__ import print_function
+
import collections
import os
import struct
@@ -97,7 +99,7 @@
if expected != actual:
self._WritePythonString('/tmp/binman.expected', expected)
self._WritePythonString('/tmp/binman.actual', actual)
- print 'Failures written to /tmp/binman.{expected,actual}'
+ print('Failures written to /tmp/binman.{expected,actual}')
self.assertEquals(expected, actual)
def test_name(self):
@@ -197,16 +199,16 @@
data = infile.read()
self._CheckStrings(C_HEADER + '''
static const struct dtd_sandbox_spl_test dtv_spl_test = {
+\t.boolval\t\t= true,
\t.bytearray\t\t= {0x6, 0x0, 0x0},
\t.byteval\t\t= 0x5,
+\t.intarray\t\t= {0x2, 0x3, 0x4, 0x0},
\t.intval\t\t\t= 0x1,
-\t.notstring\t\t= {0x20, 0x21, 0x22, 0x10, 0x0},
\t.longbytearray\t\t= {0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x10,
\t\t0x11},
-\t.stringval\t\t= "message",
-\t.boolval\t\t= true,
-\t.intarray\t\t= {0x2, 0x3, 0x4, 0x0},
+\t.notstring\t\t= {0x20, 0x21, 0x22, 0x10, 0x0},
\t.stringarray\t\t= {"multi-word", "message", ""},
+\t.stringval\t\t= "message",
};
U_BOOT_DEVICE(spl_test) = {
\t.name\t\t= "sandbox_spl_test",
@@ -217,12 +219,12 @@
static const struct dtd_sandbox_spl_test dtv_spl_test2 = {
\t.bytearray\t\t= {0x1, 0x23, 0x34},
\t.byteval\t\t= 0x8,
+\t.intarray\t\t= {0x5, 0x0, 0x0, 0x0},
\t.intval\t\t\t= 0x3,
\t.longbytearray\t\t= {0x9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
\t\t0x0},
-\t.stringval\t\t= "message2",
-\t.intarray\t\t= {0x5, 0x0, 0x0, 0x0},
\t.stringarray\t\t= {"another", "multi-word", "message"},
+\t.stringval\t\t= "message2",
};
U_BOOT_DEVICE(spl_test2) = {
\t.name\t\t= "sandbox_spl_test",
diff --git a/tools/dtoc/test_fdt.py b/tools/dtoc/test_fdt.py
index 8d70dd2..028c8cb 100755
--- a/tools/dtoc/test_fdt.py
+++ b/tools/dtoc/test_fdt.py
@@ -4,10 +4,14 @@
# Written by Simon Glass <sjg@chromium.org>
#
+from __future__ import print_function
+
from optparse import OptionParser
import glob
import os
+import shutil
import sys
+import tempfile
import unittest
# Bring in the patman libraries
@@ -17,7 +21,7 @@
import command
import fdt
-from fdt import TYPE_BYTE, TYPE_INT, TYPE_STRING, TYPE_BOOL
+from fdt import TYPE_BYTE, TYPE_INT, TYPE_STRING, TYPE_BOOL, BytesToValue
import fdt_util
from fdt_util import fdt32_to_cpu
import libfdt
@@ -45,7 +49,7 @@
# Add 12, which is sizeof(struct fdt_property), to get to start of data
offset = prop.GetOffset() + 12
data = dtb.GetContents()[offset:offset + len(prop.value)]
- return prop, [chr(x) for x in data]
+ return prop, [tools.ToChar(x) for x in data]
class TestFdt(unittest.TestCase):
@@ -75,21 +79,26 @@
"""Test the GetNode() method"""
node = self.dtb.GetNode('/spl-test')
self.assertTrue(isinstance(node, fdt.Node))
+
node = self.dtb.GetNode('/i2c@0/pmic@9')
self.assertTrue(isinstance(node, fdt.Node))
self.assertEqual('pmic@9', node.name)
self.assertIsNone(self.dtb.GetNode('/i2c@0/pmic@9/missing'))
+ node = self.dtb.GetNode('/')
+ self.assertTrue(isinstance(node, fdt.Node))
+ self.assertEqual(0, node.Offset())
+
def testFlush(self):
"""Check that we can flush the device tree out to its file"""
fname = self.dtb._fname
- with open(fname) as fd:
+ with open(fname, 'rb') as fd:
data = fd.read()
os.remove(fname)
with self.assertRaises(IOError):
- open(fname)
+ open(fname, 'rb')
self.dtb.Flush()
- with open(fname) as fd:
+ with open(fname, 'rb') as fd:
data = fd.read()
def testPack(self):
@@ -119,6 +128,10 @@
node = self.dtb.GetNode('/spl-test')
self.assertEqual(self.dtb, node.GetFdt())
+ def testBytesToValue(self):
+ self.assertEqual(BytesToValue(b'this\0is\0'),
+ (TYPE_STRING, ['this', 'is']))
+
class TestNode(unittest.TestCase):
"""Test operation of the Node class"""
@@ -277,7 +290,7 @@
"""Tests the GetEmpty() function for the various supported types"""
self.assertEqual(True, fdt.Prop.GetEmpty(fdt.TYPE_BOOL))
self.assertEqual(chr(0), fdt.Prop.GetEmpty(fdt.TYPE_BYTE))
- self.assertEqual(chr(0) * 4, fdt.Prop.GetEmpty(fdt.TYPE_INT))
+ self.assertEqual(tools.GetBytes(0, 4), fdt.Prop.GetEmpty(fdt.TYPE_INT))
self.assertEqual('', fdt.Prop.GetEmpty(fdt.TYPE_STRING))
def testGetOffset(self):
@@ -381,7 +394,7 @@
self.node.AddString('string', val)
self.dtb.Sync(auto_resize=True)
data = self.fdt.getprop(self.node.Offset(), 'string')
- self.assertEqual(val + '\0', data)
+ self.assertEqual(tools.ToBytes(val) + b'\0', data)
self.fdt.pack()
self.node.SetString('string', val + 'x')
@@ -391,21 +404,21 @@
self.node.SetString('string', val[:-1])
prop = self.node.props['string']
- prop.SetData(val)
+ prop.SetData(tools.ToBytes(val))
self.dtb.Sync(auto_resize=False)
data = self.fdt.getprop(self.node.Offset(), 'string')
- self.assertEqual(val, data)
+ self.assertEqual(tools.ToBytes(val), data)
self.node.AddEmptyProp('empty', 5)
self.dtb.Sync(auto_resize=True)
prop = self.node.props['empty']
- prop.SetData(val)
+ prop.SetData(tools.ToBytes(val))
self.dtb.Sync(auto_resize=False)
data = self.fdt.getprop(self.node.Offset(), 'empty')
- self.assertEqual(val, data)
+ self.assertEqual(tools.ToBytes(val), data)
- self.node.SetData('empty', '123')
- self.assertEqual('123', prop.bytes)
+ self.node.SetData('empty', b'123')
+ self.assertEqual(b'123', prop.bytes)
def testFromData(self):
dtb2 = fdt.Fdt.FromData(self.dtb.GetContents())
@@ -415,6 +428,32 @@
self.dtb.Sync(auto_resize=True)
self.assertTrue(dtb2.GetContents() != self.dtb.GetContents())
+ def testMissingSetInt(self):
+ """Test handling of a missing property with SetInt"""
+ with self.assertRaises(ValueError) as e:
+ self.node.SetInt('one', 1)
+ self.assertIn("node '/spl-test': Missing property 'one'",
+ str(e.exception))
+
+ def testMissingSetData(self):
+ """Test handling of a missing property with SetData"""
+ with self.assertRaises(ValueError) as e:
+ self.node.SetData('one', b'data')
+ self.assertIn("node '/spl-test': Missing property 'one'",
+ str(e.exception))
+
+ def testMissingSetString(self):
+ """Test handling of a missing property with SetString"""
+ with self.assertRaises(ValueError) as e:
+ self.node.SetString('one', 1)
+ self.assertIn("node '/spl-test': Missing property 'one'",
+ str(e.exception))
+
+ def testGetFilename(self):
+ """Test the dtb filename can be provided"""
+ self.assertEqual(tools.GetOutputFilename('source.dtb'),
+ self.dtb.GetFilename())
+
class TestFdtUtil(unittest.TestCase):
"""Tests for the fdt_util module
@@ -496,17 +535,34 @@
self.assertEqual(2, fdt_util.fdt_cells_to_cpu(val, 1))
dtb2 = fdt.FdtScan('tools/dtoc/dtoc_test_addr64.dts')
- node2 = dtb2.GetNode('/test1')
- val = node2.props['reg'].value
+ node1 = dtb2.GetNode('/test1')
+ val = node1.props['reg'].value
self.assertEqual(0x1234, fdt_util.fdt_cells_to_cpu(val, 2))
+ node2 = dtb2.GetNode('/test2')
+ val = node2.props['reg'].value
+ self.assertEqual(0x1234567890123456, fdt_util.fdt_cells_to_cpu(val, 2))
+ self.assertEqual(0x9876543210987654, fdt_util.fdt_cells_to_cpu(val[2:],
+ 2))
+ self.assertEqual(0x12345678, fdt_util.fdt_cells_to_cpu(val, 1))
+
def testEnsureCompiled(self):
- """Test a degenerate case of this function"""
+ """Test a degenerate case of this function (file already compiled)"""
dtb = fdt_util.EnsureCompiled('tools/dtoc/dtoc_test_simple.dts')
self.assertEqual(dtb, fdt_util.EnsureCompiled(dtb))
- def testGetPlainBytes(self):
- self.assertEqual('fred', fdt_util.get_plain_bytes('fred'))
+ def testEnsureCompiledTmpdir(self):
+ """Test providing a temporary directory"""
+ try:
+ old_outdir = tools.outdir
+ tools.outdir= None
+ tmpdir = tempfile.mkdtemp(prefix='test_fdt.')
+ dtb = fdt_util.EnsureCompiled('tools/dtoc/dtoc_test_simple.dts',
+ tmpdir)
+ self.assertEqual(tmpdir, os.path.dirname(dtb))
+ shutil.rmtree(tmpdir)
+ finally:
+ tools.outdir= old_outdir
def RunTestCoverage():
@@ -535,11 +591,11 @@
suite = unittest.TestLoader().loadTestsFromTestCase(module)
suite.run(result)
- print result
+ print(result)
for _, err in result.errors:
- print err
+ print(err)
for _, err in result.failures:
- print err
+ print(err)
if __name__ != '__main__':
sys.exit(1)
diff --git a/tools/easylogo/Makefile b/tools/easylogo/Makefile
deleted file mode 100644
index 9278837..0000000
--- a/tools/easylogo/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-
-hostprogs-y := easylogo
-
-always := $(hostprogs-y)
diff --git a/tools/easylogo/easylogo.c b/tools/easylogo/easylogo.c
deleted file mode 100644
index 4ba86bf..0000000
--- a/tools/easylogo/easylogo.c
+++ /dev/null
@@ -1,610 +0,0 @@
-/*
-** Easylogo TGA->header converter
-** ==============================
-** (C) 2000 by Paolo Scaffardi (arsenio@tin.it)
-** AIRVENT SAM s.p.a - RIMINI(ITALY)
-** (C) 2007-2008 Mike Frysinger <vapier@gentoo.org>
-**
-** This is still under construction!
-*/
-
-#include <errno.h>
-#include <getopt.h>
-#include <stdbool.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
-#include <sys/stat.h>
-
-#pragma pack(1)
-
-/*#define ENABLE_ASCII_BANNERS */
-
-typedef struct {
- unsigned char id;
- unsigned char ColorMapType;
- unsigned char ImageTypeCode;
- unsigned short ColorMapOrigin;
- unsigned short ColorMapLenght;
- unsigned char ColorMapEntrySize;
- unsigned short ImageXOrigin;
- unsigned short ImageYOrigin;
- unsigned short ImageWidth;
- unsigned short ImageHeight;
- unsigned char ImagePixelSize;
- unsigned char ImageDescriptorByte;
-} tga_header_t;
-
-typedef struct {
- unsigned char r, g, b;
-} rgb_t;
-
-typedef struct {
- unsigned char b, g, r;
-} bgr_t;
-
-typedef struct {
- unsigned char Cb, y1, Cr, y2;
-} yuyv_t;
-
-typedef struct {
- void *data, *palette;
- int width, height, pixels, bpp, pixel_size, size, palette_size, yuyv;
-} image_t;
-
-void *xmalloc (size_t size)
-{
- void *ret = malloc (size);
- if (!ret) {
- fprintf (stderr, "\nerror: malloc(%zu) failed: %s",
- size, strerror(errno));
- exit (1);
- }
- return ret;
-}
-
-void StringUpperCase (char *str)
-{
- int count = strlen (str);
- char c;
-
- while (count--) {
- c = *str;
- if ((c >= 'a') && (c <= 'z'))
- *str = 'A' + (c - 'a');
- str++;
- }
-}
-
-void StringLowerCase (char *str)
-{
- int count = strlen (str);
- char c;
-
- while (count--) {
- c = *str;
- if ((c >= 'A') && (c <= 'Z'))
- *str = 'a' + (c - 'A');
- str++;
- }
-}
-void pixel_rgb_to_yuyv (rgb_t * rgb_pixel, yuyv_t * yuyv_pixel)
-{
- unsigned int pR, pG, pB;
-
- /* Transform (0-255) components to (0-100) */
- pR = rgb_pixel->r * 100 / 255;
- pG = rgb_pixel->g * 100 / 255;
- pB = rgb_pixel->b * 100 / 255;
-
- /* Calculate YUV values (0-255) from RGB beetween 0-100 */
- yuyv_pixel->y1 = yuyv_pixel->y2 = 209 * (pR + pG + pB) / 300 + 16;
- yuyv_pixel->Cb = pB - (pR / 4) - (pG * 3 / 4) + 128;
- yuyv_pixel->Cr = pR - (pG * 3 / 4) - (pB / 4) + 128;
-
- return;
-}
-
-void printlogo_rgb (rgb_t * data, int w, int h)
-{
- int x, y;
-
- for (y = 0; y < h; y++) {
- for (x = 0; x < w; x++, data++)
- if ((data->r <
- 30) /*&&(data->g == 0)&&(data->b == 0) */ )
- printf (" ");
- else
- printf ("X");
- printf ("\n");
- }
-}
-
-void printlogo_yuyv (unsigned short *data, int w, int h)
-{
- int x, y;
-
- for (y = 0; y < h; y++) {
- for (x = 0; x < w; x++, data++)
- if (*data == 0x1080) /* Because of inverted on i386! */
- printf (" ");
- else
- printf ("X");
- printf ("\n");
- }
-}
-
-static inline unsigned short le16_to_cpu (unsigned short val)
-{
- union {
- unsigned char pval[2];
- unsigned short val;
- } swapped;
-
- swapped.val = val;
- return (swapped.pval[1] << 8) + swapped.pval[0];
-}
-
-int image_load_tga (image_t * image, char *filename)
-{
- FILE *file;
- tga_header_t header;
- int i;
- unsigned char app;
- rgb_t *p;
-
- if ((file = fopen (filename, "rb")) == NULL)
- return -1;
-
- fread (&header, sizeof (header), 1, file);
-
- /* byte swap: tga is little endian, host is ??? */
- header.ColorMapOrigin = le16_to_cpu (header.ColorMapOrigin);
- header.ColorMapLenght = le16_to_cpu (header.ColorMapLenght);
- header.ImageXOrigin = le16_to_cpu (header.ImageXOrigin);
- header.ImageYOrigin = le16_to_cpu (header.ImageYOrigin);
- header.ImageWidth = le16_to_cpu (header.ImageWidth);
- header.ImageHeight = le16_to_cpu (header.ImageHeight);
-
- image->width = header.ImageWidth;
- image->height = header.ImageHeight;
-
- switch (header.ImageTypeCode) {
- case 2: /* Uncompressed RGB */
- image->yuyv = 0;
- image->palette_size = 0;
- image->palette = NULL;
- break;
-
- default:
- printf ("Format not supported!\n");
- return -1;
- }
-
- image->bpp = header.ImagePixelSize;
- image->pixel_size = ((image->bpp - 1) / 8) + 1;
- image->pixels = image->width * image->height;
- image->size = image->pixels * image->pixel_size;
- image->data = xmalloc (image->size);
-
- if (image->bpp != 24) {
- printf ("Bpp not supported: %d!\n", image->bpp);
- return -1;
- }
-
- fread (image->data, image->size, 1, file);
-
-/* Swapping R and B values */
-
- p = image->data;
- for (i = 0; i < image->pixels; i++, p++) {
- app = p->r;
- p->r = p->b;
- p->b = app;
- }
-
-/* Swapping image */
-
- if (!(header.ImageDescriptorByte & 0x20)) {
- unsigned char *temp = xmalloc (image->size);
- int linesize = image->pixel_size * image->width;
- void *dest = image->data,
- *source = temp + image->size - linesize;
-
- printf ("S");
- if (temp == NULL) {
- printf ("Cannot alloc temp buffer!\n");
- return -1;
- }
-
- memcpy (temp, image->data, image->size);
- for (i = 0; i < image->height;
- i++, dest += linesize, source -= linesize)
- memcpy (dest, source, linesize);
-
- free (temp);
- }
-#ifdef ENABLE_ASCII_BANNERS
- printlogo_rgb (image->data, image->width, image->height);
-#endif
-
- fclose (file);
- return 0;
-}
-
-void image_free (image_t * image)
-{
- free (image->data);
- free (image->palette);
-}
-
-int image_rgb_to_yuyv (image_t * rgb_image, image_t * yuyv_image)
-{
- rgb_t *rgb_ptr = (rgb_t *) rgb_image->data;
- yuyv_t yuyv;
- unsigned short *dest;
- int count = 0;
-
- yuyv_image->pixel_size = 2;
- yuyv_image->bpp = 16;
- yuyv_image->yuyv = 1;
- yuyv_image->width = rgb_image->width;
- yuyv_image->height = rgb_image->height;
- yuyv_image->pixels = yuyv_image->width * yuyv_image->height;
- yuyv_image->size = yuyv_image->pixels * yuyv_image->pixel_size;
- dest = (unsigned short *) (yuyv_image->data =
- xmalloc (yuyv_image->size));
- yuyv_image->palette = 0;
- yuyv_image->palette_size = 0;
-
- while ((count++) < rgb_image->pixels) {
- pixel_rgb_to_yuyv (rgb_ptr++, &yuyv);
-
- if ((count & 1) == 0) /* Was == 0 */
- memcpy (dest, ((void *) &yuyv) + 2, sizeof (short));
- else
- memcpy (dest, (void *) &yuyv, sizeof (short));
-
- dest++;
- }
-
-#ifdef ENABLE_ASCII_BANNERS
- printlogo_yuyv (yuyv_image->data, yuyv_image->width,
- yuyv_image->height);
-#endif
- return 0;
-}
-
-int image_rgb888_to_rgb565(image_t *rgb888_image, image_t *rgb565_image)
-{
- rgb_t *rgb_ptr = (rgb_t *) rgb888_image->data;
- unsigned short *dest;
- int count = 0;
-
- rgb565_image->pixel_size = 2;
- rgb565_image->bpp = 16;
- rgb565_image->yuyv = 0;
- rgb565_image->width = rgb888_image->width;
- rgb565_image->height = rgb888_image->height;
- rgb565_image->pixels = rgb565_image->width * rgb565_image->height;
- rgb565_image->size = rgb565_image->pixels * rgb565_image->pixel_size;
- dest = (unsigned short *) (rgb565_image->data =
- xmalloc(rgb565_image->size));
- rgb565_image->palette = 0;
- rgb565_image->palette_size = 0;
-
- while ((count++) < rgb888_image->pixels) {
-
- *dest++ = ((rgb_ptr->b & 0xF8) << 8) |
- ((rgb_ptr->g & 0xFC) << 3) |
- (rgb_ptr->r >> 3);
- rgb_ptr++;
- }
-
- return 0;
-}
-
-enum comp_t {
- COMP_NONE,
- COMP_GZIP,
- COMP_LZMA,
-};
-static enum comp_t compression = COMP_NONE;
-static bool bss_storage = false;
-
-int image_save_header (image_t * image, char *filename, char *varname)
-{
- FILE *file = fopen (filename, "w");
- char app[256], str[256] = "", def_name[64];
- int count = image->size, col = 0;
- unsigned char *dataptr = image->data;
-
- if (file == NULL)
- return -1;
-
- /* Author information */
- fprintf (file,
- "/*\n * Generated by EasyLogo, (C) 2000 by Paolo Scaffardi\n *\n");
- fprintf (file,
- " * To use this, include it and call: easylogo_plot(screen,&%s, width,x,y)\n *\n",
- varname);
- fprintf (file,
- " * Where:\t'screen'\tis the pointer to the frame buffer\n");
- fprintf (file, " *\t\t'width'\tis the screen width\n");
- fprintf (file, " *\t\t'x'\t\tis the horizontal position\n");
- fprintf (file, " *\t\t'y'\t\tis the vertical position\n */\n\n");
-
- /* image compress */
- if (compression != COMP_NONE) {
- const char *errstr = NULL;
- unsigned char *compressed;
- const char *comp_name;
- struct stat st;
- FILE *compfp;
- size_t filename_len = strlen(filename);
- char *compfilename = xmalloc(filename_len + 20);
- char *compcmd = xmalloc(filename_len + 50);
-
- sprintf(compfilename, "%s.bin", filename);
- switch (compression) {
- case COMP_GZIP:
- strcpy(compcmd, "gzip");
- comp_name = "GZIP";
- break;
- case COMP_LZMA:
- strcpy(compcmd, "lzma");
- comp_name = "LZMA";
- break;
- default:
- errstr = "\nerror: unknown compression method";
- goto done;
- }
- strcat(compcmd, " > ");
- strcat(compcmd, compfilename);
- compfp = popen(compcmd, "w");
- if (!compfp) {
- errstr = "\nerror: popen() failed";
- goto done;
- }
- if (fwrite(image->data, image->size, 1, compfp) != 1) {
- errstr = "\nerror: writing data to gzip failed";
- goto done;
- }
- if (pclose(compfp)) {
- errstr = "\nerror: gzip process failed";
- goto done;
- }
-
- compfp = fopen(compfilename, "r");
- if (!compfp) {
- errstr = "\nerror: open() on gzip data failed";
- goto done;
- }
- if (stat(compfilename, &st)) {
- errstr = "\nerror: stat() on gzip file failed";
- goto done;
- }
- compressed = xmalloc(st.st_size);
- if (fread(compressed, st.st_size, 1, compfp) != 1) {
- errstr = "\nerror: reading gzip data failed";
- goto done;
- }
- fclose(compfp);
-
- unlink(compfilename);
-
- dataptr = compressed;
- count = st.st_size;
- fprintf(file, "#define EASYLOGO_ENABLE_%s %i\n\n", comp_name, count);
- if (bss_storage)
- fprintf (file, "static unsigned char EASYLOGO_DECOMP_BUFFER[%i];\n\n", image->size);
-
- done:
- free(compfilename);
- free(compcmd);
-
- if (errstr) {
- perror (errstr);
- return -1;
- }
- }
-
- /* Headers */
- fprintf (file, "#include <video_easylogo.h>\n\n");
- /* Macros */
- strcpy (def_name, varname);
- StringUpperCase (def_name);
- fprintf (file, "#define DEF_%s_WIDTH\t\t%d\n", def_name,
- image->width);
- fprintf (file, "#define DEF_%s_HEIGHT\t\t%d\n", def_name,
- image->height);
- fprintf (file, "#define DEF_%s_PIXELS\t\t%d\n", def_name,
- image->pixels);
- fprintf (file, "#define DEF_%s_BPP\t\t%d\n", def_name, image->bpp);
- fprintf (file, "#define DEF_%s_PIXEL_SIZE\t%d\n", def_name,
- image->pixel_size);
- fprintf (file, "#define DEF_%s_SIZE\t\t%d\n\n", def_name,
- image->size);
- /* Declaration */
- fprintf (file, "unsigned char DEF_%s_DATA[] = {\n",
- def_name);
-
- /* Data */
- while (count)
- switch (col) {
- case 0:
- sprintf (str, " 0x%02x", *dataptr++);
- col++;
- count--;
- break;
-
- case 16:
- fprintf (file, "%s", str);
- if (count > 0)
- fprintf (file, ",");
- fprintf (file, "\n");
-
- col = 0;
- break;
-
- default:
- strcpy (app, str);
- sprintf (str, "%s, 0x%02x", app, *dataptr++);
- col++;
- count--;
- break;
- }
-
- if (col)
- fprintf (file, "%s\n", str);
-
- /* End of declaration */
- fprintf (file, "};\n\n");
- /* Variable */
- fprintf (file, "fastimage_t %s = {\n", varname);
- fprintf (file, " DEF_%s_DATA,\n", def_name);
- fprintf (file, " DEF_%s_WIDTH,\n", def_name);
- fprintf (file, " DEF_%s_HEIGHT,\n", def_name);
- fprintf (file, " DEF_%s_BPP,\n", def_name);
- fprintf (file, " DEF_%s_PIXEL_SIZE,\n", def_name);
- fprintf (file, " DEF_%s_SIZE\n};\n", def_name);
-
- fclose (file);
-
- return 0;
-}
-
-#define DEF_FILELEN 256
-
-static void usage (int exit_status)
-{
- puts (
- "EasyLogo 1.0 (C) 2000 by Paolo Scaffardi\n"
- "\n"
- "Syntax: easylogo [options] inputfile [outputvar [outputfile]]\n"
- "\n"
- "Options:\n"
- " -r Output RGB888 instead of YUYV\n"
- " -s Output RGB565 instead of YUYV\n"
- " -g Compress with gzip\n"
- " -l Compress with lzma\n"
- " -b Preallocate space in bss for decompressing image\n"
- " -h Help output\n"
- "\n"
- "Where: 'inputfile' is the TGA image to load\n"
- " 'outputvar' is the variable name to create\n"
- " 'outputfile' is the output header file (default is 'inputfile.h')"
- );
- exit (exit_status);
-}
-
-int main (int argc, char *argv[])
-{
- int c;
- bool use_rgb888 = false;
- bool use_rgb565 = false;
- char inputfile[DEF_FILELEN],
- outputfile[DEF_FILELEN], varname[DEF_FILELEN];
-
- image_t rgb888_logo, rgb565_logo, yuyv_logo;
-
- while ((c = getopt(argc, argv, "hrsglb")) > 0) {
- switch (c) {
- case 'h':
- usage (0);
- break;
- case 'r':
- use_rgb888 = true;
- puts("Using 24-bit RGB888 Output Fromat");
- break;
- case 's':
- use_rgb565 = true;
- puts("Using 16-bit RGB565 Output Fromat");
- break;
- case 'g':
- compression = COMP_GZIP;
- puts("Compressing with gzip");
- break;
- case 'l':
- compression = COMP_LZMA;
- puts("Compressing with lzma");
- break;
- case 'b':
- bss_storage = true;
- puts("Preallocating bss space for decompressing image");
- break;
- default:
- usage (1);
- break;
- }
- }
-
- c = argc - optind;
- if (c > 4 || c < 1)
- usage (1);
-
- strcpy (inputfile, argv[optind]);
-
- if (c > 1)
- strcpy (varname, argv[optind + 1]);
- else {
- /* transform "input.tga" to just "input" */
- char *dot;
- strcpy (varname, inputfile);
- dot = strchr (varname, '.');
- if (dot)
- *dot = '\0';
- }
-
- if (c > 2)
- strcpy (outputfile, argv[optind + 2]);
- else {
- /* just append ".h" to input file name */
- strcpy (outputfile, inputfile);
- strcat (outputfile, ".h");
- }
-
- /* Make sure the output is sent as soon as we printf() */
- setbuf(stdout, NULL);
-
- printf ("Doing '%s' (%s) from '%s'...",
- outputfile, varname, inputfile);
-
- /* Import TGA logo */
-
- printf ("L");
- if (image_load_tga(&rgb888_logo, inputfile) < 0) {
- printf ("input file not found!\n");
- exit (1);
- }
-
- /* Convert, save, and free the image */
-
- if (!use_rgb888 && !use_rgb565) {
- printf ("C");
- image_rgb_to_yuyv(&rgb888_logo, &yuyv_logo);
-
- printf("S");
- image_save_header(&yuyv_logo, outputfile, varname);
- image_free(&yuyv_logo);
- } else if (use_rgb565) {
- printf("C");
- image_rgb888_to_rgb565(&rgb888_logo, &rgb565_logo);
-
- printf("S");
- image_save_header(&rgb565_logo, outputfile, varname);
- image_free(&rgb565_logo);
- } else {
- printf("S");
- image_save_header(&rgb888_logo, outputfile, varname);
- }
-
- /* Free original image and copy */
-
- image_free(&rgb888_logo);
-
- printf ("\n");
-
- return 0;
-}
diff --git a/tools/easylogo/linux_blackfin.tga b/tools/easylogo/linux_blackfin.tga
deleted file mode 100644
index e2bb17b..0000000
--- a/tools/easylogo/linux_blackfin.tga
+++ /dev/null
Binary files differ
diff --git a/tools/easylogo/linux_logo.tga b/tools/easylogo/linux_logo.tga
deleted file mode 100644
index ac53def..0000000
--- a/tools/easylogo/linux_logo.tga
+++ /dev/null
Binary files differ
diff --git a/tools/easylogo/runme.sh b/tools/easylogo/runme.sh
deleted file mode 100644
index 625ebaa..0000000
--- a/tools/easylogo/runme.sh
+++ /dev/null
@@ -1,4 +0,0 @@
-#!/bin/sh
-make
-./easylogo linux_logo.tga u_boot_logo video_logo.h
-mv video_logo.h ../../include
diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c
index eef12dd..e2801f5 100644
--- a/tools/env/fw_env.c
+++ b/tools/env/fw_env.c
@@ -10,6 +10,7 @@
#define _GNU_SOURCE
#include <compiler.h>
+#include <env.h>
#include <errno.h>
#include <env_flags.h>
#include <fcntl.h>
@@ -118,10 +119,6 @@
static int have_redund_env;
-static unsigned char active_flag = 1;
-/* obsolete_flag must be 0 to efficiently set it on NOR flash without erasing */
-static unsigned char obsolete_flag = 0;
-
#define DEFAULT_ENV_INSTANCE_STATIC
#include <env_default.h>
@@ -1138,10 +1135,11 @@
{
int rc;
struct erase_info_user erase;
+ char tmp = ENV_REDUND_OBSOLETE;
erase.start = DEVOFFSET(dev);
erase.length = DEVESIZE(dev);
- /* This relies on the fact, that obsolete_flag == 0 */
+ /* This relies on the fact, that ENV_REDUND_OBSOLETE == 0 */
rc = lseek(fd, offset, SEEK_SET);
if (rc < 0) {
fprintf(stderr, "Cannot seek to set the flag on %s\n",
@@ -1149,7 +1147,7 @@
return rc;
}
ioctl(fd, MEMUNLOCK, &erase);
- rc = write(fd, &obsolete_flag, sizeof(obsolete_flag));
+ rc = write(fd, &tmp, sizeof(tmp));
ioctl(fd, MEMLOCK, &erase);
if (rc < 0)
perror("Could not set obsolete flag");
@@ -1168,7 +1166,7 @@
(*environment.flags)++;
break;
case FLAG_BOOLEAN:
- *environment.flags = active_flag;
+ *environment.flags = ENV_REDUND_ACTIVE;
break;
default:
fprintf(stderr, "Unimplemented flash scheme %u\n",
@@ -1507,11 +1505,11 @@
} else {
switch (environment.flag_scheme) {
case FLAG_BOOLEAN:
- if (flag0 == active_flag &&
- flag1 == obsolete_flag) {
+ if (flag0 == ENV_REDUND_ACTIVE &&
+ flag1 == ENV_REDUND_OBSOLETE) {
dev_current = 0;
- } else if (flag0 == obsolete_flag &&
- flag1 == active_flag) {
+ } else if (flag0 == ENV_REDUND_OBSOLETE &&
+ flag1 == ENV_REDUND_ACTIVE) {
dev_current = 1;
} else if (flag0 == flag1) {
dev_current = 0;
diff --git a/tools/env/fw_env.h b/tools/env/fw_env.h
index b250e2f..3d2b457 100644
--- a/tools/env/fw_env.h
+++ b/tools/env/fw_env.h
@@ -4,6 +4,7 @@
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
+#include <env.h>
#include <stdint.h>
/*
diff --git a/tools/env/fw_env_main.c b/tools/env/fw_env_main.c
index 26ba662..1d193bd 100644
--- a/tools/env/fw_env_main.c
+++ b/tools/env/fw_env_main.c
@@ -26,6 +26,7 @@
* of AES key), eg. '-a aabbccddeeff00112233445566778899'.
*/
+#include <env.h>
#include <fcntl.h>
#include <getopt.h>
#include <stdio.h>
diff --git a/tools/envcrc.c b/tools/envcrc.c
index 5059492..672ef4d 100644
--- a/tools/envcrc.c
+++ b/tools/envcrc.c
@@ -59,9 +59,9 @@
#ifdef CONFIG_BUILD_ENVCRC
-# include <environment.h>
+# include <env_internal.h>
extern unsigned int env_size;
-extern env_t environment;
+extern env_t embedded_environment;
#endif /* CONFIG_BUILD_ENVCRC */
extern uint32_t crc32 (uint32_t, const unsigned char *, unsigned int);
@@ -71,7 +71,7 @@
#ifdef CONFIG_BUILD_ENVCRC
unsigned char pad = 0x00;
uint32_t crc;
- unsigned char *envptr = (unsigned char *)&environment,
+ unsigned char *envptr = (unsigned char *)&embedded_environment,
*dataptr = envptr + ENV_HEADER_SIZE;
unsigned int datasize = ENV_SIZE;
unsigned int eoe;
diff --git a/tools/ifwitool.c b/tools/ifwitool.c
new file mode 100644
index 0000000..2e020a8
--- /dev/null
+++ b/tools/ifwitool.c
@@ -0,0 +1,2304 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ifwitool, CLI utility for Integrated Firmware Image (IFWI) manipulation
+ *
+ * This is taken from the Coreboot project
+ */
+
+#include <assert.h>
+#include <stdbool.h>
+#include <getopt.h>
+#include "os_support.h"
+
+#define __packed __attribute__((packed))
+#define KiB 1024
+#define ALIGN(x, a) __ALIGN_MASK((x), (typeof(x))(a) - 1)
+#define __ALIGN_MASK(x, mask) (((x) + (mask)) & ~(mask))
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+/*
+ * min()/max()/clamp() macros that also do
+ * strict type-checking.. See the
+ * "unnecessary" pointer comparison.
+ */
+#define min(x, y) ({ \
+ typeof(x) _min1 = (x); \
+ typeof(y) _min2 = (y); \
+ (void)&_min1 == &_min2); \
+ _min1 < _min2 ? _min1 : _min2; })
+
+#define max(x, y) ({ \
+ typeof(x) _max1 = (x); \
+ typeof(y) _max2 = (y); \
+ (void)(&_max1 == &_max2); \
+ _max1 > _max2 ? _max1 : _max2; })
+
+static int verbose = 1;
+
+/* Buffer and file I/O */
+struct buffer {
+ char *name;
+ char *data;
+ size_t offset;
+ size_t size;
+};
+
+#define ERROR(...) { fprintf(stderr, "E: " __VA_ARGS__); }
+#define INFO(...) { if (verbose > 0) fprintf(stderr, "INFO: " __VA_ARGS__); }
+#define DEBUG(...) { if (verbose > 1) fprintf(stderr, "DEBUG: " __VA_ARGS__); }
+
+/*
+ * BPDT is Boot Partition Descriptor Table. It is located at the start of a
+ * logical boot partition(LBP). It stores information about the critical
+ * sub-partitions present within the LBP.
+ *
+ * S-BPDT is Secondary Boot Partition Descriptor Table. It is located after the
+ * critical sub-partitions and contains information about the non-critical
+ * sub-partitions present within the LBP.
+ *
+ * Both tables are identified by BPDT_SIGNATURE stored at the start of the
+ * table.
+ */
+#define BPDT_SIGNATURE (0x000055AA)
+
+/* Parameters passed in by caller */
+static struct param {
+ const char *file_name;
+ const char *subpart_name;
+ const char *image_name;
+ bool dir_ops;
+ const char *dentry_name;
+} param;
+
+struct bpdt_header {
+ /*
+ * This is used to identify start of BPDT. It should always be
+ * BPDT_SIGNATURE.
+ */
+ uint32_t signature;
+ /* Count of BPDT entries present */
+ uint16_t descriptor_count;
+ /* Version - Currently supported = 1 */
+ uint16_t bpdt_version;
+ /* Unused - Should be 0 */
+ uint32_t xor_redundant_block;
+ /* Version of IFWI build */
+ uint32_t ifwi_version;
+ /* Version of FIT tool used to create IFWI */
+ uint64_t fit_tool_version;
+} __packed;
+#define BPDT_HEADER_SIZE (sizeof(struct bpdt_header))
+
+struct bpdt_entry {
+ /* Type of sub-partition */
+ uint16_t type;
+ /* Attributes of sub-partition */
+ uint16_t flags;
+ /* Offset of sub-partition from beginning of LBP */
+ uint32_t offset;
+ /* Size in bytes of sub-partition */
+ uint32_t size;
+} __packed;
+#define BPDT_ENTRY_SIZE (sizeof(struct bpdt_entry))
+
+struct bpdt {
+ struct bpdt_header h;
+ /* In practice, this could be an array of 0 to n entries */
+ struct bpdt_entry e[0];
+} __packed;
+
+static inline size_t get_bpdt_size(struct bpdt_header *h)
+{
+ return (sizeof(*h) + BPDT_ENTRY_SIZE * h->descriptor_count);
+}
+
+/* Minimum size in bytes allocated to BPDT in IFWI */
+#define BPDT_MIN_SIZE ((size_t)512)
+
+/* Header to define directory header for sub-partition */
+struct subpart_dir_header {
+ /* Should be SUBPART_DIR_MARKER */
+ uint32_t marker;
+ /* Number of directory entries in the sub-partition */
+ uint32_t num_entries;
+ /* Currenty supported - 1 */
+ uint8_t header_version;
+ /* Currenty supported - 1 */
+ uint8_t entry_version;
+ /* Length of directory header in bytes */
+ uint8_t header_length;
+ /*
+ * 2s complement of 8-bit sum from first byte of header to last byte of
+ * last directory entry.
+ */
+ uint8_t checksum;
+ /* ASCII short name of sub-partition */
+ uint8_t name[4];
+} __packed;
+#define SUBPART_DIR_HEADER_SIZE \
+ (sizeof(struct subpart_dir_header))
+#define SUBPART_DIR_MARKER 0x44504324
+#define SUBPART_DIR_HEADER_VERSION_SUPPORTED 1
+#define SUBPART_DIR_ENTRY_VERSION_SUPPORTED 1
+
+/* Structure for each directory entry for sub-partition */
+struct subpart_dir_entry {
+ /* Name of directory entry - Not guaranteed to be NULL-terminated */
+ uint8_t name[12];
+ /* Offset of entry from beginning of sub-partition */
+ uint32_t offset;
+ /* Length in bytes of sub-directory entry */
+ uint32_t length;
+ /* Must be zero */
+ uint32_t rsvd;
+} __packed;
+#define SUBPART_DIR_ENTRY_SIZE \
+ (sizeof(struct subpart_dir_entry))
+
+struct subpart_dir {
+ struct subpart_dir_header h;
+ /* In practice, this could be an array of 0 to n entries */
+ struct subpart_dir_entry e[0];
+} __packed;
+
+static inline size_t subpart_dir_size(struct subpart_dir_header *h)
+{
+ return (sizeof(*h) + SUBPART_DIR_ENTRY_SIZE * h->num_entries);
+}
+
+struct manifest_header {
+ uint32_t header_type;
+ uint32_t header_length;
+ uint32_t header_version;
+ uint32_t flags;
+ uint32_t vendor;
+ uint32_t date;
+ uint32_t size;
+ uint32_t id;
+ uint32_t rsvd;
+ uint64_t version;
+ uint32_t svn;
+ uint64_t rsvd1;
+ uint8_t rsvd2[64];
+ uint32_t modulus_size;
+ uint32_t exponent_size;
+ uint8_t public_key[256];
+ uint32_t exponent;
+ uint8_t signature[256];
+} __packed;
+
+#define DWORD_SIZE 4
+#define MANIFEST_HDR_SIZE (sizeof(struct manifest_header))
+#define MANIFEST_ID_MAGIC (0x324e4d24)
+
+struct module {
+ uint8_t name[12];
+ uint8_t type;
+ uint8_t hash_alg;
+ uint16_t hash_size;
+ uint32_t metadata_size;
+ uint8_t metadata_hash[32];
+} __packed;
+
+#define MODULE_SIZE (sizeof(struct module))
+
+struct signed_pkg_info_ext {
+ uint32_t ext_type;
+ uint32_t ext_length;
+ uint8_t name[4];
+ uint32_t vcn;
+ uint8_t bitmap[16];
+ uint32_t svn;
+ uint8_t rsvd[16];
+} __packed;
+
+#define SIGNED_PKG_INFO_EXT_TYPE 0x15
+#define SIGNED_PKG_INFO_EXT_SIZE \
+ (sizeof(struct signed_pkg_info_ext))
+
+/*
+ * Attributes for various IFWI sub-partitions.
+ * LIES_WITHIN_BPDT_4K = Sub-Partition should lie within the same 4K block as
+ * BPDT.
+ * NON_CRITICAL_SUBPART = Sub-Partition entry should be present in S-BPDT.
+ * CONTAINS_DIR = Sub-Partition contains directory.
+ * AUTO_GENERATED = Sub-Partition is generated by the tool.
+ * MANDATORY_BPDT_ENTRY = Even if sub-partition is deleted, BPDT should contain
+ * an entry for it with size 0 and offset 0.
+ */
+enum subpart_attributes {
+ LIES_WITHIN_BPDT_4K = (1 << 0),
+ NON_CRITICAL_SUBPART = (1 << 1),
+ CONTAINS_DIR = (1 << 2),
+ AUTO_GENERATED = (1 << 3),
+ MANDATORY_BPDT_ENTRY = (1 << 4),
+};
+
+/* Type value for various IFWI sub-partitions */
+enum bpdt_entry_type {
+ SMIP_TYPE = 0,
+ CSE_RBE_TYPE = 1,
+ CSE_BUP_TYPE = 2,
+ UCODE_TYPE = 3,
+ IBB_TYPE = 4,
+ S_BPDT_TYPE = 5,
+ OBB_TYPE = 6,
+ CSE_MAIN_TYPE = 7,
+ ISH_TYPE = 8,
+ CSE_IDLM_TYPE = 9,
+ IFP_OVERRIDE_TYPE = 10,
+ DEBUG_TOKENS_TYPE = 11,
+ UFS_PHY_TYPE = 12,
+ UFS_GPP_TYPE = 13,
+ PMC_TYPE = 14,
+ IUNIT_TYPE = 15,
+ NVM_CONFIG_TYPE = 16,
+ UEP_TYPE = 17,
+ UFS_RATE_B_TYPE = 18,
+ MAX_SUBPARTS = 19,
+};
+
+/*
+ * There are two order requirements for an IFWI image:
+ * 1. Order in which the sub-partitions lie within the BPDT entries.
+ * 2. Order in which the sub-partitions lie within the image.
+ *
+ * header_order defines #1 i.e. the order in which the sub-partitions should
+ * appear in the BPDT entries. pack_order defines #2 i.e. the order in which
+ * sub-partitions appear in the IFWI image. pack_order controls the offset and
+ * thus sub-partitions would have increasing offsets as we loop over pack_order.
+ */
+const enum bpdt_entry_type bpdt_header_order[MAX_SUBPARTS] = {
+ /* Order of the following entries is mandatory */
+ CSE_IDLM_TYPE,
+ IFP_OVERRIDE_TYPE,
+ S_BPDT_TYPE,
+ CSE_RBE_TYPE,
+ UFS_PHY_TYPE,
+ UFS_GPP_TYPE,
+ /* Order of the following entries is recommended */
+ UEP_TYPE,
+ NVM_CONFIG_TYPE,
+ UFS_RATE_B_TYPE,
+ IBB_TYPE,
+ SMIP_TYPE,
+ PMC_TYPE,
+ CSE_BUP_TYPE,
+ UCODE_TYPE,
+ DEBUG_TOKENS_TYPE,
+ IUNIT_TYPE,
+ CSE_MAIN_TYPE,
+ ISH_TYPE,
+ OBB_TYPE,
+};
+
+const enum bpdt_entry_type bpdt_pack_order[MAX_SUBPARTS] = {
+ /* Order of the following entries is mandatory */
+ UFS_GPP_TYPE,
+ UFS_PHY_TYPE,
+ IFP_OVERRIDE_TYPE,
+ UEP_TYPE,
+ NVM_CONFIG_TYPE,
+ UFS_RATE_B_TYPE,
+ /* Order of the following entries is recommended */
+ IBB_TYPE,
+ SMIP_TYPE,
+ CSE_RBE_TYPE,
+ PMC_TYPE,
+ CSE_BUP_TYPE,
+ UCODE_TYPE,
+ CSE_IDLM_TYPE,
+ DEBUG_TOKENS_TYPE,
+ S_BPDT_TYPE,
+ IUNIT_TYPE,
+ CSE_MAIN_TYPE,
+ ISH_TYPE,
+ OBB_TYPE,
+};
+
+/* Utility functions */
+enum ifwi_ret {
+ COMMAND_ERR = -1,
+ NO_ACTION_REQUIRED = 0,
+ REPACK_REQUIRED = 1,
+};
+
+struct dir_ops {
+ enum ifwi_ret (*dir_add)(int type);
+};
+
+static enum ifwi_ret ibbp_dir_add(int type);
+
+const struct subpart_info {
+ const char *name;
+ const char *readable_name;
+ uint32_t attr;
+ struct dir_ops dir_ops;
+} subparts[MAX_SUBPARTS] = {
+ /* OEM SMIP */
+ [SMIP_TYPE] = {"SMIP", "SMIP", CONTAINS_DIR, {NULL} },
+ /* CSE RBE */
+ [CSE_RBE_TYPE] = {"RBEP", "CSE_RBE", CONTAINS_DIR |
+ MANDATORY_BPDT_ENTRY, {NULL} },
+ /* CSE BUP */
+ [CSE_BUP_TYPE] = {"FTPR", "CSE_BUP", CONTAINS_DIR |
+ MANDATORY_BPDT_ENTRY, {NULL} },
+ /* uCode */
+ [UCODE_TYPE] = {"UCOD", "Microcode", CONTAINS_DIR, {NULL} },
+ /* IBB */
+ [IBB_TYPE] = {"IBBP", "Bootblock", CONTAINS_DIR, {ibbp_dir_add} },
+ /* S-BPDT */
+ [S_BPDT_TYPE] = {"S_BPDT", "S-BPDT", AUTO_GENERATED |
+ MANDATORY_BPDT_ENTRY, {NULL} },
+ /* OBB */
+ [OBB_TYPE] = {"OBBP", "OEM boot block", CONTAINS_DIR |
+ NON_CRITICAL_SUBPART, {NULL} },
+ /* CSE Main */
+ [CSE_MAIN_TYPE] = {"NFTP", "CSE_MAIN", CONTAINS_DIR |
+ NON_CRITICAL_SUBPART, {NULL} },
+ /* ISH */
+ [ISH_TYPE] = {"ISHP", "ISH", NON_CRITICAL_SUBPART, {NULL} },
+ /* CSE IDLM */
+ [CSE_IDLM_TYPE] = {"DLMP", "CSE_IDLM", CONTAINS_DIR |
+ MANDATORY_BPDT_ENTRY, {NULL} },
+ /* IFP Override */
+ [IFP_OVERRIDE_TYPE] = {"IFP_OVERRIDE", "IFP_OVERRIDE",
+ LIES_WITHIN_BPDT_4K | MANDATORY_BPDT_ENTRY,
+ {NULL} },
+ /* Debug Tokens */
+ [DEBUG_TOKENS_TYPE] = {"DEBUG_TOKENS", "Debug Tokens", 0, {NULL} },
+ /* UFS Phy Configuration */
+ [UFS_PHY_TYPE] = {"UFS_PHY", "UFS Phy", LIES_WITHIN_BPDT_4K |
+ MANDATORY_BPDT_ENTRY, {NULL} },
+ /* UFS GPP LUN ID */
+ [UFS_GPP_TYPE] = {"UFS_GPP", "UFS GPP", LIES_WITHIN_BPDT_4K |
+ MANDATORY_BPDT_ENTRY, {NULL} },
+ /* PMC */
+ [PMC_TYPE] = {"PMCP", "PMC firmware", CONTAINS_DIR, {NULL} },
+ /* IUNIT */
+ [IUNIT_TYPE] = {"IUNP", "IUNIT", NON_CRITICAL_SUBPART, {NULL} },
+ /* NVM Config */
+ [NVM_CONFIG_TYPE] = {"NVM_CONFIG", "NVM Config", 0, {NULL} },
+ /* UEP */
+ [UEP_TYPE] = {"UEP", "UEP", LIES_WITHIN_BPDT_4K | MANDATORY_BPDT_ENTRY,
+ {NULL} },
+ /* UFS Rate B Config */
+ [UFS_RATE_B_TYPE] = {"UFS_RATE_B", "UFS Rate B Config", 0, {NULL} },
+};
+
+struct ifwi_image {
+ /* Data read from input file */
+ struct buffer input_buff;
+
+ /* BPDT header and entries */
+ struct buffer bpdt;
+ size_t input_ifwi_start_offset;
+ size_t input_ifwi_end_offset;
+
+ /* Subpartition content */
+ struct buffer subpart_buf[MAX_SUBPARTS];
+} ifwi_image;
+
+/* Buffer and file I/O */
+static off_t get_file_size(FILE *f)
+{
+ off_t fsize;
+
+ fseek(f, 0, SEEK_END);
+ fsize = ftell(f);
+ fseek(f, 0, SEEK_SET);
+ return fsize;
+}
+
+static inline void *buffer_get(const struct buffer *b)
+{
+ return b->data;
+}
+
+static inline size_t buffer_size(const struct buffer *b)
+{
+ return b->size;
+}
+
+static inline size_t buffer_offset(const struct buffer *b)
+{
+ return b->offset;
+}
+
+/*
+ * Shrink a buffer toward the beginning of its previous space.
+ * Afterward, buffer_delete() remains the means of cleaning it up
+ */
+static inline void buffer_set_size(struct buffer *b, size_t size)
+{
+ b->size = size;
+}
+
+/* Splice a buffer into another buffer. Note that it's up to the caller to
+ * bounds check the offset and size. The resulting buffer is backed by the same
+ * storage as the original, so although it is valid to buffer_delete() either
+ * one of them, doing so releases both simultaneously
+ */
+static void buffer_splice(struct buffer *dest, const struct buffer *src,
+ size_t offset, size_t size)
+{
+ dest->name = src->name;
+ dest->data = src->data + offset;
+ dest->offset = src->offset + offset;
+ dest->size = size;
+}
+
+/*
+ * Shrink a buffer toward the end of its previous space.
+ * Afterward, buffer_delete() remains the means of cleaning it up
+ */
+static inline void buffer_seek(struct buffer *b, size_t size)
+{
+ b->offset += size;
+ b->size -= size;
+ b->data += size;
+}
+
+/* Returns the start of the underlying buffer, with the offset undone */
+static inline void *buffer_get_original_backing(const struct buffer *b)
+{
+ if (!b)
+ return NULL;
+ return buffer_get(b) - buffer_offset(b);
+}
+
+int buffer_create(struct buffer *buffer, size_t size, const char *name)
+{
+ buffer->name = strdup(name);
+ buffer->offset = 0;
+ buffer->size = size;
+ buffer->data = (char *)malloc(buffer->size);
+ if (!buffer->data) {
+ fprintf(stderr, "%s: Insufficient memory (0x%zx).\n", __func__,
+ size);
+ }
+
+ return !buffer->data;
+}
+
+int buffer_write_file(struct buffer *buffer, const char *filename)
+{
+ FILE *fp = fopen(filename, "wb");
+
+ if (!fp) {
+ perror(filename);
+ return -1;
+ }
+ assert(buffer && buffer->data);
+ if (fwrite(buffer->data, 1, buffer->size, fp) != buffer->size) {
+ fprintf(stderr, "incomplete write: %s\n", filename);
+ fclose(fp);
+ return -1;
+ }
+ fclose(fp);
+ return 0;
+}
+
+void buffer_delete(struct buffer *buffer)
+{
+ assert(buffer);
+ if (buffer->name) {
+ free(buffer->name);
+ buffer->name = NULL;
+ }
+ if (buffer->data) {
+ free(buffer_get_original_backing(buffer));
+ buffer->data = NULL;
+ }
+ buffer->offset = 0;
+ buffer->size = 0;
+}
+
+int buffer_from_file(struct buffer *buffer, const char *filename)
+{
+ FILE *fp = fopen(filename, "rb");
+
+ if (!fp) {
+ perror(filename);
+ return -1;
+ }
+ buffer->offset = 0;
+ off_t file_size = get_file_size(fp);
+
+ if (file_size < 0) {
+ fprintf(stderr, "could not determine size of %s\n", filename);
+ fclose(fp);
+ return -1;
+ }
+ buffer->size = file_size;
+ buffer->name = strdup(filename);
+ buffer->data = (char *)malloc(buffer->size);
+ assert(buffer->data);
+ if (fread(buffer->data, 1, buffer->size, fp) != buffer->size) {
+ fprintf(stderr, "incomplete read: %s\n", filename);
+ fclose(fp);
+ buffer_delete(buffer);
+ return -1;
+ }
+ fclose(fp);
+ return 0;
+}
+
+static void alloc_buffer(struct buffer *b, size_t s, const char *n)
+{
+ if (buffer_create(b, s, n) == 0)
+ return;
+
+ ERROR("Buffer allocation failure for %s (size = %zx).\n", n, s);
+ exit(-1);
+}
+
+/* Little-Endian functions */
+static inline uint8_t read_ble8(const void *src)
+{
+ const uint8_t *s = src;
+ return *s;
+}
+
+static inline uint8_t read_at_ble8(const void *src, size_t offset)
+{
+ const uint8_t *s = src;
+
+ s += offset;
+ return read_ble8(s);
+}
+
+static inline void write_ble8(void *dest, uint8_t val)
+{
+ *(uint8_t *)dest = val;
+}
+
+static inline void write_at_ble8(void *dest, uint8_t val, size_t offset)
+{
+ uint8_t *d = dest;
+
+ d += offset;
+ write_ble8(d, val);
+}
+
+static inline uint8_t read_at_le8(const void *src, size_t offset)
+{
+ return read_at_ble8(src, offset);
+}
+
+static inline void write_le8(void *dest, uint8_t val)
+{
+ write_ble8(dest, val);
+}
+
+static inline void write_at_le8(void *dest, uint8_t val, size_t offset)
+{
+ write_at_ble8(dest, val, offset);
+}
+
+static inline uint16_t read_le16(const void *src)
+{
+ const uint8_t *s = src;
+
+ return (((uint16_t)s[1]) << 8) | (((uint16_t)s[0]) << 0);
+}
+
+static inline uint16_t read_at_le16(const void *src, size_t offset)
+{
+ const uint8_t *s = src;
+
+ s += offset;
+ return read_le16(s);
+}
+
+static inline void write_le16(void *dest, uint16_t val)
+{
+ write_le8(dest, val >> 0);
+ write_at_le8(dest, val >> 8, sizeof(uint8_t));
+}
+
+static inline void write_at_le16(void *dest, uint16_t val, size_t offset)
+{
+ uint8_t *d = dest;
+
+ d += offset;
+ write_le16(d, val);
+}
+
+static inline uint32_t read_le32(const void *src)
+{
+ const uint8_t *s = src;
+
+ return (((uint32_t)s[3]) << 24) | (((uint32_t)s[2]) << 16) |
+ (((uint32_t)s[1]) << 8) | (((uint32_t)s[0]) << 0);
+}
+
+static inline uint32_t read_at_le32(const void *src, size_t offset)
+{
+ const uint8_t *s = src;
+
+ s += offset;
+ return read_le32(s);
+}
+
+static inline void write_le32(void *dest, uint32_t val)
+{
+ write_le16(dest, val >> 0);
+ write_at_le16(dest, val >> 16, sizeof(uint16_t));
+}
+
+static inline void write_at_le32(void *dest, uint32_t val, size_t offset)
+{
+ uint8_t *d = dest;
+
+ d += offset;
+ write_le32(d, val);
+}
+
+static inline uint64_t read_le64(const void *src)
+{
+ uint64_t val;
+
+ val = read_at_le32(src, sizeof(uint32_t));
+ val <<= 32;
+ val |= read_le32(src);
+ return val;
+}
+
+static inline uint64_t read_at_le64(const void *src, size_t offset)
+{
+ const uint8_t *s = src;
+
+ s += offset;
+ return read_le64(s);
+}
+
+static inline void write_le64(void *dest, uint64_t val)
+{
+ write_le32(dest, val >> 0);
+ write_at_le32(dest, val >> 32, sizeof(uint32_t));
+}
+
+static inline void write_at_le64(void *dest, uint64_t val, size_t offset)
+{
+ uint8_t *d = dest;
+
+ d += offset;
+ write_le64(d, val);
+}
+
+/*
+ * Read header/entry members in little-endian format.
+ * Returns the offset upto which the read was performed.
+ */
+static size_t read_member(void *src, size_t offset, size_t size_bytes,
+ void *dst)
+{
+ switch (size_bytes) {
+ case 1:
+ *(uint8_t *)dst = read_at_le8(src, offset);
+ break;
+ case 2:
+ *(uint16_t *)dst = read_at_le16(src, offset);
+ break;
+ case 4:
+ *(uint32_t *)dst = read_at_le32(src, offset);
+ break;
+ case 8:
+ *(uint64_t *)dst = read_at_le64(src, offset);
+ break;
+ default:
+ ERROR("Read size not supported %zd\n", size_bytes);
+ exit(-1);
+ }
+
+ return (offset + size_bytes);
+}
+
+/*
+ * Convert to little endian format.
+ * Returns the offset upto which the fixup was performed.
+ */
+static size_t fix_member(void *data, size_t offset, size_t size_bytes)
+{
+ uint8_t *src = (uint8_t *)data + offset;
+
+ switch (size_bytes) {
+ case 1:
+ write_at_le8(data, *(uint8_t *)src, offset);
+ break;
+ case 2:
+ write_at_le16(data, *(uint16_t *)src, offset);
+ break;
+ case 4:
+ write_at_le32(data, *(uint32_t *)src, offset);
+ break;
+ case 8:
+ write_at_le64(data, *(uint64_t *)src, offset);
+ break;
+ default:
+ ERROR("Write size not supported %zd\n", size_bytes);
+ exit(-1);
+ }
+ return (offset + size_bytes);
+}
+
+static void print_subpart_dir(struct subpart_dir *s)
+{
+ if (verbose == 0)
+ return;
+
+ size_t i;
+
+ printf("%-25s 0x%-23.8x\n", "Marker", s->h.marker);
+ printf("%-25s %-25d\n", "Num entries", s->h.num_entries);
+ printf("%-25s %-25d\n", "Header Version", s->h.header_version);
+ printf("%-25s %-25d\n", "Entry Version", s->h.entry_version);
+ printf("%-25s 0x%-23x\n", "Header Length", s->h.header_length);
+ printf("%-25s 0x%-23x\n", "Checksum", s->h.checksum);
+ printf("%-25s ", "Name");
+ for (i = 0; i < sizeof(s->h.name); i++)
+ printf("%c", s->h.name[i]);
+
+ printf("\n");
+
+ printf("%-25s%-25s%-25s%-25s%-25s\n", "Entry #", "Name", "Offset",
+ "Length", "Rsvd");
+
+ printf("=========================================================================================================================\n");
+
+ for (i = 0; i < s->h.num_entries; i++) {
+ printf("%-25zd%-25.12s0x%-23x0x%-23x0x%-23x\n", i + 1,
+ s->e[i].name, s->e[i].offset, s->e[i].length,
+ s->e[i].rsvd);
+ }
+
+ printf("=========================================================================================================================\n");
+}
+
+static void bpdt_print_header(struct bpdt_header *h, const char *name)
+{
+ if (verbose == 0)
+ return;
+
+ printf("%-25s %-25s\n", "Header", name);
+ printf("%-25s 0x%-23.8x\n", "Signature", h->signature);
+ printf("%-25s %-25d\n", "Descriptor count", h->descriptor_count);
+ printf("%-25s %-25d\n", "BPDT Version", h->bpdt_version);
+ printf("%-25s 0x%-23x\n", "XOR checksum", h->xor_redundant_block);
+ printf("%-25s 0x%-23x\n", "IFWI Version", h->ifwi_version);
+ printf("%-25s 0x%-23llx\n", "FIT Tool Version",
+ (long long)h->fit_tool_version);
+}
+
+static void bpdt_print_entries(struct bpdt_entry *e, size_t count,
+ const char *name)
+{
+ size_t i;
+
+ if (verbose == 0)
+ return;
+
+ printf("%s entries\n", name);
+
+ printf("%-25s%-25s%-25s%-25s%-25s%-25s%-25s%-25s\n", "Entry #",
+ "Sub-Partition", "Name", "Type", "Flags", "Offset", "Size",
+ "File Offset");
+
+ printf("=========================================================================================================================================================================================================\n");
+
+ for (i = 0; i < count; i++) {
+ printf("%-25zd%-25s%-25s%-25d0x%-23.08x0x%-23x0x%-23x0x%-23zx\n",
+ i + 1, subparts[e[i].type].name,
+ subparts[e[i].type].readable_name, e[i].type, e[i].flags,
+ e[i].offset, e[i].size,
+ e[i].offset + ifwi_image.input_ifwi_start_offset);
+ }
+
+ printf("=========================================================================================================================================================================================================\n");
+}
+
+static void bpdt_validate_header(struct bpdt_header *h, const char *name)
+{
+ assert(h->signature == BPDT_SIGNATURE);
+
+ if (h->bpdt_version != 1) {
+ ERROR("Invalid header : %s\n", name);
+ exit(-1);
+ }
+
+ DEBUG("Validated header : %s\n", name);
+}
+
+static void bpdt_read_header(void *data, struct bpdt_header *h,
+ const char *name)
+{
+ size_t offset = 0;
+
+ offset = read_member(data, offset, sizeof(h->signature), &h->signature);
+ offset = read_member(data, offset, sizeof(h->descriptor_count),
+ &h->descriptor_count);
+ offset = read_member(data, offset, sizeof(h->bpdt_version),
+ &h->bpdt_version);
+ offset = read_member(data, offset, sizeof(h->xor_redundant_block),
+ &h->xor_redundant_block);
+ offset = read_member(data, offset, sizeof(h->ifwi_version),
+ &h->ifwi_version);
+ read_member(data, offset, sizeof(h->fit_tool_version),
+ &h->fit_tool_version);
+
+ bpdt_validate_header(h, name);
+ bpdt_print_header(h, name);
+}
+
+static void bpdt_read_entries(void *data, struct bpdt *bpdt, const char *name)
+{
+ size_t i, offset = 0;
+ struct bpdt_entry *e = &bpdt->e[0];
+ size_t count = bpdt->h.descriptor_count;
+
+ for (i = 0; i < count; i++) {
+ offset = read_member(data, offset, sizeof(e[i].type),
+ &e[i].type);
+ offset = read_member(data, offset, sizeof(e[i].flags),
+ &e[i].flags);
+ offset = read_member(data, offset, sizeof(e[i].offset),
+ &e[i].offset);
+ offset = read_member(data, offset, sizeof(e[i].size),
+ &e[i].size);
+ }
+
+ bpdt_print_entries(e, count, name);
+}
+
+/*
+ * Given type of sub-partition, identify BPDT entry for it.
+ * Sub-Partition could lie either within BPDT or S-BPDT.
+ */
+static struct bpdt_entry *__find_entry_by_type(struct bpdt_entry *e,
+ size_t count, int type)
+{
+ size_t i;
+
+ for (i = 0; i < count; i++) {
+ if (e[i].type == type)
+ break;
+ }
+
+ if (i == count)
+ return NULL;
+
+ return &e[i];
+}
+
+static struct bpdt_entry *find_entry_by_type(int type)
+{
+ struct bpdt *b = buffer_get(&ifwi_image.bpdt);
+
+ if (!b)
+ return NULL;
+
+ struct bpdt_entry *curr = __find_entry_by_type(&b->e[0],
+ b->h.descriptor_count,
+ type);
+
+ if (curr)
+ return curr;
+
+ b = buffer_get(&ifwi_image.subpart_buf[S_BPDT_TYPE]);
+ if (!b)
+ return NULL;
+
+ return __find_entry_by_type(&b->e[0], b->h.descriptor_count, type);
+}
+
+/*
+ * Find sub-partition type given its name. If the name does not exist, returns
+ * -1.
+ */
+static int find_type_by_name(const char *name)
+{
+ int i;
+
+ for (i = 0; i < MAX_SUBPARTS; i++) {
+ if ((strlen(subparts[i].name) == strlen(name)) &&
+ (!strcmp(subparts[i].name, name)))
+ break;
+ }
+
+ if (i == MAX_SUBPARTS) {
+ ERROR("Invalid sub-partition name %s.\n", name);
+ return -1;
+ }
+
+ return i;
+}
+
+/*
+ * Read the content of a sub-partition from input file and store it in
+ * ifwi_image.subpart_buf[SUB-PARTITION_TYPE].
+ *
+ * Returns the maximum offset occupied by the sub-partitions.
+ */
+static size_t read_subpart_buf(void *data, size_t size, struct bpdt_entry *e,
+ size_t count)
+{
+ size_t i, type;
+ struct buffer *buf;
+ size_t max_offset = 0;
+
+ for (i = 0; i < count; i++) {
+ type = e[i].type;
+
+ if (type >= MAX_SUBPARTS) {
+ ERROR("Invalid sub-partition type %zd.\n", type);
+ exit(-1);
+ }
+
+ if (buffer_size(&ifwi_image.subpart_buf[type])) {
+ ERROR("Multiple sub-partitions of type %zd(%s).\n",
+ type, subparts[type].name);
+ exit(-1);
+ }
+
+ if (e[i].size == 0) {
+ INFO("Dummy sub-partition %zd(%s). Skipping.\n", type,
+ subparts[type].name);
+ continue;
+ }
+
+ assert((e[i].offset + e[i].size) <= size);
+
+ /*
+ * Sub-partitions in IFWI image are not in the same order as
+ * in BPDT entries. BPDT entires are in header_order whereas
+ * sub-partition offsets in the image are in pack_order.
+ */
+ if ((e[i].offset + e[i].size) > max_offset)
+ max_offset = e[i].offset + e[i].size;
+
+ /*
+ * S-BPDT sub-partition contains information about all the
+ * non-critical sub-partitions. Thus, size of S-BPDT
+ * sub-partition equals size of S-BPDT plus size of all the
+ * non-critical sub-partitions. Thus, reading whole of S-BPDT
+ * here would be redundant as the non-critical partitions are
+ * read and allocated buffers separately. Also, S-BPDT requires
+ * special handling for reading header and entries.
+ */
+ if (type == S_BPDT_TYPE)
+ continue;
+
+ buf = &ifwi_image.subpart_buf[type];
+
+ alloc_buffer(buf, e[i].size, subparts[type].name);
+ memcpy(buffer_get(buf), (uint8_t *)data + e[i].offset,
+ e[i].size);
+ }
+
+ assert(max_offset);
+ return max_offset;
+}
+
+/*
+ * Allocate buffer for bpdt header, entries and all sub-partition content.
+ * Returns offset in data where BPDT ends.
+ */
+static size_t alloc_bpdt_buffer(void *data, size_t size, size_t offset,
+ struct buffer *b, const char *name)
+{
+ struct bpdt_header bpdt_header;
+
+ assert((offset + BPDT_HEADER_SIZE) < size);
+ bpdt_read_header((uint8_t *)data + offset, &bpdt_header, name);
+
+ /* Buffer to read BPDT header and entries */
+ alloc_buffer(b, get_bpdt_size(&bpdt_header), name);
+
+ struct bpdt *bpdt = buffer_get(b);
+
+ memcpy(&bpdt->h, &bpdt_header, BPDT_HEADER_SIZE);
+
+ /*
+ * If no entries are present, maximum offset occupied is (offset +
+ * BPDT_HEADER_SIZE).
+ */
+ if (bpdt->h.descriptor_count == 0)
+ return (offset + BPDT_HEADER_SIZE);
+
+ /* Read all entries */
+ assert((offset + get_bpdt_size(&bpdt->h)) < size);
+ bpdt_read_entries((uint8_t *)data + offset + BPDT_HEADER_SIZE, bpdt,
+ name);
+
+ /* Read all sub-partition content in subpart_buf */
+ return read_subpart_buf(data, size, &bpdt->e[0],
+ bpdt->h.descriptor_count);
+}
+
+static void parse_sbpdt(void *data, size_t size)
+{
+ struct bpdt_entry *s;
+
+ s = find_entry_by_type(S_BPDT_TYPE);
+ if (!s)
+ return;
+
+ assert(size > s->offset);
+
+ alloc_bpdt_buffer(data, size, s->offset,
+ &ifwi_image.subpart_buf[S_BPDT_TYPE],
+ "S-BPDT");
+}
+
+static uint8_t calc_checksum(struct subpart_dir *s)
+{
+ size_t size = subpart_dir_size(&s->h);
+ uint8_t *data = (uint8_t *)s;
+ uint8_t checksum = 0;
+ size_t i;
+ uint8_t old_checksum = s->h.checksum;
+
+ s->h.checksum = 0;
+
+ for (i = 0; i < size; i++)
+ checksum += data[i];
+
+ s->h.checksum = old_checksum;
+
+ /* 2s complement */
+ return -checksum;
+}
+
+static void validate_subpart_dir(struct subpart_dir *s, const char *name,
+ bool checksum_check)
+{
+ if (s->h.marker != SUBPART_DIR_MARKER ||
+ s->h.header_version != SUBPART_DIR_HEADER_VERSION_SUPPORTED ||
+ s->h.entry_version != SUBPART_DIR_ENTRY_VERSION_SUPPORTED ||
+ s->h.header_length != SUBPART_DIR_HEADER_SIZE) {
+ ERROR("Invalid subpart_dir for %s.\n", name);
+ exit(-1);
+ }
+
+ if (!checksum_check)
+ return;
+
+ uint8_t checksum = calc_checksum(s);
+
+ if (checksum != s->h.checksum)
+ ERROR("Invalid checksum for %s (Expected=0x%x, Actual=0x%x).\n",
+ name, checksum, s->h.checksum);
+}
+
+static void validate_subpart_dir_without_checksum(struct subpart_dir *s,
+ const char *name)
+{
+ validate_subpart_dir(s, name, 0);
+}
+
+static void validate_subpart_dir_with_checksum(struct subpart_dir *s,
+ const char *name)
+{
+ validate_subpart_dir(s, name, 1);
+}
+
+static void parse_subpart_dir(struct buffer *subpart_dir_buf,
+ struct buffer *input_buf, const char *name)
+{
+ struct subpart_dir_header hdr;
+ size_t offset = 0;
+ uint8_t *data = buffer_get(input_buf);
+ size_t size = buffer_size(input_buf);
+
+ /* Read Subpart_Dir header */
+ assert(size >= SUBPART_DIR_HEADER_SIZE);
+ offset = read_member(data, offset, sizeof(hdr.marker), &hdr.marker);
+ offset = read_member(data, offset, sizeof(hdr.num_entries),
+ &hdr.num_entries);
+ offset = read_member(data, offset, sizeof(hdr.header_version),
+ &hdr.header_version);
+ offset = read_member(data, offset, sizeof(hdr.entry_version),
+ &hdr.entry_version);
+ offset = read_member(data, offset, sizeof(hdr.header_length),
+ &hdr.header_length);
+ offset = read_member(data, offset, sizeof(hdr.checksum), &hdr.checksum);
+ memcpy(hdr.name, data + offset, sizeof(hdr.name));
+ offset += sizeof(hdr.name);
+
+ validate_subpart_dir_without_checksum((struct subpart_dir *)&hdr, name);
+
+ assert(size > subpart_dir_size(&hdr));
+ alloc_buffer(subpart_dir_buf, subpart_dir_size(&hdr), "Subpart Dir");
+ memcpy(buffer_get(subpart_dir_buf), &hdr, SUBPART_DIR_HEADER_SIZE);
+
+ /* Read Subpart Dir entries */
+ struct subpart_dir *subpart_dir = buffer_get(subpart_dir_buf);
+ struct subpart_dir_entry *e = &subpart_dir->e[0];
+ uint32_t i;
+
+ for (i = 0; i < hdr.num_entries; i++) {
+ memcpy(e[i].name, data + offset, sizeof(e[i].name));
+ offset += sizeof(e[i].name);
+ offset = read_member(data, offset, sizeof(e[i].offset),
+ &e[i].offset);
+ offset = read_member(data, offset, sizeof(e[i].length),
+ &e[i].length);
+ offset = read_member(data, offset, sizeof(e[i].rsvd),
+ &e[i].rsvd);
+ }
+
+ validate_subpart_dir_with_checksum(subpart_dir, name);
+
+ print_subpart_dir(subpart_dir);
+}
+
+/* Parse input image file to identify different sub-partitions */
+static int ifwi_parse(void)
+{
+ struct buffer *buff = &ifwi_image.input_buff;
+ const char *image_name = param.image_name;
+
+ DEBUG("Parsing IFWI image...\n");
+
+ /* Read input file */
+ if (buffer_from_file(buff, image_name)) {
+ ERROR("Failed to read input file %s.\n", image_name);
+ return -1;
+ }
+
+ INFO("Buffer %p size 0x%zx\n", buff->data, buff->size);
+
+ /* Look for BPDT signature at 4K intervals */
+ size_t offset = 0;
+ void *data = buffer_get(buff);
+
+ while (offset < buffer_size(buff)) {
+ if (read_at_le32(data, offset) == BPDT_SIGNATURE)
+ break;
+ offset += 4 * KiB;
+ }
+
+ if (offset >= buffer_size(buff)) {
+ ERROR("Image does not contain BPDT!!\n");
+ return -1;
+ }
+
+ ifwi_image.input_ifwi_start_offset = offset;
+ INFO("BPDT starts at offset 0x%zx.\n", offset);
+
+ data = (uint8_t *)data + offset;
+ size_t ifwi_size = buffer_size(buff) - offset;
+
+ /* Read BPDT and sub-partitions */
+ uintptr_t end_offset;
+
+ end_offset = ifwi_image.input_ifwi_start_offset +
+ alloc_bpdt_buffer(data, ifwi_size, 0, &ifwi_image.bpdt, "BPDT");
+
+ /* Parse S-BPDT, if any */
+ parse_sbpdt(data, ifwi_size);
+
+ /*
+ * Store end offset of IFWI. Required for copying any trailing non-IFWI
+ * part of the image.
+ * ASSUMPTION: IFWI image always ends on a 4K boundary.
+ */
+ ifwi_image.input_ifwi_end_offset = ALIGN(end_offset, 4 * KiB);
+ DEBUG("Parsing done.\n");
+
+ return 0;
+}
+
+/*
+ * This function is used by repack to count the number of BPDT and S-BPDT
+ * entries that are present. It frees the current buffers used by the entries
+ * and allocates fresh buffers that can be used for repacking. Returns BPDT
+ * entries which are empty and need to be filled in.
+ */
+static void __bpdt_reset(struct buffer *b, size_t count, size_t size)
+{
+ size_t bpdt_size = BPDT_HEADER_SIZE + count * BPDT_ENTRY_SIZE;
+
+ assert(size >= bpdt_size);
+
+ /*
+ * If buffer does not have the required size, allocate a fresh buffer.
+ */
+ if (buffer_size(b) != size) {
+ struct buffer temp;
+
+ alloc_buffer(&temp, size, b->name);
+ memcpy(buffer_get(&temp), buffer_get(b), buffer_size(b));
+ buffer_delete(b);
+ *b = temp;
+ }
+
+ struct bpdt *bpdt = buffer_get(b);
+ uint8_t *ptr = (uint8_t *)&bpdt->e[0];
+ size_t entries_size = BPDT_ENTRY_SIZE * count;
+
+ /* Zero out BPDT entries */
+ memset(ptr, 0, entries_size);
+ /* Fill any pad-space with FF */
+ memset(ptr + entries_size, 0xFF, size - bpdt_size);
+
+ bpdt->h.descriptor_count = count;
+}
+
+static void bpdt_reset(void)
+{
+ size_t i;
+ size_t bpdt_count = 0, sbpdt_count = 0, dummy_bpdt_count = 0;
+
+ /* Count number of BPDT and S-BPDT entries */
+ for (i = 0; i < MAX_SUBPARTS; i++) {
+ if (buffer_size(&ifwi_image.subpart_buf[i]) == 0) {
+ if (subparts[i].attr & MANDATORY_BPDT_ENTRY) {
+ bpdt_count++;
+ dummy_bpdt_count++;
+ }
+ continue;
+ }
+
+ if (subparts[i].attr & NON_CRITICAL_SUBPART)
+ sbpdt_count++;
+ else
+ bpdt_count++;
+ }
+
+ DEBUG("Count: BPDT = %zd, Dummy BPDT = %zd, S-BPDT = %zd\n", bpdt_count,
+ dummy_bpdt_count, sbpdt_count);
+
+ /* Update BPDT if required */
+ size_t bpdt_size = max(BPDT_MIN_SIZE,
+ BPDT_HEADER_SIZE + bpdt_count * BPDT_ENTRY_SIZE);
+ __bpdt_reset(&ifwi_image.bpdt, bpdt_count, bpdt_size);
+
+ /* Update S-BPDT if required */
+ bpdt_size = ALIGN(BPDT_HEADER_SIZE + sbpdt_count * BPDT_ENTRY_SIZE,
+ 4 * KiB);
+ __bpdt_reset(&ifwi_image.subpart_buf[S_BPDT_TYPE], sbpdt_count,
+ bpdt_size);
+}
+
+/* Initialize BPDT entries in header order */
+static void bpdt_entries_init_header_order(void)
+{
+ int i, type;
+ size_t size;
+
+ struct bpdt *bpdt, *sbpdt, *curr;
+ size_t bpdt_curr = 0, sbpdt_curr = 0, *count_ptr;
+
+ bpdt = buffer_get(&ifwi_image.bpdt);
+ sbpdt = buffer_get(&ifwi_image.subpart_buf[S_BPDT_TYPE]);
+
+ for (i = 0; i < MAX_SUBPARTS; i++) {
+ type = bpdt_header_order[i];
+ size = buffer_size(&ifwi_image.subpart_buf[type]);
+
+ if (size == 0 && !(subparts[type].attr & MANDATORY_BPDT_ENTRY))
+ continue;
+
+ if (subparts[type].attr & NON_CRITICAL_SUBPART) {
+ curr = sbpdt;
+ count_ptr = &sbpdt_curr;
+ } else {
+ curr = bpdt;
+ count_ptr = &bpdt_curr;
+ }
+
+ assert(*count_ptr < curr->h.descriptor_count);
+ curr->e[*count_ptr].type = type;
+ curr->e[*count_ptr].flags = 0;
+ curr->e[*count_ptr].offset = 0;
+ curr->e[*count_ptr].size = size;
+
+ (*count_ptr)++;
+ }
+}
+
+static void pad_buffer(struct buffer *b, size_t size)
+{
+ size_t buff_size = buffer_size(b);
+
+ assert(buff_size <= size);
+
+ if (buff_size == size)
+ return;
+
+ struct buffer temp;
+
+ alloc_buffer(&temp, size, b->name);
+ uint8_t *data = buffer_get(&temp);
+
+ memcpy(data, buffer_get(b), buff_size);
+ memset(data + buff_size, 0xFF, size - buff_size);
+
+ *b = temp;
+}
+
+/* Initialize offsets of entries using pack order */
+static void bpdt_entries_init_pack_order(void)
+{
+ int i, type;
+ struct bpdt_entry *curr;
+ size_t curr_offset, curr_end;
+
+ curr_offset = max(BPDT_MIN_SIZE, buffer_size(&ifwi_image.bpdt));
+
+ /*
+ * There are two types of sub-partitions that need to be handled here:
+ * 1. Sub-partitions that lie within the same 4K as BPDT
+ * 2. Sub-partitions that lie outside the 4K of BPDT
+ *
+ * For sub-partitions of type # 1, there is no requirement on the start
+ * or end of the sub-partition. They need to be packed in without any
+ * holes left in between. If there is any empty space left after the end
+ * of the last sub-partition in 4K of BPDT, then that space needs to be
+ * padded with FF bytes, but the size of the last sub-partition remains
+ * unchanged.
+ *
+ * For sub-partitions of type # 2, both the start and end should be a
+ * multiple of 4K. If not, then it needs to be padded with FF bytes and
+ * size adjusted such that the sub-partition ends on 4K boundary.
+ */
+
+ /* #1 Sub-partitions that lie within same 4K as BPDT */
+ struct buffer *last_bpdt_buff = &ifwi_image.bpdt;
+
+ for (i = 0; i < MAX_SUBPARTS; i++) {
+ type = bpdt_pack_order[i];
+ curr = find_entry_by_type(type);
+
+ if (!curr || curr->size == 0)
+ continue;
+
+ if (!(subparts[type].attr & LIES_WITHIN_BPDT_4K))
+ continue;
+
+ curr->offset = curr_offset;
+ curr_offset = curr->offset + curr->size;
+ last_bpdt_buff = &ifwi_image.subpart_buf[type];
+ DEBUG("type=%d, curr_offset=0x%zx, curr->offset=0x%x, curr->size=0x%x, buff_size=0x%zx\n",
+ type, curr_offset, curr->offset, curr->size,
+ buffer_size(&ifwi_image.subpart_buf[type]));
+ }
+
+ /* Pad ff bytes if there is any empty space left in BPDT 4K */
+ curr_end = ALIGN(curr_offset, 4 * KiB);
+ pad_buffer(last_bpdt_buff,
+ buffer_size(last_bpdt_buff) + (curr_end - curr_offset));
+ curr_offset = curr_end;
+
+ /* #2 Sub-partitions that lie outside of BPDT 4K */
+ for (i = 0; i < MAX_SUBPARTS; i++) {
+ type = bpdt_pack_order[i];
+ curr = find_entry_by_type(type);
+
+ if (!curr || curr->size == 0)
+ continue;
+
+ if (subparts[type].attr & LIES_WITHIN_BPDT_4K)
+ continue;
+
+ assert(curr_offset == ALIGN(curr_offset, 4 * KiB));
+ curr->offset = curr_offset;
+ curr_end = ALIGN(curr->offset + curr->size, 4 * KiB);
+ curr->size = curr_end - curr->offset;
+
+ pad_buffer(&ifwi_image.subpart_buf[type], curr->size);
+
+ curr_offset = curr_end;
+ DEBUG("type=%d, curr_offset=0x%zx, curr->offset=0x%x, curr->size=0x%x, buff_size=0x%zx\n",
+ type, curr_offset, curr->offset, curr->size,
+ buffer_size(&ifwi_image.subpart_buf[type]));
+ }
+
+ /*
+ * Update size of S-BPDT to include size of all non-critical
+ * sub-partitions.
+ *
+ * Assumption: S-BPDT always lies at the end of IFWI image.
+ */
+ curr = find_entry_by_type(S_BPDT_TYPE);
+ assert(curr);
+
+ assert(curr_offset == ALIGN(curr_offset, 4 * KiB));
+ curr->size = curr_offset - curr->offset;
+}
+
+/* Convert all members of BPDT to little-endian format */
+static void bpdt_fixup_write_buffer(struct buffer *buf)
+{
+ struct bpdt *s = buffer_get(buf);
+
+ struct bpdt_header *h = &s->h;
+ struct bpdt_entry *e = &s->e[0];
+
+ size_t count = h->descriptor_count;
+
+ size_t offset = 0;
+
+ offset = fix_member(&h->signature, offset, sizeof(h->signature));
+ offset = fix_member(&h->descriptor_count, offset,
+ sizeof(h->descriptor_count));
+ offset = fix_member(&h->bpdt_version, offset, sizeof(h->bpdt_version));
+ offset = fix_member(&h->xor_redundant_block, offset,
+ sizeof(h->xor_redundant_block));
+ offset = fix_member(&h->ifwi_version, offset, sizeof(h->ifwi_version));
+ offset = fix_member(&h->fit_tool_version, offset,
+ sizeof(h->fit_tool_version));
+
+ uint32_t i;
+
+ for (i = 0; i < count; i++) {
+ offset = fix_member(&e[i].type, offset, sizeof(e[i].type));
+ offset = fix_member(&e[i].flags, offset, sizeof(e[i].flags));
+ offset = fix_member(&e[i].offset, offset, sizeof(e[i].offset));
+ offset = fix_member(&e[i].size, offset, sizeof(e[i].size));
+ }
+}
+
+/* Write BPDT to output buffer after fixup */
+static void bpdt_write(struct buffer *dst, size_t offset, struct buffer *src)
+{
+ bpdt_fixup_write_buffer(src);
+ memcpy(buffer_get(dst) + offset, buffer_get(src), buffer_size(src));
+}
+
+/*
+ * Follows these steps to re-create image:
+ * 1. Write any non-IFWI prefix.
+ * 2. Write out BPDT header and entries.
+ * 3. Write sub-partition buffers to respective offsets.
+ * 4. Write any non-IFWI suffix.
+ *
+ * While performing the above steps, make sure that any empty holes are filled
+ * with FF.
+ */
+static void ifwi_write(const char *image_name)
+{
+ struct bpdt_entry *s = find_entry_by_type(S_BPDT_TYPE);
+
+ assert(s);
+
+ size_t ifwi_start, ifwi_end, file_end;
+
+ ifwi_start = ifwi_image.input_ifwi_start_offset;
+ ifwi_end = ifwi_start + ALIGN(s->offset + s->size, 4 * KiB);
+ file_end = ifwi_end + (buffer_size(&ifwi_image.input_buff) -
+ ifwi_image.input_ifwi_end_offset);
+
+ struct buffer b;
+
+ alloc_buffer(&b, file_end, "Final-IFWI");
+
+ uint8_t *input_data = buffer_get(&ifwi_image.input_buff);
+ uint8_t *output_data = buffer_get(&b);
+
+ DEBUG("ifwi_start:0x%zx, ifwi_end:0x%zx, file_end:0x%zx\n", ifwi_start,
+ ifwi_end, file_end);
+
+ /* Copy non-IFWI prefix, if any */
+ memcpy(output_data, input_data, ifwi_start);
+
+ DEBUG("Copied non-IFWI prefix (offset=0x0, size=0x%zx).\n", ifwi_start);
+
+ struct buffer ifwi;
+
+ buffer_splice(&ifwi, &b, ifwi_start, ifwi_end - ifwi_start);
+ uint8_t *ifwi_data = buffer_get(&ifwi);
+
+ /* Copy sub-partitions using pack_order */
+ struct bpdt_entry *curr;
+ struct buffer *subpart_buf;
+ int i, type;
+
+ for (i = 0; i < MAX_SUBPARTS; i++) {
+ type = bpdt_pack_order[i];
+
+ if (type == S_BPDT_TYPE)
+ continue;
+
+ curr = find_entry_by_type(type);
+
+ if (!curr || !curr->size)
+ continue;
+
+ subpart_buf = &ifwi_image.subpart_buf[type];
+
+ DEBUG("curr->offset=0x%x, curr->size=0x%x, type=%d, write_size=0x%zx\n",
+ curr->offset, curr->size, type, buffer_size(subpart_buf));
+
+ assert((curr->offset + buffer_size(subpart_buf)) <=
+ buffer_size(&ifwi));
+
+ memcpy(ifwi_data + curr->offset, buffer_get(subpart_buf),
+ buffer_size(subpart_buf));
+ }
+
+ /* Copy non-IFWI suffix, if any */
+ if (ifwi_end != file_end) {
+ memcpy(output_data + ifwi_end,
+ input_data + ifwi_image.input_ifwi_end_offset,
+ file_end - ifwi_end);
+ DEBUG("Copied non-IFWI suffix (offset=0x%zx,size=0x%zx).\n",
+ ifwi_end, file_end - ifwi_end);
+ }
+
+ /*
+ * Convert BPDT to little-endian format and write it to output buffer.
+ * S-BPDT is written first and then BPDT.
+ */
+ bpdt_write(&ifwi, s->offset, &ifwi_image.subpart_buf[S_BPDT_TYPE]);
+ bpdt_write(&ifwi, 0, &ifwi_image.bpdt);
+
+ if (buffer_write_file(&b, image_name)) {
+ ERROR("File write error\n");
+ exit(-1);
+ }
+
+ buffer_delete(&b);
+ printf("Image written successfully to %s.\n", image_name);
+}
+
+/*
+ * Calculate size and offset of each sub-partition again since it might have
+ * changed because of add/delete operation. Also, re-create BPDT and S-BPDT
+ * entries and write back the new IFWI image to file.
+ */
+static void ifwi_repack(void)
+{
+ bpdt_reset();
+ bpdt_entries_init_header_order();
+ bpdt_entries_init_pack_order();
+
+ struct bpdt *b = buffer_get(&ifwi_image.bpdt);
+
+ bpdt_print_entries(&b->e[0], b->h.descriptor_count, "BPDT");
+
+ b = buffer_get(&ifwi_image.subpart_buf[S_BPDT_TYPE]);
+ bpdt_print_entries(&b->e[0], b->h.descriptor_count, "S-BPDT");
+
+ DEBUG("Repack done.. writing image.\n");
+ ifwi_write(param.image_name);
+}
+
+static void init_subpart_dir_header(struct subpart_dir_header *hdr,
+ size_t count, const char *name)
+{
+ memset(hdr, 0, sizeof(*hdr));
+
+ hdr->marker = SUBPART_DIR_MARKER;
+ hdr->num_entries = count;
+ hdr->header_version = SUBPART_DIR_HEADER_VERSION_SUPPORTED;
+ hdr->entry_version = SUBPART_DIR_ENTRY_VERSION_SUPPORTED;
+ hdr->header_length = SUBPART_DIR_HEADER_SIZE;
+ memcpy(hdr->name, name, sizeof(hdr->name));
+}
+
+static size_t init_subpart_dir_entry(struct subpart_dir_entry *e,
+ struct buffer *b, size_t offset)
+{
+ memset(e, 0, sizeof(*e));
+
+ assert(strlen(b->name) <= sizeof(e->name));
+ strncpy((char *)e->name, (char *)b->name, sizeof(e->name));
+ e->offset = offset;
+ e->length = buffer_size(b);
+
+ return (offset + buffer_size(b));
+}
+
+static void init_manifest_header(struct manifest_header *hdr, size_t size)
+{
+ memset(hdr, 0, sizeof(*hdr));
+
+ hdr->header_type = 0x4;
+ assert((MANIFEST_HDR_SIZE % DWORD_SIZE) == 0);
+ hdr->header_length = MANIFEST_HDR_SIZE / DWORD_SIZE;
+ hdr->header_version = 0x10000;
+ hdr->vendor = 0x8086;
+
+ struct tm *local_time;
+ time_t curr_time;
+ char buffer[11];
+
+ curr_time = time(NULL);
+ local_time = localtime(&curr_time);
+ strftime(buffer, sizeof(buffer), "0x%Y%m%d", local_time);
+ hdr->date = strtoul(buffer, NULL, 16);
+
+ assert((size % DWORD_SIZE) == 0);
+ hdr->size = size / DWORD_SIZE;
+ hdr->id = MANIFEST_ID_MAGIC;
+}
+
+static void init_signed_pkg_info_ext(struct signed_pkg_info_ext *ext,
+ size_t count, const char *name)
+{
+ memset(ext, 0, sizeof(*ext));
+
+ ext->ext_type = SIGNED_PKG_INFO_EXT_TYPE;
+ ext->ext_length = SIGNED_PKG_INFO_EXT_SIZE + count * MODULE_SIZE;
+ memcpy(ext->name, name, sizeof(ext->name));
+}
+
+static void subpart_dir_fixup_write_buffer(struct buffer *buf)
+{
+ struct subpart_dir *s = buffer_get(buf);
+ struct subpart_dir_header *h = &s->h;
+ struct subpart_dir_entry *e = &s->e[0];
+
+ size_t count = h->num_entries;
+ size_t offset = 0;
+
+ offset = fix_member(&h->marker, offset, sizeof(h->marker));
+ offset = fix_member(&h->num_entries, offset, sizeof(h->num_entries));
+ offset = fix_member(&h->header_version, offset,
+ sizeof(h->header_version));
+ offset = fix_member(&h->entry_version, offset,
+ sizeof(h->entry_version));
+ offset = fix_member(&h->header_length, offset,
+ sizeof(h->header_length));
+ offset = fix_member(&h->checksum, offset, sizeof(h->checksum));
+ offset += sizeof(h->name);
+
+ uint32_t i;
+
+ for (i = 0; i < count; i++) {
+ offset += sizeof(e[i].name);
+ offset = fix_member(&e[i].offset, offset, sizeof(e[i].offset));
+ offset = fix_member(&e[i].length, offset, sizeof(e[i].length));
+ offset = fix_member(&e[i].rsvd, offset, sizeof(e[i].rsvd));
+ }
+}
+
+static void create_subpart(struct buffer *dst, struct buffer *info[],
+ size_t count, const char *name)
+{
+ struct buffer subpart_dir_buff;
+ size_t size = SUBPART_DIR_HEADER_SIZE + count * SUBPART_DIR_ENTRY_SIZE;
+
+ alloc_buffer(&subpart_dir_buff, size, "subpart-dir");
+
+ struct subpart_dir_header *h = buffer_get(&subpart_dir_buff);
+ struct subpart_dir_entry *e = (struct subpart_dir_entry *)(h + 1);
+
+ init_subpart_dir_header(h, count, name);
+
+ size_t curr_offset = size;
+ size_t i;
+
+ for (i = 0; i < count; i++) {
+ curr_offset = init_subpart_dir_entry(&e[i], info[i],
+ curr_offset);
+ }
+
+ alloc_buffer(dst, curr_offset, name);
+ uint8_t *data = buffer_get(dst);
+
+ for (i = 0; i < count; i++) {
+ memcpy(data + e[i].offset, buffer_get(info[i]),
+ buffer_size(info[i]));
+ }
+
+ h->checksum = calc_checksum(buffer_get(&subpart_dir_buff));
+
+ struct subpart_dir *dir = buffer_get(&subpart_dir_buff);
+
+ print_subpart_dir(dir);
+
+ subpart_dir_fixup_write_buffer(&subpart_dir_buff);
+ memcpy(data, dir, buffer_size(&subpart_dir_buff));
+
+ buffer_delete(&subpart_dir_buff);
+}
+
+static enum ifwi_ret ibbp_dir_add(int type)
+{
+ struct buffer manifest;
+ struct signed_pkg_info_ext *ext;
+ struct buffer ibbl;
+ struct buffer ibb;
+
+#define DUMMY_IBB_SIZE (4 * KiB)
+
+ assert(type == IBB_TYPE);
+
+ /*
+ * Entry # 1 - IBBP.man
+ * Contains manifest header and signed pkg info extension.
+ */
+ size_t size = MANIFEST_HDR_SIZE + SIGNED_PKG_INFO_EXT_SIZE;
+
+ alloc_buffer(&manifest, size, "IBBP.man");
+
+ struct manifest_header *man_hdr = buffer_get(&manifest);
+
+ init_manifest_header(man_hdr, size);
+
+ ext = (struct signed_pkg_info_ext *)(man_hdr + 1);
+
+ init_signed_pkg_info_ext(ext, 0, subparts[type].name);
+
+ /* Entry # 2 - IBBL */
+ if (buffer_from_file(&ibbl, param.file_name))
+ return COMMAND_ERR;
+
+ /* Entry # 3 - IBB */
+ alloc_buffer(&ibb, DUMMY_IBB_SIZE, "IBB");
+ memset(buffer_get(&ibb), 0xFF, DUMMY_IBB_SIZE);
+
+ /* Create subpartition */
+ struct buffer *info[] = {
+ &manifest, &ibbl, &ibb,
+ };
+ create_subpart(&ifwi_image.subpart_buf[type], &info[0],
+ ARRAY_SIZE(info), subparts[type].name);
+
+ return REPACK_REQUIRED;
+}
+
+static enum ifwi_ret ifwi_raw_add(int type)
+{
+ if (buffer_from_file(&ifwi_image.subpart_buf[type], param.file_name))
+ return COMMAND_ERR;
+
+ printf("Sub-partition %s(%d) added from file %s.\n", param.subpart_name,
+ type, param.file_name);
+ return REPACK_REQUIRED;
+}
+
+static enum ifwi_ret ifwi_dir_add(int type)
+{
+ if (!(subparts[type].attr & CONTAINS_DIR) ||
+ !subparts[type].dir_ops.dir_add) {
+ ERROR("Sub-Partition %s(%d) does not support dir ops.\n",
+ subparts[type].name, type);
+ return COMMAND_ERR;
+ }
+
+ if (!param.dentry_name) {
+ ERROR("%s: -e option required\n", __func__);
+ return COMMAND_ERR;
+ }
+
+ enum ifwi_ret ret = subparts[type].dir_ops.dir_add(type);
+
+ if (ret != COMMAND_ERR)
+ printf("Sub-partition %s(%d) entry %s added from file %s.\n",
+ param.subpart_name, type, param.dentry_name,
+ param.file_name);
+ else
+ ERROR("Sub-partition dir operation failed.\n");
+
+ return ret;
+}
+
+static enum ifwi_ret ifwi_add(void)
+{
+ if (!param.file_name) {
+ ERROR("%s: -f option required\n", __func__);
+ return COMMAND_ERR;
+ }
+
+ if (!param.subpart_name) {
+ ERROR("%s: -n option required\n", __func__);
+ return COMMAND_ERR;
+ }
+
+ int type = find_type_by_name(param.subpart_name);
+
+ if (type == -1)
+ return COMMAND_ERR;
+
+ const struct subpart_info *curr_subpart = &subparts[type];
+
+ if (curr_subpart->attr & AUTO_GENERATED) {
+ ERROR("Cannot add auto-generated sub-partitions.\n");
+ return COMMAND_ERR;
+ }
+
+ if (buffer_size(&ifwi_image.subpart_buf[type])) {
+ ERROR("Image already contains sub-partition %s(%d).\n",
+ param.subpart_name, type);
+ return COMMAND_ERR;
+ }
+
+ if (param.dir_ops)
+ return ifwi_dir_add(type);
+
+ return ifwi_raw_add(type);
+}
+
+static enum ifwi_ret ifwi_delete(void)
+{
+ if (!param.subpart_name) {
+ ERROR("%s: -n option required\n", __func__);
+ return COMMAND_ERR;
+ }
+
+ int type = find_type_by_name(param.subpart_name);
+
+ if (type == -1)
+ return COMMAND_ERR;
+
+ const struct subpart_info *curr_subpart = &subparts[type];
+
+ if (curr_subpart->attr & AUTO_GENERATED) {
+ ERROR("Cannot delete auto-generated sub-partitions.\n");
+ return COMMAND_ERR;
+ }
+
+ if (buffer_size(&ifwi_image.subpart_buf[type]) == 0) {
+ printf("Image does not contain sub-partition %s(%d).\n",
+ param.subpart_name, type);
+ return NO_ACTION_REQUIRED;
+ }
+
+ buffer_delete(&ifwi_image.subpart_buf[type]);
+ printf("Sub-Partition %s(%d) deleted.\n", subparts[type].name, type);
+ return REPACK_REQUIRED;
+}
+
+static enum ifwi_ret ifwi_dir_extract(int type)
+{
+ if (!(subparts[type].attr & CONTAINS_DIR)) {
+ ERROR("Sub-Partition %s(%d) does not support dir ops.\n",
+ subparts[type].name, type);
+ return COMMAND_ERR;
+ }
+
+ if (!param.dentry_name) {
+ ERROR("%s: -e option required.\n", __func__);
+ return COMMAND_ERR;
+ }
+
+ struct buffer subpart_dir_buff;
+
+ parse_subpart_dir(&subpart_dir_buff, &ifwi_image.subpart_buf[type],
+ subparts[type].name);
+
+ uint32_t i;
+ struct subpart_dir *s = buffer_get(&subpart_dir_buff);
+
+ for (i = 0; i < s->h.num_entries; i++) {
+ if (!strncmp((char *)s->e[i].name, param.dentry_name,
+ sizeof(s->e[i].name)))
+ break;
+ }
+
+ if (i == s->h.num_entries) {
+ ERROR("Entry %s not found in subpartition for %s.\n",
+ param.dentry_name, param.subpart_name);
+ exit(-1);
+ }
+
+ struct buffer dst;
+
+ DEBUG("Splicing buffer at 0x%x size 0x%x\n", s->e[i].offset,
+ s->e[i].length);
+ buffer_splice(&dst, &ifwi_image.subpart_buf[type], s->e[i].offset,
+ s->e[i].length);
+
+ if (buffer_write_file(&dst, param.file_name))
+ return COMMAND_ERR;
+
+ printf("Sub-Partition %s(%d), entry(%s) stored in %s.\n",
+ param.subpart_name, type, param.dentry_name, param.file_name);
+
+ return NO_ACTION_REQUIRED;
+}
+
+static enum ifwi_ret ifwi_raw_extract(int type)
+{
+ if (buffer_write_file(&ifwi_image.subpart_buf[type], param.file_name))
+ return COMMAND_ERR;
+
+ printf("Sub-Partition %s(%d) stored in %s.\n", param.subpart_name, type,
+ param.file_name);
+
+ return NO_ACTION_REQUIRED;
+}
+
+static enum ifwi_ret ifwi_extract(void)
+{
+ if (!param.file_name) {
+ ERROR("%s: -f option required\n", __func__);
+ return COMMAND_ERR;
+ }
+
+ if (!param.subpart_name) {
+ ERROR("%s: -n option required\n", __func__);
+ return COMMAND_ERR;
+ }
+
+ int type = find_type_by_name(param.subpart_name);
+
+ if (type == -1)
+ return COMMAND_ERR;
+
+ if (type == S_BPDT_TYPE) {
+ INFO("Tool does not support raw extract for %s\n",
+ param.subpart_name);
+ return NO_ACTION_REQUIRED;
+ }
+
+ if (buffer_size(&ifwi_image.subpart_buf[type]) == 0) {
+ ERROR("Image does not contain sub-partition %s(%d).\n",
+ param.subpart_name, type);
+ return COMMAND_ERR;
+ }
+
+ INFO("Extracting sub-partition %s(%d).\n", param.subpart_name, type);
+ if (param.dir_ops)
+ return ifwi_dir_extract(type);
+
+ return ifwi_raw_extract(type);
+}
+
+static enum ifwi_ret ifwi_print(void)
+{
+ verbose += 2;
+
+ struct bpdt *b = buffer_get(&ifwi_image.bpdt);
+
+ bpdt_print_header(&b->h, "BPDT");
+ bpdt_print_entries(&b->e[0], b->h.descriptor_count, "BPDT");
+
+ b = buffer_get(&ifwi_image.subpart_buf[S_BPDT_TYPE]);
+ bpdt_print_header(&b->h, "S-BPDT");
+ bpdt_print_entries(&b->e[0], b->h.descriptor_count, "S-BPDT");
+
+ if (param.dir_ops == 0) {
+ verbose -= 2;
+ return NO_ACTION_REQUIRED;
+ }
+
+ int i;
+ struct buffer subpart_dir_buf;
+
+ for (i = 0; i < MAX_SUBPARTS ; i++) {
+ if (!(subparts[i].attr & CONTAINS_DIR) ||
+ (buffer_size(&ifwi_image.subpart_buf[i]) == 0))
+ continue;
+
+ parse_subpart_dir(&subpart_dir_buf, &ifwi_image.subpart_buf[i],
+ subparts[i].name);
+ buffer_delete(&subpart_dir_buf);
+ }
+
+ verbose -= 2;
+
+ return NO_ACTION_REQUIRED;
+}
+
+static enum ifwi_ret ifwi_raw_replace(int type)
+{
+ buffer_delete(&ifwi_image.subpart_buf[type]);
+ return ifwi_raw_add(type);
+}
+
+static enum ifwi_ret ifwi_dir_replace(int type)
+{
+ if (!(subparts[type].attr & CONTAINS_DIR)) {
+ ERROR("Sub-Partition %s(%d) does not support dir ops.\n",
+ subparts[type].name, type);
+ return COMMAND_ERR;
+ }
+
+ if (!param.dentry_name) {
+ ERROR("%s: -e option required.\n", __func__);
+ return COMMAND_ERR;
+ }
+
+ struct buffer subpart_dir_buf;
+
+ parse_subpart_dir(&subpart_dir_buf, &ifwi_image.subpart_buf[type],
+ subparts[type].name);
+
+ uint32_t i;
+ struct subpart_dir *s = buffer_get(&subpart_dir_buf);
+
+ for (i = 0; i < s->h.num_entries; i++) {
+ if (!strcmp((char *)s->e[i].name, param.dentry_name))
+ break;
+ }
+
+ if (i == s->h.num_entries) {
+ ERROR("Entry %s not found in subpartition for %s.\n",
+ param.dentry_name, param.subpart_name);
+ exit(-1);
+ }
+
+ struct buffer b;
+
+ if (buffer_from_file(&b, param.file_name)) {
+ ERROR("Failed to read %s\n", param.file_name);
+ exit(-1);
+ }
+
+ struct buffer dst;
+ size_t dst_size = buffer_size(&ifwi_image.subpart_buf[type]) +
+ buffer_size(&b) - s->e[i].length;
+ size_t subpart_start = s->e[i].offset;
+ size_t subpart_end = s->e[i].offset + s->e[i].length;
+
+ alloc_buffer(&dst, dst_size, ifwi_image.subpart_buf[type].name);
+
+ uint8_t *src_data = buffer_get(&ifwi_image.subpart_buf[type]);
+ uint8_t *dst_data = buffer_get(&dst);
+ size_t curr_offset = 0;
+
+ /* Copy data before the sub-partition entry */
+ memcpy(dst_data + curr_offset, src_data, subpart_start);
+ curr_offset += subpart_start;
+
+ /* Copy sub-partition entry */
+ memcpy(dst_data + curr_offset, buffer_get(&b), buffer_size(&b));
+ curr_offset += buffer_size(&b);
+
+ /* Copy remaining data */
+ memcpy(dst_data + curr_offset, src_data + subpart_end,
+ buffer_size(&ifwi_image.subpart_buf[type]) - subpart_end);
+
+ /* Update sub-partition buffer */
+ int offset = s->e[i].offset;
+
+ buffer_delete(&ifwi_image.subpart_buf[type]);
+ ifwi_image.subpart_buf[type] = dst;
+
+ /* Update length of entry in the subpartition */
+ s->e[i].length = buffer_size(&b);
+ buffer_delete(&b);
+
+ /* Adjust offsets of affected entries in subpartition */
+ offset = s->e[i].offset - offset;
+ for (; i < s->h.num_entries; i++)
+ s->e[i].offset += offset;
+
+ /* Re-calculate checksum */
+ s->h.checksum = calc_checksum(s);
+
+ /* Convert members to litte-endian */
+ subpart_dir_fixup_write_buffer(&subpart_dir_buf);
+
+ memcpy(dst_data, buffer_get(&subpart_dir_buf),
+ buffer_size(&subpart_dir_buf));
+
+ buffer_delete(&subpart_dir_buf);
+
+ printf("Sub-partition %s(%d) entry %s replaced from file %s.\n",
+ param.subpart_name, type, param.dentry_name, param.file_name);
+
+ return REPACK_REQUIRED;
+}
+
+static enum ifwi_ret ifwi_replace(void)
+{
+ if (!param.file_name) {
+ ERROR("%s: -f option required\n", __func__);
+ return COMMAND_ERR;
+ }
+
+ if (!param.subpart_name) {
+ ERROR("%s: -n option required\n", __func__);
+ return COMMAND_ERR;
+ }
+
+ int type = find_type_by_name(param.subpart_name);
+
+ if (type == -1)
+ return COMMAND_ERR;
+
+ const struct subpart_info *curr_subpart = &subparts[type];
+
+ if (curr_subpart->attr & AUTO_GENERATED) {
+ ERROR("Cannot replace auto-generated sub-partitions.\n");
+ return COMMAND_ERR;
+ }
+
+ if (buffer_size(&ifwi_image.subpart_buf[type]) == 0) {
+ ERROR("Image does not contain sub-partition %s(%d).\n",
+ param.subpart_name, type);
+ return COMMAND_ERR;
+ }
+
+ if (param.dir_ops)
+ return ifwi_dir_replace(type);
+
+ return ifwi_raw_replace(type);
+}
+
+static enum ifwi_ret ifwi_create(void)
+{
+ /*
+ * Create peels off any non-IFWI content present in the input buffer and
+ * creates output file with only the IFWI present.
+ */
+
+ if (!param.file_name) {
+ ERROR("%s: -f option required\n", __func__);
+ return COMMAND_ERR;
+ }
+
+ /* Peel off any non-IFWI prefix */
+ buffer_seek(&ifwi_image.input_buff,
+ ifwi_image.input_ifwi_start_offset);
+ /* Peel off any non-IFWI suffix */
+ buffer_set_size(&ifwi_image.input_buff,
+ ifwi_image.input_ifwi_end_offset -
+ ifwi_image.input_ifwi_start_offset);
+
+ /*
+ * Adjust start and end offset of IFWI now that non-IFWI prefix is gone.
+ */
+ ifwi_image.input_ifwi_end_offset -= ifwi_image.input_ifwi_start_offset;
+ ifwi_image.input_ifwi_start_offset = 0;
+
+ param.image_name = param.file_name;
+
+ return REPACK_REQUIRED;
+}
+
+struct command {
+ const char *name;
+ const char *optstring;
+ enum ifwi_ret (*function)(void);
+};
+
+static const struct command commands[] = {
+ {"add", "f:n:e:dvh?", ifwi_add},
+ {"create", "f:vh?", ifwi_create},
+ {"delete", "f:n:vh?", ifwi_delete},
+ {"extract", "f:n:e:dvh?", ifwi_extract},
+ {"print", "dh?", ifwi_print},
+ {"replace", "f:n:e:dvh?", ifwi_replace},
+};
+
+static struct option long_options[] = {
+ {"subpart_dentry", required_argument, 0, 'e'},
+ {"file", required_argument, 0, 'f'},
+ {"help", required_argument, 0, 'h'},
+ {"name", required_argument, 0, 'n'},
+ {"dir_ops", no_argument, 0, 'd'},
+ {"verbose", no_argument, 0, 'v'},
+ {NULL, 0, 0, 0 }
+};
+
+static void usage(const char *name)
+{
+ printf("ifwitool: Utility for IFWI manipulation\n\n"
+ "USAGE:\n"
+ " %s [-h]\n"
+ " %s FILE COMMAND [PARAMETERS]\n\n"
+ "COMMANDs:\n"
+ " add -f FILE -n NAME [-d -e ENTRY]\n"
+ " create -f FILE\n"
+ " delete -n NAME\n"
+ " extract -f FILE -n NAME [-d -e ENTRY]\n"
+ " print [-d]\n"
+ " replace -f FILE -n NAME [-d -e ENTRY]\n"
+ "OPTIONs:\n"
+ " -f FILE : File to read/write/create/extract\n"
+ " -d : Perform directory operation\n"
+ " -e ENTRY: Name of directory entry to operate on\n"
+ " -v : Verbose level\n"
+ " -h : Help message\n"
+ " -n NAME : Name of sub-partition to operate on\n",
+ name, name
+ );
+
+ printf("\nNAME should be one of:\n");
+ int i;
+
+ for (i = 0; i < MAX_SUBPARTS; i++)
+ printf("%s(%s)\n", subparts[i].name, subparts[i].readable_name);
+ printf("\n");
+}
+
+int main(int argc, char **argv)
+{
+ if (argc < 3) {
+ usage(argv[0]);
+ return 1;
+ }
+
+ param.image_name = argv[1];
+ char *cmd = argv[2];
+
+ optind += 2;
+
+ uint32_t i;
+
+ for (i = 0; i < ARRAY_SIZE(commands); i++) {
+ if (strcmp(cmd, commands[i].name) != 0)
+ continue;
+
+ int c;
+
+ while (1) {
+ int option_index;
+
+ c = getopt_long(argc, argv, commands[i].optstring,
+ long_options, &option_index);
+
+ if (c == -1)
+ break;
+
+ /* Filter out illegal long options */
+ if (!strchr(commands[i].optstring, c)) {
+ ERROR("%s: invalid option -- '%c'\n", argv[0],
+ c);
+ c = '?';
+ }
+
+ switch (c) {
+ case 'n':
+ param.subpart_name = optarg;
+ break;
+ case 'f':
+ param.file_name = optarg;
+ break;
+ case 'd':
+ param.dir_ops = 1;
+ break;
+ case 'e':
+ param.dentry_name = optarg;
+ break;
+ case 'v':
+ verbose++;
+ break;
+ case 'h':
+ case '?':
+ usage(argv[0]);
+ return 1;
+ default:
+ break;
+ }
+ }
+
+ if (ifwi_parse()) {
+ ERROR("%s: ifwi parsing failed\n", argv[0]);
+ return 1;
+ }
+
+ enum ifwi_ret ret = commands[i].function();
+
+ if (ret == COMMAND_ERR) {
+ ERROR("%s: failed execution\n", argv[0]);
+ return 1;
+ }
+
+ if (ret == REPACK_REQUIRED)
+ ifwi_repack();
+
+ return 0;
+ }
+
+ ERROR("%s: invalid command\n", argv[0]);
+ return 1;
+}
diff --git a/tools/logos/u-boot_logo.svg b/tools/logos/u-boot_logo.svg
index e45ef2e..3b743af 100644
--- a/tools/logos/u-boot_logo.svg
+++ b/tools/logos/u-boot_logo.svg
@@ -85,13 +85,6 @@
inkscape:groupmode="layer"
id="layer1"
transform="translate(0,0)">
- <rect
- style="fill:#000000;fill-opacity:1;stroke:none;stroke-width:0"
- id="rect31"
- width="186"
- height="186"
- x="0"
- y="0" />
<circle
style="fill:#004466;fill-opacity:1;stroke-width:0;stroke:none"
id="path835"
diff --git a/tools/mkenvimage.c b/tools/mkenvimage.c
index 75967d0..a8eebab 100644
--- a/tools/mkenvimage.c
+++ b/tools/mkenvimage.c
@@ -65,10 +65,12 @@
exit(EXIT_FAILURE);
}
+#define CHUNK_SIZE 4096
+
int main(int argc, char **argv)
{
uint32_t crc, targetendian_crc;
- const char *txt_filename = NULL, *bin_filename = NULL;
+ const char *bin_filename = NULL;
int txt_fd, bin_fd;
unsigned char *dataptr, *envptr;
unsigned char *filebuf = NULL;
@@ -76,12 +78,11 @@
int bigendian = 0;
int redundant = 0;
unsigned char padbyte = 0xff;
+ int readbytes = 0;
int option;
int ret = EXIT_SUCCESS;
- struct stat txt_file_stat;
-
int fp, ep;
const char *prg;
@@ -156,64 +157,34 @@
/* Open the input file ... */
if (optind >= argc || strcmp(argv[optind], "-") == 0) {
- int readbytes = 0;
- int readlen = sizeof(*envptr) * 4096;
txt_fd = STDIN_FILENO;
-
- do {
- filebuf = realloc(filebuf, filesize + readlen);
- if (!filebuf) {
- fprintf(stderr, "Can't realloc memory for the input file buffer\n");
- return EXIT_FAILURE;
- }
- readbytes = read(txt_fd, filebuf + filesize, readlen);
- if (readbytes < 0) {
- fprintf(stderr, "Error while reading stdin: %s\n",
- strerror(errno));
- return EXIT_FAILURE;
- }
- filesize += readbytes;
- } while (readbytes == readlen);
-
} else {
- txt_filename = argv[optind];
- txt_fd = open(txt_filename, O_RDONLY);
+ txt_fd = open(argv[optind], O_RDONLY);
if (txt_fd == -1) {
fprintf(stderr, "Can't open \"%s\": %s\n",
- txt_filename, strerror(errno));
+ argv[optind], strerror(errno));
return EXIT_FAILURE;
}
- /* ... and check it */
- ret = fstat(txt_fd, &txt_file_stat);
- if (ret == -1) {
- fprintf(stderr, "Can't stat() on \"%s\": %s\n",
- txt_filename, strerror(errno));
- return EXIT_FAILURE;
- }
-
- filesize = txt_file_stat.st_size;
-
- filebuf = mmap(NULL, sizeof(*envptr) * filesize, PROT_READ,
- MAP_PRIVATE, txt_fd, 0);
- if (filebuf == MAP_FAILED) {
- fprintf(stderr, "mmap (%zu bytes) failed: %s\n",
- sizeof(*envptr) * filesize,
- strerror(errno));
- fprintf(stderr, "Falling back to read()\n");
-
- filebuf = malloc(sizeof(*envptr) * filesize);
- ret = read(txt_fd, filebuf, sizeof(*envptr) * filesize);
- if (ret != sizeof(*envptr) * filesize) {
- fprintf(stderr, "Can't read the whole input file (%zu bytes): %s\n",
- sizeof(*envptr) * filesize,
- strerror(errno));
-
- return EXIT_FAILURE;
- }
- }
- ret = close(txt_fd);
}
+ do {
+ filebuf = realloc(filebuf, filesize + CHUNK_SIZE);
+ if (!filebuf) {
+ fprintf(stderr, "Can't realloc memory for the input file buffer\n");
+ return EXIT_FAILURE;
+ }
+ readbytes = read(txt_fd, filebuf + filesize, CHUNK_SIZE);
+ if (readbytes < 0) {
+ fprintf(stderr, "Error while reading: %s\n",
+ strerror(errno));
+ return EXIT_FAILURE;
+ }
+ filesize += readbytes;
+ } while (readbytes > 0);
+
+ if (txt_fd != STDIN_FILENO)
+ ret = close(txt_fd);
+
/* Parse a byte at time until reaching the file OR until the environment fills
* up. Check ep against envsize - 1 to allow for extra trailing '\0'. */
for (fp = 0, ep = 0 ; fp < filesize && ep < envsize - 1; fp++) {
diff --git a/tools/mkimage.c b/tools/mkimage.c
index d1e1a67..4217188 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -105,7 +105,7 @@
" -F => re-sign existing FIT image\n"
" -p => place external data at a static position\n"
" -r => mark keys used as 'required' in dtb\n"
- " -N => engine to use for signing (pkcs11)\n");
+ " -N => openssl engine to use for signing\n");
#else
fprintf(stderr,
"Signing / verified boot not supported (CONFIG_FIT_SIGNATURE undefined)\n");
diff --git a/tools/moveconfig.py b/tools/moveconfig.py
index 1a214c5..0bbc7c1 100755
--- a/tools/moveconfig.py
+++ b/tools/moveconfig.py
@@ -354,6 +354,26 @@
CONFIG_LEN = len('CONFIG_')
+SIZES = {
+ "SZ_1": 0x00000001, "SZ_2": 0x00000002,
+ "SZ_4": 0x00000004, "SZ_8": 0x00000008,
+ "SZ_16": 0x00000010, "SZ_32": 0x00000020,
+ "SZ_64": 0x00000040, "SZ_128": 0x00000080,
+ "SZ_256": 0x00000100, "SZ_512": 0x00000200,
+ "SZ_1K": 0x00000400, "SZ_2K": 0x00000800,
+ "SZ_4K": 0x00001000, "SZ_8K": 0x00002000,
+ "SZ_16K": 0x00004000, "SZ_32K": 0x00008000,
+ "SZ_64K": 0x00010000, "SZ_128K": 0x00020000,
+ "SZ_256K": 0x00040000, "SZ_512K": 0x00080000,
+ "SZ_1M": 0x00100000, "SZ_2M": 0x00200000,
+ "SZ_4M": 0x00400000, "SZ_8M": 0x00800000,
+ "SZ_16M": 0x01000000, "SZ_32M": 0x02000000,
+ "SZ_64M": 0x04000000, "SZ_128M": 0x08000000,
+ "SZ_256M": 0x10000000, "SZ_512M": 0x20000000,
+ "SZ_1G": 0x40000000, "SZ_2G": 0x80000000,
+ "SZ_4G": 0x100000000
+}
+
### helper functions ###
def get_devnull():
"""Get the file object of '/dev/null' device."""
@@ -777,6 +797,25 @@
with open('README', 'w') as f:
f.write(''.join(newlines))
+def try_expand(line):
+ """If value looks like an expression, try expanding it
+ Otherwise just return the existing value
+ """
+ if line.find('=') == -1:
+ return line
+
+ try:
+ cfg, val = re.split("=", line)
+ val= val.strip('\"')
+ if re.search("[*+-/]|<<|SZ_+|\(([^\)]+)\)", val):
+ newval = hex(eval(val, SIZES))
+ print "\tExpanded expression %s to %s" % (val, newval)
+ return cfg+'='+newval
+ except:
+ print "\tFailed to expand expression in %s" % line
+
+ return line
+
### classes ###
class Progress:
@@ -891,6 +930,8 @@
else:
new_val = not_set
+ new_val = try_expand(new_val)
+
for line in dotconfig_lines:
line = line.rstrip()
if line.startswith(config + '=') or line == not_set:
diff --git a/tools/patman/command.py b/tools/patman/command.py
index 14edcda..16299f3 100644
--- a/tools/patman/command.py
+++ b/tools/patman/command.py
@@ -108,8 +108,8 @@
return result
def Output(*cmd, **kwargs):
- raise_on_error = kwargs.get('raise_on_error', True)
- return RunPipe([cmd], capture=True, raise_on_error=raise_on_error).stdout
+ kwargs['raise_on_error'] = kwargs.get('raise_on_error', True)
+ return RunPipe([cmd], capture=True, **kwargs).stdout
def OutputOneLine(*cmd, **kwargs):
raise_on_error = kwargs.pop('raise_on_error', True)
diff --git a/tools/patman/cros_subprocess.py b/tools/patman/cros_subprocess.py
index ebd4300..06be64c 100644
--- a/tools/patman/cros_subprocess.py
+++ b/tools/patman/cros_subprocess.py
@@ -54,7 +54,7 @@
"""
def __init__(self, args, stdin=None, stdout=PIPE_PTY, stderr=PIPE_PTY,
- shell=False, cwd=None, env=None, **kwargs):
+ shell=False, cwd=None, env=None, binary=False, **kwargs):
"""Cut-down constructor
Args:
@@ -72,6 +72,7 @@
"""
stdout_pty = None
stderr_pty = None
+ self.binary = binary
if stdout == PIPE_PTY:
stdout_pty = pty.openpty()
@@ -100,6 +101,19 @@
if kwargs:
raise ValueError("Unit tests do not test extra args - please add tests")
+ def ConvertData(self, data):
+ """Convert stdout/stderr data to the correct format for output
+
+ Args:
+ data: Data to convert, or None for ''
+
+ Returns:
+ Converted data, as bytes
+ """
+ if data is None:
+ return b''
+ return data
+
def CommunicateFilter(self, output):
"""Interact with process: Read data from stdout and stderr.
@@ -156,11 +170,11 @@
self.stdin.close()
if self.stdout:
read_set.append(self.stdout)
- stdout = []
+ stdout = b''
if self.stderr and self.stderr != self.stdout:
read_set.append(self.stderr)
- stderr = []
- combined = []
+ stderr = b''
+ combined = b''
input_offset = 0
while read_set or write_set:
@@ -186,46 +200,40 @@
write_set.remove(self.stdin)
if self.stdout in rlist:
- data = ""
+ data = b''
# We will get an error on read if the pty is closed
try:
data = os.read(self.stdout.fileno(), 1024)
except OSError:
pass
- if data == "":
+ if not len(data):
self.stdout.close()
read_set.remove(self.stdout)
else:
- stdout.append(data)
- combined.append(data)
+ stdout += data
+ combined += data
if output:
output(sys.stdout, data)
if self.stderr in rlist:
- data = ""
+ data = b''
# We will get an error on read if the pty is closed
try:
data = os.read(self.stderr.fileno(), 1024)
except OSError:
pass
- if data == "":
+ if not len(data):
self.stderr.close()
read_set.remove(self.stderr)
else:
- stderr.append(data)
- combined.append(data)
+ stderr += data
+ combined += data
if output:
output(sys.stderr, data)
# All data exchanged. Translate lists into strings.
- if stdout is not None:
- stdout = ''.join(stdout)
- else:
- stdout = ''
- if stderr is not None:
- stderr = ''.join(stderr)
- else:
- stderr = ''
- combined = ''.join(combined)
+ stdout = self.ConvertData(stdout)
+ stderr = self.ConvertData(stderr)
+ combined = self.ConvertData(combined)
# Translate newlines, if requested. We cannot let the file
# object do the translation: It is based on stdio, which is
diff --git a/tools/patman/func_test.py b/tools/patman/func_test.py
index d79e716..50a2741 100644
--- a/tools/patman/func_test.py
+++ b/tools/patman/func_test.py
@@ -12,15 +12,20 @@
import tempfile
import unittest
+try:
+ from StringIO import StringIO
+except ImportError:
+ from io import StringIO
+
import gitutil
import patchstream
import settings
+import tools
@contextlib.contextmanager
def capture():
import sys
- from cStringIO import StringIO
oldout,olderr = sys.stdout, sys.stderr
try:
out=[StringIO(), StringIO()]
@@ -124,10 +129,10 @@
"""
process_tags = True
ignore_bad_tags = True
- stefan = u'Stefan Brüns <stefan.bruens@rwth-aachen.de>'
+ stefan = b'Stefan Br\xc3\xbcns <stefan.bruens@rwth-aachen.de>'.decode('utf-8')
rick = 'Richard III <richard@palace.gov>'
- mel = u'Lord Mëlchett <clergy@palace.gov>'
- ed = u'Lond Edmund Blackaddër <weasel@blackadder.org'
+ mel = b'Lord M\xc3\xablchett <clergy@palace.gov>'.decode('utf-8')
+ ed = b'Lond Edmund Blackadd\xc3\xabr <weasel@blackadder.org'.decode('utf-8')
fred = 'Fred Bloggs <f.bloggs@napier.net>'
add_maintainers = [stefan, rick]
dry_run = True
@@ -159,7 +164,6 @@
os.remove(cc_file)
lines = out[0].splitlines()
- #print '\n'.join(lines)
self.assertEqual('Cleaned %s patches' % len(series.commits), lines[0])
self.assertEqual('Change log missing for v2', lines[1])
self.assertEqual('Change log missing for v3', lines[2])
@@ -174,27 +178,30 @@
while 'Cc:' in lines[line]:
line += 1
self.assertEqual('To: u-boot@lists.denx.de', lines[line])
- self.assertEqual('Cc: %s' % stefan.encode('utf-8'), lines[line + 1])
+ self.assertEqual('Cc: %s' % tools.FromUnicode(stefan),
+ lines[line + 1])
self.assertEqual('Version: 3', lines[line + 2])
self.assertEqual('Prefix:\t RFC', lines[line + 3])
self.assertEqual('Cover: 4 lines', lines[line + 4])
line += 5
- self.assertEqual(' Cc: %s' % mel.encode('utf-8'), lines[line + 0])
- self.assertEqual(' Cc: %s' % rick, lines[line + 1])
- self.assertEqual(' Cc: %s' % fred, lines[line + 2])
- self.assertEqual(' Cc: %s' % ed.encode('utf-8'), lines[line + 3])
+ self.assertEqual(' Cc: %s' % fred, lines[line + 0])
+ self.assertEqual(' Cc: %s' % tools.FromUnicode(ed),
+ lines[line + 1])
+ self.assertEqual(' Cc: %s' % tools.FromUnicode(mel),
+ lines[line + 2])
+ self.assertEqual(' Cc: %s' % rick, lines[line + 3])
expected = ('Git command: git send-email --annotate '
'--in-reply-to="%s" --to "u-boot@lists.denx.de" '
'--cc "%s" --cc-cmd "%s --cc-cmd %s" %s %s'
% (in_reply_to, stefan, sys.argv[0], cc_file, cover_fname,
- ' '.join(args))).encode('utf-8')
+ ' '.join(args)))
line += 4
- self.assertEqual(expected, lines[line])
+ self.assertEqual(expected, tools.ToUnicode(lines[line]))
- self.assertEqual(('%s %s, %s' % (args[0], rick, stefan))
- .encode('utf-8'), cc_lines[0])
- self.assertEqual(('%s %s, %s, %s, %s' % (args[1], fred, rick, stefan,
- ed)).encode('utf-8'), cc_lines[1])
+ self.assertEqual(('%s %s, %s' % (args[0], rick, stefan)),
+ tools.ToUnicode(cc_lines[0]))
+ self.assertEqual(('%s %s, %s, %s, %s' % (args[1], fred, ed, rick,
+ stefan)), tools.ToUnicode(cc_lines[1]))
expected = '''
This is a test of how the cover
@@ -223,7 +230,6 @@
'''
lines = open(cover_fname).read().splitlines()
- #print '\n'.join(lines)
self.assertEqual(
'Subject: [RFC PATCH v3 0/2] test: A test patch series',
lines[3])
@@ -231,7 +237,6 @@
for i, fname in enumerate(args):
lines = open(fname).read().splitlines()
- #print '\n'.join(lines)
subject = [line for line in lines if line.startswith('Subject')]
self.assertEqual('Subject: [RFC %d/%d]' % (i + 1, count),
subject[0][:18])
diff --git a/tools/patman/gitutil.py b/tools/patman/gitutil.py
index 9905bb0..dce7fa2 100644
--- a/tools/patman/gitutil.py
+++ b/tools/patman/gitutil.py
@@ -12,6 +12,7 @@
import checkpatch
import settings
+import tools
# True to use --no-decorate - we check this in Setup()
use_no_decorate = True
@@ -325,6 +326,7 @@
raw += LookupEmail(item, alias, raise_on_error=raise_on_error)
result = []
for item in raw:
+ item = tools.FromUnicode(item)
if not item in result:
result.append(item)
if tag:
@@ -395,11 +397,11 @@
git_config_to = command.Output('git', 'config', 'sendemail.to',
raise_on_error=False)
if not git_config_to:
- print ("No recipient.\n"
- "Please add something like this to a commit\n"
- "Series-to: Fred Bloggs <f.blogs@napier.co.nz>\n"
- "Or do something like this\n"
- "git config sendemail.to u-boot@lists.denx.de")
+ print("No recipient.\n"
+ "Please add something like this to a commit\n"
+ "Series-to: Fred Bloggs <f.blogs@napier.co.nz>\n"
+ "Or do something like this\n"
+ "git config sendemail.to u-boot@lists.denx.de")
return
cc = BuildEmailList(list(set(series.get('cc')) - set(series.get('to'))),
'--cc', alias, raise_on_error)
@@ -410,9 +412,7 @@
if smtp_server:
cmd.append('--smtp-server=%s' % smtp_server)
if in_reply_to:
- if type(in_reply_to) != str:
- in_reply_to = in_reply_to.encode('utf-8')
- cmd.append('--in-reply-to="%s"' % in_reply_to)
+ cmd.append('--in-reply-to="%s"' % tools.FromUnicode(in_reply_to))
if thread:
cmd.append('--thread')
diff --git a/tools/patman/patman.py b/tools/patman/patman.py
index 27a2feb..9605a36 100755
--- a/tools/patman/patman.py
+++ b/tools/patman/patman.py
@@ -1,4 +1,4 @@
-#!/usr/bin/env python2
+#!/usr/bin/env python
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (c) 2011 The Chromium OS Authors.
diff --git a/tools/patman/series.py b/tools/patman/series.py
index 2735afa..67103f0 100644
--- a/tools/patman/series.py
+++ b/tools/patman/series.py
@@ -11,6 +11,7 @@
import gitutil
import settings
import terminal
+import tools
# Series-xxx tags that we understand
valid_series = ['to', 'cc', 'version', 'changes', 'prefix', 'notes', 'name',
@@ -114,16 +115,16 @@
commit = self.commits[upto]
print(col.Color(col.GREEN, ' %s' % args[upto]))
cc_list = list(self._generated_cc[commit.patch])
- for email in set(cc_list) - to_set - cc_set:
+ for email in sorted(set(cc_list) - to_set - cc_set):
if email == None:
email = col.Color(col.YELLOW, "<alias '%s' not found>"
% tag)
if email:
print(' Cc: ', email)
print
- for item in to_set:
+ for item in sorted(to_set):
print('To:\t ', item)
- for item in cc_set - to_set:
+ for item in sorted(cc_set - to_set):
print('Cc:\t ', item)
print('Version: ', self.get('version'))
print('Prefix:\t ', self.get('prefix'))
@@ -131,7 +132,7 @@
print('Cover: %d lines' % len(self.cover))
cover_cc = gitutil.BuildEmailList(self.get('cover_cc', ''))
all_ccs = itertools.chain(cover_cc, *self._generated_cc.values())
- for email in set(all_ccs) - to_set - cc_set:
+ for email in sorted(set(all_ccs) - to_set - cc_set):
print(' Cc: ', email)
if cmd:
print('Git command: %s' % cmd)
@@ -238,19 +239,18 @@
for x in set(cc) & set(settings.bounces):
print(col.Color(col.YELLOW, 'Skipping "%s"' % x))
cc = set(cc) - set(settings.bounces)
- cc = [m.encode('utf-8') if type(m) != str else m for m in cc]
+ cc = [tools.FromUnicode(m) for m in cc]
if limit is not None:
cc = cc[:limit]
all_ccs += cc
- print(commit.patch, ', '.join(set(cc)), file=fd)
+ print(commit.patch, ', '.join(sorted(set(cc))), file=fd)
self._generated_cc[commit.patch] = cc
if cover_fname:
cover_cc = gitutil.BuildEmailList(self.get('cover_cc', ''))
- cover_cc = [m.encode('utf-8') if type(m) != str else m
- for m in cover_cc]
- cc_list = ', '.join([x.decode('utf-8')
- for x in set(cover_cc + all_ccs)])
+ cover_cc = [tools.FromUnicode(m) for m in cover_cc]
+ cc_list = ', '.join([tools.ToUnicode(x)
+ for x in sorted(set(cover_cc + all_ccs))])
print(cover_fname, cc_list.encode('utf-8'), file=fd)
fd.close()
diff --git a/tools/patman/settings.py b/tools/patman/settings.py
index ea2bc74..c98911d 100644
--- a/tools/patman/settings.py
+++ b/tools/patman/settings.py
@@ -14,6 +14,7 @@
import command
import gitutil
+import tools
"""Default settings per-project.
@@ -57,26 +58,26 @@
# Check to make sure that bogus project gets general alias.
>>> config = _ProjectConfigParser("zzz")
>>> config.readfp(StringIO(sample_config))
- >>> config.get("alias", "enemies")
- u'Evil <evil@example.com>'
+ >>> str(config.get("alias", "enemies"))
+ 'Evil <evil@example.com>'
# Check to make sure that alias gets overridden by project.
>>> config = _ProjectConfigParser("sm")
>>> config.readfp(StringIO(sample_config))
- >>> config.get("alias", "enemies")
- u'Green G. <ugly@example.com>'
+ >>> str(config.get("alias", "enemies"))
+ 'Green G. <ugly@example.com>'
# Check to make sure that settings get merged with project.
>>> config = _ProjectConfigParser("linux")
>>> config.readfp(StringIO(sample_config))
- >>> sorted(config.items("settings"))
- [(u'am_hero', u'True'), (u'process_tags', u'False')]
+ >>> sorted((str(a), str(b)) for (a, b) in config.items("settings"))
+ [('am_hero', 'True'), ('process_tags', 'False')]
# Check to make sure that settings works with unknown project.
>>> config = _ProjectConfigParser("unknown")
>>> config.readfp(StringIO(sample_config))
- >>> sorted(config.items("settings"))
- [(u'am_hero', u'True')]
+ >>> sorted((str(a), str(b)) for (a, b) in config.items("settings"))
+ [('am_hero', 'True')]
"""
def __init__(self, project_name):
"""Construct _ProjectConfigParser.
@@ -99,17 +100,6 @@
for setting_name, setting_value in project_defaults.items():
self.set(project_settings, setting_name, setting_value)
- def _to_unicode(self, val):
- """Make sure a value is of type 'unicode'
-
- Args:
- val: string or unicode object
-
- Returns:
- unicode version of val
- """
- return val if isinstance(val, unicode) else val.decode('utf-8')
-
def get(self, section, option, *args, **kwargs):
"""Extend SafeConfigParser to try project_section before section.
@@ -127,7 +117,7 @@
val = ConfigParser.SafeConfigParser.get(
self, section, option, *args, **kwargs
)
- return self._to_unicode(val)
+ return tools.ToUnicode(val)
def items(self, section, *args, **kwargs):
"""Extend SafeConfigParser to add project_section to section.
@@ -162,8 +152,8 @@
item_dict = dict(top_items)
item_dict.update(project_items)
- return {(self._to_unicode(item), self._to_unicode(val))
- for item, val in item_dict.iteritems()}
+ return {(tools.ToUnicode(item), tools.ToUnicode(val))
+ for item, val in item_dict.items()}
def ReadGitAliases(fname):
"""Read a git alias file. This is in the form used by git:
diff --git a/tools/patman/test_util.py b/tools/patman/test_util.py
index 687d407..09f258c 100644
--- a/tools/patman/test_util.py
+++ b/tools/patman/test_util.py
@@ -3,6 +3,8 @@
# Copyright (c) 2016 Google, Inc
#
+from __future__ import print_function
+
from contextlib import contextmanager
import glob
import os
@@ -15,6 +17,8 @@
except ImportError:
from io import StringIO
+PYTHON = 'python%d' % sys.version_info[0]
+
def RunTestCoverage(prog, filter_fname, exclude_list, build_dir, required=None):
"""Run tests and check that we get 100% coverage
@@ -41,31 +45,34 @@
else:
glob_list = []
glob_list += exclude_list
- glob_list += ['*libfdt.py', '*site-packages*']
- cmd = ('PYTHONPATH=$PYTHONPATH:%s/sandbox_spl/tools python-coverage run '
- '--omit "%s" %s -P1 -t' % (build_dir, ','.join(glob_list), prog))
+ glob_list += ['*libfdt.py', '*site-packages*', '*dist-packages*']
+ test_cmd = 'test' if 'binman.py' in prog else '-t'
+ cmd = ('PYTHONPATH=$PYTHONPATH:%s/sandbox_spl/tools %s-coverage run '
+ '--omit "%s" %s %s -P1' % (build_dir, PYTHON, ','.join(glob_list),
+ prog, test_cmd))
os.system(cmd)
- stdout = command.Output('python-coverage', 'report')
+ stdout = command.Output('%s-coverage' % PYTHON, 'report')
lines = stdout.splitlines()
if required:
# Convert '/path/to/name.py' just the module name 'name'
test_set = set([os.path.splitext(os.path.basename(line.split()[0]))[0]
for line in lines if '/etype/' in line])
missing_list = required
+ missing_list.discard('__init__')
missing_list.difference_update(test_set)
if missing_list:
- print 'Missing tests for %s' % (', '.join(missing_list))
- print stdout
+ print('Missing tests for %s' % (', '.join(missing_list)))
+ print(stdout)
ok = False
coverage = lines[-1].split(' ')[-1]
ok = True
- print coverage
+ print(coverage)
if coverage != '100%':
- print stdout
- print ("Type 'python-coverage html' to get a report in "
- 'htmlcov/index.html')
- print 'Coverage error: %s, but should be 100%%' % coverage
+ print(stdout)
+ print("Type '%s-coverage html' to get a report in "
+ 'htmlcov/index.html' % PYTHON)
+ print('Coverage error: %s, but should be 100%%' % coverage)
ok = False
if not ok:
raise ValueError('Test coverage failure')
diff --git a/tools/patman/tools.py b/tools/patman/tools.py
index bf09979..0d4705d 100644
--- a/tools/patman/tools.py
+++ b/tools/patman/tools.py
@@ -3,10 +3,14 @@
# Copyright (c) 2016 Google, Inc
#
+from __future__ import print_function
+
import command
import glob
import os
import shutil
+import struct
+import sys
import tempfile
import tout
@@ -23,6 +27,8 @@
# Search paths to use for Filename(), used to find files
search_paths = []
+tool_search_paths = []
+
# Tools and the packages that contain them, on debian
packages = {
'lz4': 'liblz4-tool',
@@ -77,6 +83,7 @@
"""Tidy up: delete output directory if temporary and not preserved."""
if outdir and not preserve_outdir:
_RemoveOutputDir()
+ outdir = None
def GetOutputFilename(fname):
"""Return a filename within the output directory.
@@ -95,6 +102,7 @@
if outdir:
_RemoveOutputDir()
+ outdir = None
def SetInputDirs(dirname):
"""Add a list of input directories, where input files are kept.
@@ -153,26 +161,56 @@
def NotPowerOfTwo(num):
return num and (num & (num - 1))
-def PathHasFile(fname):
+def SetToolPaths(toolpaths):
+ """Set the path to search for tools
+
+ Args:
+ toolpaths: List of paths to search for tools executed by Run()
+ """
+ global tool_search_paths
+
+ tool_search_paths = toolpaths
+
+def PathHasFile(path_spec, fname):
"""Check if a given filename is in the PATH
Args:
+ path_spec: Value of PATH variable to check
fname: Filename to check
Returns:
True if found, False if not
"""
- for dir in os.environ['PATH'].split(':'):
+ for dir in path_spec.split(':'):
if os.path.exists(os.path.join(dir, fname)):
return True
return False
-def Run(name, *args):
+def Run(name, *args, **kwargs):
+ """Run a tool with some arguments
+
+ This runs a 'tool', which is a program used by binman to process files and
+ perhaps produce some output. Tools can be located on the PATH or in a
+ search path.
+
+ Args:
+ name: Command name to run
+ args: Arguments to the tool
+ kwargs: Options to pass to command.run()
+
+ Returns:
+ CommandResult object
+ """
try:
- return command.Run(name, *args, cwd=outdir, capture=True)
+ env = None
+ if tool_search_paths:
+ env = dict(os.environ)
+ env['PATH'] = ':'.join(tool_search_paths) + ':' + env['PATH']
+ return command.Run(name, *args, capture=True,
+ capture_stderr=True, env=env, **kwargs)
except:
- if not PathHasFile(name):
- msg = "Plesae install tool '%s'" % name
+ if env and not PathHasFile(env['PATH'], name):
+ msg = "Please install tool '%s'" % name
package = packages.get(name)
if package:
msg += " (e.g. from package '%s')" % package
@@ -213,7 +251,7 @@
# If not found, just return the standard, unchanged path
return fname
-def ReadFile(fname):
+def ReadFile(fname, binary=True):
"""Read and return the contents of a file.
Args:
@@ -222,7 +260,7 @@
Returns:
data read from file, as a string.
"""
- with open(Filename(fname), 'rb') as fd:
+ with open(Filename(fname), binary and 'rb' or 'r') as fd:
data = fd.read()
#self._out.Info("Read file '%s' size %d (%#0x)" %
#(fname, len(data), len(data)))
@@ -239,3 +277,224 @@
#(fname, len(data), len(data)))
with open(Filename(fname), 'wb') as fd:
fd.write(data)
+
+def GetBytes(byte, size):
+ """Get a string of bytes of a given size
+
+ This handles the unfortunate different between Python 2 and Python 2.
+
+ Args:
+ byte: Numeric byte value to use
+ size: Size of bytes/string to return
+
+ Returns:
+ A bytes type with 'byte' repeated 'size' times
+ """
+ if sys.version_info[0] >= 3:
+ data = bytes([byte]) * size
+ else:
+ data = chr(byte) * size
+ return data
+
+def ToUnicode(val):
+ """Make sure a value is a unicode string
+
+ This allows some amount of compatibility between Python 2 and Python3. For
+ the former, it returns a unicode object.
+
+ Args:
+ val: string or unicode object
+
+ Returns:
+ unicode version of val
+ """
+ if sys.version_info[0] >= 3:
+ return val
+ return val if isinstance(val, unicode) else val.decode('utf-8')
+
+def FromUnicode(val):
+ """Make sure a value is a non-unicode string
+
+ This allows some amount of compatibility between Python 2 and Python3. For
+ the former, it converts a unicode object to a string.
+
+ Args:
+ val: string or unicode object
+
+ Returns:
+ non-unicode version of val
+ """
+ if sys.version_info[0] >= 3:
+ return val
+ return val if isinstance(val, str) else val.encode('utf-8')
+
+def ToByte(ch):
+ """Convert a character to an ASCII value
+
+ This is useful because in Python 2 bytes is an alias for str, but in
+ Python 3 they are separate types. This function converts the argument to
+ an ASCII value in either case.
+
+ Args:
+ ch: A string (Python 2) or byte (Python 3) value
+
+ Returns:
+ integer ASCII value for ch
+ """
+ return ord(ch) if type(ch) == str else ch
+
+def ToChar(byte):
+ """Convert a byte to a character
+
+ This is useful because in Python 2 bytes is an alias for str, but in
+ Python 3 they are separate types. This function converts an ASCII value to
+ a value with the appropriate type in either case.
+
+ Args:
+ byte: A byte or str value
+ """
+ return chr(byte) if type(byte) != str else byte
+
+def ToChars(byte_list):
+ """Convert a list of bytes to a str/bytes type
+
+ Args:
+ byte_list: List of ASCII values representing the string
+
+ Returns:
+ string made by concatenating all the ASCII values
+ """
+ return ''.join([chr(byte) for byte in byte_list])
+
+def ToBytes(string):
+ """Convert a str type into a bytes type
+
+ Args:
+ string: string to convert value
+
+ Returns:
+ Python 3: A bytes type
+ Python 2: A string type
+ """
+ if sys.version_info[0] >= 3:
+ return string.encode('utf-8')
+ return string
+
+def Compress(indata, algo, with_header=True):
+ """Compress some data using a given algorithm
+
+ Note that for lzma this uses an old version of the algorithm, not that
+ provided by xz.
+
+ This requires 'lz4' and 'lzma_alone' tools. It also requires an output
+ directory to be previously set up, by calling PrepareOutputDir().
+
+ Args:
+ indata: Input data to compress
+ algo: Algorithm to use ('none', 'gzip', 'lz4' or 'lzma')
+
+ Returns:
+ Compressed data
+ """
+ if algo == 'none':
+ return indata
+ fname = GetOutputFilename('%s.comp.tmp' % algo)
+ WriteFile(fname, indata)
+ if algo == 'lz4':
+ data = Run('lz4', '--no-frame-crc', '-c', fname, binary=True)
+ # cbfstool uses a very old version of lzma
+ elif algo == 'lzma':
+ outfname = GetOutputFilename('%s.comp.otmp' % algo)
+ Run('lzma_alone', 'e', fname, outfname, '-lc1', '-lp0', '-pb0', '-d8')
+ data = ReadFile(outfname)
+ elif algo == 'gzip':
+ data = Run('gzip', '-c', fname, binary=True)
+ else:
+ raise ValueError("Unknown algorithm '%s'" % algo)
+ if with_header:
+ hdr = struct.pack('<I', len(data))
+ data = hdr + data
+ return data
+
+def Decompress(indata, algo, with_header=True):
+ """Decompress some data using a given algorithm
+
+ Note that for lzma this uses an old version of the algorithm, not that
+ provided by xz.
+
+ This requires 'lz4' and 'lzma_alone' tools. It also requires an output
+ directory to be previously set up, by calling PrepareOutputDir().
+
+ Args:
+ indata: Input data to decompress
+ algo: Algorithm to use ('none', 'gzip', 'lz4' or 'lzma')
+
+ Returns:
+ Compressed data
+ """
+ if algo == 'none':
+ return indata
+ if with_header:
+ data_len = struct.unpack('<I', indata[:4])[0]
+ indata = indata[4:4 + data_len]
+ fname = GetOutputFilename('%s.decomp.tmp' % algo)
+ with open(fname, 'wb') as fd:
+ fd.write(indata)
+ if algo == 'lz4':
+ data = Run('lz4', '-dc', fname, binary=True)
+ elif algo == 'lzma':
+ outfname = GetOutputFilename('%s.decomp.otmp' % algo)
+ Run('lzma_alone', 'd', fname, outfname)
+ data = ReadFile(outfname)
+ elif algo == 'gzip':
+ data = Run('gzip', '-cd', fname, binary=True)
+ else:
+ raise ValueError("Unknown algorithm '%s'" % algo)
+ return data
+
+CMD_CREATE, CMD_DELETE, CMD_ADD, CMD_REPLACE, CMD_EXTRACT = range(5)
+
+IFWITOOL_CMDS = {
+ CMD_CREATE: 'create',
+ CMD_DELETE: 'delete',
+ CMD_ADD: 'add',
+ CMD_REPLACE: 'replace',
+ CMD_EXTRACT: 'extract',
+ }
+
+def RunIfwiTool(ifwi_file, cmd, fname=None, subpart=None, entry_name=None):
+ """Run ifwitool with the given arguments:
+
+ Args:
+ ifwi_file: IFWI file to operation on
+ cmd: Command to execute (CMD_...)
+ fname: Filename of file to add/replace/extract/create (None for
+ CMD_DELETE)
+ subpart: Name of sub-partition to operation on (None for CMD_CREATE)
+ entry_name: Name of directory entry to operate on, or None if none
+ """
+ args = ['ifwitool', ifwi_file]
+ args.append(IFWITOOL_CMDS[cmd])
+ if fname:
+ args += ['-f', fname]
+ if subpart:
+ args += ['-n', subpart]
+ if entry_name:
+ args += ['-d', '-e', entry_name]
+ Run(*args)
+
+def ToHex(val):
+ """Convert an integer value (or None) to a string
+
+ Returns:
+ hex value, or 'None' if the value is None
+ """
+ return 'None' if val is None else '%#x' % val
+
+def ToHexSize(val):
+ """Return the size of an object in hex
+
+ Returns:
+ hex value of size, or 'None' if the value is None
+ """
+ return 'None' if val is None else '%#x' % len(val)
diff --git a/tools/patman/tout.py b/tools/patman/tout.py
index 4957c7a..2a38485 100644
--- a/tools/patman/tout.py
+++ b/tools/patman/tout.py
@@ -4,16 +4,14 @@
# Terminal output logging.
#
+from __future__ import print_function
+
import sys
import terminal
# Output verbosity levels that we support
-ERROR = 0
-WARNING = 1
-NOTICE = 2
-INFO = 3
-DEBUG = 4
+ERROR, WARNING, NOTICE, INFO, DETAIL, DEBUG = range(6)
in_progress = False
@@ -87,7 +85,7 @@
ClearProgress()
if color:
msg = _color.Color(color, msg)
- _stdout.write(msg + '\n')
+ print(msg)
def DoOutput(level, msg):
"""Output a message to the terminal.
@@ -105,7 +103,7 @@
Args:
msg; Message to display.
"""
- _Output(0, msg, _color.RED)
+ _Output(ERROR, msg, _color.RED)
def Warning(msg):
"""Display a warning message
@@ -113,7 +111,7 @@
Args:
msg; Message to display.
"""
- _Output(1, msg, _color.YELLOW)
+ _Output(WARNING, msg, _color.YELLOW)
def Notice(msg):
"""Display an important infomation message
@@ -121,7 +119,7 @@
Args:
msg; Message to display.
"""
- _Output(2, msg)
+ _Output(NOTICE, msg)
def Info(msg):
"""Display an infomation message
@@ -129,7 +127,15 @@
Args:
msg; Message to display.
"""
- _Output(3, msg)
+ _Output(INFO, msg)
+
+def Detail(msg):
+ """Display a detailed message
+
+ Args:
+ msg; Message to display.
+ """
+ _Output(DETAIL, msg)
def Debug(msg):
"""Display a debug message
@@ -137,7 +143,7 @@
Args:
msg; Message to display.
"""
- _Output(4, msg)
+ _Output(DEBUG, msg)
def UserOutput(msg):
"""Display a message regardless of the current output level.
diff --git a/tools/prelink-riscv.c b/tools/prelink-riscv.c
index 52eb78e..b046794 100644
--- a/tools/prelink-riscv.c
+++ b/tools/prelink-riscv.c
@@ -8,10 +8,6 @@
* without fixup. Both RV32 and RV64 are supported.
*/
-#if __BYTE_ORDER__ != __ORDER_LITTLE_ENDIAN__
-#error "Only little-endian host is supported"
-#endif
-
#include <errno.h>
#include <stdbool.h>
#include <stdint.h>
@@ -25,6 +21,7 @@
#include <sys/stat.h>
#include <sys/types.h>
#include <unistd.h>
+#include <compiler.h>
#ifndef EM_RISCV
#define EM_RISCV 243
@@ -50,12 +47,28 @@
exit(EXIT_FAILURE); \
} while (0)
+#define PRELINK_BYTEORDER le
#define PRELINK_INC_BITS 32
#include "prelink-riscv.inc"
+#undef PRELINK_BYTEORDER
#undef PRELINK_INC_BITS
+#define PRELINK_BYTEORDER le
#define PRELINK_INC_BITS 64
#include "prelink-riscv.inc"
+#undef PRELINK_BYTEORDER
+#undef PRELINK_INC_BITS
+
+#define PRELINK_BYTEORDER be
+#define PRELINK_INC_BITS 32
+#include "prelink-riscv.inc"
+#undef PRELINK_BYTEORDER
+#undef PRELINK_INC_BITS
+
+#define PRELINK_BYTEORDER be
+#define PRELINK_INC_BITS 64
+#include "prelink-riscv.inc"
+#undef PRELINK_BYTEORDER
#undef PRELINK_INC_BITS
int main(int argc, const char *const *argv)
@@ -91,11 +104,19 @@
die("Invalid ELF file %s", argv[1]);
bool is64 = e_ident[EI_CLASS] == ELFCLASS64;
+ bool isbe = e_ident[EI_DATA] == ELFDATA2MSB;
- if (is64)
- prelink64(data);
- else
- prelink32(data);
+ if (is64) {
+ if (isbe)
+ prelink_be64(data);
+ else
+ prelink_le64(data);
+ } else {
+ if (isbe)
+ prelink_be32(data);
+ else
+ prelink_le32(data);
+ }
return 0;
}
diff --git a/tools/prelink-riscv.inc b/tools/prelink-riscv.inc
index d492587..f2b5467 100644
--- a/tools/prelink-riscv.inc
+++ b/tools/prelink-riscv.inc
@@ -12,9 +12,9 @@
#define CONCAT(x, y) CONCAT_IMPL(x, y)
#define CONCAT3(x, y, z) CONCAT(CONCAT(x, y), z)
-#define prelink_nn CONCAT(prelink, PRELINK_INC_BITS)
+#define prelink_bonn CONCAT3(prelink_, PRELINK_BYTEORDER, PRELINK_INC_BITS)
#define uintnn_t CONCAT3(uint, PRELINK_INC_BITS, _t)
-#define get_offset_nn CONCAT(get_offset_, PRELINK_INC_BITS)
+#define get_offset_bonn CONCAT3(get_offset_, PRELINK_BYTEORDER, PRELINK_INC_BITS)
#define Elf_Ehdr CONCAT3(Elf, PRELINK_INC_BITS, _Ehdr)
#define Elf_Phdr CONCAT3(Elf, PRELINK_INC_BITS, _Phdr)
#define Elf_Rela CONCAT3(Elf, PRELINK_INC_BITS, _Rela)
@@ -23,34 +23,40 @@
#define Elf_Addr CONCAT3(Elf, PRELINK_INC_BITS, _Addr)
#define ELF_R_TYPE CONCAT3(ELF, PRELINK_INC_BITS, _R_TYPE)
#define ELF_R_SYM CONCAT3(ELF, PRELINK_INC_BITS, _R_SYM)
+#define target16_to_cpu CONCAT(PRELINK_BYTEORDER, 16_to_cpu)
+#define target32_to_cpu CONCAT(PRELINK_BYTEORDER, 32_to_cpu)
+#define target64_to_cpu CONCAT(PRELINK_BYTEORDER, 64_to_cpu)
+#define targetnn_to_cpu CONCAT3(PRELINK_BYTEORDER, PRELINK_INC_BITS, _to_cpu)
+#define cpu_to_target32 CONCAT3(cpu_to_, PRELINK_BYTEORDER, 32)
+#define cpu_to_target64 CONCAT3(cpu_to_, PRELINK_BYTEORDER, 64)
-static void* get_offset_nn (void* data, Elf_Phdr* phdrs, size_t phnum, Elf_Addr addr)
+static void* get_offset_bonn (void* data, Elf_Phdr* phdrs, size_t phnum, Elf_Addr addr)
{
Elf_Phdr *p;
for (p = phdrs; p < phdrs + phnum; ++p)
- if (p->p_vaddr <= addr && p->p_vaddr + p->p_memsz > addr)
- return data + p->p_offset + (addr - p->p_vaddr);
+ if (targetnn_to_cpu(p->p_vaddr) <= addr && targetnn_to_cpu(p->p_vaddr) + targetnn_to_cpu(p->p_memsz) > addr)
+ return data + targetnn_to_cpu(p->p_offset) + (addr - targetnn_to_cpu(p->p_vaddr));
return NULL;
}
-static void prelink_nn(void *data)
+static void prelink_bonn(void *data)
{
Elf_Ehdr *ehdr = data;
Elf_Phdr *p;
Elf_Dyn *dyn;
Elf_Rela *r;
- if (ehdr->e_machine != EM_RISCV)
+ if (target16_to_cpu(ehdr->e_machine) != EM_RISCV)
die("Machine type is not RISC-V");
- Elf_Phdr *phdrs = data + ehdr->e_phoff;
+ Elf_Phdr *phdrs = data + targetnn_to_cpu(ehdr->e_phoff);
Elf_Dyn *dyns = NULL;
- for (p = phdrs; p < phdrs + ehdr->e_phnum; ++p) {
- if (p->p_type == PT_DYNAMIC) {
- dyns = data + p->p_offset;
+ for (p = phdrs; p < phdrs + target16_to_cpu(ehdr->e_phnum); ++p) {
+ if (target32_to_cpu(p->p_type) == PT_DYNAMIC) {
+ dyns = data + targetnn_to_cpu(p->p_offset);
break;
}
}
@@ -62,14 +68,14 @@
size_t rela_count = 0;
Elf_Sym *dynsym = NULL;
for (dyn = dyns;; ++dyn) {
- if (dyn->d_tag == DT_NULL)
+ if (targetnn_to_cpu(dyn->d_tag) == DT_NULL)
break;
- else if (dyn->d_tag == DT_RELA)
- rela_dyn = get_offset_nn(data, phdrs, ehdr->e_phnum, + dyn->d_un.d_ptr);
- else if (dyn->d_tag == DT_RELASZ)
- rela_count = dyn->d_un.d_val / sizeof(Elf_Rela);
- else if (dyn->d_tag == DT_SYMTAB)
- dynsym = get_offset_nn(data, phdrs, ehdr->e_phnum, + dyn->d_un.d_ptr);
+ else if (targetnn_to_cpu(dyn->d_tag) == DT_RELA)
+ rela_dyn = get_offset_bonn(data, phdrs, target16_to_cpu(ehdr->e_phnum), + targetnn_to_cpu(dyn->d_un.d_ptr));
+ else if (targetnn_to_cpu(dyn->d_tag) == DT_RELASZ)
+ rela_count = targetnn_to_cpu(dyn->d_un.d_val) / sizeof(Elf_Rela);
+ else if (targetnn_to_cpu(dyn->d_tag) == DT_SYMTAB)
+ dynsym = get_offset_bonn(data, phdrs, target16_to_cpu(ehdr->e_phnum), + targetnn_to_cpu(dyn->d_un.d_ptr));
}
@@ -80,23 +86,23 @@
die("No .dynsym found");
for (r = rela_dyn; r < rela_dyn + rela_count; ++r) {
- void* buf = get_offset_nn(data, phdrs, ehdr->e_phnum, r->r_offset);
+ void* buf = get_offset_bonn(data, phdrs, target16_to_cpu(ehdr->e_phnum), targetnn_to_cpu(r->r_offset));
if (buf == NULL)
continue;
- if (ELF_R_TYPE(r->r_info) == R_RISCV_RELATIVE)
+ if (ELF_R_TYPE(targetnn_to_cpu(r->r_info)) == R_RISCV_RELATIVE)
*((uintnn_t*) buf) = r->r_addend;
- else if (ELF_R_TYPE(r->r_info) == R_RISCV_32)
- *((uint32_t*) buf) = dynsym[ELF_R_SYM(r->r_info)].st_value;
- else if (ELF_R_TYPE(r->r_info) == R_RISCV_64)
- *((uint64_t*) buf) = dynsym[ELF_R_SYM(r->r_info)].st_value;
+ else if (ELF_R_TYPE(targetnn_to_cpu(r->r_info)) == R_RISCV_32)
+ *((uint32_t*) buf) = cpu_to_target32(targetnn_to_cpu(dynsym[ELF_R_SYM(targetnn_to_cpu(r->r_info))].st_value) + targetnn_to_cpu(r->r_addend));
+ else if (ELF_R_TYPE(targetnn_to_cpu(r->r_info)) == R_RISCV_64)
+ *((uint64_t*) buf) = cpu_to_target64(targetnn_to_cpu(dynsym[ELF_R_SYM(targetnn_to_cpu(r->r_info))].st_value) + targetnn_to_cpu(r->r_addend));
}
}
-#undef prelink_nn
+#undef prelink_bonn
#undef uintnn_t
-#undef get_offset_nn
+#undef get_offset_bonn
#undef Elf_Ehdr
#undef Elf_Phdr
#undef Elf_Rela
@@ -105,6 +111,12 @@
#undef Elf_Addr
#undef ELF_R_TYPE
#undef ELF_R_SYM
+#undef target16_to_cpu
+#undef target32_to_cpu
+#undef target64_to_cpu
+#undef targetnn_to_cpu
+#undef cpu_to_target32
+#undef cpu_to_target64
#undef CONCAT_IMPL
#undef CONCAT
diff --git a/tools/proftool.c b/tools/proftool.c
index c1803fa..fecb9d6 100644
--- a/tools/proftool.c
+++ b/tools/proftool.c
@@ -205,12 +205,12 @@
return low >= 0 ? &func_list[low] : NULL;
}
-static int read_calls(FILE *fin, int count)
+static int read_calls(FILE *fin, size_t count)
{
struct trace_call *call_data;
int i;
- notice("call count: %d\n", count);
+ notice("call count: %zu\n", count);
call_list = (struct trace_call *)calloc(count, sizeof(*call_data));
if (!call_list) {
error("Cannot allocate call_list\n");
diff --git a/tools/rmboard.py b/tools/rmboard.py
new file mode 100755
index 0000000..df4f04b
--- /dev/null
+++ b/tools/rmboard.py
@@ -0,0 +1,150 @@
+#! /usr/bin/python
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright 2019 Google LLC
+#
+
+"""
+Script to remove boards
+
+Usage:
+ rmboard.py <board_name>...
+
+A single commit is created for each board removed.
+
+Some boards may depend on files provided by another and this will cause
+problems, generally the removal of files which should not be removed.
+
+This script works by:
+ - Looking through the MAINTAINERS files which mention a board to find out
+ what files the board uses
+ - Looking through the Kconfig files which mention a board to find one that
+ needs to have material removed
+
+Search for ## to update the commit message manually.
+"""
+
+from __future__ import print_function
+
+import glob
+import os
+import re
+import sys
+
+# Bring in the patman libraries
+our_path = os.path.dirname(os.path.realpath(__file__))
+sys.path.append(os.path.join(our_path, '../tools/patman'))
+
+import command
+
+def rm_kconfig_include(path):
+ """Remove a path from Kconfig files
+
+ This function finds the given path in a 'source' statement in a Kconfig
+ file and removes that line from the file. This is needed because the path
+ is going to be removed, so any reference to it will cause a problem with
+ Kconfig parsing.
+
+ The changes are made locally and then added to the git staging area.
+
+ Args:
+ path: Path to search for and remove
+ """
+ cmd = ['git', 'grep', path]
+ stdout = command.RunPipe([cmd], capture=True, raise_on_error=False).stdout
+ if not stdout:
+ return
+ fname = stdout.split(':')[0]
+
+ print("Fixing up '%s' to remove reference to '%s'" % (fname, path))
+ cmd = ['sed', '-i', '\|%s|d' % path, fname]
+ stdout = command.RunPipe([cmd], capture=True).stdout
+
+ cmd = ['git', 'add', fname]
+ stdout = command.RunPipe([cmd], capture=True).stdout
+
+def rm_board(board):
+ """Create a commit which removes a single board
+
+ This looks up the MAINTAINERS file to file files that need to be removed,
+ then removes pieces from the Kconfig files that mention the board.
+
+
+ Args:
+ board: Board name to remove
+ """
+
+ # Find all MAINTAINERS and Kconfig files which mention the board
+ cmd = ['git', 'grep', '-l', board]
+ stdout = command.RunPipe([cmd], capture=True).stdout
+ maintain = []
+ kconfig = []
+ for line in stdout.splitlines():
+ line = line.strip()
+ if 'MAINTAINERS' in line:
+ if line not in maintain:
+ maintain.append(line)
+ elif 'Kconfig' in line:
+ kconfig.append(line)
+ paths = []
+ cc = []
+
+ # Look through the MAINTAINERS file to find things to remove
+ for fname in maintain:
+ with open(fname) as fd:
+ for line in fd:
+ line = line.strip()
+ fields = re.split('[ \t]', line, 1)
+ if len(fields) == 2:
+ if fields[0] == 'M:':
+ cc.append(fields[1])
+ elif fields[0] == 'F:':
+ paths.append(fields[1].strip())
+
+ # Expand any wildcards in the MAINTAINERS file
+ real = []
+ for path in paths:
+ if path[-1] == '/':
+ path = path[:-1]
+ if '*' in path:
+ globbed = glob.glob(path)
+ print("Expanded '%s' to '%s'" % (path, globbed))
+ real += globbed
+ else:
+ real.append(path)
+
+ # Search for Kconfig files in the resulting list. Remove any 'source' lines
+ # which reference Kconfig files we want to remove
+ for path in real:
+ cmd = ['find', path]
+ stdout = (command.RunPipe([cmd], capture=True, raise_on_error=False).
+ stdout)
+ for fname in stdout.splitlines():
+ if fname.endswith('Kconfig'):
+ rm_kconfig_include(fname)
+
+ # Remove unwanted files
+ cmd = ['git', 'rm', '-r'] + real
+ stdout = command.RunPipe([cmd], capture=True).stdout
+
+ ## Change the messages as needed
+ msg = '''arm: Remove %s board
+
+This board has not been converted to CONFIG_DM_MMC by the deadline.
+Remove it.
+
+''' % board
+ for name in cc:
+ msg += 'Patch-cc: %s\n' % name
+
+ # Create the commit
+ cmd = ['git', 'commit', '-s', '-m', msg]
+ stdout = command.RunPipe([cmd], capture=True).stdout
+
+ # Check if the board is mentioned anywhere else. The user will need to deal
+ # with this
+ cmd = ['git', 'grep', '-il', board]
+ print(command.RunPipe([cmd], capture=True, raise_on_error=False).stdout)
+ print(' '.join(cmd))
+
+for board in sys.argv[1:]:
+ rm_board(board)
diff --git a/tools/zynqmp_pm_cfg_obj_convert.py b/tools/zynqmp_pm_cfg_obj_convert.py
new file mode 100755
index 0000000..dd27f47
--- /dev/null
+++ b/tools/zynqmp_pm_cfg_obj_convert.py
@@ -0,0 +1,301 @@
+#!/usr/bin/env python3
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2019 Luca Ceresoli <luca@lucaceresoli.net>
+
+import sys
+import re
+import struct
+import logging
+import argparse
+
+parser = argparse.ArgumentParser(
+ description='Convert a PMU configuration object from C source to a binary blob.')
+parser.add_argument('-D', '--debug', action="store_true")
+parser.add_argument(
+ "in_file", metavar='INPUT_FILE',
+ help='PMU configuration object (C source as produced by Xilinx XSDK)')
+parser.add_argument(
+ "out_file", metavar='OUTPUT_FILE',
+ help='PMU configuration object binary blob')
+args = parser.parse_args()
+
+logging.basicConfig(format='%(levelname)s:%(message)s',
+ level=(logging.DEBUG if args.debug else logging.WARNING))
+
+pm_define = {
+ 'PM_CAP_ACCESS' : 0x1,
+ 'PM_CAP_CONTEXT' : 0x2,
+ 'PM_CAP_WAKEUP' : 0x4,
+
+ 'NODE_UNKNOWN' : 0,
+ 'NODE_APU' : 1,
+ 'NODE_APU_0' : 2,
+ 'NODE_APU_1' : 3,
+ 'NODE_APU_2' : 4,
+ 'NODE_APU_3' : 5,
+ 'NODE_RPU' : 6,
+ 'NODE_RPU_0' : 7,
+ 'NODE_RPU_1' : 8,
+ 'NODE_PLD' : 9,
+ 'NODE_FPD' : 10,
+ 'NODE_OCM_BANK_0' : 11,
+ 'NODE_OCM_BANK_1' : 12,
+ 'NODE_OCM_BANK_2' : 13,
+ 'NODE_OCM_BANK_3' : 14,
+ 'NODE_TCM_0_A' : 15,
+ 'NODE_TCM_0_B' : 16,
+ 'NODE_TCM_1_A' : 17,
+ 'NODE_TCM_1_B' : 18,
+ 'NODE_L2' : 19,
+ 'NODE_GPU_PP_0' : 20,
+ 'NODE_GPU_PP_1' : 21,
+ 'NODE_USB_0' : 22,
+ 'NODE_USB_1' : 23,
+ 'NODE_TTC_0' : 24,
+ 'NODE_TTC_1' : 25,
+ 'NODE_TTC_2' : 26,
+ 'NODE_TTC_3' : 27,
+ 'NODE_SATA' : 28,
+ 'NODE_ETH_0' : 29,
+ 'NODE_ETH_1' : 30,
+ 'NODE_ETH_2' : 31,
+ 'NODE_ETH_3' : 32,
+ 'NODE_UART_0' : 33,
+ 'NODE_UART_1' : 34,
+ 'NODE_SPI_0' : 35,
+ 'NODE_SPI_1' : 36,
+ 'NODE_I2C_0' : 37,
+ 'NODE_I2C_1' : 38,
+ 'NODE_SD_0' : 39,
+ 'NODE_SD_1' : 40,
+ 'NODE_DP' : 41,
+ 'NODE_GDMA' : 42,
+ 'NODE_ADMA' : 43,
+ 'NODE_NAND' : 44,
+ 'NODE_QSPI' : 45,
+ 'NODE_GPIO' : 46,
+ 'NODE_CAN_0' : 47,
+ 'NODE_CAN_1' : 48,
+ 'NODE_EXTERN' : 49,
+ 'NODE_APLL' : 50,
+ 'NODE_VPLL' : 51,
+ 'NODE_DPLL' : 52,
+ 'NODE_RPLL' : 53,
+ 'NODE_IOPLL' : 54,
+ 'NODE_DDR' : 55,
+ 'NODE_IPI_APU' : 56,
+ 'NODE_IPI_RPU_0' : 57,
+ 'NODE_GPU' : 58,
+ 'NODE_PCIE' : 59,
+ 'NODE_PCAP' : 60,
+ 'NODE_RTC' : 61,
+ 'NODE_LPD' : 62,
+ 'NODE_VCU' : 63,
+ 'NODE_IPI_RPU_1' : 64,
+ 'NODE_IPI_PL_0' : 65,
+ 'NODE_IPI_PL_1' : 66,
+ 'NODE_IPI_PL_2' : 67,
+ 'NODE_IPI_PL_3' : 68,
+ 'NODE_PL' : 69,
+ 'NODE_ID_MA' : 70,
+
+ 'XILPM_RESET_PCIE_CFG' : 1000,
+ 'XILPM_RESET_PCIE_BRIDGE' : 1001,
+ 'XILPM_RESET_PCIE_CTRL' : 1002,
+ 'XILPM_RESET_DP' : 1003,
+ 'XILPM_RESET_SWDT_CRF' : 1004,
+ 'XILPM_RESET_AFI_FM5' : 1005,
+ 'XILPM_RESET_AFI_FM4' : 1006,
+ 'XILPM_RESET_AFI_FM3' : 1007,
+ 'XILPM_RESET_AFI_FM2' : 1008,
+ 'XILPM_RESET_AFI_FM1' : 1009,
+ 'XILPM_RESET_AFI_FM0' : 1010,
+ 'XILPM_RESET_GDMA' : 1011,
+ 'XILPM_RESET_GPU_PP1' : 1012,
+ 'XILPM_RESET_GPU_PP0' : 1013,
+ 'XILPM_RESET_GPU' : 1014,
+ 'XILPM_RESET_GT' : 1015,
+ 'XILPM_RESET_SATA' : 1016,
+ 'XILPM_RESET_ACPU3_PWRON' : 1017,
+ 'XILPM_RESET_ACPU2_PWRON' : 1018,
+ 'XILPM_RESET_ACPU1_PWRON' : 1019,
+ 'XILPM_RESET_ACPU0_PWRON' : 1020,
+ 'XILPM_RESET_APU_L2' : 1021,
+ 'XILPM_RESET_ACPU3' : 1022,
+ 'XILPM_RESET_ACPU2' : 1023,
+ 'XILPM_RESET_ACPU1' : 1024,
+ 'XILPM_RESET_ACPU0' : 1025,
+ 'XILPM_RESET_DDR' : 1026,
+ 'XILPM_RESET_APM_FPD' : 1027,
+ 'XILPM_RESET_SOFT' : 1028,
+ 'XILPM_RESET_GEM0' : 1029,
+ 'XILPM_RESET_GEM1' : 1030,
+ 'XILPM_RESET_GEM2' : 1031,
+ 'XILPM_RESET_GEM3' : 1032,
+ 'XILPM_RESET_QSPI' : 1033,
+ 'XILPM_RESET_UART0' : 1034,
+ 'XILPM_RESET_UART1' : 1035,
+ 'XILPM_RESET_SPI0' : 1036,
+ 'XILPM_RESET_SPI1' : 1037,
+ 'XILPM_RESET_SDIO0' : 1038,
+ 'XILPM_RESET_SDIO1' : 1039,
+ 'XILPM_RESET_CAN0' : 1040,
+ 'XILPM_RESET_CAN1' : 1041,
+ 'XILPM_RESET_I2C0' : 1042,
+ 'XILPM_RESET_I2C1' : 1043,
+ 'XILPM_RESET_TTC0' : 1044,
+ 'XILPM_RESET_TTC1' : 1045,
+ 'XILPM_RESET_TTC2' : 1046,
+ 'XILPM_RESET_TTC3' : 1047,
+ 'XILPM_RESET_SWDT_CRL' : 1048,
+ 'XILPM_RESET_NAND' : 1049,
+ 'XILPM_RESET_ADMA' : 1050,
+ 'XILPM_RESET_GPIO' : 1051,
+ 'XILPM_RESET_IOU_CC' : 1052,
+ 'XILPM_RESET_TIMESTAMP' : 1053,
+ 'XILPM_RESET_RPU_R50' : 1054,
+ 'XILPM_RESET_RPU_R51' : 1055,
+ 'XILPM_RESET_RPU_AMBA' : 1056,
+ 'XILPM_RESET_OCM' : 1057,
+ 'XILPM_RESET_RPU_PGE' : 1058,
+ 'XILPM_RESET_USB0_CORERESET' : 1059,
+ 'XILPM_RESET_USB1_CORERESET' : 1060,
+ 'XILPM_RESET_USB0_HIBERRESET' : 1061,
+ 'XILPM_RESET_USB1_HIBERRESET' : 1062,
+ 'XILPM_RESET_USB0_APB' : 1063,
+ 'XILPM_RESET_USB1_APB' : 1064,
+ 'XILPM_RESET_IPI' : 1065,
+ 'XILPM_RESET_APM_LPD' : 1066,
+ 'XILPM_RESET_RTC' : 1067,
+ 'XILPM_RESET_SYSMON' : 1068,
+ 'XILPM_RESET_AFI_FM6' : 1069,
+ 'XILPM_RESET_LPD_SWDT' : 1070,
+ 'XILPM_RESET_FPD' : 1071,
+ 'XILPM_RESET_RPU_DBG1' : 1072,
+ 'XILPM_RESET_RPU_DBG0' : 1073,
+ 'XILPM_RESET_DBG_LPD' : 1074,
+ 'XILPM_RESET_DBG_FPD' : 1075,
+ 'XILPM_RESET_APLL' : 1076,
+ 'XILPM_RESET_DPLL' : 1077,
+ 'XILPM_RESET_VPLL' : 1078,
+ 'XILPM_RESET_IOPLL' : 1079,
+ 'XILPM_RESET_RPLL' : 1080,
+ 'XILPM_RESET_GPO3_PL_0' : 1081,
+ 'XILPM_RESET_GPO3_PL_1' : 1082,
+ 'XILPM_RESET_GPO3_PL_2' : 1083,
+ 'XILPM_RESET_GPO3_PL_3' : 1084,
+ 'XILPM_RESET_GPO3_PL_4' : 1085,
+ 'XILPM_RESET_GPO3_PL_5' : 1086,
+ 'XILPM_RESET_GPO3_PL_6' : 1087,
+ 'XILPM_RESET_GPO3_PL_7' : 1088,
+ 'XILPM_RESET_GPO3_PL_8' : 1089,
+ 'XILPM_RESET_GPO3_PL_9' : 1090,
+ 'XILPM_RESET_GPO3_PL_10' : 1091,
+ 'XILPM_RESET_GPO3_PL_11' : 1092,
+ 'XILPM_RESET_GPO3_PL_12' : 1093,
+ 'XILPM_RESET_GPO3_PL_13' : 1094,
+ 'XILPM_RESET_GPO3_PL_14' : 1095,
+ 'XILPM_RESET_GPO3_PL_15' : 1096,
+ 'XILPM_RESET_GPO3_PL_16' : 1097,
+ 'XILPM_RESET_GPO3_PL_17' : 1098,
+ 'XILPM_RESET_GPO3_PL_18' : 1099,
+ 'XILPM_RESET_GPO3_PL_19' : 1100,
+ 'XILPM_RESET_GPO3_PL_20' : 1101,
+ 'XILPM_RESET_GPO3_PL_21' : 1102,
+ 'XILPM_RESET_GPO3_PL_22' : 1103,
+ 'XILPM_RESET_GPO3_PL_23' : 1104,
+ 'XILPM_RESET_GPO3_PL_24' : 1105,
+ 'XILPM_RESET_GPO3_PL_25' : 1106,
+ 'XILPM_RESET_GPO3_PL_26' : 1107,
+ 'XILPM_RESET_GPO3_PL_27' : 1108,
+ 'XILPM_RESET_GPO3_PL_28' : 1109,
+ 'XILPM_RESET_GPO3_PL_29' : 1110,
+ 'XILPM_RESET_GPO3_PL_30' : 1111,
+ 'XILPM_RESET_GPO3_PL_31' : 1112,
+ 'XILPM_RESET_RPU_LS' : 1113,
+ 'XILPM_RESET_PS_ONLY' : 1114,
+ 'XILPM_RESET_PL' : 1115,
+ 'XILPM_RESET_GPIO5_EMIO_92' : 1116,
+ 'XILPM_RESET_GPIO5_EMIO_93' : 1117,
+ 'XILPM_RESET_GPIO5_EMIO_94' : 1118,
+ 'XILPM_RESET_GPIO5_EMIO_95' : 1119,
+
+ 'PM_CONFIG_MASTER_SECTION_ID' : 0x101,
+ 'PM_CONFIG_SLAVE_SECTION_ID' : 0x102,
+ 'PM_CONFIG_PREALLOC_SECTION_ID' : 0x103,
+ 'PM_CONFIG_POWER_SECTION_ID' : 0x104,
+ 'PM_CONFIG_RESET_SECTION_ID' : 0x105,
+ 'PM_CONFIG_SHUTDOWN_SECTION_ID' : 0x106,
+ 'PM_CONFIG_SET_CONFIG_SECTION_ID' : 0x107,
+ 'PM_CONFIG_GPO_SECTION_ID' : 0x108,
+
+ 'PM_SLAVE_FLAG_IS_SHAREABLE' : 0x1,
+ 'PM_MASTER_USING_SLAVE_MASK' : 0x2,
+
+ 'PM_CONFIG_GPO1_MIO_PIN_34_MAP' : (1 << 10),
+ 'PM_CONFIG_GPO1_MIO_PIN_35_MAP' : (1 << 11),
+ 'PM_CONFIG_GPO1_MIO_PIN_36_MAP' : (1 << 12),
+ 'PM_CONFIG_GPO1_MIO_PIN_37_MAP' : (1 << 13),
+
+ 'PM_CONFIG_GPO1_BIT_2_MASK' : (1 << 2),
+ 'PM_CONFIG_GPO1_BIT_3_MASK' : (1 << 3),
+ 'PM_CONFIG_GPO1_BIT_4_MASK' : (1 << 4),
+ 'PM_CONFIG_GPO1_BIT_5_MASK' : (1 << 5),
+
+ 'SUSPEND_TIMEOUT' : 0xFFFFFFFF,
+
+ 'PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK' : 0x00000001,
+ 'PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK' : 0x00000100,
+ 'PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK' : 0x00000200,
+}
+
+in_file = open(args.in_file, mode='r')
+out_file = open(args.out_file, mode='wb')
+
+num_re = re.compile(r"^([0-9]+)U?$")
+const_re = re.compile(r"^([A-Z_][A-Z0-9_]*)$")
+
+def process_item(item):
+ logging.debug("* ITEM " + item)
+
+ value = 0
+ for item in item.split('|'):
+ item = item.strip()
+
+ num_match = num_re .match(item)
+ const_match = const_re.match(item)
+
+ if num_match:
+ num = int(num_match.group(1))
+ logging.debug(" - num " + str(num))
+ value |= num
+ elif const_match:
+ name = const_match.group(1)
+ if not name in pm_define:
+ sys.stderr.write("Unknown define " + name + "!\n")
+ exit(1)
+ num = pm_define[name]
+ logging.debug(" - def " + hex(num))
+ value |= num
+
+ logging.debug(" = res " + hex(value))
+ out_file.write(struct.pack('<L', value))
+
+
+# Read all code
+code = in_file.read()
+
+# remove comments
+code = re.sub('//.*?\n|/\*.*?\*/', '', code, flags=re.DOTALL)
+
+# remove everything outside the XPm_ConfigObject array definition
+code = re.search('const u32 XPm_ConfigObject.*= {\n(.*)};',
+ code, flags=re.DOTALL).group(1)
+
+# Process each comma-separated array item
+for item in code.split(','):
+ item = item.strip()
+ if item:
+ process_item(item)
+
+print("Wrote %d bytes" % out_file.tell())
diff --git a/tools/zynqmp_psu_init_minimize.sh b/tools/zynqmp_psu_init_minimize.sh
new file mode 100755
index 0000000..384bb56
--- /dev/null
+++ b/tools/zynqmp_psu_init_minimize.sh
@@ -0,0 +1,148 @@
+#!/bin/bash
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2018 Michal Simek <michal.simek@xilinx.com>
+# Copyright (C) 2019 Luca Ceresoli <luca@lucaceresoli.net>
+
+usage()
+{
+ cat <<EOF
+
+Transform a pair of psu_init_gpl.c and .h files produced by the Xilinx
+Vivado tool for ZynqMP into a smaller psu_init_gpl.c file that is almost
+checkpatch compliant. Minor coding style might still be needed. Must be
+run from the top-level U-Boot source directory.
+
+Usage: zynqmp_psu_init_minimize.sh INPUT_DIR OUTPUT_DIR
+Example: zynqmp_psu_init_minimize.sh \\
+ /path/to/original/psu_init_gpl_c_and_h/ \\
+ board/xilinx/zynqmp/<my_board>/
+
+Notes: INPUT_DIR must contain both .c and .h files.
+ If INPUT_DIR and OUTPUT_DIR are the same directory,
+ psu_init_gpl.c will be overwritten.
+
+EOF
+}
+
+set -o errexit -o errtrace
+set -o nounset
+
+if [ $# -ne 2 ]
+then
+ usage >&2
+ exit 1
+fi
+
+IN="${1}/psu_init_gpl.c"
+OUT="${2}/psu_init_gpl.c"
+TMP=$(mktemp /tmp/psu_init_gpl.XXXXXX)
+trap "rm ${TMP}" ERR
+
+# Step through a temp file to allow both $IN!=$OUT and $IN==$OUT
+sed -e '/sleep.h/d' \
+ -e '/xil_io.h/d' \
+ ${IN} >${TMP}
+cp ${TMP} ${OUT}
+
+# preprocess to expand defines, then remove cpp lines starting with '#'
+gcc -I${1} -E ${OUT} -o ${TMP}
+sed '/^#/d' ${TMP} >${OUT}
+
+# Remove trivial code before psu_pll_init_data()
+sed -ni '/psu_pll_init_data/,$p' ${OUT}
+
+# Functions are lowercase in U-Boot, rename them
+sed -i 's/PSU_Mask_Write/psu_mask_write/g' ${OUT}
+sed -i 's/mask_pollOnValue/mask_pollonvalue/g' ${OUT}
+sed -i 's/RegValue/regvalue/g' ${OUT}
+sed -i 's/MaskStatus/maskstatus/g' ${OUT}
+
+sed -i '/&= psu_peripherals_powerdwn_data()/d' ${OUT}
+
+FUNCS_TO_REMOVE="psu_protection
+psu_..._protection
+psu_init_xppu_aper_ram
+mask_delay(u32
+mask_read(u32
+dpll_prog
+mask_poll(u32
+mask_pollonvalue(u32
+psu_ps_pl_reset_config_data
+psu_ps_pl_isolation_removal_data
+psu_apply_master_tz
+psu_post_config_data
+psu_post_config_data
+psu_peripherals_powerdwn_data
+psu_init_ddr_self_refresh
+xmpu
+xppu
+"
+for i in $FUNCS_TO_REMOVE; do
+sed -i "/$i/,/^}$/d" ${OUT}
+done
+
+scripts/Lindent ${OUT}
+
+# Prepend 'static' to internal functions
+sed -i 's/^.*data(void)$/static &/g' ${OUT}
+sed -i 's/^.*psu_afi_config(void)$/static &/g' ${OUT}
+sed -i 's/^void init_peripheral/static &/g' ${OUT}
+sed -i 's/^int serdes/static &/g' ${OUT}
+sed -i 's/^int init_serdes/static &/g' ${OUT}
+sed -i 's/^unsigned long /static &/g' ${OUT}
+
+sed -i 's/()$/(void)/g' ${OUT}
+sed -i 's/0X/0x/g' ${OUT}
+
+# return (0) -> return 0
+sed -ri 's/return \(([0-9]+)\)/return \1/g' ${OUT}
+
+# Add header
+cat << EOF >${TMP}
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+EOF
+
+cat ${OUT} >>${TMP}
+cp ${TMP} ${OUT}
+
+# Temporarily convert newlines to do some mangling across lines
+tr "\n" "\r" <${OUT} >${TMP}
+
+# Cleanup empty loops. E.g.:
+# |while (e) {|
+# | | ==> |while (e)|
+# | } | | ; |
+# | |
+sed -i -r 's| \{\r+(\t*)\}\r\r|\n\1\t;\n|g' ${TMP}
+
+# Remove empty line between variable declaration
+sed -i -r 's|\r(\r\t(unsigned )?int )|\1|g' ${TMP}
+
+# Remove empty lines at function beginning/end
+sed -i -e 's|\r{\r\r|\r{\r|g' ${TMP}
+sed -i -e 's|\r\r}\r|\r}\r|g' ${TMP}
+
+# Remove empty lines after '{' line
+sed -i -e 's| {\r\r| {\r|g' ${TMP}
+
+# Remove braces {} around single statement blocks. E.g.:
+# | while (e) { | | while (e) |
+# | stg(); | => | stg();|
+# | } |
+sed -i -r 's| \{(\r[^\r]*;)\r\t*\}|\1|g' ${TMP}
+
+# Remove Unnecessary parentheses around 'n_code <= 0x3C' and similar. E.g.:
+# if ((p_code >= 0x26) && ...) -> if (p_code >= 0x26 && ...)
+sed -i -r 's|\((._code .= [x[:xdigit:]]+)\)|\1|g' ${TMP}
+
+# Convert back newlines
+tr "\r" "\n" <${TMP} >${OUT}
+
+rm ${TMP}