test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir

# RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s

--- |

  define i32 @test(i32 %a) {
  body:
    ret i32 %a
  }

...
---
name:            test
isSSA:           true
tracksRegLiveness: true
registers:
  - { id: 0, class: gr32 }
liveins:
  # CHECK: [[@LINE+1]]:13: expected a named register
  - { reg: '%0' }
body: |
  bb.0.body:
    liveins: %edi

    %0 = COPY %edi
    %eax = COPY %0
    RETQ %eax
...